From: P. Schakel <P251644@workspace.rug.nl>
Date: Thu, 13 Apr 2017 09:36:22 +0000 (+0200)
Subject: Latest version of SODA.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=c5c5814382b011bc78605013ca18328d1bcf5507;p=soda.git

Latest version of SODA.
Panda Data Concentrator on TRB3 and on Xilinx KC705 board running at 2Gb/s
Feature Extraction at Kintex 7 Front End ADC board
Feature Extraction on Virtex 6 (old version)
SODA source and SODA hub on TRB3 board
---

diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain.xdc b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain.xdc
new file mode 100644
index 0000000..72c2212
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain.xdc
@@ -0,0 +1,944 @@
+set_property DIFF_TERM TRUE [get_ports AD11A_N]
+set_property IOSTANDARD LVDS [get_ports AD11A_N]
+set_property DIFF_TERM TRUE [get_ports AD11A_P]
+set_property IOSTANDARD LVDS [get_ports AD11A_P]
+set_property PACKAGE_PIN AB8 [get_ports AD11A_P]
+set_property DIFF_TERM TRUE [get_ports AD21A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD21A_N]
+set_property DIFF_TERM TRUE [get_ports AD21A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD21A_P]
+set_property PACKAGE_PIN AA21 [get_ports AD21A_P]
+set_property DIFF_TERM TRUE [get_ports AD31A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD31A_N]
+set_property DIFF_TERM TRUE [get_ports AD31A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD31A_P]
+set_property PACKAGE_PIN P16 [get_ports AD31A_P]
+set_property DIFF_TERM TRUE [get_ports AD41A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD41A_N]
+set_property DIFF_TERM TRUE [get_ports AD41A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD41A_P]
+set_property PACKAGE_PIN B18 [get_ports AD41A_P]
+set_property DIFF_TERM TRUE [get_ports AD11B_N]
+set_property IOSTANDARD LVDS [get_ports AD11B_N]
+set_property DIFF_TERM TRUE [get_ports AD11B_P]
+set_property IOSTANDARD LVDS [get_ports AD11B_P]
+set_property PACKAGE_PIN AA6 [get_ports AD11B_P]
+set_property DIFF_TERM TRUE [get_ports AD21B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD21B_N]
+set_property DIFF_TERM TRUE [get_ports AD21B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD21B_P]
+set_property PACKAGE_PIN W17 [get_ports AD21B_P]
+set_property DIFF_TERM TRUE [get_ports AD31B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD31B_N]
+set_property DIFF_TERM TRUE [get_ports AD31B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD31B_P]
+set_property PACKAGE_PIN P21 [get_ports AD31B_P]
+set_property DIFF_TERM TRUE [get_ports AD41B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD41B_N]
+set_property DIFF_TERM TRUE [get_ports AD41B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD41B_P]
+set_property PACKAGE_PIN C19 [get_ports AD41B_P]
+set_property DIFF_TERM TRUE [get_ports AD12A_N]
+set_property IOSTANDARD LVDS [get_ports AD12A_N]
+set_property DIFF_TERM TRUE [get_ports AD12A_P]
+set_property IOSTANDARD LVDS [get_ports AD12A_P]
+set_property PACKAGE_PIN U7 [get_ports AD12A_P]
+set_property DIFF_TERM TRUE [get_ports AD22A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD22A_N]
+set_property DIFF_TERM TRUE [get_ports AD22A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD22A_P]
+set_property PACKAGE_PIN W16 [get_ports AD22A_P]
+set_property DIFF_TERM TRUE [get_ports AD32A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD32A_N]
+set_property DIFF_TERM TRUE [get_ports AD32A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD32A_P]
+set_property PACKAGE_PIN R18 [get_ports AD32A_P]
+set_property DIFF_TERM TRUE [get_ports AD42A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD42A_N]
+set_property DIFF_TERM TRUE [get_ports AD42A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD42A_P]
+set_property PACKAGE_PIN C22 [get_ports AD42A_P]
+set_property DIFF_TERM TRUE [get_ports AD12B_N]
+set_property IOSTANDARD LVDS [get_ports AD12B_N]
+set_property DIFF_TERM TRUE [get_ports AD12B_P]
+set_property IOSTANDARD LVDS [get_ports AD12B_P]
+set_property PACKAGE_PIN AA5 [get_ports AD12B_P]
+set_property DIFF_TERM TRUE [get_ports AD22B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD22B_N]
+set_property DIFF_TERM TRUE [get_ports AD22B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD22B_P]
+set_property PACKAGE_PIN AA16 [get_ports AD22B_P]
+set_property DIFF_TERM TRUE [get_ports AD32B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD32B_N]
+set_property DIFF_TERM TRUE [get_ports AD32B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD32B_P]
+set_property PACKAGE_PIN R21 [get_ports AD32B_P]
+set_property DIFF_TERM TRUE [get_ports AD42B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD42B_N]
+set_property DIFF_TERM TRUE [get_ports AD42B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD42B_P]
+set_property PACKAGE_PIN A20 [get_ports AD42B_P]
+set_property DIFF_TERM TRUE [get_ports AD13A_N]
+set_property IOSTANDARD LVDS [get_ports AD13A_N]
+set_property DIFF_TERM TRUE [get_ports AD13A_P]
+set_property IOSTANDARD LVDS [get_ports AD13A_P]
+set_property PACKAGE_PIN V7 [get_ports AD13A_P]
+set_property DIFF_TERM TRUE [get_ports AD23A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD23A_N]
+set_property DIFF_TERM TRUE [get_ports AD23A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD23A_P]
+set_property PACKAGE_PIN AB15 [get_ports AD23A_P]
+set_property DIFF_TERM TRUE [get_ports AD33A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD33A_N]
+set_property DIFF_TERM TRUE [get_ports AD33A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD33A_P]
+set_property PACKAGE_PIN R17 [get_ports AD33A_P]
+set_property DIFF_TERM TRUE [get_ports AD43A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD43A_N]
+set_property DIFF_TERM TRUE [get_ports AD43A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD43A_P]
+set_property PACKAGE_PIN B20 [get_ports AD43A_P]
+set_property DIFF_TERM TRUE [get_ports AD13B_N]
+set_property IOSTANDARD LVDS [get_ports AD13B_N]
+set_property DIFF_TERM TRUE [get_ports AD13B_P]
+set_property IOSTANDARD LVDS [get_ports AD13B_P]
+set_property PACKAGE_PIN AA9 [get_ports AD13B_P]
+set_property DIFF_TERM TRUE [get_ports AD23B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD23B_N]
+set_property DIFF_TERM TRUE [get_ports AD23B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD23B_P]
+set_property PACKAGE_PIN U17 [get_ports AD23B_P]
+set_property DIFF_TERM TRUE [get_ports AD33B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD33B_N]
+set_property DIFF_TERM TRUE [get_ports AD33B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD33B_P]
+set_property PACKAGE_PIN N22 [get_ports AD33B_P]
+set_property DIFF_TERM TRUE [get_ports AD43B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD43B_N]
+set_property DIFF_TERM TRUE [get_ports AD43B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD43B_P]
+set_property PACKAGE_PIN B17 [get_ports AD43B_P]
+set_property DIFF_TERM TRUE [get_ports AD14A_N]
+set_property IOSTANDARD LVDS [get_ports AD14A_N]
+set_property DIFF_TERM TRUE [get_ports AD14A_P]
+set_property IOSTANDARD LVDS [get_ports AD14A_P]
+set_property PACKAGE_PIN W6 [get_ports AD14A_P]
+set_property DIFF_TERM TRUE [get_ports AD24A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD24A_N]
+set_property DIFF_TERM TRUE [get_ports AD24A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD24A_P]
+set_property PACKAGE_PIN AA14 [get_ports AD24A_P]
+set_property DIFF_TERM TRUE [get_ports AD34A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD34A_N]
+set_property DIFF_TERM TRUE [get_ports AD34A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD34A_P]
+set_property PACKAGE_PIN P19 [get_ports AD34A_P]
+set_property DIFF_TERM TRUE [get_ports AD44A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD44A_N]
+set_property DIFF_TERM TRUE [get_ports AD44A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD44A_P]
+set_property PACKAGE_PIN D21 [get_ports AD44A_P]
+set_property DIFF_TERM TRUE [get_ports AD14B_N]
+set_property IOSTANDARD LVDS [get_ports AD14B_N]
+set_property DIFF_TERM TRUE [get_ports AD14B_P]
+set_property IOSTANDARD LVDS [get_ports AD14B_P]
+set_property PACKAGE_PIN U8 [get_ports AD14B_P]
+set_property DIFF_TERM TRUE [get_ports AD24B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD24B_N]
+set_property DIFF_TERM TRUE [get_ports AD24B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD24B_P]
+set_property PACKAGE_PIN AA20 [get_ports AD24B_P]
+set_property DIFF_TERM TRUE [get_ports AD34B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD34B_N]
+set_property DIFF_TERM TRUE [get_ports AD34B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD34B_P]
+set_property PACKAGE_PIN K21 [get_ports AD34B_P]
+set_property DIFF_TERM TRUE [get_ports AD44B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD44B_N]
+set_property DIFF_TERM TRUE [get_ports AD44B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD44B_P]
+set_property PACKAGE_PIN D19 [get_ports AD44B_P]
+set_property DIFF_TERM TRUE [get_ports AD15A_N]
+set_property IOSTANDARD LVDS [get_ports AD15A_N]
+set_property DIFF_TERM TRUE [get_ports AD15A_P]
+set_property IOSTANDARD LVDS [get_ports AD15A_P]
+set_property PACKAGE_PIN V10 [get_ports AD15A_P]
+set_property DIFF_TERM TRUE [get_ports AD25A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD25A_N]
+set_property DIFF_TERM TRUE [get_ports AD25A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD25A_P]
+set_property PACKAGE_PIN W21 [get_ports AD25A_P]
+set_property DIFF_TERM TRUE [get_ports AD35A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD35A_N]
+set_property DIFF_TERM TRUE [get_ports AD35A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD35A_P]
+set_property PACKAGE_PIN M20 [get_ports AD35A_P]
+set_property DIFF_TERM TRUE [get_ports AD45A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD45A_N]
+set_property DIFF_TERM TRUE [get_ports AD45A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD45A_P]
+set_property PACKAGE_PIN B15 [get_ports AD45A_P]
+set_property DIFF_TERM TRUE [get_ports AD15B_N]
+set_property IOSTANDARD LVDS [get_ports AD15B_N]
+set_property DIFF_TERM TRUE [get_ports AD15B_P]
+set_property IOSTANDARD LVDS [get_ports AD15B_P]
+set_property PACKAGE_PIN W11 [get_ports AD15B_P]
+set_property DIFF_TERM TRUE [get_ports AD25B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD25B_N]
+set_property DIFF_TERM TRUE [get_ports AD25B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD25B_P]
+set_property PACKAGE_PIN V20 [get_ports AD25B_P]
+set_property DIFF_TERM TRUE [get_ports AD35B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD35B_N]
+set_property DIFF_TERM TRUE [get_ports AD35B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD35B_P]
+set_property PACKAGE_PIN M17 [get_ports AD35B_P]
+set_property DIFF_TERM TRUE [get_ports AD45B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD45B_N]
+set_property DIFF_TERM TRUE [get_ports AD45B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD45B_P]
+set_property PACKAGE_PIN C14 [get_ports AD45B_P]
+set_property DIFF_TERM TRUE [get_ports AD16A_N]
+set_property IOSTANDARD LVDS [get_ports AD16A_N]
+set_property DIFF_TERM TRUE [get_ports AD16A_P]
+set_property IOSTANDARD LVDS [get_ports AD16A_P]
+set_property PACKAGE_PIN AA11 [get_ports AD16A_P]
+set_property DIFF_TERM TRUE [get_ports AD26A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD26A_N]
+set_property DIFF_TERM TRUE [get_ports AD26A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD26A_P]
+set_property PACKAGE_PIN Y21 [get_ports AD26A_P]
+set_property DIFF_TERM TRUE [get_ports AD36A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD36A_N]
+set_property DIFF_TERM TRUE [get_ports AD36A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD36A_P]
+set_property PACKAGE_PIN H22 [get_ports AD36A_P]
+set_property DIFF_TERM TRUE [get_ports AD46A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD46A_N]
+set_property DIFF_TERM TRUE [get_ports AD46A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD46A_P]
+set_property PACKAGE_PIN D15 [get_ports AD46A_P]
+set_property DIFF_TERM TRUE [get_ports AD16B_N]
+set_property IOSTANDARD LVDS [get_ports AD16B_N]
+set_property DIFF_TERM TRUE [get_ports AD16B_P]
+set_property IOSTANDARD LVDS [get_ports AD16B_P]
+set_property PACKAGE_PIN AB13 [get_ports AD16B_P]
+set_property DIFF_TERM TRUE [get_ports AD26B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD26B_N]
+set_property DIFF_TERM TRUE [get_ports AD26B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD26B_P]
+set_property PACKAGE_PIN U16 [get_ports AD26B_P]
+set_property DIFF_TERM TRUE [get_ports AD36B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD36B_N]
+set_property DIFF_TERM TRUE [get_ports AD36B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD36B_P]
+set_property PACKAGE_PIN J20 [get_ports AD36B_P]
+set_property DIFF_TERM TRUE [get_ports AD46B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD46B_N]
+set_property DIFF_TERM TRUE [get_ports AD46B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD46B_P]
+set_property PACKAGE_PIN F15 [get_ports AD46B_P]
+set_property DIFF_TERM TRUE [get_ports AD17A_N]
+set_property IOSTANDARD LVDS [get_ports AD17A_N]
+set_property DIFF_TERM TRUE [get_ports AD17A_P]
+set_property IOSTANDARD LVDS [get_ports AD17A_P]
+set_property PACKAGE_PIN V13 [get_ports AD17A_P]
+set_property DIFF_TERM TRUE [get_ports AD27A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD27A_N]
+set_property DIFF_TERM TRUE [get_ports AD27A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD27A_P]
+set_property PACKAGE_PIN T21 [get_ports AD27A_P]
+set_property DIFF_TERM TRUE [get_ports AD37A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD37A_N]
+set_property DIFF_TERM TRUE [get_ports AD37A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD37A_P]
+set_property PACKAGE_PIN G20 [get_ports AD37A_P]
+set_property DIFF_TERM TRUE [get_ports AD47A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD47A_N]
+set_property DIFF_TERM TRUE [get_ports AD47A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD47A_P]
+set_property PACKAGE_PIN C13 [get_ports AD47A_P]
+set_property DIFF_TERM TRUE [get_ports AD17B_N]
+set_property IOSTANDARD LVDS [get_ports AD17B_N]
+set_property DIFF_TERM TRUE [get_ports AD17B_P]
+set_property IOSTANDARD LVDS [get_ports AD17B_P]
+set_property PACKAGE_PIN T13 [get_ports AD17B_P]
+set_property DIFF_TERM TRUE [get_ports AD27B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD27B_N]
+set_property DIFF_TERM TRUE [get_ports AD27B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD27B_P]
+set_property PACKAGE_PIN T18 [get_ports AD27B_P]
+set_property DIFF_TERM TRUE [get_ports AD37B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD37B_N]
+set_property DIFF_TERM TRUE [get_ports AD37B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD37B_P]
+set_property PACKAGE_PIN G21 [get_ports AD37B_P]
+set_property DIFF_TERM TRUE [get_ports AD47B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD47B_N]
+set_property DIFF_TERM TRUE [get_ports AD47B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD47B_P]
+set_property PACKAGE_PIN C12 [get_ports AD47B_P]
+set_property DIFF_TERM TRUE [get_ports AD18A_N]
+set_property IOSTANDARD LVDS [get_ports AD18A_N]
+set_property DIFF_TERM TRUE [get_ports AD18A_P]
+set_property IOSTANDARD LVDS [get_ports AD18A_P]
+set_property PACKAGE_PIN W12 [get_ports AD18A_P]
+set_property DIFF_TERM TRUE [get_ports AD28A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD28A_N]
+set_property DIFF_TERM TRUE [get_ports AD28A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD28A_P]
+set_property PACKAGE_PIN U22 [get_ports AD28A_P]
+set_property DIFF_TERM TRUE [get_ports AD38A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD38A_N]
+set_property DIFF_TERM TRUE [get_ports AD38A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD38A_P]
+set_property PACKAGE_PIN L18 [get_ports AD38A_P]
+set_property DIFF_TERM TRUE [get_ports AD48A_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD48A_N]
+set_property DIFF_TERM TRUE [get_ports AD48A_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD48A_P]
+set_property PACKAGE_PIN A13 [get_ports AD48A_P]
+set_property DIFF_TERM TRUE [get_ports AD18B_N]
+set_property IOSTANDARD LVDS [get_ports AD18B_N]
+set_property DIFF_TERM TRUE [get_ports AD18B_P]
+set_property IOSTANDARD LVDS [get_ports AD18B_P]
+set_property PACKAGE_PIN Y13 [get_ports AD18B_P]
+set_property DIFF_TERM TRUE [get_ports AD28B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD28B_N]
+set_property DIFF_TERM TRUE [get_ports AD28B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD28B_P]
+set_property PACKAGE_PIN T20 [get_ports AD28B_P]
+set_property DIFF_TERM TRUE [get_ports AD38B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD38B_N]
+set_property DIFF_TERM TRUE [get_ports AD38B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD38B_P]
+set_property PACKAGE_PIN E21 [get_ports AD38B_P]
+set_property DIFF_TERM TRUE [get_ports AD48B_N]
+set_property IOSTANDARD LVDS_25 [get_ports AD48B_N]
+set_property DIFF_TERM TRUE [get_ports AD48B_P]
+set_property IOSTANDARD LVDS_25 [get_ports AD48B_P]
+set_property PACKAGE_PIN E14 [get_ports AD48B_P]
+set_property DIFF_TERM TRUE [get_ports DCOA1_N]
+set_property IOSTANDARD LVDS [get_ports DCOA1_N]
+set_property DIFF_TERM TRUE [get_ports DCOA1_P]
+set_property IOSTANDARD LVDS [get_ports DCOA1_P]
+set_property LOC ILOGIC_X1Y74 [get_cells FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X1Y5 [get_cells FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X1Y74 [get_cells FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN W9 [get_ports DCOA1_P]
+set_property DIFF_TERM TRUE [get_ports DCOB1_N]
+set_property IOSTANDARD LVDS [get_ports DCOB1_N]
+set_property DIFF_TERM TRUE [get_ports DCOB1_P]
+set_property IOSTANDARD LVDS [get_ports DCOB1_P]
+set_property LOC ILOGIC_X1Y76 [get_cells FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X1Y6 [get_cells FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X1Y76 [get_cells FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN Y8 [get_ports DCOB1_P]
+set_property DIFF_TERM TRUE [get_ports FRA1_N]
+set_property IOSTANDARD LVDS [get_ports FRA1_N]
+set_property DIFF_TERM TRUE [get_ports FRA1_P]
+set_property IOSTANDARD LVDS [get_ports FRA1_P]
+set_property PACKAGE_PIN U10 [get_ports FRA1_P]
+set_property DIFF_TERM TRUE [get_ports FRB1_N]
+set_property IOSTANDARD LVDS [get_ports FRB1_N]
+set_property DIFF_TERM TRUE [get_ports FRB1_P]
+set_property IOSTANDARD LVDS [get_ports FRB1_P]
+set_property PACKAGE_PIN AA10 [get_ports FRB1_P]
+set_property DIFF_TERM TRUE [get_ports DCOA2_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA2_N]
+set_property DIFF_TERM TRUE [get_ports DCOA2_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA2_P]
+set_property LOC ILOGIC_X0Y76 [get_cells FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y6 [get_cells FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y76 [get_cells FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN V19 [get_ports DCOA2_P]
+set_property DIFF_TERM TRUE [get_ports DCOB2_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB2_N]
+set_property DIFF_TERM TRUE [get_ports DCOB2_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB2_P]
+set_property LOC ILOGIC_X0Y74 [get_cells FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y5 [get_cells FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y74 [get_cells FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN Y18 [get_ports DCOB2_P]
+set_property DIFF_TERM TRUE [get_ports FRA2_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRA2_N]
+set_property DIFF_TERM TRUE [get_ports FRA2_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRA2_P]
+set_property PACKAGE_PIN AA18 [get_ports FRA2_P]
+set_property DIFF_TERM TRUE [get_ports FRB2_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRB2_N]
+set_property DIFF_TERM TRUE [get_ports FRB2_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRB2_P]
+set_property PACKAGE_PIN AA19 [get_ports FRB2_P]
+set_property DIFF_TERM TRUE [get_ports DCOA3_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA3_N]
+set_property DIFF_TERM TRUE [get_ports DCOA3_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA3_P]
+set_property LOC ILOGIC_X0Y126 [get_cells FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y10 [get_cells FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y126 [get_cells FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN L19 [get_ports DCOA3_P]
+set_property DIFF_TERM TRUE [get_ports DCOB3_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB3_N]
+set_property DIFF_TERM TRUE [get_ports DCOB3_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB3_P]
+set_property LOC ILOGIC_X0Y124 [get_cells FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y9 [get_cells FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y124 [get_cells FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN N18 [get_ports DCOB3_P]
+set_property DIFF_TERM TRUE [get_ports FRA3_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRA3_N]
+set_property DIFF_TERM TRUE [get_ports FRA3_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRA3_P]
+set_property PACKAGE_PIN N20 [get_ports FRA3_P]
+set_property DIFF_TERM TRUE [get_ports FRB3_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRB3_N]
+set_property DIFF_TERM TRUE [get_ports FRB3_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRB3_P]
+set_property PACKAGE_PIN J21 [get_ports FRB3_P]
+set_property DIFF_TERM TRUE [get_ports DCOA4_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA4_N]
+set_property DIFF_TERM TRUE [get_ports DCOA4_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOA4_P]
+set_property LOC ILOGIC_X0Y176 [get_cells FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y14 [get_cells FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y176 [get_cells FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN C17 [get_ports DCOA4_P]
+set_property DIFF_TERM TRUE [get_ports DCOB4_N]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB4_N]
+set_property DIFF_TERM TRUE [get_ports DCOB4_P]
+set_property IOSTANDARD LVDS_25 [get_ports DCOB4_P]
+set_property LOC ILOGIC_X0Y174 [get_cells FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_Master]
+set_property LOC BUFIO_X0Y13 [get_cells FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio]
+set_property LOC IDELAY_X0Y174 [get_cells FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Iodly]
+set_property PACKAGE_PIN E17 [get_ports DCOB4_P]
+set_property DIFF_TERM TRUE [get_ports FRA4_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRA4_N]
+set_property DIFF_TERM TRUE [get_ports FRA4_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRA4_P]
+set_property PACKAGE_PIN B16 [get_ports FRA4_P]
+set_property DIFF_TERM TRUE [get_ports FRB4_N]
+set_property IOSTANDARD LVDS_25 [get_ports FRB4_N]
+set_property DIFF_TERM TRUE [get_ports FRB4_P]
+set_property IOSTANDARD LVDS_25 [get_ports FRB4_P]
+set_property PACKAGE_PIN E16 [get_ports FRB4_P]
+
+set_property PACKAGE_PIN W15 [get_ports {CSA[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSA[1]}]
+set_property PACKAGE_PIN V15 [get_ports {CSB[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSB[1]}]
+set_property PACKAGE_PIN U12 [get_ports SCK]
+set_property IOSTANDARD LVCMOS18 [get_ports SCK]
+set_property PACKAGE_PIN U11 [get_ports SDI]
+set_property IOSTANDARD LVCMOS18 [get_ports SDI]
+set_property PACKAGE_PIN W14 [get_ports {SDOA[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[1]}]
+set_property PACKAGE_PIN Y14 [get_ports {SDOB[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[1]}]
+set_property PACKAGE_PIN T16 [get_ports {CSA[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSA[2]}]
+set_property PACKAGE_PIN R16 [get_ports {CSB[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSB[2]}]
+set_property PACKAGE_PIN T15 [get_ports {SDOA[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[2]}]
+set_property PACKAGE_PIN U15 [get_ports {SDOB[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[2]}]
+set_property PACKAGE_PIN H17 [get_ports {CSA[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSA[3]}]
+set_property PACKAGE_PIN G17 [get_ports {CSB[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSB[3]}]
+set_property PACKAGE_PIN J16 [get_ports {SDOA[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[3]}]
+set_property PACKAGE_PIN J17 [get_ports {SDOB[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[3]}]
+set_property PACKAGE_PIN F18 [get_ports {CSA[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSA[4]}]
+set_property PACKAGE_PIN E19 [get_ports {CSB[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {CSB[4]}]
+set_property PACKAGE_PIN G15 [get_ports {SDOA[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOA[4]}]
+set_property PACKAGE_PIN G16 [get_ports {SDOB[4]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {SDOB[4]}]
+
+set_property PACKAGE_PIN K17 [get_ports GEO]
+set_property IOSTANDARD LVCMOS25 [get_ports GEO]
+set_property SLEW SLOW [get_ports GEO]
+set_property PULLUP true [get_ports GEO]
+
+#Bank 16 = 2.5V
+set_property PACKAGE_PIN H12 [get_ports SYS_CLK]
+set_property IOSTANDARD LVCMOS25 [get_ports SYS_CLK]
+
+set_property PACKAGE_PIN D11 [get_ports INTCOMC1_N]
+set_property PACKAGE_PIN E11 [get_ports INTCOMC1_P]
+set_property PACKAGE_PIN G10 [get_ports INTCOMC2_N]
+set_property PACKAGE_PIN G11 [get_ports INTCOMC2_P]
+set_property PACKAGE_PIN E9 [get_ports INTCOM0_N]
+set_property PACKAGE_PIN F9 [get_ports INTCOM0_P]
+set_property PACKAGE_PIN H8 [get_ports INTCOM1_N]
+set_property PACKAGE_PIN H9 [get_ports INTCOM1_P]
+set_property PACKAGE_PIN F8 [get_ports INTCOM2_N]
+set_property PACKAGE_PIN G8 [get_ports INTCOM2_P]
+set_property PACKAGE_PIN C9 [get_ports INTCOM3_N]
+set_property PACKAGE_PIN D9 [get_ports INTCOM3_P]
+set_property PACKAGE_PIN B10 [get_ports INTCOM4_N]
+set_property PACKAGE_PIN B11 [get_ports INTCOM4_P]
+set_property PACKAGE_PIN A8 [get_ports INTCOM5_N]
+set_property PACKAGE_PIN A9 [get_ports INTCOM5_P]
+set_property PACKAGE_PIN B8 [get_ports INTCOM6_N]
+set_property PACKAGE_PIN C8 [get_ports INTCOM6_P]
+set_property PACKAGE_PIN A10 [get_ports INTCOM7_N]
+set_property PACKAGE_PIN A11 [get_ports INTCOM7_P]
+
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC1_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC1_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC2_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOMC2_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM0_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM0_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM1_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM1_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM2_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM2_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM3_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM3_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM4_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM4_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM5_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM5_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM6_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM6_P]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM7_N]
+set_property IOSTANDARD LVCMOS25 [get_ports INTCOM7_P]
+
+set_property PACKAGE_PIN F10 [get_ports RCV_CLK_N]
+set_property DIFF_TERM TRUE [get_ports RCV_CLK_N]
+set_property IOSTANDARD LVDS_25 [get_ports RCV_CLK_N]
+set_property PACKAGE_PIN F11 [get_ports RCV_CLK_P]
+set_property DIFF_TERM TRUE [get_ports RCV_CLK_P]
+set_property IOSTANDARD LVDS_25 [get_ports RCV_CLK_P]
+
+set_property PACKAGE_PIN E12 [get_ports S_CTRL]
+set_property IOSTANDARD LVCMOS25 [get_ports S_CTRL]
+set_property PACKAGE_PIN E13 [get_ports T_CTRL]
+set_property IOSTANDARD LVCMOS25 [get_ports T_CTRL]
+
+#bank 34: 3.3V
+set_property PACKAGE_PIN W5 [get_ports SYNC]
+set_property IOSTANDARD LVCMOS18 [get_ports SYNC]
+set_property PACKAGE_PIN AA4 [get_ports CLKu]
+set_property IOSTANDARD LVCMOS18 [get_ports CLKu]
+set_property PACKAGE_PIN AA3 [get_ports DATAu]
+set_property IOSTANDARD LVCMOS18 [get_ports DATAu]
+set_property PACKAGE_PIN Y4 [get_ports LEu]
+set_property IOSTANDARD LVCMOS18 [get_ports LEu]
+set_property PACKAGE_PIN AB3 [get_ports RDu]
+set_property IOSTANDARD LVCMOS18 [get_ports RDu]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets RDu]
+
+set_property IOSTANDARD LVCMOS18 [get_ports ST_CLK_N]
+set_property PACKAGE_PIN T4 [get_ports ST_CLK_P]
+set_property PACKAGE_PIN U3 [get_ports ST_CLK_N]
+set_property IOSTANDARD LVCMOS18 [get_ports ST_CLK_P]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ST_CLK_N]
+
+set_property PACKAGE_PIN R3 [get_ports GCLK_P]
+set_property PACKAGE_PIN T3 [get_ports GCLK_N]
+set_property IOSTANDARD LVDS [get_ports GCLK_P]
+set_property IOSTANDARD LVDS [get_ports GCLK_N]
+#//set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets GCLK_N]
+
+set_property PACKAGE_PIN D6 [get_ports MGTREFCLK_P]
+set_property PACKAGE_PIN D5 [get_ports MGTREFCLK_N]
+
+set_property PACKAGE_PIN G3 [get_ports RX_N]
+set_property PACKAGE_PIN G4 [get_ports RX_P]
+set_property PACKAGE_PIN F1 [get_ports TX_N]
+set_property PACKAGE_PIN F2 [get_ports TX_P]
+set_property PACKAGE_PIN K1 [get_ports LOS]
+set_property IOSTANDARD LVCMOS18 [get_ports LOS]
+set_property PACKAGE_PIN L1 [get_ports TX_DIS]
+set_property IOSTANDARD LVCMOS18 [get_ports TX_DIS]
+
+set_property PACKAGE_PIN M2 [get_ports {MOD_DEF[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MOD_DEF[0]}]
+set_property PACKAGE_PIN M1 [get_ports {MOD_DEF[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MOD_DEF[1]}]
+set_property PACKAGE_PIN K3 [get_ports {MOD_DEF[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MOD_DEF[2]}]
+
+set_property PACKAGE_PIN T10 [get_ports TEMP_OUT]
+set_property IOSTANDARD LVCMOS18 [get_ports TEMP_OUT]
+set_property PACKAGE_PIN T11 [get_ports TEMP_IN]
+set_property IOSTANDARD LVCMOS18 [get_ports TEMP_IN]
+
+set_property PACKAGE_PIN Y1 [get_ports MON1_N]
+set_property IOSTANDARD LVCMOS18 [get_ports MON1_N]
+#set_property IOSTANDARD LVDS [get_ports MON1_N]
+set_property PACKAGE_PIN W1 [get_ports MON1_P]
+#set_property IOSTANDARD LVCMOS18 [get_ports MON1_P]
+set_property IOSTANDARD LVDS [get_ports MON1_P]
+
+set_property PACKAGE_PIN Y2 [get_ports MON2_N]
+#set_property IOSTANDARD LVCMOS18 [get_ports MON2_N]
+set_property IOSTANDARD LVDS [get_ports MON2_N]
+set_property PACKAGE_PIN Y3 [get_ports MON2_P]
+#set_property IOSTANDARD LVCMOS18 [get_ports MON2_P]
+set_property IOSTANDARD LVDS [get_ports MON2_P]
+
+set_property PACKAGE_PIN G13 [get_ports JTAG_OUT1_TCK_F]
+set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TCK_F]
+set_property PACKAGE_PIN H14 [get_ports JTAG_OUT1_TDI_F]
+set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TDI_F]
+set_property PACKAGE_PIN H13 [get_ports JTAG_OUT1_TDO_F]
+set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TDO_F]
+set_property PACKAGE_PIN F13 [get_ports JTAG_OUT1_TMS_F]
+set_property IOSTANDARD LVCMOS25 [get_ports JTAG_OUT1_TMS_F]
+
+set_property PACKAGE_PIN D1 [get_ports GT_A2B_0_N]
+set_property PACKAGE_PIN D2 [get_ports GT_A2B_0_P]
+set_property PACKAGE_PIN B1 [get_ports GT_A2B_1_N]
+set_property PACKAGE_PIN B2 [get_ports GT_A2B_1_P]
+set_property PACKAGE_PIN E3 [get_ports GT_B2A_0_N]
+set_property PACKAGE_PIN E4 [get_ports GT_B2A_0_P]
+set_property PACKAGE_PIN C3 [get_ports GT_B2A_1_N]
+set_property PACKAGE_PIN C4 [get_ports GT_B2A_1_P]
+
+#NET "DONE_P1" LOC = P6;
+#NET "CF_D0_I1" LOC = H18;
+#NET "CF_D1_I1" LOC = H19;
+#NET "CF_D2_I1" LOC = G18;
+#NET "CF_D3_I1" LOC = F19;
+#NET "CF_EMCL_I1" LOC = H12;
+#NET "CF_EMCL_I1" LOC = J19;
+#NET "CF_FCS_I1" LOC = L16;
+#NET "CF_PUDC_I1" LOC = K18;
+#NET "CCLK1_P1" LOC = G7;
+#NET "JTAG_IN1_TCK" LOC = K7;
+#NET "JTAG_IN1_TDI" LOC = K6;
+#NET "JTAG_IN1_TDO" LOC = J6;
+#NET "JTAG_IN1_TMS" LOC = L6;
+
+
+##########################################################################################
+# done inside clockmodule100Mto80M # create_clock -period 10.000 -name SYS_CLK [get_ports SYS_CLK]
+create_clock -period 6.430 -name ST_CLK_N [get_ports ST_CLK_N]
+
+
+
+
+
+create_pblock pblock_adc_1
+add_cells_to_pblock [get_pblocks pblock_adc_1] [get_cells {FEE_ADCinput_module1/AdcToplevel2356_1/* FEE_ADCinput_module1/AdcToplevel1458_1/*}]
+add_cells_to_pblock [get_pblocks pblock_adc_1] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_1 FEE_ADCinput_module1/AdcToplevel2356_1}]
+resize_pblock [get_pblocks pblock_adc_1] -add {SLICE_X106Y50:SLICE_X109Y99}
+#add_cells_to_pblock [get_pblocks pblock_adc_1] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel2356_1 FEE_ADCinput_module1/AdcToplevel1458_1]]
+create_pblock pblock_adc_2
+add_cells_to_pblock [get_pblocks pblock_adc_2] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_2/* FEE_ADCinput_module1/AdcToplevel2356_2/*}]
+add_cells_to_pblock [get_pblocks pblock_adc_2] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_2 FEE_ADCinput_module1/AdcToplevel2356_2}]
+resize_pblock [get_pblocks pblock_adc_2] -add {SLICE_X0Y50:SLICE_X3Y99}
+#add_cells_to_pblock [get_pblocks pblock_adc_2] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel1458_2 FEE_ADCinput_module1/AdcToplevel2356_2]]
+create_pblock pblock_adc_3
+add_cells_to_pblock [get_pblocks pblock_adc_3] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_3/* FEE_ADCinput_module1/AdcToplevel2356_3/*}]
+add_cells_to_pblock [get_pblocks pblock_adc_3] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_3 FEE_ADCinput_module1/AdcToplevel2356_3}]
+resize_pblock [get_pblocks pblock_adc_3] -add {SLICE_X0Y100:SLICE_X3Y149}
+#add_cells_to_pblock [get_pblocks pblock_adc_3] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel1458_3 FEE_ADCinput_module1/AdcToplevel2356_3]]
+create_pblock pblock_adc_4
+add_cells_to_pblock [get_pblocks pblock_adc_4] [get_cells {FEE_ADCinput_module1/AdcToplevel2356_4/* FEE_ADCinput_module1/AdcToplevel1458_4/*}]
+add_cells_to_pblock [get_pblocks pblock_adc_4] [get_cells {FEE_ADCinput_module1/AdcToplevel1458_4 FEE_ADCinput_module1/AdcToplevel2356_4}]
+resize_pblock [get_pblocks pblock_adc_4] -add {SLICE_X0Y151:SLICE_X3Y199}
+#add_cells_to_pblock [get_pblocks pblock_adc_4] [get_cells -quiet [list FEE_ADCinput_module1/AdcToplevel2356_4 FEE_ADCinput_module1/AdcToplevel1458_4]]
+
+#############################################################################################
+# Timing constraints
+#############################################################################################
+# The DCLK input clock, bit clock from the ADC, doesn't need a timespec.
+# This clock passes from the IOB through the BUFIO and to the .CLK input of all used ISERDES.
+# This path is made from dedicated routing.
+#   From the IOB to theBUFIO.I is a dedicated connection only availabel with Clock Capable_IO.
+#   This connection takes for all IO-banks in a FPGA and from all FPGAs of the familly an
+#   average value of 220 ps.
+#   The connection from the BUFIO.O to all ISERDES.CLK is also a dedicated connection, it
+#   takes on average 330 ps.
+#   The BUFIO average delay is: 869 ps and an LVDS IOB is average: 1094 ps.
+# A MAXSKEW constraint is used to detect the skew on the CLK net.
+
+#
+# The connection from the BUFR.O to the ISERDES.CLKDIV inputs runs over normal clock nets.
+#   Oposite to the BUFIO.O - ISERDES.CLK routing, the BUFR.O net not only connects to the
+#   ISERDES.CLKDIV pins of the I/O SERDES in the IO-bank the BUFR is located in but to all
+#   clocked elements (FFs, BRAM, DSP, ..) in that clock area.
+#   It also connects to the adjacent upper and lower clock areas.
+#   Therefore it is necessary to put timing constraints on this clock.
+# A MAXSKEW constraint to keep the skew as low as possible. makes sure the ISERDES are clocked
+# at the same time so that early-late data cannot appear at the outputs of the ISERDES.
+
+
+set_false_path -through [get_nets GEO]
+set_false_path -through [get_ports GEO]
+set_false_path -from [get_ports GEO]
+set_false_path -from [get_ports S_CTRL]
+set_false_path -to [get_ports T_CTRL]
+
+create_clock -period 12.500 -name ADC_clk_S [get_pins FEE_ADCinput_module1/ADCclkbuf/O]
+
+#//create_generated_clock -name clock40MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clock40MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clock_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT1]
+#//create_generated_clock -name clock100MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT2]
+create_generated_clock -name clock200MHz_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT3]
+create_generated_clock -name async_clock_S [get_pins clockmodule100Mto80Ma/inst/mmcm_adv_inst/CLKOUT4]
+#create_generated_clock -name rxSodaClk80_S [get_pins clockmodule40Mto80M1/inst/mmcm_adv_inst/CLKOUT1]
+#create_generated_clock -name rxSodaClk40_S [get_pins FEE_gtxModule1/FEE_SODAfrequencydiv51/clockdiv5buf/O]
+#create_generated_clock -name rxSodaClk_S [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/FEE_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT1]
+#create_generated_clock -name RXOUTCLK [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/gtx_i/gtxKintex7FEE80_init_i/U0/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i/RXOUTCLK]
+
+create_clock -name aurora_clock -period 10.000 [get_pins gen_combine.aurora_dual_module1/aurora_module_i/clock_module_i/user_clk_buf_i/I]
+#create_generated_clock -name aurora_clock [get_pins gen_combine.aurora_dual_module1/aurora_module_i/aurora_dual_i/U0/gt_wrapper_i/aurora_dual_multi_gt_i/gt0_aurora_dual_i/gtxe2_i/TXOUTCLK
+
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
+
+
+
+################################# GTX #####################
+#NET "MGTREFCLK_P" TNM_NET = "MGTREFCLK_P";
+#TIMESPEC TS_MGTREFCLK_P = PERIOD "MGTREFCLK_P" 8 ns HIGH 50 %;
+#NET "MGTREFCLK_N" TNM_NET = "MGTREFCLK_N";
+#TIMESPEC TS_MGTREFCLK_N = PERIOD "MGTREFCLK_N" 8 ns HIGH 50 %;
+create_clock -period 12.500 -name GCLK_P [get_ports GCLK_P]
+#create_clock -period 12.500 -name GCLK_N [get_ports GCLK_N]
+create_clock -period 12.500 [get_ports MGTREFCLK_P]
+#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
+#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
+#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}]
+##---------- Set placement for gt0_gtx_wrapper_i/GTXE2_CHANNEL ------
+#set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells gtxKintex7FEE80_support_i/gtxKintex7FEE80_init_i/inst/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i]
+
+#create_generated_clock -name rxSodaClk [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/FEE_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT1]
+create_clock -period 5.0 -name rxSodaClk [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/FEE_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT1]
+create_clock -period 12.5 [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*TXOUTCLK}]
+#create_clock -period 10.0 [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*RXOUTCLK}]
+create_clock -period 10.0 -name RXOUTCLK [get_pins FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/gtx_i/gtxKintex7FEE80_init_i/U0/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i/RXOUTCLK]
+
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*TXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_gtxKintex7FEE80_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clockmodule40Mto80M1/inst/clk_out2]
+
+
+create_clock -period 3.125 -name BitClk_0 [get_pins FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_1 [get_pins FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_2 [get_pins FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_3 [get_pins FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_4 [get_pins FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_5 [get_pins FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_6 [get_pins FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+create_clock -period 3.125 -name BitClk_7 [get_pins FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufio/O]
+
+create_clock -period 3.125 -name DCOA1_P -waveform {0.000 1.563} [get_ports DCOA1_P]
+create_clock -period 3.125 -name DCOA2_P -waveform {0.000 1.563} [get_ports DCOA2_P]
+create_clock -period 3.125 -name DCOA3_P -waveform {0.000 1.563} [get_ports DCOA3_P]
+create_clock -period 3.125 -name DCOA4_P -waveform {0.000 1.563} [get_ports DCOA4_P]
+create_clock -period 3.125 -name DCOB1_P -waveform {0.000 1.563} [get_ports DCOB1_P]
+create_clock -period 3.125 -name DCOB2_P -waveform {0.000 1.563} [get_ports DCOB2_P]
+create_clock -period 3.125 -name DCOB3_P -waveform {0.000 1.563} [get_ports DCOB3_P]
+create_clock -period 3.125 -name DCOB4_P -waveform {0.000 1.563} [get_ports DCOB4_P]
+#create_clock -period 1000.000 -name GEO -waveform {0.000 500.000} [get_ports GEO]
+
+#create_clock -period 12.500 -name clock_S -waveform {0.000 6.250} [get_nets clock_S]
+#create_clock -period 10.000 -name clock100MHz_S -waveform {0.000 5.000} [get_nets clock100MHz_S]
+#create_clock -period 5.000 -name clock200MHz_S -waveform {0.000 2.500} [get_nets clock200MHz_S]
+#create_clock -period 15.833 -name async_clock_S [get_nets async_clock_S]
+
+#create_clock -period 12.500 -name adcclockA0 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_1/IntClkDiv]
+#create_clock -period 12.500 -name adcclockA1 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_2/IntClkDiv]
+#create_clock -period 12.500 -name adcclockA2 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_3/IntClkDiv]
+#create_clock -period 12.500 -name adcclockA3 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel1458_4/IntClkDiv]
+#create_clock -period 12.500 -name adcclockB0 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_1/IntClkDiv]
+#create_clock -period 12.500 -name adcclockB1 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_2/IntClkDiv]
+#create_clock -period 12.500 -name adcclockB2 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_3/IntClkDiv]
+#create_clock -period 12.500 -name adcclockB3 -waveform {0.000 6.250} [get_nets FEE_ADCinput_module1/AdcToplevel2356_4/IntClkDiv]
+
+create_clock -period 12.500 -name adcclockA0 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockA1 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockA2 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockA3 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockB0 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockB1 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockB2 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+create_clock -period 12.500 -name adcclockB3 -waveform {0.000 6.250} [get_pins FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Bufr/O]
+
+
+set_false_path -from [get_clocks SYS_CLK] -to [get_clocks {ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks ST_CLK_N] -to [get_clocks {SYS_CLK GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks GCLK_P] -to [get_clocks {SYS_CLK ST_CLK_N ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks ADC_clk_S] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_0] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_1] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_2] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_3 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_3] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_4 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_4] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_5 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_5] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_6 BitClk_7}]
+set_false_path -from [get_clocks BitClk_6] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_7}]
+set_false_path -from [get_clocks BitClk_7] -to [get_clocks {SYS_CLK ST_CLK_N GCLK_P ADC_clk_S BitClk_0 BitClk_1 BitClk_2 BitClk_3 BitClk_4 BitClk_5 BitClk_6}]
+
+#//set_false_path -from [get_clocks clock_S] -to [get_clocks -include_generated_clocks {clock100MHz_S clock200MHz_S ADC_clk_S }]
+set_false_path -from [get_clocks clock_S] -to [get_clocks -include_generated_clocks {clock200MHz_S ADC_clk_S RXOUTCLK rxSodaClk aurora_clock}]
+#//set_false_path -from [get_clocks clock100MHz_S] -to [get_clocks -include_generated_clocks {clock_S ADC_clk_S}]
+set_false_path -from [get_clocks clock200MHz_S] -to [get_clocks -include_generated_clocks {clock_S ADC_clk_S aurora_clock}]
+#//set_false_path -from [get_clocks ADC_clk_S] -to [get_clocks -include_generated_clocks {clock_S clock100MHz_S clock200MHz_S}]
+set_false_path -from [get_clocks ADC_clk_S] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S aurora_clock}]
+set_false_path -from [get_clocks RXOUTCLK] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S aurora_clock}]
+set_false_path -from [get_clocks rxSodaClk] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S aurora_clock}]
+set_false_path -from [get_clocks aurora_clock] -to [get_clocks -include_generated_clocks {clock_S clock200MHz_S ADC_clk_S RXOUTCLK rxSodaClk}]
+
+set_false_path -from [get_clocks adcclockA0] -to [get_clocks BitClk_0]
+set_false_path -from [get_clocks adcclockB0] -to [get_clocks BitClk_1]
+set_false_path -from [get_clocks adcclockA1] -to [get_clocks BitClk_2]
+set_false_path -from [get_clocks adcclockB1] -to [get_clocks BitClk_3]
+set_false_path -from [get_clocks adcclockA2] -to [get_clocks BitClk_4]
+set_false_path -from [get_clocks adcclockB2] -to [get_clocks BitClk_5]
+set_false_path -from [get_clocks adcclockA3] -to [get_clocks BitClk_6]
+set_false_path -from [get_clocks adcclockB3] -to [get_clocks BitClk_7]
+
+set_false_path -from [get_clocks adcclockA0] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockB0] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockA1] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockB1] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockA2] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockB2] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockA3] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+set_false_path -from [get_clocks adcclockB3] -to [get_clocks -include_generated_clocks {clock_S async_clock_S}]
+
+set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks {adcclockA0 adcclockB0 adcclockA1 adcclockB1 adcclockA2 adcclockB2 adcclockA3 adcclockB3}]
+
+#//set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock40MHz_S]
+set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock_S]
+#//set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock100MHz_S]
+set_false_path -from [get_clocks -include_generated_clocks async_clock_S] -to [get_clocks -include_generated_clocks clock200MHz_S]
+#//set_false_path -from [get_clocks -include_generated_clocks clock40MHz_S] -to [get_clocks -include_generated_clocks async_clock_S]
+
+#//set_false_path -from [get_clocks -include_generated_clocks clock40MHz_S] -to [get_clocks -include_generated_clocks async_clock_S]
+set_false_path -from [get_clocks -include_generated_clocks clock_S] -to [get_clocks -include_generated_clocks async_clock_S]
+#//set_false_path -from [get_clocks -include_generated_clocks clock100MHz_S] -to [get_clocks -include_generated_clocks async_clock_S]
+set_false_path -from [get_clocks -include_generated_clocks clock200MHz_S] -to [get_clocks -include_generated_clocks async_clock_S]
+
+set_max_delay -from [get_clocks rxSodaClk] -to [get_clocks -include_generated_clocks {ADC_clk_S}] 3.0
+
+################################################################################
+# Timespec between groups
+################################################################################
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/*}] 3.000
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcFrame/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcFrame/*}] 3.000
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_1/*}] 3.000
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_1/*}] 3.000
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_2/*}] 3.000
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_2/*}] 3.000
+
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_3/*}] 3.000
+
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_3/*}] 3.000
+
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel1458_4/*}] 3.000
+
+
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000
+set_max_delay -from [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*}] -to [get_cells * -hierarchical -filter {NAME =~ FEE_ADCinput_module1/AdcToplevel2356_4/*}] 3.000
+
+set_max_delay -from [get_clocks BitClk_0] 1.000
+set_max_delay -from [get_clocks BitClk_1] 1.000
+set_max_delay -from [get_clocks BitClk_2] 1.000
+set_max_delay -from [get_clocks BitClk_3] 1.000
+set_max_delay -from [get_clocks BitClk_4] 1.000
+set_max_delay -from [get_clocks BitClk_5] 1.000
+set_max_delay -from [get_clocks BitClk_6] 1.000
+set_max_delay -from [get_clocks BitClk_7] 1.000
+set_max_delay -from [get_clocks adcclockA0] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockA1] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockA2] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockA3] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockB0] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockB1] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockB2] -to [get_clocks ADC_clk_S] 2.600
+set_max_delay -from [get_clocks adcclockB3] -to [get_clocks ADC_clk_S] 2.600
+#--//set_max_delay -from [get_clocks ADC_clk_S] 3.000
+
+
+#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -min -add_delay 0.000 [get_ports AD11A_N]
+#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -max -add_delay 1.000 [get_ports AD11A_N]
+#set_input_delay -clock [get_clocks BitClk_0] -min -add_delay 0.000 [get_ports AD11A_N]
+#set_input_delay -clock [get_clocks BitClk_0] -max -add_delay 1.000 [get_ports AD11A_N]
+#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -min -add_delay 0.000 [get_ports AD11A_P]
+#set_input_delay -clock [get_clocks BitClk_0] -clock_fall -max -add_delay 1.000 [get_ports AD11A_P]
+#set_input_delay -clock [get_clocks BitClk_0] -min -add_delay 0.000 [get_ports AD11A_P]
+#set_input_delay -clock [get_clocks BitClk_0] -max -add_delay 1.000 [get_ports AD11A_P]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clockmodule40Mto80M1/inst/clk_out2]
+
+# TXOUTCLK Constraint: Value is selected based on the line rate (4.0 Gbps) and lane width (4-Byte)
+#create_clock -period 10.000	 [get_pins -hier -filter {name=~*gt_wrapper_i*aurora_dual_multi_gt_i*gt0_aurora_dual_i*gtxe2_i*TXOUTCLK}]
+#### CDC Path #####
+set_false_path -to [get_pins -hier *cdc_to*]
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *ack_sync_reg1}]
+############################### GT LOC (For use in top level design) ###################################
+set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells gen_combine.aurora_dual_module1/aurora_module_i/aurora_dual_i/U0/gt_wrapper_i/aurora_dual_multi_gt_i/gt0_aurora_dual_i/gtxe2_i]
+set_property LOC GTXE2_CHANNEL_X0Y2 [get_cells gen_combine.aurora_dual_module1/aurora_module_i/aurora_dual_i/U0/gt_wrapper_i/aurora_dual_multi_gt_i/gt1_aurora_dual_i/gtxe2_i]
+
+#//set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
+#//set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
+#//set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}]
+#//set_property LOC GTXE2_CHANNEL_X0Y1 [get_cells gtxconn1_module1/gtxconn1_support_i/gtxconn1_init_i/U0/gtxconn1_i/gt0_gtxconn1_i/gtxe2_i]
+#//set_property LOC GTXE2_CHANNEL_X0Y2 [get_cells gtxconn2_module1/gtxconn2_support_i/gtxconn2_init_i/U0/gtxconn2_i/gt0_gtxconn2_i/gtxe2_i]
+
+
+# Configuration options
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain_debug.xdc b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/ADC32dualgain_debug.xdc
new file mode 100644
index 0000000..e69de29
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard.vhd
new file mode 100644
index 0000000..b45cf56
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard.vhd
@@ -0,0 +1,2383 @@
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+--library Adc_Interface;
+--    use Adc_Interface.all;
+library work;
+USE work.panda_package.all;
+use work.soda_components.all;
+    
+entity FEE_Kintex_ADCboard is
+    Port ( 
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+		SYS_CLK                 : in std_logic; -- 100MHz
+		GCLK_P                  : in std_logic;
+		GCLK_N                  : in std_logic;
+		ST_CLK_P                : in std_logic;
+		ST_CLK_N                : in std_logic;
+
+----ADC1---------------------------------------------		
+		AD11A_P                 : in std_logic;
+		AD11A_N                 : in std_logic;
+		AD11B_P                 : in std_logic;
+		AD11B_N                 : in std_logic;
+		AD12A_P                 : in std_logic;
+		AD12A_N                 : in std_logic;
+		AD12B_P                 : in std_logic;
+		AD12B_N                 : in std_logic;
+		AD13A_P                 : in std_logic;
+		AD13A_N                 : in std_logic;
+		AD13B_P                 : in std_logic;
+		AD13B_N                 : in std_logic;
+		AD14A_P                 : in std_logic;
+		AD14A_N                 : in std_logic;
+		AD14B_P                 : in std_logic;
+		AD14B_N                 : in std_logic;
+		AD15A_P                 : in std_logic;
+		AD15A_N                 : in std_logic;
+		AD15B_P                 : in std_logic;
+		AD15B_N                 : in std_logic;
+		AD16A_P                 : in std_logic;
+		AD16A_N                 : in std_logic;
+		AD16B_P                 : in std_logic;
+		AD16B_N                 : in std_logic;
+		AD17A_P                 : in std_logic;
+		AD17A_N                 : in std_logic;
+		AD17B_P                 : in std_logic;
+		AD17B_N                 : in std_logic;
+		AD18A_P                 : in std_logic;
+		AD18A_N                 : in std_logic;
+		AD18B_P                 : in std_logic;
+		AD18B_N                 : in std_logic;
+		
+		DCOA1_P                 : in std_logic;
+		DCOA1_N                 : in std_logic;
+		DCOB1_P                 : in std_logic;
+		DCOB1_N                 : in std_logic;
+		
+		FRA1_P                  : in std_logic;
+		FRA1_N                  : in std_logic;
+		FRB1_P                  : in std_logic;
+		FRB1_N                  : in std_logic;
+
+
+----ADC2---------------------------------------------		
+		AD21A_P                 : in std_logic;
+		AD21A_N                 : in std_logic;
+		AD21B_P                 : in std_logic;
+		AD21B_N                 : in std_logic;
+		AD22A_P                 : in std_logic;
+		AD22A_N                 : in std_logic;
+		AD22B_P                 : in std_logic;
+		AD22B_N                 : in std_logic;
+		AD23A_P                 : in std_logic;
+		AD23A_N                 : in std_logic;
+		AD23B_P                 : in std_logic;
+		AD23B_N                 : in std_logic;
+		AD24A_P                 : in std_logic;
+		AD24A_N                 : in std_logic;
+		AD24B_P                 : in std_logic;
+		AD24B_N                 : in std_logic;
+		AD25A_P                 : in std_logic;
+		AD25A_N                 : in std_logic;
+		AD25B_P                 : in std_logic;
+		AD25B_N                 : in std_logic;
+		AD26A_P                 : in std_logic;
+		AD26A_N                 : in std_logic;
+		AD26B_P                 : in std_logic;
+		AD26B_N                 : in std_logic;
+		AD27A_P                 : in std_logic;
+		AD27A_N                 : in std_logic;
+		AD27B_P                 : in std_logic;
+		AD27B_N                 : in std_logic;
+		AD28A_P                 : in std_logic;
+		AD28A_N                 : in std_logic;
+		AD28B_P                 : in std_logic;
+		AD28B_N                 : in std_logic;
+
+		DCOA2_P                 : in std_logic;
+		DCOA2_N                 : in std_logic;
+		DCOB2_P                 : in std_logic;
+		DCOB2_N                 : in std_logic;
+		
+		FRA2_P                  : in std_logic;
+		FRA2_N                  : in std_logic;
+		FRB2_P                  : in std_logic;
+		FRB2_N                  : in std_logic;
+
+----ADC3---------------------------------------------		
+		AD31A_P                 : in std_logic;
+		AD31A_N                 : in std_logic;
+		AD31B_P                 : in std_logic;
+		AD31B_N                 : in std_logic;
+		AD32A_P                 : in std_logic;
+		AD32A_N                 : in std_logic;
+		AD32B_P                 : in std_logic;
+		AD32B_N                 : in std_logic;
+		AD33A_P                 : in std_logic;
+		AD33A_N                 : in std_logic;
+		AD33B_P                 : in std_logic;
+		AD33B_N                 : in std_logic;
+		AD34A_P                 : in std_logic;
+		AD34A_N                 : in std_logic;
+		AD34B_P                 : in std_logic;
+		AD34B_N                 : in std_logic;
+		AD35A_P                 : in std_logic;
+		AD35A_N                 : in std_logic;
+		AD35B_P                 : in std_logic;
+		AD35B_N                 : in std_logic;
+		AD36A_P                 : in std_logic;
+		AD36A_N                 : in std_logic;
+		AD36B_P                 : in std_logic;
+		AD36B_N                 : in std_logic;
+		AD37A_P                 : in std_logic;
+		AD37A_N                 : in std_logic;
+		AD37B_P                 : in std_logic;
+		AD37B_N                 : in std_logic;
+		AD38A_P                 : in std_logic;
+		AD38A_N                 : in std_logic;
+		AD38B_P                 : in std_logic;
+		AD38B_N                 : in std_logic;
+
+		DCOA3_P                 : in std_logic;
+		DCOA3_N                 : in std_logic;
+		DCOB3_P                 : in std_logic;
+		DCOB3_N                 : in std_logic;
+		
+		FRA3_P                  : in std_logic;
+		FRA3_N                  : in std_logic;
+		FRB3_P                  : in std_logic;
+		FRB3_N                  : in std_logic;
+
+----ADC4---------------------------------------------		
+		AD41A_P                 : in std_logic;
+		AD41A_N                 : in std_logic;
+		AD41B_P                 : in std_logic;
+		AD41B_N                 : in std_logic;
+		AD42A_P                 : in std_logic;
+		AD42A_N                 : in std_logic;
+		AD42B_P                 : in std_logic;
+		AD42B_N                 : in std_logic;
+		AD43A_P                 : in std_logic;
+		AD43A_N                 : in std_logic;
+		AD43B_P                 : in std_logic;
+		AD43B_N                 : in std_logic;
+		AD44A_P                 : in std_logic;
+		AD44A_N                 : in std_logic;
+		AD44B_P                 : in std_logic;
+		AD44B_N                 : in std_logic;
+		AD45A_P                 : in std_logic;
+		AD45A_N                 : in std_logic;
+		AD45B_P                 : in std_logic;
+		AD45B_N                 : in std_logic;
+		AD46A_P                 : in std_logic;
+		AD46A_N                 : in std_logic;
+		AD46B_P                 : in std_logic;
+		AD46B_N                 : in std_logic;
+		AD47A_P                 : in std_logic;
+		AD47A_N                 : in std_logic;
+		AD47B_P                 : in std_logic;
+		AD47B_N                 : in std_logic;
+		AD48A_P                 : in std_logic;
+		AD48A_N                 : in std_logic;
+		AD48B_P                 : in std_logic;
+		AD48B_N                 : in std_logic;		
+		
+		DCOA4_P                 : in std_logic;
+		DCOA4_N                 : in std_logic;
+		DCOB4_P                 : in std_logic;
+		DCOB4_N                 : in std_logic;
+		
+		FRA4_P                  : in std_logic;
+		FRA4_N                  : in std_logic;
+		FRB4_P                  : in std_logic;
+		FRB4_N                  : in std_logic;
+		
+----ADCconfiguration---------------------------------------------		
+		SCK                     : out std_logic;
+		SDI                     : out std_logic;
+		CSA                     : out std_logic_vector(1 to 4);
+		CSB                     : out std_logic_vector(1 to 4);
+		SDOA                    : in std_logic_vector(1 to 4); -- out for parallel init
+		SDOB                    : in std_logic_vector(1 to 4); -- out for parallel init
+
+----GTX---------------------------------------------		
+		MOD_DEF                 : in std_logic_vector(2 downto 0);
+		LOS                     : in std_logic;
+		TX_DIS                  : out std_logic;
+		MGTREFCLK_P             : in std_logic;
+		MGTREFCLK_N             : in std_logic;
+
+		RX_P                    : in std_logic;
+		RX_N                    : in std_logic;
+		TX_P                    : out std_logic;
+		TX_N                    : out std_logic;
+
+----PLL---------------------------------------------		
+		S_CTRL                  : in std_logic; -- 1 : FPGA1 controls PLL&JTAG, 0 : FPGA2 controls PLL&JTAG
+		T_CTRL                  : out std_logic; -- T_CTRL from FPGA1<>T_CTRL from FPGA2 : FPGA2 controls PLL&JTAG
+		RDu                     : in std_logic;
+		CLKu                    : inout std_logic;
+		DATAu                   : inout std_logic;
+		LEu                     : inout std_logic;
+		SYNC                    : out std_logic;
+		RCV_CLK_P               : out std_logic; -- ref clock for PLL LMK04806
+		RCV_CLK_N               : out std_logic;
+		
+----interconnection---------------------------------------------		
+		INTCOMC1_P              : inout std_logic;
+		INTCOMC1_N              : inout std_logic;
+		INTCOMC2_P              : inout std_logic;
+		INTCOMC2_N              : inout std_logic;
+
+		INTCOM0_P               : inout std_logic;
+		INTCOM0_N               : inout std_logic;
+		INTCOM1_P               : inout std_logic;
+		INTCOM1_N               : inout std_logic;
+		INTCOM2_P               : inout std_logic;
+		INTCOM2_N               : inout std_logic;
+		INTCOM3_P               : inout std_logic;
+		INTCOM3_N               : inout std_logic;
+		INTCOM4_P               : inout std_logic;
+		INTCOM4_N               : inout std_logic;
+		INTCOM5_P               : inout std_logic;
+		INTCOM5_N               : inout std_logic;
+		INTCOM6_P               : inout std_logic;
+		INTCOM6_N               : inout std_logic;
+		INTCOM7_P               : inout std_logic;
+		INTCOM7_N               : inout std_logic;
+
+----Temperature-------------------------------------
+		TEMP_IN                 : out std_logic;
+		TEMP_OUT                : in std_logic;
+
+----Interconnection-------------------------------------
+		GT_A2B_0_P              : out std_logic;
+		GT_A2B_0_N              : out std_logic;
+		GT_A2B_1_P              : out std_logic;
+		GT_A2B_1_N              : out std_logic;
+		GT_B2A_0_P              : in std_logic;
+		GT_B2A_0_N              : in std_logic;
+		GT_B2A_1_P              : in std_logic;
+		GT_B2A_1_N              : in std_logic;
+
+----JTAG out-------------------------------------
+		JTAG_OUT1_TCK_F         : inout std_logic;
+		JTAG_OUT1_TDI_F         : inout std_logic;
+		JTAG_OUT1_TDO_F         : inout std_logic;
+		JTAG_OUT1_TMS_F         : inout std_logic;
+
+----Test,Monitor-------------------------------------
+		MON1_P                  : out std_logic;
+		MON1_N                  : out std_logic; -- in
+		MON2_P                  : out std_logic;
+		MON2_N                  : out std_logic
+		);
+end FEE_Kintex_ADCboard;
+
+
+
+architecture Behavioral of FEE_Kintex_ADCboard is
+constant FPGA_IN_CONTROL       : std_logic := '0';
+constant ADC_PARALLELINIT      : boolean := true;
+constant SWAPFPGAS             : boolean := false;
+constant SECOND_FE_MODULE      : boolean := true;
+constant MWD_DOUBLEFILTER      : boolean := true;
+constant MWD_PU_DOUBLEFILTER   : boolean := true;
+constant MWD_WIDTHBITS         : natural := 4;
+constant MWD_SCALEBITS         : natural := 12;
+constant MWD2_WIDTHBITS        : natural := 1;
+constant MWD2_SCALEBITS        : natural := 8;
+constant BASELINE_BWBITS       : natural := 10;
+constant WAVEFORMBUFFERSIZE    : natural := 9;
+constant CF_DELAYBITS          : natural := 3;
+constant MAXPILEUPHITS         : natural := 3;
+constant IDIVMAXBITS           : natural := 6;
+constant INTEGRALRATIOBITS     : natural := 3;
+
+		
+component clockmodule100to80M
+port(
+		CLK_IN1           : in std_logic;
+		CLK_OUT1          : out std_logic;
+		CLK_OUT2          : out std_logic;
+		CLK_OUT3          : out std_logic;
+		CLK_OUT4          : out std_logic;
+		CLK_OUT5          : out std_logic;
+		CLK_OUT6          : out std_logic;
+		RESET             : in std_logic;
+		LOCKED            : out std_logic
+		);
+end component;
+
+component clockmodule40Mto80M
+port(
+		CLK_IN1           : in std_logic;
+		CLK_OUT1          : out std_logic;
+		CLK_OUT2          : out std_logic;
+		RESET             : in std_logic;
+		LOCKED            : out std_logic
+		);
+end component;
+
+component LMK04806 is
+	generic(
+		CLK_DIV               : integer := 2      -- slow down transfer : mayb 1
+	);         
+	port( 
+		clock                   : in std_logic; --Master clock 
+		reset                   : in std_logic; --reset
+		CLKu                    : out std_logic; --Clk to LMK  
+		DATAu                   : out std_logic; --Data to LMK
+		LEu                     : out std_logic; --Data Latch to LMK
+		RDu                     : in std_logic; --Read back
+		SYNC                    : out std_logic; --Sync CLK outputs LMK
+		boot_PLL                : in std_logic; --Start booting when set high
+		booting                 : out std_logic --busy signal		
+		);
+end component;
+
+component FEE_startup is
+	port( 
+		clock                 : in std_logic;
+		ADCclock              : in std_logic;
+		clock_from_PLL        : in std_logic;
+		reset                 : in std_logic;
+		GEO                   : in std_logic;
+		IcontrolPLL           : in std_logic;
+		ADCchip_init          : out std_logic;
+		PLL_init              : out std_logic;
+		PLL_booting           : in std_logic;
+		GTX_reset             : out std_logic;
+		GTX_LOS               : in std_logic;
+		GTX_rxLocked          : in std_logic;
+		GTX_txLocked          : in std_logic;
+		GTX_error             : in std_logic;
+		PLLuseGTXclock        : out std_logic;
+		PLL_locked            : in std_logic;
+		ADCs_reset            : out std_logic;
+		ADCs_ready            : in std_logic;
+		FEE_reset             : out std_logic;
+		startupready          : out std_logic
+		);
+end component;
+
+component FEE_ADCinput_module is
+	port ( 
+		clock200MHz             : in std_logic;
+		clock80MHz              : in std_logic;
+		clockAsync              : in std_logic;
+		reset                   : in std_logic;
+		ADCs_enable             : in std_logic;
+----ADC1---------------------------------------------		
+		AD11A_P                 : in std_logic;
+		AD11A_N                 : in std_logic;
+		AD11B_P                 : in std_logic;
+		AD11B_N                 : in std_logic;
+		AD12A_P                 : in std_logic;
+		AD12A_N                 : in std_logic;
+		AD12B_P                 : in std_logic;
+		AD12B_N                 : in std_logic;
+		AD13A_P                 : in std_logic;
+		AD13A_N                 : in std_logic;
+		AD13B_P                 : in std_logic;
+		AD13B_N                 : in std_logic;
+		AD14A_P                 : in std_logic;
+		AD14A_N                 : in std_logic;
+		AD14B_P                 : in std_logic;
+		AD14B_N                 : in std_logic;
+		AD15A_P                 : in std_logic;
+		AD15A_N                 : in std_logic;
+		AD15B_P                 : in std_logic;
+		AD15B_N                 : in std_logic;
+		AD16A_P                 : in std_logic;
+		AD16A_N                 : in std_logic;
+		AD16B_P                 : in std_logic;
+		AD16B_N                 : in std_logic;
+		AD17A_P                 : in std_logic;
+		AD17A_N                 : in std_logic;
+		AD17B_P                 : in std_logic;
+		AD17B_N                 : in std_logic;
+		AD18A_P                 : in std_logic;
+		AD18A_N                 : in std_logic;
+		AD18B_P                 : in std_logic;
+		AD18B_N                 : in std_logic;
+		
+		DCOA1_P                 : in std_logic;
+		DCOA1_N                 : in std_logic;
+		DCOB1_P                 : in std_logic;
+		DCOB1_N                 : in std_logic;
+		
+		FRA1_P                  : in std_logic;
+		FRA1_N                  : in std_logic;
+		FRB1_P                  : in std_logic;
+		FRB1_N                  : in std_logic;
+
+----ADC2---------------------------------------------		
+		AD21A_P                 : in std_logic;
+		AD21A_N                 : in std_logic;
+		AD21B_P                 : in std_logic;
+		AD21B_N                 : in std_logic;
+		AD22A_P                 : in std_logic;
+		AD22A_N                 : in std_logic;
+		AD22B_P                 : in std_logic;
+		AD22B_N                 : in std_logic;
+		AD23A_P                 : in std_logic;
+		AD23A_N                 : in std_logic;
+		AD23B_P                 : in std_logic;
+		AD23B_N                 : in std_logic;
+		AD24A_P                 : in std_logic;
+		AD24A_N                 : in std_logic;
+		AD24B_P                 : in std_logic;
+		AD24B_N                 : in std_logic;
+		AD25A_P                 : in std_logic;
+		AD25A_N                 : in std_logic;
+		AD25B_P                 : in std_logic;
+		AD25B_N                 : in std_logic;
+		AD26A_P                 : in std_logic;
+		AD26A_N                 : in std_logic;
+		AD26B_P                 : in std_logic;
+		AD26B_N                 : in std_logic;
+		AD27A_P                 : in std_logic;
+		AD27A_N                 : in std_logic;
+		AD27B_P                 : in std_logic;
+		AD27B_N                 : in std_logic;
+		AD28A_P                 : in std_logic;
+		AD28A_N                 : in std_logic;
+		AD28B_P                 : in std_logic;
+		AD28B_N                 : in std_logic;
+
+		DCOA2_P                 : in std_logic;
+		DCOA2_N                 : in std_logic;
+		DCOB2_P                 : in std_logic;
+		DCOB2_N                 : in std_logic;
+		
+		FRA2_P                  : in std_logic;
+		FRA2_N                  : in std_logic;
+		FRB2_P                  : in std_logic;
+		FRB2_N                  : in std_logic;
+
+----ADC3---------------------------------------------		
+		AD31A_P                 : in std_logic;
+		AD31A_N                 : in std_logic;
+		AD31B_P                 : in std_logic;
+		AD31B_N                 : in std_logic;
+		AD32A_P                 : in std_logic;
+		AD32A_N                 : in std_logic;
+		AD32B_P                 : in std_logic;
+		AD32B_N                 : in std_logic;
+		AD33A_P                 : in std_logic;
+		AD33A_N                 : in std_logic;
+		AD33B_P                 : in std_logic;
+		AD33B_N                 : in std_logic;
+		AD34A_P                 : in std_logic;
+		AD34A_N                 : in std_logic;
+		AD34B_P                 : in std_logic;
+		AD34B_N                 : in std_logic;
+		AD35A_P                 : in std_logic;
+		AD35A_N                 : in std_logic;
+		AD35B_P                 : in std_logic;
+		AD35B_N                 : in std_logic;
+		AD36A_P                 : in std_logic;
+		AD36A_N                 : in std_logic;
+		AD36B_P                 : in std_logic;
+		AD36B_N                 : in std_logic;
+		AD37A_P                 : in std_logic;
+		AD37A_N                 : in std_logic;
+		AD37B_P                 : in std_logic;
+		AD37B_N                 : in std_logic;
+		AD38A_P                 : in std_logic;
+		AD38A_N                 : in std_logic;
+		AD38B_P                 : in std_logic;
+		AD38B_N                 : in std_logic;
+
+		DCOA3_P                 : in std_logic;
+		DCOA3_N                 : in std_logic;
+		DCOB3_P                 : in std_logic;
+		DCOB3_N                 : in std_logic;
+		
+		FRA3_P                  : in std_logic;
+		FRA3_N                  : in std_logic;
+		FRB3_P                  : in std_logic;
+		FRB3_N                  : in std_logic;
+
+----ADC4---------------------------------------------		
+		AD41A_P                 : in std_logic;
+		AD41A_N                 : in std_logic;
+		AD41B_P                 : in std_logic;
+		AD41B_N                 : in std_logic;
+		AD42A_P                 : in std_logic;
+		AD42A_N                 : in std_logic;
+		AD42B_P                 : in std_logic;
+		AD42B_N                 : in std_logic;
+		AD43A_P                 : in std_logic;
+		AD43A_N                 : in std_logic;
+		AD43B_P                 : in std_logic;
+		AD43B_N                 : in std_logic;
+		AD44A_P                 : in std_logic;
+		AD44A_N                 : in std_logic;
+		AD44B_P                 : in std_logic;
+		AD44B_N                 : in std_logic;
+		AD45A_P                 : in std_logic;
+		AD45A_N                 : in std_logic;
+		AD45B_P                 : in std_logic;
+		AD45B_N                 : in std_logic;
+		AD46A_P                 : in std_logic;
+		AD46A_N                 : in std_logic;
+		AD46B_P                 : in std_logic;
+		AD46B_N                 : in std_logic;
+		AD47A_P                 : in std_logic;
+		AD47A_N                 : in std_logic;
+		AD47B_P                 : in std_logic;
+		AD47B_N                 : in std_logic;
+		AD48A_P                 : in std_logic;
+		AD48A_N                 : in std_logic;
+		AD48B_P                 : in std_logic;
+		AD48B_N                 : in std_logic;		
+		
+		DCOA4_P                 : in std_logic;
+		DCOA4_N                 : in std_logic;
+		DCOB4_P                 : in std_logic;
+		DCOB4_N                 : in std_logic;
+		
+		FRA4_P                  : in std_logic;
+		FRA4_N                  : in std_logic;
+		FRB4_P                  : in std_logic;
+		FRB4_N                  : in std_logic;
+		ADC_clk                 : out std_logic;
+		ADCs_ready              : out std_logic;
+		adcdata                 : out array_adc_type
+		);
+end component;
+
+component AdcSerialProg is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		init                    : in std_logic;
+		clock_out               : out std_logic;
+		dataA_in                : in std_logic_vector(3 downto 0);
+		dataB_in                : in std_logic_vector(3 downto 0);
+		data_out                : out std_logic;
+		chipnselectA            : out std_logic_vector(3 downto 0);
+		chipnselectB            : out std_logic_vector(3 downto 0);
+		selREGS       : in std_logic_vector(2 downto 0)
+		);
+end component;
+
+component FEE_gtxModule is
+	Port (
+		gtpClk_P                : in std_logic;
+		gtpClk_N                : in std_logic;
+		refclk_out              : out std_logic;
+		sysClk                  : in  std_logic;	
+		asyncclk                : in std_logic;
+		reset                   : in std_logic;
+		disable_GTX_reset       : in std_logic;
+		
+		TX_DLM                  : in std_logic;
+		TX_DLM_WORD             : in std_logic_vector(7 downto 0);   
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		
+		txAsyncClk              : in std_logic;
+		txAsyncData             : in std_logic_vector(31 downto 0);
+		txAsyncDataWrite        : in std_logic;
+		txAsyncFirstData        : in std_logic;
+		txAsyncLastData         : in std_logic;
+		txAsyncFifoFull         : out std_logic;
+		txUsrClk                : out  std_logic;
+		txLocked                : out std_logic;
+		
+		rxAsyncClk              : in std_logic;
+		rxAsyncData             : out std_logic_vector(31 downto 0);
+		rxAsyncFirstData        : out std_logic;
+		rxAsyncLastData         : out std_logic;
+		rxAsyncDataRead         : in std_logic;
+		rxError                 : out std_logic;
+		rxAsyncDataOverflow     : out std_logic;
+		rxAsyncDataPresent      : out std_logic;
+		rxUsrClkdiv2            : out std_logic;
+		rxSodaClk               : out std_logic;
+		rxSodaClk40             : out std_logic;
+		rxLocked                : out std_logic;
+		
+		gtpTxP0                 : out std_logic;
+		gtpTxN0                 : out std_logic;
+		gtpRxP0                 : in std_logic;
+		gtpRxN0                 : in std_logic;
+		GT0_QPLLOUTCLK_IN       : in std_logic;
+		GT0_QPLLOUTREFCLK_IN    : in std_logic
+	);
+end component;
+
+component gtx_common is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "TRUE";        -- Set to "true" to speed up sim reset 
+    SIM_QPLLREFCLK_SEL              : bit_vector :=  "001"
+);
+port
+(
+    QPLLREFCLKSEL_IN  : in std_logic_vector(2 downto 0);
+    GTREFCLK1_IN      : in std_logic;
+    GTREFCLK0_IN : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+);
+
+end component;
+
+component FEE_adc32_module is
+	generic (
+		NROFADCS                : natural := NROFFEEADCS;
+		ADCBITS                 : natural := ADCBITS;
+		MWD_WIDTHBITS           : natural := MWD_WIDTHBITS;
+		MWD2_WIDTHBITS          : natural := MWD2_WIDTHBITS;
+		MWD_SCALEBITS           : natural := MWD_SCALEBITS;
+		MWD2_SCALEBITS          : natural := MWD2_SCALEBITS;
+		MWD_DOUBLEFILTER        : boolean := MWD_DOUBLEFILTER;
+		MWD_PU_DOUBLEFILTER     : boolean := MWD_PU_DOUBLEFILTER;
+		BASELINE_BWBITS         : natural := BASELINE_BWBITS;
+		WAVEFORMBUFFERSIZE      : natural := WAVEFORMBUFFERSIZE;
+		ADCCLOCKFREQUENCY       : natural := ADCCLOCKFREQUENCY;
+		CF_DELAYBITS            : natural := CF_DELAYBITS;
+		MAXPILEUPHITS           : natural := MAXPILEUPHITS;
+		IDIVMAXBITS             : natural := IDIVMAXBITS;
+		INTEGRALRATIOBITS       : natural := INTEGRALRATIOBITS;
+		SECOND_FE_MODULE        : boolean := SECOND_FE_MODULE
+	);
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		enable_data             : in std_logic;
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+		ADCdata                 : in array_adc_type;
+		superburst_start        : in std_logic;
+		superburst_received     : in std_logic_vector(30 downto 0);
+		force_hit               : in std_logic;
+		onesecondpulse          : in std_logic;
+		rxNotInTable            : in std_logic;
+		startupready            : in std_logic;
+		request_init            : in std_logic;
+		packet_in_data          : in std_logic_vector (31 downto 0);
+		packet_in_present       : in std_logic;
+		packet_in_read          : out std_logic;
+		packet_out_data         : out std_logic_vector(31 downto 0);
+		packet_out_first        : out std_logic;
+		packet_out_last         : out std_logic;
+		packet_out_write        : out std_logic;
+		packet_out_inpipe       : out std_logic;
+		packet_out_fifofull     : in std_logic;
+		errorbyte_out           : out std_logic_vector(7 downto 0);
+		errorbyte_in            : in std_logic_vector(7 downto 0);
+		smaart_in               : in std_logic;
+		smaart_out              : out std_logic;
+		sysmon_data             : in std_logic_vector(15 downto 0);
+		sysmon_reset            : out std_logic;
+		sysmon_address          : out std_logic_vector(6 downto 0);
+		sysmon_read             : out std_logic;
+		second_module_zero      : in std_logic;
+		enable_waveform         : out std_logic;
+		compare_error           : out std_logic
+		);
+end component;	
+
+component FEE_receive_split is
+	port ( 
+		clock_in                : in std_logic;
+		clock_local             : in std_logic;
+		clock_remote            : in std_logic;
+		reset                   : in std_logic;
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+		data_in                 : in std_logic_vector (31 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_present         : in std_logic;
+		data_in_fifofull        : out std_logic;
+		data_in_read            : out std_logic;
+		data_local              : out std_logic_vector(31 downto 0);
+		data_local_first        : out std_logic;
+		data_local_last         : out std_logic;
+		data_local_present      : out std_logic;
+		data_local_read         : in std_logic;
+		data_remote             : out std_logic_vector(31 downto 0);
+		data_remote_first       : out std_logic;
+		data_remote_last        : out std_logic;
+		data_remote_present     : out std_logic;
+		data_remote_read        : in std_logic;
+		error                   : out std_logic
+		);
+end component;
+
+component FEE_transmit_combine is
+	port ( 
+		clock_local             : in std_logic;
+		clock_remote            : in std_logic;
+		clock_out               : in std_logic;
+		reset                   : in std_logic;
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+		enable_waveform         : in std_logic;
+		data_local              : in std_logic_vector (31 downto 0);
+		data_local_first        : in std_logic;
+		data_local_last         : in std_logic;
+		data_local_write        : in std_logic;
+		data_local_inpipe       : in std_logic;
+		data_local_fifofull     : out std_logic;
+		data_remote             : in std_logic_vector(31 downto 0);
+		data_remote_first       : in std_logic;
+		data_remote_last        : in std_logic;
+		data_remote_write       : in std_logic;
+		data_remote_inpipe      : in std_logic;
+		data_remote_fifofull    : out std_logic;
+		data_remote_almostfull  : out std_logic;
+		data_out                : out std_logic_vector(31 downto 0);
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_inpipe         : out std_logic;
+		data_out_fifofull       : in std_logic;
+		error                   : out std_logic
+		);
+end component;
+
+component FEE_soda_client is
+    port(
+        SYSCLK                   : in std_logic; -- fabric clock
+        SODACLK                  : in std_logic; -- recovered clock
+        RESET                    : in std_logic; -- synchronous reset
+        CLEAR                    : in std_logic; -- asynchronous reset
+        CLK_EN                   : in std_logic; 
+
+        RX_DLM_WORD_IN           : in std_logic_vector(7 downto 0);
+        RX_DLM_IN                : in std_logic;
+        TX_DLM_OUT               : out std_logic;
+        TX_DLM_WORD_OUT          : out std_logic_vector(7 downto 0);
+        TX_DLM_PREVIEW_OUT       : out std_logic := '0';
+        LINK_PHASE_IN            : in std_logic;
+
+        START_OF_SUPERBURST      : out std_logic; -- PS
+        SUPER_BURST_NR           : out std_logic_vector(30 downto 0); -- PS
+        SODA_CMD_VALID           : out std_logic; -- PS
+        SODA_CMD_WORD            : out std_logic_vector(30 downto 0); -- PS
+        
+        SODA_DATA_IN             : in std_logic_vector(31 downto 0)    := (others => '0');
+        SODA_DATA_OUT            : out std_logic_vector(31 downto 0)    := (others => '0');
+        SODA_ADDR_IN             : in std_logic_vector(3 downto 0)    := (others => '0');
+        SODA_READ_IN             : in std_logic := '0';
+        SODA_WRITE_IN            : in std_logic := '0';
+        SODA_ACK_OUT             : out std_logic := '0';
+        LEDS_OUT                 : out std_logic_vector(3 downto 0);
+        LINK_DEBUG_IN            : in std_logic_vector(31 downto 0)    := (others => '0')
+    );
+end component;
+
+component SystemMonitorModule is
+    Port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		address                 : in std_logic_vector(6 downto 0);
+		data_write              : in std_logic;
+		data_in                 : in std_logic_vector(15 downto 0);
+		data_read               : in std_logic;
+		data_out                : out std_logic_vector(15 downto 0);
+		alarms                  : out std_logic_vector(7 downto 0)
+	);
+end component;
+
+component reboot is
+  port (
+    TRIGGER : in std_logic;
+    SYSCLK  : in std_logic
+    );
+end component;
+
+component sem_module is
+	port (
+		clk                           : in    std_logic;
+		status_heartbeat              : out   std_logic;
+		status_initialization         : out   std_logic;
+		status_observation            : out   std_logic;
+		status_correction             : out   std_logic;
+		status_classification         : out   std_logic;
+		status_injection              : out   std_logic;
+		status_essential              : out   std_logic;
+		status_uncorrectable          : out   std_logic
+	);
+end component;
+
+component aurora_dual_module is
+    port (
+		stable_clock                : in std_logic; -- 80MHz
+        reset                       : in std_logic;
+        user_clock                  : out std_logic;
+        tx_data                     : in std_logic_vector(31 downto 0);
+        tx_first                    : in std_logic;
+        tx_last                     : in std_logic;
+        tx_write                    : in std_logic;
+        tx_allowed                  : out std_logic;
+        tx_inpipe                   : in std_logic;
+        rx_data                     : out std_logic_vector(31 downto 0);
+        rx_first                    : out std_logic;
+        rx_last                     : out std_logic;
+        rx_write                    : out std_logic;
+        rx_almostfull               : in std_logic;
+        rx_inpipe                   : out std_logic;
+        locked                      : out std_logic;
+        error                       : out std_logic;
+        RXP                         : in std_logic_vector(0 to 1);
+        RXN                         : in std_logic_vector(0 to 1);
+        TXP                         : out std_logic_vector(0 to 1);
+        TXN                         : out std_logic_vector(0 to 1);
+        GTXQ0_P                     : in  std_logic;
+        GTXQ0_N                     : in  std_logic;
+        gt0_refclk_in               : in std_logic;
+        gt0_qplllock_in             : in std_logic;
+        gt0_qpllrefclklost_in       : in std_logic;
+        gt0_qpllreset_out           : out std_logic;
+        GT_QPLLOUTCLK_IN            : in std_logic;
+        GT_QPLLOUTREFCLK_IN         : in std_logic
+	);
+end component;
+
+component FEE_fiforead2write is
+	generic(
+		BITS                    : integer := 32
+	);
+	port(
+		clock                   : in std_logic; 
+		data_in                 : in std_logic_vector(BITS-1 downto 0);
+		data_in_empty           : in std_logic;
+		data_in_read            : out std_logic;
+		data_out                : out std_logic_vector(BITS-1 downto 0);
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic
+	); 
+end component;
+
+component posedge_to_pulse is
+	port (
+		clock_in                : in  std_logic;
+		clock_out               : in  std_logic;
+		en_clk                  : in  std_logic;
+		signal_in               :in  std_logic;
+		pulse                   : out std_logic
+	);
+end component;
+
+component vio_debug is
+  Port ( 
+    clk : in STD_LOGIC;
+    probe_in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_in1 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_in2 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_in3 : in STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out0 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out1 : out STD_LOGIC_VECTOR ( 0 to 0 );
+    probe_out2 : out STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+end component;
+
+component vio36
+  Port (
+    clk : IN STD_LOGIC;
+    probe_out0 : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
+  );
+end component;
+
+type adcdata_type is array(0 to 7) of std_logic_vector(15 downto 0); 
+type AdcDataOut_type is array(0 to 3) of std_logic_vector((32*((4/2)*2))-1 downto 0);
+type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0); 
+
+-- clocking
+signal clock_S                : std_logic; -- main clock, frequency equal to ADC clock, PLL reference during boot
+signal clock40MHz_S           : std_logic;
+signal clock100MHz_S          : std_logic;
+signal clock160MHz_S          : std_logic;
+signal clock200MHz_S          : std_logic;
+signal gclk_S                 : std_logic;
+signal ST_CLK_S               : std_logic;
+signal async_clock_S          : std_logic;
+signal RCV_CLK_S              : std_logic;
+signal ADC_clk_S              : std_logic;
+signal onesecondpulse_S       : std_logic;
+
+-- resetting
+signal IcontrolPLL_S          : std_logic := '0';
+signal IcontrolPLLnot_S       : std_logic := '1';
+signal clockmodule_locked_S   : std_logic;
+signal reset_S                : std_logic := '0';
+signal reset_FEE_S            : std_logic;
+signal reset_FEE_ADCclk_S     : std_logic := '0';
+signal reset_rxSodaClk_S      : std_logic;
+signal startupready_S         : std_logic;
+signal request_init_S         : std_logic := '0';
+signal GEO_S                  : std_logic := '0';
+signal GEObuf_S               : std_logic := '0';
+signal T_CTRL_S               : std_logic := '0';
+signal S_CTRL_S               : std_logic := '0';
+signal enable_waveform_S      : std_logic;
+
+-- PLL
+signal CLKu_S                 : std_logic;
+signal DATAu_S                : std_logic;
+signal LEu_S                  : std_logic;
+signal RDu_S                  : std_logic;
+signal SYNC_S                 : std_logic;
+signal pll_boot_s             : std_logic;
+signal pll_boot1_s            : std_logic;
+signal PLL_booting_busy_S     : std_logic;
+
+signal PLLuseGTXclock_S       : std_logic;
+signal PLLuseGTXclock0_S      : std_logic;
+signal PLLuseGTXclock1_S      : std_logic;
+signal clockswitch_locked_S   : std_logic;
+signal clockswitch_reset_S    : std_logic;
+
+
+-- system monitor
+signal sysmon_data_S          : std_logic_vector(15 downto 0);
+signal sysmon_reset_S         : std_logic;
+signal sysmon_address_S       : std_logic_vector(6 downto 0);
+signal sysmon_read_S          : std_logic;
+
+signal TEMP_OUT_S             : std_logic := '0';
+signal TEMP_IN_S              : std_logic := '0';
+
+-- SODA
+signal EnableDataTaking_S     : std_logic := '0';
+signal DisableDataTaking_S    : std_logic := '0';
+signal enable_data_S          : std_logic := '0';
+signal DataTaking_enabled_out_S : std_logic := '0';
+signal DataTaking_enabled_in_S  : std_logic := '0';
+signal SODA_cmd_valid_S       : std_logic := '0';
+signal SODA_cmd_word_S        : std_logic_vector(30 downto 0);
+signal superburst_out0_S      : std_logic_vector(30 downto 0);
+signal superburst_out_S       : std_logic_vector(15 downto 0);
+signal superburst_startout0_S : std_logic;
+signal superburst_startout_S  : std_logic;
+signal superburst0_in_S       : std_logic_vector(15 downto 0);
+signal superburst_in_S        : std_logic_vector(30 downto 0);
+signal superburst_start_S     : std_logic;
+signal superburst_startin0_S  : std_logic;
+signal superburst_startin0sync_S  : std_logic;
+signal clear_superburst_startin_S  : std_logic;
+signal superburst_startin1_S  : std_logic;
+signal superburst_startin2_S  : std_logic;
+signal superburst_startin3_S  : std_logic;
+		
+signal force_hit_S            : std_logic;
+signal force_hit_out0_S       : std_logic;
+signal force_hit_out_S        : std_logic;		
+
+-- ADCs
+signal SCK_S                  : std_logic;
+signal SDI_S                  : std_logic;
+signal CSA_S                  : std_logic_vector(1 to 4);
+signal CSB_S                  : std_logic_vector(1 to 4);
+signal SDOA_S                 : std_logic_vector(1 to 4);
+signal SDOB_S                 : std_logic_vector(1 to 4);
+signal ADCchip_init_S         : std_logic;
+signal ADCchip_init1_S        : std_logic;
+signal reset_ADCs_S           : std_logic;
+signal reset_ADCs0_S          : std_logic;
+signal reset_ADCs1_S          : std_logic;
+signal adcdata_S              : array_adc_type;
+signal ADCs_enable_S          : std_logic;
+signal ADCs_ready_S           : std_logic;
+
+-- gtx
+signal GTX_reset_S            : std_logic;
+signal LOS_S                  : std_logic;
+signal LOS_GEO_S              : std_logic;
+signal rxUsrClkdiv2_S         : std_logic;
+signal rxSodaClk_S            : std_logic;
+signal rxSodaClk40_S          : std_logic;
+signal rxSodaClk80_S          : std_logic;
+signal TX_DLM_S               : std_logic;
+signal TX_DLM_WORD_S          : std_logic_vector(7 downto 0);   
+signal RX_DLM_S               : std_logic;
+signal RX_DLM_WORD_S          : std_logic_vector(7 downto 0);
+signal disable_GTX_reset_S    : std_logic := '0';
+signal GTX_txLocked_S         : std_logic;
+signal GTX_txLocked_GEO_S     : std_logic;
+signal GTX_rxLocked_S         : std_logic;
+signal GTX_rxLocked_GEO_S     : std_logic;
+signal GTX_rxclockLocked_S    : std_logic;
+signal GTX_Error_S            : std_logic;
+signal GTX_Error_GEO_S        : std_logic;
+
+-- gtx common
+signal refclk_S               : std_logic;
+signal gt0_qplllock_S         : std_logic;
+signal gt0_qplloutclk_S       : std_logic;
+signal gt0_qplloutrefclk_S    : std_logic;
+signal gt0_qpllrefclklost_S   : std_logic;
+signal gt0_qpllreset_S        : std_logic;
+		
+-- FE output data
+signal FE_in_data_S           : std_logic_vector(31 downto 0);
+signal FE_out_data_S          : std_logic_vector(31 downto 0);
+signal FE_in_present_S        : std_logic;
+signal FE_in_read_S           : std_logic;
+signal FE_out_first_S         : std_logic;
+signal FE_out_last_S          : std_logic;
+signal FE_out_write_S         : std_logic;
+signal FE_out_inpipe_S        : std_logic;
+signal FE_out_fifofull_S      : std_logic;
+
+-- fiber data
+signal packet_out_clock_S     : std_logic;
+signal packet_in_data_S       : std_logic_vector(31 downto 0);
+signal packet_out_data_S      : std_logic_vector(31 downto 0);
+signal packet_in_present_S    : std_logic;
+signal packet_in_read_S       : std_logic;
+signal packet_in_first_S      : std_logic;
+signal packet_in_last_S       : std_logic;
+signal packet_out_first_S     : std_logic;
+signal packet_out_last_S      : std_logic;
+signal packet_out_write_S     : std_logic;
+signal packet_out_fifofull_S  : std_logic;
+signal rxNotInTable_S         : std_logic;
+signal errorbyte_S            : std_logic_vector(7 downto 0) := (others => '0');
+
+-- SEM
+signal doreboot_S              : std_logic := '0';
+signal status_heartbeat_S      : std_logic;
+signal status_initialization_S : std_logic;
+signal status_observation_S    : std_logic;
+signal status_correction_S     : std_logic;
+signal status_classification_S : std_logic;
+signal status_injection_S      : std_logic;
+signal status_essential_S      : std_logic;
+signal status_uncorrectable_S  : std_logic;
+
+-- interconnection
+signal aurora_clock_S          : std_logic;
+signal aurora_tx_data_S        : std_logic_vector(31 downto 0);
+signal aurora_tx_allowed_S     : std_logic;
+signal aurora_tx_first_S       : std_logic;
+signal aurora_tx_last_S        : std_logic;
+signal aurora_tx_write_S       : std_logic;
+signal aurora_tx_inpipe_S      : std_logic;
+signal aurora_rx_data_S        : std_logic_vector(31 downto 0);
+signal aurora_rx_first_S       : std_logic;
+signal aurora_rx_last_S        : std_logic;
+signal aurora_rx_write_S       : std_logic;
+signal aurora_rx_almostfull_S  : std_logic;
+signal aurora_rx_inpipe_S      : std_logic;
+signal aurora_locked_S         : std_logic;
+signal aurora_error_S          : std_logic;
+
+-- split received data
+signal split_in_S              : std_logic_vector(31 downto 0);
+signal split_in_first_S        : std_logic;
+signal split_in_last_S         : std_logic;
+signal split_in_present_S      : std_logic;
+signal split_in_fifofull_S     : std_logic;
+signal split_in_read_S         : std_logic;
+signal split_local_S           : std_logic_vector(31 downto 0);
+signal split_local_first_S     : std_logic;
+signal split_local_last_S      : std_logic;
+signal split_local_present_S   : std_logic;
+signal split_local_read_S      : std_logic;
+signal split_remote_S          : std_logic_vector(31 downto 0);
+signal split_remote_first_S    : std_logic;
+signal split_remote_last_S     : std_logic;
+signal split_remote_present_S  : std_logic;
+signal split_remote_read_S     : std_logic;
+signal split_error_S           : std_logic;
+
+-- combine FE data
+signal comb_local_S              : std_logic_vector(31 downto 0);
+signal comb_local_first_S        : std_logic;
+signal comb_local_last_S         : std_logic;
+signal comb_local_write_S        : std_logic;
+signal comb_local_inpipe_S       : std_logic;
+signal comb_local_fifofull_S     : std_logic;
+signal comb_remote_S             : std_logic_vector(31 downto 0);
+signal comb_remote_first_S       : std_logic;
+signal comb_remote_last_S        : std_logic;
+signal comb_remote_write_S       : std_logic;
+signal comb_remote_inpipe_S      : std_logic;
+signal comb_remote_fifofull_S    : std_logic;
+signal comb_remote_almostfull_S  : std_logic;
+signal comb_out_S                : std_logic_vector(31 downto 0);
+signal comb_out_first_S          : std_logic;
+signal comb_out_last_S           : std_logic;
+signal comb_out_write_S          : std_logic;
+signal comb_out_inpipe_S         : std_logic;
+signal comb_out_fifofull_S       : std_logic;
+signal comb_error_S              : std_logic;
+	
+signal split_remote_wr_S         : std_logic_vector(31 downto 0);
+signal split_remote_wr_first_S   : std_logic;
+signal split_remote_wr_last_S    : std_logic;
+signal split_remote_wr_write_S   : std_logic;
+signal split_remote_wr_allowed_S : std_logic;
+signal split_remote_fifoempty_S  : std_logic;
+
+signal gt0_qpllreset1_S          : std_logic;
+signal gt0_qpllreset2_S          : std_logic;
+
+-- test compare feature extraction results
+signal vioword_S              : std_logic_vector(35 downto 0) := (others => '0');
+signal compare_error_S        : std_logic;
+signal compare_error1_S       : std_logic;
+		
+attribute keep                   : string;
+attribute keep of clock_S  : signal is "TRUE";
+attribute keep of ADC_clk_S  : signal is "TRUE";
+--attribute keep of clock100MHz_S  : signal is "TRUE";
+attribute keep of clock200MHz_S  : signal is "TRUE";
+attribute keep of async_clock_S  : signal is "TRUE";
+
+-- test
+
+-- signal aurora1_txclock_Sdiv10_S      : std_logic;
+-- signal aurora1_rxclock_Sdiv10_S      : std_logic;
+-- signal aurora2_txclock_Sdiv10_S      : std_logic;
+-- signal aurora2_rxclock_Sdiv10_S      : std_logic;
+
+--signal vio_LMK04806_wr0_S      : std_logic;
+--signal vio_LMK04806_wr_S       : std_logic;
+signal debug_reset_S             : std_logic := '0';
+
+signal debug_packet_out_data_S   : std_logic_vector(31 downto 0);
+signal debug_packet_out_first_S  : std_logic;
+signal debug_packet_out_last_S   : std_logic;
+
+attribute mark_debug : string;
+-- attribute mark_debug of GEO_S : signal is "true";
+-- attribute mark_debug of T_CTRL_S : signal is "true";
+-- attribute mark_debug of S_CTRL_S : signal is "true";
+-- attribute mark_debug of reset_S : signal is "true";
+-- attribute mark_debug of clockmodule_locked_S : signal is "true";
+-- attribute mark_debug of IcontrolPLL_S : signal is "true";
+-- attribute mark_debug of ADCchip_init_S : signal is "true";
+-- attribute mark_debug of PLL_boot_S : signal is "true";
+-- attribute mark_debug of PLL_booting_busy_S : signal is "true";
+-- attribute mark_debug of GTX_reset_S : signal is "true";
+-- attribute mark_debug of LOS_GEO_S : signal is "true";
+-- attribute mark_debug of GTX_rxclockLocked_S : signal is "true";
+-- attribute mark_debug of GTX_txLocked_GEO_S : signal is "true";
+-- attribute mark_debug of GTX_Error_GEO_S : signal is "true";
+-- attribute mark_debug of PLLuseGTXclock_S : signal is "true";
+-- attribute mark_debug of PLLuseGTXclock0_S : signal is "true";
+-- attribute mark_debug of reset_ADCs_S : signal is "true";
+-- attribute mark_debug of ADCs_ready_S : signal is "true";
+-- attribute mark_debug of reset_FEE_S : signal is "true";
+-- attribute mark_debug of startupready_S : signal is "true";
+-- attribute mark_debug of reset_rxSodaClk_S : signal is "true";
+
+-- attribute mark_debug of status_heartbeat_S : signal is "true";
+-- attribute mark_debug of status_initialization_S : signal is "true";
+-- attribute mark_debug of status_observation_S : signal is "true";
+-- attribute mark_debug of status_correction_S : signal is "true";
+-- attribute mark_debug of status_classification_S : signal is "true";
+-- attribute mark_debug of status_injection_S : signal is "true";
+-- attribute mark_debug of status_essential_S : signal is "true";
+-- attribute mark_debug of status_uncorrectable_S : signal is "true";
+-- attribute mark_debug of doreboot_S : signal is "true";
+
+-- attribute mark_debug of LOS : signal is "true";
+-- attribute mark_debug of INTCOMC1_P : signal is "true";
+-- attribute mark_debug of INTCOMC1_N : signal is "true";
+-- attribute mark_debug of INTCOMC2_P : signal is "true";
+-- attribute mark_debug of INTCOMC2_N : signal is "true";
+
+
+-- attribute mark_debug of FE_in_data_S : signal is "true";
+-- attribute mark_debug of FE_in_present_S : signal is "true";
+-- attribute mark_debug of FE_in_read_S : signal is "true";
+-- attribute mark_debug of FE_out_data_S : signal is "true";
+-- attribute mark_debug of FE_out_first_S : signal is "true";
+-- attribute mark_debug of FE_out_last_S : signal is "true";
+-- attribute mark_debug of FE_out_write_S : signal is "true";
+-- attribute mark_debug of FE_out_inpipe_S : signal is "true";
+-- attribute mark_debug of FE_out_fifofull_S : signal is "true";
+
+-- attribute mark_debug of aurora_tx_data_S : signal is "true";
+-- attribute mark_debug of aurora_tx_write_S : signal is "true";
+-- attribute mark_debug of aurora_tx_allowed_S : signal is "true";
+-- attribute mark_debug of aurora_rx_data_S : signal is "true";
+-- attribute mark_debug of aurora_rx_write_S : signal is "true";
+-- attribute mark_debug of aurora_locked_S : signal is "true";
+-- attribute mark_debug of aurora_error_S : signal is "true";
+
+-- attribute mark_debug of packet_in_data_S : signal is "true";
+-- attribute mark_debug of packet_in_first_S : signal is "true";
+-- attribute mark_debug of packet_in_last_S : signal is "true";
+-- attribute mark_debug of packet_in_read_S : signal is "true";
+-- attribute mark_debug of packet_in_present_S : signal is "true";
+-- attribute mark_debug of packet_out_data_S : signal is "true";
+-- attribute mark_debug of packet_out_write_S : signal is "true";
+-- attribute mark_debug of packet_out_first_S : signal is "true";
+-- attribute mark_debug of packet_out_last_S : signal is "true";
+-- attribute mark_debug of packet_out_fifofull_S : signal is "true";
+
+--attribute mark_debug of debug_packet_out_data_S : signal is "true";
+--attribute mark_debug of debug_packet_out_first_S : signal is "true";
+--attribute mark_debug of debug_packet_out_last_S : signal is "true";
+-- attribute mark_debug of superburst_out_S : signal is "true";
+-- attribute mark_debug of superburst_startout0_S : signal is "true";
+-- attribute mark_debug of superburst_startout_S : signal is "true";
+-- attribute mark_debug of superburst0_in_S : signal is "true";
+-- attribute mark_debug of superburst_in_S : signal is "true";
+-- attribute mark_debug of superburst_start_S : signal is "true";
+-- attribute mark_debug of superburst_startin0_S : signal is "true";
+-- attribute mark_debug of superburst_startin0sync_S : signal is "true";
+-- attribute mark_debug of clear_superburst_startin_S : signal is "true";
+-- attribute mark_debug of superburst_startin1_S : signal is "true";
+-- attribute mark_debug of superburst_startin2_S : signal is "true";
+-- attribute mark_debug of superburst_startin3_S : signal is "true";
+
+begin
+
+-- IO buffers ------------------------------------------------	
+T_CTRL_inst : OBUF port map(O => T_CTRL,I => T_CTRL_S);
+S_CTRL_inst : IBUF port map (O => S_CTRL_S, I => S_CTRL);
+GEO_inst : IBUF port map (O => GEObuf_S, I => GEO);
+RDu_inst : IBUF port map (O => RDu_S, I => RDu);
+
+GEO_S <= GEObuf_S when SWAPFPGAS=false else not GEObuf_S;
+
+
+--IOBUF1 : IOBUF port map (O => PLLuseGTXclock0_S, IO => INTCOMC1_P, I => PLLuseGTXclock_S, T => IcontrolPLLnot_S);
+--IOBUF2 : IOBUF port map (O => superburst_start0_S, IO => INTCOMC1_N, I => superburst_startout_S, T => IcontrolPLLnot_S);	
+--IOBUF3 : IOBUF port map (O => DataTaking_enabled_in_S, IO => INTCOMC2_N, I => DataTaking_enabled_out_S, T => IcontrolPLLnot_S);	
+--IOBUF4 : IOBUF port map (O => open, IO => CLKu, I => CLKu_S, T => IcontrolPLLnot_S);    
+--IOBUF5 : IOBUF port map (O => open, IO => DATAu, I => DATAu_S, T => IcontrolPLLnot_S);    
+--IOBUF6 : IOBUF port map (O => open, IO => LEu, I => LEu_S, T => IcontrolPLLnot_S);    
+		
+INTCOMC1_P <= PLLuseGTXclock_S when IcontrolPLLnot_S='0' else 'Z';
+PLLuseGTXclock0_S <= INTCOMC1_P;
+
+INTCOMC1_N <= superburst_startout_S when IcontrolPLLnot_S='0' else 'Z';
+superburst_startin0_S <= INTCOMC1_N;
+
+INTCOMC2_N <= DataTaking_enabled_out_S when IcontrolPLLnot_S='0' else 'Z';
+DataTaking_enabled_in_S <= INTCOMC2_N;
+
+INTCOMC2_P <= force_hit_out_S when IcontrolPLLnot_S='0' else 'Z';
+force_hit_S <= INTCOMC2_P;
+
+CLKu <= CLKu_S when IcontrolPLLnot_S='0' else 'Z';
+DATAu <= DATAu_S when IcontrolPLLnot_S='0' else 'Z';
+LEu <= LEu_S when IcontrolPLLnot_S='0' else 'Z';
+SYNC <= SYNC_S when IcontrolPLLnot_S='0' else 'Z';
+
+JTAG_IOBUF1 : IOBUF port map (
+	  O => open, 
+	  IO => JTAG_OUT1_TCK_F,
+	  I => '0',
+	  T => '1'
+   ); 
+JTAG_IOBUF2 : IOBUF port map (
+	  O => open, 
+	  IO => JTAG_OUT1_TDI_F,
+	  I => '0',
+	  T => '1'
+   ); 
+JTAG_IOBUF3 : IOBUF port map (
+	  O => open, 
+	  IO => JTAG_OUT1_TDO_F,
+	  I => '0',
+	  T => '1'
+   ); 
+JTAG_IOBUF4 : IOBUF port map (
+	  O => open, 
+	  IO => JTAG_OUT1_TMS_F,
+	  I => '0',
+	  T => '1'
+   ); 
+
+TEMP_OUT_S <= TEMP_OUT;
+TEMP_IN <= TEMP_IN_S;
+
+
+--SCK <= SCK_S;
+--SDI <= SDI_S;
+--CSA <= CSA_S;
+--CSB <= CSB_S;
+SDOA_S <= SDOA;
+SDOB_S <= SDOB;
+
+SCK_inst : OBUF port map(O => SCK,I => SCK_S);
+SDI_inst : OBUF port map(O => SDI,I => SDI_S);
+CSA1_inst : OBUF port map(O => CSA(1),I => CSA_S(1));
+CSA2_inst : OBUF port map(O => CSA(2),I => CSA_S(2));
+CSA3_inst : OBUF port map(O => CSA(3),I => CSA_S(3));
+CSA4_inst : OBUF port map(O => CSA(4),I => CSA_S(4));
+CSB1_inst : OBUF port map(O => CSB(1),I => CSB_S(1));
+CSB2_inst : OBUF port map(O => CSB(2),I => CSB_S(2));
+CSB3_inst : OBUF port map(O => CSB(3),I => CSB_S(3));
+CSB4_inst : OBUF port map(O => CSB(4),I => CSB_S(4));
+--
+--GEN_SDO_parallel: if ADC_PARALLELINIT=true generate
+--   SDOA1_inst : OBUF port map (O => SDOA(1), I => SDOA_S(1));
+--   SDOA2_inst : OBUF port map (O => SDOA(2), I => SDOA_S(2));
+--   SDOA3_inst : OBUF port map (O => SDOA(3), I => SDOA_S(3));
+--   SDOA4_inst : OBUF port map (O => SDOA(4), I => SDOA_S(4));
+--   SDOB1_inst : OBUF port map (O => SDOB(1), I => SDOB_S(1));
+--   SDOB2_inst : OBUF port map (O => SDOB(2), I => SDOB_S(2));
+--   SDOB3_inst : OBUF port map (O => SDOB(3), I => SDOB_S(3));
+--   SDOB4_inst : OBUF port map (O => SDOB(4), I => SDOB_S(4));
+--end generate;
+--GEN_SDO_serial: if ADC_PARALLELINIT=false generate
+--   SDOA1_inst : IBUF port map (O => SDOA_S(1), I => SDOA(1));
+--   SDOA2_inst : IBUF port map (O => SDOA_S(2), I => SDOA(2));
+--   SDOA3_inst : IBUF port map (O => SDOA_S(3), I => SDOA(3));
+--   SDOA4_inst : IBUF port map (O => SDOA_S(4), I => SDOA(4));
+--   SDOB1_inst : IBUF port map (O => SDOB_S(1), I => SDOB(1));
+--   SDOB2_inst : IBUF port map (O => SDOB_S(2), I => SDOB(2));
+--   SDOB3_inst : IBUF port map (O => SDOB_S(3), I => SDOB(3));
+--   SDOB4_inst : IBUF port map (O => SDOB_S(4), I => SDOB(4));
+--end generate;
+
+
+--GEN_SDO_parallel: if ADC_PARALLELINIT=true generate
+--   SDOA1_inst : IOBUF port map (O => open, IO => SDOA(1), I => SDOA_S(1), T => '0');
+--   SDOA2_inst : IOBUF port map (O => open, IO => SDOA(2), I => SDOA_S(2), T => '0');
+--   SDOA3_inst : IOBUF port map (O => open, IO => SDOA(3), I => SDOA_S(3), T => '0');
+--   SDOA4_inst : IOBUF port map (O => open, IO => SDOA(4), I => SDOA_S(4), T => '0');
+--   SDOB1_inst : IOBUF port map (O => open, IO => SDOB(1), I => SDOB_S(1), T => '0');
+--   SDOB2_inst : IOBUF port map (O => open, IO => SDOB(2), I => SDOB_S(2), T => '0');
+--   SDOB3_inst : IOBUF port map (O => open, IO => SDOB(3), I => SDOB_S(3), T => '0');
+--   SDOB4_inst : IOBUF port map (O => open, IO => SDOB(4), I => SDOB_S(4), T => '0');
+--end generate;
+--GEN_SDO_serial: if ADC_PARALLELINIT=false generate
+--   SDOA1_inst : IOBUF port map (O => SDOA_S(1), IO => SDOA(1), I => '0', T => '1');
+--   SDOA2_inst : IOBUF port map (O => SDOA_S(2), IO => SDOA(2), I => '0', T => '1');
+--   SDOA3_inst : IOBUF port map (O => SDOA_S(3), IO => SDOA(3), I => '0', T => '1');
+--   SDOA4_inst : IOBUF port map (O => SDOA_S(4), IO => SDOA(4), I => '0', T => '1');
+--   SDOB1_inst : IOBUF port map (O => SDOB_S(1), IO => SDOB(1), I => '0', T => '1');
+--   SDOB2_inst : IOBUF port map (O => SDOB_S(2), IO => SDOB(2), I => '0', T => '1');
+--   SDOB3_inst : IOBUF port map (O => SDOB_S(3), IO => SDOB(3), I => '0', T => '1');
+--   SDOB4_inst : IOBUF port map (O => SDOB_S(4), IO => SDOB(4), I => '0', T => '1');
+--end generate;
+
+
+-- process(clock_S,clockmodule_locked_S,GEO_S)
+-- variable T_CTRL_count_V : integer range 0 to 3 := 0;
+-- begin
+	-- if (clockmodule_locked_S='0') then
+		-- T_CTRL_S <= GEO_S;
+	-- elsif (rising_edge(clock_S)) then
+		-- if GEO_S='0' then
+			-- if (FPGA_IN_CONTROL='0') then
+				-- if (S_CTRL_S='0') and (T_CTRL_count_V=3) then -- wrong value
+					-- T_CTRL_S <= not T_CTRL_S;
+					-- T_CTRL_count_V := 0;
+				-- elsif T_CTRL_count_V/=3 then
+					-- T_CTRL_count_V := T_CTRL_count_V+1;
+				-- end if;					
+			-- else
+				-- T_CTRL_S <= GEO_S;
+			-- end if;
+		-- else
+			-- if (FPGA_IN_CONTROL='1') then
+				-- if (S_CTRL_S='1') and (T_CTRL_count_V=3) then -- wrong value
+					-- T_CTRL_S <= not T_CTRL_S;
+					-- T_CTRL_count_V := 0;
+				-- elsif T_CTRL_count_V/=3 then
+					-- T_CTRL_count_V := T_CTRL_count_V+1;
+				-- end if;					
+			-- else
+				-- T_CTRL_S <= GEO_S;
+			-- end if;
+		-- end if;
+	-- end if;
+-- end process;
+T_CTRL_S <= '0';
+
+--IcontrolPLL_S <= '1' when (GEO='0') and (S_CTRL='1') else '0';
+--IcontrolPLL_S <= '1' when ((GEO_S='0') and (S_CTRL_S='1')) or ((GEO_S='1') and (S_CTRL_S='0')) else '0';
+
+IcontrolPLL_S <= '1' when (GEO_S='0') else '0';
+IcontrolPLLnot_S <= '0' when (GEO_S='0') else '1';
+
+-- process(clock_S,clockmodule_locked_S)
+-- begin
+	-- if clockmodule_locked_S='0' then
+		-- IcontrolPLLnot_S <= '1';
+	-- elsif (rising_edge(clock_S)) then 
+		-- IcontrolPLLnot_S <= not IcontrolPLL_S;
+	-- end if;
+-- end process;
+
+-- main reset -----------------------------------------------
+process(clock_S,clockmodule_locked_S,debug_reset_S)
+variable S_CTRL_V : std_logic := '0';
+variable count_V : std_logic_vector(5 downto 0) := (others => '0');
+begin
+	if (clockmodule_locked_S='0') or (debug_reset_S='1') then
+		reset_S <= '1';
+		count_V := (others => '0');
+	elsif (rising_edge(clock_S)) then 
+		if S_CTRL_V/=S_CTRL_S then
+			reset_S <= '1';
+			count_V := (others => '0');
+		else
+			if (count_V(count_V'left)='1') then
+				reset_S <= '0';
+			else
+				count_V := count_V+1;
+				reset_S <= '1';
+			end if;
+		end if;
+		S_CTRL_V := S_CTRL_S;
+	end if;
+end process;
+
+
+-- main clock -----------------------------------------------
+
+clockmodule100Mto80Ma: clockmodule100to80M port map(
+		CLK_IN1 => SYS_CLK,
+		CLK_OUT1 => clock40MHz_S,
+		CLK_OUT2 => clock_S, -- 80MHz
+		CLK_OUT3 => clock100MHz_S,
+		CLK_OUT4 => clock200MHz_S,
+		CLK_OUT5 => async_clock_S,
+		CLK_OUT6 => clock160MHz_S,
+		RESET => '0',
+		LOCKED => clockmodule_locked_S);
+		
+sysclk_buf : IBUFGDS
+	generic map(
+		IOSTANDARD => "LVDS"
+	)
+	port map (	
+		I	=>	GCLK_P,
+		IB	=>	GCLK_N,
+		O	=>	gclk_S
+	);
+
+--gclk_S <= GCLK_P; -- when GEO_S='0' else clock_S; --// assign fixed clock to gclk due to hardware error?
+
+
+
+-- clock to external PLL LMK04806 -------------------------------------
+
+	  
+select_RCV_CLK : BUFGMUX 
+	generic map (
+		CLK_SEL_TYPE => "ASYNC" --//ASYNC
+	)
+	port map( --
+      O => RCV_CLK_S,
+      I0 => clock_S, -- clock40MHz_S, -- clock_S,
+      I1 => rxSodaClk80_S, --clock40MHz_S, -- clock_S, -- rxSodaClk40_S,
+      S => PLLuseGTXclock1_S);
+PLLuseGTXclock1_S <= PLLuseGTXclock_S when IcontrolPLLnot_S='0' else '0';
+
+clockmodule40Mto80M1: clockmodule40Mto80M port map( 
+		CLK_IN1 => rxSodaClk40_S,
+		CLK_OUT1 => open,
+		CLK_OUT2 => rxSodaClk80_S, -- RCV_CLK_S,
+		RESET => IcontrolPLLnot_S,
+		LOCKED => clockswitch_locked_S);
+
+process(clock_S,reset_S)
+variable GTX_rxLocked_V : std_logic;
+variable timer_V : std_logic_vector(3 downto 0);
+begin
+	if reset_S='1' then
+		GTX_rxclockLocked_S <= '0';
+		timer_V := (others => '0');
+	elsif (rising_edge(clock_S)) then 
+		if ((GTX_rxLocked_GEO_S='1') and (GTX_rxLocked_V='0')) then
+			timer_V := (others => '0');
+			GTX_rxclockLocked_S <= '0';
+		else
+			if timer_V(timer_V'left)='0' then
+				timer_V := timer_V+1;
+				GTX_rxclockLocked_S <= '0';
+			else
+				if (GTX_rxLocked_GEO_S='1') and ((clockswitch_locked_S='1') or (IcontrolPLLnot_S='1')) then
+					GTX_rxclockLocked_S <= '1';
+				else
+					GTX_rxclockLocked_S <= '0';
+				end if;
+			end if;
+		end if;
+		GTX_rxLocked_V := GTX_rxLocked_GEO_S;
+	end if;
+end process;
+
+--sends clock to PLL
+OBUFDS_inst : OBUFDS
+	generic map(
+		IOSTANDARD => "LVDS_25")
+	port map( 
+		O  => RCV_CLK_P,
+		OB => RCV_CLK_N,
+		I  => RCV_CLK_S);
+		
+		
+-- external PLL LMK04806 -------------------------------------
+LMK04806_1: LMK04806 port map(
+		clock => clock_S,
+		reset => reset_S,
+		CLKu => CLKu_S,
+		DATAu => DATAu_S,
+		LEu => LEu_S,
+		RDu => RDu_S,
+		SYNC => SYNC_S,
+		boot_PLL => PLL_boot_S,
+		booting => PLL_booting_busy_S);
+PLL_boot1_S <= '1' when (PLL_boot_S='1') else '0';
+
+SystemMonitorModule1: SystemMonitorModule port map(
+		clock => ADC_clk_S,
+		reset => sysmon_reset_S,
+		address => sysmon_address_S,
+		data_write => '0',
+		data_in => (others => '0'),
+		data_read => sysmon_read_S,
+		data_out => sysmon_data_S,
+		alarms => open);
+		
+-- startup ----------------------------------------------------		
+FEE_startup1: FEE_startup port map(
+		clock => clock_S,
+		ADCclock => ADC_clk_S,
+		clock_from_PLL => gclk_S,
+		reset => reset_S,
+		GEO => GEO_S,
+		IcontrolPLL => IcontrolPLL_S,
+		ADCchip_init => ADCchip_init_S,
+		PLL_init => PLL_boot_S,
+		PLL_booting => PLL_booting_busy_S,
+		GTX_reset => GTX_reset_S,
+		GTX_LOS => LOS_GEO_S,
+		GTX_rxLocked => GTX_rxclockLocked_S, --GTX_rxLocked_S,
+		GTX_txLocked => GTX_txLocked_GEO_S,
+		GTX_error => GTX_Error_GEO_S,
+		PLLuseGTXclock => PLLuseGTXclock_S,
+		PLL_locked => PLLuseGTXclock0_S,
+		ADCs_reset => reset_ADCs_S,
+		ADCs_ready => ADCs_ready_S,
+		FEE_reset => reset_FEE_S,
+		startupready => startupready_S
+		);
+   
+-- ADC configuration (PARALLEL or SERIAL)--------------------------------------------------------------
+
+gen_adcparallelprog: if ADC_PARALLELINIT=true generate
+	 SCK_S <= '0'; -- 2-lane 16-bits serialization
+	 SDI_S <= '0'; -- normal mode (not sleeping)
+	 CSA_S <= (others => '0'); -- 2-lane 16-bits serialization
+	 CSB_S <= (others => '0'); -- 2-lane 16-bits serialization
+	 SDOA_S <= (others => '0'); -- no internal termination
+	 SDOB_S <= (others => '0'); -- no internal termination
+end generate;
+
+gen_adcserialprog: if ADC_PARALLELINIT=false generate
+AdcSerialProg1: AdcSerialProg port map(
+		clock => clock_S,
+		reset => reset_S,
+		init => ADCchip_init1_S,
+		clock_out => SCK_S,
+		dataA_in(0) => SDOA_S(1),
+		dataA_in(1) => SDOA_S(2),
+		dataA_in(2) => SDOA_S(3),
+		dataA_in(3) => SDOA_S(4),
+		dataB_in(0) => SDOB_S(1),
+		dataB_in(1) => SDOB_S(2),
+		dataB_in(2) => SDOB_S(3),
+		dataB_in(3) => SDOB_S(4),
+		data_out => SDI_S,
+		chipnselectA(0) => CSA_S(1),
+		chipnselectA(1) => CSA_S(2),
+		chipnselectA(2) => CSA_S(3),
+		chipnselectA(3) => CSA_S(4),
+		chipnselectB(0) => CSB_S(1),
+		chipnselectB(1) => CSB_S(2),
+		chipnselectB(2) => CSB_S(3),
+		chipnselectB(3) => CSB_S(4),
+		selREGS => (others => '0') 
+		);
+ADCchip_init1_S <= '1' when (ADCchip_init_S='1') else '0';
+end generate;
+
+-- ADC inputs ----------------------------------------------------------------------
+reset_ADCs1_S <= '1' when (reset_ADCs_S='1') else '0';
+
+FEE_ADCinput_module1: FEE_ADCinput_module port map(
+		clock200MHz => clock200MHz_S,
+		clock80MHz => clock_S,
+		clockAsync => async_clock_S,
+		reset => reset_ADCs1_S,
+		ADCs_enable => ADCs_enable_S,
+----ADC1---------------------------------------------		
+		AD11A_P => AD11A_P,
+		AD11A_N => AD11A_N,
+		AD11B_P => AD11B_P,
+		AD11B_N => AD11B_N,
+		AD12A_P => AD12A_P,
+		AD12A_N => AD12A_N,
+		AD12B_P => AD12B_P,
+		AD12B_N => AD12B_N,
+		AD13A_P => AD13A_P,
+		AD13A_N => AD13A_N,
+		AD13B_P => AD13B_P,
+		AD13B_N => AD13B_N,
+		AD14A_P => AD14A_P,
+		AD14A_N => AD14A_N,
+		AD14B_P => AD14B_P,
+		AD14B_N => AD14B_N,
+		AD15A_P => AD15A_P,
+		AD15A_N => AD15A_N,
+		AD15B_P => AD15B_P,
+		AD15B_N => AD15B_N,
+		AD16A_P => AD16A_P,
+		AD16A_N => AD16A_N,
+		AD16B_P => AD16B_P,
+		AD16B_N => AD16B_N,
+		AD17A_P => AD17A_P,
+		AD17A_N => AD17A_N,
+		AD17B_P => AD17B_P,
+		AD17B_N => AD17B_N,
+		AD18A_P => AD18A_P,
+		AD18A_N => AD18A_N,
+		AD18B_P => AD18B_P,
+		AD18B_N => AD18B_N,
+
+		DCOA1_P => DCOA1_P,
+		DCOA1_N => DCOA1_N,
+		DCOB1_P => DCOB1_P,
+		DCOB1_N => DCOB1_N,
+
+		FRA1_P  => FRA1_P ,
+		FRA1_N  => FRA1_N ,
+		FRB1_P  => FRB1_P ,
+		FRB1_N  => FRB1_N ,
+
+		----ADC2---------------------------------------------
+		AD21A_P => AD21A_P,
+		AD21A_N => AD21A_N,
+		AD21B_P => AD21B_P,
+		AD21B_N => AD21B_N,
+		AD22A_P => AD22A_P,
+		AD22A_N => AD22A_N,
+		AD22B_P => AD22B_P,
+		AD22B_N => AD22B_N,
+		AD23A_P => AD23A_P,
+		AD23A_N => AD23A_N,
+		AD23B_P => AD23B_P,
+		AD23B_N => AD23B_N,
+		AD24A_P => AD24A_P,
+		AD24A_N => AD24A_N,
+		AD24B_P => AD24B_P,
+		AD24B_N => AD24B_N,
+		AD25A_P => AD25A_P,
+		AD25A_N => AD25A_N,
+		AD25B_P => AD25B_P,
+		AD25B_N => AD25B_N,
+		AD26A_P => AD26A_P,
+		AD26A_N => AD26A_N,
+		AD26B_P => AD26B_P,
+		AD26B_N => AD26B_N,
+		AD27A_P => AD27A_P,
+		AD27A_N => AD27A_N,
+		AD27B_P => AD27B_P,
+		AD27B_N => AD27B_N,
+		AD28A_P => AD28A_P,
+		AD28A_N => AD28A_N,
+		AD28B_P => AD28B_P,
+		AD28B_N => AD28B_N,
+
+		DCOA2_P => DCOA2_P,
+		DCOA2_N => DCOA2_N,
+		DCOB2_P => DCOB2_P,
+		DCOB2_N => DCOB2_N,
+
+		FRA2_P  => FRA2_P ,
+		FRA2_N  => FRA2_N ,
+		FRB2_P  => FRB2_P ,
+		FRB2_N  => FRB2_N ,
+
+		----ADC3---------------------------------------------
+		AD31A_P => AD31A_P,
+		AD31A_N => AD31A_N,
+		AD31B_P => AD31B_P,
+		AD31B_N => AD31B_N,
+		AD32A_P => AD32A_P,
+		AD32A_N => AD32A_N,
+		AD32B_P => AD32B_P,
+		AD32B_N => AD32B_N,
+		AD33A_P => AD33A_P,
+		AD33A_N => AD33A_N,
+		AD33B_P => AD33B_P,
+		AD33B_N => AD33B_N,
+		AD34A_P => AD34A_P,
+		AD34A_N => AD34A_N,
+		AD34B_P => AD34B_P,
+		AD34B_N => AD34B_N,
+		AD35A_P => AD35A_P,
+		AD35A_N => AD35A_N,
+		AD35B_P => AD35B_P,
+		AD35B_N => AD35B_N,
+		AD36A_P => AD36A_P,
+		AD36A_N => AD36A_N,
+		AD36B_P => AD36B_P,
+		AD36B_N => AD36B_N,
+		AD37A_P => AD37A_P,
+		AD37A_N => AD37A_N,
+		AD37B_P => AD37B_P,
+		AD37B_N => AD37B_N,
+		AD38A_P => AD38A_P,
+		AD38A_N => AD38A_N,
+		AD38B_P => AD38B_P,
+		AD38B_N => AD38B_N,
+
+		DCOA3_P => DCOA3_P,
+		DCOA3_N => DCOA3_N,
+		DCOB3_P => DCOB3_P,
+		DCOB3_N => DCOB3_N,
+
+		FRA3_P  => FRA3_P ,
+		FRA3_N  => FRA3_N ,
+		FRB3_P  => FRB3_P ,
+		FRB3_N  => FRB3_N ,
+
+		----ADC4---------------------------------------------
+		AD41A_P => AD41A_P,
+		AD41A_N => AD41A_N,
+		AD41B_P => AD41B_P,
+		AD41B_N => AD41B_N,
+		AD42A_P => AD42A_P,
+		AD42A_N => AD42A_N,
+		AD42B_P => AD42B_P,
+		AD42B_N => AD42B_N,
+		AD43A_P => AD43A_P,
+		AD43A_N => AD43A_N,
+		AD43B_P => AD43B_P,
+		AD43B_N => AD43B_N,
+		AD44A_P => AD44A_P,
+		AD44A_N => AD44A_N,
+		AD44B_P => AD44B_P,
+		AD44B_N => AD44B_N,
+		AD45A_P => AD45A_P,
+		AD45A_N => AD45A_N,
+		AD45B_P => AD45B_P,
+		AD45B_N => AD45B_N,
+		AD46A_P => AD46A_P,
+		AD46A_N => AD46A_N,
+		AD46B_P => AD46B_P,
+		AD46B_N => AD46B_N,
+		AD47A_P => AD47A_P,
+		AD47A_N => AD47A_N,
+		AD47B_P => AD47B_P,
+		AD47B_N => AD47B_N,
+		AD48A_P => AD48A_P,
+		AD48A_N => AD48A_N,
+		AD48B_P => AD48B_P,
+		AD48B_N => AD48B_N,
+
+		DCOA4_P => DCOA4_P,
+		DCOA4_N => DCOA4_N,
+		DCOB4_P => DCOB4_P,
+		DCOB4_N => DCOB4_N,
+
+		FRA4_P  => FRA4_P ,
+		FRA4_N  => FRA4_N ,
+		FRB4_P  => FRB4_P ,
+		FRB4_N  => FRB4_N ,
+
+		ADC_clk => ADC_clk_S,
+		ADCs_ready => ADCs_ready_S,
+		adcdata => adcdata_S
+		);
+ADCs_enable_S <= '1';
+
+-- Superburst --------------------------------------------------------------
+
+--IOBUF_superburst00: IOBUF port map (O => superburst_in_S(0), IO => INTCOM0_P, I => superburst_out_S(0), T => IcontrolPLLnot_S);
+--IOBUF_superburst01: IOBUF port map (O => superburst_in_S(1), IO => INTCOM0_N, I => superburst_out_S(1), T => IcontrolPLLnot_S);
+--IOBUF_superburst02: IOBUF port map (O => superburst_in_S(2), IO => INTCOM1_P, I => superburst_out_S(2), T => IcontrolPLLnot_S);
+--IOBUF_superburst03: IOBUF port map (O => superburst_in_S(3), IO => INTCOM1_N, I => superburst_out_S(3), T => IcontrolPLLnot_S);
+--IOBUF_superburst04: IOBUF port map (O => superburst_in_S(4), IO => INTCOM2_P, I => superburst_out_S(4), T => IcontrolPLLnot_S);
+--IOBUF_superburst05: IOBUF port map (O => superburst_in_S(5), IO => INTCOM2_N, I => superburst_out_S(5), T => IcontrolPLLnot_S);
+--IOBUF_superburst06: IOBUF port map (O => superburst_in_S(6), IO => INTCOM3_P, I => superburst_out_S(6), T => IcontrolPLLnot_S);
+--IOBUF_superburst07: IOBUF port map (O => superburst_in_S(7), IO => INTCOM3_N, I => superburst_out_S(7), T => IcontrolPLLnot_S);
+--IOBUF_superburst08: IOBUF port map (O => superburst_in_S(8), IO => INTCOM4_P, I => superburst_out_S(8), T => IcontrolPLLnot_S);
+--IOBUF_superburst09: IOBUF port map (O => superburst_in_S(9), IO => INTCOM4_N, I => superburst_out_S(9), T => IcontrolPLLnot_S);
+--IOBUF_superburst10: IOBUF port map (O => superburst_in_S(10), IO => INTCOM5_P, I => superburst_out_S(10), T => IcontrolPLLnot_S);
+--IOBUF_superburst11: IOBUF port map (O => superburst_in_S(11), IO => INTCOM5_N, I => superburst_out_S(11), T => IcontrolPLLnot_S);
+--IOBUF_superburst12: IOBUF port map (O => superburst_in_S(12), IO => INTCOM6_P, I => superburst_out_S(12), T => IcontrolPLLnot_S);
+--IOBUF_superburst13: IOBUF port map (O => superburst_in_S(13), IO => INTCOM6_N, I => superburst_out_S(13), T => IcontrolPLLnot_S);
+--IOBUF_superburst14: IOBUF port map (O => superburst_in_S(14), IO => INTCOM7_P, I => superburst_out_S(14), T => IcontrolPLLnot_S);
+--IOBUF_superburst15: IOBUF port map (O => superburst_in_S(15), IO => INTCOM7_N, I => superburst_out_S(15), T => IcontrolPLLnot_S);
+	
+INTCOM0_P <= superburst_out_S(0) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM0_N <= superburst_out_S(1) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM1_P <= superburst_out_S(2) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM1_N <= superburst_out_S(3) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM2_P <= superburst_out_S(4) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM2_N <= superburst_out_S(5) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM3_P <= superburst_out_S(6) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM3_N <= superburst_out_S(7) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM4_P <= superburst_out_S(8) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM4_N <= superburst_out_S(9) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM5_P <= superburst_out_S(10) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM5_N <= superburst_out_S(11) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM6_P <= superburst_out_S(12) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM6_N <= superburst_out_S(13) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM7_P <= superburst_out_S(14) when IcontrolPLLnot_S='0' else 'Z';
+INTCOM7_N <= superburst_out_S(15) when IcontrolPLLnot_S='0' else 'Z';
+
+
+superburst_out_S(15 downto 0) <= superburst_out0_S(15 downto 0) when superburst_startout_S='1' else '0' & superburst_out0_S(30 downto 16);
+
+process(rxSodaClk_S)
+variable count_V : std_logic_vector(2 downto 0) := (others => '0');
+begin
+	if (rising_edge(rxSodaClk_S)) then
+		if (superburst_startout0_S='1') then
+			superburst_startout_S <= '1';
+			count_V := (others => '0');
+		elsif count_V="011" then
+			superburst_startout_S <= '0';
+		elsif count_V/="111" then
+			count_V := count_V+1;
+		end if;
+	end if;
+end process;
+		
+superburst0_in_S(0) <= INTCOM0_P;
+superburst0_in_S(1) <= INTCOM0_N;
+superburst0_in_S(2) <= INTCOM1_P;
+superburst0_in_S(3) <= INTCOM1_N;
+superburst0_in_S(4) <= INTCOM2_P;
+superburst0_in_S(5) <= INTCOM2_N;
+superburst0_in_S(6) <= INTCOM3_P;
+superburst0_in_S(7) <= INTCOM3_N;
+superburst0_in_S(8) <= INTCOM4_P;
+superburst0_in_S(9) <= INTCOM4_N;
+superburst0_in_S(10) <= INTCOM5_P;
+superburst0_in_S(11) <= INTCOM5_N;
+superburst0_in_S(12) <= INTCOM6_P;
+superburst0_in_S(13) <= INTCOM6_N;
+superburst0_in_S(14) <= INTCOM7_P;
+superburst0_in_S(15) <= INTCOM7_N;
+
+process(superburst_startin0_S,clear_superburst_startin_S)
+begin
+	if clear_superburst_startin_S='1' then
+		superburst_startin1_S <= '0';
+	elsif (rising_edge(superburst_startin0_S)) then
+		superburst_startin1_S <= '1';
+	end if;
+end process;
+process(ADC_clk_S)
+variable done_V : std_logic:= '0';
+begin
+	if (rising_edge(ADC_clk_S)) then
+		clear_superburst_startin_S <= '0';
+		superburst_start_S <= '0';
+		superburst_startin2_S <= superburst_startin1_S;
+		superburst_startin3_S <= superburst_startin2_S;
+		superburst_startin0sync_S <= superburst_startin0_S;
+		if (superburst_startin3_S='0') and (superburst_startin2_S='1') then
+			superburst_in_S(15 downto 0) <= superburst0_in_S(15 downto 0);
+			done_V := '0';
+		elsif (superburst_startin2_S='1') and (superburst_startin0sync_S='0') and (done_V='0') then
+			superburst_in_S(30 downto 16) <= superburst0_in_S(14 downto 0);
+			clear_superburst_startin_S <= '1';
+			superburst_start_S <= '1';
+			done_V := '1';
+		elsif (done_V='1') and (superburst_startin3_S='1') and (superburst_startin2_S='1') and (superburst_startin0sync_S='0') then
+			clear_superburst_startin_S <= '1';
+		end if;
+	end if;
+end process;
+
+-- GTX ----------------------------------------------------		
+ 
+LOS_S <= '1' when (LOS='1') or (MOD_DEF(0)='1') else '0';
+TX_DIS <= '0'; -- SFP always enabled
+
+
+FEE_gtxModule1: FEE_gtxModule port map(
+		gtpClk_P => MGTREFCLK_P,
+		gtpClk_N => MGTREFCLK_N,
+		refclk_out => refclk_S,
+		sysClk => clock_S,
+		asyncclk => async_clock_S,
+		reset => GTX_reset_S,
+		disable_GTX_reset => disable_GTX_reset_S,
+		
+		TX_DLM => TX_DLM_S,
+		TX_DLM_WORD => TX_DLM_WORD_S,
+		RX_DLM => RX_DLM_S,
+		RX_DLM_WORD => RX_DLM_WORD_S,
+		
+		txAsyncClk => packet_out_clock_S,
+		txAsyncData => packet_out_data_S,
+		txAsyncDataWrite => packet_out_write_S,
+		txAsyncFirstData => packet_out_first_S,
+		txAsyncLastData => packet_out_last_S,
+		txAsyncFifoFull => packet_out_fifofull_S,
+		txUsrClk => open,
+		txLocked => GTX_txLocked_S,
+		
+		rxAsyncClk => packet_out_clock_S,
+		rxAsyncData => packet_in_data_S,
+		rxAsyncFirstData => packet_in_first_S,
+		rxAsyncLastData => packet_in_last_S,
+		rxAsyncDataRead => packet_in_read_S,
+		rxError => GTX_Error_S,
+		rxAsyncDataOverflow => open,
+		rxAsyncDataPresent => packet_in_present_S,
+		rxUsrClkdiv2 => rxUsrClkdiv2_S,
+		rxSodaClk => rxSodaClk_S,
+		rxSodaClk40 => rxSodaClk40_S,
+		rxLocked => GTX_rxLocked_S,
+		
+		gtpTxP0 => TX_P,
+		gtpTxN0 => TX_N,
+		gtpRxP0 => RX_P,
+		gtpRxN0 => RX_N,
+		GT0_QPLLOUTCLK_IN => '0', -- gt0_qplloutclk_S,
+		GT0_QPLLOUTREFCLK_IN => '0' -- gt0_qplloutrefclk_S,
+	);
+
+
+		
+process(rxSodaClk_S)
+begin
+	if (rising_edge(rxSodaClk_S)) then
+		reset_rxSodaClk_S <= not startupready_S;
+	end if;
+end process;
+
+gtx_common1: gtx_common port map(
+		QPLLREFCLKSEL_IN => "001",
+		GTREFCLK0_IN => refclk_S,
+		GTREFCLK1_IN => '0',
+		QPLLLOCK_OUT => gt0_qplllock_S,
+		QPLLLOCKDETCLK_IN => clock_S,
+		QPLLOUTCLK_OUT => gt0_qplloutclk_S,
+		QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_S,
+		QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_S,    
+		QPLLRESET_IN => gt0_qpllreset_S
+	);
+
+posedge_to_pulse_notintable: posedge_to_pulse port map(
+    clock_in => rxSodaClk_S,
+    clock_out => ADC_clk_S,
+    en_clk => '1',
+    signal_in => GTX_Error_GEO_S,
+    pulse => rxNotInTable_S);
+
+	
+-- SODA ----------------------------------------------------		
+FEE_soda_client1: FEE_soda_client port map(
+		SYSCLK => clock_S,
+		SODACLK => rxSodaClk_S,
+		RESET => reset_rxSodaClk_S,
+		CLEAR	=> '0',
+		CLK_EN => '1',
+		RX_DLM_WORD_IN => RX_DLM_WORD_S,
+		RX_DLM_IN => RX_DLM_S,
+		TX_DLM_OUT => TX_DLM_S,
+		TX_DLM_WORD_OUT => TX_DLM_WORD_S,
+		TX_DLM_PREVIEW_OUT => open,
+		LINK_PHASE_IN => c_PHASE_H,
+		
+		START_OF_SUPERBURST => superburst_startout0_S,
+		SUPER_BURST_NR => superburst_out0_S,
+		SODA_CMD_VALID => SODA_cmd_valid_S,
+		SODA_CMD_WORD => SODA_cmd_word_S,
+
+		SODA_DATA_IN => (others => '0'),
+		SODA_DATA_OUT => open,
+		SODA_ADDR_IN => (others => '0'),
+		SODA_READ_IN => '0',
+		SODA_WRITE_IN => '0',
+		SODA_ACK_OUT => open,
+		LEDS_OUT => open,
+		LINK_DEBUG_IN => (others => '0'));
+		
+posedge_to_pulse_force_hit_out_S: posedge_to_pulse port map(
+    clock_in => rxSodaClk_S,
+    clock_out => ADC_clk_S,
+    en_clk => '1',
+    signal_in => force_hit_out0_S,
+    pulse => force_hit_out_S);
+
+	
+process(rxSodaClk_S)
+begin
+	if (rising_edge(rxSodaClk_S)) then
+		reset_rxSodaClk_S <= not startupready_S;
+	end if;
+end process;
+
+EnableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(29)='1') else '0';
+DisableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(28)='1') else '0';
+force_hit_out0_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(26)='1') else '0';
+
+datatakingprocess: process(rxSodaClk_S)
+begin
+	if (rising_edge(rxSodaClk_S)) then 
+		if DisableDataTaking_S='1' then
+			DataTaking_enabled_out_S <= '0';
+		elsif EnableDataTaking_S='1' then
+			DataTaking_enabled_out_S <= '1';
+		end if;		
+	end if;
+end process;
+   		
+process(ADC_clk_S,startupready_S)
+variable enable_data_V : std_logic := '0';
+variable DataTaking_enabled_V : std_logic := '0';
+begin
+	if (startupready_S='0') then
+		enable_data_V := '0';
+		enable_data_S <= '0';
+	elsif (rising_edge(ADC_clk_S)) then
+		enable_data_S <= DataTaking_enabled_V;
+		DataTaking_enabled_V := DataTaking_enabled_in_S;
+	end if;
+end process;
+
+process(ADC_clk_S)
+variable counter : integer range 0 to ADCCLOCKFREQUENCY-1 := 0;
+begin
+	if (rising_edge(ADC_clk_S)) then 
+		if counter/=0 then
+			counter := counter-1;
+			onesecondpulse_S <= '0';
+		else
+			counter := ADCCLOCKFREQUENCY-1;
+			onesecondpulse_S <= '1';
+		end if;
+	end if;
+end process;
+
+-- Feature extraction module ----------------------------------------------------	
+process(ADC_clk_S) -- synchronise to 1 clock
+begin
+	if (rising_edge(ADC_clk_S)) then 
+		reset_FEE_ADCclk_S <= reset_FEE_S;
+	end if;
+end process;
+
+FEE_module1: FEE_adc32_module port map(
+		clock => ADC_clk_S,
+		reset => reset_FEE_ADCclk_S,
+		enable_data => enable_data_S,
+		GEO => GEO_S,
+		ADCdata => adcdata_S,
+		superburst_start => superburst_start_S,
+		superburst_received => superburst_in_S,
+		force_hit => force_hit_S,
+		onesecondpulse => onesecondpulse_S,
+		rxNotInTable => rxNotInTable_S,
+		startupready => startupready_S,
+		request_init => request_init_S,
+		packet_in_data => FE_in_data_S,
+		packet_in_present => FE_in_present_S,
+		packet_in_read => FE_in_read_S,
+		packet_out_data => FE_out_data_S,
+		packet_out_first => FE_out_first_S,
+		packet_out_last => FE_out_last_S,
+		packet_out_write => FE_out_write_S,
+		packet_out_inpipe => FE_out_inpipe_S,
+		packet_out_fifofull => FE_out_fifofull_S,
+		errorbyte_out => errorbyte_S,
+		errorbyte_in => errorbyte_S,
+		smaart_in => TEMP_OUT_S,
+		smaart_out => TEMP_IN_S,
+		sysmon_data => sysmon_data_S,
+		sysmon_reset => sysmon_reset_S,
+		sysmon_address => sysmon_address_S,
+		sysmon_read => sysmon_read_S,
+		second_module_zero => vioword_S(9),
+		enable_waveform => enable_waveform_S,
+		compare_error => compare_error_S
+	); 
+
+	
+gen_nocombine: if NROFFEEFPGAS=1 generate
+
+	GTX_txLocked_GEO_S <= GTX_txLocked_S;
+	GTX_Error_GEO_S <= GTX_Error_S;
+	GTX_rxLocked_GEO_S <= GTX_rxLocked_S;
+	LOS_GEO_S <= LOS_S;
+	
+	packet_out_clock_S <= ADC_clk_S;
+	FE_in_data_S <= packet_in_data_S;
+	FE_in_present_S <= packet_in_present_S;
+	packet_in_read_S <= FE_in_read_S;
+--	FE_in_first_S <= packet_in_first_S;
+--	FE_in_last_S <= packet_in_last_S;
+	packet_out_data_S <= FE_out_data_S;
+	packet_out_first_S <= FE_out_first_S;
+	packet_out_last_S <= FE_out_last_S;
+	packet_out_write_S <= FE_out_write_S;
+	FE_out_fifofull_S <= packet_out_fifofull_S;
+
+end generate;
+	
+gen_combine: if NROFFEEFPGAS=2 generate
+
+	packet_out_clock_S <= aurora_clock_S;
+	GTX_txLocked_GEO_S <= GTX_txLocked_S when GEO_S='0' else '1';
+	GTX_rxLocked_GEO_S <= GTX_rxLocked_S when GEO_S='0' else '1';
+	GTX_Error_GEO_S <= GTX_Error_S when GEO_S='0' else '0';
+	LOS_GEO_S <= LOS_S when GEO_S='0' else '0';
+
+	FE_in_data_S <= split_local_S;
+--	FE_in_first_S <= split_local_first_S;
+--	FE_in_last_S <= split_local_last_S;
+	FE_in_present_S <= split_local_present_S;
+	split_local_read_S <= FE_in_read_S;
+
+	split_in_S <= packet_in_data_S when GEO_S='0' else aurora_rx_data_S;
+	split_in_first_S <= packet_in_first_S when GEO_S='0' else aurora_rx_first_S;
+	split_in_last_S <= packet_in_last_S when GEO_S='0' else aurora_rx_last_S;
+	split_in_present_S <= packet_in_present_S when GEO_S='0' else aurora_rx_write_S;
+	packet_in_read_S <= split_in_read_S when GEO_S='0' else '1';
+	
+	aurora_tx_data_S <= split_remote_wr_S when GEO_S='0' else comb_out_S;
+	aurora_tx_first_S <= split_remote_wr_first_S when GEO_S='0' else comb_out_first_S;
+	aurora_tx_last_S <= split_remote_wr_last_S when GEO_S='0' else comb_out_last_S;
+	aurora_tx_inpipe_S <= '0' when GEO_S='0' else comb_out_inpipe_S;
+	aurora_tx_write_S <= split_remote_wr_write_S when GEO_S='0' else comb_out_write_S;	
+	FEE_fiforead2write1: FEE_fiforead2write 
+		generic map(
+			BITS => 34)
+		port map(
+			clock => aurora_clock_S,
+			data_in(31 downto 0) => split_remote_S,
+			data_in(32) => split_remote_first_S,
+			data_in(33) => split_remote_last_S,
+			data_in_empty => split_remote_fifoempty_S,
+			data_in_read => split_remote_read_S,
+			data_out(31 downto 0) => split_remote_wr_S,
+			data_out(32) => split_remote_wr_first_S,
+			data_out(33) => split_remote_wr_last_S,
+			data_out_write => split_remote_wr_write_S,
+			data_out_allowed => split_remote_wr_allowed_S);
+	split_remote_fifoempty_S <= '1' when split_remote_present_S='0' else '0';
+	split_remote_wr_allowed_S <= aurora_tx_allowed_S when GEO_S='0' else '1';
+	
+	packet_out_data_S <= comb_out_S;
+	packet_out_write_S <= comb_out_write_S;
+	packet_out_first_S <= comb_out_first_S;
+	packet_out_last_S <= comb_out_last_S;
+	comb_out_fifofull_S <= packet_out_fifofull_S when GEO_S='0' else not aurora_tx_allowed_S;
+	
+	comb_local_S <= FE_out_data_S;
+	comb_local_first_S <= FE_out_first_S;
+	comb_local_last_S <= FE_out_last_S;
+	comb_local_write_S <= FE_out_write_S;
+	comb_local_inpipe_S <= FE_out_inpipe_S;
+	FE_out_fifofull_S <= comb_local_fifofull_S;
+	
+	comb_remote_S <= aurora_rx_data_S;
+	comb_remote_first_S <= aurora_rx_first_S;
+	comb_remote_last_S <= aurora_rx_last_S;
+	comb_remote_write_S <= aurora_rx_write_S when GEO_S='0' else '0';
+	comb_remote_inpipe_S <= aurora_rx_inpipe_S when GEO_S='0' else '0';
+	aurora_rx_almostfull_S <= comb_remote_almostfull_S when GEO_S='0' else '0';
+	-- error <= '1' when aurora_rx_write_S='1' and comb_remote_fifofull_S='1' else '0';	
+			
+	aurora_dual_module1: aurora_dual_module port map(
+		stable_clock => clock_S,
+		reset => reset_FEE_S,
+		user_clock => aurora_clock_S,
+		tx_data => aurora_tx_data_S,
+		tx_first => aurora_tx_first_S,
+		tx_last => aurora_tx_last_S,
+		tx_write => aurora_tx_write_S,
+		tx_allowed => aurora_tx_allowed_S,
+        tx_inpipe => aurora_tx_inpipe_S,
+		rx_data => aurora_rx_data_S,
+        rx_first => aurora_rx_first_S,
+        rx_last => aurora_rx_last_S,
+		rx_write => aurora_rx_write_S,
+        rx_almostfull => aurora_rx_almostfull_S,
+        rx_inpipe => aurora_rx_inpipe_S,
+		locked => aurora_locked_S,
+		error => aurora_error_S,
+		RXP(0) => GT_B2A_0_P,
+		RXP(1) => GT_B2A_1_P,
+		RXN(0) => GT_B2A_0_N,
+		RXN(1) => GT_B2A_1_N,
+		TXP(0) => GT_A2B_0_P,
+		TXP(1) => GT_A2B_1_P,
+		TXN(0) => GT_A2B_0_N,
+		TXN(1) => GT_A2B_1_N,
+		GTXQ0_P => MGTREFCLK_P,
+		GTXQ0_N => MGTREFCLK_N,
+		gt0_refclk_in => refclk_S,
+		gt0_qplllock_in => gt0_qplllock_S,
+		gt0_qpllrefclklost_in => gt0_qpllrefclklost_S,
+		gt0_qpllreset_out => gt0_qpllreset_S,
+		GT_QPLLOUTCLK_IN => gt0_qplloutclk_S,
+		GT_QPLLOUTREFCLK_IN => gt0_qplloutrefclk_S
+		);
+		
+	FEE_receive_split1: FEE_receive_split port map(
+		clock_in => aurora_clock_S,
+		clock_local => ADC_clk_S,
+		clock_remote => aurora_clock_S,
+		reset => reset_FEE_S,
+		GEO => GEO_S,
+		data_in => split_in_S,
+		data_in_first => split_in_first_S,
+		data_in_last => split_in_last_S,
+		data_in_present => split_in_present_S,
+		data_in_fifofull => split_in_fifofull_S,
+		data_in_read => split_in_read_S,
+		data_local => split_local_S,
+		data_local_first => split_local_first_S,
+		data_local_last => split_local_last_S,
+		data_local_present => split_local_present_S,
+		data_local_read => split_local_read_S,
+		data_remote => split_remote_S,
+		data_remote_first => split_remote_first_S,
+		data_remote_last => split_remote_last_S,
+		data_remote_present => split_remote_present_S,
+		data_remote_read => split_remote_read_S,
+		error => split_error_S);
+
+	FEE_transmit_combine1: FEE_transmit_combine port map(
+		clock_local => ADC_clk_S,
+		clock_remote => aurora_clock_S,
+		clock_out => aurora_clock_S,
+		reset => reset_FEE_S,
+		GEO => GEO_S,
+		enable_waveform => enable_waveform_S,
+		data_local => comb_local_S,
+		data_local_first => comb_local_first_S,
+		data_local_last => comb_local_last_S,
+		data_local_write => comb_local_write_S,
+		data_local_inpipe => comb_local_inpipe_S,
+		data_local_fifofull => comb_local_fifofull_S,
+		data_remote => comb_remote_S,
+		data_remote_first => comb_remote_first_S,
+		data_remote_last => comb_remote_last_S,
+		data_remote_write => comb_remote_write_S,
+		data_remote_inpipe => comb_remote_inpipe_S,
+		data_remote_fifofull => comb_remote_fifofull_S,
+		data_remote_almostfull => comb_remote_almostfull_S,
+		data_out => comb_out_S,
+		data_out_first => comb_out_first_S,
+		data_out_last => comb_out_last_S,
+		data_out_write => comb_out_write_S,
+		data_out_inpipe => comb_out_inpipe_S,
+		data_out_fifofull => comb_out_fifofull_S,
+		error => comb_error_S);
+
+end generate;	
+	
+reboot1: reboot port map(
+    TRIGGER => doreboot_S,
+    SYSCLK => clock40MHz_S);
+
+pulse_wr: posedge_to_pulse port map(
+		clock_in => ADC_clk_S,
+		clock_out => clock_S,
+		en_clk => '1',
+		signal_in => compare_error_S,
+		pulse => compare_error1_S);
+
+	
+sem_module1: sem_module port map(
+		clk => clock40MHz_S,
+		status_heartbeat => status_heartbeat_S,
+		status_initialization => status_initialization_S,
+		status_observation => status_observation_S,
+		status_correction => status_correction_S,
+		status_classification => status_classification_S,
+		status_injection => status_injection_S,
+		status_essential => status_essential_S,
+		status_uncorrectable => status_uncorrectable_S);
+
+process(clock40MHz_S)
+variable prev_status_correction_V : std_logic := '1';
+begin
+	if (rising_edge(clock40MHz_S)) then
+		doreboot_S <= '0';
+		if (status_correction_S='0') and (prev_status_correction_V/='1') then
+			if status_uncorrectable_S='1' then
+				doreboot_S <= '1';
+			end if;
+		end if;
+		if (compare_error1_S='1') and (startupready_S='1') then
+--//			doreboot_S <= '1';
+		end if;
+		prev_status_correction_V := status_correction_S;
+	end if;
+end process;
+
+superburst_lvds_out1 : OBUFDS
+	generic map(
+		IOSTANDARD => "LVDS")
+	port map( 
+		O  => MON2_P,
+		OB => MON2_N,
+		I  => superburst_startout0_S);
+superburst_lvds_out2 : OBUFDS
+	generic map(
+		IOSTANDARD => "LVDS")
+	port map( 
+		O  => MON1_P,
+		OB => MON1_N,
+		I  => superburst_startout_S);
+
+
+
+-- pulse_wr: posedge_to_pulse port map(
+		-- clock_in => clock_S,
+		-- clock_out => clock_S,
+		-- en_clk => '1',
+		-- signal_in => vio_LMK04806_wr0_S,
+		-- pulse => vio_LMK04806_wr_S);
+
+
+-- vio_debug1: vio_debug port map(
+    -- clk => clock_S,
+    -- probe_in0(0) => RDu_S,
+    -- probe_in1(0) => PLL_booting_busy_S,
+    -- probe_in2(0) => GTX_rxLocked_S,
+    -- probe_in3(0) => startupready_S,
+    -- probe_out0(0) => debug_reset_S,
+    -- probe_out1(0) => vio_LMK04806_wr0_S,
+    -- probe_out2 => vio_LMK04806_dta_S);
+
+vio36_1: vio36 port map(
+    clk => ADC_clk_S,
+    probe_out0 => vioword_S);
+	
+	
+process(packet_out_clock_S)
+begin
+	if (rising_edge(packet_out_clock_S)) then
+		if packet_out_write_S='1' then
+			debug_packet_out_data_S <= packet_out_data_S;
+			debug_packet_out_first_S <= packet_out_first_S;
+			debug_packet_out_last_S <= packet_out_last_S;
+		end if;
+	end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard_Vivado.xpr b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard_Vivado.xpr
new file mode 100644
index 0000000..953b628
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard_Vivado.xpr
@@ -0,0 +1,1826 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2015.3 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="10" Path="D:/Xilinx_proj/Panda/Xilinx/FrontEndElectronics/FEE_Kintex_ADCboard_Vivado/FEE_Kintex_ADCboard_Vivado.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="1b37de9fde294ec199fac2bb789ffffa"/>
+    <Option Name="Part" Val="xc7k160tfbg484-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PPRDIR/FEE_Kintex_ADCboard_Vivado.ip_user_files"/>
+    <Option Name="IPStaticSourceDir" Val="$PPRDIR/FEE_Kintex_ADCboard_Vivado.ip_user_files/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_sync_block.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_gt.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_cpll_railing.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/blockmem.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_tx_startup_fsm.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_rx_startup_fsm.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_multi_gt.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_auto_phase_align.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/shift_register_small.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/iirfilter_1order_selectBW.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_MWDfilter_unsigned.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_init.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/gtxkintex7fee80_clock_module.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_eventdetector.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../SODA/trb_net_std.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/Panda_package.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/gtxkintex7fee80_gt_usrclk_source.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/gtxkintex7fee80_common_reset.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_wavemux_readfifo.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_wavemux2to1.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_waveform_to_36bits.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_pulse_detect.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_pulsewaveform_buffer.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_pileup_check.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_mux2to1.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_extract_pulse.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_baselinefollower_eventdetector.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_cdc_sync_exdes.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../SODA/trb_net_components.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../SODA/trb_net16_hub_func.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_collect_pileup_pulses.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/gtxkintex7fee80_support.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_sorting_wavemux.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_sorting_mux.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_rxBitLock.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_dual_pulse_waveform.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/FEE_data8to16.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/FEE_data16to8.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/crc8_add_check32.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_support_reset_logic.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_clock_module.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/adc/AdcFrame.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/adc/AdcData.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/adc/AdcClock.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../SODA/soda_components.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/sensors/TMP104module.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../SODA/soda_reply_pkt_builder.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../SODA/soda_packet_handler.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/FEE_SODAfrequencydiv5.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_slowcontrol_packet_receiver.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_pulse_and_pileup_waveforms.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_measure_frequency.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/FEE_gtxWrapper_Kintex7.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_fifo8to32_SODA.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_fifo32to8_SODA.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_combine_data.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_board_slowcontrol.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_support.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_ll_to_axi_exdes.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_axi_to_ll_exdes.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_aurora_pkg.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/adc/AdcToplevel.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/sem_support/sem_sem_cfg.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/posedge_to_pulse.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/sensors/SystemMonitorModule.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/reboot.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/LMK04806.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/gtx_common.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_transmit_combine.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/FEE_startup.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../SODA/FEE_soda_client.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_receive_split.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/FEE_gtxModule.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_fiforead2write.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/adc/FEE_ADCinput_module.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_adc32_module.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_module.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/adc/AdcSerialProg.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/sem_module.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/FEE_Kintex_ADCboard.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/shift_register.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/sem_support/sem_sem_mon_sipo.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/sem_support/sem_sem_mon_piso.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/sem_support/sem_sem_mon_fifo.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/sem_support/sem_sem_mon.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/sem_support/sem_sem_hid.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/sem_support/sem_sem_example.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_pulse2to1_pulse.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../FEE_modules/FEE_mux_readfifo.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn1_support/gtxconn1_clock_module.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn2_support/gtxconn2_clock_module.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn1_support/gtxconn1_common_reset.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn1_support/gtxconn1_gt_usrclk_source.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn2_support/gtxconn2_common_reset.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn2_support/gtxconn2_gt_usrclk_source.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn1_support/gtxconn1_support.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn2_support/gtxconn2_support.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn1_support/gtxconn1_module.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn2_support/gtxconn2_module.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn2_support/gtxconn2_common.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/gtxconn1_support/gtxconn1_common.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/aurora_dual_support/aurora_dual_gt_common_wrapper.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/gtx/ip_vivado/gtxkintex7fee80_common.vhd">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/ip/ibert_7series_gtx_0/ibert_7series_gtx_0.xci">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="FEE_Kintex_ADCboard"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/ADC32dualgain.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/ADC32dualgain_debug.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/ADC32dualgain_debug.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="FEE_Kintex_ADCboard"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SimMode" Val="post-implementation"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_16x9" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_16x9">
+      <File Path="$PPRDIR/sources/ip/async_fifo_16x9/async_fifo_16x9.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_16x9"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_512x32" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_512x32">
+      <File Path="$PPRDIR/sources/ip/async_fifo_512x32/async_fifo_512x32.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_512x32"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="clock100to200" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clock100to200">
+      <File Path="$PPRDIR/sources/ip/clock100to200/clock100to200.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="clock100to200"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="clockmodule40Mto80M" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clockmodule40Mto80M">
+      <File Path="$PPRDIR/sources/ip/clockmodule40Mto80M_1/clockmodule40Mto80M.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="clockmodule40Mto80M"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="clockmodule100to80M" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clockmodule100to80M">
+      <File Path="$PPRDIR/sources/ip/clockmodule100to80M/clockmodule100to80M.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="clockmodule100to80M"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sem" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sem">
+      <File Path="$PPRDIR/sources/ip/sem.xcix">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/sem/sem.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="sem"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sem_sem_vio" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sem_sem_vio">
+      <File Path="$PPRDIR/sources/ip/sem_sem_vio.xcix">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/sources/ip/sem_sem_vio/sem_sem_vio.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="sem_sem_vio"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sync_fifo_512x41" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sync_fifo_512x41">
+      <File Path="$PPRDIR/sources/ip/sync_fifo_512x41/sync_fifo_512x41.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="sync_fifo_512x41"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sync_fifo_FWFT_512x36" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sync_fifo_FWFT_512x36">
+      <File Path="$PPRDIR/sources/ip/sync_fifo_FWFT_512x36/sync_fifo_FWFT_512x36.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="sync_fifo_FWFT_512x36"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sync_fifo_progfull364_progempty128_512x36" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sync_fifo_progfull364_progempty128_512x36">
+      <File Path="$PPRDIR/sources/ip/sync_fifo_progfull364_progempty128_512x36/sync_fifo_progfull364_progempty128_512x36.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="sync_fifo_progfull364_progempty128_512x36"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sync_fifo_progfull504_progempty32_512x36" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sync_fifo_progfull504_progempty32_512x36">
+      <File Path="$PPRDIR/sources/ip/sync_fifo_progfull504_progempty32_512x36/sync_fifo_progfull504_progempty32_512x36.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="sync_fifo_progfull504_progempty32_512x36"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="SystemMonitorKintex" Type="BlockSrcs" RelSrcDir="$PSRCDIR/SystemMonitorKintex">
+      <File Path="$PPRDIR/sources/ip/SystemMonitorKintex/SystemMonitorKintex.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="SystemMonitorKintex"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="gtxconn1" Type="BlockSrcs" RelSrcDir="$PSRCDIR/gtxconn1">
+      <File Path="$PPRDIR/sources/ip/gtxconn1/gtxconn1.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="gtxconn1"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="gtxconn2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/gtxconn2">
+      <File Path="$PPRDIR/sources/ip/gtxconn2/gtxconn2.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="gtxconn2"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="aurora_dual" Type="BlockSrcs" RelSrcDir="$PSRCDIR/aurora_dual">
+      <File Path="$PPRDIR/sources/ip/aurora_dual/aurora_dual.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="aurora_dual"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="vio_debug" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_debug">
+      <File Path="$PSRCDIR/sources_1/ip/vio_debug/vio_debug.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="vio_debug"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_256x32" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_256x32">
+      <File Path="$PPRDIR/sources/ip/async_fifo_256x32/async_fifo_256x32.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_256x32"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_progfull448_progempty128_fifo_512x34" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_progfull448_progempty128_fifo_512x34">
+      <File Path="$PPRDIR/sources/ip/async_progfull448_progempty128_fifo_512x34/async_progfull448_progempty128_fifo_512x34.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_progfull448_progempty128_fifo_512x34"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sync_fifo_progempty32_FWFT_512x104" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sync_fifo_progempty32_FWFT_512x104">
+      <File Path="$PPRDIR/sources/ip/sync_fifo_progempty32_FWFT_512x104/sync_fifo_progempty32_FWFT_512x104.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="sync_fifo_progempty32_FWFT_512x104"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sync_fifo_512x111" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sync_fifo_512x111">
+      <File Path="$PPRDIR/sources/ip/sync_fifo_512x111/sync_fifo_512x111.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="sync_fifo_512x111"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="vio36" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio36">
+      <File Path="$PPRDIR/sources/ip/vio36/vio36.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="vio36"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="blockmem_xilinx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blockmem_xilinx">
+      <File Path="$PPRDIR/sources/ip/blockmem_xilinx/blockmem_xilinx.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="blockmem_xilinx"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="blockmem2x18_xilinx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blockmem2x18_xilinx">
+      <File Path="$PPRDIR/sources/ip/blockmem2x18_xilinx/blockmem2x18_xilinx.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="blockmem2x18_xilinx"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="blockmem3x18_xilinx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blockmem3x18_xilinx">
+      <File Path="$PPRDIR/sources/ip/blockmem3x18_xilinx/blockmem3x18_xilinx.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="blockmem3x18_xilinx"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="blockmem4x18_xilinx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blockmem4x18_xilinx">
+      <File Path="$PPRDIR/sources/ip/blockmem4x18_xilinx/blockmem4x18_xilinx.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="blockmem4x18_xilinx"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="blockmem5x18_xilinx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blockmem5x18_xilinx">
+      <File Path="$PPRDIR/sources/ip/blockmem5x18_xilinx/blockmem5x18_xilinx.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="blockmem5x18_xilinx"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="blockmem1x18_xilinx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blockmem1x18_xilinx">
+      <File Path="$PPRDIR/sources/ip/blockmem1x18_xilinx/blockmem1x18_xilinx.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="blockmem1x18_xilinx"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="blockmem1x96_xilinx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blockmem1x96_xilinx">
+      <File Path="$PPRDIR/sources/ip/blockmem1x96_xilinx/blockmem1x96_xilinx.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="blockmem1x96_xilinx"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="blockmem2x96_xilinx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blockmem2x96_xilinx">
+      <File Path="$PPRDIR/sources/ip/blockmem2x96_xilinx/blockmem2x96_xilinx.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="blockmem2x96_xilinx"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="blockmem3x96_xilinx" Type="BlockSrcs" RelSrcDir="$PSRCDIR/blockmem3x96_xilinx">
+      <File Path="$PPRDIR/sources/ip/blockmem3x96_xilinx/blockmem3x96_xilinx.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="blockmem3x96_xilinx"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k160tfbg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_16x9_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_16x9" Part="xc7k160tfbg484-1" ConstrsSet="async_fifo_16x9" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_16x9_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_512x32_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_512x32" Part="xc7k160tfbg484-1" ConstrsSet="async_fifo_512x32" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_512x32_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="clock100to200_synth_1" Type="Ft3:Synth" SrcSet="clock100to200" Part="xc7k160tfbg484-1" ConstrsSet="clock100to200" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/clock100to200_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="clockmodule40Mto80M_synth_1" Type="Ft3:Synth" SrcSet="clockmodule40Mto80M" Part="xc7k160tfbg484-1" ConstrsSet="clockmodule40Mto80M" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/clockmodule40Mto80M_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="clockmodule100to80M_synth_1" Type="Ft3:Synth" SrcSet="clockmodule100to80M" Part="xc7k160tfbg484-1" ConstrsSet="clockmodule100to80M" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/clockmodule100to80M_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="sem_synth_1" Type="Ft3:Synth" SrcSet="sem" Part="xc7k160tfbg484-1" ConstrsSet="sem" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sem_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="sem_sem_vio_synth_1" Type="Ft3:Synth" SrcSet="sem_sem_vio" Part="xc7k160tfbg484-1" ConstrsSet="sem_sem_vio" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sem_sem_vio_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="sync_fifo_512x41_synth_1" Type="Ft3:Synth" SrcSet="sync_fifo_512x41" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_512x41" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sync_fifo_512x41_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="sync_fifo_FWFT_512x36_synth_1" Type="Ft3:Synth" SrcSet="sync_fifo_FWFT_512x36" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_FWFT_512x36" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sync_fifo_FWFT_512x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="sync_fifo_progfull364_progempty128_512x36_synth_1" Type="Ft3:Synth" SrcSet="sync_fifo_progfull364_progempty128_512x36" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_progfull364_progempty128_512x36" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sync_fifo_progfull364_progempty128_512x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="sync_fifo_progfull504_progempty32_512x36_synth_1" Type="Ft3:Synth" SrcSet="sync_fifo_progfull504_progempty32_512x36" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_progfull504_progempty32_512x36" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sync_fifo_progfull504_progempty32_512x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="SystemMonitorKintex_synth_1" Type="Ft3:Synth" SrcSet="SystemMonitorKintex" Part="xc7k160tfbg484-1" ConstrsSet="SystemMonitorKintex" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/SystemMonitorKintex_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="gtxconn1_synth_1" Type="Ft3:Synth" SrcSet="gtxconn1" Part="xc7k160tfbg484-1" ConstrsSet="gtxconn1" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/gtxconn1_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="gtxconn2_synth_1" Type="Ft3:Synth" SrcSet="gtxconn2" Part="xc7k160tfbg484-1" ConstrsSet="gtxconn2" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/gtxconn2_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="aurora_dual_synth_1" Type="Ft3:Synth" SrcSet="aurora_dual" Part="xc7k160tfbg484-1" ConstrsSet="aurora_dual" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/aurora_dual_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="vio_debug_synth_1" Type="Ft3:Synth" SrcSet="vio_debug" Part="xc7k160tfbg484-1" ConstrsSet="vio_debug" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/vio_debug_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_256x32_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_256x32" Part="xc7k160tfbg484-1" ConstrsSet="async_fifo_256x32" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_256x32_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_progfull448_progempty128_fifo_512x34_synth_1" Type="Ft3:Synth" SrcSet="async_progfull448_progempty128_fifo_512x34" Part="xc7k160tfbg484-1" ConstrsSet="async_progfull448_progempty128_fifo_512x34" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_progfull448_progempty128_fifo_512x34_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="sync_fifo_progempty32_FWFT_512x104_synth_1" Type="Ft3:Synth" SrcSet="sync_fifo_progempty32_FWFT_512x104" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_progempty32_FWFT_512x104" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sync_fifo_progempty32_FWFT_512x104_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="sync_fifo_512x111_synth_1" Type="Ft3:Synth" SrcSet="sync_fifo_512x111" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_512x111" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sync_fifo_512x111_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="vio36_synth_1" Type="Ft3:Synth" SrcSet="vio36" Part="xc7k160tfbg484-1" ConstrsSet="vio36" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/vio36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="blockmem_xilinx_synth_1" Type="Ft3:Synth" SrcSet="blockmem_xilinx" Part="xc7k160tfbg484-1" ConstrsSet="blockmem_xilinx" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/blockmem_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="blockmem2x18_xilinx_synth_1" Type="Ft3:Synth" SrcSet="blockmem2x18_xilinx" Part="xc7k160tfbg484-1" ConstrsSet="blockmem2x18_xilinx" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/blockmem2x18_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="blockmem3x18_xilinx_synth_1" Type="Ft3:Synth" SrcSet="blockmem3x18_xilinx" Part="xc7k160tfbg484-1" ConstrsSet="blockmem3x18_xilinx" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/blockmem3x18_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="blockmem4x18_xilinx_synth_1" Type="Ft3:Synth" SrcSet="blockmem4x18_xilinx" Part="xc7k160tfbg484-1" ConstrsSet="blockmem4x18_xilinx" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/blockmem4x18_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="blockmem5x18_xilinx_synth_1" Type="Ft3:Synth" SrcSet="blockmem5x18_xilinx" Part="xc7k160tfbg484-1" ConstrsSet="blockmem5x18_xilinx" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/blockmem5x18_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="blockmem1x18_xilinx_synth_1" Type="Ft3:Synth" SrcSet="blockmem1x18_xilinx" Part="xc7k160tfbg484-1" ConstrsSet="blockmem1x18_xilinx" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/blockmem1x18_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="blockmem1x96_xilinx_synth_1" Type="Ft3:Synth" SrcSet="blockmem1x96_xilinx" Part="xc7k160tfbg484-1" ConstrsSet="blockmem1x96_xilinx" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/blockmem1x96_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="blockmem2x96_xilinx_synth_1" Type="Ft3:Synth" SrcSet="blockmem2x96_xilinx" Part="xc7k160tfbg484-1" ConstrsSet="blockmem2x96_xilinx" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/blockmem2x96_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="blockmem3x96_xilinx_synth_1" Type="Ft3:Synth" SrcSet="blockmem3x96_xilinx" Part="xc7k160tfbg484-1" ConstrsSet="blockmem3x96_xilinx" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/blockmem3x96_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="constrs_1" Description="Similar to Peformance_Explore, but enables the physical optimization step (phys_opt_design) with the Explore directive after routing." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Performance_ExplorePostRoutePhysOpt" Flow="Vivado Implementation 2015">
+          <Desc>Similar to Peformance_Explore, but enables the physical optimization step (phys_opt_design) with the Explore directive after routing.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design">
+          <Option Id="Directive">0</Option>
+        </Step>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design">
+          <Option Id="Directive">0</Option>
+        </Step>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design" EnableStepBool="1">
+          <Option Id="Directive">0</Option>
+        </Step>
+        <Step Id="route_design">
+          <Option Id="MoreOptsStr"><![CDATA[-tns_cleanup]]></Option>
+          <Option Id="Directive">0</Option>
+        </Step>
+        <Step Id="post_route_phys_opt_design" EnableStepBool="1">
+          <Option Id="Directive">0</Option>
+        </Step>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_16x9_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="async_fifo_16x9" Description="Vivado Implementation Defaults" SynthRun="async_fifo_16x9_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_512x32_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="async_fifo_512x32" Description="Vivado Implementation Defaults" SynthRun="async_fifo_512x32_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="clock100to200_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="clock100to200" Description="Vivado Implementation Defaults" SynthRun="clock100to200_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="clockmodule40Mto80M_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="clockmodule40Mto80M" Description="Vivado Implementation Defaults" SynthRun="clockmodule40Mto80M_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="clockmodule100to80M_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="clockmodule100to80M" Description="Vivado Implementation Defaults" SynthRun="clockmodule100to80M_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="sem_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="sem" Description="Vivado Implementation Defaults" SynthRun="sem_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="sem_sem_vio_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="sem_sem_vio" Description="Vivado Implementation Defaults" SynthRun="sem_sem_vio_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="sync_fifo_512x41_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_512x41" Description="Vivado Implementation Defaults" SynthRun="sync_fifo_512x41_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="sync_fifo_FWFT_512x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_FWFT_512x36" Description="Vivado Implementation Defaults" SynthRun="sync_fifo_FWFT_512x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="sync_fifo_progfull364_progempty128_512x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_progfull364_progempty128_512x36" Description="Vivado Implementation Defaults" SynthRun="sync_fifo_progfull364_progempty128_512x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="sync_fifo_progfull504_progempty32_512x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_progfull504_progempty32_512x36" Description="Vivado Implementation Defaults" SynthRun="sync_fifo_progfull504_progempty32_512x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="SystemMonitorKintex_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="SystemMonitorKintex" Description="Vivado Implementation Defaults" SynthRun="SystemMonitorKintex_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="gtxconn1_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="gtxconn1" Description="Vivado Implementation Defaults" SynthRun="gtxconn1_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="gtxconn2_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="gtxconn2" Description="Vivado Implementation Defaults" SynthRun="gtxconn2_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="aurora_dual_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="aurora_dual" Description="Vivado Implementation Defaults" SynthRun="aurora_dual_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="vio_debug_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="vio_debug" Description="Vivado Implementation Defaults" SynthRun="vio_debug_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_256x32_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="async_fifo_256x32" Description="Vivado Implementation Defaults" SynthRun="async_fifo_256x32_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_progfull448_progempty128_fifo_512x34_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="async_progfull448_progempty128_fifo_512x34" Description="Vivado Implementation Defaults" SynthRun="async_progfull448_progempty128_fifo_512x34_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="sync_fifo_progempty32_FWFT_512x104_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_progempty32_FWFT_512x104" Description="Vivado Implementation Defaults" SynthRun="sync_fifo_progempty32_FWFT_512x104_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="sync_fifo_512x111_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="sync_fifo_512x111" Description="Vivado Implementation Defaults" SynthRun="sync_fifo_512x111_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="vio36_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="vio36" Description="Vivado Implementation Defaults" SynthRun="vio36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="blockmem_xilinx_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="blockmem_xilinx" Description="Vivado Implementation Defaults" SynthRun="blockmem_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="blockmem2x18_xilinx_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="blockmem2x18_xilinx" Description="Vivado Implementation Defaults" SynthRun="blockmem2x18_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="blockmem3x18_xilinx_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="blockmem3x18_xilinx" Description="Vivado Implementation Defaults" SynthRun="blockmem3x18_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="blockmem4x18_xilinx_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="blockmem4x18_xilinx" Description="Vivado Implementation Defaults" SynthRun="blockmem4x18_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="blockmem5x18_xilinx_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="blockmem5x18_xilinx" Description="Vivado Implementation Defaults" SynthRun="blockmem5x18_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="blockmem1x18_xilinx_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="blockmem1x18_xilinx" Description="Vivado Implementation Defaults" SynthRun="blockmem1x18_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="blockmem1x96_xilinx_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="blockmem1x96_xilinx" Description="Vivado Implementation Defaults" SynthRun="blockmem1x96_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="blockmem2x96_xilinx_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="blockmem2x96_xilinx" Description="Vivado Implementation Defaults" SynthRun="blockmem2x96_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="blockmem3x96_xilinx_impl_1" Type="Ft2:EntireDesign" Part="xc7k160tfbg484-1" ConstrsSet="blockmem3x96_xilinx" Description="Vivado Implementation Defaults" SynthRun="blockmem3x96_xilinx_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+</Project>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/FEE_startup.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/FEE_startup.vhd
new file mode 100644
index 0000000..44d7f6d
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/FEE_startup.vhd
@@ -0,0 +1,428 @@
+---------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   27-10-2014
+-- Module Name:   FEE_startup
+-- Description:   Startup FEE : reset, PLL, ADCs, GTX ...
+-- Modifications:
+--   30-03-2015   GTX_LOS signal added
+--   09-09-2015   GTX_LOS synchronized and longer waiting times
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_startup
+--
+--
+-- Library:
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock : stable main clock, frequency equal to ADC clock
+--     ADCclock : clock for ADC data, stable after GTX lock / ADCs init
+--     clock_from_PLL : clock from external PLL, frequency equal to ADC clock
+--     reset : reset all
+--     GEO : first ('0') or second ('1') FPGA
+--     IcontrolPLL : this FPGA controls the PLL/jtag
+--     PLL_booting : PLL initializing busy
+--     GTX_LOS : Los Off Signal from SFP module
+--     GTX_rxLocked : GTX receiver is locked to SODA frequency
+--     GTX_txLocked : GTX transmitter is locked
+--     GTX_error : error in GTX
+--     PLL_locked : external PLL is locked 
+--     ADCs_ready : frame start signals from ADCs, LVDS negative
+-- 
+-- Outputs:
+--     ADCchip_init : start initialize ADC chip with serial interface
+--     PLL_init : initialize the PLL
+--     GTX_reset : reset the GTX
+--     PLLuseGTXclock : use the GTX recovered clock as reference for the external PLL
+--     ADCs_reset : reset the ADCs
+--     FEE_reset : reset the FEE module (feature extraction / slow control / ...)
+--     startupready : startup procedure is done
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_startup is
+	port ( 
+		clock                 : in std_logic;
+		ADCclock              : in std_logic;
+		clock_from_PLL        : in std_logic;
+		reset                 : in std_logic;
+		GEO                   : in std_logic;
+		IcontrolPLL           : in std_logic;
+		ADCchip_init          : out std_logic;
+		PLL_init              : out std_logic;
+		PLL_booting           : in std_logic;
+		GTX_LOS               : in std_logic;
+		GTX_reset             : out std_logic;
+		GTX_rxLocked          : in std_logic;
+		GTX_txLocked          : in std_logic;
+		GTX_error             : in std_logic;
+		PLLuseGTXclock        : out std_logic;
+		PLL_locked            : in std_logic;
+		ADCs_reset            : out std_logic;
+		ADCs_ready            : in std_logic;
+		FEE_reset             : out std_logic;
+		startupready          : out std_logic
+		);
+end FEE_startup;
+
+architecture Behavioral of FEE_startup is
+
+type stage_type is (resetting,initPLL,waitPLLready,waitPLLlocked,resetGTX,waitGTXlocked,switchPLLclock,enableADCs,waitADCsready,enableFEE,readystate);
+signal stage_S                : stage_type := resetting;
+
+signal PLLclockdiv255_S       : std_logic;
+signal PLLclockdiv255sync0_S  : std_logic;
+signal PLLclockdiv255sync1_S  : std_logic;
+signal PLLclockdiv255_prev_S  : std_logic;
+signal PLLfrequencyERROR_S    : std_logic;
+signal PLLfrequcounter_V      : integer range 0 to 255 := 0;
+		
+signal IcontrolPLL_S          : std_logic;
+signal IcontrolPLL1_S         : std_logic;
+signal PLL_init_S             : std_logic := '0';
+signal ADCchip_init_S         : std_logic;
+signal GTX_LOS_S              : std_logic;
+signal GTX_LOS0_S             : std_logic;
+signal GTX_reset_S            : std_logic := '1';
+signal PLLuseGTXclock_S       : std_logic := '0';
+signal PLL_booting_S          : std_logic;
+signal PLL_locked_S           : std_logic;
+signal GTX_rxLocked0_S        : std_logic;
+signal GTX_rxLocked_S         : std_logic;
+signal GTX_txLocked0_S        : std_logic;
+signal GTX_txLocked_S         : std_logic;
+signal GTX_error0_S           : std_logic;
+signal GTX_error_S            : std_logic;
+signal ADCs_ready0_S          : std_logic;
+signal ADCs_ready_S           : std_logic;
+signal ADCs_reset_S           : std_logic := '1';
+signal FEE_reset_S            : std_logic := '1';
+signal FEE_reset0_S           : std_logic := '1';
+signal startupready_S         : std_logic := '0';
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of IcontrolPLL_S : signal is "true";
+-- attribute mark_debug of PLL_init_S : signal is "true";
+-- attribute mark_debug of ADCchip_init_S : signal is "true";
+-- attribute mark_debug of GTX_LOS_S : signal is "true";
+-- attribute mark_debug of GTX_reset_S : signal is "true";
+-- attribute mark_debug of PLLuseGTXclock_S : signal is "true";
+-- attribute mark_debug of PLL_booting_S : signal is "true";
+-- attribute mark_debug of PLL_locked_S : signal is "true";
+-- attribute mark_debug of GTX_rxLocked_S : signal is "true";
+-- attribute mark_debug of GTX_txLocked_S : signal is "true";
+-- attribute mark_debug of GTX_error_S : signal is "true";
+-- attribute mark_debug of ADCs_ready_S : signal is "true";
+-- attribute mark_debug of ADCs_reset_S : signal is "true";
+-- attribute mark_debug of FEE_reset_S : signal is "true";
+-- attribute mark_debug of startupready_S : signal is "true";
+-- attribute mark_debug of stage_S : signal is "true";
+
+begin
+
+
+-- FPGA1:
+-- reset , PLL unlocked
+-- initialize external PLL
+-- wait for external PLL ready
+-- wait for fiber locked
+-- switch PLL reference to reconstructed clock
+-- enable ADCs & enable FPGA2
+-- wait for ADCs ready
+-- enable FEE module
+
+-- FPGA2 with fiber:
+-- reset , PLL unlocked
+-- wait for fiber locked
+-- wait for enable ADCs
+-- enable ADCs
+-- wait for ADCs ready
+-- enable FEE module
+
+-- FPGA2 without fiber:
+-- reset , PLL unlocked
+-- wait for aurora locked
+-- wait for enable ADCs
+-- enable ADCs
+-- wait for ADCs ready
+-- enable FEE module
+
+-- synchronize to the right clock, if necessary -----------------
+PLL_init <= PLL_init_S;
+PLL_booting_S <= PLL_booting;
+ADCchip_init <= ADCchip_init_S;
+GTX_reset <= GTX_reset_S;
+PLLuseGTXclock <= PLLuseGTXclock_S;
+ADCs_reset <= ADCs_reset_S;
+startupready <= startupready_S;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		IcontrolPLL_S <= IcontrolPLL;
+		GTX_LOS_S <= GTX_LOS0_S;
+		GTX_LOS0_S <= GTX_LOS;
+		PLL_locked_S <= PLL_locked;
+		GTX_rxLocked0_S <= GTX_rxLocked;
+		GTX_rxLocked_S <= GTX_rxLocked0_S;
+		GTX_txLocked0_S <= GTX_txLocked;
+		GTX_txLocked_S <= GTX_txLocked0_S;
+		GTX_error0_S <= GTX_error;
+		GTX_error_S <= GTX_error0_S;
+		ADCs_ready0_S <= ADCs_ready;
+		ADCs_ready_S <= ADCs_ready0_S;
+	end if;
+end process;
+
+process(ADCclock,reset)
+begin
+	if reset='1' then
+		FEE_reset0_S <= '1';
+		FEE_reset <= '1';
+	elsif (rising_edge(ADCclock)) then
+
+		FEE_reset0_S <= FEE_reset_S;
+		FEE_reset <= FEE_reset0_S;
+	end if;
+end process;
+--------------------------------------------------------------------------
+
+-- check PLL frequency ---------------------------------------------------
+process(clock_from_PLL)
+variable counter_V : std_logic_vector(7 downto 0) := (others => '0');
+begin
+	if (rising_edge(clock_from_PLL)) then 
+		PLLclockdiv255_S <= counter_V(7);
+		counter_V := counter_V+1;
+	end if;
+end process;
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		PLLfrequencyERROR_S <= '0';
+		PLLclockdiv255sync0_S <= PLLclockdiv255_S;
+		PLLclockdiv255sync1_S <= PLLclockdiv255sync0_S;
+		PLLclockdiv255_prev_S <= PLLclockdiv255sync1_S;
+		if PLLclockdiv255_prev_S/=PLLclockdiv255sync1_S then
+			if (PLLfrequcounter_V<125) or (PLLfrequcounter_V>129) then
+				PLLfrequencyERROR_S <= '1';
+			end if;
+			PLLfrequcounter_V <= 0;
+		elsif PLLfrequcounter_V<255 then
+			PLLfrequcounter_V <= PLLfrequcounter_V+1;
+		end if;
+	end if;
+end process;
+--------------------------------------------------------------------------
+
+process(clock,reset,IcontrolPLL)
+variable wait_V   : std_logic_vector(17 downto 0);
+variable waitADC_V   : std_logic_vector(8 downto 0);
+begin
+	if reset='1' then
+		stage_S <= resetting;
+		ADCchip_init_S <= '0';
+		PLL_init_S <= '0';
+		GTX_reset_S <= '1';
+		PLLuseGTXclock_S <= '0';
+		ADCs_reset_S <= '1';
+		FEE_reset_S <= '1';
+		startupready_S <= '0';
+		IcontrolPLL1_S <= IcontrolPLL;
+	elsif (rising_edge(clock)) then 
+		startupready_S <= '0';
+		case stage_S is
+			when resetting =>
+				wait_V := (others => '0');
+				ADCchip_init_S <= '1';
+				PLL_init_S <= '0';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '1';
+				PLLuseGTXclock_S <= '0';
+				ADCs_reset_S <= '1';
+				FEE_reset_S <= '1';
+				if IcontrolPLL_S='1' then
+					stage_S <= initPLL;
+				else
+					stage_S <= waitPLLlocked;
+				end if;
+			when initPLL =>
+				ADCchip_init_S <= '0';
+				PLL_init_S <= '1';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '1';
+				PLLuseGTXclock_S <= '0';
+				ADCs_reset_S <= '1';
+				FEE_reset_S <= '1';
+				if PLL_booting_S='1' then
+					wait_V := (others => '0');
+					stage_S <= waitPLLready;
+				else
+					if wait_V(17)='0' then
+						wait_V := wait_V+1;
+					else
+						stage_S <= resetting;
+					end if;
+				end if;
+			when waitPLLready =>
+				PLL_init_S <= '0';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '1';
+				PLLuseGTXclock_S <= '0';
+				ADCs_reset_S <= '1';
+				FEE_reset_S <= '1';
+				if PLL_booting_S='0' then
+					wait_V := (others => '0');
+					stage_S <= resetGTX;
+				else
+					if wait_V(16)='0' then
+						wait_V := wait_V+1;
+					else
+						stage_S <= resetting;
+					end if;
+				end if;
+			when waitPLLlocked =>
+				ADCchip_init_S <= '0';
+				PLL_init_S <= '0';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '1';
+				PLLuseGTXclock_S <= '0';
+				ADCs_reset_S <= '1';
+				FEE_reset_S <= '1';
+				if ((IcontrolPLL_S='1') or (PLL_locked_S='1')) and (GTX_LOS_S='0') then
+					stage_S <= resetGTX;
+				end if;
+			when resetGTX =>
+				ADCchip_init_S <= '0';
+				PLL_init_S <= '0';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '1';
+				PLLuseGTXclock_S <= '0';
+				ADCs_reset_S <= '1';
+				FEE_reset_S <= '1';
+				if wait_V(3)='0' then
+					wait_V := wait_V+1;
+				else
+					wait_V := (others => '0');
+					stage_S <= waitGTXlocked;
+				end if;
+				if GTX_LOS_S='1' then
+					stage_S <= waitPLLlocked;
+				end if;
+			when waitGTXlocked =>
+				ADCchip_init_S <= '0';
+				PLL_init_S <= '0';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '0';
+				PLLuseGTXclock_S <= '0';
+				ADCs_reset_S <= '1';
+				FEE_reset_S <= '1';
+				if (GTX_rxLocked_S='1') and (GTX_txLocked_S='1') and (GTX_LOS_S='0') then
+					stage_S <= switchPLLclock;
+				else
+					if wait_V(13)='1' then
+						wait_V := wait_V+1;
+					else
+						if (PLLfrequencyERROR_S='1') or (GTX_LOS_S='1') then
+							stage_S <= resetting;
+						end if;
+					end if;
+				end if;
+			when switchPLLclock => -- not necessary if IcontrolPLL_S='0', but does not harm
+				ADCchip_init_S <= '0';
+				PLL_init_S <= '0';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '0';
+				PLLuseGTXclock_S <= '1';
+				ADCs_reset_S <= '1';
+				FEE_reset_S <= '1';
+				stage_S <= enableADCs;
+			when enableADCs =>
+				ADCchip_init_S <= '0';
+				PLL_init_S <= '0';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '0';
+				PLLuseGTXclock_S <= '1';
+				ADCs_reset_S <= '0';
+				FEE_reset_S <= '1';
+				wait_V := (others => '0');
+				waitADC_V := (others => '0');
+				stage_S <= waitADCsready;
+			when waitADCsready =>
+				ADCchip_init_S <= '0';
+				PLL_init_S <= '0';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '0';
+				PLLuseGTXclock_S <= '1';
+				ADCs_reset_S <= '0';
+				FEE_reset_S <= '1';
+				if PLLfrequencyERROR_S='1' then
+					stage_S <= resetting;
+				elsif (ADCs_ready_S='1') then
+					if waitADC_V(8)='1' then
+						stage_S <= enableFEE;
+					else
+						waitADC_V := waitADC_V+1;
+					end if;
+				elsif wait_V(17)='0' then
+					wait_V := wait_V+1;
+					waitADC_V := (others => '0');
+				else
+					stage_S <= resetting;
+				end if;
+			when enableFEE =>
+				PLL_init_S <= '0';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '0';
+				PLLuseGTXclock_S <= '1';
+				ADCs_reset_S <= '0';
+				stage_S <= readystate;
+			when readystate =>
+				PLL_init_S <= '0';
+				FEE_reset_S <= '0';
+				GTX_reset_S <= '0';
+				PLLuseGTXclock_S <= '1';
+				ADCs_reset_S <= '0';
+				if PLLfrequencyERROR_S='1' then
+					stage_S <= resetting;
+				elsif (GTX_rxLocked_S='0') or (GTX_txLocked_S='0') or (GTX_LOS_S='1') then
+					stage_S <= waitPLLlocked;
+stage_S <= resetting;
+				elsif ADCs_ready_S='0' then
+					ADCs_reset_S <= '1';
+					ADCchip_init_S <= '0';
+					stage_S <= enableADCs;
+				else
+					startupready_S <= '1';
+				end if;
+			when others =>
+				PLL_init_S <= '0';
+				FEE_reset_S <= '1';
+				GTX_reset_S <= '1';
+				PLLuseGTXclock_S <= '0';
+				ADCs_reset_S <= '1';
+				FEE_reset_S <= '1';
+				startupready_S <= '0';
+				stage_S <= resetting;
+		end case;
+		if IcontrolPLL1_S/=IcontrolPLL_S then -- check if the same FPGA controls PLL
+			stage_S <= resetting;
+		end if;
+		IcontrolPLL1_S <= IcontrolPLL_S;
+	end if;
+end process;
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/LMK04806.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/LMK04806.vhd
new file mode 100644
index 0000000..4cc432d
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/LMK04806.vhd
@@ -0,0 +1,414 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+--use work.util_pack.ALL;
+
+entity LMK04806 is
+	generic(
+		CLK_DIV                 : integer := 2       -- slow down transfer
+	);         
+	PORT( 
+		clock                   : in std_logic; --Master clock 
+		reset                   : in std_logic; --reset
+		CLKu                    : out std_logic; --Clk to LMK  
+		DATAu                   : out std_logic; --Data to LMK
+		LEu                     : out std_logic; --Data Latch to LMK
+		RDu                     : in std_logic; --Read back
+		SYNC                    : out std_logic; --Sync CLK outputs LMK
+		boot_PLL                : in std_logic; --Start booting when set high
+		booting                 : out std_logic --busy signal		
+		);
+end LMK04806;
+
+architecture Behavioral of LMK04806 is
+constant NROFREGS : integer := 27;
+type RomType is array (0 to NROFREGS-1) of std_logic_vector(31 downto 0);
+type RomType32 is array (0 to 31) of std_logic_vector(31 downto 0);
+-- parameters based on 'Clock design tool' from National Semiconductor
+--CONSTANT TAB62M5 : RomType := -- 62.5MHz
+--	( 
+--	x"00020000", -- R0 (Reset=1)		
+--	x"00000500", -- R0 (Reset=0)		
+--	X"00000500", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 62.5MHz)
+--	X"00000501", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 62.5MHz)
+--	X"00000502", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 125MHz) GTX & gclk
+--	X"00000503", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 125MHz) GTX & gclk
+--	X"00000504", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 62.5MHz)
+--	X"00000505", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 62.5MHz)
+--	x"11110006", --	R6 (OUT	3,2,1,0:LVDS, no delay)
+--	x"11110007", --	R7 (OUT	7,6,5,4:LVDS, no delay)
+--	x"11110008", --	R8 (OUT	11,10,9,8:LVDS, no delay)
+--	x"55555549", --	R9 (fixed pattern)			
+--	x"0000806A", --	R10	(OSCout1=LVPECL-700mV, OSCout0=disabled, OSCout1,0=disabled, OSC0,1=bypass_divider, OSCoutDIV=8, VCOdiv=1, FEEDbackMUX=CLKout6)
+--	x"4402800B", --	R11	(mode=singlePLL, 0delay, SYNC=enabled, active=high, SYNC_QUAL=1?, auto_sync=1, sSYNC=input, externalXTAL=disabled)			
+--	x"030C00aC", --	R12	(LD=0, no force SYNC, no DAC tracking, no HOLDOVER)		
+--	x"3B00800D", --	R13	(HOLDOVER pin=uwire, status pins=0, no DLD1DET, status CLKin=0, CLKin not used)			
+--	x"0000000E", --	R14	(LOS after 1200ns, CLKin not used, no DAC trip)				
+--	x"8000800F", --	R15	(MAN_DAC=512, disabled, HOLDOVER count=512, disabled)				
+--	x"01550410", --	R16	(xtal=1.65V, fixed pattern)		
+--	x"000000D8", --	R24	(LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm, delay=0ps, window=40ns)	-- DD0000D8
+--	x"010100D9", --	R25	(DAC clkdiv=4, PLL2 DLD cont=1024)
+--	x"83A8001A", --	R26	(PLL2 window=3.7ns, no 2*frequ, neg slope, chargepump=100u, PLL2 DLD count=8192???, CPout2=active)	
+--	x"0008003B", --	R27	(PLL1 not used: neg slope, div=1, PLL1 DLD count=8192, CPout1=tristate)	
+--	x"0010005C", --	R28	(PLL2 R_divider=1, PLL1 N_divider=1)
+--	x"0000015D", --	R29	(OSCin=0..63MHz, <100MHz, PLL2 N_CALdivider=10)
+--	x"0400015E", --	R30	(N_prescaler=4, N_divider=10)				
+----	X"00000500", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 62.5MHz)  ???
+--	x"0002001F" --	R31	(ReadbackReg=0	Regs:unlocked)			001F001F	
+--	);								
+-- CONSTANT TAB80 : RomType := -- 80MHz
+	-- ( 
+	-- x"00020000", -- R0 (Reset=1)		
+	-- x"00000400", -- R0 (Reset=0)		
+	-- X"00000400", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz)
+	-- X"00000401", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+	-- X"00000402", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+	-- X"00000403", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+	-- X"00000404", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+	-- X"00000405", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=40 OUT2,3 80MHz)
+	-- x"11110006", --	R6 (OUT	3,2,1,0:LVDS, no delay)
+	-- x"11110007", --	R7 (OUT	7,6,5,4:LVDS, no delay)
+	-- x"11110008", --	R8 (OUT	11,10,9,8:LVDS, no delay)
+	-- x"55555549", --	R9 (fixed pattern)			
+	-- x"0000806A", --	R10	(OSCout1=LVPECL-700mV, OSCout0=disabled, OSCout1,0=disabled, OSC0,1=bypass_divider, OSCoutDIV=8, VCOdiv=1, FEEDbackMUX=CLKout6)
+	-- x"4400800B", --	R11	(mode=singlePLL, 0delay, SYNC=enabled, active=high, SYNC_QUAL=0?, auto_sync=1, sSYNC=input, externalXTAL=disabled)			
+	-- x"030000aC", --	R12	(LD[31..27]=0, LD_type[26..24]=3, SYNC_PLLX_DLD[23..22]=0, EN_TRACK[8]=disable, force_SYNC, no DAC tracking, no HOLDOVER)		
+	-- x"6B00800D", --3B...	R13	(HOLDOVER pin=uwire, status pins=0, no DLD1DET, status CLKin=0, CLKin not used)			
+	-- x"0000000E", --	R14	(LOS after 1200ns, CLKin not used, no DAC trip)				
+	-- x"8000800F", --	R15	(MAN_DAC=512, disabled, HOLDOVER count=512, disabled)				
+	-- x"01550410", --	R16	(xtal=1.65V, fixed pattern)		
+	-- x"000000D8", --	R24	(LoopFilter: C4=10pF C3=10pF R4=200Ohm R3=200Ohm, delay=0ps, window=40ns)	-- DD0000D8
+	-- x"010100D9", --	R25	(DAC clkdiv=4, PLL2 DLD cont=1024)
+	-- x"83A8001A", --	R26	(PLL2 window=3.7ns, no 2*frequ, neg slope, chargepump=100u, PLL2 DLD count=8192???, CPout2=active)	
+	-- x"0008003B", --	R27	(PLL1 not used: neg slope, div=1, PLL1 DLD count=8192, CPout1=tristate)	
+	-- x"0010005C", --	R28	(PLL2 R_divider=1, PLL1 N_divider=1)
+	-- x"0100015D", --	R29	(OSCin=63..127MHz, <100MHz, PLL2 N_CALdivider=10)
+	-- x"0400015E", --	R30	(N_prescaler=4, N_divider=10)				
+--//--	X"00000400", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz)  ???
+	-- x"000b001F" --	R31	(ReadbackReg=11	Regs:unlocked)			001F001F	
+	-- );	
+
+
+-- CONSTANT TAB_orig : RomType := -- test
+	-- ( 
+	-- x"00020000", -- R0 (Reset=1)		
+	-- x"00000400", -- R0 (Reset=0)		
+	-- X"00000400", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=32 OUT0,1 80MHz)
+	-- X"00000401", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+	-- X"00000402", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+	-- X"00000403", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+	-- X"00000404", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+	-- X"00000405", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+	-- x"11110006", --	R6 (OUT	3,2,1,0:LVDS, no delay)
+	-- x"11110007", --	R7 (OUT	7,6,5,4:LVDS, no delay) x"61160007", for cmos_out
+	-- x"11110008", --	R8 (OUT	11,10,9,8:LVDS, no delay)
+	-- x"55555549", --	R9 (fixed pattern)			
+	-- x"1000480A", --	R10	(OSCout1[31..30]=700mV, OSCout0[27..24]=disabled, OSCout1,0[23..22]=disabled, OSC0,1[21..20]=bypass_divider, PD_OSCin[19]=0(powered), OSCoutDIV[18..16]=8, VCOdiv[12]=select, EN_FEEDBACK_MUX[11]=1, VCOdiv[10..8]=8 FEEDbackMUX[7..5]=3=CLKout6)
+	-- x"4402800B", --   R11	(mode[31..27]=singlePLL+0delay, SYNC[26]=enabled, NO_SYNC_CLKoutX_Y[25..20]=0, SYNC_mux[19..18]=0, SYNC_QUAL[17]=1, sync[16]=0=high, auto_sync[15]=1, sSYNC[14..12]=input, externalXTAL[5]=disabled)			
+	-- x"0300006C", --	R12	(LD[31..27]=0, LD_type[26..24]=3, SYNC_PLLX_DLD[23..22]=0, EN_TRACK[8]=disable, HOLDOVER[7..6]=disable)		
+	-- x"9300000D", --..3B	R13	(HOLDOVER_pin[31..27]=uwire, output[26..25]=pushpull, CLK1_mux[22..20]=0, CLK0_mux[18..16]=0, DLD1DET[15]=0,CLKin[14..12]=0, CLKin_mode[11..9]=0, CLKin[8]=high, EN_CLKinX[6..5]=0			
+	-- x"0000000E", --	R14	(LOS[31..30] after 1200ns, LOS[28]=disabled,  CLKin[26..24], CLKinX_BUF_TYPE[21..20]=0, DAC_trip[19..14][11..6]=0, EN_VTUNE_RAIL_DET[5]=0)				
+   -- x"0000004F", --   R15   (MAN_DAC [31:22]=0 (sets dac value when in manual DAC mode, set to 0), EN_MAN_DAC[20]=0 (enables manual DAC), HOLDOVER DLD+CNT[19:6]=1 (how many clocks of PLL1 PDF before HOLDOVER mode is exited. 1, I guess, if we're not using holdover mode), FORCE_HOLDOVER[5]=0,(diabled))
+	-- x"01550410", --	R16	(xtal=1.65V, fixed pattern)		
+	-- x"00000018", --   R24   (PLL2_C4_LF[31:28]=0(10pF), PLL2_C3_LF[27:23]=0(10pF), PLL2_R4_LF[22:20]=0(200 Ohm), PLL2_R3_LF[18:16]=0(200 Ohm), PLL1_N_DLY[14:12]=0 (PLL1, doesn't matter and setting to 0 delay), PLL1_R_DLY[10:8]=0(same), PLL1_WIND_SIZE[7:6]=0 (setting 0)
+	-- x"00400059", --   R25   (DAC_CLK_DIV[31:22]=1 (PLL1 relevant, setting to 1), PLL1_DLD_CNT[19:6]=1, 
+	-- x"8fA0801A", --   R26	(PLL2 window[31:30]=3.7ns, PLL2_doublefreq[29]=0, slope[28]=neg, chargepump[27..26]=max?100u, PLL2 DLD count19..6]=1024, CPout2[5]=active)	
+	-- x"0008003B", --	R27	(PLL1 not used: slope[28]=neg, div=1, PLL1 DLD count=8192, CPout1=tristate)	
+	-- x"0018001C", --	R28	(PLL2 R_divider[31..20]=1, PLL1 N_divider[19..6]=maxbit)
+	-- x"0100009D", --	R29	(OSCin[26..24]=63..127MHz, phasedet[23]<100MHz, PLL2 N_CALdivider[22..5]=DIVX*PLL2_N/PLL2_P=32*1/8=4)
+	-- x"0000003E", --	R30	(N_prescaler=PLL2_P[26:24]=8, not used, PLL1_N_divider[22..5]=1)				
+--	x"00000f00", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz)  ???
+	-- x"002b001F" --	R31	(LE must be high ReadbackReg=2	Regs:unlocked)			001F001F	
+	-- );	
+
+constant TAB : RomType := 
+	( 
+	x"00020000", -- R0 (Reset=1)		
+	x"00000400", -- R0 (Reset=0)		
+	X"00000400", -- R0, out0,1 (Power_Down=0, input=VCO, delay=off, Reset=0, Div=32 OUT0,1 80MHz)
+	X"00000401", -- R1, out2,3 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+	X"00000402", -- R2, out4,5 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+	X"00000403", -- R3, out6,7 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz) GTX & gclk
+	X"00000404", -- R4, out8,9 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+	X"00000405", -- R5, out10,11 (Power_Down=0, input=VCO, delay=off, powerdown=0, Div=32 OUT2,3 80MHz)
+	x"11110006", --	R6 (OUT	3,2,1,0:LVDS, no delay)
+	x"11110007", --	R7 (OUT	7,6,5,4:LVDS, no delay) x"61160007", for cmos_out
+	x"11110008", --	R8 (OUT	11,10,9,8:LVDS, no delay)
+	x"55555549", --	R9 (fixed pattern)			
+	x"1000486A", --	R10	(OSCout1[31..30]=700mV, OSCout0[27..24]=disabled, OSCout1,0[23..22]=disabled, OSC0,1[21..20]=bypass_divider, PD_OSCin[19]=0(powered), OSCoutDIV[18..16]=8, VCOdiv[12]=select, EN_FEEDBACK_MUX[11]=1, VCOdiv[10..8]=8 FEEDbackMUX[7..5]=3=CLKout6)
+	x"4402a00B", --   R11	(mode[31..27]=singlePLL+0delay, SYNC[26]=enabled, NO_SYNC_CLKoutX_Y[25..20]=0, SYNC_mux[19..18]=0, SYNC_QUAL[17]=1, sync[16]=0=high, auto_sync[15]=1, sSYNC[14..12]=input, externalXTAL[5]=disabled)			
+	x"030C006C", --	R12	(LD[31..27]=0, LD_type[26..24]=3, SYNC_PLLX_DLD[23..22]=0, EN_TRACK[8]=disable, HOLDOVER[7..6]=disable)		
+	x"2300000D", --..3B	R13	(HOLDOVER_pin[31..27]=status, output[26..25]=pushpull, CLK1_mux[22..20]=0, CLK0_mux[18..16]=0, DLD1DET[15]=0,CLKin[14..12]=0, CLKin_mode[11..9]=0, CLKin[8]=high, EN_CLKinX[6..5]=0			
+	x"0000000E", --	R14	(LOS[31..30] after 1200ns, LOS[28]=disabled,  CLKin[26..24], CLKinX_BUF_TYPE[21..20]=0, DAC_trip[19..14][11..6]=0, EN_VTUNE_RAIL_DET[5]=0)				
+	x"0000004F", --   R15   (MAN_DAC [31:22]=0 (sets dac value when in manual DAC mode, set to 0), EN_MAN_DAC[20]=0 (enables manual DAC), HOLDOVER DLD+CNT[19:6]=1 (how many clocks of PLL1 PDF before HOLDOVER mode is exited. 1, I guess, if we're not using holdover mode), FORCE_HOLDOVER[5]=0,(diabled))
+	x"01550410", --	R16	(xtal=1.65V, fixed pattern)		
+	x"88110018", --   R24   (PLL2_C4_LF[31:28]=8(29pF), PLL2_C3_LF[27:23]=0(29pF), PLL2_R4_LF[22:20]=1(1k), PLL2_R3_LF[18:16]=1(1k), PLL1_N_DLY[14:12]=0 (PLL1, doesn't matter and setting to 0 delay), PLL1_R_DLY[10:8]=0(same), PLL1_WIND_SIZE[7:6]=0 (setting 0)
+	x"00400059", --   R25   (DAC_CLK_DIV[31:22]=1 (PLL1 relevant, setting to 1), PLL1_DLD_CNT[19:6]=1, 
+	x"87A0801A", --   R26	(PLL2 window[31:30]=3.7ns, PLL2_doublefreq[29]=0, slope[28]=neg, chargepump[27..26]=11=3200,01=400,00=100u, PLL2 DLD count19..6]=1024, CPout2[5]=active)	
+	x"0008003B", --	R27	(PLL1 not used: slope[28]=neg, div=1, PLL1 DLD count=8192, CPout1=tristate)	
+	x"0018001C", --	R28	(PLL2 R_divider[31..20]=1, PLL1 N_divider[19..6]=maxbit)
+	x"0100009D", --	R29	(OSCin[26..24]=63..127MHz, phasedet[23]<100MHz, PLL2 N_CALdivider[22..5]=DIVX*PLL2_N/PLL2_P=32*1/8=4)
+	x"0000003E", --	R30	(N_prescaler=PLL2_P[26:24]=8, not used, PLL1_N_divider[22..5]=1)				
+--	x"00000f00", -- R0, again to force SYNC (Power_Down=0, input=VCO, delay=off, Reset=0, Div=40 OUT0,1 80MHz)  ???
+	x"002b001F" --	R31	(LE must be high ReadbackReg=2	Regs:unlocked)			001F001F	
+	);	
+	
+--CONSTANT TAB_Pawel : RomType := -- |Pawel
+--		(
+--    x"80020140", --R0 (CLKout_1_PD = 1, RESET=1, CLKout0_1_DIV=10)
+--    x"000003C0", --R0 (CLKout0_1_DIV=30)
+--    x"000003C0", --R0 (CLKout0_1_DIV=30)
+--    x"000003C0", --R0 (CLKout0_1_DIV=30)
+--    x"000003C1", --R1 (CLKout2_3_DIV=30)
+--    x"00000602", --R2 (CLKout4_5_DIV=48) --35
+--    --00000000000000000000010110100010
+--    x"00000603", --R3 (CLKout6_7_DIV=48)
+--    x"000003C4", --R4 (CLKout8_9_DIV=30)
+--    x"000003C5", --R5 (CLKout10_11_DIV=30)
+--    x"11110006", --R6 (CLKout3_TYPE=1, CLKout2_TYPE=1, CLKout1_TYPE=1, CLKout0_TYPE=1)
+--    x"11110007", --R7 (CLKout7_TYPE=1, CLKout6_TYPE=1, CLKout5_TYPE=1, CLKout4_TYPE=1)
+--    x"11110008", --R8 (CLKout11_TYPE=1, CLKout10_TYPE=1, CLKout9_TYPE=1, CLKout8_TYPE=1)
+--    x"55555549", --R9 (fixed pattern)
+--    x"910141CA", --R10 (OSCout1_LVPECL_AMP=3(-1600mV), OSCout0_TYPE=1(LVDS), EN_OSCout1[23]=0 (disabled), EN_OSCout0[22]=0 (disabled), OSCout1_MUX[21]=0 (bypass MUX), OSC_out1_MUX[20]=0(bypass MUX), PD_OSCin[19]=0(powered), OSCout_DIV[18:16]=2(divide by 2), VCO_MUX[12]=0(select VCO), EN_FEEDBACK_MUX[11]=0 (feedback mux powered down), VCO_DIV[10:8]=2(divide by 2), FEEDBACK_MUX[7:5]=3(guess it doens't matter. taking FBCLKin)
+--    x"2400800D", --R11 
+--    x"130C006C", --R12 (LD_MUX[31:27]=2 (PLL2 DLD (digital lock detect)), LD_TYPE[26:24]=3 (output push-pull), SYNC_PLL2_DLD[23]=0? (sync not forced), SYNC_PLL1_DLD[22]=0? (sync not forced), EN_TRACK[8]=0 (tracks the PLL1` which we're not using, set to 0), HOLDOVER_MODE[7:6]=1 (disabled))
+--    x"0301880D", --R13 (holdover_mux[31:27]=0 (logic low), holdover_type[26:24]=3(output (push-pull)), status_clkin1_mux[22:20]=0(logic low), status_clkin0_Type[18:16]=1 (they're both disconnected as far as I can tell, thus we want pull-up), disable_dld1_det[15]=1(disables, because we won't use PLL1), status+clkin0_mux[14:12]=0(logic low), clkin_select_mode[11:9]=4(I  think this is the case, take auto, because I don't think it will be used), clk_in_select_inv[7]=0 (not inversed), en_clkin1[6]=0 (disable), en_clkin0[5]=0 (diable)
+--    x"013FC00E", --R14 !!!see above!!!
+--    x"0000004F", --R15 (MAN_DAC [31:22]=0 (sets dac value when in manual DAC mode, set to 0), EN_MAN_DAC[20]=0 (enables manual DAC), HOLDOVER DLD+CNT[19:6]=1 (how many clocks of PLL1 PDF before HOLDOVER mode is exited. 1, I guess, if we're not using holdover mode), FORCE_HOLDOVER[5]=0,(diabled))
+--    x"01550410", --R16 (XTAL_LVL[31:30]=0 (sets the peak amplitude on the tunable crystal. --assuming 0, the lowest))
+--    x"00000018", --R24 (PLL2_C4_LF[31:28]=0(10pF), PLL2_C3_LF[27:23]=0(10pF), PLL2_R4_LF[22:20]=0(200 Ohm), PLL2_R3_LF[18:16]=0(200 Ohm), PLL1_N_DLY[14:12]=0 (PLL1, doesn't matter and setting to 0 delay), PLL1_R_DLY[10:8]=0(same), PLL1_WIND_SIZE[7:6]=0 (setting 0)
+--    x"00400059", --R25 (DAC_CLK_DIV[31:22]=1 (PLL1 relevant, setting to 1), PLL1_DLD_CNT[19:6]=1, 
+--    x"4FA8001A", --R26 (PLL2_WIND_SIZE[31:30]=2 (has to be =2 according to documentation), EN_PLL2_REF_2X[29]=0 (according to schematics), PLL2_CP_POL[28]=0 (must be negative to use internal VCO), PLL2_CP_GAIN[27:26]=3 (according to  LMK03806), PLL2_DLD_CNT[19:6]=2000 (leftmost bit =1 according to LMK03806), PLL2_CP_TRI=0 (according to LMK03806)
+--    x"0000005B", --R27 (PLL1_CP_POL[28]=0, PLL1_CP_GAIN[27:26]=0, CLKin1_PreR_DIV[23:22]=0, CLKin0_PreR_DIV[21:20]=0, PLL1_R[19:6]=1, PLL1_CP_TRI=0(because PLL1_CP_GAIN is not equal to XXXX)
+--    x"0010005C", --R28 (PLL2_R[31:20]=1, PLL1_N[19:6]=1(not used))
+--    --!!!    0000 0000 0XXX XXXX XXXX XXXX XX11 1101 --R29
+--    --x"0000003D", --R29 !!!see above!!!
+--    x"0100021D", --R29
+--    x"0200021E", --R30 (PLL2_P[26:24]=2, PLL2_N[22:5]=16)
+--    x"001F001F" --R31 (READBACK_LE[21] (guessing low)=0, READBACK_ADDRESS[20:16]=31 (from LMK03806), uWire_LOCK[5]=0 (from LMK03806)n
+--        );
+	
+type stage_type is (waiting,starting,DATAu_set,CLKu_high,CLKu_low,LEu_wait,
+							LEu_high,LEu_high0,LEu_high1,LEu_high2,LEu_high3,LEu_high4,LEu_high5,LEu_low,reading0,reading1,lockdelay);
+signal stage_S                : stage_type := waiting;
+	
+signal cnt_dly                    : std_logic_vector(3 downto 0) := (others => '0'); 
+signal regcount_S                 : integer range 0 to NROFREGS-1 := 0; 
+signal bitcount_S                 : integer range 0 to 31 := 31; 
+signal lockcount_S                : std_logic_vector(11 downto 0) := (others => '0'); 
+
+signal boot_PLL_S                 : std_logic := '0';
+signal CLKu_S                     : std_logic;
+signal DATAu_S                    : std_logic;
+signal LEu_S                      : std_logic;
+signal SYNC_S                     : std_logic;
+
+
+--------------------------------------------------------------------
+BEGIN
+
+
+booting <= '0' when (stage_S=waiting) else '1';
+SYNC_S <= '0';
+SYNC <= SYNC_S;
+CLKu <= CLKu_S;
+DATAu <= DATAu_S;
+LEu <= LEu_S;
+SYNC <= SYNC_S;
+
+--******************************************************************
+--							PLL BOOT STATEMACHINE
+--******************************************************************  
+
+process(clock,reset)
+begin
+   if reset = '1' then
+		stage_S <= waiting;
+		CLKu_S <= '0';
+		DATAu_S <= '0';
+		LEu_S <= '0';
+	elsif rising_edge(clock) then
+--//		boot_PLL_S <= boot_PLL;
+		case stage_S is
+			when waiting =>
+				CLKu_S <= '0';
+				DATAu_S <= '0';
+				LEu_S <= '0';
+				bitcount_S <= 31;
+				regcount_S <= 0;
+--//				if (boot_PLL='1') then --and (boot_PLL_S='0') then 
+				if (boot_PLL='1') or (boot_PLL_S='1') then --and (boot_PLL_S='0') then 
+					stage_S <= starting;
+				end if;
+				cnt_dly <= (others => '0');
+				lockcount_S <= (others => '0');
+			when starting =>
+				CLKu_S <= '0';
+				DATAu_S <= '0';
+				LEu_S <= '0';
+				stage_S <= DATAu_set;
+			when DATAu_set =>
+				CLKu_S <= '0';
+				DATAu_S <= TAB(regcount_S)(bitcount_S);
+				LEu_S <= '0';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					stage_S <= CLKu_high;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+			when CLKu_high =>
+				CLKu_S <= '1';
+				LEu_S <= '0';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					stage_S <= CLKu_low;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+			when CLKu_low =>
+				CLKu_S <= '0';
+				LEu_S <= '0';
+				cnt_dly <= (others => '0');
+				if bitcount_S>0 then
+					bitcount_S <= bitcount_S-1;
+					stage_S <= DATAu_set;
+				else
+					stage_S <= LEu_wait;
+				end if;
+			when LEu_wait =>
+				CLKu_S <= '0';
+				LEu_S <= '0';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					stage_S <= LEu_high;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+			when LEu_high =>
+				CLKu_S <= '0';
+				LEu_S <= '1';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					if conv_integer(unsigned(TAB(regcount_S)(4 downto 0)))<6 then
+						stage_S <= LEu_high0;
+					else
+						stage_S <= LEu_low;
+					end if;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+				
+			when LEu_high0 =>
+				CLKu_S <= '1';
+				LEu_S <= '1';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					stage_S <= LEu_high1;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+			when LEu_high1 =>
+				CLKu_S <= '0';
+				LEu_S <= '1';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					stage_S <= LEu_high2;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+			when LEu_high2 =>
+				CLKu_S <= '1';
+				LEu_S <= '1';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					stage_S <= LEu_high3;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+			when LEu_high3 =>
+				CLKu_S <= '0';
+				LEu_S <= '1';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					stage_S <= LEu_high4;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+			when LEu_high4 =>
+				CLKu_S <= '1';
+				LEu_S <= '1';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					stage_S <= LEu_high5;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+			when LEu_high5 =>
+				CLKu_S <= '0';
+				LEu_S <= '1';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					stage_S <= LEu_low;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+				
+			when LEu_low =>
+				CLKu_S <= '0';
+--				LEu_S <= '0';
+				if regcount_S<NROFREGS-1 then
+					bitcount_S <= 31;
+					LEu_S <= '0';
+					regcount_S <= regcount_S+1;
+					stage_S <= DATAu_set;
+				else
+					bitcount_S <= 26;
+					LEu_S <= '1';
+					stage_S <= reading0;
+				end if;
+			when reading0 =>
+				CLKu_S <= '0';
+				LEu_S <= '1';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					stage_S <= reading1;
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+			when reading1 =>
+				CLKu_S <= '1';
+				LEu_S <= '1';
+				if cnt_dly > CLK_DIV then
+					cnt_dly <= (others => '0');
+					if bitcount_S>0 then
+						bitcount_S <= bitcount_S-1;
+						stage_S <= reading0;
+					else
+						bitcount_S <= 31;
+						stage_S <= lockdelay;
+					end if;					
+				else 
+					cnt_dly <= cnt_dly + 1;
+				end if;
+			when lockdelay =>
+				if lockcount_S(lockcount_S'left)='0' then
+					lockcount_S <= lockcount_S+1;
+				else
+					stage_S <= waiting;  
+				end if;
+    		when others =>
+				stage_S <= waiting;  
+		end case;
+	end if;
+end process;	
+
+
+
+END Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/ADC_SLOW_CTRL.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/ADC_SLOW_CTRL.vhd
new file mode 100644
index 0000000..8405b66
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/ADC_SLOW_CTRL.vhd
@@ -0,0 +1,155 @@
+-----------------------------------------------------------
+-- 					LTM9009 SLOW CONTROL UNIT					--
+-----------------------------------------------------------
+--	Device: xc7vlx160t-1ffG484										--
+--
+-- created by P. Marciniewski										--
+-- Uppsala University, Dept of Physics and Astronomy		--
+-----------------------------------------------------------	
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use work.panda_pkg.all;
+use work.util_pack.ALL;
+
+library UNISIM;
+use UNISIM.VComponents.all;
+
+
+entity LTM9009_SLOW_CONTROL is
+	PORT( 
+		CLK75                   : in	std_logic; 
+		RES                     : in	std_logic; 
+		SCK                     : out	std_logic;
+		SDI                     : in	std_logic_vector(7 downto 0);
+		SDO                     : out	std_logic; 
+		CS                      : out	std_logic_vector(7 downto 0)
+	);
+end LTM9009_SLOW_CONTROL;
+
+----------------------------------------------------------------
+
+architecture Behavioral of LTM9009_SLOW_CONTROL is
+
+    signal clk_cnt              : std_logic_vector(6 downto 0); 
+    signal sck_i                : std_logic;
+    signal sdo_sh               : std_logic_vector(15 downto 0); 
+    signal vio_vector           : std_logic_vector(19 downto 0); 
+    signal bit_cnt              : std_logic_vector(3 downto 0);
+    signal sequencer_stm        : std_logic_vector(1 downto 0);          
+    signal adc_adr              : std_logic_vector(2 downto 0);      
+    signal adc_rd               : std_logic;      
+	 signal sdi_sh               : std_logic_vector(7 downto 0); 
+	 signal adc_ctrl_ila_vector : std_logic_vector(31 downto 0);
+	 signal adc_ctrl_vio_vector  : std_logic_vector(19 downto 0);
+
+	 
+BEGIN
+
+--    vio_vector <= "00010000000101101001";
+	adc_rd <= vio_vector(15);
+    adc_adr <= vio_vector(18 downto 16);
+
+----------------------------------------------------------------------------------------------
+--                               CLOCK DIVIDER
+----------------------------------------------------------------------------------------------
+
+    process(RES,CLK75)
+    begin
+		  if RES = '1' then 
+			   clk_cnt <= "0000000";
+		  elsif rising_edge(CLK75) then 
+            clk_cnt <= clk_cnt + 1;
+        end if;
+    end process;
+
+    sc_clk_bufg: BUFG
+    PORT MAP (
+--         I => clk_cnt(1),
+         I => clk_cnt(6),
+         O => sck_i
+    );
+
+----------------------------------------------------------------------------------------------
+--                          SEQUENCER STATE MACHINE
+----------------------------------------------------------------------------------------------
+    
+    process(RES,sck_i)
+    begin
+		  if RES = '1' then 
+			   sdo_sh 				<= x"0000";
+				bit_cnt 				<= x"0";
+				sequencer_stm 		<= "00";
+				
+        elsif rising_edge(sck_i) then
+
+            vio_vector <=  adc_ctrl_vio_vector;
+
+            case sequencer_stm is
+                when "00" =>  
+                    sdo_sh  <= vio_vector(15 downto 0);
+                    bit_cnt <= x"0";
+                    if vio_vector(19) = '1' then
+                        sequencer_stm <= "01";
+                    end if;
+                when "01" =>  
+                    sdo_sh <= sdo_sh(14 downto 0) & '0';                   
+                    if bit_cnt = 15 then
+								sequencer_stm <= "10";                      
+                    else
+                        bit_cnt <= bit_cnt + 1;
+                    end if;                
+                when "10" =>  
+                    if vio_vector(19) = '0' then
+                        sequencer_stm <= "00";
+                    end if;        
+                when others =>          
+                        sequencer_stm <= "00";
+            end case;
+        end if;            
+    end process;        
+
+----------------------------------------------------------------------------------------------
+--                          INPUT MULTIPLEXER
+----------------------------------------------------------------------------------------------
+
+   process(RES,sck_i)
+	begin
+		if RES = '1' then 
+			sdi_sh 				<= x"00";			
+		elsif falling_edge(sck_i) then
+			if sequencer_stm = "01" then 
+				if (adc_rd = '1' and bit_cnt > 7) then
+				sdi_sh(0) <= SDI(slv2int(adc_adr));
+				sdi_sh(7 downto 1) <= sdi_sh(6 downto 0);
+				end if;
+			end if;
+		end if;	
+	end process;
+
+----------------------------------------------------------------------------------------------
+--                          OUTPUT BUFFERS
+----------------------------------------------------------------------------------------------
+
+ 	SCK 		<= not clk_cnt(1) when sequencer_stm = "01" else '1'; 
+	SDO 		<= sdo_sh(15) when sequencer_stm = "01" else '1';
+	CS_DEMUX: for i in 0 to 7 generate		
+		process(sequencer_stm, adc_adr)
+		 begin
+			if sequencer_stm = "01" then 
+				if (int2slv(i,4) = '0' & adc_adr) then
+					CS(i)	 	<= '0';
+				else
+					CS(i)	 	<= '1';
+				end if;
+			else
+				CS(i)	 	<= '1';
+			end if;
+		end process;
+	end generate;
+--    adc_ctrl_vio_vector <= "00000000000000000000";
+
+END Behavioral;
diff --git a/FEE_ADC32board/modules/ADCrefdesign/AdcClock.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcClock.vhd
similarity index 75%
rename from FEE_ADC32board/modules/ADCrefdesign/AdcClock.vhd
rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcClock.vhd
index 1a22311..a5d2b49 100644
--- a/FEE_ADC32board/modules/ADCrefdesign/AdcClock.vhd
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcClock.vhd
@@ -1,523 +1,485 @@
------------------------------------------------------------------------------------------------
--- © Copyright 2007 - 2009, Xilinx, Inc. All rights reserved.
--- This file contains confidential and proprietary information of Xilinx, Inc. and is
--- protected under U.S. and international copyright and other intellectual property laws.
------------------------------------------------------------------------------------------------
---
--- Disclaimer:
---		This disclaimer is not a license and does not grant any rights to the materials
---		distributed herewith. Except as otherwise provided in a valid license issued to you
---		by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
---		ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
---		WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
---		TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
---		PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
---		negligence, or under any other theory of liability) for any loss or damage of any
---		kind or nature related to, arising under or in connection with these materials,
---		including for any direct, or any indirect, special, incidental, or consequential
---		loss or damage (including loss of data, profits, goodwill, or any type of loss or
---		damage suffered as a result of any action brought by a third party) even if such
---		damage or loss was reasonably foreseeable or Xilinx had been advised of the
---		possibility of the same.
---
--- CRITICAL APPLICATIONS
---		Xilinx products are not designed or intended to be fail-safe, or for use in any
---		application requiring fail-safe performance, such as life-support or safety devices
---		or systems, Class III medical devices, nuclear facilities, applications related to
---		the deployment of airbags, or any other applications that could lead to death,
---		personal injury, or severe property or environmental damage (individually and
---		collectively, "Critical Applications"). Customer assumes the sole risk and
---		liability of any use of Xilinx products in Critical Applications, subject only to
---		applicable laws and regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 
---
---		Contact:    e-mail  hotline@xilinx.com        phone   + 1 800 255 7778
---   ____  ____
---  /   /\/   /
--- /___/  \  /   Vendor: Xilinx
--- \   \   \/    Version: 
---  \   \        Filename: AdcClock.vhd
---  /   /        Date Last Modified:  	16 Jun 09
--- /___/   /\    Date Created: 			08/06/06
--- \   \  /  \
---  \___\/\___\
--- 
--- Device: 		Virtex-6
--- Author:		Marc Defossez
--- Entity Name:	AdcClock
--- Purpose: 	High-speed local clock control for an interface between a FPGA and a
---				Texas Instruments ADC.
--- Tools:		ISE - XST
--- Limitations: none
---
--- Revision History:
---    Rev. 
---
------------------------------------------------------------------------------------------------
--- Naming Conventions:
---   active low signals:                    "*_n"
---   clock signals:                         "clk", "clk_div#", "clk_#x"
---   reset signals:                         "rst", "rst_n"
---   generics:                              "C_*"
---   user defined types:                    "*_TYPE"
---   state machine next state:              "*_ns"
---   state machine current state:           "*_cs"
---   combinatorial signals:                 "*_com"
---   pipelined or register delay signals:   "*_d#"
---   counter signals:                       "*cnt*"
---   clock enable signals:                  "*_ce"
---   internal version of output port:       "*_i"
---   device pins:                           "*_pin"
---   ports:                                 "- Names begin with Uppercase"
---   processes:                             "*_PROCESS"
---   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------------------------
---
-library IEEE;
-	use IEEE.std_logic_1164.all;
-	use IEEE.std_logic_UNSIGNED.all;
-	use IEEE.std_logic_arith.all;
-library UNISIM;
-	use UNISIM.VCOMPONENTS.all;
------------------------------------------------------------------------------------------------
--- Entity pin description
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-entity AdcClock is
-	generic (
-	   C_BufioLoc  : string := "BUFIODQS_X0Y12";
-	   C_BufrLoc   : string := "BUFR_X0Y6";
-	   C_AdcBits   : integer := 16;
-	   C_StatTaps  : integer := 16
-	);
-    port (
-        BitClk				: in std_logic;
-        BitClkRst			: in std_logic;
-        BitClkEna			: in std_logic;
-        BitClkReSync		: in std_logic;
-		  BitClkDivReset	: in std_logic;
-        BitClk_MonClkOut	: out std_logic;   -- CLK output
-        BitClk_MonClkIn		: in std_logic;    -- ISERDES.CLK input
-        BitClk_RefClkOut	: out std_logic;   -- CLKDIV & logic output
-        BitClk_RefClkIn		: in std_logic;    -- CLKDIV & logic input
-        BitClkAlignWarn 	: out std_logic;
-		BitClkInvrtd		: out std_logic;
-        BitClkDone 			: out std_logic
-    );
-end AdcClock;
------------------------------------------------------------------------------------------------
--- Arcitecture section
------------------------------------------------------------------------------------------------
-architecture AdcClock_struct of AdcClock is
------------------------------------------------------------------------------------------------
--- Component Instantiation
------------------------------------------------------------------------------------------------
--- Components are instantiated by means / through the use of library references.
------------------------------------------------------------------------------------------------
--- Constants, Signals and Attributes Declarations
------------------------------------------------------------------------------------------------
--- Constants
-constant Low	: std_logic := '0';
-constant LowNibble : std_logic_vector(4 downto 0) := "00000";
-constant High : std_logic := '1';
--- Signals
-signal IntBitClkRst				: std_logic;
----------- ISRDS signals ------------------
-signal IntClkCtrlDlyCe			: std_logic;
-signal IntClkCtrlDlyInc			: std_logic;
-signal IntClkCtrlDlyRst			: std_logic;
-
-signal IntBitClk_Ddly			: std_logic;
-signal IntBitClk				: std_logic;
-signal IntClkCtrlIsrdsMtoS1		: std_logic;
-signal IntClkCtrlIsrdsMtoS2		: std_logic;
-signal IntClkCtrlOut			: std_logic_vector(7 downto 0);
----------- Controller signals -------------
-signal IntCal					: std_logic;
-signal IntVal					: std_logic;
-signal IntCalVal				: std_logic_vector (1 downto 0);
-signal IntProceedCnt			: std_logic_vector (2 downto 0);
-signal IntproceedCntTc			: std_logic;
-signal IntproceedCntTc_d		: std_logic;
-signal IntProceed				: std_logic;
-signal IntProceedDone			: std_logic;
-
-type StateType is (Idle, A, B, C, D, E, F, G, G1, H, K, K1, K2, IdlyIncDec, Done);
-signal State : StateType;
-signal ReturnState : StateType;
-
-signal PassedSubState		: std_logic;
-signal IntNumIncDecIdly		: std_logic_vector (3 downto 0);
-signal IntAction			: std_logic_vector (1 downto 0);
-signal IntClkCtrlDone 		: std_logic;
-signal IntClkCtrlAlgnWrn	: std_logic;
-signal IntClkCtrlInvrtd		: std_logic;
-signal IntTurnAroundBit		: std_logic;
-signal IntCalValReg			: std_logic_vector (1 downto 0);
-signal IntTimeOutCnt		: std_logic_vector (3 downto 0);
-signal IntStepCnt	 		: std_logic_vector (3 downto 0);
--- Attributes
-attribute LOC : string;
-    attribute LOC of AdcClock_I_Bufio : label is C_BufioLoc;
--- The BUFR is generated through a generate statement and therefore the LOC attribute
--- must be place into the generate statement.
--- See the BUFR generation down in the source code.
------------------------------------------------------------------------------------------------
-signal reset_clockdiv_S		: std_logic;
-		
-		
-begin
------------------------------------------------------------------------------------------------
--- Bit clock capture ISERDES Master-Slave combination
------------------------------------------------------------------------------------------------
---
-AdcClock_I_Iodly : IODELAYE1
-	generic map (
-		SIGNAL_PATTERN			=> "CLOCK",
-		REFCLK_FREQUENCY		=> 200.0,		
-		HIGH_PERFORMANCE_MODE	=> TRUE,
-		DELAY_SRC				=> "I",
-		CINVCTRL_SEL			=> FALSE,
-		IDELAY_TYPE				=> "VARIABLE",
-		IDELAY_VALUE			=> C_StatTaps,
-		ODELAY_TYPE				=> "FIXED",
-		ODELAY_VALUE			=> 0
-	)
-	port map (
-		DATAIN		=> Low,				-- in	input from FPGA fabric
-		IDATAIN		=> BitClk,			-- in	input from IOB
-		ODATAIN		=> Low,				-- in	input from I/O SERDES
-		CLKIN		=> Low,				-- in	input from BUFIO. BUFG, or BUFR
-		CE			=> IntClkCtrlDlyCe, -- in
-		INC			=> IntClkCtrlDlyInc, -- in
-		C			=> BitClk_RefClkIn,	-- in
-		RST			=> IntClkCtrlDlyRst, -- in				
-		T			=> Low,				-- in
-		DATAOUT		=> IntBitClk_Ddly,	-- out	Delayed data
-		CINVCTRL	=> Low,				-- in
-		CNTVALUEIN	=> LowNibble,		-- in [4:0]
-		CNTVALUEOUT	=> open				-- out [4:0]
-	);
-IntClkCtrlDlyRst <= BitClkRst;
---
-AdcClock_I_Isrds_Master : ISERDESE1
-	generic map (
-		SERDES_MODE			=> "MASTER",	-- 
-		INTERFACE_TYPE		=> "NETWORKING",-- 
-		IOBDELAY			=> "IBUF",		-- 
-		DATA_RATE 			=> "SDR", 		-- 
-		DATA_WIDTH 			=> 8,			--
-		DYN_CLKDIV_INV_EN	=> FALSE, 		-- 
-		DYN_CLK_INV_EN		=> FALSE, 		-- 
-		NUM_CE				=> 1, 			-- 
-		OFB_USED			=> FALSE 		-- 
-	)
-	port map (
-		D				=> BitClk,			-- in	Clock from clock input IBUFDS
-		DDLY			=> IntBitClk_Ddly, 	-- in
-		DYNCLKDIVSEL	=> Low, 			-- in
-		DYNCLKSEL		=> Low, 			-- in
-		OFB				=> Low, 			-- in
-		BITSLIP			=> Low,				-- in	!!!!!
-		CE1				=> BitClkEna,		-- in
-		CE2				=> Low,				-- in
-		RST				=> IntBitClkRst,	-- in
-		CLK				=> BitClk_MonClkIn,	-- in	Clock from BUFIO.O = BitClk
-		CLKB			=> Low, 			-- in
-		CLKDIV			=> BitClk_RefClkIn, -- in	Clock from BUFR.O = BitClkDiv
-		OCLK			=> Low, 			-- in
-		SHIFTOUT1		=> IntClkCtrlIsrdsMtoS1,-- out
-		SHIFTOUT2		=> IntClkCtrlIsrdsMtoS2,-- out
-		O				=> IntBitClk, 			-- out	Clock to BUFIO.I
-		Q1				=> IntClkCtrlOut(0),	-- out
-		Q2				=> IntClkCtrlOut(1),	-- out
-		Q3				=> IntClkCtrlOut(2),	-- out
-		Q4				=> IntClkCtrlOut(3),	-- out
-		Q5				=> IntClkCtrlOut(4),	-- out
-		Q6				=> IntClkCtrlOut(5), 	-- out
-		SHIFTIN1		=> Low, 				-- in
-		SHIFTIN2		=> Low 					-- in
-	);
---
-AdcClock_I_Isrds_Slave : ISERDESE1
-	generic map (
-		SERDES_MODE			=> "SLAVE",		-- 
-		INTERFACE_TYPE		=> "NETWORKING",-- 
-		IOBDELAY			=> "NONE",		-- 
-		DATA_RATE 			=> "SDR", 		-- 
-		DATA_WIDTH 			=> 8,			--
-		DYN_CLKDIV_INV_EN	=> FALSE, 		-- 
-		DYN_CLK_INV_EN		=> FALSE, 		-- 
-		NUM_CE				=> 1, 			-- 
-		OFB_USED			=> FALSE 		-- 
-	)
-	port map (
-		D				=> Low,				-- in
-		DDLY			=> Low, 			-- in
-		DYNCLKDIVSEL	=> Low, 			-- in
-		DYNCLKSEL		=> Low, 			-- in
-		OFB				=> Low, 			-- in
-		BITSLIP			=> Low,				-- in	!!!!!
-		CE1				=> BitClkEna,		-- in
-		CE2				=> Low,				-- in
-		RST				=> IntBitClkRst,	-- in
-		CLK				=> BitClk_MonClkIn,	-- in
-		CLKB			=> Low, 			-- in
-		CLKDIV			=> BitClk_RefClkIn,	-- in
-		OCLK			=> Low, 			-- in
-		SHIFTOUT1		=> open,			-- out
-		SHIFTOUT2		=> open,			-- out
-		O				=> open, 			-- out
-		Q1				=> open,			-- out
-		Q2				=> open,			-- out
-		Q3				=> IntClkCtrlOut(6),	-- out
-		Q4				=> IntClkCtrlOut(7),	-- out
-		Q5				=> open,				-- out
-		Q6				=> open, 				-- out
-		SHIFTIN1		=> IntClkCtrlIsrdsMtoS1,-- in
-		SHIFTIN2		=> IntClkCtrlIsrdsMtoS2 -- in
-	);
--- Input from ISERDES.O	  -- Output and CLK for all ISERDES
-AdcClock_I_Bufio : BUFIO
-	port map (I => IntBitClk, O => BitClk_MonClkOut);
---
-Gen_Bufr_Div_3 : if (C_AdcBits = 12) generate
-    attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc;
-begin
-	AdcClock_I_Bufr : BUFR
-		generic map (BUFR_DIVIDE => "3", SIM_DEVICE => "VIRTEX6") -- 12-bit = DIV by 3
---      ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES.
-		port map  (I => IntBitClk, O => BitClk_RefClkOut,
-					CE => High, CLR => BitClkDivReset);
-end generate;
---
-Gen_Bufr_Div_4 : if (C_AdcBits /= 12) generate
-    attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc;
-begin
-	AdcClock_I_Bufr : BUFR
-		generic map (BUFR_DIVIDE => "4", SIM_DEVICE => "VIRTEX6") -- 14- and 16-bit = DIV by 4
---      ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES.
-		port map  (I => IntBitClk, O => BitClk_RefClkOut,
-					CE	=> High, CLR => BitClkDivReset);
-end generate;
-
-
------------------------------------------------------------------------------------------------
--- Bit clock re-synchronizer
------------------------------------------------------------------------------------------------
-IntBitClkRst <= BitClkRst or BitClkReSync;
------------------------------------------------------------------------------------------------
--- Bit clock controller for clock alignment input.
------------------------------------------------------------------------------------------------
--- This input section makes sure 64 bits are captured before action is taken to pass to
--- the statemachine for evaluation.
--- 8 samples of the Bit Clock are taken by the ISERDES and then transferred to the parallel
--- FPGA world. The Proceed counter needs 8 reference clock rising edges before terminal count.
--- The Proceed counter terminal count then loads the 2 control bits (made from sampled clock)
--- into an intermediate register (IntCalVal).
---
--- IntCal = '1' when all outputs of the ISERDES are '1 else it's '0'.
--- IntVal = '1' when all outputs are '0' or '1'.
---
-IntCal <= IntClkCtrlOut(7) and IntClkCtrlOut(6) and IntClkCtrlOut(5) and
-			IntClkCtrlOut(4) and IntClkCtrlOut(3) and IntClkCtrlOut(2) and
-			IntClkCtrlOut(1) and IntClkCtrlOut(0);
-IntVal <= '1' when (IntClkCtrlOut = "11111111" or IntClkCtrlOut = "00000000") else '0';
---
-AdcClock_Proceed_PROCESS : process (BitClkEna, IntBitClkRst, BitClk_RefClkIn, IntProceedDone, IntClkCtrlDone)
-begin
-	if (IntBitClkRst = '1') then
-		IntProceedCnt <= (others => '0');
-		IntProceedCntTc_d <= '0';
-		IntCalVal <= (others => '0');
-		IntProceed <= '0';
-	elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then
-		if (BitClkEna = '1' and IntClkCtrlDone = '0') then
-			IntProceedCnt <= IntProceedCnt + 1;
-			IntProceedCntTc_d <= IntProceedCntTc;
-			if (IntProceedCntTc_d = '1') then
-				IntCalVal <= IntCal & IntVal;
-			end if;
-			if (IntProceedCntTc_d = '1') then
-				IntProceed <= '1';
-			elsif (IntProceedDone = '1') then
-				IntProceed <= '0';
-			end if;
-		end if;
-	end if;
-end process;
-IntProceedCntTc <= '1' when (IntProceedCnt = "110") else '0';
------------------------------------------------------------------------------------------------
--- Bit clock controller for clock alignment state machine.
------------------------------------------------------------------------------------------------
-BitClkAlignWarn <= IntClkCtrlAlgnWrn;
-BitClkInvrtd <= IntClkCtrlInvrtd;
-BitClkDone <= IntClkCtrlDone;
-
-AdcClock_State_PROCESS : process (BitClk_RefClkIn, IntBitClkRst, BitClkEna, IntProceed, IntCalVal)
-subtype ActCalVal is std_logic_vector (4 downto 0);
-begin
-	if (IntBitClkRst = '1') then
-		State				<= Idle;
-		ReturnState			<= Idle;
-		PassedSubState		<= '0';
-		--
-		IntNumIncDecIdly	<= "0000";	-- Max. 16
-		IntAction			<= "00";			
-		IntClkCtrlDlyInc	<= '1';
-		IntClkCtrlDlyCe		<= '0';
-		IntClkCtrlDone 		<= '0';
-		IntClkCtrlAlgnWrn	<= '0';
-		IntClkCtrlInvrtd	<= '0';
-		IntTurnAroundBit	<= '0';
-		IntProceedDone		<= '0';
-		IntClkCtrlDone		<= '0';
-		IntCalValReg		<= (others => '0');		-- 2-bit
-		IntTimeOutCnt		<= (others => '0');		-- 4-bit
-		IntStepCnt	 		<= (others => '0');		-- 4-bit (16)
-	elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then
-		if (BitClkEna = '1' and IntClkCtrlDone = '0') then
-		case State is 
-			when Idle =>
-				IntProceedDone <= '0';
-				PassedSubState <= '0';
-				case ActCalVal'(IntAction(1 downto 0) & IntCalVal (1 downto 0) & IntProceed) is
-					when "00001" => State <= A;
-					when "01001" => State <= B;
-					when "10001" => State <= B;
-					when "11001" => State <= B;
-					when "01111" => State <= C;
-					when "01101" => State <= D;
-					when "01011" => State <= D;
-					when "00011" => State <= E;
-					when "00101" => State <= E;
-					when "00111" => State <= E;
-					when "10011" => State <= F;
-					when "11011" => State <= F;
-					when "10101" => State <= F;
-					when "11101" => State <= F;
-					when "10111" => State <= F;
-					when "11111" => State <= F;
-					when others => State <= Idle;
-				end case;
-			when A => 						-- First time and sampling in jitter or cross area.
-				IntAction <= "01";					-- Set the action bits and go to next step.
-				State <= B;
-			when B =>						-- Input is samples in jitter or clock cross area.
-				if (PassedSubState = '1') then
-					PassedSubState <= '0';			-- Clear the pass through the substate bit.
-					IntProceedDone <= '1';			-- Reset the proceed bit.
-					State <= Idle;					-- Return for a new sample of the input.
-				elsif (IntTimeOutCnt = "1111") then	-- When arriving here something is wrong.
-					IntTimeOutCnt <= "0000";		-- Reset the counter.
-					IntAction <= "00";				-- reset the action bits.
-					IntClkCtrlAlgnWrn <= '1';		-- Raise a FLAG.
-					IntProceedDone <= '1';			-- Reset the proceed bit.
-					State <= Idle;					-- Retry, return for new sample of input.
-				else
-					IntTimeOutCnt <= IntTimeOutCnt + 1;
-					IntNumIncDecIdly <= "0010";		-- Number increments or decrements to do.
-					ReturnState <= State;			-- This state is the state to return too.
-					IntProceedDone <= '1';			-- Reset the proceed bit.
-					IntClkCtrlDlyInc <= '1';		-- Set for increment.
-					State <= IdlyIncDec;			-- Jump to Increment/decrement sub-state.
-				end if;
-			when C =>						-- After first sample, jitter or cross, is now high.
-				IntNumIncDecIdly <= "0010";			-- Number increments or decrements to do.
-				ReturnState <= Done;				-- This state is the state to return too.
-				IntClkCtrlDlyInc	<= '0';			-- Set for decrement.
-				State <= IdlyIncDec;
-			when D =>						-- Same as C but with indication of 180-deg shift.
-				IntClkCtrlInvrtd <= '1';
-				State <= C;
-			when E =>						-- First saple with valid data.
-				IntCalValReg <= IntCalVal;			-- Register the sampled value
-				IntAction <= "10";
-				IntProceedDone <= '1';				-- Reset the proceed bit.
-				IntNumIncDecIdly <= "0001";			-- Number increments or decrements to do.
-				ReturnState <= Idle;				-- When increment is done return sampling.
-				IntClkCtrlDlyInc <= '1';			-- Set for increment
-				State <= IdlyIncDec;				-- Jump to Increment/decrement sub-state.
-			when F =>						-- Next samples with valid data.
-				if (IntCalVal /= IntCalValReg) then
-					State <= G;				-- The new CalVal value is different from the first.
-				else
-					if (IntStepCnt = "1111") then 	-- Step counter at the end, 15
-						if (IntTurnAroundBit = '0') then 
-							State <= H;				-- No edge found and first time here.
-						elsif (IntCalValReg = "11") then
-							State <= K;			-- A turnaround already happend.
-						else					-- No edge is found (large 1/2 period).
-							State <= K1;		-- Move the clock edge to near the correct
-						end if;					-- edge.
-					else
-						IntStepCnt <= IntStepCnt + 1;
-						IntNumIncDecIdly <= "0001";	-- Number increments or decrements to do.
-						IntProceedDone <= '1';		-- Reset the proceed bit.
-						ReturnState <= Idle;		-- When increment is done return sampling.
-						IntClkCtrlDlyInc <= '1';	-- Set for increment
-						State <= IdlyIncDec;		-- Jump to Increment/decrement sub-state.
-					end if;
-				end if;
-			when G =>
-				if (IntCalValReg /= "01") then
-					IntClkCtrlInvrtd <= '1';
-					State <= G1;
-				else
-					State <= G1;
-				end if;
-			when G1 =>
-				if (IntTimeOutCnt = "00") then
-					State <= Done;
-				else
-					IntNumIncDecIdly <= "0010";	-- Number increments or decrements to do.
-					ReturnState <= Done;		-- After decrement it's finished.
-					IntClkCtrlDlyInc <= '0';	-- Set for decrement
-					State <= IdlyIncDec;		-- Jump to the Increment/decrement sub-state.
-				end if;
-			when H =>
-				IntTurnAroundBit <= '1';		-- Indicate that the Idelay jumps to 0.
-				IntStepCnt <= IntStepCnt + 1;	-- Set all registers to zero.
-				IntAction <= "00";				-- Take one step, let the counter flow over 
-				IntCalValReg <= "00";			-- The idelay turn over to 0.
-				IntTimeOutCnt <= "0000";		-- Start sampling from scratch.
-				IntNumIncDecIdly <= "0001";		-- Number increments or decrements to do.
-				IntProceedDone <= '1';			-- Reset the proceed bit.
-				ReturnState <= Idle;			-- After increment go sampling for new.
-				IntClkCtrlDlyInc <= '1';		-- Set for increment.
-				State <= IdlyIncDec;			-- Jump to the Increment/decrement sub-state.
-			when K =>
-				IntNumIncDecIdly <= "1111";		-- Number increments or decrements to do.
-				ReturnState <= K2;				-- After increment it is done.
-				IntClkCtrlDlyInc <= '1';		-- Set for increment.
-				State <= IdlyIncDec;			-- Jump to the Increment/decrement sub-state.
-			when K1 =>
-				IntNumIncDecIdly <= "1110";		-- Number increments or decrements to do.
-				ReturnState <= K2;				-- After increment it is done.
-				IntClkCtrlDlyInc <= '1';		-- Set for increment.
-				State <= IdlyIncDec;			-- Jump to the Increment/decrement sub-state.
-			when K2 =>
-				IntNumIncDecIdly <= "0001";		-- Number increments or decrements to do.
-				ReturnState <= Done;			-- After increment it is done.
-				IntClkCtrlDlyInc <= '1';		-- Set for increment.
-				State <= IdlyIncDec;			-- Jump to the Increment/decrement sub-state.
-			--
-			when IdlyIncDec =>				-- Increment or decrement by enable.
-				if (IntNumIncDecIdly /= "0000") then			-- Check number of tap jumps
-					IntNumIncDecIdly <= IntNumIncDecIdly - 1;	-- If not 0 jump and decrement.
-					IntClkCtrlDlyCe <= '1';						-- Do the jump. enable it.
-				else
-					IntClkCtrlDlyCe <= '0';		-- when it is enabled, disbale it
-					PassedSubState <= '1';		-- Set a check bit "I've been here and passed".
-					State <= ReturnState;		-- Return to origin.
-				end if;
-			when Done =>					-- Alignment done.
-				IntClkCtrlDone <= '1';				-- Alignment is done.
-		end case;
-		end if;
-	end if;
-end process;
---
-------------------------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------------------
+-- © Copyright 2012, Xilinx, Inc. All rights reserved.
+-- This file contains confidential and proprietary information of Xilinx, Inc. and is
+-- protected under U.S. and international copyright and other intellectual property laws.
+-----------------------------------------------------------------------------------------------
+--
+-- Disclaimer:
+--		This disclaimer is not a license and does not grant any rights to the materials
+--		distributed herewith. Except as otherwise provided in a valid license issued to you
+--		by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
+--		ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
+--		WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
+--		TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
+--		PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
+--		negligence, or under any other theory of liability) for any loss or damage of any
+--		kind or nature related to, arising under or in connection with these materials,
+--		including for any direct, or any indirect, special, incidental, or consequential
+--		loss or damage (including loss of data, profits, goodwill, or any type of loss or
+--		damage suffered as a result of any action brought by a third party) even if such
+--		damage or loss was reasonably foreseeable or Xilinx had been advised of the
+--		possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+--		Xilinx products are not designed or intended to be fail-safe, or for use in any
+--		application requiring fail-safe performance, such as life-support or safety devices
+--		or systems, Class III medical devices, nuclear facilities, applications related to
+--		the deployment of airbags, or any other applications that could lead to death,
+--		personal injury, or severe property or environmental damage (individually and
+--		collectively, "Critical Applications"). Customer assumes the sole risk and
+--		liability of any use of Xilinx products in Critical Applications, subject only to
+--		applicable laws and regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 
+--
+--		Contact:    e-mail  hotline@xilinx.com        phone   + 1 800 255 7778
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /   Vendor:                Xilinx
+-- \   \   \/    Version:               V0,03
+--  \   \        Filename:              AdcClock.vhd
+--  /   /        Date Last Modified:  	24 Jul 12
+-- /___/   /\    Date Created: 			08 Jun 09
+-- \   \  /  \
+--  \___\/\___\
+-- 
+-- Device: 		7-series
+-- Author:		Marc Defossez
+-- Entity Name:	AdcClock
+-- Purpose: 	Clock control for an ADC interface.
+-- Tools:		ISE_14.1
+-- Limitations: none
+--
+-- Revision History:
+--    Rev. 
+--
+-----------------------------------------------------------------------------------------------
+-- Naming Conventions:
+--   active low signals:                    "*_n"
+--   clock signals:                         "clk", "clk_div#", "clk_#x"
+--   reset signals:                         "rst", "rst_n"
+--   generics:                              "C_*"
+--   user defined types:                    "*_TYPE"
+--   state machine next state:              "*_ns"
+--   state machine current state:           "*_cs"
+--   combinatorial signals:                 "*_com"
+--   pipelined or register delay signals:   "*_d#"
+--   counter signals:                       "*cnt*"
+--   clock enable signals:                  "*_ce"
+--   internal version of output port:       "*_i"
+--   device pins:                           "*_pin"
+--   ports:                                 "- Names begin with Uppercase"
+--   processes:                             "*_PROCESS"
+--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
+-----------------------------------------------------------------------------------------------
+--
+library IEEE;
+	use IEEE.std_logic_1164.all;
+	use IEEE.std_logic_UNSIGNED.all;
+	use IEEE.std_logic_arith.all;
+library UNISIM;
+	use UNISIM.VCOMPONENTS.all;
+-----------------------------------------------------------------------------------------------
+-- Entity pin description
+-----------------------------------------------------------------------------------------------
+entity AdcClock is
+	generic (
+	   C_BufioLoc  : string := "BUFIO_X0Y17"; -- IO-bank 16
+	   C_BufrLoc   : string := "BUFR_X0Y17";
+	   C_IserdesLoc: string := "BUFR_X0Y17";
+	   C_StatTaps  : integer := 16
+	);
+    port (
+        BitClk				: in std_logic;
+        BitClkRst			: in std_logic;
+        BitClkEna			: in std_logic;
+        BitClkReSync		: in std_logic;
+        BitClk_MonClkOut	: out std_logic;   -- CLK output
+        BitClk_MonClkIn		: in std_logic;    -- ISERDES.CLK input
+        BitClk_RefClkOut	: out std_logic;   -- CLKDIV & logic output
+        BitClk_RefClkIn		: in std_logic;    -- CLKDIV & logic input
+        BitClkAlignWarn 	: out std_logic;
+        BitClkInvrtd		: out std_logic;
+        BitClkDone 			: out std_logic
+    );
+end AdcClock;
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcClock_struct of AdcClock is
+-----------------------------------------------------------------------------------------------
+-- Component Instantiation
+-----------------------------------------------------------------------------------------------
+-- Components are instantiated by means / through the use of library references.
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+-- Constants
+constant Low	: std_logic := '0';
+constant LowNibble : std_logic_vector(4 downto 0) := "00000";
+constant High : std_logic := '1';
+-- Signals
+signal IntBitClkRst				: std_logic;
+---------- ISRDS signals ------------------
+signal IntClkCtrlDlyCe			: std_logic;
+signal IntClkCtrlDlyInc			: std_logic;
+signal IntClkCtrlDlyRst			: std_logic;
+
+signal IntBitClk_Ddly			: std_logic;
+signal IntBitClk				: std_logic;
+signal BitClk_inv				: std_logic;
+
+signal IntClkCtrlIsrdsMtoS1		: std_logic;
+signal IntClkCtrlIsrdsMtoS2		: std_logic;
+signal IntClkCtrlOut			: std_logic_vector(7 downto 0);
+---------- Controller signals -------------
+signal IntCal					: std_logic;
+signal IntVal					: std_logic;
+signal IntCalVal				: std_logic_vector (1 downto 0);
+signal IntProceedCnt			: std_logic_vector (2 downto 0);
+signal IntproceedCntTc			: std_logic;
+signal IntproceedCntTc_d		: std_logic;
+signal IntProceed				: std_logic;
+signal IntProceedDone			: std_logic;
+
+type StateType is (Idle, A, B, C, D, E, F, G, G1, H, K, K1, K2, IdlyIncDec, Done);
+signal State : StateType;
+signal ReturnState : StateType;
+
+signal PassedSubState		: std_logic;
+signal IntNumIncDecIdly		: std_logic_vector (3 downto 0);
+signal IntAction			: std_logic_vector (1 downto 0);
+signal IntClkCtrlDone 		: std_logic;
+signal IntClkCtrlAlgnWrn	: std_logic;
+signal IntClkCtrlInvrtd		: std_logic;
+signal IntTurnAroundBit		: std_logic;
+signal IntCalValReg			: std_logic_vector (1 downto 0);
+signal IntTimeOutCnt		: std_logic_vector (3 downto 0);
+signal IntStepCnt	 		: std_logic_vector (4 downto 0); --//
+-- Attributes
+attribute KEEP_HIERARCHY : string;
+	attribute KEEP_HIERARCHY of AdcClock_struct : architecture is "YES";
+attribute LOC : string;
+	attribute LOC of AdcClock_I_Bufio : label is C_BufioLoc;
+	attribute LOC of AdcClock_I_Bufr : label is C_BufrLoc;
+	attribute LOC of AdcClock_I_Isrds_Master : label is C_IserdesLoc;
+--attribute keep                : string;
+--attribute keep of BitClk_inv   : signal is "TRUE";
+
+-----------------------------------------------------------------------------------------------
+begin
+-----------------------------------------------------------------------------------------------
+-- Bit clock capture ISERDES Master-Slave combination
+-----------------------------------------------------------------------------------------------
+--
+BitClk_inv <= not BitClk; -- peterS: invert clock for better optimal delay point
+AdcClock_I_Iodly : IDELAYE2 --_FINEDELAY
+    generic map (
+        SIGNAL_PATTERN          => "CLOCK",
+        REFCLK_FREQUENCY        => 200.0,
+        HIGH_PERFORMANCE_MODE   => "TRUE",
+        --FINEDELAY             => "BYPASS",
+        DELAY_SRC               => "IDATAIN",
+        CINVCTRL_SEL            => "FALSE",
+        IDELAY_TYPE             => "VARIABLE",
+        IDELAY_VALUE            => C_StatTaps,
+        PIPE_SEL                => "FALSE"
+    )
+    port map (
+        DATAIN          => Low, -- in
+        IDATAIN         => BitClk_inv, -- in
+        CE              => IntClkCtrlDlyCe, -- in
+        INC             => IntClkCtrlDlyInc, -- in
+        C               => BitClk_RefClkIn, -- in
+        LD              => IntClkCtrlDlyRst, -- in
+        LDPIPEEN        => Low, -- in
+        REGRST          => '0', --//IntClkCtrlDlyRst, -- in
+        DATAOUT         => IntBitClk_Ddly, -- out        
+        CINVCTRL        => Low, -- in
+        CNTVALUEOUT     => open, -- out [4:0]
+        CNTVALUEIN      => LowNibble -- in [4:0]
+    );
+IntClkCtrlDlyRst <= BitClkRst;
+
+AdcClock_I_Isrds_Master : ISERDESE2
+    generic map (
+        SERDES_MODE         => "MASTER",
+        INTERFACE_TYPE      => "NETWORKING",        
+        IOBDELAY            => "IBUF",
+        DATA_RATE           => "SDR",
+        DATA_WIDTH          => 8,
+        DYN_CLKDIV_INV_EN   => "FALSE",
+        DYN_CLK_INV_EN      => "FALSE",
+        NUM_CE              => 1,
+        OFB_USED            => "FALSE",
+        INIT_Q1             => '0',
+        INIT_Q2             => '0',
+        INIT_Q3             => '0',
+        INIT_Q4             => '0',
+        SRVAL_Q1            => '0',
+        SRVAL_Q2            => '0',
+        SRVAL_Q3            => '0',
+        SRVAL_Q4            => '0'
+    )
+    port map (
+        D               => BitClk_inv,			-- in	Clock from clock input IBUFDS
+        DDLY            => IntBitClk_Ddly, -- in
+        DYNCLKDIVSEL    => Low, -- in
+        DYNCLKSEL       => Low, -- in
+        OFB             => Low, -- in
+        BITSLIP         => Low, -- in
+        CE1             => BitClkEna, -- in
+        CE2             => Low, -- in
+        RST             => IntBitClkRst, -- in
+        CLK             => BitClk_MonClkIn, -- in
+        CLKB            => Low, -- in
+        CLKDIV          => BitClk_RefClkIn, -- in
+        CLKDIVP         => Low, -- in
+        OCLK            => Low, -- in
+        OCLKB           => Low, -- in
+        SHIFTIN1        => Low, -- in
+        SHIFTIN2        => Low, -- in        
+        O               => IntBitClk, -- out
+        Q1              => IntClkCtrlOut(0), -- out
+        Q2              => IntClkCtrlOut(1), -- out
+        Q3              => IntClkCtrlOut(2), -- out
+        Q4              => IntClkCtrlOut(3), -- out
+        Q5              => IntClkCtrlOut(4), -- out
+        Q6              => IntClkCtrlOut(5), -- out
+        Q7              => IntClkCtrlOut(6), -- out
+        Q8              => IntClkCtrlOut(7), -- out
+        SHIFTOUT1       => open, -- out
+        SHIFTOUT2       => open -- out
+    );
+-- Input from ISERDES.O	  -- Output and CLK for all ISERDES
+AdcClock_I_Bufio : BUFIO
+	port map (I => IntBitClk, O => BitClk_MonClkOut);
+
+AdcClock_I_Bufr : BUFR
+		generic map (BUFR_DIVIDE => "4", SIM_DEVICE => "7SERIES") -- 14- and 16-bit = DIV by 4
+--      ISERDES.CLK, from BUFIO.O -- ISERDES.CLKDIV, word clock for all ISERDES.
+		port map  (I => IntBitClk, O => BitClk_RefClkOut,
+					CE	=> High, CLR => BitClkReSync); --// ); --//peter low
+
+
+-----------------------------------------------------------------------------------------------
+-- Bit clock re-synchronizer
+-----------------------------------------------------------------------------------------------
+IntBitClkRst <= BitClkRst; --// or BitClkReSync;
+-----------------------------------------------------------------------------------------------
+-- Bit clock controller for clock alignment input.
+-----------------------------------------------------------------------------------------------
+-- This input section makes sure 64 bits are captured before action is taken to pass to
+-- the statemachine for evaluation.
+-- 8 samples of the Bit Clock are taken by the ISERDES and then transferred to the parallel
+-- FPGA world. The Proceed counter needs 8 reference clock rising edges before terminal count.
+-- The Proceed counter terminal count then loads the 2 control bits (made from sampled clock)
+-- into an intermediate register (IntCalVal).
+--
+-- IntCal = '1' when all outputs of the ISERDES are '1 else it's '0'.
+-- IntVal = '1' when all outputs are '0' or '1'.
+--
+IntCal <= IntClkCtrlOut(7) and IntClkCtrlOut(6) and IntClkCtrlOut(5) and
+			IntClkCtrlOut(4) and IntClkCtrlOut(3) and IntClkCtrlOut(2) and
+			IntClkCtrlOut(1) and IntClkCtrlOut(0);
+IntVal <= '1' when (IntClkCtrlOut = "11111111" or IntClkCtrlOut = "00000000") else '0';
+--
+AdcClock_Proceed_PROCESS : process (BitClkEna, IntBitClkRst, BitClk_RefClkIn, IntProceedDone, IntClkCtrlDone)
+begin
+	if (IntBitClkRst = '1') then
+		IntProceedCnt <= (others => '0');
+		IntProceedCntTc_d <= '0';
+		IntCalVal <= (others => '0');
+		IntProceed <= '0';
+	elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then
+		if (BitClkEna = '1' and IntClkCtrlDone = '0') then
+			IntProceedCnt <= IntProceedCnt + 1;
+			IntProceedCntTc_d <= IntProceedCntTc;
+			if (IntProceedCntTc_d = '1') then
+				IntCalVal <= IntCal & IntVal;
+			end if;
+			if (IntProceedCntTc_d = '1') then
+				IntProceed <= '1';
+			elsif (IntProceedDone = '1') then
+				IntProceed <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+IntProceedCntTc <= '1' when (IntProceedCnt = "110") else '0';
+-----------------------------------------------------------------------------------------------
+-- Bit clock controller for clock alignment state machine.
+-----------------------------------------------------------------------------------------------
+BitClkAlignWarn <= IntClkCtrlAlgnWrn;
+BitClkInvrtd <= IntClkCtrlInvrtd;
+BitClkDone <= IntClkCtrlDone;
+
+AdcClock_State_PROCESS : process (BitClk_RefClkIn, IntBitClkRst, BitClkEna, IntProceed, IntCalVal)
+subtype ActCalVal is std_logic_vector (4 downto 0);
+begin
+	if (IntBitClkRst = '1') then
+		State				<= Idle;
+		ReturnState			<= Idle;
+		PassedSubState		<= '0';
+		--
+		IntNumIncDecIdly	<= "0000";	-- Max. 16
+		IntAction			<= "00";			
+		IntClkCtrlDlyInc	<= '1';
+		IntClkCtrlDlyCe		<= '0';
+		IntClkCtrlDone 		<= '0';
+		IntClkCtrlAlgnWrn	<= '0';
+		IntClkCtrlInvrtd	<= '0';
+		IntTurnAroundBit	<= '0';
+		IntProceedDone		<= '0';
+		IntClkCtrlDone		<= '0';
+		IntCalValReg		<= (others => '0');		-- 2-bit
+		IntTimeOutCnt		<= (others => '0');		-- 4-bit
+		IntStepCnt	 		<= (others => '0');		-- 4-bit (16)
+	elsif (BitClk_RefClkIn'event and BitClk_RefClkIn = '1') then
+		if (BitClkEna = '1' and IntClkCtrlDone = '0') then
+		case State is 
+			when Idle =>
+				IntProceedDone <= '0';
+				PassedSubState <= '0';
+				case ActCalVal'(IntAction(1 downto 0) & IntCalVal (1 downto 0) & IntProceed) is
+					when "00001" => State <= A;
+					when "01001" => State <= B;
+					when "10001" => State <= B;
+					when "11001" => State <= B;
+					when "01111" => State <= C;
+					when "01101" => State <= D;
+					when "01011" => State <= D;
+					when "00011" => State <= E;
+					when "00101" => State <= E;
+					when "00111" => State <= E;
+					when "10011" => State <= F;
+					when "11011" => State <= F;
+					when "10101" => State <= F;
+					when "11101" => State <= F;
+					when "10111" => State <= F;
+					when "11111" => State <= F;
+					when others => State <= Idle;
+				end case;
+			when A => 						-- First time and sampling in jitter or cross area.
+				IntAction <= "01";					-- Set the action bits and go to next step.
+				State <= B;
+			when B =>						-- Input is samples in jitter or clock cross area.
+				if (PassedSubState = '1') then
+					PassedSubState <= '0';			-- Clear the pass through the substate bit.
+					IntProceedDone <= '1';			-- Reset the proceed bit.
+					State <= Idle;					-- Return for a new sample of the input.
+				elsif (IntTimeOutCnt = "1111") then	-- When arriving here something is wrong.
+					IntTimeOutCnt <= "0000";		-- Reset the counter.
+					IntAction <= "00";				-- reset the action bits.
+					IntClkCtrlAlgnWrn <= '1';		-- Raise a FLAG.
+					IntProceedDone <= '1';			-- Reset the proceed bit.
+					State <= Idle;					-- Retry, return for new sample of input.
+				else
+					IntTimeOutCnt <= IntTimeOutCnt + 1;
+					IntNumIncDecIdly <= "0010";		-- Number increments or decrements to do.
+					ReturnState <= State;			-- This state is the state to return too.
+					IntProceedDone <= '1';			-- Reset the proceed bit.
+					IntClkCtrlDlyInc <= '1';		-- Set for increment.
+					State <= IdlyIncDec;			-- Jump to Increment/decrement sub-state.
+				end if;
+			when C =>						-- After first sample, jitter or cross, is now high.
+				IntNumIncDecIdly <= "0010";			-- Number increments or decrements to do.
+				ReturnState <= Done;				-- This state is the state to return too.
+				IntClkCtrlDlyInc	<= '0';			-- Set for decrement.
+				State <= IdlyIncDec;
+			when D =>						-- Same as C but with indication of 180-deg shift.
+				IntClkCtrlInvrtd <= '1';
+				State <= C;
+			when E =>						-- First sample with valid data.
+				IntCalValReg <= IntCalVal;			-- Register the sampled value
+				IntAction <= "10";
+				IntProceedDone <= '1';				-- Reset the proceed bit.
+				IntNumIncDecIdly <= "0001";			-- Number increments or decrements to do.
+				ReturnState <= Idle;				-- When increment is done return sampling.
+				IntClkCtrlDlyInc <= '1';			-- Set for increment
+				State <= IdlyIncDec;				-- Jump to Increment/decrement sub-state.
+			when F =>						-- Next samples with valid data.
+				if (IntCalVal /= IntCalValReg) then
+					State <= G;				-- The new CalVal value is different from the first.
+				else
+					if (IntStepCnt = "11111") then 	-- Step counter at the end, 15 --//
+						if (IntTurnAroundBit = '0') then 
+							State <= H;				-- No edge found and first time here.
+						elsif (IntCalValReg = "11") then
+							State <= K;			-- A turnaround already happend.
+						else					-- No edge is found (large 1/2 period).
+							State <= K1;		-- Move the clock edge to near the correct
+						end if;					-- edge.
+					else
+						IntStepCnt <= IntStepCnt + 1;
+						IntNumIncDecIdly <= "0001";	-- Number increments or decrements to do.
+						IntProceedDone <= '1';		-- Reset the proceed bit.
+						ReturnState <= Idle;		-- When increment is done return sampling.
+						IntClkCtrlDlyInc <= '1';	-- Set for increment
+						State <= IdlyIncDec;		-- Jump to Increment/decrement sub-state.
+					end if;
+				end if;
+			when G =>
+				if (IntCalValReg /= "01") then
+					IntClkCtrlInvrtd <= '1';
+					State <= G1;
+				else
+					State <= G1;
+				end if;
+			when G1 =>
+				if (IntTimeOutCnt = "00") then
+					State <= Done;
+				else
+					IntNumIncDecIdly <= "0010";	-- Number increments or decrements to do.
+					ReturnState <= Done;		-- After decrement it's finished.
+					IntClkCtrlDlyInc <= '0';	-- Set for decrement
+					State <= IdlyIncDec;		-- Jump to the Increment/decrement sub-state.
+				end if;
+			when H =>
+				IntTurnAroundBit <= '1';		-- Indicate that the Idelay jumps to 0.
+				IntStepCnt <= IntStepCnt + 1;	-- Set all registers to zero.
+				IntAction <= "00";				-- Take one step, let the counter flow over 
+				IntCalValReg <= "00";			-- The idelay turn over to 0.
+				IntTimeOutCnt <= "0000";		-- Start sampling from scratch.
+				IntNumIncDecIdly <= "0001";		-- Number increments or decrements to do.
+				IntProceedDone <= '1';			-- Reset the proceed bit.
+				ReturnState <= Idle;			-- After increment go sampling for new.
+				IntClkCtrlDlyInc <= '1';		-- Set for increment.
+				State <= IdlyIncDec;			-- Jump to the Increment/decrement sub-state.
+			when K =>
+				IntNumIncDecIdly <= "1111";		-- Number increments or decrements to do.
+				ReturnState <= K2;				-- After increment it is done.
+				IntClkCtrlDlyInc <= '1';		-- Set for increment.
+				State <= IdlyIncDec;			-- Jump to the Increment/decrement sub-state.
+			when K1 =>
+				IntNumIncDecIdly <= "1110";		-- Number increments or decrements to do.
+				ReturnState <= K2;				-- After increment it is done.
+				IntClkCtrlDlyInc <= '1';		-- Set for increment.
+				State <= IdlyIncDec;			-- Jump to the Increment/decrement sub-state.
+			when K2 =>
+				IntNumIncDecIdly <= "0001";		-- Number increments or decrements to do.
+				ReturnState <= Done;			-- After increment it is done.
+				IntClkCtrlDlyInc <= '1';		-- Set for increment.
+				State <= IdlyIncDec;			-- Jump to the Increment/decrement sub-state.
+			--
+			when IdlyIncDec =>				-- Increment or decrement by enable.
+				if (IntNumIncDecIdly /= "0000") then			-- Check number of tap jumps
+					IntNumIncDecIdly <= IntNumIncDecIdly - 1;	-- If not 0 jump and decrement.
+					IntClkCtrlDlyCe <= '1';						-- Do the jump. enable it.
+				else
+					IntClkCtrlDlyCe <= '0';		-- when it is enabled, disbale it
+					PassedSubState <= '1';		-- Set a check bit "I've been here and passed".
+					State <= ReturnState;		-- Return to origin.
+				end if;
+			when Done =>					-- Alignment done.
+				IntClkCtrlDone <= '1';				-- Alignment is done.
+		end case;
+		end if;
+	end if;
+end process;
+--
+------------------------------------------------------------------------------------------------
+
+
+
 end  AdcClock_struct;
\ No newline at end of file
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcData.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcData.vhd
new file mode 100644
index 0000000..3dde4c1
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcData.vhd
@@ -0,0 +1,350 @@
+library IEEE;
+	use IEEE.std_logic_1164.all;
+	use IEEE.std_logic_UNSIGNED.all;
+library UNISIM;
+	use UNISIM.VCOMPONENTS.all;
+
+entity AdcData is
+	port (
+		DatD0_n              : in std_logic;
+		DatD0_p		      	: in std_logic;
+		DatD1_n		      	: in std_logic;
+		DatD1_p	      		: in std_logic;
+		DatClk		      	: in std_logic;
+		DatClkDiv	      	: in std_logic;
+		DatRst		      	: in std_logic;
+		DatEna		      	: in std_logic;
+		DatDone		      	: in std_logic;
+		DatOut	      		: out std_logic_vector(31 downto 0)
+	);
+end AdcData;
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcData_struct of AdcData  is
+signal IntDatClk           : std_logic;
+signal IntDatClk_n         : std_logic;
+--
+signal IntDatSrds0Out      : std_logic_vector(7 downto 0);
+signal IntDatSrds1Out      : std_logic_vector(7 downto 0);
+signal IntDatSrds0         : std_logic_vector(7 downto 0);
+signal IntDatSrds1         : std_logic_vector(7 downto 0);
+signal IntDat0             : std_logic_vector(7 downto 0);
+signal IntDat1             : std_logic_vector(7 downto 0);
+signal IntDat0Mux          : std_logic_vector(7 downto 0);
+signal IntDat1Mux          : std_logic_vector(7 downto 0);
+signal IntDat0Swp          : std_logic_vector(7 downto 0);
+signal IntDat1Swp          : std_logic_vector(7 downto 0);
+signal IntDatSwpBus        : std_logic_vector(31 downto 0);
+signal IntDatDone          : std_logic;
+signal IntDatEna           : std_logic;
+-- Attributes
+attribute KEEP_HIERARCHY   : string;
+attribute KEEP_HIERARCHY of AdcData_struct : architecture is "YES";
+-----------------------------------------------------------------------------------------------
+
+begin
+--
+-- DatRst and DatEna are synchronised to DatClkDiv on the level were this component "AdcData"
+-- is used. This higher level is "AdcToplevel".
+AdcData_Done_PROCESS : process (DatClkDiv, DatRst)
+begin
+	if (DatRst = '1') then
+		IntDatDone <= '0';
+	elsif (DatClkDiv'event and DatClkDiv = '1') then
+        IntDatDone <= DatDone;
+	end if;
+end process;
+--
+IntDatEna <= '1' when (IntDatDone = '1' and DatEna = '1') else '0';
+-----------------------------------------------------------------------------------------------
+IntDatClk <= DatClk;			-- CLOCK FOR P-side ISERDES
+IntDatClk_n <= not DatClk;		-- CLOCK FOR N_side ISERDES
+-----------------------------------------------------------------------------------------------
+-- ISERDES for channel ZERO
+-----------------------------------------------------------------------------------------------
+AdcData_I_Isrds_D0_p : ISERDESE2
+    generic map (
+		SERDES_MODE			=> "MASTER",			-- string 
+		INTERFACE_TYPE		=> "NETWORKING",		-- string 
+		IOBDELAY			=> "NONE",				-- string 
+		DATA_RATE 			=> "SDR", 				-- string 
+		DATA_WIDTH 			=> 4,	-- integer <-- Number of bits
+		DYN_CLKDIV_INV_EN	=> "FALSE", 			-- string 
+		DYN_CLK_INV_EN		=> "FALSE", 			-- string 
+		NUM_CE				=> 1, 					-- integer 
+		OFB_USED			=> "FALSE", 			-- string 
+        INIT_Q1             => '0',         -- bit;
+        INIT_Q2             => '0',         -- bit;
+        INIT_Q3             => '0',         -- bit;
+        INIT_Q4             => '0',         -- bit;
+        SRVAL_Q1            => '0',         -- bit;
+        SRVAL_Q2            => '0',         -- bit;
+        SRVAL_Q3            => '0',         -- bit;
+        SRVAL_Q4            => '0'          -- bit
+    )
+    port map (
+		D				=> DatD0_p,		-- in
+		DDLY			=> '0', 		-- in    
+		OFB				=> '0', 		-- in
+		BITSLIP			=> '0',-- in
+		CE1				=> IntDatDone,	-- in
+		CE2				=> '0',			-- in
+		RST				=> DatRst,	    -- in
+		CLK				=> IntDatClk, 	-- in
+		CLKB			=> '0', 		-- in
+		CLKDIV			=> DatClkDiv, 	-- in
+        CLKDIVP         => '0',         -- in
+		OCLK			=> '0', 		-- in
+        OCLKB           => '0',         -- in
+		DYNCLKDIVSEL	=> '0', 		-- in
+		DYNCLKSEL		=> '0', 		-- in
+		SHIFTOUT1		=> open, 		-- out
+		SHIFTOUT2		=> open, 		-- out
+		O				=> open, 		-- out
+		Q1				=> IntDatSrds0Out(6), -- out	(0)
+		Q2				=> IntDatSrds0Out(4), -- out	(2)
+		Q3				=> IntDatSrds0Out(2), -- out	(4)
+		Q4				=> IntDatSrds0Out(0), -- out	(6)
+		Q5				=> open, 		-- out
+		Q6				=> open, 		-- out
+        Q7              => open,        -- out
+        Q8              => open,        -- out
+		SHIFTIN1		=> '0', 		-- in
+		SHIFTIN2		=> '0' 			-- in
+	);
+AdcData_I_Isrds_D0_n : ISERDESE2
+	generic map (
+		SERDES_MODE			=> "MASTER",			-- 
+		INTERFACE_TYPE		=> "NETWORKING",		-- 
+		IOBDELAY			=> "NONE",				-- 
+		DATA_RATE 			=> "SDR", 				-- 
+		DATA_WIDTH 			=> 4,	-- <-- Number of bits
+		DYN_CLKDIV_INV_EN	=> "FALSE",      		-- 
+		DYN_CLK_INV_EN		=> "FALSE", 			-- 
+		NUM_CE				=> 1, 					-- 
+		OFB_USED			=> "FALSE", 			-- 
+        INIT_Q1             => '0',         -- bit;
+        INIT_Q2             => '0',         -- bit;
+        INIT_Q3             => '0',         -- bit;
+        INIT_Q4             => '0',         -- bit;
+        SRVAL_Q1            => '0',         -- bit;
+        SRVAL_Q2            => '0',         -- bit;
+        SRVAL_Q3            => '0',         -- bit;
+        SRVAL_Q4            => '0'          -- bit
+    )
+    port map (
+		D				=> DatD0_n,		-- in
+		DDLY			=> '0', 		-- in   
+		OFB				=> '0', 		-- in
+		BITSLIP			=> '0',-- in
+		CE1				=> IntDatDone,	-- in
+		CE2				=> '0',			-- in
+		RST				=> DatRst,	    -- in
+		CLK				=> IntDatClk_n,	-- in
+		CLKB			=> '0', 		-- in
+		CLKDIV			=> DatClkDiv, 	-- in
+        CLKDIVP         => '0',         -- in
+		OCLK			=> '0', 		-- in
+        OCLKB           => '0',         -- in
+		DYNCLKDIVSEL	=> '0', 		-- in
+		DYNCLKSEL		=> '0', 		-- in
+		SHIFTOUT1		=> open, 		-- out
+		SHIFTOUT2		=> open, 		-- out
+		O				=> open, 		-- out
+		Q1				=> IntDatSrds0Out(7), -- out	(1)
+		Q2				=> IntDatSrds0Out(5), -- out	(3)
+		Q3				=> IntDatSrds0Out(3), -- out	(5)
+		Q4				=> IntDatSrds0Out(1), -- out	(7)
+		Q5				=> open, 		-- out
+		Q6				=> open, 		-- out
+        Q7              => open,        -- out
+        Q8              => open,        -- out
+		SHIFTIN1		=> '0', 		-- in
+		SHIFTIN2		=> '0' 			-- in
+	);
+-----------------------------------------------------------------------------------------------
+-- ISERDES for channel ONE
+-----------------------------------------------------------------------------------------------
+AdcData_I_Isrds_D1_p : ISERDESE2
+    generic map (
+		SERDES_MODE			=> "MASTER",			-- string 
+		INTERFACE_TYPE		=> "NETWORKING",		-- string 
+		IOBDELAY			=> "NONE",				-- string 
+		DATA_RATE 			=> "SDR", 				-- string 
+		DATA_WIDTH 			=> 4,	-- integer <-- Number of bits
+		DYN_CLKDIV_INV_EN	=> "FALSE",				-- string 
+		DYN_CLK_INV_EN		=> "FALSE",				-- string 
+		NUM_CE				=> 1, 					-- integer 
+		OFB_USED			=> "FALSE",				-- string 
+        INIT_Q1             => '0',         -- bit;
+        INIT_Q2             => '0',         -- bit;
+        INIT_Q3             => '0',         -- bit;
+        INIT_Q4             => '0',         -- bit;
+        SRVAL_Q1            => '0',         -- bit;
+        SRVAL_Q2            => '0',         -- bit;
+        SRVAL_Q3            => '0',         -- bit;
+        SRVAL_Q4            => '0'          -- bit
+    )
+    port map (
+		D				=> DatD1_p,		-- in
+		DDLY			=> '0', 		-- in    
+		OFB				=> '0', 		-- in
+		BITSLIP			=> '0',-- in
+		CE1				=> IntDatDone,	-- in
+		CE2				=> '0',			-- in
+		RST				=> DatRst,	    -- in
+		CLK				=> IntDatClk, 	-- in
+		CLKB			=> '0', 		-- in
+		CLKDIV			=> DatClkDiv, 	-- in
+        CLKDIVP         => '0',         -- in
+		OCLK			=> '0', 		-- in
+        OCLKB           => '0',         -- in
+		DYNCLKDIVSEL	=> '0', 		-- in
+		DYNCLKSEL		=> '0', 		-- in
+		SHIFTOUT1		=> open, 		-- out
+		SHIFTOUT2		=> open, 		-- out
+		O				=> open, 		-- out
+		Q1				=> IntDatSrds1Out(6), -- out	(0)
+		Q2				=> IntDatSrds1Out(4), -- out	(2)
+		Q3				=> IntDatSrds1Out(2), -- out	(4)
+		Q4				=> IntDatSrds1Out(0), -- out	(6)
+		Q5				=> open, 		-- out
+		Q6				=> open, 		-- out
+        Q7              => open,        -- out
+        Q8              => open,        -- out
+		SHIFTIN1		=> '0', 		-- in
+		SHIFTIN2		=> '0' 			-- in
+    );
+AdcData_I_Isrds_D1_n : ISERDESE2
+	generic map (
+		SERDES_MODE			=> "MASTER",			-- 
+		INTERFACE_TYPE		=> "NETWORKING",		-- 
+		IOBDELAY			=> "NONE",				-- 
+		DATA_RATE 			=> "SDR", 				-- 
+		DATA_WIDTH 			=> 4,	-- <-- Number of bits
+		DYN_CLKDIV_INV_EN	=> "FALSE", 			-- 
+		DYN_CLK_INV_EN		=> "FALSE", 			-- 
+		NUM_CE				=> 1, 					-- 
+		OFB_USED			=> "FALSE", 			-- 
+        INIT_Q1             => '0',         -- bit;
+        INIT_Q2             => '0',         -- bit;
+        INIT_Q3             => '0',         -- bit;
+        INIT_Q4             => '0',         -- bit;
+        SRVAL_Q1            => '0',         -- bit;
+        SRVAL_Q2            => '0',         -- bit;
+        SRVAL_Q3            => '0',         -- bit;
+        SRVAL_Q4            => '0'          -- bit
+    )
+    port map (
+		D				=> DatD1_n,		-- in
+		DDLY			=> '0', 		-- in   
+		OFB				=> '0', 		-- in
+		BITSLIP			=> '0',-- in
+		CE1				=> IntDatDone,	-- in
+		CE2				=> '0',			-- in
+		RST				=> DatRst,	    -- in
+		CLK				=> IntDatClk_n,	-- in
+		CLKB			=> '0', 		-- in
+		CLKDIV			=> DatClkDiv, 	-- in
+        CLKDIVP         => '0',         -- in
+		OCLK			=> '0', 		-- in
+        OCLKB           => '0',         -- in
+		DYNCLKDIVSEL	=> '0', 		-- in
+		DYNCLKSEL		=> '0', 		-- in
+		SHIFTOUT1		=> open, 		-- out
+		SHIFTOUT2		=> open, 		-- out
+		O				=> open, 		-- out
+		Q1				=> IntDatSrds1Out(7), -- out	(1)
+		Q2				=> IntDatSrds1Out(5), -- out	(3)
+		Q3				=> IntDatSrds1Out(3), -- out	(5)
+		Q4				=> IntDatSrds1Out(1), -- out	(7)
+		Q5				=> open, 		-- out
+		Q6				=> open, 		-- out
+        Q7              => open,        -- out
+        Q8              => open,        -- out
+		SHIFTIN1		=> '0', 		-- in
+		SHIFTIN2		=> '0' 			-- in
+	);
+-----------------------------------------------------------------------------------------------
+
+
+	IntDatSrds0 <= not IntDatSrds0Out(7) & IntDatSrds0Out(6) &
+					not IntDatSrds0Out(5) & IntDatSrds0Out(4) &
+					not IntDatSrds0Out(3) & IntDatSrds0Out(2) &
+					not IntDatSrds0Out(1) & IntDatSrds0Out(0);
+	IntDatSrds1 <= not IntDatSrds1Out(7) & IntDatSrds1Out(6) &
+					not IntDatSrds1Out(5) & IntDatSrds1Out(4) &
+					not IntDatSrds1Out(3) & IntDatSrds1Out(2) &
+					not IntDatSrds1Out(1) & IntDatSrds1Out(0);
+
+-----------------------------------------------------------------------------------------------
+-- DATA REGISTER
+-----------------------------------------------------------------------------------------------
+Gen_1_DatReg : for n in 7 downto 0 generate 
+    AdcData_I_Fdce_Reg0 : FDCE
+        generic map (INIT => '0')  -- bit
+--//        port map (D => IntDatSrds0(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst,
+        port map (D => IntDatSrds0(n), C => DatClkDiv, CE => '1', CLR => '0',
+                  Q => IntDat0(n));
+    AdcData_I_Fdce_Reg1 : FDCE
+        generic map (INIT => '0')  -- bit
+--//        port map (D => IntDatSrds1(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst,
+        port map (D => IntDatSrds1(n), C => DatClkDiv, CE => '1', CLR => '0',
+                  Q => IntDat1(n));
+end generate Gen_1_DatReg;  
+
+
+IntDat0Mux <= IntDat0;
+IntDat1Mux <= IntDat1;
+
+Gen_3_DatReg : for n in 7 downto 0 generate
+    AdcData_I_Fdce_Reg2 : FDCE
+        generic map (INIT => '0')  -- bit
+--//        port map (D => IntDat0Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst,
+        port map (D => IntDat0Mux(n), C => DatClkDiv, CE => '1', CLR => '0',
+                  Q => IntDat0Swp(n));
+    AdcData_I_Fdce_Reg3 : FDCE
+        generic map (INIT => '0')  -- bit
+--//        port map (D => IntDat1Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatRst,
+        port map (D => IntDat1Mux(n), C => DatClkDiv, CE => '1', CLR => '0',
+                  Q => IntDat1Swp(n));
+end generate Gen_3_DatReg;
+
+
+
+-----------------------------------------------------------------------------------------------
+-- 2-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs
+-- Only one of these options can be chosen at a time.
+--	2-wire, Msb-Bit or Msb-Byte
+--	2-wire, Lsb-Bit or Lsb-Byte
+-----------------------------------------------------------------------------------------------
+
+-- Bit mode, MSB First, 14-bits (16-bits)
+-- Bit			: 7,       6,   5,   4,  3,  2,  1,  0
+-- Channel 0	: 0/(D14), D12, D10, D8, D6, D4, D2, D0
+-- Channel 1	: 0/(D15), D13, D11, D9, D7, D5, D3, D1
+IntDatSwpBus <= IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+					 & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
+					 & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
+					 & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
+					 & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
+					 & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
+					 & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
+					 & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2);
+Gen_1_H : for n in 0 to 15 generate
+	 I_Fdce_H : FDCE
+		  generic map (INIT => '0')
+		  port map (D => IntDatSwpBus(n+16), CE => '1', C => DatClkDiv,
+--//						CLR => DatRst, Q => DatOut(n+16));
+						CLR => '0', Q => DatOut(n+16));
+	 I_Fdce_L : FDCE
+		  generic map (INIT => '0')
+		  port map (D => IntDatSwpBus(n), CE => '1', C => DatClkDiv,
+--//						CLR => DatRst, Q => DatOut(n));
+						CLR => '0', Q => DatOut(n));
+end generate Gen_1_H;
+-----------------------------------------------------------------------------------------------
+
+
+end  AdcData_struct;
\ No newline at end of file
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcFrame.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcFrame.vhd
new file mode 100644
index 0000000..ad33620
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcFrame.vhd
@@ -0,0 +1,182 @@
+library IEEE;
+	use IEEE.std_logic_1164.all;
+	use IEEE.std_logic_UNSIGNED.all;
+	use IEEE.std_logic_textio.all;
+library UNISIM;
+	use UNISIM.VCOMPONENTS.all;
+
+entity AdcFrame is
+	port (
+		FrmClk_n             : in std_logic;		-- input n from IBUFDS_DIFF_OUT
+		FrmClk_p             : in std_logic;		-- input p from IBUFDS_DIFF_OUT
+		FrmClkRst            : in std_logic;
+		FrmClkEna            : in std_logic;
+		FrmClk               : in std_logic;
+		FrmClkDiv            : in std_logic;
+		FrmClkDone           : in std_logic;		-- Input from clock syncronisation.
+		Frame_out            : out std_logic;
+		Frame_OK             : out std_logic
+	);
+end AdcFrame;
+-----------------------------------------------------------------------------------------------
+-- Architecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcFrame_struct of AdcFrame  is
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+--
+-- Constants
+
+-- Signals
+signal IntFrmClk                : std_logic := '0';
+signal IntFrmClk_n              : std_logic := '0';
+signal IntFrmSrdsOut            : std_logic_vector (7 downto 0);
+signal IntFrmEna                : std_logic := '0';
+signal Frame_out_S              : std_Logic := '0';
+signal Frame_OK_S               : std_Logic := '0';
+-- Attributes
+attribute keep                  : string;
+attribute KEEP_HIERARCHY        : string;
+attribute KEEP_HIERARCHY of AdcFrame_struct : architecture is "YES";
+attribute keep of Frame_out_S   : signal is "TRUE";
+-----------------------------------------------------------------------------------------------
+attribute mark_debug : string;
+-- attribute mark_debug of FrmClkRst : signal is "true";
+-- attribute mark_debug of IntFrmSrdsOut : signal is "true";
+-- attribute mark_debug of IntFrmEna : signal is "true";
+
+begin
+
+AdcFrame_I_Fdce_Done : FDCE
+    generic map (INIT => '0') -- bit
+    port map(D => FrmClkDone, CE => FrmClkEna, C => FrmClkDiv, CLR => FrmClkRst,
+             Q => IntFrmEna);
+
+-----------------------------------------------------------------------------------------------
+-- ISERDES FOR FRAME CAPTURE
+-----------------------------------------------------------------------------------------------
+IntFrmClk <= FrmClk;
+IntFrmClk_n <= not FrmClk;
+--
+AdcFrame_I_Isrds_p : ISERDESE2
+	generic map (
+		SERDES_MODE         => "MASTER",            -- string
+        INTERFACE_TYPE      => "NETWORKING",        -- string
+        IOBDELAY            => "NONE",              -- string
+        DATA_RATE           => "SDR",               -- string
+        DATA_WIDTH          => 4,   -- integer <-- Number of bits
+        DYN_CLKDIV_INV_EN   => "FALSE",             -- string
+        DYN_CLK_INV_EN      => "FALSE",             -- string
+        NUM_CE              => 1,                   -- integer
+        OFB_USED            => "FALSE",             -- string
+        INIT_Q1             => '0',                 -- bit;
+        INIT_Q2             => '0',                 -- bit;
+        INIT_Q3             => '0',                 -- bit;
+        INIT_Q4             => '0',                 -- bit;
+        SRVAL_Q1            => '0',                 -- bit;
+        SRVAL_Q2            => '0',                 -- bit;
+        SRVAL_Q3            => '0',                 -- bit;
+        SRVAL_Q4            => '0'                  -- bit
+	)
+	port map (
+		D				    => FrmClk_p,		    -- in
+		DDLY			    => '0',				    -- in
+		OFB				    => '0', 			    -- in
+		BITSLIP			    => '0',    -- in
+		CE1				    => IntFrmEna,      	    -- in
+		CE2				    => '0',				    -- in
+		RST				    => FrmClkRst,		    -- in
+		CLK				    => IntFrmClk,	 	    -- in
+		CLKB			    => '0', 			    -- in
+		CLKDIV			    => FrmClkDiv,	 	    -- in
+        CLKDIVP             => '0',                 -- in
+        OCLK			    => '0', 			    -- in
+        OCLKB               => '0',                 -- in
+		DYNCLKDIVSEL	    => '0', 			    -- in
+		DYNCLKSEL		    => '0', 			    -- in
+        SHIFTOUT1		    => open,	 		    -- out
+		SHIFTOUT2		    => open, 			    -- out
+		O				    => Frame_out_S,  -- open, 			    -- out
+		Q1				    => IntFrmSrdsOut(6),    -- out	(0)
+		Q2				    => IntFrmSrdsOut(4),    -- out	(2)
+		Q3				    => IntFrmSrdsOut(2),    -- out	(4)
+		Q4				    => IntFrmSrdsOut(0),    -- out	(6)
+		Q5				    => open,	 		    -- out
+		Q6				    => open, 			    -- out
+        Q7                  => open,                -- out
+        Q8                  => open,                -- out
+		SHIFTIN1		    => '0', 			    -- in
+		SHIFTIN2		    => '0'				    -- in
+	);
+Frame_out <= Frame_out_S;
+--
+AdcFrame_I_Isrds_n : ISERDESE2
+	generic map (
+        SERDES_MODE         => "MASTER",            -- string
+        INTERFACE_TYPE      => "NETWORKING",        -- string
+        IOBDELAY            => "NONE",              -- string
+        DATA_RATE           => "SDR",               -- string
+        DATA_WIDTH          => 4,   -- integer 12-bit = 3 and 14/16 b its = 4
+        DYN_CLKDIV_INV_EN   => "FALSE",             -- string
+        DYN_CLK_INV_EN      => "FALSE",             -- string
+        NUM_CE              => 1,                   -- integer
+        OFB_USED            => "FALSE",             -- string
+        INIT_Q1             => '0',                 -- bit;
+        INIT_Q2             => '0',                 -- bit;
+        INIT_Q3             => '0',                 -- bit;
+        INIT_Q4             => '0',                 -- bit;
+        SRVAL_Q1            => '0',                 -- bit;
+        SRVAL_Q2            => '0',                 -- bit;
+        SRVAL_Q3            => '0',                 -- bit;
+        SRVAL_Q4            => '0'                  -- bit
+	)
+	port map (
+		D				    => FrmClk_n,		    -- in
+		DDLY			    => '0',				    -- in
+		OFB				    => '0', 			    -- in
+		BITSLIP			    => '0',    -- in
+		CE1				    => IntFrmEna,      	    -- in
+		CE2				    => '0',				    -- in
+		RST				    => FrmClkRst,		    -- in
+		CLK				    => IntFrmClk_n,	 	    -- in
+		CLKB			    => '0', 			    -- in
+		CLKDIV			    => FrmClkDiv,	 	    -- in
+        CLKDIVP             => '0',                 -- in
+		OCLK			    => '0', 			    -- in
+        OCLKB               => '0',                 -- in
+		DYNCLKDIVSEL	    => '0', 			    -- in
+		DYNCLKSEL		    => '0', 			    -- in
+		SHIFTOUT1		    => open,	 		    -- out
+		SHIFTOUT2		    => open, 			    -- out
+		O				    => open, 			    -- out
+		Q1				    => IntFrmSrdsOut(7),    -- out	(1)
+		Q2				    => IntFrmSrdsOut(5),    -- out	(3)
+		Q3				    => IntFrmSrdsOut(3),    -- out	(5)
+		Q4				    => IntFrmSrdsOut(1),    -- out	(7)
+		Q5				    => open,	 		    -- out
+		Q6				    => open, 			    -- out
+        Q7                  => open,                -- out
+        Q8                  => open,                -- out        
+		SHIFTIN1		    => '0', 			    -- in
+		SHIFTIN2		    => '0'				    -- in
+	);
+
+-----------------------------------------------------------------------------------------------
+-- FRAME PATTERN COMPARATOR 
+-----------------------------------------------------------------------------------------------
+process(FrmClkDiv,FrmClkRst)
+begin
+	if FrmClkRst='1' then
+		Frame_OK_S <= '0';
+	elsif rising_edge(FrmClkDiv) then
+		if  IntFrmSrdsOut=x"a5" then 
+			Frame_OK_S <= '1';
+		else
+			Frame_OK_S <= '0';
+		end if;
+	end if;
+end process;
+Frame_OK <= Frame_OK_S;
+
+end  AdcFrame_struct;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcSerialProg.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcSerialProg.vhd
new file mode 100644
index 0000000..f9d328f
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcSerialProg.vhd
@@ -0,0 +1,320 @@
+---------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   06-11-2014
+-- Module Name:   AdcSerialProg
+-- Description:   Serial programming of LTM9009
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- AdcSerialProg
+-- Module to convert serial data from ADCs (LTM9009-14) to parallel
+-- Based on Xilinx serial ADC reference design
+--
+--
+-- Library:
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock200MHz : 200MHz clock input for IODELAYCTRL
+--     reset : reset ADCs
+--     ADCs_enable : enable signal for ADCs
+--     AD*_P : serial data links from ADCs, LVDS positive
+--     AD*_N : serial data links from ADCs, LVDS negative
+--     DCO*_P : data clock from ADCs, LVDS positive
+--     DCO*_N : data clock from ADCs, LVDS negative
+--     FRA*_P : frame start signals from ADCs, LVDS positive
+--     FRA*_N : frame start signals from ADCs, LVDS negative
+-- 
+-- Outputs:
+--     ADC_clk : clock for parallel ADC data
+--     adcdata : parallel ADC data
+-- 
+-- Components:
+--     AdcToplevel : top-level module from Xilinx serial ADC reference design
+--
+----------------------------------------------------------------------------------
+
+entity AdcSerialProg is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		init                    : in std_logic;
+		clock_out               : out std_logic;
+		dataA_in                : in std_logic_vector(3 downto 0);
+		dataB_in                : in std_logic_vector(3 downto 0);
+		data_out                : out std_logic;
+		chipnselectA            : out std_logic_vector(3 downto 0);
+		chipnselectB            : out std_logic_vector(3 downto 0);
+		selREGS       : in std_logic_vector(2 downto 0)
+		);
+end AdcSerialProg;
+
+architecture Behavioral of AdcSerialProg is
+
+constant NROFREGS : integer := 10;
+type RomType is array (0 to 8*16-1) of std_logic_vector(16 downto 0); -- highest bit : csa/csb
+--type RomType is array (0 to NROFREGS-1) of std_logic_vector(15 downto 0);
+--CONSTANT REGS : RomType := -- bit15:0=CSA,1=CSB
+--	( 
+--	"0000000010000000", -- A0 (bit7=Reset)		
+--	"1000000010000000", -- A0 (bit7=Reset)		
+--	"0000000100000000", -- A1 (clock stabilize no random binary normal)		
+--	"1000000100000000", -- A1 (clock stabilize no random binary normal)		
+--	"0000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)		
+--	"1000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)		
+--	"0000001100000000", -- A3 (no test pattern)		
+--	"1000001100000000", -- A3 (no test pattern)	
+--	"0000010000000000", -- A4 (test pattern)		
+--	"1000010000000000" -- A4 (test pattern)	
+--	);								
+CONSTANT REGS : RomType := -- bit15:0=CSA,1=CSB
+	( 
+	"00000000010000000", -- A0 (bit7=Reset)		
+	"10000000010000000", -- A0 (bit7=Reset)		
+	"00000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"10000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"00000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)		
+	"10000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)		
+	"00000001100000000", -- A3 (no test pattern)		
+	"10000001100000000", -- A3 (no test pattern)	
+	"00000010000000000", -- A4 (test pattern)		
+	"10000010000000000", -- A4 (test pattern)	
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	
+	"00000000010000000", -- A0 (bit7=Reset)		
+	"10000000010000000", -- A0 (bit7=Reset)		
+	"00000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"10000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"00000001000000001", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)		
+	"10000001000000001", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)		
+--	"00000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)		
+--	"10000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)		
+	"00000001100000000", -- A3 (no test pattern)		
+	"10000001100000000", -- A3 (no test pattern)	
+	"00000010000000000", -- A4 (test pattern)		
+	"10000010000000000", -- A4 (test pattern)	
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	
+	"00000000010000000", -- A0 (bit7=Reset)		
+	"10000000010000000", -- A0 (bit7=Reset)		
+	"00000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"10000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"00000001000100111", -- A2 (4mA LVDS no termination enabled 2lanes 16bits)		
+	"10000001000100111", -- A2 (4mA LVDS no termination enabled 2lanes 16bits)		
+--	"00000001000100000", -- A2 (4mA LVDS no termination enabled 2lanes 16bits)		
+--	"10000001000100000", -- A2 (4mA LVDS no termination enabled 2lanes 16bits)		
+	"00000001100000000", -- A3 (no test pattern)		
+	"10000001100000000", -- A3 (no test pattern)	
+	"00000010000000000", -- A4 (test pattern)		
+	"10000010000000000", -- A4 (test pattern)	
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	
+	"00000000010000000", -- A0 (bit7=Reset)		
+	"10000000010000000", -- A0 (bit7=Reset)		
+	"00000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"10000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"00000001001000000", -- A2 (4.5mA LVDS no termination enabled 2lanes 16bits)		
+	"10000001001000000", -- A2 (4.5mA LVDS no termination enabled 2lanes 16bits)		
+	"00000001100000000", -- A3 (no test pattern)		
+	"10000001100000000", -- A3 (no test pattern)	
+	"00000010000000000", -- A4 (test pattern)		
+	"10000010000000000", -- A4 (test pattern)	
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	
+	"00000000010000000", -- A0 (bit7=Reset)		
+	"10000000010000000", -- A0 (bit7=Reset)		
+	"00000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"10000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"00000001010100000", -- A2 (2.5mA LVDS +termination enabled 2lanes 16bits)		
+	"10000001010100000", -- A2 (2.5mA LVDS +termination enabled 2lanes 16bits)		
+	"00000001100000000", -- A3 (no test pattern)		
+	"10000001100000000", -- A3 (no test pattern)	
+	"00000010000000000", -- A4 (test pattern)		
+	"10000010000000000", -- A4 (test pattern)	
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	
+	"00000000010000000", -- A0 (bit7=Reset)		
+	"10000000010000000", -- A0 (bit7=Reset)		
+	"00000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"10000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"00000001011000000", -- A2 (2.1mA LVDS +termination enabled 2lanes 16bits)		
+	"10000001011000000", -- A2 (2.1mA LVDS +termination enabled 2lanes 16bits)		
+	"00000001100000000", -- A3 (no test pattern)		
+	"10000001100000000", -- A3 (no test pattern)	
+	"00000010000000000", -- A4 (test pattern)		
+	"10000010000000000", -- A4 (test pattern)	
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	
+	"00000000010000000", -- A0 (bit7=Reset)		
+	"10000000010000000", -- A0 (bit7=Reset)		
+	"00000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"10000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"00000001011100000", -- A2 (1.75mA LVDS +termination enabled 2lanes 16bits)		
+	"10000001011100000", -- A2 (1.75mA LVDS +termination enabled 2lanes 16bits)		
+	"00000001100000000", -- A3 (no test pattern)		
+	"10000001100000000", -- A3 (no test pattern)	
+	"00000010000000000", -- A4 (test pattern)		
+	"10000010000000000", -- A4 (test pattern)	
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	
+	"00000000010000000", -- A0 (bit7=Reset)		
+	"10000000010000000", -- A0 (bit7=Reset)		
+	"00000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"10000000100000000", -- A1 (clock stabilize no random binary normal)		
+	"00000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)		
+	"10000001000000000", -- A2 (3.5mA LVDS no termination enabled 2lanes 16bits)		
+	"00000001100000000", -- A3 (no test pattern)		
+	"10000001100000000", -- A3 (no test pattern)	
+	"00000010000000000", -- A4 (test pattern)		
+	"10000010000000000", -- A4 (test pattern)	
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000", -- dummy		
+	"00000000000000000" -- dummy		
+	
+	);								
+
+
+type stage_type is (waiting,cs_high,cs_low,sdo_set,clk_rise,clk_high,clk_fall);
+signal stage_S                : stage_type := waiting;
+
+--type adcdata_type is array(0 to 31) of std_logic_vector(13 downto 0); 
+type AdcDataOut_type is array(0 to 3) of std_logic_vector(127 downto 0);
+type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0); 
+signal bitcount_S             : integer range 0 to 15;
+signal regcount_S             : integer range 0 to NROFREGS-1;
+signal clock_out_S            : std_logic;
+signal data_out_S             : std_logic;
+signal chipnselectA_S         : std_logic;
+signal chipnselectB_S         : std_logic;
+signal REGS_out_S             : std_logic_vector(16 downto 0);
+	
+begin
+
+process (clock)
+begin
+	if (clock'event and clock = '1') then
+		REGS_out_S <= REGS(conv_integer(selREGS)*16+regcount_S);
+	end if;
+end process;
+
+
+
+clock_out <= clock_out_S;
+data_out <= data_out_S;
+chipnselectA <= chipnselectA_S & chipnselectA_S & chipnselectA_S & chipnselectA_S;
+chipnselectB <= chipnselectB_S & chipnselectB_S & chipnselectB_S & chipnselectB_S;
+
+process(clock)
+begin
+	if rising_edge(clock) then
+		if reset='1' then
+			chipnselectA_S <= '1';
+			chipnselectB_S <= '1';
+			clock_out_S <= '0';
+			stage_S <= waiting;
+		else
+			case stage_S is
+				when waiting =>
+					bitcount_S <= 15;
+					regcount_S <= 0;
+					chipnselectA_S <= '1';
+					chipnselectB_S <= '1';
+					clock_out_S <= '0';
+					if init='1' then
+						stage_S <= cs_high;
+					end if;
+				when cs_high =>
+					clock_out_S <= '0';
+					chipnselectA_S <= '1';
+					chipnselectB_S <= '1';
+					stage_S <= cs_low;
+				when cs_low =>
+					clock_out_S <= '0';
+					chipnselectA_S <= REGS_out_S(16);
+					chipnselectB_S <= not REGS_out_S(16);
+					stage_S <= sdo_set;
+				when sdo_set =>
+					data_out_S <= REGS_out_S(bitcount_S);
+					clock_out_S <= '0';
+					stage_S <= clk_rise;
+				when clk_rise =>
+					clock_out_S <= '1';
+					stage_S <= clk_high;
+				when clk_high =>
+					clock_out_S <= '1';
+					stage_S <= clk_fall;
+				when clk_fall =>
+					clock_out_S <= '0';
+					if bitcount_S=0 then
+						bitcount_S <= 15;
+						if regcount_S=NROFREGS-1 then
+							regcount_S <= 0;
+							stage_S <= waiting;
+						else
+							regcount_S <= regcount_S+1;
+							stage_S <= cs_high;
+						end if;
+					else
+						bitcount_S <= bitcount_S-1;
+						stage_S <= sdo_set;
+					end if;
+				when others =>
+					chipnselectA_S <= '1';
+					chipnselectB_S <= '1';
+					clock_out_S <= '0';
+					stage_S <= waiting;
+			end case;
+		end if;
+	end if;
+end process;
+
+			
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcToplevel.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcToplevel.vhd
new file mode 100644
index 0000000..0911450
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/AdcToplevel.vhd
@@ -0,0 +1,492 @@
+library IEEE;
+	use IEEE.std_logic_1164.all;
+	use IEEE.STD_LOGIC_ARITH.ALL;
+	use IEEE.std_logic_UNSIGNED.all;
+	use IEEE.std_logic_textio.all;
+	use std.textio.all;
+library UNISIM;
+	use UNISIM.VCOMPONENTS.all;
+
+
+entity AdcToplevel is
+	generic (
+		C_BufioLoc            : string := "BUFIO_X0Y6";
+		C_BufrLoc             : string := "BUFR_X0Y6";
+		C_IserdesLoc          : string := "BUFR_X0Y17";
+		C_StatTaps            : integer := 16;
+		C_AdcUseIdlyCtrl      : integer := 1;	     -- 0 = No, 1 = Yes
+		C_AdcIdlyCtrlLoc      : string := "IDELAYCTRL_X0Y1"
+	);
+	port (
+		DCLK_p               : in std_logic;
+		DCLK_n               : in std_logic; -- Not used.
+		FCLK_p               : in std_logic;
+		FCLK_n               : in std_logic;
+		DATA_p               : in std_logic_vector(7 downto 0);
+		DATA_n               : in std_logic_vector(7 downto 0);
+		SysRefClk            : in std_logic; -- 200 MHz for IODELAYCTRL from application
+		clockAsync           : in std_logic;
+		AdcIntrfcRst         : in std_logic;
+		AdcIntrfcEna         : in std_logic;
+		AdcBitClkDone        : out std_logic;
+		AdcIdlyCtrlRdy       : out std_logic;
+		AdcClkDiv            : out std_logic;
+		AdcDataClk           : in std_logic;	
+		AdcDataOut           : out std_logic_vector(127 downto 0);
+		ADCs_ready           : out std_logic
+	);
+end AdcToplevel;
+
+-----------------------------------------------------------------------------------------------
+-- Arcitecture section
+-----------------------------------------------------------------------------------------------
+architecture AdcToplevel_struct of AdcToplevel  is
+-----------------------------------------------------------------------------------------------
+-- Component Instantiation
+-----------------------------------------------------------------------------------------------
+component AdcFrame is
+	port (
+		FrmClk_n             : in std_logic;		-- input n from IBUFDS_DIFF_OUT
+		FrmClk_p             : in std_logic;		-- input p from IBUFDS_DIFF_OUT
+		FrmClkRst            : in std_logic;
+		FrmClkEna            : in std_logic;
+		FrmClk               : in std_logic;
+		FrmClkDiv            : in std_logic;
+		FrmClkDone           : in std_logic;		-- Input from clock syncronisation.
+		Frame_out            : out std_logic;
+		Frame_OK             : out std_logic
+	);
+end component;
+component AdcClock is
+	generic (
+		C_BufioLoc           : string := C_BufioLoc;
+		C_BufrLoc            : string := C_BufrLoc;
+		C_IserdesLoc         : string := C_IserdesLoc;
+		C_StatTaps           : integer := C_StatTaps
+	);
+	port (
+		BitClk               : in std_logic;
+		BitClkRst            : in std_logic;
+		BitClkEna            : in std_logic;
+		BitClkReSync         : in std_logic;
+		BitClk_MonClkOut     : out std_logic;   -- CLK output
+		BitClk_MonClkIn      : in std_logic;    -- ISERDES.CLK input
+		BitClk_RefClkOut     : out std_logic;   -- CLKDIV & logic output
+		BitClk_RefClkIn      : in std_logic;    -- CLKDIV & logic input
+		BitClkAlignWarn      : out std_logic;
+		BitClkInvrtd         : out std_logic;
+		BitClkDone           : out std_logic
+	);
+end component;
+component AdcData is
+	port (
+		DatD0_n              : in std_logic;
+		DatD0_p              : in std_logic;
+		DatD1_n              : in std_logic;
+		DatD1_p              : in std_logic;
+		DatClk               : in std_logic;
+		DatClkDiv            : in std_logic;
+		DatRst               : in std_logic;
+		DatEna               : in std_logic;
+		DatDone              : in std_logic;
+		DatOut               : out std_logic_vector(31 downto 0)
+	);
+end component;
+
+component posedge_to_pulse is
+	port (
+		clock_in     : in  std_logic;
+		clock_out     : in  std_logic;
+		en_clk    : in  std_logic;
+		signal_in : in  std_logic;
+		pulse     : out std_logic
+	);
+end component;
+
+
+-----------------------------------------------------------------------------------------------
+-- Constants, Signals and Attributes Declarations
+-----------------------------------------------------------------------------------------------
+
+-- Signals
+signal IntRst                : std_logic;
+signal IntEna_d              : std_logic;
+signal IntEna                : std_logic;
+--
+signal IntBitClkDone         : std_logic;
+signal IntClk                : std_logic;
+signal IntClkDiv             : std_logic;
+signal IntDataOut            : std_logic_vector(127 downto 0);
+-----------------------------------------------------------------------------------------------
+--
+
+signal AdcBitClkAlgnWrn_S    : std_logic := '0';
+signal AdcBitClkInvrtd_S     : std_logic := '0';
+signal AdcIdlyCtrlRdy_S      : std_logic := '0';
+signal Frame_OK_S            : std_logic := '0';
+signal ADCs_ready_S          : std_logic := '0';
+signal IntBitClkDone_S       : std_logic := '0';
+signal IntBitClkDone0_S      : std_logic := '0';
+
+signal slipcounter_S         : integer range 0 to 63 := 0;
+signal ClockResync_S         : std_logic := '0';
+signal ClockResync0_S        : std_logic := '0';
+signal ClockResync1_S        : std_logic := '0';
+signal ClockResync2_S        : std_logic := '0';
+signal ClockReset_S          : std_logic := '0';
+
+signal IntEna_S              : std_logic := '0';
+signal IntRst_S              : std_logic := '0';
+signal IntEna0_S             : std_logic := '0';
+signal IntRst0_S             : std_logic := '0';
+signal frame_S               : std_logic := '0';
+signal reset_S               : std_logic := '0';
+
+
+signal AdcData_negedge       : std_logic_vector(127 downto 0);
+signal AdcDataOut_S          : std_logic_vector(127 downto 0);
+
+signal AdcIntrfcRst_IdlyCtrl_S : std_logic := '1';
+signal AdcIntrfcRst_IntClkDiv_S : std_logic := '1';
+signal AdcIntrfcRst_clockAsync_S : std_logic := '1';
+	
+-- Attributes
+attribute keep               : string;
+attribute LOC                : string;
+attribute KEEP_HIERARCHY     : string;
+attribute keep	of IntClk     : signal is "TRUE";
+attribute keep	of IntClkDiv  : signal is "TRUE";
+attribute keep	of IntRst_S   : signal is "TRUE";
+attribute keep	of IntEna_S   : signal is "TRUE";
+attribute keep	of IntBitClkDone_S   : signal is "TRUE";
+
+attribute mark_debug : string;
+-- attribute mark_debug of IntDataOut : signal is "true";
+-- attribute mark_debug of AdcBitClkAlgnWrn_S : signal is "true";
+-- attribute mark_debug of AdcBitClkInvrtd_S : signal is "true";
+-- attribute mark_debug of IntBitClkDone : signal is "true";
+-- attribute mark_debug of ClockReset_S : signal is "true";
+-- attribute mark_debug of ClockResync_S : signal is "true";
+-- attribute mark_debug of IntEna_S : signal is "true";
+-- attribute mark_debug of IntRst_S : signal is "true";
+-- attribute mark_debug of IntBitClkDone_S : signal is "true";
+-- attribute mark_debug of AdcIdlyCtrlRdy_S : signal is "true";
+-- attribute mark_debug of Frame_OK_S : signal is "true";
+-- attribute mark_debug of ADCs_ready_S : signal is "true";
+-- attribute mark_debug of AdcIntrfcRst : signal is "true";
+
+
+	
+attribute KEEP_HIERARCHY of AdcToplevel_struct : architecture is "YES";
+-----------------------------------------------------------------------------------------------
+--
+begin
+
+
+AdcClkDiv <= IntClkDiv;
+ADCs_ready <= ADCs_ready_S;
+AdcBitClkDone <= IntBitClkDone_S;
+
+process(IntClkDiv)
+begin
+	if falling_edge(IntClkDiv) then -- falling_edge
+		AdcData_negedge <= IntDataOut;
+	end if;
+end process;
+
+process(AdcDataClk)
+begin
+	if rising_edge(AdcDataClk) then 
+		AdcDataOut <= AdcData_negedge;
+	end if;
+end process;
+--AdcDataOut <= IntDataOut;
+
+-----------------------------------------------------------------------------------------------
+-- IDELAYCTRL
+-- An IDELAYCTRL component must be used per IO-bank. Normally a ADC port fits a whole
+-- IO-Bank. The number of IDELAYCTRL components should thus fit with the number of ADC port.
+-- In case of this test design, two ADC ports fit into one IO-Bank, thus only one IDLEAYCTRL
+-- component is needed.
+-- Don not forget to hook the outputs of the IDELAYCTRL components correctly to the reset and
+-- enable for each ADC block.
+-- Don not forget to LOC the IDELAYCTRL components down.
+-----------------------------------------------------------------------------------------------
+Gen_0 : if C_AdcUseIdlyCtrl = 0 generate
+	AdcIdlyCtrlRdy_S <= '1';
+end generate Gen_0;
+Gen_1 : if C_AdcUseIdlyCtrl = 1 generate
+	attribute LOC of AdcToplevel_I_IdlyCtrl_0 : label is C_AdcIdlyCtrlLoc;
+begin
+	AdcToplevel_I_IdlyCtrl_0 : IDELAYCTRL
+--//		port map (REFCLK => SysRefClk, RST => ClockResync_S, RDY => AdcIdlyCtrlRdy); --AdcIntrfcRst
+		port map (REFCLK => SysRefClk, RST => AdcIntrfcRst_IdlyCtrl_S, RDY => AdcIdlyCtrlRdy_S); --
+end generate Gen_1;
+AdcIdlyCtrlRdy <= AdcIdlyCtrlRdy_S;
+
+process(SysRefClk)
+begin
+	if (rising_edge(SysRefClk)) then
+		AdcIntrfcRst_IdlyCtrl_S <= AdcIntrfcRst;
+	end if;
+end process;
+process(IntClkDiv,AdcIntrfcRst)
+begin
+	if AdcIntrfcRst='1' then
+		AdcIntrfcRst_IntClkDiv_S <= '1';
+	elsif (rising_edge(IntClkDiv)) then
+		AdcIntrfcRst_IntClkDiv_S <= AdcIntrfcRst;
+	end if;
+end process;
+process(clockAsync,AdcIntrfcRst)
+begin
+	if AdcIntrfcRst='1' then
+		AdcIntrfcRst_clockAsync_S <= '1';
+	elsif (rising_edge(clockAsync)) then
+		AdcIntrfcRst_clockAsync_S <= AdcIntrfcRst;
+	end if;
+end process;
+
+
+-- IntRst and IntEna are the reset and enable signals to be used in the interafce.
+-- they are generated from the incomming system enable and reset.
+AdcToplevel_I_Fdpe_Rst : FDPE
+	generic map (INIT => '1')
+	port map (C => IntClkDiv, CE => '1', PRE => AdcIntrfcRst_IntClkDiv_S, D => '0', Q => IntRst); --AdcIntrfcRst
+AdcToplevel_I_Fdce_Ena_0 : FDCE
+	generic map (INIT => '0')
+	port map (C => IntClkDiv, CE => AdcIntrfcEna, CLR => IntRst, D => '1', Q => IntEna_d);
+AdcToplevel_I_Fdce_Ena_1 : FDCE
+	generic map (INIT => '0')
+	port map (C => IntClkDiv, CE => '1', CLR => IntRst, D => IntEna_d, Q => IntEna);
+
+-----------------------------------------------------------------------------------------------
+-- BIT CLOCK
+-- IntClk and IntClkDiv are the clock to be used in the interface.
+-----------------------------------------------------------------------------------------------
+-- There is no IBUFGDS used on this level of the design.
+-- The IBUFGDS can be found in the AdcIo level.
+-- That is this the reason why the DCLK_n is not used here.
+-- At the AdcIo level the DCLK_n output is connected to GND.
+AdcToplevel_I_AdcClock : AdcClock
+generic map (
+        C_BufioLoc => C_BufioLoc,      -- string  
+        C_BufrLoc => C_BufrLoc,       -- string
+        C_StatTaps => C_StatTaps       -- integer
+    )
+port map (
+	BitClk => DCLK_p,			-- in
+	BitClkRst => IntRst, -- ClockReset_S, --//IntRst, -- IntRst,			-- in
+	BitClkEna => IntEna,			-- in
+	BitClkReSync => ClockResync_S,  -- AdcReSync,		-- in
+	BitClk_MonClkOut => IntClk,			-- out	-->--|---->----
+	BitClk_MonClkIn => IntClk,			-- in	--<--|
+	BitClk_RefClkOut => IntClkDiv,		-- out	-->----|-->----
+	BitClk_RefClkIn => IntClkDiv,		-- in	--<----|
+	BitClkAlignWarn => AdcBitClkAlgnWrn_S,-- out
+	BitClkInvrtd => AdcBitClkInvrtd_S,	-- out
+	BitClkDone => IntBitClkDone	-- out Enables the AdcFrame block.
+);
+
+
+AdcToplevel_I_AdcFrame : AdcFrame
+port map (
+	FrmClk_n => FCLK_n,			-- in input n from IBUFDS_DIFF_OUT
+	FrmClk_p => FCLK_p,			-- in input p from IBUFDS_DIFF_OUT
+	FrmClkRst => IntRst_S,			-- in
+	FrmClkEna => IntEna_S,			-- in
+	FrmClk => IntClk,			-- in
+	FrmClkDiv => IntClkDiv,		-- in
+	FrmClkDone => IntBitClkDone_S,	-- in From AdcClock done.
+	Frame_out => frame_S,
+	Frame_OK => Frame_OK_S
+);
+
+-----------------------------------------------------------------------------------------------
+-- DATA INPUTS
+-- Default the interface is set in BYTE and MSB first mode.
+-- This is coded in the AdcData level and can be mnodified if wanted.
+-- Enable the generics and all selection possibilities are available.  
+-----------------------------------------------------------------------------------------------
+Gen_2 : for cw in 3 downto 0 generate
+	AdcToplevel_I_AdcData : AdcData
+	port map (
+		DatD0_n => DATA_n(cw*2),		-- in 
+		DatD0_p => DATA_p(cw*2),		-- in 
+		DatD1_n => DATA_n((cw*2)+1),	-- in 
+		DatD1_p => DATA_p((cw*2)+1),	-- in 
+		DatClk => IntClk,				-- in 
+		DatClkDiv => IntClkDiv,			-- in 
+		DatRst => IntRst_S,				-- in 
+		DatEna => IntEna_S,				-- in 
+		DatDone => IntBitClkDone_S,		-- in 
+		DatOut => IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-32)
+	);
+end generate Gen_2;
+
+--process(SysRefClk)
+--begin
+--	if (rising_edge(SysRefClk)) then 
+--		if (AdcIntrfcRst='1') then -- or (ClockResync0_S='1') then
+--			reset_clockdiv0_S <= '1';
+--		elsif frame_S='1' then
+--			reset_clockdiv0_S <= '0';
+--		end if;
+--	end if;
+--end process;
+
+--process(IntClkDiv,reset_clockdiv0_S)
+--variable counter_V : integer range 0 to 3 := 0;
+--begin
+--	if reset_clockdiv0_S='1' then
+--		ClockResync_S <= '0';
+--		counter_V := 0;
+--	elsif (rising_edge(IntClkDiv)) then
+--		if counter_V<3 then
+--			counter_V := counter_V+1;
+--			ClockResync_S <= '1';
+--		else
+--			ClockResync_S <= '0';
+--		end if;
+--	end if;
+--end process;
+--ClockResync_S <= ClockResync0_S;
+--posedge_to_pulse1: posedge_to_pulse port map(
+--		clock_in => IntClkDiv,
+--		clock_out => clockAsync,
+--		en_clk => '1',
+--		signal_in => ClockResync1_S,
+--		pulse => ClockResync_S
+--	);
+
+--process(clockAsync,AdcIntrfcRst)
+--variable count_V : integer range 0 to 127 := 0;
+--variable countsync_V : integer range 0 to 127 := 7;
+--begin
+--	if (AdcIntrfcRst='1') then
+--		reset_S <= '1';
+--		ClockResync_S <= '1';
+--		count_V := 0;
+--	elsif (rising_edge(clockAsync)) then
+--		if count_V=0 then
+--			if countsync_V>25 then
+--				countsync_V := 7;
+--			else
+--				countsync_V := countsync_V+1;
+--			end if;
+--		end if;
+--		ClockResync1_S <= ClockResync0_S;
+--		ClockResync2_S <= ClockResync1_S;
+--		if (ClockResync2_S='0') and (ClockResync1_S='1') then
+--			reset_S <= '1';
+--			ClockResync_S <= '1';
+--			count_V := 0;
+--		elsif (count_V<countsync_V) then
+--			reset_S <= '1';
+--			ClockResync_S <= '1';
+--			count_V := count_V+1;
+--		elsif (count_V<127) then
+--			reset_S <= '1';
+--			ClockResync_S <= '0';
+--			count_V := count_V+1;
+--		else
+--			ClockResync_S <= '0';
+--			reset_S <= '0';
+--		end if;
+--	end if;
+--end process;
+
+process(clockAsync,AdcIntrfcRst_clockAsync_S)
+variable count_V : integer range 0 to 7 := 0;
+begin
+	if (AdcIntrfcRst_clockAsync_S='1') then
+		reset_S <= '1';
+		ClockResync_S <= '1';
+		count_V := 0;
+	elsif (rising_edge(clockAsync)) then
+		ClockResync1_S <= ClockResync0_S;
+		ClockResync2_S <= ClockResync1_S;
+		if (ClockResync2_S='0') and (ClockResync1_S='1') then
+			ClockResync_S <= '1';
+			ClockReset_S <= '1';
+			reset_S <= '1';
+			count_V := 0;
+		elsif (count_V<2) then
+			ClockResync_S <= '1';
+			ClockReset_S <= '1';
+			reset_S <= '1';
+			count_V := count_V+1;
+		elsif (count_V<7) then
+			ClockResync_S <= '0';
+			ClockReset_S <= '1';
+			reset_S <= '1';
+			count_V := count_V+1;
+		else
+			ClockResync_S <= '0';
+			ClockReset_S <= '0';
+			reset_S <= '0';
+		end if;
+	end if;
+end process;
+
+
+process(IntClkDiv,AdcIntrfcRst_IntClkDiv_S,AdcIdlyCtrlRdy_S)
+begin
+	if (AdcIntrfcRst_IntClkDiv_S='1') or (AdcIdlyCtrlRdy_S='0') then
+		slipcounter_S <= 0;
+		ClockResync0_S <= '0'; 
+		IntEna0_S <= '0';
+		IntRst0_S <= '1';
+		ADCs_ready_S <= '0';
+		IntBitClkDone0_S <= '0';
+	elsif (rising_edge(IntClkDiv)) then
+		if (IntBitClkDone='0') or (ClockResync0_S='1') then
+			slipcounter_S <= 0;
+			ClockResync0_S <= '0';
+			IntEna0_S <= '0';
+			IntRst0_S <= '1';
+			ADCs_ready_S <= '0';
+			IntBitClkDone0_S <= '0';
+		elsif slipcounter_S<8 then
+			slipcounter_S <= slipcounter_S+1;
+			ClockResync0_S <= '0';
+			IntEna0_S <= '0';
+			IntRst0_S <= '1';
+			IntBitClkDone0_S <= '0';
+		elsif IntBitClkDone='0' then
+		elsif (AdcBitClkAlgnWrn_S='1') or (AdcBitClkInvrtd_S='1') then 
+			ClockResync0_S <= '1';
+		elsif slipcounter_S<24 then
+			slipcounter_S <= slipcounter_S+1;
+			ClockResync0_S <= '0';
+			IntEna0_S <= '1';
+			IntRst0_S <= '0';
+		elsif slipcounter_S<28 then
+			slipcounter_S <= slipcounter_S+1;
+			IntBitClkDone0_S <= '1';
+			IntEna0_S <= '1';
+			IntRst0_S <= '0';
+		elsif slipcounter_S<63 then
+			slipcounter_S <= slipcounter_S+1;
+		else
+			if (Frame_OK_S='0') then 
+				ClockResync0_S <= '1';
+			else
+				ADCs_ready_S <= '1';
+			end if;
+		end if;
+	end if;
+end process;
+
+sync_IntRst : FDPE
+	generic map (INIT => '0')
+	port map (C => IntClkDiv, CE => '1', PRE => IntRst, D => IntRst0_S, Q => IntRst_S);
+sync_IntEna : FDCE
+	generic map (INIT => '0')
+	port map (C => IntClkDiv, CE => '1', CLR => IntRst, D => IntEna0_S, Q => IntEna_S);
+sync_IntBitClkDone : FDCE
+	generic map (INIT => '0')
+	port map (C => IntClkDiv, CE => '1', CLR => '0', D => IntBitClkDone0_S, Q => IntBitClkDone_S);
+
+
+end AdcToplevel_struct;
\ No newline at end of file
diff --git a/FEE_ADC32board/modules/FEE_ADCinput_module.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_ADCinput_module.vhd
similarity index 65%
rename from FEE_ADC32board/modules/FEE_ADCinput_module.vhd
rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_ADCinput_module.vhd
index 05c8721..9a99677 100644
--- a/FEE_ADC32board/modules/FEE_ADCinput_module.vhd
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_ADCinput_module.vhd
@@ -26,7 +26,7 @@ use UNISIM.VComponents.all;
 -- 
 -- Inputs:
 --     clock200MHz : 200MHz clock input for IODELAYCTRL
---     reset : reset ADCs
+--     reset : reset ADCs
 --     ADCs_enable : enable signal for ADCs
 --     AD*_P : serial data links from ADCs, LVDS positive
 --     AD*_N : serial data links from ADCs, LVDS negative
@@ -47,6 +47,8 @@ use UNISIM.VComponents.all;
 entity FEE_ADCinput_module is
 	port ( 
 		clock200MHz             : in std_logic;
+		clock80MHz              : in std_logic;
+		clockAsync              : in std_logic;
 		reset                   : in std_logic;
 		ADCs_enable             : in std_logic;
 ----ADC1---------------------------------------------		
@@ -225,76 +227,69 @@ entity FEE_ADCinput_module is
 		FRB4_P                  : in std_logic;
 		FRB4_N                  : in std_logic;
 		ADC_clk                 : out std_logic;
-		ADCs_ready              : out std_logic;
+		ADCs_ready              : out std_logic;
 		adcdata                 : out array_adc_type
 		);
 end FEE_ADCinput_module;
 
 architecture Behavioral of FEE_ADCinput_module is
-
-
+constant C_StatTaps           : integer := 10;-- 10 = midden van 20 steps voor 80MHz/2 DDR
 
 component AdcToplevel is
 	generic (
-		C_AdcChnls          : integer := 4;     -- Number of ADC in a package 
-		C_AdcWireInt        : integer := 2;     -- 2 = 2-wire, 1 = 1-wire interface
-		C_BufioLoc          : string  := "BUFIODQS_X1Y15";
-		C_BufrLoc           : string  := "BUFR_X0Y6";
-		C_AdcBits           : integer := 16;
-		C_StatTaps          : integer := 16;
-		C_AdcUseIdlyCtrl	  : integer := 1;	     -- 0 = No, 1 = Yes
-		C_AdcIdlyCtrlLoc	  : string  := "IDELAYCTRL_X0Y3";
-		C_FrmPattern        : string  := "0000000000001111" -- "0000000011110000"  -- Read above text!  
+		C_BufioLoc            : string := "BUFIO_X0Y6";
+		C_BufrLoc             : string := "BUFR_X0Y6";
+		C_IserdesLoc          : string := "BUFR_X0Y17";
+		C_StatTaps            : integer := C_StatTaps;
+		C_AdcUseIdlyCtrl      : integer := 1;	     -- 0 = No, 1 = Yes
+		C_AdcIdlyCtrlLoc      : string := "IDELAYCTRL_X0Y1"
 	);
     port (
-		DCLK_p	           : in std_logic;
-		DCLK_n	           : in std_logic;  -- Not used.
-		FCLK_p	           : in std_logic;
-		FCLK_n	           : in std_logic;
-		DATA_p	           : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
-		DATA_n	           : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
-		-- application connections
-		SysRefClk           : in std_logic;		-- 200 MHz for IODELAYCTRL from application
-		AdcIntrfcRst        : in std_logic;
-		AdcIntrfcEna        : in std_logic;
-		AdcReSync           : in std_logic;
-		AdcFrmSyncWrn       : out std_logic;
-		AdcBitClkAlgnWrn    : out std_logic;
-		AdcBitClkInvrtd     : out std_logic;
-		AdcBitClkDone       : out std_logic;
-		AdcIdlyCtrlRdy      : out std_logic;
-
-		AdcClkDiv           : out std_logic;
-		AdcDataClk          : in std_logic;	
-		AdcDataClkNot       : in std_logic;	
-		AdcDataOut 			  : out std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
-		ADCs_ready          : out std_logic;
-		testOK              : out std_logic;
- 		testword0 			  : out std_logic_vector(35 downto 0)
+		DCLK_p               : in std_logic;
+		DCLK_n               : in std_logic; -- Not used.
+		FCLK_p               : in std_logic;
+		FCLK_n               : in std_logic;
+		DATA_p               : in std_logic_vector(7 downto 0);
+		DATA_n               : in std_logic_vector(7 downto 0);
+		SysRefClk            : in std_logic; -- 200 MHz for IODELAYCTRL from application
+		clockAsync           : in std_logic;
+		AdcIntrfcRst         : in std_logic;
+		AdcIntrfcEna         : in std_logic;
+		AdcBitClkDone        : out std_logic;
+		AdcIdlyCtrlRdy       : out std_logic;
+		AdcClkDiv            : out std_logic;
+		AdcDataClk           : in std_logic;	
+		AdcDataOut           : out std_logic_vector(127 downto 0);
+		ADCs_ready           : out std_logic
    );
-end component;
-
-component FEE_clockbuf80MHz
-	port(
-		CLK_IN1           : in     std_logic;
-		CLK_OUT1          : out    std_logic;
-		CLK_OUT2          : out    std_logic
-	);
-end component;
-
-function TermOrNot (Term : integer) return boolean is
-begin
-	if (Term = 0) then
-		return FALSE;
-	else
-		return TRUE;
-	end if;
-end TermOrNot;
-
-constant C_OnChipLvdsTerm     : integer := 1;
+end component;
+
+component FEE_clockbuf80MHz
+	port(
+		CLK_IN1           : in     std_logic;
+		CLK_OUT1          : out    std_logic;
+		CLK_OUT2          : out    std_logic
+	);
+end component;
+
+--COMPONENT async_fifo_512x128
+--  PORT (
+--    rst : IN STD_LOGIC;
+--    wr_clk : IN STD_LOGIC;
+--    rd_clk : IN STD_LOGIC;
+--    din : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
+--    wr_en : IN STD_LOGIC;
+--    rd_en : IN STD_LOGIC;
+--    dout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
+--    full : OUT STD_LOGIC;
+--    empty : OUT STD_LOGIC
+--  );
+--END COMPONENT;
+
+constant C_OnChipLvdsTerm     : boolean := true;
 
 --type adcdata_type is array(0 to 31) of std_logic_vector(13 downto 0); 
-type AdcDataOut_type is array(0 to 3) of std_logic_vector((32*((4/2)*2))-1 downto 0);
+type AdcDataOut_type is array(0 to 3) of std_logic_vector(127 downto 0);
 type adcdataserial_type is array(0 to 3) of std_logic_vector(7 downto 0); 
 
 signal adcdata1458_P          : adcdataserial_type;
@@ -353,299 +348,313 @@ signal AdcIdlyCtrlRdyB_S      : std_logic_vector(0 to 3);
 signal AdcBitClkInvrtdB_S     : std_logic_vector(0 to 3);
 signal adcclockB_S            : std_logic_vector(0 to 3);
 signal AdcDataOutB_S          : AdcDataOut_type;
-
+
+signal ADCs_ready0_S          : std_logic_vector(0 to 7);
+signal ADCs_ready1_S          : std_logic_vector(0 to 7);
 signal ADCs_ready_S           : std_logic_vector(0 to 7);
 
 signal adcdata0_S             : array_adc_type;
 signal adcdata1_S             : array_adc_type;
 
-signal ADC_clk_S              : std_logic;
-signal ADC_clknot_S           : std_logic;
+signal ADC_clk_S              : std_logic;
+
+attribute keep                : string;
+attribute DONT_TOUCH          : string;
+attribute keep of ADC_clk_S   : signal is "TRUE";
+attribute DONT_TOUCH of ADC_clk_S : signal is "TRUE";
+
+signal sync_AdcDataOutA_S     : AdcDataOut_type;
+signal sync_AdcDataOutB_S     : AdcDataOut_type;
 
-attribute keep                : string;
-attribute keep of ADC_clk_S   : signal is "TRUE";
-attribute keep of ADC_clknot_S: signal is "TRUE";
+attribute mark_debug : string;
+--attribute mark_debug of ADCs_ready1_S : signal is "true";
 
 begin
 
 ADC_clk <= ADC_clk_S;
-ADCs_ready <= '1' when (ADCs_ready_S=x"ff") and (reset='0') else '0';
-
+ADCs_ready <= '1' when (ADCs_ready1_S=x"ff") and (reset='0') else '0';
+
+process(clock80MHz) -- synchronise to 1 clock
+begin
+	if (rising_edge(clock80MHz)) then 
+		ADCs_ready0_S <= ADCs_ready_S;
+		ADCs_ready1_S <= ADCs_ready0_S;
+	end if;
+end process;
 
 -- ADC inputs ----------------------------------------------------------------------
 ---- B and A swopped !!!
 adcdata1458_0B0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD11B_P, IB => AD11B_N, O => adcdata1458_P(0)(0), OB => adcdata1458_N(0)(0));
 adcdata1458_0A0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD11A_P, IB => AD11A_N, O => adcdata1458_P(0)(1), OB => adcdata1458_N(0)(1));
 adcdata1458_0B1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD14B_P, IB => AD14B_N, O => adcdata1458_P(0)(2), OB => adcdata1458_N(0)(2));
 adcdata1458_0A1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD14A_P, IB => AD14A_N, O => adcdata1458_P(0)(3), OB => adcdata1458_N(0)(3));
 adcdata1458_0B2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD15B_P, IB => AD15B_N, O => adcdata1458_P(0)(4), OB => adcdata1458_N(0)(4));
 adcdata1458_0A2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD15A_P, IB => AD15A_N, O => adcdata1458_P(0)(5), OB => adcdata1458_N(0)(5));
 adcdata1458_0B3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD18B_P, IB => AD18B_N, O => adcdata1458_P(0)(6), OB => adcdata1458_N(0)(6));
 adcdata1458_0A3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD18A_P, IB => AD18A_N, O => adcdata1458_P(0)(7), OB => adcdata1458_N(0)(7));
 
 adcdata2367_0B0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD12B_P, IB => AD12B_N, O => adcdata2367_P(0)(0), OB => adcdata2367_N(0)(0));
 adcdata2367_0A0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD12A_P, IB => AD12A_N, O => adcdata2367_P(0)(1), OB => adcdata2367_N(0)(1));
 adcdata2367_0B1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD13B_P, IB => AD13B_N, O => adcdata2367_P(0)(2), OB => adcdata2367_N(0)(2));
 adcdata2367_0A1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD13A_P, IB => AD13A_N, O => adcdata2367_P(0)(3), OB => adcdata2367_N(0)(3));
 adcdata2367_0B2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD16B_P, IB => AD16B_N, O => adcdata2367_P(0)(4), OB => adcdata2367_N(0)(4));
 adcdata2367_0A2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD16A_P, IB => AD16A_N, O => adcdata2367_P(0)(5), OB => adcdata2367_N(0)(5));
 adcdata2367_0B3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD17B_P, IB => AD17B_N, O => adcdata2367_P(0)(6), OB => adcdata2367_N(0)(6));
 adcdata2367_0A3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD17A_P, IB => AD17A_N, O => adcdata2367_P(0)(7), OB => adcdata2367_N(0)(7));
 
 adcdata1458_1B0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD21B_P, IB => AD21B_N, O => adcdata1458_P(1)(0), OB => adcdata1458_N(1)(0));
 adcdata1458_1A0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD21A_P, IB => AD21A_N, O => adcdata1458_P(1)(1), OB => adcdata1458_N(1)(1));
 adcdata1458_1B1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD24B_P, IB => AD24B_N, O => adcdata1458_P(1)(2), OB => adcdata1458_N(1)(2));
 adcdata1458_1A1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD24A_P, IB => AD24A_N, O => adcdata1458_P(1)(3), OB => adcdata1458_N(1)(3));
 adcdata1458_1B2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD25B_P, IB => AD25B_N, O => adcdata1458_P(1)(4), OB => adcdata1458_N(1)(4));
 adcdata1458_1A2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD25A_P, IB => AD25A_N, O => adcdata1458_P(1)(5), OB => adcdata1458_N(1)(5));
 adcdata1458_1B3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD28B_P, IB => AD28B_N, O => adcdata1458_P(1)(6), OB => adcdata1458_N(1)(6));
 adcdata1458_1A3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD28A_P, IB => AD28A_N, O => adcdata1458_P(1)(7), OB => adcdata1458_N(1)(7));
 
 adcdata2367_1B0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD22B_P, IB => AD22B_N, O => adcdata2367_P(1)(0), OB => adcdata2367_N(1)(0));
 adcdata2367_1A0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD22A_P, IB => AD22A_N, O => adcdata2367_P(1)(1), OB => adcdata2367_N(1)(1));
 adcdata2367_1B1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD23B_P, IB => AD23B_N, O => adcdata2367_P(1)(2), OB => adcdata2367_N(1)(2));
 adcdata2367_1A1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD23A_P, IB => AD23A_N, O => adcdata2367_P(1)(3), OB => adcdata2367_N(1)(3));
 adcdata2367_1B2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD26B_P, IB => AD26B_N, O => adcdata2367_P(1)(4), OB => adcdata2367_N(1)(4));
 adcdata2367_1A2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD26A_P, IB => AD26A_N, O => adcdata2367_P(1)(5), OB => adcdata2367_N(1)(5));
 adcdata2367_1B3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD27B_P, IB => AD27B_N, O => adcdata2367_P(1)(6), OB => adcdata2367_N(1)(6));
 adcdata2367_1A3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD27A_P, IB => AD27A_N, O => adcdata2367_P(1)(7), OB => adcdata2367_N(1)(7));
 	
 adcdata1458_2B0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD31B_P, IB => AD31B_N, O => adcdata1458_P(2)(0), OB => adcdata1458_N(2)(0));
 adcdata1458_2A0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD31A_P, IB => AD31A_N, O => adcdata1458_P(2)(1), OB => adcdata1458_N(2)(1));
 adcdata1458_2B1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD34B_P, IB => AD34B_N, O => adcdata1458_P(2)(2), OB => adcdata1458_N(2)(2));
 adcdata1458_2A1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD34A_P, IB => AD34A_N, O => adcdata1458_P(2)(3), OB => adcdata1458_N(2)(3));
 adcdata1458_2B2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD35B_P, IB => AD35B_N, O => adcdata1458_P(2)(4), OB => adcdata1458_N(2)(4));
 adcdata1458_2A2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD35A_P, IB => AD35A_N, O => adcdata1458_P(2)(5), OB => adcdata1458_N(2)(5));
 adcdata1458_2B3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD38B_P, IB => AD38B_N, O => adcdata1458_P(2)(6), OB => adcdata1458_N(2)(6));
 adcdata1458_2A3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD38A_P, IB => AD38A_N, O => adcdata1458_P(2)(7), OB => adcdata1458_N(2)(7));
 
 adcdata2367_2B0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD32B_P, IB => AD32B_N, O => adcdata2367_P(2)(0), OB => adcdata2367_N(2)(0));
 adcdata2367_2A0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD32A_P, IB => AD32A_N, O => adcdata2367_P(2)(1), OB => adcdata2367_N(2)(1));
 adcdata2367_2B1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD33B_P, IB => AD33B_N, O => adcdata2367_P(2)(2), OB => adcdata2367_N(2)(2));
 adcdata2367_2A1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD33A_P, IB => AD33A_N, O => adcdata2367_P(2)(3), OB => adcdata2367_N(2)(3));
 adcdata2367_2B2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD36B_P, IB => AD36B_N, O => adcdata2367_P(2)(4), OB => adcdata2367_N(2)(4));
 adcdata2367_2A2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD36A_P, IB => AD36A_N, O => adcdata2367_P(2)(5), OB => adcdata2367_N(2)(5));
 adcdata2367_2B3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD37B_P, IB => AD37B_N, O => adcdata2367_P(2)(6), OB => adcdata2367_N(2)(6));
 adcdata2367_2A3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD37A_P, IB => AD37A_N, O => adcdata2367_P(2)(7), OB => adcdata2367_N(2)(7));
 	
 adcdata1458_3B0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD41B_P, IB => AD41B_N, O => adcdata1458_P(3)(0), OB => adcdata1458_N(3)(0));
 adcdata1458_3A0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD41A_P, IB => AD41A_N, O => adcdata1458_P(3)(1), OB => adcdata1458_N(3)(1));
 adcdata1458_3B1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD44B_P, IB => AD44B_N, O => adcdata1458_P(3)(2), OB => adcdata1458_N(3)(2));
 adcdata1458_3A1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD44A_P, IB => AD44A_N, O => adcdata1458_P(3)(3), OB => adcdata1458_N(3)(3));
 adcdata1458_3B2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD45B_P, IB => AD45B_N, O => adcdata1458_P(3)(4), OB => adcdata1458_N(3)(4));
 adcdata1458_3A2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD45A_P, IB => AD45A_N, O => adcdata1458_P(3)(5), OB => adcdata1458_N(3)(5));
 adcdata1458_3B3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD48B_P, IB => AD48B_N, O => adcdata1458_P(3)(6), OB => adcdata1458_N(3)(6));
 adcdata1458_3A3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD48A_P, IB => AD48A_N, O => adcdata1458_P(3)(7), OB => adcdata1458_N(3)(7));
 
 adcdata2367_3B0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD42B_P, IB => AD42B_N, O => adcdata2367_P(3)(0), OB => adcdata2367_N(3)(0));
 adcdata2367_3A0 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD42A_P, IB => AD42A_N, O => adcdata2367_P(3)(1), OB => adcdata2367_N(3)(1));
 adcdata2367_3B1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD43B_P, IB => AD43B_N, O => adcdata2367_P(3)(2), OB => adcdata2367_N(3)(2));
 adcdata2367_3A1 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD43A_P, IB => AD43A_N, O => adcdata2367_P(3)(3), OB => adcdata2367_N(3)(3));
 adcdata2367_3B2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD46B_P, IB => AD46B_N, O => adcdata2367_P(3)(4), OB => adcdata2367_N(3)(4));
 adcdata2367_3A2 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD46A_P, IB => AD46A_N, O => adcdata2367_P(3)(5), OB => adcdata2367_N(3)(5));
 adcdata2367_3B3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD47B_P, IB => AD47B_N, O => adcdata2367_P(3)(6), OB => adcdata2367_N(3)(6));
 adcdata2367_3A3 : IBUFDS_DIFF_OUT
-	generic map (IOSTANDARD => "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => AD47A_P, IB => AD47A_N, O => adcdata2367_P(3)(7), OB => adcdata2367_N(3)(7));
 
+
+
 DCOA1_buf : IBUFGDS
-	generic map (DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm), IOSTANDARD	=> "LVDS_25")
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => DCOA1_P, IB => DCOA1_N, O => DCOA1_P_S);
 DCOA1_N_S <= '0';
 DCOA2_buf : IBUFGDS
-	generic map (DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm), IOSTANDARD	=> "LVDS_25")
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => DCOA2_P, IB => DCOA2_N, O => DCOA2_P_S);
 DCOA2_N_S <= '0';
 DCOA3_buf : IBUFGDS
-	generic map (DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm), IOSTANDARD	=> "LVDS_25")
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => DCOA3_P, IB => DCOA3_N, O => DCOA3_P_S);
 DCOA3_N_S <= '0';
 DCOA4_buf : IBUFGDS
-	generic map (DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm), IOSTANDARD	=> "LVDS_25")
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => DCOA4_P, IB => DCOA4_N, O => DCOA4_P_S);
 DCOA4_N_S <= '0';
 
 DCOB1_buf : IBUFGDS
-	generic map (DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm), IOSTANDARD	=> "LVDS_25")
+	generic map (IOSTANDARD => "LVDS",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => DCOB1_P, IB => DCOB1_N, O => DCOB1_P_S);
 DCOB1_N_S <= '0';
 DCOB2_buf : IBUFGDS
-	generic map (DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm), IOSTANDARD	=> "LVDS_25")
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => DCOB2_P, IB => DCOB2_N, O => DCOB2_P_S);
 DCOB2_N_S <= '0';
 DCOB3_buf : IBUFGDS
-	generic map (DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm), IOSTANDARD	=> "LVDS_25")
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => DCOB3_P, IB => DCOB3_N, O => DCOB3_P_S);
 DCOB3_N_S <= '0';
 DCOB4_buf : IBUFGDS
-	generic map (DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm), IOSTANDARD	=> "LVDS_25")
+	generic map (IOSTANDARD => "LVDS_25",  DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I => DCOB4_P, IB => DCOB4_N, O => DCOB4_P_S);
 DCOB4_N_S <= '0';
 
 FRA1_buf : IBUFDS_DIFF_OUT
-	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic	map (IOSTANDARD	=> "LVDS", DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I	=> FRA1_P, IB => FRA1_N, O => FRA1_P_S, OB => FRA1_N_S);
 FRA2_buf : IBUFDS_DIFF_OUT
-	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I	=> FRA2_P, IB => FRA2_N, O => FRA2_P_S, OB => FRA2_N_S);
 FRA3_buf : IBUFDS_DIFF_OUT
-	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I	=> FRA3_P, IB => FRA3_N, O => FRA3_P_S, OB => FRA3_N_S);
 FRA4_buf : IBUFDS_DIFF_OUT
-	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I	=> FRA4_P, IB => FRA4_N, O => FRA4_P_S, OB => FRA4_N_S);
 
-
 FRB1_buf : IBUFDS_DIFF_OUT
-	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic	map (IOSTANDARD	=> "LVDS", DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I	=> FRB1_P, IB => FRB1_N, O => FRB1_P_S, OB => FRB1_N_S);
 FRB2_buf : IBUFDS_DIFF_OUT
-	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I	=> FRB2_P, IB => FRB2_N, O => FRB2_P_S, OB => FRB2_N_S);
 FRB3_buf : IBUFDS_DIFF_OUT
-	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I	=> FRB3_P, IB => FRB3_N, O => FRB3_P_S, OB => FRB3_N_S);
 FRB4_buf : IBUFDS_DIFF_OUT
-	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> TermOrNot(C_OnChipLvdsTerm))
+	generic	map (IOSTANDARD	=> "LVDS_25", DIFF_TERM	=> C_OnChipLvdsTerm)
 	port map (I	=> FRB4_P, IB => FRB4_N, O => FRB4_P_S, OB => FRB4_N_S);
 	
 	
 	AdcToplevel1458_1: AdcToplevel
 		generic map(
-			C_AdcChnls => 4,
-			C_AdcWireInt =>2,     -- 2 = 2-wire, 1 = 1-wire interface
-			C_BufioLoc => "BUFIODQS_X1Y14", 
-			C_BufrLoc => "BUFR_X1Y7", 
-			C_AdcBits => 16,
---			C_StatTaps => 16,
+			C_BufioLoc => "BUFIO_X1Y5",
+			C_BufrLoc => "BUFR_X1Y4", 
+			C_IserdesLoc => "ILOGIC_X1Y74",
+			C_StatTaps => C_StatTaps, -- 8
 			C_AdcUseIdlyCtrl => 1,	     -- 0 = No, 1 = Yes
-			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y3" --IDELAYCTRL_X2Y3
+			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y1" 
 		)
 		port map(
 			DCLK_p => DCOA1_P_S,
@@ -656,32 +665,25 @@ FRB4_buf : IBUFDS_DIFF_OUT
 			DATA_n => adcdata1458_n(0),
 			-- application connections
 			SysRefClk => clock200MHz,
+			clockAsync => clockAsync,
 			AdcIntrfcRst => reset,
 			AdcIntrfcEna => ADCs_enable,
-			AdcReSync => '0',
-			AdcFrmSyncWrn => AdcFrmSyncWrnA_S(0),
-			AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(0),
-			AdcBitClkInvrtd =>  AdcBitClkInvrtdA_S(0),
 			AdcBitClkDone => AdcBitClkDoneA_S(0),
 			AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(0),
 			AdcClkDiv => adcclockA_S(0),
-			adcdataclk => ADC_clk_S,
-			adcdataclknot => ADC_clknot_S,
+			AdcDataClk => ADC_clk_S,
 			AdcDataOut => AdcDataOutA_S(0),
-			ADCs_ready => ADCs_ready_S(0),
-			testOK => open,
-			testword0 => open);
+			ADCs_ready => ADCs_ready_S(0)
+			);
 	
 	AdcToplevel2356_1: AdcToplevel
 		generic map(
-			C_AdcChnls => 4,
-			C_AdcWireInt =>2,     -- 2 = 2-wire, 1 = 1-wire interface
-			C_BufioLoc => "BUFIODQS_X1Y13",
-			C_BufrLoc => "BUFR_X1Y6",
-			C_AdcBits => 16,
---			C_StatTaps => 16,
+			C_BufioLoc => "BUFIO_X1Y6",
+			C_BufrLoc => "BUFR_X1Y7",
+			C_IserdesLoc => "ILOGIC_X1Y76",
+			C_StatTaps => C_StatTaps, -- 8
 			C_AdcUseIdlyCtrl => 0,	     -- 0 = No, 1 = Yes
-			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y3"
+			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X1Y1"
 		)
 		port map(
 			DCLK_p => DCOB1_P_S,
@@ -692,33 +694,26 @@ FRB4_buf : IBUFDS_DIFF_OUT
 			DATA_n => adcdata2367_N(0),
 			-- application connections
 			SysRefClk => clock200MHz,
+			clockAsync => clockAsync,
 			AdcIntrfcRst => reset,
 			AdcIntrfcEna => ADCs_enable,
-			AdcReSync => '0',
-			AdcFrmSyncWrn => AdcFrmSyncWrnB_S(0),
-			AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(0),
-			AdcBitClkInvrtd =>  AdcBitClkInvrtdB_S(0),
 			AdcBitClkDone => AdcBitClkDoneB_S(0),
 			AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(0),
 			AdcClkDiv => adcclockB_S(0),
-			adcdataclk => ADC_clk_S,
-			adcdataclknot => ADC_clknot_S,
+			AdcDataClk => ADC_clk_S,
 			AdcDataOut => AdcDataOutB_S(0),
-			ADCs_ready => ADCs_ready_S(1),
-			testOK => open,
-			testword0 => open);
+			ADCs_ready => ADCs_ready_S(1)
+			);
 
 
 	AdcToplevel1458_2: AdcToplevel
 		generic map(
-			C_AdcChnls => 4,
-			C_AdcWireInt =>2,     -- 2 = 2-wire, 1 = 1-wire interface
-			C_BufioLoc => "BUFIODQS_X0Y13",
-			C_BufrLoc => "BUFR_X0Y6",
-			C_AdcBits => 16,
---			C_StatTaps => 16,
+			C_BufioLoc => "BUFIO_X0Y6",
+			C_BufrLoc => "BUFR_X0Y7", 
+			C_IserdesLoc => "ILOGIC_X0Y76", 
+			C_StatTaps => C_StatTaps, -- 8
 			C_AdcUseIdlyCtrl => 1,	     -- 0 = No, 1 = Yes
-			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3" --IDELAYCTRL_X2Y3
+			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y1"
 		)
 		port map(
 			DCLK_p => DCOA2_P_S,
@@ -729,32 +724,25 @@ FRB4_buf : IBUFDS_DIFF_OUT
 			DATA_n => adcdata1458_n(1),
 			-- application connections
 			SysRefClk => clock200MHz,
+			clockAsync => clockAsync,
 			AdcIntrfcRst => reset,
 			AdcIntrfcEna => ADCs_enable,
-			AdcReSync => '0',
-			AdcFrmSyncWrn => AdcFrmSyncWrnA_S(1),
-			AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(1),
-			AdcBitClkInvrtd => AdcBitClkInvrtdA_S(1),
 			AdcBitClkDone => AdcBitClkDoneA_S(1),
 			AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(1),
 			AdcClkDiv => adcclockA_S(1),
-			adcdataclk => ADC_clk_S,
-			adcdataclknot => ADC_clknot_S,
+			AdcDataClk => ADC_clk_S,
 			AdcDataOut => AdcDataOutA_S(1),
-			ADCs_ready => ADCs_ready_S(2),
-			testOK => open,
-			testword0 => open);
+			ADCs_ready => ADCs_ready_S(2)
+			);
 
 	AdcToplevel2356_2: AdcToplevel
 		generic map(
-			C_AdcChnls => 4,
-			C_AdcWireInt =>2,     -- 2 = 2-wire, 1 = 1-wire interface
-			C_BufioLoc => "BUFIODQS_X0Y14",
-			C_BufrLoc => "BUFR_X0Y7", 
-			C_AdcBits => 16,
---			C_StatTaps => 16,
+			C_BufioLoc => "BUFIO_X0Y5",
+			C_BufrLoc => "BUFR_X0Y4",
+			C_IserdesLoc => "ILOGIC_X0Y74", 
+			C_StatTaps => C_StatTaps, -- 8
 			C_AdcUseIdlyCtrl => 0,	     -- 0 = No, 1 = Yes
-			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3"
+			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y1"
 		)
 		port map(
 			DCLK_p => DCOB2_P_S,
@@ -765,33 +753,26 @@ FRB4_buf : IBUFDS_DIFF_OUT
 			DATA_n => adcdata2367_N(1),
 			-- application connections
 			SysRefClk => clock200MHz,
+			clockAsync => clockAsync,
 			AdcIntrfcRst => reset,
 			AdcIntrfcEna => ADCs_enable,
-			AdcReSync => '0',
-			AdcFrmSyncWrn => AdcFrmSyncWrnB_S(1),
-			AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(1),
-			AdcBitClkInvrtd =>  AdcBitClkInvrtdB_S(1),
 			AdcBitClkDone => AdcBitClkDoneB_S(1),
 			AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(1),
 			AdcClkDiv => adcclockB_S(1),
-			adcdataclk => ADC_clk_S,
-			adcdataclknot => ADC_clknot_S,
+			AdcDataClk => ADC_clk_S,
 			AdcDataOut => AdcDataOutB_S(1),
-			ADCs_ready => ADCs_ready_S(3),
-			testOK => open,
-			testword0 => open);
+			ADCs_ready => ADCs_ready_S(3)
+			);
 			
 
 	AdcToplevel1458_3: AdcToplevel
 		generic map(
-			C_AdcChnls => 4,
-			C_AdcWireInt =>2,     -- 2 = 2-wire, 1 = 1-wire interface
-			C_BufioLoc => "BUFIODQS_X0Y10", 
-			C_BufrLoc => "BUFR_X0Y5", 
-			C_AdcBits => 16,
---			C_StatTaps => 16,
+			C_BufioLoc => "BUFIO_X0Y10",
+			C_BufrLoc => "BUFR_X0Y11", 
+			C_IserdesLoc => "ILOGIC_X0Y126", 
+			C_StatTaps => C_StatTaps, -- 8
 			C_AdcUseIdlyCtrl => 1,	     -- 0 = No, 1 = Yes
-			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2" --IDELAYCTRL_X2Y3
+			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2" 
 		)
 		port map(
 			DCLK_p => DCOA3_P_S,
@@ -802,30 +783,23 @@ FRB4_buf : IBUFDS_DIFF_OUT
 			DATA_n => adcdata1458_n(2),
 			-- application connections
 			SysRefClk => clock200MHz,
+			clockAsync => clockAsync,
 			AdcIntrfcRst => reset,
 			AdcIntrfcEna => ADCs_enable,
-			AdcReSync => '0',
-			AdcFrmSyncWrn => AdcFrmSyncWrnA_S(2),
-			AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(2),
-			AdcBitClkInvrtd =>  AdcBitClkInvrtdA_S(2),
 			AdcBitClkDone => AdcBitClkDoneA_S(2),
 			AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(2),
 			AdcClkDiv => adcclockA_S(2),
-			adcdataclk => ADC_clk_S,
-			adcdataclknot => ADC_clknot_S,
+			AdcDataClk => ADC_clk_S,
 			AdcDataOut => AdcDataOutA_S(2),
-			ADCs_ready => ADCs_ready_S(4),
-			testOK => open,
-			testword0 => open);
+			ADCs_ready => ADCs_ready_S(4)
+			);
 
 	AdcToplevel2356_3: AdcToplevel
 		generic map(
-			C_AdcChnls => 4,
-			C_AdcWireInt =>2,     -- 2 = 2-wire, 1 = 1-wire interface
-			C_BufioLoc => "BUFIODQS_X0Y9",
-			C_BufrLoc => "BUFR_X0Y4",
-			C_AdcBits => 16,
---			C_StatTaps => 16,
+			C_BufioLoc => "BUFIO_X0Y9",
+			C_BufrLoc => "BUFR_X0Y8",
+			C_IserdesLoc => "ILOGIC_X0Y124", 
+			C_StatTaps => C_StatTaps, -- 8
 			C_AdcUseIdlyCtrl => 0,	     -- 0 = No, 1 = Yes
 			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y2"
 		)
@@ -838,33 +812,26 @@ FRB4_buf : IBUFDS_DIFF_OUT
 			DATA_n => adcdata2367_N(2),
 			-- application connections
 			SysRefClk => clock200MHz,
+			clockAsync => clockAsync,
 			AdcIntrfcRst => reset,
 			AdcIntrfcEna => ADCs_enable,
-			AdcReSync => '0',
-			AdcFrmSyncWrn => AdcFrmSyncWrnB_S(2),
-			AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(2),
-			AdcBitClkInvrtd => AdcBitClkInvrtdB_S(2),
 			AdcBitClkDone => AdcBitClkDoneB_S(2),
 			AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(2),
 			AdcClkDiv => adcclockB_S(2),
-			adcdataclk => ADC_clk_S,
-			adcdataclknot => ADC_clknot_S,
+			AdcDataClk => ADC_clk_S,
 			AdcDataOut => AdcDataOutB_S(2),
-			ADCs_ready => ADCs_ready_S(5),
-			testOK => open,
-			testword0 => open);	
+			ADCs_ready => ADCs_ready_S(5)
+			);	
 
 
 	AdcToplevel1458_4: AdcToplevel
 		generic map(
-			C_AdcChnls => 4,
-			C_AdcWireInt =>2,     -- 2 = 2-wire, 1 = 1-wire interface
-			C_BufioLoc => "BUFIODQS_X2Y9",
-			C_BufrLoc => "BUFR_X2Y4",
-			C_AdcBits => 16,
---			C_StatTaps => 16,
+			C_BufioLoc => "BUFIO_X0Y14",
+			C_BufrLoc => "BUFR_X0Y15", 
+			C_IserdesLoc => "ILOGIC_X0Y176", 
+			C_StatTaps => C_StatTaps, -- 8
 			C_AdcUseIdlyCtrl => 1,	     -- 0 = No, 1 = Yes
-			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X2Y2" --IDELAYCTRL_X2Y3
+			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3" 
 		)
 		port map(
 			DCLK_p => DCOA4_P_S,
@@ -875,32 +842,25 @@ FRB4_buf : IBUFDS_DIFF_OUT
 			DATA_n => adcdata1458_n(3),
 			-- application connections
 			SysRefClk => clock200MHz,
+			clockAsync => clockAsync,
 			AdcIntrfcRst => reset,
 			AdcIntrfcEna => ADCs_enable,
-			AdcReSync => '0',
-			AdcFrmSyncWrn => AdcFrmSyncWrnA_S(3),
-			AdcBitClkAlgnWrn => AdcBitClkAlgnWrnA_S(3),
-			AdcBitClkInvrtd =>  AdcBitClkInvrtdA_S(3),
 			AdcBitClkDone => AdcBitClkDoneA_S(3),
 			AdcIdlyCtrlRdy => AdcIdlyCtrlRdyA_S(3),
 			AdcClkDiv => adcclockA_S(3),
-			adcdataclk => ADC_clk_S,
-			adcdataclknot => ADC_clknot_S,
+			AdcDataClk => ADC_clk_S,
 			AdcDataOut => AdcDataOutA_S(3),
-			ADCs_ready => ADCs_ready_S(6),
-			testOK => open,
-			testword0 => open);
+			ADCs_ready => ADCs_ready_S(6)
+			);
 
 	AdcToplevel2356_4: AdcToplevel
 		generic map(
-			C_AdcChnls => 4,
-			C_AdcWireInt =>2,     -- 2 = 2-wire, 1 = 1-wire interface
-			C_BufioLoc => "BUFIODQS_X2Y10",
-			C_BufrLoc => "BUFR_X2Y5",
-			C_AdcBits => 16,
---			C_StatTaps => 16,
+			C_BufioLoc => "BUFIO_X0Y13",
+			C_BufrLoc => "BUFR_X0Y12",
+			C_IserdesLoc => "ILOGIC_X0Y174", 
+			C_StatTaps => C_StatTaps, -- 8
 			C_AdcUseIdlyCtrl => 0,	     -- 0 = No, 1 = Yes
-			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X2Y2"
+			C_AdcIdlyCtrlLoc => "IDELAYCTRL_X0Y3"
 		)
 		port map(
 			DCLK_p => DCOB4_P_S,
@@ -911,51 +871,55 @@ FRB4_buf : IBUFDS_DIFF_OUT
 			DATA_n => adcdata2367_N(3),
 			-- application connections
 			SysRefClk => clock200MHz,
+			clockAsync => clockAsync,
 			AdcIntrfcRst => reset,
 			AdcIntrfcEna => ADCs_enable,
-			AdcReSync => '0',
-			AdcFrmSyncWrn => AdcFrmSyncWrnB_S(3),
-			AdcBitClkAlgnWrn => AdcBitClkAlgnWrnB_S(3),
-			AdcBitClkInvrtd =>  AdcBitClkInvrtdB_S(3),
 			AdcBitClkDone => AdcBitClkDoneB_S(3),
 			AdcIdlyCtrlRdy => AdcIdlyCtrlRdyB_S(3),
 			AdcClkDiv => adcclockB_S(3),
-			adcdataclk => ADC_clk_S,
-			adcdataclknot => ADC_clknot_S,
+			AdcDataClk => ADC_clk_S,
 			AdcDataOut => AdcDataOutB_S(3),
-			ADCs_ready => ADCs_ready_S(7),
-			testOK => open,
-			testword0 => open);		
-
---ADCclkbuf : BUFG port map (
---			O => ADC_clk_S,
---			I => adcclockB_S(0));
-			
-FEE_clockbuf80MHz1: FEE_clockbuf80MHz port map(
-		CLK_IN1 => adcclockA_S(0),
-		CLK_OUT1 => ADC_clk_S,
-		CLK_OUT2 => ADC_clknot_S);
-			
-gen_adcpar1: for chipnr in 0 to 3 generate
+			ADCs_ready => ADCs_ready_S(7)
+			);		
+
+
 
-adcdata0_S((3-chipnr)*8+1) <= AdcDataOutA_S(chipnr)(0*32+7 downto 0*32+0) & AdcDataOutA_S(chipnr)(0*32+15 downto 0*32+10);
-adcdata0_S((3-chipnr)*8+2) <= not (AdcDataOutA_S(chipnr)(1*32+7 downto 1*32+0) & AdcDataOutA_S(chipnr)(1*32+15 downto 1*32+10));
-adcdata0_S((3-chipnr)*8+5) <= AdcDataOutA_S(chipnr)(2*32+7 downto 2*32+0) & AdcDataOutA_S(chipnr)(2*32+15 downto 2*32+10);
-adcdata0_S((3-chipnr)*8+6) <= not (AdcDataOutA_S(chipnr)(3*32+7 downto 3*32+0) & AdcDataOutA_S(chipnr)(3*32+15 downto 3*32+10));
+ADCclkbuf : BUFG port map (
+			O => ADC_clk_S,
+			I => adcclockA_S(0));	
 
-adcdata0_S((3-chipnr)*8+0) <= not (AdcDataOutB_S(chipnr)(0*32+7 downto 0*32+0) & AdcDataOutB_S(chipnr)(0*32+15 downto 0*32+10));
-adcdata0_S((3-chipnr)*8+3) <= AdcDataOutB_S(chipnr)(1*32+7 downto 1*32+0) & AdcDataOutB_S(chipnr)(1*32+15 downto 1*32+10);
-adcdata0_S((3-chipnr)*8+4) <= not (AdcDataOutB_S(chipnr)(2*32+7 downto 2*32+0) & AdcDataOutB_S(chipnr)(2*32+15 downto 2*32+10));
-adcdata0_S((3-chipnr)*8+7) <= AdcDataOutB_S(chipnr)(3*32+7 downto 3*32+0) & AdcDataOutB_S(chipnr)(3*32+15 downto 3*32+10);
+gen_adcpar1: for chipnr in 0 to 3 generate
+
+--process(ADC_clk_S) -- synchronise to 1 clock
+--begin
+--	if (rising_edge(ADC_clk_S)) then 
+adcdata0_S((chipnr)*8+1) <=  (sync_AdcDataOutA_S(chipnr)(0*32+7 downto 0*32+0) & sync_AdcDataOutA_S(chipnr)(0*32+15 downto 0*32+10));
+adcdata0_S((chipnr)*8+2) <=  (sync_AdcDataOutA_S(chipnr)(1*32+7 downto 1*32+0) & sync_AdcDataOutA_S(chipnr)(1*32+15 downto 1*32+10));
+adcdata0_S((chipnr)*8+5) <=  (sync_AdcDataOutA_S(chipnr)(2*32+7 downto 2*32+0) & sync_AdcDataOutA_S(chipnr)(2*32+15 downto 2*32+10));
+adcdata0_S((chipnr)*8+6) <=  (sync_AdcDataOutA_S(chipnr)(3*32+7 downto 3*32+0) & sync_AdcDataOutA_S(chipnr)(3*32+15 downto 3*32+10));
+
+adcdata0_S((chipnr)*8+0) <=  (sync_AdcDataOutB_S(chipnr)(0*32+7 downto 0*32+0) & sync_AdcDataOutB_S(chipnr)(0*32+15 downto 0*32+10));
+adcdata0_S((chipnr)*8+3) <=  (sync_AdcDataOutB_S(chipnr)(1*32+7 downto 1*32+0) & sync_AdcDataOutB_S(chipnr)(1*32+15 downto 1*32+10));
+adcdata0_S((chipnr)*8+4) <=  (sync_AdcDataOutB_S(chipnr)(2*32+7 downto 2*32+0) & sync_AdcDataOutB_S(chipnr)(2*32+15 downto 2*32+10));
+adcdata0_S((chipnr)*8+7) <=  (sync_AdcDataOutB_S(chipnr)(3*32+7 downto 3*32+0) & sync_AdcDataOutB_S(chipnr)(3*32+15 downto 3*32+10));
+--	end if;
+--end process;
 
 end generate;
 
-process(ADC_clk_S) -- synchronise to 1 clock
-begin
-	if (rising_edge(ADC_clk_S)) then 
-		adcdata1_S <= adcdata0_S;
-		adcdata <= adcdata1_S;
-	end if;
-end process;
+adcdata <= adcdata0_S;
+
+sync_AdcDataOutA_S <= AdcDataOutA_S;	
+sync_AdcDataOutB_S <= AdcDataOutB_S;
+
+--0 <- B0 =1
+--1 <- A0 =0
+--2 <- A1 =2
+--3 <- B1 =3
+--4 <- B2 =5
+--5 <- A2 =4
+--6 <- A3 =6
+--7 <- B3 =7
+
 			
 end Behavioral;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_Kintex_ADCboard.ucf b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_Kintex_ADCboard.ucf
new file mode 100644
index 0000000..b51c4dd
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/adc/FEE_Kintex_ADCboard.ucf
@@ -0,0 +1,1153 @@
+NET "AD11A_N" DIFF_TERM = "TRUE";
+NET "AD11A_N" IOSTANDARD = LVDS;
+NET "AD11A_N" LOC = AB7;
+NET "AD11A_P" DIFF_TERM = "TRUE";
+NET "AD11A_P" IOSTANDARD = LVDS;
+NET "AD11A_P" LOC = AB8;
+NET "AD21A_N" DIFF_TERM = "TRUE";
+NET "AD21A_N" IOSTANDARD = LVDS_25;
+NET "AD21A_N" LOC = AB22;
+NET "AD21A_P" DIFF_TERM = "TRUE";
+NET "AD21A_P" IOSTANDARD = LVDS_25;
+NET "AD21A_P" LOC = AA21;
+NET "AD31A_N" DIFF_TERM = "TRUE";
+NET "AD31A_N" IOSTANDARD = LVDS_25;
+NET "AD31A_N" LOC = N17;
+NET "AD31A_P" DIFF_TERM = "TRUE";
+NET "AD31A_P" IOSTANDARD = LVDS_25;
+NET "AD31A_P" LOC = P16;
+NET "AD41A_N" DIFF_TERM = "TRUE";
+NET "AD41A_N" IOSTANDARD = LVDS_25;
+NET "AD41A_N" LOC = A19;
+NET "AD41A_P" DIFF_TERM = "TRUE";
+NET "AD41A_P" IOSTANDARD = LVDS_25;
+NET "AD41A_P" LOC = B18;
+NET "AD11B_N" DIFF_TERM = "TRUE";
+NET "AD11B_N" IOSTANDARD = LVDS;
+NET "AD11B_N" LOC = AB6;
+NET "AD11B_P" DIFF_TERM = "TRUE";
+NET "AD11B_P" IOSTANDARD = LVDS;
+NET "AD11B_P" LOC = AA6;
+NET "AD21B_N" DIFF_TERM = "TRUE";
+NET "AD21B_N" IOSTANDARD = LVDS_25;
+NET "AD21B_N" LOC = Y17;
+NET "AD21B_P" DIFF_TERM = "TRUE";
+NET "AD21B_P" IOSTANDARD = LVDS_25;
+NET "AD21B_P" LOC = W17;
+NET "AD31B_N" DIFF_TERM = "TRUE";
+NET "AD31B_N" IOSTANDARD = LVDS_25;
+NET "AD31B_N" LOC = P22;
+NET "AD31B_P" DIFF_TERM = "TRUE";
+NET "AD31B_P" IOSTANDARD = LVDS_25;
+NET "AD31B_P" LOC = P21;
+NET "AD41B_N" DIFF_TERM = "TRUE";
+NET "AD41B_N" IOSTANDARD = LVDS_25;
+NET "AD41B_N" LOC = C20;
+NET "AD41B_P" DIFF_TERM = "TRUE";
+NET "AD41B_P" IOSTANDARD = LVDS_25;
+NET "AD41B_P" LOC = C19;
+NET "AD12A_N" DIFF_TERM = "TRUE";
+NET "AD12A_N" IOSTANDARD = LVDS;
+NET "AD12A_N" LOC = U6;
+NET "AD12A_P" DIFF_TERM = "TRUE";
+NET "AD12A_P" IOSTANDARD = LVDS;
+NET "AD12A_P" LOC = U7;
+NET "AD22A_N" DIFF_TERM = "TRUE";
+NET "AD22A_N" IOSTANDARD = LVDS_25;
+NET "AD22A_N" LOC = Y16;
+NET "AD22A_P" DIFF_TERM = "TRUE";
+NET "AD22A_P" IOSTANDARD = LVDS_25;
+NET "AD22A_P" LOC = W16;
+NET "AD32A_N" DIFF_TERM = "TRUE";
+NET "AD32A_N" IOSTANDARD = LVDS_25;
+NET "AD32A_N" LOC = R19;
+NET "AD32A_P" DIFF_TERM = "TRUE";
+NET "AD32A_P" IOSTANDARD = LVDS_25;
+NET "AD32A_P" LOC = R18;
+NET "AD42A_N" DIFF_TERM = "TRUE";
+NET "AD42A_N" IOSTANDARD = LVDS_25;
+NET "AD42A_N" LOC = B22;
+NET "AD42A_P" DIFF_TERM = "TRUE";
+NET "AD42A_P" IOSTANDARD = LVDS_25;
+NET "AD42A_P" LOC = C22;
+NET "AD12B_N" DIFF_TERM = "TRUE";
+NET "AD12B_N" IOSTANDARD = LVDS;
+NET "AD12B_N" LOC = AB5;
+NET "AD12B_P" DIFF_TERM = "TRUE";
+NET "AD12B_P" IOSTANDARD = LVDS;
+NET "AD12B_P" LOC = AA5;
+NET "AD22B_N" DIFF_TERM = "TRUE";
+NET "AD22B_N" IOSTANDARD = LVDS_25;
+NET "AD22B_N" LOC = AB17;
+NET "AD22B_P" DIFF_TERM = "TRUE";
+NET "AD22B_P" IOSTANDARD = LVDS_25;
+NET "AD22B_P" LOC = AA16;
+NET "AD32B_N" DIFF_TERM = "TRUE";
+NET "AD32B_N" IOSTANDARD = LVDS_25;
+NET "AD32B_N" LOC = R22;
+NET "AD32B_P" DIFF_TERM = "TRUE";
+NET "AD32B_P" IOSTANDARD = LVDS_25;
+NET "AD32B_P" LOC = R21;
+NET "AD42B_N" DIFF_TERM = "TRUE";
+NET "AD42B_N" IOSTANDARD = LVDS_25;
+NET "AD42B_N" LOC = A21;
+NET "AD42B_P" DIFF_TERM = "TRUE";
+NET "AD42B_P" IOSTANDARD = LVDS_25;
+NET "AD42B_P" LOC = A20;
+NET "AD13A_N" DIFF_TERM = "TRUE";
+NET "AD13A_N" IOSTANDARD = LVDS;
+NET "AD13A_N" LOC = W7;
+NET "AD13A_P" DIFF_TERM = "TRUE";
+NET "AD13A_P" IOSTANDARD = LVDS;
+NET "AD13A_P" LOC = V7;
+NET "AD23A_N" DIFF_TERM = "TRUE";
+NET "AD23A_N" IOSTANDARD = LVDS_25;
+NET "AD23A_N" LOC = AB16;
+NET "AD23A_P" DIFF_TERM = "TRUE";
+NET "AD23A_P" IOSTANDARD = LVDS_25;
+NET "AD23A_P" LOC = AB15;
+NET "AD33A_N" DIFF_TERM = "TRUE";
+NET "AD33A_N" IOSTANDARD = LVDS_25;
+NET "AD33A_N" LOC = P17;
+NET "AD33A_P" DIFF_TERM = "TRUE";
+NET "AD33A_P" IOSTANDARD = LVDS_25;
+NET "AD33A_P" LOC = R17;
+NET "AD43A_N" DIFF_TERM = "TRUE";
+NET "AD43A_N" IOSTANDARD = LVDS_25;
+NET "AD43A_N" LOC = B21;
+NET "AD43A_P" DIFF_TERM = "TRUE";
+NET "AD43A_P" IOSTANDARD = LVDS_25;
+NET "AD43A_P" LOC = B20;
+NET "AD13B_N" DIFF_TERM = "TRUE";
+NET "AD13B_N" IOSTANDARD = LVDS;
+NET "AD13B_N" LOC = AA8;
+NET "AD13B_P" DIFF_TERM = "TRUE";
+NET "AD13B_P" IOSTANDARD = LVDS;
+NET "AD13B_P" LOC = AA9;
+NET "AD23B_N" DIFF_TERM = "TRUE";
+NET "AD23B_N" IOSTANDARD = LVDS_25;
+NET "AD23B_N" LOC = V18;
+NET "AD23B_P" DIFF_TERM = "TRUE";
+NET "AD23B_P" IOSTANDARD = LVDS_25;
+NET "AD23B_P" LOC = U17;
+NET "AD33B_N" DIFF_TERM = "TRUE";
+NET "AD33B_N" IOSTANDARD = LVDS_25;
+NET "AD33B_N" LOC = M22;
+NET "AD33B_P" DIFF_TERM = "TRUE";
+NET "AD33B_P" IOSTANDARD = LVDS_25;
+NET "AD33B_P" LOC = N22;
+NET "AD43B_N" DIFF_TERM = "TRUE";
+NET "AD43B_N" IOSTANDARD = LVDS_25;
+NET "AD43B_N" LOC = A18;
+NET "AD43B_P" DIFF_TERM = "TRUE";
+NET "AD43B_P" IOSTANDARD = LVDS_25;
+NET "AD43B_P" LOC = B17;
+NET "AD14A_N" DIFF_TERM = "TRUE";
+NET "AD14A_N" IOSTANDARD = LVDS;
+NET "AD14A_N" LOC = Y6;
+NET "AD14A_P" DIFF_TERM = "TRUE";
+NET "AD14A_P" IOSTANDARD = LVDS;
+NET "AD14A_P" LOC = W6;
+NET "AD24A_N" DIFF_TERM = "TRUE";
+NET "AD24A_N" IOSTANDARD = LVDS_25;
+NET "AD24A_N" LOC = AA15;
+NET "AD24A_P" DIFF_TERM = "TRUE";
+NET "AD24A_P" IOSTANDARD = LVDS_25;
+NET "AD24A_P" LOC = AA14;
+NET "AD34A_N" DIFF_TERM = "TRUE";
+NET "AD34A_N" IOSTANDARD = LVDS_25;
+NET "AD34A_N" LOC = P20;
+NET "AD34A_P" DIFF_TERM = "TRUE";
+NET "AD34A_P" IOSTANDARD = LVDS_25;
+NET "AD34A_P" LOC = P19;
+NET "AD44A_N" DIFF_TERM = "TRUE";
+NET "AD44A_N" IOSTANDARD = LVDS_25;
+NET "AD44A_N" LOC = D22;
+NET "AD44A_P" DIFF_TERM = "TRUE";
+NET "AD44A_P" IOSTANDARD = LVDS_25;
+NET "AD44A_P" LOC = D21;
+NET "AD14B_N" DIFF_TERM = "TRUE";
+NET "AD14B_N" IOSTANDARD = LVDS;
+NET "AD14B_N" LOC = V8;
+NET "AD14B_P" DIFF_TERM = "TRUE";
+NET "AD14B_P" IOSTANDARD = LVDS;
+NET "AD14B_P" LOC = U8;
+NET "AD24B_N" DIFF_TERM = "TRUE";
+NET "AD24B_N" IOSTANDARD = LVDS_25;
+NET "AD24B_N" LOC = AB21;
+NET "AD24B_P" DIFF_TERM = "TRUE";
+NET "AD24B_P" IOSTANDARD = LVDS_25;
+NET "AD24B_P" LOC = AA20;
+NET "AD34B_N" DIFF_TERM = "TRUE";
+NET "AD34B_N" IOSTANDARD = LVDS_25;
+NET "AD34B_N" LOC = K22;
+NET "AD34B_P" DIFF_TERM = "TRUE";
+NET "AD34B_P" IOSTANDARD = LVDS_25;
+NET "AD34B_P" LOC = K21;
+NET "AD44B_N" DIFF_TERM = "TRUE";
+NET "AD44B_N" IOSTANDARD = LVDS_25;
+NET "AD44B_N" LOC = D20;
+NET "AD44B_P" DIFF_TERM = "TRUE";
+NET "AD44B_P" IOSTANDARD = LVDS_25;
+NET "AD44B_P" LOC = D19;
+NET "AD15A_N" DIFF_TERM = "TRUE";
+NET "AD15A_N" IOSTANDARD = LVDS;
+NET "AD15A_N" LOC = W10;
+NET "AD15A_P" DIFF_TERM = "TRUE";
+NET "AD15A_P" IOSTANDARD = LVDS;
+NET "AD15A_P" LOC = V10;
+NET "AD25A_N" DIFF_TERM = "TRUE";
+NET "AD25A_N" IOSTANDARD = LVDS_25;
+NET "AD25A_N" LOC = W22;
+NET "AD25A_P" DIFF_TERM = "TRUE";
+NET "AD25A_P" IOSTANDARD = LVDS_25;
+NET "AD25A_P" LOC = W21;
+NET "AD35A_N" DIFF_TERM = "TRUE";
+NET "AD35A_N" IOSTANDARD = LVDS_25;
+NET "AD35A_N" LOC = L21;
+NET "AD35A_P" DIFF_TERM = "TRUE";
+NET "AD35A_P" IOSTANDARD = LVDS_25;
+NET "AD35A_P" LOC = M20;
+NET "AD45A_N" DIFF_TERM = "TRUE";
+NET "AD45A_N" IOSTANDARD = LVDS_25;
+NET "AD45A_N" LOC = A15;
+NET "AD45A_P" DIFF_TERM = "TRUE";
+NET "AD45A_P" IOSTANDARD = LVDS_25;
+NET "AD45A_P" LOC = B15;
+NET "AD15B_N" DIFF_TERM = "TRUE";
+NET "AD15B_N" IOSTANDARD = LVDS;
+NET "AD15B_N" LOC = Y11;
+NET "AD15B_P" DIFF_TERM = "TRUE";
+NET "AD15B_P" IOSTANDARD = LVDS;
+NET "AD15B_P" LOC = W11;
+NET "AD25B_N" DIFF_TERM = "TRUE";
+NET "AD25B_N" IOSTANDARD = LVDS_25;
+NET "AD25B_N" LOC = W20;
+NET "AD25B_P" DIFF_TERM = "TRUE";
+NET "AD25B_P" IOSTANDARD = LVDS_25;
+NET "AD25B_P" LOC = V20;
+NET "AD35B_N" DIFF_TERM = "TRUE";
+NET "AD35B_N" IOSTANDARD = LVDS_25;
+NET "AD35B_N" LOC = M18;
+NET "AD35B_P" DIFF_TERM = "TRUE";
+NET "AD35B_P" IOSTANDARD = LVDS_25;
+NET "AD35B_P" LOC = M17;
+NET "AD45B_N" DIFF_TERM = "TRUE";
+NET "AD45B_N" IOSTANDARD = LVDS_25;
+NET "AD45B_N" LOC = C15;
+NET "AD45B_P" DIFF_TERM = "TRUE";
+NET "AD45B_P" IOSTANDARD = LVDS_25;
+NET "AD45B_P" LOC = C14;
+NET "AD16A_N" DIFF_TERM = "TRUE";
+NET "AD16A_N" IOSTANDARD = LVDS;
+NET "AD16A_N" LOC = AB11;
+NET "AD16A_P" DIFF_TERM = "TRUE";
+NET "AD16A_P" IOSTANDARD = LVDS;
+NET "AD16A_P" LOC = AA11;
+NET "AD26A_N" DIFF_TERM = "TRUE";
+NET "AD26A_N" IOSTANDARD = LVDS_25;
+NET "AD26A_N" LOC = Y22;
+NET "AD26A_P" DIFF_TERM = "TRUE";
+NET "AD26A_P" IOSTANDARD = LVDS_25;
+NET "AD26A_P" LOC = Y21;
+NET "AD36A_N" DIFF_TERM = "TRUE";
+NET "AD36A_N" IOSTANDARD = LVDS_25;
+NET "AD36A_N" LOC = G22;
+NET "AD36A_P" DIFF_TERM = "TRUE";
+NET "AD36A_P" IOSTANDARD = LVDS_25;
+NET "AD36A_P" LOC = H22;
+NET "AD46A_N" DIFF_TERM = "TRUE";
+NET "AD46A_N" IOSTANDARD = LVDS_25;
+NET "AD46A_N" LOC = D16;
+NET "AD46A_P" DIFF_TERM = "TRUE";
+NET "AD46A_P" IOSTANDARD = LVDS_25;
+NET "AD46A_P" LOC = D15;
+NET "AD16B_N" DIFF_TERM = "TRUE";
+NET "AD16B_N" IOSTANDARD = LVDS;
+NET "AD16B_N" LOC = AB12;
+NET "AD16B_P" DIFF_TERM = "TRUE";
+NET "AD16B_P" IOSTANDARD = LVDS;
+NET "AD16B_P" LOC = AB13;
+NET "AD26B_N" DIFF_TERM = "TRUE";
+NET "AD26B_N" IOSTANDARD = LVDS_25;
+NET "AD26B_N" LOC = V17;
+NET "AD26B_P" DIFF_TERM = "TRUE";
+NET "AD26B_P" IOSTANDARD = LVDS_25;
+NET "AD26B_P" LOC = U16;
+NET "AD36B_N" DIFF_TERM = "TRUE";
+NET "AD36B_N" IOSTANDARD = LVDS_25;
+NET "AD36B_N" LOC = H20;
+NET "AD36B_P" DIFF_TERM = "TRUE";
+NET "AD36B_P" IOSTANDARD = LVDS_25;
+NET "AD36B_P" LOC = J20;
+NET "AD46B_N" DIFF_TERM = "TRUE";
+NET "AD46B_N" IOSTANDARD = LVDS_25;
+NET "AD46B_N" LOC = F16;
+NET "AD46B_P" DIFF_TERM = "TRUE";
+NET "AD46B_P" IOSTANDARD = LVDS_25;
+NET "AD46B_P" LOC = F15;
+NET "AD17A_N" DIFF_TERM = "TRUE";
+NET "AD17A_N" IOSTANDARD = LVDS;
+NET "AD17A_N" LOC = V12;
+NET "AD17A_P" DIFF_TERM = "TRUE";
+NET "AD17A_P" IOSTANDARD = LVDS;
+NET "AD17A_P" LOC = V13;
+NET "AD27A_N" DIFF_TERM = "TRUE";
+NET "AD27A_N" IOSTANDARD = LVDS_25;
+NET "AD27A_N" LOC = U21;
+NET "AD27A_P" DIFF_TERM = "TRUE";
+NET "AD27A_P" IOSTANDARD = LVDS_25;
+NET "AD27A_P" LOC = T21;
+NET "AD37A_N" DIFF_TERM = "TRUE";
+NET "AD37A_N" IOSTANDARD = LVDS_25;
+NET "AD37A_N" LOC = F20;
+NET "AD37A_P" DIFF_TERM = "TRUE";
+NET "AD37A_P" IOSTANDARD = LVDS_25;
+NET "AD37A_P" LOC = G20;
+NET "AD47A_N" DIFF_TERM = "TRUE";
+NET "AD47A_N" IOSTANDARD = LVDS_25;
+NET "AD47A_N" LOC = B13;
+NET "AD47A_P" DIFF_TERM = "TRUE";
+NET "AD47A_P" IOSTANDARD = LVDS_25;
+NET "AD47A_P" LOC = C13;
+NET "AD17B_N" DIFF_TERM = "TRUE";
+NET "AD17B_N" IOSTANDARD = LVDS;
+NET "AD17B_N" LOC = U13;
+NET "AD17B_P" DIFF_TERM = "TRUE";
+NET "AD17B_P" IOSTANDARD = LVDS;
+NET "AD17B_P" LOC = T13;
+NET "AD27B_N" DIFF_TERM = "TRUE";
+NET "AD27B_N" IOSTANDARD = LVDS_25;
+NET "AD27B_N" LOC = U18;
+NET "AD27B_P" DIFF_TERM = "TRUE";
+NET "AD27B_P" IOSTANDARD = LVDS_25;
+NET "AD27B_P" LOC = T18;
+NET "AD37B_N" DIFF_TERM = "TRUE";
+NET "AD37B_N" IOSTANDARD = LVDS_25;
+NET "AD37B_N" LOC = F21;
+NET "AD37B_P" DIFF_TERM = "TRUE";
+NET "AD37B_P" IOSTANDARD = LVDS_25;
+NET "AD37B_P" LOC = G21;
+NET "AD47B_N" DIFF_TERM = "TRUE";
+NET "AD47B_N" IOSTANDARD = LVDS_25;
+NET "AD47B_N" LOC = B12;
+NET "AD47B_P" DIFF_TERM = "TRUE";
+NET "AD47B_P" IOSTANDARD = LVDS_25;
+NET "AD47B_P" LOC = C12;
+NET "AD18A_N" DIFF_TERM = "TRUE";
+NET "AD18A_N" IOSTANDARD = LVDS;
+NET "AD18A_N" LOC = Y12;
+NET "AD18A_P" DIFF_TERM = "TRUE";
+NET "AD18A_P" IOSTANDARD = LVDS;
+NET "AD18A_P" LOC = W12;
+NET "AD28A_N" DIFF_TERM = "TRUE";
+NET "AD28A_N" IOSTANDARD = LVDS_25;
+NET "AD28A_N" LOC = V22;
+NET "AD28A_P" DIFF_TERM = "TRUE";
+NET "AD28A_P" IOSTANDARD = LVDS_25;
+NET "AD28A_P" LOC = U22;
+NET "AD38A_N" DIFF_TERM = "TRUE";
+NET "AD38A_N" IOSTANDARD = LVDS_25;
+NET "AD38A_N" LOC = K19;
+NET "AD38A_P" DIFF_TERM = "TRUE";
+NET "AD38A_P" IOSTANDARD = LVDS_25;
+NET "AD38A_P" LOC = L18;
+NET "AD48A_N" DIFF_TERM = "TRUE";
+NET "AD48A_N" IOSTANDARD = LVDS_25;
+NET "AD48A_N" LOC = A14;
+NET "AD48A_P" DIFF_TERM = "TRUE";
+NET "AD48A_P" IOSTANDARD = LVDS_25;
+NET "AD48A_P" LOC = A13;
+NET "AD18B_N" DIFF_TERM = "TRUE";
+NET "AD18B_N" IOSTANDARD = LVDS;
+NET "AD18B_N" LOC = AA13;
+NET "AD18B_P" DIFF_TERM = "TRUE";
+NET "AD18B_P" IOSTANDARD = LVDS;
+NET "AD18B_P" LOC = Y13;
+NET "AD28B_N" DIFF_TERM = "TRUE";
+NET "AD28B_N" IOSTANDARD = LVDS_25;
+NET "AD28B_N" LOC = U20;
+NET "AD28B_P" DIFF_TERM = "TRUE";
+NET "AD28B_P" IOSTANDARD = LVDS_25;
+NET "AD28B_P" LOC = T20;
+NET "AD38B_N" DIFF_TERM = "TRUE";
+NET "AD38B_N" IOSTANDARD = LVDS_25;
+NET "AD38B_N" LOC = E22;
+NET "AD38B_P" DIFF_TERM = "TRUE";
+NET "AD38B_P" IOSTANDARD = LVDS_25;
+NET "AD38B_P" LOC = E21;
+NET "AD48B_N" DIFF_TERM = "TRUE";
+NET "AD48B_N" IOSTANDARD = LVDS_25;
+NET "AD48B_N" LOC = D14;
+NET "AD48B_P" DIFF_TERM = "TRUE";
+NET "AD48B_P" IOSTANDARD = LVDS_25;
+NET "AD48B_P" LOC = E14;
+NET "DCOA1_N" DIFF_TERM = "TRUE";
+NET "DCOA1_N" IOSTANDARD = LVDS;
+NET "DCOA1_N" LOC = Y9;
+NET "DCOA1_P" DIFF_TERM = "TRUE";
+NET "DCOA1_P" IOSTANDARD = LVDS;
+NET "DCOA1_P" LOC = W9;
+NET "DCOB1_N" DIFF_TERM = "TRUE";
+NET "DCOB1_N" IOSTANDARD = LVDS;
+NET "DCOB1_N" LOC = Y7;
+NET "DCOB1_P" DIFF_TERM = "TRUE";
+NET "DCOB1_P" IOSTANDARD = LVDS;
+NET "DCOB1_P" LOC = Y8;
+NET "FRA1_N" DIFF_TERM = "TRUE";
+NET "FRA1_N" IOSTANDARD = LVDS;
+NET "FRA1_N" LOC = V9;
+NET "FRA1_P" DIFF_TERM = "TRUE";
+NET "FRA1_P" IOSTANDARD = LVDS;
+NET "FRA1_P" LOC = U10;
+NET "FRB1_N" DIFF_TERM = "TRUE";
+NET "FRB1_N" IOSTANDARD = LVDS;
+NET "FRB1_N" LOC = AB10;
+NET "FRB1_P" DIFF_TERM = "TRUE";
+NET "FRB1_P" IOSTANDARD = LVDS;
+NET "FRB1_P" LOC = AA10;
+NET "DCOA2_N" DIFF_TERM = "TRUE";
+NET "DCOA2_N" IOSTANDARD = LVDS_25;
+NET "DCOA2_N" LOC = W19;
+NET "DCOA2_P" DIFF_TERM = "TRUE";
+NET "DCOA2_P" IOSTANDARD = LVDS_25;
+NET "DCOA2_P" LOC = V19;
+NET "DCOB2_N" DIFF_TERM = "TRUE";
+NET "DCOB2_N" IOSTANDARD = LVDS_25;
+NET "DCOB2_N" LOC = Y19;
+NET "DCOB2_P" DIFF_TERM = "TRUE";
+NET "DCOB2_P" IOSTANDARD = LVDS_25;
+NET "DCOB2_P" LOC = Y18;
+NET "FRA2_N" DIFF_TERM = "TRUE";
+NET "FRA2_N" IOSTANDARD = LVDS_25;
+NET "FRA2_N" LOC = AB18;
+NET "FRA2_P" DIFF_TERM = "TRUE";
+NET "FRA2_P" IOSTANDARD = LVDS_25;
+NET "FRA2_P" LOC = AA18;
+NET "FRB2_N" DIFF_TERM = "TRUE";
+NET "FRB2_N" IOSTANDARD = LVDS_25;
+NET "FRB2_N" LOC = AB20;
+NET "FRB2_P" DIFF_TERM = "TRUE";
+NET "FRB2_P" IOSTANDARD = LVDS_25;
+NET "FRB2_P" LOC = AA19;
+NET "DCOA3_N" DIFF_TERM = "TRUE";
+NET "DCOA3_N" IOSTANDARD = LVDS_25;
+NET "DCOA3_N" LOC = L20;
+NET "DCOA3_P" DIFF_TERM = "TRUE";
+NET "DCOA3_P" IOSTANDARD = LVDS_25;
+NET "DCOA3_P" LOC = L19;
+NET "DCOB3_N" DIFF_TERM = "TRUE";
+NET "DCOB3_N" IOSTANDARD = LVDS_25;
+NET "DCOB3_N" LOC = N19;
+NET "DCOB3_P" DIFF_TERM = "TRUE";
+NET "DCOB3_P" IOSTANDARD = LVDS_25;
+NET "DCOB3_P" LOC = N18;
+NET "FRA3_N" DIFF_TERM = "TRUE";
+NET "FRA3_N" IOSTANDARD = LVDS_25;
+NET "FRA3_N" LOC = M21;
+NET "FRA3_P" DIFF_TERM = "TRUE";
+NET "FRA3_P" IOSTANDARD = LVDS_25;
+NET "FRA3_P" LOC = N20;
+NET "FRB3_N" DIFF_TERM = "TRUE";
+NET "FRB3_N" IOSTANDARD = LVDS_25;
+NET "FRB3_N" LOC = J22;
+NET "FRB3_P" DIFF_TERM = "TRUE";
+NET "FRB3_P" IOSTANDARD = LVDS_25;
+NET "FRB3_P" LOC = J21;
+NET "DCOA4_N" DIFF_TERM = "TRUE";
+NET "DCOA4_N" IOSTANDARD = LVDS_25;
+NET "DCOA4_N" LOC = C18;
+NET "DCOA4_P" DIFF_TERM = "TRUE";
+NET "DCOA4_P" IOSTANDARD = LVDS_25;
+NET "DCOA4_P" LOC = C17;
+NET "DCOB4_N" DIFF_TERM = "TRUE";
+NET "DCOB4_N" IOSTANDARD = LVDS_25;
+NET "DCOB4_N" LOC = E18;
+NET "DCOB4_P" DIFF_TERM = "TRUE";
+NET "DCOB4_P" IOSTANDARD = LVDS_25;
+NET "DCOB4_P" LOC = E17;
+NET "FRA4_N" DIFF_TERM = "TRUE";
+NET "FRA4_N" IOSTANDARD = LVDS_25;
+NET "FRA4_N" LOC = A16;
+NET "FRA4_P" DIFF_TERM = "TRUE";
+NET "FRA4_P" IOSTANDARD = LVDS_25;
+NET "FRA4_P" LOC = B16;
+NET "FRB4_N" DIFF_TERM = "TRUE";
+NET "FRB4_N" IOSTANDARD = LVDS_25;
+NET "FRB4_N" LOC = D17;
+NET "FRB4_P" DIFF_TERM = "TRUE";
+NET "FRB4_P" IOSTANDARD = LVDS_25;
+NET "FRB4_P" LOC = E16;
+
+NET "CSA[1]" LOC = W15;
+NET "CSA[1]" IOSTANDARD = LVCMOS25;
+NET "CSB[1]" LOC = V15;
+NET "CSB[1]" IOSTANDARD = LVCMOS25;
+NET "SCK" LOC = U12;
+NET "SCK" IOSTANDARD = LVCMOS18;
+NET "SDI" LOC = U11;
+NET "SDI" IOSTANDARD = LVCMOS18;
+NET "SDOA[1]" LOC = W14;
+NET "SDOA[1]" IOSTANDARD = LVCMOS25;
+NET "SDOB[1]" LOC = Y14;
+NET "SDOB[1]" IOSTANDARD = LVCMOS25;
+NET "CSA[2]" LOC = T16;
+NET "CSA[2]" IOSTANDARD = LVCMOS25;
+NET "CSB[2]" LOC = R16;
+NET "CSB[2]" IOSTANDARD = LVCMOS25;
+NET "SDOA[2]" LOC = T15;
+NET "SDOA[2]" IOSTANDARD = LVCMOS25;
+NET "SDOB[2]" LOC = U15;
+NET "SDOB[2]" IOSTANDARD = LVCMOS25;
+NET "CSA[3]" LOC = H17;
+NET "CSA[3]" IOSTANDARD = LVCMOS25;
+NET "CSB[3]" LOC = G17;
+NET "CSB[3]" IOSTANDARD = LVCMOS25;
+NET "SDOA[3]" LOC = J16;
+NET "SDOA[3]" IOSTANDARD = LVCMOS25;
+NET "SDOB[3]" LOC = J17;
+NET "SDOB[3]" IOSTANDARD = LVCMOS25;
+NET "CSA[4]" LOC = F18;
+NET "CSA[4]" IOSTANDARD = LVCMOS25;
+NET "CSB[4]" LOC = E19;
+NET "CSB[4]" IOSTANDARD = LVCMOS25;
+NET "SDOA[4]" LOC = G15;
+NET "SDOA[4]" IOSTANDARD = LVCMOS25;
+NET "SDOB[4]" LOC = G16;
+NET "SDOB[4]" IOSTANDARD = LVCMOS25;
+
+NET "GCLK_N" DIFF_TERM = "TRUE";
+NET "GCLK_N" IOSTANDARD = LVDS;
+NET "GCLK_N" LOC = T3;
+NET "GCLK_P" DIFF_TERM = "TRUE";
+NET "GCLK_P" IOSTANDARD = LVDS;
+NET "GCLK_P" LOC = R3;
+#NET "GCLK_P" IOSTANDARD = LVCMOS18;
+#NET "GCLK_N" IOSTANDARD = LVCMOS18;
+#NET "GCLK_N" CLOCK_DEDICATED_ROUTE = FALSE;
+
+
+NET "GEO" LOC = K17;
+NET "GEO" IOSTANDARD = LVCMOS25;
+NET "GEO" SLEW = SLOW;
+NET "GEO" PULLUP;
+NET "GEO" TIG;
+
+#Bank 16 = 2.5V
+NET "SYS_CLK" LOC = H12;
+NET "SYS_CLK" IOSTANDARD = LVCMOS25;
+
+NET "INTCOMC1_N" LOC = D11;
+NET "INTCOMC1_P" LOC = E11;
+NET "INTCOMC2_N" LOC = G10;
+NET "INTCOMC2_P" LOC = G11;
+NET "INTCOM0_N" LOC = E9;
+NET "INTCOM0_P" LOC = F9;
+NET "INTCOM1_N" LOC = H8;
+NET "INTCOM1_P" LOC = H9;
+NET "INTCOM2_N" LOC = F8;
+NET "INTCOM2_P" LOC = G8;
+NET "INTCOM3_N" LOC = C9;
+NET "INTCOM3_P" LOC = D9;
+NET "INTCOM4_N" LOC = B10;
+NET "INTCOM4_P" LOC = B11;
+NET "INTCOM5_N" LOC = A8;
+NET "INTCOM5_P" LOC = A9;
+NET "INTCOM6_N" LOC = B8;
+NET "INTCOM6_P" LOC = C8;
+NET "INTCOM7_N" LOC = A10;
+NET "INTCOM7_P" LOC = A11;
+
+NET "INTCOMC1_N" IOSTANDARD = LVCMOS25;
+NET "INTCOMC1_P" IOSTANDARD = LVCMOS25;
+NET "INTCOMC2_N" IOSTANDARD = LVCMOS25;
+NET "INTCOMC2_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM0_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM0_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM1_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM1_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM2_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM2_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM3_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM3_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM4_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM4_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM5_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM5_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM6_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM6_P" IOSTANDARD = LVCMOS25;
+NET "INTCOM7_N" IOSTANDARD = LVCMOS25;
+NET "INTCOM7_P" IOSTANDARD = LVCMOS25;
+
+
+NET "INTCOMC1_P" SLEW = FAST;
+NET "INTCOMC1_N" SLEW = FAST;
+NET "INTCOMC2_P" SLEW = FAST;
+NET "INTCOMC2_N" SLEW = FAST;
+NET "INTCOM0_P" SLEW = FAST;
+NET "INTCOM0_N" SLEW = FAST;
+NET "INTCOM1_P" SLEW = FAST;
+NET "INTCOM1_N" SLEW = FAST;
+NET "INTCOM2_P" SLEW = FAST;
+NET "INTCOM2_N" SLEW = FAST;
+NET "INTCOM3_P" SLEW = FAST;
+NET "INTCOM3_N" SLEW = FAST;
+NET "INTCOM4_P" SLEW = FAST;
+NET "INTCOM4_N" SLEW = FAST;
+NET "INTCOM5_P" SLEW = FAST;
+NET "INTCOM5_N" SLEW = FAST;
+NET "INTCOM6_P" SLEW = FAST;
+NET "INTCOM6_N" SLEW = FAST;
+NET "INTCOM7_P" SLEW = FAST;
+NET "INTCOM7_N" SLEW = FAST;
+
+
+NET "INTCOMC1_P" DRIVE = 4;
+NET "INTCOMC1_N" DRIVE = 4;
+NET "INTCOMC2_P" DRIVE = 4;
+NET "INTCOMC2_N" DRIVE = 4;
+NET "INTCOM0_P" DRIVE = 4;
+NET "INTCOM0_N" DRIVE = 4;
+NET "INTCOM1_P" DRIVE = 4;
+NET "INTCOM1_N" DRIVE = 4;
+NET "INTCOM2_P" DRIVE = 4;
+NET "INTCOM2_N" DRIVE = 4;
+NET "INTCOM3_P" DRIVE = 4;
+NET "INTCOM3_N" DRIVE = 4;
+NET "INTCOM4_P" DRIVE = 4;
+NET "INTCOM4_N" DRIVE = 4;
+NET "INTCOM5_P" DRIVE = 4;
+NET "INTCOM5_N" DRIVE = 4;
+NET "INTCOM6_P" DRIVE = 4;
+NET "INTCOM6_N" DRIVE = 4;
+NET "INTCOM7_P" DRIVE = 4;
+NET "INTCOM7_N" DRIVE = 4;
+
+
+
+NET "RCV_CLK_N" LOC = F10;
+NET "RCV_CLK_N" DIFF_TERM = "TRUE";
+NET "RCV_CLK_N" IOSTANDARD = LVDS_25;
+NET "RCV_CLK_P" LOC = F11;
+NET "RCV_CLK_P" DIFF_TERM = "TRUE";
+NET "RCV_CLK_P" IOSTANDARD = LVDS_25;
+
+NET "S_CTRL" LOC = E12;
+NET "S_CTRL" IOSTANDARD = LVCMOS25;
+NET "T_CTRL" LOC = E13;
+NET "T_CTRL" IOSTANDARD = LVCMOS25;
+
+#bank 34: 3.3V
+NET "SYNC" LOC = W5;
+NET "SYNC" IOSTANDARD = LVCMOS18;
+NET "CLKu" LOC = AA4;
+NET "CLKu" IOSTANDARD = LVCMOS18;
+NET "DATAu" LOC = AA3;
+NET "DATAu" IOSTANDARD = LVCMOS18;
+NET "LEu" LOC = Y4;
+NET "LEu" IOSTANDARD = LVCMOS18;
+NET "RDu" LOC = AB3;
+NET "RDu" IOSTANDARD = LVCMOS18;
+NET "RDu" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "ST_CLK_N" LOC = U3;
+#NET "ST_CLK_N" DIFF_TERM = "TRUE";
+#NET "ST_CLK_N" IOSTANDARD = LVDS;
+NET "ST_CLK_N" IOSTANDARD = LVCMOS18;
+
+NET "ST_CLK_P" LOC = T4;
+#NET "ST_CLK_P" DIFF_TERM = "TRUE";
+#NET "ST_CLK_P" IOSTANDARD = LVDS;
+NET "ST_CLK_P" IOSTANDARD = LVCMOS18;
+#NET "ST_CLK_N" CLOCK_DEDICATED_ROUTE = FALSE;
+
+NET "MGTREFCLK_N" LOC = D5;
+NET "MGTREFCLK_N" DIFF_TERM = "TRUE";
+NET "MGTREFCLK_N" IOSTANDARD = LVDS;
+NET "MGTREFCLK_P" LOC = D6;
+NET "MGTREFCLK_P" DIFF_TERM = "TRUE";
+NET "MGTREFCLK_P" IOSTANDARD = LVDS;
+NET "RX_N" LOC = G3;
+NET "RX_N" DIFF_TERM = "TRUE";
+NET "RX_N" IOSTANDARD = LVDS;
+NET "RX_P" LOC = G4;
+NET "RX_P" DIFF_TERM = "TRUE";
+NET "RX_P" IOSTANDARD = LVDS;
+NET "TX_N" LOC = F1;
+NET "TX_N" DIFF_TERM = "TRUE";
+NET "TX_N" IOSTANDARD = LVDS;
+NET "TX_P" LOC = F2;
+NET "TX_P" DIFF_TERM = "TRUE";
+NET "TX_P" IOSTANDARD = LVDS;
+NET "LOS" LOC = K1;
+NET "LOS" IOSTANDARD = LVCMOS18;
+NET "TX_DIS" LOC = L1;
+NET "TX_DIS" IOSTANDARD = LVCMOS18;
+NET "MOD_DEF[0]" LOC = M2;
+NET "MOD_DEF[0]" IOSTANDARD = LVCMOS18;
+NET "MOD_DEF[1]" LOC = M1;
+NET "MOD_DEF[1]" IOSTANDARD = LVCMOS18;
+NET "MOD_DEF[2]" LOC = K3;
+NET "MOD_DEF[2]" IOSTANDARD = LVCMOS18;
+
+NET "MON1_N" LOC = Y1;
+NET "MON1_N" IOSTANDARD = LVCMOS18;
+NET "MON1_P" LOC = W1;
+NET "MON1_P" IOSTANDARD = LVCMOS18;
+NET "MON2_N" LOC = Y2;
+NET "MON2_N" IOSTANDARD = LVCMOS18;
+NET "MON2_P" LOC = Y3;
+NET "MON2_P" IOSTANDARD = LVCMOS18;
+
+NET "TEMP_OUT" LOC = T10;
+NET "TEMP_OUT" IOSTANDARD = LVCMOS18;
+NET "TEMP_IN" LOC = T11;
+NET "TEMP_IN" IOSTANDARD = LVCMOS18;
+
+#NET "GT_A2B_0_N" LOC = D1;
+#NET "GT_A2B_0_P" LOC = D2;
+#NET "GT_A2B_1_N" LOC = B1;
+#NET "GT_A2B_1_P" LOC = B2;
+#NET "GT_B2A_0_N" LOC = E3;
+#NET "GT_B2A_0_P" LOC = E4;
+#NET "GT_B2A_1_N" LOC = C3;
+#NET "GT_B2A_1_P" LOC = C4;
+#NET "DONE_P1" LOC = P6;
+#NET "CF_D0_I1" LOC = H18;
+#NET "CF_D1_I1" LOC = H19;
+#NET "CF_D2_I1" LOC = G18;
+#NET "CF_D3_I1" LOC = F19;
+#NET "CF_EMCL_I1" LOC = H12;
+#NET "CF_EMCL_I1" LOC = J19;
+#NET "CF_FCS_I1" LOC = L16;
+#NET "CF_PUDC_I1" LOC = K18;
+#NET "CCLK1_P1" LOC = G7;
+#NET "JTAG_IN1_TCK" LOC = K7;
+#NET "JTAG_IN1_TDI" LOC = K6;
+#NET "JTAG_IN1_TDO" LOC = J6;
+#NET "JTAG_IN1_TMS" LOC = L6;
+NET "JTAG_OUT1_TCK_F" LOC = G13;
+NET "JTAG_OUT1_TCK_F" IOSTANDARD = LVCMOS25;
+NET "JTAG_OUT1_TDI_F" LOC = H14;
+NET "JTAG_OUT1_TDI_F" IOSTANDARD = LVCMOS25;
+NET "JTAG_OUT1_TDO_F" LOC = H13;
+NET "JTAG_OUT1_TDO_F" IOSTANDARD = LVCMOS25;
+NET "JTAG_OUT1_TMS_F" LOC = F13;
+NET "JTAG_OUT1_TMS_F" IOSTANDARD = LVCMOS25;
+
+
+##########################################################################################
+# timing clock inputs:
+NET "SYS_CLK" TNM_NET = "SYS_CLK";
+TIMESPEC TS_SYS_CLK = PERIOD "SYS_CLK" 10 ns HIGH 50 %;
+
+NET "ST_CLK_P" TNM_NET = "ST_CLK_P";
+TIMESPEC TS_ST_CLK_P = PERIOD "ST_CLK_P" 6.43 ns HIGH 50 %;
+NET "ST_CLK_N" TNM_NET = "ST_CLK_N";
+TIMESPEC TS_ST_CLK_N = PERIOD "ST_CLK_N" 6.43 ns HIGH 50 %;
+
+NET "GCLK_P" TNM_NET = "GCLK_P";
+TIMESPEC TS_GCLK_P = PERIOD "GCLK_P" 12.5 ns HIGH 50 %;
+NET "GCLK_N" TNM_NET = "GCLK_N";
+TIMESPEC TS_GCLK_N = PERIOD "GCLK_N" 12.5 ns HIGH 50 %;
+
+##########################################################################################
+# derived clocks
+NET "async_clock_S" TNM_NET = "async_clock_S";
+TIMESPEC TS_async_clock_S = PERIOD "async_clock_S" 15.8333 ns HIGH 50 %;
+
+NET "clock100MHz_S" TNM_NET = "clock100MHz_S";
+TIMESPEC TS_clock100MHz_S = PERIOD "clock100MHz_S" 10 ns HIGH 50 %;
+
+NET "clock_S" TNM_NET = "clock_S";
+TIMESPEC TS_clock_S = PERIOD "clock_S" 12.5 ns HIGH 50 %;
+
+#NET "ST_CLK_S" TNM_NET = "ST_CLK_S";
+#TIMESPEC TS_ST_CLK_S = PERIOD "ST_CLK_S" 6.43 ns HIGH 50 %;
+
+NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S";
+TIMESPEC TS_rxSodaClk_S = PERIOD "rxSodaClk_S" 5 ns HIGH 50 %;
+
+##########################################################################################
+# between clocks 
+TIMESPEC TS_asyn_to_clock = FROM "async_clock_S" TO "clock_S" TIG ;
+TIMESPEC TS_clock_to_async = FROM "clock_S" TO "async_clock_S" TIG ;
+
+#TIMESPEC TS_G_to_ST = FROM "GCLK_P" TO "ST_CLK_S" TIG;
+#TIMESPEC TS_SODA_to_ST = FROM "rxSodaClk_S" TO "ST_CLK_S_net" TIG;
+TIMESPEC TS_SODA_to_G = FROM "rxSodaClk_S" TO "GCLK_P" TIG ;
+
+
+################################################################################################################################
+# GTX
+#NET "MGTREFCLK_P" TNM_NET = "MGTREFCLK_P";
+#TIMESPEC TS_MGTREFCLK_P = PERIOD "MGTREFCLK_P" 12.5 ns HIGH 50 %;
+#NET "MGTREFCLK_N" TNM_NET = "MGTREFCLK_N";
+#TIMESPEC TS_MGTREFCLK_N = PERIOD "MGTREFCLK_N" 12.5 ns HIGH 50 %;
+
+NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/rxRecClk_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/rxRecClk_S";
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_rxRecClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/rxRecClk_S" 10 ns HIGH 50 %;
+NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txOutClk_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txOutClk_S";
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_txOutClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txOutClk_S" 12.5 ns HIGH 50 %;
+
+
+### ???????????????? :
+NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S";
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_txUsrClk_buf_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" 10 ns HIGH 50 %;
+
+NET "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S";
+TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Kintex7_1_txUsrClkx2_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" 5 ns HIGH 50 %;
+
+
+TIMESPEC TS_FEE_gtxModule1_tx = FROM "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" 2 ns;
+TIMESPEC TS_FEE_gtxModule1_tx = FROM "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClkx2_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/txUsrClk_buf_S" 2 ns;
+
+INST "FEE_gtxModule1/FEE_gtxWrapper_Kintex7_1/gtx_i/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i" LOC = GTXE2_CHANNEL_X0Y0;
+
+################################################################################################################################
+# ADC
+NET "ADC_clk_S" TNM_NET = "ADC_clk_S";
+TIMESPEC TS_ADC_clk_S = PERIOD "ADC_clk_S" 12.5 ns HIGH 50 %;
+NET "ADC_clk_S" MAXDELAY = 3 ns;
+NET "ADC_clk_S" MAXSKEW = 1 ns;
+
+
+################################################################################################################################
+# ADC placement
+INST "FEE_ADCinput_module1/AdcToplevel1458_1" AREA_GROUP = "pblock_adc_1";
+INST "FEE_ADCinput_module1/AdcToplevel2356_1" AREA_GROUP = "pblock_adc_1";
+AREA_GROUP "pblock_adc_1" RANGE=SLICE_X106Y50:SLICE_X109Y99;
+#AREA_GROUP "pblock_adc_1" RANGE=SLICE_X104Y99:SLICE_X108Y50;
+INST "FEE_ADCinput_module1/AdcToplevel1458_2" AREA_GROUP = "pblock_adc_2";
+INST "FEE_ADCinput_module1/AdcToplevel2356_2" AREA_GROUP = "pblock_adc_2";
+AREA_GROUP "pblock_adc_2" RANGE=SLICE_X0Y50:SLICE_X3Y99;
+#AREA_GROUP "pblock_adc_2" RANGE=SLICE_X1Y99:SLICE_X2Y50;
+#AREA_GROUP "pblock_adc_2" RANGE=SLICE_X0Y99:SLICE_X2Y50;
+INST "FEE_ADCinput_module1/AdcToplevel1458_3" AREA_GROUP = "pblock_adc_3";
+INST "FEE_ADCinput_module1/AdcToplevel2356_3" AREA_GROUP = "pblock_adc_3";
+AREA_GROUP "pblock_adc_3" RANGE=SLICE_X0Y100:SLICE_X3Y149;
+#AREA_GROUP "pblock_adc_3" RANGE=SLICE_X1Y149:SLICE_X2Y100;
+INST "FEE_ADCinput_module1/AdcToplevel1458_4" AREA_GROUP = "pblock_adc_4";
+INST "FEE_ADCinput_module1/AdcToplevel2356_4" AREA_GROUP = "pblock_adc_4";
+AREA_GROUP "pblock_adc_4" RANGE=SLICE_X0Y151:SLICE_X3Y199;
+
+
+#############################################################################################
+# Timing constraints
+#############################################################################################
+# The DCLK input clock, bit clock from the ADC, doesn't need a timespec.
+# This clock passes from the IOB through the BUFIO and to the .CLK input of all used ISERDES.
+# This path is made from dedicated routing.
+#   From the IOB to the BUFIO.I is a dedicated connection only availabel with Clock Capable_IO.
+#   This connection takes for all IO-banks in a FPGA and from all FPGAs of the familly an
+#   average value of 220 ps.
+#   The connection from the BUFIO.O to all ISERDES.CLK is also a dedicated connection, it 
+#   takes on average 330 ps.
+#   The BUFIO average delay is: 869 ps and an LVDS IOB is average: 1094 ps.
+# A MAXSKEW constraint is used to detect the skew on the CLK net.
+#-->NET "*AdcClock/BitClk_MonClkOut" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntClk" MAXSKEW = 100 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntClk" MAXSKEW = 100 ps;
+
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntClk" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntClk" MAXDELAY = 400 ps;
+
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/AdcToplevel_I_AdcClock/BitClk_inv" MAXDELAY = 400 ps;
+
+#
+# The connection from the BUFR.O to the ISERDES.CLKDIV inputs runs over normal clock nets.
+#   Oposite to the BUFIO.O - ISERDES.CLK routing, the BUFR.O net not only connects to the
+#   ISERDES.CLKDIV pins of the I/O SERDES in the IO-bank the BUFR is located in but to all
+#   clocked elements (FFs, BRAM, DSP, ..) in that clock area.
+#   It also connects to the adjacent upper and lower clock areas.
+#   Therefore it is necessary to put timing constraints on this clock.
+# A MAXSKEW constraint to keep the skew as low as possible. makes sure the ISERDES are clocked
+# at the same time so that early-late data cannot appear at the outputs of the ISERDES.
+#-->NET "*AdcClock/BitClk_RefClkOut" MAXSKEW = 300 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntClkDiv" MAXSKEW = 400 ps;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntClkDiv" MAXSKEW = 400 ps;
+
+
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntRst_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntRst_S" MAXDELAY = 1.5 ns;
+
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntEna_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntEna_S" MAXDELAY = 1.5 ns;
+
+NET "FEE_ADCinput_module1/AdcToplevel1458_1/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_2/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_3/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel1458_4/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_1/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_2/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_3/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+NET "FEE_ADCinput_module1/AdcToplevel2356_4/IntBitClkDone_S" MAXDELAY = 1.5 ns;
+
+# A period constraint at the BUFR will make sure the correct timing is applied on clock net.
+#-->NET "*AdcClock/BitClk_RefClkOut" TNM_NET = "BitClkRefClk";
+#-->TIMESPEC TS_ClkDiv = PERIOD "BitClkRefClk" 3.4 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk";
+TIMESPEC TS_AdcToplevel1458_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk";
+TIMESPEC TS_AdcToplevel2356_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" 3 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk";
+TIMESPEC TS_AdcToplevel1458_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk";
+TIMESPEC TS_AdcToplevel2356_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" 3 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk";
+TIMESPEC TS_AdcToplevel1458_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk";
+TIMESPEC TS_AdcToplevel2356_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" 3 ns HIGH 50 %;
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk";
+TIMESPEC TS_AdcToplevel1458_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" 3 ns HIGH 50 %;
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk";
+TIMESPEC TS_AdcToplevel2356_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" 3 ns HIGH 50 %;
+
+
+
+
+
+
+
+################################################################################
+# Grouping of components.
+################################################################################
+# The logic of the interface is timing constraint with FROM-TO constraints.
+# The logic is first grouped per functionality and the constraints are applied.
+#-->INST "*AdcClock/AdcClock_I_Isrds_*" TNM =  FFS "AdcClk_Isrds";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM =  FFS "AdcClk_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM =  FFS "AdcClk_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM =  FFS "AdcClk_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM =  FFS "AdcClk_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM =  FFS "AdcClk_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM =  FFS "AdcClk_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM =  FFS "AdcClk_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcClock/AdcClock_I_Isrds_*" TNM =  FFS "AdcClk_Isrds4B";
+#-->INST "*AdcClock/*" TNM =  FFS "AdcClk_Ffs";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcClock/*" TNM =  FFS "AdcClk_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcClock/*" TNM =  FFS "AdcClk_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcClock/*" TNM =  FFS "AdcClk_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcClock/*" TNM =  FFS "AdcClk_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcClock/*" TNM =  FFS "AdcClk_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcClock/*" TNM =  FFS "AdcClk_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcClock/*" TNM =  FFS "AdcClk_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcClock/*" TNM =  FFS "AdcClk_Ffs4B";
+
+#-->INST "*AdcFrame/AdcFrame_I_Isrds_*" TNM =  FFS "AdcFrm_Isrds";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM =  FFS "AdcFrame_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM =  FFS "AdcFrame_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM =  FFS "AdcFrame_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM =  FFS "AdcFrame_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM =  FFS "AdcFrame_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM =  FFS "AdcFrame_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM =  FFS "AdcFrame_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/AdcFrame_I_Isrds_*" TNM =  FFS "AdcFrame_Isrds4B";
+#-->INST "*AdcFrame/*" TNM =  FFS "AdcFrm_Ffs";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/*" TNM =  FFS "AdcFrame_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/*" TNM =  FFS "AdcFrame_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/*" TNM =  FFS "AdcFrame_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/*" TNM =  FFS "AdcFrame_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/*" TNM =  FFS "AdcFrame_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/*" TNM =  FFS "AdcFrame_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/*" TNM =  FFS "AdcFrame_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/*" TNM =  FFS "AdcFrame_Ffs4B";
+
+#-->INST "*AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[0].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[1].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[2].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[3].AdcToplevel_I_AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcData_Isrds4B";
+
+#-->INST "*AdcData/*" TNM =  FFS "AdcData_Ffs";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[0].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[0].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[0].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[0].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[0].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[0].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[0].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[0].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[1].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[1].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[1].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[1].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[1].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[1].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[1].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[1].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[2].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[2].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[2].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[2].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[2].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[2].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[2].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[2].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs4B";
+
+INST "FEE_ADCinput_module1/AdcTopleveL1458_1/Gen_2[3].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs1A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_1/Gen_2[3].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs1B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_2/Gen_2[3].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs2A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_2/Gen_2[3].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs2B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_3/Gen_2[3].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs3A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_3/Gen_2[3].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs3B";
+INST "FEE_ADCinput_module1/AdcTopleveL1458_4/Gen_2[3].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs4A";
+INST "FEE_ADCinput_module1/AdcTopleveL2356_4/Gen_2[3].AdcToplevel_I_AdcData/*" TNM =  FFS "AdcData_Ffs4B";
+
+################################################################################
+# Timespec between groups
+################################################################################
+#-->TIMESPEC TS_ClkIsrds_ClkFfs = FROM "AdcClk_Isrds" TO "AdcClk_Ffs" 3 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs1A = FROM "AdcClk_Isrds1A" TO "AdcClk_Ffs1A" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs1B = FROM "AdcClk_Isrds1B" TO "AdcClk_Ffs1B" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs2A = FROM "AdcClk_Isrds2A" TO "AdcClk_Ffs2A" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs2B = FROM "AdcClk_Isrds2B" TO "AdcClk_Ffs2B" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs3A = FROM "AdcClk_Isrds3A" TO "AdcClk_Ffs3A" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs3B = FROM "AdcClk_Isrds3B" TO "AdcClk_Ffs3B" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs4A = FROM "AdcClk_Isrds4A" TO "AdcClk_Ffs4A" 2.2 ns;
+TIMESPEC TS_ClkIsrds_ClkFfs4B = FROM "AdcClk_Isrds4B" TO "AdcClk_Ffs4B" 2.2 ns;
+#-->TIMESPEC TS_FrmIsrds_FrmFfs = FROM "AdcFrm_Isrds" TO "AdcFrm_Ffs" 3 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs1A = FROM "AdcFrame_Isrds1A" TO "AdcFrame_Ffs1A" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs1B = FROM "AdcFrame_Isrds1B" TO "AdcFrame_Ffs1B" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs2A = FROM "AdcFrame_Isrds2A" TO "AdcFrame_Ffs2A" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs2B = FROM "AdcFrame_Isrds2B" TO "AdcFrame_Ffs2B" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs3A = FROM "AdcFrame_Isrds3A" TO "AdcFrame_Ffs3A" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs3B = FROM "AdcFrame_Isrds3B" TO "AdcFrame_Ffs3B" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs4A = FROM "AdcFrame_Isrds4A" TO "AdcFrame_Ffs4A" 2.2 ns;
+TIMESPEC TS_FrameIsrds_FrameFfs4B = FROM "AdcFrame_Isrds4B" TO "AdcFrame_Ffs4B" 2.2 ns;
+#-->TIMESPEC TS_DatIsrds_DatFfs = FROM "AdcDat_Isrds" TO "AdcDat_Ffs" 3 ns;
+TIMESPEC TS_DataIsrds_DataFfs1A = FROM "AdcData_Isrds1A" TO "AdcData_Ffs1A" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs1B = FROM "AdcData_Isrds1B" TO "AdcData_Ffs1B" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs2A = FROM "AdcData_Isrds2A" TO "AdcData_Ffs2A" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs2B = FROM "AdcData_Isrds2B" TO "AdcData_Ffs2B" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs3A = FROM "AdcData_Isrds3A" TO "AdcData_Ffs3A" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs3B = FROM "AdcData_Isrds3B" TO "AdcData_Ffs3B" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs4A = FROM "AdcData_Isrds4A" TO "AdcData_Ffs4A" 2.2 ns;
+TIMESPEC TS_DataIsrds_DataFfs4B = FROM "AdcData_Isrds4B" TO "AdcData_Ffs4B" 2.2 ns;
+
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv2";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv3";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv4";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv5";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv6";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv7";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv8";
+
+NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" TNM_NET = "IntClk1";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" TNM_NET = "IntClk2";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" TNM_NET = "IntClk3";
+NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" TNM_NET = "IntClk4";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" TNM_NET = "IntClk5";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" TNM_NET = "IntClk6";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" TNM_NET = "IntClk7";
+NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" TNM_NET = "IntClk8";
+
+
+TIMESPEC TS_IntClkDiv_IntClk1 = FROM "IntClkDiv1" TO "IntClk1" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk2 = FROM "IntClkDiv2" TO "IntClk2" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk3 = FROM "IntClkDiv3" TO "IntClk3" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk4 = FROM "IntClkDiv4" TO "IntClk4" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk5 = FROM "IntClkDiv5" TO "IntClk5" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk6 = FROM "IntClkDiv6" TO "IntClk6" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk7 = FROM "IntClkDiv7" TO "IntClk7" 2 ns;
+TIMESPEC TS_IntClkDiv_IntClk8 = FROM "IntClkDiv8" TO "IntClk8" 2 ns;
+
+#TIMESPEC TS_IntClk_IntClkDiv1 = FROM "IntClk1" TO "IntClkDiv1" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv2 = FROM "IntClk2" TO "IntClkDiv2" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv3 = FROM "IntClk3" TO "IntClkDiv3" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv4 = FROM "IntClk4" TO "IntClkDiv4" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv5 = FROM "IntClk5" TO "IntClkDiv5" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv6 = FROM "IntClk6" TO "IntClkDiv6" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv7 = FROM "IntClk7" TO "IntClkDiv7" 2 ns;
+#TIMESPEC TS_IntClk_IntClkDiv8 = FROM "IntClk8" TO "IntClkDiv8" 2 ns;
+
+
+###############################################################################################
+
+#TIMESPEC TS_Data_ADCclk1A = FROM "AdcData_Ffs1A" TO "ADC_clk_S" 1 ns;
+#TIMESPEC TS_Data_ADCclk2A = FROM "AdcData_Ffs2A" TO "ADC_clk_S" 1 ns;
+#TIMESPEC TS_Data_ADCclk2B = FROM "AdcData_Ffs2B" TO "ADC_clk_S 1 ns;
+#TIMESPEC TS_Data_ADCclk3A = FROM "AdcData_Ffs3A" TO "ADC_clk_S" 1 ns;
+#TIMESPEC TS_Data_ADCclk3B = FROM "AdcData_Ffs3B" TO "ADC_clk_S" 1 ns;
+#TIMESPEC TS_Data_ADCclk4A = FROM "AdcData_Ffs4A" TO "ADC_clk_S" 1 ns;
+#TIMESPEC TS_Data_ADCclk4B = FROM "AdcData_Ffs4B" TO "ADC_clk_S" 1 ns;
+
+
+# sys_clk not 
+NET "SYS_CLK" CLOCK_DEDICATED_ROUTE = BACKBONE; 
+PIN "clockmodule100Mto80Ma/mmcm_adv_inst.CLKIN1" CLOCK_DEDICATED_ROUTE = BACKBONE; 
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_SODAfrequencydiv5.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_SODAfrequencydiv5.vhd
new file mode 100644
index 0000000..16a0c4c
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_SODAfrequencydiv5.vhd
@@ -0,0 +1,190 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   18-11-2014
+-- Module Name:   FEE_SODAfrequencydiv5
+-- Description:   Converts 200MHz from GTX to 40 MHz SODA
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_SODAfrequencydiv5
+-- Measures the number of pulses in one second
+--
+-- Library
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock : recovered clock 
+--     data : data from GTX
+--     kchar : k-character signal from GTX
+-- 
+-- Outputs:
+--     clockdiv5 : input clock divided by 5 and synchronous to SODA
+--     error : error in incoming data or phase
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_SODAfrequencydiv5 is
+	port ( 
+		clock                   : in std_logic;
+		data                    : in std_logic_vector(7 downto 0);
+		kchar                   : in std_logic;
+		clockdiv5               : out std_logic;
+		error                   : out std_logic
+	);
+end FEE_SODAfrequencydiv5;
+
+architecture Behavioral of FEE_SODAfrequencydiv5 is
+constant KCHARSODA              : std_logic_vector(7 downto 0) := x"DC"; 
+
+signal clockdiv5_S              : std_logic;
+signal div5count0_S             : std_logic;
+signal clock5div2_S             : std_logic := '0';
+signal prev_clock5div2_S        : std_logic := '0';
+signal clockdiv5_reset_S        : std_logic;
+signal SODA_kchar_S             : std_logic;
+signal disable_SODAcheck_S      : std_logic := '0';
+signal disable_clock5check_S    : std_logic := '0';
+signal SODA40_signal_S          : std_logic;
+signal div5count_S              : std_logic_vector(2 downto 0) := (others => '0');
+signal SODA_count_S             : std_logic_vector(3 downto 0) := (others => '0');
+signal SODAerror_S              : std_logic;
+signal clockdiv5error_S         : std_logic;
+signal clockbiterror_S          : std_logic;
+
+begin
+	
+error <= '1' when (SODAerror_S='1') or (clockdiv5error_S='1') or (clockbiterror_S='1') else '0';
+--clockdiv5 <= clockdiv5_S;
+clockdiv5buf : BUFG
+	port map (
+		I => clockdiv5_S,
+		O => clockdiv5);
+		
+rxrecclk_bufrdiv5_i : BUFR
+	generic map ( BUFR_DIVIDE => "5" )
+	port map (
+		CE => '1',
+		CLR => clockdiv5_reset_S,
+		I => clock,
+		O => clockdiv5_S);
+
+process_checkSODA: process(clock)
+variable disable_count_V : std_logic_vector(1 downto 0) := (others => '0');
+begin
+	if (rising_edge(clock)) then 
+		div5count0_S <= '0';
+		clockbiterror_S <= '0';
+		if div5count_S/="100" then 
+			if (disable_SODAcheck_S='0') and (SODA40_signal_S='1') then -- wrong phase
+				div5count_S <= "000";
+				disable_SODAcheck_S <= '1';
+				disable_count_V := (others => '0');
+				clockbiterror_S <= '1';
+			else
+				div5count_S <= div5count_S+1;
+			end if;
+		else
+			div5count_S <= "000";
+			div5count0_S <= '1';
+			if disable_count_V(disable_count_V'left)='0' then
+				disable_count_V := disable_count_V+1;
+			else
+				disable_SODAcheck_S <= '0';
+			end if;
+		end if;
+		prev_clock5div2_S <= clock5div2_S;
+	end if;
+end process;
+
+
+
+process_checkdiv5: process(clock)
+variable disable_count_V : std_logic_vector(3 downto 0) := (others => '0');
+begin
+	if (rising_edge(clock)) then 
+		clockdiv5_reset_S <= '0';
+		clockdiv5error_S <= '0';
+		if (disable_SODAcheck_S='0') and (disable_clock5check_S='0') then
+			if (clock5div2_S/=prev_clock5div2_S) and div5count0_S='0' then -- div5 clock wrong phase : reset
+				clockdiv5_reset_S <= '1';
+				disable_clock5check_S <= '1';
+				disable_count_V := (others => '0');
+				clockdiv5error_S <= '1';
+			end if;
+		else
+			if disable_count_V(disable_count_V'left)='0' then
+				disable_count_V := disable_count_V+1;
+			else
+				disable_clock5check_S <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+process_SODAchar: process(clock)
+variable count_V : std_logic_vector(2 downto 0) := (others => '0');
+variable count_rotate_V : std_logic_vector(2 downto 0) := (others => '0');
+begin
+	if (rising_edge(clock)) then 
+		if (kchar='1') and (data=KCHARSODA) then
+			SODA_kchar_S <= '1';
+		else
+			SODA_kchar_S <= '0';
+		end if;
+	end if;
+end process;
+
+process_SODAstart: process(clock)
+variable count_V : std_logic_vector(2 downto 0) := (others => '0');
+variable count_rotate_V : std_logic_vector(2 downto 0) := (others => '0');
+begin
+	if (rising_edge(clock)) then 
+		SODA40_signal_S <= '0';
+		SODAerror_S <= '0';
+		if (SODA_count_S="0000") and (SODA_kchar_S='1') then
+			SODA40_signal_S <= '1';
+			SODA_count_S <= SODA_count_S+1;
+		elsif SODA_count_S(0)='1' then -- SODA data 
+			if SODA_kchar_S='1' then -- error
+				SODA_count_S <= "0000";
+				SODAerror_S <= '1';
+			else
+				SODA_count_S <= SODA_count_S+1;
+			end if;
+		elsif (SODA_count_S(2 downto 1)/="00") then -- SODA k-char
+			if SODA_kchar_S='0' then -- error
+				SODA_count_S <= "0000";
+				SODAerror_S <= '1';
+			else
+				SODA_count_S <= SODA_count_S+1;
+			end if;
+		elsif (SODA_count_S(3)='1') then -- end SODA packet
+			SODA_count_S <= "0000";
+			if SODA_kchar_S='1' then -- error
+				SODAerror_S <= '1';
+			end if;
+		end if;
+	end if;
+end process;
+
+process_clock5div2: process(clockdiv5_S)
+begin
+	if (rising_edge(clockdiv5_S)) then 
+		clock5div2_S <= not clock5div2_S;
+	end if;
+end process;
+
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data16to8.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data16to8.vhd
new file mode 100644
index 0000000..f211884
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data16to8.vhd
@@ -0,0 +1,109 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   04-02-2015
+-- Module Name:   FEE_data16to8
+-- Description:   Converts 16 bits data at 100MHz to 8 bits data at 200MHz
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_data16to8
+-- Converts 16 bits data at 100MHz to 8 bits data at 200MHz
+--
+-- Library
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock_in : input clock at single 
+--     data_in : 16 bits input data
+--     kchar_in : corresponding k-character (one for each input byte)
+-- 
+-- Outputs:
+--     clock_out : output clock at double speed
+--     data_out : 8 bits output data at double speed
+--     kchar_out : corresponding k-character
+-- 
+-- Components:
+--     clock100to200 : clock doubler : 100MHz -> 200MHz
+--
+----------------------------------------------------------------------------------
+
+entity FEE_data16to8 is
+	port ( 
+		clock_in                : in std_logic;
+		data_in                 : in std_logic_vector(15 downto 0);
+		kchar_in                : in std_logic_vector(1 downto 0);
+		notintable_in           : in std_logic_vector(1 downto 0);
+		clock_out               : out std_logic;
+		data_out                : out std_logic_vector(7 downto 0);
+		kchar_out               : out std_logic;
+		notintable_out          : out std_logic
+	);
+end FEE_data16to8;
+
+architecture Behavioral of FEE_data16to8 is
+
+component clock100to200 is
+	port
+	(
+		clk_in1                 : in std_logic;
+		clk_out1                : out std_logic;
+		clk_out2                : out std_logic
+	);
+end component;
+
+signal clock_out_S              : std_logic;
+signal phase_S                  : std_logic;
+signal kchar_in_S               : std_logic_vector(1 downto 0);
+
+begin
+
+clock100to200_1: clock100to200 port map(
+		clk_in1 => clock_in,
+		clk_out1 => open,
+		clk_out2 => clock_out_S);
+clock_out <= clock_out_S;
+
+process(clock_out_S)
+begin
+	if (rising_edge(clock_out_S)) then
+		kchar_in_S <= kchar_in;
+	end if;
+end process;
+	
+process(clock_out_S)
+begin
+	if (rising_edge(clock_out_S)) then
+		if kchar_in_S/=kchar_in then
+			phase_S <= '0';
+		else
+			phase_S <= not phase_S;
+		end if;
+	end if;
+end process;
+
+process(clock_out_S)
+begin
+	if (rising_edge(clock_out_S)) then
+		if phase_S='1' then
+			data_out <= data_in(7 downto 0);
+			kchar_out <= kchar_in(0);
+			notintable_out <= notintable_in(0);
+		else
+			data_out <= data_in(15 downto 8);
+			kchar_out <= kchar_in(1);
+			notintable_out <= notintable_in(1);
+		end if;
+	end if;
+end process;
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data8to16.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data8to16.vhd
new file mode 100644
index 0000000..9322aa2
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_data8to16.vhd
@@ -0,0 +1,100 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   06-02-2015
+-- Module Name:   FEE_data8to16
+-- Description:   Converts 8 bits data at 200MHz to 16 bits data at 100MHz
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_data8to16
+-- Converts 8 bits data at 200MHz to 16 bits data at 100MHz
+--
+-- Library
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock_in : input clock
+--     data_in : 8 bits input data
+--     kchar_in : corresponding k-character
+-- 
+-- Outputs:
+--     clock_out : output clock at half speed
+--     data_out : 16 bits output data at half speed
+--     kchar_out : corresponding k-character (one for each byte)
+-- 
+-- Components:
+--     clock100to200 : clock doubler : 100MHz -> 200MHz
+--
+----------------------------------------------------------------------------------
+
+entity FEE_data8to16 is
+	port ( 
+		clock_in                : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		kchar_in                : in std_logic;
+		clock_out               : in std_logic;
+		data_out                : out std_logic_vector(15 downto 0);
+		kchar_out               : out std_logic_vector(1 downto 0)
+	);
+end FEE_data8to16;
+
+architecture Behavioral of FEE_data8to16 is
+
+component clock100to200 is
+	port
+	(
+		clk_in1                 : in std_logic;
+		clk_out1                : out std_logic;
+		clk_out2                : out std_logic
+	);
+end component;
+
+signal clock_in_S               : std_logic;
+signal data_in0_S               : std_logic_vector(7 downto 0);
+signal kchar_in0_S              : std_logic;
+signal data_in1_S               : std_logic_vector(7 downto 0);
+signal kchar_in1_S              : std_logic;
+signal data_out_S               : std_logic_vector(15 downto 0);
+signal kchar_out_S              : std_logic_vector(1 downto 0);
+
+begin
+
+--clock100to200_1: clock100to200 port map(
+--		clk_in1 => clock_out,
+--		clk_out1 => open,
+--		clk_out2 => clock_in_S);
+--clock_in <= clock_in_S;
+clock_in_S <= clock_in;
+
+	
+process(clock_in_S)
+begin
+	if (rising_edge(clock_in_S)) then
+		data_in0_S <= data_in;
+		kchar_in0_S <= kchar_in;
+		data_in1_S <= data_in0_S;
+		kchar_in1_S <= kchar_in0_S;
+	end if;
+end process;
+
+process(clock_out)
+begin
+	if (rising_edge(clock_out)) then
+		data_out_S <= data_in0_S & data_in1_S;
+		kchar_out_S <= kchar_in0_S & kchar_in1_S;
+		data_out <= data_out_S;
+		kchar_out <= kchar_out_S;
+	end if;
+end process;
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxModule.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxModule.vhd
new file mode 100644
index 0000000..12ece92
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxModule.vhd
@@ -0,0 +1,413 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   26-08-2013
+-- Module Name:   FEE_gtxModule
+-- Description:   GTP/GTX/serdes tranceiver for PANDA Front End Electronics with clock synchronization
+-- Modifications:
+--   19-11-2014   Name changed from gtpBufLayerFee to FEE_gtxModule
+--   07-02-2015   Version for Kintex7
+--   25-01-2017   First/last signals added
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+library work;
+use work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_gtxModule
+-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization:
+--
+-- Receiver generates synchronous clock on incomming serial data (SODA) and detects synchronous 
+-- data packages (SODA-commands) with fixed delay. 
+-- Receives also asynchronous data from fibre and outputs it as 32 bits.
+-- SODA packages use the DLM i/o. Data is send along with K27.7 character (0xFB)
+-- Idle's consists of K28.1 & K28.5 characters (0x3c,0xBC)
+-- All other valid (non K) characters is treated as data and combined to 32-bits
+--
+-- Transmitter sends data (asynchronous to SODA). The data is organised as 32-bits words.
+-- If no data is available then idle's are sent (0x3CBC)
+--
+-- Only one channel of the dual GTP or GTX is used.
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     gtpClk_P,gtpClk_N : Reference clock for GTP/GTX, frequency must match expected SODA frequency (finally probably 155.52 MHz)
+--     sysClk : stable clock (80MHz)
+--     asyncclk : stable clock at different clock speed (not used)
+--     reset : reset GTP/GTX
+--     disable_GTX_reset : disable reset of GTX (during clock switching)
+--     TX_DLM : transmit SODA character
+--     TX_DLM_WORD : SODA character to be transmitted
+--     rxAsyncClk : Clock for the asynchronous (32-bits) data (used for slow-control in FEE)
+--     txAsyncData : asynchronous 32-bits data to be transmitted
+--     txAsyncDataWrite : write signal for asynchronous 32-bits data to be transmitted
+--     txAsyncFirstData : First asynchronous 32-bits word of the data packet to be transmitted
+--     txAsyncLastData : Last asynchronous 32-bits word of the data packet to be transmitted, used for separating packets on the fiber
+--     txAsyncClk : clock for the asynchronous 32-bits data to be transmitted
+--     rxAsyncDataRead : read signal for the asynchronous data fifo
+--     gtpRxP0,gtpRxN0 :  differential GTP/GTX inputs 
+-- 
+-- Outputs:
+--     RX_DLM : SODA character received
+--     RX_DLM_WORD : SODA character 
+--     txAsyncFifoFull : fifo for 32-bits transmit data is full
+--     txLocked : Transmitter PLL locked
+--     rxAsyncData : asynchronous 32 bits data from the receiver fifo
+--     rxError : invalid character or other receiver error
+--     rxAsyncDataOverflow : overflow bit of the receiver asynchronous data fifo
+--     rxAsyncDataPresent : Indicates if asynchronous data is available in the receiver fifo
+--     rxSodaClk : Reconstructed clock, synchronous with original SODA clock but different frequency (200MHz)
+--     rxSodaClk40 : Reconstructed SODA clock : 40MHz
+--     rxLocked : Receiver locked
+--     gtpTxP0,gtpTxN0 : differential transmit outputs of the GTP/GTX (not used at the moment)
+-- 
+-- Components:
+--     FEE_gtxWrapper_Kintex7 : module with the GTP/GTX interface
+--     FEE_SODAfrequencydiv5 : make divide by 5 clock from recovered clock
+--     FEE_fifo32to8_SODA : fifo for data to be transmitted, converts data from 32-bits to 16-bits
+--     FEE_fifo8to32_SODA : fifo for received asynchronous data, converts data from 16-bits to 32-bits
+--     sync_to_different_phase : synchronize to clock with same frequency but different phase
+--
+----------------------------------------------------------------------------------
+
+entity FEE_gtxModule is
+	Port (
+		gtpClk_P                : in std_logic;
+		gtpClk_N                : in std_logic;
+		refclk_out              : out std_logic;
+		sysClk                  : in  std_logic;	
+		asyncclk                : in std_logic;
+		reset                   : in std_logic;
+		disable_GTX_reset       : in std_logic;
+		
+		TX_DLM                  : in std_logic;
+		TX_DLM_WORD             : in std_logic_vector(7 downto 0);   
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		
+		txAsyncClk              : in std_logic;
+		txAsyncData             : in std_logic_vector(31 downto 0);
+		txAsyncDataWrite        : in std_logic;
+		txAsyncFirstData        : in std_logic;
+		txAsyncLastData         : in std_logic;
+		txAsyncFifoFull         : out std_logic;
+		txUsrClk                : out  std_logic;
+		txLocked                : out std_logic;
+		
+		rxAsyncClk              : in std_logic;
+		rxAsyncData             : out std_logic_vector(31 downto 0);
+		rxAsyncFirstData        : out std_logic;
+		rxAsyncLastData         : out std_logic;
+		rxAsyncDataRead         : in std_logic;
+		rxError                 : out std_logic;
+		rxAsyncDataOverflow     : out std_logic;
+		rxAsyncDataPresent      : out std_logic;
+		rxUsrClkdiv2            : out std_logic;
+		rxSodaClk               : out std_logic;
+		rxSodaClk40             : out std_logic;
+		rxLocked                : out std_logic;
+		
+		gtpTxP0                 : out std_logic;
+		gtpTxN0                 : out std_logic;
+		gtpRxP0                 : in std_logic;
+		gtpRxN0                 : in std_logic;
+		GT0_QPLLOUTCLK_IN       : in std_logic;
+		GT0_QPLLOUTREFCLK_IN    : in std_logic
+	);
+end FEE_gtxModule;
+
+
+architecture Behavioral of FEE_gtxModule is
+
+component FEE_gtxWrapper_Kintex7 is
+	port (
+		gtpClk_P              : in  std_logic;	
+		gtpClk_N              : in  std_logic;	
+		refclk_out              : out std_logic;
+		sysClk                : in  std_logic;	
+		gtpReset              : in  std_logic;
+		disable_GTX_reset     : in  std_logic;
+		
+		txData                : in  std_logic_vector (7 downto 0);
+		txCharIsK             : in  std_logic;
+		txP                   : out  std_logic;
+		txN                   : out  std_logic;
+		txUsrClk              : out  std_logic;
+		txLocked              : out  std_logic;
+		
+		rxData                : out  std_logic_vector (7 downto 0);
+		rxCharIsK             : out  std_logic;
+		rxNotInTable          : out  std_logic;
+		rxP                   : in  std_logic;
+		rxN                   : in  std_logic;
+		rxUsrClk              : out std_logic;
+		rxUsrClkdiv2          : out std_logic;
+		rxLocked              : out  std_logic;
+		
+		resetDone             : out  std_logic;
+		GT0_QPLLOUTCLK_IN     : in std_logic;
+		GT0_QPLLOUTREFCLK_IN  : in std_logic
+	);
+end component;
+
+component FEE_SODAfrequencydiv5 is
+	port ( 
+		clock                   : in std_logic;
+		data                    : in std_logic_vector(7 downto 0);
+		kchar                   : in std_logic;
+		clockdiv5               : out std_logic;
+		error                   : out std_logic
+	);
+end component;
+
+component FEE_fifo32to8_SODA is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(31 downto 0);
+		data_write              : in std_logic;
+		full                    : out std_logic;
+		TX_DLM                  : in std_logic;
+		TX_DLM_WORD             : in std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(7 downto 0);
+		char_is_k               : out std_logic
+	);
+end component;
+
+component FEE_fifo8to32_SODA is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		char_is_k               : in std_logic;
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(31 downto 0);
+		data_read               : in std_logic;
+		data_available          : out std_logic;
+		overflow                : out std_logic;
+		error                   : out std_logic	
+	);
+end component;
+
+component sync_to_different_phase is
+	generic (
+		WIDTH                   : natural := 18
+	);
+	port ( 
+		clock1                  : in std_logic;
+		clock2                  : in std_logic;
+		data_in                 : in std_logic_vector(WIDTH-1 downto 0);
+		data_out                : out std_logic_vector(WIDTH-1 downto 0)
+	);
+end component;
+
+component async_fifo_16x9
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(8 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(8 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+component asyncfifo is
+    generic (
+        DATA_WIDTH : natural := 9;
+        ADDR_WIDTH : natural := 2
+    );
+    port (
+		reset : in std_logic;
+		read_clock : in std_logic;
+		read_request  : in std_logic;
+		data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+		write_clock : in std_logic;
+		write_request : in std_logic;
+		data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
+		empty : out std_logic;
+		full : out std_logic;
+		valid : out std_logic
+    );
+end component;
+
+signal rxSodaClk40_S          : std_logic := '0';
+signal rxNotInTable_S         : std_logic := '0';
+signal rxLocked_S             : std_logic := '0';
+signal txLocked_S             : std_logic := '0';
+signal txreset_S              : std_logic := '0';
+signal txCharIsK_S            : std_logic := '0';
+signal txUsrClk_S             : std_logic;
+signal txData_S               : std_logic_vector(7 downto 0);
+signal rxCharIsK_S            : std_logic;
+
+signal rxUsrClk_S             : std_logic;
+signal rxData_S               : std_logic_vector(7 downto 0);
+signal rxerror_s              : std_logic;
+
+signal TX_DLM_S               : std_logic;
+signal TX_DLM_WORD_S          : std_logic_vector(7 downto 0);
+signal RX_DLM_S               : std_logic;
+signal RX_DLM_WORD_S          : std_logic_vector(7 downto 0);
+
+signal fifo_dout_S            : std_logic_vector(8 downto 0) := (others => '0');
+signal fifosync_write_S       : std_logic;
+signal fifosync_read_S        : std_logic;
+signal fifosync_empty_S       : std_logic;
+signal fifosync_full_S        : std_logic;
+signal fifosync_valid_S       : std_logic;
+signal rxphase_S              : std_logic;
+signal rxphaseError_S         : std_logic;
+signal rxAsyncData_S          : std_logic_vector(31 downto 0);
+signal rxAsyncDataRead_aftr1clk_S : std_logic;
+
+begin
+
+txUsrClk <= txUsrClk_S;
+rxSodaClk <= rxUsrClk_S;
+rxSodaClk40 <= rxSodaClk40_S;
+
+FEE_gtxWrapper_Kintex7_1 : FEE_gtxWrapper_Kintex7 
+	port map (	
+		gtpClk_P => gtpClk_P,
+		gtpClk_N => gtpClk_N,
+		refclk_out => refclk_out,
+		sysClk => sysClk,
+		gtpReset => reset,
+		disable_GTX_reset => disable_GTX_reset,
+		txData => txData_S,
+		txCharIsK => txCharIsK_S,
+		txP => gtpTxP0,
+		txN => gtpTxN0,
+		txUsrClk => txUsrClk_S,
+		txLocked => txLocked_S,
+		rxData => rxData_S,
+		rxCharIsK => rxCharIsK_S,
+		rxNotInTable => rxNotInTable_S,
+		rxP => gtpRxP0,
+		rxN => gtpRxN0,
+		rxUsrClk => rxUsrClk_S,
+		rxUsrClkdiv2 => rxUsrClkdiv2,
+		rxLocked => rxLocked_S,
+		resetDone => open,
+		GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
+		GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN
+	);
+
+FEE_SODAfrequencydiv51: FEE_SODAfrequencydiv5 port map(
+		clock => rxUsrClk_S,
+		data => rxData_S,
+		kchar => rxCharIsK_S,
+		clockdiv5 => rxSodaClk40_S,
+		error => open
+	);
+
+-- synchronise SODA signals to txUsrClk_S. same frequency, differe4nt phase -----------------
+txreset_S <= '1' when (txLocked_S='0') or (reset='1') or (rxLocked_S='0') else '0';
+fifosync: async_fifo_16x9 port map(
+		rst => txreset_S,
+		wr_clk => rxUsrClk_S,
+		rd_clk => txUsrClk_S,
+		din(7 downto 0) => TX_DLM_WORD,
+		din(8) => TX_DLM,
+		wr_en => fifosync_write_S,
+		rd_en => fifosync_read_S,
+		dout => fifo_dout_S,
+		full => fifosync_full_S,
+		empty => fifosync_empty_S);
+--fifosync: asyncfifo
+--    generic map(
+--        DATA_WIDTH => 9,
+--        ADDR_WIDTH => 2
+--    )
+--    port map(
+--		reset => txreset_S,
+--		read_clock => txUsrClk_S,
+--		read_request => fifosync_read_S,
+--		data_in(7 downto 0) => TX_DLM_WORD,
+--		data_in(8) => TX_DLM,
+--		write_clock => rxUsrClk_S,
+--		write_request => fifosync_write_S,
+--		data_out => fifo_dout_S,
+--		empty => fifosync_empty_S,
+--		full => fifosync_full_S,
+--		valid => fifosync_valid_S);
+fifosync_read_S <= '1'; -- when fifosync_empty_S='0' else '0';
+fifosync_write_S <= '1' when fifosync_full_S='0' else '0';
+
+TX_DLM_WORD_S <= fifo_dout_S(7 downto 0);
+TX_DLM_S <= fifo_dout_S(8); -- when fifosync_valid_S='1' else '0';
+
+FEE_fifo32to8_SODA1: FEE_fifo32to8_SODA port map(
+		write_clock => txAsyncClk,
+		read_clock => txUsrClk_S, 
+		reset => '0', -- reset,
+		data_in => txAsyncData,
+		data_write => txAsyncDataWrite,
+		full => txAsyncFifoFull,
+		TX_DLM => TX_DLM_S,
+		TX_DLM_WORD => TX_DLM_WORD_S,
+		data_out => txData_S,
+		char_is_k => txCharIsK_S 
+		);
+
+FEE_fifo8to32_SODA1: FEE_fifo8to32_SODA port map(
+		write_clock => rxUsrClk_S,
+		read_clock => rxAsyncClk,
+		reset => '0', -- reset,
+		data_in => rxData_S,
+		char_is_k => rxCharIsK_S,
+		RX_DLM => RX_DLM_S,
+		RX_DLM_WORD => RX_DLM_WORD_S,
+		data_out => rxAsyncData_S,
+		data_read => rxAsyncDataRead,
+		data_available => rxAsyncDataPresent,
+		overflow => rxAsyncDataOverflow,
+		error => rxerror_S);
+rxAsyncData <= rxAsyncData_S;
+rxAsyncFirstData <= '1' when (rxAsyncDataRead_aftr1clk_S='1') and (rxphase_S='0') else '0';
+rxAsyncLastData <= '1' when (rxAsyncDataRead_aftr1clk_S='1') and (rxphase_S='1') else '0';
+process(rxAsyncClk)
+begin
+	if (rising_edge(rxAsyncClk)) then
+		rxphaseError_S <= '0';
+		if (rxAsyncDataRead_aftr1clk_S='1') then
+			if rxphase_S='0' then
+				if rxAsyncData_S(31 downto 24)=x"5C" then
+					rxphase_S <= '1';
+				else
+					rxphaseError_S <= '1';
+				end if;
+			else
+				rxphase_S <= '0';
+			end if;
+		end if;
+		rxAsyncDataRead_aftr1clk_S <= rxAsyncDataRead;
+	end if;
+end process;
+
+RX_DLM <= RX_DLM_S;
+RX_DLM_WORD <= RX_DLM_WORD_S;
+
+txLocked <= txLocked_S; -- 1 => OK
+rxLocked <= rxLocked_S; -- 1 => OK
+rxError <= rxNotInTable_S or rxerror_S or rxphaseError_S; -- '1' => error
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxWrapper_Kintex7.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxWrapper_Kintex7.vhd
new file mode 100644
index 0000000..e60f83e
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/FEE_gtxWrapper_Kintex7.vhd
@@ -0,0 +1,549 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date:   05-02-2015
+-- Module Name:   FEE_gtxWrapper_Kintex7
+-- Description: GTP/GTX tranceiver for PANDA Front End Electronics on Kintex7 with clock synchronization
+-- Modifications:
+--   05-02-2015   Originally FEE_gtxWrapper_Virtex6
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library work;
+use work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_gtxWrapper_Kintex7
+-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization on a Virtex5.
+--
+-- Receiver makes recovered synchronous clock on incomming serial data (SODA). 
+-- Data is 16-bits, synchronous to recovered clock.
+-- Transmitter sends 16-bits data.
+--
+-- Only one channel of the dual GTP or GTX is used.
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     gtpClk_P,gtpClk_N : Reference clock for GTP/GTX, frequency must match expected SODA frequency 
+--     sysClk : stable clock (80MHz)
+--     gtpReset : reset GTP/GTX
+--     disable_GTX_reset : disable ressetting temporarely
+--     txData : 16-bits input data to transmit
+--     txCharIsK : data to transmit are K-characters
+--     rxP,rxN : differential transmit inputs from the GTP/GTX
+-- 
+-- Outputs:
+--     txP,txN : differential transmit outputs of the GTP/GTX
+--     txUsrClk : clock for transmit data
+--     txLocked :  transmitter locked
+--     rxData : 16-bits received data
+--     rxCharIsK : received 16-bits data (2 bytes) are K-characters
+--     rxNotInTable : receiver data not valid
+--     rxUsrClk : Recovered synchronous clock
+--     rxLocked : receiver locked to incomming data
+--     resetDone : resetting ready
+-- 
+-- Components:
+--     GTXVIRTEX5FEE : Xilinx module for GTP or GTX, generated with the IP core generator with a few adjustments
+--     FEE_rxBitLock : Module for checking and resetting the GTP/GTX to lock the receiver clock at the right phase
+--     Clock_62M5_doubler : Clock doubler with PLL
+--
+----------------------------------------------------------------------------------
+
+entity FEE_gtxWrapper_Kintex7 is
+	port (
+		gtpClk_P              : in  std_logic;	
+		gtpClk_N              : in  std_logic;	
+		refclk_out            : out std_logic;
+		sysClk                : in  std_logic;	
+		gtpReset              : in  std_logic;
+		disable_GTX_reset     : in  std_logic;
+		
+		txData                : in  std_logic_vector (7 downto 0);
+		txCharIsK             : in  std_logic;
+		txP                   : out  std_logic;
+		txN                   : out  std_logic;
+		txUsrClk              : out  std_logic;
+		txLocked              : out  std_logic;
+		
+		rxData                : out  std_logic_vector (7 downto 0);
+		rxCharIsK             : out  std_logic;
+		rxNotInTable          : out  std_logic;
+		rxP                   : in  std_logic;
+		rxN                   : in  std_logic;
+		rxUsrClk              : out std_logic;
+		rxUsrClkdiv2          : out std_logic;
+		rxLocked              : out  std_logic;
+		
+		resetDone             : out  std_logic;
+		GT0_QPLLOUTCLK_IN     : in std_logic;
+		GT0_QPLLOUTREFCLK_IN  : in std_logic
+	);
+end FEE_gtxWrapper_Kintex7;
+
+architecture Behavioral of FEE_gtxWrapper_Kintex7 is
+
+component gtxKintex7FEE80_support is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 12  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q0_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q0_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_OUT                    : out  std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_TXUSRCLKX2_OUT                      : out  std_logic; --// Modified
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic;
+       sysclk_in        : in std_logic;
+	   refclk_out       : out std_logic --// Modified
+
+);
+
+end component;
+
+component FEE_rxBitLock is
+	port (
+		clk                     : in  std_logic;
+		reset                   : in  std_logic;
+		resetDone               : in  std_logic;
+		lossOfSync              : in  std_logic;
+		rxPllLocked             : in  std_logic; 
+		rxReset                 : out  std_logic;
+		fsmStatus               : out  std_logic_vector (1 downto 0)
+	);
+end component;
+
+component FEE_data8to16 is
+	port ( 
+		clock_in                : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		kchar_in                : in std_logic;
+		clock_out               : in std_logic;
+		data_out                : out std_logic_vector(15 downto 0);
+		kchar_out               : out std_logic_vector(1 downto 0)
+	);
+end component;
+
+component FEE_data16to8 is
+	port ( 
+		clock_in                : in std_logic;
+        data_in                 : in std_logic_vector(15 downto 0);
+        kchar_in                : in std_logic_vector(1 downto 0);
+        notintable_in           : in std_logic_vector(1 downto 0);
+        clock_out               : out std_logic;
+        data_out                : out std_logic_vector(7 downto 0);
+        kchar_out               : out std_logic;
+        notintable_out          : out std_logic
+	);
+end component;
+
+component posedge_to_pulse is
+	port (
+		clock_in                : in  std_logic;
+		clock_out               : in  std_logic;
+		en_clk                  : in  std_logic;
+		signal_in               : in  std_logic;
+		pulse                   : out std_logic
+	);
+end component;
+
+
+signal gtpReset_S          : std_logic;
+signal txResetdone_S       : std_logic;
+signal pllLkDet_S          : std_logic :='0';
+signal rxResetDone_S       : std_logic :='0';
+signal rxResetDone_sysclk_S: std_logic;
+signal ff_txfullclk        : std_logic; -- tx clock at double tx speed
+signal ff_rxhalfclk        : std_logic; 
+signal ff_txhalfclk        : std_logic;
+
+signal txData16_S          : std_logic_vector(15 downto 0);
+signal txCharIsK16_S       : std_logic_vector(1 downto 0);
+
+signal rxReset_S           : std_logic :='0';
+signal rxData_S            : std_logic_vector(7 downto 0);
+signal rxCharIsK_S         : std_logic;
+signal rxNotInTable_S      : std_logic;
+signal rxData16_S          : std_logic_vector(15 downto 0);
+signal rxCharIsK16_S       : std_logic_vector(1 downto 0);
+signal rxNotInTable16_S    : std_logic_vector(1 downto 0);
+signal rxDispError16_S     : std_logic_vector(1 downto 0);
+signal rxLocked0_S         : std_logic;
+signal rxLocked1_S         : std_logic;
+signal rxLocked2_S         : std_logic;
+signal rxLossOfSync1_S     : std_logic;
+signal rxResetBitLock_S    : std_logic :='0';
+signal sync_rxResetBitLock_S : std_logic :='0';
+signal prev_rxResetBitLock_S : std_logic :='0';
+signal fsmStatus_S         : std_logic_vector(1 downto 0);
+signal rxPLLwrapper_reset_S : std_logic :='0';
+signal rxResetBitLock_pulse_S : std_logic :='0';
+
+
+signal rxCDRlock_S         : std_logic :='0';
+signal CDR_reset_S         : std_logic :='0';
+
+signal drpaddr_in_S        : std_logic_vector(8 downto 0);
+signal drpdi_in_S          : std_logic_vector(15 downto 0);
+signal drpdo_out_S         : std_logic_vector(15 downto 0);
+signal drpen_in_S          : std_logic;
+signal drprdy_out_S        : std_logic;
+signal drpwe_in_S          : std_logic;
+
+signal comma_align_latency_S        : std_logic_vector(6 downto 0);
+signal comma_align_latency_valid_S  : std_logic;
+
+
+type drp_state_type is (initting, running, reading);
+signal drp_state_S : drp_state_type := initting;	
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of rxData16_S : signal is "true";
+-- attribute mark_debug of rxCharIsK16_S : signal is "true";
+-- attribute mark_debug of rxNotInTable16_S : signal is "true";
+-- attribute mark_debug of rxDispError16_S : signal is "true";
+-- attribute mark_debug of txData : signal is "true";
+-- attribute mark_debug of txCharIsK : signal is "true";
+
+-- attribute mark_debug of gtpReset_S : signal is "true";
+-- attribute mark_debug of txResetdone_S : signal is "true";
+-- attribute mark_debug of rxResetDone_S : signal is "true";
+-- attribute mark_debug of pllLkDet_S : signal is "true";
+-- attribute mark_debug of rxReset_S : signal is "true";
+-- attribute mark_debug of rxLocked0_S : signal is "true";
+-- attribute mark_debug of rxLossOfSync1_S : signal is "true";
+-- attribute mark_debug of rxResetBitLock_S : signal is "true";
+-- attribute mark_debug of fsmStatus_S : signal is "true";
+-- attribute mark_debug of rxPLLwrapper_reset_S : signal is "true";
+-- attribute mark_debug of rxResetBitLock_pulse_S : signal is "true";
+-- attribute mark_debug of rxCDRlock_S : signal is "true";
+-- attribute mark_debug of CDR_reset_S : signal is "true";
+-- attribute mark_debug of disable_GTX_reset : signal is "true";
+
+		
+begin
+	resetDone <= rxResetDone_sysclk_S;
+	rxLocked <= rxLocked2_S;
+	txLocked <= rxResetDone_sysclk_S;	
+	rxUsrClkdiv2 <= ff_rxhalfclk;
+	txUsrClk <= ff_txfullclk;
+
+process(sysClk)
+variable resetDone_V : std_logic;
+begin
+	if rising_edge(sysClk) then
+		rxResetDone_sysclk_S <= resetDone_V;
+		resetDone_V := rxResetDone_S;
+	end if;
+end process;
+
+FEE_data8to16_1: FEE_data8to16
+	port map( 
+		clock_in => ff_txfullclk,
+		data_in => txData,
+		kchar_in => txCharIsK,
+		clock_out => ff_txhalfclk,
+		data_out => txData16_S,
+		kchar_out => txCharIsK16_S
+	);
+
+FEE_data16to8_1: FEE_data16to8 
+	port map(
+		clock_in => ff_rxhalfclk,
+		data_in => rxData16_S,
+		kchar_in => rxCharIsK16_S,
+		notintable_in => rxNotInTable16_S,
+		clock_out => rxUsrClk,
+		data_out => rxData_S,
+		kchar_out => rxCharIsK_S,
+		notintable_out => rxNotInTable_S
+	);
+rxData <= rxData_S;
+rxCharIsK <= rxCharIsK_S;
+rxNotInTable <= rxNotInTable_S;
+
+gtx_i : gtxKintex7FEE80_support 
+	port map(
+		SOFT_RESET_TX_IN => gtpReset_S,
+		SOFT_RESET_RX_IN => gtpReset_S,
+		DONT_RESET_ON_DATA_ERROR_IN => '1',
+		Q0_CLK0_GTREFCLK_PAD_N_IN => gtpClk_N,
+		Q0_CLK0_GTREFCLK_PAD_P_IN => gtpClk_P,
+
+		GT0_TX_FSM_RESET_DONE_OUT => open,
+		GT0_RX_FSM_RESET_DONE_OUT => open,
+		GT0_DATA_VALID_IN => '1', 
+		GT0_TX_MMCM_LOCK_OUT => open,
+
+		GT0_TXUSRCLK_OUT => open,
+		GT0_TXUSRCLK2_OUT => ff_txhalfclk, -- clock for tx_data (100MHz)
+		GT0_TXUSRCLKX2_OUT => ff_txfullclk, -- clock for 8 bits data (200MHz)
+		GT0_RXUSRCLK_OUT => open,
+		GT0_RXUSRCLK2_OUT => ff_rxhalfclk, -- clock for rx_data (100MHz)
+		--_________________________________________________________________________
+		--GT0  (X1Y0)
+		--____________________________CHANNEL PORTS________________________________
+		--------------------------------- CPLL Ports -------------------------------
+		gt0_cpllfbclklost_out => open,
+		gt0_cplllock_out => pllLkDet_S,
+		gt0_cpllreset_in => '0',
+		---------------------------- Channel - DRP Ports  --------------------------
+		gt0_drpaddr_in => drpaddr_in_S,
+		gt0_drpdi_in => drpdi_in_S,
+		gt0_drpdo_out => drpdo_out_S,
+		gt0_drpen_in => drpen_in_S,
+		gt0_drprdy_out => drprdy_out_S,
+		gt0_drpwe_in => drpwe_in_S,
+		--------------------------- Digital Monitor Ports --------------------------
+		gt0_dmonitorout_out => open,
+		--------------------- RX Initialization and Reset Ports --------------------
+		gt0_eyescanreset_in => '0',
+		gt0_rxuserrdy_in => '0',
+		-------------------------- RX Margin Analysis Ports ------------------------
+		gt0_eyescandataerror_out => open,
+		gt0_eyescantrigger_in => '0',
+		------------------------- Receive Ports - CDR Ports ------------------------
+		GT0_RXCDRRESET_IN => CDR_reset_S,
+		GT0_RXCDRLOCK_OUT => rxCDRlock_S,
+		------------------ Receive Ports - FPGA RX interface Ports -----------------
+		gt0_rxdata_out => rxData16_S,
+		------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+		gt0_rxdisperr_out => rxDispError16_S,
+		gt0_rxnotintable_out => rxNotInTable16_S,
+		--------------------------- Receive Ports - RX AFE -------------------------
+		gt0_gtxrxp_in => rxP,
+		------------------------ Receive Ports - RX AFE Ports ----------------------
+		gt0_gtxrxn_in => rxN,
+		------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+		gt0_rxphmonitor_out => open,
+		gt0_rxphslipmonitor_out => open,
+		--------------------- Receive Ports - RX Equalizer Ports -------------------
+		gt0_rxdfelpmreset_in => '0',
+		gt0_rxmonitorout_out => open,
+		gt0_rxmonitorsel_in => "00",
+		------------- Receive Ports - RX Initialization and Reset Ports ------------
+		gt0_gtrxreset_in => rxReset_S, 
+		gt0_rxpmareset_in => rxReset_S, 
+		------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+		gt0_rxcharisk_out => rxCharIsK16_S,
+		-------------- Receive Ports -RX Initialization and Reset Ports ------------
+		gt0_rxresetdone_out => rxResetDone_S,
+		--------------------- TX Initialization and Reset Ports --------------------
+		gt0_gttxreset_in => '0',
+		gt0_txuserrdy_in => '0',
+		------------------ Transmit Ports - TX Data Path interface -----------------
+		gt0_txdata_in => txData16_S,
+		---------------- Transmit Ports - TX Driver and OOB signaling --------------
+		gt0_gtxtxn_out => txN,
+		gt0_gtxtxp_out => txP,
+		----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+		gt0_txoutclkfabric_out => open,
+		gt0_txoutclkpcs_out => open,
+		--------------------- Transmit Ports - TX Gearbox Ports --------------------
+		gt0_txcharisk_in => txCharIsK16_S,
+		------------- Transmit Ports - TX Initialization and Reset Ports -----------
+		gt0_txresetdone_out => txResetdone_S,
+		--____________________________COMMON PORTS________________________________
+		GT0_QPLLOUTCLK_IN => GT0_QPLLOUTCLK_IN,
+		GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN,
+		sysclk_in  => sysClk,
+		refclk_out => refclk_out --// Modified
+	);
+
+
+rxLossOfSync1_S <= '0' when (rxNotInTable16_S="00") or (disable_GTX_reset='1') else '1';
+FEE_rxBitLock1 : FEE_rxBitLock port map (
+		clk => ff_rxhalfclk,
+		reset => gtpReset_S,
+		resetDone => rxResetDone_S,
+		lossOfSync => rxLossOfSync1_S,
+		rxPllLocked => PllLkDet_S,
+		rxReset => rxResetBitLock_S,
+		fsmStatus => fsmStatus_S
+	);
+
+		
+process(sysClk,gtpReset)
+variable counter_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+	if gtpReset='1' then
+		gtpReset_S	<= '1';
+		counter_V := (others => '0');
+	elsif rising_edge(sysClk) then
+		gtpReset_S	<= '0';
+		if counter_V(counter_V'left)='1' then
+			if rxResetDone_S='0' then
+				counter_V := (others => '0');
+				gtpReset_S	<= '1';
+			end if;
+		else
+			counter_V := counter_V+1;
+		end if;
+	end if;
+end process;
+
+---- rxReset_S <= gtpReset;
+rxReset_S <= '1' when ((rxPLLwrapper_reset_S='1') or (gtpReset_S='1') or (rxResetBitLock_pulse_S='1')) and (disable_GTX_reset='0') else '0';
+rxLocked0_S <= '1' when (rxResetDone_S='1') and (fsmStatus_S = "10") else '0';
+
+		
+process(SYSCLK) 
+begin
+	if rising_edge(SYSCLK) then
+		if (sync_rxResetBitLock_S='1') and (prev_rxResetBitLock_S='0') then
+			rxResetBitLock_pulse_S <= '1';
+		else	
+			rxResetBitLock_pulse_S <= '0';
+		end if;
+		sync_rxResetBitLock_S <= rxResetBitLock_S;
+		prev_rxResetBitLock_S <= sync_rxResetBitLock_S;
+	end if;
+end process;
+
+process(sysClk) 
+variable counter_V : std_logic_vector(5 downto 0) := (others => '0');
+variable timoutcounter_V : std_logic_vector(7 downto 0) := (others => '0');
+begin
+	if rising_edge(sysClk) then
+		rxPLLwrapper_reset_S <= '0';
+		CDR_reset_S <= '0';
+		comma_align_latency_valid_S <= '0';
+		drpen_in_S <= '0';
+		drpwe_in_S <= '0';
+		drpdi_in_S <= (others => '0');
+		case drp_state_S is
+			when initting =>
+				rxLocked2_S	<= '0';
+				counter_V := (others => '0');
+				if rxResetDone_S='1' then
+					drp_state_S <= running;
+				end if;
+			when running =>
+				if rxLocked1_S='0' then
+					drp_state_S <= initting;
+				else
+					if counter_V(counter_V'left) = '1' then
+						counter_V := (others => '0');
+						timoutcounter_V := (others => '0');
+						drpen_in_S <= '1';
+						drpaddr_in_S <= "101001110"; -- x"14E";
+						drp_state_S <= reading;
+					else
+						counter_V := counter_V+1;
+					end if;
+				end if;
+			when reading =>
+				if drprdy_out_S='1' then
+					comma_align_latency_S <= drpdo_out_S(6 downto 0); --		COMMA_ALIGN_LATENCY
+					comma_align_latency_valid_S <= '1';
+					if drpdo_out_S(6 downto 0)/="0000000" then
+						CDR_reset_S <= '1'; --// rxPLLwrapper_reset_S <= '1';
+						rxLocked2_S	<= '0';
+					else 
+						rxLocked2_S	<= '1';
+					end if;
+					drp_state_S <= running;
+				elsif timoutcounter_V(timoutcounter_V'left)='1' then
+					drp_state_S <= initting;
+				else
+					timoutcounter_V := timoutcounter_V+1;
+				end if;
+			when others =>
+				drp_state_S <= initting;
+		end case;
+		rxLocked1_S <= rxLocked0_S;
+	end if;
+end process;
+
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/gtx_common.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/gtx_common.vhd
new file mode 100644
index 0000000..6e74759
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/gtx_common.vhd
@@ -0,0 +1,251 @@
+---------------------------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtxkintex7fee80_common.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_common 
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+
+
+--***************************** Entity Declaration ****************************
+entity gtx_common is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE";        -- Set to "true" to speed up sim reset 
+    SIM_QPLLREFCLK_SEL              : bit_vector :=  "001"
+);
+port
+(
+    QPLLREFCLKSEL_IN  : in std_logic_vector(2 downto 0);
+    GTREFCLK1_IN      : in std_logic;
+    GTREFCLK0_IN : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+);
+
+end gtx_common;
+    
+architecture RTL of gtx_common is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "gtx_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+    impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return "0000100000";
+       elsif (qpllfbdiv_top = 20) then
+         return "0000110000" ;
+       elsif (qpllfbdiv_top = 32) then
+         return "0001100000" ;
+       elsif (qpllfbdiv_top = 40) then
+         return "0010000000" ;
+       elsif (qpllfbdiv_top = 64) then
+         return "0011100000" ;
+       elsif (qpllfbdiv_top = 66) then
+         return "0101000000" ;
+       elsif (qpllfbdiv_top = 80) then
+         return "0100100000" ;
+       elsif (qpllfbdiv_top = 100) then
+         return "0101110000" ;
+       else 
+         return "0000000000" ;
+       end if;
+    end function;
+
+    impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return '1';
+       elsif (qpllfbdiv_top = 20) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 32) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 40) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 64) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 66) then
+         return '0' ;
+       elsif (qpllfbdiv_top = 80) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 100) then
+         return '1' ;
+       else 
+         return '1' ;
+       end if;
+    end function;
+
+    constant   QPLL_FBDIV_TOP   : integer  := 40;
+    constant   QPLL_FBDIV_IN    :   bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+    constant   QPLL_FBDIV_RATIO :   bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal  tied_to_vcc_vec_i               :   std_logic_vector(63 downto 0);
+
+begin
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    tied_to_vcc_vec_i(63 downto 0)      <= (others => '1');
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTXE2_COMMON____________________________________
+
+    gtxe2_common_i : GTXE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_QPLLREFCLK_SEL   => (SIM_QPLLREFCLK_SEL),
+            SIM_VERSION          => "4.0",
+
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000040000001000"),
+        COMMON_CFG                              =>     (x"00000000"),
+        QPLL_CFG                                =>     (x"06801C1"),
+        QPLL_CLKOUT_CFG                         =>     ("0000"),
+        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
+        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
+        QPLL_CP                                 =>     ("0000011111"),
+        QPLL_CP_MONITOR_EN                      =>     ('0'),
+        QPLL_DMONITOR_SEL                       =>     ('0'),
+        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
+        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
+        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
+        QPLL_INIT_CFG                           =>     (x"000006"),
+        QPLL_LOCK_CFG                           =>     (x"21E8"),
+        QPLL_LPF                                =>     ("1111"),
+        QPLL_REFCLK_DIV                         =>     (1)
+
+        
+    )
+    port map
+    (
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      GTREFCLK1_IN,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ------------------------- Common Block -  QPLL Ports -----------------------
+        QPLLDMONITOR                    =>      open,
+        ----------------------- Common Block - Clocking Ports ----------------------
+        QPLLOUTCLK                      =>      QPLLOUTCLK_OUT,
+        QPLLOUTREFCLK                   =>      QPLLOUTREFCLK_OUT,
+        REFCLKOUTMONITOR                =>      open,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        QPLLFBCLKLOST                   =>      open,
+        QPLLLOCK                        =>      QPLLLOCK_OUT,
+        QPLLLOCKDETCLK                  =>      QPLLLOCKDETCLK_IN,
+        QPLLLOCKEN                      =>      tied_to_vcc_i,
+        QPLLOUTRESET                    =>      tied_to_ground_i,
+        QPLLPD                          =>      tied_to_vcc_i,
+        QPLLREFCLKLOST                  =>      QPLLREFCLKLOST_OUT,
+        QPLLREFCLKSEL                   =>      QPLLREFCLKSEL_IN,
+        QPLLRESET                       =>      QPLLRESET_IN,
+        QPLLRSVD1                       =>      "0000000000000000",
+        QPLLRSVD2                       =>      "11111",
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "11111",
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+end RTL;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80.vhd
new file mode 100644
index 0000000..a46be17
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80.vhd
@@ -0,0 +1,584 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 2.6
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtxkintex7fee80.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80 (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+
+entity gtxKintex7FEE80 is
+generic
+(
+    QPLL_FBDIV_TOP                 : integer  := 16;
+
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE";        -- Set to "true" to speed up sim reset
+    RX_DFE_KL_CFG2_IN               : bit_vector :=  X"301148AC";
+    PMA_RSV_IN                      : bit_vector :=  x"00018480"
+
+);
+port
+(
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X0Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    GT0_CPLLFBCLKLOST_OUT                   : out  std_logic;
+    GT0_CPLLLOCK_OUT                        : out  std_logic;
+    GT0_CPLLLOCKDETCLK_IN                   : in   std_logic;
+    GT0_CPLLREFCLKLOST_OUT                  : out  std_logic;
+    GT0_CPLLRESET_IN                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    GT0_GTREFCLK0_IN                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    GT0_DRPADDR_IN                          : in   std_logic_vector(8 downto 0);
+    GT0_DRPCLK_IN                           : in   std_logic;
+    GT0_DRPDI_IN                            : in   std_logic_vector(15 downto 0);
+    GT0_DRPDO_OUT                           : out  std_logic_vector(15 downto 0);
+    GT0_DRPEN_IN                            : in   std_logic;
+    GT0_DRPRDY_OUT                          : out  std_logic;
+    GT0_DRPWE_IN                            : in   std_logic;
+    --------------------- RX Initialization and Reset Ports --------------------
+    GT0_RXUSERRDY_IN                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    GT0_EYESCANDATAERROR_OUT                : out  std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	 GT0_RXCDRRESET_IN                       : in  std_logic;
+    GT0_RXCDRLOCK_OUT                       : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    GT0_RXUSRCLK_IN                         : in   std_logic;
+    GT0_RXUSRCLK2_IN                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    GT0_RXDATA_OUT                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    GT0_RXDISPERR_OUT                       : out  std_logic_vector(1 downto 0);
+    GT0_RXNOTINTABLE_OUT                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    GT0_GTXRXP_IN                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GT0_GTXRXN_IN                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    GT0_RXDLYEN_IN                          : in   std_logic;
+    GT0_RXDLYSRESET_IN                      : in   std_logic;
+    GT0_RXDLYSRESETDONE_OUT                 : out  std_logic;
+    GT0_RXPHALIGN_IN                        : in   std_logic;
+    GT0_RXPHALIGNDONE_OUT                   : out  std_logic;
+    GT0_RXPHALIGNEN_IN                      : in   std_logic;
+    GT0_RXPHDLYRESET_IN                     : in   std_logic;
+    GT0_RXPHMONITOR_OUT                     : out  std_logic_vector(4 downto 0);
+    GT0_RXPHSLIPMONITOR_OUT                 : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    GT0_RXLPMHFHOLD_IN                      : in   std_logic;
+    GT0_RXLPMLFHOLD_IN                      : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    GT0_RXOUTCLK_OUT                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GT0_GTRXRESET_IN                        : in   std_logic;
+    GT0_RXPCSRESET_IN                       : in   std_logic;
+    GT0_RXPMARESET_IN                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    GT0_RXCHARISK_OUT                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    GT0_RXRESETDONE_OUT                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GT0_GTTXRESET_IN                        : in   std_logic;
+    GT0_TXUSERRDY_IN                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    GT0_TXUSRCLK_IN                         : in   std_logic;
+    GT0_TXUSRCLK2_IN                        : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    GT0_TXDLYEN_IN                          : in   std_logic;
+    GT0_TXDLYSRESET_IN                      : in   std_logic;
+    GT0_TXDLYSRESETDONE_OUT                 : out  std_logic;
+    GT0_TXPHALIGN_IN                        : in   std_logic;
+    GT0_TXPHALIGNDONE_OUT                   : out  std_logic;
+    GT0_TXPHALIGNEN_IN                      : in   std_logic;
+    GT0_TXPHDLYRESET_IN                     : in   std_logic;
+    GT0_TXPHINIT_IN                         : in   std_logic;
+    GT0_TXPHINITDONE_OUT                    : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    GT0_TXDATA_IN                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    GT0_GTXTXN_OUT                          : out  std_logic;
+    GT0_GTXTXP_OUT                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    GT0_TXOUTCLK_OUT                        : out  std_logic;
+    GT0_TXOUTCLKFABRIC_OUT                  : out  std_logic;
+    GT0_TXOUTCLKPCS_OUT                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    GT0_TXCHARISK_IN                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    GT0_TXRESETDONE_OUT                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+    ---------------------- Common Block  - Ref Clock Ports ---------------------
+    GT0_GTREFCLK0_COMMON_IN                 : in   std_logic;
+    ------------------------- Common Block - QPLL Ports ------------------------
+    GT0_QPLLLOCK_OUT                        : out  std_logic;
+    GT0_QPLLLOCKDETCLK_IN                   : in   std_logic;
+    GT0_QPLLREFCLKLOST_OUT                  : out  std_logic;
+    GT0_QPLLRESET_IN                        : in   std_logic
+
+
+);
+
+
+end gtxKintex7FEE80;
+    
+architecture RTL of gtxKintex7FEE80 is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80,gtwizard_v2_6,{protocol_file=Start_from_scratch}";
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--***************************** Signal Declarations *****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal   gt0_qplloutclk_i         :   std_logic;
+    signal   gt0_qplloutrefclk_i      :   std_logic;
+
+  
+    signal  gt0_mgtrefclktx_i           :   std_logic_vector(1 downto 0);
+    signal  gt0_mgtrefclkrx_i           :   std_logic_vector(1 downto 0);
+  
+ 
+    signal   gt0_qpllclk_i            :   std_logic;
+    signal   gt0_qpllrefclk_i         :   std_logic;
+
+
+--*************************** Component Declarations **************************
+component gtxKintex7FEE80_GT
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP       : string   := "FALSE";
+    RX_DFE_KL_CFG2_IN            : bit_vector :=   X"3010D90C";
+    PMA_RSV_IN                   : bit_vector :=   X"00000000";
+    PCS_RSVD_ATTR_IN             : bit_vector :=   X"000000000000"
+);
+port 
+(   
+    --------------------------------- CPLL Ports -------------------------------
+    CPLLFBCLKLOST_OUT                       : out  std_logic;
+    CPLLLOCK_OUT                            : out  std_logic;
+    CPLLLOCKDETCLK_IN                       : in   std_logic;
+    CPLLREFCLKLOST_OUT                      : out  std_logic;
+    CPLLRESET_IN                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    GTREFCLK0_IN                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
+    DRPCLK_IN                               : in   std_logic;
+    DRPDI_IN                                : in   std_logic_vector(15 downto 0);
+    DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
+    DRPEN_IN                                : in   std_logic;
+    DRPRDY_OUT                              : out  std_logic;
+    DRPWE_IN                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    QPLLCLK_IN                              : in   std_logic;
+    QPLLREFCLK_IN                           : in   std_logic;
+    --------------------- RX Initialization and Reset Ports --------------------
+    RXUSERRDY_IN                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    EYESCANDATAERROR_OUT                    : out  std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	 RXCDRRESET_IN                           : in  std_logic;
+    RXCDRLOCK_OUT                           : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    RXUSRCLK_IN                             : in   std_logic;
+    RXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    RXDATA_OUT                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    RXDISPERR_OUT                           : out  std_logic_vector(1 downto 0);
+    RXNOTINTABLE_OUT                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    GTXRXP_IN                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GTXRXN_IN                               : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    RXDLYEN_IN                              : in   std_logic;
+    RXDLYSRESET_IN                          : in   std_logic;
+    RXDLYSRESETDONE_OUT                     : out  std_logic;
+    RXPHALIGN_IN                            : in   std_logic;
+    RXPHALIGNDONE_OUT                       : out  std_logic;
+    RXPHALIGNEN_IN                          : in   std_logic;
+    RXPHDLYRESET_IN                         : in   std_logic;
+    RXPHMONITOR_OUT                         : out  std_logic_vector(4 downto 0);
+    RXPHSLIPMONITOR_OUT                     : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    RXLPMHFHOLD_IN                          : in   std_logic;
+    RXLPMLFHOLD_IN                          : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    RXOUTCLK_OUT                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GTRXRESET_IN                            : in   std_logic;
+    RXPCSRESET_IN                           : in   std_logic;
+    RXPMARESET_IN                           : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    RXCHARISK_OUT                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    RXRESETDONE_OUT                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GTTXRESET_IN                            : in   std_logic;
+    TXUSERRDY_IN                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    TXUSRCLK_IN                             : in   std_logic;
+    TXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    TXDLYEN_IN                              : in   std_logic;
+    TXDLYSRESET_IN                          : in   std_logic;
+    TXDLYSRESETDONE_OUT                     : out  std_logic;
+    TXPHALIGN_IN                            : in   std_logic;
+    TXPHALIGNDONE_OUT                       : out  std_logic;
+    TXPHALIGNEN_IN                          : in   std_logic;
+    TXPHDLYRESET_IN                         : in   std_logic;
+    TXPHINIT_IN                             : in   std_logic;
+    TXPHINITDONE_OUT                        : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    TXDATA_IN                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    GTXTXN_OUT                              : out  std_logic;
+    GTXTXP_OUT                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    TXOUTCLK_OUT                            : out  std_logic;
+    TXOUTCLKFABRIC_OUT                      : out  std_logic;
+    TXOUTCLKPCS_OUT                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    TXCHARISK_IN                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    TXRESETDONE_OUT                         : out  std_logic
+
+
+);
+end component;
+
+
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+    impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return "0000100000";
+       elsif (qpllfbdiv_top = 20) then
+         return "0000110000" ;
+       elsif (qpllfbdiv_top = 32) then
+         return "0001100000" ;
+       elsif (qpllfbdiv_top = 40) then
+         return "0010000000" ;
+       elsif (qpllfbdiv_top = 64) then
+         return "0011100000" ;
+       elsif (qpllfbdiv_top = 66) then
+         return "0101000000" ;
+       elsif (qpllfbdiv_top = 80) then
+         return "0100100000" ;
+       elsif (qpllfbdiv_top = 100) then
+         return "0101110000" ;
+       else 
+         return "0000000000" ;
+       end if;
+    end function;
+
+    impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return '1';
+       elsif (qpllfbdiv_top = 20) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 32) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 40) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 64) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 66) then
+         return '0' ;
+       elsif (qpllfbdiv_top = 80) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 100) then
+         return '1' ;
+       else 
+         return '1' ;
+       end if;
+    end function;
+
+    constant   QPLL_FBDIV_IN    :   bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+    constant   QPLL_FBDIV_RATIO :   bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+--********************************* Main Body of Code**************************
+
+begin                       
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    gt0_qpllclk_i    <= gt0_qplloutclk_i;  
+    gt0_qpllrefclk_i <= gt0_qplloutrefclk_i; 
+
+
+ 
+    --------------------------- GT Instances  -------------------------------   
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X0Y0)
+
+    gt0_gtxKintex7FEE80_i : gtxKintex7FEE80_GT
+    generic map
+    (
+        -- Simulation attributes
+        GT_SIM_GTRESET_SPEEDUP        =>  WRAPPER_SIM_GTRESET_SPEEDUP,
+        RX_DFE_KL_CFG2_IN             =>  RX_DFE_KL_CFG2_IN,
+        PMA_RSV_IN                    =>  PMA_RSV_IN,
+        PCS_RSVD_ATTR_IN              =>  X"000000000006"
+    )
+    port map
+    (
+        --------------------------------- CPLL Ports -------------------------------
+        CPLLFBCLKLOST_OUT               =>      GT0_CPLLFBCLKLOST_OUT,
+        CPLLLOCK_OUT                    =>      GT0_CPLLLOCK_OUT,
+        CPLLLOCKDETCLK_IN               =>      GT0_CPLLLOCKDETCLK_IN,
+        CPLLREFCLKLOST_OUT              =>      GT0_CPLLREFCLKLOST_OUT,
+        CPLLRESET_IN                    =>      GT0_CPLLRESET_IN,
+        -------------------------- Channel - Clocking Ports ------------------------
+        GTREFCLK0_IN                    =>      GT0_GTREFCLK0_IN,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR_IN                      =>      GT0_DRPADDR_IN,
+        DRPCLK_IN                       =>      GT0_DRPCLK_IN,
+        DRPDI_IN                        =>      GT0_DRPDI_IN,
+        DRPDO_OUT                       =>      GT0_DRPDO_OUT,
+        DRPEN_IN                        =>      GT0_DRPEN_IN,
+        DRPRDY_OUT                      =>      GT0_DRPRDY_OUT,
+        DRPWE_IN                        =>      GT0_DRPWE_IN,
+        ------------------------------- Clocking Ports -----------------------------
+        QPLLCLK_IN                      =>      gt0_qpllclk_i,
+        QPLLREFCLK_IN                   =>      gt0_qpllrefclk_i,
+        --------------------- RX Initialization and Reset Ports --------------------
+        RXUSERRDY_IN                    =>      GT0_RXUSERRDY_IN,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR_OUT            =>      GT0_EYESCANDATAERROR_OUT,
+        ------------------------- Receive Ports - CDR Ports ------------------------
+		  RXCDRRESET_IN                   =>      GT0_RXCDRRESET_IN,
+        RXCDRLOCK_OUT                   =>      GT0_RXCDRLOCK_OUT,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXUSRCLK_IN                     =>      GT0_RXUSRCLK_IN,
+        RXUSRCLK2_IN                    =>      GT0_RXUSRCLK2_IN,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        RXDATA_OUT                      =>      GT0_RXDATA_OUT,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXDISPERR_OUT                   =>      GT0_RXDISPERR_OUT,
+        RXNOTINTABLE_OUT                =>      GT0_RXNOTINTABLE_OUT,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        GTXRXP_IN                       =>      GT0_GTXRXP_IN,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTXRXN_IN                       =>      GT0_GTXRXN_IN,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        RXDLYEN_IN                      =>      GT0_RXDLYEN_IN,
+        RXDLYSRESET_IN                  =>      GT0_RXDLYSRESET_IN,
+        RXDLYSRESETDONE_OUT             =>      GT0_RXDLYSRESETDONE_OUT,
+        RXPHALIGN_IN                    =>      GT0_RXPHALIGN_IN,
+        RXPHALIGNDONE_OUT               =>      GT0_RXPHALIGNDONE_OUT,
+        RXPHALIGNEN_IN                  =>      GT0_RXPHALIGNEN_IN,
+        RXPHDLYRESET_IN                 =>      GT0_RXPHDLYRESET_IN,
+        RXPHMONITOR_OUT                 =>      GT0_RXPHMONITOR_OUT,
+        RXPHSLIPMONITOR_OUT             =>      GT0_RXPHSLIPMONITOR_OUT,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        RXLPMHFHOLD_IN                  =>      GT0_RXLPMHFHOLD_IN,
+        RXLPMLFHOLD_IN                  =>      GT0_RXLPMLFHOLD_IN,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK_OUT                    =>      GT0_RXOUTCLK_OUT,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET_IN                    =>      GT0_GTRXRESET_IN,
+        RXPCSRESET_IN                   =>      GT0_RXPCSRESET_IN,
+        RXPMARESET_IN                   =>      GT0_RXPMARESET_IN,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        RXCHARISK_OUT                   =>      GT0_RXCHARISK_OUT,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE_OUT                 =>      GT0_RXRESETDONE_OUT,
+        --------------------- TX Initialization and Reset Ports --------------------
+        GTTXRESET_IN                    =>      GT0_GTTXRESET_IN,
+        TXUSERRDY_IN                    =>      GT0_TXUSERRDY_IN,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXUSRCLK_IN                     =>      GT0_TXUSRCLK_IN,
+        TXUSRCLK2_IN                    =>      GT0_TXUSRCLK2_IN,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        TXDLYEN_IN                      =>      GT0_TXDLYEN_IN,
+        TXDLYSRESET_IN                  =>      GT0_TXDLYSRESET_IN,
+        TXDLYSRESETDONE_OUT             =>      GT0_TXDLYSRESETDONE_OUT,
+        TXPHALIGN_IN                    =>      GT0_TXPHALIGN_IN,
+        TXPHALIGNDONE_OUT               =>      GT0_TXPHALIGNDONE_OUT,
+        TXPHALIGNEN_IN                  =>      GT0_TXPHALIGNEN_IN,
+        TXPHDLYRESET_IN                 =>      GT0_TXPHDLYRESET_IN,
+        TXPHINIT_IN                     =>      GT0_TXPHINIT_IN,
+        TXPHINITDONE_OUT                =>      GT0_TXPHINITDONE_OUT,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        TXDATA_IN                       =>      GT0_TXDATA_IN,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        GTXTXN_OUT                      =>      GT0_GTXTXN_OUT,
+        GTXTXP_OUT                      =>      GT0_GTXTXP_OUT,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK_OUT                    =>      GT0_TXOUTCLK_OUT,
+        TXOUTCLKFABRIC_OUT              =>      GT0_TXOUTCLKFABRIC_OUT,
+        TXOUTCLKPCS_OUT                 =>      GT0_TXOUTCLKPCS_OUT,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        TXCHARISK_IN                    =>      GT0_TXCHARISK_IN,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXRESETDONE_OUT                 =>      GT0_TXRESETDONE_OUT
+
+    );
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTXE2_COMMON____________________________________
+
+    gtxe2_common_0_i : GTXE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_QPLLREFCLK_SEL   => ("001"),
+            SIM_VERSION          => "4.0",
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000040000001000"),
+        COMMON_CFG                              =>     (x"00000000"),
+        QPLL_CFG                                =>     (x"06801C1"),
+        QPLL_CLKOUT_CFG                         =>     ("0000"),
+        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
+        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
+        QPLL_CP                                 =>     ("0000011111"),
+        QPLL_CP_MONITOR_EN                      =>     ('0'),
+        QPLL_DMONITOR_SEL                       =>     ('0'),
+        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
+        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
+        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
+        QPLL_INIT_CFG                           =>     (x"000006"),
+        QPLL_LOCK_CFG                           =>     (x"21E8"),
+        QPLL_LPF                                =>     ("1111"),
+        QPLL_REFCLK_DIV                         =>     (1)
+
+        
+    )
+    port map
+    (
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GT0_GTREFCLK0_COMMON_IN,
+        GTREFCLK1                       =>      tied_to_ground_i,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ------------------------- Common Block -  QPLL Ports -----------------------
+        QPLLDMONITOR                    =>      open,
+        ----------------------- Common Block - Clocking Ports ----------------------
+        QPLLOUTCLK                      =>      gt0_qplloutclk_i,
+        QPLLOUTREFCLK                   =>      gt0_qplloutrefclk_i,
+        REFCLKOUTMONITOR                =>      open,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        QPLLFBCLKLOST                   =>      open,
+        QPLLLOCK                        =>      GT0_QPLLLOCK_OUT,
+        QPLLLOCKDETCLK                  =>      GT0_QPLLLOCKDETCLK_IN,
+        QPLLLOCKEN                      =>      tied_to_vcc_i,
+        QPLLOUTRESET                    =>      tied_to_ground_i,
+        QPLLPD                          =>      tied_to_ground_i,
+        QPLLREFCLKLOST                  =>      GT0_QPLLREFCLKLOST_OUT,
+        QPLLREFCLKSEL                   =>      "001",
+        QPLLRESET                       =>      GT0_QPLLRESET_IN,
+        QPLLRSVD1                       =>      "0000000000000000",
+        QPLLRSVD2                       =>      "11111",
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "00000",
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+
+     
+end RTL;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_auto_phase_align.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_auto_phase_align.vhd
new file mode 100644
index 0000000..1781690
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_auto_phase_align.vhd
@@ -0,0 +1,202 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 2.6
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename : gtxkintex7fee80_auto_phase_align.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--  Description : The logic below implements the procedure to do automatic phase-alignment 
+--                on the 7-series GTX as described in ug476pdf, version 1.3,
+--                Chapters "Using the TX Phase Alignment to Bypass the TX Buffer"
+--                and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer"
+--                Should the logic below differ from what is described in a later version  
+--                of the user-guide, you are using an auto-alignment block, which is 
+--                out of date and needs to be updated for safe operation.
+--                     
+--
+--
+-- Module gtxKintex7FEE80_AUTO_PHASE_ALIGN
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxKintex7FEE80_AUTO_PHASE_ALIGN is     
+  Generic( 
+           GT_TYPE                  : string  := "GTX"
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RUN_PHALIGNMENT          : in  STD_LOGIC;              --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Auto phase-alignment performed sucessfully
+           PHALIGNDONE              : in  STD_LOGIC;              --\ Phase-alignment signals from and to the
+           DLYSRESET                : out STD_LOGIC;              -- |transceiver.
+           DLYSRESETDONE            : in  STD_LOGIC;              --/
+           RECCLKSTABLE             : in  STD_LOGIC               --/on the RX-side.
+           
+           );
+end gtxKintex7FEE80_AUTO_PHASE_ALIGN;
+
+architecture RTL of gtxKintex7FEE80_AUTO_PHASE_ALIGN is
+
+  component gtxKintex7FEE80_sync_block
+   generic (
+     INITIALISE : bit_vector(1 downto 0) := "00"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+  type phase_align_auto_fsm is(
+    INIT, WAIT_PHRST_DONE, COUNT_PHALIGN_DONE, PHALIGN_DONE
+    );
+    
+  signal phalign_state       : phase_align_auto_fsm := INIT;
+  signal phaligndone_prev     : std_logic := '0';
+  signal phaligndone_ris_edge : std_logic;
+
+  signal count_phalign_edges   : integer range 0 to 3:= 0;
+  signal phaligndone_sync      : std_logic := '0';
+  signal dlysresetdone_sync    : std_logic := '0';
+
+begin
+
+ sync_PHALIGNDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  PHALIGNDONE,
+            data_out        =>  phaligndone_sync 
+         );
+
+  sync_DLYSRESETDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  DLYSRESETDONE,
+            data_out        =>  dlysresetdone_sync 
+         );
+
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      phaligndone_prev <= phaligndone_sync; 
+    end if;
+  end process;
+  phaligndone_ris_edge <= '1' when (phaligndone_prev = '0') and (phaligndone_sync = '1') else '0';
+  
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if RUN_PHALIGNMENT = '0' or RECCLKSTABLE = '0' then
+        DLYSRESET           <= '0';
+        count_phalign_edges   <= 0;
+        PHASE_ALIGNMENT_DONE  <= '0';
+        phalign_state      <= INIT;
+      else
+        if phaligndone_ris_edge = '1' then
+          if count_phalign_edges < 3 then
+            count_phalign_edges <= count_phalign_edges + 1;
+          end if;
+        end if;
+        
+        DLYSRESET         <= '0';
+                  
+        case phalign_state is
+          when INIT => 
+            PHASE_ALIGNMENT_DONE <= '0';
+            if RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1' then
+              --DLYSRESET is toggled to '1'
+              DLYSRESET  <= '1';
+              phalign_state <= WAIT_PHRST_DONE;
+            end if;           
+            
+          when WAIT_PHRST_DONE =>
+            if dlysresetdone_sync = '1' then
+              phalign_state <= COUNT_PHALIGN_DONE;
+            end if;
+            --No timeout-check here as that is done in the main FSM
+            
+          when COUNT_PHALIGN_DONE =>
+            if ((GT_TYPE = "GTX" and count_phalign_edges = 2) or ((GT_TYPE = "GTH" or GT_TYPE = "GTP") and phaligndone_ris_edge = '1')) then
+              --For GTX: Only on the second edge of the PHALIGNDONE-signal the 
+              --         phase-alignment is completed
+              --For GTH, GTP: TXSYNCDONE indicates the completion of Phase Alignment
+
+              phalign_state <= PHALIGN_DONE;
+            end if;
+          
+          when PHALIGN_DONE =>
+            PHASE_ALIGNMENT_DONE <= '1';
+
+          when OTHERS =>
+            phalign_state      <= INIT;
+
+        end case;        
+      end if;      
+    end if;    
+  end process;
+
+end RTL;
+
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_clock_module.vhd
similarity index 73%
rename from FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.vhd
rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_clock_module.vhd
index ccf25dc..e908bb5 100644
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.vhd
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_clock_module.vhd
@@ -1,233 +1,242 @@
--- file: clockmodule80to80M.vhd
--- 
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- None
---
-------------------------------------------------------------------------------
--- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
--- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
-------------------------------------------------------------------------------
--- CLK_OUT1____40.000______0.000______50.0______174.629____114.212
--- CLK_OUT2____80.000______0.000______50.0______151.652____114.212
--- CLK_OUT3___100.000______0.000______50.0______144.719____114.212
--- CLK_OUT4___200.000______0.000______50.0______126.455____114.212
---
-------------------------------------------------------------------------------
--- "Input Clock   Freq (MHz)    Input Jitter (UI)"
-------------------------------------------------------------------------------
--- __primary_____________100____________0.010
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-use ieee.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity clockmodule80to80M is
-port
- (-- Clock in ports
-  CLK_IN1           : in     std_logic;
-  -- Clock out ports
-  CLK_OUT1          : out    std_logic;
-  CLK_OUT2          : out    std_logic;
-  CLK_OUT3          : out    std_logic;
-  CLK_OUT4          : out    std_logic;
-  -- Status and control signals
-  RESET             : in     std_logic;
-  LOCKED            : out    std_logic
- );
-end clockmodule80to80M;
-
-architecture xilinx of clockmodule80to80M is
-  attribute CORE_GENERATION_INFO : string;
-  attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule80to80M,clk_wiz_v3_6,{component_name=clockmodule80to80M,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-  -- Input clock buffering / unused connectors
-  signal clkin1      : std_logic;
-  -- Output clock buffering / unused connectors
-  signal clkfbout         : std_logic;
-  signal clkfbout_buf     : std_logic;
-  signal clkfboutb_unused : std_logic;
-  signal clkout0          : std_logic;
-  signal clkout0b_unused  : std_logic;
-  signal clkout1          : std_logic;
-  signal clkout1b_unused  : std_logic;
-  signal clkout2          : std_logic;
-  signal clkout2b_unused  : std_logic;
-  signal clkout3          : std_logic;
-  signal clkout3b_unused  : std_logic;
-  signal clkout4_unused   : std_logic;
-  signal clkout5_unused   : std_logic;
-  signal clkout6_unused   : std_logic;
-  -- Dynamic programming unused signals
-  signal do_unused        : std_logic_vector(15 downto 0);
-  signal drdy_unused      : std_logic;
-  -- Dynamic phase shift unused signals
-  signal psdone_unused    : std_logic;
-  -- Unused status signals
-  signal clkfbstopped_unused : std_logic;
-  signal clkinstopped_unused : std_logic;
-begin
-
-
-  -- Input buffering
-  --------------------------------------
-  clkin1 <= CLK_IN1;
-
-
-  -- Clocking primitive
-  --------------------------------------
-  -- Instantiation of the MMCM primitive
-  --    * Unused inputs are tied off
-  --    * Unused outputs are labeled unused
-  mmcm_adv_inst : MMCM_ADV
-  generic map
-   (BANDWIDTH            => "OPTIMIZED",
-    CLKOUT4_CASCADE      => FALSE,
-    CLOCK_HOLD           => FALSE,
-    COMPENSATION         => "ZHOLD",
-    STARTUP_WAIT         => FALSE,
-    DIVCLK_DIVIDE        => 1,
-    CLKFBOUT_MULT_F      => 8.000,
-    CLKFBOUT_PHASE       => 0.000,
-    CLKFBOUT_USE_FINE_PS => FALSE,
-    CLKOUT0_DIVIDE_F     => 20.000,
-    CLKOUT0_PHASE        => 0.000,
-    CLKOUT0_DUTY_CYCLE   => 0.500,
-    CLKOUT0_USE_FINE_PS  => FALSE,
-    CLKOUT1_DIVIDE       => 10,
-    CLKOUT1_PHASE        => 0.000,
-    CLKOUT1_DUTY_CYCLE   => 0.500,
-    CLKOUT1_USE_FINE_PS  => FALSE,
-    CLKOUT2_DIVIDE       => 8,
-    CLKOUT2_PHASE        => 0.000,
-    CLKOUT2_DUTY_CYCLE   => 0.500,
-    CLKOUT2_USE_FINE_PS  => FALSE,
-    CLKOUT3_DIVIDE       => 4,
-    CLKOUT3_PHASE        => 0.000,
-    CLKOUT3_DUTY_CYCLE   => 0.500,
-    CLKOUT3_USE_FINE_PS  => FALSE,
-    CLKIN1_PERIOD        => 10.000,
-    REF_JITTER1          => 0.010)
-  port map
-    -- Output clocks
-   (CLKFBOUT            => clkfbout,
-    CLKFBOUTB           => clkfboutb_unused,
-    CLKOUT0             => clkout0,
-    CLKOUT0B            => clkout0b_unused,
-    CLKOUT1             => clkout1,
-    CLKOUT1B            => clkout1b_unused,
-    CLKOUT2             => clkout2,
-    CLKOUT2B            => clkout2b_unused,
-    CLKOUT3             => clkout3,
-    CLKOUT3B            => clkout3b_unused,
-    CLKOUT4             => clkout4_unused,
-    CLKOUT5             => clkout5_unused,
-    CLKOUT6             => clkout6_unused,
-    -- Input clock control
-    CLKFBIN             => clkfbout_buf,
-    CLKIN1              => clkin1,
-    CLKIN2              => '0',
-    -- Tied to always select the primary input clock
-    CLKINSEL            => '1',
-    -- Ports for dynamic reconfiguration
-    DADDR               => (others => '0'),
-    DCLK                => '0',
-    DEN                 => '0',
-    DI                  => (others => '0'),
-    DO                  => do_unused,
-    DRDY                => drdy_unused,
-    DWE                 => '0',
-    -- Ports for dynamic phase shift
-    PSCLK               => '0',
-    PSEN                => '0',
-    PSINCDEC            => '0',
-    PSDONE              => psdone_unused,
-    -- Other control and status signals
-    LOCKED              => LOCKED,
-    CLKINSTOPPED        => clkinstopped_unused,
-    CLKFBSTOPPED        => clkfbstopped_unused,
-    PWRDWN              => '0',
-    RST                 => RESET);
-
-  -- Output buffering
-  -------------------------------------
-  clkf_buf : BUFG
-  port map
-   (O => clkfbout_buf,
-    I => clkfbout);
-
-
-  clkout1_buf : BUFG
-  port map
-   (O   => CLK_OUT1,
-    I   => clkout0);
-
-
-
-  clkout2_buf : BUFG
-  port map
-   (O   => CLK_OUT2,
-    I   => clkout1);
-
-  clkout3_buf : BUFG
-  port map
-   (O   => CLK_OUT3,
-    I   => clkout2);
-
-  clkout4_buf : BUFG
-  port map
-   (O   => CLK_OUT4,
-    I   => clkout3);
-
-end xilinx;
+-- file: clk_wiz_v2_1.vhd
+-- 
+-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+-- Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1   100.000      0.000    50.000      130.958     98.575
+-- CLK_OUT2   200.000      0.000    50.000      114.829     98.575
+--
+------------------------------------------------------------------------------
+-- Input Clock   Input Freq (MHz)   Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary         100.000            0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTXKINTEX7FEE80_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end GTXKINTEX7FEE80_CLOCK_MODULE;
+
+architecture xilinx of GTXKINTEX7FEE80_CLOCK_MODULE is
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfbout_buf     : std_logic;
+  signal clkfboutb_unused : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout0b_unused  : std_logic;
+  signal clkout1          : std_logic;
+  signal clkout1b_unused  : std_logic;
+  signal clkout2          : std_logic;
+  signal clkout2b_unused  : std_logic;
+  signal clkout3          : std_logic;
+  signal clkout3b_unused  : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  signal clkout6_unused   : std_logic;
+  -- Dynamic programming unused signals
+  signal do_unused        : std_logic_vector(15 downto 0);
+  signal drdy_unused      : std_logic;
+  -- Dynamic phase shift unused signals
+  signal psdone_unused    : std_logic;
+  -- Unused status signals
+  signal clkfbstopped_unused : std_logic;
+  signal clkinstopped_unused : std_logic;
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : BUFG
+  port map
+   (O => clkin1,
+    I => CLK_IN);
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the MMCM primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+
+  mmcm_adv_inst : MMCME2_ADV
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLKOUT4_CASCADE      => FALSE,
+    COMPENSATION         => "ZHOLD",
+    STARTUP_WAIT         => FALSE,
+    DIVCLK_DIVIDE        => DIVIDE,
+    CLKFBOUT_MULT_F      => MULT,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKFBOUT_USE_FINE_PS => FALSE,
+    CLKOUT0_DIVIDE_F     => OUT0_DIVIDE,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT0_USE_FINE_PS  => FALSE,
+    CLKIN1_PERIOD        => CLK_PERIOD,
+    CLKOUT1_DIVIDE       => OUT1_DIVIDE,
+    CLKOUT1_PHASE        => 0.000,
+    CLKOUT1_DUTY_CYCLE   => 0.500,
+    CLKOUT1_USE_FINE_PS  => FALSE,
+    CLKOUT2_DIVIDE       => OUT2_DIVIDE,
+    CLKOUT2_PHASE        => 0.000,
+    CLKOUT2_DUTY_CYCLE   => 0.500,
+    CLKOUT2_USE_FINE_PS  => FALSE,
+    CLKOUT3_DIVIDE       => OUT3_DIVIDE,
+    CLKOUT3_PHASE        => 0.000,
+    CLKOUT3_DUTY_CYCLE   => 0.500,
+    CLKOUT3_USE_FINE_PS  => FALSE,
+    REF_JITTER1          => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKFBOUTB           => clkfboutb_unused,
+    CLKOUT0             => clkout0,
+    CLKOUT0B            => clkout0b_unused,
+    CLKOUT1             => clkout1,
+    CLKOUT1B            => clkout1b_unused,
+    CLKOUT2             => clkout2,
+    CLKOUT2B            => clkout2b_unused,
+    CLKOUT3             => clkout3,
+    CLKOUT3B            => clkout3b_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    CLKOUT6             => clkout6_unused,
+    -- Input clock control
+    CLKFBIN             => clkfbout,
+    CLKIN1              => clkin1,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => do_unused,
+    DRDY                => drdy_unused,
+    DWE                 => '0',
+    -- Ports for dynamic phase shift
+    PSCLK               => '0',
+    PSEN                => '0',
+    PSINCDEC            => '0',
+    PSDONE              => psdone_unused,
+    -- Other control and status signals
+    LOCKED              => MMCM_LOCKED_OUT,
+    CLKINSTOPPED        => clkinstopped_unused,
+    CLKFBSTOPPED        => clkfbstopped_unused,
+    PWRDWN              => '0',
+    RST                 => MMCM_RESET_IN);
+
+  -- Output buffering
+  -------------------------------------
+  --clkf_buf : BUFG
+  --port map
+  -- (O => clkfbout_buf,
+  --  I => clkfbout);
+
+
+  clkout0_buf : BUFG
+  port map
+   (O   => CLK0_OUT,
+    I   => clkout0);
+
+  clkout1_buf : BUFG
+  port map
+   (O   => CLK1_OUT,
+    I   => clkout1);
+
+  clkout2_buf : BUFG
+  port map
+   (O   => CLK2_OUT,
+    I   => clkout2);
+
+  clkout3_buf : BUFG
+  port map
+   (O   => CLK3_OUT,
+    I   => clkout3);
+
+end xilinx;
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_gt.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_gt.vhd
new file mode 100644
index 0000000..4eb81b8
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_gt.vhd
@@ -0,0 +1,816 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 2.6
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtxkintex7fee80_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity gtxKintex7FEE80_GT is
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP    : string     :=  "FALSE";        -- Set to "true" to speed up sim reset
+    RX_DFE_KL_CFG2_IN         : bit_vector :=   X"301148AC";
+    PMA_RSV_IN                : bit_vector :=  x"00018480";
+    PCS_RSVD_ATTR_IN          : bit_vector :=   X"000000000000"
+);
+port 
+(
+    --------------------------------- CPLL Ports -------------------------------
+    CPLLFBCLKLOST_OUT                       : out  std_logic;
+    CPLLLOCK_OUT                            : out  std_logic;
+    CPLLLOCKDETCLK_IN                       : in   std_logic;
+    CPLLREFCLKLOST_OUT                      : out  std_logic;
+    CPLLRESET_IN                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    GTREFCLK0_IN                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    DRPADDR_IN                              : in   std_logic_vector(8 downto 0);
+    DRPCLK_IN                               : in   std_logic;
+    DRPDI_IN                                : in   std_logic_vector(15 downto 0);
+    DRPDO_OUT                               : out  std_logic_vector(15 downto 0);
+    DRPEN_IN                                : in   std_logic;
+    DRPRDY_OUT                              : out  std_logic;
+    DRPWE_IN                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    QPLLCLK_IN                              : in   std_logic;
+    QPLLREFCLK_IN                           : in   std_logic;
+    --------------------- RX Initialization and Reset Ports --------------------
+    RXUSERRDY_IN                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    EYESCANDATAERROR_OUT                    : out  std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	 RXCDRRESET_IN                           : in  std_logic;
+    RXCDRLOCK_OUT                           : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    RXUSRCLK_IN                             : in   std_logic;
+    RXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    RXDATA_OUT                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    RXDISPERR_OUT                           : out  std_logic_vector(1 downto 0);
+    RXNOTINTABLE_OUT                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    GTXRXP_IN                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GTXRXN_IN                               : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    RXDLYEN_IN                              : in   std_logic;
+    RXDLYSRESET_IN                          : in   std_logic;
+    RXDLYSRESETDONE_OUT                     : out  std_logic;
+    RXPHALIGN_IN                            : in   std_logic;
+    RXPHALIGNDONE_OUT                       : out  std_logic;
+    RXPHALIGNEN_IN                          : in   std_logic;
+    RXPHDLYRESET_IN                         : in   std_logic;
+    RXPHMONITOR_OUT                         : out  std_logic_vector(4 downto 0);
+    RXPHSLIPMONITOR_OUT                     : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    RXLPMHFHOLD_IN                          : in   std_logic;
+    RXLPMLFHOLD_IN                          : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    RXOUTCLK_OUT                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GTRXRESET_IN                            : in   std_logic;
+    RXPCSRESET_IN                           : in   std_logic;
+    RXPMARESET_IN                           : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    RXCHARISK_OUT                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    RXRESETDONE_OUT                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GTTXRESET_IN                            : in   std_logic;
+    TXUSERRDY_IN                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    TXUSRCLK_IN                             : in   std_logic;
+    TXUSRCLK2_IN                            : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    TXDLYEN_IN                              : in   std_logic;
+    TXDLYSRESET_IN                          : in   std_logic;
+    TXDLYSRESETDONE_OUT                     : out  std_logic;
+    TXPHALIGN_IN                            : in   std_logic;
+    TXPHALIGNDONE_OUT                       : out  std_logic;
+    TXPHALIGNEN_IN                          : in   std_logic;
+    TXPHDLYRESET_IN                         : in   std_logic;
+    TXPHINIT_IN                             : in   std_logic;
+    TXPHINITDONE_OUT                        : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    TXDATA_IN                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    GTXTXN_OUT                              : out  std_logic;
+    GTXTXP_OUT                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    TXOUTCLK_OUT                            : out  std_logic;
+    TXOUTCLKFABRIC_OUT                      : out  std_logic;
+    TXOUTCLKPCS_OUT                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    TXCHARISK_IN                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    TXRESETDONE_OUT                         : out  std_logic
+
+
+);
+
+
+end gtxKintex7FEE80_GT;
+
+architecture RTL of gtxKintex7FEE80_GT is
+    
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+
+
+    -- RX Datapath signals
+    signal rxdata_i                         :   std_logic_vector(63 downto 0);      
+    signal rxchariscomma_float_i            :   std_logic_vector(5 downto 0);
+    signal rxcharisk_float_i                :   std_logic_vector(5 downto 0);
+    signal rxdisperr_float_i                :   std_logic_vector(5 downto 0);
+    signal rxnotintable_float_i             :   std_logic_vector(5 downto 0);
+    signal rxrundisp_float_i                :   std_logic_vector(5 downto 0);
+    
+
+
+    -- TX Datapath signals
+    signal txdata_i                         :   std_logic_vector(63 downto 0);
+    signal txkerr_float_i                   :   std_logic_vector(5 downto 0);
+    signal txrundisp_float_i                :   std_logic_vector(5 downto 0);
+    signal rxstartofseq_float_i             :   std_logic;
+
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+    -------------------  GT Datapath byte mapping  -----------------
+
+    RXDATA_OUT    <=   rxdata_i(15 downto 0);
+
+    txdata_i    <=   (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
+
+
+
+    ----------------------------- GTXE2 Instance  --------------------------   
+
+    gtxe2_i :GTXE2_CHANNEL
+    generic map
+    (
+
+        --_______________________ Simulation-Only Attributes ___________________
+
+        SIM_RECEIVER_DETECT_PASS   =>      ("TRUE"),
+        SIM_RESET_SPEEDUP          =>      (GT_SIM_GTRESET_SPEEDUP),
+        SIM_TX_EIDLE_DRIVE_LEVEL   =>      ("X"),
+        SIM_CPLLREFCLK_SEL         =>      ("001"),
+        SIM_VERSION                =>      ("4.0"), 
+        
+
+       ------------------RX Byte and Word Alignment Attributes---------------
+        ALIGN_COMMA_DOUBLE                      =>     ("FALSE"),
+        ALIGN_COMMA_ENABLE                      =>     ("1111111111"),
+        ALIGN_COMMA_WORD                        =>     (1),
+        ALIGN_MCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_MCOMMA_VALUE                      =>     ("1010000011"),
+        ALIGN_PCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_PCOMMA_VALUE                      =>     ("0101111100"),
+        SHOW_REALIGN_COMMA                      =>     ("FALSE"), --//("TRUE"),
+        RXSLIDE_AUTO_WAIT                       =>     (7),
+        RXSLIDE_MODE                            =>     ("AUTO"),--//("PCS"),
+        RX_SIG_VALID_DLY                        =>     (10),
+
+       ------------------RX 8B/10B Decoder Attributes---------------
+        RX_DISPERR_SEQ_MATCH                    =>     ("TRUE"),
+        DEC_MCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_PCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_VALID_COMMA_ONLY                    =>     ("FALSE"),
+
+       ------------------------RX Clock Correction Attributes----------------------
+        CBCC_DATA_SOURCE_SEL                    =>     ("DECODED"),
+        CLK_COR_SEQ_2_USE                       =>     ("FALSE"),
+        CLK_COR_KEEP_IDLE                       =>     ("FALSE"),
+        CLK_COR_MAX_LAT                         =>     (9),
+        CLK_COR_MIN_LAT                         =>     (7),
+        CLK_COR_PRECEDENCE                      =>     ("TRUE"),
+        CLK_COR_REPEAT_WAIT                     =>     (0),
+        CLK_COR_SEQ_LEN                         =>     (1),
+        CLK_COR_SEQ_1_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_1_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_1_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_4                         =>     ("0000000000"),
+        CLK_CORRECT_USE                         =>     ("FALSE"),
+        CLK_COR_SEQ_2_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_2_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_2_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_4                         =>     ("0000000000"),
+
+       ------------------------RX Channel Bonding Attributes----------------------
+        CHAN_BOND_KEEP_ALIGN                    =>     ("FALSE"),
+        CHAN_BOND_MAX_SKEW                      =>     (1),
+        CHAN_BOND_SEQ_LEN                       =>     (1),
+        CHAN_BOND_SEQ_1_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_USE                     =>     ("FALSE"),
+        FTS_DESKEW_SEQ_ENABLE                   =>     ("1111"),
+        FTS_LANE_DESKEW_CFG                     =>     ("1111"),
+        FTS_LANE_DESKEW_EN                      =>     ("FALSE"),
+
+       ---------------------------RX Margin Analysis Attributes----------------------------
+        ES_CONTROL                              =>     ("000000"),
+        ES_ERRDET_EN                            =>     ("FALSE"),
+        ES_EYE_SCAN_EN                          =>     ("TRUE"),
+        ES_HORZ_OFFSET                          =>     (x"000"),
+        ES_PMA_CFG                              =>     ("0000000000"),
+        ES_PRESCALE                             =>     ("00000"),
+        ES_QUALIFIER                            =>     (x"00000000000000000000"),
+        ES_QUAL_MASK                            =>     (x"00000000000000000000"),
+        ES_SDATA_MASK                           =>     (x"00000000000000000000"),
+        ES_VERT_OFFSET                          =>     ("000000000"),
+
+       -------------------------FPGA RX Interface Attributes-------------------------
+        RX_DATA_WIDTH                           =>     (20),
+
+       ---------------------------PMA Attributes----------------------------
+        OUTREFCLK_SEL_INV                       =>     ("11"),
+        PMA_RSV                                 =>     (PMA_RSV_IN),
+        PMA_RSV2                                =>     (x"2040"),
+        PMA_RSV3                                =>     ("00"),
+        PMA_RSV4                                =>     (x"00000000"),
+        RX_BIAS_CFG                             =>     ("000000000100"),
+        DMONITOR_CFG                            =>     (x"000A00"),
+        RX_CM_SEL                               =>     ("00"),
+        RX_CM_TRIM                              =>     ("000"),
+        RX_DEBUG_CFG                            =>     ("000000000000"),
+        RX_OS_CFG                               =>     ("0000010000000"),
+        TERM_RCAL_CFG                           =>     ("10000"),
+        TERM_RCAL_OVRD                          =>     ('0'),
+        TST_RSV                                 =>     (x"00000000"),
+        RX_CLK25_DIV                            =>     (4),
+        TX_CLK25_DIV                            =>     (4),
+        UCODEER_CLR                             =>     ('0'),
+
+       ---------------------------PCI Express Attributes----------------------------
+        PCS_PCIE_EN                             =>     ("FALSE"),
+
+       ---------------------------PCS Attributes----------------------------
+        PCS_RSVD_ATTR                           =>     (PCS_RSVD_ATTR_IN),
+
+       -------------RX Buffer Attributes------------
+        RXBUF_ADDR_MODE                         =>     ("FAST"),
+        RXBUF_EIDLE_HI_CNT                      =>     ("1000"),
+        RXBUF_EIDLE_LO_CNT                      =>     ("0000"),
+        RXBUF_EN                                =>     ("FALSE"),
+        RX_BUFFER_CFG                           =>     ("000000"),
+        RXBUF_RESET_ON_CB_CHANGE                =>     ("TRUE"),
+        RXBUF_RESET_ON_COMMAALIGN               =>     ("FALSE"),
+        RXBUF_RESET_ON_EIDLE                    =>     ("FALSE"),
+        RXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        RXBUFRESET_TIME                         =>     ("00001"),
+        RXBUF_THRESH_OVFLW                      =>     (61),
+        RXBUF_THRESH_OVRD                       =>     ("FALSE"),
+        RXBUF_THRESH_UNDFLW                     =>     (4),
+        RXDLY_CFG                               =>     (x"001F"),
+        RXDLY_LCFG                              =>     (x"030"),
+        RXDLY_TAP_CFG                           =>     (x"0000"),
+        RXPH_CFG                                =>     (x"000000"),
+        RXPHDLY_CFG                             =>     (x"084020"),
+        RXPH_MONITOR_SEL                        =>     ("00000"),
+        RX_XCLK_SEL                             =>     ("RXUSR"),
+        RX_DDI_SEL                              =>     ("000000"),
+        RX_DEFER_RESET_BUF_EN                   =>     ("TRUE"),
+
+       -----------------------CDR Attributes-------------------------
+
+       --For GTX only: Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
+
+       --For GTX only: Display Port, HBR2 -   set RXCDR_CFG=72'h038C008bff20200010
+        RXCDR_CFG                               =>     (x"03000023ff10200020"),
+
+        RXCDR_FR_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_HOLD_DURING_EIDLE                 =>     ('0'),
+        RXCDR_PH_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_LOCK_CFG                          =>     ("010101"),
+
+       -------------------RX Initialization and Reset Attributes-------------------
+        RXCDRFREQRESET_TIME                     =>     ("00001"),
+        RXCDRPHRESET_TIME                       =>     ("00001"),
+        RXISCANRESET_TIME                       =>     ("00001"),
+        RXPCSRESET_TIME                         =>     ("00001"),
+        RXPMARESET_TIME                         =>     ("00011"),
+
+       -------------------RX OOB Signaling Attributes-------------------
+        RXOOB_CFG                               =>     ("0000110"),
+
+       -------------------------RX Gearbox Attributes---------------------------
+        RXGEARBOX_EN                            =>     ("FALSE"),
+        GEARBOX_MODE                            =>     ("000"),
+
+       -------------------------PRBS Detection Attribute-----------------------
+        RXPRBS_ERR_LOOPBACK                     =>     ('0'),
+
+       -------------Power-Down Attributes----------
+        PD_TRANS_TIME_FROM_P2                   =>     (x"03c"),
+        PD_TRANS_TIME_NONE_P2                   =>     (x"3c"),
+        PD_TRANS_TIME_TO_P2                     =>     (x"64"),
+
+       -------------RX OOB Signaling Attributes----------
+        SAS_MAX_COM                             =>     (64),
+        SAS_MIN_COM                             =>     (36),
+        SATA_BURST_SEQ_LEN                      =>     ("1111"),
+        SATA_BURST_VAL                          =>     ("100"),
+        SATA_EIDLE_VAL                          =>     ("100"),
+        SATA_MAX_BURST                          =>     (8),
+        SATA_MAX_INIT                           =>     (21),
+        SATA_MAX_WAKE                           =>     (7),
+        SATA_MIN_BURST                          =>     (4),
+        SATA_MIN_INIT                           =>     (12),
+        SATA_MIN_WAKE                           =>     (4),
+
+       -------------RX Fabric Clock Output Control Attributes----------
+        TRANS_TIME_RATE                         =>     (x"0E"),
+
+       --------------TX Buffer Attributes----------------
+        TXBUF_EN                                =>     ("FALSE"),
+        TXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        TXDLY_CFG                               =>     (x"001F"),
+        TXDLY_LCFG                              =>     (x"030"),
+        TXDLY_TAP_CFG                           =>     (x"0000"),
+        TXPH_CFG                                =>     (x"0780"),
+        TXPHDLY_CFG                             =>     (x"084020"),
+        TXPH_MONITOR_SEL                        =>     ("00000"),
+        TX_XCLK_SEL                             =>     ("TXUSR"),
+
+       -------------------------FPGA TX Interface Attributes-------------------------
+        TX_DATA_WIDTH                           =>     (20),
+
+       -------------------------TX Configurable Driver Attributes-------------------------
+        TX_DEEMPH0                              =>     ("00000"),
+        TX_DEEMPH1                              =>     ("00000"),
+        TX_EIDLE_ASSERT_DELAY                   =>     ("110"),
+        TX_EIDLE_DEASSERT_DELAY                 =>     ("100"),
+        TX_LOOPBACK_DRIVE_HIZ                   =>     ("FALSE"),
+        TX_MAINCURSOR_SEL                       =>     ('0'),
+        TX_DRIVE_MODE                           =>     ("DIRECT"),
+        TX_MARGIN_FULL_0                        =>     ("1001110"),
+        TX_MARGIN_FULL_1                        =>     ("1001001"),
+        TX_MARGIN_FULL_2                        =>     ("1000101"),
+        TX_MARGIN_FULL_3                        =>     ("1000010"),
+        TX_MARGIN_FULL_4                        =>     ("1000000"),
+        TX_MARGIN_LOW_0                         =>     ("1000110"),
+        TX_MARGIN_LOW_1                         =>     ("1000100"),
+        TX_MARGIN_LOW_2                         =>     ("1000010"),
+        TX_MARGIN_LOW_3                         =>     ("1000000"),
+        TX_MARGIN_LOW_4                         =>     ("1000000"),
+
+       -------------------------TX Gearbox Attributes--------------------------
+        TXGEARBOX_EN                            =>     ("FALSE"),
+
+       -------------------------TX Initialization and Reset Attributes--------------------------
+        TXPCSRESET_TIME                         =>     ("00001"),
+        TXPMARESET_TIME                         =>     ("00001"),
+
+       -------------------------TX Receiver Detection Attributes--------------------------
+        TX_RXDETECT_CFG                         =>     (x"1832"),
+        TX_RXDETECT_REF                         =>     ("100"),
+
+       ----------------------------CPLL Attributes----------------------------
+        CPLL_CFG                                =>     (x"BC07DC"),
+        CPLL_FBDIV                              =>     (5),
+        CPLL_FBDIV_45                           =>     (5),
+        CPLL_INIT_CFG                           =>     (x"00001E"),
+        CPLL_LOCK_CFG                           =>     (x"01E8"),
+        CPLL_REFCLK_DIV                         =>     (1),
+        RXOUT_DIV                               =>     (2),
+        TXOUT_DIV                               =>     (2),
+        SATA_CPLL_CFG                           =>     ("VCO_3000MHZ"),
+
+       --------------RX Initialization and Reset Attributes-------------
+        RXDFELPMRESET_TIME                      =>     ("0001111"),
+
+       --------------RX Equalizer Attributes-------------
+        RXLPM_HF_CFG                            =>     ("00000011110000"),
+        RXLPM_LF_CFG                            =>     ("00000011110000"),
+        RX_DFE_GAIN_CFG                         =>     (x"020FEA"),
+        RX_DFE_H2_CFG                           =>     ("000000000000"),
+        RX_DFE_H3_CFG                           =>     ("000001000000"),
+        RX_DFE_H4_CFG                           =>     ("00011110000"),
+        RX_DFE_H5_CFG                           =>     ("00011100000"),
+        RX_DFE_KL_CFG                           =>     ("0000011111110"),
+        RX_DFE_LPM_CFG                          =>     (x"0904"),
+        RX_DFE_LPM_HOLD_DURING_EIDLE            =>     ('0'),
+        RX_DFE_UT_CFG                           =>     ("10001111000000000"),
+        RX_DFE_VP_CFG                           =>     ("00011111100000011"),
+
+       -------------------------Power-Down Attributes-------------------------
+        RX_CLKMUX_PD                            =>     ('1'),
+        TX_CLKMUX_PD                            =>     ('1'),
+
+       -------------------------FPGA RX Interface Attribute-------------------------
+        RX_INT_DATAWIDTH                        =>     (0),
+
+       -------------------------FPGA TX Interface Attribute-------------------------
+        TX_INT_DATAWIDTH                        =>     (0),
+
+       ------------------TX Configurable Driver Attributes---------------
+        TX_QPI_STATUS_EN                        =>     ('0'),
+
+       -------------------------RX Equalizer Attributes--------------------------
+        RX_DFE_KL_CFG2                          =>     (RX_DFE_KL_CFG2_IN),
+        RX_DFE_XYD_CFG                          =>     ("0000000000000"),
+
+       -------------------------TX Configurable Driver Attributes--------------------------
+        TX_PREDRIVER_MODE                       =>     ('0')
+
+
+    )
+    port map
+    (
+                      --------------------------------- CPLL Ports -------------------------------
+        CPLLFBCLKLOST                   =>      CPLLFBCLKLOST_OUT,
+        CPLLLOCK                        =>      CPLLLOCK_OUT,
+        CPLLLOCKDETCLK                  =>      CPLLLOCKDETCLK_IN,
+        CPLLLOCKEN                      =>      tied_to_vcc_i,
+        CPLLPD                          =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      CPLLREFCLKLOST_OUT,
+        CPLLREFCLKSEL                   =>      "001",
+        CPLLRESET                       =>      CPLLRESET_IN,
+        GTRSVD                          =>      "0000000000000000",
+        PCSRSVDIN                       =>      "0000000000000000",
+        PCSRSVDIN2                      =>      "00000",
+        PMARSVDIN                       =>      "00000",
+        PMARSVDIN2                      =>      "00000",
+        TSTIN                           =>      "11111111111111111111",
+        TSTOUT                          =>      open,
+        ---------------------------------- Channel ---------------------------------
+        CLKRSVD                         =>      "0000",
+        -------------------------- Channel - Clocking Ports ------------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      tied_to_ground_i,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR                         =>      DRPADDR_IN,
+        DRPCLK                          =>      DRPCLK_IN,
+        DRPDI                           =>      DRPDI_IN,
+        DRPDO                           =>      DRPDO_OUT,
+        DRPEN                           =>      DRPEN_IN,
+        DRPRDY                          =>      DRPRDY_OUT,
+        DRPWE                           =>      DRPWE_IN,
+        ------------------------------- Clocking Ports -----------------------------
+        GTREFCLKMONITOR                 =>      open,
+        QPLLCLK                         =>      QPLLCLK_IN,
+        QPLLREFCLK                      =>      QPLLREFCLK_IN,
+        RXSYSCLKSEL                     =>      "00",
+        TXSYSCLKSEL                     =>      "00",
+        --------------------------- Digital Monitor Ports --------------------------
+        DMONITOROUT                     =>      open,
+        ----------------- FPGA TX Interface Datapath Configuration  ----------------
+        TX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------------------- Loopback Ports -----------------------------
+        LOOPBACK                        =>      tied_to_ground_vec_i(2 downto 0),
+        ----------------------------- PCI Express Ports ----------------------------
+        PHYSTATUS                       =>      open,
+        RXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        RXVALID                         =>      open,
+        ------------------------------ Power-Down Ports ----------------------------
+        RXPD                            =>      "00",
+        TXPD                            =>      "00",
+        -------------------------- RX 8B/10B Decoder Ports -------------------------
+        SETERRSTATUS                    =>      tied_to_ground_i,
+        --------------------- RX Initialization and Reset Ports --------------------
+        EYESCANRESET                    =>      tied_to_ground_i,
+        RXUSERRDY                       =>      RXUSERRDY_IN,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR                =>      EYESCANDATAERROR_OUT,
+        EYESCANMODE                     =>      tied_to_ground_i,
+        EYESCANTRIGGER                  =>      tied_to_ground_i,
+        ------------------------- Receive Ports - CDR Ports ------------------------
+        RXCDRFREQRESET                  =>      tied_to_ground_i,
+        RXCDRHOLD                       =>      tied_to_ground_i,
+        RXCDRLOCK                       =>      RXCDRLOCK_OUT,
+        RXCDROVRDEN                     =>      tied_to_ground_i,
+        RXCDRRESET                      =>      RXCDRRESET_IN, --// tied_to_ground_i,
+        RXCDRRESETRSV                   =>      tied_to_ground_i,
+        ------------------- Receive Ports - Clock Correction Ports -----------------
+        RXCLKCORCNT                     =>      open,
+        ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+        RX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXUSRCLK                        =>      RXUSRCLK_IN,
+        RXUSRCLK2                       =>      RXUSRCLK2_IN,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        RXDATA                          =>      rxdata_i,
+        ------------------- Receive Ports - Pattern Checker Ports ------------------
+        RXPRBSERR                       =>      open,
+        RXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ------------------- Receive Ports - Pattern Checker ports ------------------
+        RXPRBSCNTRESET                  =>      tied_to_ground_i,
+        -------------------- Receive Ports - RX  Equalizer Ports -------------------
+        RXDFEXYDEN                      =>      tied_to_ground_i,
+        RXDFEXYDHOLD                    =>      tied_to_ground_i,
+        RXDFEXYDOVRDEN                  =>      tied_to_ground_i,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXDISPERR(7 downto 2)           =>      rxdisperr_float_i,
+        RXDISPERR(1 downto 0)           =>      RXDISPERR_OUT,
+        RXNOTINTABLE(7 downto 2)        =>      rxnotintable_float_i,
+        RXNOTINTABLE(1 downto 0)        =>      RXNOTINTABLE_OUT,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        GTXRXP                          =>      GTXRXP_IN,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTXRXN                          =>      GTXRXN_IN,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        RXBUFRESET                      =>      tied_to_ground_i,
+        RXBUFSTATUS                     =>      open,
+        RXDDIEN                         =>      tied_to_vcc_i,
+        RXDLYBYPASS                     =>      tied_to_ground_i,
+        RXDLYEN                         =>      RXDLYEN_IN,
+        RXDLYOVRDEN                     =>      tied_to_ground_i,
+        RXDLYSRESET                     =>      RXDLYSRESET_IN,
+        RXDLYSRESETDONE                 =>      RXDLYSRESETDONE_OUT,
+        RXPHALIGN                       =>      RXPHALIGN_IN,
+        RXPHALIGNDONE                   =>      RXPHALIGNDONE_OUT,
+        RXPHALIGNEN                     =>      RXPHALIGNEN_IN,
+        RXPHDLYPD                       =>      tied_to_ground_i,
+        RXPHDLYRESET                    =>      RXPHDLYRESET_IN,
+        RXPHMONITOR                     =>      RXPHMONITOR_OUT,
+        RXPHOVRDEN                      =>      tied_to_ground_i,
+        RXPHSLIPMONITOR                 =>      RXPHSLIPMONITOR_OUT,
+        RXSTATUS                        =>      open,
+        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+        RXBYTEISALIGNED                 =>      open,
+        RXBYTEREALIGN                   =>      open,
+        RXCOMMADET                      =>      open,
+        RXCOMMADETEN                    =>      tied_to_vcc_i,
+        RXMCOMMAALIGNEN                 =>      tied_to_vcc_i,
+        RXPCOMMAALIGNEN                 =>      tied_to_vcc_i,
+        ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+        RXCHANBONDSEQ                   =>      open,
+        RXCHBONDEN                      =>      tied_to_ground_i,
+        RXCHBONDLEVEL                   =>      tied_to_ground_vec_i(2 downto 0),
+        RXCHBONDMASTER                  =>      tied_to_ground_i,
+        RXCHBONDO                       =>      open,
+        RXCHBONDSLAVE                   =>      tied_to_ground_i,
+        ----------------- Receive Ports - RX Channel Bonding Ports  ----------------
+        RXCHANISALIGNED                 =>      open,
+        RXCHANREALIGN                   =>      open,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        RXLPMHFHOLD                     =>      RXLPMHFHOLD_IN,
+        RXLPMHFOVRDEN                   =>      tied_to_ground_i,
+        RXLPMLFHOLD                     =>      RXLPMLFHOLD_IN,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        RXDFEAGCHOLD                    =>      tied_to_ground_i,
+        RXDFEAGCOVRDEN                  =>      tied_to_ground_i,
+        RXDFECM1EN                      =>      tied_to_ground_i,
+        RXDFELFHOLD                     =>      tied_to_ground_i,
+        RXDFELFOVRDEN                   =>      tied_to_ground_i,
+        RXDFELPMRESET                   =>      tied_to_ground_i,
+        RXDFETAP2HOLD                   =>      tied_to_ground_i,
+        RXDFETAP2OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP3HOLD                   =>      tied_to_ground_i,
+        RXDFETAP3OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP4HOLD                   =>      tied_to_ground_i,
+        RXDFETAP4OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP5HOLD                   =>      tied_to_ground_i,
+        RXDFETAP5OVRDEN                 =>      tied_to_ground_i,
+        RXDFEUTHOLD                     =>      tied_to_ground_i,
+        RXDFEUTOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVPHOLD                     =>      tied_to_ground_i,
+        RXDFEVPOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVSEN                       =>      tied_to_ground_i,
+        RXLPMLFKLOVRDEN                 =>      tied_to_ground_i,
+        RXMONITOROUT                    =>      open,
+        RXMONITORSEL                    =>      "00",
+        RXOSHOLD                        =>      tied_to_ground_i,
+        RXOSOVRDEN                      =>      tied_to_ground_i,
+        ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+        RXRATEDONE                      =>      open,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK                        =>      RXOUTCLK_OUT,
+        RXOUTCLKFABRIC                  =>      open,
+        RXOUTCLKPCS                     =>      open,
+        RXOUTCLKSEL                     =>      "010",
+        ---------------------- Receive Ports - RX Gearbox Ports --------------------
+        RXDATAVALID                     =>      open,
+        RXHEADER                        =>      open,
+        RXHEADERVALID                   =>      open,
+        RXSTARTOFSEQ                    =>      open,
+        --------------------- Receive Ports - RX Gearbox Ports  --------------------
+        RXGEARBOXSLIP                   =>      tied_to_ground_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET                       =>      GTRXRESET_IN,
+        RXOOBRESET                      =>      tied_to_ground_i,
+        RXPCSRESET                      =>      RXPCSRESET_IN,
+        RXPMARESET                      =>      RXPMARESET_IN,
+        ------------------ Receive Ports - RX Margin Analysis ports ----------------
+        RXLPMEN                         =>      tied_to_vcc_i,
+        ------------------- Receive Ports - RX OOB Signaling ports -----------------
+        RXCOMSASDET                     =>      open,
+        RXCOMWAKEDET                    =>      open,
+        ------------------ Receive Ports - RX OOB Signaling ports  -----------------
+        RXCOMINITDET                    =>      open,
+        ------------------ Receive Ports - RX OOB signalling Ports -----------------
+        RXELECIDLE                      =>      open,
+        RXELECIDLEMODE                  =>      "11",
+        ----------------- Receive Ports - RX Polarity Control Ports ----------------
+        RXPOLARITY                      =>      tied_to_ground_i,
+        ---------------------- Receive Ports - RX gearbox ports --------------------
+        RXSLIDE                         =>      tied_to_ground_i,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        RXCHARISCOMMA                   =>      open,
+        RXCHARISK(7 downto 2)           =>      rxcharisk_float_i,
+        RXCHARISK(1 downto 0)           =>      RXCHARISK_OUT,
+        ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
+        RXCHBONDI                       =>      "00000",
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE                     =>      RXRESETDONE_OUT,
+        -------------------------------- Rx AFE Ports ------------------------------
+        RXQPIEN                         =>      tied_to_ground_i,
+        RXQPISENN                       =>      open,
+        RXQPISENP                       =>      open,
+        --------------------------- TX Buffer Bypass Ports -------------------------
+        TXPHDLYTSTCLK                   =>      tied_to_ground_i,
+        ------------------------ TX Configurable Driver Ports ----------------------
+        TXPOSTCURSOR                    =>      "00000",
+        TXPOSTCURSORINV                 =>      tied_to_ground_i,
+        TXPRECURSOR                     =>      tied_to_ground_vec_i(4 downto 0),
+        TXPRECURSORINV                  =>      tied_to_ground_i,
+        TXQPIBIASEN                     =>      tied_to_ground_i,
+        TXQPISTRONGPDOWN                =>      tied_to_ground_i,
+        TXQPIWEAKPUP                    =>      tied_to_ground_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        CFGRESET                        =>      tied_to_ground_i,
+        GTTXRESET                       =>      GTTXRESET_IN,
+        PCSRSVDOUT                      =>      open,
+        TXUSERRDY                       =>      TXUSERRDY_IN,
+        ---------------------- Transceiver Reset Mode Operation --------------------
+        GTRESETSEL                      =>      tied_to_ground_i,
+        RESETOVRD                       =>      tied_to_ground_i,
+        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+        TXCHARDISPMODE                  =>      tied_to_ground_vec_i(7 downto 0),
+        TXCHARDISPVAL                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXUSRCLK                        =>      TXUSRCLK_IN,
+        TXUSRCLK2                       =>      TXUSRCLK2_IN,
+        --------------------- Transmit Ports - PCI Express Ports -------------------
+        TXELECIDLE                      =>      tied_to_ground_i,
+        TXMARGIN                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        TXSWING                         =>      tied_to_ground_i,
+        ------------------ Transmit Ports - Pattern Generator Ports ----------------
+        TXPRBSFORCEERR                  =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        TXDLYBYPASS                     =>      tied_to_ground_i,
+        TXDLYEN                         =>      TXDLYEN_IN,
+        TXDLYHOLD                       =>      tied_to_ground_i,
+        TXDLYOVRDEN                     =>      tied_to_ground_i,
+        TXDLYSRESET                     =>      TXDLYSRESET_IN,
+        TXDLYSRESETDONE                 =>      TXDLYSRESETDONE_OUT,
+        TXDLYUPDOWN                     =>      tied_to_ground_i,
+        TXPHALIGN                       =>      TXPHALIGN_IN,
+        TXPHALIGNDONE                   =>      TXPHALIGNDONE_OUT,
+        TXPHALIGNEN                     =>      TXPHALIGNEN_IN,
+        TXPHDLYPD                       =>      tied_to_ground_i,
+        TXPHDLYRESET                    =>      TXPHDLYRESET_IN,
+        TXPHINIT                        =>      TXPHINIT_IN,
+        TXPHINITDONE                    =>      TXPHINITDONE_OUT,
+        TXPHOVRDEN                      =>      tied_to_ground_i,
+        ---------------------- Transmit Ports - TX Buffer Ports --------------------
+        TXBUFSTATUS                     =>      open,
+        --------------- Transmit Ports - TX Configurable Driver Ports --------------
+        TXBUFDIFFCTRL                   =>      "100",
+        TXDEEMPH                        =>      tied_to_ground_i,
+        TXDIFFCTRL                      =>      "1000",
+        TXDIFFPD                        =>      tied_to_ground_i,
+        TXINHIBIT                       =>      tied_to_ground_i,
+        TXMAINCURSOR                    =>      "0000000",
+        TXPISOPD                        =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        TXDATA                          =>      txdata_i,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        GTXTXN                          =>      GTXTXN_OUT,
+        GTXTXP                          =>      GTXTXP_OUT,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK                        =>      TXOUTCLK_OUT,
+        TXOUTCLKFABRIC                  =>      TXOUTCLKFABRIC_OUT,
+        TXOUTCLKPCS                     =>      TXOUTCLKPCS_OUT,
+        TXOUTCLKSEL                     =>      "011",
+        TXRATEDONE                      =>      open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        TXCHARISK(7 downto 2)           =>      tied_to_ground_vec_i(5 downto 0),
+        TXCHARISK(1 downto 0)           =>      TXCHARISK_IN,
+        TXGEARBOXREADY                  =>      open,
+        TXHEADER                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXSEQUENCE                      =>      tied_to_ground_vec_i(6 downto 0),
+        TXSTARTSEQ                      =>      tied_to_ground_i,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXPCSRESET                      =>      tied_to_ground_i,
+        TXPMARESET                      =>      tied_to_ground_i,
+        TXRESETDONE                     =>      TXRESETDONE_OUT,
+        ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+        TXCOMFINISH                     =>      open,
+        TXCOMINIT                       =>      tied_to_ground_i,
+        TXCOMSAS                        =>      tied_to_ground_i,
+        TXCOMWAKE                       =>      tied_to_ground_i,
+        TXPDELECIDLEMODE                =>      tied_to_ground_i,
+        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+        TXPOLARITY                      =>      tied_to_ground_i,
+        --------------- Transmit Ports - TX Receiver Detection Ports  --------------
+        TXDETECTRX                      =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
+        TX8B10BBYPASS                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+        TXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ----------------------- Tx Configurable Driver  Ports ----------------------
+        TXQPISENN                       =>      open,
+        TXQPISENP                       =>      open
+
+    );
+ 
+ end RTL;
+
+
+ 
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_manual_phase_align.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_manual_phase_align.vhd
new file mode 100644
index 0000000..eb72828
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_manual_phase_align.vhd
@@ -0,0 +1,286 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 2.6
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename : gtxkintex7fee80_rx_manual_phase_align.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--  Description :     This module performs RX Buffer Phase Alignment in Manual Mode.
+--                     
+--
+--
+-- Module gtxKintex7FEE80_rx_manual_phase_align
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN is
+  Generic( NUMBER_OF_LANES          : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
+           MASTER_LANE_ID           : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RESET_PHALIGNMENT        : in  STD_LOGIC;
+           RUN_PHALIGNMENT          : in  STD_LOGIC;
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Manual phase-alignment performed sucessfully    
+           RXDLYSRESET              : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           RXDLYSRESETDONE          : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           RXPHALIGN                : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           RXPHALIGNDONE            : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           RXDLYEN                  : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+           );
+end gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN;
+
+architecture RTL of gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN is
+
+  component gtxKintex7FEE80_sync_block
+   generic (
+     INITIALISE : bit_vector(1 downto 0) := "00"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+  constant VCC_VEC  : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '1');
+  constant GND_VEC  : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+
+  type rx_phase_align_manual_fsm is(
+    INIT, WAIT_DLYRST_DONE, M_PHALIGN, M_DLYEN,
+    S_PHALIGN, M_DLYEN2, PHALIGN_DONE
+    );
+  signal rx_phalign_manual_state  : rx_phase_align_manual_fsm := INIT;
+  signal rxphaligndone_prev       : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal rxphaligndone_ris_edge   : std_logic_vector(NUMBER_OF_LANES-1 downto 0);
+
+  signal rxdlysresetdone_store    : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal rxphaligndone_store      : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal rxdone_clear             : std_logic := '0';
+
+  signal rxphaligndone_sync       : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal rxdlysresetdone_sync     : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+
+
+begin
+
+ cdc: for i in 0 to NUMBER_OF_LANES-1 generate
+ sync_RXPHALIGNDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  RXPHALIGNDONE(i),
+            data_out        =>  rxphaligndone_sync(i) 
+         );
+
+  sync_RXDLYSRESETDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  RXDLYSRESETDONE(i),
+            data_out        =>  rxdlysresetdone_sync(i) 
+         );
+
+   end generate;
+
+
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      rxphaligndone_prev    <= rxphaligndone_sync;  
+    end if;
+  end process;
+  
+  edge_detect: for i in 0 to NUMBER_OF_LANES-1 generate
+    rxphaligndone_ris_edge(i) <= '1' when (rxphaligndone_prev(i) = '0') and (rxphaligndone_sync(i) = '1') else '0';            
+  end generate;
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if rxdone_clear = '1' then
+        rxdlysresetdone_store <= (others=>'0');
+        rxphaligndone_store  <= (others=>'0');
+      else
+        for i in 0 to NUMBER_OF_LANES-1 loop
+          if rxdlysresetdone_sync(i) = '1' then
+            rxdlysresetdone_store(i) <= '1';
+          end if;
+          if rxphaligndone_ris_edge(i) = '1' then
+             rxphaligndone_store(i)  <= '1';
+          end if;
+        end loop;
+      end if;
+    end if;
+  end process;
+
+
+
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if RESET_PHALIGNMENT = '1' then
+        PHASE_ALIGNMENT_DONE    <= '0';
+        RXDLYSRESET             <= (others => '0');
+        RXPHALIGN               <= (others => '0');
+        RXDLYEN                 <= (others => '0');
+        rx_phalign_manual_state <= INIT;
+        rxdone_clear            <= '1';
+      else
+        case rx_phalign_manual_state is
+          when INIT => 
+            PHASE_ALIGNMENT_DONE <= '0';
+            rxdone_clear         <= '1';
+            
+            if RUN_PHALIGNMENT = '1' then
+              --Assert RXDLYSRESET for all lanes. 
+              rxdone_clear            <= '0';
+              RXDLYSRESET             <= (others => '1');
+              rx_phalign_manual_state <= WAIT_DLYRST_DONE;
+            end if;
+            
+          when WAIT_DLYRST_DONE =>
+            for i in 0 to NUMBER_OF_LANES - 1 loop
+              --if RXDLYSRESETDONE(i) = '1' then
+              if rxdlysresetdone_store(i) = '1' then
+                --Hold RXDLYSRESET High until RXDLYSRESETDONE of the 
+                --respective lane is asserted.
+                --Deassert RXDLYSRESET for the lane in which the 
+                --RXDLYSRESETDONE is asserted.
+                RXDLYSRESET(i) <= '0';
+              end if;
+            end loop;
+            if rxdlysresetdone_store = VCC_VEC then
+              rx_phalign_manual_state   <= M_PHALIGN;
+            end if;
+          
+          when M_PHALIGN => 
+            --When RXDLYSRESET of all lanes are deasserted, assert 
+            --RXPHALIGN for the master lane.
+            RXPHALIGN(MASTER_LANE_ID) <= '1';
+            if rxphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+              --Hold this signal High until a rising edge on RXPHALIGNDONE 
+              --of the master lane is detected, then deassert RXPHALIGN for 
+              --the master lane.
+              RXPHALIGN(MASTER_LANE_ID) <= '0';
+              rx_phalign_manual_state   <= M_DLYEN;
+            end if;
+          
+          when M_DLYEN => 
+            --Assert RXDLYEN for the master lane. This causes RXPHALIGNDONE 
+            --to be deasserted.
+            RXDLYEN(MASTER_LANE_ID) <= '1';
+            if rxphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+              --Hold RXDLYEN for the master lane High until a rising edge on
+              --RXPHALIGNDONE of the master lane is detected, then deassert 
+              --RXDLYEN for the master lane.
+              RXDLYEN(MASTER_LANE_ID)   <= '0';
+              rx_phalign_manual_state   <= S_PHALIGN;        
+            end if;
+          
+          when S_PHALIGN =>
+            --Assert RXPHALIGN for all slave lane(s). Hold this signal High until
+            --a rising edge on RXPHALIGNDONE of the respective slave lane is detected.
+            RXPHALIGN                 <= (others=>'1');--\Assert only the PHALIGN signal of
+            RXPHALIGN(MASTER_LANE_ID) <= '0';          --/the slaves.
+            for i in 0 to NUMBER_OF_LANES - 1 loop
+              if rxphaligndone_store(i) = '1' then
+                --When a rising edge on the respective lane is detected, RXPHALIGN
+                --of that lane is deasserted.
+                RXPHALIGN(i) <= '0';
+              end if;
+            end loop;
+           --The reason for checking of the occurance of at least one rising edge
+            --is to avoid the potential direct move where RXPHALIGNDONE might not 
+            --be going low fast enough. 
+            --if rxphaligndone_store = VCC_VEC and rxphaligndone_ris_edge /= GND_VEC then
+            if rxphaligndone_store = VCC_VEC then
+              rx_phalign_manual_state   <= M_DLYEN2;
+            end if;
+          
+          when M_DLYEN2 =>
+            --When RXPHALIGN for all slave lane(s) are deasserted, assert RXDLYEN 
+            --for the master lane. This causes RXPHALIGNDONE of the master lane 
+            --to be deasserted.
+            RXDLYEN(MASTER_LANE_ID) <= '1';
+            if rxphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+              --Wait until RXPHALIGNDONE of the master lane reasserts. Phase and 
+              --delay alignment for the multilane interface is complete.
+              rx_phalign_manual_state   <= PHALIGN_DONE;        
+            end if;
+          
+          when PHALIGN_DONE =>
+            --Continue to hold RXDLYEN for the master lane High to adjust RXUSRCLK 
+            --to compensate for temperature and voltage variations.
+            RXDLYEN(MASTER_LANE_ID) <= '1';
+            PHASE_ALIGNMENT_DONE    <= '1';
+
+          when OTHERS =>
+            rx_phalign_manual_state <= INIT;
+         
+        end case;
+      end if;
+    end if;
+  end process;  
+
+end RTL;
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_startup_fsm.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_startup_fsm.vhd
new file mode 100644
index 0000000..65592aa
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_rx_startup_fsm.vhd
@@ -0,0 +1,738 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 2.6
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename : gtxkintex7fee80_rx_startup_fsm.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--  Description :     This module performs RX reset and initialization.
+--                     
+--
+--
+-- Module gtxKintex7FEE80_rx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxKintex7FEE80_RX_STARTUP_FSM is
+  Generic( EXAMPLE_SIMULATION       : integer := 0;
+           GT_TYPE                  : string  := "GTX";
+           EQ_MODE                  : string  := "DFE";           --RX Equalisation Mode; set to DFE or LPM
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient                         
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;        --Stable Clock, either a stable clock from the PCB
+                                                            --or reference-clock present at startup.
+           RXUSERCLK                : in  STD_LOGIC;        --RXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;        --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;        --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;        --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the CPLL of the GT
+           RXRESETDONE              : in  STD_LOGIC;
+           MMCM_LOCK                : in  STD_LOGIC;
+           RECCLK_STABLE            : in  STD_LOGIC;
+           RECCLK_MONITOR_RESTART   : in  STD_LOGIC:='0';
+           DATA_VALID               : in  STD_LOGIC;
+           TXUSERRDY                : in  STD_LOGIC;       --TXUSERRDY from GT 
+           DONT_RESET_ON_DATA_ERROR : in  STD_LOGIC;       --Used to control the Auto-Reset of FSM when Data Error is detected
+           GTRXRESET                : out STD_LOGIC:='0';
+           MMCM_RESET               : out STD_LOGIC:='1';
+           QPLL_RESET               : out STD_LOGIC:='0';  --Reset QPLL (only if RX uses QPLL)
+           CPLL_RESET               : out STD_LOGIC:='0';  --Reset CPLL (only if RX uses CPLL)
+           RX_FSM_RESET_DONE        : out STD_LOGIC;       --Reset-sequence has sucessfully been finished.
+           RXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC;
+           PHALIGNMENT_DONE         : in  STD_LOGIC; 
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';           
+           RXDFEAGCHOLD             : out STD_LOGIC;
+           RXDFELFHOLD              : out STD_LOGIC;
+           RXLPMLFHOLD              : out STD_LOGIC;
+           RXLPMHFHOLD              : out STD_LOGIC;
+           RETRY_COUNTER            : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end gtxKintex7FEE80_RX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+--   are calculated at design-time based on the Generics
+--   
+-- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
+--   => signal which PLL has been reset
+-- * 
+
+
+
+architecture RTL of gtxKintex7FEE80_RX_STARTUP_FSM is
+
+  component gtxKintex7FEE80_sync_block
+   generic (
+     INITIALISE : bit_vector(1 downto 0) := "00"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+
+  type rx_rst_fsm_type is(
+    INIT, ASSERT_ALL_RESETS, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
+    RELEASE_MMCM_RESET, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+    MONITOR_DATA_VALID, FSM_DONE);
+    
+  signal rx_state : rx_rst_fsm_type := INIT;
+
+  constant MMCM_LOCK_CNT_MAX    : integer := 1024;
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+    
+  constant WAIT_TIMEOUT_2ms     : integer := 2000000 / STABLE_CLOCK_PERIOD;--  2 ms time-out
+  constant WAIT_TLOCK_MAX       : integer :=  100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_TIMEOUT_500us   : integer :=  500000 / STABLE_CLOCK_PERIOD;--500 us time-out
+  constant WAIT_TIMEOUT_1us     : integer :=  1000 / STABLE_CLOCK_PERIOD;  --1 us time-out
+  constant WAIT_TIMEOUT_100us    : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
+  constant WAIT_TIME_ADAPT      : integer := (37000000 /integer(2))/STABLE_CLOCK_PERIOD;
+    
+  signal init_wait_count        : integer range 0 to WAIT_MAX:=0;
+  signal init_wait_done         : std_logic := '0';
+  signal pll_reset_asserted     : std_logic := '0';
+  signal rx_fsm_reset_done_int  : std_logic := '0';
+  signal rx_fsm_reset_done_int_s2  : std_logic := '0';
+  signal rx_fsm_reset_done_int_s3  : std_logic := '0';
+   
+  signal rxresetdone_s2         : std_logic := '0'; 
+  signal rxresetdone_s3         : std_logic := '0'; 
+
+  constant MAX_RETRIES          : integer := 2**RETRY_COUNTER_BITWIDTH-1; 
+  signal retry_counter_int      : integer range 0 to MAX_RETRIES := 0;  
+  signal time_out_counter       : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+  signal recclk_mon_restart_count : integer range 0 to 3:= 0;
+  signal recclk_mon_count_reset   : std_logic := '0';
+  
+  signal reset_time_out         : std_logic := '0';
+  signal time_out_2ms           : std_logic := '0';--\Flags that the various time-out points 
+  signal time_tlock_max         : std_logic := '0';--|have been reached.
+  signal time_out_500us         : std_logic := '0';--|
+  signal time_out_1us           : std_logic := '0';--/
+  signal time_out_100us         : std_logic := '0';--/
+  signal check_tlock_max        : std_logic := '0';
+    
+  signal mmcm_lock_count        : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+  signal mmcm_lock_int          : std_logic := '0';
+  signal mmcm_lock_reclocked    : std_logic := '0';
+    
+  signal run_phase_alignment_int: std_logic := '0';
+  signal run_phase_alignment_int_s2 : std_logic := '0';
+  signal run_phase_alignment_int_s3 : std_logic := '0';
+
+  constant MAX_WAIT_BYPASS        : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
+  signal wait_bypass_count        : integer range 0 to MAX_WAIT_BYPASS-1;
+  signal time_out_wait_bypass     : std_logic := '0';
+  signal time_out_wait_bypass_s2   : std_logic := '0';
+  signal time_out_wait_bypass_s3   : std_logic := '0';
+
+  signal refclk_lost              : std_logic;
+
+  signal time_out_adapt           : std_logic := '0';   
+  signal adapt_count_reset        : std_logic := '0';   
+  signal adapt_count              : integer range 0 to WAIT_TIME_ADAPT-1;
+
+  signal      data_valid_sync: std_logic := '0';
+
+  signal      cplllock_sync: std_logic := '0';
+  signal      qplllock_sync: std_logic := '0';
+  signal      cplllock_prev: std_logic := '0';
+  signal      qplllock_prev: std_logic := '0';
+  signal      cplllock_ris_edge: std_logic := '0';
+  signal      qplllock_ris_edge: std_logic := '0';
+
+begin
+  --Alias section, signals used within this module mapped to output ports:
+  RETRY_COUNTER     <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+  RUN_PHALIGNMENT   <= run_phase_alignment_int;
+  RX_FSM_RESET_DONE <= rx_fsm_reset_done_int;
+ 
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+
+  adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate
+      time_out_adapt <= '1';
+  end generate;
+
+  adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(adapt_count_reset = '1') then
+        adapt_count    <= 0;
+        time_out_adapt <= '0';
+     elsif(adapt_count = WAIT_TIME_ADAPT -1) then
+        time_out_adapt <= '1';
+     else 
+        adapt_count    <= adapt_count + 1;  
+     end if;
+    end if;
+  end process;
+  end generate;
+
+  retries_recclk_monitor:process(STABLE_CLOCK)
+  begin
+    --This counter monitors, how many retries the RECCLK monitor
+    --runs. If during startup too many retries are necessary, the whole 
+    --initialisation-process of the transceivers gets restarted.
+    if rising_edge(STABLE_CLOCK) then  
+      if recclk_mon_count_reset = '1' then
+        recclk_mon_restart_count <= 0;
+      elsif RECCLK_MONITOR_RESTART = '1' then
+        if recclk_mon_restart_count = 3 then
+          recclk_mon_restart_count <= 0;
+        else 
+          recclk_mon_restart_count <= recclk_mon_restart_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  timeouts:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- One common large counter for generating three time-out signals.
+      -- Intermediate time-outs are derived from calculated values, based
+      -- on the period of the provided clock.
+      if reset_time_out = '1' then
+        time_out_counter  <= 0;
+        time_out_2ms      <= '0';
+        time_tlock_max    <= '0';
+        time_out_500us    <= '0';
+        time_out_1us      <= '0';
+        time_out_100us    <= '0';
+      else
+        if time_out_counter = WAIT_TIMEOUT_2ms then
+          time_out_2ms <= '1';
+        else
+          time_out_counter <= time_out_counter + 1;
+        end if;
+        
+        if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
+          time_tlock_max <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_500us then
+          time_out_500us <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_1us then
+          time_out_1us <= '1';
+        end if;
+
+        if time_out_counter = WAIT_TIMEOUT_100us then
+          time_out_100us <= '1';
+        end if;
+
+      end if;
+    end if;
+  end process;
+
+
+  mmcm_lock_wait:process(RXUSERCLK)
+  begin
+    --The lock-signal from the MMCM is not immediately used but 
+    --enabling a counter. Only when the counter hits its maximum,
+    --the MMCM is considered as "really" locked. 
+    --The counter avoids that the FSM already starts on only a 
+    --coarse lock of the MMCM (=toggling of the LOCK-signal).
+    if rising_edge(RXUSERCLK) then
+      if MMCM_LOCK = '0' then
+        mmcm_lock_count <= 0;
+        mmcm_lock_int   <= '0';
+      else       
+        if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+          mmcm_lock_count <= mmcm_lock_count + 1;
+        else
+          mmcm_lock_int <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+  -- Clock Domain Crossing
+
+  sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  RXUSERCLK,
+            data_in         =>  run_phase_alignment_int,
+            data_out        =>  run_phase_alignment_int_s2 
+         );
+
+  sync_rx_fsm_reset_done_int : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  RXUSERCLK,
+            data_in         =>  rx_fsm_reset_done_int,
+            data_out        =>  rx_fsm_reset_done_int_s2 
+         );
+
+  process(RXUSERCLK)
+  begin
+    if rising_edge(RXUSERCLK) then
+      run_phase_alignment_int_s3   <=  run_phase_alignment_int_s2;
+
+      rx_fsm_reset_done_int_s3     <=  rx_fsm_reset_done_int_s2;
+    end if;
+  end process;
+
+ sync_RXRESETDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  RXRESETDONE,
+            data_out        =>  rxresetdone_s2 
+         );
+
+  sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  time_out_wait_bypass,
+            data_out        =>  time_out_wait_bypass_s2 
+         );
+
+  sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  mmcm_lock_int,
+            data_out        =>  mmcm_lock_reclocked 
+         );
+
+  sync_data_valid : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  DATA_VALID,
+            data_out        =>  data_valid_sync
+         );
+
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+       rxresetdone_s3     <= rxresetdone_s2;
+
+       time_out_wait_bypass_s3 <=  time_out_wait_bypass_s2;
+       cplllock_prev           <=  cplllock_sync;
+       qplllock_prev           <=  qplllock_sync;
+    end if;
+  end process;
+
+ sync_CPLLLOCK : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  CPLLLOCK,
+            data_out        =>  cplllock_sync
+         );
+
+ sync_QPLLLOCK : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  QPLLLOCK,
+            data_out        =>  qplllock_sync
+         );
+
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       cplllock_ris_edge <= '0';
+     elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+       cplllock_ris_edge <= '1';
+     elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+       cplllock_ris_edge <= cplllock_ris_edge;
+     else 
+       cplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       qplllock_ris_edge <= '0';
+     elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+       qplllock_ris_edge <= '1';
+     elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+       qplllock_ris_edge <= qplllock_ris_edge;
+     else 
+       qplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+
+
+  timeout_buffer_bypass:process(RXUSERCLK)
+  begin
+    if rising_edge(RXUSERCLK) then
+      if run_phase_alignment_int_s3 = '0' then
+        wait_bypass_count     <= 0;
+        time_out_wait_bypass  <= '0';
+      elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
+        if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+          time_out_wait_bypass <= '1';
+        else
+          wait_bypass_count <= wait_bypass_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+    refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+ 
+  --FSM for resetting the GTX/GTH/GTP in the 7-series. 
+  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  --
+  -- Following steps are performed:
+  -- 1) After configuration wait for approximately 500 ns as specified in 
+  --    answer-record 43482
+  -- 2) Assert all resets on the GT and on an MMCM potentially connected. 
+  --    After that wait until a reference-clock has been detected.
+  -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+  -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+  --    Also get info from the TX-side which PLL has been reset.
+  -- 5) Wait for the RESET_DONE-signal from the GT.
+  -- 6) Signal to start the phase-alignment procedure and wait for it to 
+  --    finish.
+  -- 7) Reset-sequence has successfully run through. Signal this to the 
+  --    rest of the design by asserting RX_FSM_RESET_DONE.
+  
+  reset_fsm:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+        rx_state                <= INIT;
+        RXUSERRDY               <= '0';
+        GTRXRESET               <= '0';
+        MMCM_RESET              <= '1';
+        rx_fsm_reset_done_int   <= '0';
+        QPLL_RESET              <= '0';
+        CPLL_RESET              <= '0';
+        pll_reset_asserted      <= '0';
+        reset_time_out          <= '1';
+        retry_counter_int       <=  0;
+        run_phase_alignment_int <= '0';
+        check_tlock_max         <= '0';
+        RESET_PHALIGNMENT       <= '1';
+        recclk_mon_count_reset  <= '1';
+        adapt_count_reset       <= '1';
+        RXDFEAGCHOLD            <= '0';
+        RXDFELFHOLD             <= '0';
+        RXLPMLFHOLD             <= '0';
+        RXLPMHFHOLD             <= '0';
+
+      else
+        
+        case rx_state is
+          when INIT => 
+            --Initial state after configuration. This state will be left after
+            --approx. 500 ns and not be re-entered. 
+            if init_wait_done = '1' then
+              rx_state  <= ASSERT_ALL_RESETS;
+            end if;
+            
+          when ASSERT_ALL_RESETS => 
+            --This is the state into which the FSM will always jump back if any
+            --time-outs will occur. 
+            --The number of retries is reported on the output RETRY_COUNTER. In 
+            --case the transceiver never comes up for some reason, this machine 
+            --will still continue its best and rerun until the FPGA is turned off
+            --or the transceivers come up correctly.
+             if RX_QPLL_USED and not TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                QPLL_RESET          <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                QPLL_RESET          <= '0';
+              end if;
+            elsif not RX_QPLL_USED and TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                CPLL_RESET <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                CPLL_RESET          <= '0';
+              end if;  
+            end if;                  
+
+            RXUSERRDY               <= '0';
+            GTRXRESET               <= '1';
+            MMCM_RESET              <= '1';
+            run_phase_alignment_int <= '0';    
+            RESET_PHALIGNMENT       <= '1';
+            check_tlock_max         <= '0';
+            recclk_mon_count_reset  <= '1';
+            adapt_count_reset       <= '1';
+            
+            
+            if (RX_QPLL_USED     and not TX_QPLL_USED and (QPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or
+               (not RX_QPLL_USED and TX_QPLL_USED and (CPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or
+               (not RX_QPLL_USED and not TX_QPLL_USED and (CPLLREFCLKLOST = '0') ) or
+               (RX_QPLL_USED     and  TX_QPLL_USED and (QPLLREFCLKLOST = '0') ) then
+              rx_state  <= RELEASE_PLL_RESET;
+              reset_time_out          <= '1';
+            end if;           
+            
+          when RELEASE_PLL_RESET => 
+            --PLL-Reset of the GTX gets released and the time-out counter
+            --starts running.
+            pll_reset_asserted  <= '0';
+            reset_time_out  <= '0';
+            
+            
+            if (RX_QPLL_USED     and not TX_QPLL_USED and (qplllock_ris_edge = '1')) or
+               (not RX_QPLL_USED and TX_QPLL_USED     and (cplllock_ris_edge = '1')) then
+              rx_state                <= VERIFY_RECCLK_STABLE;
+              reset_time_out          <= '1';
+              recclk_mon_count_reset  <= '0';
+              adapt_count_reset       <= '0';
+            
+            elsif (RX_QPLL_USED     and (qplllock_sync = '1')) or
+                  (not RX_QPLL_USED and (cplllock_sync = '1')) then
+              rx_state                <= VERIFY_RECCLK_STABLE;
+              reset_time_out          <= '1';
+              recclk_mon_count_reset  <= '0';
+              adapt_count_reset       <= '0';
+            end if;
+
+            if time_out_2ms = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+
+          when VERIFY_RECCLK_STABLE =>
+            --reset_time_out  <= '0';
+            --Time-out counter is not released in this state as here the FSM
+            --does not wait for a certain period of time but checks on the number
+            --of retries in the RECCLK monitor 
+            GTRXRESET <= '0';
+            if RECCLK_STABLE = '1' then
+              rx_state        <= RELEASE_MMCM_RESET;
+              reset_time_out  <= '1';
+              
+            end if;          
+
+            if recclk_mon_restart_count = 2 then
+              --If two retries are performed in the RECCLK monitor
+              --the whole initialisation-sequence gets restarted.
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+          
+          when RELEASE_MMCM_RESET => 
+            --Release of the MMCM-reset. Waiting for the MMCM to lock.
+            reset_time_out  <= '0';
+            check_tlock_max <= '1';
+            
+            MMCM_RESET <= '0';
+            if mmcm_lock_reclocked = '1' then
+              rx_state <= WAIT_RESET_DONE;
+              reset_time_out  <= '1';
+            end if;          
+            
+            if time_tlock_max = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+            
+          when WAIT_RESET_DONE => 
+            --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
+            --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
+            if TXUSERRDY = '1' then
+               RXUSERRDY <= '1';
+            end if;
+            reset_time_out  <= '0';
+            if rxresetdone_s3 = '1' then
+              rx_state        <= DO_PHASE_ALIGNMENT; 
+              reset_time_out  <= '1';
+            end if;          
+
+            if time_out_2ms = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+          
+          when DO_PHASE_ALIGNMENT => 
+            --The direct handling of the signals for the Phase Alignment is done outside
+            --this state-machine. 
+            RESET_PHALIGNMENT       <= '0';
+            run_phase_alignment_int <= '1';
+            reset_time_out          <= '0';
+            
+            if PHALIGNMENT_DONE = '1' then
+              rx_state        <= MONITOR_DATA_VALID;
+              reset_time_out  <= '1';
+            end if;
+            
+            if time_out_wait_bypass_s3 = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <=  retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+          
+          when MONITOR_DATA_VALID => 
+              reset_time_out  <= '0';
+
+              if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0')  then
+                 rx_state              <= ASSERT_ALL_RESETS; 
+                 rx_fsm_reset_done_int <= '0';
+              elsif (data_valid_sync = '1') then
+                 rx_state              <= FSM_DONE; 
+                 rx_fsm_reset_done_int <= '0';
+                 reset_time_out        <= '1';
+              end if;
+ 
+         when FSM_DONE =>
+            reset_time_out  <= '0';
+            if data_valid_sync = '0' then
+               rx_fsm_reset_done_int <= '0';
+               reset_time_out        <= '1';
+               rx_state              <= MONITOR_DATA_VALID; 
+            elsif(time_out_1us = '1')  then
+               rx_fsm_reset_done_int <= '1';
+            end if;
+
+             if(time_out_adapt = '1') then
+               if((GT_TYPE = "GTX" ) and EQ_MODE = "DFE") then
+                  RXDFEAGCHOLD  <=  '1';
+                  RXDFELFHOLD   <=  '1';
+               else 
+                  RXDFEAGCHOLD  <=  '0';
+                  RXDFELFHOLD   <=  '0';
+                  RXLPMHFHOLD   <=  '0';
+                  RXLPMLFHOLD   <=  '0';
+               end if;
+            end if;
+
+           when OTHERS => 
+              rx_state                <= INIT;
+        end case;
+      end if;
+    end if;
+  end process;
+
+end RTL;
+
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_block.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_block.vhd
new file mode 100644
index 0000000..eb749bc
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_block.vhd
@@ -0,0 +1,144 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 2.6
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename :gtxkintex7fee80_sync_block.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--
+-- Description: Used on signals crossing from one clock domain to
+--              another, this is a flip-flop pair, with both flops
+--              placed together with RLOCs into the same slice.  Thus
+--              the routing delay between the two is minimum to safe-
+--              guard against metastability issues.
+--                     
+--
+-- Module gtxKintex7FEE80_sync_block
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity gtxkintex7fee80_sync_block is
+  generic (
+    INITIALISE : bit_vector(1 downto 0) := "00"
+  );
+  port (
+    clk         : in  std_logic;          -- clock to be sync'ed to
+    data_in     : in  std_logic;          -- Data to be 'synced'
+    data_out    : out std_logic           -- synced data
+    );
+
+end gtxkintex7fee80_sync_block;
+
+
+architecture structural of gtxkintex7fee80_sync_block is
+
+
+  -- Internal Signals
+  signal data_sync1 : std_logic;
+
+  -- These attributes will stop Vivado translating the desired flip-flops into an
+  -- SRL based shift register.
+  attribute ASYNC_REG                   : string;
+  attribute ASYNC_REG of data_sync      : label is "TRUE";
+  attribute ASYNC_REG of data_sync_reg  : label is "TRUE";
+
+ -- These attributes will stop timing errors being reported on the target flip-flop during back annotated SDF simulation.
+  attribute MSGON                      : string;
+  attribute MSGON of data_sync         : label is "FALSE";
+  attribute MSGON of data_sync_reg     : label is "FALSE";
+
+  -- These attributes will stop XST translating the desired flip-flops into an
+  -- SRL based shift register.
+  attribute shreg_extract                   : string;
+  attribute shreg_extract of data_sync      : label is "no";
+  attribute shreg_extract of data_sync_reg  : label is "no";
+
+  
+begin
+
+  data_sync : FD
+  generic map (
+    INIT => INITIALISE(0)
+  )
+  port map (
+    C    => clk,
+    D    => data_in,
+    Q    => data_sync1
+  );
+
+
+  data_sync_reg : FD
+  generic map (
+    INIT => INITIALISE(1)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync1,
+    Q    => data_out
+  );
+
+
+end structural;
+
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_pulse.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_pulse.vhd
new file mode 100644
index 0000000..c9ede59
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_sync_pulse.vhd
@@ -0,0 +1,157 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 2.6
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename :gtxkintex7fee80_sync_pulse.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--
+-- Description: Used on signals crossing from faster clock domain 
+--                     
+--
+-- Module gtxKintex7FEE80_sync_pulse
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxkintex7fee80_sync_pulse is     
+  Generic( 
+           C_NUM_SRETCH_REGS                  : integer  := 3;
+           C_NUM_SYNC_REGS                    : integer  := 3
+         );     
+
+    Port ( 
+  -- Clock and Reset
+           CLK          : in  STD_LOGIC;             
+  -- User Interface
+           USER_DONE    : out STD_LOGIC := '0';     
+  -- GT Interface
+           GT_DONE      : in  STD_LOGIC              
+           
+           );
+end gtxkintex7fee80_sync_pulse;
+
+architecture RTL of gtxkintex7fee80_sync_pulse is
+
+-- ---------------------------------------------------------------------------
+-- Wire and Register Declaration
+-- ---------------------------------------------------------------------------
+signal stretch_r : std_logic_vector (C_NUM_SRETCH_REGS-1 downto 0):= (others=>'0');
+signal sync1_r   : std_logic_vector (C_NUM_SYNC_REGS-1 downto 0):= (others=>'0');
+signal sync2_r   : std_logic_vector (C_NUM_SYNC_REGS-1 downto 0):= (others=>'0');
+
+  -- These attributes will stop Vivado translating the desired flip-flops into an
+  -- SRL based shift register.
+  attribute ASYNC_REG                       : string;
+  attribute ASYNC_REG of sync1_r            : signal is "TRUE";
+  attribute ASYNC_REG of sync2_r            : signal is "TRUE";
+
+ -- These attributes will stop XST translating the desired flip-flops into an
+  -- SRL based shift register.
+  attribute shreg_extract                   : string;
+  attribute shreg_extract of sync1_r        : signal is "no";
+  attribute shreg_extract of sync2_r        : signal is "no";
+
+
+begin
+------------------------------------------------------------------------------
+-- Stretch GT_DONE Signal
+------------------------------------------------------------------------------
+     process (CLK,GT_DONE)
+      begin
+         if (GT_DONE = '0') then
+           stretch_r <= (others=>'0');
+         elsif (CLK'event and CLK = '1') then
+           stretch_r <= ('1' & stretch_r(C_NUM_SRETCH_REGS-1 downto 1));
+       end if;
+      end process;     
+
+------------------------------------------------------------------------------
+-- Synchronizers
+------------------------------------------------------------------------------
+     process (CLK)
+      begin
+         if (CLK'event and CLK = '1') then
+           sync1_r <= (stretch_r(0) & sync1_r(C_NUM_SYNC_REGS-1 downto 1));
+         end if;
+      end process;     
+
+     process (CLK)
+      begin
+         if (CLK'event and CLK = '1') then
+           sync2_r <= (GT_DONE & sync2_r(C_NUM_SYNC_REGS-1 downto 1));
+         end if;
+      end process;     
+
+------------------------------------------------------------------------------
+-- Final Flop Stage with AND of both synchronizers - keeps USER_DONE low 
+-- when input is low for many cycles...
+------------------------------------------------------------------------------
+     process (CLK)
+      begin
+         if (CLK'event and CLK = '1') then
+           USER_DONE <= sync1_r(0) and sync2_r(0);
+         end if;
+      end process;     
+
+end RTL;
+
+
+ 
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_top.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_top.vhd
new file mode 100644
index 0000000..b6dcc22
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_top.vhd
@@ -0,0 +1,929 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 2.6
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtxkintex7fee80_init.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module gtxKintex7FEE80_init
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity gtxKintex7FEE80_top is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";          -- simulation setting for GT SecureIP model
+    EXAMPLE_SIMULATION                      : integer   := 0;               -- Set to 1 for simulation
+    STABLE_CLOCK_PERIOD                     : integer   := 12;               --Period of the stable clock driving this state-machine, unit is [ns]
+    EXAMPLE_USE_CHIPSCOPE                   : integer   := 0                -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_IN                           : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    GT0_CPLLFBCLKLOST_OUT                   : out  std_logic;
+    GT0_CPLLLOCK_OUT                        : out  std_logic;
+    GT0_CPLLLOCKDETCLK_IN                   : in   std_logic;
+    GT0_CPLLRESET_IN                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    GT0_GTREFCLK0_IN                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    GT0_DRPADDR_IN                          : in   std_logic_vector(8 downto 0);
+    GT0_DRPCLK_IN                           : in   std_logic;
+    GT0_DRPDI_IN                            : in   std_logic_vector(15 downto 0);
+    GT0_DRPDO_OUT                           : out  std_logic_vector(15 downto 0);
+    GT0_DRPEN_IN                            : in   std_logic;
+    GT0_DRPRDY_OUT                          : out  std_logic;
+    GT0_DRPWE_IN                            : in   std_logic;
+    --------------------- RX Initialization and Reset Ports --------------------
+    GT0_RXUSERRDY_IN                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    GT0_EYESCANDATAERROR_OUT                : out  std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	 GT0_RXCDRRESET_IN                       : in  std_logic;
+    GT0_RXCDRLOCK_OUT                       : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    GT0_RXUSRCLK_IN                         : in   std_logic;
+    GT0_RXUSRCLK2_IN                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    GT0_RXDATA_OUT                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    GT0_RXDISPERR_OUT                       : out  std_logic_vector(1 downto 0);
+    GT0_RXNOTINTABLE_OUT                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    GT0_GTXRXP_IN                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GT0_GTXRXN_IN                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    GT0_RXPHMONITOR_OUT                     : out  std_logic_vector(4 downto 0);
+    GT0_RXPHSLIPMONITOR_OUT                 : out  std_logic_vector(4 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    GT0_RXOUTCLK_OUT                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GT0_GTRXRESET_IN                        : in   std_logic;
+    GT0_RXPMARESET_IN                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    GT0_RXCHARISK_OUT                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    GT0_RXRESETDONE_OUT                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GT0_GTTXRESET_IN                        : in   std_logic;
+    GT0_TXUSERRDY_IN                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    GT0_TXUSRCLK_IN                         : in   std_logic;
+    GT0_TXUSRCLK2_IN                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    GT0_TXDATA_IN                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    GT0_GTXTXN_OUT                          : out  std_logic;
+    GT0_GTXTXP_OUT                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    GT0_TXOUTCLK_OUT                        : out  std_logic;
+    GT0_TXOUTCLKFABRIC_OUT                  : out  std_logic;
+    GT0_TXOUTCLKPCS_OUT                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    GT0_TXCHARISK_IN                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    GT0_TXRESETDONE_OUT                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+    ---------------------- Common Block  - Ref Clock Ports ---------------------
+    GT0_GTREFCLK0_COMMON_IN                 : in   std_logic;
+    ------------------------- Common Block - QPLL Ports ------------------------
+    GT0_QPLLLOCK_OUT                        : out  std_logic;
+    GT0_QPLLLOCKDETCLK_IN                   : in   std_logic;
+    GT0_QPLLRESET_IN                        : in   std_logic;
+		testword0             : out  std_logic_vector(35 downto 0) := (others => '0')
+
+
+);
+
+end gtxKintex7FEE80_top;
+    
+architecture RTL of gtxKintex7FEE80_top is
+
+--**************************Component Declarations*****************************
+
+
+component gtxKintex7FEE80 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP    : string    := "FALSE" -- Set to 1 to speed up sim reset
+
+);
+port
+(
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X1Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    GT0_CPLLFBCLKLOST_OUT                   : out  std_logic;
+    GT0_CPLLLOCK_OUT                        : out  std_logic;
+    GT0_CPLLLOCKDETCLK_IN                   : in   std_logic;
+    GT0_CPLLREFCLKLOST_OUT                  : out  std_logic;
+    GT0_CPLLRESET_IN                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    GT0_GTREFCLK0_IN                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    GT0_DRPADDR_IN                          : in   std_logic_vector(8 downto 0);
+    GT0_DRPCLK_IN                           : in   std_logic;
+    GT0_DRPDI_IN                            : in   std_logic_vector(15 downto 0);
+    GT0_DRPDO_OUT                           : out  std_logic_vector(15 downto 0);
+    GT0_DRPEN_IN                            : in   std_logic;
+    GT0_DRPRDY_OUT                          : out  std_logic;
+    GT0_DRPWE_IN                            : in   std_logic;
+    --------------------- RX Initialization and Reset Ports --------------------
+    GT0_RXUSERRDY_IN                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    GT0_EYESCANDATAERROR_OUT                : out  std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	 GT0_RXCDRRESET_IN                       : in  std_logic;
+    GT0_RXCDRLOCK_OUT                       : out  std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    GT0_RXUSRCLK_IN                         : in   std_logic;
+    GT0_RXUSRCLK2_IN                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    GT0_RXDATA_OUT                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    GT0_RXDISPERR_OUT                       : out  std_logic_vector(1 downto 0);
+    GT0_RXNOTINTABLE_OUT                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    GT0_GTXRXP_IN                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    GT0_GTXRXN_IN                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    GT0_RXDLYEN_IN                          : in   std_logic;
+    GT0_RXDLYSRESET_IN                      : in   std_logic;
+    GT0_RXDLYSRESETDONE_OUT                 : out  std_logic;
+    GT0_RXPHALIGN_IN                        : in   std_logic;
+    GT0_RXPHALIGNDONE_OUT                   : out  std_logic;
+    GT0_RXPHALIGNEN_IN                      : in   std_logic;
+    GT0_RXPHDLYRESET_IN                     : in   std_logic;
+    GT0_RXPHMONITOR_OUT                     : out  std_logic_vector(4 downto 0);
+    GT0_RXPHSLIPMONITOR_OUT                 : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    GT0_RXLPMHFHOLD_IN                      : in   std_logic;
+    GT0_RXLPMLFHOLD_IN                      : in   std_logic;
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    GT0_RXOUTCLK_OUT                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    GT0_GTRXRESET_IN                        : in   std_logic;
+    GT0_RXPCSRESET_IN                       : in   std_logic;
+    GT0_RXPMARESET_IN                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    GT0_RXCHARISK_OUT                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    GT0_RXRESETDONE_OUT                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    GT0_GTTXRESET_IN                        : in   std_logic;
+    GT0_TXUSERRDY_IN                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    GT0_TXUSRCLK_IN                         : in   std_logic;
+    GT0_TXUSRCLK2_IN                        : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    GT0_TXDLYEN_IN                          : in   std_logic;
+    GT0_TXDLYSRESET_IN                      : in   std_logic;
+    GT0_TXDLYSRESETDONE_OUT                 : out  std_logic;
+    GT0_TXPHALIGN_IN                        : in   std_logic;
+    GT0_TXPHALIGNDONE_OUT                   : out  std_logic;
+    GT0_TXPHALIGNEN_IN                      : in   std_logic;
+    GT0_TXPHDLYRESET_IN                     : in   std_logic;
+    GT0_TXPHINIT_IN                         : in   std_logic;
+    GT0_TXPHINITDONE_OUT                    : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    GT0_TXDATA_IN                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    GT0_GTXTXN_OUT                          : out  std_logic;
+    GT0_GTXTXP_OUT                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    GT0_TXOUTCLK_OUT                        : out  std_logic;
+    GT0_TXOUTCLKFABRIC_OUT                  : out  std_logic;
+    GT0_TXOUTCLKPCS_OUT                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    GT0_TXCHARISK_IN                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    GT0_TXRESETDONE_OUT                     : out  std_logic;
+   
+
+    --____________________________COMMON PORTS________________________________
+    ---------------------- Common Block  - Ref Clock Ports ---------------------
+    GT0_GTREFCLK0_COMMON_IN                 : in   std_logic;
+    ------------------------- Common Block - QPLL Ports ------------------------
+    GT0_QPLLLOCK_OUT                        : out  std_logic;
+    GT0_QPLLLOCKDETCLK_IN                   : in   std_logic;
+    GT0_QPLLREFCLKLOST_OUT                  : out  std_logic;
+    GT0_QPLLRESET_IN                        : in   std_logic
+
+);
+end component;
+
+component gtxKintex7FEE80_TX_STARTUP_FSM
+  Generic(
+           GT_TYPE                  : string := "GTX";
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+            TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient              
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           TXUSERCLK                : in  STD_LOGIC;              --TXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;              --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;              --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;              --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the CPLL of the GT
+           TXRESETDONE              : in  STD_LOGIC;      
+           MMCM_LOCK                : in  STD_LOGIC;      
+           GTTXRESET                : out STD_LOGIC:='0';      
+           MMCM_RESET               : out STD_LOGIC:='0';      
+           QPLL_RESET               : out STD_LOGIC:='0';        --Reset QPLL
+           CPLL_RESET               : out STD_LOGIC:='0';        --Reset CPLL
+           TX_FSM_RESET_DONE        : out STD_LOGIC:='0';        --Reset-sequence has sucessfully been finished.
+           TXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC:='0';
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';
+           PHALIGNMENT_DONE         : in  STD_LOGIC;
+           
+           RETRY_COUNTER            : out  STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end component;
+
+component gtxKintex7FEE80_RX_STARTUP_FSM
+  Generic(
+           EXAMPLE_SIMULATION       : integer := 0;
+           EQ_MODE                  : string := "DFE";
+           GT_TYPE                  : string := "GTX";
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient                         
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;        --Stable Clock, either a stable clock from the PCB
+                                                            --or reference-clock present at startup.
+           RXUSERCLK                : in  STD_LOGIC;        --RXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;        --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;        --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;        --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the CPLL of the GT
+           RXRESETDONE              : in  STD_LOGIC;
+           MMCM_LOCK                : in  STD_LOGIC;
+           RECCLK_STABLE            : in  STD_LOGIC;
+           RECCLK_MONITOR_RESTART   : in  STD_LOGIC;
+           DATA_VALID               : in  STD_LOGIC;
+           TXUSERRDY                : in  STD_LOGIC;       --TXUSERRDY from GT 
+           DONT_RESET_ON_DATA_ERROR : in  STD_LOGIC;
+           GTRXRESET                : out STD_LOGIC:='0';
+           MMCM_RESET               : out STD_LOGIC:='0';
+           QPLL_RESET               : out STD_LOGIC:='0';  --Reset QPLL (only if RX uses QPLL)
+           CPLL_RESET               : out STD_LOGIC:='0';  --Reset CPLL (only if RX uses CPLL)
+           RX_FSM_RESET_DONE        : out STD_LOGIC:='0';  --Reset-sequence has sucessfully been finished.
+           RXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC;
+           PHALIGNMENT_DONE         : in  STD_LOGIC; 
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';           
+           RXDFEAGCHOLD             : out STD_LOGIC;
+           RXDFELFHOLD              : out STD_LOGIC;
+           RXLPMLFHOLD              : out STD_LOGIC;
+           RXLPMHFHOLD              : out STD_LOGIC;
+           RETRY_COUNTER            : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end component;
+
+
+
+
+component gtxKintex7FEE80_AUTO_PHASE_ALIGN     
+  Generic(
+           GT_TYPE                  : string := "GTX"
+         );
+    port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RUN_PHALIGNMENT          : in  STD_LOGIC;              --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC;              -- Auto phase-alignment performed sucessfully
+           PHALIGNDONE              : in  STD_LOGIC;              --\ Phase-alignment signals from and to the
+           DLYSRESET                : out STD_LOGIC;              -- |transceiver.
+           DLYSRESETDONE            : in  STD_LOGIC;              --/
+           RECCLKSTABLE             : in  STD_LOGIC               --/on the RX-side.
+           
+           );
+end component;
+
+
+component gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN 
+  Generic( NUMBER_OF_LANES          : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
+           MASTER_LANE_ID           : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RESET_PHALIGNMENT        : in  STD_LOGIC;
+           RUN_PHALIGNMENT          : in  STD_LOGIC;
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Manual phase-alignment performed sucessfully  
+           TXDLYSRESET              : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXDLYSRESETDONE          : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXPHINIT                 : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXPHINITDONE             : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXPHALIGN                : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXPHALIGNDONE            : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXDLYEN                  : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+           );
+end component;
+
+component gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN 
+  Generic( NUMBER_OF_LANES          : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
+           MASTER_LANE_ID           : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RESET_PHALIGNMENT        : in  STD_LOGIC;
+           RUN_PHALIGNMENT          : in  STD_LOGIC;
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Manual phase-alignment performed sucessfully    
+           RXDLYSRESET              : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           RXDLYSRESETDONE          : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           RXPHALIGN                : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           RXPHALIGNDONE            : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           RXDLYEN                  : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+           );
+end component;
+
+  function get_cdrlock_time(is_sim : in integer) return integer is
+    variable lock_time: integer;
+  begin
+    if (is_sim = 1) then
+      lock_time := 1000;
+    else
+      lock_time := 50000 / integer(2); --Typical CDR lock time is 50,000UI as per DS183
+    end if;
+    return lock_time;
+  end function;
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+    constant RX_CDRLOCK_TIME      : integer := get_cdrlock_time(EXAMPLE_SIMULATION);       -- 200us
+    constant WAIT_TIME_CDRLOCK    : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD;      -- 200 us time-out
+
+    -------------------------- GT Wrapper Wires ------------------------------
+    signal   gt0_cpllreset_i                 : std_logic;
+    signal   gt0_cpllreset_t                 : std_logic;
+    signal   gt0_cpllrefclklost_i            : std_logic;
+    signal   gt0_cplllock_i                  : std_logic;
+    signal   gt0_txresetdone_i               : std_logic;
+    signal   gt0_rxresetdone_i               : std_logic;
+    signal   gt0_gttxreset_i                 : std_logic;
+    signal   gt0_gttxreset_t                 : std_logic;
+    signal   gt0_gtrxreset_i                 : std_logic;
+    signal   gt0_gtrxreset_t                 : std_logic;
+    signal   gt0_rxpcsreset_i                : std_logic;
+    signal   gt0_rxdfelpmreset_i             : std_logic;
+    signal   gt0_txuserrdy_i                 : std_logic;
+    signal   gt0_txuserrdy_t                 : std_logic;
+    signal   gt0_rxuserrdy_i                 : std_logic;
+    signal   gt0_rxuserrdy_t                 : std_logic;
+
+    signal   gt0_rxdfeagchold_i              : std_logic;
+    signal   gt0_rxdfelfhold_i               : std_logic;
+    signal   gt0_rxlpmlfhold_i               : std_logic;
+    signal   gt0_rxlpmhfhold_i               : std_logic;
+
+
+
+    signal   gt0_qpllreset_i                 : std_logic;
+    signal   gt0_qpllreset_t                 : std_logic;
+    signal   gt0_qpllrefclklost_i            : std_logic;
+    signal   gt0_qplllock_i                  : std_logic;
+
+
+    ------------------------------- Global Signals -----------------------------
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_vcc_i                   : std_logic;
+    signal   gt0_txphaligndone_i             : std_logic;
+    signal   gt0_txdlysreset_i               : std_logic;
+    signal   gt0_txdlysresetdone_i           : std_logic;
+    signal   gt0_txphdlyreset_i              : std_logic;
+    signal   gt0_txphalignen_i               : std_logic;
+    signal   gt0_txdlyen_i                   : std_logic;
+    signal   gt0_txphalign_i                 : std_logic;
+    signal   gt0_txphinit_i                  : std_logic;
+    signal   gt0_txphinitdone_i              : std_logic;
+    signal   gt0_run_tx_phalignment_i        : std_logic;
+    signal   gt0_rst_tx_phalignment_i        : std_logic;
+    signal   gt0_tx_phalignment_done_i       : std_logic;
+
+    signal   gt0_rxoutclk_i                  : std_logic;
+    signal   gt0_recclk_stable_i             : std_logic;
+    signal   gt0_rxphaligndone_i             : std_logic;
+    signal   gt0_rxdlysreset_i               : std_logic;
+    signal   gt0_rxdlysresetdone_i           : std_logic;
+    signal   gt0_rxphdlyreset_i              : std_logic;
+    signal   gt0_rxphalignen_i               : std_logic;
+    signal   gt0_rxdlyen_i                   : std_logic;
+    signal   gt0_rxphalign_i                 : std_logic;
+    signal   gt0_run_rx_phalignment_i        : std_logic;
+    signal   gt0_rst_rx_phalignment_i        : std_logic;
+    signal   gt0_rx_phalignment_done_i       : std_logic;
+
+
+
+    --------------------------- TX Buffer Bypass Signals --------------------
+    signal  mstr0_txsyncallin_i  :   std_logic;
+    signal  U0_TXDLYEN           :   std_logic_vector(0 downto 0);
+    signal  U0_TXDLYSRESET       :   std_logic_vector(0 downto 0);
+    signal  U0_TXDLYSRESETDONE   :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHINIT          :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHINITDONE      :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHALIGN         :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHALIGNDONE     :   std_logic_vector(0 downto 0);
+    signal  U0_run_tx_phalignment_i :   std_logic;
+    signal  U0_rst_tx_phalignment_i :   std_logic;
+
+
+    --------------------------- RX Buffer Bypass Signals --------------------
+    signal   rxmstr0_rxsyncallin_i :   std_logic;
+
+
+    signal   rx_cdrlock_counter  :   integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
+    signal      rx_cdrlocked                    : std_logic;
+
+
+    signal      testword0_S             :  std_logic_vector(35 downto 0) := (others => '0');
+
+
+
+--**************************** Main Body of Code *******************************
+begin
+    --  Static signal Assigments
+    tied_to_ground_i                             <= '0';
+    tied_to_vcc_i                                <= '1';
+
+    ----------------------------- The GT Wrapper -----------------------------
+    
+    -- Use the instantiation template in the example directory to add the GT wrapper to your design.
+    -- In this example, the wrapper is wired up for basic operation with a frame generator and frame 
+    -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is 
+    -- enabled, bonding should occur after alignment.
+
+
+    gtxKintex7FEE80_i : gtxKintex7FEE80
+    generic map
+    (
+        WRAPPER_SIM_GTRESET_SPEEDUP     =>      EXAMPLE_SIM_GTRESET_SPEEDUP
+    )
+    port map
+    (
+  
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y0)
+
+        --------------------------------- CPLL Ports -------------------------------
+        GT0_CPLLFBCLKLOST_OUT           =>      GT0_CPLLFBCLKLOST_OUT,
+        GT0_CPLLLOCK_OUT                =>      gt0_cplllock_i,
+        GT0_CPLLLOCKDETCLK_IN           =>      GT0_CPLLLOCKDETCLK_IN,
+        GT0_CPLLREFCLKLOST_OUT          =>      gt0_cpllrefclklost_i,
+        GT0_CPLLRESET_IN                =>      gt0_cpllreset_i,
+        -------------------------- Channel - Clocking Ports ------------------------
+        GT0_GTREFCLK0_IN                =>      GT0_GTREFCLK0_IN,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        GT0_DRPADDR_IN                  =>      GT0_DRPADDR_IN,
+        GT0_DRPCLK_IN                   =>      GT0_DRPCLK_IN,
+        GT0_DRPDI_IN                    =>      GT0_DRPDI_IN,
+        GT0_DRPDO_OUT                   =>      GT0_DRPDO_OUT,
+        GT0_DRPEN_IN                    =>      GT0_DRPEN_IN,
+        GT0_DRPRDY_OUT                  =>      GT0_DRPRDY_OUT,
+        GT0_DRPWE_IN                    =>      GT0_DRPWE_IN,
+        --------------------- RX Initialization and Reset Ports --------------------
+        GT0_RXUSERRDY_IN                =>      gt0_rxuserrdy_i,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        GT0_EYESCANDATAERROR_OUT        =>      GT0_EYESCANDATAERROR_OUT,
+        ------------------------- Receive Ports - CDR Ports ------------------------
+		  GT0_RXCDRRESET_IN               =>      GT0_RXCDRRESET_IN,
+        GT0_RXCDRLOCK_OUT               =>      GT0_RXCDRLOCK_OUT,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        GT0_RXUSRCLK_IN                 =>      GT0_RXUSRCLK_IN,
+        GT0_RXUSRCLK2_IN                =>      GT0_RXUSRCLK2_IN,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        GT0_RXDATA_OUT                  =>      GT0_RXDATA_OUT,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        GT0_RXDISPERR_OUT               =>      GT0_RXDISPERR_OUT,
+        GT0_RXNOTINTABLE_OUT            =>      GT0_RXNOTINTABLE_OUT,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        GT0_GTXRXP_IN                   =>      GT0_GTXRXP_IN,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GT0_GTXRXN_IN                   =>      GT0_GTXRXN_IN,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        GT0_RXDLYEN_IN                  =>      '0', -- gt0_rxdlyen_i,
+        GT0_RXDLYSRESET_IN              =>      '1', -- gt0_rxdlysreset_i,
+        GT0_RXDLYSRESETDONE_OUT         =>      gt0_rxdlysresetdone_i,
+        GT0_RXPHALIGN_IN                =>      '0', -- gt0_rxphalign_i,
+        GT0_RXPHALIGNDONE_OUT           =>      gt0_rxphaligndone_i,
+        GT0_RXPHALIGNEN_IN              =>      '1', -- gt0_rxphalignen_i,
+        GT0_RXPHDLYRESET_IN             =>      '1', -- gt0_rxphdlyreset_i,
+        GT0_RXPHMONITOR_OUT             =>      GT0_RXPHMONITOR_OUT,
+        GT0_RXPHSLIPMONITOR_OUT         =>      GT0_RXPHSLIPMONITOR_OUT,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        GT0_RXLPMHFHOLD_IN              =>      gt0_rxlpmhfhold_i,
+        GT0_RXLPMLFHOLD_IN              =>      gt0_rxlpmlfhold_i,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        GT0_RXOUTCLK_OUT                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GT0_GTRXRESET_IN                =>      gt0_gtrxreset_i,
+        GT0_RXPCSRESET_IN               =>      gt0_rxpcsreset_i,
+        GT0_RXPMARESET_IN               =>      GT0_RXPMARESET_IN,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        GT0_RXCHARISK_OUT               =>      GT0_RXCHARISK_OUT,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        GT0_RXRESETDONE_OUT             =>      gt0_rxresetdone_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        GT0_GTTXRESET_IN                =>      gt0_gttxreset_i,
+        GT0_TXUSERRDY_IN                =>      gt0_txuserrdy_i,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        GT0_TXUSRCLK_IN                 =>      GT0_TXUSRCLK_IN,
+        GT0_TXUSRCLK2_IN                =>      GT0_TXUSRCLK2_IN,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        GT0_TXDLYEN_IN                  =>      gt0_txdlyen_i,
+        GT0_TXDLYSRESET_IN              =>      gt0_txdlysreset_i,
+        GT0_TXDLYSRESETDONE_OUT         =>      gt0_txdlysresetdone_i,
+        GT0_TXPHALIGN_IN                =>      gt0_txphalign_i,
+        GT0_TXPHALIGNDONE_OUT           =>      gt0_txphaligndone_i,
+        GT0_TXPHALIGNEN_IN              =>      gt0_txphalignen_i,
+        GT0_TXPHDLYRESET_IN             =>      gt0_txphdlyreset_i,
+        GT0_TXPHINIT_IN                 =>      gt0_txphinit_i,
+        GT0_TXPHINITDONE_OUT            =>      gt0_txphinitdone_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        GT0_TXDATA_IN                   =>      GT0_TXDATA_IN,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        GT0_GTXTXN_OUT                  =>      GT0_GTXTXN_OUT,
+        GT0_GTXTXP_OUT                  =>      GT0_GTXTXP_OUT,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        GT0_TXOUTCLK_OUT                =>      GT0_TXOUTCLK_OUT,
+        GT0_TXOUTCLKFABRIC_OUT          =>      GT0_TXOUTCLKFABRIC_OUT,
+        GT0_TXOUTCLKPCS_OUT             =>      GT0_TXOUTCLKPCS_OUT,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        GT0_TXCHARISK_IN                =>      GT0_TXCHARISK_IN,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        GT0_TXRESETDONE_OUT             =>      gt0_txresetdone_i,
+
+
+
+
+    --____________________________COMMON PORTS________________________________
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GT0_GTREFCLK0_COMMON_IN         =>      GT0_GTREFCLK0_COMMON_IN,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        GT0_QPLLLOCK_OUT                =>      gt0_qplllock_i,
+        GT0_QPLLLOCKDETCLK_IN           =>      GT0_QPLLLOCKDETCLK_IN,
+        GT0_QPLLREFCLKLOST_OUT          =>      gt0_qpllrefclklost_i,
+        GT0_QPLLRESET_IN                =>      gt0_qpllreset_i
+
+    );
+
+    gt0_rxpcsreset_i                             <= tied_to_ground_i;
+
+    gt0_rxdfelpmreset_i                          <= tied_to_ground_i;
+
+
+
+
+    GT0_CPLLLOCK_OUT                             <= gt0_cplllock_i;
+    GT0_TXRESETDONE_OUT                          <= gt0_txresetdone_i;
+    GT0_RXRESETDONE_OUT                          <= gt0_rxresetdone_i;
+    GT0_RXOUTCLK_OUT                             <= gt0_rxoutclk_i;
+    GT0_QPLLLOCK_OUT                             <= gt0_qplllock_i;
+
+chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
+    gt0_cpllreset_i                              <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
+    gt0_gttxreset_i                              <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
+    gt0_gtrxreset_i                              <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
+    gt0_txuserrdy_i                              <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
+    gt0_rxuserrdy_i                              <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
+    gt0_qpllreset_i                              <= GT0_QPLLRESET_IN or gt0_qpllreset_t;
+end generate chipscope;
+
+no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
+    gt0_cpllreset_i                              <= gt0_cpllreset_t;
+    gt0_gttxreset_i                              <= gt0_gttxreset_t;
+    gt0_gtrxreset_i                              <= gt0_gtrxreset_t;
+    gt0_txuserrdy_i                              <= gt0_txuserrdy_t;
+    gt0_rxuserrdy_i                              <= gt0_rxuserrdy_t;
+    gt0_qpllreset_i                              <= gt0_qpllreset_t;
+end generate no_chipscope;
+
+
+gt0_txresetfsm_i:  gtxKintex7FEE80_TX_STARTUP_FSM 
+
+  generic map(
+           GT_TYPE                  => "GTX", --GTX or GTH or GTP
+           STABLE_CLOCK_PERIOD      => STABLE_CLOCK_PERIOD,           -- Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   => 8, 
+           TX_QPLL_USED             => FALSE ,                       -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             => FALSE,                        -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   => TRUE                 -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                     -- is enough. For single-lane applications the automatic alignment is 
+                                                                     -- sufficient              
+             )     
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        TXUSERCLK                       =>      GT0_TXUSRCLK_IN,
+        SOFT_RESET                      =>      SOFT_RESET_IN,
+        QPLLREFCLKLOST                  =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      gt0_cpllrefclklost_i,
+        QPLLLOCK                        =>      tied_to_vcc_i,
+        CPLLLOCK                        =>      gt0_cplllock_i,
+        TXRESETDONE                     =>      gt0_txresetdone_i,
+        MMCM_LOCK                       =>      GT0_TX_MMCM_LOCK_IN,
+        GTTXRESET                       =>      gt0_gttxreset_t,
+        MMCM_RESET                      =>      GT0_TX_MMCM_RESET_OUT,
+        QPLL_RESET                      =>      open,
+        CPLL_RESET                      =>      gt0_cpllreset_t,
+        TX_FSM_RESET_DONE               =>      GT0_TX_FSM_RESET_DONE_OUT,
+        TXUSERRDY                       =>      gt0_txuserrdy_t,
+        RUN_PHALIGNMENT                 =>      gt0_run_tx_phalignment_i,
+        RESET_PHALIGNMENT               =>      gt0_rst_tx_phalignment_i,
+        PHALIGNMENT_DONE                =>      gt0_tx_phalignment_done_i,
+        RETRY_COUNTER                   =>      open
+           );
+
+
+
+
+
+
+gt0_rxresetfsm_i:  gtxKintex7FEE80_RX_STARTUP_FSM 
+
+  generic map(
+           EXAMPLE_SIMULATION       => EXAMPLE_SIMULATION,
+           GT_TYPE                  => "GTX", --GTX or GTH or GTP
+           EQ_MODE                  => "LPM",                 --Rx Equalization Mode - Set to DFE or LPM
+           STABLE_CLOCK_PERIOD      => STABLE_CLOCK_PERIOD,           --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   => 8, 
+           TX_QPLL_USED             => FALSE ,                       -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             => FALSE,                        -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   =>  TRUE                        -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                     -- is enough. For single-lane applications the automatic alignment is 
+                                                                     -- sufficient              
+             )     
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        RXUSERCLK                       =>      GT0_RXUSRCLK_IN,
+        SOFT_RESET                      =>      SOFT_RESET_IN,
+        DONT_RESET_ON_DATA_ERROR        =>      DONT_RESET_ON_DATA_ERROR_IN,
+        QPLLREFCLKLOST                  =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      gt0_cpllrefclklost_i,
+        QPLLLOCK                        =>      tied_to_vcc_i,
+        CPLLLOCK                        =>      gt0_cplllock_i,
+        RXRESETDONE                     =>      gt0_rxresetdone_i,
+        MMCM_LOCK                       =>      tied_to_vcc_i,
+        RECCLK_STABLE                   =>      gt0_recclk_stable_i,
+        RECCLK_MONITOR_RESTART          =>      tied_to_ground_i,
+        DATA_VALID                      =>      GT0_DATA_VALID_IN,
+        TXUSERRDY                       =>      tied_to_vcc_i,
+        GTRXRESET                       =>      gt0_gtrxreset_t,
+        MMCM_RESET                      =>      open,
+        QPLL_RESET                      =>      open,
+        CPLL_RESET                      =>      open,
+        RX_FSM_RESET_DONE               =>      GT0_RX_FSM_RESET_DONE_OUT,
+        RXUSERRDY                       =>      gt0_rxuserrdy_t,
+        RUN_PHALIGNMENT                 =>      gt0_run_rx_phalignment_i,
+        RESET_PHALIGNMENT               =>      gt0_rst_rx_phalignment_i,
+        PHALIGNMENT_DONE                =>      gt0_rx_phalignment_done_i,
+        RXDFEAGCHOLD                    =>      gt0_rxdfeagchold_i,
+        RXDFELFHOLD                     =>      gt0_rxdfelfhold_i,
+        RXLPMLFHOLD                     =>      gt0_rxlpmlfhold_i,
+        RXLPMHFHOLD                     =>      gt0_rxlpmhfhold_i,
+        RETRY_COUNTER                   =>      open
+           );
+
+
+
+  cdrlock_timeout:process(SYSCLK_IN)
+  begin
+    if rising_edge(SYSCLK_IN) then
+        if(gt0_gtrxreset_i = '1') then
+          rx_cdrlocked       <= '0';
+          rx_cdrlock_counter <=  0                        after DLY;
+        elsif (rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
+          rx_cdrlocked       <= '1';
+          rx_cdrlock_counter <= rx_cdrlock_counter        after DLY;
+        else
+          rx_cdrlock_counter <= rx_cdrlock_counter + 1    after DLY;
+        end if;
+    end if;
+  end process;
+
+gt0_recclk_stable_i                          <= rx_cdrlocked;
+
+
+
+    --------------------------- TX Buffer Bypass Logic --------------------
+    -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer.
+    -- Include the TX SYNC module in your own design if TX Buffer is bypassed.
+
+--Manual
+   gt0_tx_manual_phase_i : gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN
+   generic map
+   ( NUMBER_OF_LANES	  => 1,
+     MASTER_LANE_ID       =>  0
+   )
+   port map
+   (
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        RESET_PHALIGNMENT               =>      U0_rst_tx_phalignment_i,   --TODO
+        RUN_PHALIGNMENT                 =>      U0_run_tx_phalignment_i,      --TODO
+        PHASE_ALIGNMENT_DONE            =>      gt0_tx_phalignment_done_i,
+        TXDLYSRESET                     =>      U0_TXDLYSRESET,
+        TXDLYSRESETDONE                 =>      U0_TXDLYSRESETDONE,
+        TXPHINIT                        =>      U0_TXPHINIT,
+        TXPHINITDONE                    =>      U0_TXPHINITDONE,
+        TXPHALIGN                       =>      U0_TXPHALIGN,
+        TXPHALIGNDONE                   =>      U0_TXPHALIGNDONE,
+        TXDLYEN                         =>      U0_TXDLYEN
+   );
+
+    gt0_txphdlyreset_i                           <= tied_to_ground_i;
+    gt0_txphalignen_i                            <= tied_to_vcc_i;
+    gt0_txdlysreset_i                            <= U0_TXDLYSRESET(0);
+    gt0_txphinit_i                               <= U0_TXPHINIT(0);
+    gt0_txphalign_i                              <= U0_TXPHALIGN(0);
+    gt0_txdlyen_i                                <= U0_TXDLYEN(0);
+    U0_TXDLYSRESETDONE(0)                        <= gt0_txdlysresetdone_i;
+    U0_TXPHINITDONE(0)                           <= gt0_txphinitdone_i;
+    U0_TXPHALIGNDONE(0)                          <= gt0_txphaligndone_i;
+
+
+
+    U0_run_tx_phalignment_i    <=  gt0_run_tx_phalignment_i 
+                                             ;
+
+    U0_rst_tx_phalignment_i    <=  gt0_rst_tx_phalignment_i 
+                                             ;
+
+
+
+   --------------------------- RX Buffer Bypass Logic --------------------
+--   The RX SYNC Module drives the ports needed to Bypass the RX Buffer.
+--   Include the RX SYNC module in your own design if RX Buffer is bypassed.
+
+
+--Auto
+
+gt0_rxphdlyreset_i                           <= tied_to_ground_i; --// '1'; --// 
+gt0_rxphalignen_i                            <= tied_to_ground_i; --//'1'; --// 
+gt0_rxdlyen_i                                <= tied_to_ground_i;
+gt0_rxphalign_i                              <= tied_to_ground_i;
+
+gt0_rx_phalignment_done_i <= '1';
+gt0_rxdlysreset_i <= '1'; --//
+
+
+
+--gt0_rx_auto_phase_align_i : gtxKintex7FEE80_AUTO_PHASE_ALIGN    
+--  generic map(
+--                 GT_TYPE                  => "GTX" --GTX or GTH or GTP
+--             )
+--  port map ( 
+--        STABLE_CLOCK                    =>      SYSCLK_IN,
+--        RUN_PHALIGNMENT                 =>      gt0_run_rx_phalignment_i,
+--        PHASE_ALIGNMENT_DONE            =>      gt0_rx_phalignment_done_i,
+--        PHALIGNDONE                     =>      gt0_rxphaligndone_i,
+--        DLYSRESET                       =>      gt0_rxdlysreset_i,
+--        DLYSRESETDONE                   =>      gt0_rxdlysresetdone_i,
+--        RECCLKSTABLE                    =>      gt0_recclk_stable_i
+--     );
+
+
+
+
+
+--testword0(22) <= gt0_cplllock_i;
+--testword0(23) <= gt0_cpllrefclklost_i;
+--testword0(24) <= gt0_cpllreset_i;
+
+
+--testword0(35 downto 22) <= testword0_S(35 downto 22);
+
+--testword0(22) <= SOFT_RESET_IN;
+--testword0(23) <= gt0_cplllock_i;
+--testword0(24) <= gt0_recclk_stable_i;
+--
+--testword0(25) <= gt0_rxuserrdy_i;
+--testword0(26) <= gt0_rxdlysreset_i;
+--testword0(27) <= gt0_rxdlysresetdone_i;
+--testword0(28) <= gt0_rxphaligndone_i;
+--testword0(29) <= gt0_rxphdlyreset_i;
+--testword0(30) <= gt0_gtrxreset_i;
+--
+--testword0(31) <= gt0_rxpcsreset_i;
+--testword0(32) <= gt0_rxresetdone_i;
+--
+--
+--testword0(33) <= gt0_run_rx_phalignment_i;
+--testword0(34) <= gt0_rst_rx_phalignment_i;
+--testword0(35) <= gt0_rx_phalignment_done_i;
+
+--testword0(33) <= gt0_txresetdone_i;
+--testword0(34) <= gt0_qpllrefclklost_i;
+--testword0(35) <= gt0_qpllreset_i;
+
+--gt0_gttxreset_i
+--gt0_txuserrdy_i
+--gt0_txphaligndone_i
+--gt0_txphdlyreset_i
+
+
+
+
+end RTL;
+
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_manual_phase_align.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_manual_phase_align.vhd
new file mode 100644
index 0000000..1db8669
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_manual_phase_align.vhd
@@ -0,0 +1,380 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 2.6
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename : gtxkintex7fee80_tx_manual_phase_align.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--  Description :     This module performs TX Buffer Phase Alignment in Manual Mode.
+--                     
+--
+--
+-- Module gtxKintex7FEE80_tx_manual_phase_align
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN is
+  Generic( NUMBER_OF_LANES          : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
+           MASTER_LANE_ID           : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RESET_PHALIGNMENT        : in  STD_LOGIC;
+           RUN_PHALIGNMENT          : in  STD_LOGIC;
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Manual phase-alignment performed sucessfully  
+           TXDLYSRESET              : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXDLYSRESETDONE          : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXPHINIT                 : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXPHINITDONE             : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXPHALIGN                : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXPHALIGNDONE            : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXDLYEN                  : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+           );
+end gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN;
+
+architecture RTL of gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN is
+
+  component gtxKintex7FEE80_sync_block
+   generic (
+     INITIALISE : bit_vector(1 downto 0) := "00"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+ component  gtxkintex7fee80_sync_pulse      
+  generic( 
+           C_NUM_SRETCH_REGS                  : integer  := 3;
+           C_NUM_SYNC_REGS                    : integer  := 3
+         );     
+
+    port ( 
+           CLK          : in  STD_LOGIC;             
+           USER_DONE    : out STD_LOGIC := '0';     
+           GT_DONE      : in  STD_LOGIC              
+           
+           );
+end component;
+
+  constant VCC_VEC  : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '1');
+  constant GND_VEC  : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+
+  signal txphaligndone_prev       : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal txphaligndone_ris_edge   : std_logic_vector(NUMBER_OF_LANES-1 downto 0);
+  signal txphinitdone_prev        : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal txphinitdone_ris_edge    : std_logic_vector(NUMBER_OF_LANES-1 downto 0);
+  signal txphinitdone_store_edge  : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal txphinitdone_clear_slave : std_logic:='0';
+  signal txdlysresetdone_store    : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal txphaligndone_store      : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal txdone_clear             : std_logic:='0';
+  
+  
+  signal count_phalign_edges     : integer range 0 to 3:= 0;
+
+ 
+  signal txphaligndone_sync      : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal txphinitdone_sync       : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+  signal txdlysresetdone_sync    : std_logic_vector(NUMBER_OF_LANES-1 downto 0) :=(others => '0');
+
+  type tx_phase_align_manual_fsm is(
+    INIT, WAIT_PHRST_DONE, M_PHINIT, M_PHALIGN, M_DLYEN,
+    S_PHINIT, S_PHALIGN, M_DLYEN2, PHALIGN_DONE
+    );
+  signal tx_phalign_manual_state : tx_phase_align_manual_fsm := INIT;
+
+begin
+
+ cdc: for i in 0 to NUMBER_OF_LANES-1 generate
+ sync_TXPHALIGNDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  TXPHALIGNDONE(i),
+            data_out        =>  txphaligndone_sync(i) 
+         );
+
+  sync_TXDLYSRESETDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  TXDLYSRESETDONE(i),
+            data_out        =>  txdlysresetdone_sync(i) 
+         );
+
+ sync_TXPHINITDONE : gtxKintex7FEE80_sync_pulse
+  port map
+         (
+            CLK             =>  STABLE_CLOCK,
+            GT_DONE         =>  TXPHINITDONE(i),
+            USER_DONE       =>  txphinitdone_sync(i) 
+         );
+  end generate;
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      txphaligndone_prev  <= txphaligndone_sync;    
+      txphinitdone_prev   <= txphinitdone_sync;
+    end if;
+  end process;
+  
+  
+  rising_edge_detect: for i in 0 to NUMBER_OF_LANES-1 generate
+    txphaligndone_ris_edge(i) <= '1' when (txphaligndone_prev(i) = '0') and (txphaligndone_sync(i) = '1') else '0';
+    txphinitdone_ris_edge(i)  <= '1' when (txphinitdone_prev(i) = '0') and (txphinitdone_sync(i) = '1') else '0';
+  end generate;
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if txdone_clear = '1' then
+        txdlysresetdone_store <= (others=>'0');
+        txphaligndone_store   <= (others=>'0');
+      else
+        for i in 0 to NUMBER_OF_LANES-1 loop
+          if txdlysresetdone_sync(i) = '1' then
+            txdlysresetdone_store(i) <= '1';
+          end if;
+          if txphaligndone_ris_edge(i) = '1' then
+             txphaligndone_store(i)  <= '1';
+          end if;
+        end loop;
+      end if;
+    end if;
+  end process;
+
+
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if txphinitdone_clear_slave = '1' then
+        --Only clear the TXPHINITDONE-storage from the slaves.
+        txphinitdone_store_edge                 <= (others=>'0');
+        --The information stored on the MASTER_LANE_ID is used differently. The way txphinitdone_store_edge
+        --is coded, it will be optimised away afterwards. It is only for simplicity of the code on the checks
+        --that the master-lane is "recorded" too.
+        txphinitdone_store_edge(MASTER_LANE_ID) <= '1';
+      else
+        for i in 0 to NUMBER_OF_LANES-1 loop
+          if txphinitdone_ris_edge(i) = '1' then
+            txphinitdone_store_edge(i) <= '1';
+          end if;
+        end loop;
+      end if;
+    end if;
+  end process;
+
+
+  
+  
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if RESET_PHALIGNMENT = '1' then
+        PHASE_ALIGNMENT_DONE      <= '0';
+        TXDLYSRESET               <= (others=> '0');
+        TXPHINIT                  <= (others=> '0');
+        TXPHALIGN                 <= (others=> '0');
+        TXDLYEN                   <= (others=> '0');
+        tx_phalign_manual_state   <= INIT;
+        txphinitdone_clear_slave  <= '1';
+        txdone_clear              <= '1';
+      else
+        case tx_phalign_manual_state is
+          when INIT => 
+            PHASE_ALIGNMENT_DONE      <= '0';
+            txphinitdone_clear_slave  <= '1';
+            txdone_clear              <= '1';
+            if RUN_PHALIGNMENT = '1' then
+              --TXDLYSRESET is toggled to '1'
+              TXDLYSRESET               <= (others=> '1');
+              txphinitdone_clear_slave  <= '0';
+              txdone_clear              <= '0';
+              tx_phalign_manual_state   <= WAIT_PHRST_DONE;
+            end if;       
+            
+          when WAIT_PHRST_DONE => 
+            --Assert TXDLYSRESET for all lanes, hold high until 
+            --TXDLYSRESETDONE of the respective lane is asserted.
+            for i in 0 to NUMBER_OF_LANES - 1 loop
+              if txdlysresetdone_store(i) = '1' then
+                --Deassert TXDLYSRESET for the lane in which 
+                --the TXDLYSRESETDONE is asserted:
+                TXDLYSRESET(i) <= '0';
+              end if;
+            end loop;
+            if txdlysresetdone_store = VCC_VEC then
+              --When all TXDLYSRESETDONE-signals are asserted, move 
+              --to the next state.
+              tx_phalign_manual_state   <= M_PHINIT;
+            end if;
+            
+          when M_PHINIT => 
+            --Assert TXPHINIT on the master and hold high until a
+            --rising edge on TXPHINITDONE is detected:
+            TXPHINIT(MASTER_LANE_ID) <= '1';
+            if txphinitdone_ris_edge(MASTER_LANE_ID) = '1' then
+              --Then deassert TXPHINIT and move to the next state.
+              TXPHINIT(MASTER_LANE_ID)  <= '0';
+              tx_phalign_manual_state   <= M_PHALIGN;
+            end if;
+            
+          when M_PHALIGN => 
+            --Assert TXPHALIGN on the master and hold high until a 
+            --rising edge on TXPHALIGNDONE is detected:
+            TXPHALIGN(MASTER_LANE_ID) <= '1';
+            if txphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+              --Then dassert TXPHALIGN and move to the next state.
+              TXPHALIGN(MASTER_LANE_ID) <= '0';
+              tx_phalign_manual_state   <= M_DLYEN;
+            end if;
+            
+          when M_DLYEN => 
+            --Assert TXDLYEN on the master and hold high until a
+            --rising edge on TXPHALIGNDONE is detected.
+            TXDLYEN(MASTER_LANE_ID) <= '1';
+            if txphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+              --Then deassert TXDLYEN and move to the next state.
+              if(NUMBER_OF_LANES > 1) then
+                TXDLYEN(MASTER_LANE_ID)   <= '0';
+                tx_phalign_manual_state   <= S_PHINIT;
+              else
+                tx_phalign_manual_state   <= PHALIGN_DONE;
+              end if;
+            end if;
+          when S_PHINIT => 
+            --Assert TXPHINIT for all slave lane(s). Hold this 
+            --signal High until TXPHINITDONE of the respective 
+            --slave lane is asserted.
+            TXPHINIT                 <= (others=>'1');--\Assert only the PHINIT-signal of
+            TXPHINIT(MASTER_LANE_ID) <= '0';          --/the slaves.
+
+            for i in 0 to NUMBER_OF_LANES - 1 loop
+              if txphinitdone_store_edge(i) = '1' then
+                --Deassert TXPHINIT for the slave lane in which 
+                --the TXPHINITDONE is asserted.
+                TXPHINIT(i) <= '0';
+              end if;
+            end loop;
+            --if txphinitdone_store_edge = VCC_VEC and txphinitdone_ris_edge /= GND_VEC then
+            if txphinitdone_store_edge = VCC_VEC then
+              --When all TXPHINITDONE-signals are high and at least one rising edge
+              --has been detected, move to the next state.
+              --The reason for checking of the occurance of at least one rising edge
+              --is to avoid the potential direct move where TXPHINITDONE might not 
+              --be going low fast enough. 
+              tx_phalign_manual_state   <= S_PHALIGN;
+            end if;
+             
+          when S_PHALIGN =>
+            --Assert TXPHALIGN for all slave lane(s). Hold this signal High 
+            --until TXPHALIGNDONE of the respective slave lane is asserted.
+            TXPHALIGN                 <= (others=>'1');--again only assertion for slave
+            TXPHALIGN(MASTER_LANE_ID) <= '0';          --but not for master
+
+            for i in 0 to NUMBER_OF_LANES - 1 loop
+              --if txphaligndone_ris_edge(i) = '1' then
+              if txphaligndone_store(i) = '1' then
+                --Deassert TXPHALIGN for the slave lane in which the 
+                --TXPHALIGNDONE is asserted.
+                TXPHALIGN(i) <= '0';
+              end if;
+            end loop;
+            --if txphaligndone_store = VCC_VEC and txphaligndone_ris_edge /= GND_VEC then
+            if txphaligndone_store = VCC_VEC  then
+              --When all TXPHALIGNDONE-signals are asserted high, move to the next
+              --state.
+              tx_phalign_manual_state   <= M_DLYEN2;
+            end if;
+            
+          when M_DLYEN2 => 
+            --Assert TXDLYEN for the master lane. This causes TXPHALIGNDONE of 
+            --the master lane to be deasserted.
+            TXDLYEN(MASTER_LANE_ID) <= '1';
+            if txphaligndone_ris_edge(MASTER_LANE_ID) = '1' then
+              --Wait until TXPHALIGNDONE of the master lane reasserts. Phase 
+              --and delay alignment for the multilane interface is complete. 
+              tx_phalign_manual_state   <= PHALIGN_DONE;
+            end if;
+            
+          when PHALIGN_DONE => 
+            --Continue to hold TXDLYEN for the master lane High to adjust 
+            --TXUSRCLK to compensate for temperature and voltage variations.
+            TXDLYEN(MASTER_LANE_ID) <= '1';
+            PHASE_ALIGNMENT_DONE    <= '1';
+
+          when OTHERS =>
+            tx_phalign_manual_state   <= INIT;
+
+        end case;      
+      end if;
+    end if;
+  end process;
+
+
+end RTL;
+
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_startup_fsm.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_startup_fsm.vhd
new file mode 100644
index 0000000..7bd5f2d
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip/gtxkintex7fee80_tx_startup_fsm.vhd
@@ -0,0 +1,562 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 2.6
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename :gtxkintex7fee80_tx_startup_fsm.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module gtxKintex7FEE80_tx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxKintex7FEE80_TX_STARTUP_FSM is
+  Generic( GT_TYPE                  : string  := "GTX";
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient              
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           TXUSERCLK                : in  STD_LOGIC;              --TXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;              --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;              --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;              --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the CPLL of the GT
+           TXRESETDONE              : in  STD_LOGIC;      
+           MMCM_LOCK                : in  STD_LOGIC;      
+           GTTXRESET                : out STD_LOGIC:='0';      
+           MMCM_RESET               : out STD_LOGIC:='1';      
+           QPLL_RESET               : out STD_LOGIC:='0';        --Reset QPLL
+           CPLL_RESET               : out STD_LOGIC:='0';        --Reset CPLL
+           TX_FSM_RESET_DONE        : out STD_LOGIC;             --Reset-sequence has sucessfully been finished.
+           TXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC:='0';
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';
+           PHALIGNMENT_DONE         : in  STD_LOGIC;
+           
+           RETRY_COUNTER            : out  STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end gtxKintex7FEE80_TX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+--   are calculated at design-time based on the Generics
+--   
+-- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX
+--   => signal which PLL has been reset
+-- * 
+
+
+
+architecture RTL of gtxKintex7FEE80_TX_STARTUP_FSM is
+
+  component gtxKintex7FEE80_sync_block
+   generic (
+     INITIALISE : bit_vector(1 downto 0) := "00"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+  type tx_rst_fsm_type is(
+    INIT, ASSERT_ALL_RESETS, RELEASE_PLL_RESET,
+    RELEASE_MMCM_RESET, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+    RESET_FSM_DONE);
+    
+  signal tx_state : tx_rst_fsm_type := INIT;
+
+  constant MMCM_LOCK_CNT_MAX    : integer := 1024;
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+    
+  constant WAIT_TIMEOUT_2ms     : integer := 2000000 / STABLE_CLOCK_PERIOD;--  2 ms time-out
+  constant WAIT_TLOCK_MAX       : integer :=  100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_TIMEOUT_500us   : integer :=  500000 / STABLE_CLOCK_PERIOD;--100 us time-out
+    
+  signal init_wait_count        : integer range 0 to WAIT_MAX:=0;
+  signal init_wait_done         : std_logic := '0';
+  signal pll_reset_asserted     : std_logic := '0';
+
+  signal tx_fsm_reset_done_int     : std_logic := '0';
+  signal tx_fsm_reset_done_int_s2  : std_logic := '0';
+  signal tx_fsm_reset_done_int_s3  : std_logic := '0';
+   
+  signal txresetdone_s2         : std_logic := '0'; 
+  signal txresetdone_s3         : std_logic := '0'; 
+
+  constant MAX_RETRIES          : integer := 2**RETRY_COUNTER_BITWIDTH-1; 
+  signal retry_counter_int      : integer range 0 to MAX_RETRIES;  
+  signal time_out_counter       : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+    
+  signal reset_time_out         : std_logic := '0';
+  signal time_out_2ms           : std_logic := '0';--\Flags that the various time-out points 
+  signal time_tlock_max         : std_logic := '0';--|have been reached.
+  signal time_out_500us         : std_logic := '0';--/
+    
+  signal mmcm_lock_count        : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+  signal mmcm_lock_int          : std_logic := '0';
+  signal mmcm_lock_reclocked    : std_logic := '0';
+    
+  signal run_phase_alignment_int    : std_logic := '0';
+  signal run_phase_alignment_int_s2 : std_logic := '0';
+  signal run_phase_alignment_int_s3 : std_logic := '0';
+
+  constant MAX_WAIT_BYPASS      : integer := 110000; --110000 TXUSRCLK cycles is the max time for Multi lane designs
+  signal wait_bypass_count      : integer range 0 to MAX_WAIT_BYPASS-1;
+  signal time_out_wait_bypass   : std_logic := '0';
+  signal time_out_wait_bypass_s2   : std_logic := '0';
+  signal time_out_wait_bypass_s3   : std_logic := '0';
+  signal refclk_lost            : std_logic;
+
+   signal      cplllock_sync: std_logic := '0';
+  signal      qplllock_sync: std_logic := '0';
+  signal      cplllock_prev: std_logic := '0';
+  signal      qplllock_prev: std_logic := '0';
+  signal      cplllock_ris_edge: std_logic := '0';
+  signal      qplllock_ris_edge: std_logic := '0';
+ 
+begin
+  --Alias section, signals used within this module mapped to output ports:
+  RETRY_COUNTER     <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+  RUN_PHALIGNMENT   <= run_phase_alignment_int;
+  TX_FSM_RESET_DONE <= tx_fsm_reset_done_int;    
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+
+  timeouts:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- One common large counter for generating three time-out signals.
+      -- Intermediate time-outs are derived from calculated values, based
+      -- on the period of the provided clock.
+      if reset_time_out = '1' then
+        time_out_counter  <= 0;
+        time_out_2ms      <= '0';
+        time_tlock_max    <= '0';
+        time_out_500us    <= '0';
+      else
+        if time_out_counter = WAIT_TIMEOUT_2ms then
+          time_out_2ms <= '1';
+        else
+          time_out_counter <= time_out_counter + 1;
+        end if;
+        
+        if time_out_counter = WAIT_TLOCK_MAX then
+          time_tlock_max <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_500us then
+          time_out_500us <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  mmcm_lock_wait:process(TXUSERCLK)
+  begin
+    if rising_edge(TXUSERCLK) then
+      if MMCM_LOCK = '0' then
+        mmcm_lock_count <= 0;
+        mmcm_lock_int   <= '0';
+      else 
+        if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+          mmcm_lock_count <= mmcm_lock_count + 1;
+        else
+          mmcm_lock_int <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+
+  -- Clock Domain Crossing
+
+  sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  TXUSERCLK,
+            data_in         =>  run_phase_alignment_int,
+            data_out        =>  run_phase_alignment_int_s2 
+         );
+
+  sync_tx_fsm_reset_done_int : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  TXUSERCLK,
+            data_in         =>  tx_fsm_reset_done_int,
+            data_out        =>  tx_fsm_reset_done_int_s2 
+         );
+
+  process(TXUSERCLK)
+  begin
+    if rising_edge(TXUSERCLK) then
+      run_phase_alignment_int_s3   <=  run_phase_alignment_int_s2;
+
+      tx_fsm_reset_done_int_s3     <=  tx_fsm_reset_done_int_s2;
+    end if;
+  end process;
+
+ sync_TXRESETDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  TXRESETDONE,
+            data_out        =>  txresetdone_s2 
+         );
+
+  sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  time_out_wait_bypass,
+            data_out        =>  time_out_wait_bypass_s2 
+         );
+
+  sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  mmcm_lock_int,
+            data_out        =>  mmcm_lock_reclocked 
+         );
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+       txresetdone_s3     <= txresetdone_s2;
+
+       time_out_wait_bypass_s3 <=  time_out_wait_bypass_s2;
+       cplllock_prev           <=  cplllock_sync;
+       qplllock_prev           <=  qplllock_sync;
+    end if;
+  end process;
+
+ sync_CPLLLOCK : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  CPLLLOCK,
+            data_out        =>  cplllock_sync
+         );
+
+ sync_QPLLLOCK : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  QPLLLOCK,
+            data_out        =>  qplllock_sync
+         );
+
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       cplllock_ris_edge <= '0';
+     elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+       cplllock_ris_edge <= '1';
+     elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+       cplllock_ris_edge <= cplllock_ris_edge;
+     else 
+       cplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       qplllock_ris_edge <= '0';
+     elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+       qplllock_ris_edge <= '1';
+     elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+       qplllock_ris_edge <= qplllock_ris_edge;
+     else 
+       qplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+
+  timeout_buffer_bypass:process(TXUSERCLK)
+  begin
+    if rising_edge(TXUSERCLK) then
+      if run_phase_alignment_int_s3 = '0' then
+        wait_bypass_count     <= 0;
+        time_out_wait_bypass  <= '0';
+      elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0')  then
+        if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+          time_out_wait_bypass <= '1';
+        else
+          wait_bypass_count <= wait_bypass_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+    refclk_lost <= '1' when ((TX_QPLL_USED and QPLLREFCLKLOST='1') or (not TX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+  --FSM for resetting the GTX/GTH/GTP in the 7-series. 
+  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  --
+  -- Following steps are performed:
+  -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in 
+  --    answer-record 43482
+  -- 2) Assert all resets on the GT and on an MMCM potentially connected. 
+  --    After that wait until a reference-clock has been detected.
+  -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+  -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+  --    Also signal to the RX-side which PLL has been reset.
+  -- 5) Wait for the RESET_DONE-signal from the GT.
+  -- 6) Signal to start the phase-alignment procedure and wait for it to 
+  --    finish.
+  -- 7) Reset-sequence has successfully run through. Signal this to the 
+  --    rest of the design by asserting TX_FSM_RESET_DONE.
+  
+  reset_fsm:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+        tx_state                <= INIT;
+        TXUSERRDY               <= '0';
+        GTTXRESET               <= '0';
+        MMCM_RESET              <= '1';
+        tx_fsm_reset_done_int   <= '0';
+        QPLL_RESET              <= '0';
+        CPLL_RESET              <= '0';
+        pll_reset_asserted      <= '0';
+        reset_time_out          <= '0';
+        retry_counter_int       <=  0;
+        run_phase_alignment_int <= '0';
+        RESET_PHALIGNMENT       <= '1';
+      else
+        
+        case tx_state is
+          when INIT => 
+            --Initial state after configuration. This state will be left after
+            --approx. 500 ns and not be re-entered. 
+            if init_wait_done = '1' then
+              tx_state        <= ASSERT_ALL_RESETS;
+              reset_time_out  <= '1';
+            end if;
+            
+          when ASSERT_ALL_RESETS => 
+            --This is the state into which the FSM will always jump back if any
+            --time-outs will occur. 
+            --The number of retries is reported on the output RETRY_COUNTER. In 
+            --case the transceiver never comes up for some reason, this machine 
+            --will still continue its best and rerun until the FPGA is turned off
+            --or the transceivers come up correctly.
+            if TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                QPLL_RESET          <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                QPLL_RESET          <= '0';
+              end if;
+            else
+              if pll_reset_asserted = '0' then
+                CPLL_RESET <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                CPLL_RESET          <= '0';
+              end if;  
+            end if;
+            TXUSERRDY               <= '0';
+            GTTXRESET               <= '1';
+            MMCM_RESET              <= '1';
+            reset_time_out          <= '0';
+            run_phase_alignment_int <= '0';     
+            RESET_PHALIGNMENT       <= '1';
+
+            if (TX_QPLL_USED and (QPLLREFCLKLOST = '0') and pll_reset_asserted = '1') or
+               (not TX_QPLL_USED and (CPLLREFCLKLOST = '0') and pll_reset_asserted = '1') then
+              tx_state  <= RELEASE_PLL_RESET;
+           end if;           
+            
+          when RELEASE_PLL_RESET => 
+            --PLL-Reset of the GTX gets released and the time-out counter
+            --starts running.
+            pll_reset_asserted  <= '0';
+
+             if (TX_QPLL_USED and (qplllock_ris_edge = '1')) or
+               (not TX_QPLL_USED and (cplllock_ris_edge = '1')) then
+              tx_state  <= RELEASE_MMCM_RESET;
+              reset_time_out  <= '1';
+            end if;
+            
+            if time_out_2ms = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+
+          when RELEASE_MMCM_RESET => 
+            GTTXRESET <= '0';
+            reset_time_out  <= '0';
+            --Release of the MMCM-reset. Waiting for the MMCM to lock.
+            MMCM_RESET <= '0';
+            if mmcm_lock_reclocked = '1' then
+              tx_state <= WAIT_RESET_DONE;
+              reset_time_out  <= '1';
+            end if;          
+            
+            if time_tlock_max = '1' and mmcm_lock_reclocked = '0' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+            
+          when WAIT_RESET_DONE => 
+            TXUSERRDY <= '1';
+            reset_time_out  <= '0';
+            if txresetdone_s3 = '1' then              
+              tx_state      <= DO_PHASE_ALIGNMENT;               
+              reset_time_out  <= '1';
+            end if;          
+
+            if time_out_500us = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;                    
+          
+          when DO_PHASE_ALIGNMENT => 
+            --The direct handling of the signals for the Phase Alignment is done outside
+            --this state-machine. 
+            RESET_PHALIGNMENT       <= '0';
+            run_phase_alignment_int <= '1';
+            reset_time_out          <= '0';
+            
+            if PHALIGNMENT_DONE = '1' then
+              tx_state        <= RESET_FSM_DONE;
+            end if;
+            
+            if time_out_wait_bypass_s3 = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <=  retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+          
+          when RESET_FSM_DONE => 
+            reset_time_out        <= '1';
+            tx_fsm_reset_done_int <= '1';
+
+          when OTHERS =>
+            tx_state              <= INIT;
+          
+        end case;
+      end if;
+    end if;
+  end process; 
+
+end RTL;
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80.vhd
new file mode 100644
index 0000000..ce90e86
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80.vhd
@@ -0,0 +1,403 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtxkintex7fee80.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80 (a Core Top)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity gtxKintex7FEE80 is
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end gtxKintex7FEE80;
+
+architecture RTL of gtxKintex7FEE80 is
+    attribute DowngradeIPIdentifiedWarnings: string;
+    attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+    attribute X_CORE_INFO : string;
+    attribute X_CORE_INFO of RTL : architecture is "gtxKintex7FEE80,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+--**************************Component Declarations*****************************
+
+component gtxKintex7FEE80_init 
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    EXAMPLE_SIMULATION                      : integer   := 0;          -- Set to 1 for simulation
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+ 
+    STABLE_CLOCK_PERIOD                     : integer   := 12;  
+        -- Set to 1 for simulation
+    EXAMPLE_USE_CHIPSCOPE                   : integer   := 1       --// Modified       -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end component;
+ 
+--**************************** Main Body of Code *******************************
+begin
+    U0 : gtxKintex7FEE80_init
+    generic map
+(
+        EXAMPLE_SIM_GTRESET_SPEEDUP   => "TRUE",
+        EXAMPLE_SIMULATION            => 0,
+ 
+        USE_BUFG           => 0,
+ 
+        STABLE_CLOCK_PERIOD           => 12,
+        EXAMPLE_USE_CHIPSCOPE         => 1 --// Modified
+)
+port map
+(
+        SYSCLK_IN                       =>      SYSCLK_IN,
+        SOFT_RESET_TX_IN                =>      SOFT_RESET_TX_IN,
+        SOFT_RESET_RX_IN                =>      SOFT_RESET_RX_IN,
+        DONT_RESET_ON_DATA_ERROR_IN     =>      DONT_RESET_ON_DATA_ERROR_IN,
+    GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
+    GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT,
+    GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
+    GT0_TX_MMCM_LOCK_IN => GT0_TX_MMCM_LOCK_IN,
+    GT0_TX_MMCM_RESET_OUT => GT0_TX_MMCM_RESET_OUT,
+
+    --_________________________________________________________________________
+    --GT0  (X1Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      gt0_cplllockdetclk_in,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+    -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      gt0_gtrefclk0_in,
+        gt0_gtrefclk1_in                =>      gt0_gtrefclk1_in,
+    ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      gt0_drpclk_in,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+    --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+    --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+    -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+	------------------------- Receive Ports - CDR Ports ------------------------
+		GT0_RXCDRRESET_IN               => GT0_RXCDRRESET_IN, --// Modified
+		GT0_RXCDRLOCK_OUT               => GT0_RXCDRLOCK_OUT, --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_in,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_in,
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+    --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_out,
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+    --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_in,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_in,
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_out,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  => GT0_QPLLOUTCLK_IN,
+     GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN 
+
+);
+ 
+end RTL;    
+ 
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_auto_phase_align.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_auto_phase_align.vhd
new file mode 100644
index 0000000..e3a0db5
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_auto_phase_align.vhd
@@ -0,0 +1,198 @@
+--//////////////////////////////////////////////////////////////////////////////
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtxkintex7fee80_auto_phase_align.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description : The logic below implements the procedure to do automatic phase-alignment 
+--                on the 7-series GTX as described in ug476pdf, version 1.3,
+--                Chapters "Using the TX Phase Alignment to Bypass the TX Buffer"
+--                and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer"
+--                Should the logic below differ from what is described in a later version  
+--                of the user-guide, you are using an auto-alignment block, which is 
+--                out of date and needs to be updated for safe operation.
+--                     
+--
+--
+-- Module gtxKintex7FEE80_AUTO_PHASE_ALIGN
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxKintex7FEE80_AUTO_PHASE_ALIGN is     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RUN_PHALIGNMENT          : in  STD_LOGIC;              --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Auto phase-alignment performed sucessfully
+           PHALIGNDONE              : in  STD_LOGIC;              --\ Phase-alignment signals from and to the
+           DLYSRESET                : out STD_LOGIC;              -- |transceiver.
+           DLYSRESETDONE            : in  STD_LOGIC;              --/
+           RECCLKSTABLE             : in  STD_LOGIC               --/on the RX-side.
+           
+           );
+end gtxKintex7FEE80_AUTO_PHASE_ALIGN;
+
+architecture RTL of gtxKintex7FEE80_AUTO_PHASE_ALIGN is
+
+  component gtxKintex7FEE80_sync_block
+   generic (
+     INITIALISE : bit_vector(5 downto 0) := "000000"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+  type phase_align_auto_fsm is(
+    INIT, WAIT_PHRST_DONE, COUNT_PHALIGN_DONE, PHALIGN_DONE
+    );
+    
+  signal phalign_state       : phase_align_auto_fsm := INIT;
+  signal phaligndone_prev     : std_logic := '0';
+  signal phaligndone_ris_edge : std_logic;
+
+  signal count_phalign_edges   : integer range 0 to 3:= 0;
+  signal phaligndone_sync      : std_logic := '0';
+  signal dlysresetdone_sync    : std_logic := '0';
+
+begin
+
+ sync_PHALIGNDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  PHALIGNDONE,
+            data_out        =>  phaligndone_sync 
+         );
+
+  sync_DLYSRESETDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  DLYSRESETDONE,
+            data_out        =>  dlysresetdone_sync 
+         );
+
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      phaligndone_prev <= phaligndone_sync; 
+    end if;
+  end process;
+  phaligndone_ris_edge <= '1' when (phaligndone_prev = '0') and (phaligndone_sync = '1') else '0';
+  
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if RUN_PHALIGNMENT = '0' or RECCLKSTABLE = '0' then
+        DLYSRESET           <= '0';
+        count_phalign_edges   <= 0;
+        PHASE_ALIGNMENT_DONE  <= '0';
+        phalign_state      <= INIT;
+      else
+        if phaligndone_ris_edge = '1' then
+          if count_phalign_edges < 3 then
+            count_phalign_edges <= count_phalign_edges + 1;
+          end if;
+        end if;
+        
+        DLYSRESET         <= '0';
+                  
+        case phalign_state is
+          when INIT => 
+            PHASE_ALIGNMENT_DONE <= '0';
+            if RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1' then
+              --DLYSRESET is toggled to '1'
+              DLYSRESET  <= '1';
+              phalign_state <= WAIT_PHRST_DONE;
+            end if;           
+            
+          when WAIT_PHRST_DONE =>
+            if dlysresetdone_sync = '1' then
+              phalign_state <= COUNT_PHALIGN_DONE;
+            end if;
+            --No timeout-check here as that is done in the main FSM
+            
+          when COUNT_PHALIGN_DONE =>
+            if (count_phalign_edges = 2) then
+
+              --For GTX: Only on the second edge of the PHALIGNDONE-signal the 
+              --         phase-alignment is completed
+              --For GTH, GTP: TXSYNCDONE indicates the completion of Phase Alignment
+
+              phalign_state <= PHALIGN_DONE;
+            end if;
+          
+          when PHALIGN_DONE =>
+            PHASE_ALIGNMENT_DONE <= '1';
+
+          when OTHERS =>
+            phalign_state      <= INIT;
+
+        end case;        
+      end if;      
+    end if;    
+  end process;
+
+end RTL;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_cpll_railing.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_cpll_railing.vhd
new file mode 100644
index 0000000..8664c5d
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_cpll_railing.vhd
@@ -0,0 +1,144 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtxkintex7fee80_cpll_railing.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module gtxKintex7FEE80_cpll_railing
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity gtxKintex7FEE80_cpll_railing is
+generic( USE_BUFG       : integer := 0
+       );
+   port  (
+         cpll_reset_out : out std_logic;
+         cpll_pd_out : out std_logic;
+         refclk_out : out std_logic;
+        
+         refclk_in : in std_logic
+          );
+   end gtxKintex7FEE80_cpll_railing;
+
+
+architecture RTL of gtxKintex7FEE80_cpll_railing is
+
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+attribute equivalent_register_removal: string; 
+signal cpllpd_wait    :   std_logic_vector(95 downto 0)  := x"FFFFFFFFFFFFFFFFFFFFFFFF";
+signal cpllreset_wait :   std_logic_vector(127 downto 0) := x"000000000000000000000000000000FF";
+attribute equivalent_register_removal of cpllpd_wait : signal is "no";
+attribute equivalent_register_removal of cpllreset_wait : signal is "no";
+signal    gtrefclk0_i      :std_logic ;
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+  use_bufg_cpll:if(USE_BUFG = 1) generate
+  refclk_buf : BUFG
+  port map
+   (O   => gtrefclk0_i,
+    I   => refclk_in);
+
+  end generate;
+
+  use_bufr_cpll:if(USE_BUFG = 0) generate
+  refclk_buf : BUFR
+  port map
+   (O   => gtrefclk0_i,
+    CE  => tied_to_vcc_i,
+    CLR => tied_to_ground_i,
+    I   => refclk_in);
+
+  end generate;
+
+    process( gtrefclk0_i )
+    begin
+        if(gtrefclk0_i'event and gtrefclk0_i = '1') then 
+           cpllpd_wait <= cpllpd_wait(94 downto 0) & '0';
+           cpllreset_wait <= cpllreset_wait(126 downto 0) & '0';
+         end if;
+    end process;
+
+cpll_pd_out <= cpllpd_wait(95);
+cpll_reset_out <= cpllreset_wait(127);
+refclk_out <= gtrefclk0_i;
+
+
+ end RTL;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_gt.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_gt.vhd
new file mode 100644
index 0000000..8e82fbc
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_gt.vhd
@@ -0,0 +1,834 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtxkintex7fee80_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity gtxKintex7FEE80_GT is
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP    : string     :=  "FALSE";        -- Set to "TRUE" to speed up sim reset
+    RX_DFE_KL_CFG2_IN         : bit_vector :=   X"301148AC";
+    SIM_CPLLREFCLK_SEL        : bit_vector :=   "001";
+    PMA_RSV_IN                : bit_vector :=  x"00018480";
+    PCS_RSVD_ATTR_IN          : bit_vector :=   X"000000000000"
+);
+port 
+(
+     cpllpd_in : in std_logic;
+     cpllrefclksel_in : in std_logic_vector(2 downto 0);
+    --------------------------------- CPLL Ports -------------------------------
+    cpllfbclklost_out                       : out  std_logic;
+    cplllock_out                            : out  std_logic;
+    cplllockdetclk_in                       : in   std_logic;
+    cpllrefclklost_out                      : out  std_logic;
+    cpllreset_in                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gtrefclk0_in                            : in   std_logic;
+    gtrefclk1_in                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    drpaddr_in                              : in   std_logic_vector(8 downto 0);
+    drpclk_in                               : in   std_logic;
+    drpdi_in                                : in   std_logic_vector(15 downto 0);
+    drpdo_out                               : out  std_logic_vector(15 downto 0);
+    drpen_in                                : in   std_logic;
+    drprdy_out                              : out  std_logic;
+    drpwe_in                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    qpllclk_in                              : in   std_logic;
+    qpllrefclk_in                           : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    dmonitorout_out                         : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    eyescanreset_in                         : in   std_logic;
+    rxuserrdy_in                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    eyescandataerror_out                    : out  std_logic;
+    eyescantrigger_in                       : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	RXCDRRESET_IN                           : in  std_logic; --// Modified
+    RXCDRLOCK_OUT                           : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    rxusrclk_in                             : in   std_logic;
+    rxusrclk2_in                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    rxdata_out                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    rxdisperr_out                           : out  std_logic_vector(1 downto 0);
+    rxnotintable_out                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gtxrxp_in                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gtxrxn_in                               : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    rxdlyen_in                              : in   std_logic;
+    rxdlysreset_in                          : in   std_logic;
+    rxdlysresetdone_out                     : out  std_logic;
+    rxphalign_in                            : in   std_logic;
+    rxphaligndone_out                       : out  std_logic;
+    rxphalignen_in                          : in   std_logic;
+    rxphdlyreset_in                         : in   std_logic;
+    rxphmonitor_out                         : out  std_logic_vector(4 downto 0);
+    rxphslipmonitor_out                     : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    rxlpmhfhold_in                          : in   std_logic;
+    rxlpmlfhold_in                          : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    rxdfelpmreset_in                        : in   std_logic;
+    rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
+    rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    rxoutclk_out                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gtrxreset_in                            : in   std_logic;
+    rxpmareset_in                           : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    rxcharisk_out                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    rxresetdone_out                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gttxreset_in                            : in   std_logic;
+    txuserrdy_in                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    txusrclk_in                             : in   std_logic;
+    txusrclk2_in                            : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    txdlyen_in                              : in   std_logic;
+    txdlysreset_in                          : in   std_logic;
+    txdlysresetdone_out                     : out  std_logic;
+    txphalign_in                            : in   std_logic;
+    txphaligndone_out                       : out  std_logic;
+    txphalignen_in                          : in   std_logic;
+    txphdlyreset_in                         : in   std_logic;
+    txphinit_in                             : in   std_logic;
+    txphinitdone_out                        : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    txdata_in                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gtxtxn_out                              : out  std_logic;
+    gtxtxp_out                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    txoutclk_out                            : out  std_logic;
+    txoutclkfabric_out                      : out  std_logic;
+    txoutclkpcs_out                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    txcharisk_in                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    txresetdone_out                         : out  std_logic
+
+
+);
+
+
+end gtxKintex7FEE80_GT;
+
+architecture RTL of gtxKintex7FEE80_GT is
+   
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+
+
+    -- RX Datapath signals
+    signal rxdata_i                         :   std_logic_vector(63 downto 0);      
+    signal rxchariscomma_float_i            :   std_logic_vector(5 downto 0);
+    signal rxcharisk_float_i                :   std_logic_vector(5 downto 0);
+    signal rxdisperr_float_i                :   std_logic_vector(5 downto 0);
+    signal rxnotintable_float_i             :   std_logic_vector(5 downto 0);
+    signal rxrundisp_float_i                :   std_logic_vector(5 downto 0);
+
+
+    -- TX Datapath signals
+    signal txdata_i                         :   std_logic_vector(63 downto 0);
+    signal txkerr_float_i                   :   std_logic_vector(5 downto 0);
+    signal txrundisp_float_i                :   std_logic_vector(5 downto 0);
+    signal rxstartofseq_float_i             :   std_logic;
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+    -------------------  GT Datapath byte mapping  -----------------
+    RXDATA_OUT    <=   rxdata_i(15 downto 0);
+
+    txdata_i    <=   (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
+
+
+
+    ----------------------------- GTXE2 Instance  --------------------------   
+
+    gtxe2_i :GTXE2_CHANNEL
+    generic map
+    (
+
+        --_______________________ Simulation-Only Attributes ___________________
+
+        SIM_RECEIVER_DETECT_PASS   =>      ("TRUE"),
+        SIM_RESET_SPEEDUP          =>      (GT_SIM_GTRESET_SPEEDUP),
+        SIM_TX_EIDLE_DRIVE_LEVEL   =>      ("X"),
+        SIM_CPLLREFCLK_SEL         =>      (SIM_CPLLREFCLK_SEL),
+        SIM_VERSION                =>      ("4.0"), 
+        
+
+       ------------------RX Byte and Word Alignment Attributes---------------
+        ALIGN_COMMA_DOUBLE                      =>     ("FALSE"),
+        ALIGN_COMMA_ENABLE                      =>     ("1111111111"),
+        ALIGN_COMMA_WORD                        =>     (1),
+        ALIGN_MCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_MCOMMA_VALUE                      =>     ("1010000011"),
+        ALIGN_PCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_PCOMMA_VALUE                      =>     ("0101111100"),
+        SHOW_REALIGN_COMMA                      =>     ("FALSE"),
+        RXSLIDE_AUTO_WAIT                       =>     (7),
+        RXSLIDE_MODE                            =>     ("AUTO"), --// ("PCS"), Modified
+        RX_SIG_VALID_DLY                        =>     (10),
+
+       ------------------RX 8B/10B Decoder Attributes---------------
+        RX_DISPERR_SEQ_MATCH                    =>     ("TRUE"),
+        DEC_MCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_PCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_VALID_COMMA_ONLY                    =>     ("FALSE"),
+
+       ------------------------RX Clock Correction Attributes----------------------
+        CBCC_DATA_SOURCE_SEL                    =>     ("DECODED"),
+        CLK_COR_SEQ_2_USE                       =>     ("FALSE"),
+        CLK_COR_KEEP_IDLE                       =>     ("FALSE"),
+        CLK_COR_MAX_LAT                         =>     (9),
+        CLK_COR_MIN_LAT                         =>     (7),
+        CLK_COR_PRECEDENCE                      =>     ("TRUE"),
+        CLK_COR_REPEAT_WAIT                     =>     (0),
+        CLK_COR_SEQ_LEN                         =>     (1),
+        CLK_COR_SEQ_1_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_1_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_1_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_4                         =>     ("0000000000"),
+        CLK_CORRECT_USE                         =>     ("FALSE"),
+        CLK_COR_SEQ_2_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_2_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_2_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_4                         =>     ("0000000000"),
+
+       ------------------------RX Channel Bonding Attributes----------------------
+        CHAN_BOND_KEEP_ALIGN                    =>     ("FALSE"),
+        CHAN_BOND_MAX_SKEW                      =>     (1),
+        CHAN_BOND_SEQ_LEN                       =>     (1),
+        CHAN_BOND_SEQ_1_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_USE                     =>     ("FALSE"),
+        FTS_DESKEW_SEQ_ENABLE                   =>     ("1111"),
+        FTS_LANE_DESKEW_CFG                     =>     ("1111"),
+        FTS_LANE_DESKEW_EN                      =>     ("FALSE"),
+
+       ---------------------------RX Margin Analysis Attributes----------------------------
+        ES_CONTROL                              =>     ("000000"),
+        ES_ERRDET_EN                            =>     ("FALSE"),
+        ES_EYE_SCAN_EN                          =>     ("TRUE"),
+        ES_HORZ_OFFSET                          =>     (x"000"),
+        ES_PMA_CFG                              =>     ("0000000000"),
+        ES_PRESCALE                             =>     ("00000"),
+        ES_QUALIFIER                            =>     (x"00000000000000000000"),
+        ES_QUAL_MASK                            =>     (x"00000000000000000000"),
+        ES_SDATA_MASK                           =>     (x"00000000000000000000"),
+        ES_VERT_OFFSET                          =>     ("000000000"),
+
+       -------------------------FPGA RX Interface Attributes-------------------------
+        RX_DATA_WIDTH                           =>     (20),
+
+       ---------------------------PMA Attributes----------------------------
+        OUTREFCLK_SEL_INV                       =>     ("11"),
+        PMA_RSV                                 =>     (PMA_RSV_IN),
+        PMA_RSV2                                =>     (x"2040"), --// was 2050
+        PMA_RSV3                                =>     ("00"),
+        PMA_RSV4                                =>     (x"00000000"),
+        RX_BIAS_CFG                             =>     ("000000000100"),
+        DMONITOR_CFG                            =>     (x"000A00"),
+        RX_CM_SEL                               =>     ("00"),
+        RX_CM_TRIM                              =>     ("000"), --// was 010
+        RX_DEBUG_CFG                            =>     ("000000000000"),
+        RX_OS_CFG                               =>     ("0000010000000"),
+        TERM_RCAL_CFG                           =>     ("10000"),
+        TERM_RCAL_OVRD                          =>     ('0'),
+        TST_RSV                                 =>     (x"00000000"),
+        RX_CLK25_DIV                            =>     (4),
+        TX_CLK25_DIV                            =>     (4),
+        UCODEER_CLR                             =>     ('0'),
+
+       ---------------------------PCI Express Attributes----------------------------
+        PCS_PCIE_EN                             =>     ("FALSE"),
+
+       ---------------------------PCS Attributes----------------------------
+        PCS_RSVD_ATTR                           =>     (PCS_RSVD_ATTR_IN),
+
+       -------------RX Buffer Attributes------------
+        RXBUF_ADDR_MODE                         =>     ("FAST"),
+        RXBUF_EIDLE_HI_CNT                      =>     ("1000"),
+        RXBUF_EIDLE_LO_CNT                      =>     ("0000"),
+        RXBUF_EN                                =>     ("FALSE"),
+        RX_BUFFER_CFG                           =>     ("000000"),
+        RXBUF_RESET_ON_CB_CHANGE                =>     ("TRUE"),
+        RXBUF_RESET_ON_COMMAALIGN               =>     ("FALSE"),
+        RXBUF_RESET_ON_EIDLE                    =>     ("FALSE"),
+        RXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        RXBUFRESET_TIME                         =>     ("00001"),
+        RXBUF_THRESH_OVFLW                      =>     (61),
+        RXBUF_THRESH_OVRD                       =>     ("FALSE"),
+        RXBUF_THRESH_UNDFLW                     =>     (4),
+        RXDLY_CFG                               =>     (x"001F"),
+        RXDLY_LCFG                              =>     (x"030"),
+        RXDLY_TAP_CFG                           =>     (x"0000"),
+        RXPH_CFG                                =>     (x"000000"),
+        RXPHDLY_CFG                             =>     (x"084020"),
+        RXPH_MONITOR_SEL                        =>     ("00000"),
+        RX_XCLK_SEL                             =>     ("RXUSR"),
+        RX_DDI_SEL                              =>     ("000000"),
+        RX_DEFER_RESET_BUF_EN                   =>     ("TRUE"),
+
+       -----------------------CDR Attributes-------------------------
+
+       --For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
+
+       --For Display Port, HBR2 -   set RXCDR_CFG=72'h038c008bff20200010
+
+       --For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
+
+       --For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
+
+       --For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
+
+       --For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
+
+       --For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
+
+       --For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
+        RXCDR_CFG                               =>     (x"03000023ff10200020"),
+        RXCDR_FR_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_HOLD_DURING_EIDLE                 =>     ('0'),
+        RXCDR_PH_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_LOCK_CFG                          =>     ("010101"),
+
+       -------------------RX Initialization and Reset Attributes-------------------
+        RXCDRFREQRESET_TIME                     =>     ("00001"),
+        RXCDRPHRESET_TIME                       =>     ("00001"),
+        RXISCANRESET_TIME                       =>     ("00001"),
+        RXPCSRESET_TIME                         =>     ("00001"),
+        RXPMARESET_TIME                         =>     ("00011"),
+
+       -------------------RX OOB Signaling Attributes-------------------
+        RXOOB_CFG                               =>     ("0000110"),
+
+       -------------------------RX Gearbox Attributes---------------------------
+        RXGEARBOX_EN                            =>     ("FALSE"),
+        GEARBOX_MODE                            =>     ("000"),
+
+       -------------------------PRBS Detection Attribute-----------------------
+        RXPRBS_ERR_LOOPBACK                     =>     ('0'),
+
+       -------------Power-Down Attributes----------
+        PD_TRANS_TIME_FROM_P2                   =>     (x"03c"),
+        PD_TRANS_TIME_NONE_P2                   =>     (x"3c"),
+        PD_TRANS_TIME_TO_P2                     =>     (x"64"),
+
+       -------------RX OOB Signaling Attributes----------
+        SAS_MAX_COM                             =>     (64),
+        SAS_MIN_COM                             =>     (36),
+        SATA_BURST_SEQ_LEN                      =>     ("0101"),
+        SATA_BURST_VAL                          =>     ("100"),
+        SATA_EIDLE_VAL                          =>     ("100"),
+        SATA_MAX_BURST                          =>     (8),
+        SATA_MAX_INIT                           =>     (21),
+        SATA_MAX_WAKE                           =>     (7),
+        SATA_MIN_BURST                          =>     (4),
+        SATA_MIN_INIT                           =>     (12),
+        SATA_MIN_WAKE                           =>     (4),
+
+       -------------RX Fabric Clock Output Control Attributes----------
+        TRANS_TIME_RATE                         =>     (x"0E"),
+
+       --------------TX Buffer Attributes----------------
+        TXBUF_EN                                =>     ("FALSE"),
+        TXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        TXDLY_CFG                               =>     (x"001F"),
+        TXDLY_LCFG                              =>     (x"030"),
+        TXDLY_TAP_CFG                           =>     (x"0000"),
+        TXPH_CFG                                =>     (x"0780"),
+        TXPHDLY_CFG                             =>     (x"084020"),
+        TXPH_MONITOR_SEL                        =>     ("00000"),
+        TX_XCLK_SEL                             =>     ("TXUSR"),
+
+       -------------------------FPGA TX Interface Attributes-------------------------
+        TX_DATA_WIDTH                           =>     (20),
+
+       -------------------------TX Configurable Driver Attributes-------------------------
+        TX_DEEMPH0                              =>     ("00000"),
+        TX_DEEMPH1                              =>     ("00000"),
+        TX_EIDLE_ASSERT_DELAY                   =>     ("110"),
+        TX_EIDLE_DEASSERT_DELAY                 =>     ("100"),
+        TX_LOOPBACK_DRIVE_HIZ                   =>     ("FALSE"),
+        TX_MAINCURSOR_SEL                       =>     ('0'),
+        TX_DRIVE_MODE                           =>     ("DIRECT"),
+        TX_MARGIN_FULL_0                        =>     ("1001110"),
+        TX_MARGIN_FULL_1                        =>     ("1001001"),
+        TX_MARGIN_FULL_2                        =>     ("1000101"),
+        TX_MARGIN_FULL_3                        =>     ("1000010"),
+        TX_MARGIN_FULL_4                        =>     ("1000000"),
+        TX_MARGIN_LOW_0                         =>     ("1000110"),
+        TX_MARGIN_LOW_1                         =>     ("1000100"),
+        TX_MARGIN_LOW_2                         =>     ("1000010"),
+        TX_MARGIN_LOW_3                         =>     ("1000000"),
+        TX_MARGIN_LOW_4                         =>     ("1000000"),
+
+       -------------------------TX Gearbox Attributes--------------------------
+        TXGEARBOX_EN                            =>     ("FALSE"),
+
+       -------------------------TX Initialization and Reset Attributes--------------------------
+        TXPCSRESET_TIME                         =>     ("00001"),
+        TXPMARESET_TIME                         =>     ("00001"),
+
+       -------------------------TX Receiver Detection Attributes--------------------------
+        TX_RXDETECT_CFG                         =>     (x"1832"),
+        TX_RXDETECT_REF                         =>     ("100"),
+
+       ----------------------------CPLL Attributes----------------------------
+        CPLL_CFG                                =>     (x"BC07DC"),
+        CPLL_FBDIV                              =>     (5),
+        CPLL_FBDIV_45                           =>     (5),
+        CPLL_INIT_CFG                           =>     (x"00001E"),
+        CPLL_LOCK_CFG                           =>     (x"01E8"),
+        CPLL_REFCLK_DIV                         =>     (1),
+        RXOUT_DIV                               =>     (2),
+        TXOUT_DIV                               =>     (2),
+        SATA_CPLL_CFG                           =>     ("VCO_3000MHZ"),
+
+       --------------RX Initialization and Reset Attributes-------------
+        RXDFELPMRESET_TIME                      =>     ("0001111"),
+
+       --------------RX Equalizer Attributes-------------
+        RXLPM_HF_CFG                            =>     ("00000011110000"),
+        RXLPM_LF_CFG                            =>     ("00000011110000"),
+        RX_DFE_GAIN_CFG                         =>     (x"020FEA"),
+        RX_DFE_H2_CFG                           =>     ("000000000000"),
+        RX_DFE_H3_CFG                           =>     ("000001000000"),
+        RX_DFE_H4_CFG                           =>     ("00011110000"),
+        RX_DFE_H5_CFG                           =>     ("00011100000"),
+        RX_DFE_KL_CFG                           =>     ("0000011111110"),
+        RX_DFE_LPM_CFG                          =>     (x"0904"),
+        RX_DFE_LPM_HOLD_DURING_EIDLE            =>     ('0'),
+        RX_DFE_UT_CFG                           =>     ("10001111000000000"),
+        RX_DFE_VP_CFG                           =>     ("00011111100000011"),
+
+       -------------------------Power-Down Attributes-------------------------
+        RX_CLKMUX_PD                            =>     ('1'),
+        TX_CLKMUX_PD                            =>     ('1'),
+
+       -------------------------FPGA RX Interface Attribute-------------------------
+        RX_INT_DATAWIDTH                        =>     (0),
+
+       -------------------------FPGA TX Interface Attribute-------------------------
+        TX_INT_DATAWIDTH                        =>     (0),
+
+       ------------------TX Configurable Driver Attributes---------------
+        TX_QPI_STATUS_EN                        =>     ('0'),
+
+       -------------------------RX Equalizer Attributes--------------------------
+        RX_DFE_KL_CFG2                          =>     (RX_DFE_KL_CFG2_IN),
+        RX_DFE_XYD_CFG                          =>     ("0000000000000"),
+
+       -------------------------TX Configurable Driver Attributes--------------------------
+        TX_PREDRIVER_MODE                       =>     ('0')
+
+
+    )
+    port map
+    (
+        --------------------------------- CPLL Ports -------------------------------
+        CPLLFBCLKLOST                   =>      cpllfbclklost_out,
+        CPLLLOCK                        =>      cplllock_out,
+        CPLLLOCKDETCLK                  =>      cplllockdetclk_in,
+        CPLLLOCKEN                      =>      tied_to_vcc_i,
+        CPLLPD                          =>      cpllpd_in,
+        CPLLREFCLKLOST                  =>      cpllrefclklost_out,
+        CPLLREFCLKSEL                   =>      cpllrefclksel_in,
+        CPLLRESET                       =>      cpllreset_in,
+        GTRSVD                          =>      "0000000000000000",
+        PCSRSVDIN                       =>      "0000000000000000",
+        PCSRSVDIN2                      =>      "00000",
+        PMARSVDIN                       =>      "00000",
+        PMARSVDIN2                      =>      "00000",
+        TSTIN                           =>      "11111111111111111111",
+        TSTOUT                          =>      open,
+        ---------------------------------- Channel ---------------------------------
+        CLKRSVD                         =>      tied_to_ground_vec_i(3 downto 0),
+        -------------------------- Channel - Clocking Ports ------------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      gtrefclk0_in,
+        GTREFCLK1                       =>      gtrefclk1_in,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR                         =>      drpaddr_in,
+        DRPCLK                          =>      drpclk_in,
+        DRPDI                           =>      drpdi_in,
+        DRPDO                           =>      drpdo_out,
+        DRPEN                           =>      drpen_in,
+        DRPRDY                          =>      drprdy_out,
+        DRPWE                           =>      drpwe_in,
+        ------------------------------- Clocking Ports -----------------------------
+        GTREFCLKMONITOR                 =>      open,
+        QPLLCLK                         =>      qpllclk_in,
+        QPLLREFCLK                      =>      qpllrefclk_in,
+        RXSYSCLKSEL                     =>      "00",
+        TXSYSCLKSEL                     =>      "00",
+        --------------------------- Digital Monitor Ports --------------------------
+        DMONITOROUT                     =>      dmonitorout_out,
+        ----------------- FPGA TX Interface Datapath Configuration  ----------------
+        TX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------------------- Loopback Ports -----------------------------
+        LOOPBACK                        =>      tied_to_ground_vec_i(2 downto 0),
+        ----------------------------- PCI Express Ports ----------------------------
+        PHYSTATUS                       =>      open,
+        RXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        RXVALID                         =>      open,
+        ------------------------------ Power-Down Ports ----------------------------
+        RXPD                            =>      "00",
+        TXPD                            =>      "00",
+        -------------------------- RX 8B/10B Decoder Ports -------------------------
+        SETERRSTATUS                    =>      tied_to_ground_i,
+        --------------------- RX Initialization and Reset Ports --------------------
+        EYESCANRESET                    =>      eyescanreset_in,
+        RXUSERRDY                       =>      rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR                =>      eyescandataerror_out,
+        EYESCANMODE                     =>      tied_to_ground_i,
+        EYESCANTRIGGER                  =>      eyescantrigger_in,
+        ------------------------- Receive Ports - CDR Ports ------------------------
+        RXCDRFREQRESET                  =>      tied_to_ground_i,
+        RXCDRHOLD                       =>      tied_to_ground_i,
+        RXCDRLOCK                       =>      RXCDRLOCK_OUT, --// Modified
+        RXCDROVRDEN                     =>      tied_to_ground_i,
+        RXCDRRESET                      =>      RXCDRRESET_IN, --// Modified tied_to_ground_i,
+        RXCDRRESETRSV                   =>      tied_to_ground_i,
+        ------------------- Receive Ports - Clock Correction Ports -----------------
+        RXCLKCORCNT                     =>      open,
+        ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+        RX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXUSRCLK                        =>      rxusrclk_in,
+        RXUSRCLK2                       =>      rxusrclk2_in,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        RXDATA                          =>      rxdata_i,
+        ------------------- Receive Ports - Pattern Checker Ports ------------------
+        RXPRBSERR                       =>      open,
+        RXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ------------------- Receive Ports - Pattern Checker ports ------------------
+        RXPRBSCNTRESET                  =>      tied_to_ground_i,
+        -------------------- Receive Ports - RX  Equalizer Ports -------------------
+        RXDFEXYDEN                      =>      tied_to_vcc_i,
+        RXDFEXYDHOLD                    =>      tied_to_ground_i,
+        RXDFEXYDOVRDEN                  =>      tied_to_ground_i,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXDISPERR(7 downto 2)           =>      rxdisperr_float_i,
+        RXDISPERR(1 downto 0)           =>      rxdisperr_out,
+        RXNOTINTABLE(7 downto 2)        =>      rxnotintable_float_i,
+        RXNOTINTABLE(1 downto 0)        =>      rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        GTXRXP                          =>      gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTXRXN                          =>      gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        RXBUFRESET                      =>      tied_to_ground_i,
+        RXBUFSTATUS                     =>      open,
+        RXDDIEN                         =>      tied_to_vcc_i,
+        RXDLYBYPASS                     =>      tied_to_ground_i,
+        RXDLYEN                         =>      rxdlyen_in,
+        RXDLYOVRDEN                     =>      tied_to_ground_i,
+        RXDLYSRESET                     =>      rxdlysreset_in,
+        RXDLYSRESETDONE                 =>      rxdlysresetdone_out,
+        RXPHALIGN                       =>      rxphalign_in,
+        RXPHALIGNDONE                   =>      rxphaligndone_out,
+        RXPHALIGNEN                     =>      rxphalignen_in,
+        RXPHDLYPD                       =>      tied_to_ground_i,
+        RXPHDLYRESET                    =>      rxphdlyreset_in,
+        RXPHMONITOR                     =>      rxphmonitor_out,
+        RXPHOVRDEN                      =>      tied_to_ground_i,
+        RXPHSLIPMONITOR                 =>      rxphslipmonitor_out,
+        RXSTATUS                        =>      open,
+        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+        RXBYTEISALIGNED                 =>      open,
+        RXBYTEREALIGN                   =>      open,
+        RXCOMMADET                      =>      open,
+        RXCOMMADETEN                    =>      tied_to_vcc_i,
+        RXMCOMMAALIGNEN                 =>      tied_to_vcc_i,
+        RXPCOMMAALIGNEN                 =>      tied_to_vcc_i,
+        ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+        RXCHANBONDSEQ                   =>      open,
+        RXCHBONDEN                      =>      tied_to_ground_i,
+        RXCHBONDLEVEL                   =>      tied_to_ground_vec_i(2 downto 0),
+        RXCHBONDMASTER                  =>      tied_to_ground_i,
+        RXCHBONDO                       =>      open,
+        RXCHBONDSLAVE                   =>      tied_to_ground_i,
+        ----------------- Receive Ports - RX Channel Bonding Ports  ----------------
+        RXCHANISALIGNED                 =>      open,
+        RXCHANREALIGN                   =>      open,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        RXLPMHFHOLD                     =>      rxlpmhfhold_in,
+        RXLPMHFOVRDEN                   =>      tied_to_ground_i,
+        RXLPMLFHOLD                     =>      rxlpmlfhold_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        RXDFEAGCHOLD                    =>      tied_to_ground_i,
+        RXDFEAGCOVRDEN                  =>      tied_to_ground_i,
+        RXDFECM1EN                      =>      tied_to_ground_i,
+        RXDFELFHOLD                     =>      tied_to_ground_i,
+        RXDFELFOVRDEN                   =>      tied_to_ground_i,
+        RXDFELPMRESET                   =>      rxdfelpmreset_in,
+        RXDFETAP2HOLD                   =>      tied_to_ground_i,
+        RXDFETAP2OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP3HOLD                   =>      tied_to_ground_i,
+        RXDFETAP3OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP4HOLD                   =>      tied_to_ground_i,
+        RXDFETAP4OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP5HOLD                   =>      tied_to_ground_i,
+        RXDFETAP5OVRDEN                 =>      tied_to_ground_i,
+        RXDFEUTHOLD                     =>      tied_to_ground_i,
+        RXDFEUTOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVPHOLD                     =>      tied_to_ground_i,
+        RXDFEVPOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVSEN                       =>      tied_to_ground_i,
+        RXLPMLFKLOVRDEN                 =>      tied_to_ground_i,
+        RXMONITOROUT                    =>      rxmonitorout_out,
+        RXMONITORSEL                    =>      rxmonitorsel_in,
+        RXOSHOLD                        =>      tied_to_ground_i,
+        RXOSOVRDEN                      =>      tied_to_ground_i,
+        ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+        RXRATEDONE                      =>      open,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK                        =>      rxoutclk_out,
+        RXOUTCLKFABRIC                  =>      open,
+        RXOUTCLKPCS                     =>      open,
+        RXOUTCLKSEL                     =>      "010",
+        ---------------------- Receive Ports - RX Gearbox Ports --------------------
+        RXDATAVALID                     =>      open,
+        RXHEADER                        =>      open,
+        RXHEADERVALID                   =>      open,
+        RXSTARTOFSEQ                    =>      open,
+        --------------------- Receive Ports - RX Gearbox Ports  --------------------
+        RXGEARBOXSLIP                   =>      tied_to_ground_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET                       =>      gtrxreset_in,
+        RXOOBRESET                      =>      tied_to_ground_i,
+        RXPCSRESET                      =>      tied_to_ground_i,
+        RXPMARESET                      =>      rxpmareset_in,
+        ------------------ Receive Ports - RX Margin Analysis ports ----------------
+        RXLPMEN                         =>      tied_to_vcc_i,
+        ------------------- Receive Ports - RX OOB Signaling ports -----------------
+        RXCOMSASDET                     =>      open,
+        RXCOMWAKEDET                    =>      open,
+        ------------------ Receive Ports - RX OOB Signaling ports  -----------------
+        RXCOMINITDET                    =>      open,
+        ------------------ Receive Ports - RX OOB signalling Ports -----------------
+        RXELECIDLE                      =>      open,
+        RXELECIDLEMODE                  =>      "11",
+        ----------------- Receive Ports - RX Polarity Control Ports ----------------
+        RXPOLARITY                      =>      tied_to_ground_i,
+        ---------------------- Receive Ports - RX gearbox ports --------------------
+        RXSLIDE                         =>      tied_to_ground_i,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        RXCHARISCOMMA                   =>      open,
+        RXCHARISK(7 downto 2)           =>      rxcharisk_float_i,
+        RXCHARISK(1 downto 0)           =>      rxcharisk_out,
+        ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
+        RXCHBONDI                       =>      "00000",
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE                     =>      rxresetdone_out,
+        -------------------------------- Rx AFE Ports ------------------------------
+        RXQPIEN                         =>      tied_to_ground_i,
+        RXQPISENN                       =>      open,
+        RXQPISENP                       =>      open,
+        --------------------------- TX Buffer Bypass Ports -------------------------
+        TXPHDLYTSTCLK                   =>      tied_to_ground_i,
+        ------------------------ TX Configurable Driver Ports ----------------------
+        TXPOSTCURSOR                    =>      "00000",
+        TXPOSTCURSORINV                 =>      tied_to_ground_i,
+        TXPRECURSOR                     =>      tied_to_ground_vec_i(4 downto 0),
+        TXPRECURSORINV                  =>      tied_to_ground_i,
+        TXQPIBIASEN                     =>      tied_to_ground_i,
+        TXQPISTRONGPDOWN                =>      tied_to_ground_i,
+        TXQPIWEAKPUP                    =>      tied_to_ground_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        CFGRESET                        =>      tied_to_ground_i,
+        GTTXRESET                       =>      gttxreset_in,
+        PCSRSVDOUT                      =>      open,
+        TXUSERRDY                       =>      txuserrdy_in,
+        ---------------------- Transceiver Reset Mode Operation --------------------
+        GTRESETSEL                      =>      tied_to_ground_i,
+        RESETOVRD                       =>      tied_to_ground_i,
+        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+        TXCHARDISPMODE                  =>      tied_to_ground_vec_i(7 downto 0),
+        TXCHARDISPVAL                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXUSRCLK                        =>      txusrclk_in,
+        TXUSRCLK2                       =>      txusrclk2_in,
+        --------------------- Transmit Ports - PCI Express Ports -------------------
+        TXELECIDLE                      =>      tied_to_ground_i,
+        TXMARGIN                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        TXSWING                         =>      tied_to_ground_i,
+        ------------------ Transmit Ports - Pattern Generator Ports ----------------
+        TXPRBSFORCEERR                  =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        TXDLYBYPASS                     =>      tied_to_ground_i,
+        TXDLYEN                         =>      txdlyen_in,
+        TXDLYHOLD                       =>      tied_to_ground_i,
+        TXDLYOVRDEN                     =>      tied_to_ground_i,
+        TXDLYSRESET                     =>      txdlysreset_in,
+        TXDLYSRESETDONE                 =>      txdlysresetdone_out,
+        TXDLYUPDOWN                     =>      tied_to_ground_i,
+        TXPHALIGN                       =>      txphalign_in,
+        TXPHALIGNDONE                   =>      txphaligndone_out,
+        TXPHALIGNEN                     =>      txphalignen_in,
+        TXPHDLYPD                       =>      tied_to_ground_i,
+        TXPHDLYRESET                    =>      txphdlyreset_in,
+        TXPHINIT                        =>      txphinit_in,
+        TXPHINITDONE                    =>      txphinitdone_out,
+        TXPHOVRDEN                      =>      tied_to_ground_i,
+        ---------------------- Transmit Ports - TX Buffer Ports --------------------
+        TXBUFSTATUS                     =>      open,
+        --------------- Transmit Ports - TX Configurable Driver Ports --------------
+        TXBUFDIFFCTRL                   =>      "100",
+        TXDEEMPH                        =>      tied_to_ground_i,
+        TXDIFFCTRL                      =>      "1000",
+        TXDIFFPD                        =>      tied_to_ground_i,
+        TXINHIBIT                       =>      tied_to_ground_i,
+        TXMAINCURSOR                    =>      "0000000",
+        TXPISOPD                        =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        TXDATA                          =>      txdata_i,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        GTXTXN                          =>      gtxtxn_out,
+        GTXTXP                          =>      gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK                        =>      txoutclk_out,
+        TXOUTCLKFABRIC                  =>      txoutclkfabric_out,
+        TXOUTCLKPCS                     =>      txoutclkpcs_out,
+        TXOUTCLKSEL                     =>      "011",
+        TXRATEDONE                      =>      open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        TXCHARISK(7 downto 2)           =>      tied_to_ground_vec_i(5 downto 0),
+        TXCHARISK(1 downto 0)           =>      txcharisk_in,
+        TXGEARBOXREADY                  =>      open,
+        TXHEADER                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXSEQUENCE                      =>      tied_to_ground_vec_i(6 downto 0),
+        TXSTARTSEQ                      =>      tied_to_ground_i,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXPCSRESET                      =>      tied_to_ground_i,
+        TXPMARESET                      =>      tied_to_ground_i,
+        TXRESETDONE                     =>      txresetdone_out,
+        ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+        TXCOMFINISH                     =>      open,
+        TXCOMINIT                       =>      tied_to_ground_i,
+        TXCOMSAS                        =>      tied_to_ground_i,
+        TXCOMWAKE                       =>      tied_to_ground_i,
+        TXPDELECIDLEMODE                =>      tied_to_ground_i,
+        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+        TXPOLARITY                      =>      tied_to_ground_i,
+        --------------- Transmit Ports - TX Receiver Detection Ports  --------------
+        TXDETECTRX                      =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
+        TX8B10BBYPASS                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+        TXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ----------------------- Tx Configurable Driver  Ports ----------------------
+        TXQPISENN                       =>      open,
+        TXQPISENP                       =>      open
+
+     );
+
+
+ end RTL;
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_init.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_init.vhd
new file mode 100644
index 0000000..bec1524
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_init.vhd
@@ -0,0 +1,885 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtxkintex7fee80_init.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module gtxKintex7FEE80_init
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity gtxKintex7FEE80_init is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    EXAMPLE_SIMULATION                      : integer   := 0;          -- Set to 1 for simulation
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+ 
+    STABLE_CLOCK_PERIOD                     : integer   := 12;  
+        -- Set to 1 for simulation
+    EXAMPLE_USE_CHIPSCOPE                   : integer   := 1       --// Modified    -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+    --_________________________________________________________________________
+    --GT0  (X1Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end gtxKintex7FEE80_init;
+    
+architecture RTL of gtxKintex7FEE80_init is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+
+component gtxKintex7FEE80_multi_gt 
+generic
+(
+    -- Simulation attributes
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+    WRAPPER_SIM_GTRESET_SPEEDUP    : string    := "FALSE" -- Set to "TRUE" to speed up sim reset
+
+);
+port
+(
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X1Y0)
+    --____________________________CHANNEL PORTS________________________________
+
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllrefclklost_out                  : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxdlyen_in                          : in   std_logic;
+    gt0_rxdlysreset_in                      : in   std_logic;
+    gt0_rxdlysresetdone_out                 : out  std_logic;
+    gt0_rxphalign_in                        : in   std_logic;
+    gt0_rxphaligndone_out                   : out  std_logic;
+    gt0_rxphalignen_in                      : in   std_logic;
+    gt0_rxphdlyreset_in                     : in   std_logic;
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    gt0_rxlpmhfhold_in                      : in   std_logic;
+    gt0_rxlpmlfhold_in                      : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    gt0_txdlyen_in                          : in   std_logic;
+    gt0_txdlysreset_in                      : in   std_logic;
+    gt0_txdlysresetdone_out                 : out  std_logic;
+    gt0_txphalign_in                        : in   std_logic;
+    gt0_txphaligndone_out                   : out  std_logic;
+    gt0_txphalignen_in                      : in   std_logic;
+    gt0_txphdlyreset_in                     : in   std_logic;
+    gt0_txphinit_in                         : in   std_logic;
+    gt0_txphinitdone_out                    : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+   
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN : in  std_logic;
+     GT0_QPLLOUTREFCLK_IN : in  std_logic 
+
+);
+end component;
+
+component gtxKintex7FEE80_TX_STARTUP_FSM
+  Generic(
+           EXAMPLE_SIMULATION       : integer := 0;
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient              
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           TXUSERCLK                : in  STD_LOGIC;              --TXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;              --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;              --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;              --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the CPLL of the GT
+           TXRESETDONE              : in  STD_LOGIC;      
+           MMCM_LOCK                : in  STD_LOGIC;      
+           GTTXRESET                : out STD_LOGIC:='0';      
+           MMCM_RESET               : out STD_LOGIC:='0';      
+           QPLL_RESET               : out STD_LOGIC:='0';        --Reset QPLL
+           CPLL_RESET               : out STD_LOGIC:='0';        --Reset CPLL
+           TX_FSM_RESET_DONE        : out STD_LOGIC:='0';        --Reset-sequence has sucessfully been finished.
+           TXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC:='0';
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';
+           PHALIGNMENT_DONE         : in  STD_LOGIC;
+           
+           RETRY_COUNTER            : out  STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end component;
+
+component gtxKintex7FEE80_RX_STARTUP_FSM
+  Generic(
+           EXAMPLE_SIMULATION       : integer := 0;
+           EQ_MODE                  : string := "DFE";
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient                         
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;        --Stable Clock, either a stable clock from the PCB
+                                                            --or reference-clock present at startup.
+           RXUSERCLK                : in  STD_LOGIC;        --RXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;        --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;        --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;        --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the CPLL of the GT
+           RXRESETDONE              : in  STD_LOGIC;
+           MMCM_LOCK                : in  STD_LOGIC;
+           RECCLK_STABLE            : in  STD_LOGIC;
+           RECCLK_MONITOR_RESTART   : in  STD_LOGIC;
+           DATA_VALID               : in  STD_LOGIC;
+           TXUSERRDY                : in  STD_LOGIC;       --TXUSERRDY from GT 
+           DONT_RESET_ON_DATA_ERROR : in  STD_LOGIC;
+           GTRXRESET                : out STD_LOGIC:='0';
+           MMCM_RESET               : out STD_LOGIC:='0';
+           QPLL_RESET               : out STD_LOGIC:='0';  --Reset QPLL (only if RX uses QPLL)
+           CPLL_RESET               : out STD_LOGIC:='0';  --Reset CPLL (only if RX uses CPLL)
+           RX_FSM_RESET_DONE        : out STD_LOGIC:='0';  --Reset-sequence has sucessfully been finished.
+           RXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC;
+           PHALIGNMENT_DONE         : in  STD_LOGIC; 
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';           
+           RXDFEAGCHOLD             : out STD_LOGIC;
+           RXDFELFHOLD              : out STD_LOGIC;
+           RXLPMLFHOLD              : out STD_LOGIC;
+           RXLPMHFHOLD              : out STD_LOGIC;
+           RETRY_COUNTER            : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end component;
+
+
+
+
+component gtxKintex7FEE80_AUTO_PHASE_ALIGN     
+    port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RUN_PHALIGNMENT          : in  STD_LOGIC;              --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC;              -- Auto phase-alignment performed sucessfully
+           PHALIGNDONE              : in  STD_LOGIC;              --\ Phase-alignment signals from and to the
+           DLYSRESET                : out STD_LOGIC;              -- |transceiver.
+           DLYSRESETDONE            : in  STD_LOGIC;              --/
+           RECCLKSTABLE             : in  STD_LOGIC               --/on the RX-side.
+           
+           );
+end component;
+
+
+component gtxKintex7FEE80_TX_MANUAL_PHASE_ALIGN 
+  Generic( NUMBER_OF_LANES          : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
+           MASTER_LANE_ID           : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RESET_PHALIGNMENT        : in  STD_LOGIC;
+           RUN_PHALIGNMENT          : in  STD_LOGIC;
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Manual phase-alignment performed sucessfully  
+           TXDLYSRESET              : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXDLYSRESETDONE          : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXPHINIT                 : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXPHINITDONE             : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXPHALIGN                : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXPHALIGNDONE            : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXDLYEN                  : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+           );
+end component;
+
+component gtxKintex7FEE80_RX_MANUAL_PHASE_ALIGN 
+  Generic( NUMBER_OF_LANES          : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
+           MASTER_LANE_ID           : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RESET_PHALIGNMENT        : in  STD_LOGIC;
+           RUN_PHALIGNMENT          : in  STD_LOGIC;
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Manual phase-alignment performed sucessfully    
+           RXDLYSRESET              : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           RXDLYSRESETDONE          : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           RXPHALIGN                : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           RXPHALIGNDONE            : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           RXDLYEN                  : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+           );
+end component;
+
+  function get_cdrlock_time(is_sim : in integer) return integer is
+    variable lock_time: integer;
+  begin
+    if (is_sim = 1) then
+      lock_time := 1000;
+    else
+      lock_time := 50000 / integer(2); --Typical CDR lock time is 50,000UI as per DS183
+    end if;
+    return lock_time;
+  end function;
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+    constant RX_CDRLOCK_TIME      : integer := get_cdrlock_time(EXAMPLE_SIMULATION);       -- 200us
+    constant WAIT_TIME_CDRLOCK    : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD;      -- 200 us time-out
+
+
+
+    -------------------------- GT Wrapper Wires ------------------------------
+    signal   gt0_txpmaresetdone_i            : std_logic;
+    signal   gt0_rxpmaresetdone_i            : std_logic;
+    signal   gt0_cpllreset_i                 : std_logic;
+    signal   gt0_cpllreset_t                 : std_logic;
+    signal   gt0_cpllrefclklost_i            : std_logic;
+    signal   gt0_cplllock_i                  : std_logic;
+    signal   gt0_txresetdone_i               : std_logic;
+    signal   gt0_rxresetdone_i               : std_logic;
+    signal   gt0_gttxreset_i                 : std_logic;
+    signal   gt0_gttxreset_t                 : std_logic;
+    signal   gt0_gtrxreset_i                 : std_logic;
+    signal   gt0_gtrxreset_t                 : std_logic;
+    signal   gt0_rxdfelpmreset_i             : std_logic;
+    signal   gt0_txuserrdy_i                 : std_logic;
+    signal   gt0_txuserrdy_t                 : std_logic;
+    signal   gt0_rxuserrdy_i                 : std_logic;
+    signal   gt0_rxuserrdy_t                 : std_logic;
+
+    signal   gt0_rxdfeagchold_i              : std_logic;
+    signal   gt0_rxdfelfhold_i               : std_logic;
+    signal   gt0_rxlpmlfhold_i               : std_logic;
+    signal   gt0_rxlpmhfhold_i               : std_logic;
+
+
+
+    signal   gt0_qpllreset_i                 : std_logic;
+    signal   gt0_qpllreset_t                 : std_logic;
+    signal   gt0_qpllrefclklost_i            : std_logic;
+    signal   gt0_qplllock_i                  : std_logic;
+
+
+    ------------------------------- Global Signals -----------------------------
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_vcc_i                   : std_logic;
+    signal   gt0_txphaligndone_i             : std_logic;
+    signal   gt0_txdlysreset_i               : std_logic;
+    signal   gt0_txdlysresetdone_i           : std_logic;
+    signal   gt0_txphdlyreset_i              : std_logic;
+    signal   gt0_txphalignen_i               : std_logic;
+    signal   gt0_txdlyen_i                   : std_logic;
+    signal   gt0_txphalign_i                 : std_logic;
+    signal   gt0_txphinit_i                  : std_logic;
+    signal   gt0_txphinitdone_i              : std_logic;
+    signal   gt0_run_tx_phalignment_i        : std_logic;
+    signal   gt0_rst_tx_phalignment_i        : std_logic;
+    signal   gt0_tx_phalignment_done_i       : std_logic;
+
+    signal   gt0_txoutclk_i                  : std_logic;
+    signal   gt0_rxoutclk_i                  : std_logic;
+    signal   gt0_rxoutclk_i2                 : std_logic;
+    signal   gt0_txoutclk_i2                 : std_logic;
+    signal   gt0_recclk_stable_i             : std_logic;
+    signal   gt0_rx_cdrlocked                : std_logic;
+    signal   gt0_rx_cdrlock_counter  :   integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
+    signal   gt0_rxphaligndone_i             : std_logic;
+    signal   gt0_rxdlysreset_i               : std_logic;
+    signal   gt0_rxdlysresetdone_i           : std_logic;
+    signal   gt0_rxphdlyreset_i              : std_logic;
+    signal   gt0_rxphalignen_i               : std_logic;
+    signal   gt0_rxdlyen_i                   : std_logic;
+    signal   gt0_rxphalign_i                 : std_logic;
+    signal   gt0_run_rx_phalignment_i        : std_logic;
+    signal   gt0_rst_rx_phalignment_i        : std_logic;
+    signal   gt0_rx_phalignment_done_i       : std_logic;
+
+
+
+    --------------------------- TX Buffer Bypass Signals --------------------
+    signal  mstr0_txsyncallin_i  :   std_logic;
+    signal  U0_TXDLYEN           :   std_logic_vector(0 downto 0);
+    signal  U0_TXDLYSRESET       :   std_logic_vector(0 downto 0);
+    signal  U0_TXDLYSRESETDONE   :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHINIT          :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHINITDONE      :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHALIGN         :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHALIGNDONE     :   std_logic_vector(0 downto 0);
+    signal  U0_run_tx_phalignment_i :   std_logic;
+    signal  U0_rst_tx_phalignment_i :   std_logic;
+
+
+    --------------------------- RX Buffer Bypass Signals --------------------
+    signal   rxmstr0_rxsyncallin_i :   std_logic;
+    signal  U0_RXDLYEN           :   std_logic_vector(0 downto 0);
+    signal  U0_RXDLYSRESET       :   std_logic_vector(0 downto 0);
+    signal  U0_RXDLYSRESETDONE   :   std_logic_vector(0 downto 0);
+    signal  U0_RXPHALIGN         :   std_logic_vector(0 downto 0);
+    signal  U0_RXPHALIGNDONE     :   std_logic_vector(0 downto 0);
+    signal  U0_run_rx_phalignment_i :   std_logic;
+    signal  U0_rst_rx_phalignment_i :   std_logic;
+
+
+
+    signal      rx_cdrlocked                    : std_logic;
+
+
+ 
+
+
+--**************************** Main Body of Code *******************************
+begin
+    --  Static signal Assigments
+    tied_to_ground_i                             <= '0';
+    tied_to_vcc_i                                <= '1';
+
+    ----------------------------- The GT Wrapper -----------------------------
+    
+    -- Use the instantiation template in the example directory to add the GT wrapper to your design.
+    -- In this example, the wrapper is wired up for basic operation with a frame generator and frame 
+    -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is 
+    -- enabled, bonding should occur after alignment.
+
+
+    gtxKintex7FEE80_i : gtxKintex7FEE80_multi_gt
+    generic map
+    (
+        USE_BUFG                        =>      USE_BUFG,
+        WRAPPER_SIM_GTRESET_SPEEDUP     =>      EXAMPLE_SIM_GTRESET_SPEEDUP
+    )
+    port map
+    (
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y0)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_i,
+        gt0_cplllockdetclk_in           =>      gt0_cplllockdetclk_in,
+        gt0_cpllrefclklost_out          =>      gt0_cpllrefclklost_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_i,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      gt0_gtrefclk0_in,
+        gt0_gtrefclk1_in                =>      gt0_gtrefclk1_in,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      gt0_drpclk_in,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_i,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+	------------------------- Receive Ports - CDR Ports ------------------------
+		GT0_RXCDRRESET_IN               => GT0_RXCDRRESET_IN, --// Modified
+		GT0_RXCDRLOCK_OUT               => GT0_RXCDRLOCK_OUT, --// Modified
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_in,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_in,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxdlyen_in                  =>      gt0_rxdlyen_i,
+        gt0_rxdlysreset_in              =>      gt0_rxdlysreset_i,
+        gt0_rxdlysresetdone_out         =>      gt0_rxdlysresetdone_i,
+        gt0_rxphalign_in                =>      gt0_rxphalign_i,
+        gt0_rxphaligndone_out           =>      gt0_rxphaligndone_i,
+        gt0_rxphalignen_in              =>      gt0_rxphalignen_i,
+        gt0_rxphdlyreset_in             =>      gt0_rxphdlyreset_i,
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        gt0_rxlpmhfhold_in              =>      gt0_rxlpmhfhold_i,
+        gt0_rxlpmlfhold_in              =>      gt0_rxlpmlfhold_i,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_i,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_i,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_i,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_in,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_in,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        gt0_txdlyen_in                  =>      gt0_txdlyen_i,
+        gt0_txdlysreset_in              =>      gt0_txdlysreset_i,
+        gt0_txdlysresetdone_out         =>      gt0_txdlysresetdone_i,
+        gt0_txphalign_in                =>      gt0_txphalign_i,
+        gt0_txphaligndone_out           =>      gt0_txphaligndone_i,
+        gt0_txphalignen_in              =>      gt0_txphalignen_i,
+        gt0_txphdlyreset_in             =>      gt0_txphdlyreset_i,
+        gt0_txphinit_in                 =>      gt0_txphinit_i,
+        gt0_txphinitdone_out            =>      gt0_txphinitdone_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_i,
+
+
+
+
+    --____________________________COMMON PORTS________________________________
+        gt0_qplloutclk_in               =>      gt0_qplloutclk_in,
+        gt0_qplloutrefclk_in            =>      gt0_qplloutrefclk_in
+    );
+
+
+gt0_rxdfelpmreset_i                          <= tied_to_ground_i;
+
+
+GT0_CPLLLOCK_OUT                             <= gt0_cplllock_i;
+GT0_TXRESETDONE_OUT                          <= gt0_txresetdone_i;
+GT0_RXRESETDONE_OUT                          <= gt0_rxresetdone_i;
+GT0_RXOUTCLK_OUT                             <= gt0_rxoutclk_i;
+GT0_TXOUTCLK_OUT                             <= gt0_txoutclk_i;
+
+chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
+gt0_cpllreset_i                              <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
+    gt0_gttxreset_i                              <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
+    gt0_gtrxreset_i                              <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
+    gt0_txuserrdy_i                              <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
+    gt0_rxuserrdy_i                              <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
+end generate chipscope;
+
+no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
+gt0_cpllreset_i                              <= gt0_cpllreset_t;
+gt0_gttxreset_i                              <= gt0_gttxreset_t;
+gt0_gtrxreset_i                              <= gt0_gtrxreset_t;
+gt0_txuserrdy_i                              <= gt0_txuserrdy_t;
+gt0_rxuserrdy_i                              <= gt0_rxuserrdy_t;
+end generate no_chipscope;
+
+
+gt0_txresetfsm_i:  gtxKintex7FEE80_TX_STARTUP_FSM 
+
+  generic map(
+           EXAMPLE_SIMULATION       => EXAMPLE_SIMULATION,
+           STABLE_CLOCK_PERIOD      => STABLE_CLOCK_PERIOD,           -- Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   => 8, 
+           TX_QPLL_USED             => FALSE ,                       -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             => FALSE,                        -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   => TRUE                 -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                     -- is enough. For single-lane applications the automatic alignment is 
+                                                                     -- sufficient              
+             )     
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        TXUSERCLK                       =>      GT0_TXUSRCLK_IN,
+        SOFT_RESET                      =>      SOFT_RESET_TX_IN,
+        QPLLREFCLKLOST                  =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      gt0_cpllrefclklost_i,
+        QPLLLOCK                        =>      tied_to_vcc_i,
+        CPLLLOCK                        =>      gt0_cplllock_i,
+        TXRESETDONE                     =>      gt0_txresetdone_i,
+        MMCM_LOCK                       =>      GT0_TX_MMCM_LOCK_IN,
+        GTTXRESET                       =>      gt0_gttxreset_t,
+        MMCM_RESET                      =>      GT0_TX_MMCM_RESET_OUT,
+        QPLL_RESET                      =>      open,
+        CPLL_RESET                      =>      gt0_cpllreset_t,
+        TX_FSM_RESET_DONE               =>      GT0_TX_FSM_RESET_DONE_OUT,
+        TXUSERRDY                       =>      gt0_txuserrdy_t,
+        RUN_PHALIGNMENT                 =>      gt0_run_tx_phalignment_i,
+        RESET_PHALIGNMENT               =>      gt0_rst_tx_phalignment_i,
+        PHALIGNMENT_DONE                =>      gt0_tx_phalignment_done_i,
+        RETRY_COUNTER                   =>      open
+           );
+
+
+
+
+
+
+
+
+gt0_rxresetfsm_i:  gtxKintex7FEE80_RX_STARTUP_FSM 
+
+  generic map(
+           EXAMPLE_SIMULATION       => EXAMPLE_SIMULATION,
+           EQ_MODE                  => "LPM",                 --Rx Equalization Mode - Set to DFE or LPM
+           STABLE_CLOCK_PERIOD      => STABLE_CLOCK_PERIOD,           --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   => 8, 
+           TX_QPLL_USED             => FALSE ,                       -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             => FALSE,                        -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   =>  FALSE                        -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                     -- is enough. For single-lane applications the automatic alignment is 
+                                                                     -- sufficient              
+             )     
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        RXUSERCLK                       =>      GT0_RXUSRCLK_IN,
+        SOFT_RESET                      =>      SOFT_RESET_RX_IN,
+        DONT_RESET_ON_DATA_ERROR        =>      DONT_RESET_ON_DATA_ERROR_IN,
+        QPLLREFCLKLOST                  =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      gt0_cpllrefclklost_i,
+        QPLLLOCK                        =>      tied_to_vcc_i,
+        CPLLLOCK                        =>      gt0_cplllock_i,
+        RXRESETDONE                     =>      gt0_rxresetdone_i,
+        MMCM_LOCK                       =>      tied_to_vcc_i,
+        RECCLK_STABLE                   =>      gt0_recclk_stable_i,
+        RECCLK_MONITOR_RESTART          =>      tied_to_ground_i,
+        DATA_VALID                      =>      GT0_DATA_VALID_IN,
+        TXUSERRDY                       =>      tied_to_vcc_i,
+        GTRXRESET                       =>      gt0_gtrxreset_t,
+        MMCM_RESET                      =>      open,
+        QPLL_RESET                      =>      open,
+        CPLL_RESET                      =>      open,
+        RX_FSM_RESET_DONE               =>      GT0_RX_FSM_RESET_DONE_OUT,
+        RXUSERRDY                       =>      gt0_rxuserrdy_t,
+        RUN_PHALIGNMENT                 =>      gt0_run_rx_phalignment_i,
+        RESET_PHALIGNMENT               =>      gt0_rst_rx_phalignment_i,
+        PHALIGNMENT_DONE                =>      gt0_rx_phalignment_done_i,
+        RXDFEAGCHOLD                    =>      gt0_rxdfeagchold_i,
+        RXDFELFHOLD                     =>      gt0_rxdfelfhold_i,
+        RXLPMLFHOLD                     =>      gt0_rxlpmlfhold_i,
+        RXLPMHFHOLD                     =>      gt0_rxlpmhfhold_i,
+        RETRY_COUNTER                   =>      open
+           );
+
+
+
+  gt0_cdrlock_timeout:process(SYSCLK_IN)
+  begin
+    if rising_edge(SYSCLK_IN) then
+        if(gt0_gtrxreset_i = '1') then
+          gt0_rx_cdrlocked       <= '0';
+          gt0_rx_cdrlock_counter <=  0                        after DLY;
+        elsif (gt0_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
+          gt0_rx_cdrlocked       <= '1';
+          gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter        after DLY;
+        else
+          gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter + 1    after DLY;
+        end if;
+    end if;
+  end process;
+
+gt0_recclk_stable_i                          <= gt0_rx_cdrlocked;
+
+
+
+    --------------------------- TX Buffer Bypass Logic --------------------
+    -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer.
+    -- Include the TX SYNC module in your own design if TX Buffer is bypassed.
+
+
+--Auto
+gt0_txphdlyreset_i                           <= tied_to_ground_i;
+gt0_txphalignen_i                            <= tied_to_ground_i;
+gt0_txdlyen_i                                <= tied_to_ground_i;
+gt0_txphalign_i                              <= tied_to_ground_i;
+gt0_txphinit_i                               <= tied_to_ground_i;
+
+gt0_tx_auto_phase_align_i : gtxKintex7FEE80_AUTO_PHASE_ALIGN    
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        RUN_PHALIGNMENT                 =>      gt0_run_tx_phalignment_i,
+        PHASE_ALIGNMENT_DONE            =>      gt0_tx_phalignment_done_i,
+        PHALIGNDONE                     =>      gt0_txphaligndone_i,
+        DLYSRESET                       =>      gt0_txdlysreset_i,
+        DLYSRESETDONE                   =>      gt0_txdlysresetdone_i,
+        RECCLKSTABLE                    =>      tied_to_vcc_i
+           );
+
+
+
+
+   --------------------------- RX Buffer Bypass Logic --------------------
+--   The RX SYNC Module drives the ports needed to Bypass the RX Buffer.
+--   Include the RX SYNC module in your own design if RX Buffer is bypassed.
+
+
+--Auto
+gt0_rxphdlyreset_i                           <=  '1'; --// Modified???????  tied_to_ground_i;
+gt0_rxphalignen_i                            <=  '1'; --// Modified???????  tied_to_ground_i;
+gt0_rxdlyen_i                                <= tied_to_ground_i;
+gt0_rxphalign_i                              <= tied_to_ground_i;
+
+
+gt0_rx_phalignment_done_i <= '1'; --// Modified
+gt0_rxdlysreset_i <= '1'; --// Modified
+-- gt0_rx_auto_phase_align_i : gtxKintex7FEE80_AUTO_PHASE_ALIGN    
+  -- port map ( 
+        -- STABLE_CLOCK                    =>      SYSCLK_IN,
+        -- RUN_PHALIGNMENT                 =>      gt0_run_rx_phalignment_i,
+        -- PHASE_ALIGNMENT_DONE            =>      gt0_rx_phalignment_done_i,
+        -- PHALIGNDONE                     =>      gt0_rxphaligndone_i,
+        -- DLYSRESET                       =>      gt0_rxdlysreset_i,
+        -- DLYSRESETDONE                   =>      gt0_rxdlysresetdone_i,
+        -- RECCLKSTABLE                    =>      gt0_recclk_stable_i
+     -- );
+
+
+
+end RTL;
+
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_multi_gt.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_multi_gt.vhd
new file mode 100644
index 0000000..0bdbbd2
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_multi_gt.vhd
@@ -0,0 +1,509 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtxkintex7fee80_multi_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_multi_gt (a Multi GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+
+entity gtxKintex7FEE80_multi_gt is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE";        -- Set to "TRUE" to speed up sim reset
+    RX_DFE_KL_CFG2_IN               : bit_vector :=  X"301148AC";
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+ 
+    PMA_RSV_IN                      : bit_vector :=  x"00018480"
+);
+port
+(
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X0Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllrefclklost_out                  : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxdlyen_in                          : in   std_logic;
+    gt0_rxdlysreset_in                      : in   std_logic;
+    gt0_rxdlysresetdone_out                 : out  std_logic;
+    gt0_rxphalign_in                        : in   std_logic;
+    gt0_rxphaligndone_out                   : out  std_logic;
+    gt0_rxphalignen_in                      : in   std_logic;
+    gt0_rxphdlyreset_in                     : in   std_logic;
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    gt0_rxlpmhfhold_in                      : in   std_logic;
+    gt0_rxlpmlfhold_in                      : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    gt0_txdlyen_in                          : in   std_logic;
+    gt0_txdlysreset_in                      : in   std_logic;
+    gt0_txdlysresetdone_out                 : out  std_logic;
+    gt0_txphalign_in                        : in   std_logic;
+    gt0_txphaligndone_out                   : out  std_logic;
+    gt0_txphalignen_in                      : in   std_logic;
+    gt0_txphdlyreset_in                     : in   std_logic;
+    gt0_txphinit_in                         : in   std_logic;
+    gt0_txphinitdone_out                    : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+
+end gtxKintex7FEE80_multi_gt;
+    
+architecture RTL of gtxKintex7FEE80_multi_gt is
+    attribute DowngradeIPIdentifiedWarnings: string;
+    attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80_multi_gt,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--***************************** Signal Declarations *****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal   gt0_qplloutclk_i         :   std_logic;
+    signal   gt0_qplloutrefclk_i      :   std_logic;
+
+    signal  gt0_mgtrefclktx_i           :   std_logic_vector(1 downto 0);
+    signal  gt0_mgtrefclkrx_i           :   std_logic_vector(1 downto 0);
+ 
+    signal   gt0_qpllclk_i            :   std_logic;
+    signal   gt0_qpllrefclk_i         :   std_logic;
+    signal   gt0_cpllreset_i            :   std_logic;
+    signal   gt0_cpllpd_i         :   std_logic;
+    signal   cpll_reset0_i            :   std_logic;
+    signal   cpll_pd0_i         :   std_logic;
+
+--*************************** Component Declarations **************************
+component gtxKintex7FEE80_GT
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP       : string   := "FALSE";
+    RX_DFE_KL_CFG2_IN            : bit_vector :=   X"3010D90C";
+    PMA_RSV_IN                   : bit_vector :=   X"00000000";
+    SIM_CPLLREFCLK_SEL           : bit_vector :=   "001";
+    PCS_RSVD_ATTR_IN             : bit_vector :=   X"000000000000"
+);
+port 
+(   
+     cpllpd_in : in std_logic;
+     cpllrefclksel_in : in std_logic_vector (2 downto 0);
+    --------------------------------- CPLL Ports -------------------------------
+    cpllfbclklost_out                       : out  std_logic;
+    cplllock_out                            : out  std_logic;
+    cplllockdetclk_in                       : in   std_logic;
+    cpllrefclklost_out                      : out  std_logic;
+    cpllreset_in                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gtrefclk0_in                            : in   std_logic;
+    gtrefclk1_in                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    drpaddr_in                              : in   std_logic_vector(8 downto 0);
+    drpclk_in                               : in   std_logic;
+    drpdi_in                                : in   std_logic_vector(15 downto 0);
+    drpdo_out                               : out  std_logic_vector(15 downto 0);
+    drpen_in                                : in   std_logic;
+    drprdy_out                              : out  std_logic;
+    drpwe_in                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    qpllclk_in                              : in   std_logic;
+    qpllrefclk_in                           : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    dmonitorout_out                         : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    eyescanreset_in                         : in   std_logic;
+    rxuserrdy_in                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    eyescandataerror_out                    : out  std_logic;
+    eyescantrigger_in                       : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	RXCDRRESET_IN                           : in  std_logic; --// Modified
+    RXCDRLOCK_OUT                           : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    rxusrclk_in                             : in   std_logic;
+    rxusrclk2_in                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    rxdata_out                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    rxdisperr_out                           : out  std_logic_vector(1 downto 0);
+    rxnotintable_out                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gtxrxp_in                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gtxrxn_in                               : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    rxdlyen_in                              : in   std_logic;
+    rxdlysreset_in                          : in   std_logic;
+    rxdlysresetdone_out                     : out  std_logic;
+    rxphalign_in                            : in   std_logic;
+    rxphaligndone_out                       : out  std_logic;
+    rxphalignen_in                          : in   std_logic;
+    rxphdlyreset_in                         : in   std_logic;
+    rxphmonitor_out                         : out  std_logic_vector(4 downto 0);
+    rxphslipmonitor_out                     : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    rxlpmhfhold_in                          : in   std_logic;
+    rxlpmlfhold_in                          : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    rxdfelpmreset_in                        : in   std_logic;
+    rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
+    rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    rxoutclk_out                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gtrxreset_in                            : in   std_logic;
+    rxpmareset_in                           : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    rxcharisk_out                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    rxresetdone_out                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gttxreset_in                            : in   std_logic;
+    txuserrdy_in                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    txusrclk_in                             : in   std_logic;
+    txusrclk2_in                            : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    txdlyen_in                              : in   std_logic;
+    txdlysreset_in                          : in   std_logic;
+    txdlysresetdone_out                     : out  std_logic;
+    txphalign_in                            : in   std_logic;
+    txphaligndone_out                       : out  std_logic;
+    txphalignen_in                          : in   std_logic;
+    txphdlyreset_in                         : in   std_logic;
+    txphinit_in                             : in   std_logic;
+    txphinitdone_out                        : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    txdata_in                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gtxtxn_out                              : out  std_logic;
+    gtxtxp_out                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    txoutclk_out                            : out  std_logic;
+    txoutclkfabric_out                      : out  std_logic;
+    txoutclkpcs_out                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    txcharisk_in                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    txresetdone_out                         : out  std_logic
+
+
+);
+end component;
+component gtxKintex7FEE80_cpll_railing
+  Generic(
+           USE_BUFG       : integer := 0
+);
+port 
+(   
+        cpll_reset_out : out std_logic;
+         cpll_pd_out : out std_logic;
+         refclk_out : out std_logic;
+        
+         refclk_in : in std_logic
+
+);
+end component;
+
+
+
+--********************************* Main Body of Code**************************
+
+begin                       
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    gt0_qpllclk_i    <= GT0_QPLLOUTCLK_IN;  
+    gt0_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN; 
+
+
+ 
+    --------------------------- GT Instances  -------------------------------   
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X0Y0)
+
+gt0_gtxKintex7FEE80_i : gtxKintex7FEE80_GT 
+    generic map
+    (
+        -- Simulation attributes
+        GT_SIM_GTRESET_SPEEDUP        =>  WRAPPER_SIM_GTRESET_SPEEDUP,
+        RX_DFE_KL_CFG2_IN             =>  RX_DFE_KL_CFG2_IN,
+        SIM_CPLLREFCLK_SEL            =>  "001",
+        PMA_RSV_IN                    =>  PMA_RSV_IN,
+        PCS_RSVD_ATTR_IN              =>  X"000000000000"
+    )
+    port map
+    (
+        cpllpd_in => gt0_cpllpd_i,
+        cpllrefclksel_in => "001",
+        --------------------------------- CPLL Ports -------------------------------
+        cpllfbclklost_out               =>      gt0_cpllfbclklost_out,
+        cplllock_out                    =>      gt0_cplllock_out,
+        cplllockdetclk_in               =>      gt0_cplllockdetclk_in,
+        cpllrefclklost_out              =>      gt0_cpllrefclklost_out,
+        cpllreset_in                    =>      gt0_cpllreset_i,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gtrefclk0_in                    =>      gt0_gtrefclk0_in,
+        gtrefclk1_in                    =>      gt0_gtrefclk1_in,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        drpaddr_in                      =>      gt0_drpaddr_in,
+        drpclk_in                       =>      gt0_drpclk_in,
+        drpdi_in                        =>      gt0_drpdi_in,
+        drpdo_out                       =>      gt0_drpdo_out,
+        drpen_in                        =>      gt0_drpen_in,
+        drprdy_out                      =>      gt0_drprdy_out,
+        drpwe_in                        =>      gt0_drpwe_in,
+        ------------------------------- Clocking Ports -----------------------------
+        qpllclk_in                      =>      gt0_qpllclk_i,
+        qpllrefclk_in                   =>      gt0_qpllrefclk_i,
+        --------------------------- Digital Monitor Ports --------------------------
+        dmonitorout_out                 =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        eyescanreset_in                 =>      gt0_eyescanreset_in,
+        rxuserrdy_in                    =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        eyescandataerror_out            =>      gt0_eyescandataerror_out,
+        eyescantrigger_in               =>      gt0_eyescantrigger_in,
+		------------------------- Receive Ports - CDR Ports ------------------------
+		RXCDRRESET_IN                   =>      GT0_RXCDRRESET_IN, --// Modified
+		RXCDRLOCK_OUT                   =>      GT0_RXCDRLOCK_OUT, --// Modified
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        rxusrclk_in                     =>      gt0_rxusrclk_in,
+        rxusrclk2_in                    =>      gt0_rxusrclk2_in,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        rxdata_out                      =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        rxdisperr_out                   =>      gt0_rxdisperr_out,
+        rxnotintable_out                =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gtxrxp_in                       =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gtxrxn_in                       =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        rxdlyen_in                      =>      gt0_rxdlyen_in,
+        rxdlysreset_in                  =>      gt0_rxdlysreset_in,
+        rxdlysresetdone_out             =>      gt0_rxdlysresetdone_out,
+        rxphalign_in                    =>      gt0_rxphalign_in,
+        rxphaligndone_out               =>      gt0_rxphaligndone_out,
+        rxphalignen_in                  =>      gt0_rxphalignen_in,
+        rxphdlyreset_in                 =>      gt0_rxphdlyreset_in,
+        rxphmonitor_out                 =>      gt0_rxphmonitor_out,
+        rxphslipmonitor_out             =>      gt0_rxphslipmonitor_out,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        rxlpmhfhold_in                  =>      gt0_rxlpmhfhold_in,
+        rxlpmlfhold_in                  =>      gt0_rxlpmlfhold_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        rxdfelpmreset_in                =>      gt0_rxdfelpmreset_in,
+        rxmonitorout_out                =>      gt0_rxmonitorout_out,
+        rxmonitorsel_in                 =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        rxoutclk_out                    =>      gt0_rxoutclk_out,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gtrxreset_in                    =>      gt0_gtrxreset_in,
+        rxpmareset_in                   =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        rxcharisk_out                   =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        rxresetdone_out                 =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gttxreset_in                    =>      gt0_gttxreset_in,
+        txuserrdy_in                    =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        txusrclk_in                     =>      gt0_txusrclk_in,
+        txusrclk2_in                    =>      gt0_txusrclk2_in,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        txdlyen_in                      =>      gt0_txdlyen_in,
+        txdlysreset_in                  =>      gt0_txdlysreset_in,
+        txdlysresetdone_out             =>      gt0_txdlysresetdone_out,
+        txphalign_in                    =>      gt0_txphalign_in,
+        txphaligndone_out               =>      gt0_txphaligndone_out,
+        txphalignen_in                  =>      gt0_txphalignen_in,
+        txphdlyreset_in                 =>      gt0_txphdlyreset_in,
+        txphinit_in                     =>      gt0_txphinit_in,
+        txphinitdone_out                =>      gt0_txphinitdone_out,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        txdata_in                       =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gtxtxn_out                      =>      gt0_gtxtxn_out,
+        gtxtxp_out                      =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        txoutclk_out                    =>      gt0_txoutclk_out,
+        txoutclkfabric_out              =>      gt0_txoutclkfabric_out,
+        txoutclkpcs_out                 =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        txcharisk_in                    =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        txresetdone_out                 =>      gt0_txresetdone_out
+
+    );
+
+
+   cpll_railing0_i : gtxKintex7FEE80_cpll_railing
+  generic map(
+           USE_BUFG       => USE_BUFG
+   ) 
+   port map
+   (
+        cpll_reset_out => cpll_reset0_i,
+        cpll_pd_out => cpll_pd0_i,
+        refclk_out => open,
+        refclk_in => gt0_gtrefclk0_in
+);
+
+
+gt0_cpllreset_i <= cpll_reset0_i or gt0_cpllreset_in; 
+gt0_cpllpd_i <= cpll_pd0_i ; 
+end RTL;     
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_rx_startup_fsm.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_rx_startup_fsm.vhd
new file mode 100644
index 0000000..60c1802
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_rx_startup_fsm.vhd
@@ -0,0 +1,788 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 3.5
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename : gtxkintex7fee80_rx_startup_fsm.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--  Description :     This module performs RX reset and initialization.
+--                     
+--
+--
+-- Module gtxKintex7FEE80_rx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library unisim;
+use unisim.vcomponents.all;
+
+entity gtxKintex7FEE80_RX_STARTUP_FSM is
+  Generic( EXAMPLE_SIMULATION       : integer := 0;
+           EQ_MODE                  : string  := "DFE";           --RX Equalisation Mode; set to DFE or LPM
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient                         
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;        --Stable Clock, either a stable clock from the PCB
+                                                            --or reference-clock present at startup.
+           RXUSERCLK                : in  STD_LOGIC;        --RXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;        --User Reset, can be pulled any time
+
+           QPLLREFCLKLOST           : in  STD_LOGIC;        --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;        --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the CPLL of the GT
+           RXRESETDONE              : in  STD_LOGIC;
+           MMCM_LOCK                : in  STD_LOGIC;
+           RECCLK_STABLE            : in  STD_LOGIC;
+           RECCLK_MONITOR_RESTART   : in  STD_LOGIC:='0';
+           DATA_VALID               : in  STD_LOGIC;
+           TXUSERRDY                : in  STD_LOGIC;       --TXUSERRDY from GT 
+           DONT_RESET_ON_DATA_ERROR : in  STD_LOGIC;       --Used to control the Auto-Reset of FSM when Data Error is detected
+           GTRXRESET                : out STD_LOGIC;
+           MMCM_RESET               : out STD_LOGIC;
+           QPLL_RESET               : out STD_LOGIC:='0';  --Reset QPLL (only if RX uses QPLL)
+           CPLL_RESET               : out STD_LOGIC:='0';  --Reset CPLL (only if RX uses CPLL)
+           RX_FSM_RESET_DONE        : out STD_LOGIC;       --Reset-sequence has sucessfully been finished.
+           RXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC;
+           PHALIGNMENT_DONE         : in  STD_LOGIC; 
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';           
+           RXDFEAGCHOLD             : out STD_LOGIC;
+           RXDFELFHOLD              : out STD_LOGIC;
+           RXLPMLFHOLD              : out STD_LOGIC;
+           RXLPMHFHOLD              : out STD_LOGIC;
+           RETRY_COUNTER            : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end gtxKintex7FEE80_RX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+--   are calculated at design-time based on the Generics
+--   
+-- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
+--   => signal which PLL has been reset
+-- * 
+
+
+
+architecture RTL of gtxKintex7FEE80_RX_STARTUP_FSM is
+
+  component gtxKintex7FEE80_sync_block
+   generic (
+     INITIALISE : bit_vector(5 downto 0) := "000000"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+  type rx_rst_fsm_type is(
+    INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
+    RELEASE_MMCM_RESET, WAIT_FOR_RXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+    MONITOR_DATA_VALID, FSM_DONE);
+    
+  signal rx_state : rx_rst_fsm_type := INIT;
+
+  constant MMCM_LOCK_CNT_MAX    : integer := 256;
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+  constant WAIT_TIMEOUT_2ms     : integer := 2000000 / STABLE_CLOCK_PERIOD;--  2 ms time-out
+  constant WAIT_TLOCK_MAX       : integer :=  100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_TIMEOUT_500us   : integer :=  500000 / STABLE_CLOCK_PERIOD;--500 us time-out
+  constant WAIT_TIMEOUT_1us     : integer :=  1000 / STABLE_CLOCK_PERIOD;  --1 us time-out
+  constant WAIT_TIMEOUT_100us    : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
+  constant WAIT_TIME_ADAPT      : integer := (37000000 /integer(2))/STABLE_CLOCK_PERIOD;
+  constant WAIT_TIME_MAX    : integer := 100 ; --10 us time-out
+    
+  signal init_wait_count        : integer range 0 to WAIT_MAX:=0;
+  signal init_wait_done         : std_logic := '0';
+  signal pll_reset_asserted     : std_logic := '0';
+  signal rx_fsm_reset_done_int  : std_logic := '0';
+  signal rx_fsm_reset_done_int_s2  : std_logic := '0';
+  signal rx_fsm_reset_done_int_s3  : std_logic := '0';
+   
+  signal rxresetdone_s2         : std_logic := '0'; 
+  signal rxresetdone_s3         : std_logic := '0'; 
+
+  constant MAX_RETRIES          : integer := 2**RETRY_COUNTER_BITWIDTH-1; 
+  signal retry_counter_int      : integer range 0 to MAX_RETRIES := 0;  
+  signal time_out_counter       : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+  signal recclk_mon_restart_count : integer range 0 to 3:= 0;
+  signal recclk_mon_count_reset   : std_logic := '0';
+  
+  signal reset_time_out         : std_logic := '0';
+  signal time_out_2ms           : std_logic := '0';--\Flags that the various time-out points 
+  signal time_tlock_max         : std_logic := '0';--|have been reached.
+  signal time_out_500us         : std_logic := '0';--|
+  signal time_out_1us           : std_logic := '0';--/
+  signal time_out_100us         : std_logic := '0';--/
+  signal check_tlock_max        : std_logic := '0';
+    
+  signal mmcm_lock_count        : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+  signal mmcm_lock_int          : std_logic := '0';
+  signal mmcm_lock_i            : std_logic := '0';
+  signal mmcm_lock_reclocked    : std_logic := '0';
+  signal gtrxreset_i    : std_logic := '0';
+  signal mmcm_reset_i    : std_logic := '1';
+  signal rxpmaresetdone_i    : std_logic := '0';
+  signal txpmaresetdone_i    : std_logic := '0';
+  signal rxpmaresetdone_ss    : std_logic := '0';
+  signal rxpmaresetdone_sync    : std_logic ;
+  signal txpmaresetdone_sync    : std_logic ;
+  signal rxpmaresetdone_s    : std_logic ;
+  signal rxpmaresetdone_rx_s    : std_logic ;
+  signal pmaresetdone_fallingedge_detect    : std_logic ;
+  signal pmaresetdone_fallingedge_detect_s    : std_logic ;
+    
+  signal run_phase_alignment_int: std_logic := '0';
+  signal run_phase_alignment_int_s2 : std_logic := '0';
+  signal run_phase_alignment_int_s3 : std_logic := '0';
+
+  constant MAX_WAIT_BYPASS        : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
+  signal wait_bypass_count        : integer range 0 to MAX_WAIT_BYPASS-1;
+  signal time_out_wait_bypass     : std_logic := '0';
+  signal time_out_wait_bypass_s2   : std_logic := '0';
+  signal time_out_wait_bypass_s3   : std_logic := '0';
+
+  signal refclk_lost              : std_logic;
+
+  signal time_out_adapt           : std_logic := '0';   
+  signal adapt_count_reset        : std_logic := '0';   
+  signal adapt_count              : integer range 0 to WAIT_TIME_ADAPT-1;
+  signal      data_valid_sync: std_logic := '0';
+  signal      cplllock_sync: std_logic := '0';
+  signal      qplllock_sync: std_logic := '0';
+  signal      cplllock_prev: std_logic := '0';
+  signal      qplllock_prev: std_logic := '0';
+  signal      cplllock_ris_edge: std_logic := '0';
+  signal      qplllock_ris_edge: std_logic := '0';
+  signal      wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+  signal      wait_time_done : std_logic;
+
+
+  attribute shreg_extract                   : string;
+  attribute ASYNC_REG                       : string;
+
+  signal      reset_sync_reg1_tx : std_logic;
+  signal      reset_sync_reg1 : std_logic;
+  signal      gtrxreset_s : std_logic;
+  signal      gtrxreset_tx_s : std_logic;
+  signal      txpmaresetdone_s : std_logic;
+begin
+  --Alias section, signals used within this module mapped to output ports:
+  RETRY_COUNTER     <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+  RUN_PHALIGNMENT   <= run_phase_alignment_int;
+  RX_FSM_RESET_DONE <= rx_fsm_reset_done_int;
+  GTRXRESET <= gtrxreset_i; 
+  MMCM_RESET <= mmcm_reset_i; 
+  process(STABLE_CLOCK,SOFT_RESET)
+  begin
+    if (SOFT_RESET = '1') then
+        init_wait_done <= '0';
+        init_wait_count <= 0 ;
+    elsif rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+
+  adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate
+      time_out_adapt <= '1';
+  end generate;
+
+  adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(adapt_count_reset = '1') then
+        adapt_count    <= 0;
+        time_out_adapt <= '0';
+     elsif(adapt_count = WAIT_TIME_ADAPT -1) then
+        time_out_adapt <= '1';
+     else 
+        adapt_count    <= adapt_count + 1;  
+     end if;
+    end if;
+  end process;
+  end generate;
+
+  retries_recclk_monitor:process(STABLE_CLOCK)
+  begin
+    --This counter monitors, how many retries the RECCLK monitor
+    --runs. If during startup too many retries are necessary, the whole 
+    --initialisation-process of the transceivers gets restarted.
+    if rising_edge(STABLE_CLOCK) then  
+      if recclk_mon_count_reset = '1' then
+        recclk_mon_restart_count <= 0;
+      elsif RECCLK_MONITOR_RESTART = '1' then
+        if recclk_mon_restart_count = 3 then
+          recclk_mon_restart_count <= 0;
+        else 
+          recclk_mon_restart_count <= recclk_mon_restart_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  timeouts:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- One common large counter for generating three time-out signals.
+      -- Intermediate time-outs are derived from calculated values, based
+      -- on the period of the provided clock.
+      if reset_time_out = '1' then
+        time_out_counter  <= 0;
+        time_out_2ms      <= '0';
+        time_tlock_max    <= '0';
+        time_out_500us    <= '0';
+        time_out_1us      <= '0';
+        time_out_100us    <= '0';
+      else
+        if time_out_counter = WAIT_TIMEOUT_2ms then
+          time_out_2ms <= '1';
+        else
+          time_out_counter <= time_out_counter + 1;
+        end if;
+        
+        if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
+          time_tlock_max <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_500us then
+          time_out_500us <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_1us then
+          time_out_1us <= '1';
+        end if;
+
+        if time_out_counter = WAIT_TIMEOUT_100us then
+          time_out_100us <= '1';
+        end if;
+
+      end if;
+    end if;
+  end process;
+
+
+
+  mmcm_lock_wait:process(STABLE_CLOCK)
+  begin
+    --The lock-signal from the MMCM is not immediately used but 
+    --enabling a counter. Only when the counter hits its maximum,
+    --the MMCM is considered as "really" locked. 
+    --The counter avoids that the FSM already starts on only a 
+    --coarse lock of the MMCM (=toggling of the LOCK-signal).
+    if rising_edge(STABLE_CLOCK) then
+      if mmcm_lock_i = '0' then
+        mmcm_lock_count <= 0;
+        mmcm_lock_reclocked   <= '0';
+      else       
+        if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+          mmcm_lock_count <= mmcm_lock_count + 1;
+        else
+          mmcm_lock_reclocked <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+  -- Clock Domain Crossing
+
+  sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  RXUSERCLK,
+            data_in         =>  run_phase_alignment_int,
+            data_out        =>  run_phase_alignment_int_s2 
+         );
+
+  sync_rx_fsm_reset_done_int : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  RXUSERCLK,
+            data_in         =>  rx_fsm_reset_done_int,
+            data_out        =>  rx_fsm_reset_done_int_s2 
+         );
+
+  process(RXUSERCLK)
+  begin
+    if rising_edge(RXUSERCLK) then
+      run_phase_alignment_int_s3   <=  run_phase_alignment_int_s2;
+
+      rx_fsm_reset_done_int_s3     <=  rx_fsm_reset_done_int_s2;
+    end if;
+  end process;
+
+ sync_RXRESETDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  RXRESETDONE,
+            data_out        =>  rxresetdone_s2 
+         );
+
+  sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  time_out_wait_bypass,
+            data_out        =>  time_out_wait_bypass_s2 
+         );
+
+  sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  MMCM_LOCK,
+            data_out        =>  mmcm_lock_i 
+         );
+
+  sync_data_valid : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  DATA_VALID,
+            data_out        =>  data_valid_sync
+         );
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+       rxresetdone_s3     <= rxresetdone_s2;
+
+       time_out_wait_bypass_s3 <=  time_out_wait_bypass_s2;
+
+       cplllock_prev           <=  cplllock_sync;
+       qplllock_prev           <=  qplllock_sync;
+    end if;
+  end process;
+
+ sync_CPLLLOCK : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  CPLLLOCK,
+            data_out        =>  cplllock_sync
+         );
+
+ sync_QPLLLOCK : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  QPLLLOCK,
+            data_out        =>  qplllock_sync
+         );
+
+
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       cplllock_ris_edge <= '0';
+     elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+       cplllock_ris_edge <= '1';
+     elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+       cplllock_ris_edge <= cplllock_ris_edge;
+     else 
+       cplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       qplllock_ris_edge <= '0';
+     elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+       qplllock_ris_edge <= '1';
+     elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+       qplllock_ris_edge <= qplllock_ris_edge;
+     else 
+       qplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+
+  timeout_buffer_bypass:process(RXUSERCLK)
+  begin
+    if rising_edge(RXUSERCLK) then
+      if run_phase_alignment_int_s3 = '0' then
+        wait_bypass_count     <= 0;
+        time_out_wait_bypass  <= '0';
+      elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
+        if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+          time_out_wait_bypass <= '1';
+        else
+          wait_bypass_count <= wait_bypass_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+   refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+
+  timeout_max:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+        if((rx_state = ASSERT_ALL_RESETS) or
+          (rx_state = RELEASE_MMCM_RESET)) then
+            wait_time_cnt <= WAIT_TIME_MAX;
+        elsif (wait_time_cnt > 0 ) then
+            wait_time_cnt <= wait_time_cnt - 1;
+          end if;
+       end if;
+   end process;
+
+  wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+ 
+  --FSM for resetting the GTX/GTH/GTP in the 7-series. 
+  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  --
+  -- Following steps are performed:
+  -- 1) After configuration wait for approximately 500 ns as specified in 
+  --    answer-record 43482
+  -- 2) Assert all resets on the GT and on an MMCM potentially connected. 
+  --    After that wait until a reference-clock has been detected.
+  -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+  -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+  --    Also get info from the TX-side which PLL has been reset.
+  -- 5) Wait for the RESET_DONE-signal from the GT.
+  -- 6) Signal to start the phase-alignment procedure and wait for it to 
+  --    finish.
+  -- 7) Reset-sequence has successfully run through. Signal this to the 
+  --    rest of the design by asserting RX_FSM_RESET_DONE.
+  
+  reset_fsm:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if (SOFT_RESET = '1' ) then
+      --if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+        rx_state                <= INIT;
+        RXUSERRDY               <= '0';
+        gtrxreset_i               <= '0';
+        mmcm_reset_i              <= '0';
+        rx_fsm_reset_done_int   <= '0';
+        QPLL_RESET              <= '0';
+        CPLL_RESET              <= '0';
+        pll_reset_asserted      <= '0';
+        reset_time_out          <= '1';
+        retry_counter_int       <=  0;
+        run_phase_alignment_int <= '0';
+        check_tlock_max         <= '0';
+        RESET_PHALIGNMENT       <= '1';
+        recclk_mon_count_reset  <= '1';
+        adapt_count_reset       <= '1';
+        RXDFEAGCHOLD            <= '0';
+        RXDFELFHOLD             <= '0';
+        RXLPMLFHOLD             <= '0';
+        RXLPMHFHOLD             <= '0';
+
+      else
+        
+        case rx_state is
+          when INIT => 
+            --Initial state after configuration. This state will be left after
+            --approx. 500 ns and not be re-entered. 
+            if init_wait_done = '1' then
+              rx_state  <= ASSERT_ALL_RESETS;
+            end if;
+            
+          when ASSERT_ALL_RESETS => 
+            --This is the state into which the FSM will always jump back if any
+            --time-outs will occur. 
+            --The number of retries is reported on the output RETRY_COUNTER. In 
+            --case the transceiver never comes up for some reason, this machine 
+            --will still continue its best and rerun until the FPGA is turned off
+            --or the transceivers come up correctly.
+             if RX_QPLL_USED and not TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                QPLL_RESET          <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                QPLL_RESET          <= '0';
+              end if;
+            elsif not RX_QPLL_USED and TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                CPLL_RESET <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                CPLL_RESET          <= '0';
+              end if;  
+            end if;
+
+            RXUSERRDY               <= '0';
+            gtrxreset_i               <= '1';
+            mmcm_reset_i              <= '1';
+            run_phase_alignment_int <= '0';    
+            RESET_PHALIGNMENT       <= '1';
+            check_tlock_max         <= '0';
+            recclk_mon_count_reset  <= '1';
+            adapt_count_reset       <= '1';
+            
+            if (RX_QPLL_USED     and not TX_QPLL_USED  and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+               (not RX_QPLL_USED and TX_QPLL_USED  and (cplllock_sync = '0') and pll_reset_asserted = '1') or
+               (not RX_QPLL_USED and not TX_QPLL_USED  ) or
+               (RX_QPLL_USED and  TX_QPLL_USED  ) then
+              rx_state  <= WAIT_FOR_PLL_LOCK;
+              reset_time_out          <= '1';
+            end if;           
+           
+          when  WAIT_FOR_PLL_LOCK =>
+              if(wait_time_done = '1') then
+                 rx_state        <=  RELEASE_PLL_RESET;  
+            end if;
+ 
+          when RELEASE_PLL_RESET => 
+            --PLL-Reset of the GTX gets released and the time-out counter
+            --starts running.
+            pll_reset_asserted  <= '0';
+            reset_time_out  <= '0';
+            
+            if (RX_QPLL_USED     and not TX_QPLL_USED and (qplllock_sync = '1')) or
+               (not RX_QPLL_USED and TX_QPLL_USED     and (cplllock_sync = '1')) then
+              rx_state                <= VERIFY_RECCLK_STABLE;
+              reset_time_out          <= '1';
+              recclk_mon_count_reset  <= '0';
+              adapt_count_reset       <= '0';
+            elsif (RX_QPLL_USED and (qplllock_sync = '1')) or
+                  (not RX_QPLL_USED and (cplllock_sync = '1')) then
+              rx_state                <= VERIFY_RECCLK_STABLE;
+              reset_time_out          <= '1';
+              recclk_mon_count_reset  <= '0';
+              adapt_count_reset       <= '0';
+            end if;
+            
+            if time_out_2ms = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+
+          when VERIFY_RECCLK_STABLE =>
+            --reset_time_out  <= '0';
+            --Time-out counter is not released in this state as here the FSM
+            --does not wait for a certain period of time but checks on the number
+            --of retries in the RECCLK monitor 
+            gtrxreset_i <= '0';
+            if RECCLK_STABLE = '1' then
+              rx_state        <= RELEASE_MMCM_RESET;
+              reset_time_out  <= '1';
+              
+            end if;          
+
+            if recclk_mon_restart_count = 2 then
+              --If two retries are performed in the RECCLK monitor
+              --the whole initialisation-sequence gets restarted.
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+          
+          when RELEASE_MMCM_RESET => 
+            --Release of the MMCM-reset. Waiting for the MMCM to lock.
+            check_tlock_max <= '1';
+            
+            mmcm_reset_i <= '0';
+            reset_time_out  <= '0';
+         
+            if mmcm_lock_reclocked = '1' then
+              rx_state <= WAIT_FOR_RXUSRCLK;
+              reset_time_out  <= '1';
+            end if;          
+            
+            if (time_tlock_max = '1' and reset_time_out = '0' )then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+ 
+           when WAIT_FOR_RXUSRCLK =>
+              if wait_time_done = '1' then
+               rx_state <=  WAIT_RESET_DONE;  
+            end if;
+           
+          when WAIT_RESET_DONE => 
+            --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
+            --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
+            if TXUSERRDY = '1' then
+               RXUSERRDY <= '1';
+            end if;
+            reset_time_out  <= '0';
+            if rxresetdone_s3 = '1' then
+              rx_state        <= DO_PHASE_ALIGNMENT; 
+              reset_time_out  <= '1';
+            end if;          
+
+            if time_out_2ms = '1' and reset_time_out = '0' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+          
+          when DO_PHASE_ALIGNMENT => 
+            --The direct handling of the signals for the Phase Alignment is done outside
+            --this state-machine. 
+            RESET_PHALIGNMENT       <= '0';
+            run_phase_alignment_int <= '1';
+            reset_time_out          <= '0';
+            
+            if PHALIGNMENT_DONE = '1' then
+              rx_state        <= MONITOR_DATA_VALID;
+              reset_time_out  <= '1';
+            end if;
+            
+            if time_out_wait_bypass_s3 = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <=  retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+          
+          when MONITOR_DATA_VALID => 
+              reset_time_out  <= '0';
+
+              if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0')  then
+                 rx_state              <= ASSERT_ALL_RESETS; 
+                 rx_fsm_reset_done_int <= '0';
+              elsif (data_valid_sync = '1') then
+                 rx_state              <= FSM_DONE; 
+                 rx_fsm_reset_done_int <= '0';
+                 reset_time_out        <= '1';
+              end if;
+ 
+         when FSM_DONE =>
+            reset_time_out  <= '0';
+            if data_valid_sync = '0' then
+               rx_fsm_reset_done_int <= '0';
+               reset_time_out        <= '1';
+               rx_state              <= MONITOR_DATA_VALID;
+ 
+            elsif(time_out_1us = '1' and reset_time_out = '0')  then
+               rx_fsm_reset_done_int <= '1';
+            end if;
+
+            if(time_out_adapt = '1') then
+               if(EQ_MODE = "DFE") then
+                  RXDFEAGCHOLD  <=  '1';
+                  RXDFELFHOLD   <=  '1';
+                  RXLPMHFHOLD   <=  '0';
+                  RXLPMLFHOLD   <=  '0';
+               else 
+                  RXDFEAGCHOLD  <=  '0';
+                  RXDFELFHOLD   <=  '0';
+                  RXLPMHFHOLD   <=  '0';
+                  RXLPMLFHOLD   <=  '0';
+               end if;
+            end if;
+           when OTHERS => 
+              rx_state                <= INIT;
+        end case;
+      end if;
+    end if;
+  end process;
+
+end RTL;
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_sync_block.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_sync_block.vhd
new file mode 100644
index 0000000..9ce2535
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_sync_block.vhd
@@ -0,0 +1,194 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 3.5
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename : gtxkintex7fee80_sync_block.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--
+-- Description: Used on signals crossing from one clock domain to
+--              another, this is a flip-flop pair, with both flops
+--              placed together with RLOCs into the same slice.  Thus
+--              the routing delay between the two is minimum to safe-
+--              guard against metastability issues.
+--                     
+--
+-- Module gtxKintex7FEE80_sync_block
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity gtxKintex7FEE80_sync_block is
+  generic (
+    INITIALISE : bit_vector(5 downto 0) := "000000"
+  );
+  port (
+    clk         : in  std_logic;          -- clock to be sync'ed to
+    data_in     : in  std_logic;          -- Data to be 'synced'
+    data_out    : out std_logic           -- synced data
+    );
+
+-- attribute dont_touch : string;
+-- attribute dont_touch    of   gtxKintex7FEE80_sync_block : entity is "yes";
+
+end gtxKintex7FEE80_sync_block;
+
+
+architecture structural of gtxKintex7FEE80_sync_block is
+
+
+  -- Internal Signals
+  signal data_sync1 : std_logic;
+  signal data_sync2 : std_logic;
+  signal data_sync3 : std_logic;
+  signal data_sync4 : std_logic;
+  signal data_sync5 : std_logic;
+
+  -- These attributes will stop timing errors being reported in back annotated
+  -- SDF simulation.
+  attribute ASYNC_REG                       : string;
+  attribute ASYNC_REG of data_sync_reg1    : label is "true";
+  attribute ASYNC_REG of data_sync_reg2    : label is "true";
+  attribute ASYNC_REG of data_sync_reg3    : label is "true";
+  attribute ASYNC_REG of data_sync_reg4    : label is "true";
+  attribute ASYNC_REG of data_sync_reg5    : label is "true";
+  attribute ASYNC_REG of data_sync_reg6    : label is "true";
+
+  -- These attributes will stop XST translating the desired flip-flops into an
+  -- SRL based shift register.
+  attribute shreg_extract                   : string;
+  attribute shreg_extract of data_sync_reg1 : label is "no";
+  attribute shreg_extract of data_sync_reg2 : label is "no";
+  attribute shreg_extract of data_sync_reg3 : label is "no";
+  attribute shreg_extract of data_sync_reg4 : label is "no";
+  attribute shreg_extract of data_sync_reg5 : label is "no";
+  attribute shreg_extract of data_sync_reg6 : label is "no";
+
+  
+begin
+
+  data_sync_reg1 : FD
+  generic map (
+    INIT => INITIALISE(0)
+  )
+  port map (
+    C    => clk,
+    D    => data_in,
+    Q    => data_sync1
+  );
+
+ data_sync_reg2 : FD
+  generic map (
+    INIT => INITIALISE(1)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync1,
+    Q    => data_sync2
+  );
+
+ data_sync_reg3 : FD
+  generic map (
+    INIT => INITIALISE(2)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync2,
+    Q    => data_sync3
+  );
+
+ data_sync_reg4 : FD
+  generic map (
+    INIT => INITIALISE(3)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync3,
+    Q    => data_sync4
+  );
+
+ data_sync_reg5 : FD
+  generic map (
+    INIT => INITIALISE(4)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync4,
+    Q    => data_sync5
+  );  
+
+  data_sync_reg6 : FD
+  generic map (
+    INIT => INITIALISE(5)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync5,
+    Q    => data_out
+  );
+
+
+
+end structural;
+
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_tx_startup_fsm.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_tx_startup_fsm.vhd
new file mode 100644
index 0000000..5ce8c64
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/IPsources/gtxkintex7fee80_tx_startup_fsm.vhd
@@ -0,0 +1,609 @@
+--//////////////////////////////////////////////////////////////////////////////
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename :gtxkintex7fee80_tx_startup_fsm.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module gtxKintex7FEE80_tx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity gtxKintex7FEE80_TX_STARTUP_FSM is
+  Generic(
+           EXAMPLE_SIMULATION       : integer := 0; 
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient              
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           TXUSERCLK                : in  STD_LOGIC;              --TXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;              --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;              --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;              --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the CPLL of the GT
+           TXRESETDONE              : in  STD_LOGIC;      
+           MMCM_LOCK                : in  STD_LOGIC;      
+           GTTXRESET                : out STD_LOGIC;      
+           MMCM_RESET               : out STD_LOGIC:='1';      
+           QPLL_RESET               : out STD_LOGIC:='0';        --Reset QPLL
+           CPLL_RESET               : out STD_LOGIC:='0';        --Reset CPLL
+           TX_FSM_RESET_DONE        : out STD_LOGIC;             --Reset-sequence has sucessfully been finished.
+           TXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC:='0';
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';
+           PHALIGNMENT_DONE         : in  STD_LOGIC;
+           
+           RETRY_COUNTER            : out  STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end gtxKintex7FEE80_TX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+--   are calculated at design-time based on the Generics
+--   
+-- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX
+--   => signal which PLL has been reset
+-- * 
+
+
+
+architecture RTL of gtxKintex7FEE80_TX_STARTUP_FSM is
+
+  component gtxKintex7FEE80_sync_block
+   generic (
+     INITIALISE : bit_vector(5 downto 0) := "000000"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+  type tx_rst_fsm_type is(
+    INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET,
+    WAIT_FOR_TXOUTCLK, RELEASE_MMCM_RESET, WAIT_FOR_TXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+    RESET_FSM_DONE);
+    
+  signal tx_state : tx_rst_fsm_type := INIT;
+
+  constant MMCM_LOCK_CNT_MAX    : integer := 256;
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+    
+  constant WAIT_TIMEOUT_2ms     : integer := 2000000 / STABLE_CLOCK_PERIOD;--  2 ms time-out
+  constant WAIT_TLOCK_MAX       : integer :=  100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_TIMEOUT_500us   : integer :=  500000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_1us_cycles      : integer :=  1000 / STABLE_CLOCK_PERIOD;--1 us time-out
+  constant WAIT_1us             : integer := WAIT_1us_cycles+ 10;                    -- 1us plus some additional margin
+    
+  signal init_wait_count        : integer range 0 to WAIT_MAX:=0;
+  signal init_wait_done         : std_logic := '0';
+  signal pll_reset_asserted     : std_logic := '0';
+
+  signal tx_fsm_reset_done_int     : std_logic := '0';
+  signal tx_fsm_reset_done_int_s2  : std_logic := '0';
+  signal tx_fsm_reset_done_int_s3  : std_logic := '0';
+   
+  signal txresetdone_s2         : std_logic := '0'; 
+  signal txresetdone_s3         : std_logic := '0'; 
+
+  constant MAX_RETRIES          : integer := 2**RETRY_COUNTER_BITWIDTH-1; 
+  signal retry_counter_int      : integer range 0 to MAX_RETRIES;  
+  signal time_out_counter       : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+    
+  signal reset_time_out         : std_logic := '0';
+  signal time_out_2ms           : std_logic := '0';--\Flags that the various time-out points 
+  signal time_tlock_max         : std_logic := '0';--|have been reached.
+  signal time_out_500us         : std_logic := '0';--/
+    
+  signal mmcm_lock_count        : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+  signal mmcm_lock_int          : std_logic := '0';
+  signal mmcm_lock_i            : std_logic := '0';
+  signal mmcm_lock_reclocked    : std_logic := '0';
+    
+  signal run_phase_alignment_int    : std_logic := '0';
+  signal run_phase_alignment_int_s2 : std_logic := '0';
+  signal run_phase_alignment_int_s3 : std_logic := '0';
+  constant MAX_WAIT_BYPASS      : integer := 45824; --110000 TXUSRCLK cycles is the max time for Multi lane designs
+ 
+  constant WAIT_TIME_MAX    : integer := 100 ; --10 us time-out
+
+  signal wait_bypass_count      : integer range 0 to MAX_WAIT_BYPASS-1;
+  signal time_out_wait_bypass   : std_logic := '0';
+  signal time_out_wait_bypass_s2   : std_logic := '0';
+  signal time_out_wait_bypass_s3   : std_logic := '0';
+  signal txuserrdy_i   : std_logic := '0';
+  signal refclk_lost            : std_logic;
+  signal gttxreset_i            : std_logic := '0';
+  signal txpmaresetdone_i            : std_logic := '0';
+  signal txpmaresetdone_sync            : std_logic ;
+
+  signal      cplllock_sync: std_logic := '0';
+  signal      qplllock_sync: std_logic := '0';
+  signal      cplllock_prev: std_logic := '0';
+  signal      qplllock_prev: std_logic := '0';
+  signal      cplllock_ris_edge: std_logic := '0';
+  signal      qplllock_ris_edge: std_logic := '0';
+ signal      wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+  signal      wait_time_done :std_logic;
+ 
+begin
+  --Alias section, signals used within this module mapped to output ports:
+  RETRY_COUNTER     <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+  RUN_PHALIGNMENT   <= run_phase_alignment_int;
+  TX_FSM_RESET_DONE <= tx_fsm_reset_done_int;    
+  GTTXRESET <= gttxreset_i;
+
+  process(STABLE_CLOCK,SOFT_RESET)
+  begin
+    if (SOFT_RESET = '1') then
+        init_wait_done <= '0';
+        init_wait_count <= 0 ;
+    elsif rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+  timeouts:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- One common large counter for generating three time-out signals.
+      -- Intermediate time-outs are derived from calculated values, based
+      -- on the period of the provided clock.
+      if reset_time_out = '1' then
+        time_out_counter  <= 0;
+        time_out_2ms      <= '0';
+        time_tlock_max    <= '0';
+        time_out_500us    <= '0';
+      else
+        if time_out_counter = WAIT_TIMEOUT_2ms then
+          time_out_2ms <= '1';
+        else
+          time_out_counter <= time_out_counter + 1;
+        end if;
+        
+        if time_out_counter = WAIT_TLOCK_MAX then
+          time_tlock_max <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_500us then
+          time_out_500us <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  mmcm_lock_wait:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if mmcm_lock_i = '0' then
+        mmcm_lock_count <= 0;
+        mmcm_lock_reclocked   <= '0';
+      else 
+        if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+          mmcm_lock_count <= mmcm_lock_count + 1;
+        else
+          mmcm_lock_reclocked <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+ 
+ 
+
+  -- Clock Domain Crossing
+
+  sync_run_phase_alignment_int : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  TXUSERCLK,
+            data_in         =>  run_phase_alignment_int,
+            data_out        =>  run_phase_alignment_int_s2 
+         );
+
+  sync_tx_fsm_reset_done_int : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  TXUSERCLK,
+            data_in         =>  tx_fsm_reset_done_int,
+            data_out        =>  tx_fsm_reset_done_int_s2 
+         );
+
+  process(TXUSERCLK)
+  begin
+    if rising_edge(TXUSERCLK) then
+      run_phase_alignment_int_s3   <=  run_phase_alignment_int_s2;
+
+      tx_fsm_reset_done_int_s3     <=  tx_fsm_reset_done_int_s2;
+    end if;
+  end process;
+
+ sync_TXRESETDONE : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  TXRESETDONE,
+            data_out        =>  txresetdone_s2 
+         );
+
+  sync_time_out_wait_bypass : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  time_out_wait_bypass,
+            data_out        =>  time_out_wait_bypass_s2 
+         );
+
+  sync_mmcm_lock_reclocked : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  MMCM_LOCK,
+            data_out        =>  mmcm_lock_i 
+         );
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+       txresetdone_s3     <= txresetdone_s2;
+
+       time_out_wait_bypass_s3 <=  time_out_wait_bypass_s2;
+
+       cplllock_prev           <=  cplllock_sync;
+       qplllock_prev           <=  qplllock_sync;
+    end if;
+  end process;
+
+ sync_CPLLLOCK : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  CPLLLOCK,
+            data_out        =>  cplllock_sync
+         );
+
+ sync_QPLLLOCK : gtxKintex7FEE80_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  QPLLLOCK,
+            data_out        =>  qplllock_sync
+         );
+
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       cplllock_ris_edge <= '0';
+     elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+       cplllock_ris_edge <= '1';
+     elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+       cplllock_ris_edge <= cplllock_ris_edge;
+     else 
+       cplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       qplllock_ris_edge <= '0';
+     elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+       qplllock_ris_edge <= '1';
+     elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+       qplllock_ris_edge <= qplllock_ris_edge;
+     else 
+       qplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+
+
+  timeout_buffer_bypass:process(TXUSERCLK)
+  begin
+    if rising_edge(TXUSERCLK) then
+      if run_phase_alignment_int_s3 = '0' then
+        wait_bypass_count     <= 0;
+        time_out_wait_bypass  <= '0';
+      elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0')  then
+        if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+          time_out_wait_bypass <= '1';
+        else
+          wait_bypass_count <= wait_bypass_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+   refclk_lost <= '1' when ((TX_QPLL_USED and QPLLREFCLKLOST='1') or (not TX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+  timeout_max:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+        if((tx_state = ASSERT_ALL_RESETS) or
+          (tx_state = RELEASE_PLL_RESET) or 
+          (tx_state = RELEASE_MMCM_RESET)) then
+            wait_time_cnt <= WAIT_TIME_MAX;
+        elsif (wait_time_cnt > 0 ) then
+            wait_time_cnt <= wait_time_cnt - 1;
+          end if;
+       end if;
+   end process;
+
+  wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+
+  --FSM for resetting the GTX/GTH/GTP in the 7-series. 
+  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  --
+  -- Following steps are performed:
+  -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in 
+  --    answer-record 43482
+  -- 2) Assert all resets on the GT and on an MMCM potentially connected. 
+  --    After that wait until a reference-clock has been detected.
+  -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+  -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+  --    Also signal to the RX-side which PLL has been reset.
+  -- 5) Wait for the RESET_DONE-signal from the GT.
+  -- 6) Signal to start the phase-alignment procedure and wait for it to 
+  --    finish.
+  -- 7) Reset-sequence has successfully run through. Signal this to the 
+  --    rest of the design by asserting TX_FSM_RESET_DONE.
+  
+  reset_fsm:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1') then
+      --if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+        tx_state                <= INIT;
+        TXUSERRDY               <= '0';
+        gttxreset_i               <= '0';
+        MMCM_RESET              <= '0';
+        tx_fsm_reset_done_int   <= '0';
+        QPLL_RESET              <= '0';
+        CPLL_RESET              <= '0';
+        pll_reset_asserted      <= '0';
+        reset_time_out          <= '0';
+        retry_counter_int       <=  0;
+        run_phase_alignment_int <= '0';
+        RESET_PHALIGNMENT       <= '1';
+      else
+        
+        case tx_state is
+          when INIT => 
+            --Initial state after configuration. This state will be left after
+            --approx. 500 ns and not be re-entered. 
+            if init_wait_done = '1' then
+              tx_state        <= ASSERT_ALL_RESETS;
+              reset_time_out  <= '1';
+            end if;
+            
+          when ASSERT_ALL_RESETS => 
+            --This is the state into which the FSM will always jump back if any
+            --time-outs will occur. 
+            --The number of retries is reported on the output RETRY_COUNTER. In 
+            --case the transceiver never comes up for some reason, this machine 
+            --will still continue its best and rerun until the FPGA is turned off
+            --or the transceivers come up correctly.
+            if TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                QPLL_RESET          <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                QPLL_RESET          <= '0';
+              end if;
+            else
+              if pll_reset_asserted = '0' then
+                CPLL_RESET <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                CPLL_RESET          <= '0';
+              end if;  
+            end if;
+            TXUSERRDY               <= '0';
+            gttxreset_i               <= '1';
+            MMCM_RESET              <= '1';
+            reset_time_out          <= '1';
+            run_phase_alignment_int <= '0';     
+            RESET_PHALIGNMENT       <= '1';
+
+            if (TX_QPLL_USED  and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+               (not TX_QPLL_USED  and (cplllock_sync = '0') and pll_reset_asserted = '1') then
+              tx_state  <= WAIT_FOR_PLL_LOCK;
+           end if;    
+       
+           when WAIT_FOR_PLL_LOCK =>
+              if(wait_time_done = '1') then
+                 tx_state        <=  RELEASE_PLL_RESET;  
+           end if;    
+         
+          when RELEASE_PLL_RESET => 
+            --PLL-Reset of the GTX gets released and the time-out counter
+            --starts running.
+            pll_reset_asserted  <= '0';
+
+            if (TX_QPLL_USED and (qplllock_sync = '1')) or
+               (not TX_QPLL_USED and (cplllock_sync = '1')) then
+              tx_state  <= WAIT_FOR_TXOUTCLK;
+              reset_time_out  <= '1';
+            end if;
+            
+            if time_out_2ms = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+
+           when WAIT_FOR_TXOUTCLK =>
+            gttxreset_i <= '0';
+              if(wait_time_done = '1') then
+               tx_state <=  RELEASE_MMCM_RESET;  
+           end if;    
+
+          when RELEASE_MMCM_RESET => 
+            --Release of the MMCM-reset. Waiting for the MMCM to lock.
+            MMCM_RESET <= '0';
+            reset_time_out  <= '0';
+            if mmcm_lock_reclocked = '1' then
+              tx_state <= WAIT_FOR_TXUSRCLK;
+              reset_time_out  <= '1';
+            end if;          
+            
+            if (time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0') then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+
+           when WAIT_FOR_TXUSRCLK =>
+              if(wait_time_done = '1') then
+               tx_state <=  WAIT_RESET_DONE; 
+           end if;    
+ 
+          when WAIT_RESET_DONE => 
+            TXUSERRDY <= '1';
+            reset_time_out  <= '0';
+            if txresetdone_s3 = '1' then              
+              tx_state      <= DO_PHASE_ALIGNMENT;               
+              reset_time_out  <= '1';
+            end if;          
+
+            if (time_out_500us = '1' and reset_time_out = '0') then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;                    
+          
+          when DO_PHASE_ALIGNMENT => 
+            --The direct handling of the signals for the Phase Alignment is done outside
+            --this state-machine. 
+            RESET_PHALIGNMENT       <= '0';
+            run_phase_alignment_int <= '1';
+            reset_time_out          <= '0';
+            
+            if PHALIGNMENT_DONE = '1' then
+              tx_state        <= RESET_FSM_DONE;
+            end if;
+            
+            if time_out_wait_bypass_s3 = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <=  retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+          
+          when RESET_FSM_DONE => 
+            reset_time_out        <= '1';
+            tx_fsm_reset_done_int <= '1';
+
+          when OTHERS =>
+            tx_state              <= INIT;
+          
+        end case;
+      end if;
+    end if;
+  end process; 
+
+end RTL;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80/gtxKintex7FEE80.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80/gtxKintex7FEE80.xci
new file mode 100644
index 0000000..49de6c9
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80/gtxKintex7FEE80.xci
@@ -0,0 +1,1239 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>gtxKintex7FEE80</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gtwizard" spirit:version="3.5"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">gtxKintex7FEE80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_refclk">REFCLK0_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK0_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">gtxKintex7FEE80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK0_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK0_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_tx_pll" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_rx_pll" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_encoding" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_decoding" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_drp_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txbuf_en" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txoutclk_source" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxbuf_en" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxusrclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_comma_preset" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_align_comma_word" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxslide" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_dfe_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxslide_mode" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80_top.ucf b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80_exdes.xdc
similarity index 60%
rename from FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80_top.ucf
rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80_exdes.xdc
index 09fb567..9a528fe 100644
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80_top.ucf
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxKintex7FEE80_exdes.xdc
@@ -1,96 +1,104 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : gtxVirtex6FEE80_top.ucf
-## /___/   /\     
-## \   \  /  \ 
-##  \___\/\___\
-##
-##
-## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-## Device:  xc6vlx130t
-## Package: ff484
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-################################## Clock Constraints ##########################
-
-NET "q3_clk0_refclk_i" TNM_NET = "q3_clk0_refclk_i";
-TIMESPEC "TS_q3_clk0_refclk_i" = PERIOD "q3_clk0_refclk_i" 12.5;
-
-
-
-# User Clock Constraints
-NET "gtx0_txusrclk2_i" TNM_NET = "gtx0_txusrclk2_i";
-TIMESPEC "TS_gtx0_txusrclk2_i" = PERIOD "gtx0_txusrclk2_i" 5.0;
-
-NET "gtx0_rxusrclk2_i" TNM_NET = "gtx0_rxusrclk2_i";
-TIMESPEC "TS_gtx0_rxusrclk2_i" = PERIOD "gtx0_rxusrclk2_i" 5.0;
-
-
-
-#################### locs for top level ports (ML623 Board) ###################
-
-
-
-####################### GTX reference clock constraints #######################
-NET Q3_CLK0_MGTREFCLK_PAD_N_IN  LOC=L3;
-NET Q3_CLK0_MGTREFCLK_PAD_P_IN  LOC=L4;
-
-
-################################# mgt wrapper constraints #####################
-
-##---------- Set placement for gtx0_gtx_wrapper_i/GTX_DUAL ------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i LOC=GTXE1_X0Y12;
-
-
-
+################################################################################
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor: Xilinx
+## \   \   \/     Version : 3.5
+##  \   \         Application : 7 Series FPGAs Transceivers Wizard
+##  /   /         Filename : gtxKintex7FEE80_exdes.xdc
+## /___/   /\     
+## \   \  /  \ 
+##  \___\/\___\
+##
+##
+## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
+## Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+##
+## Device:  xc7k160t
+## Package: fbg484
+##
+## (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+## 
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+
+
+################################## Clock Constraints ##########################
+
+
+####################### GT reference clock constraints #########################
+ 
+
+    create_clock -period 12.5 [get_ports Q0_CLK0_GTREFCLK_PAD_P_IN]
+
+
+
+
+
+create_clock -name drpclk_in_i -period 12.5 [get_ports DRP_CLK_IN_P]
+
+
+# User Clock Constraints
+
+
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}]
+################################# RefClk Location constraints #####################
+set_property LOC D5 [get_ports  Q0_CLK0_GTREFCLK_PAD_N_IN ] 
+set_property LOC D6 [get_ports  Q0_CLK0_GTREFCLK_PAD_P_IN ]
+
+## LOC constrain for DRP_CLK_P/N 
+## set_property LOC C25 [get_ports  DRP_CLK_IN_P]
+## set_property LOC B25 [get_ports  DRP_CLK_IN_N]
+ 
+################################# mgt wrapper constraints #####################
+
+##---------- Set placement for gt0_gtx_wrapper_i/GTXE2_CHANNEL ------
+set_property LOC GTXE2_CHANNEL_X0Y0 [get_cells gtxKintex7FEE80_support_i/gtxKintex7FEE80_init_i/U0/gtxKintex7FEE80_i/gt0_gtxKintex7FEE80_i/gtxe2_i]
+
+##---------- Set ASYNC_REG for flop which have async input ----------
+##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt0_frame_gen*system_reset_r_reg}]
+##set_property ASYNC_REG TRUE [get_cells -hier -filter {name=~*gt0_frame_check*system_reset_r_reg}]
+
+##---------- Set False Path from one clock to other ----------
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_clock_module.vhd
similarity index 64%
rename from FEE_ADC32board/project/ipcore_dir/clockmodule80M.vhd
rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_clock_module.vhd
index 43be5a5..6ef9b3e 100644
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.vhd
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_clock_module.vhd
@@ -1,199 +1,245 @@
--- file: clockmodule80M.vhd
--- 
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- None
---
-------------------------------------------------------------------------------
--- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
--- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
-------------------------------------------------------------------------------
--- CLK_OUT1____99.999______0.000______50.0______144.151____174.045
---
-------------------------------------------------------------------------------
--- "Input Clock   Freq (MHz)    Input Jitter (UI)"
-------------------------------------------------------------------------------
--- __primary__________155.52____________0.010
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-use ieee.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity clockmodule80M is
-port
- (-- Clock in ports
-  CLK_IN1           : in     std_logic;
-  -- Clock out ports
-  CLK_OUT1          : out    std_logic;
-  -- Status and control signals
-  LOCKED            : out    std_logic
- );
-end clockmodule80M;
-
-architecture xilinx of clockmodule80M is
-  attribute CORE_GENERATION_INFO : string;
-  attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule80M,clk_wiz_v3_6,{component_name=clockmodule80M,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=6.430,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-  -- Input clock buffering / unused connectors
-  signal clkin1      : std_logic;
-  -- Output clock buffering / unused connectors
-  signal clkfbout         : std_logic;
-  signal clkfbout_buf     : std_logic;
-  signal clkfboutb_unused : std_logic;
-  signal clkout0          : std_logic;
-  signal clkout0b_unused  : std_logic;
-  signal clkout1_unused   : std_logic;
-  signal clkout1b_unused  : std_logic;
-  signal clkout2_unused   : std_logic;
-  signal clkout2b_unused  : std_logic;
-  signal clkout3_unused   : std_logic;
-  signal clkout3b_unused  : std_logic;
-  signal clkout4_unused   : std_logic;
-  signal clkout5_unused   : std_logic;
-  signal clkout6_unused   : std_logic;
-  -- Dynamic programming unused signals
-  signal do_unused        : std_logic_vector(15 downto 0);
-  signal drdy_unused      : std_logic;
-  -- Dynamic phase shift unused signals
-  signal psdone_unused    : std_logic;
-  -- Unused status signals
-  signal clkfbstopped_unused : std_logic;
-  signal clkinstopped_unused : std_logic;
-begin
-
-
-  -- Input buffering
-  --------------------------------------
-  clkin1 <= CLK_IN1;
-
-
-  -- Clocking primitive
-  --------------------------------------
-  -- Instantiation of the MMCM primitive
-  --    * Unused inputs are tied off
-  --    * Unused outputs are labeled unused
-  mmcm_adv_inst : MMCM_ADV
-  generic map
-   (BANDWIDTH            => "OPTIMIZED",
-    CLKOUT4_CASCADE      => FALSE,
-    CLOCK_HOLD           => FALSE,
-    COMPENSATION         => "ZHOLD",
-    STARTUP_WAIT         => FALSE,
-    DIVCLK_DIVIDE        => 5,
-    CLKFBOUT_MULT_F      => 43.000,
-    CLKFBOUT_PHASE       => 0.000,
-    CLKFBOUT_USE_FINE_PS => FALSE,
-    CLKOUT0_DIVIDE_F     => 13.375,
-    CLKOUT0_PHASE        => 0.000,
-    CLKOUT0_DUTY_CYCLE   => 0.500,
-    CLKOUT0_USE_FINE_PS  => FALSE,
-    CLKIN1_PERIOD        => 6.430,
-    REF_JITTER1          => 0.010)
-  port map
-    -- Output clocks
-   (CLKFBOUT            => clkfbout,
-    CLKFBOUTB           => clkfboutb_unused,
-    CLKOUT0             => clkout0,
-    CLKOUT0B            => clkout0b_unused,
-    CLKOUT1             => clkout1_unused,
-    CLKOUT1B            => clkout1b_unused,
-    CLKOUT2             => clkout2_unused,
-    CLKOUT2B            => clkout2b_unused,
-    CLKOUT3             => clkout3_unused,
-    CLKOUT3B            => clkout3b_unused,
-    CLKOUT4             => clkout4_unused,
-    CLKOUT5             => clkout5_unused,
-    CLKOUT6             => clkout6_unused,
-    -- Input clock control
-    CLKFBIN             => clkfbout_buf,
-    CLKIN1              => clkin1,
-    CLKIN2              => '0',
-    -- Tied to always select the primary input clock
-    CLKINSEL            => '1',
-    -- Ports for dynamic reconfiguration
-    DADDR               => (others => '0'),
-    DCLK                => '0',
-    DEN                 => '0',
-    DI                  => (others => '0'),
-    DO                  => do_unused,
-    DRDY                => drdy_unused,
-    DWE                 => '0',
-    -- Ports for dynamic phase shift
-    PSCLK               => '0',
-    PSEN                => '0',
-    PSINCDEC            => '0',
-    PSDONE              => psdone_unused,
-    -- Other control and status signals
-    LOCKED              => LOCKED,
-    CLKINSTOPPED        => clkinstopped_unused,
-    CLKFBSTOPPED        => clkfbstopped_unused,
-    PWRDWN              => '0',
-    RST                 => '0');
-
-  -- Output buffering
-  -------------------------------------
-  clkf_buf : BUFG
-  port map
-   (O => clkfbout_buf,
-    I => clkfbout);
-
-
-  clkout1_buf : BUFG
-  port map
-   (O   => CLK_OUT1,
-    I   => clkout0);
-
-
-
-end xilinx;
+-- file: clk_wiz_v2_1.vhd
+-- 
+-- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+-- Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1   100.000      0.000    50.000      130.958     98.575
+-- CLK_OUT2   200.000      0.000    50.000      114.829     98.575
+--
+------------------------------------------------------------------------------
+-- Input Clock   Input Freq (MHz)   Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary         100.000            0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity gtxKintex7FEE80_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end gtxKintex7FEE80_CLOCK_MODULE;
+
+architecture xilinx of gtxKintex7FEE80_CLOCK_MODULE is
+  attribute X_CORE_INFO : string;
+  attribute X_CORE_INFO of xilinx : architecture is "gtxKintex7FEE80,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfbout_buf     : std_logic;
+  signal clkfboutb_unused : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout0b_unused  : std_logic;
+  signal clkout1          : std_logic;
+  signal clkout1b_unused  : std_logic;
+  signal clkout2          : std_logic;
+  signal clkout2b_unused  : std_logic;
+  signal clkout3          : std_logic;
+  signal clkout3b_unused  : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  signal clkout6_unused   : std_logic;
+  -- Dynamic programming unused signals
+  signal do_unused        : std_logic_vector(15 downto 0);
+  signal drdy_unused      : std_logic;
+  -- Dynamic phase shift unused signals
+  signal psdone_unused    : std_logic;
+  -- Unused status signals
+  signal clkfbstopped_unused : std_logic;
+  signal clkinstopped_unused : std_logic;
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : BUFG
+  port map
+   (O => clkin1,
+    I => CLK_IN);
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the MMCM primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+
+  mmcm_adv_inst : MMCME2_ADV
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLKOUT4_CASCADE      => FALSE,
+    COMPENSATION         => "ZHOLD",
+    STARTUP_WAIT         => FALSE,
+    DIVCLK_DIVIDE        => DIVIDE,
+    CLKFBOUT_MULT_F      => MULT,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKFBOUT_USE_FINE_PS => FALSE,
+    CLKOUT0_DIVIDE_F     => OUT0_DIVIDE,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT0_USE_FINE_PS  => FALSE,
+    CLKIN1_PERIOD        => CLK_PERIOD,
+    CLKOUT1_DIVIDE       => OUT1_DIVIDE,
+    CLKOUT1_PHASE        => 0.000,
+    CLKOUT1_DUTY_CYCLE   => 0.500,
+    CLKOUT1_USE_FINE_PS  => FALSE,
+    CLKOUT2_DIVIDE       => OUT2_DIVIDE,
+    CLKOUT2_PHASE        => 0.000,
+    CLKOUT2_DUTY_CYCLE   => 0.500,
+    CLKOUT2_USE_FINE_PS  => FALSE,
+    CLKOUT3_DIVIDE       => OUT3_DIVIDE,
+    CLKOUT3_PHASE        => 0.000,
+    CLKOUT3_DUTY_CYCLE   => 0.500,
+    CLKOUT3_USE_FINE_PS  => FALSE,
+    REF_JITTER1          => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKFBOUTB           => clkfboutb_unused,
+    CLKOUT0             => clkout0,
+    CLKOUT0B            => clkout0b_unused,
+    CLKOUT1             => clkout1,
+    CLKOUT1B            => clkout1b_unused,
+    CLKOUT2             => clkout2,
+    CLKOUT2B            => clkout2b_unused,
+    CLKOUT3             => clkout3,
+    CLKOUT3B            => clkout3b_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    CLKOUT6             => clkout6_unused,
+    -- Input clock control
+    CLKFBIN             => clkfbout,
+    CLKIN1              => clkin1,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => do_unused,
+    DRDY                => drdy_unused,
+    DWE                 => '0',
+    -- Ports for dynamic phase shift
+    PSCLK               => '0',
+    PSEN                => '0',
+    PSINCDEC            => '0',
+    PSDONE              => psdone_unused,
+    -- Other control and status signals
+    LOCKED              => MMCM_LOCKED_OUT,
+    CLKINSTOPPED        => clkinstopped_unused,
+    CLKFBSTOPPED        => clkfbstopped_unused,
+    PWRDWN              => '0',
+    RST                 => MMCM_RESET_IN);
+
+  -- Output buffering
+  -------------------------------------
+  --clkf_buf : BUFG
+  --port map
+  -- (O => clkfbout_buf,
+  --  I => clkfbout);
+
+
+  clkout0_buf : BUFG
+  port map
+   (O   => CLK0_OUT,
+    I   => clkout0);
+
+  clkout1_buf : BUFG
+  port map
+   (O   => CLK1_OUT,
+    I   => clkout1);
+
+--  clkout2_buf : BUFG
+--  port map
+--   (O   => CLK2_OUT,
+--    I   => clkout2);
+--
+--  clkout3_buf : BUFG
+--  port map
+--   (O   => CLK3_OUT,
+--    I   => clkout3);
+
+CLK2_OUT <= '0';
+CLK3_OUT <= '0';
+end xilinx;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common.vhd
new file mode 100644
index 0000000..0857143
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common.vhd
@@ -0,0 +1,247 @@
+---------------------------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtxkintex7fee80_common.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module gtxKintex7FEE80_common 
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity gtxKintex7FEE80_common is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "TRUE";        -- Set to "true" to speed up sim reset 
+    SIM_QPLLREFCLK_SEL              : bit_vector :=  "001"
+);
+port
+(
+    QPLLREFCLKSEL_IN  : in std_logic_vector(2 downto 0);
+    GTREFCLK1_IN      : in std_logic;
+    GTREFCLK0_IN : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+);
+
+end gtxKintex7FEE80_common;
+    
+architecture RTL of gtxKintex7FEE80_common is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "gtxKintex7FEE80_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+    impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return "0000100000";
+       elsif (qpllfbdiv_top = 20) then
+         return "0000110000" ;
+       elsif (qpllfbdiv_top = 32) then
+         return "0001100000" ;
+       elsif (qpllfbdiv_top = 40) then
+         return "0010000000" ;
+       elsif (qpllfbdiv_top = 64) then
+         return "0011100000" ;
+       elsif (qpllfbdiv_top = 66) then
+         return "0101000000" ;
+       elsif (qpllfbdiv_top = 80) then
+         return "0100100000" ;
+       elsif (qpllfbdiv_top = 100) then
+         return "0101110000" ;
+       else 
+         return "0000000000" ;
+       end if;
+    end function;
+
+    impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return '1';
+       elsif (qpllfbdiv_top = 20) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 32) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 40) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 64) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 66) then
+         return '0' ;
+       elsif (qpllfbdiv_top = 80) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 100) then
+         return '1' ;
+       else 
+         return '1' ;
+       end if;
+    end function;
+
+    constant   QPLL_FBDIV_TOP   : integer  := 16;
+    constant   QPLL_FBDIV_IN    :   bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+    constant   QPLL_FBDIV_RATIO :   bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal  tied_to_vcc_vec_i               :   std_logic_vector(63 downto 0);
+
+begin
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    tied_to_vcc_vec_i(63 downto 0)      <= (others => '1');
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTXE2_COMMON____________________________________
+
+    gtxe2_common_i : GTXE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_QPLLREFCLK_SEL   => (SIM_QPLLREFCLK_SEL),
+            SIM_VERSION          => "4.0",
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000040000001000"),
+        COMMON_CFG                              =>     (x"00000000"),
+        QPLL_CFG                                =>     (x"06801C1"),
+        QPLL_CLKOUT_CFG                         =>     ("0000"),
+        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
+        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
+        QPLL_CP                                 =>     ("0000011111"),
+        QPLL_CP_MONITOR_EN                      =>     ('0'),
+        QPLL_DMONITOR_SEL                       =>     ('0'),
+        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
+        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
+        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
+        QPLL_INIT_CFG                           =>     (x"000006"),
+        QPLL_LOCK_CFG                           =>     (x"21E8"),
+        QPLL_LPF                                =>     ("1111"),
+        QPLL_REFCLK_DIV                         =>     (1)
+
+        
+    )
+    port map
+    (
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      GTREFCLK1_IN,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ------------------------- Common Block -  QPLL Ports -----------------------
+        QPLLDMONITOR                    =>      open,
+        ----------------------- Common Block - Clocking Ports ----------------------
+        QPLLOUTCLK                      =>      QPLLOUTCLK_OUT,
+        QPLLOUTREFCLK                   =>      QPLLOUTREFCLK_OUT,
+        REFCLKOUTMONITOR                =>      open,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        QPLLFBCLKLOST                   =>      open,
+        QPLLLOCK                        =>      QPLLLOCK_OUT,
+        QPLLLOCKDETCLK                  =>      QPLLLOCKDETCLK_IN,
+        QPLLLOCKEN                      =>      tied_to_vcc_i,
+        QPLLOUTRESET                    =>      tied_to_ground_i,
+        QPLLPD                          =>      tied_to_vcc_i,
+        QPLLREFCLKLOST                  =>      QPLLREFCLKLOST_OUT,
+        QPLLREFCLKSEL                   =>      QPLLREFCLKSEL_IN,
+        QPLLRESET                       =>      QPLLRESET_IN,
+        QPLLRSVD1                       =>      "0000000000000000",
+        QPLLRSVD2                       =>      "11111",
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "11111",
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+end RTL;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common_reset.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common_reset.vhd
new file mode 100644
index 0000000..65ebb28
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_common_reset.vhd
@@ -0,0 +1,154 @@
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtxkintex7fee80_common_reset.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module gtxKintex7FEE80_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity gtxKintex7FEE80_common_reset is 
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic:= '0'  --Reset QPLL
+   );
+end gtxKintex7FEE80_common_reset;
+
+architecture RTL of gtxKintex7FEE80_common_reset is
+
+
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+
+
+  signal init_wait_count  : std_logic_vector(7 downto 0) :=(others => '0');
+  signal init_wait_done   : std_logic :='0';
+  signal common_reset_asserted   : std_logic :='0';
+  signal common_reset_i   : std_logic ;
+
+  type rst_type is(
+    INIT, ASSERT_COMMON_RESET);
+    
+  signal state : rst_type := INIT;
+
+begin
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1') then
+        state                <= INIT;
+        common_reset_asserted   <= '0';
+        COMMON_RESET   <= '0';
+      else
+        
+        case state is
+          when INIT => 
+            if init_wait_done = '1' then
+              state        <= ASSERT_COMMON_RESET;
+            end if;
+            
+          when ASSERT_COMMON_RESET =>
+             if common_reset_asserted = '0' then
+                COMMON_RESET          <= '1';
+                common_reset_asserted  <= '1';
+              else
+                COMMON_RESET          <= '0';
+              end if;
+           when OTHERS =>
+            state   <= INIT;
+         end case;
+       end if;
+    end if;
+  end process;
+ 
+
+end RTL; 
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_gt_usrclk_source.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_gt_usrclk_source.vhd
new file mode 100644
index 0000000..63414e5
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_gt_usrclk_source.vhd
@@ -0,0 +1,206 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtxkintex7fee80_gt_usrclk_source.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+-- Module gtxKintex7FEE80_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity gtxKintex7FEE80_GT_USRCLK_SOURCE is
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXUSRCLKX2_OUT           : out std_logic; --// Modified
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_TXCLK_LOCK_OUT           : out std_logic;
+    GT0_TX_MMCM_RESET_IN         : in std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    Q0_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q0_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q0_CLK0_GTREFCLK_OUT                    : out  std_logic
+);
+
+
+end gtxKintex7FEE80_GT_USRCLK_SOURCE;
+
+architecture RTL of gtxKintex7FEE80_GT_USRCLK_SOURCE is
+
+component GTXKINTEX7FEE80_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+    signal   tied_to_ground_i     :   std_logic;
+    signal   tied_to_vcc_i        :   std_logic;
+ 
+    signal   gt0_txoutclk_i :   std_logic;
+    signal   gt0_rxoutclk_i :   std_logic;
+
+    attribute syn_noclockbuf : boolean;
+    signal   q0_clk0_gtrefclk :   std_logic;
+    attribute syn_noclockbuf of q0_clk0_gtrefclk : signal is true;
+
+    signal  gt0_txusrclk_i                  : std_logic;
+    signal  gt0_rxusrclk_i                  : std_logic;
+    signal  txoutclk_mmcm0_locked_i         : std_logic;
+    signal  txoutclk_mmcm0_reset_i          : std_logic;
+    signal  gt0_txoutclk_to_mmcm_i          : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+    --  Static signal Assigments    
+    tied_to_ground_i         <= '0';
+    tied_to_vcc_i            <= '1';
+    gt0_txoutclk_i                               <= GT0_TXOUTCLK_IN;
+    gt0_rxoutclk_i                               <= GT0_RXOUTCLK_IN;
+
+    Q0_CLK0_GTREFCLK_OUT                         <= q0_clk0_gtrefclk;
+
+    --IBUFDS_GTE2
+    ibufds_instq0_clk0 : IBUFDS_GTE2  
+    port map
+    (
+        O               => 	q0_clk0_gtrefclk,
+        ODIV2           =>    open,
+        CEB             => 	tied_to_ground_i,
+        I               => 	Q0_CLK0_GTREFCLK_PAD_P_IN,
+        IB              => 	Q0_CLK0_GTREFCLK_PAD_N_IN
+    );
+
+
+    
+    -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+    -- for improved jitter performance, and to avoid consuming an additional BUFG
+    txoutclk_mmcm0_reset_i                       <= GT0_TX_MMCM_RESET_IN;
+    txoutclk_mmcm0_i : gtxKintex7FEE80_CLOCK_MODULE
+    generic map
+    (
+        MULT                            =>      40.0,  --// 35.0, Modified
+        DIVIDE                          =>      4,
+        CLK_PERIOD                      =>      12.5,
+        OUT0_DIVIDE                     =>      8.0,  --// 7.0 Modified 
+        OUT1_DIVIDE                     =>      4,    --// 1 Modified 
+        OUT2_DIVIDE                     =>      1,
+        OUT3_DIVIDE                     =>      1
+    )
+    port map
+    (
+        CLK0_OUT                        =>      gt0_txusrclk_i,
+        CLK1_OUT                        =>      GT0_TXUSRCLKX2_OUT, --// Modified
+        CLK2_OUT                        =>      open,
+        CLK3_OUT                        =>      open,
+        CLK_IN                          =>      gt0_txoutclk_i,
+        MMCM_LOCKED_OUT                 =>      txoutclk_mmcm0_locked_i,
+        MMCM_RESET_IN                   =>      txoutclk_mmcm0_reset_i
+    );
+
+
+    rxoutclk_bufg1_i : BUFG
+    port map
+    (
+        I                               =>      gt0_rxoutclk_i,
+        O                               =>      gt0_rxusrclk_i
+    );
+
+
+
+ 
+GT0_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT0_TXCLK_LOCK_OUT                           <= txoutclk_mmcm0_locked_i;
+GT0_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+end RTL;
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_support.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_support.vhd
new file mode 100644
index 0000000..0ee8e9d
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/gtx/ip_vivado/gtxkintex7fee80_support.vhd
@@ -0,0 +1,663 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtxkintex7fee80_support.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module gtxKintex7FEE80_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity gtxKintex7FEE80_support is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 12  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q0_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q0_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_OUT                    : out  std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_TXUSRCLKX2_OUT                      : out  std_logic; --// Modified
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic; --// Modified
+     GT0_QPLLOUTREFCLK_IN : in std_logic; --// Modified
+       sysclk_in        : in std_logic;
+	   refclk_out       : out std_logic --// Modified
+
+);
+
+end gtxKintex7FEE80_support;
+    
+architecture RTL of gtxKintex7FEE80_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component gtxKintex7FEE80
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y0)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component gtxKintex7FEE80_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component gtxKintex7FEE80_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE" ;       -- Set to "TRUE" to speed up sim reset
+    SIM_QPLLREFCLK_SEL              :bit_vector  := "001"
+ 
+);
+port
+(
+    QPLLREFCLKSEL_IN   : in std_logic_vector(2 downto 0);
+    GTREFCLK0_IN : in std_logic;
+    GTREFCLK1_IN      : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component gtxKintex7FEE80_GT_USRCLK_SOURCE 
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXUSRCLKX2_OUT           : out std_logic; --// Modified
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_TXCLK_LOCK_OUT           : out std_logic;
+    GT0_TX_MMCM_RESET_IN         : in std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    Q0_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q0_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q0_CLK0_GTREFCLK_OUT                    : out  std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y0)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt0_rxdlyen_i                   : std_logic;
+    signal  gt0_rxdlysreset_i               : std_logic;
+    signal  gt0_rxdlysresetdone_i           : std_logic;
+    signal  gt0_rxphalign_i                 : std_logic;
+    signal  gt0_rxphaligndone_i             : std_logic;
+    signal  gt0_rxphalignen_i               : std_logic;
+    signal  gt0_rxphdlyreset_i              : std_logic;
+    signal  gt0_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt0_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt0_txdlyen_i                   : std_logic;
+    signal  gt0_txdlysreset_i               : std_logic;
+    signal  gt0_txdlysresetdone_i           : std_logic;
+    signal  gt0_txphalign_i                 : std_logic;
+    signal  gt0_txphaligndone_i             : std_logic;
+    signal  gt0_txphalignen_i               : std_logic;
+    signal  gt0_txphdlyreset_i              : std_logic;
+    signal  gt0_txphinit_i                  : std_logic;
+    signal  gt0_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt0_txmmcm_lock_i               : std_logic;
+    signal    gt0_txmmcm_reset_i              : std_logic;
+    ----------------------------- Reference Clocks ----------------------------
+    
+signal    q0_clk0_refclk_i                : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+     GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i;
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+     gt0_qplloutclk_i <= gt0_qplloutclk_in;  --// Modified
+     gt0_qplloutrefclk_i <= gt0_qplloutrefclk_in;  --// Modified
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+    
+  
+    gt_usrclk_source : gtxKintex7FEE80_GT_USRCLK_SOURCE
+    port map
+   (
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+		GT0_TXUSRCLKX2_OUT              =>      GT0_TXUSRCLKX2_OUT,  --// Modified
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_TXCLK_LOCK_OUT              =>      gt0_txmmcm_lock_i,
+        GT0_TX_MMCM_RESET_IN            =>      gt0_txmmcm_reset_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+        GT0_RXOUTCLK_IN                 =>      gt0_rxoutclk_i,
+        Q0_CLK0_GTREFCLK_PAD_N_IN       =>      Q0_CLK0_GTREFCLK_PAD_N_IN,
+        Q0_CLK0_GTREFCLK_PAD_P_IN       =>      Q0_CLK0_GTREFCLK_PAD_P_IN,
+        Q0_CLK0_GTREFCLK_OUT            =>      q0_clk0_refclk_i
+
+    );
+refclk_out <= q0_clk0_refclk_i; --// Modified
+sysclk_in_i <= sysclk_in;
+
+--// Modified
+    -- common0_i:gtxKintex7FEE80_common 
+  -- generic map
+  -- (
+   -- WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+   -- SIM_QPLLREFCLK_SEL => "001"
+  -- )
+ -- port map
+   -- (
+    -- QPLLREFCLKSEL_IN    => "001",
+    -- GTREFCLK0_IN      => q0_clk0_refclk_i,
+    -- GTREFCLK1_IN      => tied_to_ground_i,
+    -- QPLLLOCK_OUT => gt0_qplllock_i,
+    -- QPLLLOCKDETCLK_IN => sysclk_in_i,
+    -- QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    -- QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    -- QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    -- QPLLRESET_IN => gt0_qpllreset_t
+
+-- );
+
+    common_reset_i:gtxKintex7FEE80_common_reset 
+   generic map 
+   (
+      STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   )
+   port map
+   (    
+      STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET => soft_reset_tx_in,               --User Reset, can be pulled any time
+      COMMON_RESET => commonreset_i              --Reset QPLL
+   );
+
+
+    gtxKintex7FEE80_init_i : gtxKintex7FEE80
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_tx_in                =>      SOFT_RESET_TX_IN,
+        soft_reset_rx_in                =>      SOFT_RESET_RX_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_mmcm_lock_in             =>      gt0_txmmcm_lock_i,
+        gt0_tx_mmcm_reset_out           =>      gt0_txmmcm_reset_i,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y0)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      q0_clk0_refclk_i,
+        gt0_gtrefclk1_in                =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+		------------------------- Receive Ports - CDR Ports ------------------------
+		GT0_RXCDRRESET_IN               =>      GT0_RXCDRRESET_IN, --// Modified
+		GT0_RXCDRLOCK_OUT               =>      GT0_RXCDRLOCK_OUT, --// Modified
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+
+
+end RTL;
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/SystemMonitorKintex/SystemMonitorKintex.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/SystemMonitorKintex/SystemMonitorKintex.xci
new file mode 100644
index 0000000..892d773
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/SystemMonitorKintex/SystemMonitorKintex.xci
@@ -0,0 +1,284 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>SystemMonitorKintex</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="xadc_wiz" spirit:version="3.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R0">46573</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R1">22500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R10">21845</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R11">20753</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R12">39321</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R13">37355</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R14">27306</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R15">25122</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R2">41287</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R3">51763</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R4">43322</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R5">21190</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R6">38229</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R7">44622</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R8">22937</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALARM_LIMIT_R9">20753</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIGURATION_R0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIGURATION_R1">16640</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CONFIGURATION_R2">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_FREQUENCY">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXTERNAL_MUXADDR_ENABLE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EXTERNAL_MUX_CHANNEL">VP_VN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FIFO_DEPTH">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI4STREAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BUSY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CONVST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CONVSTCLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DCLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DRP">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_EOC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_EOS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_EXTERNAL_MUX">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_JTAGBUSY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_JTAGLOCKED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_JTAGMODIFIED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OT_ALARM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RESET">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_TEMP_BUS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_USER_TEMP_ALARM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VBRAM_ALARM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VCCAUX_ALARM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VCCDDRO_ALARM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VCCINT_ALARM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VCCPAUX_ALARM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VCCPINT_ALARM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VP">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLUDE_INTR">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SAMPLING_RATE">769230.7692307692</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SEQUENCE_R0">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SEQUENCE_R1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SEQUENCE_R2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SEQUENCE_R3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SEQUENCE_R4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SEQUENCE_R5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SEQUENCE_R6">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SEQUENCE_R7">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_FILE_NAME">design</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_FILE_REL_PATH">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_FILE_SEL">Default</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX0">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX10">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX11">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX12">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX13">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX14">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX15">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX3">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX4">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX5">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX6">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX7">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX8">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VAUX9">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">SystemMonitorKintex</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP0_VAUXN0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP10_VAUXN10">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP11_VAUXN11">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP12_VAUXN12">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP13_VAUXN13">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP14_VAUXN14">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP15_VAUXN15">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP1_VAUXN1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP2_VAUXN2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP3_VAUXN3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP4_VAUXN4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP5_VAUXN5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP6_VAUXN6">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP7_VAUXN7">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP8_VAUXN8">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VAUXP9_VAUXN9">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACQUISITION_TIME_VP_VN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADC_CONVERSION_RATE">1000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADC_OFFSET_AND_GAIN_CALIBRATION">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADC_OFFSET_CALIBRATION">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_TEMPERATURE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP0_VAUXN0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP10_VAUXN10">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP11_VAUXN11">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP12_VAUXN12">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP13_VAUXN13">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP14_VAUXN14">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP15_VAUXN15">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP1_VAUXN1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP2_VAUXN2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP3_VAUXN3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP4_VAUXN4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP5_VAUXN5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP6_VAUXN6">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP7_VAUXN7">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP8_VAUXN8">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VAUXP9_VAUXN9">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VBRAM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VCCAUX">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VCCDDRO">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VCCINT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VCCPAUX">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VCCPINT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AVERAGE_ENABLE_VP_VN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_OPERATION">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP0_VAUXN0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP10_VAUXN10">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP11_VAUXN11">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP12_VAUXN12">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP13_VAUXN13">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP14_VAUXN14">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP15_VAUXN15">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP1_VAUXN1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP2_VAUXN2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP3_VAUXN3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP4_VAUXN4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP5_VAUXN5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP6_VAUXN6">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP7_VAUXN7">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP8_VAUXN8">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VAUXP9_VAUXN9">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BIPOLAR_VP_VN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_AVERAGING">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_CALIBRATION">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_TEMPERATURE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP0_VAUXN0">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP10_VAUXN10">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP11_VAUXN11">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP12_VAUXN12">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP13_VAUXN13">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP14_VAUXN14">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP15_VAUXN15">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP1_VAUXN1">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP2_VAUXN2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP3_VAUXN3">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP4_VAUXN4">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP5_VAUXN5">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP6_VAUXN6">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP7_VAUXN7">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP8_VAUXN8">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VAUXP9_VAUXN9">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VBRAM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VCCAUX">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VCCDDRO">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VCCINT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VCCPAUX">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VCCPINT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VP_VN">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VREFN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VREFP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">SystemMonitorKintex</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_FREQUENCY">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_AXI4STREAM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_BUSY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CALIBRATION_AVERAGING">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CHANNEL">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CONVST">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CONVSTCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DCLK">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_DRP">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_EOC">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_EOS">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_EXTERNAL_MUX">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_JTAGBUSY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_JTAGLOCKED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_JTAGMODIFIED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_JTAG_ARBITER">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_RESET">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_TEMP_BUS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_VBRAM_ALARM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_VCCDDRO_ALARM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_VCCPAUX_ALARM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_VCCPINT_ALARM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXTERNAL_MUXADDR_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EXTERNAL_MUX_CHANNEL">VP_VN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_DEPTH">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INCREASE_ACQUISITION_TIME">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">ENABLE_DRP</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_WAVE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OT_ALARM">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_ADCA">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_ADCB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SENSOR_OFFSET_AND_GAIN_CALIBRATION">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SENSOR_OFFSET_CALIBRATION">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SEQUENCER_MODE">Off</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SIM_FILE_NAME">design</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SIM_FILE_REL_PATH">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SIM_FILE_SEL">Default</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLE_CHANNEL_ACQUISITION_TIME">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLE_CHANNEL_ENABLE_CALIBRATION">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLE_CHANNEL_SELECTION">TEMPERATURE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STARTUP_CHANNEL_SELECTION">single_channel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STIMULUS_FREQ">1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TEMPERATURE_ALARM_OT_RESET">70.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TEMPERATURE_ALARM_OT_TRIGGER">125.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TEMPERATURE_ALARM_RESET">60.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TEMPERATURE_ALARM_TRIGGER">85.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TIMING_MODE">Continuous</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_TEMP_ALARM">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VBRAM_ALARM_LOWER">0.95</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VBRAM_ALARM_UPPER">1.05</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCAUX_ALARM">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCAUX_ALARM_LOWER">1.75</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCAUX_ALARM_UPPER">1.89</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCDDRO_ALARM_LOWER">1.15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCDDRO_ALARM_UPPER">1.25</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCDDRO_VOLT">1_2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCINT_ALARM">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCINT_ALARM_LOWER">0.97</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCINT_ALARM_UPPER">1.03</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCPAUX_ALARM_LOWER">1.71</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCPAUX_ALARM_UPPER">1.8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCPINT_ALARM_LOWER">0.95</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.VCCPINT_ALARM_UPPER">1.00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WAVEFORM_TYPE">CONSTANT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.XADC_STARUP_SELECTION">simultaneous_sampling</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ADC_CONVERSION_RATE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CHANNEL_ENABLE_VP_VN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DCLK_FREQUENCY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.ENABLE_JTAG_ARBITER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SEQUENCER_MODE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.XADC_STARUP_SELECTION" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_16x9/async_fifo_16x9.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_16x9/async_fifo_16x9.xci
new file mode 100644
index 0000000..a75af03
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_16x9/async_fifo_16x9.xci
@@ -0,0 +1,423 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_16x9</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_16x9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_256x32/async_fifo_256x32.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_256x32/async_fifo_256x32.xci
new file mode 100644
index 0000000..66a996c
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_256x32/async_fifo_256x32.xci
@@ -0,0 +1,425 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_256x32</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">253</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">252</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_256x32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">253</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">252</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_512x32/async_fifo_512x32.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_512x32/async_fifo_512x32.xci
new file mode 100644
index 0000000..5fed711
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_fifo_512x32/async_fifo_512x32.xci
@@ -0,0 +1,423 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_512x32</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">508</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_512x32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">508</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_progfull448_progempty128_fifo_512x34/async_progfull448_progempty128_fifo_512x34.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_progfull448_progempty128_fifo_512x34/async_progfull448_progempty128_fifo_512x34.xci
new file mode 100644
index 0000000..b255f47
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/async_progfull448_progempty128_fifo_512x34/async_progfull448_progempty128_fifo_512x34.xci
@@ -0,0 +1,429 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_progfull448_progempty128_fifo_512x34</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">34</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">34</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">129</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">448</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">447</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_progfull448_progempty128_fifo_512x34</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">129</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">448</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">447</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">34</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">34</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">Single_Programmable_Empty_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual/aurora_dual.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual/aurora_dual.xci
new file mode 100644
index 0000000..59d8fd5
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual/aurora_dual.xci
@@ -0,0 +1,243 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>aurora_dual</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="aurora_8b10b" spirit:version="11.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOCCPORT_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK_LOC_N">BL7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK_LOC_P">BL8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REFCLK_SOURCE">none</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_START_LANE">X0Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_START_QUAD">X0Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_active_transceiverquads">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SINGLEEND_GTREFCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SINGLEEND_INITCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.TXDIFFCTRL_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USDMON_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.USDRPADDR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.backchannel_mode">Sidebands</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_aurora_lanes">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_column_used">left</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpll_fbdiv">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpll_fbdiv_45">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_device">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_drp_if">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_example_simulation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_family">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_clock_1">GTXQ0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_clock_2">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_1">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_10">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_11">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_12">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_13">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_14">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_15">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_16">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_17">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_18">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_19">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_2">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_20">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_21">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_22">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_23">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_24">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_25">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_26">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_27">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_28">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_29">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_3">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_30">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_31">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_32">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_33">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_34">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_35">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_36">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_37">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_38">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_39">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_4">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_40">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_41">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_42">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_43">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_44">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_45">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_46">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_47">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_48">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_5">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_6">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_7">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_8">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_gt_loc_9">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_init_clk">80.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_lane_width">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_line_rate">20000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_nfc_mode">IMM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_refclk_frequency">80000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rembuswidthselect">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_row_used">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_rxoutdiv">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_simplex">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_simplex_mode">TX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_stream">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_txoutdiv">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ucolumn_used">right</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ufc">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ufcbuswidthselect">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ufcrembuswidthselect">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_ufcstrbbuswidthselect">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_byteswap">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_chipscope">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_crc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_use_scrambler">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xpackage">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">aurora_dual</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.dataflow_config">Duplex</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.drp_freq">80.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.flow_mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtquadcnt">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.interface_mode">Framing</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_7series">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.is_board">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.isv7gth">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.port7dmonitorout">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.supportlevel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.transceivercontrol">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.user_interface">AXI_4_Streaming</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Backchannel_mode">Sidebands</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CHANNEL_ENABLE">X0Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_AURORA_LANES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_COLUMN_USED">left</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DOCCPORT_ENABLE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DRP_IF">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EXAMPLE_SIMULATION">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_CLOCK_1">GTXQ0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_CLOCK_2">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_1">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_10">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_11">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_12">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_13">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_14">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_15">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_16">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_17">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_18">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_19">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_2">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_20">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_21">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_22">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_23">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_24">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_25">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_26">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_27">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_28">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_29">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_3">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_30">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_31">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_32">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_33">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_34">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_35">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_36">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_37">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_38">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_39">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_4">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_40">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_41">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_42">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_43">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_44">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_45">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_46">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_47">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_48">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_5">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_6">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_7">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_8">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_GT_LOC_9">X</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INIT_CLK">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LANE_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_LINE_RATE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK_FREQUENCY">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_REFCLK_SOURCE">none</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ROW_USED">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_START_LANE">X0Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_START_QUAD">X0Y0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_UCOLUMN_USED">right</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_BYTESWAP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_CHIPSCOPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_CRC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_USE_SCRAMBLER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_active_transceiverquads">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">aurora_dual</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRP_FREQ">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dataflow_Config">Duplex</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Flow_Mode">UFC+_Immediate_NFC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Mode">Framing</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLEEND_GTREFCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SINGLEEND_INITCLK">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SupportLevel">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TransceiverControl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_AURORA_LANES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GT_CLOCK_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GT_LOC_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GT_LOC_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_GT_LOC_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_INIT_CLK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LANE_WIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_LINE_RATE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_REFCLK_FREQUENCY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.DRP_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Flow_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Interface_Mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SINGLEEND_INITCLK" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SupportLevel" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/sim_reset_mgt_model.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_aurora_pkg.vhd
similarity index 54%
rename from FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/sim_reset_mgt_model.vhd
rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_aurora_pkg.vhd
index f1ed3db..3ceea68 100644
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/sim_reset_mgt_model.vhd
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_aurora_pkg.vhd
@@ -1,31 +1,10 @@
---------------------------------------------------------------------------------
---   ____  ____ 
---  /   /\/   / 
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
---  /   /         Filename : sim_reset_mgt_model.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\ 
---
---
--- Module SIM_RESET_MGT_MODEL
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
---
--- The Reset On Configuration(ROC) module is part of the UNISIM library
--- and is required for emulating the GSR pulse at the beginning of functional
--- simulation in order to correctly reset the VHDL MGT smart model.This module
--- is required for simulation only.
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
+-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
+--
 -- This file contains confidential and proprietary information
 -- of Xilinx, Inc. and is protected under U.S. and
 -- international copyright and other intellectual property
 -- laws.
--- 
+--
 -- DISCLAIMER
 -- This disclaimer is not a license and does not grant any
 -- rights to the materials distributed herewith. Except as
@@ -47,7 +26,7 @@
 -- by a third party) even if such damage or loss was
 -- reasonably foreseeable or Xilinx had been advised of the
 -- possibility of the same.
--- 
+--
 -- CRITICAL APPLICATIONS
 -- Xilinx products are not designed or intended to be fail-
 -- safe, or for use in any application requiring fail-safe
@@ -61,43 +40,45 @@
 -- liability of any use of Xilinx products in Critical
 -- Applications, subject only to applicable laws and
 -- regulations governing limitations on product liability.
--- 
+--
 -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
---***************************** Entity Declaration *****************************
-
-entity SIM_RESET_MGT_MODEL is
-port 
-(
-    GSR_IN     : in std_logic
-);
-end SIM_RESET_MGT_MODEL;
-
-architecture BEHAVIORAL of SIM_RESET_MGT_MODEL is
-  
-                  
---********************************* Main Body of Code****************************
-                       
-begin                      
-    GSR <= GSR_IN;                       
-    ------------------------------  ROCBUF Instantiation -----------------------   
-    -- This component is required for correctly resetting the VHDL GTX component on configuration
-    -- It is for simulation alone and will be ripped out during synthesis.
-    U1 : ROCBUF 
-    port map 
-    (
-        I => GSR,
-        O => open
-    ); 
-
-
-end BEHAVIORAL;
-
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+
+--
+--  AURORA
+--
+--
+--  Description: Aurora Package Definition
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use STD.TEXTIO.all;
+
+package AURORA_PKG is
+
+    function std_bool (EXP_IN : in boolean) return std_logic;
+
+end;
+
+package body AURORA_PKG is
+
+    function std_bool (EXP_IN : in boolean) return std_logic is
+
+    begin
+
+        if (EXP_IN) then
+
+            return('1');
+
+        else
+
+            return('0');
+
+        end if;
+
+    end std_bool;
+
+end;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_axi_to_ll_exdes.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_axi_to_ll_exdes.vhd
new file mode 100644
index 0000000..78bdc04
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_axi_to_ll_exdes.vhd
@@ -0,0 +1,183 @@
+------------------------------------------------------------------------------
+-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+------------------------------------------------------------------------------
+--
+--  AXI_TO_LL_EXDES
+--
+--
+--  Description: This light wrapper/shim convertes Legacy LocalLink interface
+--               signals from AXI-4 Stream protocol signals
+--
+--
+------------------------------------------------------------------------------/
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_MISC.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity aurora_dual_AXI_TO_LL_EXDES is
+generic
+(
+    DATA_WIDTH  : integer :=   16;      -- DATA bus width
+    STRB_WIDTH  : integer :=   2;       -- STROBE bus width
+    REM_WIDTH   : integer :=   1;       -- REM bus width
+    USE_UFC_REM : integer :=   0        -- UFC REM bus width identifier
+);  
+
+port
+(
+
+  ----------------------  AXI4-S Interface -------------------------------
+ 
+  AXI4_S_IP_TX_TDATA              : in    std_logic_vector (0 to DATA_WIDTH-1);
+  AXI4_S_IP_TX_TKEEP              : in    std_logic_vector (0 to STRB_WIDTH-1);
+  AXI4_S_IP_TX_TVALID             : in    std_logic;
+  AXI4_S_IP_TX_TLAST              : in    std_logic;
+  AXI4_S_OP_TX_TREADY             : out   std_logic;
+
+  ----------------------  LocalLink Interface ----------------------------
+  LL_OP_DATA                      : out   std_logic_vector (0 to DATA_WIDTH-1);
+  LL_OP_REM                       : out   std_logic_vector (0 to REM_WIDTH -1);
+  LL_OP_SRC_RDY_N                 : out   std_logic;
+  LL_OP_SOF_N                     : out   std_logic;
+  LL_OP_EOF_N                     : out   std_logic;
+  LL_IP_DST_RDY_N                 : in    std_logic;
+
+  ----------------------  System Interface ----------------------------
+  USER_CLK                        : in    std_logic;
+  RESET                           : in    std_logic;
+  CHANNEL_UP                      : in    std_logic
+
+);
+
+end aurora_dual_AXI_TO_LL_EXDES;
+
+architecture BEHAVIORAL of aurora_dual_AXI_TO_LL_EXDES is
+  attribute core_generation_info               : string;
+attribute core_generation_info of BEHAVIORAL : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}";
+
+--***********************************Parameter Declarations***************************
+
+    constant DLY             : time      := 1 ns;
+
+    signal   new_pkt_r                   : std_logic;
+    signal   new_pkt                     : std_logic;
+    signal   temp_cond                   : std_logic;
+    signal   ll_op_sof                   : std_logic;
+    signal   ll_ip_dst_rdy               : std_logic;
+    signal   AXI4_S_IP_TX_TKEEP_i        : std_logic_vector(0 to STRB_WIDTH-1);
+
+begin
+
+--*********************************Main Body of Code**********************************
+
+
+
+   ll_ip_dst_rdy       <= not LL_IP_DST_RDY_N;
+
+ 
+   process(USER_CLK)
+   begin
+     if(USER_CLK'event and USER_CLK='1') then
+       LL_OP_DATA          <= AXI4_S_IP_TX_TDATA;
+     end if;
+   end process;
+
+ 
+   AXI4_S_IP_TX_TKEEP_i          <= AXI4_S_IP_TX_TKEEP;
+
+
+
+
+   process(USER_CLK)
+   begin
+     if(USER_CLK'event and USER_CLK='1') then
+       LL_OP_SRC_RDY_N     <= not AXI4_S_IP_TX_TVALID;
+       LL_OP_EOF_N         <= not AXI4_S_IP_TX_TLAST;
+     end if;
+   end process;
+   process(USER_CLK)
+   begin
+     if(USER_CLK'event and USER_CLK='1') then
+        LL_OP_REM           <= ("0" & AXI4_S_IP_TX_TKEEP_i(0)) + ("0" & AXI4_S_IP_TX_TKEEP_i(1)) + ("0" & AXI4_S_IP_TX_TKEEP_i(2)) + ("0" & AXI4_S_IP_TX_TKEEP_i(3))  - '1';
+     end if;
+   end process;
+   new_pkt             <= '0' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else
+			  '1' when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND not AXI4_S_IP_TX_TLAST) = '1') else
+			  new_pkt_r;
+
+   temp_cond           <= '0' when (new_pkt_r = '1') else
+			  '1';
+   ll_op_sof           <= temp_cond when ((AXI4_S_IP_TX_TVALID AND ll_ip_dst_rdy AND AXI4_S_IP_TX_TLAST) = '1') else
+			  (new_pkt and (not new_pkt_r));
+
+   process(USER_CLK)
+   begin
+     if(USER_CLK'event and USER_CLK='1') then
+       LL_OP_SOF_N         <= not ll_op_sof;
+     end if;
+   end process;
+
+   process(USER_CLK)
+   begin
+     if(USER_CLK'event and USER_CLK='1') then
+       if(RESET = '1') then
+         new_pkt_r     <=  '0' after DLY; 
+       elsif(CHANNEL_UP = '1') then
+         new_pkt_r     <=  new_pkt after DLY; 
+       else
+         new_pkt_r     <=  '0' after DLY; 
+       end if;
+     end if;
+   end process;
+
+   -- Assign output from temp signal
+   AXI4_S_OP_TX_TREADY <= ll_ip_dst_rdy;
+
+end BEHAVIORAL;   
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_cdc_sync_exdes.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_cdc_sync_exdes.vhd
new file mode 100644
index 0000000..7836bcb
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_cdc_sync_exdes.vhd
@@ -0,0 +1,741 @@
+------------------------------------------------------------------------------/
+-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+--------------------------------------------------------------------------------
+
+--Generic Help
+--C_CDC_TYPE : Defines the type of CDC needed
+--             0 means pulse synchronizer. Used to transfer one clock pulse 
+--               from prmry domain to scndry domain.
+--             1 means level synchronizer. Used to transfer level signal.
+--             2 means level synchronizer with ack. Used to transfer level 
+--               signal. Input signal should change only when prmry_ack is detected
+--
+--C_FLOP_INPUT : when set to 1 adds one flop stage to the input prmry_in signal
+--               Set to 0 when incoming signal is purely floped signal.
+--
+--C_RESET_STATE : Generally sync flops need not have resets. However, in some cases
+--                it might be needed.
+--              0 means reset not needed for sync flops 
+--              1 means reset needed for sync flops. i
+--                In this case prmry_resetn should be in prmry clock, 
+--                while scndry_reset should be in scndry clock.
+--
+--C_SINGLE_BIT : CDC should normally be done for single bit signals only. 
+--               However, based on design buses can also be CDC'ed.
+--               0 means it is a bus. In this case input be connected to prmry_vect_in.
+--                 Output is on scndry_vect_out.
+--               1 means it is a single bit. In this case input be connected to prmry_in. 
+--                 Output is on scndry_out.
+--
+--C_VECTOR_WIDTH : defines the size of bus. This is irrelevant when C_SINGLE_BIT = 1
+--
+--C_MTBF_STAGES : Defines the number of sync stages needed. Allowed values are 0 to 6.
+--                Value of 0, 1 is allowed only for level CDC.
+--                Min value for Pulse CDC is 2
+--
+--Whenever this file is used following XDC constraint has to be added 
+
+--         set_false_path -to [get_pins -hier *cdc_to*]        
+
+
+--IO Ports 
+--
+--        prmry_aclk      : clock of originating domain (source domain)
+--        prmry_resetn    : sync reset of originating clock domain (source domain)
+--        prmry_in        : input signal bit. This should be a pure flop output without 
+--                          any combi logic. This is source. 
+--        prmry_vect_in   : bus signal. From Source domain.
+--        prmry_ack       : Ack signal, valid for one clock period, in prmry_aclk domain.
+--                          Used only when C_CDC_TYPE = 2
+--        scndry_aclk     : destination clock.
+--        scndry_resetn   : sync reset of destination domain
+--        scndry_out      : sync'ed output in destination domain. Single bit.
+--        scndry_vect_out : sync'ed output in destination domain. bus.
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_misc.all;
+
+
+
+entity  aurora_dual_cdc_sync_exdes is
+    generic (
+        C_CDC_TYPE                  : integer range 0 to 2 := 1                 ;
+                                    -- 0 is pulse synch
+                                    -- 1 is level synch
+                                    -- 2 is ack based level sync
+        C_RESET_STATE               : integer range 0 to 1 := 0                 ;
+                                    -- 0 is reset not needed 
+                                    -- 1 is reset needed 
+        C_SINGLE_BIT                : integer range 0 to 1 := 1                 ; 
+                                    -- 0 is bus input
+                                    -- 1 is single bit input
+        C_FLOP_INPUT                : integer range 0 to 1 := 0                 ;
+        C_VECTOR_WIDTH              : integer range 0 to 32 := 32                             ;
+        C_MTBF_STAGES               : integer range 0 to 6 := 2                 
+            -- Vector Data witdth
+    );
+
+    port (
+        prmry_aclk                  : in  std_logic                             ;               --
+        prmry_resetn                : in  std_logic                             ;               --
+        prmry_in                    : in  std_logic                             ;               --
+        prmry_vect_in               : in  std_logic_vector                                      --
+                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --
+        prmry_ack                   : out std_logic                             ;
+                                                                                                --
+        scndry_aclk                 : in  std_logic                             ;               --
+        scndry_resetn               : in  std_logic                             ;               --
+                                                                                                --
+        -- Primary to Secondary Clock Crossing                                                  --
+        scndry_out                  : out std_logic                             ;               --
+                                                                                                --
+        scndry_vect_out             : out std_logic_vector                                      --
+                                        (C_VECTOR_WIDTH - 1 downto 0)                           --
+
+    );
+
+end aurora_dual_cdc_sync_exdes;
+
+-------------------------------------------------------------------------------
+-- Architecture
+-------------------------------------------------------------------------------
+architecture implementation of aurora_dual_cdc_sync_exdes is
+  attribute DowngradeIPIdentifiedWarnings: string;
+  attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
+
+-------------------------------------------------------------------------------
+-- Functions
+-------------------------------------------------------------------------------
+
+-- No Functions Declared
+
+-------------------------------------------------------------------------------
+-- Constants Declarations
+-------------------------------------------------------------------------------
+
+-- No Constants Declared
+
+-------------------------------------------------------------------------------
+-- Begin architecture logic
+-------------------------------------------------------------------------------
+begin
+-- Generate PULSE clock domain crossing
+GENERATE_PULSE_P_S_CDC_OPEN_ENDED : if C_CDC_TYPE = 0 generate
+
+-- Primary to Secondary
+signal s_out_d1_cdc_to          : std_logic := '0';
+signal s_out_d2           	: std_logic := '0';
+signal s_out_d3           	: std_logic := '0';
+signal s_out_d4           	: std_logic := '0';
+signal s_out_d5           	: std_logic := '0';
+signal s_out_d6           	: std_logic := '0';
+signal s_out_d7           	: std_logic := '0';
+signal s_out_re           	: std_logic := '0';
+signal prmry_in_xored           : std_logic := '0';
+signal p_in_d1_cdc_from   	: std_logic := '0';
+
+
+
+ -----------------------------------------------------------------------------
+  -- ATTRIBUTE Declarations
+  -----------------------------------------------------------------------------
+  -- Prevent x-propagation on clock-domain crossing register
+  ATTRIBUTE async_reg                      	: STRING;
+  ATTRIBUTE async_reg OF s_out_d1_cdc_to  	: SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_out_d2  		: SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_out_d3  		: SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_out_d4  		: SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_out_d5  		: SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_out_d6  		: SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_out_d7  		: SIGNAL IS "true"; 
+
+  ATTRIBUTE shift_extract                      	: STRING;
+  ATTRIBUTE shift_extract OF s_out_d1_cdc_to  	: SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_out_d2  		: SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_out_d3  		: SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_out_d4  		: SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_out_d5  		: SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_out_d6  		: SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_out_d7  		: SIGNAL IS "no";
+ 
+begin
+
+    --*****************************************************************************
+    --**                  Asynchronous Pulse Clock Crossing                      **
+    --**                  PRIMARY TO SECONDARY OPEN-ENDED                        **
+    --*****************************************************************************
+
+prmry_in_xored <= prmry_in xor p_in_d1_cdc_from;
+ 
+    REG_P_IN : process(prmry_aclk)
+        begin
+            if(prmry_aclk'EVENT and prmry_aclk ='1')then
+                if(prmry_resetn = '0' and C_RESET_STATE = 1)then
+                    p_in_d1_cdc_from  <= '0';
+                else
+                    p_in_d1_cdc_from  <= prmry_in_xored;
+                end if;
+            end if;
+        end process REG_P_IN;
+
+
+    P_IN_CROSS2SCNDRY : process(scndry_aclk)
+        begin
+            if(scndry_aclk'EVENT and scndry_aclk ='1')then
+                if(scndry_resetn = '0' and C_RESET_STATE = 1)then
+                    s_out_d1_cdc_to  	<= '0';
+                    s_out_d2  		<= '0';
+                    s_out_d3  		<= '0';
+                    s_out_d4  		<= '0';
+                    s_out_d5  		<= '0';
+                    s_out_d6  		<= '0';
+                    s_out_d7  		<= '0';
+                    scndry_out          <= '0';
+                else
+                    s_out_d1_cdc_to  	<= p_in_d1_cdc_from;
+                    s_out_d2  		<= s_out_d1_cdc_to;
+                    s_out_d3  		<= s_out_d2;
+                    s_out_d4  		<= s_out_d3;
+                    s_out_d5  		<= s_out_d4;
+                    s_out_d6  		<= s_out_d5;
+                    s_out_d7  		<= s_out_d6;
+                    scndry_out          <= s_out_re;
+                end if;
+            end if;
+        end process P_IN_CROSS2SCNDRY;
+
+MTBF_2 : if C_MTBF_STAGES = 2 generate
+begin
+                    s_out_re  <= s_out_d2 xor s_out_d3;
+
+end generate MTBF_2;
+
+MTBF_3 : if C_MTBF_STAGES = 3 generate
+begin
+                    s_out_re  <= s_out_d3 xor s_out_d4;
+
+end generate MTBF_3;
+
+MTBF_4 : if C_MTBF_STAGES = 4 generate
+begin
+                    s_out_re  <= s_out_d4 xor s_out_d5;
+
+end generate MTBF_4;
+
+MTBF_5 : if C_MTBF_STAGES = 5 generate
+begin
+                    s_out_re  <= s_out_d5 xor s_out_d6;
+
+end generate MTBF_5;
+
+MTBF_6 : if C_MTBF_STAGES = 6 generate
+begin
+                    s_out_re  <= s_out_d6 xor s_out_d7;
+
+end generate MTBF_6;
+
+   -- Feed secondary pulse out
+
+end generate GENERATE_PULSE_P_S_CDC_OPEN_ENDED;
+
+
+-- Generate LEVEL clock domain crossing with reset state = 0
+GENERATE_LEVEL_P_S_CDC : if C_CDC_TYPE = 1 generate
+begin
+-- Primary to Secondary
+
+SINGLE_BIT : if C_SINGLE_BIT = 1 generate 
+
+signal p_level_in_d1_cdc_from        : std_logic := '0';
+signal p_level_in_int        : std_logic := '0';
+signal s_level_out_d1_cdc_to       : std_logic := '0';
+signal s_level_out_d2       : std_logic := '0';
+signal s_level_out_d3       : std_logic := '0';
+signal s_level_out_d4       : std_logic := '0';
+signal s_level_out_d5       : std_logic := '0';
+signal s_level_out_d6       : std_logic := '0';
+ -----------------------------------------------------------------------------
+  -- ATTRIBUTE Declarations
+  -----------------------------------------------------------------------------
+  -- Prevent x-propagation on clock-domain crossing register
+  ATTRIBUTE async_reg                      : STRING;
+  ATTRIBUTE async_reg OF s_level_out_d1_cdc_to  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_d2  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_d3  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_d4  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_d5  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_d6  : SIGNAL IS "true"; 
+
+  ATTRIBUTE shift_extract                      	: STRING;
+  ATTRIBUTE shift_extract OF s_level_out_d1_cdc_to  : SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_level_out_d2  : SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_level_out_d3  : SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_level_out_d4  : SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_level_out_d5  : SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_level_out_d6  : SIGNAL IS "no"; 
+
+  ATTRIBUTE keep                           	: STRING;
+  ATTRIBUTE keep OF p_level_in_d1_cdc_from   : SIGNAL IS "true";
+begin
+
+    --*****************************************************************************
+    --**                  Asynchronous Level Clock Crossing                      **
+    --**                        PRIMARY TO SECONDARY                             **
+    --*****************************************************************************
+    -- register is scndry to provide clean ff output to clock crossing logic
+
+INPUT_FLOP : if C_FLOP_INPUT = 1 generate
+begin
+
+    REG_PLEVEL_IN : process(prmry_aclk)
+        begin
+            if(prmry_aclk'EVENT and prmry_aclk ='1')then
+                if(prmry_resetn = '0' and C_RESET_STATE = 1)then
+                    p_level_in_d1_cdc_from  <= '0';
+                else
+                    p_level_in_d1_cdc_from  <= prmry_in;
+                end if;
+            end if;
+        end process REG_PLEVEL_IN;
+
+         p_level_in_int <= p_level_in_d1_cdc_from;
+
+end generate INPUT_FLOP;
+
+
+NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
+begin
+
+       p_level_in_int <= prmry_in;
+
+end generate NO_INPUT_FLOP;
+
+    CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
+        begin
+            if(scndry_aclk'EVENT and scndry_aclk ='1')then
+                if(scndry_resetn = '0' and C_RESET_STATE = 1)then
+                    s_level_out_d1_cdc_to  <= '0';
+                    s_level_out_d2  <= '0';
+                    s_level_out_d3  <= '0';
+                    s_level_out_d4  <= '0';
+                    s_level_out_d5  <= '0';
+                    s_level_out_d6  <= '0';
+                else
+                    s_level_out_d1_cdc_to  <= p_level_in_int;
+                    s_level_out_d2  <= s_level_out_d1_cdc_to;
+                    s_level_out_d3  <= s_level_out_d2;
+                    s_level_out_d4  <= s_level_out_d3;
+                    s_level_out_d5  <= s_level_out_d4;
+                    s_level_out_d6  <= s_level_out_d5;
+                end if;
+            end if;
+        end process CROSS_PLEVEL_IN2SCNDRY;
+
+
+
+
+MTBF_L1 : if C_MTBF_STAGES = 1 generate
+begin
+    scndry_out <= s_level_out_d1_cdc_to;
+                   
+
+end generate MTBF_L1;
+
+MTBF_L2 : if C_MTBF_STAGES = 2 generate
+begin
+
+    scndry_out <= s_level_out_d2;
+                   
+
+end generate MTBF_L2;
+
+MTBF_L3 : if C_MTBF_STAGES = 3 generate
+begin
+    
+   scndry_out <= s_level_out_d3;
+
+
+
+end generate MTBF_L3;
+
+MTBF_L4 : if C_MTBF_STAGES = 4 generate
+begin
+    scndry_out <= s_level_out_d4;
+
+               
+
+end generate MTBF_L4;
+
+MTBF_L5 : if C_MTBF_STAGES = 5 generate
+begin
+
+    scndry_out <= s_level_out_d5;
+             
+
+end generate MTBF_L5;
+
+MTBF_L6 : if C_MTBF_STAGES = 6 generate
+begin
+
+    scndry_out <= s_level_out_d6;
+           
+
+end generate MTBF_L6;
+
+end generate SINGLE_BIT;
+
+
+
+MULTI_BIT : if C_SINGLE_BIT = 0 generate 
+
+signal p_level_in_bus_d1_cdc_from      : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d1_cdc_to       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d1_cdc_tig       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d2       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d3       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d4       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d5       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+signal s_level_out_bus_d6       : std_logic_vector(C_VECTOR_WIDTH - 1 downto 0);
+ -----------------------------------------------------------------------------
+  -- ATTRIBUTE Declarations
+  -----------------------------------------------------------------------------
+  -- Prevent x-propagation on clock-domain crossing register
+  ATTRIBUTE async_reg                      : STRING;
+  ATTRIBUTE async_reg OF s_level_out_bus_d1_cdc_to  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_bus_d2  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_bus_d3  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_bus_d4  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_bus_d5  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_bus_d6  : SIGNAL IS "true"; 
+
+  ATTRIBUTE shift_extract                      	: STRING;
+  ATTRIBUTE shift_extract OF s_level_out_bus_d1_cdc_to  : SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_level_out_bus_d2  : SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_level_out_bus_d3  : SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_level_out_bus_d4  : SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_level_out_bus_d5  : SIGNAL IS "no"; 
+  ATTRIBUTE shift_extract OF s_level_out_bus_d6  : SIGNAL IS "no"; 
+
+begin
+
+    --*****************************************************************************
+    --**                  Asynchronous Level Clock Crossing                      **
+    --**                        PRIMARY TO SECONDARY                             **
+    --*****************************************************************************
+    -- register is scndry to provide clean ff output to clock crossing logic
+--    REG_PLEVEL_IN : process(prmry_aclk)
+--        begin
+--            if(prmry_aclk'EVENT and prmry_aclk ='1')then
+--                if(prmry_resetn = '0' and C_RESET_STATE = 1)then
+--                    p_level_in_bus_d1_cdc_from  <= (others => '0');
+--                else
+--                    p_level_in_bus_d1_cdc_from  <= prmry_vect_in;
+--                end if;
+--            end if;
+--        end process REG_PLEVEL_IN;
+
+    CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
+        begin
+            if(scndry_aclk'EVENT and scndry_aclk ='1')then
+                if(scndry_resetn = '0' and C_RESET_STATE = 1)then
+                    s_level_out_bus_d1_cdc_to  <= (others => '0');
+                    s_level_out_bus_d2  <= (others => '0');
+                    s_level_out_bus_d3  <= (others => '0');
+                    s_level_out_bus_d4  <= (others => '0');
+                    s_level_out_bus_d5  <= (others => '0');
+                    s_level_out_bus_d6  <= (others => '0');
+                else
+                    s_level_out_bus_d1_cdc_to  <= prmry_vect_in;
+                    s_level_out_bus_d2  <= s_level_out_bus_d1_cdc_to;
+                    s_level_out_bus_d3  <= s_level_out_bus_d2;
+                    s_level_out_bus_d4  <= s_level_out_bus_d3;
+                    s_level_out_bus_d5  <= s_level_out_bus_d4;
+                    s_level_out_bus_d6  <= s_level_out_bus_d5;
+                end if;
+            end if;
+        end process CROSS_PLEVEL_IN2SCNDRY;
+
+
+
+MTBF_L1 : if C_MTBF_STAGES = 1 generate
+begin
+
+    scndry_vect_out <= s_level_out_bus_d1_cdc_to;
+                   
+
+end generate MTBF_L1;
+
+MTBF_L2 : if C_MTBF_STAGES = 2 generate
+begin
+
+    scndry_vect_out <= s_level_out_bus_d2;
+                   
+
+end generate MTBF_L2;
+
+MTBF_L3 : if C_MTBF_STAGES = 3 generate
+begin
+    
+   scndry_vect_out <= s_level_out_bus_d3;
+
+
+
+end generate MTBF_L3;
+
+MTBF_L4 : if C_MTBF_STAGES = 4 generate
+begin
+    scndry_vect_out <= s_level_out_bus_d4;
+
+               
+
+end generate MTBF_L4;
+
+MTBF_L5 : if C_MTBF_STAGES = 5 generate
+begin
+
+    scndry_vect_out <= s_level_out_bus_d5;
+             
+
+end generate MTBF_L5;
+
+MTBF_L6 : if C_MTBF_STAGES = 6 generate
+begin
+
+    scndry_vect_out <= s_level_out_bus_d6;
+           
+
+end generate MTBF_L6;
+
+end generate MULTI_BIT;
+
+
+end generate GENERATE_LEVEL_P_S_CDC;
+
+
+GENERATE_LEVEL_ACK_P_S_CDC : if C_CDC_TYPE = 2 generate
+-- Primary to Secondary
+
+
+signal p_level_in_d1_cdc_from        : std_logic := '0';
+signal p_level_in_int              : std_logic := '0';
+signal s_level_out_d1_cdc_to       : std_logic := '0';
+signal s_level_out_d2       : std_logic := '0';
+signal s_level_out_d3       : std_logic := '0';
+signal s_level_out_d4       : std_logic := '0';
+signal s_level_out_d5       : std_logic := '0';
+signal s_level_out_d6       : std_logic := '0';
+signal p_level_out_d1_cdc_to       : std_logic := '0';
+signal p_level_out_d2       : std_logic := '0';
+signal p_level_out_d3       : std_logic := '0';
+signal p_level_out_d4       : std_logic := '0';
+signal p_level_out_d5       : std_logic := '0';
+signal p_level_out_d6       : std_logic := '0';
+signal p_level_out_d7       : std_logic := '0';
+signal scndry_out_int       : std_logic := '0';
+signal prmry_pulse_ack      : std_logic := '0';
+ -----------------------------------------------------------------------------
+  -- ATTRIBUTE Declarations
+  -----------------------------------------------------------------------------
+  -- Prevent x-propagation on clock-domain crossing register
+  ATTRIBUTE async_reg                      : STRING;
+  ATTRIBUTE async_reg OF s_level_out_d1_cdc_to  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_d2  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_d3  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_d4  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_d5  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF s_level_out_d6  : SIGNAL IS "true"; 
+
+  ATTRIBUTE async_reg OF p_level_out_d1_cdc_to  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF p_level_out_d2  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF p_level_out_d3  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF p_level_out_d4  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF p_level_out_d5  : SIGNAL IS "true"; 
+  ATTRIBUTE async_reg OF p_level_out_d6  : SIGNAL IS "true"; 
+
+begin
+
+    --*****************************************************************************
+    --**                  Asynchronous Level Clock Crossing                      **
+    --**                        PRIMARY TO SECONDARY                             **
+    --*****************************************************************************
+    -- register is scndry to provide clean ff output to clock crossing logic
+INPUT_FLOP : if C_FLOP_INPUT = 1 generate
+begin
+
+    REG_PLEVEL_IN : process(prmry_aclk)
+        begin
+            if(prmry_aclk'EVENT and prmry_aclk ='1')then
+                if(prmry_resetn = '0' and C_RESET_STATE = 1)then
+                    p_level_in_d1_cdc_from  <= '0';
+                else
+                    p_level_in_d1_cdc_from  <= prmry_in;
+                end if;
+            end if;
+        end process REG_PLEVEL_IN;
+
+    p_level_in_int <= p_level_in_d1_cdc_from;
+
+end generate INPUT_FLOP;
+
+
+NO_INPUT_FLOP : if C_FLOP_INPUT = 0 generate
+begin
+
+    p_level_in_int <= prmry_in;
+
+end generate NO_INPUT_FLOP;
+
+    CROSS_PLEVEL_IN2SCNDRY : process(scndry_aclk)
+        begin
+            if(scndry_aclk'EVENT and scndry_aclk ='1')then
+                if(scndry_resetn = '0' and C_RESET_STATE = 1)then
+                    s_level_out_d1_cdc_to  <= '0';
+                    s_level_out_d2  <= '0';
+                    s_level_out_d3  <= '0';
+                    s_level_out_d4  <= '0';
+                    s_level_out_d5  <= '0';
+                    s_level_out_d6  <= '0';
+                else
+                    s_level_out_d1_cdc_to  <= p_level_in_int;
+                    s_level_out_d2  <= s_level_out_d1_cdc_to;
+                    s_level_out_d3  <= s_level_out_d2;
+                    s_level_out_d4  <= s_level_out_d3;
+                    s_level_out_d5  <= s_level_out_d4;
+                    s_level_out_d6  <= s_level_out_d5;
+                end if;
+            end if;
+        end process CROSS_PLEVEL_IN2SCNDRY;
+
+
+    CROSS_PLEVEL_SCNDRY2PRMRY : process(prmry_aclk)
+        begin
+            if(prmry_aclk'EVENT and prmry_aclk ='1')then
+                if(prmry_resetn = '0' and C_RESET_STATE = 1)then
+                    p_level_out_d1_cdc_to  <= '0';
+                    p_level_out_d2  <= '0';
+                    p_level_out_d3  <= '0';
+                    p_level_out_d4  <= '0';
+                    p_level_out_d5  <= '0';
+                    p_level_out_d6  <= '0';
+                    p_level_out_d7  <= '0';
+                    prmry_ack       <= '0';
+                else
+                    p_level_out_d1_cdc_to  <= scndry_out_int;
+                    p_level_out_d2  <= p_level_out_d1_cdc_to;
+                    p_level_out_d3  <= p_level_out_d2;
+                    p_level_out_d4  <= p_level_out_d3;
+                    p_level_out_d5  <= p_level_out_d4;
+                    p_level_out_d6  <= p_level_out_d5;
+                    p_level_out_d7  <= p_level_out_d6;
+                    prmry_ack       <= prmry_pulse_ack;
+                end if;
+            end if;
+        end process CROSS_PLEVEL_SCNDRY2PRMRY;
+
+
+
+
+MTBF_L2 : if C_MTBF_STAGES = 2 or C_MTBF_STAGES = 1 generate
+begin
+
+    scndry_out_int <= s_level_out_d2;
+    prmry_pulse_ack <= p_level_out_d3 xor p_level_out_d2;
+                   
+
+end generate MTBF_L2;
+
+MTBF_L3 : if C_MTBF_STAGES = 3 generate
+begin
+    
+   scndry_out_int <= s_level_out_d3;
+   prmry_pulse_ack <= p_level_out_d4 xor p_level_out_d3;
+
+
+
+end generate MTBF_L3;
+
+MTBF_L4 : if C_MTBF_STAGES = 4 generate
+begin
+    scndry_out_int <= s_level_out_d4;
+   prmry_pulse_ack <= p_level_out_d5 xor p_level_out_d4;
+
+               
+
+end generate MTBF_L4;
+
+MTBF_L5 : if C_MTBF_STAGES = 5 generate
+begin
+
+    scndry_out_int <= s_level_out_d5;
+   prmry_pulse_ack <= p_level_out_d6 xor p_level_out_d5;
+             
+
+end generate MTBF_L5;
+
+MTBF_L6 : if C_MTBF_STAGES = 6 generate
+begin
+
+    scndry_out_int <= s_level_out_d6;
+   prmry_pulse_ack <= p_level_out_d7 xor p_level_out_d6;
+           
+
+end generate MTBF_L6;
+
+       scndry_out <= scndry_out_int;
+
+
+end generate GENERATE_LEVEL_ACK_P_S_CDC;
+
+
+end implementation;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_clock_module.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_clock_module.vhd
new file mode 100644
index 0000000..bc4966b
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_clock_module.vhd
@@ -0,0 +1,148 @@
+-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+
+--
+--  CLOCK_MODULE
+--
+--
+--
+--  Description: A module provided as a convenience for desingners using 4-byte
+--               lane Aurora Modules. This module takes the V5 reference clock as
+--               input, and produces a fabric clock on a global clock net suitable
+--               for driving application logic connected to the Aurora User Interface.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+-- synthesis translate_off
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- synthesis translate_on
+
+entity aurora_dual_CLOCK_MODULE is
+
+    port (
+            INIT_CLK_P             : in std_logic;
+            INIT_CLK_N             : in std_logic;
+            INIT_CLK_O             : out std_logic;
+            GT_CLK                 : in std_logic;
+            GT_CLK_LOCKED          : in std_logic;
+            USER_CLK               : out std_logic;
+            SYNC_CLK               : out std_logic;
+            PLL_NOT_LOCKED         : out std_logic
+
+         );
+
+end aurora_dual_CLOCK_MODULE;
+
+architecture MAPPED of aurora_dual_CLOCK_MODULE is
+  attribute core_generation_info           : string;
+  attribute core_generation_info of MAPPED : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}";
+
+    component IBUFDS
+        port (
+
+                O : out std_ulogic;
+                I : in std_ulogic;
+                IB : in std_ulogic);
+
+    end component;
+
+
+-- External Register Declarations --
+
+
+    component BUFG
+
+        port (
+
+                O : out std_ulogic;
+                I : in  std_ulogic
+
+             );
+
+    end component;
+
+    signal  user_clk_i     : std_logic;
+    signal INIT_CLK_I       : std_logic;
+
+begin
+
+
+
+    USER_CLK       <= user_clk_i;
+    SYNC_CLK       <= user_clk_i;
+    PLL_NOT_LOCKED <= not GT_CLK_LOCKED;
+
+    -- The User Clock is distributed on a global clock net.
+    user_clk_buf_i : BUFG
+
+        port map (
+
+                    I => GT_CLK,
+                    O => user_clk_i
+
+                 );
+      -- init_clk_ibufg_i :  IBUFDS --// Modified
+      -- port map (
+           -- I  => INIT_CLK_P,
+           -- IB => INIT_CLK_N,
+           -- O  => INIT_CLK_I
+               -- );
+
+      -- init_clk_buf_i : BUFG
+      -- port map 
+        -- (
+          -- I  => INIT_CLK_I,
+          -- O  => INIT_CLK_O
+        -- );
+INIT_CLK_O <= '0'; --// Modified
+
+end MAPPED;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_gt_common_wrapper.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_gt_common_wrapper.vhd
new file mode 100644
index 0000000..e639721
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_gt_common_wrapper.vhd
@@ -0,0 +1,229 @@
+------------------------------------------------------------------------------/
+-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+--------------------------------------------------------------------------------
+library IEEE;
+  use IEEE.numeric_std.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.std_logic_misc.all;
+  use ieee.std_logic_1164.all;
+
+library UNISIM;
+  use UNISIM.Vcomponents.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity aurora_dual_gt_common_wrapper is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP    : string   := "FALSE" -- Set to "TRUE" to speed up sim reset
+);
+port
+(
+--____________________________COMMON PORTS ,_______________________________{
+   gt_qpllclk_quad1_i    : out  std_logic;
+   gt_qpllrefclk_quad1_i : out  std_logic;
+--____________________________COMMON PORTS ,_______________________________}
+    ---------------------- Common Block  - Ref Clock Ports ---------------------
+    gt0_gtrefclk0_common_in    :  in  std_logic;
+    ------------------------- Common Block - QPLL Ports ------------------------
+    gt0_qplllock_out           : out std_logic;
+    gt0_qplllockdetclk_in      : in  std_logic;
+    gt0_qpllrefclklost_out     : out std_logic;
+    gt0_qpllreset_in           : in  std_logic  
+);
+
+end aurora_dual_gt_common_wrapper;
+  
+architecture STRUCTURE of aurora_dual_gt_common_wrapper is
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+    impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return "0000100000";
+       elsif (qpllfbdiv_top = 20) then
+         return "0000110000" ;
+       elsif (qpllfbdiv_top = 32) then
+         return "0001100000" ;
+       elsif (qpllfbdiv_top = 40) then
+         return "0010000000" ;
+       elsif (qpllfbdiv_top = 64) then
+         return "0011100000" ;
+       elsif (qpllfbdiv_top = 66) then
+         return "0101000000" ;
+       elsif (qpllfbdiv_top = 80) then
+         return "0100100000" ;
+       elsif (qpllfbdiv_top = 100) then
+         return "0101110000" ;
+       else
+         return "0000000000" ;
+       end if;
+    end function;
+
+    impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return '1';
+       elsif (qpllfbdiv_top = 20) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 32) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 40) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 64) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 66) then
+         return '0' ;
+       elsif (qpllfbdiv_top = 80) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 100) then
+         return '1' ;
+       else
+         return '1' ;
+       end if;
+    end function;
+
+    constant   QPLL_FBDIV_TOP   :   integer  := 40;
+    constant   QPLL_FBDIV_IN    :   bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+    constant   QPLL_FBDIV_RATIO :   bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+--********************************* Main Body of Code**************************
+
+begin                      
+
+--********************************* Main Body of Code**************************
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTXE2_COMMON____________________________________
+gtxe2_common_i : GTXE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_QPLLREFCLK_SEL   => ("001"),
+            SIM_VERSION          => ("4.0"),
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000040000001000"),
+        COMMON_CFG                              =>     (x"00000000"),
+        QPLL_CFG                                =>     (x"06801C1"),
+        QPLL_CLKOUT_CFG                         =>     ("0000"),
+        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
+        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
+        QPLL_CP                                 =>     ("0000011111"),
+        QPLL_CP_MONITOR_EN                      =>     ('0'),
+        QPLL_DMONITOR_SEL                       =>     ('0'),
+        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
+        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
+        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
+        QPLL_INIT_CFG                           =>     (x"000006"),
+        QPLL_LOCK_CFG                           =>     (x"21E8"),
+        QPLL_LPF                                =>     ("1111"),
+        QPLL_REFCLK_DIV                         =>     (1)
+
+       
+    )
+    port map
+    (
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      gt0_gtrefclk0_common_in,
+        GTREFCLK1                       =>      tied_to_ground_i,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        QPLLDMONITOR                    =>      open,
+        QPLLFBCLKLOST                   =>      open,
+        QPLLLOCK                        =>      gt0_qplllock_out,
+        QPLLLOCKDETCLK                  =>      gt0_qplllockdetclk_in,
+        QPLLLOCKEN                      =>      tied_to_vcc_i,
+        QPLLOUTCLK                     => gt_qpllclk_quad1_i,
+        QPLLOUTREFCLK                  => gt_qpllrefclk_quad1_i,
+        QPLLOUTRESET                    =>      tied_to_ground_i,
+        QPLLPD                          =>      tied_to_vcc_i,
+        QPLLREFCLKLOST                  =>      gt0_qpllrefclklost_out,
+        QPLLREFCLKSEL                   =>      "001",
+        QPLLRESET                       =>      gt0_qpllreset_in,
+        QPLLRSVD1                       =>      "0000000000000000",
+        QPLLRSVD2                       =>      "11111",
+        REFCLKOUTMONITOR                =>      open,
+        ----------------------------- Common Block Ports ---------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "11111",
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+end STRUCTURE;
+ 
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_ll_to_axi_exdes.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_ll_to_axi_exdes.vhd
new file mode 100644
index 0000000..f7af7a8
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_ll_to_axi_exdes.vhd
@@ -0,0 +1,140 @@
+------------------------------------------------------------------------------
+-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+------------------------------------------------------------------------------
+--
+--  LL_TO_AXI_EXDES
+--
+--
+--  Description: This light wrapper/shim convertes Legacy LocalLink interface
+--               signals from AXI-4 Stream protocol signals
+--
+--
+------------------------------------------------------------------------------/
+library IEEE;
+use IEEE.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_misc.all;
+use ieee.std_logic_1164.all;
+
+entity aurora_dual_LL_TO_AXI_EXDES is
+generic
+(
+    DATA_WIDTH  : integer :=   16;      -- DATA bus width
+    STRB_WIDTH  : integer :=   2;       -- STROBE bus width
+    USE_UFC_REM : integer :=   0;       -- UFC REM bus width identifier
+     USE_4_NFC   : integer :=   0;       --  0 => PDU, 1 => NFC, 2 => UFC
+    REM_WIDTH   : integer :=   1        -- REM bus width
+);  
+
+port
+(
+
+  ----------------------  AXI4-S Interface -------------------------------
+  AXI4_S_OP_TDATA                 : out   std_logic_vector (0 to DATA_WIDTH-1);
+  AXI4_S_OP_TKEEP                 : out   std_logic_vector (0 to STRB_WIDTH-1);
+  AXI4_S_OP_TVALID                : out   std_logic;
+  AXI4_S_OP_TLAST                 : out   std_logic;
+  AXI4_S_IP_TREADY                : in    std_logic;
+
+  ----------------------  LocalLink Interface ----------------------------
+  LL_IP_DATA                      : in    std_logic_vector (0 to DATA_WIDTH-1);
+  LL_IP_REM                       : in    std_logic_vector (0 to REM_WIDTH-1);
+  LL_IP_SRC_RDY_N                 : in    std_logic;
+  LL_IP_SOF_N                     : in    std_logic;
+  LL_IP_EOF_N                     : in    std_logic;
+  LL_OP_DST_RDY_N                 : out   std_logic
+
+);
+
+end aurora_dual_LL_TO_AXI_EXDES;
+
+architecture BEHAVIORAL of aurora_dual_LL_TO_AXI_EXDES is
+  attribute core_generation_info               : string;
+attribute core_generation_info of BEHAVIORAL : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}";
+
+--***********************************Parameter Declarations***************************
+
+    constant DLY                  : time      := 1 ns;
+    signal   ll_ip_rem_inc_shift  : std_logic_vector(0 to STRB_WIDTH-1);
+    signal   rem_int              : integer range 0 to 4;
+    signal   ufc_rem_int          : integer range 0 to 16;
+signal   AXI4_S_OP_TKEEP_i        : std_logic_vector(0 to STRB_WIDTH-1);
+begin
+
+--*********************************Main Body of Code**********************************
+
+ 
+        AXI4_S_OP_TDATA      <= LL_IP_DATA;
+
+ 
+            AXI4_S_OP_TKEEP <= AXI4_S_OP_TKEEP_i ;
+
+
+
+
+
+pdu_rem : if USE_UFC_REM = 0 generate
+   rem_int             <= TO_INTEGER(unsigned (LL_IP_REM + '1'));
+ll_ip_rem_inc_shift <= to_stdlogicvector("1111" srl rem_int);
+AXI4_S_OP_TKEEP_i     <= "1111" when (LL_IP_REM = "11") else
+                          (not ll_ip_rem_inc_shift);
+end generate pdu_rem;
+
+ufc_rem : if USE_UFC_REM = 1 generate
+   ufc_rem_int         <= TO_INTEGER(unsigned (LL_IP_REM + '1'));
+ll_ip_rem_inc_shift <= to_stdlogicvector("1111" srl ufc_rem_int);
+AXI4_S_OP_TKEEP_i     <= "1111" when (LL_IP_REM = "11") else
+                          (not ll_ip_rem_inc_shift);
+end generate ufc_rem;  
+
+   AXI4_S_OP_TVALID    <= not LL_IP_SRC_RDY_N;
+   AXI4_S_OP_TLAST     <= not LL_IP_EOF_N;
+   LL_OP_DST_RDY_N     <= not AXI4_S_IP_TREADY;
+
+end BEHAVIORAL;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_module.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_module.vhd
new file mode 100644
index 0000000..3fc835f
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_module.vhd
@@ -0,0 +1,877 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_MISC.all;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+use WORK.AURORA_PKG.all;
+
+-- synthesis translate_off
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- synthesis translate_on
+
+entity aurora_dual_module is
+    port (
+		stable_clock                : in std_logic; -- 80MHz
+		reset                       : in std_logic;
+		user_clock                  : out std_logic;
+		tx_data                     : in std_logic_vector(31 downto 0);
+		tx_first                    : in std_logic;
+		tx_last                     : in std_logic;
+		tx_write                    : in std_logic;
+		tx_allowed                  : out std_logic;
+		tx_inpipe                   : in std_logic;
+		rx_data                     : out std_logic_vector(31 downto 0);
+		rx_first                    : out std_logic;
+		rx_last                     : out std_logic;
+		rx_write                    : out std_logic;
+		rx_almostfull               : in std_logic;
+		rx_inpipe                   : out std_logic;
+		locked                      : out std_logic;
+		error                       : out std_logic;
+		RXP                         : in std_logic_vector(0 to 1);
+		RXN                         : in std_logic_vector(0 to 1);
+		TXP                         : out std_logic_vector(0 to 1);
+		TXN                         : out std_logic_vector(0 to 1);
+		GTXQ0_P                     : in  std_logic;
+		GTXQ0_N                     : in  std_logic;
+		gt0_refclk_in               : in std_logic;
+		gt0_qplllock_in             : in std_logic;
+		gt0_qpllrefclklost_in       : in std_logic;
+		gt0_qpllreset_out           : out std_logic;
+		GT_QPLLOUTCLK_IN            : in std_logic;
+		GT_QPLLOUTREFCLK_IN         : in std_logic
+	);
+end aurora_dual_module;
+
+architecture MAPPED of aurora_dual_module is
+  attribute DowngradeIPIdentifiedWarnings: string;
+  attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes";
+  attribute core_generation_info           : string;
+  attribute core_generation_info of MAPPED : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=40000,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=true,c_ufc=false,flow_mode=None,interface_mode=Streaming,dataflow_config=Duplex}";
+
+-- Parameter Declarations --
+
+    constant DLY : time := 1 ns;
+
+-- External Register Declarations --
+
+    signal HARD_ERR_Buffer    : std_logic;
+    signal SOFT_ERR_Buffer    : std_logic;
+signal LANE_UP_Buffer     : std_logic_vector(0 to 1);
+    signal CHANNEL_UP_Buffer  : std_logic;
+signal TXP_Buffer         : std_logic_vector(0 to 1);
+signal TXN_Buffer         : std_logic_vector(0 to 1);
+
+-- Internal Register Declarations --
+
+    signal gt_reset_i         : std_logic;
+    signal system_reset_i     : std_logic;
+    signal sysreset_vio_i     : std_logic;
+    signal sysreset_i         : std_logic;
+    signal gtreset_vio_i      : std_logic;
+    signal gtreset_vio_o      : std_logic;
+    signal loopback_vio_i     : std_logic_vector(2 downto 0);
+    signal loopback_vio_o     : std_logic_vector(2 downto 0);
+
+-- Wire Declarations --
+
+    -- Stream TX Interface
+
+signal tx_d_i             : std_logic_vector(0 to 31);
+signal tx_rem_i           : std_logic_vector(0 to 1);
+    signal tx_src_rdy_n_i     : std_logic;
+    signal tx_sof_n_i         : std_logic;
+    signal tx_eof_n_i         : std_logic;
+
+    signal tx_dst_rdy_n_i     : std_logic;
+
+    -- LocalLink RX Interface
+
+signal rx_d_i             : std_logic_vector(0 to 31);
+signal rx_rem_i           : std_logic_vector(0 to 1) := (others => '1');
+    signal rx_src_rdy_n_i     : std_logic;
+    signal rx_sof_n_i         : std_logic;
+    signal rx_eof_n_i         : std_logic;
+
+
+    -- Native Flow Control TX Interface
+
+    signal nfc_req_n_i        : std_logic;
+    signal nfc_nb_i           : std_logic_vector(0 to 3);
+    signal nfc_ack_n_i        : std_logic;
+
+    -- Native Flow Control RX Interface
+    signal rx_snf_i           : std_logic;
+    signal rx_fc_nb_i         : std_logic_vector(0 to 3);
+    signal rx_fc_nb_int        : std_logic_vector(0 to 3);
+
+    -- User Flow Control TX Interface
+
+    signal ufc_tx_req_n_i     : std_logic;
+    signal ufc_tx_ms_i        : std_logic_vector(0 to 2);
+    signal ufc_tx_ack_n_i     : std_logic;
+
+    -- User Flow Control RX Inteface
+
+signal ufc_rx_data_i      : std_logic_vector(0 to 31);
+signal ufc_rx_rem_i       : std_logic_vector(0 to 1);
+    signal ufc_rx_src_rdy_n_i : std_logic;
+    signal ufc_rx_sof_n_i     : std_logic;
+    signal ufc_rx_eof_n_i     : std_logic;
+   
+
+    -- Error Detection Interface
+
+    signal hard_err_i       : std_logic;
+    signal soft_err_i       : std_logic;
+    signal frame_err_i      : std_logic;
+    -- Status
+
+    signal channel_up_i       : std_logic;
+    signal channel_up_r       : std_logic;
+    signal channel_up_r_vio   : std_logic;
+signal lane_up_i          : std_logic_vector(0 to 1);
+
+    -- Clock Compensation Control Interface
+
+    signal warn_cc_i          : std_logic;
+
+    -- System Interface
+
+    signal pll_not_locked_i   : std_logic;
+    signal pll_not_locked_ila : std_logic;
+    signal user_clk_i         : std_logic;
+    signal reset_i            : std_logic;
+    signal power_down_i       : std_logic;
+    signal loopback_i         : std_logic_vector(2 downto 0);
+    signal tx_lock_i          : std_logic;
+    signal link_reset_i       : std_logic := '0';
+    signal link_reset_ila     : std_logic := '0';
+    signal rx_resetdone_i     : std_logic;
+    signal tx_resetdone_i     : std_logic;
+    signal tx_resetdone_ila   : std_logic;
+    attribute keep            : string;
+    signal init_clk_i         : std_logic;
+    attribute keep of init_clk_i  : signal is "true";
+signal daddr_in_i         : std_logic_vector(8 downto 0);
+signal dclk_in_i          : std_logic;
+signal den_in_i           : std_logic;
+signal di_in_i            : std_logic_vector(15 downto 0);
+signal drdy_out_unused_i  : std_logic;
+signal drpdo_out_unused_i : std_logic_vector(15 downto 0);
+signal dwe_in_i           : std_logic;
+signal daddr_in_LANE1_i         : std_logic_vector(8 downto 0);
+signal dclk_in_LANE1_i          : std_logic;
+signal den_in_LANE1_i           : std_logic;
+signal di_in_LANE1_i            : std_logic_vector(15 downto 0);
+signal drdy_out_LANE1_unused_i  : std_logic;
+signal drpdo_out_LANE1_unused_i : std_logic_vector(15 downto 0);
+signal dwe_in_LANE1_i           : std_logic;
+    --Frame check signals
+signal tied_to_ground_i    :   std_logic;  
+signal tied_to_gnd_vec_i   :   std_logic_vector(0 to 31);
+
+   -- TX AXI PDU I/F signals
+signal tx_data_i           :   std_logic_vector(0 to 31);
+   signal tx_tvalid_i         :   std_logic;
+   signal tx_tready_i         :   std_logic;
+
+signal tx_tkeep_i          :   std_logic_vector(0 to 3);
+   signal tx_tlast_i          :   std_logic;
+   -- RX AXI PDU I/F signals
+signal rx_data_i           :   std_logic_vector(0 to 31);
+   signal rx_tvalid_i         :   std_logic;
+signal rx_tkeep_i          :   std_logic_vector(0 to 3);
+   signal rx_tlast_i          :   std_logic;
+
+    -- TX AXI UFC I/F signals
+signal axi_ufc_tx_ms_i     :   std_logic_vector(0 to 2);
+   signal axi_ufc_tx_req_n_i  :   std_logic;
+   signal axi_ufc_tx_ack_n_i  :   std_logic;
+
+    -- RX AXI UFC I/F signals
+signal axi_ufc_rx_data_i   :   std_logic_vector(0 to 31);
+signal axi_ufc_rx_rem_i    :   std_logic_vector(0 to 3);
+   signal axi_ufc_rx_src_rdy_n_i  :   std_logic;
+   signal axi_ufc_rx_eof_n_i  :   std_logic;
+
+    -- TX AXI NFC I/F signals
+    signal axi_nfc_nb_i       :   std_logic_vector(0 to 3);
+    signal axi_nfc_req_n_i    :   std_logic;
+    signal axi_nfc_ack_n_i    :   std_logic;
+
+
+
+
+
+    --SLACK Registers
+    signal lane_up_r          : std_logic_vector(0 to 1);
+    signal lane_up_r2         : std_logic_vector(0 to 1);
+    signal drpclk_i           :   std_logic;
+
+-- Component Declarations --
+
+    component BUFG is
+        port (
+
+                O : out std_ulogic;
+                I : in  std_ulogic
+
+             );
+    end component;
+
+
+   -- AXI Shim modules
+   component aurora_dual_LL_TO_AXI_EXDES is
+   generic
+   (
+    DATA_WIDTH  : integer :=   16;      -- DATA bus width
+    USE_UFC_REM : integer :=   0;       -- UFC REM bus width identifier
+    STRB_WIDTH  : integer :=   2;       -- STROBE bus width
+    USE_4_NFC   : integer :=   0;       --  0 => PDU, 1 => NFC, 2 => UFC
+    REM_WIDTH   : integer :=   1        -- REM bus width
+   );  
+
+   port
+   (
+
+    ----------------------  AXI4-S Interface -------------------------------
+    AXI4_S_OP_TDATA                 : out   std_logic_vector (0 to DATA_WIDTH-1);
+    AXI4_S_OP_TKEEP                 : out   std_logic_vector (0 to STRB_WIDTH-1);
+    AXI4_S_OP_TVALID                : out   std_logic;
+    AXI4_S_OP_TLAST                 : out   std_logic;
+    AXI4_S_IP_TREADY                : in    std_logic;
+
+    ----------------------  LocalLink Interface ----------------------------
+    LL_IP_DATA                      : in    std_logic_vector (0 to DATA_WIDTH-1);
+    LL_IP_REM                       : in    std_logic_vector (0 to REM_WIDTH-1);
+    LL_IP_SRC_RDY_N                 : in    std_logic;
+    LL_IP_SOF_N                     : in    std_logic;
+    LL_IP_EOF_N                     : in    std_logic;
+    LL_OP_DST_RDY_N                 : out   std_logic
+
+   );
+   end component;
+
+   component aurora_dual_AXI_TO_LL_EXDES is
+   generic
+   (
+    DATA_WIDTH  : integer :=   16;      -- DATA bus width
+    STRB_WIDTH  : integer :=   2;       -- STROBE bus width
+    REM_WIDTH   : integer :=   1;       -- REM bus width
+    USE_UFC_REM : integer :=   0        -- UFC REM bus width identifier
+   );  
+
+   port
+   (
+
+     ----------------------  AXI4-S Interface -------------------------------
+     AXI4_S_IP_TX_TDATA              : in    std_logic_vector (0 to DATA_WIDTH-1);
+     AXI4_S_IP_TX_TKEEP              : in    std_logic_vector (0 to STRB_WIDTH-1);
+     AXI4_S_IP_TX_TVALID             : in    std_logic;
+     AXI4_S_IP_TX_TLAST              : in    std_logic;
+     AXI4_S_OP_TX_TREADY             : out   std_logic;
+
+     ----------------------  LocalLink Interface ----------------------------
+     LL_OP_DATA                      : out   std_logic_vector (0 to DATA_WIDTH-1);
+     LL_OP_REM                       : out   std_logic_vector (0 to REM_WIDTH -1);
+     LL_OP_SRC_RDY_N                 : out   std_logic;
+     LL_OP_SOF_N                     : out   std_logic;
+     LL_OP_EOF_N                     : out   std_logic;
+     LL_IP_DST_RDY_N                 : in    std_logic;
+
+     ----------------------  System Interface ----------------------------
+     USER_CLK                        : in    std_logic;
+     RESET                           : in    std_logic;
+     CHANNEL_UP                      : in    std_logic
+
+   );
+   end component;
+   
+
+
+
+    component aurora_dual_support
+        port   (
+         -- TX Stream Interface
+s_axi_tx_tdata         : in  std_logic_vector(0 to 31);
+                s_axi_tx_tvalid        : in  std_logic;
+                s_axi_tx_tready        : out std_logic;
+s_axi_tx_tkeep         : in std_logic_vector(0 to 3);
+                s_axi_tx_tlast         : in  std_logic;
+
+         -- RX Stream Interface
+m_axi_rx_tdata         : out std_logic_vector(0 to 31);
+m_axi_rx_tkeep         : out std_logic_vector(0 to 3);
+                m_axi_rx_tvalid        : out std_logic;
+                m_axi_rx_tlast         : out std_logic;
+        -- Native Flow Control TX Interface
+                s_axi_nfc_req          : in std_logic;
+                s_axi_nfc_nb           : in std_logic_vector(0 to 3);
+                s_axi_nfc_ack          : out std_logic;
+
+        -- Native Flow Control RX Interface
+                m_axi_rx_snf           : out std_logic;
+                m_axi_rx_fc_nb         : out std_logic_vector(0 to 3);
+        -- User Flow Control TX Interface
+                s_axi_ufc_tx_req       : in std_logic;
+                s_axi_ufc_tx_ms        : in std_logic_vector(0 to 2);
+                s_axi_ufc_tx_ack       : out std_logic;
+        -- User Flow Control RX Inteface
+
+m_axi_ufc_rx_tdata     : out std_logic_vector(0 to 31);
+m_axi_ufc_rx_tkeep     : out std_logic_vector(0 to 3);
+                m_axi_ufc_rx_tvalid    : out std_logic;
+                m_axi_ufc_rx_tlast     : out std_logic;
+        -- GT Serial I/O
+
+    rxp                    : in std_logic_vector(0 to 1);
+    rxn                    : in std_logic_vector(0 to 1);
+
+    txp                    : out std_logic_vector(0 to 1);
+    txn                    : out std_logic_vector(0 to 1);
+
+        -- GT Reference Clock Interface
+                gt_refclk1_p    : in std_logic;
+                gt_refclk1_n    : in std_logic;
+        -- Error Detection Interface
+
+                hard_err       : out std_logic;
+                soft_err       : out std_logic;
+               
+                frame_err      : out std_logic;
+
+
+        -- Status
+
+                channel_up       : out std_logic;
+    lane_up                : out std_logic_vector(0 to 1);
+        -- System Interface
+
+                user_clk_out     : out std_logic;
+                sys_reset_out    : out std_logic;
+                gt_reset         : in std_logic;
+                reset            : in std_logic;
+                power_down       : in std_logic;
+                loopback         : in std_logic_vector(2 downto 0);
+                init_clk_p          : in  std_logic; 
+                init_clk_n          : in  std_logic; 
+                init_clk_out        : out std_logic;
+                pll_not_locked_out  : out std_logic;
+                tx_resetdone_out    : out std_logic;
+                rx_resetdone_out    : out std_logic;
+                link_reset_out      : out std_logic;
+
+drpclk_in                                                   : in   std_logic;
+drpaddr_in                              : in   std_logic_vector(8 downto 0);
+drpdi_in                                : in   std_logic_vector(15 downto 0);
+drpdo_out                               : out  std_logic_vector(15 downto 0);
+drpen_in                                : in   std_logic;
+drprdy_out                              : out  std_logic;
+drpwe_in                                : in   std_logic;
+drpaddr_in_lane1                              : in   std_logic_vector(8 downto 0);
+drpdi_in_lane1                                : in   std_logic_vector(15 downto 0);
+drpdo_out_lane1                               : out  std_logic_vector(15 downto 0);
+drpen_in_lane1                                : in   std_logic;
+drprdy_out_lane1                              : out  std_logic;
+drpwe_in_lane1                                : in   std_logic;
+   	
+
+                tx_lock          : out std_logic;
+		sysclk_in                : in std_logic;  --// Modified
+		gt0_refclk_in            : in std_logic;  --// Modified
+		gt0_qplllock_in          : in std_logic;  --// Modified
+		gt0_qpllrefclklost_in    : in std_logic;  --// Modified
+		gt0_qpllreset_out        : out std_logic;  --// Modified
+		GT_QPLLOUTCLK_IN         : in std_logic;  --// Modified
+		GT_QPLLOUTREFCLK_IN      : in std_logic  --// Modified
+            );
+
+    end component;
+
+	
+	
+
+
+signal tx_allowed_S              :   std_logic;
+signal tx_data_S                 :   std_logic_vector(31 downto 0);
+signal insertUFC_word_S          :   std_logic_vector(31 downto 0);
+signal insertUFC_S               :   std_logic;
+
+attribute mark_debug : string;
+		
+-- attribute mark_debug of pll_not_locked_i : signal is "true";
+-- attribute mark_debug of power_down_i : signal is "true";
+-- attribute mark_debug of tx_lock_i : signal is "true";
+-- attribute mark_debug of rx_resetdone_i : signal is "true";
+-- attribute mark_debug of tx_resetdone_i : signal is "true";
+-- attribute mark_debug of lane_up_r2 : signal is "true";
+-- attribute mark_debug of hard_err_i : signal is "true";
+-- attribute mark_debug of soft_err_i : signal is "true";
+-- attribute mark_debug of frame_err_i : signal is "true";
+attribute mark_debug of lane_up_i : signal is "true";
+attribute mark_debug of locked : signal is "true";
+-- attribute mark_debug of channel_up_i : signal is "true";
+-- attribute mark_debug of gt0_qplllock_in : signal is "true";
+-- attribute mark_debug of gt0_qpllrefclklost_in : signal is "true";
+-- attribute mark_debug of gt0_qpllreset_out : signal is "true";
+-- attribute mark_debug of system_reset_i : signal is "true";
+-- attribute mark_debug of reset_i : signal is "true";
+-- attribute mark_debug of gtreset_vio_o : signal is "true";
+
+attribute mark_debug of tx_allowed_S : signal is "true";
+attribute mark_debug of tx_data_S : signal is "true";
+attribute mark_debug of nfc_req_n_i : signal is "true";
+attribute mark_debug of nfc_ack_n_i : signal is "true";
+attribute mark_debug of nfc_nb_i : signal is "true";
+
+attribute mark_debug of tx_write : signal is "true";
+attribute mark_debug of tx_data : signal is "true";
+attribute mark_debug of tx_first : signal is "true";
+attribute mark_debug of tx_last : signal is "true";
+attribute mark_debug of tx_allowed : signal is "true";
+attribute mark_debug of rx_data : signal is "true";
+attribute mark_debug of rx_write : signal is "true";
+attribute mark_debug of rx_first : signal is "true";
+attribute mark_debug of rx_last : signal is "true";
+attribute mark_debug of rx_almostfull : signal is "true";
+attribute mark_debug of rx_rem_i : signal is "true";
+
+attribute mark_debug of tx_inpipe : signal is "true";
+attribute mark_debug of rx_inpipe : signal is "true";
+attribute mark_debug of insertUFC_S : signal is "true";
+attribute mark_debug of ufc_tx_req_n_i : signal is "true";
+attribute mark_debug of ufc_tx_ack_n_i : signal is "true";
+attribute mark_debug of ufc_rx_src_rdy_n_i : signal is "true";
+attribute mark_debug of ufc_rx_sof_n_i : signal is "true";
+attribute mark_debug of ufc_rx_eof_n_i : signal is "true";
+attribute mark_debug of ufc_rx_data_i : signal is "true";
+
+	  
+	  
+begin
+
+tx_allowed <= tx_allowed_S;
+tx_allowed_S <= '1' when tx_dst_rdy_n_i='0' else '0';
+tx_src_rdy_n_i <= '0' when tx_write='1' else '1';
+reset_i <= reset;
+gtreset_vio_o <= reset;
+user_clock <= user_clk_i;
+rx_write <= '1' when rx_src_rdy_n_i='0' else '0';
+rx_first <= '1' when rx_sof_n_i='0' else '0';
+rx_last <= '1' when rx_eof_n_i='0' else '0';
+loopback_vio_o <=   "000"; --// Modified 000
+tx_data_S <= insertUFC_word_S when insertUFC_S='1' else tx_data;
+gendata: for i in 0 to 31 generate
+tx_d_i(i) <= tx_data_S(i);
+rx_data(i) <= rx_d_i(i);
+end generate;
+tx_rem_i <= (others => '1');
+tx_sof_n_i<= '0' when tx_first='1' else '1';
+tx_eof_n_i<= '0' when tx_last='1' else '1';
+error <= '1' when (HARD_ERR_Buffer='1') or (SOFT_ERR_Buffer='1') else '0';
+locked <= '1' when (LANE_UP_Buffer="11") and (CHANNEL_UP_Buffer='1') else '0';
+
+TXP <= TXP_Buffer;
+TXN <= TXN_Buffer;
+init_clk_i <= stable_clock;
+drpclk_i <= stable_clock;
+-- drpclk_bufg : BUFG
+-- port map 
+  -- (
+	-- I  => stable_clock,
+	-- O  => drpclk_i
+  -- );
+
+process (user_clk_i)
+variable retrycount_V : std_logic_vector(11 downto 0);
+begin
+	if (user_clk_i 'event and user_clk_i = '1') then
+		if nfc_req_n_i='0' then
+			retrycount_V := (others => '0');
+			if nfc_ack_n_i='0' then
+				nfc_req_n_i <= '1';
+			end if;
+		elsif (rx_almostfull='1') then
+			nfc_nb_i <= (others => '1');
+			if retrycount_V(retrycount_V'left)='1' then
+				nfc_req_n_i <= '0';
+			else
+				retrycount_V := retrycount_V+1;
+			end if;
+		else
+			nfc_nb_i <= (others => '0');
+			if rx_src_rdy_n_i='0' then
+				retrycount_V := (others => '0');
+			end if;
+			if retrycount_V(retrycount_V'left)='1' then
+				nfc_req_n_i <= '0';
+			else
+				retrycount_V := retrycount_V+1;
+			end if;
+		end if;
+	end if;
+end process;  
+
+ufc_tx_ms_i <= "001";
+process (user_clk_i)
+variable retrycount_V : std_logic_vector(12 downto 0);
+variable busy_V : std_logic := '0';
+variable tx_insert_inpipe0_V : std_logic := '0';
+begin
+	if (user_clk_i 'event and user_clk_i = '1') then
+		insertUFC_S <= '0';
+		if (tx_write='1') and (tx_allowed_S='1') and (tx_first='1') then
+			busy_V := '1';
+		elsif (tx_write='1') and (tx_allowed_S='1') and (tx_last='1') then
+			busy_V := '0';
+		end if;
+		if ufc_tx_req_n_i='0' then
+			if ufc_tx_ack_n_i='0' then
+				ufc_tx_req_n_i <= '1';
+				insertUFC_S <= '1';
+			end if;
+		elsif tx_inpipe='0' then
+			insertUFC_word_S <= x"00000000";
+			if (busy_V='0') and (tx_write='0') and (tx_allowed_S='1') then
+				if tx_insert_inpipe0_V='0' then
+					retrycount_V := (others => '0');
+					ufc_tx_req_n_i <= '0';
+					tx_insert_inpipe0_V := '1';
+				elsif retrycount_V(retrycount_V'left)='1' then
+					retrycount_V := (others => '0');
+					ufc_tx_req_n_i <= '0';
+					tx_insert_inpipe0_V := '1';
+				else
+					retrycount_V := retrycount_V+1;
+				end if;
+			end if;
+		else
+			insertUFC_word_S <= x"00000001";
+			if tx_insert_inpipe0_V='1' then
+				tx_insert_inpipe0_V := '0';
+				retrycount_V := (others => '0');
+				ufc_tx_req_n_i <= '0';
+				tx_insert_inpipe0_V := '0';
+			else
+				if retrycount_V(retrycount_V'left)='1' then
+					retrycount_V := (others => '0');
+					ufc_tx_req_n_i <= '0';
+					tx_insert_inpipe0_V := '0';
+				else
+					retrycount_V := retrycount_V+1;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;	
+
+process (user_clk_i)
+begin
+	if (user_clk_i 'event and user_clk_i = '1') then
+		if (ufc_rx_src_rdy_n_i='0') and (ufc_rx_sof_n_i='0') and (ufc_rx_eof_n_i='0') then
+			rx_inpipe <= ufc_rx_data_i(0);
+		end if;
+	end if;
+end process;
+
+    tied_to_ground_i    <= '0';
+
+    process (user_clk_i)
+    begin
+      if (user_clk_i 'event and user_clk_i = '1') then
+        lane_up_r    <=  lane_up_i;
+        lane_up_r2   <=  lane_up_r;
+      end if;
+    end process;
+
+
+
+
+
+    -- Register User I/O --
+
+    -- Register User Outputs from core.
+
+    process (user_clk_i)
+
+    begin
+
+        if (user_clk_i 'event and user_clk_i = '1') then
+
+            HARD_ERR_Buffer  <= hard_err_i;
+            SOFT_ERR_Buffer  <= soft_err_i;
+            LANE_UP_Buffer     <= lane_up_i;
+            CHANNEL_UP_Buffer  <= channel_up_i;
+
+        end if;
+
+    end process;
+
+    -- System Interface
+
+    power_down_i     <= '0';
+
+    process (user_clk_i)
+    begin
+        if (user_clk_i 'event and user_clk_i = '1') then
+            channel_up_r  <= channel_up_i;
+        end if;
+    end process;
+
+
+daddr_in_i  <=  (others=>'0');
+dclk_in_i   <=  '0';
+den_in_i    <=  '0';
+di_in_i     <=  (others=>'0');
+dwe_in_i    <=  '0';
+daddr_in_LANE1_i  <=  (others=>'0');
+dclk_in_LANE1_i   <=  '0';
+den_in_LANE1_i    <=  '0';
+di_in_LANE1_i     <=  (others=>'0');
+dwe_in_LANE1_i    <=  '0';
+    -- _______________________________ Module Instantiations ________________________--
+
+
+    --_____________________________ RX AXI SHIM _______________________________
+    frame_chk_axi_to_ll_pdu_i : aurora_dual_AXI_TO_LL_EXDES
+    generic map
+    (
+       DATA_WIDTH           => 32,
+       STRB_WIDTH           => 4,
+       REM_WIDTH            => 2,
+       USE_UFC_REM          => 0
+    )
+    port map
+    (
+      -- AXI4-S input signals
+      AXI4_S_IP_TX_TVALID  => rx_tvalid_i,
+      AXI4_S_OP_TX_TREADY  => OPEN,
+      AXI4_S_IP_TX_TDATA   => rx_data_i,
+      AXI4_S_IP_TX_TKEEP   => rx_tkeep_i,
+      AXI4_S_IP_TX_TLAST   => rx_tlast_i,
+
+      -- LocalLink output Interface
+      LL_OP_DATA           => rx_d_i,
+      LL_OP_SOF_N          => rx_sof_n_i,
+      LL_OP_EOF_N          => rx_eof_n_i,
+      LL_OP_REM            => rx_rem_i,
+      LL_OP_SRC_RDY_N      => rx_src_rdy_n_i,
+      LL_IP_DST_RDY_N      => tied_to_ground_i,
+
+      -- System Interface
+      USER_CLK              => user_clk_i,      
+      RESET                 => system_reset_i,
+      CHANNEL_UP            => channel_up_r
+     );
+
+
+    frame_chk_axi_to_ll_ufc_i : aurora_dual_AXI_TO_LL_EXDES
+    generic map
+    (
+       DATA_WIDTH           => 32,
+       STRB_WIDTH           => 4,
+       REM_WIDTH            => 2,
+       USE_UFC_REM          => 1
+    )
+    port map
+    (
+       -- AXI4-S input signals
+      AXI4_S_IP_TX_TVALID   => axi_ufc_rx_src_rdy_n_i,
+      AXI4_S_OP_TX_TREADY   => OPEN,
+      AXI4_S_IP_TX_TDATA    => axi_ufc_rx_data_i,
+      AXI4_S_IP_TX_TKEEP    => axi_ufc_rx_rem_i,
+      AXI4_S_IP_TX_TLAST    => axi_ufc_rx_eof_n_i,
+
+      -- LocalLink output Interface
+      LL_OP_DATA            => ufc_rx_data_i,
+      LL_OP_SOF_N           => ufc_rx_sof_n_i,
+      LL_OP_EOF_N           => ufc_rx_eof_n_i,
+      LL_OP_REM             => ufc_rx_rem_i,
+      LL_OP_SRC_RDY_N       => ufc_rx_src_rdy_n_i,
+      LL_IP_DST_RDY_N       => tied_to_ground_i,
+
+      -- System Interface
+      USER_CLK              => user_clk_i,      
+      RESET                 => system_reset_i,
+      CHANNEL_UP            => channel_up_r
+    );
+
+    --_____________________________ TX AXI SHIM _______________________________
+    frame_gen_ll_to_axi_pdu_i : aurora_dual_LL_TO_AXI_EXDES
+    generic map
+    (
+       DATA_WIDTH           => 32,
+       STRB_WIDTH           => 4,
+       USE_4_NFC            => 0,
+       REM_WIDTH            => 2
+    )
+
+    port map
+    (
+      LL_IP_DATA            => tx_d_i,
+      LL_IP_SOF_N           => tx_sof_n_i,
+      LL_IP_EOF_N           => tx_eof_n_i,
+      LL_IP_REM             => tx_rem_i,
+      LL_IP_SRC_RDY_N       => tx_src_rdy_n_i,
+      LL_OP_DST_RDY_N       => tx_dst_rdy_n_i,
+
+      AXI4_S_OP_TVALID      => tx_tvalid_i,
+      AXI4_S_OP_TDATA       => tx_data_i,
+      AXI4_S_OP_TKEEP       => tx_tkeep_i,
+      AXI4_S_OP_TLAST       => tx_tlast_i,
+      AXI4_S_IP_TREADY      => tx_tready_i
+
+    );
+
+    frame_gen_ll_to_axi_ufc_i : aurora_dual_LL_TO_AXI_EXDES
+    generic map
+    (
+       DATA_WIDTH           => 3,
+       USE_UFC_REM          => 1,     
+       STRB_WIDTH           => 4,
+       USE_4_NFC            => 2,
+       REM_WIDTH            => 2
+    )
+
+    port map
+    (
+      LL_IP_DATA            => ufc_tx_ms_i,
+      LL_IP_SOF_N           => tied_to_ground_i,
+      LL_IP_EOF_N           => tied_to_ground_i,
+LL_IP_REM             => "00",
+      LL_IP_SRC_RDY_N       => ufc_tx_req_n_i,
+      LL_OP_DST_RDY_N       => ufc_tx_ack_n_i,
+
+      -- AXI4-S output signals
+      AXI4_S_OP_TVALID      => axi_ufc_tx_req_n_i,
+      AXI4_S_OP_TDATA       => axi_ufc_tx_ms_i,
+      AXI4_S_OP_TKEEP       => OPEN,
+      AXI4_S_OP_TLAST       => OPEN,
+      AXI4_S_IP_TREADY      => axi_ufc_tx_ack_n_i
+    );
+
+    frame_gen_ll_to_axi_nfc_i : aurora_dual_LL_TO_AXI_EXDES
+    generic map
+    (
+       DATA_WIDTH           => 4,
+       STRB_WIDTH           => 4,
+       USE_4_NFC            => 1,
+       REM_WIDTH            => 2
+    )
+
+    port map
+    (
+      LL_IP_DATA            => nfc_nb_i,
+      LL_IP_SOF_N           => tied_to_ground_i,
+      LL_IP_EOF_N           => tied_to_ground_i,
+LL_IP_REM             => "00",
+      LL_IP_SRC_RDY_N       => nfc_req_n_i,
+      LL_OP_DST_RDY_N       => nfc_ack_n_i,
+
+      -- AXI4-S output signals
+      AXI4_S_OP_TVALID      => axi_nfc_req_n_i,
+      AXI4_S_OP_TDATA       => axi_nfc_nb_i,
+      AXI4_S_OP_TKEEP       => OPEN,
+      AXI4_S_OP_TLAST       => OPEN,
+      AXI4_S_IP_TREADY      => axi_nfc_ack_n_i
+     
+    );
+
+    -- Module Instantiations --
+    aurora_module_i : aurora_dual_support
+        port map   (
+        -- AXI TX Interface
+                   s_axi_tx_tdata          => tx_data_i,
+                   s_axi_tx_tkeep          => tx_tkeep_i,
+                   s_axi_tx_tvalid         => tx_tvalid_i,
+                   s_axi_tx_tlast          => tx_tlast_i,
+                   s_axi_tx_tready         => tx_tready_i,
+
+        -- AXI RX Interface
+                   m_axi_rx_tdata          => rx_data_i,
+                   m_axi_rx_tkeep          => rx_tkeep_i,
+                   m_axi_rx_tvalid         => rx_tvalid_i,
+                   m_axi_rx_tlast          => rx_tlast_i,
+
+        -- Native Flow Control TX Interface
+                    s_axi_nfc_req          => axi_nfc_req_n_i,
+                    s_axi_nfc_nb           => axi_nfc_nb_i,
+                    s_axi_nfc_ack          => axi_nfc_ack_n_i,
+
+        -- Native Flow Control RX Interface
+            	    m_axi_rx_snf           => rx_snf_i,
+                    m_axi_rx_fc_nb         => rx_fc_nb_int,
+        -- User Flow Control TX Interface
+                    s_axi_ufc_tx_req       => axi_ufc_tx_req_n_i,
+                    s_axi_ufc_tx_ms        => axi_ufc_tx_ms_i,
+                    s_axi_ufc_tx_ack       => axi_ufc_tx_ack_n_i,
+        -- User Flow Control RX Inteface
+                    m_axi_ufc_rx_tdata     => axi_ufc_rx_data_i,
+                    m_axi_ufc_rx_tkeep     => axi_ufc_rx_rem_i,
+                    m_axi_ufc_rx_tvalid    => axi_ufc_rx_src_rdy_n_i,
+                    m_axi_ufc_rx_tlast     => axi_ufc_rx_eof_n_i,
+        -- GT Serial I/O
+                    rxp              => RXP,
+                    rxn              => RXN,
+                    txp              => TXP_Buffer,
+                    txn              => TXN_Buffer,
+
+        -- GT Reference Clock Interface
+                   gt_refclk1_p    => GTXQ0_P,
+                   gt_refclk1_n    => GTXQ0_N,
+ 
+
+        -- Error Detection Interface
+
+                    hard_err       => hard_err_i,
+                    soft_err       => soft_err_i,
+                    frame_err      => frame_err_i,
+
+        -- Status
+
+                    channel_up       => channel_up_i,
+                    lane_up          => lane_up_i,
+
+        -- System Interface
+
+                    user_clk_out     => user_clk_i,
+                    sys_reset_out    => system_reset_i,
+                    reset            => reset_i,
+                    power_down       => power_down_i,
+                    loopback         => loopback_vio_o,
+                    gt_reset         => gtreset_vio_o,
+                    init_clk_p        => '1',
+                    init_clk_n        => '0',
+                    init_clk_out      => open,
+            	    pll_not_locked_out => pll_not_locked_i,
+            	    tx_resetdone_out   => tx_resetdone_i,
+            	    rx_resetdone_out   => rx_resetdone_i,
+            	    link_reset_out     => link_reset_i,
+
+
+drpclk_in                           => drpclk_i,
+drpaddr_in   => daddr_in_i,
+drpen_in     => den_in_i,
+drpdi_in      => di_in_i,
+drprdy_out   => drdy_out_unused_i,
+drpdo_out  => drpdo_out_unused_i,
+drpwe_in     => dwe_in_i,
+drpaddr_in_lane1   => daddr_in_lane1_i,
+drpen_in_lane1     => den_in_lane1_i,
+drpdi_in_lane1      => di_in_lane1_i,
+drprdy_out_lane1   => drdy_out_lane1_unused_i,
+drpdo_out_lane1  => drpdo_out_lane1_unused_i,
+drpwe_in_lane1     => dwe_in_lane1_i,
+                    tx_lock          => tx_lock_i,
+		sysclk_in => stable_clock,
+		gt0_refclk_in => gt0_refclk_in, --// Modified
+		gt0_qplllock_in => gt0_qplllock_in,  --// Modified
+		gt0_qpllrefclklost_in => gt0_qpllrefclklost_in,  --// Modified
+		gt0_qpllreset_out => gt0_qpllreset_out, --// Modified
+		GT_QPLLOUTCLK_IN => GT_QPLLOUTCLK_IN, --// Modified
+		GT_QPLLOUTREFCLK_IN => GT_QPLLOUTREFCLK_IN --// Modified
+                 );
+
+end MAPPED; 
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support.vhd
new file mode 100644
index 0000000..92d88b0
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support.vhd
@@ -0,0 +1,587 @@
+------------------------------------------------------------------------------/
+-- (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------/
+ library ieee;
+     use ieee.std_logic_1164.all;
+     use ieee.std_logic_misc.all;
+     use IEEE.numeric_std.all;
+     use ieee.std_logic_arith.all;
+     use ieee.std_logic_unsigned.all;
+
+-- synthesis translate_off
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- synthesis translate_on
+
+entity  aurora_dual_support is
+port (
+    -- AXI TX Interface
+    s_axi_tx_tdata         : in  std_logic_vector(0 to 31);
+    s_axi_tx_tkeep         : in std_logic_vector(0 to 3);
+    s_axi_tx_tvalid        : in  std_logic;
+    s_axi_tx_tready        : out std_logic;
+    s_axi_tx_tlast         : in  std_logic;
+
+
+    -- AXI RX Interface
+    m_axi_rx_tdata         : out std_logic_vector(0 to 31);
+    m_axi_rx_tkeep         : out std_logic_vector(0 to 3);
+    m_axi_rx_tvalid        : out std_logic;
+    m_axi_rx_tlast         : out std_logic;
+
+    -- Native Flow Control TX Interface
+    s_axi_nfc_req          : in std_logic;
+ 
+    s_axi_nfc_nb           : in std_logic_vector(0 to 3);
+    s_axi_nfc_ack          : out std_logic;
+
+    -- Native Flow Control RX Interface
+    m_axi_rx_snf           : out std_logic;
+ 
+    m_axi_rx_fc_nb         : out std_logic_vector(0 to 3);
+
+    -- User Flow Control TX Interface
+    s_axi_ufc_tx_req       : in std_logic;
+ 
+    s_axi_ufc_tx_ms        : in std_logic_vector(0 to 2);
+    s_axi_ufc_tx_ack       : out std_logic;
+
+
+    -- User Flow Control RX Inteface
+ 
+    m_axi_ufc_rx_tdata     : out std_logic_vector(0 to 31);
+    m_axi_ufc_rx_tkeep     : out std_logic_vector(0 to 3);
+    m_axi_ufc_rx_tvalid    : out std_logic;
+    m_axi_ufc_rx_tlast     : out std_logic;
+
+
+ 
+    -- GT Serial I/O
+    rxp                    : in std_logic_vector(0 to 1);
+    rxn                    : in std_logic_vector(0 to 1);
+
+    txp                    : out std_logic_vector(0 to 1);
+    txn                    : out std_logic_vector(0 to 1);
+
+    -- GT Reference Clock Interface
+    gt_refclk1_p             : in  std_logic;
+    gt_refclk1_n             : in  std_logic;
+
+    -- Error Detection Interface
+ 
+    frame_err              : out std_logic;
+    hard_err               : out std_logic;
+    soft_err               : out std_logic;
+    channel_up             : out std_logic;
+    lane_up                : out std_logic_vector(0 to 1);
+
+
+
+
+    -- System Interface
+    user_clk_out           : out std_logic;
+    reset                  : in  std_logic;
+    gt_reset               : in  std_logic;
+    sys_reset_out          : out std_logic;
+
+    power_down             : in  std_logic;
+    loopback               : in  std_logic_vector(2 downto 0);
+    tx_lock                : out std_logic;
+    init_clk_p             : in  std_logic;
+    init_clk_n             : in  std_logic;
+    init_clk_out           : out std_logic;
+    tx_resetdone_out       : out std_logic;
+    rx_resetdone_out       : out std_logic;
+    link_reset_out         : out std_logic;
+
+
+    --DRP Ports
+    drpclk_in                         : in   std_logic;
+    drpaddr_in             : in   std_logic_vector(8 downto 0);
+    drpdi_in               : in   std_logic_vector(15 downto 0);
+    drpdo_out              : out  std_logic_vector(15 downto 0);
+    drpen_in               : in   std_logic;
+    drprdy_out             : out  std_logic;
+    drpwe_in               : in   std_logic;
+    drpaddr_in_lane1             : in   std_logic_vector(8 downto 0);
+    drpdi_in_lane1               : in   std_logic_vector(15 downto 0);
+    drpdo_out_lane1              : out  std_logic_vector(15 downto 0);
+    drpen_in_lane1               : in   std_logic;
+    drprdy_out_lane1             : out  std_logic;
+    drpwe_in_lane1               : in   std_logic;
+   
+
+    pll_not_locked_out      : out  std_logic;
+		sysclk_in                : in std_logic;  --// Modified
+		gt0_refclk_in            : in std_logic;  --// Modified
+		gt0_qplllock_in          : in std_logic;  --// Modified
+		gt0_qpllrefclklost_in    : in std_logic;  --// Modified
+		gt0_qpllreset_out        : out std_logic;  --// Modified
+		GT_QPLLOUTCLK_IN         : in std_logic; --// Modified
+		GT_QPLLOUTREFCLK_IN      : in std_logic --// Modified
+ );
+
+end aurora_dual_support;
+
+
+architecture STRUCTURE of aurora_dual_support is
+  attribute core_generation_info           : string;
+  attribute core_generation_info of STRUCTURE : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}";
+
+    component aurora_dual
+        port   (
+         -- TX Stream Interface
+         S_AXI_TX_TDATA         : in  std_logic_vector(0 to 31);
+         S_AXI_TX_TKEEP         : in std_logic_vector(0 to 3);
+         S_AXI_TX_TVALID        : in  std_logic;
+         S_AXI_TX_TREADY        : out std_logic;
+         S_AXI_TX_TLAST         : in  std_logic;
+
+         -- RX Stream Interface
+         M_AXI_RX_TDATA         : out std_logic_vector(0 to 31);
+         M_AXI_RX_TKEEP         : out std_logic_vector(0 to 3);
+         M_AXI_RX_TVALID        : out std_logic;
+         M_AXI_RX_TLAST         : out std_logic;
+         -- Native Flow Control TX Interface
+         S_AXI_NFC_TX_TVALID    : in std_logic;
+         S_AXI_NFC_TX_TDATA     : in std_logic_vector(0 to 3);
+         S_AXI_NFC_TX_TREADY    : out std_logic;
+
+         -- Native Flow Control RX Interface
+         M_AXI_NFC_RX_TVALID    : out std_logic;
+         M_AXI_NFC_RX_TDATA     : out std_logic_vector(0 to 3);
+         -- User Flow Control TX Interface
+
+         S_AXI_UFC_TX_TVALID    : in std_logic;
+         S_AXI_UFC_TX_TDATA     : in std_logic_vector(0 to 2);
+         S_AXI_UFC_TX_TREADY    : out std_logic;
+
+         -- User Flow Control RX Inteface
+         M_AXI_UFC_RX_TDATA     : out std_logic_vector(0 to 31);
+         M_AXI_UFC_RX_TKEEP     : out std_logic_vector(0 to 3);
+         M_AXI_UFC_RX_TVALID    : out std_logic;
+         M_AXI_UFC_RX_TLAST     : out std_logic;
+
+         -- GT Serial I/O
+    RXP                    : in std_logic_vector(0 to 1);
+    RXN                    : in std_logic_vector(0 to 1);
+    TXP                    : out std_logic_vector(0 to 1);
+    TXN                    : out std_logic_vector(0 to 1);
+
+         -- GT Reference Clock Interface
+         gt_refclk1           : in std_logic;
+
+         -- Error Detection Interface
+         HARD_ERR               : out std_logic;
+         SOFT_ERR               : out std_logic;
+
+         -- Status
+         CHANNEL_UP             : out std_logic;
+         LANE_UP             : out std_logic_vector(0 to 1);
+
+               
+         FRAME_ERR              : out std_logic;
+
+
+
+
+         -- System Interface
+
+         USER_CLK         : in std_logic;
+         SYNC_CLK         : in std_logic;
+         GT_RESET         : in std_logic;
+         RESET            : in std_logic;
+         sys_reset_out    : out std_logic;
+         POWER_DOWN       : in std_logic;
+         LOOPBACK         : in std_logic_vector(2 downto 0);
+         TX_OUT_CLK       : out std_logic;
+         INIT_CLK_IN         : in  std_logic; 
+         PLL_NOT_LOCKED      : in  std_logic;
+         TX_RESETDONE_OUT    : out std_logic;
+         RX_RESETDONE_OUT    : out std_logic;
+         LINK_RESET_OUT      : out std_logic;
+
+         drpclk_in                                             : in   std_logic;
+    drpaddr_in             : in   std_logic_vector(8 downto 0);
+    drpdi_in               : in   std_logic_vector(15 downto 0);
+    drpdo_out              : out  std_logic_vector(15 downto 0);
+    drpen_in               : in   std_logic;
+    drprdy_out             : out  std_logic;
+    drpwe_in               : in   std_logic;
+    drpaddr_in_lane1             : in   std_logic_vector(8 downto 0);
+    drpdi_in_lane1               : in   std_logic_vector(15 downto 0);
+    drpdo_out_lane1              : out  std_logic_vector(15 downto 0);
+    drpen_in_lane1               : in   std_logic;
+    drprdy_out_lane1             : out  std_logic;
+    drpwe_in_lane1               : in   std_logic;
+   	
+--------------------{
+--__________COMMON PORTS _______________________________{
+    ------------------------- Common Block - QPLL Ports ------------------------
+      gt0_qplllock_in       :  in  std_logic;
+      gt0_qpllrefclklost_in :  in  std_logic;
+      gt0_qpllreset_out     :  out std_logic;
+  gt_qpllclk_quad1_in      : in  std_logic;  
+  gt_qpllrefclk_quad1_in   : in  std_logic;  
+--____________________________COMMON PORTS _______________________________}
+         TX_LOCK          : out std_logic
+    );
+
+    end component;
+
+
+component aurora_dual_gt_common_wrapper
+port
+(
+--____________________________COMMON PORTS ,_______________________________{
+   gt_qpllclk_quad1_i    : out  std_logic;
+   gt_qpllrefclk_quad1_i : out  std_logic;
+--____________________________COMMON PORTS ,_______________________________}
+    ---------------------- Common Block  - Ref Clock Ports ---------------------
+    gt0_gtrefclk0_common_in    :  in  std_logic;
+    ------------------------- Common Block - QPLL Ports ------------------------
+    gt0_qplllock_out           : out std_logic;
+    gt0_qplllockdetclk_in      : in  std_logic;
+    gt0_qpllrefclklost_out     : out std_logic;
+    gt0_qpllreset_in           : in  std_logic  
+
+);
+end component;
+
+
+  component IBUFDS_GTE2
+  port (
+     O : out std_ulogic;
+     ODIV2 : out std_ulogic;
+     CEB : in std_ulogic;
+     I : in std_ulogic;
+     IB : in std_ulogic
+       );
+  end component;
+
+    component BUFG
+
+        port (
+
+                O : out std_ulogic;
+                I : in  std_ulogic
+
+             );
+
+    end component;
+
+    component aurora_dual_CLOCK_MODULE
+        port (
+                INIT_CLK_P              : in std_logic;
+                INIT_CLK_N              : in std_logic;
+                INIT_CLK_O              : out std_logic; 
+                GT_CLK                  : in std_logic;
+                GT_CLK_LOCKED           : in std_logic;
+                USER_CLK                : out std_logic;
+                SYNC_CLK                : out std_logic;
+                PLL_NOT_LOCKED          : out std_logic
+             );
+    end component;
+
+    component aurora_dual_SUPPORT_RESET_LOGIC
+        port (
+                RESET                  : in std_logic;
+                USER_CLK               : in std_logic;
+                INIT_CLK_IN            : in std_logic;
+                GT_RESET_IN            : in std_logic;
+                SYSTEM_RESET           : out std_logic;
+                GT_RESET_OUT           : out std_logic
+             );
+    end component;
+
+  component  aurora_dual_cdc_sync is
+    generic (
+        C_CDC_TYPE                  : integer range 0 to 2 := 1                 ;
+                                    -- 0 is pulse synch
+                                    -- 1 is level synch
+                                    -- 2 is ack based level sync
+        C_RESET_STATE               : integer range 0 to 1 := 0                 ;
+                                    -- 0 is reset not needed 
+                                    -- 1 is reset needed 
+        C_SINGLE_BIT                : integer range 0 to 1 := 1                 ; 
+                                    -- 0 is bus input
+                                    -- 1 is single bit input
+        C_FLOP_INPUT                : integer range 0 to 1 := 0                 ;
+        C_VECTOR_WIDTH              : integer range 0 to 32 := 32               ;
+        C_MTBF_STAGES               : integer range 0 to 6 := 2                 
+            -- Vector Data witdth
+    );
+
+    port (
+        prmry_aclk                  : in  std_logic                             ;               --
+        prmry_resetn                : in  std_logic                             ;               --
+        prmry_in                    : in  std_logic                             ;               --
+        prmry_vect_in               : in  std_logic_vector                                      --
+                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --
+        prmry_ack                   : out std_logic                             ;
+                                                                                                --
+        scndry_aclk                 : in  std_logic                             ;               --
+        scndry_resetn               : in  std_logic                             ;               --
+                                                                                                --
+        -- Primary to Secondary Clock Crossing                                                  --
+        scndry_out                  : out std_logic                             ;               --
+                                                                                                --
+        scndry_vect_out             : out std_logic_vector                                      --
+                                        (C_VECTOR_WIDTH - 1 downto 0)                           --
+
+    );
+  end component;
+
+------------  Wire declarations
+--------------------{
+    ------------------------- Common Block - QPLL Ports ------------------------
+signal gt0_qplllock_i         : std_logic;
+signal gt0_qpllrefclklost_i   : std_logic;
+signal gt0_qpllreset_i        : std_logic;
+signal                      gt_qpllclk_quad1_i  :  std_logic;
+signal                      gt_qpllrefclk_quad1_i  :  std_logic;
+--------------------}
+signal               gt_refclk1_i    :   std_logic;
+
+signal               tx_out_clk_i            :  std_logic;
+signal               user_clk_i              :  std_logic;
+signal               sync_clk_i              :  std_logic;
+signal               pll_not_locked_i        :  std_logic;
+signal               tx_lock_i               :  std_logic;
+
+signal               init_clk_i              :  std_logic;
+signal               tx_resetdone_i          :  std_logic;
+signal               rx_resetdone_i          :  std_logic;
+signal               link_reset_i            :  std_logic;
+signal               system_reset_i          :  std_logic;
+signal               gt_reset_i              :  std_logic;
+signal               drpclk_i                :  std_logic;
+signal               reset_sync_user_clk     : std_logic;
+signal               gt_reset_sync_init_clk  : std_logic;
+begin
+
+ --*********************************Main Body of Code**********************************
+
+ --// Modified
+      -- IBUFDS_GTE2_CLK1 :  IBUFDS_GTE2
+      -- port map (
+           -- I     => gt_refclk1_p,
+           -- IB    => gt_refclk1_n,
+           -- CEB   => '0',
+           -- O     => gt_refclk1_i,
+           -- ODIV2 => OPEN);
+
+
+  drpclk_i <= drpclk_in;
+
+    -- Instantiate a clock module for clock division
+
+    clock_module_i : aurora_dual_CLOCK_MODULE
+        port map (
+                    INIT_CLK_P          => init_clk_p,
+                    INIT_CLK_N          => init_clk_n,
+                    INIT_CLK_O          => open, --// Modified init_clk_i,
+                    GT_CLK              => tx_out_clk_i,
+                    GT_CLK_LOCKED       => tx_lock_i,
+                    USER_CLK            => user_clk_i,
+                    SYNC_CLK            => sync_clk_i,
+                    PLL_NOT_LOCKED      => pll_not_locked_i
+                 );
+
+  --  outputs
+  init_clk_out          <=  init_clk_i;
+  user_clk_out          <=  user_clk_i;
+  pll_not_locked_out    <=  pll_not_locked_i;
+  tx_lock               <=  tx_lock_i;
+  tx_resetdone_out      <=  tx_resetdone_i;
+  rx_resetdone_out      <=  rx_resetdone_i;
+  link_reset_out        <=  link_reset_i;
+
+
+    reset_sync_user_clk    <= reset;
+    gt_reset_sync_init_clk <= gt_reset;
+
+    support_reset_logic_i : aurora_dual_SUPPORT_RESET_LOGIC
+        port map (
+                   RESET               =>  reset_sync_user_clk,
+                   USER_CLK            =>  user_clk_i,
+                   INIT_CLK_IN         =>  init_clk_i,
+                   GT_RESET_IN         =>  gt_reset_sync_init_clk,
+                   SYSTEM_RESET        =>  system_reset_i,
+                   GT_RESET_OUT        =>  gt_reset_i
+                 );
+
+ --// Modified				 
+-- -------- instance of _gt_common_wrapper ---{
+-- gt_common_support : aurora_dual_gt_common_wrapper
+
+-- port map
+-- (
+-- --____________________________COMMON PORTS ,_______________________________{
+  -- gt_qpllclk_quad1_i      => gt_qpllclk_quad1_i ,
+  -- gt_qpllrefclk_quad1_i   => gt_qpllrefclk_quad1_i ,
+    -- ---------------------- Common Block  - Ref Clock Ports ---------------------
+      -- gt0_gtrefclk0_common_in  =>  gt_refclk1_i,
+
+    -- ------------------------- Common Block - QPLL Ports ------------------------
+      -- gt0_qplllock_out        => gt0_qplllock_i,
+      -- gt0_qplllockdetclk_in   => init_clk_i,
+      -- gt0_qpllrefclklost_out  => gt0_qpllrefclklost_i ,
+      -- gt0_qpllreset_in  =>  gt0_qpllreset_i 
+-- --____________________________COMMON PORTS ,_______________________________}
+-- );
+init_clk_i <= sysclk_in;  --// Modified
+gt_qpllclk_quad1_i <= GT_QPLLOUTCLK_IN; --// Modified
+gt_qpllrefclk_quad1_i <= GT_QPLLOUTREFCLK_IN; --// Modified
+gt_refclk1_i <= gt0_refclk_in;  --// Modified
+gt0_qplllock_i <= gt0_qplllock_in; --// Modified
+gt0_qpllrefclklost_i <= gt0_qpllrefclklost_in; --// Modified
+gt0_qpllreset_out <= gt0_qpllreset_i; --// Modified
+-------- instance of _gt_common_wrapper ---}
+
+     aurora_dual_i : aurora_dual
+     port map (
+        -- AXI TX Interface
+        s_axi_tx_tdata               => s_axi_tx_tdata,
+        s_axi_tx_tkeep               => s_axi_tx_tkeep,
+        s_axi_tx_tvalid              => s_axi_tx_tvalid,
+        s_axi_tx_tlast               => s_axi_tx_tlast,
+        s_axi_tx_tready              => s_axi_tx_tready,
+
+        -- AXI RX Interface
+        m_axi_rx_tdata               => m_axi_rx_tdata,
+        m_axi_rx_tkeep               => m_axi_rx_tkeep,
+        m_axi_rx_tvalid              => m_axi_rx_tvalid,
+        m_axi_rx_tlast               => m_axi_rx_tlast,
+        -- Native Flow Control TX Interface
+        s_axi_nfc_tx_tvalid          => s_axi_nfc_req,
+        s_axi_nfc_tx_tdata           => s_axi_nfc_nb,
+        s_axi_nfc_tx_tready          => s_axi_nfc_ack,
+
+        -- Native Flow Control RX Interface
+	     m_axi_nfc_rx_tvalid          => m_axi_rx_snf,
+        m_axi_nfc_rx_tdata           => m_axi_rx_fc_nb,
+
+ 
+        -- User Flow Control TX Interface
+        s_axi_ufc_tx_tvalid          => s_axi_ufc_tx_req,
+        s_axi_ufc_tx_tdata           => s_axi_ufc_tx_ms,
+        s_axi_ufc_tx_tready          => s_axi_ufc_tx_ack,
+
+        -- User Flow Control RX Inteface
+        m_axi_ufc_rx_tdata           => m_axi_ufc_rx_tdata,
+        m_axi_ufc_rx_tkeep           => m_axi_ufc_rx_tkeep,
+        m_axi_ufc_rx_tvalid          => m_axi_ufc_rx_tvalid,
+        m_axi_ufc_rx_tlast           => m_axi_ufc_rx_tlast,
+
+        -- GT Serial I/O
+        rxp                          => rxp,
+        rxn                          => rxn,
+        txp                          => txp,
+        txn                          => txn,
+
+        -- GT Reference Clock Interface
+        gt_refclk1                   => gt_refclk1_i,
+        -- Error Detection Interface
+        frame_err                    => frame_err,
+
+        -- Error Detection Interface
+        hard_err                     => hard_err,
+        soft_err                     => soft_err,
+
+        -- Status
+        channel_up                   => channel_up,
+        lane_up                      => lane_up,
+
+
+
+
+        -- System Interface
+        user_clk                     => user_clk_i,
+        sync_clk                     => sync_clk_i,
+        reset                        => system_reset_i,
+        sys_reset_out                => sys_reset_out,
+        power_down                   => power_down,
+        loopback                     => loopback,
+        gt_reset                     => gt_reset_i,
+        tx_lock                      => tx_lock_i,
+        init_clk_in                  => init_clk_i,
+        pll_not_locked               => pll_not_locked_i,
+	tx_resetdone_out             => tx_resetdone_i,
+	rx_resetdone_out             => rx_resetdone_i,
+        link_reset_out               => link_reset_i,
+
+
+        drpclk_in                            => drpclk_i,
+        drpaddr_in                   => drpaddr_in,
+        drpen_in                     => drpen_in,
+        drpdi_in                     => drpdi_in,
+        drprdy_out                   => drprdy_out, 
+        drpdo_out                    => drpdo_out,
+        drpwe_in                     => drpwe_in,
+        drpaddr_in_lane1                   => drpaddr_in_lane1,
+        drpen_in_lane1                     => drpen_in_lane1,
+        drpdi_in_lane1                     => drpdi_in_lane1,
+        drprdy_out_lane1                   => drprdy_out_lane1, 
+        drpdo_out_lane1                    => drpdo_out_lane1,
+        drpwe_in_lane1                     => drpwe_in_lane1,
+--------------------{
+--__________COMMON PORTS _______________________________{
+    ------------------------- Common Block - QPLL Ports ------------------------
+      gt0_qplllock_in        =>  gt0_qplllock_i,
+      gt0_qpllrefclklost_in  =>  gt0_qpllrefclklost_i,
+      gt0_qpllreset_out      =>  gt0_qpllreset_i,
+  gt_qpllclk_quad1_in      => gt_qpllclk_quad1_i ,
+  gt_qpllrefclk_quad1_in   => gt_qpllrefclk_quad1_i ,
+--____________________________COMMON PORTS ,_______________________________}
+--------------------}
+        tx_out_clk                   => tx_out_clk_i
+
+     );
+
+ end STRUCTURE; 
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support_reset_logic.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support_reset_logic.vhd
new file mode 100644
index 0000000..af12dc2
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/aurora_dual_support/aurora_dual_support_reset_logic.vhd
@@ -0,0 +1,220 @@
+ 
+-- (c) Copyright 2008 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+--
+---------------------------------------------------------------------------------------------
+--  AURORA RESET LOGIC
+--
+--
+--  Description: RESET logic using Debouncer
+--
+--        
+
+library IEEE;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_misc.all;
+use ieee.std_logic_1164.all;
+
+-- synthesis translate_off
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+-- synthesis translate_on
+
+entity aurora_dual_SUPPORT_RESET_LOGIC is
+    port (
+
+           RESET                  : in std_logic;
+           USER_CLK               : in std_logic;
+           INIT_CLK_IN            : in std_logic;
+           GT_RESET_IN            : in std_logic;
+           SYSTEM_RESET           : out std_logic;
+           GT_RESET_OUT           : out std_logic
+         );
+
+end aurora_dual_SUPPORT_RESET_LOGIC;
+
+architecture MAPPED of aurora_dual_SUPPORT_RESET_LOGIC is
+  attribute DowngradeIPIdentifiedWarnings: string;
+  attribute DowngradeIPIdentifiedWarnings of MAPPED : architecture is "yes";
+  attribute core_generation_info           : string;
+attribute core_generation_info of MAPPED : architecture is "aurora_dual,aurora_8b10b_v11_0_2,{user_interface=AXI_4_Streaming,backchannel_mode=Sidebands,c_aurora_lanes=2,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=1,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=2,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=40000,c_nfc=true,c_nfc_mode=IMM,c_refclk_frequency=80000,c_simplex=false,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC+_Immediate_NFC,interface_mode=Framing,dataflow_config=Duplex}";
+
+-- Parameter Declarations --
+
+    constant DLY : time := 1 ns;
+
+-- Internal Register Declarations --
+
+    signal reset_debounce_r   : std_logic_vector(0 to 3);
+    signal debounce_gt_rst_r  : std_logic_vector(0 to 3) := "0000";
+    signal reset_debounce_r2  : std_logic;
+    signal gt_rst_r           : std_logic;
+    signal tied_to_ground_i   : std_logic;     
+    signal gt_rst_sync        : std_logic;
+
+    attribute ASYNC_REG                     : string;
+    attribute SHIFT_EXTRACT                 : string;
+ 
+    attribute ASYNC_REG of debounce_gt_rst_r: signal is "true";
+    attribute SHIFT_EXTRACT of debounce_gt_rst_r: signal is "no";
+
+-- Component Declarations --
+
+  component  aurora_dual_cdc_sync_exdes is
+    generic (
+        C_CDC_TYPE                  : integer range 0 to 2 := 1                 ;
+                                    -- 0 is pulse synch
+                                    -- 1 is level synch
+                                    -- 2 is ack based level sync
+        C_RESET_STATE               : integer range 0 to 1 := 0                 ;
+                                    -- 0 is reset not needed 
+                                    -- 1 is reset needed 
+        C_SINGLE_BIT                : integer range 0 to 1 := 1                 ; 
+                                    -- 0 is bus input
+                                    -- 1 is single bit input
+        C_FLOP_INPUT                : integer range 0 to 1 := 0                 ;
+        C_VECTOR_WIDTH              : integer range 0 to 32 := 32                             ;
+        C_MTBF_STAGES               : integer range 0 to 6 := 2                 
+            -- Vector Data witdth
+    );
+
+    port (
+        prmry_aclk                  : in  std_logic                             ;               --
+        prmry_resetn                : in  std_logic                             ;               --
+        prmry_in                    : in  std_logic                             ;               --
+        prmry_vect_in               : in  std_logic_vector                                      --
+                                        (C_VECTOR_WIDTH - 1 downto 0)           ;               --
+        prmry_ack                   : out std_logic                             ;
+                                                                                                --
+        scndry_aclk                 : in  std_logic                             ;               --
+        scndry_resetn               : in  std_logic                             ;               --
+                                                                                                --
+        -- Primary to Secondary Clock Crossing                                                  --
+        scndry_out                  : out std_logic                             ;               --
+                                                                                                --
+        scndry_vect_out             : out std_logic_vector                                      --
+                                        (C_VECTOR_WIDTH - 1 downto 0)                           --
+
+    );
+
+   end component;
+
+begin
+
+    -- Tie off top level constants.
+    tied_to_ground_i     <= '0';
+
+    -- ___________________________Debouncing circuit for GT_RESET_IN________________________
+-- Reset sync from INIT_CLK to USER_CLK
+
+      gt_rst_r_cdc_sync : aurora_dual_cdc_sync_exdes
+      generic map
+        (
+           c_cdc_type      => 1             ,   
+           c_flop_input    => 1             ,  
+           c_reset_state   => 0             ,  
+           c_single_bit    => 1             ,  
+           c_vector_width  => 2             ,  
+           c_mtbf_stages   => 4               
+         )
+      port map   
+         (
+           prmry_aclk      => INIT_CLK_IN        ,
+           prmry_resetn    => '1'                ,
+           prmry_in        => gt_rst_r           ,
+           prmry_vect_in   => "00"               ,
+           scndry_aclk     => USER_CLK           ,
+           scndry_resetn   => '1'                ,
+           prmry_ack       => open               ,
+           scndry_out      => gt_rst_sync        ,
+           scndry_vect_out => open                     
+          );
+
+
+    -- Debounce the GT_RESET_IN signal using the INIT_CLK
+    process(INIT_CLK_IN)
+    begin
+        if(INIT_CLK_IN'event and INIT_CLK_IN='1') then
+            debounce_gt_rst_r <=  GT_RESET_IN & debounce_gt_rst_r(0 to 2);
+            gt_rst_r  <=   debounce_gt_rst_r(0) and
+                           debounce_gt_rst_r(1) and
+                           debounce_gt_rst_r(2) and
+                           debounce_gt_rst_r(3);
+        end if;
+    end process;
+       
+
+    GT_RESET_OUT  <=   gt_rst_r;
+
+    -- _______________________Debounce the Reset signal________________________ --
+
+    -- Simple Debouncer for Reset button. The debouncer has an
+    -- asynchronous reset tied to GT_RESET_IN. This is primarily for simulation, to ensure
+    -- that unknown values are not driven into the reset line
+    process (USER_CLK, gt_rst_sync)
+    begin
+        if (gt_rst_sync = '1') then
+            reset_debounce_r <= "1111";
+        elsif (USER_CLK 'event and USER_CLK = '1') then
+            reset_debounce_r <= RESET & reset_debounce_r(0 to 2);
+        end if;
+    end process;
+
+    process(USER_CLK)
+    begin
+        if(USER_CLK'event and USER_CLK='1') then
+            reset_debounce_r2 <=  (reset_debounce_r(0) and
+                                  reset_debounce_r(1) and
+                                  reset_debounce_r(2) and
+                                  reset_debounce_r(3));
+        end if;
+    end process;
+
+    SYSTEM_RESET <=  reset_debounce_r2;
+
+end MAPPED;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x18_xilinx/blockmem1x18_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x18_xilinx/blockmem1x18_xilinx.xci
new file mode 100644
index 0000000..27c9002
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x18_xilinx/blockmem1x18_xilinx.xci
@@ -0,0 +1,200 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>blockmem1x18_xilinx</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.3"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     3.10055 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">blockmem1x18_xilinx.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">blockmem1x18_xilinx</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Use_ENB_Pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x96_xilinx/blockmem1x96_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x96_xilinx/blockmem1x96_xilinx.xci
new file mode 100644
index 0000000..b14b2c6
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem1x96_xilinx/blockmem1x96_xilinx.xci
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>blockmem1x96_xilinx</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.3"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     10.67465 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">blockmem1x96_xilinx.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">blockmem1x96_xilinx</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x18_xilinx/blockmem2x18_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x18_xilinx/blockmem2x18_xilinx.xci
new file mode 100644
index 0000000..2656cdd
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x18_xilinx/blockmem2x18_xilinx.xci
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>blockmem2x18_xilinx</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.3"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     3.10055 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">blockmem2x18_xilinx.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">NO_CHANGE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">blockmem2x18_xilinx</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">NO_CHANGE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x96_xilinx/blockmem2x96_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x96_xilinx/blockmem2x96_xilinx.xci
new file mode 100644
index 0000000..37bdcfb
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem2x96_xilinx/blockmem2x96_xilinx.xci
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>blockmem2x96_xilinx</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.3"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     10.67465 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">blockmem2x96_xilinx.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">blockmem2x96_xilinx</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x18_xilinx/blockmem3x18_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x18_xilinx/blockmem3x18_xilinx.xci
new file mode 100644
index 0000000..c3ca32f
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x18_xilinx/blockmem3x18_xilinx.xci
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>blockmem3x18_xilinx</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.3"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     3.10055 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">blockmem3x18_xilinx.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">NO_CHANGE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">blockmem3x18_xilinx</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">NO_CHANGE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x96_xilinx/blockmem3x96_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x96_xilinx/blockmem3x96_xilinx.xci
new file mode 100644
index 0000000..bd17c6d
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem3x96_xilinx/blockmem3x96_xilinx.xci
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>blockmem3x96_xilinx</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.3"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     10.67465 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">blockmem3x96_xilinx.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">blockmem3x96_xilinx</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">96</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem4x18_xilinx/blockmem4x18_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem4x18_xilinx/blockmem4x18_xilinx.xci
new file mode 100644
index 0000000..8dd9f34
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem4x18_xilinx/blockmem4x18_xilinx.xci
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>blockmem4x18_xilinx</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.3"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     3.10055 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">blockmem4x18_xilinx.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">NO_CHANGE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">blockmem4x18_xilinx</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">NO_CHANGE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem5x18_xilinx/blockmem5x18_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem5x18_xilinx/blockmem5x18_xilinx.xci
new file mode 100644
index 0000000..12aeb40
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem5x18_xilinx/blockmem5x18_xilinx.xci
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>blockmem5x18_xilinx</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.3"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     3.10055 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">blockmem5x18_xilinx.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">NO_CHANGE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">blockmem5x18_xilinx</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">NO_CHANGE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem_xilinx/blockmem_xilinx.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem_xilinx/blockmem_xilinx.xci
new file mode 100644
index 0000000..11e0a88
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/blockmem_xilinx/blockmem_xilinx.xci
@@ -0,0 +1,199 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>blockmem_xilinx</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.3"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP     :     3.84935 mW</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">blockmem_xilinx.mem</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">NO_CHANGE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">blockmem_xilinx</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">NO_CHANGE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clock100to200/clock100to200.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clock100to200/clock100to200.xci
new file mode 100644
index 0000000..3cad49e
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clock100to200/clock100to200.xci
@@ -0,0 +1,517 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>clock100to200</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock   Freq (MHz)    Input Jitter (UI)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___100.000______0.000______50.0______130.958_____98.575</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2___200.000______0.000______50.0______114.829_____98.575</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clock100to200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">130.958</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">98.575</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">114.829</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">98.575</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clock100to200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_LOCKED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_RESET" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule100to80M/clockmodule100to80M.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule100to80M/clockmodule100to80M.xci
new file mode 100644
index 0000000..0d23002
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule100to80M/clockmodule100to80M.xci
@@ -0,0 +1,549 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>clockmodule100to80M</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">40.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">66.667</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">65</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">160.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock   Freq (MHz)    Input Jitter (UI)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">8.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">20.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1____40.000______0.000______50.0______174.629____114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2____80.000______0.000______50.0______151.652____114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">CLK_OUT3___100.000______0.000______50.0______144.719____114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">CLK_OUT4___200.000______0.000______50.0______126.455____114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">CLK_OUT5____66.667______0.000______50.0______157.646____114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">CLK_OUT6___160.000______0.000______50.0______131.841____114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clockmodule100to80M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">174.629</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.00</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">151.652</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">144.719</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">126.455</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">157.646</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">65</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">131.841</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">114.212</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clockmodule100to80M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">8.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">20.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_USED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_USED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_USED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.SECONDARY_SOURCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule40Mto80M_1/clockmodule40Mto80M.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule40Mto80M_1/clockmodule40Mto80M.xci
new file mode 100644
index 0000000..7d50fe6
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/clockmodule40Mto80M_1/clockmodule40Mto80M.xci
@@ -0,0 +1,524 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>clockmodule40Mto80M</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">250.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">40.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock   Freq (MHz)    Input Jitter (UI)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary______________40____________0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">24.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">25.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">24.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1____40.000______0.000______50.0______247.096____196.976</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2____80.000______0.000______50.0______200.412____196.976</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">40</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clockmodule40Mto80M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">250.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">247.096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">196.976</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">40</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">200.412</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">196.976</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clockmodule40Mto80M</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">24.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">25.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">24.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">40</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_RESET" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/gtxKintex7FEE80_clockmodule/gtxKintex7FEE80_clockmodule.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/gtxKintex7FEE80_clockmodule/gtxKintex7FEE80_clockmodule.xci
new file mode 100644
index 0000000..29a5be7
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/gtxKintex7FEE80_clockmodule/gtxKintex7FEE80_clockmodule.xci
@@ -0,0 +1,521 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>gtxKintex7FEE80_clockmodule</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.1"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">gtxKintex7FEE80_clockmodule</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">125.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">12.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">12.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">136.213</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">100.585</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">119.661</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">100.585</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">gtxKintex7FEE80_clockmodule</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Global_buffer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock   Freq (MHz)    Input Jitter (UI)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary______________80____________0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___100.000______0.000______50.0______136.213____100.585</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2___200.000______0.000______50.0______119.661____100.585</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">12.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">12.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">125.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem.xcix b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem.xcix
new file mode 100644
index 0000000..cb83cf4
Binary files /dev/null and b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem.xcix differ
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_sem_vio.xcix b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_sem_vio.xcix
new file mode 100644
index 0000000..c0d0ce4
Binary files /dev/null and b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_sem_vio.xcix differ
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_cfg.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_cfg.vhd
new file mode 100644
index 0000000..a144334
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_cfg.vhd
@@ -0,0 +1,250 @@
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/    Core:          sem
+--  \   \        Entity:        sem_sem_cfg
+--  /   /        Filename:      sem_sem_cfg.vhd
+-- /___/   /\    Purpose:       Wrapper file for configuration logic.
+-- \   \  /  \
+--  \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity is a wrapper to encapsulate the FRAME_ECC and ICAP primitives.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- icap_clk                      input  The controller clock, used to clock
+--                                      the configuration logic as well.
+--
+-- icap_o[31:0]                  output ICAP data output.  Synchronous to
+--                                      icap_clk.
+--
+-- icap_csib                     input  ICAP chip select, active low.  Used
+--                                      to enable the ICAP for read or write.
+--                                      Synchronous to icap_clk.
+--
+-- icap_rdwrb                    input  ICAP write select, active low.  Used
+--                                      to select between read or write.
+--                                      Synchronous to icap_clk.
+--
+-- icap_i[31:0]                  input  ICAP data input.  Synchronous to
+--                                      icap_clk.
+--
+-- fecc_crcerr                   output FRAME_ECC status indicating a device
+--                                      CRC check at end of readback cycle
+--                                      has failed.  Synchronous to icap_clk.
+--
+-- fecc_eccerr                   output FRAME_ECC status indicating a frame
+--                                      ECC check at end of frame readback
+--                                      has failed.  Synchronous to icap_clk.
+--
+-- fecc_eccerrsingle             output FRAME_ECC status indicating syndrome
+--                                      appears to be for a single bit error.
+--                                      Synchronous to icap_clk.
+--
+-- fecc_syndromevalid            output FRAME_ECC status indicating syndrome
+--                                      is valid in this cycle.  Synchronous
+--                                      to icap_clk.
+--
+-- fecc_syndrome[12:0]           output FRAME_ECC syndrome.  Synchronous to
+--                                      icap_clk.
+--
+-- fecc_far[25:0]                output FRAME_ECC status showing FAR or EFAR.
+--                                      Synchronous to icap_clk.
+--
+-- fecc_synbit[4:0]              output FRAME_ECC status indicating location
+--                                      of error in a word.  Synchronous to
+--                                      icap_clk.
+--
+-- fecc_synword[6:0]             output FRAME_ECC status indicating location
+--                                      of error word in a frame.  Synchronous
+--                                      to icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- TCQ                           int    Sets the clock-to-out for behavioral
+--                                      descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_cfg
+-- |
+-- +- ICAPE2 (unisim)
+-- |
+-- \- FRAME_ECCE2 (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_cfg is
+port (
+  icap_clk                      : in    std_logic;
+  icap_o                        : out   std_logic_vector(31 downto 0);
+  icap_csib                     : in    std_logic;
+  icap_rdwrb                    : in    std_logic;
+  icap_i                        : in    std_logic_vector(31 downto 0);
+  fecc_crcerr                   : out   std_logic;
+  fecc_eccerr                   : out   std_logic;
+  fecc_eccerrsingle             : out   std_logic;
+  fecc_syndromevalid            : out   std_logic;
+  fecc_syndrome                 : out   std_logic_vector(12 downto 0);
+  fecc_far                      : out   std_logic_vector(25 downto 0);
+  fecc_synbit                   : out   std_logic_vector(4 downto 0);
+  fecc_synword                  : out   std_logic_vector(6 downto 0)
+  );
+end entity sem_sem_cfg;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_cfg is
+
+  ---------------------------------------------------------------------------
+  -- Define local constants.
+  ---------------------------------------------------------------------------
+
+  constant TCQ : time := 1 ps;
+
+  ---------------------------------------------------------------------------
+  -- Declare non-library components.
+  ---------------------------------------------------------------------------
+
+  -- None
+
+  ---------------------------------------------------------------------------
+  -- Declare signals.
+  ---------------------------------------------------------------------------
+
+  -- None
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+  begin
+
+  ---------------------------------------------------------------------------
+  -- Instantiate the FRAME_ECC primitive.
+  ---------------------------------------------------------------------------
+
+  example_frame_ecc : FRAME_ECCE2
+  generic map (
+    FRAME_RBT_IN_FILENAME => "NONE",
+    FARSRC => "EFAR"
+    )
+  port map (
+    CRCERROR => fecc_crcerr,
+    ECCERROR => fecc_eccerr,
+    ECCERRORSINGLE => fecc_eccerrsingle,
+    FAR => fecc_far,
+    SYNBIT => fecc_synbit,
+    SYNDROME => fecc_syndrome,
+    SYNDROMEVALID => fecc_syndromevalid,
+    SYNWORD => fecc_synword
+    );
+
+  ---------------------------------------------------------------------------
+  -- Instantiate the ICAP primitive.
+  ---------------------------------------------------------------------------
+
+  example_icap : ICAPE2
+  generic map (
+    SIM_CFG_FILE_NAME => "NONE",
+    DEVICE_ID => X"FFFFFFFF",
+    ICAP_WIDTH => "X32"
+    )
+  port map (
+    O => icap_o,
+    CLK => icap_clk,
+    CSIB => icap_csib,
+    I => icap_i,
+    RDWRB => icap_rdwrb
+    );
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_example.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_example.vhd
new file mode 100644
index 0000000..282f1e6
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_example.vhd
@@ -0,0 +1,603 @@
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/    Core:          sem
+--  \   \        Entity:        sem_sem_example
+--  /   /        Filename:      sem_sem_example.vhd
+-- /___/   /\    Purpose:       System level design example.
+-- \   \  /  \
+--  \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity is the system level design example, the top level of what is
+-- intended for physical implementation.  This entity is essentially an HDL
+-- netlist of sub-entities used to construct the solution.  The system level
+-- design example is customized by the Vivado IP Catalog.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- clk                           input  System clock; the entire system is
+--                                      synchronized to this signal, which
+--                                      is distributed on a global clock
+--                                      buffer and referred to as icap_clk.
+--
+-- status_heartbeat              output Heartbeat signal for external watch
+--                                      dog timer implementation; pulses
+--                                      when readback runs.  Synchronous to
+--                                      icap_clk.
+--
+-- status_initialization         output Indicates initialization is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_observation            output Indicates observation is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_correction             output Indicates correction is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_classification         output Indicates classification is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_injection              output Indicates injection is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_essential              output Indicates essential error condition.
+--                                      Qualified by de-assertion of the
+--                                      status_classification signal, and
+--                                      is synchronous to icap_clk.
+--
+-- status_uncorrectable          output Indicates uncorrectable error
+--                                      condition. Qualified by de-assertion
+--                                      of the status_correction signal, and
+--                                      is synchronous to icap_clk.
+--
+-- monitor_tx                    output Serial status output.  Synchronous
+--                                      to icap_clk, but received externally
+--                                      by another device as an asynchronous
+--                                      signal, perceived as lower bitrate.
+--                                      Uses 8N1 protocol.
+--
+-- monitor_rx                    input  Serial command input.  Asynchronous
+--                                      signal provided by another device at
+--                                      a lower bitrate, synchronized to the
+--                                      icap_clk and oversampled.  Uses 8N1
+--                                      protocol.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- TCQ                           int    Sets the clock-to-out for behavioral
+--                                      descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_example
+-- |
+-- +- sem (sem_controller)
+-- |
+-- +- sem_sem_cfg
+-- |
+-- +- sem_sem_mon
+-- |
+-- +- sem_sem_hid
+-- |
+-- +- IBUF (unisim)
+-- |
+-- \- BUFGCE (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_example is
+port (
+  clk                           : in    std_logic;
+  status_heartbeat              : out   std_logic;
+  status_initialization         : out   std_logic;
+  status_observation            : out   std_logic;
+  status_correction             : out   std_logic;
+  status_classification         : out   std_logic;
+  status_injection              : out   std_logic;
+  status_essential              : out   std_logic;
+  status_uncorrectable          : out   std_logic;
+  monitor_tx                    : out   std_logic;
+  monitor_rx                    : in    std_logic;
+  disable_all                   : out   std_logic;
+  ADC_selREGS                   : out   std_logic_vector(2 downto 0);
+  disable_tests                 : out   std_logic_vector(3 downto 0);
+  insert_data                   : in    std_logic_vector(7 downto 0);
+  insert_data_available         : in    std_logic;
+  insert_data_read              : out   std_logic
+    );
+end entity sem_sem_example;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_example is
+
+  ---------------------------------------------------------------------------
+  -- Define local constants.
+  ---------------------------------------------------------------------------
+
+  constant TCQ : time := 1 ps;
+
+  ---------------------------------------------------------------------------
+  -- Declare non-library components.
+  ---------------------------------------------------------------------------
+
+  component sem
+  port (
+    status_heartbeat            : out   std_logic;
+    status_initialization       : out   std_logic;
+    status_observation          : out   std_logic;
+    status_correction           : out   std_logic;
+    status_classification       : out   std_logic;
+    status_injection            : out   std_logic;
+    status_essential            : out   std_logic;
+    status_uncorrectable        : out   std_logic;
+    monitor_txdata              : out   std_logic_vector(7 downto 0);
+    monitor_txwrite             : out   std_logic;
+    monitor_txfull              : in    std_logic;
+    monitor_rxdata              : in    std_logic_vector(7 downto 0);
+    monitor_rxread              : out   std_logic;
+    monitor_rxempty             : in    std_logic;
+    inject_strobe               : in    std_logic;
+    inject_address              : in    std_logic_vector(39 downto 0);
+    fecc_crcerr                 : in    std_logic;
+    fecc_eccerr                 : in    std_logic;
+    fecc_eccerrsingle           : in    std_logic;
+    fecc_syndromevalid          : in    std_logic;
+    fecc_syndrome               : in    std_logic_vector(12 downto 0);
+    fecc_far                    : in    std_logic_vector(25 downto 0);
+    fecc_synbit                 : in    std_logic_vector(4 downto 0);
+    fecc_synword                : in    std_logic_vector(6 downto 0);
+    icap_o                      : in    std_logic_vector(31 downto 0);
+    icap_i                      : out   std_logic_vector(31 downto 0);
+    icap_csib                   : out   std_logic;
+    icap_rdwrb                  : out   std_logic;
+    icap_clk                    : in    std_logic;
+    icap_request                : out   std_logic;
+    icap_grant                  : in    std_logic
+    );
+  end component;
+
+  component sem_sem_cfg
+  port (
+    fecc_crcerr                 : out   std_logic;
+    fecc_eccerr                 : out   std_logic;
+    fecc_eccerrsingle           : out   std_logic;
+    fecc_syndromevalid          : out   std_logic;
+    fecc_syndrome               : out   std_logic_vector(12 downto 0);
+    fecc_far                    : out   std_logic_vector(25 downto 0);
+    fecc_synbit                 : out   std_logic_vector(4 downto 0);
+    fecc_synword                : out   std_logic_vector(6 downto 0);
+    icap_o                      : out   std_logic_vector(31 downto 0);
+    icap_i                      : in    std_logic_vector(31 downto 0);
+    icap_clk                    : in    std_logic;
+    icap_csib                   : in    std_logic;
+    icap_rdwrb                  : in    std_logic
+    );
+  end component;
+
+  component sem_sem_mon
+  port (
+    icap_clk                    : in    std_logic;
+    monitor_tx                  : out   std_logic;
+    monitor_rx                  : in    std_logic;
+    monitor_txdata              : in    std_logic_vector(7 downto 0);
+    monitor_txwrite             : in    std_logic;
+    monitor_txfull              : out   std_logic;
+    monitor_rxdata              : out   std_logic_vector(7 downto 0);
+    monitor_rxread              : in    std_logic;
+    monitor_rxempty             : out   std_logic
+    );
+  end component;
+
+  component sem_sem_hid
+  port (
+    icap_clk                    : in    std_logic;
+    status_heartbeat            : in    std_logic;
+    status_initialization       : in    std_logic;
+    status_observation          : in    std_logic;
+    status_correction           : in    std_logic;
+    status_classification       : in    std_logic;
+    status_injection            : in    std_logic;
+    status_essential            : in    std_logic;
+    status_uncorrectable        : in    std_logic;
+    inject_strobe               : out   std_logic;
+    inject_address              : out   std_logic_vector(39 downto 0);
+  disable_all                   : out   std_logic;
+  ADC_selREGS                   : out   std_logic_vector(2 downto 0);
+  disable_tests                 : out   std_logic_vector(3 downto 0)
+   );
+  end component;
+
+  ---------------------------------------------------------------------------
+  -- Declare signals.
+  ---------------------------------------------------------------------------
+
+  signal status_heartbeat_internal : std_logic;
+  signal status_initialization_internal : std_logic;
+  signal status_observation_internal : std_logic;
+  signal status_correction_internal : std_logic;
+  signal status_classification_internal : std_logic;
+  signal status_injection_internal : std_logic;
+  signal status_essential_internal : std_logic;
+  signal status_uncorrectable_internal : std_logic;
+
+  signal monitor_txdata         : std_logic_vector(7 downto 0);
+  signal monitor_txwrite        : std_logic;
+  signal monitor_txfull         : std_logic;
+  signal monitor_rxdata         : std_logic_vector(7 downto 0);
+  signal monitor_rxread         : std_logic;
+  signal monitor_rxempty        : std_logic;
+  signal inject_strobe          : std_logic;
+  signal inject_address         : std_logic_vector(39 downto 0);
+  signal fecc_crcerr            : std_logic;
+  signal fecc_eccerr            : std_logic;
+  signal fecc_eccerrsingle      : std_logic;
+  signal fecc_syndromevalid     : std_logic;
+  signal fecc_syndrome          : std_logic_vector(12 downto 0);
+  signal fecc_far               : std_logic_vector(25 downto 0);
+  signal fecc_synbit            : std_logic_vector(4 downto 0);
+  signal fecc_synword           : std_logic_vector(6 downto 0);
+  signal icap_o                 : std_logic_vector(31 downto 0);
+  signal icap_i                 : std_logic_vector(31 downto 0);
+  signal icap_csib              : std_logic;
+  signal icap_rdwrb             : std_logic;
+  signal icap_unused            : std_logic;
+  signal icap_grant             : std_logic;
+  signal icap_clk               : std_logic;
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+  constant V_ENABLETIME : integer := 21; -- FOR 115200 259; FOR 9600
+  signal monitor_rxdata_S       : std_logic_vector(7 downto 0);
+  signal monitor_rxread_S       : std_logic;
+  signal monitor_rxempty_S      : std_logic;
+  signal insert_rxdata_S        : std_logic_vector(7 downto 0);
+  signal insert_rxempty_S       : std_logic := '0';
+  signal insertingcmd_S         : std_logic := '0';
+  signal insert_S               : std_logic := '0';
+  
+  signal monitor_tx_S           : std_logic;
+  signal monitor_txdata_S       : std_logic_vector(7 downto 0);
+  signal monitor_txwrite_S      : std_logic;
+  signal monitor_txfull_S       : std_logic := '0';
+  signal insert_data_read_S     : std_logic := '0';
+  signal insert_txdata_S        : std_logic_vector(7 downto 0);
+  signal insert_txwrite_S       : std_logic := '0';
+  signal insertingstat_S        : std_logic := '0';
+  signal insert_writecr_S       : std_logic := '0';
+  
+  
+
+attribute mark_debug : string;
+-- attribute mark_debug of monitor_rx : signal is "true";
+-- attribute mark_debug of monitor_rxdata_S : signal is "true";
+-- attribute mark_debug of monitor_rxread_S : signal is "true";
+-- attribute mark_debug of monitor_rxempty_S : signal is "true";
+
+-- attribute mark_debug of insertingcmd_S : signal is "true";
+-- attribute mark_debug of insert_rxempty_S : signal is "true";
+-- attribute mark_debug of insert_S : signal is "true";
+-- attribute mark_debug of monitor_txdata_S : signal is "true";
+-- attribute mark_debug of monitor_txwrite_S : signal is "true";
+-- attribute mark_debug of monitor_txfull_S : signal is "true";
+-- attribute mark_debug of insert_data_read_S : signal is "true";
+-- attribute mark_debug of insert_txdata_S : signal is "true";
+-- attribute mark_debug of insert_txwrite_S : signal is "true";
+-- attribute mark_debug of insertingstat_S : signal is "true";
+-- attribute mark_debug of insert_writecr_S : signal is "true";
+-- attribute mark_debug of monitor_tx_S : signal is "true";
+			
+  begin
+
+  ---------------------------------------------------------------------------
+  -- This design (the example, including the controller itself) is fully
+  -- synchronous; the global clock buffer is instantiated here to drive
+  -- the icap_clk signal.
+  ---------------------------------------------------------------------------
+
+  example_bufg : BUFGCE
+  port map (
+    I => clk,
+    O => icap_clk,
+    CE => '1'
+    );
+
+  ---------------------------------------------------------------------------
+  -- The controller sub-entity is the kernel of the soft error mitigation
+  -- solution.  The port list is dynamic based on the IP core options.
+  ---------------------------------------------------------------------------
+
+  example_controller : sem
+  port map (
+    status_heartbeat => status_heartbeat_internal,
+    status_initialization => status_initialization_internal,
+    status_observation => status_observation_internal,
+    status_correction => status_correction_internal,
+    status_classification => status_classification_internal,
+    status_injection => status_injection_internal,
+    status_essential => status_essential_internal,
+    status_uncorrectable => status_uncorrectable_internal,
+    monitor_txdata => monitor_txdata,
+    monitor_txwrite => monitor_txwrite,
+    monitor_txfull => monitor_txfull,
+    monitor_rxdata => monitor_rxdata,
+    monitor_rxread => monitor_rxread,
+    monitor_rxempty => monitor_rxempty,
+    inject_strobe => inject_strobe,
+    inject_address => inject_address,
+    fecc_crcerr => fecc_crcerr,
+    fecc_eccerr => fecc_eccerr,
+    fecc_eccerrsingle => fecc_eccerrsingle,
+    fecc_syndromevalid => fecc_syndromevalid,
+    fecc_syndrome => fecc_syndrome,
+    fecc_far => fecc_far,
+    fecc_synbit => fecc_synbit,
+    fecc_synword => fecc_synword,
+    icap_o => icap_o,
+    icap_i => icap_i,
+    icap_csib => icap_csib,
+    icap_rdwrb => icap_rdwrb,
+    icap_clk => icap_clk,
+    icap_request => icap_unused,
+    icap_grant => icap_grant
+    );
+
+  icap_grant <= '1';
+  status_heartbeat <= status_heartbeat_internal;
+  status_initialization <= status_initialization_internal;
+  status_observation <= status_observation_internal;
+  status_correction <= status_correction_internal;
+  status_classification <= status_classification_internal;
+  status_injection <= status_injection_internal;
+  status_essential <= status_essential_internal;
+  status_uncorrectable <= status_uncorrectable_internal;
+
+  ---------------------------------------------------------------------------
+  -- The cfg sub-entity contains the device specific primitives to access
+  -- the internal configuration port and the frame crc/ecc status signals.
+  ---------------------------------------------------------------------------
+
+  example_cfg : sem_sem_cfg
+  port map (
+    fecc_crcerr => fecc_crcerr,
+    fecc_eccerr => fecc_eccerr,
+    fecc_eccerrsingle => fecc_eccerrsingle,
+    fecc_syndromevalid => fecc_syndromevalid,
+    fecc_syndrome => fecc_syndrome,
+    fecc_far => fecc_far,
+    fecc_synbit => fecc_synbit,
+    fecc_synword => fecc_synword,
+    icap_o => icap_o,
+    icap_i => icap_i,
+    icap_csib => icap_csib,
+    icap_rdwrb => icap_rdwrb,
+    icap_clk => icap_clk
+    );
+
+  ---------------------------------------------------------------------------
+  -- The mon sub-entity contains a UART for communication purposes.
+  ---------------------------------------------------------------------------
+
+  example_mon : sem_sem_mon
+  port map (
+    icap_clk => icap_clk,
+    monitor_tx => monitor_tx_S,
+    monitor_rx => monitor_rx,
+    monitor_txdata => monitor_txdata_S,
+    monitor_txwrite => monitor_txwrite_S,
+    monitor_txfull => monitor_txfull_S,
+    monitor_rxdata => monitor_rxdata_S,
+    monitor_rxread => monitor_rxread_S,
+    monitor_rxempty => monitor_rxempty_S
+    );
+monitor_tx <= monitor_tx_S;
+monitor_txdata_S <= monitor_txdata when insertingstat_S='0' else insert_txdata_S;
+monitor_txwrite_S <= monitor_txwrite when insertingstat_S='0' else insert_txwrite_S;
+monitor_txfull <= monitor_txfull_S when insertingstat_S='0' else '1';
+monitor_rxdata <= monitor_rxdata_S when insertingcmd_S='0' else insert_rxdata_S;
+monitor_rxread_S <= monitor_rxread when insertingcmd_S='0' else '0';
+monitor_rxempty <= monitor_rxempty_S when insertingcmd_S='0' else insert_rxempty_S;
+
+process(icap_clk)
+variable rxcount_V           : integer range 0 to 16*V_ENABLETIME*12 := 0;
+variable delaycount_V        : integer range 0 to 16*V_ENABLETIME*115200 := 0;
+begin
+	if rising_edge(icap_clk) then
+		if delaycount_V<16*V_ENABLETIME*115200-1 then
+			delaycount_V := delaycount_V+1;
+		else
+			delaycount_V := 0;
+			insert_S <= '1';
+		end if;
+		if insertingcmd_S='0' then
+			if monitor_rx='1' then
+				if rxcount_V<16*V_ENABLETIME*12-1 then
+					rxcount_V := rxcount_V+1;
+				else
+					if (monitor_rxempty_S='1') and (monitor_rxread='0') and (insert_S='1') then
+						insertingcmd_S <= '1';
+						insert_rxempty_S <= '0';
+						insert_rxdata_S <= x"53";
+					end if;
+				end if;
+			else
+				rxcount_V := 0;
+			end if;
+		else
+			insert_S <= '0';
+			if insert_rxempty_S='1' then
+				insertingcmd_S <= '0';
+			else
+				if monitor_rxread='1' then
+					insert_rxempty_S <= '1';
+				end if;
+			end if;
+		end if;		
+	end if;
+end process;
+
+process(icap_clk)
+variable rxcount_V           : integer range 0 to 16*V_ENABLETIME*12 := 0;
+begin
+	if rising_edge(icap_clk) then
+		insert_data_read_S <= '0';
+		insert_txwrite_S <= '0';
+		if insertingstat_S='0' then
+			if (monitor_tx_S='1') and (monitor_txwrite_S='0') then
+				if rxcount_V<16*V_ENABLETIME*12-1 then
+					rxcount_V := rxcount_V+1;
+				else
+					if (insert_data_available='1') then
+						insert_data_read_S <= '1';
+						insertingstat_S <= '1';
+						insert_writecr_S <= '0';
+					end if;
+				end if;
+			else
+				rxcount_V := 0;
+			end if;
+		else
+			if insert_writecr_S='0' then
+				if insert_data_read_S='1' then
+					insert_txdata_S <= insert_data;
+					if monitor_txfull_S='0' then
+						insert_txwrite_S <= '1';
+					end if;
+				else
+					if insert_txwrite_S='0' then
+						if monitor_txfull_S='0' then
+							insert_txwrite_S <= '1';
+						end if;
+					else
+						insert_writecr_S <= '1';
+					end if;
+				end if;
+			else
+				insert_txdata_S <= x"0d";
+				if insert_txwrite_S='1' then
+					insertingstat_S <= '0';
+				else
+					if monitor_txfull_S='0' then
+						insert_txwrite_S <= '1';
+					end if;
+				end if;
+			end if;
+		end if;		
+	end if;
+end process;
+insert_data_read <= insert_data_read_S;
+
+
+  ---------------------------------------------------------------------------
+  -- The hid sub-entity contains a Vivado Lab Tools VIO for interfacing.
+  ---------------------------------------------------------------------------
+
+  example_hid : sem_sem_hid
+  port map (
+    icap_clk => icap_clk,
+    status_heartbeat => status_heartbeat_internal,
+    status_initialization => status_initialization_internal,
+    status_observation => status_observation_internal,
+    status_correction => status_correction_internal,
+    status_classification => status_classification_internal,
+    status_injection => status_injection_internal,
+    status_essential => status_essential_internal,
+    status_uncorrectable => status_uncorrectable_internal,
+    inject_strobe => inject_strobe,
+    inject_address => inject_address,
+	disable_all => disable_all,
+	ADC_selREGS => ADC_selREGS,
+	disable_tests => disable_tests
+    );
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_hid.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_hid.vhd
new file mode 100644
index 0000000..8cc10d9
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_hid.vhd
@@ -0,0 +1,413 @@
+
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/    Core:          sem
+--  \   \        Entity:        sem_sem_hid
+--  /   /        Filename:      sem_sem_hid.vhd
+-- /___/   /\    Purpose:       HID Shim using Vivado Lab Tools components.
+-- \   \  /  \
+--  \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity contains instances of Virtual Input/Output (VIO) cores to enable 
+-- interactive injection of errors and observation of status.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- icap_clk                      input  The system clock signal.
+--
+-- status_heartbeat              input  Heartbeat signal for external watch
+--                                      dog timer implementation; pulses
+--                                      when readback runs.  Synchronous to
+--                                      icap_clk.
+--
+-- status_initialization         input  Indicates initialization is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_observation            input  Indicates observation is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_correction             input  Indicates correction is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_classification         input  Indicates classification is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_injection              input  Indicates injection is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_essential              input  Indicates essential error condition.
+--                                      Qualified by de-assertion of the
+--                                      status_classification signal, and
+--                                      is synchronous to icap_clk.
+--
+-- status_uncorrectable          input  Indicates uncorrectable error
+--                                      condition. Qualified by de-assertion
+--                                      of the status_correction signal, and
+--                                      is synchronous to icap_clk.
+--
+-- inject_strobe                 output Error injection port strobe used
+--                                      by the controller to enable capture
+--                                      of the error injection address.
+--                                      Synchronous to icap_clk.
+--
+-- inject_address[39:0]          output Error injection port address used
+--                                      to specify the location of a bit
+--                                      to be corrupted.  Synchronous to
+--                                      icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- TCQ                           int    Sets the clock-to-out for behavioral
+--                                      descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_hid
+-- |
+-- \- sem_sem_vio 
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_hid is
+port (
+  icap_clk                      : in    std_logic;
+  status_heartbeat              : in    std_logic;
+  status_initialization         : in    std_logic;
+  status_observation            : in    std_logic;
+  status_correction             : in    std_logic;
+  status_classification         : in    std_logic;
+  status_injection              : in    std_logic;
+  status_essential              : in    std_logic;
+  status_uncorrectable          : in    std_logic;
+  inject_strobe                 : out   std_logic;
+  inject_address                : out   std_logic_vector(39 downto 0);
+  disable_all                   : out   std_logic;
+  ADC_selREGS                   : out   std_logic_vector(2 downto 0);
+  disable_tests                 : out   std_logic_vector(3 downto 0)
+  );
+end entity sem_sem_hid;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_hid is
+
+  ---------------------------------------------------------------------------
+  -- Define local constants.
+  ---------------------------------------------------------------------------
+
+  constant TCQ : time := 1 ps;
+  constant MAXOFFSET : integer := 16383;
+  constant MAXCOUNT : integer := 4095;
+  
+  ---------------------------------------------------------------------------
+  -- Define local output wires.
+  ---------------------------------------------------------------------------
+
+  signal inject_strobe_internal          : std_logic;
+  signal inject_address_internal         : std_logic_vector(39 downto 0);
+  signal previous_inject_strobe_internal : std_logic:= '0';
+  
+  
+type testmode_type is (NORMAL,IDLE,INJECT,OBSERV,RESET,AUTO,TIMED,NONE);
+signal testmode_S              : testmode_type := NORMAL;			
+signal testmode                : std_logic_vector(2 downto 0);	
+signal prev_testmode_S         : testmode_type := NORMAL;			
+signal count_S                 : integer range 0 to MAXCOUNT := 0;
+signal offset_S                : integer range 0 to MAXOFFSET := 0;
+signal inject_address_S        : std_logic_vector(39 downto 0);	
+signal prev_inject_address_S   : std_logic_vector(39 downto 0);	
+  
+  attribute mark_debug : string;
+  attribute mark_debug of status_heartbeat        : signal is "true";
+  attribute mark_debug of status_initialization   : signal is "true";
+  attribute mark_debug of status_observation      : signal is "true";
+  attribute mark_debug of status_correction       : signal is "true";
+  attribute mark_debug of status_classification   : signal is "true";
+  attribute mark_debug of status_injection        : signal is "true";
+  attribute mark_debug of status_essential        : signal is "true";
+  attribute mark_debug of status_uncorrectable    : signal is "true";
+  attribute mark_debug of inject_address_internal : signal is "true";
+  attribute mark_debug of disable_all             : signal is "true";
+  attribute mark_debug of ADC_selREGS             : signal is "true";
+  attribute mark_debug of disable_tests           : signal is "true";
+
+  ---------------------------------------------------------------------------
+  -- Component Declaration
+  ---------------------------------------------------------------------------
+  
+  component sem_sem_vio
+    port  (
+      clk        : in std_logic;
+      probe_in0  : in std_logic_vector(0 downto 0);
+      probe_in1  : in std_logic_vector(0 downto 0);
+      probe_in2  : in std_logic_vector(0 downto 0);
+      probe_in3  : in std_logic_vector(0 downto 0);
+      probe_in4  : in std_logic_vector(0 downto 0);
+      probe_in5  : in std_logic_vector(0 downto 0);
+      probe_in6  : in std_logic_vector(0 downto 0);
+      probe_in7  : in std_logic_vector(0 downto 0);
+      probe_out0 : out std_logic_vector(0 downto 0);
+      probe_out1 : out std_logic_vector(39 downto 0);
+      probe_out2 : out std_logic_vector(2 downto 0);
+      probe_out3 : out std_logic_vector(0 downto 0);
+      probe_out4 : out std_logic_vector(2 downto 0);
+      probe_out5 : out std_logic_vector(3 downto 0);
+      probe_out6 : out std_logic_vector(0 downto 0);
+      probe_out7 : out std_logic_vector(0 downto 0) 		       
+    );
+    end component;
+
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+  begin
+
+  ---------------------------------------------------------------------------
+  -- Create a 1-cycle pulse from the VIO inject_strobe output to ensure a 
+  -- single error injection command is issued to the SEM controller.
+  ---------------------------------------------------------------------------
+  
+  process(icap_clk)
+  begin
+    if rising_edge(icap_clk) then
+      previous_inject_strobe_internal <= inject_strobe_internal after TCQ;
+    end if;
+  end process;
+  
+  -- inject_strobe  <= (not previous_inject_strobe_internal) and 
+                     -- inject_strobe_internal;
+  -- inject_address <= inject_address_internal;
+
+  ---------------------------------------------------------------------------
+  -- Instantiate the SEM VIO core.
+  ---------------------------------------------------------------------------
+
+  example_vio : sem_sem_vio
+  port map (
+    clk           => icap_clk,                
+    probe_in0(0)  => status_heartbeat,        
+    probe_in1(0)  => status_uncorrectable,    
+    probe_in2(0)  => status_essential,        
+    probe_in3(0)  => status_injection,        
+    probe_in4(0)  => status_classification,   
+    probe_in5(0)  => status_correction,       
+    probe_in6(0)  => status_observation,      
+    probe_in7(0)  => status_initialization,   
+    probe_out0(0) => inject_strobe_internal,  
+    probe_out1(39 downto 0) => inject_address_internal,
+    probe_out2(2 downto 0) => testmode,  
+    probe_out3(0) => disable_all,  
+    probe_out4(2 downto 0) => ADC_selREGS,  
+    probe_out5(3 downto 0) => disable_tests,  
+    probe_out6(0) => open,  
+    probe_out7(0) => open  		       
+  );
+testmode_S <= NORMAL when testmode="000" else
+	IDLE when testmode="001" else
+	INJECT when testmode="010" else
+	OBSERV when testmode="011" else
+	RESET when testmode="100" else
+	AUTO when testmode="101" else
+	TIMED when testmode="110" else
+	NONE when testmode="111" else 
+	IDLE when testmode="000" else
+	NORMAL;
+	
+inject_address <= inject_address_S;
+
+  process(icap_clk)
+  begin
+    if rising_edge(icap_clk) then
+		inject_strobe <= '0';
+		case testmode_S is
+			when NORMAL =>
+				inject_address_S <= inject_address_internal;
+				if (inject_strobe_internal='1') and (previous_inject_strobe_internal='0') then
+					inject_strobe <= '1';
+				end if;
+			when IDLE =>
+				inject_address_S(39 downto 36) <= "1110";
+				inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+				if (prev_testmode_S/=testmode_S) then 
+					inject_strobe <= '1';
+				end if;
+				if (inject_strobe_internal='1') and (previous_inject_strobe_internal='0') then
+					inject_strobe <= '1';						
+				end if;
+			when INJECT =>
+				inject_address_S(39 downto 36) <= "1100";
+				inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+				if (prev_testmode_S/=testmode_S) then 
+					inject_strobe <= '1';
+				end if;
+				if (inject_strobe_internal='1') and (previous_inject_strobe_internal='0') then
+					inject_strobe <= '1';						
+				end if;
+			when OBSERV =>
+				inject_address_S(39 downto 36) <= "1010";
+				inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+				if (prev_testmode_S/=testmode_S) then 
+					inject_strobe <= '1';
+				end if;
+				if (inject_strobe_internal='1') and (previous_inject_strobe_internal='0') then
+					inject_strobe <= '1';						
+				end if;
+			when RESET =>
+				inject_address_S(39 downto 36) <= "1011";
+				inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+				if (prev_testmode_S/=testmode_S) then 
+					inject_strobe <= '1';
+				end if;
+				if (inject_strobe_internal='1') and (previous_inject_strobe_internal='0') then
+					inject_strobe <= '1';						
+				end if;
+			when AUTO =>
+				inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+				if (prev_inject_address_S(35 downto 0)/=inject_address_internal(35 downto 0))
+					or (prev_testmode_S/=testmode_S) 
+					or ((inject_strobe_internal='1') and (previous_inject_strobe_internal='0')) then
+					inject_strobe <= '1';						
+					inject_address_S(39 downto 36) <= "1110";
+					count_S <= 0;
+				else
+					if count_S=1000 then
+						inject_address_S(39 downto 36) <= "1100";
+						inject_strobe <= '1';	
+					elsif count_S=2000 then
+						inject_address_S(39 downto 36) <= "1010";
+						inject_strobe <= '1';
+					end if;
+					if count_S<4095 then
+						count_S <= count_S+1;
+					end if;
+				end if;
+			when TIMED =>
+				if (prev_inject_address_S(35 downto 0)/=inject_address_internal(35 downto 0))
+					or (prev_testmode_S/=testmode_S) 
+					or ((inject_strobe_internal='1') and (previous_inject_strobe_internal='0')) then
+					inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0);
+					offset_S <= 0;
+					count_S <= 0;
+				else
+					if offset_S<MAXOFFSET then
+						if count_S=0 then
+							inject_strobe <= '1';						
+							inject_address_S(39 downto 36) <= "1110";
+							inject_address_S(35 downto 0) <= inject_address_internal(35 downto 0) + conv_std_logic_vector(offset_S,36);
+						elsif count_S=100 then
+							inject_address_S(39 downto 36) <= "1100";
+							inject_strobe <= '1';	
+						elsif count_S=200 then
+							inject_address_S(39 downto 36) <= "1010";
+							inject_strobe <= '1';
+						end if;
+						if count_S<MAXCOUNT then 
+							count_S <= count_S+1;
+						else
+							count_S <= 0;
+							offset_S <= offset_S+1;
+						end if;
+					end if;
+				end if;
+			when NONE =>
+			when OTHERS =>
+		end case;		
+		prev_testmode_S <= testmode_S;
+		prev_inject_address_S <= inject_address_internal;
+    end if;
+  end process;
+  
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
+
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon.vhd
new file mode 100644
index 0000000..b1070b5
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon.vhd
@@ -0,0 +1,321 @@
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/    Core:          sem
+--  \   \        Entity:        sem_sem_mon
+--  /   /        Filename:      sem_sem_mon.vhd
+-- /___/   /\    Purpose:       MON Shim for RS232 Port.
+-- \   \  /  \
+--  \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity is a MON Shim implementation for communication with external
+-- RS232 devices.  Examples of external devices include a desktop or laptop
+-- computer, or an embedded processor system.  This shim may be replaced with
+-- a custom user-supplied design to enable communication with other devices.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- icap_clk                      input  The system clock signal.
+--
+-- monitor_tx                    output Serial status output.  Synchronous
+--                                      to icap_clk, but received externally
+--                                      by another device as an asynchronous
+--                                      signal, perceived as lower bitrate.
+--                                      Uses 8N1 protocol.
+--
+-- monitor_rx                    input  Serial command input.  Asynchronous
+--                                      signal provided by another device at
+--                                      a lower bitrate, synchronized to the
+--                                      icap_clk and oversampled.  Uses 8N1
+--                                      protocol.
+--
+-- monitor_txdata[7:0]           input  Output data from controller,
+--                                      qualified by monitor_txwrite.
+--                                      Synchronous to icap_clk.
+--
+-- monitor_txwrite               input  Write strobe, used by peripheral
+--                                      to capture data.  Synchronous to
+--                                      icap_clk.
+--
+-- monitor_txfull                output Flow control signal indicating the
+--                                      peripheral is not ready to receive
+--                                      additional data writes.  Synchronous
+--                                      to icap_clk.
+--
+-- monitor_rxdata[7:0]           output Input data to controller qualified
+--                                      by monitor_rxread. Synchronous to
+--                                      icap_clk.
+--
+-- monitor_rxread                input  Read strobe, used by peripheral
+--                                      to change state.  Synchronous to
+--                                      icap_clk.
+--
+-- monitor_rxempty               output Flow control signal indicating the
+--                                      peripheral is not ready to service
+--                                      additional data reads.  Synchronous
+--                                      to icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- TCQ                           int    Sets the clock-to-out for behavioral
+--                                      descriptions of sequential logic.
+--
+-- V_ENABLETIME                  int    This sets communication baud rate;
+--                                      see user guide for additional detail.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_mon
+-- |
+-- +- sem_sem_mon_fifo
+-- |
+-- +- sem_sem_mon_piso
+-- |
+-- \- sem_sem_mon_sipo
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_mon is
+port (
+  icap_clk                      : in    std_logic;
+  monitor_tx                    : out   std_logic;
+  monitor_rx                    : in    std_logic;
+  monitor_txdata                : in    std_logic_vector(7 downto 0);
+  monitor_txwrite               : in    std_logic;
+  monitor_txfull                : out   std_logic;
+  monitor_rxdata                : out   std_logic_vector(7 downto 0);
+  monitor_rxread                : in    std_logic;
+  monitor_rxempty               : out   std_logic
+  );
+end entity sem_sem_mon;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_mon is
+
+  ---------------------------------------------------------------------------
+  -- Define local constants.
+  ---------------------------------------------------------------------------
+
+  constant TCQ : time := 1 ps;
+  constant V_ENABLETIME : integer := 21; -- FOR 115200 259; FOR 9600
+
+  ---------------------------------------------------------------------------
+  -- Declare non-library components.
+  ---------------------------------------------------------------------------
+
+  component sem_sem_mon_fifo
+  port (
+    icap_clk                    : in    std_logic;
+    data_in                     : in    std_logic_vector(7 downto 0);
+    data_out                    : out   std_logic_vector(7 downto 0);
+    write                       : in    std_logic;
+    read                        : in    std_logic;
+    full                        : out   std_logic;
+    data_present                : out   std_logic
+    );
+  end component;
+
+  component sem_sem_mon_sipo
+  port (
+    icap_clk                    : in    std_logic;
+    data_out                    : out   std_logic_vector(7 downto 0);
+    serial_in                   : in    std_logic;
+    en_16_x_baud                : in    std_logic;
+    data_strobe                 : out   std_logic
+    );
+  end component;
+
+  component sem_sem_mon_piso
+  port (
+    icap_clk                    : in    std_logic;
+    data_in                     : in    std_logic_vector(7 downto 0);
+    send_character              : in    std_logic;
+    en_16_x_baud                : in    std_logic;
+    serial_out                  : out   std_logic;
+    tx_complete                 : out   std_logic
+    );
+  end component;
+
+  ---------------------------------------------------------------------------
+  -- Declare signals.
+  ---------------------------------------------------------------------------
+
+  signal en_16_x_counter        : std_logic_vector(11 downto 0) := X"000";
+  signal en_16_x_baud           : std_logic;
+  signal fifo_read              : std_logic;
+  signal fifo_data_present      : std_logic;
+  signal fifo_data_out          : std_logic_vector(7 downto 0);
+  signal txfull_p               : std_logic;
+  signal fifo_write             : std_logic;
+  signal fifo_data_in           : std_logic_vector(7 downto 0);
+  signal fifo_unused            : std_logic;
+  signal rxempty_n              : std_logic;
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+  begin
+
+  ---------------------------------------------------------------------------
+  -- Create the 16x enable signal for baud rate generation.  This has an
+  -- initial value, but no functional reset; it runs continuously.
+  ---------------------------------------------------------------------------
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      if (en_16_x_baud = '1') then
+        en_16_x_counter <= X"000" after TCQ;
+      else
+        en_16_x_counter <= en_16_x_counter + X"001" after TCQ;
+      end if;
+    end if;
+  end process;
+
+  en_16_x_baud <= '1' when (en_16_x_counter = conv_std_logic_vector(V_ENABLETIME,12)) else '0';
+
+  ---------------------------------------------------------------------------
+  -- Implement the transmit channel with a FIFO and PISO.
+  ---------------------------------------------------------------------------
+
+  example_mon_fifo_tx : sem_sem_mon_fifo
+  port map (
+    data_in => monitor_txdata,
+    data_out => fifo_data_out,
+    write => monitor_txwrite,
+    read => fifo_read,
+    full => txfull_p,
+    data_present => fifo_data_present,
+    icap_clk => icap_clk
+    );
+
+  example_mon_piso : sem_sem_mon_piso
+  port map (
+    data_in => fifo_data_out,
+    send_character => fifo_data_present,
+    en_16_x_baud => en_16_x_baud,
+    serial_out => monitor_tx,
+    tx_complete => fifo_read,
+    icap_clk => icap_clk
+    );
+
+  monitor_txfull <= txfull_p;
+
+  ---------------------------------------------------------------------------
+  -- Implement the receive channel with a SIPO and FIFO.
+  ---------------------------------------------------------------------------
+
+  example_mon_sipo : sem_sem_mon_sipo
+  port map (
+    serial_in => monitor_rx,
+    data_out => fifo_data_in,
+    data_strobe => fifo_write,
+    en_16_x_baud => en_16_x_baud,
+    icap_clk => icap_clk
+    );
+
+  example_mon_fifo_rx : sem_sem_mon_fifo
+  port map (
+    data_in => fifo_data_in,
+    data_out => monitor_rxdata,
+    write => fifo_write,
+    read => monitor_rxread,
+    full => fifo_unused,
+    data_present => rxempty_n,
+    icap_clk => icap_clk
+    );
+
+  monitor_rxempty <= not (rxempty_n);
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon_fifo.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon_fifo.vhd
new file mode 100644
index 0000000..dddfafa
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon_fifo.vhd
@@ -0,0 +1,293 @@
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/    Core:          sem
+--  \   \        Entity:        sem_sem_mon_fifo
+--  /   /        Filename:      sem_sem_mon_fifo.vhd
+-- /___/   /\    Purpose:       MON Shim 32x8 FIFO.
+-- \   \  /  \
+--  \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity contains a 32x8 synchronous FIFO implementation.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- icap_clk                      input  The system clock signal.
+--
+-- data_in[7:0]                  input  Input to the FIFO. Synchronous
+--                                      to icap_clk.
+--
+-- data_out[7:0]                 output Output from the FIFO.  Synchronous
+--                                      to icap_clk.
+--
+-- write                         input  Write strobe, used to enable data
+--                                      capture.  Synchronous to icap_clk.
+--
+-- read                          input  Read strobe, used to advance data
+--                                      output to next value.  Synchronous
+--                                      to icap_clk.
+--
+-- full                          output Indicates when the FIFO is full.
+--                                      Synchronous to icap_clk.
+--
+-- data_present                  output Indicates when the FIFO has data
+--                                      (not empty). Synchronous to icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- TCQ                           int    Sets the clock-to-out for behavioral
+--                                      descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_mon_fifo
+-- |
+-- \- SRLC32E (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_mon_fifo is
+port (
+  icap_clk                      : in    std_logic;
+  data_in                       : in    std_logic_vector(7 downto 0);
+  data_out                      : out   std_logic_vector(7 downto 0);
+  write                         : in    std_logic;
+  read                          : in    std_logic;
+  full                          : out   std_logic;
+  data_present                  : out   std_logic
+  );
+end entity sem_sem_mon_fifo;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_mon_fifo is
+
+  ---------------------------------------------------------------------------
+  -- Define local constants.
+  ---------------------------------------------------------------------------
+
+  constant TCQ : time := 1 ps;
+
+  ---------------------------------------------------------------------------
+  -- Declare non-library components.
+  ---------------------------------------------------------------------------
+
+  -- None
+
+  ---------------------------------------------------------------------------
+  -- Declare signals.
+  ---------------------------------------------------------------------------
+
+  signal augend                 : std_logic_vector(5 downto 0) := "011111";
+  signal addend                 : std_logic_vector(5 downto 0);
+  signal addsel                 : std_logic_vector(1 downto 0);
+  signal valid_write            : std_logic;
+  signal valid_read             : std_logic;
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+  begin
+
+  ---------------------------------------------------------------------------
+  -- Data storage.
+  ---------------------------------------------------------------------------
+
+  data_srl_0 : SRLC32E
+  port map (
+    D => data_in(0),
+    CE => write,
+    CLK => icap_clk,
+    A => augend(4 downto 0),
+    Q => data_out(0),
+    Q31 => open
+    );
+
+  data_srl_1 : SRLC32E
+  port map (
+    D => data_in(1),
+    CE => write,
+    CLK => icap_clk,
+    A => augend(4 downto 0),
+    Q => data_out(1),
+    Q31 => open
+    );
+
+  data_srl_2 : SRLC32E
+  port map (
+    D => data_in(2),
+    CE => write,
+    CLK => icap_clk,
+    A => augend(4 downto 0),
+    Q => data_out(2),
+    Q31 => open
+    );
+
+  data_srl_3 : SRLC32E
+  port map (
+    D => data_in(3),
+    CE => write,
+    CLK => icap_clk,
+    A => augend(4 downto 0),
+    Q => data_out(3),
+    Q31 => open
+    );
+
+  data_srl_4 : SRLC32E
+  port map (
+    D => data_in(4),
+    CE => write,
+    CLK => icap_clk,
+    A => augend(4 downto 0),
+    Q => data_out(4),
+    Q31 => open
+    );
+
+  data_srl_5 : SRLC32E
+  port map (
+    D => data_in(5),
+    CE => write,
+    CLK => icap_clk,
+    A => augend(4 downto 0),
+    Q => data_out(5),
+    Q31 => open
+    );
+
+  data_srl_6 : SRLC32E
+  port map (
+    D => data_in(6),
+    CE => write,
+    CLK => icap_clk,
+    A => augend(4 downto 0),
+    Q => data_out(6),
+    Q31 => open
+    );
+
+  data_srl_7 : SRLC32E
+  port map (
+    D => data_in(7),
+    CE => write,
+    CLK => icap_clk,
+    A => augend(4 downto 0),
+    Q => data_out(7),
+    Q31 => open
+    );
+
+  ---------------------------------------------------------------------------
+  -- Buffer management.
+  ---------------------------------------------------------------------------
+
+  valid_write <= write when (augend /= "111111") else '0';
+  valid_read <= read and augend(5);
+  addsel <= valid_read & valid_write;
+
+  process (addsel)
+  begin
+    case addsel is
+      when "01" => addend <= "000001";
+      when "10" => addend <= "111111";
+      when others => addend <= "000000";
+    end case;
+  end process;
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      augend <= (augend + addend) after TCQ;
+    end if;
+  end process;
+
+  data_present <= augend(5);
+  full <= '1' when (augend = "111111") else '0';
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon_piso.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon_piso.vhd
new file mode 100644
index 0000000..3354251
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon_piso.vhd
@@ -0,0 +1,309 @@
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/    Core:          sem
+--  \   \        Entity:        sem_sem_mon_piso
+--  /   /        Filename:      sem_sem_mon_piso.vhd
+-- /___/   /\    Purpose:       MON Shim 8N1 PISO.
+-- \   \  /  \
+--  \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity contains an 8N1 PISO implementation.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- icap_clk                      input  The system clock signal.
+--
+-- data_in[7:0]                  input  Input to the PISO. Synchronous
+--                                      to icap_clk.
+--
+-- send_character                input  Qualifies availability of valid
+--                                      data on data_in port.  Synchronous
+--                                      to icap_clk.
+--
+-- en_16_x_baud                  input  Enable signal with periodic single
+--                                      cycle pulses at 16 times baud rate.
+--                                      Synchronous to icap_clk.
+--
+-- serial_out                    output Serialized output.  Synchronous
+--                                      to icap_clk.
+--
+-- tx_complete                   output Indicates transmission complete.
+--                                      Synchronous to icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- TCQ                           int    Sets the clock-to-out for behavioral
+--                                      descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_mon_piso
+-- |
+-- \- FD (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_mon_piso is
+port (
+  icap_clk                      : in    std_logic;
+  data_in                       : in    std_logic_vector(7 downto 0);
+  send_character                : in    std_logic;
+  en_16_x_baud                  : in    std_logic;
+  serial_out                    : out   std_logic;
+  tx_complete                   : out   std_logic
+  );
+end entity sem_sem_mon_piso;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_mon_piso is
+
+  ---------------------------------------------------------------------------
+  -- Define local constants.
+  ---------------------------------------------------------------------------
+
+  constant TCQ : time := 1 ps;
+
+  ---------------------------------------------------------------------------
+  -- Declare non-library components.
+  ---------------------------------------------------------------------------
+
+  -- None
+
+  ---------------------------------------------------------------------------
+  -- Declare signals.
+  ---------------------------------------------------------------------------
+
+  signal hot_delay              : std_logic_vector(15 downto 0) := X"0000";
+  signal bit_select             : std_logic_vector(2 downto 0) := "000";
+  signal piso_out               : std_logic := '1';
+  signal all_done               : std_logic := '0';
+  signal tx_start               : std_logic := '0';
+  signal tx_stop                : std_logic := '0';
+  signal tx_run                 : std_logic := '0';
+  signal tx_bit                 : std_logic;
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+  begin
+
+  ---------------------------------------------------------------------------
+  -- Convert parallel data to serial data with provision for stop and start.
+  -- Follow this by a flip-flop instance specifically for packing to pin.
+  ---------------------------------------------------------------------------
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      if (tx_start = '1') then
+        piso_out <= '0' after TCQ;
+      elsif (tx_stop = '1') then
+        piso_out <= '1' after TCQ;
+      elsif (tx_run = '1') then
+        piso_out <= data_in(conv_integer(bit_select)) after TCQ;
+      else
+        piso_out <= '1' after TCQ;
+      end if;
+    end if;
+  end process;
+
+  pipeline_serial : FD
+  generic map (INIT => '1')
+  port map (
+    D => piso_out,
+    Q => serial_out,
+    C => icap_clk
+    );
+
+  ---------------------------------------------------------------------------
+  -- Transmit bit counter.
+  ---------------------------------------------------------------------------
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      if (tx_start = '1') then
+        bit_select <= "000" after TCQ;
+      elsif ((en_16_x_baud = '1') and (tx_run = '1') and (tx_bit = '1')) then
+        bit_select <= bit_select + "001" after TCQ;
+      end if;
+    end if;
+  end process;
+
+  ---------------------------------------------------------------------------
+  -- Start bit enable.
+  ---------------------------------------------------------------------------
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      if (en_16_x_baud = '1') then
+        tx_start <= (
+          (not tx_start and     (send_character and not tx_start and not tx_run) and not tx_stop and not tx_bit) or
+          (not tx_start and     (send_character and not tx_start and not tx_run) and     tx_stop and     tx_bit) or
+          (    tx_start and not (send_character and not tx_start and not tx_run) and not tx_stop and not tx_bit) )
+          after TCQ;
+      end if;
+    end if;
+  end process;
+
+  ---------------------------------------------------------------------------
+  -- Stop bit enable.
+  ---------------------------------------------------------------------------
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      if (en_16_x_baud = '1') then
+        tx_stop <= (
+          (not tx_stop and     (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0))) and     tx_run and     tx_bit) or
+          (    tx_stop and not (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0))) and not tx_run and not tx_bit) )
+          after TCQ;
+      end if;
+    end if;
+  end process;
+
+  ---------------------------------------------------------------------------
+  -- Run bit enable.
+  ---------------------------------------------------------------------------
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      if (en_16_x_baud = '1') then
+        tx_run <= (
+          (not tx_run and     tx_start and     tx_bit and not (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0)))) or
+          (    tx_run and not tx_start and not tx_bit and not (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0)))) or
+          (    tx_run and not tx_start and     tx_bit and not (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0)))) or
+          (    tx_run and     tx_start and not tx_bit and not (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0)))) )
+          after TCQ;
+      end if;
+    end if;
+  end process;
+
+  ---------------------------------------------------------------------------
+  -- Bit rate enable.
+  ---------------------------------------------------------------------------
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      if (en_16_x_baud = '1') then
+        hot_delay(0) <= (
+          (not tx_stop and not (send_character and not tx_start and not tx_run) and     tx_bit) or
+          (    tx_stop and     (send_character and not tx_start and not tx_run) and     tx_bit) or
+          (not tx_stop and     (send_character and not tx_start and not tx_run) and not tx_bit) )
+          after TCQ;
+        hot_delay(15 downto 1) <= hot_delay(14 downto 0) after TCQ;
+      end if;
+    end if;
+  end process;
+
+  tx_bit <= hot_delay(15);
+
+  ---------------------------------------------------------------------------
+  -- Transmit complete strobe.
+  ---------------------------------------------------------------------------
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      all_done <= (en_16_x_baud and (tx_bit and (bit_select(2) and bit_select(1) and bit_select(0)))) after TCQ;
+    end if;
+  end process;
+
+  tx_complete <= all_done;
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon_sipo.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon_sipo.vhd
new file mode 100644
index 0000000..25caa19
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sem_support/sem_sem_mon_sipo.vhd
@@ -0,0 +1,243 @@
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/    Core:          sem
+--  \   \        Entity:        sem_sem_mon_sipo
+--  /   /        Filename:      sem_sem_mon_sipo.vhd
+-- /___/   /\    Purpose:       MON Shim 8N1 SIPO.
+-- \   \  /  \
+--  \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity contains an 8N1 SIPO implementation.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- icap_clk                      input  The system clock signal.
+--
+-- data_out[7:0]                 output Output from the SIPO.  Synchronous
+--                                      to icap_clk.
+--
+-- serial_in                     output Asynchronous serial input.
+--
+-- en_16_x_baud                  input  Enable signal with periodic single
+--                                      cycle pulses at 16 times baud rate.
+--                                      Synchronous to icap_clk.
+--
+-- data_strobe                   output Indicates reception complete.
+--                                      Synchronous to icap_clk.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- TCQ                           int    Sets the clock-to-out for behavioral
+--                                      descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_mon_sipo
+-- |
+-- \- FD (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_sem_mon_sipo is
+port (
+  icap_clk                      : in    std_logic;
+  data_out                      : out   std_logic_vector(7 downto 0);
+  serial_in                     : in    std_logic;
+  en_16_x_baud                  : in    std_logic;
+  data_strobe                   : out   std_logic
+  );
+end entity sem_sem_mon_sipo;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_sem_mon_sipo is
+
+  ---------------------------------------------------------------------------
+  -- Define local constants.
+  ---------------------------------------------------------------------------
+
+  constant TCQ : time := 1 ps;
+
+  attribute ASYNC_REG : string;
+  attribute ASYNC_REG of sync_reg_a : label is "TRUE";
+  attribute ASYNC_REG of sync_reg_b : label is "TRUE";
+  attribute ASYNC_REG of sync_reg_c : label is "TRUE";
+  attribute ASYNC_REG of sync_reg_d : label is "TRUE";
+
+  ---------------------------------------------------------------------------
+  -- Declare non-library components.
+  ---------------------------------------------------------------------------
+
+  -- None
+
+  ---------------------------------------------------------------------------
+  -- Declare signals.
+  ---------------------------------------------------------------------------
+
+  signal sync_serial_a          : std_logic;
+  signal sync_serial_b          : std_logic;
+  signal sync_serial_c          : std_logic;
+  signal stop_bit               : std_logic;
+  signal edge_delay             : std_logic;
+  signal start_edge             : std_logic;
+  signal delay_line             : std_logic_vector(150 downto 0) := (others => '0');
+  signal valid_delay            : std_logic_vector(151 downto 0) := (others => '0');
+  signal data_strobe_int        : std_logic := '0';
+  signal valid_char             : std_logic := '0';
+  signal purge                  : std_logic := '0';
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+  begin
+
+  ---------------------------------------------------------------------------
+  -- Synchronize serial input.
+  ---------------------------------------------------------------------------
+
+  sync_reg_a : FD
+  port map (D => serial_in, Q => sync_serial_a, C => icap_clk);
+  sync_reg_b : FD
+  port map (D => sync_serial_a, Q => sync_serial_b, C => icap_clk);
+  sync_reg_c : FD
+  port map (D => sync_serial_b, Q => sync_serial_c, C => icap_clk);
+  sync_reg_d : FD
+  port map (D => sync_serial_c, Q => stop_bit, C => icap_clk);
+
+  ---------------------------------------------------------------------------
+  -- Create a delay line to pick out various bits of the serial signal by
+  -- capturing the incoming signal at 16 times the baud rate.  This block
+  -- also delays the valid_char pulse, the length of time equivalent to
+  -- purge the data shift register.  This is used to generate purge signal
+  -- which locks out additional strobes that might otherwise occur while
+  -- the most recent captured data makes it way out of the shift register.
+  ---------------------------------------------------------------------------
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      if (en_16_x_baud = '1') then
+        delay_line <= (delay_line(149 downto 0) & stop_bit) after TCQ;
+        valid_char <= (not edge_delay and start_edge and stop_bit and not purge) after TCQ;
+        valid_delay <= (valid_delay(150 downto 0) & valid_char) after TCQ;
+        purge <= ((purge or valid_char) and not valid_delay(151)) after TCQ;
+      end if;
+    end if;
+  end process;
+
+  data_out   <= (delay_line( 15) &
+                 delay_line( 31) &
+                 delay_line( 47) &
+                 delay_line( 63) &
+                 delay_line( 79) &
+                 delay_line( 95) &
+                 delay_line(111) &
+                 delay_line(127));
+  edge_delay  <= delay_line(149);
+  start_edge  <= delay_line(150);
+
+  ---------------------------------------------------------------------------
+  -- Generate a single-cycle output data strobe when the character is valid.
+  ---------------------------------------------------------------------------
+
+  process (icap_clk)
+  begin
+    if rising_edge (icap_clk) then
+      data_strobe_int <= (valid_char and en_16_x_baud) after TCQ;
+    end if;
+  end process;
+
+  data_strobe <= data_strobe_int;
+
+  ---------------------------------------------------------------------------
+  --
+  ---------------------------------------------------------------------------
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_512x111/sync_fifo_512x111.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_512x111/sync_fifo_512x111.xci
new file mode 100644
index 0000000..4054ef0
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_512x111/sync_fifo_512x111.xci
@@ -0,0 +1,422 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>sync_fifo_512x111</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">sync_fifo_512x111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_512x41/sync_fifo_512x41.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_512x41/sync_fifo_512x41.xci
new file mode 100644
index 0000000..bb9095c
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_512x41/sync_fifo_512x41.xci
@@ -0,0 +1,424 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>sync_fifo_512x41</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">41</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">41</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">sync_fifo_512x41</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">41</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">41</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_FWFT_512x36/sync_fifo_FWFT_512x36.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_FWFT_512x36/sync_fifo_FWFT_512x36.xci
new file mode 100644
index 0000000..697bad6
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_FWFT_512x36/sync_fifo_FWFT_512x36.xci
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>sync_fifo_FWFT_512x36</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">511</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">sync_fifo_FWFT_512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">511</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progempty32_FWFT_512x104/sync_fifo_progempty32_FWFT_512x104.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progempty32_FWFT_512x104/sync_fifo_progempty32_FWFT_512x104.xci
new file mode 100644
index 0000000..01cc946
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progempty32_FWFT_512x104/sync_fifo_progempty32_FWFT_512x104.xci
@@ -0,0 +1,427 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>sync_fifo_progempty32_FWFT_512x104</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">33</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">511</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">sync_fifo_progempty32_FWFT_512x104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">33</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">511</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">104</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">Single_Programmable_Empty_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Extra_Logic" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progfull364_progempty128_512x36/sync_fifo_progfull364_progempty128_512x36.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progfull364_progempty128_512x36/sync_fifo_progfull364_progempty128_512x36.xci
new file mode 100644
index 0000000..aba0aec
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progfull364_progempty128_512x36/sync_fifo_progfull364_progempty128_512x36.xci
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>sync_fifo_progfull364_progempty128_512x36</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">129</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">364</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">363</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">sync_fifo_progfull364_progempty128_512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">129</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">364</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">363</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">Single_Programmable_Empty_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progfull504_progempty128_512x36/sync_fifo_progfull504_progempty128_512x36.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progfull504_progempty128_512x36/sync_fifo_progfull504_progempty128_512x36.xci
new file mode 100644
index 0000000..c6477e2
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progfull504_progempty128_512x36/sync_fifo_progfull504_progempty128_512x36.xci
@@ -0,0 +1,424 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>sync_fifo_progfull504_progempty128_512x36</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="12.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">sync_fifo_progfull504_progempty128_512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">504</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">503</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">Single_Programmable_Empty_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">129</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">129</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">504</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">503</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progfull504_progempty32_512x36/sync_fifo_progfull504_progempty32_512x36.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progfull504_progempty32_512x36/sync_fifo_progfull504_progempty32_512x36.xci
new file mode 100644
index 0000000..233fe69
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/sync_fifo_progfull504_progempty32_512x36/sync_fifo_progfull504_progempty32_512x36.xci
@@ -0,0 +1,426 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>sync_fifo_progfull504_progempty32_512x36</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">33</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">504</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">503</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">sync_fifo_progfull504_progempty32_512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">33</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">504</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">503</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">Single_Programmable_Empty_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/vio36/vio36.xci b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/vio36/vio36.xci
new file mode 100644
index 0000000..3274dc9
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/ip/vio36/vio36.xci
@@ -0,0 +1,822 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>vio36</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SIGNAL_CLOCK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN100_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN101_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN102_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN103_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN104_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN105_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN106_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN107_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN108_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN109_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN10_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN110_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN111_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN112_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN113_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN114_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN115_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN116_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN117_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN118_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN119_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN11_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN120_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN121_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN122_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN123_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN124_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN125_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN126_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN127_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN128_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN129_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN12_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN130_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN131_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN132_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN133_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN134_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN135_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN136_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN137_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN138_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN139_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN13_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN140_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN141_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN142_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN143_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN144_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN145_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN146_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN147_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN148_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN149_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN14_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN150_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN151_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN152_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN153_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN154_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN155_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN156_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN157_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN158_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN159_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN15_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN160_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN161_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN162_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN163_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN164_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN165_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN166_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN167_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN168_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN169_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN16_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN170_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN171_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN172_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN173_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN174_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN175_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN176_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN177_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN178_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN179_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN17_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN180_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN181_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN182_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN183_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN184_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN185_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN186_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN187_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN188_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN189_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN18_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN190_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN191_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN192_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN193_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN194_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN195_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN196_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN197_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN198_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN199_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN19_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN1_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN200_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN201_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN202_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN203_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN204_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN205_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN206_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN207_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN208_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN209_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN20_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN210_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN211_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN212_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN213_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN214_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN215_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN216_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN217_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN218_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN219_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN21_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN220_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN221_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN222_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN223_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN224_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN225_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN226_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN227_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN228_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN229_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN22_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN230_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN231_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN232_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN233_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN234_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN235_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN236_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN237_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN238_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN239_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN23_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN240_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN241_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN242_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN243_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN244_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN245_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN246_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN247_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN248_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN249_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN24_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN250_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN251_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN252_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN253_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN254_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN255_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN25_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN26_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN27_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN28_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN29_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN2_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN30_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN31_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN32_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN33_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN34_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN35_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN36_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN37_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN38_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN39_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN3_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN40_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN41_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN42_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN43_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN44_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN45_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN46_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN47_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN48_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN49_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN4_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN50_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN51_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN52_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN53_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN54_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN55_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN56_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN57_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN58_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN59_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN5_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN60_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN61_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN62_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN63_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN64_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN65_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN66_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN67_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN68_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN69_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN6_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN70_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN71_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN72_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN73_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN74_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN75_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN76_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN77_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN78_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN79_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN7_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN80_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN81_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN82_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN83_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN84_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN85_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN86_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN87_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN88_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN89_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN8_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN90_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN91_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN92_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN93_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN94_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN95_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN96_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN97_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN98_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN99_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN9_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT0_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT0_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT100_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT100_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT101_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT101_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT102_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT102_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT103_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT103_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT104_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT104_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT105_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT105_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT106_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT106_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT107_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT107_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT108_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT108_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT109_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT109_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT10_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT10_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT110_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT110_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT111_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT111_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT112_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT112_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT113_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT113_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT114_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT114_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT115_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT115_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT116_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT116_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT117_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT117_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT118_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT118_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT119_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT119_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT11_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT11_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT120_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT120_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT121_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT121_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT122_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT122_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT123_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT123_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT124_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT124_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT125_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT125_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT126_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT126_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT127_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT127_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT128_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT128_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT129_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT129_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT12_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT12_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT130_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT130_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT131_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT131_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT132_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT132_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT133_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT133_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT134_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT134_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT135_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT135_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT136_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT136_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT137_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT137_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT138_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT138_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT139_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT139_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT13_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT13_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT140_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT140_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT141_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT141_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT142_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT142_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT143_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT143_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT144_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT144_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT145_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT145_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT146_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT146_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT147_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT147_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT148_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT148_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT149_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT149_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT14_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT14_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT150_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT150_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT151_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT151_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT152_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT152_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT153_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT153_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT154_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT154_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT155_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT155_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT156_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT156_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT157_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT157_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT158_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT158_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT159_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT159_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT15_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT15_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT160_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT160_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT161_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT161_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT162_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT162_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT163_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT163_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT164_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT164_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT165_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT165_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT166_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT166_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT167_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT167_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT168_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT168_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT169_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT169_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT16_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT16_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT170_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT170_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT171_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT171_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT172_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT172_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT173_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT173_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT174_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT174_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT175_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT175_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT176_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT176_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT177_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT177_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT178_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT178_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT179_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT179_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT17_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT17_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT180_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT180_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT181_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT181_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT182_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT182_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT183_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT183_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT184_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT184_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT185_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT185_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT186_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT186_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT187_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT187_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT188_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT188_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT189_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT189_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT18_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT18_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT190_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT190_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT191_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT191_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT192_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT192_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT193_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT193_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT194_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT194_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT195_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT195_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT196_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT196_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT197_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT197_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT198_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT198_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT199_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT199_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT19_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT19_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT1_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT1_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT200_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT200_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT201_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT201_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT202_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT202_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT203_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT203_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT204_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT204_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT205_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT205_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT206_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT206_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT207_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT207_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT208_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT208_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT209_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT209_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT20_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT20_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT210_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT210_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT211_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT211_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT212_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT212_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT213_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT213_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT214_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT214_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT215_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT215_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT216_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT216_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT217_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT217_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT218_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT218_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT219_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT219_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT21_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT21_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT220_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT220_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT221_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT221_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT222_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT222_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT223_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT223_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT224_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT224_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT225_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT225_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT226_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT226_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT227_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT227_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT228_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT228_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT229_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT229_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT22_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT22_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT230_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT230_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT231_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT231_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT232_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT232_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT233_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT233_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT234_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT234_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT235_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT235_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT236_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT236_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT237_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT237_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT238_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT238_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT239_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT239_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT23_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT23_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT240_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT240_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT241_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT241_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT242_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT242_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT243_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT243_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT244_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT244_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT245_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT245_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT246_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT246_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT247_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT247_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT248_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT248_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT249_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT249_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT24_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT24_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT250_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT250_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT251_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT251_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT252_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT252_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT253_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT253_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT254_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT254_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT255_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT255_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT25_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT25_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT26_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT26_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT27_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT27_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT28_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT28_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT29_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT29_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT2_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT2_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT30_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT30_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT31_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT31_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT32_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT32_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT33_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT33_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT34_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT34_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT35_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT35_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT36_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT36_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT37_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT37_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT38_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT38_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT39_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT39_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT3_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT3_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT40_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT40_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT41_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT41_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT42_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT42_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT43_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT43_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT44_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT44_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT45_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT45_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT46_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT46_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT47_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT47_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT48_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT48_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT49_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT49_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT4_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT4_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT50_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT50_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT51_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT51_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT52_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT52_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT53_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT53_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT54_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT54_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT55_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT55_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT56_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT56_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT57_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT57_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT58_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT58_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT59_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT59_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT5_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT5_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT60_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT60_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT61_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT61_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT62_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT62_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT63_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT63_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT64_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT64_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT65_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT65_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT66_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT66_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT67_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT67_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT68_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT68_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT69_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT69_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT6_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT6_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT70_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT70_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT71_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT71_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT72_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT72_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT73_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT73_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT74_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT74_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT75_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT75_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT76_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT76_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT77_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT77_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT78_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT78_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT79_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT79_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT7_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT7_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT80_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT80_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT81_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT81_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT82_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT82_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT83_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT83_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT84_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT84_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT85_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT85_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT86_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT86_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT87_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT87_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT88_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT88_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT89_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT89_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT8_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT8_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT90_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT90_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT91_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT91_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT92_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT92_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT93_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT93_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT94_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT94_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT96_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT96_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k160t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg484</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_PROBE_IN" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.C_PROBE_OUT0_WIDTH" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/reboot.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/reboot.vhd
new file mode 100644
index 0000000..b78cf59
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/reboot.vhd
@@ -0,0 +1,119 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity reboot is
+  port (
+    TRIGGER : in std_logic;
+    SYSCLK  : in std_logic
+    );
+end reboot;
+
+architecture Behavioral of reboot is
+  
+
+  type FSM_STATE is (STATE_00, STATE_01, STATE_02, STATE_03, STATE_04, STATE_05,
+                     STATE_06, STATE_07, STATE_08, STATE_09, STATE_10, STATE_11);
+  signal NEXT_STATE : FSM_STATE                    := STATE_00;
+  signal CE         : std_logic                     := '1';
+  signal I          : std_logic_vector(31 downto 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
+  signal ICAP_WRITE : std_logic                     := '1';
+begin
+  
+  ICAPE2_inst : ICAPE2
+    generic map (
+      ICAP_WIDTH        => "X32",
+      SIM_CFG_FILE_NAME => "NONE"
+      )
+    port map (
+      O     => open,                       -- 32-bit output (not used)
+      CLK   => SYSCLK,                  -- 1-bit Clock Input
+      CSIB  => CE,                      -- 1-bit Active-Low ICAP Enable
+      I     => I,                       -- 32-bit iConfiguration data input bus
+      RDWRB => ICAP_WRITE               -- 1-bit input: Read/Write Select input
+      );
+
+  process(SYSCLK)
+  begin
+    if (falling_edge(SYSCLK)) then
+      if (TRIGGER = '0') then
+        case NEXT_STATE is
+          when STATE_00 =>
+            ICAP_WRITE <= '1';
+            CE         <= '1';
+            I          <= x"00000000";
+            NEXT_STATE <= STATE_01;
+          when STATE_01 =>
+            ICAP_WRITE <= '0';
+            CE         <= '1';
+            I          <= x"00000000";
+            NEXT_STATE <= STATE_02;
+          when STATE_02 =>
+            ICAP_WRITE <= '0';
+            CE         <= '0';
+            I          <= x"00000000";
+            NEXT_STATE <= STATE_03;
+          when STATE_03 =>
+            ICAP_WRITE <= '0';
+            CE         <= '0';
+            I          <= x"FFFFFFFF";  -- dummy word
+            NEXT_STATE <= STATE_04;
+          when STATE_04 =>
+            ICAP_WRITE <= '0';
+            CE         <= '0';
+            I          <= x"5599AA66";  -- sync word
+            NEXT_STATE <= STATE_05;
+          when STATE_05 =>
+            ICAP_WRITE <= '0';
+            CE         <= '0';
+            I          <= x"04000000";  -- Type 1 NO OP
+            NEXT_STATE <= STATE_06;
+          when STATE_06 =>
+            ICAP_WRITE <= '0';
+            CE         <= '0';
+            I          <= x"0C400080";  -- Type 1 Write 1 word to WBSTAR
+            NEXT_STATE <= STATE_07;
+          when STATE_07 =>
+            ICAP_WRITE <= '0';
+            CE         <= '0';
+            I          <= x"00000000";  -- x"00800000" Warm boot start address
+            NEXT_STATE <= STATE_08;
+          when STATE_08 =>
+            ICAP_WRITE <= '0';
+            CE         <= '0';
+            I          <= x"0C000180";  -- Type 1 write 1 word to CMD
+            NEXT_STATE <= STATE_09;
+          when STATE_09 =>
+            ICAP_WRITE <= '0';
+            CE         <= '0';
+            I          <= x"000000F0";  -- IPROG command
+            NEXT_STATE <= STATE_10;
+          when STATE_10 =>
+            ICAP_WRITE <= '0';
+            CE         <= '0';
+            I          <= x"04000000";  -- Type 1 NO OP
+            NEXT_STATE <= STATE_11;
+          when STATE_11 =>
+            ICAP_WRITE <= '0';
+            CE         <= '1';          -- deassert CE
+            I          <= x"04000000";
+            NEXT_STATE <= STATE_11;
+          when others =>
+            ICAP_WRITE <= '1';
+            CE         <= '1';
+            I          <= x"AAAAAAAA";
+            NEXT_STATE <= STATE_00;
+        end case;
+      else
+        ICAP_WRITE <= '1';
+        CE         <= '1';
+        I          <= x"AAAABBBB";
+        NEXT_STATE <= STATE_00;
+      end if;
+    end if;
+  end process;
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/sem_module.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/sem_module.vhd
new file mode 100644
index 0000000..14578f4
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/sem_module.vhd
@@ -0,0 +1,359 @@
+-----------------------------------------------------------------------------
+--
+--
+--
+-----------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /
+-- \   \   \/    Core:          sem
+--  \   \        Entity:        sem_sem_example
+--  /   /        Filename:      sem_sem_example.vhd
+-- /___/   /\    Purpose:       System level design example.
+-- \   \  /  \
+--  \___\/\___\
+--
+-----------------------------------------------------------------------------
+--
+-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Description:
+--
+-- This entity is the system level design example, the top level of what is
+-- intended for physical implementation.  This entity is essentially an HDL
+-- netlist of sub-entities used to construct the solution.  The system level
+-- design example is customized by the Vivado IP Catalog.
+--
+-----------------------------------------------------------------------------
+--
+-- Port Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- clk                           input  System clock; the entire system is
+--                                      synchronized to this signal, which
+--                                      is distributed on a global clock
+--                                      buffer and referred to as icap_clk.
+--
+-- status_heartbeat              output Heartbeat signal for external watch
+--                                      dog timer implementation; pulses
+--                                      when readback runs.  Synchronous to
+--                                      icap_clk.
+--
+-- status_initialization         output Indicates initialization is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_observation            output Indicates observation is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_correction             output Indicates correction is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_classification         output Indicates classification is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_injection              output Indicates injection is taking
+--                                      place.  Synchronous to icap_clk.
+--
+-- status_essential              output Indicates essential error condition.
+--                                      Qualified by de-assertion of the
+--                                      status_classification signal, and
+--                                      is synchronous to icap_clk.
+--
+-- status_uncorrectable          output Indicates uncorrectable error
+--                                      condition. Qualified by de-assertion
+--                                      of the status_correction signal, and
+--                                      is synchronous to icap_clk.
+--
+-- monitor_tx                    output Serial status output.  Synchronous
+--                                      to icap_clk, but received externally
+--                                      by another device as an asynchronous
+--                                      signal, perceived as lower bitrate.
+--                                      Uses 8N1 protocol.
+--
+-- monitor_rx                    input  Serial command input.  Asynchronous
+--                                      signal provided by another device at
+--                                      a lower bitrate, synchronized to the
+--                                      icap_clk and oversampled.  Uses 8N1
+--                                      protocol.
+--
+-----------------------------------------------------------------------------
+--
+-- Generic and Constant Definition:
+--
+-- Name                          Type   Description
+-- ============================= ====== ====================================
+-- TCQ                           int    Sets the clock-to-out for behavioral
+--                                      descriptions of sequential logic.
+--
+-----------------------------------------------------------------------------
+--
+-- Entity Dependencies:
+--
+-- sem_sem_example
+-- |
+-- +- sem (sem_controller)
+-- |
+-- +- sem_sem_cfg
+-- |
+-- +- sem_sem_mon
+-- |
+-- +- sem_sem_hid
+-- |
+-- +- IBUF (unisim)
+-- |
+-- \- BUFGCE (unisim)
+--
+-----------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+-----------------------------------------------------------------------------
+-- Entity
+-----------------------------------------------------------------------------
+
+entity sem_module is
+port (
+	clk                           : in    std_logic;
+	status_heartbeat              : out   std_logic;
+	status_initialization         : out   std_logic;
+	status_observation            : out   std_logic;
+	status_correction             : out   std_logic;
+	status_classification         : out   std_logic;
+	status_injection              : out   std_logic;
+	status_essential              : out   std_logic;
+	status_uncorrectable          : out   std_logic
+	);
+end sem_module;
+
+-----------------------------------------------------------------------------
+-- Architecture
+-----------------------------------------------------------------------------
+
+architecture xilinx of sem_module is
+
+  ---------------------------------------------------------------------------
+  -- Define local constants.
+  ---------------------------------------------------------------------------
+
+  constant TCQ : time := 1 ps;
+
+  ---------------------------------------------------------------------------
+  -- Declare non-library components.
+  ---------------------------------------------------------------------------
+
+  component sem
+  port (
+    status_heartbeat            : out   std_logic;
+    status_initialization       : out   std_logic;
+    status_observation          : out   std_logic;
+    status_correction           : out   std_logic;
+    status_classification       : out   std_logic;
+    status_injection            : out   std_logic;
+    status_essential            : out   std_logic;
+    status_uncorrectable        : out   std_logic;
+    monitor_txdata              : out   std_logic_vector(7 downto 0);
+    monitor_txwrite             : out   std_logic;
+    monitor_txfull              : in    std_logic;
+    monitor_rxdata              : in    std_logic_vector(7 downto 0);
+    monitor_rxread              : out   std_logic;
+    monitor_rxempty             : in    std_logic;
+    inject_strobe               : in    std_logic;
+    inject_address              : in    std_logic_vector(39 downto 0);
+    fecc_crcerr                 : in    std_logic;
+    fecc_eccerr                 : in    std_logic;
+    fecc_eccerrsingle           : in    std_logic;
+    fecc_syndromevalid          : in    std_logic;
+    fecc_syndrome               : in    std_logic_vector(12 downto 0);
+    fecc_far                    : in    std_logic_vector(25 downto 0);
+    fecc_synbit                 : in    std_logic_vector(4 downto 0);
+    fecc_synword                : in    std_logic_vector(6 downto 0);
+    icap_o                      : in    std_logic_vector(31 downto 0);
+    icap_i                      : out   std_logic_vector(31 downto 0);
+    icap_csib                   : out   std_logic;
+    icap_rdwrb                  : out   std_logic;
+    icap_clk                    : in    std_logic;
+    icap_request                : out   std_logic;
+    icap_grant                  : in    std_logic
+    );
+  end component;
+
+  component sem_sem_cfg
+  port (
+    fecc_crcerr                 : out   std_logic;
+    fecc_eccerr                 : out   std_logic;
+    fecc_eccerrsingle           : out   std_logic;
+    fecc_syndromevalid          : out   std_logic;
+    fecc_syndrome               : out   std_logic_vector(12 downto 0);
+    fecc_far                    : out   std_logic_vector(25 downto 0);
+    fecc_synbit                 : out   std_logic_vector(4 downto 0);
+    fecc_synword                : out   std_logic_vector(6 downto 0);
+    icap_o                      : out   std_logic_vector(31 downto 0);
+    icap_i                      : in    std_logic_vector(31 downto 0);
+    icap_clk                    : in    std_logic;
+    icap_csib                   : in    std_logic;
+    icap_rdwrb                  : in    std_logic
+    );
+  end component;
+
+
+  ---------------------------------------------------------------------------
+  -- Declare signals.
+  ---------------------------------------------------------------------------
+  signal fecc_crcerr            : std_logic;
+  signal fecc_eccerr            : std_logic;
+  signal fecc_eccerrsingle      : std_logic;
+  signal fecc_syndromevalid     : std_logic;
+  signal fecc_syndrome          : std_logic_vector(12 downto 0);
+  signal fecc_far               : std_logic_vector(25 downto 0);
+  signal fecc_synbit            : std_logic_vector(4 downto 0);
+  signal fecc_synword           : std_logic_vector(6 downto 0);
+  signal icap_o                 : std_logic_vector(31 downto 0);
+  signal icap_i                 : std_logic_vector(31 downto 0);
+  signal icap_csib              : std_logic;
+  signal icap_rdwrb             : std_logic;
+  signal icap_unused            : std_logic;
+  signal icap_grant             : std_logic;
+  signal icap_clk               : std_logic;
+
+attribute mark_debug : string;
+-- attribute mark_debug of monitor_rx : signal is "true";
+
+			
+  begin
+
+  ---------------------------------------------------------------------------
+  -- This design (the example, including the controller itself) is fully
+  -- synchronous; the global clock buffer is instantiated here to drive
+  -- the icap_clk signal.
+  ---------------------------------------------------------------------------
+
+  example_bufg : BUFGCE
+  port map (
+    I => clk,
+    O => icap_clk,
+    CE => '1'
+    );
+
+  ---------------------------------------------------------------------------
+  -- The controller sub-entity is the kernel of the soft error mitigation
+  -- solution.  The port list is dynamic based on the IP core options.
+  ---------------------------------------------------------------------------
+
+  sem_controller : sem
+  port map (
+    status_heartbeat => status_heartbeat,
+    status_initialization => status_initialization,
+    status_observation => status_observation,
+    status_correction => status_correction,
+    status_classification => status_classification,
+    status_injection => status_injection,
+    status_essential => status_essential,
+    status_uncorrectable => status_uncorrectable,
+    monitor_txdata => open,
+    monitor_txwrite => open,
+    monitor_txfull => '0',
+    monitor_rxdata => (others => '0'),
+    monitor_rxread => open,
+    monitor_rxempty => '1',
+    inject_strobe => '0',
+    inject_address => (others => '0'),
+    fecc_crcerr => fecc_crcerr,
+    fecc_eccerr => fecc_eccerr,
+    fecc_eccerrsingle => fecc_eccerrsingle,
+    fecc_syndromevalid => fecc_syndromevalid,
+    fecc_syndrome => fecc_syndrome,
+    fecc_far => fecc_far,
+    fecc_synbit => fecc_synbit,
+    fecc_synword => fecc_synword,
+    icap_o => icap_o,
+    icap_i => icap_i,
+    icap_csib => icap_csib,
+    icap_rdwrb => icap_rdwrb,
+    icap_clk => icap_clk,
+    icap_request => icap_unused,
+    icap_grant => icap_grant
+    );
+
+  icap_grant <= '1';
+
+  ---------------------------------------------------------------------------
+  -- The cfg sub-entity contains the device specific primitives to access
+  -- the internal configuration port and the frame crc/ecc status signals.
+  ---------------------------------------------------------------------------
+
+  sem_cfg : sem_sem_cfg
+  port map (
+    fecc_crcerr => fecc_crcerr,
+    fecc_eccerr => fecc_eccerr,
+    fecc_eccerrsingle => fecc_eccerrsingle,
+    fecc_syndromevalid => fecc_syndromevalid,
+    fecc_syndrome => fecc_syndrome,
+    fecc_far => fecc_far,
+    fecc_synbit => fecc_synbit,
+    fecc_synword => fecc_synword,
+    icap_o => icap_o,
+    icap_i => icap_i,
+    icap_csib => icap_csib,
+    icap_rdwrb => icap_rdwrb,
+    icap_clk => icap_clk
+    );
+
+
+end architecture xilinx;
+
+-----------------------------------------------------------------------------
+--
+-----------------------------------------------------------------------------
diff --git a/FEE_ADC32board/modules/SystemMonitorModule.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/sensors/SystemMonitorModule.vhd
similarity index 91%
rename from FEE_ADC32board/modules/SystemMonitorModule.vhd
rename to FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/sensors/SystemMonitorModule.vhd
index a045402..853f80b 100644
--- a/FEE_ADC32board/modules/SystemMonitorModule.vhd
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/sensors/SystemMonitorModule.vhd
@@ -12,46 +12,46 @@ USE ieee.std_logic_unsigned.all;
 USE ieee.std_logic_arith.all;
 
 ----------------------------------------------------------------------------------
--- SystemMonitorModule
+-- SystemMonitorModule
 -- Reads FPGA system parameters: temperature and voltages
--- The Xilinx System Monitor measures several FPGA physical operating parameters.
+-- The Xilinx System Monitor measures several FPGA physical operating parameters.
 -- For further information see Xilinx documentation
 -- The settings and parameters are accessable with a 16-bits data bus and 7 bits address bus.
 -- This module initializes the System Monitor so that the main parameters are continuously measured.
--- This behaviour can bechanged because all settings are accessable.
---
---
--- The main settings addresses and their initialize value are:
+-- This behaviour can be changed because all settings are accessable.
+--
+--
+-- The main settings addresses and their initialize value are:
 --   0x40 : 1000 -- average 16
 --   0x41 : 2000 -- enable sequence & alarms, no calibration
 --   0x42 : 1400 -- clock division = 20 : 50MHz/2.5MHz
 --   0x48 : 3700 -- select temp,VCCint,VCCaux,VrefP,VrefN
 --   0x49 : 0000 -- not Vaux
 --   0x4a : 3700 -- enable averaging
---   0x4b : 0000 -- disable averaging Vau
---   0x4c : 0000 -- unipolar inputs
---   0x4d : 0000 -- unipolar inputs
---   0x4e : 0000 -- default Acquisition Time
---   0x4f : 0000 -- default Acquisition Time
---
---
--- The system parameters are measured with an 10 bits ADC:
---
--- For die Temperature (address 0) :
--- Temperature(degreeC) = (ADCcode * 503.975)/1024 - 273.15
---
--- For VCCint (1V, address=1), VCCaux (2.5V, address=2), VrefP(2.5V, address=4) : 
--- Supply Voltage (Volts) = (ADCcode / 1024) x 3V
---
--- For VrefN(0.0V, address=5) :
--- Voltage (Volts) = ADCcode(2-complement) * 977uV
---
+--   0x4b : 0000 -- disable averaging Vau
+--   0x4c : 0000 -- unipolar inputs
+--   0x4d : 0000 -- unipolar inputs
+--   0x4e : 0000 -- default Acquisition Time
+--   0x4f : 0000 -- default Acquisition Time
+--
+--
+-- The system parameters are measured with an 10 bits ADC:
+--
+-- For die Temperature (address 0) :
+-- Temperature(degreeC) = (ADCcode * 503.975)/1024 - 273.15
+--
+-- For VCCint (1V, address=1), VCCaux (2.5V, address=2), VrefP(2.5V, address=4) : 
+-- Supply Voltage (Volts) = (ADCcode / 1024) x 3V
+--
+-- For VrefN(0.0V, address=5) :
+-- Voltage (Volts) = ADCcode(2-complement) * 977uV
+--
 --
 --
 -- Library:
 --
 -- Generics:
---
+--
 -- Inputs:
 --     clock : clock for the system monitor (must not exceed 100MHz)
 --     reset : reset
@@ -78,80 +78,76 @@ entity SystemMonitorModule is
     Port ( 
 		clock                   : in std_logic;
 		reset                   : in std_logic;
-		address                 : in std_logic_vector(6 downto 0);
+		address                 : in std_logic_vector(6 downto 0);
 		data_write              : in std_logic;
-		data_in                 : in std_logic_vector(15 downto 0);
-		data_read               : in std_logic;
-		data_out                : out std_logic_vector(15 downto 0);
-		alarms                  : out std_logic_vector(7 downto 0);
-		testword0               : out std_logic_vector(35 downto 0));
+		data_in                 : in std_logic_vector(15 downto 0);
+		data_read               : in std_logic;
+		data_out                : out std_logic_vector(15 downto 0);
+		alarms                  : out std_logic_vector(7 downto 0));
 end SystemMonitorModule;
 
 
 architecture Behavioral of SystemMonitorModule is
 
-component SystemMonitorVirtex
-    port (
-          DADDR_IN            : in  STD_LOGIC_VECTOR (6 downto 0);     -- Address bus for the dynamic reconfiguration port
-          DCLK_IN             : in  STD_LOGIC;                         -- Clock input for the dynamic reconfiguration port
-          DEN_IN              : in  STD_LOGIC;                         -- Enable Signal for the dynamic reconfiguration port
-          DI_IN               : in  STD_LOGIC_VECTOR (15 downto 0);    -- Input data bus for the dynamic reconfiguration port
-          DWE_IN              : in  STD_LOGIC;                         -- Write Enable for the dynamic reconfiguration port
-          RESET_IN            : in  STD_LOGIC;                         -- Reset signal for the System Monitor control logic
-          BUSY_OUT            : out  STD_LOGIC;                        -- ADC Busy signal
-          CHANNEL_OUT         : out  STD_LOGIC_VECTOR (4 downto 0);    -- Channel Selection Outputs
-          DO_OUT              : out  STD_LOGIC_VECTOR (15 downto 0);   -- Output data bus for dynamic reconfiguration port
-          DRDY_OUT            : out  STD_LOGIC;                        -- Data ready signal for the dynamic reconfiguration port
-          EOC_OUT             : out  STD_LOGIC;                        -- End of Conversion Signal
-          EOS_OUT             : out  STD_LOGIC;                        -- End of Sequence Signal
-          JTAGBUSY_OUT        : out  STD_LOGIC;                        -- JTAG DRP transaction is in progress signal
-          JTAGLOCKED_OUT      : out  STD_LOGIC;                        -- DRP port lock request has been made by JTAG
-          JTAGMODIFIED_OUT    : out  STD_LOGIC;                        -- Indicates JTAG Write to the DRP has occurred
-          OT_OUT              : out  STD_LOGIC;                        -- Over-Temperature alarm output
-          VCCAUX_ALARM_OUT    : out  STD_LOGIC;                        -- VCCAUX-sensor alarm output
-          VCCINT_ALARM_OUT    : out  STD_LOGIC;                        -- VCCINT-sensor alarm output
-          USER_TEMP_ALARM_OUT : out  STD_LOGIC;                        -- Temperature-sensor alarm output
-          VP_IN               : in  STD_LOGIC;                         -- Dedicated Analog Input Pair
-          VN_IN               : in  STD_LOGIC
-);
+component SystemMonitorKintex
+    port (
+          DADDR_IN            : in  STD_LOGIC_VECTOR (6 downto 0);     -- Address bus for the dynamic reconfiguration port
+          DCLK_IN             : in  STD_LOGIC;                         -- Clock input for the dynamic reconfiguration port
+          DEN_IN              : in  STD_LOGIC;                         -- Enable Signal for the dynamic reconfiguration port
+          DI_IN               : in  STD_LOGIC_VECTOR (15 downto 0);    -- Input data bus for the dynamic reconfiguration port
+          DWE_IN              : in  STD_LOGIC;                         -- Write Enable for the dynamic reconfiguration port
+          RESET_IN            : in  STD_LOGIC;                         -- Reset signal for the System Monitor control logic
+          BUSY_OUT            : out  STD_LOGIC;                        -- ADC Busy signal
+          CHANNEL_OUT         : out  STD_LOGIC_VECTOR (4 downto 0);    -- Channel Selection Outputs
+          DO_OUT              : out  STD_LOGIC_VECTOR (15 downto 0);   -- Output data bus for dynamic reconfiguration port
+          DRDY_OUT            : out  STD_LOGIC;                        -- Data ready signal for the dynamic reconfiguration port
+          EOC_OUT             : out  STD_LOGIC;                        -- End of Conversion Signal
+          EOS_OUT             : out  STD_LOGIC;                        -- End of Sequence Signal
+          JTAGBUSY_OUT        : out  STD_LOGIC;                        -- JTAG DRP transaction is in progress signal
+          JTAGLOCKED_OUT      : out  STD_LOGIC;                        -- DRP port lock request has been made by JTAG
+          JTAGMODIFIED_OUT    : out  STD_LOGIC;                        -- Indicates JTAG Write to the DRP has occurred
+          OT_OUT              : out  STD_LOGIC;                        -- Over-Temperature alarm output
+          VCCAUX_ALARM_OUT    : out  STD_LOGIC;                        -- VCCAUX-sensor alarm output
+          VCCINT_ALARM_OUT    : out  STD_LOGIC;                        -- VCCINT-sensor alarm output
+          USER_TEMP_ALARM_OUT : out  STD_LOGIC;                        -- Temperature-sensor alarm output
+          ALARM_OUT          : out STD_LOGIC;                         -- OR'ed output of all the Alarms
+          VP_IN               : in  STD_LOGIC;                         -- Dedicated Analog Input Pair
+          VN_IN               : in  STD_LOGIC
+);
 end component;
-constant NROFREGISTERS : natural :=11;
+
+
+constant NROFREGISTERS : natural :=11;
 type registerarray_type is array (0 to NROFREGISTERS-1) 
 			of std_logic_vector (23 downto 0);
-
-constant REGISTERARRAY : registerarray_type := (
-x"401000", -- average 16
+
+constant REGISTERARRAY : registerarray_type := (
+x"401000", -- average 16
 x"412000", -- enable sequence & alarms, no calibration
 x"421400", -- clock division = 20 : 50MHz/2.5MHz
 x"483700", -- select temp,VCCint,VCCaux,VrefP,VrefN
 x"490000", -- not Vaux
 x"4a3700", -- enable averaging
-x"4b0000", -- disable averaging Vau
-x"4c0000", -- unipolar inputs
-x"4d0000", -- unipolar inputs
-x"4e0000", -- default Acquisition Time
-x"4f0000"); -- default Acquisition Time
-
-
-
-
-
-
-
- 
+x"4b0000", -- disable averaging Vau
+x"4c0000", -- unipolar inputs
+x"4d0000", -- unipolar inputs
+x"4e0000", -- default Acquisition Time
+x"4f0000"); -- default Acquisition Time
+
+
 --0x40 : 1000 -- average 16
 --0x41 : 2000 -- enable sequence & alarms, no calibration
 --0x42 : 1400 -- clock division = 20 : 50MHz/2.5MHz
 --0x48 : 3700 -- select temp,VCCint,VCCaux,VrefP,VrefN
 --0x49 : 0000 -- not Vaux
 --0x4a : 3700 -- enable averaging
---0x4b : 0000 -- disable averaging Vau
---0x4c : 0000 -- unipolar inputs
---0x4d : 0000 -- unipolar inputs
---0x4e : 0000 -- default Acquisition Time
---0x4f : 0000 -- default Acquisition Time
-
-
+--0x4b : 0000 -- disable averaging Vau
+--0x4c : 0000 -- unipolar inputs
+--0x4d : 0000 -- unipolar inputs
+--0x4e : 0000 -- default Acquisition Time
+--0x4f : 0000 -- default Acquisition Time
+
+
 signal registerindex_S        : integer range 0 to NROFREGISTERS;
 signal accesscounter_S        : integer range 0 to 7;
 signal delaycounter_S         : std_logic_vector(11 downto 0);
@@ -160,8 +156,8 @@ signal sysmon_active_S        : std_logic := '0';
 signal DR_address_S           : std_logic_vector(6 downto 0);
 signal DR_address_init_S      : std_logic_vector(6 downto 0);
 signal DR_enable_S            : std_logic := '0';
-signal DR_data_in_S           : std_logic_vector(15 downto 0);
-signal DR_data_init_S         : std_logic_vector(15 downto 0);
+signal DR_data_in_S           : std_logic_vector(15 downto 0);
+signal DR_data_init_S         : std_logic_vector(15 downto 0);
 
 signal DR_write_S             : std_logic := '0';
 signal DR_write_init_S        : std_logic := '0';
@@ -177,105 +173,105 @@ signal OverTemperatur_alarm_S : std_logic := '0';
 signal VCCaux_alarm_S         : std_logic := '0';
 signal VCCint_alarm_S         : std_logic := '0';
 signal USERtemp_alarm_S       : std_logic := '0';
-
-
-		
-begin
-
-
-SystemMonitorVirtex1: SystemMonitorVirtex port map ( 
-		DADDR_IN => DR_address_S,
-		DCLK_IN => clock,
-		DEN_IN => DR_enable_S,
-		DI_IN => DR_data_in_S,
-		DWE_IN => DR_write_S,
-		RESET_IN => reset,
-		BUSY_OUT => ADC_busy_S,
-		CHANNEL_OUT => channel_S,
-		DO_OUT => DR_data_out_S,
-		DRDY_OUT => DR_ready_S,
-		EOC_OUT => EndofConversion_S,
-		EOS_OUT => EndofSequence_S,
-		JTAGBUSY_OUT => open,
-		JTAGLOCKED_OUT => open,
-		JTAGMODIFIED_OUT => open,
-		OT_OUT => OverTemperatur_alarm_S,
-		VCCAUX_ALARM_OUT => VCCaux_alarm_S,
-		VCCINT_ALARM_OUT => VCCint_alarm_S,
-		USER_TEMP_ALARM_OUT => USERtemp_alarm_S,
-		VP_IN => '0',
-		VN_IN => '0'
-		);
-
-alarms(3 downto 0) <= OverTemperatur_alarm_S & VCCaux_alarm_S & VCCint_alarm_S & USERtemp_alarm_S;
-alarms(7 downto 4) <= (others => '0');
-
-DR_address_S <= DR_address_init_S when sysmon_active_S='0' else address;
-DR_enable_S <= '1' when ((data_read='1') and (sysmon_active_S='1')) or (DR_write_S='1') else '0';
-data_out <= DR_data_out_S;
-
-DR_write_S <= '1' when ((data_write='1') and (sysmon_active_S='1')) or (DR_write_init_S='1') else '0';
-DR_data_in_S <= data_in when (sysmon_active_S='1') else DR_data_init_S;
-
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of DR_data_out_S : signal is "true";
+-- attribute mark_debug of DR_address_S : signal is "true";
+-- attribute mark_debug of sysmon_active_S : signal is "true";
+-- attribute mark_debug of DR_enable_S : signal is "true";
+-- attribute mark_debug of ADC_busy_S : signal is "true";
+-- attribute mark_debug of DR_ready_S : signal is "true";
+-- attribute mark_debug of EndofConversion_S : signal is "true";
+-- attribute mark_debug of EndofSequence_S : signal is "true";
+-- attribute mark_debug of channel_S : signal is "true";
+
+begin
+
+
+SystemMonitorKintex1: SystemMonitorKintex port map ( 
+		DADDR_IN => DR_address_S,
+		DCLK_IN => clock,
+		DEN_IN => DR_enable_S,
+		DI_IN => DR_data_in_S,
+		DWE_IN => DR_write_S,
+		RESET_IN => reset,
+		BUSY_OUT => ADC_busy_S,
+		CHANNEL_OUT => channel_S,
+		DO_OUT => DR_data_out_S,
+		DRDY_OUT => DR_ready_S,
+		EOC_OUT => EndofConversion_S,
+		EOS_OUT => EndofSequence_S,
+		JTAGBUSY_OUT => open,
+		JTAGLOCKED_OUT => open,
+		JTAGMODIFIED_OUT => open,
+		OT_OUT => OverTemperatur_alarm_S,
+		VCCAUX_ALARM_OUT => VCCaux_alarm_S,
+		VCCINT_ALARM_OUT => VCCint_alarm_S,
+		ALARM_OUT => open,
+		USER_TEMP_ALARM_OUT => USERtemp_alarm_S,
+		VP_IN => '0',
+		VN_IN => '0'
+		);
+
+alarms(3 downto 0) <= OverTemperatur_alarm_S & VCCaux_alarm_S & VCCint_alarm_S & USERtemp_alarm_S;
+alarms(7 downto 4) <= (others => '0');
+
+DR_address_S <= DR_address_init_S when sysmon_active_S='0' else address;
+DR_enable_S <= '1' when ((data_read='1') and (sysmon_active_S='1')) or (DR_write_S='1') else '0';
+data_out <= DR_data_out_S;
+
+DR_write_S <= '1' when ((data_write='1') and (sysmon_active_S='1')) or (DR_write_init_S='1') else '0';
+DR_data_in_S <= data_in when (sysmon_active_S='1') else DR_data_init_S;
+
 process(clock)
 begin
 	if (rising_edge(clock)) then 
-		if (reset = '1') and (sysmon_active_S='1') then 
-			DR_write_init_S <= '0';
-			sysmon_active_S <= '0';
-			registerindex_S <= 0;
-			accesscounter_S <= 0;
+		if (reset = '1') and (sysmon_active_S='1') then 
+			DR_write_init_S <= '0';
+			sysmon_active_S <= '0';
+			registerindex_S <= 0;
+			accesscounter_S <= 0;
 			delaycounter_S <= (others => '0');
-		else
-			if sysmon_active_S='0' then
-				if delaycounter_S(delaycounter_S'left)='0' then 
-					delaycounter_S <= delaycounter_S+1;
-					DR_write_init_S <= '0';
-					registerindex_S <= 0;
-					accesscounter_S <= 0;
-					DR_address_init_S <= (others => '0');
-				else
-					if accesscounter_S<7 then
-						if accesscounter_S=0 then
-							DR_address_init_S <= REGISTERARRAY(registerindex_S)(22 downto 16);
-							DR_data_init_S <= REGISTERARRAY(registerindex_S)(15 downto 0);
-							DR_write_init_S <= '1';
-						else
-							DR_write_init_S <= '0';
-						end if;
-						accesscounter_S <= accesscounter_S+1;
-					else
-						accesscounter_S <= 0;
-						DR_write_init_S <= '0';
-						if registerindex_S<NROFREGISTERS then
-							registerindex_S <= registerindex_S+1;
-						else
-							DR_address_init_S <= (others => '0');
-							DR_data_init_S <= (others => '0');
-							registerindex_S <= 0;
-							sysmon_active_S <= '1';
-						end if;
-					end if;
-				end if;
-			else
-				accesscounter_S <= 0;
-				DR_write_init_S <= '0';
-			end if;
+			DR_address_init_S <= (others => '0');
+			DR_data_init_S <= (others => '0');
+		else
+			if sysmon_active_S='0' then
+				if delaycounter_S(delaycounter_S'left)='0' then 
+					delaycounter_S <= delaycounter_S+1;
+					DR_write_init_S <= '0';
+					registerindex_S <= 0;
+					accesscounter_S <= 0;
+					DR_address_init_S <= (others => '0');
+				else
+					if accesscounter_S<7 then
+						if accesscounter_S=0 then
+							DR_address_init_S <= REGISTERARRAY(registerindex_S)(22 downto 16);
+							DR_data_init_S <= REGISTERARRAY(registerindex_S)(15 downto 0);
+							DR_write_init_S <= '1';
+						else
+							DR_write_init_S <= '0';
+						end if;
+						accesscounter_S <= accesscounter_S+1;
+					else
+						accesscounter_S <= 0;
+						DR_write_init_S <= '0';
+						if registerindex_S<NROFREGISTERS then
+							registerindex_S <= registerindex_S+1;
+						else
+							DR_address_init_S <= (others => '0');
+							DR_data_init_S <= (others => '0');
+							registerindex_S <= 0;
+							sysmon_active_S <= '1';
+						end if;
+					end if;
+				end if;
+			else
+				accesscounter_S <= 0;
+				DR_write_init_S <= '0';
+			end if;
 		end if;
 	end if;
 end process;
 
-testword0(15 downto 0) <= DR_data_out_S;
-testword0(22 downto 16) <= DR_address_S;
-testword0(23) <= sysmon_active_S;
-testword0(24) <= '0';
-testword0(25) <= DR_enable_S;
-testword0(26) <= ADC_busy_S;
-testword0(27) <= DR_ready_S;
-testword0(28) <= EndofConversion_S;
-testword0(29) <= EndofSequence_S;
-testword0(30) <= '1' when OverTemperatur_alarm_S='1' or VCCaux_alarm_S='1' or VCCint_alarm_S='1' or USERtemp_alarm_S='1' else '0';
-testword0(35 downto 31) <= channel_S;
-
 end Behavioral;
 
diff --git a/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/sensors/TMP104module.vhd b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/sensors/TMP104module.vhd
new file mode 100644
index 0000000..b20efb0
--- /dev/null
+++ b/FEE_ADC32board/FEE_Kintex_ADCboard_Vivado/sources/sensors/TMP104module.vhd
@@ -0,0 +1,296 @@
+---------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   9-10-2012
+-- Module Name:   TMP104module
+-- Description:   Module to access TMP104 temperature sensor
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- TMP104module
+-- Module to access TMP104 temperature sensor with smaart interface:
+-- Serial connection with baudrate from 4.8 to 114 kbps
+--   startbit=0, stopbit=1
+--   first byte : calibrate = 0x55
+--   second byte : command
+--   third byte (after 1 wait cycle) : data, receive or send
+--
+-- sequence:
+--     startbit=0 1 0 1 0 1 0 1 0 stopbit=1 startbit=0 p0 p1 p2 p3 p4 p5 p6 p7 stopbit=1 
+--     wait=1 startbit=0 d0 d1 d2 d3 d4 d5 d6 d7 stopbit=1
+--
+-- TMP104:
+--     d<7..0> : data (receive or send)
+--     p0 = R/W
+--     p2,p1 = 00=read temp, 01=configuration, 10=low temperature, 11= high temperature
+--     p6..p3 = in/id : 0000
+--     p7 = GLB : global command
+--
+--
+-- Library:
+-- 
+-- Generics:
+--     TMP104CLOCKDIVIDER : number of clockcycles for 1 smaart bit (defines baudrate)
+--     TMP104INTERVAL : number of smaart clock cycles between temperature measurements
+-- 
+-- Inputs:
+--     clock : clock input
+--     reset : synchronous reset 
+--     smaart_in : smaart serial data from TMP01
+-- 
+-- Outputs:
+--     smaart_out : smaart serial data to TMP01
+--     temperature : measured temperature in binary twos complement format, range -55 to +127 degree C
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity TMP104module is
+	generic (
+		TMP104CLOCKDIVIDER      : natural := 1628;
+		TMP104INTERVAL          : natural := 50
+		);
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		smaart_in               : in std_logic;
+		smaart_out              : out std_logic;
+		temperature             : out std_logic_vector (7 downto 0)
+		);
+end TMP104module;
+
+architecture Behavioral of TMP104module is
+
+
+constant BYTE_CALIBRATE : std_logic_vector(7 downto 0) := "01010101";
+constant CMD_INITIALIZE : std_logic_vector(7 downto 0) := "10001100";
+constant CMD_ASSIGN : std_logic_vector(7 downto 0) := "10010000";
+constant CMD_CLEARINTERRUPT : std_logic_vector(7 downto 0) := "10101001";
+constant CMD_RESET : std_logic_vector(7 downto 0) := "10110100";
+constant CMD_READTEMPERATURE : std_logic_vector(7 downto 0) := "00000001";
+
+
+type command_state_type is (RST,INIT,WAITREADY,ASSIGN,GETTEMPERATURE);
+signal command_state_S        : command_state_type := INIT;
+signal return_state_S         : command_state_type := INIT;
+
+type smaart_state_type is (WAIT0,START0,CALIBRATE,STOP0,START1,COMMAND,STOP1,WAIT1,START2,DATA,STOP2);
+signal smaart_state_S        : smaart_state_type := WAIT0;
+							
+signal clockdivcounter_S      : integer range 0 to TMP104CLOCKDIVIDER := 0;
+signal clockdiv_full_S        : std_logic := '0';
+signal clockdiv_half_S        : std_logic := '0';
+signal clockdivphase_S        : std_logic := '0';
+
+signal command_counter_S      : integer range 0 to TMP104INTERVAL := 0;
+signal bitcounter_S           : integer range 0 to 7 := 0;
+signal command_S              : std_logic_vector (7 downto 0) := x"00"; 
+signal senddata_S             : std_logic_vector (7 downto 0) := x"02"; 
+signal receivedata_S          : std_logic_vector (7 downto 0) := x"00"; 
+signal start_smaart_s         : std_logic := '0';
+signal smaart_out_S           : std_logic := '1';
+constant TMP104CLOCKDIVIDERdiv2 : integer range 0 to TMP104CLOCKDIVIDER := TMP104CLOCKDIVIDER/2;
+begin
+
+smaart_out <= smaart_out_S;
+
+clockdiv_process: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if clockdivcounter_S<TMP104CLOCKDIVIDERdiv2-1 then
+			clockdivcounter_S <= clockdivcounter_S+1;
+			clockdiv_full_S <= '0';
+			clockdiv_half_S <= '0';
+		else
+			clockdivcounter_S <= 0;
+			if clockdivphase_S='0' then
+				clockdiv_full_S <= '1';
+				clockdiv_half_S <= '0';
+				clockdivphase_S <= '1';
+			else
+				clockdiv_full_S <= '0';
+				clockdiv_half_S <= '1';
+				clockdivphase_S <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+command_process: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if reset='1' then
+			command_counter_S <= 0;
+			start_smaart_S <= '0';
+			command_state_S <= INIT;
+		else
+			if clockdiv_full_S='1' then
+				case command_state_S is
+					when RST =>
+						if command_counter_S<TMP104INTERVAL-1 then
+							start_smaart_S <= '0';
+							command_counter_S <= command_counter_S+1;
+						else
+							start_smaart_S <= '1';
+							command_counter_S <= 0;
+							command_S <= CMD_RESET;
+							command_state_S <= WAITREADY;
+							return_state_S <= INIT;
+						end if;
+					when INIT =>
+						if command_counter_S<TMP104INTERVAL-1 then
+							start_smaart_S <= '0';
+							command_counter_S <= command_counter_S+1;
+						else
+							start_smaart_S <= '1';
+							command_counter_S <= 0;
+							command_S <= CMD_INITIALIZE;
+							command_state_S <= WAITREADY;
+							return_state_S <= ASSIGN;
+						end if;
+					when ASSIGN =>
+						if command_counter_S<TMP104INTERVAL-1 then
+							start_smaart_S <= '0';
+							command_counter_S <= command_counter_S+1;
+						else
+							start_smaart_S <= '1';
+							command_counter_S <= 0;
+							command_S <= CMD_ASSIGN;
+							command_state_S <= WAITREADY;
+							return_state_S <= GETTEMPERATURE;
+						end if;
+					when WAITREADY => 
+						start_smaart_S <= '0';
+						command_counter_S <= 0;
+						if smaart_state_S=WAIT0 then
+							command_state_S <= return_state_S; 
+						end if;
+					when GETTEMPERATURE =>
+						if command_counter_S=0 then
+							temperature <= receivedata_S;
+						end if;
+						if command_counter_S<TMP104INTERVAL-1 then
+							start_smaart_S <= '0';
+							command_counter_S <= command_counter_S+1;
+						else
+							start_smaart_S <= '1';
+							command_counter_S <= 0;
+							command_S <= CMD_READTEMPERATURE;
+							command_state_S <= WAITREADY;
+							return_state_S <= GETTEMPERATURE;
+						end if;
+					when others =>
+						start_smaart_S <= '0';
+						command_counter_S <= 0;
+						command_state_S <= INIT;
+				end case;
+			else
+				start_smaart_S <= '0';
+			end if;
+		end if;
+	end if;
+end process;
+
+smaart_process: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if reset='1' then
+			smaart_out_S <= '1';
+			bitcounter_S <= 0;
+			smaart_state_S <= WAIT0;
+		else
+			if (clockdiv_full_S='1') and ((smaart_state_S=DATA) or (smaart_state_S=STOP2))  then
+				if (smaart_state_S=STOP2) then
+					receivedata_S(7) <= smaart_in;
+				elsif (bitcounter_S>0) then
+					receivedata_S(bitcounter_S-1) <= smaart_in;
+				end if;
+			end if;			
+			if start_smaart_S='1' then
+				smaart_out_S <= '1';
+				bitcounter_S <= 0;
+				smaart_state_S <= START0;
+			elsif clockdiv_full_S='1' then
+				case smaart_state_S is
+					when WAIT0 =>
+						smaart_out_S <= '1';
+						bitcounter_S <= 0;
+						smaart_state_S <= WAIT0;
+					when START0 =>
+						smaart_out_S <= '0';
+						bitcounter_S <= 0;
+						smaart_state_S <= CALIBRATE;
+					when CALIBRATE =>
+						smaart_out_S <= BYTE_CALIBRATE(bitcounter_S);
+						if bitcounter_S<7 then
+							bitcounter_S <= bitcounter_S+1;
+						else
+							bitcounter_S <= 0;
+							smaart_state_S <= STOP0;
+						end if;
+					when STOP0 =>
+						smaart_out_S <= '1';
+						bitcounter_S <= 0;
+						smaart_state_S <= START1;
+					when START1 =>
+						smaart_out_S <= '0';
+						bitcounter_S <= 0;
+						smaart_state_S <= COMMAND;
+					when COMMAND =>
+						smaart_out_S <= command_S(bitcounter_S);
+						if bitcounter_S<7 then
+							bitcounter_S <= bitcounter_S+1;
+						else
+							bitcounter_S <= 0;
+							smaart_state_S <= STOP1;
+						end if;
+					when STOP1 =>
+						smaart_out_S <= '1';
+						bitcounter_S <= 0;
+						smaart_state_S <= WAIT1;
+					when WAIT1 =>
+						smaart_out_S <= '1';
+						bitcounter_S <= 0;
+						smaart_state_S <= START2;
+					when START2 =>
+						if (command_S(0)='1') or (command_S(7)='1') then -- init or read
+							smaart_out_S <= '1';
+						else
+							smaart_out_S <= '0';
+						end if;
+						bitcounter_S <= 0;
+						smaart_state_S <= DATA;
+					when DATA =>
+						if (command_S(0)='1') or (command_S(7)='1') then -- init or read
+							smaart_out_S <= '1';
+						else
+							smaart_out_S <= senddata_S(bitcounter_S);
+						end if;
+						if bitcounter_S<7 then
+							bitcounter_S <= bitcounter_S+1;
+						else
+							bitcounter_S <= 0;
+							smaart_state_S <= STOP2;
+						end if;
+					when STOP2 =>
+						smaart_out_S <= '1';
+						bitcounter_S <= 0;
+						smaart_state_S <= WAIT0;
+					when others => 
+						smaart_out_S <= '1';
+						bitcounter_S <= 0;
+						smaart_state_S <= WAIT0;
+				end case;
+			end if;
+		end if;
+	end if;
+end process;
+			
+
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_MWDfilter_unsigned.vhd b/FEE_ADC32board/FEE_modules/FEE_MWDfilter_unsigned.vhd
new file mode 100644
index 0000000..56c87bf
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_MWDfilter_unsigned.vhd
@@ -0,0 +1,283 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI-cart/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   2008, 22-04-2015
+-- Module Name:   FEE_MWDfilter_unsigned
+-- Description:   Moving Window Deconvolution filter for unsigned signals
+-- Modifications:
+--   23-04-2015   offset added
+--   24-04-2015   signed output added
+--   30-04-2015   unsigned output added
+--   28-02-2017   decrease output bits
+--   08-03-2017   width of the MWD input changed to width+1 for less resources
+--   05-04-2017   rewritten in std_logic_vector instead of integers
+----------------------------------------------------------------------------------
+
+------------------------------------------------------------------------------------------------------
+-- FEE_MWDfilter_unsigned
+--		Moving Window Deconvolution filter for unsigned signals.
+--      Formula:
+--      N(k) = A(k) - A(k-w) + 1/T * sum(A(k-1)..A(k-w))
+--          k : index in ADC data stream
+--          N(k) : Output value
+--          A(k) : new ADC value
+--          A(k-w) : old ADC value (w samples before)
+--          w : Width of window
+--          T : Tau = exponential decay time constant to compensate for
+--          sum(A(k-1)..A(k-w)) : summation of w ADC values
+--
+-- generics
+--		MWD_DATABITS : number of ADC bits
+--		MWD_WIDTHBITS : number of bits for the width
+--		MWD_SCALEBITS : number of bits for tau factor, also scaling for calculations
+--		
+-- inputs
+--		clock : ADC sampling clock 
+--		reset : synchrounous reset
+--		data_in : ADC sampling data, signed
+--		MWD_width : width plus 1 of the MWD filter 
+--		MWD_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq)
+--
+-- outputs
+--      data_out_signed : signed MWD data output, width depends on MWD_WIDTHBITS
+--		data_out_unsigned : unsigned MWD data output (half of the range is added), width depends on MWD_WIDTHBITS
+--
+-- components
+--		shift_register : shift register for std_logic_vector
+--
+------------------------------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_SIGNED.ALL;
+
+entity FEE_MWDfilter_unsigned is
+	generic (
+		MWD_DATABITS            : natural := 14;
+		MWD_WIDTHBITS           : natural := 8;
+		MWD_SCALEBITS           : natural := 15
+		);
+    Port (
+		clock                   : in std_logic;
+		reset                   : in  std_logic;
+		data_in                 : in  std_logic_vector((MWD_DATABITS-1) downto 0);
+		MWD_width               : in  std_logic_vector((MWD_WIDTHBITS-1) downto 0);
+		MWD_tau_factor          : in  std_logic_vector((MWD_SCALEBITS-1) downto 0);
+		data_out_signed         : out  std_logic_vector(MWD_DATABITS downto 0);
+		data_out_unsigned       : out  std_logic_vector(MWD_DATABITS downto 0));
+end FEE_MWDfilter_unsigned; 
+
+architecture Behavioral of FEE_MWDfilter_unsigned is
+
+component shift_register_small is
+	generic (
+		width                   : natural := MWD_DATABITS;
+		depthbits               : natural := MWD_WIDTHBITS
+		);
+    port (
+		clock                   : in  std_logic; 
+		data_in                 : in std_logic_vector((width-1) downto 0); 
+		depth                   : in std_logic_vector((depthbits-1) downto 0);
+		data_out                : out  std_logic_vector((width-1) downto 0));
+end component;
+
+constant ZEROS                  : std_logic_vector(63 downto 0) := (others => '0');
+constant ONES                   : std_logic_vector(63 downto 0) := (others => '1');
+
+signal initializing_S           : std_logic := '1';
+signal MWD_disable_S            : std_logic := '1';
+
+signal resetcounter_S           : std_logic_vector(MWD_WIDTHBITS+2 downto 0);
+signal MWD_width_S              : std_logic_vector(MWD_WIDTHBITS-1 downto 0);
+signal data_in_signed_S         : std_logic_vector(MWD_DATABITS downto 0);
+signal shiftregin_S             : std_logic_vector(MWD_DATABITS-1 downto 0);
+signal data_in_delayed_S        : std_logic_vector(MWD_DATABITS-1 downto 0);
+signal data_in_delayed0_S       : std_logic_vector(MWD_DATABITS-1 downto 0);
+signal MWD_tau_factor_S         : std_logic_vector(MWD_SCALEBITS downto 0);
+signal summated_samples_S       : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0);
+
+signal data_out_S               : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0) := (others => '0'); -- signed
+signal data_out_scaled_S        : std_logic_vector(MWD_DATABITS downto 0) := (others => '0'); -- signed
+
+signal mult_S                   : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0) := (others => '0'); -- signed
+signal add_S                    : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0) := (others => '0'); -- signed
+signal data_in_signed1_S        : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0);
+
+attribute mark_debug : string;
+attribute mark_debug of reset : signal is "true";
+attribute mark_debug of MWD_disable_S : signal is "true";
+attribute mark_debug of initializing_S : signal is "true";
+--attribute mark_debug of resetcounter_S : signal is "true";
+--attribute mark_debug of shiftregin_S : signal is "true";
+--attribute mark_debug of data_in_delayed_S : signal is "true";
+--attribute mark_debug of summated_samples_S : signal is "true";
+--attribute mark_debug of data_out_S : signal is "true";
+
+begin
+
+process(clock)
+begin
+	if rising_edge(clock) then
+		if (reset='1') or (MWD_width_S/=MWD_width) or (MWD_width_S=ZEROS(MWD_WIDTHBITS-1 downto 0)) then
+			MWD_disable_S <= '1';
+		else
+			MWD_disable_S <= '0';
+		end if;
+		MWD_width_S <= MWD_width;
+	end if;
+end process;
+
+data_in_signed_S <= ('0' & data_in)-conv_std_logic_vector(2**(MWD_DATABITS-1),MWD_DATABITS+1);
+shiftregin_S <= (others => '0') when (initializing_S='1') or (MWD_disable_S='1') else data_in_signed_S(MWD_DATABITS-1 downto 0);
+gen_shiftreg2: if MWD_WIDTHBITS>1 generate
+shift_register_MWD: shift_register_small
+	generic map(
+		width => MWD_DATABITS,
+		depthbits => MWD_WIDTHBITS)
+	port map(
+		clock => clock,
+		data_in => shiftregin_S,
+		depth => MWD_width_S,
+		data_out => data_in_delayed_S);
+end generate;
+gen_noshiftreg2: if MWD_WIDTHBITS<=1 generate
+-- shift_register_MWD: shift_register_small 
+	-- generic map(
+		-- width => MWD_DATABITS,
+		-- depthbits => 2)
+	-- port map(
+		-- clock => clock,
+		-- data_in => shiftregin_S,
+		-- depth => "01",
+		-- data_out => data_in_delayed_S);
+	process(clock)
+	begin
+		if rising_edge(clock) then
+			data_in_delayed_S <= data_in_delayed0_S;
+			data_in_delayed0_S <= shiftregin_S;
+		end if;
+	end process;
+end generate;
+
+data_out_signed <= data_out_scaled_S;
+data_out_scaled_S <= 
+	(MWD_DATABITS => '1', others => '0') when conv_integer(signed(data_out_S))<-2**MWD_DATABITS else
+	(MWD_DATABITS => '0', others => '1') when conv_integer(signed(data_out_S))>=2**MWD_DATABITS else
+	data_out_S(MWD_DATABITS downto 0);
+	
+--data_out_unsigned <= conv_std_logic_vector(conv_integer(signed(data_out_S))+2**(MWD_DATABITS+MWD_WIDTHBITS),MWD_DATABITS+MWD_WIDTHBITS+2)(MWD_DATABITS+MWD_WIDTHBITS downto 0);
+data_out_unsigned <= conv_std_logic_vector(conv_integer(signed(data_out_scaled_S))+2**MWD_DATABITS,MWD_DATABITS+2)(MWD_DATABITS downto 0);
+
+-- process(clock)
+-- variable shiftregin_V :  integer range -2**(MWD_DATABITS-1) to 2**(MWD_DATABITS-1)-1;
+-- variable data_in_delayed_V :  integer range -2**(MWD_DATABITS-1) to 2**(MWD_DATABITS-1)-1;
+-- variable bdiff_V :  integer range -2**MWD_DATABITS to 2**MWD_DATABITS-1;
+-- variable multiplied_V :  std_logic_vector(MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS-1 downto 0); -- signed
+-- variable multiplied_scaledback_V :  std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS-1 downto 0); -- signed
+-- begin
+	-- if rising_edge(clock) then
+		-- shiftregin_V  := conv_integer(signed(shiftregin_S));
+		-- data_in_delayed_V  := conv_integer(signed(data_in_delayed_S));
+		-- bdiff_V := shiftregin_V - data_in_delayed_V;	 
+		-- multiplied_V := conv_std_logic_vector(conv_integer(signed('0' & MWD_tau_factor_S)) * summated_samples_S,MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS); -- signed multiply : MWD_SCALEBITS + MWD_WIDTHBITS + MWD_WIDTHBITS
+		-- multiplied_scaledback_V := multiplied_V(MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS-1 downto MWD_SCALEBITS);
+		
+		-- if MWD_disable_S='1' then
+			-- data_out_S <= conv_std_logic_vector(conv_integer(signed(data_in_signed_S)),MWD_DATABITS+MWD_WIDTHBITS+1);
+			-- resetcounter_S <= (others => '0');
+			-- initializing_S <= '1';
+			-- summated_samples_S <= 0;
+		-- elsif initializing_S='1' then
+			-- if resetcounter_S(resetcounter_S'left-1)='0' then
+				-- resetcounter_S <= resetcounter_S+1;
+			-- else
+				-- initializing_S <= '0';
+			-- end if;
+			-- summated_samples_S <= 0;
+		-- else
+			-- if	resetcounter_S(resetcounter_S'left)='0' then
+				-- resetcounter_S <= resetcounter_S+1;
+			-- else
+				-- data_out_S <= conv_std_logic_vector(bdiff_V + conv_integer(signed(multiplied_scaledback_V)),MWD_DATABITS+MWD_WIDTHBITS+1);	 -- signed	
+			-- end if;
+			-- summated_samples_S <= (summated_samples_S+shiftregin_V)-data_in_delayed_V;
+		-- end if;
+	-- end if;
+-- end process;
+MWD_tau_factor_S <= '0' & MWD_tau_factor;
+
+
+-- process(clock)
+-- begin
+	-- if rising_edge(clock) then
+		-- if (MWD_disable_S='1') or (reset='1') then
+			-- data_out_S <= conv_std_logic_vector(conv_integer(signed(data_in_signed_S)),MWD_DATABITS+MWD_WIDTHBITS+1);
+			-- resetcounter_S <= (others => '0');
+			-- initializing_S <= '1';
+			-- summated_samples_S <= 0;
+		-- elsif initializing_S='1' then
+			-- if resetcounter_S(resetcounter_S'left-1)='0' then
+				-- resetcounter_S <= resetcounter_S+1;
+			-- else
+				-- initializing_S <= '0';
+			-- end if;
+			-- summated_samples_S <= 0;
+		-- else
+			-- if	resetcounter_S(resetcounter_S'left)='0' then
+				-- resetcounter_S <= resetcounter_S+1;
+			-- else
+				-- data_out_S <= conv_std_logic_vector((conv_integer(signed(shiftregin_S)) - conv_integer(signed(data_in_delayed_S))) + 
+					-- conv_integer(signed(conv_std_logic_vector(conv_integer(signed('0' & MWD_tau_factor_S)) * summated_samples_S,MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS)(MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS-1 downto MWD_SCALEBITS))),MWD_DATABITS+MWD_WIDTHBITS+1);	 -- signed	
+			-- end if;
+			-- summated_samples_S <= (summated_samples_S+conv_integer(signed(shiftregin_S)))-conv_integer(signed(data_in_delayed_S));
+		-- end if;
+	-- end if;
+-- end process;
+
+data_out_S <= add_S + mult_S when initializing_S='0' else data_in_signed1_S;
+
+data_in_signed1_S(MWD_DATABITS+MWD_WIDTHBITS downto MWD_DATABITS) <= (others => data_in_signed_S(MWD_DATABITS-1));
+data_in_signed1_S(MWD_DATABITS-1 downto 0) <= data_in_signed_S(MWD_DATABITS-1 downto 0);
+
+
+process(clock)
+variable mult_V : std_logic_vector(MWD_SCALEBITS+1+MWD_DATABITS+MWD_WIDTHBITS+1-1 downto 0);
+variable shiftregin_V : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0);
+variable data_in_delayed_V : std_logic_vector(MWD_DATABITS+MWD_WIDTHBITS downto 0);
+begin
+	if rising_edge(clock) then
+		if (MWD_disable_S='1') or (reset='1') then
+--			data_out_S <= (others => '0');
+--			data_out_S(MWD_DATABITS-1 downto 0) <= data_in_signed_S(MWD_DATABITS-1 downto 0);
+			resetcounter_S <= (others => '0');
+			initializing_S <= '1';
+			summated_samples_S <= (others => '0');
+		elsif initializing_S='1' then
+			if resetcounter_S(resetcounter_S'left-1)='0' then
+				resetcounter_S <= resetcounter_S+1;
+			else
+				initializing_S <= '0';
+			end if;
+			summated_samples_S <= (others => '0');
+		else
+			if	resetcounter_S(resetcounter_S'left)='0' then
+				resetcounter_S <= resetcounter_S+1;
+			else
+				mult_V := MWD_tau_factor_S * summated_samples_S;
+				mult_S <= mult_V(MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS downto MWD_SCALEBITS);
+				shiftregin_V(MWD_DATABITS+MWD_WIDTHBITS downto MWD_DATABITS) := (others => shiftregin_S(MWD_DATABITS-1));
+				shiftregin_V(MWD_DATABITS-1 downto 0) := shiftregin_S;
+				data_in_delayed_V(MWD_DATABITS+MWD_WIDTHBITS downto MWD_DATABITS) := (others => data_in_delayed_S(MWD_DATABITS-1));
+				data_in_delayed_V(MWD_DATABITS-1 downto 0) := data_in_delayed_S;
+				add_S <= shiftregin_V - data_in_delayed_V;
+--				data_out_S <= (shiftregin_S  + mult_V(MWD_SCALEBITS+MWD_DATABITS+MWD_WIDTHBITS downto MWD_SCALEBITS)) - data_in_delayed_S;
+			end if;
+			summated_samples_S <= (summated_samples_S+shiftregin_S)-data_in_delayed_S;
+		end if;
+	end if;
+end process;
+
+
+end Behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_SODAfrequencydiv5.vhd b/FEE_ADC32board/FEE_modules/FEE_SODAfrequencydiv5.vhd
index 3eaa682..b8a7ba8 100644
--- a/FEE_ADC32board/FEE_modules/FEE_SODAfrequencydiv5.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_SODAfrequencydiv5.vhd
@@ -69,7 +69,9 @@ error <= '1' when (SODAerror_S='1') or (clockdiv5error_S='1') or (clockbiterror_
 clockdiv5 <= clockdiv5_S;
 	
 rxrecclk_bufrdiv5_i : BUFR
-	generic map ( BUFR_DIVIDE => "5" )
+	generic map ( 
+		BUFR_DIVIDE => "5",
+		SIM_DEVICE => "VIRTEX6")
 	port map (
 		CE => '1',
 		CLR => clockdiv5_reset_S,
diff --git a/FEE_ADC32board/FEE_modules/FEE_adc32_module.vhd b/FEE_ADC32board/FEE_modules/FEE_adc32_module.vhd
index cdb51cb..ea82d1f 100644
--- a/FEE_ADC32board/FEE_modules/FEE_adc32_module.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_adc32_module.vhd
@@ -1,5 +1,5 @@
 ----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
+-- Company:       KVI-cart/RUG/Groningen University
 -- Engineer:      Peter Schakel
 -- Create Date:   15-02-2012
 -- Module Name:   FEE_adc32_module
@@ -13,6 +13,13 @@
 --   02-10-2014   onesecondpulse, errorbyte
 --   10-10-2014   Integral as measurement for the energy instead of maximum
 --   16-10-2014   inpipe signals
+--   24-04-2015   Moving Window Deconvolution added
+--   19-08-2015   Force_hit added: force waveform acquisition with SODA command
+--   06-10-2015   Invert ADCs bit added
+--   05-11-2015   Data errorbit added
+--   28-10-2016   Enable_waveform to FEE_pulse_and_pileup_waveforms
+--   23-02-2017   Parallel data from Feature Extraction instead of 36-bits, MWD registers in FE
+--   05-04-2017   Second Feature Extraction module for detecting errors due to radiation
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -26,7 +33,7 @@ use UNISIM.VComponents.all;
 ----------------------------------------------------------------------------------
 -- FEE_adc32_module
 -- Module for Front End Electronics: fiber connection, adc waveform reading & multiplexers & feature extraction.
--- ADC data is analysed or put in waveforms if regarded as pileup. 
+-- ADC data is analysed or put in waveforms. 
 --
 -- The data is sent to the GTP/GTX transceiver in packets
 -- Slow control processes slow-control packets on the fiber to/from the multiplexer board.
@@ -41,7 +48,8 @@ use UNISIM.VComponents.all;
 --         bit3: enable waveforms
 --         bit 17..16 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read
 --         bit 18 = reset/initializes FPGA System monitor
---    board_register B: read
+--    board_register B: 
+--       read
 --         bit1 : Data Taken enabled (enable and disabled is done with SODA packets)
 --         bit 5..4 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare
 --         bit 15..6 = ADC value from FPGA System monitor
@@ -53,7 +61,7 @@ use UNISIM.VComponents.all;
 --            bit20 : error : transmit data error, multiplexer error
 --            bit21 : error : receive data buffer overrun
 --            bit22 : error : adc data buffer overrun
---            bit23 : error : data taken disabled
+--            bit23 : error : data taken disabled
 --    board_register C: automatically sent
 --            data not important; this slowcontrol command indicates buffer full
 --    board_register D: read
@@ -61,58 +69,91 @@ use UNISIM.VComponents.all;
 --
 -- Each ADC has its own set of registers. See module FEE_pulse_and_pileup_waveforms for addresses.
 --
+-- The resulting output data packets : 4 32-bit words, with CRC8 in last word
+--   0xDA ADCnumber(7..0) superburstnumber(15..0)
+--   timestamp(15..0) energy(15..0) 
+--   CF_before(15..0) CF_after(15..0)
+--   0000 statusbyte(7..0) CRC8(7..0)
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+--   0x5C address(7..0) replybit 0000000 data(31..24)
+--   data(23..0) CRC8(7..0)
+--
+-- The waveform packets : 32-bit words, with CRC8 in last word
+--   0xAF ADCnumber(7..0) superburstnumber(15..0)
+--   timestamp(15..0) 0x00 statusbyte(7..0)
+--   0 adc0(14..0) 0 adc1(14..0) : 2 adc-samples 15 bits signed
+--   0 adc2(14..0) 0 adc3(14..0) : next 2 adc-samples 15 bits signed
+--   .........
+--   1 adcn(14..0) 1 00 CRC8(7..0) : last 32-bit word: last adc-sample 15 bits signed
+--         or
+--   0 0000 1 00 CRC8(7..0) : last 32-bit word: no sample--
 --
 -- 
 -- Library
 --     work.panda_package :  for type declarations and constants
 --
 -- Generics:
---     NROFADCS : number of the adc's, probably 16
---     ADCBITS : number of ADC-bits
---     BASELINE_BWBITS : number of bits for the baseline IIR filter bandwidth
---     WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
---     ADCCLOCKFREQUENCY : Frequency of the ADCclock in Hz
---     CF_DELAYBITS : number of bits for the constant fraction delay
---     CF_FRACTIONBIT : number of bits for the calculated fraction of the precise timestamp
---     IDIVMAXBITS : number of bits for maximum to integral ratio check
---     INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+--    NROFADCS : number of the adc's, probably 16
+--    ADCBITS : number of ADC-bits
+--    MWD_WIDTHBITS : number of bits for the width
+--    MWD_SCALEBITS : number of bits for tau factor, also scaling for calculations
+--    MWD2_WIDTHBITS : number of bits for the width of second MWD
+--    MWD2_SCALEBITS : number of bits for tau factor for second MWD, also scaling for calculations
+--    MWD_DOUBLEFILTER : two MWD filters in series for single pulses
+--    MWD_PU_DOUBLEFILTER : two MWD filters in series for pileup
+--    BASELINE_BWBITS : number of bits for the baseline IIR filter bandwidth
+--    WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+--    ADCCLOCKFREQUENCY : Frequency of the ADCclock in Hz
+--    CF_DELAYBITS : number of bits for the constant fraction delay
+--    IDIVMAXBITS : number of bits for maximum to integral ratio check
+--    INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+--    MAXPILEUPHITS : maximum number of hits in one pileup waveform
+--    SECOND_FE_MODULE : Second Feature Extraction module for detecting errors due to radiation
 -- 
 -- Inputs:
---     clock : clock for everything
---     reset : reset all
---     enable_data :  enable data, controlled by SODA
---     ADCdata : parallel sampling adc data 
---     rxNotInTable : error in received fiber data, used for status
---     superburst_start : Signal to indicate start of new superburst, received (back) from pin
---     superburst_received : superburstnumber
---     startupready : startup procedure is finished: ready to send data
---     request_init : send a request to the DC to initialize all registers
---     packet_in_data : 32 bits data input from fiber module
---     packet_in_present : data available from fiber module
---     packet_out_fifofull : connected fifo for packet data is full
---     errorbyte_in : errors occurred for slow control reply
---     smaart_in : serial input from external TMP104 sensor
---     sysmon_data : data from the FPGA system monitor module
+--    clock : clock for everything
+--    reset : reset all
+--    enable_data :  enable data, controlled by SODA
+--    GEO : FPGA identification: 0:this is FPGA1, 1:this is FPGA2
+--    ADCdata : parallel sampling adc data 
+--    superburst_start : Signal to indicate start of new superburst, received (back) from pin
+--    superburst_received : superburstnumber
+--    force_hit : force hit at input
+--    onesecondpulse : pulse per second for frequency measurement
+--    rxNotInTable : error in received fiber data, used for status
+--    startupready : startup procedure is finished: ready to send data
+--    request_init : send a request to the DC to initialize all registers
+--    packet_in_data : 32 bits data input from fiber module
+--    packet_in_present : data available from fiber module
+--    packet_out_fifofull : connected fifo for packet data is full
+--    errorbyte_in : errors occurred for slow control reply
+--    smaart_in : serial input from external TMP104 sensor
+--    sysmon_data : data from the FPGA system monitor module
+--    second_module_zero : signal to prevent second module optimized from the design
 -- 
 -- Outputs:
---     packet_in_read : read signal to fiber module to read next data
---     packet_out_data : packet data to fiber module
---     packet_out_first : first 32-bit data word of a packet
---     packet_out_last : last 32-bit data word of a packet
---     packet_out_write : write signal for packet data
---     errorbyte_out : errors occurred: adjust with other FE instances for comparison
---     smaart_out : serial output to external TMP104 sensor
---     sysmon_reset : reset signal to the FPGA system monitor module
---     sysmon_address : selection address for the FPGA system monitor module
---     sysmon_read  : read signal to the FPGA system monitor module
+--    packet_in_read : read signal to fiber module to read next data
+--    packet_out_data : packet data to fiber module
+--    packet_out_first : first 32-bit data word of a packet
+--    packet_out_last : last 32-bit data word of a packet
+--    packet_out_write : write signal for packet data
+--    packet_out_inpipe : more data to come soon
+--    errorbyte_out : errors occurred: adjust with other FE instances for comparison
+--    smaart_out : serial output to external TMP104 sensor
+--    sysmon_reset : reset signal to the FPGA system monitor module
+--    sysmon_address : selection address for the FPGA system monitor module
+--    sysmon_read  : read signal to the FPGA system monitor module
+--    enable_waveform : produce waveforms and not Feature Extraction data
+--    compare_error  : error comparing the output of two modules
 --
 -- Components:
---     FEE_board_slowcontrol : slowcontrol unit to translate fiber packets to slowcontrol commands
---     FEE_slowcontrol_packet_receiver : Read and interprets data (=slowcontrol commands) from fiber from Multiplexer board
---     FEE_pulse_and_pileup_waveforms : measure waveforms for pulses and pileup and multiplex to one stream
---     FEE_combine_data : combine slow-control, pileup waveforms and feature extraction data to one stream to GTP/GTX
---     FEE_measure_frequency : measure frequency of hits
---     TMP104module : module to access external temperature sensor TMP104
+--    FEE_board_slowcontrol : slowcontrol unit to translate fiber packets to slowcontrol commands
+--    FEE_slowcontrol_packet_receiver : Read and interprets data (=slowcontrol commands) from fiber from Multiplexer board
+--    FEE_pulse_and_pileup_waveforms : measure waveforms for pulses and pileup and multiplex to one stream
+--    FEE_combine_data : combine slow-control, pileup waveforms and feature extraction data to one stream to GTP/GTX
+--    FEE_measure_frequency : measure frequency of hits
+--    TMP104module : module to access external temperature sensor TMP104
 -- 
 ----------------------------------------------------------------------------------
 
@@ -120,21 +161,30 @@ entity FEE_adc32_module is
 	generic (
 		NROFADCS                : natural := 32;
 		ADCBITS                 : natural := 14;
+		MWD_WIDTHBITS           : natural := 5;
+		MWD_SCALEBITS           : natural := 16;
+		MWD2_WIDTHBITS          : natural := 2;
+		MWD2_SCALEBITS          : natural := 16;
+		MWD_DOUBLEFILTER        : boolean := false;
+		MWD_PU_DOUBLEFILTER     : boolean := false;
 		BASELINE_BWBITS         : natural := 10;
 		WAVEFORMBUFFERSIZE      : natural := 10;
 		ADCCLOCKFREQUENCY       : natural := 80000000;
 		CF_DELAYBITS            : natural := 4;
-		CF_FRACTIONBIT          : natural := 11;
 		IDIVMAXBITS             : natural := 6;
-		INTEGRALRATIOBITS       : natural := 3
+		INTEGRALRATIOBITS       : natural := 3;
+		MAXPILEUPHITS           : natural := 3;
+		SECOND_FE_MODULE        : boolean := false
 	);
 	port ( 
 		clock                   : in std_logic;
 		reset                   : in std_logic;
 		enable_data             : in std_logic;
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
 		ADCdata                 : in array_adc_type;
 		superburst_start        : in std_logic;
-		superburst_received     : in std_logic_vector(30 downto 0);
+		superburst_received     : in std_logic_vector(30 downto 0);
+		force_hit               : in std_logic;
 		onesecondpulse          : in std_logic;
 		rxNotInTable            : in std_logic;
 		startupready            : in std_logic;
@@ -146,6 +196,7 @@ entity FEE_adc32_module is
 		packet_out_first        : out std_logic;
 		packet_out_last         : out std_logic;
 		packet_out_write        : out std_logic;
+		packet_out_inpipe       : out std_logic;
 		packet_out_fifofull     : in std_logic;
 		errorbyte_out           : out std_logic_vector(7 downto 0);
 		errorbyte_in            : in std_logic_vector(7 downto 0);
@@ -154,11 +205,10 @@ entity FEE_adc32_module is
 		sysmon_data             : in std_logic_vector(15 downto 0);
 		sysmon_reset            : out std_logic;
 		sysmon_address          : out std_logic_vector(6 downto 0);
-		sysmon_read             : out std_logic;
-		testindex               : in integer range 0 to NROFADCS/2-1;
-		testword0               : out std_logic_vector(35 downto 0);
-		testword1               : out std_logic_vector(35 downto 0);
-		testword2               : out std_logic_vector(35 downto 0)
+		sysmon_read             : out std_logic;
+		second_module_zero      : in std_logic;
+		enable_waveform         : out std_logic;
+		compare_error           : out std_logic
 		);
 end FEE_adc32_module;
 
@@ -170,6 +220,7 @@ component FEE_board_slowcontrol is
 		clock                   : in std_logic;
 		reset                   : in std_logic;
 		enable                  : in std_logic;
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
 		overflow_in             : in std_logic;
 		request_init            : in std_logic;
 		byte_data               : in std_logic_vector(7 downto 0);
@@ -211,36 +262,49 @@ component FEE_pulse_and_pileup_waveforms is
 	generic (
 		NROFADCS                : natural := NROFADCS;
 		ADCBITS                 : natural := ADCBITS;
-		BWBITS                  : natural := BASELINE_BWBITS;
+		MWD_WIDTHBITS           : natural := MWD_WIDTHBITS;
+		MWD_SCALEBITS           : natural := MWD_SCALEBITS;
+		MWD2_WIDTHBITS          : natural := MWD2_WIDTHBITS;
+		MWD2_SCALEBITS          : natural := MWD2_SCALEBITS;
+		BASELINE_BWBITS         : natural := BASELINE_BWBITS;
+		MWD_DOUBLEFILTER        : boolean := MWD_DOUBLEFILTER;
+		MWD_PU_DOUBLEFILTER     : boolean := MWD_PU_DOUBLEFILTER;
 		WAVEFORMBUFFERSIZE      : natural := WAVEFORMBUFFERSIZE;
 		IDIVMAXBITS             : natural := IDIVMAXBITS;
 		INTEGRALRATIOBITS       : natural := INTEGRALRATIOBITS;
-		CF_DELAYBITS            : natural := CF_DELAYBITS
+		CF_DELAYBITS            : natural := CF_DELAYBITS;
+		MAXPILEUPHITS           : natural := MAXPILEUPHITS;
+		NOWAVEFORMS             : boolean := false
 		);
     Port (
 		clock                   : in std_logic;
 		reset                   : in std_logic;
-		superburstnumber        : in std_logic_vector(30 downto 0); 
-		timestampcounter        : in std_logic_vector(15 downto 0); 
+		superburstnumber        : in std_logic_vector(30 downto 0); 
+		superburstupdate        : in std_logic; 
 		ADCdata                 : in array_adc_type;
 		enable_data             : in std_logic;
+		enable_waveform         : in std_logic;
+		force_hit               : in std_logic;
 		slowcontrol_byte_data   : in std_logic_vector (7 downto 0);
 		slowcontrol_byte_write  : in std_logic;
 		slowcontrol_byte_request: in std_logic;
-		pulsedata_out           : out std_logic_vector(35 downto 0);
+		pulsedata_channel       : out std_logic_vector(7 downto 0);
+		pulsedata_status        : out std_logic_vector(7 downto 0);
+		pulsedata_superburst    : out std_logic_vector(30 downto 0);
+		pulsedata_timestamp     : out std_logic_vector(15 downto 0);
+		pulsedata_energy        : out std_logic_vector(15 downto 0);
+		pulsedata_CFvalbefore   : out std_logic_vector(15 downto 0);		
+		pulsedata_CFvalafter    : out std_logic_vector(15 downto 0);
 		pulsedata_read          : in std_logic;
 		pulsedata_available     : out std_logic;
 		pulsedata_inpipe        : out std_logic;
-		pileupdata_out          : out std_logic_vector(35 downto 0);
-		pileupdata_read         : in std_logic;
-		pileupdata_available    : out std_logic;
-		pileupdata_inpipe       : out std_logic;
+		wavedata_out            : out std_logic_vector(35 downto 0);
+		wavedata_read           : in std_logic;
+		wavedata_available      : out std_logic;
+		wavedata_inpipe         : out std_logic;
 		pulsedetect             : out std_logic_vector(0 to NROFADCS-1);
-		overflow                : out std_logic;
-		testindex               : in integer range 0 to NROFADCS/2-1;
-		testword0               : out std_logic_vector(35 downto 0);
-		testword1               : out std_logic_vector(35 downto 0);
-		testword2               : out std_logic_vector(35 downto 0)
+		overflow                : out std_logic;
+		error                   : out std_logic
 		);
 end component;
 
@@ -248,8 +312,16 @@ component FEE_combine_data is
     port ( 
 		clock                   : in std_logic;
 		reset                   : in std_logic;
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+		enable_waveform         : in std_logic;
 		-- signals to/from data fifo :
-		pulse_data              : in  std_logic_vector(35 downto 0);
+		pulse_channel           : in  std_logic_vector(7 downto 0);
+		pulse_status            : in  std_logic_vector(7 downto 0);
+		pulse_superburst        : in  std_logic_vector(30 downto 0);
+		pulse_timestamp         : in  std_logic_vector(15 downto 0);
+		pulse_energy            : in  std_logic_vector(15 downto 0);
+		pulse_CFvalbefore       : in  std_logic_vector(15 downto 0);
+		pulse_CFvalafter        : in  std_logic_vector(15 downto 0);
 		pulse_notpresent        : in  std_logic; -- empty signal from fifo
 		pulse_inpipe            : in  std_logic;
 		pulse_read              : out std_logic; -- read from FWFT fifo
@@ -269,9 +341,9 @@ component FEE_combine_data is
 		packet_firstword        : out std_logic;
 		packet_lastword         : out std_logic;
 		packet_datawrite        : out std_logic;
+		packet_inpipe           : out std_logic;
 		packet_fifofull         : in std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
+		error                   : out std_logic
 		);
 end component;
 
@@ -308,31 +380,34 @@ constant init_freqnr : integer := init_frequency_in_kHz * 83322;
 signal error_occurred_S                 : std_logic_vector (7 downto 0) := (others => '0');
 signal enable_data_S                    : std_logic := '0';
 signal startupready_S                   : std_logic := '0';
-
-signal rxAsyncDataRead_S                : std_logic := '0';
-signal rxAsyncData_S                    : std_logic_vector (31 downto 0) := (others => '0');
-
+signal ADCdata_S                        : array_adc_type;
 signal packet_in_read_S                 : std_logic;
-
-signal superburstnumber_s               : std_logic_vector(30 downto 0);
-
-signal SODA_cmd_word_S                  : std_logic_vector(30 downto 0) := (others => '0');
-signal SODA_cmd_valid_S                 : std_logic := '0';
+signal reset1_S                         : std_logic;
+signal soft_reset_S                     : std_logic;
 
-signal slowcontrol_error1_S             : std_logic := '0';
+signal slowcontrol_error1_S             : std_logic;
+signal invertADCs_S                     : std_logic;
+signal clear_errors_S                   : std_logic;
 
-signal clear_errors_S                   : std_logic := '0';
-
-signal pulsedata_out_S                  : std_logic_vector(35 downto 0);
+signal pulsedata_channel_S              : std_logic_vector(7 downto 0);
+signal pulsedata_status_S               : std_logic_vector(7 downto 0);
+signal pulsedata_superburst_S           : std_logic_vector(30 downto 0);
+signal pulsedata_timestamp_S            : std_logic_vector(15 downto 0);
+signal pulsedata_energy_S               : std_logic_vector(15 downto 0);
+signal pulsedata_CFvalbefore_S          : std_logic_vector(15 downto 0);
+signal pulsedata_CFvalafter_S           : std_logic_vector(15 downto 0);
 signal pulsedata_read_S                 : std_logic;
 signal pulsedata_available_S            : std_logic;
 signal pulsedata_inpipe_S               : std_logic;
-signal pileupdata_out_S                 : std_logic_vector(35 downto 0);
-signal pileupdata_read_S                : std_logic;
-signal pileupdata_available_S           : std_logic;
+signal wavedata_out_S                   : std_logic_vector(35 downto 0);
+signal wavedata_read_S                  : std_logic;
+signal wavedata_available_S             : std_logic;
 signal pulse_notpresent_S               : std_logic;
-signal pileupdata_inpipe_s              : std_logic;
+signal wavedata_inpipe_S                : std_logic;
+signal wave_inpipe_S                    : std_logic;
 signal overflow_S                       : std_logic;
+signal dataerror_S                      : std_logic;
+signal request_init_S                   : std_logic;
 
 signal slowcontrol_data_S               : std_logic_vector(31 downto 0);
 signal slowcontrol_address_S            : std_logic_vector(7 downto 0);
@@ -355,13 +430,10 @@ signal board_control_B_S                : std_logic_vector(31 downto 0);
 signal board_control_C_S                : std_logic_vector(31 downto 0);
 signal board_control_D_S                : std_logic_vector(31 downto 0);
 
-
-signal timestampcounter_s               : std_logic_vector(15 downto 0) := (others => '0');
-signal start_of_superburst_S            : std_logic := '0';
-
 signal MUX_error_S                      : std_logic := '0';
 
 signal enable_waveform_S                : std_logic := '0';
+signal enable_waveform_aftr1clk_S       : std_logic;
 signal wave_notpresent_S                : std_logic := '0';
 signal wave_read_S                      : std_logic := '0';
 
@@ -372,28 +444,48 @@ signal pulsefrequency_S                 : std_logic_vector (31 downto 0);
 signal sysmon_address_S                 : std_logic_vector(6 downto 0);
 signal sysmon_address_saved_S           : std_logic_vector(6 downto 0);
 signal temperature_S                    : std_logic_vector (7 downto 0) := (others => '0');
-signal testword0_S                      : std_logic_vector(35 downto 0);
-signal testword1_S                      : std_logic_vector(35 downto 0);
 
-constant DEBUG : std_logic := '0';
-begin
-
-	 
-timestampcounter: process(clock)
+
+signal adcdata2_S                       : array_adc_type;
+signal pulsedata2_channel_S             : std_logic_vector(7 downto 0);
+signal pulsedata2_status_S              : std_logic_vector(7 downto 0);
+signal pulsedata2_superburst_S          : std_logic_vector(30 downto 0);
+signal pulsedata2_timestamp_S           : std_logic_vector(15 downto 0);
+signal pulsedata2_energy_S              : std_logic_vector(15 downto 0);
+signal pulsedata2_CFvalbefore_S         : std_logic_vector(15 downto 0);
+signal pulsedata2_CFvalafter_S          : std_logic_vector(15 downto 0);
+signal pulsedata2_available_S           : std_logic;
+signal pulsedata2_inpipe_S              : std_logic;
+signal pulsedetect2_S                   : std_logic_vector(0 to NROFADCS-1);
+signal overflow2_S                      : std_logic;
+signal dataerror2_S                     : std_logic;
+signal reset2a_S                        : std_logic;
+signal reset2_S                         : std_logic;
+signal request_init2_S                  : std_logic := '0';
+signal unequal_counter_S                : std_logic_vector(23 downto 0) := (others => '0');
+signal unequal_time_S                   : std_logic_vector(23 downto 0) := (others => '0');
+signal unequal_S                        : std_logic := '0';
+signal reboot_S                         : std_logic := '0';
+signal superburst2_start_S              : std_logic;
+signal slowcontrol2_byte_write_S        : std_logic;
+	
+attribute mark_debug : string;
+attribute mark_debug of pulsedata2_available_S : signal is "true";
+attribute mark_debug of pulsedata2_inpipe_S : signal is "true";
+attribute mark_debug of overflow2_S : signal is "true";
+attribute mark_debug of dataerror2_S : signal is "true";
+attribute mark_debug of reset2a_S : signal is "true";
+attribute mark_debug of reset2_S : signal is "true";
+attribute mark_debug of request_init2_S : signal is "true";
+attribute mark_debug of unequal_counter_S : signal is "true";
+attribute mark_debug of unequal_time_S : signal is "true";
+attribute mark_debug of unequal_S : signal is "true";
+attribute mark_debug of reboot_S : signal is "true";
+
 begin
-	if (rising_edge(clock)) then 
-		if superburst_start='1' then
-			timestampcounter_S <= (others => '0');
-			superburstnumber_S <= superburst_received;
-		else
-			timestampcounter_S <= timestampcounter_S+1;
-		end if;
-	end if;
-end process;
-	 
-	 
-gendebug2: if DEBUG='0' generate
 
+compare_error <= reboot_S;
+enable_waveform <= enable_waveform_S;
 
 FEE_slowcontrol_packet_receiver1:  FEE_slowcontrol_packet_receiver port map(
 		clock => clock,
@@ -409,12 +501,14 @@ FEE_slowcontrol_packet_receiver1:  FEE_slowcontrol_packet_receiver port map(
 		overflow => receive_overflow_S);
 packet_in_read <= packet_in_read_S;
 
+request_init_S <= '1' when (request_init='1') or (request_init2_S='1') else '0';
 FEE_board_slowcontrol1: FEE_board_slowcontrol port map(
 		clock => clock,
 		reset => reset,
 		enable => startupready,
+		GEO => GEO,
 		overflow_in => receive_overflow_S,
-		request_init => request_init,
+		request_init => request_init_S,
 		byte_data => slowcontrol_byte_data_S,
 		byte_write => slowcontrol_byte_write_S,
 		byte_request => slowcontrol_byte_request_S,
@@ -451,15 +545,12 @@ begin
 			if (slowcontrol_overflow_S='1') then
 				error_occurred_S(2) <= '1';
 			end if;
---			if cf_error_S='1' then
---				error_occurred_S(3) <= '1';
---			end if;
 			if MUX_error_S='1' then
 				error_occurred_S(4) <= '1';
 			end if;
---			if (rxAsyncDataOverflow_S='1') then
---				error_occurred_S(5) <= '1';
---			end if;
+			if (dataerror_S='1') then
+				error_occurred_S(5) <= '1';
+			end if;
 			if overflow_S='1' then
 				error_occurred_S(6) <= '1';
 			end if;
@@ -469,8 +560,13 @@ begin
 end process;
 
 
-
-
+soft_reset_S <= board_control_A_S(0);
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		invertADCs_S <= board_control_A_S(1);
+	end if;
+end process;
 clear_errors_S <= board_control_A_S(2);
 enable_waveform_S <= board_control_A_S(3);
 pulsedetectmux_S <= pulsedetect_S(conv_integer(unsigned(board_control_A_S(20 downto 16))));
@@ -506,39 +602,178 @@ errorbyte_out <= error_occurred_S;
 
 board_status_D_S(31 downto 0) <= pulsefrequency_S;
 
+gen_invert: for i in 0 to NROFADCS-1 generate
+	ADCdata_S(i) <= not ADCdata(i) when invertADCs_S='1' else ADCdata(i);
+end generate;	
 
-FEE_pulse_and_pileup_waveforms1: FEE_pulse_and_pileup_waveforms port map(
+FEE_pulse_and_pileup_waveforms1: FEE_pulse_and_pileup_waveforms 
+	generic map(
+		NROFADCS => NROFADCS,
+		ADCBITS => ADCBITS,
+		MWD_WIDTHBITS => MWD_WIDTHBITS,
+		MWD_SCALEBITS => MWD_SCALEBITS,
+		MWD2_WIDTHBITS => MWD2_WIDTHBITS,
+		MWD2_SCALEBITS => MWD2_SCALEBITS,
+		BASELINE_BWBITS => BASELINE_BWBITS,
+		MWD_DOUBLEFILTER => MWD_DOUBLEFILTER,
+		MWD_PU_DOUBLEFILTER => MWD_PU_DOUBLEFILTER,
+		WAVEFORMBUFFERSIZE => WAVEFORMBUFFERSIZE,
+		IDIVMAXBITS => IDIVMAXBITS,
+		INTEGRALRATIOBITS => INTEGRALRATIOBITS,
+		CF_DELAYBITS => CF_DELAYBITS,
+		MAXPILEUPHITS => MAXPILEUPHITS,
+		NOWAVEFORMS => false
+		)
+	port map(
 		clock => clock,
-		reset => reset,
-		superburstnumber => superburstnumber_S,
-		timestampcounter => timestampcounter_S,
-		ADCdata => ADCdata,
+		reset => reset1_S,
+		superburstnumber => superburst_received,
+		superburstupdate => superburst_start,
+		ADCdata => ADCdata_S,
 		enable_data => enable_data,
+		enable_waveform => enable_waveform_S,
+		force_hit => force_hit,
 		slowcontrol_byte_data => slowcontrol_byte_data_S,
 		slowcontrol_byte_write => slowcontrol_byte_write_S,
 		slowcontrol_byte_request => slowcontrol_byte_request_S,
-		pulsedata_out => pulsedata_out_S,
+		pulsedata_channel => pulsedata_channel_S,
+		pulsedata_status => pulsedata_status_S,
+		pulsedata_superburst => pulsedata_superburst_S,
+		pulsedata_timestamp => pulsedata_timestamp_S,
+		pulsedata_energy => pulsedata_energy_S,
+		pulsedata_CFvalbefore => pulsedata_CFvalbefore_S,	
+		pulsedata_CFvalafter => pulsedata_CFvalafter_S,
 		pulsedata_read => pulsedata_read_S,
 		pulsedata_available => pulsedata_available_S,
 		pulsedata_inpipe => pulsedata_inpipe_S,
-		pileupdata_out => pileupdata_out_S,
-		pileupdata_read => pileupdata_read_S,
-		pileupdata_available => pileupdata_available_S,
-		pileupdata_inpipe => pileupdata_inpipe_S,
+		wavedata_out => wavedata_out_S,
+		wavedata_read => wavedata_read_S,
+		wavedata_available => wavedata_available_S,
+		wavedata_inpipe => wavedata_inpipe_S,
 		pulsedetect => pulsedetect_S,
 		overflow => overflow_S,
-		testindex => testindex,
-		testword0 => testword0,
-		testword1 => testword1,
-		testword2 => testword2
+		error => dataerror_S
 		);
-		
+reset1_S <= '1' when (reset='1') or (reset2a_S='1') or (soft_reset_S='1') else '0';
+
+gen_second_FE_module: if SECOND_FE_MODULE=TRUE generate
+
+FEE_pulse_and_pileup_waveforms2: FEE_pulse_and_pileup_waveforms 
+	generic map(
+		NROFADCS => NROFADCS,
+		ADCBITS => ADCBITS,
+		MWD_WIDTHBITS => MWD_WIDTHBITS,
+		MWD_SCALEBITS => MWD_SCALEBITS,
+		MWD2_WIDTHBITS => MWD2_WIDTHBITS,
+		MWD2_SCALEBITS => MWD2_SCALEBITS,
+		BASELINE_BWBITS => BASELINE_BWBITS,
+		MWD_DOUBLEFILTER => MWD_DOUBLEFILTER,
+		MWD_PU_DOUBLEFILTER => MWD_PU_DOUBLEFILTER,
+		WAVEFORMBUFFERSIZE => WAVEFORMBUFFERSIZE,
+		IDIVMAXBITS => IDIVMAXBITS,
+		INTEGRALRATIOBITS => INTEGRALRATIOBITS,
+		CF_DELAYBITS => CF_DELAYBITS,
+		MAXPILEUPHITS => MAXPILEUPHITS,
+		NOWAVEFORMS => true
+		)
+	port map(
+		clock => clock,
+		reset => reset2_S,
+		superburstnumber => superburst_received,
+		superburstupdate => superburst2_start_S,
+		ADCdata => adcdata2_S,
+		enable_data => enable_data,
+		enable_waveform => '0',
+		force_hit => force_hit,
+		slowcontrol_byte_data => slowcontrol_byte_data_S,
+		slowcontrol_byte_write => slowcontrol_byte_write_S,
+		slowcontrol_byte_request => slowcontrol_byte_request_S,
+		pulsedata_channel => pulsedata2_channel_S,
+		pulsedata_status => pulsedata2_status_S,
+		pulsedata_superburst => pulsedata2_superburst_S,
+		pulsedata_timestamp => pulsedata2_timestamp_S,
+		pulsedata_energy => pulsedata2_energy_S,
+		pulsedata_CFvalbefore => pulsedata2_CFvalbefore_S,	
+		pulsedata_CFvalafter => pulsedata2_CFvalafter_S,
+		pulsedata_read => pulsedata_read_S,
+		pulsedata_available => pulsedata2_available_S,
+		pulsedata_inpipe => pulsedata2_inpipe_S,
+		wavedata_out => open,
+		wavedata_read => wavedata_read_S,
+		wavedata_available => open,
+		wavedata_inpipe => open,
+		pulsedetect => pulsedetect2_S,
+		overflow => overflow2_S,
+		error => dataerror2_S
+		);
+	superburst2_start_S <= superburst_start when second_module_zero='0' else '0';
+	slowcontrol2_byte_write_S <= slowcontrol_byte_write_S when second_module_zero='0' else '0';
+	adcdata2_S <= adcdata_S when second_module_zero='0' else (others => (others => '0'));
+	
+	reset2_S <= '1' when (reset='1') or (reset2a_S='1') or (soft_reset_S='1') else '0';
+
+	process(clock) 
+	variable request_init_done_V   : std_logic := '1';
+	begin
+		if (rising_edge(clock)) then 
+			unequal_S <= '0';
+			reboot_S <= '0';
+			reset2a_S <= '0';
+			request_init2_S <= '0';
+			if (second_module_zero='1') or (reset='1') or (enable_waveform_aftr1clk_S/=enable_waveform_S) then
+				unequal_counter_S <= (others => '0');
+				reset2a_S <= '1';
+				unequal_time_S <= (others => '0');
+				request_init_done_V := '0';
+			else
+				if (unequal_counter_S(8)='1') and (request_init_done_V='0') then
+					request_init2_S <= '1';
+					request_init_done_V := '1';
+				end if;
+				if (enable_waveform_S='0')  then
+					if ((pulsedata2_channel_S/=pulsedata_channel_S) or 
+						(pulsedata2_status_S/=pulsedata_status_S) or 
+						(pulsedata2_superburst_S/=pulsedata_superburst_S) or 
+						(pulsedata2_timestamp_S/=pulsedata_timestamp_S) or 
+						(pulsedata2_energy_S/=pulsedata_energy_S) or 					
+						(pulsedata2_CFvalbefore_S/=pulsedata_CFvalbefore_S) or
+						(pulsedata2_CFvalafter_S/=pulsedata_CFvalafter_S) or
+						(pulsedata2_available_S/=pulsedata_available_S) or
+						(pulsedata2_inpipe_S/=pulsedata_inpipe_S) or
+						(pulsedetect2_S/=pulsedetect_S) or
+						(overflow2_S/=overflow_S) or
+						(dataerror2_S/=dataerror_S)) then
+						unequal_time_S <= unequal_counter_S;
+						unequal_S <= '1';
+						if (unequal_counter_S(unequal_counter_S'left)='1') then
+							reboot_S <= '1';
+						end if;
+					end if;
+				end if;
+				if unequal_counter_S(unequal_counter_S'left)='0' then
+					unequal_counter_S <= unequal_counter_S+1;
+				end if;
+			end if;
+			enable_waveform_aftr1clk_S <= enable_waveform_S;
+		end if;
+	end process;
+	
+end generate;
+	
 pulse_notpresent_S <= not pulsedata_available_S;
 FEE_combine_data1: FEE_combine_data port map(
 		clock => clock,
 		reset => reset,
+		GEO => GEO,
+		enable_waveform => enable_waveform_S,
 		-- signals to/from data fifo :
-		pulse_data => pulsedata_out_S,
+		pulse_channel => pulsedata_channel_S,
+		pulse_status => pulsedata_status_S,
+		pulse_superburst => pulsedata_superburst_S,
+		pulse_timestamp => pulsedata_timestamp_S,
+		pulse_energy => pulsedata_energy_S,
+		pulse_CFvalbefore => pulsedata_CFvalbefore_S,	
+		pulse_CFvalafter => pulsedata_CFvalafter_S,
 		pulse_notpresent => pulse_notpresent_S,
 		pulse_inpipe => pulsedata_inpipe_S,
 		pulse_read => pulsedata_read_S,
@@ -549,62 +784,35 @@ FEE_combine_data1: FEE_combine_data port map(
 		slowcontrol_notpresent => slowcontrol_notpresent_S,
 		slowcontrol_read => slowcontrol_read_S,
 		-- signals to/from waveform fifo
-		wave_data => pileupdata_out_S,
+		wave_data => wavedata_out_S,
 		wave_notpresent => wave_notpresent_S,
-		wave_inpipe => pileupdata_inpipe_S,
+		wave_inpipe => wave_inpipe_S,
 		wave_read => wave_read_S,
 		-- signals to/from fiber module
 		packet_data_out => packet_out_data,
 		packet_firstword => packet_out_first,
 		packet_lastword => packet_out_last,
 		packet_datawrite => packet_out_write,
+		packet_inpipe => packet_out_inpipe,
 		packet_fifofull => packet_out_fifofull,
-		error => MUX_error_S,
-		testword0 => open);
+		error => MUX_error_S);
 
-wave_notpresent_S <= '1' when (pileupdata_available_S='0') or (enable_waveform_S='0') else '0';
-pileupdata_read_S <= '1' when (enable_waveform_S='0') and (pileupdata_available_S='1') else wave_read_S;
+wave_notpresent_S <= '1' when (wavedata_available_S='0') or (enable_waveform_S='0') else '0';
+wavedata_read_S <= '1' when (enable_waveform_S='0') and (wavedata_available_S='1') else wave_read_S;
+wave_inpipe_S <= '1' when (wavedata_inpipe_S='1') and (enable_waveform_S='1') else '0';
 
---gtpClk_I : IBUFDS port map(
---		O => gtpClk_S,
---		I => gtpClkP0,
---		IB => gtpClkN0);
-		
---GTX_refclock: IBUFDS_GTXE1 port map(
---		O => gtpClk_S,
---		ODIV2 => open,
---		CEB => '0',
---		I => MGTREFCLK_P,
---		IB => MGTREFCLK_N);
-end generate; --debug
-	 
-gendebug3: if DEBUG='0' generate
 FEE_measure_frequency1: FEE_measure_frequency port map(
 		clock => clock,
 		pulse => pulsedetectmux_S,
 		onesecondpulse => onesecondpulse,
 		frequency => pulsefrequency_S);
-end generate; -- debug
 		
---TMP104module1: TMP104module port map(
---		clock => clock,
---		reset => reset,
---		smaart_in => smaart_in,
---		smaart_out => smaart_out,
---		temperature => temperature_S);
---testword0(34 downto 0) <= testword0_S(34 downto 0);
---testword0(35) <= enable_waveform_S;
-
---testword1(15 downto 0) <= packet_in_data(31 downto 16);		 
---testword1(16) <= packet_in_present;		 
---testword1(17) <= packet_in_read_S;		 
---testword1(18) <= slowcontrol_byte_write_S;		 
---testword1(19) <= slowcontrol_byte_request_S;		 
---testword1(27 downto 20) <= slowcontrol_byte_data_S;		 
---testword1(28) <= slowcontrol_error1_S;	
---testword1(29) <= receive_overflow_S;	
---testword1(34 downto 30) <= testword1_S(4 downto 0);		 
---testword1(35) <= '1' when testword1_S(23 downto 0)=x"000000" else '0';
-
+TMP104module1: TMP104module port map(
+		clock => clock,
+		reset => reset,
+		smaart_in => smaart_in,
+		smaart_out => smaart_out,
+		temperature => temperature_S
+		);
 		
 end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_baselinefollower_eventdetector.vhd b/FEE_ADC32board/FEE_modules/FEE_baselinefollower_eventdetector.vhd
index e350749..6de3ddb 100644
--- a/FEE_ADC32board/FEE_modules/FEE_baselinefollower_eventdetector.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_baselinefollower_eventdetector.vhd
@@ -1,11 +1,14 @@
 ----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
+-- Company:       KVI-cart/RUG/Groningen University
 -- Engineer:      Peter Schakel
 -- Create Date:   27-01-2012
 -- Module Name:   FEE_baselinefollower_eventdetector
 -- Description:   Baseline reconstruction, pulse detection
 -- Modifications:
 --   16-09-2014   name changed from baselinefollower_eventdetector to FEE_baselinefollower_eventdetector
+--   24-04-2015   Moving Window Deconvolution added
+--   03-03-2016   Output delayed with 1 clock
+--   23-02-2017   Added one additional Moving Window Deconvolution with short width
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -18,30 +21,38 @@ use IEEE.std_logic_UNSIGNED.ALL;
 --      Baseline reconstruction, pulse detection
 --
 -- generics
---      ADCBITS : number of ADC bits
---      BWBITS : number of bits for the IIR filter bandwidth
+--		ADCBITS : number of ADC bits
+--		BASELINE_BWBITS : number of bits for the IIR filter bandwidth
+--		MWD_WIDTHBITS : number of bits for the width
+--		MWD_SCALEBITS : number of bits for tau factor, also scaling for calculations
+--      MWD2_WIDTHBITS : number of bits for the width of second MWD
+--      MWD2_SCALEBITS : number of bits for tau factor for second MWD, also scaling for calculations
+--      MWD_DOUBLEFILTER : two MWD filters in series
 --
 -- inputs
---      clock : ADC sampling clock 
---      reset : synchrounous reset
---      enable : enable detection of pulses
+--		clock : ADC sampling clock 
+--		reset : synchrounous reset
+--		enable : enable detection of pulses
 --		ADCdata : ADC sampling data
---      threshold : threshold above baseline for start of pulse
---      IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BWBITS)/samplefrequency)
---      maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline 
+--      MWD1_width : width of the first MWD filter
+--      MWD1_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for first single pulse MWD
+--      MWD2_width : width of the second MWD filter
+--      MWD2_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for second single pulse MWD
+--		threshold : threshold above baseline for start of pulse
+--		IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BASELINE_BWBITS)/samplefrequency)
+--		maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline 
 --
 -- outputs
---      baseline : resulting corrected baseline
---      ADC_delayed : ADC data delayed with 1 clock
---      ADC_minus_baseline : ADC values delayed minus baseline
---      baseline_inhibit : signal to indicate a pulse is valid and baseline filtering/stdev is inhibit
---      pulse_active : the ADC-signal exceeds the trigger-level
---      pulse_rising : the pulse has not yet reached its maximum
---      max_data : maximum value of waveform
+--		ADC_minus_baseline : ADC values delayed minus baseline
+--		baseline_inhibit : signal to indicate a pulse is valid and baseline filtering/stdev is inhibit
+--		pulse_active : the ADC-signal exceeds the trigger-level
+--		pulse_rising : the pulse has not yet reached its maximum
+--		max_data : maximum value of waveform
 --
--- components
---      IIRfilter_1order : IIR filter for the baseline
---      FEE_eventdetector : detection of pulse
+-- components
+--		FEE_MWDfilter_unsigned : Moving Window deconvolution
+--		iirfilter_1order_selectBW : IIR filter for the baseline
+--		FEE_eventdetector : detection of pulse
 --
 ----------------------------------------------------------------------------------
 
@@ -50,40 +61,63 @@ use IEEE.std_logic_UNSIGNED.ALL;
 entity FEE_baselinefollower_eventdetector is
 	generic (
 		ADCBITS                 : natural := 16;
-		BWBITS                  : natural := 10
+		BASELINE_BWBITS         : natural := 10;
+		MWD_WIDTHBITS           : natural := 8;
+		MWD_SCALEBITS           : natural := 16;
+		MWD2_WIDTHBITS          : natural := 2;
+		MWD2_SCALEBITS          : natural := 16;
+		MWD_DOUBLEFILTER        : boolean := false
 		);
 	port (
-		clock                   : in  std_logic;
-		reset                   : in  std_logic;
-		enable                  : in  std_logic;
-		ADCdata                 : in std_logic_vector((ADCBITS-1) downto 0);
-		threshold               : in std_logic_vector((ADCBITS-1) downto 0);
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		enable                  : in std_logic;
+		ADCdata                 : in std_logic_vector(ADCBITS-1 downto 0);
+		MWD1_width              : in std_logic_vector((MWD_WIDTHBITS-1) downto 0);
+		MWD1_tau_factor         : in std_logic_vector((MWD_SCALEBITS-1) downto 0);
+		MWD2_width              : in std_logic_vector(MWD2_WIDTHBITS-1 downto 0);
+		MWD2_tau_factor         : in std_logic_vector((MWD2_SCALEBITS-1) downto 0);
+		threshold               : in std_logic_vector(ADCBITS-1 downto 0);
 		IIRfilterBW             : in std_logic_vector(2 downto 0);
 		maxabovebaseline        : in std_logic_vector(3 downto 0);
-		baseline                : out std_logic_vector((ADCBITS-1) downto 0);
-		ADC_delayed             : out std_logic_vector(ADCBITS-1 downto 0);
 		ADC_minus_baseline      : out std_logic_vector(ADCBITS downto 0);
 		baseline_inhibit        : out std_logic;
 		pulse_active            : out std_logic;
 		pulse_rising            : out std_logic;
-		max_data                : out std_logic_vector(ADCBITS-1 downto 0)
+		max_data                : out std_logic_vector(ADCBITS-1 downto 0)
 	);
 end FEE_baselinefollower_eventdetector;
 
 architecture Behavioral of FEE_baselinefollower_eventdetector is
 
+component FEE_MWDfilter_unsigned is
+	generic (
+		MWD_DATABITS            : natural := ADCBITS;
+		MWD_WIDTHBITS           : natural := MWD_WIDTHBITS;
+		MWD_SCALEBITS           : natural := MWD_SCALEBITS
+		);
+    Port (
+		clock                   : in std_logic;
+		reset                   : in  std_logic;
+		data_in                 : in  std_logic_vector((MWD_DATABITS-1) downto 0);
+		MWD_width               : in  std_logic_vector((MWD_WIDTHBITS-1) downto 0);
+		MWD_tau_factor          : in  std_logic_vector((MWD_SCALEBITS-1) downto 0);
+		data_out_signed         : out  std_logic_vector(MWD_DATABITS downto 0);
+		data_out_unsigned       : out  std_logic_vector(MWD_DATABITS downto 0));
+end component; 
+
 component iirfilter_1order_selectBW is
 	generic (
-		ADCBITS : natural := ADCBITS;
-		BWBITS : natural := BWBITS
+		ADCBITS                 : natural := ADCBITS+MWD_WIDTHBITS+4;
+		BWBITS                  : natural := BASELINE_BWBITS
 		);
 	port ( 
-		clock : in  std_logic;
-		reset : in  std_logic;
-		data_in : in  std_logic_vector ((ADCBITS-1) downto 0);
-		BWidx : in  std_logic_vector (2 downto 0);
-		inhibit : in  std_logic;
-		data_out : out  std_logic_vector ((ADCBITS-1) downto 0));
+		clock                   : in  std_logic;
+		reset                   : in  std_logic;
+		data_in                 : in  std_logic_vector (ADCBITS-1 downto 0);
+		BWidx                   : in  std_logic_vector (2 downto 0);
+		inhibit                 : in  std_logic;
+		data_out                : out std_logic_vector (ADCBITS-1 downto 0));
 end component;
 
 component FEE_eventdetector is
@@ -102,29 +136,84 @@ component FEE_eventdetector is
 		max_data                : out std_logic_vector(ADCBITS-1 downto 0)
 		);
 end component;
+
+constant ZEROS                : std_logic_vector(63 downto 0) := (others => '0');
+
+signal MWD1data_unsigned_S    : std_logic_vector(ADCBITS downto 0);
+signal MWDdata_unsigned_S     : std_logic_vector(ADCBITS+1 downto 0);
 
-signal ADC_delayed_S          : std_logic_vector((ADCBITS-1) downto 0) := (others => '0');
-signal baseline_S             : std_logic_vector((ADCBITS-1) downto 0) := (others => '0');
-signal ADC_minusbaseline_S    : std_logic_vector(ADCBITS downto 0) := (others => '0');
+signal ADC_delayed_S          : std_logic_vector(ADCBITS+1 downto 0);
+signal baseline_S             : std_logic_vector(ADCBITS+1 downto 0);
+signal ADC_minusbaselinei_S   : integer range -2**(ADCBITS+2) to 2**(ADCBITS+2)-1;
+signal ADC_minusbaseline_S    : std_logic_vector(ADCBITS downto 0);
 signal baseline_inhibit_S     : std_logic := '0';
-signal pulse_active_S         : std_logic := '0';
+signal pulse_active_S         : std_logic := '0';
+signal pulse_rising_S         : std_logic := '0';
 signal enable_S               : std_logic := '0';
-
 
+attribute mark_debug : string;
+-- attribute mark_debug of ADC_delayed_S : signal is "true";
+-- attribute mark_debug of MWD1data_unsigned_S : signal is "true";
+-- attribute mark_debug of MWDdata_unsigned_S : signal is "true";
+-- attribute mark_debug of baseline_S : signal is "true";
+-- attribute mark_debug of ADC_minusbaselinei_S : signal is "true";
+-- attribute mark_debug of ADC_minusbaseline_S : signal is "true";
+-- attribute mark_debug of baseline_inhibit_S : signal is "true";
+attribute mark_debug of pulse_active_S : signal is "true";
 
 begin
-	
 
+FEE_MWDfilter_unsigned1: FEE_MWDfilter_unsigned 
+	generic map(
+		MWD_DATABITS => ADCBITS,
+		MWD_WIDTHBITS => MWD_WIDTHBITS,
+		MWD_SCALEBITS => MWD_SCALEBITS)
+	port map(
+		clock => clock,
+		reset => reset,
+		data_in => ADCdata,
+		MWD_width => MWD1_width,
+		MWD_tau_factor => MWD1_tau_factor,
+		data_out_unsigned => MWD1data_unsigned_S,
+		data_out_signed => open);
 
-baselinefilter: iirfilter_1order_selectBW port map(
-	clock => clock,
-	reset => reset,
-	data_in => ADC_delayed_S,
-	BWidx => IIRfilterBW(2 downto 0),
-	inhibit => baseline_inhibit_S,
-	data_out => baseline_S);
+gen_second_MWD: if MWD_DOUBLEFILTER=true generate
+	FEE_MWDfilter_unsigned2: FEE_MWDfilter_unsigned 
+		generic map(
+			MWD_DATABITS => ADCBITS+1,
+			MWD_WIDTHBITS => MWD2_WIDTHBITS,
+			MWD_SCALEBITS => MWD2_SCALEBITS)
+		port map(
+			clock => clock,
+			reset => reset,
+			data_in => MWD1data_unsigned_S,
+			MWD_width => MWD2_width,
+			MWD_tau_factor => MWD2_tau_factor,
+			data_out_unsigned => MWDdata_unsigned_S,
+			data_out_signed => open);
+end generate;
 
-ADC_minusbaseline_S <= conv_std_logic_vector(conv_integer(signed('0' & ADCdata)) - conv_integer(signed('0' & baseline_S)),(ADCBITS+1));
+gen_no_second_MWD: if MWD_DOUBLEFILTER=false generate
+	MWDdata_unsigned_S <= '0' & MWD1data_unsigned_S;
+end generate;
+	
+baselinefilter: iirfilter_1order_selectBW 
+	generic map(
+		ADCBITS => ADCBITS+2,
+		BWBITS => BASELINE_BWBITS)
+	port map(
+		clock => clock,
+		reset => reset,
+		data_in => ADC_delayed_S,
+		BWidx => IIRfilterBW(2 downto 0),
+		inhibit => baseline_inhibit_S,
+		data_out => baseline_S);
+
+ADC_minusbaselinei_S <= conv_integer(signed('0' & MWDdata_unsigned_S)) - conv_integer(signed('0' & baseline_S));
+ADC_minusbaseline_S <=
+	(0 => '0', others => '1') when ADC_minusbaselinei_S>2**ADCBITS-1 else -- clip positive
+	(0 => '1', others => '0') when ADC_minusbaselinei_S<-2**ADCBITS else -- clip negative
+	conv_std_logic_vector(ADC_minusbaselinei_S,ADCBITS+1); -- in range
 
 FEE_eventdetector1: FEE_eventdetector port map(
 	clock => clock,
@@ -134,25 +223,34 @@ FEE_eventdetector1: FEE_eventdetector port map(
 	maxabovebaseline => maxabovebaseline,
 	baseline_freeze => baseline_inhibit_S,
 	pulse_active => pulse_active_S,
-	pulse_rising => pulse_rising,
+	pulse_rising => pulse_rising_S,
 	max_data => max_data);
-pulse_active <= pulse_active_S when enable_S='1' else '0';
 
 
 process(clock)
 begin
 	if rising_edge(clock) then
-		ADC_delayed_S <= ADCdata;
+		ADC_delayed_S <= MWDdata_unsigned_S;
 		if pulse_active_S='0' then
 			enable_S <= enable;
 		end if;
 	end if;
 end process;
 
-baseline <= baseline_S;
-baseline_inhibit <= baseline_inhibit_S;
-ADC_delayed <= ADC_delayed_S;
-ADC_minus_baseline <= ADC_minusbaseline_S;
+process(clock)
+begin
+	if rising_edge(clock) then
+		pulse_rising <= pulse_rising_S;
+		if enable_S='1' then
+			pulse_active <= pulse_active_S;
+		else 
+			pulse_active <= '0';
+		end if;
+		baseline_inhibit <= baseline_inhibit_S;
+		ADC_minus_baseline <= ADC_minusbaseline_S;
+	end if;
+end process;
+
 
 end Behavioral;
 
diff --git a/FEE_ADC32board/FEE_modules/FEE_board_slowcontrol.vhd b/FEE_ADC32board/FEE_modules/FEE_board_slowcontrol.vhd
index 2059f59..0db2ffc 100644
--- a/FEE_ADC32board/FEE_modules/FEE_board_slowcontrol.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_board_slowcontrol.vhd
@@ -70,6 +70,7 @@ entity FEE_board_slowcontrol is
 		clock                   : in std_logic;
 		reset                   : in std_logic;
 		enable                  : in std_logic;
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
 		overflow_in             : in std_logic;
 		request_init            : in std_logic;
 		byte_data               : in std_logic_vector(7 downto 0);
@@ -96,8 +97,8 @@ architecture Behavioral of FEE_board_slowcontrol is
 
 component sync_fifo_512x41
 	port (
-		rst                     : in std_logic;
-		clk                  : in std_logic;
+		srst                    : in std_logic;
+		clk                     : in std_logic;
 		din                     : in std_logic_vector(40 downto 0);
 		wr_en                   : in std_logic;
 		rd_en                   : in std_logic;
@@ -115,7 +116,7 @@ signal slowcontrol_reply_S          : std_logic := '0';
 signal slowcontrol_write_S          : std_logic;
 signal slowcontrol_fifofull_S       : std_logic;
 
-signal board_control_A_S            : std_logic_vector (31 downto 0) := x"00000000";
+signal board_control_A_S            : std_logic_vector (31 downto 0) := x"00000008";
 signal board_control_B_S            : std_logic_vector (31 downto 0) := x"00000000";
 signal board_control_C_S            : std_logic_vector (31 downto 0) := x"00000000";
 signal board_control_D_S            : std_logic_vector (31 downto 0) := x"00000000";
@@ -172,15 +173,18 @@ begin
 			end if;
 			if byte_idx_S=0 then
 				if (byte_write='1') then
-					if (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then
+					if (NROFFEEFPGAS=1) and (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then
 						selected_S <= '1';
 						selected_reg_S <= byte_data(1 downto 0);
+					elsif (NROFFEEFPGAS=2) and (byte_data(7 downto 3)=ADDRESS_FEE_CONTROL(7 downto 3)) and (byte_data(0)=GEO) then
+						selected_S <= '1';
+						selected_reg_S <= byte_data(2 downto 1);
 					else
 						selected_S <= '0';
 					end if;
 					byte_idx_S <= 1;
 				elsif byte_request='1' then
-					if (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then
+					if (NROFFEEFPGAS=1) and (byte_data(7 downto 2)=ADDRESS_FEE_CONTROL(7 downto 2)) then
 						case byte_data(1 downto 0) is
 							when "00" => slowcontrol_data_S <= board_status_A;
 							when "01" => slowcontrol_data_S <= board_status_B;
@@ -194,6 +198,20 @@ begin
 						if slowcontrol_fifofull_S='1' then
 							overflow2_S <= '1';
 						end if;
+					elsif  (NROFFEEFPGAS=2) and (byte_data(7 downto 3)=ADDRESS_FEE_CONTROL(7 downto 3)) and (byte_data(0)=GEO) then
+						case byte_data(2 downto 1) is
+							when "00" => slowcontrol_data_S <= board_status_A;
+							when "01" => slowcontrol_data_S <= board_status_B;
+							when "10" => slowcontrol_data_S <= board_status_C;
+							when "11" => slowcontrol_data_S <= board_status_D;
+							when others => 
+						end case;
+						slowcontrol_address_S <= byte_data;
+						slowcontrol_reply_S <= '1';
+						slowcontrol_write_S <= '1';
+						if slowcontrol_fifofull_S='1' then
+							overflow2_S <= '1';
+						end if;
 					end if;								
 					selected_S <= '0';
 					byte_idx_S <= 0;
@@ -214,7 +232,7 @@ begin
 							overflow2_S <= '0';
 							slowcontrol_data_S <= (others => '0');
 							slowcontrol_address_S <= ADDRESS_FEE_SLOWCONTROLERROR;
-							slowcontrol_reply_S <= '1';  -- ??
+							slowcontrol_reply_S <= '0';  -- ??
 							slowcontrol_write_S <= '1';
 						end if;
 					end if;
@@ -255,7 +273,7 @@ end process;
 
 fifo_in_S <= slowcontrol_reply_S & slowcontrol_address_S & slowcontrol_data_S;
 fifo1: sync_fifo_512x41 port map(
-		rst => reset,
+		srst => reset,
 		clk => clock,
 		din => fifo_in_S,
 		wr_en => slowcontrol_write_S,
diff --git a/FEE_ADC32board/FEE_modules/FEE_collect_pileup_pulses.vhd b/FEE_ADC32board/FEE_modules/FEE_collect_pileup_pulses.vhd
new file mode 100644
index 0000000..109c917
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_collect_pileup_pulses.vhd
@@ -0,0 +1,310 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI-cart/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   04-04-2017
+-- Module Name:   FEE_collect_pileup_pulses
+-- Description:   Collect results of Feature Extraction for pileup pulses
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+USE work.panda_package.all;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_collect_pileup_pulses
+-- Collect results of Feature Extraction for pileup pulses
+-- Hits in pileup waveform are stored in memory and if the waveform is regarded as valid pileup then the hits are written to the output.
+--
+--
+-- generics
+--    MAXPILEUPHITS : maximum number of hits in one pileup waveform
+--		
+-- inputs
+--    clock : clock
+--    reset : synchrounous reset
+--    pulse_active : pulse is active: above thresshold
+--    pileup_valid : pileup waveform is valid
+--    detect_singlepulse : single hit detected
+--    detect_pileuppulse : hit detected in pileup waveform
+--    detect_clearpulse : clear pileup waveform
+--    detect_purge : clear detected hits in pileup waveform
+--    data_in_write : write signal for input data
+--    data_in_superburst : superburstnumber
+--    data_in_timestamp : time within superburst
+--    data_in_energy : energy of the hit
+--    data_in_CF1 : Constant Fraction result: sample before zero-crossing
+--    data_in_CF2 : Constant Fraction result: sample after zero-crossing
+--			  
+-- outputs
+--    data_out_write : write signal for input data
+--    data_out_superburst : superburstnumber
+--    data_out_timestamp : time within superburst
+--    data_out_energy : energy of the hit
+--    data_out_CF1 : Constant Fraction result: sample before zero-crossing
+--    data_out_CF2 : Constant Fraction result: sample after zero-crossing
+--    data_out_skipped : Previous data was skipped
+--
+-- Components:
+--     blockmem : memory for pileup data
+--     blockmem1x96_xilinx, blockmem2x96_xilinx, blockmem3x96_xilinx : Xilinx block memory IP cores
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_collect_pileup_pulses is
+	generic (
+		MAXPILEUPHITS           : natural := 3
+		);
+    Port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		pulse_active            : in std_logic;
+		pileup_valid            : in std_logic;
+		detect_singlepulse      : in std_logic;
+		detect_pileuppulse      : in std_logic;
+		detect_clearpulse       : in std_logic;
+		detect_purge            : in std_logic;
+		data_in_write           : in std_logic;	
+		data_in_superburst      : in std_logic_vector(30 downto 0);
+		data_in_timestamp       : in std_logic_vector(15 downto 0);
+		data_in_energy          : in std_logic_vector(15 downto 0);
+		data_in_CF1             : in std_logic_vector(15 downto 0);
+		data_in_CF2             : in std_logic_vector(15 downto 0);
+		data_out_write          : out std_logic;
+		data_out_superburst     : out std_logic_vector(30 downto 0);
+		data_out_timestamp      : out std_logic_vector(15 downto 0);
+		data_out_energy         : out std_logic_vector(15 downto 0);
+		data_out_CF1            : out std_logic_vector(15 downto 0);
+		data_out_CF2            : out std_logic_vector(15 downto 0);
+		data_out_skipped        : out std_logic
+		);
+end FEE_collect_pileup_pulses;
+
+architecture Behavioral of FEE_collect_pileup_pulses is
+
+component blockmem is
+	generic (
+		ADDRESS_BITS : natural := twologarray(MAXPILEUPHITS);
+		DATA_BITS  : natural := 96
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+COMPONENT blockmem1x96_xilinx
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
+  );
+END COMPONENT;
+
+COMPONENT blockmem2x96_xilinx
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
+  );
+END COMPONENT;
+
+COMPONENT blockmem3x96_xilinx
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0)
+  );
+END COMPONENT;
+
+constant ZEROS                               : std_logic_vector(63 downto 0) := (others => '0');
+constant ONES                                : std_logic_vector(63 downto 0) := (others => '1');
+type pileupbuffer_superburst_type is array(0 to MAXPILEUPHITS-1) of std_logic_vector(30 downto 0);
+type pileupbuffer_16bits_type is array(0 to MAXPILEUPHITS-1) of std_logic_vector(15 downto 0);
+
+
+signal mem_writeaddress_S                    : std_logic_vector(twologarray(MAXPILEUPHITS)-1 downto 0);
+signal mem_readaddress_S                     : std_logic_vector(twologarray(MAXPILEUPHITS)-1 downto 0);
+
+signal data_out_write_S                      : std_logic := '0';
+signal hitcount_S                            : integer range 0 to MAXPILEUPHITS;
+signal resultcount_S                         : integer range 0 to MAXPILEUPHITS;
+signal readcount_S                           : integer range 0 to MAXPILEUPHITS;
+signal pileupbuffer_skipped_S                : std_logic;
+		
+attribute mark_debug : string;
+-- attribute mark_debug of clipping_S : signal is "true";
+
+begin
+
+data_out_write <= data_out_write_S;
+mem_writeaddress_S <= conv_std_logic_vector(hitcount_S,twologarray(MAXPILEUPHITS));
+mem_readaddress_S <= conv_std_logic_vector(readcount_S,twologarray(MAXPILEUPHITS));
+
+gen_otherbitsmemblock: if twologarray(MAXPILEUPHITS)>3 generate
+	blockmem1: blockmem port map(
+		clock => clock,
+		write_enable => data_in_write,
+		write_address => mem_writeaddress_S,
+		data_in(15 downto 0) => data_in_CF2,
+		data_in(31 downto 16) => data_in_CF1,
+		data_in(47 downto 32) => data_in_energy,
+		data_in(63 downto 48) => data_in_timestamp,
+		data_in(94 downto 64) => data_in_superburst,
+		data_in(95) => pileupbuffer_skipped_S,
+		read_address => mem_readaddress_S,
+		data_out(15 downto 0) => data_out_CF2,
+		data_out(31 downto 16) => data_out_CF1,
+		data_out(47 downto 32) => data_out_energy,
+		data_out(63 downto 48) => data_out_timestamp,
+		data_out(94 downto 64) => data_out_superburst,
+		data_out(95) => data_out_skipped
+		);
+end generate;
+
+gen_1bitsmemblock: if twologarray(MAXPILEUPHITS)=1 generate
+blockmem1x96_xilinx1: blockmem1x96_xilinx port map(
+    clka => clock,
+    wea(0) => data_in_write,
+    addra => mem_writeaddress_S,
+	dina(15 downto 0) => data_in_CF2,
+	dina(31 downto 16) => data_in_CF1,
+	dina(47 downto 32) => data_in_energy,
+	dina(63 downto 48) => data_in_timestamp,
+	dina(94 downto 64) => data_in_superburst,
+	dina(95) => pileupbuffer_skipped_S,
+    clkb => clock,
+    addrb => mem_readaddress_S,
+	doutb(15 downto 0) => data_out_CF2,
+	doutb(31 downto 16) => data_out_CF1,
+	doutb(47 downto 32) => data_out_energy,
+	doutb(63 downto 48) => data_out_timestamp,
+	doutb(94 downto 64) => data_out_superburst,
+	doutb(95) => data_out_skipped);
+end generate;
+gen_2bitsmemblock: if twologarray(MAXPILEUPHITS)=2 generate
+blockmem2x96_xilinx1: blockmem2x96_xilinx port map(
+    clka => clock,
+    wea(0) => data_in_write,
+    addra => mem_writeaddress_S,
+	dina(15 downto 0) => data_in_CF2,
+	dina(31 downto 16) => data_in_CF1,
+	dina(47 downto 32) => data_in_energy,
+	dina(63 downto 48) => data_in_timestamp,
+	dina(94 downto 64) => data_in_superburst,
+	dina(95) => pileupbuffer_skipped_S,
+    clkb => clock,
+    addrb => mem_readaddress_S,
+	doutb(15 downto 0) => data_out_CF2,
+	doutb(31 downto 16) => data_out_CF1,
+	doutb(47 downto 32) => data_out_energy,
+	doutb(63 downto 48) => data_out_timestamp,
+	doutb(94 downto 64) => data_out_superburst,
+	doutb(95) => data_out_skipped);
+end generate;
+gen_3bitsmemblock: if twologarray(MAXPILEUPHITS)=3 generate
+blockmem1x96_xilinx1: blockmem3x96_xilinx port map(
+    clka => clock,
+    wea(0) => data_in_write,
+    addra => mem_writeaddress_S,
+	dina(15 downto 0) => data_in_CF2,
+	dina(31 downto 16) => data_in_CF1,
+	dina(47 downto 32) => data_in_energy,
+	dina(63 downto 48) => data_in_timestamp,
+	dina(94 downto 64) => data_in_superburst,
+	dina(95) => pileupbuffer_skipped_S,
+    clkb => clock,
+    addrb => mem_readaddress_S,
+	doutb(15 downto 0) => data_out_CF2,
+	doutb(31 downto 16) => data_out_CF1,
+	doutb(47 downto 32) => data_out_energy,
+	doutb(63 downto 48) => data_out_timestamp,
+	doutb(94 downto 64) => data_out_superburst,
+	doutb(95) => data_out_skipped);
+end generate;
+
+process(clock)
+variable detect_pileupvalidpulse_V : std_logic;
+variable pileuppulse_detected_V    : std_logic := '0';
+begin
+	if rising_edge(clock) then
+		data_out_write_S <= '0';
+		detect_pileupvalidpulse_V := '0';
+		if detect_pileuppulse='1' then
+			if pulse_active='1' then
+				pileuppulse_detected_V := '1';
+			else
+				pileuppulse_detected_V := '0';
+				detect_pileupvalidpulse_V := '1';
+			end if;
+		elsif pileuppulse_detected_V='1' then
+			if pulse_active='0' then
+				pileuppulse_detected_V := '0';
+				detect_pileupvalidpulse_V := '1';
+			end if;
+		end if;
+		if (data_in_write='1') then
+			if hitcount_S<MAXPILEUPHITS then
+				hitcount_S <= hitcount_S+1;
+			else
+				pileupbuffer_skipped_S <= '1';
+			end if;
+		end if;
+		if detect_pileupvalidpulse_V='1' then
+			if (hitcount_S=0) and (data_in_write='0') then
+				pileupbuffer_skipped_S <= '1';
+			elsif (hitcount_S=0) and (data_in_write='1') then
+				resultcount_S <= 1;
+				readcount_S <= 0;
+			else
+				pileupbuffer_skipped_S <= '0';
+				if (data_in_write='1') and (hitcount_S<MAXPILEUPHITS) then
+					resultcount_S <= hitcount_S+1;
+				else
+					resultcount_S <= hitcount_S;
+				end if;
+				hitcount_S <= 0;
+				readcount_S <= 0;
+			end if;
+		else
+			if readcount_S<resultcount_S then
+				data_out_write_S <= '1';
+				readcount_S <= readcount_S+1;
+			end if;
+		end if;
+		if (reset='1') or (detect_singlepulse='1') or (detect_clearpulse='1') or (detect_purge='1') then
+			hitcount_S <= 0;
+			readcount_S <= 0;
+			resultcount_S <= 0;
+		end if;
+		if (pileup_valid='0') and (pulse_active='0') and (data_in_write='0') then
+			hitcount_S <= 0;
+		end if;
+	end if;
+end process;	
+	
+	
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_combine_data.vhd b/FEE_ADC32board/FEE_modules/FEE_combine_data.vhd
index d186789..606b52e 100644
--- a/FEE_ADC32board/FEE_modules/FEE_combine_data.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_combine_data.vhd
@@ -1,5 +1,5 @@
 ----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
+-- Company:       KVI-cart/RUG/Groningen University
 -- Engineer:      Peter Schakel
 -- Create Date:   28-02-2012
 -- Module Name:   FEE_combine_data
@@ -8,6 +8,7 @@
 --   09-09-2014   New data formats without hamming code
 --   10-10-2014   Integral as measurement for the energy instead of maximum
 --   16-10-2014   Inpipe signals, better sorting between waveforms and single pulse packets
+--   23-02-2017   Parallel data from Feature Extraction instead of 36-bits
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -21,13 +22,11 @@ USE work.panda_package.all;
 -- Module in the Front End Electronics that builds packets from Pulse data, waveforms and 
 -- Slow-control data to send to the fiber module.
 --
--- The pulse data consists of three successive 36-bits words with bits 35..34 the index:
---        	bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
---        	bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
---        	bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+-- The pulse data from the feature extraction contains values that determine time and energy.
+-- The parameters are received in parallel.
 --
 -- The Slow-control commands consists of address and data plus a bit to indicate reply.
--- If an error occurs then a slowcontrol packet with address ADDRESS_FEE_SLOWCONTROLERROR is sent
+-- If an error occurs then a slowcontrol packet with address ADDRESS_FEE_SLOWCONTROLERROR is sent.
 --
 -- The waveform data consists of 36-bits data with variable length :
 --        	bits(35..32)="0000" : bits(31..16)=superburstnumber, bits(31..0)=timestamp inside superburst
@@ -42,9 +41,9 @@ USE work.panda_package.all;
 --
 -- The resulting data packets : 4 32-bit words, with CRC8 in last word
 --   0xDA ADCnumber(7..0) superburstnumber(15..0)
---   0000 energy(15..0) 
+--   timestamp(15..0) energy(15..0) 
 --   CF_before(15..0) CF_after(15..0)
---   timestamp(15..0) statusbyte(7..0) CRC8(7..0)
+--   0000 statusbyte(7..0) CRC8(7..0)
 --
 -- The slow control packets : 2 32-bit words, with CRC8 in last word
 --   0x5C address(7..0) replybit 0000000 data(31..24)
@@ -68,11 +67,19 @@ USE work.panda_package.all;
 -- Inputs:
 --     clock : clock input
 --     reset : synchronous reset
---     pulse_data : data with results from Feature Extraction
+--     GEO : FPGA identification: 0:this is FPGA1, 1:this is FPGA2
+--     pulse_channel : results from Feature Extraction: ADC channel number
+--     pulse_status : results from Feature Extraction: status byte
+--     pulse_superburst : results from Feature Extraction: superburst number
+--     pulse_timestamp : results from Feature Extraction: timestamp within superburst
+--     pulse_energy : results from Feature Extraction: energy
+--     pulse_CFvalbefore : results from Feature Extraction: ADC sample before zero-crossing Constant Fraction method
+--     pulse_CFvalafter : results from Feature Extraction: ADC sample after zero-crossing Constant Fraction method
 --     pulse_notpresent : pulse data not available (empty signal from connected fifo)
 --     pulse_inpipe : more single pulse data on its way
---     slowcontrol_data : slow-control command : 
---          first address-word with bit31=reply, bit30..28=101 and bit23..0=address then data-word
+--     slowcontrol_data : data slow-control command
+--     slowcontrol_address : address slow-control command
+--     slowcontrol_reply : slow-control command contains a reply on a request
 --     slowcontrol_notpresent : slow-control not available (empty signal from fifo)
 --     wave_data : data with pileup waveforms from pileup multiplexer
 --     wave_notpresent : pileup waveform not available (empty signal from fifo)
@@ -87,11 +94,11 @@ USE work.panda_package.all;
 --     packet_firstword : first 32-bit data word of a packet
 --     packet_lastword : last 32-bit data word of a packet
 --     packet_datawrite : write signal for packet data
+--     packet_inpipe : more data to come soon
 --     error : error on incomming data (no sequential index)
 -- 
 -- Components:
---     crc8_add_check32 : add and checks a CRC8 code to a stream of 32 bits data words
---                        the check is not used in this module
+--     crc8_add_check32 : add and checks a CRC8 code to a stream of 32 bits data words (check is not used)
 --
 ----------------------------------------------------------------------------------
 
@@ -99,8 +106,16 @@ entity FEE_combine_data is
     port ( 
 		clock                   : in std_logic;
 		reset                   : in std_logic;
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+		enable_waveform         : in std_logic;
 		-- signals to/from data fifo :
-		pulse_data              : in  std_logic_vector(35 downto 0);
+		pulse_channel           : in  std_logic_vector(7 downto 0);
+		pulse_status            : in  std_logic_vector(7 downto 0);
+		pulse_superburst        : in  std_logic_vector(30 downto 0);
+		pulse_timestamp         : in  std_logic_vector(15 downto 0);
+		pulse_energy            : in  std_logic_vector(15 downto 0);
+		pulse_CFvalbefore       : in  std_logic_vector(15 downto 0);
+		pulse_CFvalafter        : in  std_logic_vector(15 downto 0);
 		pulse_notpresent        : in  std_logic; -- empty signal from fifo
 		pulse_inpipe            : in  std_logic;
 		pulse_read              : out std_logic; -- read from FWFT fifo
@@ -120,9 +135,10 @@ entity FEE_combine_data is
 		packet_firstword        : out std_logic;
 		packet_lastword         : out std_logic;
 		packet_datawrite        : out std_logic;
+		packet_inpipe           : out std_logic;
 		packet_fifofull         : in std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0));
+		error                   : out std_logic
+		);
 end FEE_combine_data;
 
 architecture Behavioral of FEE_combine_data is
@@ -169,27 +185,61 @@ signal packet_datawrite_S           : std_logic;
 signal packet_lastword_S            : std_logic;
 signal packet_firstword_S           : std_logic := '1';
 
-
---signal delay_inpipe_pulse_S         : std_logic := '0';
---signal delay_inpipe_wave_S          : std_logic := '0';
-
 signal wave_read0_S                 : std_logic := '0';
 signal wave_read_S                  : std_logic := '0';
 signal superburst_S                 : std_logic_vector (15 downto 0);
 signal timestamp_S                  : std_logic_vector (15 downto 0);
 signal statusbyte_S                 : std_logic_vector (7 downto 0);
---signal channel_S                    : std_logic_vector (7 downto 0);
+signal channel_S                    : std_logic_vector (7 downto 0);
 signal energy_S                     : std_logic_vector (15 downto 0);
 signal CF_before_S                  : std_logic_vector (15 downto 0);
 signal CF_after_S                   : std_logic_vector (15 downto 0);
 
 
-signal waveisolder_S                : std_logic := '0';
+attribute mark_debug : string;
+-- attribute mark_debug of wave_notpresent : signal is "true";
+-- attribute mark_debug of wave_inpipe : signal is "true";
+-- attribute mark_debug of wave_read : signal is "true";
+-- attribute mark_debug of tx_state_S : signal is "true";
+-- attribute mark_debug of error_S : signal is "true";
+-- attribute mark_debug of statusbyte_S : signal is "true";
+-- attribute mark_debug of pulse_read_S : signal is "true";
+
+-- attribute mark_debug of pulse_data : signal is "true";
+-- attribute mark_debug of pulse_notpresent : signal is "true";
+-- attribute mark_debug of pulse_inpipe : signal is "true";
+-- attribute mark_debug of pulse_read : signal is "true";
+
+
+-- attribute mark_debug of energy_S : signal is "true";
+-- attribute mark_debug of crc8_data_in_S : signal is "true";
+-- attribute mark_debug of crc8_data_in_valid_S : signal is "true";
+-- attribute mark_debug of crc8_data_in_last_S : signal is "true";
+-- attribute mark_debug of packet_data_out : signal is "true";
+-- attribute mark_debug of crc8_data_out_valid_S : signal is "true";
+-- attribute mark_debug of crc8_data_out_last_S : signal is "true";
+-- attribute mark_debug of packet_firstword : signal is "true";
+-- attribute mark_debug of packet_lastword : signal is "true";
+-- attribute mark_debug of packet_datawrite : signal is "true";
+-- attribute mark_debug of packet_fifofull : signal is "true";
+-- attribute mark_debug of packet_inpipe : signal is "true";
 
+-- attribute mark_debug of crc8_reset_S : signal is "true";
+-- attribute mark_debug of crc8_clear_S : signal is "true";
+-- attribute mark_debug of crc8_writeword_S : signal is "true";
+-- attribute mark_debug of prev_crc8_data_out_valid_S : signal is "true";
+-- attribute mark_debug of prev_crc8_data_out_last_S : signal is "true";
+
+									
 begin
 
 error <= error_S;
-
+packet_inpipe <= '1' when 
+		(((pulse_inpipe='1') and (enable_waveform='0')) or ((wave_inpipe='1') and (enable_waveform='1')) or (tx_state_S/=idle))
+		or (((pulse_notpresent='0') and (enable_waveform='0')) or (slowcontrol_notpresent='0') or ((wave_notpresent='0') and (enable_waveform='1')))
+		or ((crc8_writeword_S='1') or (crc8_data_out_valid_S='1'))
+	else '0';
+		
 crc8_data_in_valid_S <= '1' when (crc8_writeword_S='1') and (packet_fifofull='0') else '0';
 crc8_reset_S <= '1' when (crc8_clear_S='1') or (reset='1') else '0';
 crc8check: crc8_add_check32 port map(
@@ -254,74 +304,30 @@ wave_read <= wave_read_S;
 pulse_read <= pulse_read_S;
 slowcontrol_read <= slowcontrol_read_S;
 
---process(clock)
---variable inpipe_counter_V : integer range 0 to INPIPE_DELAY := 0;
---begin
---	if rising_edge(clock) then
---		if reset='1' then
---			inpipe_counter_V := 0;
---			delay_inpipe_pulse_S <= '0';
---		else
---			if (pulse_read_S='1') or -- and (dfifo_prog_empty_S(index)='1')) or
---				(wave_read_S='1') -- and (dfifo_prog_empty_S(index_other)='1'))
---				then
---				inpipe_counter_V := INPIPE_DELAY;
---				delay_inpipe_pulse_S <= '1';
---			else			
---				if inpipe_counter_V/=0 then
---					inpipe_counter_V := inpipe_counter_V-1;
---					delay_inpipe_pulse_S <= '1';
---				else
---					delay_inpipe_pulse_S <= '0';
---				end if;
---			end if;
---		end if;
---	end if;
---end process;
---
---process(clock)
---variable inpipe_counter_V : integer range 0 to INPIPE_DELAY := 0;
---begin
---	if rising_edge(clock) then
---		if reset='1' then
---			inpipe_counter_V := 0;
---			delay_inpipe_wave_S <= '0';
---		else
---			if (wave_read_S='1') or -- and (dfifo_prog_empty_S(index)='1')) or
---				(pulse_read_S='1') -- and (dfifo_prog_empty_S(index_other)='1'))
---				then
---				inpipe_counter_V := INPIPE_DELAY;
---				delay_inpipe_wave_S <= '1';
---			else			
---				if inpipe_counter_V/=0 then
---					inpipe_counter_V := inpipe_counter_V-1;
---					delay_inpipe_wave_S <= '1';
---				else
---					delay_inpipe_wave_S <= '0';
---				end if;
---			end if;
---		end if;
---	end if;
---end process;
 
-waveisolder_S <= '1' when ((wave_data(31 downto 16)<pulse_data(31 downto 16)) and (not ((wave_data(31 downto 30)="00") and (pulse_data(31 downto 30)="11")))) or
-	((wave_data(31 downto 16)=pulse_data(31 downto 16)) and (wave_data(15 downto 0)<pulse_data(15 downto 0)))
+wave_read_S <= '1' when 
+		((enable_waveform='0') and (wave_notpresent='0'))
+		or ((enable_waveform='1') and (tx_state_S=idle) and (wave_notpresent='0') and (slowcontrol_notpresent='1'))
+		or ((tx_state_S=wave0) and (wave_notpresent='0'))
+		or ((tx_state_S=wave2) and (wave_notpresent='0') and (wave_data(35 downto 32)/="0000"))
 	else '0';
-
-wave_read_S <= '1' when (wave_data(35 downto 32)/="0000") and (tx_state_S=idle) and (wave_notpresent='0') else wave_read0_S;
+	
+-- wave_read_S <= '1' when 
+	-- ((wave_data(35 downto 32)/="0000") and (tx_state_S=idle) and (wave_notpresent='0')) 
+		-- or ((enable_waveform='0') and (wave_notpresent='0')) 
+	-- else wave_read0_S;
 
-wave_read0_S <= '1' when (wave_notpresent='0') and (packet_fifofull='0') and 
-	(((pulse_notpresent='0') or (pulse_inpipe='0')) or (tx_state_S/=idle)) and
-	((tx_state_S=wave0) or (tx_state_S=wave2) or
-	((tx_state_S=idle) and (slowcontrol_notpresent='1') and ((pulse_notpresent='1') or (waveisolder_S='1'))))
-	else '0';
+-- wave_read0_S <= '1' when 
+	-- (wave_notpresent='0') and (packet_fifofull='0') and (enable_waveform='1') and (tx_state_S/=idle) 
+		-- and ((tx_state_S=wave0) or (tx_state_S=wave2) or ((tx_state_S=idle) and (slowcontrol_notpresent='1')))
+	-- else '0';
 	
-pulse_read_S <= '1' when (pulse_data(35 downto 34)/="00") and (tx_state_S=idle) and (pulse_notpresent='0') else pulse_read0_S;
+pulse_read_S <= '1' when ((tx_state_S=idle) and (pulse_notpresent='0')) 
+	or ((enable_waveform='1') and (pulse_notpresent='0')) else pulse_read0_S;
 
-pulse_read0_S <= '1' when (pulse_notpresent='0') and (packet_fifofull='0') and
-	((wave_notpresent='0') or (wave_inpipe='0') or (tx_state_S/=idle)) and
-	((tx_state_S=data0) or (tx_state_S=data1) or
-	((tx_state_S=idle) and (slowcontrol_notpresent='1') and ((wave_notpresent='1') or (waveisolder_S='0'))))
+pulse_read0_S <= '1' when 
+	(pulse_notpresent='0') and (packet_fifofull='0') and (enable_waveform='0')
+		and ((tx_state_S=idle) and (slowcontrol_notpresent='1'))
 	else '0';
 
 slowcontrol_read_S <= '1' when (slowcontrol_notpresent='0') and (packet_fifofull='0') and (tx_state_S=idle) else '0';
@@ -363,26 +369,13 @@ begin
 						else
 							crc8_data_in_last_S <= '0';
 						end if;
-
-						if pulse_read_S='1' then
-							if pulse_data(35 downto 34)="00" then
-								error_S <= '0';
---								channel_S(0) <= pulse_data(33);
-								if pulse_data(32)='1' then 
-									statusbyte_S <= STATBYTE_FEEPULSESKIPPED;
-								else
-									statusbyte_S <= x"00";
-								end if;
-								superburst_S <= pulse_data(31 downto 16);
-								timestamp_S <= pulse_data(15 downto 0);
-								tx_state_S <= data0;
-							else
-								error_S <= '1';
-							end if;							
+						if (enable_waveform='0') and (pulse_read_S='1') then
+							error_S <= '0';
+							tx_state_S <= data0;
 						elsif slowcontrol_read_S='1' then  
 							error_S <= '0';
 							tx_state_S <= slow0;
-						elsif wave_read_S='1' then  
+						elsif (enable_waveform='1') and (wave_read_S='1') then  
 							if wave_data(35 downto 32)="0000" then
 								superburst_S <= wave_data(31 downto 16);
 								timestamp_S <= wave_data(15 downto 0);
@@ -394,68 +387,54 @@ begin
 						else
 						end if;
 					when data0 =>
-						if pulse_read_S='1' then
-							timeoutcounter_V := 0;
-							if pulse_data(35 downto 34)="01" then
---								channel_S(7 downto 0) <= pulse_data(23 downto 16);
-								energy_S <= pulse_data(15 downto 0);
-								crc8_data_in_S <= x"DA" & pulse_data(23 downto 16) & superburst_S;
-								crc8_writeword_S <= '1';
-								crc8_data_in_last_S <= '0';
-								tx_state_S <= data1;
-							else
-								error_S <= '1';
-								tx_state_S <= init;
+						statusbyte_S <= pulse_status;
+						channel_S <= pulse_channel;
+						superburst_S <= pulse_superburst(15 downto 0);
+						timestamp_S <= pulse_timestamp;
+						energy_S <= pulse_energy;
+						CF_before_S <= pulse_CFvalbefore;
+						CF_after_S <= pulse_CFvalafter;
+--						if packet_fifofull='0' then
+							if (NROFFEEFPGAS=1) or (GEO='0') then
+								crc8_data_in_S <= x"DA" & pulse_channel & pulse_superburst(15 downto 0);
+							else -- map ADC channel number to higher level
+								crc8_data_in_S <= x"DA" & pulse_channel+conv_std_logic_vector(NROFFEEADCS,8) & pulse_superburst(15 downto 0);
 							end if;
-						else
-							if timeoutcounter_V/=15 then
-								timeoutcounter_V := timeoutcounter_V+1;
-							else
-								error_S <= '1';
-								tx_state_S <= init;
-							end if;
-						end if;
+							crc8_writeword_S <= '1';
+							crc8_data_in_last_S <= '0';
+							tx_state_S <= data1;
+--						end if;
 					when data1 =>
-						if pulse_read_S='1' then
-							timeoutcounter_V := 0;
-							if pulse_data(35 downto 34)="10" then
-								CF_before_S <= pulse_data(31 downto 16);
-								CF_after_S <= pulse_data(15 downto 0);
-								crc8_data_in_S <= x"0000" & energy_S;
-								crc8_writeword_S <= '1';
-								crc8_data_in_last_S <= '0';
-								tx_state_S <= data2;
-							else
-								error_S <= '1';
-								tx_state_S <= init;
-							end if;
-						else
-							if timeoutcounter_V/=15 then
-								timeoutcounter_V := timeoutcounter_V+1;
-							else
-								error_S <= '1';
-								tx_state_S <= init;
-							end if;
+						if packet_fifofull='0' then
+							crc8_data_in_S <= timestamp_S & energy_S;
+							crc8_writeword_S <= '1';
+							crc8_data_in_last_S <= '0';
+							tx_state_S <= data2;
 						end if;
 					when data2 =>
-						crc8_data_in_S <= CF_before_S & CF_after_S;
-						crc8_writeword_S <= '1';
-						crc8_data_in_last_S <= '0';
-						crc8_lastword_S <= timestamp_S & statusbyte_S & x"00";
-						crc8_lastwrite_S <= '1';
-						tx_state_S <= idle;
-
+						if packet_fifofull='0' then
+							crc8_data_in_S <= CF_before_S & CF_after_S;
+							crc8_writeword_S <= '1';
+							crc8_data_in_last_S <= '0';
+							crc8_lastword_S <= x"0000" & statusbyte_S & x"00";
+							crc8_lastwrite_S <= '1';
+							tx_state_S <= idle;
+						end if;
 					when wave0 =>
 						if wave_read_S='1' then
 							timeoutcounter_V := 0;
 							if wave_data(35 downto 32)="0001" then
 								statusbyte_S <= wave_data(31 downto 24);
---								channel_S <= wave_data(7 downto 0);
 							else
 								error_S <= '1';
 								tx_state_S <= init;
 							end if;
-							crc8_data_in_S <= x"AF" & wave_data(7 downto 0) & superburst_S;
+--								channel_S <= wave_data(7 downto 0);
+							if (NROFFEEFPGAS=1) or (GEO='0') then
+								crc8_data_in_S <= x"AF" & wave_data(7 downto 0) & superburst_S;
+							else -- map ADC channel number to higher level
+								crc8_data_in_S <= x"AF" & wave_data(7 downto 0)+conv_std_logic_vector(NROFFEEADCS,8) & superburst_S;
+							end if;
 							crc8_writeword_S <= '1';
 							crc8_data_in_last_S <= '0';
 							tx_state_S <= wave1;
@@ -522,53 +501,7 @@ begin
 		end if;
 	end if;
 end process datahandling;
-	
-
-
-
-testword0(3 downto 0) <= pulse_data(35 downto 32);
-testword0(4) <= pulse_notpresent;
-testword0(5) <= pulse_inpipe;
-testword0(6) <= pulse_read_S;
-testword0(7) <= pulse_read0_S;
-
-testword0(11 downto 8) <= wave_data(35 downto 32);
-testword0(12) <= wave_notpresent;
-testword0(13) <= wave_inpipe;
-testword0(14) <= wave_read_S;
-testword0(15) <= wave_read0_S;
-
-testword0(19 downto 16) <= 
-	x"0" when tx_state_S=init else
-	x"1" when tx_state_S=idle else
-	x"2" when tx_state_S=data0 else
-	x"3" when tx_state_S=data1 else
-	x"4" when tx_state_S=data2 else
-	x"5" when tx_state_S=wave0 else
-	x"6" when tx_state_S=wave1 else
-	x"7" when tx_state_S=wave2 else
-	x"8" when tx_state_S=slow0 else
-	x"f";
-	
-testword0(20) <= waveisolder_S;
-testword0(21) <= crc8_reset_S;
-testword0(22) <= crc8_clear_S;
-testword0(23) <= crc8_data_in_valid_S;
-testword0(24) <= crc8_data_in_last_S;
-testword0(25) <= crc8_writeword_S;
-testword0(26) <= crc8_data_out_valid_S;
-testword0(27) <= crc8_data_out_last_S;
-testword0(28) <= '0';
-testword0(29) <= crc8_lastwrite_S;
-testword0(30) <= slowcontrol_notpresent;
-testword0(31) <= slowcontrol_read_S;
-testword0(32) <= packet_datawrite_S;
-testword0(33) <= packet_lastword_S;
-testword0(34) <= packet_firstword_S;
-
 	
-testword0(35) <= error_S;
-
 
 end Behavioral;
 
diff --git a/FEE_ADC32board/FEE_modules/FEE_dual_pulse_waveform.vhd b/FEE_ADC32board/FEE_modules/FEE_dual_pulse_waveform.vhd
index eb2e45b..2584723 100644
--- a/FEE_ADC32board/FEE_modules/FEE_dual_pulse_waveform.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_dual_pulse_waveform.vhd
@@ -1,782 +1,1295 @@
-----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
--- Engineer:      Peter Schakel
--- Create Date:   30-01-2012
--- Module Name:   FEE_dual_pulse_waveform
--- Description:   Module to detect pulses and outputs them as waveforms with single pulse or pile-up, dual gain inputs
--- Modifications:
---   08-09-2014   Added: Constant Fraction values before and after zero-crossing
---   16-09-2014   name changed from dual_pulse_waveform to FEE_dual_pulse_waveform
---   22-09-2014   single clock
---   24-09-2014   enable_highgain and enable_lowgain inputs added
---   10-10-2014   Integral as measurement for the energy instead of maximum
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.std_logic_ARITH.ALL;
-use IEEE.std_logic_UNSIGNED.ALL;
-
-
-------------------------------------------------------------------------------------------------------
--- FEE_dual_pulse_waveform
---    Module to detect pulses and outputs them as waveforms with single pulse or pile-up
---    Two ADC inputs, one for the high gain and one for the low gain are corrected for baseline fluctuations.
---    If a pulse or pileup is detected at the low-gain input, the high-gain input is ignored.
---    Pulses are detected: check if the ADC signal is above the adjustable tresshold.
---    The samples are stored in buffer memory as waveform.
---    The actual superburst-number and a timestamp within the superburst is added.
---    Waveforms longer than an adjustable duration are treated as pileup waveforms,
---    waveforms shorter than this, but longer as an adjustable minimum duration are tested for Integral/Maximum ratio:
---    The waveform is discarded if the maximum multiplied with IdivMAX_discard value is larger than the integral.
---    The waveform is regarded as pileup if the maximum multiplied with IdivMAX_pileup value is smaller than the integral.
---    From the single pulse waveforms the Constant Fraction values before and after the zero-crossing are put in the
---    resulting packet, as well as two successive samples containing the maximum of the pulse.
---
---
--- generics
---    ADCBITS : number of ADC-bits
---    BWBITS : number of bits for the IIR filter bandwidth
---    WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
---    IDIVMAXBITS : number of bits for maximum to integral ratio check
---    INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
---    CF_DELAYBITS : number of bits for the Constant Fraction delay
---		
--- inputs
---    clock : clock
---    reset : synchrounous reset
---    enable : enable pulse detection
---    superburstnumber : actual superburstnumber
---    timestampcounter : timestampcounter within superburst
---    ADCdata_highgain : ADC signal from the high-gain input
---    ADCdata_lowgain : ADC signal from the low-gain input
---    threshold_highgain : threshold above baseline for start of pulse (high gain)
---    threshold_lowgain : threshold above baseline for start of pulse (low gain)
---    enable_highgain : enable high gain input
---    enable_lowgain : enable low gain input
---    IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BWBITS)/samplefrequency)
---    maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline 
---    minpulselength : number of samples below which the pulse is ignored
---    pileuplength : number of samples above which the pulse is treated as pileup
---    maxwavelength : maximum number of samples that can be saved in one waveform
---    IdivMAX_discard : when this value multiplied with the maximum is larger than the integral then the waveform is discarded
---    IdivMAX_pileup : when this value multiplied with the maximum is smaller than the integral then the waveform is regarded as pileup
---    fullsize_wave_highgain : take waveforms with maximum size for highgain input
---    fullsize_wave_lowgain : take waveforms with maximum size for lowgain input
---    pulsedata_allowed : writing of pulse 36-bits data result allowed
---    pulsedata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
---    pileupdata_allowed : writing of pileup 36-bits data result allowed
---    pileupdata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
---			  
--- outputs
---    ADC_minus_baseline_highgain : baseline compensated signal from high gain input, signed
---    ADC_minus_baseline_lowgain : baseline compensated signal from low gain input, signed
---    pulsedata_write : write 36-bits pulse data result
---    pulsedata_out : 36-bits pulse data result:
---        	bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
---        	bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
---        	bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
---    pileupdata_write : write 36-bits pileup data result
---    pileupdata_out : 36-bits pileup data result:
---        	bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
---        	bits(35..32)="0001" : 
---              bits(31..24) = statusbyte 
---              bits(23..8) = 0
---              bits(7..0) = adcnumber (channel identification)
---        	bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
---        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
---        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
---    pulsedetect : indicates if a pulse (regular or pileup) is detected on the high or low-gain input
---    overflow : pulse or pileup waveform is lost
---
--- Components:
---     FEE_baselinefollower_eventdetector : baseline follower with detection of pulse
---     FEE_pileup_check : check length of pulse and Maximum/Integral ratio to determine if pileup occurred
---     FEE_extract_pulse : perform maximum check and constant fraction
---     FEE_pulsewaveform_buffer : buffer for waveform data, timestamps arre added
---     FEE_waveform_to_36bits : convert waveform data to 36-bits wide data stream 
---     FEE_wavemux2to1 : select next waveform, based on timestamp
---     FEE_pulse2to1_pulse : combine hits from high and low gain ADC inputs to one data packet stream
---
-------------------------------------------------------------------------------------------------------
-
-
-
-entity FEE_dual_pulse_waveform is
-	generic (
-		ADCBITS                 : natural := 14;
-		BWBITS                  : natural := 10;
-		WAVEFORMBUFFERSIZE      : natural := 11;
-		IDIVMAXBITS             : natural := 6;
-		INTEGRALRATIOBITS       : natural := 3;
-		CF_DELAYBITS            : natural := 8
-		);
-    Port (
-		clock                   : in  std_logic;
-		reset                   : in  std_logic;
-		enable                  : in  std_logic;
-		adcnumber               : in std_logic_vector(7 downto 0); 
-		cf_delay                : in std_logic_vector(CF_DELAYBITS-1 downto 0);
-		superburstnumber        : in std_logic_vector(30 downto 0); 
-		timestampcounter        : in std_logic_vector(15 downto 0); 
-		ADCdata_highgain        : in std_logic_vector((ADCBITS-1) downto 0);
-		ADCdata_lowgain         : in std_logic_vector((ADCBITS-1) downto 0);
-		threshold_highgain      : in std_logic_vector((ADCBITS-1) downto 0);
-		threshold_lowgain       : in std_logic_vector((ADCBITS-1) downto 0);
-		enable_highgain         : in  std_logic;
-		enable_lowgain          : in  std_logic;
-		IIRfilterBW             : in std_logic_vector(2 downto 0);
-		maxabovebaseline        : in std_logic_vector(3 downto 0);
-		minpulselength          : in std_logic_vector(7 downto 0);
-		pileuplength            : in std_logic_vector(7 downto 0);
-		maxwavelength           : in std_logic_vector(7 downto 0);
-		IdivMAX_discard         : in std_logic_vector(IDIVMAXBITS-1 downto 0);
-		IdivMAX_pileup          : in std_logic_vector(IDIVMAXBITS-1 downto 0);
-		fullsize_wave_highgain  : in  std_logic;
-		fullsize_wave_lowgain   : in  std_logic;
-		ADC_minus_baseline_highgain : out std_logic_vector(ADCBITS downto 0);
-		ADC_minus_baseline_lowgain : out std_logic_vector(ADCBITS downto 0);
-		pulsedata_allowed       : in std_logic;
-		pulsedata_almostfull    : in std_logic;
-		pulsedata_write         : out std_logic;
-		pulsedata_out           : out std_logic_vector(35 downto 0);
-		pileupdata_allowed      : in std_logic;
-		pileupdata_almostfull   : in std_logic;
-		pileupdata_write        : out std_logic;
-		pileupdata_out          : out std_logic_vector(35 downto 0);
-		pulsedetect             : out std_logic;
-		overflow                : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0);
-		testword1               : out std_logic_vector(35 downto 0);
-		testword2               : out std_logic_vector(35 downto 0)
-		);
-end FEE_dual_pulse_waveform;
-
-architecture Behavioral of FEE_dual_pulse_waveform is
-
-component FEE_baselinefollower_eventdetector is
-	generic (
-		ADCBITS                 : natural := ADCBITS;
-		BWBITS                  : natural := BWBITS
-		);
-	port (
-		clock                   : in  std_logic;
-		reset                   : in  std_logic;
-		enable                  : in  std_logic;
-		ADCdata                 : in std_logic_vector((ADCBITS-1) downto 0);
-		threshold               : in std_logic_vector((ADCBITS-1) downto 0);
-		IIRfilterBW             : in std_logic_vector(2 downto 0);
-		maxabovebaseline        : in std_logic_vector(3 downto 0);
-		baseline                : out std_logic_vector((ADCBITS-1) downto 0);
-		ADC_delayed             : out std_logic_vector(ADCBITS-1 downto 0);
-		ADC_minus_baseline      : out std_logic_vector(ADCBITS downto 0);
-		baseline_inhibit        : out std_logic;
-		pulse_active            : out std_logic;
-		pulse_rising            : out std_logic;
-		max_data                : out std_logic_vector(ADCBITS-1 downto 0)
-	);
-end component;
-
-component FEE_pileup_check is
-	generic (
-		ADCBITS                 : natural := ADCBITS;
-		IDIVMAXBITS             : natural := IDIVMAXBITS;
-		INTEGRALRATIOBITS       : natural := INTEGRALRATIOBITS
-		);
-   Port (
-		clock                   : in  std_logic;
-		reset                   : in  std_logic;
-		superburstnumber        : in std_logic_vector(30 downto 0); 
-		timestampcounter        : in std_logic_vector(15 downto 0); 
-		ADC_highgain            : in std_logic_vector(ADCBITS downto 0); -- signed
-		enable_highgain         : in  std_logic;
-		max_data_highgain       : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
-		pulse_active_highgain   : in std_logic;
-		pulse_rising_highgain   : in std_logic;
-		clipping_highgain       : in std_logic;
-		ADC_lowgain             : in std_logic_vector(ADCBITS downto 0); -- signed
-		enable_lowgain          : in  std_logic;
-		max_data_lowgain        : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
-		pulse_active_lowgain    : in std_logic;
-		pulse_rising_lowgain    : in std_logic;
-		minpulselength          : in std_logic_vector(7 downto 0);
-		pileuplength            : in std_logic_vector(7 downto 0);
-		maxwavelength           : in std_logic_vector(7 downto 0);
-		IdivMAX_discard         : in std_logic_vector(IDIVMAXBITS-1 downto 0);
-		IdivMAX_pileup          : in std_logic_vector(IDIVMAXBITS-1 downto 0);
-		fullsize_wave_highgain  : in  std_logic;
-		fullsize_wave_lowgain   : in  std_logic;
-		pulse_valid_highgain    : out std_logic;
-		singlepulse_highgain    : out std_logic;
-		pileuppulse_highgain    : out std_logic;
-		clearpulse_highgain     : out std_logic;
+----------------------------------------------------------------------------------
+-- Company:       KVI-cart/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   30-01-2012
+-- Module Name:   FEE_dual_pulse_waveform
+-- Description:   Module to detect pulses and outputs them as waveforms with single pulse or pile-up, dual gain inputs
+-- Modifications:
+--   08-09-2014   Added: Constant Fraction values before and after zero-crossing
+--   16-09-2014   name changed from dual_pulse_waveform to FEE_dual_pulse_waveform
+--   22-09-2014   single clock
+--   24-09-2014   enable_highgain and enable_lowgain inputs added
+--   10-10-2014   Integral as measurement for the energy instead of maximum
+--   24-04-2015   Moving Window Deconvolution added
+--   19-08-2015   Force_hit added: force waveform acquisition with SODA command
+--   23-10-2015   wavedata_inpipe added, earlier reading of data, outputs data when available 
+--   28-10-2016   Enable_waveform input added
+--   23-02-2017   Parallel data from Feature Extraction instead of 36-bits
+--   05-04-2017   Pileup correction, added second MWD, optimized for area, 
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+USE work.panda_package.all;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_dual_pulse_waveform
+--    Module to detect and analyse pulses and outputs them with data that determines time and energy.
+--    There is also a mode in which the pulses are passed on as waveforms.
+--    Two ADC inputs, one for the high gain and one for the low gain are corrected for baseline fluctuations.
+--    If a pulse at the high-gain input is clipping, the result of the low-gain input is taken.
+--    Pulses are detected: check if the ADC signal is above the adjustable tresshold.
+--    The samples are also stored in buffer memory as waveform.
+--    The actual superburst-number and a timestamp within the superburst is added.
+--    Waveforms longer than an adjustable duration are treated as pileup : parallel processed with shorter detection settings (MWD and CF).
+--    Waveforms shorter than this, but longer as an adjustable minimum duration are tested for Integral/Maximum ratio:
+--    The waveform is discarded if the maximum multiplied with IdivMAX_discard value is larger than the integral.
+--    The waveform is regarded as pileup if the maximum multiplied with IdivMAX_pileup value is smaller than the integral.
+--    The integral value determines the energy.
+--    From the single pulse waveforms and the pileup pulses the Constant Fraction values before and after the zero-crossing are put in the
+--    resulting packet.
+--
+--
+-- generics
+--    ADCNUMBER : number of the ADC to put in the resulting data
+--    ADCBITS : number of ADC-bits
+--    BASELINE_BWBITS : number of bits for the IIR filter bandwidth
+--    MWD_WIDTHBITS : number of bits for the width
+--    MWD_SCALEBITS : number of bits for tau factor, also scaling for calculations
+--    MWD2_WIDTHBITS : number of bits for the width of second MWD
+--    MWD2_SCALEBITS : number of bits for tau factor for second MWD, also scaling for calculations
+--    MWD_DOUBLEFILTER : two MWD filters in series for single pulses
+--    MWD_PU_DOUBLEFILTER : two MWD filters in series for pileup
+--    WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+--    IDIVMAXBITS : number of bits for maximum to integral ratio check
+--    INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+--    MAXPILEUPHITS : maximum number of hits in one pileup waveform
+--    CF_DELAYBITS : number of bits for the Constant Fraction delay
+--    NOWAVEFORMS : produce hit results, do not produce waveforms
+--		
+-- inputs
+--    clock : clock
+--    reset : synchrounous reset
+--    enable : enable pulse detection
+--    enable_waveform : outputs waveforms and not feature extraction data
+--    force_hit : force hit at input
+--    CF_delay : delay for the Constant Fraction method for single pulses
+--    CFpu_delay : delay for the Constant Fraction method for pileup pulses
+--    superburstnumber : actual superburstnumber
+--    superburstupdate : new superburstnumber
+--    ADCdata_highgain : ADC signal from the high-gain input
+--    ADCdata_lowgain : ADC signal from the low-gain input
+--    MWD1_width : width of the first MWD filter
+--    MWD1_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for first single pulse MWD
+--    MWD2_width : width of the second MWD filter
+--    MWD2_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for second single pulse MWD
+--    MWDpu1_width : width of the first pileup MWD filter
+--    MWDpu1_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for first pileup MWD
+--    MWDpu2_width : width of the second pileup MWD filter
+--    MWDpu2_tau_factor : factor for exponential compensation : 2^MWD_SCALEBITS/(Tau*samlefreq) for second pileup MWD
+--    threshold_highgain : threshold above baseline for start of pulse (high gain)
+--    threshold_lowgain : threshold above baseline for start of pulse (low gain)
+--    enable_highgain : enable high gain input
+--    enable_lowgain : enable low gain input
+--    enable_rawdata : send raw data in waveform instead of baseline corrected data
+--    IIRfilterBW : factor for first order IIR filter; formula BW[Hz]=2^IIRfilterBW/(PI*(2^BASELINE_BWBITS)/samplefrequency)
+--    maxabovebaseline : 2^maximum number of samples a pulse can last to prevent deadlock threshold/baseline 
+--    minpulselength : number of samples below which the pulse is ignored
+--    pileuplength : number of samples above which the pulse is treated as pileup
+--    maxwavelength : maximum number of samples that can be saved in one waveform
+--    IdivMAX_discard : when this value multiplied with the maximum is larger than the integral then the waveform is discarded
+--    IdivMAX_pileup : when this value multiplied with the maximum is smaller than the integral then the waveform is regarded as pileup
+--    fullsize_wave_highgain : take waveforms with maximum size for highgain input
+--    fullsize_wave_lowgain : take waveforms with maximum size for lowgain input
+--    pulsedata_allowed : writing of pulse 36-bits data result allowed
+--    pulsedata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
+--    wavedata_allowed : writing of pileup 36-bits data result allowed
+--    wavedata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
+--			  
+-- outputs
+--    pulsedata_write : write 36-bits pulse data result
+--    pulsedata_lowgain : high or low gain channel
+--    pulsedata_superburst : superburstnumber
+--    pulsedata_timestamp : time within superburst
+--    pulsedata_energy : energy of the hit
+--    pulsedata_CFvalbefore : Constant Fraction result: sample before zero-crossing
+--    pulsedata_CFvalafter : Constant Fraction result: sample after zero-crossing
+--    pulsedata_status : status byte
+-- 	  wavedata_available : waveform data available
+--    wavedata_write : write 36-bits pileup data result
+--    wavedata_out : 36-bits pileup data result:
+--        	bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+--        	bits(35..32)="0001" : 
+--              bits(31..24) = statusbyte 
+--              bits(23..8) = 0
+--              bits(7..0) = adcnumber (channel identification)
+--        	bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--    pulsedetect : indicates if a pulse (regular or pileup) is detected on the high or low-gain input
+--    overflow : pulse or pileup waveform is lost
+--    error : error occured
+--
+-- Components:
+--     FEE_baselinefollower_eventdetector : baseline follower with detection of pulse
+--     FEE_pileup_check : check length of pulse and Maximum/Integral ratio to determine if pileup occurred
+--     FEE_pulse_detect : detect pulse for pileup data
+--     FEE_extract_pulse : perform maximum check and constant fraction
+--     FEE_collect_pileup_pulses : Collect results of Feature Extraction for pileup pulses
+--     FEE_pulsewaveform_buffer : buffer for waveform data, timestamps arre added
+--     FEE_waveform_to_36bits : convert waveform data to 36-bits wide data stream 
+--     FEE_wavemux2to1 : select next waveform, based on timestamp
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_dual_pulse_waveform is
+	generic (
+		ADCNUMBER               : natural := 0;
+		ADCBITS                 : natural := 14;
+		BASELINE_BWBITS         : natural := 10;
+		MWD_WIDTHBITS           : natural := 5;
+		MWD_SCALEBITS           : natural := 16;
+		MWD2_WIDTHBITS          : natural := 2;
+		MWD2_SCALEBITS          : natural := 16;
+		MWD_DOUBLEFILTER        : boolean := false;
+		MWD_PU_DOUBLEFILTER     : boolean := false;
+		WAVEFORMBUFFERSIZE      : natural := 11;
+		IDIVMAXBITS             : natural := 6;
+		INTEGRALRATIOBITS       : natural := 3;
+		CF_DELAYBITS            : natural := 8;
+		MAXPILEUPHITS           : natural := 3;
+		NOWAVEFORMS             : boolean := false
+		);
+    Port (
+		clock                   : in  std_logic;
+		reset                   : in  std_logic;
+		enable                  : in  std_logic;
+		enable_waveform         : in std_logic;
+		force_hit               : in std_logic;
+		CF_delay                : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+		CFpu_delay              : in std_logic_vector(1 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0); 
+		superburstupdate        : in std_logic; 
+		ADCdata_highgain        : in std_logic_vector(ADCBITS-1 downto 0);
+		ADCdata_lowgain         : in std_logic_vector(ADCBITS-1 downto 0);
+		MWD1_width              : in  std_logic_vector(MWD_WIDTHBITS-1 downto 0);
+		MWD1_tau_factor         : in  std_logic_vector(MWD_SCALEBITS-1 downto 0);
+		MWD2_width              : in  std_logic_vector(MWD2_WIDTHBITS-1 downto 0);
+		MWD2_tau_factor         : in  std_logic_vector(MWD2_SCALEBITS-1 downto 0);
+		MWDpu1_width            : in  std_logic_vector(1 downto 0);
+		MWDpu1_tau_factor       : in  std_logic_vector(MWD_SCALEBITS-1 downto 0);
+		MWDpu2_width            : in  std_logic_vector(MWD2_WIDTHBITS-1 downto 0);
+		MWDpu2_tau_factor       : in  std_logic_vector(MWD2_SCALEBITS-1 downto 0);
+		threshold_highgain      : in std_logic_vector(ADCBITS-1 downto 0);
+		threshold_lowgain       : in std_logic_vector(ADCBITS-1 downto 0);
+		enable_highgain         : in  std_logic;
+		enable_lowgain          : in  std_logic;
+		enable_rawdata          : in  std_logic;
+		IIRfilterBW             : in std_logic_vector(2 downto 0);
+		maxabovebaseline        : in std_logic_vector(3 downto 0);
+		minpulselength          : in std_logic_vector(7 downto 0);
+		pileuplength            : in std_logic_vector(7 downto 0);
+		maxwavelength           : in std_logic_vector(7 downto 0);
+		IdivMAX_discard         : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+		IdivMAX_pileup          : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+		fullsize_wave_highgain  : in  std_logic;
+		fullsize_wave_lowgain   : in  std_logic;
+		pulsedata_allowed       : in std_logic;
+		pulsedata_write         : out std_logic;
+		pulsedata_lowgain       : out std_logic;
+		pulsedata_superburst    : out std_logic_vector(30 downto 0);
+		pulsedata_timestamp     : out std_logic_vector(15 downto 0);
+		pulsedata_energy        : out std_logic_vector(15 downto 0);
+		pulsedata_CFvalbefore   : out std_logic_vector(15 downto 0);
+		pulsedata_CFvalafter    : out std_logic_vector(15 downto 0);
+		pulsedata_status        : out std_logic_vector(7 downto 0);
+		wavedata_allowed        : in std_logic;
+		wavedata_almostfull     : in std_logic;
+		wavedata_available      : out std_logic;
+		wavedata_write          : out std_logic;
+		wavedata_out            : out std_logic_vector(35 downto 0);
+		pulsedetect             : out std_logic;
+		overflow                : out std_logic;
+		error                   : out std_logic
+		);
+end FEE_dual_pulse_waveform;
+
+architecture Behavioral of FEE_dual_pulse_waveform is
+
+component FEE_baselinefollower_eventdetector is
+	generic (
+		ADCBITS                 : natural := ADCBITS;
+		BASELINE_BWBITS         : natural := BASELINE_BWBITS;
+		MWD_WIDTHBITS           : natural := MWD_WIDTHBITS;
+		MWD_SCALEBITS           : natural := MWD_SCALEBITS;
+		MWD2_WIDTHBITS          : natural := MWD2_WIDTHBITS;
+		MWD2_SCALEBITS          : natural := MWD2_SCALEBITS;
+		MWD_DOUBLEFILTER        : boolean := MWD_DOUBLEFILTER
+		);
+	port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		enable                  : in std_logic;
+		ADCdata                 : in std_logic_vector(ADCBITS-1 downto 0);
+		MWD1_width              : in std_logic_vector((MWD_WIDTHBITS-1) downto 0);
+		MWD1_tau_factor         : in std_logic_vector((MWD_SCALEBITS-1) downto 0);
+		MWD2_width              : in std_logic_vector(MWD2_WIDTHBITS-1 downto 0);
+		MWD2_tau_factor         : in std_logic_vector((MWD2_SCALEBITS-1) downto 0);
+		threshold               : in std_logic_vector(ADCBITS-1 downto 0);
+		IIRfilterBW             : in std_logic_vector(2 downto 0);
+		maxabovebaseline        : in std_logic_vector(3 downto 0);
+		ADC_minus_baseline      : out std_logic_vector(ADCBITS downto 0);
+		baseline_inhibit        : out std_logic;
+		pulse_active            : out std_logic;
+		pulse_rising            : out std_logic;
+		max_data                : out std_logic_vector(ADCBITS-1 downto 0)
+	);
+end component;
+
+component FEE_pileup_check is
+	generic (
+		ADCBITS                 : natural := ADCBITS;
+		IDIVMAXBITS             : natural := IDIVMAXBITS;
+		INTEGRALRATIOBITS       : natural := INTEGRALRATIOBITS
+		);
+   Port (
+		clock                   : in  std_logic;
+		reset                   : in  std_logic;
+		superburstnumber        : in std_logic_vector(30 downto 0); 
+		timestampcounter        : in std_logic_vector(15 downto 0); 
+		force_hit               : in std_logic;
+		ADC_highgain            : in std_logic_vector(ADCBITS downto 0); -- signed
+		enable_highgain         : in  std_logic;
+		threshold_highgain      : in std_logic_vector(ADCBITS-1 downto 0);
+		max_data_highgain       : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
+		pulse_active_highgain   : in std_logic;
+		pulse_rising_highgain   : in std_logic;
+		clipping_highgain       : in std_logic;
+		ADC_lowgain             : in std_logic_vector(ADCBITS downto 0); -- signed
+		enable_lowgain          : in  std_logic;
+		threshold_lowgain       : in std_logic_vector(ADCBITS-1 downto 0);
+		max_data_lowgain        : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
+		pulse_active_lowgain    : in std_logic;
+		pulse_rising_lowgain    : in std_logic;
+		minpulselength          : in std_logic_vector(7 downto 0);
+		pileuplength            : in std_logic_vector(7 downto 0);
+		maxwavelength           : in std_logic_vector(7 downto 0);
+		IdivMAX_discard         : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+		IdivMAX_pileup          : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+		fullsize_wave_highgain  : in  std_logic;
+		fullsize_wave_lowgain   : in  std_logic;
+		pulse_valid_highgain    : out std_logic;
+		singlepulse_highgain    : out std_logic;
+		pileuppulse_highgain    : out std_logic;
+		clearpulse_highgain     : out std_logic;
 		integral_highgain       : out std_logic_vector(15 downto 0);
 		pulse_valid_lowgain     : out std_logic;
 		singlepulse_lowgain     : out std_logic;
 		pileuppulse_lowgain     : out std_logic;
 		clearpulse_lowgain      : out std_logic;
 		integral_lowgain        : out std_logic_vector(15 downto 0);
-		superburst              : out std_logic_vector(15 downto 0);
-		timestamp               : out std_logic_vector(15 downto 0);
-		testword0               : out std_logic_vector(35 downto 0)
-		);
-end component;
-
-
-component FEE_extract_pulse is
-	generic (
-		ADCBITS                 : natural := ADCBITS;
-		WAVEFORMBUFFERSIZE      : natural := WAVEFORMBUFFERSIZE;
-		CF_DELAYBITS            : natural := CF_DELAYBITS
-		);
-   Port (
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		cf_delay                : in std_logic_vector(CF_DELAYBITS-1 downto 0);
-		pulse_valid             : in std_logic;
-		pulse_rising            : in std_logic;
-		pulse_detected          : in std_logic;
-		pileup_detected         : in std_logic;
-		clear_waveform          : in std_logic;
-		data_in                 : in std_logic_vector(ADCBITS downto 0); -- signed data
+		superburst              : out std_logic_vector(30 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0)
+		);
+end component;
+
+component FEE_pulse_detect is
+	generic (
+		ADCDATABITS             : natural := ADCBITS;
+		INTEGRALBITS            : natural := 0
+		);
+	Port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		ADCdata                 : in std_logic_vector(ADCDATABITS downto 0); -- signed
+		pulse_active            : in std_logic;
+		minpulselength          : in std_logic_vector(4 downto 0);
+		pulse_valid             : out std_logic;
+		singlepulse             : out std_logic;
+		integral                : out std_logic_vector(15 downto 0)
+		);
+end component;
+
+component FEE_extract_pulse is
+	generic (
+		ADCBITS                 : natural := ADCBITS;
+		CF_DELAYBITS            : natural := CF_DELAYBITS
+		);
+   Port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		cf_delay                : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+		pulse_valid             : in std_logic;
+		pulse_detected          : in std_logic;
+		pileup_detected         : in std_logic;
+		clear_waveform          : in std_logic;
+		data_in                 : in std_logic_vector(ADCBITS downto 0); -- signed data
 		integral                : in std_logic_vector(15 downto 0);
-		superburstnumber        : in std_logic_vector(30 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0);
 		timestamp               : in std_logic_vector(15 downto 0);
 		pulse_write             : out std_logic;
-		pulse_superburst        : out std_logic_vector(15 downto 0);
+		pulse_superburst        : out std_logic_vector(30 downto 0);
 		pulse_timestamp         : out std_logic_vector(15 downto 0);
 		pulse_skipped           : out std_logic;
 		pulse_energy            : out std_logic_vector(15 downto 0);
 		pulse_CF1               : out std_logic_vector(15 downto 0);
 		pulse_CF2               : out std_logic_vector(15 downto 0)
 		);
-end component;
-
-		
-component FEE_pulsewaveform_buffer is
-	generic (
-		ADCBITS                 : natural := ADCBITS;
-		WAVEFORMBUFFERSIZE      : natural := WAVEFORMBUFFERSIZE
-		);
-    Port (
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		pulse_valid             : in std_logic;
-		pulse_rising            : in std_logic;
-		pulse_detected          : in std_logic;
-		pileup_detected         : in std_logic;
-		clear_waveform          : in std_logic;
-		data_in                 : in std_logic_vector(ADCBITS downto 0); -- signed data
-		superburst               : in std_logic_vector(15 downto 0);
-		timestamp               : in std_logic_vector(15 downto 0);
-		data_out                : out std_logic_vector(35 downto 0);
-		data_out_read           : in std_logic;
-		data_out_available      : out std_logic;
-		overflow                : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
-		);
-end component;
-
-component FEE_waveform_to_36bits is
-    Port (
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		adcnumber               : in std_logic_vector(7 downto 0); 
-		data_in                 : in std_logic_vector(35 downto 0); 
-		data_in_available       : in std_logic;
-		data_in_read            : out std_logic;
-		overflow_in             : in std_logic;
-		pileupdata_out          : out std_logic_vector(35 downto 0);
-		pileupdata_write        : out std_logic;
-		pileupdata_allowed      : in std_logic;
-		pileupdata_almostfull   : in std_logic;
-		error                   : out std_logic;
-		overflow_out            : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
-		);
-end component;
-
-component FEE_wavemux2to1 is
-	generic(
-		TIMEOUTBITS             : natural := 16
-	);
-	Port (
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		data1_in                : in std_logic_vector(35 downto 0); 
-		data1_in_write          : in std_logic;
-		data1_in_available      : in std_logic;
-		data1_in_allowed        : out std_logic;
-		data2_in                : in std_logic_vector(35 downto 0); 
-		data2_in_write          : in std_logic;
-		data2_in_available      : in std_logic;
-		data2_in_allowed        : out std_logic;
-		data_out                : out std_logic_vector(35 downto 0);
-		data_out_write          : out std_logic;
-		data_out_available      : out std_logic;
-		data_out_allowed        : in std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
-	);
-end component;
-
-component FEE_pulse2to1_pulse is
-	Port (
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		channel                 : in std_logic_vector(7 downto 0);
-		pulse1_write            : in std_logic;
-		pulse1_superburst       : in std_logic_vector(15 downto 0);
-		pulse1_timestamp        : in std_logic_vector(15 downto 0);
-		pulse1_skipped          : in std_logic;
-		pulse1_energy           : in std_logic_vector(15 downto 0);
-		pulse1_CF1              : in std_logic_vector(15 downto 0);
-		pulse1_CF2              : in std_logic_vector(15 downto 0);
-		pulse2_write            : in std_logic;
-		pulse2_superburst       : in std_logic_vector(15 downto 0);
-		pulse2_timestamp        : in std_logic_vector(15 downto 0);
-		pulse2_skipped          : in std_logic;
-		pulse2_energy           : in std_logic_vector(15 downto 0);
-		pulse2_CF1              : in std_logic_vector(15 downto 0);
-		pulse2_CF2              : in std_logic_vector(15 downto 0);
-		pulse_skipped           : out std_logic;
-		data_out                : out std_logic_vector(35 downto 0);
-		data_out_write          : out std_logic;
-		data_out_almostfull     : in std_logic;
-		data_out_allowed        : in std_logic
-	);
-end component;
-
-
-
-signal pulsedetect_S               : std_logic := '0';
-
-signal pulse_active_highgain_S     : std_logic := '0';
-signal pulse_rising_highgain0_S    : std_logic := '0';
-signal pulse_rising_highgain_S     : std_logic := '0';
-signal pulse_active_lowgain_S      : std_logic := '0';
-signal pulse_rising_lowgain0_S     : std_logic := '0';
-signal pulse_rising_lowgain_S      : std_logic := '0';
-signal ADC_minus_baseline_highgain0_S : std_logic_vector(ADCBITS downto 0);
-signal ADC_minus_baseline_lowgain0_S : std_logic_vector(ADCBITS downto 0);
-signal ADC_minus_baseline_highgain_S : std_logic_vector(ADCBITS downto 0);
-signal ADC_minus_baseline_lowgain_S : std_logic_vector(ADCBITS downto 0);
-
-signal pulse_valid_highgain0_S     : std_logic := '0';
-signal pulse_valid_highgain_S      : std_logic := '0';
-signal singlepulse_highgain_S      : std_logic := '0';
-signal pileuppulse_highgain_S      : std_logic := '0';
-signal clearpulse_highgain_S       : std_logic := '0';
-signal integral_highgain_S         : std_logic_vector(15 downto 0);
-signal max_data_highgain_S         : std_logic_vector(ADCBITS-1 downto 0);
-signal clipping_highgain_S         : std_logic := '0';
-
-signal baseline_highgain_S         : std_logic_vector(ADCBITS-1 downto 0);
-signal baseline_inhibit_highgain_S : std_logic := '0';
-signal baseline_lowgain_S          : std_logic_vector(ADCBITS-1 downto 0);
-signal baseline_inhibit_lowgain_S  : std_logic := '0';
-
-signal pulse_valid_lowgain0_S      : std_logic := '0';
-signal pulse_valid_lowgain_S       : std_logic := '0';
-signal singlepulse_lowgain_S       : std_logic := '0';
-signal pileuppulse_lowgain_S       : std_logic := '0';
-signal clearpulse_lowgain_S        : std_logic := '0';
-signal integral_lowgain_S          : std_logic_vector(15 downto 0);
-signal max_data_lowgain_S          : std_logic_vector(ADCBITS-1 downto 0);
-signal superburst_S                : std_logic_vector(15 downto 0);
-signal timestamp_S                 : std_logic_vector(15 downto 0);
-
-signal adcnumber_highgain_S        : std_logic_vector(7 downto 0);
-signal data_out_highgain_S         : std_logic_vector(35 downto 0);
-signal data_out_available_highgain_S : std_logic := '0';
-signal data_out_read_highgain_S    : std_logic := '0';
-signal overflow_highgain_S         : std_logic := '0';
-signal overflow_hg_S               : std_logic := '0';
-signal pileupdata1_out_S           : std_logic_vector(35 downto 0);
-signal pileupdata1_write_S         : std_logic := '0';
-signal pileupdata1_allowed_S       : std_logic := '0';
-
-signal pulse_write_highgain_S      : std_logic;
-signal pulse_superburst_highgain_S : std_logic_vector(15 downto 0);
-signal pulse_timestamp_highgain_S  : std_logic_vector(15 downto 0);
-signal pulse_skipped_highgain_S    : std_logic;
-signal pulse_energy_highgain_S     : std_logic_vector(15 downto 0);
-signal pulse_CF1_highgain_S        : std_logic_vector(15 downto 0);
-signal pulse_CF2_highgain_S        : std_logic_vector(15 downto 0);
-
-signal pulse_write_lowgain_S       : std_logic;
-signal pulse_superburst_lowgain_S  : std_logic_vector(15 downto 0);
-signal pulse_timestamp_lowgain_S   : std_logic_vector(15 downto 0);
-signal pulse_skipped_lowgain_S     : std_logic;
-signal pulse_energy_lowgain_S      : std_logic_vector(15 downto 0);
-signal pulse_CF1_lowgain_S         : std_logic_vector(15 downto 0);
-signal pulse_CF2_lowgain_S         : std_logic_vector(15 downto 0);
+end component;
+
+component FEE_collect_pileup_pulses is
+	generic (
+		MAXPILEUPHITS           : natural := MAXPILEUPHITS
+		);
+    Port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		pulse_active            : in std_logic;
+		pileup_valid            : in std_logic;
+		detect_singlepulse      : in std_logic;
+		detect_pileuppulse      : in std_logic;
+		detect_clearpulse       : in std_logic;
+		detect_purge            : in std_logic;
+		data_in_write           : in std_logic;	
+		data_in_superburst      : in std_logic_vector(30 downto 0);
+		data_in_timestamp       : in std_logic_vector(15 downto 0);
+		data_in_energy          : in std_logic_vector(15 downto 0);
+		data_in_CF1             : in std_logic_vector(15 downto 0);
+		data_in_CF2             : in std_logic_vector(15 downto 0);
+		data_out_write          : out std_logic;
+		data_out_superburst     : out std_logic_vector(30 downto 0);
+		data_out_timestamp      : out std_logic_vector(15 downto 0);
+		data_out_energy         : out std_logic_vector(15 downto 0);
+		data_out_CF1            : out std_logic_vector(15 downto 0);
+		data_out_CF2            : out std_logic_vector(15 downto 0);
+		data_out_skipped        : out std_logic
+		);
+end component;
+		
+component FEE_pulsewaveform_buffer is
+	generic (
+		ADCBITS                 : natural := ADCBITS;
+		WAVEFORMBUFFERSIZE      : natural := WAVEFORMBUFFERSIZE
+		);
+    Port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		pulse_valid             : in std_logic;
+		pulse_rising            : in std_logic;
+		pulse_detected          : in std_logic;
+		pileup_detected         : in std_logic;
+		clear_waveform          : in std_logic;
+		data_in                 : in std_logic_vector(ADCBITS downto 0); -- signed data
+		superburst              : in std_logic_vector(15 downto 0);
+		timestamp               : in std_logic_vector(15 downto 0);
+		data_out                : out std_logic_vector(35 downto 0);
+		data_out_read           : in std_logic;
+		data_out_available      : out std_logic;
+		overflow                : out std_logic
+		);
+end component;
+
+component FEE_waveform_to_36bits is
+	generic (
+		ADCNUMBER               : natural := 0
+		);
+    Port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(35 downto 0); 
+		data_in_available       : in std_logic;
+		data_in_read            : out std_logic;
+		overflow_in             : in std_logic;
+		wavedata_out            : out std_logic_vector(35 downto 0);
+		wavedata_write          : out std_logic;
+		wavedata_inpipe         : out std_logic;
+		wavedata_allowed        : in std_logic;
+		wavedata_almostfull     : in std_logic;
+		error                   : out std_logic;
+		overflow_out            : out std_logic
+		);
+end component;
+
+component FEE_wavemux2to1 is
+	generic(
+		TIMEOUTBITS             : natural := 9
+	);
+	Port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data1_in                : in std_logic_vector(35 downto 0); 
+		data1_in_write          : in std_logic;
+		data1_in_available      : in std_logic;
+		data1_in_allowed        : out std_logic;
+		data2_in                : in std_logic_vector(35 downto 0); 
+		data2_in_write          : in std_logic;
+		data2_in_available      : in std_logic;
+		data2_in_allowed        : out std_logic;
+		data_out                : out std_logic_vector(35 downto 0);
+		data_out_write          : out std_logic;
+		data_out_available      : out std_logic;
+		data_out_allowed        : in std_logic;
+		error                   : out std_logic;
+		timeerror               : out std_logic
+	);
+end component;
+
+constant ZEROS                               : std_logic_vector(63 downto 0) := (others => '0');
+constant ONES                                : std_logic_vector(63 downto 0) := (others => '1');
+type pileupbuffer_superburst_type is array(0 to MAXPILEUPHITS-1) of std_logic_vector(30 downto 0);
+type pileupbuffer_16bits_type is array(0 to MAXPILEUPHITS-1) of std_logic_vector(15 downto 0);
+
+signal reset_buffer_S                        : std_logic;
+signal pulsedetect_S                         : std_logic;
+signal enable_S                              : std_logic;
+signal enable_highgain_S                     : std_logic;
+signal enable_lowgain_S                      : std_logic;
+signal timestampcounter_S                    : std_logic_vector(15 downto 0);
+signal superburstnumber_S                    : std_logic_vector(30 downto 0);
+signal pileuplength_S                        : std_logic_vector(7 downto 0);
+signal IdivMAX_pileup_S                      : std_logic_vector(IDIVMAXBITS-1 downto 0);
+
+signal ADCdata_highgain_S                    : std_logic_vector(ADCBITS-1 downto 0);
+signal pulse_active_highgain_S               : std_logic := '0';
+signal pulse_rising_highgain0_S              : std_logic := '0';
+signal pulse_rising_highgain_S               : std_logic := '0';
+signal pulse_active_lowgain_S                : std_logic := '0';
+signal pulse_rising_lowgain0_S               : std_logic := '0';
+signal pulse_rising_lowgain_S                : std_logic := '0';
+signal ADC_minus_baseline_highgain0_S        : std_logic_vector(ADCBITS downto 0);
+signal ADC_minus_baseline_lowgain0_S         : std_logic_vector(ADCBITS downto 0);
+signal ADC_minus_baseline_highgain_S         : std_logic_vector(ADCBITS downto 0);
+signal ADC_minus_baseline_lowgain_S          : std_logic_vector(ADCBITS downto 0);
+signal pulse_skipped_occurred_S              : std_logic := '0';
+
+
+
+signal ADCdata_lowgain_S                     : std_logic_vector(ADCBITS-1 downto 0);
+signal detect_pulse_valid_highgain0_S        : std_logic := '0';
+signal detect_pulse_valid_highgain_S         : std_logic := '0';
+signal detect_singlepulse_highgain_S         : std_logic := '0';
+signal detect_pileuppulse_highgain_S         : std_logic := '0';
+signal detect_clearpulse_highgain_S          : std_logic := '0';
+signal detect_pileupvalidpulse_highgain_S    : std_logic;
+signal detect_integral_highgain_S            : std_logic_vector(15 downto 0);
+signal detect_purge_highgain_S               : std_logic;
+signal max_data_highgain_S                   : std_logic_vector(ADCBITS-1 downto 0);
+signal clipping_highgain_S                   : std_logic := '0';
+
+signal baseline_inhibit_highgain_S           : std_logic := '0';
+signal baseline_inhibit_lowgain_S            : std_logic := '0';
+
+signal detect_pulse_valid_lowgain0_S         : std_logic := '0';
+signal detect_pulse_valid_lowgain_S          : std_logic := '0';
+signal detect_singlepulse_lowgain_S          : std_logic := '0';
+signal detect_pileuppulse_lowgain_S          : std_logic := '0';
+signal detect_clearpulse_lowgain_S           : std_logic := '0';
+signal detect_pileupvalidpulse_lowgain_S     : std_logic;
+signal detect_integral_lowgain_S             : std_logic_vector(15 downto 0);
+signal detect_purge_lowgain_S                : std_logic;
+signal max_data_lowgain_S                    : std_logic_vector(ADCBITS-1 downto 0);
+signal detect_superburst_S                   : std_logic_vector(30 downto 0);
+signal detect_timestamp_S                    : std_logic_vector(15 downto 0);
+
+signal wavedata_highgain_S                   : std_logic_vector(35 downto 0);
+signal wavedata_available_highgain_S         : std_logic := '0';
+signal wavedata_read_highgain_S              : std_logic := '0';
+signal wave_overflow_highgain_S              : std_logic := '0';
+signal wave_overflow_hg_S                    : std_logic := '0';
+signal wavedata1_out_S                       : std_logic_vector(35 downto 0);
+signal wavedata1_write_S                     : std_logic;
+signal wavedata1_allowed_S                   : std_logic;
+signal wavedata1_inpipe_S                    : std_logic;
+
+signal pulse_write_highgain_S                : std_logic;
+signal pulse_superburst_highgain_S           : std_logic_vector(30 downto 0);
+signal pulse_timestamp_highgain_S            : std_logic_vector(15 downto 0);
+signal pulse_skipped_highgain_S              : std_logic;
+signal pulse_energy_highgain_S               : std_logic_vector(15 downto 0);
+signal pulse_CF1_highgain_S                  : std_logic_vector(15 downto 0);
+signal pulse_CF2_highgain_S                  : std_logic_vector(15 downto 0);
+
+signal threshold_pileup_highgain_S           : std_logic_vector(ADCBITS-1 downto 0);
+signal pileup_ADC_minus_baseline_highgain0_S : std_logic_vector(ADCBITS downto 0);
+signal pileup_ADC_minus_baseline_highgain_S  : std_logic_vector(ADCBITS downto 0);
+
+signal pileup_active_highgain_S              : std_logic;
+signal pileup_rising_highgain0_S             : std_logic;
+signal pileup_valid_highgain_S               : std_logic;
+signal pileup_pulse_highgain_S               : std_logic;
+signal pileup_integral_highgain_S            : std_logic_vector(15 downto 0);
+
+signal pileupdta_write_highgain_S            : std_logic;
+signal pileupdta_superburst_highgain_S       : std_logic_vector(30 downto 0);
+signal pileupdta_timestamp_highgain_S        : std_logic_vector(15 downto 0);
+signal pileupdta_energy_highgain_S           : std_logic_vector(15 downto 0);
+signal pileupdta_CF1_highgain_S              : std_logic_vector(15 downto 0);
+signal pileupdta_CF2_highgain_S              : std_logic_vector(15 downto 0);
+
+signal pulse_write_lowgain_S                 : std_logic;
+signal pulse_superburst_lowgain_S            : std_logic_vector(30 downto 0);
+signal pulse_timestamp_lowgain_S             : std_logic_vector(15 downto 0);
+signal pulse_skipped_lowgain_S               : std_logic;
+signal pulse_energy_lowgain_S                : std_logic_vector(15 downto 0);
+signal pulse_CF1_lowgain_S                   : std_logic_vector(15 downto 0);
+signal pulse_CF2_lowgain_S                   : std_logic_vector(15 downto 0);
+signal pulsedata_status0_S                   : std_logic_vector(7 downto 0);
+signal pulsedata_status1_S                   : std_logic_vector(7 downto 0);
+
+signal threshold_pileup_lowgain_S            : std_logic_vector(ADCBITS-1 downto 0);
+signal pileup_ADC_minus_baseline_lowgain0_S  : std_logic_vector(ADCBITS downto 0);
+signal pileup_ADC_minus_baseline_lowgain_S   : std_logic_vector(ADCBITS downto 0);
+
+signal pileup_active_lowgain_S               : std_logic;
+signal pileup_rising_lowgain0_S              : std_logic;
+signal pileup_valid_lowgain_S                : std_logic;
+signal pileup_pulse_lowgain_S                : std_logic;
+signal pileup_integral_lowgain_S             : std_logic_vector(15 downto 0);
+
+signal pileupdta_write_lowgain_S             : std_logic;
+signal pileupdta_superburst_lowgain_S        : std_logic_vector(30 downto 0);
+signal pileupdta_timestamp_lowgain_S         : std_logic_vector(15 downto 0);
+signal pileupdta_energy_lowgain_S            : std_logic_vector(15 downto 0);
+signal pileupdta_CF1_lowgain_S               : std_logic_vector(15 downto 0);
+signal pileupdta_CF2_lowgain_S               : std_logic_vector(15 downto 0);
+
+signal pileup_write_highgain_S               : std_logic;
+signal pileup_superburst_highgain_S          : std_logic_vector(30 downto 0);
+signal pileup_timestamp_highgain_S           : std_logic_vector(15 downto 0);
+signal pileup_energy_highgain_S              : std_logic_vector(15 downto 0);
+signal pileup_CF1_highgain_S                 : std_logic_vector(15 downto 0);
+signal pileup_CF2_highgain_S                 : std_logic_vector(15 downto 0);
+signal pileup_skipped_highgain_S             : std_logic := '0';
+
+signal pileup_write_lowgain_S                : std_logic;
+signal pileup_superburst_lowgain_S           : std_logic_vector(30 downto 0);
+signal pileup_timestamp_lowgain_S            : std_logic_vector(15 downto 0);
+signal pileup_energy_lowgain_S               : std_logic_vector(15 downto 0);
+signal pileup_CF1_lowgain_S                  : std_logic_vector(15 downto 0);
+signal pileup_CF2_lowgain_S                  : std_logic_vector(15 downto 0);
+signal pileup_skipped_lowgain_S              : std_logic := '0';
+
+signal pulsedata_superburst_S                : std_logic_vector(30 downto 0);
+signal pulsedata_timestamp_S                 : std_logic_vector(15 downto 0);
+
+signal wavedata_lowgain_S                    : std_logic_vector(35 downto 0);
+signal wavedata_available_lowgain_S          : std_logic := '0';
+signal wavedata_read_lowgain_S               : std_logic := '0';
+signal wave_overflow_lowgain_S               : std_logic := '0';
+signal wave_overflow_lg_S                    : std_logic := '0';
+signal wavedata2_out_S                       : std_logic_vector(35 downto 0);
+signal wavedata2_write_S                     : std_logic;
+signal wavedata2_allowed_S                   : std_logic;
+signal wavedata2_inpipe_S                    : std_logic;
+
+signal pulsedata_write_S                     : std_logic := '0';
+signal wavedata_out_S                        : std_logic_vector(35 downto 0);
+signal wavedata_write_S                      : std_logic := '0';
+
+signal wave_error_S                          : std_logic := '0';
+signal wave_error_to36_1_S                   : std_logic := '0';
+signal wave_error_to36_2_S                   : std_logic := '0';
+signal data_error_S                          : std_logic := '0';
+signal pulsetime_error_S                     : std_logic := '0';
+
+		
+attribute mark_debug : string;
+
+-- attribute mark_debug of clipping_highgain_S : signal is "true";
+
+-- attribute mark_debug of ADCdata_highgain_S : signal is "true";
+-- attribute mark_debug of pulse_active_highgain_S : signal is "true";
+-- attribute mark_debug of ADC_minus_baseline_highgain_S : signal is "true";
+-- attribute mark_debug of detect_singlepulse_highgain_S : signal is "true";
+-- attribute mark_debug of detect_pileuppulse_highgain_S : signal is "true";
+-- attribute mark_debug of detect_clearpulse_highgain_S : signal is "true";
+-- attribute mark_debug of detect_pileupvalidpulse_highgain_S : signal is "true";
+-- attribute mark_debug of pileup_write_highgain_S : signal is "true";
+-- attribute mark_debug of pileup_skipped_highgain_S : signal is "true";
+-- attribute mark_debug of pileup_ADC_minus_baseline_highgain0_S : signal is "true";
+-- attribute mark_debug of pileup_active_highgain_S : signal is "true";
+-- attribute mark_debug of pileup_integral_highgain_S : signal is "true";
+-- attribute mark_debug of pileup_valid_highgain_S : signal is "true";
+-- attribute mark_debug of pileup_pulse_highgain_S : signal is "true";
+-- attribute mark_debug of pileupdta_write_highgain_S : signal is "true";
+-- attribute mark_debug of pileup_hitcount_highgain_S : signal is "true";
+-- attribute mark_debug of pileup_resultcount_highgain_S : signal is "true";
+-- attribute mark_debug of pileup_readcount_highgain_S : signal is "true";
+
+-- attribute mark_debug of ADCdata_lowgain_S : signal is "true";
+-- attribute mark_debug of pulse_active_lowgain_S : signal is "true";
+-- attribute mark_debug of ADC_minus_baseline_lowgain_S : signal is "true";
+-- attribute mark_debug of detect_singlepulse_lowgain_S : signal is "true";
+-- attribute mark_debug of detect_pileuppulse_lowgain_S : signal is "true";
+-- attribute mark_debug of detect_clearpulse_lowgain_S : signal is "true";
+-- attribute mark_debug of detect_pileupvalidpulse_lowgain_S : signal is "true";
+-- attribute mark_debug of pileup_write_lowgain_S : signal is "true";
+-- attribute mark_debug of pileup_skipped_lowgain_S : signal is "true";
+-- attribute mark_debug of pileup_ADC_minus_baseline_lowgain0_S : signal is "true";
+-- attribute mark_debug of pileup_active_lowgain_S : signal is "true";
+-- attribute mark_debug of pileup_integral_lowgain_S : signal is "true";
+-- attribute mark_debug of pileup_valid_lowgain_S : signal is "true";
+-- attribute mark_debug of pileup_pulse_lowgain_S : signal is "true";
+-- attribute mark_debug of pileupdta_write_lowgain_S : signal is "true";
+-- attribute mark_debug of pileup_hitcount_lowgain_S : signal is "true";
+-- attribute mark_debug of pileup_resultcount_lowgain_S : signal is "true";
+-- attribute mark_debug of pileup_readcount_lowgain_S : signal is "true";
+
+-- attribute mark_debug of pulse_write_highgain_S : signal is "true";
+-- attribute mark_debug of pulse_skipped_highgain_S : signal is "true";
+-- attribute mark_debug of pulse_write_lowgain_S : signal is "true";
+-- attribute mark_debug of pulse_skipped_lowgain_S : signal is "true";
+-- attribute mark_debug of pulsedata_write_S : signal is "true";
+-- attribute mark_debug of pulsedata_allowed : signal is "true";
+
+-- attribute mark_debug of wavedata1_write_S : signal is "true";
+-- attribute mark_debug of wavedata1_inpipe_S : signal is "true";
+-- attribute mark_debug of wavedata1_allowed_S : signal is "true";
+-- attribute mark_debug of wavedata2_write_S : signal is "true";
+-- attribute mark_debug of wavedata2_inpipe_S : signal is "true";
+-- attribute mark_debug of wavedata2_allowed_S : signal is "true";
+-- attribute mark_debug of wavedata_write_S : signal is "true";
+-- attribute mark_debug of wavedata_available : signal is "true";
+-- attribute mark_debug of wavedata_allowed : signal is "true";
+
+-- attribute mark_debug of wave_overflow_highgain_S : signal is "true";
+-- attribute mark_debug of wave_overflow_lowgain_S : signal is "true";
+-- attribute mark_debug of wave_overflow_hg_S : signal is "true";
+-- attribute mark_debug of wave_overflow_lg_S : signal is "true";
+
+begin
+
+error <= '1' when ((wave_error_to36_1_S='1') or (wave_error_to36_2_S='1') or (wave_error_S='1')) and (enable_waveform='1') else '0';
+overflow <= '1' when 
+		(((wave_overflow_highgain_S='1') or (wave_overflow_lowgain_S='1') or (wave_overflow_hg_S='1') or (wave_overflow_lg_S='1')) and (enable_waveform='1'))
+--			or ((pulse_skipped_highgain_S='1') and (pulse_write_highgain_S='1') and (enable_waveform='0'))
+--			or ((pulse_skipped_lowgain_S='1') and (pulse_write_lowgain_S='1') and (enable_waveform='0')) 
+			or ((pulse_skipped_occurred_S='1') and (enable_waveform='0'))
+		else '0';
+
+enable_S <= '1' when (enable='1') and ((enable_highgain='1') or (enable_lowgain='1')) else '0';
+enable_highgain_S <= '1' when (enable_highgain='1') or ((enable_lowgain='0') and (enable_highgain='0')) else '0';
+enable_lowgain_S <= '1' when (enable_lowgain='1') or ((enable_lowgain='0') and (enable_highgain='0')) else '0';
+
+
+pulsedetect <= pulsedetect_S;
+pulsedetect_S <= '1' when (detect_singlepulse_highgain_S='1') or (detect_pileuppulse_highgain_S='1') 
+	or (detect_singlepulse_lowgain_S='1') or (detect_pileuppulse_lowgain_S='1') else '0';
+
+ADCdata_highgain_S <= ADCdata_highgain;
+ADCdata_lowgain_S <= ADCdata_lowgain;
+
+
+timestampcounter: process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if superburstupdate='1' then
+			timestampcounter_S <= (others => '0');
+			superburstnumber_S <= superburstnumber;
+		else
+			timestampcounter_S <= timestampcounter_S+1;
+		end if;
+	end if;
+end process;
+
+-- Regular hits ------------------------------------------------------------------------------------------------------------
+
+baseline_high: FEE_baselinefollower_eventdetector 
+	generic map(
+		ADCBITS => ADCBITS,
+		BASELINE_BWBITS => BASELINE_BWBITS,
+		MWD_WIDTHBITS => MWD_WIDTHBITS,
+		MWD_SCALEBITS => MWD_SCALEBITS,
+		MWD2_WIDTHBITS => MWD2_WIDTHBITS,
+		MWD2_SCALEBITS => MWD2_SCALEBITS,
+		MWD_DOUBLEFILTER => MWD_DOUBLEFILTER)
+	port map(
+		clock => clock,
+		reset => reset,
+		enable => enable_S,
+		ADCdata => ADCdata_highgain_S,
+		MWD1_width => MWD1_width,
+		MWD1_tau_factor => MWD1_tau_factor,
+		MWD2_width => MWD2_width,
+		MWD2_tau_factor => MWD2_tau_factor,
+		threshold => threshold_highgain,
+		IIRfilterBW => IIRfilterBW,
+		maxabovebaseline => maxabovebaseline,
+		ADC_minus_baseline => ADC_minus_baseline_highgain0_S,
+		baseline_inhibit => baseline_inhibit_highgain_S,
+		pulse_active => pulse_active_highgain_S,
+		pulse_rising => pulse_rising_highgain0_S,
+		max_data => max_data_highgain_S);
+
+baseline_low: FEE_baselinefollower_eventdetector 
+	generic map(
+		ADCBITS => ADCBITS,
+		BASELINE_BWBITS => BASELINE_BWBITS,
+		MWD_WIDTHBITS => MWD_WIDTHBITS,
+		MWD_SCALEBITS => MWD_SCALEBITS,
+		MWD2_WIDTHBITS => MWD2_WIDTHBITS,
+		MWD2_SCALEBITS => MWD2_SCALEBITS,
+		MWD_DOUBLEFILTER => MWD_DOUBLEFILTER)
+	port map(
+		clock => clock,
+		reset => reset,
+		enable => enable_S,
+		ADCdata => ADCdata_lowgain_S,
+		MWD1_width => MWD1_width,
+		MWD1_tau_factor => MWD1_tau_factor,
+		MWD2_width => MWD2_width,
+		MWD2_tau_factor => MWD2_tau_factor,
+		threshold => threshold_lowgain,
+		IIRfilterBW => IIRfilterBW,
+		maxabovebaseline => maxabovebaseline,
+		ADC_minus_baseline => ADC_minus_baseline_lowgain0_S,
+		baseline_inhibit => baseline_inhibit_lowgain_S,
+		pulse_active => pulse_active_lowgain_S,
+		pulse_rising => pulse_rising_lowgain0_S,
+		max_data => max_data_lowgain_S);
+		
+pileuplength_S <= pileuplength when enable_waveform='0' else (others => '0');
+IdivMAX_pileup_S <= IdivMAX_pileup when enable_waveform='0' else (others => '1');
+pileup_check1: FEE_pileup_check port map(
+		clock => clock,
+		reset => reset,
+		superburstnumber => superburstnumber_S,
+		timestampcounter => timestampcounter_S, 
+		force_hit => force_hit,
+		ADC_highgain => ADC_minus_baseline_highgain0_S,
+		enable_highgain => enable_highgain_S,
+		threshold_highgain => threshold_highgain,
+		max_data_highgain => max_data_highgain_S,
+		pulse_active_highgain => pulse_active_highgain_S,
+		pulse_rising_highgain => pulse_rising_highgain0_S,
+		clipping_highgain => clipping_highgain_S,
+		ADC_lowgain => ADC_minus_baseline_lowgain0_S,
+		enable_lowgain => enable_lowgain_S,
+		threshold_lowgain => threshold_lowgain,
+		max_data_lowgain => max_data_lowgain_S,
+		pulse_active_lowgain => pulse_active_lowgain_S,
+		pulse_rising_lowgain => pulse_rising_lowgain0_S,
+		minpulselength => minpulselength,
+		pileuplength => pileuplength_S,
+		maxwavelength => maxwavelength,
+		IdivMAX_discard => IdivMAX_discard,
+		IdivMAX_pileup => IdivMAX_pileup_S,
+		fullsize_wave_highgain => fullsize_wave_highgain,
+		fullsize_wave_lowgain => fullsize_wave_lowgain,
+		pulse_valid_highgain => detect_pulse_valid_highgain0_S,
+		singlepulse_highgain => detect_singlepulse_highgain_S,
+		pileuppulse_highgain => detect_pileuppulse_highgain_S,
+		clearpulse_highgain => detect_clearpulse_highgain_S,
+		integral_highgain => detect_integral_highgain_S,
+		pulse_valid_lowgain => detect_pulse_valid_lowgain0_S,
+		singlepulse_lowgain => detect_singlepulse_lowgain_S,
+		pileuppulse_lowgain => detect_pileuppulse_lowgain_S,
+		clearpulse_lowgain => detect_clearpulse_lowgain_S,
+		integral_lowgain => detect_integral_lowgain_S,
+		superburst => detect_superburst_S,
+		timestamp => detect_timestamp_S);
 
 		
-		
-signal adcnumber_lowgain_S         : std_logic_vector(7 downto 0);
-signal data_out_lowgain_S          : std_logic_vector(35 downto 0);
-signal data_out_available_lowgain_S : std_logic := '0';
-signal data_out_read_lowgain_S     : std_logic := '0';
-signal overflow_lowgain_S          : std_logic := '0';
-signal overflow_lg_S               : std_logic := '0';
-signal pileupdata2_out_S           : std_logic_vector(35 downto 0);
-signal pileupdata2_write_S         : std_logic := '0';
-signal pileupdata2_allowed_S       : std_logic := '0';
-
-signal pulsedata_out_S             : std_logic_vector(35 downto 0);
-signal pulsedata_write_S           : std_logic := '0';
-signal pileupdata_out_S            : std_logic_vector(35 downto 0);
-signal pileupdata_write_S          : std_logic := '0';
-
-signal error_pulse_S               : std_logic := '0';
-signal error_pileup_S              : std_logic := '0';
-signal error_to36_1_S              : std_logic := '0';
-signal error_to36_2_S              : std_logic := '0';
-
-signal testword0_S                 : std_logic_vector(35 downto 0) := (others => '0');
-signal testword1_S                 : std_logic_vector(35 downto 0) := (others => '0');
-signal testword2_S                 : std_logic_vector(35 downto 0) := (others => '0');
-
-begin
-
-pulsedetect <= pulsedetect_S;
-pulsedetect_S <= '1' when (singlepulse_highgain_S='1') or (pileuppulse_highgain_S='1') 
-	or (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') else '0';
-
-FEE_baselinefollower_eventdetector_highgain: FEE_baselinefollower_eventdetector port map(
-		clock => clock,
-		reset => reset,
-		enable => enable,
-		ADCdata => ADCdata_highgain,
-		threshold => threshold_highgain,
-		IIRfilterBW => IIRfilterBW,
-		maxabovebaseline => maxabovebaseline,
-		baseline => baseline_highgain_S,
-		ADC_delayed => open,
-		ADC_minus_baseline => ADC_minus_baseline_highgain0_S,
-		baseline_inhibit => baseline_inhibit_highgain_S,
-		pulse_active => pulse_active_highgain_S,
-		pulse_rising => pulse_rising_highgain0_S,
-		max_data => max_data_highgain_S);
-ADC_minus_baseline_highgain <= ADC_minus_baseline_highgain_S;
-
-FEE_baselinefollower_eventdetector_lowgain: FEE_baselinefollower_eventdetector port map(
-		clock => clock,
-		reset => reset,
-		enable => enable,
-		ADCdata => ADCdata_lowgain,
-		threshold => threshold_lowgain,
-		IIRfilterBW => IIRfilterBW,
-		maxabovebaseline => maxabovebaseline,
-		baseline => baseline_lowgain_S,
-		ADC_delayed => open,
-		ADC_minus_baseline => ADC_minus_baseline_lowgain0_S,
-		baseline_inhibit => baseline_inhibit_lowgain_S,
-		pulse_active => pulse_active_lowgain_S,
-		pulse_rising => pulse_rising_lowgain0_S,
-		max_data => max_data_lowgain_S);
-ADC_minus_baseline_lowgain <= ADC_minus_baseline_lowgain_S;
-
-FEE_pileup_check1: FEE_pileup_check port map(
-		clock => clock,
-		reset => reset,
-		superburstnumber => superburstnumber,
-		timestampcounter => timestampcounter, 
-		ADC_highgain => ADC_minus_baseline_highgain0_S,
-		enable_highgain => enable_highgain,
-		max_data_highgain => max_data_highgain_S,
-		pulse_active_highgain => pulse_active_highgain_S,
-		pulse_rising_highgain => pulse_rising_highgain0_S,
-		clipping_highgain => clipping_highgain_S,
-		ADC_lowgain => ADC_minus_baseline_lowgain0_S,
-		enable_lowgain => enable_lowgain,
-		max_data_lowgain => max_data_lowgain_S,
-		pulse_active_lowgain => pulse_active_lowgain_S,
-		pulse_rising_lowgain => pulse_rising_lowgain0_S,
-		minpulselength => minpulselength,
-		pileuplength => pileuplength,
-		maxwavelength => maxwavelength,
-		IdivMAX_discard => IdivMAX_discard,
-		IdivMAX_pileup => IdivMAX_pileup,
-		fullsize_wave_highgain => fullsize_wave_highgain,
-		fullsize_wave_lowgain => fullsize_wave_lowgain,
-		pulse_valid_highgain => pulse_valid_highgain0_S,
-		singlepulse_highgain => singlepulse_highgain_S,
-		pileuppulse_highgain => pileuppulse_highgain_S,
-		clearpulse_highgain => clearpulse_highgain_S,
-		integral_highgain => integral_highgain_S,
-		pulse_valid_lowgain => pulse_valid_lowgain0_S,
-		singlepulse_lowgain => singlepulse_lowgain_S,
-		pileuppulse_lowgain => pileuppulse_lowgain_S,
-		clearpulse_lowgain => clearpulse_lowgain_S,
-		integral_lowgain => integral_lowgain_S,
-		superburst => superburst_S,
-		timestamp => timestamp_S,
-		testword0 => open);
-
-		
-process(clock)
-begin
+process(clock)
+begin
 	if (rising_edge(clock)) then 
-		if enable_highgain='1' then
-			pulse_valid_highgain_S <= pulse_valid_highgain0_S;
+		if enable_highgain_S='1' then
+			detect_pulse_valid_highgain_S <= detect_pulse_valid_highgain0_S;
 			pulse_rising_highgain_S <= pulse_rising_highgain0_S;
 		else
-			pulse_valid_highgain_S <= '0';
+			detect_pulse_valid_highgain_S <= '0';
 			pulse_rising_highgain_S <= '0';
-		end if;
-		ADC_minus_baseline_highgain_S <= ADC_minus_baseline_highgain0_S;
-		if enable_lowgain='1' then
-			pulse_valid_lowgain_S <= pulse_valid_lowgain0_S;
+		end if;
+		if enable_rawdata='1' then
+			ADC_minus_baseline_highgain_S <= '0' & ADCdata_highgain_S;
+		else
+			ADC_minus_baseline_highgain_S <= ADC_minus_baseline_highgain0_S;
+		end if;
+		if enable_lowgain_S='1' then
+			detect_pulse_valid_lowgain_S <= detect_pulse_valid_lowgain0_S;
 			pulse_rising_lowgain_S <= pulse_rising_lowgain0_S;
 		else
-			pulse_valid_lowgain_S <= '0';
+			detect_pulse_valid_lowgain_S <= '0';
 			pulse_rising_lowgain_S <= '0';
-		end if;
-		ADC_minus_baseline_lowgain_S <= ADC_minus_baseline_lowgain0_S;
-		if pulse_active_highgain_S='1' then
-			if ADCdata_highgain((ADCBITS-1) downto (ADCBITS-4)) = "1111" then
-				clipping_highgain_S <= '1';
-			end if;
-		else
-			clipping_highgain_S <= '0';
-		end if;
-	end if;
+		end if;
+		if enable_rawdata='1' then
+			ADC_minus_baseline_lowgain_S <= '0' & ADCdata_lowgain_S;
+		else
+			ADC_minus_baseline_lowgain_S <= ADC_minus_baseline_lowgain0_S;
+		end if;
+		if pulse_active_highgain_S='1' then
+			if ADCdata_highgain_S((ADCBITS-1) downto (ADCBITS-4)) = "1111" then
+				clipping_highgain_S <= '1';
+			end if;
+			if (detect_pulse_valid_highgain_S='1') and (ADC_minus_baseline_highgain0_S(ADCBITS)='0') and (ADC_minus_baseline_highgain0_S(ADCBITS-1 downto 0)=ONES(ADCBITS-1 downto 0)) then
+				clipping_highgain_S <= '1';
+			end if;
+		else
+			clipping_highgain_S <= '0';
+		end if;
+	end if;
 end process;
 
-FEE_extract_pulse1: FEE_extract_pulse port map(
-		clock => clock,
-		reset => reset,
-		cf_delay => cf_delay,
-		pulse_valid => pulse_valid_highgain_S,
-		pulse_rising => pulse_rising_highgain_S,
-		pulse_detected => singlepulse_highgain_S,
-		pileup_detected => pileuppulse_highgain_S,
-		clear_waveform => clearpulse_highgain_S,
+extract_high: FEE_extract_pulse 
+	generic map(
+		ADCBITS => ADCBITS,
+		CF_DELAYBITS => CF_DELAYBITS)
+	port map(
+		clock => clock,
+		reset => reset,
+		cf_delay => CF_delay,
+		pulse_valid => detect_pulse_valid_highgain_S,
+		pulse_detected => detect_singlepulse_highgain_S,
+		pileup_detected => detect_pileuppulse_highgain_S,
+		clear_waveform => detect_clearpulse_highgain_S,
 		data_in => ADC_minus_baseline_highgain_S,
-		integral => integral_highgain_S,
-		superburstnumber => superburstnumber,
-		timestamp => timestampcounter,
-		pulse_write => pulse_write_highgain_S,
-		pulse_superburst => pulse_superburst_highgain_S,
+		integral => detect_integral_highgain_S,
+		superburstnumber => superburstnumber_S,
+		timestamp => timestampcounter_S,
+		pulse_write => pulse_write_highgain_S,
+		pulse_superburst => pulse_superburst_highgain_S,
 		pulse_timestamp => pulse_timestamp_highgain_S,
-		pulse_skipped => pulse_skipped_highgain_S,
-		pulse_energy => pulse_energy_highgain_S,
-		pulse_CF1 => pulse_CF1_highgain_S,
+		pulse_skipped => pulse_skipped_highgain_S,
+		pulse_energy => pulse_energy_highgain_S,
+		pulse_CF1 => pulse_CF1_highgain_S,
 		pulse_CF2 => pulse_CF2_highgain_S);
 
-FEE_extract_pulse2: FEE_extract_pulse port map(
-		clock => clock,
-		reset => reset,
-		cf_delay => cf_delay,
-		pulse_valid => pulse_valid_lowgain_S,
-		pulse_rising => pulse_rising_lowgain_S,
-		pulse_detected => singlepulse_lowgain_S,
-		pileup_detected => pileuppulse_lowgain_S,
-		clear_waveform => clearpulse_lowgain_S,
+extract_low: FEE_extract_pulse 
+	generic map(
+		ADCBITS => ADCBITS,
+		CF_DELAYBITS => CF_DELAYBITS)
+	port map(
+		clock => clock,
+		reset => reset,
+		cf_delay => CF_delay,
+		pulse_valid => detect_pulse_valid_lowgain_S,
+		pulse_detected => detect_singlepulse_lowgain_S,
+		pileup_detected => detect_pileuppulse_lowgain_S,
+		clear_waveform => detect_clearpulse_lowgain_S,
 		data_in => ADC_minus_baseline_lowgain_S,
-		integral => integral_lowgain_S,
-		superburstnumber => superburstnumber,
-		timestamp => timestampcounter,
-		pulse_write => pulse_write_lowgain_S,
-		pulse_superburst => pulse_superburst_lowgain_S,
-		pulse_timestamp => pulse_timestamp_lowgain_S,
-		pulse_skipped => pulse_skipped_lowgain_S,
-		pulse_energy => pulse_energy_lowgain_S,
-		pulse_CF1 => pulse_CF1_lowgain_S,
+		integral => detect_integral_lowgain_S,
+		superburstnumber => superburstnumber_S,
+		timestamp => timestampcounter_S,
+		pulse_write => pulse_write_lowgain_S,
+		pulse_superburst => pulse_superburst_lowgain_S,
+		pulse_timestamp => pulse_timestamp_lowgain_S,
+		pulse_skipped => pulse_skipped_lowgain_S,
+		pulse_energy => pulse_energy_lowgain_S,
+		pulse_CF1 => pulse_CF1_lowgain_S,
 		pulse_CF2 => pulse_CF2_lowgain_S);		
 
-FEE_pulsewaveform_buffer1: FEE_pulsewaveform_buffer port map(
-		clock => clock,
-		reset => reset,
-		pulse_valid => pulse_valid_highgain_S,
-		pulse_rising => pulse_rising_highgain_S,
-		pulse_detected => singlepulse_highgain_S,
-		pileup_detected => pileuppulse_highgain_S,
-		clear_waveform => clearpulse_highgain_S,
-		data_in => ADC_minus_baseline_highgain_S,
-		superburst => superburst_S,
-		timestamp => timestamp_S,
-		data_out => data_out_highgain_S,
-		data_out_read => data_out_read_highgain_S,
-		data_out_available => data_out_available_highgain_S,
-		overflow => overflow_highgain_S,
-		testword0 => testword1);
-
-FEE_pulsewaveform_buffer2: FEE_pulsewaveform_buffer port map(
-		clock => clock,
-		reset => reset,
-		pulse_valid => pulse_valid_lowgain_S,
-		pulse_rising => pulse_rising_lowgain_S,
-		pulse_detected => singlepulse_lowgain_S,
-		pileup_detected => pileuppulse_lowgain_S,
-		clear_waveform => clearpulse_lowgain_S,
-		data_in => ADC_minus_baseline_lowgain_S,
-		superburst => superburst_S,
-		timestamp => timestamp_S,
-		data_out => data_out_lowgain_S,
-		data_out_read => data_out_read_lowgain_S,
-		data_out_available => data_out_available_lowgain_S,
-		overflow => overflow_lowgain_S,
-		testword0 => open);		
-		
-FEE_pulse2to1_pulse1: FEE_pulse2to1_pulse port map(
-		clock => clock,
-		reset => reset,
-		channel => adcnumber, 
-		pulse1_write => pulse_write_highgain_S,
-		pulse1_superburst => pulse_superburst_highgain_S,
-		pulse1_timestamp => pulse_timestamp_highgain_S,
-		pulse1_skipped => pulse_skipped_highgain_S,
-		pulse1_energy => pulse_energy_highgain_S,
-		pulse1_CF1 => pulse_CF1_highgain_S,
-		pulse1_CF2 => pulse_CF2_highgain_S,
-		pulse2_write => pulse_write_lowgain_S,
-		pulse2_superburst => pulse_superburst_lowgain_S,
-		pulse2_timestamp => pulse_timestamp_lowgain_S,
-		pulse2_skipped => pulse_skipped_lowgain_S,
-		pulse2_energy => pulse_energy_lowgain_S,
-		pulse2_CF1 => pulse_CF1_lowgain_S,
-		pulse2_CF2 => pulse_CF2_lowgain_S,		
-		pulse_skipped => open,		
-		data_out => pulsedata_out_S,
-		data_out_write => pulsedata_write_S,
-		data_out_almostfull => pulsedata_almostfull,
-		data_out_allowed => pulsedata_allowed);
-pulsedata_out <= pulsedata_out_S;
-pulsedata_write <= pulsedata_write_S;
-
-
-		
-adcnumber_highgain_S <= adcnumber AND x"fe";
-FEE_waveform_to_36bits1: FEE_waveform_to_36bits port map(
-		clock => clock,
-		reset => reset,
-		adcnumber => adcnumber_highgain_S,
-		data_in => data_out_highgain_S,
-		data_in_available => data_out_available_highgain_S,
-		data_in_read => data_out_read_highgain_S,
-		overflow_in => overflow_highgain_S,
-		pileupdata_out => pileupdata1_out_S,
-		pileupdata_write => pileupdata1_write_S,
-		pileupdata_allowed => pileupdata1_allowed_S,
-		pileupdata_almostfull => pileupdata_almostfull,
-		overflow_out => overflow_hg_S,
-		error => error_to36_1_S,
-		testword0 => open);
-
-adcnumber_lowgain_S <= adcnumber OR x"01";
-FEE_waveform_to_36bits2: FEE_waveform_to_36bits port map(
-		clock => clock,
-		reset => reset,
-		adcnumber => adcnumber_lowgain_S,
-		data_in => data_out_lowgain_S,
-		data_in_available => data_out_available_lowgain_S,
-		data_in_read => data_out_read_lowgain_S,
-		overflow_in => overflow_lowgain_S,
-		pileupdata_out => pileupdata2_out_S,
-		pileupdata_write => pileupdata2_write_S,
-		pileupdata_allowed => pileupdata2_allowed_S,
-		pileupdata_almostfull => pileupdata_almostfull,
-		overflow_out => overflow_lg_S,
-		error => error_to36_2_S,
-		testword0 => open);
-overflow <= '1' when (overflow_highgain_S='1') or (overflow_lowgain_S='1') or (overflow_hg_S='1') or (overflow_lg_S='1') else '0';
-
-FEE_wavemux2to1_pileup: FEE_wavemux2to1 port map(
-		clock => clock,
-		reset => reset,
-		data1_in => pileupdata1_out_S,
-		data1_in_write => pileupdata1_write_S,
-		data1_in_available => data_out_available_highgain_S, -- '0',
-		data1_in_allowed => pileupdata1_allowed_S,
-		data2_in => pileupdata2_out_S,
-		data2_in_write => pileupdata2_write_S,
-		data2_in_available => data_out_available_lowgain_S, -- '0',
-		data2_in_allowed => pileupdata2_allowed_S,
-		data_out => pileupdata_out_S,
-		data_out_write => pileupdata_write_S,
-		data_out_available => open,
-		data_out_allowed => pileupdata_allowed,
-		error => error_pileup_S,
-		testword0 => testword2);
-pileupdata_out <= pileupdata_out_S;
-pileupdata_write <= pileupdata_write_S;
+-- Pileup Highgain ------------------------------------------------------------------------------------------------------------\
+
+threshold_pileup_highgain_S <= threshold_highgain;
+baseline_pileup_high: FEE_baselinefollower_eventdetector
+	generic map(
+		ADCBITS => ADCBITS,
+		BASELINE_BWBITS => BASELINE_BWBITS,
+		MWD_WIDTHBITS => 2,
+		MWD_SCALEBITS => MWD_SCALEBITS,
+		MWD2_WIDTHBITS => MWD2_WIDTHBITS,
+		MWD2_SCALEBITS => MWD2_SCALEBITS,
+		MWD_DOUBLEFILTER => MWD_PU_DOUBLEFILTER)
+	port map(
+		clock => clock,
+		reset => reset,
+		enable => enable_S,
+		ADCdata => ADCdata_highgain_S,
+		MWD1_width => MWDpu1_width,
+		MWD1_tau_factor => MWDpu1_tau_factor,
+		MWD2_width => MWDpu2_width,
+		MWD2_tau_factor => MWDpu2_tau_factor,
+		threshold => threshold_pileup_highgain_S,
+		IIRfilterBW => IIRfilterBW,
+		maxabovebaseline => maxabovebaseline,
+		ADC_minus_baseline => pileup_ADC_minus_baseline_highgain0_S,
+		baseline_inhibit => open,
+		pulse_active => pileup_active_highgain_S,
+		pulse_rising => pileup_rising_highgain0_S,
+		max_data => open);
+
+pileup_detect_high: FEE_pulse_detect port map(
+		clock => clock,
+		reset => reset,
+		ADCdata => pileup_ADC_minus_baseline_highgain0_S,
+		pulse_active => pileup_active_highgain_S,
+		minpulselength => "000" & MWDpu1_width,
+		pulse_valid => pileup_valid_highgain_S,
+		singlepulse => pileup_pulse_highgain_S,
+		integral => pileup_integral_highgain_S);
+		
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		pileup_ADC_minus_baseline_highgain_S <= pileup_ADC_minus_baseline_highgain0_S;
+	end if;
+end process;		
+
+extract_pu_high: FEE_extract_pulse
+	generic map(
+		ADCBITS => ADCBITS,
+		CF_DELAYBITS => 2)
+	port map(
+		clock => clock,
+		reset => reset,
+		cf_delay => CFpu_delay,
+		pulse_valid => pileup_valid_highgain_S,
+		pulse_detected => pileup_pulse_highgain_S,
+		pileup_detected => '0',
+		clear_waveform => '0',
+		data_in => pileup_ADC_minus_baseline_highgain_S,
+		integral => pileup_integral_highgain_S,
+		superburstnumber => superburstnumber_S,
+		timestamp => timestampcounter_S,
+		pulse_write => pileupdta_write_highgain_S,
+		pulse_superburst => pileupdta_superburst_highgain_S,
+		pulse_timestamp => pileupdta_timestamp_highgain_S,
+		pulse_skipped => open,
+		pulse_energy => pileupdta_energy_highgain_S,
+		pulse_CF1 => pileupdta_CF1_highgain_S,
+		pulse_CF2 => pileupdta_CF2_highgain_S);
+
+FEE_collect_pileup_pulses_high: FEE_collect_pileup_pulses port map(
+		clock => clock,
+		reset => reset,
+		pulse_active => pulse_active_highgain_S,
+		pileup_valid => pileup_valid_highgain_S,
+		detect_singlepulse => detect_singlepulse_highgain_S,
+		detect_pileuppulse => detect_pileuppulse_highgain_S,
+		detect_clearpulse => detect_clearpulse_highgain_S,
+		detect_purge => detect_purge_highgain_S,
+		data_in_write => pileupdta_write_highgain_S,
+		data_in_superburst => pileupdta_superburst_highgain_S,
+		data_in_timestamp => pileupdta_timestamp_highgain_S,
+		data_in_energy => pileupdta_energy_highgain_S,
+		data_in_CF1 => pileupdta_CF1_highgain_S,
+		data_in_CF2 => pileupdta_CF2_highgain_S,
+		data_out_write => pileup_write_highgain_S,
+		data_out_superburst => pileup_superburst_highgain_S,
+		data_out_timestamp => pileup_timestamp_highgain_S,
+		data_out_energy => pileup_energy_highgain_S,
+		data_out_CF1 => pileup_CF1_highgain_S,
+		data_out_CF2 => pileup_CF2_highgain_S,
+		data_out_skipped => pileup_skipped_highgain_S);
+detect_purge_highgain_S <= '1' when (detect_pileuppulse_lowgain_S='1') or (detect_singlepulse_lowgain_S='1') else '0';
+ 	
+		
+-- Pileup Lowgain ------------------------------------------------------------------------------------------------------------
+threshold_pileup_lowgain_S <= threshold_lowgain;
+baseline_pileup_low: FEE_baselinefollower_eventdetector 
+	generic map(
+		ADCBITS => ADCBITS,
+		BASELINE_BWBITS => BASELINE_BWBITS,
+		MWD_WIDTHBITS => 2,
+		MWD_SCALEBITS => MWD_SCALEBITS,
+		MWD2_WIDTHBITS => MWD2_WIDTHBITS,
+		MWD2_SCALEBITS => MWD2_SCALEBITS,
+		MWD_DOUBLEFILTER => MWD_PU_DOUBLEFILTER)
+	port map(
+		clock => clock,
+		reset => reset,
+		enable => enable_S,
+		ADCdata => ADCdata_lowgain_S,
+		MWD1_width => MWDpu1_width,
+		MWD1_tau_factor => MWDpu1_tau_factor,
+		MWD2_width => MWDpu2_width,
+		MWD2_tau_factor => MWDpu2_tau_factor,
+		threshold => threshold_pileup_lowgain_S,
+		IIRfilterBW => IIRfilterBW,
+		maxabovebaseline => maxabovebaseline,
+		ADC_minus_baseline => pileup_ADC_minus_baseline_lowgain0_S,
+		baseline_inhibit => open,
+		pulse_active => pileup_active_lowgain_S,
+		pulse_rising => pileup_rising_lowgain0_S,
+		max_data => open);
+
+pileup_detect_low: FEE_pulse_detect port map(
+		clock => clock,
+		reset => reset,
+		ADCdata => pileup_ADC_minus_baseline_lowgain0_S,
+		pulse_active => pileup_active_lowgain_S,
+		minpulselength => "000" & MWDpu1_width,
+		pulse_valid => pileup_valid_lowgain_S,
+		singlepulse => pileup_pulse_lowgain_S,
+		integral => pileup_integral_lowgain_S);
+		
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		pileup_ADC_minus_baseline_lowgain_S <= pileup_ADC_minus_baseline_lowgain0_S;
+	end if;
+end process;		
+
+extract_pu_low: FEE_extract_pulse 
+	generic map(
+		ADCBITS => ADCBITS,
+		CF_DELAYBITS => 2)
+	port map(
+		clock => clock,
+		reset => reset,
+		cf_delay => CFpu_delay,
+		pulse_valid => pileup_valid_lowgain_S,
+		pulse_detected => pileup_pulse_lowgain_S,
+		pileup_detected => '0',
+		clear_waveform => '0',
+		data_in => pileup_ADC_minus_baseline_lowgain_S,
+		integral => pileup_integral_lowgain_S,
+		superburstnumber => superburstnumber_S,
+		timestamp => timestampcounter_S,
+		pulse_write => pileupdta_write_lowgain_S,
+		pulse_superburst => pileupdta_superburst_lowgain_S,
+		pulse_timestamp => pileupdta_timestamp_lowgain_S,
+		pulse_skipped => open,
+		pulse_energy => pileupdta_energy_lowgain_S,
+		pulse_CF1 => pileupdta_CF1_lowgain_S,
+		pulse_CF2 => pileupdta_CF2_lowgain_S);
+
+FEE_collect_pileup_pulses_low: FEE_collect_pileup_pulses port map(
+		clock => clock,
+		reset => reset,
+		pulse_active => pulse_active_lowgain_S,
+		pileup_valid => pileup_valid_lowgain_S,
+		detect_singlepulse => detect_singlepulse_lowgain_S,
+		detect_pileuppulse => detect_pileuppulse_lowgain_S,
+		detect_clearpulse => detect_clearpulse_lowgain_S,
+		detect_purge => detect_purge_lowgain_S,
+		data_in_write => pileupdta_write_lowgain_S,
+		data_in_superburst => pileupdta_superburst_lowgain_S,
+		data_in_timestamp => pileupdta_timestamp_lowgain_S,
+		data_in_energy => pileupdta_energy_lowgain_S,
+		data_in_CF1 => pileupdta_CF1_lowgain_S,
+		data_in_CF2 => pileupdta_CF2_lowgain_S,
+		data_out_write => pileup_write_lowgain_S,
+		data_out_superburst => pileup_superburst_lowgain_S,
+		data_out_timestamp => pileup_timestamp_lowgain_S,
+		data_out_energy => pileup_energy_lowgain_S,
+		data_out_CF1 => pileup_CF1_lowgain_S,
+		data_out_CF2 => pileup_CF2_lowgain_S,
+		data_out_skipped => pileup_skipped_lowgain_S);
+detect_purge_lowgain_S <= '1' when (detect_pileuppulse_highgain_S='1') or (detect_singlepulse_highgain_S='1') else '0';
+ 		
+	
+-- Write to output ------------------------------------------------------------------------------------------------------------
+pulsedata_write <= '1' when (pulsedata_write_S='1') and (pulsedata_allowed='1') else '0';
+process(clock)
+begin
+	if rising_edge(clock) then
+		if (pulsedata_write_S='1') and (pulsedata_allowed='0') then
+			pulse_skipped_occurred_S <= '1';
+		end if;
+		if (pulsedata_write_S='1') and (pulsedata_allowed='1') then
+			pulse_skipped_occurred_S <= '0';
+		end if;
+	end if;
+end process;
+		
+-- pulsedata_write_S <= '1' when (enable_waveform='0') 
+	-- and (((pulse_write_highgain_S='1') and (conv_integer(unsigned(pulse_energy_highgain_S))>conv_integer(unsigned(threshold_highgain))))
+		-- or ((pulse_write_lowgain_S='1') and (conv_integer(unsigned(pulse_energy_lowgain_S))>conv_integer(unsigned(threshold_lowgain))))
+		-- or ((pileup_write_highgain_S='1') and (conv_integer(unsigned(pileup_energy_highgain_S))>conv_integer(unsigned(threshold_highgain))))
+		-- or ((pileup_write_lowgain_S='1') and (conv_integer(unsigned(pileup_energy_lowgain_S))>conv_integer(unsigned(threshold_lowgain)))))
+	-- else '0';
+pulsedata_write_S <= '1' when (enable_waveform='0') 
+	and ((pulse_write_highgain_S='1')
+		or (pulse_write_lowgain_S='1')
+		or (pileup_write_highgain_S='1')
+		or (pileup_write_lowgain_S='1'))
+	else '0';
+pulsedata_superburst <= pulsedata_superburst_S;
+pulsedata_superburst_S <= 
+	pulse_superburst_highgain_S when pulse_write_highgain_S='1' else
+	pulse_superburst_lowgain_S when pulse_write_lowgain_S='1' else
+	pileup_superburst_highgain_S when pileup_write_highgain_S='1' else
+	pileup_superburst_lowgain_S when pileup_write_lowgain_S='1'
+;--	else (others => '0');
+pulsedata_timestamp <= pulsedata_timestamp_S;
+pulsedata_timestamp_S <= 
+	pulse_timestamp_highgain_S when pulse_write_highgain_S='1' else
+	pulse_timestamp_lowgain_S when pulse_write_lowgain_S='1' else
+	pileup_timestamp_highgain_S when pileup_write_highgain_S='1' else
+	pileup_timestamp_lowgain_S when pileup_write_lowgain_S='1' 
+;--	else (others => '0');
+pulsedata_energy <=
+	pulse_energy_highgain_S when pulse_write_highgain_S='1' else
+	pulse_energy_lowgain_S when pulse_write_lowgain_S='1' else
+	pileup_energy_highgain_S when pileup_write_highgain_S='1' else
+	pileup_energy_lowgain_S when pileup_write_lowgain_S='1' 
+;--	else (others => '0');
+pulsedata_CFvalbefore <=
+	pulse_CF1_highgain_S when pulse_write_highgain_S='1' else
+	pulse_CF1_lowgain_S when pulse_write_lowgain_S='1' else
+	pileup_CF1_highgain_S when pileup_write_highgain_S='1' else
+	pileup_CF1_lowgain_S when pileup_write_lowgain_S='1' 
+;--	else (others => '0');
+pulsedata_CFvalafter <=
+	pulse_CF2_highgain_S when pulse_write_highgain_S='1' else
+	pulse_CF2_lowgain_S when pulse_write_lowgain_S='1' else
+	pileup_CF2_highgain_S when pileup_write_highgain_S='1' else
+	pileup_CF2_lowgain_S when pileup_write_lowgain_S='1' 
+;--	else (others => '0');
+pulsedata_status0_S <= 
+	STATBYTE_FEEPULSESKIPPED when ((pulse_skipped_highgain_S='1') and (pulse_write_highgain_S='1')) 
+		or ((pulse_skipped_lowgain_S='1') and (pulse_write_lowgain_S='1')) 
+		or ((pileup_skipped_highgain_S='1') and (pileup_write_highgain_S='1'))
+		or ((pileup_skipped_lowgain_S='1') and (pileup_write_lowgain_S='1'))
+		or (pulse_skipped_occurred_S='1') else
+	(others => '0');
+pulsedata_status1_S <= 
+	STATBYTE_PILEUPHIT when (pileup_write_highgain_S='1') or (pileup_write_lowgain_S='1') else
+	(others => '0');
+pulsedata_status <= pulsedata_status0_S or pulsedata_status1_S;
+pulsedata_lowgain <= '1' when (pulse_write_lowgain_S='1') or (pileup_write_lowgain_S='1') else '0';
+
+gen_waves: if NOWAVEFORMS=false generate
+reset_buffer_S <= '1' when (reset='1') or (enable_waveform='0') else '0';
+FEE_pulsewaveform_buffer1: FEE_pulsewaveform_buffer port map(
+		clock => clock,
+		reset => reset_buffer_S,
+		pulse_valid => detect_pulse_valid_highgain_S,
+		pulse_rising => pulse_rising_highgain_S,
+		pulse_detected => detect_singlepulse_highgain_S,
+		pileup_detected => detect_pileuppulse_highgain_S,
+		clear_waveform => detect_clearpulse_highgain_S,
+		data_in => ADC_minus_baseline_highgain_S,
+		superburst => detect_superburst_S(15 downto 0),
+		timestamp => detect_timestamp_S,
+		data_out => wavedata_highgain_S,
+		data_out_read => wavedata_read_highgain_S,
+		data_out_available => wavedata_available_highgain_S,
+		overflow => wave_overflow_highgain_S);
+
+FEE_pulsewaveform_buffer2: FEE_pulsewaveform_buffer port map(
+		clock => clock,
+		reset => reset_buffer_S,
+		pulse_valid => detect_pulse_valid_lowgain_S,
+		pulse_rising => pulse_rising_lowgain_S,
+		pulse_detected => detect_singlepulse_lowgain_S,
+		pileup_detected => detect_pileuppulse_lowgain_S,
+		clear_waveform => detect_clearpulse_lowgain_S,
+		data_in => ADC_minus_baseline_lowgain_S,
+		superburst => detect_superburst_S(15 downto 0),
+		timestamp => detect_timestamp_S,
+		data_out => wavedata_lowgain_S,
+		data_out_read => wavedata_read_lowgain_S,
+		data_out_available => wavedata_available_lowgain_S,
+		overflow => wave_overflow_lowgain_S);		
+		
+FEE_waveform_to_36bits1: FEE_waveform_to_36bits 
+	generic map(
+		ADCNUMBER => ADCNUMBER)
+	port map(
+		clock => clock,
+		reset => reset,
+		data_in => wavedata_highgain_S,
+		data_in_available => wavedata_available_highgain_S,
+		data_in_read => wavedata_read_highgain_S,
+		overflow_in => wave_overflow_highgain_S,
+		wavedata_out => wavedata1_out_S,
+		wavedata_write => wavedata1_write_S,
+		wavedata_inpipe => wavedata1_inpipe_S,
+		wavedata_allowed => wavedata1_allowed_S,
+		wavedata_almostfull => wavedata_almostfull,
+		overflow_out => wave_overflow_hg_S,
+		error => wave_error_to36_1_S);
+
+FEE_waveform_to_36bits2: FEE_waveform_to_36bits 
+	generic map(
+		ADCNUMBER => ADCNUMBER+1)
+	port map(
+		clock => clock,
+		reset => reset,
+		data_in => wavedata_lowgain_S,
+		data_in_available => wavedata_available_lowgain_S,
+		data_in_read => wavedata_read_lowgain_S,
+		overflow_in => wave_overflow_lowgain_S,
+		wavedata_out => wavedata2_out_S,
+		wavedata_write => wavedata2_write_S,
+		wavedata_inpipe => wavedata2_inpipe_S,
+		wavedata_allowed => wavedata2_allowed_S,
+		wavedata_almostfull => wavedata_almostfull,
+		overflow_out => wave_overflow_lg_S,
+		error => wave_error_to36_2_S);
+
+FEE_wavemux2to1_pileup: FEE_wavemux2to1 port map(
+		clock => clock,
+		reset => reset,
+		data1_in => wavedata1_out_S,
+		data1_in_write => wavedata1_write_S,
+		data1_in_available => wavedata1_inpipe_S,
+		data1_in_allowed => wavedata1_allowed_S,
+		data2_in => wavedata2_out_S,
+		data2_in_write => wavedata2_write_S,
+		data2_in_available => wavedata2_inpipe_S,
+		data2_in_allowed => wavedata2_allowed_S,
+		data_out => wavedata_out_S,
+		data_out_write => wavedata_write_S,
+		data_out_available => wavedata_available,
+		data_out_allowed => wavedata_allowed,
+		error => wave_error_S,
+		timeerror => open);
+wavedata_out <= wavedata_out_S;
+wavedata_write <= wavedata_write_S;
+end generate;
+
+
+gen_nowaves: if NOWAVEFORMS=true generate
+	wavedata_out <= (others => '0');
+	wavedata_write <= '0';
+	wavedata_available <= '0';
+	wave_error_S <= '0';
+end generate;
 
 -----------------------------------------------------------------
 -- tests:
-
+
 process(clock)
-variable prev_data_V : std_logic_vector(3 downto 0);
-begin
+variable prev_data_V : std_logic_vector(3 downto 0);
+begin
 	if rising_edge(clock) then
-		testword0_S(35) <= '0';
-		if pileupdata_write_S='1' then
-			case pileupdata_out_S(35 downto 32) is
+		data_error_S <= '0';
+		if wavedata_write_S='1' then
+			case wavedata_out_S(35 downto 32) is
 				when "0000" =>
 					if (prev_data_V/="0100") and (prev_data_V/="0101") then
-						testword0_S(35) <= '1';
+						data_error_S <= '1';
 					end if;
 				when "0001" =>
 					if (prev_data_V/="0000") then
-						testword0_S(35) <= '1';
+						data_error_S <= '1';
 					end if;
 				when "0010" =>
 					if (prev_data_V/="0001") and (prev_data_V/="0010") then
-						testword0_S(35) <= '1';
+						data_error_S <= '1';
 					end if;
 				when "0100" =>
 					if (prev_data_V/="0010") then
-						testword0_S(35) <= '1';
+						data_error_S <= '1';
 					end if;
 				when "0101" =>
 					if (prev_data_V/="0010") then
-						testword0_S(35) <= '1';
+						data_error_S <= '1';
 					end if;
 				when others =>
-					testword0_S(35) <= '1';
+					data_error_S <= '1';
 			end case;
-			prev_data_V := pileupdata_out_S(35 downto 32);
-		end if;
-	end if;
+			prev_data_V := wavedata_out_S(35 downto 32);
+		end if;
+	end if;
 end process;
 
+process(clock)
+variable sb_V : std_logic_vector(30 downto 0) := (others => '0');
+variable tm_V : std_logic_vector(15 downto 0) := (others => '0');
+begin
+	if rising_edge(clock) then
+		pulsetime_error_S <= '0';
+		if (pulsedata_write_S='1') and (pulsedata_allowed='1') then
+			if (pulsedata_superburst_S & pulsedata_timestamp_S) < (sb_V & tm_V) then
+				pulsetime_error_S <= '1';
+			end if;
+			sb_V := pulsedata_superburst_S;
+			tm_V := pulsedata_timestamp_S;
+		end if;
+	end if;
+end process;
 
-testword0 <= testword0_S;
-
-
-
-testword0_S(3 downto 0) <= data_out_highgain_S(35 downto 32);
-testword0_S(4) <= data_out_read_highgain_S;
-testword0_S(5) <= data_out_available_highgain_S;
---testword0_S(6) <= overflow_highgain_S;
-testword0_S(9 downto 6) <= data_out_lowgain_S(35 downto 32);
-testword0_S(10) <= data_out_read_lowgain_S;
-testword0_S(11) <= data_out_available_lowgain_S;
---testword0_S(13) <= overflow_lowgain_S;
-
-testword0_S(15 downto 12) <= pileupdata1_out_S(35 downto 32);
-testword0_S(16) <= pileupdata1_write_S;
-testword0_S(17) <= pileupdata1_allowed_S;
-testword0_S(18) <= pileupdata_almostfull;
---testword0_S(21) <= overflow_hg_S;
-testword0_S(19) <= error_to36_1_S;
-
-testword0_S(23 downto 20) <= pileupdata2_out_S(35 downto 32);
-testword0_S(24) <= pileupdata2_write_S;
-testword0_S(25) <= pileupdata2_allowed_S;
-testword0_S(26) <= pileupdata_almostfull;
---testword0_S(30) <= overflow_lg_S;
-testword0_S(27) <= error_to36_2_S;
-testword0_S(28) <= error_pileup_S;
-
-testword0_S(32 downto 29) <= pileupdata_out_S(35 downto 32);
-testword0_S(33) <= pileupdata_write_S;
-testword0_S(34) <= pileupdata_allowed;
+	
+	
+end Behavioral;
 
 
-
-end Behavioral;
-
-
diff --git a/FEE_ADC32board/FEE_modules/FEE_eventdetector.vhd b/FEE_ADC32board/FEE_modules/FEE_eventdetector.vhd
index 6a0d996..32efcda 100644
--- a/FEE_ADC32board/FEE_modules/FEE_eventdetector.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_eventdetector.vhd
@@ -7,6 +7,7 @@
 -- Modifications: 
 --    16-09-2014: name changed from eventdetector to FEE_eventdetector
 --    10-10-2014: threshold for end of pulse is half the normal threshold
+--    15-04-2016: max_data output clipped to positive values
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -80,7 +81,6 @@ abovetriggerlevel_S <= '1'
 
 process(clock)
 variable counter_V : std_logic_vector(3 downto 0);
---variable below_zero_V : std_logic;
 begin
 	if rising_edge(clock) then
 		if reset='1' then
@@ -89,14 +89,8 @@ begin
 			if abovetriggerlevel_S='1' then
 				freeze_extend_S <= '1';
 				counter_V := (others => '0');
-	--			below_zero_V := '0';
 			elsif counter_V(counter_V'left)='0' then
-	--			if (conv_integer(signed(data_in))>0) and (below_zero_V='0') then
-	--				counter_V := (others => '0');
-	--			else
-	--				below_zero_V := '1';
-					counter_V := counter_V+1;
-	--			end if;
+				counter_V := counter_V+1;
 				freeze_extend_S <= '1';
 			else
 				freeze_extend_S <= '0';
@@ -105,7 +99,7 @@ begin
 	end if;
 end process;
 
-pulsetoolong_S <= counter_S(conv_integer(unsigned(maxabovebaseline)));
+pulsetoolong_S <= counter_S(10); --// counter_S(conv_integer(unsigned(maxabovebaseline)));
 data_below_max_S <= '1' when conv_integer(signed(data_in))<=conv_integer(signed(max_data_S)) else '0';
 pulse_rising <= '1' 
 	when (data_below_max_S='0') 
@@ -123,7 +117,11 @@ begin
 		else
 			if abovetriggerlevel_S='0' then
 				counter_S <= (others => '0');
-				max_data_S <= data_in;
+				if data_in>=0 then
+					max_data_S <= data_in;
+				else
+					max_data_S <= (others => '0');
+				end if;
 				half_threshold_S <= '0';
 			elsif pulsetoolong_S='0' then
 				if (half_threshold_S='0') and (counter_S(2)='1') then
diff --git a/FEE_ADC32board/FEE_modules/FEE_extract_pulse.vhd b/FEE_ADC32board/FEE_modules/FEE_extract_pulse.vhd
index 09f1ac0..8abdc30 100644
--- a/FEE_ADC32board/FEE_modules/FEE_extract_pulse.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_extract_pulse.vhd
@@ -1,5 +1,5 @@
 ----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
+-- Company:       KVI-cart/RUG/Groningen University
 -- Engineer:      Peter Schakel
 -- Create Date:   02-09-2014
 -- Module Name:   FEE_extract_pulse
@@ -7,6 +7,9 @@
 -- Modifications:
 --   10-10-2014   Integral as measurement for the energy instead of maximum
 --   27-10-2014   Constant Fraction with negative or equal instead of negative
+--   27-05-2016   Increase time window to measure valid CF zerocrossing
+--   21-01-2017   Enable shorter pulses, integrate one additional sample at the end of the pulse 
+--   05-04-2017   Shift register optimized for area
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -29,7 +32,6 @@ use IEEE.std_logic_UNSIGNED.ALL;
 --
 -- generics
 --    ADCBITS : Number of bits from the ADC's. The input data is signed and has ADCBITS+1 bits.
---    WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
 --    CF_DELAYBITS : number of bits for the Constant Fraction delay
 --		
 -- inputs
@@ -37,7 +39,6 @@ use IEEE.std_logic_UNSIGNED.ALL;
 --		reset : synchrounous reset
 --		cf_delay : delay (number of ADC samples) for the constant fraction
 --		pulse_valid : input data is valid pulse data
---		pulse_rising : the pulse has not yet reached its maximum
 --		pulse_detected : previous samples are regarded as valid pulse data
 --		pileup_detected : previous samples are regarded as pileup waveform data
 --		clear_waveform : previous samples do not give valid data, clear this data
@@ -66,7 +67,6 @@ use IEEE.std_logic_UNSIGNED.ALL;
 entity FEE_extract_pulse is
 	generic (
 		ADCBITS                 : natural := 14;
-		WAVEFORMBUFFERSIZE      : natural := 10;
 		CF_DELAYBITS            : natural := 8
 		);
    Port (
@@ -74,7 +74,6 @@ entity FEE_extract_pulse is
 		reset                   : in std_logic;
 		cf_delay                : in std_logic_vector(CF_DELAYBITS-1 downto 0);
 		pulse_valid             : in std_logic;
-		pulse_rising            : in std_logic;
 		pulse_detected          : in std_logic;
 		pileup_detected         : in std_logic;
 		clear_waveform          : in std_logic;
@@ -83,7 +82,7 @@ entity FEE_extract_pulse is
 		superburstnumber        : in std_logic_vector(30 downto 0);
 		timestamp               : in std_logic_vector(15 downto 0);
 		pulse_write             : out std_logic;
-		pulse_superburst        : out std_logic_vector(15 downto 0);
+		pulse_superburst        : out std_logic_vector(30 downto 0);
 		pulse_timestamp         : out std_logic_vector(15 downto 0);
 		pulse_skipped           : out std_logic;
 		pulse_energy            : out std_logic_vector(15 downto 0);
@@ -96,7 +95,7 @@ architecture Behavioral of FEE_extract_pulse is
 
 component shift_register is
 	generic (
-		width                   : natural := ADCBITS+1; -- signed signal 
+		width                   : natural := ADCBITS+1;
 		depthbits               : natural := CF_DELAYBITS
 		);
     port (
@@ -107,23 +106,36 @@ component shift_register is
 		depth                   : in std_logic_vector((depthbits-1) downto 0);
 		data_out                : out  std_logic_vector((width-1) downto 0));
 end component;
-
 
-constant zeros                   : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
+component shift_register_small is
+	generic (
+		width                   : natural := ADCBITS+1;
+		depthbits               : natural := CF_DELAYBITS
+		);
+    port (
+		clock                   : in  std_logic; 
+		data_in                 : in std_logic_vector((width-1) downto 0); 
+		depth                   : in std_logic_vector((depthbits-1) downto 0);
+		data_out                : out  std_logic_vector((width-1) downto 0));
+end component;
+
 
 signal pulse_write_S             : std_logic;
-signal pulse_superburst_S        : std_logic_vector(15 downto 0);
-signal pulse_timestamp_S         : std_logic_vector(15 downto 0);
+signal pulse_superburst_S        : std_logic_vector(30 downto 0);
+signal pulse_timestamp_S         : std_logic_vector(15 downto 0);
+signal pulse_energy_S            : std_logic_vector(15 downto 0);
 signal pulse_max_S               : std_logic_vector(ADCBITS downto 0); 
 signal pulse_CF1_S               : std_logic_vector(15 downto 0);
 signal pulse_CF2_S               : std_logic_vector(15 downto 0);
+signal pulse_detected_S          : std_logic; 
 
 signal prev_setmax_S             : std_logic; -- maximum set in previous clock cycle
 signal prev_pulse_valid_S        : std_logic; -- valid signal in previous clock cycle
-signal after_max_counter_S       : std_logic_vector(CF_DELAYBITS downto 0) := (others => '0');
+signal after_max_counter_S       : std_logic_vector(CF_DELAYBITS+1 downto 0) := (others => '0');
 
 signal pulse_skipped_S           : std_logic := '0'; 
-signal CF_available_S            : std_logic := '0'; 
+signal CF_available0_S           : std_logic := '0'; 
+signal CF_available_S            : std_logic; 
 
 signal data_delayed_S            : std_logic_vector(ADCBITS downto 0) := (others => '0');
 signal data_delayedx4_S          : std_logic_vector(ADCBITS+2 downto 0) := (others => '0');
@@ -131,37 +143,55 @@ signal cf_signal_S               : std_logic_vector(ADCBITS+3 downto 0) := (othe
 signal prev_cf_signal_S          : std_logic_vector(ADCBITS+3 downto 0) := (others => '0');
 signal cf_negorzero_S            : std_logic;
 signal prev_cf_negorzero_S       : std_logic;
-signal enable_CF_S               : std_logic;
+signal enable_CF_S               : std_logic;
+signal enable1_CF_S              : std_logic;
+
+attribute mark_debug : string;
+
+
+-- attribute mark_debug of pulse_valid : signal is "true";
+-- attribute mark_debug of pulse_detected : signal is "true";
+-- attribute mark_debug of pulse_detected_S : signal is "true";
+-- attribute mark_debug of pulse_write_S : signal is "true";
+-- attribute mark_debug of CF_available0_S : signal is "true";
+-- attribute mark_debug of CF_available_S : signal is "true";
+-- attribute mark_debug of prev_setmax_S : signal is "true";
+-- attribute mark_debug of enable_CF_S : signal is "true";
+-- attribute mark_debug of after_max_counter_S : signal is "true";
+-- attribute mark_debug of cf_negorzero_S : signal is "true";
+-- attribute mark_debug of prev_cf_negorzero_S : signal is "true";
+-- attribute mark_debug of cf_signal_S : signal is "true";
+-- attribute mark_debug of pulse_skipped_S : signal is "true";
+
 
 begin
 
 pulse_write <= pulse_write_S;
 pulse_superburst <= pulse_superburst_S;
-pulse_timestamp <= pulse_timestamp_S;
-pulse_skipped <= pulse_skipped_S;
-pulse_energy <= integral;
+pulse_timestamp <= pulse_timestamp_S;
+pulse_energy <= pulse_energy_S;
 pulse_CF1 <= pulse_CF1_S;
 pulse_CF2 <= pulse_CF2_S;
-
-pulse_write_S <= pulse_detected when CF_available_S='1' else '0';
-
-check_skipped: process(clock)
-variable holdcounter_V : integer range 0 to 3 := 3; -- keep value at the output for 4 clock cycles
-begin
-	if rising_edge(clock) then
-		if (pulse_detected='1') and (CF_available_S='0') then
-			pulse_skipped_S <= '1';
-		elsif pulse_detected='1' then
-			holdcounter_V := 0;
-		elsif holdcounter_V<3 then
-			holdcounter_V := holdcounter_V+1;
-			if holdcounter_V=2 then
-				pulse_skipped_S <= '0';
-			end if;
-		end if;
-	end if;
-end process;
-
+process(clock)
+begin
+	if rising_edge(clock) then
+		pulse_write_S <= '0';
+		if pulse_detected='1' then
+--			pulse_energy_S <= integral;
+		end if;
+		if pulse_detected_S='1' then
+			pulse_energy_S <= integral;
+			if CF_available_S='1' then
+				pulse_skipped <= pulse_skipped_S;
+				pulse_write_S <= '1';
+				pulse_skipped_S <= '0';
+			else
+				pulse_skipped_S <= '1';
+			end if;
+		end if;
+		pulse_detected_S <= pulse_detected;
+	end if;
+end process;	
 
 get_maxima: process(clock)
 begin
@@ -182,40 +212,37 @@ end process;
 after_max: process(clock)
 begin
 	if rising_edge(clock) then
-		if reset='1' then
-			enable_CF_S <= '0';
-		else	
-			if (pulse_valid='0') then
-				enable_CF_S <= '0';
+		if (pulse_valid='0') then
+			enable1_CF_S <= '0';
+		else
+			if prev_pulse_valid_S='0' then
+				enable1_CF_S <= '1';
 			else
-				if prev_pulse_valid_S='0' then
-					enable_CF_S <= '1';
+				if prev_setmax_S='1' then
+					after_max_counter_S <= (others => '0');
 				else
-					if prev_setmax_S='1' then
-						after_max_counter_S <= (others => '0');
-					else
-						if after_max_counter_S(CF_DELAYBITS-1 downto 0) = cf_delay then
-							enable_CF_S <= '0';
-						end if;
-						if after_max_counter_S(CF_DELAYBITS)='0' then
-							after_max_counter_S <= after_max_counter_S+1;
-						end if;
+					if after_max_counter_S(CF_DELAYBITS downto 0) = cf_delay & '0' then
+						enable1_CF_S <= '0';
+					end if;
+					if after_max_counter_S(after_max_counter_S'left)='0' then
+						after_max_counter_S <= after_max_counter_S+1;
 					end if;
 				end if;
 			end if;
 		end if;
 	end if;
 end process;
+enable_CF_S <= '1' when (enable1_CF_S='1') or ((pulse_valid='1') and (prev_pulse_valid_S='0')) or (pulse_detected='1') or (pulse_detected_S='1') else '0';   
 
-shiftregister1: shift_register 
+shiftregister1: shift_register_small 
 	generic map(
 		width => ADCBITS+1, -- signed signal 
 		depthbits => CF_DELAYBITS
 		)
 	port map(
 		clock => clock,
-		reset => reset,
-		hold => '0',
+--		reset => '0', 
+--		hold => '0',
 		data_in => data_in,
 		depth => cf_delay,
 		data_out => data_delayed_S);
@@ -231,33 +258,29 @@ variable pulse_CF1_V : integer range -2**(ADCBITS+3) to 2**(ADCBITS+3)-1;
 variable pulse_CF2_V : integer range -2**(ADCBITS+3) to 2**(ADCBITS+3)-1;
 begin
 	if (rising_edge(clock)) then
-		if reset='1' then
-			CF_available_S <= '0';
-		else
-			if (pulse_valid='0') and (pulse_detected='0') then
-				CF_available_S <= '0';
-			else
-				if prev_cf_negorzero_S='1' then
-					if cf_negorzero_S='0' then
-						if enable_CF_S='1' then
-							pulse_CF1_V := -conv_integer(signed(prev_cf_signal_S));
-							if pulse_CF1_V>65535 then
-								pulse_CF1_S <= x"ffff";
-							else
-								pulse_CF1_S <= conv_std_logic_vector(pulse_CF1_V,16);
-							end if;
-							pulse_CF2_V := conv_integer(signed(cf_signal_S));
-							if pulse_CF2_V>65535 then
-								pulse_CF2_S <= x"ffff";
-							else
-								pulse_CF2_S <= conv_std_logic_vector(pulse_CF2_V,16);
-							end if;
-							pulse_superburst_S <= superburstnumber(15 downto 0);
-							pulse_timestamp_S <= timestamp;
-							CF_available_S <= '1';
+		if (pulse_valid='0') and (pulse_detected='0') and (pulse_detected_S='0') then
+			CF_available0_S <= '0';
+		else
+			if prev_cf_negorzero_S='1' then
+				if cf_negorzero_S='0' then
+					if enable_CF_S='1' then
+						pulse_CF1_V := -conv_integer(signed(prev_cf_signal_S));
+						if pulse_CF1_V>65535 then
+							pulse_CF1_S <= x"ffff";
+						else
+							pulse_CF1_S <= conv_std_logic_vector(pulse_CF1_V,16);
+						end if;
+						pulse_CF2_V := conv_integer(signed(cf_signal_S));
+						if pulse_CF2_V>65535 then
+							pulse_CF2_S <= x"ffff";
+						else
+							pulse_CF2_S <= conv_std_logic_vector(pulse_CF2_V,16);
 						end if;
-					else
+						pulse_superburst_S <= superburstnumber;
+						pulse_timestamp_S <= timestamp;
+						CF_available0_S <= '1';
 					end if;
+				else
 				end if;
 			end if;
 		end if;
@@ -265,7 +288,10 @@ begin
 		prev_cf_signal_S <= cf_signal_S;
 	end if;
 end process;
-
+CF_available_S <= '1' when (CF_available0_S='1') 
+	or (((pulse_valid='1') or (pulse_detected_S='1')) 
+		and ((prev_cf_negorzero_S='1') and (cf_negorzero_S='0') and (enable_CF_S='1')))
+	else '0';
 
 end Behavioral;
 
diff --git a/FEE_ADC32board/FEE_modules/FEE_fifo32to8_SODA.vhd b/FEE_ADC32board/FEE_modules/FEE_fifo32to8_SODA.vhd
index ea4cbb8..fca0d7e 100644
--- a/FEE_ADC32board/FEE_modules/FEE_fifo32to8_SODA.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_fifo32to8_SODA.vhd
@@ -79,30 +79,29 @@ signal fifo_dataout_S           : std_logic_vector(31 downto 0);
 signal fifo_databuf_S           : std_logic_vector(31 downto 0);
 signal data_out_S               : std_logic_vector(7 downto 0);
 signal char_is_k_S              : std_logic;
-signal fifo_empty_S             : std_logic;
-signal prev_fifo_empty_S        : std_logic;
+signal fifo_empty_S             : std_logic;
 
 signal fifo_buffilled_S         : std_logic := '0';
-signal fifo_read_after1clk_S    : std_logic := '0';
+signal fifo_read_after1clk_S    : std_logic := '0';
 signal TX_DLM_S                 : std_logic;
-signal TX_DLM_WORD_S            : std_logic_vector(7 downto 0);
-signal bytecounter_S            : integer range 0 to 3 := 0;
+signal TX_DLM_WORD_S            : std_logic_vector(7 downto 0);
+signal bytecounter_S            : integer range 0 to 3 := 0;
 signal write_data_S             : std_logic;
 signal lastbytefilled_S         : std_logic;
-signal lastbyte_S               : std_logic_vector(7 downto 0);
-
+signal lastbyte_S               : std_logic_vector(7 downto 0);
+
 
 begin
-
+
 process (read_clock)
 begin
-	if rising_edge(read_clock) then
-		data_out <= data_out_S;
+	if rising_edge(read_clock) then
+		data_out <= data_out_S;
 		char_is_k <= char_is_k_S;
 	end if;
-end process;
-
-	
+end process;
+
+	
 fifo: async_fifo_512x32 port map(
 		rst => reset,
 		wr_clk => write_clock,
@@ -116,76 +115,75 @@ fifo: async_fifo_512x32 port map(
 
 fifo_read_S <= '1' when (fifo_empty_S='0') and (TX_DLM='0') and (fifo_read_after1clk_S='0') and (lastbytefilled_S='0')
 		and (((bytecounter_S=0)  and (fifo_buffilled_S='0')) or ((bytecounter_S=3) and (fifo_buffilled_S='0')))
-	else '0';
+	else '0';
 	
-data_out_S <= 
+data_out_S <= 
 	KCHARSODA when TX_DLM='1' else
-	TX_DLM_WORD_S when (TX_DLM_S='1') else
-	KCHAR285 when (write_data_S='0') else
-	lastbyte_S when (lastbytefilled_S='1') else
-	fifo_dataout_S(31 downto 24) when (fifo_read_after1clk_S='1') else
-	fifo_databuf_S((3-bytecounter_S)*8+7 downto (3-bytecounter_S)*8);
-	
+	TX_DLM_WORD_S when (TX_DLM_S='1') else
+	KCHAR285 when (write_data_S='0') else
+	lastbyte_S when (lastbytefilled_S='1') else
+	fifo_dataout_S(31 downto 24) when (fifo_read_after1clk_S='1') else
+	fifo_databuf_S((3-bytecounter_S)*8+7 downto (3-bytecounter_S)*8);
+	
 char_is_k_S <=
 	'1' when TX_DLM='1' else
-	'0' when (TX_DLM_S='1') else
-	'1' when (write_data_S='0') else
-	'0' when fifo_read_after1clk_S='1' else 
+	'0' when (TX_DLM_S='1') else
+	'1' when (write_data_S='0') else
+	'0' when fifo_read_after1clk_S='1' else 
 	'0';
-
-write_data_S <= '1' when ((TX_DLM='0') and (TX_DLM_S='0')) and 
-	((fifo_read_after1clk_S='1') or (bytecounter_S/=0) or (fifo_buffilled_S='1') or (lastbytefilled_S='1')) else '0';
-
+
+write_data_S <= '1' when ((TX_DLM='0') and (TX_DLM_S='0')) and 
+	((fifo_read_after1clk_S='1') or (bytecounter_S/=0) or (fifo_buffilled_S='1') or (lastbytefilled_S='1')) else '0';
+
 tx_process : process (read_clock)
 begin
 	if rising_edge(read_clock) then
 		if reset='1' then
 			fifo_read_after1clk_S <= '0';
-			TX_DLM_S <= '0';
-			lastbytefilled_S <= '0';
+			TX_DLM_S <= '0';
+			lastbytefilled_S <= '0';
 			bytecounter_S <= 0;
-		else
-			TX_DLM_S <= TX_DLM;
-			if TX_DLM='1' then
-				TX_DLM_WORD_S <= TX_DLM_WORD;
-			end if;
+		else
+			TX_DLM_S <= TX_DLM;
+			if TX_DLM='1' then
+				TX_DLM_WORD_S <= TX_DLM_WORD;
+			end if;
 			fifo_read_after1clk_S <= fifo_read_S;
-			prev_fifo_empty_S <= fifo_empty_S;
-			if not ((TX_DLM='1') or (TX_DLM_S='1') or (write_data_S='0')) then
-				lastbytefilled_S <= '0';
-			end if;
-			if (fifo_read_after1clk_S='1') then
-				if (TX_DLM='1') and (fifo_buffilled_S='0') and (bytecounter_S=3) then 
-					lastbytefilled_S <= '1';
-					lastbyte_S <= fifo_databuf_S(7 downto 0);
-				end if;
-				fifo_databuf_S <= fifo_dataout_S;
-				fifo_buffilled_S <= '1';
-			end if;	
-			if (TX_DLM='1') or (TX_DLM_S='1') then
-			elsif lastbytefilled_S='1' then
-				bytecounter_S <= 0;
-			else
-				case bytecounter_S is
-					when 0 =>
-						if (fifo_buffilled_S='1') or (fifo_read_after1clk_S='1') then
-							fifo_buffilled_S <= '1';
-							bytecounter_S <= 1;
-						end if;
-					when 1 =>
-						fifo_buffilled_S <= '1';
-						bytecounter_S <= 2;
-					when 2 =>
-						fifo_buffilled_S <= '0';
-						bytecounter_S <= 3;
-					when 3 =>
-						fifo_buffilled_S <= '0';
-						bytecounter_S <= 0;
-					when others =>
-						fifo_buffilled_S <= '0';
-						bytecounter_S <= 0;
-				end case;
-			end if;
+			if not ((TX_DLM='1') or (TX_DLM_S='1') or (write_data_S='0')) then
+				lastbytefilled_S <= '0';
+			end if;
+			if (TX_DLM='1') and (fifo_buffilled_S='0') and (bytecounter_S=3) then 
+				lastbytefilled_S <= '1';
+				lastbyte_S <= fifo_databuf_S(7 downto 0);
+			end if;
+			if (fifo_read_after1clk_S='1') then
+				fifo_databuf_S <= fifo_dataout_S;
+				fifo_buffilled_S <= '1';
+			end if;	
+			if (TX_DLM='1') or (TX_DLM_S='1') then
+			elsif lastbytefilled_S='1' then
+				bytecounter_S <= 0;
+			else
+				case bytecounter_S is
+					when 0 =>
+						if (fifo_buffilled_S='1') or (fifo_read_after1clk_S='1') then
+							fifo_buffilled_S <= '1';
+							bytecounter_S <= 1;
+						end if;
+					when 1 =>
+						fifo_buffilled_S <= '1';
+						bytecounter_S <= 2;
+					when 2 =>
+						fifo_buffilled_S <= '0';
+						bytecounter_S <= 3;
+					when 3 =>
+						fifo_buffilled_S <= '0';
+						bytecounter_S <= 0;
+					when others =>
+						fifo_buffilled_S <= '0';
+						bytecounter_S <= 0;
+				end case;
+			end if;
 		end if;
 	end if;
 end process;
diff --git a/FEE_ADC32board/FEE_modules/FEE_fiforead2write.vhd b/FEE_ADC32board/FEE_modules/FEE_fiforead2write.vhd
new file mode 100644
index 0000000..2c8a2a5
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_fiforead2write.vhd
@@ -0,0 +1,138 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   14-03-2016
+-- Module Name:   FEE_fiforead2write
+-- Description:   Converts reading from fifo to write
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+----------------------------------------------------------------------------------
+-- FEE_fiforead2write
+-- Converts reading from fifo to write
+--
+--
+--
+-- Library
+--
+-- 
+-- Generics
+--     BITS : number of bits at input and output
+--
+-- Inputs:
+--     clock : clock input for 64 bits data
+--     data_in : input data
+--     data_in_empty : empty from connected fifo
+--     data_out_allowed : writing of input data is allowed
+-- 
+-- Outputs:
+--     data_in_read : read data from fifo
+--     data_out : output data
+--     data_out_write : write signal for output data
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity FEE_fiforead2write is
+	generic(
+		BITS                    : integer := 32
+	);
+	port(
+		clock                   : in std_logic; 
+		data_in                 : in std_logic_vector(BITS-1 downto 0);
+		data_in_empty           : in std_logic;
+		data_in_read            : out std_logic;
+		data_out                : out std_logic_vector(BITS-1 downto 0);
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic
+	); 
+end FEE_fiforead2write;
+
+
+
+architecture behaviour of FEE_fiforead2write is
+
+signal data_in_read_S          : std_logic;
+signal data_in_read_aftr1clk_S : std_logic := '0';
+signal data_out_filled_S       : std_logic := '0';
+signal data_out_trywrite_S     : std_logic := '0';
+signal data_out_buf_S          : std_logic_vector(BITS-1 downto 0);
+signal data_out_S              : std_logic_vector(BITS-1 downto 0);
+
+
+begin
+
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when (data_in_empty='0') and (data_out_allowed='1') and (data_out_filled_S='0') else '0';
+out_process: process(clock)
+begin
+	if rising_edge(clock) then
+		data_out_trywrite_S <= '0';
+		data_in_read_aftr1clk_S <= data_in_read_S;
+		if data_in_read_aftr1clk_S='1' then 
+			if data_out_allowed='1' then
+				if (data_out_trywrite_S='1') then
+					if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+						data_out_S <= data_out_buf_S;
+						data_out_buf_S <= data_in;
+						data_out_trywrite_S <= '1'; -- write previous data
+						data_out_filled_S <= '1';
+					else -- write new data
+						data_out_S <= data_in;
+						data_out_trywrite_S <= '1';
+						data_out_filled_S <= '0';
+					end if;
+				else -- data_out_trywrite_S='0'
+					if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+						data_out_S <= data_out_buf_S;
+						data_out_buf_S <= data_in;
+						data_out_trywrite_S <= '1'; -- write previous data
+						data_out_filled_S <= '1';
+					else -- -- data_out_filled_S='0',  write new data
+						data_out_S <= data_in;
+						data_out_trywrite_S <= '1';
+						data_out_filled_S <= '0';
+					end if;
+				end if;
+			else -- data_out_allowed='0'
+				if data_out_trywrite_S='1' then -- try again, save new data
+					data_out_buf_S <= data_in;
+					data_out_trywrite_S <= '1';
+					data_out_filled_S <= '1';
+					if data_out_filled_S='1' then
+						--error
+					end if;
+				else -- data_out_trywrite_S='0'
+					if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+						data_out_S <= data_out_buf_S;
+						data_out_buf_S <= data_in;
+						data_out_trywrite_S <= '1'; -- write previous data
+						data_out_filled_S <= '1';
+					else -- data_out_filled_S='0'
+						data_out_S <= data_in;
+						data_out_trywrite_S <= '1';
+						data_out_filled_S <= '0';
+					end if;
+				end if;
+			end if;
+		elsif (data_out_allowed='0') and (data_out_trywrite_S='1') then -- try again
+			data_out_trywrite_S <= '1';
+		elsif data_out_filled_S='1' then
+			if data_out_allowed='1' then
+				data_out_S <= data_out_buf_S;
+				data_out_trywrite_S <= '1';
+				data_out_filled_S <= '0';
+			end if;
+		else
+		end if;
+	end if;
+end process;
+data_out_write <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+data_out <= data_out_S;
+
+end behaviour;
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_gtxWrapper_Virtex6.vhd b/FEE_ADC32board/FEE_modules/FEE_gtxWrapper_Virtex6.vhd
index a9883ef..553a16e 100644
--- a/FEE_ADC32board/FEE_modules/FEE_gtxWrapper_Virtex6.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_gtxWrapper_Virtex6.vhd
@@ -219,7 +219,6 @@ signal rxData_S            : std_logic_vector(7 downto 0);
 signal rxReset_S           : std_logic :='0';
 signal rxRecClk_S          : std_logic :='0';
 signal rxRecClk_buf_S      : std_logic :='0';
-signal rxRecClk_double_S   : std_logic :='0';
 
 signal rxLocked_S          : std_logic;
 signal txLocked_S          : std_logic;
@@ -252,7 +251,7 @@ signal disable_GTX_reset_S : std_logic :='0';
 
     -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
     signal  gtx0_txdlyaligndisable_i        : std_logic;
-    signal  gtx0_txdlyalignmonenb_i         : std_logic;
+    signal  gtx0_txdlyalignmonenb_i         : std_logic := '0';
     signal  gtx0_txdlyalignmonitor_i        : std_logic_vector(7 downto 0);
     signal  gtx0_txdlyalignreset_i          : std_logic;
     signal  gtx0_txenpmaphasealign_i        : std_logic;
@@ -281,7 +280,9 @@ begin
 --		O => rxRecClk_buf_S);
 		
 rxrecclk_bufr1_i : BUFR
-	generic map ( BUFR_DIVIDE => "BYPASS" )
+	generic map ( 
+		BUFR_DIVIDE => "BYPASS",
+		SIM_DEVICE => "VIRTEX6")
 	port map (
 		CE => '1',
 		CLR => '0',
@@ -393,8 +394,6 @@ rxPLLwrapper_reset_S <= '1' when (rxResetBitLock_pulse_S='1') else '0';
 --			I => txOutClk_S);
 txLocked_S <= '1' when (txResetdone_S='1') and (gtx0_tx_sync_done_i='1') else '0';			
 				
-rxRecClk_double_S <= '0';
-		
 process(rxRecClk_buf_S)
 begin
 	if rising_edge(rxRecClk_buf_S) then
diff --git a/FEE_ADC32board/FEE_modules/FEE_measure_frequency.vhd b/FEE_ADC32board/FEE_modules/FEE_measure_frequency.vhd
index c024f53..f1aa67c 100644
--- a/FEE_ADC32board/FEE_modules/FEE_measure_frequency.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_measure_frequency.vhd
@@ -50,14 +50,16 @@ end FEE_measure_frequency;
 architecture Behavioral of FEE_measure_frequency is
 
 signal counter_S                  : std_logic_vector(31 downto 0) := (others => '0');
+signal frequency_S                : std_logic_vector(31 downto 0) := (others => '0');
 
 begin
-
+
+frequency <= frequency_S;
 process(clock)
 begin
 	if (rising_edge(clock)) then 
 		if onesecondpulse='1' then
-			frequency <= counter_S;
+			frequency_S <= counter_S;
 			if pulse='1' then
 				counter_S <= x"00000001";
 			else
diff --git a/FEE_ADC32board/FEE_modules/FEE_mux2to1.vhd b/FEE_ADC32board/FEE_modules/FEE_mux2to1.vhd
index 5b7c216..d52bd75 100644
--- a/FEE_ADC32board/FEE_modules/FEE_mux2to1.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_mux2to1.vhd
@@ -1,11 +1,14 @@
 ----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
+-- Company:       KVI-cart/RUG/Groningen University
 -- Engineer:      Peter Schakel
 -- Create Date:   05-03-2012
 -- Module Name:   FEE_mux2to1
 -- Description:   compare timestamp of 36bits data pass on first
 -- Modifications:
 --    16-10-2014: 3*36bits words; bits 35 and 34 as indenticication
+--    25-09-2015: compare bug fixed at FFFF->0000 superburst change
+--    12-10-2015: bug fixed : pulse skipped bit in wrong channel 
+--    22-02-2017: rewritten to parallel data instead of 36bits words
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -16,43 +19,56 @@ use IEEE.std_logic_UNSIGNED.ALL;
 
 ------------------------------------------------------------------------------------------------------
 -- FEE_mux2to1
---	   Compare timestamp of 36bits data and pass on first
---    If data from only one is available then this is passed on directly
---    The 36-bits data contains packets with 3 words:
---        	bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
---        	bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
---        	bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+--    Compare timestamp of two hits and pass data on in right order.
+--    If data from only one is available then this data is passed on directly
+--    The data consists of the members of a hit :
+--        channel : number of the ADC
+--        statusbyte : 8 bits with status
+--        energy : energy of a hit
+--        CFvalbefore : Constant Fraction method : sample before zero crossing
+--        CFvalafter : Constant Fraction method : sample after zero crossing
+--        timestamp : integer part of the timestamp of a hit within the superburst, unit: sample-clock cycles
+--        superburst : number of the superburst to which the hit belongs
 --
 --
 -- generics
 --		
 -- inputs
---     clock : ADC sampling clock 
---     reset : synchrounous reset
---     data1_in : data from first 36-bits input, 3 words:
---        	bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
---        	bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
---        	bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
---     data1_in_write : write signal for data1_in
---     data1_in_available : more data available: wait with timestamp check until the timestamp is read
---     data2_in : data from second 36-bits input, 3 words:
---        	bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
---        	bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
---        	bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
---     data2_in_write : write signal for data2_in
---     data2_in_available : more data available: wait with timestamp check until the timestamp is read
---     data_out_allowed : writing of resulting data allowed
+--    clock : ADC sampling clock 
+--    reset : synchronous reset
+--    channel1 : data input 1 : adc channel
+--    statusbyte1 : data input 1 : status
+--    energy1 : data input 1 : pulse energy
+--    CFvalbefore1 : data input 1 : Constant Fraction method : sample before zero crossing
+--    CFvalafter1 : data input 1 : Constant Fraction method : sample after zero crossing
+--    timestamp1 : data input 1 : time
+--    superburst1 : data input 1 : superburst number
+--    data1_in_write : write signal for data1_in
+--    data1_in_inpipe : more data available: wait with timestamp check until the timestamp is read
+--    channel2 : data input 2 : adc channel
+--    statusbyte2 : data input 2 : status
+--    energy2 : data input 2 : pulse energy
+--    CFvalbefore2 : data input 2 : Constant Fraction method : sample before zero crossing
+--    CFvalafter2 : data input 2 : Constant Fraction method : sample after zero crossing
+--    timestamp2 : data input 2 : time
+--    superburst2 : data input 2 : superburst number
+--    data2_in_write : write signal for data2_in
+--    data2_in_inpipe : more data available: wait with timestamp check until the timestamp is read
+--    data_out_allowed : writing of resulting data allowed
 --			  
 -- outputs
---     data1_in_allowed : signal to allow data input 1
---     data2_in_allowed : signal to allow data input 2
---     data_out : 36-bits data with valid pulse waveform, 3 words:
---        	bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
---        	bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
---        	bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
---     data_out_write : write signal for 36-bits output data
---     data_out_available : data available: in this module or at the input
---     error : error in data bits 35..32
+--    data1_in_allowed : signal to allow data input 1
+--    data2_in_allowed : signal to allow data input 2
+--    channel : data output : adc channel
+--    statusbyte : data output : status
+--    energy : data output : pulse energy
+--    CFvalbefore : data output : Constant Fraction method : sample before zero crossing
+--    CFvalafter : data output : Constant Fraction method : sample after zero crossing
+--    timestamp : data output : time
+--    superburst : data output : superburst number
+--    data_out_write : write signal for 36-bits output data
+--    data_out_inpipe : data available: in this module or at the input
+--    error : error in data bits 35..32
 --
 -- components
 --
@@ -61,283 +77,215 @@ use IEEE.std_logic_UNSIGNED.ALL;
 
 
 entity FEE_mux2to1 is
-    Port (
+   port (
 		clock                   : in std_logic;
 		reset                   : in std_logic;
-		data1_in                : in std_logic_vector(35 downto 0); 
+		channel1                : in std_logic_vector(7 downto 0);
+		statusbyte1             : in std_logic_vector(7 downto 0);
+		energy1                 : in std_logic_vector(15 downto 0);
+		CFvalbefore1            : in std_logic_vector(15 downto 0);
+		CFvalafter1             : in std_logic_vector(15 downto 0);
+		timestamp1              : in std_logic_vector(15 downto 0);
+		superburst1             : in std_logic_vector(30 downto 0);
 		data1_in_write          : in std_logic;
-		data1_in_available      : in std_logic;
+		data1_in_inpipe         : in std_logic;
 		data1_in_allowed        : out std_logic;
-		data2_in                : in std_logic_vector(35 downto 0); 
+		channel2                : in std_logic_vector(7 downto 0);
+		statusbyte2             : in std_logic_vector(7 downto 0);
+		energy2                 : in std_logic_vector(15 downto 0);
+		CFvalbefore2            : in std_logic_vector(15 downto 0);
+		CFvalafter2             : in std_logic_vector(15 downto 0);
+		timestamp2              : in std_logic_vector(15 downto 0);
+		superburst2             : in std_logic_vector(30 downto 0);
 		data2_in_write          : in std_logic;
-		data2_in_available      : in std_logic;
+		data2_in_inpipe         : in std_logic;
 		data2_in_allowed        : out std_logic;
-		data_out                : out std_logic_vector(35 downto 0);
+		channel                 : out std_logic_vector(7 downto 0);
+		statusbyte              : out std_logic_vector(7 downto 0);
+		energy                  : out std_logic_vector(15 downto 0);
+		CFvalbefore             : out std_logic_vector(15 downto 0);
+		CFvalafter              : out std_logic_vector(15 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0);
+		superburst              : out std_logic_vector(30 downto 0);
 		data_out_write          : out std_logic;
-		data_out_available      : out std_logic;
+		data_out_inpipe         : out std_logic;
 		data_out_allowed        : in std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
+		error                   : out std_logic
 		);
 end FEE_mux2to1;
 
 
 architecture Behavioral of FEE_mux2to1 is
 
-constant TIMEOUTBITS             : integer := 6;
-signal timeout_counter_S         : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
-
-signal error_S                   : std_logic := '0';
-signal read_pulse1_S             : std_logic := '0';
-signal read_pulse2_S             : std_logic := '0';
-signal data1_in_allowed_S        : std_logic := '0';
-signal data2_in_allowed_S        : std_logic := '0';
-signal data1_in_write_S          : std_logic := '0';
-signal data2_in_write_S          : std_logic := '0';
-signal data_out_trywrite_S       : std_logic := '0';
-signal data_out_write_S          : std_logic := '0';
-signal data_out_available_S      : std_logic := '0';
-signal data_out_S                : std_logic_vector(35 downto 0) := (others => '0');
+attribute syn_keep     : boolean;
+attribute syn_preserve : boolean;
+
+constant TIMEOUTBITS             : integer := 12;
+--//signal timeout_counter_S         : std_logic_vector(TIMEOUTBITS downto 0) := (others => '0');
+signal clear_timeout_counter_S   : std_logic := '0';
+signal inc_timeout_counter_S     : std_logic := '0';
+
+
+		
+signal error_S                   : std_logic;
+signal data1_in_write_S          : std_logic;
+signal data2_in_write_S          : std_logic;
+signal data_out_write_S          : std_logic;
+signal data1_in_inpipe_S         : std_logic;
+signal data2_in_inpipe_S         : std_logic;
+signal data_out_inpipe_S         : std_logic;
+signal data1_in_allowed_S        : std_logic;
+signal data2_in_allowed_S        : std_logic;
+signal data_out_allowed_S        : std_logic;
 signal data1_timestamp_valid_S   : std_logic := '0';
 signal data2_timestamp_valid_S   : std_logic := '0';
 
-begin
+signal outreg_filled_S           : std_logic := '0';
 
-error <= error_S;
+signal time1equalorlarger_S      : std_logic := '0';
+signal time2equalorlarger_S      : std_logic := '0';
 
-data_out_available <= data_out_available_S;
-data_out_available_S <= '1' when (data1_in_available='1') or (data2_in_available='1') 
-		or (data_out_trywrite_S='1') 
-		or (data1_timestamp_valid_S='1') or (data2_timestamp_valid_S='1')
-	else '0';
 
-data_out <= data_out_S;
-data_out_write <= data_out_write_S;
-data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+-- attribute mark_debug : string;
+-- attribute mark_debug of data1_in_allowed_S : signal is "true";
+-- attribute mark_debug of data2_in_allowed_S : signal is "true";
+-- attribute mark_debug of data1_in_write_S : signal is "true";
+-- attribute mark_debug of data2_in_write_S : signal is "true";
+-- attribute mark_debug of data1_in_inpipe_S : signal is "true";
+-- attribute mark_debug of data2_in_inpipe_S : signal is "true";
+-- attribute mark_debug of inc_timeout_counter_S : signal is "true";
+-- attribute mark_debug of clear_timeout_counter_S : signal is "true";
+-- attribute mark_debug of data_out_inpipe_S : signal is "true";
 
-data1_in_allowed <= data1_in_allowed_S;
-data1_in_allowed_S <= '1' when (data_out_allowed='1')
-	and ((read_pulse1_S='1') 
-		or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data1_timestamp_valid_S='0')))
-	else '0';
+				
+					
+begin
 
+data1_in_allowed <= data1_in_allowed_S;
 data2_in_allowed <= data2_in_allowed_S;
-data2_in_allowed_S <= '1' when (data_out_allowed='1')
-	and ((read_pulse2_S='1') 
-		or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data2_timestamp_valid_S='0')))
+data_out_allowed_S <= data_out_allowed;
+data1_in_write_S <= data1_in_write;
+data2_in_write_S <= data2_in_write;
+data_out_write <= data_out_write_S;
+data1_in_inpipe_S <= data1_in_inpipe;
+data2_in_inpipe_S <= data2_in_inpipe;
+data_out_inpipe <= data_out_inpipe_S;
+
+error <= error_S;
+
+data_out_write_S <= '1' when (outreg_filled_S='1') and (data_out_allowed_S='1') else '0';
+
+data_out_inpipe_S <= '1' when 
+		(data1_in_inpipe_S='1') or (data2_in_inpipe_S='1')  or
+		(outreg_filled_S='1') 
+	else '0';
+	
+--data1_in_allowed_S <= '1' when
+--		((data_out_allowed_S='1') or (outreg_filled_S='0')) and
+--		(data1_timestamp_valid_S='1')
+--	else '0';
+data1_in_allowed_S <= '1' when
+		(outreg_filled_S='0') and
+		(data1_timestamp_valid_S='1')
 	else '0';
 
---data2_in_allowed_S <= '1' when (data_out_allowed='1')
---	and ((read_pulse2_S='1') 
---		or (((read_pulse1_S='0') and (data1_timestamp_valid_S='0')) 
---			and ((read_pulse2_S='0') and (data2_timestamp_valid_S='0'))))
+	
+--data2_in_allowed_S <= '1' when
+--		((data_out_allowed_S='1') or (outreg_filled_S='0')) and
+--		(data2_timestamp_valid_S='1') and
+--		(data1_in_write_S='0')
 --	else '0';
+data2_in_allowed_S <= '1' when
+		(outreg_filled_S='0') and
+		(data2_timestamp_valid_S='1') and
+		(data1_in_write_S='0')
+	else '0';
 
-data1_in_write_S <= '1' when (data1_in_write='1') and (data1_in_allowed_S='1') else '0';
-data2_in_write_S <= '1' when (data2_in_write='1') and (data2_in_allowed_S='1') else '0';
 
-readprocess: process(clock)
-variable data1_timestamp_V       : std_logic_vector(31 downto 0) := (others => '0');
-variable data2_timestamp_V       : std_logic_vector(31 downto 0) := (others => '0');
-variable data1_timestamp_valid_V : std_logic;
-variable data2_timestamp_valid_V : std_logic;
-variable data1_lowchannel_V      : std_logic;
-variable data2_lowchannel_V      : std_logic;
-variable data1_pulseskipped_V    : std_logic;
-variable data2_pulseskipped_V    : std_logic;
 
+time1equalorlarger_S <= '1' when 
+		(superburst1>superburst2) or
+		((superburst1=superburst2) and 
+			(timestamp1>=timestamp2))
+	else '0';
+time2equalorlarger_S <= '1' when 
+		(superburst2>superburst1) or
+		((superburst2=superburst1) and 
+			(timestamp2>=timestamp1))
+	else '0';
+
+
+data1_timestamp_valid_S <= '1' when -- when timestamp1<=timestamp2
+		((time2equalorlarger_S='1') and (data1_in_inpipe_S='1')) or 
+		(data2_in_inpipe_S='0') 
+	else '0';
+data2_timestamp_valid_S <= '1' when -- when timestamp2<=timestamp1
+		((time1equalorlarger_S='1') and (data2_in_inpipe_S='1')) or
+		(data1_in_inpipe_S='0') 
+	else '0';
+
+process(clock)
 begin
-	if rising_edge(clock) then
+	if rising_edge(clock) then	
+		clear_timeout_counter_S <= '0';
+		inc_timeout_counter_S <= '0';
 		if reset='1' then
-			data_out_trywrite_S <= '0';
-			read_pulse1_S <= '0';
-			read_pulse2_S <= '0';
-			data1_timestamp_valid_V := '0';
-			data2_timestamp_valid_V := '0';
-			data1_timestamp_valid_S <= '0';
-			data2_timestamp_valid_S <= '0';
-			timeout_counter_S <= (others => '0');
+			error_S <= '0';
+			timestamp <= (others => '0');
+			outreg_filled_S <= '0';
 		else
-			if (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
-				data_out_trywrite_S <= '1'; -- try again
-				timeout_counter_S <= (others => '0');
+			if data1_in_write_S='1' then
+				clear_timeout_counter_S <= '1';
+				channel <= channel1;
+				statusbyte <= statusbyte1;
+				energy <= energy1;
+				CFvalbefore <= CFvalbefore1;
+				CFvalafter <= CFvalafter1;
+				timestamp <= timestamp1;
+				superburst <= superburst1;
+				outreg_filled_S <= '1';
+				error_S <= '0';
+			elsif data2_in_write_S='1' then
+				clear_timeout_counter_S <= '1';
+				channel <= channel2;
+				statusbyte <= statusbyte2;
+				energy <= energy2;
+				CFvalbefore <= CFvalbefore2;
+				CFvalafter <= CFvalafter2;
+				timestamp <= timestamp2;
+				superburst <= superburst2;
+				outreg_filled_S <= '1';
+				error_S <= '0';
 			else
-				if read_pulse1_S='1' then
-					data1_timestamp_valid_V := '0';
-					if data1_in_write_S='1' then
-						timeout_counter_S <= (others => '0');
-						if (data1_in(35 downto 34)="01") then -- next data
-							error_S <= '0';
-							data_out_S <= data1_in;
-							data_out_trywrite_S <= '1';
-						elsif (data1_in(35 downto 34)="10") then -- last data
-							error_S <= '0';
-							data_out_S <= data1_in;
-							read_pulse1_S <= '0';
-							data_out_trywrite_S <= '1';
-						else -- error
-							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
-							data_out_trywrite_S <= '0';
-						end if;
-					else
-						data_out_trywrite_S <= '0';
-						if timeout_counter_S(TIMEOUTBITS-1)='1' then
-							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
-						else
-							if data_out_allowed='1' then
-								timeout_counter_S <= timeout_counter_S+1;
-							end if;
-							error_S <= '0';
-						end if;
-					end if;
-				elsif read_pulse2_S='1' then
-					data2_timestamp_valid_V := '0';
-					if data2_in_write_S='1' then
-						timeout_counter_S <= (others => '0');
-						if (data2_in(35 downto 34)="01") then -- next data
-							error_S <= '0';
-							data_out_S <= data2_in;
-							data_out_trywrite_S <= '1';
-						elsif (data2_in(35 downto 34)="10") then -- last data
-							error_S <= '0';
-							data_out_S <= data2_in;
-							read_pulse2_S <= '0';
-							data_out_trywrite_S <= '1';
-						else -- error
-							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
-							data_out_trywrite_S <= '0';
-						end if;
-					else
-						data_out_trywrite_S <= '0';
-						if timeout_counter_S(TIMEOUTBITS-1)='1' then
-							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
-						else
-							if data_out_allowed='1' then
-								timeout_counter_S <= timeout_counter_S+1;
-							end if;
-							error_S <= '0';
-						end if;
-					end if;
+				if data_out_write_S='1' then
+					outreg_filled_S <= '0';
+					clear_timeout_counter_S <= '1';
+				elsif outreg_filled_S='1' then
+--//					-- if timeout_counter_S(TIMEOUTBITS)='1' then
+						-- error_S <= '1';
+						-- outreg_filled_S <= '0';
+					-- else
+						-- inc_timeout_counter_S <= '1';
+					-- end if;
 				else
-					timeout_counter_S <= (others => '0');
-					if data1_in_write_S='1' then
-						if (data1_in(35 downto 34)="00") then
-							data1_timestamp_V := data1_in(31 downto 0);
-							data1_lowchannel_V := data1_in(33);
-							data1_pulseskipped_V := data1_in(32);
-							data1_timestamp_valid_V := '1';
-						else -- error
-							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
-						end if;
-					end if;
-					if data2_in_write_S='1' then
-						if (data2_in(35 downto 34)="00") then
-							data2_timestamp_V := data2_in(31 downto 0);
-							data2_lowchannel_V := data1_in(33);
-							data2_pulseskipped_V := data1_in(32);
-							data2_timestamp_valid_V := '1';
-						else -- error
-							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
-						end if;
-					end if;
-					if data1_timestamp_valid_V='1' then
-						if data2_timestamp_valid_V='1' then
-							if (data1_timestamp_V(31 downto 0)<data2_timestamp_V(31 downto 0)) -- select 1
-									or (((data1_timestamp_V(31 downto 30)="11") and (data2_timestamp_V(31 downto 30)="00"))) then
-								read_pulse1_S <= '1';
-								data1_timestamp_valid_V := '0';
-								data_out_trywrite_S <= '1';						
-								data_out_S <= "00" & data1_lowchannel_V & data1_pulseskipped_V & data1_timestamp_V;
-							else -- select 2
-								read_pulse2_S <= '1';
-								data2_timestamp_valid_V := '0';
-								data_out_trywrite_S <= '1';						
-								data_out_S <= "00" & data2_lowchannel_V & data2_pulseskipped_V & data2_timestamp_V;
-							end if;
-						elsif data2_in_available='1' then -- data expected: wait
-							data_out_trywrite_S <= '0';
-						else -- write 1
-							read_pulse1_S <= '1';
-							data1_timestamp_valid_V := '0';
-							data_out_trywrite_S <= '1';						
-							data_out_S <= "00" & data1_lowchannel_V & data1_pulseskipped_V & data1_timestamp_V;
-						end if;
-					elsif data2_timestamp_valid_V='1' then
-						if data1_in_available='1' then -- data expected: wait
-							data_out_trywrite_S <= '0';
-						else -- write 2
-							read_pulse2_S <= '1';
-							data2_timestamp_valid_V := '0';
-							data_out_trywrite_S <= '1';						
-							data_out_S <= "00" & data2_lowchannel_V & data2_pulseskipped_V & data2_timestamp_V;
-						end if;
-					else -- no valid timestamps
-						data_out_trywrite_S <= '0';
-					end if;
-				end if;					
-				data1_timestamp_valid_S <= data1_timestamp_valid_V;
-				data2_timestamp_valid_S <= data2_timestamp_valid_V;
+					clear_timeout_counter_S <= '1';
+				end if;
 			end if;
 		end if;
 	end if;
 end process;
-						
-
-
-
--- testword0 <= (others => '0');
-
-testword0(0) <= data1_in_write;
-testword0(1) <= data1_in_available;
-testword0(2) <= data1_in_allowed_S;
-testword0(3) <= read_pulse1_S;
-testword0(4) <= data1_in_write_S;
-testword0(5) <= data1_timestamp_valid_S;
-testword0(9 downto 6) <= data1_in(35 downto 32);
-
-testword0(10) <= data2_in_write;
-testword0(11) <= data2_in_available;
-testword0(12) <= data2_in_allowed_S;
-testword0(13) <= read_pulse2_S;
-testword0(14) <= data2_in_write_S;
-testword0(15) <= data2_timestamp_valid_S;
-testword0(19 downto 16) <= data2_in(35 downto 32);
-
-
-testword0(20) <= data_out_trywrite_S;
-testword0(21) <= data_out_write_S;
-testword0(22) <= data_out_available_S;
-testword0(23) <= data_out_allowed;
-testword0(27 downto 24) <= data_out_S(35 downto 32);
-testword0(28) <= error_S;
-
 
 
-testword0(35 downto 29) <= (others => '0');
+--//-- process(clock)
+-- begin
+	-- if rising_edge(clock) then	
+		-- if (reset='1') or (clear_timeout_counter_S='1') then
+			-- timeout_counter_S <= (others => '0');
+		-- elsif inc_timeout_counter_S='1' then
+			-- timeout_counter_S <= timeout_counter_S+1;
+		-- end if;
+	-- end if;
+-- end process;
 
 
 end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_mux_readfifo.vhd b/FEE_ADC32board/FEE_modules/FEE_mux_readfifo.vhd
index df92b80..23ab5bc 100644
--- a/FEE_ADC32board/FEE_modules/FEE_mux_readfifo.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_mux_readfifo.vhd
@@ -65,15 +65,18 @@ signal data_in_saved_S           : std_logic := '0';
 signal data_in_read_S            : std_logic := '0';
 signal data_in_read_after1clk_S  : std_logic := '0';
 signal data_out_trywrite_S       : std_logic := '0';
+signal data_out_allowed_S        : std_logic := '0';
 
 
 begin
 
-data_out_inpipe <= '1' when (data_in_available='1') or (data_out_trywrite_S='1') or 
-	(data_in_saved_S='1') else '0';
+data_out_inpipe <= '1' when (data_in_available='1') or (data_out_trywrite_S='1') or (data_in_saved_S='1') else '0';
 
 data_in_read <= data_in_read_S;
-data_in_read_S <= '1' when (data_out_allowed='1') and (data_in_available='1') and (data_in_saved_S='0') else '0';
+data_in_read_S <= '1' when 
+((data_out_allowed='1') or ((data_in_saved_S='0') and (data_out_allowed='0') and (data_out_allowed_S='0') and (data_in_read_after1clk_S='0')))
+ and (data_in_available='1') and (data_in_saved_S='0') else '0';
+
 
 data_out_write <= data_out_write_S;
 data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
@@ -111,6 +114,7 @@ begin
 			end if;
 			data_in_read_after1clk_S <= data_in_read_S;
 		end if;
+		data_out_allowed_S <= data_out_allowed;
 	end if;
 end process;
 
diff --git a/FEE_ADC32board/FEE_modules/FEE_pileup_check.vhd b/FEE_ADC32board/FEE_modules/FEE_pileup_check.vhd
index 6c3876f..4919cea 100644
--- a/FEE_ADC32board/FEE_modules/FEE_pileup_check.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_pileup_check.vhd
@@ -1,5 +1,5 @@
 ----------------------------------------------------------------------------------
--- Company: KVI/RUG/Groningen University
+-- Company: KVI-cart/RUG/Groningen University
 -- Engineer: Peter Schakel
 -- Create Date:   16-03-2012
 -- Module Name:   FEE_pileup_check
@@ -9,6 +9,11 @@
 --   16-09-2014   name changed from pileup_check to FEE_pileup_check
 --   24-09-2014   enable_highgain and enable_lowgain inputs added
 --   10-10-2014   Integral output added, as measurement for the energy instead of maximum
+--   19-08-2015   Force_hit added: force waveform acquisition with SODA command
+--   15-12-2015   Clipping check registered
+--   01-02-2016   Check for waveforms with only small values
+--   15-04-2016   Bug repaired for high gain waveforms with maximum length
+--   24-02-2017   Superburstnumber to 31 bits instead of 16 bits
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -40,13 +45,17 @@ use IEEE.std_logic_UNSIGNED.ALL;
 --     reset : synchrounous reset
 --     superburstnumber : actual superburstnumber
 --     timestampcounter : timestampcounter within superburst
+--     force_hit : force hit at input
 --     ADC_highgain : signed ADC value, corrected for baseline
 --     enable_highgain : enable high gain input
+--     threshold_highgain : threshold for high gain, in this module used to check for wavforms with only small signals
 --     max_data_highgain : maximum of the waveform, calculated by the eventdetector (unsigned)
 --     pulse_active_highgain : high gain pulse active (signal above threshold)
---     pulse_rising_highgain : high gain pulse has not yet reached maximum
+--     pulse_rising_highgain : high gain pulse has not yet reached maximum
+--     clipping_highgain : high gain pulse is clipping to maximum value: low gain input should be taken
 --     ADC_lowgain : signed ADC value, corrected for baseline
 --     enable_lowgain : enable low gain input
+--     threshold_lowgain : threshold for low gain, in this module used to check for wavforms with only small signals
 --     max_data_lowgain : maximum of the waveform, calculated by the eventdetector (unsigned)
 --     pulse_active_lowgain : low gain pulse active (signal above threshold)
 --     pulse_rising_lowgain : low gain pulse has not yet reached maximum
@@ -88,14 +97,17 @@ entity FEE_pileup_check is
 		reset                   : in std_logic;
 		superburstnumber        : in std_logic_vector(30 downto 0); 
 		timestampcounter        : in std_logic_vector(15 downto 0); 
+		force_hit               : in std_logic;
 		ADC_highgain            : in std_logic_vector(ADCBITS downto 0); -- signed
 		enable_highgain         : in std_logic;
+		threshold_highgain      : in std_logic_vector(ADCBITS-1 downto 0);
 		max_data_highgain       : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
 		pulse_active_highgain   : in std_logic;
 		pulse_rising_highgain   : in std_logic;
 		clipping_highgain       : in std_logic;
 		ADC_lowgain             : in std_logic_vector(ADCBITS downto 0); -- signed
 		enable_lowgain          : in std_logic;
+		threshold_lowgain       : in std_logic_vector(ADCBITS-1 downto 0);
 		max_data_lowgain        : in std_logic_vector(ADCBITS-1 downto 0); -- unsigned
 		pulse_active_lowgain    : in std_logic;
 		pulse_rising_lowgain    : in std_logic;
@@ -116,15 +128,18 @@ entity FEE_pileup_check is
 		pileuppulse_lowgain     : out std_logic;
 		clearpulse_lowgain      : out std_logic;
 		integral_lowgain        : out std_logic_vector(15 downto 0);
-		superburst              : out std_logic_vector(15 downto 0);
-		timestamp               : out std_logic_vector(15 downto 0);
-		testword0               : out std_logic_vector(35 downto 0)
+		superburst              : out std_logic_vector(30 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0)
 		);
 end FEE_pileup_check;
 
 architecture Behavioral of FEE_pileup_check is
 
 constant ZEROS                       : std_logic_vector(31 downto 0) := (others => '0');
+
+
+signal force_hit_S                   : std_logic := '0';
+
 signal pulse_highgain_tooshort_S     : std_logic := '0';
 signal pulse_highgain_toolong_S      : std_logic := '0';
 signal pulse_highgain_pileup_S       : std_logic := '0';
@@ -138,7 +153,8 @@ signal pulse_active_highgain_prev2_S : std_logic := '0';
 signal counter_highgain_S            : std_logic_vector(7 downto 0);
 
 signal singlepulse_lowgain_occured_S : std_logic := '0';
-signal pileuppulse_lowgain_occured_S : std_logic := '0';
+signal pileuppulse_lowgain_occured_S : std_logic := '0';
+
 signal pulse_lowgain_tooshort_S      : std_logic := '0';
 signal pulse_lowgain_toolong_S       : std_logic := '0';
 signal pulse_lowgain_pileup_S        : std_logic := '0';
@@ -153,26 +169,25 @@ signal pulse_active_lowgain_prev2_S  : std_logic := '0';
 signal clipping_highgain_S           : std_logic := '0';
 signal counter_lowgain_S             : std_logic_vector(7 downto 0) := (others => '0');
 
-signal superburst_highgain_S         : std_logic_vector(15 downto 0) := (others => '0');
+signal superburst_highgain_S         : std_logic_vector(30 downto 0) := (others => '0');
 signal timestamp_highgain_S          : std_logic_vector(15 downto 0) := (others => '0');
-signal superburst_lowgain_S          : std_logic_vector(15 downto 0) := (others => '0');
+signal superburst_lowgain_S          : std_logic_vector(30 downto 0) := (others => '0');
 signal timestamp_lowgain_S           : std_logic_vector(15 downto 0) := (others => '0');
 
 
-signal integral_highgain_S           : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
-signal maxXconstant1_highgain_S      : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
-signal maxXconstant2_highgain_S      : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
-signal integral_highgain_stdl_S      : std_logic_vector(ADCBITS+9 downto 0);
+signal integral_highgain_S           : integer range -2**(16+INTEGRALRATIOBITS) to 2**(16+INTEGRALRATIOBITS)-1;
+signal maxXconstant1_highgain_S      : integer range 0 to 2**(ADCBITS+IDIVMAXBITS)-1;
+signal maxXconstant2_highgain_S      : integer range 0 to 2**(ADCBITS+IDIVMAXBITS)-1;
 signal pulse_highgain_toonarrow_s    : std_logic := '0';
-signal pulse_highgain_toowide_S      : std_logic := '0';
+signal pulse_highgain_toowide_S      : std_logic := '0';
+signal lowsignalwaveform_highgain_S  : std_logic := '0';
 
-
-signal integral_lowgain_S            : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
-signal maxXconstant1_lowgain_S       : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
-signal maxXconstant2_lowgain_S       : integer range -2**(ADCBITS+9) to 2**(ADCBITS+9)-1;
-signal integral_lowgain_stdl_S       : std_logic_vector(ADCBITS+9 downto 0);
+signal integral_lowgain_S            : integer range -2**(16+INTEGRALRATIOBITS) to 2**(16+INTEGRALRATIOBITS)-1;
+signal maxXconstant1_lowgain_S       : integer range 0 to 2**(ADCBITS+IDIVMAXBITS)-1;
+signal maxXconstant2_lowgain_S       : integer range 0 to 2**(ADCBITS+IDIVMAXBITS)-1;
 signal pulse_lowgain_toonarrow_s     : std_logic := '0';
 signal pulse_lowgain_toowide_S       : std_logic := '0';
+signal lowsignalwaveform_lowgain_S   : std_logic := '0';
 
 signal fullsize_wave_highgain_S      : std_logic := '0';
 signal fullsize_wave_lowgain_S       : std_logic := '0';
@@ -183,56 +198,115 @@ signal pulse_busy_highgain_S         : std_logic := '0';
 signal pulse_active_lowgain_S        : std_logic := '0';
 signal prev_pulse_active_lowgains_s  : std_logic := '0';
 signal pulse_busy_lowgain_S          : std_logic := '0';
+
+signal lowgain_chosen_S              : std_logic := '0';
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of ADC_highgain : signal is "true";
+-- attribute mark_debug of max_data_highgain : signal is "true";
+-- attribute mark_debug of pulse_active_highgain : signal is "true";
+-- attribute mark_debug of pulse_active_highgain_S : signal is "true";
+-- attribute mark_debug of pulse_rising_highgain : signal is "true";
+-- attribute mark_debug of pulse_busy_highgain_S : signal is "true";
+-- attribute mark_debug of pulse_highgain_tooshort_S : signal is "true";
+-- attribute mark_debug of pulse_highgain_toolong_S : signal is "true";
+-- attribute mark_debug of pulse_highgain_pileup_S : signal is "true";
+-- attribute mark_debug of singlepulse_highgain_S : signal is "true";
+-- attribute mark_debug of pileuppulse_highgain_S : signal is "true";
+-- attribute mark_debug of clearpulse_highgain_S : signal is "true";
+-- attribute mark_debug of pulse_highgain_toonarrow_s : signal is "true";
+-- attribute mark_debug of pulse_highgain_toowide_S : signal is "true";
+-- attribute mark_debug of lowsignalwaveform_highgain_S : signal is "true";
+
+-- attribute mark_debug of singlepulse_lowgain_occured_S : signal is "true";
+-- attribute mark_debug of pileuppulse_lowgain_occured_S : signal is "true";
+
+-- attribute mark_debug of ADC_lowgain : signal is "true";
+-- attribute mark_debug of max_data_lowgain : signal is "true";
+-- attribute mark_debug of pulse_active_lowgain : signal is "true";
+-- attribute mark_debug of pulse_active_lowgain_S : signal is "true";
+-- attribute mark_debug of pulse_rising_lowgain : signal is "true";
+-- attribute mark_debug of pulse_busy_lowgain_S : signal is "true";
+-- attribute mark_debug of pulse_lowgain_tooshort_S : signal is "true";
+-- attribute mark_debug of pulse_lowgain_toolong_S : signal is "true";
+-- attribute mark_debug of pulse_lowgain_pileup_S : signal is "true";
+-- attribute mark_debug of singlepulse_lowgain_S : signal is "true";
+-- attribute mark_debug of pileuppulse_lowgain_S : signal is "true";
+-- attribute mark_debug of clearpulse_lowgain_S : signal is "true";
+-- attribute mark_debug of pulse_lowgain_toonarrow_s : signal is "true";
+-- attribute mark_debug of pulse_lowgain_toowide_S : signal is "true";
+-- attribute mark_debug of lowsignalwaveform_lowgain_S : signal is "true";
+
+-- attribute mark_debug of clipping_highgain : signal is "true";
+-- attribute mark_debug of clipping_highgain_S : signal is "true";
+
 
 --integer range 0 to 2**(ADCBITS+IDIVMAXBITS-1)-1;
 begin
 
-integral_highgain_stdl_S <= conv_std_logic_vector(integral_highgain_S,ADCBITS+10);
-integral_highgain <= 
-	x"0000" when (integral_highgain_stdl_S(ADCBITS+9)='1') else  -- negative
-	x"ffff" when (integral_highgain_stdl_S(ADCBITS+8 downto INTEGRALRATIOBITS+15)/=ZEROS(ADCBITS+8 downto INTEGRALRATIOBITS+15)) -- clip
-	else integral_highgain_stdl_S(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);
-
-integral_lowgain_stdl_S <= conv_std_logic_vector(integral_lowgain_S,ADCBITS+10);
-integral_lowgain <= 
-	x"0000" when (integral_lowgain_stdl_S(ADCBITS+9)='1') else  -- negative
-	x"ffff" when (integral_lowgain_stdl_S(ADCBITS+8 downto INTEGRALRATIOBITS+15)/=ZEROS(ADCBITS+8 downto INTEGRALRATIOBITS+15)) -- clip
-	else integral_lowgain_stdl_S(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);
-
+integral_highgain <= conv_std_logic_vector(integral_highgain_S,INTEGRALRATIOBITS+16+1)(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);
+integral_lowgain <= conv_std_logic_vector(integral_lowgain_S,INTEGRALRATIOBITS+16+1)(INTEGRALRATIOBITS+15 downto INTEGRALRATIOBITS);
 
 process(clock)
 begin
 	if (rising_edge(clock)) then 
-		if (enable_highgain='1') then
-			fullsize_wave_highgain_S <= fullsize_wave_highgain;
-		else
-			fullsize_wave_highgain_S <= '0';
-		end if;
-		if (enable_lowgain='1') then
-			fullsize_wave_lowgain_S <= fullsize_wave_lowgain;
+		force_hit_S <= force_hit;
+	end if;
+end process;
+	
+-- process(clock)
+-- begin
+	-- if (rising_edge(clock)) then 
+		-- if (enable_highgain='1') then
+			-- fullsize_wave_highgain_S <= fullsize_wave_highgain;
+		-- else
+			-- fullsize_wave_highgain_S <= '0';
+		-- end if;
+		-- if (enable_lowgain='1') then
+			-- fullsize_wave_lowgain_S <= fullsize_wave_lowgain;
+		-- else
+			-- fullsize_wave_lowgain_S <= '0';
+		-- end if;
+	-- end if;
+-- end process;
+fullsize_wave_highgain_S <= fullsize_wave_highgain when enable_highgain='1' else '0';
+fullsize_wave_lowgain_S <= fullsize_wave_lowgain when enable_lowgain='1' else '0';
+
+--clipping_highgain_S <= clipping_highgain;
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (pulse_active_highgain='1') then
+			if clipping_highgain='1' then
+				clipping_highgain_S <= '1';
+			end if;
 		else
-			fullsize_wave_lowgain_S <= '0';
+			if (pulse_active_lowgain='0') or (enable_lowgain='0') then
+				clipping_highgain_S <= '0';
+			end if;
 		end if;
 	end if;
 end process;
 
-clipping_highgain_S <= clipping_highgain;
-
-process(clock)
+process(clock)
+variable integral_highgain_V : integer range -2**(16+INTEGRALRATIOBITS) to 2**(16+INTEGRALRATIOBITS)-1 := 0;
 begin
 	if rising_edge(clock) then
 		if (reset='1') then
-			integral_highgain_S <= conv_integer(signed(ADC_highgain));
+			integral_highgain_V := conv_integer(signed(ADC_highgain));
 		else
 			if ((pulse_active_highgain='0') and (pulse_active_highgain_prev1_S='0')) or
 				((pulse_active_highgain='1') and (pulse_active_highgain_prev1_S='0') and (pulse_active_highgain_prev2_S='1'))then
-				integral_highgain_S <= conv_integer(signed(ADC_highgain));
+				integral_highgain_V := conv_integer(signed(ADC_highgain));
+			elsif integral_highgain_S+conv_integer(signed(ADC_highgain))>2**(16+INTEGRALRATIOBITS)-1 then
+				integral_highgain_V := 2**(16+INTEGRALRATIOBITS)-1;
 			else
-				integral_highgain_S <= integral_highgain_S+conv_integer(signed(ADC_highgain));
-			end if;
-		end if;
+				integral_highgain_V := integral_highgain_S+conv_integer(signed(ADC_highgain));
+			end if;
+		end if;
+		integral_highgain_S <= integral_highgain_V;
 		pulse_active_highgain_prev2_S <= pulse_active_highgain_prev1_S;
-		pulse_active_highgain_prev1_S <= pulse_active_highgain;
+		pulse_active_highgain_prev1_S <= pulse_active_highgain;
 	end if;
 end process;
 		
@@ -245,20 +319,25 @@ begin
 end process;
 pulse_highgain_toonarrow_S <= '1' when maxXconstant1_highgain_S>integral_highgain_S else '0';
 pulse_highgain_toowide_S <= '1' when maxXconstant2_highgain_S<integral_highgain_S else '0';
+
 
 process(clock)
+variable integral_lowgain_V : integer range -2**(16+INTEGRALRATIOBITS) to 2**(16+INTEGRALRATIOBITS)-1;
 begin
 	if rising_edge(clock) then
-		if (reset='1') then
-			integral_lowgain_S <= conv_integer(signed(ADC_lowgain));
+		if (reset='1') then
+			integral_lowgain_V := conv_integer(signed(ADC_lowgain));
 		else
-			if ((pulse_active_lowgain='0') and (pulse_active_lowgain_prev1_S='0')) or 
-				((pulse_active_lowgain='1') and (pulse_active_lowgain_prev1_S='0') and (pulse_active_lowgain_prev2_S='1')) then -- if 2nd pulse within 1 clock
-				integral_lowgain_S <= conv_integer(signed(ADC_lowgain));
+			if ((pulse_active_lowgain='0') and (pulse_active_lowgain_prev1_S='0')) or
+				((pulse_active_lowgain='1') and (pulse_active_lowgain_prev1_S='0') and (pulse_active_lowgain_prev2_S='1'))then
+				integral_lowgain_V := conv_integer(signed(ADC_lowgain));
+			elsif integral_lowgain_S+conv_integer(signed(ADC_lowgain))>2**(16+INTEGRALRATIOBITS)-1 then
+				integral_lowgain_V := 2**(16+INTEGRALRATIOBITS)-1;
 			else
-				integral_lowgain_S <= integral_lowgain_S+conv_integer(signed(ADC_lowgain));
+				integral_lowgain_V := integral_lowgain_S+conv_integer(signed(ADC_lowgain));
 			end if;
-		end if;
+		end if;
+		integral_lowgain_S <= integral_lowgain_V;
 		pulse_active_lowgain_prev2_S <= pulse_active_lowgain_prev1_S;
 		pulse_active_lowgain_prev1_S <= pulse_active_lowgain;
 	end if;
@@ -288,6 +367,7 @@ singlepulse_highgain_S <= enable_highgain
 		and (pulse_highgain_toowide_S='0')
 		and ((singlepulse_lowgain_occured_S='0') -- and (pulse_lowgain_tooshort_S='1')
 			and (pileuppulse_lowgain_occured_S='0'))
+		and ((not ((pulse_active_lowgain='1') and (clipping_highgain_S='1'))) or (enable_lowgain='0'))
 		and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))
 	else '0';
 singlepulse_highgain <= singlepulse_highgain_S;
@@ -298,13 +378,16 @@ pileuppulse_highgain_S <= enable_highgain
 		(((pulse_active_highgain='0') and (prev_pulseactive_highgain_S='1')) 
 			and ((pulse_highgain_toolong_S='0') and ((pulse_highgain_tooshort_S='0') and (pulse_highgain_toonarrow_S='0')))
 			and ((pulse_highgain_pileup_S='1') or (pulse_highgain_toowide_S='1'))
-			and ((singlepulse_lowgain_occured_S='0')  -- and (pulse_lowgain_tooshort_S='1') 
-				and (pileuppulse_lowgain_occured_S='0'))
-			and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))
+			and ((singlepulse_lowgain_occured_S='0') and (singlepulse_lowgain_S='0')  -- and (pulse_lowgain_tooshort_S='1') 
+				and (pileuppulse_lowgain_occured_S='0') and (pileuppulse_lowgain_S='0'))
+			and ((not ((pulse_active_lowgain='1') and (clipping_highgain_S='1'))) or (enable_lowgain='0'))
+			and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))
+			and (lowsignalwaveform_highgain_S='0'))
 		or (((pulse_highgain_toolong_S='1') and (prev_pulse_highgain_toolong_S='0'))
-			and ((singlepulse_lowgain_occured_S='0') -- and (pulse_lowgain_tooshort_S='1') 
-				and (pileuppulse_lowgain_occured_S='0'))
-			and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))
+			and ((singlepulse_lowgain_occured_S='0') and (pileuppulse_lowgain_S='0') and (singlepulse_lowgain_S='0') -- and (pulse_lowgain_tooshort_S='1') 
+				and (pileuppulse_lowgain_occured_S='0') and ((clipping_highgain_S='0') or (pulse_active_lowgain='0')))
+			and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))
+			and (lowsignalwaveform_highgain_S='0'))
 		or (((pulse_highgain_toolong_S='1') and (prev_pulse_highgain_toolong_S='0'))
 			and ((fullsize_wave_highgain_S='1') and (fullsize_wave_lowgain_S='0')))
 	else '0';
@@ -329,7 +412,7 @@ begin
 			pulse_highgain_pileup_S <= '0';
 			pulse_busy_highgain_S <= '0';
 		else				
-			if (pulse_active_highgain_S='1') or (pulse_active_highgain='1')  then
+			if (pulse_active_highgain_S='1') or (pulse_active_highgain='1') or (force_hit_S='1') then
 				pulse_busy_highgain_S <= enable_highgain;
 				if counter_highgain_S<maxwavelength then
 					counter_highgain_S <= counter_highgain_S+1;
@@ -341,7 +424,7 @@ begin
 					pulse_highgain_toolong_S <= enable_highgain;
 				end if;
 				if (pulse_active_highgain_S='1') and (prev_pulseactive_highgainS_S='0') then
-					superburst_highgain_S <= superburstnumber(15 downto 0);
+					superburst_highgain_S <= superburstnumber;
 					timestamp_highgain_S <= timestampcounter;
 				end if;
 			else
@@ -401,10 +484,12 @@ pileuppulse_lowgain_S <= enable_lowgain
 			and ((pulse_lowgain_pileup_S='1') or (pulse_lowgain_toowide_S='1'))
 			and ((pulse_lowgain_toolong_S='0') and (pulse_lowgain_tooshort_S='0'))
 			and ((clipping_highgain_S='1') or (enable_highgain='0'))
-			and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))
+			and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))
+			and (lowsignalwaveform_lowgain_S='0'))
 		or (((pulse_lowgain_toolong_S='1') and (prev_pulse_lowgain_toolong_S='0'))
 			and ((clipping_highgain_S='1') or (enable_highgain='0'))
-			and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0')))
+			and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='0'))
+			and (lowsignalwaveform_lowgain_S='0'))
 		or (((pulse_lowgain_toolong_S='1') and (prev_pulse_lowgain_toolong_S='0'))
 			and ((fullsize_wave_highgain_S='0') and (fullsize_wave_lowgain_S='1')))
 	else '0';
@@ -428,7 +513,7 @@ begin
 			pulse_lowgain_pileup_S <= '0';
 			pulse_busy_lowgain_S <= '0';
 		else
-			if (pulse_active_lowgain_S='1') or (pulse_active_lowgain='1') then
+			if (pulse_active_lowgain_S='1') or (pulse_active_lowgain='1') or (force_hit_S='1') then
 				pulse_busy_lowgain_S <= enable_lowgain;
 				if counter_lowgain_S<maxwavelength then
 					counter_lowgain_S <= counter_lowgain_S+1;
@@ -440,7 +525,7 @@ begin
 					pulse_lowgain_toolong_S <= enable_lowgain;
 				end if;
 				if (pulse_active_lowgain_S='1') or (prev_pulse_active_lowgainS_S='0') then
-					superburst_lowgain_S <= superburstnumber(15 downto 0);
+					superburst_lowgain_S <= superburstnumber;
 					timestamp_lowgain_S <= timestampcounter;
 				end if;
 			else
@@ -454,72 +539,39 @@ begin
 		prev_pulseactive_lowgain_S <= pulse_active_lowgain;
 		prev_pulse_active_lowgainS_S <= pulse_active_lowgain_S;
 	end if;
-end process;
+end process;
+
+process(clock)
+begin
+	if rising_edge(clock) then
+		if ('0' & max_data_highgain)<=(threshold_highgain & '0') then
+			lowsignalwaveform_highgain_S <= '1';
+		else
+			lowsignalwaveform_highgain_S <= '0';
+		end if;
+		if ('0' & max_data_lowgain)<=(threshold_lowgain & '0') then
+			lowsignalwaveform_lowgain_S <= '1';
+		else
+			lowsignalwaveform_lowgain_S <= '0';
+		end if;
+	end if;
+end process;
 
-process(clock)
-begin
-	if rising_edge(clock) then
-		if reset='1' then
-			superburst <= (others => '0');
-			timestamp <= (others => '0');
-		else				
-			if (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') then
-				superburst <= superburst_lowgain_S;
-				timestamp <= timestamp_lowgain_S;
-			elsif (singlepulse_highgain_S='1') or (pileuppulse_highgain_S='1') then
-				superburst <= superburst_highgain_S;
-				timestamp <= timestamp_highgain_S;
-			end if;
-		end if;
-	end if;
+
+superburst <= superburst_lowgain_S when (lowgain_chosen_S='1') or (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') else superburst_highgain_S;
+timestamp <= timestamp_lowgain_S when (lowgain_chosen_S='1') or (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') else timestamp_highgain_S;
+
+process(clock)
+begin
+	if rising_edge(clock) then
+		if (singlepulse_lowgain_S='1') or (pileuppulse_lowgain_S='1') then
+			lowgain_chosen_S <= '1';
+		elsif (singlepulse_highgain_S='1') or (pileuppulse_highgain_S='1') then
+			lowgain_chosen_S <= '0';
+		end if;
+	end if;
 end process;
 
---testword0(0) <= pulse_active_highgain;
---testword0(1) <= pulse_rising_highgain;
---
---testword0(2) <= pulse_active_highgain_S; -- pulse_highgain_tooshort_S;
---testword0(3) <= pulse_highgain_toolong_S;
---testword0(4) <= prev_pulse_highgain_toolong_S;
---testword0(5) <= prev_pulseactive_highgain_S;
---testword0(6) <= singlepulse_highgain_S;
---testword0(7) <= pileuppulse_highgain_S;
---testword0(8) <= pulse_busy_highgain_S; -- pulse_highgain_toonarrow_s;
---testword0(9) <= pulse_highgain_toowide_S;
---
---testword0(15 downto 10) <= counter_highgain_S(5 downto 0);
---testword0(16) <= pulse_active_lowgain;
---testword0(17) <= pulse_rising_lowgain;
---testword0(18) <= pulse_active_lowgain_S; -- pulse_lowgain_tooshort_S;
---testword0(19) <= pulse_lowgain_toolong_S;
---testword0(20) <= prev_pulse_lowgain_toolong_S;
---testword0(21) <= prev_pulseactive_lowgain_S;
---testword0(22) <= singlepulse_lowgain_S;
---testword0(23) <= pileuppulse_lowgain_S;
---testword0(24) <= pulse_busy_lowgain_S; -- pulse_lowgain_toonarrow_s;
---testword0(25) <= pulse_lowgain_toowide_S;
---
---testword0(31 downto 26) <= counter_lowgain_S(5 downto 0);
---
---testword0(32) <= singlepulse_lowgain_occured_S;
---testword0(33) <= pileuppulse_lowgain_occured_S;
---testword0(34) <= clearpulse_highgain_S;
---testword0(35) <= clearpulse_lowgain_S;
-
-
-testword0(22) <= pulse_active_highgain;
-testword0(23) <= pulse_active_highgain_S; -- pulse_highgain_tooshort_S;
-testword0(24) <= singlepulse_highgain_S;
-testword0(25) <= pileuppulse_highgain_S;
-testword0(26) <= pulse_busy_highgain_S; -- pulse_highgain_toonarrow_s;
-testword0(27) <= pulse_active_lowgain;
-testword0(28) <= pulse_active_lowgain_S; -- pulse_lowgain_tooshort_S;
-testword0(29) <= singlepulse_lowgain_S;
-testword0(30) <= pileuppulse_lowgain_S;
-testword0(31) <= pulse_busy_lowgain_S; -- pulse_lowgain_toonarrow_s;
-testword0(32) <= singlepulse_lowgain_occured_S;
-testword0(33) <= pileuppulse_lowgain_occured_S;
-testword0(34) <= clearpulse_highgain_S;
-testword0(35) <= clearpulse_lowgain_S;
 
 end Behavioral;
 
diff --git a/FEE_ADC32board/FEE_modules/FEE_pulse2to1_pulse.vhd b/FEE_ADC32board/FEE_modules/FEE_pulse2to1_pulse.vhd
index b38a36a..7c4550e 100644
--- a/FEE_ADC32board/FEE_modules/FEE_pulse2to1_pulse.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_pulse2to1_pulse.vhd
@@ -105,6 +105,14 @@ signal pulse2_skipped_S          : std_logic := '0';
 signal pulse1_skipbit_S          : std_logic;
 signal pulse2_skipbit_S          : std_logic;
 
+-- attribute mark_debug : string;
+-- attribute mark_debug of pulse1_skipped : signal is "true";
+-- attribute mark_debug of pulse2_skipped : signal is "true";
+-- attribute mark_debug of pulse1_skipped_S : signal is "true";
+-- attribute mark_debug of pulse1_skipbit_S : signal is "true";
+-- attribute mark_debug of pulse2_skipped_S : signal is "true";
+-- attribute mark_debug of pulse2_skipbit_S : signal is "true";
+
 begin
 
 pulse_skipped <= '1' when (pulse1_skipped_S='1') or (pulse2_skipped_S='1') else '0';
diff --git a/FEE_ADC32board/FEE_modules/FEE_pulse_and_pileup_waveforms.vhd b/FEE_ADC32board/FEE_modules/FEE_pulse_and_pileup_waveforms.vhd
index 5cc71af..421c3c3 100644
--- a/FEE_ADC32board/FEE_modules/FEE_pulse_and_pileup_waveforms.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_pulse_and_pileup_waveforms.vhd
@@ -1,5 +1,5 @@
 ----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
+-- Company:       KVI-cart/RUG/Groningen University
 -- Engineer:      Peter Schakel
 -- Create Date:   03-02-2012
 -- Module Name:   FEE_pulse_and_pileup_waveforms
@@ -10,6 +10,12 @@
 --   23-09-2014   sort pileup waveforms
 --   10-10-2014   Integral as measurement for the energy instead of maximum
 --   16-10-2014   inpipe signals
+--   24-04-2015   Moving Window Deconvolution added
+--   21-07-2015   Disable pulsedata_allowed_S and wavedata_allowed_S for better timing
+--   19-08-2015   Force_hit added: force waveform acquisition with SODA command
+--   23-10-2015   Check on buffer filled passed on to wave multiplexer: wavedata_moretocome_S signal
+--   28-10-2016   Enable_waveform input added
+--   23-02-2017   Parallel data from Feature Extraction instead of 36-bits
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -27,10 +33,11 @@ use IEEE.std_logic_textio.all; -- I/O for logic types
 --     on each input pulses are detected and the waveform is put in a buffer.
 --     A timestamp is added, based on maximum signal in waveform.
 --     From each high-gain and low-gain input pair only one waveform at the same time is choosen and passed on.
---     The waveform are distinguish for single pulse and pileup waveforms.
---     The single pulse waveforms are sorted, based on timestamp, and multiplexed to one stream.
---     The pileup waveforms multiplexed to one stream (unsorted).
---     The parameters are organised in registers A,B,C,D :
+--     The waveform are distinguish for single pulse and multiple pulses (pileup).
+--     The single pulse and multiple pulses are sorted, based on timestamp, and multiplexed to one stream.
+--     There is also a mode in which the waveforms are produced. They are also multiplexed and sorted to one stream.
+--
+--     The parameters are organised in 4 registers :
 --       board_register A: write
 --         register_A(7..0) = threshold High
 --         register_A(15..8) = threshold Low
@@ -38,63 +45,88 @@ use IEEE.std_logic_textio.all; -- I/O for logic types
 --         register_A(17) = disable Low
 --         register_A(23..18) = I/Max discard
 --         register_A(29..24) = I/Max pileup
+--         register_A(30) = enable raw data in waveform instead of baseline corrected data
 --       board_register B: write
 --         register_B(7..0) = minimum pulselength
 --         register_B(15..8) = pileup length
 --         register_B(23..16) = maximum wavelength
 --         register_B(24) = fullsize High
 --         register_B(25) = fullsize Low
---         register_B(29..26) = CF delay
+--         register_B(29..26) = CF delay
+--         register_B(31..30) = CF delay Pileup
+--      board_register C: write
+--         register_C(4..0) = MWD1_width
+--         register_C(9..8) = MWD2_width 
+--         register_C(11..10) = MWDpu1_width
+--         register_C(13..12) = MWDpu2_width
+--         register_C(31..16) = MWD1_tau_factor , MWDpu_tau_factor
+--      board_register D: write
+--         register_D(15..0) = MWD2_tau_factor
+--         register_D(31..16) = MWD2pu_tau_factor
 --
 --
 -- generics
---     NROFADCS : number of adc-inputs (two adc-inputs are a combined high-gain and low-gain pair)
---     ADCBITS : number of ADC-bits
---     BWBITS : number of bits for the baseline IIR filter bandwidth
---     WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
---     IDIVMAXBITS : number of bits for maximum to integral ratio check
---     INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
---     CF_DELAYBITS : number of bits for the Constant Fraction delay
+--    NROFADCS : number of adc-inputs (two adc-inputs are a combined high-gain and low-gain pair)
+--    ADCBITS : number of ADC-bits
+--    MWD_WIDTHBITS : number of bits for the width
+--    MWD_SCALEBITS : number of bits for tau factor, also scaling for calculations
+--    MWD2_WIDTHBITS : number of bits for the width of second MWD
+--    MWD2_SCALEBITS : number of bits for tau factor for second MWD, also scaling for calculations
+--    MWD_DOUBLEFILTER : two MWD filters in series for single pulses
+--    MWD_PU_DOUBLEFILTER : two MWD filters in series for pileup
+--    BASELINE_BWBITS : number of bits for the baseline IIR filter bandwidth
+--    WAVEFORMBUFFERSIZE : number of bits for the buffer memory address: power of this constant will give the size
+--    IDIVMAXBITS : number of bits for maximum to integral ratio check
+--    INTEGRALRATIOBITS : number of bits for integral to energy ratio (bits to shift to the right)
+--    CF_DELAYBITS : number of bits for the Constant Fraction delay
+--    MAXPILEUPHITS : maximum number of hits in one pileup waveform
+--    NOWAVEFORMS : no waveforms
 --		
 -- inputs
---     clock : clock
---     reset : synchrounous reset
---     superburstnumber : actual superburstnumber
---     timestampcounter : timestampcounter within superburst
---     ADCdata : array with ADC data for each input
---     enable_data : enable adc data
---     slowcontrol_byte_data : data from slowcontrol containing commands/settings (sent byte-wise)
---     slowcontrol_byte_write : write signal for the slowcontrol commands
---     slowcontrol_byte_request : indicates that the slowcontrol command is a request for data (status reading)
---     pulsedata_read : read signal for data with resulting single pulse waveforms
---     pileupdata_read : read signal for data with resulting pileup waveforms
+--    clock : clock
+--    reset : synchrounous reset
+--    superburstnumber : actual superburstnumber
+--    superburstupdate : new superburstnumber
+--    ADCdata : array with ADC data for each input
+--    enable_data : enable adc data
+--    enable_waveform : produce waveforms and not Feature Extraction data
+--    force_hit : force hit at input
+--    slowcontrol_byte_data : data from slowcontrol containing commands/settings (sent byte-wise)
+--    slowcontrol_byte_write : write signal for the slowcontrol commands
+--    slowcontrol_byte_request : indicates that the slowcontrol command is a request for data (status reading)
+--    pulsedata_read : read signal for data with resulting single pulse waveforms
+--    wavedata_read : read signal for data with resulting pileup waveforms
 --			  
 -- outputs
---     pulsedata_out : 36 bits output data with resulting single pulse waveforms:
---        	bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
---        	bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
---        	bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
---     pulsedata_available : output single pulse data is available
---     pulsedata_inpipe : more single pulse data on its way 
---     pileupdata_out : 36-bits output data with resulting pileup waveforms:
---        	bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
---        	bits(35..32)="0001" : 
+--    pulsedata_channel : results from Feature Extraction: ADC channel number
+--    pulsedata_status : results from Feature Extraction: status byte
+--    pulsedata_superburst : results from Feature Extraction: superburst number
+--    pulsedata_timestamp : results from Feature Extraction: timestamp within superburst
+--    pulsedata_energy : results from Feature Extraction: energy
+--    pulsedata_CFvalbefore : results from Feature Extraction: ADC sample before zero-crossing Constant Fraction method
+--    pulsedata_CFvalafter : results from Feature Extraction: ADC sample after zero-crossing Constant Fraction method
+--    pulsedata_available : output single pulse data is available
+--    pulsedata_inpipe : more single pulse data on its way 
+--    wavedata_out : 36-bits output data with resulting pileup waveforms:
+--       	bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+--       	bits(35..32)="0001" : 
 --              bits(31..24) = statusbyte (bit6=overflow) 
 --              bits(23..16) = 0
 --              bits(7..0) = adcnumber (channel identifaction)
 --        	bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
 --        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
 --        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
---     pileupdata_available : output pileup data is available
---     pileupdata_inpipe : more pileup data on its way 
---     pulsedetect : pulse detected for each of the ADC channels
---     overflow : overflow in data from one of the channels: data is lost
+--    wavedata_available : output pileup data is available
+--    wavedata_inpipe : more pileup data on its way 
+--    pulsedetect : pulse detected for each of the ADC channels
+--    overflow : overflow in data from one of the channels: data is lost
+--    error : error in data
 --
 -- components
---     FEE_dual_pulse_waveform : module to extract waveform containing pulse from high_gain/low_gain pair
---     FEE_sorting_mux : multiplexer for pulse data, sort based on timestamp
---     FEE_sorting_wavemux : sorted multiplexer for waveform data
---     FEE_slowcontrol_receive_from_cpu : receive slowcontrol commands, byte-wise
+--    FEE_dual_pulse_waveform : module to extract waveform containing pulse from high_gain/low_gain pair
+--    FEE_sorting_mux : multiplexer for pulse data, sort based on timestamp
+--    FEE_sorting_wavemux : sorted multiplexer for waveform data
+--    FEE_slowcontrol_receive_from_cpu : receive slowcontrol commands, byte-wise
 --
 --
 ------------------------------------------------------------------------------------------------------
@@ -105,36 +137,49 @@ entity FEE_pulse_and_pileup_waveforms is
 	generic (
 		NROFADCS                : natural := 16;
 		ADCBITS                 : natural := 14;
-		BWBITS                  : natural := 10;
+		MWD_WIDTHBITS           : natural := 5;
+		MWD_SCALEBITS           : natural := 16;
+		MWD2_WIDTHBITS          : natural := 2;
+		MWD2_SCALEBITS          : natural := 16;
+		MWD_DOUBLEFILTER        : boolean := false;
+		MWD_PU_DOUBLEFILTER     : boolean := false;
+		BASELINE_BWBITS         : natural := 10;
 		WAVEFORMBUFFERSIZE      : natural := 11;
 		IDIVMAXBITS             : natural := 6;
 		INTEGRALRATIOBITS       : natural := 3;
-		CF_DELAYBITS            : natural := 8
+		CF_DELAYBITS            : natural := 8;
+		MAXPILEUPHITS           : natural := 3;
+		NOWAVEFORMS             : boolean := false
 		);
     Port (
 		clock                   : in std_logic;
 		reset                   : in std_logic;
 		superburstnumber        : in std_logic_vector(30 downto 0); 
-		timestampcounter        : in std_logic_vector(15 downto 0); 
+		superburstupdate        : in std_logic; 
 		ADCdata                 : in array_adc_type;
 		enable_data             : in std_logic;
+		enable_waveform         : in std_logic;
+		force_hit               : in std_logic;
 		slowcontrol_byte_data   : in std_logic_vector (7 downto 0);
 		slowcontrol_byte_write  : in std_logic;
 		slowcontrol_byte_request: in std_logic;
-		pulsedata_out           : out std_logic_vector(35 downto 0);
+		pulsedata_channel       : out std_logic_vector(7 downto 0);
+		pulsedata_status        : out std_logic_vector(7 downto 0);
+		pulsedata_superburst    : out std_logic_vector(30 downto 0);
+		pulsedata_timestamp     : out std_logic_vector(15 downto 0);
+		pulsedata_energy        : out std_logic_vector(15 downto 0);
+		pulsedata_CFvalbefore   : out std_logic_vector(15 downto 0);		
+		pulsedata_CFvalafter    : out std_logic_vector(15 downto 0);
 		pulsedata_read          : in std_logic;
 		pulsedata_available     : out std_logic;
 		pulsedata_inpipe        : out std_logic;
-		pileupdata_out          : out std_logic_vector(35 downto 0);
-		pileupdata_read         : in std_logic;
-		pileupdata_available    : out std_logic;
-		pileupdata_inpipe       : out std_logic;
+		wavedata_out            : out std_logic_vector(35 downto 0);
+		wavedata_read           : in std_logic;
+		wavedata_available      : out std_logic;
+		wavedata_inpipe         : out std_logic;
 		pulsedetect             : out std_logic_vector(0 to NROFADCS-1);
 		overflow                : out std_logic;
-		testindex               : in integer range 0 to NROFADCS/2-1;
-		testword0               : out std_logic_vector(35 downto 0);
-		testword1               : out std_logic_vector(35 downto 0);
-		testword2               : out std_logic_vector(35 downto 0)
+		error                   : out std_logic
 		);
 end FEE_pulse_and_pileup_waveforms;
 
@@ -142,51 +187,73 @@ architecture Behavioral of FEE_pulse_and_pileup_waveforms is
 
 component FEE_dual_pulse_waveform is
 	generic (
+		ADCNUMBER               : natural := 0;
 		ADCBITS                 : natural := ADCBITS;
-		BWBITS                  : natural := BWBITS;
+		BASELINE_BWBITS         : natural := BASELINE_BWBITS;
+		MWD_WIDTHBITS           : natural := MWD_WIDTHBITS;
+		MWD_SCALEBITS           : natural := MWD_SCALEBITS;
+		MWD2_WIDTHBITS          : natural := MWD2_WIDTHBITS;
+		MWD2_SCALEBITS          : natural := MWD2_SCALEBITS;
+		MWD_DOUBLEFILTER        : boolean := MWD_DOUBLEFILTER;
+		MWD_PU_DOUBLEFILTER     : boolean := MWD_PU_DOUBLEFILTER;
 		WAVEFORMBUFFERSIZE      : natural := WAVEFORMBUFFERSIZE;
 		IDIVMAXBITS             : natural := IDIVMAXBITS;
 		INTEGRALRATIOBITS       : natural := INTEGRALRATIOBITS;
-		CF_DELAYBITS            : natural := CF_DELAYBITS
+		CF_DELAYBITS            : natural := CF_DELAYBITS;
+		MAXPILEUPHITS           : natural := MAXPILEUPHITS;
+		NOWAVEFORMS             : boolean := NOWAVEFORMS
 		);
     Port (
 		clock                   : in  std_logic;
-		reset                   : in  std_logic;
-		enable                  : in  std_logic;
-		adcnumber               : in std_logic_vector(7 downto 0); 
-		cf_delay                : in std_logic_vector(CF_DELAYBITS-1 downto 0);
-		superburstnumber        : in std_logic_vector(30 downto 0); 
-		timestampcounter        : in std_logic_vector(15 downto 0); 
-		ADCdata_highgain        : in std_logic_vector((ADCBITS-1) downto 0);
-		ADCdata_lowgain         : in std_logic_vector((ADCBITS-1) downto 0);
-		threshold_highgain      : in std_logic_vector((ADCBITS-1) downto 0);
-		threshold_lowgain       : in std_logic_vector((ADCBITS-1) downto 0);
+		reset                   : in  std_logic;
+		enable                  : in  std_logic;
+		enable_waveform         : in std_logic;
+		force_hit               : in std_logic;
+		CF_delay                : in std_logic_vector(CF_DELAYBITS-1 downto 0);
+		CFpu_delay              : in std_logic_vector(1 downto 0);
+		superburstnumber        : in std_logic_vector(30 downto 0); 
+		superburstupdate        : in std_logic; 
+		ADCdata_highgain        : in std_logic_vector(ADCBITS-1 downto 0);
+		ADCdata_lowgain         : in std_logic_vector(ADCBITS-1 downto 0);
+		MWD1_width              : in  std_logic_vector(MWD_WIDTHBITS-1 downto 0);
+		MWD1_tau_factor         : in  std_logic_vector(MWD_SCALEBITS-1 downto 0);
+		MWD2_width              : in  std_logic_vector(MWD2_WIDTHBITS-1 downto 0);
+		MWD2_tau_factor         : in  std_logic_vector(MWD2_SCALEBITS-1 downto 0);
+		MWDpu1_width            : in  std_logic_vector(1 downto 0);
+		MWDpu1_tau_factor       : in  std_logic_vector(MWD_SCALEBITS-1 downto 0);
+		MWDpu2_width            : in  std_logic_vector(MWD2_WIDTHBITS-1 downto 0);
+		MWDpu2_tau_factor       : in  std_logic_vector(MWD2_SCALEBITS-1 downto 0);
+		threshold_highgain      : in std_logic_vector(ADCBITS-1 downto 0);
+		threshold_lowgain       : in std_logic_vector(ADCBITS-1 downto 0);
 		enable_highgain         : in  std_logic;
 		enable_lowgain          : in  std_logic;
+		enable_rawdata          : in  std_logic;
 		IIRfilterBW             : in std_logic_vector(2 downto 0);
 		maxabovebaseline        : in std_logic_vector(3 downto 0);
-		minpulselength          : in std_logic_vector(7 downto 0);
-		pileuplength            : in std_logic_vector(7 downto 0);
-		maxwavelength           : in std_logic_vector(7 downto 0);
-		IdivMAX_discard         : in std_logic_vector(IDIVMAXBITS-1 downto 0);
-		IdivMAX_pileup          : in std_logic_vector(IDIVMAXBITS-1 downto 0);
-		fullsize_wave_highgain  : in  std_logic;
-		fullsize_wave_lowgain   : in  std_logic;
-		ADC_minus_baseline_highgain : out std_logic_vector(ADCBITS downto 0);
-		ADC_minus_baseline_lowgain : out std_logic_vector(ADCBITS downto 0);
-		pulsedata_allowed       : in std_logic;
-		pulsedata_almostfull    : in std_logic;
-		pulsedata_write         : out std_logic;
-		pulsedata_out           : out std_logic_vector(35 downto 0);
-		pileupdata_allowed      : in std_logic;
-		pileupdata_almostfull   : in std_logic;
-		pileupdata_write        : out std_logic;
-		pileupdata_out          : out std_logic_vector(35 downto 0);
+		minpulselength          : in std_logic_vector(7 downto 0);
+		pileuplength            : in std_logic_vector(7 downto 0);
+		maxwavelength           : in std_logic_vector(7 downto 0);
+		IdivMAX_discard         : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+		IdivMAX_pileup          : in std_logic_vector(IDIVMAXBITS-1 downto 0);
+		fullsize_wave_highgain  : in  std_logic;
+		fullsize_wave_lowgain   : in  std_logic;
+		pulsedata_allowed       : in std_logic;
+		pulsedata_write         : out std_logic;
+		pulsedata_lowgain       : out std_logic;
+		pulsedata_superburst    : out std_logic_vector(30 downto 0);
+		pulsedata_timestamp     : out std_logic_vector(15 downto 0);
+		pulsedata_energy        : out std_logic_vector(15 downto 0);
+		pulsedata_CFvalbefore   : out std_logic_vector(15 downto 0);
+		pulsedata_CFvalafter    : out std_logic_vector(15 downto 0);
+		pulsedata_status        : out std_logic_vector(7 downto 0);
+		wavedata_allowed        : in std_logic;
+		wavedata_almostfull     : in std_logic;
+		wavedata_available      : out std_logic;
+		wavedata_write          : out std_logic;
+		wavedata_out            : out std_logic_vector(35 downto 0);
 		pulsedetect             : out std_logic;
-		overflow                : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0);
-		testword1               : out std_logic_vector(35 downto 0);
-		testword2               : out std_logic_vector(35 downto 0)
+		overflow                : out std_logic;
+		error                   : out std_logic
 		);
 end component;
 
@@ -197,17 +264,28 @@ component FEE_sorting_mux is
     Port ( 
 		clock                   : in std_logic;
 		reset                   : in std_logic;
-		data_in                 : in array_halfadc36bits_type;
+		superburstnumber        : in std_logic_vector(30 downto 0);		
+		superburstupdate        : in std_logic;
+		data_in_status          : in array_halfadc8bits_type;
+		data_in_lowgain         : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_superburst      : in array_halfadc31bits_type;
+		data_in_timestamp       : in array_halfadc16bits_type;
+		data_in_energy          : in array_halfadc16bits_type;
+		data_in_CFvalbefore     : in array_halfadc16bits_type;		
+		data_in_CFvalafter      : in array_halfadc16bits_type;		
 		data_in_write           : in std_logic_vector(0 to NROFMUXINPUTS-1);
 		data_in_allowed         : out std_logic_vector(0 to NROFMUXINPUTS-1);
-		data_in_almostfull      : out std_logic_vector(0 to NROFMUXINPUTS-1);
-		data_out                : out std_logic_vector(35 downto 0);
+		data_out_channel        : out std_logic_vector(7 downto 0);
+		data_out_status         : out std_logic_vector(7 downto 0);
+		data_out_superburst     : out std_logic_vector(30 downto 0);
+		data_out_timestamp      : out std_logic_vector(15 downto 0);
+		data_out_energy         : out std_logic_vector(15 downto 0);
+		data_out_CFvalbefore    : out std_logic_vector(15 downto 0);		
+		data_out_CFvalafter     : out std_logic_vector(15 downto 0);
 		data_out_read           : in std_logic;
 		data_out_available      : out std_logic;
 		data_out_inpipe         : out std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0);
-		testword1               : out std_logic_vector(35 downto 0)
+		error                   : out std_logic
 		);
 end component;
 
@@ -221,15 +299,14 @@ component FEE_sorting_wavemux is
 		reset                   : in std_logic;
 		data_in                 : in array_halfadc36bits_type;
 		data_in_write           : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_available       : in std_logic_vector(0 to NROFMUXINPUTS-1);
 		data_in_allowed         : out std_logic_vector(0 to NROFMUXINPUTS-1);
-		data_in_almostfull      : out std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_almostfull      : out std_logic_vector(0 to NROFMUXINPUTS-1);
 		data_out                : out std_logic_vector(35 downto 0);
 		data_out_read           : in std_logic;
 		data_out_available      : out std_logic;
-		data_out_inpipe         : out std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0);
-		testword1               : out std_logic_vector(35 downto 0)
+		data_out_inpipe         : out std_logic;
+		error                   : out std_logic
 		);
 end component;
 
@@ -242,84 +319,135 @@ component FEE_slowcontrol_receive_from_cpu is
 		byte_write              : in std_logic;
 		byte_request            : in std_logic;
 		register_A              : out std_logic_vector (31 downto 0);
-		register_B              : out std_logic_vector (31 downto 0)
+		register_B              : out std_logic_vector (31 downto 0);
+		register_C              : out std_logic_vector (31 downto 0);
+		register_D              : out std_logic_vector (31 downto 0)
 		);
 end component;
 
 constant zeros                     : std_logic_vector(0 to NROFADCS/2-1) := (others => '0');
 signal ADCdata_S                   : array_adc_type;
 signal enable_high_S               : std_logic_vector(0 to NROFADCS/2-1);
-signal enable_low_S                : std_logic_vector(0 to NROFADCS/2-1);
-signal adcnumber_S                 : array_halfadc8bits_type;
+signal enable_low_S                : std_logic_vector(0 to NROFADCS/2-1);
+signal enable_rawdata_S            : std_logic_vector(0 to NROFADCS/2-1);
+
 signal pulsedata_allowed_S         : std_logic_vector(0 to NROFADCS/2-1);
 signal pulsedata_write_S           : std_logic_vector(0 to NROFADCS/2-1);
-signal pulsedata_almostfull_S      : std_logic_vector(0 to NROFADCS/2-1);
-signal pulsedata_out_S             : array_halfadc36bits_type;
+signal pulsedata_status_S          : array_halfadc8bits_type;
+signal pulsedata_lowgain_S         : std_logic_vector(0 to NROFADCS/2-1);
+signal pulsedata_superburst_S      : array_halfadc31bits_type;
+signal pulsedata_timestamp_S       : array_halfadc16bits_type;
+signal pulsedata_energy_S          : array_halfadc16bits_type;
+signal pulsedata_CFvalbefore_S     : array_halfadc16bits_type;
+signal pulsedata_CFvalafter_S      : array_halfadc16bits_type;
 signal pulsedata_inpipe_S          : std_logic;
-signal pileupdata_allowed_S        : std_logic_vector(0 to NROFADCS/2-1);
-signal pileupdata_write_S          : std_logic_vector(0 to NROFADCS/2-1);
-signal pileupdata_almostfull_S     : std_logic_vector(0 to NROFADCS/2-1);
-signal pileupdata_out_S            : array_halfadc36bits_type;
+signal pulsedata_error_S           : std_logic;
+signal wavedata_allowed_S          : std_logic_vector(0 to NROFADCS/2-1);
+signal wavedata_write_S            : std_logic_vector(0 to NROFADCS/2-1);
+signal wavedata_almostfull_S       : std_logic_vector(0 to NROFADCS/2-1);
+signal wavedata_moretocome_S       : std_logic_vector(0 to NROFADCS/2-1);
+signal wavedata_out_S              : array_halfadc36bits_type;
 signal overflow_S                  : std_logic_vector(0 to NROFADCS/2-1);
+signal errorarray_S                : std_logic_vector(0 to NROFADCS/2-1);
 signal pulsedata_available_S       : std_logic;
-signal pileupdata_available_S      : std_logic;
-signal pileupdata_inpipe_S         : std_logic;
+signal wavedata_available_S        : std_logic;
+signal wavedata_inpipe_S           : std_logic;
+signal wavedata_error_S            : std_logic;
+signal wavedata_output_S           : std_logic_vector(35 downto 0);
+signal reset_wavemux_S             : std_logic;
 
 signal pulsedetect_S               : std_logic_vector(0 to NROFADCS-1);
-signal pileupdata_output_S         : std_logic_vector(35 downto 0);
 
 signal register_A_S                : array_halfadc32bits_type := (others => (others => '0'));
 signal register_B_S                : array_halfadc32bits_type := (others => (others => '0'));
-
-signal dataerrors_S                : std_logic_vector(0 to NROFADCS/2-1);
-
-signal testword0_S                 : array_halfadc36bits_type;
-signal testword1_S                 : array_halfadc36bits_type;
-signal testword2_S                 : array_halfadc36bits_type;
-
+signal register_C_S                : array_halfadc32bits_type := (others => (others => '0'));
+signal register_D_S                : array_halfadc32bits_type := (others => (others => '0'));
+
+attribute mark_debug : string;
+-- attribute mark_debug of pulsedata_almostfull_S : signal is "true";
+-- attribute mark_debug of pulsedata_write_S : signal is "true";
+-- attribute mark_debug of wavedata_almostfull_S : signal is "true";
+-- attribute mark_debug of wavedata_moretocome_S : signal is "true";
+-- attribute mark_debug of wavedata_write_S : signal is "true";
+-- attribute mark_debug of pulsedata_error_S : signal is "true";
+-- attribute mark_debug of wavedata_error_S : signal is "true";
+-- attribute mark_debug of errorarray_S : signal is "true";
+-- attribute mark_debug of error : signal is "true";
 
 begin
 
+error <= '1' when (pulsedata_error_S='1') or (wavedata_error_S='1') or errorarray_S(0 to NROFADCS/2-1)/=zeros(0 to NROFADCS/2-1) else '0';
 
-	waves	: for index in 0 to NROFADCS/2-1 generate
+	FEs: for index in 0 to NROFADCS/2-1 generate
 	
 		FEE_slowcontrol_receive_from_cpu_all: FEE_slowcontrol_receive_from_cpu port map(
 				clock => clock,
 				reset => reset,
-				address => conv_std_logic_vector(index*2,8),
+				address => conv_std_logic_vector(index*NROFREGSPERCHANNEL,8),
 				byte_data => slowcontrol_byte_data,
 				byte_write => slowcontrol_byte_write,
 				byte_request => slowcontrol_byte_request,
 				register_A => register_A_S(index),
-				register_B => register_B_S(index));
+				register_B => register_B_S(index),
+				register_C => register_C_S(index),
+				register_D => register_D_S(index));
 
-		adcnumber_S(index) <= conv_std_logic_vector(index*2,8);
-		process(clock)
-		begin
-			if (rising_edge(clock)) then 
+--		process(clock)
+--		begin
+--			if (rising_edge(clock)) then 
 				enable_high_S(index) <= not register_A_S(index)(16);
-				enable_low_S(index) <= not register_A_S(index)(17);
-			end if;
-		end process;		
-		ADCdata_S(index*2) <= ADCdata(index*2);-- when enable_high_S(index)='1' else (others => '0');
-		ADCdata_S(index*2+1) <= ADCdata(index*2+1);-- when enable_low_S(index)='1' else (others => '0');
+				enable_low_S(index) <= not register_A_S(index)(17);
+				enable_rawdata_S(index) <= register_A_S(index)(30);
+--			end if;
+--		end process;		
+		ADCdata_S(index*2) <= ADCdata(index*2);
+		ADCdata_S(index*2+1) <= ADCdata(index*2+1);
 		
-		FEE_dual_pulse_waveform1: FEE_dual_pulse_waveform port map(
+		FEE_dual_pulse_waveform1: FEE_dual_pulse_waveform 
+		generic map(
+			ADCNUMBER => index*2,
+			ADCBITS => ADCBITS,
+			BASELINE_BWBITS => BASELINE_BWBITS,
+			MWD_WIDTHBITS => MWD_WIDTHBITS,
+			MWD_SCALEBITS => MWD_SCALEBITS,
+			MWD2_WIDTHBITS => MWD2_WIDTHBITS,
+			MWD2_SCALEBITS => MWD2_SCALEBITS,
+			MWD_DOUBLEFILTER => MWD_DOUBLEFILTER,
+			MWD_PU_DOUBLEFILTER => MWD_PU_DOUBLEFILTER,
+			WAVEFORMBUFFERSIZE => WAVEFORMBUFFERSIZE,
+			IDIVMAXBITS => IDIVMAXBITS,
+			INTEGRALRATIOBITS => INTEGRALRATIOBITS,
+			CF_DELAYBITS => CF_DELAYBITS,
+			MAXPILEUPHITS => MAXPILEUPHITS,
+			NOWAVEFORMS => NOWAVEFORMS
+			)
+		port map(
 			clock => clock,
 			reset => reset,
 			enable => enable_data,
-			adcnumber => adcnumber_S(index),
-			cf_delay => register_B_S(index)(29 downto 26),
+			enable_waveform => enable_waveform,
+			force_hit => force_hit,
+			cf_delay => register_B_S(index)(CF_DELAYBITS+25 downto 26),
+			CFpu_delay => register_B_S(index)(31 downto 30),
 			superburstnumber => superburstnumber,
-			timestampcounter => timestampcounter,
+			superburstupdate => superburstupdate,
 			ADCdata_highgain => ADCdata_S(index*2),
 			ADCdata_lowgain => ADCdata_S(index*2+1),
+			MWD1_width => register_C_S(index)(MWD_WIDTHBITS-1 downto 0),
+			MWD1_tau_factor => register_C_S(index)(MWD_SCALEBITS+15 downto 16),
+			MWD2_width => register_C_S(index)(MWD2_WIDTHBITS+7 downto 8),
+			MWD2_tau_factor => register_D_S(index)(MWD2_SCALEBITS-1 downto 0),
+			MWDpu1_width => register_C_S(index)(11 downto 10),
+			MWDpu1_tau_factor => register_C_S(index)(MWD_SCALEBITS+15 downto 16),
+			MWDpu2_width => register_C_S(index)(MWD2_WIDTHBITS+11 downto 12),
+			MWDpu2_tau_factor => register_D_S(index)(MWD2_SCALEBITS+15 downto 16),
 			threshold_highgain(7 downto 0) => register_A_S(index)(7 downto 0),
 			threshold_highgain((ADCBITS-1) downto 8) => (others => '0'),
 			threshold_lowgain(7 downto 0) => register_A_S(index)(15 downto 8),
 			threshold_lowgain((ADCBITS-1) downto 8) => (others => '0'),
 			enable_highgain => enable_high_S(index),
 			enable_lowgain => enable_low_S(index),
+			enable_rawdata => enable_rawdata_S(index),
 			IIRfilterBW => (others => '0'), 
 			maxabovebaseline => "1010", 
 			minpulselength => register_B_S(index)(7 downto 0),
@@ -329,232 +457,84 @@ begin
 			IdivMAX_pileup => register_A_S(index)(IDIVMAXBITS+23 downto 24),
 			fullsize_wave_highgain => register_B_S(index)(24),
 			fullsize_wave_lowgain => register_B_S(index)(25),
-			ADC_minus_baseline_highgain => open, -- testword0_S(idx)(14 downto 0),
-			ADC_minus_baseline_lowgain => open, -- testword0_S(idx)(30 downto 16),
 			pulsedata_allowed => pulsedata_allowed_S(index),
-			pulsedata_almostfull => pulsedata_almostfull_S(index),
 			pulsedata_write => pulsedata_write_S(index),
-			pulsedata_out => pulsedata_out_S(index),
-			pileupdata_allowed => pileupdata_allowed_S(index),
-			pileupdata_almostfull => pileupdata_almostfull_S(index),
-			pileupdata_write => pileupdata_write_S(index),
-			pileupdata_out => pileupdata_out_S(index),
+			pulsedata_lowgain => pulsedata_lowgain_S(index),
+			pulsedata_superburst => pulsedata_superburst_S(index),
+			pulsedata_timestamp => pulsedata_timestamp_S(index),
+			pulsedata_energy => pulsedata_energy_S(index),
+			pulsedata_CFvalbefore => pulsedata_CFvalbefore_S(index),
+			pulsedata_CFvalafter => pulsedata_CFvalafter_S(index),
+			pulsedata_status => pulsedata_status_S(index),
+			wavedata_allowed => '1', --// 21072015 wavedata_allowed_S(index),
+			wavedata_almostfull => wavedata_almostfull_S(index),
+			wavedata_available => wavedata_moretocome_S(index),
+			wavedata_write => wavedata_write_S(index),
+			wavedata_out => wavedata_out_S(index),
 			pulsedetect => pulsedetect_S(index),
 			overflow => overflow_S(index),
-			testword0 => testword0_S(index),
-			testword1 => testword1_S(index),
-			testword2 => testword2_S(index));
-
-process(clock)
-type array_halfadc4bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(3 downto 0);
-variable prev_data_V : array_halfadc4bits_type;
-begin
-	if rising_edge(clock) then
-		dataerrors_S(index) <= '0';
-		if pileupdata_write_S(index)='1' then
-			case pileupdata_out_S(index)(35 downto 32) is
-				when "0000" =>
-					if (prev_data_V(index)/="0100") and (prev_data_V(index)/="0101") then
-						dataerrors_S(index) <= '1';
-					end if;
-				when "0001" =>
-					if (prev_data_V(index)/="0000") then
-						dataerrors_S(index) <= '1';
-					end if;
-				when "0010" =>
-					if (prev_data_V(index)/="0001") and (prev_data_V(index)/="0010") then
-						dataerrors_S(index) <= '1';
-					end if;
-				when "0100" =>
-					if (prev_data_V(index)/="0010") then
-						dataerrors_S(index) <= '1';
-					end if;
-				when "0101" =>
-					if (prev_data_V(index)/="0010") then
-						dataerrors_S(index) <= '1';
-					end if;
-				when others =>
-					dataerrors_S(index) <= '1';
-			end case;
-			prev_data_V(index) := pileupdata_out_S(index)(35 downto 32);
-		end if;
-	end if;
-end process;
+			error => errorarray_S(index));
 
 	end generate;
 overflow <= '1' when overflow_S(0 to NROFADCS/2-1)/=zeros(0 to NROFADCS/2-1) else '0';
 pulsedetect_S(NROFADCS/2 to NROFADCS-1) <= (others => '0');
 pulsedetect <= pulsedetect_S;
-
+
 FEE_sorting_mux1: FEE_sorting_mux port map(
 		clock => clock,
 		reset => reset,
-		data_in => pulsedata_out_S,
+		superburstnumber => superburstnumber,
+		superburstupdate => superburstupdate,
+		data_in_status => pulsedata_status_S,
+		data_in_lowgain => pulsedata_lowgain_S,
+		data_in_superburst => pulsedata_superburst_S,
+		data_in_timestamp => pulsedata_timestamp_S,
+		data_in_energy => pulsedata_energy_S,
+		data_in_CFvalbefore => pulsedata_CFvalbefore_S,
+		data_in_CFvalafter => pulsedata_CFvalafter_S,
 		data_in_write => pulsedata_write_S,
 		data_in_allowed => pulsedata_allowed_S,
-		data_in_almostfull => pulsedata_almostfull_S,
-		data_out => pulsedata_out,
+		data_out_channel => pulsedata_channel,
+		data_out_status => pulsedata_status,
+		data_out_superburst => pulsedata_superburst,
+		data_out_timestamp => pulsedata_timestamp,
+		data_out_energy => pulsedata_energy,
+		data_out_CFvalbefore => pulsedata_CFvalbefore,	
+		data_out_CFvalafter => pulsedata_CFvalafter,
 		data_out_read => pulsedata_read,
 		data_out_available => pulsedata_available_S,
 		data_out_inpipe => pulsedata_inpipe_S,
-		error => open,
-		testword0 => open,
-		testword1 => open);
+		error => pulsedata_error_S);
 pulsedata_available <= pulsedata_available_S;
 pulsedata_inpipe <= pulsedata_inpipe_S;
-
--- FEE_sorting_wavemux_pileup: FEE_sorting_wavemux port map(
-FEE_sorting_wavemux1: FEE_sorting_wavemux port map(
-		clock => clock,
-		reset => reset,
-		data_in => pileupdata_out_S,
-		data_in_write => pileupdata_write_S,
-		data_in_allowed => pileupdata_allowed_S,
-		data_in_almostfull => pileupdata_almostfull_S,
-		data_out => pileupdata_output_S,
-		data_out_read => pileupdata_read,
-		data_out_available => pileupdata_available_S,
-		data_out_inpipe => pileupdata_inpipe_S,
-		error => open,
-		testword0 => open,
-		testword1 => open);
-pileupdata_available <= pileupdata_available_S;
-pileupdata_out <= pileupdata_output_S;
-pileupdata_inpipe <= pileupdata_inpipe_S;
-
-
-
---process(clock)
---type array_16_type is array(0 to NROFADCS/2-1) of std_logic_vector(15 downto 0);
---type array_8_type is array(0 to NROFADCS/2-1) of std_logic_vector(7 downto 0);
---variable l1 : line;
---variable l2 : line;
---variable c : std_logic_vector(63 downto 0) := x"0000000000000000";
---variable pulse_time_V : array_16_type;
---variable pulse_sb_V : array_16_type;
---variable pulse_energy_V : array_16_type;
---variable pulse_chan_V : array_8_type;
---variable wave_time_V : array_16_type;
---variable wave_sb_V : array_16_type;
---variable wave_chan_V : array_8_type;
---file file0: text;
---file file1: text;
---begin
---	if rising_edge(clock) then
---		if c=x"0000000000000000" then
---			file_open(file0,"D:\data\Panda\pulses.txt",WRITE_MODE);
---			file_open(file1,"D:\data\Panda\waves.txt",WRITE_MODE);
---		end if;
---		c := c+1;
---		for i in 0 to NROFADCS/2-1 loop
---			if pulsedata_write_S(i)='1' then
---				if pulsedata_out_S(i)(35 downto 34)="00" then
---					pulse_sb_V(i) := pulsedata_out_S(i)(31 downto 16);
---					pulse_time_V(i) := pulsedata_out_S(i)(15 downto 0);
---				elsif pulsedata_out_S(i)(35 downto 34)="01" then
---					pulse_chan_V(i) := pulsedata_out_S(i)(23 downto 16);
---					pulse_energy_V(i) := pulsedata_out_S(i)(15 downto 0);
---					hwrite(l1,c,right,16);		
---					write(l1," "); 
---					hwrite(l1,pulse_sb_V(i),right,4);		
---					write(l1," "); 
---					hwrite(l1,pulse_time_V(i),right,4);		
---					write(l1," "); 
---					hwrite(l1,pulse_chan_V(i),right,2);		
---					write(l1," "); 
---					hwrite(l1,pulse_energy_V(i),right,4);		
---					writeline(file0,l1); 
---				end if;
---			end if;
---			if pileupdata_write_S(i)='1' then
---				if pileupdata_out_S(i)(35 downto 32) ="0000" then
---					wave_sb_V(i) := pileupdata_out_S(i)(31 downto 16);
---					wave_time_V(i) := pileupdata_out_S(i)(15 downto 0);
---				elsif pileupdata_out_S(i)(35 downto 32) ="0001" then
---					wave_chan_V(i) := pileupdata_out_S(i)(7 downto 0);
---					hwrite(l2,c,right,16);		
---					write(l2," "); 
---					hwrite(l2,wave_sb_V(i),right,4);		
---					write(l2," "); 
---					hwrite(l2,wave_time_V(i),right,4);		
---					write(l2," "); 
---					hwrite(l2,wave_chan_V(i),right,2);		
---					writeline(file1,l2); 
---				end if;
---			end if;
---		end loop;
---	end if;
---end process;
-
-
-
-testword0(33 downto 0) <= testword0_S(testindex)(33 downto 0);
-testword0(35) <= testword0_S(testindex)(35);
-testword0(34) <= '1' when 
-	(testword0_S(0)(35)='1') or
-	(testword0_S(1)(35)='1') or
-	(testword0_S(2)(35)='1') or
-	(testword0_S(3)(35)='1') or
-	(testword0_S(4)(35)='1') or
-	(testword0_S(5)(35)='1') or
-	(testword0_S(6)(35)='1') or
-	(testword0_S(7)(35)='1') or
-	(testword0_S(8)(35)='1') or
-	(testword0_S(9)(35)='1') or
-	(testword0_S(10)(35)='1') or
-	(testword0_S(11)(35)='1') or
-	(testword0_S(12)(35)='1') or
-	(testword0_S(13)(35)='1') or
-	(testword0_S(14)(35)='1') or
-	(testword0_S(15)(35)='1') else '0';
-
-
-
-
-testword1(15 downto 0) <= testword1_S(0)(15 downto 0);
-testword1(31 downto 16) <= dataerrors_S;
-testword1(32) <= '1' when dataerrors_S/=x"0000";
-testword1(35) <= testword0_S(testindex)(28);
-testword1(34) <= '1' when 
-	(testword0_S(0)(35)='1') or
-	(testword0_S(1)(35)='1') or
-	(testword0_S(2)(35)='1') or
-	(testword0_S(3)(35)='1') or
-	(testword0_S(4)(35)='1') or
-	(testword0_S(5)(35)='1') or
-	(testword0_S(6)(35)='1') or
-	(testword0_S(7)(35)='1') or
-	(testword0_S(8)(35)='1') or
-	(testword0_S(9)(35)='1') or
-	(testword0_S(10)(35)='1') or
-	(testword0_S(11)(35)='1') or
-	(testword0_S(12)(35)='1') or
-	(testword0_S(13)(35)='1') or
-	(testword0_S(14)(35)='1') or
-	(testword0_S(15)(35)='1') else '0';
-	
-testword2(33 downto 0) <= testword2_S(testindex)(33 downto 0);
-testword2(35) <= testword0_S(testindex)(35);
-testword2(34) <= testword0_S(testindex)(28);
---testword2(34) <= '1' when 
---	(testword0_S(0)(35)='1') or
---	(testword0_S(1)(35)='1') or
---	(testword0_S(2)(35)='1') or
---	(testword0_S(3)(35)='1') or
---	(testword0_S(4)(35)='1') or
---	(testword0_S(5)(35)='1') or
---	(testword0_S(6)(35)='1') or
---	(testword0_S(7)(35)='1') or
---	(testword0_S(8)(35)='1') or
---	(testword0_S(9)(35)='1') or
---	(testword0_S(10)(35)='1') or
---	(testword0_S(11)(35)='1') or
---	(testword0_S(12)(35)='1') or
---	(testword0_S(13)(35)='1') or
---	(testword0_S(14)(35)='1') or
---	(testword0_S(15)(35)='1') else '0';
-
-	
+
+gen_waveforms: if NOWAVEFORMS=false generate
+	reset_wavemux_S <= '1' when (reset='1') or (enable_waveform='0') else '0';
+	FEE_sorting_wavemux1: FEE_sorting_wavemux port map(
+			clock => clock,
+			reset => reset_wavemux_S,
+			data_in => wavedata_out_S,
+			data_in_write => wavedata_write_S,
+			data_in_available => wavedata_moretocome_S,
+			data_in_allowed => wavedata_allowed_S,
+			data_in_almostfull => wavedata_almostfull_S,
+			data_out => wavedata_output_S,
+			data_out_read => wavedata_read,
+			data_out_available => wavedata_available_S,
+			data_out_inpipe => wavedata_inpipe_S,
+			error => wavedata_error_S);
+	wavedata_available <= wavedata_available_S;
+	wavedata_out <= wavedata_output_S;
+	wavedata_inpipe <= wavedata_inpipe_S;
+end generate;
+gen_nowaveforms: if NOWAVEFORMS=true generate
+	wavedata_allowed_S <= (others => '1');
+	wavedata_almostfull_S <= (others => '0');
+	wavedata_output_S <= (others => '0');
+	wavedata_available_S <= '0';
+	wavedata_inpipe_S <= '0';
+	wavedata_error_S <= '0';
+end generate;
 	
 end Behavioral;
 
diff --git a/FEE_ADC32board/FEE_modules/FEE_pulse_detect.vhd b/FEE_ADC32board/FEE_modules/FEE_pulse_detect.vhd
new file mode 100644
index 0000000..abe169e
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_pulse_detect.vhd
@@ -0,0 +1,158 @@
+----------------------------------------------------------------------------------
+-- Company: KVI-cart/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date:   15-02-2017
+-- Module Name:   FEE_pulse_detect
+-- Description: Checks and compares two pulselength's
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_pulse_detect
+--     Detect if ADC data contains a valid pulse. Comparing with threshold is done in other module.
+--     If the pulse-time is below an adjustable number of samples then the pulse is rejected.
+--     Also, the ADC samples are summated. The resulting integral determines the pulse energy.
+--     At the end of the pulse 1-clockcycle signals are generated for : valid pulse, pileup or cleanup
+--
+--
+--
+-- generics
+--     ADCDATABITS : number of ADC-bits
+--     INTEGRALBITS : number of scaling bits for integral (divide by 2^INTEGRALBITS)
+--		
+-- inputs
+--     clock : ADC sampling clock 
+--     reset : synchrounous reset
+--     ADCdata : signed ADC value, corrected for baseline
+--     pulse_active : high gain pulse active (signal above threshold)
+--     minpulselength : number of samples below which the pulse is ignored
+--			  
+-- outputs
+--     pulse_valid : high gain pulse data valid, and pulse not too long
+--     singlepulse : high gain pulse detected
+--     integral : high gain scaled integral output as value for the energy
+--
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_pulse_detect is
+	generic (
+		ADCDATABITS             : natural := 14;
+		INTEGRALBITS            : natural := 1
+		);
+   Port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		ADCdata                 : in std_logic_vector(ADCDATABITS downto 0); -- signed
+		pulse_active            : in std_logic;
+		minpulselength          : in std_logic_vector(4 downto 0);
+		pulse_valid             : out std_logic;
+		singlepulse             : out std_logic;
+		integral                : out std_logic_vector(15 downto 0)
+		);
+end FEE_pulse_detect;
+
+architecture Behavioral of FEE_pulse_detect is
+
+constant ZEROS                       : std_logic_vector(31 downto 0) := (others => '0');
+constant MAXWAVELENGTH               : std_logic_vector(4 downto 0) := (others => '1');
+
+signal pulse_tooshort_S              : std_logic := '0';
+signal pulse_toolong_S               : std_logic := '0';
+signal prev_pulseactive_S            : std_logic := '0';
+signal singlepulse_S                 : std_logic := '0';
+signal pulse_active_prev1_S          : std_logic := '0';
+signal pulse_active_prev2_S          : std_logic := '0';
+signal counter_S                     : std_logic_vector(4 downto 0);
+
+signal integral_S                    : integer range -2**(16+INTEGRALBITS) to 2**(16+INTEGRALBITS)-1;
+
+signal pulse_active_S                : std_logic := '0';
+signal pulse_busy_S                  : std_logic := '0';
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of ADCdata : signal is "true";
+
+begin
+
+integral <= (others => '0') when integral_S<0 else conv_std_logic_vector(integral_S,16+INTEGRALBITS)(16+INTEGRALBITS-1 downto INTEGRALBITS);
+
+process(clock)
+begin
+	if rising_edge(clock) then
+		if (reset='1') then
+			integral_S <= conv_integer(signed(ADCdata));
+		else
+			if ((pulse_active='0') and (pulse_active_prev1_S='0')) or
+				((pulse_active='1') and (pulse_active_prev1_S='0') and (pulse_active_prev2_S='1'))then
+				integral_S <= conv_integer(signed(ADCdata));
+			else
+				if integral_S+conv_integer(signed(ADCdata))>2**(16+INTEGRALBITS)-1 then
+					integral_S <= 2**(16+INTEGRALBITS)-1;
+				else
+					integral_S <= integral_S+conv_integer(signed(ADCdata));
+				end if;
+			end if;
+		end if;
+		pulse_active_prev2_S <= pulse_active_prev1_S;
+		pulse_active_prev1_S <= pulse_active;
+	end if;
+end process;
+
+
+pulse_tooshort_S <= '1' when (counter_S<minpulselength) else '0';
+
+singlepulse_S <= '1' 
+	when (((pulse_active='0') and (prev_pulseactive_S='1')) 
+		or ((pulse_active='0') and (counter_S=MAXWAVELENGTH) and (pulse_toolong_S='0')))
+		and ((pulse_toolong_S='0') and (pulse_tooshort_S='0'))
+	else '0';
+singlepulse <= singlepulse_S;
+
+pulse_valid <= '1' 
+	when (pulse_active_S='1') and (pulse_toolong_S='0')
+	else '0';
+
+pulse_active_S <= '1' 
+	when (pulse_active='1')
+	else '0';
+
+
+process(clock)
+begin
+	if rising_edge(clock) then
+--		if reset='1' then
+--			counter_S <= (others => '0');
+--			pulse_toolong_S <= '0';
+--			pulse_busy_S <= '0';
+--		else				
+			if (pulse_active_S='1') or (pulse_active='1') then
+				pulse_busy_S <= '1';
+				if counter_S<MAXWAVELENGTH then
+					counter_S <= counter_S+1;
+					pulse_toolong_S <= '0';
+				else
+					pulse_toolong_S <= '1';
+				end if;
+			else
+				pulse_busy_S <= '0';
+				pulse_toolong_S <= '0';
+				counter_S <= (others => '0');
+			end if;
+--		end if;
+		prev_pulseactive_S <= pulse_active;
+	end if;
+end process;
+
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_pulsewaveform_buffer.vhd b/FEE_ADC32board/FEE_modules/FEE_pulsewaveform_buffer.vhd
index e4d51f9..67d381e 100644
--- a/FEE_ADC32board/FEE_modules/FEE_pulsewaveform_buffer.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_pulsewaveform_buffer.vhd
@@ -1,5 +1,5 @@
 ----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
+-- Company:       KVI-cart/RUG/Groningen University
 -- Engineer:      Peter Schakel
 -- Create Date:   31-01-2012
 -- Module Name:   FEE_pulsewaveform_buffer
@@ -79,8 +79,7 @@ entity FEE_pulsewaveform_buffer is
 		data_out                : out std_logic_vector(35 downto 0);
 		data_out_read           : in std_logic;
 		data_out_available      : out std_logic;
-		overflow                : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
+		overflow                : out std_logic
 		);
 end FEE_pulsewaveform_buffer;
 
@@ -100,6 +99,19 @@ component blockmem is
 		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
 	);
 end component;
+
+COMPONENT blockmem_xilinx
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
+  );
+END COMPONENT;
+
 constant zeros                   : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto 0) := (others => '0');
 signal data_in_S                 : std_logic_vector(15 downto 0) := (others => '0');
 signal sample0_S                 : std_logic_vector(15 downto 0) := (others => '0');
@@ -115,10 +127,8 @@ signal read_address_S            : std_logic_vector(WAVEFORMBUFFERSIZE-1 downto
 signal read_data_S               : std_logic_vector(35 downto 0) := (others => '0');
 signal data_out_available_S      : std_logic := '0';
 signal pileup_detected_S         : std_logic := '0';
-signal pulse_rising_S            : std_logic := '0';
 signal prev_pulse_valid_S        : std_logic := '0';
 
-signal lastsample_even_S         : std_logic := '0';
 signal space_enough_S            : std_logic := '0';
 
 
@@ -144,18 +154,26 @@ begin
 		data_in_S(ADCBITS downto 0) <= data_in;
 		-- data_in_S(15 downto ADCBITS+1) <= (others => '0');
 		data_in_S(15) <= data_in_S(14);
-		pulse_rising_S <= pulse_rising;
 	end if;
 end process;
 
-blockmem1: blockmem port map(
-		clock => clock,
-		write_enable => write_enable_S,
-		write_address => write_address_S,
-		data_in => write_data_S,
-		read_address => read_address_S,
-		data_out => read_data_S);
+-- blockmem1: blockmem port map(
+		-- clock => clock,
+		-- write_enable => write_enable_S,
+		-- write_address => write_address_S,
+		-- data_in => write_data_S,
+		-- read_address => read_address_S,
+		-- data_out => read_data_S);
 data_out <= read_data_S;
+blockmem1: blockmem_xilinx port map(
+    clka => clock,
+    wea(0) => write_enable_S,
+    addra => write_address_S,
+    dina => write_data_S,
+    clkb => clock,
+    addrb => read_address_S,
+    doutb => read_data_S);
+
 
 write_data_S <= 
 	"1000" & superburst & timestamp when ((writemode_S=TIMESTAMP0) and (pileup_detected_S='1')) else	
@@ -180,7 +198,6 @@ begin
 			wavestart_address_S <= (others => '0');
 			nextstart_address_S <= (others => '0');
 			pileup_detected_S <= '0';
-			lastsample_even_S <= '0';
 			writemode_S <= ACQUIRE_EVEN;
 		else
 			prev_pulse_valid_S <= pulse_valid;
@@ -190,7 +207,6 @@ begin
 						pileup_detected_S <= '1';
 						write_address_S <= wavestart_address_S; -- for timestamp
 						nextstart_address_S <= write_address_S+1;
-						lastsample_even_S <= '1';
 						writemode_S <= TIMESTAMP0;
 					elsif (clear_waveform='1') or (pulse_detected='1') then
 						write_address_S <= wavestart_address_S+1;
@@ -213,7 +229,6 @@ begin
 						pileup_detected_S <= '1';
 						write_address_S <= wavestart_address_S; -- for timestamp
 						nextstart_address_S <= write_address_S+1;
-						lastsample_even_S <= '0';
 						writemode_S <= TIMESTAMP0;
 					elsif (clear_waveform='1') or (pulse_detected='1') then
 						write_address_S <= wavestart_address_S+1;
@@ -270,33 +285,7 @@ begin
 	end if;
 end process;
 
-
-
-testword0(1 downto 0) <= 
-	"00" when (writemode_S=ACQUIRE_EVEN) else
-	"01" when (writemode_S=ACQUIRE_ODD) else
-	"10" when (writemode_S=TIMESTAMP0) else
-	"11" when (writemode_S=SKIPPULSE) else
-	"11"; 
-
-testword0(2) <= space_enough_S;
-testword0(3) <= pulse_valid;
-testword0(4) <= pulse_detected;
-testword0(5) <= pileup_detected;
-testword0(6) <= clear_waveform;
-testword0(7) <= write_enable_S;
-testword0(15 downto 8) <= write_address_S(7 downto 0);
-testword0(19 downto 16) <= write_data_S(35 downto 32);
-
-
-testword0(27 downto 20) <= read_address_S(7 downto 0);
-testword0(31 downto 28) <= read_data_S(35 downto 32);
-testword0(32) <= data_out_read;
-testword0(33) <= data_out_available_S;
-testword0(34) <= '0';
-
-
-		
+	
 end Behavioral;
 
 
diff --git a/FEE_ADC32board/FEE_modules/FEE_receive_split.vhd b/FEE_ADC32board/FEE_modules/FEE_receive_split.vhd
new file mode 100644
index 0000000..e5a5b89
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_receive_split.vhd
@@ -0,0 +1,347 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   06-01-2017
+-- Module Name:   FEE_receive_split
+-- Description:   Split commands/data from fiber to 2 data streams
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_receive_split
+-- Split commands/data from fiber to 2 data streams.
+-- Addresses 0..FEESLOWCONTROLBOARDADDRESS-1 are passed on to local FEE
+-- Addresses FEESLOWCONTROLBOARDADDRESS..2*FEESLOWCONTROLBOARDADDRESS-1 are passed on to the remote FE
+-- Addresses 2*FEESLOWCONTROLBOARDADDRESS and beyound are passed on to both FE
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+--   0x5C address(7..0) replybit 0000000 data(31..24)
+--   data(23..0) CRC8(7..0)
+--
+--
+-- 
+-- Library
+--     work.panda_package :  for type declarations and constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--    clock_in : clock for input data
+--    clock_local : clock for data to local FE
+--    clock_remote : clock for data to remote FE
+--    reset : reset all
+--    GEO :  which FPGA on the board, 0:this is FPGA1, 1:this is FPGA2
+--    data_in : 32 bits data input from fiber module
+--    data_in_first : first 32 bits data in packet from fiber module
+--    data_in_last : last 32 bits data in packet from fiber module
+--    data_in_present : data available from fiber module or data write in case of GEO='1'
+--    data_in_fifofull : fifo for local data is full
+--    data_local_read : read for data to local FE
+--    data_remote_read : read for data to remote FE
+-- 
+-- Outputs:
+--    data_in_read : read signal to fiber module to read next data
+--    data_local : packet data to local FE
+--    data_local_first : first 32 bits word in packet to local FE
+--    data_local_last : last 32 bits word in packet to local FE
+--    data_local_present : data available in fifo to local FE
+--    data_remote : packet data to remote FE
+--    data_remote_first : first 32 bits word in packet to local FE
+--    data_ermote_last : last 32 bits word in packet to local FE
+--    data_remote_present : data available in fifo to remote FE
+--    error : error in data or data loss
+--
+-- Components:
+--    async_fifo_256x32 : asynchronous fifo for local and remote data
+-- 
+----------------------------------------------------------------------------------
+
+entity FEE_receive_split is
+	port ( 
+		clock_in                : in std_logic;
+		clock_local             : in std_logic;
+		clock_remote            : in std_logic;
+		reset                   : in std_logic;
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+		data_in                 : in std_logic_vector (31 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_present         : in std_logic;
+		data_in_fifofull        : out std_logic;
+		data_in_read            : out std_logic;
+		data_local              : out std_logic_vector(31 downto 0);
+		data_local_first        : out std_logic;
+		data_local_last         : out std_logic;
+		data_local_present      : out std_logic;
+		data_local_read         : in std_logic;
+		data_remote             : out std_logic_vector(31 downto 0);
+		data_remote_first       : out std_logic;
+		data_remote_last        : out std_logic;
+		data_remote_present     : out std_logic;
+		data_remote_read        : in std_logic;
+		error                   : out std_logic
+		);
+end FEE_receive_split;
+
+architecture Behavioral of FEE_receive_split is
+
+component async_fifo_256x32
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(31 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(31 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+
+signal data_in_read_S                   : std_logic;
+signal fifo_local_data_in_S             : std_logic_vector(31 downto 0);
+signal fifo_remote_data_in_S            : std_logic_vector(31 downto 0);
+signal fifo_local_write_S               : std_logic;
+signal fifo_remote_write_S              : std_logic;
+signal retry_local_write_S              : std_logic := '0';
+signal retry_remote_write_S             : std_logic := '0';
+signal valid_address_local_S            : std_logic;
+signal valid_address_remote_S           : std_logic;
+signal valid_data_local_S               : std_logic := '0';
+signal valid_data_remote_S              : std_logic := '0';
+signal fifo_local_full_S                : std_logic;
+signal fifo_remote_full_S               : std_logic;
+signal fifo_local_empty_S               : std_logic;
+signal fifo_remote_empty_S              : std_logic;
+signal data_in_read_aftr1clk_S          : std_logic := '0';
+signal secondwordphase_S                : std_logic := '0';
+signal error_S                          : std_logic;
+signal timeoutcnt_S                     : std_logic_vector(5 downto 0) := (others => '0');
+
+signal data_local_present_S             : std_logic;
+signal data_local_S                     : std_logic_vector(31 downto 0);
+signal data_local_read_S                : std_logic;
+signal data_local_read_aftr1clk_S       : std_logic;
+signal local_phase_S                    : std_logic;
+signal data_remote_present_S            : std_logic;
+signal data_remote_S                    : std_logic_vector(31 downto 0);
+signal data_remote_read_S               : std_logic;
+signal data_remote_read_aftr1clk_S      : std_logic;
+signal remote_phase_S                   : std_logic;
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of data_in_read_S : signal is "true";
+-- attribute mark_debug of fifo_local_full_S : signal is "true";
+-- attribute mark_debug of fifo_remote_full_S : signal is "true";
+-- attribute mark_debug of GEO : signal is "true";
+-- attribute mark_debug of data_in : signal is "true";
+-- attribute mark_debug of data_in_first : signal is "true";
+-- attribute mark_debug of data_in_last : signal is "true";
+-- attribute mark_debug of data_in_present : signal is "true";
+-- attribute mark_debug of data_in_fifofull : signal is "true";
+-- attribute mark_debug of data_in_read : signal is "true";
+-- attribute mark_debug of data_local : signal is "true";
+-- attribute mark_debug of data_local_first : signal is "true";
+-- attribute mark_debug of data_local_last : signal is "true";
+-- attribute mark_debug of data_local_present : signal is "true";
+-- attribute mark_debug of data_local_read : signal is "true";
+-- attribute mark_debug of data_remote : signal is "true";
+-- attribute mark_debug of data_remote_first : signal is "true";
+-- attribute mark_debug of data_remote_last : signal is "true";
+-- attribute mark_debug of data_remote_present : signal is "true";
+-- attribute mark_debug of data_remote_read : signal is "true";
+-- attribute mark_debug of error : signal is "true";
+
+
+begin
+
+error <= error_S;
+data_in_fifofull <= fifo_local_full_S;
+data_local_read_S <= data_local_read;
+data_local <= data_local_S;
+data_local_present <= data_local_present_S;
+data_local_first <= '1' when (data_local_read_aftr1clk_S='1') and (local_phase_S='0') else '0';
+data_local_last <= '1' when (data_local_read_aftr1clk_S='1') and (local_phase_S='1') else '0';
+process(clock_local)
+begin
+	if (rising_edge(clock_local)) then
+		if (data_local_read_aftr1clk_S='1') then
+			if local_phase_S='0' then
+				if data_local_S(31 downto 24)=x"5C" then
+					local_phase_S <= '1';
+				end if;
+			else
+				local_phase_S <= '0';
+			end if;
+		end if;
+		data_local_read_aftr1clk_S <= data_local_read_S;
+	end if;
+end process;
+
+data_remote_read_S <= data_remote_read or GEO;
+data_remote <= data_remote_S;
+data_remote_present <= data_remote_present_S;
+data_remote_first <= '1' when (data_remote_read_aftr1clk_S='1') and (remote_phase_S='0') else '0';
+data_remote_last <= '1' when (data_remote_read_aftr1clk_S='1') and (remote_phase_S='1') else '0';
+process(clock_remote)
+begin
+	if (rising_edge(clock_remote)) then
+		if (data_remote_read_aftr1clk_S='1') then
+			if remote_phase_S='0' then
+				if data_remote_S(31 downto 24)=x"5C" then
+					remote_phase_S <= '1';
+				end if;
+			else
+				remote_phase_S <= '0';
+			end if;
+		end if;
+		data_remote_read_aftr1clk_S <= data_remote_read_S;
+	end if;
+end process;
+		
+fifo_local: async_fifo_256x32 port map(
+		rst => reset,
+		wr_clk => clock_in,
+		rd_clk => clock_local,
+		din => fifo_local_data_in_S,
+		wr_en => fifo_local_write_S,
+		rd_en => data_local_read_S,
+		dout => data_local_S,
+		full => fifo_local_full_S,
+		empty => fifo_local_empty_S);
+data_local_present_S <= '1' when fifo_local_empty_S='0' else '0';
+		
+fifo_remote: async_fifo_256x32 port map(
+		rst => reset,
+		wr_clk => clock_in,
+		rd_clk => clock_remote,
+		din => fifo_remote_data_in_S,
+		wr_en => fifo_remote_write_S,
+		rd_en => data_remote_read_S,
+		dout => data_remote_S,
+		full => fifo_remote_full_S,
+		empty => fifo_remote_empty_S);
+data_remote_present_S <= '1' when fifo_remote_empty_S='0' else '0';
+		
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+--   0x5C address(7..0) replybit 0000000 data(31..24)
+--   data(23..0) CRC8(7..0)
+
+
+
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when (data_in_present='1') and (fifo_local_full_S='0') and (fifo_remote_full_S='0') and (GEO='0') else '0';
+
+fifo_local_data_in_S <= data_in;
+fifo_remote_data_in_S <= data_in;
+
+valid_address_local_S <= '1' when (data_in(31 downto 24)=x"5C") and  -- (data_in_first='1') and 
+	((conv_integer(unsigned(data_in(23 downto 16)))<FEESLOWCONTROLBOARDADDRESS/2) or
+	 (conv_integer(unsigned(data_in(23 downto 16)))>=FEESLOWCONTROLBOARDADDRESS) or
+	 (GEO='1')) else '0';
+valid_address_remote_S <= '1' when (data_in(31 downto 24)=x"5C") and (GEO='0') and -- (data_in_first='1') and 
+	(conv_integer(unsigned(data_in(23 downto 16)))>=FEESLOWCONTROLBOARDADDRESS/2) else '0';
+
+fifo_local_write_S <= data_in_present when GEO='1'
+	else '1' when 
+		((data_in_read_aftr1clk_S='1') or (retry_local_write_S='1')) and
+		(((secondwordphase_S='0') and (valid_address_local_S='1')) or 
+		((secondwordphase_S='1') and (valid_data_local_S='1'))) 
+	else '0';
+fifo_remote_write_S <= '1' when 
+	((data_in_read_aftr1clk_S='1') or (retry_remote_write_S='1')) and
+	(((secondwordphase_S='0') and (valid_address_remote_S='1')) or 
+	((secondwordphase_S='1') and (valid_data_remote_S='1'))) 
+	else '0';
+
+process(clock_in)
+begin
+	if (rising_edge(clock_in)) then 
+		retry_local_write_S <= '0';
+		retry_remote_write_S <= '0';
+		error_S <= '0';
+		if reset='1' then
+			timeoutcnt_S <= (others => '0');
+			secondwordphase_S <= '0';
+			valid_data_local_S <= '0';
+			valid_data_remote_S <= '0';
+		else
+			if (retry_local_write_S='1') and (fifo_local_write_S='1') and (fifo_local_full_S='1') then
+				retry_local_write_S <= '1';
+			end if;
+			if (retry_remote_write_S='1') and (fifo_remote_write_S='1') and (fifo_remote_full_S='1') then
+				retry_remote_write_S <= '1';
+			end if;
+			if data_in_read_aftr1clk_S='1' then
+				timeoutcnt_S <= (others => '0');
+				if secondwordphase_S='0' then
+					if (valid_address_local_S='1') then
+						valid_data_local_S <= '1';
+						if (fifo_local_full_S='1') then
+							retry_local_write_S <= '1';
+						end if;
+					else
+						valid_data_local_S <= '0';
+					end if;
+					if (valid_address_remote_S='1') then
+						valid_data_remote_S <= '1';
+						if (fifo_remote_full_S='1') then
+							retry_remote_write_S <= '1';
+						end if;
+					else 
+						valid_data_remote_S <= '0';
+					end if;
+					if (valid_address_local_S='0') and (valid_address_remote_S='0') then
+						error_S <= '1';
+						secondwordphase_S <= '0';
+						valid_data_local_S <= '0';
+						valid_data_remote_S <= '0';
+					else 
+						secondwordphase_S <= '1';
+					end if;
+				else
+					secondwordphase_S <= '0';
+					if (valid_data_local_S='1') then
+						if (fifo_local_full_S='1') then
+							retry_local_write_S <= '1';
+						else
+							valid_data_local_S <= '0';
+						end if;
+					end if;
+					if (valid_data_remote_S='1') then
+						if (fifo_remote_full_S='1') then
+							retry_remote_write_S <= '1';
+						else
+							valid_data_remote_S <= '0';
+						end if;
+					end if;
+				end if;
+			else
+				if (secondwordphase_S='1') and (fifo_local_full_S='0') and (fifo_remote_full_S='1') then
+					if timeoutcnt_S(timeoutcnt_S'left)='1' then
+						error_S <= '1';
+						timeoutcnt_S <= (others => '0');
+						secondwordphase_S <= '0';
+						valid_data_local_S <= '0';
+						valid_data_remote_S <= '0';
+					else
+						timeoutcnt_S <= timeoutcnt_S+1;
+					end if;
+				end if;
+			end if;
+		end if;
+		data_in_read_aftr1clk_S <= data_in_read_S;
+	end if;
+end process;
+	 
+		
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_slowcontrol_packet_receiver.vhd b/FEE_ADC32board/FEE_modules/FEE_slowcontrol_packet_receiver.vhd
index 3584b1f..2c990ed 100644
--- a/FEE_ADC32board/FEE_modules/FEE_slowcontrol_packet_receiver.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_slowcontrol_packet_receiver.vhd
@@ -8,12 +8,14 @@
 --   12-09-2014   New dataformat, name changed to FEE_slowcontrol_packet_receiver
 --   22-09-2014   single clock
 --   10-10-2014   bug with high rate of slow-control commands solved 
+--   18-01-2017   bug with high rate of slow-control commands solved 
 ----------------------------------------------------------------------------------
 
 library IEEE;
 use IEEE.std_logic_1164.ALL;
 USE ieee.std_logic_unsigned.all ;
 USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
 
 ----------------------------------------------------------------------------------
 -- FEE_slowcontrol_packet_receiver
@@ -89,7 +91,7 @@ end component;
 
 component sync_fifo_512x41
 	port (
-		rst                     : in std_logic;
+		srst                    : in std_logic;
 		clk                     : in std_logic;
 		din                     : in std_logic_vector(40 downto 0);
 		wr_en                   : in std_logic;
@@ -136,11 +138,20 @@ signal slowcontrol_dataout_S        : std_logic_vector (31 downto 0);
 signal sfifo_in_S                   : std_logic_vector (40 downto 0);
 signal sfifo_out_S                  : std_logic_vector (40 downto 0);
 signal sfifo_full_S                 : std_logic := '0';
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of crc8_slowerror_S : signal is "true";
+-- attribute mark_debug of error_S : signal is "true";
+-- attribute mark_debug of overflow : signal is "true";
+-- attribute mark_debug of slowcontrol_write_S : signal is "true";
+-- attribute mark_debug of sfifo_full_S : signal is "true";
+-- attribute mark_debug of packet_data_valid_S : signal is "true";
 
 begin
 
 data_error <= '1' when (crc8_slowerror_S='1') or (error_S='1')  else '0';
-overflow <= '1' when ((slowcontrol_write_S='1') and (sfifo_full_S='1')) else '0';
+overflow <= '1' when ((slowcontrol_write_S='1') and (sfifo_full_S='1')) 
+or (crc8_slowerror_S='1') or (error_S='1') else '0';
 
 packet_data_read <= packet_data_read_S;
 packet_data_read_S <= '1' when 
@@ -191,7 +202,16 @@ begin
 					else
 						if packet_data_valid_S='1' then
 							if packet_data_in(31 downto 24)=x"5C" then -- slowcontrol
-								slowcontrol_address_S <= packet_data_in(23 downto 16);
+								if NROFFEEFPGAS=1 then
+									slowcontrol_address_S <= packet_data_in(23 downto 16);
+								else -- map all ADC channel addresses to base region
+									if (conv_integer(unsigned(packet_data_in(23 downto 16)))>=FEESLOWCONTROLBOARDADDRESS/2) and 
+										(conv_integer(unsigned(packet_data_in(23 downto 16)))<FEESLOWCONTROLBOARDADDRESS) then
+										slowcontrol_address_S <= packet_data_in(23 downto 16)-conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS/2,8);
+									else
+										slowcontrol_address_S <= packet_data_in(23 downto 16);
+									end if;
+								end if;
 								slowcontrol_request_S <= packet_data_in(15);
 								slowcontrol_data_S(31 downto 24) <= packet_data_in(7 downto 0);
 								error_S <= '0';
@@ -227,12 +247,12 @@ slowcontrolpackethandling: process(clock)
 begin
 	if rising_edge(clock) then
 		if reset='1' then
-			slowcontrol_write_S <= '0';
+--			slowcontrol_write_S <= '0';
 			slowpacketvalid_S <= '0';
 			crc8_slowerror_S <= '0';
 		else
 			if slowpacketvalid_S='0' then
-				slowcontrol_write_S <= '0';
+--				slowcontrol_write_S <= '0';
 				crc8_slowerror_S <= '0';
 				if (rec_state_S=slow1) and (packet_data_valid_S='1') and (enable_S='1') then
 					slowpacketvalid_S <= '1';			
@@ -240,10 +260,10 @@ begin
 			else
 				slowpacketvalid_S <= '0';
 				if (crc8_data_out_valid_S='1') and (crc8_data_out_last_S='1') and (crc8_error_S='0') then -- everything ok
-					slowcontrol_write_S <= enable_S;
+--					slowcontrol_write_S <= enable_S;
 					crc8_slowerror_S <= '0';
 				else
-					slowcontrol_write_S <= '0';
+--					slowcontrol_write_S <= '0';
 					crc8_slowerror_S <= enable_S;
 				end if;
 			end if;
@@ -251,12 +271,14 @@ begin
 	end if;
 end process slowcontrolpackethandling;
 
+slowcontrol_write_S <= '1' when (slowpacketvalid_S='1') and (crc8_data_out_valid_S='1') and (crc8_data_out_last_S='1') and (crc8_error_S='0') and (enable_S='1') else '0';
+
 sfifo_in_S(31 downto 0) <= slowcontrol_data_S;
 sfifo_in_S(39 downto 32) <= slowcontrol_address_S;
 sfifo_in_S(40) <= slowcontrol_request_S;
 
 sfifo: sync_fifo_512x41 port map(
-		rst => reset,
+		srst => reset,
 		clk => clock,
 		din => sfifo_in_S,
 		wr_en =>  slowcontrol_write_S,
diff --git a/FEE_ADC32board/FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd b/FEE_ADC32board/FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd
index 9fb82b4..a9bb4c3 100644
--- a/FEE_ADC32board/FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd
@@ -1,5 +1,5 @@
 ---------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
+-- Company:       KVI-cart/RUG/Groningen University
 -- Engineer:      Peter Schakel
 -- Create Date:   21-03-2011
 -- Module Name:   FEE_slowcontrol_receive_from_cpu
@@ -8,6 +8,7 @@
 --   12-09-2014   Reduce nrof Registers to 2, replaced channel by address 
 --   22-09-2014   single clock
 --   08-10-2014   error signal removed
+--   23-02-2017   back to 4 registers again
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -31,7 +32,7 @@ USE ieee.std_logic_arith.all ;
 --     reset : synchronous reset 
 --     address : base-address of channel
 --     byte_data : 8-bits slowcontrol data:
---                 Byte0 : bit7..4=index of the channel bit3..2=index of register
+--                 Byte0 : bit7..2=index of the channel bit1..0=index of register
 --                 Byte1,2,3,4 : 32-bits data, MSB first
 --     byte_write : write signal for byte-data, only selected channel (with index in first byte equals channel) should read
 --     byte_request : request signal for reading data, here only used for check and synchronization
@@ -39,6 +40,8 @@ USE ieee.std_logic_arith.all ;
 -- Outputs:
 --     register_A : 32-bits output register A
 --     register_B : 32-bits output register B
+--     register_C : 32-bits output register C
+--     register_D : 32-bits output register D
 -- 
 -- Components:
 --
@@ -53,7 +56,9 @@ entity FEE_slowcontrol_receive_from_cpu is
 		byte_write              : in std_logic;
 		byte_request            : in std_logic;
 		register_A              : out std_logic_vector (31 downto 0);
-		register_B              : out std_logic_vector (31 downto 0)
+		register_B              : out std_logic_vector (31 downto 0);
+		register_C              : out std_logic_vector (31 downto 0);
+		register_D              : out std_logic_vector (31 downto 0)
 		);
 end FEE_slowcontrol_receive_from_cpu;
 
@@ -63,29 +68,47 @@ architecture Behavioral of FEE_slowcontrol_receive_from_cpu is
 signal byte_idx_S             : integer range 0 to 4 := 0;
 signal selected_S             : std_logic := '0';
 signal register_buf_S         : std_logic_vector(31 downto 8);
-signal selected_reg_S         : std_logic_vector(0 downto 0);
+signal selected_reg_S         : std_logic_vector(1 downto 0);
 
-signal register_A_S           : std_logic_vector (31 downto 0) := x"12183264"; -- default FEE
-signal register_B_S           : std_logic_vector (31 downto 0) := x"0C643208"; -- default FEE
+signal register_A_S           : std_logic_vector (31 downto 0) := x"28043264"; -- x"12183264"; -- default FEE
+signal register_B_S           : std_logic_vector (31 downto 0) := x"4C64140a"; -- x"4C641C05"; -- default FEE
+signal register_C_S           : std_logic_vector (31 downto 0) := x"1B72020A"; -- default FEE
+signal register_D_S           : std_logic_vector (31 downto 0) := x"00000000"; -- default FEE
+
+--       board_register A: write
+--         register_A(7..0) = threshold High
+--         register_A(15..8) = threshold Low
+--         register_A(16) = disable High
+--         register_A(17) = disable Low
+--         register_A(23..18) = I/Max discard
+--         register_A(29..24) = I/Max pileup
+--         register_A(30) = enable raw data in waveform instead of baseline corrected data
+--       board_register B: write
+--         register_B(7..0) = minimum pulselength
+--         register_B(15..8) = pileup length
+--         register_B(23..16) = maximum wavelength
+--         register_B(24) = fullsize High
+--         register_B(25) = fullsize Low
+--         register_B(29..26) = CF delay
+--         register_B(31..30) = CF delay Pileup
+--      board_register C: write
+--         register_C(4..0) = MWD1_width
+--         register_C(9..8) = MWD2_width 
+--         register_C(11..10) = MWDpu1_width
+--         register_C(13..12) = MWDpu2_width
+--         register_C(31..16) = MWD1_tau_factor , MWD2_tau_factor
+--      board_register D: write
+--         register_D(15..0) = MWDpu1_tau_factor
+--         register_D(31..16) = MWDpu2_tau_factor
 
--- register_A(7..0) = threshold High
--- register_A(15..8) = threshold Low
--- register_A(16) = disable High
--- register_A(17) = disable Low
--- register_A(23..18) = I/Max discard
--- register_A(29..24) = I/Max pileup
--- register_B(7..0) = minimum pulselength
--- register_B(15..8) = pileup length
--- register_B(23..16) = maximum wavelength
--- register_B(24) = fullsize High
--- register_B(25) = fullsize Low
--- register_B(29..26) = CF delay
 
 
 begin
 
 register_A <= register_A_S;
-register_B <= register_B_S;
+register_B <= register_B_S;
+register_C <= register_C_S;
+register_D <= register_D_S;
 
 
 rd_process: process(clock)
@@ -97,9 +120,9 @@ begin
 		else
 			if byte_idx_S=0 then
 				if (byte_write='1') then
-					if (byte_data(7 downto 1)=address(7 downto 1)) then
+					if (byte_data(7 downto 2)=address(7 downto 2)) then
 						selected_S <= '1';
-						selected_reg_S <= byte_data(0 downto 0);
+						selected_reg_S <= byte_data(1 downto 0);
 					else
 						selected_S <= '0';
 					end if;
@@ -121,8 +144,10 @@ begin
 							register_buf_S(15 downto 8) <= byte_data;
 						when 4 => 
 							case selected_reg_S is 
-								when "0" => register_A_S <= register_buf_S(31 downto 8) & byte_data;
-								when "1" => register_B_S <= register_buf_S(31 downto 8) & byte_data;
+								when "00" => register_A_S <= register_buf_S(31 downto 8) & byte_data;
+								when "01" => register_B_S <= register_buf_S(31 downto 8) & byte_data;
+								when "10" => register_C_S <= register_buf_S(31 downto 8) & byte_data;
+								when "11" => register_D_S <= register_buf_S(31 downto 8) & byte_data;
 								when others =>
 							end case;
 						when others =>
diff --git a/FEE_ADC32board/FEE_modules/FEE_sorting_mux.vhd b/FEE_ADC32board/FEE_modules/FEE_sorting_mux.vhd
index 047a47e..b0ab20e 100644
--- a/FEE_ADC32board/FEE_modules/FEE_sorting_mux.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_sorting_mux.vhd
@@ -1,5 +1,5 @@
 ----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
+-- Company:       KVI-cart/RUG/Groningen University
 -- Engineer:      Peter Schakel
 -- Create Date:   05-03-2012
 -- Module Name:   FEE_sorting_mux
@@ -8,6 +8,11 @@
 --    22-09-2014: single clock
 --    11-10-2014: adc-channel number 8 bits
 --    16-10-2014: inpipe check
+--    21-07-2015: data_out_inpipe clocked
+--    13-10-2015: time difference between channel checked with fifo counts
+--    05-11-2015: time difference between fifo  input and output 
+--    04-19-2016: additional check on recent read from input fifo 
+--    21-02-2017: rewritten to parallel in/out instead of 36bits words
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -18,381 +23,451 @@ USE work.panda_package.all;
 
 ----------------------------------------------------------------------------------
 -- FEE_sorting_mux
--- Multiplexes multiple input pulse data stream with waveform data to one stream.
--- Both consists of packets of 36-bits words: 32 bits data and 4 bits for index/check
--- The data is sorted based on the 32-bits timestamp.
--- This sorting is done by comparing the time of 2 waveforms; the first in time is passed on.
+-- Multiplexes multiple input pulse data stream to one stream.
+-- The input contains hit data: channelnumber, superburstnumber, time within superburst, Constant Fraction method: sample before and after, energy and status.
+-- The data is sorted based on the superburst number, the 16-bits timestamp within the superburst and the fractional part.
+-- This sorting is done by comparing the time of 2 items; the first in time is passed on.
 -- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.
 --
 -- Library:
 --     work.panda_package: constants and types
 --
 -- Generics:
---     NROFMUXINPUTS : number of input-channels
+--     NROFMUXINPUTS : number of input-channels
 --
 -- Inputs:
---     inputclock : clock for input data (write side incomming fifo)
---     MUXclock : clock for multiplexer part, between the fifos
---     outputclock : clock for output data (read side outgoing fifo)
+--     clock : clock for input data (write side incomming fifo)
 --     reset : reset, must be long enough for all clocks
---     data_in : array of input data streams, structure of each (three 36-bits words):
---        	bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
---        	bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
---        	bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
+--     superburstnumber : actual superburstnumber that is sent by SODA
+--     superburstupdate : new superburstnumber issued by SODA
+--     data_in_status : status-byte, for each connected FEE
+--     data_in_lowgain : high or low gain channel, for each connected FEE
+--     data_in_superburst : superburstnumber, for each connected FEE
+--     data_in_timestamp : time within superburst, for each connected FEE
+--     data_in_energy : energy of the hit, for each connected FEE
+--     data_in_CFvalbefore : Constant Fraction result: sample before zero-crossing, for each connected FEE
+--     data_in_CFvalafter : Constant Fraction result: sample after zero-crossing, for each connected FEE
 --     data_in_write : write signal for data_in (write into fifo)
 --     data_out_read : read signal for outgoing data (read from fifo)
 -- 
 -- Outputs:
 --     data_in_allowed : write to input data allowed (not full)
---     data_in_almostfull : input fifo is too full for maximum length waveform
---     data_out : output data (three 36-bits words):
---        	bits(35..34)="00" : bit(33)=low_gain channel, bit(32)=pulse skipped, bits(31..16)=superburst, bits(15..0)=timestamp
---        	bits(35..34)="01" : bits(23..16)=channels(7 downto 0), bits(15..0)=energy
---        	bits(35..34)="10" : bits(31..16)=CF sample before zero crossing, bits(15..0)=CF sample after zero crossing
---     data_out_available : data_out available (output fifo not empty)
+--     data_out_channel : pulse-data : adc channel number
+--     data_out_status : pulse-data : status
+--     data_out_superburst : pulse-data : superburstnumber
+--     data_out_timestamp : pulse-data : time (ADC-clock)
+--     data_out_energy : pulse-data : energy
+--     data_out_CFvalbefore : pulse-data : Constant Fraction result: sample before zero-crossing
+--     data_out_CFvalafter : pulse-data : Constant Fraction result: sample after zero-crossing
+--     data_out_available : data_out available (output fifo not empty)
 --     data_out_inpipe : more data on its way
 --     error : data error, index in data words incorrect
 -- 
--- Components:
---     FEE_mux_readfifo : read data from fifo and writes to next level
---     FEE_mux2to1 : compares the data and passes the first in time on
---     sync_fifo_progfull504_progempty128_512x36 : synchronous fifo with programmable full and empty
---     sync_fifo_FWFT_512x36 : synchronous fifo with First Word Fall Through
---
+-- Components:
+--     FEE_mux2to1 : compares the data and passes the first in time on
+--     sync_fifo_progempty32_FWFT_512x104 : synchronous fifo for input data
+--     sync_fifo_512x111 : synchronous fifo for output data
 --
 --
 ----------------------------------------------------------------------------------
 
 entity FEE_sorting_mux is
 	generic(
-		NROFMUXINPUTS           : natural := 8
+		NROFMUXINPUTS           : natural := 16
 	);
-    Port ( 
+    port ( 
 		clock                   : in std_logic;
 		reset                   : in std_logic;
-		data_in                 : in array_halfadc36bits_type;
+		superburstnumber        : in std_logic_vector(30 downto 0);		
+		superburstupdate        : in std_logic;
+		data_in_status          : in array_halfadc8bits_type;
+		data_in_lowgain         : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_superburst      : in array_halfadc31bits_type;
+		data_in_timestamp       : in array_halfadc16bits_type;
+		data_in_energy          : in array_halfadc16bits_type;
+		data_in_CFvalbefore     : in array_halfadc16bits_type;		
+		data_in_CFvalafter      : in array_halfadc16bits_type;		
 		data_in_write           : in std_logic_vector(0 to NROFMUXINPUTS-1);
 		data_in_allowed         : out std_logic_vector(0 to NROFMUXINPUTS-1);
-		data_in_almostfull      : out std_logic_vector(0 to NROFMUXINPUTS-1);
-		data_out                : out std_logic_vector(35 downto 0);
+		data_out_channel        : out std_logic_vector(7 downto 0);
+		data_out_status         : out std_logic_vector(7 downto 0);
+		data_out_superburst     : out std_logic_vector(30 downto 0);
+		data_out_timestamp      : out std_logic_vector(15 downto 0);
+		data_out_energy         : out std_logic_vector(15 downto 0);
+		data_out_CFvalbefore    : out std_logic_vector(15 downto 0);		
+		data_out_CFvalafter     : out std_logic_vector(15 downto 0);
 		data_out_read           : in std_logic;
 		data_out_available      : out std_logic;
 		data_out_inpipe         : out std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0);
-		testword1               : out std_logic_vector(35 downto 0)
+		error                   : out std_logic
 	);
 end FEE_sorting_mux;
 
 
-architecture Behavioral of FEE_sorting_mux is
-
-component FEE_mux2to1 is
-    Port (
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		data1_in                : in std_logic_vector(35 downto 0); 
-		data1_in_write          : in std_logic;
-		data1_in_available      : in std_logic;
-		data1_in_allowed        : out std_logic;
-		data2_in                : in std_logic_vector(35 downto 0); 
-		data2_in_write          : in std_logic;
-		data2_in_available      : in std_logic;
-		data2_in_allowed        : out std_logic;
-		data_out                : out std_logic_vector(35 downto 0);
-		data_out_write          : out std_logic;
-		data_out_available      : out std_logic;
-		data_out_allowed        : in std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
-		);
-end component;
-
-component FEE_mux_readfifo is
+
+architecture Behavioral of FEE_sorting_mux is
+
+component FEE_mux2to1 is
 	port (
 		clock                   : in std_logic;
 		reset                   : in std_logic;
-		data_in                 : in std_logic_vector(35 downto 0);
-		data_in_available       : in std_logic;
-		data_in_read            : out std_logic;
-		data_out                : out std_logic_vector(35 downto 0);
+		channel1                : in std_logic_vector(7 downto 0);
+		statusbyte1             : in std_logic_vector(7 downto 0);
+		energy1                 : in std_logic_vector(15 downto 0);
+		CFvalbefore1            : in std_logic_vector(15 downto 0);
+		CFvalafter1             : in std_logic_vector(15 downto 0);
+		timestamp1              : in std_logic_vector(15 downto 0);
+		superburst1             : in std_logic_vector(30 downto 0);
+		data1_in_write          : in std_logic;
+		data1_in_inpipe         : in std_logic;
+		data1_in_allowed        : out std_logic;
+		channel2                : in std_logic_vector(7 downto 0);
+		statusbyte2             : in std_logic_vector(7 downto 0);
+		energy2                 : in std_logic_vector(15 downto 0);
+		CFvalbefore2            : in std_logic_vector(15 downto 0);
+		CFvalafter2             : in std_logic_vector(15 downto 0);
+		timestamp2              : in std_logic_vector(15 downto 0);
+		superburst2             : in std_logic_vector(30 downto 0);
+		data2_in_write          : in std_logic;
+		data2_in_inpipe         : in std_logic;
+		data2_in_allowed        : out std_logic;
+		channel                 : out std_logic_vector(7 downto 0);
+		statusbyte              : out std_logic_vector(7 downto 0);
+		energy                  : out std_logic_vector(15 downto 0);
+		CFvalbefore             : out std_logic_vector(15 downto 0);
+		CFvalafter              : out std_logic_vector(15 downto 0);
+		timestamp               : out std_logic_vector(15 downto 0);
+		superburst              : out std_logic_vector(30 downto 0);
 		data_out_write          : out std_logic;
 		data_out_inpipe         : out std_logic;
-		data_out_allowed        : in std_logic);
+		data_out_allowed        : in std_logic;
+		error                   : out std_logic
+		);
 end component;
-
-component sync_fifo_progfull504_progempty128_512x36
-	port (
-		rst                     : in std_logic;
+
+component sync_fifo_progempty32_FWFT_512x104 is
+port (
+		srst                    : in std_logic;
 		clk                     : in std_logic;
-		din                     : in std_logic_vector(35 downto 0);
+		din                     : in std_logic_vector(103 downto 0);
 		wr_en                   : in std_logic;
 		rd_en                   : in std_logic;
-		dout                    : out std_logic_vector(35 downto 0);
+		dout                    : out std_logic_vector(103 downto 0);
 		full                    : out std_logic;
 		empty                   : out std_logic;
-		prog_full               : out std_logic;
-		prog_empty              : out std_logic);
+		prog_empty              : out std_logic
+	);
 end component;
 
-component sync_fifo_FWFT_512x36
+component sync_fifo_512x111
 	port (
-		rst                     : in std_logic;
+		srst                    : in std_logic;
 		clk                     : in std_logic;
-		din                     : in std_logic_vector(35 downto 0);
+		din                     : in std_logic_vector(110 downto 0);
 		wr_en                   : in std_logic;
 		rd_en                   : in std_logic;
-		dout                    : out std_logic_vector(35 downto 0);
+		dout                    : out std_logic_vector(110 downto 0);
 		full                    : out std_logic;
 		empty                   : out std_logic);
 end component;
-
-
+
 type twologarray_type is array(0 to 63) of natural;
 constant twologarray : twologarray_type :=
 (0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);
 
-constant mux2to1_gen_max      : integer := twologarray(NROFMUXINPUTS); -- -1;
-constant INPIPE_DELAY         : integer := 63;
-constant zeros                : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-constant ones                 : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
-
---type mux2to1_gen_type is array(0 to mux2to1_gen_max-1) of integer;
---constant mux2to1_gen          : mux2to1_gen_type := (8,4,2,1);
-
-type data_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(35 downto 0);
-type singlebit_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic;
-
-signal error_S                : std_logic := '0';
-
-signal data_S                 : data_type;
-signal data_out_inpipe_S      : singlebit_type := (others => (others => '0'));
-signal data_write_S           : singlebit_type := (others => (others => '0'));
-signal data_allowed_S         : singlebit_type := (others => (others => '0'));
-signal error_array_S          : singlebit_type := (others => (others => '0'));
-
-signal reset_MUXclock_S       : std_logic := '0';
-
+constant mux2to1_gen_max      : integer := twologarray(NROFMUXINPUTS); 
+constant INPIPE_DELAY_BITS    : integer := 4;
+constant ZEROS                : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+constant ONES                 : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
+
+type fiber_index_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(3 downto 0);
+type statusbyte_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(7 downto 0);
+type energy_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(15 downto 0);
+type timefraction_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(11 downto 0);
+type timestamp_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(15 downto 0);
+type superburstnumber_element_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(30 downto 0);
+
+type element8bits_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(7 downto 0);
+type element16bits_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(15 downto 0);
+type element31bits_type is array(0 to NROFMUXINPUTS-1) of std_logic_vector(30 downto 0);
+
+type matrix8bits_type is array(0 to mux2to1_gen_max) of element8bits_type;
+type matrix16bits_type is array(0 to mux2to1_gen_max) of element16bits_type;
+type matrix31bits_type is array(0 to mux2to1_gen_max) of element31bits_type;
+type matrix1bits_type is array(0 to mux2to1_gen_max) of std_logic_vector(0 to NROFMUXINPUTS-1);
+
+constant allZEROS             : matrix1bits_type := (others => (others => '0'));
+
+signal error_S                : std_logic := '0';
+signal reset_S                : std_logic;
+signal timeout_counter_S      : std_logic_vector (13 downto 0) := (others => '0');
+
+signal superburstnumber_S     : std_logic_vector (30 downto 0) := (others => '0');
+signal timestampcounter_S     : std_logic_vector (15 downto 0) := (others => '0');
+
+signal channel_S              : matrix8bits_type;
+signal superburst_S           : matrix31bits_type;
+signal statusbyte_S           : matrix8bits_type;
+signal timestamp_S            : matrix16bits_type;
+signal energy_S               : matrix16bits_type;
+signal CFvalafter_S           : matrix16bits_type;
+signal CFvalbefore_S          : matrix16bits_type;
+
+signal data_out_inpipe_S      : matrix1bits_type;
+signal data_write_S           : matrix1bits_type;
+signal data_allowed_S         : matrix1bits_type;
+signal error_array_S          : matrix1bits_type;
+
+signal reset_MUXclock_S       : std_logic := '0';
+
+			
 -- signals for fifo from adc-fe to adc-mux
 signal dfifo_wr_S             : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_wr1_S            : std_logic_vector(0 to NROFMUXINPUTS-1);
+signal dfifo_wr2_S            : std_logic_vector(0 to NROFMUXINPUTS-1);
 signal dfifo_rd_S             : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal dfifo_out_S            : array_halfadc36bits_type := (others => (others => '0'));
 signal dfifo_full_S           : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
 signal dfifo_empty_S          : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal data_in_available_S    : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_prog_full_S      : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
 signal dfifo_prog_empty_S     : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-
-signal delay_inpipe_S         : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal read36_inpipe_S        : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal waitafterwrite_S       : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
 
 
 -- signals for fifo from adc-mux to packet-composer
-signal tfifo_in_S             : std_logic_vector (35 downto 0);
+signal tfifo_wr_S             : std_logic := '0';
 signal tfifo_rd_S             : std_logic := '0';
 signal tfifo_full_S           : std_logic := '0';
 signal tfifo_empty_S          : std_logic := '0';
-
-type testword_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector (35 downto 0);
-signal testword0_S            : testword_type;
-
+signal tfifo_statusbyte_S     : std_logic_vector (7 downto 0);
+signal moretocome_S           : std_logic;
+
+
+-- tests
+signal sorterroroccured_S     : std_logic := '0';
+signal sorterrorcount_S       : std_logic_vector (7 downto 0);
+
+signal sorterror_S            : std_logic := '0';
+signal lastsuperburst_S       : std_logic_vector (30 downto 0);
+signal lasttimestamp_S        : std_logic_vector (15 downto 0);
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of error_array_S : signal is "true";
+-- attribute mark_debug of data_out_inpipe_S : signal is "true";
+-- attribute mark_debug of data_write_S : signal is "true";
+-- attribute mark_debug of data_allowed_S : signal is "true";
+
+
+begin
+
+error <= error_S;
+
+timestampcounter: process(clock)
 begin
+	if (rising_edge(clock)) then 
+		if superburstupdate='1' then
+			timestampcounter_S <= (others => '0');
+			superburstnumber_S <= superburstnumber;
+		else
+			timestampcounter_S <= timestampcounter_S+1;
+		end if;
+	end if;
+end process;
+
+
+mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate 
 
-
-data_out_inpipe <= '1' 
-	when dfifo_empty_S/=ones(0 to NROFMUXINPUTS-1) or (tfifo_empty_S='0') or (data_out_inpipe_S(mux2to1_gen_max,0)='1')
-	else '0';
-
-
-MUX_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate 
-
-process(clock)
-type inpipe_counter_type is array(0 to NROFMUXINPUTS-1) of integer range 0 to INPIPE_DELAY;
-variable inpipe_counter_V : inpipe_counter_type := (others => 0);
-variable index_other : integer range 0 to NROFMUXINPUTS-1;
-begin
-	if rising_edge(clock) then
-		if reset='1' then
-			inpipe_counter_V(index) := 0;
-			delay_inpipe_S(index) <= '0';
-		else
-			index_other := conv_integer(unsigned((conv_std_logic_vector(index,8) xor x"01")));
-			if ((dfifo_wr_S(index)='1') and (dfifo_prog_empty_S(index)='1')) or
-				((dfifo_wr_S(index_other)='1') and (dfifo_prog_empty_S(index_other)='1'))
-				then
-				inpipe_counter_V(index) := INPIPE_DELAY;
-				delay_inpipe_S(index) <= '1';
-			else			
-				if inpipe_counter_V(index)/=0 then
-					inpipe_counter_V(index) := inpipe_counter_V(index)-1;
-					delay_inpipe_S(index) <= '1';
-				else
-					delay_inpipe_S(index) <= '0';
-				end if;
-			end if;
-		end if;
-	end if;
-end process;
-
-dfifo: sync_fifo_progfull504_progempty128_512x36 port map(
-		rst => reset,
+dfifo: sync_fifo_progempty32_FWFT_512x104 port map(
+		srst => reset,
 		clk => clock,
-		din => data_in(index),
+		din(15 downto 0) => data_in_CFvalbefore(index),
+		din(31 downto 16) => data_in_CFvalafter(index),
+		din(47 downto 32) => data_in_energy(index),
+		din(63 downto 48) => data_in_timestamp(index),
+		din(94 downto 64) => data_in_superburst(index),
+		din(95) => data_in_lowgain(index),
+		din(103 downto 96) => data_in_status(index),
 		wr_en => dfifo_wr_S(index),
 		rd_en => dfifo_rd_S(index),
-		dout => dfifo_out_S(index),
+		dout(15 downto 0) => CFvalbefore_S(0)(index),
+		dout(31 downto 16) => CFvalafter_S(0)(index),
+		dout(47 downto 32) => energy_S(0)(index),
+		dout(63 downto 48) => timestamp_S(0)(index),
+		dout(94 downto 64) => superburst_S(0)(index),
+		dout(95) => channel_S(0)(index)(0),
+		dout(103 downto 96) => statusbyte_S(0)(index),
 		full => dfifo_full_S(index),
 		empty => dfifo_empty_S(index),
-		prog_full => data_in_almostfull(index),
 		prog_empty => dfifo_prog_empty_S(index));
-		
-dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
+				
+dfifo_wr_S(index) <= data_in_write(index);
 data_in_allowed(index) <= NOT dfifo_full_S(index);
-
-data_in_available_S(index) <= '1' when dfifo_empty_S(index)='0' else '0';
-
-FEE_mux_readfifo1: FEE_mux_readfifo port map(
-		clock => clock,
-		reset => reset,
-		data_in => dfifo_out_S(index),
-		data_in_available => data_in_available_S(index),
-		data_in_read => dfifo_rd_S(index),
-		data_out => data_S(0,index),
-		data_out_write => data_write_S(0,index),
-		data_out_inpipe => read36_inpipe_S(index),
-		data_out_allowed => data_allowed_S(0,index));
-
-process(data_out_inpipe_S(0,index),read36_inpipe_S(index),delay_inpipe_S(index),dfifo_wr_S(index)) -- ,dfifo_prog_empty_S)
---variable index_other : integer range 0 to NROFMUXINPUTS-1;
-begin
---	index_other := conv_integer(unsigned((conv_std_logic_vector(index,16) xor x"0001")));
---	if (read36_inpipe_S(index)='1') or ((dfifo_prog_empty_S(index_other)='1') and (delay_inpipe_S(index)='1')) or
---		(dfifo_wr_occuredrecently_S(index)='1') or -- was there a write recently (time: one datapacket plus a few slowcontrols ?
- 	if (read36_inpipe_S(index)='1') or (delay_inpipe_S(index)='1') or
-		(dfifo_wr_S(index)='1') then
-		data_out_inpipe_S(0,index) <= '1';
-	else
-		data_out_inpipe_S(0,index) <= '0';
-	end if;
-end process;
-			
-end generate;
-
-
-MUX_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate 
-
-	MUX_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate 
-	
-		FEE_mux2to1_1: FEE_mux2to1 port map(
+
+channel_S(0)(index)(7 downto 1) <= conv_std_logic_vector(index,7);
+
+waitafterwrite_S(index) <= '0' 
+	when ((superburstnumber_S & timestampcounter_S)-(superburst_S(0)(index) & timestamp_S(0)(index))>255) 
+		or (dfifo_prog_empty_S(index)='0') 
+	else '1';
+data_write_S(0)(index) <= '1' when (data_allowed_S(0)(index)='1') and (dfifo_empty_S(index)='0') and (waitafterwrite_S(index)='0') else '0';
+dfifo_rd_S(index) <= data_write_S(0)(index);
+data_out_inpipe_S(0)(index) <= '1' when (dfifo_empty_S(index)='0') or (dfifo_wr_S(index)='1') or (dfifo_wr1_S(index)='1') or (dfifo_wr2_S(index)='1') else '0';
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		dfifo_wr1_S(index) <= dfifo_wr_S(index);
+		dfifo_wr2_S(index) <= dfifo_wr1_S(index);
+	end if;
+end process;
+
+end generate;
+
+
+multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate 
+
+	multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate 
+	
+		FEE_mux2to1_1: FEE_mux2to1 port map(
 			clock => clock,
-			reset => reset,
-			data1_in => data_S(i1,i2*2),
-			data1_in_write => data_write_S(i1,i2*2),
-			data1_in_available => data_out_inpipe_S(i1,i2*2),
-			data1_in_allowed => data_allowed_S(i1,i2*2),
-			data2_in => data_S(i1,i2*2+1),
-			data2_in_write => data_write_S(i1,i2*2+1),
-			data2_in_available => data_out_inpipe_S(i1,i2*2+1),
-			data2_in_allowed => data_allowed_S(i1,i2*2+1),
-			data_out => data_S(i1+1,i2),
-			data_out_write => data_write_S(i1+1,i2),
-			data_out_available => data_out_inpipe_S(i1+1,i2),
-			data_out_allowed => data_allowed_S(i1+1,i2),
-			error => error_array_S(i1,i2),
-			testword0 => testword0_S(i1,i2));
-			
-	end generate;
-end generate;
-
-process(clock)
+			reset => reset_S,
+			channel1 => channel_S(i1)(i2*2),
+			statusbyte1 => statusbyte_S(i1)(i2*2),
+			energy1 => energy_S(i1)(i2*2),
+			CFvalbefore1 => CFvalbefore_S(i1)(i2*2),
+			CFvalafter1 => CFvalafter_S(i1)(i2*2),
+			timestamp1 => timestamp_S(i1)(i2*2),
+			superburst1 => superburst_S(i1)(i2*2),
+			data1_in_write => data_write_S(i1)(i2*2),
+			data1_in_inpipe => data_out_inpipe_S(i1)(i2*2),
+			data1_in_allowed => data_allowed_S(i1)(i2*2),
+			channel2 => channel_S(i1)(i2*2+1),
+			statusbyte2 => statusbyte_S(i1)(i2*2+1),
+			energy2 => energy_S(i1)(i2*2+1),
+			CFvalbefore2 => CFvalbefore_S(i1)(i2*2+1),
+			CFvalafter2 => CFvalafter_S(i1)(i2*2+1),
+			timestamp2 => timestamp_S(i1)(i2*2+1),
+			superburst2 => superburst_S(i1)(i2*2+1),
+			data2_in_write => data_write_S(i1)(i2*2+1),
+			data2_in_inpipe => data_out_inpipe_S(i1)(i2*2+1),
+			data2_in_allowed => data_allowed_S(i1)(i2*2+1),
+			channel => channel_S(i1+1)(i2),
+			statusbyte => statusbyte_S(i1+1)(i2),
+			energy => energy_S(i1+1)(i2),
+			CFvalbefore => CFvalbefore_S(i1+1)(i2),
+			CFvalafter => CFvalafter_S(i1+1)(i2),
+			timestamp => timestamp_S(i1+1)(i2),
+			superburst => superburst_S(i1+1)(i2),
+			data_out_write => data_write_S(i1+1)(i2),
+			data_out_inpipe => data_out_inpipe_S(i1+1)(i2),
+			data_out_allowed => data_allowed_S(i1+1)(i2),
+			error => error_array_S(i1)(i2));
+
+	end generate;
+end generate;
+
+process(clock)
 begin
-	if (rising_edge(clock)) then 
-		error_S <= '0';
-		for i1 in 0 to mux2to1_gen_max-1 loop 
+	if (rising_edge(clock)) then 
+		error_S <= '0';
+		for i1 in 0 to mux2to1_gen_max-1 loop 
 			for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop 
-				if error_array_S(i1,i2)='1' then
-					error_S <= '1';
-				end if;
-			end loop;
-		end loop;
-	end if;
+				if error_array_S(i1)(i2)='1' then
+					error_S <= '1';
+				end if;
+			end loop;
+		end loop;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if data_out_inpipe_S=allZEROS then
+			moretocome_S <= '0';
+		else
+			moretocome_S <= '1';
+		end if;
+	end if;
 end process;
-error <= error_S;
-
-data_allowed_S(mux2to1_gen_max,0) <= '1' when (tfifo_full_S='0') else '0';
-tfifo_in_S <= data_S(mux2to1_gen_max,0);
-tfifo: sync_fifo_FWFT_512x36 port map(
-		rst => reset,
+	
+data_allowed_S(mux2to1_gen_max)(0) <= '1' when (tfifo_full_S='0') else '0';
+
+tfifo_wr_S <= '1' when (data_write_S(mux2to1_gen_max)(0)='1') else '0';
+		
+tfifo: sync_fifo_512x111 port map(
+		srst => reset, 
 		clk => clock,
-		din => tfifo_in_S,
-		wr_en => data_write_S(mux2to1_gen_max,0),
+		din(15 downto 0) => CFvalbefore_S(mux2to1_gen_max)(0),
+		din(31 downto 16) => CFvalafter_S(mux2to1_gen_max)(0),
+		din(47 downto 32) => energy_S(mux2to1_gen_max)(0),
+		din(63 downto 48) => timestamp_S(mux2to1_gen_max)(0),
+		din(94 downto 64) => superburst_S(mux2to1_gen_max)(0),
+		din(102 downto 95) => statusbyte_S(mux2to1_gen_max)(0),
+		din(110 downto 103) => channel_S(mux2to1_gen_max)(0),
+		wr_en => tfifo_wr_S,
 		rd_en => tfifo_rd_S,
-		dout => data_out,
+		dout(15 downto 0) => data_out_CFvalbefore,
+		dout(31 downto 16) => data_out_CFvalafter,
+		dout(47 downto 32) => data_out_energy,
+		dout(63 downto 48) => data_out_timestamp,
+		dout(94 downto 64) => data_out_superburst,
+		dout(102 downto 95) => data_out_status,
+		dout(110 downto 103) => data_out_channel,
 		full => tfifo_full_S,
-		empty => tfifo_empty_S);
-
-		
-tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';
-data_out_available <= '1' when tfifo_empty_S='0' else '0';
-
-
-
-
---testword0(33 downto 0) <= data_in(0)(33 downto 0);
---testword0(34) <= time_error_S;
---testword0(35) <= idx_error_S;
-testword1(33 downto 0) <= data_in(1)(33 downto 0);
-testword1(34) <= '0';
-testword1(35) <= '0';
-
-
-
-	
-gentest: for i in 0 to 7 generate
-testword0(i) <= dfifo_full_S(i);
-end generate;
-
-testword0(8) <= dfifo_rd_S(7);
-testword0(9) <= data_in_available_S(7);
-
-testword0(10) <= data_write_S(0,7);
-testword0(11) <= data_out_inpipe_S(0,7);
-testword0(12) <= data_allowed_S(0,7);
-
-testword0(13) <= data_write_S(1,3);
-testword0(14) <= data_out_inpipe_S(1,3);
-testword0(15) <= data_allowed_S(1,3);
-
-testword0(16) <= data_write_S(2,1);
-testword0(17) <= data_out_inpipe_S(2,1);
-testword0(18) <= data_allowed_S(2,1);
-
-testword0(19) <= data_write_S(3,0);
-testword0(20) <= data_out_inpipe_S(3,0);
-testword0(21) <= data_allowed_S(3,0);
-
-
-testword0(22) <= data_write_S(0,0);
-testword0(23) <= data_out_inpipe_S(0,0);
-testword0(24) <= data_allowed_S(0,0);
-
-testword0(25) <= data_write_S(1,0);
-testword0(26) <= data_out_inpipe_S(1,0);
-testword0(27) <= data_allowed_S(1,0);
-
-testword0(28) <= data_write_S(2,0);
-testword0(29) <= data_out_inpipe_S(2,0);
-testword0(30) <= data_allowed_S(2,0);
-
-
-testword0(31) <= data_write_S(mux2to1_gen_max,0);
-testword0(32) <= tfifo_full_S;
-testword0(33) <= tfifo_rd_S;
-testword0(34) <= error_S;
-testword0(35) <= '0';
---
---
---
---testword1 <= testword0_S(2,0);
+		empty => tfifo_empty_S);
 		
+tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';
+data_out_available <= '1' when tfifo_empty_S='0' else '0';
+
+data_out_inpipe <= '1' when (tfifo_empty_S='0') or (moretocome_S='1') else '0';
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if (tfifo_wr_S='1') or (tfifo_full_S='1') or (dfifo_empty_S=ONES) or (timeout_counter_S(timeout_counter_S'left)='1') then
+			timeout_counter_S <= (others => '0');
+		else
+			timeout_counter_S <= timeout_counter_S+1;
+		end if;
+	end if;
+end process;
+reset_S <= '1' when (reset='1') or (timeout_counter_S(timeout_counter_S'left)='1') else '0';
+
+sorterror_S <= '1' when (data_write_S(mux2to1_gen_max)(0)='1') and (
+		(superburst_S(mux2to1_gen_max)(0)<lastsuperburst_S)
+	or ((superburst_S(mux2to1_gen_max)(0)=lastsuperburst_S) and (timestamp_S(mux2to1_gen_max)(0)<lasttimestamp_S))
+	) else '0';
+
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if reset='1' then
+			lastsuperburst_S <= (others => '0');
+			lasttimestamp_S <= (others => '0');
+			sorterrorcount_S <= (others => '0');
+		else
+			if data_write_S(mux2to1_gen_max)(0)='1' then
+				if sorterror_S='0' then
+					lastsuperburst_S <= superburst_S(mux2to1_gen_max)(0);
+					lasttimestamp_S <= timestamp_S(mux2to1_gen_max)(0);
+					sorterrorcount_S <= (others => '0');
+					sorterroroccured_S <= '0';
+				else
+					sorterroroccured_S <= '1';
+					if sorterrorcount_S(sorterrorcount_S'left)='0' then
+						sorterrorcount_S <= sorterrorcount_S+1;
+					else
+						lastsuperburst_S <= (others => '0');
+						lasttimestamp_S <= (others => '0');
+						sorterrorcount_S <= (others => '0');
+					end if;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
 end Behavioral;
 
diff --git a/FEE_ADC32board/FEE_modules/FEE_sorting_wavemux.vhd b/FEE_ADC32board/FEE_modules/FEE_sorting_wavemux.vhd
index 6fa1ff9..344cb07 100644
--- a/FEE_ADC32board/FEE_modules/FEE_sorting_wavemux.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_sorting_wavemux.vhd
@@ -1,38 +1,41 @@
-----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
--- Engineer:      Peter Schakel
--- Create Date:   03-02-2012
--- Module Name:   FEE_sorting_wavemux
--- Description:   Multiplexer for FEE data, sorting on timestamp
--- Modifications:
---   23-09-2014   single clock, remove fullness fifo, 
---   16-10-2014   inpipe signals 
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.all;
-USE ieee.std_logic_arith.all;
-USE work.panda_package.all;
-
-----------------------------------------------------------------------------------
--- FEE_sorting_wavemux
--- Multiplexes multiple input pulse data stream with waveform data to one stream.
--- Both consists of packets of 36-bits words: 32 bits data and 4 bits for index/check
--- The data is sorted based on the 32-bits timestamp.
--- This sorting is done by comparing the time of 2 waveforms; the first in time is passed on.
--- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.
---
--- Library:
---     work.panda_package: constants and types
---
--- Generics:
+----------------------------------------------------------------------------------
+-- Company:       KVI-cart/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   03-02-2012
+-- Module Name:   FEE_sorting_wavemux
+-- Description:   Multiplexer for FEE data, sorting on timestamp
+-- Modifications:
+--   23-09-2014   single clock, remove fullness fifo, 
+--   16-10-2014   inpipe signals 
+--   21-07-2015   data_out_inpipe clocked
+--   23-10-2015   added available, improved response to delayed input data
+--   15-04-2016   improved check on input buffer read delaytime (waittillend_S)
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+USE work.panda_package.all;
+
+----------------------------------------------------------------------------------
+-- FEE_sorting_wavemux
+-- Multiplexes multiple input pulse data stream with waveform data to one stream.
+-- Both consists of packets of 36-bits words: 32 bits data and 4 bits for index/check
+-- The data is sorted based on the 32-bits timestamp.
+-- This sorting is done by comparing the time of 2 waveforms; the first in time is passed on.
+-- Multiple of these comparators are placed in a tree structure. The last segment provides the sorted data.
+--
+-- Library:
+--     work.panda_package: constants and types
+--
+-- Generics:
 --     NROFMUXINPUTS : number of input-channels
---
--- Inputs:
---     clock : clock
---     reset : reset, must be long enough for all clocks
---     data_in : array of input data streams, structure of each:
+--
+-- Inputs:
+--     clock : clock
+--     reset : reset, must be long enough for all clocks
+--     data_in : array of input data streams, structure of each:
 --        	bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
 --        	bits(35..32)="0001" : 
 --              bits(31..24) = statusbyte (bit6=overflow) 
@@ -41,307 +44,460 @@ USE work.panda_package.all;
 --        	bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
 --        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
 --        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
---     data_in_write : write signal for data_in (write into fifo)
---     data_out_read : read signal for outgoing data (read from fifo)
--- 
--- Outputs:
---     data_in_allowed : write to input data allowed (not full)
---     data_in_almostfull : input fifo is too full for maximum length waveform
---     data_out : output data
---        	bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
---        	bits(35..32)="0001" : 
---              bits(31..24) = statusbyte (bit6=overflow) 
---              bits(23..8) = 0
---              bits(7..0) = adcnumber (channel identification)
---        	bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
---        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
---        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--     data_in_write : write signal for data_in (write into fifo)
+--     data_in_available : more data available in pipeline
+--     data_out_read : read signal for outgoing data (read from fifo)
+-- 
+-- Outputs:
+--     data_in_allowed : write to input data allowed (not full)
+--     data_in_almostfull : input fifo is too full for maximum length waveform
+--     data_out : output data
+--        	bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
+--        	bits(35..32)="0001" : 
+--              bits(31..24) = statusbyte (bit6=overflow) 
+--              bits(23..8) = 0
+--              bits(7..0) = adcnumber (channel identification)
+--        	bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--        	bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--        	bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
 --     data_out_available : data_out available (output fifo not empty)
---     data_out_inpipe : more data on its way
---     error : data error, index in data words incorrect
--- 
+--     data_out_inpipe : more data on its way
+--     error : data error, index in data words incorrect
+-- 
 -- Components:
 --     FEE_wavemux_readfifo : read data from fifo and writes to next level
 --     FEE_wavemux2to1 : compares the data and passes the first in time on
---     sync_fifo_progfull364_progempty128_512x36 : synchronous fifo with programmable full and empty
---     sync_fifo_FWFT_512x36 : synchronous fifo with First Word Fall Through
---
---
---
-----------------------------------------------------------------------------------
-
-entity FEE_sorting_wavemux is
-	generic(
-		NROFMUXINPUTS           : natural := 16
-	);
-    Port ( 
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		data_in                 : in array_halfadc36bits_type;
-		data_in_write           : in std_logic_vector(0 to NROFMUXINPUTS-1);
-		data_in_allowed         : out std_logic_vector(0 to NROFMUXINPUTS-1);
-		data_in_almostfull      : out std_logic_vector(0 to NROFMUXINPUTS-1);
-		data_out                : out std_logic_vector(35 downto 0);
-		data_out_read           : in std_logic;
-		data_out_available      : out std_logic;
-		data_out_inpipe         : out std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0);
-		testword1               : out std_logic_vector(35 downto 0)
-);
-end FEE_sorting_wavemux;
-
-
+--     sync_fifo_progfull364_progempty128_512x36 : synchronous fifo with programmable full and empty
+--     sync_fifo_FWFT_512x36 : synchronous fifo with First Word Fall Through
+--
+--
+--
+----------------------------------------------------------------------------------
+
+entity FEE_sorting_wavemux is
+	generic(
+		NROFMUXINPUTS           : natural := 16
+	);
+    Port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in array_halfadc36bits_type;
+		data_in_write           : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_available       : in std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_allowed         : out std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_in_almostfull      : out std_logic_vector(0 to NROFMUXINPUTS-1);
+		data_out                : out std_logic_vector(35 downto 0);
+		data_out_read           : in std_logic;
+		data_out_available      : out std_logic;
+		data_out_inpipe         : out std_logic;
+		error                   : out std_logic
+		);
+end FEE_sorting_wavemux;
+
+
 architecture Behavioral of FEE_sorting_wavemux is
 
 component FEE_wavemux2to1 is
-	generic(
-		TIMEOUTBITS             : natural := 6
-	);
+	generic(
+		TIMEOUTBITS             : natural := 8
+	);
 	Port (
-		clock                   : in std_logic;
+		clock                   : in std_logic;
 		reset                   : in std_logic;
 		data1_in                : in std_logic_vector(35 downto 0); 
 		data1_in_write          : in std_logic;
-		data1_in_available      : in std_logic;
+		data1_in_available      : in std_logic;
 		data1_in_allowed        : out std_logic;
 		data2_in                : in std_logic_vector(35 downto 0); 
 		data2_in_write          : in std_logic;
-		data2_in_available      : in std_logic;
+		data2_in_available      : in std_logic;
 		data2_in_allowed        : out std_logic;
 		data_out                : out std_logic_vector(35 downto 0);
 		data_out_write          : out std_logic;
-		data_out_available      : out std_logic;
+		data_out_available      : out std_logic;
 		data_out_allowed        : in std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
+		error                   : out std_logic;
+		timeerror               : out std_logic
 	);
-end component;
-
-component FEE_wavemux_readfifo is
-	port (
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		data_in                 : in std_logic_vector(35 downto 0);
-		data_in_available       : in std_logic;
+end component;
+
+component FEE_wavemux_readfifo is
+	port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(35 downto 0);
+		data_in_available       : in std_logic;
 		data_in_read            : out std_logic;
-		data_out                : out std_logic_vector(35 downto 0);
-		data_out_write          : out std_logic;
-		data_out_inpipe         : out std_logic;
+		data_out                : out std_logic_vector(35 downto 0);
+		data_out_write          : out std_logic;
+		data_out_inpipe         : out std_logic;
 		data_out_allowed        : in std_logic);
-end component;
-
-component sync_fifo_progfull364_progempty128_512x36
-	port (
-		rst                     : in std_logic;
-		clk                     : in std_logic;
-		din                     : in std_logic_vector(35 downto 0);
-		wr_en                   : in std_logic;
-		rd_en                   : in std_logic;
-		dout                    : out std_logic_vector(35 downto 0);
-		full                    : out std_logic;
-		empty                   : out std_logic;
-		prog_full               : out std_logic;
-		prog_empty              : out std_logic);
-end component;
-
-component sync_fifo_FWFT_512x36
-	port (
-		rst                     : in std_logic;
-		clk                     : in std_logic;
-		din                     : in std_logic_vector(35 downto 0);
-		wr_en                   : in std_logic;
-		rd_en                   : in std_logic;
-		dout                    : out std_logic_vector(35 downto 0);
-		full                    : out std_logic;
-		empty                   : out std_logic);
-end component;
-
-type twologarray_type is array(0 to 63) of natural;
-constant twologarray : twologarray_type :=
-(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);
-
-constant mux2to1_gen_max      : integer := twologarray(NROFMUXINPUTS); -- -1;
-constant INPIPE_DELAY         : integer := 63;
-constant zeros                : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-constant ones                 : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
+end component;
+
+component sync_fifo_progfull364_progempty128_512x36
+	port (
+		srst                    : in std_logic;
+		clk                     : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		prog_full               : out std_logic;
+		prog_empty              : out std_logic);
+end component;
+
+component sync_fifo_FWFT_512x36
+	port (
+		srst                    : in std_logic;
+		clk                     : in std_logic;
+		din                     : in std_logic_vector(35 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(35 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+type twologarray_type is array(0 to 63) of natural;
+constant twologarray : twologarray_type :=
+(0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5);
+
+constant mux2to1_gen_max      : integer := twologarray(NROFMUXINPUTS); -- -1;
+constant INPIPE_DELAY_BITS    : integer := 8; -- 8;
+constant ZEROS                : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+constant ONES                 : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '1');
 
 --type mux2to1_gen_type is array(0 to mux2to1_gen_max-1) of integer;
 --constant mux2to1_gen          : mux2to1_gen_type := (8,4,2,1);
 
-type data_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector(35 downto 0);
-type singlebit_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic;
+type data_type_arr is array(0 to NROFMUXINPUTS-1) of std_logic_vector(35 downto 0);
+type data_type is array(0 to mux2to1_gen_max) of data_type_arr;
+type singlebit_type is array(0 to mux2to1_gen_max) of std_logic_vector(0 to NROFMUXINPUTS-1);
 
 signal error_S                : std_logic := '0';
+signal reset_S                : std_logic;
+signal timeout_counter_S      : std_logic_vector (13 downto 0) := (others => '0');
 
 signal data_S                 : data_type;
-signal data_out_inpipe_S      : singlebit_type := (others => (others => '0'));
-signal data_write_S           : singlebit_type := (others => (others => '0'));
-signal data_allowed_S         : singlebit_type := (others => (others => '0'));
+signal data_out_inpipe_S      : singlebit_type := (others => (others => '0'));
+signal data_write_S           : singlebit_type := (others => (others => '0'));
+signal data_allowed_S         : singlebit_type := (others => (others => '0'));
 signal error_array_S          : singlebit_type := (others => (others => '0'));
+signal timeerror_array_S      : singlebit_type := (others => (others => '0'));
+
+-- signals for fifo from adc-fe to adc-mux
+signal dfifo_wr_S             : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_rd_S             : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_out_S            : array_halfadc36bits_type := (others => (others => '0'));
+signal dfifo_full_S           : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_empty_S          : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal data_in_available_S    : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal dfifo_prog_empty_S     : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal waittillend_S          : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal data_in_almostfull_S   : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal timedifflargeinout_S   : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal norecentdfiforead_S    : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
 
--- signals for fifo from adc-fe to adc-mux
-signal dfifo_wr_S             : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal dfifo_rd_S             : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal dfifo_out_S            : array_halfadc36bits_type := (others => (others => '0'));
-signal dfifo_full_S           : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal dfifo_empty_S          : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal data_in_available_S    : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal dfifo_prog_empty_S     : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-
-signal delay_inpipe_S         : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-signal read36_inpipe_S        : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
-
--- signals for fifo from adc-mux to packet-composer
+signal delay_inpipe_S         : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal read36_inpipe_S        : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal read36_allowed_S       : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+
+-- signals for fifo from adc-mux to packet-composer
 signal tfifo_in_S             : std_logic_vector (35 downto 0);
-signal tfifo_rd_S             : std_logic := '0';
-signal tfifo_full_S           : std_logic := '0';
-signal tfifo_empty_S          : std_logic := '0';
+signal tfifo_write_S          : std_logic := '0';
+signal tfifo_rd_S             : std_logic := '0';
+signal tfifo_full_S           : std_logic := '0';
+signal tfifo_empty_S          : std_logic := '0';
+
+-- signals for timecheck
+signal prev_data0_S           : std_logic_vector (35 downto 0) := (others => '0');
+signal timeerror_S            : std_logic := '0';
+signal inputerror_S           : std_logic_vector(0 to NROFMUXINPUTS-1) := (others => '0');
+signal fifoinerror_S          : std_logic := '0';
+		
+signal data0_S                : array_halfadc36bits_type;
+-- attribute mark_debug : string;
+-- attribute mark_debug of timeerror_S : signal is "true";
+-- attribute mark_debug of inputerror_S : signal is "true";
+-- attribute mark_debug of fifoinerror_S : signal is "true";
+-- attribute mark_debug of tfifo_in_S : signal is "true";
+-- attribute mark_debug of tfifo_write_S : signal is "true";
+-- attribute mark_debug of tfifo_full_S : signal is "true";
+-- attribute mark_debug of tfifo_empty_S : signal is "true";
+-- attribute mark_debug of dfifo_full_S : signal is "true";
+-- attribute mark_debug of dfifo_empty_S : signal is "true";
+-- attribute mark_debug of data_in_available_S : signal is "true";
+-- attribute mark_debug of dfifo_rd_S : signal is "true";
+-- attribute mark_debug of data_in_write : signal is "true";
+-- attribute mark_debug of data_in_available : signal is "true";
+-- attribute mark_debug of dfifo_prog_empty_S : signal is "true";
+-- attribute mark_debug of waittillend_S : signal is "true";
+-- attribute mark_debug of data_in_almostfull_S : signal is "true";
+-- attribute mark_debug of timedifflargeinout_S : signal is "true";
+-- attribute mark_debug of delay_inpipe_S : signal is "true";
+-- attribute mark_debug of read36_inpipe_S : signal is "true";
+-- attribute mark_debug of read36_allowed_S : signal is "true";
+-- attribute mark_debug of error_array_S : signal is "true";
+-- attribute mark_debug of data0_S : signal is "true";
+
+begin
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (dfifo_empty_S/=ONES(0 to NROFMUXINPUTS-1)) 
+				or (tfifo_empty_S='0') 
+				or (data_out_inpipe_S(mux2to1_gen_max)(0)='1') 
+		then
+			data_out_inpipe <= '1'; --//
+		else
+			data_out_inpipe <= '0';
+		end if;
+	end if;
+end process;
 
-type testword_type is array(0 to mux2to1_gen_max,0 to NROFMUXINPUTS-1) of std_logic_vector (35 downto 0);
-signal testword0_S            : testword_type;
+FEE_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate 
 
-begin
-
-data_out_inpipe <= '1' 
-	when (dfifo_empty_S/=ones(0 to NROFMUXINPUTS-1)) or (tfifo_empty_S='0') or (data_out_inpipe_S(mux2to1_gen_max,0)='1')
+timedifflargeinout_S(index) <= '1' when
+	((data_in(index)(31 downto 16)>data_S(0)(index)(31 downto 16)) and (data_in(index)(31 downto 16)-data_S(0)(index)(31 downto 16)>1)) or
+	((data_in(index)(31 downto 16)<data_S(0)(index)(31 downto 16)) and (data_S(0)(index)(31 downto 16)-data_in(index)(31 downto 16)<x"ffff"))
 	else '0';
-
-FEE_mux_inputs: for index in 0 to NROFMUXINPUTS-1 generate 
-
-process(clock)
-type inpipe_counter_type is array(0 to NROFMUXINPUTS-1) of integer range 0 to INPIPE_DELAY;
-variable inpipe_counter_V : inpipe_counter_type := (others => 0);
-variable index_other : integer range 0 to NROFMUXINPUTS-1;
-begin
-	if rising_edge(clock) then
-		if reset='1' then
-			inpipe_counter_V(index) := 0;
-			delay_inpipe_S(index) <= '0';
-		else
-			index_other := conv_integer(unsigned((conv_std_logic_vector(index,8) xor x"01")));
-			if ((dfifo_wr_S(index)='1') and (dfifo_prog_empty_S(index)='1')) or
-				((dfifo_wr_S(index_other)='1') and (dfifo_prog_empty_S(index_other)='1'))
-				then
-				inpipe_counter_V(index) := INPIPE_DELAY;
-				delay_inpipe_S(index) <= '1';
-			else			
-				if inpipe_counter_V(index)/=0 then
-					inpipe_counter_V(index) := inpipe_counter_V(index)-1;
-					delay_inpipe_S(index) <= '1';
-				else
-					delay_inpipe_S(index) <= '0';
-				end if;
-			end if;
-		end if;
-	end if;
-end process;
-
-
-dfifo: sync_fifo_progfull364_progempty128_512x36 port map(
-		rst => reset,
-		clk => clock,
-		din => data_in(index),
-		wr_en => dfifo_wr_S(index),
-		rd_en => dfifo_rd_S(index),
-		dout => dfifo_out_S(index),
-		full => dfifo_full_S(index),
-		empty => dfifo_empty_S(index),
-		prog_full => data_in_almostfull(index),
-		prog_empty => dfifo_prog_empty_S(index));
-
-		dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
-data_in_allowed(index) <= NOT dfifo_full_S(index);
+
+process(clock)
+variable delaycount_V           : std_logic_vector(INPIPE_DELAY_BITS downto 0) := (others => '0');
+begin
+	if rising_edge(clock) then
+		if (dfifo_wr_S(index)='1') and (data_in(index)(35 downto 32)="0000") and (dfifo_prog_empty_S(index)='1') and (norecentdfiforead_S(index)='0')
+			and ((timedifflargeinout_S(index)='0') or (data_S(0)(index)(35 downto 32)/="0000"))
+		then
+			waittillend_S(index) <= '1';
+			delaycount_V := (others => '0');
+		elsif delaycount_V(INPIPE_DELAY_BITS)='0' then
+			delaycount_V := delaycount_V+1;
+			waittillend_S(index) <= '1';
+		else
+			waittillend_S(index) <= '0';
+		end if;
+	end if;
+end process;
+
+process(clock)
+variable delaycount_V           : std_logic_vector(INPIPE_DELAY_BITS downto 0) := (others => '0');
+begin
+	if rising_edge(clock) then
+		norecentdfiforead_S(index) <= '0';
+		if (data_write_S(0)(index)='1') or (data_allowed_S(0)(index)='0') then 
+			delaycount_V := (others => '0');
+		else
+			if (data_S(0)(index)(35 downto 32)="0000") then
+				if delaycount_V(delaycount_V'left)='0' then
+					delaycount_V := delaycount_V+1;
+				else
+					norecentdfiforead_S(index) <= '1';
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+dfifo: sync_fifo_progfull364_progempty128_512x36 port map(
+		srst => reset,
+		clk => clock,
+		din => data_in(index),
+		wr_en => dfifo_wr_S(index),
+		rd_en => dfifo_rd_S(index),
+		dout => dfifo_out_S(index),
+		full => dfifo_full_S(index),
+		empty => dfifo_empty_S(index),
+		prog_full => data_in_almostfull_S(index),
+		prog_empty => dfifo_prog_empty_S(index));
+
+		dfifo_wr_S(index) <= '1' when (dfifo_full_S(index)='0') and (data_in_write(index)='1') else '0';
+data_in_allowed(index) <= NOT dfifo_full_S(index);
+data_in_almostfull(index) <= data_in_almostfull_S(index);
 
 data_in_available_S(index) <= '1' when dfifo_empty_S(index)='0' else '0';
 
-FEE_wavemux_readfifo1: FEE_wavemux_readfifo port map(
-		clock => clock,
-		reset => reset,
-		data_in => dfifo_out_S(index),
-		data_in_available => data_in_available_S(index),
+FEE_wavemux_readfifo1: FEE_wavemux_readfifo port map(
+		clock => clock,
+		reset => reset,
+		data_in => dfifo_out_S(index),
+		data_in_available => data_in_available_S(index),
 		data_in_read => dfifo_rd_S(index),
-		data_out => data_S(0,index),
-		data_out_write => data_write_S(0,index),
-		data_out_inpipe => read36_inpipe_S(index),
-		data_out_allowed => data_allowed_S(0,index));
-	
-process(data_out_inpipe_S(0,index),read36_inpipe_S(index),delay_inpipe_S(index),dfifo_wr_S(index)) -- ,dfifo_prog_empty_S)
---variable index_other : integer range 0 to NROFMUXINPUTS-1;
-begin
---	index_other := conv_integer(unsigned((conv_std_logic_vector(index,16) xor x"0001")));
---	if (read36_inpipe_S(index)='1') or ((dfifo_prog_empty_S(index_other)='1') and (delay_inpipe_S(index)='1')) or
---		(dfifo_wr_occuredrecently_S(index)='1') or -- was there a write recently (time: one datapacket plus a few slowcontrols ?
- 	if (read36_inpipe_S(index)='1') or (delay_inpipe_S(index)='1') or
-		(dfifo_wr_S(index)='1') then
-		data_out_inpipe_S(0,index) <= '1';
-	else
-		data_out_inpipe_S(0,index) <= '0';
-	end if;
-end process;
-			
+		data_out => data_S(0)(index),
+		data_out_write => data_write_S(0)(index),
+		data_out_inpipe => read36_inpipe_S(index),
+		data_out_allowed => read36_allowed_S(index));
+read36_allowed_S(index) <= '1' when (data_allowed_S(0)(index)='1') and 
+	((waittillend_S(index)='0') or (data_S(0)(index)(35 downto 32)/="0000")) else '0';
+
+data0_S(index) <= data_S(0)(index);
+
+data_out_inpipe_S(0)(index) <= '1' when (data_in_available(index)='1') or (read36_inpipe_S(index)='1') else '0'; -- or (delay_inpipe_S(index)='1') else '0';
+			
 end generate;
 
 
 FEE_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate 
 
-	FEE_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate 
+	FEE_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate 
 	
-		FEE_wavemux2to1_1: FEE_wavemux2to1 port map(
-			clock => clock,
-			reset => reset,
-			data1_in => data_S(i1,i2*2),
-			data1_in_write => data_write_S(i1,i2*2),
-			data1_in_available => data_out_inpipe_S(i1,i2*2),
-			data1_in_allowed => data_allowed_S(i1,i2*2),
-			data2_in => data_S(i1,i2*2+1),
-			data2_in_write => data_write_S(i1,i2*2+1),
-			data2_in_available => data_out_inpipe_S(i1,i2*2+1),
-			data2_in_allowed => data_allowed_S(i1,i2*2+1),
-			data_out => data_S(i1+1,i2),
-			data_out_write => data_write_S(i1+1,i2),
-			data_out_available => data_out_inpipe_S(i1+1,i2),
-			data_out_allowed => data_allowed_S(i1+1,i2),
-			error => error_array_S(i1,i2),
-			testword0 => testword0_S(i1,i2));
+		FEE_wavemux2to1_1: FEE_wavemux2to1 
+		generic map(
+			TIMEOUTBITS => 11
+		)		
+		port map(
+			clock => clock,
+			reset => reset_S,
+			data1_in => data_S(i1)(i2*2),
+			data1_in_write => data_write_S(i1)(i2*2),
+			data1_in_available => data_out_inpipe_S(i1)(i2*2),
+			data1_in_allowed => data_allowed_S(i1)(i2*2),
+			data2_in => data_S(i1)(i2*2+1),
+			data2_in_write => data_write_S(i1)(i2*2+1),
+			data2_in_available => data_out_inpipe_S(i1)(i2*2+1),
+			data2_in_allowed => data_allowed_S(i1)(i2*2+1),
+			data_out => data_S(i1+1)(i2),
+			data_out_write => data_write_S(i1+1)(i2),
+			data_out_available => data_out_inpipe_S(i1+1)(i2),
+			data_out_allowed => data_allowed_S(i1+1)(i2),
+			error => error_array_S(i1)(i2),
+			timeerror => timeerror_array_S(i1)(i2));
 			
 	end generate;
 end generate;
 
 process(clock)
-begin
+begin
 	if (rising_edge(clock)) then 
 		error_S <= '0';
 		for i1 in 0 to mux2to1_gen_max-1 loop 
-			for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop 
-				if error_array_S(i1,i2)='1' then
+			for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop 
+				if error_array_S(i1)(i2)='1' then
 					error_S <= '1';
 				end if;
 			end loop;
 		end loop;
 	end if;
-end process;
+end process;
 error <= error_S;
 
-data_allowed_S(mux2to1_gen_max,0) <= '1' when (tfifo_full_S='0') else '0';
-tfifo_in_S <= data_S(mux2to1_gen_max,0);
-tfifo: sync_fifo_FWFT_512x36 port map(
-		rst => reset,
-		clk => clock,
-		din => tfifo_in_S,
-		wr_en => data_write_S(mux2to1_gen_max,0),
-		rd_en => tfifo_rd_S,
-		dout => data_out,
-		full => tfifo_full_S,
-		empty => tfifo_empty_S);
-
+data_allowed_S(mux2to1_gen_max)(0) <= '1' when (tfifo_full_S='0') else '0';
+tfifo_in_S <= data_S(mux2to1_gen_max)(0);
+tfifo: sync_fifo_FWFT_512x36 port map(
+		srst => reset,
+		clk => clock,
+		din => tfifo_in_S,
+		wr_en => tfifo_write_S,
+		rd_en => tfifo_rd_S,
+		dout => data_out,
+		full => tfifo_full_S,
+		empty => tfifo_empty_S);
+tfifo_write_S <= data_write_S(mux2to1_gen_max)(0);
 tfifo_rd_S <= '1' when (data_out_read='1') and (tfifo_empty_S='0') else '0';
 data_out_available <= '1' when tfifo_empty_S='0' else '0';
 
-
-testword0 <= (others => '0');
-testword1 <= (others => '0');
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if (tfifo_write_S='1') or (tfifo_full_S='1') or (dfifo_empty_S=ONES) or (timeout_counter_S(timeout_counter_S'left)='1') then
+			timeout_counter_S <= (others => '0');
+		else
+			timeout_counter_S <= timeout_counter_S+1;
+		end if;
+	end if;
+end process;
+reset_S <= '1' when (reset='1') or (timeout_counter_S(timeout_counter_S'left)='1') else '0';
+
+
+process(clock)
+variable time_counter_V : integer range 0 to 2047 := 0;
+begin
+	if (rising_edge(clock)) then 
+		timeerror_S <= '0';
+		if data_write_S(mux2to1_gen_max)(0)='1' then
+			if tfifo_in_S(35 downto 32)="0000" then
+				if tfifo_in_S(31 downto 16)=prev_data0_S(31 downto 16) then
+					if tfifo_in_S(15 downto 0)<prev_data0_S(15 downto 0) then
+						timeerror_S <= '1';
+					end if;
+				elsif tfifo_in_S(31 downto 16)<prev_data0_S(31 downto 16) then
+					if tfifo_in_S(31 downto 30)="00" and prev_data0_S(31 downto 30)="11" then
+					else
+						if time_counter_V<2000 then
+							timeerror_S <= '1';
+						end if;
+					end if;
+				elsif tfifo_in_S(31 downto 16)>prev_data0_S(31 downto 16) then
+					if tfifo_in_S(31 downto 30)="11" and prev_data0_S(31 downto 30)="00" then
+						if time_counter_V<2000 then
+							timeerror_S <= '1';
+						end if;
+					end if;
+				end if;
+				time_counter_V := 0;
+				prev_data0_S <= tfifo_in_S;
+			end if;
+		else
+			time_counter_V := time_counter_V+1;
+		end if;
+	end if;
+end process;
+
+process(clock)
+variable prevdata_V : std_logic_vector(3 downto 0) := "0000";
+begin
+	if (rising_edge(clock)) then 
+		fifoinerror_S <= '0';
+		if tfifo_write_S='1' then
+			if (tfifo_in_S(35 downto 32)="0000") then
+				if (prevdata_V(3 downto 1)/="010") then fifoinerror_S <= '1'; end if;
+			elsif (tfifo_in_S(35 downto 32)="0001") then
+				if (prevdata_V/="0000") then fifoinerror_S <= '1'; end if;
+			elsif (tfifo_in_S(35 downto 32)="0010") then
+				if (prevdata_V/="0010") and (prevdata_V/="0001") then fifoinerror_S <= '1'; end if;
+			elsif (tfifo_in_S(35 downto 32)="0100") then
+				if (prevdata_V/="0010") then fifoinerror_S <= '1'; end if;
+			elsif (tfifo_in_S(35 downto 32)="0101") then 
+				if (prevdata_V/="0010") then fifoinerror_S <= '1'; end if;
+			else
+				fifoinerror_S <= '1';
+			end if;
+			prevdata_V := tfifo_in_S(35 downto 32);
+		end if;
+	end if;
+end process;
+
+
+geninerrors: for i in 0 to NROFMUXINPUTS-1 generate
+process(clock)
+variable prevdata_V : std_logic_vector(3 downto 0) := "0000";
+begin
+	if (rising_edge(clock)) then 
+		inputerror_S(i) <= '0';
+		if data_write_S(0)(i)='1' then
+			if (data_S(0)(i)(35 downto 32)="0000") then
+				if (prevdata_V(3 downto 1)/="010") then inputerror_S(i) <= '1'; end if;
+			elsif (data_S(0)(i)(35 downto 32)="0001") then
+				if (prevdata_V/="0000") then inputerror_S(i) <= '1'; end if;
+			elsif (data_S(0)(i)(35 downto 32)="0010") then
+				if (prevdata_V/="0010") and (prevdata_V/="0001") then inputerror_S(i) <= '1'; end if;
+			elsif (data_S(0)(i)(35 downto 32)="0100") then
+				if (prevdata_V/="0010") then inputerror_S(i) <= '1'; end if;
+			elsif (data_S(0)(i)(35 downto 32)="0101") then 
+				if (prevdata_V/="0010") then inputerror_S(i) <= '1'; end if;
+			else
+				inputerror_S(i) <= '1';
+			end if;
+			prevdata_V := data_S(0)(i)(35 downto 32);
+		end if;
+	end if;
+end process;
+end generate;
+
+
+end Behavioral;
 
-	
-end Behavioral;
-
diff --git a/FEE_ADC32board/FEE_modules/FEE_transmit_combine.vhd b/FEE_ADC32board/FEE_modules/FEE_transmit_combine.vhd
new file mode 100644
index 0000000..48c6629
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/FEE_transmit_combine.vhd
@@ -0,0 +1,577 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   13-01-2017
+-- Module Name:   FEE_transmit_combine
+-- Description:   Combine data from two FPGAs to one data stream
+-- Modifications:
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+USE work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- FEE_transmit_combine
+-- Combine data from two FPGAs to one data stream.
+-- The data consist of hits, waveform or slow control.
+-- The hits and the waveforms are time ordered.
+--
+--
+-- The resulting data packets : 4 32-bit words, with CRC8 in last word
+--   0xDA ADCnumber(7..0) superburstnumber(15..0)
+--   timestamp(15..0) energy(15..0) 
+--   CF_before(15..0) CF_after(15..0)
+--   0000 statusbyte(7..0) CRC8(7..0)
+--
+-- The slow control packets : 2 32-bit words, with CRC8 in last word
+--   0x5C address(7..0) replybit 0000000 data(31..24)
+--   data(23..0) CRC8(7..0)
+--
+-- The waveform packets : 32-bit words, with CRC8 in last word
+--   0xAF ADCnumber(7..0) superburstnumber(15..0)
+--   timestamp(15..0) 0x00 statusbyte(7..0)
+--   0 adc0(14..0) 0 adc1(14..0) : 2 adc-samples 15 bits signed
+--   0 adc2(14..0) 0 adc3(14..0) : next 2 adc-samples 15 bits signed
+--   .........
+--   1 adcn(14..0) 1 00 CRC8(7..0) : last 32-bit word: last adc-sample 15 bits signed
+--         or
+--   0 0000 1 00 CRC8(7..0) : last 32-bit word: no sample--
+--
+-- 
+-- Library
+--     work.panda_package :  for type declarations and constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--    clock_local : clock for Feature Extraction in the same FPGA
+--    clock_remote : clock for Feature Extraction in the other FPGA
+--    clock_out : clock for output data
+--    reset : reset all
+--    GEO : indicates which FPGA, 0:this is FPGA1, 1:this is FPGA2
+--    data_local : data from local FE
+--    data_local_first : indicates first 32-bits data word in packet from local FE
+--    data_local_last : indicates last 32-bits data word in packet from local FE
+--    data_local_write : write signal for data from local FE
+--    data_local_inpipe : more data on its way from local FE
+--    data_remote : data from remote FE
+--    data_remote_first : indicates first 32-bits data word in packet from remote FE
+--    data_remote_last : indicates last 32-bits data word in packet from remote FE
+--    data_remote_write : write signal for data from remote FE
+--    data_remote_inpipe : more data on its way from remote FE
+--    data_out_fifofull : full signal from fifo connected to the output
+-- 
+-- Outputs:
+--    data_local_fifofull : input fifo for local data is full
+--    data_remote_fifofull : input fifo for remote data is full
+--    data_out : data to fiber module
+--    data_out_first : first 32-bit data word of a packet
+--    data_out_last : last 32-bit data word of a packet
+--    data_out_write : write signal for output data
+--    error : errors occurred: adjust with other FE instances for comparison
+--
+-- Components:
+--    async_progfull192_progempty128_fifo_256x34 : fifo to buffer data from local and remote FPGA
+-- 
+----------------------------------------------------------------------------------
+
+entity FEE_transmit_combine is
+	port ( 
+		clock_local             : in std_logic;
+		clock_remote            : in std_logic;
+		clock_out               : in std_logic;
+		reset                   : in std_logic;
+		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
+		enable_waveform         : in std_logic;
+		data_local              : in std_logic_vector (31 downto 0);
+		data_local_first        : in std_logic;
+		data_local_last         : in std_logic;
+		data_local_write        : in std_logic;
+		data_local_inpipe       : in std_logic;
+		data_local_fifofull     : out std_logic;
+		data_remote             : in std_logic_vector(31 downto 0);
+		data_remote_first       : in std_logic;
+		data_remote_last        : in std_logic;
+		data_remote_write       : in std_logic;
+		data_remote_inpipe      : in std_logic;
+		data_remote_fifofull    : out std_logic;
+		data_remote_almostfull  : out std_logic;
+		data_out                : out std_logic_vector(31 downto 0);
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_inpipe         : out std_logic;
+		data_out_fifofull       : in std_logic;
+		error                   : out std_logic
+		);
+end FEE_transmit_combine;
+
+architecture Behavioral of FEE_transmit_combine is
+
+component async_progfull448_progempty128_fifo_512x34
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(33 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(33 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic;
+		prog_full               : out std_logic;
+		prog_empty              : out std_logic);
+end component;
+
+type data_type is (NONE,HITDATA,SLOWCONTROL,WAVEFORM);
+signal fifo_local_progfull_S            : std_logic;
+signal data_local_write_S               : std_logic;
+signal errorin_local_S                  : std_logic;
+
+signal data_remote_write_S              : std_logic;
+signal errorin_remote_S                 : std_logic;
+
+signal data_local_inpipe_S              : std_logic;
+signal fifo_local_empty_S               : std_logic;
+signal data_local_read_S                : std_logic;
+signal fifo_local_read_aftr1clk_S       : std_logic;
+signal data_local_S                     : std_logic_vector (31 downto 0);
+signal data_local_first_S               : std_logic;
+signal data_local_last_S                : std_logic;
+signal header_local_hits0_S             : std_logic_vector (31 downto 0);
+signal header_local_hits1_S             : std_logic_vector (31 downto 0);
+signal data_local_type_S                : data_type;
+signal data_local_count_S               : integer range 0 to 255 := 0;
+
+signal data_remote_inpipe_S             : std_logic;
+signal fifo_remote_empty_S              : std_logic;
+signal data_remote_read_S               : std_logic;
+signal fifo_remote_read_aftr1clk_S      : std_logic;
+signal data_remote_S                    : std_logic_vector (31 downto 0);
+signal data_remote_first_S              : std_logic;
+signal data_remote_last_S               : std_logic;
+signal header_remote_hits0_S            : std_logic_vector (31 downto 0);
+signal header_remote_hits1_S            : std_logic_vector (31 downto 0);
+signal data_remote_type_S               : data_type;
+signal data_remote_count_S              : integer range 0 to 255 := 0;
+
+type writemode_type is (WAITNEXT,LOCALSLOWCONTROL,REMOTESLOWCONTROL,LOCALHITS0,LOCALHITS1,LOCALHITS2,
+		REMOTEHITS0,REMOTEHITS1,REMOTEHITS2,LOCALWAVES0,LOCALWAVES1,REMOTEWAVES0,REMOTEWAVES1);
+signal writemode_S                      : writemode_type := WAITNEXT;
+signal timeoutcount_S                   : std_logic_vector (9 downto 0);
+signal errorout_S                       : std_logic;
+signal data_out_S                       : std_logic_vector (31 downto 0);
+signal data_out_write_S                 : std_logic;
+signal data_out_first_S                 : std_logic;
+signal data_out_last_S                  : std_logic;
+
+signal data_out_saved_S                 : std_logic_vector (31 downto 0);
+signal data_out_save_S                  : std_logic := '0';
+signal data_out_saved_first_S           : std_logic;
+signal data_out_saved_last_S            : std_logic;
+
+
+	
+-- attribute mark_debug : string;
+-- attribute mark_debug of errorout_S : signal is "true";
+-- attribute mark_debug of enable_waveform : signal is "true";
+-- attribute mark_debug of data_local : signal is "true";
+-- attribute mark_debug of data_local_first : signal is "true";
+-- attribute mark_debug of data_local_last : signal is "true";
+-- attribute mark_debug of data_local_write : signal is "true";
+-- attribute mark_debug of data_local_inpipe : signal is "true";
+-- attribute mark_debug of data_local_fifofull : signal is "true";
+-- attribute mark_debug of fifo_local_empty_S : signal is "true";
+-- attribute mark_debug of data_remote : signal is "true";
+-- attribute mark_debug of data_remote_first : signal is "true";
+-- attribute mark_debug of data_remote_last : signal is "true";
+-- attribute mark_debug of data_remote_write : signal is "true";
+-- attribute mark_debug of data_remote_inpipe : signal is "true";
+-- attribute mark_debug of data_remote_fifofull : signal is "true";
+-- attribute mark_debug of fifo_remote_empty_S : signal is "true";
+-- attribute mark_debug of data_remote_almostfull : signal is "true";
+-- attribute mark_debug of data_out : signal is "true";
+-- attribute mark_debug of data_out_first : signal is "true";
+-- attribute mark_debug of data_out_last : signal is "true";
+-- attribute mark_debug of data_out_write : signal is "true";
+-- attribute mark_debug of data_out_inpipe : signal is "true";
+-- attribute mark_debug of data_out_fifofull : signal is "true";
+-- attribute mark_debug of writemode_S : signal is "true";
+-- attribute mark_debug of data_local_count_S : signal is "true";
+-- attribute mark_debug of data_remote_count_S : signal is "true";
+
+
+begin
+
+error <= '1' when (errorout_S='1') or (errorin_local_S='1') or (errorin_remote_S='1') else '0';
+data_out_inpipe <= '1' when (data_local_inpipe_S='1') or (data_remote_inpipe_S='1') or (writemode_S/=WAITNEXT) or 
+	(fifo_local_empty_S='0') or (fifo_remote_empty_S='0') else '0';
+data_out <= data_out_S when (data_out_save_S='0') else data_out_saved_S;
+data_out_write <= '1' when (data_out_write_S='1') and (data_out_fifofull='0') else '0';
+data_out_first <= data_out_first_S when (data_out_save_S='0') else data_out_saved_first_S;
+data_out_last <=  data_out_last_S when (data_out_save_S='0') else data_out_saved_last_S;
+
+
+fifo_local: async_progfull448_progempty128_fifo_512x34 port map(
+		rst => reset,
+		wr_clk => clock_local,
+		rd_clk => clock_out,
+		din(33) => data_local_first,
+		din(32) => data_local_last,
+		din(31 downto 0) => data_local,
+		wr_en => data_local_write,
+		rd_en => data_local_read_S,
+		dout(33) => data_local_first_S,
+		dout(32) => data_local_last_S,
+		dout(31 downto 0) => data_local_S,
+		full => data_local_fifofull,
+		empty => fifo_local_empty_S,
+		prog_full => fifo_local_progfull_S,
+		prog_empty => open);
+		
+fifo_remote_hits: async_progfull448_progempty128_fifo_512x34 port map(
+		rst => reset,
+		wr_clk => clock_remote,
+		rd_clk => clock_out,
+		din(33) => data_remote_first,
+		din(32) => data_remote_last,
+		din(31 downto 0) => data_remote,
+		wr_en => data_remote_write,
+		rd_en => data_remote_read_S,
+		dout(33) => data_remote_first_S,
+		dout(32) => data_remote_last_S,
+		dout(31 downto 0) => data_remote_S,
+		full => data_remote_fifofull,
+		empty => fifo_remote_empty_S,
+		prog_full => data_remote_almostfull,
+		prog_empty => open);
+	
+		
+process(clock_out)
+begin
+	if (rising_edge(clock_out)) then 
+		data_local_inpipe_S <= data_local_inpipe;
+		data_remote_inpipe_S <= data_remote_inpipe;
+	end if;
+end process;
+
+
+data_local_read_S <= '1' when ((fifo_local_empty_S='0') and (data_out_fifofull='0') and (data_out_save_S='0')) and
+	(((data_local_count_S=0) or ((data_local_count_S=1) and (fifo_local_read_aftr1clk_S='0'))) or
+	(((writemode_S=LOCALHITS0) or (writemode_S=LOCALHITS1) or ((writemode_S=LOCALHITS2) and (fifo_local_read_aftr1clk_S='0'))) or
+	((writemode_S=LOCALWAVES0) or ((writemode_S=LOCALWAVES1) and (data_local_last_S='0')))))
+	else '0';
+
+data_remote_read_S <= '1' when ((fifo_remote_empty_S='0') and (data_out_fifofull='0') and (data_out_save_S='0')) and
+	(((data_remote_count_S=0) or ((data_remote_count_S=1) and (fifo_remote_read_aftr1clk_S='0'))) or
+	(((writemode_S=REMOTEHITS0) or (writemode_S=REMOTEHITS1) or ((writemode_S=REMOTEHITS2) and (fifo_remote_read_aftr1clk_S='0'))) or
+	((writemode_S=REMOTEWAVES0) or ((writemode_S=REMOTEWAVES1) and (data_remote_last_S='0'))))) else '0';
+		
+process(clock_out)
+variable local_timestamp_V     : std_logic_vector(31 downto 0);
+variable remote_timestamp_V    : std_logic_vector(31 downto 0);
+begin
+	if (rising_edge(clock_out)) then 
+		errorout_S <= '0';
+		data_out_write_S <= '0';
+		data_out_first_S <= '0';
+		data_out_last_S <= '0';
+		if (data_out_write_S='1') and (data_out_fifofull='1') then
+			data_out_write_S <= '1';
+			data_out_first_S <= data_out_first_S;
+			data_out_last_S <= data_out_last_S;
+			if (fifo_local_read_aftr1clk_S='1') or (fifo_remote_read_aftr1clk_S='1') then
+				data_out_save_S <= '1';
+				data_out_saved_S <= data_out_S;
+				data_out_saved_first_S <= data_out_first_S;
+				data_out_saved_last_S <= data_out_last_S;
+			end if;
+		elsif data_out_save_S='1' then
+			data_out_write_S <= '1';
+			data_out_save_S <= '0';
+			data_out_first_S <= data_out_first_S;
+			data_out_last_S <= data_out_last_S;
+		end if;
+		if (fifo_local_read_aftr1clk_S='1') then
+			if data_local_first_S='1' then
+				header_local_hits0_S <= data_local_S;
+				data_local_count_S <= 1;
+				if data_local_S(31 downto 24)=x"5c" then
+					data_local_type_S <= SLOWCONTROL;
+				elsif data_local_S(31 downto 24)=x"da" then
+					data_local_type_S <= HITDATA;
+				elsif data_local_S(31 downto 24)=x"af" then
+					data_local_type_S <= WAVEFORM;
+				else
+					data_local_type_S <= NONE;
+					data_local_count_S <= 0;
+					errorout_S <= '1';
+				end if;
+			elsif data_local_count_S=0 then
+				errorout_S <= '1';
+			elsif data_local_count_S=1 then
+				header_local_hits1_S <= data_local_S;
+				data_local_count_S <= data_local_count_S+1;
+			elsif data_local_count_S>1 then
+				data_local_count_S <= data_local_count_S+1;
+			end if;
+		end if;
+		if (fifo_remote_read_aftr1clk_S='1') then
+			if data_remote_first_S='1' then
+				header_remote_hits0_S <= data_remote_S;
+				data_remote_count_S <= 1;
+				if data_remote_S(31 downto 24)=x"5c" then
+					data_remote_type_S <= SLOWCONTROL;
+				elsif data_remote_S(31 downto 24)=x"da" then
+					data_remote_type_S <= HITDATA;
+				elsif data_remote_S(31 downto 24)=x"af" then
+					data_remote_type_S <= WAVEFORM;
+				else
+					data_remote_type_S <= NONE;
+					data_remote_count_S <= 0;
+					errorout_S <= '1';
+				end if;
+			elsif data_remote_count_S=0 then
+				errorout_S <= '1';
+			elsif data_remote_count_S=1 then
+				header_remote_hits1_S <= data_remote_S;
+				data_remote_count_S <= data_remote_count_S+1;
+			elsif data_remote_count_S>1 then
+				data_remote_count_S <= data_remote_count_S+1;
+			end if;
+		end if;
+		
+		if (data_out_save_S='1') or ((data_out_fifofull='1') and (writemode_S=WAITNEXT)) then
+		else
+			case writemode_S is
+				when LOCALSLOWCONTROL =>
+					data_out_S <= header_local_hits1_S;
+					data_out_last_S <= '1';
+					data_out_write_S <= '1';
+					data_local_count_S <= 0;
+					writemode_S <= WAITNEXT;
+				when REMOTESLOWCONTROL =>
+					data_out_S <= header_remote_hits1_S;
+					data_out_last_S <= '1';
+					data_out_write_S <= '1';
+					data_remote_count_S <= 0;
+					writemode_S <= WAITNEXT;
+				when LOCALHITS0 =>
+					data_out_S <= header_local_hits1_S;
+					data_out_write_S <= not enable_waveform;
+					writemode_S <= LOCALHITS1;
+				when LOCALHITS1 => 
+					if (fifo_local_read_aftr1clk_S='1') then
+						data_out_S <= data_local_S;
+						data_out_write_S <= not enable_waveform;
+						writemode_S <= LOCALHITS2;
+					else 
+						if timeoutcount_S(timeoutcount_S'left)='0' then
+							if data_out_fifofull='0' then
+								timeoutcount_S <= timeoutcount_S+1;
+							end if;
+						else
+							timeoutcount_S <= (others => '0');
+							errorout_S <= '1';
+							data_local_count_S <= 0;
+							writemode_S <= WAITNEXT;
+						end if;
+					end if;
+				when LOCALHITS2 =>
+					if (fifo_local_read_aftr1clk_S='1') then
+						data_out_S <= data_local_S;
+						data_out_write_S <= not enable_waveform;
+						data_out_last_S <= '1';
+						data_local_count_S <= 0;
+						writemode_S <= WAITNEXT;
+					else 
+						if timeoutcount_S(timeoutcount_S'left)='0' then
+							if data_out_fifofull='0' then
+								timeoutcount_S <= timeoutcount_S+1;
+							end if;
+						else
+							timeoutcount_S <= (others => '0');
+							errorout_S <= '1';
+							data_local_count_S <= 0;
+							writemode_S <= WAITNEXT;
+						end if;
+					end if;
+				when REMOTEHITS0 =>
+					data_out_S <= header_remote_hits1_S;
+					data_out_write_S <= not enable_waveform;
+					writemode_S <= REMOTEHITS1;
+				when REMOTEHITS1 => 
+					if (fifo_remote_read_aftr1clk_S='1') then
+						data_out_S <= data_remote_S;
+						data_out_write_S <= not enable_waveform;
+						writemode_S <= REMOTEHITS2;
+					else 
+						if timeoutcount_S(timeoutcount_S'left)='0' then
+							if data_out_fifofull='0' then
+								timeoutcount_S <= timeoutcount_S+1;
+							end if;
+						else
+							timeoutcount_S <= (others => '0');
+							errorout_S <= '1';
+							data_remote_count_S <= 0;
+							writemode_S <= WAITNEXT;
+						end if;
+					end if;
+				when REMOTEHITS2 =>
+					if (fifo_remote_read_aftr1clk_S='1') then
+						data_out_S <= data_remote_S;
+						data_out_write_S <= not enable_waveform;
+						data_out_last_S <= '1';
+						data_remote_count_S <= 0;
+						writemode_S <= WAITNEXT;
+					else 
+						if timeoutcount_S(timeoutcount_S'left)='0' then
+							if data_out_fifofull='0' then
+								timeoutcount_S <= timeoutcount_S+1;
+							end if;
+						else
+							timeoutcount_S <= (others => '0');
+							errorout_S <= '1';
+							data_remote_count_S <= 0;
+							writemode_S <= WAITNEXT;
+						end if;
+					end if;
+				when LOCALWAVES0 =>
+					data_out_S <= header_local_hits1_S;
+					data_out_write_S <= enable_waveform;
+					writemode_S <= LOCALWAVES1;
+				when LOCALWAVES1 =>
+					if (fifo_local_read_aftr1clk_S='1') then
+						data_out_S <= data_local_S;
+						data_out_write_S <= enable_waveform;
+						data_out_last_S <= data_local_last_S;
+						if data_local_last_S='1' then
+							data_local_count_S <= 0;
+							writemode_S <= WAITNEXT;
+						end if;
+					else 
+						if timeoutcount_S(timeoutcount_S'left)='0' then
+							if data_out_fifofull='0' then
+								timeoutcount_S <= timeoutcount_S+1;
+							end if;
+						else
+							timeoutcount_S <= (others => '0');
+							errorout_S <= '1';
+							data_local_count_S <= 0;
+							writemode_S <= WAITNEXT;
+						end if;
+					end if;
+				when REMOTEWAVES0 =>
+					data_out_S <= header_remote_hits1_S;
+					data_out_write_S <= enable_waveform;
+					writemode_S <= REMOTEWAVES1;
+				when REMOTEWAVES1 =>
+					if (fifo_remote_read_aftr1clk_S='1') then
+						data_out_S <= data_remote_S;
+						data_out_write_S <= enable_waveform;
+						data_out_last_S <= data_remote_last_S;
+						if data_remote_last_S='1' then
+							data_remote_count_S <= 0;
+							writemode_S <= WAITNEXT;
+						end if;
+					else 
+						if timeoutcount_S(timeoutcount_S'left)='0' then
+							if data_out_fifofull='0' then
+								timeoutcount_S <= timeoutcount_S+1;
+							end if;
+						else
+							timeoutcount_S <= (others => '0');
+							errorout_S <= '1';
+							data_remote_count_S <= 0;
+							writemode_S <= WAITNEXT;
+						end if;
+					end if;
+				when WAITNEXT =>
+					timeoutcount_S <= (others => '0');
+					if (data_local_count_S=2) and (data_local_type_S=SLOWCONTROL) then
+						data_out_S <= header_local_hits0_S;
+						data_out_first_S <= '1';
+						data_out_write_S <= '1';					
+						writemode_S <= LOCALSLOWCONTROL;
+					elsif (data_remote_count_S=2) and (data_remote_type_S=SLOWCONTROL) then
+						data_out_S <= header_remote_hits0_S;
+						data_out_first_S <= '1';
+						data_out_write_S <= '1';					
+						writemode_S <= REMOTESLOWCONTROL;
+					elsif ((data_local_count_S=2) and (data_remote_count_S=2)) then
+						local_timestamp_V := header_local_hits0_S(15 downto 0) & header_local_hits1_S(31 downto 16);
+						remote_timestamp_V := header_remote_hits0_S(15 downto 0) & header_remote_hits1_S(31 downto 16);
+						if ((local_timestamp_V(31 downto 0)<remote_timestamp_V(31 downto 0)) -- select local
+							or (((local_timestamp_V(31 downto 30)="11") and (remote_timestamp_V(31 downto 30)="00"))))
+								and (not ((local_timestamp_V(31 downto 30)="00") and (remote_timestamp_V(31 downto 30)="11"))) then
+							data_out_S <= header_local_hits0_S;
+							if data_local_type_S=HITDATA then
+								data_out_first_S <= '1';
+								data_out_write_S <= not enable_waveform;			
+								writemode_S <= LOCALHITS0;
+							elsif data_local_type_S=WAVEFORM then
+								data_out_first_S <= '1';
+								data_out_write_S <= enable_waveform;			
+								writemode_S <= LOCALWAVES0;
+							else 
+								data_local_count_S <= 0;
+								errorout_S <= '1';
+							end if;
+						else
+							data_out_S <= header_remote_hits0_S;
+							if data_remote_type_S=HITDATA then
+								data_out_first_S <= '1';
+								data_out_write_S <= not enable_waveform;			
+								writemode_S <= REMOTEHITS0;
+							elsif data_remote_type_S=WAVEFORM then
+								data_out_first_S <= '1';
+								data_out_write_S <= enable_waveform;			
+								writemode_S <= REMOTEWAVES0;
+							else 
+								data_remote_count_S <= 0;
+								errorout_S <= '1';
+							end if;
+						end if;
+					elsif ((data_local_count_S=2) and (fifo_remote_empty_S='1') and (data_remote_count_S/=2)) and (data_remote_inpipe_S='0') then
+						data_out_S <= header_local_hits0_S;
+						if data_local_type_S=HITDATA then
+							data_out_first_S <= '1';
+							data_out_write_S <= not enable_waveform;			
+							writemode_S <= LOCALHITS0;
+						elsif data_local_type_S=WAVEFORM then
+							data_out_first_S <= '1';
+							data_out_write_S <= enable_waveform;			
+							writemode_S <= LOCALWAVES0;
+						else 
+							data_local_count_S <= 0;
+							errorout_S <= '1';
+						end if;
+					elsif ((fifo_local_empty_S='1') and (data_local_count_S/=2) and (data_remote_count_S=2)) and (data_local_inpipe_S='0') then
+						data_out_S <= header_remote_hits0_S;
+						if data_remote_type_S=HITDATA then
+							data_out_first_S <= '1';
+							data_out_write_S <= not enable_waveform;			
+							writemode_S <= REMOTEHITS0;
+						elsif data_remote_type_S=WAVEFORM then
+							data_out_first_S <= '1';
+							data_out_write_S <= enable_waveform;			
+							writemode_S <= REMOTEWAVES0;
+						else 
+							data_remote_count_S <= 0;
+							errorout_S <= '1';
+						end if;
+					end if;
+				when others =>
+			end case;
+		end if;
+		fifo_local_read_aftr1clk_S <= data_local_read_S;
+		fifo_remote_read_aftr1clk_S <= data_remote_read_S;
+	end if;
+end process;
+	 
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_waveform_to_36bits.vhd b/FEE_ADC32board/FEE_modules/FEE_waveform_to_36bits.vhd
index 1c77815..1c37e36 100644
--- a/FEE_ADC32board/FEE_modules/FEE_waveform_to_36bits.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_waveform_to_36bits.vhd
@@ -1,225 +1,319 @@
-----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
--- Engineer:      Peter Schakel
--- Create Date:   01-02-2012
--- Module Name:   FEE_waveform_to_36bits
--- Description:   put waveform data in 36-bits wide data stream
--- Modifications:
---    14-08-2014: bug in read signal, output 'overflow_out' added
---    16-09-2014: name changed from waveform_to_36bits to FEE_waveform_to_36bits
---    11-10-2014: adc-channel number 8 bits
---    23-10-2014: finish actual waveform in case of almost full signal
-----------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.std_logic_ARITH.ALL;
-use IEEE.std_logic_UNSIGNED.ALL;
-use work.panda_package.all;
-
-
-------------------------------------------------------------------------------------------------------
--- FEE_waveform_to_36bits
---     Put waveform data in 36-bits wide data stream
---     Input waveform data is 36 bits wide, starting with timestamp and with the four highest bits for begin/time/end identification.
---     Output data is 36 bits wide with the four highest bits for identification
---
---
--- generics
---		
--- inputs
---     clock : ADC sampling clock 
---     reset : synchrounous reset
---     adcnumber : 8 bits indification of the adc channel
---     data_in : data from adc waveform buffer:
---          bits(35..32)="1000" : bits(31..0)=timestamp for pileup waveform
---          bits(35..32)="0010" : bits(31..16)=data sample, bits(15..0)=next data sample
---          bits(35..32)="0100" : bits(31..16)=last data sample, bits(15..0)=0000
---          bits(35..32)="0101" : bits(31..16)=last but one pulse data sample, bits(15..0)=last data sample
---          bits(35..32)="1111" : error, bits(31..0)=don't care
---     overflow_in : buffer overflow in adc waveform buffer, set bit in statusbyte
---     pileupdata_allowed : writing of pile-up data allowed
---     pileupdata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
---			  
--- outputs
---     data_in_read : read signal to adc waveform buffer
---     pileupdata_out : 36-bits data with pile-up waveform:
---          bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
---          bits(35..32)="0001" : 
---              bits(31..24) = statusbyte (bit6=overflow) 
---              bits(23..8) = 0
---              bits(7..0) = adcnumber (channel identifaction)
---          bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
---          bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
---          bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
---     pileupdata_write : write signal for pile-up data output
---     overflow_out : buffer overflow: data skipped
---     error : error in incoming data
---
--- components
---
-------------------------------------------------------------------------------------------------------
-
-
-
-entity FEE_waveform_to_36bits is
-    Port (
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		adcnumber               : in std_logic_vector(7 downto 0); 
-		data_in                 : in std_logic_vector(35 downto 0); 
-		data_in_available       : in std_logic;
-		data_in_read            : out std_logic;
-		overflow_in             : in std_logic;
-		pileupdata_out          : out std_logic_vector(35 downto 0);
-		pileupdata_write        : out std_logic;
-		pileupdata_allowed      : in std_logic;
-		pileupdata_almostfull   : in std_logic;
-		overflow_out            : out std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
-		);
-end FEE_waveform_to_36bits;
-
-architecture Behavioral of FEE_waveform_to_36bits is
-
-signal data_in_read_S            : std_logic := '0';
-signal data_in_read_after1clk_S  : std_logic := '0';
-signal pileupdata_write_S        : std_logic := '0';
-signal pileupdata_trywrite_S     : std_logic := '0';
-
-signal lastdata_S                : std_logic := '0';
-signal lastdata0_S               : std_logic := '0';
-signal lastdata1_S               : std_logic := '0';
-
-signal writingadcnumber_S        : std_logic := '0';
-signal writeadcnumber_S          : std_logic := '0';
+----------------------------------------------------------------------------------
+-- Company:       KVI-cart/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   01-02-2012
+-- Module Name:   FEE_waveform_to_36bits
+-- Description:   put waveform data in 36-bits wide data stream
+-- Modifications:
+--    14-08-2014: bug in read signal, output 'overflow_out' added
+--    16-09-2014: name changed from waveform_to_36bits to FEE_waveform_to_36bits
+--    11-10-2014: adc-channel number 8 bits
+--    23-10-2014: finish actual waveform in case of almost full signal
+--    23-10-2015: wavedata_inpipe added, earlier reading of data, outputs data when available 
+--    03-03-2017: signals renamed: wave instead of pileup
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+use work.panda_package.all;
+
+
+------------------------------------------------------------------------------------------------------
+-- FEE_waveform_to_36bits
+--     Put waveform data in 36-bits wide data stream
+--     Input waveform data is 36 bits wide, starting with timestamp and with the four highest bits for begin/time/end identification.
+--     Output data is 36 bits wide with the four highest bits for identification
+--
+--
+-- generics
+--     ADCNUMBER : indification of the adc channel
+--		
+-- inputs
+--     clock : ADC sampling clock 
+--     reset : synchrounous reset
+--     data_in : data from adc waveform buffer:
+--          bits(35..32)="1000" : bits(31..0)=timestamp for wave waveform
+--          bits(35..32)="0010" : bits(31..16)=data sample, bits(15..0)=next data sample
+--          bits(35..32)="0100" : bits(31..16)=last data sample, bits(15..0)=0000
+--          bits(35..32)="0101" : bits(31..16)=last but one pulse data sample, bits(15..0)=last data sample
+--          bits(35..32)="1111" : error, bits(31..0)=don't care
+--     overflow_in : buffer overflow in adc waveform buffer, set bit in statusbyte
+--     wavedata_allowed : writing of pile-up data allowed
+--     wavedata_almostfull : input fifo multiplexer is too full for complete maximum-length waveform
+--			  
+-- outputs
+--     data_in_read : read signal to adc waveform buffer
+--     wavedata_out : 36-bits data with pile-up waveform:
+--          bits(35..32)="0000" : bits(31..0)=timestamp of maximum value in waveform
+--          bits(35..32)="0001" : 
+--              bits(31..24) = statusbyte (bit6=overflow) 
+--              bits(23..8) = 0
+--              bits(7..0) = adcnumber (channel identifaction)
+--          bits(35..32)="0010" : bits(31..16)=adc sample, bits(15..0)=next adc sample
+--          bits(35..32)="0100" : bits(31..16)=last adc sample, bits(15..0)=0
+--          bits(35..32)="0101" : bits(31..16)=last but one adc sample, bits(15..0)=last adc sample
+--     wavedata_write : write signal for pile-up data output
+--     wavedata_inpipe : more data in pipeline available
+--     overflow_out : buffer overflow: data skipped
+--     error : error in incoming data
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+
+
+entity FEE_waveform_to_36bits is
+	generic (
+		ADCNUMBER               : natural := 0
+		);
+    port (
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(35 downto 0); 
+		data_in_available       : in std_logic;
+		data_in_read            : out std_logic;
+		overflow_in             : in std_logic;
+		wavedata_out            : out std_logic_vector(35 downto 0);
+		wavedata_write          : out std_logic;
+		wavedata_inpipe         : out std_logic;
+		wavedata_allowed        : in std_logic;
+		wavedata_almostfull     : in std_logic;
+		overflow_out            : out std_logic;
+		error                   : out std_logic
+		);
+end FEE_waveform_to_36bits;
+
+architecture Behavioral of FEE_waveform_to_36bits is
+
+signal data_in_read_S            : std_logic := '0';
+signal data_in_read_after1clk_S  : std_logic := '0';
+signal wavedata_write_S          : std_logic := '0';
+signal wavedata_trywrite_S       : std_logic := '0';
+signal skipthiswave_S            : std_logic := '0';
+
+signal writingadcnumber_S        : std_logic := '0';
+signal writeadcnumber_S          : std_logic := '0';
 signal overflow_occurred_S       : std_logic := '0';
 signal clear_overflow_occurred_S : std_logic := '0';
 signal overflow_in_S             : std_logic := '0';
-signal error1_S                  : std_logic := '0';
-signal pileupdata_out_S          : std_logic_vector(35 downto 0) := (others => '0');
-
-begin
-
-overflow_out <= overflow_occurred_S;
-error <= error1_S;
-data_in_read <= data_in_read_S;
-data_in_read_S <= '1' 
-	when (data_in_available='1') and (writingadcnumber_S='0') and (pileupdata_allowed='1') and 
-		((pileupdata_almostfull='0') or (lastdata_S='0'))--and (prevent_reading_S='0')
-		else '0';
-
-lastdata0_S <= '1' when (data_in_read_after1clk_S='1') and (data_in(35 downto 32)="010") else '0';
-lastdata_S <= '1' when (lastdata0_S='1') or (lastdata1_S='1') else '0';
-process(clock)
-begin
-	if rising_edge(clock) then
-		if reset='1' then
-			lastdata1_S <= '0';
-		else
-			if data_in_read_after1clk_S='1' then
-				lastdata1_S <= lastdata0_S;
-			end if;
+signal error_S                   : std_logic := '0';
+signal error1_S                  : std_logic := '0';
+signal wavedata_out_S            : std_logic_vector(35 downto 0) := (others => '0');
+signal data_in_saved_S           : std_logic := '0';
+signal wavedata_allowed_S        : std_logic := '0';
+signal data_in_S                 : std_logic_vector(35 downto 0) := (others => '0');
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of data_in_read_after1clk_S : signal is "true";
+-- attribute mark_debug of wavedata_write_S : signal is "true";
+-- attribute mark_debug of wavedata_trywrite_S : signal is "true";
+-- attribute mark_debug of writingadcnumber_S : signal is "true";
+-- attribute mark_debug of writeadcnumber_S : signal is "true";
+-- attribute mark_debug of data_in_saved_S : signal is "true";
+-- attribute mark_debug of error_S : signal is "true";
+-- attribute mark_debug of error1_S : signal is "true";
+-- attribute mark_debug of overflow_occurred_S : signal is "true";
+-- attribute mark_debug of overflow_in_S : signal is "true";
+
+
+begin
+
+overflow_out <= overflow_occurred_S;
+error <= error1_S;
+--wavedata_inpipe <= '1' when (wavedata_trywrite_S='1') or (data_in_available='1') or (data_in_saved_S='1') or (data_in_read_after1clk_S='1') or (data_in_read_S='1') else '0';
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		if (wavedata_trywrite_S='1') or (data_in_available='1') or (data_in_saved_S='1') or (data_in_read_after1clk_S='1') or (data_in_read_S='1') then
+			wavedata_inpipe <= '1';
+		else
+			wavedata_inpipe <= '0';
 		end if;
 	end if;
-end process;
-		
-writingadcnumber_S <= '1' when 
-		(writeadcnumber_S='1') 
-		or ((data_in_read_after1clk_S='1') and (data_in(34 downto 32)="000")) 
-	else '0';
-
-pileupdata_out <= pileupdata_out_S;	
-
-pileupdata_write <= pileupdata_write_S;
-pileupdata_write_S <= '1' when (pileupdata_trywrite_S='1') and (pileupdata_allowed='1') else '0';
-
-readprocess: process(clock)
-variable statusbyte_V            : std_logic_vector(7 downto 0) := (others => '0');
-begin
+end process;
+
+data_in_read <= data_in_read_S;
+--data_in_read_S <= '1' 
+--	when (data_in_available='1') and (writingadcnumber_S='0') and (wavedata_allowed='1') --and 
+--		else '0';
+
+data_in_read_S <= '1' when 
+((wavedata_allowed='1') or ((data_in_saved_S='0') and (wavedata_allowed='0') and (wavedata_allowed_S='0') and (data_in_read_after1clk_S='0')))
+ and (data_in_available='1') and (data_in_saved_S='0') and (writingadcnumber_S='0') else '0';
+
+
+--lastdata0_S <= '1' when (data_in_read_after1clk_S='1') and (data_in(35 downto 33)="010") else '0';
+--lastdata_S <= '1' when (lastdata0_S='1') or (lastdata1_S='1') else '0';
+--process(clock)
+--begin
+--	if rising_edge(clock) then
+--		if reset='1' then
+--			lastdata1_S <= '0';
+--		else
+--			if data_in_read_after1clk_S='1' then
+--				lastdata1_S <= lastdata0_S;
+--			end if;
+--		end if;
+--	end if;
+--end process;
+		
+writingadcnumber_S <= '1' when 
+		(writeadcnumber_S='1') 
+		or ((data_in_read_after1clk_S='1') and (data_in(34 downto 32)="000")) 
+	else '0';
+
+wavedata_out <= wavedata_out_S;	
+
+wavedata_write <= wavedata_write_S;
+wavedata_write_S <= '1' when (wavedata_trywrite_S='1') and (wavedata_allowed='1') else '0';
+
+readprocess: process(clock)
+variable statusbyte_V            : std_logic_vector(7 downto 0) := (others => '0');
+begin
 	if rising_edge(clock) then
 		error1_S <= '0';
-		clear_overflow_occurred_S <= '0';
-		if reset='1' then
-			pileupdata_trywrite_S <= '0';
-			writeadcnumber_S <= '0';
-			statusbyte_V := (others => '0');
-			overflow_occurred_S <= '0';
+		clear_overflow_occurred_S <= '0';
+		if reset='1' then
+			wavedata_trywrite_S <= '0';
+			writeadcnumber_S <= '0';
+			statusbyte_V := (others => '0');
+			overflow_occurred_S <= '0';
 			data_in_read_after1clk_S <= '0';
-			overflow_in_S <= overflow_in;
-		else
-			if ((overflow_in='1') and (overflow_in_S='0')) or (error1_S='1') then
+			overflow_in_S <= overflow_in;
+		else
+			if ((overflow_in='1') and (overflow_in_S='0')) or (error1_S='1') then
 				overflow_occurred_S <= '1';
 			elsif clear_overflow_occurred_S='1' then
 				overflow_occurred_S <= '0';
 			end if;
-			overflow_in_S <= overflow_in;
-			data_in_read_after1clk_S <= data_in_read_S;
-			if data_in_read_after1clk_S='1' then
-				case data_in(35 downto 32) is
-					when "1000" =>
-						pileupdata_out_S <= "0000" & data_in(31 downto 0);
-						pileupdata_trywrite_S <= '1';
-						writeadcnumber_S <= '1';
-					when "0010" => -- samples
-						writeadcnumber_S <= '0';
-						pileupdata_out_S <= data_in;
-						pileupdata_trywrite_S <= '1';
-					when "0100" => -- last sample
-						writeadcnumber_S <= '0';
-						pileupdata_out_S <= data_in;
-						pileupdata_trywrite_S <= '1';
-					when "0101" => -- last samples
-						writeadcnumber_S <= '0';
-						pileupdata_out_S <= data_in;
-						pileupdata_trywrite_S <= '1';
-					when others =>
-						error1_S <= '1';
-						pileupdata_trywrite_S <= '0';
-				end case;
-			else -- not data_in_read_after1clk_S
-				if (writeadcnumber_S='1') and (pileupdata_trywrite_S='1') and (pileupdata_allowed='1') then
+			overflow_in_S <= overflow_in;
+			data_in_read_after1clk_S <= data_in_read_S;
+
+			if (wavedata_write_S='0') and (wavedata_trywrite_S='1') then -- unsuccesfull try again
+				wavedata_trywrite_S <= '1';
+				if data_in_read_after1clk_S='1' then
+					data_in_S <= data_in;
+					data_in_saved_S <= '1';
+				end if;
+			elsif data_in_saved_S='1' then -- write saved data
+				case data_in_S(35 downto 32) is
+					when "1000" =>
+						wavedata_out_S <= "0000" & data_in_S(31 downto 0);
+						if wavedata_almostfull='1' then
+							overflow_occurred_S <= '1';
+							skipthiswave_S <= '1';
+							wavedata_trywrite_S <= '0';
+						else
+							skipthiswave_S <= '0';
+							wavedata_trywrite_S <= '1';
+						end if;
+						writeadcnumber_S <= '1';
+					when "0010" => -- samples
+						writeadcnumber_S <= '0';
+						wavedata_out_S <= data_in_S;
+						wavedata_trywrite_S <= not skipthiswave_S;
+					when "0100" => -- last sample
+						writeadcnumber_S <= '0';
+						wavedata_out_S <= data_in_S;
+						wavedata_trywrite_S <= not skipthiswave_S;
+					when "0101" => -- last samples
+						writeadcnumber_S <= '0';
+						wavedata_out_S <= data_in_S;
+						wavedata_trywrite_S <= not skipthiswave_S;
+					when others =>
+						error1_S <= '1';
+						writeadcnumber_S <= '0';
+						wavedata_trywrite_S <= '0';
+						skipthiswave_S <= '1';
+				end case;
+				if data_in_read_after1clk_S='1' then -- save next data
+					data_in_S <= data_in;
+					data_in_saved_S <= '1';
+				else
+					data_in_saved_S <= '0';
+				end if;
+			elsif data_in_read_after1clk_S='1' then
+				case data_in(35 downto 32) is
+					when "1000" =>
+						wavedata_out_S <= "0000" & data_in(31 downto 0);
+						if wavedata_almostfull='1' then
+							overflow_occurred_S <= '1';
+							skipthiswave_S <= '1';
+							wavedata_trywrite_S <= '0';
+						else
+							skipthiswave_S <= '0';
+							wavedata_trywrite_S <= '1';
+						end if;
+						writeadcnumber_S <= '1';
+					when "0010" => -- samples
+						writeadcnumber_S <= '0';
+						wavedata_out_S <= data_in;
+						wavedata_trywrite_S <= not skipthiswave_S;
+					when "0100" => -- last sample
+						writeadcnumber_S <= '0';
+						wavedata_out_S <= data_in;
+						wavedata_trywrite_S <= not skipthiswave_S;
+					when "0101" => -- last samples
+						writeadcnumber_S <= '0';
+						wavedata_out_S <= data_in;
+						wavedata_trywrite_S <= not skipthiswave_S;
+					when others =>
+						error1_S <= '1';
+						writeadcnumber_S <= '0';
+						wavedata_trywrite_S <= '0';
+						skipthiswave_S <= '1';
+				end case;
+			else -- not data_in_read_after1clk_S
+				if (writeadcnumber_S='1') and (wavedata_trywrite_S='1') and (wavedata_allowed='1') and (skipthiswave_S='0') then
 					if overflow_occurred_S='1' then
-						statusbyte_V := STATBYTE_FEEPULSESKIPPED;
-						clear_overflow_occurred_S <= '1';
-					else	
-						statusbyte_V := (others => '0');
-					end if;
-					pileupdata_out_S <= "0001" & statusbyte_V & x"0000" & adcnumber;
-					pileupdata_trywrite_S <= '1';
-					writeadcnumber_S <= '0';
-				elsif (pileupdata_trywrite_S='1') and (pileupdata_allowed='0') then -- keep trying
-					pileupdata_trywrite_S <= '1';
-				elsif (writeadcnumber_S='1') then
-					writeadcnumber_S <= '0';
-				else
-					pileupdata_trywrite_S <= '0';
-				end if;
-			end if;
-		end if;
-	end if;
-end process;
-
-
-testword0(3 downto 0) <= data_in(35 downto 32);
-testword0(4) <= data_in_read_S;
-testword0(5) <= data_in_available;
-testword0(6) <=  data_in_read_after1clk_S;
-testword0(7) <= data_in_read_S;
-testword0(11 downto 8) <= pileupdata_out_S(35 downto 32);
-testword0(12) <= pileupdata_write_S;
-testword0(13) <= pileupdata_trywrite_S;
-testword0(14) <= writingadcnumber_S;
-testword0(15) <= writeadcnumber_S;
-testword0(16) <= overflow_occurred_S;
-testword0(17) <= clear_overflow_occurred_S;
-testword0(18) <= overflow_in_S;
-testword0(19) <= error1_S;
-testword0(20) <= pileupdata_allowed;
-testword0(21) <= pileupdata_almostfull;
-testword0(22) <= writeadcnumber_S;
-
-end Behavioral;
-
-
+						statusbyte_V := STATBYTE_FEEPULSESKIPPED;
+						clear_overflow_occurred_S <= '1';
+					else	
+						statusbyte_V := (others => '0');
+					end if;
+					wavedata_out_S <= "0001" & statusbyte_V & x"0000" & conv_std_logic_vector(ADCNUMBER,8);
+					wavedata_trywrite_S <= '1';
+					writeadcnumber_S <= '0';
+				elsif (writeadcnumber_S='1') then
+					writeadcnumber_S <= '0';
+				else
+					wavedata_trywrite_S <= '0';
+				end if;
+			end if;
+		end if;
+		wavedata_allowed_S <= wavedata_allowed;
+	end if;
+end process;
+
+process(clock)
+variable prevdata_V : std_logic_vector(3 downto 0) := "0000";
+begin
+	if (rising_edge(clock)) then 
+		error_S <= '0';
+		if wavedata_write_S='1' then
+			if (wavedata_out_S(35 downto 32)="0000") then
+				if (prevdata_V(3 downto 1)/="010") then error_S <= '1'; end if;
+			elsif (wavedata_out_S(35 downto 32)="0001") then
+				if (prevdata_V/="0000") then error_S <= '1'; end if;
+			elsif (wavedata_out_S(35 downto 32)="0010") then
+				if (prevdata_V/="0010") and (prevdata_V/="0001") then error_S <= '1'; end if;
+			elsif (wavedata_out_S(35 downto 32)="0100") then
+				if (prevdata_V/="0010") then error_S <= '1'; end if;
+			elsif (wavedata_out_S(35 downto 32)="0101") then 
+				if (prevdata_V/="0010") then error_S <= '1'; end if;
+			else
+				error_S <= '1';
+			end if;
+			prevdata_V := wavedata_out_S(35 downto 32);
+		end if;
+	end if;
+end process;
+
+
+
+end Behavioral;
+
+
diff --git a/FEE_ADC32board/FEE_modules/FEE_wavemux2to1.vhd b/FEE_ADC32board/FEE_modules/FEE_wavemux2to1.vhd
index c1cc47d..572e41d 100644
--- a/FEE_ADC32board/FEE_modules/FEE_wavemux2to1.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_wavemux2to1.vhd
@@ -1,12 +1,15 @@
-----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
--- Engineer:      Peter Schakel
--- Create Date:   03-02-2012
--- Module Name:   FEE_wavemux2to1
--- Description:   compare timestamp of 36bits data pass on first
--- Modifications:
---    11-10-2014: adc-channel number 8 bits
---    23-10-2014: proper end of packet in case of timeout
+----------------------------------------------------------------------------------
+-- Company:       KVI-cart/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   03-02-2012
+-- Module Name:   FEE_wavemux2to1
+-- Description:   compare timestamp of 36bits data pass on first
+-- Modifications:
+--    11-10-2014: adc-channel number 8 bits
+--    23-10-2014: proper end of packet in case of timeout
+--    25-09-2015: compare bug fixed at FFFF->0000 superburst change
+--    23-10-2015: code rewritten, now without variables
+--    20-01-2017: check on valid first word for passing on new values
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -32,10 +35,11 @@ use IEEE.std_logic_UNSIGNED.ALL;
 --
 --
 -- generics
+--		TIMEOUTBITS : number of bits for timeout counter inwhich time the next word should be available
 --		
 -- inputs
 --		clock : ADC sampling clock 
---		reset : synchrounous reset
+--		reset : synchronous reset
 --		data1_in : data from first 36-bits input
 --        	bits(35..32)="0000" : bits(31..16)=superburst, bits(15..0)=timestamp within superburst
 --        	bits(35..32)="0001" : 
@@ -75,6 +79,7 @@ use IEEE.std_logic_UNSIGNED.ALL;
 --		data_out_write : write signal for 36-bits output data
 --    data_out_available : data available: in this module or at the input
 --    error : error in data bits 35..32
+--    timeerror : error in time of output wave, only for debug
 --
 -- components
 --
@@ -83,293 +88,316 @@ use IEEE.std_logic_UNSIGNED.ALL;
 
 
 entity FEE_wavemux2to1 is
-	generic(
-		TIMEOUTBITS             : natural := 6
-	);
+	generic(
+		TIMEOUTBITS             : natural := 8
+	);
 	Port (
-		clock                   : in std_logic;
+		clock                   : in std_logic;
 		reset                   : in std_logic;
 		data1_in                : in std_logic_vector(35 downto 0); 
 		data1_in_write          : in std_logic;
-		data1_in_available      : in std_logic;
+		data1_in_available      : in std_logic;
 		data1_in_allowed        : out std_logic;
 		data2_in                : in std_logic_vector(35 downto 0); 
 		data2_in_write          : in std_logic;
-		data2_in_available      : in std_logic;
+		data2_in_available      : in std_logic;
 		data2_in_allowed        : out std_logic;
 		data_out                : out std_logic_vector(35 downto 0);
 		data_out_write          : out std_logic;
-		data_out_available      : out std_logic;
+		data_out_available      : out std_logic;
 		data_out_allowed        : in std_logic;
-		error                   : out std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
+		error                   : out std_logic;
+		timeerror               : out std_logic
 	);
 end FEE_wavemux2to1;
 
 
 architecture Behavioral of FEE_wavemux2to1 is
 
-signal timeout_counter_S         : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
-
-signal error_S                   : std_logic := '0';
-signal read_pulse1_S             : std_logic := '0';
-signal read_pulse2_S             : std_logic := '0';
-signal data1_in_allowed_S        : std_logic := '0';
+--//signal timeout_counter_S         : std_logic_vector(TIMEOUTBITS downto 0) := (others => '0');
+signal clear_timeout_counter_S   : std_logic := '0';
+signal inc_timeout_counter_S     : std_logic := '0';
+
+signal error_S                   : std_logic := '0';
+signal read_pulse1_S             : std_logic := '0';
+signal read_pulse2_S             : std_logic := '0';
+signal data1_in_allowed_S        : std_logic := '0';
 signal data2_in_allowed_S        : std_logic := '0';
 signal data1_in_write_S          : std_logic := '0';
-signal data2_in_write_S          : std_logic := '0';
-signal data_out_trywrite_S       : std_logic := '0';
-signal data_out_write_S          : std_logic := '0';
-signal data_out_available_S      : std_logic := '0';
-signal data_out_S                : std_logic_vector(35 downto 0) := (others => '0');
-signal data1_timestamp_valid_S   : std_logic := '0';
-signal data2_timestamp_valid_S   : std_logic := '0';
-
+signal data2_in_write_S          : std_logic := '0';
+signal data_out_trywrite_S       : std_logic := '0';
+signal data_out_write_S          : std_logic := '0';
+signal data_out_available_S      : std_logic;
+signal data_out_S                : std_logic_vector(35 downto 0);
+signal prevdata1first_S          : std_logic := '0';
+signal prevdata2first_S          : std_logic := '0';
+signal selectdata1_S             : std_logic;
+signal data_outfilled_S          : std_logic := '0';
+
+signal data1_in_available_S      : std_logic;
+signal data2_in_available_S      : std_logic;
+
+signal timeerror_S               : std_logic;
+signal prevdataout_S             : std_logic_vector(31 downto 0);
+signal derror_S                  : std_logic := '0';
+
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of error_S : signal is "true";
+-- attribute mark_debug of data1_in_available : signal is "true";
+-- attribute mark_debug of read_pulse1_S : signal is "true";
+-- attribute mark_debug of data1_in_write_S : signal is "true";
+-- attribute mark_debug of data2_in_available : signal is "true";
+-- attribute mark_debug of read_pulse2_S : signal is "true";
+-- attribute mark_debug of data2_in_write_S : signal is "true";
+-- attribute mark_debug of timeout_counter_S : signal is "true";
+-- attribute mark_debug of data_out_trywrite_S : signal is "true";
+-- attribute mark_debug of data_out_write_S : signal is "true";
+-- attribute mark_debug of data_out_allowed : signal is "true";
+
+
 begin
 
-error <= error_S;
+error <= error_S;
+
+data1_in_available_S <= data1_in_available;
+data2_in_available_S <= data2_in_available;
+
 
 data_out_available <= data_out_available_S;
-data_out_available_S <= '1' when (data1_in_available='1') or (data2_in_available='1') 
-		or (data_out_trywrite_S='1') 
-		or (data1_timestamp_valid_S='1') or (data2_timestamp_valid_S='1')
-	else '0';
-
-data_out <= data_out_S;
-data_out_write <= data_out_write_S;
-data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
-
-data1_in_allowed <= data1_in_allowed_S;
-data1_in_allowed_S <= '1' when (data_out_allowed='1')
-	and ((read_pulse1_S='1') 
-		or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data1_timestamp_valid_S='0')))
-	else '0';
-
-data2_in_allowed <= data2_in_allowed_S;
-data2_in_allowed_S <= '1' when (data_out_allowed='1')
-	and ((read_pulse2_S='1') 
-		or ((read_pulse1_S='0') and (read_pulse2_S='0') and (data2_timestamp_valid_S='0')))
-	else '0';
-
---data2_in_allowed_S <= '1' when (data_out_allowed='1')
---	and ((read_pulse2_S='1') 
---		or (((read_pulse1_S='0') and (data1_timestamp_valid_S='0')) 
---			and ((read_pulse2_S='0') and (data2_timestamp_valid_S='0'))))
---	else '0';
-
+data_out_available_S <= '1' when (data1_in_available_S='1') or (data2_in_available_S='1') 
+		or (data_out_trywrite_S='1') or (read_pulse1_S='1') or (read_pulse2_S='1')
+	else '0';
+
+data_out <= data_out_S;
+data_out_write <= data_out_write_S;
+data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+
+selectdata1_S <= '1' when 
+	((data1_in(31 downto 0)<data2_in(31 downto 0))
+		or (((data1_in(31 downto 30)="11") and (data2_in(31 downto 30)="00")))) 
+			and (not ((data1_in(31 downto 30)="00") and (data2_in(31 downto 30)="11"))) 
+	else '0';
+data1_in_allowed <= data1_in_allowed_S; 
+--data1_in_allowed_S <= '1' when ((data_outfilled_S='0') or ((data_out_trywrite_S='1') and (data_out_write_S='1'))) and
+data1_in_allowed_S <= '1' when ((data_out_trywrite_S='0') or ((data_out_trywrite_S='1') and (data_out_write_S='1'))) and
+	 ((read_pulse1_S='1') 
+		or ((read_pulse2_S='0') and (data1_in(35 downto 32)="0000") and (data2_in(35 downto 32)="0000") and (selectdata1_S='1'))
+		or ((read_pulse2_S='0') and (data2_in_available_S='0'))
+--//		or ((timeout_counter_S(TIMEOUTBITS)='1') and (selectdata1_S='1'))
+		)
+	else '0';
+data2_in_allowed <= data2_in_allowed_S;
+--data2_in_allowed_S <= '1' when ((data_outfilled_S='0') or ((data_out_trywrite_S='1') and (data_out_write_S='1'))) and
+data2_in_allowed_S <= '1' when ((data_out_trywrite_S='0') or ((data_out_trywrite_S='1') and (data_out_write_S='1'))) and
+	 ((read_pulse2_S='1') 
+		or ((read_pulse1_S='0') and (data1_in(35 downto 32)="0000") and (data2_in(35 downto 32)="0000") and (selectdata1_S='0'))
+		or ((read_pulse1_S='0') and (data1_in_available_S='0'))
+--//		or ((timeout_counter_S(TIMEOUTBITS)='1') and (selectdata1_S='0'))
+		)
+	else '0';
+
+	
 data1_in_write_S <= '1' when (data1_in_write='1') and (data1_in_allowed_S='1') else '0';
 data2_in_write_S <= '1' when (data2_in_write='1') and (data2_in_allowed_S='1') else '0';
-
+
 readprocess: process(clock)
-variable data1_timestamp_V       : std_logic_vector(31 downto 0) := (others => '0');
-variable data2_timestamp_V       : std_logic_vector(31 downto 0) := (others => '0');
-variable data1_timestamp_valid_V : std_logic := '0';
-variable data2_timestamp_valid_V : std_logic := '0';
-begin
-	if rising_edge(clock) then
-		if reset='1' then
-			data_out_trywrite_S <= '0';
-			read_pulse1_S <= '0';
-			read_pulse2_S <= '0';
-			data1_timestamp_valid_V := '0';
-			data2_timestamp_valid_V := '0';
-			data1_timestamp_valid_S <= '0';
-			data2_timestamp_valid_S <= '0';
-			timeout_counter_S <= (others => '0');
+begin
+	if rising_edge(clock) then
+		clear_timeout_counter_S <= '0';
+		inc_timeout_counter_S <= '0';
+		error_S <= '0'; --// timeout_counter_S(TIMEOUTBITS);
+		if reset='1' then
+			data_out_trywrite_S <= '0';
+			data_outfilled_S <= '0';
+			read_pulse1_S <= '0';
+			read_pulse2_S <= '0';
+			clear_timeout_counter_S <= '1';
 		else
-			if (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
-				data_out_trywrite_S <= '1'; -- try again
-				timeout_counter_S <= (others => '0');
+			if (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
+				data_outfilled_S <= '1';
+				data_out_trywrite_S <= '1'; -- try again
+				clear_timeout_counter_S <= '1';
 			else
+				if (data_out_trywrite_S='1') and (data_out_write_S='1') then -- succesful write
+					data_outfilled_S <= '0';
+				end if;	
 				if read_pulse1_S='1' then
-					data1_timestamp_valid_V := '0';
 					if data1_in_write_S='1' then
-						timeout_counter_S <= (others => '0');
+						clear_timeout_counter_S <= '1';
 						if (data1_in(35 downto 32)="0001") or (data1_in(35 downto 32)="0010") then -- next data
-							error_S <= '0';
-							data_out_S <= data1_in;
+							data_out_S <= data1_in;
 							data_out_trywrite_S <= '1';
+							data_outfilled_S <= '1';
 						elsif (data1_in(35 downto 33)="010") then -- last data
-							error_S <= '0';
 							data_out_S <= data1_in;
-							read_pulse1_S <= '0';
+							read_pulse1_S <= '0';
 							data_out_trywrite_S <= '1';
+							data_outfilled_S <= '1';
 						else -- error
 							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
+							read_pulse1_S <= '0';
+							read_pulse2_S <= '0';
 							data_out_trywrite_S <= '0';
+							data_outfilled_S <= '0';
 						end if;
 					else
-						data_out_trywrite_S <= '0';
-						if timeout_counter_S(TIMEOUTBITS-1)='1' then
-							data_out_S <= "0100" & x"00000000"; -- force last data
-							data_out_trywrite_S <= '1';
-							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
-							timeout_counter_S <= (others => '0');
-						else
+--//						-- if timeout_counter_S(TIMEOUTBITS)='1' then
+							-- data_out_S <= "0100" & x"00000000"; -- force last data
+							-- data_out_trywrite_S <= '1';
+							-- error_S <= '1';
+							-- read_pulse1_S <= '0';
+							-- read_pulse2_S <= '0';
+							-- clear_timeout_counter_S <= '1';
+							-- data_outfilled_S <= '1';
+						-- else
+							data_out_trywrite_S <= '0';
+							data_outfilled_S <= '0';
 							if data_out_allowed='1' then
 								if data_out_write_S='1' then
-									timeout_counter_S <= (others => '0');
+									clear_timeout_counter_S <= '1';
 								else
-									timeout_counter_S <= timeout_counter_S+1;
+									inc_timeout_counter_S <= '1';
 								end if;
 							end if;
-							error_S <= '0';
-						end if;
-					end if;
+--//						end if;
+					end if;
 				elsif read_pulse2_S='1' then
-					data2_timestamp_valid_V := '0';
 					if data2_in_write_S='1' then
-						timeout_counter_S <= (others => '0');
+						clear_timeout_counter_S <= '1';
 						if (data2_in(35 downto 32)="0001") or (data2_in(35 downto 32)="0010") then -- next data
-							error_S <= '0';
-							data_out_S <= data2_in;
+							data_out_S <= data2_in;
 							data_out_trywrite_S <= '1';
+							data_outfilled_S <= '1';
 						elsif (data2_in(35 downto 33)="010") then -- last data
-							error_S <= '0';
 							data_out_S <= data2_in;
-							read_pulse2_S <= '0';
+							read_pulse2_S <= '0';
 							data_out_trywrite_S <= '1';
+							data_outfilled_S <= '1';
 						else -- error
 							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
+							read_pulse1_S <= '0';
+							read_pulse2_S <= '0';
 							data_out_trywrite_S <= '0';
+							data_outfilled_S <= '0';
 						end if;
 					else
-						data_out_trywrite_S <= '0';
-						if timeout_counter_S(TIMEOUTBITS-1)='1' then
-							data_out_S <= "0100" & x"00000000"; -- force last data
-							data_out_trywrite_S <= '1';
-							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
-							timeout_counter_S <= (others => '0');
-						else
+--//						-- if timeout_counter_S(TIMEOUTBITS)='1' then
+							-- data_out_S <= "0100" & x"00000000"; -- force last data
+							-- data_out_trywrite_S <= '1';
+							-- error_S <= '1';
+							-- read_pulse1_S <= '0';
+							-- read_pulse2_S <= '0';
+							-- clear_timeout_counter_S <= '1';
+							-- data_outfilled_S <= '1';
+						-- else
+							data_out_trywrite_S <= '0';
+							data_outfilled_S <= '0';
 							if data_out_allowed='1' then
 								if data_out_write_S='1' then
-									timeout_counter_S <= (others => '0');
+									clear_timeout_counter_S <= '1';
 								else
-									timeout_counter_S <= timeout_counter_S+1;
+									inc_timeout_counter_S <= '1';
 								end if;
-							end if;
-							error_S <= '0';
+--//							end if;
 						end if;
 					end if;
 				else
-					timeout_counter_S <= (others => '0');
 					if data1_in_write_S='1' then
-						if (data1_in(35 downto 32)="0000") then
-							data1_timestamp_V := data1_in(31 downto 0);
-							data1_timestamp_valid_V := '1';
-						else -- error
-							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
-						end if;
-					end if;
-					if data2_in_write_S='1' then
-						if (data2_in(35 downto 32)="0000") then
-							data2_timestamp_V := data2_in(31 downto 0);
-							data2_timestamp_valid_V := '1';
-						else -- error
-							error_S <= '1';
-							read_pulse1_S <= '0';
-							read_pulse2_S <= '0';
-							data1_timestamp_valid_V := '0';
-							data2_timestamp_valid_V := '0';
-						end if;
-					end if;
-					if data1_timestamp_valid_V='1' then
-						if data2_timestamp_valid_V='1' then
-							if (data1_timestamp_V(31 downto 0)<data2_timestamp_V(31 downto 0)) -- select 1
-									or (((data1_timestamp_V(31 downto 30)="11") and (data2_timestamp_V(31 downto 30)="00"))) then
-								read_pulse1_S <= '1';
-								data1_timestamp_valid_V := '0';
-								data_out_trywrite_S <= '1';						
-								data_out_S <= "0000" & data1_timestamp_V;
-							else -- select 2
-								read_pulse2_S <= '1';
-								data2_timestamp_valid_V := '0';
-								data_out_trywrite_S <= '1';						
-								data_out_S <= "0000" & data2_timestamp_V;
+						read_pulse1_S <= '1';
+						read_pulse2_S <= '0';
+						data_out_S <= data1_in;
+						data_out_trywrite_S <= '1';
+						clear_timeout_counter_S <= '1';
+						data_outfilled_S <= '1';
+					elsif data2_in_write_S='1' then
+						read_pulse1_S <= '0';
+						read_pulse2_S <= '1';
+						data_out_S <= data2_in;
+						data_out_trywrite_S <= '1';
+						clear_timeout_counter_S <= '1';
+						data_outfilled_S <= '1';
+					else
+						if (data1_in_available='1') and (data2_in_available='0') then
+							clear_timeout_counter_S <= '1';
+							data_out_S <= data1_in;
+						elsif (data1_in_available='0') and (data2_in_available='1') then
+							clear_timeout_counter_S <= '1';
+							data_out_S <= data2_in;
+						elsif (data1_in_available='1') and (data2_in_available='1') then
+                            if (data1_in(35 downto 32)="0000") and (data2_in(35 downto 32)="0000") then
+                                if (selectdata1_S='0')  then
+                                    data_out_S <= data2_in;
+                                else
+                                    data_out_S <= data1_in;
+                                end if;
+                            end if;
+							if data_out_allowed='1' then
+--//								-- if (timeout_counter_S(TIMEOUTBITS)='0') then
+									-- inc_timeout_counter_S <= '1';
+								-- else
+									-- error_S <= '1';
+								-- end if;
+							else
+								clear_timeout_counter_S <= '1';
 							end if;
-						elsif data2_in_available='1' then -- data expected: wait
-							data_out_trywrite_S <= '0';
-						else -- write 1
-							read_pulse1_S <= '1';
-							data1_timestamp_valid_V := '0';
-							data_out_trywrite_S <= '1';						
-							data_out_S <= "0000" & data1_timestamp_V;							
-						end if;
-					elsif data2_timestamp_valid_V='1' then
-						if data1_in_available='1' then -- data expected: wait
-							data_out_trywrite_S <= '0';
-						else -- write 2
-							read_pulse2_S <= '1';
-							data2_timestamp_valid_V := '0';
-							data_out_trywrite_S <= '1';						
-							data_out_S <= "0000" & data2_timestamp_V;							
 						end if;
-					else -- no valid timestamps
+						data_outfilled_S <= '0';
 						data_out_trywrite_S <= '0';
 					end if;
 				end if;					
-				data1_timestamp_valid_S <= data1_timestamp_valid_V;
-				data2_timestamp_valid_S <= data2_timestamp_valid_V;
-			end if;
-		end if;
-	end if;
-end process;
-						
-
-
-
--- testword0 <= (others => '0');
-
-testword0(0) <= data1_in_write;
-testword0(1) <= data1_in_available;
-testword0(2) <= data1_in_allowed_S;
-testword0(3) <= read_pulse1_S;
-testword0(4) <= data1_in_write_S;
-testword0(5) <= data1_timestamp_valid_S;
-testword0(9 downto 6) <= data1_in(35 downto 32);
+			end if;
+		end if;
+	end if;
+end process;
+						
+--//-- process(clock)
+-- begin
+	-- if rising_edge(clock) then	
+		-- if (reset='1') or (clear_timeout_counter_S='1') then
+			-- timeout_counter_S <= (others => '0');
+		-- elsif inc_timeout_counter_S='1' then
+			-- timeout_counter_S <= timeout_counter_S+1;
+		-- end if;
+	-- end if;
+-- end process;
 
-testword0(10) <= data2_in_write;
-testword0(11) <= data2_in_available;
-testword0(12) <= data2_in_allowed_S;
-testword0(13) <= read_pulse2_S;
-testword0(14) <= data2_in_write_S;
-testword0(15) <= data2_timestamp_valid_S;
-testword0(19 downto 16) <= data2_in(35 downto 32);
-
-
-testword0(20) <= data_out_trywrite_S;
-testword0(21) <= data_out_write_S;
-testword0(22) <= data_out_available_S;
-testword0(23) <= data_out_allowed;
-testword0(27 downto 24) <= data_out_S(35 downto 32);
-testword0(28) <= error_S;
+process(clock)
+begin
+	if rising_edge(clock) then
+		timeerror_S <= '0';
+		if (data_out_write_S='1') and (data_out_S(35 downto 32)="0000") then 
+			if data_out_S(31 downto 0)<prevdataout_S then
+				timeerror_S <= '1';
+			end if;
+			prevdataout_S <= data_out_S(31 downto 0);
+		end if;
+	end if;
+end process;
+timeerror <= timeerror_S;
+	
+process(clock)
+variable prevdata_V : std_logic_vector(3 downto 0) := "0000";
+begin
+	if (rising_edge(clock)) then 
+		derror_S <= '0';
+		if data_out_write_S='1' then
+			if (data_out_S(35 downto 32)="0000") then
+				if (prevdata_V(3 downto 1)/="010") then derror_S <= '1'; end if;
+			elsif (data_out_S(35 downto 32)="0001") then
+				if (prevdata_V/="0000") then derror_S <= '1'; end if;
+			elsif (data_out_S(35 downto 32)="0010") then
+				if (prevdata_V/="0010") and (prevdata_V/="0001") then derror_S <= '1'; end if;
+			elsif (data_out_S(35 downto 32)="0100") then
+				if (prevdata_V/="0010") then derror_S <= '1'; end if;
+			elsif (data_out_S(35 downto 32)="0101") then 
+				if (prevdata_V/="0010") then derror_S <= '1'; end if;
+			else
+				derror_S <= '1';
+			end if;
+			prevdata_V := data_out_S(35 downto 32);
+		end if;
+	end if;
+end process;
 
-
-
-testword0(33 downto 29) <= timeout_counter_S(TIMEOUTBITS-1 downto TIMEOUTBITS-5);
-testword0(35 downto 34) <= (others => '0');
-
-
-end Behavioral;
-
-
+end Behavioral;
diff --git a/FEE_ADC32board/FEE_modules/FEE_wavemux_readfifo.vhd b/FEE_ADC32board/FEE_modules/FEE_wavemux_readfifo.vhd
index 7066dff..ca8d397 100644
--- a/FEE_ADC32board/FEE_modules/FEE_wavemux_readfifo.vhd
+++ b/FEE_ADC32board/FEE_modules/FEE_wavemux_readfifo.vhd
@@ -6,6 +6,7 @@
 -- Description:   Read 36-bits data from fifo and write to next module
 -- Modifications:
 --    16-10-2014: inpipe signal
+--    16-10-2015: reads one data word when output writing is not allowed
 ----------------------------------------------------------------------------------
 
 library IEEE;
@@ -65,6 +66,7 @@ signal data_in_saved_S           : std_logic := '0';
 signal data_in_read_S            : std_logic := '0';
 signal data_in_read_after1clk_S  : std_logic := '0';
 signal data_out_trywrite_S       : std_logic := '0';
+signal data_out_allowed_S        : std_logic := '0';
 
 
 begin
@@ -72,7 +74,10 @@ begin
 data_out_inpipe <= '1' when (data_in_available='1') or (data_out_trywrite_S='1') or (data_in_saved_S='1') else '0';
 
 data_in_read <= data_in_read_S;
-data_in_read_S <= '1' when (data_out_allowed='1') and (data_in_available='1') and (data_in_saved_S='0') else '0';
+data_in_read_S <= '1' when 
+((data_out_allowed='1') or ((data_in_saved_S='0') and (data_out_allowed='0') and (data_out_allowed_S='0') and (data_in_read_after1clk_S='0')))
+ and (data_in_available='1') and (data_in_saved_S='0') else '0';
+
 
 data_out_write <= data_out_write_S;
 data_out_write_S <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
@@ -110,6 +115,7 @@ begin
 			end if;
 			data_in_read_after1clk_S <= data_in_read_S;
 		end if;
+		data_out_allowed_S <= data_out_allowed;
 	end if;
 end process;
 
diff --git a/FEE_ADC32board/FEE_modules/GrayCounter.vhd b/FEE_ADC32board/FEE_modules/GrayCounter.vhd
new file mode 100644
index 0000000..0d2f076
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/GrayCounter.vhd
@@ -0,0 +1,46 @@
+----------------------------------------
+-- Function    : Code Gray counter.
+-- Coder       : Alex Claros F.
+-- Date        : 15/May/2005.
+-- Translator  : Alexander H Pham (VHDL)
+----------------------------------------
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.std_logic_unsigned.all;
+    use ieee.std_logic_arith.all;
+    
+entity GrayCounter is
+    generic (
+        COUNTER_WIDTH : natural := 4
+    );
+    port (                                  --'Gray' code count output.
+        GrayCount_out :out std_logic_vector (COUNTER_WIDTH-1 downto 0);  
+        Enable_in     :in  std_logic;       -- Count enable.
+        Clear_in      :in  std_logic;       -- Count reset.
+        clk           :in  std_logic        -- Input clock
+    );
+end entity;
+
+architecture rtl of GrayCounter is
+    signal BinaryCount :std_logic_vector (COUNTER_WIDTH-1 downto 0);
+begin
+    process (clk) 
+	 variable b1 : std_logic_vector(COUNTER_WIDTH-2 downto 0);
+	 variable b2 : std_logic_vector(COUNTER_WIDTH-2 downto 0);
+	 begin
+        if (rising_edge(clk)) then
+            if (Clear_in = '1') then
+                --Gray count begins @ '1' with
+                BinaryCount   <= conv_std_logic_vector(1, COUNTER_WIDTH);  
+                GrayCount_out <= (others=>'0');
+            -- first 'Enable_in'.
+            elsif (Enable_in = '1') then
+                BinaryCount   <= BinaryCount + 1;
+					 b1 := BinaryCount(COUNTER_WIDTH-2 downto 0);
+					 b2 := BinaryCount(COUNTER_WIDTH-1 downto 1);
+                GrayCount_out <= BinaryCount(COUNTER_WIDTH-1) & (b1 xor b2);
+             end if;
+        end if;
+    end process;
+    
+end architecture;
diff --git a/FEE_ADC32board/FEE_modules/Panda_package.vhd b/FEE_ADC32board/FEE_modules/Panda_package.vhd
index 0de958a..6c93ba6 100644
--- a/FEE_ADC32board/FEE_modules/Panda_package.vhd
+++ b/FEE_ADC32board/FEE_modules/Panda_package.vhd
@@ -13,31 +13,36 @@ use IEEE.std_logic_UNSIGNED.ALL;
 
 package panda_package is
 
-	constant NROFADCS : natural := 32;
-	constant NROFFIBERS : natural := 4;
-	constant ADCINDEXSHIFT : natural := 1;
-	constant NROFMUXREGS : natural := 14;
-	constant ADCBITS : natural := 14;
-	constant ADCCLOCKFREQUENCY : natural := 80000000; -- 80000000; -- 62500000;
-	constant FEESLOWCONTROLADRESSES : natural := 2*NROFADCS/(ADCINDEXSHIFT+1)+4;
-	constant FEESLOWCONTROLBOARDADDRESS : natural := 2*NROFADCS/(ADCINDEXSHIFT+1);
-
+	constant DOPRECLUSTERING               : boolean := false;  
+	constant NROFFEEFPGAS                  : natural := 2;
+	constant NROFFEEADCS                   : natural := 32;
+	constant NROFFIBERS                    : natural := 4;
+	constant ADCINDEXSHIFT                 : natural := 1;
+	constant NROFMUXREGS                   : natural := 14;
+	constant ADCBITS                       : natural := 14;
+	constant NROFREGSPERCHANNEL            : natural := 4;
+	constant ADCCLOCKFREQUENCY             : natural := 80000000;
+	constant FEESLOWCONTROLADRESSES : natural := (NROFFEEFPGAS*NROFREGSPERCHANNEL*NROFFEEADCS)/(ADCINDEXSHIFT+1)+4*NROFFEEFPGAS; -- number of addressen for initialization all FEE adddresses
+	constant FEESLOWCONTROLBOARDADDRESS : natural := (NROFFEEFPGAS*NROFREGSPERCHANNEL*NROFFEEADCS)/(ADCINDEXSHIFT+1); -- number of addressen for initialization all FEE adddresses
+	
 -- statusbyte in data stream :
-    constant STATBYTE_DCPULSESKIPPED     : std_logic_vector(7 downto 0) := "00000100";
-    constant STATBYTE_DCWAVESKIPPED      : std_logic_vector(7 downto 0) := "00000100";
-    constant STATBYTE_DCCOMBINEDHITS     : std_logic_vector(7 downto 0) := "00000001";
-    constant STATBYTE_DCCOMBINEDDISCARDED : std_logic_vector(7 downto 0) := "00000010";
-    constant STATBYTE_DCSUPERBURSTMISSED : std_logic_vector(7 downto 0) := "00001100";
-
-    constant STATBYTE_FEEPULSESKIPPED    : std_logic_vector(7 downto 0) := "01000000";
-    constant STATBYTE_FEECFNOZEROCROSS   : std_logic_vector(7 downto 0) := "00100000";
-    constant STATBYTE_FEECFERROR         : std_logic_vector(7 downto 0) := "00010000";
+    constant STATBYTE_DCPULSESKIPPED       : std_logic_vector(7 downto 0) := "00000100";
+    constant STATBYTE_DCWAVESKIPPED        : std_logic_vector(7 downto 0) := "00000100";
+    constant STATBYTE_DCCOMBINEDHITS       : std_logic_vector(7 downto 0) := "00000001";
+    constant STATBYTE_DCCOMBINEDDISCARDED  : std_logic_vector(7 downto 0) := "00000010";
+    constant STATBYTE_DCSUPERBURSTMISSED   : std_logic_vector(7 downto 0) := "00001100";
+
+    constant STATBYTE_PILEUPHITBITNR       : integer := 7;
+    constant STATBYTE_PILEUPHIT            : std_logic_vector(7 downto 0) := (STATBYTE_PILEUPHITBITNR => '1', others => '0');
+    constant STATBYTE_FEEPULSESKIPPED      : std_logic_vector(7 downto 0) := "01000000";
+    constant STATBYTE_FEECFNOZEROCROSS     : std_logic_vector(7 downto 0) := "00100000";
+    constant STATBYTE_FEECFERROR           : std_logic_vector(7 downto 0) := "00010000";
 
 -- fiber constants
 constant KCHAR280        : std_logic_vector(7 downto 0) := "00011100"; -- 1C
 constant KCHAR281        : std_logic_vector(7 downto 0) := "00111100"; -- 3C
 constant KCHAR285        : std_logic_vector(7 downto 0) := "10111100"; -- BC
--- constant KCHAR277        : std_logic_vector(7 downto 0) := "11111011"; -- FB
+
 constant KCHAR286        : std_logic_vector(7 downto 0) := x"DC";
 
 constant KCHARIDLE       : std_logic_vector(15 downto 0) := KCHAR281 & KCHAR285;  -- 3CBC peter: bytes different for word sync
@@ -56,6 +61,7 @@ constant KCHARSODA       : std_logic_vector(7 downto 0) := KCHAR286;  -- DC
 --         bit3 : received character not in table: fiber error
 --         bit4 : pulse data skipped due to full multiplexer fifo
 --         bit5 : receiver locked
+--         bit6 : data being sent to the output fiber (same for each fiber: there is only one output)
 --         bit15..8 : number of pulse data packets skipped due to full buffers
 --         bit31..16 : number of successful hamming code corrections
 	constant ADDRESS_MUX_MAXCFLUTS : std_logic_vector(23 downto 0) := x"800001";
@@ -77,8 +83,13 @@ constant KCHARSODA       : std_logic_vector(7 downto 0) := KCHAR286;  -- DC
 --         bit1 : reset timestamp counters
 --         bit2 : Enable data taking 
 --         bit3 : Disable data taking
---         bit4 : Enable Aurora interface to Computer Node
-	constant ADDRESS_MUX_HISTOGRAM : std_logic_vector(23 downto 0) := x"800004";
+--         bit4 : Enable data to Compute Node
+--         bit5 : Enable waveforms to Compute Node
+--         bit6 : Select multiplexer status from waveform instead of pulses
+--         bit7 : Enable external SODA
+--         bit8 : Reset fibers to FEE
+--         bit9 : Disable packet limit (minimum time for one packet to prevent UDP buffer overrun)
+	constant ADDRESS_MUX_HISTOGRAM : std_logic_vector(23 downto 0) := x"800004"; --(disabled)
 --       settings for the histogram : 
 --         bit0 : clear the histogram
 --         bit1 : start reading of the histogram
@@ -114,7 +125,7 @@ constant KCHARSODA       : std_logic_vector(7 downto 0) := KCHAR286;  -- DC
 --         bit 17 : select 1 low/high combination instead of 1 adc channel
 	constant ADDRESS_MUX_SYSMON : std_logic_vector(23 downto 0) := x"80000c";
 --       write to FPGA system monitor
---         bit 31 : slect read/write, write='0', read='1'
+--         bit 31 : select read/write, write='0', read='1'
 --         bit 30 : reset/reconfigure FPGA system monitor
 --         bit 22..16 : 7-bits address of FPGA system monitor
 --         bit 15..0 : 16-bits data for FPGA system monitor
@@ -123,10 +134,7 @@ constant KCHARSODA       : std_logic_vector(7 downto 0) := KCHAR286;  -- DC
 --         bit 15..0 : data from FPGA system monitor
 	constant ADDRESS_MUX_CROSSSWITCH : std_logic_vector(23 downto 0) := x"80000d";
 --       write to cross switch configuration
---         bit 7..0 : selected multiplexer input
---         bit 15..8 : ADC-channel to switch to selected multiplexer input (fibernr*NROFADCS+adcnumber or fibernr*NROFADCS/2+adcnumber/2 if high/low gain ADCs are used)
---         bit 16 : select if selected multiplexer input will be combined with neighbour (only for even inputs)
---         bit 31 : write to configuration register (extra check)
+--         bit 31..0 : corresponding ADC input will be combined with the same ADC input channel on the neighbouring ADC board
 	constant ADDRESS_MUX_ENERGYCORRECTION : std_logic_vector(23 downto 0) := x"80000e";
 --       energy correction Look Up Table
 --         bit 15..0 : gain correction (multiplying factor shifted by number of scalingsbits)
@@ -136,16 +144,39 @@ constant KCHARSODA       : std_logic_vector(7 downto 0) := KCHAR286;  -- DC
 -- addresses slowcontrol commands for Multiplexer
 	constant ADDRESS_BOARDNUMBER : std_logic_vector(23 downto 0) := x"002000";
 --         bit11..0 = sets the unique boardnumber
---         bit31 = initialize all FEE registers that have been set
+--         bit31 = initialize all FEE registers that have been set from the shadow registers in the Data Concentrator
 
 -- addresses slowcontrol commands for Front End Electronics board
+--   address 0..FEESLOWCONTROLBOARDADDRESS-1 are the addresses for each ADC channel.
+--   even numbered addresses contains register_A, odd numbered registers contains register_B
+--       board_register A: write
+--         register_A(7..0) = threshold High
+--         register_A(15..8) = threshold Low
+--         register_A(16) = disable High
+--         register_A(17) = disable Low
+--         register_A(23..18) = I/Max discard
+--         register_A(29..24) = I/Max pileup
+--         register_A(30) = enable raw data in waveform instead of baseline corrected data
+--       board_register B: write
+--         register_B(7..0) = minimum pulselength
+--         register_B(15..8) = pileup length
+--         register_B(23..16) = maximum wavelength
+--         register_B(24) = fullsize High
+--         register_B(25) = fullsize Low
+--         register_B(29..26) = CF delay
 	constant ADDRESS_FEE_CONTROL : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS,8);
 --         bit0: reset all
+--         bit1: invert ADC signals
 --         bit2: clear errors
 --         bit3: enable waveforms
---         bit 17..16 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read
---         bit 18 = reset/initializes FPGA System monitor
-	constant ADDRESS_FEE_STATUS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+1,8);
+--         bit20..16 = select channel for frequency measurement
+--         bit 21 = reset/initializes FPGA System monitor
+--         bit 23..22 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare, change activates read
+	constant ADDRESS_FEE_STATUS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+1*NROFFEEFPGAS,8);
+--       write:
+--         bit4..0 : MWD width, depends on MWD_WIDTHBITS
+--         bit26..16 : lowest part of MWD tau factor, depends on MWD_TAUBITS
+--       read:
 --         bit1 : Data Taken enabled (enable and disabled is done with SODA packets)
 --         bit 5..4 = ADC index from FPGA System monitor: 0=temp, 1=VCCint, 2=VCCaux, 3=spare
 --         bit 15..6 = ADC value from FPGA System monitor
@@ -154,34 +185,35 @@ constant KCHARSODA       : std_logic_vector(7 downto 0) := KCHAR286;  -- DC
 --            bit17 : error : receive data error (slowcontrol)
 --            bit18 : error : slowcontrol buffer overrun
 --            bit19 : error : not used
---            bit20 : error : transmit data error, multipleser error
+--            bit20 : error : transmit data error, multiplexer error
 --            bit21 : error : receive data buffer overrun
 --            bit22 : error : adc data buffer overrun
 --            bit23 : error : receive fiber not locked
-	constant ADDRESS_FEE_SLOWCONTROLERROR : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+2,8);
+	constant ADDRESS_FEE_SLOWCONTROLERROR : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+2*NROFFEEFPGAS,8);
 --            data not important; this slowcontrol command indicates buffer full
-	constant ADDRESS_FEE_MEASURE_FREQUENCY : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+3,8);
+	constant ADDRESS_FEE_MEASURE_FREQUENCY : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+3*NROFFEEFPGAS,8);
 --            bit31..0 : number of hits in one second
-	constant ADDRESS_FEE_REQUESTALLREGISTERS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+4,8);
+	constant ADDRESS_FEE_REQUESTALLREGISTERS : std_logic_vector(7 downto 0) := conv_std_logic_vector(FEESLOWCONTROLBOARDADDRESS+4*NROFFEEFPGAS,8);
 
 	type array_muxregister_type is array(0 to NROFMUXREGS-1) of std_logic_vector(31 downto 0);
 	
-	type array_adc_type is array(0 to NROFADCS-1) of std_logic_vector(ADCBITS-1 downto 0);
-	type array_adc64bits_type is array(0 to NROFADCS-1) of std_logic_vector(63 downto 0);
-	type array_adc48bits_type is array(0 to NROFADCS-1) of std_logic_vector(47 downto 0);
-	type array_adc36bits_type is array(0 to NROFADCS-1) of std_logic_vector(35 downto 0);
-	type array_adc32bits_type is array(0 to NROFADCS-1) of std_logic_vector(31 downto 0);
-	type array_adc24bits_type is array(0 to NROFADCS-1) of std_logic_vector(23 downto 0);
-	type array_adc16bits_type is array(0 to NROFADCS-1) of std_logic_vector(15 downto 0);
-	type array_adc9bits_type is array(0 to NROFADCS-1) of std_logic_vector(8 downto 0);
-	type array_adc8bits_type is array(0 to NROFADCS-1) of std_logic_vector(7 downto 0);
-	type array_adc4bits_type is array(0 to NROFADCS-1) of std_logic_vector(3 downto 0);
-
-	type array_halfadc36bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(35 downto 0);
-	type array_halfadc32bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(31 downto 0);
-	type array_halfadc16bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(15 downto 0);
-	type array_halfadc9bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(8 downto 0);
-	type array_halfadc8bits_type is array(0 to NROFADCS/2-1) of std_logic_vector(7 downto 0);
+	type array_adc_type is array(0 to NROFFEEADCS-1) of std_logic_vector(ADCBITS-1 downto 0);
+	type array_adc64bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(63 downto 0);
+	type array_adc48bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(47 downto 0);
+	type array_adc36bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(35 downto 0);
+	type array_adc32bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(31 downto 0);
+	type array_adc24bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(23 downto 0);
+	type array_adc16bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(15 downto 0);
+	type array_adc9bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(8 downto 0);
+	type array_adc8bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(7 downto 0);
+	type array_adc4bits_type is array(0 to NROFFEEADCS-1) of std_logic_vector(3 downto 0);
+
+	type array_halfadc36bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(35 downto 0);
+	type array_halfadc32bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(31 downto 0);
+	type array_halfadc31bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(30 downto 0);
+	type array_halfadc16bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(15 downto 0);
+	type array_halfadc9bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(8 downto 0);
+	type array_halfadc8bits_type is array(0 to NROFFEEADCS/2-1) of std_logic_vector(7 downto 0);
 	
 	type array_fiber64bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(63 downto 0);
 	type array_fiber48bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(47 downto 0);
@@ -196,14 +228,14 @@ constant KCHARSODA       : std_logic_vector(7 downto 0) := KCHAR286;  -- DC
 	type array_fiber8bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(7 downto 0);
 	type array_fiber4bits_type is array(0 to NROFFIBERS-1) of std_logic_vector(3 downto 0);
 
-	type array_DCadc36bits_type is array(0 to NROFADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(35 downto 0);
-	type array_fiberXadc36bits_type is array(0 to NROFFIBERS*(NROFADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(35 downto 0);
-	type array_fiberXadc16bits_type is array(0 to NROFFIBERS*(NROFADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(15 downto 0);
+	type array_DCadc36bits_type is array(0 to NROFFEEADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(35 downto 0);
+	type array_fiberXadc36bits_type is array(0 to NROFFIBERS*(NROFFEEADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(35 downto 0);
+	type array_fiberXadc16bits_type is array(0 to NROFFIBERS*(NROFFEEADCS/(ADCINDEXSHIFT+1))-1) of std_logic_vector(15 downto 0);
 	type twologarray_type is array(0 to 128) of natural;
 	constant twologarray : twologarray_type :=
 (0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7);
-	type array_fiberXadcCrossSwitch_type is array(0 to NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(twologarray(NROFFIBERS*NROFADCS/(ADCINDEXSHIFT+1))-1 downto 0);
+	type array_fiberXadcCrossSwitch_type is array(0 to NROFFIBERS*NROFFEEADCS/(ADCINDEXSHIFT+1)-1) of std_logic_vector(twologarray(NROFFIBERS*NROFFEEADCS/(ADCINDEXSHIFT+1))-1 downto 0);
 
 ----------------------------------------------------------------------------------
 -- add_hamming_code_26_32
diff --git a/FEE_ADC32board/FEE_modules/asyncfifo.vhd b/FEE_ADC32board/FEE_modules/asyncfifo.vhd
new file mode 100644
index 0000000..9e5f66b
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/asyncfifo.vhd
@@ -0,0 +1,174 @@
+------------------------------------------------------------
+-- Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
+-- Coder    : Alex Claros F.
+-- Date     : 15/May/2005.
+-- Notes    : This implementation is based on the article 
+--            'Asynchronous FIFO in Virtex-II FPGAs'
+--            writen by Peter Alfke. This TechXclusive 
+--            article can be downloaded from the
+--            Xilinx website. It has some minor modifications.
+-- Coder     : Deepak Kumar Tala (Verilog)
+-- Translator: Alexander H Pham (VHDL)
+------------------------------------------------------------
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.std_logic_unsigned.all;
+    
+entity asyncfifo is
+    generic (
+        DATA_WIDTH : natural := 8;
+        ADDR_WIDTH : natural := 4
+    );
+    port (
+		reset : in std_logic;
+		read_clock : in std_logic;
+		read_request  : in std_logic;
+		data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+		write_clock : in std_logic;
+		write_request : in std_logic;
+		data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
+		empty : out std_logic;
+		full : out std_logic;
+		valid : out std_logic
+    );
+end entity;
+
+
+architecture rtl of asyncfifo is
+    ----/Internal connections & variables------
+    constant FIFO_DEPTH : integer := 2**ADDR_WIDTH;
+
+    type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
+    signal Mem : RAM (0 to FIFO_DEPTH-1);
+    
+    signal pNextWordToWrite     :std_logic_vector (ADDR_WIDTH-1 downto 0);
+    signal pNextWordToRead      :std_logic_vector (ADDR_WIDTH-1 downto 0);
+    signal EqualAddresses       :std_logic;
+    signal NextWriteAddressEn   :std_logic;
+    signal NextReadAddressEn    :std_logic;
+    signal Set_Status           :std_logic;
+    signal Rst_Status           :std_logic;
+    signal Status               :std_logic;
+    signal PresetFull           :std_logic;
+    signal PresetEmpty          :std_logic;
+    signal empty_i,full_i       :std_logic;
+    
+    component GrayCounter is
+    generic (
+        COUNTER_WIDTH : natural := ADDR_WIDTH
+    );
+    port (
+        GrayCount_out :out std_logic_vector (COUNTER_WIDTH-1 downto 0);
+        Enable_in     :in  std_logic;  --Count enable.
+        Clear_in   	 :in  std_logic;  --Count reset.
+        clk           :in  std_logic
+    );
+    end component;
+begin
+
+    --------------Code--------------/
+    --Data ports logic:
+    --(Uses a dual-port RAM).
+    --'data_out' logic:
+    process (read_clock) begin
+        if (rising_edge(read_clock)) then
+            if (read_request = '1' and empty_i = '0') then
+                data_out <= Mem(conv_integer(pNextWordToRead));
+            end if;
+        end if;
+    end process;
+            
+    --'data_in' logic:
+    process (write_clock) begin
+        if (rising_edge(write_clock)) then
+            if (write_request = '1' and full_i = '0') then
+                Mem(conv_integer(pNextWordToWrite)) <= data_in;
+            end if;
+        end if;
+    end process;
+
+    --Fifo addresses support logic: 
+    --'Next Addresses' enable logic:
+    NextWriteAddressEn <= write_request and (not full_i);
+    NextReadAddressEn  <= read_request  and (not empty_i);
+           
+    --Addreses (Gray counters) logic:
+    GrayCounter_pWr : GrayCounter
+    port map (
+        GrayCount_out => pNextWordToWrite,
+        Enable_in     => NextWriteAddressEn,
+        Clear_in      => reset,
+        clk           => write_clock
+    );
+       
+    GrayCounter_pRd : GrayCounter
+    port map (
+        GrayCount_out => pNextWordToRead,
+        Enable_in     => NextReadAddressEn,
+        Clear_in      => reset,
+        clk           => read_clock
+    );
+
+    --'EqualAddresses' logic:
+    EqualAddresses <= '1' when (pNextWordToWrite = pNextWordToRead) else '0';
+
+    --'Quadrant selectors' logic:
+    process (pNextWordToWrite, pNextWordToRead)
+        variable set_status_bit0 :std_logic;
+        variable set_status_bit1 :std_logic;
+        variable rst_status_bit0 :std_logic;
+        variable rst_status_bit1 :std_logic;
+    begin
+        set_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xnor pNextWordToRead(ADDR_WIDTH-1);
+        set_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xor  pNextWordToRead(ADDR_WIDTH-2);
+        Set_Status <= set_status_bit0 and set_status_bit1;
+        
+        rst_status_bit0 := pNextWordToWrite(ADDR_WIDTH-2) xor  pNextWordToRead(ADDR_WIDTH-1);
+        rst_status_bit1 := pNextWordToWrite(ADDR_WIDTH-1) xnor pNextWordToRead(ADDR_WIDTH-2);
+        Rst_Status      <= rst_status_bit0 and rst_status_bit1;
+    end process;
+    
+    --'Status' latch logic:
+    process (Set_Status, Rst_Status, reset) begin--D Latch w/ Asynchronous Clear & Preset.
+        if (Rst_Status = '1' or reset = '1') then
+            Status <= '0';  --Going 'Empty'.
+        elsif (Set_Status = '1') then
+            Status <= '1';  --Going 'Full'.
+        end if;
+    end process;
+    
+    --'full' logic for the writing port:
+    PresetFull <= Status and EqualAddresses;  --'Full' Fifo.
+    
+    process (write_clock, PresetFull) begin --D Flip-Flop w/ Asynchronous Preset.
+        if (PresetFull = '1') then
+            full_i <= '1';
+        elsif (rising_edge(write_clock)) then
+            full_i <= '0';
+        end if;
+    end process;
+    full <= full_i;
+    
+    --'empty' logic for the reading port:
+    PresetEmpty <= not Status and EqualAddresses;  --'Empty' Fifo.
+    
+    process (read_clock, PresetEmpty) begin --D Flip-Flop w/ Asynchronous Preset.
+        if (PresetEmpty = '1') then
+            empty_i <= '1';
+        elsif (rising_edge(read_clock)) then
+            empty_i <= '0';
+        end if;
+    end process;
+    
+    empty <= empty_i;
+	 
+    process (read_clock) begin 
+		if (rising_edge(read_clock)) then
+			if (empty_i='0') and (NextReadAddressEn='1') then 
+				valid <= '1';
+			else
+				valid <= '0';
+			end if;
+		end if;
+    end process;
+end architecture;
\ No newline at end of file
diff --git a/FEE_ADC32board/FEE_modules/iirfilter_1order_selectBW.vhd b/FEE_ADC32board/FEE_modules/iirfilter_1order_selectBW.vhd
index 1ebc47c..ab64e40 100644
--- a/FEE_ADC32board/FEE_modules/iirfilter_1order_selectBW.vhd
+++ b/FEE_ADC32board/FEE_modules/iirfilter_1order_selectBW.vhd
@@ -48,9 +48,9 @@ entity iirfilter_1order_selectBW is
 end iirfilter_1order_selectBW;
 
 architecture Behavioral of iirfilter_1order_selectBW is
-signal data_x_BW              : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
-signal data_out_unscaled_delayed : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
-signal data_out_multiplied    : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
+signal data_x_BW              : std_logic_vector((ADCBITS+BWBITS-1)downto 0); --//  := (others => '0');
+signal data_out_unscaled_delayed : std_logic_vector((ADCBITS+BWBITS-1) downto 0); --// := (others => '0');
+signal data_out_multiplied    : std_logic_vector((ADCBITS+BWBITS-1) downto 0); --// := (others => '0');
 signal BWidx_i                : integer range 0 to 7 := 0;
 
 begin
@@ -59,15 +59,15 @@ process(clock)
 variable data_out_unscaled : std_logic_vector((ADCBITS+BWBITS-1) downto 0) := (others => '0');
 begin
 	if rising_edge(clock) then
-		if reset='1' then
-			data_out_unscaled_delayed((ADCBITS+BWBITS-1) downto BWBITS) <= data_in;
-			data_out_unscaled_delayed((BWBITS-1) downto 0) <= (others => '0');
-			data_out_multiplied(BWidx_i-1 downto 0) <= (others => '0');
-			data_out_multiplied(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
-			data_x_BW <= (others => '0');
-			data_x_BW(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
-			data_out <= data_in;
-		else
+		-- if reset='1' then
+			-- data_out_unscaled_delayed((ADCBITS+BWBITS-1) downto BWBITS) <= data_in;
+			-- data_out_unscaled_delayed((BWBITS-1) downto 0) <= (others => '0');
+			-- data_out_multiplied(BWidx_i-1 downto 0) <= (others => '0');
+			-- data_out_multiplied(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
+			-- data_x_BW <= (others => '0');
+			-- data_x_BW(ADCBITS+BWidx_i-1 downto BWidx_i) <= data_in;
+			-- data_out <= data_in;
+		-- else
 			if inhibit='0' then
 				data_out_unscaled := data_x_BW + data_out_unscaled_delayed-data_out_multiplied;
 				
@@ -80,11 +80,11 @@ begin
 				data_out_unscaled_delayed <= data_out_unscaled;
 				data_out <= data_out_unscaled((ADCBITS+BWBITS-1) downto BWBITS);
 			end if;
-		end if;
+--		end if;
 	end if;
 end process;
 
-BWidx_i <= conv_integer(unsigned(BWidx));
+BWidx_i <= 0; --// conv_integer(unsigned(BWidx));
 
 end Behavioral;
 
diff --git a/FEE_ADC32board/FEE_modules/posedge_async_to_pulse.vhd b/FEE_ADC32board/FEE_modules/posedge_async_to_pulse.vhd
new file mode 100644
index 0000000..4a0fff1
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/posedge_async_to_pulse.vhd
@@ -0,0 +1,64 @@
+-----------------------------------------------------------------------------------
+-- posedge_async_to_pulse
+--		Makes pulse with duration 1 clock-cycle from async positive edge
+--	
+-- inputs
+--		clock_in : clock input for input signal
+--		clock_out : clock input to synchronize to
+--		en_clk : clock enable
+--		signal_in : rising edge of this signal will result in pulse
+--
+--	output
+--		pulse : pulse output : one clock cycle '1'
+--
+-----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity posedge_async_to_pulse is
+	port (
+		clock_out         : in  std_logic;
+		signal_in         : in  std_logic;
+		pulse             : out std_logic
+	);
+end posedge_async_to_pulse;
+
+architecture behavioral of posedge_async_to_pulse is
+
+  signal qff1	: std_logic := '0'; 
+  signal qff2	: std_logic := '0'; 
+  signal qff3	: std_logic := '0'; 
+begin  
+
+process (signal_in,qff3)
+begin
+	if qff3='1' then
+		qff1 <= '0';
+	elsif rising_edge(signal_in) then
+		qff1 <= '1';
+	end if;
+end process;
+
+
+process (clock_out)
+begin
+	if rising_edge(clock_out) then
+		if qff3='1' then
+			qff2 <= '0';
+		else
+			qff2 <= qff1;
+		end if;
+		if (qff2='1') and (qff3='0') then
+			pulse <= '1';
+		else
+			pulse <= '0';
+		end if;
+		qff3 <= qff2;
+	end if;
+end process; 
+
+end behavioral;
+
diff --git a/FEE_ADC32board/FEE_modules/shift_register.vhd b/FEE_ADC32board/FEE_modules/shift_register.vhd
index 8b99229..dd6f6c4 100644
--- a/FEE_ADC32board/FEE_modules/shift_register.vhd
+++ b/FEE_ADC32board/FEE_modules/shift_register.vhd
@@ -1,5 +1,5 @@
 ----------------------------------------------------------------------------------
--- Company:       KVI/RUG/Groningen University
+-- Company:       KVI-cart/RUG/Groningen University
 -- Engineer:      Peter Schakel
 -- Create Date:   22-02-2009
 -- Module Name:   shift_register 
@@ -53,13 +53,15 @@ end shift_register;
 architecture behavior of shift_register is
 
 type arrtype is array((2**depthbits-1) downto 0) of std_logic_vector((width-1) downto 0);
-signal mem : arrtype; -- := (others => (others => '0'));
+signal mem : arrtype := (others => (others => '0'));
 signal outptr : std_logic_vector((depthbits-1) downto 0) := (others => '0');
 signal mem_out : std_logic_vector((width-1) downto 0) := (others => '0');
 signal lastreset : std_logic := '0';
 
 attribute syn_ramstyle : string; 
 attribute syn_ramstyle of mem : signal is "block_ram"; 
+attribute ram_style: string;
+attribute ram_style of mem : signal is "block";
 
 begin
 
diff --git a/FEE_ADC32board/FEE_modules/shift_register_small.vhd b/FEE_ADC32board/FEE_modules/shift_register_small.vhd
new file mode 100644
index 0000000..d249877
--- /dev/null
+++ b/FEE_ADC32board/FEE_modules/shift_register_small.vhd
@@ -0,0 +1,226 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI-cart/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   22-02-2009
+-- Module Name:   shift_register_small 
+-- Description:   Shifts data for an adjustable number of clock cycles
+----------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- shift_register_small
+--		Shifts data for an adjustable number of clock cycles
+--
+-- generics
+--		width : number of bits for the data to shift
+--		DEPTHBITS : number of bits for the number of clock cycles to shift
+--		
+-- inputs
+--		clock : ADC sampling clock 
+--		reset : synchrounous reset
+--		hold : hold all values
+--		data_in : data to shift
+--		depth : number of clock cycles to shift for
+--
+-- outputs
+--		data_out : shifted data
+--
+-- components
+--		blockmem : simple dual ported memory with 1 clock
+--		blockmem1x18_xilinx,blockmem2x18_xilinx,blockmem3x18_xilinx,blockmem4x18_xilinxblockmem5x18_xilinx : Xilinx dual ported memory
+--
+------------------------------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity shift_register_small is
+	generic (
+		WIDTH                   : natural := 16;
+		DEPTHBITS               : natural := 9
+		);
+    port (
+		clock                   : in  std_logic; 
+		data_in                 : in std_logic_vector((width-1) downto 0); 
+		depth                   : in std_logic_vector((DEPTHBITS-1) downto 0);
+		data_out                : out  std_logic_vector((width-1) downto 0));
+end shift_register_small;
+
+architecture behavior of shift_register_small is
+
+component blockmem is
+	generic (
+		ADDRESS_BITS            : natural := DEPTHBITS;
+		DATA_BITS               : natural := width
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+COMPONENT blockmem1x18_xilinx
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+  );
+END COMPONENT;
+
+COMPONENT blockmem2x18_xilinx
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+  );
+END COMPONENT;
+
+COMPONENT blockmem3x18_xilinx
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+  );
+END COMPONENT;
+
+COMPONENT blockmem4x18_xilinx
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+  );
+END COMPONENT;
+
+COMPONENT blockmem5x18_xilinx
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+  );
+END COMPONENT;
+
+type arrtype is array((2**DEPTHBITS-1) downto 0) of std_logic_vector((width-1) downto 0);
+signal mem : arrtype := (others => (others => '0'));
+signal outptr_S : std_logic_vector((DEPTHBITS-1) downto 0) := (others => '0');
+signal memadr_S : std_logic_vector((DEPTHBITS-1) downto 0) := (others => '0');
+
+signal mem_in_S : std_logic_vector(17 downto 0) := (others => '0');
+signal mem_out_S : std_logic_vector(17 downto 0) := (others => '0');
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of mem : signal is "block_ram"; 
+attribute ram_style: string;
+attribute ram_style of mem : signal is "block";
+
+begin
+
+gen_others: if (DEPTHBITS>5) or (DEPTHBITS>18) generate
+	blockmem1: blockmem port map(
+			clock => clock,
+			write_enable => '1',
+			write_address => memadr_S,
+			data_in => data_in,
+			read_address => outptr_S,
+			data_out => data_out);
+end generate;
+		
+		
+mem_in_S(width-1 downto 0) <= data_in;
+data_out <= mem_out_S(width-1 downto 0);
+
+gen_1x18: if (DEPTHBITS=1) and (DEPTHBITS<=18) generate
+	blockmem1: blockmem1x18_xilinx port map(
+		clka => clock,
+		wea => (others => '1'),
+		addra => memadr_S,
+		dina => mem_in_S,
+		clkb => clock,
+		addrb => outptr_S,
+		doutb => mem_out_S);
+end generate;
+
+gen_2x18: if (DEPTHBITS=2) and (DEPTHBITS<=18) generate
+	blockmem1: blockmem2x18_xilinx port map(
+		clka => clock,
+		wea => (others => '1'),
+		addra => memadr_S,
+		dina => mem_in_S,
+		clkb => clock,
+		addrb => outptr_S,
+		doutb => mem_out_S);
+end generate;
+
+gen_3x18: if (DEPTHBITS=3) and (DEPTHBITS<=18) generate
+	blockmem1: blockmem3x18_xilinx port map(
+		clka => clock,
+		wea => (others => '1'),
+		addra => memadr_S,
+		dina => mem_in_S,
+		clkb => clock,
+		addrb => outptr_S,
+		doutb => mem_out_S);
+end generate;
+
+gen_4x18: if (DEPTHBITS=4) and (DEPTHBITS<=18) generate
+	blockmem1: blockmem4x18_xilinx port map(
+		clka => clock,
+		wea => (others => '1'),
+		addra => memadr_S,
+		dina => mem_in_S,
+		clkb => clock,
+		addrb => outptr_S,
+		doutb => mem_out_S);
+end generate;
+
+gen_5x18: if (DEPTHBITS=5) and (DEPTHBITS<=18) generate
+	blockmem1: blockmem5x18_xilinx port map(
+		clka => clock,
+		wea => (others => '1'),
+		addra => memadr_S,
+		dina => mem_in_S,
+		clkb => clock,
+		addrb => outptr_S,
+		doutb => mem_out_S);
+end generate;
+
+
+memadr_S <= outptr_S+depth;
+process (clock)
+begin
+	if rising_edge(clock) then
+		outptr_S <= outptr_S+1;
+	end if;
+end process;
+
+
+end behavior;
diff --git a/FEE_ADC32board/modules/ADCrefdesign/AdcData.vhd b/FEE_ADC32board/modules/ADCrefdesign/AdcData.vhd
deleted file mode 100644
index 79072ed..0000000
--- a/FEE_ADC32board/modules/ADCrefdesign/AdcData.vhd
+++ /dev/null
@@ -1,775 +0,0 @@
------------------------------------------------------------------------------------------------
--- © Copyright 2007 - 2011, Xilinx, Inc. All rights reserved.
--- This file contains confidential and proprietary information of Xilinx, Inc. and is
--- protected under U.S. and international copyright and other intellectual property laws.
------------------------------------------------------------------------------------------------
---
--- Disclaimer:
---		This disclaimer is not a license and does not grant any rights to the materials
---		distributed herewith. Except as otherwise provided in a valid license issued to you
---		by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
---		ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
---		WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
---		TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
---		PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
---		negligence, or under any other theory of liability) for any loss or damage of any
---		kind or nature related to, arising under or in connection with these materials,
---		including for any direct, or any indirect, special, incidental, or consequential
---		loss or damage (including loss of data, profits, goodwill, or any type of loss or
---		damage suffered as a result of any action brought by a third party) even if such
---		damage or loss was reasonably foreseeable or Xilinx had been advised of the
---		possibility of the same.
---
--- CRITICAL APPLICATIONS
---		Xilinx products are not designed or intended to be fail-safe, or for use in any
---		application requiring fail-safe performance, such as life-support or safety devices
---		or systems, Class III medical devices, nuclear facilities, applications related to
---		the deployment of airbags, or any other applications that could lead to death,
---		personal injury, or severe property or environmental damage (individually and
---		collectively, "Critical Applications"). Customer assumes the sole risk and
---		liability of any use of Xilinx products in Critical Applications, subject only to
---		applicable laws and regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 
---
---		Contact:    e-mail  hotline@xilinx.com        phone   + 1 800 255 7778
---   ____  ____
---  /   /\/   /
--- /___/  \  /   Vendor: 				Xilinx
--- \   \   \/    Version: 
---  \   \        Filename: 				AdcData.vhd
---  /   /        Date Last Modified:	15 Feb 2011
--- /___/   /\    Date Created:			18 Dec 2007
--- \   \  /  \
---  \___\/\___\
--- 
--- Device: 		Virtex-6
--- Author: 		Marc Defossez
--- Entity Name: AdcData
--- Purpose: 	2-channel ADC data receiver interface.
---				The output of this module is alwasy fprmatted in 32-bit.
---				When the interface is for a 12-bit ADC then the output is formatted as:
---				32 ---------- 16 , 15 ----------- 0
---				 0000 & (12-bit) ,  0000 & (12-bit)
---				When the interface is for 14-bit or 16-bit the the ouput is formatted as:
---				32 ---------- 16 , 15 ----------- 0
---				 (   16-bit   ) ,  (   16-bit    )
--- 				In 1-wire mode the 32-bit output shows two channels
---				In 2-wire mode the 32-bit output shows two words of the same channel.
---
--- Tools: 		ISE_11.2.xx
--- Limitations: none
---
--- Revision History:
---	Rev 21 Jun 09
---		Adaption to Virtex-6
---	Rev 20 Oct 09
---		Removal of the input buffers.
---		FPGA is placed in a different hierarchical level for easyness of portability.
---	Rev 28 Oct 09
---		Removal of two mode options.
---		C_AdcBytOrBitMode and C_AdcMsbOrLsbFst are now coded as default BYTE MODE and MSB FIRST
---		This can still be changed by making the generics again available at higher HDL levels.
---  Rev 09 Dec 2010
---      Made sure the output of the interface is always FFs with enable.
---      Therefore instantiated the FFs in staid of using plain VHDL descriptions.
---  Rev 15 Feb 2011
---      Review of implementation of the AdcData hierarchical level.
---
------------------------------------------------------------------------------------------------
--- Naming Conventions:
---   active low signals:                    "*_n"
---   clock signals:                         "clk", "clk_div#", "clk_#x"
---   reset signals:                         "rst", "rst_n"
---   generics:                              "C_*"
---   user defined types:                    "*_TYPE"
---   state machine next state:              "*_ns"
---   state machine current state:           "*_cs"
---   combinatorial signals:                 "*_com"
---   pipelined or register delay signals:   "*_d#"
---   counter signals:                       "*cnt*"
---   clock enable signals:                  "*_ce"
---   internal version of output port:       "*_i"
---   device pins:                           "*_pin"
---   ports:                                 "- Names begin with Uppercase"
---   processes:                             "*_PROCESS"
---   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------------------------
---
-library IEEE;
-	use IEEE.std_logic_1164.all;
-	use IEEE.std_logic_UNSIGNED.all;
-library UNISIM;
-	use UNISIM.VCOMPONENTS.all;
------------------------------------------------------------------------------------------------
--- Entity pin description
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-entity AdcData is
-	generic (
-		C_AdcBits			: integer := 16;	-- Can be 12, 14 or 16
-		C_AdcBytOrBitMode	: integer := 0;     -- 1 = BIT mode, 0 = BYTE mode,
-		C_AdcMsbOrLsbFst	: integer := 0;     -- 0 = MSB first, 1 = LSB first
-		C_AdcWireInt		: integer := 1		-- 1 = 1-wire, 2 = 2-wire.
-	);
-    port (
-        DatD0_n			: in std_logic;
-		DatD0_p			: in std_logic;
-		DatD1_n			: in std_logic;
-		DatD1_p			: in std_logic;
-		DatClk			: in std_logic;
-		DatClkDiv		: in std_logic;
-		DatRst			: in std_logic;
-		DatEna			: in std_logic;
-		DatDone			: in std_logic;
-		DatBitSlip_p	: in std_logic;
-        DatBitSlip_n	: in std_logic;
-        DatSwapMux		: in std_logic;
-        DatMsbRegEna	: in std_logic;
-        DatLsbRegEna	: in std_logic;
-        DatReSync		: in std_logic;
-		DatOut			: out std_logic_vector(31 downto 0)
-    );
-end AdcData;
------------------------------------------------------------------------------------------------
--- Arcitecture section
------------------------------------------------------------------------------------------------
-architecture AdcData_struct of AdcData  is
------------------------------------------------------------------------------------------------
--- Component Instantiation
------------------------------------------------------------------------------------------------
--- Components are instantiated through library naming.
------------------------------------------------------------------------------------------------
--- Constants, Signals and Attributes Declarations
------------------------------------------------------------------------------------------------
--- Functions
--- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.
--- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.
--- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.
-function DatBits (Bits : integer) return integer is
-variable Temp : integer;
-begin
-	if (Bits = 12) then
-		Temp := 12;
-	elsif (Bits = 14) then
-		Temp := 16;
-	elsif (Bits = 16) then
-		Temp := 16;
-	end if;
-return Temp;
-end function DatBits;
--- Constants
-constant IntIsrdsDataWidth : integer := DatBits(C_AdcBits)/4;
-constant Low			: std_logic := '0';
-constant High			: std_logic := '1';
--- Signals
-signal IntDatClk		: std_logic;
-signal IntDatClk_n		: std_logic;
---
--- ADC resolution = 12-bit: IntDatSrds0Out(5 downto 0) and IntDatSrds1Out(5 downto 0)
--- ADC resolution = 14-bit or 16-bit: IntDatSrds0Out(7 downto 0) and IntDatSrds1Out(7 downto 0)
-signal IntDatSrds0Out	: std_logic_vector(7 downto 0);
-signal IntDatSrds1Out	: std_logic_vector(7 downto 0);
-signal IntDatSrds0		: std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDatSrds1		: std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat0			: std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat1			: std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat0Mux       : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat1Mux       : std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat0Swp		: std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDat1Swp		: std_logic_vector((DatBits(C_AdcBits)/2)-1 downto 0);
-signal IntDatSwpBus     : std_logic_vector(31 downto 0);
-signal IntDatDone		: std_logic;
-signal IntDatEna 		: std_logic;
--- Attributes
------------------------------------------------------------------------------------------------
-begin
---
--- DatRst en DatEna are synchronised to DatClkDiv on a higher hierarchical level.
--- the higher level is "AdcToplevel".
-AdcData_Done_PROCESS : process (DatClkDiv, DatRst)
-begin
-	if (DatRst = High) then
-		IntDatDone <= Low;
-	elsif (DatClkDiv'event and DatClkDiv = '1') then
-		IntDatDone <= DatDone;
-	end if;
-end process;
--- "IntDatDone" enables the ISERDES.
--- "IntDatEna" is the enable for the logic behind the ISERDES.
---
-IntDatEna <= High when (IntDatDone = High and DatEna = High) else Low;
------------------------------------------------------------------------------------------------
-IntDatClk <= DatClk;			-- CLOCK FOR P-side ISERDES
-IntDatClk_n <= not DatClk;		-- CLOCK FOR N_side ISERDES
------------------------------------------------------------------------------------------------
--- ISERDES for channel ZERO
------------------------------------------------------------------------------------------------
-AdcData_I_Isrds_D0_p : ISERDESE1
-	generic map (
-		SERDES_MODE			=> "MASTER",			-- 
-		INTERFACE_TYPE		=> "NETWORKING",		-- 
-		IOBDELAY			=> "NONE",				-- 
-		DATA_RATE 			=> "SDR", 				-- 
-		DATA_WIDTH 			=> IntIsrdsDataWidth,	-- <-- Number of bits
-		DYN_CLKDIV_INV_EN	=> FALSE, 				-- 
-		DYN_CLK_INV_EN		=> FALSE, 				-- 
-		NUM_CE				=> 1, 					-- 
-		OFB_USED			=> FALSE 				-- 
-	)
-	port map (
-		D				=> DatD0_p,		-- in
-		DDLY			=> Low, 		-- in
-		DYNCLKDIVSEL	=> Low, 		-- in
-		DYNCLKSEL		=> Low, 		-- in
-		OFB				=> Low, 		-- in
-		BITSLIP			=> DatBitSlip_p,-- in
-		CE1				=> IntDatDone,	-- in
-		CE2				=> Low,			-- in
-		RST				=> DatRst,	    -- in
-		CLK				=> IntDatClk, 	-- in
-		CLKB			=> Low, 		-- in
-		CLKDIV			=> DatClkDiv, 	-- in
-		OCLK			=> Low, 		-- in
-		SHIFTOUT1		=> open, 		-- out
-		SHIFTOUT2		=> open, 		-- out
-		O				=> open, 		-- out
-		Q1				=> IntDatSrds0Out(6), -- out	(0)
-		Q2				=> IntDatSrds0Out(4), -- out	(2)
-		Q3				=> IntDatSrds0Out(2), -- out	(4)
-		Q4				=> IntDatSrds0Out(0), -- out	(6)
-		Q5				=> open, 		-- out
-		Q6				=> open, 		-- out
-		SHIFTIN1		=> Low, 		-- in
-		SHIFTIN2		=> Low 			-- in
-	);
-AdcData_I_Isrds_D0_n : ISERDESE1
-	generic map (
-		SERDES_MODE			=> "MASTER",			-- 
-		INTERFACE_TYPE		=> "NETWORKING",		-- 
-		IOBDELAY			=> "NONE",				-- 
-		DATA_RATE 			=> "SDR", 				-- 
-		DATA_WIDTH 			=> IntIsrdsDataWidth,	-- <-- Number of bits
-		DYN_CLKDIV_INV_EN	=> FALSE, 				-- 
-		DYN_CLK_INV_EN		=> FALSE, 				-- 
-		NUM_CE				=> 1, 					-- 
-		OFB_USED			=> FALSE 				-- 
-	)
-	port map (
-		D				=> DatD0_n,		-- in
-		DDLY			=> Low, 		-- in
-		DYNCLKDIVSEL	=> Low, 		-- in
-		DYNCLKSEL		=> Low, 		-- in
-		OFB				=> Low, 		-- in
-		BITSLIP			=> DatBitSlip_n,-- in
-		CE1				=> IntDatDone,	-- in
-		CE2				=> Low,			-- in
-		RST				=> DatRst,	    -- in
-		CLK				=> IntDatClk_n,	-- in
-		CLKB			=> Low, 		-- in
-		CLKDIV			=> DatClkDiv, 	-- in
-		OCLK			=> Low, 		-- in
-		SHIFTOUT1		=> open, 		-- out
-		SHIFTOUT2		=> open, 		-- out
-		O				=> open, 		-- out
-		Q1				=> IntDatSrds0Out(7), -- out	(1)
-		Q2				=> IntDatSrds0Out(5), -- out	(3)
-		Q3				=> IntDatSrds0Out(3), -- out	(5)
-		Q4				=> IntDatSrds0Out(1), -- out	(7)
-		Q5				=> open, 		-- out
-		Q6				=> open, 		-- out
-		SHIFTIN1		=> Low, 		-- in
-		SHIFTIN2		=> Low 			-- in
-	);
------------------------------------------------------------------------------------------------
--- ISERDES for channel ONE
------------------------------------------------------------------------------------------------
-AdcData_I_Isrds_D1_p : ISERDESE1
-	generic map (
-		SERDES_MODE			=> "MASTER",			-- 
-		INTERFACE_TYPE		=> "NETWORKING",		-- 
-		IOBDELAY			=> "NONE",				-- 
-		DATA_RATE 			=> "SDR", 				-- 
-		DATA_WIDTH 			=> IntIsrdsDataWidth,	-- <-- Number of bits
-		DYN_CLKDIV_INV_EN	=> FALSE, 				-- 
-		DYN_CLK_INV_EN		=> FALSE, 				-- 
-		NUM_CE				=> 1, 					-- 
-		OFB_USED			=> FALSE 				-- 
-	)
-	port map (
-		D				=> DatD1_p,		-- in
-		DDLY			=> Low, 		-- in
-		DYNCLKDIVSEL	=> Low, 		-- in
-		DYNCLKSEL		=> Low, 		-- in
-		OFB				=> Low, 		-- in
-		BITSLIP			=> DatBitSlip_p,-- in
-		CE1				=> IntDatDone,	-- in
-		CE2				=> Low,			-- in
-		RST				=> DatRst,	    -- in
-		CLK				=> IntDatClk, 	-- in
-		CLKB			=> Low, 		-- in
-		CLKDIV			=> DatClkDiv, 	-- in
-		OCLK			=> Low, 		-- in
-		SHIFTOUT1		=> open, 		-- out
-		SHIFTOUT2		=> open, 		-- out
-		O				=> open, 		-- out
-		Q1				=> IntDatSrds1Out(6), -- out	(0)
-		Q2				=> IntDatSrds1Out(4), -- out	(2)
-		Q3				=> IntDatSrds1Out(2), -- out	(4)
-		Q4				=> IntDatSrds1Out(0), -- out	(6)
-		Q5				=> open, 		-- out
-		Q6				=> open, 		-- out
-		SHIFTIN1		=> Low, 		-- in
-		SHIFTIN2		=> Low 			-- in
-	);
-AdcData_I_Isrds_D1_n : ISERDESE1
-	generic map (
-		SERDES_MODE			=> "MASTER",			-- 
-		INTERFACE_TYPE		=> "NETWORKING",		-- 
-		IOBDELAY			=> "NONE",				-- 
-		DATA_RATE 			=> "SDR", 				-- 
-		DATA_WIDTH 			=> IntIsrdsDataWidth,	-- <-- Number of bits
-		DYN_CLKDIV_INV_EN	=> FALSE, 				-- 
-		DYN_CLK_INV_EN		=> FALSE, 				-- 
-		NUM_CE				=> 1, 					-- 
-		OFB_USED			=> FALSE 				-- 
-	)
-	port map (
-		D				=> DatD1_n,		-- in
-		DDLY			=> Low, 		-- in
-		DYNCLKDIVSEL	=> Low, 		-- in
-		DYNCLKSEL		=> Low, 		-- in
-		OFB				=> Low, 		-- in
-		BITSLIP			=> DatBitSlip_n,-- in
-		CE1				=> IntDatDone,	-- in
-		CE2				=> Low,			-- in
-		RST				=> DatRst,	    -- in
-		CLK				=> IntDatClk_n,	-- in
-		CLKB			=> Low, 		-- in
-		CLKDIV			=> DatClkDiv, 	-- in
-		OCLK			=> Low, 		-- in
-		SHIFTOUT1		=> open, 		-- out
-		SHIFTOUT2		=> open, 		-- out
-		O				=> open, 		-- out
-		Q1				=> IntDatSrds1Out(7), -- out	(1)
-		Q2				=> IntDatSrds1Out(5), -- out	(3)
-		Q3				=> IntDatSrds1Out(3), -- out	(5)
-		Q4				=> IntDatSrds1Out(1), -- out	(7)
-		Q5				=> open, 		-- out
-		Q6				=> open, 		-- out
-		SHIFTIN1		=> Low, 		-- in
-		SHIFTIN2		=> Low 			-- in
-	);
------------------------------------------------------------------------------------------------
-Gen_1_DatBus : if (DatBits(C_AdcBits)/2) = 6 generate
-begin
-	IntDatSrds0 <= not IntDatSrds0Out(5) & IntDatSrds0Out(4) &
-					not IntDatSrds0Out(3) & IntDatSrds0Out(2) &
-					not IntDatSrds0Out(1) & IntDatSrds0Out(0);
-	IntDatSrds1 <= not IntDatSrds1Out(5) & IntDatSrds1Out(4) &
-					not IntDatSrds1Out(3) & IntDatSrds1Out(2) &
-					not IntDatSrds1Out(1) & IntDatSrds1Out(0);
-end generate;
-Gen_2_DatBus : if (DatBits(C_AdcBits)/2) = 8 generate
-begin
-	IntDatSrds0 <= not IntDatSrds0Out(7) & IntDatSrds0Out(6) &
-					not IntDatSrds0Out(5) & IntDatSrds0Out(4) &
-					not IntDatSrds0Out(3) & IntDatSrds0Out(2) &
-					not IntDatSrds0Out(1) & IntDatSrds0Out(0);
-	IntDatSrds1 <= not IntDatSrds1Out(7) & IntDatSrds1Out(6) &
-					not IntDatSrds1Out(5) & IntDatSrds1Out(4) &
-					not IntDatSrds1Out(3) & IntDatSrds1Out(2) &
-					not IntDatSrds1Out(1) & IntDatSrds1Out(0);
-end generate; 
------------------------------------------------------------------------------------------------
--- DATA REGISTER
------------------------------------------------------------------------------------------------
-Gen_1_DatReg : for n in (DatBits(C_AdcBits)/2)-1 downto 0 generate 
-    AdcData_I_Fdce_Reg0 : FDCE
-        generic map (INIT => '0')  -- bit
-        port map (D => IntDatSrds0(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
-                  Q => IntDat0(n));
-    AdcData_I_Fdce_Reg1 : FDCE
-        generic map (INIT => '0')  -- bit
-        port map (D => IntDatSrds1(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
-                  Q => IntDat1(n));
-end generate Gen_1_DatReg;  
------------------------------------------------------------------------------------------------
--- BIT SWAP MULTIPLEXER and REGISTER
--- Swap the bits in correct order when the pattern detected is bit swapped.
------------------------------------------------------------------------------------------------
-Gen_2_DatMux : for n in (DatBits(C_AdcBits)/4)-1 downto 0 generate
-begin
-    IntDat0Mux((n*2)+1) <= IntDat0(n*2)     when (DatSwapMux = '1') else IntDat0((n*2)+1);
-    IntDat0Mux(n*2)     <= IntDat0((n*2)+1) when (DatSwapMux = '1') else IntDat0(n*2);
-    IntDat1Mux((n*2)+1) <= IntDat1(n*2)     when (DatSwapMux = '1') else IntDat1((n*2)+1);
-    IntDat1Mux(n*2)     <= IntDat1((n*2)+1) when (DatSwapMux = '1') else IntDat1(n*2);
-end generate Gen_2_DatMux;
-Gen_3_DatReg : for n in (DatBits(C_AdcBits)/2)-1 downto 0 generate
-    AdcData_I_Fdce_Reg2 : FDCE
-        generic map (INIT => '0')  -- bit
-        port map (D => IntDat0Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
-                  Q => IntDat0Swp(n));
-    AdcData_I_Fdce_Reg3 : FDCE
-        generic map (INIT => '0')  -- bit
-        port map (D => IntDat1Mux(n), C => DatClkDiv, CE => IntDatEna, CLR => DatReSync,
-                  Q => IntDat1Swp(n));
-end generate Gen_3_DatReg;
------------------------------------------------------------------------------------------------
--- 1-WIRE, 12x SERIALIZATION for 12-bit ADCs
--- The data from one ADC will show up in the output of one interface channel. It is so that the
--- 32-bit output of the interface shows both channels. Bits 31:16 show the upper channel and
--- bits 15:0 show the lower channel.
------------------------------------------------------------------------------------------------
-Gen_1w_12b : if (C_AdcBits = 12 and C_AdcWireInt = 1) generate
-	-- 1-wire mode is only coded for BIT wise operation.
-	Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
---		-- MSB first.
---		-- Output	: 31						16	15							0
---		--			: "0000" & MSB(5:0) & LSB(5:0)	"0000" & MSB(5:0) & LSB(5:0)
-        IntDatSwpBus <= "0000" & IntDat1Swp(5 downto 0) & IntDat1Swp(5 downto 0) &
-                        "0000" & IntDat0Swp(5 downto 0) & IntDat0Swp(5 downto 0);
-        Gen_1_H : for n in 6 to 15 generate
-            I_Fdce_HH : FDCE
-                generic map (INIT => '0')
-                port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
-                          CLR => DatReSync, Q => DatOut(n+16));
-            I_Fdce_HL : FDCE
-                generic map (INIT => '0')
-                port map (D => IntDatSwpBus(n), CE => DatMsbRegEna, C => DatClkDiv,
-                          CLR => DatReSync, Q => DatOut(n));
-        end generate Gen_1_H;
-        Gen_1_L : for n in 0 to 5 generate
-            I_Fdce_LH : FDCE
-                generic map (INIT => '0')
-                port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
-                          CLR => DatReSync, Q => DatOut(n+16));
-            I_Fdce_LL : FDCE
-                generic map (INIT => '0')
-                port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                          CLR => DatReSync, Q => DatOut(n));
-        end generate Gen_1_L;
-	end generate;
-	Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
-		-- LSB first.
-		-- Output	: 31             22 & 21    16 & 15              6 & 5      0
-		--			: "0000" & LSB(0:5) & MSB(0:5)   "0000" & LSB(0:5) & MSB(0:5)
-		IntDatSwpBus <= "0000" & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & -- 31-|
-		                         IntDat1Swp(3) & IntDat1Swp(4) & IntDat1Swp(5) & --    |-22
-		                IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) &          -- 21-|
-		                IntDat1Swp(3) & IntDat1Swp(4) & IntDat1Swp(5) &          --    |-16
-		                "0000" & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & -- 15-|
-                                 IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5) & --    |-6
-                        IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) &          --  5-|
-                        IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5);           --    |-0
-        Gen_1_H : for n in 6 to 15 generate
-            I_Fdce_HH : FDCE
-                generic map (INIT => '0')
-                port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
-                          CLR => DatReSync, Q => DatOut(n+16));
-            I_Fdce_HL : FDCE
-                generic map (INIT => '0')
-                port map (D => IntDatSwpBus(n), CE => DatMsbRegEna, C => DatClkDiv,
-                          CLR => DatReSync, Q => DatOut(n));
-        end generate Gen_1_H;
-        Gen_1_L : for n in 0 to 5 generate
-            I_Fdce_LH : FDCE
-                generic map (INIT => '0')
-                port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
-                          CLR => DatReSync, Q => DatOut(n+16));
-            I_Fdce_LL : FDCE
-                generic map (INIT => '0')
-                port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                          CLR => DatReSync, Q => DatOut(n));
-        end generate Gen_1_L;
-	end generate;
-end generate;
------------------------------------------------------------------------------------------------
--- 2-WIRE, 12x SERIALIZATION for 12-bit ADCs
--- Only one of these options can be chosen at a time.
---	2-wire, Msb-Bit or Msb-Byte
---	2-wire, Lsb-Bit or Lsb-Byte
------------------------------------------------------------------------------------------------
-Gen_2w_12b : if (C_AdcBits = 12 and C_AdcWireInt = 2) generate
-	Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
-	-- Bit mode, MSB First
-	-- Bit			: 5    4   3   2   1   0
-	-- Channel 0	: D10, D8, D6, D4, D2, D0
-	-- Channel 1	: D11, D9, D7, D5, D3, D1
-	-- Output		: 0 0 0 0, D11, D10,  D9,  D8,  D7,  D6,  D5,  D4,  D3,  D2,  D1,  D0
-	--				: 0 0 0 0, 1_5, 0_5, 1_4, 0_4, 1_3, 0_3, 1_2, 0_2, 1_1, 0_1, 1_0, 0_0
-        Gen_1_Bit :	if C_AdcBytOrBitMode = 1 generate	-- Bit mode
-            IntDatSwpBus <= "0000"
-                            & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
-                            & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
-                            & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
-                            & "0000"
-                            & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
-                            & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
-                            & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0);
-            Gen_1_HL : for n in 0 to 15 generate
-                I_Fdce_H : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+16));
-                I_Fdce_L : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n));
-            end generate Gen_1_HL;
-		end generate;
-	-- Byte mode, MSB First
-	-- Bit			: 5    4    3   2   1   0
-	-- Channel 0	: D5,  D4,  D3, D2, D1, D0
-	-- Channel 1	: D11, D10, D9, D8, D7, D6
-	-- Output		: 0 0 0 0, D11, D10,  D9,  D8,  D7,  D6,  D5,  D4,  D3,  D2,  D1,  D0
-	--				: 0 0 0 0, 1_5, 1_4, 1_3, 1_2, 1_1, 1_0, 0_5, 0_4, 0_3, 0_2, 0_1, 0_0
-		Gen_1_Byt : if C_AdcBytOrBitMode = 0 generate	-- Byte Mode
-            IntDatSwpBus <= "0000"
-                            & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(3) & IntDat1Swp(2)
-                            & IntDat1Swp(1) & IntDat1Swp(0) & IntDat0Swp(5) & IntDat0Swp(4)
-                            & IntDat0Swp(3) & IntDat0Swp(2) & IntDat0Swp(1) & IntDat0Swp(0)
-                            & "0000"
-                            & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(3) & IntDat1Swp(2)
-                            & IntDat1Swp(1) & IntDat1Swp(0) & IntDat0Swp(5) & IntDat0Swp(4)
-                            & IntDat0Swp(3) & IntDat0Swp(2) & IntDat0Swp(1) & IntDat0Swp(0);
-            Gen_1_HL : for n in 0 to 15 generate
-                I_Fdce_H : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+16));
-                I_Fdce_L : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n));
-            end generate Gen_1_HL;
-		end generate;
-	end generate;
---
-	Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
-	-- Bit mode, LSB First
-	-- Bit			: 5   4   3   2   1   0
-	-- Channel 0	: D0, D2, D4, D6, D8, D10
-	-- Channel 1	: D1, D3, D5, D7, D9, D11
-	-- Output		: 0 0 0 0, D11, D10,  D9,  D8,  D7,  D6,  D5,  D4,  D3,  D2,  D1,  D0
-	--				: 0 0 0 0, 1_0, 0_0, 1_1, 0_1, 1_2, 0_2, 1_3, 0_3, 1_4, 0_4, 1_5, 0_5
-		Gen_1_Bit :	if C_AdcBytOrBitMode = 1 generate	-- Bit mode
-            IntDatSwpBus <= "0000"
-                            & IntDat1Swp(0) & IntDat0Swp(0) & IntDat1Swp(1) & IntDat0Swp(1)
-                            & IntDat1Swp(2) & IntDat0Swp(2) & IntDat1Swp(3) & IntDat0Swp(3)
-                            & IntDat1Swp(4) & IntDat0Swp(4) & IntDat1Swp(5) & IntDat0Swp(5)
-                            & "0000"
-                            & IntDat1Swp(0) & IntDat0Swp(0) & IntDat1Swp(1) & IntDat0Swp(1)
-                            & IntDat1Swp(2) & IntDat0Swp(2) & IntDat1Swp(3) & IntDat0Swp(3)
-                            & IntDat1Swp(4) & IntDat0Swp(4) & IntDat1Swp(5) & IntDat0Swp(5);
-            Gen_1_HL : for n in 0 to 15 generate
-               I_Fdce_H : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+16));
-                I_Fdce_L : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n));
-            end generate Gen_1_HL;
-		end generate;
-	-- Byte Mode, LSB First
-	-- Bit			: 5   4   3   2   1    0
-	-- Channel 0	: D0, D1, D2, D3, D4,  D5
-	-- Channel 1	: D6, D7, D8, D9, D10, D11
-	-- Output		: 0 0 0 0, D11, D10,  D9,  D8,  D7,  D6,  D5,  D4,  D3,  D2,  D1,  D0
-	--				: 0 0 0 0, 1_0, 1_1, 1_2, 1_3, 1_4, 1_5, 0_0, 0_1, 0_2, 0_3, 0_4, 0_5
-		Gen_1_Byt : if C_AdcBytOrBitMode = 0 generate	-- Byte Mode
-            IntDatSwpBus <= "0000"
-                            & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
-                            & IntDat1Swp(4) & IntDat1Swp(5) & IntDat0Swp(0) & IntDat0Swp(1)
-                            & IntDat0Swp(2) & IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5)
-                            & "0000"
-                            & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
-                            & IntDat1Swp(4) & IntDat1Swp(5) & IntDat0Swp(0) & IntDat0Swp(1)
-                            & IntDat0Swp(2) & IntDat0Swp(3) & IntDat0Swp(4) & IntDat0Swp(5);
-            Gen_1_HL : for n in 0 to 15 generate
-                I_Fdce_H : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+16));
-                I_Fdce_L : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n));
-            end generate Gen_1_HL;
-		end generate;
-	end generate;
-end generate;
------------------------------------------------------------------------------------------------
--- 1-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs
--- The data from one ADC will show up in the output of one interface channel. It is so that the
--- 32-bit output of the interface shows both channels. Bits 31:16 show the upper channel (CH_1) 
--- and bits 15:0 show the lower (CH_0) channel. 
------------------------------------------------------------------------------------------------
-Gen_1w_1416b : if (C_AdcBits /= 12 and C_AdcWireInt = 1) generate
-	-- 1-wire is only coded for BIT wise operation
-	Gen_1_Msb : if C_AdcMsbOrLsbFst = 0 generate
-        IntDatSwpBus <= IntDat1Swp(7 downto 0) & IntDat1Swp(7 downto 0) &
-                        IntDat0Swp(7 downto 0) & IntDat0Swp(7 downto 0);
-            Gen_1_HL : for n in 0 to 7 generate
-                I_Fdce_HH : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+24), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+24));
-                I_Fdce_HL : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+8), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+8));
-                I_Fdce_LH : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+16));
-                I_Fdce_LL : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n));
-            end generate Gen_1_HL;
-	end generate;
-	Gen_1_Lsb : if C_AdcMsbOrLsbFst = 1 generate
-            IntDatSwpBus <= IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3) &
-                            IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7) &
-                            IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3) &
-                            IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7) &
-                            IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3) &
-                            IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(7) &
-                            IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3) &
-                            IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(7);
-            Gen_1_HL : for n in 0 to 7 generate
-                I_Fdce_HH : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+24), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+24));
-                I_Fdce_HL : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+8), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+8));
-                I_Fdce_LH : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+16), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+16));
-                I_Fdce_LL : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n));
-            end generate Gen_1_HL;
-	end generate;
-end generate;
------------------------------------------------------------------------------------------------
--- 2-WIRE, 16x SERIALIZATION for 14-bit and 16-bit ADCs
--- Only one of these options can be chosen at a time.
---	2-wire, Msb-Bit or Msb-Byte
---	2-wire, Lsb-Bit or Lsb-Byte
------------------------------------------------------------------------------------------------
-Gen_1416Bit : if (C_AdcBits /= 12 and C_AdcWireInt = 2) generate
---	Shift in order is assumed MSB first.
-	Gen_2_Msb : if C_AdcMsbOrLsbFst = 0 generate
-	-- Bit mode, MSB First, 14-bits (16-bits)
-	-- Bit			: 7,       6,   5,   4,  3,  2,  1,  0
-	-- Channel 0	: 0/(D14), D12, D10, D8, D6, D4, D2, D0
-	-- Channel 1	: 0/(D15), D13, D11, D9, D7, D5, D3, D1
-		Gen1_Bit : if C_AdcBytOrBitMode = 1 generate	-- Bit mode
-            IntDatSwpBus <= IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
-                            & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
-                            & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
-                            & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2)
-                            & IntDat1Swp(5) & IntDat0Swp(5) & IntDat1Swp(4) & IntDat0Swp(4)
-                            & IntDat1Swp(7) & IntDat0Swp(7) & IntDat1Swp(6) & IntDat0Swp(6)
-                            & IntDat1Swp(1) & IntDat0Swp(1) & IntDat1Swp(0) & IntDat0Swp(0)
-                            & IntDat1Swp(3) & IntDat0Swp(3) & IntDat1Swp(2) & IntDat0Swp(2);
-            Gen_1_H : for n in 0 to 15 generate
-                I_Fdce_H : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+16));
-                I_Fdce_L : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n));
-            end generate Gen_1_H;
-		end generate;                        
-	-- Byte Mode, MSB First, 14-bits (16-bits)
-	-- Data Bit		: 7,       6,       5,   4,   3,   2,   1,  0,
-	-- Channel 0	: D7,      D6,      D5,  D4,  D3,  D2,  D1, D0,
-	-- Channel 1	: 0/(D15), 0/(D14), D13, D12, D11, D10, D9, D8
-		Gen1_Byt : if C_AdcBytOrBitMode = 0 generate	-- Byte Mode (not tested)
-            IntDatSwpBus <= IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(7) & IntDat1Swp(6)
-                            & IntDat1Swp(1) & IntDat1Swp(0) & IntDat1Swp(3) & IntDat1Swp(2)
-                            & IntDat0Swp(5) & IntDat0Swp(4) & IntDat0Swp(7) & IntDat0Swp(6)
-                            & IntDat0Swp(1) & IntDat0Swp(0) & IntDat0Swp(3) & IntDat0Swp(2)
-                            & IntDat1Swp(5) & IntDat1Swp(4) & IntDat1Swp(7) & IntDat1Swp(6)
-                            & IntDat1Swp(1) & IntDat1Swp(0) & IntDat1Swp(3) & IntDat1Swp(2)
-                            & IntDat0Swp(5) & IntDat0Swp(4) & IntDat0Swp(7) & IntDat0Swp(6)
-                            & IntDat0Swp(1) & IntDat0Swp(0) & IntDat0Swp(3) & IntDat0Swp(2);
-            Gen_1_H : for n in 0 to 15 generate
-                I_Fdce_H : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+16));
-                I_Fdce_L : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n));
-            end generate Gen_1_H;
-		end generate;
-	end generate;
--- Shift in order is assumed LSB first
-	Gen_2_Lsb : if C_AdcMsbOrLsbFst = 1 generate
-	-- Bit mode, LSB First, 14-bits (16-bit)
-	-- Data Bit		; 7,  6,  5,  4,  3,  2,   1,   0
-	-- Channel 0	: D0, D2, D4, D6, D8, D10, D12, 0/(D14)
-	-- Channel 1	: D1, D3, D5, D7, D9, D11, D13, 0/(D15)
-		Gen_2_Bit : if C_AdcBytOrBitMode = 1 generate	-- Bit mode
-            IntDatSwpBus <= IntDat0Swp(2) & IntDat1Swp(2) & IntDat0Swp(3) & IntDat1Swp(3)
-                            & IntDat0Swp(0) & IntDat1Swp(0) & IntDat0Swp(1) & IntDat1Swp(1)
-                            & IntDat0Swp(6) & IntDat1Swp(6) & IntDat0Swp(7) & IntDat1Swp(7)
-                            & IntDat0Swp(4) & IntDat1Swp(4) & IntDat0Swp(5) & IntDat1Swp(5)
-                            & IntDat0Swp(2) & IntDat1Swp(2) & IntDat0Swp(3) & IntDat1Swp(3)
-                            & IntDat0Swp(0) & IntDat1Swp(0) & IntDat0Swp(1) & IntDat1Swp(1)
-                            & IntDat0Swp(6) & IntDat1Swp(6) & IntDat0Swp(7) & IntDat1Swp(7)
-                            & IntDat0Swp(4) & IntDat1Swp(4) & IntDat0Swp(5) & IntDat1Swp(5);
-            Gen_1_H : for n in 0 to 15 generate
-                I_Fdce_H : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+16));
-                I_Fdce_L : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n));
-            end generate Gen_1_H;
-		end generate;
-	-- Byte Mode, LSB First, 14-bits (16-bit)
-	-- Data Bit		: 7,  6,  5,   4,   3,   2,   1,      0
-	-- Channel 0	: D0, D1, D2,  D3,  D4,  D5,  D6,      D7
-	-- Channel 1	: D8, D9, D10, D11, D12, D13, 0/(D14), 0/(D15)
-		Gen_2_Byt : if C_AdcBytOrBitMode = 0 generate	-- Byte Mode (not tested)
-            IntDatSwpBus <= IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
-                            & IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7)
-                            & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3) 
-                            & IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(6)
-                            & IntDat1Swp(0) & IntDat1Swp(1) & IntDat1Swp(2) & IntDat1Swp(3)
-                            & IntDat1Swp(4) & IntDat1Swp(5) & IntDat1Swp(6) & IntDat1Swp(7)
-                            & IntDat0Swp(0) & IntDat0Swp(1) & IntDat0Swp(2) & IntDat0Swp(3) 
-                            & IntDat0Swp(4) & IntDat0Swp(5) & IntDat0Swp(6) & IntDat0Swp(6);
-            Gen_1_H : for n in 0 to 15 generate
-                I_Fdce_H : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n+16), CE => DatMsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n+16));
-                I_Fdce_L : FDCE
-                    generic map (INIT => '0')
-                    port map (D => IntDatSwpBus(n), CE => DatLsbRegEna, C => DatClkDiv,
-                              CLR => DatReSync, Q => DatOut(n));
-            end generate Gen_1_H;
-		end generate;
-	end generate;
-end generate;
---
------------------------------------------------------------------------------------------------
-end  AdcData_struct;
\ No newline at end of file
diff --git a/FEE_ADC32board/modules/ADCrefdesign/AdcFrame.vhd b/FEE_ADC32board/modules/ADCrefdesign/AdcFrame.vhd
deleted file mode 100644
index 0c5a3ff..0000000
--- a/FEE_ADC32board/modules/ADCrefdesign/AdcFrame.vhd
+++ /dev/null
@@ -1,859 +0,0 @@
------------------------------------------------------------------------------------------------
--- © Copyright 2007 - 2011, Xilinx, Inc. All rights reserved.
--- This file contains confidential and proprietary information of Xilinx, Inc. and is
--- protected under U.S. and international copyright and other intellectual property laws.
------------------------------------------------------------------------------------------------
---
--- Disclaimer:
---		This disclaimer is not a license and does not grant any rights to the materials
---		distributed herewith. Except as otherwise provided in a valid license issued to you
---		by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
---		ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
---		WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
---		TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
---		PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
---		negligence, or under any other theory of liability) for any loss or damage of any
---		kind or nature related to, arising under or in connection with these materials,
---		including for any direct, or any indirect, special, incidental, or consequential
---		loss or damage (including loss of data, profits, goodwill, or any type of loss or
---		damage suffered as a result of any action brought by a third party) even if such
---		damage or loss was reasonably foreseeable or Xilinx had been advised of the
---		possibility of the same.
---
--- CRITICAL APPLICATIONS
---		Xilinx products are not designed or intended to be fail-safe, or for use in any
---		application requiring fail-safe performance, such as life-support or safety devices
---		or systems, Class III medical devices, nuclear facilities, applications related to
---		the deployment of airbags, or any other applications that could lead to death,
---		personal injury, or severe property or environmental damage (individually and
---		collectively, "Critical Applications"). Customer assumes the sole risk and
---		liability of any use of Xilinx products in Critical Applications, subject only to
---		applicable laws and regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 
---
---		Contact:    e-mail  hotline@xilinx.com        phone   + 1 800 255 7778
---   ____  ____
---  /   /\/   /
--- /___/  \  /   Vendor: Xilinx
--- \   \   \/    Version: 
---  \   \        Filename: AdcFrame.vhd
---  /   /        Date Last Modified:	29 Mar 11
--- /___/   /\    Date Created: 			05 Oct 07
--- \   \  /  \
---  \___\/\___\
--- 
--- Device:		Virtex-6
--- Author:		Marc Defossez
--- Entity Name: AdcFrame
--- Purpose:		This file is part of an FPGA interface for a Texas Instruments ADC.
--- Tools:		ISE_13.1
--- Limitations: none
---
--- Revision History:
---  Rev. 28 Oct 2009
---      Corrected the circuit to check for "Bouble Nibble" at the output of the ISEDRES.
---		Made the reaction of this circuit immediate (asynchrounous).
---		Then synchronousity steps in after registering the signals.
---  Rev. 16 feb 2011
---      Replace HDL synthesized FFs by instantiated FFs for frame data path.
---      Check implementation results is ISE_12.4 with PlanAhead through a AdcFrame_Toplevel.
---  Rev 07 Mar 2011
---      Modified the calculation of some "generate" parameters to be able to work in 1-wire
---      and 2-wire mode. generate parameters to create sets of FFs.
---  Rev 09 Mar 2011
---      Problem solved with 1-wire interface not finding correct frame pattern.
---      In the past 1-wire and 2-wire was selected with 0 and 1 while for recent interfaces
---      this is changed to 1 and 2 (To reflect in the selection the interface type).
---      The function calculating the frame pattern for use with the comparator still used
---      the old selection style. Result was that 2-wire functioned normally and 1-wire
---      returned a all zero compare pattern.
---      Finalized the integration and documentation of the "DoubleNibbleDetect".
------------------------------------------------------------------------------------------------
--- Naming Conventions:
---   active low signals:                    "*_n"
---   clock signals:                         "clk", "clk_div#", "clk_#x"
---   reset signals:                         "rst", "rst_n"
---   generics:                              "C_*"
---   user defined types:                    "*_TYPE"
---   state machine next state:              "*_ns"
---   state machine current state:           "*_cs"
---   combinatorial signals:                 "*_com"
---   pipelined or register delay signals:   "*_d#"
---   counter signals:                       "*cnt*"
---   clock enable signals:                  "*_ce"
---   internal version of output port:       "*_i"
---   device pins:                           "*_pin"
---   ports:                                 "- Names begin with Uppercase"
---   processes:                             "*_PROCESS"
---   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------------------------
---
-library IEEE;
-	use IEEE.std_logic_1164.all;
-	use IEEE.std_logic_UNSIGNED.all;
-	use IEEE.std_logic_textio.all;
-	use std.textio.all;
-library UNISIM;
-	use UNISIM.VCOMPONENTS.all;
-library AdcFrame_lib;
-    use AdcFrame_lib.all;
---library AdcMem;
---    use AdcMem.all;
-    
------------------------------------------------------------------------------------------------
--- Entity pin description
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
-entity AdcFrame is
-	generic (
-		C_AdcBits			: integer;
-		C_AdcWireInt		: integer;
-		C_FrmPattern		: string
-	);
-    port (
-        FrmClk_n		: in std_logic;		-- input n from IBUFDS_DIFF_OUT
-        FrmClk_p		: in std_logic;		-- input p from IBUFDS_DIFF_OUT
-        FrmClkRst		: in std_logic;
-        FrmClkEna		: in std_logic;
-        FrmClk			: in std_logic;
-        FrmClkDiv		: in std_logic;
-        FrmClkDone		: in std_logic;		-- Input from clock syncronisation.
-        FrmClkReSync	: in std_logic;
-        FrmClkBitSlip_p	: out std_logic;
-        FrmClkBitSlip_n	: out std_logic;
-        FrmClkSwapMux	: out std_logic;
-        FrmClkMsbRegEna	: out std_logic;
-        FrmClkLsbRegEna	: out std_logic;
-        FrmClkReSyncOut	: out std_logic;
-		FrmClkDat		: out std_logic_vector(15 downto 0);
-        FrmClkSyncWarn	: out std_logic;
-		  Frame_out : out std_logic;
-		  testOK : out std_logic;
-			testword0 			  : out std_logic_vector(35 downto 0)
-    );
-end AdcFrame;
------------------------------------------------------------------------------------------------
--- Architecture section
------------------------------------------------------------------------------------------------
-architecture AdcFrame_struct of AdcFrame  is
------------------------------------------------------------------------------------------------
--- Component Instantiation
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
--- Constants, Signals and Attributes Declarations
------------------------------------------------------------------------------------------------
--- Functions
--- A std_logic_vector is converted to a string.
-	function stdlvec_to_str(inp: std_logic_vector) return string is
-	variable temp: string(inp'left+1 downto 1) := (others => 'X');
-	begin
-		for i in inp'reverse_range loop
-			if (inp(i) = '1') then
-				temp(i+1) := '1';
-			elsif (inp(i) = '0') then
-				temp(i+1) := '0'; 
-			end if;
-		end loop;
-	return temp;
-	end function stdlvec_to_str;
---
--- A string is converted to a std_logic_vector.
-	function str_to_stdlvec(Inp: string) return std_logic_vector is
-	variable Temp : std_logic_vector(Inp'range) := (others => 'X');
-	begin 
-		for i in Inp'range loop
-			if (Inp(i) = '1') then
-				Temp(i) := '1';
-			elsif (Inp(i) = '0') then
-				Temp(i) := '0'; 
-			end if;
-		end loop;
-	return Temp;
-	end function str_to_stdlvec;
---
--- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.
--- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.
--- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.
-	function FrmBits (Bits : integer) return integer is
-	variable Temp : integer;
-	begin
-		if (Bits = 12) then
-			Temp := 12;
-		elsif (Bits = 14) then
-			Temp := 16;
-		elsif (Bits = 16) then
-			Temp := 16;
-		end if;
-	return Temp;
-	end function FrmBits;
---
--- Word symmetry check
--- A word (16-bit) is checked for bit pair symmetry
--- Example: In one byte there are 16 possible symmetry positions.
--- 			00000000, 00000011, 00001100, 00001111,
--- 			00110000, 00110011, 00111100, 00111111,
--- 			11000000, 11000011, 11001100, 11001111,
--- 			11110000, 11110011, 11111100, 11111111,
--- Bit_7=Bit_6, Bit_5=Bit_4, Bit_3=Bit_2, and Bit_1=Bit_0
-	function SymChck (Inp: std_logic_vector) return std_logic is
-	variable Temp : std_logic_vector ((Inp'left-1)/2 downto 0) := (others => '0');
-	variable Sym : std_logic := '0';
-	begin
-		for n in (Inp'left-1)/2 downto 0 loop
-			Temp(n) := Inp((n*2)+1) xor Inp(n*2);
-			Sym := Temp(n) or Sym;
-		end loop;
-		assert false
-		report CR & " Pattern XORed/ORed = " & stdlvec_to_str(Temp) & CR
-		severity note;
-	return Sym;
-	end function SymChck;
---
--- When a symmetric byte, bit pattern is found, make the requested pattern rotate
--- by one bit to become a non-symmetric pattern.	
-	function BitShft(Inp: std_logic_vector; Wire: integer) return std_logic_vector is
-	variable Temp : std_logic_vector (Inp'range):= (others => '0');
-	begin
--- Bit shift all bits.
--- Example: 16-bit frame word = 11111111_00000000 or 00000000_11110000
--- After shifting the word returned looks as: 11111110_00000001 and 00000000_01111000
-		if (SymChck(Inp) = '0') then
-			if (Wire = 1 ) then		-- 1-wire, shift 15-bits
-				for n in Inp'left downto 0 loop
-					if (n /= 0) then
-						Temp(n) := Inp(n-1);
-					elsif (n = 0) then
-						Temp(Temp'right) := Inp(Inp'left);
-					end if;
-				end loop;
-			else -- (Wire = 2)		-- 2-wire, shift 8-bits
-				for n in (Inp'left-8) downto 0 loop
-					if (n /= 0) then
-						Temp(n) := Inp(n-1);
-					elsif (n = 0) then
-						Temp(Temp'right) := Inp(Inp'left-8);
-					end if;
-				end loop;
-			end if;
-		elsif (SymChck(Inp) = '1') then
-		-- Don't do anything, return the word as it came in.
-			Temp := Inp;
-		end if;
-		--
-		assert false
-		report	CR &
-				" Pattern Shifted = " & stdlvec_to_str(Temp) & CR & 
-				" Comparator Value A = " & stdlvec_to_str(Temp(15 downto 8)) & CR &
-				" Comparator Value B = " & stdlvec_to_str(Temp(7 downto 0)) & CR
-		severity note;
-	return Temp;
-	end function BitShft;
---
--- Bit swap operation: 
--- Bit n of the output string gets bit n-1 of the input. ex: out(7) <= In(6).
--- Bit n-1 of the output string gets bit n of the input. ex: out(6) <= In(7).
--- Bit n-2 of the output string gets bit n-3 of the input. ex: out(5) <= In(4).
--- Bit n-3 of the output string gets bit n-2 of the input. ex: out(4) <= In(5).
--- and etcetera....
--- This:		Bit_7, Bit_6, Bit_5, Bit_4, Bit_3, Bit_2, Bit_1, Bit_0.
--- Results in:	Bit_6, Bit_7, Bit-$, Bit_5, Bit_2, Bit_3, Bit_0, Bit_1.
-	function BitSwap(Inp: std_logic_vector) return std_logic_vector is
-	variable Temp : std_logic_vector (Inp'range);
-	begin
-		for n in (Inp'left-1)/2 downto 0 loop
-			Temp((n*2)+1) := Inp(n*2);
-			Temp(n*2) := Inp((n*2)+1);
-		end loop;
-		assert false
-		report CR &
-				" Pattern Bit Swapped = " & stdlvec_to_str(Temp) & CR &
-				" Comparator Value C = " & stdlvec_to_str(Temp(15 downto 8)) & CR &
-				" Comparator Value D = " & stdlvec_to_str(Temp(7 downto 0))	& CR			
-		severity note;
-	return Temp;
-	end function BitSwap;
---
-	function TermOrNot (Term : integer) return boolean is
-	begin
-		if (Term = 0) then
-			return FALSE;
-		else
-			return TRUE;
-		end if;
-	end TermOrNot;
-	
-component DoubleNibbleDetect is
-	port (
-        Clock   : in std_logic;
-        RstIn   : in std_logic;
-        Final   : out std_logic;
-        DataIn  : in std_logic_vector(3 downto 0);
-        DataOut : out std_logic_vector(3 downto 0)
-	);
-end component;	
-
-component GenPulse is
-    port (
-        Clk		: in std_logic;
-        Ena		: in std_logic;
-        SigIn	: in std_logic;
-        SigOut	: out std_logic
-    );
-end component;
-
---
--- Constants
--- Transform the pattern STRING into a std_logic_vector.
-constant IntPattern	:
-		std_logic_vector(FrmBits(C_AdcBits)-1 downto 0)	:= str_to_stdlvec(C_FrmPattern);
--- Shift the pattern for one bit.
-constant IntPatternBitShifted :
-		std_logic_vector(FrmBits(C_AdcBits)-1 downto 0)	:= BitShft(IntPattern, C_AdcWireInt);
--- Bit swap the by one bit shifted pattern.
-constant IntPatternBitSwapped :
-		std_logic_vector(FrmBits(C_AdcBits)-1 downto 0)	:= BitSwap(IntPatternBitShifted);
--- Define the bytes for pattern comparison.
-constant IntPatternA : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
-		IntPatternBitShifted(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);
-constant IntPatternB : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
-		IntPatternBitShifted((FrmBits(C_AdcBits)/2)-1 downto 0);
-constant IntPatternC : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
-		IntPatternBitSwapped(FrmBits(C_AdcBits)-1 downto FrmBits(C_AdcBits)/2);
-constant IntPatternD : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0) :=
-		IntPatternBitSwapped((FrmBits(C_AdcBits)/2)-1 downto 0);
--- Calculate the data width for a ISERDES.		
-constant IntIsrdsDataWidth : integer := FrmBits(C_AdcBits)/4;
-constant Low : std_logic := '0';
-constant High : std_logic := '1';
-attribute keep                : string;
--- Signals
-signal IntFrmClk			        : std_logic;
-signal IntFrmClk_n			        : std_logic;
-signal IntFrmSrdsOut		        : std_logic_vector (7 downto 0);
---
-signal IntFrmSrdsDatEvn		        : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);
-signal IntFrmSrdsDatOdd             : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);
-signal IntFrmSrdsDatEvn_d           : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);
-signal IntFrmSrdsDatOdd_d           : std_logic_vector((FrmBits(C_AdcBits)/4)-1 downto 0);
-signal IntFrmSrdsDat                : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);
-signal IntFrmDat			        : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);
-signal IntFrmDatMux                 : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);
-signal IntFrmDatSwp			        : std_logic_vector((FrmBits(C_AdcBits)/2)-1 downto 0);
-signal IntFrmDatSwpBus              : std_logic_vector(15 downto 0);
-signal IntFrmClkDat			        : std_logic_vector(15 downto 0);
---
-signal IntFrmDbleNibFnlEvn          : std_logic;
-signal IntFrmDbleNibFnlEvn_d        : std_logic;
-signal IntFrmDbleNibFnlOdd          : std_logic;
-signal IntFrmDbleNibFnlOdd_d        : std_logic;
-signal IntFrmDbleNibFnl		        : std_logic;
---
-signal IntFrmEna			        : std_logic;
-signal IntFrmCmp			        : std_logic_vector(3 downto 0);
-signal IntFrmEquGte			        : std_logic;
-signal IntFrmEqu_d			        : std_logic;
-signal IntFrmSwapMux_d		        : std_logic;
-signal IntFrmSwapMux_d_Ena          : std_logic;
-signal IntFrmLsbMsb_d 		        : std_logic;
-signal IntFrmLsbMsb_d_Ena           : std_logic;
-signal IntFrmMsbAllZero_d 	        : std_logic;
-signal IntFrmMsbAllZero_d_Ena       : std_logic;
---
-signal IntFrmRegEna_d		        : std_logic;
-signal IntFrmMsbRegEna_d	        : std_logic;
-signal IntFrmLsbRegEna_d	        : std_logic;
---
-signal IntFrmEvntCnt		        : std_logic_vector (3 downto 0); -- count event counter
-signal IntFrmEvntCntTc		        : std_logic;
-signal IntFrmEvntCntTc_d	        : std_logic;
-signal IntFrmSlipCnt		        : std_logic_vector (3 downto 0); -- count to 8
-signal IntFrmSlipCntTc		        : std_logic;
-signal IntFrmSlipCntTc_d	        : std_logic;
-signal IntFrmSlipCntTc_d1           : std_logic;
-signal IntFrmSlipCntTc_d2Ena        : std_logic;
-signal IntFrmSlipCntTc_d2           : std_logic;
-signal IntFrmWarnCnt		        : std_logic_vector (2 downto 0);
-signal IntFrmWarnCntTc		        : std_logic;
-signal IntFrmWarnCntTc_d	        : std_logic;
-signal IntFrmClkReSync              : std_logic;
-signal IntFrmReSyncOut		        : std_logic;
---
-signal IntFrmBitSlip		        : std_logic_vector (5 downto 0);
-signal IntFrmEquSet_d		        : std_Logic;
-
-signal Frame_out_S		        : std_Logic;
--- Attributes
-attribute keep of Frame_out_S    : signal is "TRUE";
------------------------------------------------------------------------------------------------
-begin
------------------------------------------------------------------------------------------------
--- ISERDES FOR FRAME CAPTURE
------------------------------------------------------------------------------------------------
-IntFrmClk <= FrmClk;
-IntFrmClk_n <= not FrmClk;
---
-AdcFrame_I_Isrds_p : ISERDESE1
-	generic map (
-		SERDES_MODE			=> "MASTER",			-- 
-		INTERFACE_TYPE		=> "NETWORKING",		-- 
-		IOBDELAY			=> "NONE",				-- 
-		DATA_RATE 			=> "SDR", 				-- 
-		DATA_WIDTH 			=> IntIsrdsDataWidth,	-- <-- Number of bits
-		DYN_CLKDIV_INV_EN	=> FALSE, 				-- 
-		DYN_CLK_INV_EN		=> FALSE, 				-- 
-		NUM_CE				=> 1, 					-- 
-		OFB_USED			=> FALSE 				-- 
-	)
-	port map (
-		D				=> FrmClk_p,		-- in
-		DDLY			=> Low,				-- in
-		DYNCLKDIVSEL	=> Low, 			-- in
-		DYNCLKSEL		=> Low, 			-- in
-		OFB				=> Low, 			-- in
-		BITSLIP			=> IntFrmBitSlip(0),-- in
-		CE1				=> IntFrmEna,      	-- in
-		CE2				=> Low,				-- in
-		RST				=> FrmClkRst,		-- in
-		CLK				=> IntFrmClk,	 	-- in
-		CLKB			=> Low, 			-- in
-		CLKDIV			=> FrmClkDiv,	 	-- in
-		OCLK			=> Low, 			-- in
-		SHIFTOUT1		=> open,	 		-- out
-		SHIFTOUT2		=> open, 			-- out
-		O				=> Frame_out_S, 			-- out
-		Q1				=> IntFrmSrdsOut(6), -- out	(0)
-		Q2				=> IntFrmSrdsOut(4), -- out	(2)
-		Q3				=> IntFrmSrdsOut(2), -- out	(4)
-		Q4				=> IntFrmSrdsOut(0), -- out	(6)
-		Q5				=> open,	 		-- out
-		Q6				=> open, 			-- out
-		SHIFTIN1		=> Low, 			-- in
-		SHIFTIN2		=> Low				-- in
-	);
-Frame_out <= Frame_out_S;
-
-AdcFrame_I_Isrds_n : ISERDESE1
-	generic map (
-		SERDES_MODE			=> "MASTER",			-- 
-		INTERFACE_TYPE		=> "NETWORKING",		-- 
-		IOBDELAY			=> "NONE",				-- 
-		DATA_RATE 			=> "SDR", 				-- 
-		DATA_WIDTH 			=> IntIsrdsDataWidth,	-- 12-bit = 3 and 14/16 b its = 4
-		DYN_CLKDIV_INV_EN	=> FALSE, 				-- 
-		DYN_CLK_INV_EN		=> FALSE, 				-- 
-		NUM_CE				=> 1, 					-- 
-		OFB_USED			=> FALSE 				-- 
-	)
-	port map (
-		D				=> FrmClk_n,		-- in
-		DDLY			=> Low,				-- in
-		DYNCLKDIVSEL	=> Low, 			-- in
-		DYNCLKSEL		=> Low, 			-- in
-		OFB				=> Low, 			-- in
-		BITSLIP			=> IntFrmBitSlip(1),-- in
-		CE1				=> IntFrmEna,      	-- in
-		CE2				=> Low,				-- in
-		RST				=> FrmClkRst,		-- in
-		CLK				=> IntFrmClk_n,	 	-- in
-		CLKB			=> Low, 			-- in
-		CLKDIV			=> FrmClkDiv,	 	-- in
-		OCLK			=> Low, 			-- in
-		SHIFTOUT1		=> open,	 		-- out
-		SHIFTOUT2		=> open, 			-- out
-		O				=> open, 			-- out
-		Q1				=> IntFrmSrdsOut(7), -- out	(1)
-		Q2				=> IntFrmSrdsOut(5), -- out	(3)
-		Q3				=> IntFrmSrdsOut(3), -- out	(5)
-		Q4				=> IntFrmSrdsOut(1), -- out	(7)
-		Q5				=> open,	 		-- out
-		Q6				=> open, 			-- out
-		SHIFTIN1		=> Low, 			-- in
-		SHIFTIN2		=> Low				-- in
-	);
------------------------------------------------------------------------------------------------
--- INVERT THE NEEDED BITS.
------------------------------------------------------------------------------------------------
-Gen_1_FrmBus : if (FrmBits(C_AdcBits)/2) = 6 generate
-	IntFrmSrdsDatEvn <= IntFrmSrdsOut(4) & IntFrmSrdsOut(2) & IntFrmSrdsOut(0);
-	IntFrmSrdsDatOdd <= not IntFrmSrdsOut(5) & not IntFrmSrdsOut(3) & not IntFrmSrdsOut(1); 	
-end generate Gen_1_FrmBus;
-Gen_2_FrmBus : if (FrmBits(C_AdcBits)/2) = 8 generate
-	IntFrmSrdsDatEvn <= IntFrmSrdsOut(6) & IntFrmSrdsOut(4) &
-	                    IntFrmSrdsOut(2) & IntFrmSrdsOut(0);
-    IntFrmSrdsDatOdd <= not IntFrmSrdsOut(7) & not IntFrmSrdsOut(5) &
-                        not IntFrmSrdsOut(3) & not IntFrmSrdsOut(1); 
-end generate Gen_2_FrmBus;
------------------------------------------------------------------------------------------------
--- Double Nibble Detection.
--- When the ADC is used in 1-wire mode the frame pattern is 12 or 16 bits long.
--- It is captured in two ISERDES. One running at rising CLK and the orther runnsing at falling
--- CLK. For some reason, afetr a bitslip a ISERDES can output twice the same nibble of data. 
--- This phenomenon is called ""Double nibble" and as written before happens after a
--- Bitslip request.
--- The output of each ISERDES is first checked for these double nibbles and if needed the
--- ISERDES output is corrected. After that the data is passed into the franme pattern
--- Recognition part of the design. 
------------------------------------------------------------------------------------------------
-Gen_1_DbleNibChk : if (C_AdcWireInt = 1) generate
-    AdcFrame_I_DblNbblDtct_Evn : DoubleNibbleDetect
-        port map (
-            Clock   => FrmClkDiv, -- in
-            RstIn   => FrmClkRst, -- in
-            Final   => IntFrmDbleNibFnlEvn, -- out
-            DataIn  => IntFrmSrdsDatEvn, -- in [3:0]
-            DataOut => IntFrmSrdsDatEvn_d  -- out [3:0]
-        );
---
-    AdcFrame_I_DblNbblDtct_Odd : DoubleNibbleDetect
-        port map (
-            Clock   => FrmClkDiv, -- in
-            RstIn   => FrmClkRst, -- in
-            Final   => IntFrmDbleNibFnlOdd, -- out
-            DataIn  => IntFrmSrdsDatOdd, -- in [3:0]
-            DataOut => IntFrmSrdsDatOdd_d  -- out [3:0]
-        );
---
-    AdcFrame_DblNibFnl_PROCESS : process (FrmClkDiv)
-    begin
-        if (FrmClkRst = '1' ) then
-            IntFrmDbleNibFnlOdd_d <= '0';
-            IntFrmDbleNibFnlEvn_d <= '0';
-        elsif (FrmClkDiv'event and FrmClkDiv = '1') then
-            if (IntFrmDbleNibFnlOdd = '1') then
-                IntFrmDbleNibFnlOdd_d <= '1';
-            else --(IntFrmDbleNibFnlOdd = '0')
-                IntFrmDbleNibFnlOdd_d <= '0';
-            end if;
-            if (IntFrmDbleNibFnlEvn = '1') then
-                IntFrmDbleNibFnlEvn_d <= '1';
-            else --(IntFrmDbleNibFnlOdd = '0')
-                IntFrmDbleNibFnlEvn_d <= '0';
-            end if;
-        end if;
-    end process AdcFrame_DblNibFnl_PROCESS;
---
-    IntFrmDbleNibFnl <= IntFrmDbleNibFnlOdd_d and IntFrmDbleNibFnlEvn_d;
-end generate Gen_1_DbleNibChk;
---
-Gen_2_DbleNibChk : if (C_AdcWireInt = 2) generate
-    IntFrmSrdsDatEvn_d <= IntFrmSrdsDatEvn;
-    IntFrmSrdsDatOdd_d <= IntFrmSrdsDatOdd;
-    IntFrmDbleNibFnl <= Low;
-end generate Gen_2_DbleNibChk;
------------------------------------------------------------------------------------------------
--- DATA REGISTER
------------------------------------------------------------------------------------------------
-Gen_1_DatBus : for n in (FrmBits(C_AdcBits)/4) downto 1 generate
-    IntFrmSrdsDat((n*2)-1) <= IntFrmSrdsDatOdd_d(n-1);
-    IntFrmSrdsDat((n*2)-2) <= IntFrmSrdsDatEvn_d(n-1);
-end generate Gen_1_DatBus;
---
-Gen_1_DatReg : for n in (FrmBits(C_AdcBits)/2)-1 downto 0 generate 
-    AdcFrame_I_Fdce_Reg1 : FDCE
-        generic map (INIT => '0') -- bit
-        port map(D => IntFrmSrdsDat(n), CE => IntFrmEna, C => FrmClkDiv,
-                 CLR => IntFrmReSyncOut, Q => IntFrmDat(n));
-end generate Gen_1_DatReg;
------------------------------------------------------------------------------------------------
--- BIT SWAP MULTIPLEXER and REGISTER
--- Swap the bits in correct order when the pattern detected is bit swapped.
------------------------------------------------------------------------------------------------
-Gen_2_DatMux : for n in (FrmBits(C_AdcBits)/4)-1 downto 0 generate
-begin
-    IntFrmDatMux((n*2)+1) <= IntFrmDat(n*2)     when (IntFrmSwapMux_d = '1') else IntFrmDat((n*2)+1);
-    IntFrmDatMux(n*2)     <= IntFrmDat((n*2)+1) when (IntFrmSwapMux_d = '1') else IntFrmDat(n*2);
-end generate Gen_2_DatMux;
-Gen_3_DatReg : for n in (FrmBits(C_AdcBits)/2)-1 downto 0 generate
-    AdcFrame_I_Fdce_Reg2 : FDCE
-        generic map (INIT => '0')  -- bit
-        port map (D => IntFrmDatMux(n), C => FrmClkDiv, CE => IntFrmEna, CLR => IntFrmReSyncOut,
-                  Q => IntFrmDatSwp(n));
-end generate Gen_3_DatReg;
------------------------------------------------------------------------------------------------
--- FRAME OUTPUT REGISTERS
------------------------------------------------------------------------------------------------
-Gen_4_OutReg12 : if C_AdcBits = 12 generate
-    IntFrmDatSwpBus <= "0000" &
-                       IntFrmDatSwp(5) & IntFrmDatSwp(4) &
-                       IntFrmDatSwp(3) & IntFrmDatSwp(2) &
-                       IntFrmDatSwp(1) & IntFrmDatSwp(0) &
-                       IntFrmDatSwp(5) & IntFrmDatSwp(4) &
-                       IntFrmDatSwp(3) & IntFrmDatSwp(2) &
-                       IntFrmDatSwp(1) & IntFrmDatSwp(0);
-    Gen_4_H : for n in 6 to 15 generate
-        AdcFrame_I_Fdce_FrmClkDatMsb : FDCE
-        generic map (INIT => '0')
-        port map (D => IntFrmDatSwpBus(n), CE => IntFrmMsbRegEna_d, C => FrmClkDiv,
-                CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));
-    end generate Gen_4_H;
-    Gen_4_L : for n in 0 to 5 generate
-        AdcFrame_I_Fdce_FrmClkDatLsb : FDCE
-        generic map (INIT => '0')
-        port map (D => IntFrmDatSwpBus(n), CE => IntFrmLsbRegEna_d, C => FrmClkDiv,
-                CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));
-    end generate Gen_4_L;
-end generate Gen_4_OutReg12;
---
-Gen_5_OutReg12n : if C_AdcBits /= 12 generate
-    IntFrmDatSwpBus <= IntFrmDatSwp(7) & IntFrmDatSwp(6) &
-                       IntFrmDatSwp(5) & IntFrmDatSwp(4) &
-                       IntFrmDatSwp(3) & IntFrmDatSwp(2) &
-                       IntFrmDatSwp(1) & IntFrmDatSwp(0) &
-                       IntFrmDatSwp(7) & IntFrmDatSwp(6) &
-                       IntFrmDatSwp(5) & IntFrmDatSwp(4) &
-                       IntFrmDatSwp(3) & IntFrmDatSwp(2) &
-                       IntFrmDatSwp(1) & IntFrmDatSwp(0);
-    Gen_5_H : for n in 8 to 15 generate
-        AdcFrame_I_Fdce_FrmClkDatMsb : FDCE
-        generic map (INIT => '0')
-        port map (D => IntFrmDatSwpBus(n), CE => IntFrmMsbRegEna_d, C => FrmClkDiv,
-                CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));
-    end generate Gen_5_H;
-    Gen_5_L : for n in 0 to 7 generate
-        AdcFrame_I_Fdce_FrmClkDatLsb : FDCE
-        generic map (INIT => '0')
-        port map (D => IntFrmDatSwpBus(n), CE => IntFrmLsbRegEna_d, C => FrmClkDiv,
-                CLR => IntFrmReSyncOut, Q => IntFrmClkDat(n));
-    end generate Gen_5_L;
-end generate Gen_5_OutReg12n;
---
-FrmClkDat <= IntFrmClkDat;
------------------------------------------------------------------------------------------------
--- FRAME PATTERN COMPARATOR 
------------------------------------------------------------------------------------------------
-IntFrmCmp(2 downto 0) <= "101" when (IntFrmSrdsDat = IntPatternA) else	-- Equ, 	, Msb
-						 "100" when (IntFrmSrdsDat = IntPatternB) else	-- Equ, 	, Lsb
-						 "111" when (IntFrmSrdsDat = IntPatternC) else	-- Equ, swpd, Msb
-						 "110" when (IntFrmSrdsDat = IntPatternD) else	-- Equ, Swpd, Lsb
-						 "000";
-IntFrmCmp(3) <= High when (C_AdcWireInt = 2) else Low; -- Msb = all zero
---
--- When "Equ" goes high, one of the four patterns has been found.
--- The other two signals will reflect (Msb or Lsb, bitswapped or not) what pattern has been
--- found. WHen "Equ" thus goes high, store the status of all signals and make sure it can't
--- be changed.
---
-IntFrmEquGte <= (IntFrmCmp(2) or IntFrmEqu_d) and IntFrmEna;
---
-AdcFrame_I_Fdce_FrmMsbAllZero_d : FDCE
-    generic map (INIT => '0')
-    port map (D => IntFrmCmp(3), CE => IntFrmMsbAllZero_d_Ena, C => FrmClkDiv,
-              CLR => IntFrmReSyncOut, Q => IntFrmMsbAllZero_d);
-AdcFrame_I_Fdce_FrmEqu_d : FDCE
-    generic map (INIT => '0')
-    port map (D => IntFrmEquGte, CE => High, C => FrmClkDiv,
-              CLR => IntFrmReSyncOut, Q => IntFrmEqu_d);
-AdcFrame_I_Fdce_FrmSwapMux_d : FDCE
-    generic map (INIT => '0')
-    port map (D => IntFrmCmp(1), CE => IntFrmSwapMux_d_Ena, C => FrmClkDiv,
-              CLR => IntFrmReSyncOut, Q => IntFrmSwapMux_d);
-AdcFrame_I_Fdce_FrmLsbMsb_d : FDCE
-    generic map (INIT => '0')
-    port map (D => IntFrmCmp(0), CE => IntFrmLsbMsb_d_Ena, C => FrmClkDiv,
-              CLR => IntFrmReSyncOut, Q => IntFrmLsbMsb_d);
---
-IntFrmMsbAllZero_d_Ena <= IntFrmCmp(2) and not IntFrmEqu_d;
-IntFrmSwapMux_d_Ena <= IntFrmCmp(2)and not IntFrmEqu_d;
-IntFrmLsbMsb_d_Ena <= IntFrmCmp(2) and not IntFrmEqu_d;
-FrmClkSwapMux <= IntFrmSwapMux_d;
------------------------------------------------------------------------------------------------
--- OUTPUT REGISTER ENABLER
------------------------------------------------------------------------------------------------
-AdcFrame_EnaSel_PROCESS : process (FrmClkDiv, IntFrmMsbAllZero_d, IntFrmEqu_d)
-subtype IntFrmRegEnaCase is std_logic_vector(4 downto 0);
-begin
-	if (IntFrmMsbAllZero_d = High) then
-		IntFrmRegEna_d <= Low;
-		IntFrmMsbRegEna_d <= High;
-		IntFrmLsbRegEna_d <= High;
-	elsif (FrmClkDiv'event and FrmClkDiv = '1') then
-		case IntFrmRegEnaCase'(IntFrmLsbMsb_d, IntFrmEqu_d, IntFrmRegEna_d,
-									IntFrmMsbRegEna_d, IntFrmLsbRegEna_d) is
-			when "00001" =>	IntFrmRegEna_d <= '0';
-							IntFrmMsbRegEna_d <= '0'; -- A
-							IntFrmLsbRegEna_d <= '1'; --
-			when "01001" =>	IntFrmRegEna_d <= '1';
-							IntFrmMsbRegEna_d <= '0'; -- B
-							IntFrmLsbRegEna_d <= '1'; --
-			when "01101" =>	IntFrmRegEna_d <= '1';
-							IntFrmMsbRegEna_d <= '1'; -- C
-							IntFrmLsbRegEna_d <= '0'; --
-			when "01110" =>	IntFrmRegEna_d <= '1';
-							IntFrmMsbRegEna_d <= '0'; -- D, goto C 
-							IntFrmLsbRegEna_d <= '1'; --
-			--
-			when "11001" =>	IntFrmRegEna_d <= '1';
-							IntFrmMsbRegEna_d <= '1'; -- E
-							IntFrmLsbRegEna_d <= '0'; --
-			when "11110" =>	IntFrmRegEna_d <= '1';
-							IntFrmMsbRegEna_d <= '0'; -- F
-							IntFrmLsbRegEna_d <= '1'; --
-			when "11101" =>	IntFrmRegEna_d <= '1';
-							IntFrmMsbRegEna_d <= '1'; -- G, goto F
-							IntFrmLsbRegEna_d <= '0'; --
-			--
-			when others =>	IntFrmRegEna_d <= '0';
-							IntFrmMsbRegEna_d <= '0';
-							IntFrmLsbRegEna_d <= '1';
-		end case;
-	end if;
-end process;
-FrmClkMsbRegEna <= IntFrmMsbRegEna_d;
-FrmClkLsbRegEna <= IntFrmLsbRegEna_d;
------------------------------------------------------------------------------------------------
--- SAMPLE EVENT COUNTER
--- Take a frame sample every 16 ClkDiv cycles.
------------------------------------------------------------------------------------------------
-AdcFrame_EvntCnt_PROCESS : process (FrmClkDiv, IntFrmReSyncOut)
-begin
-	if (IntFrmReSyncOut = High) then
-		IntFrmEvntCnt <= (others => '0');
-		IntFrmEvntCntTc_d <= Low;
-	elsif (FrmClkDiv'event and FrmClkDiv = '1') then
-		if (IntFrmEquSet_d = Low and IntFrmEna = High) then
-			IntFrmEvntCnt <= IntFrmEvntCnt + "01";
-			IntFrmEvntCntTc_d <= IntFrmEvntCntTc;
-		end if;
-	end if;
-end process;
-IntFrmEvntCntTc <= High when (IntFrmEvntCnt = "1110") else Low;
---IntFrmEvntCntTc <= High when (IntFrmEvntCnt = ((2**IntFrmEvntCnt'length)-2)) else Low;
------------------------------------------------------------------------------------------------
--- BITSLIP EVENT COUNTER
--- Bitslip 8 times for a 8-bit ISERDES and 6 times for a 6-bit ISERDES.
------------------------------------------------------------------------------------------------
-AdcFrame_SlipCnt_PROCESS : process (FrmClkDiv, IntFrmReSyncOut)
-begin
-	if (IntFrmReSyncOut = High) then
-		IntFrmSlipCnt <= (others => '0');
-	elsif (FrmClkDiv'event and FrmClkDiv = '1') then
-		if (IntFrmEvntCntTc_d = High) then
-			IntFrmSlipCnt <= IntFrmSlipCnt + "01";
-		end if;
-		if (IntFrmEvntCntTc_d = High and IntFrmSlipCntTc = High) then
-			IntFrmSlipCntTc_d <= High;
-		else 
-			IntFrmSlipCntTc_d <= Low;
-		end if;
-	end if;
-end process;
---Terminal count points.
-AdcFrame_SlipCntTc_12 : if (FrmBits(C_AdcBits) = 12) generate
-	IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1011") else Low; -- 11 or X'B'
-end generate;
-AdcFrame_SlipCntTc_1_16 : if (FrmBits(C_AdcBits) = 16) generate
-	IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1111") else Low; -- 15 or X'F'
-end generate;
---AdcFrame_SlipCntTc_1_12 : if (C_AdcWireInt = 1 and FrmBits(C_AdcBits) = 12) generate
---	IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1011") else Low; -- 11 or X'B'
---end generate;
---AdcFrame_SlipCntTc_2_12 : if (C_AdcWireInt = 2 and FrmBits(C_AdcBits) = 12) generate
---	IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "0101") else Low; -- 5
---end generate;
---AdcFrame_SlipCntTc_1_16 : if (C_AdcWireInt = 1 and FrmBits(C_AdcBits) = 16) generate
---	IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "1111") else Low; -- 15 or X'F'
---end generate;
---AdcFrame_SlipCntTc_2_16 : if (C_AdcWireInt = 2 and FrmBits(C_AdcBits) = 16) generate
---	IntFrmSlipCntTc <= High when (IntFrmSlipCnt = "0111") else Low; -- 7
---end generate;
-AdcFrame_I_Fdce_SlipCntTc_1 : FDCE
-    generic map (INIT => '0')
-    port map (D => High, CE => IntFrmSlipCntTc_d, C => FrmClkDiv,
-              CLR => IntFrmSlipCntTc_d2, Q => IntFrmSlipCntTc_d1);
-IntFrmSlipCntTc_d2Ena <= IntFrmSlipCntTc_d and IntFrmSlipCntTc_d1;
-AdcFrame_I_Fdce_SlipCntTc_2 : FDCE
-    generic map (INIT => '0')
-    port map (D => IntFrmSlipCntTc_d2Ena, CE => High, C => FrmClkDiv,
-              CLR => IntFrmReSyncOut, Q => IntFrmSlipCntTc_d2);
------------------------------------------------------------------------------------------------
--- WARNING EVENT COUNTER
--- When this counter issues terminal count, sunchronisation was impossible for 8 times.
------------------------------------------------------------------------------------------------
-AdcFrame_WarnCnt_PROCESS : process (FrmClkDiv, FrmClkRst)
-begin
-	if (FrmClkRst = High) then
-		IntFrmWarnCnt <= (others => '0');
-		IntFrmWarnCntTc_d <= Low;
-	elsif (FrmClkDiv'event and FrmClkDiv = '1') then
-		if (IntFrmSlipCntTc_d = High) then
-			IntFrmWarnCnt <= IntFrmWarnCnt + "01";
-			IntFrmWarnCntTc_d <= IntFrmWarnCntTc;
-		end if;
-	end if;
-end process;
-IntFrmWarnCntTc <= High when (IntFrmWarnCnt = "110") else Low;
-FrmClkSyncWarn <= IntFrmWarnCntTc_d;
------------------------------------------------------------------------------------------------
--- Enable, RESYNC or INTERNAL RESET
--- This is the reset logic for the whole design.
--- Whenever one of these signals (IntFrmSlipCntTc_d2, IntFrmDbleNibFnl, FrmClkReSync, FrmClkRst)
--- is high the circuit is pulled int reset (call it a re-sync operation).
--- 
--- The only components not influenced by this are the ISERDES and the Sync Warning Counter.
--- they only act on the extrenal "FrmClkRst" input.
--- 
--- A circuit enable "IntFrmEna" is generated when the inputs "FrmClkDone" and "FrmClkEna" are
--- high and when the "IntFrmReSync" reset is released.
------------------------------------------------------------------------------------------------
-AdcFrame_I_GenPulse_1 : GenPulse
-    port map (
-        Clk		=> FrmClkDiv, -- in
-        Ena		=> High, -- in
-        SigIn	=> FrmClkReSync, -- in
-        SigOut	=> IntFrmClkReSync -- out
-    );
-IntFrmReSyncOut <= IntFrmSlipCntTc_d2 or IntFrmDbleNibFnl or IntFrmClkReSync or FrmClkRst;
-FrmClkReSyncOut <= IntFrmReSyncOut;
---
-AdcFrame_I_Fdce_Done : FDCE
-    generic map (INIT => '0') -- bit
-    port map(D => FrmClkDone, CE => FrmClkEna, C => FrmClkDiv, CLR => IntFrmReSyncOut,
-             Q => IntFrmEna);
------------------------------------------------------------------------------------------------
--- BITSLIP STATE MACHINE.
------------------------------------------------------------------------------------------------
-AdcFrame_Bitslip_PROCESS : process (IntFrmReSyncOut, FrmClkDiv)
-subtype IntFrmBitSlipCase is std_logic_vector(5 downto 0);
-begin
-	if (IntFrmReSyncOut = High) then
-		IntFrmBitSlip <= (others => '0');
-	elsif (FrmClkDiv'event and FrmClkDiv = '1') then
-		if (IntFrmEna = High and IntFrmEquSet_d = Low) then
-			case IntFrmBitSlipCase'(IntFrmEqu_d, IntFrmEvntCntTc_d, IntFrmBitSlip(5),
-									IntFrmBitSlip(4), IntFrmBitSlip(3), IntFrmBitSlip(2)) is
-				when "000000" => IntFrmBitSlip <= "000000"; -- B 
-				when "010000" => IntFrmBitSlip <= "000101"; -- C Slip_p
-				when "000001" => IntFrmBitSlip <= "000100"; -- D
-				when "010001" => IntFrmBitSlip <= "001010"; -- E Slip_n
-				when "000010" => IntFrmBitSlip <= "001000"; -- F
-				when "010010" => IntFrmBitSlip <= "000101"; -- G Slip_p and goto D
-				--
-				when "100000" => IntFrmBitSlip <= "000000"; -- H 
-				when "110000" => IntFrmBitSlip <= "100101"; -- K Slip_p
-				when "101001" => IntFrmBitSlip <= "110000"; -- L EquSet
-				when "101100" => IntFrmBitSlip <= "110000"; -- M Halt
-				--
-				when "100001" => IntFrmBitSlip <= "000100"; -- N
-				when "110001" => IntFrmBitSlip <= "101010"; -- P Slip_n
-				when "101010" => IntFrmBitSlip <= "110000"; -- R EquSet goto M
-				--
-				when "100010" => IntFrmBitSlip <= "001000"; -- S
-				when "110010" => IntFrmBitSlip <= "100101"; -- T Slip_p goto L
-				--
-				when others => IntFrmBitSlip <= "110000";
-			end case;
-		end if;
-	end if;
-end process;
-FrmClkBitSlip_p <= IntFrmBitSlip(0);
-FrmClkBitSlip_n <= IntFrmBitSlip(1);
-IntFrmEquSet_d <= IntFrmBitSlip(4);
-
-
-testword0(7 downto 0) <= IntFrmSrdsOut;
-testOK <= '1' when IntFrmSrdsOut=x"A5" else '0';
-
---
------------------------------------------------------------------------------------------------
-end  AdcFrame_struct;
diff --git a/FEE_ADC32board/modules/ADCrefdesign/AdcToplevel.vhd b/FEE_ADC32board/modules/ADCrefdesign/AdcToplevel.vhd
deleted file mode 100644
index 77959dd..0000000
--- a/FEE_ADC32board/modules/ADCrefdesign/AdcToplevel.vhd
+++ /dev/null
@@ -1,739 +0,0 @@
-----------------------------------------------------------------------------------------------
--- Copyright 2010, Xilinx, Inc. All rights reserved.
--- This file contains confidential and proprietary information of Xilinx, Inc. and is
--- protected under U.S. and international copyright and other intellectual property laws.
------------------------------------------------------------------------------------------------
---
--- Disclaimer:
---		This disclaimer is not a license and does not grant any rights to the materials
---		distributed herewith. Except as otherwise provided in a valid license issued to you
---		by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
---		ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
---		WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
---		TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
---		PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
---		negligence, or under any other theory of liability) for any loss or damage of any
---		kind or nature related to, arising under or in connection with these materials,
---		including for any direct, or any indirect, special, incidental, or consequential
---		loss or damage (including loss of data, profits, goodwill, or any type of loss or
---		damage suffered as a result of any action brought by a third party) even if such
---		damage or loss was reasonably foreseeable or Xilinx had been advised of the
---		possibility of the same.
---
--- CRITICAL APPLICATIONS
---		Xilinx products are not designed or intended to be fail-safe, or for use in any
---		application requiring fail-safe performance, such as life-support or safety devices
---		or systems, Class III medical devices, nuclear facilities, applications related to
---		the deployment of airbags, or any other applications that could lead to death,
---		personal injury, or severe property or environmental damage (individually and
---		collectively, "Critical Applications"). Customer assumes the sole risk and
---		liability of any use of Xilinx products in Critical Applications, subject only to
---		applicable laws and regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 
---
---		Contact:    e-mail  hotline@xilinx.com        phone   + 1 800 255 7778
---   ____  ____
---  /   /\/   /
--- /___/  \  / 			Vendor:              Xilinx Inc.
--- \   \   \/ 			Version:              
---  \   \        		
---  /   /        		Filename:            AdcToplevel.vhd
--- /___/   /\    		Date Created:        Nov 07
--- \   \  /  \          Date Last Modified:  7 Mar 2011
---  \___\/\___\
--- 
--- Device:          Virtex-6
--- Author:          defossez
--- Entity Name:     AdcToplevel
--- Purpose:         Top level for an interface between a Virtex-6 FPGA and ADS6245 
--- Tools:           ISE_13.1 
--- Limitations:     none
---
--- Revision History:
---	Rev. 20 Oct 09
---      Made the ADC interface more generic, with speate FPGA IO file and etcetera.
---  Rev. 27 Dec 10
---      Retrived the file after accidental delete.
---  Rev. 7 Mar 11
---      - Adjustment of the range, in the entity declaration, of "AdcMemFlags" when
---        used for 1 and 2 wire interface.
---      - Brought the generic C_FrmPattern to the top level entity declaration. Now it is 
---        possible to provide the frame pattern to search for when the AdcToplevel component
---        is instantiated.
---      - Added extensive comments for teh top level entity generics and ports.
------------------------------------------------------------------------------------------------
--- Naming Conventions:
---   active low signals:                    "*_n"
---   clock signals:                         "clk", "clk_div#", "clk_#x"
---   reset signals:                         "rst", "rst_n"
---   generics:                              "C_*"
---   user defined types:                    "*_TYPE"
---   state machine next state:              "*_ns"
---   state machine current state:           "*_cs"
---   combinatorial signals:                 "*_com"
---   pipelined or register delay signals:   "*_d#"
---   counter signals:                       "*cnt*"
---   clock enable signals:                  "*_ce"
---   internal version of output port:       "*_i"
---   device pins:                           "*_pin"
---   ports:                                 "- Names begin with Uppercase"
---   processes:                             "*_PROCESS"
---   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------------------------
---
-library IEEE;
-	use IEEE.std_logic_1164.all;
-	use IEEE.std_logic_UNSIGNED.all;
-	use IEEE.std_logic_textio.all;
-	use std.textio.all;
-library UNISIM;
-	use UNISIM.VCOMPONENTS.all;
------------------------------------------------------------------------------------------------
--- Entity pin description
------------------------------------------------------------------------------------------------
---      GENERICS
--- C_AdcChnls           -- ADC Channels available in a package.
--- C_AdcBits            -- Value can be 12, 14, or 16 (14 is means 14-bit burried in 16-bit)
--- C_AdcWireInt         -- 0 = 1-wire, 1 = 2-wire
--- C_FrmPattern         -- Pattern to lock the frame to.
---
--- A 14 or 16 bit ADC in 2-wire mode has a 8-bit frame pattern. The C_FrmPattern parameter
--- must be set to:  C_FrmPattern ==> "0000000011110000".
--- A 14 or 16 bit ADC in 1-wire mode has a 16-bit frame pattern. The C_FrmPattern parameter
--- must be set to:  C_FrmPattern ==> "1111111100000000".
--- The same applies for a 12-bit ADC device.
---      C_FrmPattern        : string    := "111111000000";      -- 1-wire, 12 bit.
---      C_FrmPattern        : string    := "000000111000";      -- 2-wire, 12 bit.
---
--- C_StatTaps           -- Number of taps the IDELAY starts from (Middle of the Tap chain).
--- C_IdelayCtrlLoc      -- Hard location of the IDELAYCTRL component.
---      PORTS
--- DATA_n           -- I -- ADC data input signals from the ADC device.
--- DATA_p           -- I -- 
--- DCLK_n, DCLK_p   -- I -- High speed clock from the ADC device.
--- FCLK_n, FCLK_p   -- I -- Word or frame clock from the ADC device.
--- SysRefClk        -- I -- Reference clock for IDELAYCTRL (200 MHz).
--- AdcIntrfcRst     -- I -- Reset for the interface from the application.
--- AdcIntrfcEna     -- I -- Enable signal for the interface from the application.
--- AdcReSync        -- I -- Signal to restart the resync process.
--- AdcFrmSyncWrn    -- O -- Warning from the sync logic, alignment is not possible
--- AdcBitClkAlgnWrn -- O -- Status signal. BitClock adjusted.
--- AdcBitClkInvrtd  -- O -- Bit clock state, rising or falling
--- AdcBitClkDone    -- O -- Bit clock alignment done
--- AdcIdlyCtrlRdy   -- O -- IDELAYCTRL ready
-
------------------------------------------------------------------------------------------------
-entity AdcToplevel is
-	generic (
-		C_AdcChnls          : integer := 4;     -- Number of ADC in a package 
-		C_AdcWireInt        : integer := 2;     -- 2 = 2-wire, 1 = 1-wire interface
-		C_BufioLoc          : string  := "BUFIODQS_X0Y12";
-		C_BufrLoc           : string  := "BUFR_X0Y6";
-		C_AdcBits           : integer := 16;
-		C_StatTaps          : integer := 16;
-		C_AdcUseIdlyCtrl    : integer := 1;	     -- 0 = No, 1 = Yes
-		C_AdcIdlyCtrlLoc    : string  := "IDELAYCTRL_X0Y3";
-		C_FrmPattern        : string  := "0000000011110000"  -- Read above text!
-	);
-    port (
-		DCLK_p	           : in std_logic;
-		DCLK_n	           : in std_logic;  -- Not used.
-		FCLK_p	           : in std_logic;
-		FCLK_n	           : in std_logic;
-		DATA_p	           : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
-		DATA_n	           : in std_logic_vector((C_AdcChnls*C_AdcWireInt)-1 downto 0);
-		-- application connections
-		SysRefClk           : in std_logic;		-- 200 MHz for IODELAYCTRL from application
-		AdcIntrfcRst        : in std_logic;
-		AdcIntrfcEna        : in std_logic;
-		AdcReSync           : in std_logic;
-		AdcFrmSyncWrn       : out std_logic;
-		AdcBitClkAlgnWrn    : out std_logic;
-		AdcBitClkInvrtd     : out std_logic;
-		AdcBitClkDone       : out std_logic;
-		AdcIdlyCtrlRdy      : out std_logic;
-
-		AdcClkDiv           : out std_logic;
-		AdcDataClk          : in std_logic;	
-		AdcDataClkNot       : in std_logic;	
-		AdcDataOut 			  : out std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
-		ADCs_ready          : out std_logic;
-		testOK              : out std_logic;
-		testword0 			  : out std_logic_vector(35 downto 0)
-    );
-end AdcToplevel;
------------------------------------------------------------------------------------------------
--- Arcitecture section
------------------------------------------------------------------------------------------------
-architecture AdcToplevel_struct of AdcToplevel  is
------------------------------------------------------------------------------------------------
--- Component Instantiation
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
--- Constants, Signals and Attributes Declarations
------------------------------------------------------------------------------------------------
--- Functions
-function int_to_chr(int: integer) return character is
-    variable temp : character;
-begin
-	case int is
-		when  0 => temp := '0';
-		when  1 => temp := '1';
-		when  2 => temp := '2';
-		when  3 => temp := '3';
-		when  4 => temp := '4';
-		when  5 => temp := '5';
-		when  6 => temp := '6';
-		when  7 => temp := '7';
-		when  8 => temp := '8';
-		when  9 => temp := '9';
-		when 10 => temp := 'A';
-		when 11 => temp := 'B';
-		when 12 => temp := 'C';
-		when 13 => temp := 'D';
-		when 14 => temp := 'E';
-		when 15 => temp := 'F';
-		when 16 => temp := 'G';
-		when 17 => temp := 'H';
-		when 18 => temp := 'I';
-		when 19 => temp := 'J';
-		when 20 => temp := 'K';
-		when 21 => temp := 'L';
-		when 22 => temp := 'M';
-		when 23 => temp := 'N';
-		when 24 => temp := 'O';
-		when 25 => temp := 'P';
-		when 26 => temp := 'Q';
-		when 27 => temp := 'R';
-		when 28 => temp := 'S';
-		when 29 => temp := 'T';
-		when 30 => temp := 'U';
-		when 31 => temp := 'V';
-		when 32 => temp := 'W';
-		when 33 => temp := 'X';
-		when 34 => temp := 'Y';
-		when 35 => temp := 'Z';
-		when others => temp := '?';
-	end case;
-return temp;
-end function int_to_chr;
---
-function int_to_str(int: integer; base: integer) return string is
-    variable temp:      string(1 to 10);
-    variable num:       integer;
-    variable abs_int:   integer;
-    variable len:       integer := 1;
-    variable power:     integer := 1;
-begin
-    abs_int := abs(int);	-- Negative numbers
-    num     := abs_int;
-    
-    while num >= base loop                     -- Determine how many
-      len := len + 1;                          -- characters required
-      num := num / base;                       -- to represent the
-    end loop ;                                 -- number.
-
-    for i in len downto 1 loop        			        -- Convert the number to
-      temp(i) := int_to_chr(abs_int/power mod base);	-- a string starting
-      power := power * base;                   			-- with the right hand
-    end loop ;                                	 		-- side.
-
-    -- return result and add sign if required
-    if int < 0 then
-       return '-'& temp(1 to len);
-     else
-       return temp(1 to len);
-    end if;
-end function int_to_str;
--- In two wire mode a 12 bit ADC has 2 channels of 6 bits. The AdcBits stay at 12.
--- In two wire mode a 14 bit ADC has 2 channels of 8 bits. The AdcBits is set at 16.
--- In two wire mode a 16 bit ADC has 2 channels of 8 bits. The AdcBits stay at 16.
-function AdcBits (Bits : integer) return integer is
-variable Temp : integer;
-begin
-	if (Bits = 12) then
-		Temp := 12;
-	elsif (Bits = 14) then
-		Temp := 16;
-	elsif (Bits = 16) then
-		Temp := 16;
-	end if;
-return Temp;
-end function AdcBits;
-
-component AdcClock is
-	generic (
-	   C_BufioLoc  : string := C_BufioLoc;
-	   C_BufrLoc   : string := C_BufrLoc;
-	   C_AdcBits   : integer := C_AdcBits;
-	   C_StatTaps  : integer := C_StatTaps
-	);
-    port (
-        BitClk				: in std_logic;
-        BitClkRst			: in std_logic;
-        BitClkEna			: in std_logic;
-        BitClkReSync		: in std_logic;
-		  BitClkDivReset	: in std_logic;
-        BitClk_MonClkOut	: out std_logic;   -- CLK output
-        BitClk_MonClkIn		: in std_logic;    -- ISERDES.CLK input
-        BitClk_RefClkOut	: out std_logic;   -- CLKDIV & logic output
-        BitClk_RefClkIn		: in std_logic;    -- CLKDIV & logic input
-        BitClkAlignWarn 	: out std_logic;
-		BitClkInvrtd		: out std_logic;
-        BitClkDone 			: out std_logic
-    );
-end component;
-
-component AdcFrame is
-	generic (
-		C_AdcBits			: integer;
-		C_AdcWireInt		: integer;
-		C_FrmPattern		: string
-	);
-    port (
-        FrmClk_n		: in std_logic;		-- input n from IBUFDS_DIFF_OUT
-        FrmClk_p		: in std_logic;		-- input p from IBUFDS_DIFF_OUT
-        FrmClkRst		: in std_logic;
-        FrmClkEna		: in std_logic;
-        FrmClk			: in std_logic;
-        FrmClkDiv		: in std_logic;
-        FrmClkDone		: in std_logic;		-- Input from clock syncronisation.
-        FrmClkReSync	: in std_logic;
-        FrmClkBitSlip_p	: out std_logic;
-        FrmClkBitSlip_n	: out std_logic;
-        FrmClkSwapMux	: out std_logic;
-        FrmClkMsbRegEna	: out std_logic;
-        FrmClkLsbRegEna	: out std_logic;
-        FrmClkReSyncOut	: out std_logic;
-		FrmClkDat		: out std_logic_vector(15 downto 0);
-        FrmClkSyncWarn	: out std_logic;
-		  Frame_out : out std_logic;
-		  testOK : out std_logic;
-			testword0 			  : out std_logic_vector(35 downto 0)
-    );
-end component;
-
-component AdcData is
-	generic (
-		C_AdcBits			: integer := C_AdcBits;	-- Can be 12, 14 or 16
-		C_AdcBytOrBitMode	: integer := 1;     -- 1 = BIT mode, 0 = BYTE mode,
-		C_AdcMsbOrLsbFst	: integer := 0;     -- 0 = MSB first, 1 = LSB first
-		C_AdcWireInt		: integer := C_AdcWireInt		-- 1 = 1-wire, 2 = 2-wire.
-	);
-    port (
-        DatD0_n			: in std_logic;
-		DatD0_p			: in std_logic;
-		DatD1_n			: in std_logic;
-		DatD1_p			: in std_logic;
-		DatClk			: in std_logic;
-		DatClkDiv		: in std_logic;
-		DatRst			: in std_logic;
-		DatEna			: in std_logic;
-		DatDone			: in std_logic;
-		DatBitSlip_p	: in std_logic;
-        DatBitSlip_n	: in std_logic;
-        DatSwapMux		: in std_logic;
-        DatMsbRegEna	: in std_logic;
-        DatLsbRegEna	: in std_logic;
-        DatReSync		: in std_logic;
-		DatOut			: out std_logic_vector(31 downto 0)
-    );
-end component;
-
-attribute keep					: string;
-
--- Constants
-constant Low : std_logic := '0';
-constant High : std_logic := '1';
--- Signals
-signal IntIdlyCtrlRdy		: std_logic := '0';
-signal IntRst0				: std_logic := '0';
-signal IntRst				: std_logic := '0';
-signal IntEna_d				: std_logic := '0';
-signal IntEna				: std_logic := '0';
---
-signal IntBitClkDone		: std_logic := '0';
-signal IntClk				: std_logic := '0';
-signal IntClkDiv			: std_logic := '0';
-attribute keep	of IntClkDiv				: signal is "TRUE";
-signal IntClkBitSlip_p		: std_logic := '0';
-signal IntClkBitSlip_n		: std_logic := '0';
-signal IntClkSwapMux		: std_logic := '0';
-signal IntClkMsbRegEna		: std_logic := '0';
-signal IntClkLsbRegEna		: std_logic := '0';
-signal IntFrmClkReSyncOut	: std_logic := '0';
-signal IntDataOut 			: std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0) := (others => '0');
-signal IntDataOut_S  		: std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0) := (others => '0');
--- Attributes
-attribute LOC : string;
------------------------------------------------------------------------------------------------
---
-signal AdcBitClkAlgnWrn_S		: std_logic := '0';
-signal AdcBitClkInvrtd_S		: std_logic := '0';
-signal adcfrmsyncwrn_S		: std_logic := '0';
-signal AdcIdlyCtrlRdy_S		: std_logic := '0';
-signal testOK_S		: std_logic := '0';
-signal testword0_S 			: std_logic_vector(35 downto 0) := (others => '0');
-signal AdcReSync_S		: std_logic := '0';
-signal slipoccurred_S : std_logic := '0';
-signal slipsoccurred_S : std_logic := '0';
-signal slipcounter_S : integer range 0 to 255 := 0;
-signal IntBitClkDone_S : std_logic := '0';
-signal ClockResync_S : std_logic := '0';
-signal ClockResync0_S : std_logic := '0';
-
-signal IntEna_S : std_logic := '0';
-signal IntRst_S : std_logic := '0';
-signal frame_S : std_logic := '0';
-signal reset_clockdiv_S : std_logic := '0';
-
-signal AdcData_negedge : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
-signal AdcDataOut_S : std_logic_vector((32*((C_AdcChnls/2)*C_AdcWireInt))-1 downto 0);
-
-
--- Attributes
-attribute keep of reset_clockdiv_S    : signal is "TRUE";
-
-begin
-
-AdcClkDiv <= IntClkDiv;
---AdcDataOut <= IntDataOut;
-
---process(IntClkDiv)
---begin
---	if falling_edge(IntClkDiv) then 
---		AdcData_negedge <= IntDataOut;
---	end if;
---end process;
-
-process(IntClkDiv)
-begin
-	if rising_edge(IntClkDiv) then 
-		IntDataOut_S <= IntDataOut;
-	end if;
-end process;
-
-process(AdcDataClkNot)
-begin
-	if rising_edge(AdcDataClkNot) then 
-		AdcData_negedge <= IntDataOut_S;
-	end if;
-end process;
-
-process(AdcDataClk)
-begin
-	if rising_edge(AdcDataClk) then 
-		AdcDataOut <= AdcDataOut_S;
-		AdcDataOut_S <= AdcData_negedge;
-	end if;
-end process;
-
-
------------------------------------------------------------------------------------------------
--- IDELAYCTRL
--- An IDELAYCTRL component must be used per IO-bank. Normally a ADC port fits a whole
--- IO-Bank. The number of IDELAYCTRL components should thus fit with the number of ADC port.
--- In case of this test design, two ADC ports fit into one IO-Bank, thus only one IDLEAYCTRL
--- component is needed.
--- Don not forget to hook the outputs of the IDELAYCTRL components correctly to the reset and
--- enable for each ADC block.
--- Don not forget to LOC the IDELAYCTRL components down.
------------------------------------------------------------------------------------------------
-Gen_0 : if C_AdcUseIdlyCtrl = 0 generate
-	AdcIdlyCtrlRdy_S <= High;
-end generate Gen_0;
-Gen_1 : if C_AdcUseIdlyCtrl = 1 generate
-attribute LOC of AdcToplevel_I_IdlyCtrl_0 : label is C_AdcIdlyCtrlLoc;
-begin
-	AdcToplevel_I_IdlyCtrl_0 : IDELAYCTRL
-		port map (REFCLK => SysRefClk, RST => reset_clockdiv_S , RDY => AdcIdlyCtrlRdy_S);--peter AdcIntrfcRst
-end generate Gen_1;
-AdcIdlyCtrlRdy <= AdcIdlyCtrlRdy_S;
--- IntRst and IntEna are the reset and enable signals to be used in the interafce.
--- they are generated from the incomming system enable and reset.
-
-AdcToplevel_I_Fdpe_Rst : FDPE
-	generic map (INIT => '1')
-	port map (C => IntClkDiv, CE => High, PRE => reset_clockdiv_S, D => Low, Q => IntRst);--peter AdcIntrfcRst
-
-	
-
-AdcToplevel_I_Fdce_Ena_0 : FDCE
-	generic map (INIT => '0')
-	port map (C => IntClkDiv, CE => AdcIntrfcEna, CLR => IntRst, D => High, Q => IntEna_d);
-AdcToplevel_I_Fdce_Ena_1 : FDCE
-	generic map (INIT => '0')
-	port map (C => IntClkDiv, CE => High, CLR => IntRst, D => IntEna_d, Q => IntEna);
------------------------------------------------------------------------------------------------
--- C_AdcChnls		= c
--- C_AdcWireInt		= w
--- C_AdcBits		= b
------------------------------------------------------------------------------------------------
--- BIT CLOCK
--- IntClk and IntClkDiv are the clock to be used in the interface.
------------------------------------------------------------------------------------------------
--- There is no IBUFGDS used on this level of the design.
--- The IBUFGDS can be found in the AdcIo level.
--- That is this the reason why the DCLK_n is not used here.
--- At the AdcIo level the DCLK_n output is connected to GND.
-AdcToplevel_I_AdcClock : AdcClock -- entity AdcClock.AdcClock
-generic map (
-        C_BufioLoc      => C_BufioLoc,      -- string  
-        C_BufrLoc       => C_BufrLoc,       -- string
-        C_AdcBits       => C_AdcBits,       -- integer
-        C_StatTaps      => C_StatTaps       -- integer
-    )
-port map (
-	BitClk				=> DCLK_p,			-- in
-	BitClkRst			=> IntRst,			-- in
-	BitClkEna			=> '1', -- IntEna_S,			-- in
-	BitClkReSync		=> ClockResync_S,  -- AdcReSync_S,		-- in
-	BitClkDivReset		=> reset_clockdiv_S,
-	BitClk_MonClkOut	=> IntClk,			-- out	-->--|---->----
-	BitClk_MonClkIn		=> IntClk,			-- in	--<--|
-	BitClk_RefClkOut	=> IntClkDiv,		-- out	-->----|-->----
-	BitClk_RefClkIn		=> IntClkDiv,		-- in	--<----|
-	BitClkAlignWarn 	=> AdcBitClkAlgnWrn_S,-- out
-	BitClkInvrtd		=> AdcBitClkInvrtd_S,	-- out
-	BitClkDone 			=> IntBitClkDone	-- out Enables the AdcFrame block.
-);
-AdcBitClkDone <= IntBitClkDone; -- IntBitClkDone_S;
-AdcBitClkInvrtd <= AdcBitClkInvrtd_S; 
-AdcBitClkAlgnWrn <= AdcBitClkAlgnWrn_S;
------------------------------------------------------------------------------------------------
--- WORD / FRAME CLOCK
------------------------------------------------------------------------------------------------
-AdcToplevel_I_AdcFrame : AdcFrame -- entity AdcFrame_Lib.AdcFrame
-generic map (
-	C_AdcBits			=> C_AdcBits,		-- integer;
-	C_AdcWireInt		=> C_AdcWireInt,	-- integer;
-	C_FrmPattern		=> C_FrmPattern  	-- string -- 1 or 2-wire, 12 or 16(14)-bit
-)
-port map (
-	FrmClk_n		=> FCLK_n,			-- in input n from IBUFDS_DIFF_OUT
-	FrmClk_p		=> FCLK_p,			-- in input p from IBUFDS_DIFF_OUT
-	FrmClkRst		=> IntRst_S,			-- in
-	FrmClkEna		=> IntEna_S,			-- in
-	FrmClk			=> IntClk,			-- in
-	FrmClkDiv		=> IntClkDiv,		-- in
-	FrmClkDone		=> IntBitClkDone, -- IntBitClkDone_S,	-- in From AdcClock done.
-	FrmClkReSync	=> AdcReSync_S,		-- in
-	FrmClkBitSlip_p	=> IntClkBitSlip_p,	-- out
-	FrmClkBitSlip_n	=> IntClkBitSlip_n,	-- out
-	FrmClkSwapMux	=> IntClkSwapMux,	-- out
-	FrmClkMsbRegEna	=> IntClkMsbRegEna,	-- out
-	FrmClkLsbRegEna	=> IntClkLsbRegEna,	-- out
-	FrmClkReSyncOut	=> IntFrmClkReSyncOut,	-- out
-	FrmClkDat		=> open,		-- out
-	FrmClkSyncWarn	=> AdcFrmSyncWrn_S,		-- out
-	Frame_out => frame_S,
-	testOK => testOK_S,
-	testword0 => testword0_S
-);
-adcfrmsyncwrn <= adcfrmsyncwrn_S;
-testOK <= testOK_S;
------------------------------------------------------------------------------------------------
--- DATA INPUTS
--- Default the interface is set in BYTE and MSB first mode.
--- This is coded in the AdcData level and can be mnodified if wanted.
--- Enable the generics and all selection possibilities are available.  
------------------------------------------------------------------------------------------------
-Gen_2 : for cw in ((C_AdcChnls/2)*C_AdcWireInt)-1 downto 0 generate
---	assert false
---	report int_to_str((32*((cw+1)+(p*C_AdcChnls))),10)
---	severity note;
-	AdcToplevel_I_AdcData : AdcData -- entity AdcData.AdcData
-	generic map (
-		C_AdcBits		=> C_AdcBits,		-- Can be 12, 14 or 16
-		C_AdcWireInt	=> C_AdcWireInt		-- 1 = 1-wire, 2 = 2-wire.
-	)
-	port map (
-		DatD0_n			=> DATA_n(cw*2),		-- in 
-		DatD0_p			=> DATA_p(cw*2),		-- in 
-		DatD1_n			=> DATA_n((cw*2)+1),	-- in 
-		DatD1_p			=> DATA_p((cw*2)+1),	-- in 
-		DatClk			=> IntClk,				-- in 
-		DatClkDiv		=> IntClkDiv,			-- in 
-		DatRst			=> IntRst_S,				-- in 
-		DatEna			=> IntEna_S,				-- in 
-		DatDone			=> IntBitClkDone, -- IntBitClkDone_S,		-- in 
-		DatBitSlip_p	=> IntClkBitSlip_p,		-- in 
-		DatBitSlip_n	=> IntClkBitSlip_n,		-- in 
-		DatSwapMux		=> IntClkSwapMux,		-- in 
-		DatMsbRegEna	=> IntClkMsbRegEna,		-- in 
-		DatLsbRegEna	=> IntClkLsbRegEna,		-- in 
-		DatReSync		=> IntFrmClkReSyncOut,	-- in
-		DatOut			=> IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-32)
-	);
-	
-	
---AdcDataOut((32*(cw+1))-1 downto (32*(cw+1))-(32/C_AdcWireInt)) <= IntDataOut((32*(cw+1))-1 downto (32*(cw+1))-(32/C_AdcWireInt));
-
-
-
-end generate Gen_2;
-
-	
-process(IntClkDiv)
-begin
-	if (rising_edge(IntClkDiv)) then 
-		AdcReSync_S <= AdcReSync;
-	end if;
-end process;
-
--- reset_clockdiv_S <= '1' when (frame_S='0') and (reset_clockdiv0_S='1') else '0';
-reset_clockdiv : FDPE
-	generic map (INIT => '1')
-	port map (C => frame_S, CE => High, PRE => AdcIntrfcRst, D => Low, Q => reset_clockdiv_S);
-
---process(SysRefClk)
---begin
---	if (rising_edge(SysRefClk)) then 
---		if (AdcIntrfcRst='1') then -- or (ClockResync0_S='1') then
---			reset_clockdiv0_S <= '1';
---		elsif frame_S='1' then
---			reset_clockdiv0_S <= '0';
---		end if;
---	end if;
---end process;
-
---process(IntClkDiv,reset_clockdiv0_S)
---variable counter_V : integer range 0 to 3 := 0;
---begin
---	if reset_clockdiv0_S='1' then
---		ClockResync_S <= '0';
---		counter_V := 0;
---	elsif (rising_edge(IntClkDiv)) then
---		if counter_V<3 then
---			counter_V := counter_V+1;
---			ClockResync_S <= '1';
---		else
---			ClockResync_S <= '0';
---		end if;
---	end if;
---end process;
-ClockResync_S <= ClockResync0_S;
-process(IntClkDiv,AdcIntrfcRst) -- reset_clockdiv_S)
-begin
---	if reset_clockdiv_S='1' then
-	if AdcIntrfcRst='1' then
-		slipoccurred_S <= '0';
-		slipsoccurred_S <= '0';
-		slipcounter_S <= 0;
-		ClockResync0_S <= '0';
-		IntBitClkDone_S <= '0';
-		IntEna_S <= '0';
-		IntRst_S <= '0';
-		ADCs_ready <= '0';
-	elsif (rising_edge(IntClkDiv)) then
-		if (IntBitClkDone='0') or (ClockResync_S='1') then
-			slipcounter_S <= 0;
-			slipoccurred_S <= '0';
-			slipsoccurred_S <= '0';
-			ClockResync0_S <= '0';
-			IntBitClkDone_S <= '0';
-			IntEna_S <= '0';
-			IntRst_S <= '0';
-			ADCs_ready <= '0';
-		elsif slipcounter_S<2 then
-			slipcounter_S <= slipcounter_S+1;
-			ClockResync0_S <= '0';
-			slipoccurred_S <= '0';
-			slipsoccurred_S <= '0';
-			IntBitClkDone_S <= '0';
-			IntEna_S <= '0';
-			IntRst_S <= '0';
-		elsif slipcounter_S<31 then
-			slipcounter_S <= slipcounter_S+1;
-			ClockResync0_S <= '0';
-			slipoccurred_S <= '0';
-			slipsoccurred_S <= '0';
-			IntBitClkDone_S <= '0';
-			IntEna_S <= '0';
-			IntRst_S <= '0';
-		elsif slipcounter_S<33 then
-			slipcounter_S <= slipcounter_S+1;
-			IntRst_S <= '1';
-		elsif slipcounter_S<63 then
-			slipcounter_S <= slipcounter_S+1;
-			IntRst_S <= '0';
-		elsif slipcounter_S<95 then
-			slipcounter_S <= slipcounter_S+1;
-			IntEna_S <= '1';
-		elsif slipcounter_S<111 then
-			slipcounter_S <= slipcounter_S+1;
-			IntBitClkDone_S <= '1';
-		elsif slipcounter_S<254 then
-			slipcounter_S <= slipcounter_S+1;
-			IntBitClkDone_S <= '1';
-			if (IntClkBitSlip_p='1') then
-				if slipoccurred_S='1' then 
-					slipsoccurred_S <= '1';
-				end if;
-				slipoccurred_S <= '1';
-			end if;
-			if (IntClkBitSlip_n='1') then
-				slipsoccurred_S <= '1';
-				slipoccurred_S <= '1';
-			end if;
-		elsif slipcounter_S<255 then
-			slipcounter_S <= slipcounter_S+1;
---			if (slipsoccurred_S='1') or (testOK_S='0') or (IntClkSwapMux='1') or (AdcBitClkInvrtd_S='0') or (AdcBitClkAlgnWrn_S='1') then
-			if (slipsoccurred_S='1') or (IntClkSwapMux='1') or (AdcBitClkAlgnWrn_S='1') then
---			if (testOK_S='0') or (IntClkSwapMux='1') or (AdcBitClkAlgnWrn_S='1') then
-				ClockResync0_S <= '1';
-			else
-				ADCs_ready <= '1';
-			end if;
-		else
-			ClockResync0_S <= '0';
-		end if;
-	end if;
-end process;
-
-
-
-
------------------------------------------------------------------------------------------------
---
-
---1000
-testword0(0) <= IntRst;
-testword0(1) <= AdcReSync_S;
-testword0(2) <= AdcBitClkAlgnWrn_S;
-testword0(3) <= AdcBitClkInvrtd_S;
-
---0001
-testword0(4) <= IntBitClkDone;
-testword0(5) <= IntClkBitSlip_p;
-testword0(6) <= IntClkBitSlip_n;
-testword0(7) <= IntClkSwapMux;
-
---0011
-testword0(8) <= IntRst_S; -- IntClkMsbRegEna;
-testword0(9) <= IntEna_S; -- IntClkLsbRegEna;
-testword0(10) <= IntFrmClkReSyncOut;
-testword0(11) <= AdcFrmSyncWrn_S;
-
---1000
-testword0(12) <= AdcIntrfcRst;
-testword0(13) <= testOK_S;
-testword0(14) <= Frame_S;
-testword0(15) <= AdcIdlyCtrlRdy_S;
-
-testword0(16) <= AdcReSync_S;
-testword0(17) <= slipoccurred_S;
-testword0(18) <= slipsoccurred_S;
-testword0(19) <= IntBitClkDone_S;
-testword0(20) <= ClockResync_S;
-testword0(21) <= ClockResync0_S;
-testword0(22) <= reset_clockdiv_S;
-testword0(23) <= reset_clockdiv_S;
-
-
--- testword0(23 downto 16) <= testword0_S(7 downto 0);
-		
-testword0(35 downto 24) <= (others => '0');
-
-end AdcToplevel_struct;
\ No newline at end of file
diff --git a/FEE_ADC32board/modules/ADCrefdesign/DoubleNibbleDetect.vhd b/FEE_ADC32board/modules/ADCrefdesign/DoubleNibbleDetect.vhd
deleted file mode 100644
index 0152478..0000000
--- a/FEE_ADC32board/modules/ADCrefdesign/DoubleNibbleDetect.vhd
+++ /dev/null
@@ -1,293 +0,0 @@
----------------------------------------------------------------------------------------------
--- © Copyright 2011, Xilinx, Inc. All rights reserved.
--- This file contains confidential and proprietary information of Xilinx, Inc. and is
--- protected under U.S. and international copyright and other intellectual property laws.
----------------------------------------------------------------------------------------------
---
--- Disclaimer:
---		This disclaimer is not a license and does not grant any rights to the materials
---		distributed herewith. Except as otherwise provided in a valid license issued to you
---		by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
---		ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
---		WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
---		TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
---		PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
---		negligence, or under any other theory of liability) for any loss or damage of any
---		kind or nature related to, arising under or in connection with these materials,
---		including for any direct, or any indirect, special, incidental, or consequential
---		loss or damage (including loss of data, profits, goodwill, or any type of loss or
---		damage suffered as a result of any action brought by a third party) even if such
---		damage or loss was reasonably foreseeable or Xilinx had been advised of the
---		possibility of the same.
---
--- CRITICAL APPLICATIONS
---		Xilinx products are not designed or intended to be fail-safe, or for use in any
---		application requiring fail-safe performance, such as life-support or safety devices
---		or systems, Class III medical devices, nuclear facilities, applications related to
---		the deployment of airbags, or any other applications that could lead to death,
---		personal injury, or severe property or environmental damage (individually and
---		collectively, "Critical Applications"). Customer assumes the sole risk and
---		liability of any use of Xilinx products in Critical Applications, subject only to
---		applicable laws and regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
---
---		Contact:    e-mail  hotline@xilinx.com        phone   + 1 800 255 7778
---   ____  ____
---  /   /\/   /
--- /___/  \  / 			Vendor:              Xilinx Inc.
--- \   \   \/ 			Version:
---  \   \        		Filename:            DoubleNibbleDetect.vhd
---  /   /        		Date Created:        16 March, 2011
--- /___/   /\    		Date Last Modified:  16 March, 2011
--- \   \  /  \
---  \___\/\___\
---
--- Device:          Virtex-6
--- Author:          defossez
--- Entity Name:     DoubleNibbleDetect
--- Purpose:         Create a on-off signal that already reacts at the combinatorial input.
--- Tools:           ISE_13.1
--- Limitations:     none
---
--- Revision History:
---	Rev.
---
-------------------------------------------------------------------------------
--- Naming Conventions:
---   active low signals:                    "*_n"
---   clock signals:                         "clk", "clk_div#", "clk_#x"
---   reset signals:                         "rst", "rst_n"
---   generics:                              "C_*"
---   user defined types:                    "*_TYPE"
---   state machine next state:              "*_ns"
---   state machine current state:           "*_cs"
---   combinatorial signals:                 "*_com"
---   pipelined or register delay signals:   "*_d#"
---   counter signals:                       "*cnt*"
---   clock enable signals:                  "*_ce"
---   internal version of output port:       "*_i"
---   device pins:                           "*_pin"
---   ports:                                 "- Names begin with Uppercase"
---   processes:                             "*_PROCESS"
---   component instantiations:              "<ENTITY_>I_<#|FUNC>"
----------------------------------------------------------------------------------------------
-library IEEE;
-	use IEEE.std_logic_1164.all;
-	use IEEE.std_logic_UNSIGNED.all;
-library UNISIM;
-	use UNISIM.vcomponents.all;
----------------------------------------------------------------------------------------------
--- Entity pin description
----------------------------------------------------------------------------------------------
--- Clock    : Clock for the design.
--- RstIn    : Reset input. Resets the necessary logic at startup.
--- Final    : This circuit checks a nibble (4-bit) for appearing twice, when for rotations or
---            slips are made, teh fifth ossurence resets the circuit. this is signalled ouside
---            so that a upper layer of design can take action. 
--- DataIn   : Nibble input.
--- DataOut  : Corrected nibble output.
----------------------------------------------------------------------------------------------
-entity DoubleNibbleDetect is
-	port (
-        Clock   : in std_logic;
-        RstIn   : in std_logic;
-        Final   : out std_logic;
-        DataIn  : in std_logic_vector(3 downto 0);
-        DataOut : out std_logic_vector(3 downto 0)
-	);
-end DoubleNibbleDetect;
----------------------------------------------------------------------------------------------
--- Architecture section
----------------------------------------------------------------------------------------------
-architecture DoubleNibbleDetect_struct of DoubleNibbleDetect is
----------------------------------------------------------------------------------------------
--- Component Instantiation
----------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------
--- Constants, Signals and Attributes Declarations
----------------------------------------------------------------------------------------------
--- Functions
--- Constants
-constant Low  : std_logic	:= '0';
-constant High : std_logic	:= '1';
--- Signals
-signal IntRegOutIn      : std_logic_vector(3 downto 0);
-signal IntAddr          : std_logic_vector(4 downto 0);
-signal IntSrlOut        : std_logic_vector(3 downto 0);
---
-signal IntRegOutIn_s      : std_logic_vector(3 downto 0);
-signal IntAddr_s          : std_logic_vector(4 downto 0);
-signal IntSrlOut_s        : std_logic_vector(3 downto 0);
-signal DataOut_s        : std_logic_vector(3 downto 0);
---
-signal IntEqu           : std_logic;
-signal IntEqu_d         : std_logic;
-signal IntPulse         : std_logic;
-signal IntSlipCnt       : std_logic_vector(3 downto 0);
-signal IntSlipCnt_d     : std_logic_vector(3 downto 0);
-signal IntSlipCntRst    : std_logic;
-signal IntEquCnt        : std_logic_vector(3 downto 0);
-signal IntEquCnt_d      : std_logic_vector(3 downto 0);
---
-signal IntRstSet        : std_logic;
-signal IntRstIn         : std_logic;
-signal IntRstFf_d       : std_logic_vector(7 downto 0) := X"00";
-signal IntRstIn_d       : std_logic;
---
-signal IntAddrSet       : std_logic_vector(3 downto 0);
--- Attributes
-attribute IOB : string;
-attribute HBLKNM : string;
----------------------------------------------------------------------------------------------
-begin
----------------------------------------------------------------------------------------------
--- Delay the start of the ciruit after reset.
----------------------------------------------------------------------------------------------
-IntRstIn <= RstIn or IntRstSet;
---
-Gen_Rst : for n in 0 to 7 generate
-    Reg_Lsb : if n = 0 generate
-        DbleNibl_I_Fdse : FDSE -- Synchronous set
-        generic map (INIT => '0')
-        port map (D => Low, CE => High, C => Clock, S => IntRstSet, Q => IntRstFf_d(n));
-    end generate Reg_Lsb;
-    Reg_MidL : if n > 0 and n <= 5 generate
-        DbleNibl_I_Fdse : FDSE -- Synchronous set
-        generic map (INIT => '0')
-        port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstSet,
-                  Q => IntRstFf_d(n));
-    end generate Reg_MidL;
-    Reg_MidH : if n = 6 generate
-        DbleNibl_I_Fdse : FDSE -- Synchronous set
-        generic map (INIT => '0')
-        port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstIn,
-                  Q => IntRstFf_d(n));
-    end generate Reg_MidH;
-    Reg_Msb : if n = 7 generate
-        DbleNibl_I_Fdse : FDSE -- Synchronous set
-        generic map (INIT => '0')
-        port map (D => IntRstFf_d(n-1), CE => High, C => Clock, S => IntRstIn,
-                  Q => IntRstFf_d(n));
-        --
-        IntRstIn_d <= IntRstFf_d(n);
-    end generate Reg_Msb;
-end generate Gen_Rst;
----------------------------------------------------------------------------------------------
--- Data path registers
----------------------------------------------------------------------------------------------
-Gen_Reg : for n in 3 downto 0 generate
-    In_I_Fdce : FDCE
-        generic map (INIT => '0')
-        port map (D => DataIn(n), CE => High, C => Clock, CLR => IntRstIn_d,
-                  Q => IntRegOutIn_s(n));
-IntRegOutIn(n) <= IntRegOutIn_s(n); -- after 100 ps;
-    DbleNibl_I_Srlc32e : SRLC32E
-        generic map (INIT => X"00000000")
-        port map (D => IntRegOutIn(n), A => IntAddr,  CE => High, CLK => Clock, Q31 => open,
-                  Q => IntSrlOut_s(n));
-IntSrlOut(n) <= IntSrlOut_s(n);  -- after 100 ps;
-    Out_I_Fdce : FDCE
-        generic map (INIT => '0')
-        port map (D => IntSrlOut(n), CE => High, C => Clock, CLR => IntRstIn_d,
-                  Q => DataOut_s(n));
-DataOut(n) <= DataOut_s(n);  -- after 100 ps;
-end generate Gen_Reg;
----------------------------------------------------------------------------------------------
--- Compare present and past for equality.
----------------------------------------------------------------------------------------------
-IntEqu <= '1' when (DataIn = IntRegOutIn) else '0';
------------------------------------------------------------------------------------------------
--- Generate the SRL addresses
----------------------------------------------------------------------------------------------
-IntAddr(3 downto 0) <= "0100" when (IntEquCnt_d = "0000" and IntSlipCnt_d = "0000") else
-                       "0011" when (IntEquCnt_d = "0001" and IntSlipCnt_d = "0111") else
-                       "0010" when (IntEquCnt_d = "0011" and IntSlipCnt_d = "0110") else
-                       "0001" when (IntEquCnt_d = "0010" and IntSlipCnt_d = "0010") else
-                       "0000" when (IntEquCnt_d = "0110" and IntSlipCnt_d = "0011") else
-                       "0100" when (IntEquCnt_d = "0111" and IntSlipCnt_d = "0001");
-IntAddr(4) <= Low;
---IntRstSet <= '1' when (IntEquCnt_d = "0111" and IntSlipCnt_d = "0001") else '0';
-IntRstSet <= '1' when (IntEquCnt_d = "0110" and IntSlipCnt_d = "0000" and IntPulse = '1')
-                 else '0';
-Final <= IntRstSet;
----------------------------------------------------------------------------------------------
--- Equal/Double nibble detect counters
----------------------------------------------------------------------------------------------
-IntPulse <= IntEqu or IntEqu_d;
---
-DbleNibl_I_Fdce : FDCE     -- Asynchronous reset
-    generic map (INIT => '0')
-    port map (D => High, CE => IntEqu, C => Clock, CLR => IntSlipCntRst, Q => IntEqu_d);
--- When a double nibble is detected shift the pulse over four taps and reset the shifter
--- at the fifth tap.
----------------------------------------------------------------------------------------------
--- Slip Counter
--- When equality is detected, this counter counts till a preset number and then resets.
----------------------------------------------------------------------------------------------
-IntSlipCntRst <= '1' when (IntRstIn_d = '1' or IntSlipCnt_d = "0101") else '0';
---
-Gen_SlipCnt : for n in 3 downto 0 generate
-    attribute HBLKNM of Cnt_I_Fdre : label is "SlipCnt";
-    attribute IOB of Cnt_I_Fdre : label is "FALSE";
-    begin
-    Cnt_I_Fdre : FDRE   -- Synchronous reset
-        generic map (INIT => '0')
-        port map (D => IntSlipCnt(n), CE => IntPulse, C => Clock, R => IntSlipCntRst,
-                  Q => IntSlipCnt_d(n));
-end generate Gen_SlipCnt;
--- These ar the "SlipCnt" states, orginized in Gray mode
-DbleNibl_SlipCnt_PROCESS : process (IntSlipCnt_d)
-begin
-    case IntSlipCnt_d(3 downto 0) is
-        when "0000" => IntSlipCnt <= "0001";  -- after 100 ps;
-        when "0001" => IntSlipCnt <= "0011";  -- after 100 ps;
-        when "0011" => IntSlipCnt <= "0010";  -- after 100 ps;
-        when "0010" => IntSlipCnt <= "0110";  -- after 100 ps;
-        when "0110" => IntSlipCnt <= "0111";  -- after 100 ps;
-        when "0111" => IntSlipCnt <= "0101";  -- after 100 ps;
-        when "0101" => IntSlipCnt <= "0000";  -- after 100 ps;
-        when others => IntSlipCnt <= "0000";  -- after 100 ps;
-    end case;
-end process;
----------------------------------------------------------------------------------------------
--- Equ Counter
--- Count how many times a double nibble is detected.
--- becuase a nibble of data is taken, it can only be four times.
--- When equality is detected for the fift time the system is reset.
----------------------------------------------------------------------------------------------
-Gen_EquCnt : for n in 3 downto 0 generate
-    attribute HBLKNM of Equ_I_Fdre : label is "EquCnt";
-    attribute IOB of Equ_I_Fdre : label is "FALSE";
-    begin
-    Equ_I_Fdre : FDRE   -- Synchronous reset
-        generic map (INIT => '0')
-        port map (D => IntEquCnt(n), CE => IntEqu, C => Clock, R => IntRstIn_d,
-                  Q => IntEquCnt_d(n));
-end generate Gen_EquCnt;
---
-DbleNibl_EquCnt_PROCESS : process (IntEquCnt_d)
-begin
-    case IntEquCnt_d(3 downto 0) is
-        when "0000" => IntEquCnt <= "0001";  -- after 100 ps;
-        when "0001" => IntEquCnt <= "0011";  -- after 100 ps;
-        when "0011" => IntEquCnt <= "0010";  -- after 100 ps;
-        when "0010" => IntEquCnt <= "0110";  -- after 100 ps;
-        when "0110" => IntEquCnt <= "0111";  -- after 100 ps;
-        when "0111" => IntEquCnt <= "0101";  -- after 100 ps;
-        when "0101" => IntEquCnt <= "0100";  -- after 100 ps;
-        when "0100" => IntEquCnt <= "1100";  -- after 100 ps;
-        when "1100" => IntEquCnt <= "1101";  -- after 100 ps;
-        when "1101" => IntEquCnt <= "1111";  -- after 100 ps;
-        when "1111" => IntEquCnt <= "1110";  -- after 100 ps;
-        when "1110" => IntEquCnt <= "1010";  -- after 100 ps;
-        when "1010" => IntEquCnt <= "1011";  -- after 100 ps;
-        when "1011" => IntEquCnt <= "1001";  -- after 100 ps;
-        when "1001" => IntEquCnt <= "1000";  -- after 100 ps;
-        when "1000" => IntEquCnt <= "0000";  -- after 100 ps;
-        when others => IntEquCnt <= "0000";  -- after 100 ps;
-    end case;
-end process;
---
----------------------------------------------------------------------------------------------
-end DoubleNibbleDetect_struct;
diff --git a/FEE_ADC32board/modules/ADCrefdesign/GenPulse.vhd b/FEE_ADC32board/modules/ADCrefdesign/GenPulse.vhd
deleted file mode 100644
index dd77e92..0000000
--- a/FEE_ADC32board/modules/ADCrefdesign/GenPulse.vhd
+++ /dev/null
@@ -1,132 +0,0 @@
------------------------------------------------------------------------------------------------
--- © Copyright 2008 - 2009, Xilinx, Inc. All rights reserved.
--- This file contains confidential and proprietary information of Xilinx, Inc. and is
--- protected under U.S. and international copyright and other intellectual property laws.
------------------------------------------------------------------------------------------------
---
--- Disclaimer:
---		This disclaimer is not a license and does not grant any rights to the materials
---		distributed herewith. Except as otherwise provided in a valid license issued to you
---		by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS
---		ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL
---		WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED
---		TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
---		PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including
---		negligence, or under any other theory of liability) for any loss or damage of any
---		kind or nature related to, arising under or in connection with these materials,
---		including for any direct, or any indirect, special, incidental, or consequential
---		loss or damage (including loss of data, profits, goodwill, or any type of loss or
---		damage suffered as a result of any action brought by a third party) even if such
---		damage or loss was reasonably foreseeable or Xilinx had been advised of the
---		possibility of the same.
---
--- CRITICAL APPLICATIONS
---		Xilinx products are not designed or intended to be fail-safe, or for use in any
---		application requiring fail-safe performance, such as life-support or safety devices
---		or systems, Class III medical devices, nuclear facilities, applications related to
---		the deployment of airbags, or any other applications that could lead to death,
---		personal injury, or severe property or environmental damage (individually and
---		collectively, "Critical Applications"). Customer assumes the sole risk and
---		liability of any use of Xilinx products in Critical Applications, subject only to
---		applicable laws and regulations governing limitations on product liability.
---
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. 
---
---		Contact:    e-mail  hotline@xilinx.com        phone   + 1 800 255 7778
---   ____  ____
---  /   /\/   /
--- /___/  \  /   Vendor: Xilinx
--- \   \   \/    Version: 
---  \   \        Filename: GenPulse.vhd
---  /   /        Date Last Modified:  
--- /___/   /\    Date Created:  08 Mar 08 
--- \   \  /  \
---  \___\/\___\
--- 
--- Device: 
--- Author: Marc Defossez
--- Entity Name:  GenPulse
--- Purpose: Generate a clock cycle wide pulse from a wide high input
--- Tools: ISE_10.1
--- Limitations: none
---
--- Revision History:
---    Rev. 
---
------------------------------------------------------------------------------------------------
--- Naming Conventions:
---   active low signals:                    "*_n"
---   clock signals:                         "clk", "clk_div#", "clk_#x"
---   reset signals:                         "rst", "rst_n"
---   generics:                              "C_*"
---   user defined types:                    "*_TYPE"
---   state machine next state:              "*_ns"
---   state machine current state:           "*_cs"
---   combinatorial signals:                 "*_com"
---   pipelined or register delay signals:   "*_d#"
---   counter signals:                       "*cnt*"
---   clock enable signals:                  "*_ce"
---   internal version of output port:       "*_i"
---   device pins:                           "*_pin"
---   ports:                                 "- Names begin with Uppercase"
---   processes:                             "*_PROCESS"
---   component instantiations:              "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------------------------
---
-library IEEE;
-	use IEEE.std_logic_1164.all;
-	use IEEE.std_logic_UNSIGNED.all;
-library UNISIM;
-	use UNISIM.VCOMPONENTS.all;
------------------------------------------------------------------------------------------------
--- Entity pin description
------------------------------------------------------------------------------------------------
---
------------------------------------------------------------------------------------------------
-entity GenPulse is
-    port (
-        Clk		: in std_logic;
-        Ena		: in std_logic;
-        SigIn	: in std_logic;
-        SigOut	: out std_logic
-    );
-end GenPulse;
-
------------------------------------------------------------------------------------------------
--- Arcitecture section
------------------------------------------------------------------------------------------------
-architecture GenPulse_struct of GenPulse  is
------------------------------------------------------------------------------------------------
--- Component Instantiation
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------
--- Constants, Signals and Attributes Declarations
------------------------------------------------------------------------------------------------
--- Functions
--- Constants
--- constant Low  : std_logic	:= '0';
--- constant High : std_logic	:= '1';
--- Signals
-signal IntSigOut : std_logic;
-signal IntSigIn_n : std_logic;
-signal IntSigClr	: std_logic;
--- Attributes
------------------------------------------------------------------------------------------------
---
-begin
---
-GenPulse_I_Fdce_1 : FDCE
-	generic map (INIT => '0')
-	port map (D => SigIn, C => Clk, CLR => IntSigClr, CE => Ena, Q => IntSigOut);
---
-IntSigIn_n <= not SigIn;
---
-GenPulse_I_Fdce_2 : FDCE
-	generic map (INIT => '0')
-	port map (D => IntSigOut, C => Clk, CLR => IntSigIn_n, CE => IntSigOut, Q => IntSigClr);
---
-SigOut <= IntSigOut;
---
------------------------------------------------------------------------------------------------
-end  GenPulse_struct;
---
\ No newline at end of file
diff --git a/FEE_ADC32board/modules/LMK03806.vhd b/FEE_ADC32board/modules/LMK03806.vhd
deleted file mode 100644
index 5314b04..0000000
--- a/FEE_ADC32board/modules/LMK03806.vhd
+++ /dev/null
@@ -1,564 +0,0 @@
------------------------------------------------------------
--- 					LMK03033 CONTROL UNIT						--
---																			--
---					uWIRE configuration Loader						--
------------------------------------------------------------
---	Device: xc5vlx50t-3ff665										--
---	ISE 11.4																--
--- created 15 Nov 2011 by Walter Puccio						--
--- Uppsala University, IRFU										--
--- Modified 23 Jan 2011 by P. Marciniewski					--
--- Uppsala University, Dept of Physics and Astronomy		--
------------------------------------------------------------	
-
-
--- LMK03806:
--- refclock/R = VCO/(P*N)
--- CLKout = VCO/Divide
---
--- refclock : reference input clock
--- R = R-divider (register 28)
--- VCO = Voltage Controlled Oscillator = 2370..2600 MHz
--- P = Prescaler : 2..8
--- N = N-divider
--- CLKout = Clock outputs (CLKout0..11)
--- Divide = outputclock divider
---
--- 80MHz -> 80 MHz :
---       R=1, VCO=2560, P=2, N=16, divide=32
---
--- 40MHz -> 80 MHz :
---       R=1, VCO=2560, P=2, N=32, divide=32
--- 40MHz -> 80 MHz :
---       R=1, VCO=2560, P=4, N=16, divide=32
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library UNISIM;
-use UNISIM.VComponents.all;
---use work.util_pack.ALL;
-
-entity LMK03806 is
-	generic(
-		CLK_DIV               : integer := 6;       -- slow down transfer
-		ADCCLOCKFREQUENCY     : natural := 62500000
-	);         
-	PORT( 
-		clock                 : in std_logic; --Master clock 
-		CLKu                  : out std_logic; --Clk to LMK  
-		DATAu                 : out std_logic; --Data to LMK
-		LEu                   : out std_logic; --Data Latch to LMK
-		RDn                   : in std_logic; --Read back
-		SYNC                  : out std_logic; --Sync CLK outputs LMK
-		boot_PLL              : in std_logic; --Start booting when set high
-		reset_GTX             : out std_logic; --delayed reset for GTX			
-		reset_ADCs            : out std_logic; --delayed reset for ADCs		
-		booting               : out std_logic; --busy signal		
-		testwordin            : in std_logic_vector(15 downto 0)
-		);
-end LMK03806;
-
-
-----------------------------------------------------------------
-
-architecture Behavioral of LMK03806 is
-constant NROFREGS : integer := 23+1+6;
-type RomType is array (0 to NROFREGS-1) of std_logic_vector(31 downto 0);
-type RomType32 is array (0 to 31) of std_logic_vector(31 downto 0);
--- parameters based on 'Clock design tool' from National Semiconductor
-CONSTANT TAB80M : RomType :=
--- 80MHz reference to 80MHz
-		( 
-		x"00020000",	--	R0		(Reset=1)		
-		x"00020000",	--	R0		(Reset=1)		
-		X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
-		X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
-		X"00000401", --R1 (Div=40 OUT2,3 80MHz)
-		X"00000401", --R1 (Div=40 OUT2,3 80MHz)
-		X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
-		X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
-		X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
-		X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
-		X"00000404", --R4 (Div=40 OUT8,9 80MHz)
-		X"00000404", --R4 (Div=40 OUT8,9 80MHz)
-		X"00000405", --R5 (Div=40 OUT10,11 80MHz)
-		X"00000405", --R5 (Div=40 OUT10,11 80MHz)
-		x"11110006",	--	R6		(OUT	3,2,1,0		:	LVDS)
-		x"11110007",	--	R7		(OUT	7,6,5,4		:	LVDS)  11110007
-		x"11110008",	--	R8		(OUT	11,10,9,8	:	LVDS)
-		x"55555549",	--	R9		(fixed pattern)			
-		x"1000400A",	--	R10	(OSCout1=LVPECL-1600mV OSCout0=LVDS	OSCout1..0=disabled	OSC0..1=bypass_divider	OSCoutDIV=2)
-		x"3401100B",	--	R11	(SYNC=enabled	active=low	externalXTAL=disabled)			
-		x"130C006C",	--	R12	(LD_MUX=PLL_DLD	LD_TYPE=output	Force	sync)		
-		x"7B03800D",	--	R13	(READ_BACK=pushpull	GPout0=weak	pulldown)			
-		x"0300000E",	--	R14	(GPout1=weak	pulldown)				
-		x"C1550410",	--	R16	(fixed pattern)		
-		x"DD000018",	--	R24	(LoopFilter:	C4=10pF	C3=10pF	R4=200Ohm	R3=200Ohm)	00000018
-		x"83A8001A",	--	R26	(reffrequ=normal	chargepump=100uA	PLL_DLD_CNT=8192	???????????)		
-		x"0010001C",	--	R28	(R_divider=1			          
-		x"0080041D",	--	R29	(OSCin=63MHz..127MHz	N_CALdivider=32	
-		x"0200041E",	--	R30	(N_prescaler=2	N_divider=32)				
-		x"0002001F"		--	R31	(ReadbackReg=0	Regs:unlocked)			001F001F	
-		);		
-
-
-CONSTANT TAB80M_orig : RomType :=
--- 80MHz reference to 80MHz
-		( 
-		x"00020000",    --      R0              (Reset=1)               
-		x"00020000",    --      R0              (Reset=1)               
-		X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
-		X"00000400", --R0 (Reset=0, Div=32 OUT0,1 80MHz)
-		X"00000401", --R1 (Div=40 OUT2,3 80MHz)
-		X"00000401", --R1 (Div=40 OUT2,3 80MHz)
-		X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
-		X"00000402", --R2 (Div=20 OUT4,5 80MHz, GTX0) 00000282
-		X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
-		X"00000403", --R3 (Div=20 OUT6,7 80MHz, GTX1) 00000283
-		X"00000404", --R4 (Div=40 OUT8,9 80MHz)
-		X"00000404", --R4 (Div=40 OUT8,9 80MHz)
-		X"00000405", --R5 (Div=40 OUT10,11 80MHz)
-		X"00000405", --R5 (Div=40 OUT10,11 80MHz)
-		x"11110006",    --      R6              (OUT    3,2,1,0         :       LVDS)
-		x"11110007",    --      R7              (OUT    7,6,5,4         :       LVDS)  11110007
-		x"11110008",    --      R8              (OUT    11,10,9,8       :       LVDS)
-		x"55555549",    --      R9              (fixed pattern)                 
-		x"1000400A",    --      R10     (OSCout1=LVPECL-1600mV OSCout0=LVDS     OSCout1..0=disabled     OSC0..1=bypass_divider  OSCoutDIV=2)
-		x"3401100B",    --      R11     (SYNC=enabled   active=low      externalXTAL=disabled)                  
-		x"130C006C",    --      R12     (LD_MUX=PLL_DLD LD_TYPE=output  Force   sync)           
-		x"7B03800D",    --      R13     (READ_BACK=pushpull     GPout0=weak     pulldown)                       
-		x"0300000E",    --      R14     (GPout1=weak    pulldown)                               
-		x"C1550410",    --      R16     (fixed pattern)         
-		x"DD000018",    --      R24     (LoopFilter:    C4=10pF C3=10pF R4=200Ohm       R3=200Ohm)      00000018
-		x"83A8001A",    --      R26     (reffrequ=normal        chargepump=100uA        PLL_DLD_CNT=8192        ???????????)            
-		x"0010001C",    --      R28     (R_divider=1                              ????????? :2          
-		x"0180021D",    --      R29     (OSCin=63MHz..127MHz    N_CALdivider=16 
-		x"0200021E",    --      R30     (N_prescaler=2  N_divider=16)                           
-		x"0002001F"             --      R31     (ReadbackReg=0  Regs:unlocked)                  001F001F        
-		);              
-
---CONSTANT TAB62M5 : RomType :=		
----- 62.5MHz reference to 62.5MHz
---		( 
---		x"00020000",	--	R0		(Reset=1)		
---		x"00020000",	--	R0		(Reset=1)		
---		X"00000500", --R0 (Reset=0, Div=40 OUT0,1 62.5MHz)
---		X"00000500", --R0 (Reset=0, Div=40 OUT0,1 62.5MHz)
---		X"00000501", --R1 (Div=40 OUT2,3 62.5MHz)
---		X"00000501", --R1 (Div=40 OUT2,3 62.5MHz)
---		X"00000502", --R2 (Div=20 OUT4,5 125MHz, GTX0) 00000282
---		X"00000502", --R2 (Div=20 OUT4,5 125MHz, GTX0) 00000282
---		X"00000503", --R3 (Div=20 OUT6,7 125MHz, GTX1) 00000283
---		X"00000503", --R3 (Div=20 OUT6,7 125MHz, GTX1) 00000283
---		X"00000504", --R4 (Div=40 OUT8,9 62.5MHz)
---		X"00000504", --R4 (Div=40 OUT8,9 62.5MHz)
---		X"00000505", --R5 (Div=40 OUT10,11 62.5MHz)
---		X"00000505", --R5 (Div=40 OUT10,11 62.5MHz)
---		x"11110006",	--	R6		(OUT	3,2,1,0		:	LVDS)
---		x"11110007",	--	R7		(OUT	7,6,5,4		:	LVDS)  11110007
---		x"11110008",	--	R8		(OUT	11,10,9,8	:	LVDS)
---		x"55555549",	--	R9		(fixed pattern)			
---		x"1000400A",	--	R10	(OSCout1=LVPECL-1600mV OSCout0=LVDS	OSCout1..0=disabled	OSC0..1=bypass_divider	OSCoutDIV=2)
---		x"3401100B",	--	R11	(SYNC=enabled	active=low	externalXTAL=disabled)			
---		x"130C006C",	--	R12	(LD_MUX=PLL_DLD	LD_TYPE=output	Force	sync)		
---		x"7B03800D",	--	R13	(READ_BACK=pushpull	GPout0=weak	pulldown)			
---		x"0300000E",	--	R14	(GPout1=weak	pulldown)				
---		x"C1550410",	--	R16	(fixed pattern)		
---		x"DD000018",	--	R24	(LoopFilter:	C4=10pF	C3=10pF	R4=200Ohm	R3=200Ohm)	00000018
---		x"83A8001A",	--	R26	(reffrequ=normal	chargepump=100uA	PLL_DLD_CNT=8192	???????????)		
---		x"0010001C",	--	R28	(R_divider=1			          ????????? :2 		
---		x"0080029D",	--	R29	(OSCin=0..63MHz	N_CALdivider=20	
---		x"0200029E",	--	R30	(N_prescaler=2	N_divider=20)				
---		x"0002001F"		--	R31	(ReadbackReg=0	Regs:unlocked)			001F001F	
---		);								
-
---		( 
---		X"000204c0", --R0 (Reset=1, Div=38 OUT0,1)
---		X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
---		X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
---		X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0)
---		X"00000163", --R3 (Div=19 OUT6,7 125MHz, GTX1)
---		X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
---		X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
---		X"11110006", --R6 (OUT3,2,1,0 : LVDS)
---		X"11110007", --R7 (OUT7,6,5,4 : LVDS)
---		X"11110008", --R8 (OUT11,10,9,8 : LVDS)
---		X"55555549", --R9 (fixed)
---		X"1002400a", --R10 (OSCout0=700mV OSCout1=off OSCout=disabled OSC0,1=bypass_divider OSCoutDIV=2)
---		X"3400000b", --R11 (SYNC=enabled, active=high, externalXTAL=disabled)
---		X"138c006c", --R12 (LD_MUX=PLL_DLD, LD_TYPE=output, Force sync)
---		X"7b03800d", --R13 (READ_BACK=pushpull, GPout0=weak pulldown)
---		X"0300000e", --R14 (GPout1=weak pulldown)
---		X"c1550410", --R16 (fixed)
---		X"00000018", --R24 (LoopFilter: C4=10pF, C3=10pF, R4=200Ohm, R3=200Ohm)  
---		X"8fa8001a", --R26 (reffrequ=normal, chargepump=3.2mA, PLL_DLD_CNT=8192  ???????????) 
---		X"0010001c", --R28 (R_divider=1, 
---		X"0080027d", --R29 (OSCin=0..63MHz, N_CALdivider=19 ?????????????)
---		X"0100027e", --R30 (N_prescaler=2, N_divider=19)
---		X"0000001f"  --R31 (ReadbackReg=0, Regs:unlocked)
---		);	
-
---		( 
---		x"80020140",	--	R0		(Reset=1	Div=10	OUT0..1 -> PWD)		
---		x"00000400",	--	R0		(Div=32	OUT0..1	-> 77.76 MHz	ADC)	
---		x"00000401",	--	R1		(Div=32	OUT2..3	-> 77.76 MHz	ADC)		
---		x"00000202",	--	R2		(Div=16	OUT4..5	-> 155.52 MHz	GTX0)	
---		x"00000203",	--	R3		(Div=16	OUT6..7	-> 155.52 MHz	GTX1)	
---		x"00000404",	--	R4		(Div=32	OUT8..9	-> 77.76 MHz	ADC)		
---		x"00000405",	--	R5		(Div=32	OUT10	11	-> 77.76 MHz	ADC)		
---		x"11110006",	--	R6		(OUT	3,2,1,0		:	LVDS)
---		x"11110007",	--	R7		(OUT	7,6,5,4		:	LVDS)
---		x"11110008",	--	R8		(OUT	11,10,9,8	:	LVDS)
---		x"55555549",	--	R9		(fixed pattern)					
---		x"9102400A",	--	R10	(OSCout1=LVPECL-1600mV OSCout0=LVDS	OSCout1..0=disabled	OSC0..1=bypass_divider	OSCoutDIV=2)
---		x"343f100B",	--	R11	(SYNC=enabled	active=low, pulldownR	externalXTAL=disabled)	 -- peter, was	3401100B		
---		x"138C006C",	--	R12	(LD_MUX=PLL_DLD	LD_TYPE=output	Force	sync)	 -- peter, was	130C006C	
---		x"3B03800D",	--	R13	(READ_BACK=pushpull	GPout0=weak	pulldown)			 -- peter, was	3B03826D	
---		x"0300000E",	--	R14	(GPout1=weak	pulldown)				
---		x"C1550410",	--	R16	(fixed pattern)					
---		x"00000018",	--	R24	(LoopFilter:	C4=10pF	C3=10pF	R4=200Ohm	R3=200Ohm)	
---		x"8FA8001A",	--	R26	(reffrequ=normal	chargepump=3.2mA	PLL_DLD_CNT=8192	???????????)		
---		x"0010001C",	--	R28	(R_divider=2				-- peter, was	0010001C
---		x"0180021D",	--	R29	(OSCin=127..255Hz	N_CALdivider=16	?????????????)		-- peter, was	0280011D	
---		x"0200021E",	--	R30	(N_prescaler=2	N_divider=16)				-- peter, was	0200011E
---		x"001F001F"		--	R31	(ReadbackReg=31	Regs:unlocked)				
---		);								
-
---		( -- Pawel
---		x"80020140",	--	R0		(Reset=1	Div=10	OUT0..1 -> PWD)		
---		x"00000400",	--	R0		(Div=32	OUT0..1	-> 77.76 MHz	ADC)	
---		x"00000401",	--	R1		(Div=32	OUT2..3	-> 77.76 MHz	ADC)		
---		x"00000202",	--	R2		(Div=16	OUT4..5	-> 155.52 MHz	GTX0)	
---		x"00000203",	--	R3		(Div=16	OUT6..7	-> 155.52 MHz	GTX1)	
---		x"00000404",	--	R4		(Div=32	OUT8..9	-> 77.76 MHz	ADC)		
---		x"00000405",	--	R5		(Div=32	OUT10	11	-> 77.76 MHz	ADC)		
---		x"11110006",	--	R6		(OUT	3,2,1,0		:	LVDS)
---		x"11110007",	--	R7		(OUT	7,6,5,4		:	LVDS)
---		x"11110008",	--	R8		(OUT	11,10,9,8	:	LVDS)
---		x"55555549",	--	R9		(fixed pattern)					
---		x"9102400A",	--	R10	(OSCout1=LVPECL-1600mV OSCout0=LVDS	OSCout1..0=disabled	OSC0..1=bypass_divider	OSCoutDIV=2)
---		x"3401100B",	--	R11	(SYNC=enabled	active=high	externalXTAL=disabled)			
---		x"130C006C",	--	R12	(LD_MUX=PLL_DLD	LD_TYPE=output	Force	sync)		
---		x"3B03826D",	--	R13	(READ_BACK=pushpull	GPout0=weak	pulldown)			
---		x"0300000E",	--	R14	(GPout1=weak	pulldown)				
---		x"C1550410",	--	R16	(fixed pattern)					
---		x"00000018",	--	R24	(LoopFilter:	C4=10pF	C3=10pF	R4=200Ohm	R3=200Ohm)	
---		x"8FA8001A",	--	R26	(reffrequ=normal	chargepump=3.2mA	PLL_DLD_CNT=8192	???????????)		
---		x"0010001C",	--	R28	(R_divider=1					
---		x"0080021D",	--	R29	(OSCin=0..63MHz	N_CALdivider=19	?????????????)			
---		x"0200021E",	--	R30	(N_prescaler=2	N_divider=19)				
---		x"001F001F"		--	R31	(ReadbackReg=0	Regs:unlocked)				
---		);		
-
---		( -- Pawel
---		x"80020140",	--	R0		(Reset=1	Div=10	OUT0..1 -> PWD)		
---		x"00000500",	--	R0		(Div=32	OUT0..1	-> 77.76 MHz	ADC)	
---		x"00000501",	--	R1		(Div=32	OUT2..3	-> 77.76 MHz	ADC)		
---		x"00000282",	--	R2		(Div=16	OUT4..5	-> 155.52 MHz	GTX0)	
---		x"00000283",	--	R3		(Div=16	OUT6..7	-> 155.52 MHz	GTX1)	
---		x"00000504",	--	R4		(Div=32	OUT8..9	-> 77.76 MHz	ADC)		
---		x"00000505",	--	R5		(Div=32	OUT10	11	-> 77.76 MHz	ADC)		
---		x"00000500",	--	R0		(Div=32	OUT0..1	-> 77.76 MHz	ADC)	
---		x"00000501",	--	R1		(Div=32	OUT2..3	-> 77.76 MHz	ADC)		
---		x"00000282",	--	R2		(Div=16	OUT4..5	-> 155.52 MHz	GTX0)	
---		x"00000283",	--	R3		(Div=16	OUT6..7	-> 155.52 MHz	GTX1)	
---		x"00000504",	--	R4		(Div=32	OUT8..9	-> 77.76 MHz	ADC)		
---		x"00000505",	--	R5		(Div=32	OUT10	11	-> 77.76 MHz	ADC)		
---		x"11110006",	--	R6		(OUT	3,2,1,0		:	LVDS)
---		x"11110007",	--	R7		(OUT	7,6,5,4		:	LVDS)
---		x"11110008",	--	R8		(OUT	11,10,9,8	:	LVDS)
---		x"55555549",	--	R9		(fixed pattern)					
---		x"9000400A",	--	R10	(OSCout1=LVPECL-1600mV OSCout0=LVDS	OSCout1..0=disabled	OSC0..1=bypass_divider	OSCoutDIV=2)
---		x"3401100B",	--	R11	(SYNC=enabled	active=low	externalXTAL=disabled)			
---		x"130C006C",	--	R12	(LD_MUX=PLL_DLD	LD_TYPE=output	Force	sync)		
---		x"7B02800D",	--	R13	(READ_BACK=pushpull	GPout0=weak	pulldown)			
---		x"0200000E",	--	R14	(GPout1=weak	pulldown)				
---		x"C1550410",	--	R16	(fixed pattern)					
---		x"00000018",	--	R24	(LoopFilter:	C4=10pF	C3=10pF	R4=200Ohm	R3=200Ohm)	
---		x"8FA8001A",	--	R26	(reffrequ=normal	chargepump=3.2mA	PLL_DLD_CNT=8192	???????????)		
---		x"0020001C",	--	R28	(R_divider=2					
---		x"0180051D",	--	R29	(OSCin=0..63MHz	N_CALdivider=40	?????????????)			
---		x"0200051E",	--	R30	(N_prescaler=2	N_divider=40)				
---		x"001F001F"		--	R31	(ReadbackReg=0	Regs:unlocked)				
---		);								
-
-
---		( 
---		x"00020000",	--	R0		(Reset=1)		
---		x"00020000",	--	R0		(Reset=1)		
---		X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
---		X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
---		X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
---		X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
---		X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0)
---		X"000004c2", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
---		X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1)
---		X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1)
---		X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
---		X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
---		X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
---		X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
---		x"11110006",	--	R6		(OUT	3,2,1,0		:	LVDS)
---		x"11110007",	--	R7		(OUT	7,6,5,4		:	LVDS)
---		x"11110008",	--	R8		(OUT	11,10,9,8	:	LVDS)
---		x"55555549",	--	R9		(fixed pattern)			
---		x"9002400A",	--	R10	(OSCout1=LVPECL-1600mV OSCout0=LVDS	OSCout1..0=disabled	OSC0..1=bypass_divider	OSCoutDIV=2)
-------		x"9000400A",	--	R10	(OSCout1=LVPECL-1600mV OSCout0=LVDS	OSCout1..0=disabled	OSC0..1=bypass_divider	OSCoutDIV=2)
---		x"3401100B",	--	R11	(SYNC=enabled	active=low	externalXTAL=disabled)			
---		x"138C006C",	--	R12	(LD_MUX=PLL_DLD	LD_TYPE=output	Force	sync)		
---		x"3B03826D",	--	R13	(READ_BACK=pushpull	GPout0=weak	pulldown)	 130C006C		
-------		x"7B02800D",	--	R13	(READ_BACK=pushpull	GPout0=weak	pulldown)			
---		x"0300000E",	--	R14	(GPout1=weak	pulldown)				
-------		x"0200000E",	--	R14	(GPout1=weak	pulldown)				
---		x"C1550410",	--	R16	(fixed pattern)		
---		x"00000018",	--	R24	(LoopFilter:	C4=10pF	C3=10pF	R4=200Ohm	R3=200Ohm)	
---		x"8FA8001A",	--	R26	(reffrequ=normal	chargepump=3.2mA	PLL_DLD_CNT=8192	???????????)		
---		x"0010001C",	--	R28	(R_divider=1			          ????????? :2 		
---		x"0080027D",	--	R29	(OSCin=0..63MHz	N_CALdivider=19	?????????????)			
---		x"0200027E",	--	R30	(N_prescaler=2	N_divider=19)				
---		x"0002001F"		--	R31	(ReadbackReg=0	Regs:unlocked)			001F001F	
---		);				
-
-				
---		( 
---		x"00020000",	--	R0		(Reset=1)		
---		x"00020000",	--	R0		(Reset=1)		
---		X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
---		X"000004c0", --R0 (Reset=0, Div=38 OUT0,1 62.5MHz)
---		X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
---		X"000004c1", --R1 (Div=38 OUT2,3 62.5MHz)
---		X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
---		X"00000262", --R2 (Div=19 OUT4,5 125MHz, GTX0) 00000262
---		X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1) 00000263
---		X"00000263", --R3 (Div=19 OUT6,7 125MHz, GTX1) 00000263
---		X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
---		X"000004c4", --R4 (Div=38 OUT8,9 62.5MHz)
---		X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
---		X"000004c5", --R5 (Div=38 OUT10,11 62.5MHz)
---		x"11110006",	--	R6		(OUT	3,2,1,0		:	LVDS)
---		x"11110007",	--	R7		(OUT	7,6,5,4		:	LVDS)  11110007
---		x"11110008",	--	R8		(OUT	11,10,9,8	:	LVDS)
---		x"55555549",	--	R9		(fixed pattern)			
-------		x"9002400A",	--	R10	(OSCout1=LVPECL-1600mV OSCout0=LVDS	OSCout1..0=disabled	OSC0..1=bypass_divider	OSCoutDIV=2)
---		x"9000400A",	--	R10	(OSCout1=LVPECL-1600mV OSCout0=LVDS	OSCout1..0=disabled	OSC0..1=bypass_divider	OSCoutDIV=2)
---		x"3401100B",	--	R11	(SYNC=enabled	active=low	externalXTAL=disabled)			
---		x"138C006C",	--	R12	(LD_MUX=PLL_DLD	LD_TYPE=output	Force	sync)		
-------		x"3B03826D",	--	R13	(READ_BACK=pushpull	GPout0=weak	pulldown)	 130C006C		
---		x"7B02800D",	--	R13	(READ_BACK=pushpull	GPout0=weak	pulldown)			
-------		x"0300000E",	--	R14	(GPout1=weak	pulldown)				
---		x"0200000E",	--	R14	(GPout1=weak	pulldown)				
---		x"C1550410",	--	R16	(fixed pattern)		
---		x"77110018",	--	R24	(LoopFilter:	C4=10pF	C3=10pF	R4=200Ohm	R3=200Ohm)	00000018
---		x"8FA8001A",	--	R26	(reffrequ=normal	chargepump=3.2mA	PLL_DLD_CNT=8192	???????????)		
---		x"0020001C",	--	R28	(R_divider=1			          ????????? :2 		
---		x"0180027D",	--	R29	(OSCin=0..63MHz	N_CALdivider=19	?????????????)		 0080027D	
---		x"0200027E",	--	R30	(N_prescaler=2	N_divider=19)				
---		x"0002001F"		--	R31	(ReadbackReg=0	Regs:unlocked)			001F001F	
---		);								
-
-
-
-
-
-
-
-signal tab                         : RomType; 
-signal SHIFT_REG                   : std_logic_vector(31 downto 0); 
-signal PLLbootstate                : std_logic_vector(3 downto 0); 
-signal bit_cnt                     : std_logic_vector(6 downto 0); 
-signal cnt_dly                     : std_logic_vector(3 downto 0); 
-signal ptr	                       : std_logic_vector(4 downto 0); 
-
-signal boot_dly_cnt                : std_logic_vector(31 downto 0) := (others => '0');
-signal pll_res                     : std_logic;
-
-signal pll_boot                    : std_logic;
-signal pll_clk                     : std_logic;
-signal pll_data                    : std_logic;
-signal pll_le                      : std_logic;
-signal pll_sync                    : std_logic;
-signal pll_reset_GTX               : std_logic;
-signal pll_reset_ADCs              : std_logic;
-
-signal reset_counter_V1					: std_logic_vector(15 downto 0);
-signal reset_counter_V2					: std_logic_vector(7 downto 0);
-
---------------------------------------------------------------------
-BEGIN
-
-tab <= TAB80M;-- when ADCCLOCKFREQUENCY=80000000 else TAB62M5;
-
---******************************************************************
---								RESET SEQUENCER
---******************************************************************  
-
-process(clock)
-begin
-	if rising_edge(clock) then
-		if PLLbootstate /= x"0" then
-			reset_counter_V1 <= (others => '0');
-			pll_reset_ADCs <= '1';
-			pll_reset_GTX <= '1';
-			booting <= '1';
-		else
-			booting <= '0';
-			if reset_counter_V1 < x"ffff" then
-				reset_counter_V1 <= reset_counter_V1 + 1;
-			else
-				pll_reset_ADCs <= '0';
-				pll_reset_GTX <= '0';
-			end if;
-		end if;
-	end if;
-end process;
-
-
-process(clock)
-begin
-	if rising_edge(clock) then
-		if reset_counter_V2 < x"ff" then
-			reset_counter_V2 <= reset_counter_V2 + 1;
-			pll_res <= '1';
-		else
-			pll_res <= '0';
-		end if;
-	end if;
-end process;
-
-
---******************************************************************
---							PLL BOOT STATEMACHINE
---******************************************************************  
-
-process(clock, pll_res)
-begin
-   if pll_res = '1' then
-		PLLbootstate <= (others => '0');
-		pll_sync 	<= '1';
-		--GOE <= '0';
-		pll_clk 	<= '0';
-		pll_le 	<= '0';
-		ptr 	<= (others => '0');
-
-	elsif rising_edge(clock) then
-
-		pll_boot <= BOOT_PLL;
-		
-		case PLLbootstate is
-			when x"0" =>	--IDLE here until BOOT_DLY goes High
-				pll_sync <= '1';
-				--GOE <= '0';
-				pll_clk <= '0';
-				pll_le <= '0';
-				ptr <= (others => '0');
-				if pll_boot = '1' then PLLbootstate <= x"1";
-				end if;
-				
---*******Start
-			when x"1" =>	--Set up for TX
-				pll_le <= '0';
-				pll_clk <= '0';
-if ptr=24 then
-SHIFT_REG(15 downto 0) <= x"0018";
-SHIFT_REG(31 downto 16) <= testwordin;
-else
-				SHIFT_REG <= tab(conv_integer(ptr));
-end if;
-				bit_cnt <= (others => '0');
-				cnt_dly <= (others => '0');
-				PLLbootstate <= x"2";
-				
-			when x"2" =>	--CLK low
-				pll_clk <= '0';
-				if cnt_dly > CLK_DIV then
-					cnt_dly <= (others => '0');
-					PLLbootstate <= x"3";
-				else cnt_dly <= cnt_dly + 1;
-				end if;
-
-			when x"3" =>	--CLK high
-				pll_clk <= '1';
-				if cnt_dly > CLK_DIV then
-					cnt_dly <= (others => '0');
-					bit_cnt <= bit_cnt + 1;
-					PLLbootstate <= x"4";
-				else cnt_dly <= cnt_dly + 1;
-				end if;
-
-			when x"4" =>	--Loop through all bits and regs
-				pll_clk <= '0';
-				cnt_dly <= (others => '0');
-				SHIFT_REG <= SHIFT_REG(30 downto 0) & '0';
-				if bit_cnt > 31 then	--32 bits
-					pll_le <= '1';
-					if conv_integer(ptr) < NROFREGS-1 then	--nr of regs
-						ptr <= ptr + 1;
-						PLLbootstate <= x"5";
-					else 
-----peter						pll_sync <= '0';
-						PLLbootstate <= x"6";
-					end if;
-				else PLLbootstate <= x"2";
-				end if;
-
-			when x"5" =>	--Latch Delay
-				if cnt_dly > CLK_DIV then
-					cnt_dly <= (others => '0');
-					PLLbootstate <= x"1";
-				else cnt_dly <= cnt_dly + 1;
-				end if;
-
-			when x"6" =>	--pll_sync Delay
-				if cnt_dly > CLK_DIV then
-					cnt_dly <= (others => '0');
-					PLLbootstate <= x"7";
-				else cnt_dly <= cnt_dly + 1;
-				end if;
-
-			when x"7" =>	--SYNC
-				if cnt_dly > CLK_DIV then
-					cnt_dly <= (others => '0');
-					PLLbootstate <= x"8";
-					pll_sync <= '0';	
-				else cnt_dly <= cnt_dly + 1;
-				end if;
-				pll_le <= '0';
-
-			when x"8" =>	--SYNC
-				if cnt_dly > CLK_DIV then
-					cnt_dly <= (others => '0');
-					PLLbootstate <= x"9";
-				else cnt_dly <= cnt_dly + 1;
-				end if;
-				pll_le <= '0';
-
-			when x"9" =>	--IDLE here until BOOT_PLL goes low
-				pll_sync <= '1';	
-				pll_le <= '0';
-				if pll_boot = '0' then PLLbootstate <= x"0";
-				end if;
-				
-    		when others =>	-- make sure other states wont lock up.
-				PLLbootstate <= (others => '0');   
-		end case;
-	end if;
-end process;	
-
---Shift out bits, MSB first
-pll_data <= SHIFT_REG(31);
-
-
-CLKu 			<= pll_clk;
-DATAu 		<= pll_data;
-LEu 			<= pll_le;
-SYNC			<= pll_sync;
-reset_GTX	<= pll_reset_GTX;
-reset_ADCs	<= pll_reset_ADCs;
-
-
-END Behavioral;
-
-
diff --git a/FEE_ADC32board/project/FEE_ADC32board.gise b/FEE_ADC32board/project/FEE_ADC32board.gise
deleted file mode 100644
index d8991cb..0000000
--- a/FEE_ADC32board/project/FEE_ADC32board.gise
+++ /dev/null
@@ -1,33 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FEE_ADC32board.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema"/>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/FEE_ADC32board.ucf b/FEE_ADC32board/project/FEE_ADC32board.ucf
deleted file mode 100644
index c20f4de..0000000
--- a/FEE_ADC32board/project/FEE_ADC32board.ucf
+++ /dev/null
@@ -1,1009 +0,0 @@
-NET "AD11A_N" DIFF_TERM = "TRUE";
-NET "AD11A_N" IOSTANDARD = LVDS_25;
-NET "AD11A_N" LOC = C17;
-NET "AD11A_P" DIFF_TERM = "TRUE";
-NET "AD11A_P" IOSTANDARD = LVDS_25;
-NET "AD11A_P" LOC = C16;
-NET "AD11B_N" DIFF_TERM = "TRUE";
-NET "AD11B_N" IOSTANDARD = LVDS_25;
-NET "AD11B_N" LOC = A18;
-NET "AD11B_P" DIFF_TERM = "TRUE";
-NET "AD11B_P" IOSTANDARD = LVDS_25;
-NET "AD11B_P" LOC = A17;
-NET "AD12A_N" DIFF_TERM = "TRUE";
-NET "AD12A_N" IOSTANDARD = LVDS_25;
-NET "AD12A_N" LOC = D18;
-NET "AD12A_P" DIFF_TERM = "TRUE";
-NET "AD12A_P" IOSTANDARD = LVDS_25;
-NET "AD12A_P" LOC = D17;
-NET "AD12B_N" DIFF_TERM = "TRUE";
-NET "AD12B_N" IOSTANDARD = LVDS_25;
-NET "AD12B_N" LOC = C18;
-NET "AD12B_P" DIFF_TERM = "TRUE";
-NET "AD12B_P" IOSTANDARD = LVDS_25;
-NET "AD12B_P" LOC = B18;
-NET "AD13A_N" DIFF_TERM = "TRUE";
-NET "AD13A_N" IOSTANDARD = LVDS_25;
-NET "AD13A_N" LOC = F17;
-NET "AD13A_P" DIFF_TERM = "TRUE";
-NET "AD13A_P" IOSTANDARD = LVDS_25;
-NET "AD13A_P" LOC = E17;
-NET "AD13B_N" DIFF_TERM = "TRUE";
-NET "AD13B_N" IOSTANDARD = LVDS_25;
-NET "AD13B_N" LOC = H15;
-NET "AD13B_P" DIFF_TERM = "TRUE";
-NET "AD13B_P" IOSTANDARD = LVDS_25;
-NET "AD13B_P" LOC = G15;
-NET "AD14A_N" DIFF_TERM = "TRUE";
-NET "AD14A_N" IOSTANDARD = LVDS_25;
-NET "AD14A_N" LOC = H16;
-NET "AD14A_P" DIFF_TERM = "TRUE";
-NET "AD14A_P" IOSTANDARD = LVDS_25;
-NET "AD14A_P" LOC = G16;
-NET "AD14B_N" DIFF_TERM = "TRUE";
-NET "AD14B_N" IOSTANDARD = LVDS_25;
-NET "AD14B_N" LOC = B16;
-NET "AD14B_P" DIFF_TERM = "TRUE";
-NET "AD14B_P" IOSTANDARD = LVDS_25;
-NET "AD14B_P" LOC = A16;
-NET "AD15A_N" DIFF_TERM = "TRUE";
-NET "AD15A_N" IOSTANDARD = LVDS_25;
-NET "AD15A_N" LOC = F14;
-NET "AD15A_P" DIFF_TERM = "TRUE";
-NET "AD15A_P" IOSTANDARD = LVDS_25;
-NET "AD15A_P" LOC = G14;
-NET "AD15B_N" DIFF_TERM = "TRUE";
-NET "AD15B_N" IOSTANDARD = LVDS_25;
-NET "AD15B_N" LOC = B14;
-NET "AD15B_P" DIFF_TERM = "TRUE";
-NET "AD15B_P" IOSTANDARD = LVDS_25;
-NET "AD15B_P" LOC = A14;
-NET "AD16A_N" DIFF_TERM = "TRUE";
-NET "AD16A_N" IOSTANDARD = LVDS_25;
-NET "AD16A_N" LOC = E14;
-NET "AD16A_P" DIFF_TERM = "TRUE";
-NET "AD16A_P" IOSTANDARD = LVDS_25;
-NET "AD16A_P" LOC = D14;
-NET "AD16B_N" DIFF_TERM = "TRUE";
-NET "AD16B_N" IOSTANDARD = LVDS_25;
-NET "AD16B_N" LOC = G13;
-NET "AD16B_P" DIFF_TERM = "TRUE";
-NET "AD16B_P" IOSTANDARD = LVDS_25;
-NET "AD16B_P" LOC = F13;
-NET "AD17A_N" DIFF_TERM = "TRUE";
-NET "AD17A_N" IOSTANDARD = LVDS_25;
-NET "AD17A_N" LOC = D13;
-NET "AD17A_P" DIFF_TERM = "TRUE";
-NET "AD17A_P" IOSTANDARD = LVDS_25;
-NET "AD17A_P" LOC = C13;
-NET "AD17B_N" DIFF_TERM = "TRUE";
-NET "AD17B_N" IOSTANDARD = LVDS_25;
-NET "AD17B_N" LOC = E12;
-NET "AD17B_P" DIFF_TERM = "TRUE";
-NET "AD17B_P" IOSTANDARD = LVDS_25;
-NET "AD17B_P" LOC = F12;
-NET "AD18A_N" DIFF_TERM = "TRUE";
-NET "AD18A_N" IOSTANDARD = LVDS_25;
-NET "AD18A_N" LOC = B13;
-NET "AD18A_P" DIFF_TERM = "TRUE";
-NET "AD18A_P" IOSTANDARD = LVDS_25;
-NET "AD18A_P" LOC = A13;
-NET "AD18B_N" DIFF_TERM = "TRUE";
-NET "AD18B_N" IOSTANDARD = LVDS_25;
-NET "AD18B_N" LOC = H13;
-NET "AD18B_P" DIFF_TERM = "TRUE";
-NET "AD18B_P" IOSTANDARD = LVDS_25;
-NET "AD18B_P" LOC = H12;
-
-NET "AD21A_N" DIFF_TERM = "TRUE";
-NET "AD21A_N" IOSTANDARD = LVDS_25;
-NET "AD21A_N" LOC = H22;
-NET "AD21A_P" DIFF_TERM = "TRUE";
-NET "AD21A_P" IOSTANDARD = LVDS_25;
-NET "AD21A_P" LOC = J22;
-NET "AD21B_N" DIFF_TERM = "TRUE";
-NET "AD21B_N" IOSTANDARD = LVDS_25;
-NET "AD21B_N" LOC = K22;
-NET "AD21B_P" DIFF_TERM = "TRUE";
-NET "AD21B_P" IOSTANDARD = LVDS_25;
-NET "AD21B_P" LOC = K21;
-NET "AD22A_N" DIFF_TERM = "TRUE";
-NET "AD22A_N" IOSTANDARD = LVDS_25;
-NET "AD22A_N" LOC = L17;
-NET "AD22A_P" DIFF_TERM = "TRUE";
-NET "AD22A_P" IOSTANDARD = LVDS_25;
-NET "AD22A_P" LOC = K17;
-NET "AD22B_N" DIFF_TERM = "TRUE";
-NET "AD22B_N" IOSTANDARD = LVDS_25;
-NET "AD22B_N" LOC = L19;
-NET "AD22B_P" DIFF_TERM = "TRUE";
-NET "AD22B_P" IOSTANDARD = LVDS_25;
-NET "AD22B_P" LOC = L18;
-NET "AD23A_N" DIFF_TERM = "TRUE";
-NET "AD23A_N" IOSTANDARD = LVDS_25;
-NET "AD23A_N" LOC = K20;
-NET "AD23A_P" DIFF_TERM = "TRUE";
-NET "AD23A_P" IOSTANDARD = LVDS_25;
-NET "AD23A_P" LOC = J20;
-NET "AD23B_N" DIFF_TERM = "TRUE";
-NET "AD23B_N" IOSTANDARD = LVDS_25;
-NET "AD23B_N" LOC = J17;
-NET "AD23B_P" DIFF_TERM = "TRUE";
-NET "AD23B_P" IOSTANDARD = LVDS_25;
-NET "AD23B_P" LOC = J18;
-NET "AD24A_N" DIFF_TERM = "TRUE";
-NET "AD24A_N" IOSTANDARD = LVDS_25;
-NET "AD24A_N" LOC = J19;
-NET "AD24A_P" DIFF_TERM = "TRUE";
-NET "AD24A_P" IOSTANDARD = LVDS_25;
-NET "AD24A_P" LOC = K19;
-NET "AD24B_N" DIFF_TERM = "TRUE";
-NET "AD24B_N" IOSTANDARD = LVDS_25;
-NET "AD24B_N" LOC = H21;
-NET "AD24B_P" DIFF_TERM = "TRUE";
-NET "AD24B_P" IOSTANDARD = LVDS_25;
-NET "AD24B_P" LOC = G21;
-NET "AD25A_N" DIFF_TERM = "TRUE";
-NET "AD25A_N" IOSTANDARD = LVDS_25;
-NET "AD25A_N" LOC = H18;
-NET "AD25A_P" DIFF_TERM = "TRUE";
-NET "AD25A_P" IOSTANDARD = LVDS_25;
-NET "AD25A_P" LOC = H17;
-NET "AD25B_N" DIFF_TERM = "TRUE";
-NET "AD25B_N" IOSTANDARD = LVDS_25;
-NET "AD25B_N" LOC = F19;
-NET "AD25B_P" DIFF_TERM = "TRUE";
-NET "AD25B_P" IOSTANDARD = LVDS_25;
-NET "AD25B_P" LOC = G19;
-NET "AD26A_N" DIFF_TERM = "TRUE";
-NET "AD26A_N" IOSTANDARD = LVDS_25;
-NET "AD26A_N" LOC = E22;
-NET "AD26A_P" DIFF_TERM = "TRUE";
-NET "AD26A_P" IOSTANDARD = LVDS_25;
-NET "AD26A_P" LOC = E21;
-NET "AD26B_N" DIFF_TERM = "TRUE";
-NET "AD26B_N" IOSTANDARD = LVDS_25;
-NET "AD26B_N" LOC = D19;
-NET "AD26B_P" DIFF_TERM = "TRUE";
-NET "AD26B_P" IOSTANDARD = LVDS_25;
-NET "AD26B_P" LOC = E19;
-NET "AD27A_N" DIFF_TERM = "TRUE";
-NET "AD27A_N" IOSTANDARD = LVDS_25;
-NET "AD27A_N" LOC = C20;
-NET "AD27A_P" DIFF_TERM = "TRUE";
-NET "AD27A_P" IOSTANDARD = LVDS_25;
-NET "AD27A_P" LOC = B20;
-NET "AD27B_N" DIFF_TERM = "TRUE";
-NET "AD27B_N" IOSTANDARD = LVDS_25;
-NET "AD27B_N" LOC = B21;
-NET "AD27B_P" DIFF_TERM = "TRUE";
-NET "AD27B_P" IOSTANDARD = LVDS_25;
-NET "AD27B_P" LOC = A21;
-NET "AD28A_N" DIFF_TERM = "TRUE";
-NET "AD28A_N" IOSTANDARD = LVDS_25;
-NET "AD28A_N" LOC = F18;
-NET "AD28A_P" DIFF_TERM = "TRUE";
-NET "AD28A_P" IOSTANDARD = LVDS_25;
-NET "AD28A_P" LOC = G18;
-NET "AD28B_N" DIFF_TERM = "TRUE";
-NET "AD28B_N" IOSTANDARD = LVDS_25;
-NET "AD28B_N" LOC = C21;
-NET "AD28B_P" DIFF_TERM = "TRUE";
-NET "AD28B_P" IOSTANDARD = LVDS_25;
-NET "AD28B_P" LOC = B22;
-
-NET "AD31A_N" DIFF_TERM = "TRUE";
-NET "AD31A_N" IOSTANDARD = LVDS_25;
-NET "AD31A_N" LOC = T21;
-NET "AD31A_P" DIFF_TERM = "TRUE";
-NET "AD31A_P" IOSTANDARD = LVDS_25;
-NET "AD31A_P" LOC = U21;
-NET "AD31B_N" DIFF_TERM = "TRUE";
-NET "AD31B_N" IOSTANDARD = LVDS_25;
-NET "AD31B_N" LOC = Y21;
-NET "AD31B_P" DIFF_TERM = "TRUE";
-NET "AD31B_P" IOSTANDARD = LVDS_25;
-NET "AD31B_P" LOC = AA21;
-NET "AD32A_N" DIFF_TERM = "TRUE";
-NET "AD32A_N" IOSTANDARD = LVDS_25;
-NET "AD32A_N" LOC = AB21;
-NET "AD32A_P" DIFF_TERM = "TRUE";
-NET "AD32A_P" IOSTANDARD = LVDS_25;
-NET "AD32A_P" LOC = AB20;
-NET "AD32B_N" DIFF_TERM = "TRUE";
-NET "AD32B_N" IOSTANDARD = LVDS_25;
-NET "AD32B_N" LOC = U20;
-NET "AD32B_P" DIFF_TERM = "TRUE";
-NET "AD32B_P" IOSTANDARD = LVDS_25;
-NET "AD32B_P" LOC = U19;
-NET "AD33A_N" DIFF_TERM = "TRUE";
-NET "AD33A_N" IOSTANDARD = LVDS_25;
-NET "AD33A_N" LOC = W20;
-NET "AD33A_P" DIFF_TERM = "TRUE";
-NET "AD33A_P" IOSTANDARD = LVDS_25;
-NET "AD33A_P" LOC = Y20;
-NET "AD33B_N" DIFF_TERM = "TRUE";
-NET "AD33B_N" IOSTANDARD = LVDS_25;
-NET "AD33B_N" LOC = V21;
-NET "AD33B_P" DIFF_TERM = "TRUE";
-NET "AD33B_P" IOSTANDARD = LVDS_25;
-NET "AD33B_P" LOC = V20;
-NET "AD34A_N" DIFF_TERM = "TRUE";
-NET "AD34A_N" IOSTANDARD = LVDS_25;
-NET "AD34A_N" LOC = AA22;
-NET "AD34A_P" DIFF_TERM = "TRUE";
-NET "AD34A_P" IOSTANDARD = LVDS_25;
-NET "AD34A_P" LOC = Y22;
-NET "AD34B_N" DIFF_TERM = "TRUE";
-NET "AD34B_N" IOSTANDARD = LVDS_25;
-NET "AD34B_N" LOC = T19;
-NET "AD34B_P" DIFF_TERM = "TRUE";
-NET "AD34B_P" IOSTANDARD = LVDS_25;
-NET "AD34B_P" LOC = T18;
-NET "AD35A_N" DIFF_TERM = "TRUE";
-NET "AD35A_N" IOSTANDARD = LVDS_25;
-NET "AD35A_N" LOC = R20;
-NET "AD35A_P" DIFF_TERM = "TRUE";
-NET "AD35A_P" IOSTANDARD = LVDS_25;
-NET "AD35A_P" LOC = R19;
-NET "AD35B_N" DIFF_TERM = "TRUE";
-NET "AD35B_N" IOSTANDARD = LVDS_25;
-NET "AD35B_N" LOC = P17;
-NET "AD35B_P" DIFF_TERM = "TRUE";
-NET "AD35B_P" IOSTANDARD = LVDS_25;
-NET "AD35B_P" LOC = N17;
-NET "AD36A_N" DIFF_TERM = "TRUE";
-NET "AD36A_N" IOSTANDARD = LVDS_25;
-NET "AD36A_N" LOC = R22;
-NET "AD36A_P" DIFF_TERM = "TRUE";
-NET "AD36A_P" IOSTANDARD = LVDS_25;
-NET "AD36A_P" LOC = P22;
-NET "AD36B_N" DIFF_TERM = "TRUE";
-NET "AD36B_N" IOSTANDARD = LVDS_25;
-NET "AD36B_N" LOC = N21;
-NET "AD36B_P" DIFF_TERM = "TRUE";
-NET "AD36B_P" IOSTANDARD = LVDS_25;
-NET "AD36B_P" LOC = N22;
-NET "AD37A_N" DIFF_TERM = "TRUE";
-NET "AD37A_N" IOSTANDARD = LVDS_25;
-NET "AD37A_N" LOC = M19;
-NET "AD37A_P" DIFF_TERM = "TRUE";
-NET "AD37A_P" IOSTANDARD = LVDS_25;
-NET "AD37A_P" LOC = M20;
-NET "AD37B_N" DIFF_TERM = "TRUE";
-NET "AD37B_N" IOSTANDARD = LVDS_25;
-NET "AD37B_N" LOC = L21;
-NET "AD37B_P" DIFF_TERM = "TRUE";
-NET "AD37B_P" IOSTANDARD = LVDS_25;
-NET "AD37B_P" LOC = L22;
-NET "AD38A_N" DIFF_TERM = "TRUE";
-NET "AD38A_N" IOSTANDARD = LVDS_25;
-NET "AD38A_N" LOC = N18;
-NET "AD38A_P" DIFF_TERM = "TRUE";
-NET "AD38A_P" IOSTANDARD = LVDS_25;
-NET "AD38A_P" LOC = M18;
-NET "AD38B_N" DIFF_TERM = "TRUE";
-NET "AD38B_N" IOSTANDARD = LVDS_25;
-NET "AD38B_N" LOC = N20;
-NET "AD38B_P" DIFF_TERM = "TRUE";
-NET "AD38B_P" IOSTANDARD = LVDS_25;
-NET "AD38B_P" LOC = M21;
-
-NET "AD41A_N" DIFF_TERM = "TRUE";
-NET "AD41A_N" IOSTANDARD = LVDS_25;
-NET "AD41A_N" LOC = U8;
-NET "AD41A_P" DIFF_TERM = "TRUE";
-NET "AD41A_P" IOSTANDARD = LVDS_25;
-NET "AD41A_P" LOC = V8;
-NET "AD41B_N" DIFF_TERM = "TRUE";
-NET "AD41B_N" IOSTANDARD = LVDS_25;
-NET "AD41B_N" LOC = Y7;
-NET "AD41B_P" DIFF_TERM = "TRUE";
-NET "AD41B_P" IOSTANDARD = LVDS_25;
-NET "AD41B_P" LOC = Y6;
-NET "AD42A_N" DIFF_TERM = "TRUE";
-NET "AD42A_N" IOSTANDARD = LVDS_25;
-NET "AD42A_N" LOC = T7;
-NET "AD42A_P" DIFF_TERM = "TRUE";
-NET "AD42A_P" IOSTANDARD = LVDS_25;
-NET "AD42A_P" LOC = T6;
-NET "AD42B_N" DIFF_TERM = "TRUE";
-NET "AD42B_N" IOSTANDARD = LVDS_25;
-NET "AD42B_N" LOC = AA6;
-NET "AD42B_P" DIFF_TERM = "TRUE";
-NET "AD42B_P" IOSTANDARD = LVDS_25;
-NET "AD42B_P" LOC = AB6;
-NET "AD43A_N" DIFF_TERM = "TRUE";
-NET "AD43A_N" IOSTANDARD = LVDS_25;
-NET "AD43A_N" LOC = W7;
-NET "AD43A_P" DIFF_TERM = "TRUE";
-NET "AD43A_P" IOSTANDARD = LVDS_25;
-NET "AD43A_P" LOC = V7;
-NET "AD43B_N" DIFF_TERM = "TRUE";
-NET "AD43B_N" IOSTANDARD = LVDS_25;
-NET "AD43B_N" LOC = AB8;
-NET "AD43B_P" DIFF_TERM = "TRUE";
-NET "AD43B_P" IOSTANDARD = LVDS_25;
-NET "AD43B_P" LOC = AB9;
-NET "AD44A_N" DIFF_TERM = "TRUE";
-NET "AD44A_N" IOSTANDARD = LVDS_25;
-NET "AD44A_N" LOC = V6;
-NET "AD44A_P" DIFF_TERM = "TRUE";
-NET "AD44A_P" IOSTANDARD = LVDS_25;
-NET "AD44A_P" LOC = U6;
-NET "AD44B_N" DIFF_TERM = "TRUE";
-NET "AD44B_N" IOSTANDARD = LVDS_25;
-NET "AD44B_N" LOC = W8;
-NET "AD44B_P" DIFF_TERM = "TRUE";
-NET "AD44B_P" IOSTANDARD = LVDS_25;
-NET "AD44B_P" LOC = W9;
-NET "AD45A_N" DIFF_TERM = "TRUE";
-NET "AD45A_N" IOSTANDARD = LVDS_25;
-NET "AD45A_N" LOC = T8;
-NET "AD45A_P" DIFF_TERM = "TRUE";
-NET "AD45A_P" IOSTANDARD = LVDS_25;
-NET "AD45A_P" LOC = R9;
-NET "AD45B_N" DIFF_TERM = "TRUE";
-NET "AD45B_N" IOSTANDARD = LVDS_25;
-NET "AD45B_N" LOC = Y11;
-NET "AD45B_P" DIFF_TERM = "TRUE";
-NET "AD45B_P" IOSTANDARD = LVDS_25;
-NET "AD45B_P" LOC = AA11;
-NET "AD46A_N" DIFF_TERM = "TRUE";
-NET "AD46A_N" IOSTANDARD = LVDS_25;
-NET "AD46A_N" LOC = Y10;
-NET "AD46A_P" DIFF_TERM = "TRUE";
-NET "AD46A_P" IOSTANDARD = LVDS_25;
-NET "AD46A_P" LOC = W10;
-NET "AD46B_N" DIFF_TERM = "TRUE";
-NET "AD46B_N" IOSTANDARD = LVDS_25;
-NET "AD46B_N" LOC = V11;
-NET "AD46B_P" DIFF_TERM = "TRUE";
-NET "AD46B_P" IOSTANDARD = LVDS_25;
-NET "AD46B_P" LOC = U11;
-NET "AD47A_N" DIFF_TERM = "TRUE";
-NET "AD47A_N" IOSTANDARD = LVDS_25;
-NET "AD47A_N" LOC = T11;
-NET "AD47A_P" DIFF_TERM = "TRUE";
-NET "AD47A_P" IOSTANDARD = LVDS_25;
-NET "AD47A_P" LOC = T12;
-NET "AD47B_N" DIFF_TERM = "TRUE";
-NET "AD47B_N" IOSTANDARD = LVDS_25;
-NET "AD47B_N" LOC = W12;
-NET "AD47B_P" DIFF_TERM = "TRUE";
-NET "AD47B_P" IOSTANDARD = LVDS_25;
-NET "AD47B_P" LOC = V12;
-NET "AD48A_N" DIFF_TERM = "TRUE";
-NET "AD48A_N" IOSTANDARD = LVDS_25;
-NET "AD48A_N" LOC = U10;
-NET "AD48A_P" DIFF_TERM = "TRUE";
-NET "AD48A_P" IOSTANDARD = LVDS_25;
-NET "AD48A_P" LOC = T9;
-NET "AD48B_N" DIFF_TERM = "TRUE";
-NET "AD48B_N" IOSTANDARD = LVDS_25;
-NET "AD48B_N" LOC = AA12;
-NET "AD48B_P" DIFF_TERM = "TRUE";
-NET "AD48B_P" IOSTANDARD = LVDS_25;
-NET "AD48B_P" LOC = Y12;
-
-NET "DATAu" LOC = B10;
-NET "CLKu" LOC = A11;
-NET "RDu" LOC = C10;
-NET "LEu" LOC = A12;
-NET "SYNC" LOC = G11;
-
-NET "S_CTRL" LOC = W14;
-NET "T_CTRL" LOC = Y14;
-NET "GEO" LOC = AB13;
-
-#
-NET "SCK" LOC = W17;
-NET "SDI" LOC = W18;
-NET "CSA[1]" LOC = AA17;
-NET "CSA[2]" LOC = AB18;
-NET "CSA[3]" LOC = V18;
-NET "CSA[4]" LOC = T16;
-NET "CSB[1]" LOC = Y17;
-NET "CSB[2]" LOC = AA18;
-NET "CSB[3]" LOC = V17;
-NET "CSB[4]" LOC = R16;
-
-NET "SDOA[1]" LOC = Y16;
-NET "SDOA[2]" LOC = AA19;
-NET "SDOA[3]" LOC = V13;
-NET "SDOA[4]" LOC = T17;
-NET "SDOB[1]" LOC = AA16;
-NET "SDOB[2]" LOC = AB19;
-NET "SDOB[3]" LOC = W13;
-NET "SDOB[4]" LOC = U18;
-
-#
-#NET "D<0>"   LOC = "V15";
-#NET "D<1>"   LOC = "U15";
-#NET "D<2>"   LOC = "R15";
-#NET "D<3>"   LOC = "R14";
-#NET "D<4>"   LOC = "Y19";
-#NET "D<5>"   LOC = "W19";
-#NET "D<6>"   LOC = "U16";
-#NET "D<7>"   LOC = "V16";
-NET "DCOA1_N" DIFF_TERM = "TRUE";
-NET "DCOA1_N" IOSTANDARD = LVDS_25;
-NET "DCOA1_N" LOC = F16;
-NET "DCOA1_P" DIFF_TERM = "TRUE";
-NET "DCOA1_P" IOSTANDARD = LVDS_25;
-NET "DCOA1_P" LOC = E16;
-NET "DCOA2_N" DIFF_TERM = "TRUE";
-NET "DCOA2_N" IOSTANDARD = LVDS_25;
-NET "DCOA2_N" LOC = D22;
-NET "DCOA2_P" DIFF_TERM = "TRUE";
-NET "DCOA2_P" IOSTANDARD = LVDS_25;
-NET "DCOA2_P" LOC = C22;
-NET "DCOA3_N" DIFF_TERM = "TRUE";
-NET "DCOA3_N" IOSTANDARD = LVDS_25;
-NET "DCOA3_N" LOC = P20;
-NET "DCOA3_P" DIFF_TERM = "TRUE";
-NET "DCOA3_P" IOSTANDARD = LVDS_25;
-NET "DCOA3_P" LOC = P19;
-NET "DCOA4_N" DIFF_TERM = "TRUE";
-NET "DCOA4_N" IOSTANDARD = LVDS_25;
-NET "DCOA4_N" LOC = Y9;
-NET "DCOA4_P" DIFF_TERM = "TRUE";
-NET "DCOA4_P" IOSTANDARD = LVDS_25;
-NET "DCOA4_P" LOC = AA9;
-NET "DCOB1_N" DIFF_TERM = "TRUE";
-NET "DCOB1_N" IOSTANDARD = LVDS_25;
-NET "DCOB1_N" LOC = B19;
-NET "DCOB1_P" DIFF_TERM = "TRUE";
-NET "DCOB1_P" IOSTANDARD = LVDS_25;
-NET "DCOB1_P" LOC = A19;
-NET "DCOB2_N" DIFF_TERM = "TRUE";
-NET "DCOB2_N" IOSTANDARD = LVDS_25;
-NET "DCOB2_N" LOC = E20;
-NET "DCOB2_P" DIFF_TERM = "TRUE";
-NET "DCOB2_P" IOSTANDARD = LVDS_25;
-NET "DCOB2_P" LOC = D20;
-NET "DCOB3_N" DIFF_TERM = "TRUE";
-NET "DCOB3_N" IOSTANDARD = LVDS_25;
-NET "DCOB3_N" LOC = V22;
-NET "DCOB3_P" DIFF_TERM = "TRUE";
-NET "DCOB3_P" IOSTANDARD = LVDS_25;
-NET "DCOB3_P" LOC = W22;
-NET "DCOB4_N" DIFF_TERM = "TRUE";
-NET "DCOB4_N" IOSTANDARD = LVDS_25;
-NET "DCOB4_N" LOC = AA8;
-NET "DCOB4_P" DIFF_TERM = "TRUE";
-NET "DCOB4_P" IOSTANDARD = LVDS_25;
-NET "DCOB4_P" LOC = AA7;
-
-NET "FRA1_N" DIFF_TERM = "TRUE";
-NET "FRA1_N" IOSTANDARD = LVDS_25;
-NET "FRA1_N" LOC = C15;
-NET "FRA1_P" DIFF_TERM = "TRUE";
-NET "FRA1_P" IOSTANDARD = LVDS_25;
-NET "FRA1_P" LOC = B15;
-NET "FRA2_N" DIFF_TERM = "TRUE";
-NET "FRA2_N" IOSTANDARD = LVDS_25;
-NET "FRA2_N" LOC = G20;
-NET "FRA2_P" DIFF_TERM = "TRUE";
-NET "FRA2_P" IOSTANDARD = LVDS_25;
-NET "FRA2_P" LOC = H20;
-NET "FRA3_N" DIFF_TERM = "TRUE";
-NET "FRA3_N" IOSTANDARD = LVDS_25;
-NET "FRA3_N" LOC = R17;
-NET "FRA3_P" DIFF_TERM = "TRUE";
-NET "FRA3_P" IOSTANDARD = LVDS_25;
-NET "FRA3_P" LOC = P18;
-NET "FRA4_N" DIFF_TERM = "TRUE";
-NET "FRA4_N" IOSTANDARD = LVDS_25;
-NET "FRA4_N" LOC = U9;
-NET "FRA4_P" DIFF_TERM = "TRUE";
-NET "FRA4_P" IOSTANDARD = LVDS_25;
-NET "FRA4_P" LOC = V10;
-NET "FRB1_N" DIFF_TERM = "TRUE";
-NET "FRB1_N" IOSTANDARD = LVDS_25;
-NET "FRB1_N" LOC = E15;
-NET "FRB1_P" DIFF_TERM = "TRUE";
-NET "FRB1_P" IOSTANDARD = LVDS_25;
-NET "FRB1_P" LOC = D15;
-NET "FRB2_N" DIFF_TERM = "TRUE";
-NET "FRB2_N" IOSTANDARD = LVDS_25;
-NET "FRB2_N" LOC = F22;
-NET "FRB2_P" DIFF_TERM = "TRUE";
-NET "FRB2_P" IOSTANDARD = LVDS_25;
-NET "FRB2_P" LOC = F21;
-NET "FRB3_N" DIFF_TERM = "TRUE";
-NET "FRB3_N" IOSTANDARD = LVDS_25;
-NET "FRB3_N" LOC = T22;
-NET "FRB3_P" DIFF_TERM = "TRUE";
-NET "FRB3_P" IOSTANDARD = LVDS_25;
-NET "FRB3_P" LOC = R21;
-NET "FRB4_N" DIFF_TERM = "TRUE";
-NET "FRB4_N" IOSTANDARD = LVDS_25;
-NET "FRB4_N" LOC = AB10;
-NET "FRB4_P" DIFF_TERM = "TRUE";
-NET "FRB4_P" IOSTANDARD = LVDS_25;
-NET "FRB4_P" LOC = AB11;
-
-NET "GCLK_N" DIFF_TERM = "TRUE";
-NET "GCLK_N" IOSTANDARD = LVDS_25;
-NET "GCLK_N" LOC = U13;
-NET "GCLK_P" DIFF_TERM = "TRUE";
-NET "GCLK_P" IOSTANDARD = LVDS_25;
-NET "GCLK_P" LOC = T13;
-
-
-NET "INTCOM0_N"   LOC = "A6";
-NET "INTCOM0_P"   LOC = "A7";
-NET "INTCOM1_N"   LOC = "B6";
-NET "INTCOM1_P"   LOC = "C6";
-NET "INTCOM2_N"   LOC = "H10";
-NET "INTCOM2_P"   LOC = "G10";
-NET "INTCOM3_N"   LOC = "D9";
-NET "INTCOM3_P"   LOC = "E9";
-NET "INTCOM4_N"   LOC = "G9";
-NET "INTCOM4_P"   LOC = "F9";
-NET "INTCOM5_N"   LOC = "E6";
-NET "INTCOM5_P"   LOC = "E7";
-NET "INTCOM6_N"   LOC = "F11";
-NET "INTCOM6_P"   LOC = "E11";
-NET "INTCOM7_N"   LOC = "F7";
-NET "INTCOM7_P"   LOC = "F8";
-
-NET "INTCOMC1_N"   LOC = "C7";
-#NET "INTCOMC1_N" DIFF_TERM = "TRUE";
-#NET "INTCOMC1_N" IOSTANDARD = BLVDS_25;
-NET "INTCOMC1_P"   LOC = "C8";
-#NET "INTCOMC1_P" DIFF_TERM = "TRUE";
-#NET "INTCOMC1_P" IOSTANDARD = BLVDS_25;
-NET "INTCOMC2_N"   LOC = "D7";
-#NET "INTCOMC2_N" DIFF_TERM = "TRUE";
-#NET "INTCOMC2_N" IOSTANDARD = BLVDS_25;
-NET "INTCOMC2_P"   LOC = "D8";
-#NET "INTCOMC2_P" DIFF_TERM = "TRUE";
-#NET "INTCOMC2_P" IOSTANDARD = BLVDS_25;
-
-
-NET "TCK_F"   LOC = "AA14";
-NET "TDI_F"   LOC = "AB16";
-NET "TDO_F"   LOC = "AB15";
-NET "TMS_F"   LOC = "AB14";
-
-
-
-#
-#NET "SM0_N"   LOC = "B11";
-#NET "SM0_P"   LOC = "C11";
-NET "SM1_N"   LOC = "B9";
-NET "SM1_P"   LOC = "A9";
-#NET "SM2_N"   LOC = "E10";
-#NET "SM2_P"   LOC = "D10";
-NET "SM3_N"   LOC = "B8";
-NET "SM3_P"   LOC = "A8";
-#
-#
-#NET "TEMP_IN"   LOC = "U14";
-#NET "TEMP_OUT"   LOC = "T14";
-#
-#NET "RX_N"   LOC = "T2";
-#NET "RX_P"   LOC = "T1";
-#NET "TX_N"   LOC = "V2";
-#NET "TX_P"   LOC = "V1";
-NET "MOD_DEF[0]" LOC = G8;
-NET "MOD_DEF[1]" LOC = H8;
-NET "MOD_DEF[2]" LOC = D12;
-NET "TX_DIS" LOC = H11;
-NET "LOS" LOC = C12;
-
-NET "MGTREFCLK_N" LOC = L3;
-NET "MGTREFCLK_P" LOC = L4;
-NET "RCV_CLK_N" LOC = Y15;
-NET "RCV_CLK_P" LOC = W15;
-NET "ST_CLK_N" LOC = G6;
-NET "ST_CLK_P" LOC = F6;
-NET "RX_N" LOC = G4;
-NET "RX_P" LOC = G3;
-NET "TX_N" LOC = K2;
-NET "TX_P" LOC = K1;
-
-#NET "PROGRAM_B" LOC = F5;
-
-#
-#NET "XRX0_N"   LOC = "E4";
-#NET "XRX0_P"   LOC = "E3";
-#NET "XRX1_N"   LOC = "C4";
-#NET "XRX1_P"   LOC = "C3";
-#NET "XTX0_N"   LOC = "H2";
-#NET "XTX0_P"   LOC = "H1";
-#NET "XTX1_N"   LOC = "F2";
-#NET "XTX1_P"   LOC = "F1";
-#Created by Constraints Editor (xc6vlx130t-ff484-3) - 2012/07/23
-#NET "DCOA1_P" TNM_NET = DCOA1_P;
-#TIMESPEC TS_DCOA1_P = PERIOD "DCOA1_P" 3.125 ns HIGH 50%;
-#NET "DCOA2_P" TNM_NET = DCOA2_P;
-#TIMESPEC TS_DCOA2_P = PERIOD "DCOA2_P" 3.125 ns HIGH 50%;
-#NET "DCOA3_P" TNM_NET = DCOA3_P;
-#TIMESPEC TS_DCOA3_P = PERIOD "DCOA3_P" 3.125 ns HIGH 50%;
-#NET "DCOA4_P" TNM_NET = DCOA4_P;
-#TIMESPEC TS_DCOA4_P = PERIOD "DCOA4_P" 3.125 HIGH 50%;
-#NET "DCOB1_P" TNM_NET = DCOB1_P;
-#TIMESPEC TS_DCOB1_P = PERIOD "DCOB1_P" 3.125 ns HIGH 50%;
-#NET "DCOB2_P" TNM_NET = DCOB2_P;
-#TIMESPEC TS_DCOB2_P = PERIOD "DCOB2_P" 3.125 ns HIGH 50%;
-#NET "DCOB3_P" TNM_NET = DCOB3_P;
-#TIMESPEC TS_DCOB3_P = PERIOD "DCOB3_P" 3.125 ns HIGH 50%;
-#NET "DCOB4_P" TNM_NET = DCOB4_P;
-#TIMESPEC TS_DCOB4_P = PERIOD "DCOB4_P" 3.125 ns HIGH 50%;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" MAXSKEW = 100 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" MAXSKEW = 100 ps;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" MAXDELAY = 500 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" MAXDELAY = 500 ps;
-
-#390
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" MAXDELAY = 750 ps;
-
-# half of real frequency because of synchronisation with falling edge
-#NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv";
-#TIMESPEC TS_AdcToplevel1458_1_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" 12.5 ns HIGH 50 %;
-#NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv";
-#TIMESPEC TS_AdcToplevel2356_1_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" 12.5 ns HIGH 50 %;
-#
-#NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv";
-#TIMESPEC TS_AdcToplevel1458_2_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" 12.5 ns HIGH 50 %;
-#NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv";
-#TIMESPEC TS_AdcToplevel2356_2_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" 12.5 ns HIGH 50 %;
-#
-#NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv";
-#TIMESPEC TS_AdcToplevel1458_3_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" 12.5 ns HIGH 50 %;
-#NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv";
-#TIMESPEC TS_AdcToplevel2356_3_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" 12.5 ns HIGH 50 %;
-#
-#NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv";
-#TIMESPEC TS_AdcToplevel1458_4_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" 12.5 ns HIGH 50 %;
-#NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv";
-#TIMESPEC TS_AdcToplevel2356_4_IntClkDiv = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" 12.5 ns HIGH 50 %;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk";
-TIMESPEC TS_AdcToplevel1458_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClk" 3 ns HIGH 50 %;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk";
-TIMESPEC TS_AdcToplevel2356_1_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClk" 3 ns HIGH 50 %;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk";
-TIMESPEC TS_AdcToplevel1458_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClk" 3 ns HIGH 50 %;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk";
-TIMESPEC TS_AdcToplevel2356_2_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClk" 3 ns HIGH 50 %;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk";
-TIMESPEC TS_AdcToplevel1458_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClk" 3 ns HIGH 50 %;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk";
-TIMESPEC TS_AdcToplevel2356_3_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClk" 3 ns HIGH 50 %;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk";
-TIMESPEC TS_AdcToplevel1458_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClk" 3 ns HIGH 50 %;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" TNM_NET = "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk";
-TIMESPEC TS_AdcToplevel2356_4_IntClk = PERIOD "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClk" 3 ns HIGH 50 %;
-
-
-#NET "ADC_clk_S" TNM_NET = "ADC_clk_S";
-#TIMESPEC TS_ADC_clk_S = PERIOD "ADC_clk_S" 12.5 ns HIGH 50 %;
-#NET "ADC_clk_S" MAXDELAY = 1.6 ns;
-#NET "ADC_clk_S" MAXSKEW = 1.6 ns;
-#NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "FEE_ADCinput_module1/ADC_clknot_S";
-#TIMESPEC TS_clknot_S = PERIOD "FEE_ADCinput_module1/ADC_clknot_S" 12.5 ns HIGH 50 %;
-#NET "FEE_ADCinput_module1/ADC_clknot_S" MAXDELAY = 1.6 ns;
-#NET "FEE_ADCinput_module1/ADC_clknot_S" MAXSKEW = 1.6 ns;
-#
-#TIMESPEC TS_AdcToplevel1458_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TO "ADC_clk_S" 4.5 ns;
-#
-#TIMESPEC TS_AdcToplevel1458_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel1458_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_A_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_B_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_C_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-#TIMESPEC TS_AdcToplevel2356_D_IntClkDiv = FROM "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TO "FEE_ADCinput_module1/ADC_clknot_S" 4.5 ns;
-
-NET "ADC_clk_S" TNM_NET = "ADC_clk_S_clk";
-TIMESPEC TS_ADC_clk_S_clk = PERIOD "ADC_clk_S_clk" 12.5 ns HIGH 50 %;
-NET "ADC_clk_S" TNM_NET = "ADC_clk_S_net";
-NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "ADC_clknot_S_clk";
-TIMESPEC TS_ADC_clknot_S_clk = PERIOD "ADC_clknot_S_clk" 12.5 ns HIGH 50 %;
-NET "FEE_ADCinput_module1/ADC_clknot_S" TNM_NET = "ADC_clknot_S_net";
-
-NET "ADC_clk_S" MAXDELAY = 1.6 ns;
-NET "ADC_clk_S" MAXSKEW = 1 ns;
-NET "FEE_ADCinput_module1/ADC_clknot_S" MAXDELAY = 1.4 ns;
-NET "FEE_ADCinput_module1/ADC_clknot_S" MAXSKEW = 1 ns;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1458_1_per";
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv1458_2_per";
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv1458_3_per";
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv1458_4_per";
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv2356_1_per";
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv2356_2_per";
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv2356_3_per";
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv2356_4_per";
-
-TIMESPEC TS_AdcToplevel1458_1_IntClkDiv_per = PERIOD "IntClkDiv1458_1_per" 12.5 ns HIGH 50 %;
-TIMESPEC TS_AdcToplevel1458_2_IntClkDiv_per = PERIOD "IntClkDiv1458_2_per" 12.5 ns HIGH 50 %;
-TIMESPEC TS_AdcToplevel1458_3_IntClkDiv_per = PERIOD "IntClkDiv1458_3_per" 12.5 ns HIGH 50 %;
-TIMESPEC TS_AdcToplevel1458_4_IntClkDiv_per = PERIOD "IntClkDiv1458_4_per" 12.5 ns HIGH 50 %;
-TIMESPEC TS_AdcToplevel2356_1_IntClkDiv_per = PERIOD "IntClkDiv2356_1_per" 12.5 ns HIGH 50 %;
-TIMESPEC TS_AdcToplevel2356_2_IntClkDiv_per = PERIOD "IntClkDiv2356_2_per" 12.5 ns HIGH 50 %;
-TIMESPEC TS_AdcToplevel2356_3_IntClkDiv_per = PERIOD "IntClkDiv2356_3_per" 12.5 ns HIGH 50 %;
-TIMESPEC TS_AdcToplevel2356_4_IntClkDiv_per = PERIOD "IntClkDiv2356_4_per" 12.5 ns HIGH 50 %;
-
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/IntClkDiv" TNM_NET = "IntClkDiv1458_1_net";
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/IntClkDiv" TNM_NET = "IntClkDiv1458_2_net";
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/IntClkDiv" TNM_NET = "IntClkDiv1458_3_net";
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/IntClkDiv" TNM_NET = "IntClkDiv1458_4_net";
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/IntClkDiv" TNM_NET = "IntClkDiv2356_1_net";
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/IntClkDiv" TNM_NET = "IntClkDiv2356_2_net";
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/IntClkDiv" TNM_NET = "IntClkDiv2356_3_net";
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/IntClkDiv" TNM_NET = "IntClkDiv2356_4_net";
-
-TIMESPEC TS_AdcToplevel1458_1_IntClkDiv_net = FROM "IntClkDiv1458_1_net" TO "ADC_clknot_S_net" 4 ns;
-TIMESPEC TS_AdcToplevel1458_2_IntClkDiv_net = FROM "IntClkDiv1458_2_net" TO "ADC_clknot_S_net" 4 ns;
-TIMESPEC TS_AdcToplevel1458_3_IntClkDiv_net = FROM "IntClkDiv1458_3_per" TO "ADC_clknot_S_net" 4 ns;
-TIMESPEC TS_AdcToplevel1458_4_IntClkDiv_net = FROM "IntClkDiv1458_4_per" TO "ADC_clknot_S_net" 4 ns;
-TIMESPEC TS_AdcToplevel2356_1_IntClkDiv_net = FROM "IntClkDiv2356_1_per" TO "ADC_clknot_S_net" 4 ns;
-TIMESPEC TS_AdcToplevel2356_2_IntClkDiv_net = FROM "IntClkDiv2356_2_per" TO "ADC_clknot_S_net" 4 ns;
-TIMESPEC TS_AdcToplevel2356_3_IntClkDiv_net = FROM "IntClkDiv2356_3_per" TO "ADC_clknot_S_net" 4 ns;
-TIMESPEC TS_AdcToplevel2356_4_IntClkDiv_net = FROM "IntClkDiv2356_4_per" TO "ADC_clknot_S_net" 4 ns;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXSKEW = 300 ps;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/AdcToplevel_I_AdcFrame/Frame_out_S" MAXDELAY = 870 ps;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/reset_clockdiv_S" MAXSKEW = 250 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/reset_clockdiv_S" MAXSKEW = 250 ps;
-
-NET "FEE_ADCinput_module1/AdcTopleveL1458_1/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_2/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_3/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL1458_4/reset_clockdiv_S" MAXDELAY = 750 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_1/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_2/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_3/reset_clockdiv_S" MAXDELAY = 850 ps;
-NET "FEE_ADCinput_module1/AdcTopleveL2356_4/reset_clockdiv_S" MAXDELAY = 850 ps;
-
-
-NET "FEE_ADCinput_module1/FRA1_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA1_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA2_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA2_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA3_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA3_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA4_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRA4_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB1_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB1_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB2_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB2_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB3_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB3_N_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB4_P_S" MAXDELAY = 20 ps;
-NET "FEE_ADCinput_module1/FRB4_N_S" MAXDELAY = 20 ps;
-
-NET "ST_CLK_P" TNM_NET = "ST_CLK_P";
-TIMESPEC TS_ST_CLK_P = PERIOD "ST_CLK_P" 6.43 ns HIGH 50 %;
-NET "ST_CLK_N" TNM_NET = "ST_CLK_N";
-TIMESPEC TS_ST_CLK_N = PERIOD "ST_CLK_N" 6.43 ns HIGH 50 %;
-
-INST "*AdcClock/AdcClock_I_Isrds_*" TNM =  FFS "AdcClk_Isrds";
-INST "*AdcFrame/AdcFrame_I_Isrds_*" TNM =  FFS "AdcFrm_Isrds";
-INST "*AdcData/AdcData_I_Isrds_*" TNM =  FFS "AdcDat_Isrds";
-INST "*AdcClock/*" TNM =  FFS "AdcClk_Ffs";
-INST "*AdcFrame/*" TNM =  FFS "AdcFrm_Ffs";
-INST "*AdcData/*" TNM =  FFS "AdcDat_Ffs";
-TIMESPEC TS_ClkIsrds_ClkFfs = FROM "AdcClk_Isrds" TO "AdcClk_Ffs" 2.4 ns;
-TIMESPEC TS_FrmIsrds_FrmFfs = FROM "AdcFrm_Isrds" TO "AdcFrm_Ffs" 2.4 ns;
-TIMESPEC TS_DatIsrds_DatFfs = FROM "AdcDat_Isrds" TO "AdcDat_Ffs" 2.4 ns;
-
-NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S_clk";
-TIMESPEC TS_clock_ADCref_S_clk = PERIOD "clock_ADCref_S_clk" 12.5 ns HIGH 50 %;
-NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S_net";
-
-NET "ST_CLK_S" TNM_NET = "ST_CLK_S_clk";
-TIMESPEC TS_ST_CLK_S_clk = PERIOD "ST_CLK_S_clk" 6.43 ns HIGH 50 %;
-NET "ST_CLK_S" TNM_NET = "ST_CLK_S_net";
-
-NET "GCLK_S" TNM_NET = "GCLK_S_clk";
-TIMESPEC TS_GCLK_S_clk = PERIOD "GCLK_S_clk" 12.5 ns HIGH 50 %;
-NET "GCLK_S" TNM_NET = "GCLK_S_net";
-
-#NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S";
-#TIMESPEC TS_rxSodaClk_S_clk = PERIOD "rxSodaClk_S_clk" 6.25 ns HIGH 50 %;
-#NET "rxSodaClk_S" TNM_NET = "rxSodaClk_S_net";
-
-NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "rxSodaClk_S";
-TIMESPEC TS_rxSodaClk_S_clk = PERIOD "rxSodaClk_S_clk" 6.25 ns HIGH 50 %;
-NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "rxSodaClk_S_net";
-
-
-TIMESPEC TS_ADC_to_ADC = FROM "clock_ADCref_S_net" TO "clock_ADCref_S_net" 12.5 ns;
-TIMESPEC TS_ST_to_ST = FROM "ST_CLK_S_net" TO "ST_CLK_S_net" 6.43 ns;
-TIMESPEC TS_G_to_G = FROM "GCLK_S_net" TO "GCLK_S_net" 12.5 ns;
-TIMESPEC TS_SODA_to_SODA = FROM "rxSodaClk_S_net" TO "rxSodaClk_S_net" 6.25 ns;
-
-
-TIMESPEC TS_ADC_to_ST = FROM "clock_ADCref_S_net" TO "ST_CLK_S_net" TIG;
-TIMESPEC TS_ST_to_ADC = FROM "ST_CLK_S_net" TO "clock_ADCref_S_net" TIG;
-TIMESPEC TS_G_to_ST = FROM "GCLK_S_net" TO "ST_CLK_S_net" TIG;
-TIMESPEC TS_SODA_to_ST = FROM "rxSodaClk_S_net" TO "ST_CLK_S_net" TIG;
-TIMESPEC TS_SODA_to_G = FROM "rxSodaClk_S_net" TO "GCLK_S_net" TIG;
-TIMESPEC TS_SODA_to_ADC = FROM "rxSodaClk_S_net" TO "clock_ADCref_S_net" TIG;
-
-#NET "ST_CLK_S" TNM_NET = "ST_CLK_S";
-#NET "GCLK_S" TNM_NET = "GCLK_S";
-#NET "clock_ADCref_S" TNM_NET = "clock_ADCref_S";
-##NET "clock125Mhz_S" TNM_NET = "clock125MHz_S";
-#NET "clock200Mhz_S" TNM_NET = "clock200MHz_S";
-##NET "clock100Mhz_S" TNM_NET = "clock100MHz_S";
-#
-##TIMESPEC TS_125M_to_ref = FROM "clock125MHz_S" TO "clock_ADCref_S" TIG;
-##TIMESPEC TS_ref_to_125M = FROM "clock_ADCref_S" TO "clock125MHz_S" TIG;
-#TIMESPEC TS_GCLK_to_ref = FROM "GCLK_S" TO "clock_ADCref_S" TIG;
-#TIMESPEC TS_ref_to_GCLK = FROM "clock_ADCref_S" TO "GCLK_S" TIG;
-##TIMESPEC TS_GCLK_to_125M = FROM "GCLK_S" TO "clock125MHz_S" TIG;
-##TIMESPEC TS_125M_to_GCLK = FROM "clock125MHz_S" TO "GCLK_S" TIG;
-#
-#
-##TIMESPEC TS_62M5_to_100M = FROM "clock62M5Hz_S" TO "clock100MHz_S" TIG;
-##TIMESPEC TS_100M_to_62M5 = FROM "clock100MHz_S" TO "clock62M5Hz_S" TIG;
-##TIMESPEC TS_125M_to_100M = FROM "clock125MHz_S" TO "clock100MHz_S" TIG;
-##TIMESPEC TS_100M_to_125M = FROM "clock100MHz_S" TO "clock125MHz_S" TIG;
-#
-#TIMESPEC TS_ref_to_200M = FROM "clock62M5Hz_S" TO "clock200MHz_S" TIG;
-#TIMESPEC TS_200M_to_ref = FROM "clock200MHz_S" TO "clock62M5Hz_S" TIG;
-#TIMESPEC TS_GCLK_to_200M = FROM "GCLK_S" TO "clock200MHz_S" TIG;
-#TIMESPEC TS_200M_to_GCLK = FROM "clock200MHz_S" TO "GCLK_S" TIG;
-##TIMESPEC TS_125M_to_200M = FROM "clock125MHz_S" TO "clock200MHz_S" TIG;
-##TIMESPEC TS_200M_to_125M = FROM "clock200MHz_S" TO "clock125MHz_S" TIG;
-#
-#TIMESPEC TS_ref_to_ST_CLK = FROM "clock_ADCref_S" TO "ST_CLK_S" TIG;
-#TIMESPEC TS_ST_CLK_to_ref = FROM "ST_CLK_S" TO "clock_ADCref_S" TIG;
-#TIMESPEC TS_GCLK_to_ST_CLK = FROM "GCLK_S" TO "ST_CLK_S" TIG;
-#TIMESPEC TS_ST_CLK_to_GCLK = FROM "ST_CLK_S" TO "GCLK_S" TIG;
-##TIMESPEC TS_125M_to_ST_CLK = FROM "clock125MHz_S" TO "ST_CLK_S" TIG;
-##TIMESPEC TS_ST_CLK_to_125M = FROM "ST_CLK_S" TO "clock125MHz_S" TIG;
-#TIMESPEC TS_200M_to_ST_CLK = FROM "clock200MHz_S" TO "ST_CLK_S" TIG;
-#TIMESPEC TS_ST_CLK_to_200M = FROM "ST_CLK_S" TO "clock200MHz_S" TIG;
-#
-#NET "ST_CLK_S_BUFG" TNM_NET = "ST_CLK_S_BUFG";
-#TIMESPEC TS_ref_to_ST_CLK_BUFG = FROM "clock_ADCref_S" TO "ST_CLK_S_BUFG" TIG;
-#TIMESPEC TS_ST_CLK_BUFG_to_ref = FROM "ST_CLK_S_BUFG" TO "clock_ADCref_S" TIG;
-#TIMESPEC TS_GCLK_to_ST_CLK_BUFG = FROM "GCLK_S" TO "ST_CLK_S_BUFG" TIG;
-#TIMESPEC TS_ST_CLK_BUFG_to_GCLK = FROM "ST_CLK_S_BUFG" TO "GCLK_S" TIG;
-##TIMESPEC TS_125M_to_ST_CLK_BUFG = FROM "clock125MHz_S" TO "ST_CLK_S_BUFG" TIG;
-##TIMESPEC TS_ST_CLK_BUFG_to_125M = FROM "ST_CLK_S_BUFG" TO "clock125MHz_S" TIG;
-#TIMESPEC TS_200M_to_ST_CLK_BUFG = FROM "clock200MHz_S" TO "ST_CLK_S_BUFG" TIG;
-#TIMESPEC TS_ST_CLK_BUFG_to_200M = FROM "ST_CLK_S_BUFG" TO "clock200MHz_S" TIG;
-
-#TIMESPEC TS_62M5_to_txUsrClk2 = FROM "clock62M5Hz_S" TO "FEE_gtxModule1/txUsrClk2_S" 20 ns;
-#TIMESPEC TS_txUsrClk2_to_62M5 = FROM "FEE_gtxModule1/txUsrClk2_S" TO "clock62M5Hz_S" 20 ns;
-
-NET "GCLK_P" TNM_NET = "GCLK_P";
-TIMESPEC TS_GCLK_P = PERIOD "GCLK_P" 12.5 ns HIGH 50 %;
-NET "GCLK_N" TNM_NET = "GCLK_N";
-TIMESPEC TS_GCLK_N = PERIOD "GCLK_N" 12.5 ns HIGH 50 %;
-
-NET "MGTREFCLK_P" TNM_NET = "MGTREFCLK_P";
-TIMESPEC TS_MGTREFCLK_P = PERIOD "MGTREFCLK_P" 12.5 ns HIGH 50 %;
-NET "MGTREFCLK_N" TNM_NET = "MGTREFCLK_N";
-TIMESPEC TS_MGTREFCLK_N = PERIOD "MGTREFCLK_N" 12.5 ns HIGH 50 %;
-
-NET "FEE_gtxModule1/txUsrClk_S" TNM_NET = "FEE_gtxModule1/txUsrClk_S";
-TIMESPEC TS_FEE_gtxModule1_txUsrClk_S = PERIOD "FEE_gtxModule1/txUsrClk_S" 5 ns HIGH 50 %;
-NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" TNM_NET = "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S";
-TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Virtex6_1_rxRecClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk_S" 5 ns HIGH 50 %;
-NET "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S" TNM_NET = FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S;
-TIMESPEC TS_FEE_gtxModule1_FEE_gtxWrapper_Virtex6_1_txOutClk_S = PERIOD "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk_S" 12.5 ns HIGH 50%;
-#INST FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/gtx_i/gtx0_gtxVirtex6FEE_i/gtxe1_i LOC=GTXE1_X0Y12;
-#INST FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/gtx_i LOC=GTXE1_X0Y12;
-
-#TIMESPEC TS_RXCLK_to_TXCLK = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" TO "FEE_gtxModule1/txUsrClk2_S" 3 ns;
-#TIMESPEC TS_TXCLK_to_RXCLK = FROM "FEE_gtxModule1/txUsrClk2_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" 3 ns;
-#TIMESPEC TS_RXCLK_to_TXCLK0 = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk0_S" 3 ns;
-#TIMESPEC TS_TXCLK0_to_RXCLK = FROM "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/txOutClk0_S" TO "FEE_gtxModule1/FEE_gtxWrapper_Virtex6_1/rxRecClk0_S" 3 ns;
-
-
-NET "GEO" IOSTANDARD = LVCMOS25;
-#NET "GEO" DRIVE = 12;
-NET "GEO" SLEW = SLOW;
-NET "GEO" PULLUP;
-net "GEO" TIG;
-#NET "S_CTRL" TIG;
-#NET "T_CTRL_S" TIG;
-
-#INST "FEE_ADCinput_module1/AdcTopleveL1458_1/*" AREA_GROUP=pblock_adc_A1;
-#AREA_GROUP "pblock_adc_A1" RANGE=SLICE_X30Y140:SLICE_X35Y159;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL2356_1/*" AREA_GROUP=pblock_adc_B1;
-#AREA_GROUP "pblock_adc_B1" RANGE=SLICE_X30Y120:SLICE_X35Y139;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL1458_2/*" AREA_GROUP=pblock_adc_A2;
-#AREA_GROUP "pblock_adc_A2" RANGE=SLICE_X0Y120:SLICE_X5Y139;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL2356_2/*" AREA_GROUP=pblock_adc_B2;
-#AREA_GROUP "pblock_adc_B2" RANGE=SLICE_X0Y140:SLICE_X5Y159;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL1458_3/*" AREA_GROUP=pblock_adc_A3;
-#AREA_GROUP "pblock_adc_A3" RANGE=SLICE_X0Y100:SLICE_X5Y119;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL2356_3/*" AREA_GROUP=pblock_adc_B3;
-#AREA_GROUP "pblock_adc_B3" RANGE=SLICE_X0Y80:SLICE_X5Y99;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL1458_4/*" AREA_GROUP=pblock_adc_A4;
-#AREA_GROUP "pblock_adc_A4" RANGE=SLICE_X64Y100:SLICE_X69Y119;
-#
-#INST "FEE_ADCinput_module1/AdcTopleveL2356_4/*" AREA_GROUP=pblock_adc_B4;
-#AREA_GROUP "pblock_adc_B4" RANGE=SLICE_X64Y80:SLICE_X69Y99;
-
-
-INST "FEE_ADCinput_module1/AdcTopleveL1458_1/*" AREA_GROUP=pblock_adc_1;
-INST "FEE_ADCinput_module1/AdcTopleveL2356_1/*" AREA_GROUP=pblock_adc_1;
-AREA_GROUP "pblock_adc_1" RANGE=SLICE_X30Y120:SLICE_X35Y159;
-
-INST "FEE_ADCinput_module1/AdcTopleveL1458_2/*" AREA_GROUP=pblock_adc_2;
-INST "FEE_ADCinput_module1/AdcTopleveL2356_2/*" AREA_GROUP=pblock_adc_2;
-AREA_GROUP "pblock_adc_2" RANGE=SLICE_X0Y120:SLICE_X5Y159;
-
-INST "FEE_ADCinput_module1/AdcTopleveL1458_3/*" AREA_GROUP=pblock_adc_3;
-INST "FEE_ADCinput_module1/AdcTopleveL2356_3/*" AREA_GROUP=pblock_adc_3;
-AREA_GROUP "pblock_adc_3" RANGE=SLICE_X0Y80:SLICE_X5Y119;
-
-INST "FEE_ADCinput_module1/AdcTopleveL1458_4/*" AREA_GROUP=pblock_adc_4;
-INST "FEE_ADCinput_module1/AdcTopleveL2356_4/*" AREA_GROUP=pblock_adc_4;
-AREA_GROUP "pblock_adc_4" RANGE=SLICE_X64Y80:SLICE_X69Y119;
-
-
diff --git a/FEE_ADC32board/project/FEE_ADC32board.xise b/FEE_ADC32board/project/FEE_ADC32board.xise
deleted file mode 100644
index dbe2747..0000000
--- a/FEE_ADC32board/project/FEE_ADC32board.xise
+++ /dev/null
@@ -1,669 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="../FEE_modules/FEE_pulse_and_pileup_waveforms.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_sorting_wavemux.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_wavemux_readfifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_wavemux2to1.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/shift_register.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/iirfilter_1order_selectBW.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_combine_data.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_slowcontrol_receive_from_cpu.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/blockmem.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="253"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/posedge_to_pulse.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="254"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/crc8_add_check32.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="255"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_sorting_mux.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="256"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_extract_pulse.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="259"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_pulse2to1_pulse.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="260"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_mux2to1.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="269"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/div_pipe_r4_arch2/mypack.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="268"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_adc32_module.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="270"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_baselinefollower_eventdetector.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="271"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_board_slowcontrol.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="272"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_dual_pulse_waveform.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="273"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_eventdetector.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="274"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_mux_readfifo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="275"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_pileup_check.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="276"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_pulsewaveform_buffer.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="277"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_slowcontrol_packet_receiver.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="278"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_waveform_to_36bits.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="279"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/Panda_package.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="280"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_measure_frequency.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="295"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_SODAfrequencydiv5.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="295"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_fifo8to32_SODA.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="296"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_fifo32to8_SODA.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="297"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_rxBitLock.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="298"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_gtxModule.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="299"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
-    </file>
-    <file xil_pn:name="../FEE_modules/FEE_gtxWrapper_Virtex6.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="300"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/sync_fifo_512x41.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/sync_fifo_FWFT_512x36.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="107"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/sync_fifo_progfull504_progempty128_512x36.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="114"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/sync_fifo_progfull364_progempty128_512x36.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="121"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="121"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/gtxVirtex6FEE80.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="128"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/async_fifo_16x9.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="145"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="145"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/async_fifo_512x32.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="152"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="152"/>
-    </file>
-    <file xil_pn:name="FEE_ADC32board.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
-    </file>
-    <file xil_pn:name="FEE_ADC32board_top.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="161"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/clockmodule80to80M.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="162"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/clockmodule80M.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="168"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="168"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/clockmodule40switch.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="174"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="174"/>
-    </file>
-    <file xil_pn:name="../modules/FEE_ADCinput_module.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="180"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="180"/>
-    </file>
-    <file xil_pn:name="../modules/LMK03806.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="181"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="181"/>
-    </file>
-    <file xil_pn:name="../modules/SystemMonitorModule.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="182"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="182"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/icon0.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="183"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="183"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/ila36.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="191"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="191"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/ila128.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="198"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="198"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/SystemMonitorVirtex.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="205"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="205"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/vio36.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="211"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="211"/>
-    </file>
-    <file xil_pn:name="../../SODA/soda_FEE_endpoint.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="218"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="218"/>
-    </file>
-    <file xil_pn:name="../../SODA/soda_packet_handler.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="219"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="219"/>
-    </file>
-    <file xil_pn:name="../../SODA/soda_reply_pkt_builder.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="220"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="220"/>
-    </file>
-    <file xil_pn:name="../../SODA/soda_d8crc8.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="221"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="221"/>
-    </file>
-    <file xil_pn:name="../modules/ADCrefdesign/AdcClock.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="157"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="157"/>
-    </file>
-    <file xil_pn:name="../modules/ADCrefdesign/AdcData.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="158"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="158"/>
-    </file>
-    <file xil_pn:name="../modules/ADCrefdesign/AdcFrame.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="159"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="159"/>
-    </file>
-    <file xil_pn:name="../modules/ADCrefdesign/AdcToplevel.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="160"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="160"/>
-    </file>
-    <file xil_pn:name="../modules/ADCrefdesign/DoubleNibbleDetect.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="161"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="161"/>
-    </file>
-    <file xil_pn:name="../modules/ADCrefdesign/GenPulse.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="162"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="162"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/FEE_clockbuf80MHz.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="163"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/sync_fifo_512x41.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/sync_fifo_FWFT_512x36.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/sync_fifo_progfull504_progempty128_512x36.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/sync_fifo_progfull364_progempty128_512x36.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="122"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/gtxVirtex6FEE80.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="129"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/async_fifo_16x9.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="146"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/async_fifo_512x32.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="153"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/clockmodule80to80M.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="163"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/clockmodule80M.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="169"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/clockmodule40switch.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="175"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/icon0.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="184"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/ila36.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="192"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/ila128.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="199"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/SystemMonitorVirtex.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="206"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/vio36.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="212"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/FEE_clockbuf80MHz.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="164"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
-    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
-    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Busy" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin CS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin DIn" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin RdWr" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="Quiet(Off)" xil_pn:valueState="default"/>
-    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Drive Done Pin High" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Fallback Reconfiguration" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|Behavioral" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="FEE_ADC32board_top.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG to System Monitor Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance with IOB Packing;C:/Xilinx/14.7/ISE_DS/ISE/virtex6/data/virtex6_performance_with_iobpacking.xds" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="top" xil_pn:valueState="default"/>
-    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_map.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="top_timesim.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_translate.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>
-    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="top" xil_pn:valueState="default"/>
-    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/top" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.top" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
-    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.top" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Starting Address for Fallback Configuration virtex6" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="C:/Xilinx/14.7/ISE_DS/ISE/virtex6/data/virtex6_performance_with_physicalsynthesis2.xds" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="iMPACT Project File" xil_pn:value="FEE_V2_ADC32board.ipf" xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|sim_SODA2_tb|behavior" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="FEE_test_ADC32" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-20T09:50:16" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AA4862807094468B9C6DDA953391E7F7" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/FEE_ADC32board_top.vhd b/FEE_ADC32board/project/FEE_ADC32board_top.vhd
deleted file mode 100644
index b4e936e..0000000
--- a/FEE_ADC32board/project/FEE_ADC32board_top.vhd
+++ /dev/null
@@ -1,2184 +0,0 @@
-
-library IEEE;
-use IEEE.std_logic_1164.ALL;
-USE ieee.std_logic_unsigned.all;
-USE ieee.std_logic_arith.all;
-library UNISIM;
-use UNISIM.VComponents.all;
-library work;
-use work.panda_package.all;
---use work.panda_pkg.all;
-
-entity top is
-    Port ( 
-		GEO                     : in std_logic; -- 0:this is FPGA1, 1:this is FPGA2
-		GCLK_P                  : in std_logic; -- clock equal to GTX refclock (62.5MHz or 80MHz)
-		GCLK_N                  : in std_logic;
-		
-		ST_CLK_P                : in std_logic; -- 155.52MHz
-		ST_CLK_N                : in std_logic;
-
-
-----ADC1---------------------------------------------		
-		AD11A_P                 : in std_logic;
-		AD11A_N                 : in std_logic;
-		AD11B_P                 : in std_logic;
-		AD11B_N                 : in std_logic;
-		AD12A_P                 : in std_logic;
-		AD12A_N                 : in std_logic;
-		AD12B_P                 : in std_logic;
-		AD12B_N                 : in std_logic;
-		AD13A_P                 : in std_logic;
-		AD13A_N                 : in std_logic;
-		AD13B_P                 : in std_logic;
-		AD13B_N                 : in std_logic;
-		AD14A_P                 : in std_logic;
-		AD14A_N                 : in std_logic;
-		AD14B_P                 : in std_logic;
-		AD14B_N                 : in std_logic;
-		AD15A_P                 : in std_logic;
-		AD15A_N                 : in std_logic;
-		AD15B_P                 : in std_logic;
-		AD15B_N                 : in std_logic;
-		AD16A_P                 : in std_logic;
-		AD16A_N                 : in std_logic;
-		AD16B_P                 : in std_logic;
-		AD16B_N                 : in std_logic;
-		AD17A_P                 : in std_logic;
-		AD17A_N                 : in std_logic;
-		AD17B_P                 : in std_logic;
-		AD17B_N                 : in std_logic;
-		AD18A_P                 : in std_logic;
-		AD18A_N                 : in std_logic;
-		AD18B_P                 : in std_logic;
-		AD18B_N                 : in std_logic;
-		
-		DCOA1_P                 : in std_logic;
-		DCOA1_N                 : in std_logic;
-		DCOB1_P                 : in std_logic;
-		DCOB1_N                 : in std_logic;
-		
-		FRA1_P                  : in std_logic;
-		FRA1_N                  : in std_logic;
-		FRB1_P                  : in std_logic;
-		FRB1_N                  : in std_logic;
-
-----ADC2---------------------------------------------		
-		AD21A_P                 : in std_logic;
-		AD21A_N                 : in std_logic;
-		AD21B_P                 : in std_logic;
-		AD21B_N                 : in std_logic;
-		AD22A_P                 : in std_logic;
-		AD22A_N                 : in std_logic;
-		AD22B_P                 : in std_logic;
-		AD22B_N                 : in std_logic;
-		AD23A_P                 : in std_logic;
-		AD23A_N                 : in std_logic;
-		AD23B_P                 : in std_logic;
-		AD23B_N                 : in std_logic;
-		AD24A_P                 : in std_logic;
-		AD24A_N                 : in std_logic;
-		AD24B_P                 : in std_logic;
-		AD24B_N                 : in std_logic;
-		AD25A_P                 : in std_logic;
-		AD25A_N                 : in std_logic;
-		AD25B_P                 : in std_logic;
-		AD25B_N                 : in std_logic;
-		AD26A_P                 : in std_logic;
-		AD26A_N                 : in std_logic;
-		AD26B_P                 : in std_logic;
-		AD26B_N                 : in std_logic;
-		AD27A_P                 : in std_logic;
-		AD27A_N                 : in std_logic;
-		AD27B_P                 : in std_logic;
-		AD27B_N                 : in std_logic;
-		AD28A_P                 : in std_logic;
-		AD28A_N                 : in std_logic;
-		AD28B_P                 : in std_logic;
-		AD28B_N                 : in std_logic;
-
-		DCOA2_P                 : in std_logic;
-		DCOA2_N                 : in std_logic;
-		DCOB2_P                 : in std_logic;
-		DCOB2_N                 : in std_logic;
-		
-		FRA2_P                  : in std_logic;
-		FRA2_N                  : in std_logic;
-		FRB2_P                  : in std_logic;
-		FRB2_N                  : in std_logic;
-
-----ADC3---------------------------------------------		
-		AD31A_P                 : in std_logic;
-		AD31A_N                 : in std_logic;
-		AD31B_P                 : in std_logic;
-		AD31B_N                 : in std_logic;
-		AD32A_P                 : in std_logic;
-		AD32A_N                 : in std_logic;
-		AD32B_P                 : in std_logic;
-		AD32B_N                 : in std_logic;
-		AD33A_P                 : in std_logic;
-		AD33A_N                 : in std_logic;
-		AD33B_P                 : in std_logic;
-		AD33B_N                 : in std_logic;
-		AD34A_P                 : in std_logic;
-		AD34A_N                 : in std_logic;
-		AD34B_P                 : in std_logic;
-		AD34B_N                 : in std_logic;
-		AD35A_P                 : in std_logic;
-		AD35A_N                 : in std_logic;
-		AD35B_P                 : in std_logic;
-		AD35B_N                 : in std_logic;
-		AD36A_P                 : in std_logic;
-		AD36A_N                 : in std_logic;
-		AD36B_P                 : in std_logic;
-		AD36B_N                 : in std_logic;
-		AD37A_P                 : in std_logic;
-		AD37A_N                 : in std_logic;
-		AD37B_P                 : in std_logic;
-		AD37B_N                 : in std_logic;
-		AD38A_P                 : in std_logic;
-		AD38A_N                 : in std_logic;
-		AD38B_P                 : in std_logic;
-		AD38B_N                 : in std_logic;
-
-		DCOA3_P                 : in std_logic;
-		DCOA3_N                 : in std_logic;
-		DCOB3_P                 : in std_logic;
-		DCOB3_N                 : in std_logic;
-		
-		FRA3_P                  : in std_logic;
-		FRA3_N                  : in std_logic;
-		FRB3_P                  : in std_logic;
-		FRB3_N                  : in std_logic;
-
-----ADC4---------------------------------------------		
-		AD41A_P                 : in std_logic;
-		AD41A_N                 : in std_logic;
-		AD41B_P                 : in std_logic;
-		AD41B_N                 : in std_logic;
-		AD42A_P                 : in std_logic;
-		AD42A_N                 : in std_logic;
-		AD42B_P                 : in std_logic;
-		AD42B_N                 : in std_logic;
-		AD43A_P                 : in std_logic;
-		AD43A_N                 : in std_logic;
-		AD43B_P                 : in std_logic;
-		AD43B_N                 : in std_logic;
-		AD44A_P                 : in std_logic;
-		AD44A_N                 : in std_logic;
-		AD44B_P                 : in std_logic;
-		AD44B_N                 : in std_logic;
-		AD45A_P                 : in std_logic;
-		AD45A_N                 : in std_logic;
-		AD45B_P                 : in std_logic;
-		AD45B_N                 : in std_logic;
-		AD46A_P                 : in std_logic;
-		AD46A_N                 : in std_logic;
-		AD46B_P                 : in std_logic;
-		AD46B_N                 : in std_logic;
-		AD47A_P                 : in std_logic;
-		AD47A_N                 : in std_logic;
-		AD47B_P                 : in std_logic;
-		AD47B_N                 : in std_logic;
-		AD48A_P                 : in std_logic;
-		AD48A_N                 : in std_logic;
-		AD48B_P                 : in std_logic;
-		AD48B_N                 : in std_logic;		
-		
-		DCOA4_P                 : in std_logic;
-		DCOA4_N                 : in std_logic;
-		DCOB4_P                 : in std_logic;
-		DCOB4_N                 : in std_logic;
-		
-		FRA4_P                  : in std_logic;
-		FRA4_N                  : in std_logic;
-		FRB4_P                  : in std_logic;
-		FRB4_N                  : in std_logic;
-		
-----ADCconfiguration---------------------------------------------		
-		SCK                     : out std_logic;
-		SDI                     : out std_logic;
-		CSA                     : out std_logic_vector(1 to 4);
-		CSB                     : out std_logic_vector(1 to 4);
-		SDOA                    : inout std_logic_vector(1 to 4);
-		SDOB                    : inout std_logic_vector(1 to 4);
-
-----GTX---------------------------------------------		
-		MOD_DEF                 : in std_logic_vector(2 downto 0);
-		LOS                     : in std_logic;
-		TX_DIS                  : out std_logic;
-		MGTREFCLK_P             : in std_logic;
-		MGTREFCLK_N             : in std_logic;
-
-		RX_P                    : in std_logic;
-		RX_N                    : in std_logic;
-		TX_P                    : out std_logic;
-		TX_N                    : out std_logic;
-
-----PLL---------------------------------------------		
-
-		S_CTRL                  : in std_logic; -- 1 : FPGA1 controls PLL&JTAG, 0 : FPGA2 controls PLL&JTAG
-		T_CTRL                  : out std_logic; -- T_CTRL from FPGA1<>FPGA2 : FPGA1 controls PLL&JTAG
-
-		RDu                     : in std_logic;
-		CLKu                    : out std_logic;
-		DATAu                   : out std_logic;
-		LEu                     : out std_logic;
-		SYNC                    : out std_logic;
-		RCV_CLK_P               : out std_logic; -- ref clock for PLL LMK03806
-		RCV_CLK_N               : out std_logic;
-		
-----TMP104---------------------------------------------				
---		TEMP_IN                 : out std_logic;
---		TEMP_OUT                : in std_logic;
-		
-----test---------------------------------------------		
-		SM1_P                   : out std_logic;
-		SM1_N                   : out std_logic;
-		SM3_P                   : in std_logic;
-		SM3_N                   : in std_logic;
-
-		INTCOMC1_P              : inout std_logic;
-		INTCOMC1_N              : inout std_logic;
-		INTCOMC2_P              : inout std_logic;
-		INTCOMC2_N              : inout std_logic;
-
-		INTCOM0_P               : inout std_logic;
-		INTCOM0_N               : inout std_logic;
-		INTCOM1_P               : inout std_logic;
-		INTCOM1_N               : inout std_logic;
-		INTCOM2_P               : inout std_logic;
-		INTCOM2_N               : inout std_logic;
-		INTCOM3_P               : inout std_logic;
-		INTCOM3_N               : inout std_logic;
-		INTCOM4_P               : inout std_logic;
-		INTCOM4_N               : inout std_logic;
-		INTCOM5_P               : inout std_logic;
-		INTCOM5_N               : inout std_logic;
-		INTCOM6_P               : inout std_logic;
-		INTCOM6_N               : inout std_logic;
-		INTCOM7_P               : inout std_logic;
-		INTCOM7_N               : inout std_logic;
-
-		TCK_F                   : in std_logic;
-		TDI_F                   : in std_logic;
-		TDO_F                   : in std_logic;
-		TMS_F                   : in std_logic
---		PROGRAM_B               : inout std_logic
-
-
---		D                       : in std_logic_VECTOR (7 downto 0)
-		);
-end top;
-
-
-
-architecture Behavioral of top is
-
-component clockmodule80M
-port (
-		CLK_IN1           : in std_logic;
-		CLK_OUT1          : out std_logic;
-		LOCKED            : out std_logic
-		);
-end component;
-
-component clock155to200MHz
-port(
-		CLK_IN1           : in std_logic;
-		CLK_IN2           : in std_logic;
-		CLK_IN_SEL        : in std_logic;
-		CLK_OUT1          : out std_logic;
-		RESET             : in std_logic;
-		LOCKED            : out std_logic
-		);
-end component;
-
-component clockmodule80to80M
-port(
-		CLK_IN1           : in std_logic;
-		CLK_OUT1          : out std_logic;
-		CLK_OUT2          : out std_logic;
-		CLK_OUT3          : out std_logic;
-		CLK_OUT4          : out std_logic;
-		RESET             : in std_logic;
-		LOCKED            : out std_logic
-		);
-end component;
-
-component clockmodule40to80
-port(
-		CLK_IN1           : in std_logic;
-		CLK_OUT1          : out std_logic;
-		LOCKED            : out std_logic
-		);
-end component;
-
-component clockmodule40switch
-port(
-		CLK_IN1           : in std_logic;
-		CLK_IN2           : in std_logic;
-		CLK_IN_SEL        : in std_logic;
-		CLK_OUT1          : out std_logic;
-		CLK_OUT2          : out std_logic;
-		RESET             : in std_logic;
-		LOCKED            : out std_logic
-		);
-end component;
-
-component LMK03806 is
-	generic(
-		CLK_DIV               : integer := 6;       -- slow down transfer
-		ADCCLOCKFREQUENCY     : natural := ADCCLOCKFREQUENCY
-	);         
-	PORT( 
-		clock                 : in std_logic; --Master clock 
-		CLKu                  : out std_logic; --Clk to LMK  
-		DATAu                 : out std_logic; --Data to LMK
-		LEu                   : out std_logic; --Data Latch to LMK
-		RDn                   : in std_logic; --Read back
-		SYNC                  : out std_logic; --Sync CLK outputs LMK
-		boot_PLL              : in std_logic; --Start booting when set high
-		reset_GTX             : out std_logic; --delayed reset for GTX			
-		reset_ADCs            : out std_logic; --delayed reset for ADCs		
-		booting               : out std_logic; --busy signal		
-		testwordin            : in std_logic_vector(15 downto 0)
-	);
-end component;
-
-component FEE_ADCinput_module is
-	port ( 
-		clock200MHz             : in std_logic;
-		reset                   : in std_logic;
-		ADCs_enable             : in std_logic;
-----ADC1---------------------------------------------		
-		AD11A_P                 : in std_logic;
-		AD11A_N                 : in std_logic;
-		AD11B_P                 : in std_logic;
-		AD11B_N                 : in std_logic;
-		AD12A_P                 : in std_logic;
-		AD12A_N                 : in std_logic;
-		AD12B_P                 : in std_logic;
-		AD12B_N                 : in std_logic;
-		AD13A_P                 : in std_logic;
-		AD13A_N                 : in std_logic;
-		AD13B_P                 : in std_logic;
-		AD13B_N                 : in std_logic;
-		AD14A_P                 : in std_logic;
-		AD14A_N                 : in std_logic;
-		AD14B_P                 : in std_logic;
-		AD14B_N                 : in std_logic;
-		AD15A_P                 : in std_logic;
-		AD15A_N                 : in std_logic;
-		AD15B_P                 : in std_logic;
-		AD15B_N                 : in std_logic;
-		AD16A_P                 : in std_logic;
-		AD16A_N                 : in std_logic;
-		AD16B_P                 : in std_logic;
-		AD16B_N                 : in std_logic;
-		AD17A_P                 : in std_logic;
-		AD17A_N                 : in std_logic;
-		AD17B_P                 : in std_logic;
-		AD17B_N                 : in std_logic;
-		AD18A_P                 : in std_logic;
-		AD18A_N                 : in std_logic;
-		AD18B_P                 : in std_logic;
-		AD18B_N                 : in std_logic;
-		
-		DCOA1_P                 : in std_logic;
-		DCOA1_N                 : in std_logic;
-		DCOB1_P                 : in std_logic;
-		DCOB1_N                 : in std_logic;
-		
-		FRA1_P                  : in std_logic;
-		FRA1_N                  : in std_logic;
-		FRB1_P                  : in std_logic;
-		FRB1_N                  : in std_logic;
-
-----ADC2---------------------------------------------		
-		AD21A_P                 : in std_logic;
-		AD21A_N                 : in std_logic;
-		AD21B_P                 : in std_logic;
-		AD21B_N                 : in std_logic;
-		AD22A_P                 : in std_logic;
-		AD22A_N                 : in std_logic;
-		AD22B_P                 : in std_logic;
-		AD22B_N                 : in std_logic;
-		AD23A_P                 : in std_logic;
-		AD23A_N                 : in std_logic;
-		AD23B_P                 : in std_logic;
-		AD23B_N                 : in std_logic;
-		AD24A_P                 : in std_logic;
-		AD24A_N                 : in std_logic;
-		AD24B_P                 : in std_logic;
-		AD24B_N                 : in std_logic;
-		AD25A_P                 : in std_logic;
-		AD25A_N                 : in std_logic;
-		AD25B_P                 : in std_logic;
-		AD25B_N                 : in std_logic;
-		AD26A_P                 : in std_logic;
-		AD26A_N                 : in std_logic;
-		AD26B_P                 : in std_logic;
-		AD26B_N                 : in std_logic;
-		AD27A_P                 : in std_logic;
-		AD27A_N                 : in std_logic;
-		AD27B_P                 : in std_logic;
-		AD27B_N                 : in std_logic;
-		AD28A_P                 : in std_logic;
-		AD28A_N                 : in std_logic;
-		AD28B_P                 : in std_logic;
-		AD28B_N                 : in std_logic;
-
-		DCOA2_P                 : in std_logic;
-		DCOA2_N                 : in std_logic;
-		DCOB2_P                 : in std_logic;
-		DCOB2_N                 : in std_logic;
-		
-		FRA2_P                  : in std_logic;
-		FRA2_N                  : in std_logic;
-		FRB2_P                  : in std_logic;
-		FRB2_N                  : in std_logic;
-
-----ADC3---------------------------------------------		
-		AD31A_P                 : in std_logic;
-		AD31A_N                 : in std_logic;
-		AD31B_P                 : in std_logic;
-		AD31B_N                 : in std_logic;
-		AD32A_P                 : in std_logic;
-		AD32A_N                 : in std_logic;
-		AD32B_P                 : in std_logic;
-		AD32B_N                 : in std_logic;
-		AD33A_P                 : in std_logic;
-		AD33A_N                 : in std_logic;
-		AD33B_P                 : in std_logic;
-		AD33B_N                 : in std_logic;
-		AD34A_P                 : in std_logic;
-		AD34A_N                 : in std_logic;
-		AD34B_P                 : in std_logic;
-		AD34B_N                 : in std_logic;
-		AD35A_P                 : in std_logic;
-		AD35A_N                 : in std_logic;
-		AD35B_P                 : in std_logic;
-		AD35B_N                 : in std_logic;
-		AD36A_P                 : in std_logic;
-		AD36A_N                 : in std_logic;
-		AD36B_P                 : in std_logic;
-		AD36B_N                 : in std_logic;
-		AD37A_P                 : in std_logic;
-		AD37A_N                 : in std_logic;
-		AD37B_P                 : in std_logic;
-		AD37B_N                 : in std_logic;
-		AD38A_P                 : in std_logic;
-		AD38A_N                 : in std_logic;
-		AD38B_P                 : in std_logic;
-		AD38B_N                 : in std_logic;
-
-		DCOA3_P                 : in std_logic;
-		DCOA3_N                 : in std_logic;
-		DCOB3_P                 : in std_logic;
-		DCOB3_N                 : in std_logic;
-		
-		FRA3_P                  : in std_logic;
-		FRA3_N                  : in std_logic;
-		FRB3_P                  : in std_logic;
-		FRB3_N                  : in std_logic;
-
-----ADC4---------------------------------------------		
-		AD41A_P                 : in std_logic;
-		AD41A_N                 : in std_logic;
-		AD41B_P                 : in std_logic;
-		AD41B_N                 : in std_logic;
-		AD42A_P                 : in std_logic;
-		AD42A_N                 : in std_logic;
-		AD42B_P                 : in std_logic;
-		AD42B_N                 : in std_logic;
-		AD43A_P                 : in std_logic;
-		AD43A_N                 : in std_logic;
-		AD43B_P                 : in std_logic;
-		AD43B_N                 : in std_logic;
-		AD44A_P                 : in std_logic;
-		AD44A_N                 : in std_logic;
-		AD44B_P                 : in std_logic;
-		AD44B_N                 : in std_logic;
-		AD45A_P                 : in std_logic;
-		AD45A_N                 : in std_logic;
-		AD45B_P                 : in std_logic;
-		AD45B_N                 : in std_logic;
-		AD46A_P                 : in std_logic;
-		AD46A_N                 : in std_logic;
-		AD46B_P                 : in std_logic;
-		AD46B_N                 : in std_logic;
-		AD47A_P                 : in std_logic;
-		AD47A_N                 : in std_logic;
-		AD47B_P                 : in std_logic;
-		AD47B_N                 : in std_logic;
-		AD48A_P                 : in std_logic;
-		AD48A_N                 : in std_logic;
-		AD48B_P                 : in std_logic;
-		AD48B_N                 : in std_logic;		
-		
-		DCOA4_P                 : in std_logic;
-		DCOA4_N                 : in std_logic;
-		DCOB4_P                 : in std_logic;
-		DCOB4_N                 : in std_logic;
-		
-		FRA4_P                  : in std_logic;
-		FRA4_N                  : in std_logic;
-		FRB4_P                  : in std_logic;
-		FRB4_N                  : in std_logic;
-		ADC_clk                 : out std_logic;
-		ADCs_ready              : out std_logic;
-		adcdata                 : out array_adc_type
-		);
-end component;
-
-component FEE_adc32_module is
-	generic (
-		NROFADCS                : natural := NROFADCS;
-		ADCBITS                 : natural := 14;
-		BASELINE_BWBITS         : natural := 10;
-		WAVEFORMBUFFERSIZE      : natural := 10;
-		ADCCLOCKFREQUENCY       : natural := ADCCLOCKFREQUENCY;
-		CF_DELAYBITS            : natural := 4;
-		CF_FRACTIONBIT          : natural := 11;
-		IDIVMAXBITS             : natural := 6;
-		INTEGRALRATIOBITS       : natural := 3
-	);
-	port ( 
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		enable_data             : in std_logic;
-		ADCdata                 : in array_adc_type;
-		superburst_start        : in std_logic;
-		superburst_received     : in std_logic_vector(30 downto 0);
-		onesecondpulse          : in std_logic;
-		rxNotInTable            : in std_logic;
-		startupready            : in std_logic;
-		request_init            : in std_logic;
-		packet_in_data          : in std_logic_vector (31 downto 0);
-		packet_in_present       : in std_logic;
-		packet_in_read          : out std_logic;
-		packet_out_data         : out std_logic_vector(31 downto 0);
-		packet_out_last         : out std_logic;
-		packet_out_write        : out std_logic;
-		packet_out_fifofull     : in std_logic;
-		errorbyte_out           : out std_logic_vector(7 downto 0);
-		errorbyte_in            : in std_logic_vector(7 downto 0);
-		smaart_in               : in std_logic;
-		smaart_out              : out std_logic;
-		sysmon_data             : in std_logic_vector(15 downto 0);
-		sysmon_reset            : out std_logic;
-		sysmon_address          : out std_logic_vector(6 downto 0);
-		sysmon_read             : out std_logic;
-		testindex               : in integer range 0 to NROFADCS/2-1;
-		testword0               : out std_logic_vector(35 downto 0);
-		testword1               : out std_logic_vector(35 downto 0);
-		testword2               : out std_logic_vector(35 downto 0)
-		);
-end component;	
-
-component FEE_gtxModule is
-	generic(
-		ADCCLOCKFREQUENCY       : natural := ADCCLOCKFREQUENCY -- 80000000 -- 62500000 
-	);         
-	Port (	
-		gtpClk                  : in std_logic;
-		asyncclk                : in std_logic;
-		reset                   : in std_logic;
-		disable_GTX_reset       : in std_logic;
-		
-		TX_DLM                  : in std_logic;
-		TX_DLM_WORD             : in std_logic_vector(7 downto 0);   
-		RX_DLM                  : out std_logic;
-		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
-		
-		txAsyncClk              : in std_logic;
-		txAsyncData             : in std_logic_vector(31 downto 0);
-		txAsyncDataWrite        : in std_logic;
-		txAsyncLastData         : in std_logic;
-		txAsyncFifoFull         : out std_logic;
-		txUsrClk                : out  std_logic;
-		txLocked                : out std_logic;
-		
-		rxAsyncClk              : in std_logic;
-		rxAsyncData             : out std_logic_vector(31 downto 0);
-		rxAsyncDataRead         : in std_logic;
-		rxNotInTable            : out std_logic;
-		rxAsyncDataOverflow     : out std_logic;
-		rxAsyncDataPresent      : out std_logic;
-		rxSodaClk               : out std_logic;
-		rxSodaClk40             : out std_logic;
-		rxLocked                : out std_logic;
-		
-		gtpTxP0                 : out std_logic;
-		gtpTxN0                 : out std_logic;
-		gtpRxP0                 : in std_logic;
-		gtpRxN0                 : in std_logic;
-		testword0               : out std_logic_vector(35 downto 0)
-	);
-end component;
-
-component soda_FEE_endpoint is
-	generic(
-		SODA_16BIT_INTERFACE	: boolean := FALSE
-	);
-	port(
-		SYSCLK					: in	std_logic; -- fabric clock
-		RESET						: in	std_logic; -- synchronous reset
-		CLEAR						: in	std_logic; -- asynchronous reset
-		CLK_EN					: in	std_logic; 
-
-		RX_DLM_WORD_IN			: in	std_logic_vector(7 downto 0)	:= (others => '0');
-		RX_DLM_IN				: in std_logic;
-		TX_DLM_OUT				: out	std_logic;
-		TX_DLM_WORD_OUT		: out	std_logic_vector(7 downto 0)	:= (others => '0');
-
-		
-		START_OF_SUPERBURST		: out std_logic	:= '0';
-		SUPER_BURST_NR				: out std_logic_vector(30 downto 0) := (others => '0');
-		SODA_CMD_VALID			: out std_logic := '0';
-		SODA_CMD_WORD			: out std_logic_vector(30 downto 0) := (others => '0');
-		
-		STAT						: out  std_logic_vector(31 downto 0) := (others => '0') -- DEBUG
-	);
-end component;
-
-component SystemMonitorModule is
-    Port ( 
-		clock                   : in std_logic;
-		reset                   : in std_logic;
-		address                 : in std_logic_vector(6 downto 0);
-		data_write              : in std_logic;
-		data_in                 : in std_logic_vector(15 downto 0);
-		data_read               : in std_logic;
-		data_out                : out std_logic_vector(15 downto 0);
-		alarms                  : out std_logic_vector(7 downto 0);
-		testword0               : out std_logic_vector(35 downto 0));
-end component;
-
-component posedge_to_pulse is
-	port (
-		clock_in                : in  std_logic;
-		clock_out               : in  std_logic;
-		en_clk                  : in  std_logic;
-		signal_in               : in  std_logic;
-		pulse                   : out std_logic
-	);
-end component;
-
-component posedge_async_to_pulse is
-	port (
-		clock_out         : in  std_logic;
-		signal_in         : in  std_logic;
-		pulse             : out std_logic
-	);
-end component;
-
-component icon0
-	port ( 
-    CONTROL0                  : inout std_logic_vector(35 downto 0);
-    CONTROL1                  : inout std_logic_vector(35 downto 0);
-    CONTROL2                  : inout std_logic_vector(35 downto 0);
-    CONTROL3                  : inout std_logic_vector(35 downto 0);
-    CONTROL4                  : inout std_logic_vector(35 downto 0));
-end component;
-
-component ila36
-	port ( 
-    CONTROL                   : inout std_logic_vector(35 downto 0);
-    CLK                       : in std_logic;
-    TRIG0                     : in std_logic_vector(35 downto 0));
-end component;
-
-component ila128
-	port ( 
-    CONTROL                   : inout std_logic_vector(35 downto 0);
-    CLK                       : in std_logic;
-    TRIG0                     : in std_logic_vector(127 downto 0));
-end component;
-
-component vio36
-	port ( 
-    CONTROL                   : inout std_logic_vector(35 downto 0);
-    ASYNC_OUT                 : out std_logic_vector(35 downto 0));
-end component;
-
-attribute keep                : string;
-constant DEBUG : boolean := false;
--- clocking
-signal ST_CLK_S               : std_logic;
-attribute keep of ST_CLK_S    : signal is "TRUE";
-signal clock_ADCrefdiv2_S     : std_logic; 
-signal clock_ADCref_S         : std_logic; -- 62.5 or 80 MHz
-attribute keep of clock_ADCref_S : signal is "TRUE";
-signal clock100MHz_S          : std_logic;
-signal clock200MHz_S          : std_logic;
-signal clock80MHz_PLL1_S      : std_logic;
-signal GCLK_S                 : std_logic;
-attribute keep of GCLK_S      : signal is "TRUE";
-signal gtpClk_S               : std_logic;
-signal RCV_CLK_P_S            : std_logic;
-signal RCV_CLK_S              : std_logic;
-signal RCV_CLK_not_S          : std_logic;
-signal RCV_CLKref_S           : std_logic;
-signal RCV_CLKrx_S            : std_logic;
-signal ADC_clk_S              : std_logic;
-attribute keep of ADC_clk_S   : signal is "TRUE";
-signal txUsrClk_S             : std_logic;
-
-
-signal clockPLL1_locked_S     : std_logic;
-signal clockPLL2_reset_S      : std_logic;
-signal clockmodule_locked_S   : std_logic;
-signal clockswitch_locked_S   : std_logic;
-		
--- resetting
-signal coldstart_counter_S    : std_logic_vector(7 downto 0) := (others => '0');
-signal coldstart_S            : std_logic := '0';
-signal reset_S                : std_logic := '0';
-signal reset_FEE_S            : std_logic := '0';
-signal reset_FEE_ADCclk_S     : std_logic := '0';
-signal resetting_S            : std_logic := '0';
-signal resetting_stclk_S      : std_logic := '0';
-signal IcontrolPLL_S          : std_logic := '0';
-signal otherFPGAnotconfigured0_S : std_logic := '0';
-signal otherFPGAnotconfigured_S  : std_logic := '0';
-signal PLLconfigured_S        : std_logic := '0';
-signal startupready_S         : std_logic := '0';
-signal selectPLLclk_S         : std_logic := '0';
-signal selectPLLclk_stclk_S   : std_logic := '0';
-signal disable_GTX_reset_S    : std_logic := '0';
-signal GEO_S                  : std_logic := '0';
-signal GEO_stclk_S            : std_logic := '0';
-signal T_CTRL_S               : std_logic := '0';
-signal S_CTRL0_S              : std_logic := '0';
-signal phaseSYNC_S            : std_logic := '0';
-signal boot_PLL_S             : std_logic := '0';
-signal PLL_booting_S          : std_logic := '0';
-signal adcintrfcena_s         : std_logic := '0';
-signal reset_ADCs_S           : std_logic := '0';
-signal ADCs_enable_S          : std_logic := '0';
-signal reset_GTX_S            : std_logic := '0';
-signal reset_counter_S        : integer range 0 to 65535 := 0;
-signal timeout_counter_S      : integer range 0 to 65535 := 0;
-signal external_sync_out_S    : std_logic := '0';
-signal external_sync_in0_S    : std_logic := '0';
-signal external_sync_in_S     : std_logic := '0';
-signal reset_rxSodaClk_S      : std_logic;
-signal ADCs_ready_S           : std_logic;
-
-
--- SODA
-signal EnableDataTaking_S     : std_logic := '0';
-signal DisableDataTaking_S    : std_logic := '0';
-signal enable_data_S          : std_logic := '0';
-signal DataTaking_enabled_out_S : std_logic := '0';
-signal DataTaking_enabled_in_S  : std_logic := '0';
-signal SODA_cmd_valid_S       : std_logic := '0';
-signal SODA_cmd_word_S        : std_logic_vector(30 downto 0);
-signal superburst_out_S       : std_logic_vector(30 downto 0);
-signal superburst_in_S        : std_logic_vector(30 downto 0);
-signal superburst_start0_S    : std_logic;
-signal superburst_start1_S    : std_logic;
-signal superburst_start_S     : std_logic;
-signal superburst_startout0_S : std_logic;
-signal superburst_startout_S  : std_logic;
-signal TX_DLM_S               : std_logic;
-signal TX_DLM_WORD_S          : std_logic_vector(7 downto 0);   
-signal RX_DLM_S               : std_logic;
-signal RX_DLM_WORD_S          : std_logic_vector(7 downto 0);
-
--- fiber data
-signal packet_in_data_S       : std_logic_vector(31 downto 0);
-signal packet_out_data_S      : std_logic_vector(31 downto 0) := (others => '0');
-signal packet_in_present_S    : std_logic := '0';
-signal packet_in_read_S       : std_logic := '0';
-signal packet_out_last_S      : std_logic := '0';
-signal packet_out_write_S     : std_logic := '0';
-signal packet_out_fifofull_S  : std_logic := '0';
-signal rxNotInTable0_S        : std_logic;
-signal rxNotInTable_S         : std_logic;
-
-
--- clock check
-signal GCLKdiv10_S            : std_logic := '0';
-signal GCLKdiv10_prev1_S      : std_logic := '0';
-signal GCLKdiv10_prev2_S      : std_logic := '0';
-signal PLLfrequencyERROR_S    : std_logic := '0';
-
--- lmk03806
-signal CLKu_S                           : std_logic := '0';
-signal DATAu_S                          : std_logic := '0';
-signal LEu_S                            : std_logic := '0';
-signal SYNC_S                           : std_logic := '0';
-signal SYNC0_S                          : std_logic := '0';
-signal SYNC1_S                          : std_logic := '0';
-signal SYNC2_S                          : std_logic := '0';
-signal debug_sync_S                     : std_logic := '0';
-
--- ADCs
-signal adcdata_S              : array_adc_type;
-
--- GTX
-signal LOS_S                  : std_logic;
-signal rxSodaClk_S            : std_logic;
-attribute keep of rxSodaClk_S : signal is "TRUE";
-signal rxSodaClk40_S          : std_logic;
-signal rxSodaClk40b_S         : std_logic;
-signal rxSodaClk80_S          : std_logic;
-signal rxLocked_S             : std_logic;
-signal rxLocked0_S            : std_logic;
-signal rxLocked_sync_S        : std_logic;
-
--- phasedet
-signal phasedet_S             : std_logic;
-signal GCLKdiv2_S             : std_logic;
-signal GCLKdiv4_S             : std_logic;
-signal rxSodaClkdiv4_S        : std_logic;
-signal phaseerr_max_S         : integer range 0 to 1023 := 0;
-signal phasedet_count_S       : integer range 0 to 1023 := 0;
-signal phaseerr_count_S       : integer range 0 to 1023 := 0;
-signal phasecheck_ready_S     : std_logic := '0';
-signal phasecheck_ready1_S    : std_logic := '0';
-signal phaseSYNCpulse_S       : std_logic := '0';
-signal phasecheckcounter_S    : integer range 0 to 255 := 0;
-
-
--- timestamp reset
---signal ResetToZero_S          : std_logic;
-signal onesecondpulse_S       : std_logic;
-		
-signal SYNC_stclk_S           : std_logic;
-signal SYNC_stclk2_S          : std_logic;
-signal SYNC_adcclk_S          : std_logic;
-signal SYNC_adcclk2_S         : std_logic;
-signal SYNC_soda_S            : std_logic;
-signal SYNC_soda2_S           : std_logic;
-
--- system monitor
-signal sysmon_data_S          : std_logic_vector(15 downto 0);
-signal sysmon_reset_S         : std_logic;
-signal sysmon_address_S       : std_logic_vector(6 downto 0);
-signal sysmon_read_S          : std_logic;
-
--- test compare feature extraction results
-constant SECOND_FE_MODULE     : boolean := false;
-signal adcdata2_S             : array_adc_type;
-signal request_init_S         : std_logic := '0';
-signal reset_FEE_ADCclk2_S    : std_logic := '0';
-signal reset_FEE_ADCclk2a_S   : std_logic := '0';
-signal packet_out_data2_S     : std_logic_vector(31 downto 0);
-signal packet_in_read2_S      : std_logic;
-signal packet_out_last2_S     : std_logic;
-signal packet_out_write2_S    : std_logic;
-signal unequal_counter_S      : std_logic_vector(31 downto 0) := (others => '0');
-signal unequal_time_S         : std_logic_vector(31 downto 0) := (others => '0');
-signal zero_data_S            : std_logic;
-signal unequal_S              : std_logic;
-signal errorbyte_S            : std_logic_vector(7 downto 0) := (others => '0');
-
-
--- test
-signal control0_S             : std_logic_vector(35 downto 0) := (others => '0');
-signal control1_S             : std_logic_vector(35 downto 0) := (others => '0');
-signal control2_S             : std_logic_vector(35 downto 0) := (others => '0');
-signal control3_S             : std_logic_vector(35 downto 0) := (others => '0');
-signal control4_S             : std_logic_vector(35 downto 0) := (others => '0');
-signal testword0a_S           : std_logic_vector(35 downto 0) := (others => '0');
-signal testword0b_S           : std_logic_vector(35 downto 0) := (others => '0');
-signal testword0_S            : std_logic_vector(35 downto 0) := (others => '0');
-signal testword1_S            : std_logic_vector(35 downto 0) := (others => '0');
-signal testwordb_S            : std_logic_vector(35 downto 0) := (others => '0');
-signal testword2_S            : std_logic_vector(127 downto 0) := (others => '0');
-signal vioword_S              : std_logic_vector(35 downto 0) := (others => '0');
-signal vioword2_S             : std_logic_vector(35 downto 0) := (others => '0');
-signal testwordA0_S           : std_logic_vector(35 downto 0) := (others => '0');
-signal testwordB0_S           : std_logic_vector(35 downto 0) := (others => '0');
-
-signal selectnr_S             : integer range 0 to 3 := 0;
-signal testclockDiv2_S        : std_logic_vector(7 downto 0) := (others => '0');
-signal forced_reset_S         : std_logic := '0';
-signal test_resetadc_s        : std_logic := '0';
-signal testclocks_S           : std_logic_vector(8 downto 0) := (others => '0');
-signal testclockDiv100_S      : std_logic_vector(8 downto 0) := (others => '0');
-
-begin
--- GEO=0:this is FPGA1, GEO=1:this is FPGA2
--- S_CTRL=1 : FPGA1 controls PLL&JTAG 
--- S_CTRL=0 : FPGA2 controls PLL&JTAG 
-
--- T_CTRL1 T_CTRL2  PLL_controlled_by   S_CTRL
---    0        0       0  =   FPGA2        0
---    1        0       1  =   FPGA1        1
---    0        1       1  =   FPGA1        1
---    1        1       0  =   FPGA2        0
-
-IcontrolPLL_S <= '1' when (GEO/=S_CTRL) else '0'; -- '1' when this FPGA controls the PLL
-
-coldstartprocess: process(ST_CLK_S)
-begin
-	if rising_edge(ST_CLK_S) then
-		if coldstart_counter_S/=x"ff" then
-			coldstart_S <= '0';
-			coldstart_counter_S <= coldstart_counter_S+1;
-		else
-			coldstart_S <= '1';
-		end if;
-	end if;
-end process;
-
-
-T_CTRL <= T_CTRL_S;
-T_CTRL_S <= 
-	coldstart_S when GEO='1'  -- PLL_controlled_by FPGA2
-	else '0' when  PLLconfigured_S='0'  -- PLL_controlled_by FPGA1 during booting
-	else '1'; -- PLL_controlled_by FPGA2, but reference frequency from FPGA1
-PLLconfigured_S <= '1' when (PLL_booting_S='0') and (resetting_S='0') else '0';
-process(clock_ADCref_S)
-begin
-	if rising_edge(clock_ADCref_S) then
-		if GEO='0' then
-			if T_CTRL_S=S_CTRL then 
-				if otherFPGAnotconfigured0_S='1' then
-					otherFPGAnotconfigured_S <= '1';
-				end if;
-				otherFPGAnotconfigured0_S <= '1';
-			else
-				otherFPGAnotconfigured0_S <= '0';
-				otherFPGAnotconfigured_S <= '0';
-			end if;
-		else
-			otherFPGAnotconfigured0_S <= '0';
-			otherFPGAnotconfigured_S <= '0';
-		end if;
-	end if;
-end process;
-	
-sysclk_buf : IBUFGDS
-		port map (	I	=>	GCLK_P,
-						IB	=>	GCLK_N,
-						O	=>	GCLK_S);
-ST_CLK_buf : IBUFGDS
-		port map (	I	=>	ST_CLK_P,
-						IB	=>	ST_CLK_N,
-						O	=>	ST_CLK_S);
-
-clockmodule80Ma: clockmodule80M port map(
-		CLK_IN1 => ST_CLK_S,
-		CLK_OUT1 => clock80MHz_PLL1_S,
-		LOCKED => clockPLL1_locked_S);
-clockmodule80to80Ma: clockmodule80to80M port map(
-		CLK_IN1 => clock80MHz_PLL1_S,
-		CLK_OUT1 => clock_ADCrefdiv2_S, -- 40MHz
-		CLK_OUT2 => clock_ADCref_S, -- 80MHz
-		CLK_OUT3 => clock100MHz_S,
-		CLK_OUT4 => clock200MHz_S,
-		RESET => clockPLL2_reset_S,
-		LOCKED => clockmodule_locked_S);
-clockPLL2_reset_S <= '1' when clockPLL1_locked_S='0' else '0';
-
-
-reset_S <= '1' when (clockmodule_locked_S='0') or (forced_reset_S='1') else '0';
-resetprocess: process(clock_ADCref_S,reset_S,GEO)
-variable resetFEE_count_V : integer range 0 to 16 := 0;
-begin
-	if reset_S='1' then
-		reset_counter_S <= 0;
-		boot_PLL_S <= '0';
-		reset_GTX_S <= '1';
-		resetting_S <= '1';
-		rxLocked_sync_S <= '0';
-		GEO_S <= GEO;
-		resetFEE_count_V := 0;
-		reset_FEE_S <= '1';
-		disable_GTX_reset_S <= '0';
-	elsif rising_edge(clock_ADCref_S) then
-		rxLocked_sync_S <= rxLocked_S;
-		if resetFEE_count_V<16 then
-			resetFEE_count_V := resetFEE_count_V+1;		
-			reset_FEE_S <= '1';
-		else
-			reset_FEE_S <= '0';
-		end if;
-		GEO_S <= GEO;
-		if GEO_S='0' then -- FPGA1
-			if ((PLLfrequencyERROR_S='1') and (selectPLLclk_S='1')) or (otherFPGAnotconfigured_S='1') then -- restart all
-				reset_counter_S <= 0;
-				boot_PLL_S <= '0';
-				reset_GTX_S <= '1';
-				resetting_S <= '1';
-				startupready_S <= '0';
-				disable_GTX_reset_S <= '0';
-			elsif reset_counter_S=1000 then -- start PLL boot
-				reset_counter_S <= reset_counter_S+1;
-				boot_PLL_S <= '1';
-				timeout_counter_S <= 0;
-			elsif reset_counter_S=1002 then -- wait for PLL boot finished
-				boot_PLL_S <= '0';
-				if PLL_booting_S='1' then
-					if timeout_counter_S<65535 then
-						timeout_counter_S <= timeout_counter_S+1;
-					else
-						timeout_counter_S <= 0;
-					end if;
-				else
-					reset_counter_S <= reset_counter_S+1;
-					timeout_counter_S <= 0;
-				end if;
-			elsif reset_counter_S=10000 then -- reset GTX
-				resetting_S <= '0';
-				reset_GTX_S <= '1';
-				reset_counter_S <= reset_counter_S+1;
-			elsif reset_counter_S=10001 then -- wait for rx-locked
-				resetting_S <= '0';
-				startupready_S <= '0';
-				reset_GTX_S <= '0';
-				if rxLocked_sync_S='1' then
-					reset_counter_S <= reset_counter_S+1;
-				end if;
-			elsif reset_counter_S=11000 then -- disable resetting in GTX
-				disable_GTX_reset_S <= '1';
-				reset_counter_S <= reset_counter_S+1;
-			elsif reset_counter_S=11010 then -- switch reference clock
-				startupready_S <= '1';
-				reset_counter_S <= reset_counter_S+1;
-			elsif reset_counter_S=11080 then -- enable resetting in GTX
-				disable_GTX_reset_S <= '0';
-				reset_counter_S <= reset_counter_S+1;
-			else
-				if reset_counter_S/=65535 then 
-					reset_counter_S <= reset_counter_S+1;
-				else -- final state
-					resetting_S <= '0';
-					startupready_S <= '1';
-				end if;
-				boot_PLL_S <= '0';
-				reset_GTX_S <= '0';
-			end if;
-		else -- GEO=1
-			disable_GTX_reset_S <= '0';
-			if (S_CTRL0_S='1') or (otherFPGAnotconfigured_S='1') then
-				reset_counter_S <= 0;
-				boot_PLL_S <= '0';
-				reset_GTX_S <= '1';
-				resetting_S <= '1';
-				startupready_S <= '0';
-			elsif reset_counter_S=10000 then -- reset GTX 
-				resetting_S <= '0';
-				reset_GTX_S <= '1';
-				reset_counter_S <= reset_counter_S+1;
-			elsif reset_counter_S=10001 then -- wait for rx-locked
-				resetting_S <= '0';
-				startupready_S <= '0';
-				reset_GTX_S <= '0';
-				if rxLocked_sync_S='1' then
-					reset_counter_S <= reset_counter_S+1;
-				end if;
-			elsif reset_counter_S=11000 then -- switch reference clock
-				startupready_S <= '1';
-				reset_counter_S <= reset_counter_S+1;
-			else
-				if reset_counter_S/=65535 then 
-					reset_counter_S <= reset_counter_S+1;
-				else
-					resetting_S <= '0';
-					startupready_S <= '1';
-				end if;
-				boot_PLL_S <= '0';
-				reset_GTX_S <= '0';
-				if startupready_S='1' then
-					if rxLocked_sync_S='0' then 
-					end if;
-				end if;
-			end if;
-		end if;
-		S_CTRL0_S <= S_CTRL;
-	end if;
-end process;
-
-   -- ICAP_VIRTEX6: Internal Configuration Access Port
-   --               Virtex-6
-   -- Xilinx HDL Language Template, version 13.3
-
---   ICAP_VIRTEX6_inst : ICAP_VIRTEX6
---   generic map (
---      DEVICE_ID => X"4244093",     -- Specifies the pre-programmed Device ID value
---      ICAP_WIDTH => "X8",          -- Specifies the input and output data width to be used with the
---                                   -- ICAP_VIRTEX6.
---      SIM_CFG_FILE_NAME => "NONE"  -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
---                                   -- model
---   )
---   port map (
---      BUSY => BUSY,   -- 1-bit output: Busy/Ready output
---      O => O,         -- 32-bit output: Configuration data output bus
---      CLK => CLK,     -- 1-bit input: Clock Input
---      CSB => CSB,     -- 1-bit input: Active-Low ICAP input Enable
---      I => I,         -- 32-bit input: Configuration data input bus
---      RDWRB => RDWRB  -- 1-bit input: Read/Write Select input
---   );
-
-resync_pulse1:  posedge_to_pulse port map(
-		clock_in => ST_CLK_S,
-		clock_out => ST_CLK_S, -- clock_ADCref_S,
-		en_clk => '1',
-		signal_in => phaseSYNC_S,
-		pulse => phaseSYNCpulse_S);
-
-syncpulse_proc: process(ST_CLK_S)
-variable synccount_V : integer range 0 to 15 := 0;
-begin
-	if rising_edge(ST_CLK_S) then
-		if synccount_V<15 then
-			synccount_V := synccount_V+1;
-			external_sync_out_S <= '1';
-		else
-			external_sync_out_S <= '0';
-			if (phaseSYNCpulse_S='1') then
-				synccount_V := 0;
-			end if; 
-		end if;
-	end if;
-end process;
-
-ADCresetprocess: process(clock_ADCref_S)
-variable adcreset_counter_V : integer range 0 to 65535 := 0;
-begin
-	if rising_edge(clock_ADCref_S) then
-		if (resetting_S='1') or ((PLL_booting_S='1') and (GEO_S='0')) or (startupready_S='0') or
-				(test_resetADC_S='1') or (external_sync_out_S='1') or (external_sync_in_S='1') or
-				((phasecheck_ready1_S='0') and (GEO_S='0')) or
-				((rxLocked_sync_S='0') and (GEO_S='0'))
-				then
-			reset_ADCs_S <= '1';
-			AdcIntrfcEna_S <= '0';
-			adcreset_counter_V := 0;
-		elsif adcreset_counter_V=65335 then -- wait for lock
-			if rxLocked_sync_S='1' then
-				adcreset_counter_V := adcreset_counter_V+1;
-				reset_ADCs_S <= '0';
-			end if;
-		elsif adcreset_counter_V=65535 then
-			reset_ADCs_S <= '0';
-			AdcIntrfcEna_S <= '1';
-		else
-			adcreset_counter_V := adcreset_counter_V+1;
-		end if;
-		if GEO='1' then
-			external_sync_in_S <= external_sync_in0_S;
-		else
-			external_sync_in_S <= '0';
-		end if;
-		if (SYNC0_S='0') or (external_sync_in_S='1') or (debug_sync_S='1') then
-			SYNC1_S <= '1';
-		else
-			SYNC1_S <= '0';
-		end if;
-		phasecheck_ready1_S <= phasecheck_ready_S;
-	end if;
-end process;
-
-
---syncbuf1: IOBUFDS
---	generic map (
---		IOSTANDARD => "BLVDS_25"
---	)
---	port map (
---		O => external_sync_in0_S, -- Buffer output
---		IO => INTCOMC1_P, -- Diff_p inout (connect directly to top-level port)
---		IOB => INTCOMC1_N, -- Diff_n inout (connect directly to top-level port)
---		I => external_sync_out_S, -- Buffer input
---		T => GEO -- 3-state enable input, high=input, low=output
---	);
---
---startsuperburst1: IOBUFDS
---	generic map (
---		IOSTANDARD => "BLVDS_25"
---	)
---	port map (
---		O => superburst_start0_S, 
---		IO => INTCOMC2_P,
---		IOB => INTCOMC2_N,
---		I => superburst_startout_S,
---		T => GEO
---	);
-
-IOBUF1 : IOBUF port map (
-      O => external_sync_in0_S,     -- Buffer output
-      IO => INTCOMC1_P,   -- Buffer inout port (connect directly to top-level port)
-      I => external_sync_out_S,     -- Buffer input
-      T => GEO      -- 3-state enable input, high=input, low=output 
-   );
-	
-IOBUF2 : IOBUF port map (
-      O => superburst_start0_S,     -- Buffer output
-      IO => INTCOMC1_N,   -- Buffer inout port (connect directly to top-level port)
-      I => superburst_startout_S,     -- Buffer input
-      T => GEO      -- 3-state enable input, high=input, low=output 
-   );	
-	
-IOBUF3 : IOBUF port map (
-      O => DataTaking_enabled_in_S,     -- Buffer output
-      IO => INTCOMC2_N,   -- Buffer inout port (connect directly to top-level port)
-      I => DataTaking_enabled_out_S,     -- Buffer input
-      T => GEO      -- 3-state enable input, high=input, low=output 
-   );	
-
---INTCOMC1_P <= external_sync_out_S when GEO='0' else 'Z';
---external_sync_in0_S <= INTCOMC1_P;
---INTCOMC1_N <= superburst_startout_S when GEO='0' else 'Z';
---superburst_start0_S <= INTCOMC1_N;
---INTCOMC2_N <= DataTaking_enabled_out_S when GEO='0' else 'Z';
---DataTaking_enabled_in_S <= INTCOMC2_N;
-
-		
-process(ADC_clk_S,startupready_S)
-variable enable_data_V : std_logic := '0';
-variable DataTaking_enabled_V : std_logic := '0';
-begin
-	if (startupready_S='0') then
-		enable_data_V := '0';
-		enable_data_S <= '0';
-	elsif (rising_edge(ADC_clk_S)) then
-		enable_data_S <= DataTaking_enabled_V;
-		DataTaking_enabled_V := DataTaking_enabled_in_S;
-	end if;
-end process;
-
-process(ADC_clk_S)
-begin
-	if (rising_edge(ADC_clk_S)) then
-		superburst_start1_S <= superburst_start0_S;
-	end if;
-end process;
-
-sync_startofsuperburst: posedge_to_pulse port map(
-		clock_in => ADC_clk_S,
-		clock_out => ADC_clk_S,
-		en_clk => '1',
-		signal_in => superburst_start1_S,
-		pulse => superburst_start_S);
-
-INTCOM0_P <= superburst_out_S(0) when GEO='0' else 'Z';
-INTCOM0_N <= superburst_out_S(1) when GEO='0' else 'Z';
-INTCOM1_P <= superburst_out_S(2) when GEO='0' else 'Z';
-INTCOM1_N <= superburst_out_S(3) when GEO='0' else 'Z';
-INTCOM2_P <= superburst_out_S(4) when GEO='0' else 'Z';
-INTCOM2_N <= superburst_out_S(5) when GEO='0' else 'Z';
-INTCOM3_P <= superburst_out_S(6) when GEO='0' else 'Z';
-INTCOM3_N <= superburst_out_S(7) when GEO='0' else 'Z';
-INTCOM4_P <= superburst_out_S(8) when GEO='0' else 'Z';
-INTCOM4_N <= superburst_out_S(9) when GEO='0' else 'Z';
-INTCOM5_P <= superburst_out_S(10) when GEO='0' else 'Z';
-INTCOM5_N <= superburst_out_S(11) when GEO='0' else 'Z';
-INTCOM6_P <= superburst_out_S(12) when GEO='0' else 'Z';
-INTCOM6_N <= superburst_out_S(13) when GEO='0' else 'Z';
-INTCOM7_P <= superburst_out_S(14) when GEO='0' else 'Z';
-INTCOM7_N <= superburst_out_S(15) when GEO='0' else 'Z';
-
-superburst_in_S(0) <= INTCOM0_P;
-superburst_in_S(1) <= INTCOM0_N;
-superburst_in_S(2) <= INTCOM1_P;
-superburst_in_S(3) <= INTCOM1_N;
-superburst_in_S(4) <= INTCOM2_P;
-superburst_in_S(5) <= INTCOM2_N;
-superburst_in_S(6) <= INTCOM3_P;
-superburst_in_S(7) <= INTCOM3_N;
-superburst_in_S(8) <= INTCOM4_P;
-superburst_in_S(9) <= INTCOM4_N;
-superburst_in_S(10) <= INTCOM5_P;
-superburst_in_S(11) <= INTCOM5_N;
-superburst_in_S(12) <= INTCOM6_P;
-superburst_in_S(13) <= INTCOM6_N;
-superburst_in_S(14) <= INTCOM7_P;
-superburst_in_S(15) <= INTCOM7_N;
-superburst_in_S(30 downto 16) <= (others => '0');
-	
-sync_SYNC_stclk_S:  posedge_to_pulse port map(
-		clock_in => clock_ADCref_S,
-		clock_out => ST_CLK_S,
-		en_clk => '1',
-		signal_in => SYNC1_S,
-		pulse => SYNC2_S);
-
-SYNC <= not SYNC2_S;
-
-
-process(rxSodaClk40_S)
-begin
-	if (rising_edge(rxSodaClk40_S)) then 
-		rxSodaClkdiv4_S <= not rxSodaClkdiv4_S;
-	end if;
-end process;
-process(GCLK_S)
-begin
-	if (rising_edge(GCLK_S)) then
-		if GCLKdiv2_S='1' then
-			GCLKdiv4_S <= not GCLKdiv4_S;
-		end if;
-		GCLKdiv2_S <= not GCLKdiv2_S;
-	end if;
-end process;
-phaseerr_max_S <= 50 when vioword_S(23 downto 16)=x"00" else conv_integer(unsigned(vioword_S(23 downto 16)));
-phasedet_S <= '1' when GCLKdiv4_S/=rxSodaClkdiv4_S else '0';
-process(ST_CLK_S)
-variable waitcounter_V : integer range 0 to 155520 := 0;
-begin
-	if (rising_edge(ST_CLK_S)) then
-		if (resetting_stclk_S='1') or (selectPLLclk_stclk_S='0') or (GEO_stclk_S='1') then
-			waitcounter_V := 0;
-			phasedet_count_S <= 0;
-			phaseerr_count_S <= 0;
-			phasecheckcounter_S <= 0;
-			phaseSYNC_S <= '0';
-		elsif (waitcounter_V<155520) then -- *(1+conv_integer(unsigned(vioword_S(27 downto 24))))) then
-			waitcounter_V := waitcounter_V+1;
-			phasedet_count_S <= 0;
-			phaseerr_count_S <= 0;
-			phasecheckcounter_S <= 0;
-			phaseSYNC_S <= '0';
-		elsif (waitcounter_V=155520) then -- always one syncpulse
-			waitcounter_V := waitcounter_V+1;
-			phasedet_count_S <= 0;
-			phaseerr_count_S <= 0;
-			phasecheckcounter_S <= 0;
-			phaseSYNC_S <= '1';
-		else
-			if phasedet_count_S=1023 then
-				if phasecheckcounter_S<255 then
-					phasecheck_ready_S <= '0';
-					phasecheckcounter_S <= phasecheckcounter_S+1;
-					if (phaseerr_count_S>phaseerr_max_S) then
-						if vioword_S(5)='0' then
-							phaseSYNC_S <= '1';
-							waitcounter_V := 0;
-						else
-							phaseSYNC_S <= '0';
-						end if;
-					else
-						phaseSYNC_S <= '0';
-					end if;
-				else
-					phasecheck_ready_S <= '1';
-					if (phaseerr_count_S>200) then
---					if (phaseerr_count_S>400) then
-						if vioword_S(5)='0' then
-							phaseSYNC_S <= '1';
-							waitcounter_V := 0;
-						else
-							phaseSYNC_S <= '0';
-						end if;
-					else
-						phaseSYNC_S <= '0';
-					end if;
-				end if;
-				phasedet_count_S <= 0;
-				if phasedet_S='1' then
-					phaseerr_count_S <= 1;
-				else
-					phaseerr_count_S <= 0;
-				end if;
-			else
-				phaseSYNC_S <= '0';
-				phasedet_count_S <= phasedet_count_S+1;
-				if phasedet_S='1' then
-					phaseerr_count_S <= phaseerr_count_S+1;
-				end if;
-			end if;
-		end if;
-		resetting_stclk_S <= resetting_S;
-		selectPLLclk_stclk_S <= selectPLLclk_S;
-		GEO_stclk_S <= GEO;
-	end if;
-end process;
-
-
-gclk_div10_process: process(GCLK_S)
-variable counter_V : integer range 0 to 99 := 0;
-begin
-	if (rising_edge(GCLK_S)) then 
-		if counter_V<49 then -- 99 for 125MHz
-			counter_V := counter_V+1;
-		else
-			counter_V := 0;
-			GCLKdiv10_S <= not GCLKdiv10_S;
-		end if;
-	end if;
-end process;
-checkfrequency_process: process(ST_CLK_S)
-variable counter_V : integer range 0 to 255 := 0;
-variable first_check_V : integer range 0 to 7 := 0;
-begin
-	if (rising_edge(ST_CLK_S)) then 
-		if (resetting_stclk_S='1') or (selectPLLclk_stclk_S='0') or (GEO_stclk_S='1') then
-			PLLfrequencyERROR_S <= '0';
-			first_check_V := 0;
-		else
-			if GCLKdiv10_prev1_S/=GCLKdiv10_prev2_S then
-				if (((counter_V>=122) or (counter_V<=125)) and (ADCCLOCKFREQUENCY=62500000)) or 
-					(((counter_V>=96) or (counter_V<=99)) and (ADCCLOCKFREQUENCY=80000000)) then				
-					PLLfrequencyERROR_S <= '0';					
-					if first_check_V/=7 then
-						first_check_V := first_check_V+1;
-					end if;
-				else
-					if first_check_V=7 then
-						PLLfrequencyERROR_S <= '1';
-						first_check_V := 0;
-					else
-						first_check_V := first_check_V+1;
-					end if;
-				end if;
-				counter_V := 0;
-			elsif counter_V<255 then
-				counter_V := counter_V+1;
-			end if;
-		end if;
-		GCLKdiv10_prev2_S <= GCLKdiv10_prev1_S;
-		GCLKdiv10_prev1_S <= GCLKdiv10_S;
-	end if;
-end process;
-
-external_PLL: LMK03806 port map(
-		clock => clock_ADCref_S,   
-		CLKu => CLKu_S,
-		DATAu => DATAu_S,
-		LEu => LEu_S,
-		RDn => RDu,
-		SYNC => SYNC0_S,
-		boot_PLL => boot_PLL_S,
-		reset_GTX => open, -- reset_GTX_S,	
-		reset_ADCs => open, -- reset_ADCs0_S,
-		booting => PLL_booting_S,
-		testwordin => vioword2_S(15 downto 0));
-CLKu <= CLKu_S;
-DATAu <= DATAu_S;
-LEu <= LEu_S;
-
--- ADC configuration --------------------------------------------------------------
-		SCK <= '0'; -- 2-lane 16-bits serialization
-		SDI <= '0'; -- normal mode (not sleeping)
-		CSA <= (others => '0'); -- 2-lane 16-bits serialization
-		CSB <= (others => '0'); -- 2-lane 16-bits serialization
-		SDOA <= (others => '0'); -- no internal termination
-		SDOB <= (others => '0'); -- no internal termination
-
-
-
-GTX_refclock: IBUFDS_GTXE1 port map(
-		O => gtpClk_S,
-		ODIV2 => open,
-		CEB => '0',
-		I => MGTREFCLK_P,
-		IB => MGTREFCLK_N);
-
---select_RCV_CLK : BUFGMUX_CTRL port map(
---      O => RCV_CLK_S,
---      I0 => clock_ADCref_S,
---      I1 => rxSodaClk80_S,
---      S => selectPLLclk_S); ---- rxLocked_S);
---RCV_CLK_S <= clock_ADCref_S;	
-process (clock_ADCref_S)
-begin
-	if (rising_edge(clock_ADCref_S)) then 
-		if vioword_S(11)='0' then
-			if (startupready_S='1') and (rxLocked_S='1') then
-				selectPLLclk_S <= '1';
-			else 
-				selectPLLclk_S <= '0';
-			end if;
-		else
-			selectPLLclk_S <= vioword_S(10); --//
-		end if;
-	end if;
-end process;
-	
---rxRecClk40_BUFG: BUFG port map(
---		I => rxSodaClk40_S,
---		O => rxSodaClk40b_S);
---clockmodule40to80_1: clockmodule40to80 port map(
---  CLK_IN1 => rxSodaClk40b_S,
---  CLK_OUT1 => rxSodaClk80_S,
---  LOCKED => open);
-
-clockmodule40switch1: clockmodule40switch port map(
-		CLK_IN1 => rxSodaClk40_S,
-		CLK_IN2 => clock_ADCrefdiv2_S,
-		CLK_IN_SEL => selectPLLclk_S,
-		CLK_OUT1 => RCV_CLK_S,
-		CLK_OUT2 => open,
-		RESET => '0',
-		LOCKED => clockswitch_locked_S);
-
---process (clock_ADCref_S)
---begin
---	if (rising_edge(clock_ADCref_S)) then 
---		RCV_CLKref_S <= not RCV_CLKref_S;
---	end if;
---end process;
---process (rxSodaClk80_S)
---begin
---	if (rising_edge(rxSodaClk80_S)) then 
---		RCV_CLKrx_S <= not RCV_CLKrx_S;
---	end if;
---end process;
---RCV_CLK_S <= RCV_CLKrx_S when selectPLLclk_S='1' else RCV_CLKref_S;	
---
---U2 : OBUFDS port map( -- OBUFDS_LVDSEXT_33
---		I	=> RCV_CLK_S,
---		O	=> RCV_CLK_P,
---		OB	=> RCV_CLK_N);
-		
-
-RCV_CLK_not_S <= not RCV_CLK_S;
-U1 : FDDRRSE port map(
-		Q => RCV_CLK_P_S,
-		C0 => RCV_CLK_S,
-		C1 => RCV_CLK_not_S,
-		CE => '1',  -- 1 for fpga1   not GEO, -- 
-		D0 => '1',  -- 1 for fpga1  not GEO, -- 
-		D1 => '0',
-		R => '0',
-		S => '0');		
-U2 : OBUFDS port map( -- OBUFDS_LVDSEXT_33
-		I	=> RCV_CLK_P_S,
-		O	=> RCV_CLK_P,
-		OB	=> RCV_CLK_N);
-			
-
-
-LOS_S <= '1' when (LOS='1') or (MOD_DEF(0)='1') else '0';
-TX_DIS <= '0'; -- SFP always enabled
-
-process(ADC_clk_S) -- synchronise to 1 clock
-begin
-	if (rising_edge(ADC_clk_S)) then 
-		reset_FEE_ADCclk_S <= reset_FEE_S;
-		ADCs_enable_S <= AdcIntrfcEna_S;
-	end if;
-end process;
-
-FEE_ADCinput_module1: FEE_ADCinput_module port map(
-		clock200MHz => clock200MHz_S,
-		reset => reset_ADCs_S,
-		ADCs_enable => ADCs_enable_S,
-----ADC1---------------------------------------------		
-		AD11A_P => AD11A_P,
-		AD11A_N => AD11A_N,
-		AD11B_P => AD11B_P,
-		AD11B_N => AD11B_N,
-		AD12A_P => AD12A_P,
-		AD12A_N => AD12A_N,
-		AD12B_P => AD12B_P,
-		AD12B_N => AD12B_N,
-		AD13A_P => AD13A_P,
-		AD13A_N => AD13A_N,
-		AD13B_P => AD13B_P,
-		AD13B_N => AD13B_N,
-		AD14A_P => AD14A_P,
-		AD14A_N => AD14A_N,
-		AD14B_P => AD14B_P,
-		AD14B_N => AD14B_N,
-		AD15A_P => AD15A_P,
-		AD15A_N => AD15A_N,
-		AD15B_P => AD15B_P,
-		AD15B_N => AD15B_N,
-		AD16A_P => AD16A_P,
-		AD16A_N => AD16A_N,
-		AD16B_P => AD16B_P,
-		AD16B_N => AD16B_N,
-		AD17A_P => AD17A_P,
-		AD17A_N => AD17A_N,
-		AD17B_P => AD17B_P,
-		AD17B_N => AD17B_N,
-		AD18A_P => AD18A_P,
-		AD18A_N => AD18A_N,
-		AD18B_P => AD18B_P,
-		AD18B_N => AD18B_N,
-
-		DCOA1_P => DCOA1_P,
-		DCOA1_N => DCOA1_N,
-		DCOB1_P => DCOB1_P,
-		DCOB1_N => DCOB1_N,
-
-		FRA1_P  => FRA1_P ,
-		FRA1_N  => FRA1_N ,
-		FRB1_P  => FRB1_P ,
-		FRB1_N  => FRB1_N ,
-
-		----ADC2---------------------------------------------
-		AD21A_P => AD21A_P,
-		AD21A_N => AD21A_N,
-		AD21B_P => AD21B_P,
-		AD21B_N => AD21B_N,
-		AD22A_P => AD22A_P,
-		AD22A_N => AD22A_N,
-		AD22B_P => AD22B_P,
-		AD22B_N => AD22B_N,
-		AD23A_P => AD23A_P,
-		AD23A_N => AD23A_N,
-		AD23B_P => AD23B_P,
-		AD23B_N => AD23B_N,
-		AD24A_P => AD24A_P,
-		AD24A_N => AD24A_N,
-		AD24B_P => AD24B_P,
-		AD24B_N => AD24B_N,
-		AD25A_P => AD25A_P,
-		AD25A_N => AD25A_N,
-		AD25B_P => AD25B_P,
-		AD25B_N => AD25B_N,
-		AD26A_P => AD26A_P,
-		AD26A_N => AD26A_N,
-		AD26B_P => AD26B_P,
-		AD26B_N => AD26B_N,
-		AD27A_P => AD27A_P,
-		AD27A_N => AD27A_N,
-		AD27B_P => AD27B_P,
-		AD27B_N => AD27B_N,
-		AD28A_P => AD28A_P,
-		AD28A_N => AD28A_N,
-		AD28B_P => AD28B_P,
-		AD28B_N => AD28B_N,
-
-		DCOA2_P => DCOA2_P,
-		DCOA2_N => DCOA2_N,
-		DCOB2_P => DCOB2_P,
-		DCOB2_N => DCOB2_N,
-
-		FRA2_P  => FRA2_P ,
-		FRA2_N  => FRA2_N ,
-		FRB2_P  => FRB2_P ,
-		FRB2_N  => FRB2_N ,
-
-		----ADC3---------------------------------------------
-		AD31A_P => AD31A_P,
-		AD31A_N => AD31A_N,
-		AD31B_P => AD31B_P,
-		AD31B_N => AD31B_N,
-		AD32A_P => AD32A_P,
-		AD32A_N => AD32A_N,
-		AD32B_P => AD32B_P,
-		AD32B_N => AD32B_N,
-		AD33A_P => AD33A_P,
-		AD33A_N => AD33A_N,
-		AD33B_P => AD33B_P,
-		AD33B_N => AD33B_N,
-		AD34A_P => AD34A_P,
-		AD34A_N => AD34A_N,
-		AD34B_P => AD34B_P,
-		AD34B_N => AD34B_N,
-		AD35A_P => AD35A_P,
-		AD35A_N => AD35A_N,
-		AD35B_P => AD35B_P,
-		AD35B_N => AD35B_N,
-		AD36A_P => AD36A_P,
-		AD36A_N => AD36A_N,
-		AD36B_P => AD36B_P,
-		AD36B_N => AD36B_N,
-		AD37A_P => AD37A_P,
-		AD37A_N => AD37A_N,
-		AD37B_P => AD37B_P,
-		AD37B_N => AD37B_N,
-		AD38A_P => AD38A_P,
-		AD38A_N => AD38A_N,
-		AD38B_P => AD38B_P,
-		AD38B_N => AD38B_N,
-
-		DCOA3_P => DCOA3_P,
-		DCOA3_N => DCOA3_N,
-		DCOB3_P => DCOB3_P,
-		DCOB3_N => DCOB3_N,
-
-		FRA3_P  => FRA3_P ,
-		FRA3_N  => FRA3_N ,
-		FRB3_P  => FRB3_P ,
-		FRB3_N  => FRB3_N ,
-
-		----ADC4---------------------------------------------
-		AD41A_P => AD41A_P,
-		AD41A_N => AD41A_N,
-		AD41B_P => AD41B_P,
-		AD41B_N => AD41B_N,
-		AD42A_P => AD42A_P,
-		AD42A_N => AD42A_N,
-		AD42B_P => AD42B_P,
-		AD42B_N => AD42B_N,
-		AD43A_P => AD43A_P,
-		AD43A_N => AD43A_N,
-		AD43B_P => AD43B_P,
-		AD43B_N => AD43B_N,
-		AD44A_P => AD44A_P,
-		AD44A_N => AD44A_N,
-		AD44B_P => AD44B_P,
-		AD44B_N => AD44B_N,
-		AD45A_P => AD45A_P,
-		AD45A_N => AD45A_N,
-		AD45B_P => AD45B_P,
-		AD45B_N => AD45B_N,
-		AD46A_P => AD46A_P,
-		AD46A_N => AD46A_N,
-		AD46B_P => AD46B_P,
-		AD46B_N => AD46B_N,
-		AD47A_P => AD47A_P,
-		AD47A_N => AD47A_N,
-		AD47B_P => AD47B_P,
-		AD47B_N => AD47B_N,
-		AD48A_P => AD48A_P,
-		AD48A_N => AD48A_N,
-		AD48B_P => AD48B_P,
-		AD48B_N => AD48B_N,
-
-		DCOA4_P => DCOA4_P,
-		DCOA4_N => DCOA4_N,
-		DCOB4_P => DCOB4_P,
-		DCOB4_N => DCOB4_N,
-
-		FRA4_P  => FRA4_P ,
-		FRA4_N  => FRA4_N ,
-		FRB4_P  => FRB4_P ,
-		FRB4_N  => FRB4_N ,
-
-		ADC_clk => ADC_clk_S,
-		ADCs_ready => ADCs_ready_S,
-		adcdata => adcdata_S
-		);
-
-gen_FEE: if DEBUG=false generate
-FEE_module1: FEE_adc32_module port map(
-		clock => ADC_clk_S,
-		reset => reset_FEE_ADCclk_S,
-		enable_data => enable_data_S,
-		ADCdata => adcdata_S,
-		superburst_start => superburst_start_S,
-		superburst_received => superburst_in_S,
-		onesecondpulse => onesecondpulse_S,
-		rxNotInTable => rxNotInTable_S,
-		startupready => startupready_S,
-		request_init => request_init_S,
-		packet_in_data => packet_in_data_S,
-		packet_in_present => packet_in_present_S,
-		packet_in_read => packet_in_read_S,
-		packet_out_data => packet_out_data_S,
-		packet_out_last => packet_out_last_S,
-		packet_out_write => packet_out_write_S,
-		packet_out_fifofull => packet_out_fifofull_S,
-		errorbyte_out => errorbyte_S,
-		errorbyte_in => errorbyte_S,
-		smaart_in => '0', -- TEMP_OUT,
-		smaart_out => open,
-		sysmon_data => sysmon_data_S,
-		sysmon_reset => sysmon_reset_S,
-		sysmon_address => sysmon_address_S,
-		sysmon_read => sysmon_read_S,
-		testindex => conv_integer(unsigned(vioword_S(15 downto 12))),
-		testword0 => open,
-		testword1 => open, 
-		testword2 => open
-	); -- TEMP_IN);
-end generate;
-
-gen_second_FE_module: if SECOND_FE_MODULE=TRUE generate
-
-
-	FEE_module2: FEE_adc32_module port map(
-			clock => ADC_clk_S,
-			reset => reset_FEE_ADCclk2_S,
-			enable_data => enable_data_S,
-			ADCdata => adcdata2_S,
-			superburst_start => superburst_start_S,
-			superburst_received => superburst_in_S,
-			onesecondpulse => onesecondpulse_S,
-			rxNotInTable => rxNotInTable_S,
-			startupready => startupready_S,
-			request_init => request_init_S,
-			packet_in_data => packet_in_data_S,
-			packet_in_present => packet_in_present_S,
-			packet_in_read => packet_in_read2_S,
-			packet_out_data => packet_out_data2_S,
-			packet_out_last => packet_out_last2_S,
-			packet_out_write => packet_out_write2_S,
-			packet_out_fifofull => packet_out_fifofull_S,
-			errorbyte_out => open,
-			errorbyte_in => errorbyte_S,
-			smaart_in => '0', -- TEMP_OUT,
-			smaart_out => open,
-			sysmon_data => sysmon_data_S,
-			sysmon_reset => open,
-			sysmon_address => open,
-			sysmon_read => open,
-			testindex => conv_integer(unsigned(vioword_S(15 downto 12))),
-			testword0 => open,
-			testword1 => testword0b_S, -- testword0_S,
-			testword2 => open
-		); -- TEMP_IN);
-
-	reset_FEE_ADCclk2_S <= '1' when (reset_FEE_ADCclk_S='1') or (reset_FEE_ADCclk2a_S='1') else '0';
-	zero_data_S <= '1' when (vioword_S(9)='1') else '0';
-	adcdata2_S <= adcdata_S when zero_data_S='0' else (others => (others => '0'));
-
-	process(ADC_clk_S) 
-	begin
-		if (rising_edge(ADC_clk_S)) then 
-			unequal_S <= '0';
-			request_init_S <= '0';
-			if (zero_data_S='1') or (reset_FEE_ADCclk_S='1') or (vioword_S(8)='1') then
-				unequal_counter_S <= (others => '0');
-				reset_FEE_ADCclk2a_S <= '1';
-				unequal_time_S <= (others => '0');
-			else
-				if unequal_counter_S(31 downto 0)=x"0000000f" then
-					reset_FEE_ADCclk2a_S <= '0';
-				end if;
-				if unequal_counter_S=x"000000ff" then
-					request_init_S <= '1';
-				end if;
-				if (packet_in_read2_S/=packet_in_read_S) or 
-					(packet_out_data2_S/=packet_out_data_S) or 
-					(packet_out_last2_S/=packet_out_last_S) or 
-					(packet_out_write2_S/=packet_out_write_S) then
-					unequal_time_S <= unequal_counter_S;
-					unequal_S <= '1';
-				end if;
-				if unequal_counter_S/=x"ffffffff" then
-					unequal_counter_S <= unequal_counter_S+1;
-				end if;
-			end if;
-		end if;
-	end process;
-
-end generate;
-
-process(ADC_clk_S)
-variable counter : integer range 0 to ADCCLOCKFREQUENCY-1 := 0;
-begin
-	if (rising_edge(ADC_clk_S)) then 
-		if counter/=0 then
-			counter := counter-1;
-			onesecondpulse_S <= '0';
-		else
-			counter := ADCCLOCKFREQUENCY-1;
-			onesecondpulse_S <= '1';
-		end if;
-	end if;
-end process;
-		
-FEE_gtxModule1: FEE_gtxModule port map(
-		gtpClk => gtpClk_S,
-		asyncclk => clock_ADCref_S,
-		reset => reset_GTX_S,
-		disable_GTX_reset => disable_GTX_reset_S,
-		TX_DLM => TX_DLM_S,
-		TX_DLM_WORD => TX_DLM_WORD_S,
-		RX_DLM => RX_DLM_S,
-		RX_DLM_WORD => RX_DLM_WORD_S,
-		txAsyncClk => ADC_clk_S,
-		txAsyncData => packet_out_data_S,
-		txAsyncDataWrite => packet_out_write_S,
-		txAsyncLastData => packet_out_last_S,
-		txAsyncFifoFull => packet_out_fifofull_S,	
-		txUsrClk => txUsrClk_S,
-		txLocked => open,
-		rxAsyncClk => ADC_clk_S,
-		rxAsyncData => packet_in_data_S,
-		rxAsyncDataRead => packet_in_read_S,
-		rxNotInTable => rxNotInTable0_S,
-		rxAsyncDataOverflow => open,
-		rxAsyncDataPresent => packet_in_present_S,
-		rxSodaClk => rxSodaClk_S,
-		rxSodaClk40 => rxSodaClk40_S,
-		rxLocked => rxLocked0_S,
-		gtpTxP0 => TX_P,
-		gtpTxN0 => TX_N,
-		gtpRxP0 => RX_P,
-		gtpRxN0 => RX_N,
-		testword0 => testwordb_S -- testword0(35 downto 0)
-	);
-
-posedge_to_pulse_notintable: posedge_to_pulse port map(
-    clock_in => rxSodaClk_S,
-    clock_out => ADC_clk_S,
-    en_clk => '1',
-    signal_in => rxNotInTable0_S,
-    pulse => rxNotInTable_S);
-
-rxLocked_S <= '1' when ((rxLocked0_S='1') or (disable_GTX_reset_S='1')) and (LOS_S='0') else '0';
-
-
-datatakingprocess: process(rxSodaClk_S)
-begin
-	if (rising_edge(rxSodaClk_S)) then 
-		if DisableDataTaking_S='1' then
-			DataTaking_enabled_out_S <= '0';
-		elsif EnableDataTaking_S='1' then
-			DataTaking_enabled_out_S <= '1';
-		end if;		
-	end if;
-end process;
-
-
-process(rxSodaClk_S)
-begin
-	if (rising_edge(rxSodaClk_S)) then
-		reset_rxSodaClk_S <= reset_S;
-	end if;
-end process;
-
- 
-posedge_to_pulse_superburst_startout: posedge_to_pulse port map(
-    clock_in => rxSodaClk_S,
-    clock_out => ADC_clk_S,
-    en_clk => '1',
-    signal_in => superburst_startout0_S,
-    pulse => superburst_startout_S);
-	 
-soda_FEE_endpoint1: soda_FEE_endpoint port map(
-		SYSCLK => rxSodaClk_S,
-		RESET => reset_rxSodaClk_S,
-		CLEAR	=> '0',
-		CLK_EN => '1',
-		RX_DLM_WORD_IN => RX_DLM_WORD_S,
-		RX_DLM_IN => RX_DLM_S,
-		TX_DLM_OUT => TX_DLM_S,
-		TX_DLM_WORD_OUT => TX_DLM_WORD_S,
-		START_OF_SUPERBURST => superburst_startout0_S,
-		SUPER_BURST_NR => superburst_out_S,
-		SODA_CMD_VALID => SODA_cmd_valid_S,
-		SODA_CMD_WORD => SODA_cmd_word_S,
-		STAT => open);
---ResetToZero_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(30)='1') else '0'; -- reset timestamp to I/O pin
-EnableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(29)='1') else '0';
-DisableDataTaking_S <= '1' when (SODA_cmd_valid_S='1') and (SODA_cmd_word_S(28)='1') else '0';
-
-SystemMonitorModule1: SystemMonitorModule port map(
-		clock => ADC_clk_S,
-		reset => sysmon_reset_S,
-		address => sysmon_address_S,
-		data_write => '0',
-		data_in => (others => '0'),
-		data_read => sysmon_read_S,
-		data_out => sysmon_data_S,
-		alarms => open,
-		testword0 => open);
-
-
-icon1: icon0 port map(
-	CONTROL0 => control0_S,
-	CONTROL1 => control1_S,
-	CONTROL2 => control2_S,
-	CONTROL3 => control3_S,
-	CONTROL4 => control4_S);
-
-ila36_1: ila36 port map(
-	CONTROL => control0_S,
-	CLK => txUsrClk_S, -- ADC_clk_S, -- ST_CLK_S, 
-	TRIG0 => testword1_S); -- testword0_S
-
-ila36_2: ila36 port map(
-	CONTROL => control1_S,
-	CLK => rxSodaClk_S, -- clock_ADCref_S, -- ADC_clk_S, ,clock_ADCref_S
-	TRIG0 => testword1_S);
-	
-ila128_1: ila128 port map(
-	CONTROL => control2_S,
-	CLK => clock_ADCref_S, -- ADC_clk_S,
-	TRIG0 => testword2_S); -- (others => '0')); -- 
-
-vio36_1: vio36 port map (
-	CONTROL => control3_S,
-	ASYNC_OUT => vioword_S);
-	
-vio36_2: vio36 port map (
-	CONTROL => control4_S,
-	ASYNC_OUT => vioword2_S);
-	
---testword0_S(31 downto 0) <= unequal_time_S;
---testword0_S(32) <= reset_FEE_ADCclk2_S;
---testword0_S(33) <= zero_data_S;
---testword0_S(34) <= unequal_S;
---testword0_S(35) <= '1' when unequal_counter_S=x"ffffffff" else '0';
-
--- testword0_S <= testword0a_S when vioword_S(10)='0' else testword0b_S;
-
-testclocks_S(0) <= clock_ADCref_S;
-testclocks_S(1) <= clock_ADCrefdiv2_S;
-testclocks_S(2) <= clock100MHz_S;
-testclocks_S(3) <= clock200MHz_S;
-testclocks_S(4) <= RCV_CLK_S;
-testclocks_S(5) <= GCLK_S;
-testclocks_S(6) <= rxSodaClk_S;
-testclocks_S(7) <= rxSodaClk40_S;
-testclocks_S(8) <= ADC_clk_S;
-gen_testclocks: for i in 0 to 8 generate
-process(testclocks_S(i))
-variable cnt_V : integer range 0 to 99 := 0;
-begin
-	if (rising_edge(testclocks_S(i))) then 
-		if cnt_V<99 then
-			cnt_V := cnt_V+1;
-		else
-			cnt_V := 0;
-			testclockDiv100_S(i) <= not testclockDiv100_S(i);
-		end if;
-	end if;
-end process;
-end generate;
---testword0_S(8 downto 0) <= testclockDiv100_S;
---testword0_S(9) <= LOS_S;
---testword0_S(10) <= rxLocked_S;
---testword0_S(11) <= rxLocked0_S;
---testword0_S(12) <= rxLocked_sync_S;
---testword0_S(13) <= selectPLLclk_S;
---testword0_S(14) <= rxLocked_S;
---testword0_S(23 downto 16) <= RX_DLM_WORD_S;
---testword0_S(24) <= RX_DLM_S;
---testword0_S(32 downto 25) <= TX_DLM_WORD_S;
---testword0_S(33) <= TX_DLM_S;
---testword0_S(34) <= superburst_startout_S;
---testword0_S(35) <= SODA_cmd_valid_S;
-
-testword0_S(15 downto 0) <= superburst_out_S(15 downto 0);
-testword0_S(31 downto 16) <= superburst_in_S(15 downto 0);
-testword0_S(32) <= superburst_startout_S;
-testword0_S(33) <= superburst_start0_S;
-testword0_S(34) <= superburst_start1_S;
-testword0_S(35) <= superburst_start_S;
-
-
---testword2_S(31 downto 0) <= unequal_time_S;
---testword2_S(32) <= reset_FEE_ADCclk2_S;
---testword2_S(33) <= zero_data_S;
---testword2_S(34) <= unequal_S;
---testword2_S(35) <= '1' when unequal_counter_S=x"ffffffff" else '0';
---testword2_S(67 downto 36) <= packet_out_data_S;
---testword2_S(68) <= packet_out_write_S;
---testword2_S(69) <= packet_out_last_S;
---testword2_S(70) <= packet_out_fifofull_S;
---testword2_S(71) <= '0';
---testword2_S(103 downto 72) <= packet_out_data2_S;
---testword2_S(104) <= packet_out_write2_S;
---testword2_S(105) <= packet_out_last2_S;
---testword2_S(106) <= packet_out_fifofull_S;
---testword2_S(107) <= '0';
-
-testword1_S(30 downto 0) <= testwordb_S(30 downto 0);		
-testword1_S(31) <= errorbyte_S(0);		
-testword1_S(32) <= errorbyte_S(1);		
-testword1_S(33) <= errorbyte_S(2);		
-testword1_S(34) <= errorbyte_S(4);		
-testword1_S(35) <= errorbyte_S(6);		
-
-testword2_S(0) <= rxLocked_sync_S; -- coldstart_S;
-testword2_S(1) <= reset_S;
-testword2_S(2) <= resetting_S;
-testword2_S(3) <= reset_GTX_S; -- IcontrolPLL_S;
-testword2_S(4) <= reset_ADCs_S; -- otherFPGAnotconfigured0_S;
-testword2_S(5) <= otherFPGAnotconfigured_S;
-testword2_S(6) <= PLLconfigured_S;
-testword2_S(7) <= selectPLLclk_S;
-testword2_S(8) <= startupready_S; -- T_CTRL_S;
-testword2_S(9) <= external_sync_in_S; 
-testword2_S(10) <= rxLocked_S;
-testword2_S(11) <= S_CTRL0_S;
-testword2_S(12) <= boot_PLL_S;
-testword2_S(13) <= PLL_booting_S;
-testword2_S(14) <= adcintrfcena_s;
-testword2_S(15) <= phasecheck_ready1_S;
-testword2_S(16) <= GCLKdiv4_S; --reset_GTX_S;
-testword2_S(17) <= rxSodaClkdiv4_S; --ADCs_ready_S;
-testword2_S(18) <= '1' when phasedet_count_S=1023 else '0'; --GEO;
-testword2_S(19) <= '1' when phasecheckcounter_S<255 else '0'; -- PLLfrequencyERROR_S;
-testword2_S(20) <= SYNC_S;
-testword2_S(21) <= PLLfrequencyERROR_S;
-testword2_S(22) <= phasedet_S;
-testword2_S(23) <= phaseSYNC_S;
-testword2_S(24) <= clockswitch_locked_S;
-testword2_S(25) <= phaseSYNCpulse_S;
-testword2_S(35 downto 26) <= conv_std_logic_vector(phaseerr_count_S,10);
-
-selectnr_S <= conv_integer(vioword_S(35 downto 34));
-
-generatetest1 : for index in 0 to 7 generate
---	testword2_S(index*16+13 downto index*16+0) <= adcdata_S(selectnr_S*8+index)(13 downto 0);
---	testword2_S(index*16+15 downto index*16+14) <= (others => '0');
-end generate;
-	
-forced_reset_S <= vioword_S(0);
-
-process(clock_ADCref_S)
-variable prev_vioword2 : std_logic := '0';
-variable prev_vioword3 : std_logic := '0';
-begin
-	if (rising_edge(clock_ADCref_S)) then 
-		if prev_vioword2 /= vioword_S(2) then
-			test_resetADC_S <= '1';
-		else
-			test_resetADC_S <= '0';
-		end if;
-		prev_vioword2 := vioword_S(2);
-		if prev_vioword3 /= vioword_S(3) then
-			debug_sync_S <= '1';
-		else
-			debug_sync_S <= '0';
-		end if;
-		prev_vioword3 := vioword_S(3);
-	end if;
-end process;
-
-process(ST_CLK_S)
-begin
-	if (rising_edge(ST_CLK_S)) then 
-		testclockDiv2_S(0) <= not testclockDiv2_S(0);
-	end if;
-end process;
-process(clock_ADCref_S)
-begin
-	if (rising_edge(clock_ADCref_S)) then 
-		testclockDiv2_S(1) <= not testclockDiv2_S(1);
-	end if;
-end process;
-process(clock_ADCrefdiv2_S)
-begin
-	if (rising_edge(clock_ADCrefdiv2_S)) then 
-		testclockDiv2_S(2) <= not testclockDiv2_S(2);
-	end if;
-end process;
-process(RCV_CLK_S) 
-begin
-	if (rising_edge(RCV_CLK_S)) then
-		testclockDiv2_S(3) <= not testclockDiv2_S(3);
-	end if;
-end process;
-process(GCLK_S)
-begin
-	if (rising_edge(GCLK_S)) then 
-		testclockDiv2_S(4) <= not testclockDiv2_S(4);
-	end if;
-end process;
-process(rxSodaClk_S)
-begin
-	if (rising_edge(rxSodaClk_S)) then 
-		testclockDiv2_S(5) <= not testclockDiv2_S(5);
-	end if;
-end process;
-process(txUsrClk_S)
-begin
-	if (rising_edge(txUsrClk_S)) then 
-		testclockDiv2_S(6) <= not testclockDiv2_S(6);
-	end if;
-end process;
-process(ADC_clk_S)
-begin
-	if (rising_edge(ADC_clk_S)) then 
-		testclockDiv2_S(7) <= not testclockDiv2_S(7);
-	end if;
-end process;
-
-
-SM1_P <= testclockDiv2_S(conv_integer(unsigned(vioword_S(32 downto 30))));
-SM1_N <= testclockDiv2_S(conv_integer(unsigned(vioword_S(32 downto 30))));
-
---SM3_P <= '0'; -- testclockDiv2_S(conv_integer(unsigned(vioword_S(31 downto 30))));
---SM3_N <= '0'; -- testclockDiv2_S(conv_integer(unsigned(vioword_S(31 downto 30))));
-
-
-end Behavioral;
-
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.asy b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.asy
deleted file mode 100644
index b5b3c4e..0000000
--- a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.asy
+++ /dev/null
@@ -1,17 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 FEE_clockbuf80MHz
-RECTANGLE Normal 32 32 576 1088
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk_in1
-PINATTR Polarity IN
-LINE Normal 608 80 576 80
-PIN 608 80 RIGHT 36
-PINATTR PinName clk_out1
-PINATTR Polarity OUT
-LINE Normal 608 176 576 176
-PIN 608 176 RIGHT 36
-PINATTR PinName clk_out2
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.gise b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.gise
deleted file mode 100644
index 913f68e..0000000
--- a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.gise
+++ /dev/null
@@ -1,52 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FEE_clockbuf80MHz.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="FEE_clockbuf80MHz.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="FEE_clockbuf80MHz.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1411996303" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1411996303">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2931233228134520341" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3005896570206739925" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9209316580054018149" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.ucf b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.ucf
deleted file mode 100644
index 9b5a1f0..0000000
--- a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.ucf
+++ /dev/null
@@ -1,58 +0,0 @@
-# file: FEE_clockbuf80MHz.ucf
-# 
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-
-# Input clock periods. These duplicate the values entered for the
-#  input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 12.500 ns HIGH 50% INPUT_JITTER 125.0ps;
-
-
-# FALSE PATH constraints 
-
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vho b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vho
deleted file mode 100644
index 2174648..0000000
--- a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vho
+++ /dev/null
@@ -1,89 +0,0 @@
--- 
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- None
---
-------------------------------------------------------------------------------
--- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
--- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
-------------------------------------------------------------------------------
--- CLK_OUT1____80.000______0.000______50.0______147.966____103.963
--- CLK_OUT2____80.000____180.000______50.0______147.966____103.963
---
-------------------------------------------------------------------------------
--- "Input Clock   Freq (MHz)    Input Jitter (UI)"
-------------------------------------------------------------------------------
--- __primary______________80____________0.010
-
-
--- The following code must appear in the VHDL architecture header:
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component FEE_clockbuf80MHz
-port
- (-- Clock in ports
-  CLK_IN1           : in     std_logic;
-  -- Clock out ports
-  CLK_OUT1          : out    std_logic;
-  CLK_OUT2          : out    std_logic
- );
-end component;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : FEE_clockbuf80MHz
-  port map
-   (-- Clock in ports
-    CLK_IN1 => CLK_IN1,
-    -- Clock out ports
-    CLK_OUT1 => CLK_OUT1,
-    CLK_OUT2 => CLK_OUT2);
--- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xco b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xco
deleted file mode 100644
index d5db7fd..0000000
--- a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xco
+++ /dev/null
@@ -1,269 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Thu Sep 25 14:23:17 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:clk_wiz:3.6
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
-# END Select
-# BEGIN Parameters
-CSET calc_done=DONE
-CSET clk_in_sel_port=CLK_IN_SEL
-CSET clk_out1_port=CLK_OUT1
-CSET clk_out1_use_fine_ps_gui=false
-CSET clk_out2_port=CLK_OUT2
-CSET clk_out2_use_fine_ps_gui=false
-CSET clk_out3_port=CLK_OUT3
-CSET clk_out3_use_fine_ps_gui=false
-CSET clk_out4_port=CLK_OUT4
-CSET clk_out4_use_fine_ps_gui=false
-CSET clk_out5_port=CLK_OUT5
-CSET clk_out5_use_fine_ps_gui=false
-CSET clk_out6_port=CLK_OUT6
-CSET clk_out6_use_fine_ps_gui=false
-CSET clk_out7_port=CLK_OUT7
-CSET clk_out7_use_fine_ps_gui=false
-CSET clk_valid_port=CLK_VALID
-CSET clkfb_in_n_port=CLKFB_IN_N
-CSET clkfb_in_p_port=CLKFB_IN_P
-CSET clkfb_in_port=CLKFB_IN
-CSET clkfb_in_signaling=SINGLE
-CSET clkfb_out_n_port=CLKFB_OUT_N
-CSET clkfb_out_p_port=CLKFB_OUT_P
-CSET clkfb_out_port=CLKFB_OUT
-CSET clkfb_stopped_port=CLKFB_STOPPED
-CSET clkin1_jitter_ps=125.0
-CSET clkin1_ui_jitter=0.010
-CSET clkin2_jitter_ps=100.0
-CSET clkin2_ui_jitter=0.010
-CSET clkout1_drives=BUFG
-CSET clkout1_requested_duty_cycle=50.000
-CSET clkout1_requested_out_freq=80
-CSET clkout1_requested_phase=0.000
-CSET clkout2_drives=BUFG
-CSET clkout2_requested_duty_cycle=50.000
-CSET clkout2_requested_out_freq=80
-CSET clkout2_requested_phase=180
-CSET clkout2_used=true
-CSET clkout3_drives=BUFG
-CSET clkout3_requested_duty_cycle=50.000
-CSET clkout3_requested_out_freq=80
-CSET clkout3_requested_phase=0.000
-CSET clkout3_used=false
-CSET clkout4_drives=BUFG
-CSET clkout4_requested_duty_cycle=50.000
-CSET clkout4_requested_out_freq=80
-CSET clkout4_requested_phase=0.000
-CSET clkout4_used=false
-CSET clkout5_drives=BUFG
-CSET clkout5_requested_duty_cycle=50.000
-CSET clkout5_requested_out_freq=80
-CSET clkout5_requested_phase=0.000
-CSET clkout5_used=false
-CSET clkout6_drives=BUFG
-CSET clkout6_requested_duty_cycle=50.000
-CSET clkout6_requested_out_freq=80
-CSET clkout6_requested_phase=0.000
-CSET clkout6_used=false
-CSET clkout7_drives=BUFG
-CSET clkout7_requested_duty_cycle=50.000
-CSET clkout7_requested_out_freq=80
-CSET clkout7_requested_phase=0.000
-CSET clkout7_used=false
-CSET clock_mgr_type=MANUAL
-CSET component_name=FEE_clockbuf80MHz
-CSET daddr_port=DADDR
-CSET dclk_port=DCLK
-CSET dcm_clk_feedback=1X
-CSET dcm_clk_out1_port=CLK0
-CSET dcm_clk_out2_port=CLK0
-CSET dcm_clk_out3_port=CLK0
-CSET dcm_clk_out4_port=CLK0
-CSET dcm_clk_out5_port=CLK0
-CSET dcm_clk_out6_port=CLK0
-CSET dcm_clkdv_divide=2.0
-CSET dcm_clkfx_divide=1
-CSET dcm_clkfx_multiply=4
-CSET dcm_clkgen_clk_out1_port=CLKFX
-CSET dcm_clkgen_clk_out2_port=CLKFX
-CSET dcm_clkgen_clk_out3_port=CLKFX
-CSET dcm_clkgen_clkfx_divide=1
-CSET dcm_clkgen_clkfx_md_max=0.000
-CSET dcm_clkgen_clkfx_multiply=4
-CSET dcm_clkgen_clkfxdv_divide=2
-CSET dcm_clkgen_clkin_period=10.000
-CSET dcm_clkgen_notes=None
-CSET dcm_clkgen_spread_spectrum=NONE
-CSET dcm_clkgen_startup_wait=false
-CSET dcm_clkin_divide_by_2=false
-CSET dcm_clkin_period=10.000
-CSET dcm_clkout_phase_shift=NONE
-CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
-CSET dcm_notes=None
-CSET dcm_phase_shift=0
-CSET dcm_pll_cascade=NONE
-CSET dcm_startup_wait=false
-CSET den_port=DEN
-CSET din_port=DIN
-CSET dout_port=DOUT
-CSET drdy_port=DRDY
-CSET dwe_port=DWE
-CSET feedback_source=FDBK_AUTO
-CSET in_freq_units=Units_MHz
-CSET in_jitter_units=Units_UI
-CSET input_clk_stopped_port=INPUT_CLK_STOPPED
-CSET jitter_options=UI
-CSET jitter_sel=No_Jitter
-CSET locked_port=LOCKED
-CSET mmcm_bandwidth=OPTIMIZED
-CSET mmcm_clkfbout_mult_f=12.000
-CSET mmcm_clkfbout_phase=0.000
-CSET mmcm_clkfbout_use_fine_ps=false
-CSET mmcm_clkin1_period=12.500
-CSET mmcm_clkin2_period=10.000
-CSET mmcm_clkout0_divide_f=12.000
-CSET mmcm_clkout0_duty_cycle=0.500
-CSET mmcm_clkout0_phase=0.000
-CSET mmcm_clkout0_use_fine_ps=false
-CSET mmcm_clkout1_divide=12
-CSET mmcm_clkout1_duty_cycle=0.500
-CSET mmcm_clkout1_phase=180.000
-CSET mmcm_clkout1_use_fine_ps=false
-CSET mmcm_clkout2_divide=1
-CSET mmcm_clkout2_duty_cycle=0.500
-CSET mmcm_clkout2_phase=0.000
-CSET mmcm_clkout2_use_fine_ps=false
-CSET mmcm_clkout3_divide=1
-CSET mmcm_clkout3_duty_cycle=0.500
-CSET mmcm_clkout3_phase=0.000
-CSET mmcm_clkout3_use_fine_ps=false
-CSET mmcm_clkout4_cascade=false
-CSET mmcm_clkout4_divide=1
-CSET mmcm_clkout4_duty_cycle=0.500
-CSET mmcm_clkout4_phase=0.000
-CSET mmcm_clkout4_use_fine_ps=false
-CSET mmcm_clkout5_divide=1
-CSET mmcm_clkout5_duty_cycle=0.500
-CSET mmcm_clkout5_phase=0.000
-CSET mmcm_clkout5_use_fine_ps=false
-CSET mmcm_clkout6_divide=1
-CSET mmcm_clkout6_duty_cycle=0.500
-CSET mmcm_clkout6_phase=0.000
-CSET mmcm_clkout6_use_fine_ps=false
-CSET mmcm_clock_hold=false
-CSET mmcm_compensation=ZHOLD
-CSET mmcm_divclk_divide=1
-CSET mmcm_notes=None
-CSET mmcm_ref_jitter1=0.010
-CSET mmcm_ref_jitter2=0.010
-CSET mmcm_startup_wait=false
-CSET num_out_clks=2
-CSET override_dcm=false
-CSET override_dcm_clkgen=false
-CSET override_mmcm=false
-CSET override_pll=false
-CSET platform=nt64
-CSET pll_bandwidth=OPTIMIZED
-CSET pll_clk_feedback=CLKFBOUT
-CSET pll_clkfbout_mult=4
-CSET pll_clkfbout_phase=0.000
-CSET pll_clkin_period=10.000
-CSET pll_clkout0_divide=1
-CSET pll_clkout0_duty_cycle=0.500
-CSET pll_clkout0_phase=0.000
-CSET pll_clkout1_divide=1
-CSET pll_clkout1_duty_cycle=0.500
-CSET pll_clkout1_phase=0.000
-CSET pll_clkout2_divide=1
-CSET pll_clkout2_duty_cycle=0.500
-CSET pll_clkout2_phase=0.000
-CSET pll_clkout3_divide=1
-CSET pll_clkout3_duty_cycle=0.500
-CSET pll_clkout3_phase=0.000
-CSET pll_clkout4_divide=1
-CSET pll_clkout4_duty_cycle=0.500
-CSET pll_clkout4_phase=0.000
-CSET pll_clkout5_divide=1
-CSET pll_clkout5_duty_cycle=0.500
-CSET pll_clkout5_phase=0.000
-CSET pll_compensation=SYSTEM_SYNCHRONOUS
-CSET pll_divclk_divide=1
-CSET pll_notes=None
-CSET pll_ref_jitter=0.010
-CSET power_down_port=POWER_DOWN
-CSET prim_in_freq=80
-CSET prim_in_jitter=0.010
-CSET prim_source=No_buffer
-CSET primary_port=CLK_IN1
-CSET primitive=MMCM
-CSET primtype_sel=MMCM_ADV
-CSET psclk_port=PSCLK
-CSET psdone_port=PSDONE
-CSET psen_port=PSEN
-CSET psincdec_port=PSINCDEC
-CSET relative_inclk=REL_PRIMARY
-CSET reset_port=RESET
-CSET secondary_in_freq=100.000
-CSET secondary_in_jitter=0.010
-CSET secondary_port=CLK_IN2
-CSET secondary_source=Single_ended_clock_capable_pin
-CSET ss_mod_freq=250
-CSET ss_mode=CENTER_HIGH
-CSET status_port=STATUS
-CSET summary_strings=empty
-CSET use_clk_valid=false
-CSET use_clkfb_stopped=false
-CSET use_dyn_phase_shift=false
-CSET use_dyn_reconfig=false
-CSET use_freeze=false
-CSET use_freq_synth=false
-CSET use_inclk_stopped=false
-CSET use_inclk_switchover=false
-CSET use_locked=false
-CSET use_max_i_jitter=false
-CSET use_min_o_jitter=false
-CSET use_min_power=false
-CSET use_phase_alignment=true
-CSET use_power_down=false
-CSET use_reset=false
-CSET use_spread_spectrum=false
-CSET use_spread_spectrum_1=false
-CSET use_status=false
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-05-10T12:44:55Z
-# END Extra information
-GENERATE
-# CRC: f339ac6c
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xise b/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xise
deleted file mode 100644
index ff919f7..0000000
--- a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.xise
+++ /dev/null
@@ -1,75 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="FEE_clockbuf80MHz.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="FEE_clockbuf80MHz.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|FEE_clockbuf80MHz|xilinx" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="FEE_clockbuf80MHz.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/FEE_clockbuf80MHz" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="FEE_clockbuf80MHz" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-25T16:23:42" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A92535ED933448509FBB6E5ADC9D6C4B" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings>
-    <binding xil_pn:location="/FEE_clockbuf80MHz" xil_pn:name="FEE_clockbuf80MHz.ucf"/>
-  </bindings>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.asy b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.asy
deleted file mode 100644
index 4d8a6f6..0000000
--- a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.asy
+++ /dev/null
@@ -1,89 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 SystemMonitorVirtex
-RECTANGLE Normal 32 32 640 1504
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName di_in[15:0]
-PINATTR Polarity IN
-LINE Wide 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName daddr_in[6:0]
-PINATTR Polarity IN
-LINE Normal 0 144 32 144
-PIN 0 144 LEFT 36
-PINATTR PinName den_in
-PINATTR Polarity IN
-LINE Normal 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName dwe_in
-PINATTR Polarity IN
-LINE Normal 0 208 32 208
-PIN 0 208 LEFT 36
-PINATTR PinName dclk_in
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName reset_in
-PINATTR Polarity IN
-LINE Normal 0 400 32 400
-PIN 0 400 LEFT 36
-PINATTR PinName vp_in
-PINATTR Polarity IN
-LINE Normal 0 432 32 432
-PIN 0 432 LEFT 36
-PINATTR PinName vn_in
-PINATTR Polarity IN
-LINE Wide 672 80 640 80
-PIN 672 80 RIGHT 36
-PINATTR PinName do_out[15:0]
-PINATTR Polarity OUT
-LINE Normal 672 112 640 112
-PIN 672 112 RIGHT 36
-PINATTR PinName drdy_out
-PINATTR Polarity OUT
-LINE Normal 672 176 640 176
-PIN 672 176 RIGHT 36
-PINATTR PinName user_temp_alarm_out
-PINATTR Polarity OUT
-LINE Normal 672 208 640 208
-PIN 672 208 RIGHT 36
-PINATTR PinName vccint_alarm_out
-PINATTR Polarity OUT
-LINE Normal 672 240 640 240
-PIN 672 240 RIGHT 36
-PINATTR PinName vccaux_alarm_out
-PINATTR Polarity OUT
-LINE Normal 672 272 640 272
-PIN 672 272 RIGHT 36
-PINATTR PinName ot_out
-PINATTR Polarity OUT
-LINE Wide 672 336 640 336
-PIN 672 336 RIGHT 36
-PINATTR PinName channel_out[4:0]
-PINATTR Polarity OUT
-LINE Normal 672 368 640 368
-PIN 672 368 RIGHT 36
-PINATTR PinName eoc_out
-PINATTR Polarity OUT
-LINE Normal 672 400 640 400
-PIN 672 400 RIGHT 36
-PINATTR PinName eos_out
-PINATTR Polarity OUT
-LINE Normal 672 432 640 432
-PIN 672 432 RIGHT 36
-PINATTR PinName busy_out
-PINATTR Polarity OUT
-LINE Normal 672 464 640 464
-PIN 672 464 RIGHT 36
-PINATTR PinName jtaglocked_out
-PINATTR Polarity OUT
-LINE Normal 672 496 640 496
-PIN 672 496 RIGHT 36
-PINATTR PinName jtagmodified_out
-PINATTR Polarity OUT
-LINE Normal 672 528 640 528
-PIN 672 528 RIGHT 36
-PINATTR PinName jtagbusy_out
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.gise b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.gise
deleted file mode 100644
index b6a2bee..0000000
--- a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.gise
+++ /dev/null
@@ -1,53 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="SystemMonitorVirtex.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="SystemMonitorVirtex.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="SystemMonitorVirtex.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="SystemMonitorVirtex.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1381060267" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1381060267">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3728760624764540981" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="851620736073740107" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3180520481145995643" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vhd b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vhd
deleted file mode 100644
index c196fb5..0000000
--- a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vhd
+++ /dev/null
@@ -1,192 +0,0 @@
--- file: SystemMonitorVirtex.vhd
--- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-Library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
-entity SystemMonitorVirtex is
-    port (
-          DADDR_IN            : in  STD_LOGIC_VECTOR (6 downto 0);     -- Address bus for the dynamic reconfiguration port
-          DCLK_IN             : in  STD_LOGIC;                         -- Clock input for the dynamic reconfiguration port
-          DEN_IN              : in  STD_LOGIC;                         -- Enable Signal for the dynamic reconfiguration port
-          DI_IN               : in  STD_LOGIC_VECTOR (15 downto 0);    -- Input data bus for the dynamic reconfiguration port
-          DWE_IN              : in  STD_LOGIC;                         -- Write Enable for the dynamic reconfiguration port
-          RESET_IN            : in  STD_LOGIC;                         -- Reset signal for the System Monitor control logic
-          BUSY_OUT            : out  STD_LOGIC;                        -- ADC Busy signal
-          CHANNEL_OUT         : out  STD_LOGIC_VECTOR (4 downto 0);    -- Channel Selection Outputs
-          DO_OUT              : out  STD_LOGIC_VECTOR (15 downto 0);   -- Output data bus for dynamic reconfiguration port
-          DRDY_OUT            : out  STD_LOGIC;                        -- Data ready signal for the dynamic reconfiguration port
-          EOC_OUT             : out  STD_LOGIC;                        -- End of Conversion Signal
-          EOS_OUT             : out  STD_LOGIC;                        -- End of Sequence Signal
-          JTAGBUSY_OUT        : out  STD_LOGIC;                        -- JTAG DRP transaction is in progress signal
-          JTAGLOCKED_OUT      : out  STD_LOGIC;                        -- DRP port lock request has been made by JTAG
-          JTAGMODIFIED_OUT    : out  STD_LOGIC;                        -- Indicates JTAG Write to the DRP has occurred
-          OT_OUT              : out  STD_LOGIC;                        -- Over-Temperature alarm output
-          VCCAUX_ALARM_OUT    : out  STD_LOGIC;                        -- VCCAUX-sensor alarm output
-          VCCINT_ALARM_OUT    : out  STD_LOGIC;                        -- VCCINT-sensor alarm output
-          USER_TEMP_ALARM_OUT : out  STD_LOGIC;                        -- Temperature-sensor alarm output
-          VP_IN               : in  STD_LOGIC;                         -- Dedicated Analog Input Pair
-          VN_IN               : in  STD_LOGIC
-);
-end SystemMonitorVirtex;
-
-architecture xilinx of SystemMonitorVirtex is
-
-  attribute X_CORE_INFO : string;
-  attribute X_CORE_INFO of xilinx : architecture is "sysmon_wiz_v2_1, Coregen 12.4";
-
-  signal aux_channel_p : std_logic_vector (15 downto 0);
-  signal aux_channel_n : std_logic_vector (15 downto 0);
-
-begin
-
-        aux_channel_p(0) <= '0';
-        aux_channel_n(0) <= '0';
-
-        aux_channel_p(1) <= '0';
-        aux_channel_n(1) <= '0';
-
-        aux_channel_p(2) <= '0';
-        aux_channel_n(2) <= '0';
-
-        aux_channel_p(3) <= '0';
-        aux_channel_n(3) <= '0';
-
-        aux_channel_p(4) <= '0';
-        aux_channel_n(4) <= '0';
-
-        aux_channel_p(5) <= '0';
-        aux_channel_n(5) <= '0';
-
-        aux_channel_p(6) <= '0';
-        aux_channel_n(6) <= '0';
-
-        aux_channel_p(7) <= '0';
-        aux_channel_n(7) <= '0';
-
-        aux_channel_p(8) <= '0';
-        aux_channel_n(8) <= '0';
-
-        aux_channel_p(9) <= '0';
-        aux_channel_n(9) <= '0';
-
-        aux_channel_p(10) <= '0';
-        aux_channel_n(10) <= '0';
-
-        aux_channel_p(11) <= '0';
-        aux_channel_n(11) <= '0';
-
-        aux_channel_p(12) <= '0';
-        aux_channel_n(12) <= '0';
-
-        aux_channel_p(13) <= '0';
-        aux_channel_n(13) <= '0';
-
-        aux_channel_p(14) <= '0';
-        aux_channel_n(14) <= '0';
-
-        aux_channel_p(15) <= '0';
-        aux_channel_n(15) <= '0';
-
-
- SYSMON_INST : SYSMON
-     generic map(
-        INIT_40 => X"0000", -- config reg 0
-        INIT_41 => X"3000", -- config reg 1
-        INIT_42 => X"1900", -- config reg 2
-        INIT_48 => X"0100", -- Sequencer channel selection
-        INIT_49 => X"0000", -- Sequencer channel selection
-        INIT_4A => X"0000", -- Sequencer Average selection
-        INIT_4B => X"0000", -- Sequencer Average selection
-        INIT_4C => X"0000", -- Sequencer Bipolar selection
-        INIT_4D => X"0000", -- Sequencer Bipolar selection
-        INIT_4E => X"0000", -- Sequencer Acq time selection
-        INIT_4F => X"0000", -- Sequencer Acq time selection
-        INIT_50 => X"b5ed", -- Temp alarm trigger
-        INIT_51 => X"5999", -- Vccint upper alarm limit
-        INIT_52 => X"e000", -- Vccaux upper alarm limit
-        INIT_53 => X"ca33",  -- Temp alarm OT upper
-        INIT_54 => X"a93a", -- Temp alarm reset
-        INIT_55 => X"5111", -- Vccint lower alarm limit
-        INIT_56 => X"caaa", -- Vccaux lower alarm limit
-        INIT_57 => X"ae4e",  -- Temp alarm OT reset
-        SIM_DEVICE => "VIRTEX6",
-        SIM_MONITOR_FILE => "design.txt"
-        )
-
-port map (
-        CONVST              => '0',
-        CONVSTCLK           => '0',
-        DADDR(6 downto 0)   => DADDR_IN(6 downto 0),
-        DCLK                => DCLK_IN,
-        DEN                 => DEN_IN,
-        DI(15 downto 0)     => DI_IN(15 downto 0),
-        DWE                 => DWE_IN,
-        RESET               => RESET_IN,
-        VAUXN(15 downto 0)  => aux_channel_n(15 downto 0),
-        VAUXP(15 downto 0)  => aux_channel_p(15 downto 0),
-        ALM(2)              => VCCAUX_ALARM_OUT,
-        ALM(1)              => VCCINT_ALARM_OUT,
-        ALM(0)              => USER_TEMP_ALARM_OUT,
-        BUSY                => BUSY_OUT,
-        CHANNEL(4 downto 0) => CHANNEL_OUT(4 downto 0),
-        DO(15 downto 0)     => DO_OUT(15 downto 0),
-        DRDY                => DRDY_OUT,
-        EOC                 => EOC_OUT,
-        EOS                 => EOS_OUT,
-        JTAGBUSY            => JTAGBUSY_OUT,
-        JTAGLOCKED          => JTAGLOCKED_OUT,
-        JTAGMODIFIED        => JTAGMODIFIED_OUT,
-        OT                  => OT_OUT,
-        VN                  => VN_IN,
-        VP                  => VP_IN
-         );
-end xilinx;
-
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vho b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vho
deleted file mode 100644
index 320cf0c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.vho
+++ /dev/null
@@ -1,112 +0,0 @@
--- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
---
-
--- The following code must appear in the VHDL architecture header:
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component SystemMonitorVirtex
-    port (
-          DADDR_IN            : in  STD_LOGIC_VECTOR (6 downto 0);     -- Address bus for the dynamic reconfiguration port
-          DCLK_IN             : in  STD_LOGIC;                         -- Clock input for the dynamic reconfiguration port
-          DEN_IN              : in  STD_LOGIC;                         -- Enable Signal for the dynamic reconfiguration port
-          DI_IN               : in  STD_LOGIC_VECTOR (15 downto 0);    -- Input data bus for the dynamic reconfiguration port
-          DWE_IN              : in  STD_LOGIC;                         -- Write Enable for the dynamic reconfiguration port
-          RESET_IN            : in  STD_LOGIC;                         -- Reset signal for the System Monitor control logic
-          BUSY_OUT            : out  STD_LOGIC;                        -- ADC Busy signal
-          CHANNEL_OUT         : out  STD_LOGIC_VECTOR (4 downto 0);    -- Channel Selection Outputs
-          DO_OUT              : out  STD_LOGIC_VECTOR (15 downto 0);   -- Output data bus for dynamic reconfiguration port
-          DRDY_OUT            : out  STD_LOGIC;                        -- Data ready signal for the dynamic reconfiguration port
-          EOC_OUT             : out  STD_LOGIC;                        -- End of Conversion Signal
-          EOS_OUT             : out  STD_LOGIC;                        -- End of Sequence Signal
-          JTAGBUSY_OUT        : out  STD_LOGIC;                        -- JTAG DRP transaction is in progress signal
-          JTAGLOCKED_OUT      : out  STD_LOGIC;                        -- DRP port lock request has been made by JTAG
-          JTAGMODIFIED_OUT    : out  STD_LOGIC;                        -- Indicates JTAG Write to the DRP has occurred
-          OT_OUT              : out  STD_LOGIC;                        -- Over-Temperature alarm output
-          VCCAUX_ALARM_OUT    : out  STD_LOGIC;                        -- VCCAUX-sensor alarm output
-          VCCINT_ALARM_OUT    : out  STD_LOGIC;                        -- VCCINT-sensor alarm output
-          USER_TEMP_ALARM_OUT : out  STD_LOGIC;                        -- Temperature-sensor alarm output
-          VP_IN               : in  STD_LOGIC;                         -- Dedicated Analog Input Pair
-          VN_IN               : in  STD_LOGIC
-);
-end component;
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : SystemMonitorVirtex
-  port map ( 
-          DADDR_IN            => DADDR_IN, 
-          DCLK_IN             => DCLK_IN, 
-          DEN_IN              => DEN_IN, 
-          DI_IN               => DI_IN,
-          DWE_IN              => DWE_IN, 
-          RESET_IN            => RESET_IN, 
-          BUSY_OUT            => BUSY_OUT,
-          CHANNEL_OUT         => CHANNEL_OUT,
-          DO_OUT              => DO_OUT,
-          DRDY_OUT            => DRDY_OUT,
-          EOC_OUT             => EOC_OUT,
-          EOS_OUT             => EOS_OUT,
-          JTAGBUSY_OUT        => JTAGBUSY_OUT,
-          JTAGLOCKED_OUT      => JTAGLOCKED_OUT,
-          JTAGMODIFIED_OUT    => JTAGMODIFIED_OUT,
-          OT_OUT              => OT_OUT,
-          VCCAUX_ALARM_OUT    => VCCAUX_ALARM_OUT,
-          VCCINT_ALARM_OUT    => VCCINT_ALARM_OUT,
-          USER_TEMP_ALARM_OUT => USER_TEMP_ALARM_OUT,
-          VP_IN               => VP_IN, 
-          VN_IN               => VN_IN
-         );
-
--- INST_TAG_END ------ End INSTANTIATION Template ---------
-
-
-
-
-
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xco b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xco
deleted file mode 100644
index d8fdbe6..0000000
--- a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xco
+++ /dev/null
@@ -1,163 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.3
-# Date: Wed Oct 17 13:30:12 2012
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:sysmon_wiz:2.1
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT System_Monitor_Wizard family Xilinx,_Inc. 2.1
-# END Select
-# BEGIN Parameters
-CSET acquisition_time_vauxp0_vauxn0=false
-CSET acquisition_time_vauxp10_vauxn10=false
-CSET acquisition_time_vauxp11_vauxn11=false
-CSET acquisition_time_vauxp12_vauxn12=false
-CSET acquisition_time_vauxp13_vauxn13=false
-CSET acquisition_time_vauxp14_vauxn14=false
-CSET acquisition_time_vauxp15_vauxn15=false
-CSET acquisition_time_vauxp1_vauxn1=false
-CSET acquisition_time_vauxp2_vauxn2=false
-CSET acquisition_time_vauxp3_vauxn3=false
-CSET acquisition_time_vauxp4_vauxn4=false
-CSET acquisition_time_vauxp5_vauxn5=false
-CSET acquisition_time_vauxp6_vauxn6=false
-CSET acquisition_time_vauxp7_vauxn7=false
-CSET acquisition_time_vauxp8_vauxn8=false
-CSET acquisition_time_vauxp9_vauxn9=false
-CSET acquisition_time_vp_vn=false
-CSET adc_conversion_rate=100.0
-CSET adc_offset_and_gain_calibration=false
-CSET adc_offset_calibration=false
-CSET average_enable_temperature=false
-CSET average_enable_vauxp0_vauxn0=false
-CSET average_enable_vauxp10_vauxn10=false
-CSET average_enable_vauxp11_vauxn11=false
-CSET average_enable_vauxp12_vauxn12=false
-CSET average_enable_vauxp13_vauxn13=false
-CSET average_enable_vauxp14_vauxn14=false
-CSET average_enable_vauxp15_vauxn15=false
-CSET average_enable_vauxp1_vauxn1=false
-CSET average_enable_vauxp2_vauxn2=false
-CSET average_enable_vauxp3_vauxn3=false
-CSET average_enable_vauxp4_vauxn4=false
-CSET average_enable_vauxp5_vauxn5=false
-CSET average_enable_vauxp6_vauxn6=false
-CSET average_enable_vauxp7_vauxn7=false
-CSET average_enable_vauxp8_vauxn8=false
-CSET average_enable_vauxp9_vauxn9=false
-CSET average_enable_vccaux=false
-CSET average_enable_vccint=false
-CSET average_enable_vp_vn=false
-CSET bipolar_operation=false
-CSET bipolar_vauxp0_vauxn0=false
-CSET bipolar_vauxp10_vauxn10=false
-CSET bipolar_vauxp11_vauxn11=false
-CSET bipolar_vauxp12_vauxn12=false
-CSET bipolar_vauxp13_vauxn13=false
-CSET bipolar_vauxp14_vauxn14=false
-CSET bipolar_vauxp15_vauxn15=false
-CSET bipolar_vauxp1_vauxn1=false
-CSET bipolar_vauxp2_vauxn2=false
-CSET bipolar_vauxp3_vauxn3=false
-CSET bipolar_vauxp4_vauxn4=false
-CSET bipolar_vauxp5_vauxn5=false
-CSET bipolar_vauxp6_vauxn6=false
-CSET bipolar_vauxp7_vauxn7=false
-CSET bipolar_vauxp8_vauxn8=false
-CSET bipolar_vauxp9_vauxn9=false
-CSET bipolar_vp_vn=false
-CSET channel_averaging=None
-CSET channel_enable_calibration=false
-CSET channel_enable_temperature=false
-CSET channel_enable_vauxp0_vauxn0=false
-CSET channel_enable_vauxp10_vauxn10=false
-CSET channel_enable_vauxp11_vauxn11=false
-CSET channel_enable_vauxp12_vauxn12=false
-CSET channel_enable_vauxp13_vauxn13=false
-CSET channel_enable_vauxp14_vauxn14=false
-CSET channel_enable_vauxp15_vauxn15=false
-CSET channel_enable_vauxp1_vauxn1=false
-CSET channel_enable_vauxp2_vauxn2=false
-CSET channel_enable_vauxp3_vauxn3=false
-CSET channel_enable_vauxp4_vauxn4=false
-CSET channel_enable_vauxp5_vauxn5=false
-CSET channel_enable_vauxp6_vauxn6=false
-CSET channel_enable_vauxp7_vauxn7=false
-CSET channel_enable_vauxp8_vauxn8=false
-CSET channel_enable_vauxp9_vauxn9=false
-CSET channel_enable_vccaux=false
-CSET channel_enable_vccint=false
-CSET channel_enable_vp_vn=false
-CSET channel_enable_vrefn=false
-CSET channel_enable_vrefp=false
-CSET component_name=SystemMonitorVirtex
-CSET dclk_frequency=62.5
-CSET enable_busy=true
-CSET enable_calibration_averaging=true
-CSET enable_channel=true
-CSET enable_convst=false
-CSET enable_convstclk=false
-CSET enable_dclk=true
-CSET enable_drp=true
-CSET enable_eoc=true
-CSET enable_eos=true
-CSET enable_jtagbusy=true
-CSET enable_jtaglocked=true
-CSET enable_jtagmodified=true
-CSET enable_reset=true
-CSET increase_acquisition_time=false
-CSET ot_alarm=true
-CSET sensor_offset_and_gain_calibration=false
-CSET sensor_offset_calibration=false
-CSET sequencer_mode=Off
-CSET sim_file_name=design
-CSET single_channel_acquisition_time=false
-CSET single_channel_enable_calibration=true
-CSET single_channel_selection=Temperature
-CSET startup_channel_selection=single_channel
-CSET temperature_alarm_ot_reset=70.0
-CSET temperature_alarm_ot_trigger=125.0
-CSET temperature_alarm_reset=60.0
-CSET temperature_alarm_trigger=85.0
-CSET timing_mode=Continuous
-CSET user_temp_alarm=true
-CSET vccaux_alarm=true
-CSET vccaux_alarm_lower=2.375
-CSET vccaux_alarm_upper=2.625
-CSET vccint_alarm=true
-CSET vccint_alarm_lower=0.95
-CSET vccint_alarm_upper=1.05
-# END Parameters
-GENERATE
-# CRC: f7c86d59
diff --git a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xise b/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xise
deleted file mode 100644
index e2f9a9c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/SystemMonitorVirtex.xise
+++ /dev/null
@@ -1,68 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="SystemMonitorVirtex.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SystemMonitorVirtex|xilinx" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="SystemMonitorVirtex.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SystemMonitorVirtex" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="SystemMonitorVirtex" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-10-17T15:30:23" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="57CB37DF213B424C978A20B38A2AF937" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/_xmsgs/pn_parser.xmsgs b/FEE_ADC32board/project/ipcore_dir/_xmsgs/pn_parser.xmsgs
deleted file mode 100644
index bcb73a2..0000000
--- a/FEE_ADC32board/project/ipcore_dir/_xmsgs/pn_parser.xmsgs
+++ /dev/null
@@ -1,15 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<!-- IMPORTANT: This is an internal file that has been generated   -->
-<!--     by the Xilinx ISE software.  Any direct editing or        -->
-<!--     changes made to this file may result in unpredictable     -->
-<!--     behavior or data corruption.  It is strongly advised that -->
-<!--     users do not edit the contents of this file.              -->
-<!--                                                               -->
-<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
-
-<messages>
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/Project/Panda/GIT/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vhd&quot; into library work</arg>
-</msg>
-
-</messages>
-
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.asy b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.asy
deleted file mode 100644
index 203f9b9..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.asy
+++ /dev/null
@@ -1,41 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 async_fifo_16x9
-RECTANGLE Normal 32 32 800 4064
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Normal 0 208 32 208
-PIN 0 208 LEFT 36
-PINATTR PinName wr_clk
-PINATTR Polarity IN
-LINE Wide 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName din[8:0]
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 464 32 464
-PIN 0 464 LEFT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Normal 832 240 800 240
-PIN 832 240 RIGHT 36
-PINATTR PinName rd_clk
-PINATTR Polarity IN
-LINE Wide 832 272 800 272
-PIN 832 272 RIGHT 36
-PINATTR PinName dout[8:0]
-PINATTR Polarity OUT
-LINE Normal 832 304 800 304
-PIN 832 304 RIGHT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 832 496 800 496
-PIN 832 496 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.gise b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.gise
deleted file mode 100644
index 5e02c17..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.gise
+++ /dev/null
@@ -1,53 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="async_fifo_16x9.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="async_fifo_16x9.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="async_fifo_16x9.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="async_fifo_16x9.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8196757456903485200" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8922373193325759184" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6619080276402113216" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.ngc b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.ngc
deleted file mode 100644
index 9dda322..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$3a644<,[o}e~g`n;"2*73>(-80!<m4/+])[WGIOL*!=6>:;123452739:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456788:0<=>?0123=567893;=6?>a:37>LHW]]0JHI\NRECG@W:6;3:5=l5>4;KMTPR=IMNYNZ\NDEP?56<768>0=;4FNQWW>AOFL@6:97>115922?OIX\^1HDLKI=36>586=2;=6B[[PTV9@JGCG5;>6=0>5:35>JSSX\^1HBLKO=36>586;2;1EC^ZT;PFCFCF490;2<=41;KMTPR=ZLMHIO2?:1<25>7=AGZ^X7\\T@>3>58692;1EC^ZT;PPPG:7294:<6?5IORVP?QBI5:1<3??;08JJUSS2^OI0=4?>0910>460=;27?4FNQWW>DBCZH^BIEGHH=394;7>3;0BB][[:@FGVGRNMACLD1?50?37?7<NFY__6IG_AEKS84<768>0>7GAPTV9@LVEL@Z7=7>11491>JSSX\^1HB^NDNR?5?699<196B[[PTV9@JVELFZ7=7>12:6257=32@D[YY4NDEPB86<7688087GAPTV9EABUJ591<3??;58JJUSS2^OJ0>4?>0580?IR\Y__6_JNDEPFGF:4294:<6;:4062043289:;<=?46595=<053?K?7;ONAg95ri~6;9~mj96;-2:8<56?:9:9=?57:HLSQQ<PMK]N0:4?>09:55=>893;<=>?012:45?530<:=675IORVP?BNFH636=0>1:;9MKVR\3NBBO27:1<24>?=AGZ^X7jfn=:94;74300DYY^ZT;FLQQG;03:5=>56:NWWTPR=LF__N1650?31?<<H]]Z^X7j`uu>;>5853H<?7LO9A99B@ATF49437LJKR@>2:==FLMXJ0?0n;@FGVD:429437LJKR@>0:`=FLMXJ^IOKDS>3:c=FLMXJ^IOKDS>24;`<IMNYM_JNDEP?548a3HNO^L\KAEFQ8449981JHI\NRECG@W:6;3:5j6OKDSCQ@DBCZ5;82h5NDEPBVAGCL[6:2h5NDEPBVAGCL[692h5NDEPBVAGCL[682h5NDEPBVAGCL[6?2h5NDEPBVAGCL[6>2h5NDEPBVAGCL[6=2h5NDEPBVAGCL[6<2h5NDEPBVAGCL[632h5NDEPBVAGCL[622k5NDEPBPLCOANB7<3?>;@FGVDRNMACLD1?50?d8EABUI]CNDDIG<0<;?DBCZK6;255NDEPA848?3HNO^O2=>`9B@ATE4:0;255NDEPA868a3HNO^OZFEIKDL969981JHI\MTHGKMBN;93:5j6OKDS@WM@NNOA6:2h5NDEPASWGCL[6;2k5NDEPASWGCL[6:<3h4AEFQFRTFLMX7=<0i;@FGVGQUIMNY0<<1109B@ATE_[KOH_2>3;2=b>GCL[H\^LJKR=30:`=FLMXI[_OKDS>2:`=FLMXI[_OKDS>1:`=FLMXI[_OKDS>0:`=FLMXI[_OKDS>7:`=FLMXI[_OKDS>6:`=FLMXI[_OKDS>5:`=FLMXI[_OKDS>4:`=FLMXI[_OKDS>;:`=FLMXI[_OKDS>::6=FDE30M^WAC^PFC40<JDGTECH@_@FGV@UTW[KEKH64BTQ\MK@H92I97NK>2:AKAFMXD@INB^KPTXRF0>EKC9<0OAE>8148GIM5?9?0OAE=X99@HN4_91:>7NBD9168GIMF=2IGGL?8;BNHE4B5?2IGGL?K469@HNG6L130OAENREAOO1=DDBH>7NBDB0;8GIME_[IGG85LLJA21>EKCM;>7NBDDWa8GIMC^VNBZDJJ5:AOOC^?3JF@JU?7029@HW?<KFGFEYZJD068GJTBWNOEI_O[INL\MK@H?2IYILZJD09G3>BEA]OY^i5KEMCZAAYPZ@^N46JFAEK?4;?<L@KOE1??>89GMDBN48;556JFAEK?578>3MCJHD2>3?;8@LGCA5;?2o5KI@FJ843=8730HDOKI=36:==CAHNB0<07;EKB@L:5611OELJF<2<;?AOFL@6?255KI@FJ808?3MCJHD29>99GMDBN4>437IGNDH>;:==CAHNB0407;EKA@L:7601OEOJF<02==>BNJMC7=<06;EKA@L:6:730HDLKI=30:<=CAKNB0<:1b:FJFAO;9<0;245KICFJ843902NBNIG31?:8@LDCA58546JFBEK?7;><L@HOE1:18:FJFAO;=720HDLKI=4=<>BNJMC7;364DH@GM9>902NBNIG39?58@LHF494<7IGAA=3=3>BNFH692:5KIOC?7;1<L@DJ0908;EKME939?2NBBL29>69GMKG;?730HD@N<983:2=CAGK74394DHLA85803MCEN1?17:FJJG:56>1OECL33?58@LHE4=4<7IGAB=7=3>BNFK6=2:5KIO@?3;?<L@DI054?>69GMKD;07k0HD^NDHR?4;e<L@ZJHD^31;2=e>BNXHNB\1?1a:FJTGBNX5:5o6JFPCFJT97=87k0HD^MDHR?5;><LFKOC1>19:FLEAI;99427IANDN>25;?<LFKOC1?=>89GKDBH489556J@AEM?518e3MEJHB2>5;2==>BHIME7=807;EMB@J:6611OCLJ@<3<;?AIFLF68255KO@FL818?3MEJHB2:>99GKDBH4?437IANDN>4:==CGHND0507;EMB@J:>6>1OCLQ]EF:8@JDCG5:556J@BEM?558>3MEIHB2>1?;8@JDCG5;9245KOCFL845912NDNIA315<a?AIELF6:97>19:FLFAI;9<437IAMDN>2:==CGKND0?07;EMA@J:4611OCOJ@<5<;?AIELF6>255KOCFL838?3MEIHB28>99GKGBH41437IAMDN>::2=CGKUYIJo4DNRB@JV;87i0HB^NDNR?5?69i2ND\LJ@P=3=e>BHXKND\1>1c:FLTGBHX5;1<3o4DNRA@JV;9720HB[[A=2=<>BH]]K7=364DNWWE94902NDYYO33?:8@JSSI5>546J@UUC?1;><LF__M1818:FLQQG;?7k0HB[[A=:94;><LF__M1618:FLQQD;8720HB[[B=3=<>BH]]H7>364DNWWF95902NDYYL34?:8@JSSJ5?546J@UU@?2;><LF__N191a:FLQQD;03:546J@UU@?<;5<MGK<7H@NREGM7>CIJ>1NBOY]EO:8B30119:;96HNLRG1?CB43ONH86HKCD18BAV33ON[I<5H3:EM@4=N:2C;>6G>2:K16>O4:2C?>6G:8:KMMQVX8920ECG[P^22<>OIA]ZT<?64IOKWTZ6402CEEY^P05:8MKOSXV:>46GAIUR\43><AGC_\R>89:KMMQUSI]O<7D@FT^233>OIA]U;=:5FNHV\471<AGC_S==8;HLJPZ63?2CEEYQ?569JJLRX8?=0ECG[_154?LHN\V:3;6GAIU]3=2=NF@^T<L94IOKW[5D03@DBXR>L7:KMMQY7L>1BBDZP0D58MKOSW9L<7D@FT^333>OIA]U:=:5FNHV\571<AGC_S<=8;HLJPZ73?2CEEYQ>569JJLRX9?=0ECG[_054?LHN\V;3;6GAIU]2=2=NF@^T=L94IOKW[4D03@DBXR?L7:KMMQY6L>1BBDZP1D58MKOSW8L<7D@FT^033>OIA]U9=:5FNHV\671<AGC_S?=8;HLJPZ43?2CEEYQ=569JJLRX:?=0ECG[_354?LHN\V83;6GAIU]1=2=NF@^T>L94IOKW[7D03@DBXR<L7:KMMQY5L>1BBDZP2D58MKOSW;L<7D@FT^133>OIA]U8=:5FNHV\771<AGC_S>=8;HLJPZ53?2CEEYQ<569JJLRX;?=0ECG[_254?LHN\V93;6GAIU]0=2=NF@^T?L94IOKW[6D03@DBXR=L7:KMMQY4L>1BBDZP3D58MKOSW:L=7D@FT^C5?LHN\VH27D@FT^DJH@b<AG@NOYJMIUGQVa=NFCOHX^LFTDPQ7>OI^?1GCLJJD79OKFMBL>1GCJGLAM68HPR5<2F^X>:4LTV70>JR\<>0@XZ95:OPCJHd3DkacXjrrkljf=JageyZh||inl1?K703GO_[B\D4:LLJ@7<G8=0C]ZFMHXF[UTNE@^BZH]PNFA`?U(5889:<<=PL59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ9:RH[MJR\GG87]\J6:RP@JHB92[37_OBB0:F5==UIDUFCIKl;SFB@ATBKJ6;2n5]D@FGV@ED484h7_JNDEPFGF:56l1YHLJKRDA@86<76j1YHLJKRDA@868612XOMIJ]_BMOHLUNGGUC[NAAFHE`?WCFLV]BHYFPAb9QADBX_@N_DRL:;SGDG@d<ZLMHIL2?:1<:?WC@KLK7<3l4RDE@ADTBOJO=7_KHCD@a?WC@KLH7<7>19:PFCFCE494o7_KHCMIBVATDDB=0^HILLJ@:?WUSI5:1<394RRVB858>3[Y_N1>50?58VVRE494o7_][R@OBVVRUID=0^^Z]AL@g?WUSZLMJ^^Z]EF58VVRUMNH:=6\\TSGD[UTNG[C_URO>1:PPPWC@WYXBC_G[Y^@;?VGQMMK_M:5\BHVFVW5<[MZ:=6]GRDE\A]RUIJ^TBJMj;RJQABYJAGUXEWK>3:QJIZEHDECXEB@PCIG@Od=TADUOI[GLE99POLVXX@D=7^AZRBG4?VTQIEUJ;6]]V@N\F3=T\H^^_95[RTG7?Q_WM?l0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/LzlvZTCWYD_^V>R_SF\TKRUS8WTTB\P13]l[}i;87;=j6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-N|jtXZMU[BY\T1\]Q@ZVI\[Q9QRV@R^32[jYg5:5=;h4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+H~hzVXOS]@[RZ0^[WBXXG^YW>SPXNP\55YhWqe7<3?9e:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})JpfxT[_Q_NUPX4XYPZVZEX_U>]^ZLVZ5XgVrd0=0>6d9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~(EqeySZ\PPOVQ_4[X_[U[BY\T2\][KWY5WfUsc1>117g8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'Drd~RY]_QLWV^4ZW^XT\CZ][2_\\JTX9VeTtb2?>040?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&XOS]@[RZ2^[WBXXG^YW<SPXNP\57Yh>:1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv RE]SJQT\9TUYHR^ATSY1YZ^HZV;:Sb8<;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*TCWYD_^V<R_SF\TKRUS:WTTB\P11]l27=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$[_Q_NUPX4XYPZVZEX_U>]^ZLVZ5Xg?80Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/VP\TKRUS8WT[_Q_NUPX6XY_G[U9Sb8=;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*QUWYD_^V<R_VP\TKRUS:WTTB\P1^m50>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%lt`l_rvbc`]6U'xoS~zh_hlpp*B;87<?7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.ep}keX{}kliV?R.sf\wqaXagy#I2>>768Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'nyrbnQ|t`ef_4[)zmUxxjQfnrv,@949>=1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv gr{mgZusinoP=P }d^qwcZoi{}%O0>097:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})`{pdhS~zngdY2Y+tcWz~lSd`|t.S\v`aX8?=0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/fqzjfYt|hmnW<S!re]ppbYnfz~$]R|jg^353>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%lt`l_rvbc`]6U'xoS~zh_hlpp*WXzlmT>;94U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+bu~fjUxxlij[0_-vaYt|nUbb~z Q^pfcZ51<2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!hsxl`[vrfolQ:Q#y}_rvd[lht|&N7<38;;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*atqgiTyoheZ3^*rtX{}mTec}{/E>2:32<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#j}vnb]ppdabS8W%{Q|tf]jjvr(L585:95Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,cvikVymjkT1\,tvZusoVcey!K<2<53>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%lt`l_rvbc`]6U'}yS~zh_hlpp*WXzlmT<;94U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+bu~fjUxxlij[0_-swYt|nUbb~z Q^pfcZ71?2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!hsxl`[vrfolQ:Q#y}_rvd[lht|&[T~hiP2758Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'nyrbnQ|t`ef_4[){UxxjQfnrv,UZtboV9=86[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-dw|hdWz~jkhU=]/pg[vr`W`dxx"J30?47?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&mxucmPsucda^4Z&{nTyiPioqw+A:66?>0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/fqzjfYt|hmnW?S!re]ppbYnfz~$H1<1659V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~(ozseoR}{afgX6X(ulVykRgasu-G868102_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!hsxl`[vrfolQ9Q#|k_rvd[lht|&[T~hi30?4;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&mxucmPsucda^4Z&{nTyiPioqw+TYumn6:2;64U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+bu~fjUxxlij[3_-vaYt|nUbb~z Q^pfc949>11^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv gr{mgZusinoP>P }d^qwcZoi{}%ZSkh<2<53>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%lt`l_rvbc`]5U'xoS~zh_hlpp*WXzlmT<;94U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+bu~fjUxxlij[3_-vaYt|nUbb~z Q^pfcZ71?2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!hsxl`[vrfolQ9Q#|k_rvd[lht|&[T~hiP2758Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'nyrbnQ|t`ef_7[)zmUxxjQfnrv,UZtboV9=86[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-dw|hdWz~jkhU=]/uq[vr`W`dxx"J30?47?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&mxucmPsucda^4Z&~xTyiPioqw+A:66?>0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/fqzjfYt|hmnW?S!ws]ppbYnfz~$H1<1659V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~(ozseoR}{afgX6X(pzVykRgasu-G868102_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!hsxl`[vrfolQ9Q#y}_rvd[lht|&[T~hi30?4;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&mxucmPsucda^4Z&~xTyiPioqw+TYumn6:2;64U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+bu~fjUxxlij[3_-swYt|nUbb~z Q^pfc949>11^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv gr{mgZusinoP>P xr^qwcZoi{}%ZSkh<2<53>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%lt`l_rvbc`]5U'}yS~zh_hlpp*WXzlmT<;94U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+bu~fjUxxlij[3_-swYt|nUbb~z Q^pfcZ71?2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!hsxl`[vrfolQ9Q#y}_rvd[lht|&[T~hiP2758Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'nyrbnQ|t`ef_7[){UxxjQfnrv,UZtboV9>?6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-q`Zvi|{Uiec2?>418Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'{nT|cz}_ckm8482;2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwYeag6928=4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+wbXxg~ySoga<2<66>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%yhR~ats]amkY7=;1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXj`dT=8<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+wbXxg~ySoga_371?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&xoS}`{r^`jjZ5292_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwY`kV:>=6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-q`Zvi|{UloR?:1:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})ulVzexQhc^065>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%yhR~ats]dgZ51l2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwY`kVkx~hiPl`qw_6[Xzln~ohQwos]25Zi1m2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwY`kVkx~hiPl`qw_6[Xzln~ohQwos]25Zi6>m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp^5ZW{ooynkPxnp\57Yh>l1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp^5ZW{ooynkPxnp\57Yh9>90Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/sf\tkruWniTm~|jg^nbwq]4UVxnhxmj_ymq[456Wqe7<3?9d:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})ulVzexQhc^cpv`aXdhyW>SPrdfvg`Yg{U:?Ra:3:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})pzVzexQmio>3:05<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#z|Ppovq[goi484>?6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{Uiec2=>418Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'~xT|cz}_ckm8682:2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!xr^rmpwYeagU;9?5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTnd`P1408Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'~xT|cz}_ckm[7353\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"y}_qlwvZdnfV9>=6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{UloR>:1:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})pzVzexQhc^365>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%|~R~ats]dgZ4292_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!xr^rmpwY`kV9=o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{UloRo|rde\hdusS:WT~hjzcd]{kwY1Wf<o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.uq[uhszVmhSl}}ef]oevr\;TUyii{le^zlvZ0Xg8<h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.uq[uhszVmhSl}}ef]oevr\;TUyii{le^zlvZ1Xg?n0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/vp\tkruWniTm~|jg^nbwq]4UVxnhxmj_ymq[2Yh9>80Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/vp\tkruWniTm~|jg^nbwq]4UVxnhxmj_ymq[=7Xpf6;2<8l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*quWyd~Ril_`qqabYkiz~P?PQ}eew`aZ~hzV2Tc8h4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvdu)zz~x#nabp1]`khv6WFXT:Ra90:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btf{'xxx~!lolr3[fijx8UD^R8Po043?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{kx"}{s.aliu6Xkfg{=RA]_7]l636<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~l}!rrvp+fijx9Uhc`~>_NP\2Zi4>91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}ar,qwqu(kfg{<Rm`mq3\KWY1Wf>>n6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fpbw+tt|z%ym`Qjmqvz[cdXa<20Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hr`q-vvrt'{kfShctx]j0c=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&xjaR|k_dl\m4303\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~iQnup\tist95:5Sd`y7e9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$Aljk_fa3*firf}Q8QRIAD^346ZiXimnT<RAZT^zlv96998UBB[Q?769V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$Aljk_fa3*firf}Q8QRIAD^346ZiXimnT<RAZT^zlv97998=<7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*KflmUlo= lotlw_6[XOGNT=:<Po^cg`Z6XG\^Ttb|32?3232=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| M`fg[be7&je~byU<]^EM@Z70:VeTmijP0^MVPZ~hz595=<;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?4;323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~7=3;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?6;323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~7?38l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uovX7XY@FMU:;?Q`_`fg[5YH]]6:2;m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznuY0YZAILV;<>RaPaef\4ZIR\585:n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{atZ1^[BHCW8=9SbQnde]3[JSS4:4>86[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{_177?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkrX9<>0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+be7&je~byQ=559V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmpZ5202_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-dg5(dg|dSi?31?7;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkrXl8692864U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu]g5959=>1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexRj>_074?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkrXl8U99:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{at^f2[60f3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kzo|.vqww*Kj}qUhc`~>_FLG[4>7WfUFYUQ7_n35f>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}j#y|tr-Nip~Xkfg{=RIAD^3;4ZiXE\RT4Ra>17`8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`hy%{~z|/Lov|Zehey;TKCJP192\kZKRPV2Tc<<9b:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqf{'}xx~!Bmtz\gjkw9VMEHR?70^m\IP^X0Ve:?;l4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsdu)z~x#@czx^aliu7XOGNT=5>Po^OV\Z>Xg8>=86[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fubw+qt|z%hc`~>_FLG[4>7WfUFYUQ7_n7b?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~kx"z}{s.pbiZ`rdeUmnRg:7:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqf{'}xx~!}al]eqijXa=l0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!}al]tvZciW`;<o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)JimnTkdm?.fa3*firf}Q8QRIAD^34<ZiXimnT<RAZT^zlv97998=h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*KflmUlen>!gb2-gjsi|R9VSJ@K_05;[jYflmU;SB[[_ymq87869>i0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!xpovq+HgclVmbo= hc1,`kphsS:WTKCJP16:\kZgclV:TCXZPxnp?7;76=h1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cle7&ni;"naznu>2:0g<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%||cz}/fk`4+ad8'idycz32?7b?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ifc1,dg5(dg|d0>081:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rvi|{%len>!gb2-gjsi|R9VSJ@K_05;[jYflmU;SB[[<0<45>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!hib2-cf6)kfexV=R_FLG[41?WfUjhiQ?_NWW878092_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dmf6)oj:%ob{atZ1^[BHCW8=3SbQnde]3[JSS4:4>56[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZ7212_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dmf6)oj:%ob{at^06=>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!hib2-cf6)kfexR=:d:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rvi|{%len>!gb2-gjsi|Vn:0=0:d:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rvi|{%len>!gb2-gjsi|Vn:0<0:d:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rvi|{%len>!gb2-gjsi|Vn:0?0:d:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rvi|{%len>!gb2-gjsi|Vn:0>0:c:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rvi|{%len>!gb2-gjsi|Vn:S=;l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mbo= hc1,`kphsWm;T=8m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'nch<#il0/alqkrXl8U99n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(o`i;"jm?.bmvjqYc9V9>h6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb5484>h6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb54;4>h6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb54:4>o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb5W8?h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*ank9$lo= lotlw[a4X:<i0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!xpovq+bod8'mh<#m`uov\`7Y4=>1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"y}_qlwvZvk}z;7<3Qfnw7f?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt({U{by|Ppmwp5969W`d}=RGAV^2;5>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/ofi*aee'miaj hbleb*kabkj$iaj!hn`vjr`djo'djxdxj_cnh[hcjWnoe#{ocie,`wqt3l2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+kbe&~f|R|nm^pg[`h3m2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+kbe&~f|R|nm^pg[`h6;:1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wgjW{nTic=<;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%ym`Qxr^gm10=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(EdsSjPrrv\evtboVMEHR?=_n]NQ]Y5Wf;:985Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae Mlw{[rtXzz~Tm~|jg^EM@Z75WfUFYUQ>_n327a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(ZZ^TJXBC_FGM0==R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(o{yh< hrrv\bpjk&{ySi?;8:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$~~zmlj-dvvrc9'myyQiumn-vvrXl;>37X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"i}suf2*btt|Vl~`a }su]g71e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'gm|~i||t/eqwq(ulVxxxR|jg=2=0f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(fn}yh}{.fppp+tcW{ySkh<0<7g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h rrvahn)io~xo~~z!gsqw*wbXzz~T~hi32?6a?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!}su`oo*h`{nyy hrrv-vaYu{}UyijQ?4c9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#}{bmi,jbqul{y"j||t/pg[wusW{olS<:m;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%yylck.ldswbu{}$l~~z!re]qwqYumnU98n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae nfuq`wus&nxxx#y}_sqw[wc`494?o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!agvpgvvr)o{y"z|Prrv\v`a;97>i7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"`hwsfqwq(`zz~%{Q}su]qabY7<k1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wusjea$bjy}dsqw*btt|'}yS}{_sgd[45c3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&xoS}{_`qqab2b3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&xoS}{_`qqabY@FMU:>RaPMTZ\6Zi382_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%yhR||t^cpv`aXl8>;7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"|k_sqw[duumnUo>>m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&xxxobd/sf\vvrXkfgi?i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae re]qwqYdgdh:?i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae ws]qwqYf{{ol8h5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae ws]qwqYf{{olSJ@K_00\kZKRPV;Tc9>4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&xxxobd/vp\vvrXizxnkRj>419V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#}{bmi,swYu{}Ujkh_e00g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h rrvahn)pzVxxxRm`mc1g?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!}su`oo*quW{ySnabb0a8QVCUW_CXEOBJ9:TJARYSQYO<7[G]TDZ5<>QBI5:1<384WDC?4;0<_LK7=384WDC?6;><_LK7?7>16:UFE95902]NN1>50?48S@D;8720[HLXE=2=<>QBJ^O7=364WD@TA94902]NNZK33?:8S@DPM5>546YJBVG?1;><_LH\I181a:UFFRC;?3:546YJBVG?3;d<_[C_IRHFRRV`?RTN\LUFCIKPAb9TVLRBWDEOIRLk;VPJP@YPAM^CSLj4WSKWAZQNL]BTN<j4XHNJJ]+_LK*;"<.\TT@#4+7'IZIBE;5WSUNJF2=_[]ULBIl4X^ALV@YNFOE=7Ujm_Hfe?]boWYxba[k}shmm55=_ldUFmga}Vdppmjh682RoaRCfnnpUawungg90T~z<;Xgp<d=XWVRGB@QP_1]\[P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"Cnde]dmf6)oj:%ob{atZ1^[BHCW8=3SbQnde]3[JSSWqey0?0>1978[ZY_DGGTSR?P_^W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%FmijPgb2-gjsi|R9VSJ@K_051[jYflmU;SB[[_ymq87869>i0SRQWLOO\[Z4XWV_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwY`kVkx~hiPl`qw_6[Xzln~ohQwos]26Zi6?k1TSRVCNL]\[6YXW\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"y}_qlwvZadWhyyijQcarvX7XYummhiRv`r^5\k41c3VUTTA@B_^]7[ZYR8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$Aua}_SF\TKRUS8WT^IQ_NUPX6XY_G[U:=RaPxn>3:41d3VUTTA@B_^]6[ZYR8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$Aua}_VP\TKRUS8WT[_Q_NUPX6XY_G[U9SbQwo=2=5c=f{pdhSkgio^35|<77il1jt`l_gkekZ71p0&mekaPgdlfvdrhzV|2S>"tc^cg`Zh`kVidb~z}ahlw95*dWhz{`dmnthmm[qwmVkse~3?,b]btujnkh~bccQ{yqg\vdeo59&hSl~lhabpliiW}s{iR|kci?3(fYfxyfbolzfoo]w}ucXhic1="l_`rshlef|`eeSywe^uggm;7$jUj|}bfc`vjkkYsqyoT{mg=1.`[d~nWhno~Ryfduj>77*dWhrbSl|zsdp\slbs`4;'oRowi^ctqvcuW~coxe3>,b]b|lYe}zoySzgkti?2(fYfp`UomyoPwhfwl803$jUjtdQfd^uj`qn:<%iTmugPrtqfvZqnl}b6=!mPayk\p|vb59&hSlvf_vwpawYpam~c1<"l_`zjwZrci}kT{dj{h<47(fYfp`yTxik|t^uj`qn:<%iTmug|_ukg[roc|a73 nQnxhq\pncbxV}bhyf24-a\e}otW}y~oQxievk91*dWhrbRzzsdp\slbs`4>'oRowir]w}uc:8%iTobcboo]`hjel59&hSnaznu]w}uc:8%iThlzn_bmvjqYpam~c19"l_egeepjsWkgyh3Ml`lhWqtnfn&hSiga_vkgpm;>$jUoecQxievk[d~n{4;'oRjfn^uj`qnXzhic1><#c^fjjZqnl}bT~img=76/gZbnfV}bhyfPw`ak964+kVnbbRyfduj\saeo5?>'oRjfn^uj`qnX{ic1?"l_emvpZtt|V|j`0>#c^flqqYpam~c14"l_dlbficXzeeh0>#c^gmegjbW{yS~wac<3/gZcuzfxTecdjcukljZr~xl7; nQjrsmq[lhmmj~bccQ{yqg\e}ot59&hSh|}os]jjocd|`eeSywe^pbgm;7$jUn~a}_hliafrnggUu}kPreak95*dWlxycQfnkg`pliiW}s{iRynci?3(fYbz{eySd`eebvjkkYsqyoT{img=1.`[`tug{Ubbgklthmm[qwmV}yoe3?,b]eehokq4|b~ykw6-a\bpjkWofjk~Q}su]uei;6$jUcm~QnllmppZcjx}s6<!mPh`q\eikh{}Umyab20-a\lduXiqcTm{|es?3(fYoizUjtdQnwtqfv86+kVbjRowi^`vw`t:8%iTdl}Payk\vaYd`hdeia3?,b]kevYfp`Uyy~k}=1.`[mgtWhrbSz|Pcicmj`j:8%iTdl}Payk\spubz4:'oRfns^c{mvYslh~j1="l_icp[d~n{V~oi~z20-a\lduXiqcxSygk=1.`[mgtWhrbRzdedr>4)eX`hyTmug|_unbwq;7$jUcm~Qnxhq\pwcflp7: nQgar]b|luX|z~yn0>#c^jbwZgazUy~k}=1.`[mgtWkkhgx~20-a\lduXlh~jSnaznu?3(fYoizUomyoPcnwmpvYfp`y6<!mPh`q\`drfWje~by}Pr`ak95*dWakxSio{a^alqkrtW{nhd0>#c^jbwZbf|hUhcx`{s^ubgm;7$jUcm~Qkauc\gjsi|zU|hnf20-a\lduXlh~jSnaznuq\sweo59&hSeo|_hlw[fjl59&hSeo|_lcpp`tXkl7; nQgar]nahoia}Umeak20-a\lduXgoyjaax=1.`[mgtWyxdkRhcafq\e}ot59&hSeo|_qplcZ`kinyT~lmg=1.`[mgtWyxdkRhcafq\vaeo59&hSeo|_qplcZ`kinyT{lmg=1.`[mgtWyxdkRhcafq\saeo59&hSeo|_qplcZ`kinyT{mg=1.`[mgtW{nThlzn_bmvjq;7$jUcm~Q}d^ppp86+kVbjR||t<3/gZnf{Vygm{kPcd?3(fYoizUx~~z20-a\lduX}gnn~kb`w<2/gZnf{V|j`dj20-a\lduX{Ujof3?,b]kevYpzVnjxlQlotlw95*dWakxSz|Prrv>4)eXadzgi`kat`vjkkYsqyo6>!mPilroahci|h~bccQ{yqg\e}ot58&hSdcldofjqgsafdTxt~j_sc`l87+kVcf|akbeovbpliiW}s{iR|kci?2(fYneyfnah`{aukljZr~xlU|mnf21-a\mhvkmdoexlzfoo]w}ucXmic1<"l_hosh`kbf}keb`Ptxrf[rtd`4;'oRgaiu]tvZvi|{U}ma3?,b]jjqcunhinSywe<2/gZkbefxrSywe<3/gZknnVlb`hQaalg>FigicZ~yeci#c^opcjhX~hf6=!mPoqvjil|f|`eeS`ake<2/gZiqm{lgczQcov?3(fYwzlfdmiQcaugmg|;6$jU{~hb`ae]qabu:8%iT|gb_gkekZr~xl7>=?v<6-a\twi`Wlg{xtQ{hsgplZgt{lxS{oc=3.`[uthoVof|ywPtipfwmYf{zoyxRxnl^c{mv;68;8'oR~}of]fiur~W}byi~fParqfvqYqieUymnf21101(fYwzfmTi`~{y^vkv`uoWhyxizPv`n\vaeo58:9>!mPpsmd[`kw|pUdk|h^cpw`tsWkgSzolh<3367*dWyxdkRkbpu{\pmtb{aUj~k}t^tbhZqcka7:<?<#c^rqkbYbey~rSyf}erj\evubz}U}maQxrbj>5545$jU{~biPelrw}ZrozlycSckhaug\rdj:;%iT|ah_dosp|Ysqyo6<!mPpsmd[`kw|pUu}kPaykp95*dWyxdkRkbpu{\p|vbW{khd0>#c^rqkbYbey~rSywe^pggm;7$jU{~biPelrw}Zr~xlU|mnf20-a\twi`Wlg{xtQ{yqg\saeo59&hS}|`g^gntqX|pznSz|lh<2/gZvugnUmyabPtipfwmYf{zoyxRxnl<30(fYwzfmTjxbc_ujqavnXizyn~yQyam]b|lu:9988 nQrne\bpjkW}byi~fParqfvqYqieUymnf21100(fYwzfmTjxbc_ujqavnXizyn~yQyam]q`fn:9988 nQrne\bpjkW}byi~fParqfvqYqieU|mnf21100(fYwzfmTjxbc_ujqavnXizyn~yQyam]t`fn:9988 nQrne\bpjkW}byi~fParqfvqYqieU|~nf21100(fYwzfmTjxbc_ujqavnXflmjxhQyam?26)eXx{elSk{cl^vzt`;7$jU{~biPftno[qwmVkse~3?,b]svjaXn|fgSywe^pbgm;7$jU{~biPftno[qwmVxooe3?,b]svjaXn|fgSywe^ubgm;7$jU{~biPftno[qwmV}ooe3?,b]svjaXn|fgSywe^uqgm;7$jUymnfPtxrf95*dW{nThlzn_bmvjqYpam~c19"l_sf\``vs`4;= nQ}d^dqat;6$jUyhR~ats]tmaro5=&hSjlh^vzt`;7$jUyijQ|lhaf[hicmVkse~3?,b]qabYtd`inS`ake^pbgm;7$jUyijQ|lhaf[hicmVxooe3?,b]qabYtd`inS`ake^ubgm;7$jUyijQ|lhaf[hicmV}ooe3?,b]qabYtd`inS`ake^uqgm;7$jUxucmgrnlj~`tX{}kli0<#c^wm``tadf}T`by20-a\qvcXkfgfccQ`vdpehjq:8%iTy~kPcnonkkYrfmoyjaax=1.`[pubWmommxb{_rgwplh`{4:'oR{|e^flqqYu{}7: nQzsd]fgf;7$jU~hQjcb]b|lu:8%iTy~kPeba\vdeo59&hSx}j_da`[wbd`4:'oR{|e^g`gZqfka7; nQzsd]fgfYpljb6<!mPurg\afeX{ic1="l_tqf[`kemmnnhR|jg<2/gZstmVlbjb?9_gnbcv;7$jU~hQiwgv\`drfWje~by3?,b]ueiocWee|1="l_vc`lZr~xl7; nQxdbj\p|vb59&hSz|Pabi\hjq:8%iT{Qkauc\gjsi|V}bhyf24-a\swYcmy~c1<8#c^uq[acw|aUjtd}21107(fYpzVnn|yfPr`ak940+kV}ySikti]q`fn:998? nQxr^fftqnXhic1<8#c^uq[acw|aU|hnf21107(fYpzVnn|yfPwsak940+kV}ySk|jq<3/gZquWyd~Ryfduj>0)eX{U{by|PwhfwlZgaz7:<!mPws]sjqtX`ndR|nci?7(fYpzVzexQxievk[wbd`4;; nQxr^rmpwYpam~cSzolh<6/gZquWyd~Ryfduj\saeo58:'oRy}_qlwvZqnl}bT{mg=5.`[rtXzly{cc}j_mcwake~58&hSz|lh^vzt`;7u;<0m~wac^djbjY6>q3'jdh`_fgmawgsg{U}5R=#{|3;?gjlWdofSjka_fgmawodWjy~<84bmi\i`kXoldT|gb_vkgpm7e3kf`S`kb_fgm[utneV}ym}~jr^t5b>dkcVgnaRijn^vlt42<jeaTahcPgdl\r2Y6Wqy=>5mlj]nahYnfySob`cj37?gjlWdofSb{{ptv\fiidck1h`fQw_qlwvv1<kfg{mk<;efn2>bnf5:5:6jfn=3=2>bnf585:6jfn=1=2>bnf5>5:6jfn=7=2>bnf5<5:6jfn=5=<>bnf521<384dhl?<;1<lf0=08;emvp979?2ndyy2=>69gkpr;;7=0hb{{<5<4?air|5?5;6j`uu>5:2=cg|~7;374dnww8=<76>1ocxz38?78ahvsq8<0jdh`_fgmawgsg{Uym`hffn31?coagVmnbh|ntnp\pjv6;2lbjbQheogqeqiuW3T??h4fhdl[bcim{kcQy9^1/$]okagr+OB\J Fgmawgsg{*:8#9>7:djbjY`mgoymya}_w;\7Z~t|=1myab6;hlsqqYedb<0ahc`rx:8jbee}`fo>6``a:mvpussWkf`??5}alnlku]7U'xja#| v7]mklhn|'xja"]KP/UJ@@YWZ@G:4#|nmc9q`ZdnfViex84re]`hn3<zmUnb55}d^nlcle6:2xoS~znttq\big`{Vkx=<5}ergw[gjlW{kfjdh`3:pppc=tqgic~b`fzdp\bcd<{UiecQlnup5?rtXkea>7z|Peo:8swYkgnch=?5xr^qweqstWofjk~Qns|BCt17>3IJs>5o5F;695~U?9383>7?82;307023?3;2=4jtn3:3>4=i:1;1:6*=7d813d=z[>l1>5<516095652<==1=4?nf:Q227<5j=0;6<=<5564>4?6j;1X;k4=b583>454==><6<7>b49g6=g=83;1=v]71;0;6?70:3;8?8:;7;3:5dc<~];2j7>51;39<5}T08094?4>73827633<>0:5<oj;%056?71<2\9;k4={t35f?7<}8<h6=5r$050>70<j;2j6=4>9;4:>2`|@;<:7)?n4;0;e>\1=38p>h4<1;'62b=:hl0(;6529a8 =6=:1h0(<7m:09'5<g=:190e?o?:18'523=:0l0b<9;:198m7?b290/=:;528d8j4132810e?7k:18'523=:0l0b<9;:398m7?d290/=:;528d8j4132:10e?7m:18'523=:0l0b<9;:598m7?f290/=:;528d8j4132<10e?76:18'523=:0l0b<9;:798m7??290/=:;528d8j4132>10e?78:18'523=:0l0b<9;:998m7db2900e?m>:188m7d>2900e?m=:188m7df2900c?on:18'523=:h30b<9;:198k7g?290/=:;52`;8j4132810c?o8:18'523=:h30b<9;:398k7g1290/=:;52`;8j4132:10c?o::18'523=:h30b<9;:598k7g3290/=:;52`;8j4132<10c?o<:18'523=:h30b<9;:798k7g5290/=:;52`;8j4132>10c?o>:18'523=:h30b<9;:998k7d62900c?om:188f71d290:6=4?{%3b0?77j2B9;o5G2738k46f2900qo<?3;290?6=8r.:m94>099K62d<@;<:7)?>b;58m30=831b4?4?::k232<722e:;44?::a654=83>1<7>t$0c7>46?3A8<n6F=609'54d=?2c=:7>5;h:1>5<<a8=<6=44o05:>5<<uk89>7>54;294~"6i=0:<55G26`8L7063-;:n794i7494?=n0;0;66g>7683>>i6?00;66sm23394?2=83:p(<o;:02;?M40j2B9:<5+10`93>o1>3:17d6=:188m4102900c<96:188yg43?3:187>50z&2e1<68?1C>:l4H342?!76j390e;850;9j3`<722c3>7>5;n34=?6=3th9984?:583>5}#9h>1==64H35a?M4192B=?6*>6`82e6=n>?0;66g72;29?l70?3:17b?89;29?xd5=k0;694?:1y'5d2=9920D?9m;I055>N1;2.::l4>a29j23<722c3>7>5;h343?6=3f;<57>5;|`10d<72=0;6=u+1`6955><@;=i7E<91:J57>"6>h0:m>5+10`93>o1>3:17d6=:188m4102900c<96:188yg4203:1?7>50z&2e1<68<1C>:l4H342?M043-;=m7?n3:&25g<43`<=6=44i9094?=h9>31<75rb37f>5<4290;w)?n4;331>N5?k1C>;?4H718 40f28k87)?>b;18m30=831b4?4?::m23<<722wi>9750;694?6|,8k?6<>7;I04f>N5>81C:>5+17c95d5<,8;i6:5f6783>>o?:3:17d?87;29?j7013:17pl=5183>1<729q/=l:511:8L71e3A8==6*>1c84?l012900e5<50;9j521=831d=:750;9~f72a290?6=4?{%3b0?7702B9;o5G2738 47e2>1b:;4?::k;6?6=3`;<;7>5;n34=?6=3th98h4?:583>5}#9h>1==64H35a?M4192.:=o48;h45>5<<a181<75f16594?=h9>31<75rb374>5<4290;w)?n4;331>N5?k1C>;?4H718 40f28k87)?>b;18m30=831b4?4?::m23<<722wi>8:50;694?6|,8k?6<>7;I04f>N5>81/=<l57:k52?6=3`296=44i054>5<<g8=26=44}c067?6=<3:1<v*>a5824==O:>h0D?8>;%32f?1<a?<1<75f8383>>o6?>0;66a>7883>>{e:<n1<7=50;2x 4g328:>7E<8b:J124=O>:1/=;o51`18 47e2:1b:;4?::k;6?6=3f;<57>5;|`10=<72=0;6=u+1`6955><@;=i7E<91:J57>"6>h0:m>5+10`93>o1>3:17d6=:188m4102900c<96:188yg4383:1?h4=:33xL7063-;j87<7d:X51?b|990n6<<51e81g?762o0:?7?j:3f96c<4838;6p*94;08m4>b290/=:;519f8j4132910e<69:18'523=91?0b<9;:198m702290/=:;52768j4132910e>650;&230<4?2d:;94?;:k02?6=,8=>6>94n057>4=<a:?1<7*>74803>h6?=0976g<4;29 4122:=0b<9;:298mg6=83.:;84nf:l231<732cji7>5$056>d`<f8=?6<54i`f94?"6?<0jj6`>7581?>ofk3:1(<9::`d8j4132:10ell50;&230<fn2d:;94;;:kbe?6=,8=>6lh4n057>0=<ah31<7*>748bb>h6?=0=76gn8;29 4122hl0b<9;:698md1=83.:;84nf:l231<?32c:5=4?:%341?7?n2d:;94?;:k2<d<72-;<97?79:l231<732c9:o4?:%341?41i2d:;94?;:k7b?6=,8=>69k4n057>5=<a=n1<7*>7487a>h6?=0:76g;c;29 4122=o0b<9;:398m1d=83.:;84;e:l231<432cim7>5$056>g?<f8=?6=54ic:94?"6?<0i56`>7582?>oe?3:1(<9::c;8j4132;10eo850;&230<e12d:;94<;:ka1?6=,8=>6o74n057>1=<ak>1<7*>748a=>h6?=0>76gm3;29 4122k30b<9;:798mg4=83.:;84m9:l231<032ci=7>5$056>g?<f8=?6554i7d94?=nno0;66g85;29?l7793:17d?90;29?l72n3:17bh;:18'523=n:1e=::50:9lb7<72-;<97h<;o340?7<3fl:6=4+1679b6=i9>>1>65`f183>!70=3l87c?84;18?jca290/=:;5f29m522=<21dih4?:%341?`43g;<87;4;ngg>5<#9>?1j>5a16692>=hmj0;6)?85;d0?k70<3=07bkm:18'523=n:1e=::58:9lb`<72-;<97hk;o340?6<3flh6=4+1679ba=i9>>1=65`fc83>!70=3lo7c?84;08?j`f290/=:;5fe9m522=;21dj44?:%341?`c3g;<87:4;nd;>5<#9>?1ji5a16691>=hn>0;6)?85;dg?k70<3<07bh9:18'523=nm1e=::57:9lb0<72-;<97hk;o340?><3f;3<7>5$056>41a3g;<87>4;n34a?6=,8=>6<9i;o340?7<3f;<h7>5$056>41a3g;<87<4;n34g?6=,8=>6<9i;o340?5<3f;247>5;n:0>5<<j;=h6=4>:183!7f<3;;n6F=7c9K637<g8:j6=44}c0a3?6=090;6=u+1`6952g<@;=i7E<91:X51?c|9?0:;7659;3;>4?=9h0:n7o5b;a9`?4?28l1q)?81;0a1>hc:3:0bh:50:&256<23-;:87;4$036>0=#98<196*>1686?!7603?0(<?6:49'54g==2.:=n4:;%32`?3<,8;n685+10d91>"6:90>7)?=1;78 4452<1/=?=55:&261<23-;997;4$005>0=#9;=196*>2986?!7513?0(<<n:49'57d==2.:>n4:;%31`?3<,88n685+13d91>"6;90>7)?<1;78 4552<1/=>=55:&271<23-;897;4$015>0=#9:=196*>3986?!7413?0(<=n:49'56d==2.:?n4:;%30`?3<,89n685+12d91>"6<90>7)?;1;78 4252<1/=9=55:&201<23-;?97;4$065>0=#9==196*>4986?!7313?0(<:n:49'51d==2.:8n4:;%37`?3<,8>n685+15d91>"6=90>7)?:1;78 4352<1/=8=55:&211<23-;>97;4$075>0=#9<=196*>5986?!7213?0(<;n:49'50d==2.:9n4;;%36`?2<,8?n6<8i;%34f?7>12.:4<474:l2<7<5<2d:4>4?;%3:1?7?<2.:5;4>859'5<e=>;1/=4j52718 4g72=1/=l?54:&133<5?<1/>:952678j71?291e>:75259'5<1=99>0e::50;9j32<722c:<=4?::k247<722c:4:4?::k2<=<722c:4o4?:I3:a>=n91i1<7F>9d98m4?62900e<7=:188m4?42900e<7;:188m6c=83.:;84<d:l231<732c8o7>5$056>6b<f8=?6<54i2`94?"6?<08h6`>7581?>o4i3:1(<9::2f8j4132:10e9950;&230<4l2d:;94;;:k72?6=,8=>6>j4n057>0=<a=?1<7*>7480`>h6?=0=76g;4;29 4122:n0b<9;:698m15=83.:;84<d:l231<?32c?>7>5$056>6b<f8=?6454i5394?"6?<08h6`>758b?>o383:1(<9::2f8j4132k10e>h50;&230<4l2d:;94l;:k0=?6=,8=>6>j4n057>a=<a=k1<7*>7487=>h6?=0;7E?6e:9j0=<72-;<97:6;o340?7<@83n76g:2;29 4122<;0b<9;:19K5<c<3`?;6=4+167914=i9>>1=6F>9d98m0>=83.:;84:7:l231<732c>:7>5$056>01<f8=?6<54i4794?"6?<0>;6`>7581?>o2<3:1(<9::458j4132:10e;?50;&230<2?2d:;94;;:k54?6=,8=>6894n057>0=<a<l1<7*>74863>h6?=0=76g:e;29 4122<=0b<9;:698m0b=83.:;84:7:l231<?32c>o7>5$056>01<f8=?6454i4`94?"6?<0>;6`>758b?>o2i3:1(<9::458j4132k10e8750;&230<2?2d:;94l;:k67?6=,8=>6894n057>a=<a1i1<7*>748;f>h6?=0;76g7a;29 41221h0b<9;:098m=?=83.:;847b:l231<532c347>5$056>=d<f8=?6>54i9594?"6?<03n6`>7587?>o?>3:1(<9::9`8j4132<10e4;50;&230<?j2d:;949;:k:0?6=,8=>65l4n057>2=<a091<7*>748;f>h6?=0376g62;29 41221h0b<9;:898m<7=83.:;847b:l231<f32c2<7>5$056>=d<f8=?6o54i9d94?"6?<03n6`>758`?>o?m3:1(<9::9`8j4132m10e5j50;&230<?j2d:;94j;:k;1?6=,8=>65l4n057>c=<a0n1<7*>748:g>h6?=0;76g6b;29 41220i0b<9;:098m<g=83.:;846c:l231<532c257>5$056><e<f8=?6>54i8:94?"6?<02o6`>7587?>o>?3:1(<9::8a8j4132<10el850;&230<>k2d:;949;:kb1?6=,8=>64m4n057>2=<ah>1<7*>748:g>h6?=0376gn3;29 41220i0b<9;:898md4=83.:;846c:l231<f32cj=7>5$056><e<f8=?6o54i`294?"6?<02o6`>758`?>o>n3:1(<9::8a8j4132m10e4k50;&230<>k2d:;94j;:k:2?6=,8=>64m4n057>c=<akn1<7*>748ag>h6?=0;76gmb;29 4122ki0b<9;:098mf6=83.:;84mf:l231<732cii7>5$056>g`<f8=?6<54ob:94?"6?<0h;6`>7583?>id>3:1(<9::b58j4132810cn;50;&230<d?2d:;94=;:m`0?6=,8=>6n94n057>6=<gj91<7*>748`3>h6?=0?76al2;29 4122j=0b<9;:498ka7=83.:;84l7:l231<132eo<7>5$056>f1<f8=?6:54obd94?"6?<0h;6`>758;?>idm3:1(<9::b58j4132010cnj50;&230<d?2d:;94n;:m`g?6=,8=>6n94n057>g=<gjh1<7*>748`3>h6?=0h76ala;29 4122j=0b<9;:e98kf?=83.:;84l7:l231<b32eh=7>5$056>f1<f8=?6k54oec94?"6?<0o56`>7583?>ic03:1(<9::e;8j4132810ci950;&230<c12d:;94=;:mg2?6=,8=>6i74n057>6=<gm?1<7*>748g=>h6?=0?76ak4;29 4122m30b<9;:498k`5=83.:;84k9:l231<132en>7>5$056>a?<f8=?6:54od394?"6?<0o56`>758;?>ib83:1(<9::e;8j4132010cih50;&230<c12d:;94n;:mga?6=,8=>6i74n057>g=<gmn1<7*>748g=>h6?=0h76akc;29 4122m30b<9;:e98kad=83.:;84k9:l231<b32eo?7>5$056>a?<f8=?6k54od594?"6?<0n:6`>7583?>ib=3:1(<9::d48j4132810cho50;&230<b12d:;94?;:mf<?6=,8=>6h74n057>4=<a;<26=4+167963><f8=?6=5G18g8?l41?3:1(<9::34;?k70<3;0D<7j;:k123<72-;<97<98:l231<532c9:84?:%341?4102d:;94<;:k131<72-;<97<83:l231<73A;2i65f26094?"6?<09;>5a16695>N61l10e?9>:18'523=:>90b<9;:39K5<c<3`8<<7>5$056>7143g;<87=4H0;f?>o5>o0;6)?85;047>h6?=0?76g=6d83>!70=38<?6`>7586?>o5>m0;6)?85;047>h6?=0=76g=6b83>!70=38<?6`>7584?>{t:??1<7;t^346?84e?38=j63=b6812`=::k=1>;j4=3`4>70d3ty847>52z\0<>;5j>0=<6s|3783>7}Y;?16>o955g9~w63=838pR>;4=3`4>0c<uz9?6=4={_17?84e?3?o7p}m0;296~Xe8279n:4n6:pe`<72;qUmh522c59e0=z{hn1<7<t^`f897d020o0q~ol:181[gd348i;779;|qbf?6=:rTjn63=b68:1>{tih0;6?uQa`9>6g1=1=1vl750;0xZd?<5;h<65k4}rc;>5<5sWk370<m7;:g?xuf?3:1>vPn7:?1f2<?=2wx=4>50;1xZ4?7348i;7?61:?1f2<61;1v9h50;0xZ1`<5;h<6984}r6g>5<5sW>o70<m7;66?xu3k3:1>vP;c:?1f2<3<2wx8o4?:3y]0g=::k=18>5rs7d94?4|V?l01?l8:658yv`a2909wShi;<0a3?77:2wx;84?:3y]30=::k=1;95rs022>5<5sW;;=63=b68245=z{oo1<7<t^gg897d02l90q~hl:181[`d348i;7k=;|qef?6=:rTmn63=b68gf>{tnh0;6?uQf`9>6g1=l:1vk750;0xZc?<5;h<6i?4}rd;>5<5sWl370<m7;f3?xua?3:1>vPi7:?1f2<di2wxj;4?:3y]b3=::k=1o45rsg794?4|Vo?01?l8:b38yv>4290?9v3=7b824d=Y0:1U=464^0:3?[70m2T:;i5Q16a897d0282<70<m7;64?84e?39j70<m7;1a?84e?39h70<m7;1f?84e?32m70<m7;;3?84e?33:70<m7;;1?84e?33870<m7;`a?84e?32=70<m7;:4?84e?32370<m7;::?84e?32j70<m7;:`?84e?3ho70<m7;;e?84e?3k;70<m7;c2?84e?3k970<m7;c0?84e?3k?70<m7;`f?84e?33<70<m7;;;?84e?33270<m7;;b?84e?33i70<m7;;g?84e?3i;70<m7;42?84e?3??70<m7;76?84e?3?=70<m7;7;?84e?3>970<m7;62?84e?3>;70<m7;1e?84e?39270<m7;7`?84e?3?i70<m7;7b?84e?3?270<m7;70?84e?38=:63=b68120=::k=1=564=3`4>4?4348i;7?64:\ff>Xbk2Tnh6Pje:\fb>Xa82Tm=6Pi2:\e0>{zj;;j6=4::183!7f<3;;;6F=7c9K637<,8;i6>5f6783>>o1?3:17d9j:188m=4=831d=:750;9~f77>290>6=4?{%3b0?77?2B9;o5G2738 47e2:1b:;4?::k53?6=3`=n6=44i9094?=h9>31<75rb33;>5<2290;w)?n4;333>N5?k1C>;?4$03a>6=n>?0;66g97;29?l1b2900e5<50;9l52?=831vn??;:186>5<7s-;j87??7:J13g=O:?;0(<?m:29j23<722c=;7>5;h5f>5<<a181<75`16;94?=zj;;86=4::183!7f<3;;;6F=7c9K637<,8;i6>5f6783>>o1?3:17d9j:188m=4=831d=:750;9~f775290>6=4?{%3b0?77?2B9;o5G2738 47e2:1b:;4?::k53?6=3`=n6=44i9094?=h9>31<75rb332>5<2290;w)?n4;33=>N5?k1C>;?4$03a>2=n>?0;66g97;29?l>52900e<98:188k41>2900qo<<d;291?6=8r.:m94>069K62d<@;<:7)?>b;18m30=831b::4?::k4a?6=3`296=44o05:>5<<uk88o7>55;294~"6i=0:<:5G26`8L7063-;:n7=4i7494?=n>>0;66g8e;29?l>52900c<96:188yg44j3:197>50z&2e1<68>1C>:l4H342?!76j390e;850;9j22<722c<i7>5;h:1>5<<g8=26=44}c003?6==3:1<v*>a58242=O:>h0D?8>;%32f?5<a?<1<75f6683>>o0m3:17d6=:188k41>2900qo<<6;291?6=8r.:m94>069K62d<@;<:7)?>b;18m30=831b::4?::k4a?6=3`296=44o05:>5<<uk8897>55;294~"6i=0:<:5G26`8L7063-;:n7=4i7494?=n>>0;66g8e;29?l>52900c<96:188yg44<3:197>50z&2e1<6801C>:l4H342?!76j3=0e;850;9j22<722c3>7>5;h343?6=3f;<57>5;|`16c<72<0;6=u+1`69551<@;=i7E<91:&25g<43`<=6=44i7594?=n?l0;66g72;29?j7013:17pl=2d83>0<729q/=l:51158L71e3A8==6*>1c80?l012900e;950;9j3`<722c3>7>5;n34=?6=3th9>i4?:483>5}#9h>1==74H35a?M4192.:=o48;h45>5<<a?=1<75f8383>>o6?>0;66a>7883>>{e9kn1<7:50;2x 4g328:=7E<8b:J124=O>:1/=;o51`18 47e2:1b:;4?::k4a?6=3`296=44o05:>5<<uk;ii7>54;294~"6i=0:<;5G26`8L7063A<87)?9a;3b7>"69k087d89:188m2c=831b4?4?::m23<<722wi=oh50;694?6|,8k?6<>9;I04f>N5>81C:>5+17c95d5<,8;i6>5f6783>>o0m3:17d6=:188k41>2900qo?l0;290?6=8r.:m94>079K62d<@;<:7E8<;%35e?7f;2.:=o4<;h45>5<<a>o1<75f8383>>i6?00;66sm1e794?2=83:p(<o;:025?M40j2B9:<5G629'53g=9h90(<?m:29j23<722c<i7>5;h:1>5<<g8=26=44}c3g2?6=<3:1<v*>a58243=O:>h0D?8>;I40?!71i3;j?6*>1c80?l012900e:k50;9j<7<722e:;44?::a5a1=83>1<7>t$0c7>4613A8<n6F=609K26=#9?k1=l=4$03a>6=n>?0;66g8e;29?l>52900c<96:188yg7c03:187>50z&2e1<68?1C>:l4H342?M043-;=m7?n3:&25g<43`<=6=44i6g94?=n0;0;66a>7883>>{e9k?1<7:50;2x 4g328:=7E<8b:J124=O>:1/=;o51`18 47e2:1b:;4?::k4a?6=3`296=44o05:>5<<uk;i:7>54;294~"6i=0:<;5G26`8L7063A<87)?9a;3b7>"69k087d89:188m2c=831b4?4?::m23<<722wi=o950;694?6|,8k?6<>9;I04f>N5>81C:>5+17c95d5<,8;i6>5f6783>>o0m3:17d6=:188k41>2900qo?m8;290?6=8r.:m94>079K62d<@;<:7E8<;%35e?7f;2.:=o4<;h45>5<<a>o1<75f8383>>i6?00;66sm1b;94?2=83:p(<o;:025?M40j2B9:<5G629'53g=9h90(<?m:29j23<722c<i7>5;h:1>5<<g8=26=44}c3`e?6=<3:1<v*>a58243=O:>h0D?8>;I40?!71i3;j?6*>1c80?l012900e:k50;9j<7<722e:;44?::a5fd=83>1<7>t$0c7>4613A8<n6F=609K26=#9?k1=l=4$03a>6=n>?0;66g8e;29?l>52900c<96:188yg7dk3:187>50z&2e1<68?1C>:l4H342?M043-;=m7?n3:&25g<43`<=6=44i6g94?=n0;0;66a>7883>>{e9o81<7:50;2x 4g328:=7E<8b:J124=#98h1?6g96;29?l1b2900e5<50;9l52?=831vn<h>:187>5<7s-;j87??6:J13g=O:?;0(<?m:29j23<722c<i7>5;h:1>5<<g8=26=44}c3e4?6=<3:1<v*>a58243=O:>h0D?8>;%32f?5<a?<1<75f7d83>>o?:3:17b?89;29?xd6mo0;694?:1y'5d2=99<0D?9m;I055>"69k087d89:188m2c=831b4?4?::m23<<722wi=h>50;694?6|,8k?6<>9;I04f>N5>81/=<l53:k52?6=3`=n6=44i9094?=h9>31<75rb0fe>5<3290;w)?n4;332>N5?k1C>;?4$03a>6=n>?0;66g8e;29?l>52900c<96:188yg7cm3:187>50z&2e1<68?1C>:l4H342?!76j390e;850;9j3`<722c3>7>5;n34=?6=3th:hi4?:583>5}#9h>1==84H35a?M4192.:=o4<;h45>5<<a>o1<75f8383>>i6?00;66sm1d694?2=83:p(<o;:025?M40j2B9:<5+10`97>o1>3:17d9j:188m=4=831d=:750;9~f4c4290?6=4?{%3b0?77>2B9;o5G2738 47e2:1b:;4?::k4a?6=3`296=44o05:>5<<uk;n>7>54;294~"6i=0:<;5G26`8L7063-;:n7=4i7494?=n?l0;66g72;29?j7013:17pl>e083>1<729q/=l:51148L71e3A8==6*>1c80?l012900e:k50;9j<7<722e:;44?::a5c0=83>1<7>t$0c7>4613A8<n6F=609'54d=;2c=:7>5;h5f>5<<a181<75`16;94?=zj8l>6=4;:183!7f<3;;:6F=7c9K637<,8;i6>5f6783>>o0m3:17d6=:188k41>2900qo?i4;290?6=8r.:m94>079K62d<@;<:7)?>b;18m30=831b;h4?::k;6?6=3f;<57>5;|`2b6<72=0;6=u+1`69550<@;=i7E<91:&25g<43`<=6=44i6g94?=n0;0;66a>7883>>{e:9>1<7=50;2x 4g328<>7E<8b:J124=#98h1=95f11f94?=n99o1<75`16294?=zj;886=4<:183!7f<3;=96F=7c9K637<,8;i6<:4i02g>5<<a8:n6=44o053>5<<uk8?>7>54;294~"6i=0::;5G26`8L7063-;:n788;h33`?6=3`;;i7>5;h33b?6=3f;<<7>5;|`100<72:0;6=u+1`69533<@;=i7E<91:&25g<6<2c:<i4?::k24`<722e:;=4?::a610=8391<7>t$0c7>4023A8<n6F=609'54d=9=1b==j50;9j55c=831d=:>50;9~f73f29086=4?{%3b0?71=2B9;o5G2738 47e28>0e<>k:188m46b2900c<9?:188yg4183:1?7>50z&2e1<6><1C>:l4H342?!76j3;?7d??d;29?l77m3:17b?80;29?xd5810;694?:1y'5d2=9?<0D?9m;I055>"69k0986*>7781<0=n99n1<75f11g94?=n99l1<75`16294?=zj;:26=4::183!7f<3;=;6F=7c9K637<,8;i6?;4$055>7>23`;;h7>5;h33a?6=3`;;j7>5;h324?6=3f;<<7>5;|`142<72:0;6=u+1`69533<@;=i7E<91:&25g<5:2c:<i4?::k24`<722e:;=4?::a5`0=8391<7>t$0c7>4023A8<n6F=609'54d=:;1b==j50;9j55c=831d=:>50;9~f4c?290?6=4?{%3b0?71>2B9;o5G2738 47e2;h0(<99:3:5?l77l3:17d??e;29?l77n3:17b?80;29?xd6n10;6>4?:1y'5d2=9??0D?9m;I055>"69k09>6g>0e83>>o68l0;66a>7183>>{e9ok1<7:50;2x 4g328<=7E<8b:J124=#98h1>o5+16496=1<a8:o6=44i02f>5<<a8:m6=44o053>5<<uk;jm7>53;294~"6i=0::85G26`8L7063-;:n7<=;h33`?6=3`;;i7>5;n344?6=3th:m:4?:283>5}#9h>1=;;4H35a?M4192.:=o4=2:k24a<722c:<h4?::m235<722wi=l750;194?6|,8k?6<8:;I04f>N5>81/=<l5239'520=:130e<>k:188m46b2900c<9?:188yg7f>3:1?7>50z&2e1<6><1C>:l4H342?!76j3897)?86;0;<>o68m0;66g>0d83>>i6?90;66sm1d;94?3=83:p(<o;:044?M40j2B9:<5+10`966=#9><1>584i02g>5<<a8:n6=44i02e>5<<a8;;6=44o053>5<<uk;mn7>55;294~"6i=0:::5G26`8L7063-;:n7<<;%342?4??2c:<i4?::k24`<722c:<k4?::k255<722e:;=4?::a5cc=83=1<7>t$0c7>40>3A8<n6F=609'54d=:h1b==j50;9j55c=831b==h50;9j546=831b=<?50;9j544=831d=:>50;9~f4`a290?6=4?{%3b0?71>2B9;o5G2738 47e28i0e<>k:188m46b2900e<>i:188k4172900qo<?0;292?6=8r.:m94>699K62d<@;<:7)?>b;04?l77l3:17d??e;29?l77n3:17d?>0;29?l7693:17b?80;29?xd59j0;6:4?:1y'5d2=9?30D?9m;I055>"69k09m6g>0e83>>o68l0;66g>0g83>>o6990;66g>1083>>o69;0;66a>7183>>{e:8o1<7950;2x 4g328<27E<8b:J124=#98h1:6g>0e83>>o68l0;66g>0g83>>o6990;66g>1083>>o69;0;66a>7183>>{e:8l1<7950;2x 4g328<27E<8b:J124=#98h1><5f11f94?=n99o1<75f11d94?=n98:1<75f10394?=n9881<75`16294?=zj;;o6=4::183!7f<3;=;6F=7c9K637<,8;i6<;4i02g>5<<a8:n6=44i02e>5<<a8;;6=44o053>5<<uk8997>54;294~"6i=0::;5G26`8L7063-;:n7==;%342?4?<2c:<i4?::k24`<722c:<k4?::m235<722wi>?850;794?6|,8k?6<88;I04f>N5>81/=<l5329'520=:1>0e<>k:188m46b2900e<>i:188m4772900c<9?:188yg45<3:1?7>50z&2e1<6><1C>:l4H342?!76j3827d??d;29?l77m3:17b?80;29?xd6i10;6>4?:1y'5d2=9??0D?9m;I055>"69k0956*>7781<<=n99n1<75f11g94?=h9>:1<75rb0c6>5<4290;w)?n4;351>N5?k1C>;?4$03a>7?<,8==6?67;h33`?6=3`;;i7>5;n344?6=3th9<<4?:783>5}#9h>1=;64H35a?M4192.:=o4>029j55b=831b==k50;9j55`=831b=<>50;9j547=831d=:>50;9~f76129096=4?{%3b0?7192B9;o5G2738m46d2900c<9?:188yg44n3:1>7>50z&2e1<6>81C>:l4H342?l77k3:17b?80;29?xu5jl0;6:uQ2cg8972?28=<70<;9;343>;5<h0:;:5224`9521<5;?>6<98;<073?1b3ty::i4?:06x971d28:j70<;8;:1?842;32970<:4;:1?843m32970<;f;:1?842832970<;0;3;a>;5<909:o522529fd=::=:1n5522529f2=::=:1n;522529f0=::=:1n9522529f6=::=:1n?522529f4=::=:1=;>4=363>43a3ty:h44?:2y>5ab=9>301??k:02f?846k3;:=6s|1ec94?5|58nn6<96;<02b?77n279=i4>0e9~w4be2908w0?kf;34=>;59l0:=<5220a955b<uz;oo7>53z?2a5<6?016><k511g8977d28:m7p}>ec83>7}:9ll1=:74=322>46c3ty:in4?:2y>5c6=9>301<hj:02f?87an3;;i6s|1df94?5|58l:6<96;<3ea?76:279<=4>0d9~w4cb2908w0?i2;34=>;6nl0:==52212955`<uz89>7>52z?167<6?01U>o?4}r077?6=0r79=<497:?157<1?279=>497:?151<1?279=5497:?15<<1?279=l497:?141<6?91v?>=:187847:3;<563=05824`=:9ol1==j4=361>46a3ty9<>4?:3y>655=9>30R?om;|q1e4<72;qU>l?4=363>c3<uz8j>7>52z\1e7=::=:1j;5rs3c0>5<5sW8j?63=418e3>{t:h>1<7<t^3c7?84383l37p}=a483>7}Y:h?01?:?:g;8yv4f>3:1>vP=a79>616=nh1v?o8:181[4f?2798=4ib:p6d>=838pR?o7;<074?`d3ty9ml4?:3y]6dg<5;>;6kk4}r07=?6=<r79><4>769>674=9>=01?:n:908972>28=27p}=4683>7}::==1=:74=33e>46c3ty98i4?:`y>654=9>=01?><:054?84283;<563=108232=::881;h5220193`=::8>1;h5220:93`=::831;h5220c93`=z{;>h6=4>1z?10c<6?016=h?57d9>5`4=?l16=h=57d9>5`2=?l16=hh57d9>5c6=?l16=k?57d9>5c4=?l16=n757d9>5fg=?l16=nl57d9>5fe=?l16=o;57d9>5g0=?l16=o957d9>5g>=?l1v?;=:18a842<3;<563=2e8232=::;o1;h5223d93`=:::>1=:94=316>2c<5;9=6:k4=314>2c<5;9i6:k4=31`>2c<5;9o6:k4}r065?6=98q6>8=516;894`42>o01<h;:6g894`22>o01<h9:6g894bc2>o01<jj:6g894ba2>o01<k?:6g894b22>o01<j9:6g894b02>o01<j7:6g894dc2>o01<lj:6g894da2>o01<m?:6g8yv4d:3:1?vP=c39>675=99n01??j:02e?xu5jh0;69uQ2cc8976328:o70<;2;33`>;5890:<i5rs362>5<5s48?<7??1:?107<6?91v?l6:1815~X5j016>=<5679>655=>?16>895679>61c=>?16>9h5679>606=>?16>865679>603=>?16>9>5749>647=>?16><<5679>645=>?16><:5679>64>=>?16><75679>64g=>?16=h?5679>5`4=>?16=h=5679>5`2=>?16=hh5679>5c6=>?16=k?5679>5c4=>?16=n75679>5fg=>?16=nl5679>5fe=>?16=o;5679>5g0=>?16=o95679>5g>=>?1v?:;:18g843838=963=418eb>;5:m0=;63=2d853>;5:o0=;63=35853>;5;<0=;63=37853>;5;>0=;63=3c853>;5;j0=;63=3e853>;5::0:;=5rs3a2>5<5?rT9o<52233923=::;81:;5225:923=::<n1:;52241923=::<>1:;5225;923=::<o1:;5225c923=::<h1:;52255923=::=:1:k5223f923=::;o1:;5223d923=:::>1:;52227923=:::<1:;52225923=:::h1:;5222a923=:::n1:;521g1923=:9o>1:;521g7923=:9o<1:;521ef923=:9mo1:;521ed923=:9l:1:;521e7923=:9m<1:;521e5923=:9m21:;521cf923=:9ko1:;521cd923=:9j:1:;5rs336>5<2s48?<7:l;<02<?70127:m;4>0e9>5cc=99n01<o::02f?xu59?0;68u225290a=::831=:74=0c4>46c34;j:7??e:?2b`<6981v??8:18684383>m70<>a;34=>;6m=03>63>a6824`=:9oo1==h4}r07f?6=;r798h4>789>616=90:01?:=:02f?xu51>0;6?uQ285897272h=0q~<68;296~X51116>9>5a99~w7?>2909wS<69:?105<f12wx>4o50;0xZ7?f348?<7on;|q1=g<72;qU>4l4=363>dd<uz82o7>52z\1=f=::=:1mn5rs3;g>5<5sW82h63=418b`>{t:0o1<7<t^3;f?84383kn7p}=a183>7}Y:h:01?:?:c28yv4403:18v3=41801>;5;k0:;4521`;955b<58k36<>j;|q17<<72=q6>9>5379>66e=9>301<on:02g?87f13;;i6s|22c94?2|5;>;6>64=31g>41>34;m:76=;<3be?77m2wx>=o50;5x977628=270<?8;33a>;5800:<h52215955c<58k>6<>k;<032?77k279<<4>0d9~w76e290=w0<>2;34=>;59103>63=09824c=::931==h4=324>46c34;mj7??f:p65e=83?p1??<:05:?846132970<?8;33`>;5800:==522129547<uz8;h7>54z?151<6?016><o5839>65?=99n01?>?:033?xu6nm0;6>u22109<7=::9914?522139526<uz89;7>56z?16a<6?016>>;5839>64b=99l01?<::02f?845>3;;j63=25824a=z{;836=4:{<01a?701279?;472:?15`<69916>?;511f8974128:n7p}=2883>1}::;l1=:74=314>=4<5;;n6<>k;<012?77l2wx>>>50;:x975328=270<=5;33b>;5:?0:==52236955c<58k36<>k;<00b?77k279=n4>139>64b=98:0q~<<1;297~;5;<0:;45222`9<7=::8l1==k4}r006?6=;r79?;4>789>66e=0;16><m511g8yv44;3:1?v3=36823<=:::n14?5220a9546<uz89=7>53z?164<6?016>?=511g8977b28;97p}=2183>6}::;;14?522309<7=::8l1=:>4}r062?6=:r7998472:?100<6?91v?;6:187843m3;<;63=4g8232=::<:1=:94=37b>4173ty99n4?:3y>60d=0;16>9851628yv42n3:1?v3=528232=::<>1=:94=343>4173ty9954?:3y>60>=9>301?;n:02f?xu5=>0;6>u224:9<7=::<=1=:74=366>46b3ty9984?:5y>601=0;16>8;516;8972228:o70<:a;33`>{t:<o1<7<t=37f>41>348=<7??e:p60b=839p1?;j:908973c28=270<;6;33a>{t:<h1<7:t=37g>=4<5;?i6<96;<072?77l279:=4>0e9~w72f2909w0<;7;:1?843i3;<56s|25:94?4|5;>265<4=36;>41>3ty9<h4?:3y>644=0;16>=951628yv47n3:1>v3=128;6>;5810:;=5rs333>5<5s48:876=;<03=?7082wx>?o50;0x974c21801?<;:053?xu5:k0;6?u223g9<7=::;?1=:>4}r01g?6=:r79>k472:?163<6?91v<h6:18187a832970?ia;344>{t9o=1<7<t=0d2>=4<58l36<9?;|q2a2<72;q6=ik5839>5`>=9>:0q~?j5;296~;6lo03>63>e78235=z{8ki6=4={<3f5?>534;j97?80:p5de=838p1<k=:90894g128=;7p}>ae83>7}:9l914?521`59526<uz;ji7>52z?2b6<?:27:m54>719~w4ga2909w0?i4;:1?87f13;<<6s|1c294?4|58l>65<4=0cb>4173ty:jn4?:3y>5``=0;16=kl51628yv7bi3:1>v3>de8;6>;6m00:;=5rs0`:>5<5s4;ih76=;<3f5?7012wx=oo50;0x94db21801<k=:05:?xu6jk0;6?u21cd9<7=:9l91=:74}r3ag?6=:r7:o=472:?2a1<6?01v<m::18187d13;<563>fc824a=z{8i=6=4<{<3`e?70127:jl4>0e9>5cd=99o0q~?l7;290~;6kk0:;4521g:955b<58lj6<>j;<3ef?77n2wx=n650;7x94`521801<ml:05:?87a03;;i63>f`824c=:9oh1=<>4}r3`5?6=:r7:o4472:?2f0<6?01v<m=:18187di32970?m6;34=>{t9j91<7<t=0aa>=4<58h<6<96;|q2g1<72;q6=nm5839>5g>=9>30q~?m1;296~;6j<03>63>f2823<=z{8h96=4={<3a2?>534;m87?89:p5g5=838p1<l8:90894`228=27p}>b583>7}:9k214?521g4952?<uz;o=7>52z?2`0<6?016=h7511f8yv7c:3:1?v3>d7823<=:9l21==h4=0g:>46b3ty:h>4?:5y>5a1=9>301<k9:02g?87b03;;h63>e8824c=z{8n?6=4:{<3f4?>534;o47?89:?2a3<68l16=h6511g894c>28;;7p}>ce83>7}:9m?14?521cf952?<uz;hi7>52z?2`3<?:27:nh4>789~w4ea2909w0?k7;:1?87en3;<56s|1e294?4|58n365<4=0a3>41>3ty9?h4?:2y>616=;=16>>:5839>66`=9>:0q~<?5;297~;5<90?n63=108;6>;58?0:;=5rs0df>5<5s4;mi7?80:?144<6981v<hi:18187an3;<<63=00824c=z{;:;6=4={<034?708279<<4>119~w77e2909w0<>c;344>;59o0:=?5rs33`>5<5s48:h7?80:?15c<6991v??k:181846m3;<<63=1g8254=zug9:m7>51zJ124=zf:;i6=4>{I055>{i;8i1<7?tH342?xh49m0;6<uG2738yk56m3:1=vF=609~j67a290:wE<91:m776=83;pD?8>;|l064<728qC>;?4}o116?6=9rB9:<5rn200>5<6sA8==6sa33694?7|@;<:7p`<2483>4}O:?;0qc==6;295~N5>81vb><8:182M4192we??650;0xL7063td8>44?:3yK637<ug99m7>52zJ124=zf:8i6=4={I055>{i;;i1<7<tH342?xh4:m0;6?uG2738yk55m3:1>vF=609~j64a2909wE<91:m766=838pD?8>;|l074<728qC>;?4}o106?6=9rB9:<5rn210>5<6sA8==6sa32694?7|@;<:7p`<3483>4}O:?;0qc=<6;295~N5>81vb>=8:182M4192we?>650;3xL7063td8?44?:3yK637<ug98m7>52zJ124=zf:9i6=4<{I055>{i;:i1<7<tH342?xh4;m0;6?uG2738yk54m3:1>vF=609~j65a2909wE<91:m716=838pD?8>;|l004<72;qC>;?4}o176?6=:rB9:<5rn260>5<5sA8==6sa35694?4|@;<:7p`<4483>7}O:?;0qc=;6;296~N5>81vb>:8:181M4192we?9650;0xL7063td8844?:3yK637<ug9?m7>52zJ124=zf:>i6=4={I055>{i;=i1<7<tH342?xh4<m0;6<uG2738yk53m3:1=vF=609~j62a290:wE<91:m706=83;pD?8>;|l014<728qC>;?4}o166?6=9rB9:<5rn270>5<6sA8==6sa34694?7|@;<:7p`<5483>4}O:?;0qc=:6;295~N5>81vb>;8:182M4192we?8650;3xL7063td8944?:0yK637<ug9>m7>51zJ124=zf:?i6=4>{I055>{i;<i1<7?tH342?xh4=m0;6<uG2738yk52m3:1=vF=609~j63a290:wE<91:m736=83;pD?8>;|l024<728qC>;?4}o156?6=9rB9:<5rn240>5<6sA8==6sa37694?7|@;<:7p`<6483>4}O:?;0qc=96;295~N5>81vb>88:182M4192we?;650;3xL7063td8:44?:0yK637<ug9=m7>51zJ124=zf:<i6=4>{I055>{i;?i1<7?tH342?xh4>m0;6<uG2738yk51m3:1=vF=609~j60a290:wE<91:m726=83;pD?8>;|l034<728qC>;?4}o146?6=9rB9:<5rn250>5<6sA8==6sa36694?7|@;<:7p`<7483>4}O:?;0qc=86;295~N5>81vb>98:182M4192we?:650;3xL7063td8;44?:0yK637<ug9<m7>51zJ124=zf:=i6=4>{I055>{i;>i1<7?tH342?xh4?m0;6<uG2738yk50m3:1=vF=609~j61a290:wE<91:m7=6=83;pD?8>;|l0<4<728qC>;?4}o1;6?6=9rB9:<5rn2:0>5<6sA8==6sa39694?7|@;<:7p`<8483>4}O:?;0qc=76;295~N5>81vb>68:182M4192we?5650;3xL7063td8444?:0yK637<ug93m7>51zJ124=zf:2i6=4>{I055>{i;1i1<7?tH342?xh40m0;6<uG2738yk5?m3:1=vF=609~j6>a290:wE<91:m7<6=83;pD?8>;|l0=4<72;qC>;?4}o1:6?6=:rB9:<5rn2;0>5<6sA8==6sa38694?7|@;<:7p`<9483>4}O:?;0qc=66;295~N5>81vb>78:182M4192we?4650;3xL7063td::>4?:0yK637<utwvLMMt40;9f0`e:=98qMNM{1CDU}zHI
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.vhd b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.vhd
deleted file mode 100644
index eb91ad6..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.vhd
+++ /dev/null
@@ -1,283 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
--- You must compile the wrapper file async_fifo_16x9.vhd when simulating
--- the core, async_fifo_16x9. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-LIBRARY XilinxCoreLib;
--- synthesis translate_on
-ENTITY async_fifo_16x9 IS
-  PORT (
-    rst : IN STD_LOGIC;
-    wr_clk : IN STD_LOGIC;
-    rd_clk : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END async_fifo_16x9;
-
-ARCHITECTURE async_fifo_16x9_a OF async_fifo_16x9 IS
--- synthesis translate_off
-COMPONENT wrapped_async_fifo_16x9
-  PORT (
-    rst : IN STD_LOGIC;
-    wr_clk : IN STD_LOGIC;
-    rd_clk : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END COMPONENT;
-
--- Configuration specification
-  FOR ALL : wrapped_async_fifo_16x9 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
-    GENERIC MAP (
-      c_add_ngc_constraint => 0,
-      c_application_type_axis => 0,
-      c_application_type_rach => 0,
-      c_application_type_rdch => 0,
-      c_application_type_wach => 0,
-      c_application_type_wdch => 0,
-      c_application_type_wrch => 0,
-      c_axi_addr_width => 32,
-      c_axi_aruser_width => 1,
-      c_axi_awuser_width => 1,
-      c_axi_buser_width => 1,
-      c_axi_data_width => 64,
-      c_axi_id_width => 4,
-      c_axi_ruser_width => 1,
-      c_axi_type => 0,
-      c_axi_wuser_width => 1,
-      c_axis_tdata_width => 64,
-      c_axis_tdest_width => 4,
-      c_axis_tid_width => 8,
-      c_axis_tkeep_width => 4,
-      c_axis_tstrb_width => 4,
-      c_axis_tuser_width => 4,
-      c_axis_type => 0,
-      c_common_clock => 0,
-      c_count_type => 0,
-      c_data_count_width => 4,
-      c_default_value => "BlankString",
-      c_din_width => 9,
-      c_din_width_axis => 1,
-      c_din_width_rach => 32,
-      c_din_width_rdch => 64,
-      c_din_width_wach => 32,
-      c_din_width_wdch => 64,
-      c_din_width_wrch => 2,
-      c_dout_rst_val => "0",
-      c_dout_width => 9,
-      c_enable_rlocs => 0,
-      c_enable_rst_sync => 1,
-      c_error_injection_type => 0,
-      c_error_injection_type_axis => 0,
-      c_error_injection_type_rach => 0,
-      c_error_injection_type_rdch => 0,
-      c_error_injection_type_wach => 0,
-      c_error_injection_type_wdch => 0,
-      c_error_injection_type_wrch => 0,
-      c_family => "virtex6",
-      c_full_flags_rst_val => 1,
-      c_has_almost_empty => 0,
-      c_has_almost_full => 0,
-      c_has_axi_aruser => 0,
-      c_has_axi_awuser => 0,
-      c_has_axi_buser => 0,
-      c_has_axi_rd_channel => 0,
-      c_has_axi_ruser => 0,
-      c_has_axi_wr_channel => 0,
-      c_has_axi_wuser => 0,
-      c_has_axis_tdata => 0,
-      c_has_axis_tdest => 0,
-      c_has_axis_tid => 0,
-      c_has_axis_tkeep => 0,
-      c_has_axis_tlast => 0,
-      c_has_axis_tready => 1,
-      c_has_axis_tstrb => 0,
-      c_has_axis_tuser => 0,
-      c_has_backup => 0,
-      c_has_data_count => 0,
-      c_has_data_counts_axis => 0,
-      c_has_data_counts_rach => 0,
-      c_has_data_counts_rdch => 0,
-      c_has_data_counts_wach => 0,
-      c_has_data_counts_wdch => 0,
-      c_has_data_counts_wrch => 0,
-      c_has_int_clk => 0,
-      c_has_master_ce => 0,
-      c_has_meminit_file => 0,
-      c_has_overflow => 0,
-      c_has_prog_flags_axis => 0,
-      c_has_prog_flags_rach => 0,
-      c_has_prog_flags_rdch => 0,
-      c_has_prog_flags_wach => 0,
-      c_has_prog_flags_wdch => 0,
-      c_has_prog_flags_wrch => 0,
-      c_has_rd_data_count => 0,
-      c_has_rd_rst => 0,
-      c_has_rst => 1,
-      c_has_slave_ce => 0,
-      c_has_srst => 0,
-      c_has_underflow => 0,
-      c_has_valid => 0,
-      c_has_wr_ack => 0,
-      c_has_wr_data_count => 0,
-      c_has_wr_rst => 0,
-      c_implementation_type => 2,
-      c_implementation_type_axis => 1,
-      c_implementation_type_rach => 1,
-      c_implementation_type_rdch => 1,
-      c_implementation_type_wach => 1,
-      c_implementation_type_wdch => 1,
-      c_implementation_type_wrch => 1,
-      c_init_wr_pntr_val => 0,
-      c_interface_type => 0,
-      c_memory_type => 1,
-      c_mif_file_name => "BlankString",
-      c_msgon_val => 1,
-      c_optimization_mode => 0,
-      c_overflow_low => 0,
-      c_preload_latency => 1,
-      c_preload_regs => 0,
-      c_prim_fifo_type => "512x36",
-      c_prog_empty_thresh_assert_val => 2,
-      c_prog_empty_thresh_assert_val_axis => 1022,
-      c_prog_empty_thresh_assert_val_rach => 1022,
-      c_prog_empty_thresh_assert_val_rdch => 1022,
-      c_prog_empty_thresh_assert_val_wach => 1022,
-      c_prog_empty_thresh_assert_val_wdch => 1022,
-      c_prog_empty_thresh_assert_val_wrch => 1022,
-      c_prog_empty_thresh_negate_val => 3,
-      c_prog_empty_type => 0,
-      c_prog_empty_type_axis => 0,
-      c_prog_empty_type_rach => 0,
-      c_prog_empty_type_rdch => 0,
-      c_prog_empty_type_wach => 0,
-      c_prog_empty_type_wdch => 0,
-      c_prog_empty_type_wrch => 0,
-      c_prog_full_thresh_assert_val => 13,
-      c_prog_full_thresh_assert_val_axis => 1023,
-      c_prog_full_thresh_assert_val_rach => 1023,
-      c_prog_full_thresh_assert_val_rdch => 1023,
-      c_prog_full_thresh_assert_val_wach => 1023,
-      c_prog_full_thresh_assert_val_wdch => 1023,
-      c_prog_full_thresh_assert_val_wrch => 1023,
-      c_prog_full_thresh_negate_val => 12,
-      c_prog_full_type => 0,
-      c_prog_full_type_axis => 0,
-      c_prog_full_type_rach => 0,
-      c_prog_full_type_rdch => 0,
-      c_prog_full_type_wach => 0,
-      c_prog_full_type_wdch => 0,
-      c_prog_full_type_wrch => 0,
-      c_rach_type => 0,
-      c_rd_data_count_width => 4,
-      c_rd_depth => 16,
-      c_rd_freq => 1,
-      c_rd_pntr_width => 4,
-      c_rdch_type => 0,
-      c_reg_slice_mode_axis => 0,
-      c_reg_slice_mode_rach => 0,
-      c_reg_slice_mode_rdch => 0,
-      c_reg_slice_mode_wach => 0,
-      c_reg_slice_mode_wdch => 0,
-      c_reg_slice_mode_wrch => 0,
-      c_synchronizer_stage => 2,
-      c_underflow_low => 0,
-      c_use_common_overflow => 0,
-      c_use_common_underflow => 0,
-      c_use_default_settings => 0,
-      c_use_dout_rst => 1,
-      c_use_ecc => 0,
-      c_use_ecc_axis => 0,
-      c_use_ecc_rach => 0,
-      c_use_ecc_rdch => 0,
-      c_use_ecc_wach => 0,
-      c_use_ecc_wdch => 0,
-      c_use_ecc_wrch => 0,
-      c_use_embedded_reg => 0,
-      c_use_fifo16_flags => 0,
-      c_use_fwft_data_count => 0,
-      c_valid_low => 0,
-      c_wach_type => 0,
-      c_wdch_type => 0,
-      c_wr_ack_low => 0,
-      c_wr_data_count_width => 4,
-      c_wr_depth => 16,
-      c_wr_depth_axis => 1024,
-      c_wr_depth_rach => 16,
-      c_wr_depth_rdch => 1024,
-      c_wr_depth_wach => 16,
-      c_wr_depth_wdch => 1024,
-      c_wr_depth_wrch => 16,
-      c_wr_freq => 1,
-      c_wr_pntr_width => 4,
-      c_wr_pntr_width_axis => 10,
-      c_wr_pntr_width_rach => 4,
-      c_wr_pntr_width_rdch => 10,
-      c_wr_pntr_width_wach => 4,
-      c_wr_pntr_width_wdch => 10,
-      c_wr_pntr_width_wrch => 4,
-      c_wr_response_latency => 1,
-      c_wrch_type => 0
-    );
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_async_fifo_16x9
-  PORT MAP (
-    rst => rst,
-    wr_clk => wr_clk,
-    rd_clk => rd_clk,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty
-  );
--- synthesis translate_on
-
-END async_fifo_16x9_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.vho b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.vho
deleted file mode 100644
index fa03d03..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.vho
+++ /dev/null
@@ -1,95 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
---    Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3   --
---                                                                            --
---    Rev 1. The FIFO Generator is a parameterizable first-in/first-out       --
---    memory queue generator. Use it to generate resource and performance     --
---    optimized FIFOs with common or independent read/write clock domains,    --
---    and optional fixed or programmable full and empty flags and             --
---    handshaking signals.  Choose from a selection of memory resource        --
---    types for implementation.  Optional Hamming code based error            --
---    detection and correction as well as error injection capability for      --
---    system test help to insure data integrity.  FIFO width and depth are    --
---    parameterizable, and for native interface FIFOs, asymmetric read and    --
---    write port widths are also supported.                                   --
---------------------------------------------------------------------------------
-
--- Interfaces:
---    AXI4Stream_MASTER_M_AXIS
---    AXI4Stream_SLAVE_S_AXIS
---    AXI4_MASTER_M_AXI
---    AXI4_SLAVE_S_AXI
---    AXI4Lite_MASTER_M_AXI
---    AXI4Lite_SLAVE_S_AXI
---    master_aclk
---    slave_aclk
---    slave_aresetn
-
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-COMPONENT async_fifo_16x9
-  PORT (
-    rst : IN STD_LOGIC;
-    wr_clk : IN STD_LOGIC;
-    rd_clk : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END COMPONENT;
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : async_fifo_16x9
-  PORT MAP (
-    rst => rst,
-    wr_clk => wr_clk,
-    rd_clk => rd_clk,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty
-  );
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file async_fifo_16x9.vhd when simulating
--- the core, async_fifo_16x9. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xco b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xco
deleted file mode 100644
index c361245..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xco
+++ /dev/null
@@ -1,213 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Thu Nov 27 10:27:02 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:fifo_generator:9.3
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=async_fifo_16x9
-CSET data_count=false
-CSET data_count_width=4
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=2
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=3
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=13
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=12
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=9
-CSET input_depth=16
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=9
-CSET output_depth=16
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=4
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET synchronization_stages=2
-CSET synchronization_stages_axi=2
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=4
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-11-19T12:39:56Z
-# END Extra information
-GENERATE
-# CRC: e70f47ef
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xise b/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xise
deleted file mode 100644
index 466e213..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_16x9.xise
+++ /dev/null
@@ -1,74 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="async_fifo_16x9.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="async_fifo_16x9.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|async_fifo_16x9|async_fifo_16x9_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="async_fifo_16x9.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/async_fifo_16x9" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="async_fifo_16x9" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-27T11:28:50" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5E9AED9EED564544B04AED8AD2D6A268" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.asy b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.asy
deleted file mode 100644
index bb91418..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.asy
+++ /dev/null
@@ -1,41 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 async_fifo_512x32
-RECTANGLE Normal 32 32 800 3680
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Normal 0 208 32 208
-PIN 0 208 LEFT 36
-PINATTR PinName wr_clk
-PINATTR Polarity IN
-LINE Wide 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName din[31:0]
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 464 32 464
-PIN 0 464 LEFT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Normal 832 240 800 240
-PIN 832 240 RIGHT 36
-PINATTR PinName rd_clk
-PINATTR Polarity IN
-LINE Wide 832 272 800 272
-PIN 832 272 RIGHT 36
-PINATTR PinName dout[31:0]
-PINATTR Polarity OUT
-LINE Normal 832 304 800 304
-PIN 832 304 RIGHT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 832 496 800 496
-PIN 832 496 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.gise b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.gise
deleted file mode 100644
index c15f6b8..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.gise
+++ /dev/null
@@ -1,54 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="async_fifo_512x32.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="async_fifo_512x32.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="async_fifo_512x32.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="async_fifo_512x32.vho" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_v8_3_readme.txt" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1343823802" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1343823802">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6081577449302675146" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6587804894567336138" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3493164220429793914" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.ngc b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.ngc
deleted file mode 100644
index 72932bd..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$2a040<,[o}e~g`n;"2*731&=$:,)<4-03840=789:;8=5?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>;;12;41=710::7<?n;069MKVR\3KOH_O]D@FGV974294:m6?;:HLSQQ<FLMXI[_OKDS>27?699=1::7GAPTV9@LGCA5;>6=0>4:35>LHW]]0OEOJF<0794;7238<1CXZ_UU8GKDBH48?1<3?:;049KPRW]]0OCOJ@<0794;7<:830>7GAPTV9EABUI]CNDDIG<083:4?<:3CE\XZ5AEFQFQOB@@MC0<4?>0686?OIX\^1HD^NDHR?5?699=196D@_UU8GMUDCAY6:6=0>5:09KPRW]]0OC]OKOQ>2>586=281CXZ_UU8GKUDCGY6:6=0>2:11>LHW]]0oec2<1;2=51=4:3E^X][[:emvp95629437>=?221341=3918:<6:5IORVP?QBI591<3?46395=1=110<:<68697;52<?1>0<25;??;7CBEDGFIHKJMLONAg95ri~6;9~mj96;-2683C@A<22?><?=;98JJUSS2^OI[H28:1<2?<2<19:2>6798:;52<0>1?;;748997;:23?>>0<=5?5N659BE3G?3HKJM;ONA028EDGFIHKJ:LONA@CB55=FIHKJMLONA@C5EDGb3HNO^L\KAEFQ858a3HNO^L\KAEFQ8469n2KOH_O]D@FGV9766o1JHI\NRECG@W:6:7;:7LJKR@PGEABU4891<3h4AEFQEWBFLMX7=>0j;@FGVDTCIMNY0<0j;@FGVDTCIMNY0?0j;@FGVDTCIMNY0>0j;@FGVDTCIMNY090j;@FGVDTCIMNY080j;@FGVDTCIMNY0;0j;@FGVDTCIMNY0:0j;@FGVDTCIMNY050j;@FGVDTCIMNY040i;@FGVDRNMACLD1>1109B@ATF\@OCEJF31;2=b>GCL[K_EHFFGI>2:c=FLMXIXDKGIFJ?4;763HNO^OZFEIKDL97=87l0MIJ]BUKFLLAO484n7LJKRCUQEABU494m7LJKRCUQEABU48:5j6OKDS@TVDBCZ5;:2k5NDEPASWGCL[6:>3?>;@FGVGQUIMNY0<=50?d8EABUJ^XJHI\312<f?DBCZK]YMIJ]<0<f?DBCZK]YMIJ]<3<f?DBCZK]YMIJ]<2<f?DBCZK]YMIJ]<5<f?DBCZK]YMIJ]<4<f?DBCZK]YMIJ]<7<f?DBCZK]YMIJ]<6<f?DBCZK]YMIJ]<9<f?DBCZK]YMIJ]<8<0?DJK12KXUCMPRDE;?GSTW@DMC<5L2:AF57=D@LI@SAGLEOQF[Q_WM;1HE95LLJ25?FJL91:=7NBD2626?FJL:Q20OAE=X0:31>EKC0:>7NBDA058GIMF9M8<7NBDA0F73>EKCH;O445LLJCQ@FJL=2IGGO?6;BNHFRTDDB?0OAEL149@HNB6=2IGGIXl;BNH@SYCA_COI85LLJD[<>EKCOR:4==4CMP:?FIJE@^_II?;;BMQAZABFLXJXDAA_HLEK2=DZLK_II?4De9GAIG^MMU\^DZJ2:FJ<>BNIMC7<374DHCGM977601OELJF<03==>BNIMC7=?06;EKB@L:6;730HDOKI=37:g=CAHNB0<;50?;8@LGCA5;>255KI@FJ848?3MCJHD2=>99GMDBN4:437IGNDH>7:==CAHNB0807;EKB@L:1611OELJF<6<;?AOFL@63255KI@FJ8<8?3MCIHD2?>89GMGBN48:556JFBEK?548>3MCIHD2>2?;8@LDCA5;8245KICFJ8429j2NBNIG31483:<=CAKNB0<;18:FJFAO;9720HDLKI=0=<>BNJMC7?364DH@GM92902NBNIG35?:8@LDCA5<546JFBEK?3;><L@HOE1618:FJFAO;17k0HD^NDHR?4;e<L@ZJHD^31;2=e>BNXHNB\1?1a:FJTGBNX5:5o6JFPCFJT97=87k0HD^MDHR?5;><LFKOC1>19:FLEAI;99427IANDN>25;?<LFKOC1?=>89GKDBH489556J@AEM?518e3MEJHB2>5;2==>BHIME7=807;EMB@J:6611OCLJ@<3<;?AIFLF68255KO@FL818?3MEJHB2:>99GKDBH4?437IANDN>4:==CGHND0507;EMB@J:>6>1OCLQ]EF:8@JDCG5:556J@BEM?558>3MEIHB2>1?;8@JDCG5;9245KOCFL845912NDNIA315<a?AIELF6:97>19:FLFAI;9<437IAMDN>2:==CGKND0?07;EMA@J:4611OCOJ@<5<;?AIELF6>255KOCFL838?3MEIHB28>99GKGBH41437IAMDN>::2=CGKUYIJo4DNRB@JV;87i0HB^NDNR?5?69i2ND\LJ@P=3=e>BHXKND\1>1c:FLTGBHX5;1<3o4DNRA@JV;9780I994EOCQ@@H03LDI[_KA4:D1B54<N>?0JLB\E39E@6=ALJ>0JIMJ3:DGT1=ALYO:7J=4GOF2?L4<A980E<<4I308M64<A=80E864IOKWTZ6702CEEY^P00:8MKOSXV:946GAIUR\46><AGC_\R>;8:KMMQVX8<20ECG[P^25<>OIA]ZT<:74IOKWWQGSM>1BBDZP0158MKOSW9;<7D@FT^213>OIA]U;?:5FNHV\411<AGC_S=;8;HLJPZ61?2CEEYQ?769JJLRX81=0ECG[_1;4?LHN\V:J;6GAIU]3F2=NF@^T<N94IOKW[5B03@DBXR>J7:KMMQY7N>1BBDZP1158MKOSW8;<7D@FT^313>OIA]U:?:5FNHV\511<AGC_S<;8;HLJPZ71?2CEEYQ>769JJLRX91=0ECG[_0;4?LHN\V;J;6GAIU]2F2=NF@^T=N94IOKW[4B03@DBXR?J7:KMMQY6N>1BBDZP2158MKOSW;;<7D@FT^013>OIA]U9?:5FNHV\611<AGC_S?;8;HLJPZ41?2CEEYQ=769JJLRX:1=0ECG[_3;4?LHN\V8J;6GAIU]1F2=NF@^T>N94IOKW[7B03@DBXR<J7:KMMQY5N>1BBDZP3158MKOSW:;<7D@FT^113>OIA]U8?:5FNHV\711<AGC_S>;8;HLJPZ51?2CEEYQ<769JJLRX;1=0ECG[_2;4?LHN\V9J;6GAIU]0F2=NF@^T?N94IOKW[6B03@DBXR=J7:KMMQY4N?1BBDZPA79JJLRXJ01BBDZPFHNF7>OI^?1GCLJJD79OKFMBL>1GCJGLAM68HPR5<2F^X>:4LTV70>JR\<>0@XZ95:OPCJH23D_SOTm4M`hlvScu{`eeo6CfnnpUawungg80B=<4N018J4643G;??6@>629M5=1<FL^\C_E;;OMMA4=H02E%;;vk_M38T1=WI[^j7]GA_CWPMA^e3YCESO[\N@OF=>VLWAF^XCC<;QPF2>VTLFDN=6_7;SCNF4>B911YM@QBOEG2=>TCIMNYSNACLHQJKKYO_JEEJDIl;SGB@ZQNL]BTMn5]E@F\SLBS@VH>7_KHCD`8V@ADMHXNKNK9;SGDG@Dc3[OLOAENREP@HN1<ZLMH@FLk;SQWVDKFZZ^YM@94RRVQEHDc3[Y_^HINRRVQAB1<ZZ^YIJL>1:PPPWC@WYXBC_G[Y^C25>TT\[OLS]\FOSKW]ZD63Z20_LXJD@VB7>UCX8;0_E\JG^G[PWGD\VDLOh5\HSGD[HOIWZCQI<=4SHO\GJJKAZCDBRMGEBIb?VOJWMO]ENK7;RIJTZVNF?1XCX\LE69PVSGKWH=0__XNL^@5?VRF\\Y?7Y\ZE59W]UC1n2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!Bxnp\VAYWF]XP<PQ]D^RMPW]6UVRD^R;=_n]{k9699?l0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/LzlvZTCWYD_^V?R_SF\TKRUS;WTTB\P50]l[}i;87;=j6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-N|jtXZMU[BY\T2\]Q@ZVI\[Q8QRV@R^73[jYg5:5=;h4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+H~hzVXOS]@[RZ1^[WBXXG^YW9SPXNP\0<YhWqe7<3?9f:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})JpfxT^IQ_NUPX0XYULVZEX_U:]^ZLVZ2?WfUsc1>117d8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'Drd~R\K_QLWV^3ZW[NT\CZ][7_\\JTX<>UdSua30?35b>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%Ftb|PRE]SJQT\>TUYHR^ATSY4YZ^HZV>=SbQwo=2=53`<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#@v`r^PG[UHSZR=VS_JPPOVQ_=[XPFXT88Q`_ym?4;71m2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!Bxnp\SWYWF]XP<PQXR^RMPW]6UVRD^R6Po^zl8586>l1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv Mymq[RTXXG^YW<SPWS]SJQT\:TUSC_Q8_n]{k9699?o0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/LzlvZQUWYD_^V<R_VP\TKRUS:WTTB\P6^m\|j:768<n7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.O{kwYPZVZEX_U<]^UQ[UHSZR>VSUA]_4]l[}i;87;=i6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-N|jtX_[U[BY\T4\]TVZVI\[Q>QRV@R^6\kZ~h494::h5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,I}iuW^XT\CZ][4_\SWYWF]XP:PQWOS]0[jYg5:5=;k4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+H~hzV]YS]@[RZ4^[RTXXG^YW:SPXNP\6ZiXpf6;2<8j;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*Kg{U\^R^ATSY4YZQUWYD_^V6R_YMQ[4YhWqe7<3?93:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})ULVZEX_U?]^PG[UHSZR;VSUA]_40\k35<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#_JPPOVQ_4[XZMU[BY\T2\][KWY29Ve=?6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-Q@ZVI\[Q9QR\K_QLWV^5ZWQEYS8>Po718Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'[NT\CZ][2_\VAYWF]XP8PQWOS]7=Zi1;2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!]D^RMPW]3UVXOS]@[RZ7^[]IUW=2Tc;=4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+WBXXG^YW8SPRE]SJQT\>TUSC_Q;7^m57>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%YHR^ATSY5YZTCWYD_^V9R_YMQ[10Xg?90Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/SF\TKRUS>WT^IQ_NUPX<XY_G[U?9Ra92:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})PZVZEX_U?]^UQ[UHSZR;VSUA]_9]l27=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$[_Q_NUPX5XYPZVZEX_U=]^ZLVZ1Xg?80Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/VP\TKRUS;WT[_Q_NUPX7XY_G[U=Sb8=;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*QUWYD_^V=R_VP\TKRUS=WTTB\P5^m56>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%\^R^ATSY7YZQUWYD_^V;R_YMQ[1Yh>;1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv WS]SJQT\=TU\^R^ATSY5YZ^HZV9Tc;<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+RTXXG^YW;SPWS]SJQT\?TUSC_Q=_n41?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&]YS]@[RZ5^[RTXXG^YW5SPXNP\5Zi2;2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwYeag6;28=4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+wbXxg~ySoga<0<67>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%yhR~ats]amk:56<90Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/sf\tkruWkce0>0:3:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})ulVzexQmio>7:05<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#jPpovq[goi4<4>?6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-q`Zvi|{Uiec29>418Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'{nT|cz}_ckm8282;2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwYeag6328<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+wbXxg~ySoga_171?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&xoS}`{r^`jjZ72:2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwYeagU99?5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,vaYwf}xTnd`P3408Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'{nT|cz}_ckm[1353\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"|k_qlwvZdnfV?>>6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-q`Zvi|{UiecQ9539V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~(zmU{by|Pbhl\304<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#jPpovq[goiW1?97X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.pg[uhszVmh0=0:2:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})ulVzexQhc=3=17=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$~iQnup\cf:56<80Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/sf\tkruWni7?3;=;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*tcWyd~Ril<5<66>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%yhR~ats]dg939=;1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXoj6=28<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+wbXxg~ySjm37?71?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&xoS}`{r^e`8=8292_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwY`kV:>=6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-q`Zvi|{UloR?:1:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})ulVzexQhc^065>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%yhR~ats]dgZ5292_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwY`kV>>=6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-q`Zvi|{UloR;:1:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})ulVzexQhc^465>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%yhR~ats]dgZ1292_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwY`kV2>46[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-q`Zvi|{UloRo|rde?4;3?3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"|k_qlwvZadWhyyij2>>4:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'{nT|cz}_fa\evtbo585955Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,vaYwf}xTknQnssgd868202_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwY`kVkx~hi34?7;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&xoS}`{r^e`[duumn6>2864U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+wbXxg~ySjmParpfc909=11^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh<6<6<>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%yhR~ats]dgZgtzlm743;8;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*tcWyd~Ril_`qqabY7=>1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_074?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&xoS}`{r^e`[duumnU99:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,vaYwf}xTknQnssgd[6303\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"|k_qlwvZadWhyyijQ;569V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~(zmU{by|Pgb]bwwc`W<?<7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.pg[uhszVmhSl}}ef]512=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$~iQnup\cfYf{{olS:;8;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*tcWyd~Ril_`qqabY?=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp969=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp979=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp949=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp959=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp929=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp939=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp909=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp919=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp9>9>m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp^>ZW{ooynkPxnp\53Yh>l1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv re]sjqtXojUjkh_mcpp^>ZW{ooynkPxnp\53Yh9?n0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/sf\tkruWniTm~|jg^nbwq]?UVxnhxmj_ymq[41Xg?o0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/sf\tkruWniTm~|jg^nbwq]?UVxnhxmj_ymq[41Xg8=87X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.pg[uhszVmhSl}}ef]oevr\0TUyii{le^zlvZ7?9Vrd0=0>6e9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~(zmU{by|Pgb]bwwc`WekxxV6R_sggqfcXpfxT=5Q`729V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~(zmU{by|Pgb]bwwc`WekxxV6R_sggqfcXpfxT=4?Pxn>3:40c3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"|k_qlwvZadWhyyijQcarvX<XYummhiRv`r^3:[j143\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"|k_qlwvZadWhyyijQcarvX<XYummhiRv`r^035Z~h494::i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,vaYwf}xTknQnssgd[igt|R2VSkkubg\|jtX:9Ud;?5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,vaYwf}xTknQnssgd[igt|R2VSkkubg\|jtX:8;Ttb2?>7f8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'{nT|cz}_fa\evtboVfjyU7]^pf`pebWqeyS??Po608Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'{nT|cz}_fa\evtboVfjyU7]^pf`pebWqeyS?<>_ym?4;113\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"|k_qlwvZadWhyyijQcarvX<XYummhiRv`r^015Z~h494T_Z>9d:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})ulVzexQhc^cpv`aXdhyW5SPrdfvg`Yg{U9>Ra82:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})ulVzexQhc^cpv`aXdhyW5SPrdfvg`Yg{U9?<Qwo=2=2a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$~iQnup\cfYf{{olSao|tZ:^[wcc}joTtb|P22]l1f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$~iQnup\cfYf{{olSao|t^26g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%yhR~ats]dgZgtzlmT`l}{_07`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&xoS}`{r^e`[duumnUgm~zP24a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'{nT|cz}_fa\evtboVfjyQ<5b9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~(zmU{by|Pgb]bwwc`WekxxR::c:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})ulVzexQhc^cpv`aXdhyS8;l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*tcWyd~Ril_`qqabYkiz~T:8m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+wbXxg~ySjmParpfcZjf{}U<9n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,vaYwf}xTknQnssgd[igt|V2>?6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{Uiec2?>418Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'~xT|cz}_ckm8482;2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!xr^rmpwYeag6928=4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+rtXxg~ySoga<2<67>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%|~R~ats]amk:36<90Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/vp\tkruWkce080:3:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})pzVzexQmio>5:05<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#z|Ppovq[goi4>4>?6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{Uiec27>408Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'~xT|cz}_ckm[5353\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"y}_qlwvZdnfV;>>6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{UiecQ=539V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~({U{by|Pbhl\704<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#z|Ppovq[goiW=?97X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.uq[uhszVhbbR;:2:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})pzVzexQmio]517=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr${Qnup\flhX?<80Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/vp\tkruWkceS5;=;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*quWyd~Ril<1<66>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%|~R~ats]dg979=;1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv ws]sjqtXoj6928<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+rtXxg~ySjm33?71?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&}yS}`{r^e`8182:2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!xr^rmpwY`k5?59?5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTkn29>408Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'~xT|cz}_fa?3;353\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"y}_qlwvZad414>=6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{UloR>:1:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})pzVzexQhc^365>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%|~R~ats]dgZ4292_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!xr^rmpwY`kV9>=6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{UloR::1:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})pzVzexQhc^765>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/e`|+ekcq%|~R~ats]dgZ0292_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!xr^rmpwY`kV=>=6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{UloR6:8:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})pzVzexQhc^cpv`a;87?37X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.uq[uhszVmhSl}}ef>2:0><]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#z|Ppovq[beXizxnk1<1599V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~({U{by|Pgb]bwwc`4:4>46[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{UloRo|rde?0;3?3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"y}_qlwvZadWhyyij2:>4:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'~xT|cz}_fa\evtbo5<5955Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd828202_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!xr^rmpwY`kVkx~hi38?74?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&}yS}`{r^e`[duumnU;9:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[4303\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"y}_qlwvZadWhyyijQ=569V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hcy,`hn~({U{by|Pgb]bwwc`W:?<7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.uq[uhszVmhSl}}ef]712=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr${Qnup\cfYf{{olS8;8;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*quWyd~Ril_`qqabY1=>1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv ws]sjqtXojUjkh_674?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&}yS}`{r^e`[duumnU39i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|5:59i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|5;59i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|5859i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|5959i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|5>59i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|5?59i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|5<59i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|5=59i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|525;?5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|R2VSkkubg\|jtX99;Ttb2?>648Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'~xT|cz}_fa\evtboVfjyU7]^pf`pebWqeyS<>>_ym?4;YT_9<o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.uq[uhszVmhSl}}ef]oevr\0TUyii{le^zlvZ77Wf=97X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.uq[uhszVmhSl}}ef]oevr\0TUyii{le^zlvZ769Vrd0=09d:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})pzVzexQhc^cpv`aXdhyW5SPrdfvg`Yg{U:=Ra9c:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ilx/aoo})pzVzexQhc^cpv`aXdhyW5SPrdfvg`Yg{U?Sb8k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*quWyd~Ril_`qqabYkiz~P4PQ}eew`aZ~hzV>Tc<8l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*quWyd~Ril_`qqabYkiz~P4PQ}eew`aZ~hzV?Tc;j4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+rtXxg~ySjmParpfcZjf{}Q3QR|jdtaf[}iuW<Ud=:<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+rtXxg~ySjmParpfcZjf{}Q3QR|jdtaf[}iuW?;Ttb2?>04`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fa{*fjlp&}yS}`{r^e`[duumnUgm~zT8\]qaasdmVrd~R8Po608Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gbz-gim'~xT|cz}_fa\evtboVfjyU7]^pf`pebWqeyS:?Pxn>3:40d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"y}_qlwvZadWhyyijQcarvX<XYummhiRv`r^5\k24<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#z|Ppovq[beXizxnkRbnsuY;YZtbl|inSua}_93\|j:768<h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.uq[uhszVmhSl}}ef]oevr\0TUyii{le^zlvZ>Xg>;0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/vp\tkruWniTm~|jg^nbwq]?UVxnhxmj_ymq[<7Xpf6;2;m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+rtXxg~ySjmParpfcZjf{}Q3QR|jdtaf[}iuW0Ud9n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,swYwf}xTknQnssgd[igt|V:>o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{UloRo|rde\hdusW8?h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.uq[uhszVmhSl}}ef]oevrX:<i0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)ojr%oaew/vp\tkruWniTm~|jg^nbwqY4=j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`kq$h`fv ws]sjqtXojUjkh_mcppZ22k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!xr^rmpwY`kVkx~hiPl`qw[03d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*be&jf`t"y}_qlwvZadWhyyijQcarv\20e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-cf~)keas#z|Ppovq[beXizxnkRbnsu]41f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr${Qnup\cfYf{{olSao|t^:54>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxj#||tr-`4*aj}q$hm|vndv?4;073\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$ko|.sqww*e7'ng~t#mnrs{maq:66?:0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hr`q-vvrt'j:$k`{w.bcqv|hb|585:=5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqev(u{}y$o=!hmtz-gdtuqgo0>091:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btf{'xxx~!l0.enq}(`eR:V"jc>.l355>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxj#||tr-`4*aj}q$laV?R.fop*hu192_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j|ns/pppv)d8&mfyu hmZ0^*bkt&dy==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fpbw+tt|z%h<"ibuy,di^5Z&ngx"`}91:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btf{'xxx~!l0.enq}(`eR>V"jc|.lq61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxj#||tr-`4*p6494>:6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fpbw+tt|z%h<"x><1<210=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&mym~ }suq,g5)q95;59;5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqev(u{}y$o=!y1=3=503<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~l}!rrvp+f6(~8692884U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvdu)zz~x#n> v0>1:4323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$ko|.sqww*e7';7?3;9;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwgt&{y"m?/w3?7;72=2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j|ns/pppv)d8&|:090:6:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btf{'xxx~!l0.t28186>91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}ar,qwqu(k8%laxv!c`pq}kcs494=<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fpbw+tt|z%h="ibuy,`ewt~fl~7=38?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwgt&{y"m>/fov|+efz{seiy2=>728Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zhy%~~z|/b3,chs&jky~t`jt=1=24=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&mym~ }suq,g4)`e|r%k`U?]/en5+k6>81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}ar,qwqu(k8%laxv!glY2Y+aj{'gx:<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqev(u{}y$o<!hmtz-ch]5U'mf#c|609V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*auiz$yy} c0-dip~)odQ8Q#ibs/op24=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&mym~ }suq,g4)`e|r%k`U;]/enw+kt=<1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}ar,qwqu(k8%}=1>1579V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*auiz$yy} c0-u59699<?0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hr`q-vvrt'j;$z<2>>448Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zhy%~~z|/b3,r4:668?>7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gscp*wus{&i:#{?32?75?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{kx"}{s.a2+s7;:7;>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fpbw+tt|z%h="x><2<62>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxj#||tr-`5*p64:4:985Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqev(u{}y$o<!y1=6=13=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&mym~ }suq,g4)q95>5=8<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvdu)zz~x#nabp17e?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{kx"}{s.aliu6Xkfg{=RA]_7]l25=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&mym~ }suq,gjkw8Vida}?POS]5[j72:2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j|ns/pppv)dgdz:9o5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqev(u{}y$~lcPelrw}Z`eW`?37X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gscp*wus{&xjaRkbpu{\m1`<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%ym`Q}d^gm[l72;2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#jPpovq[ujr{86;2:>4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'Dg~tRil0/alqkr\0TULBIQ=16]l[hsW;UDYY<>719V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$A`{w_fa3*firf}Q3QRIAD^023ZiXe|rT>RAZT2361>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphs484>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{<3<61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphs4:4>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{<5<61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphs4<4>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{<7<61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphs4>4>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{<9<5g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsS1WTKCJP205\kZkrpV8TCXZ31?4`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkr\0TULBIQ=16]l[hsW;UDYY2=>7a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjq]?UVMEHR<>7^m\ip~X:VE^X1=16d9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmp^>ZWNDOS??8_n]nq}Y5WF__0>0>17f8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjq]?UVMEHR<>7^m\ip~X:VE^X1=12638Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjq]?UVMEHR<>7^m\ip~X:VE^X1=1_cfg43e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}Q3QRIAD^023ZiXe|rT>RAZT=6=2a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|R2VSJ@K_334[jYj}qU9SB[[<5<22f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|R2VSJ@K_334[jYj}qU9SB[[<4<5`>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsS1WTKCJP205\kZkrpV8TCXZ35?35g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsS1WTKCJP205\kZkrpV8TCXZ36?4g?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkr\0TULBIQ=16]l[hsW;UDYY29>04`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkr\0TULBIQ=16]l[hsW;UDYY28>7f8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjq]?UVMEHR<>7^m\ip~X:VE^X19117a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjq]?UVMEHR<>7^m\ip~X:VE^X161719V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmp^>ZWNDOS??8_n]nq}Y5WF__050PSV360>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsW8??7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*ad8'idyczP2468Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjqY4==1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexR::4:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw[0333\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~T:8:4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu]411=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|V2>46[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{_e3?4;3?3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~Th<2>>4:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjqYc9585955Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{at^f2868202_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-dg5(dg|dSi?34?7;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkrXl86>2864U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu]g5909=11^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexRj><6<6<>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsWm;743;8;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\`4Y7=>1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexRj>_074?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkrXl8U99:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{at^f2[6303\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~Th<Q;569V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmpZb6W<?<7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*ad8'idyczPd0]512=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|Vn:S:;8;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\`4Y?>j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixar,twqu(EdsSnabp0]DJAY5;9UdS@[W_06\k47182_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jyns/uppv)d9&mfyu laspzj`r;87<;7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvcp*rus{&i:#jczx/abvwim}6:2;>4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsdu)z~x#n? glw{*fguzpdnx1<1619V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*apiz$|y} c0-dip~)khxyuck{<2<55>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}j#y|tr-`5*aj}q$laV>R.fo2*h7192_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jyns/uppv)d9&mfyu hmZ3^*bkt&dy==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fubw+qt|z%h="ibuy,di^4Z&ngx"`}91:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqf{'}xx~!l1.enq}(`eR9V"jc|.lq55>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}j#y|tr-`5*aj}q$laV:R.fop*hu2=2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jyns/uppv)d9&|:0=0:6:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqf{'}xx~!l1.t28586=<1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixar,twqu(k8%}=1?1579V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*apiz$|y} c0-u59799<?0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hw`q-svrt'j;$z<2=>448Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`hy%{~z|/b3,r4:568?>7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvcp*rus{&i:#{?33?75?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~kx"z}{s.a2+s7;;7;>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fubw+qt|z%h="x><5<62>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}j#y|tr-`5*p64=4::=5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etev(p{}y$o?!hmtz-gdtuqgo0=090:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqf{'}xx~!l2.enq}(di{xrbhz31?43?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~kx"z}{s.a1+bkrp'ij~waeu>1:36<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{l}!wrvp+f4(ods"no}rxlfp959>81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixar,twqu(k;%laxv!glY3Y+aj9'g::<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etev(p{}y$o?!hmtz-ch]6U'mf#c|609V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*apiz$|y} c3-dip~)odQ9Q#ibs/op24=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|m~ xsuq,g7)`e|r%k`U<]/enw+kt>81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixar,twqu(k;%laxv!glY7Y+aj{'gx985Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etev(p{}y$o?!y1=2=13=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|m~ xsuq,g7)q95:5=8;4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsdu)z~x#n< v0>2:00<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{l}!wrvp+f4(~86:2<;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crgt&~y"m=/w3?6;313\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kzo|.vqww*e5';7>3?:5:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqf{'}xx~!l2.t28682>2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jyns/uppv)d:&|:0>0>549V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*apiz$|y} c3-u5929=?1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixar,twqu(k;%}=1:11408Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`hy%{~z|/bmnt4023\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kzo|.vqww*ehey;TKCJP222\kZKRPV;?Sb;=;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crgt&~y"m`mq06e>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}j#y|tr-qehYa}efTjoQf569V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*apiz$|y} r`o\bpjkW`>m7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| r`o\swYbfVc:;85Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(EdsSjgl0/e`4+eh}g~P4PQHNE]16=YhWdsS?Q@UU0230=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| Mlw{[bod8'mh<#m`uovX<XY@FMU9>5Q`_lw{[7YH]]9:9l5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(o`i;"jm?.bmvjq:66<k0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!xpovq+bod8'mh<#m`uov?6;3f3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.ejg5(`k9$hcx`{<2<6e>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!hib2-cf6)kfex1:15`9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$kdm?.fa3*firf}6>28o4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'nch<#il0/alqkr;>7?j7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*ank9$lo= lotlw8282i2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dmf6)oj:%ob{at=:=34=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byU7]^EM@Z450VeTaxvP2^MVP979?81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cle7&ni;"naznuY;YZAILV894RaPmtz\6ZIR\585;<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(o`i;"jm?.bmvjq]?UVMEHR<=8^m\ip~X:VE^X1=1729V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$kdm?.fa3*firf}Q3QRIAD^01<ZiXe|rT>RAZT=1=54153\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.ejg5(`k9$hcx`{[9_\CKBX:;2TcRczx^0\KPR;;78<:6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmp^>ZWNDOS?<7_n]nq}Y5WF__0>0Pbef334=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byU7]^EM@Z450VeTaxvP2^MVP929?;1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cle7&ni;"naznuY;YZAILV894RaPmtz\6ZIR\5>5=:?4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'nch<#il0/alqkr\0TULBIQ=29]l[hsW;UDYY2:>608Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pxg~y#jgl0/e`4+eh}g~P4PQHNE]16=YhWdsS?Q@UU>6:4163\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.ejg5(`k9$hcx`{[9_\CKBX:;2TcRczx^0\KPR;>7=97X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*ank9$lo= lotlw_=[XOGNT>?6Po^ov|Z4XG\^7:3?81:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rvi|{%len>!gb2-gjsi|R2VSJ@K_30;[jYj}qU9SB[[<6<46>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!hib2-cf6)kfexV6R_FLG[74?WfUfyuQ=_NWW8286?81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cle7&ni;"naznuY;YZAILV894RaPmtz\6ZIR\525;85Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(o`i;"jm?.bmvjq]?UVMEHR<=8^m\ip~X:VE^X161_RU21<=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQ>589V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$kdm?.fa3*firf}U9945Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(o`i;"jm?.bmvjqY4=01^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cle7&ni;"naznu]71<=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQ:589V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$kdm?.fa3*firf}U=945Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(o`i;"jm?.bmvjqY0=01^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cle7&ni;"naznu];1a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQk1=2=1a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQk1=3=1a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQk1=0=1a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQk1=1=1a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQk1=6=1a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQk1=7=1a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQk1=4=1a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQk1=5=1a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQk1=:=1f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gha3*be7&je~byQk1^26g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!hib2-cf6)kfexRj>_07`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ifc1,dg5(dg|dSi?P24a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pxg~y#jgl0/e`4+eh}g~Th<Q<5b9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$kdm?.fa3*firf}Uo=R::c:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rvi|{%len>!gb2-gjsi|Vn:S8;l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mbo= hc1,`kphsWm;T:8m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'nch<#il0/alqkrXl8U<9n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(o`i;"jm?.bmvjqYc9V2>h6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb54;4>h6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb54:4>h6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb54=4>h6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb54<4>h6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb54?4>h6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb54>4>h6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb5414>o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`aj:%kn>!cnwmpZb5W;?h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*ank9$lo= lotlw[a4X;<i0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!xpovq+bod8'mh<#m`uov\`7Y3=j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cle7&ni;"naznu]g6Z32k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dmf6)oj:%ob{at^f1[33d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.ejg5(`k9$hcx`{_e0\30e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%||cz}/fk`4+ad8'idyczPd3];12=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}yS}`{r^roqv7;87Ubb{;j;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,swYwf}xT|a{|1=2=[lhq9VCEZR>:7:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rtXxg~yS}bzs3>2:Zoi~<o0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!xr^rmpwYwd|y90<0Piot2[LHQW9h?7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&dof#jlb.f`nc+aeenk%bjklc/`nc*aii}c}ioch.ocwmscXjeaTahcPgdl,rdjnl'ixx!}alnlku]7U'xja#| v7]mklhn|'xja"]KP/UJ@@YWZ@G:4#|nmcg8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,cgk)okgl"jlbg`,mc`ed&kgl#j`nthtffha)fh~bzhQmlj]nahY`mg%}magk.bqwv*tfeeed|V>R.scn*w)q>Vddecg{.scn+VBW&^COIR^]IL3;*wgjW`dxyao{e16g?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.lgn+qkwW{kfSjPeo6f?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.lgn+qkwW{kfSjPeo307>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h r`o\vaYbf:90Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*tfeV}ySh`<f:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$~iQnup?4;Ynf;TECXP02f8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+WUSWO_G@RIJN5:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+btt|m;%k}{_gwoh+tt|Vn:855Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae gsqw`4(`zz~Tjxbc.sqw[a4302_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%l~~zk1/eqwqYa}ef%~~zPd26`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!}su`oo*h`{nyy hrrv-vaYu{}Uyij2?>5a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+kapzmxxx#i}su,q`Ztt|Vxnk1?14b9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#}{bmi,jbqul{y"j||t/pg[wusW{ol0?0;b:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$~~zmlj-mcrtczz~%k}{.sf\vvrXzlmT<9l4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&xxxobd/oetvatt|'myy }d^pppZtboV;?n6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!agvpgvvr)o{y"jPrrv\v`aX:=i0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*tt|kf`#cixreppp+au{}$|~R||t^pfc969<j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wusjea$bjy}dsqw*btt|'}yS}{_sgd8483j2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%ekz|krrv-cwus&~xT~~zPrde\41d<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'gm|~i||t/eqwq(pzVxxxR|jg^30`>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h rrvahn)ulVxxxRo|rde74>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h rrvahn)ulVxxxRo|rde\`4273\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&xoS}{_`qqabYc::i0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*tt|kf`#jPrrv\gjke;m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wusjea$~iQ}su]`khd6;m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wusjea${Q}su]bwwc`<91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wusjea${Q}su]bwwc`Wm;?<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!xr^pppZgtzlmTh?:;;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%yylck.uq[wusWhyyijQ}surlp6e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'~xT~~zPcnoa7a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim({UyyQlol`2g>STM[U]E^GMLD18RFE>3_CN[RZVPD58RLTSMQ<=7ZKN<1<5?RCF484=7ZKN<3<;?RCF4:0;2;5XE@>0:==PMK]N0=07;VGAS@:6611\IOYJ<3<;?RCE_L68255XECUF818?3^OI[H2:>99TAGQB4?4j7ZKMWD>4>58?3^OI[H28>c9TVLRBWOCY_Ym4WSKWAZKHLLUJo6Y]IUG\IJBBWKn0[_G[E^UJ@QNXIm1\^DZJ_VKGPMYE9m1SEAGAX,ZGF%6)9)Y_YO.?.0"BWFON>2RXXAGM7:ZPPZAIL>1S_YQYCB`8\ZEHZLUBBKA9;Yfa[Lba3QncS]|fmWgqwlii991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc=4Xrv0?\ct091TSRVCNL]\[5YXW\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.ejg5(`k9$hcx`{[9_\CKBX:;2TcRczx^0\KPR;;78<i6QP_YNMIZYX99UTSX> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nis"nbdx.O{kwYULVZEX_U>]^PG[UHSZR8VSUA]_43\kZ~h494:;h5P_^ZOJHYXW8;TSR[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-N|jtXZMU[BY\T3\]Q@ZVI\[Q?QRV@R^6:[jYg5:5=:k4_^][HKKXWV;9SRQZ0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$lou lljz,I}iuW[NT\CZ][4_\VAYWF]XP:PQWOS]73ZiXpf6;2<9k;^]\\IHJWVU:?RQPU1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+H~hzV]YS]@[RZ2^[RTXXG^YW<SPXNP\<ZiXpf6;2<6;;^]\\IHJWVU:8RQPU1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'Dg~tRifc1,dg5(dg|dW5SPGOF\67>XgVg~tR<POTV152b<WVUS@CCP_^36[ZYR8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$Aua}_VP\TKRUS>WT[_Q_NUPX<XY_G[U:SbQwo=2=52b<WVUS@CCP_^35[ZYR8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$Aua}_VP\TKRUS:WT[_Q_NUPX0XY_G[U>SbQwo=2=52b<WVUS@CCP_^34[ZYR8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dg}(ddbr$Aua}_VP\TKRUS<WT[_Q_NUPX2XY_G[U8SbQwo=2=51e<WVUS@CCP_^3;[ZYR8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim({UyyQlol`23g=XWVRGB@QP_0]\[P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkr\0TULBIQ=16]l[hsW;UDYY2<>3:0?ZYXPEDFSRQ=_^]V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$A`{w_fk`4+ad8'idyczT8\]DJAY5:1UdS`{w_3]LQQ56?l1TSRVCNL]\[6YXW\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.Onq}Y`k9$hcx`{[9_\CKBX:8=TcRczx^0\KPR491;0SRQWLOO\[Z2XWV_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+adp'iggu!}d^rmpwY`kVkx~hiPl`qw_=[Xzln~ohQwos]2<4Yg5:5=5>4_^][HKKXWV?TSR[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-tvZvi|{UloRo|rde\hdusS1WT~hjzcd]{kwY19Vrd0=0>7b9\[Z^KFDUTS;QP_T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jmw.bnh|*tcWyd~Ril_`qqabYkiz~P4PQ}eew`aZ~hzV;=Sb?8b:]\[]JIEVUT;RQPU1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%knv!cmi{+rtXxg~ySjmParpfcZjf{}Q3QR|jdtaf[}iuW<Ud=8j4_^][HKKXWV2TSR[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/scn[wbXmgUb=:j4_^][HKKXWV3TSR[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mht#mcky-N|jtXZMU[BY\T7\]Q@ZVI\[Q3QRV@R^66[jYg5:5=<?4ar{mgZ`nnfU>=?v<202:b>gtqgiTjdh`_431|64+n`ldSjkaescwkwYq0V9'wnQnde]mcfYdggy~lgat<2/gZgwxechmyg`n^vzt`Yfp`y6<!mPaqromfgsafdTxt~j_sc`l86+kVk{|aglaukljZr~xlUyhnf20-a\euvkajkeb`Ptxrf[rgd`4:'oRopmk`eqohfV~r|hQxdbj>4)eXiyzgeno{inl\p|vbW~xhd0>#c^c{mZgcl{U|eizg=20/gZgaVkyy~k}_vkgpm;6$jUjtdQnwtqfvZqnl}b6=!mPayk\fpubzV}bhyf21-a\e}oXlh~jSzgkti?50)eXiqcTeiQxievk91*dWhrbS{|es]tmaro58&hSlvf_u{sa86+kVkseRyzsdp\slbs`4;'oRowir]w`drfW~coxe394-a\e}otW}nnyQxievk91*dWhrbRzfd^uj`qn:0%iTmug|_uifauYpam~c19"l_`zjwZrt|{hT{dj{h<6/gZgazUy~k}_vkgpm;3$jUjtd}Ptxrf95*dWjefab`Pcmm`o86+kVidyczPtxrf95*dWmkmRm`uov\slbs`43'oRjjf`wopZpfd|o6NaoakRvqmka+kVnbbRyfduj>77*dWmceSzgkti]b|lu:9%iThd`PwhfwlZtfka78>!mPdhl\slbs`Vxooe394-a\`lhX`ndRynci?06)eXl`dT{dj{h^uggm;1<%iThd`PwhfwlZquka79 nQkotv\vvrX~hf6<!mPdnww[roc|a78>!mPeocah`Yudfix1="l_dlbficXzz~Tt`l=0.`[`tug{Ubbgklthmm[qwm4:'oRk}rnp\mklbk}cdbRzvpd]b|lu:8%iTi|`r^kmn`esafdTxt~j_sc`l86+kVoy~b|PiohfgqohfV~r|hQ}dbj>4)eXm{xd~RgajdawmjhX|pznSzolh<2/gZcuzfxTecdjcukljZr~xlU|hnf20-a\awthzVcefhm{inl\p|vbW~xhd0>#c^dbilj~5cyxhv9,b]eqijXneklR||t^tbh87+kVbjRocmnqw[`kw|p7; nQgar]bhhit|Vl~`a3?,b]kevYfp`Uj~x}jr<2/gZnf{VkseRoxurgq95*dWakxSlvf_cwpaw;7$jUcm~Qnxh]q`Zeoigdn`0>#c^jbwZgaVx~h|20-a\lduXiqcT{Qlh`lmai;7$jUcm~Qnxh]tqvcu59&hSeo|_`zjwZrci}k6<!mPh`q\e}otW}nny3?,b]kevYfp`yTxdj20-a\lduXiqcxSyejeq?3(fYoizUjtd}Ptmcpp86+kVbjRowir]wv`gcq4;'oRfns^c{mvYs{}xi1="l_icp[d~n{V~~h|20-a\lduXjhi`y}3?,b]kevYci}kTob{at<2/gZnf{VnjxlQlotlwwZgaz7; nQgar]geqgXkfex~Q}abj>4)eX`hyThlzn_bmvjquXzmic1="l_icp[agsiVidycz|_vc`l86+kVbjRjnt`]`kphs{V}ooe3?,b]kevYci}kTob{atr]tvfn:8%iTdl}Piov\gim:8%iTdl}Pm`qwawYdm4:'oRfns^ofilhn|Vlb`h3?,b]kevYh~lxm`by20-a\lduXx{elSkbngr]b|lu:8%iTdl}Ppsmd[cjfozUymnf20-a\lduXx{elSkbngr]q`fn:8%iTdl}Ppsmd[cjfozU|mnf20-a\lduXx{elSkbngr]t`fn:8%iTdl}Ppsmd[cjfozU|~nf20-a\lduXzmUomyoPcnwmp86+kVbjR|k_sqw95*dWakxS}{=0.`[mgtWzfjzhQle<2/gZnf{Vyyy3?,b]kevYrfmoyjaax=1.`[mgtWkgei3?,b]kevYpzVkhg0>#c^jbwZquWmkmRm`uov>4)eX`hyT{Q}su?3(fYneyfnah`{aukljZr~xl79 nQfmqnfi`hsi}cdbRzvpd]b|lu:9%iTe`~celgmpdrnggUu}kPr`ak94*dW`g{`hcjnucwmjhX|pznSjlh<3/gZojxeoficznthmm[qwmV}joe3>,b]jiujbeldmyg`n^vzt`Ypljb6=!mPilroahci|h~bccQ{yqg\sweo58&hSd`ft^uq[uhszV|j`0>#c^kmp`taijoTxt~j=1.`[hcjg{sTxt~j=0.`[hoaWocgiR`nmd?Ahdhl[}xbbj"l_lqdkkYqie7: nQ`puknmgsafdTabjj=1.`[jpbzofd{Rb`w<2/gZvumeejhRbntdl`}87+kVzyiaand^pfcv;7$jU{~dcPfhdl[qwm4?:>u=9,b]svjaXmdzuRzgrdqk[dutm{~Tzlb22-a\twi`Wlg{xtQ{hsgplZgt{lxS{oc_`zjw877:;&hS}|`g^gntqX|axneQnsrgqpZpfdVxjoe3>030/gZvugnUna}zv_ujqavnXizyn~yQyam]q`fn:9989 nQrne\ahvsqV~c~h}g_`qpawrX~hfT{lmg=0216)eXx{elShctx]wlwct`Vkxh|{_wco[rbd`4;;>?"l_qplcZcjx}sTxe|jsi]bwvcu|V|j`Ry}ci?2474+kVzycjQjmqvz[qnumzbTbhintd]uei;4$jU{~biPelrw}Zr~xl7; nQrne\ahvsqV~r|hQnxhq>1)eXx{elShctx]w}ucXzhic18"l_qplcZcjx}sTxt~j_sf`l83+kVzycjQjmqvz[qwmV}joe3:,b]svjaXmdzuRzvpd]t`fn:=%iT|ah_dosp|YsqyoT{mg=4.`[uthoVl~`aQ{hsgplZgt{lxS{oc=42:(fYwzfmTjxbc_ujqavnXizyn~yQyam]b|lu:9988 nQrne\bpjkW}byi~fParqfvqYqieUymnf21100(fYwzfmTjxbc_ujqavnXizyn~yQyam]q`fn:9988 nQrne\bpjkW}byi~fParqfvqYqieU|mnf21100(fYwzfmTjxbc_ujqavnXizyn~yQyam]t`fn:9988 nQrne\bpjkW}byi~fParqfvqYqieU|~nf21100(fYwzfmTjxbc_ujqavnXflmjxhQyam?64=*dWyxdkRhzlm]w}uc:8%iT|ah_gwohZr~xlUjtd}25-a\twi`Wog`Rzvpd]qefn:=%iT|ah_gwohZr~xlUyhnf25-a\twi`Wog`Rzvpd]tefn:=%iT|ah_gwohZr~xlU|hnf25-a\twi`Wog`Rzvpd]tvfn:=%iT~lmg_u{sa86+kVxoSio{a^alqkrX`nd07#c^pg[acw|a7>=?"l_sf\bwcv58&hSjPpovq[roc|a72 nQ}dbj\p|vb59&hSkh_rnjg`YjgmoTmug|=1.`[wc`WzfbohQboeg\vdeo59&hSkh_rnjg`YjgmoT~img=1.`[wc`WzfbohQboeg\sdeo59&hSkh_rnjg`YjgmoT{img=1.`[wc`WzfbohQboeg\sweo59&hSx`kesdokrYkg~7; nQzsd]`khkhfVe}ihcov?3(fYr{lUhc`c`n^wm``tadf}6<!mPurg\```f}e~Thz{ioep95*dW|ynSiazt^ppp87+kVxiRklc<2/gZstmVohoRowir?3(fYr{lUnonQ}abj>4)eX}zoTinmPreak95*dW|ynShml_vc`l86+kVxiRklc^uggm;7$jU~hQjcb]tvfn:8%iTy~kPel`f`accW{ol1="l_tqf[coag8<Tjaohs<2/gZstmVl|jyQkauc\gjsi|4:'oRxnlhf\hjq:8%iT{lmg_u{sa86+kV}ooeQ{yqg>4)eX{UjofQcov?3(fYpzVnjxlQlotlw[roc|a72 nQxr^fftqn:=88'oRy}_egspmYfp`y6==<;,b]tvZbbx}bT~lmg=04/gZquWmo{xeQ}dbj>5543$jU|~Rjjpuj\sdeo58<'oRy}_egspmYpljb6==<;,b]tvZbbx}bT{mg=04/gZquWoxn}0?#c^uq[uhszV}bhyf29-a\swYwf}xT{dj{h^c{mv;68%iT{Qnup\slbs`Vxjoe3;,b]tvZvi|{U|eizg_sf`l877$jU|~R~ats]tmaroW~khd0:#c^uq[uhszV}bhyfPweak946+kV}yS}`{r^uj`qnX{ic19"l_vp\v`uwggynSao{eoaz94*dW~xhdRzvpd?3y7><izseoRhffn]657~4:%lbjbQheogqeqiuW2T?!ur199ahnYjmdUlicQheogqmfYd{}x::6lck^ofiZabfVzye`Qxievk5g=edbUfi`Qheo]svlkX{k{|h|Pv7d8fimXelgTkh`Ptnr20>dkcVgnaRijn^t5[7Y{};87obd_lgn[lhw}}Ui`bmd159ahnYjmdUdyy~zt^`okfme3jf`SuQnupp3>eheykyi>5kdl48`lh;87=0hd`311<4?aoi48;5;6jfn=31:2=cag6:?394dhl?51803mce0<;17:fjj9716>1oec2>7?58`lh;914<7iga<0;=2>bnf5;5;6jfn=03:2=cag69=394dhl?67803mce0?=17:fjj9436>1oec2=5?58`lh;:?4<7iga<35=3>bnf5832:5kio>1=;0<l`d7>394dhl?758>3mce0>?50?58`lh;;84=7iga<2<5?aoi4=4=7iga<4<5?aoi4?4=7iga<6<5?aoi414=7iga<8<4?air|5:546j`uu>24;><lf0<?18:flqq:6:720hb{{<01=<>bh}}6:8364dnww843902ndyy2>6?:8`jss48=546j`uu>2<;><lf0<717:flqq:6611ocxz321<;?air|58:255kotv?678?3me~x1<<>99gkpr;:=437iazt=06:==cg|~7>;07;emvp940611ocxz329<;?air|5822:5kotv?6;><lf0>>1a:flqq:493:546j`uu>05;1<lf0>08;emvp929?2ndyy2:>69gkpr;>7=0hb{{<6<4?air|525;6j`uu>::0=bey~r=;5iigm\c`hbzh~d~R|nmgkek44<n`ldSjkaescwkwYsgy;87kgio^efj`tf|fxTz5Q<2g9emciXoldn~lz`r^t;[6*'P`fbbu.LOSG#C`hbzh~d~-?<.234?coagVmnbh|ntnp\r=Y4Wqy86hzlm;8mkvr|Vhgg;5belmq}==iojh~eajn;nwwtprXjeai7jPbhl\gkru>2xoSnbd5:pg[`h?3{nT`bifc008vaYt|h~~Rhcafq\ev763{oxiyQmlj]qeh`nnf90~~zm;vp\flhXkg~y:6y}_bnh1>quWld37z|Plnejg44<{Uxxlzzs^doebuXizwKL}6<3:BC|63c2O0?6<u\6d800=<6;h0:?>>;978174dfsg9?:7?4n264>3=#;=>1?>h4}R4`>62?289j6<=<05;5>756kl1X=?;53c794?74;9>2:7<<1e38W3e=;k?1<7?<316:2?449m>0h>;k:182>4}T>l08854>3`8276631?09?<mm;wV21g<7280:6<=;{R4f>62?289j6<=<05;5>756kk1/??o51358R6222;q~=?h51:w275<73t.:?n4>f:`01a<72==1j=4>35yK77><,8<;6>;k;[70>7}6=3;=6p*<4280f5=#=?089k5+6e801`=#9<=1=6*>57800<=n;191<7*>3d80<7=i9:n1<65f39394?"6;l084?5a12f95>=n;>l1<7*>3d80<7=i9:n1>65f36g94?"6;l084?5a12f97>=n;>n1<7*>3d80<7=i9:n1865f36a94?"6;l084?5a12f91>=n;>h1<7*>3d80<7=i9:n1:65f36c94?"6;l084?5a12f93>=n;>31<7*>3d80<7=i9:n1465f36:94?"6;l084?5a12f9=>=n;>=1<7*>3d80<7=i9:n1m65f36494?"6;l084?5a12f9f>=n;>>1<7*>3d80<7=i9:n1o65f36194?"6;l084?5a12f9`>=n;>81<7*>3d80<7=i9:n1i65f36394?"6;l084?5a12f9b>=n;>:1<7*>3d80<7=i9:n1==54i24e>5<#9:o1?5<4n01g>47<3`9=i7>5$01f>6>53g;8h7?=;:k02a<72-;8i7=72:l27a<6;21b?;m50;&27`<40;1e=>j51598m60e290/=>k53908j45c28?07d=7a;29 45b2:297c?<d;35?>o4000;6)?<e;1;6>h6;m0:;65f39:94?"6;l084?5a12f95==<a:2<6=4+12g97=4<f89o6<74;h1;2?6=,89n6>6=;o30`?7f32c8484?:%30a?5?:2d:?i4>b:9j7=2=83.:?h4<839m56b=9j10e>6?:18'56c=;180b<=k:0f8?l50=3:1(<=j:2:1?k74l3;n76g<6`83>!74m393>6`>3e82b>=n;kn1<75f3cd94?=n;k21<75f3b294?=n;k31<75`3`694?"6;l08m>5a12f94>=h;h81<7*>3d80e6=i9:n1=65`3`294?"6;l08m>5a12f96>=h;0l1<7*>3d80e6=i9:n1?65`38g94?"6;l08m>5a12f90>=h;0n1<7*>3d80e6=i9:n1965`38a94?"6;l08m>5a12f92>=h;0h1<7*>3d80e6=i9:n1;65`38c94?"6;l08m>5a12f9<>=h;031<7*>3d80e6=i9:n1565`38:94?"6;l08m>5a12f9e>=h;0=1<7*>3d80e6=i9:n1n65`38794?"6;l08m>5a12f9g>=h;0>1<7*>3d80e6=i9:n1h65`38194?"6;l08m>5a12f9a>=h;081<7*>3d80e6=i9:n1j65`38394?"6;l08m>5a12f955=<g:3;6=4+12g97d5<f89o6<?4;n1;b?6=,89n6>o<;o30`?7532e84h4?:%30a?5f;2d:?i4>3:9l7=b=83.:?h4<a29m56b=9=10c>6l:18'56c=;h90b<=k:078?j5fj3:1(<=j:2c0?k74l3;=76a<a`83>!74m39j?6`>3e823>=h;h31<7*>3d80e6=i9:n1=554o2c;>5<#9:o1?l=4n01g>4?<3f9j;7>5$01f>6g43g;8h7?n;:m0e3<72-;8i7=n3:l27a<6j21d?l;50;&27`<4i:1e=>j51b98k6g6290/=>k53`18j45c28n07b=66;29 45b2:k87c?<d;3f?>i40k0;6)?<e;1b7>h6;m0:j65`3c094?=h;hi1<75m35094?7=83:p(<8?:20:?M5382B8>55`12`94?=zj:>:6=4>:183!7183n;7E=;0:J06==hko0;66sm24g94?2=83:p(<8?:bf8L6273A9946*j0;58m02=831b:k4?::k205<722e:8?4?::a60b=83>1<7>t$043>fb<@:>;7E==8:&f4?1<a<>1<75f6g83>>o6<90;66a>4383>>{e:j:1<7:50;2x 4072jn0D>:?;I11<>"b83=0e8:50;9j2c<722c:8=4?::m207<722wi>oh50;694?6|,8<;6nj4H263?M5502.n<794i4694?=n>o0;66g>4183>>i6<;0;66sm31d94?2=83:p(<8?:b`8L6273A9946*j0;08m02=831b:o4?::k5b?6=3f;?>7>5;|`05c<72:0;6=u+1729gd=O;=:0D><7;I71?!75l3;>j6*j0;08m02=831b:k4?::m207<722wi??:50;194?6|,8<;6no4H263?M5502B>>6*>2e821c=#m9097d;;:188m3`=831d=9<50;9~f675290?6=4?{%354?ec3A9?<6F<299K17=#9;n1=8h4$d293>o2<3:17d8i:188m4272900c<:=:188yg56m3:1?7>50z&225<di2B88=5G33:8L04<,88o6<;i;%g3>7=n==0;66g9f;29?j73:3:17pl<2283>6<729q/=;>5c`9K716<@:837E;=;%31`?72n2.n<7<4i4694?=n>o0;66a>4383>>{e;8;1<7:50;2x 4072jn0D>:?;I11<>N2:2.:>i4>5g9'a5<03`??6=44i7d94?=n9=:1<75`15094?=zj:;36=4;:183!7183io7E=;0:J06==#m90<7d;;:188m3`=831b=9>50;9l514=831vn>?8:187>5<7s-;=<7mk;I174>N4:11/i=48;h77>5<<a?l1<75f15294?=h9=81<75rb235>5<3290;w)?90;ag?M5382B8>55+e184?l332900e;h50;9j516=831d=9<50;9~f67c290>6=4?{%354?eb3A9?<6F<299K17=#9;n1=8h4i4694?=n=<0;66g9f;29?l7383:17b?;2;29?xd49j0;694?:1y'536=km1C?9>4H20;?!c72>1b994?::k5b?6=3`;?<7>5;n376?6=3th8=o4?:583>5}#9?:1oi5G3528L64?3-o;6:5f5583>>o1n3:17d?;0;29?j73:3:17pl<1183>1<729q/=;>5ce9K716<@:837E;=;%31`?72n2.n<794i4694?=n>o0;66g>4183>>i6<;0;66sm28f94?2=83:p(<8?:00f?M5382B8>55f5683>>o093:17d?:3;29?j7413:17pl=9b83>1<729q/=;>513g8L6273A9946g:7;29?l162900e<;<:188k45>2900qo<6b;290?6=8r.::=4>2d9K716<@:837d;8:188m27=831b=8=50;9l56?=831vn?7n:187>5<7s-;=<7?=e:J005=O;;20e8950;9j34<722c:9>4?::m27<<722wi>4k50;694?6|,8<;6<<j;I174>N4:11b9:4?::k45?6=3`;>?7>5;n30=?6=3th9n=4?:583>5}#9?:1=?k4H263?M5502c>;7>5;h52>5<<a8?86=44o01:>5<<uk8jj7>54;294~"6>90:>h5G3528L64?3`?<6=44i6394?=n9<91<75`12;94?=zj;kn6=4;:183!7183;9i6F<419K77><a<=1<75f7083>>o6=:0;66a>3883>>{e:hn1<7:50;2x 407288n7E=;0:J06==n=>0;66g81;29?l72;3:17b?<9;29?xd5j80;694?:1y'536=9;o0D>:?;I11<>o2?3:17d9>:188m4342900c<=6:188yg44i3:187>50z&225<6:l1C?9>4H20;?l302900e:?50;9j505=831d=>750;9~f75>290?6=4?{%354?75m2B88=5G33:8m01=831b;<4?::k216<722e:?44?::a66>=83>1<7>t$043>44b3A9?<6F<299j12<722c<=7>5;h367?6=3f;857>5;|`172<72=0;6=u+172957c<@:>;7E==8:k63?6=3`=:6=44i070>5<<g8926=44}c00f?6=<3:1<v*>61826`=O;=:0D><7;h74>5<<a>;1<75f14194?=h9:31<75rb36g>5<3290;w)?90;31a>N4<91C??64i4594?=n?80;66g>5283>>i6;00;66sm25a94?2=83:p(<8?:00f?M5382B8>55f5683>>o093:17d?:3;29?j7413:17pl=4c83>1<729q/=;>513g8L6273A9946g:7;29?l162900e<;<:188k45>2900qo<;a;290?6=8r.::=4>2d9K716<@:837d;8:188m27=831b=8=50;9l56?=831vn?:j:187>5<7s-;=<7?=e:J005=O;;20e8950;9j34<722c:9>4?::m27<<722wi>4:50;794?6|,8<;6nm4H263?M5502.n<7<4i4694?=n=<0;66g9b;29?l0a2900c<:=:188yg4>;3:197>50z&225<dk2B88=5G33:8 `6=:2c>87>5;h76>5<<a?h1<75f6g83>>i6<;0;66sm28094?3=83:p(<8?:ba8L6273A9946*j0;08m02=831b984?::k5f?6=3`<m6=44o061>5<<uk82=7>55;294~"6>90ho6F<419K77><,l:1>6g:4;29?l322900e;l50;9j2c<722e:8?4?::a6<6=83?1<7>t$043>fe<@:>;7E==8:&f4?4<a<>1<75f5483>>o1j3:17d8i:188k4252900qo<7f;291?6=8r.::=4lc:J005=O;;20(h>52:k60?6=3`?>6=44i7`94?=n>o0;66a>4383>>{e:1o1<7;50;2x 4072ji0D>:?;I11<>"b8380e8:50;9j10<722c=n7>5;h4e>5<<g8>96=44}c0;`?6==3:1<v*>618`g>N4<91C??64$d296>o2<3:17d;::188m3d=831b:k4?::m207<722wi>5m50;794?6|,8<;6nm4H263?M5502.n<7<4i4694?=n=<0;66g9b;29?l0a2900c<:=:188yg4?:3:197>50z&225<dk2B88=5G33:8 `6=:2c>87>5;h76>5<<a?h1<75f6g83>>i6<;0;66sm29394?3=83:p(<8?:ba8L6273A9946*j0;08m02=831b984?::k5f?6=3`<m6=44o061>5<<uk83<7>55;294~"6>90ho6F<419K77><,l:1>6g:4;29?l322900e;l50;9j2c<722e:8?4?::a62`=83?1<7>t$043>fe<@:>;7E==8:&f4?4<a<>1<75f5483>>o1j3:17d8i:188k4252900qo<8e;291?6=8r.::=4lc:J005=O;;20(h>52:k60?6=3`?>6=44i7`94?=n>o0;66a>4383>>{e:>n1<7;50;2x 4072ji0D>:?;I11<>"b8380e8:50;9j10<722c=n7>5;h4e>5<<g8>96=44}c04g?6==3:1<v*>618`g>N4<91C??64$d296>o2<3:17d;::188m3d=831b:k4?::m207<722wi>:l50;794?6|,8<;6nm4H263?M5502.n<7<4i4694?=n=<0;66g9b;29?l0a2900c<:=:188yg57;3:197>50z&225<dk2B88=5G33:8 `6=:2c>87>5;h76>5<<a?h1<75f6g83>>i6<;0;66sm31094?3=83:p(<8?:ba8L6273A9946*j0;08m02=831b984?::k5f?6=3`<m6=44o061>5<<uk9;=7>55;294~"6>90ho6F<419K77><,l:1>6g:4;29?l322900e;l50;9j2c<722e:8?4?::a756=83?1<7>t$043>fe<@:>;7E==8:&f4?4<a<>1<75f5483>>o1j3:17d8i:188k4252900qo<if;291?6=8r.::=4lc:J005=O;;20(h>52:k60?6=3`?>6=44i7`94?=n>o0;66a>4383>>{e:oo1<7;50;2x 4072ji0D>:?;I11<>"b8380e8:50;9j10<722c=n7>5;h4e>5<<g8>96=44}c0e`?6==3:1<v*>618`g>N4<91C??64$d296>o2<3:17d;::188m3d=831b:k4?::m207<722wi>k;50;794?6|,8<;6nm4H263?M5502.n<7<4i4694?=n=<0;66g9b;29?l0a2900c<:=:188yg4a<3:197>50z&225<dk2B88=5G33:8 `6=:2c>87>5;h76>5<<a?h1<75f6g83>>i6<;0;66sm2g194?3=83:p(<8?:ba8L6273A9946*j0;08m02=831b984?::k5f?6=3`<m6=44o061>5<<uk8m>7>55;294~"6>90ho6F<419K77><,l:1>6g:4;29?l322900e;l50;9j2c<722e:8?4?::a6c7=83?1<7>t$043>fe<@:>;7E==8:&f4?4<a<>1<75f5483>>o1j3:17d8i:188k4252900qo<i0;291?6=8r.::=4lc:J005=O;;20(h>52:k60?6=3`?>6=44i7`94?=n>o0;66a>4383>>{e:ll1<7;50;2x 4072ji0D>:?;I11<>"b8380e8:50;9j10<722c=n7>5;h4e>5<<g8>96=44}c0fa?6==3:1<v*>618`g>N4<91C??64$d296>o2<3:17d;::188m3d=831b:k4?::m207<722wi>hj50;794?6|,8<;6nk4H263?M5502.n<794i4694?=n=<0;66g9f;29?l7383:17b?;2;29?xd5m:0;684?:1y'536=kj1C?9>4H20;?!c72;1b994?::k61?6=3`<i6=44i7d94?=h9=81<75rb3g1>5<2290;w)?90;a`?M5382B8>55+e181?l332900e8;50;9j2g<722c=j7>5;n376?6=3th9i<4?:483>5}#9?:1on5G3528L64?3-o;6?5f5583>>o2=3:17d8m:188m3`=831d=9<50;9~f7c7290>6=4?{%354?ed3A9?<6F<299'a5<53`??6=44i4794?=n>k0;66g9f;29?j73:3:17pl=dg83>0<729q/=;>5cb9K716<@:837)k?:39j11<722c>97>5;h4a>5<<a?l1<75`15094?=zj;nn6=4::183!7183ih7E=;0:J06==#m9097d;;:188m03=831b:o4?::k5b?6=3f;?>7>5;|`1`a<72<0;6=u+1729gf=O;=:0D><7;%g3>7=n==0;66g:5;29?l0e2900e;h50;9l514=831vn?jl:186>5<7s-;=<7mj;I174>N4:11/i=48;h77>5<<a<?1<75f6g83>>o6<90;66a>4383>>{e9lh1<7:50;2x 4072jh0D>:?;I11<>"b8380e8:50;9j2g<722c=j7>5;n376?6=3th:il4?:583>5}#9?:1oo5G3528L64?3-o;6?5f5583>>o1j3:17d8i:188k4252900qo?j9;290?6=8r.::=4lb:J005=O;;20(h>52:k60?6=3`<i6=44i7d94?=h9=81<75rb0g;>5<3290;w)?90;aa?M5382B8>55+e181?l332900e;l50;9j2c<722e:8?4?::a5`1=83>1<7>t$043>fd<@:>;7E==8:&f4?4<a<>1<75f6c83>>o1n3:17b?;2;29?xd6m?0;694?:1y'536=kk1C?9>4H20;?!c72;1b994?::k5f?6=3`<m6=44o061>5<<uk;n97>54;294~"6>90hn6F<419K77><,l:1>6g:4;29?l0e2900e;h50;9l514=831vn<k;:187>5<7s-;=<7mm;I174>N4:11/i=4=;h77>5<<a?h1<75f6g83>>i6<;0;66sm1d194?2=83:p(<8?:b`8L6273A9946*j0;08m02=831b:o4?::k5b?6=3f;?>7>5;|`2=7<72=0;6=u+1729gg=O;=:0D><7;%g3>7=n==0;66g9b;29?l0a2900c<:=:188yg7>93:187>50z&225<dj2B88=5G33:8 `6=:2c>87>5;h4a>5<<a?l1<75`15094?=zj83;6=4;:183!7183ii7E=;0:J06==#m9097d;;:188m3d=831b:k4?::m207<722wi=5h50;694?6|,8<;6nl4H263?M5502.n<7<4i4694?=n>k0;66g9f;29?j73:3:17pl>8d83>1<729q/=;>5cc9K716<@:837)k?:39j11<722c=n7>5;h4e>5<<g8>96=44}c3;`?6=<3:1<v*>618`f>N4<91C??64$d296>o2<3:17d8m:188m3`=831d=9<50;9~f4>d290?6=4?{%354?ee3A9?<6F<299'a5<53`??6=44i7`94?=n>o0;66a>4383>>{e91h1<7:50;2x 4072jh0D>:?;I11<>"b8380e8:50;9j2g<722c=j7>5;n376?6=3th:4l4?:583>5}#9?:1oo5G3528L64?3-o;6?5f5583>>o1j3:17d8i:188k4252900qo<<2;290?6=8r.::=4lb:J005=O;;20(h>52:k60?6=3`<i6=44i7d94?=h9=81<75rb312>5<3290;w)?90;aa?M5382B8>55+e181?l332900e;l50;9j2c<722e:8?4?::a666=83>1<7>t$043>fd<@:>;7E==8:&f4?4<a<>1<75f6c83>>o1n3:17b?;2;29?xd5:o0;694?:1y'536=kk1C?9>4H20;?!c72;1b994?::k5f?6=3`<m6=44o061>5<<uk89i7>54;294~"6>90hn6F<419K77><,l:1>6g:4;29?l0e2900e;h50;9l514=831vn?<k:187>5<7s-;=<7mm;I174>N4:11/i=4=;h77>5<<a?h1<75f6g83>>i6<;0;66sm23a94?2=83:p(<8?:b`8L6273A9946*j0;08m02=831b:o4?::k5b?6=3f;?>7>5;|`16g<72=0;6=u+1729gg=O;=:0D><7;%g3>7=n==0;66g9b;29?l0a2900c<:=:188yg45i3:187>50z&225<dj2B88=5G33:8 `6=:2c>87>5;h4a>5<<a?l1<75`15094?=zj8n26=4;:183!7183ii7E=;0:J06==#m9097d;;:188m3d=831b:k4?::m207<722wi=i650;694?6|,8<;6nl4H263?M5502.n<7<4i4694?=n>k0;66g9f;29?j73:3:17pl>d683>1<729q/=;>5cc9K716<@:837)k?:39j11<722c=n7>5;h4e>5<<g8>96=44}c3g2?6=<3:1<v*>618`f>N4<91C??64$d296>o2<3:17d8m:188m3`=831d=9<50;9~f4b2290?6=4?{%354?ee3A9?<6F<299'a5<53`??6=44i7`94?=n>o0;66a>4383>>{e9m>1<7:50;2x 4072jh0D>:?;I11<>"b8380e8:50;9j2g<722c=j7>5;n376?6=3th:h>4?:583>5}#9?:1oo5G3528L64?3-o;6?5f5583>>o1j3:17d8i:188k4252900qo?k2;290?6=8r.::=4lb:J005=O;;20(h>52:k60?6=3`<i6=44i7d94?=h9=81<75rb0f2>5<3290;w)?90;aa?M5382B8>55+e181?l332900e;l50;9j2c<722e:8?4?::a65`=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a65c=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a65b=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a65e=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a65d=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a65g=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a65?=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a65>=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a651=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a5g0=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a5g3=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a5g2=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a5g5=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a5g4=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a5g7=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a5g6=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a5d`=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a5dc=83>1<7>t$043>fd<@:>;7E==8:J66>"6:m0:9k5+e181?l332900e;l50;9j2c<722e:8?4?::a5d2=83>1<7>t$043>fd<@:>;7E==8:&f4?4<a<>1<75f6c83>>o1n3:17b?;2;29?xd6i:0;694?:1y'536=kk1C?9>4H20;?!c72;1b994?::k5f?6=3`<m6=44o061>5<<uk;j>7>54;294~"6>90hn6F<419K77><,l:1>6g:4;29?l0e2900e;h50;9l514=831vn<o>:187>5<7s-;=<7mm;I174>N4:11/i=4=;h77>5<<a?h1<75f6g83>>i6<;0;66sm1`294?2=83:p(<8?:b`8L6273A9946*j0;08m02=831b:o4?::k5b?6=3f;?>7>5;|`2=c<72=0;6=u+1729gg=O;=:0D><7;%g3>7=n==0;66g9b;29?l0a2900c<:=:188yg7>m3:187>50z&225<dj2B88=5G33:8 `6=:2c>87>5;h4a>5<<a?l1<75`15094?=zj83o6=4;:183!7183ii7E=;0:J06==#m9097d;;:188m3d=831b:k4?::m207<722wi=4m50;694?6|,8<;6nl4H263?M5502.n<7<4i4694?=n>k0;66g9f;29?j73:3:17pl>fe83>1<729q/=;>5cc9K716<@:837)k?:39j11<722c=n7>5;h4e>5<<g8>96=44}c3eg?6=<3:1<v*>618`f>N4<91C??64$d296>o2<3:17d8m:188m3`=831d=9<50;9~f4`e290?6=4?{%354?ee3A9?<6F<299'a5<53`??6=44i7`94?=n>o0;66a>4383>>{e9ok1<7:50;2x 4072jh0D>:?;I11<>"b8380e8:50;9j2g<722c=j7>5;n376?6=3th:j44?:583>5}#9?:1oo5G3528L64?3-o;6?5f5583>>o1j3:17d8i:188k4252900qo?i8;290?6=8r.::=4lb:J005=O;;20(h>52:k60?6=3`<i6=44i7d94?=h9=81<75rb0d4>5<3290;w)?90;aa?M5382B8>55+e181?l332900e;l50;9j2c<722e:8?4?::a5c0=83>1<7>t$043>fd<@:>;7E==8:&f4?4<a<>1<75f6c83>>o1n3:17b?;2;29?xd6n<0;694?:1y'536=kk1C?9>4H20;?!c72;1b994?::k5f?6=3`<m6=44o061>5<<uk8>j7>53;294~"6>90:>55G3528L64?3-o;6h5+12d970d<am81<75fd283>>i6;00;66sm2b394?5=83:p(<8?:00;?M5382B8>55+e18f?lb52900ei=50;9l56?=831vn>>m:187>5<7s-;=<7?=9:J005=O;;20(h>5549'56`=;<h0ei<50;9j`6<722co87>5;n30=?6=3th99o4?:483>5}#9?:1=?o4H263?M5502.n<7m8;hf1>5<<am91<75fd583>>oc=3:17b?<9;29?xd51<0;6;4?:1y'536=9;h0D>:?;I11<>"b83;<7dj=:188ma5=831bh94?::kg1?6=3`n=6=44o01:>5<<uk99=7>53;294~"6>90:>55G3528L64?3-o;6h5fd383>>oc;3:17b?<9;29?xd4:>0;6>4?:1y'536=9;20D>:?;I11<>"b83o0(<=i:270?lb52900ei=50;9l56?=831vn?o9:186>5<7s-;=<7?=a:J005=O;;20(h>5259j`7<722co?7>5;hf7>5<<am?1<75`12;94?=zj;k?6=4::183!7183;9m6F<419K77><,l:1>95fd383>>oc;3:17dj;:188ma3=831d=>750;9~f7g5290>6=4?{%354?75i2B88=5G33:8 `6=:=1bh?4?::kg7?6=3`n?6=44ie794?=h9:31<75rb3c3>5<2290;w)?90;31e>N4<91C??64$d2961=nl;0;66gk3;29?lb32900ei;50;9l56?=831vn?o7:180>5<7s-;=<7?=8:J005=O;;20(h>5229j`7<722co?7>5;n30=?6=3th9n44?:483>5}#9?:1=?o4H263?M5502.n<7<;;hf1>5<<am91<75fd583>>oc=3:17b?<9;29?xd5j>0;684?:1y'536=9;k0D>:?;I11<>"b838?7dj=:188ma5=831bh94?::kg1?6=3f;857>5;|`1f0<72<0;6=u+172957g<@:>;7E==8:&f4?433`n96=44ie194?=nl=0;66gk5;29?j7413:17pl=bc83>6<729q/=;>513:8L6273A9946*j0;00?lb52900ei=50;9l56?=831vn?:<:186>5<7s-;=<7?=a:J005=O;;20(h>5259j`7<722co?7>5;hf7>5<<am?1<75`12;94?=zj;>:6=4::183!7183;9m6F<419K77><,l:1>95fd383>>oc;3:17dj;:188ma3=831d=>750;9~f75a290>6=4?{%354?75i2B88=5G33:8 `6=:=1bh?4?::kg7?6=3`n?6=44ie794?=h9:31<75rb31g>5<2290;w)?90;31e>N4<91C??64$d2961=nl;0;66gk3;29?lb32900ei;50;9l56?=831vn?:::180>5<7s-;=<7?=8:J005=O;;20(h>5229j`7<722co?7>5;n30=?6=3th99;4?:483>5}#9?:1=?o4H263?M5502.n<7<;;hf1>5<<am91<75fd583>>oc=3:17b?<9;29?xd5==0;684?:1y'536=9;k0D>:?;I11<>"b838?7dj=:188ma5=831bh94?::kg1?6=3f;857>5;|`117<72<0;6=u+172957g<@:>;7E==8:&f4?463`n96=44ie194?=nl=0;66gk5;29?j7413:17pl=5983>6<729q/=;>513:8L6273A9946*j0;00?lb52900ei=50;9l56?=831vn?97:184>5<7s-;=<7?=c:J005=O;;20(h>52c9j`7<722co?7>5;hf7>5<<am?1<75fd783>>oc?3:17b?<9;29?xd5??0;6;4?:1y'536=9;h0D>:?;I11<>"b838j7dj=:188ma5=831bh94?::kg1?6=3`n=6=44o01:>5<<uk8o57>57;294~"6>90:>n5G3528L64?3-o;6?l4ie094?=nl:0;66gk4;29?lb22900ei850;9j`2<722e:?44?::a6a1=83<1<7>t$043>44e3A9?<6F<299'a5<5i2co>7>5;hf0>5<<am>1<75fd483>>oc>3:17b?<9;29?xd6k80;6>4?:1y'536=9;20D>:?;I11<>"b83;j7)?<f;16=>oc:3:17dj<:188k45>2900qo?l3;290?6=8r.::=4>289K716<@:837)k?:378 45a2:?27dj=:188ma5=831bh94?::m27<<722wi><h50;194?6|,8<;6<<7;I174>N4:11/i=4>a:kg6?6=3`n86=44o01:>5<<uk89=7>54;294~"6>90:>45G3528L64?3-o;6?;4$01e>63f3`n96=44ie194?=nl=0;66a>3883>>{e9>:1<7=50;2x 40728837E=;0:J06==#m90:m6*>3g8015=nl;0;66gk3;29?j7413:17pl>6g83>6<729q/=;>513:8L6273A9946*j0;3b?!74n39><6gk2;29?lb42900c<=6:188yg71m3:1?7>50z&225<6:11C?9>4H20;?!c728k0(<=i:271?lb52900ei=50;9l56?=831vn<8k:180>5<7s-;=<7?=8:J005=O;;20(h>51`9'56`=;<80ei<50;9j`6<722e:?44?::a53e=8391<7>t$043>44?3A9?<6F<299'a5<6i2.:?k4<509j`7<722co?7>5;n30=?6=3th::o4?:283>5}#9?:1=?64H263?M5502.n<7?n;%30b?5292co>7>5;hf0>5<<g8926=44}c35<?6=;3:1<v*>61826==O;=:0D><7;%g3>4g<,89m6>;l;hf1>5<<am91<75`12;94?=zj8<<6=4<:183!7183;946F<419K77><,l:1=l5+12d970e<am81<75fd283>>i6;00;66sm17494?5=83:p(<8?:00;?M5382B8>55+e182e>"6;o088i5fd383>>oc;3:17b?<9;29?xd6><0;6>4?:1y'536=9;20D>:?;I11<>"b83;j7)?<f;17`>oc:3:17dj<:188k45>2900qo?94;297?6=8r.::=4>299K716<@:837)k?:0c8 45a2:>h7dj=:188ma5=831d=>750;9~f40429086=4?{%354?7502B88=5G33:8 `6=9h1/=>h535a8ma4=831bh>4?::m27<<722wi=;<50;194?6|,8<;6<<7;I174>N4:11/i=4>a:&27c<4<k1bh?4?::kg7?6=3f;857>5;|`224<72:0;6=u+172957><@:>;7E==8:&f4?7f3-;8j7=;b:kg6?6=3`n86=44o01:>5<<uk;h87>55;294~"6>90:>l5G3528L64?3-o;6<m4$01e>6303`n96=44ie194?=nl=0;66gk5;29?j7413:17pl>c783>3<729q/=;>513`8L6273A9946*j0;05?!74n39>;6gk2;29?lb42900ei:50;9j`0<722co:7>5;n30=?6=3th:o54?:683>5}#9?:1=?m4H263?M5502.n<7?k;hf1>5<<am91<75fd583>>oc=3:17dj9:188ma1=831d=>750;9~f745290>6=4?{%354?75i2B88=5G33:8 `6=9j1/=>h534:8ma4=831bh>4?::kg0?6=3`n>6=44o01:>5<<uk8987>56;294~"6>90:>o5G3528L64?3-o;6?84$01e>63?3`n96=44ie194?=nl=0;66gk5;29?lb12900c<=6:188yg45>3:1;7>50z&225<6:j1C?9>4H20;?!c728n0ei<50;9j`6<722co87>5;hf6>5<<am<1<75fd683>>i6;00;66sm1bd94?1=83:p(<8?:00`?M5382B8>55+e182`>oc:3:17dj<:188ma2=831bh84?::kg2?6=3`n<6=44o01:>5<<uk8:o7>57;294~"6>90:>n5G3528L64?3-o;6<j4ie094?=nl:0;66gk4;29?lb22900ei850;9j`2<722e:?44?::a5fg=83=1<7>t$043>44d3A9?<6F<299'a5<6l2co>7>5;hf0>5<<am>1<75fd483>>oc>3:17dj8:188k45>2900qo?ld;290?6=8r.::=4>289K716<@:837)k?:0`8ma4=831bh>4?::kg0?6=3f;857>5;|`2gf<72>0;6=u+172957e<@:>;7E==8:&f4?403`n96=44ie194?=nl=0;66gk5;29?lb12900ei950;9l56?=831vn?<7:184>5<7s-;=<7?=c:J005=O;;20(h>51e9j`7<722co?7>5;hf7>5<<am?1<75fd783>>oc?3:17b?<9;29?xd59h0;694?:1y'536=9;30D>:?;I11<>"b83;i7)?<f;16e>oc:3:17dj<:188ma2=831d=>750;9~f77>290<6=4?{%354?75k2B88=5G33:8 `6=:>1bh?4?::kg7?6=3`n?6=44ie794?=nl?0;66gk7;29?j7413:17pl<2483>1<729q/=;>513;8L6273A9946*j0;a7?!74n39>?6gk2;29?lb42900ei:50;9l56?=831vn><=:187>5<7s-;=<7mk;I174>N4:11C9?5+13f950`<a<>1<75f6g83>>o6<90;66a>4383>>{e:k91<7;50;2x 407288j7E=;0:J06==#m90=7dj=:188ma5=831bh94?::kg1?6=3f;857>5;|`115<72<0;6=u+172957g<@:>;7E==8:&f4?7?3`n96=44ie194?=nl=0;66gk5;29?j7413:17pl=7`83>0<729q/=;>513c8L6273A9946*j0;03?lb52900ei=50;9j`1<722co97>5;n30=?6=3th::44?:283>5}#9?:1=?64H263?M5502.n<7?n;%30b?53m2co>7>5;hf0>5<<g8926=44}c055?6=;3:1<v*>61826==O;=:0D><7;%g3>75<am81<75fd283>>i6;00;66sm27094?2=83:p(<8?:00:?M5382B8>55+e181<>"6;o089;5fd383>>oc;3:17dj;:188k45>2900qo<l3;290?6=8r.::=4>289K716<@:837)k?:3:8 45a2:?>7dj=:188ma5=831bh94?::m27<<722wi>n<50;194?6|,8<;6<<7;I174>N4:11/i=4=3:&27c<4<o1bh?4?::kg7?6=3f;857>5;|`22d<72:0;6=u+172957><@:>;7E==8:&f4?443-;8j7=;e:kg6?6=3`n86=44o01:>5<<uk8=i7>54;294~"6>90:>45G3528L64?3-o;6n64$01e>6313`n96=44ie194?=nl=0;66a>3883>>{e:jl1<7:50;2x 40728827E=;0:J06==#m90h46*>3g8010=nl;0;66gk3;29?lb32900c<=6:188yg4013:1;7>50z&225<6:j1C?9>4H20;?!c72;i0ei<50;9j`6<722co87>5;hf6>5<<am<1<75fd683>>i6;00;66sm27d94?3=83:p(<8?:00b?M5382B8>55+e181=>"6;o08995fd383>>oc;3:17dj;:188ma3=831d=>750;9~f715290=6=4?{%354?75j2B88=5G33:8 `6=:h1/=>h53468ma4=831bh>4?::kg0?6=3`n>6=44ie494?=h9:31<75rb357>5<0290;w)?90;31g>N4<91C??64$d296g=nl;0;66gk3;29?lb32900ei;50;9j`3<722co;7>5;n30=?6=3th9h=4?:483>5}#9?:1=?o4H263?M5502.n<7<6;%30b?53i2co>7>5;hf0>5<<am>1<75fd483>>i6;00;66sm2e194?0=83:p(<8?:00a?M5382B8>55+e181e>"6;o088l5fd383>>oc;3:17dj;:188ma3=831bh;4?::m27<<722wi>i;50;594?6|,8<;6<<l;I174>N4:11/i=4=b:kg6?6=3`n86=44ie694?=nl<0;66gk6;29?lb02900c<=6:188yg4cj3:197>50z&225<6:h1C?9>4H20;?!c72<1/=>h535d8ma4=831bh>4?::kg0?6=3`n>6=44o01:>5<<uk8om7>57;294~"6>90:>n5G3528L64?3-o;6<k4ie094?=nl:0;66gk4;29?lb22900ei850;9j`2<722e:?44?::a753=8381<7>t$043>4433A9?<6F<299j`4<722e:?44?::a75c=8381<7>t$043>4433A9?<6F<299j`4<722e:?44?::a751=8381<7>t$043>4433A9?<6F<299j`4<722e:?44?::a75>=832;6=4?{%354?73;2B88=5G33:8^05=mrl1==47:8825?752891=94n:c8`>a<5:3;26p`nb;28jgb=82.o47:4$e;90>"ci3>0(il54:&gg?2<,mn186*ke;68 a`=<2.n=7:4$d090>"b;3>0(h:54:&f1?2<,l<186*j7;68 `>=<2.n57:4$dc90>"bj3>0(hm54:&f`?2<,lo186*jf;68 c6=<2.m=7:4$g090>"a;3>0(k:54:&e1?2<,o<186*i7;68 c>=<2.m57:4$gc90>"aj3>0(km54:&e`?2<,oo186*if;68 4672=1/==?54:&247<33-;;?7:4$027>1=#99?186*>0787?!77?3>0(<>7:59'55?=<2.:<l4;;%33f?2<,8:h695+11f90>"68l0?7)??f;68 4772=1/=<?54:&257<33-;:?7:4$037>1=#98?186*>1787?!76?3>0(<?7:59'54?=<2.:=l4;;%32f?2<,8;h695+10f90>"69l0?7)?>f;68 4472=1/=??53:&267<43-;9?7?<8:&201<6=<1/=9;5719m510=:=1e=9950:&214<6<11/=8<515:8 43?2<;0(<;6:20a?!72k390(<;k:29'76d=;:k0(>=l:21b?k54l3:0b>=j:368 4332j30e;<50;9j21<722ch97>5;ha5>5<<a8>26=44i06b>5<<a8>i6=4G14c8?l73k3:1D<;n;:k20a<722c:8h4?::k20c<722c:9=4?::k06?6=,89n6>?4n01g>5=<a::1<7*>3d805>h6;m0:76g=f;29 45b2:;0b<=k:398m7c=83.:?h4<1:l27a<432c8n7>5$01f>67<f89o6954i2c94?"6;l08=6`>3e86?>o413:1(<=j:238j45c2?10e>650;&27`<492d:?i48;:k03?6=,89n6>?4n01g>==<a:<1<7*>3d805>h6;m0276g<5;29 45b2:;0b<=k:`98m62=83.:?h4<1:l27a<e32c8?7>5$01f>67<f89o6n54i3f94?"6;l08=6`>3e8g?>o4m3:1(<=j:2f8j45c291C=8o4;h1`>5<#9:o1?i5a12f95>N6=h10e9?50;&27`<382d:?i4?;I36e>=n;o0;6)?<e;63?k74l3;0D<;n;:k73?6=,89n6984n01g>5=<a=?1<7*>3d872>h6;m0:76g;4;29 45b2=<0b<=k:398m15=83.:?h4;6:l27a<432c><7>5$01f>10<f89o6954i5d94?"6;l0?:6`>3e86?>o3m3:1(<=j:548j45c2?10e9j50;&27`<3>2d:?i48;:k7g?6=,89n6984n01g>==<a=h1<7*>3d872>h6;m0276g;a;29 45b2=<0b<=k:`98m1?=83.:?h4;6:l27a<e32c?47>5$01f>10<f89o6n54i5094?"6;l0?:6`>3e8g?>o013:1(<=j:6:8j45c2910e:950;&27`<002d:?i4>;:k42?6=,89n6:64n01g>7=<a>?1<7*>3d84<>h6;m0876g84;29 45b2>20b<=k:598m25=83.:?h488:l27a<232c3>7>5$01f>2><f89o6;54i9394?"6;l0<46`>3e84?>o?83:1(<=j:6:8j45c2110e:h50;&27`<002d:?i46;:k4a?6=,89n6:64n01g>d=<a>n1<7*>3d84<>h6;m0i76g8c;29 45b2>20b<=k:b98m2d=83.:?h488:l27a<c32c<m7>5$01f>2><f89o6h54i6094?"6;l0<46`>3e8e?>o?i3:1(<=j:9;8j45c2910e5650;&27`<?12d:?i4>;:k;3?6=,89n6574n01g>7=<a1<1<7*>3d8;=>h6;m0876g75;29 45b2130b<=k:598m=2=83.:?h479:l27a<232c2?7>5$01f>=?<f89o6;54i8094?"6;l0356`>3e84?>o>93:1(<=j:9;8j45c2110e4>50;&27`<?12d:?i46;:k;b?6=,89n6574n01g>d=<a1o1<7*>3d8;=>h6;m0i76g7d;29 45b2130b<=k:b98m=e=83.:?h479:l27a<c32c3n7>5$01f>=?<f89o6h54i9194?"6;l0356`>3e8e?>o>>3:1(<=j:878j45c2910e4:50;&27`<>=2d:?i4>;:k:=?6=,89n6464n01g>5=<a0=1<7*>3d8:<>h6;m0:76an1;29 45b2h:0b<=k:198k<`=83.:?h4n0:l27a<632e2i7>5$01f>d6<f89o6?54o8f94?"6;l0j<6`>3e80?>i>k3:1(<=j:`28j45c2=10c4l50;&27`<f82d:?i4:;:mbe?6=,89n6l>4n01g>3=<gh31<7*>3d8b4>h6;m0<76an8;29 45b2h:0b<=k:998kd1=83.:?h4n0:l27a<>32ej:7>5$01f>d6<f89o6l54o`794?"6;l0j<6`>3e8a?>if<3:1(<=j:`28j45c2j10cl=50;&27`<f82d:?i4k;:mb6?6=,89n6l>4n01g>`=<g0k1<7*>3d8b4>h6;m0m76am3;29 45b2k80b<=k:198kg7=83.:?h4m2:l27a<632ei<7>5$01f>g4<f89o6?54o`d94?"6;l0i>6`>3e80?>ifm3:1(<=j:c08j45c2=10clj50;&27`<e:2d:?i4:;:mag?6=,89n6o<4n01g>3=<gkh1<7*>3d8a6>h6;m0<76ama;29 45b2k80b<=k:998kg?=83.:?h4m2:l27a<>32ei47>5$01f>g4<f89o6l54oc594?"6;l0i>6`>3e8a?>ie>3:1(<=j:c08j45c2j10co;50;&27`<e:2d:?i4k;:ma0?6=,89n6o<4n01g>`=<ghi1<7*>3d8a6>h6;m0m76al0;29 45b2kl0b<=k:198kgc=83.:?h4mf:l27a<632eh?7>5$01f>f4<f89o6=54ob394?"6;l0h>6`>3e82?>o4;90;6)?<e;11b>h6;m0;7E?:a:9j77c=83.:?h4<2g9m56b=92B:9l54i20g>5<#9:o1??h4n01g>7=<a:8h6=4+12g977`<f89o6>54i21:>5<#9:o1?>64n01g>5=O9<k07d=<7;29 45b2:937c?<d;38L43f32c8?;4?:%30a?5402d:?i4=;I36e>=n;:?1<7*>3d807==i9:n1?6F>5`98m653290/=>k532:8j45c2=10e>=<:18'56c=;:20b<=k:498m655290/=>k532:8j45c2?10e>=>:18'56c=;:20b<=k:698yv5el3:1;vP<be9>746=9=:01>?k:063?85693;?<63<138205=:;9l1:o523309516<uz;8=7>55z?007<6;k16>4o5569>6db==>16>>95569>61g==>1v<==:1805~;4<80hj63<1185b>;49k0=j63<1b85b>;49m0=j63<1785b>;49>0=j63<1985b>;51l0<=63=9`845>;51k0<=63=9b845>;51m0<=63=b0845>;5im0<=63=ad845>;5io0<=63=b1845>;5;k0<=63=36845>;5;10<=63=38845>;5;h0<=63=4d845>;5<h0<=63=4c845>;5<j0<=63=4e845>;4:<0o863<09802>;48108963<09800>;48108?63<0981`>;4810?n63<0987e>;4810?563<0987<>;4810?>63<098:2>;48102863<098:=>;48102;63<09806a=:;921??m4=22;>42>349;47?;a:?04=<6<o16?=651428yv7?93:1?v3>8`8207=::h:1h9522c19`1=z{8296=4<{<3;f?73:279m=4k2:?1f6<c:2wx=5=50;1x94>d28>970<n2;f7?84e=3n?7p}>8583>6}:91n1=9<4=3c1>a4<5;h>6i<4}r3;1?6=;r7:4h4>439>6d2=l=16>o95d59~w4>12908w0?7f;376>;5i=0o>63=b68g6>{t91=1<7=t=0;3>425348j:7j;;<0a=?b33ty:454?:2y>5<7=9=801?o9:e0897d>2m80q~?79;297~;61;0:8?522`:9`7=::kh1h?5rs0fb>5<4s4;n?7?;2:?17a<c=2799=4k2:p5ad=839p1<k;:061?844l3n870<:0;f0?xu6lj0;6>u21d79514<5;9m6i;4=371>a4<uz;oh7>53z?2a3<6<;16>>h5d29>604=l:1v<jj:18087b?3;?>63=408g1>;5==0o96s|1ed94?5|58o36<:=;<075?b4348>87j<;|q2a5<72:q6=h75150897242m?01?;9:e78yv7b93:1?v3>e`8207=::=91h>522449`6=z{8o96=4<{<3ff?73:279884k3:?11=<c;2wx>n>50;0x97e728>97S=m2:p75e=83;9w0<8b;76?840k3?>70<8d;76?840m3?>70<8f;76?84?83?>70<71;76?84?:3?>70<7c;76?84?l3?>70<7e;76?84?n3?>70<60;76?84>93?>70<62;76?84>;3?>70<64;76?842n3;856s|24f94?2|5;?o6<:=;<06b?b4349;n7j;;<06f?b43ty99h4?:3y>60c=9=80R>ol;|q0<g<72;qU?5l4=22;><g<uz92:7>52z\0=3=:;921m?5rs2c2>5<5sW9j=63<098b7>{t;h?1<7<t^2c6?85703k?7p}<a783>7}Y;h<01>>7:`78yv5f?3:1>vP<a69>75>=i?1v>o7:181[5f0278<54n7:p7d?=838pR>o6;<13<?g?3ty8ml4?:3y]7dg<5::36l74}r1bf?6=:rT8mo5231:9ed=z{:2h6=4={_1;g>;48102n6s|39f94?4|V:2o70=?8;;`?xu40l0;6?uQ39g8966?20n0q~=7f;296~X40o16?=659d9~w6?72909wS=60:?04=<>n2wx?4?50;0xZ6?6349;47o>;|q0=7<72;qU?4<4=22;>de<uz92?7>52z\0=6=:;921n95rs2;7>5<5sW92863<098a1>{t;0?1<7<t^2;6?85703h=7p}<9683>7}Y;0=01>>7:c58yv5>03:1>vP<999>75>=j11v>76:181[5>1278<54m9:p7<g=838pR>7n;<13<?df3ty85o4?:3y]7<d<5::36ol4}r1:g?6=:rT85n5231:9ff=z{:3o6=4={_1:`>;4810jh6s|38g94?4|V:3n70=?8;cf?xu41o0;6?uQ38d8966?2hl0q~=n0;296~X4i916?=65b19~w6g52909wS=n2:?04=<e92wx?l:50;0xZ6g3349;47l<;|q054<72=q6>oh5152897e728>;70=>1;376>;49;0=j6s|31d94?4|5::m6<:=;<0:1?b43ty8=84?:06x973c28>;70<:e;374>;4910:8?5226`92g=::>i1:o5226f92g=::>o1:o5226d92g=::1:1:o5229392g=::181:o5229a92g=::1n1:o5229g92g=::1l1:o5228292g=::0;1:o5228092g=::091:o5228692g=z{:;?6=4=5z?052<6<;16=4m56c9>5<b=>k16=4k56c9>5<`=>k16=l>56c9>5d7=>k16=l<56c9>5d5=>k16=l:56c9>651=>k16>=656c9>65?=>k16>=o56c9>65d=>k16>=m56c9>65b=>k16>=k56c9>65`=>k16>?o56c9>67d=>k16>?m56c9>67b=>k16>?k56c9>67`=>k16>>>56c9>667=>k16>><56c9>5`5=>k16=h:56c9>5`3=>k16=h856c9>5`1=>k16=h656c9>5`?=>k16=ho56c9>5`d=>k1v>?n:182=~;49j0:8?522ea9516<5;no6;l4=3ff>3d<5;nm6;l4=3g3>3d<5;o:6;l4=3g1>3d<5;o86;l4=3gg>427348ni78m;<0fb?0e348m<78m;<0e5?0e348m>78m;<0e7?0e348m878m;<0e1?0e348mh78m;<0ea?0e348mj78m;<134?0e349;=78m;<136?0e349;?78m;|q05<<72;?p1>?m:061?87a=3<i70?i6;4a?87a?3<i70?i8;4a?87a13<i70?ia;4a?87aj3<i70?ic;4a?87al3<i70?ne;4a?87fn3<i70?m0;4a?87e93<i70?m2;4a?87e;3<i70?m4;4a?87e=3<i70?m6;4a?87c93<i70?k2;4a?87c;3<i70?k4;4a?87c=3<i70?k6;4a?87c?3<i70?k8;4a?87c13<i70?7a;4a?87?j3<i70?7c;4a?87?l3<i70?7e;4a?87?n3<i70?60;4a?87>93<i70?62;4a?xu4k90;6>uQ3b2897e62m801?7::e08yv5e13:18vP<b89>60`=l;16?=l5d39>60d=l;1v>>n:181857j3;8563<098`1>{t;k21<7=i{_1a<>;5=m0>863=5d860>;49m0>863<17860>;49>0>863<19860>;49l0>863<1g860>;5?k0>863=7b860>;5?m0>863=7d860>;5?o0>863=81860>;5080>863=83860>;50j0>863=8e860>;50l0>863=8g860>;5190>863=90860>;51;0>863=92860>;51=0>863>9b860>;61m0>863>9d860>;61o0>863>a1860>;6i80>863>a3860>;6i:0>863>a5860>;58>0>863=09860>;5800>863=0`860>;58k0>863=0b860>;58m0>863=0d860>;58o0>863=2`860>;5:k0>863=2b860>;5:m0>863=2d860>;5:o0>863=31860>;5;80>863=33860>;6m:0>863>e5860>;6m<0>863>e7860>;6m>0>863>e9860>;6m00>863>e`860>;6mk0>863<09856>{t;9n1<7?j{<0gg?32348oh7;:;<0ga?32348oj7;:;<0f4?32348n=7;:;<0f6?32348n?7;:;<0e`?32348mi7;:;<0eb?32349;<7;:;<135?32349;>7;:;<137?32348nh7;:;<0fa?32348nj7;:;<0e4?32348m=7;:;<0e6?32348m?7;:;<0e0?32348m97;:;<0`5?741278<54<359>75>=;:901>>7:211?8570398=63<098`2>{t;kl1<7:6{_1ab>;5jo0>863=c1860>;4990>863<1c860>;49j0>863<10860>;4::0>863<13860>;4:=0>863<0g860>;5lj0>863=de860>;5ll0>863=dg860>;5m90>863=e0860>;5m;0>863=e2860>;5mm0>863=ed860>;5mo0>863=f1860>;5n80>863=f3860>;5n:0>863=f5860>;5n<0>863=fe860>;5nl0>863=fg860>;4890>863<00860>;48;0>863<02860>;6n<0>863>f7860>;6n>0>863>f9860>;6n00>863>f`860>;6nk0>863>fb860>;6nm0>863>ad860>;6io0>863>b1860>;6j80>863>b3860>;6j:0>863>b5860>;6j<0>863>b7860>;6l80>863>d3860>;6l:0>863>d5860>;6l<0>863>d7860>;6l>0>863>d9860>;6l00>863>8`860>;60k0>863>8b860>;60m0>863>8d860>;60o0>863>91860>;6180>863>93860>;4:;0>863<09850>{t:191<7jt=3:`>4253488h7j;;<355?b5348==7j=;<056?b3348=i7j;;<04=?b1348=j7j:;<046?b1348<87j8;<13a?b6349;47=8;<064?b23ty9494?:4y>6=b=9=801?=k:e0894052m801<8>:e18966?2:20q~<75;291~;50l0:8?5222d9`1=:9?91h?521709`6=:;921?45rs3:5>5<2s483j7?;2:?17c<c:27::94k2:?226<c;278<54<a:p6=1=83?p1?7?:061?84393n?70?95;f1?871<3n870=?8;1a?xu5010;68u22839514<5;>:6i<4=045>a4<58<>6i=4=22;>7c<uz8357>55z?1=7<6<;16>9=5d59>531=l;16=;85d29>75>=:o1v?6n:18684>;3;?>63=428g6>;6>10o>63>668g7>;48108<6s|29`94?3|5;3?6<:=;<3b0?0a348?97j=;<35<?b4349;47==;|q056<72=q6?<851508966?28>o70=?8;37a>;48k0o?6s|37c94?4|V:<j70=?8;51?xu4?<0;6?uQ3678966?2>k0q~=70;296~X40916?=657c9~w6>32909wS=74:?04=<0k2wx?5;50;0xZ6>2349;479k;|q0<3<72;qU?584=22;>2c<uz93;7>52z\0<2=:;921;k5rs2:;>5<5sW93463<098;4>{t;131<7<t^2::?857032:7p}<8`83>7}Y;1k01>>7:908yv51j3:1>vP<6c9>75>=?:1v>8l:181[51k278<5484:p73b=838pR>8k;<13<?123ty8:h4?:3y]73c<5::36:84}r15b?6=:rT8:k5231:932=z{:=;6=4={_144>;4810<56s|36394?4|V:=:70=?8;:0?xu4?;0;6?uQ3608966?21h0q~=83;296~X4?:16?=658b9~w6132909wS=84:?04=<?l2wx?:850;0xZ611349;476j;|q032<72;qU?:94=22;>=`<uz9<47>52z\03==:;9215=5rs25:>5<5sW9<563<098:5>{t;>k1<7<t^25b?85703397p}<7c83>7}Y;>h01>>7:818yv50k3:1>vP<7b9>75>=0=1v>9k:181[50l278<5475:p72c=838pR>9j;<13<?>13ty8;k4?:3y]72`<5::36594}r1;5?6=:rT84<5231:9<==z{:286=4={_1;7>;48103m6s|2g494?2|5;lo6<:=;<35f?b534;=m7j<;<13<?2b3ty9j:4?:5y>6cc=9=801<8l:e08940e2m901>>7:5d8yv4a03:18v3=fg8207=:9?n1h?5217a9`6=:;9219=5rs3d:>5<3s49;<7?;2:?22`<c:27::i4k3:?04=<3;2wx>ko50;6x966628>970?9f;f1?871m3n870=?8;67?xu5nk0;69u23109514<58=;6i<4=04e>a5<5::369;4}r0eg?6=<r78<>4>439>5cb=>o16=:>5d29>75>=<>1v?8?:18184?k3<m70=?e;30=>{t:?91<7ot=35a>4253483h78i;<055?b4348=>7j<;<05a?b5348<57j<;<05b?b3348<>7j:;<040?b1348><7j;;|q121<720q6>:m5150897>b2?l01?;=:e6897052m801?8j:e18971>2m>01?8i:e1897152m901?9;:e18yv41=3:15v3=7e8207=::1l1:k5226:9`3=::><1h85226;9`0=::?l1h?522609`1=::>>1h9522409`0=z{;<=6=47{<04a?73:2795=49f:?111<c<279;54k5:?133<c<279;l4k2:?137<c:279;94k5:p631=83=p1?9i:061?84>93<m70<:4;f1?84003n?70<86;f0?840i3n870<84;f1?xu5>10;6;u22929514<5;396;h4=375>a2<5;=36i=4=355>a4<5;=j6i:4}r05=?6==r794<4>439>6<5=>o16>885d39>62>=l;16>:o5d49~w70f290?w0<72;376>;51=0=j63=598g6>;5?00o>6s|24c94?5|5;?o6;h4=37f>3`<5;?i6<=6;|q11f<72;q6>9k512;8973e2m?0q~<:9;296~;5;k0:?45224`9`1=z{;i?6=4k{<0gg?73:279ih49f:?1f6<c;27::44k2:?1g6<c;279o?4k2:?22d<c:279ok4k2:?1`5<c<279h>4k5:?1`0<c>279hl4k3:?042<c92wx>n;50;;x97bc28>970<jf;4e?84e=3n>70<l3;f1?84dn3n870<k0;f0?84c;3n870<k5;f0?84ci3n?7p}=c783><}::mo1=9<4=3d3>3`<5;h>6i=4=3f:>a0<5;n<6i;4=3f3>a4<5;n86i:4=3f6>a2<5;nj6i;4}r0`3?6=0r79hk4>439>6c7=>o16>o95d49>6a?=l<16>i95d59>6a5=l;16>i;5d49>6ag=l?1v?m7:18484b83;?>63=f385b>;5j>0o?63=d88g0>;5l>0o?63=d48g6>;5lk0o>6s|2b;94?0|5;o:6<:=;<0e7?0a348i57j:;<0g=?b4348o;7j=;<0gf?b43ty9ol4?:4y>6`4=9=801?h;:7d897d>2m901?j6:e0897be2m>0q~<lb;290~;5m:0:8?522g792c=::kh1h>522ec9`7=z{;o?6=4l{<0f`?73:279m=4k5:?1f6<c=27::44k3:?1g6<c<279o?4k3:?1gc<c<279h=4k5:?1`6<c>279h84k7:?1`g<c=278<84k1:p6`3=838p1?kj:061?84f83n87p}=e783>6}::ll1=9<4=3dg>3`<5;k96i;4}r0f3?6=;r79j=4>439>6cc=>o16>l<5d29~w7c?2908w0<i1;376>;5no0=j63=a58g1>{t:l31<7=t=3d1>425349;<78i;<0b0?b43ty9il4?:2y>6c5=9=801>>>:7d897g12m?0q~<jb;297~;5n=0:8?5231092c=::h<1h>5rs3g`>5<4s48m97?;2:?046<1n279m54k3:p6g`=839p1?li:061?84d93n870<65;f7?xu5jm0;6>u22cd92c=::j:1:k52287956?<uz8ii7>52z?1f4<6;016>4;5d79~w7dd2909w0<6e;30=>;51<0o96s|33294?2|5:;=6<:?;<123?738278=54>419>777=9:30q~==6;297~;49k0:8=5230a9516<5:8<6<=6;|q05a<72:q6?<j51508967b2?l01><>:e08yv56n3:1>v3<1g8207=:;;;1h>5rs23f>5<4s49:h7;:;<12a?73:278=k49f:p774=83>p1><<:7d896402m801><::e18964528>97p}<2583>7}:;;>1=9<4=204>a5<uz99?7>53z?066<6<;16??:56g9>773=l;1v>?=:181856:3;?>63<0g85b>{t;8:1<7<t=233>425349:=78i;|q1=<<72;q6>4k5569>6<b=9:30q~<68;296~;51j0:?45228f912=z{;3<6=4={<0:f?7412795n4:7:p6<0=838p1?7n:01:?84>j3?<7p}=a483>7}::0n1=8=4=3c5>45>3ty9m>4?:3y>6<e=9<901?o;:01:?xu5i80;6?u228`9505<5;k96<=6;|q1=c<72;q6>4o5141897g728927p}=a683>7}::0o1=8=4=3c;>45>3ty9mn4?:3y>6g7==>16>o>512;8yv4fj3:1>v3=ag827<=::k:19:5rs3cb>5<5s48ji7?<9:?1ec<2?2wx>l750;0x97gc289270<ne;74?xu5j10;6?u22c29505<5;h26<=6;|q1f3<72;q6>lh5141897d028927p}=b583>7}::ho1=8=4=3`6>45>3ty9n?4?:3y>6db=9<901?l<:01:?xu5jh0;6?u22c39505<5;hi6<=6;|q173<72;q6>>l5569>66g=9:30q~<<5;296~;5;00:?45222c912=z{;9?6=4={<00<?741279?44:7:p665=838p1?=8:01:?84403?<7p}=4383>7}:::k1=8=4=360>45>3ty98=4?:3y>66?=9<901?:>:01:?xu5;l0;6?u222:9505<5;9m6<=6;|q17f<72;q6>>951418975c28927p}=4583>7}:::h1=8=4=366>45>3ty9844?:3y>61c==>16>9j512;8yv4303:1>v3=4b827<=::=n19:5rs364>5<5s48?n7?<9:?10f<2?2wx>9850;0x972f289270<;b;74?xu5=<0;6?u225f9505<5;?=6<=6;|q116<72;q6>9m51418973328927p}=5083>7}::=h1=8=4=371>45>3ty98k4?:3y>61g=9<901?;?:01:?xu5=>0;6?u225g9505<5;?36<=6;|q135<72:q6>:65d69>620=l?16>;k512;8yv41j3:1>v3=7c85b>;5>80:?45rs34`>5<5s48<o78i;<056?7412wx>;j50;0x971c2?l01?8i:01:?xu5?80;6?u226g92c=::>81=>74}r047?6=:r79;k49f:?131<6;01v?9::18184?83<m70<86;30=>{t:>=1<7<t=3:2>3`<5;=36<=6;|q13<<72;q6>5<56g9>62?=9:30q~<k1;297~;5l00o;63=d68g2>;5ko0:?45rs3a`>5<5s48oo78i;<0`6?7412wx>nj50;0x97bc2?l01?m<:01:?xu5kl0;6?u22eg92c=::m:1=>74}r0g6?6=:r79hk49f:?1`6<6;01v?j;:18184b83<m70<k5;30=>{t:m<1<7<t=3g2>3`<5;n<6<=6;|q1`=<72;q6>h<56g9>6a?=9:30q~<ka;296~;5m:0=j63=d`827<=z{;;i6=4={<3f0?0a348:57?<9:p67?=838p1<k::7d8974?28927p}=2683>7}:9l<1:k52234956?<uz8997>52z?2a2<1n279>94>389~w7442908w0?j8;4e?845:3;8563=1b8g3>{t:;:1<7<t=0g:>3`<5;8:6<=6;|q15`<72:q6=ho56g9>64`=9:301?<7:e58yv7dm3:1>v3>8c85b>;6kj0:?45rs0aa>5<5s4;3o78i;<3`e?7412wx=n750;0x94>c2?l01<m7:01:?xu6k>0;6?u219g92c=:9j<1=>74}r3`1?6=;r7:4k49f:?2g1<6;016=nh5d69~w4e52909w0?60;4e?87d;3;856s|1b294?5|583:6;h4=0a2>45>34;hm7j8;|q234<72;q6=4m56g9>537=9:30q~?82;296~;61m0=j63>63827<=z{8=86=4={<3:a?0a34;=?7?<9:p522=838p1<7i:7d8940328927p}>7483>7}:9h:1:k52177956?<uz;<:7>52z?2e4<1n27::;4>389~w4102909w0?n2;4e?871?3;856s|16:94?4|58k86;h4=04;>45>3ty:;44?:3y>5c3=>o16=;7512;8yv70i3:1>v3>f785b>;6>h0:?45rs05a>5<5s4;m;78i;<35f?7412wx=:m50;0x94`?2?l01<8l:01:?xu6?m0;6?u21g;92c=:9?n1=>74}r34a?6=:r7:jl49f:?22`<6;01v<9i:18187aj3<m70?9f;30=>{t91:1<7<t=0d`>3`<58=;6<=6;|q15a<72;q6=h=56g9>64e=9:30q~?k0;296~;60h0=j63>cg827<=z{8386=4={<3:g?73:27:mh49f:p5<2=838p1<7k:061?87fn3<m7p}>9483>7}:90o1=9<4=0`3>3`<uz;2:7>52z?2=c<6<;16=o?56g9~w4?02909w0?n0;376>;6j;0=j6s|18:94?4|58k:6<:=;<3a7?0a3ty:544?:3y>5d4=9=801<l;:7d8yv7>i3:1>v3>a28207=:9k?1:k5rs0;a>5<5s4;j87?;2:?2f3<1n2wx><>50;0x974f28>970<>c;f5?xu5980;6>u223`9514<5;;h6i=4=33:>a5<uz8:>7>54z?16f<6<;16><m5d39>67>=l;16><75d39~w774290>w0<=d;376>;5:?0o>63=1b8g1>;5:10o863=188g1>{t:8>1<78t=30f>425348987j=;<012?b4348:o7j;;<01<?b4348:57j;;|q150<72?q6>?h5150897452m801?<;:e1897412m>01?<7:e48977f2m80q~<>6;293~;5;90:8?522339`1=::;81h>522369`1=::;<1h85223:9`0=::831h;5rs334>5<0s488=7?;2:?15c<c:279><4k2:?167<c<279>94k5:?163<c>279=l4k4:p64>=832p1?==:061?87bj3<m70<>f;f0?84593n870<=2;f6?845<3n=70<=6;f4?846i3n87p}>fd83>7}::9=1=9<4=30b>3`<uz;mj7>52z?14=<6<;16>?l56g9~w7672909w0<?9;376>;5:j0=j6s|21394?4|5;:j6<:=;<01`?0a3ty9<?4?:3y>65d=9=801?<j:7d8yv47;3:1>v3=0b8207=::;l1:k5rs327>5<5s48;h7?;2:?175<1n2wx>=;50;0x976b28>970<<1;4e?xu58?0;6?u221d9514<5;996;h4}r3fg?6=:r7:j84>439>651=>o1v<kk:18187a>3;?>63=0985b>{t9lo1<7<t=0d4>425348;578i;|q2ac<72;q6=k651508976f2?l0q~?i0;296~;6n00:8?5221`92c=z{8l:6=4={<3ee?73:279<n49f:p5c4=838p1<hm:061?847l3<m7p}>f283>7}:9oi1=9<4=32f>3`<uz;m87>52z?2ba<6<;16>=h56g9~w4d02909w0?k1;376>;6ko0o:6s|1c:94?5|58n96<:=;<3`b?b434;ho7j<;|q2f<<72=q6=i=5150894ea2m801<mn:e0894ed2m80q~?ma;291~;6l=0:8?521b:9`7=:9jl1h8521bc9`1=:9ji1h85rs0`a>5<1s4;o97?;2:?2g3<c:27:o54k3:?2gc<c<27:ol4k3:?2gf<c<2wx=om50;4x94b128>970?l4;f1?87d>3n870?l8;f7?87di3n=70?ld;f1?xu6jm0;6:u21e59514<58i86i:4=0a7>a5<58i=6i:4=0a;>a3<58ij6i;4=0a`>a0<uz;ii7>57z?2`=<6<;16=n?5d39>5f5=l;16=n:5d59>5f0=l<16=n65d79>5fb=l=1v<li:18;87c13;?>63>9385b>;6k80o?63>c28g7>;6k=0o963>c78g2>;6k10o;63>ce8g7>{t9h?1<7<t=0cf>42534;o=78i;|q2e3<72;q6=lh5150894b52?l0q~?n7;296~;6j90:8?521e192c=z{8k36=4={<3a5?73:27:h949f:p5d?=838p1<l=:061?87c=3<m7p}>a`83>7}:9k91=9<4=0f5>3`<uz;jn7>52z?2f1<6<;16=i956g9~w4gd2909w0?m5;376>;6l10=j6s|1`f94?4|58h=6<:=;<3g=?0a3ty8<94?:2y>6`b=>o16?=;512;8966?2=i0q~=?6;296~;48>0:?45231:90a=z{8986=4={<3``?74127:on4k7:p562=838p1??n:01:?84613n<7p}<2483>7}:;;?1=>74=201>3`<uz;897>52z?13d<6;016>:75d69~w4512909w0<kb;30=>;5lh0o;6srn4aa>5<6sA9946sa5ba94?7|@:837p`:ce83>4}O;;20qc;le;295~N4:11vb8mi:182M5502we9i>50;3xL64?3td>h<4?:0yK77><ug?o>7>51zJ06==zf<n86=4>{I11<>{i=m>1<7?tH20;?xh2l<0;6<uG33:8yk3c>3:1=vF<299~j0b0290:wE==8:m1a>=83;pD><7;|l6`<<728qC??64}o7ge?6=9rB8>55rn4fa>5<6sA9946sa5ea94?7|@:837p`:de83>4}O;;20qc;ke;295~N4:11vb8ji:182M5502we9h>50;3xL64?3td>i<4?:0yK77><ug?n>7>51zJ06==zf<o86=4>{I11<>{i=l>1<7?tH20;?xh2m<0;6<uG33:8yk3b>3:1=vF<299~j0c0290:wE==8:m1`>=83;pD><7;|l6a<<728qC??64}o7fe?6=9rB8>55rn4ga>5<6sA9946sa5da94?7|@:837p`:ee83>4}O;;20qc;je;295~N4:11vb8ki:182M5502we9k>50;3xL64?3td>j<4?:0yK77><ug?m>7>51zJ06==zf<l86=4>{I11<>{i=o>1<7?tH20;?xh2n<0;6<uG33:8yk3a>3:1=vF<299~j0`0290:wE==8:m1c>=83;pD><7;|l6b<<728qC??64}o7ee?6=9rB8>55rn4da>5<6sA9946sa5ga94?7|@:837p`:fe83>4}O;;20qc;ie;295~N4:11vb8hi:182M5502we:=>50;3xL64?3td=<<4?:0yK77><ug<;>7>51zJ06==zf?:86=4>{I11<>{i>9>1<7?tH20;?xh18<0;6<uG33:8yk07>3:1=vF<299~j360290:wE==8:m25>=83;pD><7;|l54<<728qC??64}o43e?6=9rB8>55rn72a>5<6sA9946sa61a94?7|@:837p`90e83>4}O;;20qc8?e;295~N4:11vb;>i:182M5502we:<>50;3xL64?3td==<4?:0yK77><ug<:>7>51zJ06==zf?;86=4>{I11<>{i>8>1<7?tH20;?xh19<0;6<uG33:8yk06>3:1=vF<299~j370290:wE==8:m24>=83;pD><7;|l55<<728qC??64}o42e?6=9rB8>55rn73a>5<6sA9946sa60a94?7|@:837p`91e83>4}O;;20qc8>e;295~N4:11vb;?i:182M5502we:?>50;3xL64?3td=><4?:0yK77><ug<9>7>51zJ06==zf?886=4>{I11<>{i>;>1<7?tH20;?xh1:<0;6<uG33:8yk05>3:1=vF<299~j340290:wE==8:m27>=83;pD><7;|l56<<728qC??64}o41e?6=9rB8>55rn70a>5<6sA9946sa63a94?7|@:837p`92e83>4}O;;20qc8=e;295~N4:11vb;<i:182M5502we:>>50;3xL64?3td=?<4?:0yK77><ug<8>7>51zJ06==zf?986=4>{I11<>{i>:>1<7?tH20;?xh1;<0;6<uG33:8yk04>3:1=vF<299~j350290:wE==8:m26>=83;pD><7;|l57<<728qC??64}o40e?6=9rB8>55rn71a>5<6sA9946sa62a94?7|@:837p`93e83>4}O;;20qc8<e;295~N4:11vb;=i:182M5502we:9>50;3xL64?3td=8<4?:0yK77><ug<?>7>51zJ06==zf?>86=4>{I11<>{i>=>1<7?tH20;?xh1<<0;6<uG33:8yk03>3:1=vF<299~j320290:wE==8:m21>=83;pD><7;|l50<<728qC??64}o47e?6=9rB8>55rn76a>5<6sA9946sa65a94?7|@:837p`94e83>4}O;;20qc8;e;295~N4:11vb;:i:182M5502we:8>50;3xL64?3td=9<4?:0yK77><ug<>>7>51zJ06==zf??86=4>{I11<>{i><>1<7?tH20;?xh1=<0;6<uG33:8yk02>3:1=vF<299~j330290:wE==8:m20>=83;pD><7;|l51<<728qC??64}o46e?6=9rB8>55rn77a>5<6sA9946sa64a94?7|@:837p`95e83>4}O;;20qc8:e;295~N4:11vb;;i:182M5502we:;>50;3xL64?3td=:<4?:0yK77><ug<=>7>51zJ06==zf?<86=4>{I11<>{i>?>1<7?tH20;?xh1><0;6<uG33:8yk01>3:1=vF<299~j300290:wE==8:m23>=83;pD><7;|l52<<728qC??64}o45e?6=9rB8>55rn74a>5<6sA9946sa67a94?7|@:837p`96e83>4}O;;20qc89e;295~N4:11vb;8i:182M5502we::>50;3xL64?3td=;<4?:0yK77><ug<<>7>51zJ06==zf?=86=4>{I11<>{i>>>1<7?tH20;?xh1?<0;6<uG33:8yk00>3:1=vF<299~j310290:wE==8:m22>=83;pD><7;|l53<<728qC??64}o44e?6=9rB8>55rn75a>5<6sA9946sa66a94?7|@:837p`97e83>4}O;;20qc88e;295~N4:11vb;9i:182M5502we:5>50;3xL64?3td=4<4?:0yK77><ug<3>7>51zJ06==zf?286=4>{I11<>{i>1>1<7?tH20;?xh10<0;6<uG33:8yk0?>3:1=vF<299~j3>0290:wE==8:m2=>=83;pD><7;|l5<<<728qC??64}o4;e?6=9rB8>55rn7:a>5<6sA9946sa69a94?7|@:837p`98e83>4}O;;20qc87e;295~N4:11vb;6i:182M5502we:4>50;3xL64?3td=5<4?:0yK77><ug<2>7>51zJ06==zf?386=4>{I11<>{i>0>1<7?tH20;?xh11<0;6<uG33:8yk0>>3:1=vF<299~j3?0290:wE==8:m2<>=83;pD><7;|l5=<<728qC??64}o4:e?6=9rB8>55rn7;a>5<6sA9946sa68a94?7|@:837p`99e83>4}O;;20qc86e;295~N4:11vb;7i:182M5502we:l>50;3xL64?3td=m<4?:0yK77><ug<j>7>51zJ06==zf?k86=4>{I11<>{i>h>1<7?tH20;?xh1i<0;6<uG33:8yk0f>3:1=vF<299~j3g0290:wE==8:m2d>=83;pD><7;|l5e<<728qC??64}o4be?6=9rB8>55rn7ca>5<6sA9946sa6`a94?7|@:837p`9ae83>4}O;;20qc8ne;295~N4:11vb;oi:182M5502we:o>50;3xL64?3td=n<4?:0yK77><ug<i>7>51zJ06==zf?h86=4>{I11<>{i>k>1<7?tH20;?xh1j<0;6<uG33:8yk0e>3:1=vF<299~j3d0290:wE==8:m2g>=83;pD><7;|l5f<<728qC??64}o4ae?6=9rB8>55rn7`a>5<6sA9946sa6ca94?7|@:837p`9be83>4}O;;20qc8me;295~N4:11vb;li:182M5502we:n>50;3xL64?3td=o<4?:0yK77><ug<h>7>51zJ06==zf?i86=4>{I11<>{i>j>1<7?tH20;?xh1k<0;6<uG33:8yk0d>3:1=vF<299~j3e0290:wE==8:m2f>=83;pD><7;|l5g<<728qC??64}o4`e?6=9rB8>55rn7aa>5<6sA9946sa6ba94?7|@:837p`9ce83>4}O;;20qc8le;295~N4:11vb;mi:182M5502we:i>50;3xL64?3td=h<4?:0yK77><ug<o>7>51zJ06==zf?n86=4>{I11<>{i>m>1<7?tH20;?xh1l<0;6<uG33:8yk0c>3:1=vF<299~j3b0290:wE==8:m2a>=83;pD><7;|l5`<<728qC??64}o4ge?6=9rB8>55rn7fa>5<6sA9946sa6ea94?7|@:837p`9de83>4}O;;20qc8ke;295~N4:11vb;ji:182M5502we:h>50;3xL64?3td=i<4?:0yK77><ug<n>7>51zJ06==zf?o86=4>{I11<>{i>l>1<7?tH20;?xh1m<0;6<uG33:8yk0b>3:1=vF<299~j3c0290:wE==8:m2`>=83;pD><7;|l5a<<728qC??64}o4fe?6=9rB8>55rn7ga>5<6sA9946sa6da94?7|@:837p`9ee83>4}O;;20qc8je;295~N4:11vb;ki:182M5502we:k>50;3xL64?3td=j<4?:0yK77><ug<m>7>51zJ06==zf?l86=4>{I11<>{i>o>1<7?tH20;?xh1n<0;6<uG33:8yk0a>3:1=vF<299~j3`0290:wE==8:m2c>=83;pD><7;|l5b<<728qC??64}o4ee?6=9rB8>55rn7da>5<6sA9946sa6ga94?7|@:837p`9fe83>4}O;;20qc8ie;295~N4:11vqpsO@By;76<?mm:28>>r@A@x4xFGXrwKL
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.vhd b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.vhd
deleted file mode 100644
index 1c37393..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.vhd
+++ /dev/null
@@ -1,282 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2012 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
--- You must compile the wrapper file async_fifo_512x32.vhd when simulating
--- the core, async_fifo_512x32. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-LIBRARY XilinxCoreLib;
--- synthesis translate_on
-ENTITY async_fifo_512x32 IS
-  PORT (
-    rst : IN STD_LOGIC;
-    wr_clk : IN STD_LOGIC;
-    rd_clk : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END async_fifo_512x32;
-
-ARCHITECTURE async_fifo_512x32_a OF async_fifo_512x32 IS
--- synthesis translate_off
-COMPONENT wrapped_async_fifo_512x32
-  PORT (
-    rst : IN STD_LOGIC;
-    wr_clk : IN STD_LOGIC;
-    rd_clk : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END COMPONENT;
-
--- Configuration specification
-  FOR ALL : wrapped_async_fifo_512x32 USE ENTITY XilinxCoreLib.fifo_generator_v8_3(behavioral)
-    GENERIC MAP (
-      c_add_ngc_constraint => 0,
-      c_application_type_axis => 0,
-      c_application_type_rach => 0,
-      c_application_type_rdch => 0,
-      c_application_type_wach => 0,
-      c_application_type_wdch => 0,
-      c_application_type_wrch => 0,
-      c_axi_addr_width => 32,
-      c_axi_aruser_width => 1,
-      c_axi_awuser_width => 1,
-      c_axi_buser_width => 1,
-      c_axi_data_width => 64,
-      c_axi_id_width => 4,
-      c_axi_ruser_width => 1,
-      c_axi_type => 0,
-      c_axi_wuser_width => 1,
-      c_axis_tdata_width => 64,
-      c_axis_tdest_width => 4,
-      c_axis_tid_width => 8,
-      c_axis_tkeep_width => 4,
-      c_axis_tstrb_width => 4,
-      c_axis_tuser_width => 4,
-      c_axis_type => 0,
-      c_common_clock => 0,
-      c_count_type => 0,
-      c_data_count_width => 9,
-      c_default_value => "BlankString",
-      c_din_width => 32,
-      c_din_width_axis => 1,
-      c_din_width_rach => 32,
-      c_din_width_rdch => 64,
-      c_din_width_wach => 32,
-      c_din_width_wdch => 64,
-      c_din_width_wrch => 2,
-      c_dout_rst_val => "0",
-      c_dout_width => 32,
-      c_enable_rlocs => 0,
-      c_enable_rst_sync => 1,
-      c_error_injection_type => 0,
-      c_error_injection_type_axis => 0,
-      c_error_injection_type_rach => 0,
-      c_error_injection_type_rdch => 0,
-      c_error_injection_type_wach => 0,
-      c_error_injection_type_wdch => 0,
-      c_error_injection_type_wrch => 0,
-      c_family => "virtex6",
-      c_full_flags_rst_val => 1,
-      c_has_almost_empty => 0,
-      c_has_almost_full => 0,
-      c_has_axi_aruser => 0,
-      c_has_axi_awuser => 0,
-      c_has_axi_buser => 0,
-      c_has_axi_rd_channel => 0,
-      c_has_axi_ruser => 0,
-      c_has_axi_wr_channel => 0,
-      c_has_axi_wuser => 0,
-      c_has_axis_tdata => 0,
-      c_has_axis_tdest => 0,
-      c_has_axis_tid => 0,
-      c_has_axis_tkeep => 0,
-      c_has_axis_tlast => 0,
-      c_has_axis_tready => 1,
-      c_has_axis_tstrb => 0,
-      c_has_axis_tuser => 0,
-      c_has_backup => 0,
-      c_has_data_count => 0,
-      c_has_data_counts_axis => 0,
-      c_has_data_counts_rach => 0,
-      c_has_data_counts_rdch => 0,
-      c_has_data_counts_wach => 0,
-      c_has_data_counts_wdch => 0,
-      c_has_data_counts_wrch => 0,
-      c_has_int_clk => 0,
-      c_has_master_ce => 0,
-      c_has_meminit_file => 0,
-      c_has_overflow => 0,
-      c_has_prog_flags_axis => 0,
-      c_has_prog_flags_rach => 0,
-      c_has_prog_flags_rdch => 0,
-      c_has_prog_flags_wach => 0,
-      c_has_prog_flags_wdch => 0,
-      c_has_prog_flags_wrch => 0,
-      c_has_rd_data_count => 0,
-      c_has_rd_rst => 0,
-      c_has_rst => 1,
-      c_has_slave_ce => 0,
-      c_has_srst => 0,
-      c_has_underflow => 0,
-      c_has_valid => 0,
-      c_has_wr_ack => 0,
-      c_has_wr_data_count => 0,
-      c_has_wr_rst => 0,
-      c_implementation_type => 2,
-      c_implementation_type_axis => 1,
-      c_implementation_type_rach => 1,
-      c_implementation_type_rdch => 1,
-      c_implementation_type_wach => 1,
-      c_implementation_type_wdch => 1,
-      c_implementation_type_wrch => 1,
-      c_init_wr_pntr_val => 0,
-      c_interface_type => 0,
-      c_memory_type => 1,
-      c_mif_file_name => "BlankString",
-      c_msgon_val => 1,
-      c_optimization_mode => 0,
-      c_overflow_low => 0,
-      c_preload_latency => 1,
-      c_preload_regs => 0,
-      c_prim_fifo_type => "512x36",
-      c_prog_empty_thresh_assert_val => 2,
-      c_prog_empty_thresh_assert_val_axis => 1022,
-      c_prog_empty_thresh_assert_val_rach => 1022,
-      c_prog_empty_thresh_assert_val_rdch => 1022,
-      c_prog_empty_thresh_assert_val_wach => 1022,
-      c_prog_empty_thresh_assert_val_wdch => 1022,
-      c_prog_empty_thresh_assert_val_wrch => 1022,
-      c_prog_empty_thresh_negate_val => 3,
-      c_prog_empty_type => 0,
-      c_prog_empty_type_axis => 5,
-      c_prog_empty_type_rach => 5,
-      c_prog_empty_type_rdch => 5,
-      c_prog_empty_type_wach => 5,
-      c_prog_empty_type_wdch => 5,
-      c_prog_empty_type_wrch => 5,
-      c_prog_full_thresh_assert_val => 509,
-      c_prog_full_thresh_assert_val_axis => 1023,
-      c_prog_full_thresh_assert_val_rach => 1023,
-      c_prog_full_thresh_assert_val_rdch => 1023,
-      c_prog_full_thresh_assert_val_wach => 1023,
-      c_prog_full_thresh_assert_val_wdch => 1023,
-      c_prog_full_thresh_assert_val_wrch => 1023,
-      c_prog_full_thresh_negate_val => 508,
-      c_prog_full_type => 0,
-      c_prog_full_type_axis => 5,
-      c_prog_full_type_rach => 5,
-      c_prog_full_type_rdch => 5,
-      c_prog_full_type_wach => 5,
-      c_prog_full_type_wdch => 5,
-      c_prog_full_type_wrch => 5,
-      c_rach_type => 0,
-      c_rd_data_count_width => 9,
-      c_rd_depth => 512,
-      c_rd_freq => 1,
-      c_rd_pntr_width => 9,
-      c_rdch_type => 0,
-      c_reg_slice_mode_axis => 0,
-      c_reg_slice_mode_rach => 0,
-      c_reg_slice_mode_rdch => 0,
-      c_reg_slice_mode_wach => 0,
-      c_reg_slice_mode_wdch => 0,
-      c_reg_slice_mode_wrch => 0,
-      c_underflow_low => 0,
-      c_use_common_overflow => 0,
-      c_use_common_underflow => 0,
-      c_use_default_settings => 0,
-      c_use_dout_rst => 1,
-      c_use_ecc => 0,
-      c_use_ecc_axis => 0,
-      c_use_ecc_rach => 0,
-      c_use_ecc_rdch => 0,
-      c_use_ecc_wach => 0,
-      c_use_ecc_wdch => 0,
-      c_use_ecc_wrch => 0,
-      c_use_embedded_reg => 0,
-      c_use_fifo16_flags => 0,
-      c_use_fwft_data_count => 0,
-      c_valid_low => 0,
-      c_wach_type => 0,
-      c_wdch_type => 0,
-      c_wr_ack_low => 0,
-      c_wr_data_count_width => 9,
-      c_wr_depth => 512,
-      c_wr_depth_axis => 1024,
-      c_wr_depth_rach => 16,
-      c_wr_depth_rdch => 1024,
-      c_wr_depth_wach => 16,
-      c_wr_depth_wdch => 1024,
-      c_wr_depth_wrch => 16,
-      c_wr_freq => 1,
-      c_wr_pntr_width => 9,
-      c_wr_pntr_width_axis => 10,
-      c_wr_pntr_width_rach => 4,
-      c_wr_pntr_width_rdch => 10,
-      c_wr_pntr_width_wach => 4,
-      c_wr_pntr_width_wdch => 10,
-      c_wr_pntr_width_wrch => 4,
-      c_wr_response_latency => 1,
-      c_wrch_type => 0
-    );
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_async_fifo_512x32
-  PORT MAP (
-    rst => rst,
-    wr_clk => wr_clk,
-    rd_clk => rd_clk,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty
-  );
--- synthesis translate_on
-
-END async_fifo_512x32_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.vho b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.vho
deleted file mode 100644
index d5e22e8..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.vho
+++ /dev/null
@@ -1,92 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2012 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
---    Generated from core with identifier: xilinx.com:ip:fifo_generator:8.3   --
---                                                                            --
---    The FIFO Generator is a parameterizable first-in/first-out memory       --
---    queue generator. Use it to generate resource and performance            --
---    optimized FIFOs with common or independent read/write clock domains,    --
---    and optional fixed or programmable full and empty flags and             --
---    handshaking signals.  Choose from a selection of memory resource        --
---    types for implementation.  Optional Hamming code based error            --
---    detection and correction as well as error injection capability for      --
---    system test help to insure data integrity.  FIFO width and depth are    --
---    parameterizable, and for native interface FIFOs, asymmetric read and    --
---    write port widths are also supported.                                   --
---------------------------------------------------------------------------------
-
--- Interfaces:
---    AXI4Stream_MASTER_M_AXIS
---    AXI4Stream_SLAVE_S_AXIS
---    AXI4_MASTER_M_AXI
---    AXI4_SLAVE_S_AXI
---    AXI4Lite_MASTER_M_AXI
---    AXI4Lite_SLAVE_S_AXI
-
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-COMPONENT async_fifo_512x32
-  PORT (
-    rst : IN STD_LOGIC;
-    wr_clk : IN STD_LOGIC;
-    rd_clk : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END COMPONENT;
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : async_fifo_512x32
-  PORT MAP (
-    rst => rst,
-    wr_clk => wr_clk,
-    rd_clk => rd_clk,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty
-  );
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file async_fifo_512x32.vhd when simulating
--- the core, async_fifo_512x32. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.xco b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.xco
deleted file mode 100644
index 39a4720..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.xco
+++ /dev/null
@@ -1,217 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.3
-# Date: Thu Jul 26 14:36:50 2012
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:fifo_generator:8.3
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Fifo_Generator xilinx.com:ip:fifo_generator:8.3
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=async_fifo_512x32
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=2
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=3
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_handshake_flag_options_axis=false
-CSET enable_handshake_flag_options_rach=false
-CSET enable_handshake_flag_options_rdch=false
-CSET enable_handshake_flag_options_wach=false
-CSET enable_handshake_flag_options_wdch=false
-CSET enable_handshake_flag_options_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Independent_Clocks_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=509
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=508
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=32
-CSET input_depth=512
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=32
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=Empty
-CSET programmable_empty_type_rach=Empty
-CSET programmable_empty_type_rdch=Empty
-CSET programmable_empty_type_wach=Empty
-CSET programmable_empty_type_wdch=Empty
-CSET programmable_empty_type_wrch=Empty
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=Full
-CSET programmable_full_type_rach=Full
-CSET programmable_full_type_rdch=Full
-CSET programmable_full_type_wach=Full
-CSET programmable_full_type_wdch=Full
-CSET programmable_full_type_wrch=Full
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=9
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=9
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2011-03-14T07:12:32.000Z
-# END Extra information
-GENERATE
-# CRC: 5b1bf9c4
diff --git a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.xise b/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.xise
deleted file mode 100644
index d4e46b4..0000000
--- a/FEE_ADC32board/project/ipcore_dir/async_fifo_512x32.xise
+++ /dev/null
@@ -1,72 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="async_fifo_512x32.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="async_fifo_512x32.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|async_fifo_512x32|async_fifo_512x32_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="async_fifo_512x32.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/async_fifo_512x32" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="async_fifo_512x32" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-26T16:38:38" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="CECC96E91D3845338B0F194B6C73657D" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.asy b/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.asy
deleted file mode 100644
index 1ddbd3d..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.asy
+++ /dev/null
@@ -1,33 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 clockmodule40switch
-RECTANGLE Normal 32 32 576 1088
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk_in1
-PINATTR Polarity IN
-LINE Normal 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName clk_in2
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName clk_in_sel
-PINATTR Polarity IN
-LINE Normal 0 432 32 432
-PIN 0 432 LEFT 36
-PINATTR PinName reset
-PINATTR Polarity IN
-LINE Normal 608 80 576 80
-PIN 608 80 RIGHT 36
-PINATTR PinName clk_out1
-PINATTR Polarity OUT
-LINE Normal 608 176 576 176
-PIN 608 176 RIGHT 36
-PINATTR PinName clk_out2
-PINATTR Polarity OUT
-LINE Normal 608 976 576 976
-PIN 608 976 RIGHT 36
-PINATTR PinName locked
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.gise b/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.gise
deleted file mode 100644
index 71a76e6..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.gise
+++ /dev/null
@@ -1,52 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clockmodule40switch.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="clockmodule40switch.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="clockmodule40switch.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-798096215140453084" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="6740456813635759876" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6111184890770083540" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.ucf b/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.ucf
deleted file mode 100644
index 5f59e70..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.ucf
+++ /dev/null
@@ -1,61 +0,0 @@
-# file: clockmodule40switch.ucf
-# 
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-
-# Input clock periods. These duplicate the values entered for the
-#  input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;
-NET "CLK_IN2" TNM_NET = "CLK_IN2";
-TIMESPEC "TS_CLK_IN2" = PERIOD "CLK_IN2" 25.000 ns HIGH 50% INPUT_JITTER 250.0ps;
-
-
-# FALSE PATH constraints 
-PIN "RESET" TIG;
-
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.vho b/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.vho
deleted file mode 100644
index 7ef2b24..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.vho
+++ /dev/null
@@ -1,100 +0,0 @@
--- 
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- None
---
-------------------------------------------------------------------------------
--- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
--- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
-------------------------------------------------------------------------------
--- CLK_OUT1____40.000______0.000______50.0______247.096____196.976
--- CLK_OUT2____80.000______0.000______50.0______200.412____196.976
---
-------------------------------------------------------------------------------
--- "Input Clock   Freq (MHz)    Input Jitter (UI)"
-------------------------------------------------------------------------------
--- __primary______________40____________0.010
--- _secondary____________40____________0.010
-
-
--- The following code must appear in the VHDL architecture header:
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component clockmodule40switch
-port
- (-- Clock in ports
-  CLK_IN1           : in     std_logic;
-  CLK_IN2           : in     std_logic;
-  CLK_IN_SEL           : in     std_logic;
-  -- Clock out ports
-  CLK_OUT1          : out    std_logic;
-  CLK_OUT2          : out    std_logic;
-  -- Status and control signals
-  RESET             : in     std_logic;
-  LOCKED            : out    std_logic
- );
-end component;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : clockmodule40switch
-  port map
-   (-- Clock in ports
-    CLK_IN1 => CLK_IN1,
-    CLK_IN2 => CLK_IN2,
-    CLK_IN_SEL => CLK_IN_SEL,
-    -- Clock out ports
-    CLK_OUT1 => CLK_OUT1,
-    CLK_OUT2 => CLK_OUT2,
-    -- Status and control signals
-    RESET  => RESET,
-    LOCKED => LOCKED);
--- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.xco b/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.xco
deleted file mode 100644
index 854378f..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.xco
+++ /dev/null
@@ -1,269 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Wed Nov 26 08:54:36 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:clk_wiz:3.6
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
-# END Select
-# BEGIN Parameters
-CSET calc_done=DONE
-CSET clk_in_sel_port=CLK_IN_SEL
-CSET clk_out1_port=CLK_OUT1
-CSET clk_out1_use_fine_ps_gui=false
-CSET clk_out2_port=CLK_OUT2
-CSET clk_out2_use_fine_ps_gui=false
-CSET clk_out3_port=CLK_OUT3
-CSET clk_out3_use_fine_ps_gui=false
-CSET clk_out4_port=CLK_OUT4
-CSET clk_out4_use_fine_ps_gui=false
-CSET clk_out5_port=CLK_OUT5
-CSET clk_out5_use_fine_ps_gui=false
-CSET clk_out6_port=CLK_OUT6
-CSET clk_out6_use_fine_ps_gui=false
-CSET clk_out7_port=CLK_OUT7
-CSET clk_out7_use_fine_ps_gui=false
-CSET clk_valid_port=CLK_VALID
-CSET clkfb_in_n_port=CLKFB_IN_N
-CSET clkfb_in_p_port=CLKFB_IN_P
-CSET clkfb_in_port=CLKFB_IN
-CSET clkfb_in_signaling=SINGLE
-CSET clkfb_out_n_port=CLKFB_OUT_N
-CSET clkfb_out_p_port=CLKFB_OUT_P
-CSET clkfb_out_port=CLKFB_OUT
-CSET clkfb_stopped_port=CLKFB_STOPPED
-CSET clkin1_jitter_ps=250.0
-CSET clkin1_ui_jitter=0.010
-CSET clkin2_jitter_ps=250.0
-CSET clkin2_ui_jitter=0.010
-CSET clkout1_drives=BUFG
-CSET clkout1_requested_duty_cycle=50.000
-CSET clkout1_requested_out_freq=40
-CSET clkout1_requested_phase=0.000
-CSET clkout2_drives=BUFG
-CSET clkout2_requested_duty_cycle=50.000
-CSET clkout2_requested_out_freq=80
-CSET clkout2_requested_phase=0.000
-CSET clkout2_used=true
-CSET clkout3_drives=BUFG
-CSET clkout3_requested_duty_cycle=50.000
-CSET clkout3_requested_out_freq=100.000
-CSET clkout3_requested_phase=0.000
-CSET clkout3_used=false
-CSET clkout4_drives=BUFG
-CSET clkout4_requested_duty_cycle=50.000
-CSET clkout4_requested_out_freq=100.000
-CSET clkout4_requested_phase=0.000
-CSET clkout4_used=false
-CSET clkout5_drives=BUFG
-CSET clkout5_requested_duty_cycle=50.000
-CSET clkout5_requested_out_freq=100.000
-CSET clkout5_requested_phase=0.000
-CSET clkout5_used=false
-CSET clkout6_drives=BUFG
-CSET clkout6_requested_duty_cycle=50.000
-CSET clkout6_requested_out_freq=100.000
-CSET clkout6_requested_phase=0.000
-CSET clkout6_used=false
-CSET clkout7_drives=BUFG
-CSET clkout7_requested_duty_cycle=50.000
-CSET clkout7_requested_out_freq=100.000
-CSET clkout7_requested_phase=0.000
-CSET clkout7_used=false
-CSET clock_mgr_type=MANUAL
-CSET component_name=clockmodule40switch
-CSET daddr_port=DADDR
-CSET dclk_port=DCLK
-CSET dcm_clk_feedback=1X
-CSET dcm_clk_out1_port=CLK0
-CSET dcm_clk_out2_port=CLK0
-CSET dcm_clk_out3_port=CLK0
-CSET dcm_clk_out4_port=CLK0
-CSET dcm_clk_out5_port=CLK0
-CSET dcm_clk_out6_port=CLK0
-CSET dcm_clkdv_divide=2.0
-CSET dcm_clkfx_divide=1
-CSET dcm_clkfx_multiply=4
-CSET dcm_clkgen_clk_out1_port=CLKFX
-CSET dcm_clkgen_clk_out2_port=CLKFX
-CSET dcm_clkgen_clk_out3_port=CLKFX
-CSET dcm_clkgen_clkfx_divide=1
-CSET dcm_clkgen_clkfx_md_max=0.000
-CSET dcm_clkgen_clkfx_multiply=4
-CSET dcm_clkgen_clkfxdv_divide=2
-CSET dcm_clkgen_clkin_period=10.000
-CSET dcm_clkgen_notes=None
-CSET dcm_clkgen_spread_spectrum=NONE
-CSET dcm_clkgen_startup_wait=false
-CSET dcm_clkin_divide_by_2=false
-CSET dcm_clkin_period=10.000
-CSET dcm_clkout_phase_shift=NONE
-CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
-CSET dcm_notes=None
-CSET dcm_phase_shift=0
-CSET dcm_pll_cascade=NONE
-CSET dcm_startup_wait=false
-CSET den_port=DEN
-CSET din_port=DIN
-CSET dout_port=DOUT
-CSET drdy_port=DRDY
-CSET dwe_port=DWE
-CSET feedback_source=FDBK_AUTO
-CSET in_freq_units=Units_MHz
-CSET in_jitter_units=Units_UI
-CSET input_clk_stopped_port=INPUT_CLK_STOPPED
-CSET jitter_options=UI
-CSET jitter_sel=No_Jitter
-CSET locked_port=LOCKED
-CSET mmcm_bandwidth=OPTIMIZED
-CSET mmcm_clkfbout_mult_f=24.000
-CSET mmcm_clkfbout_phase=0.000
-CSET mmcm_clkfbout_use_fine_ps=false
-CSET mmcm_clkin1_period=25.000
-CSET mmcm_clkin2_period=25.000
-CSET mmcm_clkout0_divide_f=24.000
-CSET mmcm_clkout0_duty_cycle=0.500
-CSET mmcm_clkout0_phase=0.000
-CSET mmcm_clkout0_use_fine_ps=false
-CSET mmcm_clkout1_divide=12
-CSET mmcm_clkout1_duty_cycle=0.500
-CSET mmcm_clkout1_phase=0.000
-CSET mmcm_clkout1_use_fine_ps=false
-CSET mmcm_clkout2_divide=1
-CSET mmcm_clkout2_duty_cycle=0.500
-CSET mmcm_clkout2_phase=0.000
-CSET mmcm_clkout2_use_fine_ps=false
-CSET mmcm_clkout3_divide=1
-CSET mmcm_clkout3_duty_cycle=0.500
-CSET mmcm_clkout3_phase=0.000
-CSET mmcm_clkout3_use_fine_ps=false
-CSET mmcm_clkout4_cascade=false
-CSET mmcm_clkout4_divide=1
-CSET mmcm_clkout4_duty_cycle=0.500
-CSET mmcm_clkout4_phase=0.000
-CSET mmcm_clkout4_use_fine_ps=false
-CSET mmcm_clkout5_divide=1
-CSET mmcm_clkout5_duty_cycle=0.500
-CSET mmcm_clkout5_phase=0.000
-CSET mmcm_clkout5_use_fine_ps=false
-CSET mmcm_clkout6_divide=1
-CSET mmcm_clkout6_duty_cycle=0.500
-CSET mmcm_clkout6_phase=0.000
-CSET mmcm_clkout6_use_fine_ps=false
-CSET mmcm_clock_hold=false
-CSET mmcm_compensation=ZHOLD
-CSET mmcm_divclk_divide=1
-CSET mmcm_notes=None
-CSET mmcm_ref_jitter1=0.010
-CSET mmcm_ref_jitter2=0.010
-CSET mmcm_startup_wait=false
-CSET num_out_clks=2
-CSET override_dcm=false
-CSET override_dcm_clkgen=false
-CSET override_mmcm=false
-CSET override_pll=false
-CSET platform=nt64
-CSET pll_bandwidth=OPTIMIZED
-CSET pll_clk_feedback=CLKFBOUT
-CSET pll_clkfbout_mult=4
-CSET pll_clkfbout_phase=0.000
-CSET pll_clkin_period=10.000
-CSET pll_clkout0_divide=1
-CSET pll_clkout0_duty_cycle=0.500
-CSET pll_clkout0_phase=0.000
-CSET pll_clkout1_divide=1
-CSET pll_clkout1_duty_cycle=0.500
-CSET pll_clkout1_phase=0.000
-CSET pll_clkout2_divide=1
-CSET pll_clkout2_duty_cycle=0.500
-CSET pll_clkout2_phase=0.000
-CSET pll_clkout3_divide=1
-CSET pll_clkout3_duty_cycle=0.500
-CSET pll_clkout3_phase=0.000
-CSET pll_clkout4_divide=1
-CSET pll_clkout4_duty_cycle=0.500
-CSET pll_clkout4_phase=0.000
-CSET pll_clkout5_divide=1
-CSET pll_clkout5_duty_cycle=0.500
-CSET pll_clkout5_phase=0.000
-CSET pll_compensation=SYSTEM_SYNCHRONOUS
-CSET pll_divclk_divide=1
-CSET pll_notes=None
-CSET pll_ref_jitter=0.010
-CSET power_down_port=POWER_DOWN
-CSET prim_in_freq=40
-CSET prim_in_jitter=0.010
-CSET prim_source=Global_buffer
-CSET primary_port=CLK_IN1
-CSET primitive=MMCM
-CSET primtype_sel=MMCM_ADV
-CSET psclk_port=PSCLK
-CSET psdone_port=PSDONE
-CSET psen_port=PSEN
-CSET psincdec_port=PSINCDEC
-CSET relative_inclk=REL_PRIMARY
-CSET reset_port=RESET
-CSET secondary_in_freq=40
-CSET secondary_in_jitter=0.010
-CSET secondary_port=CLK_IN2
-CSET secondary_source=Global_buffer
-CSET ss_mod_freq=250
-CSET ss_mode=CENTER_HIGH
-CSET status_port=STATUS
-CSET summary_strings=empty
-CSET use_clk_valid=false
-CSET use_clkfb_stopped=false
-CSET use_dyn_phase_shift=false
-CSET use_dyn_reconfig=false
-CSET use_freeze=false
-CSET use_freq_synth=true
-CSET use_inclk_stopped=false
-CSET use_inclk_switchover=true
-CSET use_locked=true
-CSET use_max_i_jitter=false
-CSET use_min_o_jitter=false
-CSET use_min_power=false
-CSET use_phase_alignment=true
-CSET use_power_down=false
-CSET use_reset=true
-CSET use_spread_spectrum=false
-CSET use_spread_spectrum_1=false
-CSET use_status=false
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-05-10T12:44:55Z
-# END Extra information
-GENERATE
-# CRC: 41fd2223
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.xise b/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.xise
deleted file mode 100644
index 5f86341..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.xise
+++ /dev/null
@@ -1,75 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="clockmodule40switch.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="clockmodule40switch.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|clockmodule40switch|xilinx" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="clockmodule40switch.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clockmodule40switch" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="clockmodule40switch" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-26T09:55:02" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1222C6006EB742BD9905A04365D9D9E4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings>
-    <binding xil_pn:location="/clockmodule40switch" xil_pn:name="clockmodule40switch.ucf"/>
-  </bindings>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.asy b/FEE_ADC32board/project/ipcore_dir/clockmodule80M.asy
deleted file mode 100644
index 07d8d94..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.asy
+++ /dev/null
@@ -1,17 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 clockmodule80M
-RECTANGLE Normal 32 32 576 1088
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk_in1
-PINATTR Polarity IN
-LINE Normal 608 80 576 80
-PIN 608 80 RIGHT 36
-PINATTR PinName clk_out1
-PINATTR Polarity OUT
-LINE Normal 608 976 576 976
-PIN 608 976 RIGHT 36
-PINATTR PinName locked
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.gise b/FEE_ADC32board/project/ipcore_dir/clockmodule80M.gise
deleted file mode 100644
index c0a8fe5..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.gise
+++ /dev/null
@@ -1,52 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clockmodule80M.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="clockmodule80M.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="clockmodule80M.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1409562302" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1409562302">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4328670307819663427" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5868735601060516189" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="136310429885004787" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.ucf b/FEE_ADC32board/project/ipcore_dir/clockmodule80M.ucf
deleted file mode 100644
index 6fbd645..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.ucf
+++ /dev/null
@@ -1,58 +0,0 @@
-# file: clockmodule80M.ucf
-# 
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-
-# Input clock periods. These duplicate the values entered for the
-#  input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 6.430 ns HIGH 50% INPUT_JITTER 64.3ps;
-
-
-# FALSE PATH constraints 
-
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.vho b/FEE_ADC32board/project/ipcore_dir/clockmodule80M.vho
deleted file mode 100644
index e70f46c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.vho
+++ /dev/null
@@ -1,90 +0,0 @@
--- 
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- None
---
-------------------------------------------------------------------------------
--- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
--- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
-------------------------------------------------------------------------------
--- CLK_OUT1____99.999______0.000______50.0______144.151____174.045
---
-------------------------------------------------------------------------------
--- "Input Clock   Freq (MHz)    Input Jitter (UI)"
-------------------------------------------------------------------------------
--- __primary__________155.52____________0.010
-
-
--- The following code must appear in the VHDL architecture header:
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component clockmodule80M
-port
- (-- Clock in ports
-  CLK_IN1           : in     std_logic;
-  -- Clock out ports
-  CLK_OUT1          : out    std_logic;
-  -- Status and control signals
-  LOCKED            : out    std_logic
- );
-end component;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : clockmodule80M
-  port map
-   (-- Clock in ports
-    CLK_IN1 => CLK_IN1,
-    -- Clock out ports
-    CLK_OUT1 => CLK_OUT1,
-    -- Status and control signals
-    LOCKED => LOCKED);
--- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.xco b/FEE_ADC32board/project/ipcore_dir/clockmodule80M.xco
deleted file mode 100644
index 28df986..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.xco
+++ /dev/null
@@ -1,269 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Wed Nov 26 08:35:23 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:clk_wiz:3.6
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
-# END Select
-# BEGIN Parameters
-CSET calc_done=DONE
-CSET clk_in_sel_port=CLK_IN_SEL
-CSET clk_out1_port=CLK_OUT1
-CSET clk_out1_use_fine_ps_gui=false
-CSET clk_out2_port=CLK_OUT2
-CSET clk_out2_use_fine_ps_gui=false
-CSET clk_out3_port=CLK_OUT3
-CSET clk_out3_use_fine_ps_gui=false
-CSET clk_out4_port=CLK_OUT4
-CSET clk_out4_use_fine_ps_gui=false
-CSET clk_out5_port=CLK_OUT5
-CSET clk_out5_use_fine_ps_gui=false
-CSET clk_out6_port=CLK_OUT6
-CSET clk_out6_use_fine_ps_gui=false
-CSET clk_out7_port=CLK_OUT7
-CSET clk_out7_use_fine_ps_gui=false
-CSET clk_valid_port=CLK_VALID
-CSET clkfb_in_n_port=CLKFB_IN_N
-CSET clkfb_in_p_port=CLKFB_IN_P
-CSET clkfb_in_port=CLKFB_IN
-CSET clkfb_in_signaling=SINGLE
-CSET clkfb_out_n_port=CLKFB_OUT_N
-CSET clkfb_out_p_port=CLKFB_OUT_P
-CSET clkfb_out_port=CLKFB_OUT
-CSET clkfb_stopped_port=CLKFB_STOPPED
-CSET clkin1_jitter_ps=64.3
-CSET clkin1_ui_jitter=0.010
-CSET clkin2_jitter_ps=100.0
-CSET clkin2_ui_jitter=0.010
-CSET clkout1_drives=BUFG
-CSET clkout1_requested_duty_cycle=50.000
-CSET clkout1_requested_out_freq=100
-CSET clkout1_requested_phase=0.000
-CSET clkout2_drives=BUFG
-CSET clkout2_requested_duty_cycle=50.000
-CSET clkout2_requested_out_freq=100.000
-CSET clkout2_requested_phase=0.000
-CSET clkout2_used=false
-CSET clkout3_drives=BUFG
-CSET clkout3_requested_duty_cycle=50.000
-CSET clkout3_requested_out_freq=100.000
-CSET clkout3_requested_phase=0.000
-CSET clkout3_used=false
-CSET clkout4_drives=BUFG
-CSET clkout4_requested_duty_cycle=50.000
-CSET clkout4_requested_out_freq=100.000
-CSET clkout4_requested_phase=0.000
-CSET clkout4_used=false
-CSET clkout5_drives=BUFG
-CSET clkout5_requested_duty_cycle=50.000
-CSET clkout5_requested_out_freq=100.000
-CSET clkout5_requested_phase=0.000
-CSET clkout5_used=false
-CSET clkout6_drives=BUFG
-CSET clkout6_requested_duty_cycle=50.000
-CSET clkout6_requested_out_freq=100.000
-CSET clkout6_requested_phase=0.000
-CSET clkout6_used=false
-CSET clkout7_drives=BUFG
-CSET clkout7_requested_duty_cycle=50.000
-CSET clkout7_requested_out_freq=100.000
-CSET clkout7_requested_phase=0.000
-CSET clkout7_used=false
-CSET clock_mgr_type=MANUAL
-CSET component_name=clockmodule80M
-CSET daddr_port=DADDR
-CSET dclk_port=DCLK
-CSET dcm_clk_feedback=1X
-CSET dcm_clk_out1_port=CLK0
-CSET dcm_clk_out2_port=CLK0
-CSET dcm_clk_out3_port=CLK0
-CSET dcm_clk_out4_port=CLK0
-CSET dcm_clk_out5_port=CLK0
-CSET dcm_clk_out6_port=CLK0
-CSET dcm_clkdv_divide=2.0
-CSET dcm_clkfx_divide=1
-CSET dcm_clkfx_multiply=4
-CSET dcm_clkgen_clk_out1_port=CLKFX
-CSET dcm_clkgen_clk_out2_port=CLKFX
-CSET dcm_clkgen_clk_out3_port=CLKFX
-CSET dcm_clkgen_clkfx_divide=1
-CSET dcm_clkgen_clkfx_md_max=0.000
-CSET dcm_clkgen_clkfx_multiply=4
-CSET dcm_clkgen_clkfxdv_divide=2
-CSET dcm_clkgen_clkin_period=10.000
-CSET dcm_clkgen_notes=None
-CSET dcm_clkgen_spread_spectrum=NONE
-CSET dcm_clkgen_startup_wait=false
-CSET dcm_clkin_divide_by_2=false
-CSET dcm_clkin_period=10.000
-CSET dcm_clkout_phase_shift=NONE
-CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
-CSET dcm_notes=None
-CSET dcm_phase_shift=0
-CSET dcm_pll_cascade=NONE
-CSET dcm_startup_wait=false
-CSET den_port=DEN
-CSET din_port=DIN
-CSET dout_port=DOUT
-CSET drdy_port=DRDY
-CSET dwe_port=DWE
-CSET feedback_source=FDBK_AUTO
-CSET in_freq_units=Units_MHz
-CSET in_jitter_units=Units_UI
-CSET input_clk_stopped_port=INPUT_CLK_STOPPED
-CSET jitter_options=UI
-CSET jitter_sel=No_Jitter
-CSET locked_port=LOCKED
-CSET mmcm_bandwidth=OPTIMIZED
-CSET mmcm_clkfbout_mult_f=43.000
-CSET mmcm_clkfbout_phase=0.000
-CSET mmcm_clkfbout_use_fine_ps=false
-CSET mmcm_clkin1_period=6.430
-CSET mmcm_clkin2_period=10.000
-CSET mmcm_clkout0_divide_f=13.375
-CSET mmcm_clkout0_duty_cycle=0.500
-CSET mmcm_clkout0_phase=0.000
-CSET mmcm_clkout0_use_fine_ps=false
-CSET mmcm_clkout1_divide=1
-CSET mmcm_clkout1_duty_cycle=0.500
-CSET mmcm_clkout1_phase=0.000
-CSET mmcm_clkout1_use_fine_ps=false
-CSET mmcm_clkout2_divide=1
-CSET mmcm_clkout2_duty_cycle=0.500
-CSET mmcm_clkout2_phase=0.000
-CSET mmcm_clkout2_use_fine_ps=false
-CSET mmcm_clkout3_divide=1
-CSET mmcm_clkout3_duty_cycle=0.500
-CSET mmcm_clkout3_phase=0.000
-CSET mmcm_clkout3_use_fine_ps=false
-CSET mmcm_clkout4_cascade=false
-CSET mmcm_clkout4_divide=1
-CSET mmcm_clkout4_duty_cycle=0.500
-CSET mmcm_clkout4_phase=0.000
-CSET mmcm_clkout4_use_fine_ps=false
-CSET mmcm_clkout5_divide=1
-CSET mmcm_clkout5_duty_cycle=0.500
-CSET mmcm_clkout5_phase=0.000
-CSET mmcm_clkout5_use_fine_ps=false
-CSET mmcm_clkout6_divide=1
-CSET mmcm_clkout6_duty_cycle=0.500
-CSET mmcm_clkout6_phase=0.000
-CSET mmcm_clkout6_use_fine_ps=false
-CSET mmcm_clock_hold=false
-CSET mmcm_compensation=ZHOLD
-CSET mmcm_divclk_divide=5
-CSET mmcm_notes=None
-CSET mmcm_ref_jitter1=0.010
-CSET mmcm_ref_jitter2=0.010
-CSET mmcm_startup_wait=false
-CSET num_out_clks=1
-CSET override_dcm=false
-CSET override_dcm_clkgen=false
-CSET override_mmcm=false
-CSET override_pll=false
-CSET platform=nt64
-CSET pll_bandwidth=OPTIMIZED
-CSET pll_clk_feedback=CLKFBOUT
-CSET pll_clkfbout_mult=4
-CSET pll_clkfbout_phase=0.000
-CSET pll_clkin_period=10.000
-CSET pll_clkout0_divide=1
-CSET pll_clkout0_duty_cycle=0.500
-CSET pll_clkout0_phase=0.000
-CSET pll_clkout1_divide=1
-CSET pll_clkout1_duty_cycle=0.500
-CSET pll_clkout1_phase=0.000
-CSET pll_clkout2_divide=1
-CSET pll_clkout2_duty_cycle=0.500
-CSET pll_clkout2_phase=0.000
-CSET pll_clkout3_divide=1
-CSET pll_clkout3_duty_cycle=0.500
-CSET pll_clkout3_phase=0.000
-CSET pll_clkout4_divide=1
-CSET pll_clkout4_duty_cycle=0.500
-CSET pll_clkout4_phase=0.000
-CSET pll_clkout5_divide=1
-CSET pll_clkout5_duty_cycle=0.500
-CSET pll_clkout5_phase=0.000
-CSET pll_compensation=SYSTEM_SYNCHRONOUS
-CSET pll_divclk_divide=1
-CSET pll_notes=None
-CSET pll_ref_jitter=0.010
-CSET power_down_port=POWER_DOWN
-CSET prim_in_freq=155.52
-CSET prim_in_jitter=0.010
-CSET prim_source=No_buffer
-CSET primary_port=CLK_IN1
-CSET primitive=MMCM
-CSET primtype_sel=MMCM_ADV
-CSET psclk_port=PSCLK
-CSET psdone_port=PSDONE
-CSET psen_port=PSEN
-CSET psincdec_port=PSINCDEC
-CSET relative_inclk=REL_PRIMARY
-CSET reset_port=RESET
-CSET secondary_in_freq=100.000
-CSET secondary_in_jitter=0.010
-CSET secondary_port=CLK_IN2
-CSET secondary_source=Single_ended_clock_capable_pin
-CSET ss_mod_freq=250
-CSET ss_mode=CENTER_HIGH
-CSET status_port=STATUS
-CSET summary_strings=empty
-CSET use_clk_valid=false
-CSET use_clkfb_stopped=false
-CSET use_dyn_phase_shift=false
-CSET use_dyn_reconfig=false
-CSET use_freeze=false
-CSET use_freq_synth=true
-CSET use_inclk_stopped=false
-CSET use_inclk_switchover=false
-CSET use_locked=true
-CSET use_max_i_jitter=false
-CSET use_min_o_jitter=false
-CSET use_min_power=false
-CSET use_phase_alignment=true
-CSET use_power_down=false
-CSET use_reset=false
-CSET use_spread_spectrum=false
-CSET use_spread_spectrum_1=false
-CSET use_status=false
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-05-10T12:44:55Z
-# END Extra information
-GENERATE
-# CRC: c8df1962
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.xise b/FEE_ADC32board/project/ipcore_dir/clockmodule80M.xise
deleted file mode 100644
index 7f439ad..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80M.xise
+++ /dev/null
@@ -1,75 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="clockmodule80M.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="clockmodule80M.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|clockmodule80M|xilinx" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="clockmodule80M.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clockmodule80M" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="clockmodule80M" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-26T09:35:49" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3A77989C9A5740C8BC9FB6A41BD011E7" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings>
-    <binding xil_pn:location="/clockmodule80M" xil_pn:name="clockmodule80M.ucf"/>
-  </bindings>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.asy b/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.asy
deleted file mode 100644
index b3be860..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.asy
+++ /dev/null
@@ -1,33 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 clockmodule80to80M
-RECTANGLE Normal 32 32 576 1088
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk_in1
-PINATTR Polarity IN
-LINE Normal 0 432 32 432
-PIN 0 432 LEFT 36
-PINATTR PinName reset
-PINATTR Polarity IN
-LINE Normal 608 80 576 80
-PIN 608 80 RIGHT 36
-PINATTR PinName clk_out1
-PINATTR Polarity OUT
-LINE Normal 608 176 576 176
-PIN 608 176 RIGHT 36
-PINATTR PinName clk_out2
-PINATTR Polarity OUT
-LINE Normal 608 272 576 272
-PIN 608 272 RIGHT 36
-PINATTR PinName clk_out3
-PINATTR Polarity OUT
-LINE Normal 608 368 576 368
-PIN 608 368 RIGHT 36
-PINATTR PinName clk_out4
-PINATTR Polarity OUT
-LINE Normal 608 976 576 976
-PIN 608 976 RIGHT 36
-PINATTR PinName locked
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.gise b/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.gise
deleted file mode 100644
index 4ca6f49..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.gise
+++ /dev/null
@@ -1,52 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="clockmodule80to80M.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="clockmodule80to80M.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="clockmodule80to80M.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1409562302" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1409562302">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5501743936565268942" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-6677609659508388402" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="1239178134026909054" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.ucf b/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.ucf
deleted file mode 100644
index 80a26ae..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.ucf
+++ /dev/null
@@ -1,59 +0,0 @@
-# file: clockmodule80to80M.ucf
-# 
-# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
-# 
-# This file contains confidential and proprietary information
-# of Xilinx, Inc. and is protected under U.S. and
-# international copyright and other intellectual property
-# laws.
-# 
-# DISCLAIMER
-# This disclaimer is not a license and does not grant any
-# rights to the materials distributed herewith. Except as
-# otherwise provided in a valid license issued to you by
-# Xilinx, and to the maximum extent permitted by applicable
-# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-# (2) Xilinx shall not be liable (whether in contract or tort,
-# including negligence, or under any other theory of
-# liability) for any loss or damage of any kind or nature
-# related to, arising under or in connection with these
-# materials, including for any direct, or any indirect,
-# special, incidental, or consequential loss or damage
-# (including loss of data, profits, goodwill, or any type of
-# loss or damage suffered as a result of any action brought
-# by a third party) even if such damage or loss was
-# reasonably foreseeable or Xilinx had been advised of the
-# possibility of the same.
-# 
-# CRITICAL APPLICATIONS
-# Xilinx products are not designed or intended to be fail-
-# safe, or for use in any application requiring fail-safe
-# performance, such as life-support or safety devices or
-# systems, Class III medical devices, nuclear facilities,
-# applications related to the deployment of airbags, or any
-# other applications that could lead to death, personal
-# injury, or severe property or environmental damage
-# (individually and collectively, "Critical
-# Applications"). Customer assumes the sole risk and
-# liability of any use of Xilinx products in Critical
-# Applications, subject only to applicable laws and
-# regulations governing limitations on product liability.
-# 
-# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-# PART OF THIS FILE AT ALL TIMES.
-# 
-
-# Input clock periods. These duplicate the values entered for the
-#  input clocks. You can use these to time your system
-#----------------------------------------------------------------
-NET "CLK_IN1" TNM_NET = "CLK_IN1";
-TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 10.000 ns HIGH 50% INPUT_JITTER 100.0ps;
-
-
-# FALSE PATH constraints 
-PIN "RESET" TIG;
-
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.vho b/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.vho
deleted file mode 100644
index 6eb16cc..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.vho
+++ /dev/null
@@ -1,101 +0,0 @@
--- 
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- None
---
-------------------------------------------------------------------------------
--- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
--- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
-------------------------------------------------------------------------------
--- CLK_OUT1____40.000______0.000______50.0______174.629____114.212
--- CLK_OUT2____80.000______0.000______50.0______151.652____114.212
--- CLK_OUT3___100.000______0.000______50.0______144.719____114.212
--- CLK_OUT4___200.000______0.000______50.0______126.455____114.212
---
-------------------------------------------------------------------------------
--- "Input Clock   Freq (MHz)    Input Jitter (UI)"
-------------------------------------------------------------------------------
--- __primary_____________100____________0.010
-
-
--- The following code must appear in the VHDL architecture header:
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component clockmodule80to80M
-port
- (-- Clock in ports
-  CLK_IN1           : in     std_logic;
-  -- Clock out ports
-  CLK_OUT1          : out    std_logic;
-  CLK_OUT2          : out    std_logic;
-  CLK_OUT3          : out    std_logic;
-  CLK_OUT4          : out    std_logic;
-  -- Status and control signals
-  RESET             : in     std_logic;
-  LOCKED            : out    std_logic
- );
-end component;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : clockmodule80to80M
-  port map
-   (-- Clock in ports
-    CLK_IN1 => CLK_IN1,
-    -- Clock out ports
-    CLK_OUT1 => CLK_OUT1,
-    CLK_OUT2 => CLK_OUT2,
-    CLK_OUT3 => CLK_OUT3,
-    CLK_OUT4 => CLK_OUT4,
-    -- Status and control signals
-    RESET  => RESET,
-    LOCKED => LOCKED);
--- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.xco b/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.xco
deleted file mode 100644
index 0dfdf37..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.xco
+++ /dev/null
@@ -1,269 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Wed Nov 26 08:36:53 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:clk_wiz:3.6
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
-# END Select
-# BEGIN Parameters
-CSET calc_done=DONE
-CSET clk_in_sel_port=CLK_IN_SEL
-CSET clk_out1_port=CLK_OUT1
-CSET clk_out1_use_fine_ps_gui=false
-CSET clk_out2_port=CLK_OUT2
-CSET clk_out2_use_fine_ps_gui=false
-CSET clk_out3_port=CLK_OUT3
-CSET clk_out3_use_fine_ps_gui=false
-CSET clk_out4_port=CLK_OUT4
-CSET clk_out4_use_fine_ps_gui=false
-CSET clk_out5_port=CLK_OUT5
-CSET clk_out5_use_fine_ps_gui=false
-CSET clk_out6_port=CLK_OUT6
-CSET clk_out6_use_fine_ps_gui=false
-CSET clk_out7_port=CLK_OUT7
-CSET clk_out7_use_fine_ps_gui=false
-CSET clk_valid_port=CLK_VALID
-CSET clkfb_in_n_port=CLKFB_IN_N
-CSET clkfb_in_p_port=CLKFB_IN_P
-CSET clkfb_in_port=CLKFB_IN
-CSET clkfb_in_signaling=SINGLE
-CSET clkfb_out_n_port=CLKFB_OUT_N
-CSET clkfb_out_p_port=CLKFB_OUT_P
-CSET clkfb_out_port=CLKFB_OUT
-CSET clkfb_stopped_port=CLKFB_STOPPED
-CSET clkin1_jitter_ps=100.0
-CSET clkin1_ui_jitter=0.010
-CSET clkin2_jitter_ps=100.0
-CSET clkin2_ui_jitter=0.010
-CSET clkout1_drives=BUFG
-CSET clkout1_requested_duty_cycle=50.000
-CSET clkout1_requested_out_freq=40.000
-CSET clkout1_requested_phase=0.000
-CSET clkout2_drives=BUFG
-CSET clkout2_requested_duty_cycle=50.000
-CSET clkout2_requested_out_freq=80.000
-CSET clkout2_requested_phase=0.000
-CSET clkout2_used=true
-CSET clkout3_drives=BUFG
-CSET clkout3_requested_duty_cycle=50.000
-CSET clkout3_requested_out_freq=100.000
-CSET clkout3_requested_phase=0.000
-CSET clkout3_used=true
-CSET clkout4_drives=BUFG
-CSET clkout4_requested_duty_cycle=50.000
-CSET clkout4_requested_out_freq=200
-CSET clkout4_requested_phase=0.000
-CSET clkout4_used=true
-CSET clkout5_drives=BUFG
-CSET clkout5_requested_duty_cycle=50.000
-CSET clkout5_requested_out_freq=200.000
-CSET clkout5_requested_phase=0.000
-CSET clkout5_used=false
-CSET clkout6_drives=BUFG
-CSET clkout6_requested_duty_cycle=50.000
-CSET clkout6_requested_out_freq=100.000
-CSET clkout6_requested_phase=0.000
-CSET clkout6_used=false
-CSET clkout7_drives=BUFG
-CSET clkout7_requested_duty_cycle=50.000
-CSET clkout7_requested_out_freq=100.000
-CSET clkout7_requested_phase=0.000
-CSET clkout7_used=false
-CSET clock_mgr_type=MANUAL
-CSET component_name=clockmodule80to80M
-CSET daddr_port=DADDR
-CSET dclk_port=DCLK
-CSET dcm_clk_feedback=1X
-CSET dcm_clk_out1_port=CLK0
-CSET dcm_clk_out2_port=CLK0
-CSET dcm_clk_out3_port=CLK0
-CSET dcm_clk_out4_port=CLK0
-CSET dcm_clk_out5_port=CLK0
-CSET dcm_clk_out6_port=CLK0
-CSET dcm_clkdv_divide=2.0
-CSET dcm_clkfx_divide=1
-CSET dcm_clkfx_multiply=4
-CSET dcm_clkgen_clk_out1_port=CLKFX
-CSET dcm_clkgen_clk_out2_port=CLKFX
-CSET dcm_clkgen_clk_out3_port=CLKFX
-CSET dcm_clkgen_clkfx_divide=1
-CSET dcm_clkgen_clkfx_md_max=0.000
-CSET dcm_clkgen_clkfx_multiply=4
-CSET dcm_clkgen_clkfxdv_divide=2
-CSET dcm_clkgen_clkin_period=10.000
-CSET dcm_clkgen_notes=None
-CSET dcm_clkgen_spread_spectrum=NONE
-CSET dcm_clkgen_startup_wait=false
-CSET dcm_clkin_divide_by_2=false
-CSET dcm_clkin_period=10.000
-CSET dcm_clkout_phase_shift=NONE
-CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
-CSET dcm_notes=None
-CSET dcm_phase_shift=0
-CSET dcm_pll_cascade=NONE
-CSET dcm_startup_wait=false
-CSET den_port=DEN
-CSET din_port=DIN
-CSET dout_port=DOUT
-CSET drdy_port=DRDY
-CSET dwe_port=DWE
-CSET feedback_source=FDBK_AUTO
-CSET in_freq_units=Units_MHz
-CSET in_jitter_units=Units_UI
-CSET input_clk_stopped_port=INPUT_CLK_STOPPED
-CSET jitter_options=UI
-CSET jitter_sel=No_Jitter
-CSET locked_port=LOCKED
-CSET mmcm_bandwidth=OPTIMIZED
-CSET mmcm_clkfbout_mult_f=8.000
-CSET mmcm_clkfbout_phase=0.000
-CSET mmcm_clkfbout_use_fine_ps=false
-CSET mmcm_clkin1_period=10.000
-CSET mmcm_clkin2_period=10.000
-CSET mmcm_clkout0_divide_f=20.000
-CSET mmcm_clkout0_duty_cycle=0.500
-CSET mmcm_clkout0_phase=0.000
-CSET mmcm_clkout0_use_fine_ps=false
-CSET mmcm_clkout1_divide=10
-CSET mmcm_clkout1_duty_cycle=0.500
-CSET mmcm_clkout1_phase=0.000
-CSET mmcm_clkout1_use_fine_ps=false
-CSET mmcm_clkout2_divide=8
-CSET mmcm_clkout2_duty_cycle=0.500
-CSET mmcm_clkout2_phase=0.000
-CSET mmcm_clkout2_use_fine_ps=false
-CSET mmcm_clkout3_divide=4
-CSET mmcm_clkout3_duty_cycle=0.500
-CSET mmcm_clkout3_phase=0.000
-CSET mmcm_clkout3_use_fine_ps=false
-CSET mmcm_clkout4_cascade=false
-CSET mmcm_clkout4_divide=4
-CSET mmcm_clkout4_duty_cycle=0.500
-CSET mmcm_clkout4_phase=0.000
-CSET mmcm_clkout4_use_fine_ps=false
-CSET mmcm_clkout5_divide=1
-CSET mmcm_clkout5_duty_cycle=0.500
-CSET mmcm_clkout5_phase=0.000
-CSET mmcm_clkout5_use_fine_ps=false
-CSET mmcm_clkout6_divide=1
-CSET mmcm_clkout6_duty_cycle=0.500
-CSET mmcm_clkout6_phase=0.000
-CSET mmcm_clkout6_use_fine_ps=false
-CSET mmcm_clock_hold=false
-CSET mmcm_compensation=ZHOLD
-CSET mmcm_divclk_divide=1
-CSET mmcm_notes=None
-CSET mmcm_ref_jitter1=0.010
-CSET mmcm_ref_jitter2=0.010
-CSET mmcm_startup_wait=false
-CSET num_out_clks=4
-CSET override_dcm=false
-CSET override_dcm_clkgen=false
-CSET override_mmcm=false
-CSET override_pll=false
-CSET platform=nt64
-CSET pll_bandwidth=OPTIMIZED
-CSET pll_clk_feedback=CLKFBOUT
-CSET pll_clkfbout_mult=4
-CSET pll_clkfbout_phase=0.000
-CSET pll_clkin_period=10.000
-CSET pll_clkout0_divide=1
-CSET pll_clkout0_duty_cycle=0.500
-CSET pll_clkout0_phase=0.000
-CSET pll_clkout1_divide=1
-CSET pll_clkout1_duty_cycle=0.500
-CSET pll_clkout1_phase=0.000
-CSET pll_clkout2_divide=1
-CSET pll_clkout2_duty_cycle=0.500
-CSET pll_clkout2_phase=0.000
-CSET pll_clkout3_divide=1
-CSET pll_clkout3_duty_cycle=0.500
-CSET pll_clkout3_phase=0.000
-CSET pll_clkout4_divide=1
-CSET pll_clkout4_duty_cycle=0.500
-CSET pll_clkout4_phase=0.000
-CSET pll_clkout5_divide=1
-CSET pll_clkout5_duty_cycle=0.500
-CSET pll_clkout5_phase=0.000
-CSET pll_compensation=SYSTEM_SYNCHRONOUS
-CSET pll_divclk_divide=1
-CSET pll_notes=None
-CSET pll_ref_jitter=0.010
-CSET power_down_port=POWER_DOWN
-CSET prim_in_freq=100
-CSET prim_in_jitter=0.010
-CSET prim_source=No_buffer
-CSET primary_port=CLK_IN1
-CSET primitive=MMCM
-CSET primtype_sel=MMCM_ADV
-CSET psclk_port=PSCLK
-CSET psdone_port=PSDONE
-CSET psen_port=PSEN
-CSET psincdec_port=PSINCDEC
-CSET relative_inclk=REL_PRIMARY
-CSET reset_port=RESET
-CSET secondary_in_freq=100.000
-CSET secondary_in_jitter=0.010
-CSET secondary_port=CLK_IN2
-CSET secondary_source=Single_ended_clock_capable_pin
-CSET ss_mod_freq=250
-CSET ss_mode=CENTER_HIGH
-CSET status_port=STATUS
-CSET summary_strings=empty
-CSET use_clk_valid=false
-CSET use_clkfb_stopped=false
-CSET use_dyn_phase_shift=false
-CSET use_dyn_reconfig=false
-CSET use_freeze=false
-CSET use_freq_synth=true
-CSET use_inclk_stopped=false
-CSET use_inclk_switchover=false
-CSET use_locked=true
-CSET use_max_i_jitter=false
-CSET use_min_o_jitter=false
-CSET use_min_power=false
-CSET use_phase_alignment=true
-CSET use_power_down=false
-CSET use_reset=true
-CSET use_spread_spectrum=false
-CSET use_spread_spectrum_1=false
-CSET use_status=false
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-05-10T12:44:55Z
-# END Extra information
-GENERATE
-# CRC: f0b0ba04
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.xise b/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.xise
deleted file mode 100644
index c15c032..0000000
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule80to80M.xise
+++ /dev/null
@@ -1,75 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="clockmodule80to80M.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="clockmodule80to80M.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|clockmodule80to80M|xilinx" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="clockmodule80to80M.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clockmodule80to80M" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="clockmodule80to80M" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-26T09:37:18" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="5931B5D0516D4A0896A5522B5D44137B" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings>
-    <binding xil_pn:location="/clockmodule80to80M" xil_pn:name="clockmodule80to80M.ucf"/>
-  </bindings>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/coregen.cgp b/FEE_ADC32board/project/ipcore_dir/coregen.cgp
deleted file mode 100644
index 1f2a88e..0000000
--- a/FEE_ADC32board/project/ipcore_dir/coregen.cgp
+++ /dev/null
@@ -1,9 +0,0 @@
-SET busformat = BusFormatAngleBracketNotRipped
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET package = ff484
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
diff --git a/FEE_ADC32board/project/ipcore_dir/data_vio.ngc b/FEE_ADC32board/project/ipcore_dir/data_vio.ngc
deleted file mode 100644
index 465356a..0000000
--- a/FEE_ADC32board/project/ipcore_dir/data_vio.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
-$b254=7<2:;<=:401210>6688>0<;??1:07?77788=0??4FNQWW>DU^FJUBB1=>:1<22>552@D[YY4\YOA\MK:493:5=45<2;MVPUSS2HYRBNQ@UU>05?699118>7AZTQWW>V_IKVE^X1=>:1<22>512@DDYY4LOOVQKI:4=3:5869IFG33?2@ANOLMJKHIFGDEB4=?022;<=>?0108E54<I880M?<4A2:8ECGDI:K;n6O\YOA\MK:76j1J_T@L_HL?558d3HYRBNQFN=32:f=F[PDHSD@313<`?DU^FJUBB1?<>b9BW\HDW@D7=90l;@QZJFYNF5;>2n5NSXL@[LH;9?4h7L]VNB]JJ9706j1J_T@L_HL?5=8d3HYRBNQFN=3::g=F[PDHSD@31?a8EV_IKVCE0?>1c:CP]KEXAG69=3m4AR[MGZOI4;85o6O\YOA\MK:5;7i0M^WAC^KM8729k2KXUCMPIO>11;e<IZSEORGA<34=g>GTQGITEC2=7?a8EV_IKVCE0?61c:CP]KEXAG6953l4AR[MGZOI4;4h7L]VNB]JJ9576l1J_T@L_HL?74<76j1J_T@L_HL?748e3HYRBNQFN=1=f>GTQGITEC2;>c9BW\HDW@D793l4AR[MGZOI4?4i7L]VNB]JJ919j2KXUCMPIO>;:g=F[PDHSD@39?a8EV_IKVE^X1>1d:CP]KEXG\^7==0k;@QZJFYH]]6:=3j4AR[MGZIR\5;92i5NSXL@[JSS4895h6O\YOA\KPR;9=4o7L]VNB]LQQ:6=7n0M^WAC^MVP9716m1J_T@L_NWW8419l2KXUCMPOTV?5=8c3HYRBNQ@UU>2=;e<IZSEORAZT=3=`>GTQGITCXZ321<g?DU^FJUDYY2=1?f8EV_IKVE^X1<=>e9BW\HDWF__0?=1d:CP]KEXG\^7>90k;@QZJFYH]]6993j4AR[MGZIR\58=2i5NSXL@[JSS4;=5h6O\YOA\KPR;:14o7L]VNB]LQQ:517i0M^WAC^MVP949l2KXUCMPOTV?758a3HYRBNQ@UU>05?69l2KXUCMPOTV?748d3HYRBNQ@UU>0:f=F[PDHSB[[<5<`?DU^FJUDYY2:>b9BW\HDWF__0;0l;@QZJFYH]]6<2n5NSXL@[JSS414h7L]VNB]LQQ:>6=1I==77;CWP[LHAG81H>6MN2:AF57=D@LI@SAGLEOQF[Q_WM;1HE>5LLJ18GIT>3JEFADZ[EEc8GJHSZFF7<3l4CNLWVJJ;994i7NAATSMO8479j2IDBY\@L=31:g=DGG^YCA2>3?`8GJHSZFF7=90m;BMMPWIK48?5n6M@NUPLH9716k1HCCZ]OM>23;d<KFD_^BB319<a?FII\[EG0<71a:ALJQTHD5;5n6M@NUPLH9476k1HCCZ]OM>15;d<KFD_^BB323<a?FII\[EG0?=1b:ALJQTHD58?2o5LOOVQKI:5=7h0OB@[RNN?638e3JEEX_AC<35=f>EHF]XD@1<7>c9@KKRUGE6953o4CNLWVJJ;:7h0OB@[RNN?758e3JEEX_AC<23=f>EHF]XD@1==>c9@KKRUGE68?3l4CNLWVJJ;;=4o7NAATSMO863=87h0OB@[RNN?708f3JEEX_AC<2<b?FII\[EG090n;BMMPWIK4<4j7NAATSMO838f3JEEX_AC<6<b?FII\[EG050n;BMMPWIK404:86M@RD]DAKCUI]CDBRGAFN58GWCF\LN:7I<4DH78@ZEKC8:0JIL6EBC;3056>=8;86HKCD18BAC43ONY86HKRD:8BC@ANOLN=6I<;FLG2>NBIMUG=6G=;H21?L753@897D==;H61?L3>3@DBX^ZNTD18MKP53EC97AA8;MMDMFGK<2F^X<:4LTV10>JR\:>0@XZ;4:NVP02<D\^=;6CZXB[\H7=I8;1E=>5A3758J@RPG[A:7B?4P59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ1:S0?T7292X:7^84SNWQG@1<[[FH=;Kn;R[MGZOI494i7^WAC^KM8469j2YRBNQFN=32:g=TQGITEC2>2?`8W\HDW@D7=>0m;R[MGZOI48>5n6]VNB]JJ9726k1XUCMPIO>22;d<[PDHSD@316<a?V_IKVCE0<61b:QZJFYNF5;22l5\YOA\MK:66k1XUCMPIO>14;d<[PDHSD@320<a?V_IKVCE0?<1b:QZJFYNF5882o5\YOA\MK:5<7h0_T@L_HL?608e3ZSEORGA<34=f>U^FJUBB1<8>c9P]KEXAG6943l4SXL@[LH;:04j7^WAC^KM878e3ZSEORGA<22=`>U^FJUBB1=>:1<a?V_IKVCE0>?1a:QZJFYNF595m6]VNB]JJ929i2YRBNQFN=7=e>U^FJUBB181a:QZJFYNF5=5m6]VNB]JJ9>9i2YRBNQFN=;=f>U^FJUDYY2?>b9P]KEXG\^7==0l;R[MGZIR\5;:2n5\YOA\KPR;9;4h7^WAC^MVP9746j1XUCMPOTV?518d3ZSEORAZT=36:f=TQGITCXZ317<`?V_IKVE^X1?8>b9P]KEXG\^7=50l;R[MGZIR\5;22o5\YOA\KPR;97i0_T@L_NWW8769k2YRBNQ@UU>15;e<[PDHSB[[<30=g>U^FJUDYY2=3?a8W\HDWF__0?:1c:QZJFYH]]6993m4SXL@[JSS4;<5o6]VNB]LQQ:5?7i0_T@L_NWW87>9k2YRBNQ@UU>1=;d<[PDHSB[[<3<`?V_IKVE^X1=?>d9P]KEXG\^7?<4?>b9P]KEXG\^7?<0m;R[MGZIR\595n6]VNB]LQQ:36k1XUCMPOTV?1;d<[PDHSB[[<7<a?V_IKVE^X191b:QZJFYH]]632o5\YOA\KPR;17=0XCCPNDV7?Q_WM880Y=!F_WKL+DTJWygh?=;T2,MZPNG&NJXLQKOTV06>S7'@U]EB!HEO]BW\HDW@DP<P NSXL@[LHXKLFG#L]VNB]E[HS_;;1^<"GPVHM,C@HXIZSEORGA[1_-EV_IKVCESNKCL.CP]KEXZVG^T>:4U1-J[SOH'NOESL]VNB]JJ^6Z&HYRBNQFN^AFHI)TWHYRBNQI_SGD77=R8&CTZDA GDL\EV_IKVCEW=S!AR[MGZOIWJOG@"]PAR[MGZTBO:>0Y=!F_WKL+BCIWHYRBNQFNZ2^*DU^FJUBBRMJLM-P[DU^FJUYS_KH309V4*OX^@E$KH@PAR[MGZOIS9W%M^WAC^KM[FCKD&YTY^K]_SGD6c=R8&CTZDA GDL\EV_IKVCEW=S!AR[MGZOIWJOG@"[\ES]NQ]573\:$ERXFO.EFJZGTQGITECU?]/CP]KEXAGUHIAB U^DBHIOIO;l0Y=!F_WKL+BCIWHYRBNQFNZ2^*DU^FJUBBRMJLM-V[WOTAGM8>6[?/H]UMJ)@MGUJ_T@L_HLX4X(F[PDHSD@PCDNO+PYT\H^HAIQa379V4*OX^@E$KH@PAR[MGZOIS9W%M^WAC^KM[FCKD&kxucmPmtz\bZir|:<0Y=!F_WKL+BCIWHYRBNQFNZ2^*DU^FJUBBRMJLM-bw|hdWdsSQ`uu11?P6(AV\BC"IJN^CP]KEXAGQ;Q#O\YOA\MKYDMEF$jlbcioe\kpr5m2_;#DQYIN-DAKYF[PDHSD@T0\,BW\HDW@DTOHBC/gf2[jss:l1^<"GPVHM,C@HXIZSEORGA[1_-EV_IKVCESNKCL.dg6Zir|;o0Y=!F_WKL+BCIWHYRBNQFNZ2^*DU^FJUBBRMJLM-e`6Yh}}8m7X> I^TJK*ABFVKXUCMPIOY3Y+GTQGITECQLEMN,ip~6Wf?<5Z0.K\RLI(OLDTM^WAC^KM_5[)IZSEORGA_BGOH*tn{`dlSb{{319V4*OX^@E$KH@PAR[MGZOIS9W%M^WAC^KM[FCKD&xiQfn^l07>S7'@U]EB!HEO]BW\HDW@DP==S!AR[MGZOIWJOG@"O\YOA\BZKRP:90Y=!F_WKL+BCIWHYRBNQFNZ33Y+GTQGITECQLEMN,EV_IKVXTAXV<5:W3+LYQAF%LICQNSXL@[LH\99W%M^WAC^KM[FCKD&YTM^WAC^D\V@A4;2_;#DQYIN-DAKYF[PDHSD@T11_-EV_IKVCESNKCL.Q\EV_IKVXNK>;4U1-J[SOH'NOESL]VNB]JJ^77U'KXUCMPIO]@AIJ([VKXUCMPR^PFC64<]9%BS[G@/FGM[DU^FJUBBV??]/CP]KEXAGUHIAB S^WPAWYUMN9;7X> I^TJK*ABFVKXUCMPIOY24X(F[PDHSD@PCDNO+PUBZVG^T>?4U1-J[SOH'NOESL]VNB]JJ^77U'KXUCMPIO]@AIJ(]VLJ@AGAG228Q5)NW_CD#JKA_@QZJFYNFR;;Q#O\YOA\MKYDMEF$YR\FSHLD76=R8&CTZDA GDL\EV_IKVCEW<>R.@QZJFYNFVIN@A!Z_RVBPFKCWg9<7X> I^TJK*ABFVKXUCMPIOY24X(F[PDHSD@PCDNO+du~fjUfyuQi_nww72=R8&CTZDA GDL\EV_IKVCEW<>R.@QZJFYNFVIN@A!nsxl`[hsW{Udyy=<;T2,MZPNG&MNBRO\YOA\MK]68T$J_T@L_HL\G@JK'okg`d`h_nww6c=R8&CTZDA GDL\EV_IKVCEW<>R.@QZJFYNFVIN@A!id0]lqq4a3\:$ERXFO.EFJZGTQGITECU>0\,BW\HDW@DTOHBC/gf1[jss:o1^<"GPVHM,C@HXIZSEORGA[02^*DU^FJUBBRMJLM-e`6Yh}}9;7X> I^TJK*ABFVKXUCMPIOY24X(F[PDHSD@PCDNO+hs9Ve~x><4U1-J[SOH'NOESL]VNB]JJ^77U'KXUCMPIO]@AIJ(z`ybbjQ`uu12?P6(AV\BC"IJN^CP]KEXAGQ:<P NSXL@[LHXKLFG#x}jr^km[k543\:$ERXFO.EFJZGTQGITECU>1\,BW\HDW@DTOHBC/@QZJFYAWD_S?>5Z0.K\RLI(OLDTM^WAC^KM_47Z&HYRBNQFN^AFHI)F[PDHS_QBUY16?P6(AV\BC"IJN^CP]KEXAGQ:=P NSXL@[LHXKLFG#^QNSXL@[CYUMN987X> I^TJK*ABFVKXUCMPIOY25X(F[PDHSD@PCDNO+VYF[PDHS_KH349V4*OX^@E$KH@PAR[MGZOIS8;V"L]VNB]JJZEBDE%XSL]VNB]Q[WC@;;1^<"GPVHM,C@HXIZSEORGA[03^*DU^FJUBBRMJLM-P[PUBZVXNK>>4U1-J[SOH'NOESL]VNB]JJ^76U'KXUCMPIO]@AIJ(]ZOYS@[W309V4*OX^@E$KH@PAR[MGZOIS8;V"L]VNB]JJZEBDE%^SKOCLHLD75=R8&CTZDA GDL\EV_IKVCEW<?R.@QZJFYNFVIN@A!Z_SKPMKA4;2_;#DQYIN-DAKYF[PDHSD@T10_-EV_IKVCESNKCL.W\WQGSKDNTb>94U1-J[SOH'NOESL]VNB]JJ^76U'KXUCMPIO]@AIJ(izseoRczx^d\kpr4?2_;#DQYIN-DAKYF[PDHSD@T10_-EV_IKVCESNKCL.cp}keXe|rT~Razt218Q5)NW_CD#JKA_@QZJFYNFR;:Q#O\YOA\MKYDMEF$jlbcioe\kpr5n2_;#DQYIN-DAKYF[PDHSD@T10_-EV_IKVCESNKCL.dg5Zir|;l0Y=!F_WKL+BCIWHYRBNQFNZ32Y+GTQGITECQLEMN,ba4Xg|~9j6[?/H]UMJ)@MGUJ_T@L_HLX54[)IZSEORGA_BGOH*`c;Ve~x>>4U1-J[SOH'NOESL]VNB]JJ^76U'KXUCMPIO]@AIJ(e|r:Sb{{339V4*OX^@E$KH@PAR[MGZOIS8;V"L]VNB]JJZEBDE%ye~gag^mvp67<]9%BS[G@/FGM[DU^FJUBBV?>]/CP]KEXAGUHIAB urgq[lhXf:90Y=!F_WKL+BCIWHYRBNQFNZ31Y+GTQGITECQLEMN,EV_IKVLTAXV<3:W3+LYQAF%LICQNSXL@[LH\9;W%M^WAC^KM[FCKD&KXUCMPR^OV\63<]9%BS[G@/FGM[DU^FJUBBV?=]/CP]KEXAGUHIAB S^CP]KEXNVXNK>=4U1-J[SOH'NOESL]VNB]JJ^75U'KXUCMPIO]@AIJ([VKXUCMPRDE01>S7'@U]EB!HEO]BW\HDW@DP=?S!AR[MGZOIWJOG@"]PAR[MGZTXZLM8>6[?/H]UMJ)@MGUJ_T@L_HLX57[)IZSEORGA_BGOH*UX]ZOYS_KH319V4*OX^@E$KH@PAR[MGZOIS88V"L]VNB]JJZEBDE%^_H\PMTZ05>S7'@U]EB!HEO]BW\HDW@DP=?S!AR[MGZOIWJOG@"[PF@NOMKA482_;#DQYIN-DAKYF[PDHSD@T13_-EV_IKVCESNKCL.W\VLUNFN987X> I^TJK*ABFVKXUCMPIOY26X(F[PDHSD@PCDNO+PYT\H^HAIQa369V4*OX^@E$KH@PAR[MGZOIS88V"L]VNB]JJZEBDE%jt`l_lw{[cYh}}9<7X> I^TJK*ABFVKXUCMPIOY26X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww76=R8&CTZDA GDL\EV_IKVCEW<<R.@QZJFYNFVIN@A!iamnjjbYh}}8m7X> I^TJK*ABFVKXUCMPIOY26X(F[PDHSD@PCDNO+cb6Wf>k5Z0.K\RLI(OLDTM^WAC^KM_44Z&HYRBNQFN^AFHI)al;Udyy<i;T2,MZPNG&MNBRO\YOA\MK]6:T$J_T@L_HL\G@JK'on8Sb{{319V4*OX^@E$KH@PAR[MGZOIS88V"L]VNB]JJZEBDE%fyu?Potv06>S7'@U]EB!HEO]BW\HDW@DP=?S!AR[MGZOIWJOG@"|fshld[jss;81^<"GPVHM,C@HXIZSEORGA[00^*DU^FJUBBRMJLM-vw`tXagUe?>5Z0.K\RLI(OLDTM^WAC^KM_45Z&HYRBNQFN^AFHI)F[PDHSKQBUY10?P6(AV\BC"IJN^CP]KEXAGQ:?P NSXL@[LHXKLFG#L]VNB]Q[HS_;<1^<"GPVHM,C@HXIZSEORGA[01^*DU^FJUBBRMJLM-P[DU^FJUMS_KH329V4*OX^@E$KH@PAR[MGZOIS89V"L]VNB]JJZEBDE%XSL]VNB]QAB523\:$ERXFO.EFJZGTQGITECU>3\,BW\HDW@DTOHBC/R]BW\HDW[UYIJ==;T2,MZPNG&MNBRO\YOA\MK]6;T$J_T@L_HL\G@JK'ZU^_H\PRDE04>S7'@U]EB!HEO]BW\HDW@DP=>S!AR[MGZOIWJOG@"[\ES]NQ]563\:$ERXFO.EFJZGTQGITECU>3\,BW\HDW@DTOHBC/T]EEIJNFN9;7X> I^TJK*ABFVKXUCMPIOY27X(F[PDHSD@PCDNO+PYUAZCEK>=4U1-J[SOH'NOESL]VNB]JJ^74U'KXUCMPIO]@AIJ(]VY_MYMBD^l03>S7'@U]EB!HEO]BW\HDW@DP=>S!AR[MGZOIWJOG@"o|yoa\ip~XnVe~x>94U1-J[SOH'NOESL]VNB]JJ^74U'KXUCMPIO]@AIJ(izseoRczx^p\kpr4;2_;#DQYIN-DAKYF[PDHSD@T12_-EV_IKVCESNKCL.dbhioioVe~x?h4U1-J[SOH'NOESL]VNB]JJ^74U'KXUCMPIO]@AIJ(nm;Tcxz=f:W3+LYQAF%LICQNSXL@[LH\9:W%M^WAC^KM[FCKD&lo>Razt3d8Q5)NW_CD#JKA_@QZJFYNFR;8Q#O\YOA\MKYDMEF$ji=Potv04>S7'@U]EB!HEO]BW\HDW@DP=>S!AR[MGZOIWJOG@"czx0]lqq553\:$ERXFO.EFJZGTQGITECU>3\,BW\HDW@DTOHBC/skpmkaXg|~8=6[?/H]UMJ)@MGUJ_T@L_HLX56[)IZSEORGA_BGOH*stm{UbbR`<3:W3+LYQAF%LICQNSXL@[LH\9=W%M^WAC^KM[FCKD&KXUCMPF^OV\65<]9%BS[G@/FGM[DU^FJUBBV?;]/CP]KEXAGUHIAB AR[MGZTXE\R896[?/H]UMJ)@MGUJ_T@L_HLX51[)IZSEORGA_BGOH*UXIZSEORHPRDE07>S7'@U]EB!HEO]BW\HDW@DP=9S!AR[MGZOIWJOG@"]PAR[MGZTBO:?0Y=!F_WKL+BCIWHYRBNQFNZ37Y+GTQGITECQLEMN,WZGTQGIT^R\JG208Q5)NW_CD#JKA_@QZJFYNFR;?Q#O\YOA\MKYDMEF$_R[\ES]QAB573\:$ERXFO.EFJZGTQGITECU>4\,BW\HDW@DTOHBC/TQFVZKRP:;0Y=!F_WKL+BCIWHYRBNQFNZ37Y+GTQGITECQLEMN,QZ@FDECEK>>4U1-J[SOH'NOESL]VNB]JJ^73U'KXUCMPIO]@AIJ(]VXB_D@H329V4*OX^@E$KH@PAR[MGZOIS8>V"L]VNB]JJZEBDE%^S^ZNTBOG[k503\:$ERXFO.EFJZGTQGITECU>4\,BW\HDW@DTOHBC/`qzjfYj}qUmSb{{369V4*OX^@E$KH@PAR[MGZOIS8>V"L]VNB]JJZEBDE%jt`l_lw{[wYh}}987X> I^TJK*ABFVKXUCMPIOY20X(F[PDHSD@PCDNO+cgkd`dlSb{{2g9V4*OX^@E$KH@PAR[MGZOIS8>V"L]VNB]JJZEBDE%mh<Q`uu0e?P6(AV\BC"IJN^CP]KEXAGQ:8P NSXL@[LHXKLFG#kj=_nww6c=R8&CTZDA GDL\EV_IKVCEW<:R.@QZJFYNFVIN@A!id2]lqq573\:$ERXFO.EFJZGTQGITECU>4\,BW\HDW@DTOHBC/lw{5Zir|:80Y=!F_WKL+BCIWHYRBNQFNZ37Y+GTQGITECQLEMN,vlunfnUdyy=>;T2,MZPNG&MNBRO\YOA\MK]6<T$J_T@L_HL\G@JK'|yn~Rga_o10?P6(AV\BC"IJN^CP]KEXAGQ:9P NSXL@[LHXKLFG#L]VNB]E[HS_;:1^<"GPVHM,C@HXIZSEORGA[07^*DU^FJUBBRMJLM-BW\HDW[UFYU=:;T2,MZPNG&MNBRO\YOA\MK]6=T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB543\:$ERXFO.EFJZGTQGITECU>5\,BW\HDW@DTOHBC/R]BW\HDW[OL?85Z0.K\RLI(OLDTM^WAC^KM_43Z&HYRBNQFN^AFHI)TWHYRBNQ]_SGD77=R8&CTZDA GDL\EV_IKVCEW<;R.@QZJFYNFVIN@A!\_TQFVZTBO::0Y=!F_WKL+BCIWHYRBNQFNZ36Y+GTQGITECQLEMN,QVCUWD_S?<5Z0.K\RLI(OLDTM^WAC^KM_43Z&HYRBNQFN^AFHI)RWOKG@D@H319V4*OX^@E$KH@PAR[MGZOIS8?V"L]VNB]JJZEBDE%^S_G\IOE07>S7'@U]EB!HEO]BW\HDW@DP=8S!AR[MGZOIWJOG@"[PSUCWGHBXf:=0Y=!F_WKL+BCIWHYRBNQFNZ36Y+GTQGITECQLEMN,evikVg~tRhPotv03>S7'@U]EB!HEO]BW\HDW@DP=8S!AR[MGZOIWJOG@"o|yoa\ip~XzVe~x>=4U1-J[SOH'NOESL]VNB]JJ^72U'KXUCMPIO]@AIJ(nhfgeciPotv1b>S7'@U]EB!HEO]BW\HDW@DP=8S!AR[MGZOIWJOG@"hk1^mvp7`<]9%BS[G@/FGM[DU^FJUBBV?:]/CP]KEXAGUHIAB fe0\kpr5n2_;#DQYIN-DAKYF[PDHSD@T14_-EV_IKVCESNKCL.dg7Zir|::0Y=!F_WKL+BCIWHYRBNQFNZ36Y+GTQGITECQLEMN,ip~6Wf??5Z0.K\RLI(OLDTM^WAC^KM_43Z&HYRBNQFN^AFHI)uazcekRazt238Q5)NW_CD#JKA_@QZJFYNFR;>Q#O\YOA\MKYDMEF$y~k}_hl\j65<]9%BS[G@/FGM[DU^FJUBBV?9]/CP]KEXAGUHIAB AR[MGZ@XE\R8?6[?/H]UMJ)@MGUJ_T@L_HLX53[)IZSEORGA_BGOH*GTQGIT^RCZX278Q5)NW_CD#JKA_@QZJFYNFR;=Q#O\YOA\MKYDMEF$_RO\YOA\BZTBO:90Y=!F_WKL+BCIWHYRBNQFNZ35Y+GTQGITECQLEMN,WZGTQGIT^HI<5:W3+LYQAF%LICQNSXL@[LH\9?W%M^WAC^KM[FCKD&YTM^WAC^P\V@A4:2_;#DQYIN-DAKYF[PDHSD@T17_-EV_IKVCESNKCL.Q\QVCUW[OL?=5Z0.K\RLI(OLDTM^WAC^KM_40Z&HYRBNQFN^AFHI)R[LXTAXV<1:W3+LYQAF%LICQNSXL@[LH\9?W%M^WAC^KM[FCKD&_TJLBCIOE04>S7'@U]EB!HEO]BW\HDW@DP=;S!AR[MGZOIWJOG@"[PRHQJJB543\:$ERXFO.EFJZGTQGITECU>6\,BW\HDW@DTOHBC/T]PPDRDEMUe?:5Z0.K\RLI(OLDTM^WAC^KM_40Z&HYRBNQFN^AFHI)f{pdhS`{w_g]lqq503\:$ERXFO.EFJZGTQGITECU>6\,BW\HDW@DTOHBC/`qzjfYj}qUySb{{329V4*OX^@E$KH@PAR[MGZOIS8<V"L]VNB]JJZEBDE%mmabfnf]lqq4a3\:$ERXFO.EFJZGTQGITECU>6\,BW\HDW@DTOHBC/gf2[jss:o1^<"GPVHM,C@HXIZSEORGA[04^*DU^FJUBBRMJLM-e`7Yh}}8m7X> I^TJK*ABFVKXUCMPIOY22X(F[PDHSD@PCDNO+cb4Wf?=5Z0.K\RLI(OLDTM^WAC^KM_40Z&HYRBNQFN^AFHI)j}q;Tcxz<2:W3+LYQAF%LICQNSXL@[LH\9?W%M^WAC^KM[FCKD&xbd`h_nww74=R8&CTZDA GDL\EV_IKVCEW<8R.@QZJFYNFVIN@A!zsdp\mkYi;:1^<"GPVHM,C@HXIZSEORGA[05^*DU^FJUBBRMJLM-BW\HDWOUFYU=<;T2,MZPNG&MNBRO\YOA\MK]6?T$J_T@L_HL\G@JK'HYRBNQ]_LW[70=R8&CTZDA GDL\EV_IKVCEW<9R.@QZJFYNFVIN@A!\_@QZJFYAW[OL?>5Z0.K\RLI(OLDTM^WAC^KM_41Z&HYRBNQFN^AFHI)TWHYRBNQ]EF16?P6(AV\BC"IJN^CP]KEXAGQ:;P NSXL@[LHXKLFG#^QNSXL@[WYUMN997X> I^TJK*ABFVKXUCMPIOY23X(F[PDHSD@PCDNO+VYR[LXT^HI<0:W3+LYQAF%LICQNSXL@[LH\9>W%M^WAC^KM[FCKD&_XI_QBUY12?P6(AV\BC"IJN^CP]KEXAGQ:;P NSXL@[LHXKLFG#XQIAMNJJB573\:$ERXFO.EFJZGTQGITECU>7\,BW\HDW@DTOHBC/T]QMVOIO:90Y=!F_WKL+BCIWHYRBNQFNZ34Y+GTQGITECQLEMN,QZUSI]IFHR`<7:W3+LYQAF%LICQNSXL@[LH\9>W%M^WAC^KM[FCKD&kxucmPmtz\bZir|:=0Y=!F_WKL+BCIWHYRBNQFNZ34Y+GTQGITECQLEMN,evikVg~tR|Potv07>S7'@U]EB!HEO]BW\HDW@DP=:S!AR[MGZOIWJOG@"hnlmkmcZir|;l0Y=!F_WKL+BCIWHYRBNQFNZ34Y+GTQGITECQLEMN,ba7Xg|~9j6[?/H]UMJ)@MGUJ_T@L_HLX52[)IZSEORGA_BGOH*`c:Ve~x?h4U1-J[SOH'NOESL]VNB]JJ^70U'KXUCMPIO]@AIJ(nm9Tcxz<0:W3+LYQAF%LICQNSXL@[LH\9>W%M^WAC^KM[FCKD&g~t<Q`uu11?P6(AV\BC"IJN^CP]KEXAGQ:;P NSXL@[LHXKLFG#g|ioe\kpr492_;#DQYIN-DAKYF[PDHSD@T16_-EV_IKVCESNKCL.wpawYnfVd8?6[?/H]UMJ)@MGUJ_T@L_HLX5=[)IZSEORGA_BGOH*GTQGITJRCZX218Q5)NW_CD#JKA_@QZJFYNFR;3Q#O\YOA\MKYDMEF$M^WAC^P\IP^4=2_;#DQYIN-DAKYF[PDHSD@T19_-EV_IKVCESNKCL.Q\EV_IKVLT^HI<3:W3+LYQAF%LICQNSXL@[LH\91W%M^WAC^KM[FCKD&YTM^WAC^PFC63<]9%BS[G@/FGM[DU^FJUBBV?7]/CP]KEXAGUHIAB S^CP]KEXZVXNK><4U1-J[SOH'NOESL]VNB]JJ^7?U'KXUCMPIO]@AIJ([V_XI_Q]EF13?P6(AV\BC"IJN^CP]KEXAGQ:4P NSXL@[LHXKLFG#X]JR^OV\67<]9%BS[G@/FGM[DU^FJUBBV?7]/CP]KEXAGUHIAB U^DBHIOIO::0Y=!F_WKL+BCIWHYRBNQFNZ3;Y+GTQGITECQLEMN,QZTN[@DL?>5Z0.K\RLI(OLDTM^WAC^KM_4>Z&HYRBNQFN^AFHI)RWZ^JXNCK_o14?P6(AV\BC"IJN^CP]KEXAGQ:4P NSXL@[LHXKLFG#l}vnb]nq}YaWf?:5Z0.K\RLI(OLDTM^WAC^KM_4>Z&HYRBNQFN^AFHI)f{pdhS`{w_s]lqq543\:$ERXFO.EFJZGTQGITECU>8\,BW\HDW@DTOHBC/gcohlh`Wf>k5Z0.K\RLI(OLDTM^WAC^KM_4>Z&HYRBNQFN^AFHI)al8Udyy<i;T2,MZPNG&MNBRO\YOA\MK]60T$J_T@L_HL\G@JK'on9Sb{{2g9V4*OX^@E$KH@PAR[MGZOIS82V"L]VNB]JJZEBDE%mh>Q`uu13?P6(AV\BC"IJN^CP]KEXAGQ:4P NSXL@[LHXKLFG#`{w1^mvp64<]9%BS[G@/FGM[DU^FJUBBV?7]/CP]KEXAGUHIAB rhqjjbYh}}9:7X> I^TJK*ABFVKXUCMPIOY2<X(F[PDHSD@PCDNO+pubzVceSc=<;T2,MZPNG&MNBRO\YOA\MK]61T$J_T@L_HL\G@JK'HYRBNQI_LW[76=R8&CTZDA GDL\EV_IKVCEW<7R.@QZJFYNFVIN@A!NSXL@[WYJ]Q9>7X> I^TJK*ABFVKXUCMPIOY2=X(F[PDHSD@PCDNO+VYF[PDHSKQ]EF10?P6(AV\BC"IJN^CP]KEXAGQ:5P NSXL@[LHXKLFG#^QNSXL@[WC@;<1^<"GPVHM,C@HXIZSEORGA[0;^*DU^FJUBBRMJLM-P[DU^FJUYS_KH339V4*OX^@E$KH@PAR[MGZOIS83V"L]VNB]JJZEBDE%XSX]JR^PFC66<]9%BS[G@/FGM[DU^FJUBBV?6]/CP]KEXAGUHIAB URGQ[HS_;81^<"GPVHM,C@HXIZSEORGA[0;^*DU^FJUBBRMJLM-V[CGKD@DL?=5Z0.K\RLI(OLDTM^WAC^KM_4?Z&HYRBNQFN^AFHI)RW[CXECI<3:W3+LYQAF%LICQNSXL@[LH\90W%M^WAC^KM[FCKD&_T_YO[CLF\j61<]9%BS[G@/FGM[DU^FJUBBV?6]/CP]KEXAGUHIAB ar{mgZkrpVlTcxz<7:W3+LYQAF%LICQNSXL@[LH\90W%M^WAC^KM[FCKD&kxucmPmtz\vZir|:90Y=!F_WKL+BCIWHYRBNQFNZ3:Y+GTQGITECQLEMN,bdjkagmTcxz=f:W3+LYQAF%LICQNSXL@[LH\90W%M^WAC^KM[FCKD&lo=Razt3d8Q5)NW_CD#JKA_@QZJFYNFR;2Q#O\YOA\MKYDMEF$ji<Potv1b>S7'@U]EB!HEO]BW\HDW@DP=4S!AR[MGZOIWJOG@"hk3^mvp66<]9%BS[G@/FGM[DU^FJUBBV?6]/CP]KEXAGUHIAB mtz2[jss;;1^<"GPVHM,C@HXIZSEORGA[0;^*DU^FJUBBRMJLM-qmvoioVe~x>?4U1-J[SOH'NOESL]VNB]JJ^7>U'KXUCMPIO]@AIJ(}zoySd`Pn208Q5)NW_CD#JKA_@QZJFYNFR;V"L]VNB]JJZEBDE%J_T@L_G]NQ]553\:$ERXFO.EFJZGTQGITECU>]/CP]KEXAGUHIAB AR[MGZTXE\R886[?/H]UMJ)@MGUJ_T@L_HLX5X(F[PDHSD@PCDNO+VYF[PDHSKQ]EF11?P6(AV\BC"IJN^CP]KEXAGQ:Q#O\YOA\MKYDMEF$_RO\YOA\V@A4<2_;#DQYIN-DAKYF[PDHSD@T1\,BW\HDW@DTOHBC/R]BW\HDW[UYIJ=>;T2,MZPNG&MNBRO\YOA\MK]6U'KXUCMPIO]@AIJ([V_XI_Q]EF0e?P6(AV\BC"IJN^CP]KEXAGQ:Q#O\YOA\MKYDMEF$Y^K]_LW[75=R8&CTZDA GDL\EV_IKVCEW<S!AR[MGZOIWJOG@"[PF@NOMKA5n2_;#DQYIN-DAKYF[PDHSD@T1\,BW\HDW@DTOHBC/T]QMVOIO:80Y=!F_WKL+BCIWHYRBNQFNZ3^*DU^FJUBBRMJLM-V[VRF\JGOSc=9;T2,MZPNG&MNBRO\YOA\MK]6U'KXUCMPIO]@AIJ(izseoRczx^d\kpr4>2_;#DQYIN-DAKYF[PDHSD@T1\,BW\HDW@DTOHBC/`qzjfYj}qUySb{{339V4*OX^@E$KH@PAR[MGZOIS8W%M^WAC^KM[FCKD&lj`agag^mvp7c<]9%BS[G@/FGM[DU^FJUBBV?R.@QZJFYNFVIN@A!id0]lqq4b3\:$ERXFO.EFJZGTQGITECU>]/CP]KEXAGUHIAB fe0\kpr5m2_;#DQYIN-DAKYF[PDHSD@T1\,BW\HDW@DTOHBC/gf0[jss:o1^<"GPVHM,C@HXIZSEORGA[0_-EV_IKVCESNKCL.ov|4Yh}}9:7X> I^TJK*ABFVKXUCMPIOY2Y+GTQGITECQLEMN,vlunfnUdyy=?;T2,MZPNG&MNBRO\YOA\MK]6U'KXUCMPIO]@AIJ(}zoySd`Pn218Q5)NW_CD#JKA_@QZJFYNFR8;Q#O\YOA\MKYDMEF$M^WAC^D\IP^4;2_;#DQYIN-DAKYF[PDHSD@T21_-EV_IKVCESNKCL.CP]KEXZVG^T>;4U1-J[SOH'NOESL]VNB]JJ^47U'KXUCMPIO]@AIJ([VKXUCMPF^PFC65<]9%BS[G@/FGM[DU^FJUBBV<?]/CP]KEXAGUHIAB S^CP]KEXZLM896[?/H]UMJ)@MGUJ_T@L_HLX65[)IZSEORGA_BGOH*UXIZSEOR\PRDE06>S7'@U]EB!HEO]BW\HDW@DP>=S!AR[MGZOIWJOG@"]PURGQ[WC@;91^<"GPVHM,C@HXIZSEORGA[32^*DU^FJUBBRMJLM-VW@TXE\R8=6[?/H]UMJ)@MGUJ_T@L_HLX65[)IZSEORGA_BGOH*SXNHFGECI<0:W3+LYQAF%LICQNSXL@[LH\:9W%M^WAC^KM[FCKD&_T^D]FNF10?P6(AV\BC"IJN^CP]KEXAGQ9<P NSXL@[LHXKLFG#XQ\T@V@IAYi;>1^<"GPVHM,C@HXIZSEORGA[32^*DU^FJUBBRMJLM-bw|hdWdsSkQ`uu14?P6(AV\BC"IJN^CP]KEXAGQ9<P NSXL@[LHXKLFG#l}vnb]nq}YuWf?>5Z0.K\RLI(OLDTM^WAC^KM_76Z&HYRBNQFN^AFHI)aiefbbjQ`uu0e?P6(AV\BC"IJN^CP]KEXAGQ9<P NSXL@[LHXKLFG#kj>_nww6c=R8&CTZDA GDL\EV_IKVCEW?>R.@QZJFYNFVIN@A!id3]lqq4a3\:$ERXFO.EFJZGTQGITECU=0\,BW\HDW@DTOHBC/gf0[jss;91^<"GPVHM,C@HXIZSEORGA[32^*DU^FJUBBRMJLM-nq}7Xg|~8>6[?/H]UMJ)@MGUJ_T@L_HLX65[)IZSEORGA_BGOH*tn{`dlSb{{309V4*OX^@E$KH@PAR[MGZOIS;:V"L]VNB]JJZEBDE%~h|Pio]m76=R8&CTZDA GDL\EV_IKVCEW??R.@QZJFYNFVIN@A!NSXL@[CYJ]Q987X> I^TJK*ABFVKXUCMPIOY15X(F[PDHSD@PCDNO+DU^FJUYS@[W349V4*OX^@E$KH@PAR[MGZOIS;;V"L]VNB]JJZEBDE%XSL]VNB]E[WC@;:1^<"GPVHM,C@HXIZSEORGA[33^*DU^FJUBBRMJLM-P[DU^FJUYIJ=:;T2,MZPNG&MNBRO\YOA\MK]59T$J_T@L_HL\G@JK'ZUJ_T@L_S]QAB553\:$ERXFO.EFJZGTQGITECU=1\,BW\HDW@DTOHBC/R]VW@TXZLM8<6[?/H]UMJ)@MGUJ_T@L_HLX64[)IZSEORGA_BGOH*STM[UFYU=>;T2,MZPNG&MNBRO\YOA\MK]59T$J_T@L_HL\G@JK'\UMMABFNF13?P6(AV\BC"IJN^CP]KEXAGQ9=P NSXL@[LHXKLFG#XQ]IRKMC65<]9%BS[G@/FGM[DU^FJUBBV<>]/CP]KEXAGUHIAB U^QWEQEJLVd8;6[?/H]UMJ)@MGUJ_T@L_HLX64[)IZSEORGA_BGOH*gtqgiTaxvPf^mvp61<]9%BS[G@/FGM[DU^FJUBBV<>]/CP]KEXAGUHIAB ar{mgZkrpVxTcxz<3:W3+LYQAF%LICQNSXL@[LH\:8W%M^WAC^KM[FCKD&lj`agag^mvp7`<]9%BS[G@/FGM[DU^FJUBBV<>]/CP]KEXAGUHIAB fe3\kpr5n2_;#DQYIN-DAKYF[PDHSD@T20_-EV_IKVCESNKCL.dg6Zir|;l0Y=!F_WKL+BCIWHYRBNQFNZ02Y+GTQGITECQLEMN,ba5Xg|~8<6[?/H]UMJ)@MGUJ_T@L_HLX64[)IZSEORGA_BGOH*krp8Udyy==;T2,MZPNG&MNBRO\YOA\MK]59T$J_T@L_HL\G@JK'{cxeciPotv05>S7'@U]EB!HEO]BW\HDW@DP><S!AR[MGZOIWJOG@"{|es]jjZh4;2_;#DQYIN-DAKYF[PDHSD@T23_-EV_IKVCESNKCL.CP]KEXNVG^T>=4U1-J[SOH'NOESL]VNB]JJ^45U'KXUCMPIO]@AIJ(IZSEOR\PMTZ01>S7'@U]EB!HEO]BW\HDW@DP>?S!AR[MGZOIWJOG@"]PAR[MGZ@XZLM8?6[?/H]UMJ)@MGUJ_T@L_HLX67[)IZSEORGA_BGOH*UXIZSEOR\JG278Q5)NW_CD#JKA_@QZJFYNFR89Q#O\YOA\MKYDMEF$_RO\YOA\VZTBO:80Y=!F_WKL+BCIWHYRBNQFNZ01Y+GTQGITECQLEMN,WZSTM[UYIJ=?;T2,MZPNG&MNBRO\YOA\MK]5:T$J_T@L_HL\G@JK'\YN^RCZX238Q5)NW_CD#JKA_@QZJFYNFR89Q#O\YOA\MKYDMEF$YRHNLMKMC66<]9%BS[G@/FGM[DU^FJUBBV<=]/CP]KEXAGUHIAB U^PJWLH@;:1^<"GPVHM,C@HXIZSEORGA[30^*DU^FJUBBRMJLM-V[VRF\JGOSc=8;T2,MZPNG&MNBRO\YOA\MK]5:T$J_T@L_HL\G@JK'hyrbnQbuy]e[jss;>1^<"GPVHM,C@HXIZSEORGA[30^*DU^FJUBBRMJLM-bw|hdWdsSQ`uu10?P6(AV\BC"IJN^CP]KEXAGQ9>P NSXL@[LHXKLFG#koclhld[jss:o1^<"GPVHM,C@HXIZSEORGA[30^*DU^FJUBBRMJLM-e`4Yh}}8m7X> I^TJK*ABFVKXUCMPIOY16X(F[PDHSD@PCDNO+cb5Wf>k5Z0.K\RLI(OLDTM^WAC^KM_74Z&HYRBNQFN^AFHI)al:Udyy=?;T2,MZPNG&MNBRO\YOA\MK]5:T$J_T@L_HL\G@JK'ds=Razt208Q5)NW_CD#JKA_@QZJFYNFR89Q#O\YOA\MKYDMEF$~d}fnf]lqq563\:$ERXFO.EFJZGTQGITECU=2\,BW\HDW@DTOHBC/tqfvZoiWg987X> I^TJK*ABFVKXUCMPIOY17X(F[PDHSD@PCDNO+DU^FJUMS@[W329V4*OX^@E$KH@PAR[MGZOIS;9V"L]VNB]JJZEBDE%J_T@L_S]NQ]523\:$ERXFO.EFJZGTQGITECU=3\,BW\HDW@DTOHBC/R]BW\HDWOUYIJ=<;T2,MZPNG&MNBRO\YOA\MK]5;T$J_T@L_HL\G@JK'ZUJ_T@L_SGD70=R8&CTZDA GDL\EV_IKVCEW?=R.@QZJFYNFVIN@A!\_@QZJFYUW[OL??5Z0.K\RLI(OLDTM^WAC^KM_75Z&HYRBNQFN^AFHI)TW\YN^R\JG228Q5)NW_CD#JKA_@QZJFYNFR88Q#O\YOA\MKYDMEF$Y^K]_LW[74=R8&CTZDA GDL\EV_IKVCEW?=R.@QZJFYNFVIN@A!Z_GCOHLH@;91^<"GPVHM,C@HXIZSEORGA[31^*DU^FJUBBRMJLM-V[WOTAGM8?6[?/H]UMJ)@MGUJ_T@L_HLX66[)IZSEORGA_BGOH*SX[]K_O@JPn258Q5)NW_CD#JKA_@QZJFYNFR88Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8;6[?/H]UMJ)@MGUJ_T@L_HLX66[)IZSEORGA_BGOH*gtqgiTaxvPr^mvp65<]9%BS[G@/FGM[DU^FJUBBV<<]/CP]KEXAGUHIAB f`nomkaXg|~9j6[?/H]UMJ)@MGUJ_T@L_HLX66[)IZSEORGA_BGOH*`c9Ve~x?h4U1-J[SOH'NOESL]VNB]JJ^44U'KXUCMPIO]@AIJ(nm8Tcxz=f:W3+LYQAF%LICQNSXL@[LH\::W%M^WAC^KM[FCKD&lo?Razt228Q5)NW_CD#JKA_@QZJFYNFR88Q#O\YOA\MKYDMEF$axv>_nww77=R8&CTZDA GDL\EV_IKVCEW?=R.@QZJFYNFVIN@A!}irkmcZir|:;0Y=!F_WKL+BCIWHYRBNQFNZ00Y+GTQGITECQLEMN,qvcuW`dTb>=4U1-J[SOH'NOESL]VNB]JJ^43U'KXUCMPIO]@AIJ(IZSEORHPMTZ07>S7'@U]EB!HEO]BW\HDW@DP>9S!AR[MGZOIWJOG@"O\YOA\VZKRP:?0Y=!F_WKL+BCIWHYRBNQFNZ07Y+GTQGITECQLEMN,WZGTQGITJR\JG218Q5)NW_CD#JKA_@QZJFYNFR8?Q#O\YOA\MKYDMEF$_RO\YOA\V@A4=2_;#DQYIN-DAKYF[PDHSD@T25_-EV_IKVCESNKCL.Q\EV_IKVXT^HI<2:W3+LYQAF%LICQNSXL@[LH\:=W%M^WAC^KM[FCKD&YTY^K]_SGD75=R8&CTZDA GDL\EV_IKVCEW?:R.@QZJFYNFVIN@A!ZSDP\IP^492_;#DQYIN-DAKYF[PDHSD@T25_-EV_IKVCESNKCL.W\BDJKAGM8<6[?/H]UMJ)@MGUJ_T@L_HLX61[)IZSEORGA_BGOH*SXZ@YBBJ=<;T2,MZPNG&MNBRO\YOA\MK]5<T$J_T@L_HL\G@JK'\UXXLZLME]m72=R8&CTZDA GDL\EV_IKVCEW?:R.@QZJFYNFVIN@A!nsxl`[hsWoUdyy=8;T2,MZPNG&MNBRO\YOA\MK]5<T$J_T@L_HL\G@JK'hyrbnQbuy]q[jss;:1^<"GPVHM,C@HXIZSEORGA[36^*DU^FJUBBRMJLM-eeijnfnUdyy<i;T2,MZPNG&MNBRO\YOA\MK]5<T$J_T@L_HL\G@JK'on:Sb{{2g9V4*OX^@E$KH@PAR[MGZOIS;>V"L]VNB]JJZEBDE%mh?Q`uu0e?P6(AV\BC"IJN^CP]KEXAGQ98P NSXL@[LHXKLFG#kj<_nww75=R8&CTZDA GDL\EV_IKVCEW?:R.@QZJFYNFVIN@A!buy3\kpr4:2_;#DQYIN-DAKYF[PDHSD@T25_-EV_IKVCESNKCL.pjwlh`Wf?<5Z0.K\RLI(OLDTM^WAC^KM_72Z&HYRBNQFN^AFHI)r{lxTecQa329V4*OX^@E$KH@PAR[MGZOIS;?V"L]VNB]JJZEBDE%J_T@L_G]NQ]543\:$ERXFO.EFJZGTQGITECU=5\,BW\HDW@DTOHBC/@QZJFYUWD_S?85Z0.K\RLI(OLDTM^WAC^KM_73Z&HYRBNQFN^AFHI)TWHYRBNQI_SGD76=R8&CTZDA GDL\EV_IKVCEW?;R.@QZJFYNFVIN@A!\_@QZJFYUMN9>7X> I^TJK*ABFVKXUCMPIOY11X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF11?P6(AV\BC"IJN^CP]KEXAGQ99P NSXL@[LHXKLFG#^QZSDP\V@A482_;#DQYIN-DAKYF[PDHSD@T24_-EV_IKVCESNKCL.WPAWYJ]Q9:7X> I^TJK*ABFVKXUCMPIOY11X(F[PDHSD@PCDNO+PYAIEFBBJ=?;T2,MZPNG&MNBRO\YOA\MK]5=T$J_T@L_HL\G@JK'\UYE^GAG218Q5)NW_CD#JKA_@QZJFYNFR8>Q#O\YOA\MKYDMEF$YR][AUAN@Zh4?2_;#DQYIN-DAKYF[PDHSD@T24_-EV_IKVCESNKCL.cp}keXe|rTjRazt258Q5)NW_CD#JKA_@QZJFYNFR8>Q#O\YOA\MKYDMEF$m~wac^ov|ZtXg|~8?6[?/H]UMJ)@MGUJ_T@L_HLX60[)IZSEORGA_BGOH*`fdecekRazt3d8Q5)NW_CD#JKA_@QZJFYNFR8>Q#O\YOA\MKYDMEF$ji?Potv1b>S7'@U]EB!HEO]BW\HDW@DP>8S!AR[MGZOIWJOG@"hk2^mvp7`<]9%BS[G@/FGM[DU^FJUBBV<:]/CP]KEXAGUHIAB fe1\kpr482_;#DQYIN-DAKYF[PDHSD@T24_-EV_IKVCESNKCL.ov|4Yh}}997X> I^TJK*ABFVKXUCMPIOY11X(F[PDHSD@PCDNO+wotagmTcxz<1:W3+LYQAF%LICQNSXL@[LH\:<W%M^WAC^KM[FCKD&xiQfn^l07>S7'@U]EB!HEO]BW\HDW@DP>;S!AR[MGZOIWJOG@"O\YOA\BZKRP:90Y=!F_WKL+BCIWHYRBNQFNZ05Y+GTQGITECQLEMN,EV_IKVXTAXV<5:W3+LYQAF%LICQNSXL@[LH\:?W%M^WAC^KM[FCKD&YTM^WAC^D\V@A4;2_;#DQYIN-DAKYF[PDHSD@T27_-EV_IKVCESNKCL.Q\EV_IKVXNK>;4U1-J[SOH'NOESL]VNB]JJ^41U'KXUCMPIO]@AIJ([VKXUCMPR^PFC64<]9%BS[G@/FGM[DU^FJUBBV<9]/CP]KEXAGUHIAB S^WPAWYUMN9;7X> I^TJK*ABFVKXUCMPIOY12X(F[PDHSD@PCDNO+PUBZVG^T>?4U1-J[SOH'NOESL]VNB]JJ^41U'KXUCMPIO]@AIJ(]VLJ@AGAG228Q5)NW_CD#JKA_@QZJFYNFR8=Q#O\YOA\MKYDMEF$YR\FSHLD76=R8&CTZDA GDL\EV_IKVCEW?8R.@QZJFYNFVIN@A!Z_RVBPFKCWg9<7X> I^TJK*ABFVKXUCMPIOY12X(F[PDHSD@PCDNO+du~fjUfyuQi_nww72=R8&CTZDA GDL\EV_IKVCEW?8R.@QZJFYNFVIN@A!nsxl`[hsW{Udyy=<;T2,MZPNG&MNBRO\YOA\MK]5>T$J_T@L_HL\G@JK'okg`d`h_nww6c=R8&CTZDA GDL\EV_IKVCEW?8R.@QZJFYNFVIN@A!id0]lqq4a3\:$ERXFO.EFJZGTQGITECU=6\,BW\HDW@DTOHBC/gf1[jss:o1^<"GPVHM,C@HXIZSEORGA[34^*DU^FJUBBRMJLM-e`6Yh}}9;7X> I^TJK*ABFVKXUCMPIOY12X(F[PDHSD@PCDNO+hs9Ve~x><4U1-J[SOH'NOESL]VNB]JJ^41U'KXUCMPIO]@AIJ(z`ybbjQ`uu12?P6(AV\BC"IJN^CP]KEXAGQ9:P NSXL@[LHXKLFG#x}jr^km[k543\:$ERXFO.EFJZGTQGITECU=7\,BW\HDW@DTOHBC/@QZJFYAWD_S?>5Z0.K\RLI(OLDTM^WAC^KM_71Z&HYRBNQFN^AFHI)F[PDHS_QBUY16?P6(AV\BC"IJN^CP]KEXAGQ9;P NSXL@[LHXKLFG#^QNSXL@[CYUMN987X> I^TJK*ABFVKXUCMPIOY13X(F[PDHSD@PCDNO+VYF[PDHS_KH349V4*OX^@E$KH@PAR[MGZOIS;=V"L]VNB]JJZEBDE%XSL]VNB]Q[WC@;;1^<"GPVHM,C@HXIZSEORGA[35^*DU^FJUBBRMJLM-P[PUBZVXNK>>4U1-J[SOH'NOESL]VNB]JJ^40U'KXUCMPIO]@AIJ(]ZOYS@[W309V4*OX^@E$KH@PAR[MGZOIS;=V"L]VNB]JJZEBDE%^SKOCLHLD75=R8&CTZDA GDL\EV_IKVCEW?9R.@QZJFYNFVIN@A!Z_SKPMKA4;2_;#DQYIN-DAKYF[PDHSD@T26_-EV_IKVCESNKCL.W\WQGSKDNTb>94U1-J[SOH'NOESL]VNB]JJ^40U'KXUCMPIO]@AIJ(izseoRczx^d\kpr4?2_;#DQYIN-DAKYF[PDHSD@T26_-EV_IKVCESNKCL.cp}keXe|rT~Razt218Q5)NW_CD#JKA_@QZJFYNFR8<Q#O\YOA\MKYDMEF$jlbcioe\kpr5n2_;#DQYIN-DAKYF[PDHSD@T26_-EV_IKVCESNKCL.dg5Zir|;l0Y=!F_WKL+BCIWHYRBNQFNZ04Y+GTQGITECQLEMN,ba4Xg|~9j6[?/H]UMJ)@MGUJ_T@L_HLX62[)IZSEORGA_BGOH*`c;Ve~x>>4U1-J[SOH'NOESL]VNB]JJ^40U'KXUCMPIO]@AIJ(e|r:Sb{{339V4*OX^@E$KH@PAR[MGZOIS;=V"L]VNB]JJZEBDE%ye~gag^mvp67<]9%BS[G@/FGM[DU^FJUBBV<8]/CP]KEXAGUHIAB urgq[lhXf:90Y=!F_WKL+BCIWHYRBNQFNZ0;Y+GTQGITECQLEMN,EV_IKVLTAXV<3:W3+LYQAF%LICQNSXL@[LH\:1W%M^WAC^KM[FCKD&KXUCMPR^OV\63<]9%BS[G@/FGM[DU^FJUBBV<7]/CP]KEXAGUHIAB S^CP]KEXNVXNK>=4U1-J[SOH'NOESL]VNB]JJ^4?U'KXUCMPIO]@AIJ([VKXUCMPRDE01>S7'@U]EB!HEO]BW\HDW@DP>5S!AR[MGZOIWJOG@"]PAR[MGZTXZLM8>6[?/H]UMJ)@MGUJ_T@L_HLX6=[)IZSEORGA_BGOH*UX]ZOYS_KH319V4*OX^@E$KH@PAR[MGZOIS;2V"L]VNB]JJZEBDE%^_H\PMTZ05>S7'@U]EB!HEO]BW\HDW@DP>5S!AR[MGZOIWJOG@"[PF@NOMKA482_;#DQYIN-DAKYF[PDHSD@T29_-EV_IKVCESNKCL.W\VLUNFN987X> I^TJK*ABFVKXUCMPIOY1<X(F[PDHSD@PCDNO+PYT\H^HAIQa369V4*OX^@E$KH@PAR[MGZOIS;2V"L]VNB]JJZEBDE%jt`l_lw{[cYh}}9<7X> I^TJK*ABFVKXUCMPIOY1<X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww76=R8&CTZDA GDL\EV_IKVCEW?6R.@QZJFYNFVIN@A!iamnjjbYh}}8m7X> I^TJK*ABFVKXUCMPIOY1<X(F[PDHSD@PCDNO+cb6Wf>k5Z0.K\RLI(OLDTM^WAC^KM_7>Z&HYRBNQFN^AFHI)al;Udyy<i;T2,MZPNG&MNBRO\YOA\MK]50T$J_T@L_HL\G@JK'on8Sb{{319V4*OX^@E$KH@PAR[MGZOIS;2V"L]VNB]JJZEBDE%fyu?Potv06>S7'@U]EB!HEO]BW\HDW@DP>5S!AR[MGZOIWJOG@"|fshld[jss;81^<"GPVHM,C@HXIZSEORGA[3:^*DU^FJUBBRMJLM-vw`tXagUe?>5Z0.K\RLI(OLDTM^WAC^KM_7?Z&HYRBNQFN^AFHI)F[PDHSKQBUY10?P6(AV\BC"IJN^CP]KEXAGQ95P NSXL@[LHXKLFG#L]VNB]Q[HS_;<1^<"GPVHM,C@HXIZSEORGA[3;^*DU^FJUBBRMJLM-P[DU^FJUMS_KH329V4*OX^@E$KH@PAR[MGZOIS;3V"L]VNB]JJZEBDE%XSL]VNB]QAB523\:$ERXFO.EFJZGTQGITECU=9\,BW\HDW@DTOHBC/R]BW\HDW[UYIJ==;T2,MZPNG&MNBRO\YOA\MK]51T$J_T@L_HL\G@JK'ZU^_H\PRDE04>S7'@U]EB!HEO]BW\HDW@DP>4S!AR[MGZOIWJOG@"[\ES]NQ]563\:$ERXFO.EFJZGTQGITECU=9\,BW\HDW@DTOHBC/T]EEIJNFN9;7X> I^TJK*ABFVKXUCMPIOY1=X(F[PDHSD@PCDNO+PYUAZCEK>=4U1-J[SOH'NOESL]VNB]JJ^4>U'KXUCMPIO]@AIJ(]VY_MYMBD^l03>S7'@U]EB!HEO]BW\HDW@DP>4S!AR[MGZOIWJOG@"o|yoa\ip~XnVe~x>94U1-J[SOH'NOESL]VNB]JJ^4>U'KXUCMPIO]@AIJ(izseoRczx^p\kpr4;2_;#DQYIN-DAKYF[PDHSD@T28_-EV_IKVCESNKCL.dbhioioVe~x?h4U1-J[SOH'NOESL]VNB]JJ^4>U'KXUCMPIO]@AIJ(nm;Tcxz=f:W3+LYQAF%LICQNSXL@[LH\:0W%M^WAC^KM[FCKD&lo>Razt3d8Q5)NW_CD#JKA_@QZJFYNFR82Q#O\YOA\MKYDMEF$ji=Potv04>S7'@U]EB!HEO]BW\HDW@DP>4S!AR[MGZOIWJOG@"czx0]lqq553\:$ERXFO.EFJZGTQGITECU=9\,BW\HDW@DTOHBC/skpmkaXg|~8=6[?/H]UMJ)@MGUJ_T@L_HLX6<[)IZSEORGA_BGOH*stm{UbbR`<2:W3+LYQAF%LICQNSXL@[LH\:T$J_T@L_HL\G@JK'HYRBNQI_LW[77=R8&CTZDA GDL\EV_IKVCEW?S!AR[MGZOIWJOG@"O\YOA\VZKRP:>0Y=!F_WKL+BCIWHYRBNQFNZ0^*DU^FJUBBRMJLM-P[DU^FJUMS_KH339V4*OX^@E$KH@PAR[MGZOIS;W%M^WAC^KM[FCKD&YTM^WAC^PFC62<]9%BS[G@/FGM[DU^FJUBBV<R.@QZJFYNFVIN@A!\_@QZJFYUW[OL?<5Z0.K\RLI(OLDTM^WAC^KM_7[)IZSEORGA_BGOH*UX]ZOYS_KH2g9V4*OX^@E$KH@PAR[MGZOIS;W%M^WAC^KM[FCKD&_XI_QBUY13?P6(AV\BC"IJN^CP]KEXAGQ9Q#O\YOA\MKYDMEF$YRHNLMKMC7`<]9%BS[G@/FGM[DU^FJUBBV<R.@QZJFYNFVIN@A!Z_SKPMKA4:2_;#DQYIN-DAKYF[PDHSD@T2\,BW\HDW@DTOHBC/T]PPDRDEMUe?;5Z0.K\RLI(OLDTM^WAC^KM_7[)IZSEORGA_BGOH*gtqgiTaxvPf^mvp60<]9%BS[G@/FGM[DU^FJUBBV<R.@QZJFYNFVIN@A!nsxl`[hsW{Udyy==;T2,MZPNG&MNBRO\YOA\MK]5U'KXUCMPIO]@AIJ(nhfgeciPotv1a>S7'@U]EB!HEO]BW\HDW@DP>P NSXL@[LHXKLFG#kj>_nww6`=R8&CTZDA GDL\EV_IKVCEW?S!AR[MGZOIWJOG@"hk2^mvp7c<]9%BS[G@/FGM[DU^FJUBBV<R.@QZJFYNFVIN@A!id2]lqq4a3\:$ERXFO.EFJZGTQGITECU=]/CP]KEXAGUHIAB mtz2[jss;81^<"GPVHM,C@HXIZSEORGA[3_-EV_IKVCESNKCL.pjwlh`Wf?=5Z0.K\RLI(OLDTM^WAC^KM_7[)IZSEORGA_BGOH*stm{UbbR`<3:W3+LYQAF%LICQNSXL@[LH\;9W%M^WAC^KM[FCKD&KXUCMPF^OV\65<]9%BS[G@/FGM[DU^FJUBBV=?]/CP]KEXAGUHIAB AR[MGZTXE\R896[?/H]UMJ)@MGUJ_T@L_HLX75[)IZSEORGA_BGOH*UXIZSEORHPRDE07>S7'@U]EB!HEO]BW\HDW@DP?=S!AR[MGZOIWJOG@"]PAR[MGZTBO:?0Y=!F_WKL+BCIWHYRBNQFNZ13Y+GTQGITECQLEMN,WZGTQGIT^R\JG208Q5)NW_CD#JKA_@QZJFYNFR9;Q#O\YOA\MKYDMEF$_R[\ES]QAB573\:$ERXFO.EFJZGTQGITECU<0\,BW\HDW@DTOHBC/TQFVZKRP:;0Y=!F_WKL+BCIWHYRBNQFNZ13Y+GTQGITECQLEMN,QZ@FDECEK>>4U1-J[SOH'NOESL]VNB]JJ^57U'KXUCMPIO]@AIJ(]VXB_D@H329V4*OX^@E$KH@PAR[MGZOIS::V"L]VNB]JJZEBDE%^S^ZNTBOG[k503\:$ERXFO.EFJZGTQGITECU<0\,BW\HDW@DTOHBC/`qzjfYj}qUmSb{{369V4*OX^@E$KH@PAR[MGZOIS::V"L]VNB]JJZEBDE%jt`l_lw{[wYh}}987X> I^TJK*ABFVKXUCMPIOY04X(F[PDHSD@PCDNO+cgkd`dlSb{{2g9V4*OX^@E$KH@PAR[MGZOIS::V"L]VNB]JJZEBDE%mh<Q`uu0e?P6(AV\BC"IJN^CP]KEXAGQ8<P NSXL@[LHXKLFG#kj=_nww6c=R8&CTZDA GDL\EV_IKVCEW>>R.@QZJFYNFVIN@A!id2]lqq573\:$ERXFO.EFJZGTQGITECU<0\,BW\HDW@DTOHBC/lw{5Zir|:80Y=!F_WKL+BCIWHYRBNQFNZ13Y+GTQGITECQLEMN,vlunfnUdyy=>;T2,MZPNG&MNBRO\YOA\MK]48T$J_T@L_HL\G@JK'|yn~Rga_o10?P6(AV\BC"IJN^CP]KEXAGQ8=P NSXL@[LHXKLFG#L]VNB]E[HS_;:1^<"GPVHM,C@HXIZSEORGA[23^*DU^FJUBBRMJLM-BW\HDW[UFYU=:;T2,MZPNG&MNBRO\YOA\MK]49T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB543\:$ERXFO.EFJZGTQGITECU<1\,BW\HDW@DTOHBC/R]BW\HDW[OL?85Z0.K\RLI(OLDTM^WAC^KM_67Z&HYRBNQFN^AFHI)TWHYRBNQ]_SGD77=R8&CTZDA GDL\EV_IKVCEW>?R.@QZJFYNFVIN@A!\_TQFVZTBO::0Y=!F_WKL+BCIWHYRBNQFNZ12Y+GTQGITECQLEMN,QVCUWD_S?<5Z0.K\RLI(OLDTM^WAC^KM_67Z&HYRBNQFN^AFHI)RWOKG@D@H319V4*OX^@E$KH@PAR[MGZOIS:;V"L]VNB]JJZEBDE%^S_G\IOE07>S7'@U]EB!HEO]BW\HDW@DP?<S!AR[MGZOIWJOG@"[PSUCWGHBXf:=0Y=!F_WKL+BCIWHYRBNQFNZ12Y+GTQGITECQLEMN,evikVg~tRhPotv03>S7'@U]EB!HEO]BW\HDW@DP?<S!AR[MGZOIWJOG@"o|yoa\ip~XzVe~x>=4U1-J[SOH'NOESL]VNB]JJ^56U'KXUCMPIO]@AIJ(nhfgeciPotv1b>S7'@U]EB!HEO]BW\HDW@DP?<S!AR[MGZOIWJOG@"hk1^mvp7`<]9%BS[G@/FGM[DU^FJUBBV=>]/CP]KEXAGUHIAB fe0\kpr5n2_;#DQYIN-DAKYF[PDHSD@T30_-EV_IKVCESNKCL.dg7Zir|::0Y=!F_WKL+BCIWHYRBNQFNZ12Y+GTQGITECQLEMN,ip~6Wf??5Z0.K\RLI(OLDTM^WAC^KM_67Z&HYRBNQFN^AFHI)uazcekRazt238Q5)NW_CD#JKA_@QZJFYNFR9:Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV=R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY0Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\;T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU<]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX7X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ8Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU<]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[2_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX7X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^5Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ8Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX7X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW>S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ1^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY0Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX7X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_6[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]4U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ8Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV:R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY7Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\<T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU;]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX0X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ?Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU;]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[5_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX0X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^2Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ?Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX0X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW9S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ6^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY7Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX0X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_1[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]3U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ?Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV;R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY6Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\=T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU:]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX1X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ>Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU:]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[4_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX1X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^3Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ>Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX1X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW8S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ7^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY6Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX1X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_0[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]2U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ>Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV8R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY5Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\>T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU9]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX2X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ=Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU9]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[7_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX2X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^0Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ=Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX2X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW;S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ4^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY5Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX2X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_3[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]1U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ=Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV9R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY4Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\?T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU8]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX3X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ<Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU8]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[6_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX3X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^1Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ<Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX3X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW:S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ5^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY4Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX3X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_2[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]0U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ<Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV6R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY;Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\0T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU7]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX<X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ3Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU7]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[9_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX<X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^>Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ3Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX<X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW5S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ:^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY;Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX<X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_=[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]?U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ3Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV7R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY:Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\1T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU6]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX=X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ2Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU6]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[8_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX=X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^?Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ2Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX=X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW4S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ;^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY:Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX=X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_<[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]>U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ2Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUDYYU?]/CP]KEXG\^TOHBC/RJJBQYUMN9:7X> I^TJK*ABFVKXUCMPOTVX4X(F[PDHSB[[_BGOH*STM[UYIJ=<;T2,MZPNG&MNBRO\YOA\KPR\99W%M^WAC^MVPZEBDE%XDDH[_SGD77=R8&CTZDA GDL\EV_IKVE^XV??]/CP]KEXG\^TOHBC/TQFVZTBO:90Y=!F_WKL+BCIWHYRBNQ@UUY25X(F[PDHSB[[_BGOH*UOAO^T^HI<2:W3+LYQAF%LICQNSXL@[JSSS8;V"L]VNB]LQQYDMEF$Y^K]_SGD76=R8&CTZDA GDL\EV_IKVE^XV?=]/CP]KEXG\^TOHBC/RJJBQYUMN997X> I^TJK*ABFVKXUCMPOTVX57[)IZSEORAZT^AFHI)R[LXT^HI<3:W3+LYQAF%LICQNSXL@[JSSS89V"L]VNB]LQQYDMEF$_EGIT^PFC64<]9%BS[G@/FGM[DU^FJUDYYU>3\,BW\HDWF__SNKCL.WPAWYUMN987X> I^TJK*ABFVKXUCMPOTVX51[)IZSEORAZT^AFHI)T@@L_S_KH339V4*OX^@E$KH@PAR[MGZIR\R;?Q#O\YOA\KPRXKLFG#X]JR^PFC65<]9%BS[G@/FGM[DU^FJUDYYU>5\,BW\HDWF__SNKCL.QKMCRXZLM8>6[?/H]UMJ)@MGUJ_T@L_NWW_43Z&HYRBNQ@UU]@AIJ(]ZOYS_KH329V4*OX^@E$KH@PAR[MGZIR\R;=Q#O\YOA\KPRXKLFG#^FFFU]QAB553\:$ERXFO.EFJZGTQGITCXZT17_-EV_IKVE^XRMJLM-VW@TXZLM8?6[?/H]UMJ)@MGUJ_T@L_NWW_41Z&HYRBNQ@UU]@AIJ([ACMXR\JG208Q5)NW_CD#JKA_@QZJFYH]]Q:;P NSXL@[JSSWJOG@"[\ES]QAB543\:$ERXFO.EFJZGTQGITCXZT19_-EV_IKVE^XRMJLM-PLL@SW[OL??5Z0.K\RLI(OLDTM^WAC^MVP^7?U'KXUCMPOTV\G@JK'\YN^R\JG218Q5)NW_CD#JKA_@QZJFYH]]Q:5P NSXL@[JSSWJOG@"]GIGV\V@A4:2_;#DQYIN-DAKYF[PDHSB[[[0;^*DU^FJUDYYQLEMN,QVCUW[OL??5Z0.K\RLI(OLDTM^WAC^MVP^7Z&HYRBNQ@UU]@AIJ([ACMXR\JG238Q5)NW_CD#JKA_@QZJFYH]]Q:Q#O\YOA\KPRXKLFG#X]JR^PFC65<]9%BS[G@/FGM[DU^FJUDYYU=0\,BW\HDWF__SNKCL.QKMCRXZLM8>6[?/H]UMJ)@MGUJ_T@L_NWW_76Z&HYRBNQ@UU]@AIJ(]ZOYS_KH329V4*OX^@E$KH@PAR[MGZIR\R8:Q#O\YOA\KPRXKLFG#^FFFU]QAB553\:$ERXFO.EFJZGTQGITCXZT20_-EV_IKVE^XRMJLM-VW@TXZLM8?6[?/H]UMJ)@MGUJ_T@L_NWW_74Z&HYRBNQ@UU]@AIJ([ACMXR\JG208Q5)NW_CD#JKA_@QZJFYH]]Q9>P NSXL@[JSSWJOG@"[\ES]QAB543\:$ERXFO.EFJZGTQGITCXZT22_-EV_IKVE^XRMJLM-PLL@SW[OL??5Z0.K\RLI(OLDTM^WAC^MVP^44U'KXUCMPOTV\G@JK'\YN^R\JG218Q5)NW_CD#JKA_@QZJFYH]]Q98P NSXL@[JSSWJOG@"]GIGV\V@A4:2_;#DQYIN-DAKYF[PDHSB[[[36^*DU^FJUDYYQLEMN,QVCUW[OL?>5Z0.K\RLI(OLDTM^WAC^MVP^42U'KXUCMPOTV\G@JK'ZBBJYQ]EF11?P6(AV\BC"IJN^CP]KEXG\^P>8S!AR[MGZIR\VIN@A!ZSDP\V@A4;2_;#DQYIN-DAKYF[PDHSB[[[34^*DU^FJUDYYQLEMN,WMOA\VXNK><4U1-J[SOH'NOESL]VNB]LQQ]5>T$J_T@L_NWW[FCKD&_XI_Q]EF10?P6(AV\BC"IJN^CP]KEXG\^P>:S!AR[MGZIR\VIN@A!\HHDW[WC@;;1^<"GPVHM,C@HXIZSEORAZTZ04Y+GTQGITCXZPCDNO+PUBZVXNK>=4U1-J[SOH'NOESL]VNB]LQQ]50T$J_T@L_NWW[FCKD&YCEKZPRDE06>S7'@U]EB!HEO]BW\HDWF__W?6R.@QZJFYH]]UHIAB URGQ[WC@;:1^<"GPVHM,C@HXIZSEORAZTZ0:Y+GTQGITCXZPCDNO+VNNN]UYIJ==;T2,MZPNG&MNBRO\YOA\KPR\:0W%M^WAC^MVPZEBDE%^_H\PRDE06>S7'@U]EB!HEO]BW\HDWF__W?S!AR[MGZIR\VIN@A!\HHDW[WC@;81^<"GPVHM,C@HXIZSEORAZTZ0^*DU^FJUDYYQLEMN,QVCUW[OL?>5Z0.K\RLI(OLDTM^WAC^MVP^57U'KXUCMPOTV\G@JK'ZBBJYQ]EF11?P6(AV\BC"IJN^CP]KEXG\^P?=S!AR[MGZIR\VIN@A!ZSDP\V@A4;2_;#DQYIN-DAKYF[PDHSB[[[23^*DU^FJUDYYQLEMN,WMOA\VXNK><4U1-J[SOH'NOESL]VNB]LQQ]49T$J_T@L_NWW[FCKD&_XI_Q]EF11?P6(AV\BC"IJN^CP]KEXG\^P?P NSXL@[JSSWJOG@"]GIGV\V@A492_;#DQYIN-DAKYF[PDHSB[[[2_-EV_IKVE^XRMJLM-VW@TXZLM8>6[?/H]UMJ)@MGUJ_T@L_NWW_1[)IZSEORAZT^AFHI)T@@L_S_KH309V4*OX^@E$KH@PAR[MGZIR\R>V"L]VNB]LQQYDMEF$Y^K]_SGD77=R8&CTZDA GDL\EV_IKVE^XV;R.@QZJFYH]]UHIAB SIKEPZTBO:;0Y=!F_WKL+BCIWHYRBNQ@UUY6Y+GTQGITCXZPCDNO+PUBZVXNK><4U1-J[SOH'NOESL]VNB]LQQ]1U'KXUCMPOTV\G@JK'ZBBJYQ]EF12?P6(AV\BC"IJN^CP]KEXG\^P:P NSXL@[JSSWJOG@"[\ES]QAB553\:$ERXFO.EFJZGTQGITCXZT7\,BW\HDWF__SNKCL.QKMCRXZLM8=6[?/H]UMJ)@MGUJ_T@L_NWW_2[)IZSEORAZT^AFHI)R[LXT^HI<2:W3+LYQAF%LICQNSXL@[JSSS1W%M^WAC^MVPZEBDE%XDDH[_SGD74=R8&CTZDA GDL\EV_IKVE^XV6R.@QZJFYH]]UHIAB URGQ[WC@;;1^<"GPVHM,C@HXIZSEORAZTZ;^*DU^FJUDYYQLEMN,WMOA\VXNK>?4U1-J[SOH'NOESL]VNB]LQQ]>U'KXUCMPOTV\G@JK'\YN^R\JG238Q5)NW_CD#JKA_R[MGZOIS:8V"^WAC^KM[FCKD&KXUCMPF^OV\67<]9%BS[G@/FGM[V_IKVCEW><R.R[MGZOIWJOG@"O\YOA\VZKRP;l0Y=!F_WKL+BCIWZSEORGA[20^*V_IKVCESNKCL.QKMCRXZLM8<6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,W\HDWOUFYU=?;T2,MZPNG&MNBR]VNB]JJ^55U'YRBNQFN^AFHI)TQGIT^RCZX218Q5)NW_CD#JKA_R[MGZOIS:8V"^WAC^KM[FCKD&YTM^WAC^D\V@A4;2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB S^CP]KEXZVXNK><4U1-J[SOH'NOES^WAC^KM_64Z&ZSEORGA_BGOH*UX[PDHSKQ]EF11?P6(AV\BC"IJN^QZJFYNFR99Q#]VNB]JJZEBDE%XS^WAC^P\V@A4:2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB URGQ[FJLW[OL>h5Z0.K\RLI(OLDT_T@L_HLX77[)[PDHSD@PCDNO+PUBZVG^T?k4U1-J[SOH'NOES^WAC^KM_64Z&ZSEORGA_BGOH*STM[UYIJ<i;T2,MZPNG&MNBR]VNB]JJ^55U'YRBNQFN^AFHI)RWOKG@D@H2d9V4*OX^@E$KH@PSXL@[LH\;;W%_T@L_HL\G@JK'\UYE^GAG238Q5)NW_CD#JKA_R[MGZOIS:8V"^WAC^KM[FCKD&_T_YO[CLF\j7c<]9%BS[G@/FGM[V_IKVCEW><R.R[MGZOIWJOG@"[PSXL@[C4b3\:$ERXFO.EFJZU^FJUBBV==]/QZJFYNFVIN@A!Z_R[MGZT4=2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB ar{mgZkrpVlTcxz<5:W3+LYQAF%LICQ\YOA\MK]4:T$XUCMPIO]@AIJ(izseoRczx^p\kpr5l2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB cmm`o`b5l2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB f`nomka492_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB f`nomkaXg|~9h6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ba7Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ba4Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ba5Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ba2Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ba3Xg|~9i6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ip~6Wf>n5Z0.K\RLI(OLDT_T@L_HLX77[)[PDHSD@PCDNO+wotagm8<6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,vlunfnUdyy=j;T2,MZPNG&MNBR]VNB]JJ^55U'YRBNQFN^AFHI)tqgiTjRkkgd-J[M4K&\UOCXZ<9:W3+LYQAF%LICQ\YOA\MK]4:T$XUCMPIO]@AIJ({pdhSkQjdfg,QZBH]]:856[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,w|hdWoUnhjk U^FLQQ74i2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB sxl`[cYblno$eIAZT=2=7d=R8&CTZDA GDL\W\HDW@DP??S!SXL@[LHXKLFG#~wac^d\aaab'`NDYY2>>228Q5)NW_CD#JKA_R[MGZOIS:8V"^WAC^KM[FCKD&yrbnQi_nww71=R8&CTZDA GDL\W\HDW@DP??S!SXL@[LHXKLFG#~wac^ov|Z`Xg|~886[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,w|hdWdsSQ`uu1f?P6(AV\BC"IJN^QZJFYNFR99Q#]VNB]JJZEBDE%xucmPr^ggc`)NWE8C"XQKOTV0=>S7'@U]EB!HEO]P]KEXAGQ8>P \YOA\MKYDMEF$t`l_s]f`bc(]VNDYY><9:W3+LYQAF%LICQ\YOA\MK]4:T$XUCMPIO]@AIJ({pdhSQjdfg,QZBH]];8m6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,w|hdW{Unhjk iEMVP969;h1^<"GPVHM,C@HX[PDHSD@T33_-W\HDW@DTOHBC/r{mgZtXmmmn#dJ@UU>2:66<]9%BS[G@/FGM[V_IKVCEW><R.R[MGZOIWJOG@"}vnb]q[jss:o1^<"GPVHM,C@HX[PDHSD@T33_-W\HDW@DTOHBC/tqfvZoiWg9:7X> I^TJK*ABFVYRBNQFNZ10Y+U^FJUBBRMJLM-BW\HDWOUFYU=>;T2,MZPNG&MNBR]VNB]JJ^54U'YRBNQFN^AFHI)F[PDHS_QBUY0e?P6(AV\BC"IJN^QZJFYNFR98Q#]VNB]JJZEBDE%XDDH[_SGD75=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#^WAC^D\IP^482_;#DQYIN-DAKYTQGITECU<3\,P]KEXAGUHIAB SXL@[WYJ]Q987X> I^TJK*ABFVYRBNQFNZ10Y+U^FJUBBRMJLM-P[DU^FJUMS_KH329V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'ZUJ_T@L_S]QAB553\:$ERXFO.EFJZU^FJUBBV=<]/QZJFYNFVIN@A!\_R[MGZ@XZLM8>6[?/H]UMJ)@MGUXUCMPIOY07X(TQGITECQLEMN,WZU^FJUYS_KH339V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'\YN^RMCK^PFC7c<]9%BS[G@/FGM[V_IKVCEW>=R.R[MGZOIWJOG@"[\ES]NQ]4b3\:$ERXFO.EFJZU^FJUBBV=<]/QZJFYNFVIN@A!ZSDP\V@A5n2_;#DQYIN-DAKYTQGITECU<3\,P]KEXAGUHIAB U^DBHIOIO;o0Y=!F_WKL+BCIWZSEORGA[21^*V_IKVCESNKCL.W\VLUNFN9:7X> I^TJK*ABFVYRBNQFNZ10Y+U^FJUBBRMJLM-V[VRF\JGOSc<j;T2,MZPNG&MNBR]VNB]JJ^54U'YRBNQFN^AFHI)RWZSEORH=e:W3+LYQAF%LICQ\YOA\MK]4;T$XUCMPIO]@AIJ(]VYRBNQ]349V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'hyrbnQbuy]e[jss;<1^<"GPVHM,C@HX[PDHSD@T32_-W\HDW@DTOHBC/`qzjfYj}qUySb{{2e9V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'jfdofkk2e9V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'okg`d`h309V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'okg`d`h_nww6a=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#kj>_nww6a=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#kj=_nww6a=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#kj<_nww6a=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#kj;_nww6a=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#kj:_nww6`=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#`{w1^mvp7e<]9%BS[G@/FGM[V_IKVCEW>=R.R[MGZOIWJOG@"|fshld75=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#g|ioe\kpr4m2_;#DQYIN-DAKYTQGITECU<3\,P]KEXAGUHIAB sxl`[cYblno$ERF=L/W\@JSS;01^<"GPVHM,C@HX[PDHSD@T32_-W\HDW@DTOHBC/r{mgZ`Xmmmn#XQKOTV37<=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#~wac^d\aaab'\UOCXZ>3`9V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'zseoRhPeeef+lBH]]6;2>o4U1-J[SOH'NOES^WAC^KM_65Z&ZSEORGA_BGOH*u~fjUmShjhe.kGKPR;979;7X> I^TJK*ABFVYRBNQFNZ10Y+U^FJUBBRMJLM-p}keXnVe~x>:4U1-J[SOH'NOES^WAC^KM_65Z&ZSEORGA_BGOH*u~fjUfyuQi_nww71=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#~wac^ov|ZtXg|~8i6[?/H]UMJ)@MGUXUCMPIOY07X(TQGITECQLEMN,w|hdW{Unhjk I^N1L+SXLF__?45Z0.K\RLI(OLDT_T@L_HLX76[)[PDHSD@PCDNO+vikVxTiiij/T]GKPR7;01^<"GPVHM,C@HX[PDHSD@T32_-W\HDW@DTOHBC/r{mgZtXmmmn#XQKOTV27d=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#~wac^p\aaab'`NDYY2?>2c8Q5)NW_CD#JKA_R[MGZOIS:9V"^WAC^KM[FCKD&yrbnQ}_dfda*oCG\^7=3=?;T2,MZPNG&MNBR]VNB]JJ^54U'YRBNQFN^AFHI)tqgiT~Razt3d8Q5)NW_CD#JKA_R[MGZOIS:9V"^WAC^KM[FCKD&xiQfn^l05>S7'@U]EB!HEO]P]KEXAGQ88P \YOA\MKYDMEF$M^WAC^D\IP^492_;#DQYIN-DAKYTQGITECU<4\,P]KEXAGUHIAB AR[MGZTXE\R9j6[?/H]UMJ)@MGUXUCMPIOY00X(TQGITECQLEMN,WMOA\VXNK>>4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*U^FJUMS@[W319V4*OX^@E$KH@PSXL@[LH\;=W%_T@L_HL\G@JK'ZSEOR\PMTZ07>S7'@U]EB!HEO]P]KEXAGQ88P \YOA\MKYDMEF$_RO\YOA\BZTBO:90Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.Q\EV_IKVXT^HI<2:W3+LYQAF%LICQ\YOA\MK]4<T$XUCMPIO]@AIJ([VYRBNQI_SGD77=R8&CTZDA GDL\W\HDW@DP?9S!SXL@[LHXKLFG#^Q\YOA\VZTBO:80Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.WPAWYDDBUYIJ<j;T2,MZPNG&MNBR]VNB]JJ^53U'YRBNQFN^AFHI)R[LXTAXV=e:W3+LYQAF%LICQ\YOA\MK]4<T$XUCMPIO]@AIJ(]ZOYS_KH2g9V4*OX^@E$KH@PSXL@[LH\;=W%_T@L_HL\G@JK'\UMMABFNF0f?P6(AV\BC"IJN^QZJFYNFR9?Q#]VNB]JJZEBDE%^S_G\IOE05>S7'@U]EB!HEO]P]KEXAGQ88P \YOA\MKYDMEF$YR][AUAN@Zh5m2_;#DQYIN-DAKYTQGITECU<4\,P]KEXAGUHIAB U^QZJFYA:l1^<"GPVHM,C@HX[PDHSD@T35_-W\HDW@DTOHBC/T]P]KEXZ:?0Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.cp}keXe|rTjRazt278Q5)NW_CD#JKA_R[MGZOIS:>V"^WAC^KM[FCKD&kxucmPmtz\vZir|;n0Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.aokfmbl;n0Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.dbhioio:;0Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.dbhioioVe~x?j4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*`c9Ve~x?j4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*`c:Ve~x?j4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*`c;Ve~x?j4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*`c<Ve~x?j4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*`c=Ve~x?k4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*krp8Udyy<l;T2,MZPNG&MNBR]VNB]JJ^53U'YRBNQFN^AFHI)uazcek>>4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*tn{`dlSb{{3d9V4*OX^@E$KH@PSXL@[LH\;=W%_T@L_HL\G@JK'zseoRhPeeef+LYO:E$^SIAZT2;8Q5)NW_CD#JKA_R[MGZOIS:>V"^WAC^KM[FCKD&yrbnQi_dfda*SXLF__<>74U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*u~fjUmShjhe.W\@JSS9:k0Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.qzjfYaWlnli"gKOTV?4;5f3\:$ERXFO.EFJZU^FJUBBV=;]/QZJFYNFVIN@A!|yoa\bZccol%bHB[[<0<04>S7'@U]EB!HEO]P]KEXAGQ88P \YOA\MKYDMEF$t`l_g]lqq533\:$ERXFO.EFJZU^FJUBBV=;]/QZJFYNFVIN@A!|yoa\ip~XnVe~x>:4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*u~fjUfyuQ}_nww7`=R8&CTZDA GDL\W\HDW@DP?9S!SXL@[LHXKLFG#~wac^p\aaab'@UG>E Z_EMVP6?<]9%BS[G@/FGM[V_IKVCEW>:R.R[MGZOIWJOG@"}vnb]q[`b`m&_THB[[02;8Q5)NW_CD#JKA_R[MGZOIS:>V"^WAC^KM[FCKD&yrbnQ}_dfda*SXLF__=>o4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*u~fjUyShjhe.kGKPR;879j7X> I^TJK*ABFVYRBNQFNZ17Y+U^FJUBBRMJLM-p}keXzVookh!fDNWW848482_;#DQYIN-DAKYTQGITECU<4\,P]KEXAGUHIAB sxl`[wYh}}8m7X> I^TJK*ABFVYRBNQFNZ17Y+U^FJUBBRMJLM-vw`tXagUe?<5Z0.K\RLI(OLDT_T@L_HLX70[)[PDHSD@PCDNO+DU^FJUMS@[W309V4*OX^@E$KH@PSXL@[LH\;<W%_T@L_HL\G@JK'HYRBNQ]_LW[6c=R8&CTZDA GDL\W\HDW@DP?8S!SXL@[LHXKLFG#^FFFU]QAB573\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!\YOA\BZKRP::0Y=!F_WKL+BCIWZSEORGA[27^*V_IKVCESNKCL.QZJFYUWD_S?>5Z0.K\RLI(OLDT_T@L_HLX70[)[PDHSD@PCDNO+VYF[PDHSKQ]EF10?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%XSL]VNB]Q[WC@;;1^<"GPVHM,C@HX[PDHSD@T34_-W\HDW@DTOHBC/R]P]KEXNVXNK><4U1-J[SOH'NOES^WAC^KM_63Z&ZSEORGA_BGOH*UX[PDHS_Q]EF11?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%^_H\PCMI\V@A5m2_;#DQYIN-DAKYTQGITECU<5\,P]KEXAGUHIAB URGQ[HS_:l1^<"GPVHM,C@HX[PDHSD@T34_-W\HDW@DTOHBC/TQFVZTBO;l0Y=!F_WKL+BCIWZSEORGA[27^*V_IKVCESNKCL.W\BDJKAGM9i6[?/H]UMJ)@MGUXUCMPIOY01X(TQGITECQLEMN,QZTN[@DL?<5Z0.K\RLI(OLDT_T@L_HLX70[)[PDHSD@PCDNO+PYT\H^HAIQa2d9V4*OX^@E$KH@PSXL@[LH\;<W%_T@L_HL\G@JK'\UXUCMPF3g8Q5)NW_CD#JKA_R[MGZOIS:?V"^WAC^KM[FCKD&_T_T@L_S16?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%jt`l_lw{[cYh}}9>7X> I^TJK*ABFVYRBNQFNZ16Y+U^FJUBBRMJLM-bw|hdWdsSQ`uu0g?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%h`bmdee0g?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%mmabfnf12?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%mmabfnf]lqq4c3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!id0]lqq4c3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!id3]lqq4c3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!id2]lqq4c3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!id5]lqq4c3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!id4]lqq4b3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!buy3\kpr5k2_;#DQYIN-DAKYTQGITECU<5\,P]KEXAGUHIAB rhqjjb573\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!}irkmcZir|:o0Y=!F_WKL+BCIWZSEORGA[27^*V_IKVCESNKCL.qzjfYaWlnli"GPH3N-QZBH]]927X> I^TJK*ABFVYRBNQFNZ16Y+U^FJUBBRMJLM-p}keXnVookh!Z_EMVP55>3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!|yoa\bZccol%^SIAZT01b?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%xucmPf^ggc`)nLF__0=0<a:W3+LYQAF%LICQ\YOA\MK]4=T$XUCMPIO]@AIJ({pdhSkQjdfg,mAIR\5;5?=5Z0.K\RLI(OLDT_T@L_HLX70[)[PDHSD@PCDNO+vikVlTcxz<4:W3+LYQAF%LICQ\YOA\MK]4=T$XUCMPIO]@AIJ({pdhS`{w_g]lqq533\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!|yoa\ip~XzVe~x>k4U1-J[SOH'NOES^WAC^KM_63Z&ZSEORGA_BGOH*u~fjUyShjhe.K\H7N)]VNDYY=6;T2,MZPNG&MNBR]VNB]JJ^52U'YRBNQFN^AFHI)tqgiT~Rkkgd-V[AIR\9927X> I^TJK*ABFVYRBNQFNZ16Y+U^FJUBBRMJLM-p}keXzVookh!Z_EMVP45f3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!|yoa\vZccol%bHB[[<1<0e>S7'@U]EB!HEO]P]KEXAGQ89P \YOA\MKYDMEF$t`l_s]f`bc(aME^X1?1319V4*OX^@E$KH@PSXL@[LH\;<W%_T@L_HL\G@JK'zseoR|Potv1b>S7'@U]EB!HEO]P]KEXAGQ89P \YOA\MKYDMEF$y~k}_hl\j67<]9%BS[G@/FGM[V_IKVCEW>8R.R[MGZOIWJOG@"O\YOA\BZKRP:;0Y=!F_WKL+BCIWZSEORGA[24^*V_IKVCESNKCL.CP]KEXZVG^T?h4U1-J[SOH'NOES^WAC^KM_60Z&ZSEORGA_BGOH*UOAO^T^HI<0:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ([PDHSKQBUY13?P6(AV\BC"IJN^QZJFYNFR9=Q#]VNB]JJZEBDE%XUCMPR^OV\65<]9%BS[G@/FGM[V_IKVCEW>8R.R[MGZOIWJOG@"]PAR[MGZ@XZLM8?6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,WZGTQGIT^R\JG208Q5)NW_CD#JKA_R[MGZOIS:<V"^WAC^KM[FCKD&YT_T@L_G]QAB553\:$ERXFO.EFJZU^FJUBBV=9]/QZJFYNFVIN@A!\_R[MGZTXZLM8>6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,QVCUWJF@S_KH2d9V4*OX^@E$KH@PSXL@[LH\;?W%_T@L_HL\G@JK'\YN^RCZX3g8Q5)NW_CD#JKA_R[MGZOIS:<V"^WAC^KM[FCKD&_XI_Q]EF0e?P6(AV\BC"IJN^QZJFYNFR9=Q#]VNB]JJZEBDE%^SKOCLHLD6`=R8&CTZDA GDL\W\HDW@DP?;S!SXL@[LHXKLFG#XQ]IRKMC67<]9%BS[G@/FGM[V_IKVCEW>8R.R[MGZOIWJOG@"[PSUCWGHBXf;o0Y=!F_WKL+BCIWZSEORGA[24^*V_IKVCESNKCL.W\W\HDWO8n7X> I^TJK*ABFVYRBNQFNZ15Y+U^FJUBBRMJLM-V[V_IKVX896[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,evikVg~tRhPotv01>S7'@U]EB!HEO]P]KEXAGQ8:P \YOA\MKYDMEF$m~wac^ov|ZtXg|~9h6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,giidcln9h6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,bdjkagm8=6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,bdjkagmTcxz=d:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(nm;Tcxz=d:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(nm8Tcxz=d:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(nm9Tcxz=d:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(nm>Tcxz=d:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(nm?Tcxz=e:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(e|r:Sb{{2b9V4*OX^@E$KH@PSXL@[LH\;?W%_T@L_HL\G@JK'{cxeci<0:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(z`ybbjQ`uu1f?P6(AV\BC"IJN^QZJFYNFR9=Q#]VNB]JJZEBDE%xucmPf^ggc`)NWA8G"XQKOTV0=>S7'@U]EB!HEO]P]KEXAGQ8:P \YOA\MKYDMEF$t`l_g]f`bc(]VNDYY><9:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ({pdhSkQjdfg,QZBH]];8m6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,w|hdWoUnhjk iEMVP969;h1^<"GPVHM,C@HX[PDHSD@T37_-W\HDW@DTOHBC/r{mgZ`Xmmmn#dJ@UU>2:66<]9%BS[G@/FGM[V_IKVCEW>8R.R[MGZOIWJOG@"}vnb]e[jss;=1^<"GPVHM,C@HX[PDHSD@T37_-W\HDW@DTOHBC/r{mgZkrpVlTcxz<4:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ({pdhS`{w_s]lqq5b3\:$ERXFO.EFJZU^FJUBBV=9]/QZJFYNFVIN@A!|yoa\vZccol%BSA<G.T]GKPR412_;#DQYIN-DAKYTQGITECU<6\,P]KEXAGUHIAB sxl`[wYblno$YRJ@UU20=>S7'@U]EB!HEO]P]KEXAGQ8:P \YOA\MKYDMEF$t`l_s]f`bc(]VNDYY?<a:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ({pdhSQjdfg,mAIR\5:5?l5Z0.K\RLI(OLDT_T@L_HLX73[)[PDHSD@PCDNO+vikVxTiiij/hFLQQ:66::0Y=!F_WKL+BCIWZSEORGA[24^*V_IKVCESNKCL.qzjfYuWf>k5Z0.K\RLI(OLDT_T@L_HLX73[)[PDHSD@PCDNO+pubzVceSc=>;T2,MZPNG&MNBR]VNB]JJ^50U'YRBNQFN^AFHI)F[PDHSKQBUY12?P6(AV\BC"IJN^QZJFYNFR9<Q#]VNB]JJZEBDE%J_T@L_S]NQ]4a3\:$ERXFO.EFJZU^FJUBBV=8]/QZJFYNFVIN@A!\HHDW[WC@;91^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/R[MGZ@XE\R8<6[?/H]UMJ)@MGUXUCMPIOY03X(TQGITECQLEMN,W\HDW[UFYU=<;T2,MZPNG&MNBR]VNB]JJ^50U'YRBNQFN^AFHI)TWHYRBNQI_SGD76=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#^QNSXL@[WYUMN997X> I^TJK*ABFVYRBNQFNZ14Y+U^FJUBBRMJLM-P[V_IKVLT^HI<2:W3+LYQAF%LICQ\YOA\MK]4?T$XUCMPIO]@AIJ([VYRBNQ]_SGD77=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#X]JR^AOOZTBO;o0Y=!F_WKL+BCIWZSEORGA[25^*V_IKVCESNKCL.WPAWYJ]Q8n7X> I^TJK*ABFVYRBNQFNZ14Y+U^FJUBBRMJLM-VW@TXZLM9j6[?/H]UMJ)@MGUXUCMPIOY03X(TQGITECQLEMN,QZ@FDECEK?k4U1-J[SOH'NOES^WAC^KM_61Z&ZSEORGA_BGOH*SXZ@YBBJ=>;T2,MZPNG&MNBR]VNB]JJ^50U'YRBNQFN^AFHI)RWZ^JXNCK_o0f?P6(AV\BC"IJN^QZJFYNFR9<Q#]VNB]JJZEBDE%^S^WAC^D1a>S7'@U]EB!HEO]P]KEXAGQ8;P \YOA\MKYDMEF$YR]VNB]Q70=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#l}vnb]nq}YaWf?85Z0.K\RLI(OLDT_T@L_HLX72[)[PDHSD@PCDNO+du~fjUfyuQ}_nww6a=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#nb`cjgg6a=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#koclhld74=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#koclhld[jss:m1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/gf2[jss:m1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/gf1[jss:m1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/gf0[jss:m1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/gf7[jss:m1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/gf6[jss:l1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/lw{5Zir|;i0Y=!F_WKL+BCIWZSEORGA[25^*V_IKVCESNKCL.pjwlh`;91^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/skpmkaXg|~8i6[?/H]UMJ)@MGUXUCMPIOY03X(TQGITECQLEMN,w|hdWoUnhjk I^J1H+SXLF__?45Z0.K\RLI(OLDT_T@L_HLX72[)[PDHSD@PCDNO+vikVlTiiij/T]GKPR7;01^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/r{mgZ`Xmmmn#XQKOTV27d=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#~wac^d\aaab'`NDYY2?>2c8Q5)NW_CD#JKA_R[MGZOIS:=V"^WAC^KM[FCKD&yrbnQi_dfda*oCG\^7=3=?;T2,MZPNG&MNBR]VNB]JJ^50U'YRBNQFN^AFHI)tqgiTjRazt268Q5)NW_CD#JKA_R[MGZOIS:=V"^WAC^KM[FCKD&yrbnQbuy]e[jss;=1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/r{mgZkrpVxTcxz<e:W3+LYQAF%LICQ\YOA\MK]4?T$XUCMPIO]@AIJ({pdhSQjdfg,MZJ5@'_THB[[389V4*OX^@E$KH@PSXL@[LH\;>W%_T@L_HL\G@JK'zseoR|Peeef+PYCG\^;?45Z0.K\RLI(OLDT_T@L_HLX72[)[PDHSD@PCDNO+vikVxTiiij/T]GKPR6;h1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/r{mgZtXmmmn#dJ@UU>3:6g<]9%BS[G@/FGM[V_IKVCEW>9R.R[MGZOIWJOG@"}vnb]q[`b`m&cOCXZ31?13?P6(AV\BC"IJN^QZJFYNFR9<Q#]VNB]JJZEBDE%xucmPr^mvp7`<]9%BS[G@/FGM[V_IKVCEW>9R.R[MGZOIWJOG@"{|es]jjZh492_;#DQYIN-DAKYTQGITECU<8\,P]KEXAGUHIAB AR[MGZ@XE\R8=6[?/H]UMJ)@MGUXUCMPIOY0<X(TQGITECQLEMN,EV_IKVXTAXV=f:W3+LYQAF%LICQ\YOA\MK]40T$XUCMPIO]@AIJ([ACMXR\JG228Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&YRBNQI_LW[75=R8&CTZDA GDL\W\HDW@DP?5S!SXL@[LHXKLFG#^WAC^P\IP^4;2_;#DQYIN-DAKYTQGITECU<8\,P]KEXAGUHIAB S^CP]KEXNVXNK>=4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*UXIZSEOR\PRDE06>S7'@U]EB!HEO]P]KEXAGQ84P \YOA\MKYDMEF$_R]VNB]E[WC@;;1^<"GPVHM,C@HX[PDHSD@T39_-W\HDW@DTOHBC/R]P]KEXZVXNK><4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*STM[UH@FQ]EF0f?P6(AV\BC"IJN^QZJFYNFR93Q#]VNB]JJZEBDE%^_H\PMTZ1a>S7'@U]EB!HEO]P]KEXAGQ84P \YOA\MKYDMEF$Y^K]_SGD6c=R8&CTZDA GDL\W\HDW@DP?5S!SXL@[LHXKLFG#XQIAMNJJB4b3\:$ERXFO.EFJZU^FJUBBV=7]/QZJFYNFVIN@A!Z_SKPMKA492_;#DQYIN-DAKYTQGITECU<8\,P]KEXAGUHIAB U^QWEQEJLVd9i6[?/H]UMJ)@MGUXUCMPIOY0<X(TQGITECQLEMN,QZU^FJUM>h5Z0.K\RLI(OLDT_T@L_HLX7=[)[PDHSD@PCDNO+PYTQGIT^>;4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*gtqgiTaxvPf^mvp63<]9%BS[G@/FGM[V_IKVCEW>6R.R[MGZOIWJOG@"o|yoa\ip~XzVe~x?j4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*ekgjanh?j4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*`fdecek>?4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*`fdecekRazt3f8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&lo=Razt3f8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&lo>Razt3f8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&lo?Razt3f8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&lo8Razt3f8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&lo9Razt3g8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&g~t<Q`uu0`?P6(AV\BC"IJN^QZJFYNFR93Q#]VNB]JJZEBDE%ye~gag228Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&xbd`h_nww7`=R8&CTZDA GDL\W\HDW@DP?5S!SXL@[LHXKLFG#~wac^d\aaab'@UC>A Z_EMVP6?<]9%BS[G@/FGM[V_IKVCEW>6R.R[MGZOIWJOG@"}vnb]e[`b`m&_THB[[02;8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&yrbnQi_dfda*SXLF__=>o4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*u~fjUmShjhe.kGKPR;879j7X> I^TJK*ABFVYRBNQFNZ1;Y+U^FJUBBRMJLM-p}keXnVookh!fDNWW848482_;#DQYIN-DAKYTQGITECU<8\,P]KEXAGUHIAB sxl`[cYh}}9?7X> I^TJK*ABFVYRBNQFNZ1;Y+U^FJUBBRMJLM-p}keXe|rTjRazt268Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&yrbnQbuy]q[jss;l1^<"GPVHM,C@HX[PDHSD@T39_-W\HDW@DTOHBC/r{mgZtXmmmn#DQC2I,V[AIR\:30Y=!F_WKL+BCIWZSEORGA[2:^*V_IKVCESNKCL.qzjfYuWlnli"[PDNWW46?<]9%BS[G@/FGM[V_IKVCEW>6R.R[MGZOIWJOG@"}vnb]q[`b`m&_THB[[12c8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&yrbnQ}_dfda*oCG\^7<3=n;T2,MZPNG&MNBR]VNB]JJ^5?U'YRBNQFN^AFHI)tqgiT~Rkkgd-j@JSS4848<6[?/H]UMJ)@MGUXUCMPIOY0<X(TQGITECQLEMN,w|hdW{Udyy<i;T2,MZPNG&MNBR]VNB]JJ^5?U'YRBNQFN^AFHI)r{lxTecQa309V4*OX^@E$KH@PSXL@[LH\;0W%_T@L_HL\G@JK'HYRBNQI_LW[74=R8&CTZDA GDL\W\HDW@DP?4S!SXL@[LHXKLFG#L]VNB]Q[HS_:o1^<"GPVHM,C@HX[PDHSD@T38_-W\HDW@DTOHBC/RJJBQYUMN9;7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-P]KEXNVG^T>>4U1-J[SOH'NOES^WAC^KM_6?Z&ZSEORGA_BGOH*U^FJUYS@[W329V4*OX^@E$KH@PSXL@[LH\;0W%_T@L_HL\G@JK'ZUJ_T@L_G]QAB543\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!\_@QZJFYUW[OL??5Z0.K\RLI(OLDT_T@L_HLX7<[)[PDHSD@PCDNO+VYTQGITJR\JG208Q5)NW_CD#JKA_R[MGZOIS:3V"^WAC^KM[FCKD&YT_T@L_S]QAB553\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!ZSDP\GIMXZLM9i6[?/H]UMJ)@MGUXUCMPIOY0=X(TQGITECQLEMN,QVCUWD_S>h5Z0.K\RLI(OLDT_T@L_HLX7<[)[PDHSD@PCDNO+PUBZVXNK?h4U1-J[SOH'NOES^WAC^KM_6?Z&ZSEORGA_BGOH*SXNHFGECI=e:W3+LYQAF%LICQ\YOA\MK]41T$XUCMPIO]@AIJ(]VXB_D@H309V4*OX^@E$KH@PSXL@[LH\;0W%_T@L_HL\G@JK'\UXXLZLME]m6`=R8&CTZDA GDL\W\HDW@DP?4S!SXL@[LHXKLFG#XQ\YOA\B7c<]9%BS[G@/FGM[V_IKVCEW>7R.R[MGZOIWJOG@"[PSXL@[W523\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!nsxl`[hsWoUdyy=:;T2,MZPNG&MNBR]VNB]JJ^5>U'YRBNQFN^AFHI)f{pdhS`{w_s]lqq4c3\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!llnahaa4c3\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!iamnjjb563\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!iamnjjbYh}}8o7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-e`4Yh}}8o7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-e`7Yh}}8o7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-e`6Yh}}8o7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-e`1Yh}}8o7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-e`0Yh}}8n7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-nq}7Xg|~9o6[?/H]UMJ)@MGUXUCMPIOY0=X(TQGITECQLEMN,vlunfn9;7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-qmvoioVe~x>k4U1-J[SOH'NOES^WAC^KM_6?Z&ZSEORGA_BGOH*u~fjUmShjhe.K\L7J)]VNDYY=6;T2,MZPNG&MNBR]VNB]JJ^5>U'YRBNQFN^AFHI)tqgiTjRkkgd-V[AIR\9927X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-p}keXnVookh!Z_EMVP45f3\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!|yoa\bZccol%bHB[[<1<0e>S7'@U]EB!HEO]P]KEXAGQ85P \YOA\MKYDMEF$t`l_g]f`bc(aME^X1?1319V4*OX^@E$KH@PSXL@[LH\;0W%_T@L_HL\G@JK'zseoRhPotv00>S7'@U]EB!HEO]P]KEXAGQ85P \YOA\MKYDMEF$t`l_lw{[cYh}}9?7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-p}keXe|rT~Razt2g8Q5)NW_CD#JKA_R[MGZOIS:3V"^WAC^KM[FCKD&yrbnQ}_dfda*OXD;B%YRJ@UU1:?P6(AV\BC"IJN^QZJFYNFR92Q#]VNB]JJZEBDE%xucmPr^ggc`)RWME^X==6;T2,MZPNG&MNBR]VNB]JJ^5>U'YRBNQFN^AFHI)tqgiT~Rkkgd-V[AIR\89j7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-p}keXzVookh!fDNWW8584i2_;#DQYIN-DAKYTQGITECU<9\,P]KEXAGUHIAB sxl`[wYblno$eIAZT=3=75=R8&CTZDA GDL\W\HDW@DP?4S!SXL@[LHXKLFG#~wac^p\kpr5n2_;#DQYIN-DAKYTQGITECU<9\,P]KEXAGUHIAB urgq[lhXf:;0Y=!F_WKL+BCIWZSEORGA[52^*V_IKVCESNKCL.CP]KEXNVG^T>?4U1-J[SOH'NOES^WAC^KM_16Z&ZSEORGA_BGOH*GTQGIT^RCZX3d8Q5)NW_CD#JKA_R[MGZOIS=:V"^WAC^KM[FCKD&YCEKZPRDE04>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$_T@L_G]NQ]573\:$ERXFO.EFJZU^FJUBBV:?]/QZJFYNFVIN@A!\YOA\VZKRP:90Y=!F_WKL+BCIWZSEORGA[52^*V_IKVCESNKCL.Q\EV_IKVLT^HI<3:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ([VKXUCMPR^PFC64<]9%BS[G@/FGM[V_IKVCEW9>R.R[MGZOIWJOG@"]PSXL@[CYUMN997X> I^TJK*ABFVYRBNQFNZ63Y+U^FJUBBRMJLM-P[V_IKVXT^HI<2:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ(]ZOYSNBD_SGD6`=R8&CTZDA GDL\W\HDW@DP8=S!SXL@[LHXKLFG#X]JR^OV\7c<]9%BS[G@/FGM[V_IKVCEW9>R.R[MGZOIWJOG@"[\ES]QAB4a3\:$ERXFO.EFJZU^FJUBBV:?]/QZJFYNFVIN@A!Z_GCOHLH@:l1^<"GPVHM,C@HX[PDHSD@T41_-W\HDW@DTOHBC/T]QMVOIO:;0Y=!F_WKL+BCIWZSEORGA[52^*V_IKVCESNKCL.W\WQGSKDNTb?k4U1-J[SOH'NOES^WAC^KM_16Z&ZSEORGA_BGOH*SX[PDHSK<j;T2,MZPNG&MNBR]VNB]JJ^27U'YRBNQFN^AFHI)RWZSEOR\<5:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ(izseoRczx^d\kpr4=2_;#DQYIN-DAKYTQGITECU;0\,P]KEXAGUHIAB ar{mgZkrpVxTcxz=d:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ(keehghj=d:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ(nhfgeci<1:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ(nhfgeciPotv1`>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$ji?Potv1`>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$ji<Potv1`>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$ji=Potv1`>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$ji:Potv1`>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$ji;Potv1a>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$axv>_nww6f=R8&CTZDA GDL\W\HDW@DP8=S!SXL@[LHXKLFG#g|ioe04>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$~d}fnf]lqq5b3\:$ERXFO.EFJZU^FJUBBV:?]/QZJFYNFVIN@A!|yoa\bZccol%BSE<C.T]GKPR412_;#DQYIN-DAKYTQGITECU;0\,P]KEXAGUHIAB sxl`[cYblno$YRJ@UU20=>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$t`l_g]f`bc(]VNDYY?<a:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ({pdhSkQjdfg,mAIR\5:5?l5Z0.K\RLI(OLDT_T@L_HLX05[)[PDHSD@PCDNO+vikVlTiiij/hFLQQ:66::0Y=!F_WKL+BCIWZSEORGA[52^*V_IKVCESNKCL.qzjfYaWf?95Z0.K\RLI(OLDT_T@L_HLX05[)[PDHSD@PCDNO+vikVg~tRhPotv00>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$t`l_lw{[wYh}}9n7X> I^TJK*ABFVYRBNQFNZ63Y+U^FJUBBRMJLM-p}keXzVookh!F_M0K*PYCG\^856[?/H]UMJ)@MGUXUCMPIOY74X(TQGITECQLEMN,w|hdW{Unhjk U^FLQQ6412_;#DQYIN-DAKYTQGITECU;0\,P]KEXAGUHIAB sxl`[wYblno$YRJ@UU30e>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$t`l_s]f`bc(aME^X1>13`9V4*OX^@E$KH@PSXL@[LH\<9W%_T@L_HL\G@JK'zseoR|Peeef+lBH]]6:2>>4U1-J[SOH'NOES^WAC^KM_16Z&ZSEORGA_BGOH*u~fjUySb{{2g9V4*OX^@E$KH@PSXL@[LH\<9W%_T@L_HL\G@JK'|yn~Rga_o12?P6(AV\BC"IJN^QZJFYNFR>:Q#]VNB]JJZEBDE%J_T@L_G]NQ]563\:$ERXFO.EFJZU^FJUBBV:>]/QZJFYNFVIN@A!NSXL@[WYJ]Q8m7X> I^TJK*ABFVYRBNQFNZ62Y+U^FJUBBRMJLM-PLL@SW[OL?=5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+V_IKVLTAXV<0:W3+LYQAF%LICQ\YOA\MK]39T$XUCMPIO]@AIJ([PDHS_QBUY10?P6(AV\BC"IJN^QZJFYNFR>:Q#]VNB]JJZEBDE%XSL]VNB]E[WC@;:1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/R]BW\HDW[UYIJ==;T2,MZPNG&MNBR]VNB]JJ^26U'YRBNQFN^AFHI)TWZSEORHPRDE06>S7'@U]EB!HEO]P]KEXAGQ?=P \YOA\MKYDMEF$_R]VNB]Q[WC@;;1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/TQFVZEKCVXNK?k4U1-J[SOH'NOES^WAC^KM_17Z&ZSEORGA_BGOH*STM[UFYU<j;T2,MZPNG&MNBR]VNB]JJ^26U'YRBNQFN^AFHI)R[LXT^HI=f:W3+LYQAF%LICQ\YOA\MK]39T$XUCMPIO]@AIJ(]VLJ@AGAG3g8Q5)NW_CD#JKA_R[MGZOIS=;V"^WAC^KM[FCKD&_T^D]FNF12?P6(AV\BC"IJN^QZJFYNFR>:Q#]VNB]JJZEBDE%^S^ZNTBOG[k4b3\:$ERXFO.EFJZU^FJUBBV:>]/QZJFYNFVIN@A!Z_R[MGZ@5m2_;#DQYIN-DAKYTQGITECU;1\,P]KEXAGUHIAB U^QZJFYU;<1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/`qzjfYj}qUmSb{{349V4*OX^@E$KH@PSXL@[LH\<8W%_T@L_HL\G@JK'hyrbnQbuy]q[jss:m1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/bnlgncc:m1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/gcohlh`;81^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/gcohlh`Wf>i5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+cb6Wf>i5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+cb5Wf>i5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+cb4Wf>i5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+cb3Wf>i5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+cb2Wf>h5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+hs9Ve~x?m4U1-J[SOH'NOES^WAC^KM_17Z&ZSEORGA_BGOH*tn{`dl?=5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+wotagmTcxz<e:W3+LYQAF%LICQ\YOA\MK]39T$XUCMPIO]@AIJ({pdhSkQjdfg,MZN5D'_THB[[389V4*OX^@E$KH@PSXL@[LH\<8W%_T@L_HL\G@JK'zseoRhPeeef+PYCG\^;?45Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+vikVlTiiij/T]GKPR6;h1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/r{mgZ`Xmmmn#dJ@UU>3:6g<]9%BS[G@/FGM[V_IKVCEW9?R.R[MGZOIWJOG@"}vnb]e[`b`m&cOCXZ31?13?P6(AV\BC"IJN^QZJFYNFR>:Q#]VNB]JJZEBDE%xucmPf^mvp62<]9%BS[G@/FGM[V_IKVCEW9?R.R[MGZOIWJOG@"}vnb]nq}YaWf?95Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+vikVg~tR|Potv0a>S7'@U]EB!HEO]P]KEXAGQ?=P \YOA\MKYDMEF$t`l_s]f`bc(AVF9D#[PDNWW7<=R8&CTZDA GDL\W\HDW@DP8<S!SXL@[LHXKLFG#~wac^p\aaab'\UOCXZ?389V4*OX^@E$KH@PSXL@[LH\<8W%_T@L_HL\G@JK'zseoR|Peeef+PYCG\^:?l5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+vikVxTiiij/hFLQQ:76:k0Y=!F_WKL+BCIWZSEORGA[53^*V_IKVCESNKCL.qzjfYuWlnli"gKOTV?5;573\:$ERXFO.EFJZU^FJUBBV:>]/QZJFYNFVIN@A!|yoa\vZir|;l0Y=!F_WKL+BCIWZSEORGA[53^*V_IKVCESNKCL.wpawYnfVd8=6[?/H]UMJ)@MGUXUCMPIOY76X(TQGITECQLEMN,EV_IKVLTAXV<1:W3+LYQAF%LICQ\YOA\MK]3:T$XUCMPIO]@AIJ(IZSEOR\PMTZ1b>S7'@U]EB!HEO]P]KEXAGQ?>P \YOA\MKYDMEF$_EGIT^PFC66<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"]VNB]E[HS_;91^<"GPVHM,C@HX[PDHSD@T43_-W\HDW@DTOHBC/R[MGZTXE\R8?6[?/H]UMJ)@MGUXUCMPIOY76X(TQGITECQLEMN,WZGTQGITJR\JG218Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&YTM^WAC^P\V@A4:2_;#DQYIN-DAKYTQGITECU;2\,P]KEXAGUHIAB S^QZJFYAW[OL??5Z0.K\RLI(OLDT_T@L_HLX07[)[PDHSD@PCDNO+VYTQGIT^R\JG208Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&_XI_QLLJ]QAB4b3\:$ERXFO.EFJZU^FJUBBV:=]/QZJFYNFVIN@A!ZSDP\IP^5m2_;#DQYIN-DAKYTQGITECU;2\,P]KEXAGUHIAB URGQ[WC@:o1^<"GPVHM,C@HX[PDHSD@T43_-W\HDW@DTOHBC/T]EEIJNFN8n7X> I^TJK*ABFVYRBNQFNZ61Y+U^FJUBBRMJLM-V[WOTAGM8=6[?/H]UMJ)@MGUXUCMPIOY76X(TQGITECQLEMN,QZUSI]IFHR`=e:W3+LYQAF%LICQ\YOA\MK]3:T$XUCMPIO]@AIJ(]VYRBNQI2d9V4*OX^@E$KH@PSXL@[LH\<;W%_T@L_HL\G@JK'\UXUCMPR278Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&kxucmPmtz\bZir|:?0Y=!F_WKL+BCIWZSEORGA[50^*V_IKVCESNKCL.cp}keXe|rT~Razt3f8Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&igcnejd3f8Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&lj`agag238Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&lj`agag^mvp7b<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"hk1^mvp7b<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"hk2^mvp7b<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"hk3^mvp7b<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"hk4^mvp7b<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"hk5^mvp7c<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"czx0]lqq4d3\:$ERXFO.EFJZU^FJUBBV:=]/QZJFYNFVIN@A!}irkmc66<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"|fshld[jss;l1^<"GPVHM,C@HX[PDHSD@T43_-W\HDW@DTOHBC/r{mgZ`Xmmmn#DQG2M,V[AIR\:30Y=!F_WKL+BCIWZSEORGA[50^*V_IKVCESNKCL.qzjfYaWlnli"[PDNWW46?<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"}vnb]e[`b`m&_THB[[12c8Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&yrbnQi_dfda*oCG\^7<3=n;T2,MZPNG&MNBR]VNB]JJ^25U'YRBNQFN^AFHI)tqgiTjRkkgd-j@JSS4848<6[?/H]UMJ)@MGUXUCMPIOY76X(TQGITECQLEMN,w|hdWoUdyy=;;T2,MZPNG&MNBR]VNB]JJ^25U'YRBNQFN^AFHI)tqgiTaxvPf^mvp62<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"}vnb]nq}YuWf?h5Z0.K\RLI(OLDT_T@L_HLX07[)[PDHSD@PCDNO+vikVxTiiij/H]O6M(RWME^X>74U1-J[SOH'NOES^WAC^KM_14Z&ZSEORGA_BGOH*u~fjUyShjhe.W\@JSS8:30Y=!F_WKL+BCIWZSEORGA[50^*V_IKVCESNKCL.qzjfYuWlnli"[PDNWW56g<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"}vnb]q[`b`m&cOCXZ30?1b?P6(AV\BC"IJN^QZJFYNFR>9Q#]VNB]JJZEBDE%xucmPr^ggc`)nLF__0<0<0:W3+LYQAF%LICQ\YOA\MK]3:T$XUCMPIO]@AIJ({pdhSQ`uu0e?P6(AV\BC"IJN^QZJFYNFR>9Q#]VNB]JJZEBDE%~h|Pio]m74=R8&CTZDA GDL\W\HDW@DP8>S!SXL@[LHXKLFG#L]VNB]E[HS_;81^<"GPVHM,C@HX[PDHSD@T42_-W\HDW@DTOHBC/@QZJFYUWD_S>k5Z0.K\RLI(OLDT_T@L_HLX06[)[PDHSD@PCDNO+VNNN]UYIJ=?;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)TQGITJRCZX228Q5)NW_CD#JKA_R[MGZOIS=9V"^WAC^KM[FCKD&YRBNQ]_LW[76=R8&CTZDA GDL\W\HDW@DP8>S!SXL@[LHXKLFG#^QNSXL@[CYUMN987X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-P[DU^FJUYS_KH339V4*OX^@E$KH@PSXL@[LH\<:W%_T@L_HL\G@JK'ZUXUCMPF^PFC64<]9%BS[G@/FGM[V_IKVCEW9=R.R[MGZOIWJOG@"]PSXL@[WYUMN997X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-VW@TXKEAT^HI=e:W3+LYQAF%LICQ\YOA\MK]3;T$XUCMPIO]@AIJ(]ZOYS@[W2d9V4*OX^@E$KH@PSXL@[LH\<:W%_T@L_HL\G@JK'\YN^R\JG3d8Q5)NW_CD#JKA_R[MGZOIS=9V"^WAC^KM[FCKD&_TJLBCIOE1a>S7'@U]EB!HEO]P]KEXAGQ??P \YOA\MKYDMEF$YR\FSHLD74=R8&CTZDA GDL\W\HDW@DP8>S!SXL@[LHXKLFG#XQ\T@V@IAYi:l1^<"GPVHM,C@HX[PDHSD@T42_-W\HDW@DTOHBC/T]P]KEXN;o0Y=!F_WKL+BCIWZSEORGA[51^*V_IKVCESNKCL.W\W\HDW[9>7X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-bw|hdWdsSkQ`uu16?P6(AV\BC"IJN^QZJFYNFR>8Q#]VNB]JJZEBDE%jt`l_lw{[wYh}}8o7X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-`hjelmm8o7X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-eeijnfn9:7X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-eeijnfnUdyy<k;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)al8Udyy<k;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)al;Udyy<k;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)al:Udyy<k;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)al=Udyy<k;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)al<Udyy<j;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)j}q;Tcxz=c:W3+LYQAF%LICQ\YOA\MK]3;T$XUCMPIO]@AIJ(z`ybbj=?;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)uazcekRazt2g8Q5)NW_CD#JKA_R[MGZOIS=9V"^WAC^KM[FCKD&yrbnQi_dfda*OX@;F%YRJ@UU1:?P6(AV\BC"IJN^QZJFYNFR>8Q#]VNB]JJZEBDE%xucmPf^ggc`)RWME^X==6;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)tqgiTjRkkgd-V[AIR\89j7X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-p}keXnVookh!fDNWW8584i2_;#DQYIN-DAKYTQGITECU;3\,P]KEXAGUHIAB sxl`[cYblno$eIAZT=3=75=R8&CTZDA GDL\W\HDW@DP8>S!SXL@[LHXKLFG#~wac^d\kpr4<2_;#DQYIN-DAKYTQGITECU;3\,P]KEXAGUHIAB sxl`[hsWoUdyy=;;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)tqgiTaxvPr^mvp6c<]9%BS[G@/FGM[V_IKVCEW9=R.R[MGZOIWJOG@"}vnb]q[`b`m&CT@?F!U^FLQQ5>3\:$ERXFO.EFJZU^FJUBBV:<]/QZJFYNFVIN@A!|yoa\vZccol%^SIAZT11:?P6(AV\BC"IJN^QZJFYNFR>8Q#]VNB]JJZEBDE%xucmPr^ggc`)RWME^X<=n;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)tqgiT~Rkkgd-j@JSS4948m6[?/H]UMJ)@MGUXUCMPIOY77X(TQGITECQLEMN,w|hdW{Unhjk iEMVP979;91^<"GPVHM,C@HX[PDHSD@T42_-W\HDW@DTOHBC/r{mgZtXg|~9j6[?/H]UMJ)@MGUXUCMPIOY77X(TQGITECQLEMN,qvcuW`dTb>?4U1-J[SOH'NOES^WAC^KM_12Z&ZSEORGA_BGOH*GTQGITJRCZX238Q5)NW_CD#JKA_R[MGZOIS=>V"^WAC^KM[FCKD&KXUCMPR^OV\7`<]9%BS[G@/FGM[V_IKVCEW9:R.R[MGZOIWJOG@"]GIGV\V@A482_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB SXL@[CYJ]Q9;7X> I^TJK*ABFVYRBNQFNZ67Y+U^FJUBBRMJLM-P]KEXZVG^T>=4U1-J[SOH'NOES^WAC^KM_12Z&ZSEORGA_BGOH*UXIZSEORHPRDE07>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$_RO\YOA\VZTBO:80Y=!F_WKL+BCIWZSEORGA[56^*V_IKVCESNKCL.Q\W\HDWOUYIJ==;T2,MZPNG&MNBR]VNB]JJ^23U'YRBNQFN^AFHI)TWZSEOR\PRDE06>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$Y^K]_BNH[WC@:l1^<"GPVHM,C@HX[PDHSD@T45_-W\HDW@DTOHBC/TQFVZKRP;o0Y=!F_WKL+BCIWZSEORGA[56^*V_IKVCESNKCL.WPAWYUMN8m7X> I^TJK*ABFVYRBNQFNZ67Y+U^FJUBBRMJLM-V[CGKD@DL>h5Z0.K\RLI(OLDT_T@L_HLX01[)[PDHSD@PCDNO+PYUAZCEK>?4U1-J[SOH'NOES^WAC^KM_12Z&ZSEORGA_BGOH*SX[]K_O@JPn3g8Q5)NW_CD#JKA_R[MGZOIS=>V"^WAC^KM[FCKD&_T_T@L_G0f?P6(AV\BC"IJN^QZJFYNFR>?Q#]VNB]JJZEBDE%^S^WAC^P01>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$m~wac^ov|Z`Xg|~896[?/H]UMJ)@MGUXUCMPIOY70X(TQGITECQLEMN,evikVg~tR|Potv1`>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$oaalkdf1`>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$jlbcioe05>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$jlbcioe\kpr5l2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB fe3\kpr5l2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB fe0\kpr5l2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB fe1\kpr5l2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB fe6\kpr5l2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB fe7\kpr5m2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB mtz2[jss:j1^<"GPVHM,C@HX[PDHSD@T45_-W\HDW@DTOHBC/skpmka482_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB rhqjjbYh}}9n7X> I^TJK*ABFVYRBNQFNZ67Y+U^FJUBBRMJLM-p}keXnVookh!F_I0O*PYCG\^856[?/H]UMJ)@MGUXUCMPIOY70X(TQGITECQLEMN,w|hdWoUnhjk U^FLQQ6412_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB sxl`[cYblno$YRJ@UU30e>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$t`l_g]f`bc(aME^X1>13`9V4*OX^@E$KH@PSXL@[LH\<=W%_T@L_HL\G@JK'zseoRhPeeef+lBH]]6:2>>4U1-J[SOH'NOES^WAC^KM_12Z&ZSEORGA_BGOH*u~fjUmSb{{359V4*OX^@E$KH@PSXL@[LH\<=W%_T@L_HL\G@JK'zseoRczx^d\kpr4<2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB sxl`[hsW{Udyy=j;T2,MZPNG&MNBR]VNB]JJ^23U'YRBNQFN^AFHI)tqgiT~Rkkgd-J[I4O&\UOCXZ<9:W3+LYQAF%LICQ\YOA\MK]3<T$XUCMPIO]@AIJ({pdhSQjdfg,QZBH]]:856[?/H]UMJ)@MGUXUCMPIOY70X(TQGITECQLEMN,w|hdW{Unhjk U^FLQQ74i2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB sxl`[wYblno$eIAZT=2=7d=R8&CTZDA GDL\W\HDW@DP89S!SXL@[LHXKLFG#~wac^p\aaab'`NDYY2>>228Q5)NW_CD#JKA_R[MGZOIS=>V"^WAC^KM[FCKD&yrbnQ}_nww6c=R8&CTZDA GDL\W\HDW@DP89S!SXL@[LHXKLFG#x}jr^km[k563\:$ERXFO.EFJZU^FJUBBV::]/QZJFYNFVIN@A!NSXL@[CYJ]Q9:7X> I^TJK*ABFVYRBNQFNZ66Y+U^FJUBBRMJLM-BW\HDW[UFYU<i;T2,MZPNG&MNBR]VNB]JJ^22U'YRBNQFN^AFHI)T@@L_S_KH319V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'ZSEORHPMTZ04>S7'@U]EB!HEO]P]KEXAGQ?9P \YOA\MKYDMEF$_T@L_S]NQ]543\:$ERXFO.EFJZU^FJUBBV::]/QZJFYNFVIN@A!\_@QZJFYAW[OL?>5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+VYF[PDHS_Q]EF11?P6(AV\BC"IJN^QZJFYNFR>>Q#]VNB]JJZEBDE%XS^WAC^D\V@A4:2_;#DQYIN-DAKYTQGITECU;5\,P]KEXAGUHIAB S^QZJFYUW[OL??5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+PUBZVIGGR\JG3g8Q5)NW_CD#JKA_R[MGZOIS=?V"^WAC^KM[FCKD&_XI_QBUY0f?P6(AV\BC"IJN^QZJFYNFR>>Q#]VNB]JJZEBDE%^_H\PRDE1b>S7'@U]EB!HEO]P]KEXAGQ?9P \YOA\MKYDMEF$YRHNLMKMC7c<]9%BS[G@/FGM[V_IKVCEW9;R.R[MGZOIWJOG@"[PRHQJJB563\:$ERXFO.EFJZU^FJUBBV::]/QZJFYNFVIN@A!Z_RVBPFKCWg8n7X> I^TJK*ABFVYRBNQFNZ66Y+U^FJUBBRMJLM-V[V_IKVL9i6[?/H]UMJ)@MGUXUCMPIOY71X(TQGITECQLEMN,QZU^FJUY?85Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+du~fjUfyuQi_nww70=R8&CTZDA GDL\W\HDW@DP88S!SXL@[LHXKLFG#l}vnb]nq}YuWf>i5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+fjhkboo>i5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+cgkd`dl?<5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+cgkd`dlSb{{2e9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'on:Sb{{2e9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'on9Sb{{2e9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'on8Sb{{2e9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'on?Sb{{2e9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'on>Sb{{2d9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'ds=Razt3a8Q5)NW_CD#JKA_R[MGZOIS=?V"^WAC^KM[FCKD&xbd`h319V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'{cxeciPotv0a>S7'@U]EB!HEO]P]KEXAGQ?9P \YOA\MKYDMEF$t`l_g]f`bc(AVB9@#[PDNWW7<=R8&CTZDA GDL\W\HDW@DP88S!SXL@[LHXKLFG#~wac^d\aaab'\UOCXZ?389V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'zseoRhPeeef+PYCG\^:?l5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+vikVlTiiij/hFLQQ:76:k0Y=!F_WKL+BCIWZSEORGA[57^*V_IKVCESNKCL.qzjfYaWlnli"gKOTV?5;573\:$ERXFO.EFJZU^FJUBBV::]/QZJFYNFVIN@A!|yoa\bZir|:>0Y=!F_WKL+BCIWZSEORGA[57^*V_IKVCESNKCL.qzjfYj}qUmSb{{359V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'zseoRczx^p\kpr4m2_;#DQYIN-DAKYTQGITECU;5\,P]KEXAGUHIAB sxl`[wYblno$ERB=H/W\@JSS;01^<"GPVHM,C@HX[PDHSD@T44_-W\HDW@DTOHBC/r{mgZtXmmmn#XQKOTV37<=R8&CTZDA GDL\W\HDW@DP88S!SXL@[LHXKLFG#~wac^p\aaab'\UOCXZ>3`9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'zseoR|Peeef+lBH]]6;2>o4U1-J[SOH'NOES^WAC^KM_13Z&ZSEORGA_BGOH*u~fjUyShjhe.kGKPR;979;7X> I^TJK*ABFVYRBNQFNZ66Y+U^FJUBBRMJLM-p}keXzVe~x?h4U1-J[SOH'NOES^WAC^KM_13Z&ZSEORGA_BGOH*stm{UbbR`<1:W3+LYQAF%LICQ\YOA\MK]3>T$XUCMPIO]@AIJ(IZSEORHPMTZ05>S7'@U]EB!HEO]P]KEXAGQ?:P \YOA\MKYDMEF$M^WAC^P\IP^5n2_;#DQYIN-DAKYTQGITECU;6\,P]KEXAGUHIAB SIKEPZTBO::0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.QZJFYAWD_S?=5Z0.K\RLI(OLDT_T@L_HLX03[)[PDHSD@PCDNO+V_IKVXTAXV<3:W3+LYQAF%LICQ\YOA\MK]3>T$XUCMPIO]@AIJ([VKXUCMPF^PFC65<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"]PAR[MGZTXZLM8>6[?/H]UMJ)@MGUXUCMPIOY72X(TQGITECQLEMN,WZU^FJUMS_KH339V4*OX^@E$KH@PSXL@[LH\<?W%_T@L_HL\G@JK'ZUXUCMPR^PFC64<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"[\ES]@HNYUMN8n7X> I^TJK*ABFVYRBNQFNZ65Y+U^FJUBBRMJLM-VW@TXE\R9i6[?/H]UMJ)@MGUXUCMPIOY72X(TQGITECQLEMN,QVCUW[OL>k5Z0.K\RLI(OLDT_T@L_HLX03[)[PDHSD@PCDNO+PYAIEFBBJ<j;T2,MZPNG&MNBR]VNB]JJ^21U'YRBNQFN^AFHI)RW[CXECI<1:W3+LYQAF%LICQ\YOA\MK]3>T$XUCMPIO]@AIJ(]VY_MYMBD^l1a>S7'@U]EB!HEO]P]KEXAGQ?:P \YOA\MKYDMEF$YR]VNB]E6`=R8&CTZDA GDL\W\HDW@DP8;S!SXL@[LHXKLFG#XQ\YOA\V63<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"o|yoa\ip~XnVe~x>;4U1-J[SOH'NOES^WAC^KM_10Z&ZSEORGA_BGOH*gtqgiTaxvPr^mvp7b<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"mcobif`7b<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"hnlmkmc67<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"hnlmkmcZir|;n0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.dg5Zir|;n0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.dg6Zir|;n0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.dg7Zir|;n0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.dg0Zir|;n0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.dg1Zir|;o0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.ov|4Yh}}8h7X> I^TJK*ABFVYRBNQFNZ65Y+U^FJUBBRMJLM-qmvoio::0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.pjwlh`Wf?h5Z0.K\RLI(OLDT_T@L_HLX03[)[PDHSD@PCDNO+vikVlTiiij/H]K6I(RWME^X>74U1-J[SOH'NOES^WAC^KM_10Z&ZSEORGA_BGOH*u~fjUmShjhe.W\@JSS8:30Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.qzjfYaWlnli"[PDNWW56g<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"}vnb]e[`b`m&cOCXZ30?1b?P6(AV\BC"IJN^QZJFYNFR>=Q#]VNB]JJZEBDE%xucmPf^ggc`)nLF__0<0<0:W3+LYQAF%LICQ\YOA\MK]3>T$XUCMPIO]@AIJ({pdhSkQ`uu17?P6(AV\BC"IJN^QZJFYNFR>=Q#]VNB]JJZEBDE%xucmPmtz\bZir|:>0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.qzjfYj}qUySb{{3d9V4*OX^@E$KH@PSXL@[LH\<?W%_T@L_HL\G@JK'zseoR|Peeef+LYK:A$^SIAZT2;8Q5)NW_CD#JKA_R[MGZOIS=<V"^WAC^KM[FCKD&yrbnQ}_dfda*SXLF__<>74U1-J[SOH'NOES^WAC^KM_10Z&ZSEORGA_BGOH*u~fjUyShjhe.W\@JSS9:k0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.qzjfYuWlnli"gKOTV?4;5f3\:$ERXFO.EFJZU^FJUBBV:9]/QZJFYNFVIN@A!|yoa\vZccol%bHB[[<0<04>S7'@U]EB!HEO]P]KEXAGQ?:P \YOA\MKYDMEF$t`l_s]lqq4a3\:$ERXFO.EFJZU^FJUBBV:9]/QZJFYNFVIN@A!zsdp\mkYi;81^<"GPVHM,C@HX[PDHSD@T46_-W\HDW@DTOHBC/@QZJFYAWD_S?<5Z0.K\RLI(OLDT_T@L_HLX02[)[PDHSD@PCDNO+DU^FJUYS@[W2g9V4*OX^@E$KH@PSXL@[LH\<>W%_T@L_HL\G@JK'ZBBJYQ]EF13?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%XUCMPF^OV\66<]9%BS[G@/FGM[V_IKVCEW99R.R[MGZOIWJOG@"]VNB]Q[HS_;:1^<"GPVHM,C@HX[PDHSD@T46_-W\HDW@DTOHBC/R]BW\HDWOUYIJ=<;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)TWHYRBNQ]_SGD77=R8&CTZDA GDL\W\HDW@DP8:S!SXL@[LHXKLFG#^Q\YOA\BZTBO:80Y=!F_WKL+BCIWZSEORGA[55^*V_IKVCESNKCL.Q\W\HDW[UYIJ==;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)R[LXTOAEPRDE1a>S7'@U]EB!HEO]P]KEXAGQ?;P \YOA\MKYDMEF$Y^K]_LW[6`=R8&CTZDA GDL\W\HDW@DP8:S!SXL@[LHXKLFG#X]JR^PFC7`<]9%BS[G@/FGM[V_IKVCEW99R.R[MGZOIWJOG@"[PF@NOMKA5m2_;#DQYIN-DAKYTQGITECU;7\,P]KEXAGUHIAB U^PJWLH@;81^<"GPVHM,C@HX[PDHSD@T46_-W\HDW@DTOHBC/T]PPDRDEMUe>h5Z0.K\RLI(OLDT_T@L_HLX02[)[PDHSD@PCDNO+PYTQGITJ?k4U1-J[SOH'NOES^WAC^KM_11Z&ZSEORGA_BGOH*SX[PDHS_=:;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)f{pdhS`{w_g]lqq523\:$ERXFO.EFJZU^FJUBBV:8]/QZJFYNFVIN@A!nsxl`[hsW{Udyy<k;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)ddfi`ii<k;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)aiefbbj=>;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)aiefbbjQ`uu0g?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%mh<Q`uu0g?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%mh?Q`uu0g?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%mh>Q`uu0g?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%mh9Q`uu0g?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%mh8Q`uu0f?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%fyu?Potv1g>S7'@U]EB!HEO]P]KEXAGQ?;P \YOA\MKYDMEF$~d}fnf13?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%ye~gag^mvp6c<]9%BS[G@/FGM[V_IKVCEW99R.R[MGZOIWJOG@"}vnb]e[`b`m&CTD?B!U^FLQQ5>3\:$ERXFO.EFJZU^FJUBBV:8]/QZJFYNFVIN@A!|yoa\bZccol%^SIAZT11:?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%xucmPf^ggc`)RWME^X<=n;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)tqgiTjRkkgd-j@JSS4948m6[?/H]UMJ)@MGUXUCMPIOY73X(TQGITECQLEMN,w|hdWoUnhjk iEMVP979;91^<"GPVHM,C@HX[PDHSD@T46_-W\HDW@DTOHBC/r{mgZ`Xg|~886[?/H]UMJ)@MGUXUCMPIOY73X(TQGITECQLEMN,w|hdWdsSkQ`uu17?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%xucmPmtz\vZir|:o0Y=!F_WKL+BCIWZSEORGA[55^*V_IKVCESNKCL.qzjfYuWlnli"GPL3J-QZBH]]927X> I^TJK*ABFVYRBNQFNZ64Y+U^FJUBBRMJLM-p}keXzVookh!Z_EMVP55>3\:$ERXFO.EFJZU^FJUBBV:8]/QZJFYNFVIN@A!|yoa\vZccol%^SIAZT01b?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%xucmPr^ggc`)nLF__0=0<a:W3+LYQAF%LICQ\YOA\MK]3?T$XUCMPIO]@AIJ({pdhSQjdfg,mAIR\5;5?=5Z0.K\RLI(OLDT_T@L_HLX02[)[PDHSD@PCDNO+vikVxTcxz=f:W3+LYQAF%LICQ\YOA\MK]3?T$XUCMPIO]@AIJ(}zoySd`Pn238Q5)NW_CD#JKA_R[MGZOIS=2V"^WAC^KM[FCKD&KXUCMPF^OV\67<]9%BS[G@/FGM[V_IKVCEW96R.R[MGZOIWJOG@"O\YOA\VZKRP;l0Y=!F_WKL+BCIWZSEORGA[5:^*V_IKVCESNKCL.QKMCRXZLM8<6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,W\HDWOUFYU=?;T2,MZPNG&MNBR]VNB]JJ^2?U'YRBNQFN^AFHI)TQGIT^RCZX218Q5)NW_CD#JKA_R[MGZOIS=2V"^WAC^KM[FCKD&YTM^WAC^D\V@A4;2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB S^CP]KEXZVXNK><4U1-J[SOH'NOES^WAC^KM_1>Z&ZSEORGA_BGOH*UX[PDHSKQ]EF11?P6(AV\BC"IJN^QZJFYNFR>3Q#]VNB]JJZEBDE%XS^WAC^P\V@A4:2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB URGQ[FJLW[OL>h5Z0.K\RLI(OLDT_T@L_HLX0=[)[PDHSD@PCDNO+PUBZVG^T?k4U1-J[SOH'NOES^WAC^KM_1>Z&ZSEORGA_BGOH*STM[UYIJ<i;T2,MZPNG&MNBR]VNB]JJ^2?U'YRBNQFN^AFHI)RWOKG@D@H2d9V4*OX^@E$KH@PSXL@[LH\<1W%_T@L_HL\G@JK'\UYE^GAG238Q5)NW_CD#JKA_R[MGZOIS=2V"^WAC^KM[FCKD&_T_YO[CLF\j7c<]9%BS[G@/FGM[V_IKVCEW96R.R[MGZOIWJOG@"[PSXL@[C4b3\:$ERXFO.EFJZU^FJUBBV:7]/QZJFYNFVIN@A!Z_R[MGZT4=2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB ar{mgZkrpVlTcxz<5:W3+LYQAF%LICQ\YOA\MK]30T$XUCMPIO]@AIJ(izseoRczx^p\kpr5l2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB cmm`o`b5l2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB f`nomka492_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB f`nomkaXg|~9h6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ba7Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ba4Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ba5Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ba2Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ba3Xg|~9i6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ip~6Wf>n5Z0.K\RLI(OLDT_T@L_HLX0=[)[PDHSD@PCDNO+wotagm8<6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,vlunfnUdyy=j;T2,MZPNG&MNBR]VNB]JJ^2?U'YRBNQFN^AFHI)tqgiTjRkkgd-J[M4K&\UOCXZ<9:W3+LYQAF%LICQ\YOA\MK]30T$XUCMPIO]@AIJ({pdhSkQjdfg,QZBH]]:856[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,w|hdWoUnhjk U^FLQQ74i2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB sxl`[cYblno$eIAZT=2=7d=R8&CTZDA GDL\W\HDW@DP85S!SXL@[LHXKLFG#~wac^d\aaab'`NDYY2>>228Q5)NW_CD#JKA_R[MGZOIS=2V"^WAC^KM[FCKD&yrbnQi_nww71=R8&CTZDA GDL\W\HDW@DP85S!SXL@[LHXKLFG#~wac^ov|Z`Xg|~886[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,w|hdWdsSQ`uu1f?P6(AV\BC"IJN^QZJFYNFR>3Q#]VNB]JJZEBDE%xucmPr^ggc`)NWE8C"XQKOTV0=>S7'@U]EB!HEO]P]KEXAGQ?4P \YOA\MKYDMEF$t`l_s]f`bc(]VNDYY><9:W3+LYQAF%LICQ\YOA\MK]30T$XUCMPIO]@AIJ({pdhSQjdfg,QZBH]];8m6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,w|hdW{Unhjk iEMVP969;h1^<"GPVHM,C@HX[PDHSD@T49_-W\HDW@DTOHBC/r{mgZtXmmmn#dJ@UU>2:66<]9%BS[G@/FGM[V_IKVCEW96R.R[MGZOIWJOG@"}vnb]q[jss:o1^<"GPVHM,C@HX[PDHSD@T49_-W\HDW@DTOHBC/tqfvZoiWg9:7X> I^TJK*ABFVYRBNQFNZ6:Y+U^FJUBBRMJLM-BW\HDWOUFYU=>;T2,MZPNG&MNBR]VNB]JJ^2>U'YRBNQFN^AFHI)F[PDHS_QBUY0e?P6(AV\BC"IJN^QZJFYNFR>2Q#]VNB]JJZEBDE%XDDH[_SGD75=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#^WAC^D\IP^482_;#DQYIN-DAKYTQGITECU;9\,P]KEXAGUHIAB SXL@[WYJ]Q987X> I^TJK*ABFVYRBNQFNZ6:Y+U^FJUBBRMJLM-P[DU^FJUMS_KH329V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'ZUJ_T@L_S]QAB553\:$ERXFO.EFJZU^FJUBBV:6]/QZJFYNFVIN@A!\_R[MGZ@XZLM8>6[?/H]UMJ)@MGUXUCMPIOY7=X(TQGITECQLEMN,WZU^FJUYS_KH339V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'\YN^RMCK^PFC7c<]9%BS[G@/FGM[V_IKVCEW97R.R[MGZOIWJOG@"[\ES]NQ]4b3\:$ERXFO.EFJZU^FJUBBV:6]/QZJFYNFVIN@A!ZSDP\V@A5n2_;#DQYIN-DAKYTQGITECU;9\,P]KEXAGUHIAB U^DBHIOIO;o0Y=!F_WKL+BCIWZSEORGA[5;^*V_IKVCESNKCL.W\VLUNFN9:7X> I^TJK*ABFVYRBNQFNZ6:Y+U^FJUBBRMJLM-V[VRF\JGOSc<j;T2,MZPNG&MNBR]VNB]JJ^2>U'YRBNQFN^AFHI)RWZSEORH=e:W3+LYQAF%LICQ\YOA\MK]31T$XUCMPIO]@AIJ(]VYRBNQ]349V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'hyrbnQbuy]e[jss;<1^<"GPVHM,C@HX[PDHSD@T48_-W\HDW@DTOHBC/`qzjfYj}qUySb{{2e9V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'jfdofkk2e9V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'okg`d`h309V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'okg`d`h_nww6a=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#kj>_nww6a=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#kj=_nww6a=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#kj<_nww6a=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#kj;_nww6a=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#kj:_nww6`=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#`{w1^mvp7e<]9%BS[G@/FGM[V_IKVCEW97R.R[MGZOIWJOG@"|fshld75=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#g|ioe\kpr4m2_;#DQYIN-DAKYTQGITECU;9\,P]KEXAGUHIAB sxl`[cYblno$ERF=L/W\@JSS;01^<"GPVHM,C@HX[PDHSD@T48_-W\HDW@DTOHBC/r{mgZ`Xmmmn#XQKOTV37<=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#~wac^d\aaab'\UOCXZ>3`9V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'zseoRhPeeef+lBH]]6;2>o4U1-J[SOH'NOES^WAC^KM_1?Z&ZSEORGA_BGOH*u~fjUmShjhe.kGKPR;979;7X> I^TJK*ABFVYRBNQFNZ6:Y+U^FJUBBRMJLM-p}keXnVe~x>:4U1-J[SOH'NOES^WAC^KM_1?Z&ZSEORGA_BGOH*u~fjUfyuQi_nww71=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#~wac^ov|ZtXg|~8i6[?/H]UMJ)@MGUXUCMPIOY7=X(TQGITECQLEMN,w|hdW{Unhjk I^N1L+SXLF__?45Z0.K\RLI(OLDT_T@L_HLX0<[)[PDHSD@PCDNO+vikVxTiiij/T]GKPR7;01^<"GPVHM,C@HX[PDHSD@T48_-W\HDW@DTOHBC/r{mgZtXmmmn#XQKOTV27d=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#~wac^p\aaab'`NDYY2?>2c8Q5)NW_CD#JKA_R[MGZOIS=3V"^WAC^KM[FCKD&yrbnQ}_dfda*oCG\^7=3=?;T2,MZPNG&MNBR]VNB]JJ^2>U'YRBNQFN^AFHI)tqgiT~Razt3d8Q5)NW_CD#JKA_R[MGZOIS=3V"^WAC^KM[FCKD&xiQfn^l05>S7'@U]EB!HEO]P]KEXAGQ><P \YOA\MKYDMEF$M^WAC^D\IP^492_;#DQYIN-DAKYTQGITECU:0\,P]KEXAGUHIAB AR[MGZTXE\R9j6[?/H]UMJ)@MGUXUCMPIOY64X(TQGITECQLEMN,WMOA\VXNK>>4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*U^FJUMS@[W319V4*OX^@E$KH@PSXL@[LH\=9W%_T@L_HL\G@JK'ZSEOR\PMTZ07>S7'@U]EB!HEO]P]KEXAGQ><P \YOA\MKYDMEF$_RO\YOA\BZTBO:90Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.Q\EV_IKVXT^HI<2:W3+LYQAF%LICQ\YOA\MK]28T$XUCMPIO]@AIJ([VYRBNQI_SGD77=R8&CTZDA GDL\W\HDW@DP9=S!SXL@[LHXKLFG#^Q\YOA\VZTBO:80Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.WPAWYDDBUYIJ<j;T2,MZPNG&MNBR]VNB]JJ^37U'YRBNQFN^AFHI)R[LXTAXV=e:W3+LYQAF%LICQ\YOA\MK]28T$XUCMPIO]@AIJ(]ZOYS_KH2g9V4*OX^@E$KH@PSXL@[LH\=9W%_T@L_HL\G@JK'\UMMABFNF0f?P6(AV\BC"IJN^QZJFYNFR?;Q#]VNB]JJZEBDE%^S_G\IOE05>S7'@U]EB!HEO]P]KEXAGQ><P \YOA\MKYDMEF$YR][AUAN@Zh5m2_;#DQYIN-DAKYTQGITECU:0\,P]KEXAGUHIAB U^QZJFYA:l1^<"GPVHM,C@HX[PDHSD@T51_-W\HDW@DTOHBC/T]P]KEXZ:?0Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.cp}keXe|rTjRazt278Q5)NW_CD#JKA_R[MGZOIS<:V"^WAC^KM[FCKD&kxucmPmtz\vZir|;n0Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.aokfmbl;n0Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.dbhioio:;0Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.dbhioioVe~x?j4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*`c9Ve~x?j4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*`c:Ve~x?j4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*`c;Ve~x?j4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*`c<Ve~x?j4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*`c=Ve~x?k4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*krp8Udyy<l;T2,MZPNG&MNBR]VNB]JJ^37U'YRBNQFN^AFHI)uazcek>>4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*tn{`dlSb{{3d9V4*OX^@E$KH@PSXL@[LH\=9W%_T@L_HL\G@JK'zseoRhPeeef+LYO:E$^SIAZT2;8Q5)NW_CD#JKA_R[MGZOIS<:V"^WAC^KM[FCKD&yrbnQi_dfda*SXLF__<>74U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*u~fjUmShjhe.W\@JSS9:k0Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.qzjfYaWlnli"gKOTV?4;5f3\:$ERXFO.EFJZU^FJUBBV;?]/QZJFYNFVIN@A!|yoa\bZccol%bHB[[<0<04>S7'@U]EB!HEO]P]KEXAGQ><P \YOA\MKYDMEF$t`l_g]lqq533\:$ERXFO.EFJZU^FJUBBV;?]/QZJFYNFVIN@A!|yoa\ip~XnVe~x>:4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*u~fjUfyuQ}_nww7`=R8&CTZDA GDL\W\HDW@DP9=S!SXL@[LHXKLFG#~wac^p\aaab'@UG>E Z_EMVP6?<]9%BS[G@/FGM[V_IKVCEW8>R.R[MGZOIWJOG@"}vnb]q[`b`m&_THB[[02;8Q5)NW_CD#JKA_R[MGZOIS<:V"^WAC^KM[FCKD&yrbnQ}_dfda*SXLF__=>o4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*u~fjUyShjhe.kGKPR;879j7X> I^TJK*ABFVYRBNQFNZ73Y+U^FJUBBRMJLM-p}keXzVookh!fDNWW848482_;#DQYIN-DAKYTQGITECU:0\,P]KEXAGUHIAB sxl`[wYh}}8m7X> I^TJK*ABFVYRBNQFNZ73Y+U^FJUBBRMJLM-vw`tXagUe?<5Z0.K\RLI(OLDT_T@L_HLX14[)[PDHSD@PCDNO+DU^FJUMS@[W309V4*OX^@E$KH@PSXL@[LH\=8W%_T@L_HL\G@JK'HYRBNQ]_LW[6c=R8&CTZDA GDL\W\HDW@DP9<S!SXL@[LHXKLFG#^FFFU]QAB573\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!\YOA\BZKRP::0Y=!F_WKL+BCIWZSEORGA[43^*V_IKVCESNKCL.QZJFYUWD_S?>5Z0.K\RLI(OLDT_T@L_HLX14[)[PDHSD@PCDNO+VYF[PDHSKQ]EF10?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%XSL]VNB]Q[WC@;;1^<"GPVHM,C@HX[PDHSD@T50_-W\HDW@DTOHBC/R]P]KEXNVXNK><4U1-J[SOH'NOES^WAC^KM_07Z&ZSEORGA_BGOH*UX[PDHS_Q]EF11?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%^_H\PCMI\V@A5m2_;#DQYIN-DAKYTQGITECU:1\,P]KEXAGUHIAB URGQ[HS_:l1^<"GPVHM,C@HX[PDHSD@T50_-W\HDW@DTOHBC/TQFVZTBO;l0Y=!F_WKL+BCIWZSEORGA[43^*V_IKVCESNKCL.W\BDJKAGM9i6[?/H]UMJ)@MGUXUCMPIOY65X(TQGITECQLEMN,QZTN[@DL?<5Z0.K\RLI(OLDT_T@L_HLX14[)[PDHSD@PCDNO+PYT\H^HAIQa2d9V4*OX^@E$KH@PSXL@[LH\=8W%_T@L_HL\G@JK'\UXUCMPF3g8Q5)NW_CD#JKA_R[MGZOIS<;V"^WAC^KM[FCKD&_T_T@L_S16?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%jt`l_lw{[cYh}}9>7X> I^TJK*ABFVYRBNQFNZ72Y+U^FJUBBRMJLM-bw|hdWdsSQ`uu0g?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%h`bmdee0g?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%mmabfnf12?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%mmabfnf]lqq4c3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!id0]lqq4c3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!id3]lqq4c3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!id2]lqq4c3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!id5]lqq4c3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!id4]lqq4b3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!buy3\kpr5k2_;#DQYIN-DAKYTQGITECU:1\,P]KEXAGUHIAB rhqjjb573\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!}irkmcZir|:o0Y=!F_WKL+BCIWZSEORGA[43^*V_IKVCESNKCL.qzjfYaWlnli"GPH3N-QZBH]]927X> I^TJK*ABFVYRBNQFNZ72Y+U^FJUBBRMJLM-p}keXnVookh!Z_EMVP55>3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!|yoa\bZccol%^SIAZT01b?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%xucmPf^ggc`)nLF__0=0<a:W3+LYQAF%LICQ\YOA\MK]29T$XUCMPIO]@AIJ({pdhSkQjdfg,mAIR\5;5?=5Z0.K\RLI(OLDT_T@L_HLX14[)[PDHSD@PCDNO+vikVlTcxz<4:W3+LYQAF%LICQ\YOA\MK]29T$XUCMPIO]@AIJ({pdhS`{w_g]lqq533\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!|yoa\ip~XzVe~x>k4U1-J[SOH'NOES^WAC^KM_07Z&ZSEORGA_BGOH*u~fjUyShjhe.K\H7N)]VNDYY=6;T2,MZPNG&MNBR]VNB]JJ^36U'YRBNQFN^AFHI)tqgiT~Rkkgd-V[AIR\9927X> I^TJK*ABFVYRBNQFNZ72Y+U^FJUBBRMJLM-p}keXzVookh!Z_EMVP45f3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!|yoa\vZccol%bHB[[<1<0e>S7'@U]EB!HEO]P]KEXAGQ>=P \YOA\MKYDMEF$t`l_s]f`bc(aME^X1?1319V4*OX^@E$KH@PSXL@[LH\=8W%_T@L_HL\G@JK'zseoR|Potv1b>S7'@U]EB!HEO]P]KEXAGQ>=P \YOA\MKYDMEF$y~k}_hl\j67<]9%BS[G@/FGM[V_IKVCEW8<R.R[MGZOIWJOG@"O\YOA\BZKRP:;0Y=!F_WKL+BCIWZSEORGA[40^*V_IKVCESNKCL.CP]KEXZVG^T?h4U1-J[SOH'NOES^WAC^KM_04Z&ZSEORGA_BGOH*UOAO^T^HI<0:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ([PDHSKQBUY13?P6(AV\BC"IJN^QZJFYNFR?9Q#]VNB]JJZEBDE%XUCMPR^OV\65<]9%BS[G@/FGM[V_IKVCEW8<R.R[MGZOIWJOG@"]PAR[MGZ@XZLM8?6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,WZGTQGIT^R\JG208Q5)NW_CD#JKA_R[MGZOIS<8V"^WAC^KM[FCKD&YT_T@L_G]QAB553\:$ERXFO.EFJZU^FJUBBV;=]/QZJFYNFVIN@A!\_R[MGZTXZLM8>6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,QVCUWJF@S_KH2d9V4*OX^@E$KH@PSXL@[LH\=;W%_T@L_HL\G@JK'\YN^RCZX3g8Q5)NW_CD#JKA_R[MGZOIS<8V"^WAC^KM[FCKD&_XI_Q]EF0e?P6(AV\BC"IJN^QZJFYNFR?9Q#]VNB]JJZEBDE%^SKOCLHLD6`=R8&CTZDA GDL\W\HDW@DP9?S!SXL@[LHXKLFG#XQ]IRKMC67<]9%BS[G@/FGM[V_IKVCEW8<R.R[MGZOIWJOG@"[PSUCWGHBXf;o0Y=!F_WKL+BCIWZSEORGA[40^*V_IKVCESNKCL.W\W\HDWO8n7X> I^TJK*ABFVYRBNQFNZ71Y+U^FJUBBRMJLM-V[V_IKVX896[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,evikVg~tRhPotv01>S7'@U]EB!HEO]P]KEXAGQ>>P \YOA\MKYDMEF$m~wac^ov|ZtXg|~9h6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,giidcln9h6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,bdjkagm8=6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,bdjkagmTcxz=d:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(nm;Tcxz=d:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(nm8Tcxz=d:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(nm9Tcxz=d:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(nm>Tcxz=d:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(nm?Tcxz=e:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(e|r:Sb{{2b9V4*OX^@E$KH@PSXL@[LH\=;W%_T@L_HL\G@JK'{cxeci<0:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(z`ybbjQ`uu1f?P6(AV\BC"IJN^QZJFYNFR?9Q#]VNB]JJZEBDE%xucmPf^ggc`)NWA8G"XQKOTV0=>S7'@U]EB!HEO]P]KEXAGQ>>P \YOA\MKYDMEF$t`l_g]f`bc(]VNDYY><9:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ({pdhSkQjdfg,QZBH]];8m6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,w|hdWoUnhjk iEMVP969;h1^<"GPVHM,C@HX[PDHSD@T53_-W\HDW@DTOHBC/r{mgZ`Xmmmn#dJ@UU>2:66<]9%BS[G@/FGM[V_IKVCEW8<R.R[MGZOIWJOG@"}vnb]e[jss;=1^<"GPVHM,C@HX[PDHSD@T53_-W\HDW@DTOHBC/r{mgZkrpVlTcxz<4:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ({pdhS`{w_s]lqq5b3\:$ERXFO.EFJZU^FJUBBV;=]/QZJFYNFVIN@A!|yoa\vZccol%BSA<G.T]GKPR412_;#DQYIN-DAKYTQGITECU:2\,P]KEXAGUHIAB sxl`[wYblno$YRJ@UU20=>S7'@U]EB!HEO]P]KEXAGQ>>P \YOA\MKYDMEF$t`l_s]f`bc(]VNDYY?<a:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ({pdhSQjdfg,mAIR\5:5?l5Z0.K\RLI(OLDT_T@L_HLX17[)[PDHSD@PCDNO+vikVxTiiij/hFLQQ:66::0Y=!F_WKL+BCIWZSEORGA[40^*V_IKVCESNKCL.qzjfYuWf>k5Z0.K\RLI(OLDT_T@L_HLX17[)[PDHSD@PCDNO+pubzVceSc=>;T2,MZPNG&MNBR]VNB]JJ^34U'YRBNQFN^AFHI)F[PDHSKQBUY12?P6(AV\BC"IJN^QZJFYNFR?8Q#]VNB]JJZEBDE%J_T@L_S]NQ]4a3\:$ERXFO.EFJZU^FJUBBV;<]/QZJFYNFVIN@A!\HHDW[WC@;91^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/R[MGZ@XE\R8<6[?/H]UMJ)@MGUXUCMPIOY67X(TQGITECQLEMN,W\HDW[UFYU=<;T2,MZPNG&MNBR]VNB]JJ^34U'YRBNQFN^AFHI)TWHYRBNQI_SGD76=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#^QNSXL@[WYUMN997X> I^TJK*ABFVYRBNQFNZ70Y+U^FJUBBRMJLM-P[V_IKVLT^HI<2:W3+LYQAF%LICQ\YOA\MK]2;T$XUCMPIO]@AIJ([VYRBNQ]_SGD77=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#X]JR^AOOZTBO;o0Y=!F_WKL+BCIWZSEORGA[41^*V_IKVCESNKCL.WPAWYJ]Q8n7X> I^TJK*ABFVYRBNQFNZ70Y+U^FJUBBRMJLM-VW@TXZLM9j6[?/H]UMJ)@MGUXUCMPIOY67X(TQGITECQLEMN,QZ@FDECEK?k4U1-J[SOH'NOES^WAC^KM_05Z&ZSEORGA_BGOH*SXZ@YBBJ=>;T2,MZPNG&MNBR]VNB]JJ^34U'YRBNQFN^AFHI)RWZ^JXNCK_o0f?P6(AV\BC"IJN^QZJFYNFR?8Q#]VNB]JJZEBDE%^S^WAC^D1a>S7'@U]EB!HEO]P]KEXAGQ>?P \YOA\MKYDMEF$YR]VNB]Q70=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#l}vnb]nq}YaWf?85Z0.K\RLI(OLDT_T@L_HLX16[)[PDHSD@PCDNO+du~fjUfyuQ}_nww6a=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#nb`cjgg6a=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#koclhld74=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#koclhld[jss:m1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/gf2[jss:m1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/gf1[jss:m1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/gf0[jss:m1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/gf7[jss:m1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/gf6[jss:l1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/lw{5Zir|;i0Y=!F_WKL+BCIWZSEORGA[41^*V_IKVCESNKCL.pjwlh`;91^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/skpmkaXg|~8i6[?/H]UMJ)@MGUXUCMPIOY67X(TQGITECQLEMN,w|hdWoUnhjk I^J1H+SXLF__?45Z0.K\RLI(OLDT_T@L_HLX16[)[PDHSD@PCDNO+vikVlTiiij/T]GKPR7;01^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/r{mgZ`Xmmmn#XQKOTV27d=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#~wac^d\aaab'`NDYY2?>2c8Q5)NW_CD#JKA_R[MGZOIS<9V"^WAC^KM[FCKD&yrbnQi_dfda*oCG\^7=3=?;T2,MZPNG&MNBR]VNB]JJ^34U'YRBNQFN^AFHI)tqgiTjRazt268Q5)NW_CD#JKA_R[MGZOIS<9V"^WAC^KM[FCKD&yrbnQbuy]e[jss;=1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/r{mgZkrpVxTcxz<e:W3+LYQAF%LICQ\YOA\MK]2;T$XUCMPIO]@AIJ({pdhSQjdfg,MZJ5@'_THB[[389V4*OX^@E$KH@PSXL@[LH\=:W%_T@L_HL\G@JK'zseoR|Peeef+PYCG\^;?45Z0.K\RLI(OLDT_T@L_HLX16[)[PDHSD@PCDNO+vikVxTiiij/T]GKPR6;h1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/r{mgZtXmmmn#dJ@UU>3:6g<]9%BS[G@/FGM[V_IKVCEW8=R.R[MGZOIWJOG@"}vnb]q[`b`m&cOCXZ31?13?P6(AV\BC"IJN^QZJFYNFR?8Q#]VNB]JJZEBDE%xucmPr^mvp7`<]9%BS[G@/FGM[V_IKVCEW8=R.R[MGZOIWJOG@"{|es]jjZh492_;#DQYIN-DAKYTQGITECU:4\,P]KEXAGUHIAB AR[MGZ@XE\R8=6[?/H]UMJ)@MGUXUCMPIOY60X(TQGITECQLEMN,EV_IKVXTAXV=f:W3+LYQAF%LICQ\YOA\MK]2<T$XUCMPIO]@AIJ([ACMXR\JG228Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&YRBNQI_LW[75=R8&CTZDA GDL\W\HDW@DP99S!SXL@[LHXKLFG#^WAC^P\IP^4;2_;#DQYIN-DAKYTQGITECU:4\,P]KEXAGUHIAB S^CP]KEXNVXNK>=4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*UXIZSEOR\PRDE06>S7'@U]EB!HEO]P]KEXAGQ>8P \YOA\MKYDMEF$_R]VNB]E[WC@;;1^<"GPVHM,C@HX[PDHSD@T55_-W\HDW@DTOHBC/R]P]KEXZVXNK><4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*STM[UH@FQ]EF0f?P6(AV\BC"IJN^QZJFYNFR??Q#]VNB]JJZEBDE%^_H\PMTZ1a>S7'@U]EB!HEO]P]KEXAGQ>8P \YOA\MKYDMEF$Y^K]_SGD6c=R8&CTZDA GDL\W\HDW@DP99S!SXL@[LHXKLFG#XQIAMNJJB4b3\:$ERXFO.EFJZU^FJUBBV;;]/QZJFYNFVIN@A!Z_SKPMKA492_;#DQYIN-DAKYTQGITECU:4\,P]KEXAGUHIAB U^QWEQEJLVd9i6[?/H]UMJ)@MGUXUCMPIOY60X(TQGITECQLEMN,QZU^FJUM>h5Z0.K\RLI(OLDT_T@L_HLX11[)[PDHSD@PCDNO+PYTQGIT^>;4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*gtqgiTaxvPf^mvp63<]9%BS[G@/FGM[V_IKVCEW8:R.R[MGZOIWJOG@"o|yoa\ip~XzVe~x?j4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*ekgjanh?j4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*`fdecek>?4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*`fdecekRazt3f8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&lo=Razt3f8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&lo>Razt3f8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&lo?Razt3f8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&lo8Razt3f8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&lo9Razt3g8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&g~t<Q`uu0`?P6(AV\BC"IJN^QZJFYNFR??Q#]VNB]JJZEBDE%ye~gag228Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&xbd`h_nww7`=R8&CTZDA GDL\W\HDW@DP99S!SXL@[LHXKLFG#~wac^d\aaab'@UC>A Z_EMVP6?<]9%BS[G@/FGM[V_IKVCEW8:R.R[MGZOIWJOG@"}vnb]e[`b`m&_THB[[02;8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&yrbnQi_dfda*SXLF__=>o4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*u~fjUmShjhe.kGKPR;879j7X> I^TJK*ABFVYRBNQFNZ77Y+U^FJUBBRMJLM-p}keXnVookh!fDNWW848482_;#DQYIN-DAKYTQGITECU:4\,P]KEXAGUHIAB sxl`[cYh}}9?7X> I^TJK*ABFVYRBNQFNZ77Y+U^FJUBBRMJLM-p}keXe|rTjRazt268Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&yrbnQbuy]q[jss;l1^<"GPVHM,C@HX[PDHSD@T55_-W\HDW@DTOHBC/r{mgZtXmmmn#DQC2I,V[AIR\:30Y=!F_WKL+BCIWZSEORGA[46^*V_IKVCESNKCL.qzjfYuWlnli"[PDNWW46?<]9%BS[G@/FGM[V_IKVCEW8:R.R[MGZOIWJOG@"}vnb]q[`b`m&_THB[[12c8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&yrbnQ}_dfda*oCG\^7<3=n;T2,MZPNG&MNBR]VNB]JJ^33U'YRBNQFN^AFHI)tqgiT~Rkkgd-j@JSS4848<6[?/H]UMJ)@MGUXUCMPIOY60X(TQGITECQLEMN,w|hdW{Udyy<i;T2,MZPNG&MNBR]VNB]JJ^33U'YRBNQFN^AFHI)r{lxTecQa309V4*OX^@E$KH@PSXL@[LH\=<W%_T@L_HL\G@JK'HYRBNQI_LW[74=R8&CTZDA GDL\W\HDW@DP98S!SXL@[LHXKLFG#L]VNB]Q[HS_:o1^<"GPVHM,C@HX[PDHSD@T54_-W\HDW@DTOHBC/RJJBQYUMN9;7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-P]KEXNVG^T>>4U1-J[SOH'NOES^WAC^KM_03Z&ZSEORGA_BGOH*U^FJUYS@[W329V4*OX^@E$KH@PSXL@[LH\=<W%_T@L_HL\G@JK'ZUJ_T@L_G]QAB543\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!\_@QZJFYUW[OL??5Z0.K\RLI(OLDT_T@L_HLX10[)[PDHSD@PCDNO+VYTQGITJR\JG208Q5)NW_CD#JKA_R[MGZOIS<?V"^WAC^KM[FCKD&YT_T@L_S]QAB553\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!ZSDP\GIMXZLM9i6[?/H]UMJ)@MGUXUCMPIOY61X(TQGITECQLEMN,QVCUWD_S>h5Z0.K\RLI(OLDT_T@L_HLX10[)[PDHSD@PCDNO+PUBZVXNK?h4U1-J[SOH'NOES^WAC^KM_03Z&ZSEORGA_BGOH*SXNHFGECI=e:W3+LYQAF%LICQ\YOA\MK]2=T$XUCMPIO]@AIJ(]VXB_D@H309V4*OX^@E$KH@PSXL@[LH\=<W%_T@L_HL\G@JK'\UXXLZLME]m6`=R8&CTZDA GDL\W\HDW@DP98S!SXL@[LHXKLFG#XQ\YOA\B7c<]9%BS[G@/FGM[V_IKVCEW8;R.R[MGZOIWJOG@"[PSXL@[W523\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!nsxl`[hsWoUdyy=:;T2,MZPNG&MNBR]VNB]JJ^32U'YRBNQFN^AFHI)f{pdhS`{w_s]lqq4c3\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!llnahaa4c3\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!iamnjjb563\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!iamnjjbYh}}8o7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-e`4Yh}}8o7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-e`7Yh}}8o7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-e`6Yh}}8o7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-e`1Yh}}8o7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-e`0Yh}}8n7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-nq}7Xg|~9o6[?/H]UMJ)@MGUXUCMPIOY61X(TQGITECQLEMN,vlunfn9;7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-qmvoioVe~x>k4U1-J[SOH'NOES^WAC^KM_03Z&ZSEORGA_BGOH*u~fjUmShjhe.K\L7J)]VNDYY=6;T2,MZPNG&MNBR]VNB]JJ^32U'YRBNQFN^AFHI)tqgiTjRkkgd-V[AIR\9927X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-p}keXnVookh!Z_EMVP45f3\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!|yoa\bZccol%bHB[[<1<0e>S7'@U]EB!HEO]P]KEXAGQ>9P \YOA\MKYDMEF$t`l_g]f`bc(aME^X1?1319V4*OX^@E$KH@PSXL@[LH\=<W%_T@L_HL\G@JK'zseoRhPotv00>S7'@U]EB!HEO]P]KEXAGQ>9P \YOA\MKYDMEF$t`l_lw{[cYh}}9?7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-p}keXe|rT~Razt2g8Q5)NW_CD#JKA_R[MGZOIS<?V"^WAC^KM[FCKD&yrbnQ}_dfda*OXD;B%YRJ@UU1:?P6(AV\BC"IJN^QZJFYNFR?>Q#]VNB]JJZEBDE%xucmPr^ggc`)RWME^X==6;T2,MZPNG&MNBR]VNB]JJ^32U'YRBNQFN^AFHI)tqgiT~Rkkgd-V[AIR\89j7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-p}keXzVookh!fDNWW8584i2_;#DQYIN-DAKYTQGITECU:5\,P]KEXAGUHIAB sxl`[wYblno$eIAZT=3=75=R8&CTZDA GDL\W\HDW@DP98S!SXL@[LHXKLFG#~wac^p\kpr5n2_;#DQYIN-DAKYTQGITECU:5\,P]KEXAGUHIAB urgq[lhXf:;0Y=!F_WKL+BCIWZSEORGA[44^*V_IKVCESNKCL.CP]KEXNVG^T>?4U1-J[SOH'NOES^WAC^KM_00Z&ZSEORGA_BGOH*GTQGIT^RCZX3d8Q5)NW_CD#JKA_R[MGZOIS<<V"^WAC^KM[FCKD&YCEKZPRDE04>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$_T@L_G]NQ]573\:$ERXFO.EFJZU^FJUBBV;9]/QZJFYNFVIN@A!\YOA\VZKRP:90Y=!F_WKL+BCIWZSEORGA[44^*V_IKVCESNKCL.Q\EV_IKVLT^HI<3:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ([VKXUCMPR^PFC64<]9%BS[G@/FGM[V_IKVCEW88R.R[MGZOIWJOG@"]PSXL@[CYUMN997X> I^TJK*ABFVYRBNQFNZ75Y+U^FJUBBRMJLM-P[V_IKVXT^HI<2:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ(]ZOYSNBD_SGD6`=R8&CTZDA GDL\W\HDW@DP9;S!SXL@[LHXKLFG#X]JR^OV\7c<]9%BS[G@/FGM[V_IKVCEW88R.R[MGZOIWJOG@"[\ES]QAB4a3\:$ERXFO.EFJZU^FJUBBV;9]/QZJFYNFVIN@A!Z_GCOHLH@:l1^<"GPVHM,C@HX[PDHSD@T57_-W\HDW@DTOHBC/T]QMVOIO:;0Y=!F_WKL+BCIWZSEORGA[44^*V_IKVCESNKCL.W\WQGSKDNTb?k4U1-J[SOH'NOES^WAC^KM_00Z&ZSEORGA_BGOH*SX[PDHSK<j;T2,MZPNG&MNBR]VNB]JJ^31U'YRBNQFN^AFHI)RWZSEOR\<5:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ(izseoRczx^d\kpr4=2_;#DQYIN-DAKYTQGITECU:6\,P]KEXAGUHIAB ar{mgZkrpVxTcxz=d:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ(keehghj=d:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ(nhfgeci<1:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ(nhfgeciPotv1`>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$ji?Potv1`>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$ji<Potv1`>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$ji=Potv1`>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$ji:Potv1`>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$ji;Potv1a>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$axv>_nww6f=R8&CTZDA GDL\W\HDW@DP9;S!SXL@[LHXKLFG#g|ioe04>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$~d}fnf]lqq5b3\:$ERXFO.EFJZU^FJUBBV;9]/QZJFYNFVIN@A!|yoa\bZccol%BSE<C.T]GKPR412_;#DQYIN-DAKYTQGITECU:6\,P]KEXAGUHIAB sxl`[cYblno$YRJ@UU20=>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$t`l_g]f`bc(]VNDYY?<a:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ({pdhSkQjdfg,mAIR\5:5?l5Z0.K\RLI(OLDT_T@L_HLX13[)[PDHSD@PCDNO+vikVlTiiij/hFLQQ:66::0Y=!F_WKL+BCIWZSEORGA[44^*V_IKVCESNKCL.qzjfYaWf?95Z0.K\RLI(OLDT_T@L_HLX13[)[PDHSD@PCDNO+vikVg~tRhPotv00>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$t`l_lw{[wYh}}9n7X> I^TJK*ABFVYRBNQFNZ75Y+U^FJUBBRMJLM-p}keXzVookh!F_M0K*PYCG\^856[?/H]UMJ)@MGUXUCMPIOY62X(TQGITECQLEMN,w|hdW{Unhjk U^FLQQ6412_;#DQYIN-DAKYTQGITECU:6\,P]KEXAGUHIAB sxl`[wYblno$YRJ@UU30e>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$t`l_s]f`bc(aME^X1>13`9V4*OX^@E$KH@PSXL@[LH\=?W%_T@L_HL\G@JK'zseoR|Peeef+lBH]]6:2>>4U1-J[SOH'NOES^WAC^KM_00Z&ZSEORGA_BGOH*u~fjUySb{{2g9V4*OX^@E$KH@PSXL@[LH\=?W%_T@L_HL\G@JK'|yn~Rga_o12?P6(AV\BC"IJN^QZJFYNFR?<Q#]VNB]JJZEBDE%J_T@L_G]NQ]563\:$ERXFO.EFJZU^FJUBBV;8]/QZJFYNFVIN@A!NSXL@[WYJ]Q8m7X> I^TJK*ABFVYRBNQFNZ74Y+U^FJUBBRMJLM-PLL@SW[OL?=5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+V_IKVLTAXV<0:W3+LYQAF%LICQ\YOA\MK]2?T$XUCMPIO]@AIJ([PDHS_QBUY10?P6(AV\BC"IJN^QZJFYNFR?<Q#]VNB]JJZEBDE%XSL]VNB]E[WC@;:1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/R]BW\HDW[UYIJ==;T2,MZPNG&MNBR]VNB]JJ^30U'YRBNQFN^AFHI)TWZSEORHPRDE06>S7'@U]EB!HEO]P]KEXAGQ>;P \YOA\MKYDMEF$_R]VNB]Q[WC@;;1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/TQFVZEKCVXNK?k4U1-J[SOH'NOES^WAC^KM_01Z&ZSEORGA_BGOH*STM[UFYU<j;T2,MZPNG&MNBR]VNB]JJ^30U'YRBNQFN^AFHI)R[LXT^HI=f:W3+LYQAF%LICQ\YOA\MK]2?T$XUCMPIO]@AIJ(]VLJ@AGAG3g8Q5)NW_CD#JKA_R[MGZOIS<=V"^WAC^KM[FCKD&_T^D]FNF12?P6(AV\BC"IJN^QZJFYNFR?<Q#]VNB]JJZEBDE%^S^ZNTBOG[k4b3\:$ERXFO.EFJZU^FJUBBV;8]/QZJFYNFVIN@A!Z_R[MGZ@5m2_;#DQYIN-DAKYTQGITECU:7\,P]KEXAGUHIAB U^QZJFYU;<1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/`qzjfYj}qUmSb{{349V4*OX^@E$KH@PSXL@[LH\=>W%_T@L_HL\G@JK'hyrbnQbuy]q[jss:m1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/bnlgncc:m1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/gcohlh`;81^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/gcohlh`Wf>i5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+cb6Wf>i5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+cb5Wf>i5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+cb4Wf>i5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+cb3Wf>i5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+cb2Wf>h5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+hs9Ve~x?m4U1-J[SOH'NOES^WAC^KM_01Z&ZSEORGA_BGOH*tn{`dl?=5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+wotagmTcxz<e:W3+LYQAF%LICQ\YOA\MK]2?T$XUCMPIO]@AIJ({pdhSkQjdfg,MZN5D'_THB[[389V4*OX^@E$KH@PSXL@[LH\=>W%_T@L_HL\G@JK'zseoRhPeeef+PYCG\^;?45Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+vikVlTiiij/T]GKPR6;h1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/r{mgZ`Xmmmn#dJ@UU>3:6g<]9%BS[G@/FGM[V_IKVCEW89R.R[MGZOIWJOG@"}vnb]e[`b`m&cOCXZ31?13?P6(AV\BC"IJN^QZJFYNFR?<Q#]VNB]JJZEBDE%xucmPf^mvp62<]9%BS[G@/FGM[V_IKVCEW89R.R[MGZOIWJOG@"}vnb]nq}YaWf?95Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+vikVg~tR|Potv0a>S7'@U]EB!HEO]P]KEXAGQ>;P \YOA\MKYDMEF$t`l_s]f`bc(AVF9D#[PDNWW7<=R8&CTZDA GDL\W\HDW@DP9:S!SXL@[LHXKLFG#~wac^p\aaab'\UOCXZ?389V4*OX^@E$KH@PSXL@[LH\=>W%_T@L_HL\G@JK'zseoR|Peeef+PYCG\^:?l5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+vikVxTiiij/hFLQQ:76:k0Y=!F_WKL+BCIWZSEORGA[45^*V_IKVCESNKCL.qzjfYuWlnli"gKOTV?5;573\:$ERXFO.EFJZU^FJUBBV;8]/QZJFYNFVIN@A!|yoa\vZir|;l0Y=!F_WKL+BCIWZSEORGA[45^*V_IKVCESNKCL.wpawYnfVd8=6[?/H]UMJ)@MGUXUCMPIOY6<X(TQGITECQLEMN,EV_IKVLTAXV<1:W3+LYQAF%LICQ\YOA\MK]20T$XUCMPIO]@AIJ(IZSEOR\PMTZ1b>S7'@U]EB!HEO]P]KEXAGQ>4P \YOA\MKYDMEF$_EGIT^PFC66<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"]VNB]E[HS_;91^<"GPVHM,C@HX[PDHSD@T59_-W\HDW@DTOHBC/R[MGZTXE\R8?6[?/H]UMJ)@MGUXUCMPIOY6<X(TQGITECQLEMN,WZGTQGITJR\JG218Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&YTM^WAC^P\V@A4:2_;#DQYIN-DAKYTQGITECU:8\,P]KEXAGUHIAB S^QZJFYAW[OL??5Z0.K\RLI(OLDT_T@L_HLX1=[)[PDHSD@PCDNO+VYTQGIT^R\JG208Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&_XI_QLLJ]QAB4b3\:$ERXFO.EFJZU^FJUBBV;7]/QZJFYNFVIN@A!ZSDP\IP^5m2_;#DQYIN-DAKYTQGITECU:8\,P]KEXAGUHIAB URGQ[WC@:o1^<"GPVHM,C@HX[PDHSD@T59_-W\HDW@DTOHBC/T]EEIJNFN8n7X> I^TJK*ABFVYRBNQFNZ7;Y+U^FJUBBRMJLM-V[WOTAGM8=6[?/H]UMJ)@MGUXUCMPIOY6<X(TQGITECQLEMN,QZUSI]IFHR`=e:W3+LYQAF%LICQ\YOA\MK]20T$XUCMPIO]@AIJ(]VYRBNQI2d9V4*OX^@E$KH@PSXL@[LH\=1W%_T@L_HL\G@JK'\UXUCMPR278Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&kxucmPmtz\bZir|:?0Y=!F_WKL+BCIWZSEORGA[4:^*V_IKVCESNKCL.cp}keXe|rT~Razt3f8Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&igcnejd3f8Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&lj`agag238Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&lj`agag^mvp7b<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"hk1^mvp7b<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"hk2^mvp7b<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"hk3^mvp7b<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"hk4^mvp7b<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"hk5^mvp7c<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"czx0]lqq4d3\:$ERXFO.EFJZU^FJUBBV;7]/QZJFYNFVIN@A!}irkmc66<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"|fshld[jss;l1^<"GPVHM,C@HX[PDHSD@T59_-W\HDW@DTOHBC/r{mgZ`Xmmmn#DQG2M,V[AIR\:30Y=!F_WKL+BCIWZSEORGA[4:^*V_IKVCESNKCL.qzjfYaWlnli"[PDNWW46?<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"}vnb]e[`b`m&_THB[[12c8Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&yrbnQi_dfda*oCG\^7<3=n;T2,MZPNG&MNBR]VNB]JJ^3?U'YRBNQFN^AFHI)tqgiTjRkkgd-j@JSS4848<6[?/H]UMJ)@MGUXUCMPIOY6<X(TQGITECQLEMN,w|hdWoUdyy=;;T2,MZPNG&MNBR]VNB]JJ^3?U'YRBNQFN^AFHI)tqgiTaxvPf^mvp62<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"}vnb]nq}YuWf?h5Z0.K\RLI(OLDT_T@L_HLX1=[)[PDHSD@PCDNO+vikVxTiiij/H]O6M(RWME^X>74U1-J[SOH'NOES^WAC^KM_0>Z&ZSEORGA_BGOH*u~fjUyShjhe.W\@JSS8:30Y=!F_WKL+BCIWZSEORGA[4:^*V_IKVCESNKCL.qzjfYuWlnli"[PDNWW56g<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"}vnb]q[`b`m&cOCXZ30?1b?P6(AV\BC"IJN^QZJFYNFR?3Q#]VNB]JJZEBDE%xucmPr^ggc`)nLF__0<0<0:W3+LYQAF%LICQ\YOA\MK]20T$XUCMPIO]@AIJ({pdhSQ`uu0e?P6(AV\BC"IJN^QZJFYNFR?3Q#]VNB]JJZEBDE%~h|Pio]m74=R8&CTZDA GDL\W\HDW@DP94S!SXL@[LHXKLFG#L]VNB]E[HS_;81^<"GPVHM,C@HX[PDHSD@T58_-W\HDW@DTOHBC/@QZJFYUWD_S>k5Z0.K\RLI(OLDT_T@L_HLX1<[)[PDHSD@PCDNO+VNNN]UYIJ=?;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)TQGITJRCZX228Q5)NW_CD#JKA_R[MGZOIS<3V"^WAC^KM[FCKD&YRBNQ]_LW[76=R8&CTZDA GDL\W\HDW@DP94S!SXL@[LHXKLFG#^QNSXL@[CYUMN987X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-P[DU^FJUYS_KH339V4*OX^@E$KH@PSXL@[LH\=0W%_T@L_HL\G@JK'ZUXUCMPF^PFC64<]9%BS[G@/FGM[V_IKVCEW87R.R[MGZOIWJOG@"]PSXL@[WYUMN997X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-VW@TXKEAT^HI=e:W3+LYQAF%LICQ\YOA\MK]21T$XUCMPIO]@AIJ(]ZOYS@[W2d9V4*OX^@E$KH@PSXL@[LH\=0W%_T@L_HL\G@JK'\YN^R\JG3d8Q5)NW_CD#JKA_R[MGZOIS<3V"^WAC^KM[FCKD&_TJLBCIOE1a>S7'@U]EB!HEO]P]KEXAGQ>5P \YOA\MKYDMEF$YR\FSHLD74=R8&CTZDA GDL\W\HDW@DP94S!SXL@[LHXKLFG#XQ\T@V@IAYi:l1^<"GPVHM,C@HX[PDHSD@T58_-W\HDW@DTOHBC/T]P]KEXN;o0Y=!F_WKL+BCIWZSEORGA[4;^*V_IKVCESNKCL.W\W\HDW[9>7X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-bw|hdWdsSkQ`uu16?P6(AV\BC"IJN^QZJFYNFR?2Q#]VNB]JJZEBDE%jt`l_lw{[wYh}}8o7X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-`hjelmm8o7X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-eeijnfn9:7X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-eeijnfnUdyy<k;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)al8Udyy<k;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)al;Udyy<k;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)al:Udyy<k;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)al=Udyy<k;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)al<Udyy<j;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)j}q;Tcxz=c:W3+LYQAF%LICQ\YOA\MK]21T$XUCMPIO]@AIJ(z`ybbj=?;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)uazcekRazt2g8Q5)NW_CD#JKA_R[MGZOIS<3V"^WAC^KM[FCKD&yrbnQi_dfda*OX@;F%YRJ@UU1:?P6(AV\BC"IJN^QZJFYNFR?2Q#]VNB]JJZEBDE%xucmPf^ggc`)RWME^X==6;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)tqgiTjRkkgd-V[AIR\89j7X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-p}keXnVookh!fDNWW8584i2_;#DQYIN-DAKYTQGITECU:9\,P]KEXAGUHIAB sxl`[cYblno$eIAZT=3=75=R8&CTZDA GDL\W\HDW@DP94S!SXL@[LHXKLFG#~wac^d\kpr4<2_;#DQYIN-DAKYTQGITECU:9\,P]KEXAGUHIAB sxl`[hsWoUdyy=;;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)tqgiTaxvPr^mvp6c<]9%BS[G@/FGM[V_IKVCEW87R.R[MGZOIWJOG@"}vnb]q[`b`m&CT@?F!U^FLQQ5>3\:$ERXFO.EFJZU^FJUBBV;6]/QZJFYNFVIN@A!|yoa\vZccol%^SIAZT11:?P6(AV\BC"IJN^QZJFYNFR?2Q#]VNB]JJZEBDE%xucmPr^ggc`)RWME^X<=n;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)tqgiT~Rkkgd-j@JSS4948m6[?/H]UMJ)@MGUXUCMPIOY6=X(TQGITECQLEMN,w|hdW{Unhjk iEMVP979;91^<"GPVHM,C@HX[PDHSD@T58_-W\HDW@DTOHBC/r{mgZtXg|~9j6[?/H]UMJ)@MGUXUCMPIOY6=X(TQGITECQLEMN,qvcuW`dTb>?4U1-J[SOH'NOES^WAC^KM_36Z&ZSEORGA_BGOH*GTQGITJRCZX238Q5)NW_CD#JKA_R[MGZOIS?:V"^WAC^KM[FCKD&KXUCMPR^OV\7`<]9%BS[G@/FGM[V_IKVCEW;>R.R[MGZOIWJOG@"]GIGV\V@A482_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB SXL@[CYJ]Q9;7X> I^TJK*ABFVYRBNQFNZ43Y+U^FJUBBRMJLM-P]KEXZVG^T>=4U1-J[SOH'NOES^WAC^KM_36Z&ZSEORGA_BGOH*UXIZSEORHPRDE07>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$_RO\YOA\VZTBO:80Y=!F_WKL+BCIWZSEORGA[72^*V_IKVCESNKCL.Q\W\HDWOUYIJ==;T2,MZPNG&MNBR]VNB]JJ^07U'YRBNQFN^AFHI)TWZSEOR\PRDE06>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$Y^K]_BNH[WC@:l1^<"GPVHM,C@HX[PDHSD@T61_-W\HDW@DTOHBC/TQFVZKRP;o0Y=!F_WKL+BCIWZSEORGA[72^*V_IKVCESNKCL.WPAWYUMN8m7X> I^TJK*ABFVYRBNQFNZ43Y+U^FJUBBRMJLM-V[CGKD@DL>h5Z0.K\RLI(OLDT_T@L_HLX25[)[PDHSD@PCDNO+PYUAZCEK>?4U1-J[SOH'NOES^WAC^KM_36Z&ZSEORGA_BGOH*SX[]K_O@JPn3g8Q5)NW_CD#JKA_R[MGZOIS?:V"^WAC^KM[FCKD&_T_T@L_G0f?P6(AV\BC"IJN^QZJFYNFR<;Q#]VNB]JJZEBDE%^S^WAC^P01>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$m~wac^ov|Z`Xg|~896[?/H]UMJ)@MGUXUCMPIOY54X(TQGITECQLEMN,evikVg~tR|Potv1`>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$oaalkdf1`>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$jlbcioe05>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$jlbcioe\kpr5l2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB fe3\kpr5l2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB fe0\kpr5l2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB fe1\kpr5l2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB fe6\kpr5l2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB fe7\kpr5m2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB mtz2[jss:j1^<"GPVHM,C@HX[PDHSD@T61_-W\HDW@DTOHBC/skpmka482_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB rhqjjbYh}}9n7X> I^TJK*ABFVYRBNQFNZ43Y+U^FJUBBRMJLM-p}keXnVookh!F_I0O*PYCG\^856[?/H]UMJ)@MGUXUCMPIOY54X(TQGITECQLEMN,w|hdWoUnhjk U^FLQQ6412_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB sxl`[cYblno$YRJ@UU30e>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$t`l_g]f`bc(aME^X1>13`9V4*OX^@E$KH@PSXL@[LH\>9W%_T@L_HL\G@JK'zseoRhPeeef+lBH]]6:2>>4U1-J[SOH'NOES^WAC^KM_36Z&ZSEORGA_BGOH*u~fjUmSb{{359V4*OX^@E$KH@PSXL@[LH\>9W%_T@L_HL\G@JK'zseoRczx^d\kpr4<2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB sxl`[hsW{Udyy=j;T2,MZPNG&MNBR]VNB]JJ^07U'YRBNQFN^AFHI)tqgiT~Rkkgd-J[I4O&\UOCXZ<9:W3+LYQAF%LICQ\YOA\MK]18T$XUCMPIO]@AIJ({pdhSQjdfg,QZBH]]:856[?/H]UMJ)@MGUXUCMPIOY54X(TQGITECQLEMN,w|hdW{Unhjk U^FLQQ74i2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB sxl`[wYblno$eIAZT=2=7d=R8&CTZDA GDL\W\HDW@DP:=S!SXL@[LHXKLFG#~wac^p\aaab'`NDYY2>>228Q5)NW_CD#JKA_R[MGZOIS?:V"^WAC^KM[FCKD&yrbnQ}_nww6c=R8&CTZDA GDL\W\HDW@DP:=S!SXL@[LHXKLFG#x}jr^km[k563\:$ERXFO.EFJZU^FJUBBV8>]/QZJFYNFVIN@A!NSXL@[CYJ]Q9:7X> I^TJK*ABFVYRBNQFNZ42Y+U^FJUBBRMJLM-BW\HDW[UFYU<i;T2,MZPNG&MNBR]VNB]JJ^06U'YRBNQFN^AFHI)T@@L_S_KH319V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'ZSEORHPMTZ04>S7'@U]EB!HEO]P]KEXAGQ==P \YOA\MKYDMEF$_T@L_S]NQ]543\:$ERXFO.EFJZU^FJUBBV8>]/QZJFYNFVIN@A!\_@QZJFYAW[OL?>5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+VYF[PDHS_Q]EF11?P6(AV\BC"IJN^QZJFYNFR<:Q#]VNB]JJZEBDE%XS^WAC^D\V@A4:2_;#DQYIN-DAKYTQGITECU91\,P]KEXAGUHIAB S^QZJFYUW[OL??5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+PUBZVIGGR\JG3g8Q5)NW_CD#JKA_R[MGZOIS?;V"^WAC^KM[FCKD&_XI_QBUY0f?P6(AV\BC"IJN^QZJFYNFR<:Q#]VNB]JJZEBDE%^_H\PRDE1b>S7'@U]EB!HEO]P]KEXAGQ==P \YOA\MKYDMEF$YRHNLMKMC7c<]9%BS[G@/FGM[V_IKVCEW;?R.R[MGZOIWJOG@"[PRHQJJB563\:$ERXFO.EFJZU^FJUBBV8>]/QZJFYNFVIN@A!Z_RVBPFKCWg8n7X> I^TJK*ABFVYRBNQFNZ42Y+U^FJUBBRMJLM-V[V_IKVL9i6[?/H]UMJ)@MGUXUCMPIOY55X(TQGITECQLEMN,QZU^FJUY?85Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+du~fjUfyuQi_nww70=R8&CTZDA GDL\W\HDW@DP:<S!SXL@[LHXKLFG#l}vnb]nq}YuWf>i5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+fjhkboo>i5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+cgkd`dl?<5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+cgkd`dlSb{{2e9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'on:Sb{{2e9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'on9Sb{{2e9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'on8Sb{{2e9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'on?Sb{{2e9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'on>Sb{{2d9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'ds=Razt3a8Q5)NW_CD#JKA_R[MGZOIS?;V"^WAC^KM[FCKD&xbd`h319V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'{cxeciPotv0a>S7'@U]EB!HEO]P]KEXAGQ==P \YOA\MKYDMEF$t`l_g]f`bc(AVB9@#[PDNWW7<=R8&CTZDA GDL\W\HDW@DP:<S!SXL@[LHXKLFG#~wac^d\aaab'\UOCXZ?389V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'zseoRhPeeef+PYCG\^:?l5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+vikVlTiiij/hFLQQ:76:k0Y=!F_WKL+BCIWZSEORGA[73^*V_IKVCESNKCL.qzjfYaWlnli"gKOTV?5;573\:$ERXFO.EFJZU^FJUBBV8>]/QZJFYNFVIN@A!|yoa\bZir|:>0Y=!F_WKL+BCIWZSEORGA[73^*V_IKVCESNKCL.qzjfYj}qUmSb{{359V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'zseoRczx^p\kpr4m2_;#DQYIN-DAKYTQGITECU91\,P]KEXAGUHIAB sxl`[wYblno$ERB=H/W\@JSS;01^<"GPVHM,C@HX[PDHSD@T60_-W\HDW@DTOHBC/r{mgZtXmmmn#XQKOTV37<=R8&CTZDA GDL\W\HDW@DP:<S!SXL@[LHXKLFG#~wac^p\aaab'\UOCXZ>3`9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'zseoR|Peeef+lBH]]6;2>o4U1-J[SOH'NOES^WAC^KM_37Z&ZSEORGA_BGOH*u~fjUyShjhe.kGKPR;979;7X> I^TJK*ABFVYRBNQFNZ42Y+U^FJUBBRMJLM-p}keXzVe~x?h4U1-J[SOH'NOES^WAC^KM_37Z&ZSEORGA_BGOH*stm{UbbR`<1:W3+LYQAF%LICQ\YOA\MK]1:T$XUCMPIO]@AIJ(IZSEORHPMTZ05>S7'@U]EB!HEO]P]KEXAGQ=>P \YOA\MKYDMEF$M^WAC^P\IP^5n2_;#DQYIN-DAKYTQGITECU92\,P]KEXAGUHIAB SIKEPZTBO::0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.QZJFYAWD_S?=5Z0.K\RLI(OLDT_T@L_HLX27[)[PDHSD@PCDNO+V_IKVXTAXV<3:W3+LYQAF%LICQ\YOA\MK]1:T$XUCMPIO]@AIJ([VKXUCMPF^PFC65<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"]PAR[MGZTXZLM8>6[?/H]UMJ)@MGUXUCMPIOY56X(TQGITECQLEMN,WZU^FJUMS_KH339V4*OX^@E$KH@PSXL@[LH\>;W%_T@L_HL\G@JK'ZUXUCMPR^PFC64<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"[\ES]@HNYUMN8n7X> I^TJK*ABFVYRBNQFNZ41Y+U^FJUBBRMJLM-VW@TXE\R9i6[?/H]UMJ)@MGUXUCMPIOY56X(TQGITECQLEMN,QVCUW[OL>k5Z0.K\RLI(OLDT_T@L_HLX27[)[PDHSD@PCDNO+PYAIEFBBJ<j;T2,MZPNG&MNBR]VNB]JJ^05U'YRBNQFN^AFHI)RW[CXECI<1:W3+LYQAF%LICQ\YOA\MK]1:T$XUCMPIO]@AIJ(]VY_MYMBD^l1a>S7'@U]EB!HEO]P]KEXAGQ=>P \YOA\MKYDMEF$YR]VNB]E6`=R8&CTZDA GDL\W\HDW@DP:?S!SXL@[LHXKLFG#XQ\YOA\V63<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"o|yoa\ip~XnVe~x>;4U1-J[SOH'NOES^WAC^KM_34Z&ZSEORGA_BGOH*gtqgiTaxvPr^mvp7b<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"mcobif`7b<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"hnlmkmc67<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"hnlmkmcZir|;n0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.dg5Zir|;n0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.dg6Zir|;n0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.dg7Zir|;n0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.dg0Zir|;n0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.dg1Zir|;o0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.ov|4Yh}}8h7X> I^TJK*ABFVYRBNQFNZ41Y+U^FJUBBRMJLM-qmvoio::0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.pjwlh`Wf?h5Z0.K\RLI(OLDT_T@L_HLX27[)[PDHSD@PCDNO+vikVlTiiij/H]K6I(RWME^X>74U1-J[SOH'NOES^WAC^KM_34Z&ZSEORGA_BGOH*u~fjUmShjhe.W\@JSS8:30Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.qzjfYaWlnli"[PDNWW56g<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"}vnb]e[`b`m&cOCXZ30?1b?P6(AV\BC"IJN^QZJFYNFR<9Q#]VNB]JJZEBDE%xucmPf^ggc`)nLF__0<0<0:W3+LYQAF%LICQ\YOA\MK]1:T$XUCMPIO]@AIJ({pdhSkQ`uu17?P6(AV\BC"IJN^QZJFYNFR<9Q#]VNB]JJZEBDE%xucmPmtz\bZir|:>0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.qzjfYj}qUySb{{3d9V4*OX^@E$KH@PSXL@[LH\>;W%_T@L_HL\G@JK'zseoR|Peeef+LYK:A$^SIAZT2;8Q5)NW_CD#JKA_R[MGZOIS?8V"^WAC^KM[FCKD&yrbnQ}_dfda*SXLF__<>74U1-J[SOH'NOES^WAC^KM_34Z&ZSEORGA_BGOH*u~fjUyShjhe.W\@JSS9:k0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.qzjfYuWlnli"gKOTV?4;5f3\:$ERXFO.EFJZU^FJUBBV8=]/QZJFYNFVIN@A!|yoa\vZccol%bHB[[<0<04>S7'@U]EB!HEO]P]KEXAGQ=>P \YOA\MKYDMEF$t`l_s]lqq4a3\:$ERXFO.EFJZU^FJUBBV8=]/QZJFYNFVIN@A!zsdp\mkYi;81^<"GPVHM,C@HX[PDHSD@T62_-W\HDW@DTOHBC/@QZJFYAWD_S?<5Z0.K\RLI(OLDT_T@L_HLX26[)[PDHSD@PCDNO+DU^FJUYS@[W2g9V4*OX^@E$KH@PSXL@[LH\>:W%_T@L_HL\G@JK'ZBBJYQ]EF13?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%XUCMPF^OV\66<]9%BS[G@/FGM[V_IKVCEW;=R.R[MGZOIWJOG@"]VNB]Q[HS_;:1^<"GPVHM,C@HX[PDHSD@T62_-W\HDW@DTOHBC/R]BW\HDWOUYIJ=<;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)TWHYRBNQ]_SGD77=R8&CTZDA GDL\W\HDW@DP:>S!SXL@[LHXKLFG#^Q\YOA\BZTBO:80Y=!F_WKL+BCIWZSEORGA[71^*V_IKVCESNKCL.Q\W\HDW[UYIJ==;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)R[LXTOAEPRDE1a>S7'@U]EB!HEO]P]KEXAGQ=?P \YOA\MKYDMEF$Y^K]_LW[6`=R8&CTZDA GDL\W\HDW@DP:>S!SXL@[LHXKLFG#X]JR^PFC7`<]9%BS[G@/FGM[V_IKVCEW;=R.R[MGZOIWJOG@"[PF@NOMKA5m2_;#DQYIN-DAKYTQGITECU93\,P]KEXAGUHIAB U^PJWLH@;81^<"GPVHM,C@HX[PDHSD@T62_-W\HDW@DTOHBC/T]PPDRDEMUe>h5Z0.K\RLI(OLDT_T@L_HLX26[)[PDHSD@PCDNO+PYTQGITJ?k4U1-J[SOH'NOES^WAC^KM_35Z&ZSEORGA_BGOH*SX[PDHS_=:;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)f{pdhS`{w_g]lqq523\:$ERXFO.EFJZU^FJUBBV8<]/QZJFYNFVIN@A!nsxl`[hsW{Udyy<k;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)ddfi`ii<k;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)aiefbbj=>;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)aiefbbjQ`uu0g?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%mh<Q`uu0g?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%mh?Q`uu0g?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%mh>Q`uu0g?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%mh9Q`uu0g?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%mh8Q`uu0f?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%fyu?Potv1g>S7'@U]EB!HEO]P]KEXAGQ=?P \YOA\MKYDMEF$~d}fnf13?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%ye~gag^mvp6c<]9%BS[G@/FGM[V_IKVCEW;=R.R[MGZOIWJOG@"}vnb]e[`b`m&CTD?B!U^FLQQ5>3\:$ERXFO.EFJZU^FJUBBV8<]/QZJFYNFVIN@A!|yoa\bZccol%^SIAZT11:?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%xucmPf^ggc`)RWME^X<=n;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)tqgiTjRkkgd-j@JSS4948m6[?/H]UMJ)@MGUXUCMPIOY57X(TQGITECQLEMN,w|hdWoUnhjk iEMVP979;91^<"GPVHM,C@HX[PDHSD@T62_-W\HDW@DTOHBC/r{mgZ`Xg|~886[?/H]UMJ)@MGUXUCMPIOY57X(TQGITECQLEMN,w|hdWdsSkQ`uu17?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%xucmPmtz\vZir|:o0Y=!F_WKL+BCIWZSEORGA[71^*V_IKVCESNKCL.qzjfYuWlnli"GPL3J-QZBH]]927X> I^TJK*ABFVYRBNQFNZ40Y+U^FJUBBRMJLM-p}keXzVookh!Z_EMVP55>3\:$ERXFO.EFJZU^FJUBBV8<]/QZJFYNFVIN@A!|yoa\vZccol%^SIAZT01b?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%xucmPr^ggc`)nLF__0=0<a:W3+LYQAF%LICQ\YOA\MK]1;T$XUCMPIO]@AIJ({pdhSQjdfg,mAIR\5;5?=5Z0.K\RLI(OLDT_T@L_HLX26[)[PDHSD@PCDNO+vikVxTcxz=f:W3+LYQAF%LICQ\YOA\MK]1;T$XUCMPIO]@AIJ(}zoySd`Pn248Q5)NW_CD#JKA_R[MGZIR\R99Q#]VNB]LQQYDMEF$ER]]L^V1*PYTZE8m7X> I^TJK*ABFVYRBNQ@UUY06X(TQGITCXZPCDNO+ISSWF__?;5Z0.K\RLI(OLDT_T@L_NWW_64Z&ZSEORAZT^AFHI)T@@L_SB[[_ugnt66<]9%BS[G@/FGM[V_IKVE^XV==]/QZJFYH]]UHIAB URGQ[WC@;91^<"GPVHM,C@HX[PDHSB[[[20^*V_IKVE^XRMJLM-lqqYsmdz8:6[?/H]UMJ)@MGUXUCMPOTVX76[)[PDHSB[[_BGOH*OX[[FTX? Z_RPO6c=R8&CTZDA GDL\W\HDWF__W>=R.R[MGZIR\VIN@A!CUU]LQQ513\:$ERXFO.EFJZU^FJUDYYU<3\,P]KEXG\^TOHBC/RJJBQYH]]Ui`~<0:W3+LYQAF%LICQ\YOA\KPR\;:W%_T@L_NWW[FCKD&_XI_Q]EF13?P6(AV\BC"IJN^QZJFYH]]Q8?P \YOA\KPRXKLFG#b{{_ugnt60<]9%BS[G@/FGM[V_IKVE^XV=;]/QZJFYH]]UHIAB I^QQHZR5&\UX^A<i;T2,MZPNG&MNBR]VNB]LQQ]4<T$XUCMPOTV\G@JK'E__SB[[379V4*OX^@E$KH@PSXL@[JSSS:>V"^WAC^MVPZEBDE%XDDH[_NWW[qcjx::0Y=!F_WKL+BCIWZSEORAZTZ17Y+U^FJUDYYQLEMN,QVCUW[OL?=5Z0.K\RLI(OLDT_T@L_NWW_62Z&ZSEORAZT^AFHI)h}}Ui`~<6:W3+LYQAF%LICQ\YOA\KPR\;<W%_T@L_NWW[FCKD&CT__BPT3,V[VTK:o1^<"GPVHM,C@HX[PDHSB[[[27^*V_IKVE^XRMJLM-OQQYH]]9=7X> I^TJK*ABFVYRBNQ@UUY01X(TQGITCXZPCDNO+VNNN]UDYYQ{elr04>S7'@U]EB!HEO]P]KEXG\^P?8S!SXL@[JSSWJOG@"[\ES]QAB573\:$ERXFO.EFJZU^FJUDYYU<5\,P]KEXG\^TOHBC/nww[qcjx:<0Y=!F_WKL+BCIWZSEORAZTZ15Y+U^FJUDYYQLEMN,MZUUDV^9"XQ\RM0e?P6(AV\BC"IJN^QZJFYH]]Q8:P \YOA\KPRXKLFG#A[[_NWW73=R8&CTZDA GDL\W\HDWF__W>8R.R[MGZIR\VIN@A!\HHDW[JSSW}of|>>4U1-J[SOH'NOES^WAC^MVP^51U'YRBNQ@UU]@AIJ(]ZOYS_KH319V4*OX^@E$KH@PSXL@[JSSS:<V"^WAC^MVPZEBDE%dyyQ{elr02>S7'@U]EB!HEO]P]KEXG\^P?:S!SXL@[JSSWJOG@"GPSSN\P7(RWZXG>k5Z0.K\RLI(OLDT_T@L_NWW_61Z&ZSEORAZT^AFHI)K]]UDYY=9;T2,MZPNG&MNBR]VNB]LQQ]4?T$XUCMPOTV\G@JK'ZBBJYQ@UU]wahv482_;#DQYIN-DAKYTQGITCXZT36_-W\HDWF__SNKCL.WPAWYUMN9;7X> I^TJK*ABFVYRBNQ@UUY03X(TQGITCXZPCDNO+jssW}of|>84U1-J[SOH'NOES^WAC^MVP^5?U'YRBNQ@UU]@AIJ(AVYY@RZ=.T]PVI4a3\:$ERXFO.EFJZU^FJUDYYU<8\,P]KEXG\^TOHBC/MWW[JSS;?1^<"GPVHM,C@HX[PDHSB[[[2:^*V_IKVE^XRMJLM-PLL@SWF__Sykbp228Q5)NW_CD#JKA_R[MGZIR\R93Q#]VNB]LQQYDMEF$Y^K]_SGD75=R8&CTZDA GDL\W\HDWF__W>6R.R[MGZIR\VIN@A!`uu]wahv4>2_;#DQYIN-DAKYTQGITCXZT38_-W\HDWF__SNKCL.K\WWJX\;$^S^\C2g9V4*OX^@E$KH@PSXL@[JSSS:3V"^WAC^MVPZEBDE%GYYQ@UU15?P6(AV\BC"IJN^QZJFYH]]Q85P \YOA\KPRXKLFG#^FFFU]LQQYsmdz8<6[?/H]UMJ)@MGUXUCMPOTVX7<[)[PDHSB[[_BGOH*STM[UYIJ=?;T2,MZPNG&MNBR]VNB]LQQ]41T$XUCMPOTV\G@JK'fSykbp248Q5)NW_CD#JKA_R[MGZIR\R>;Q#]VNB]LQQYDMEF$ER]]L^V1*PYTZE8m7X> I^TJK*ABFVYRBNQ@UUY74X(TQGITCXZPCDNO+ISSWF__?;5Z0.K\RLI(OLDT_T@L_NWW_16Z&ZSEORAZT^AFHI)T@@L_SB[[_ugnt66<]9%BS[G@/FGM[V_IKVE^XV:?]/QZJFYH]]UHIAB URGQ[WC@;91^<"GPVHM,C@HX[PDHSB[[[52^*V_IKVE^XRMJLM-lqqYsmdz8:6[?/H]UMJ)@MGUXUCMPOTVX04[)[PDHSB[[_BGOH*OX[[FTX? Z_RPO6c=R8&CTZDA GDL\W\HDWF__W9?R.R[MGZIR\VIN@A!CUU]LQQ513\:$ERXFO.EFJZU^FJUDYYU;1\,P]KEXG\^TOHBC/RJJBQYH]]Ui`~<0:W3+LYQAF%LICQ\YOA\KPR\<8W%_T@L_NWW[FCKD&_XI_Q]EF13?P6(AV\BC"IJN^QZJFYH]]Q?=P \YOA\KPRXKLFG#b{{_ugnt60<]9%BS[G@/FGM[V_IKVE^XV:=]/QZJFYH]]UHIAB I^QQHZR5&\UX^A<i;T2,MZPNG&MNBR]VNB]LQQ]3:T$XUCMPOTV\G@JK'E__SB[[379V4*OX^@E$KH@PSXL@[JSSS=8V"^WAC^MVPZEBDE%XDDH[_NWW[qcjx::0Y=!F_WKL+BCIWZSEORAZTZ61Y+U^FJUDYYQLEMN,QVCUW[OL?=5Z0.K\RLI(OLDT_T@L_NWW_14Z&ZSEORAZT^AFHI)h}}Ui`~<6:W3+LYQAF%LICQ\YOA\KPR\<:W%_T@L_NWW[FCKD&CT__BPT3,V[VTK:o1^<"GPVHM,C@HX[PDHSB[[[51^*V_IKVE^XRMJLM-OQQYH]]9=7X> I^TJK*ABFVYRBNQ@UUY77X(TQGITCXZPCDNO+VNNN]UDYYQ{elr04>S7'@U]EB!HEO]P]KEXG\^P8>S!SXL@[JSSWJOG@"[\ES]QAB573\:$ERXFO.EFJZU^FJUDYYU;3\,P]KEXG\^TOHBC/nww[qcjx:<0Y=!F_WKL+BCIWZSEORAZTZ67Y+U^FJUDYYQLEMN,MZUUDV^9"XQ\RM0e?P6(AV\BC"IJN^QZJFYH]]Q?8P \YOA\KPRXKLFG#A[[_NWW73=R8&CTZDA GDL\W\HDWF__W9:R.R[MGZIR\VIN@A!\HHDW[JSSW}of|>>4U1-J[SOH'NOES^WAC^MVP^23U'YRBNQ@UU]@AIJ(]ZOYS_KH319V4*OX^@E$KH@PSXL@[JSSS=>V"^WAC^MVPZEBDE%dyyQ{elr02>S7'@U]EB!HEO]P]KEXG\^P88S!SXL@[JSSWJOG@"GPSSN\P7(RWZXG>k5Z0.K\RLI(OLDT_T@L_NWW_13Z&ZSEORAZT^AFHI)K]]UDYY=9;T2,MZPNG&MNBR]VNB]LQQ]3=T$XUCMPOTV\G@JK'ZBBJYQ@UU]wahv482_;#DQYIN-DAKYTQGITCXZT44_-W\HDWF__SNKCL.WPAWYUMN9;7X> I^TJK*ABFVYRBNQ@UUY71X(TQGITCXZPCDNO+jssW}of|>84U1-J[SOH'NOES^WAC^MVP^21U'YRBNQ@UU]@AIJ(AVYY@RZ=.T]PVI4a3\:$ERXFO.EFJZU^FJUDYYU;6\,P]KEXG\^TOHBC/MWW[JSS;?1^<"GPVHM,C@HX[PDHSB[[[54^*V_IKVE^XRMJLM-PLL@SWF__Sykbp228Q5)NW_CD#JKA_R[MGZIR\R>=Q#]VNB]LQQYDMEF$Y^K]_SGD75=R8&CTZDA GDL\W\HDWF__W98R.R[MGZIR\VIN@A!`uu]wahv4>2_;#DQYIN-DAKYTQGITCXZT46_-W\HDWF__SNKCL.K\WWJX\;$^S^\C2g9V4*OX^@E$KH@PSXL@[JSSS==V"^WAC^MVPZEBDE%GYYQ@UU15?P6(AV\BC"IJN^QZJFYH]]Q?;P \YOA\KPRXKLFG#^FFFU]LQQYsmdz8<6[?/H]UMJ)@MGUXUCMPOTVX02[)[PDHSB[[_BGOH*STM[UYIJ=?;T2,MZPNG&MNBR]VNB]LQQ]3?T$XUCMPOTV\G@JK'fSykbp248Q5)NW_CD#JKA_R[MGZIR\R>3Q#]VNB]LQQYDMEF$ER]]L^V1*PYTZE8m7X> I^TJK*ABFVYRBNQ@UUY7<X(TQGITCXZPCDNO+ISSWF__?;5Z0.K\RLI(OLDT_T@L_NWW_1>Z&ZSEORAZT^AFHI)T@@L_SB[[_ugnt66<]9%BS[G@/FGM[V_IKVE^XV:7]/QZJFYH]]UHIAB URGQ[WC@;91^<"GPVHM,C@HX[PDHSB[[[5:^*V_IKVE^XRMJLM-lqqYsmdz8:6[?/H]UMJ)@MGUXUCMPOTVX0<[)[PDHSB[[_BGOH*OX[[FTX? Z_RPO6c=R8&CTZDA GDL\W\HDWF__W97R.R[MGZIR\VIN@A!CUU]LQQ513\:$ERXFO.EFJZU^FJUDYYU;9\,P]KEXG\^TOHBC/RJJBQYH]]Ui`~<0:W3+LYQAF%LICQ\YOA\KPR\<0W%_T@L_NWW[FCKD&_XI_Q]EF13?P6(AV\BC"IJN^QZJFYH]]Q?5P \YOA\KPRXKLFG#b{{_ugnt60<]9%BS[G@/FGM[V_IKVE^XV;?]/QZJFYH]]UHIAB I^QQHZR5&\UX^A<i;T2,MZPNG&MNBR]VNB]LQQ]28T$XUCMPOTV\G@JK'E__SB[[379V4*OX^@E$KH@PSXL@[JSSS<:V"^WAC^MVPZEBDE%XDDH[_NWW[qcjx::0Y=!F_WKL+BCIWZSEORAZTZ73Y+U^FJUDYYQLEMN,QVCUW[OL?=5Z0.K\RLI(OLDT_T@L_NWW_06Z&ZSEORAZT^AFHI)h}}Ui`~<6:W3+LYQAF%LICQ\YOA\KPR\=8W%_T@L_NWW[FCKD&CT__BPT3,V[VTK:o1^<"GPVHM,C@HX[PDHSB[[[43^*V_IKVE^XRMJLM-OQQYH]]9=7X> I^TJK*ABFVYRBNQ@UUY65X(TQGITCXZPCDNO+VNNN]UDYYQ{elr04>S7'@U]EB!HEO]P]KEXG\^P9<S!SXL@[JSSWJOG@"[\ES]QAB573\:$ERXFO.EFJZU^FJUDYYU:1\,P]KEXG\^TOHBC/nww[qcjx:<0Y=!F_WKL+BCIWZSEORAZTZ71Y+U^FJUDYYQLEMN,MZUUDV^9"XQ\RM0e?P6(AV\BC"IJN^QZJFYH]]Q>>P \YOA\KPRXKLFG#A[[_NWW73=R8&CTZDA GDL\W\HDWF__W8<R.R[MGZIR\VIN@A!\HHDW[JSSW}of|>>4U1-J[SOH'NOES^WAC^MVP^35U'YRBNQ@UU]@AIJ(]ZOYS_KH319V4*OX^@E$KH@PSXL@[JSSS<8V"^WAC^MVPZEBDE%dyyQ{elr02>S7'@U]EB!HEO]P]KEXG\^P9>S!SXL@[JSSWJOG@"GPSSN\P7(RWZXG>k5Z0.K\RLI(OLDT_T@L_NWW_05Z&ZSEORAZT^AFHI)K]]UDYY=9;T2,MZPNG&MNBR]VNB]LQQ]2;T$XUCMPOTV\G@JK'ZBBJYQ@UU]wahv482_;#DQYIN-DAKYTQGITCXZT52_-W\HDWF__SNKCL.WPAWYUMN9;7X> I^TJK*ABFVYRBNQ@UUY67X(TQGITCXZPCDNO+jssW}of|>84U1-J[SOH'NOES^WAC^MVP^33U'YRBNQ@UU]@AIJ(AVYY@RZ=.T]PVI4a3\:$ERXFO.EFJZU^FJUDYYU:4\,P]KEXG\^TOHBC/MWW[JSS;?1^<"GPVHM,C@HX[PDHSB[[[46^*V_IKVE^XRMJLM-PLL@SWF__Sykbp228Q5)NW_CD#JKA_R[MGZIR\R??Q#]VNB]LQQYDMEF$Y^K]_SGD75=R8&CTZDA GDL\W\HDWF__W8:R.R[MGZIR\VIN@A!`uu]wahv4>2_;#DQYIN-DAKYTQGITCXZT54_-W\HDWF__SNKCL.K\WWJX\;$^S^\C2g9V4*OX^@E$KH@PSXL@[JSSS<?V"^WAC^MVPZEBDE%GYYQ@UU15?P6(AV\BC"IJN^QZJFYH]]Q>9P \YOA\KPRXKLFG#^FFFU]LQQYsmdz8<6[?/H]UMJ)@MGUXUCMPOTVX10[)[PDHSB[[_BGOH*STM[UYIJ=?;T2,MZPNG&MNBR]VNB]LQQ]2=T$XUCMPOTV\G@JK'fSykbp248Q5)NW_CD#JKA_R[MGZIR\R?=Q#]VNB]LQQYDMEF$ER]]L^V1*PYTZE8m7X> I^TJK*ABFVYRBNQ@UUY62X(TQGITCXZPCDNO+ISSWF__?;5Z0.K\RLI(OLDT_T@L_NWW_00Z&ZSEORAZT^AFHI)T@@L_SB[[_ugnt66<]9%BS[G@/FGM[V_IKVE^XV;9]/QZJFYH]]UHIAB URGQ[WC@;91^<"GPVHM,C@HX[PDHSB[[[44^*V_IKVE^XRMJLM-lqqYsmdz8:6[?/H]UMJ)@MGUXUCMPOTVX12[)[PDHSB[[_BGOH*OX[[FTX? Z_RPO6c=R8&CTZDA GDL\W\HDWF__W89R.R[MGZIR\VIN@A!CUU]LQQ513\:$ERXFO.EFJZU^FJUDYYU:7\,P]KEXG\^TOHBC/RJJBQYH]]Ui`~<0:W3+LYQAF%LICQ\YOA\KPR\=>W%_T@L_NWW[FCKD&_XI_Q]EF13?P6(AV\BC"IJN^QZJFYH]]Q>;P \YOA\KPRXKLFG#b{{_ugnt60<]9%BS[G@/FGM[V_IKVE^XV;7]/QZJFYH]]UHIAB I^QQHZR5&\UX^A<i;T2,MZPNG&MNBR]VNB]LQQ]20T$XUCMPOTV\G@JK'E__SB[[379V4*OX^@E$KH@PSXL@[JSSS<2V"^WAC^MVPZEBDE%XDDH[_NWW[qcjx::0Y=!F_WKL+BCIWZSEORAZTZ7;Y+U^FJUDYYQLEMN,QVCUW[OL?=5Z0.K\RLI(OLDT_T@L_NWW_0>Z&ZSEORAZT^AFHI)h}}Ui`~<6:W3+LYQAF%LICQ\YOA\KPR\=0W%_T@L_NWW[FCKD&CT__BPT3,V[VTK:o1^<"GPVHM,C@HX[PDHSB[[[4;^*V_IKVE^XRMJLM-OQQYH]]9=7X> I^TJK*ABFVYRBNQ@UUY6=X(TQGITCXZPCDNO+VNNN]UDYYQ{elr04>S7'@U]EB!HEO]P]KEXG\^P94S!SXL@[JSSWJOG@"[\ES]QAB573\:$ERXFO.EFJZU^FJUDYYU:9\,P]KEXG\^TOHBC/nww[qcjx:<0Y=!F_WKL+BCIWZSEORAZTZ43Y+U^FJUDYYQLEMN,MZUUDV^9"XQ\RM0e?P6(AV\BC"IJN^QZJFYH]]Q=<P \YOA\KPRXKLFG#A[[_NWW73=R8&CTZDA GDL\W\HDWF__W;>R.R[MGZIR\VIN@A!\HHDW[JSSW}of|>>4U1-J[SOH'NOES^WAC^MVP^07U'YRBNQ@UU]@AIJ(]ZOYS_KH319V4*OX^@E$KH@PSXL@[JSSS?:V"^WAC^MVPZEBDE%dyyQ{elr02>S7'@U]EB!HEO]P]KEXG\^P:<S!SXL@[JSSWJOG@"GPSSN\P7(RWZXG>k5Z0.K\RLI(OLDT_T@L_NWW_37Z&ZSEORAZT^AFHI)K]]UDYY=9;T2,MZPNG&MNBR]VNB]LQQ]19T$XUCMPOTV\G@JK'ZBBJYQ@UU]wahv482_;#DQYIN-DAKYTQGITCXZT60_-W\HDWF__SNKCL.WPAWYUMN9;7X> I^TJK*ABFVYRBNQ@UUY55X(TQGITCXZPCDNO+jssW}of|>84U1-J[SOH'NOES^WAC^MVP^05U'YRBNQ@UU]@AIJ(AVYY@RZ=.T]PVI4a3\:$ERXFO.EFJZU^FJUDYYU92\,P]KEXG\^TOHBC/MWW[JSS;?1^<"GPVHM,C@HX[PDHSB[[[70^*V_IKVE^XRMJLM-PLL@SWF__Sykbp228Q5)NW_CD#JKA_R[MGZIR\R<9Q#]VNB]LQQYDMEF$Y^K]_SGD75=R8&CTZDA GDL\W\HDWF__W;<R.R[MGZIR\VIN@A!`uu]wahv4>2_;#DQYIN-DAKYTQGITCXZT62_-W\HDWF__SNKCL.K\WWJX\;$^S^\C2g9V4*OX^@E$KH@PSXL@[JSSS?9V"^WAC^MVPZEBDE%GYYQ@UU15?P6(AV\BC"IJN^QZJFYH]]Q=?P \YOA\KPRXKLFG#^FFFU]LQQYsmdz8<6[?/H]UMJ)@MGUXUCMPOTVX26[)[PDHSB[[_BGOH*STM[UYIJ=?;T2,MZPNG&MNBR]VNB]LQQ]1;T$XUCMPOTV\G@JK'fSykbp268Q5)NW_CD#JKA_R[MGZIR\VKOH_ \YOA\KPRXIMNY#NAZNU-@M979;=1^<"GPVHM,C@HX[PDHSB[[_@FGV+U^FJUDYYQNDEP,GJSI\&IB0?0<4:W3+LYQAF%LICQ\YOA\KPRXIMNY"^WAC^MVPZGCL[%HCX@[/BK?7;543\:$ERXFO.EFJZU^FJUDYYQNDEP-W\HDWF__SLJKR.ALQKR(L5:5?>5Z0.K\RLI(OLDT_T@L_NWW[DBCZ'YRBNQ@UU]B@AT(KF_EX"J31?10?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"M@UOV,@949;:1^<"GPVHM,C@HX[PDHSB[[_@FGV+U^FJUDYYQNDEP,GJSI\&N7?3=i;T2,MZPNG&MNBR]VNB]LQQYFLMX%_T@L_NWW[DBCZ&IDYCZ GZ2^*BhO&\UFYUMV3`9V4*OX^@E$KH@PSXL@[JSSWHNO^#]VNB]LQQYFLMX$OB[AT.EX4X(RWONYI>74U1-J[SOH'NOES^WAC^MVPZGCL[$XUCMPOTV\EABU'JE^BY!H[1_-QZJR\:h0Y=!F_WKL+BCIWZSEORAZT^CG@W(TQGITCXZPAEFQ+FIRF]%LW=S!U^ZLVF_4n2_;#DQYIN-DAKYTQGITCXZPAEFQ*V_IKVE^XROKDS-@KPHS'NQ:Q#IaH/W\IP^DQ:k0Y=!F_WKL+BCIWZSEORAZT^CG@W(TQGITCXZPAEFQ+FIRF]%LW<S!U^DGV@5>3\:$ERXFO.EFJZU^FJUDYYQNDEP-W\HDWF__SLJKR.ALQKR(OR;V"XQCUU1a?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"M@UOV,C^7Z&\USC_MV3g9V4*OX^@E$KH@PSXL@[JSSWHNO^#]VNB]LQQYFLMX$OB[AT.EX6X(@fA$^S@[WCX1b?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"M@UOV,C^4Z&\UMH_K<9:W3+LYQAF%LICQ\YOA\KPRXIMNY"^WAC^MVPZGCL[%HCX@[/FY1Y+SXD\^8n6[?/H]UMJ)@MGUXUCMPOTV\EABU&ZSEORAZT^CG@W)DG\D_#JU=]/W\\JTDQ:k0Y=!F_WKL+BCIWZSEORAZT^CG@W(TQGITCXZPAEFQ+FIRF]%LW>S!U^DGV@5>3\:$ERXFO.EFJZU^FJUDYYQNDEP-W\HDWF__SLJKR.ALQKR(OR9V"XQCUU1a?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"M@UOV,C^5Z&\USC_MV329V4*OX^@E$KH@PSXL@[JSSWHNO^#]VNB]LQQYFLMX$OB[AT.Q?4;543\:$ERXFO.EFJZU^FJUDYYQNDEP-W\HDWF__SLJKR.ALQKR([5;5?>5Z0.K\RLI(OLDT_T@L_NWW[DBCZ'YRBNQ@UU]B@AT(KF_EX"]32?10?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"M@UOV,W959;81^<"GPVHM,C@HX[PDHSB[[_@FGV+U^FJUDYYQNDEP,@I_6W[OL?<5Z0.K\RLI(OLDT_T@L_NWW[DBCZ'YRBNQ@UU]B@AT(LES9S_KH2g9V4*OX^@E$KH@PSXL@[JSSWHNO^#]VNB]LQQYFLMX$@XZPCD13?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"BZT^MVP67<]9%BS[G@/FGM[V_IKVE^XROKDS,P]KEXG\^TMIJ]/`pn[aj~9:;0Y=!F_WKL+BCIWZSEORAZT^CG@W(TQGITCXZPAEFQ+dtjWmfr>?h4U1-J[SOH'NOES^WAC^MVPZGCL[$XUCMPOTV\EABU'jdSnk<2:W3+LYQAF%LICQ\YOA\KPRXIMNY"^WAC^MVPZGCL[%hbyQ}ergw65=R8&CTZDA GDL\PWGI['_TM_C U^AOADT6n2_;#DQYIN-DAKYSZHDX"XQNRL-V[AIR\;:0Y=!F_WKL+BCIW]XJB^ Z_@PN+PYCG\^;>=5Z0.K\RLI(OLDTX_OAS/W\EWK(]VNDYY?=c:W3+LYQAF%LICQ[R@LP*PYFZD%^SJKA_EGOE\]6U'_TJI<?;T2,MZPNG&MNBRZ]AOQ-QZGUE&_T^KJ]E328Q5)NW_CD#JKA_UPBJV(RWHXF#XQ[FEPF61=R8&CTZDA GDL\PWGI['_TM_C dhl\hdrd`ln:h6[?/H]UMJ)@MGU_^L@\.T]BVH)nKEX9<6[?/H]UMJ)@MGU_^L@\.T]BVH)nL@D7<3<?;T2,MZPNG&MNBRZ]AOQ-QZGUE&cOEC2>>378Q5)NW_CD#JKA_UPBJV(RWHXF#dJ@UU]gh|:76;?0Y=!F_WKL+BCIW]XJB^ Z_@PN+lBH]]Uo`t2>>2;8Q5)NW_CD#JKA_TRGEQCXG\^P==>R.TRGEQCXKLFG#JKA_BNH*PUBZVXNK><4U1-J[SOH'NOESX^KAUG\KPR\99:V"X^KAUG\G@JK'ZBBJYQ]EF1:?P6(AV\BC"IJN^WS@DRBWF__W<>>]/WS@DRBWJOG@"IJN^AOO+STM[UYIJ==;T2,MZPNG&MNBR[_D@VF[JSSS8::Q#[_D@VF[FCKD&YCEKZPRDE0=>S7'@U]EB!HEO]VTAGSMVE^XV??2\,VTAGSMVIN@A!HEO]@HN(R[LXT^HI<2:W3+LYQAF%LICQZPECWAZIR\R;;>P ZPECWAZEBDE%XDDH[_SGD7<=R8&CTZDA GDL\QUBF\LUDYYU>02_-QUBF\LUHIAB GDL\GIM)]ZOYS_KH339V4*OX^@E$KH@PUQFBP@YH]]Q:<>S!UQFBP@YDMEF$_EGIT^PFC6?<]9%BS[G@/FGM[PVCI]OTCXZT116^*PVCI]OTOHBC/FGM[FJL&\YN^R\JG208Q5)NW_CD#JKA_TRGEQCXG\^P==:R.TRGEQCXKLFG#^FFFU]QAB5>3\:$ERXFO.EFJZSWLH^NSB[[[026Y+SWLH^NSNKCL.EFJZEKC'_XI_Q]EF11?P6(AV\BC"IJN^WS@DRBWF__W<>:]/WS@DRBWJOG@"]GIGV\V@A412_;#DQYIN-DAKYRXMK_IRAZTZ332X(RXMK_IRMJLM-DAKYDDB$^_H\PRDE06>S7'@U]EB!HEO]VTAGSMVE^XV??6\,VTAGSMVIN@A!\HHDW[WC@;01^<"GPVHM,C@HX]YNJXHQ@UUY242[)]YNJXHQLEMN,C@HXKEA%Y^K]_SGD77=R8&CTZDA GDL\QUBF\LUDYYU>06_-QUBF\LUHIAB SIKEPZTBO:30Y=!F_WKL+BCIW\ZOMYKPOTVX55>Z&\ZOMYKPCDNO+BCIWJF@"X]JR^PFC64<]9%BS[G@/FGM[PVCI]OTCXZT11:^*PVCI]OTOHBC/RJJBQYUMN927X> I^TJK*ABFV_[HLZJ_NWW_46>U'_[HLZJ_BGOH*ABFVIGG#[\ES]QAB553\:$ERXFO.EFJZSWLH^NSB[[[02:Y+SWLH^NSNKCL.QKMCRXZLM856[?/H]UMJ)@MGU^\IO[E^MVP^768T$^\IO[E^AFHI)@MGUH@F ZSDP\V@A4:2_;#DQYIN-DAKYRXMK_IRAZTZ324X(RXMK_IRMJLM-PLL@SW[OL?45Z0.K\RLI(OLDTY]JNTD]LQQ]698W%Y]JNTD]@AIJ(OLDTOAE!URGQ[WC@;;1^<"GPVHM,C@HX]YNJXHQ@UUY254[)]YNJXHQLEMN,WMOA\VXNK>74U1-J[SOH'NOESX^KAUG\KPR\988V"X^KAUG\G@JK'NOESNBD.TQFVZTBO:80Y=!F_WKL+BCIW\ZOMYKPOTVX544Z&\ZOMYKPCDNO+VNNN]UYIJ=6;T2,MZPNG&MNBR[_D@VF[JSSS8;8Q#[_D@VF[FCKD&MNBRMCK/WPAWYUMN997X> I^TJK*ABFV_[HLZJ_NWW_474U'_[HLZJ_BGOH*UOAO^T^HI<9:W3+LYQAF%LICQZPECWAZIR\R;:8P ZPECWAZEBDE%LICQLLJ,VW@TXZLM8>6[?/H]UMJ)@MGU^\IO[E^MVP^76<T$^\IO[E^AFHI)T@@L_S_KH389V4*OX^@E$KH@PUQFBP@YH]]Q:=8S!UQFBP@YDMEF$KH@PCMI-QVCUW[OL??5Z0.K\RLI(OLDTY]JNTD]LQQ]69<W%Y]JNTD]@AIJ([ACMXR\JG2;8Q5)NW_CD#JKA_TRGEQCXG\^P=<8R.TRGEQCXKLFG#JKA_BNH*PUBZVXNK><4U1-J[SOH'NOESX^KAUG\KPR\98<V"X^KAUG\G@JK'ZBBJYQ]EF1:?P6(AV\BC"IJN^WS@DRBWF__W<?8]/WS@DRBWJOG@"IJN^AOO+STM[UYIJ==;T2,MZPNG&MNBR[_D@VF[JSSS8;<Q#[_D@VF[FCKD&YCEKZPRDE0=>S7'@U]EB!HEO]VTAGSMVE^XV?>8\,VTAGSMVIN@A!HEO]@HN(R[LXT^HI<2:W3+LYQAF%LICQZPECWAZIR\R;:4P ZPECWAZEBDE%XDDH[_SGD7<=R8&CTZDA GDL\QUBF\LUDYYU>18_-QUBF\LUHIAB GDL\GIM)]ZOYS_KH339V4*OX^@E$KH@PUQFBP@YH]]Q:=4S!UQFBP@YDMEF$_EGIT^PFC6?<]9%BS[G@/FGM[PVCI]OTCXZT132^*PVCI]OTOHBC/FGM[FJL&\YN^R\JG208Q5)NW_CD#JKA_TRGEQCXG\^P=?>R.TRGEQCXKLFG#^FFFU]QAB5>3\:$ERXFO.EFJZSWLH^NSB[[[002Y+SWLH^NSNKCL.EFJZEKC'_XI_Q]EF11?P6(AV\BC"IJN^WS@DRBWF__W<<>]/WS@DRBWJOG@"]GIGV\V@A412_;#DQYIN-DAKYRXMK_IRAZTZ316X(RXMK_IRMJLM-DAKYDDB$^_H\PRDE06>S7'@U]EB!HEO]VTAGSMVE^XV?=2\,VTAGSMVIN@A!\HHDW[WC@;01^<"GPVHM,C@HX]YNJXHQ@UUY266[)]YNJXHQLEMN,C@HXKEA%Y^K]_SGD77=R8&CTZDA GDL\QUBF\LUDYYU>22_-QUBF\LUHIAB SIKEPZTBO:30Y=!F_WKL+BCIW\ZOMYKPOTVX572Z&\ZOMYKPCDNO+BCIWJF@"X]JR^PFC64<]9%BS[G@/FGM[PVCI]OTCXZT136^*PVCI]OTOHBC/RJJBQYUMN927X> I^TJK*ABFV_[HLZJ_NWW_442U'_[HLZJ_BGOH*ABFVIGG#[\ES]QAB553\:$ERXFO.EFJZSWLH^NSB[[[006Y+SWLH^NSNKCL.QKMCRXZLM856[?/H]UMJ)@MGU^\IO[E^MVP^75>T$^\IO[E^AFHI)@MGUH@F ZSDP\V@A4:2_;#DQYIN-DAKYRXMK_IRAZTZ312X(RXMK_IRMJLM-PLL@SW[OL?45Z0.K\RLI(OLDTY]JNTD]LQQ]6:>W%Y]JNTD]@AIJ(OLDTOAE!URGQ[WC@;;1^<"GPVHM,C@HX]YNJXHQ@UUY262[)]YNJXHQLEMN,WMOA\VE^X><4U1-J[SOH'NOESX^KAUG\KPR\9;=V"X^KAUG\G@JK'ZBBJYQ]EF1a?P6(AV\BC"IJN^WS@DRBWF__W;:R.TRGEQCXKLFG#JKA_OM\GIM)]ZOYS_KH309V4*OX^@E$KH@PUQFBP@YH]]Q=8P ZPECWAZEBDE%XDDH[_SGD7g=R8&CTZDA GDL\QUBF\LUDYYU95\,VTAGSMVIN@A!HEO]MKZEKC'_XI_Q]EF12?P6(AV\BC"IJN^WS@DRBWF__W;;R.TRGEQCXKLFG#^FFFU]QAB5e3\:$ERXFO.EFJZSWLH^NSB[[[74^*PVCI]OTOHBC/FGM[KIXKEA%Y^K]_SGD74=R8&CTZDA GDL\QUBF\LUDYYU96\,VTAGSMVIN@A!\HHDW[WC@;k1^<"GPVHM,C@HX]YNJXHQ@UUY53X(RXMK_IRMJLM-DAKYIGVIGG#[\ES]QAB563\:$ERXFO.EFJZSWLH^NSB[[[75^*PVCI]OTOHBC/RJJBQYUMN9i7X> I^TJK*ABFV_[HLZJ_NWW_3>Z&\ZOMYKPCDNO+BCIWGETOAE!URGQ[WC@;81^<"GPVHM,C@HX]YNJXHQ@UUY5<X(RXMK_IRMJLM-PLL@SW[OL?o5Z0.K\RLI(OLDTY]JNTD]LQQ]11T$^\IO[E^AFHI)@MGUECRMCK/WPAWYUMN9:7X> I^TJK*ABFV_[HLZJ_NWW_3?Z&\ZOMYKPCDNO+VNNN]UYIJ=m;T2,MZPNG&MNBR[_D@VF[JSSS>:V"X^KAUG\G@JK'NOESCAPCMI-QVCUW[OL?<5Z0.K\RLI(OLDTY]JNTD]LQQ]08T$^\IO[E^AFHI)T@@L_S_KH3c9V4*OX^@E$KH@PUQFBP@YH]]Q<=P ZPECWAZEBDE%LICQAO^AOO+STM[UYIJ=>;T2,MZPNG&MNBR[_D@VF[JSSS>;V"X^KAUG\G@JK'ZBBJYQ]EF1a?P6(AV\BC"IJN^WS@DRBWF__W:<R.TRGEQCXKLFG#JKA_OM\GIM)]ZOYS_KH309V4*OX^@E$KH@PUQFBP@YH]]Q<>P ZPECWAZEBDE%XDDH[_SGD7g=R8&CTZDA GDL\QUBF\LUDYYU83\,VTAGSMVIN@A!HEO]MKZEKC'_XI_Q]EF12?P6(AV\BC"IJN^WS@DRBWF__W:=R.TRGEQCXKLFG#^FFFU]QAB5e3\:$ERXFO.EFJZSWLH^NSB[[[66^*PVCI]OTOHBC/FGM[KIXKEA%Y^K]_SGD74=R8&CTZDA GDL\QUBF\LUDYYU84\,VTAGSMVIN@A!\HHDW[WC@;k1^<"GPVHM,C@HX]YNJXHQ@UUY41X(RXMK_IRMJLM-DAKYIGVIGG#[\ES]QAB563\:$ERXFO.EFJZSWLH^NSB[[[67^*PVCI]OTOHBC/RJJBQYUMN9i7X> I^TJK*ABFV_[HLZJ_NWW_20Z&\ZOMYKPCDNO+BCIWGETOAE!URGQ[WC@;81^<"GPVHM,C@HX]YNJXHQ@UUY42X(RXMK_IRMJLM-PLL@SW[OL?o5Z0.K\RLI(OLDTY]JNTD]LQQ]0?T$^\IO[E^AFHI)@MGUECRMCK/WPAWYUMN9:7X> I^TJK*ABFV_[HLZJ_NWW_21Z&\ZOMYKPCDNO+VNNN]UYIJ=m;T2,MZPNG&MNBR[_D@VF[JSSS>2V"X^KAUG\G@JK'NOESCAPCMI-QVCUW[OL?<5Z0.K\RLI(OLDTY]JNTD]LQQ]00T$^\IO[E^AFHI)T@@L_S_KH3c9V4*OX^@E$KH@PUQFBP@YH]]Q<5P ZPECWAZEBDE%LICQAO^AOO+STM[UYIJ=>;T2,MZPNG&MNBR[_D@VF[JSSS>3V"X^KAUG\G@JK'ZBBJYQ]EF1a?P6(AV\BC"IJN^WS@DRBWF__W5>R.TRGEQCXKLFG#JKA_OM\GIM)]ZOYS_KH309V4*OX^@E$KH@PUQFBP@YH]]Q3<P ZPECWAZEBDE%XDDH[_SGD7g=R8&CTZDA GDL\QUBF\LUDYYU71\,VTAGSMVIN@A!HEO]MKZEKC'_XI_Q]EF12?P6(AV\BC"IJN^WS@DRBWF__W5?R.TRGEQCXKLFG#^FFFU]QAB5e3\:$ERXFO.EFJZSWLH^NSB[[[90^*PVCI]OTOHBC/FGM[KIXKEA%Y^K]_SGD74=R8&CTZDA GDL\QUBF\LUDYYU72\,VTAGSMVIN@A!\HHDW[WC@;k1^<"GPVHM,C@HX]YNJXHQ@UUY;7X(RXMK_IRMJLM-DAKYIGVIGG#[\ES]QAB563\:$ERXFO.EFJZSWLH^NSB[[[91^*PVCI]OTOHBC/RJJBQYUMN9i7X> I^TJK*ABFV_[HLZJ_NWW_=2Z&\ZOMYKPCDNO+BCIWGETOAE!URGQ[WC@;81^<"GPVHM,C@HX]YNJXHQ@UUY;0X(RXMK_IRMJLM-PLL@SW[OL?o5Z0.K\RLI(OLDTY]JNTD]LQQ]?=T$^\IO[E^AFHI)@MGUECRMCK/WPAWYUMN9:7X> I^TJK*ABFV_[HLZJ_NWW_=3Z&\ZOMYKPCDNO+VNNN]UYIJ=m;T2,MZPNG&MNBR[_D@VF[JSSS1<V"X^KAUG\G@JK'NOESCAPCMI-QVCUW[OL?<5Z0.K\RLI(OLDTY]JNTD]LQQ]?>T$^\IO[E^AFHI)T@@L_S_KH3c9V4*OX^@E$KH@PUQFBP@YH]]Q3;P ZPECWAZEBDE%LICQAO^AOO+STM[UYIJ=>;T2,MZPNG&MNBR[_D@VF[JSSS1=V"X^KAUG\G@JK'ZBBJYQ]EF1a?P6(AV\BC"IJN^WS@DRBWF__W56R.TRGEQCXKLFG#JKA_OM\GIM)]ZOYS_KH309V4*OX^@E$KH@PUQFBP@YH]]Q34P ZPECWAZEBDE%XDDH[_SGD7g=R8&CTZDA GDL\QUBF\LUDYYU79\,VTAGSMVIN@A!HEO]MKZEKC'_XI_Q]EF12?P6(AV\BC"IJN^WS@DRBWF__W57R.TRGEQCXKLFG#^FFFU]QAB5e3\:$ERXFO.EFJZSWLH^NSB[[[82^*PVCI]OTOHBC/FGM[KIXKEA%Y^K]_SGD74=R8&CTZDA GDL\QUBF\LUDYYU60\,VTAGSMVIN@A!\HHDW[WC@;k1^<"GPVHM,C@HX]YNJXHQ@UUY:5X(RXMK_IRMJLM-DAKYIGVIGG#[\ES]QAB563\:$ERXFO.EFJZSWLH^NSB[[[83^*PVCI]OTOHBC/RJJBQYUMN9i7X> I^TJK*ABFV_[HLZJ_NWW_<4Z&\ZOMYKPCDNO+BCIWGETOAE!URGQ[WC@;81^<"GPVHM,C@HX]YNJXHQ@UUY:6X(RXMK_IRMJLM-PLL@SW[OL?o5Z0.K\RLI(OLDTY]JNTD]LQQ]>;T$^\IO[E^AFHI)@MGUECRMCK/WPAWYUMN9:7X> I^TJK*ABFV_[HLZJ_NWW_<5Z&\ZOMYKPCDNO+VNNN]UYIJ=m;T2,MZPNG&MNBR[_D@VF[JSSS0>V"X^KAUG\G@JK'NOESCAPCMI-QVCUW[OL?<5Z0.K\RLI(OLDTY]JNTD]LQQ]><T$^\IO[E^AFHI)T@@L_S_KH3c9V4*OX^@E$KH@PUQFBP@YH]]Q29P ZPECWAZEBDE%LICQAO^AOO+STM[UYIJ=>;T2,MZPNG&MNBR[_D@VF[JSSS0?V"X^KAUG\G@JK'ZBBJYQ]EF1;?P6(AV\BC"IJN^WS@DRBWF__W48R.TRGEQCXKLFG#JKA_BNH*PUBZVXNK>?4U1-J[SOH'NOESX^KAUG\KPR\1?W%Y]JNTD]@AIJ([ACMXR\JG2:8Q5)NW_CD#JKA_TRGEQCXG\^P5:S!UQFBP@YDMEF$KH@PCMI-QVCUW[OL?<5Z0.K\RLI(OLDTY]JNTD]LQQ]>?T$^\IO[E^AFHI)T@@L_S_KH399V4*OX^@E$KH@PUQFBP@YH]]Q24P ZPECWAZEBDE%LICQLLJ,VW@TXZLM8=6[?/H]UMJ)@MGU^\IO[E^MVP^??U'_[HLZJ_BGOH*UOAO^T^HI<8:W3+LYQAF%LICQZPECWAZIR\R32Q#[_D@VF[FCKD&MNBRMCK/WPAWYUMN9:7X> I^TJK*ABFV_[HLZJ_NWW_<?Z&\ZOMYKPCDNO+VNNN]UYIJ?7;T2,MZPNG&CE\XZPSIKEP9776820Y=!F_WKL+LHW]]UXDDH[<03=5==R8&CTZDA IORVPZUOAO^7=?0>8:W3+LYQAF%BB][[_RJJBQ:6;7;37X> I^TJK*OIX\^T_EGIT=37:4><]9%BS[G@/HLSQQYT@@L_0<;1199V4*OX^@E$EC^ZT^QKMCR;9?4:46[?/H]UMJ)NFY__S^FFFU>23;7?3\:$ERXFO.KMTPRX[ACMX1?7>0:8Q5)NW_CD#D@_UU]PLL@S4835=:5Z0.K\RLI(AGZ^XR]GIGV?5;7?3\:$ERXFO.KMTPRX[ACMX1<?>0:8Q5)NW_CD#D@_UU]PLL@S4;;5=55Z0.K\RLI(AGZ^XR]GIGV?678602_;#DQYIN-JJUSSWZBBJY2=3?3;?P6(AV\BC"GAPTV\WMOA\58?2<64U1-J[SOH'@D[YYQ\HHDW8739911^<"GPVHM,MKVR\VYCEKZ327<2<>S7'@U]EB!FNQWW[VNNN]69;3?7;T2,MZPNG&CE\XZPSIKEP94?6820Y=!F_WKL+LHW]]UXDDH[<3;=52=R8&CTZDA IORVPZUOAO^7>3?7;T2,MZPNG&CE\XZPSIKEP9576820Y=!F_WKL+LHW]]UXDDH[<23=5==R8&CTZDA IORVPZUOAO^7??0>8:W3+LYQAF%BB][[_RJJBQ:4;7;37X> I^TJK*OIX\^T_EGIT=17:4><]9%BS[G@/HLSQQYT@@L_0>;1199V4*OX^@E$EC^ZT^QKMCR;;?4:46[?/H]UMJ)NFY__S^FFFU>03;7?3\:$ERXFO.KMTPRX[ACMX1=7>0:8Q5)NW_CD#D@_UU]PLL@S4:35=:5Z0.K\RLI(AGZ^XR]GIGV?7;7?3\:$ERXFO.KMTPRX[ACMX1:?>0:8Q5)NW_CD#D@_UU]PLL@S4=;5=55Z0.K\RLI(AGZ^XR]GIGV?078602_;#DQYIN-JJUSSWZBBJY2;3?3;?P6(AV\BC"GAPTV\WMOA\5>?2<64U1-J[SOH'@D[YYQ\HHDW8139911^<"GPVHM,MKVR\VYCEKZ347<2<>S7'@U]EB!FNQWW[VNNN]6?;3?7;T2,MZPNG&CE\XZPSIKEP92?6820Y=!F_WKL+LHW]]UXDDH[<5;=52=R8&CTZDA IORVPZUOAO^783?7;T2,MZPNG&CE\XZPSIKEP9376820Y=!F_WKL+LHW]]UXDDH[<43=5==R8&CTZDA IORVPZUOAO^79?0>8:W3+LYQAF%BB][[_RJJBQ:2;7;37X> I^TJK*OIX\^T_EGIT=77:4><]9%BS[G@/HLSQQYT@@L_08;1199V4*OX^@E$EC^ZT^QKMCR;=?4:46[?/H]UMJ)NFY__S^FFFU>63;7?3\:$ERXFO.KMTPRX[ACMX1;7>0:8Q5)NW_CD#D@_UU]PLL@S4<35=:5Z0.K\RLI(AGZ^XR]GIGV?1;7?3\:$ERXFO.KMTPRX[ACMX18?>0:8Q5)NW_CD#D@_UU]PLL@S4?;5=55Z0.K\RLI(AGZ^XR]GIGV?278602_;#DQYIN-JJUSSWZBBJY293?3;?P6(AV\BC"GAPTV\WMOA\5<?2<94U1-J[SOH'@D[YYQ\HHDW8386?2_;#DQYIN-JJUSSWZBBJY28>058Q5)NW_CD#D@_UU]PLL@S414:;6[?/H]UMJ)NFY__S^FFFU>::4g<]9%BS[G@/NWWTPRX[ACMX1??0?3b?P6(AV\BC"AZTQWW[VNNN]6:<<0>a:W3+LYQAF%DYY^ZT^QKMCR;9985=l5Z0.K\RLI(G\^[YYQ\HHDW846468k0Y=!F_WKL+JSSX\^T_EGIT=330;7f3\:$ERXFO.MVPUSSWZBBJY2>04<2e>S7'@U]EB!@UURVPZUOAO^7==811`9V4*OX^@E$CXZ_UU]PLL@S48:<2<o4U1-J[SOH'F__\XZPSIKEP97707;j7X> I^TJK*IR\Y__S^FFFU>24<8612_;#DQYIN-LQQVR\VYCEKZ311<2e>S7'@U]EB!@UURVPZUOAO^7=<>11`9V4*OX^@E$CXZ_UU]PLL@S48;:2<o4U1-J[SOH'F__\XZPSIKEP976:7;j7X> I^TJK*IR\Y__S^FFFU>25686i2_;#DQYIN-LQQVR\VYCEKZ3106=5d=R8&CTZDA OTVSQQYT@@L_0<?:>0c8Q5)NW_CD#B[[PTV\WMOA\5;::3?n;T2,MZPNG&E^X][[_RJJBQ:69>4:m6[?/H]UMJ)H]]Z^XR]GIGV?54>99h1^<"GPVHM,KPRW]]UXDDH[<03::4?<]9%BS[G@/NWWTPRX[ACMX1?>>0c8Q5)NW_CD#B[[PTV\WMOA\5;9<3?n;T2,MZPNG&E^X][[_RJJBQ:6:84:m6[?/H]UMJ)H]]Z^XR]GIGV?57499h1^<"GPVHM,KPRW]]UXDDH[<000:4g<]9%BS[G@/NWWTPRX[ACMX1?=4?3b?P6(AV\BC"AZTQWW[VNNN]6:>80>a:W3+LYQAF%DYY^ZT^QKMCR;9;<5=l5Z0.K\RLI(G\^[YYQ\HHDW84406830Y=!F_WKL+JSSX\^T_EGIT=31:4?<]9%BS[G@/NWWTPRX[ACMX1?<>0;8Q5)NW_CD#B[[PTV\WMOA\5;?2<74U1-J[SOH'F__\XZPSIKEP9726830Y=!F_WKL+JSSX\^T_EGIT=35:4?<]9%BS[G@/NWWTPRX[ACMX1?8>0;8Q5)NW_CD#B[[PTV\WMOA\5;32<74U1-J[SOH'F__\XZPSIKEP97>6820Y=!F_WKL+JSSX\^T_EGIT=3=5<=R8&CTZDA OTVSQQYT@@L_0?>1189V4*OX^@E$CXZ_UU]PLL@S4;;5=45Z0.K\RLI(G\^[YYQ\HHDW8749901^<"GPVHM,KPRW]]UXDDH[<31=5<=R8&CTZDA OTVSQQYT@@L_0?:1189V4*OX^@E$CXZ_UU]PLL@S4;?5=45Z0.K\RLI(G\^[YYQ\HHDW8709901^<"GPVHM,KPRW]]UXDDH[<35=5<=R8&CTZDA OTVSQQYT@@L_0?61189V4*OX^@E$CXZ_UU]PLL@S4;35=55Z0.K\RLI(G\^[YYQ\HHDW878612_;#DQYIN-LQQVR\VYCEKZ331<2=>S7'@U]EB!@UURVPZUOAO^7?<0>9:W3+LYQAF%DYY^ZT^QKMCR;;;4:56[?/H]UMJ)H]]Z^XR]GIGV?768612_;#DQYIN-LQQVR\VYCEKZ335<2=>S7'@U]EB!@UURVPZUOAO^7?80>9:W3+LYQAF%DYY^ZT^QKMCR;;?4:56[?/H]UMJ)H]]Z^XR]GIGV?728612_;#DQYIN-LQQVR\VYCEKZ339<2=>S7'@U]EB!@UURVPZUOAO^7?40>8:W3+LYQAF%DYY^ZT^QKMCR;;7;27X> I^TJK*IR\Y__S^FFFU>74;7>3\:$ERXFO.MVPUSSWZBBJY2;1?3:?P6(AV\BC"AZTQWW[VNNN]6?>3?6;T2,MZPNG&E^X][[_RJJBQ:3;7;27X> I^TJK*IR\Y__S^FFFU>70;7>3\:$ERXFO.MVPUSSWZBBJY2;5?3:?P6(AV\BC"AZTQWW[VNNN]6?:3?6;T2,MZPNG&E^X][[_RJJBQ:3?7;27X> I^TJK*IR\Y__S^FFFU>7<;7>3\:$ERXFO.MVPUSSWZBBJY2;9?3;?P6(AV\BC"AZTQWW[VNNN]6?2<74U1-J[SOH'F__\XZPSIKEP9376830Y=!F_WKL+JSSX\^T_EGIT=72:4?<]9%BS[G@/NWWTPRX[ACMX1;=>0;8Q5)NW_CD#B[[PTV\WMOA\5?82<74U1-J[SOH'F__\XZPSIKEP9336830Y=!F_WKL+JSSX\^T_EGIT=76:4?<]9%BS[G@/NWWTPRX[ACMX1;9>0;8Q5)NW_CD#B[[PTV\WMOA\5?<2<74U1-J[SOH'F__\XZPSIKEP93?6830Y=!F_WKL+JSSX\^T_EGIT=7::4><]9%BS[G@/NWWTPRX[ACMX1;1189V4*OX^@E$CXZ_UU]PLL@S4?:5=45Z0.K\RLI(G\^[YYQ\HHDW8379901^<"GPVHM,KPRW]]UXDDH[<70=5<=R8&CTZDA OTVSQQYT@@L_0;=1189V4*OX^@E$CXZ_UU]PLL@S4?>5=45Z0.K\RLI(G\^[YYQ\HHDW8339901^<"GPVHM,KPRW]]UXDDH[<74=5<=R8&CTZDA OTVSQQYT@@L_0;91189V4*OX^@E$CXZ_UU]PLL@S4?25=45Z0.K\RLI(G\^[YYQ\HHDW83?9911^<"GPVHM,KPRW]]UXDDH[<7<2=>S7'@U]EB!@UURVPZUOAO^7;=0>9:W3+LYQAF%DYY^ZT^QKMCR;?84:56[?/H]UMJ)H]]Z^XR]GIGV?378612_;#DQYIN-LQQVR\VYCEKZ372<2=>S7'@U]EB!@UURVPZUOAO^7;90>9:W3+LYQAF%DYY^ZT^QKMCR;?<4:56[?/H]UMJ)H]]Z^XR]GIGV?338612_;#DQYIN-LQQVR\VYCEKZ376<2=>S7'@U]EB!@UURVPZUOAO^7;50>9:W3+LYQAF%DYY^ZT^QKMCR;?04:46[?/H]UMJ)H]]Z^XR]GIGV?3;7>3\:$ERXFO.MVPUSSWZBBJY270?3:?P6(AV\BC"AZTQWW[VNNN]63=3?6;T2,MZPNG&E^X][[_RJJBQ:?:7;27X> I^TJK*IR\Y__S^FFFU>;7;7>3\:$ERXFO.MVPUSSWZBBJY274?3:?P6(AV\BC"AZTQWW[VNNN]6393?6;T2,MZPNG&E^X][[_RJJBQ:?>7;27X> I^TJK*IR\Y__S^FFFU>;3;7>3\:$ERXFO.MVPUSSWZBBJY278?3:?P6(AV\BC"AZTQWW[VNNN]6353?7;T2,MZPNG&E^X][[_RJJBQ:?6830Y=!F_WKL+JSSX\^T_EGIT=;3:4?<]9%BS[G@/NWWTPRX[ACMX17>>0;8Q5)NW_CD#B[[PTV\WMOA\5392<74U1-J[SOH'F__\XZPSIKEP9?46830Y=!F_WKL+JSSX\^T_EGIT=;7:4?<]9%BS[G@/NWWTPRX[ACMX17:>0;8Q5)NW_CD#B[[PTV\WMOA\53=2<74U1-J[SOH'F__\XZPSIKEP9?06830Y=!F_WKL+JSSX\^T_EGIT=;;:4?<]9%BS[G@/NWWTPRX[ACMX176>0:8Q5)NW_CD#B[[PTV\WMOA\535i6[?/H]UMJ)UMZO_=?5Z0.K\RLI([]K_SIAZT008Q5)NW_CD#X^KAUG?4;743\:$ERXFO.WS@DRB48:5=>5Z0.K\RLI(]YNJXH2>1?30?P6(AV\BC"[_D@VF84499:1^<"GPVHM,QUBF\L6:?3?<;T2,MZPNG&_[HLZJ<06=56=R8&CTZDA UQFBP@:6=7;87X> I^TJK*SWLH^N0<81129V4*OX^@E$Y]JNTD>23;743\:$ERXFO.WS@DRB4825=>5Z0.K\RLI(]YNJXH2>9?31?P6(AV\BC"[_D@VF8486;2_;#DQYIN-VTAGSM58;2<=4U1-J[SOH'\ZOMYK320<27>S7'@U]EB!ZPECWA9456890Y=!F_WKL+PVCI]O7>>0>3:W3+LYQAF%^\IO[E=07:45<]9%BS[G@/TRGEQC;:<4:?6[?/H]UMJ)RXMK_I1<9>018Q5)NW_CD#X^KAUG?6286;2_;#DQYIN-VTAGSM5832<=4U1-J[SOH'\ZOMYK328<26>S7'@U]EB!ZPECWA9499:1^<"GPVHM,QUBF\L68<3?<;T2,MZPNG&_[HLZJ<23=56=R8&CTZDA UQFBP@:4:7;87X> I^TJK*SWLH^N0>=1129V4*OX^@E$Y]JNTD>00;743\:$ERXFO.WS@DRB4:?5=>5Z0.K\RLI(]YNJXH2<6?30?P6(AV\BC"[_D@VF86199:1^<"GPVHM,QUBF\L6843?<;T2,MZPNG&_[HLZJ<2;=57=R8&CTZDA UQFBP@:46890Y=!F_WKL+PVCI]O78=0>3:W3+LYQAF%^\IO[E=62:45<]9%BS[G@/TRGEQC;<;4:?6[?/H]UMJ)RXMK_I1:<>018Q5)NW_CD#X^KAUG?0186;2_;#DQYIN-VTAGSM5>>2<=4U1-J[SOH'\ZOMYK347<27>S7'@U]EB!ZPECWA9206890Y=!F_WKL+PVCI]O7850>3:W3+LYQAF%^\IO[E=6::44<]9%BS[G@/TRGEQC;<7;87X> I^TJK*SWLH^N08>1129V4*OX^@E$Y]JNTD>65;743\:$ERXFO.WS@DRB4<85=>5Z0.K\RLI(]YNJXH2:3?30?P6(AV\BC"[_D@VF80299:1^<"GPVHM,QUBF\L6>93?<;T2,MZPNG&_[HLZJ<44=56=R8&CTZDA UQFBP@:2?7;87X> I^TJK*SWLH^N0861129V4*OX^@E$Y]JNTD>6=;753\:$ERXFO.WS@DRB4<4:?6[?/H]UMJ)RXMK_I18?>018Q5)NW_CD#X^KAUG?2486;2_;#DQYIN-VTAGSM5<92<=4U1-J[SOH'\ZOMYK362<26>S7'@U]EB!ZPECWA9099;1^<"GPVHM,QUBF\L6<2<<4U1-J[SOH'\ZOMYK38?31?P6(AV\BC"[_D@VF8<86;2_;#DQYIN-V[AGSIVE^Xk5Z0.K\RLI(]VNDYY?n;T2,MZPNG&_T_YO[UR-@BBYDMVd956[?/H]UMJ)RWZ^JXX] F^QWEQ]7U'CT_YO[.T]PPDR512_;#DQYIN-V[VRF\\Y$JR][AUY2Y+OX[]K_"XQ\T@V1=>S7'@U]EB!Z_RVBPPU(NVY_MYU=]/K\WQGS&\UXXLZ=9:W3+LYQAF%^S^ZNTTQ,BZUSI]Q8Q#GPSUCW*PYT\H^956[?/H]UMJ)RWZ^JXX] F^QWEQ]3U'CT_YO[.T]PPDR512_;#DQYIN-V[VRF\\Y$JR][AUY6Y+OX[]K_"XQ\T@V1=>S7'@U]EB!Z_RVBPPU(NVY_MYU9]/K\WQGS&\UXXLZ=9:W3+LYQAF%^S^ZNTTQ,BZUSI]Q<Q#GPSUCW*PYT\H^:m6[?/H]UMJ)RWZ^JXX] TEM\j`~s911^<"GPVHM,QZUSI]_X#XQLE^l03>S7'@U]EB!Z_RVBPPU(]VYFYU!Z_BQ\IP^(A=$^S@[W17-Nip~XG1;94>94U1-J[SOH'\UXXLZZS.W\WHS_'\UH_RCZX.K7*PYJ]Q;=#@czx^M;5324?2_;#DQYIN-V[VRF\\Y$YR]BUY-V[FUXE\R$E9 Z_LW[53)Je|rTC5<902`8Q5)NW_CD#XQ\T@VVW*SX[D_S#XQLS^OV\*O3&\UFYU?9/Lov|ZI?:?:T_Z><7:W3+LYQAF%^S^ZNTTQ,QZUJ]Q%^SN]PMTZ,M1(RWD_S=;!Bmtz\K=40?:=0Y=!F_WKL+PYT\H^^_"[PSLW[+PYD[VG^T"G;.T]NQ]71'Dg~tRA735402>S7'@U]EB!Z_RVBPPU(]VYFYU!Z_BQ\IP^(A=$^S@[W17-Nip~XG19>?:5Z0.K\RLI(]VY_MY[\/T]PIP^(]VIXS@[W/H6-QZKRP8<$A`{w_N:0=<503\:$ERXFO.W\WQGS]Z%^S^CZX.W\GVYJ]Q%B8#[PMTZ22*Kj}qUD49;=379V4*OX^@E$YR][AUWP+PYTE\R$YRM\_LW[+L2)]VG^T<8 Mlw{[J>09;80Y=!F_WKL+PYT\H^^_"[PSUCW[FHS'JC7=3<=;T2,MZPNG&_T_YO[UR-V[VRF\VIEX"MF<3<16>S7'@U]EB!Z_RVBPPU(]VY_MYQLNU-@M959:;1^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(K@6?2?<4U1-J[SOH'\UXXLZZS.W\WQGSWJD_#NG35?01?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.AJ8385:2_;#DQYIN-V[VRF\\Y$YR][AU]@JQ)DA5=5><5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$H1>1209V4*OX^@E$YR][AUWP+PYT\H^TOCZ D=3=64=R8&CTZDA U^QWEQST'\UXXLZPCOV,@949:81^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(L595><5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$H1:1209V4*OX^@E$YR][AUWP+PYT\H^TOCZ D=7=64=R8&CTZDA U^QWEQST'\UXXLZPCOV,@909:81^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(L5=5>i5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$KV>R.FlK*PYJ]QIR>55Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$KV>R.T]E@WC5?2_;#DQYIN-V[VRF\\Y$YR][AU]@JQ)@S9W%YRBZT3;8Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/FY3Y+SXPFXHU?j4U1-J[SOH'\UXXLZZS.W\WQGSWJD_#JU>]/EmL+SXE\RHU?64U1-J[SOH'\UXXLZZS.W\WQGSWJD_#JU>]/W\BATB:>1^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(OR;V"XQCUU0:?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.EX5X(RWQEYOT<k;T2,MZPNG&_T_YO[UR-V[VRF\VIEX"IT2\,DjM(RWD_SOT<7;T2,MZPNG&_T_YO[UR-V[VRF\VIEX"IT2\,V[CBUM;=0Y=!F_WKL+PYT\H^^_"[PSUCW[FHS'NQ9Q#[PLTV1=>S7'@U]EB!Z_RVBPPU(]VY_MYQLNU-D_7[)]VRD^NW=d:W3+LYQAF%^S^ZNTTQ,QZUSI]UHBY!H[2_-CkN)]VG^TNW=8:W3+LYQAF%^S^ZNTTQ,QZUSI]UHBY!H[2_-QZ@CZL8<7X> I^TJK*SX[]K_Y^!Z_RVBPZEI\&MP?P Z_MWW6<=R8&CTZDA U^QWEQST'\UXXLZPCOV,C^5Z&\USC_MV2e9V4*OX^@E$YR][AUWP+PYT\H^TOCZ GZ6^*BhO&\UFYUMV299V4*OX^@E$YR][AUWP+PYT\H^TOCZ GZ6^*PYAL[O9;6[?/H]UMJ)RWZ^JXX] U^QWEQYDF]%LW9S!U^NVP7?<]9%BS[G@/T]PPDRR[&_T_YO[_BLW+B]3U'_TTB\LY3f8Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/FY6Y+Ai@'_TAXVLY3:8Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/FY6Y+SXNMXN>:5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$KV;R.T]OQQ4>3\:$ERXFO.W\WQGS]Z%^S^ZNT^AMP*A\=T$^SUA]CX0g?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.EX2X(@fA$^S@[WCX0;?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.EX2X(RWONYI?94U1-J[SOH'\UXXLZZS.W\WQGSWJD_#JU9]/W\HPR512_;#DQYIN-V[VRF\\Y$YR][AU]@JQ)@S?W%YRV@RB[1<>S7'@U]EB!Z_RVBPPU(]VY_MYQLNU-D_2[)]VLO^H<8;T2,MZPNG&_T_YO[UR-V[VRF\VIEX"IT7\,V[ISS:01^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(OR=V"XQWOSAZ64=R8&CTZDA U^QWEQST'\UXXLZPCOV,W969:81^<"GPVHM,QZUSI]_X#XQ\T@V\GKR([5;5><5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$_1<1209V4*OX^@E$YR][AUWP+PYT\H^TOCZ S=1=64=R8&CTZDA U^QWEQST'\UXXLZPCOV,W929:81^<"GPVHM,QZUSI]_X#XQ\T@V\GKR([5?5><5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$_181209V4*OX^@E$YR][AUWP+PYT\H^TOCZ S=5=52=R8&CTZDA U^QWEQST'\U_HB?n;T2,MZPNG&_T_YO[UR-jWQGS494:m6[?/H]UMJ)RWZ^JXX] iRVBP9799h1^<"GPVHM,QZUSI]_X#d][AU>1:4g<]9%BS[G@/T]PPDRR[&cXXLZ33?3b?P6(AV\BC"[PSUCWQV)n[]K_090>a:W3+LYQAF%^S^ZNTTQ,mVRF\5?5=l5Z0.K\RLI(]VY_MY[\/hQWEQ:168k0Y=!F_WKL+PYT\H^^_"g\T@V?3;7b3\:$ERXFO.W\WQGS]Z%b_YO[_BLW8586m2_;#DQYIN-V[VRF\\Y$e^ZNT^AMP9799l1^<"GPVHM,QZUSI]_X#d][AU]@JQ:568o0Y=!F_WKL+PYT\H^^_"g\T@V\GKR;;7;n7X> I^TJK*SX[]K_Y^!fSUCW[FHS4=4:i6[?/H]UMJ)RWZ^JXX] iRVBPZEI\5?5=h5Z0.K\RLI(]VY_MY[\/hQWEQYDF]6=2<k4U1-J[SOH'\UXXLZZS.kPPDRXKG^7;3??;T2,MZPNG&koh2?>028Q5)NW_CD#ljkr=3=55=R8&CTZDA aefq878682_;#DQYIN-b`at;;7897X> I^TJK*tb{l~TjRkkgd-J[M4K&\UOCXZ>d:W3+LYQAF%yi~k{_g]f`bc(]VNDYY>>d:W3+LYQAF%yi~k{_g]f`bc(]VNDYY?>e:W3+LYQAF%yi~k{_g]f`bc(aME^X1>11d9V4*OX^@E$~h}jt^d\aaab'`NDYY2>>b9VW@TX^@YBNAK<;WA@=>PNM^U_U]K>d:ZJHLH_%QNI,= > RVVF%6)9)KXODG:;YMQG\0<PZ^GEO94XRV\CKB03QY_S[MLb:Z\GJTBW@DMC;5Wdc]J`46<PmgTAld`rWgqwlii991Sh`QBiomqR`ttafd87U}{309`llvtkfznS{g`_w3\46Yf$)Rb`d`w BMQA%Abflxjxb|/10,2<>bf|hU}eb<7;ecweZpng%ice}}loqg\rliX~8U;?Ro#NNLF(KIIM;io7io{a^tjk)eoayyhc}kPvhm\r4Y7;Vk'wnQwcn]omvr:Kfg{cckat^Lbi`;ci}kTzda4Eocah`YTqgic~b``ur]JjussWYeyx0z}ud9FjddkmVYrbnf}oomvwZIr|yS]a}t<vqq`=BfhhgiRO|yoakvjhh}zUBb}{{_Qmqp8ru}l1Nbllce^Cp}keozfddy~Q@uurvpZVhz}7~xk4Sxl`lwiig|yTEc~zt^RlvqYPam~c1><4Sxl`lwiig|yTCxzuu]SkwrX_`nd0==;@qzjfnugge~RGaptv\TjtsW^coxe3<2:Cp}keozfddy~Q@uurvpZVhz}U\eizg=208Mkpbz}UH`bmd_Hlsqq;aieyn nQwddtjg``fe`fr1{g}tdz5(fYdg{oTxt~j=8.`[h``W`n6=!mPm`hlvZpbzzcdb0?>,b]nmkiuWoydaa=0.`[gsndmUyi{g|inl>4)eXkfxnS`oeos]uaw;6$jUhckPmhllvZpbz48'oRm`rd]nmkiuWhf{dlQyes?:3)eX{{f::Rzvpd?1(fYr{lUbb{Qllj?3(fYr{lUjt`l_hl>5)eX}zoTm~wac^mvp87+kVxiR}vnb]jj87+kVxiR}vnb]lqq;6$jUjt`l_hl\slbs`499 nQnsxl`[jssW~coxe3<2-a\w|hdW`dT{dj{h<11(fYtqgiTcxzPwhfwl855$t;:7um9vmz41q+an>2?!?sO@q0:g2=GHqi;>7H52;3xW=1=k9:15>4>33:g24<5kk>2wclie;38jg`a2<1/nkj5bg58yV072j:;64=5120;`37=:jh?j6jl0383>4<6sZ2<6n>?:819564?l?;1>nl;9:tWf1<7280:6;?7{R:4>f672091=><7d7396fd312.ij;46f:&b`?e7=2hh<?4?:`791<2=>82pDoh;;%d:>f653S?368u8:98a><<f2t.ijn4l009'1f<d8:1/4;4l059j6`<72-km6?j4n`g94>=n:j0;6)oi:3f8jdc=921b>l4?:%ce>7b<fho1>65f2883>!ga2;n0blk53:9j6=<72-km6?j4n`g90>=n:>0;6)oi:3f8jdc==21b>;4?:%ce>7b<fho1:65f2483>!ga2;n0blk57:9j61<72-km6?j4n`g9<>=n::0;6)oi:3f8jdc=121b>?4?:%ce>7b<fho1m65f2083>!ga2;n0blk5b:9j5c<72-km6?j4n`g9g>=n9l0;6)oi:3f8jdc=l21b=i4?:%ce>7b<fho1i65f1b83>!ga2;n0blk5f:9j5g<72-km6?j4n`g955=<a8k1<7*nf;0g?kgb28;07d?6:18'ec<5l2dji7?=;:k2<?6=,hl1>i5aad827>=n9>0;6)oi:3f8jdc=9=10e<850;&bb?4c3gkn6<;4;h16>5<#io09h6`ne;35?>o4<3:1(lh52e9me`<6?21b?>4?:%ce>7b<fho1=554i2094?"fn38o7coj:0;8?l56290/mk4=d:lba?7f32c8<7>5$`d96a=iil0:n65f2g83>!ga2;n0blk51b98m7d=83.jj7<k;ocf>4b<3`8;6=4+ag81`>hfm3;n76g>5;29 d`=:m1emh4>f:9jgc<72-km6nk4n`g94>=nkm0;6)oi:bg8jdc=921boo4?:%ce>fc<fho1>65fc`83>!ga2jo0blk53:9jg<<72-km6nk4n`g90>=nk10;6)oi:bg8jdc==21bo:4?:%ce>fc<fho1:65fc783>!ga2jo0blk57:9jg0<72-km6nk4n`g9<>=nk=0;6)oi:bg8jdc=121bo>4?:%ce>fc<fho1m65fc383>!ga2jo0blk5b:9jg5<72-km6nk4n`g9g>=njo0;6)oi:bg8jdc=l21bnh4?:%ce>fc<fho1i65fbe83>!ga2jo0blk5f:9jff<72-km6nk4n`g955=<akh1<7*nf;af?kgb28;07dln:18'ec<dm2dji7?=;:ka=?6=,hl1oh5aad827>=nj10;6)oi:bg8jdc=9=10eo950;&bb?eb3gkn6<;4;hf5>5<#io0hi6`ne;35?>oc=3:1(lh5cd9me`<6?21bh94?:%ce>fc<fho1=554ie194?"fn3in7coj:0;8?lb5290/mk4le:lba?7f32co=7>5$`d9g`=iil0:n65fd183>!ga2jo0blk51b98mfe=83.jj7mj;ocf>4b<3`i:6=4+ag8`a>hfm3;n76gm6;29 d`=kl1emh4>f:9(3`<72-km6:j4n`g94>=,?j0;6)oi:6f8jdc=921 ;o4?:%ce>2b<fho1>65$7`83>!ga2>n0blk53:9(3<<72-km6:j4n`g90>=,?10;6)oi:6f8jdc==21 ;;4?:%ce>2b<fho1:65$7483>!ga2>n0blk57:9(31<72-km6:j4n`g9<>=,?:0;6)oi:6f8jdc=121 ;?4?:%ce>2b<fho1m65$7083>!ga2>n0blk5b:9(35<72-km6:j4n`g9g>=,>o0;6)oi:6f8jdc=l21 :h4?:%ce>2b<fho1i65$6e83>!ga2>n0blk5f:9(2g<72-km6:j4n`g955=<#?k1<7*nf;5g?kgb28;07&86:18'ec<0l2dji7?=;:)5<?6=,hl1;i5aad827>=,>>0;6)oi:6f8jdc=9=10';850;&bb?1c3gkn6<;4;*46>5<#io0<h6`ne;35?>-1<3:1(lh57e9me`<6?21 :>4?:%ce>2b<fho1=554+7094?"fn3=o7coj:0;8?.>2290/mk48d:lba?7f32!387>5$`d93a=iil0:n65$8283>!ga2>n0blk51b98/=4=83.jj79k;ocf>4b<3"2:6=4+ag84`>hfm3;n76%70;29 d`=?m1emh4>f:9(32<72-km6:j4n`g964=<#?i1<7*nf;5g?kgb2;807&8>:18'ec<0l2dji7<<;:k6a?6=3f>m6=4+ag87a>hfm3:07b:k:18'ec<3m2dji7?4;n6a>5<#io0?i6`ne;08?j2f290/mk4;e:lba?5<3f>26=4+ag87a>hfm3>07b:7:18'ec<3m2dji7;4;n64>5<#io0?i6`ne;48?j21290/mk4;e:lba?1<3f>>6=4+ag87a>hfm3207b:;:18'ec<3m2dji774;n60>5<#io0?i6`ne;c8?j25290/mk4;e:lba?d<3f>;6=4+ag87a>hfm3i07b=i:18'ec<3m2dji7j4;n1f>5<#io0?i6`ne;g8?j5c290/mk4;e:lba?`<3f9h6=4+ag87a>hfm3;;76a<b;29 d`=<l1emh4>1:9l7d<72-km69k4n`g957=<g:31<7*nf;6f?kgb28907b=7:18'ec<3m2dji7?;;:m03?6=,hl18h5aad821>=h=?0;6)oi:5g8jdc=9?10c8;50;&bb?2b3gkn6<94;n77>5<#io0?i6`ne;3;?>i2;3:1(lh54d9me`<6121d9?4?:%ce>1c<fho1=l54o4394?"fn3>n7coj:0`8?j37290/mk4;e:lba?7d32e?o7>5$`d90`=iil0:h65`4083>!ga2=o0blk51d98k60=83.jj7:j;ocf>4`<3fl;6=4+ag8fb>hfm3:07bkj:18'ec<bn2dji7?4;ng`>5<#io0nj6`ne;08?jce290/mk4jf:lba?5<3foj6=4+ag8fb>hfm3>07bk6:18'ec<bn2dji7;4;ng;>5<#io0nj6`ne;48?jc0290/mk4jf:lba?1<3fo=6=4+ag8fb>hfm3207bk::18'ec<bn2dji774;ng7>5<#io0nj6`ne;c8?jc4290/mk4jf:lba?d<3fo:6=4+ag8fb>hfm3i07bk?:18'ec<bn2dji7j4;nfe>5<#io0nj6`ne;g8?jbb290/mk4jf:lba?`<3fno6=4+ag8fb>hfm3;;76akc;29 d`=mo1emh4>1:9l`g<72-km6hh4n`g957=<gmk1<7*nf;ge?kgb28907bj6:18'ec<bn2dji7?;;:mg<?6=,hl1ik5aad821>=hn>0;6)oi:dd8jdc=9?10ck850;&bb?ca3gkn6<94;nd6>5<#io0nj6`ne;3;?>ia<3:1(lh5eg9me`<6121dj>4?:%ce>``<fho1=l54og094?"fn3om7coj:0`8?j`6290/mk4jf:lba?7d32enh7>5$`d9ac=iil0:h65`e383>!ga2ll0blk51d98ka1=83.jj7ki;ocf>4`<3"=m6=4+ag84`>hfm38;76lmf`83>4<729q/j4462:Jab<=Ojo>0c4?50;9~fg`e290:6=4?{%d:>g`23Ahm56Fmf59lef<722wi5>m50;;94?6|,o31n85Gbg;8Lg`33-3i6<5f1183>>o693:17d?=:188m45=831b9o4?::k6a?6=3`236=44oc294?=hj80;66sm92f94?5=83:p(k75a09Kfc?<@kl?7)7m:d9j=0<722c2:7>5;nca>5<<uk3?=7>59;294~"a13h>7Eli9:Jab1=#1k0:7d??:188m47=831b=?4?::k27?6=3`?i6=44i4g94?=n010;66am0;29?jd62900qo7;2;297?6=8r.m57o>;I`e=>Nen=1/5o4j;h;6>5<<a0<1<75`ac83>>{e1=<1<7750;2x c?=j<1Cnk74Hcd7?!?e281b==4?::k25?6=3`;96=44i0194?=n=k0;66g:e;29?l>?2900co>50;9lf4<722wi59950;194?6|,o31m<5Gbg;8Lg`33-3i6h5f9483>>o>>3:17bom:188yg?3j3:157>50z&e=?d23Ahm56Fmf59'=g<63`;;6=44i0394?=n9;0;66g>3;29?l3e2900e8k50;9j<=<722ei<7>5;n`2>5<<uk3?o7>53;294~"a13k:7Eli9:Jab1=#1k0n7d7::188m<0=831dmo4?::a=06=8331<7>t$g;9f0=Ojo30Doh;;%;a>4=n990;66g>1;29?l752900e<=50;9j1g<722c>i7>5;h:;>5<<gk:1<75`b083>>{e1<;1<7=50;2x c?=i81Cnk74Hcd7?!?e2l1b584?::k:2?6=3fki6=44}c;61?6=13:1<v*i9;`6?Mda12Bij95+9c82?l772900e<?50;9j57<722c:?7>5;h7a>5<<a<o1<75f8983>>ie83:17bl>:188yg?2>3:1?7>50z&e=?g63Ahm56Fmf59'=g<b3`3>6=44i8494?=hik0;66sm94c94??=83:p(k75b49Kfc?<@kl?7)7m:09j55<722c:=7>5;h31>5<<a891<75f5c83>>o2m3:17d67:188kg6=831dn<4?::a=0d=8391<7>t$g;9e4=Ojo30Doh;;%;a>`=n1<0;66g66;29?jge2900qo7:f;29=?6=8r.m57l:;I`e=>Nen=1/5o4>;h33>5<<a8;1<75f1383>>o6;3:17d;m:188m0c=831b454?::ma4?6=3fh:6=44}c;54?6=;3:1<v*i9;c2?Mda12Bij95+9c8f?l?22900e4850;9leg<722wi5;:50;;94?6|,o31n85Gbg;8Lg`33-3i6<5f1183>>o693:17d?=:188m45=831b9o4?::k6a?6=3`236=44oc294?=hj80;66sm97794?5=83:p(k75a09Kfc?<@kl?7)7m:d9j=0<722c2:7>5;nca>5<<uk3=57>59;294~"a13h>7Eli9:Jab1=#1k0:7d??:188m47=831b=?4?::k27?6=3`?i6=44i4g94?=n010;66am0;29?jd62900qo79a;297?6=8r.m57o>;I`e=>Nen=1/5o4j;h;6>5<<a0<1<75`ac83>>{e1?o1<7750;2x c?=j<1Cnk74Hcd7?!?e281b==4?::k25?6=3`;96=44i0194?=n=k0;66g:e;29?l>?2900co>50;9lf4<722wi5;h50;194?6|,o31m<5Gbg;8Lg`33-3i6h5f9483>>o>>3:17bom:188yg?0;3:157>50z&e=?d23Ahm56Fmf59'=g<63`;;6=44i0394?=n9;0;66g>3;29?l3e2900e8k50;9j<=<722ei<7>5;n`2>5<<uk3<87>53;294~"a13k:7Eli9:Jab1=#1k0n7d7::188m<0=831dmo4?::a=2>=8331<7>t$g;9f0=Ojo30Doh;;%;a>4=n990;66g>1;29?l752900e<=50;9j1g<722c>i7>5;h:;>5<<gk:1<75`b083>>{e1>31<7=50;2x c?=i81Cnk74Hcd7?!?e2l1b584?::k:2?6=3fki6=44}c;4`?6=13:1<v*i9;`6?Mda12Bij95+9c82?l772900e<?50;9j57<722c:?7>5;h7a>5<<a<o1<75f8983>>ie83:17bl>:188yg?0m3:1?7>50z&e=?g63Ahm56Fmf59'=g<b3`3>6=44i8494?=hik0;66sm99094??=83:p(k75b49Kfc?<@kl?7)7m:09j55<722c:=7>5;h31>5<<a891<75f5c83>>o2m3:17d67:188kg6=831dn<4?::a==5=8391<7>t$g;9e4=Ojo30Doh;;%;a>`=n1<0;66g66;29?jge2900qo777;29=?6=8r.m57l:;I`e=>Nen=1/5o4>;h33>5<<a8;1<75f1383>>o6;3:17d;m:188m0c=831b454?::ma4?6=3fh:6=44}c;;<?6=;3:1<v*i9;c2?Mda12Bij95+9c8f?l?22900e4850;9leg<722wi55m50;;94?6|,o31n85Gbg;8Lg`33-3i6<5f1183>>o693:17d?=:188m45=831b9o4?::k6a?6=3`236=44oc294?=hj80;66sm99f94?5=83:p(k75a09Kfc?<@kl?7)7m:d9j=0<722c2:7>5;nca>5<<uk32=7>59;294~"a13h>7Eli9:Jab1=#1k0:7d??:188m47=831b=?4?::k27?6=3`?i6=44i4g94?=n010;66am0;29?jd62900qo762;297?6=8r.m57o>;I`e=>Nen=1/5o4j;h;6>5<<a0<1<75`ac83>>{e10<1<7750;2x c?=j<1Cnk74Hcd7?!?e281b==4?::k25?6=3`;96=44i0194?=n=k0;66g:e;29?l>?2900co>50;9lf4<722wi54950;194?6|,o31m<5Gbg;8Lg`33-3i6h5f9483>>o>>3:17bom:188yg?>j3:157>50z&e=?d23Ahm56Fmf59'=g<63`;;6=44i0394?=n9;0;66g>3;29?l3e2900e8k50;9j<=<722ei<7>5;n`2>5<<uk32o7>53;294~"a13k:7Eli9:Jab1=#1k0n7d7::188m<0=831dmo4?::a=d6=8331<7>t$g;9f0=Ojo30Doh;;%;a>4=n990;66g>1;29?l752900e<=50;9j1g<722c>i7>5;h:;>5<<gk:1<75`b083>>{e1h;1<7=50;2x c?=i81Cnk74Hcd7?!?e2l1b584?::k:2?6=3fki6=44}c;b1?6=13:1<v*i9;`6?Mda12Bij95+9c82?l772900e<?50;9j57<722c:?7>5;h7a>5<<a<o1<75f8983>>ie83:17bl>:188yg?f>3:1?7>50z&e=?g63Ahm56Fmf59'=g<b3`3>6=44i8494?=hik0;66sm9`c94??=83:p(k75b49Kfc?<@kl?7)7m:09j55<722c:=7>5;h31>5<<a891<75f5c83>>o2m3:17d67:188kg6=831dn<4?::a=dd=8391<7>t$g;9e4=Ojo30Doh;;%;a>`=n1<0;66g66;29?jge2900qo7nf;29=?6=8r.m57l:;I`e=>Nen=1/5o4>;h33>5<<a8;1<75f1383>>o6;3:17d;m:188m0c=831b454?::ma4?6=3fh:6=44}c;a4?6=;3:1<v*i9;c2?Mda12Bij95+9c8f?l?22900e4850;9leg<722wi5o:50;;94?6|,o31n85Gbg;8Lg`33-3i6<5f1183>>o693:17d?=:188m45=831b9o4?::k6a?6=3`236=44oc294?=hj80;66sm9c794?5=83:p(k75a09Kfc?<@kl?7)7m:d9j=0<722c2:7>5;nca>5<<uk3i57>59;294~"a13h>7Eli9:Jab1=#1k0:7d??:188m47=831b=?4?::k27?6=3`?i6=44i4g94?=n010;66am0;29?jd62900qo7ma;297?6=8r.m57o>;I`e=>Nen=1/5o4j;h;6>5<<a0<1<75`ac83>>{e1ko1<7750;2x c?=j<1Cnk74Hcd7?!?e281b==4?::k25?6=3`;96=44i0194?=n=k0;66g:e;29?l>?2900co>50;9lf4<722wi5oh50;194?6|,o31m<5Gbg;8Lg`33-3i6h5f9483>>o>>3:17bom:188yg?d;3:157>50z&e=?d23Ahm56Fmf59'=g<63`;;6=44i0394?=n9;0;66g>3;29?l3e2900e8k50;9j<=<722ei<7>5;n`2>5<<uk3h87>53;294~"a13k:7Eli9:Jab1=#1k0n7d7::188m<0=831dmo4?::a=f>=8331<7>t$g;9f0=Ojo30Doh;;%;a>4=n990;66g>1;29?l752900e<=50;9j1g<722c>i7>5;h:;>5<<gk:1<75`b083>>{e1j31<7=50;2x c?=i81Cnk74Hcd7?!?e2l1b584?::k:2?6=3fki6=44}c;``?6=13:1<v*i9;`6?Mda12Bij95+9c82?l772900e<?50;9j57<722c:?7>5;h7a>5<<a<o1<75f8983>>ie83:17bl>:188yg?dm3:1?7>50z&e=?g63Ahm56Fmf59'=g<b3`3>6=44i8494?=hik0;66sm9e094??=83:p(k75b49Kfc?<@kl?7)7m:09j55<722c:=7>5;h31>5<<a891<75f5c83>>o2m3:17d67:188kg6=831dn<4?::a=a5=8391<7>t$g;9e4=Ojo30Doh;;%;a>`=n1<0;66g66;29?jge2900qo7k7;29=?6=8r.m57l:;I`e=>Nen=1/5o4>;h33>5<<a8;1<75f1383>>o6;3:17d;m:188m0c=831b454?::ma4?6=3fh:6=44}c;g<?6=;3:1<v*i9;c2?Mda12Bij95+9c8f?l?22900e4850;9leg<722wi5k750;194?6|,o31m<5Gbg;8Lg`33-3i685f9483>>o>>3:17bom:188yg?a03:197>50z&e=?g43Ahm56Fmf59'=g<d3`3>6=44i8494?=n1>0;66g68;29?jge2900qo7ie;297?6=8r.m57o>;I`e=>Nen=1/5o4:;h;6>5<<a0<1<75`ac83>>{ej1o1<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk9>o7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th89i4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi?:<50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>9<:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=78;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<8883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm39g94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb2:e>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c1:4?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0=4<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a7<4=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f6?4290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg5><3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd41<0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e;0<1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:3<6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9247>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8544?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi?4o50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>7m:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=:e;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<5g83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm37294?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb242>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c156?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`026<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a732=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f602290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg51>3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4>>0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e;?21<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:<26=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9=m7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8:o4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi?;m50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>8k:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=9e;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<6g83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm36294?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb252>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c140?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`030<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a720=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f610290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg5003:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4?00;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e;>k1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:=i6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9<o7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8;i4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi?:k50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>9i:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=70;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<8083>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm39094?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb2:0>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c1;0?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0<0<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a7=0=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f6>0290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg5?i3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd40k0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e;1i1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:2o6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<ukhm<7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thij<4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722winhh50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vnl6::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qoo74;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygg??3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xdf0?0;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pln8883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sma9:94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{ei1h1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zjh2j6=4::183!`>21l0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;h`1>5<<gk:1<75rb`2`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}cc3f?6==3:1<v*i9;:e?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ci>7>5;n`3>5<<ukk;i7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thj<i4?:483>5}#n003j6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9jf7<722ei<7>5;|`b55<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::ae5`=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wim<<50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vnl?>:186>5<7s-l265h4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?ld52900co>50;9~fd73290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188ygg6;3:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qoo>6;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pln1483>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xdf910;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{ei8=1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sma0c94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb`3:>5<2290;w)h6:9d8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3`h96=44oc294?=zjh;h6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<ukk:n7>55;294~"a132m7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ka6?6=3fh;6=44}cc2a?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`b5a<72<0;6=u+f88;b>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831bn?4?::ma4?6=3thj>=4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wim<h50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::ae74=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~fd46290>6=4?{%d:>=`<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17dl=:188kg6=831vnl<;:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qoo=3;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygg5>3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xdf:<0;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pln2983>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sma3594?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{ei;k1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zjh826=4::183!`>21l0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;h`1>5<<gk:1<75rb`0`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}cc1f?6==3:1<v*i9;:e?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ci>7>5;n`3>5<<ukk9i7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thj>i4?:483>5}#n003j6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9jf7<722ei<7>5;|`b75<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::ae7`=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wim><50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vnl=>:186>5<7s-l265h4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?ld52900co>50;9~fd53290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188ygg4;3:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qoo<6;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pln3483>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xdf;10;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{ei:=1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sma2c94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb`1:>5<2290;w)h6:9d8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3`h96=44oc294?=zjh9h6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<ukk8n7>55;294~"a132m7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ka6?6=3fh;6=44}cc0a?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`b7a<72<0;6=u+f88;b>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831bn?4?::ma4?6=3thj8=4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wim>h50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::ae15=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~fd26290>6=4?{%d:>=`<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17dl=:188kg6=831vnl:::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qoo;4;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygg3?3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xdf<?0;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pln4883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sma5:94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{ei=h1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zjh>j6=4::183!`>21l0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;h`1>5<<gk:1<75rb`6g>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}cc7g?6==3:1<v*i9;:e?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ci>7>5;n`3>5<<ukk?j7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thj8h4?:483>5}#n003j6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9jf7<722ei<7>5;|`b14<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::ae06=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wim8=50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vnl;=:186>5<7s-l265h4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?ld52900co>50;9~fd32290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188ygg2<3:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qoo:7;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pln5783>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xdf=00;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{ei<21<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sma4`94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb`7b>5<2290;w)h6:9d8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3`h96=44oc294?=zjh?o6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<ukk>o7>55;294~"a132m7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ka6?6=3fh;6=44}cc6b?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`b1`<72<0;6=u+f88;b>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831bn?4?::ma4?6=3thj:<4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wim;>50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::ae35=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~fd05290>6=4?{%d:>=`<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17dl=:188kg6=831vnl8::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qoo94;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygg1?3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xdf>?0;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pln6883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sma7:94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{ei?h1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zjh<j6=4::183!`>21l0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;h`1>5<<gk:1<75rb`4g>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}cc5g?6==3:1<v*i9;:e?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ci>7>5;n`3>5<<ukk=j7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thj:h4?:483>5}#n003j6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9jf7<722ei<7>5;|`b34<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::ae26=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wim:=50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vnl9=:186>5<7s-l265h4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?ld52900co>50;9~fd12290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188ygg0<3:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qoo87;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pln7783>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xdf?00;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{ei>21<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sma6`94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb`5b>5<2290;w)h6:9d8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3`h96=44oc294?=zjh=o6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<ukk<o7>55;294~"a132m7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ka6?6=3fh;6=44}cc4b?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`b3`<72<0;6=u+f88;b>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831bn?4?::ma4?6=3thj4<4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wim5>50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::ae=5=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~fd>5290>6=4?{%d:>=`<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17dl=:188kg6=831vn4=i:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo7;4;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl64883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm95g94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb870>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c;6<?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`:1a<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a=34=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f<00290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg?1k3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd>?80;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e1><1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj0=i6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk33<7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th2484?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi55o50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn46i:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo764;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl69883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm98g94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb8c0>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c;b<?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`:ea<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a=g4=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f<d0290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg?ek3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd>k80;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e1j<1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj0ii6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk3o<7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th2h84?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi5io50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn4h9:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo7i7;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pln0583>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xdf890;684?:1y'b<<?k2Bij45Gbg68 <d=82c>57>5;h7a>5<<a<l1<75f8983>>ie83:17pln0083>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xd>no0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{ei991<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sma1094?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rbc:g>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c`:4?6==3:1<v*i9;c0?Mda12Bij95+9c80?l?22900e4850;9j=2<722c247>5;nca>5<<ukh2=7>55;294~"a13k87Eli9:Jab1=#1k0>;6g65;29?l?12900e4950;9j==<722ejn7>5;|`a=7<72<0;6=u+f88b7>Nen01Cnk:4$8`92>o>=3:17d79:188m<1=831b554?::mbf?6=3thi5>4?:483>5}#n00j?6Fmf89Kfc2<,0h186g65;29?l?12900e4950;9j==<722ejn7>5;|`a=1<72<0;6=u+f88b7>Nen01Cnk:4$8`96>o>=3:17d79:188m<1=831b554?::mbf?6=3thi584?:483>5}#n00j?6Fmf89Kfc2<,0h1>6g65;29?l?12900e4950;9j==<722ejn7>5;|`a=3<72<0;6=u+f88b7>Nen01Cnk:4$8`96>o>=3:17d79:188m<1=831b554?::mbf?6=3thi5:4?:483>5}#n00j?6Fmf89Kfc2<,0h1>6g65;29?l?12900e4950;9j==<722ejn7>5;|`a=<<72;0;6=u+f88:g>Nen01Cnk:4i8694?=hik0;66smbec94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rbc`5>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygde;3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbc`b>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygde?3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbc`f>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygdej3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbca1>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygden3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbca5>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygdd;3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbcab>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygdd?3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbcaf>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygddj3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbcf2>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygde=3:1>7>50z&e=?g73Ahm56Fmf59'=g<23`3>6=44o``94?=zjkh26=4=:183!`>2h:0Doh6;I`e0>">j3?0e4;50;9leg<722winoj50;094?6|,o31m=5Gbg;8Lg`33-3i685f9483>>ifj3:17plmc083>7<729q/j44n0:Jab<=Ojo>0(4l55:k:1?6=3fki6=44}c``1?6=:3:1<v*i9;c3?Mda12Bij95+9c86?l?22900cll50;9~fge>29096=4?{%d:>d6<@kl27Eli4:&:f?3<a0?1<75`ac83>>{ejjn1<7<50;2x c?=i91Cnk74Hcd7?!?e2<1b584?::mbf?6=3thih=4?:383>5}#n00j<6Fmf89Kfc2<,0h196g65;29?jge2900qolm4;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygde03:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qolmc;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygdd83:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qoll4;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygdd03:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qollc;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygddn3:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qo7j6;297?6=8r.m57li8:Jab<=Ojo>0e8j50;9j=a<722ejn7>5;|`:a6<72=0;6=u+f88b2>Nen01Cnk:4i4f94?=n000;66gm3;29?j?b2900qo7ja;297?6=8r.m57li8:Jab<=Ojo>0e8j50;9j=a<722ejn7>5;|`:a2<72=0;6=u+f88b2>Nen01Cnk:4i4f94?=n000;66gm3;29?j?b2900qo7je;297?6=8r.m57li8:Jab<=Ojo>0e8j50;9j=a<722ejn7>5;|`:ag<72=0;6=u+f88b2>Nen01Cnk:4i4f94?=n000;66gm3;29?j?b2900qo7i1;297?6=8r.m57li8:Jab<=Ojo>0e8j50;9j=a<722ejn7>5;|`:a0<72;0;6=u+f88b4>Nen01Cnk:4$8`91>o>=3:17bom:188yg?b13:1>7>50z&e=?g73Ahm56Fmf59'=g<23`3>6=44o``94?=zj0oo6=4=:183!`>2h:0Doh6;I`e0>">j3?0e4;50;9leg<722wi5k>50;094?6|,o31m=5Gbg;8Lg`33-3i685f9483>>ifj3:17pl6e583>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xd>m10;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pl6eb83>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xd>mo0;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pl61383>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb830>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`:4c<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f<77290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd>900;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj0;o6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg?5m3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd>:o0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e1;n1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj09=6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk38;7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th2?84?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi5<l50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a=4e=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi5<k50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a=4`=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi5<650;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn4?>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo7>6;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl61683>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm90694?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb836>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c;2e?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;a0<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f=c1290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd?m;0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj1o86=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th3in4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn5h?:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk3;=7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th2<?4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi5=>50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn4>6:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo7?a;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl60983>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm8dg94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e0ll1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm8g394?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e0o81<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm8d`94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb9g7>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c:f=?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;ad<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a<`1=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f=c?290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg>bl3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd?j10;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj1h26=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th3n84?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn5l9:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl7bg83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb9a0>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo6k4;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl7d483>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm8e194?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb9f`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c:g`?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;`g<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a<f7=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi4n<50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a<f2=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi4n;50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a<gc=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f=d0290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg>ek3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd?jm0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e0kk1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj1hi6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk2h<7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th34o4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn56l:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl78983>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb9::>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`;=7<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f=?129096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c:b3?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;e=<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a<d0=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f=ga290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg>e83:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd?il0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e00>1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm88794?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e00=1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm88:94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e00;1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj12j6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk23j7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th35=4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi45j50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn56j:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo663;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl75d83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb97e>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`;1g<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f=3d290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd?><0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj1<26=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg>0i3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd??k0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e0>31<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj1296=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk23?7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th34<4?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi4;950;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a<3>=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi4;o50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a<3d=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi4;:50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn5;k:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo692;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl76283>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm87294?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb942>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c:52?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;74<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f=55290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd?:l0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj18m6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th3?54?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn5=l:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk2?h7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th38h4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi49m50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn5;::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo6:6;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl75583>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm82c94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e0:h1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm82f94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e0:o1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm82594?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb913>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c:01?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;73<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a<65=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f=53290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg>413:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd?8=0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj1:>6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th3<<4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn5>=:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl70c83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb92e>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo6=0;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl72083>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm80d94?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb90;>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c:1=?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;62<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a<5b=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi4=k50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a<46=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi4<?50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a<5g=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f=64290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg>703:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd?800;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e09<1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj1:<6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk2;o7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<h:4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn:j7:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl8d583>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb6f6>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`4``<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f2c529096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c5e7?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`4b1<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a3c4=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f2`e290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg1ak3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd0nh0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e?l:1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm7d394?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e?l91<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm7d694?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e?mn1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj>n=6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk=on7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<hn4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi;i750;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn:jn:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo9kf;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl8a`83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb6ca>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`4e2<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f2g?290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd0j80;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj>h>6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg1d>3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd0k>0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e?j?1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj>in6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk=hj7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<oi4?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi;o=50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a3g2=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi;o850;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a3g1=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi;o>50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn:o6:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo9ne;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl8ag83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm7`a94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb6cg>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c5a6?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`43a<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f21b290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd0?h0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj>=i6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th<494?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn:67:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk=257>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<5l4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi;4650;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn:o>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo9n2;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl8a183>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm79494?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e?1=1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm79;94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e?1k1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm79194?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb65`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c5;5?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`4<7<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a32`=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f2>7290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg1?=3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd0=90;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj>?:6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th<8i4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn::j:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl85683>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb67a>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo99c;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl86e83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm77`94?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb657>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c541?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`436<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a30?=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi;8o50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a30e=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi;8j50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a300=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f22a290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg12<3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd0=<0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e?<81<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj>?86=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk=>47>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<>>4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn:<;:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl82183>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb602>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`46d<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f24b29096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c50b?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`405<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a36c=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f220290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg1303:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd0<?0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e?;i1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm73f94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e?;l1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm72294?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e?;31<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj>896=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk=9;7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<>54?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi;?;50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn:<9:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo9=b;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl9f783>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb7d4>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`5b6<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f3`3290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd1nm0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj>::6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg16:3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd09:0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e?8;1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj>;j6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk=:n7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<=44?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi:kh50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a356=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi;=<50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a355=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi:km50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn;h::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo8ia;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl9fc83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm6g:94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb7d:>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c4ea?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`5g<<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f3ef290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd1k?0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj?i<6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th=h=4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn;j;:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk<n97>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th=i;4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi:h:50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn;kk:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo8je;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl9eb83>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm6e094?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e>m91<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm6e794?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e>m<1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm6bd94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb7a;>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c4``?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`5g`<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a2fd=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f3ed290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg0c93:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd11j0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj?3o6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th=544?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn;7n:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl9a283>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb7c4>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo8m8;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl9b883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm6c594?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb7a3>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c4`5?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`5fc<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a2d3=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi:l850;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a2d>=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi:l750;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a2d4=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f3?e290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg0f83:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd1i80;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e>0o1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj?3m6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk<j87>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th=:k4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn;9?:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl96b83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb74g>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`533<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f31f29096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c4;f?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`5<f<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a2=g=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f3?4290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg0><3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd11;0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e>>21<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm66;94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e>>h1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm66a94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e>>?1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj?<n6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk<<?7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th=;94?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi::?50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn;9=:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo887;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl94383>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb760>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`57c<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f327290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd1<00;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj?>o6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg02m3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd1=o0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e><n1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj?<=6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk<=;7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th=:84?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi:9l50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a21e=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi:9k50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a21`=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi:9650;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn;:>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo8;6;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl94683>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm65694?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb766>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c47e?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`550<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f371290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd19;0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj?;86=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th==n4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn;<?:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk<8=7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th=??4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi:>>50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn;=6:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo8<a;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl93983>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm60g94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e>8l1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm63394?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e>;81<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm60`94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb737>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c42=?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`55d<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a241=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f37?290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg06l3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2m10;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj<o26=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th>i84?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn8k9:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl:eg83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb4d0>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo8?4;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl90483>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm61194?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb72`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c43`?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`54g<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a1c7=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi9k<50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a1c2=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi9k;50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a1`c=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f0c0290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg3bk3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2mm0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e=lk1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj<oi6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk?m<7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th>no4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn8ll:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl:b983>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb4`:>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`6g7<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f0e129096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c7g3?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`6`=<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a1a0=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f0ba290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg3b83:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2ll0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e=j>1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm5b794?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e=j=1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm5b:94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e=j;1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj<hj6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk?ij7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th>o=4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi9oj50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn8lj:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo;l3;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl:8d83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb4:e>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`6<g<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f0>d290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd21<0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj<326=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg3fi3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2ik0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e=h31<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj<h96=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk?i?7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th>n<4?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi94950;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a1<>=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi94o50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a1<d=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi94:50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn86k:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo;62;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl:9283>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm58294?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb4;2>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c7:2?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`624<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f005290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd2=l0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj<?m6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th>:54?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn88l:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk?<h7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th>;h4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi9:m50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn86::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo;76;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl:8583>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm57c94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e=?h1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm57f94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e=?o1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm57594?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb443>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c751?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`623<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a135=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f003290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg3113:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2;=0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj<9>6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th>?<4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn8==:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl:3c83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb41e>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo;:0;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl:5083>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm55d94?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb47;>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c76=?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`612<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a16b=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi9>k50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a116=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi99?50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a16g=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f054290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg3403:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2;00;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e=:<1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj<9<6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk?8o7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th><:4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn8>7:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl:0583>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb426>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`64`<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f07529096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c717?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`661<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a174=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f04e290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg35k3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2:h0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e=8:1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm50394?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e=891<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm50694?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e=9n1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj<:=6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk?;n7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th><n4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi9=750;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn8>n:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo;?f;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;d`83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb5fa>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`7`2<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f1b?290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd3m80;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj=o>6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg2a>3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd3n>0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e<o?1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj=ln6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk>mj7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?ji4?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi8h=50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a0`2=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi8h850;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a0`1=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi8h>50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn9j6:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo:ke;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;dg83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm4ea94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb5fg>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c6f6?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`7ea<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f1gb290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd3ih0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj=ki6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th?n94?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn9l7:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk>h57>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?ol4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi8n650;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn9j>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo:k2;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;d183>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm4c494?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e<k=1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm4c;94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e<kk1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm4c194?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb5c`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c6a5?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`7f7<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a0d`=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f1d7290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg2e=3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd3090;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj=2:6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th?;i4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn99j:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl;8683>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb5:a>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo:6c;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;9e83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm48`94?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb5c7>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c6b1?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`7e6<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a0=?=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi85o50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a0=e=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi85j50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a0=0=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f11a290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg2?<3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd30<0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e<181<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj=286=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk>347>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?9>4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn9;;:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl;5183>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb572>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`71d<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f13b29096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c65b?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`735<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a03c=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f110290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg2003:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd3??0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e<<i1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm44f94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e<<l1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm47294?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e<<31<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj=?96=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk>>;7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?954?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi88;50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn9;9:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo::b;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;2783>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb504>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`766<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f143290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd3:m0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj=9:6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg23:3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd3<:0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e<=;1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj=>j6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk>?n7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?844?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi8?h50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a066=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi8><50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a065=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi8?m50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn9<::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo:=a;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;2c83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm43:94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb50:>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c61a?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0b<<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f6`f290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd4n?0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj:l<6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th?<=4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn9>;:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk>:97>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?=;4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi8<:50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn9?k:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo:>e;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;1b83>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm41094?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e<991<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm41794?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e<9<1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm3gd94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb2d;>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c1e`?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0b`<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a7cd=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f6`d290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg2793:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4kj0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj:io6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th8o44?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn>mn:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl<d283>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb2f4>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo=j8;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<e883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm3d594?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb2d3>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c1e5?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0ac<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a7a3=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi?i850;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a7a>=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi?i750;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a7a4=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f6ee290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg5c83:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4l80;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e;jo1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:im6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9o87>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th85k4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn>o?:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl<9b83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb2;g>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`0e3<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f6gf29096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c1af?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0ff<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a7gg=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f6e4290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg5d<3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4k;0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e;h21<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm3`;94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e;hh1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm3`a94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e;h?1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:3n6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9j?7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8m94?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi?l?50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>o=:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=n7;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl=c583>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb3a6>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`1ga<72;0;6=u+f88:g>Nen01Cnk:4i8694?=hik0;66sm2bc94?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c0`f?6==3:1<v*i9;:`?Mda12Bij95+9c83?l3>2900e8l50;9j1c<722c347>5;n`3>5<<uk8ho7>55;294~"a132h7Eli9:Jab1=#1k0;7d;6:188m0d=831b9k4?::k;<?6=3fh;6=44}c0`3?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`1g3<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a6f>=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f7e>290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg4e93:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e:k81<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk8im7>52;294~"a133h7Eli9:Jab1=n1=0;66anb;29?xd5j>0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj;h36=4::183!`>21i0Doh6;I`e0>">j3:0e8750;9j1g<722c>j7>5;h:;>5<<gk:1<75rb3`:>5<2290;w)h6:9a8Lg`>3Ahm86*6b;28m0?=831b9o4?::k6b?6=3`236=44oc294?=zj;h?6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk8i?7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th9n84?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi>o850;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn?6m:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl=8b83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb3;7>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo<61;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm28094?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e:091<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm29g94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb3:g>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c0;b?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`1=5<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a62>=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg4013:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e:1;1<7<50;2x c?=1j1Cnk74Hcd7?l?32900cll50;9~f71b290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd5?o0;684?:1y'b<<?k2Bij45Gbg68 <d=82c>57>5;h7a>5<<a<l1<75f8983>>ie83:17pl=8183>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xd5?k0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e:>k1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj;=h6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk8<h7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th9:84?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn?89:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl=6d83>7<729q/j446c:Jab<=Ojo>0e4:50;9leg<722wi>;l50;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo<9c;291?6=8r.m576l;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f5g83>>o?03:17bl?:188yg41l3:197>50z&e=?>d3Ahm56Fmf59'=g<73`?26=44i4`94?=n=o0;66g78;29?jd72900qo<98;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl=6683>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm27;94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb34b>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c066?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a605=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg42j3:1>7>50z&e=??d3Ahm56Fmf59j=1<722ejn7>5;|`11=<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f73>290>6=4?{%d:>=e<@kl27Eli4:&:f?6<a<31<75f5c83>>o2n3:17d67:188kg6=831vn?;n:186>5<7s-l265m4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g:f;29?l>?2900co>50;9~f732290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg42<3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd5=?0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e:<=1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj;9m6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th98=4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn?:7:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk8?97>54;294~"a13k97Eli9:Jab1=#1k0>m6g65;29?l?12900e4950;9leg<722wi>9850;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a611=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi>9<50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn?:>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo<;3;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl=4583>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm23a94?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c01`?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a663=8381<7>t$g;9=f=Ojo30Doh;;h;7>5<<ghh1<75rb311>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`176<72<0;6=u+f88;g>Nen01Cnk:4$8`94>o213:17d;m:188m0`=831b454?::ma4?6=3th9?94?:483>5}#n003o6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e8h50;9j<=<722ei<7>5;|`16c<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a67c=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f757290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg4493:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd5900;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj;;j6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th9>?4?:383>5}#n002o6Fmf89Kfc2<a0>1<75`ac83>>{e:8l1<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk89<7>55;294~"a132h7Eli9:Jab1=#1k0;7d;6:188m0d=831b9k4?::k;<?6=3fh;6=44}c015?6==3:1<v*i9;:`?Mda12Bij95+9c83?l3>2900e8l50;9j1c<722c347>5;n`3>5<<uk8:o7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th9=o4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi><j50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn??j:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo<?6;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm21594?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c03b?6=:3:1<v*i9;;`?Mda12Bij95f9583>>ifj3:17pl=0b83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb32g>5<2290;w)h6:9a8Lg`>3Ahm86*6b;28m0?=831b9o4?::k6b?6=3`236=44oc294?=zj;:n6=4::183!`>21i0Doh6;I`e0>">j3:0e8750;9j1g<722c>j7>5;h:;>5<<gk:1<75rb32:>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c03<?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`14d<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a65d=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f4`4290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd6n=0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj8lh6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg7a13:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e9ok1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm1g`94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e9o<1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj8l>6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk;m;7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th:j54?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi=h>50;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo?j1;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm1d;94?4=83:p(k759b9Kfc?<@kl?7d7;:188kdd=831vn<k9:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl>e683>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xd6m10;684?:1y'b<<?k2Bij45Gbg68 <d=82c>57>5;h7a>5<<a<l1<75f8983>>ie83:17pl>e283>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm1d094?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb0g7>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c3f1?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`2fd<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f4de290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd6k:0;6?4?:1y'b<<>k2Bij45Gbg68m<2=831dmo4?::a5f6=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg7d93:197>50z&e=?>d3Ahm56Fmf59'=g<73`?26=44i4`94?=n=o0;66g78;29?jd72900qo?l2;291?6=8r.m576l;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f5g83>>o?03:17bl?:188yg7el3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd6jj0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e9ko1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj8hm6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk;j;7>54;294~"a13k97Eli9:Jab1=#1k0>m6g65;29?l?12900e4950;9leg<722wi=l650;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo?m0;296?6=8r.m577l;I`e=>Nen=1b594?::mbf?6=3th:mi4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn<oj:186>5<7s-l265m4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g:f;29?l>?2900co>50;9~f4ga290>6=4?{%d:>=e<@kl27Eli4:&:f?6<a<31<75f5c83>>o2n3:17d67:188kg6=831vn<on:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo?n9;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl>ac83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm1`a94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb0;7>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`2=0<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f4?c29096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c3:e?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a5<d=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi=4m50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a5<1=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f4?1290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg7>03:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd6100;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e91;1<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk;3>7>54;294~"a13k97Eli9:Jab1=#1k0>m6g65;29?l?12900e4950;9leg<722wi=5o50;094?6|,o315n5Gbg;8Lg`33`3?6=44o``94?=zj82<6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th:454?:483>5}#n003o6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e8h50;9j<=<722ei<7>5;|`2<<<72<0;6=u+f88;g>Nen01Cnk:4$8`94>o213:17d;m:188m0`=831b454?::ma4?6=3th:494?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi=5=50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn<6::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo?76;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl>6d83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb04e>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`232<72;0;6=u+f88:g>Nen01Cnk:4i8694?=hik0;66sm16694?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c341?6==3:1<v*i9;:`?Mda12Bij95+9c83?l3>2900e8l50;9j1c<722c347>5;n`3>5<<uk;<:7>55;294~"a132h7Eli9:Jab1=#1k0;7d;6:188m0d=831b9k4?::k;<?6=3fh;6=44}c345?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`235<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a524=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f414290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg72j3:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e9<i1<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk;=87>52;294~"a133h7Eli9:Jab1=n1=0;66anb;29?xd6>80;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj8<96=4::183!`>21i0Doh6;I`e0>">j3:0e8750;9j1g<722c>j7>5;h:;>5<<gk:1<75rb040>5<2290;w)h6:9a8Lg`>3Ahm86*6b;28m0?=831b9o4?::k6b?6=3`236=44oc294?=zj8?n6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk;>h7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th:9k4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi=;>50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn<:7:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl>4883>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb072>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo?;e;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm15d94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e9<:1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm15`94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb06b>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c37g?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`20a<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a563=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg74>3:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e9:o1<7<50;2x c?=1j1Cnk74Hcd7?l?32900cll50;9~f45e290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd6;j0;684?:1y'b<<?k2Bij45Gbg68 <d=82c>57>5;h7a>5<<a<l1<75f8983>>ie83:17pl>3e83>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xd6;10;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e9:=1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj8926=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk;8m7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th:>?4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn<<<:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl>2c83>7<729q/j446c:Jab<=Ojo>0e4:50;9leg<722wi=?650;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo?=9;291?6=8r.m576l;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f5g83>>o?03:17bl?:188yg75i3:197>50z&e=?>d3Ahm56Fmf59'=g<73`?26=44i4`94?=n=o0;66g78;29?jd72900qo?=5;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl>2583>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm13494?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb004>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c33b?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a546=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg7603:1>7>50z&e=??d3Ahm56Fmf59j=1<722ejn7>5;|`250<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f471290>6=4?{%d:>=e<@kl27Eli4:&:f?6<a<31<75f5c83>>o2n3:17d67:188kg6=831vn<?8:186>5<7s-l265m4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g:f;29?l>?2900co>50;9~f475290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg7693:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd69:0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e98>1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:>26=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th88l4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn>;=:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk9?j7>54;294~"a13k97Eli9:Jab1=#1k0>m6g65;29?l?12900e4950;9leg<722wi?8>50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a707=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi?9m50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>:m:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=;d;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<4d83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm32494?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c103?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a76`=8381<7>t$g;9=f=Ojo30Doh;;h;7>5<<ghh1<75rb21`>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`07a<72<0;6=u+f88;g>Nen01Cnk:4$8`94>o213:17d;m:188m0`=831b454?::ma4?6=3th8?h4?:483>5}#n003o6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e8h50;9j<=<722ei<7>5;|`07<<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a76>=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f65f290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg54j3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4::0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj:8?6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th8>n4?:383>5}#n002o6Fmf89Kfc2<a0>1<75`ac83>>{e;;31<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk99m7>55;294~"a132h7Eli9:Jab1=#1k0;7d;6:188m0d=831b9k4?::k;<?6=3fh;6=44}c11f?6==3:1<v*i9;:`?Mda12Bij95+9c83?l3>2900e8l50;9j1c<722c347>5;n`3>5<<uk99:7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8>84?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi??950;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn><7:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=>0;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm30394?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c12=?6=:3:1<v*i9;;`?Mda12Bij95f9583>>ifj3:17pl<1783>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb234>5<2290;w)h6:9a8Lg`>3Ahm86*6b;28m0?=831b9o4?::k6b?6=3`236=44oc294?=zj:;36=4::183!`>21i0Doh6;I`e0>">j3:0e8750;9j1g<722c>j7>5;h:;>5<<gk:1<75rb230>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c126?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`051<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a743=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f7`c290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd5nl0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj::=6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg57;3:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e;9>1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm31794?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e;9:1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj;lm6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9;=7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8<?4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi>ho50;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo<jb;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm2g194?4=83:p(k759b9Kfc?<@kl?7d7;:188kdd=831vn?h?:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl=f083>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xd5n;0;684?:1y'b<<?k2Bij45Gbg68 <d=82c>57>5;h7a>5<<a<l1<75f8983>>ie83:17pl=ee83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm2da94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb3gf>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c0fb?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`1`2<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f7b?290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd5m90;6?4?:1y'b<<>k2Bij45Gbg68m<2=831dmo4?::a6ab=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg4cm3:197>50z&e=?>d3Ahm56Fmf59'=g<73`?26=44i4`94?=n=o0;66g78;29?jd72900qo<kf;291?6=8r.m576l;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f5g83>>o?03:17bl?:188yg4ci3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd5l00;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e:mh1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj;nh6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk82i7>54;294~"a13k97Eli9:Jab1=#1k0>m6g65;29?l?12900e4950;9leg<722wi>4h50;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo<n7;296?6=8r.m577l;I`e=>Nen=1b594?::mbf?6=3th9m94?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn?o::186>5<7s-l265m4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g:f;29?l>?2900co>50;9~f7g1290>6=4?{%d:>=e<@kl27Eli4:&:f?6<a<31<75f5c83>>o2n3:17d67:188kg6=831vn?o>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo<n0;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl=a383>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm2`194?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb0ag>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`2g`<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f4b129096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c3g7?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a5a2=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi=i;50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a5a6=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f4ea290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg7c93:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd6l;0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{enj0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zjon1<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk;;97>52;294~"a133h7Eli9:Jab1=n1=0;66anb;29?xd68;0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj8:86=4::183!`>21i0Doh6;I`e0>">j3:0e8750;9j1g<722c>j7>5;h:;>5<<gk:1<75rb027>5<2290;w)h6:9a8Lg`>3Ahm86*6b;28m0?=831b9o4?::k6b?6=3`236=44oc294?=zjol1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zjoo1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj8:;6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk;;=7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thim=4?:683>5}#n00j96Fmf89Kfc2<,0h1h6g65;29?l?12900e4950;9j==<722c257>5;h;b>5<<ghh1<75rbcc0>5<0290;w)h6:`78Lg`>3Ahm86*6b;f8m<3=831b5;4?::k:3?6=3`336=44i8;94?=n1h0;66anb;29?xde1h0;6:4?:1y'b<<f=2Bij45Gbg68 <d=l2c297>5;h;5>5<<a0=1<75f9983>>o>13:17d7n:188kdd=831vno7m:184>5<7s-l26l;4Hcd:?Mda<2.2n7j4i8794?=n1?0;66g67;29?l??2900e4750;9j=d<722ejn7>5;|`a=`<72?0;6=u+f88b0>Nen01Cnk:4$8`9=5=n1<0;66g66;29?l?02900e4650;9j=<<722ejn7>5;|`a=c<72>0;6=u+f88b1>Nen01Cnk:4$8`9<g=n1<0;66g66;29?l?02900e4650;9j=<<722c2m7>5;nca>5<<ukhj=7>57;294~"a13k>7Eli9:Jab1=#1k03n6g65;29?l?12900e4950;9j==<722c257>5;h;b>5<<ghh1<75rbcc1>5<1290;w)h6:`68Lg`>3Ahm86*6b;37?l?22900e4850;9j=2<722c247>5;h;:>5<<ghh1<75rbc;g>5<1290;w)h6:`68Lg`>3Ahm86*6b;d8m<3=831b5;4?::k:3?6=3`336=44i8;94?=hik0;66smb8a94?1=83:p(k75a49Kfc?<@kl?7)7m:e9j=0<722c2:7>5;h;4>5<<a021<75f9883>>o>i3:17bom:188yv72290?wS?:;<330?3>34;;>77:;<331??33ty::7>54z\22>;69>0>563>148:1>;6910286s|1683>1}Y9>16=?o5589>57>=1<16=?l5959~w4>=83>pR<64=01g>0?<589i64;4=01f><2<uz;26=4;{_3:?87283?270?;e;;6?872933?7p}>a;290~X6i27::>4:9:?224<>=27::9464:p5g<72=qU=o5216491<=:9>>158521659=1=z{8i1<7:t^0a894>>2<301<68:87894>f20>0q~?k:187[7c34;2o7;6;<3:e??234;2h77;;|q2a?6=<rT:i63>ag86=>;6im02963>b18:0>{t9o0;69uQ1g9>5f4==016=n>5949>5f5=1=1v?>50;6xZ76<58n>6874=0f0><3<58n=64:4}r02>5<3sW8:70?j8;7:?87b>33>70?j9;;7?xu5:3:18vP=2:?2bg<2127:j4465:?2bf<><2wx>>4?:5y]66=::9o1945221a9=0=::9l1595rs3694?2|V;>01?<>:4;8977a20?01?<=:868yv42290?wS<:;<000?3>3488>77:;<001??33ty9:7>54z\12>;5<>0>563=448:1>;5<10286s|2683>1}Y:>16>8o5589>60>=1<16>8l5959~w7>=83>pR?64=34g>0?<5;<i64;4=34f><2<uz826=4;{_0:?84?83?270<8e;;6?84?933?7p}=a;290~X5i2795>4:9:?1=4<>=27959464:p6g<72=qU>o522`491<=::h>158522`59=1=z{;i1<7:t^3a897d>2<301?l8:87897df20>0q~<j:187[4b348ho7;6;<0`e??2348hh77;;|q1b?6=<rT9j63=dg86=>;5lm02963=e18:0>{t;90;69uQ319>6c4==016>k>5949>6c5=1=1v>?50;6xZ67<5::>6874=220><3<5::=64:4}r11>5<3sW9970=>8;7:?856>33>70=>9;;7?xu4;3:18vP<3:?06g<21278>4465:?06f<><2wx?94?:5y]71=:;:o1945232a9=0=:;:l1595rs2794?2|V:?01>;>:4;8962a20?01>;=:868yv512909wS=9;<16`?d73ty8;7>52z\03>;4=o0i<6s|3983>7}Y;116?;?5b19~w6?=838pR>74=240>g6<uz9j6=4={_1b?851=3h;7p}<b;296~X4j278::4m0:p7f<72;qU?n5237;9f5=z{:n1<7<t^2f8960e2k:0q~=j:181[5b349=h7l?;|q0b?6=:rT8j63<6g8a4>{t<90;6?uQ419>727=j91v9?50;0xZ17<5:=86o>4}r61>5<5sW>970=85;`3?xu3;3:1>vP;3:?032<e82wx894?:3y]01=:;>31n=5rs5794?4|V=?01>9m:c28yv212909wS:9;<14`?d73ty?;7>52z\73>;4?o0i<6s|4983>7}Y<116?5?5b19~w1?=838pR974=2:0>g6<uz>j6=4={_6b?85?=3h;7p};b;296~X3j2784:4m0:p0f<72;qU8n5239;9f5=z{=n1<7<t^5f896>e2k:0q~:i:181[2a3493h7l?;|q64?6=:rT><63<8g8a4>{t=80;6?uQ509>7<7=j91v8<50;0xZ04<5:386o>4}r70>5<5sW?870=65;`3?xu2<3:1>vP:4:?0=2<e82wx984?:3y]10=:;031n=5rs4494?4|V<<01>7m:c28yv3b290::nuQ5d9>e56==016m=?5589>=c`==016m==5589>e54==0165k85589>=c1==0165io5589>=a3==0165i>5589>=fd==0165n85589>=f7==0165om5589>=g1==0165o<5589>=db==0165l65589>=d5==01654k5589>=<?==01654:5589>==`==01655o5589>==3==01655>5589>=2d==0165:85589>=27==0165;m5589>=31==0165;<5589>=0b==0165865589>=05==01659k5589>=1?==01659:5589>=6`==016m9?5589>e6`==016m>j5589>e6d==016m>75589>e61==016m>;5589>e65==016m>?5589>e7`==016m?j5589>e7d==016m?75589>e71==016m?;5589>e75==016m??5589>e4`==016m<j5589>e4d==016m<75589>e41==016m<;5589>e45==016m<?5589>e5`==016m=j5589>e5d==016m5o5589>e=>==016m585589>e=2==0165hh5589>=`e==0165h65589>=`2==0165<65589>=4`==0165<k5589>=60==0165>95589>=63==0165?k5589>=7`==0165?j5589><`d==0164k<5589><c7==0165=75589>=5g==0165=65589>=57==0165=<5589>=56==0164ok5589><f3==0164n:5589><ae==0164ij5589><ad==0164i:5589><a3==0164i=5589><<7==0164465589><<1==0164lh5589><g6==0164lk5589><d1==0164l65589><d0==0164;:5589><3d==0164;o5589><=4==01645=5589><=7==0164:o5589><2d==0164:75589><61==0164>k5589><6b==01648;5589><00==01648:5589><1b==01649k5589><1e==0164=o5589><47==0164<>5589><7>==0164?75589><71==0164?>5589><77==0164<h5589>3ab==016;h:5589>3`5==016;kl5589>3ce==016;ko5589>3c5==016;k:5589>3c4==016;o>5589>3g1==016;o85589>3fc==016;nh5589>3fb==016;n85589>3f1==016;n;5589>3=5==016;5o5589>3=?==016;l?5589>3d4==016;l>5589>3<?==016;4o5589>3<>==016;885589>30b==016;8m5589>322==016;:;5589>325==016;;m5589>33b==016;;l5589>37?==016;>>5589>37`==016;995589>31>==016;985589>36`==016;9>5589>36c==016:km5589>355==016;=<5589>34g==016;<l5589>34?==016;<<5589>345==016;<?5589>2f`==016:i85589>2a3==016:hj5589>2`c==016:hm5589>2`3==016:h85589>2`2==016:l<5589>2d?==016:l65589>2f6==016:n?5589>2g`==016:o65589>2g?==016:o95589>223==016::m5589>22d==016:4=5589>2<2==016:4<5589>2=d==016:5m5589>2=g==016:965589>21`==016:9k5589>230==016:;95589>233==016:8k5589>20`==016:8j5589>24d==016:?<5589>277==016:>75589>26g==016:>65589>267==016:><5589>266==0169hk5589>1c3==0169k:5589>25e==016:=j5589>25d==016:=:5589>253==016:==5589>1f7==0169n65589>1f1==0169ih5589>1`6==0169ik5589>1a1==0169i65589>1a0==01694:5589>1<d==01694o5589>1g4==0169o=5589>1g7==0169lo5589>1dd==0169l75589>131==0169;k5589>13b==01695;5589>1=0==01695:5589>12b==0169:k5589>12e==0169>o5589>117==01699>5589>10>==0169875589>101==01698>5589>107==01699h5589>15b==0169<:5589>145==0169?l5589>17e==0169?o5589>175==0169?:5589>174==0168h>5589>0`1==0168h85589>0cc==0168kh5589>0cb==0168k85589>0c1==0168k;5589>0g5==0168oo5589>0g?==0168i?5589>0a4==0168i>5589>0f?==0168no5589>0f>==0168585589>0=b==01685m5589>0d2==0168l;5589>0d5==01684m5589>0<b==01684l5589>00?==0168;>5589>00`==0168:95589>02>==0168:85589>03`==0168:>5589>03c==0168?m5589>065==0168><5589>01g==01689l5589>01?==01689<5589>015==01689?5589>7c`==0168=85589>053==0168<j5589>04c==0168<m5589>043==0168<85589>042==016?i<5589>7a?==016?i65589>7c6==016?k?5589>7``==016?h65589>7`?==016?h95589>7d3==016?lm5589>7dd==016?n=5589>7f2==016?n<5589>7gd==016?om5589>7gg==01v;?50;03b~X1927i4i4:9:?b41<2127j4>4:9:?b<7<2127j4<4:9:?b<5<2127j;k4:9:?b3`<2127j;i4:9:?b3f<2127j;o4:9:?b3d<2127j;44:9:?b3=<2127j;:4:9:?b33<2127j;84:9:?b31<2127j;>4:9:?b37<2127j;<4:9:?b35<2127j:k4:9:?b2`<2127j:i4:9:?b2f<2127j:o4:9:?b2d<2127j:44:9:?b2=<2127j::4:9:?b23<2127j:84:9:?b21<2127j:>4:9:?b27<2127j:<4:9:?b25<2127j9k4:9:?b1`<2127j9i4:9:?b1f<2127j9o4:9:?b1d<2127j944:9:?b1=<2127j9:4:9:?b13<2127j984:9:?b11<2127j9>4:9:?b17<2127j9<4:9:?b15<2127j8k4:9:?b0`<2127j8i4:9:?b0f<2127j8o4:9:?b0d<2127j844:9:?b0=<2127j8:4:9:?b03<2127j884:9:?b01<2127j8>4:9:?b05<2127j?h4:9:?b7f<2127j?l4:9:?b7=<2127j?;4:9:?b71<2127j??4:9:?b75<2127j>h4:9:?b6f<2127j>l4:9:?b6=<2127j>;4:9:?b61<2127j>?4:9:?b65<2127j=h4:9:?b5f<2127j=l4:9:?b5=<2127j=;4:9:?b51<2127j=?4:9:?b55<2127j<h4:9:?b4f<2127j4o4:9:?b<<<2127j4:4:9:?b<0<2127ij=4:9:?ab4<2127iik4:9:?0<f<212784i4:9:?0<d<212784o4:9:?0<3<212784:4:9:?0<1<21278484:9:?0<7<212784>4:9:?0<5<212784<4:9:?03`<21278;k4:9:?03f<21278;i4:9:?03d<21278;o4:9:?03=<21278;44:9:?033<21278;:4:9:?031<21278;84:9:?035<21278;<4:9:?02`<21278:k4:9:?02f<21278:i4:9:?02d<21278:o4:9:?02=<21278:44:9:?023<21278::4:9:?021<21278:84:9:?027<21278:>4:9:?025<21278:<4:9:?01`<212789k4:9:?0=d<212785o4:9:?0==<21278544:9:?0=3<212785:4:9:?0=1<21278584:9:?0=7<212785>4:9:?0=5<212785<4:9:?0<`<212784k4:9:?0<=<21278444:9:?037<21278;>4:9:?01f<212789i4:9:?:`2<2m272h?4:e:?:ga<2m272o54:e:?:g6<2m272nh4:e:?:f<<2m272n94:e:?:ec<2m272ml4:e:?:e0<2m272m=4:e:?:=g<2m2725;4:e:?:=4<2m2724n4:e:?:<2<2m2724?4:e:?:3a<2m272;54:e:?:36<2m272:h4:e:?:2<<2m272:94:e:?:1c<2m2729l4:e:?:10<2m2729=4:e:?:0g<2m2728;4:e:?:04<2m272?n4:e:?a`d<2127iok4:9:?agf<2127io54:9:?ag1<2127io=4:9:?aff<2127in54:9:?af1<21272=l4:9:?:50<21272=94:9:?:52<21272=;4:9:?:54<21273ii4:9:?;a=<21273i:4:9:?;ad<21273i44:9:?;a1<21273o=4:9:?;fg<21273nl4:9:?;fa<21273nn4:9:?;f2<212735>4:9:?;<`<212734i4:9:?;=5<212734k4:9:?;<d<21273:;4:9:?;24<21273:=4:9:?;26<21273:?4:9:?;1a<21273?44:9:?;71<21273?>4:9:?;73<21273?84:9:?;75<21273<n4:9:?;42<21273<;4:9:?;4<<21273<54:9:?;46<2127<hk4:9:?4`d<2127<h44:9:?4`f<2127<ho4:9:?4`3<2127<n?4:9:?4ea<2127<mn4:9:?4ec<2127<mh4:9:?4e<<2127<484:9:?4<5<2127<;k4:9:?4<7<2127<4<4:9:?43f<2127<954:9:?416<2127<9?4:9:?410<2127<994:9:?40c<2127<>o4:9:?463<2127<>84:9:?46=<2127<>:4:9:?467<2127=jh4:9:?5b<<2127=j54:9:?5bg<2127=jl4:9:?5b0<2127=h<4:9:?5gf<2127=oo4:9:?5g`<2127=oi4:9:?5g=<2127=m94:9:?5=c<2127=5h4:9:?5e4<2127=m=4:9:?5=g<2127=;:4:9:?537<2127=;<4:9:?531<2127=;>4:9:?52`<2127=8l4:9:?500<2127=894:9:?502<2127=8;4:9:?504<2127==i4:9:?55=<2127==:4:9:?55d<2127==44:9:?551<2127>j=4:9:?6ag<2127>il4:9:?6aa<2127>in4:9:?6a2<2127>o>4:9:?6f`<2127>ni4:9:?6g5<2127>nk4:9:?6fd<2127>5;4:9:?6=4<2127>5=4:9:?6=6<2127>5?4:9:?6<a<2127>:44:9:?621<2127>:>4:9:?623<2127>:84:9:?625<2127>?n4:9:?672<2127>?;4:9:?67<<2127>?54:9:?676<2127><k4:9:?64d<2127><44:9:?64f<2127><o4:9:?643<2127?i?4:9:?7`a<2127?hn4:9:?7`c<2127?hh4:9:?7`<<2127?n84:9:?7f5<2127?mk4:9:?7f7<2127?n<4:9:?7ef<2127?454:9:?7<6<2127?4?4:9:?7<0<2127?494:9:?73c<2127?9o4:9:?713<2127?984:9:?71=<2127?9:4:9:?717<2127?>h4:9:?76<<2127?>54:9:?76g<2127?>l4:9:?760<2127?<<4:9:?0bf<21278jo4:9:?0b`<21278ji4:9:?0b=<21278h94:9:?0gc<21278oh4:9:?0`4<21278h=4:9:?0gg<21278m:4:9:?0e7<21278m<4:9:?0e1<21278m>4:9:?0=`<21279o44:9:?1g=<21279o;4:9:?1g2<21279n;4:9:?1f0<21279n>4:9:?1f1<212795=4:9:?1<c<212794i4:9:?1<`<21279;i4:9:?13f<21279;l4:9:?13g<21279:l4:9:?12<<21279::4:9:?12=<212799:4:9:?113<21279994:9:?110<21279894:9:?106<212798<4:9:?107<21279?<4:9:?175<21279>h4:9:?16c<21279=h4:9:?15a<21279=o4:9:?15f<21279<o4:9:?14d<21279<54:9:?14<<2127:j54:9:?2b2<2127:j84:9:?2b3<2127:i84:9:?2a1<2127:i?4:9:?2a6<2127:nk4:9:?2f`<2127:nn4:9:?2fa<2127:mn4:9:?2eg<2127:m44:9:?2ed<2127:544:9:?2==<2127:5;4:9:?2=2<2127:4;4:9:?2<0<2127:4>4:9:?2<1<2127:;>4:9:?237<2127:;=4:9:?234<2127::=4:9:?21c<2127:9i4:9:?21`<2127:8i4:9:?20f<2127:8l4:9:?20g<2127:?l4:9:?27<<2127:?:4:9:?27=<2127:>:4:9:?263<2127:>94:9:?260<2127:=94:9:?256<2127:=<4:9:?257<212788h4:9:?00a<212788o4:9:?00f<21278?o4:9:?07d<21278?54:9:?07<<21278>54:9:?062<21278>84:9:?063<21278=84:9:?051<21278=?4:9:?056<21278<?4:9:?044<21279jk4:9:?045<21279ik4:9:?1a`<21279in4:9:?1aa<21279hn4:9:?1`g<21279h44:9:?1`d<21279m>4:9:?1e7<21279m=4:9:?1e4<2127:h?4:9:?2`4<2127:ok4:9:?2`5<2127:<<4:9:?245<2127mi7;6;<de>0?<uz<96=4={_41?8d>j33<7p}93;296~X1;27i5o468:p21<72;qU:952b8`9=<=z{??1<7<t^7789g?e20k0q~89:181[0134hj<779;|q53?6=:rT=;63ma18:1>{t>10;6?uQ699>fd6=1>1v;750;0xZ3?<5kk;6464}r4b>5<5sW<j70ln0;;:?xu1j3:1>vP9b:?ae5<>i2wx:n4?:2y]2f=:;<i14552b8c9=3=z{?n1<7<t^7f89gg420<0q~8j:181[0b34hj?77:;|q5b?6=:rT=j63ma28:3>{t?90;6?uQ719>fd5=111v:?50;0xZ27<5kk86474}r51>5<5sW=970ln3;;b?xu0;3:1>vP83:?a=f<>=2wx;94?:3y]31=:j0i15;5rs6794?4|V>?01o7l:858yv112909wS99;<`:g???3ty<;7>52z\43>;e1h0296s|7983>7}Y?116n4m5989~w2?=838pR:74=c;g><3<uz=j6=4={_5b?8d>l33=7p}8b;296~X0j27i5i467:p3f<72;qU;n52b8f9===z{>o1<7<t^6g89g?c2030q~9i:181[1a34h3i7om;|q;4?6=;rT3<63m988:0>;e1h02;6s|8083>`4|V1;01l6<:4`89d>52k801l6>:4`89d>72k801l9i:4`89d1b2k801l9k:4`89d1d2k801l9m:4`89d1f2k801l96:4`89d1?2k801l98:4`89d112k801l9::4`89d132k801l9<:4`89d152k801l9>:4`89d172k801l8i:4`89d0b2k801l8k:4`89d0d2k801l8m:4`89d0f2k801l86:4`89d0?2k801l88:4`89d012k801l8::4`89d032k801l8<:4`89d052k801l8>:4`89d072k801l;i:4`89d3b2k801l;k:4`89d3d2k801l;m:4`89d3f2k801l;6:4`89d3?2k801l;8:4`89d312k801l;::4`89d332k801l;<:4`89d352k801l;>:4`89d372k801l:i:4`89d2b2k801l:k:4`89d2d2k801l:m:4`89d2f2k801l:6:4`89d2?2k801l:8:4`89d212k801l:::4`89d232k801l:<:4`89d262k801l:?:4`89d5a2k801l=j:4`89d5c2k801l=l:4`89d5e2k801l=n:4`89d5>2k801l=7:4`89d502k801l=9:4`89d522k801l=;:4`89d542k801l==:4`89d562k801l=?:4`89d4a2k801l<j:4`89d4c2k801l<l:4`89d4e2k801l<n:4`89d4>2k801l<7:4`89d402k801l<9:4`89d422k801l<;:4`89d442k801l<=:4`89d462k801l<?:4`89d7a2k801l?j:4`89d7c2k801l?l:4`89d7e2k801l?n:4`89d7>2k801l?7:4`89d702k801l?9:4`89d722k801l?;:4`89d742k801l?=:4`89d762k801l??:4`89d6a2k801l>j:4`89d6c2k801l>l:4`89d6e2k801l6m:4`89d>f2k801l66:4`89d>?2k801l68:4`89d>12k801l6::4`89d>32k801>6l:4`896>f2<h01>69:4`896>32<h01>6=:4`896>72<h01>9j:4`8961d2<h01>9n:4`8961?2<h01>99:4`896132<h01>9?:4`8960b2<h01>8l:4`8960f2<h01>87:4`896012<h01>8;:4`896052<h01>8?:4`8963b2<h01>7n:4`896??2<h01>79:4`896?32<h01>7=:4`896?72<h01>6j:4`896>?2<h01>9=:4`8963d2<h014j7:8789<b02<h014j<:8789<b52<h014mj:8789<ec2<h014m6:8789<e?2<h014m;:8789<e42<h014li:8789<db2<h014ln:8789<d>2<h014l::8789<d32<h014l?:8789<ga2<h014om:8789<gf2<h014o9:8789<g22<h014o>:8789<g72<h0147l:8789<?e2<h01478:8789<?12<h0147=:8789<?62<h0146k:8789<>d2<h01467:8789<>02<h0146<:8789<>52<h0149j:8789<1c2<h01496:8789<1?2<h0149;:8789<142<h0148i:8789<0b2<h0148n:8789<0>2<h0148::8789<032<h0148?:8789<3a2<h014;m:8789<3f2<h014;9:8789<322<h014;>:8789<372<h014:l:8789<2e2<h014:8:8789<212<h014:=:8789<262<h014=k:8789<5d2<h01o7n:8:8yv>529099vP72:?b41<2j27j<9478:?b<7<2j27j4=4:b:?b3`<2j27j;n4:b:?b3d<2j27j;54:b:?b33<2j27j;94:b:?b37<2j27j;=4:b:?b2`<2j27j:n4:b:?b2d<2j27j:54:b:?b23<2j27j:94:b:?b27<2j27j:=4:b:?b1`<2j27j9n4:b:?b1d<2j27j954:b:?b13<2j27j994:b:?b17<2j27j9=4:b:?b0`<2j27j8n4:b:?b0d<2j27j854:b:?b03<2j27j894:b:?:b`<>>27i5l469:p<6<728:?wS6<;<`e4?>?34h3i778;<;2=??0343:<778;<;3b??0343:?778;<;26??0342no778;<:f7??0342n>778;<:f2??0342n9778;<:ab??0342i:778;<:a1??0342i5778;<:a<??03422>778;<:;=??034234778;<:;g??03423n778;<:51??0342>o778;<:6f??0342>j778;<:6a??034284778;<:1b??03429i778;<:06??03428=778;<:3f??0342;>778;<:35??0342;9778;<:30??034=oi778;<5g1??034=o8778;<5g<??034=o;778;<5a5??034=j4778;<5b3??034=jn778;<5be??034=38778;<54f??034=<m778;<54a??034=<h778;<563??034=?i778;<57`??034=>=778;<564??034=9m778;<515??034=9<778;<510??034=9?778;<4e`??034<m8778;<4e7??034<m;778;<4e2??034<o<778;<4`3??034<h:778;<4`e??034<h5778;<4b7??034<2m778;<4:=??034<2h778;<4:g??034<<:778;<45`??034<=o778;<444??034<=j778;<47=??034<?<778;<40b??034<??778;<476??034<:o778;<427??034<:>778;<422??034<:9778;<7fb??034?n:778;<7f1??034?n5778;<7f<??034?h>778;<7a=??034?i4778;<7ag??034?in778;<7:1??034?3o778;<7;f??034?3j778;<7;a??034?=4778;<76b??034?>i778;<756??034?==778;<70f??034?8>778;<705??034?89778;<700??034?;i778;<731??034?;8778;<73<??034?;;778;<6f5??034>o4778;<6g3??034>on778;<6ge??034>i8778;<6bf??034>jm778;<6ba??034>jh778;<6;3??034><i778;<64`??034>3=778;<6;4??034>>m778;<665??034>><778;<660??034>>?778;<61`??034>98778;<617??034>9;778;<612??034>;<778;<1e3??0349m:778;<1ee??0349m5778;<1g7??0349hm778;<1`=??0349hh778;<1`g??0349j:778;<1:`??03492o778;<1b4??03492j778;<0`e??0348h9778;<0`0??0348i;778;<0a6??0348i=778;<0:5??03483o778;<0;f??0348<i778;<04=??0348<4778;<05f??0348=:778;<051??0348>4778;<067??0348>>778;<071??0348?<778;<00b??03488>778;<01`??03489o778;<02b??0348:m778;<02=??0348;o778;<033??0348;:778;<3e=??034;m8778;<3e7??034;n:778;<3f5??034;n<778;<3`4??034;in778;<3ae??034;jh778;<3b<??034;j;778;<3:e??034;29778;<3:0??034;3;778;<3;6??034;3=778;<340??034;=j778;<35a??034;==778;<36g??034;>n778;<37a??034;?5778;<37<??034;8n778;<302??034;89778;<31<??034;9?778;<316??034;:9778;<324??034;;j778;<17b??0349?m778;<17=??03498o778;<103??03498:778;<11=??034998778;<117??0349::778;<125??0349:<778;<137??0348mi778;<0e`??0348m<778;<0ff??0348nm778;<0g`??0348o4778;<0g3??0348j8778;<0:b??03482i778;<3g7??034;hi778;<3``??034;;>778;<dg><1<5oi15:52b8c9=d=z{1>1<7<t^9689g?e20<0q~6::181[>234h2n77:;|qb3?6=kr7ijl461:?agg<?127io:479:?ag6<?127ink479:?afg<?127in:479:?af6<?1272io479:?:a2<?1272i>479:?247<>>2wxm54?:2158daj3kh70l7d;7a?8g783?i70o?1;7a?8g7:3?i707i6;7a?8?a?3?i70li0;7a?8da93?i70lka;7a?8ddn3?i70llc;7a?8dd03?i70ll4;7a?8dd83?i70lmc;7a?8de03?i70lm4;7a?8de;3?o70lm6;7g?8?b;3?o707j6;7g?8?6i3?i707>5;7a?8?6<3?i707>7;7a?8?6>3?i707>1;7a?8?603?i707>f;:;?8?6m323707>c;7a?8?6k323707>b;7a?8?6j323707<6;7a?8?4?3?i707=e;7a?8?5n3?i706jd;7a?8>b03?i706j7;7a?8>bi3?i706j9;7a?8>b<3?i706jb;7a?8>a:323706i1;:;?8>bn3?i706jf;:;?8>bm3?i706je;:;?8?713?i707?a;7a?8?793?i707?2;7a?8>d83?i706mb;7a?8>ei3?i706md;7a?8>ek3?i706m7;7a?8>em3?i706l5;:;?8>d<323706l2;7a?8>d:323706l1;7a?8>d9323706kc;7a?8>cl3?i706k4;7a?8>c=3?i70663;7a?8>?m3?i7067d;7a?8>>83?i7067f;7a?8>?i3?i70661;7a?8>>032370667;:;?8>>=3?i70665;:;?8>><3?i70664;:;?8>fn3?i706m0;7a?8>f?3?i706n8;7a?8>1>3?i70691;7a?8>183?i70693;7a?8>1:3?i706:d;7a?8>1<3?i7069b;:;?8>1i32370698;7a?8>1032370697;7a?8>1?32370672;7a?8>?;3?i7068a;7a?8>0j3?i706<9;7a?8>4<3?i706<3;7a?8>4>3?i706<5;7a?8>483?i706<7;7a?8>4m323706<d;:;?8>4j3?i706<b;:;?8>4i3?i706<a;:;?8>2=3?i706:6;7a?8>3l3?i706;e;7a?8>7k3?i706?7;7a?8>7>3?i706?9;7a?8>703?i706?3;7a?8>7i3?i706>1;:;?8>68323706?e;7a?8>7m323706?d;7a?8>7l323706=8;7a?8>513?i706=0;7a?8>593?i709kf;7a?81ci3?i709k9;7a?81ck3?i709kb;7a?81c>3?i709kd;7a?81b<323709j3;:;?81b93?i709j1;:;?81b83?i709j0;:;?81aj3?i709ic;7a?81a;3?i709i4;7a?81e:3?i709nd;7a?81fk3?i709nf;7a?81fm3?i709n9;7a?81e83?i709m7;:;?81e>323709m4;7a?81e<323709m3;7a?81e;323709le;7a?81dn3?i709l6;7a?81d?3?i70975;7a?81?83?i7098f;7a?81?:3?i70971;7a?810k3?i70973;7a?81?i32370979;:;?81??3?i70977;:;?81?>3?i70976;:;?81f93?i709n2;7a?81>13?i7096a;7a?81203?i709:3;7a?812:3?i709:5;7a?812<3?i709;f;7a?812>3?i709:d;:;?812k323709:a;7a?812i323709:9;7a?812132370984;7a?810=3?i7099c;7a?811l3?i709=b;7a?815>3?i709=5;7a?81503?i709=7;7a?815:3?i709=9;7a?8148323709=f;:;?815l3?i709=d;:;?815k3?i709=c;:;?813?3?i709;8;7a?814n3?i709;0;7a?80am3?i708i9;7a?80a03?i708ib;7a?80ai3?i708i5;7a?80ak3?i709?3;:;?817:323709?0;7a?8178323708if;7a?80an323709>a;7a?816j3?i709>2;7a?816;3?i708k1;7a?80dk3?i708lb;7a?80dm3?i708ld;7a?80d03?i708lf;7a?80c>323708k5;:;?80c;3?i708k3;:;?80c:3?i708k2;:;?80bl3?i708je;7a?80b=3?i708j6;7a?80f<3?i7086f;7a?80>m3?i708n1;7a?80f83?i7086b;7a?80f:3?i708n9;:;?80f0323708n6;7a?80f>323708n5;7a?80f=323708l0;7a?80d93?i708m8;7a?80e13?i70887;7a?800:3?i70881;7a?800<3?i70883;7a?801m3?i70885;7a?800k3237088b;:;?80013?i70889;:;?80003?i70888;:;?80>;3?i70864;7a?80?j3?i7087c;7a?803i3?i708;5;7a?803<3?i708;7;7a?803>3?i708;1;7a?80303?i708;f;:;?803m323708;c;7a?803k323708;b;7a?803j32370896;7a?801?3?i708:e;7a?802n3?i708>d;7a?80603?i708>7;7a?806i3?i708>9;7a?806<3?i708>b;7a?805:323708=1;:;?806n3?i708>f;:;?806m3?i708>e;:;?80413?i708<a;7a?80493?i708<2;7a?83a83?i70;jb;7a?83bi3?i70;jd;7a?83bk3?i70;j7;7a?83bm3?i70;i5;:;?83a<32370;i2;7a?83a:32370;i1;7a?83a9323708?c;7a?807l3?i708?4;7a?807=3?i70;l3;7a?83em3?i70;md;7a?83d83?i70;mf;7a?83ei3?i70;l1;7a?83d032370;l7;:;?83d=3?i70;l5;:;?83d<3?i70;l4;:;?83cn3?i70;j0;7a?83c?3?i70;k8;7a?83>>3?i70;61;7a?83>83?i70;63;7a?83>:3?i70;7d;7a?83><3?i70;6b;:;?83>i32370;68;7a?83>032370;67;7a?83>?32370;m2;7a?83e;3?i70;na;7a?83fj3?i70;99;7a?831<3?i70;93;7a?831>3?i70;95;7a?83183?i70;97;7a?831m32370;9d;:;?831j3?i70;9b;:;?831i3?i70;9a;:;?83?=3?i70;76;7a?830l3?i70;8e;7a?834k3?i70;<7;7a?834>3?i70;<9;7a?83403?i70;<3;7a?834i3?i70;;1;:;?833832370;<e;7a?834m32370;<d;7a?834l32370;:8;7a?83213?i70;:0;7a?83293?i70;?f;7a?837i3?i70;?9;7a?837k3?i70;?b;7a?837>3?i70;?d;7a?836<32370;>3;:;?83693?i70;>1;:;?83683?i70;>0;:;?835j3?i70;=c;7a?835;3?i70;=4;7a?82b:3?i70:kd;7a?82ck3?i70:kf;7a?82cm3?i70:k9;7a?82b83?i70:j7;:;?82b>32370:j4;7a?82b<32370:j3;7a?82b;32370:ie;7a?82an3?i70:i6;7a?82a?3?i70:m5;7a?82e83?i70:nf;7a?82e:3?i70:m1;7a?82fk3?i70:m3;7a?82ei32370:m9;:;?82e?3?i70:m7;:;?82e>3?i70:m6;:;?82c93?i70:k2;7a?82d13?i70:la;7a?82?03?i70:73;7a?82?:3?i70:75;7a?82?<3?i70:8f;7a?82?>3?i70:7d;:;?82?k32370:7a;7a?82?i32370:79;7a?82?132370:n4;7a?82f=3?i70:6c;7a?82>l3?i70::b;7a?822>3?i70::5;7a?82203?i70::7;7a?822:3?i70::9;7a?821832370::f;:;?822l3?i70::d;:;?822k3?i70::c;:;?820?3?i70:88;7a?821n3?i70:80;7a?825m3?i70:=9;7a?82503?i70:=b;7a?825i3?i70:=5;7a?825k3?i70:<3;:;?824:32370:<0;7a?824832370:=f;7a?825n32370:;a;7a?823j3?i70:;2;7a?823;3?i70:?1;7a?85ak3?i70=ib;7a?85am3?i70=id;7a?85a03?i70=if;7a?827>32370:?5;:;?827;3?i70:?3;:;?827:3?i70:?2;:;?826l3?i70:>e;7a?826=3?i70:>6;7a?85c<3?i70=lf;7a?85dm3?i70=k1;7a?85c83?i70=lb;7a?85c:3?i70=k9;:;?85c032370=k6;7a?85c>32370=k5;7a?85c=32370=i0;7a?85a93?i70=j8;7a?85b13?i70=n7;7a?85f:3?i70=n1;7a?85f<3?i70=n3;7a?85>m3?i70=n5;7a?85fk32370=nb;:;?85f13?i70=n9;:;?85f03?i70=n8;:;?85d;3?i70=l4;7a?85ej3?i70=mc;7a?84d13?i70<l8;7a?84d>3?i70<l7;7a?84dk3?i70<lc;:;?84dj3?i70<lb;:;?84e>3?i70<m5;7a?84e;3?i70<m4;7a?84e13?i70<m9;:;?84e03?i70<m8;:;?84>83?i70<7f;7a?84?l3?i70<7e;7a?84>;3?i70<63;:;?84>:3?i70<62;:;?840l3?i70<8c;7a?840i3?i70<8b;7a?84?83?i70<70;:;?840n3?i70<8f;:;?841i3?i70<99;7a?841?3?i70<98;7a?841l3?i70<9d;:;?841k3?i70<9c;:;?842?3?i70<:6;7a?842<3?i70<:5;7a?842i3?i70<:a;:;?84213?i70<:9;:;?843<3?i70<;3;7a?84393?i70<;2;7a?843?3?i70<;7;:;?843>3?i70<;6;:;?84493?i70<<0;7a?845m3?i70<=f;7a?844<3?i70<<4;:;?844;3?i70<<3;:;?846m3?i70<>d;7a?846j3?i70<>c;7a?84593?i70<=1;:;?84583?i70<=0;:;?847j3?i70<?a;7a?84703?i70<?9;7a?847m3?i70<?e;:;?847l3?i70<?d;:;?87a03?i70?i7;7a?87a=3?i70?i6;7a?87aj3?i70?ib;:;?87ai3?i70?ia;:;?87b=3?i70?j4;7a?87b:3?i70?j3;7a?87b03?i70?j8;:;?87b?3?i70?j7;:;?87en3?i70?me;7a?87ek3?i70?md;7a?87d:3?i70?l2;:;?87d93?i70?l1;:;?87fk3?i70?nb;7a?87f13?i70?na;7a?87fn3?i70?nf;:;?87fm3?i70?ne;:;?87>13?i70?68;7a?87>>3?i70?67;7a?87>k3?i70?6c;:;?87>j3?i70?6b;:;?87?>3?i70?75;7a?87?;3?i70?74;7a?87?13?i70?79;:;?87?03?i70?78;:;?870;3?i70?82;7a?87083?i70?81;7a?870>3?i70?86;:;?870=3?i70?85;:;?87183?i70?:f;7a?872l3?i70?:e;7a?871;3?i70?93;:;?871:3?i70?92;:;?873l3?i70?;c;7a?873i3?i70?;b;7a?87283?i70?:0;:;?873n3?i70?;f;:;?874i3?i70?<9;7a?874?3?i70?<8;7a?874l3?i70?<d;:;?874k3?i70?<c;:;?875?3?i70?=6;7a?875<3?i70?=5;7a?875i3?i70?=a;:;?87513?i70?=9;:;?876<3?i70?>3;7a?87693?i70?>2;7a?876?3?i70?>7;:;?876>3?i70?>6;:;?853m3?i70=;d;7a?853j3?i70=;c;7a?85293?i70=:1;:;?85283?i70=:0;:;?854j3?i70=<a;7a?85403?i70=<9;7a?854m3?i70=<e;:;?854l3?i70=<d;:;?85503?i70==7;7a?855=3?i70==6;7a?855j3?i70==b;:;?855i3?i70==a;:;?856=3?i70=>4;7a?856:3?i70=>3;7a?85603?i70=>8;:;?856?3?i70=>7;:;?857:3?i70=?1;7a?84an3?i70=?0;7a?857=3?i70=?5;:;?857<3?i70=?4;:;?84bn3?i70<je;7a?84bk3?i70<jd;7a?84a:3?i70<i2;:;?84a93?i70<i1;:;?84ck3?i70<kb;7a?84c13?i70<ka;7a?84cn3?i70<kf;:;?84cm3?i70<ke;:;?84f;3?i70<n2;7a?84f83?i70<n1;7a?84f>3?i70<n6;:;?84f=3?i70<n5;:;?87c:3?i70?k1;7a?87dn3?i70?k0;7a?87c=3?i70?k5;:;?87c<3?i70?k4;:;?87793?i70??0;7a?8`b2<h01kh55c9>552==k16==:5899>555==k16===5899~wd?=838p1o7k:``89g?d20k0q~l9:185[d1349j9767;<1b=?3>349h?767;<1af?>?349jm77;;|qa3?6=>rTi;63:668;<>;2>k0>563:848;<>;2?m03463:6b8:0>{tj10;6;uQb99>1<2=01169465589>1g4=01169lo5899>1<?=1=1vo750;4xZg?<5<i:6564=4a6>0?<5<nm6564=4f4>=><5<i=64:4}r`b>5<1sWhj70;je;:;?83a:3?2708?c;:;?807<32370;i3;;7?xuej3:1:vPmb:?55g<?027==k4:9:?57<<?027=?<478:?565<><2wxnn4?:7y]ff=:>=21455265a91<=:>?<1455264g9<==:>=n1595rscf94?0|Vkn01;9::9:8931>2<301;7<:9:893>e21201;9n:868yvdb290=wSlj;<4b6?>?34<j:7;6;<4`4?>?34<i4767;<4b3??33tyij7>56z\ab>;1ko034639d286=>;1mm034639e48;<>;1l=0286s|c183>3}Yk916:km5899>356==016;<o5899>344=0116;=?5959~wf7=83<pRn?4=2f1>=><5:n=6874=2d3>=><5:o36564=2f4><2<uzi96=49{_a1?8151323709=d;7:?813?323709<f;:;?815m33?7p}l3;292~Xd;27<9;478:?41d<2127<;9478:?42f<?027<9o464:pg1<72?qUo9527919<==:?1=194527`39<==:?031455279:9=1=z{j?1<78t^b7892d721201:l;:4;892eb21201:m9:9:892d220>0q~m9:185[e134=oh767;<5f5?3>34=mn767;<5e7?>?34=n>77;;|q`3?6=>rTh;6370`8;<>;?8l0>5637298;<>;?:90346370g8:0>{tk10;6;uQc99><61=01164>l5589><03=011649j5899><6e=1=1vn750;4xZf?<51<?6564=94;>0?<51296564=95b>=><51<264:4}rab>5<1sWij70661;:;?8>>=3?2706nf;:;?8>f?32370666;;7?xudj3:1:vPlb:?;f`<?0273o?4:9:?;`f<?0273h9478:?;g6<><2wxon4?:7y]gf=:;ol1455241191<=:<8n145524079<==:<9>1595rsbf94?0|Vjn015km:9:89=ca2<3014>6:9:89<66212015h?:868yvea290=wSmi;<;2<?>?343:o7;6;<;02?>?3439i767;<;2`??33tyo<7>56z\g4>;3:j03463;3186=>;3<h03463;438;<>;3;80286s|d083>3}Yl8168875899>00b==0168:95899>03`=011688k5959~wa4=83<pRi<4=5:5>=><5=2j6874=5c7>=><5=3h6564=5:a><2<uzn86=49{_f0?82e;32370:m7;7:?82c932370:l9;:;?82e033?7p}k4;292~Xc<27?i=478:?7a1<2127?jh478:?7b3<?027?i8464:p`0<72?qUh85251f9<==:=8;1945253`9<==:=;9145525009=1=z{m<1<78t^e48905f212018=j:4;8903?212018;?:9:8905a20>0q~j8:181[b03438j7l?;|qg<?6=:rTo4636708a4>{tl00;6?uQd89>=20=j91vio50;0xZag<50=i6o>4}rfa>5<5sWni70770;`3?xuck3:1>vPkc:?:<0<e82wxhi4?:3y]`a=:11k1n=5rseg94?4|Vmo0146i:c28yvba2909wSji;<;:0?d73tyn<7>52z\f4>;>100i<6s|e083>7}Ym81654k5b19~w`4=838pRh<4=867>g6<uzo86=4={_g0?8?f;3h;7p}j4;296~Xb<272m54m0:pa0<72;qUi8529`f9f5=z{l<1<7<t^d489<d52k:0q~k8:181[c0343i;7l?;|qf<?6=:rTn4636bb8a4>{tm00;6?uQe89>=f7=j91vho50;0xZ`g<50i=6o>4}rga>5<5sWoi707lb;`3?xubk3:1>vPjc:?:`5<e82wxii4?:3y]aa=:1=31n=5rsdg94?4|Vlo014j::c28yv`72909wSh?;<;ge?d73tym=7>52z\e5>;><l0i<6s|f383>7}Yn;1658=5b19~wc5=838pRk=4=87;>g6<uzl?6=4={_d7?8?2l3h;7p}i5;296~Xa=272:?4m0:pb3<72;qUj;529759f5=z{o=1<7<t^g589<0d2k:0q~hn:1810~;>no0i<63n0286f>;f8:034636f78;<>;f<80>n63n3g86f>;f;m0>n63n3c86f>;f;00>n63n3686f>;f;<0>n63n3286f>;f;80>n63n2g86f>;f:m0>n63n2c86f>;f:00>n63n2686f>;f:<0>n63n2286f>;f:80>n63n1g86f>;f9m0>n63n1c86f>;f900>n63n1686f>;f9<0>n63n1286f>;f980>n63n0g86f>;f8m0>n63n0c86f>;f0h0>n63n8986f>;f0?0>n63n8586f>{tnk0;6?u2b9f9f5=:j1o15;5rs025>5<5s4ln6564=ga9eg=z{8:<6=4={<334?>?34lo6ll4}r33<?6=:r7:<>4m0:?eg??23ty:<44?:3y>557=j916ji466:p55g=838p1<>?:c289ce=1?1v<>m:1818`b2k:01kh5899~w46d2909w0??1;:;?877:3ki7p}>0e83>7}:99>1n=52fe8:1>{t99o1<7<t=020>0?<58:>6ll4}r32=?6=:r7:=<478:?24c<fj2wx=<o50;0x947421201<??:``8yv76j3:1>v3>178a4>;68o0296s|10a94?4|58;?6o>4=033><0<uz;:h7>52z?256<e827:<k466:p54c=838p1<?>:c2894752120q~?>f;296~;69=03463>148bf>{t9;:1<7<t=034>g6<58;;64;4}r315?6=:r7:=;4:9:?25=<fj2wx=?m50;0x944321201<<=:``8yv75l3:1>v3>278;<>;6::0jn6s|13g94?4|58826o>4=001><3<uz;9j7>52z?262<e827:>>466:p566=838p1<<9:c28944520<0q~?<1;296~;6:=0i<63>248;<>{t9:81<7<t=004>=><58836ll4}r307?6=:r7:>l4m0:?266<>=2wx=>:50;0x944>2<301<<m:``8yv74n3:1>v3>368;<>;6;<0jn6s|15294?4|58926564=015>dd<uz;?=7>52z?27f<e827:?8465:p514=838p1<=n:c28945120<0q~?;3;296~;6;00i<63>348:2>{t9=>1<7<t=014>g6<58936564}r371?6=:r7:?l478:?27g<fj2wx=9850;0x945c2k:01<=9:878yv73?3:1>v3>3b86=>;6;l0jn6s|14094?4|58>j6564=06;>dd<uz;>?7>52z?20f<?027:844nb:p502=838p1<:i:c28942?20?0q~?:5;296~;6<m0i<63>488:2>{t9<<1<7<t=06`>g6<58>36484}r363?6=:r7:8l4m0:?20g<?02wx=8650;0x942c21201<:j:``8yv7213:1>v3>518a4>;6<00296s|14c94?4|58>m6874=072>dd<uz;=97>52z?21a<?027:9o4nb:p530=838p1<;i:9:8943d2hh0q~?97;296~;6>;0i<63>5c8:1>{t9?21<7<t=043>g6<58?h6484}r35=?6=:r7:9k4m0:?21g<>>2wx=;o50;0x943c2k:01<;j:9:8yv71j3:1>v3>618;<>;6>80jn6s|17a94?4|58<86o>4=07`><3<uz;=h7>52z?227<2127::94nb:p52>=838p1<9?:9:8940b2hh0q~?89;296~;6?;03463>6g8bf>{t9>k1<7<t=056>g6<58<n64;4}r34f?6=:r7:;>4m0:?22c<>>2wx=:m50;0x94152k:01<8j:848yv70l3:1>v3>718a4>;6?80346s|16g94?4|58=86564=057>dd<uz;<j7>52z?233<e827::k465:p5=6=838p1<9::4;894102hh0q~?7b;296~;60:03463>808bf>{t91i1<7<t=0:6>=><58296ll4}r3;`?6=:r7:454m0:?2<4<>=2wx=5k50;0x94>12k:01<6=:848yv7?n3:1>v3>848a4>;60802:6s|18294?4|58286o>4=0:7>=><uz;2=7>52z?2<3<?027:4:4nb:p5<4=838p1<66:c2894>520?0q~?63;296~;6010>563>8`8bf>{t90o1<7<t=0;5>=><583?6ll4}r3:b?6=:r7:55478:?2=0<fj2wx=l>50;0x94?e2k:01<7;:878yv7f93:1>v3>988a4>;61<02:6s|1`094?4|58336o>4=0;7><0<uz;j?7>52z?2=3<e827:5:478:p5d2=838p1<76:9:894?f2hh0q~?n5;296~;61j0i<63>948:1>{t9h<1<7<t=0;a>0?<583o6ll4}r3a5?6=:r7:m4478:?2e2<fj2wx=o<50;0x94ge21201<o7:``8yv7e;3:1>v3>ad8a4>;6i>0296s|1c694?4|58kh6o>4=0c;><0<uz;i97>52z?2eg<e827:m:466:p5g0=838p1<o6:c2894gf2120q~?m7;296~;6ij03463>ae8bf>{t9k21<7<t=0ce>g6<58k364;4}r3a=?6=:r7:mh4:9:?2f5<fj2wx=n:50;0x94dd21201<ln:``8yv7d=3:1>v3>bd8;<>;6jk0jn6s|1b494?4|58i:6o>4=0`b><3<uz;h;7>52z?2fc<e827:no466:p5f>=838p1<lj:c2894df20<0q~?l9;296~;6jj0i<63>be8;<>{t9jk1<7<t=0`e>=><58i;6ll4}r3`f?6=:r7:o?4m0:?2fg<>=2wx=nm50;0x94e62<301<m<:``8yv7c?3:1>v3>cg8;<>;6km0jn6s|1e:94?4|58n:6564=0af>dd<uz;o57>52z?2`1<e827:oi465:p5ag=838p1<j=:c2894eb20<0q~?kb;296~;6l80i<63>ce8:2>{t9mi1<7<t=0ae>g6<58n;6564}r3g`?6=:r7:h?478:?2`6<fj2wx=ik50;0x94b22k:01<mj:878yv7cn3:1>v3>d586=>;6l?0jn6s|1dc94?4|58o96564=0g3>dd<uz;nn7>52z?2a1<?027:i<4nb:p5`e=838p1<k8:c2894c720?0q~?jd;296~;6m<0i<63>e08:2>{t9lo1<7<t=0g7>g6<58o;6484}r3fb?6=:r7:i?4m0:?2a6<?02wx=k>50;0x94c221201<k9:``8yv7a93:1>v3>e98a4>;6m80296s|1g094?4|58o<6874=0g:>dd<uz;mh7>52z?2b0<?027:j>4nb:p5cc=838p1<h8:9:894`32hh0q~?if;296~;6nh0i<63>f28:1>{t:9:1<7<t=0d;>g6<58l?6484}r035?6=:r7:j:4m0:?2b6<>>2wx>=<50;0x94`22k:01<h9:9:8yv47;3:1>v3>f98;<>;6n00jn6s|21694?4|58li6o>4=0d7><3<uz8;97>52z?2bd<2127:jn4nb:p646=838p1?>7:9:897612hh0q~<>1;296~;58h03463=068bf>{t:881<7<t=32g>g6<5;:=64;4}r027?6=:r79<o4m0:?142<>>2wx><:50;0x976f2k:01?>9:848yv46=3:1>v3=098a4>;5800346s|20494?4|5;:i6564=32`>dd<uz8:;7>52z?14`<e8279<:465:p64>=838p1?>k:4;8976a2hh0q~<=3;296~;59k03463=188bf>{t:;>1<7<t=33g>=><5;;j6ll4}r011?6=:r79>=4m0:?15<<>=2wx>?850;0x977b2k:01??n:848yv45?3:1>v3=1e8a4>;59002:6s|23:94?4|5;;i6o>4=33`>=><uz8957>52z?15`<?0279=k4nb:p67g=838p1?<>:c28977f20?0q~<=b;296~;5:90>563=238bf>{t::<1<7<t=30f>=><5;8h6ll4}r003?6=:r79?=478:?16a<fj2wx>>650;0x97542k:01?<l:878yv4413:1>v3=308a4>;5:m02:6s|22c94?4|5;9;6o>4=30`><0<uz88n7>52z?16`<e8279>k478:p66e=838p1?=>:9:897552hh0q~<<d;296~;5;=0i<63=2e8:1>{t::o1<7<t=310>0?<5;9>6ll4}r07=?6=:r798<478:?17c<fj2wx>9o50;0x972421201?:?:``8yv43j3:1>v3=478a4>;5;o0296s|25a94?4|5;>?6o>4=363><0<uz8?h7>52z?106<e8279?k466:p61c=838p1?:>:c2897252120q~<;f;296~;5<=03463=448bf>{t:<:1<7<t=364>g6<5;>;64;4}r065?6=:r798;4:9:?10=<fj2wx>8m50;0x973321201?;=:``8yv42l3:1>v3=578;<>;5=:0jn6s|24g94?4|5;?26o>4=371><3<uz8>j7>52z?112<e82799>466:p636=838p1?;9:c28973520<0q~<91;296~;5==0i<63=548;<>{t:?81<7<t=374>=><5;?36ll4}r057?6=:r799l4m0:?116<>=2wx>;:50;0x973>2<301?;m:``8yv41n3:1>v3=668;<>;5><0jn6s|26294?4|5;<26564=345>dd<uz8<=7>52z?12f<e8279:8465:p624=838p1?8n:c28970120<0q~<83;296~;5>00i<63=648:2>{t:>>1<7<t=344>g6<5;<36564}r041?6=:r79:l478:?12g<fj2wx>:850;0x970c2k:01?89:878yv40?3:1>v3=6b86=>;5>l0jn6s|29094?4|5;=j6564=35;>dd<uz83?7>52z?13f<?0279;44nb:p6=2=838p1?9i:c28971?20?0q~<75;296~;5?m0i<63=788:2>{t:1<1<7<t=35`>g6<5;=36484}r0;3?6=:r79;l4m0:?13g<?02wx>5650;0x971c21201?9j:``8yv4?13:1>v3=818a4>;5?00296s|29c94?4|5;=m6874=3:2>dd<uz8297>52z?1<a<?02794o4nb:p6<0=838p1?6i:9:897>d2hh0q~<67;296~;51;0i<63=8c8:1>{t:021<7<t=3;3>g6<5;2h6484}r0:=?6=:r794k4m0:?1<g<>>2wx>4o50;0x97>c2k:01?6j:9:8yv4>j3:1>v3=918;<>;5180jn6s|28a94?4|5;386o>4=3:`><3<uz82h7>52z?1=7<21279594nb:p6d>=838p1?o?:9:897?b2hh0q~<n9;296~;5i;03463=9g8bf>{t:hk1<7<t=3c6>g6<5;3n64;4}r0bf?6=:r79m>4m0:?1=c<>>2wx>lm50;0x97g52k:01?7j:848yv4fl3:1>v3=a18a4>;5i80346s|2`g94?4|5;k86564=3c7>dd<uz8jj7>52z?1e3<e82795k465:p6g6=838p1?o::4;897g02hh0q~<mb;296~;5j:03463=b08bf>{t:ki1<7<t=3`6>=><5;h96ll4}r0a`?6=:r79n54m0:?1f4<>=2wx>ok50;0x97d12k:01?l=:848yv4en3:1>v3=b48a4>;5j802:6s|2b294?4|5;h86o>4=3`7>=><uz8h=7>52z?1f3<?0279n:4nb:p6f4=838p1?l6:c2897d520?0q~<l3;296~;5j10>563=b`8bf>{t:jo1<7<t=3a5>=><5;i?6ll4}r0`b?6=:r79o5478:?1g0<fj2wx>i>50;0x97ee2k:01?m;:878yv4c93:1>v3=c88a4>;5k<02:6s|2e094?4|5;i36o>4=3a7><0<uz8o?7>52z?1g3<e8279o:478:p6a2=838p1?m6:9:897ef2hh0q~<k5;296~;5kj0i<63=c48:1>{t:m<1<7<t=3aa>0?<5;io6ll4}r0f5?6=:r79h4478:?1`2<fj2wx>h<50;0x97be21201?j7:``8yv4b;3:1>v3=dd8a4>;5l>0296s|2d694?4|5;nh6o>4=3f;><0<uz8n97>52z?1`g<e8279h:466:p6`0=838p1?j6:c2897bf2120q~<j7;296~;5lj03463=de8bf>{t:l21<7<t=3fe>g6<5;n364;4}r0f=?6=:r79hh4:9:?1a5<fj2wx>k:50;0x97cd21201?kn:``8yv4a=3:1>v3=ed8;<>;5mk0jn6s|2g494?4|5;l:6o>4=3gb><3<uz8m;7>52z?1ac<e8279io466:p6c>=838p1?kj:c2897cf20<0q~<i9;296~;5mj0i<63=ee8;<>{t:ok1<7<t=3ge>=><5;l;6ll4}r0ef?6=:r79j?4m0:?1ag<>=2wx>km50;0x97`62<301?h<:``8yv57?3:1>v3=fg8;<>;5nm0jn6s|31:94?4|5:::6564=3df>dd<uz9;57>52z?041<e8279ji465:p75g=838p1>>=:c2897`b20<0q~=?b;296~;4880i<63=fe8:2>{t;9i1<7<t=3de>g6<5::;6564}r13`?6=:r78<?478:?046<fj2wx?=k50;0x96622k:01?hj:878yv57n3:1>v3<0586=>;48?0jn6s|30c94?4|5:;96564=233>dd<uz9:n7>52z?051<?0278=<4nb:p74e=838p1>?8:c28967720?0q~=>d;296~;49<0i<63<108:2>{t;8o1<7<t=237>g6<5:;;6484}r12b?6=:r78=?4m0:?056<?02wx??>50;0x967221201>?9:``8yv5593:1>v3<198a4>;4980296s|33094?4|5:;<6874=23:>dd<uz99h7>52z?060<?0278>>4nb:p77c=838p1><8:9:896432hh0q~==f;296~;4:h0i<63<228:1>{t;::1<7<t=20;>g6<5:8?6484}r105?6=:r78>:4m0:?066<>>2wx?><50;0x96422k:01><9:9:8yv54;3:1>v3<298;<>;4:00jn6s|32694?4|5:8i6o>4=207><3<uz9897>52z?06d<21278>n4nb:p716=838p1>=7:9:896512hh0q~=;1;296~;4;h03463<368bf>{t;=81<7<t=21g>g6<5:9=64;4}r177?6=:r78?o4m0:?072<>>2wx?9:50;0x965f2k:01>=9:848yv53=3:1>v3<398a4>;4;00346s|35494?4|5:9i6564=21`>dd<uz9?;7>52z?07`<e8278?:465:p71>=838p1>=k:4;8965a2hh0q~=:3;296~;4<k03463<488bf>{t;<>1<7<t=26g>=><5:>j6ll4}r161?6=:r789=4m0:?00<<>=2wx?8850;0x962b2k:01>:n:848yv52?3:1>v3<4e8a4>;4<002:6s|34:94?4|5:>i6o>4=26`>=><uz9>57>52z?00`<?02788k4nb:p70g=838p1>;>:c28962f20?0q~=:b;296~;4=90>563<538bf>{t;hn1<7<t=2c2>=><5:3h6ll4}r1ba?6=:r78m?478:?0=a<fj2wx?lh50;0x96g22k:01>o9:878yv5e83:1>v3<ac86f>;4jh0i<6s|3c394?4|5:k36o>4=2;`><3<uz9i>7>52z?0e2<e82785i466:p7g5=838p1>o=:c2896?d20<0q~=m4;296~;4i80i<63<a18:2>{t;k?1<7<t=2c7>g6<5:3m6484}r1a2?6=:r78m>4m0:?0=`<?02wx?o950;0x96g021201>o9:``8yv5e03:1>v3<ab86f>;4k;0i<6s|3c;94?4|5:k26o>4=2;g><3<uz9ih7>53z?0fg<e8278nn478:?0fd<e:2wx?ok50;0x96dd2k:01>ln:9:8yv5en3:1>v3<ac8a4>;41o0296s|3b294?4|5:k86564=2;e>dd<uz9h=7>52z?0e1<?0278m=4nb:p7f3=839p1>m<:c2896e321201>m=:9:8yv5d>3:1>v3<c58a4>;4k;0i>6s|3b594?4|5:kh6o>4=2c3><3<uz9h47>52z?0e=<21278ml4nb:p7ag=838p1>mj:9:896e>2hh0q~=kb;296~;4ko03463<c`8bf>{t;mi1<7<t=2f1>g6<5:n864;4}r1g`?6=:r78h54:b:?0a2<e82wx?ik50;0x96b22k:01>m6:878yv5cn3:1>v3<d58a4>;4kh02:6s|3d294?4|5:im6o>4=2a:><0<uz9n=7>52z?0g`<e8278oi466:p7`4=838p1>j>:c2896ed20<0q~=j3;296~;4l90i<63<cc8;<>{t;l>1<7<t=2f7>=><5:n86ll4}r1f1?6=:r78h44:b:?0ac<e82wx?h850;0x96b12k:01>mn:878yv5bi3:1?v3<e98a4>;4m003463<e68a6>{t;lh1<7<t=2g:>g6<5:o<6564}r1fg?6=:r78h54m0:?0gf<>=2wx?hj50;0x96b721201>ml:``8yv5bm3:1>v3<d08;<>;4km0jn6s|3g094?5|5:l;6o>4=2d2>=><5:om6564}r1e7?6=:r78j<4m0:?0ac<e:2wx?k:50;0x96b>2k:01>mk:878yv5a=3:1>v3<d486=>;4l>0jn6s|41594?4|5:li6564=2d5>dd<uz>;47>52z?0bf<?0278j:4nb:p05?=838p1>hi:c28916720?0q~:?a;296~;38<0>n63;158a4>{t<9h1<7<t=521>g6<5:l=64;4}r63g?6=:r7?<<4m0:?0b2<>>2wx8=j50;0x96`d2k:01>h9:848yv27m3:1>v3<fc8a4>;4nh02:6s|41d94?4|5:ln6o>4=2d:><0<uz>:<7>52z?0ba<e8278j5478:p047=838p19>>:9:891672hh0q~:>2;296~;38?0>n63;1b8a4>{t<891<7<t=520>g6<5:l<64;4}r623?6=;r7?=84m0:?753<?027?=94m2:p04>=838p19?9:c2891732120q~:>9;296~;38<0i<63<f88:1>{t<8k1<7<t=2dg>=><5:l26ll4}r62f?6=:r78jh478:?0bd<fj2wx8<h50;1x917c2k:019?j:9:8917d2120q~:=0;296~;39l0i<63;1b8a6>{t<;;1<7<t=525>g6<5:lj64;4}r616?6=:r7?<?4:9:?741<fj2wx8>:50;0x914?212019<<:``8yv24=3:1>v3;288;<>;3:=0jn6s|42494?4|5=8h6o>4=50g><3<uz>8;7>52z?777<2j27?8<4m0:p06>=838p19<i:c28914420?0q~:<9;296~;3:l0i<63;258:2>{t<:k1<7<t=50:>g6<5=886484}r60f?6=:r7?>54m0:?762<>>2wx8>m50;0x914e2k:019<9:848yv24l3:1>v3;2`8a4>;3:<0346s|42g94?4|5=8n6564=50g>dd<uz>8j7>52z?776<2j27?844m0:p016=838p19=?:c28914320?0q~:;4;297~;3<;0i<63;428;<>;3<80i>6s|45794?4|5=>86o>4=562>=><uz>?:7>52z?777<e827?>;465:p011=838p19<n:9:891412hh0q~:;8;296~;3:k03463;268bf>{t<=i1<7=t=56b>g6<5=>i6564=56:>=><uz>?h7>52z?70g<e827?844m2:p01c=838p19=<:c28914020?0q~:;f;296~;3:o0>563;308bf>{t<?;1<7<t=576>=><5=?;6ll4}r656?6=:r7?9;478:?714<fj2wx8;=50;0x913>2k:019;n:878yv21<3:1>v3;5g86f>;3>l0i<6s|47794?4|5=?h6o>4=573><3<uz>=:7>52z?71g<e827?9<466:p031=838p19;9:c28913720<0q~:98;296~;3=<0i<63;558:2>{t<?31<7<t=57;>g6<5=?86484}r65e?6=:r7?9:4m0:?717<?02wx8;l50;0x913e212019;n:``8yv21k3:1>v3;6186f>;3??0i<6s|47f94?4|5=?o6o>4=572><3<uz><=7>53z?72c<e827?;=478:?72`<e:2wx8:<50;0x91172k:0198j:9:8yv20;3:1>v3;5g8a4>;3=:0296s|46694?4|5=?<6564=570>dd<uz><97>52z?71=<?027?994nb:p02?=839p1998:c28911?21201999:9:8yv20i3:1>v3;798a4>;3??0i>6s|46`94?4|5=<;6o>4=577><3<uz><o7>52z?71f<2127?9h4nb:p0=c=838p196=:9:8911c2hh0q~:7f;296~;30:03463;7d8bf>{t<0:1<7<t=5:5>g6<5=2<64;4}r6:5?6=:r7?4n4:b:?7=g<e82wx84<50;0x91>>2k:0199k:878yv2>;3:1>v3;898a4>;3?l02:6s|48694?4|5=286o>4=55g><0<uz>297>52z?7<7<e827?4<466:p0<0=838p196::c2891>720<0q~:67;296~;30=0i<63;7g8;<>{t<021<7<t=5:;>=><5=2<6ll4}r6:=?6=:r7?4i4:b:?7e6<e82wx84o50;0x91>f2k:0199j:878yv2>m3:1?v3;9b8a4>;31m03463;9c8a6>{t<0l1<7<t=5;g>g6<5=3i6564}r6b4?6=:r7?4n4m0:?7<5<>=2wx8l?50;0x91>32120196?:``8yv2f:3:1>v3;848;<>;3080jn6s|4`494?5|5=k?6o>4=5c6>=><5=k86564}r6b3?6=:r7?m84m0:?7e6<e:2wx8l650;0x91>c2k:0196>:878yv2f13:1>v3;8886=>;30k0jn6s|4c`94?4|5=km6564=5cb>dd<uz>io7>52z?7f5<?027?mo4nb:p0gb=838p19l<:c2891d320?0q~:me;296~;3j00>n63;c98a4>{t<kl1<7<t=5`5>g6<5=kj64;4}r6`4?6=:r7?n84m0:?7eg<>>2wx8n?50;0x91d72k:019on:848yv2d:3:1>v3;ag8a4>;3il02:6s|4b194?4|5=h96o>4=5cg><0<uz>h87>52z?7f4<e827?mn478:p0f3=838p19l::9:891d32hh0q~:l6;296~;3jh0>n63;d18a4>{t<j=1<7<t=5`4>g6<5=ki64;4}r6`f?6=;r7?o44m0:?7gd<?027?o54m2:p0fe=838p19mn:c2891e?2120q~:ld;296~;3j00i<63;ae8:1>{t<jo1<7<t=5`2>=><5=ko6ll4}r6`b?6=:r7?n?478:?7e`<fj2wx8i=50;1x91b62k:019j=:9:891b72120q~:k4;296~;3l;0i<63;d18a6>{t<m?1<7<t=5`b>g6<5=kn64;4}r6g2?6=:r7?n;4:9:?7f=<fj2wx8h650;0x91bd212019j8:``8yv2b13:1>v3;de8;<>;3l10jn6s|4dc94?4|5=o;6o>4=5g2><3<uz>nn7>52z?7a3<2j27?j84m0:p0`e=838p19k<:c2891b020?0q~:jd;296~;3m;0i<63;d98:2>{t<lo1<7<t=5fg>g6<5=n<6484}r6fb?6=:r7?hn4m0:?7`g<>>2wx8k>50;0x91ba2k:019jn:848yv2a93:1>v3;dd8a4>;3l00346s|4g094?4|5=o96564=5g2>dd<uz>m?7>52z?7a2<2j27?ji4m0:p0c2=838p19k;:c2891b?20?0q~:i8;297~;3n?0i<63;f68;<>;3n<0i>6s|4g;94?4|5=l<6o>4=5d6>=><uz>mm7>52z?7a3<e827?hl465:p0cd=838p19jj:9:891bf2hh0q~:ic;296~;3lo03463;dc8bf>{t=9:1<7=t=5df>g6<5=lm6564=5dg>=><uz?;=7>52z?7bc<e827?ji4m2:p154=838p19k8:c2891be20?0q~;?3;296~;3m:0>563;e48bf>{t=8?1<7<t=42:>=><5<:?6ll4}r722?6=:r7><l478:?640<fj2wx9<950;0x906c2k:018>j:878yv3603:1>v3:1286f>;2:;0i<6s|50;94?4|5<;;6o>4=427><3<uz?:m7>52z?64c<e827><8466:p14d=838p18>n:c28906320<0q~;>c;296~;2800i<63:098:2>{t=8n1<7<t=42`>g6<5<:<6484}r72a?6=:r7><o4m0:?643<?02wx9<h50;0x906a212018>j:``8yv3583:1>v3:1586f>;2:h0i<6s|53394?4|5<;:6o>4=426><3<uz?997>53z?666<e827>>9478:?667<e:2wx9?850;0x90432k:018<=:9:8yv35?3:1>v3:128a4>;28>0296s|53:94?4|5<:i6564=424>dd<uz?957>52z?64f<?027><54nb:p17b=839p18<m:c28904d212018<n:9:8yv35m3:1>v3:2b8a4>;2:h0i>6s|53d94?4|5<;?6o>4=42;><3<uz?8<7>52z?655<2127>=?4nb:p114=838p18=9:9:890562hh0q~;;3;296~;2;>03463:338bf>{t==>1<7<t=41b>g6<5<9i64;4}r771?6=:r7>8=4:b:?60c<e82wx99850;0x905c2k:018=>:878yv33?3:1>v3:3b8a4>;2;;02:6s|55:94?4|5<9<6o>4=412><0<uz??57>52z?673<e827>?8466:p11g=838p18=6:c28905320<0q~;;b;296~;2;10i<63:328;<>{t==i1<7<t=41`>=><5<9i6ll4}r77`?6=:r7>8<4:b:?612<e82wx99k50;0x905b2k:018==:878yv32:3:1?v3:518a4>;2=803463:4g8a6>{t=<91<7<t=472>g6<5<>m6564}r760?6=:r7>8=4m0:?671<>=2wx98;50;0x905?212018=;:``8yv32>3:1>v3:388;<>;2;<0jn6s|54c94?5|5<?36o>4=47:>=><5<?<6564}r76f?6=:r7>944m0:?612<e:2wx98m50;0x90262k:018=::878yv32l3:1>v3:3e86=>;2;o0jn6s|57d94?4|5<<86564=47f>dd<uz?<<7>52z?621<?027>9k4nb:p127=838p1888:c28900?20?0q~;82;296~;2>m0>n63:7b8a4>{t=>91<7<t=44b>g6<5<?n64;4}r740?6=:r7>:44m0:?61c<>>2wx9:;50;0x90032k:018;j:848yv30>3:1>v3:628a4>;2>;02:6s|56594?4|5<<=6o>4=442><0<uz?<47>52z?620<e827>:=478:p12?=838p1886:9:8900?2hh0q~;8a;296~;2>l0>n63:858a4>{t=>h1<7<t=44a>g6<5<?m64;4}r74b?6=;r7>;i4m0:?63`<?027>;n4m2:p1=6=838p189j:c28901d2120q~;71;296~;2>m0i<63:608:1>{t=181<7<t=446>=><5<<:6ll4}r7;7?6=:r7>:;478:?627<fj2wx95950;1x90>22k:01869:9:890>32120q~;78;296~;20?0i<63:858a6>{t=131<7<t=44f>g6<5<<964;4}r7;e?6=:r7>:l4:9:?62f<fj2wx94m50;0x90?72120186m:``8yv3>l3:1>v3:908;<>;20j0jn6s|58g94?4|5<3?6o>4=4;6><3<uz?2j7>52z?6=d<2j27>m44m0:p1d6=838p1878:c2890>e20?0q~;n1;296~;21?0i<63:8b8:2>{t=h81<7<t=4;2>g6<5<2i6484}r7b7?6=:r7>5=4m0:?6<c<>>2wx9l:50;0x90?42k:0186j:848yv3f=3:1>v3:938a4>;20m0346s|5`494?4|5<3=6564=4;6>dd<uz?j;7>52z?6=g<2j27>n<4m0:p1d>=838p1877:c2890>d20?0q~;nc;297~;2ih0i<63:ac8;<>;2i00i>6s|5`f94?4|5<ki6o>4=4c:>=><uz?ji7>52z?6=d<e827>4h465:p1d`=838p187=:9:890>b2hh0q~;m0;296~;21:03463:8g8bf>{t=k>1<7=t=4`1>g6<5<h86564=4`2>=><uz?i97>52z?6f6<e827>n<4m2:p1g0=838p187m:c2890>a20?0q~;m7;296~;21>0>563:988bf>{t=j31<7<t=4`g>=><5<h36ll4}r7`e?6=:r7>nh478:?6f<<fj2wx9nl50;0x90e62k:018m=:878yv3dk3:1>v3:c686f>;2l?0i<6s|5bf94?4|5<i?6o>4=4`;><3<uz?hi7>52z?6g6<e827>n4466:p1f`=838p18lj:c2890d?20<0q~;k0;296~;2jm0i<63:bb8:2>{t=m;1<7<t=4a3>g6<5<hi6484}r7g6?6=:r7>nk4m0:?6fd<?02wx9i=50;0x90e4212018m=:``8yv3c<3:1>v3:c986f>;2ll0i<6s|5e794?4|5<i>6o>4=4`:><3<uz?o57>53z?6`2<e827>h5478:?6`3<e:2wx9io50;0x90b?2k:018j9:9:8yv3cj3:1>v3:c68a4>;2jk0296s|5ea94?4|5<hm6564=4`a>dd<uz?oh7>52z?6g5<?027>nn4nb:p1`7=839p18ji:c2890c7212018jj:9:8yv3b:3:1>v3:e18a4>;2ll0i>6s|5d194?4|5<i36o>4=4``><3<uz?n87>52z?6g1<2127>o;4nb:p1c0=838p18kn:9:890c22hh0q~;i7;296~;2mk03463:e78bf>{t=o21<7<t=4gf>g6<5<om64;4}r7e=?6=:r7>j94:b:?546<e82wx9ko50;0x90`62k:018k::878yv3aj3:1>v3:f18a4>;2m?02:6s|5ga94?4|5<oi6o>4=4g6><0<uz?mh7>52z?6ad<e827>i4466:p1cc=838p18kk:c2890c?20<0q~;if;296~;2mj0i<63:e68;<>{t>9:1<7<t=4d3>=><5<om6ll4}r435?6=:r7>j84:b:?54g<e82wx:=<50;0x90`52k:018k9:878yv07>3:1?v39058a4>;18<034639028a6>{t>9=1<7<t=726>g6<5?:86564}r43<?6=:r7>j94m0:?6a=<>=2wx:=750;0x90cd212018k7:``8yv07i3:1>v3:ee8;<>;2m00jn6s|61g94?5|5?:h6o>4=72g>=><5?:i6564}r43b?6=:r7=<i4m0:?54g<e:2wx:<>50;0x90`22k:018k6:878yv0693:1>v3:f086=>;2n:0jn6s|63194?4|5?;<6564=731>dd<uz<987>52z?55=<?027==>4nb:p273=838p1;?m:c28937d20?0q~8=6;296~;1:80>n639318a4>{t>;=1<7<t=73f>g6<5?;964;4}r41<?6=:r7==i4m0:?556<>>2wx:?750;0x937?2k:01;?=:848yv05i3:1>v39168a4>;19?02:6s|63`94?4|5?;j6o>4=736><0<uz<9o7>52z?55<<e827==9478:p27b=838p1;?k:9:8937d2hh0q~8=e;296~;1:;0>n639398a4>{t>;l1<7<t=73e>g6<5?;864;4}r407?6=;r7=?<4m0:?577<?027=?=4m2:p262=838p1;==:c2893572120q~8<5;296~;1:80i<639148:1>{t>:<1<7<t=73:>=><5?;>6ll4}r403?6=:r7==l478:?553<fj2wx:>l50;1x935>2k:01;=n:9:8935?2120q~8<c;296~;1;h0i<639398a6>{t>:n1<7<t=701>g6<5?;=64;4}r40a?6=:r7==h4:9:?565<fj2wx:8>50;0x932321201;=i:``8yv0293:1>v39448;<>;1<90jn6s|64094?4|5?>36o>4=76:><3<uz<>?7>52z?50`<2j27=9i4m0:p202=838p1;:m:c28935a20?0q~8:5;296~;1<h0i<639418:2>{t><<1<7<t=766>g6<5?9m6484}r463?6=:r7=894m0:?506<>>2wx:8650;0x93202k:01;:=:848yv0213:1>v39478a4>;1<80346s|64c94?4|5?>j6564=76:>dd<uz<>n7>52z?50c<2j27=:84m0:p20e=838p1;:l:c28932720?0q~890;297~;1=l0i<6395g8;<>;1=m0i>6s|67394?4|5??m6o>4=77g>=><uz<=>7>52z?50`<e827=8?465:p235=838p1;:9:9:893252hh0q~894;296~;1<>034639428bf>{t>?21<7=t=745>g6<5?<<6564=746>=><uz<=57>52z?522<e827=:84m2:p23g=838p1;:i:c28932420?0q~89b;296~;1<k0>56394e8bf>{t>>n1<7<t=752>=><5?<h6ll4}r44a?6=:r7=;?478:?52a<fj2wx::h50;0x93122k:01;99:878yv0?83:1>v397c86f>;10h0i<6s|69394?4|5?=36o>4=74`><3<uz<3>7>52z?532<e827=:i466:p2=5=838p1;9=:c28930d20<0q~874;296~;1?80i<639718:2>{t>1?1<7<t=757>g6<5?<m6484}r4;2?6=:r7=;>4m0:?52`<?02wx:5950;0x931021201;99:``8yv0?03:1>v397b86f>;11;0i<6s|69;94?4|5?=26o>4=74g><3<uz<3h7>53z?5<g<e827=4n478:?5<d<e:2wx:5k50;0x93>d2k:01;6n:9:8yv0?n3:1>v397c8a4>;1>o0296s|68294?4|5?=86564=74e>dd<uz<2=7>52z?531<?027=;=4nb:p2<3=839p1;7<:c2893?321201;7=:9:8yv0>>3:1>v39958a4>;11;0i>6s|68594?4|5?=h6o>4=753><3<uz<247>52z?53=<2127=;l4nb:p2dg=838p1;7j:9:893?>2hh0q~8nb;296~;11o0346399`8bf>{t>hi1<7<t=7c1>g6<5?k864;4}r4b`?6=:r7=m54:b:?5f2<e82wx:lk50;0x93g22k:01;76:878yv0fn3:1>v39a58a4>;11h02:6s|6c294?4|5?3m6o>4=7;:><0<uz<i=7>52z?5=`<e827=5i466:p2g4=838p1;o>:c2893?d20<0q~8m3;296~;1i90i<6399c8;<>{t>k>1<7<t=7c7>=><5?k86ll4}r4a1?6=:r7=m44:b:?5fc<e82wx:o850;0x93g12k:01;7n:878yv0ei3:1?v39b98a4>;1j0034639b68a6>{t>kh1<7<t=7`:>g6<5?h<6564}r4ag?6=:r7=m54m0:?5=f<>=2wx:oj50;0x93g721201;7l:``8yv0em3:1>v39a08;<>;11m0jn6s|6b094?5|5?i;6o>4=7a2>=><5?hm6564}r4`7?6=:r7=o<4m0:?5fc<e:2wx:n:50;0x93g>2k:01;7k:878yv0d=3:1>v39a486=>;1i>0jn6s|6e594?4|5?ii6564=7a5>dd<uz<o47>52z?5gf<?027=o:4nb:p2a?=838p1;mi:c2893b720?0q~8ka;296~;1l<0>n639e58a4>{t>mh1<7<t=7f1>g6<5?i=64;4}r4gg?6=:r7=h<4m0:?5g2<>>2wx:ij50;0x93ed2k:01;m9:848yv0cm3:1>v39cc8a4>;1kh02:6s|6ed94?4|5?in6o>4=7a:><0<uz<n<7>52z?5ga<e827=o5478:p2`7=838p1;j>:9:893b72hh0q~8j2;296~;1l?0>n639eb8a4>{t>l91<7<t=7f0>g6<5?i<64;4}r4f3?6=;r7=i84m0:?5a3<?027=i94m2:p2`>=838p1;k9:c2893c32120q~8j9;296~;1l<0i<639c88:1>{t>lk1<7<t=7ag>=><5?i26ll4}r4ff?6=:r7=oh478:?5gd<fj2wx:hh50;1x93cc2k:01;kj:9:893cd2120q~8i0;296~;1ml0i<639eb8a6>{t>o;1<7<t=7f5>g6<5?ij64;4}r4e6?6=:r7=h?4:9:?5`1<fj2wx;=:50;0x93`?21201;h<:``8yv17=3:1>v39f88;<>;1n=0jn6s|71494?4|5?lh6o>4=7dg><3<uz=;;7>52z?447<2j27<=<4m0:p35>=838p1;hi:c2893`420?0q~9?9;296~;1nl0i<639f58:2>{t?9k1<7<t=7d:>g6<5?l86484}r53f?6=:r7=j54m0:?5b2<>>2wx;=m50;0x93`e2k:01;h9:848yv17l3:1>v39f`8a4>;1n<0346s|71g94?4|5?ln6564=7dg>dd<uz=;j7>52z?446<2j27<=44m0:p346=838p1:>?:c2893`320?0q~9>4;297~;09;0i<638128;<>;0980i>6s|70794?4|5>;86o>4=632>=><uz=::7>52z?447<e827=j;465:p341=838p1;hn:9:893`12hh0q~9>8;296~;1nk034639f68bf>{t?8i1<7=t=63b>g6<5>;i6564=63:>=><uz=:h7>52z?45g<e827<=44m2:p34c=838p1:><:c2893`020?0q~9>f;296~;1no0>5638008bf>{t?:;1<7<t=606>=><5>8;6ll4}r506?6=:r7<>;478:?464<fj2wx;>=50;0x924>2k:01:<n:878yv14<3:1>v382g86f>;0;l0i<6s|72794?4|5>8h6o>4=603><3<uz=8:7>52z?46g<e827<><466:p361=838p1:<9:c28924720<0q~9<8;296~;0:<0i<638258:2>{t?:31<7<t=60;>g6<5>886484}r50e?6=:r7<>:4m0:?467<?02wx;>l50;0x924e21201:<n:``8yv14k3:1>v383186f>;0<?0i<6s|72f94?4|5>8o6o>4=602><3<uz=?=7>53z?47c<e827<8=478:?47`<e:2wx;9<50;0x92272k:01:=j:9:8yv13;3:1>v382g8a4>;0::0296s|75694?4|5>8<6564=600>dd<uz=?97>52z?46=<?027<>94nb:p31?=839p1::8:c28922?21201::9:9:8yv13i3:1>v38498a4>;0<?0i>6s|75`94?4|5>9;6o>4=607><3<uz=?o7>52z?46f<2127<>h4nb:p30c=838p1:;=:9:8922c2hh0q~9:f;296~;0=:0346384d8bf>{t??:1<7<t=675>g6<5>?<64;4}r555?6=:r7<9n4:b:?42g<e82wx;;<50;0x923>2k:01::k:878yv11;3:1>v38598a4>;0<l02:6s|77694?4|5>?86o>4=66g><0<uz==97>52z?417<e827<9<466:p330=838p1:;::c28923720<0q~997;296~;0==0i<6384g8;<>{t??21<7<t=67;>=><5>?<6ll4}r55=?6=:r7<9i4:b:?436<e82wx;;o50;0x923f2k:01::j:878yv11m3:1?v386b8a4>;0>m0346386c8a6>{t??l1<7<t=64g>g6<5><i6564}r544?6=:r7<9n4m0:?415<>=2wx;:?50;0x923321201:;?:``8yv10:3:1>v38548;<>;0=80jn6s|76494?5|5>=?6o>4=656>=><5>=86564}r543?6=:r7<;84m0:?436<e:2wx;:650;0x923c2k:01:;>:878yv1013:1>v385886=>;0=k0jn6s|79`94?4|5>=m6564=65b>dd<uz=3o7>52z?4<5<?027<;o4nb:p3=b=838p1:6<:c2892>320?0q~97e;296~;0000>n638998a4>{t?1l1<7<t=6:5>g6<5>=j64;4}r5:4?6=:r7<484m0:?43g<>>2wx;4?50;0x92>72k:01:9n:848yv1>:3:1>v387g8a4>;0?l02:6s|78194?4|5>296o>4=65g><0<uz=287>52z?4<4<e827<;n478:p3<3=838p1:6::9:892>32hh0q~966;296~;00h0>n638a18a4>{t?0=1<7<t=6:4>g6<5>=i64;4}r5:f?6=;r7<544m0:?4=d<?027<554m2:p3<e=838p1:7n:c2892??2120q~96d;296~;0000i<6387e8:1>{t?0o1<7<t=6:2>=><5>=o6ll4}r5:b?6=:r7<4?478:?43`<fj2wx;l=50;1x92g62k:01:o=:9:892g72120q~9n4;296~;0i;0i<638a18a6>{t?h?1<7<t=6:b>g6<5>=n64;4}r5b2?6=:r7<4;4:9:?4<=<fj2wx;o650;0x92gd21201:o8:``8yv1e13:1>v38ae8;<>;0i10jn6s|7cc94?4|5>h;6o>4=6`2><3<uz=in7>52z?4f3<2j27<o84m0:p3ge=838p1:l<:c2892g020?0q~9md;296~;0j;0i<638a98:2>{t?ko1<7<t=6cg>g6<5>k<6484}r5ab?6=:r7<mn4m0:?4eg<>>2wx;n>50;0x92ga2k:01:on:848yv1d93:1>v38ad8a4>;0i00346s|7b094?4|5>h96564=6`2>dd<uz=h?7>52z?4f2<2j27<oi4m0:p3f2=838p1:l;:c2892g?20?0q~9l8;297~;0k?0i<638c68;<>;0k<0i>6s|7b;94?4|5>i<6o>4=6a6>=><uz=hm7>52z?4f3<e827<ml465:p3fd=838p1:oj:9:892gf2hh0q~9lc;296~;0io034638ac8bf>{t?m:1<7=t=6af>g6<5>im6564=6ag>=><uz=o=7>52z?4gc<e827<oi4m2:p3a4=838p1:l8:c2892ge20?0q~9k3;296~;0j:0>5638b48bf>{t?l?1<7<t=6f:>=><5>n?6ll4}r5f2?6=:r7<hl478:?4`0<fj2wx;h950;0x92bc2k:01:jj:878yv1b03:1>v38e286f>;0n;0i<6s|7d;94?4|5>o;6o>4=6f7><3<uz=nm7>52z?4`c<e827<h8466:p3`d=838p1:jn:c2892b320<0q~9jc;296~;0l00i<638d98:2>{t?ln1<7<t=6f`>g6<5>n<6484}r5fa?6=:r7<ho4m0:?4`3<?02wx;hh50;0x92ba21201:jj:``8yv1a83:1>v38e586f>;0nh0i<6s|7g394?4|5>o:6o>4=6f6><3<uz=m97>53z?4b6<e827<j9478:?4b7<e:2wx;k850;0x92`32k:01:h=:9:8yv1a?3:1>v38e28a4>;0l>0296s|7g:94?4|5>ni6564=6f4>dd<uz=m57>52z?4`f<?027<h54nb:p3cb=839p1:hm:c2892`d21201:hn:9:8yv1am3:1>v38fb8a4>;0nh0i>6s|7gd94?4|5>o?6o>4=6f;><3<uz2;<7>52z?4a5<2127<i?4nb:p<44=838p15>9:9:89=662hh0q~6>3;296~;?8>034637038bf>{t08>1<7<t=92b>g6<51:i64;4}r:21?6=:r73==4:b:?;5c<e82wx4<850;0x9=6c2k:015>>:878yv>6?3:1>v370b8a4>;?8;02:6s|80:94?4|51:<6o>4=922><0<uz2:57>52z?;43<e8273<8466:p<4g=838p15>6:c289=6320<0q~6>b;296~;?810i<637028;<>{t08i1<7<t=92`>=><51:i6ll4}r:2`?6=:r73=<4:b:?;62<e82wx4<k50;0x9=6b2k:015>=:878yv>5:3:1?v37218a4>;?:80346371g8a6>{t0;91<7<t=902>g6<51;m6564}r:10?6=:r73==4m0:?;41<>=2wx4?;50;0x9=6?212015>;:``8yv>5>3:1>v37088;<>;?8<0jn6s|83c94?5|51836o>4=90:>=><518<6564}r:1f?6=:r73>44m0:?;62<e:2wx4?m50;0x9=762k:015>::878yv>5l3:1>v370e86=>;?8o0jn6s|82d94?4|51986564=90f>dd<uz2?<7>52z?;71<?0273>k4nb:p<17=838p15=8:c289=5?20?0q~6;2;296~;?;m0>n6374b8a4>{t0=91<7<t=91b>g6<518n64;4}r:70?6=:r73?44m0:?;6c<>>2wx49;50;0x9=532k:015<j:848yv>3>3:1>v37328a4>;?;;02:6s|85594?4|519=6o>4=912><0<uz2?47>52z?;70<e8273?=478:p<1?=838p15=6:9:89=5?2hh0q~6;a;296~;?;l0>n637558a4>{t0=h1<7<t=91a>g6<518m64;4}r:7b?6=;r738i4m0:?;0`<?02738n4m2:p<06=838p15:j:c289=2d2120q~6:1;296~;?;m0i<637308:1>{t0<81<7<t=916>=><519:6ll4}r:67?6=:r73?;478:?;77<fj2wx48950;1x9=322k:015;9:9:89=332120q~6:8;296~;?=?0i<637558a6>{t0<31<7<t=91f>g6<519964;4}r:6e?6=:r73?l4:9:?;7f<fj2wx4;m50;0x9=07212015;m:``8yv>1l3:1>v37608;<>;?=j0jn6s|87g94?4|51<?6o>4=946><3<uz2=j7>52z?;2d<2j273;44m0:p<26=838p1588:c289=3e20?0q~681;296~;?>?0i<6375b8:2>{t0>81<7<t=942>g6<51?i6484}r:47?6=:r73:=4m0:?;1c<>>2wx4::50;0x9=042k:015;j:848yv>0=3:1>v37638a4>;?=m0346s|86494?4|51<=6564=946>dd<uz2<;7>52z?;2g<2j2734<4m0:p<2>=838p1587:c289=3d20?0q~68c;297~;??h0i<6377c8;<>;??00i>6s|86f94?4|51=i6o>4=95:>=><uz2<i7>52z?;2d<e82739h465:p<2`=838p158=:9:89=3b2hh0q~670;296~;?>:0346375g8bf>{t01>1<7=t=9:1>g6<51286564=9:2>=><uz2397>52z?;<6<e82734<4m2:p<=0=838p158m:c289=3a20?0q~677;296~;?>>0>5637688bf>{t0031<7<t=9:g>=><51236ll4}r::e?6=:r734h478:?;<<<fj2wx44l50;0x9=?62k:0157=:878yv>>k3:1>v379686f>;?i?0i<6s|88f94?4|513?6o>4=9:;><3<uz22i7>52z?;=6<e827344466:p<<`=838p156j:c289=>?20<0q~6n0;296~;?0m0i<6378b8:2>{t0h;1<7<t=9;3>g6<512i6484}r:b6?6=:r734k4m0:?;<d<?02wx4l=50;0x9=?42120157=:``8yv>f<3:1>v379986f>;?il0i<6s|8`794?4|513>6o>4=9::><3<uz2j57>53z?;e2<e8273m5478:?;e3<e:2wx4lo50;0x9=g?2k:015o9:9:8yv>fj3:1>v37968a4>;?0k0296s|8`a94?4|512m6564=9:a>dd<uz2jh7>52z?;=5<?02734n4nb:p<g7=839p15oi:c289=d7212015oj:9:8yv>e:3:1>v37b18a4>;?il0i>6s|8c194?4|51336o>4=9:`><3<uz2i87>52z?;=1<212735;4nb:p<f0=838p15ln:9:89=d22hh0q~6l7;296~;?jk034637b78bf>{t0j21<7<t=9`f>g6<51hm64;4}r:`=?6=:r73o94:b:?;`6<e82wx4no50;0x9=e62k:015l::878yv>dj3:1>v37c18a4>;?j?02:6s|8ba94?4|51hi6o>4=9`6><0<uz2hh7>52z?;fd<e8273n4466:p<fc=838p15lk:c289=d?20<0q~6lf;296~;?jj0i<637b68;<>{t0m:1<7<t=9a3>=><51hm6ll4}r:g5?6=:r73o84:b:?;`g<e82wx4i<50;0x9=e52k:015l9:878yv>c>3:1?v37d58a4>;?l<034637d28a6>{t0m=1<7<t=9f6>g6<51n86564}r:g<?6=:r73o94m0:?;f=<>=2wx4i750;0x9=dd212015l7:``8yv>ci3:1>v37be8;<>;?j00jn6s|8eg94?5|51nh6o>4=9fg>=><51ni6564}r:gb?6=:r73hi4m0:?;`g<e:2wx4h>50;0x9=e22k:015l6:878yv>b93:1>v37c086=>;?k:0jn6s|8g194?4|51o<6564=9g1>dd<uz2m87>52z?;a=<?0273i>4nb:p<c3=838p15km:c289=cd20?0q~6i6;296~;?n80>n636018a4>{t0o=1<7<t=9gf>g6<51o964;4}r:e<?6=:r73ii4m0:?;a6<>>2wx4k750;0x9=c?2k:015k=:848yv>ai3:1>v37e68a4>;?m?02:6s|8g`94?4|51oj6o>4=9g6><0<uz2mo7>52z?;a<<e8273i9478:p<cb=838p15kk:9:89=cd2hh0q~6ie;296~;?n;0>n636098a4>{t0ol1<7<t=9ge>g6<51o864;4}r;37?6=;r72<<4m0:?:47<?0272<=4m2:p=52=838p14>=:c289<672120q~7?5;296~;?n80i<637e48:1>{t19<1<7<t=9g:>=><51o>6ll4}r;33?6=:r73il478:?;a3<fj2wx5=l50;1x9<6>2k:014>n:9:89<6?2120q~7?c;296~;>8h0i<636098a6>{t19n1<7<t=9d1>g6<51o=64;4}r;3a?6=:r73ih4:9:?;b5<fj2wx5?>50;0x9<73212014>i:``8yv?593:1>v36148;<>;>990jn6s|93094?4|50;36o>4=83:><3<uz39?7>52z?:5`<2j272>i4m0:p=72=838p14?m:c289<6a20?0q~7=5;296~;>9h0i<636118:2>{t1;<1<7<t=836>g6<50:m6484}r;13?6=:r72=94m0:?:56<>>2wx5?650;0x9<702k:014?=:848yv?513:1>v36178a4>;>980346s|93c94?4|50;j6564=83:>dd<uz39n7>52z?:5c<2j272?84m0:p=7e=838p14?l:c289<7720?0q~7<0;297~;>:l0i<6362g8;<>;>:m0i>6s|92394?4|508m6o>4=80g>=><uz38>7>52z?:5`<e8272=?465:p=65=838p14?9:9:89<752hh0q~7<4;296~;>9>034636128bf>{t1:21<7=t=815>g6<509<6564=816>=><uz3857>52z?:72<e8272?84m2:p=6g=838p14?i:c289<7420?0q~7<b;296~;>9k0>56361e8bf>{t1:o1<7<t=81g><0<509h6o?4}r;74?6=:r72?k478:?:7f<e82wx59=50;0x9<2520<014:>:c38yv?3=3:1>v36458;<>;><80i<6s|95:94?4|50><6484=865>g7<uz3?m7>52z?:0<<?02728;4m0:p=1b=838p14:l:8489<2e2k;0q~7;f;296~;><l0346364c8a4>{t1<81<7<t=872><0<50?;6o?4}r;60?6=:r729>478:?:15<e82wx58950;0x9<3120<014;::c38yv?213:1>v36598;<>;>=<0i<6s|94a94?4|50?i6484=87b>g7<uz3>i7>52z?:1a<?02729l4m0:p=37=838p148?:8489<3a2k;0q~793;296~;>>;0346365g8a4>{t1?<1<7<t=846><0<50<?6o?4}r;5<?6=:r72::478:?:21<e82wx5;l50;0x9<0f20<01486:c38yv?1l3:1>v366b8;<>;>>00i<6s|96294?4|50<m6484=84f>g7<uz3<>7>52z?:34<?0272:h4m0:p=23=838p149;:8489<142k;0q~787;296~;>??034636728a4>{t1>k1<7<t=85:><0<50=36o?4}r;4g?6=:r72;o478:?:3=<e82wx5:h50;0x9<1b20<0149k:c38yv??93:1>v36818;<>;>?m0i<6s|99694?4|50286484=8:1>g7<uz33:7>52z?:<0<?02724?4m0:p==?=838p1467:8489<>02k;0q~77b;296~;>0h034636868a4>{t11o1<7<t=8:g><0<502h6o?4}r;:4?6=:r724k478:?:<f<e82wx54=50;0x9<?520<0147>:c38yv?>=3:1>v36958;<>;>180i<6s|98:94?4|503<6484=8;5>g7<uz32m7>52z?:=<<?02725;4m0:p=<b=838p147l:8489<?e2k;0q~76f;296~;>1l0346369c8a4>{t1h81<7<t=8c2><0<50k;6o?4}r;b0?6=:r72m>478:?:e5<e82wx5l950;0x9<g120<014o::c38yv?f13:1>v36a98;<>;>i<0i<6s|9`a94?4|50ki6484=8cb>g7<uz3ji7>52z?:ea<?0272ml4m0:p=g7=838p14l?:8489<ga2k;0q~7m3;296~;>j;034636ag8a4>{t1k<1<7<t=8`6><0<50h?6o?4}r;a<?6=:r72n:478:?:f1<e82wx5ol50;0x9<df20<014l6:c38yv?el3:1>v36bb8;<>;>j00i<6s|9b294?4|50hm6484=8`f>g7<uz3h>7>52z?:g4<?0272nh4m0:p=f3=838p14m;:8489<e42k;0q~7l7;296~;>k?034636c28a4>{t1jk1<7<t=8a:><0<50i36o?4}r;`g?6=:r72oo478:?:g=<e82wx5nh50;0x9<eb20<014mk:c38yv?c93:1>v36d18;<>;>km0i<6s|9e694?4|50n86484=8f1>g7<uz3o:7>52z?:`0<?0272h?4m0:p=a?=838p14j7:8489<b02k;0q~7kb;296~;>lh034636d68a4>{t1mi1<7=t=8g4>0b<50oj68j4=8g0><c<uz3oh7>53z?:ag<2l272ih4:d:?:a2<>m2wx5ik50;0x9<`62<n014km:8g8yv?cn3:1>v36e58;<>;>m?0jn6s|9d294?4|50o36564=8gb>dd<uz3n=7>52z?:af<?0272ih4nb:p=`4=838p14ki:9:89<`62hh0q~7i2;297~;>m<0jn636e28a7>;>m?02h6s|9g194?5|50o26ll4=8g4>g5<50oj64j4}r;e0?6=;r72ii4nb:?:ag<e;272ih46d:p=c3=838p14h?:``89<`620n0q~7ia;297~;>n?0i<636f68;<>;>n002:6s|9g`94?4|50l<6o>4=8d:><3<uz3mo7>55z?:b=<fj272ik4:b:?:af<2j272i54:b:?:a1<2j2wx5kj50;7x9<`>2hh014ki:c089<cd2k8014k7:c089<c32k80q~o?5;296~;f8=0i<63n018;<>{ti9<1<7;t=`27>0`<5h:;68h4=`22>0`<5h:868h4=8df>dd<uzk;;7>53z?b45<e827j<<478:?:bc<?02wxm=650;0x9d662k:014hi:c08yvg713:1>v3n028a4>;f8;0346s|a1c94?4|5h:96o>4=8df><3<uzk?>7>52z?b06<e827j8<478:pe=e=838p1<?::848962d2k:0q~o7d;296~;6:102:63>138a4>{ti1o1<7<t=01a><0<588>6o>4}rc;b?6=:r7:8h466:?27=<e82wxm4>50;0x940620<01<:m:c28yvg>93:1>v3>758:2>;6=l0i<6s|a8094?4|582<6484=052>g6<uzk2?7>52z?2=d<>>27:494m0:pe<2=838p1<ok:84894?02k:0q~o65;296~;6k902:63>a`8a4>{ti0<1<7<t=0f0><0<5ol1n=5rs`;4>5<5s4;n:779;<3a`?d73tyj554?:3y>5c?=1?16=h=5b19~wd?>2909w0<?c;;5?87a>3h;7p}n9`83>7}::8l15;5221;9f5=z{h3i6=4={<006??1348:o7l?;|qb=f<72;q6>9;5979>67`=j91vl7k:181842033=70<;2;`3?xuf1l0;6?u227`9=3=::<?1n=5rs`;e>5<5s48<i779;<05<?d73tyjm=4?:3y>6<7=1?16>:l5b19~wdg62909w0<n4;;5?87c83h;7p}na383>7}::k=15;5229g9f5=z{hk86=4={<0`e??1348i87l?;|qbe1<72;q6?l85979>6f1=j91vlo::18185c;33=70=6e;`3?xufi?0;6?u24129=3=:;jh1n=5rs`c4>5<5s4>9h779;<1e<?d73tyjm54?:3y>00g=1?168?;5b19~wdg>2909w0:77;;5?822:3h;7p}na`83>7}:<k>15;5246d9f5=z{hki6=4={<6f5??134>jo7l?;|qbef<72;q6>ij5979>6d7=j91vlok:181837m33=70:k9;`3?xufil0;6?u252`9=3=:=9<1n=5rs`ce>5<5s4?=4779;<707?d73tyjn=4?:3y>1<3=1?169;>5b19~wdd62909w0;l2;;5?83?l3h;7p}nb383>7}:=ll15;525cc9f5=z{hh86=4={<42g??134?n;7l?;|qbf1<72;q6:975979>242=j91vll::181800>33=708;1;`3?xufj?0;6?u26`19=3=:>?o1n=5rs``4>5<5s48m<779;<0ge?d73tyjn54?:3y>2a6=1?16:4l5b19~wdd>2909w08id;;5?80d03h;7p}nb`83>7}:?;k15;526g79f5=z{hhi6=4={<563??134=9>7l?;|qbff<72;q6;5:5979>31`=j91vllk:18181e933=7098c;`3?xufjl0;6?u27eg9=3=:?h31n=5rs``e>5<5s42;n779;<5g2?d73tyjo=4?:3y><6>=1?164==5b19~wde62909w0695;;5?8>483h;7p}nc383>7}:;9915;522df9f5=z{hi86=4={<::6??1342>h7l?;|qbg1<72;q64oh5979><=g=j91vlm::1818>bk33=706m7;`3?xufk?0;6?u290;9=3=:0l>1n=5rs`a4>5<5s4h3h767;<;25?d73tyjo54?:3y>740=1?16?=>5b19~wde>2909w0==9;;5?856;3h;7p}nc`83>7}:;:i15;523349f5=z{hii6=4={<17b??1349857l?;|qbgf<72:q6m=m5899>e=d=j916m5o5899~wdec2908w0o?e;:;?8g7k3h;70o?b;:;?xufkl0;6>u2a029<==:i9o1n=52a1f9<==z{him6=4<{<c26?>?34k:<7l?;<c3b?>?3tyjh=4?:2y>e42=0116m<<5b19>e47=011vlj>:1808g6>32370o>4;`3?8g6;3237p}nd383>6}:i8214552a049f5=:i8?1455rs`f0>5<4s4k:m767;<c2<?d734k:;767;|qb`1<72:q6m<m5899>e4g=j916m<75899~wdb22908w0o>e;:;?8g6k3h;70o>b;:;?xufl?0;6>u234g9<==:;0k1n=5238`9<==z{hn<6=4<{<c14?>?34k:i7l?;<c2`?>?3tyjh54?:2y>e74=0116m?>5b19>e4`=011vlj6:1808g5<32370o=2;`3?8g593237p}nd`83>6}:i;<14552a369f5=:i;91455rs`fa>5<4s4k94767;<c12?d734k99767;|qb`f<72:q6m?o5899>e7>=j916m?95899~wdbc2908w0o=c;:;?8g5i3h;70o=9;:;?xufll0;6>u2a3g9<==:i;i1n=52a3`9<==z{hnm6=4<{<c04?>?34k9i7l?;<c1`?>?3tyji=4?:2y>e64=0116m>>5b19>e7`=011vlk>:180851832370=:e;`3?852n3237p}ne383>6}:i:>14552a209f5=:i:;1455rs`g0>5<4s4k8:767;<c00?d734k8?767;|qba1<72:q6m>65899>e60=j916m>;5899~wdc22908w0o<a;:;?8g403h;70o<7;:;?xufm?0;6>u2a2a9<==:i:k1n=52a2;9<==z{ho<6=4<{<c0a?>?34k8o7l?;<c0f?>?3tyji54?:2y>e16=0116m>k5b19>e6b=011vlk6:1808g3;32370o;0;`3?8g4n3237p}ne`83>6}:;?8145523729f5=:;?;1455rs`ga>5<4s49=8767;<156?d7349=?767;|qbaf<72:q6?;85899>732=j916?;;5899~wdcc2908w0=98;:;?851>3h;70=97;:;?xufml0;6>u237c9<==:;?21n=5237;9<==z{hom6=4<{<15g?>?349=m7l?;<15f?>?3tyjj=4?:2y>73c=0116?;m5b19>73b=011vlh>:180850832370=9e;`3?851n3237p}nf383>6}:;>81455234a9f5=:;<n1455rs`d0>5<4s49<8767;<144?d7349<=767;|qbb1<72:q6?:85899>722=j916?:;5899~wd`22908w0=88;:;?850>3h;70=87;:;?xufn?0;6>u236c9<==:;>21n=5236;9<==z{hl<6=4<{<14g?>?349<m7l?;<14f?>?3tyjj54?:2y>72c=0116?:m5b19>72b=011vlh6:18085?832370=8e;`3?850n3237p}nf`83>6}:;18145523929f5=:;1;1455rs`da>5<4s4938767;<1;6?d73493?767;|qbbf<72:q6?585899>7=2=j916?5;5899~wd`c2908w0=78;:;?850:3h;70=83;:;?xufnl0;6>u239c9<==:;1<1n=523959<==z{hlm6=4<{<1;g?>?3493m7l?;<1;f?>?3tyi<=4?:2y>7=e=j916?5j5899>=6e=011vo>>:1818?39323707<d;ca?xue8;0;6?u29549<==:1=81mo5rsc20>5<5s43?n767;<;73?ge3tyi<94?:3y>=06=011659m5ac9~wg622909w07:5;:;?8?293ki7p}m0783>7}:1<k145529449eg=z{k:<6=4={<;6b?>?343>n7om;|qa4=<72:q6?5k5899>7=>=j916?575899~wg6>2909w0794;:;?8?183ki7p}m0`83>7}:1?3145529779eg=z{k:i6=4={<;5a?>?343=m7om;|qa4f<72;q65:=5899>=3`=ik1vo>k:1818?0032370784;ca?xue8l0;6?u296f9<==:1>31mo5rsc2e>5<5s433>767;<;4a?ge3tyi==4?:3y>==1=011655=5ac9~wg762909w077c;:;?8??03ki7p}m1383>7}:10;1455299f9eg=z{k;86=4<{<1:4?>?3493i7l?;<1;b?>?3tyi=94?:3y>=<0=011654<5ac9~wg722909w076b;:;?8?>?3ki7p}m1783>7}:1h:1455298a9eg=z{k;<6=4={<;b1?>?343j=7om;|qa5=<72;q65lo5899>=d0=ik1vo?6:1818?fn323707nb;ca?xue9h0;6?u29c69<==:1k:1mo5rsc3a>5<5s43i5767;<;a1?ge3tyi=n4?:3y>=gc=01165oo5ac9~wg7c2909w07l3;:;?8?en3ki7p}m1d83>6}:;08145523829f5=:;0;1455rsc3e>5<5s43h4767;<;`0?ge3tyi>=4?:3y>=fb=01165n75ac9~wg462909w07k2;:;?8?dm3ki7p}m2383>7}:1m=145529e19eg=z{k886=4={<c71?>?343o47om;|qa61<72:q6m995899>e13=j916m9:5899~wg422908w0o;9;:;?8g3?3h;70o;6;:;?xue:?0;6>u2a5`9<==:i=31n=52a5:9<==z{k8<6=4<{<c7`?>?34k?n7l?;<c7e?>?3tyi>54?:2y>e1`=0116m9j5b19>e1e=011vo<6:18085><32370=62;`3?85>;3237p}m2`83>6}:i<;14552a5d9f5=:i=o1455rsc0a>5<4s4k>?767;<c65?d734k><767;|qa6f<72:q6m8;5899>e05=j916m8<5899~wg4c2908w0o:7;:;?8g2=3h;70o:4;:;?xue:l0;6>u2a4;9<==:i<=1n=52a449<==z{k8m6=4<{<c6f?>?34k>57l?;<c6<?>?3tyi?=4?:2y>e0b=0116m8l5b19>e0g=011vo=>:1808g2n32370o:d;`3?8g2k3237p}m3383>6}:i?;14552a4d9f5=:i<o1455rsc10>5<4s4k=?767;<c55?d734k=<767;|qa71<72:q6?485899>7<2=j916?4;5899~wg522908w0o95;:;?8g1;3h;70o92;:;?xue;?0;6>u2a759<==:i??1n=52a769<==z{k9<6=4<{<c5=?>?34k=;7l?;<c52?>?3tyi?54?:2y>e3d=0116m;75b19>e3>=011vo=6:1808g1l32370o9b;`3?8g1i3237p}m3`83>6}:i?l14552a7f9f5=:i?i1455rsc1a>5<4s4k<=767;<c5b?d734k=i767;|qa7f<72:q6m:=5899>e27=j916m:>5899~wg5c2908w0o85;:;?8g0;3h;70o82;:;?xue;l0;6>u2a659<==:i>?1n=52a669<==z{k9m6=4<{<1:<?>?3492:7l?;<1:3?>?3tyi8=4?:2y>e2?=0116m:95b19>e20=011vo:>:1808g0j32370o89;`3?8g003237p}m4383>6}:i>n14552a6`9f5=:i>k1455rsc60>5<4s4k<j767;<c4`?d734k<o767;|qa01<72:q6m5?5899>e2`=j916m:k5899~wg222908w0o73;:;?8g?93h;70o70;:;?xue<?0;6>u2a919f5=:i1814552a979<==z{k><6=4<{<c;3?>?34k397l?;<c;0?>?3tyi854?:2y>e=?=0116m595b19>e=0=011vo:6:1808g?j32370o79;`3?8g?03237p}m4`83>6}:;0k1455238:9f5=:;031455rsc6a>5<d9r7iik4m0:?:5c<e:272=h4m2:?:5f<2n272=o4:f:?;b7<e:273j<4m2:?;ac<2n273ih4:f:?;g0<e:273o94m2:?;g7<2n273o<4:f:?;==<e:2735:4m2:?;=0<2n273594:f:?;2g<e:273:l4m2:?;2=<2n273::4:f:?;7`<e:273?i4m2:?;7g<2n273?l4:f:?;54<e:273==4m2:?;4`<2n273<i4:f:?4a1<e:27<i>4m2:?4a4<2n27<i=4:f:?4f2<e:27<n;4m2:?4f1<2n27<n>4:f:?4<d<e:27<444m2:?4<2<2n27<4;4:f:?41a<e:27<9n4m2:?41d<2n27<944:f:?475<e:27<>k4m2:?46a<2n27<>n4:f:?446<e:27<<?4m2:?445<2n27=jk4:f:?5`3<e:27=h84m2:?5`6<2n27=h?4:f:?5e<<e:27=m54m2:?5e3<2n27=m84:f:?53f<e:27=;o4m2:?53<<2n27=;54:f:?50c<e:27=8h4m2:?50f<2n27=8o4:f:?567<e:27=><4m2:?55c<2n27==h4:f:?6b0<e:27>j94m2:?6b7<2n27>j<4:f:?6g=<e:27>o:4m2:?6g0<2n27>o94:f:?6=g<e:27>5l4m2:?6==<2n27>5:4:f:?62`<e:27>:i4m2:?62g<2n27>:l4:f:?604<e:27>8=4m2:?67`<2n27>?i4:f:?651<e:27>=>4m2:?654<2n27>==4:f:?7a2<e:27?i;4m2:?7a1<2n27?i>4:f:?7fd<e:27?n44m2:?7f2<2n27?n;4:f:?7<a<e:27?4n4m2:?7<d<2n27?444:f:?725<e:27?9k4m2:?71a<2n27?9n4:f:?776<e:27???4m2:?775<2n27?>k4:f:?743<e:27?<84m2:?746<2n27?<?4:f:?0`<<e:278h54m2:?0`3<2n278h84:f:?0ef<e:278mo4m2:?0e<<2n278m54:f:?1gf<2n279oo4:f:?1f<<2n279n54:f:?1=6<2n2795?4:f:?1<5<2n279;k4:f:?12a<2n279:n4:f:?11d<2n279944:f:?102<2n2798;4:f:?171<2n279?>4:f:?164<2n279>=4:f:?14`<2n279<i4:f:?2bg<2n27:jl4:f:?2a=<2n27:i:4:f:?2g7<2n27:o<4:f:?2ec<2n27:mh4:f:?2=f<2n27:5o4:f:?2<<<2n27:454:f:?233<2n27:;84:f:?226<2n27::?4:f:?215<2n27:8k4:f:?27a<2n27:?n4:f:?26d<2n27:>44:f:?252<2n27:=;4:f:?014<2n2789=4:f:?07`<2n278?i4:f:?06g<2n278>l4:f:?05=<2n278=:4:f:?040<2n278<94:f:?1b7<2n279j<4:f:?1`c<2n279hh4:f:?1e3<2n279m84:f:?2`0<2n27:h94:f:?241<2n27:<>4:f:pf1e=838p1o6j:8789gbf2k:0q~l;d;296~;f<=0i<63<5e86f>{tj=o1<7<t=`7;>g6<5:?m68l4}r`7b?6=:r7j9l4m0:?024<2j2wxn8>50;0x9d3d2k:01>8<:4`8yvd293:1>v3n5d8a4>;4><0>n6s|b4094?4|5h<;6o>4=244>0d<uzh>?7>52z?b27<e8278:44:b:pf02=838p1l8;:c28960e2<h0q~l:5;296~;f>?0i<63<6e86f>{tj<<1<7<t=`4;>g6<5:<m68l4}r`63?6=:r7j:l4m0:?034<2j2wxn8650;0x9d212k:01>9<:4`8yvd213:1>v3n6b8a4>;4?<0>n6s|b4c94?4|5h<n6o>4=254>0d<uzh>n7>52z?b35<e8278;44:b:pf0e=838p1l9=:c28961e2<h0q~l:d;296~;f?=0i<63<7e86f>{tj<o1<7<t=`55>g6<5:=m68l4}r`6b?6=:r7j;54m0:?0<4<2j2wxn;>50;0x9d1f2k:01>6<:4`8yvd193:1>v3n7b8a4>;40<0>n6s|b7094?4|5h=n6o>4=2:4>0d<uzh=?7>52z?b0=<e8278444:b:pf32=838p1l6?:c2896>e2<h0q~l95;296~;f0;0i<63<8e86f>{tj?<1<7<t=81e>0d<5h2?6o>4}r`53?6=:r72894:b:?b<3<e82wxn;650;0x9<2>2<h01l67:c28yvd113:1>v364d86f>;f0h0i<6s|b7c94?4|50?868l4=`2a>g6<uzh=n7>52z?:1=<2j27j<i4m0:pf3e=838p14;k:4`89d6a2k:0q~l9d;296~;>>;0>n63n108a4>{tj?o1<7<t=`6b>g6<5:2m68l4}r`5b?6=:r72::4:b:?b56<e82wxn:>50;0x9<0d2<h01l?::c28yvd093:1>v367086f>;f9>0i<6s|b6094?4|50==68l4=`3:>g6<uzh<?7>52z?:3g<2j27j=o4m0:pf22=838p146?:4`89d7c2k:0q~l85;296~;>0<0>n63n1g8a4>{tj><1<7<t=8:b>0d<5h8:6o>4}r`43?6=:r724k4:b:?b66<e82wxn:650;0x9<?32<h01l<::c28yvd013:1>v3n4b8a4>;4180>n6s|b6c94?4|503268l4=`04>g6<uzh<n7>52z?:=`<2j27j>44m0:pf2e=838p14o<:4`89d4e2k:0q~l8d;296~;>i10>n63n2e8a4>{tj>o1<7<t=8cg>0d<5h8m6o>4}r`4b?6=:r72n?4:b:?b74<e82wxn5>50;0x9<d02<h01l=<:c28yvd?93:1>v36bb86f>;f;<0i<6s|b9094?4|50i:68l4=`14>g6<uzh3?7>52z?:g3<2j27j?44m0:pf=2=838p1l:j:c2896?42<h0q~l75;296~;>kk0>n63n3c8a4>{tj1<1<7<t=8f3>0d<5h9o6o>4}r`;3?6=:r72h84:b:?b7c<e82wxn5650;0x9<bf2<h01l:>:c28yvd?13:1>v3n518a4>;41<0>n6s|b9c94?4|5h?96o>4=2;4>0d<uzh3n7>52z?b11<e8278544:b:pf=e=838p1l;9:c2896?e2<h0q~l7f;29=~;e100jn63mcg8a6>;ekj0i>63mc98a6>;ek=0i>63mc18a6>;ejj0i>63mb98a6>;ej=0i>6s|b8:94?4|5knj6564=cc1>dd<uzh2m7>52z?a=d<fj27i5h467:pf<d=838p1o7m:``89g?b2020q~l6c;296~;e1l02563m9b8bf>{tj0o1<7<t=c;f>dd<5kk964;4}r`:b?6=:r7i5k4nb:?ae7<>12wxnl>50;0x9gg72hh01o7j:878yvdf93:1>v3ma08bf>;ei;0246s|b`194?4|5kk86ll4=c;f><0<uzhj87>53z?af2<2l27inl4:d:?af6<>m2wxnl;50;1x9gde2<n01olj:4f89gd020o0q~ln6;297~;ejo0>h63mc386`>;ejk02i6s|b`594?5|5ki868j4=ca5>0b<5khm64k4}r`b<?6=;r7io:4:d:?agd<2l27io>46e:pfd?=839p1omm:4f89geb2<n01om8:8g8yvdfi3:1>v3md086`>;ekk02i6s|b``94?4|5kh?6564=c`5>dd<uzhjo7>52z?af=<?027inl4nb:pfdb=838p1oll:9:89gdb2hh0q~lne;296~;ek903463mc38bf>{tjhl1<7<t=ca7>=><5ki=6ll4}r`a4?6=:r7io5478:?agd<fj2wxno?50;0x9ged21201omj:``8yvde:3:1>v3mcg8;<>;el80jn6s|be094?5|5kh>6ll4=c`0>g5<5kh=64j4}r`g7?6=;r7in44nb:?af2<e;27inl46d:pfa2=839p1olk:``89gde2k901olj:8f8yvdc=3:1?v3mc08bf>;ejo0i?63mc38:`>{tjm<1<7=t=ca6>dd<5ki86o=4=ca5><b<uzho;7>53z?ag<<fj27io:4m3:?agd<>l2wxni650;1x9gec2hh01omm:c189geb20n0q~lk9;296~;el90jn63md08:`>{tjmh1<7<t=c;3>dd<5kk:6474}r`gg?6=:r7i5<4nb:?ae4<>02wxnij50;0x9g?52hh01oo>:858yvdcm3:1>v3m928bf>;ei802m6s|bed94?4|5k3?6ll4=c;e><?<uzhn<7>52z?a=0<fj27i5k468:pf`7=838p1o79:``89g?a20=0q~lj2;296~;e1>0jn63m9g8:e>{tjl91<7ot=c;4><3<5k3=64;4=c;6><3<5k3?64;4=c;0><3<5k3964;4=c;2><3<5k3;64;4=c`7>g6<5kh>64;4}r`f0?6=ir7i5:466:?a=3<>>27i58466:?a=1<>>27i5>466:?a=7<>>27i5<466:?a=5<>>27in54m0:?af<<>=2wxnh;50;cx9g?020=01o79:8589g?220=01o7;:8589g?420=01o7=:8589g?620=01o7?:8589gdd2k:01olk:878yvdb>3:1mv3m968:<>;e1?02463m948:<>;e1=02463m928:<>;e1;02463m908:<>;e1902463mc18a4>;ek80296s|bd594?2|5ki?6o>4=ca6><3<5k3m6484=cc2><0<uzhn47>54z?ag=<e827io4465:?a=c<>=27im<465:pf`?=839p1oml:c289gec20?01oo=:848yvdbi3:1?v3mcg8a4>;el902963ma38:3>{tjlh1<7<<{<;e<??2343o;7??;<;g6?77343hh7??;<;`<?77343h?7??;<;aa?77343i57??;<;a0?77343jj7??;<;be?77343j97??;<;b4?773432n7??;<;:2?773432=7??;<;;g?773433;7??;<;;6?77343<h7??;<;4<?77343<?7??;<;5a?77343=57??;<;50?77343>j7??;<;6e?77343>97??;<;64?77343?n7??;<;72?77343?=7??;<;0g?77343n87l?;<;f1??23tyiin4?:31x9<`?20<014j8:0389<b528;014mk:0389<e?28;014m<:0389<db28;014l6:0389<d328;014oi:0389<gf28;014o::0389<g728;0147m:0389<?128;0147>:0389<>d28;01468:0389<>528;0149k:0389<1?28;0149<:0389<0b28;01486:0389<0328;014;i:0389<3f28;014;::0389<3728;014:m:0389<2128;014:>:0389<5d28;014k7:c289<c>20?0q~ljd;2966}:1o215:529e5957=:1m81=?529bf957=:1j21=?529b1957=:1ko1=?529c;957=:1k>1=?529`d957=:1hk1=?529`7957=:1h:1=?5298`957=:10<1=?52983957=:11i1=?52995957=:1181=?5296f957=:1>21=?52961957=:1?o1=?5297;957=:1?>1=?5294d957=:1<k1=?52947957=:1<:1=?5295`957=:1=<1=?52953957=:1:i1=?529da9f5=:1ln1585rscgf>5<5;r72j5468:?:`2<6;272h?4>3:?:ga<6;272o54>3:?:g6<6;272nh4>3:?:f<<6;272n94>3:?:ec<6;272ml4>3:?:e0<6;272m=4>3:?:=g<6;2725;4>3:?:=4<6;2724n4>3:?:<2<6;2724?4>3:?:3a<6;272;54>3:?:36<6;272:h4>3:?:2<<6;272:94>3:?:1c<6;2729l4>3:?:10<6;2729=4>3:?:0g<6;2728;4>3:?:04<6;272?n4>3:?:ac<e8272j=465:pfc4=839p1oh?:c289g`621201oki:c08yvda;3:1>v3mf08a4>;emo0346srn0f:3?6=9rBij95rn0f:<?6=9rBij95rn0f:=?6=9rBij95rn0f:e?6=9rBij95rn0f:f?6=9rBij95rn0f:g?6=9rBij95rn0f:`?6=9rBij95rn0f:a?6=9rBij95rn0f:b?6=9rBij95rn0fb4?6=9rBij95rn0fb5?6=9rBij95rn0fb6?6=9rBij95rn0fb7?6=9rBij95rn0fb0?6=9rBij95rn0fb1?6=9rBij95rn0fb2?6=9rBij95rn0fb3?6=9rBij95rn0fb<?6=9rBij95rn0fb=?6=9rBij95rn0fbe?6=9rBij95rn0fbf?6=9rBij95rn0fbg?6=9rBij95rn0fb`?6=9rBij95rn0fba?6=9rBij95rn0fbb?6=9rBij95rn0fa4?6=9rBij95rn0fa5?6=9rBij95rn0fa6?6=9rBij95rn0fa7?6=9rBij95rn0fa0?6=9rBij95rn0fa1?6=9rBij95rn0fa2?6=9rBij95rn0fa3?6=9rBij95rn0fa<?6=9rBij95rn0fa=?6=9rBij95rn0fae?6=9rBij95rn0faf?6=9rBij95rn0fag?6=9rBij95rn0fa`?6=9rBij95rn0faa?6=9rBij95rn0fab?6=9rBij95rn0f`4?6=9rBij95rn0f`5?6=9rBij95rn0f`6?6=9rBij95rn0f`7?6=9rBij95rn0f`0?6=9rBij95rn0f`1?6=9rBij95rn0f`2?6=9rBij95rn0f`3?6=9rBij95rn0f`<?6=9rBij95rn0f`=?6=9rBij95rn0f`e?6=9rBij95rn0f`f?6=9rBij95rn0f`g?6=9rBij95rn0f``?6=9rBij95rn0f`a?6=9rBij95rn0f`b?6=9rBij95rn0fg4?6=9rBij95rn0fg5?6=9rBij95rn0fg6?6=9rBij95rn0fg7?6=9rBij95rn0fg0?6=9rBij95rn0fg1?6=9rBij95rn0fg2?6=9rBij95rn0fg3?6=9rPm47?t8`8~Lg`33td:hi650;3xLg`33td:hi750;3xLg`33td:hio50;3xLg`33td:hil50;3xLg`33td:him50;3xLg`33td:hij50;3xLg`33td:hik50;3xLg`33td:hih50;3xLg`33td:hh>50;3xLg`33td:hh?50;3xLg`33td:hh<50;3xLg`33td:hh=50;3xLg`33td:hh:50;3xLg`33td:hh;50;3xLg`33td:hh850;3xLg`33td:hh950;3xLg`33td:hh650;3xLg`33td:hh750;3xLg`33td:hho50;3xLg`33td:hhl50;3xLg`33td:hhm50;3xLg`33td:hhj50;3xLg`33td:hhk50;3xLg`33td:hhh50;3xLg`33td:hk>50;3xLg`33td:hk?50;3xLg`33td:hk<50;3xLg`33td:hk=50;3xLg`33td:hk:50;3xLg`33td:hk;50;3xLg`33td:hk850;3xLg`33td:hk950;3xLg`33td:hk650;3xLg`33td:hk750;3xLg`33td:hko50;3xLg`33td:hkl50;3xLg`33td:hkm50;3xLg`33td:hkj50;3xLg`33td:hkk50;3xLg`33td:hkh50;3xLg`33td:i=>50;3xLg`33td:i=?50;3xLg`33td:i=<50;3xLg`33td:i==50;3xLg`33td:i=:50;3xLg`33td:i=;50;3xLg`33td:i=850;3xLg`33td:i=950;3xLg`33td:i=650;3xLg`33td:i=750;3xLg`33td:i=o50;3xLg`33td:i=l50;3xLg`33td:i=m50;3xLg`33td:i=j50;3xLg`33td:i=k50;3xLg`33td:i=h50;3xLg`33td:i<>50;3xLg`33td:i<?50;3xLg`33td:i<<50;3xLg`33td:i<=50;3xLg`33td:i<:50;3xLg`33td:i<;50;3xLg`33td:i<850;3xLg`33td:i<950;3xLg`33td:i<650;3xLg`33td:i<750;3xLg`33td:i<o50;3xLg`33td:i<l50;3xLg`33td:i<m50;3xLg`33td:i<j50;3xLg`33td:i<k50;3xLg`33td:i<h50;3xLg`33td:i?>50;3xLg`33td:i??50;3xLg`33td:i?<50;3xLg`33td:i?=50;3xLg`33td:i?:50;3xLg`33td:i?;50;3xLg`33td:i?850;3xLg`33td:i?950;3xLg`33td:i?650;3xLg`33td:i?750;3xLg`33td:i?o50;3xLg`33td:i?l50;3xLg`33td:i?m50;3xLg`33td:i?j50;3xLg`33td:i?k50;3xLg`33td:i?h50;3xLg`33td:i>>50;3xLg`33td:i>?50;3xLg`33td:i><50;3xLg`33td:i>=50;3xLg`33td:i>:50;3xLg`33td:i>;50;3xLg`33td:i>850;3xLg`33td:i>950;3xLg`33td:i>650;3xLg`33td:i>750;3xLg`33td:i>o50;3xLg`33td:i>l50;3xLg`33td:i>m50;3xLg`33td:i>j50;3xLg`33td:i>k50;3xLg`33td:i>h50;3xLg`33td:i9>50;3xLg`33td:i9?50;3xLg`33td:i9<50;3xLg`33td:i9=50;3xLg`33td:i9:50;3xLg`33td:i9;50;3xLg`33td:i9850;3xLg`33td:i9950;3xLg`33td:i9650;3xLg`33td:i9750;3xLg`33td:i9o50;3xLg`33td:i9l50;3xLg`33td:i9m50;3xLg`33td:i9j50;3xLg`33td:i9k50;3xLg`33td:i9h50;3xLg`33td:i8>50;3xLg`33td:i8?50;3xLg`33td:i8<50;3xLg`33td:i8=50;3xLg`33td:i8:50;3xLg`33td:i8;50;3xLg`33td:i8850;3xLg`33td:i8950;3xLg`33td:i8650;3xLg`33td:i8750;3xLg`33td:i8o50;3xLg`33td:i8l50;3xLg`33td:i8m50;3xLg`33td:i8j50;3xLg`33td:i8k50;3xLg`33td:i8h50;3xLg`33td:i;>50;3xLg`33td:i;?50;3xLg`33td:i;<50;3xLg`33td:i;=50;3xLg`33td:i;:50;3xLg`33td:i;;50;3xLg`33td:i;850;3xLg`33td:i;950;3xLg`33td:i;650;3xLg`33td:i;750;3xLg`33td:i;o50;3xLg`33td:i;l50;3xLg`33td:i;m50;3xLg`33td:i;j50;3xLg`33td:i;k50;3xLg`33td:i;h50;3xLg`33td:i:>50;3xLg`33td:i:?50;3xLg`33td:i:<50;3xLg`33td:i:=50;3xLg`33td:i::50;3xLg`33td:i:;50;3xLg`33td:i:850;3xLg`33td:i:950;3xLg`33td:i:650;3xLg`33td:i:750;3xLg`33td:i:o50;3xLg`33td:i:l50;3xLg`33td:i:m50;3xLg`33td:i:j50;3xLg`33td:i:k50;3xLg`33td:i:h50;3xLg`33td:i5>50;3xLg`33td:i5?50;3xLg`33td:i5<50;3xLg`33td:i5=50;3xLg`33td:i5:50;3xLg`33td:i5;50;3xLg`33td:i5850;3xLg`33td:i5950;3xLg`33td:i5650;3xLg`33td:i5750;3xLg`33td:i5o50;3xLg`33td:i5l50;3xLg`33td:i5m50;3xLg`33td:i5j50;3xLg`33td:i5k50;3xLg`33td:i5h50;3xLg`33td:i4>50;3xLg`33td:i4?50;3xLg`33td:i4<50;3xLg`33td:i4=50;3xLg`33td:i4:50;3xLg`33td:i4;50;3xLg`33td:i4850;3xLg`33td:i4950;3xLg`33td:i4650;3xLg`33td:i4750;3xLg`33td:i4o50;3xLg`33td:i4l50;3xLg`33td:i4m50;3xLg`33td:i4j50;3xLg`33td:i4k50;3xLg`33td:i4h50;3xLg`33td:il>50;3xLg`33td:il?50;3xLg`33td:il<50;3xLg`33td:il=50;3xLg`33td:il:50;3xLg`33td:il;50;3xLg`33td:il850;3xLg`33td:il950;3xLg`33td:il650;3xLg`33td:il750;3xLg`33td:ilo50;3xLg`33td:ill50;3xLg`33td:ilm50;3xLg`33td:ilj50;3xLg`33td:ilk50;3xLg`33td:ilh50;3xLg`33td:io>50;3xLg`33td:io?50;3xLg`33td:io<50;3xLg`33td:io=50;3xLg`33td:io:50;3xLg`33td:io;50;3xLg`33td:io850;3xLg`33td:io950;3xLg`33td:io650;3xLg`33td:io750;3xLg`33td:ioo50;3xLg`33td:iol50;3xLg`33td:iom50;3xLg`33td:ioj50;3xLg`33td:iok50;3xLg`33td:ioh50;3xLg`33td:in>50;3xLg`33td:in?50;3xLg`33td:in<50;3xLg`33td:in=50;3xLg`33td:in:50;3xLg`33td:in;50;3xLg`33td:in850;3xLg`33td:in950;3xLg`33td:in650;3xLg`33td:in750;3xLg`33td:ino50;3xLg`33td:inl50;3xLg`33td:inm50;3xLg`33td:inj50;3xLg`33td:ink50;3xLg`33td:inh50;3xLg`33td:ii>50;3xLg`33td:ii?50;3xLg`33td:ii<50;3xLg`33td:ii=50;3xLg`33td:ii:50;3xLg`33td:ii;50;3xLg`33td:ii850;3xLg`33td:ii950;3xLg`33td:ii650;3xLg`33td:ii750;3xLg`33td:iio50;3xLg`33td:iil50;3xLg`33td:iim50;3xLg`33td:iij50;3xLg`33td:iik50;3xLg`33td:iih50;3xLg`33td:ih>50;3xLg`33td:ih?50;3xLg`33td:ih<50;3xLg`33td:ih=50;3xLg`33td:ih:50;3xLg`33td:ih;50;3xLg`33td:ih850;3xLg`33td:ih950;3xLg`33td:ih650;3xLg`33td:ih750;3xLg`33td:iho50;3xLg`33td:ihl50;3xLg`33td:ihm50;3xLg`33td:ihj50;3xLg`33td:ihk50;3xLg`33td:ihh50;3xLg`33td:ik>50;3xLg`33td:ik?50;3xLg`33td:ik<50;3xLg`33td:ik=50;3xLg`33td:ik:50;3xLg`33td:ik;50;3xLg`33td:ik850;3xLg`33td:ik950;3xLg`33td:ik650;3xLg`33td:ik750;3xLg`33td:iko50;3xLg`33td:ikl50;3xLg`33td:ikm50;3xLg`33td:ikj50;3xLg`33td:ikk50;3xLg`33td:ikh50;3xLg`33td:j=>50;3xLg`33td:j=?50;3xLg`33td:j=<50;3xLg`33td:j==50;3xLg`33td:j=:50;3xLg`33td:j=;50;3xLg`33td:j=850;3xLg`33td:j=950;3xLg`33td:j=650;3xLg`33td:j=750;3xLg`33td:j=o50;3xLg`33td:j=l50;3xLg`33td:j=m50;3xLg`33td:j=j50;3xLg`33td:j=k50;3xLg`33td:j=h50;3xLg`33td:j<>50;3xLg`33td:j<?50;3xLg`33td:j<<50;3xLg`33td:j<=50;3xLg`33td:j<:50;3xLg`33td:j<;50;3xLg`33td:j<850;3xLg`33td:j<950;3xLg`33td:j<650;3xLg`33td:j<750;3xLg`33td:j<o50;3xLg`33td:j<l50;3xLg`33td:j<m50;3xLg`33td:j<j50;3xLg`33td:j<k50;3xLg`33td:j<h50;3xLg`33td:j?>50;3xLg`33td:j??50;3xLg`33td:j?<50;3xLg`33td:j?=50;3xLg`33td:j?:50;3xLg`33td:j?;50;3xLg`33td:j?850;3xLg`33td:j?950;3xLg`33td:j?650;3xLg`33td:j?750;3xLg`33td:j?o50;3xLg`33td:j?l50;3xLg`33td:j?m50;3xLg`33td:j?j50;3xLg`33td:j?k50;3xLg`33td:j?h50;3xLg`33td:j>>50;3xLg`33td:j>?50;3xLg`33td:j><50;3xLg`33td:j>=50;3xLg`33td:j>:50;3xLg`33td:j>;50;3xLg`33td:j>850;3xLg`33td:j>950;3xLg`33td:j>650;3xLg`33td:j>750;3xLg`33td:j>o50;3xLg`33td:j>l50;3xLg`33td:j>m50;3xLg`33td:j>j50;3xLg`33td:j>k50;3xLg`33td:j>h50;3xLg`33td:j9>50;3xLg`33td:j9?50;3xLg`33td:j9<50;3xLg`33td:j9=50;3xLg`33td:j9:50;3xLg`33td:j9;50;3xLg`33td:j9850;3xLg`33td:j9950;3xLg`33td:j9650;3xLg`33td:j9750;3xLg`33td:j9o50;3xLg`33td:j9l50;3xLg`33td:j9m50;3xLg`33td:j9j50;3xLg`33td:j9k50;3xLg`33td:j9h50;3xLg`33td:j8>50;3xLg`33td:j8?50;3xLg`33td:j8<50;3xLg`33td:j8=50;3xLg`33td:j8:50;3xLg`33td:j8;50;3xLg`33td:j8850;3xLg`33td:j8950;3xLg`33td:j8650;3xLg`33td:j8750;3xLg`33td:j8o50;3xLg`33td:j8l50;3xLg`33td:j8m50;3xLg`33td:j8j50;3xLg`33td:j8k50;3xLg`33td:j8h50;3xLg`33td:j;>50;3xLg`33td:j;?50;3xLg`33td:j;<50;3xLg`33td:j;=50;3xLg`33td:j;:50;3xLg`33td:j;;50;3xLg`33td:j;850;3xLg`33td:j;950;3xLg`33td:j;650;3xLg`33td:j;750;3xLg`33td:j;o50;3xLg`33td:j;l50;3xLg`33td:j;m50;3xLg`33td:j;j50;3xLg`33td:j;k50;3xLg`33td:j;h50;3xLg`33td:j:>50;3xLg`33td:j:?50;3xLg`33td:j:<50;3xLg`33td:j:=50;3xLg`33td:j::50;3xLg`33td:j:;50;3xLg`33td:j:850;3xLg`33td:j:950;3xLg`33td:j:650;3xLg`33td:j:750;3xLg`33td:j:o50;3xLg`33td:j:l50;3xLg`33td:j:m50;3xLg`33td:j:j50;3xLg`33td:j:k50;3xLg`33td:j:h50;3xLg`33td:j5>50;3xLg`33td:j5?50;3xLg`33td:j5<50;3xLg`33td:j5=50;3xLg`33td:j5:50;3xLg`33td:j5;50;3xLg`33td:j5850;3xLg`33td:j5950;3xLg`33td:j5650;3xLg`33td:j5750;3xLg`33td:j5o50;3xLg`33td:j5l50;3xLg`33td:j5m50;3xLg`33td:j5j50;3xLg`33td:j5k50;3xLg`33td:j5h50;3xLg`33td:j4>50;3xLg`33td:j4?50;3xLg`33td:j4<50;3xLg`33td:j4=50;3xLg`33td:j4:50;3xLg`33td:j4;50;3xLg`33td:j4850;3xLg`33td:j4950;3xLg`33td:j4650;3xLg`33td:j4750;3xLg`33td:j4o50;3xLg`33td:j4l50;3xLg`33td:j4m50;3xLg`33td:j4j50;3xLg`33td:j4k50;3xLg`33td:j4h50;3xLg`33td:jl>50;3xLg`33td:jl?50;3xLg`33td:jl<50;3xLg`33td:jl=50;3xLg`33td:jl:50;3xLg`33td:jl;50;3xLg`33td:jl850;3xLg`33td:jl950;3xLg`33td:jl650;3xLg`33td:jl750;3xLg`33td:jlo50;3xLg`33td:jll50;3xLg`33td:jlm50;3xLg`33td:jlj50;3xLg`33td:jlk50;3xLg`33td:jlh50;3xLg`33td:jo>50;3xLg`33td:jo?50;3xLg`33td:jo<50;3xLg`33td:jo=50;3xLg`33td:jo:50;3xLg`33td:jo;50;3xLg`33td:jo850;3xLg`33td:jo950;3xLg`33td:jo650;3xLg`33td:jo750;3xLg`33td:joo50;3xLg`33td:jol50;3xLg`33td:jom50;3xLg`33td:joj50;3xLg`33td:jok50;3xLg`33td:joh50;3xLg`33td:jn>50;3xLg`33td:jn?50;3xLg`33td:jn<50;3xLg`33td:jn=50;3xLg`33td:jn:50;3xLg`33td:jn;50;3xLg`33td:jn850;3xLg`33td:jn950;3xLg`33td:jn650;3xLg`33td:jn750;3xLg`33td:jno50;3xLg`33td:jnl50;3xLg`33td:jnm50;3xLg`33td:jnj50;3xLg`33td:jnk50;3xLg`33td:jnh50;3xLg`33td:ji>50;3xLg`33td:ji?50;3xLg`33td:ji<50;3xLg`33td:ji=50;3xLg`33td:ji:50;3xLg`33td:ji;50;3xLg`33td:ji850;3xLg`33td:ji950;3xLg`33td:ji650;3xLg`33td:ji750;3xLg`33td:jio50;3xLg`33td:jil50;3xLg`33td:jim50;3xLg`33td:jij50;3xLg`33td:jik50;3xLg`33td:jih50;3xLg`33td:jh>50;3xLg`33td:jh?50;3xLg`33td:jh<50;3xLg`33td:jh=50;3xLg`33td:jh:50;3xLg`33td:jh;50;3xLg`33td:jh850;3xLg`33td:jh950;3xLg`33td:jh650;3xLg`33td:jh750;3xLg`33td:jho50;3xLg`33td:jhl50;3xLg`33td:jhm50;3xLg`33td:jhj50;3xLg`33td:jhk50;3xLg`33td:jhh50;3xLg`33td:jk>50;3xLg`33td:jk?50;3xLg`33td:jk<50;3xLg`33td:jk=50;3xLg`33td:jk:50;3xLg`33td:jk;50;3xLg`33td:jk850;3xLg`33td:jk950;3xLg`33td:jk650;3xLg`33td:jk750;3xLg`33td:jko50;3xLg`33td:jkl50;3xLg`33td:jkm50;3xLg`33td:jkj50;3xLg`33td:jkk50;3xLg`33td:jkh50;3xLg`33td9<=>50;3xLg`33td9<=?50;3xLg`33td9<=<50;3xLg`33td9<==50;3xLg`33td9<=:50;3xLg`33td9<=;50;3xLg`33td9<=850;3xLg`33td9<=950;3xLg`33td9<=650;3xLg`33td9<=750;3xLg`33td9<=o50;3xLg`33td9<=l50;3xLg`33td9<=m50;3xLg`33td9<=j50;3xLg`33td9<=k50;3xLg`33td9<=h50;3xLg`33td9<<>50;3xLg`33td9<<?50;3xLg`33td9<<<50;3xLg`33td9<<=50;3xLg`33td9<<:50;3xLg`33td9<<;50;3xLg`33td9<<850;3xLg`33td9<<950;3xLg`33td9<<650;3xLg`33td9<<750;3xLg`33td9<<o50;3xLg`33td9<<l50;3xLg`33td9<<m50;3xLg`33td9<<j50;3xLg`33td9<<k50;3xLg`33td9<<h50;3xLg`33td9<?>50;3xLg`33td9<??50;3xLg`33td9<?<50;3xLg`33td9<?=50;3xLg`33td9<?:50;3xLg`33td9<?;50;3xLg`33td9<?850;3xLg`33td9<?950;3xLg`33td9<?650;3xLg`33td9<?750;3xLg`33td9<?o50;3xLg`33td9<?l50;3xLg`33td9<?m50;3xLg`33td9<?j50;3xLg`33td9<?k50;3xLg`33td9<?h50;3xLg`33td9<>>50;3xLg`33td9<>?50;3xLg`33td9<><50;3xLg`33td9<>=50;3xLg`33td9<>:50;3xLg`33td9<>;50;3xLg`33td9<>850;3xLg`33td9<>950;3xLg`33td9<>650;3xLg`33td9<>750;3xLg`33td9<>o50;3xLg`33td9<>l50;3xLg`33td9<>m50;3xLg`33td9<>j50;3xLg`33td9<>k50;3xLg`33td9<>h50;3xLg`33td9<9>50;3xLg`33td9<9?50;3xLg`33td9<9<50;3xLg`33td9<9=50;3xLg`33td9<9:50;3xLg`33td9<9;50;3xLg`33td9<9850;3xLg`33td9<9950;3xLg`33td9<9650;3xLg`33td9<9750;3xLg`33td9<9o50;3xLg`33td9<9l50;3xLg`33td9<9m50;3xLg`33td9<9j50;3xLg`33td9<9k50;3xLg`33td9<9h50;3xLg`33td9<8>50;3xLg`33td9<8?50;3xLg`33td9<8<50;3xLg`33td9<8=50;3xLg`33td9<8:50;3xLg`33td9<8;50;3xLg`33td9<8850;3xLg`33td9<8950;3xLg`33td9<8650;3xLg`33td9<8750;3xLg`33td9<8o50;3xLg`33td9<8l50;3xLg`33td9<8m50;3xLg`33td9<8j50;3xLg`33td9<8k50;3xLg`33td9<8h50;3xLg`33td9<;>50;3xLg`33td9<;?50;3xLg`33td9<;<50;3xLg`33td9<;=50;3xLg`33td9<;:50;3xLg`33td9<;;50;3xLg`33td9<;850;3xLg`33td9<;950;3xLg`33td9<;650;3xLg`33td9<;750;3xLg`33td9<;o50;3xLg`33td9<;l50;3xLg`33td9<;m50;3xLg`33td9<;j50;3xLg`33td9<;k50;3xLg`33td9<;h50;3xLg`33td9<:>50;3xLg`33td9<:?50;3xLg`33td9<:<50;3xLg`33td9<:=50;3xLg`33td9<::50;3xLg`33td9<:;50;3xLg`33td9<:850;3xLg`33td9<:950;3xLg`33td9<:650;3xLg`33td9<:750;3xLg`33td9<:o50;3xLg`33td9<:l50;3xLg`33td9<:m50;3xLg`33td9<:j50;3xLg`33td9<:k50;3xLg`33td9<:h50;3xLg`33td9<5>50;3xLg`33td9<5?50;3xLg`33td9<5<50;3xLg`33td9<5=50;3xLg`33td9<5:50;3xLg`33td9<5;50;3xLg`33td9<5850;3xLg`33td9<5950;3xLg`33td9<5650;3xLg`33td9<5750;3xLg`33td9<5o50;3xLg`33td9<5l50;3xLg`33td9<5m50;3xLg`33td9<5j50;3xLg`33td9<5k50;3xLg`33td9<5h50;3xLg`33td9<4>50;3xLg`33td9<4?50;3xLg`33td9<4<50;3xLg`33td9<4=50;3xLg`33td9<4:50;3xLg`33td9<4;50;3xLg`33td9<4850;3xLg`33td9<4950;3xLg`33td9<4650;3xLg`33td9<4750;3xLg`33td9<4o50;3xLg`33td9<4l50;3xLg`33td9<4m50;3xLg`33td9<4j50;3xLg`33td9<4k50;3xLg`33td9<4h50;3xLg`33td9<l>50;3xLg`33td9<l?50;3xLg`33td9<l<50;3xLg`33td9<l=50;3xLg`33td9<l:50;3xLg`33td9<l;50;3xLg`33td9<l850;3xLg`33td9<l950;3xLg`33td9<l650;3xLg`33td9<l750;3xLg`33td9<lo50;3xLg`33td9<ll50;3xLg`33td9<lm50;3xLg`33td9<lj50;3xLg`33td9<lk50;3xLg`33td9<lh50;3xLg`33td9<o>50;3xLg`33td9<o?50;3xLg`33td9<o<50;3xLg`33td9<o=50;3xLg`33td9<o:50;3xLg`33td9<o;50;3xLg`33td9<o850;3xLg`33td9<o950;3xLg`33td9<o650;3xLg`33td9<o750;3xLg`33td9<oo50;3xLg`33td9<ol50;3xLg`33td9<om50;3xLg`33td9<oj50;3xLg`33td9<ok50;3xLg`33td9<oh50;3xLg`33td9<n>50;3xLg`33td9<n?50;3xLg`33td9<n<50;3xLg`33td9<n=50;3xLg`33td9<n:50;3xLg`33td9<n;50;3xLg`33td9<n850;3xLg`33td9<n950;3xLg`33td9<n650;3xLg`33td9<n750;3xLg`33td9<no50;3xLg`33td9<nl50;3xLg`33td9<nm50;3xLg`33td9<nj50;3xLg`33td9<nk50;3xLg`33td9<nh50;3xLg`33td9<i>50;3xLg`33td9<i?50;3xLg`33td9<i<50;3xLg`33td9<i=50;3xLg`33td9<i:50;3xLg`33td9<i;50;3xLg`33td9<i850;3xLg`33td9<i950;3xLg`33td9<i650;3xLg`33td9<i750;3xLg`33td9<io50;3xLg`33td9<il50;3xLg`33td9<im50;3xLg`33td9<ij50;3xLg`33td9<ik50;3xLg`33td9<ih50;3xLg`33td9<h>50;3xLg`33td9<h?50;3xLg`33td9<h<50;3xLg`33td9<h=50;3xLg`33td9<h:50;3xLg`33td9<h;50;3xLg`33td9<h850;3xLg`33td9<h950;3xLg`33td9<h650;3xLg`33td9<h750;3xLg`33td9<ho50;3xLg`33td9<hl50;3xLg`33td9<hm50;3xLg`33td9<hj50;3xLg`33td9<hk50;3xLg`33td9<hh50;3xLg`33td9<k>50;3xLg`33td9<k?50;3xLg`33td9<k<50;3xLg`33td9<k=50;3xLg`33td9<k:50;3xLg`33td9<k;50;3xLg`33td9<k850;3xLg`33td9<k950;3xLg`33td9<k650;3xLg`33td9<k750;3xLg`33td9<ko50;3xLg`33td9<kl50;3xLg`33td9<km50;3xLg`33td9<kj50;3xLg`33td9<kk50;3xLg`33td9<kh50;3xLg`33td9==>50;3xLg`33td9==?50;3xLg`33td9==<50;3xLg`33td9===50;3xLg`33td9==:50;3xLg`33td9==;50;3xLg`33td9==850;3xLg`33td9==950;3xLg`33td9==650;3xLg`33td9==750;3xLg`33td9==o50;3xLg`33td9==l50;3xLg`33td9==m50;3xLg`33td9==j50;3xLg`33td9==k50;3xLg`33td9==h50;3xLg`33td9=<>50;3xLg`33td9=<?50;3xLg`33td9=<<50;3xLg`33td9=<=50;3xLg`33td9=<:50;3xLg`33td9=<;50;3xLg`33td9=<850;3xLg`33td9=<950;3xLg`33td9=<650;3xLg`33td9=<750;3xLg`33td9=<o50;3xLg`33td9=<l50;3xLg`33td9=<m50;3xLg`33td9=<j50;3xLg`33td9=<k50;3xLg`33td9=<h50;3xLg`33td9=?>50;3xLg`33td9=??50;3xLg`33td9=?<50;3xLg`33td9=?=50;3xLg`33td9=?:50;3xLg`33td9=?;50;3xLg`33td9=?850;3xLg`33td9=?950;3xLg`33td9=?650;3xLg`33td9=?750;3xLg`33td9=?o50;3xLg`33td9=?l50;3xLg`33td9=?m50;3xLg`33td9=?j50;3xLg`33td9=?k50;3xLg`33td9=?h50;3xLg`33td9=>>50;3xLg`33td9=>?50;3xLg`33td9=><50;3xLg`33td9=>=50;3xLg`33td9=>:50;3xLg`33td9=>;50;3xLg`33td9=>850;3xLg`33td9=>950;3xLg`33td9=>650;3xLg`33td9=>750;3xLg`33td9=>o50;3xLg`33td9=>l50;3xLg`33td9=>m50;3xLg`33td9=>j50;3xLg`33td9=>k50;3xLg`33td9=>h50;3xLg`33td9=9>50;3xLg`33td9=9?50;3xLg`33td9=9<50;3xLg`33td9=9=50;3xLg`33td9=9:50;3xLg`33td9=9;50;3xLg`33td9=9850;3xLg`33td9=9950;3xLg`33td9=9650;3xLg`33td9=9750;3xLg`33td9=9o50;3xLg`33td9=9l50;3xLg`33td9=9m50;3xLg`33td9=9j50;3xLg`33td9=9k50;3xLg`33td9=9h50;3xLg`33td9=8>50;3xLg`33td9=8?50;3xLg`33td9=8<50;3xLg`33td9=8=50;3xLg`33td9=8:50;3xLg`33td9=8;50;3xLg`33td9=8850;3xLg`33td9=8950;3xLg`33td9=8650;3xLg`33td9=8750;3xLg`33td9=8o50;3xLg`33td9=8l50;3xLg`33td9=8m50;3xLg`33td9=8j50;3xLg`33td9=8k50;3xLg`33td9=8h50;3xLg`33td9=;>50;3xLg`33td9=;?50;3xLg`33td9=;<50;3xLg`33td9=;=50;3xLg`33td9=;:50;3xLg`33td9=;;50;3xLg`33td9=;850;3xLg`33td9=;950;3xLg`33td9=;650;3xLg`33td9=;750;3xLg`33td9=;o50;3xLg`33td9=;l50;3xLg`33td9=;m50;3xLg`33td9=;j50;3xLg`33td9=;k50;3xLg`33td9=;h50;3xLg`33td9=:>50;3xLg`33td9=:?50;3xLg`33td9=:<50;3xLg`33td9=:=50;3xLg`33td9=::50;3xLg`33td9=:;50;3xLg`33td9=:850;3xLg`33td9=:950;3xLg`33td9=:650;3xLg`33td9=:750;3xLg`33td9=:o50;3xLg`33td9=:l50;3xLg`33td9=:m50;3xLg`33td9=:j50;3xLg`33td9=:k50;3xLg`33td9=:h50;3xLg`33td9=5>50;3xLg`33td9=5?50;3xLg`33td9=5<50;3xLg`33td9=5=50;3xLg`33td9=5:50;3xLg`33td9=5;50;3xLg`33td9=5850;3xLg`33td9=5950;3xLg`33td9=5650;3xLg`33td9=5750;3xLg`33td9=5o50;3xLg`33td9=5l50;3xLg`33td9=5m50;3xLg`33td9=5j50;3xLg`33td9=5k50;3xLg`33td9=5h50;3xLg`33td9=4>50;3xLg`33td9=4?50;3xLg`33td9=4<50;3xLg`33td9=4=50;3xLg`33td9=4:50;3xLg`33td9=4;50;3xLg`33td9=4850;3xLg`33td9=4950;3xLg`33td9=4650;3xLg`33td9=4750;3xLg`33td9=4o50;3xLg`33td9=4l50;3xLg`33td9=4m50;3xLg`33td9=4j50;3xLg`33td9=4k50;3xLg`33td9=4h50;3xLg`33td9=l>50;3xLg`33td9=l?50;3xLg`33td9=l<50;3xLg`33td9=l=50;3xLg`33td9=l:50;3xLg`33td9=l;50;3xLg`33td9=l850;3xLg`33td9=l950;3xLg`33td9=l650;3xLg`33td9=l750;3xLg`33td9=lo50;3xLg`33td9=ll50;3xLg`33td9=lm50;3xLg`33td9=lj50;3xLg`33td9=lk50;3xLg`33td9=lh50;3xLg`33td9=o>50;3xLg`33td9=o?50;3xLg`33td9=o<50;3xLg`33td9=o=50;3xLg`33td9=o:50;3xLg`33td9=o;50;3xLg`33td9=o850;3xLg`33td9=o950;3xLg`33td9=o650;3xLg`33td9=o750;3xLg`33td9=oo50;3xLg`33td9=ol50;3xLg`33td9=om50;3xLg`33td9=oj50;3xLg`33td9=ok50;3xLg`33td9=oh50;3xLg`33td9=n>50;3xLg`33td9=n?50;3xLg`33td9=n<50;3xLg`33td9=n=50;3xLg`33td9=n:50;3xLg`33td9=n;50;3xLg`33td9=n850;3xLg`33td9=n950;3xLg`33td9=n650;3xLg`33td9=n750;3xLg`33td9=no50;3xLg`33td9=nl50;3xLg`33td9=nm50;3xLg`33td9=nj50;3xLg`33td9=nk50;3xLg`33td9=nh50;3xLg`33td9=i>50;3xLg`33td9=i?50;3xLg`33td9=i<50;3xLg`33td9=i=50;3xLg`33td9=i:50;3xLg`33td9=i;50;3xLg`33td9=i850;3xLg`33td9=i950;3xLg`33td9=i650;3xLg`33td9=i750;3xLg`33td9=io50;3xLg`33td9=il50;3xLg`33td9=im50;3xLg`33td9=ij50;3xLg`33td9=ik50;3xLg`33td9=ih50;3xLg`33td9=h>50;3xLg`33td9=h?50;3xLg`33td9=h<50;3xLg`33td9=h=50;3xLg`33td9=h:50;3xLg`33td9=h;50;3xLg`33td9=h850;3xLg`33td9=h950;3xLg`33td9=h650;3xLg`33td9=h750;3xLg`33td9=ho50;3xLg`33td9=hl50;3xLg`33td9=hm50;3xLg`33td9=hj50;3xLg`33td9=hk50;3xLg`33td9=hh50;3xLg`33td9=k>50;3xLg`33td9=k?50;3xLg`33td9=k<50;3xLg`33td9=k=50;3xLg`33td9=k:50;3xLg`33td9=k;50;3xLg`33td9=k850;3xLg`33td9=k950;3xLg`33td9=k650;3xLg`33td9=k750;3xLg`33td9=ko50;3xLg`33td9=kl50;3xLg`33td9=km50;3xLg`33td9=kj50;3xLg`33td9=kk50;3xLg`33td9=kh50;3xLg`33td9>=>50;3xLg`33td9>=?50;3xLg`33td9>=<50;3xLg`33td9>==50;3xLg`33td9>=:50;3xLg`33td9>=;50;3xLg`33td9>=850;3xLg`33td9>=950;3xLg`33td9>=650;3xLg`33td9>=750;3xLg`33td9>=o50;3xLg`33td9>=l50;3xLg`33td9>=m50;3xLg`33td9>=j50;3xLg`33td9>=k50;3xLg`33td9>=h50;3xLg`33td9><>50;3xLg`33td9><?50;3xLg`33td9><<50;3xLg`33td9><=50;3xLg`33td9><:50;3xLg`33td9><;50;3xLg`33td9><850;3xLg`33td9><950;3xLg`33td9><650;3xLg`33td9><750;3xLg`33td9><o50;3xLg`33td9><l50;3xLg`33td9><m50;3xLg`33td9><j50;3xLg`33td9><k50;3xLg`33td9><h50;3xLg`33td9>?>50;3xLg`33td9>??50;3xLg`33td9>?<50;3xLg`33td9>?=50;3xLg`33td9>?:50;3xLg`33td9>?;50;3xLg`33td9>?850;3xLg`33td9>?950;3xLg`33td9>?650;3xLg`33td9>?750;3xLg`33td9>?o50;3xLg`33td9>?l50;3xLg`33td9>?m50;3xLg`33td9>?j50;3xLg`33td9>?k50;3xLg`33td9>?h50;3xLg`33td9>>>50;3xLg`33td9>>?50;3xLg`33td9>><50;3xLg`33td9>>=50;3xLg`33td9>>:50;3xLg`33td9>>;50;3xLg`33td9>>850;3xLg`33td9>>950;3xLg`33td9>>650;3xLg`33td9>>750;3xLg`33td9>>o50;3xLg`33td9>>l50;3xLg`33td9>>m50;3xLg`33td9>>j50;3xLg`33td9>>k50;3xLg`33td9>>h50;3xLg`33td9>9>50;3xLg`33td9>9?50;3xLg`33td9>9<50;3xLg`33td9>9=50;3xLg`33td9>9:50;3xLg`33td9>9;50;3xLg`33td9>9850;3xLg`33td9>9950;3xLg`33td9>9650;3xLg`33td9>9750;3xLg`33td9>9o50;3xLg`33td9>9l50;3xLg`33td9>9m50;3xLg`33td9>9j50;3xLg`33td9>9k50;3xLg`33td9>9h50;3xLg`33td9>8>50;3xLg`33td9>8?50;3xLg`33td9>8<50;3xLg`33td9>8=50;3xLg`33td9>8:50;3xLg`33td9>8;50;3xLg`33td9>8850;3xLg`33td9>8950;3xLg`33td9>8650;3xLg`33td9>8750;3xLg`33td9>8o50;3xLg`33td9>8l50;3xLg`33td9>8m50;3xLg`33td9>8j50;3xLg`33td9>8k50;3xLg`33td9>8h50;3xLg`33td9>;>50;3xLg`33td9>;?50;3xLg`33td9>;<50;3xLg`33td9>;=50;3xLg`33td9>;:50;3xLg`33td9>;;50;3xLg`33td9>;850;3xLg`33td9>;950;3xLg`33td9>;650;3xLg`33td9>;750;3xLg`33td9>;o50;3xLg`33td9>;l50;3xLg`33td9>;m50;3xLg`33td9>;j50;3xLg`33td9>;k50;3xLg`33td9>;h50;3xLg`33td9>:>50;3xLg`33td9>:?50;3xLg`33td9>:<50;3xLg`33td9>:=50;3xLg`33td9>::50;3xLg`33td9>:;50;3xLg`33td9>:850;3xLg`33td9>:950;3xLg`33td9>:650;3xLg`33td9>:750;3xLg`33td9>:o50;3xLg`33td9>:l50;3xLg`33td9>:m50;3xLg`33td9>:j50;3xLg`33td9>:k50;3xLg`33td9>:h50;3xLg`33td9>5>50;3xLg`33td9>5?50;3xLg`33td9>5<50;3xLg`33td9>5=50;3xLg`33td9>5:50;3xLg`33td9>5;50;3xLg`33td9>5850;3xLg`33td9>5950;3xLg`33td9>5650;3xLg`33td9>5750;3xLg`33td9>5o50;3xLg`33td9>5l50;3xLg`33td9>5m50;3xLg`33td9>5j50;3xLg`33td9>5k50;3xLg`33td9>5h50;3xLg`33td9>4>50;3xLg`33td9>4?50;3xLg`33td9>4<50;3xLg`33td9>4=50;3xLg`33td9>4:50;3xLg`33td9>4;50;3xLg`33td9>4850;3xLg`33td9>4950;3xLg`33td9>4650;3xLg`33td9>4750;3xLg`33td9>4o50;3xLg`33td9>4l50;3xLg`33td9>4m50;3xLg`33td9>4j50;3xLg`33td9>4k50;3xLg`33td9>4h50;3xLg`33td9>l>50;3xLg`33td9>l?50;3xLg`33td9>l<50;3xLg`33td9>l=50;3xLg`33td9>l:50;3xLg`33td9>l;50;3xLg`33td9>l850;3xLg`33td9>l950;3xLg`33td9>l650;3xLg`33td9>l750;3xLg`33td9>lo50;3xLg`33td9>ll50;3xLg`33td9>lm50;3xLg`33td9>lj50;3xLg`33td9>lk50;3xLg`33td9>lh50;3xLg`33td9>o>50;3xLg`33td9>o?50;3xLg`33td9>o<50;3xLg`33td9>o=50;3xLg`33td9>o:50;3xLg`33td9>o;50;3xLg`33td9>o850;3xLg`33td9>o950;3xLg`33td9>o650;3xLg`33td9>o750;3xLg`33td9>oo50;3xLg`33td9>ol50;3xLg`33td9>om50;3xLg`33td9>oj50;3xLg`33td9>ok50;3xLg`33td9>oh50;3xLg`33td9>n>50;3xLg`33td9>n?50;3xLg`33td9>n<50;3xLg`33td9>n=50;3xLg`33td9>n:50;3xLg`33td9>n;50;3xLg`33td9>n850;3xLg`33td9>n950;3xLg`33td9>n650;3xLg`33td9>n750;3xLg`33td9>no50;3xLg`33td9>nl50;3xLg`33td9>nm50;3xLg`33td9>nj50;3xLg`33td9>nk50;3xLg`33td9>nh50;3xLg`33td9>i>50;3xLg`33td9>i?50;3xLg`33td9>i<50;3xLg`33td9>i=50;3xLg`33td9>i:50;3xLg`33td9>i;50;3xLg`33td9>i850;3xLg`33td9>i950;3xLg`33td9>i650;3xLg`33td9>i750;3xLg`33td9>io50;3xLg`33td9>il50;3xLg`33td9>im50;3xLg`33td9>ij50;3xLg`33td9>ik50;3xLg`33td9>ih50;3xLg`33td9>h>50;3xLg`33td9>h?50;3xLg`33td9>h<50;3xLg`33td9>h=50;3xLg`33td9>h:50;3xLg`33td9>h;50;3xLg`33td9>h850;3xLg`33td9>h950;3xLg`33td9>h650;3xLg`33td9>h750;3xLg`33td9>ho50;3xLg`33td9>hl50;3xLg`33td9>hm50;3xLg`33td9>hj50;3xLg`33td9>hk50;3xLg`33td9>hh50;3xLg`33td9>k>50;3xLg`33td9>k?50;3xLg`33td9>k<50;3xLg`33td9>k=50;3xLg`33td9>k:50;3xLg`33td9>k;50;3xLg`33td9>k850;3xLg`33td9>k950;3xLg`33td9>k650;3xLg`33td9>k750;3xLg`33td9>ko50;3xLg`33td9>kl50;3xLg`33td9>km50;3xLg`33td9>kj50;3xLg`33td9>kk50;3xLg`33td9>kh50;3xLg`33td9?=>50;3xLg`33td9?=?50;3xLg`33td9?=<50;3xLg`33td9?==50;3xLg`33td9?=:50;3xLg`33td9?=;50;3xLg`33td9?=850;3xLg`33td9?=950;3xLg`33td9?=650;3xLg`33td9?=750;3xLg`33td9?=o50;3xLg`33td9?=l50;3xLg`33td9?=m50;3xLg`33td9?=j50;3xLg`33td9?=k50;3xLg`33td9?=h50;3xLg`33td9?<>50;3xLg`33td9?<?50;3xLg`33td9?<<50;3xLg`33td9?<=50;3xLg`33td9?<:50;3xLg`33td9?<;50;3xLg`33td9?<850;3xLg`33td9?<950;3xLg`33td9?<650;3xLg`33td9?<750;3xLg`33td9?<o50;3xLg`33td9?<l50;3xLg`33td9?<m50;3xLg`33td9?<j50;3xLg`33td9?<k50;3xLg`33td9?<h50;3xLg`33td9??>50;3xLg`33td9???50;3xLg`33td9??<50;3xLg`33td9??=50;3xLg`33td9??:50;3xLg`33td9??;50;3xLg`33td9??850;3xLg`33td9??950;3xLg`33td9??650;3xLg`33td9??750;3xLg`33td9??o50;3xLg`33td9??l50;3xLg`33td9??m50;3xLg`33td9??j50;3xLg`33td9??k50;3xLg`33td9??h50;3xLg`33td9?>>50;3xLg`33td9?>?50;3xLg`33td9?><50;3xLg`33td9?>=50;3xLg`33td9?>:50;3xLg`33td9?>;50;3xLg`33td9?>850;3xLg`33td9?>950;3xLg`33td9?>650;3xLg`33td9?>750;3xLg`33td9?>o50;3xLg`33td9?>l50;3xLg`33td9?>m50;3xLg`33td9?>j50;3xLg`33td9?>k50;3xLg`33td9?>h50;3xLg`33td9?9>50;3xLg`33td9?9?50;3xLg`33td9?9<50;3xLg`33td9?9=50;3xLg`33td9?9:50;3xLg`33td9?9;50;3xLg`33td9?9850;3xLg`33td9?9950;3xLg`33td9?9650;3xLg`33td9?9750;3xLg`33td9?9o50;3xLg`33td9?9l50;3xLg`33td9?9m50;3xLg`33td9?9j50;3xLg`33td9?9k50;3xLg`33td9?9h50;3xLg`33td9?8>50;3xLg`33td9?8?50;3xLg`33td9?8<50;3xLg`33td9?8=50;3xLg`33td9?8:50;3xLg`33td9?8;50;3xLg`33td9?8850;3xLg`33td9?8950;3xLg`33td9?8650;3xLg`33td9?8750;3xLg`33td9?8o50;3xLg`33td9?8l50;3xLg`33td9?8m50;3xLg`33td9?8j50;3xLg`33td9?8k50;3xLg`33td9?8h50;3xLg`33td9?;>50;3xLg`33td9?;?50;3xLg`33td9?;<50;3xLg`33td9?;=50;3xLg`33td9?;:50;3xLg`33td9?;;50;3xLg`33td9?;850;3xLg`33td9?;950;3xLg`33td9?;650;3xLg`33td9?;750;3xLg`33td9?;o50;3xLg`33td9?;l50;3xLg`33td9?;m50;3xLg`33td9?;j50;3xLg`33td9?;k50;3xLg`33td9?;h50;3xLg`33td9?:>50;3xLg`33td9?:?50;3xLg`33td9?:<50;3xLg`33td9?:=50;3xLg`33td9?::50;3xLg`33td9?:;50;3xLg`33td9?:850;3xLg`33td9?:950;3xLg`33td9?:650;3xLg`33td9?:750;3xLg`33td9?:o50;3xLg`33td9?:l50;3xLg`33td9?:m50;3xLg`33td9?:j50;3xLg`33td9?:k50;3xLg`33td9?:h50;3xLg`33td9?5>50;3xLg`33td9?5?50;3xLg`33td9?5<50;3xLg`33td9?5=50;3xLg`33td9?5:50;3xLg`33td9?5;50;3xLg`33td9?5850;3xLg`33td9?5950;3xLg`33td9?5650;3xLg`33td9?5750;3xLg`33td9?5o50;3xLg`33td9?5l50;3xLg`33td9?5m50;3xLg`33td9?5j50;3xLg`33td9?5k50;3xLg`33td9?5h50;3xLg`33td9?4>50;3xLg`33td9?4?50;3xLg`33td9?4<50;3xLg`33td9?4=50;3xLg`33td9?4:50;3xLg`33td9?4;50;3xLg`33td9?4850;3xLg`33td9?4950;3xLg`33td9?4650;3xLg`33td9?4750;3xLg`33td9?4o50;3xLg`33td9?4l50;3xLg`33td9?4m50;3xLg`33td9?4j50;3xLg`33td9?4k50;3xLg`33td9?4h50;3xLg`33td9?l>50;3xLg`33td9?l?50;3xLg`33td9?l<50;3xLg`33td9?l=50;3xLg`33td9?l:50;3xLg`33td9?l;50;3xLg`33td9?l850;3xLg`33td9?l950;3xLg`33td9?l650;3xLg`33td9?l750;3xLg`33td9?lo50;3xLg`33td9?ll50;3xLg`33td9?lm50;3xLg`33td9?lj50;3xLg`33td9?lk50;3xLg`33twvqMNL{3;`3?7f>123:isO@Cy3yEFWstJK
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/double_reset.vhd b/FEE_ADC32board/project/ipcore_dir/double_reset.vhd
deleted file mode 100644
index 10d5b6b..0000000
--- a/FEE_ADC32board/project/ipcore_dir/double_reset.vhd
+++ /dev/null
@@ -1,140 +0,0 @@
-------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
---  /   /         Filename : double_reset.vhd
--- /___/   /\     
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Module DOUBLE_RESET
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
-entity DOUBLE_RESET is
-port
-(
-        CLK                :   in    std_logic;
-        PLLLKDET           :   in    std_logic;
-        GTXTEST_DONE       :   out   std_logic;
-        GTXTEST_BIT1       :   out   std_logic
-);
-
-end DOUBLE_RESET;
-
-architecture RTL of DOUBLE_RESET is
---***********************************Parameter Declarations********************
-    constant DLY : time := 1 ns;
-
---*******************************Register Declarations************************
-    signal plllkdet_sync  :   std_logic;
-    signal plllkdet_r     :   std_logic;
-    signal reset_dly_ctr  :   unsigned(10 downto 0);
-    signal reset_dly_done :   std_logic;
-    signal testdone_f     :   std_logic_vector(3 downto 0);
-
-begin
---*******************************Main Body of Code****************************
-
-    process(CLK )
-    begin
-        if(CLK'event and CLK = '1') then
-           plllkdet_r    <= PLLLKDET   after DLY;
-           plllkdet_sync <= plllkdet_r after DLY;
-        end if;
-    end process;
-
-    GTXTEST_BIT1 <= reset_dly_done; 
-    GTXTEST_DONE <= testdone_f(0) when (reset_dly_ctr = b"00000000000") else '0';
-
-    process(CLK )
-    begin
-        if(CLK'event and CLK = '1') then
-          if (plllkdet_sync = '0') then
-            reset_dly_ctr <= b"11111111111"     after DLY;
-          elsif (reset_dly_ctr /= b"00000000000") then
-            reset_dly_ctr <= reset_dly_ctr - 1 after DLY;
-          end if;
-        end if;
-    end process;
-
-    process(CLK )
-    begin
-        if(CLK'event and CLK = '1') then
-          if (plllkdet_sync = '0') then
-             reset_dly_done <= '0'   after DLY;
-          elsif (reset_dly_ctr(10) = '0') then
-             reset_dly_done <= reset_dly_ctr(8)   after DLY;
-          end if;
-        end if;
-    end process;
-
-    process(CLK )
-    begin
-        if(CLK'event and CLK = '1') then
-          if(reset_dly_ctr /= b"00000000000") then
-             testdone_f <= b"1111" after DLY;
-          else
-             testdone_f <= '0' & testdone_f(3 downto 1) after DLY;      
-          end if;
-        end if;
-    end process;
-    
-
-end RTL;
diff --git a/FEE_ADC32board/project/ipcore_dir/fifo_generator_v8_3_readme.txt b/FEE_ADC32board/project/ipcore_dir/fifo_generator_v8_3_readme.txt
deleted file mode 100644
index 3028471..0000000
--- a/FEE_ADC32board/project/ipcore_dir/fifo_generator_v8_3_readme.txt
+++ /dev/null
@@ -1,197 +0,0 @@
-                    Core Name: Xilinx LogiCORE FIFO Generator
-                    Version: 8.3
-                    Release Date: October 19, 2011
-
-
-================================================================================
-
-This document contains the following sections: 
-
-1. Introduction
-2. New Features
-3. Supported Devices
-4. Resolved Issues
-5. Known Issues 
-6. Technical Support
-7. Core Release History
-8. Legal Disclaimer
- 
-================================================================================
- 
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
-   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
-   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v8.2
-solution. For the latest core updates, see the product page at:
- 
-   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
-
-
-2. NEW FEATURES  
- 
-   - ISE 13.3 software support
-   - QVirtex-6L device support
-
-3. SUPPORTED DEVICES
-
-   The following device families are supported by the core for this release.
-
-   - Zynq-7000*
-
-   - Virtex-7
-   - Virtex-7 XT (7vx485t)
-   - Virtex-7 -2L
-
-   - Kintex-7
-   - Kintex-7 -2L
-
-   - Artix-7*
-
-   - Virtex-6 XC CXT/LXT/SXT/HXT
-   - Virtex-6 XQ LXT/SXT
-   - Virtex-6 -1L XC LXT/SXT 
-
-   - Spartan-6 XC LX/LXT 
-   - Spartan-6 XA 
-   - Spartan-6 XQ LX/LXT
-   - Spartan-6 -1L XC LX
-
-   - Virtex-5 XC LX/LXT/SXT/TXT/FXT
-   - Virtex-5 XQ LX/ LXT/SXT/FXT
-
-   - Virtex-4 XC LX/SX/FX
-   - Virtex-4 XQ LX/SX/FX
-   - Virtex-4 XQR LX/SX/FX
-
-   - Spartan-3 XC
-   - Spartan-3 XA
-   - Spartan-3A XC 3A / 3A DSP / 3AN DSP
-   - Spartan-3A XA 3A / 3A DSP
-   - Spartan-3E XC
-   - Spartan-3E XA
-
-*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
-
-4. RESOLVED ISSUES 
-
-
-5. KNOWN ISSUES 
-
-   The following are known issues for v8.2 of this core at time of release:
-
-   - In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
-     into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
-     page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
-     - CR 467240
-     - AR 31379
-
-   - When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
-     correct behavior of the FIFO status flags cannot be guaranteed after the first write.
-
-     Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
-     For more information and additional workaround see Answer Record 41099.
-
-
-   The most recent information, including known issues, workarounds, and
-   resolutions for this version is provided in the IP Release Notes User Guide
-   located at 
-
-   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
-
-
-6. TECHNICAL SUPPORT 
-
-   To obtain technical support, create a WebCase at www.xilinx.com/support.
-   Questions are routed to a team with expertise using this product.  
-     
-   Xilinx provides technical support for use of this product when used
-   according to the guidelines described in the core documentation, and
-   cannot guarantee timing, functionality, or support of this product for
-   designs that do not follow specified guidelines.
-
-
-7. CORE RELEASE HISTORY 
-
-Date        By            Version      Description
-================================================================================
-09/28/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L and QSpartan-6 device support
-06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7* and Zynq-7000* device support
-03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
-10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
-09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
-07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
-06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
-04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
-12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
-09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
-06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
-04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
-09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
-03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
-10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
-08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
-04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
-09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
-07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
-01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
-08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
-04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
-11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
-05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
-04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
-================================================================================
-
-8. Legal Disclaimer
-
- (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
-
- This file contains confidential and proprietary information
- of Xilinx, Inc. and is protected under U.S. and
- international copyright and other intellectual property
- laws.
- 
- DISCLAIMER
- This disclaimer is not a license and does not grant any
- rights to the materials distributed herewith. Except as
- otherwise provided in a valid license issued to you by
- Xilinx, and to the maximum extent permitted by applicable
- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
- (2) Xilinx shall not be liable (whether in contract or tort,
- including negligence, or under any other theory of
- liability) for any loss or damage of any kind or nature
- related to, arising under or in connection with these
- materials, including for any direct, or any indirect,
- special, incidental, or consequential loss or damage
- (including loss of data, profits, goodwill, or any type of
- loss or damage suffered as a result of any action brought
- by a third party) even if such damage or loss was
- reasonably foreseeable or Xilinx had been advised of the
- possibility of the same.
- 
- CRITICAL APPLICATIONS
- Xilinx products are not designed or intended to be fail-
- safe, or for use in any application requiring fail-safe
- performance, such as life-support or safety devices or
- systems, Class III medical devices, nuclear facilities,
- applications related to the deployment of airbags, or any
- other applications that could lead to death, personal
- injury, or severe property or environmental damage
- (individually and collectively, "Critical
- Applications"). Customer assumes the sole risk and
- liability of any use of Xilinx products in Critical
- Applications, subject only to applicable laws and
- regulations governing limitations on product liability.
- 
- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
- PART OF THIS FILE AT ALL TIMES.
diff --git a/FEE_ADC32board/project/ipcore_dir/frame_check.vhd b/FEE_ADC32board/project/ipcore_dir/frame_check.vhd
deleted file mode 100644
index 5b4a18c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/frame_check.vhd
+++ /dev/null
@@ -1,702 +0,0 @@
--------------------------------------------------------------------------------
---   ____  ____ 
---  /   /\/   / 
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard  
---  /   /         Filename : frame_check.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\ 
---
---
--- Module FRAME_CHECK
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard  
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-use std.textio.all;
-use ieee.std_logic_textio.all;
-use ieee.std_logic_misc.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
---***********************************Entity Declaration************************
-
-entity FRAME_CHECK is
-generic
-(
-    RX_DATA_WIDTH            : integer := 16;
-    RXCTRL_WIDTH             : integer := 2;
-    USE_COMMA                : integer := 1;
-    NONE_MSB_FIRST_DEC       : integer := 0;
-    COMMA_DOUBLE_DEC         : integer := 0;
-    CHANBOND_SEQ_LEN         : integer := 1;
-    WORDS_IN_BRAM            : integer := 256;
-    CONFIG_INDEPENDENT_LANES : integer := 0;
-    START_OF_PACKET_CHAR     : std_logic_vector(15 downto 0) ;
-    COMMA_DOUBLE_CHAR        : std_logic_vector(15 downto 0) := x"f628";
-    MEM_00       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_01       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_02       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_03       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_04       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_05       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_06       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_07       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_08       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_09       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_10       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_11       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_12       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_13       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_14       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_15       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_16       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_17       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_18       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_19       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_20       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_21       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_22       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_23       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_24       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_25       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_26       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_27       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_28       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_29       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_30       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_31       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_32       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_33       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_34       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_35       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_36       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_37       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_38       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_39       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_00      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_01      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_02      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_03      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_04      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_05      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_06      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_07      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000"
-);
-port
-(
-    -- User Interface
-    RX_DATA                  : in  std_logic_vector((RX_DATA_WIDTH-1) downto 0); 
-    RXCTRL_IN                : in  std_logic_vector((RXCTRL_WIDTH-1) downto 0); 
-  
-    RX_ENMCOMMA_ALIGN        : out std_logic;
-    RX_ENPCOMMA_ALIGN        : out std_logic;
-    RX_ENCHAN_SYNC           : out std_logic; 
-    RX_CHANBOND_SEQ          : in  std_logic; 
-
-    -- Control Interface
-    INC_IN                   : in std_logic; 
-    INC_OUT                  : out std_logic; 
-    PATTERN_MATCH_N          : out std_logic;
-    RESET_ON_ERROR           : in std_logic; 
-      
-    -- Error Monitoring
-    ERROR_COUNT              : out std_logic_vector(7 downto 0);
-    
-    -- Track Data
-    TRACK_DATA               : out std_logic;
-   
-    -- System Interface
-    USER_CLK                 : in std_logic;       
-    SYSTEM_RESET             : in std_logic
-  
-);
-
-
-end FRAME_CHECK;
-
-
-architecture RTL of FRAME_CHECK is
-
-
---***********************************Parameter Declarations********************
-
-    constant DLY : time := 1 ns;
-
---***************************Internal Register Declarations********************
-
-    signal  begin_r                     :   std_logic;
-    signal  data_error_detected_r       :   std_logic;
-    signal  error_count_r               :   unsigned(8 downto 0);
-    signal  error_detected_r            :   std_logic;
-    signal  read_counter_i              :   unsigned(8 downto 0);    
-    signal  rx_chanbond_seq_r           :   std_logic;
-    signal  rx_chanbond_seq_r2          :   std_logic;
-    signal  rx_chanbond_seq_r3          :   std_logic;
-    signal  rx_data_r                   :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r2                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r3                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r4                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r5                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r6                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r7                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r_track             :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rxctrl_r                    :   std_logic_vector((RXCTRL_WIDTH-1) downto 0);
-    signal  rxctrl_r2                   :   std_logic_vector((RXCTRL_WIDTH-1) downto 0);
-    signal  rxctrl_r3                   :   std_logic_vector((RXCTRL_WIDTH-1) downto 0);
-    signal  rxctrl_or                   :   std_logic;
-    signal  start_of_packet_detected_r  :   std_logic;    
-    signal  track_data_r                :   std_logic;
-    signal  track_data_r2               :   std_logic;
-    signal  track_data_r3               :   std_logic;
-    signal  track_data_r4               :   std_logic;
-    signal  sel                         :   std_logic_vector(1 downto 0);
-    signal  bram_data_r                 :   std_logic_vector(31 downto 0);
-         
- 
---*********************************Wire Declarations***************************
-   
-    signal  bram_data_i                 :   std_logic_vector(31 downto 0);
-
-    signal  chanbondseq_in_data         :   std_logic;
-    signal  error_detected_c            :   std_logic;
-    signal  input_to_chanbond_data_i    :   std_logic;
-    signal  input_to_chanbond_reg_i     :   std_logic;
-    signal  next_begin_c                :   std_logic;
-    signal  next_data_error_detected_c  :   std_logic;
-    signal  next_track_data_c           :   std_logic;
-    signal  start_of_packet_detected_c  :   std_logic;
-    signal  rx_chanbond_reg             :   std_logic_vector((CHANBOND_SEQ_LEN-1) downto 0);
-    signal  rx_chanbond_reg_bitwise_or_i:   std_logic;
-    signal  rx_data_aligned             :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_has_start_char_c    :   std_logic;
-    signal  rx_data_matches_bram_c      :   std_logic;
-    signal  tied_to_ground_i            :   std_logic;
-    signal  tied_to_ground_vec_i        :   std_logic_vector(31 downto 0);
-    signal  tied_to_vcc_i               :   std_logic;
-
-
---*********************************Main Body of Code***************************
-begin
-
-    --_______________________  Static signal Assigments _______________________   
-
-    tied_to_ground_i        <= '0';
-    tied_to_ground_vec_i    <= (others=>'0');
-    tied_to_vcc_i           <= '1';
-
-    --______________________ Register RXDATA once to ease timing ______________   
-
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            rx_data_r <= RX_DATA after DLY;
-        end if;
-    end process;
-
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            rxctrl_r <= RXCTRL_IN after DLY;
-        end if;
-    end process;
-    --________________________________ State machine __________________________    
-    
-    
-    -- State registers
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(RESET_ON_ERROR ='1' or SYSTEM_RESET = '1' ) then
-                begin_r                <=  '1' after DLY;
-                track_data_r           <=  '0' after DLY;
-                data_error_detected_r  <=  '0' after DLY;
-            else
-                begin_r                <=  next_begin_c after DLY;
-                track_data_r           <=  next_track_data_c after DLY;
-                data_error_detected_r  <=  next_data_error_detected_c after DLY;
-            end if;
-        end if;
-    end process;
-
-    -- Next state logic
-    next_begin_c               <=   (begin_r and not start_of_packet_detected_r) or data_error_detected_r ;
-
-    next_track_data_c          <=   (begin_r and start_of_packet_detected_r) or (track_data_r and not error_detected_r);
-                                      
-    next_data_error_detected_c <=   (track_data_r and error_detected_r);                               
-          
-    start_of_packet_detected_c <=   INC_IN when (CONFIG_INDEPENDENT_LANES=0) else rx_data_has_start_char_c;
-
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        start_of_packet_detected_r    <=   start_of_packet_detected_c after DLY;
-    end if;    
-    end process;
-    
-    -- Registering for timing
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        track_data_r2    <=   track_data_r after DLY;
-    end if;    
-    end process;
-
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        track_data_r3    <=   track_data_r2 after DLY;
-    end if;    
-    end process;
-
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        track_data_r4    <=   track_data_r3 after DLY;
-    end if;    
-    end process;
-
-    --______________________________ Capture incoming data ____________________ 
-
-
-
-datapath_width_32_40_16_or_20: if ((RX_DATA_WIDTH=16) or (RX_DATA_WIDTH=20) or (RX_DATA_WIDTH=32) or (RX_DATA_WIDTH=40)) generate
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(SYSTEM_RESET = '1') then 
-                rx_data_r2      <=  (others => '0') after DLY;
-                rx_data_r4      <=  (others => '0') after DLY;
-                rx_data_r5      <=  (others => '0') after DLY;
-                rx_data_r6      <=  (others => '0') after DLY;
-                rx_data_r7      <=  (others => '0') after DLY;
-                rx_data_r_track <=  (others => '0') after DLY;
-            else
-                rx_data_r2      <=  rx_data_r after DLY;
-                rx_data_r4      <=  rx_data_r3 after DLY;
-                rx_data_r5      <=  rx_data_r4 after DLY;
-                rx_data_r6      <=  rx_data_r5 after DLY;
-                rx_data_r7      <=  rx_data_r6 after DLY;
-                rx_data_r_track <=  rx_data_r7 after DLY;
-            end if;
-        end if;    
-    end process;
-
-    rx_data_aligned <= rx_data_r3;
-
-    --___________________________ Code for Channel bonding ____________________    
-    -- code to prevent checking of clock correction sequences for the start of packet char
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            rx_chanbond_seq_r    <=  RX_CHANBOND_SEQ after DLY;
-            rx_chanbond_seq_r2   <=  rx_chanbond_seq_r after DLY;
-            rx_chanbond_seq_r3   <=  rx_chanbond_seq_r2 after DLY;
-        end if;    
-    end process;
-
-    input_to_chanbond_reg_i  <= rx_chanbond_seq_r2;
-    input_to_chanbond_data_i <= tied_to_ground_i;
-end generate datapath_width_32_40_16_or_20;
-
-datapath_width_8_or_10: if ((RX_DATA_WIDTH=8) or (RX_DATA_WIDTH=10)) generate
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(SYSTEM_RESET = '1') then 
-                rx_data_r2      <=  (others => '0') after DLY;
-                rx_data_r3      <=  (others => '0') after DLY;
-                rx_data_r4      <=  (others => '0') after DLY;
-                rx_data_r5      <=  (others => '0') after DLY;
-                rx_data_r_track <=  (others => '0') after DLY;
-            else
-                rx_data_r2      <=  rx_data_r after DLY;
-                rx_data_r3      <=  rx_data_r2 after DLY;
-                rx_data_r4      <=  rx_data_r3 after DLY;
-                rx_data_r5      <=  rx_data_r4 after DLY;
-                rx_data_r_track <=  rx_data_r5 after DLY;
-            end if;
-        end if;    
-    end process;
-    
-    rx_data_aligned <= RX_DATA;
-    input_to_chanbond_reg_i  <= RX_CHANBOND_SEQ;
-    input_to_chanbond_data_i <= RX_CHANBOND_SEQ;
-end generate datapath_width_8_or_10;
-
-
-
-   
-
-
-
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(SYSTEM_RESET = '1') then
-              rxctrl_r2      <=  (others => '0') after DLY;
-              rxctrl_r3      <=  (others => '0') after DLY;
-            else
-              rxctrl_r2      <=  rxctrl_r after DLY;
-              rxctrl_r3      <=  rxctrl_r2 after DLY;
-            end if;
-        end if;
-    end process;
-
-    --___________________________ Code for Channel bonding ____________________    
-    -- code to prevent checking of clock correction sequences for the start of packet char
-    register_chan_seq: for i in 0 to (CHANBOND_SEQ_LEN-1) generate
-        case_i_equal_to_0: if (i=0) generate 
-            rx_chanbond_reg_0 : FD port map (Q => rx_chanbond_reg(i),D => input_to_chanbond_reg_i,C => USER_CLK);
-        end generate case_i_equal_to_0;
-        case_i_greater_than_0: if (i>0) generate 
-            rx_chanbond_reg_i :FD port map (Q => rx_chanbond_reg(i),D => rx_chanbond_reg(i-1),C => USER_CLK);
-        end generate case_i_greater_than_0;
-    end generate register_chan_seq;
-    
-    chanbondseq_in_data <= input_to_chanbond_data_i or rx_chanbond_reg_bitwise_or_i;
-
-    process(rx_chanbond_reg)
-    variable rx_chanbond_var : std_logic;
-    variable i               : std_logic;
-    begin
-        rx_chanbond_var := '0';
-        bit_wise_or : for  i in 0 to (CHANBOND_SEQ_LEN-1) loop
-            rx_chanbond_var :=  rx_chanbond_var or rx_chanbond_reg(i);
-        end loop;
-        rx_chanbond_reg_bitwise_or_i <= rx_chanbond_var;
-    end process;
-
-    process(RXCTRL_IN)
-    variable or_rxctrl_var : std_logic;
-    variable i             : std_logic;
-    begin
-        or_rxctrl_var := '0';
-        bit_wise_rxctrl_or : for  i in 0 to (RXCTRL_WIDTH-1) loop
-            or_rxctrl_var :=  or_rxctrl_var or RXCTRL_IN(i);
-        end loop;
-        rxctrl_or <= or_rxctrl_var;
-    end process;
-
-
-
-    rx_data_has_start_char_c <= '1' when ((rx_data_aligned(7 downto 0) = START_OF_PACKET_CHAR(7 downto 0)) and (chanbondseq_in_data='0') and (rxctrl_or='1')) else '0';
-
-    --_____________________________ Assign output ports _______________________    
-
-    TRACK_DATA      <=  track_data_r;    
-
-
-    -- Drive the enamcommaalign port of the mgt for alignment
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if(SYSTEM_RESET = '1') then 
-            RX_ENMCOMMA_ALIGN   <= '0' after DLY;
-        else              
-            RX_ENMCOMMA_ALIGN   <= '1' after DLY;
-        end if;
-    end if;    
-    end process;
-
-    -- Drive the enapcommaalign port of the mgt for alignment
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if(SYSTEM_RESET = '1') then  
-            RX_ENPCOMMA_ALIGN   <= '0' after DLY;
-        else              
-            RX_ENPCOMMA_ALIGN   <= '1' after DLY;
-        end if;
-    end if;    
-    end process;
-
-    INC_OUT         <=  start_of_packet_detected_c;   
-
-    PATTERN_MATCH_N <=  data_error_detected_r;
-
-    -- Drive the enchansync port of the mgt for channel bonding
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if(SYSTEM_RESET = '1') then 
-            RX_ENCHAN_SYNC   <= '0' after DLY;
-        else              
-            RX_ENCHAN_SYNC   <= '1' after DLY;
-        end if;
-    end if;    
-    end process;
-    
-    --___________________________ Check incoming data for errors ______________
-         
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-            bram_data_r   <= bram_data_i after DLY;
-    end if;    
-    end process;
-    
-    --An error is detected when data read for the BRAM does not match the incoming data
-use_40bit : if RX_DATA_WIDTH = 40 generate
-    rx_data_matches_bram_c <= '0' when (rx_data_r_track /= (tied_to_ground_vec_i(7 downto 0) & bram_data_r)) else '1';
-end generate use_40bit;
-
-not_40bit : if RX_DATA_WIDTH /= 40 generate
-    rx_data_matches_bram_c <= '0' when (rx_data_r_track /= bram_data_r((RX_DATA_WIDTH-1) downto 0)) else '1';
-end generate not_40bit;
-
-    error_detected_c    <=   track_data_r4 and not rx_data_matches_bram_c;   
-    
-    
-enable_error_check : if USE_COMMA = 1 generate
-    --We register the error_detected signal for use with the error counter logic
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if(not(track_data_r = '1')) then 
-            error_detected_r    <= '0' after DLY;
-        else
-            error_detected_r    <=  error_detected_c after DLY;
-        end if;
-    end if;    
-    end process;
-end generate enable_error_check;
-
-disable_error_check : if USE_COMMA = 0 generate
-    -- Since the comma detect logic has not been enabled, the error counter has been disabled since
-    -- it doesnt make sense to be searching for an align character in the data. To enable the error 
-    -- count again, please see the code above
-    
-       error_detected_r    <= '0';
-
-end generate disable_error_check;
-
-    
-    --We count the total number of errors we detect. By keeping a count we make it less likely that we will miss
-    --errors we did not directly observe. This counter must be reset when it reaches its max value
-    process ( USER_CLK )
-    begin
-    if( USER_CLK'event and USER_CLK = '1') then
-        if(SYSTEM_RESET='1') then
-            error_count_r       <=  (others => '0') after DLY;
-        elsif(error_detected_r = '1') then
-            error_count_r       <=  error_count_r + 1 after DLY;
-        end if;
-    end if;
-    end process;
-        
-            
-    --Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches
-    --max value) to the module output
-    ERROR_COUNT     <=   std_logic_vector(error_count_r(7 downto 0));
-
-    --____________________________ Counter to read from BRAM __________________________    
-four_byte : if RX_DATA_WIDTH > 20 generate
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1)))  then
-            read_counter_i   <=  (others => '0') after DLY;
-        elsif(((start_of_packet_detected_r and not track_data_r)='1')) then
-            read_counter_i   <=  "000000001" after DLY;
-        else read_counter_i  <=  read_counter_i + 1 after DLY;
-        end if;
-    end if;
-    end process;
-end generate four_byte;
-
-one_or_two_byte : if RX_DATA_WIDTH <= 20 generate
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))
-        or ((start_of_packet_detected_r and not track_data_r)='1'))  then
-            read_counter_i   <=  (others => '0') after DLY;
-        else read_counter_i  <=  read_counter_i + 1 after DLY;
-        end if;
-    end if;
-    end process;
-end generate one_or_two_byte;
-
-    --________________________________ BRAM Instantiation _____________________________    
-
-    dual_port_block_ram_i  :  RAMB16_S36_S36 
-    generic map
-    (
-        INIT_00          =>  MEM_00,
-        INIT_01          =>  MEM_01,
-        INIT_02          =>  MEM_02,
-        INIT_03          =>  MEM_03,
-        INIT_04          =>  MEM_04,
-        INIT_05          =>  MEM_05,
-        INIT_06          =>  MEM_06,
-        INIT_07          =>  MEM_07,
-        INIT_08          =>  MEM_08,
-        INIT_09          =>  MEM_09,
-        INIT_0A          =>  MEM_0A,
-        INIT_0B          =>  MEM_0B,
-        INIT_0C          =>  MEM_0C,
-        INIT_0D          =>  MEM_0D,
-        INIT_0E          =>  MEM_0E,
-        INIT_0F          =>  MEM_0F,
-        INIT_10          =>  MEM_10,
-        INIT_11          =>  MEM_11,
-        INIT_12          =>  MEM_12,
-        INIT_13          =>  MEM_13,
-        INIT_14          =>  MEM_14,
-        INIT_15          =>  MEM_15,
-        INIT_16          =>  MEM_16,
-        INIT_17          =>  MEM_17,
-        INIT_18          =>  MEM_18,
-        INIT_19          =>  MEM_19,
-        INIT_1A          =>  MEM_1A,
-        INIT_1B          =>  MEM_1B,
-        INIT_1C          =>  MEM_1C,
-        INIT_1D          =>  MEM_1D,
-        INIT_1E          =>  MEM_1E,
-        INIT_1F          =>  MEM_1F,
-        INIT_20          =>  MEM_20,
-        INIT_21          =>  MEM_21,
-        INIT_22          =>  MEM_22,
-        INIT_23          =>  MEM_23,
-        INIT_24          =>  MEM_24,
-        INIT_25          =>  MEM_25,
-        INIT_26          =>  MEM_26,
-        INIT_27          =>  MEM_27,
-        INIT_28          =>  MEM_28,
-        INIT_29          =>  MEM_29,
-        INIT_2A          =>  MEM_2A,
-        INIT_2B          =>  MEM_2B,
-        INIT_2C          =>  MEM_2C,
-        INIT_2D          =>  MEM_2D,
-        INIT_2E          =>  MEM_2E,
-        INIT_2F          =>  MEM_2F,
-        INIT_30          =>  MEM_30,
-        INIT_31          =>  MEM_31,
-        INIT_32          =>  MEM_32,
-        INIT_33          =>  MEM_33,
-        INIT_34          =>  MEM_34,
-        INIT_35          =>  MEM_35,
-        INIT_36          =>  MEM_36,
-        INIT_37          =>  MEM_37,
-        INIT_38          =>  MEM_38,
-        INIT_39          =>  MEM_39,
-        INIT_3A          =>  MEM_3A,
-        INIT_3B          =>  MEM_3B,
-        INIT_3C          =>  MEM_3C,
-        INIT_3D          =>  MEM_3D,
-        INIT_3E          =>  MEM_3E,
-        INIT_3F          =>  MEM_3F,
-        INITP_00         =>  MEMP_00,
-        INITP_01         =>  MEMP_01,
-        INITP_02         =>  MEMP_02,
-        INITP_03         =>  MEMP_03,
-        INITP_04         =>  MEMP_04,
-        INITP_05         =>  MEMP_05,
-        INITP_06         =>  MEMP_06,
-        INITP_07         =>  MEMP_07
-
-    )
-    port map 
-    (
-        ADDRA            =>  std_logic_vector(read_counter_i),
-        DIA              =>  tied_to_ground_vec_i(31 downto 0),
-        DIPA             =>  tied_to_ground_vec_i(3 downto 0),
-        DOA              =>  bram_data_i,
-        DOPA             =>  open, 
-        WEA              =>  tied_to_ground_i,
-        ENA              =>  tied_to_vcc_i,
-        SSRA             =>  tied_to_ground_i, 
-        CLKA             =>  USER_CLK,
-                  
-        ADDRB            =>  tied_to_ground_vec_i(8 downto 0),
-        DIB              =>  tied_to_ground_vec_i(31 downto 0),
-        DIPB             =>  tied_to_ground_vec_i(3 downto 0),
-        DOB              =>  open,  
-        DOPB             =>  open, 
-        WEB              =>  tied_to_ground_i,
-        ENB              =>  tied_to_ground_i,
-        SSRB             =>  tied_to_ground_i,
-        CLKB             =>  tied_to_ground_i       
-    );       
-    
-    
-end RTL;           
-
diff --git a/FEE_ADC32board/project/ipcore_dir/frame_gen.vhd b/FEE_ADC32board/project/ipcore_dir/frame_gen.vhd
deleted file mode 100644
index 2d76452..0000000
--- a/FEE_ADC32board/project/ipcore_dir/frame_gen.vhd
+++ /dev/null
@@ -1,329 +0,0 @@
--------------------------------------------------------------------------------
---   ____  ____ 
---  /   /\/   / 
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
---  /   /         Filename : frame_gen.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\ 
---
---
--- Module FRAME_GEN
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
---***********************************Entity Declaration************************
-
-entity FRAME_GEN is
-generic
-(
-    WORDS_IN_BRAM : integer    :=   256;
-    MEM_00       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_01       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_02       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_03       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_04       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_05       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_06       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_07       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_08       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_09       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_10       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_11       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_12       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_13       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_14       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_15       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_16       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_17       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_18       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_19       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_20       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_21       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_22       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_23       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_24       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_25       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_26       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_27       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_28       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_29       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_30       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_31       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_32       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_33       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_34       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_35       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_36       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_37       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_38       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_39       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_00      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_01      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_02      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_03      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_04      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_05      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_06      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_07      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000"
-);    
-port
-(
-    -- User Interface
-    TX_DATA             : out   std_logic_vector(39 downto 0);
-    TX_CHARISK          : out   std_logic_vector(3 downto 0); 
-
-    -- System Interface
-    USER_CLK            : in    std_logic;      
-    SYSTEM_RESET        : in    std_logic
-); 
-
-
-end FRAME_GEN;
-
-architecture RTL of FRAME_GEN is
-
---***********************************Parameter Declarations********************
-
-    constant DLY : time := 1 ns;
-
---********************************* Wire Declarations************************** 
-
-    signal  tx_charisk_i            :   std_logic_vector(3 downto 0);
-    signal  tx_data_bram_i          :   std_logic_vector(31 downto 0);
-    signal  tied_to_ground_vec_i    :   std_logic_vector(31 downto 0);
-    signal  tied_to_ground_i        :   std_logic;
-    signal  tied_to_vcc_i           :   std_logic;
-    signal  tied_to_vcc_vec_i       :   std_logic_vector(15 downto 0);
-
---***************************Internal signalister Declarations******************** 
-
-    signal  read_counter_i          :   unsigned(8 downto 0);    
-
-
---*********************************Main Body of Code***************************
-begin
-
-    tied_to_ground_vec_i    <=   (others=>'0');
-    tied_to_ground_i        <=   '0';
-    tied_to_vcc_i           <=   '1';
-            
-    --__________________________ Counter to read from BRAM ____________________    
-    
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1)))then
-                read_counter_i <= (others => '0') after DLY;
-            else
-                read_counter_i <= read_counter_i + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-    -- Assign TX_DATA to BRAM output
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(SYSTEM_RESET='1') then
-                TX_DATA      <= (others => '0') after DLY;
-            else
-                TX_DATA      <= (tied_to_ground_vec_i(7 downto 0) & tx_data_bram_i) after DLY; 
-            end if;
-        end if;
-    end process;
-
-    -- Assign TX_CHARISK to BRAM output
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(SYSTEM_RESET='1') then
-                TX_CHARISK    <= (others => '0') after DLY;
-            else
-                TX_CHARISK    <= tx_charisk_i after DLY; 
-            end if;
-        end if;
-    end process;
-
-    --______________________________ BRAM Instantiation _______________________    
-
-    dual_port_block_ram_i  :  RAMB16_S36_S36 
-    generic map
-    (
-        INIT_00          =>  MEM_00,
-        INIT_01          =>  MEM_01,
-        INIT_02          =>  MEM_02,
-        INIT_03          =>  MEM_03,
-        INIT_04          =>  MEM_04,
-        INIT_05          =>  MEM_05,
-        INIT_06          =>  MEM_06,
-        INIT_07          =>  MEM_07,
-        INIT_08          =>  MEM_08,
-        INIT_09          =>  MEM_09,
-        INIT_0A          =>  MEM_0A,
-        INIT_0B          =>  MEM_0B,
-        INIT_0C          =>  MEM_0C,
-        INIT_0D          =>  MEM_0D,
-        INIT_0E          =>  MEM_0E,
-        INIT_0F          =>  MEM_0F,
-        INIT_10          =>  MEM_10,
-        INIT_11          =>  MEM_11,
-        INIT_12          =>  MEM_12,
-        INIT_13          =>  MEM_13,
-        INIT_14          =>  MEM_14,
-        INIT_15          =>  MEM_15,
-        INIT_16          =>  MEM_16,
-        INIT_17          =>  MEM_17,
-        INIT_18          =>  MEM_18,
-        INIT_19          =>  MEM_19,
-        INIT_1A          =>  MEM_1A,
-        INIT_1B          =>  MEM_1B,
-        INIT_1C          =>  MEM_1C,
-        INIT_1D          =>  MEM_1D,
-        INIT_1E          =>  MEM_1E,
-        INIT_1F          =>  MEM_1F,
-        INIT_20          =>  MEM_20,
-        INIT_21          =>  MEM_21,
-        INIT_22          =>  MEM_22,
-        INIT_23          =>  MEM_23,
-        INIT_24          =>  MEM_24,
-        INIT_25          =>  MEM_25,
-        INIT_26          =>  MEM_26,
-        INIT_27          =>  MEM_27,
-        INIT_28          =>  MEM_28,
-        INIT_29          =>  MEM_29,
-        INIT_2A          =>  MEM_2A,
-        INIT_2B          =>  MEM_2B,
-        INIT_2C          =>  MEM_2C,
-        INIT_2D          =>  MEM_2D,
-        INIT_2E          =>  MEM_2E,
-        INIT_2F          =>  MEM_2F,
-        INIT_30          =>  MEM_30,
-        INIT_31          =>  MEM_31,
-        INIT_32          =>  MEM_32,
-        INIT_33          =>  MEM_33,
-        INIT_34          =>  MEM_34,
-        INIT_35          =>  MEM_35,
-        INIT_36          =>  MEM_36,
-        INIT_37          =>  MEM_37,
-        INIT_38          =>  MEM_38,
-        INIT_39          =>  MEM_39,
-        INIT_3A          =>  MEM_3A,
-        INIT_3B          =>  MEM_3B,
-        INIT_3C          =>  MEM_3C,
-        INIT_3D          =>  MEM_3D,
-        INIT_3E          =>  MEM_3E,
-        INIT_3F          =>  MEM_3F,
-        INITP_00         =>  MEMP_00,
-        INITP_01         =>  MEMP_01,
-        INITP_02         =>  MEMP_02,
-        INITP_03         =>  MEMP_03,
-        INITP_04         =>  MEMP_04,
-        INITP_05         =>  MEMP_05,
-        INITP_06         =>  MEMP_06,
-        INITP_07         =>  MEMP_07
-    )
-    port map 
-    (
-        ADDRA            =>  std_logic_vector(read_counter_i),
-        DIA              =>  tied_to_ground_vec_i(31 downto 0),
-        DIPA             =>  tied_to_ground_vec_i(3 downto 0),
-        DOA              =>  tx_data_bram_i,
-        DOPA             =>  tx_charisk_i, 
-        WEA              =>  tied_to_ground_i,
-        ENA              =>  tied_to_vcc_i,
-        SSRA             =>  tied_to_ground_i, 
-        CLKA             =>  USER_CLK,
-                         
-        ADDRB            =>  tied_to_ground_vec_i(8 downto 0),
-        DIB              =>  tied_to_ground_vec_i(31 downto 0),
-        DIPB             =>  tied_to_ground_vec_i(3 downto 0),
-        DOB              =>  open,  
-        DOPB             =>  open, 
-        WEB              =>  tied_to_ground_i,
-        ENB              =>  tied_to_ground_i,
-        SSRB             =>  tied_to_ground_i,
-        CLKB             =>  tied_to_ground_i       
-    );                   
-
-end RTL;
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.gise b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.gise
deleted file mode 100644
index f0166db..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.gise
+++ /dev/null
@@ -1,51 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="gtxVirtex6FEE80.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="gtxvirtex6fee80.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1409562302" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1409562302">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-2856154284446432025" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="4212411167637456903" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6456468924679109783" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.vho b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.vho
deleted file mode 100644
index f9439a3..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.vho
+++ /dev/null
@@ -1,270 +0,0 @@
-------------------------------------------------------------------------------
---   ____  ____ 
---  /   /\/   / 
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
---  /   /         Filename : gtxvirtex6fee80.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Instantiation Template
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-
-
---**************************Component Declarations*****************************
-
-
-component gtxVirtex6FEE80 
-generic
-(
-    -- Simulation attributes
-    WRAPPER_SIM_GTXRESET_SPEEDUP    : integer   := 0 -- Set to 1 to speed up sim reset
-);
-port
-(
-    
-    --_________________________________________________________________________
-    --_________________________________________________________________________
-    --GTX0  (X0_Y12)
-
-    ----------------------- Receive Ports - 8b10b Decoder ----------------------
-    GTX0_RXCHARISK_OUT                      : out  std_logic;
-    GTX0_RXDISPERR_OUT                      : out  std_logic;
-    GTX0_RXNOTINTABLE_OUT                   : out  std_logic;
-    --------------- Receive Ports - Comma Detection and Alignment --------------
-    GTX0_RXENMCOMMAALIGN_IN                 : in   std_logic;
-    GTX0_RXENPCOMMAALIGN_IN                 : in   std_logic;
-    ------------------- Receive Ports - RX Data Path interface -----------------
-    GTX0_RXDATA_OUT                         : out  std_logic_vector(7 downto 0);
-    GTX0_RXRECCLK_OUT                       : out  std_logic;
-    GTX0_RXRESET_IN                         : in   std_logic;
-    GTX0_RXUSRCLK2_IN                       : in   std_logic;
-    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-    GTX0_RXCDRRESET_IN                      : in   std_logic;
-    GTX0_RXN_IN                             : in   std_logic;
-    GTX0_RXP_IN                             : in   std_logic;
-    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-    GTX0_RXDLYALIGNDISABLE_IN               : in   std_logic;
-    GTX0_RXDLYALIGNMONENB_IN                : in   std_logic;
-    GTX0_RXDLYALIGNMONITOR_OUT              : out  std_logic_vector(7 downto 0);
-    GTX0_RXDLYALIGNOVERRIDE_IN              : in   std_logic;
-    GTX0_RXDLYALIGNRESET_IN                 : in   std_logic;
-    GTX0_RXENPMAPHASEALIGN_IN               : in   std_logic;
-    GTX0_RXPMASETPHASE_IN                   : in   std_logic;
-    GTX0_RXSTATUS_OUT                       : out  std_logic_vector(2 downto 0);
-    --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-    GTX0_RXLOSSOFSYNC_OUT                   : out  std_logic_vector(1 downto 0);
-    ------------------------ Receive Ports - RX PLL Ports ----------------------
-    GTX0_GTXRXRESET_IN                      : in   std_logic;
-    GTX0_MGTREFCLKRX_IN                     : in   std_logic;
-    GTX0_PLLRXRESET_IN                      : in   std_logic;
-    GTX0_RXPLLLKDET_OUT                     : out  std_logic;
-    GTX0_RXRESETDONE_OUT                    : out  std_logic;
-    -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-    GTX0_PHYSTATUS_OUT                      : out  std_logic;
-    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-    GTX0_TXCHARISK_IN                       : in   std_logic;
-    ------------------------- Transmit Ports - GTX Ports -----------------------
-    GTX0_GTXTEST_IN                         : in   std_logic_vector(12 downto 0);
-    ------------------ Transmit Ports - TX Data Path interface -----------------
-    GTX0_TXDATA_IN                          : in   std_logic_vector(7 downto 0);
-    GTX0_TXOUTCLK_OUT                       : out  std_logic;
-    GTX0_TXRESET_IN                         : in   std_logic;
-    GTX0_TXUSRCLK2_IN                       : in   std_logic;
-    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-    GTX0_TXN_OUT                            : out  std_logic;
-    GTX0_TXP_OUT                            : out  std_logic;
-    -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-    GTX0_TXDLYALIGNDISABLE_IN               : in   std_logic;
-    GTX0_TXDLYALIGNMONENB_IN                : in   std_logic;
-    GTX0_TXDLYALIGNMONITOR_OUT              : out  std_logic_vector(7 downto 0);
-    GTX0_TXDLYALIGNRESET_IN                 : in   std_logic;
-    GTX0_TXENPMAPHASEALIGN_IN               : in   std_logic;
-    GTX0_TXPMASETPHASE_IN                   : in   std_logic;
-    ----------------------- Transmit Ports - TX PLL Ports ----------------------
-    GTX0_GTXTXRESET_IN                      : in   std_logic;
-    GTX0_TXRESETDONE_OUT                    : out  std_logic
-
-
-);
-end component;
-
-
-
-component gtxvirtex6fee80_tx_sync 
-port
-(
-    TXENPMAPHASEALIGN       : out std_logic;
-    TXPMASETPHASE           : out std_logic;
-    TXDLYALIGNDISABLE       : out std_logic;
-    TXDLYALIGNRESET         : out std_logic;
-    SYNC_DONE               : out std_logic;
-    USER_CLK                : in  std_logic;
-    RESET                   : in  std_logic
-);
-end component;
-
-component gtxvirtex6fee80_rx_sync 
-port
-(
-    RXENPMAPHASEALIGN       : out std_logic;
-    RXPMASETPHASE           : out std_logic;
-    RXDLYALIGNDISABLE       : out std_logic;
-    RXDLYALIGNRESET         : out std_logic;
-    SYNC_DONE               : out std_logic;
-    USER_CLK                : in  std_logic;
-    RESET                   : in  std_logic
-);
-end component;
-
-
-
-
-
-
-    ----------------------------- The GTX Wrapper -----------------------------
-
-
-    gtxVirtex6FEE80_i : gtxVirtex6FEE80
-    generic map
-    (
-        WRAPPER_SIM_GTXRESET_SPEEDUP    =>      1
-    )
-    port map
-    (
-        --_____________________________________________________________________
-        --_____________________________________________________________________
-        --GTX0  (X0Y12)
-
-        ----------------------- Receive Ports - 8b10b Decoder ----------------------
-        GTX0_RXCHARISK_OUT              =>      ,
-        GTX0_RXDISPERR_OUT              =>      ,
-        GTX0_RXNOTINTABLE_OUT           =>      ,
-        --------------- Receive Ports - Comma Detection and Alignment --------------
-        GTX0_RXENMCOMMAALIGN_IN         =>      ,
-        GTX0_RXENPCOMMAALIGN_IN         =>      ,
-        ------------------- Receive Ports - RX Data Path interface -----------------
-        GTX0_RXDATA_OUT                 =>      ,
-        GTX0_RXRECCLK_OUT               =>      ,
-        GTX0_RXRESET_IN                 =>      ,
-        GTX0_RXUSRCLK2_IN               =>      ,
-        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-        GTX0_RXCDRRESET_IN              =>      ,
-        GTX0_RXN_IN                     =>      ,
-        GTX0_RXP_IN                     =>      ,
-        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-        GTX0_RXDLYALIGNDISABLE_IN       =>      ,
-        GTX0_RXDLYALIGNMONENB_IN        =>      ,
-        GTX0_RXDLYALIGNMONITOR_OUT      =>      ,
-        GTX0_RXDLYALIGNOVERRIDE_IN      =>      ,
-        GTX0_RXDLYALIGNRESET_IN         =>      ,
-        GTX0_RXENPMAPHASEALIGN_IN       =>      ,
-        GTX0_RXPMASETPHASE_IN           =>      ,
-        GTX0_RXSTATUS_OUT               =>      ,
-        --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-        GTX0_RXLOSSOFSYNC_OUT           =>      ,
-        ------------------------ Receive Ports - RX PLL Ports ----------------------
-        GTX0_GTXRXRESET_IN              =>      ,
-        GTX0_MGTREFCLKRX_IN             =>      ,
-        GTX0_PLLRXRESET_IN              =>      ,
-        GTX0_RXPLLLKDET_OUT             =>      ,
-        GTX0_RXRESETDONE_OUT            =>      ,
-        -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-        GTX0_PHYSTATUS_OUT              =>      ,
-        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-        GTX0_TXCHARISK_IN               =>      ,
-        ------------------------- Transmit Ports - GTX Ports -----------------------
-        GTX0_GTXTEST_IN                 =>      ,
-        ------------------ Transmit Ports - TX Data Path interface -----------------
-        GTX0_TXDATA_IN                  =>      ,
-        GTX0_TXOUTCLK_OUT               =>      ,
-        GTX0_TXRESET_IN                 =>      ,
-        GTX0_TXUSRCLK2_IN               =>      ,
-        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-        GTX0_TXN_OUT                    =>      ,
-        GTX0_TXP_OUT                    =>      ,
-        -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-        GTX0_TXDLYALIGNDISABLE_IN       =>      ,
-        GTX0_TXDLYALIGNMONENB_IN        =>      ,
-        GTX0_TXDLYALIGNMONITOR_OUT      =>      ,
-        GTX0_TXDLYALIGNRESET_IN         =>      ,
-        GTX0_TXENPMAPHASEALIGN_IN       =>      ,
-        GTX0_TXPMASETPHASE_IN           =>      ,
-        ----------------------- Transmit Ports - TX PLL Ports ----------------------
-        GTX0_GTXTXRESET_IN              =>      ,
-        GTX0_TXRESETDONE_OUT            =>      
-
-
-    );
-
-
-
-    -----------------------Dedicated GTX Reference Clock Inputs ---------------
-    -- Each dedicated refclk you are using in your design will need its own IBUFDS_GTXE1 instance
-    
-    q3_clk0_refclk_ibufds_i : IBUFDS_GTXE1
-    port map
-    (
-        O                               =>      ,
-        ODIV2                           =>      ,
-        CEB                             =>      ,
-        I                               =>      ,  -- Connect to package pin L4
-        IB                              =>        -- Connect to package pin L3
-    );
-
-
-
-
-
-    ------------------------------ TXSYNC module ------------------------------
-    -- Since you are bypassing the TX Buffer in your wrapper, you will need to drive
-    -- the phase alignment ports to align the phase of the TX Datapath. Include
-    -- this module in your design to have phase alignment performed automatically as
-    -- it is done in the example design.
-
-    
-    gtx0_txsync_i : gtxvirtex6fee80_tx_sync
-    port map
-    (
-        TXENPMAPHASEALIGN               =>            
-        TXPMASETPHASE                   =>      
-        TXDLYALIGNDISABLE               =>      
-        TXDLYALIGNRESET                 =>      
-        SYNC_DONE                       =>      
-        USER_CLK                        =>      
-        RESET                           =>      ,
-    );
-
-
-    ---------------------------- RXSYNC modules -------------------------------
-    -- The RXSYNC module performs phase synchronization for all the active RX datapaths. It
-    -- waits for the user clocks to be stable, then drives the RX phase align signals on each
-    -- GTX. When phase synchronization is complete, it asserts SYNC_DONE
-    
-    -- Include one RX_SYNC module per Buffer bypassed RX datapath in your own design. RX_SYNC modules
-    -- can also be shared, but when sharing, make sure to hold the module in reset until all lanes have 
-    -- a stable clock
-    
-  
-    
-    gtx0_rxsync_i : gtxvirtex6fee80_rx_sync
-    port map
-    (
-        RXENPMAPHASEALIGN               =>          
-        RXPMASETPHASE                   =>      
-        RXDLYALIGNDISABLE               =>      
-        RXDLYALIGNRESET                 =>      
-        SYNC_DONE                       =>      
-        USER_CLK                        =>      
-        RESET                           =>      ,
-    );
-    
-
-
-
-
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.xco b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.xco
deleted file mode 100644
index 3377535..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.xco
+++ /dev/null
@@ -1,411 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Mon Dec 01 12:54:17 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:v6_gtxwizard:1.12
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Virtex-6_FPGA_GTX_Transceiver_Wizard xilinx.com:ip:v6_gtxwizard:1.12
-# END Select
-# BEGIN Parameters
-CSET advanced_clocking=false
-CSET bytes_to_reduce_error=8
-CSET cb_seq_1_1=00000000
-CSET cb_seq_1_1_disp=false
-CSET cb_seq_1_1_k=false
-CSET cb_seq_1_1_mask=true
-CSET cb_seq_1_2=00000000
-CSET cb_seq_1_2_disp=false
-CSET cb_seq_1_2_k=false
-CSET cb_seq_1_2_mask=true
-CSET cb_seq_1_3=00000000
-CSET cb_seq_1_3_disp=false
-CSET cb_seq_1_3_k=false
-CSET cb_seq_1_3_mask=true
-CSET cb_seq_1_4=00000000
-CSET cb_seq_1_4_disp=false
-CSET cb_seq_1_4_k=false
-CSET cb_seq_1_4_mask=true
-CSET cb_seq_2_1=00000000
-CSET cb_seq_2_1_disp=false
-CSET cb_seq_2_1_k=false
-CSET cb_seq_2_1_mask=true
-CSET cb_seq_2_2=00000000
-CSET cb_seq_2_2_disp=false
-CSET cb_seq_2_2_k=false
-CSET cb_seq_2_2_mask=true
-CSET cb_seq_2_3=00000000
-CSET cb_seq_2_3_disp=false
-CSET cb_seq_2_3_k=false
-CSET cb_seq_2_3_mask=true
-CSET cb_seq_2_4=00000000
-CSET cb_seq_2_4_disp=false
-CSET cb_seq_2_4_k=false
-CSET cb_seq_2_4_mask=true
-CSET cb_sequence_1_max_skew=1
-CSET cb_sequence_2_max_skew=1
-CSET cb_sequence_length=1
-CSET cc_keep_one_idle=false
-CSET cc_seq_1_1=00000000
-CSET cc_seq_1_1_disp=false
-CSET cc_seq_1_1_k=true
-CSET cc_seq_1_1_mask=true
-CSET cc_seq_1_2=00000000
-CSET cc_seq_1_2_disp=false
-CSET cc_seq_1_2_k=true
-CSET cc_seq_1_2_mask=true
-CSET cc_seq_1_3=00000000
-CSET cc_seq_1_3_disp=false
-CSET cc_seq_1_3_k=true
-CSET cc_seq_1_3_mask=true
-CSET cc_seq_1_4=00000000
-CSET cc_seq_1_4_disp=false
-CSET cc_seq_1_4_k=true
-CSET cc_seq_1_4_mask=true
-CSET cc_seq_2_1=00000000
-CSET cc_seq_2_1_disp=false
-CSET cc_seq_2_1_k=true
-CSET cc_seq_2_1_mask=true
-CSET cc_seq_2_2=00000000
-CSET cc_seq_2_2_disp=false
-CSET cc_seq_2_2_k=true
-CSET cc_seq_2_2_mask=true
-CSET cc_seq_2_3=00000000
-CSET cc_seq_2_3_disp=false
-CSET cc_seq_2_3_k=true
-CSET cc_seq_2_3_mask=true
-CSET cc_seq_2_4=00000000
-CSET cc_seq_2_4_disp=false
-CSET cc_seq_2_4_k=true
-CSET cc_seq_2_4_mask=true
-CSET cc_sequence_length=1
-CSET cdr_ph_adj_time=10100
-CSET chan_bond_keep_align=false
-CSET chan_bond_seq_2_cfg=00000
-CSET clk_cor_precedence=CC
-CSET clk_cor_repeat_wait=0
-CSET column=Left
-CSET com_burst_val=15
-CSET comma_alignment=Any_Byte_Boundary
-CSET comma_double=false
-CSET comma_mask=1111111100
-CSET comma_preset=K28.5
-CSET component_name=gtxVirtex6FEE80
-CSET dec_mcomma_detect=false
-CSET dec_pcomma_detect=false
-CSET dec_valid_comma_only=false
-CSET decoding=8B/10B
-CSET dfe_mode=Fixed_tap_mode
-CSET disable_ac_coupling=true
-CSET driver_swing=1000
-CSET en_idle_reset_buf=false
-CSET enable_dfe=false
-CSET encoding=8B/10B
-CSET errors_to_lose_sync=256
-CSET fifo_lower_bounds=14
-CSET fifo_upper_bounds=16
-CSET highpass_pole_location=Use_RXEQPOLE_Port
-CSET max_cb_level=7
-CSET mcomma_detect=true
-CSET minus_comma=1010000011
-CSET oob_clk_divider=0000000
-CSET pci_express_mode=false
-CSET pcomma_detect=true
-CSET pll_sata=false
-CSET plus_comma=0101111100
-CSET postemphasis_level=00000
-CSET ppm_offset=0_(Synchronous)
-CSET preemphasis_level=0000
-CSET protocol_file=Start_from_scratch
-CSET refclk_ac_coupling_x0_y0=false
-CSET refclk_ac_coupling_x0_y1=false
-CSET refclk_ac_coupling_x0_y10=false
-CSET refclk_ac_coupling_x0_y11=false
-CSET refclk_ac_coupling_x0_y12=false
-CSET refclk_ac_coupling_x0_y13=false
-CSET refclk_ac_coupling_x0_y14=false
-CSET refclk_ac_coupling_x0_y15=false
-CSET refclk_ac_coupling_x0_y16=false
-CSET refclk_ac_coupling_x0_y17=false
-CSET refclk_ac_coupling_x0_y18=false
-CSET refclk_ac_coupling_x0_y19=false
-CSET refclk_ac_coupling_x0_y2=false
-CSET refclk_ac_coupling_x0_y20=false
-CSET refclk_ac_coupling_x0_y21=false
-CSET refclk_ac_coupling_x0_y22=false
-CSET refclk_ac_coupling_x0_y23=false
-CSET refclk_ac_coupling_x0_y3=false
-CSET refclk_ac_coupling_x0_y4=false
-CSET refclk_ac_coupling_x0_y5=false
-CSET refclk_ac_coupling_x0_y6=false
-CSET refclk_ac_coupling_x0_y7=false
-CSET refclk_ac_coupling_x0_y8=false
-CSET refclk_ac_coupling_x0_y9=false
-CSET rx_datapath_width=8
-CSET rx_decode_seq_match=true
-CSET rx_divider=/2
-CSET rx_en_idle_hold_cdr=false
-CSET rx_en_idle_hold_dfe=true
-CSET rx_en_idle_reset_fr=false
-CSET rx_en_idle_reset_ph=false
-CSET rx_en_mode_reset_buf=true
-CSET rx_en_rate_reset_buf=true
-CSET rx_en_realign_reset_buf=false
-CSET rx_fifo_addr_mode=FULL
-CSET rx_idle_hi_cnt=1000
-CSET rx_idle_lo_cnt=0000
-CSET rx_line_rate=2
-CSET rx_oob_threshold=011
-CSET rx_refclk_x0_y0=REFCLK1_Q0
-CSET rx_refclk_x0_y1=REFCLK1_Q0
-CSET rx_refclk_x0_y10=REFCLK1_Q2
-CSET rx_refclk_x0_y11=REFCLK1_Q2
-CSET rx_refclk_x0_y12=REFCLK0_Q3
-CSET rx_refclk_x0_y13=REFCLK1_Q3
-CSET rx_refclk_x0_y14=REFCLK1_Q3
-CSET rx_refclk_x0_y15=REFCLK1_Q3
-CSET rx_refclk_x0_y16=REFCLK1_Q4
-CSET rx_refclk_x0_y17=REFCLK1_Q4
-CSET rx_refclk_x0_y18=REFCLK1_Q4
-CSET rx_refclk_x0_y19=REFCLK1_Q4
-CSET rx_refclk_x0_y2=REFCLK1_Q0
-CSET rx_refclk_x0_y20=REFCLK1_Q5
-CSET rx_refclk_x0_y21=REFCLK1_Q5
-CSET rx_refclk_x0_y22=REFCLK1_Q5
-CSET rx_refclk_x0_y23=REFCLK1_Q5
-CSET rx_refclk_x0_y24=REFCLK1_Q6
-CSET rx_refclk_x0_y25=REFCLK1_Q6
-CSET rx_refclk_x0_y26=REFCLK1_Q6
-CSET rx_refclk_x0_y27=REFCLK1_Q6
-CSET rx_refclk_x0_y28=REFCLK1_Q7
-CSET rx_refclk_x0_y29=REFCLK1_Q7
-CSET rx_refclk_x0_y3=REFCLK1_Q0
-CSET rx_refclk_x0_y30=REFCLK1_Q7
-CSET rx_refclk_x0_y31=REFCLK1_Q7
-CSET rx_refclk_x0_y32=REFCLK1_Q8
-CSET rx_refclk_x0_y33=REFCLK1_Q8
-CSET rx_refclk_x0_y34=REFCLK1_Q8
-CSET rx_refclk_x0_y35=REFCLK1_Q8
-CSET rx_refclk_x0_y4=REFCLK1_Q1
-CSET rx_refclk_x0_y5=REFCLK1_Q1
-CSET rx_refclk_x0_y6=REFCLK1_Q1
-CSET rx_refclk_x0_y7=REFCLK1_Q1
-CSET rx_refclk_x0_y8=REFCLK1_Q2
-CSET rx_refclk_x0_y9=REFCLK1_Q2
-CSET rx_reference_clock=80.00
-CSET rx_slide_mode=OFF
-CSET rx_termination_voltage=MGTAVTT
-CSET rxlossofsyncport=true
-CSET rxrecclk_source=AUTO
-CSET rxrundisp_indicates_cc=false
-CSET rxusrclk_source=RXRECCLK
-CSET sas_max_comsas=52
-CSET sas_min_comsas=40
-CSET sata_burst_val=4
-CSET sata_idle_val=4
-CSET second_order_cdr_loop=false
-CSET show_realign_comma=true
-CSET sync_app=true
-CSET termination_ctrl=00000
-CSET termination_imp=50
-CSET termination_ovrd=false
-CSET trans_time_from_p2=60
-CSET trans_time_non_p2=25
-CSET trans_time_rate=FF
-CSET trans_time_to_p2=100
-CSET tx_datapath_width=8
-CSET tx_divider=/2
-CSET tx_drive_mode=DIRECT
-CSET tx_en_rate_reset_buf=true
-CSET tx_idle_assert_delay=100
-CSET tx_idle_deassert_delay=010
-CSET tx_line_rate=2
-CSET tx_refclk_x0_y0=use_rx_pll
-CSET tx_refclk_x0_y1=use_rx_pll
-CSET tx_refclk_x0_y10=use_rx_pll
-CSET tx_refclk_x0_y11=use_rx_pll
-CSET tx_refclk_x0_y12=use_rx_pll
-CSET tx_refclk_x0_y13=use_rx_pll
-CSET tx_refclk_x0_y14=use_rx_pll
-CSET tx_refclk_x0_y15=use_rx_pll
-CSET tx_refclk_x0_y16=use_rx_pll
-CSET tx_refclk_x0_y17=use_rx_pll
-CSET tx_refclk_x0_y18=use_rx_pll
-CSET tx_refclk_x0_y19=use_rx_pll
-CSET tx_refclk_x0_y2=use_rx_pll
-CSET tx_refclk_x0_y20=use_rx_pll
-CSET tx_refclk_x0_y21=use_rx_pll
-CSET tx_refclk_x0_y22=use_rx_pll
-CSET tx_refclk_x0_y23=use_rx_pll
-CSET tx_refclk_x0_y24=use_rx_pll
-CSET tx_refclk_x0_y25=use_rx_pll
-CSET tx_refclk_x0_y26=use_rx_pll
-CSET tx_refclk_x0_y27=use_rx_pll
-CSET tx_refclk_x0_y28=use_rx_pll
-CSET tx_refclk_x0_y29=use_rx_pll
-CSET tx_refclk_x0_y3=use_rx_pll
-CSET tx_refclk_x0_y30=use_rx_pll
-CSET tx_refclk_x0_y31=use_rx_pll
-CSET tx_refclk_x0_y32=use_rx_pll
-CSET tx_refclk_x0_y33=use_rx_pll
-CSET tx_refclk_x0_y34=use_rx_pll
-CSET tx_refclk_x0_y35=use_rx_pll
-CSET tx_refclk_x0_y4=use_rx_pll
-CSET tx_refclk_x0_y5=use_rx_pll
-CSET tx_refclk_x0_y6=use_rx_pll
-CSET tx_refclk_x0_y7=use_rx_pll
-CSET tx_refclk_x0_y8=use_rx_pll
-CSET tx_refclk_x0_y9=use_rx_pll
-CSET tx_reference_clock=80.00
-CSET tx_tdcc_cfg=11
-CSET txoutclk_source=AUTO
-CSET txpll_sata=00
-CSET txrx_invert=00011
-CSET txusrclk_source=TXOUTCLK
-CSET use_cb=false
-CSET use_cc=false
-CSET use_comma_detect=true
-CSET use_external_rxusrclk=false
-CSET use_external_txusrclk=false
-CSET use_gtx_x0_y0=false
-CSET use_gtx_x0_y1=false
-CSET use_gtx_x0_y10=false
-CSET use_gtx_x0_y11=false
-CSET use_gtx_x0_y12=true
-CSET use_gtx_x0_y13=false
-CSET use_gtx_x0_y14=false
-CSET use_gtx_x0_y15=false
-CSET use_gtx_x0_y16=false
-CSET use_gtx_x0_y17=false
-CSET use_gtx_x0_y18=false
-CSET use_gtx_x0_y19=false
-CSET use_gtx_x0_y2=false
-CSET use_gtx_x0_y20=false
-CSET use_gtx_x0_y21=false
-CSET use_gtx_x0_y22=false
-CSET use_gtx_x0_y23=false
-CSET use_gtx_x0_y24=false
-CSET use_gtx_x0_y25=false
-CSET use_gtx_x0_y26=false
-CSET use_gtx_x0_y27=false
-CSET use_gtx_x0_y28=false
-CSET use_gtx_x0_y29=false
-CSET use_gtx_x0_y3=false
-CSET use_gtx_x0_y30=false
-CSET use_gtx_x0_y31=false
-CSET use_gtx_x0_y32=false
-CSET use_gtx_x0_y33=false
-CSET use_gtx_x0_y34=false
-CSET use_gtx_x0_y35=false
-CSET use_gtx_x0_y4=false
-CSET use_gtx_x0_y5=false
-CSET use_gtx_x0_y6=false
-CSET use_gtx_x0_y7=false
-CSET use_gtx_x0_y8=false
-CSET use_gtx_x0_y9=false
-CSET use_no_rx=false
-CSET use_no_tx=false
-CSET use_port_comfinish=false
-CSET use_port_cominitdet=false
-CSET use_port_comsasdet=false
-CSET use_port_comwakedet=false
-CSET use_port_drp=false
-CSET use_port_enmcommaalign=true
-CSET use_port_enpcommaalign=true
-CSET use_port_gtxtest=false
-CSET use_port_loopback=false
-CSET use_port_phystatus=true
-CSET use_port_plllkdet=true
-CSET use_port_plllkdeten=true
-CSET use_port_pllpowerdown=false
-CSET use_port_refclkpowerdown=false
-CSET use_port_rxbufreset=false
-CSET use_port_rxbufstatus=false
-CSET use_port_rxbyteisaligned=false
-CSET use_port_rxbyterealign=false
-CSET use_port_rxcdrreset=true
-CSET use_port_rxchariscomma=false
-CSET use_port_rxcharisk=true
-CSET use_port_rxcommadet=false
-CSET use_port_rxlossofsync=true
-CSET use_port_rxoversampleerr=false
-CSET use_port_rxpolarity=false
-CSET use_port_rxpowerdown=false
-CSET use_port_rxrate=false
-CSET use_port_rxrecclk=true
-CSET use_port_rxreset=true
-CSET use_port_rxrundisp=false
-CSET use_port_rxslide=false
-CSET use_port_rxstatus=true
-CSET use_port_rxvalid=false
-CSET use_port_txbufstatus=false
-CSET use_port_txbypass8b10b=false
-CSET use_port_txchardispmode=false
-CSET use_port_txchardispval=false
-CSET use_port_txcominit=false
-CSET use_port_txcomsas=false
-CSET use_port_txcomwake=false
-CSET use_port_txdetectrx=false
-CSET use_port_txelecidle=false
-CSET use_port_txenprbstst=false
-CSET use_port_txinhibit=false
-CSET use_port_txkerr=false
-CSET use_port_txoutclk=true
-CSET use_port_txpolarity=false
-CSET use_port_txpowerdown=false
-CSET use_port_txprbsforceerr=false
-CSET use_port_txrate=false
-CSET use_port_txreset=true
-CSET use_port_txrundisp=false
-CSET use_prbs_detector=false
-CSET use_resistor_cal_circuit=false
-CSET use_rx_eq=false
-CSET use_rx_oob=false
-CSET use_rx_oversampling=false
-CSET use_rxbuffer=false
-CSET use_rxpllrefclk=false
-CSET use_rxprbserr_loopback=false
-CSET use_turbo_mode=false
-CSET use_two_cb_sequences=false
-CSET use_two_cc_sequences=false
-CSET use_tx_oversampling=false
-CSET use_txbuffer=false
-CSET use_txpllrefclk=false
-CSET wideband_highpass_mix=000
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2011-04-08T05:24:23Z
-# END Extra information
-GENERATE
-# CRC: dc79b500
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.xise b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.xise
deleted file mode 100644
index 87cce56..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80.xise
+++ /dev/null
@@ -1,143 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="gtxVirtex6FEE80/example_design/mgt_usrclk_source_mmcm.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/example_design/double_reset.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_tx_sync.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_rx_sync.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/example_design/frame_gen.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/example_design/frame_check.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_top.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
-    </file>
-    <file xil_pn:name="gtxvirtex6fee80_gtx.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
-    </file>
-    <file xil_pn:name="gtxvirtex6fee80.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/example_design/gtx_attributes.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/implement/data_vio.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/implement/icon.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-    </file>
-    <file xil_pn:name="gtxVirtex6FEE80/implement/ila.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gtxVirtex6FEE80_top|RTL" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="gtxVirtex6FEE80/example_design/gtxvirtex6fee80_top.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gtxVirtex6FEE80_top" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="gtxVirtex6FEE80" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-12-01T13:54:54" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="DB12E7AF65204F95AA56371BC098BFF3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/doc/ug516_v6_gtxwizard.pdf b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/doc/ug516_v6_gtxwizard.pdf
deleted file mode 100644
index c3ea38c..0000000
Binary files a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/doc/ug516_v6_gtxwizard.pdf and /dev/null differ
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/double_reset.vhd b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/double_reset.vhd
deleted file mode 100644
index 10d5b6b..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/double_reset.vhd
+++ /dev/null
@@ -1,140 +0,0 @@
-------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
---  /   /         Filename : double_reset.vhd
--- /___/   /\     
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Module DOUBLE_RESET
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
-entity DOUBLE_RESET is
-port
-(
-        CLK                :   in    std_logic;
-        PLLLKDET           :   in    std_logic;
-        GTXTEST_DONE       :   out   std_logic;
-        GTXTEST_BIT1       :   out   std_logic
-);
-
-end DOUBLE_RESET;
-
-architecture RTL of DOUBLE_RESET is
---***********************************Parameter Declarations********************
-    constant DLY : time := 1 ns;
-
---*******************************Register Declarations************************
-    signal plllkdet_sync  :   std_logic;
-    signal plllkdet_r     :   std_logic;
-    signal reset_dly_ctr  :   unsigned(10 downto 0);
-    signal reset_dly_done :   std_logic;
-    signal testdone_f     :   std_logic_vector(3 downto 0);
-
-begin
---*******************************Main Body of Code****************************
-
-    process(CLK )
-    begin
-        if(CLK'event and CLK = '1') then
-           plllkdet_r    <= PLLLKDET   after DLY;
-           plllkdet_sync <= plllkdet_r after DLY;
-        end if;
-    end process;
-
-    GTXTEST_BIT1 <= reset_dly_done; 
-    GTXTEST_DONE <= testdone_f(0) when (reset_dly_ctr = b"00000000000") else '0';
-
-    process(CLK )
-    begin
-        if(CLK'event and CLK = '1') then
-          if (plllkdet_sync = '0') then
-            reset_dly_ctr <= b"11111111111"     after DLY;
-          elsif (reset_dly_ctr /= b"00000000000") then
-            reset_dly_ctr <= reset_dly_ctr - 1 after DLY;
-          end if;
-        end if;
-    end process;
-
-    process(CLK )
-    begin
-        if(CLK'event and CLK = '1') then
-          if (plllkdet_sync = '0') then
-             reset_dly_done <= '0'   after DLY;
-          elsif (reset_dly_ctr(10) = '0') then
-             reset_dly_done <= reset_dly_ctr(8)   after DLY;
-          end if;
-        end if;
-    end process;
-
-    process(CLK )
-    begin
-        if(CLK'event and CLK = '1') then
-          if(reset_dly_ctr /= b"00000000000") then
-             testdone_f <= b"1111" after DLY;
-          else
-             testdone_f <= '0' & testdone_f(3 downto 1) after DLY;      
-          end if;
-        end if;
-    end process;
-    
-
-end RTL;
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/frame_check.vhd b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/frame_check.vhd
deleted file mode 100644
index 5b4a18c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/frame_check.vhd
+++ /dev/null
@@ -1,702 +0,0 @@
--------------------------------------------------------------------------------
---   ____  ____ 
---  /   /\/   / 
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard  
---  /   /         Filename : frame_check.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\ 
---
---
--- Module FRAME_CHECK
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard  
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-use std.textio.all;
-use ieee.std_logic_textio.all;
-use ieee.std_logic_misc.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
---***********************************Entity Declaration************************
-
-entity FRAME_CHECK is
-generic
-(
-    RX_DATA_WIDTH            : integer := 16;
-    RXCTRL_WIDTH             : integer := 2;
-    USE_COMMA                : integer := 1;
-    NONE_MSB_FIRST_DEC       : integer := 0;
-    COMMA_DOUBLE_DEC         : integer := 0;
-    CHANBOND_SEQ_LEN         : integer := 1;
-    WORDS_IN_BRAM            : integer := 256;
-    CONFIG_INDEPENDENT_LANES : integer := 0;
-    START_OF_PACKET_CHAR     : std_logic_vector(15 downto 0) ;
-    COMMA_DOUBLE_CHAR        : std_logic_vector(15 downto 0) := x"f628";
-    MEM_00       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_01       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_02       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_03       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_04       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_05       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_06       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_07       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_08       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_09       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_10       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_11       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_12       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_13       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_14       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_15       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_16       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_17       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_18       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_19       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_20       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_21       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_22       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_23       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_24       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_25       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_26       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_27       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_28       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_29       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_30       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_31       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_32       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_33       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_34       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_35       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_36       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_37       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_38       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_39       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_00      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_01      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_02      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_03      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_04      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_05      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_06      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_07      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000"
-);
-port
-(
-    -- User Interface
-    RX_DATA                  : in  std_logic_vector((RX_DATA_WIDTH-1) downto 0); 
-    RXCTRL_IN                : in  std_logic_vector((RXCTRL_WIDTH-1) downto 0); 
-  
-    RX_ENMCOMMA_ALIGN        : out std_logic;
-    RX_ENPCOMMA_ALIGN        : out std_logic;
-    RX_ENCHAN_SYNC           : out std_logic; 
-    RX_CHANBOND_SEQ          : in  std_logic; 
-
-    -- Control Interface
-    INC_IN                   : in std_logic; 
-    INC_OUT                  : out std_logic; 
-    PATTERN_MATCH_N          : out std_logic;
-    RESET_ON_ERROR           : in std_logic; 
-      
-    -- Error Monitoring
-    ERROR_COUNT              : out std_logic_vector(7 downto 0);
-    
-    -- Track Data
-    TRACK_DATA               : out std_logic;
-   
-    -- System Interface
-    USER_CLK                 : in std_logic;       
-    SYSTEM_RESET             : in std_logic
-  
-);
-
-
-end FRAME_CHECK;
-
-
-architecture RTL of FRAME_CHECK is
-
-
---***********************************Parameter Declarations********************
-
-    constant DLY : time := 1 ns;
-
---***************************Internal Register Declarations********************
-
-    signal  begin_r                     :   std_logic;
-    signal  data_error_detected_r       :   std_logic;
-    signal  error_count_r               :   unsigned(8 downto 0);
-    signal  error_detected_r            :   std_logic;
-    signal  read_counter_i              :   unsigned(8 downto 0);    
-    signal  rx_chanbond_seq_r           :   std_logic;
-    signal  rx_chanbond_seq_r2          :   std_logic;
-    signal  rx_chanbond_seq_r3          :   std_logic;
-    signal  rx_data_r                   :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r2                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r3                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r4                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r5                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r6                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r7                  :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_r_track             :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rxctrl_r                    :   std_logic_vector((RXCTRL_WIDTH-1) downto 0);
-    signal  rxctrl_r2                   :   std_logic_vector((RXCTRL_WIDTH-1) downto 0);
-    signal  rxctrl_r3                   :   std_logic_vector((RXCTRL_WIDTH-1) downto 0);
-    signal  rxctrl_or                   :   std_logic;
-    signal  start_of_packet_detected_r  :   std_logic;    
-    signal  track_data_r                :   std_logic;
-    signal  track_data_r2               :   std_logic;
-    signal  track_data_r3               :   std_logic;
-    signal  track_data_r4               :   std_logic;
-    signal  sel                         :   std_logic_vector(1 downto 0);
-    signal  bram_data_r                 :   std_logic_vector(31 downto 0);
-         
- 
---*********************************Wire Declarations***************************
-   
-    signal  bram_data_i                 :   std_logic_vector(31 downto 0);
-
-    signal  chanbondseq_in_data         :   std_logic;
-    signal  error_detected_c            :   std_logic;
-    signal  input_to_chanbond_data_i    :   std_logic;
-    signal  input_to_chanbond_reg_i     :   std_logic;
-    signal  next_begin_c                :   std_logic;
-    signal  next_data_error_detected_c  :   std_logic;
-    signal  next_track_data_c           :   std_logic;
-    signal  start_of_packet_detected_c  :   std_logic;
-    signal  rx_chanbond_reg             :   std_logic_vector((CHANBOND_SEQ_LEN-1) downto 0);
-    signal  rx_chanbond_reg_bitwise_or_i:   std_logic;
-    signal  rx_data_aligned             :   std_logic_vector((RX_DATA_WIDTH-1) downto 0);
-    signal  rx_data_has_start_char_c    :   std_logic;
-    signal  rx_data_matches_bram_c      :   std_logic;
-    signal  tied_to_ground_i            :   std_logic;
-    signal  tied_to_ground_vec_i        :   std_logic_vector(31 downto 0);
-    signal  tied_to_vcc_i               :   std_logic;
-
-
---*********************************Main Body of Code***************************
-begin
-
-    --_______________________  Static signal Assigments _______________________   
-
-    tied_to_ground_i        <= '0';
-    tied_to_ground_vec_i    <= (others=>'0');
-    tied_to_vcc_i           <= '1';
-
-    --______________________ Register RXDATA once to ease timing ______________   
-
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            rx_data_r <= RX_DATA after DLY;
-        end if;
-    end process;
-
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            rxctrl_r <= RXCTRL_IN after DLY;
-        end if;
-    end process;
-    --________________________________ State machine __________________________    
-    
-    
-    -- State registers
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(RESET_ON_ERROR ='1' or SYSTEM_RESET = '1' ) then
-                begin_r                <=  '1' after DLY;
-                track_data_r           <=  '0' after DLY;
-                data_error_detected_r  <=  '0' after DLY;
-            else
-                begin_r                <=  next_begin_c after DLY;
-                track_data_r           <=  next_track_data_c after DLY;
-                data_error_detected_r  <=  next_data_error_detected_c after DLY;
-            end if;
-        end if;
-    end process;
-
-    -- Next state logic
-    next_begin_c               <=   (begin_r and not start_of_packet_detected_r) or data_error_detected_r ;
-
-    next_track_data_c          <=   (begin_r and start_of_packet_detected_r) or (track_data_r and not error_detected_r);
-                                      
-    next_data_error_detected_c <=   (track_data_r and error_detected_r);                               
-          
-    start_of_packet_detected_c <=   INC_IN when (CONFIG_INDEPENDENT_LANES=0) else rx_data_has_start_char_c;
-
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        start_of_packet_detected_r    <=   start_of_packet_detected_c after DLY;
-    end if;    
-    end process;
-    
-    -- Registering for timing
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        track_data_r2    <=   track_data_r after DLY;
-    end if;    
-    end process;
-
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        track_data_r3    <=   track_data_r2 after DLY;
-    end if;    
-    end process;
-
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        track_data_r4    <=   track_data_r3 after DLY;
-    end if;    
-    end process;
-
-    --______________________________ Capture incoming data ____________________ 
-
-
-
-datapath_width_32_40_16_or_20: if ((RX_DATA_WIDTH=16) or (RX_DATA_WIDTH=20) or (RX_DATA_WIDTH=32) or (RX_DATA_WIDTH=40)) generate
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(SYSTEM_RESET = '1') then 
-                rx_data_r2      <=  (others => '0') after DLY;
-                rx_data_r4      <=  (others => '0') after DLY;
-                rx_data_r5      <=  (others => '0') after DLY;
-                rx_data_r6      <=  (others => '0') after DLY;
-                rx_data_r7      <=  (others => '0') after DLY;
-                rx_data_r_track <=  (others => '0') after DLY;
-            else
-                rx_data_r2      <=  rx_data_r after DLY;
-                rx_data_r4      <=  rx_data_r3 after DLY;
-                rx_data_r5      <=  rx_data_r4 after DLY;
-                rx_data_r6      <=  rx_data_r5 after DLY;
-                rx_data_r7      <=  rx_data_r6 after DLY;
-                rx_data_r_track <=  rx_data_r7 after DLY;
-            end if;
-        end if;    
-    end process;
-
-    rx_data_aligned <= rx_data_r3;
-
-    --___________________________ Code for Channel bonding ____________________    
-    -- code to prevent checking of clock correction sequences for the start of packet char
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            rx_chanbond_seq_r    <=  RX_CHANBOND_SEQ after DLY;
-            rx_chanbond_seq_r2   <=  rx_chanbond_seq_r after DLY;
-            rx_chanbond_seq_r3   <=  rx_chanbond_seq_r2 after DLY;
-        end if;    
-    end process;
-
-    input_to_chanbond_reg_i  <= rx_chanbond_seq_r2;
-    input_to_chanbond_data_i <= tied_to_ground_i;
-end generate datapath_width_32_40_16_or_20;
-
-datapath_width_8_or_10: if ((RX_DATA_WIDTH=8) or (RX_DATA_WIDTH=10)) generate
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(SYSTEM_RESET = '1') then 
-                rx_data_r2      <=  (others => '0') after DLY;
-                rx_data_r3      <=  (others => '0') after DLY;
-                rx_data_r4      <=  (others => '0') after DLY;
-                rx_data_r5      <=  (others => '0') after DLY;
-                rx_data_r_track <=  (others => '0') after DLY;
-            else
-                rx_data_r2      <=  rx_data_r after DLY;
-                rx_data_r3      <=  rx_data_r2 after DLY;
-                rx_data_r4      <=  rx_data_r3 after DLY;
-                rx_data_r5      <=  rx_data_r4 after DLY;
-                rx_data_r_track <=  rx_data_r5 after DLY;
-            end if;
-        end if;    
-    end process;
-    
-    rx_data_aligned <= RX_DATA;
-    input_to_chanbond_reg_i  <= RX_CHANBOND_SEQ;
-    input_to_chanbond_data_i <= RX_CHANBOND_SEQ;
-end generate datapath_width_8_or_10;
-
-
-
-   
-
-
-
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(SYSTEM_RESET = '1') then
-              rxctrl_r2      <=  (others => '0') after DLY;
-              rxctrl_r3      <=  (others => '0') after DLY;
-            else
-              rxctrl_r2      <=  rxctrl_r after DLY;
-              rxctrl_r3      <=  rxctrl_r2 after DLY;
-            end if;
-        end if;
-    end process;
-
-    --___________________________ Code for Channel bonding ____________________    
-    -- code to prevent checking of clock correction sequences for the start of packet char
-    register_chan_seq: for i in 0 to (CHANBOND_SEQ_LEN-1) generate
-        case_i_equal_to_0: if (i=0) generate 
-            rx_chanbond_reg_0 : FD port map (Q => rx_chanbond_reg(i),D => input_to_chanbond_reg_i,C => USER_CLK);
-        end generate case_i_equal_to_0;
-        case_i_greater_than_0: if (i>0) generate 
-            rx_chanbond_reg_i :FD port map (Q => rx_chanbond_reg(i),D => rx_chanbond_reg(i-1),C => USER_CLK);
-        end generate case_i_greater_than_0;
-    end generate register_chan_seq;
-    
-    chanbondseq_in_data <= input_to_chanbond_data_i or rx_chanbond_reg_bitwise_or_i;
-
-    process(rx_chanbond_reg)
-    variable rx_chanbond_var : std_logic;
-    variable i               : std_logic;
-    begin
-        rx_chanbond_var := '0';
-        bit_wise_or : for  i in 0 to (CHANBOND_SEQ_LEN-1) loop
-            rx_chanbond_var :=  rx_chanbond_var or rx_chanbond_reg(i);
-        end loop;
-        rx_chanbond_reg_bitwise_or_i <= rx_chanbond_var;
-    end process;
-
-    process(RXCTRL_IN)
-    variable or_rxctrl_var : std_logic;
-    variable i             : std_logic;
-    begin
-        or_rxctrl_var := '0';
-        bit_wise_rxctrl_or : for  i in 0 to (RXCTRL_WIDTH-1) loop
-            or_rxctrl_var :=  or_rxctrl_var or RXCTRL_IN(i);
-        end loop;
-        rxctrl_or <= or_rxctrl_var;
-    end process;
-
-
-
-    rx_data_has_start_char_c <= '1' when ((rx_data_aligned(7 downto 0) = START_OF_PACKET_CHAR(7 downto 0)) and (chanbondseq_in_data='0') and (rxctrl_or='1')) else '0';
-
-    --_____________________________ Assign output ports _______________________    
-
-    TRACK_DATA      <=  track_data_r;    
-
-
-    -- Drive the enamcommaalign port of the mgt for alignment
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if(SYSTEM_RESET = '1') then 
-            RX_ENMCOMMA_ALIGN   <= '0' after DLY;
-        else              
-            RX_ENMCOMMA_ALIGN   <= '1' after DLY;
-        end if;
-    end if;    
-    end process;
-
-    -- Drive the enapcommaalign port of the mgt for alignment
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if(SYSTEM_RESET = '1') then  
-            RX_ENPCOMMA_ALIGN   <= '0' after DLY;
-        else              
-            RX_ENPCOMMA_ALIGN   <= '1' after DLY;
-        end if;
-    end if;    
-    end process;
-
-    INC_OUT         <=  start_of_packet_detected_c;   
-
-    PATTERN_MATCH_N <=  data_error_detected_r;
-
-    -- Drive the enchansync port of the mgt for channel bonding
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if(SYSTEM_RESET = '1') then 
-            RX_ENCHAN_SYNC   <= '0' after DLY;
-        else              
-            RX_ENCHAN_SYNC   <= '1' after DLY;
-        end if;
-    end if;    
-    end process;
-    
-    --___________________________ Check incoming data for errors ______________
-         
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-            bram_data_r   <= bram_data_i after DLY;
-    end if;    
-    end process;
-    
-    --An error is detected when data read for the BRAM does not match the incoming data
-use_40bit : if RX_DATA_WIDTH = 40 generate
-    rx_data_matches_bram_c <= '0' when (rx_data_r_track /= (tied_to_ground_vec_i(7 downto 0) & bram_data_r)) else '1';
-end generate use_40bit;
-
-not_40bit : if RX_DATA_WIDTH /= 40 generate
-    rx_data_matches_bram_c <= '0' when (rx_data_r_track /= bram_data_r((RX_DATA_WIDTH-1) downto 0)) else '1';
-end generate not_40bit;
-
-    error_detected_c    <=   track_data_r4 and not rx_data_matches_bram_c;   
-    
-    
-enable_error_check : if USE_COMMA = 1 generate
-    --We register the error_detected signal for use with the error counter logic
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if(not(track_data_r = '1')) then 
-            error_detected_r    <= '0' after DLY;
-        else
-            error_detected_r    <=  error_detected_c after DLY;
-        end if;
-    end if;    
-    end process;
-end generate enable_error_check;
-
-disable_error_check : if USE_COMMA = 0 generate
-    -- Since the comma detect logic has not been enabled, the error counter has been disabled since
-    -- it doesnt make sense to be searching for an align character in the data. To enable the error 
-    -- count again, please see the code above
-    
-       error_detected_r    <= '0';
-
-end generate disable_error_check;
-
-    
-    --We count the total number of errors we detect. By keeping a count we make it less likely that we will miss
-    --errors we did not directly observe. This counter must be reset when it reaches its max value
-    process ( USER_CLK )
-    begin
-    if( USER_CLK'event and USER_CLK = '1') then
-        if(SYSTEM_RESET='1') then
-            error_count_r       <=  (others => '0') after DLY;
-        elsif(error_detected_r = '1') then
-            error_count_r       <=  error_count_r + 1 after DLY;
-        end if;
-    end if;
-    end process;
-        
-            
-    --Here we connect the lower 8 bits of the count (the MSbit is used only to check when the counter reaches
-    --max value) to the module output
-    ERROR_COUNT     <=   std_logic_vector(error_count_r(7 downto 0));
-
-    --____________________________ Counter to read from BRAM __________________________    
-four_byte : if RX_DATA_WIDTH > 20 generate
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1)))  then
-            read_counter_i   <=  (others => '0') after DLY;
-        elsif(((start_of_packet_detected_r and not track_data_r)='1')) then
-            read_counter_i   <=  "000000001" after DLY;
-        else read_counter_i  <=  read_counter_i + 1 after DLY;
-        end if;
-    end if;
-    end process;
-end generate four_byte;
-
-one_or_two_byte : if RX_DATA_WIDTH <= 20 generate
-    process( USER_CLK )
-    begin
-    if(USER_CLK'event and USER_CLK = '1') then
-        if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1))
-        or ((start_of_packet_detected_r and not track_data_r)='1'))  then
-            read_counter_i   <=  (others => '0') after DLY;
-        else read_counter_i  <=  read_counter_i + 1 after DLY;
-        end if;
-    end if;
-    end process;
-end generate one_or_two_byte;
-
-    --________________________________ BRAM Instantiation _____________________________    
-
-    dual_port_block_ram_i  :  RAMB16_S36_S36 
-    generic map
-    (
-        INIT_00          =>  MEM_00,
-        INIT_01          =>  MEM_01,
-        INIT_02          =>  MEM_02,
-        INIT_03          =>  MEM_03,
-        INIT_04          =>  MEM_04,
-        INIT_05          =>  MEM_05,
-        INIT_06          =>  MEM_06,
-        INIT_07          =>  MEM_07,
-        INIT_08          =>  MEM_08,
-        INIT_09          =>  MEM_09,
-        INIT_0A          =>  MEM_0A,
-        INIT_0B          =>  MEM_0B,
-        INIT_0C          =>  MEM_0C,
-        INIT_0D          =>  MEM_0D,
-        INIT_0E          =>  MEM_0E,
-        INIT_0F          =>  MEM_0F,
-        INIT_10          =>  MEM_10,
-        INIT_11          =>  MEM_11,
-        INIT_12          =>  MEM_12,
-        INIT_13          =>  MEM_13,
-        INIT_14          =>  MEM_14,
-        INIT_15          =>  MEM_15,
-        INIT_16          =>  MEM_16,
-        INIT_17          =>  MEM_17,
-        INIT_18          =>  MEM_18,
-        INIT_19          =>  MEM_19,
-        INIT_1A          =>  MEM_1A,
-        INIT_1B          =>  MEM_1B,
-        INIT_1C          =>  MEM_1C,
-        INIT_1D          =>  MEM_1D,
-        INIT_1E          =>  MEM_1E,
-        INIT_1F          =>  MEM_1F,
-        INIT_20          =>  MEM_20,
-        INIT_21          =>  MEM_21,
-        INIT_22          =>  MEM_22,
-        INIT_23          =>  MEM_23,
-        INIT_24          =>  MEM_24,
-        INIT_25          =>  MEM_25,
-        INIT_26          =>  MEM_26,
-        INIT_27          =>  MEM_27,
-        INIT_28          =>  MEM_28,
-        INIT_29          =>  MEM_29,
-        INIT_2A          =>  MEM_2A,
-        INIT_2B          =>  MEM_2B,
-        INIT_2C          =>  MEM_2C,
-        INIT_2D          =>  MEM_2D,
-        INIT_2E          =>  MEM_2E,
-        INIT_2F          =>  MEM_2F,
-        INIT_30          =>  MEM_30,
-        INIT_31          =>  MEM_31,
-        INIT_32          =>  MEM_32,
-        INIT_33          =>  MEM_33,
-        INIT_34          =>  MEM_34,
-        INIT_35          =>  MEM_35,
-        INIT_36          =>  MEM_36,
-        INIT_37          =>  MEM_37,
-        INIT_38          =>  MEM_38,
-        INIT_39          =>  MEM_39,
-        INIT_3A          =>  MEM_3A,
-        INIT_3B          =>  MEM_3B,
-        INIT_3C          =>  MEM_3C,
-        INIT_3D          =>  MEM_3D,
-        INIT_3E          =>  MEM_3E,
-        INIT_3F          =>  MEM_3F,
-        INITP_00         =>  MEMP_00,
-        INITP_01         =>  MEMP_01,
-        INITP_02         =>  MEMP_02,
-        INITP_03         =>  MEMP_03,
-        INITP_04         =>  MEMP_04,
-        INITP_05         =>  MEMP_05,
-        INITP_06         =>  MEMP_06,
-        INITP_07         =>  MEMP_07
-
-    )
-    port map 
-    (
-        ADDRA            =>  std_logic_vector(read_counter_i),
-        DIA              =>  tied_to_ground_vec_i(31 downto 0),
-        DIPA             =>  tied_to_ground_vec_i(3 downto 0),
-        DOA              =>  bram_data_i,
-        DOPA             =>  open, 
-        WEA              =>  tied_to_ground_i,
-        ENA              =>  tied_to_vcc_i,
-        SSRA             =>  tied_to_ground_i, 
-        CLKA             =>  USER_CLK,
-                  
-        ADDRB            =>  tied_to_ground_vec_i(8 downto 0),
-        DIB              =>  tied_to_ground_vec_i(31 downto 0),
-        DIPB             =>  tied_to_ground_vec_i(3 downto 0),
-        DOB              =>  open,  
-        DOPB             =>  open, 
-        WEB              =>  tied_to_ground_i,
-        ENB              =>  tied_to_ground_i,
-        SSRB             =>  tied_to_ground_i,
-        CLKB             =>  tied_to_ground_i       
-    );       
-    
-    
-end RTL;           
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/frame_gen.vhd b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/frame_gen.vhd
deleted file mode 100644
index 2d76452..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/frame_gen.vhd
+++ /dev/null
@@ -1,329 +0,0 @@
--------------------------------------------------------------------------------
---   ____  ____ 
---  /   /\/   / 
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
---  /   /         Filename : frame_gen.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\ 
---
---
--- Module FRAME_GEN
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
---***********************************Entity Declaration************************
-
-entity FRAME_GEN is
-generic
-(
-    WORDS_IN_BRAM : integer    :=   256;
-    MEM_00       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_01       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_02       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_03       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_04       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_05       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_06       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_07       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_08       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_09       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_10       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_11       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_12       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_13       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_14       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_15       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_16       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_17       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_18       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_19       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_20       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_21       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_22       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_23       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_24       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_25       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_26       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_27       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_28       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_29       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_30       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_31       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_32       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_33       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_34       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_35       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_36       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_37       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_38       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_39       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_00      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_01      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_02      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_03      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_04      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_05      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_06      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_07      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000"
-);    
-port
-(
-    -- User Interface
-    TX_DATA             : out   std_logic_vector(39 downto 0);
-    TX_CHARISK          : out   std_logic_vector(3 downto 0); 
-
-    -- System Interface
-    USER_CLK            : in    std_logic;      
-    SYSTEM_RESET        : in    std_logic
-); 
-
-
-end FRAME_GEN;
-
-architecture RTL of FRAME_GEN is
-
---***********************************Parameter Declarations********************
-
-    constant DLY : time := 1 ns;
-
---********************************* Wire Declarations************************** 
-
-    signal  tx_charisk_i            :   std_logic_vector(3 downto 0);
-    signal  tx_data_bram_i          :   std_logic_vector(31 downto 0);
-    signal  tied_to_ground_vec_i    :   std_logic_vector(31 downto 0);
-    signal  tied_to_ground_i        :   std_logic;
-    signal  tied_to_vcc_i           :   std_logic;
-    signal  tied_to_vcc_vec_i       :   std_logic_vector(15 downto 0);
-
---***************************Internal signalister Declarations******************** 
-
-    signal  read_counter_i          :   unsigned(8 downto 0);    
-
-
---*********************************Main Body of Code***************************
-begin
-
-    tied_to_ground_vec_i    <=   (others=>'0');
-    tied_to_ground_i        <=   '0';
-    tied_to_vcc_i           <=   '1';
-            
-    --__________________________ Counter to read from BRAM ____________________    
-    
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if((SYSTEM_RESET='1') or (read_counter_i = (WORDS_IN_BRAM-1)))then
-                read_counter_i <= (others => '0') after DLY;
-            else
-                read_counter_i <= read_counter_i + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-    -- Assign TX_DATA to BRAM output
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(SYSTEM_RESET='1') then
-                TX_DATA      <= (others => '0') after DLY;
-            else
-                TX_DATA      <= (tied_to_ground_vec_i(7 downto 0) & tx_data_bram_i) after DLY; 
-            end if;
-        end if;
-    end process;
-
-    -- Assign TX_CHARISK to BRAM output
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(SYSTEM_RESET='1') then
-                TX_CHARISK    <= (others => '0') after DLY;
-            else
-                TX_CHARISK    <= tx_charisk_i after DLY; 
-            end if;
-        end if;
-    end process;
-
-    --______________________________ BRAM Instantiation _______________________    
-
-    dual_port_block_ram_i  :  RAMB16_S36_S36 
-    generic map
-    (
-        INIT_00          =>  MEM_00,
-        INIT_01          =>  MEM_01,
-        INIT_02          =>  MEM_02,
-        INIT_03          =>  MEM_03,
-        INIT_04          =>  MEM_04,
-        INIT_05          =>  MEM_05,
-        INIT_06          =>  MEM_06,
-        INIT_07          =>  MEM_07,
-        INIT_08          =>  MEM_08,
-        INIT_09          =>  MEM_09,
-        INIT_0A          =>  MEM_0A,
-        INIT_0B          =>  MEM_0B,
-        INIT_0C          =>  MEM_0C,
-        INIT_0D          =>  MEM_0D,
-        INIT_0E          =>  MEM_0E,
-        INIT_0F          =>  MEM_0F,
-        INIT_10          =>  MEM_10,
-        INIT_11          =>  MEM_11,
-        INIT_12          =>  MEM_12,
-        INIT_13          =>  MEM_13,
-        INIT_14          =>  MEM_14,
-        INIT_15          =>  MEM_15,
-        INIT_16          =>  MEM_16,
-        INIT_17          =>  MEM_17,
-        INIT_18          =>  MEM_18,
-        INIT_19          =>  MEM_19,
-        INIT_1A          =>  MEM_1A,
-        INIT_1B          =>  MEM_1B,
-        INIT_1C          =>  MEM_1C,
-        INIT_1D          =>  MEM_1D,
-        INIT_1E          =>  MEM_1E,
-        INIT_1F          =>  MEM_1F,
-        INIT_20          =>  MEM_20,
-        INIT_21          =>  MEM_21,
-        INIT_22          =>  MEM_22,
-        INIT_23          =>  MEM_23,
-        INIT_24          =>  MEM_24,
-        INIT_25          =>  MEM_25,
-        INIT_26          =>  MEM_26,
-        INIT_27          =>  MEM_27,
-        INIT_28          =>  MEM_28,
-        INIT_29          =>  MEM_29,
-        INIT_2A          =>  MEM_2A,
-        INIT_2B          =>  MEM_2B,
-        INIT_2C          =>  MEM_2C,
-        INIT_2D          =>  MEM_2D,
-        INIT_2E          =>  MEM_2E,
-        INIT_2F          =>  MEM_2F,
-        INIT_30          =>  MEM_30,
-        INIT_31          =>  MEM_31,
-        INIT_32          =>  MEM_32,
-        INIT_33          =>  MEM_33,
-        INIT_34          =>  MEM_34,
-        INIT_35          =>  MEM_35,
-        INIT_36          =>  MEM_36,
-        INIT_37          =>  MEM_37,
-        INIT_38          =>  MEM_38,
-        INIT_39          =>  MEM_39,
-        INIT_3A          =>  MEM_3A,
-        INIT_3B          =>  MEM_3B,
-        INIT_3C          =>  MEM_3C,
-        INIT_3D          =>  MEM_3D,
-        INIT_3E          =>  MEM_3E,
-        INIT_3F          =>  MEM_3F,
-        INITP_00         =>  MEMP_00,
-        INITP_01         =>  MEMP_01,
-        INITP_02         =>  MEMP_02,
-        INITP_03         =>  MEMP_03,
-        INITP_04         =>  MEMP_04,
-        INITP_05         =>  MEMP_05,
-        INITP_06         =>  MEMP_06,
-        INITP_07         =>  MEMP_07
-    )
-    port map 
-    (
-        ADDRA            =>  std_logic_vector(read_counter_i),
-        DIA              =>  tied_to_ground_vec_i(31 downto 0),
-        DIPA             =>  tied_to_ground_vec_i(3 downto 0),
-        DOA              =>  tx_data_bram_i,
-        DOPA             =>  tx_charisk_i, 
-        WEA              =>  tied_to_ground_i,
-        ENA              =>  tied_to_vcc_i,
-        SSRA             =>  tied_to_ground_i, 
-        CLKA             =>  USER_CLK,
-                         
-        ADDRB            =>  tied_to_ground_vec_i(8 downto 0),
-        DIB              =>  tied_to_ground_vec_i(31 downto 0),
-        DIPB             =>  tied_to_ground_vec_i(3 downto 0),
-        DOB              =>  open,  
-        DOPB             =>  open, 
-        WEB              =>  tied_to_ground_i,
-        ENB              =>  tied_to_ground_i,
-        SSRB             =>  tied_to_ground_i,
-        CLKB             =>  tied_to_ground_i       
-    );                   
-
-end RTL;
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.sdc b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.sdc
deleted file mode 100644
index 147d520..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.sdc
+++ /dev/null
@@ -1,72 +0,0 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : gtxVirtex6FEE80_top.sdc
-## /___/   /\     
-## \   \  /  \ 
-##  \___\/\___\
-##
-##
-## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-## Device:  xc6vlx130t
-## Package: ff484
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-################################################################################
-
-
- 
-# Buffer Constraints for synthesis
-define_attribute {n:gtx0_txoutclk_i} {syn_noclockbuf} {1};
-
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.ucf b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.ucf
deleted file mode 100644
index 09fb567..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.ucf
+++ /dev/null
@@ -1,96 +0,0 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : gtxVirtex6FEE80_top.ucf
-## /___/   /\     
-## \   \  /  \ 
-##  \___\/\___\
-##
-##
-## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-## Device:  xc6vlx130t
-## Package: ff484
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-################################## Clock Constraints ##########################
-
-NET "q3_clk0_refclk_i" TNM_NET = "q3_clk0_refclk_i";
-TIMESPEC "TS_q3_clk0_refclk_i" = PERIOD "q3_clk0_refclk_i" 12.5;
-
-
-
-# User Clock Constraints
-NET "gtx0_txusrclk2_i" TNM_NET = "gtx0_txusrclk2_i";
-TIMESPEC "TS_gtx0_txusrclk2_i" = PERIOD "gtx0_txusrclk2_i" 5.0;
-
-NET "gtx0_rxusrclk2_i" TNM_NET = "gtx0_rxusrclk2_i";
-TIMESPEC "TS_gtx0_rxusrclk2_i" = PERIOD "gtx0_rxusrclk2_i" 5.0;
-
-
-
-#################### locs for top level ports (ML623 Board) ###################
-
-
-
-####################### GTX reference clock constraints #######################
-NET Q3_CLK0_MGTREFCLK_PAD_N_IN  LOC=L3;
-NET Q3_CLK0_MGTREFCLK_PAD_P_IN  LOC=L4;
-
-
-################################# mgt wrapper constraints #####################
-
-##---------- Set placement for gtx0_gtx_wrapper_i/GTX_DUAL ------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i LOC=GTXE1_X0Y12;
-
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.xcf b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.xcf
deleted file mode 100644
index 24eb6ec..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxVirtex6FEE80_top.xcf
+++ /dev/null
@@ -1,74 +0,0 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : gtxVirtex6FEE80_top.xcf
-## /___/   /\     
-## \   \  /  \ 
-##  \___\/\___\
-##
-##
-## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-## Device:  xc6vlx130t
-## Package: ff484
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-################################################################################
-
-
- 
-# Buffer Constraints for synthesis
-BEGIN MODEL "gtxVirtex6FEE80_top"
-NET "gtx0_txoutclk_i" BUFFER_TYPE = none;
-
-END;
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtx_attributes.ucf b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtx_attributes.ucf
deleted file mode 100644
index c2a09c5..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtx_attributes.ucf
+++ /dev/null
@@ -1,280 +0,0 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : gtx_attributes.ucf
-## /___/   /\      
-## \   \  /  \ 
-##  \___\/\___\
-##
-##
-## GTX ATTRIBUTES 
-## This file contains the attributes for the active GTX transceivers in the
-## design. If you would like to use this file in your design, please make
-## sure that the path to the GTX instance is correct.
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-############################## Active GTX Attributes #######################
- 
-##________________________ Attributes for GTX 0_____________________
- 
-
-##--------------------------TX PLL----------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK_SOURCE                          = "RXPLL";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_OVERSAMPLE_MODE                     = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_COM_CFG                          = 24'h21680a;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_CP_CFG                           = 8'h07;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_FB                        = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_OUT                       = 2;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_REF                       = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL45_FB                      = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_LKDET_CFG                        = 3'b111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK25_DIVIDER                       = 4;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_SATA                             = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_TDCC_CFG                            = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CAS_CLK_EN                         = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i POWER_SAVE                             = 10'b0000110100;
-
-##-----------------------TX Interface-------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_TXUSRCLK                           = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DATA_WIDTH                          = 10;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_USRCLK_CFG                          = 6'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_CTRL                          = "TXPLLREFCLK_DIV1";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_DLY                           = 10'b0000000000;
-
-##------------TX Buffering and Phase Alignment----------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_PMADATA_OPT                         = 1'b1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_TX_CFG                             = 20'h80082;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BUFFER_USE                          = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BYTECLK_CFG                         = 6'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_EN_RATE_RESET_BUF                   = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_XCLK_SEL                            = "TXUSR";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_CTRINC                     = 4'b0100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_LPFINC                     = 4'b0110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_MONSEL                     = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_OVRDSETTING                = 8'b10000000;
-
-##-----------------------TX Gearbox---------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEARBOX_ENDEC                          = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXGEARBOX_USE                          = "FALSE";
-
-##--------------TX Driver and OOB Signalling------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DRIVE_MODE                          = "DIRECT";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_ASSERT_DELAY                   = 3'b101;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_DEASSERT_DELAY                 = 3'b011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_HIZ                   = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_PD                    = "FALSE";
-
-##------------TX Pipe Control for PCI Express/SATA------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COM_BURST_VAL                          = 4'b1111;
-
-##----------------TX Attributes for PCI Express---------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_0                            = 5'b11010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_1                            = 5'b10000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_0                       = 7'b1001110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_1                       = 7'b1001001;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_2                       = 7'b1000101;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_3                       = 7'b1000010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_4                       = 7'b1000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_0                        = 7'b1000110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_1                        = 7'b1000100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_2                        = 7'b1000010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_3                        = 7'b1000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_4                        = 7'b1000000;
-
-##--------------------------RX PLL----------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_OVERSAMPLE_MODE                     = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_COM_CFG                          = 24'h21680a;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_CP_CFG                           = 8'h07;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_FB                        = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_OUT                       = 2;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_REF                       = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL45_FB                      = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_LKDET_CFG                        = 3'b111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_CLK25_DIVIDER                       = 4;
-
-##-----------------------RX Interface-------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_RXUSRCLK                           = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DATA_WIDTH                          = 10;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_CTRL                          = "RXRECCLKPMA_DIV1";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_DLY                           = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXUSRCLK_DLY                           = 16'h0000;
-
-##--------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i AC_CAP_DIS                             = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CDR_PH_ADJ_TIME                        = 5'b10100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i OOBDETECT_THRESHOLD                    = 3'b011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CDR_SCAN                           = 27'h640404C;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RX_CFG                             = 25'h05ce008;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_GND                           = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_VTTRX                         = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_CDR                    = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_FR                    = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_PH                    = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DETECT_RX_CFG                       = 14'h1832;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_CTRL                       = 5'b00000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_OVRD                       = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CM_TRIM                                = 2'b01;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RXSYNC_CFG                         = 7'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CFG                                = 76'h0040000040000000003;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BGTEST_CFG                             = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BIAS_CFG                               = 17'h00000;
-
-##------------RX Decision Feedback Equalizer(DFE)-------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CAL_TIME                           = 5'b01100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CFG                                = 8'b00011011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_DFE                    = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_OFFSET                          = 8'h4C;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_SCANMODE                        = 2'b00;
-
-##-----------------------PRBS Detection-----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPRBSERR_LOOPBACK                     = 1'b0;
-
-##----------------Comma Detection and Alignment---------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i ALIGN_COMMA_WORD                       = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_10B_ENABLE                       = 10'b1111111100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_DOUBLE                           = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_MCOMMA_DETECT                      = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_PCOMMA_DETECT                      = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_VALID_COMMA_ONLY                   = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_10B_VALUE                       = 10'b1010000011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_DETECT                          = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_10B_VALUE                       = 10'b0101111100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_DETECT                          = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DECODE_SEQ_MATCH                    = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_AUTO_WAIT                     = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_MODE                          = "OFF";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SHOW_REALIGN_COMMA                     = "TRUE";
-
-##---------------RX Loss-of-sync State Machine----------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_INVALID_INCR                    = 8;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_THRESHOLD                       = 256;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOSS_OF_SYNC_FSM                    = "TRUE";
-
-##-----------------------RX Gearbox---------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXGEARBOX_USE                          = "FALSE";
-
-##-----------RX Elastic Buffer and Phase alignment------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_BUFFER_USE                          = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_BUF                   = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_MODE_RESET_BUF                   = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_RATE_RESET_BUF                   = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF                = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF2               = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_FIFO_ADDR_MODE                      = "FAST";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_HI_CNT                         = 4'b1000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_LO_CNT                         = 4'b0000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_XCLK_SEL                            = "RXUSR";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_CTRINC                     = 4'b1110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_EDGESET                    = 5'b00010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_LPFINC                     = 4'b1110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_MONSEL                     = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_OVRDSETTING                = 8'b10000000;
-
-##----------------------Clock Correction----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_ADJ_LEN                        = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_DET_LEN                        = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_INSERT_IDLE_FLAG               = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_KEEP_IDLE                      = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MAX_LAT                        = 16;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MIN_LAT                        = 14;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_PRECEDENCE                     = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_REPEAT_WAIT                    = 0;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_1                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_2                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_3                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_4                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_ENABLE                   = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_1                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_2                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_3                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_4                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_ENABLE                   = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_USE                      = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_CORRECT_USE                        = "FALSE";
-
-##----------------------Channel Bonding----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_1_MAX_SKEW                   = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_2_MAX_SKEW                   = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_KEEP_ALIGN                   = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_1                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_2                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_3                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_4                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_ENABLE                 = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_1                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_2                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_3                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_4                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_CFG                    = 5'b00000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_ENABLE                 = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_USE                    = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_LEN                      = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCI_EXPRESS_MODE                       = "FALSE";
-
-##-----------RX Attributes for PCI Express/SATA/SAS----------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MAX_COMSAS                         = 52;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MIN_COMSAS                         = 40;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_BURST_VAL                         = 3'b100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_IDLE_VAL                          = 3'b100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_BURST                         = 11;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_INIT                          = 34;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_WAKE                          = 11;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_BURST                         = 6;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_INIT                          = 19;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_WAKE                          = 6;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_FROM_P2                     = 12'h03c;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_NON_P2                      = 8'h19;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_RATE                        = 8'hff;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_TO_P2                       = 10'h064;
-
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxvirtex6fee80_rx_sync.vhd b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxvirtex6fee80_rx_sync.vhd
deleted file mode 100644
index f3fd3cf..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxvirtex6fee80_rx_sync.vhd
+++ /dev/null
@@ -1,244 +0,0 @@
-------------------------------------------------------------------------------
---   ____  ____ 
---  /   /\/   /
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard 
---  /   /         Filename : gtxvirtex6fee80_rx_sync.vhd
--- /___/   /\     
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Module gtxvirtex6fee80_rx_sync
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
-entity gtxvirtex6fee80_rx_sync is
-port
-(
-    RXENPMAPHASEALIGN    :   out   std_logic;
-    RXPMASETPHASE        :   out   std_logic;
-    RXDLYALIGNDISABLE    :   out   std_logic;
-    RXDLYALIGNOVERRIDE   :   out   std_logic;
-    RXDLYALIGNRESET      :   out   std_logic;
-    SYNC_DONE            :   out   std_logic;
-    USER_CLK             :   in    std_logic;
-    RESET                :   in    std_logic
-);
-
-
-end gtxvirtex6fee80_rx_sync;
-
-architecture RTL of gtxvirtex6fee80_rx_sync is
---***********************************Parameter Declarations********************
-
-    constant DLY : time := 1 ns;
-
---*******************************Register Declarations************************
-
-    signal   begin_r                        :   std_logic;
-    signal   phase_align_r                  :   std_logic;
-    signal   ready_r                        :   std_logic;
-    signal   sync_counter_r                 :   unsigned(5 downto 0);
-    signal   sync_done_count_r              :   unsigned(5 downto 0);
-    signal   align_reset_counter_r          :   unsigned(4 downto 0);
-    signal   wait_after_sync_r              :   std_logic;
-    signal   wait_before_setphase_counter_r :   unsigned(5 downto 0);
-    signal   wait_before_setphase_r         :   std_logic;
-    signal   align_reset_r                  :   std_logic;
-    
---*******************************Wire Declarations****************************
-    
-    signal   count_32_setphase_complete_r   :   std_logic;
-    signal   count_32_wait_complete_r       :   std_logic;
-    signal   count_align_reset_complete_r   :   std_logic;
-    signal   next_phase_align_c             :   std_logic;
-    signal   next_align_reset_c             :   std_logic;
-    signal   next_ready_c                   :   std_logic;
-    signal   next_wait_after_sync_c         :   std_logic;
-    signal   next_wait_before_setphase_c    :   std_logic;
-    signal   sync_32_times_done_r           :   std_logic;
-    
-    attribute max_fanout:string; 
-    attribute max_fanout of ready_r : signal is "2";
-
-begin
---*******************************Main Body of Code****************************
-
-    --________________________________ State machine __________________________    
-    -- This state machine manages the phase alingment procedure of the GTX on the
-    -- receive side. The module is held in reset till the usrclk source is stable
-    -- and RXRESETDONE is asserted. In the case that a MMCM is used to generate 
-    -- rxusrclk, the mmcm_locked signal is used to indicate a stable usrclk source.
-    -- Once RXRESETDONE and mmcm_locked are asserted, the state machine goes 
-    -- into the align_reset_r state where RXDLYALIGNRESET is asserted for 20 cycles. 
-    -- After this, it goes into the wait_before_setphase_r state for 32 cycles. 
-    -- After asserting RXENPMAPHASEALIGN and waiting 32 cycles, it enters the 
-    -- phase_align_r state where RXPMASETPHASE is asserted for 32 clock cycles. 
-    -- After the port is deasserted, the state machine goes into a wait state for
-    -- 32 cycles. This procedure is repeated 32 times.
-    
-    -- State registers
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(RESET='1') then
-                begin_r                 <=  '1' after DLY;
-                align_reset_r           <=  '0' after DLY;
-                wait_before_setphase_r  <=  '0' after DLY;
-                phase_align_r           <=  '0' after DLY;
-                wait_after_sync_r       <=  '0' after DLY;
-                ready_r                 <=  '0' after DLY;
-            else
-                begin_r                 <=  '0' after DLY;
-                align_reset_r           <=  next_align_reset_c after DLY;
-                wait_before_setphase_r  <=  next_wait_before_setphase_c after DLY;
-                phase_align_r           <=  next_phase_align_c after DLY;
-                wait_after_sync_r       <=  next_wait_after_sync_c after DLY;
-                ready_r                 <=  next_ready_c after DLY;
-            end if;
-        end if;
-    end process;
-
-    -- Next state logic
-    next_align_reset_c          <=  begin_r or
-                                    (align_reset_r and  not count_align_reset_complete_r);
-                                 
-    next_wait_before_setphase_c <=  (align_reset_r and count_align_reset_complete_r) or
-                                    (wait_before_setphase_r and not count_32_wait_complete_r);                                
-                                        
-    next_phase_align_c          <=  (wait_before_setphase_r and count_32_wait_complete_r) or
-                                    (phase_align_r and not count_32_setphase_complete_r) or
-                                    (wait_after_sync_r and count_32_wait_complete_r and not sync_32_times_done_r);
-                                        
-    next_wait_after_sync_c      <=  (phase_align_r and count_32_setphase_complete_r) or
-                                    (wait_after_sync_r and not count_32_wait_complete_r);
-
-    next_ready_c                <=  (wait_after_sync_r and count_32_wait_complete_r and sync_32_times_done_r) or
-                                    ready_r;
-
-    --______ Counter for holding RXDLYALIGNRESET for 20 RXUSRCLK2 cycles ______
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (align_reset_r='0') then
-                align_reset_counter_r <= (others=>'0') after DLY;
-            else
-                align_reset_counter_r <= align_reset_counter_r + 1 after DLY;
-            end if;
-        end if ;
-    end process;
-        
-    count_align_reset_complete_r <= align_reset_counter_r(4)
-                                    and align_reset_counter_r(2);
-                                    
-    --_______Counter for waiting 32 clock cycles before RXPMASETPHASE _________
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if ((wait_before_setphase_r='0') and (wait_after_sync_r='0')) then
-                wait_before_setphase_counter_r <= (others=>'0') after DLY;
-            else
-                wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-    count_32_wait_complete_r <= wait_before_setphase_counter_r(5);
-    
-    --_______________ Counter for holding SYNC for SYNC_CYCLES ________________
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (phase_align_r='0') then
-                sync_counter_r <= (others=>'0') after DLY;
-            else
-                sync_counter_r <= sync_counter_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-    count_32_setphase_complete_r <= sync_counter_r(5);
-
-    --__________ Counter for counting number of times sync is done ____________
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (RESET='1') then
-                sync_done_count_r <= (others=>'0') after DLY;
-            elsif((count_32_wait_complete_r ='1') and (phase_align_r = '1')) then
-                sync_done_count_r <= sync_done_count_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-    sync_32_times_done_r <= sync_done_count_r(5);
-
-    --_______________ Assign the phase align ports into the GTX _______________
-
-    RXDLYALIGNRESET      <=  align_reset_r;
-    RXENPMAPHASEALIGN    <=  (not begin_r) and (not align_reset_r);
-    RXPMASETPHASE        <=  phase_align_r;
-    RXDLYALIGNDISABLE    <=  '1';
-    RXDLYALIGNOVERRIDE   <=  '1';
-
-    --_______________________ Assign the sync_done port _______________________
-    
-    SYNC_DONE <= ready_r;
-    
-    
-end RTL;
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxvirtex6fee80_top.vhd b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxvirtex6fee80_top.vhd
deleted file mode 100644
index c99700c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxvirtex6fee80_top.vhd
+++ /dev/null
@@ -1,1373 +0,0 @@
-------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor: Xilinx
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard 
---  /   /         Filename : gtxvirtex6fee80_top.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Module gtxVirtex6FEE80_top
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
---***********************************Entity Declaration************************
-
-entity gtxVirtex6FEE80_top is
-generic
-(
-    EXAMPLE_CONFIG_INDEPENDENT_LANES        : integer   := 1;
-    EXAMPLE_LANE_WITH_START_CHAR            : integer   := 0;    -- specifies lane with unique start frame ch
-    EXAMPLE_WORDS_IN_BRAM                   : integer   := 512;  -- specifies amount of data in BRAM
-    EXAMPLE_SIM_GTXRESET_SPEEDUP            : integer   := 1;    -- simulation setting for GTX SecureIP model
-    EXAMPLE_USE_CHIPSCOPE                   : integer   := 1     -- Set to 1 to use Chipscope to drive resets
-);
-port
-(
-    Q3_CLK0_MGTREFCLK_PAD_N_IN              : in   std_logic;
-    Q3_CLK0_MGTREFCLK_PAD_P_IN              : in   std_logic;
-    GTXTXRESET_IN                           : in   std_logic;
-    GTXRXRESET_IN                           : in   std_logic;
-    TRACK_DATA_OUT                          : out  std_logic;
-    RXN_IN                                  : in   std_logic;
-    RXP_IN                                  : in   std_logic;
-    TXN_OUT                                 : out  std_logic;
-    TXP_OUT                                 : out  std_logic
-    
-);
-
-
-end gtxVirtex6FEE80_top;
-    
-architecture RTL of gtxVirtex6FEE80_top is
-
---**************************Component Declarations*****************************
-
-
-component gtxVirtex6FEE80 
-generic
-(
-    -- Simulation attributes
-    WRAPPER_SIM_GTXRESET_SPEEDUP    : integer   := 0 -- Set to 1 to speed up sim reset
-);
-port
-(
-
-    --_________________________________________________________________________
-    --_________________________________________________________________________
-    --GTX0  (X0_Y12)
-
-      GTX0_DOUBLE_RESET_CLK_IN                : in   std_logic;
-    ----------------------- Receive Ports - 8b10b Decoder ----------------------
-    GTX0_RXCHARISK_OUT                      : out  std_logic;
-    GTX0_RXDISPERR_OUT                      : out  std_logic;
-    GTX0_RXNOTINTABLE_OUT                   : out  std_logic;
-    --------------- Receive Ports - Comma Detection and Alignment --------------
-    GTX0_RXENMCOMMAALIGN_IN                 : in   std_logic;
-    GTX0_RXENPCOMMAALIGN_IN                 : in   std_logic;
-    ------------------- Receive Ports - RX Data Path interface -----------------
-    GTX0_RXDATA_OUT                         : out  std_logic_vector(7 downto 0);
-    GTX0_RXRECCLK_OUT                       : out  std_logic;
-    GTX0_RXRESET_IN                         : in   std_logic;
-    GTX0_RXUSRCLK2_IN                       : in   std_logic;
-    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-    GTX0_RXCDRRESET_IN                      : in   std_logic;
-    GTX0_RXN_IN                             : in   std_logic;
-    GTX0_RXP_IN                             : in   std_logic;
-    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-    GTX0_RXDLYALIGNDISABLE_IN               : in   std_logic;
-    GTX0_RXDLYALIGNMONENB_IN                : in   std_logic;
-    GTX0_RXDLYALIGNMONITOR_OUT              : out  std_logic_vector(7 downto 0);
-    GTX0_RXDLYALIGNOVERRIDE_IN              : in   std_logic;
-    GTX0_RXDLYALIGNRESET_IN                 : in   std_logic;
-    GTX0_RXENPMAPHASEALIGN_IN               : in   std_logic;
-    GTX0_RXPMASETPHASE_IN                   : in   std_logic;
-    GTX0_RXSTATUS_OUT                       : out  std_logic_vector(2 downto 0);
-    --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-    GTX0_RXLOSSOFSYNC_OUT                   : out  std_logic_vector(1 downto 0);
-    ------------------------ Receive Ports - RX PLL Ports ----------------------
-    GTX0_GTXRXRESET_IN                      : in   std_logic;
-    GTX0_MGTREFCLKRX_IN                     : in   std_logic;
-    GTX0_PLLRXRESET_IN                      : in   std_logic;
-    GTX0_RXPLLLKDET_OUT                     : out  std_logic;
-    GTX0_RXRESETDONE_OUT                    : out  std_logic;
-    -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-    GTX0_PHYSTATUS_OUT                      : out  std_logic;
-    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-    GTX0_TXCHARISK_IN                       : in   std_logic;
-    ------------------ Transmit Ports - TX Data Path interface -----------------
-    GTX0_TXDATA_IN                          : in   std_logic_vector(7 downto 0);
-    GTX0_TXOUTCLK_OUT                       : out  std_logic;
-    GTX0_TXRESET_IN                         : in   std_logic;
-    GTX0_TXUSRCLK2_IN                       : in   std_logic;
-    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-    GTX0_TXN_OUT                            : out  std_logic;
-    GTX0_TXP_OUT                            : out  std_logic;
-    -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-    GTX0_TXDLYALIGNDISABLE_IN               : in   std_logic;
-    GTX0_TXDLYALIGNMONENB_IN                : in   std_logic;
-    GTX0_TXDLYALIGNMONITOR_OUT              : out  std_logic_vector(7 downto 0);
-    GTX0_TXDLYALIGNRESET_IN                 : in   std_logic;
-    GTX0_TXENPMAPHASEALIGN_IN               : in   std_logic;
-    GTX0_TXPMASETPHASE_IN                   : in   std_logic;
-    ----------------------- Transmit Ports - TX PLL Ports ----------------------
-    GTX0_GTXTXRESET_IN                      : in   std_logic;
-    GTX0_TXRESETDONE_OUT                    : out  std_logic
-
-
-);
-end component;
-
-component MGT_USRCLK_SOURCE 
-generic
-(
-    FREQUENCY_MODE   : string   := "LOW";    
-    PERFORMANCE_MODE : string   := "MAX_SPEED"    
-);
-port
-(
-    DIV1_OUT                : out std_logic;
-    DIV2_OUT                : out std_logic;
-    DCM_LOCKED_OUT          : out std_logic;
-    CLK_IN                  : in  std_logic;
-    DCM_RESET_IN            : in  std_logic
-
-);
-end component;
-
-component FRAME_GEN 
-generic
-(
-    WORDS_IN_BRAM : integer    :=   256;
-    MEM_00       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_01       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_02       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_03       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_04       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_05       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_06       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_07       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_08       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_09       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_10       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_11       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_12       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_13       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_14       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_15       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_16       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_17       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_18       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_19       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_20       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_21       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_22       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_23       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_24       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_25       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_26       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_27       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_28       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_29       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_30       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_31       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_32       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_33       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_34       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_35       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_36       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_37       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_38       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_39       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_00      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_01      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_02      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_03      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_04      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_05      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_06      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_07      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000"
-);    
-port
-(
-    -- User Interface
-    TX_DATA             : out   std_logic_vector(39 downto 0);
-    TX_CHARISK          : out   std_logic_vector(3 downto 0); 
-
-    -- System Interface
-    USER_CLK            : in    std_logic;
-    SYSTEM_RESET        : in    std_logic
-); 
-end component;
-
-component FRAME_CHECK 
-generic
-(
-    RX_DATA_WIDTH            : integer := 16;
-    RXCTRL_WIDTH             : integer := 2;
-    USE_COMMA                : integer := 1;
-    NONE_MSB_FIRST_DEC       : integer := 0;
-    COMMA_DOUBLE_DEC         : integer := 0;
-    CHANBOND_SEQ_LEN         : integer := 1;
-    WORDS_IN_BRAM            : integer := 256;
-    CONFIG_INDEPENDENT_LANES : integer := 0;
-    START_OF_PACKET_CHAR     : std_logic_vector(15 downto 0) ;
-    COMMA_DOUBLE_CHAR        : std_logic_vector(15 downto 0) := x"f628";
-    MEM_00       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_01       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_02       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_03       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_04       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_05       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_06       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_07       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_08       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_09       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_10       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_11       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_12       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_13       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_14       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_15       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_16       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_17       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_18       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_19       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_20       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_21       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_22       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_23       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_24       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_25       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_26       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_27       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_28       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_29       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_30       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_31       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_32       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_33       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_34       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_35       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_36       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_37       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_38       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_39       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_00      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_01      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_02      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_03      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_04      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_05      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_06      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_07      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000"
-);
-port
-(
-    -- User Interface
-    RX_DATA                  : in  std_logic_vector((RX_DATA_WIDTH-1) downto 0);
- 
-    RXCTRL_IN                : in  std_logic_vector((RXCTRL_WIDTH-1) downto 0);  
-    RX_ENMCOMMA_ALIGN        : out std_logic;
-    RX_ENPCOMMA_ALIGN        : out std_logic;
- 
-    RX_ENCHAN_SYNC           : out std_logic; 
-    RX_CHANBOND_SEQ          : in  std_logic; 
-
-    -- Control Interface
-    INC_IN                   : in std_logic; 
-    INC_OUT                  : out std_logic; 
-    PATTERN_MATCH_N          : out std_logic;
-    RESET_ON_ERROR           : in std_logic; 
-    
-    -- Error Monitoring
-    ERROR_COUNT              : out std_logic_vector(7 downto 0);
-    
-    -- Track Data
-    TRACK_DATA               : out std_logic;
- 
-    -- System Interface
-    USER_CLK                 : in std_logic;
-    SYSTEM_RESET             : in std_logic
-  
-);
-end component;
-
-component MGT_USRCLK_SOURCE_MMCM
-generic
-(
-    MULT                 : real             := 2.0;
-    DIVIDE               : integer          := 2;    
-    CLK_PERIOD           : real             := 6.4;    
-    OUT0_DIVIDE          : real             := 2.0;
-    OUT1_DIVIDE          : integer          := 2;
-    OUT2_DIVIDE          : integer          := 2;
-    OUT3_DIVIDE          : integer          := 2
-);
-port
-(
-    CLKFBOUT                : out std_logic; 
-    CLK0_OUT                : out std_logic;
-    CLK1_OUT                : out std_logic;
-    CLK2_OUT                : out std_logic;
-    CLK3_OUT                : out std_logic;
-    CLK_IN                  : in  std_logic;
-    MMCM_LOCKED_OUT         : out std_logic;
-    MMCM_RESET_IN           : in  std_logic
-);
-end component;
-
-component gtxVirtex6FEE80_tx_sync
-generic
-(
-    -- Simulation attributes
-    SIM_TXPMASETPHASE_SPEEDUP    : integer   := 0 -- Set to 1 to speed up sim reset
-);
-port
-(
-    TXENPMAPHASEALIGN       : out std_logic;
-    TXPMASETPHASE           : out std_logic;
-    TXDLYALIGNDISABLE       : out std_logic;
-    TXDLYALIGNRESET         : out std_logic;
-    SYNC_DONE               : out std_logic;
-    USER_CLK                : in  std_logic;
-    RESET                   : in  std_logic
-);
-end component;
-
-component gtxVirtex6FEE80_rx_sync
-port
-(
-    RXENPMAPHASEALIGN       : out std_logic;
-    RXPMASETPHASE           : out std_logic;
-    RXDLYALIGNDISABLE       : out std_logic;
-    RXDLYALIGNOVERRIDE      : out std_logic;
-    RXDLYALIGNRESET         : out std_logic;
-    SYNC_DONE               : out std_logic;
-    USER_CLK                : in  std_logic;
-    RESET                   : in  std_logic
-);
-end component;
-
-
--- Chipscope modules
-attribute syn_black_box                : boolean;
-attribute syn_noprune                  : boolean;
-
-
-component data_vio
-port
-(
-    control                 : inout std_logic_vector(35 downto 0);
-    clk                     : in    std_logic;
-    async_in                : in    std_logic_vector(31 downto 0);
-    async_out               : out   std_logic_vector(31 downto 0);
-    sync_in                 : in    std_logic_vector(31 downto 0);
-    sync_out                : out   std_logic_vector(31 downto 0)
-);
-end component;
-attribute syn_black_box of data_vio : component is TRUE;
-attribute syn_noprune of data_vio   : component is TRUE;
-
-
-component icon
-port
-(
-    control0                : inout std_logic_vector(35 downto 0);
-    control1                : inout std_logic_vector(35 downto 0);
-    control2                : inout std_logic_vector(35 downto 0);
-    control3                : inout std_logic_vector(35 downto 0)
-);
-end component;
-attribute syn_black_box of icon : component is TRUE;
-attribute syn_noprune of icon   : component is TRUE;
-
-
-component ila
-port
-(
-    control                 : inout std_logic_vector(35 downto 0);
-    clk                     : in    std_logic;
-    trig0                   : in    std_logic_vector(84 downto 0)
-);
-end component;
-
-
-attribute syn_black_box of ila : component is TRUE;
-attribute syn_noprune of ila   : component is TRUE;
-
-
---***********************************Parameter Declarations********************
-
-    constant DLY : time := 1 ns;
- 
-    attribute max_fanout : string; 
-
---************************** Register Declarations ****************************
-
-    signal   gtx0_txresetdone_r              : std_logic;
-    signal   gtx0_txresetdone_r2             : std_logic;
-    signal   gtx0_rxresetdone_i_r            : std_logic;
-    signal   gtx0_rxresetdone_r              : std_logic;
-    signal   gtx0_rxresetdone_r2             : std_logic;
-    signal   gtx0_rxresetdone_r3             : std_logic;
-    attribute max_fanout of gtx0_rxresetdone_i_r : signal is "1";
-    signal   gtx0_rxdata_r                   : std_logic_vector(7 downto 0);
-    signal   gtx0_rxcharisk_r                : std_logic_vector(0 downto 0);    
-
-
---**************************** Wire Declarations ******************************
-    -------------------------- MGT Wrapper Wires ------------------------------
-    --________________________________________________________________________
-    --________________________________________________________________________
-    --GTX0   (X0Y12)
-
-    ----------------------- Receive Ports - 8b10b Decoder ----------------------
-    signal  gtx0_rxcharisk_i                : std_logic;
-    signal  gtx0_rxdisperr_i                : std_logic;
-    signal  gtx0_rxnotintable_i             : std_logic;
-    --------------- Receive Ports - Comma Detection and Alignment --------------
-    signal  gtx0_rxenmcommaalign_i          : std_logic;
-    signal  gtx0_rxenpcommaalign_i          : std_logic;
-    ------------------- Receive Ports - RX Data Path interface -----------------
-    signal  gtx0_rxdata_i                   : std_logic_vector(7 downto 0);
-    signal  gtx0_rxrecclk_i                 : std_logic;
-    signal  gtx0_rxreset_i                  : std_logic;
-    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-    signal  gtx0_rxcdrreset_i               : std_logic;
-    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-    signal  gtx0_rxdlyaligndisable_i        : std_logic;
-    signal  gtx0_rxdlyalignmonenb_i         : std_logic;
-    signal  gtx0_rxdlyalignmonitor_i        : std_logic_vector(7 downto 0);
-    signal  gtx0_rxdlyalignoverride_i       : std_logic;
-    signal  gtx0_rxdlyalignreset_i          : std_logic;
-    signal  gtx0_rxenpmaphasealign_i        : std_logic;
-    signal  gtx0_rxpmasetphase_i            : std_logic;
-    signal  gtx0_rxstatus_i                 : std_logic_vector(2 downto 0);
-    --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-    signal  gtx0_rxlossofsync_i             : std_logic_vector(1 downto 0);
-    ------------------------ Receive Ports - RX PLL Ports ----------------------
-    signal  gtx0_gtxrxreset_i               : std_logic;
-    signal  gtx0_pllrxreset_i               : std_logic;
-    signal  gtx0_rxplllkdet_i               : std_logic;
-    signal  gtx0_rxresetdone_i              : std_logic;
-    -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-    signal  gtx0_phystatus_i                : std_logic;
-    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-    signal  gtx0_txcharisk_i                : std_logic;
-    ------------------ Transmit Ports - TX Data Path interface -----------------
-    signal  gtx0_txdata_i                   : std_logic_vector(7 downto 0);
-    signal  gtx0_txoutclk_i                 : std_logic;
-    signal  gtx0_txreset_i                  : std_logic;
-    -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-    signal  gtx0_txdlyaligndisable_i        : std_logic;
-    signal  gtx0_txdlyalignmonenb_i         : std_logic;
-    signal  gtx0_txdlyalignmonitor_i        : std_logic_vector(7 downto 0);
-    signal  gtx0_txdlyalignreset_i          : std_logic;
-    signal  gtx0_txenpmaphasealign_i        : std_logic;
-    signal  gtx0_txpmasetphase_i            : std_logic;
-    ----------------------- Transmit Ports - TX PLL Ports ----------------------
-    signal  gtx0_gtxtxreset_i               : std_logic;
-    signal  gtx0_txresetdone_i              : std_logic;
-
-
-
-
-    signal  gtx0_tx_system_reset_c          : std_logic;
-    signal  gtx0_rx_system_reset_c          : std_logic;
-    signal  gtx0_double_reset_clk_i         : std_logic;
-    signal  tied_to_ground_i                : std_logic;
-    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
-    signal  tied_to_vcc_i                   : std_logic;
-    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
-    signal  drp_clk_in_i                    : std_logic;
- 
-
-    ----------------------------- User Clocks ---------------------------------
-
-    signal  gtx0_txusrclk2_i                : std_logic;
-    signal  gtx0_rxusrclk2_i                : std_logic;
-    signal  txoutclk_mmcm0_locked_i         : std_logic;
-    signal  txoutclk_mmcm0_reset_i          : std_logic;
-    signal  gtx0_txoutclk_to_mmcm_i         : std_logic;
-
-
-    ----------------------------- Reference Clocks ----------------------------
-    
-    signal    q3_clk0_refclk_i                : std_logic;
-    signal    q3_clk0_refclk_i_bufg           : std_logic;
-
-    ----------------------- Frame check/gen Module Signals --------------------
-    
-    signal    gtx0_matchn_i                   : std_logic;
-    
-    signal    gtx0_txcharisk_float_i          : std_logic_vector(2 downto 0);
-    
-    signal    gtx0_txdata_float_i             : std_logic_vector(31 downto 0);
-    
-    signal    gtx0_track_data_i               : std_logic;
-    signal    gtx0_block_sync_i               : std_logic;
-    signal    gtx0_error_count_i              : std_logic_vector(7 downto 0);
-    signal    gtx0_frame_check_reset_i        : std_logic;
-    signal    gtx0_inc_in_i                   : std_logic;
-    signal    gtx0_inc_out_i                  : std_logic;
-    signal    gtx0_unscrambled_data_i         : std_logic_vector(7 downto 0);
-
-    signal    reset_on_data_error_i           : std_logic;
-    signal    track_data_out_i                : std_logic;
- 
-    
-    ------------------------- Sync Module Signals -----------------------------
-
-    signal    gtx0_rx_sync_done_i             : std_logic;
-    signal    gtx0_reset_rxsync_c             : std_logic;
-
-
-    signal    gtx0_tx_sync_done_i             : std_logic;
-    signal    gtx0_reset_txsync_c             : std_logic;
-
-    ----------------------- Chipscope Signals ---------------------------------
-
-    signal  tx_data_vio_control_i           : std_logic_vector(35 downto 0);
-    signal  rx_data_vio_control_i           : std_logic_vector(35 downto 0);
-    signal  shared_vio_control_i            : std_logic_vector(35 downto 0);
-    signal  ila_control_i                   : std_logic_vector(35 downto 0);
-    signal  tx_data_vio_async_in_i          : std_logic_vector(31 downto 0);
-    signal  tx_data_vio_sync_in_i           : std_logic_vector(31 downto 0);
-    signal  tx_data_vio_async_out_i         : std_logic_vector(31 downto 0);
-    signal  tx_data_vio_sync_out_i          : std_logic_vector(31 downto 0);
-    signal  rx_data_vio_async_in_i          : std_logic_vector(31 downto 0);
-    signal  rx_data_vio_sync_in_i           : std_logic_vector(31 downto 0);
-    signal  rx_data_vio_async_out_i         : std_logic_vector(31 downto 0);
-    signal  rx_data_vio_sync_out_i          : std_logic_vector(31 downto 0);
-    signal  shared_vio_in_i                 : std_logic_vector(31 downto 0);
-    signal  shared_vio_out_i                : std_logic_vector(31 downto 0);
-    signal  ila_in_i                        : std_logic_vector(84 downto 0);
-
-    signal  gtx0_tx_data_vio_async_in_i     : std_logic_vector(31 downto 0);
-    signal  gtx0_tx_data_vio_sync_in_i      : std_logic_vector(31 downto 0);
-    signal  gtx0_tx_data_vio_async_out_i    : std_logic_vector(31 downto 0);
-    signal  gtx0_tx_data_vio_sync_out_i     : std_logic_vector(31 downto 0);
-    signal  gtx0_rx_data_vio_async_in_i     : std_logic_vector(31 downto 0);
-    signal  gtx0_rx_data_vio_sync_in_i      : std_logic_vector(31 downto 0);
-    signal  gtx0_rx_data_vio_async_out_i    : std_logic_vector(31 downto 0);
-    signal  gtx0_rx_data_vio_sync_out_i     : std_logic_vector(31 downto 0);
-    signal  gtx0_ila_in_i                   : std_logic_vector(84 downto 0);
-
-
-    signal    gtxtxreset_i                    : std_logic;
-    signal    gtxrxreset_i                    : std_logic;
-
-    signal    user_tx_reset_i                 : std_logic;
-    signal    user_rx_reset_i                 : std_logic;
-    signal    tx_vio_clk_i                    : std_logic;
-    signal    tx_vio_clk_mux_out_i            : std_logic;
-    signal    rx_vio_ila_clk_i                : std_logic;
-    signal    rx_vio_ila_clk_mux_out_i        : std_logic;
-
-    
---**************************** Main Body of Code *******************************
-begin
-
-    --  Static signal Assigments
-    tied_to_ground_i                             <= '0';
-    tied_to_ground_vec_i                         <= x"0000000000000000";
-    tied_to_vcc_i                                <= '1';
-    tied_to_vcc_vec_i                            <= x"ff";
-
-
-
-    
-  
-
-    -----------------------Dedicated GTX Reference Clock Inputs ---------------
-    -- The dedicated reference clock inputs you selected in the GUI are implemented using
-    -- IBUFDS_GTXE1 instances.
-    --
-    -- In the UCF file for this example design, you will see that each of
-    -- these IBUFDS_GTXE1 instances has been LOCed to a particular set of pins. By LOCing to these
-    -- locations, we tell the tools to use the dedicated input buffers to the GTX reference
-    -- clock network, rather than general purpose IOs. To select other pins, consult the 
-    -- Implementation chapter of UG___, or rerun the wizard.
-    --
-    -- This network is the highest performace (lowest jitter) option for providing clocks
-    -- to the GTX transceivers.
-    
-    q3_clk0_refclk_ibufds_i : IBUFDS_GTXE1
-    port map
-    (
-        O                               =>      q3_clk0_refclk_i,
-        ODIV2                           =>      open,
-        CEB                             =>      tied_to_ground_i,
-        I                               =>      Q3_CLK0_MGTREFCLK_PAD_P_IN,
-        IB                              =>      Q3_CLK0_MGTREFCLK_PAD_N_IN
-    );
-
- 
-
-   q3_clk0_refclk_bufg_i : BUFG
-    port map
-    (
-        I                               =>      q3_clk0_refclk_i,
-        O                               =>      q3_clk0_refclk_i_bufg
-    );
-
-    -----------------------Clock Input to Double Reset Module------------------
-     gtx0_double_reset_clk_i <= q3_clk0_refclk_i_bufg;
-
-
-    ----------------------------------- User Clocks ---------------------------
-    
-    -- The clock resources in this section were added based on userclk source selections on
-    -- the Latency, Buffering, and Clocking page of the GUI. A few notes about user clocks:
-    -- * The userclk and userclk2 for each GTX datapath (TX and RX) must be phase aligned to 
-    --   avoid data errors in the fabric interface whenever the datapath is wider than 10 bits
-    -- * To minimize clock resources, you can share clocks between GTXs. GTXs using the same frequency
-    --   or multiples of the same frequency can be accomadated using MMCMs. Use caution when
-    --   using RXRECCLK as a clock source, however - these clocks can typically only be shared if all
-    --   the channels using the clock are receiving data from TX channels that share a reference clock 
-    --   source with each other.
-
-    txoutclk_mmcm0_reset_i                       <= not gtx0_rxplllkdet_i;
-    txoutclk_mmcm0_i : MGT_USRCLK_SOURCE_MMCM
-    generic map
-    (
-        MULT                            =>      15.0,
-        DIVIDE                          =>      1,
-        CLK_PERIOD                      =>      12.5,
-        OUT0_DIVIDE                     =>      6.0,
-        OUT1_DIVIDE                     =>      1,
-        OUT2_DIVIDE                     =>      1,
-        OUT3_DIVIDE                     =>      1
-    )
-    port map
-    (
-        CLKFBOUT                        =>      open,
-        CLK0_OUT                        =>      gtx0_txusrclk2_i,
-        CLK1_OUT                        =>      open,
-        CLK2_OUT                        =>      open,
-        CLK3_OUT                        =>      open,
-        CLK_IN                          =>      gtx0_txoutclk_i,
-        MMCM_LOCKED_OUT                 =>      txoutclk_mmcm0_locked_i,
-        MMCM_RESET_IN                   =>      txoutclk_mmcm0_reset_i
-    );
-
-
-    rxrecclk_bufr1_i : BUFR
-    generic map
-    (
-        BUFR_DIVIDE                     =>      "BYPASS"
-    )
-    port map
-    (
-        CE                              =>      '1',
-        CLR                             =>      '0',
-        I                               =>      gtx0_rxrecclk_i,
-        O                               =>      gtx0_rxusrclk2_i
-    );
-
-
-
-
-    ----------------------------- The GTX Wrapper -----------------------------
-    
-    -- Use the instantiation template in the example directory to add the GTX wrapper to your design.
-    -- In this example, the wrapper is wired up for basic operation with a frame generator and frame 
-    -- checker. The GTXs will reset, then attempt to align and transmit data. If channel bonding is 
-    -- enabled, bonding should occur after alignment.
-
-
-    gtxVirtex6FEE80_i : gtxVirtex6FEE80
-    generic map
-    (
-        WRAPPER_SIM_GTXRESET_SPEEDUP    =>      EXAMPLE_SIM_GTXRESET_SPEEDUP
-    )
-    port map
-    (
-  
- 
- 
- 
-
-        --_____________________________________________________________________
-        --_____________________________________________________________________
-        --GTX0  (X0Y12)
-        GTX0_DOUBLE_RESET_CLK_IN        =>      gtx0_double_reset_clk_i,
-        ----------------------- Receive Ports - 8b10b Decoder ----------------------
-        GTX0_RXCHARISK_OUT              =>      gtx0_rxcharisk_i,
-        GTX0_RXDISPERR_OUT              =>      gtx0_rxdisperr_i,
-        GTX0_RXNOTINTABLE_OUT           =>      gtx0_rxnotintable_i,
-        --------------- Receive Ports - Comma Detection and Alignment --------------
-        GTX0_RXENMCOMMAALIGN_IN         =>      gtx0_rxenmcommaalign_i,
-        GTX0_RXENPCOMMAALIGN_IN         =>      gtx0_rxenpcommaalign_i,
-        ------------------- Receive Ports - RX Data Path interface -----------------
-        GTX0_RXDATA_OUT                 =>      gtx0_rxdata_i,
-        GTX0_RXRECCLK_OUT               =>      gtx0_rxrecclk_i,
-        GTX0_RXRESET_IN                 =>      gtx0_rxreset_i,
-        GTX0_RXUSRCLK2_IN               =>      gtx0_rxusrclk2_i,
-        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-        GTX0_RXCDRRESET_IN              =>      gtx0_rxcdrreset_i,
-        GTX0_RXN_IN                     =>      RXN_IN,
-        GTX0_RXP_IN                     =>      RXP_IN,
-        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-        GTX0_RXDLYALIGNDISABLE_IN       =>      gtx0_rxdlyaligndisable_i,
-        GTX0_RXDLYALIGNMONENB_IN        =>      gtx0_rxdlyalignmonenb_i,
-        GTX0_RXDLYALIGNMONITOR_OUT      =>      gtx0_rxdlyalignmonitor_i,
-        GTX0_RXDLYALIGNOVERRIDE_IN      =>      gtx0_rxdlyalignoverride_i,
-        GTX0_RXDLYALIGNRESET_IN         =>      gtx0_rxdlyalignreset_i,
-        GTX0_RXENPMAPHASEALIGN_IN       =>      gtx0_rxenpmaphasealign_i,
-        GTX0_RXPMASETPHASE_IN           =>      gtx0_rxpmasetphase_i,
-        GTX0_RXSTATUS_OUT               =>      gtx0_rxstatus_i,
-        --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-        GTX0_RXLOSSOFSYNC_OUT           =>      gtx0_rxlossofsync_i,
-        ------------------------ Receive Ports - RX PLL Ports ----------------------
-        GTX0_GTXRXRESET_IN              =>      gtx0_gtxrxreset_i,
-        GTX0_MGTREFCLKRX_IN             =>      q3_clk0_refclk_i,
-        GTX0_PLLRXRESET_IN              =>      gtx0_pllrxreset_i,
-        GTX0_RXPLLLKDET_OUT             =>      gtx0_rxplllkdet_i,
-        GTX0_RXRESETDONE_OUT            =>      gtx0_rxresetdone_i,
-        -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-        GTX0_PHYSTATUS_OUT              =>      gtx0_phystatus_i,
-        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-        GTX0_TXCHARISK_IN               =>      gtx0_txcharisk_i,
-        ------------------ Transmit Ports - TX Data Path interface -----------------
-        GTX0_TXDATA_IN                  =>      gtx0_txdata_i,
-        GTX0_TXOUTCLK_OUT               =>      gtx0_txoutclk_i,
-        GTX0_TXRESET_IN                 =>      gtx0_txreset_i,
-        GTX0_TXUSRCLK2_IN               =>      gtx0_txusrclk2_i,
-        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-        GTX0_TXN_OUT                    =>      TXN_OUT,
-        GTX0_TXP_OUT                    =>      TXP_OUT,
-        -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-        GTX0_TXDLYALIGNDISABLE_IN       =>      gtx0_txdlyaligndisable_i,
-        GTX0_TXDLYALIGNMONENB_IN        =>      gtx0_txdlyalignmonenb_i,
-        GTX0_TXDLYALIGNMONITOR_OUT      =>      gtx0_txdlyalignmonitor_i,
-        GTX0_TXDLYALIGNRESET_IN         =>      gtx0_txdlyalignreset_i,
-        GTX0_TXENPMAPHASEALIGN_IN       =>      gtx0_txenpmaphasealign_i,
-        GTX0_TXPMASETPHASE_IN           =>      gtx0_txpmasetphase_i,
-        ----------------------- Transmit Ports - TX PLL Ports ----------------------
-        GTX0_GTXTXRESET_IN              =>      gtx0_gtxtxreset_i,
-        GTX0_TXRESETDONE_OUT            =>      gtx0_txresetdone_i
-
-
-    );
-
-    -- Hold the TX in reset till the TX user clocks are stable
-    gtx0_txreset_i <= not txoutclk_mmcm0_locked_i;
-
-    -- Hold the RX in reset till the RX user clocks are stable
-  
-    gtx0_rxreset_i <= not gtx0_rxplllkdet_i;
-
-
-
-    ------------------------------ TXSYNC module ------------------------------
-    -- The TXSYNC module performs phase synchronization for all the active TX datapaths. It
-    -- waits for the user clocks to be stable, then drives the phase align signals on each
-    -- GTX. When phase synchronization is complete, it asserts SYNC_DONE
-    
-    -- Include the TX_SYNC module in your own design to perform phase synchronization if
-    -- your protocol bypasses the TX Buffers
-
-  
-    
-    gtx0_reset_txsync_c  <=  not gtx0_txresetdone_r2;  
-
-    -- SIM_TXPMASETPHASE_SPEEDUP is a simulation only attribute and MUST be set to 0 
-    -- during implementation      
-    gtx0_txsync_i : gtxVirtex6FEE80_tx_sync
-    generic map
-    (
-        SIM_TXPMASETPHASE_SPEEDUP       =>      EXAMPLE_SIM_GTXRESET_SPEEDUP
-    )
-    port map
-    (
-        TXENPMAPHASEALIGN               =>      gtx0_txenpmaphasealign_i,
-        TXPMASETPHASE                   =>      gtx0_txpmasetphase_i,
-        TXDLYALIGNDISABLE               =>      gtx0_txdlyaligndisable_i,
-        TXDLYALIGNRESET                 =>      gtx0_txdlyalignreset_i,
-        SYNC_DONE                       =>      gtx0_tx_sync_done_i,
-        USER_CLK                        =>      gtx0_txusrclk2_i,
-        RESET                           =>      gtx0_reset_txsync_c
-    );
-
-    ---------------------------- RXSYNC modules -------------------------------
-    -- The RXSYNC module performs phase synchronization for all the active RX datapaths. It
-    -- waits for the user clocks to be stable, then drives the RX phase align signals on each
-    -- GTX. When phase synchronization is complete, it asserts SYNC_DONE
-    
-    -- Include one RX_SYNC module per Buffer bypassed RX datapath in your own design. RX_SYNC modules
-    -- can also be shared, but when sharing, make sure to hold the module in reset until all lanes have 
-    -- a stable clock
-    
-  
-    gtx0_rxsync_i : gtxVirtex6FEE80_rx_sync
-    port map
-    (
-        RXENPMAPHASEALIGN               =>      gtx0_rxenpmaphasealign_i,
-        RXPMASETPHASE                   =>      gtx0_rxpmasetphase_i,
-        RXDLYALIGNDISABLE               =>      gtx0_rxdlyaligndisable_i,
-        RXDLYALIGNOVERRIDE              =>      gtx0_rxdlyalignoverride_i,
-        RXDLYALIGNRESET                 =>      gtx0_rxdlyalignreset_i,
-        SYNC_DONE                       =>      gtx0_rx_sync_done_i,
-        USER_CLK                        =>      gtx0_rxusrclk2_i,
-        RESET                           =>      gtx0_reset_rxsync_c
-    );
-    
-    gtx0_reset_rxsync_c       <= '1' when (gtx0_rxresetdone_r3 = '0') else '0';
-    
-
-
-    -------------------------- User Module Resets -----------------------------
-    -- All the User Modules i.e. FRAME_GEN, FRAME_CHECK and the sync modules
-    -- are held in reset till the RESETDONE goes high. 
-    -- The RESETDONE is registered a couple of times on USRCLK2 and connected 
-    -- to the reset of the modules
-    
-    process( gtx0_rxusrclk2_i)
-    begin
-         if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then
-            gtx0_rxresetdone_i_r  <= gtx0_rxresetdone_i   after DLY;
-         end if; 
-    end process; 
-
-    process( gtx0_rxusrclk2_i,gtx0_rxresetdone_i_r)
-    begin
-        if(gtx0_rxresetdone_i_r = '0') then
-            gtx0_rxresetdone_r    <= '0'   after DLY;
-            gtx0_rxresetdone_r2   <= '0'   after DLY;
-        elsif(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then
-            gtx0_rxresetdone_r    <= gtx0_rxresetdone_i_r after DLY;
-            gtx0_rxresetdone_r2   <= gtx0_rxresetdone_r   after DLY;
-        end if;
-    end process;
-
-    process( gtx0_rxusrclk2_i)
-    begin
-         if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then
-            gtx0_rxresetdone_r3  <= gtx0_rxresetdone_r2   after DLY;
-         end if; 
-    end process; 
-
-    process( gtx0_txusrclk2_i,gtx0_txresetdone_i)
-    begin
-        if(gtx0_txresetdone_i = '0') then
-            gtx0_txresetdone_r  <= '0'   after DLY;
-            gtx0_txresetdone_r2 <= '0'   after DLY;
-        elsif(gtx0_txusrclk2_i'event and gtx0_txusrclk2_i = '1') then
-            gtx0_txresetdone_r  <= gtx0_txresetdone_i   after DLY;
-            gtx0_txresetdone_r2 <= gtx0_txresetdone_r   after DLY;
-        end if;
-    end process;
-
-
-    ------------------------------ Frame Generators ---------------------------
-    -- The example design uses Block RAM based frame generators to provide test
-    -- data to the GTXs for transmission. By default the frame generators are 
-    -- loaded with an incrementing data sequence that includes commas/alignment
-    -- characters for alignment. If your protocol uses channel bonding, the 
-    -- frame generator will also be preloaded with a channel bonding sequence.
-    
-    -- You can modify the data transmitted by changing the INIT values of the frame
-    -- generator in this file. Pay careful attention to bit order and the spacing
-    -- of your control and alignment characters.
-
-    gtx0_frame_gen : FRAME_GEN
-    generic map
-    (
-        WORDS_IN_BRAM                   =>      EXAMPLE_WORDS_IN_BRAM,
-        MEM_00                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_01                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_02                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_03                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_04                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_05                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_06                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_07                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_08                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_09                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_0A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_0B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_0C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_0D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_0E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_0F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_10                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_11                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_12                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_13                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_14                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_15                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_16                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_17                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_18                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_19                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_1A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_1B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_1C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_1D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_1E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_1F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_20                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_21                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_22                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_23                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_24                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_25                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_26                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_27                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_28                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_29                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_2A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_2B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_2C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_2D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_2E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_2F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_30                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_31                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_32                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_33                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_34                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_35                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_36                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_37                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_38                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_39                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_3A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_3B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_3C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_3D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_3E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_3F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEMP_00                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_01                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_02                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_03                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_04                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_05                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_06                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_07                  =>  x"0000000000000000000000000000000000000000000000000000000000000000"
-    )
-    port map
-    (
-        -- User Interface
-        TX_DATA(39 downto 8)            =>      gtx0_txdata_float_i,
-        TX_DATA(7 downto 0)             =>      gtx0_txdata_i,
- 
-        TX_CHARISK(3 downto 1)          =>      gtx0_txcharisk_float_i,
-        TX_CHARISK(0)                   =>      gtx0_txcharisk_i,
-        -- System Interface
-        USER_CLK                        =>      gtx0_txusrclk2_i,
-        SYSTEM_RESET                    =>      gtx0_tx_system_reset_c
-    );
-    
-
-
-    ---------------------------------- Frame Checkers -------------------------
-    -- The example design uses Block RAM based frame checkers to verify incoming  
-    -- data. By default the frame generators are loaded with a data sequence that 
-    -- matches the outgoing sequence of the frame generators for the TX ports.
-    
-    -- You can modify the expected data sequence by changing the INIT values of the frame
-    -- checkers in this file. Pay careful attention to bit order and the spacing
-    -- of your control and alignment characters.
-    
-    -- When the frame checker receives data, it attempts to synchronise to the 
-    -- incoming pattern by looking for the first sequence in the pattern. Once it 
-    -- finds the first sequence, it increments through the sequence, and indicates an 
-    -- error whenever the next value received does not match the expected value.
-
-    gtx0_frame_check_reset_i                     <= reset_on_data_error_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else gtx0_matchn_i;
-
-    -- gtx0_frame_check0 is always connected to the lane with the start of char
-    -- and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off
-    gtx0_inc_in_i                                <= '0';
-
-    process(gtx0_rxusrclk2_i)
-    begin 
-       if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then
-         gtx0_rxdata_r <= gtx0_rxdata_i   after DLY;
-       end if;
-    end process;
-
-    process(gtx0_rxusrclk2_i)
-    begin 
-       if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then
-         gtx0_rxcharisk_r(0) <= gtx0_rxcharisk_i   after DLY;
-       end if;
-    end process;
- 
-
- 
- 
-    gtx0_frame_check : FRAME_CHECK
-    generic map
-    (
-        RX_DATA_WIDTH                   =>      8,
-        RXCTRL_WIDTH                    =>      1,
-        USE_COMMA                       =>      1,
-        WORDS_IN_BRAM                   =>      EXAMPLE_WORDS_IN_BRAM,
-        CONFIG_INDEPENDENT_LANES        =>      1,
-        START_OF_PACKET_CHAR            =>      x"02bc",
-        MEM_00                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_01                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_02                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_03                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_04                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_05                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_06                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_07                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_08                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_09                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_0A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_0B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_0C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_0D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_0E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_0F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_10                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_11                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_12                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_13                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_14                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_15                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_16                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_17                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_18                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_19                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_1A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_1B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_1C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_1D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_1E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_1F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_20                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_21                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_22                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_23                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_24                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_25                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_26                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_27                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_28                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_29                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_2A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_2B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_2C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_2D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_2E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_2F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_30                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_31                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_32                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_33                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_34                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_35                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_36                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_37                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_38                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_39                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_3A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_3B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_3C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_3D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_3E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_3F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEMP_00                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_01                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_02                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_03                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_04                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_05                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_06                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_07                  =>  x"0000000000000000000000000000000000000000000000000000000000000000"
-    )
-    port map
-    (
-        -- MGT Interface
-        RX_DATA                         =>      gtx0_rxdata_r,
-        RXCTRL_IN                       =>      gtx0_rxcharisk_r,
-        RX_ENMCOMMA_ALIGN               =>      gtx0_rxenmcommaalign_i,
-        RX_ENPCOMMA_ALIGN               =>      gtx0_rxenpcommaalign_i,
-        RX_ENCHAN_SYNC                  =>      open,
-        RX_CHANBOND_SEQ                 =>      tied_to_ground_i,
-        -- Control Interface
-        INC_IN                          =>      gtx0_inc_in_i,
-        INC_OUT                         =>      gtx0_inc_out_i,
-        PATTERN_MATCH_N                 =>      gtx0_matchn_i,
-        RESET_ON_ERROR                  =>      gtx0_frame_check_reset_i,
-        -- System Interface
-        USER_CLK                        =>      gtx0_rxusrclk2_i,
-        SYSTEM_RESET                    =>      gtx0_rx_system_reset_c,
-        ERROR_COUNT                     =>      gtx0_error_count_i,
-        TRACK_DATA                      =>      gtx0_track_data_i
-    );
-        
-
-
-    TRACK_DATA_OUT                               <= track_data_out_i;
-
-    track_data_out_i                             <= 
-                                gtx0_track_data_i ;
-
-
-
-    ----------------------------- Chipscope Connections -----------------------
-    -- When the example design is run in hardware, it uses chipscope to allow the
-    -- example design and GTX wrapper to be controlled and monitored. The 
-    -- EXAMPLE_USE_CHIPSCOPE parameter allows chipscope to be removed for simulation.
-    
-chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
-    
-    
-    -- Shared VIO for all transievers 
-    shared_vio_i : data_vio
-    port map
-    (
-        control                         =>      shared_vio_control_i,
-        clk                             =>      tied_to_ground_i,
-        async_in                        =>      shared_vio_in_i,
-        async_out                       =>      shared_vio_out_i,
-        sync_in                         =>      tied_to_ground_vec_i(31 downto 0),
-        sync_out                        =>      open
-    );
-    
-    -- ICON for all VIOs 
-    i_icon : icon
-    port map
-    (
-        control0                        =>      shared_vio_control_i,
-        control1                        =>      tx_data_vio_control_i,
-        control2                        =>      rx_data_vio_control_i,
-        control3                        =>      ila_control_i
-    );
-
-    
-    -- TX VIO 
-    tx_data_vio_i : data_vio
-    port map
-    (
-        control                         =>      tx_data_vio_control_i,
-        clk                             =>      gtx0_txusrclk2_i,
-        async_in                        =>      tx_data_vio_async_in_i,
-        async_out                       =>      tx_data_vio_async_out_i,
-        sync_in                         =>      tx_data_vio_sync_in_i,
-        sync_out                        =>      tx_data_vio_sync_out_i
-    );
-    
-    -- RX VIO 
-    rx_data_vio_i : data_vio
-    port map
-    (
-        control                         =>      rx_data_vio_control_i,
-        clk                             =>      gtx0_rxusrclk2_i,
-        async_in                        =>      rx_data_vio_async_in_i,
-        async_out                       =>      rx_data_vio_async_out_i,
-        sync_in                         =>      rx_data_vio_sync_in_i,
-        sync_out                        =>      rx_data_vio_sync_out_i
-    );
-    
-    -- RX ILA
-    ila_i : ila
-    port map
-    (
-        control                         =>      ila_control_i,
-        clk                             =>      gtx0_rxusrclk2_i,
-        trig0                           =>      ila_in_i
-    );
-
-
-
-    -- assign resets for frame_gen modules
-    gtx0_tx_system_reset_c                       <= not gtx0_tx_sync_done_i or user_tx_reset_i;
-    -- assign resets for frame_check modules
-    gtx0_rx_system_reset_c                       <= not gtx0_rx_sync_done_i or user_rx_reset_i;
-
-    gtx0_gtxtxreset_i                            <= gtxtxreset_i or gtxrxreset_i;
-    gtx0_gtxrxreset_i                            <= gtxtxreset_i or gtxrxreset_i;
-
-    -- Shared VIO Outputs
-    gtxtxreset_i                                 <= shared_vio_out_i(31);
-    gtxrxreset_i                                 <= shared_vio_out_i(30);
-    user_tx_reset_i                              <= shared_vio_out_i(29);
-    user_rx_reset_i                              <= shared_vio_out_i(28);
-
-    -- Shared VIO Inputs
-    shared_vio_in_i(31 downto 0)                 <= "00000000000000000000000000000000";
-
-    -- Chipscope connections on GTX 0
-    gtx0_tx_data_vio_async_in_i(31)              <= '0';
-    gtx0_tx_data_vio_async_in_i(30)              <= gtx0_txresetdone_i;
-    gtx0_tx_data_vio_async_in_i(29 downto 22)    <= gtx0_txdlyalignmonitor_i;
-    gtx0_tx_data_vio_async_in_i(21 downto 0)     <= "0000000000000000000000";
-    gtx0_tx_data_vio_sync_in_i(31 downto 0)      <= "00000000000000000000000000000000";
-    gtx0_txdlyalignmonenb_i                      <= tx_data_vio_async_out_i(30);
-    gtx0_rx_data_vio_async_in_i(31)              <= gtx0_rxplllkdet_i;
-    gtx0_rx_data_vio_async_in_i(30)              <= gtx0_rxresetdone_i;
-    gtx0_rx_data_vio_async_in_i(29 downto 22)    <= gtx0_rxdlyalignmonitor_i;
-    gtx0_rx_data_vio_async_in_i(21 downto 0)     <= "0000000000000000000000";
-    gtx0_rx_data_vio_sync_in_i(31 downto 0)      <= "00000000000000000000000000000000";
-    gtx0_pllrxreset_i                            <= rx_data_vio_async_out_i(31);
-    gtx0_rxcdrreset_i                            <= rx_data_vio_async_out_i(30);
-    gtx0_ila_in_i(84)                            <= gtx0_rxcharisk_i;
-    gtx0_ila_in_i(83)                            <= gtx0_rxdisperr_i;
-    gtx0_ila_in_i(82)                            <= gtx0_rxnotintable_i;
-    gtx0_ila_in_i(81 downto 74)                  <= gtx0_rxdata_i;
-    gtx0_ila_in_i(73 downto 71)                  <= gtx0_rxstatus_i;
-    gtx0_ila_in_i(70 downto 69)                  <= gtx0_rxlossofsync_i;
-    gtx0_ila_in_i(68)                            <= gtx0_phystatus_i;
-    gtx0_ila_in_i(67 downto 60)                  <= gtx0_error_count_i;
-    gtx0_ila_in_i(59 downto 0)                   <= "000000000000000000000000000000000000000000000000000000000000";
-
-
-
-    tx_data_vio_async_in_i              <=      gtx0_tx_data_vio_async_in_i;
-
-
-    tx_data_vio_sync_in_i               <=      gtx0_tx_data_vio_sync_in_i;
-
-    rx_data_vio_async_in_i              <=      gtx0_rx_data_vio_async_in_i;
-
-
-    rx_data_vio_sync_in_i               <=      gtx0_rx_data_vio_sync_in_i;
-
-
-    ila_in_i                            <=      gtx0_ila_in_i;
-
-
-end generate chipscope;
-
-
-no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
-
-    -- If Chipscope is not being used, drive GTX reset signal
-    -- from the top level ports
-    gtx0_gtxtxreset_i                            <= GTXTXRESET_IN;
-    gtx0_gtxrxreset_i                            <= GTXRXRESET_IN;
-
-    -- assign resets for frame_gen modules
-    gtx0_tx_system_reset_c                       <= not gtx0_tx_sync_done_i;
-    -- assign resets for frame_check modules
-    gtx0_rx_system_reset_c                       <= not gtx0_rx_sync_done_i;
-
-    gtxtxreset_i                                 <= tied_to_ground_i;
-    gtxrxreset_i                                 <= tied_to_ground_i;
-    user_tx_reset_i                              <= tied_to_ground_i;
-    user_rx_reset_i                              <= tied_to_ground_i;
-    gtx0_txdlyalignmonenb_i                      <= tied_to_ground_i;
-    gtx0_pllrxreset_i                            <= tied_to_ground_i;
-    gtx0_rxcdrreset_i                            <= tied_to_ground_i;
-
-
-
-end generate no_chipscope;
-
-
-end RTL;
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxvirtex6fee80_tx_sync.vhd b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxvirtex6fee80_tx_sync.vhd
deleted file mode 100644
index aa5cab4..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/gtxvirtex6fee80_tx_sync.vhd
+++ /dev/null
@@ -1,226 +0,0 @@
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor: Xilinx
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
---  /   /         Filename : gtxvirtex6fee80_tx_sync.vhd
--- /___/   /\     
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Module gtxvirtex6fee80_tx_sync
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
-entity gtxvirtex6fee80_tx_sync is
-generic
-(
-    SIM_TXPMASETPHASE_SPEEDUP   : integer:=0
-); 
-port
-(
-    TXENPMAPHASEALIGN    :   out    std_logic;
-    TXPMASETPHASE        :   out    std_logic;
-    TXDLYALIGNDISABLE    :   out    std_logic;
-    TXDLYALIGNRESET      :   out    std_logic;
-    SYNC_DONE            :   out    std_logic;
-    USER_CLK             :   in     std_logic;
-    RESET                :   in     std_logic
-);
-
-
-end gtxvirtex6fee80_tx_sync;
-
-architecture RTL of gtxvirtex6fee80_tx_sync is
---***********************************Parameter Declarations********************
-
-    constant DLY : time := 1 ns;
-
---*******************************Register Declarations************************
-
-    signal  begin_r                         :   std_logic;
-    signal  phase_align_r                   :   std_logic;
-    signal  ready_r                         :   std_logic;
-    signal  sync_counter_r                  :   unsigned(15 downto 0);
-    signal  wait_before_setphase_counter_r  :   unsigned(5 downto 0);
-    signal  align_reset_counter_r           :   unsigned(4 downto 0);
-    signal  wait_before_setphase_r          :   std_logic;
-    signal  align_reset_r                   :   std_logic;
-    
---*******************************Wire Declarations****************************
-    
-    signal   count_setphase_complete_r      :   std_logic;
-    signal   count_32_complete_r            :   std_logic;
-    signal   count_align_reset_complete_r   :   std_logic;
-    signal   next_phase_align_c             :   std_logic;
-    signal   next_ready_c                   :   std_logic;
-    signal   next_wait_before_setphase_c    :   std_logic;
-    signal   next_align_reset_c             :   std_logic;
-
-begin
---*******************************Main Body of Code****************************
-
-    --________________________________ State machine __________________________    
-    -- This state machine manages the TX phase alignment procedure of the GTX.
-    -- The module is held in reset till TXRESETDONE is asserted. Once TXRESETDONE 
-    -- is asserted, the state machine goes into the align_reset_r state, asserting
-    -- TXDLYALIGNRESET for 20 TXUSRCLK2 cycles. After this, it goes into the 
-    -- wait_before_setphase_r state for 32 cycles. After asserting TXENPMAPHASEALIGN and 
-    -- waiting 32 cycles, it goes into the phase_align_r state where the last 
-    -- part of the alignment procedure is completed. This involves asserting 
-    -- TXPMASETPHASE for 8192 (TXPLL_DIVSEL_OUT=1), 16384 (TXPLL_DIVSEL_OUT=2), 
-    -- or 32768 (TXPLL_DIVSEL_OUT=4) clock cycles. After completion of the phase 
-    -- alignment procedure, TXDLYALIGNDISABLE is deasserted.
-    
-    -- State registers
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(RESET='1') then
-                begin_r                    <=  '1' after DLY;
-                align_reset_r              <=  '0' after DLY;
-                wait_before_setphase_r     <=  '0' after DLY;
-                phase_align_r              <=  '0' after DLY;
-                ready_r                    <=  '0' after DLY;
-            else
-                begin_r                    <=  '0' after DLY;
-                align_reset_r              <=  next_align_reset_c after DLY;
-                wait_before_setphase_r     <=  next_wait_before_setphase_c after DLY;
-                phase_align_r              <=  next_phase_align_c after DLY;
-                ready_r                    <=  next_ready_c after DLY;
-            end if;
-        end if;
-    end process;
-
-    -- Next state logic
-    next_align_reset_c              <=  begin_r or 
-                                        (align_reset_r and not count_align_reset_complete_r);
-    
-    next_wait_before_setphase_c     <=  (align_reset_r and count_align_reset_complete_r) or 
-                                        (wait_before_setphase_r and not count_32_complete_r);
-                                        
-    next_phase_align_c              <=  (wait_before_setphase_r and count_32_complete_r) or
-                                        (phase_align_r and not count_setphase_complete_r);
-                                        
-    next_ready_c                    <=  (phase_align_r and count_setphase_complete_r) or
-                                        ready_r;
-
-    --______ Counter for holding TXDLYALIGNRESET for 20 TXUSRCLK2 cycles ______
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (align_reset_r='0') then
-                align_reset_counter_r <= (others=>'0') after DLY;
-            else
-                align_reset_counter_r <= align_reset_counter_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-    
-    count_align_reset_complete_r <= align_reset_counter_r(4) 
-                                    and align_reset_counter_r(2);
-
-    --______ Counter for waiting 32 clock cycles before TXPMASETPHASE _________
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (wait_before_setphase_r='0') then
-                wait_before_setphase_counter_r <= (others=>'0') after DLY;
-            else
-                wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-    count_32_complete_r <= wait_before_setphase_counter_r(5);
-
-    --_______________ Counter for holding SYNC for SYNC_CYCLES ________________
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (phase_align_r='0') then
-                sync_counter_r <= (others=>'0') after DLY;
-            else
-                sync_counter_r <= sync_counter_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=1) generate
-    -- 64 cycles of setphase for simulation
-    count_setphase_complete_r <= sync_counter_r(6);
-end generate fast_simulation;
-
-no_fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=0) generate
-    -- 16384 cycles of setphase for output divider of 2
-    count_setphase_complete_r <= sync_counter_r(14);
-end generate no_fast_simulation;
-
-    --_______________ Assign the phase align ports into the GTX _______________
-
-    TXDLYALIGNRESET   <= '0';
-    TXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);
-    TXPMASETPHASE     <= phase_align_r;
-    TXDLYALIGNDISABLE <= '1';
-
-    --_______________________ Assign the sync_done port _______________________
-    
-    SYNC_DONE <= ready_r;
-    
-    
-end RTL;
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/mgt_usrclk_source_mmcm.vhd b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/mgt_usrclk_source_mmcm.vhd
deleted file mode 100644
index 112e87f..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/example_design/mgt_usrclk_source_mmcm.vhd
+++ /dev/null
@@ -1,218 +0,0 @@
-------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   / 
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard 
---  /   /         Filename : mgt_usrclk_source_mmcm.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\ 
---
---
--- Module MGT_USRCLK_SOURCE_MMCM (for use with Virtex-6 GTX Transceivers)
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
---***********************************Entity Declaration*******************************
-entity MGT_USRCLK_SOURCE_MMCM is
-generic
-(
-    MULT                : real              := 2.0;
-    DIVIDE              : integer           := 2;    
-    CLK_PERIOD          : real              := 6.4;    
-    OUT0_DIVIDE         : real              := 2.0;
-    OUT1_DIVIDE         : integer           := 2;
-    OUT2_DIVIDE         : integer           := 2;
-    OUT3_DIVIDE         : integer           := 2
-);
-port
-(
-    CLKFBOUT           : out std_logic; 
-    CLK0_OUT           : out std_logic;
-    CLK1_OUT           : out std_logic;
-    CLK2_OUT           : out std_logic;
-    CLK3_OUT           : out std_logic;
-    CLK_IN             : in  std_logic;
-    MMCM_LOCKED_OUT    : out std_logic;
-    MMCM_RESET_IN      : in  std_logic
-);
-
-
-end MGT_USRCLK_SOURCE_MMCM;
-
-architecture RTL of MGT_USRCLK_SOURCE_MMCM is
---*********************************Wire Declarations**********************************
-
-    signal   tied_to_ground_vec_i :   std_logic_vector(15 downto 0);
-    signal   tied_to_ground_i     :   std_logic;
-    signal   tied_to_vcc_i        :   std_logic;
-    signal   clkout0_i            :   std_logic;
-    signal   clkout1_i            :   std_logic;
-    signal   clkout2_i            :   std_logic;
-    signal   clkout3_i            :   std_logic;
-    signal   clkfbout_i           :   std_logic;
-    signal   clkfbout_buf         :   std_logic;
-
-begin
-
---*********************************** Beginning of Code *******************************
-
-    --  Static signal Assigments    
-    tied_to_ground_i         <= '0';
-    tied_to_ground_vec_i     <= (others=>'0');
-    tied_to_vcc_i            <= '1';
-
-    -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
-    -- for improved jitter performance, and to avoid consuming an additional BUFG
-    mmcm_adv_i  : MMCM_ADV
-    generic map
-    (
-         COMPENSATION     =>  "ZHOLD",
-         CLKFBOUT_MULT_F  =>  MULT,
-         DIVCLK_DIVIDE    =>  DIVIDE,
-         CLKFBOUT_PHASE   =>  0.0,
-         CLKIN1_PERIOD    =>  CLK_PERIOD,
-         CLKIN2_PERIOD    =>  10.0,          -- Not used
-         CLKOUT0_DIVIDE_F =>  OUT0_DIVIDE,
-         CLKOUT0_PHASE    =>  0.0,
-         CLKOUT1_DIVIDE   =>  OUT1_DIVIDE,
-         CLKOUT1_PHASE    =>  0.0,
-         CLKOUT2_DIVIDE   =>  OUT2_DIVIDE,
-         CLKOUT2_PHASE    =>  0.0,
-         CLKOUT3_DIVIDE   =>  OUT3_DIVIDE,
-         CLKOUT3_PHASE    =>  0.0,
-         CLOCK_HOLD       =>  TRUE         
-    )
-    port map
-    (
-         CLKIN1          =>  CLK_IN,
-         CLKIN2          =>  tied_to_ground_i,
-         CLKINSEL        =>  tied_to_vcc_i,
-         CLKFBIN         =>  clkfbout_buf,
-         CLKOUT0         =>  clkout0_i,
-         CLKOUT0B        =>  open,
-         CLKOUT1         =>  clkout1_i,
-         CLKOUT1B        =>  open,
-         CLKOUT2         =>  clkout2_i,
-         CLKOUT2B        =>  open,
-         CLKOUT3         =>  clkout3_i,
-         CLKOUT3B        =>  open,
-         CLKOUT4         =>  open,
-         CLKOUT5         =>  open,
-         CLKOUT6         =>  open,
-         CLKFBOUT        =>  clkfbout_i,
-         CLKFBOUTB       =>  open,
-         CLKFBSTOPPED    =>  open,
-         CLKINSTOPPED    =>  open,
-         DO              =>  open,
-         DRDY            =>  open,
-         DADDR           =>  tied_to_ground_vec_i(6 downto 0),
-         DCLK            =>  tied_to_ground_i,
-         DEN             =>  tied_to_ground_i,
-         DI              =>  tied_to_ground_vec_i(15 downto 0),
-         DWE             =>  tied_to_ground_i,
-         LOCKED          =>  MMCM_LOCKED_OUT,
-         PSCLK           =>  tied_to_ground_i,
-         PSEN            =>  tied_to_ground_i,        
-         PSINCDEC        =>  tied_to_ground_i, 
-         PSDONE          =>  open,         
-         PWRDWN          =>  tied_to_ground_i,
-         RST             =>  MMCM_RESET_IN     
-    );
-    
-    clkfb_bufg_i  :  BUFG   
-    port map
-    (
-        O      =>    clkfbout_buf, 
-        I      =>    clkfbout_i
-    ); 
-    CLKFBOUT   <=    clkfbout_buf;
-    
-    clkout0_bufg_i  :  BUFG   
-    port map
-    (
-        O      =>    CLK0_OUT, 
-        I      =>    clkout0_i
-    ); 
-
-
-    clkout1_bufg_i  :  BUFG   
-    port map
-    (
-        O      =>    CLK1_OUT,
-        I      =>    clkout1_i
-    );
-    
-    
-    clkout2_bufg_i  :  BUFG   
-    port map
-    (
-        O      =>    CLK2_OUT, 
-        I      =>    clkout2_i
-    ); 
-
-
-    clkout3_bufg_i  :  BUFG   
-    port map
-    (
-        O      =>    CLK3_OUT,
-        I      =>    clkout3_i
-    );    
-    
-end RTL;
- 
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/gtxvirtex6fee80.pf b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/gtxvirtex6fee80.pf
deleted file mode 100644
index 77cc061..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/gtxvirtex6fee80.pf
+++ /dev/null
@@ -1,221 +0,0 @@
-description=User generated protocol
-rx_line_rate=2
-use_rx_oversampling=false
-rx_divider=/2
-rx_datapath_width=10
-decoding=8B/10B
-rx_reference_clock=80.00
-tx_line_rate=2
-use_tx_oversampling=false
-tx_divider=/2
-tx_datapath_width=10
-encoding=8B/10B
-tx_reference_clock=80.00
-use_port_rxoversampleerr=false
-use_port_drp=false
-ppm_offset=0_(Synchronous)
-use_port_txbypass8b10b=false
-use_port_txchardispmode=false
-use_port_txchardispval=false
-use_port_txkerr=false
-use_port_txrundisp=false
-use_port_rxchariscomma=false
-use_port_rxcharisk=true
-use_port_rxrundisp=false
-use_txbuffer=false
-use_rxbuffer=false
-txusrclk_source=TXOUTCLK
-use_external_txusrclk=false
-rxusrclk_source=RXRECCLK
-use_external_rxusrclk=false
-use_port_txoutclk=true
-use_port_txreset=true
-use_port_txbufstatus=false
-use_port_rxreset=true
-use_port_rxrecclk=true
-use_port_rxbufstatus=false
-use_port_rxbufreset=false
-use_comma_detect=true
-dec_valid_comma_only=false
-comma_preset=K28.5
-plus_comma=0101111100
-minus_comma=1010000011
-comma_mask=1111111100
-comma_double=false
-comma_alignment=Any_Byte_Boundary
-use_port_enpcommaalign=true
-use_port_enmcommaalign=true
-use_port_rxslide=false
-use_port_rxbyteisaligned=false
-use_port_rxbyterealign=false
-use_port_rxcommadet=false
-preemphasis_level=0000
-driver_swing=1000
-wideband_highpass_mix=000
-enable_dfe=false
-dfe_mode=Fixed_tap_mode
-disable_ac_coupling=true
-rx_termination_voltage=MGTAVTT
-postemphasis_level=00000
-use_port_txpolarity=false
-use_port_txinhibit=false
-use_port_rxpolarity=false
-use_port_rxcdrreset=true
-pci_express_mode=false
-com_burst_val=15
-sata_burst_val=4
-sata_idle_val=4
-trans_time_to_p2=100
-trans_time_from_p2=60
-trans_time_non_p2=25
-use_port_loopback=false
-use_port_rxpowerdown=false
-use_port_rxstatus=true
-use_port_rxvalid=false
-use_port_cominitdet=false
-use_port_comsasdet=false
-use_port_comwakedet=false
-use_port_txcominit=false
-use_port_txcomsas=false
-use_port_txcomwake=false
-use_port_comfinish=false
-use_port_txpowerdown=false
-use_port_txdetectrx=false
-use_port_txelecidle=false
-use_port_phystatus=true
-use_rx_oob=false
-rx_oob_threshold=011
-use_prbs_detector=false
-use_port_txenprbstst=false
-use_port_txprbsforceerr=false
-use_port_rxlossofsync=true
-rxlossofsyncport=true
-errors_to_lose_sync=256
-bytes_to_reduce_error=8
-use_cb=false
-cb_sequence_length=1
-cb_sequence_1_max_skew=1
-use_two_cb_sequences=false
-cb_sequence_2_max_skew=1
-cb_seq_1_1_mask=true
-cb_seq_1_1=00000000
-cb_seq_1_1_k=false
-cb_seq_1_1_disp=false
-cb_seq_1_2_mask=true
-cb_seq_1_2=00000000
-cb_seq_1_2_k=false
-cb_seq_1_2_disp=false
-cb_seq_1_3_mask=true
-cb_seq_1_3=00000000
-cb_seq_1_3_k=false
-cb_seq_1_3_disp=false
-cb_seq_1_4_mask=true
-cb_seq_1_4=00000000
-cb_seq_1_4_k=false
-cb_seq_1_4_disp=false
-cb_seq_2_1_mask=true
-cb_seq_2_1=00000000
-cb_seq_2_1_k=false
-cb_seq_2_1_disp=false
-cb_seq_2_2_mask=true
-cb_seq_2_2=00000000
-cb_seq_2_2_k=false
-cb_seq_2_2_disp=false
-cb_seq_2_3_mask=true
-cb_seq_2_3=00000000
-cb_seq_2_3_k=false
-cb_seq_2_3_disp=false
-cb_seq_2_4_mask=true
-cb_seq_2_4=00000000
-cb_seq_2_4_k=false
-cb_seq_2_4_disp=false
-use_cc=false
-cc_sequence_length=1
-fifo_upper_bounds=16
-fifo_lower_bounds=14
-use_two_cc_sequences=false
-cc_seq_1_1_mask=true
-cc_seq_1_1=00000000
-cc_seq_1_1_k=true
-cc_seq_1_1_disp=false
-cc_seq_1_2_mask=true
-cc_seq_1_2=00000000
-cc_seq_1_2_k=true
-cc_seq_1_2_disp=false
-cc_seq_1_3_mask=true
-cc_seq_1_3=00000000
-cc_seq_1_3_k=true
-cc_seq_1_3_disp=false
-cc_seq_1_4_mask=true
-cc_seq_1_4=00000000
-cc_seq_1_4_k=true
-cc_seq_1_4_disp=false
-cc_seq_2_1_mask=true
-cc_seq_2_1=00000000
-cc_seq_2_1_k=true
-cc_seq_2_1_disp=false
-cc_seq_2_2_mask=true
-cc_seq_2_2=00000000
-cc_seq_2_2_k=true
-cc_seq_2_2_disp=false
-cc_seq_2_3_mask=true
-cc_seq_2_3=00000000
-cc_seq_2_3_k=true
-cc_seq_2_3_disp=false
-cc_seq_2_4_mask=true
-cc_seq_2_4=00000000
-cc_seq_2_4_k=true
-cc_seq_2_4_disp=false
-txoutclk_source=AUTO
-rxrecclk_source=AUTO
-dec_mcomma_detect=false
-dec_pcomma_detect=false
-mcomma_detect=true
-pcomma_detect=true
-use_rx_eq=false
-use_turbo_mode=false
-highpass_pole_location=Use_RXEQPOLE_Port
-use_resistor_cal_circuit=false
-second_order_cdr_loop=false
-oob_clk_divider=0000000
-pll_sata=false
-rx_decode_seq_match=true
-rx_slide_mode=OFF
-termination_ctrl=00000
-termination_imp=50
-termination_ovrd=false
-txrx_invert=00011
-use_port_plllkdet=true
-use_port_plllkdeten=true
-use_port_pllpowerdown=false
-use_port_refclkpowerdown=false
-cdr_ph_adj_time=10100
-rx_en_idle_reset_fr=false
-rx_en_idle_hold_cdr=false
-rx_en_idle_reset_ph=false
-rx_en_idle_hold_dfe=true
-en_idle_reset_buf=false
-rx_idle_hi_cnt=1000
-rx_idle_lo_cnt=0000
-rxrundisp_indicates_cc=false
-max_cb_level=7
-cc_keep_one_idle=false
-clk_cor_precedence=CC
-clk_cor_repeat_wait=0
-txpll_sata=00
-tx_en_rate_reset_buf=true
-tx_drive_mode=DIRECT
-show_realign_comma=true
-rx_en_mode_reset_buf=true
-rx_en_rate_reset_buf=true
-rx_en_realign_reset_buf=false
-rx_fifo_addr_mode=FULL
-chan_bond_seq_2_cfg=00000
-sas_max_comsas=52
-sas_min_comsas=40
-trans_time_rate=FF
-chan_bond_keep_align=false
-tx_tdcc_cfg=11
-tx_idle_assert_delay=100
-tx_idle_deassert_delay=010
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/chipscope_project.cpj b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/chipscope_project.cpj
deleted file mode 100644
index 3cbda0f..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/chipscope_project.cpj
+++ /dev/null
@@ -1,3760 +0,0 @@
-#ChipScope Pro Analyzer Project File, Version 3.0
-#Thu Jul 27 15:56:09 IST 2006
-device.1.configFileDir=D:/Xilinx_proj/Panda/Xilinx/FrontEndElectronics/FEE_V2_ADC32board_SODA2/ipcore_dir/gtxVirtex6FEE80/implement/
-device.1.configFilename=gtxVirtex6FEE80_top.bit
-deviceChain.deviceName0=System_ACE
-deviceChain.deviceName1=XC6VLX130T
-deviceChain.iRLength0=8
-deviceChain.iRLength1=10
-deviceChain.name0=MyDevice0
-deviceChain.name1=MyDevice1
-#deviceIds=0a00109302a96093
-focus=
-mdiAreaHeight=0.7984031936127745
-mdiAreaHeightLast=0.7984031936127745
-mdiAspect=141
-mdiCount=5
-mdiDevice0=1
-mdiDevice1=1
-mdiDevice2=1
-mdiDevice3=1
-mdiDevice4=1
-mdiType0=1
-mdiType1=6
-mdiType2=6
-mdiType3=0
-mdiType4=6
-mdiUnit0=3
-mdiUnit1=1
-mdiUnit2=2
-mdiUnit3=3
-mdiUnit4=0
-navigatorHeight=0.17864271457085829
-navigatorHeightLast=0.17864271457085829
-navigatorWidth=0.17904612978889758
-navigatorWidthLast=0.17904612978889758
-serverHost=localhost
-serverPort=50001
-unit.-1.-1.username=
-unit.1.-1.coretype=SYSTEM MONITOR
-unit.1.-1.port.-1.buscount=0
-unit.1.-1.port.-1.channelcount=0
-unit.1.-1.portcount=0
-unit.1.-1.username=
-unit.1.0.6.HEIGHT6=0.3133998
-unit.1.0.6.WIDTH6=0.29241645
-unit.1.0.6.X6=0.0032133677
-unit.1.0.6.Y6=0.0
-unit.1.0.coretype=VIO
-unit.1.0.portcount=3
-unit.1.0.username=MYVIO0
-unit.1.0.port.-1.buscount=0
-unit.1.0.port.-1.channelcount=32
-unit.1.0.port.-1.s.0.alias=unused0
-unit.1.0.port.-1.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.0.name=AsyncIn[0]
-unit.1.0.port.-1.s.0.orderindex=-1
-unit.1.0.port.-1.s.0.visible=1
-unit.1.0.port.-1.s.0.display=14
-unit.1.0.port.-1.s.0.persistance=0
-unit.1.0.port.-1.s.0.value=0
-unit.1.0.port.-1.s.1.alias=unused1
-unit.1.0.port.-1.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.1.name=AsyncIn[1]
-unit.1.0.port.-1.s.1.orderindex=-1
-unit.1.0.port.-1.s.1.visible=1
-unit.1.0.port.-1.s.1.display=14
-unit.1.0.port.-1.s.1.persistance=0
-unit.1.0.port.-1.s.1.value=0
-unit.1.0.port.-1.s.2.alias=unused2
-unit.1.0.port.-1.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.2.name=AsyncIn[2]
-unit.1.0.port.-1.s.2.orderindex=-1
-unit.1.0.port.-1.s.2.visible=1
-unit.1.0.port.-1.s.2.display=14
-unit.1.0.port.-1.s.2.persistance=0
-unit.1.0.port.-1.s.2.value=0
-unit.1.0.port.-1.s.3.alias=unused3
-unit.1.0.port.-1.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.3.name=AsyncIn[3]
-unit.1.0.port.-1.s.3.orderindex=-1
-unit.1.0.port.-1.s.3.visible=1
-unit.1.0.port.-1.s.3.display=14
-unit.1.0.port.-1.s.3.persistance=0
-unit.1.0.port.-1.s.3.value=0
-unit.1.0.port.-1.s.4.alias=unused4
-unit.1.0.port.-1.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.4.name=AsyncIn[4]
-unit.1.0.port.-1.s.4.orderindex=-1
-unit.1.0.port.-1.s.4.visible=1
-unit.1.0.port.-1.s.4.display=14
-unit.1.0.port.-1.s.4.persistance=0
-unit.1.0.port.-1.s.4.value=0
-unit.1.0.port.-1.s.5.alias=unused5
-unit.1.0.port.-1.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.5.name=AsyncIn[5]
-unit.1.0.port.-1.s.5.orderindex=-1
-unit.1.0.port.-1.s.5.visible=1
-unit.1.0.port.-1.s.5.display=14
-unit.1.0.port.-1.s.5.persistance=0
-unit.1.0.port.-1.s.5.value=0
-unit.1.0.port.-1.s.6.alias=unused6
-unit.1.0.port.-1.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.6.name=AsyncIn[6]
-unit.1.0.port.-1.s.6.orderindex=-1
-unit.1.0.port.-1.s.6.visible=1
-unit.1.0.port.-1.s.6.display=14
-unit.1.0.port.-1.s.6.persistance=0
-unit.1.0.port.-1.s.6.value=0
-unit.1.0.port.-1.s.7.alias=unused7
-unit.1.0.port.-1.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.7.name=AsyncIn[7]
-unit.1.0.port.-1.s.7.orderindex=-1
-unit.1.0.port.-1.s.7.visible=1
-unit.1.0.port.-1.s.7.display=14
-unit.1.0.port.-1.s.7.persistance=0
-unit.1.0.port.-1.s.7.value=0
-unit.1.0.port.-1.s.8.alias=unused8
-unit.1.0.port.-1.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.8.name=AsyncIn[8]
-unit.1.0.port.-1.s.8.orderindex=-1
-unit.1.0.port.-1.s.8.visible=1
-unit.1.0.port.-1.s.8.display=14
-unit.1.0.port.-1.s.8.persistance=0
-unit.1.0.port.-1.s.8.value=0
-unit.1.0.port.-1.s.9.alias=unused9
-unit.1.0.port.-1.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.9.name=AsyncIn[9]
-unit.1.0.port.-1.s.9.orderindex=-1
-unit.1.0.port.-1.s.9.visible=1
-unit.1.0.port.-1.s.9.display=14
-unit.1.0.port.-1.s.9.persistance=0
-unit.1.0.port.-1.s.9.value=0
-unit.1.0.port.-1.s.10.alias=unused10
-unit.1.0.port.-1.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.10.name=AsyncIn[10]
-unit.1.0.port.-1.s.10.orderindex=-1
-unit.1.0.port.-1.s.10.visible=1
-unit.1.0.port.-1.s.10.display=14
-unit.1.0.port.-1.s.10.persistance=0
-unit.1.0.port.-1.s.10.value=0
-unit.1.0.port.-1.s.11.alias=unused11
-unit.1.0.port.-1.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.11.name=AsyncIn[11]
-unit.1.0.port.-1.s.11.orderindex=-1
-unit.1.0.port.-1.s.11.visible=1
-unit.1.0.port.-1.s.11.display=14
-unit.1.0.port.-1.s.11.persistance=0
-unit.1.0.port.-1.s.11.value=0
-unit.1.0.port.-1.s.12.alias=unused12
-unit.1.0.port.-1.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.12.name=AsyncIn[12]
-unit.1.0.port.-1.s.12.orderindex=-1
-unit.1.0.port.-1.s.12.visible=1
-unit.1.0.port.-1.s.12.display=14
-unit.1.0.port.-1.s.12.persistance=0
-unit.1.0.port.-1.s.12.value=0
-unit.1.0.port.-1.s.13.alias=unused13
-unit.1.0.port.-1.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.13.name=AsyncIn[13]
-unit.1.0.port.-1.s.13.orderindex=-1
-unit.1.0.port.-1.s.13.visible=1
-unit.1.0.port.-1.s.13.display=14
-unit.1.0.port.-1.s.13.persistance=0
-unit.1.0.port.-1.s.13.value=0
-unit.1.0.port.-1.s.14.alias=unused14
-unit.1.0.port.-1.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.14.name=AsyncIn[14]
-unit.1.0.port.-1.s.14.orderindex=-1
-unit.1.0.port.-1.s.14.visible=1
-unit.1.0.port.-1.s.14.display=14
-unit.1.0.port.-1.s.14.persistance=0
-unit.1.0.port.-1.s.14.value=0
-unit.1.0.port.-1.s.15.alias=unused15
-unit.1.0.port.-1.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.15.name=AsyncIn[15]
-unit.1.0.port.-1.s.15.orderindex=-1
-unit.1.0.port.-1.s.15.visible=1
-unit.1.0.port.-1.s.15.display=14
-unit.1.0.port.-1.s.15.persistance=0
-unit.1.0.port.-1.s.15.value=0
-unit.1.0.port.-1.s.16.alias=unused16
-unit.1.0.port.-1.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.16.name=AsyncIn[16]
-unit.1.0.port.-1.s.16.orderindex=-1
-unit.1.0.port.-1.s.16.visible=1
-unit.1.0.port.-1.s.16.display=14
-unit.1.0.port.-1.s.16.persistance=0
-unit.1.0.port.-1.s.16.value=0
-unit.1.0.port.-1.s.17.alias=unused17
-unit.1.0.port.-1.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.17.name=AsyncIn[17]
-unit.1.0.port.-1.s.17.orderindex=-1
-unit.1.0.port.-1.s.17.visible=1
-unit.1.0.port.-1.s.17.display=14
-unit.1.0.port.-1.s.17.persistance=0
-unit.1.0.port.-1.s.17.value=0
-unit.1.0.port.-1.s.18.alias=unused18
-unit.1.0.port.-1.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.18.name=AsyncIn[18]
-unit.1.0.port.-1.s.18.orderindex=-1
-unit.1.0.port.-1.s.18.visible=1
-unit.1.0.port.-1.s.18.display=14
-unit.1.0.port.-1.s.18.persistance=0
-unit.1.0.port.-1.s.18.value=0
-unit.1.0.port.-1.s.19.alias=unused19
-unit.1.0.port.-1.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.19.name=AsyncIn[19]
-unit.1.0.port.-1.s.19.orderindex=-1
-unit.1.0.port.-1.s.19.visible=1
-unit.1.0.port.-1.s.19.display=14
-unit.1.0.port.-1.s.19.persistance=0
-unit.1.0.port.-1.s.19.value=0
-unit.1.0.port.-1.s.20.alias=unused20
-unit.1.0.port.-1.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.20.name=AsyncIn[20]
-unit.1.0.port.-1.s.20.orderindex=-1
-unit.1.0.port.-1.s.20.visible=1
-unit.1.0.port.-1.s.20.display=14
-unit.1.0.port.-1.s.20.persistance=0
-unit.1.0.port.-1.s.20.value=0
-unit.1.0.port.-1.s.21.alias=unused21
-unit.1.0.port.-1.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.21.name=AsyncIn[21]
-unit.1.0.port.-1.s.21.orderindex=-1
-unit.1.0.port.-1.s.21.visible=1
-unit.1.0.port.-1.s.21.display=14
-unit.1.0.port.-1.s.21.persistance=0
-unit.1.0.port.-1.s.21.value=0
-unit.1.0.port.-1.s.22.alias=unused22
-unit.1.0.port.-1.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.22.name=AsyncIn[22]
-unit.1.0.port.-1.s.22.orderindex=-1
-unit.1.0.port.-1.s.22.visible=1
-unit.1.0.port.-1.s.22.display=14
-unit.1.0.port.-1.s.22.persistance=0
-unit.1.0.port.-1.s.22.value=0
-unit.1.0.port.-1.s.23.alias=unused23
-unit.1.0.port.-1.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.23.name=AsyncIn[23]
-unit.1.0.port.-1.s.23.orderindex=-1
-unit.1.0.port.-1.s.23.visible=1
-unit.1.0.port.-1.s.23.display=14
-unit.1.0.port.-1.s.23.persistance=0
-unit.1.0.port.-1.s.23.value=0
-unit.1.0.port.-1.s.24.alias=unused24
-unit.1.0.port.-1.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.24.name=AsyncIn[24]
-unit.1.0.port.-1.s.24.orderindex=-1
-unit.1.0.port.-1.s.24.visible=1
-unit.1.0.port.-1.s.24.display=14
-unit.1.0.port.-1.s.24.persistance=0
-unit.1.0.port.-1.s.24.value=0
-unit.1.0.port.-1.s.25.alias=unused25
-unit.1.0.port.-1.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.25.name=AsyncIn[25]
-unit.1.0.port.-1.s.25.orderindex=-1
-unit.1.0.port.-1.s.25.visible=1
-unit.1.0.port.-1.s.25.display=14
-unit.1.0.port.-1.s.25.persistance=0
-unit.1.0.port.-1.s.25.value=0
-unit.1.0.port.-1.s.26.alias=unused26
-unit.1.0.port.-1.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.26.name=AsyncIn[26]
-unit.1.0.port.-1.s.26.orderindex=-1
-unit.1.0.port.-1.s.26.visible=1
-unit.1.0.port.-1.s.26.display=14
-unit.1.0.port.-1.s.26.persistance=0
-unit.1.0.port.-1.s.26.value=0
-unit.1.0.port.-1.s.27.alias=unused27
-unit.1.0.port.-1.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.27.name=AsyncIn[27]
-unit.1.0.port.-1.s.27.orderindex=-1
-unit.1.0.port.-1.s.27.visible=1
-unit.1.0.port.-1.s.27.display=14
-unit.1.0.port.-1.s.27.persistance=0
-unit.1.0.port.-1.s.27.value=0
-unit.1.0.port.-1.s.28.alias=unused28
-unit.1.0.port.-1.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.28.name=AsyncIn[28]
-unit.1.0.port.-1.s.28.orderindex=-1
-unit.1.0.port.-1.s.28.visible=1
-unit.1.0.port.-1.s.28.display=14
-unit.1.0.port.-1.s.28.persistance=0
-unit.1.0.port.-1.s.28.value=0
-unit.1.0.port.-1.s.29.alias=unused29
-unit.1.0.port.-1.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.29.name=AsyncIn[29]
-unit.1.0.port.-1.s.29.orderindex=-1
-unit.1.0.port.-1.s.29.visible=1
-unit.1.0.port.-1.s.29.display=14
-unit.1.0.port.-1.s.29.persistance=0
-unit.1.0.port.-1.s.29.value=0
-unit.1.0.port.-1.s.30.alias=unused30
-unit.1.0.port.-1.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.30.name=AsyncIn[30]
-unit.1.0.port.-1.s.30.orderindex=-1
-unit.1.0.port.-1.s.30.visible=1
-unit.1.0.port.-1.s.30.display=14
-unit.1.0.port.-1.s.30.persistance=0
-unit.1.0.port.-1.s.30.value=0
-unit.1.0.port.-1.s.31.alias=unused31
-unit.1.0.port.-1.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.-1.s.31.name=AsyncIn[31]
-unit.1.0.port.-1.s.31.orderindex=-1
-unit.1.0.port.-1.s.31.visible=1
-unit.1.0.port.-1.s.31.display=14
-unit.1.0.port.-1.s.31.persistance=0
-unit.1.0.port.-1.s.31.value=0
-unit.1.0.port.0.buscount=0
-unit.1.0.port.0.channelcount=0
-unit.1.0.port.1.buscount=0
-unit.1.0.port.1.channelcount=32
-unit.1.0.port.1.s.31.alias=gtxtxreset
-unit.1.0.port.1.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.31.name=AsyncOut[31]
-unit.1.0.port.1.s.31.orderindex=-1
-unit.1.0.port.1.s.31.visible=1
-unit.1.0.port.1.s.31.display=1
-unit.1.0.port.1.s.31.persistance=0
-unit.1.0.port.1.s.31.value=0
-unit.1.0.port.1.s.30.alias=gtxrxreset
-unit.1.0.port.1.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.30.name=AsyncOut[30]
-unit.1.0.port.1.s.30.orderindex=-1
-unit.1.0.port.1.s.30.visible=1
-unit.1.0.port.1.s.30.display=1
-unit.1.0.port.1.s.30.persistance=0
-unit.1.0.port.1.s.30.value=0
-unit.1.0.port.1.s.29.alias=user_tx_reset
-unit.1.0.port.1.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.29.name=AsyncOut[29]
-unit.1.0.port.1.s.29.orderindex=-1
-unit.1.0.port.1.s.29.visible=1
-unit.1.0.port.1.s.29.display=1
-unit.1.0.port.1.s.29.persistance=0
-unit.1.0.port.1.s.29.value=0
-unit.1.0.port.1.s.28.alias=user_rx_reset
-unit.1.0.port.1.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.28.name=AsyncOut[28]
-unit.1.0.port.1.s.28.orderindex=-1
-unit.1.0.port.1.s.28.visible=1
-unit.1.0.port.1.s.28.display=1
-unit.1.0.port.1.s.28.persistance=0
-unit.1.0.port.1.s.28.value=0
-unit.1.0.port.1.s.0.alias=unused0
-unit.1.0.port.1.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.0.name=AsyncOut[0]
-unit.1.0.port.1.s.0.orderindex=-1
-unit.1.0.port.1.s.0.visible=1
-unit.1.0.port.1.s.0.display=1
-unit.1.0.port.1.s.0.persistance=0
-unit.1.0.port.1.s.0.value=0
-unit.1.0.port.1.s.1.alias=unused1
-unit.1.0.port.1.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.1.name=AsyncOut[1]
-unit.1.0.port.1.s.1.orderindex=-1
-unit.1.0.port.1.s.1.visible=1
-unit.1.0.port.1.s.1.display=1
-unit.1.0.port.1.s.1.persistance=0
-unit.1.0.port.1.s.1.value=0
-unit.1.0.port.1.s.2.alias=unused2
-unit.1.0.port.1.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.2.name=AsyncOut[2]
-unit.1.0.port.1.s.2.orderindex=-1
-unit.1.0.port.1.s.2.visible=1
-unit.1.0.port.1.s.2.display=1
-unit.1.0.port.1.s.2.persistance=0
-unit.1.0.port.1.s.2.value=0
-unit.1.0.port.1.s.3.alias=unused3
-unit.1.0.port.1.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.3.name=AsyncOut[3]
-unit.1.0.port.1.s.3.orderindex=-1
-unit.1.0.port.1.s.3.visible=1
-unit.1.0.port.1.s.3.display=1
-unit.1.0.port.1.s.3.persistance=0
-unit.1.0.port.1.s.3.value=0
-unit.1.0.port.1.s.4.alias=unused4
-unit.1.0.port.1.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.4.name=AsyncOut[4]
-unit.1.0.port.1.s.4.orderindex=-1
-unit.1.0.port.1.s.4.visible=1
-unit.1.0.port.1.s.4.display=1
-unit.1.0.port.1.s.4.persistance=0
-unit.1.0.port.1.s.4.value=0
-unit.1.0.port.1.s.5.alias=unused5
-unit.1.0.port.1.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.5.name=AsyncOut[5]
-unit.1.0.port.1.s.5.orderindex=-1
-unit.1.0.port.1.s.5.visible=1
-unit.1.0.port.1.s.5.display=1
-unit.1.0.port.1.s.5.persistance=0
-unit.1.0.port.1.s.5.value=0
-unit.1.0.port.1.s.6.alias=unused6
-unit.1.0.port.1.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.6.name=AsyncOut[6]
-unit.1.0.port.1.s.6.orderindex=-1
-unit.1.0.port.1.s.6.visible=1
-unit.1.0.port.1.s.6.display=1
-unit.1.0.port.1.s.6.persistance=0
-unit.1.0.port.1.s.6.value=0
-unit.1.0.port.1.s.7.alias=unused7
-unit.1.0.port.1.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.7.name=AsyncOut[7]
-unit.1.0.port.1.s.7.orderindex=-1
-unit.1.0.port.1.s.7.visible=1
-unit.1.0.port.1.s.7.display=1
-unit.1.0.port.1.s.7.persistance=0
-unit.1.0.port.1.s.7.value=0
-unit.1.0.port.1.s.8.alias=unused8
-unit.1.0.port.1.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.8.name=AsyncOut[8]
-unit.1.0.port.1.s.8.orderindex=-1
-unit.1.0.port.1.s.8.visible=1
-unit.1.0.port.1.s.8.display=1
-unit.1.0.port.1.s.8.persistance=0
-unit.1.0.port.1.s.8.value=0
-unit.1.0.port.1.s.9.alias=unused9
-unit.1.0.port.1.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.9.name=AsyncOut[9]
-unit.1.0.port.1.s.9.orderindex=-1
-unit.1.0.port.1.s.9.visible=1
-unit.1.0.port.1.s.9.display=1
-unit.1.0.port.1.s.9.persistance=0
-unit.1.0.port.1.s.9.value=0
-unit.1.0.port.1.s.10.alias=unused10
-unit.1.0.port.1.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.10.name=AsyncOut[10]
-unit.1.0.port.1.s.10.orderindex=-1
-unit.1.0.port.1.s.10.visible=1
-unit.1.0.port.1.s.10.display=1
-unit.1.0.port.1.s.10.persistance=0
-unit.1.0.port.1.s.10.value=0
-unit.1.0.port.1.s.11.alias=unused11
-unit.1.0.port.1.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.11.name=AsyncOut[11]
-unit.1.0.port.1.s.11.orderindex=-1
-unit.1.0.port.1.s.11.visible=1
-unit.1.0.port.1.s.11.display=1
-unit.1.0.port.1.s.11.persistance=0
-unit.1.0.port.1.s.11.value=0
-unit.1.0.port.1.s.12.alias=unused12
-unit.1.0.port.1.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.12.name=AsyncOut[12]
-unit.1.0.port.1.s.12.orderindex=-1
-unit.1.0.port.1.s.12.visible=1
-unit.1.0.port.1.s.12.display=1
-unit.1.0.port.1.s.12.persistance=0
-unit.1.0.port.1.s.12.value=0
-unit.1.0.port.1.s.13.alias=unused13
-unit.1.0.port.1.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.13.name=AsyncOut[13]
-unit.1.0.port.1.s.13.orderindex=-1
-unit.1.0.port.1.s.13.visible=1
-unit.1.0.port.1.s.13.display=1
-unit.1.0.port.1.s.13.persistance=0
-unit.1.0.port.1.s.13.value=0
-unit.1.0.port.1.s.14.alias=unused14
-unit.1.0.port.1.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.14.name=AsyncOut[14]
-unit.1.0.port.1.s.14.orderindex=-1
-unit.1.0.port.1.s.14.visible=1
-unit.1.0.port.1.s.14.display=1
-unit.1.0.port.1.s.14.persistance=0
-unit.1.0.port.1.s.14.value=0
-unit.1.0.port.1.s.15.alias=unused15
-unit.1.0.port.1.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.15.name=AsyncOut[15]
-unit.1.0.port.1.s.15.orderindex=-1
-unit.1.0.port.1.s.15.visible=1
-unit.1.0.port.1.s.15.display=1
-unit.1.0.port.1.s.15.persistance=0
-unit.1.0.port.1.s.15.value=0
-unit.1.0.port.1.s.16.alias=unused16
-unit.1.0.port.1.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.16.name=AsyncOut[16]
-unit.1.0.port.1.s.16.orderindex=-1
-unit.1.0.port.1.s.16.visible=1
-unit.1.0.port.1.s.16.display=1
-unit.1.0.port.1.s.16.persistance=0
-unit.1.0.port.1.s.16.value=0
-unit.1.0.port.1.s.17.alias=unused17
-unit.1.0.port.1.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.17.name=AsyncOut[17]
-unit.1.0.port.1.s.17.orderindex=-1
-unit.1.0.port.1.s.17.visible=1
-unit.1.0.port.1.s.17.display=1
-unit.1.0.port.1.s.17.persistance=0
-unit.1.0.port.1.s.17.value=0
-unit.1.0.port.1.s.18.alias=unused18
-unit.1.0.port.1.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.18.name=AsyncOut[18]
-unit.1.0.port.1.s.18.orderindex=-1
-unit.1.0.port.1.s.18.visible=1
-unit.1.0.port.1.s.18.display=1
-unit.1.0.port.1.s.18.persistance=0
-unit.1.0.port.1.s.18.value=0
-unit.1.0.port.1.s.19.alias=unused19
-unit.1.0.port.1.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.19.name=AsyncOut[19]
-unit.1.0.port.1.s.19.orderindex=-1
-unit.1.0.port.1.s.19.visible=1
-unit.1.0.port.1.s.19.display=1
-unit.1.0.port.1.s.19.persistance=0
-unit.1.0.port.1.s.19.value=0
-unit.1.0.port.1.s.20.alias=unused20
-unit.1.0.port.1.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.20.name=AsyncOut[20]
-unit.1.0.port.1.s.20.orderindex=-1
-unit.1.0.port.1.s.20.visible=1
-unit.1.0.port.1.s.20.display=1
-unit.1.0.port.1.s.20.persistance=0
-unit.1.0.port.1.s.20.value=0
-unit.1.0.port.1.s.21.alias=unused21
-unit.1.0.port.1.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.21.name=AsyncOut[21]
-unit.1.0.port.1.s.21.orderindex=-1
-unit.1.0.port.1.s.21.visible=1
-unit.1.0.port.1.s.21.display=1
-unit.1.0.port.1.s.21.persistance=0
-unit.1.0.port.1.s.21.value=0
-unit.1.0.port.1.s.22.alias=unused22
-unit.1.0.port.1.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.22.name=AsyncOut[22]
-unit.1.0.port.1.s.22.orderindex=-1
-unit.1.0.port.1.s.22.visible=1
-unit.1.0.port.1.s.22.display=1
-unit.1.0.port.1.s.22.persistance=0
-unit.1.0.port.1.s.22.value=0
-unit.1.0.port.1.s.23.alias=unused23
-unit.1.0.port.1.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.23.name=AsyncOut[23]
-unit.1.0.port.1.s.23.orderindex=-1
-unit.1.0.port.1.s.23.visible=1
-unit.1.0.port.1.s.23.display=1
-unit.1.0.port.1.s.23.persistance=0
-unit.1.0.port.1.s.23.value=0
-unit.1.0.port.1.s.24.alias=unused24
-unit.1.0.port.1.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.24.name=AsyncOut[24]
-unit.1.0.port.1.s.24.orderindex=-1
-unit.1.0.port.1.s.24.visible=1
-unit.1.0.port.1.s.24.display=1
-unit.1.0.port.1.s.24.persistance=0
-unit.1.0.port.1.s.24.value=0
-unit.1.0.port.1.s.25.alias=unused25
-unit.1.0.port.1.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.25.name=AsyncOut[25]
-unit.1.0.port.1.s.25.orderindex=-1
-unit.1.0.port.1.s.25.visible=1
-unit.1.0.port.1.s.25.display=1
-unit.1.0.port.1.s.25.persistance=0
-unit.1.0.port.1.s.25.value=0
-unit.1.0.port.1.s.26.alias=unused26
-unit.1.0.port.1.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.26.name=AsyncOut[26]
-unit.1.0.port.1.s.26.orderindex=-1
-unit.1.0.port.1.s.26.visible=1
-unit.1.0.port.1.s.26.display=1
-unit.1.0.port.1.s.26.persistance=0
-unit.1.0.port.1.s.26.value=0
-unit.1.0.port.1.s.27.alias=unused27
-unit.1.0.port.1.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.0.port.1.s.27.name=AsyncOut[27]
-unit.1.0.port.1.s.27.orderindex=-1
-unit.1.0.port.1.s.27.visible=1
-unit.1.0.port.1.s.27.display=1
-unit.1.0.port.1.s.27.persistance=0
-unit.1.0.port.1.s.27.value=0
-unit.1.0.port.2.buscount=0
-unit.1.0.port.2.channelcount=0
-unit.1.0.vio.count=4
-unit.1.0.vio.posn.0.channel=31
-unit.1.0.vio.posn.0.name=DataPort[31]
-unit.1.0.vio.posn.0.port=1
-unit.1.0.vio.posn.0.type=signal
-unit.1.0.vio.posn.1.channel=30
-unit.1.0.vio.posn.1.name=DataPort[30]
-unit.1.0.vio.posn.1.port=1
-unit.1.0.vio.posn.1.type=signal
-unit.1.0.vio.posn.2.channel=29
-unit.1.0.vio.posn.2.name=DataPort[29]
-unit.1.0.vio.posn.2.port=1
-unit.1.0.vio.posn.2.type=signal
-unit.1.0.vio.posn.3.channel=28
-unit.1.0.vio.posn.3.name=DataPort[28]
-unit.1.0.vio.posn.3.port=1
-unit.1.0.vio.posn.3.type=signal
-unit.1.0.vio.readperiod=0
-unit.1.1.6.HEIGHT6=0.3133998
-unit.1.1.6.WIDTH6=0.34575835
-unit.1.1.6.X6=0.2962725
-unit.1.1.6.Y6=0.0
-unit.1.1.coretype=VIO
-unit.1.1.portcount=3
-unit.1.1.username=MYVIO1
-unit.1.1.port.-1.b.0.alias=txdlyalignmonitor
-unit.1.1.port.-1.b.0.channellist=22 23 24 25 26 27 28 29
-unit.1.1.port.-1.b.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.b.0.name=txdlyalignmonitor
-unit.1.1.port.-1.b.0.orderindex=-1
-unit.1.1.port.-1.b.0.radix=Hex
-unit.1.1.port.-1.b.0.signedOffset=0.0
-unit.1.1.port.-1.b.0.signedPrecision=0
-unit.1.1.port.-1.b.0.signedScaleFactor=1.0
-unit.1.1.port.-1.b.0.tokencount=0
-unit.1.1.port.-1.b.0.unsignedOffset=0.0
-unit.1.1.port.-1.b.0.unsignedPrecision=0
-unit.1.1.port.-1.b.0.unsignedScaleFactor=1.0
-unit.1.1.port.-1.b.0.visible=1
-unit.1.1.port.-1.b.0.display=0
-unit.1.1.port.-1.b.0.value=00000000
-unit.1.1.port.-1.buscount=1
-unit.1.1.port.-1.channelcount=32
-unit.1.1.port.-1.s.31.alias=txplllkdet
-unit.1.1.port.-1.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.31.name=AsyncIn[31]
-unit.1.1.port.-1.s.31.orderindex=-1
-unit.1.1.port.-1.s.31.visible=1
-unit.1.1.port.-1.s.31.display=14
-unit.1.1.port.-1.s.31.persistance=0
-unit.1.1.port.-1.s.31.value=0
-unit.1.1.port.-1.s.30.alias=txresetdone
-unit.1.1.port.-1.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.30.name=AsyncIn[30]
-unit.1.1.port.-1.s.30.orderindex=-1
-unit.1.1.port.-1.s.30.visible=1
-unit.1.1.port.-1.s.30.display=14
-unit.1.1.port.-1.s.30.persistance=0
-unit.1.1.port.-1.s.30.value=0
-unit.1.1.port.-1.s.29.alias=txdlyalignmonitor[7]
-unit.1.1.port.-1.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.29.name=AsyncIn[29]
-unit.1.1.port.-1.s.29.orderindex=-1
-unit.1.1.port.-1.s.29.visible=1
-unit.1.1.port.-1.s.29.display=0
-unit.1.1.port.-1.s.29.persistance=0
-unit.1.1.port.-1.s.29.value=0
-unit.1.1.port.-1.s.28.alias=txdlyalignmonitor[6]
-unit.1.1.port.-1.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.28.name=AsyncIn[28]
-unit.1.1.port.-1.s.28.orderindex=-1
-unit.1.1.port.-1.s.28.visible=1
-unit.1.1.port.-1.s.28.display=0
-unit.1.1.port.-1.s.28.persistance=0
-unit.1.1.port.-1.s.28.value=0
-unit.1.1.port.-1.s.27.alias=txdlyalignmonitor[5]
-unit.1.1.port.-1.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.27.name=AsyncIn[27]
-unit.1.1.port.-1.s.27.orderindex=-1
-unit.1.1.port.-1.s.27.visible=1
-unit.1.1.port.-1.s.27.display=0
-unit.1.1.port.-1.s.27.persistance=0
-unit.1.1.port.-1.s.27.value=0
-unit.1.1.port.-1.s.26.alias=txdlyalignmonitor[4]
-unit.1.1.port.-1.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.26.name=AsyncIn[26]
-unit.1.1.port.-1.s.26.orderindex=-1
-unit.1.1.port.-1.s.26.visible=1
-unit.1.1.port.-1.s.26.display=0
-unit.1.1.port.-1.s.26.persistance=0
-unit.1.1.port.-1.s.26.value=0
-unit.1.1.port.-1.s.25.alias=txdlyalignmonitor[3]
-unit.1.1.port.-1.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.25.name=AsyncIn[25]
-unit.1.1.port.-1.s.25.orderindex=-1
-unit.1.1.port.-1.s.25.visible=1
-unit.1.1.port.-1.s.25.display=0
-unit.1.1.port.-1.s.25.persistance=0
-unit.1.1.port.-1.s.25.value=0
-unit.1.1.port.-1.s.24.alias=txdlyalignmonitor[2]
-unit.1.1.port.-1.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.24.name=AsyncIn[24]
-unit.1.1.port.-1.s.24.orderindex=-1
-unit.1.1.port.-1.s.24.visible=1
-unit.1.1.port.-1.s.24.display=0
-unit.1.1.port.-1.s.24.persistance=0
-unit.1.1.port.-1.s.24.value=0
-unit.1.1.port.-1.s.23.alias=txdlyalignmonitor[1]
-unit.1.1.port.-1.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.23.name=AsyncIn[23]
-unit.1.1.port.-1.s.23.orderindex=-1
-unit.1.1.port.-1.s.23.visible=1
-unit.1.1.port.-1.s.23.display=0
-unit.1.1.port.-1.s.23.persistance=0
-unit.1.1.port.-1.s.23.value=0
-unit.1.1.port.-1.s.22.alias=txdlyalignmonitor[0]
-unit.1.1.port.-1.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.22.name=AsyncIn[22]
-unit.1.1.port.-1.s.22.orderindex=-1
-unit.1.1.port.-1.s.22.visible=1
-unit.1.1.port.-1.s.22.display=0
-unit.1.1.port.-1.s.22.persistance=0
-unit.1.1.port.-1.s.22.value=0
-unit.1.1.port.-1.s.0.alias=unused0
-unit.1.1.port.-1.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.0.name=AsyncIn[0]
-unit.1.1.port.-1.s.0.orderindex=-1
-unit.1.1.port.-1.s.0.visible=1
-unit.1.1.port.-1.s.0.display=14
-unit.1.1.port.-1.s.0.persistance=0
-unit.1.1.port.-1.s.0.value=0
-unit.1.1.port.-1.s.1.alias=unused1
-unit.1.1.port.-1.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.1.name=AsyncIn[1]
-unit.1.1.port.-1.s.1.orderindex=-1
-unit.1.1.port.-1.s.1.visible=1
-unit.1.1.port.-1.s.1.display=14
-unit.1.1.port.-1.s.1.persistance=0
-unit.1.1.port.-1.s.1.value=0
-unit.1.1.port.-1.s.2.alias=unused2
-unit.1.1.port.-1.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.2.name=AsyncIn[2]
-unit.1.1.port.-1.s.2.orderindex=-1
-unit.1.1.port.-1.s.2.visible=1
-unit.1.1.port.-1.s.2.display=14
-unit.1.1.port.-1.s.2.persistance=0
-unit.1.1.port.-1.s.2.value=0
-unit.1.1.port.-1.s.3.alias=unused3
-unit.1.1.port.-1.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.3.name=AsyncIn[3]
-unit.1.1.port.-1.s.3.orderindex=-1
-unit.1.1.port.-1.s.3.visible=1
-unit.1.1.port.-1.s.3.display=14
-unit.1.1.port.-1.s.3.persistance=0
-unit.1.1.port.-1.s.3.value=0
-unit.1.1.port.-1.s.4.alias=unused4
-unit.1.1.port.-1.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.4.name=AsyncIn[4]
-unit.1.1.port.-1.s.4.orderindex=-1
-unit.1.1.port.-1.s.4.visible=1
-unit.1.1.port.-1.s.4.display=14
-unit.1.1.port.-1.s.4.persistance=0
-unit.1.1.port.-1.s.4.value=0
-unit.1.1.port.-1.s.5.alias=unused5
-unit.1.1.port.-1.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.5.name=AsyncIn[5]
-unit.1.1.port.-1.s.5.orderindex=-1
-unit.1.1.port.-1.s.5.visible=1
-unit.1.1.port.-1.s.5.display=14
-unit.1.1.port.-1.s.5.persistance=0
-unit.1.1.port.-1.s.5.value=0
-unit.1.1.port.-1.s.6.alias=unused6
-unit.1.1.port.-1.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.6.name=AsyncIn[6]
-unit.1.1.port.-1.s.6.orderindex=-1
-unit.1.1.port.-1.s.6.visible=1
-unit.1.1.port.-1.s.6.display=14
-unit.1.1.port.-1.s.6.persistance=0
-unit.1.1.port.-1.s.6.value=0
-unit.1.1.port.-1.s.7.alias=unused7
-unit.1.1.port.-1.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.7.name=AsyncIn[7]
-unit.1.1.port.-1.s.7.orderindex=-1
-unit.1.1.port.-1.s.7.visible=1
-unit.1.1.port.-1.s.7.display=14
-unit.1.1.port.-1.s.7.persistance=0
-unit.1.1.port.-1.s.7.value=0
-unit.1.1.port.-1.s.8.alias=unused8
-unit.1.1.port.-1.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.8.name=AsyncIn[8]
-unit.1.1.port.-1.s.8.orderindex=-1
-unit.1.1.port.-1.s.8.visible=1
-unit.1.1.port.-1.s.8.display=14
-unit.1.1.port.-1.s.8.persistance=0
-unit.1.1.port.-1.s.8.value=0
-unit.1.1.port.-1.s.9.alias=unused9
-unit.1.1.port.-1.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.9.name=AsyncIn[9]
-unit.1.1.port.-1.s.9.orderindex=-1
-unit.1.1.port.-1.s.9.visible=1
-unit.1.1.port.-1.s.9.display=14
-unit.1.1.port.-1.s.9.persistance=0
-unit.1.1.port.-1.s.9.value=0
-unit.1.1.port.-1.s.10.alias=unused10
-unit.1.1.port.-1.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.10.name=AsyncIn[10]
-unit.1.1.port.-1.s.10.orderindex=-1
-unit.1.1.port.-1.s.10.visible=1
-unit.1.1.port.-1.s.10.display=14
-unit.1.1.port.-1.s.10.persistance=0
-unit.1.1.port.-1.s.10.value=0
-unit.1.1.port.-1.s.11.alias=unused11
-unit.1.1.port.-1.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.11.name=AsyncIn[11]
-unit.1.1.port.-1.s.11.orderindex=-1
-unit.1.1.port.-1.s.11.visible=1
-unit.1.1.port.-1.s.11.display=14
-unit.1.1.port.-1.s.11.persistance=0
-unit.1.1.port.-1.s.11.value=0
-unit.1.1.port.-1.s.12.alias=unused12
-unit.1.1.port.-1.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.12.name=AsyncIn[12]
-unit.1.1.port.-1.s.12.orderindex=-1
-unit.1.1.port.-1.s.12.visible=1
-unit.1.1.port.-1.s.12.display=14
-unit.1.1.port.-1.s.12.persistance=0
-unit.1.1.port.-1.s.12.value=0
-unit.1.1.port.-1.s.13.alias=unused13
-unit.1.1.port.-1.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.13.name=AsyncIn[13]
-unit.1.1.port.-1.s.13.orderindex=-1
-unit.1.1.port.-1.s.13.visible=1
-unit.1.1.port.-1.s.13.display=14
-unit.1.1.port.-1.s.13.persistance=0
-unit.1.1.port.-1.s.13.value=0
-unit.1.1.port.-1.s.14.alias=unused14
-unit.1.1.port.-1.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.14.name=AsyncIn[14]
-unit.1.1.port.-1.s.14.orderindex=-1
-unit.1.1.port.-1.s.14.visible=1
-unit.1.1.port.-1.s.14.display=14
-unit.1.1.port.-1.s.14.persistance=0
-unit.1.1.port.-1.s.14.value=0
-unit.1.1.port.-1.s.15.alias=unused15
-unit.1.1.port.-1.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.15.name=AsyncIn[15]
-unit.1.1.port.-1.s.15.orderindex=-1
-unit.1.1.port.-1.s.15.visible=1
-unit.1.1.port.-1.s.15.display=14
-unit.1.1.port.-1.s.15.persistance=0
-unit.1.1.port.-1.s.15.value=0
-unit.1.1.port.-1.s.16.alias=unused16
-unit.1.1.port.-1.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.16.name=AsyncIn[16]
-unit.1.1.port.-1.s.16.orderindex=-1
-unit.1.1.port.-1.s.16.visible=1
-unit.1.1.port.-1.s.16.display=14
-unit.1.1.port.-1.s.16.persistance=0
-unit.1.1.port.-1.s.16.value=0
-unit.1.1.port.-1.s.17.alias=unused17
-unit.1.1.port.-1.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.17.name=AsyncIn[17]
-unit.1.1.port.-1.s.17.orderindex=-1
-unit.1.1.port.-1.s.17.visible=1
-unit.1.1.port.-1.s.17.display=14
-unit.1.1.port.-1.s.17.persistance=0
-unit.1.1.port.-1.s.17.value=0
-unit.1.1.port.-1.s.18.alias=unused18
-unit.1.1.port.-1.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.18.name=AsyncIn[18]
-unit.1.1.port.-1.s.18.orderindex=-1
-unit.1.1.port.-1.s.18.visible=1
-unit.1.1.port.-1.s.18.display=14
-unit.1.1.port.-1.s.18.persistance=0
-unit.1.1.port.-1.s.18.value=0
-unit.1.1.port.-1.s.19.alias=unused19
-unit.1.1.port.-1.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.19.name=AsyncIn[19]
-unit.1.1.port.-1.s.19.orderindex=-1
-unit.1.1.port.-1.s.19.visible=1
-unit.1.1.port.-1.s.19.display=14
-unit.1.1.port.-1.s.19.persistance=0
-unit.1.1.port.-1.s.19.value=0
-unit.1.1.port.-1.s.20.alias=unused20
-unit.1.1.port.-1.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.20.name=AsyncIn[20]
-unit.1.1.port.-1.s.20.orderindex=-1
-unit.1.1.port.-1.s.20.visible=1
-unit.1.1.port.-1.s.20.display=14
-unit.1.1.port.-1.s.20.persistance=0
-unit.1.1.port.-1.s.20.value=0
-unit.1.1.port.-1.s.21.alias=unused21
-unit.1.1.port.-1.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.-1.s.21.name=AsyncIn[21]
-unit.1.1.port.-1.s.21.orderindex=-1
-unit.1.1.port.-1.s.21.visible=1
-unit.1.1.port.-1.s.21.display=14
-unit.1.1.port.-1.s.21.persistance=0
-unit.1.1.port.-1.s.21.value=0
-unit.1.1.port.0.buscount=0
-unit.1.1.port.0.channelcount=0
-unit.1.1.port.0.buscount=0
-unit.1.1.port.0.channelcount=32
-unit.1.1.port.0.s.0.alias=unused0
-unit.1.1.port.0.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.0.name=SyncIn[0]
-unit.1.1.port.0.s.0.orderindex=-1
-unit.1.1.port.0.s.0.visible=1
-unit.1.1.port.0.s.0.display=14
-unit.1.1.port.0.s.0.persistance=0
-unit.1.1.port.0.s.0.value=0
-unit.1.1.port.0.s.1.alias=unused1
-unit.1.1.port.0.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.1.name=SyncIn[1]
-unit.1.1.port.0.s.1.orderindex=-1
-unit.1.1.port.0.s.1.visible=1
-unit.1.1.port.0.s.1.display=14
-unit.1.1.port.0.s.1.persistance=0
-unit.1.1.port.0.s.1.value=0
-unit.1.1.port.0.s.2.alias=unused2
-unit.1.1.port.0.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.2.name=SyncIn[2]
-unit.1.1.port.0.s.2.orderindex=-1
-unit.1.1.port.0.s.2.visible=1
-unit.1.1.port.0.s.2.display=14
-unit.1.1.port.0.s.2.persistance=0
-unit.1.1.port.0.s.2.value=0
-unit.1.1.port.0.s.3.alias=unused3
-unit.1.1.port.0.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.3.name=SyncIn[3]
-unit.1.1.port.0.s.3.orderindex=-1
-unit.1.1.port.0.s.3.visible=1
-unit.1.1.port.0.s.3.display=14
-unit.1.1.port.0.s.3.persistance=0
-unit.1.1.port.0.s.3.value=0
-unit.1.1.port.0.s.4.alias=unused4
-unit.1.1.port.0.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.4.name=SyncIn[4]
-unit.1.1.port.0.s.4.orderindex=-1
-unit.1.1.port.0.s.4.visible=1
-unit.1.1.port.0.s.4.display=14
-unit.1.1.port.0.s.4.persistance=0
-unit.1.1.port.0.s.4.value=0
-unit.1.1.port.0.s.5.alias=unused5
-unit.1.1.port.0.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.5.name=SyncIn[5]
-unit.1.1.port.0.s.5.orderindex=-1
-unit.1.1.port.0.s.5.visible=1
-unit.1.1.port.0.s.5.display=14
-unit.1.1.port.0.s.5.persistance=0
-unit.1.1.port.0.s.5.value=0
-unit.1.1.port.0.s.6.alias=unused6
-unit.1.1.port.0.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.6.name=SyncIn[6]
-unit.1.1.port.0.s.6.orderindex=-1
-unit.1.1.port.0.s.6.visible=1
-unit.1.1.port.0.s.6.display=14
-unit.1.1.port.0.s.6.persistance=0
-unit.1.1.port.0.s.6.value=0
-unit.1.1.port.0.s.7.alias=unused7
-unit.1.1.port.0.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.7.name=SyncIn[7]
-unit.1.1.port.0.s.7.orderindex=-1
-unit.1.1.port.0.s.7.visible=1
-unit.1.1.port.0.s.7.display=14
-unit.1.1.port.0.s.7.persistance=0
-unit.1.1.port.0.s.7.value=0
-unit.1.1.port.0.s.8.alias=unused8
-unit.1.1.port.0.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.8.name=SyncIn[8]
-unit.1.1.port.0.s.8.orderindex=-1
-unit.1.1.port.0.s.8.visible=1
-unit.1.1.port.0.s.8.display=14
-unit.1.1.port.0.s.8.persistance=0
-unit.1.1.port.0.s.8.value=0
-unit.1.1.port.0.s.9.alias=unused9
-unit.1.1.port.0.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.9.name=SyncIn[9]
-unit.1.1.port.0.s.9.orderindex=-1
-unit.1.1.port.0.s.9.visible=1
-unit.1.1.port.0.s.9.display=14
-unit.1.1.port.0.s.9.persistance=0
-unit.1.1.port.0.s.9.value=0
-unit.1.1.port.0.s.10.alias=unused10
-unit.1.1.port.0.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.10.name=SyncIn[10]
-unit.1.1.port.0.s.10.orderindex=-1
-unit.1.1.port.0.s.10.visible=1
-unit.1.1.port.0.s.10.display=14
-unit.1.1.port.0.s.10.persistance=0
-unit.1.1.port.0.s.10.value=0
-unit.1.1.port.0.s.11.alias=unused11
-unit.1.1.port.0.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.11.name=SyncIn[11]
-unit.1.1.port.0.s.11.orderindex=-1
-unit.1.1.port.0.s.11.visible=1
-unit.1.1.port.0.s.11.display=14
-unit.1.1.port.0.s.11.persistance=0
-unit.1.1.port.0.s.11.value=0
-unit.1.1.port.0.s.12.alias=unused12
-unit.1.1.port.0.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.12.name=SyncIn[12]
-unit.1.1.port.0.s.12.orderindex=-1
-unit.1.1.port.0.s.12.visible=1
-unit.1.1.port.0.s.12.display=14
-unit.1.1.port.0.s.12.persistance=0
-unit.1.1.port.0.s.12.value=0
-unit.1.1.port.0.s.13.alias=unused13
-unit.1.1.port.0.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.13.name=SyncIn[13]
-unit.1.1.port.0.s.13.orderindex=-1
-unit.1.1.port.0.s.13.visible=1
-unit.1.1.port.0.s.13.display=14
-unit.1.1.port.0.s.13.persistance=0
-unit.1.1.port.0.s.13.value=0
-unit.1.1.port.0.s.14.alias=unused14
-unit.1.1.port.0.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.14.name=SyncIn[14]
-unit.1.1.port.0.s.14.orderindex=-1
-unit.1.1.port.0.s.14.visible=1
-unit.1.1.port.0.s.14.display=14
-unit.1.1.port.0.s.14.persistance=0
-unit.1.1.port.0.s.14.value=0
-unit.1.1.port.0.s.15.alias=unused15
-unit.1.1.port.0.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.15.name=SyncIn[15]
-unit.1.1.port.0.s.15.orderindex=-1
-unit.1.1.port.0.s.15.visible=1
-unit.1.1.port.0.s.15.display=14
-unit.1.1.port.0.s.15.persistance=0
-unit.1.1.port.0.s.15.value=0
-unit.1.1.port.0.s.16.alias=unused16
-unit.1.1.port.0.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.16.name=SyncIn[16]
-unit.1.1.port.0.s.16.orderindex=-1
-unit.1.1.port.0.s.16.visible=1
-unit.1.1.port.0.s.16.display=14
-unit.1.1.port.0.s.16.persistance=0
-unit.1.1.port.0.s.16.value=0
-unit.1.1.port.0.s.17.alias=unused17
-unit.1.1.port.0.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.17.name=SyncIn[17]
-unit.1.1.port.0.s.17.orderindex=-1
-unit.1.1.port.0.s.17.visible=1
-unit.1.1.port.0.s.17.display=14
-unit.1.1.port.0.s.17.persistance=0
-unit.1.1.port.0.s.17.value=0
-unit.1.1.port.0.s.18.alias=unused18
-unit.1.1.port.0.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.18.name=SyncIn[18]
-unit.1.1.port.0.s.18.orderindex=-1
-unit.1.1.port.0.s.18.visible=1
-unit.1.1.port.0.s.18.display=14
-unit.1.1.port.0.s.18.persistance=0
-unit.1.1.port.0.s.18.value=0
-unit.1.1.port.0.s.19.alias=unused19
-unit.1.1.port.0.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.19.name=SyncIn[19]
-unit.1.1.port.0.s.19.orderindex=-1
-unit.1.1.port.0.s.19.visible=1
-unit.1.1.port.0.s.19.display=14
-unit.1.1.port.0.s.19.persistance=0
-unit.1.1.port.0.s.19.value=0
-unit.1.1.port.0.s.20.alias=unused20
-unit.1.1.port.0.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.20.name=SyncIn[20]
-unit.1.1.port.0.s.20.orderindex=-1
-unit.1.1.port.0.s.20.visible=1
-unit.1.1.port.0.s.20.display=14
-unit.1.1.port.0.s.20.persistance=0
-unit.1.1.port.0.s.20.value=0
-unit.1.1.port.0.s.21.alias=unused21
-unit.1.1.port.0.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.21.name=SyncIn[21]
-unit.1.1.port.0.s.21.orderindex=-1
-unit.1.1.port.0.s.21.visible=1
-unit.1.1.port.0.s.21.display=14
-unit.1.1.port.0.s.21.persistance=0
-unit.1.1.port.0.s.21.value=0
-unit.1.1.port.0.s.22.alias=unused22
-unit.1.1.port.0.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.22.name=SyncIn[22]
-unit.1.1.port.0.s.22.orderindex=-1
-unit.1.1.port.0.s.22.visible=1
-unit.1.1.port.0.s.22.display=14
-unit.1.1.port.0.s.22.persistance=0
-unit.1.1.port.0.s.22.value=0
-unit.1.1.port.0.s.23.alias=unused23
-unit.1.1.port.0.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.23.name=SyncIn[23]
-unit.1.1.port.0.s.23.orderindex=-1
-unit.1.1.port.0.s.23.visible=1
-unit.1.1.port.0.s.23.display=14
-unit.1.1.port.0.s.23.persistance=0
-unit.1.1.port.0.s.23.value=0
-unit.1.1.port.0.s.24.alias=unused24
-unit.1.1.port.0.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.24.name=SyncIn[24]
-unit.1.1.port.0.s.24.orderindex=-1
-unit.1.1.port.0.s.24.visible=1
-unit.1.1.port.0.s.24.display=14
-unit.1.1.port.0.s.24.persistance=0
-unit.1.1.port.0.s.24.value=0
-unit.1.1.port.0.s.25.alias=unused25
-unit.1.1.port.0.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.25.name=SyncIn[25]
-unit.1.1.port.0.s.25.orderindex=-1
-unit.1.1.port.0.s.25.visible=1
-unit.1.1.port.0.s.25.display=14
-unit.1.1.port.0.s.25.persistance=0
-unit.1.1.port.0.s.25.value=0
-unit.1.1.port.0.s.26.alias=unused26
-unit.1.1.port.0.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.26.name=SyncIn[26]
-unit.1.1.port.0.s.26.orderindex=-1
-unit.1.1.port.0.s.26.visible=1
-unit.1.1.port.0.s.26.display=14
-unit.1.1.port.0.s.26.persistance=0
-unit.1.1.port.0.s.26.value=0
-unit.1.1.port.0.s.27.alias=unused27
-unit.1.1.port.0.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.27.name=SyncIn[27]
-unit.1.1.port.0.s.27.orderindex=-1
-unit.1.1.port.0.s.27.visible=1
-unit.1.1.port.0.s.27.display=14
-unit.1.1.port.0.s.27.persistance=0
-unit.1.1.port.0.s.27.value=0
-unit.1.1.port.0.s.28.alias=unused28
-unit.1.1.port.0.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.28.name=SyncIn[28]
-unit.1.1.port.0.s.28.orderindex=-1
-unit.1.1.port.0.s.28.visible=1
-unit.1.1.port.0.s.28.display=14
-unit.1.1.port.0.s.28.persistance=0
-unit.1.1.port.0.s.28.value=0
-unit.1.1.port.0.s.29.alias=unused29
-unit.1.1.port.0.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.29.name=SyncIn[29]
-unit.1.1.port.0.s.29.orderindex=-1
-unit.1.1.port.0.s.29.visible=1
-unit.1.1.port.0.s.29.display=14
-unit.1.1.port.0.s.29.persistance=0
-unit.1.1.port.0.s.29.value=0
-unit.1.1.port.0.s.30.alias=unused30
-unit.1.1.port.0.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.30.name=SyncIn[30]
-unit.1.1.port.0.s.30.orderindex=-1
-unit.1.1.port.0.s.30.visible=1
-unit.1.1.port.0.s.30.display=14
-unit.1.1.port.0.s.30.persistance=0
-unit.1.1.port.0.s.30.value=0
-unit.1.1.port.0.s.31.alias=unused31
-unit.1.1.port.0.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.0.s.31.name=SyncIn[31]
-unit.1.1.port.0.s.31.orderindex=-1
-unit.1.1.port.0.s.31.visible=1
-unit.1.1.port.0.s.31.display=14
-unit.1.1.port.0.s.31.persistance=0
-unit.1.1.port.0.s.31.value=0
-unit.1.1.port.1.buscount=0
-unit.1.1.port.1.channelcount=0
-unit.1.1.port.1.buscount=0
-unit.1.1.port.1.channelcount=32
-unit.1.1.port.1.s.31.alias=plltxreset
-unit.1.1.port.1.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.31.name=AsyncOut[31]
-unit.1.1.port.1.s.31.orderindex=-1
-unit.1.1.port.1.s.31.visible=1
-unit.1.1.port.1.s.31.display=1
-unit.1.1.port.1.s.31.persistance=0
-unit.1.1.port.1.s.31.value=0
-unit.1.1.port.1.s.0.alias=unused0
-unit.1.1.port.1.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.0.name=AsyncOut[0]
-unit.1.1.port.1.s.0.orderindex=-1
-unit.1.1.port.1.s.0.visible=1
-unit.1.1.port.1.s.0.display=1
-unit.1.1.port.1.s.0.persistance=0
-unit.1.1.port.1.s.0.value=0
-unit.1.1.port.1.s.1.alias=unused1
-unit.1.1.port.1.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.1.name=AsyncOut[1]
-unit.1.1.port.1.s.1.orderindex=-1
-unit.1.1.port.1.s.1.visible=1
-unit.1.1.port.1.s.1.display=1
-unit.1.1.port.1.s.1.persistance=0
-unit.1.1.port.1.s.1.value=0
-unit.1.1.port.1.s.2.alias=unused2
-unit.1.1.port.1.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.2.name=AsyncOut[2]
-unit.1.1.port.1.s.2.orderindex=-1
-unit.1.1.port.1.s.2.visible=1
-unit.1.1.port.1.s.2.display=1
-unit.1.1.port.1.s.2.persistance=0
-unit.1.1.port.1.s.2.value=0
-unit.1.1.port.1.s.3.alias=unused3
-unit.1.1.port.1.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.3.name=AsyncOut[3]
-unit.1.1.port.1.s.3.orderindex=-1
-unit.1.1.port.1.s.3.visible=1
-unit.1.1.port.1.s.3.display=1
-unit.1.1.port.1.s.3.persistance=0
-unit.1.1.port.1.s.3.value=0
-unit.1.1.port.1.s.4.alias=unused4
-unit.1.1.port.1.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.4.name=AsyncOut[4]
-unit.1.1.port.1.s.4.orderindex=-1
-unit.1.1.port.1.s.4.visible=1
-unit.1.1.port.1.s.4.display=1
-unit.1.1.port.1.s.4.persistance=0
-unit.1.1.port.1.s.4.value=0
-unit.1.1.port.1.s.5.alias=unused5
-unit.1.1.port.1.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.5.name=AsyncOut[5]
-unit.1.1.port.1.s.5.orderindex=-1
-unit.1.1.port.1.s.5.visible=1
-unit.1.1.port.1.s.5.display=1
-unit.1.1.port.1.s.5.persistance=0
-unit.1.1.port.1.s.5.value=0
-unit.1.1.port.1.s.6.alias=unused6
-unit.1.1.port.1.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.6.name=AsyncOut[6]
-unit.1.1.port.1.s.6.orderindex=-1
-unit.1.1.port.1.s.6.visible=1
-unit.1.1.port.1.s.6.display=1
-unit.1.1.port.1.s.6.persistance=0
-unit.1.1.port.1.s.6.value=0
-unit.1.1.port.1.s.7.alias=unused7
-unit.1.1.port.1.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.7.name=AsyncOut[7]
-unit.1.1.port.1.s.7.orderindex=-1
-unit.1.1.port.1.s.7.visible=1
-unit.1.1.port.1.s.7.display=1
-unit.1.1.port.1.s.7.persistance=0
-unit.1.1.port.1.s.7.value=0
-unit.1.1.port.1.s.8.alias=unused8
-unit.1.1.port.1.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.8.name=AsyncOut[8]
-unit.1.1.port.1.s.8.orderindex=-1
-unit.1.1.port.1.s.8.visible=1
-unit.1.1.port.1.s.8.display=1
-unit.1.1.port.1.s.8.persistance=0
-unit.1.1.port.1.s.8.value=0
-unit.1.1.port.1.s.9.alias=unused9
-unit.1.1.port.1.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.9.name=AsyncOut[9]
-unit.1.1.port.1.s.9.orderindex=-1
-unit.1.1.port.1.s.9.visible=1
-unit.1.1.port.1.s.9.display=1
-unit.1.1.port.1.s.9.persistance=0
-unit.1.1.port.1.s.9.value=0
-unit.1.1.port.1.s.10.alias=unused10
-unit.1.1.port.1.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.10.name=AsyncOut[10]
-unit.1.1.port.1.s.10.orderindex=-1
-unit.1.1.port.1.s.10.visible=1
-unit.1.1.port.1.s.10.display=1
-unit.1.1.port.1.s.10.persistance=0
-unit.1.1.port.1.s.10.value=0
-unit.1.1.port.1.s.11.alias=unused11
-unit.1.1.port.1.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.11.name=AsyncOut[11]
-unit.1.1.port.1.s.11.orderindex=-1
-unit.1.1.port.1.s.11.visible=1
-unit.1.1.port.1.s.11.display=1
-unit.1.1.port.1.s.11.persistance=0
-unit.1.1.port.1.s.11.value=0
-unit.1.1.port.1.s.12.alias=unused12
-unit.1.1.port.1.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.12.name=AsyncOut[12]
-unit.1.1.port.1.s.12.orderindex=-1
-unit.1.1.port.1.s.12.visible=1
-unit.1.1.port.1.s.12.display=1
-unit.1.1.port.1.s.12.persistance=0
-unit.1.1.port.1.s.12.value=0
-unit.1.1.port.1.s.13.alias=unused13
-unit.1.1.port.1.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.13.name=AsyncOut[13]
-unit.1.1.port.1.s.13.orderindex=-1
-unit.1.1.port.1.s.13.visible=1
-unit.1.1.port.1.s.13.display=1
-unit.1.1.port.1.s.13.persistance=0
-unit.1.1.port.1.s.13.value=0
-unit.1.1.port.1.s.14.alias=unused14
-unit.1.1.port.1.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.14.name=AsyncOut[14]
-unit.1.1.port.1.s.14.orderindex=-1
-unit.1.1.port.1.s.14.visible=1
-unit.1.1.port.1.s.14.display=1
-unit.1.1.port.1.s.14.persistance=0
-unit.1.1.port.1.s.14.value=0
-unit.1.1.port.1.s.15.alias=unused15
-unit.1.1.port.1.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.15.name=AsyncOut[15]
-unit.1.1.port.1.s.15.orderindex=-1
-unit.1.1.port.1.s.15.visible=1
-unit.1.1.port.1.s.15.display=1
-unit.1.1.port.1.s.15.persistance=0
-unit.1.1.port.1.s.15.value=0
-unit.1.1.port.1.s.16.alias=unused16
-unit.1.1.port.1.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.16.name=AsyncOut[16]
-unit.1.1.port.1.s.16.orderindex=-1
-unit.1.1.port.1.s.16.visible=1
-unit.1.1.port.1.s.16.display=1
-unit.1.1.port.1.s.16.persistance=0
-unit.1.1.port.1.s.16.value=0
-unit.1.1.port.1.s.17.alias=unused17
-unit.1.1.port.1.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.17.name=AsyncOut[17]
-unit.1.1.port.1.s.17.orderindex=-1
-unit.1.1.port.1.s.17.visible=1
-unit.1.1.port.1.s.17.display=1
-unit.1.1.port.1.s.17.persistance=0
-unit.1.1.port.1.s.17.value=0
-unit.1.1.port.1.s.18.alias=unused18
-unit.1.1.port.1.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.18.name=AsyncOut[18]
-unit.1.1.port.1.s.18.orderindex=-1
-unit.1.1.port.1.s.18.visible=1
-unit.1.1.port.1.s.18.display=1
-unit.1.1.port.1.s.18.persistance=0
-unit.1.1.port.1.s.18.value=0
-unit.1.1.port.1.s.19.alias=unused19
-unit.1.1.port.1.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.19.name=AsyncOut[19]
-unit.1.1.port.1.s.19.orderindex=-1
-unit.1.1.port.1.s.19.visible=1
-unit.1.1.port.1.s.19.display=1
-unit.1.1.port.1.s.19.persistance=0
-unit.1.1.port.1.s.19.value=0
-unit.1.1.port.1.s.20.alias=unused20
-unit.1.1.port.1.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.20.name=AsyncOut[20]
-unit.1.1.port.1.s.20.orderindex=-1
-unit.1.1.port.1.s.20.visible=1
-unit.1.1.port.1.s.20.display=1
-unit.1.1.port.1.s.20.persistance=0
-unit.1.1.port.1.s.20.value=0
-unit.1.1.port.1.s.21.alias=unused21
-unit.1.1.port.1.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.21.name=AsyncOut[21]
-unit.1.1.port.1.s.21.orderindex=-1
-unit.1.1.port.1.s.21.visible=1
-unit.1.1.port.1.s.21.display=1
-unit.1.1.port.1.s.21.persistance=0
-unit.1.1.port.1.s.21.value=0
-unit.1.1.port.1.s.22.alias=unused22
-unit.1.1.port.1.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.22.name=AsyncOut[22]
-unit.1.1.port.1.s.22.orderindex=-1
-unit.1.1.port.1.s.22.visible=1
-unit.1.1.port.1.s.22.display=1
-unit.1.1.port.1.s.22.persistance=0
-unit.1.1.port.1.s.22.value=0
-unit.1.1.port.1.s.23.alias=unused23
-unit.1.1.port.1.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.23.name=AsyncOut[23]
-unit.1.1.port.1.s.23.orderindex=-1
-unit.1.1.port.1.s.23.visible=1
-unit.1.1.port.1.s.23.display=1
-unit.1.1.port.1.s.23.persistance=0
-unit.1.1.port.1.s.23.value=0
-unit.1.1.port.1.s.24.alias=unused24
-unit.1.1.port.1.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.24.name=AsyncOut[24]
-unit.1.1.port.1.s.24.orderindex=-1
-unit.1.1.port.1.s.24.visible=1
-unit.1.1.port.1.s.24.display=1
-unit.1.1.port.1.s.24.persistance=0
-unit.1.1.port.1.s.24.value=0
-unit.1.1.port.1.s.25.alias=unused25
-unit.1.1.port.1.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.25.name=AsyncOut[25]
-unit.1.1.port.1.s.25.orderindex=-1
-unit.1.1.port.1.s.25.visible=1
-unit.1.1.port.1.s.25.display=1
-unit.1.1.port.1.s.25.persistance=0
-unit.1.1.port.1.s.25.value=0
-unit.1.1.port.1.s.26.alias=unused26
-unit.1.1.port.1.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.26.name=AsyncOut[26]
-unit.1.1.port.1.s.26.orderindex=-1
-unit.1.1.port.1.s.26.visible=1
-unit.1.1.port.1.s.26.display=1
-unit.1.1.port.1.s.26.persistance=0
-unit.1.1.port.1.s.26.value=0
-unit.1.1.port.1.s.27.alias=unused27
-unit.1.1.port.1.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.27.name=AsyncOut[27]
-unit.1.1.port.1.s.27.orderindex=-1
-unit.1.1.port.1.s.27.visible=1
-unit.1.1.port.1.s.27.display=1
-unit.1.1.port.1.s.27.persistance=0
-unit.1.1.port.1.s.27.value=0
-unit.1.1.port.1.s.28.alias=unused28
-unit.1.1.port.1.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.28.name=AsyncOut[28]
-unit.1.1.port.1.s.28.orderindex=-1
-unit.1.1.port.1.s.28.visible=1
-unit.1.1.port.1.s.28.display=1
-unit.1.1.port.1.s.28.persistance=0
-unit.1.1.port.1.s.28.value=0
-unit.1.1.port.1.s.29.alias=unused29
-unit.1.1.port.1.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.29.name=AsyncOut[29]
-unit.1.1.port.1.s.29.orderindex=-1
-unit.1.1.port.1.s.29.visible=1
-unit.1.1.port.1.s.29.display=1
-unit.1.1.port.1.s.29.persistance=0
-unit.1.1.port.1.s.29.value=0
-unit.1.1.port.1.s.30.alias=unused30
-unit.1.1.port.1.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.1.s.30.name=AsyncOut[30]
-unit.1.1.port.1.s.30.orderindex=-1
-unit.1.1.port.1.s.30.visible=1
-unit.1.1.port.1.s.30.display=1
-unit.1.1.port.1.s.30.persistance=0
-unit.1.1.port.1.s.30.value=0
-unit.1.1.port.2.buscount=0
-unit.1.1.port.2.channelcount=0
-unit.1.1.port.2.buscount=0
-unit.1.1.port.2.channelcount=32
-unit.1.1.port.2.s.0.alias=unused0
-unit.1.1.port.2.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.0.name=SyncOut[0]
-unit.1.1.port.2.s.0.orderindex=-1
-unit.1.1.port.2.s.0.visible=1
-unit.1.1.port.2.s.0.display=1
-unit.1.1.port.2.s.0.persistance=0
-unit.1.1.port.2.s.0.value=0
-unit.1.1.port.2.s.1.alias=unused1
-unit.1.1.port.2.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.1.name=SyncOut[1]
-unit.1.1.port.2.s.1.orderindex=-1
-unit.1.1.port.2.s.1.visible=1
-unit.1.1.port.2.s.1.display=1
-unit.1.1.port.2.s.1.persistance=0
-unit.1.1.port.2.s.1.value=0
-unit.1.1.port.2.s.2.alias=unused2
-unit.1.1.port.2.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.2.name=SyncOut[2]
-unit.1.1.port.2.s.2.orderindex=-1
-unit.1.1.port.2.s.2.visible=1
-unit.1.1.port.2.s.2.display=1
-unit.1.1.port.2.s.2.persistance=0
-unit.1.1.port.2.s.2.value=0
-unit.1.1.port.2.s.3.alias=unused3
-unit.1.1.port.2.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.3.name=SyncOut[3]
-unit.1.1.port.2.s.3.orderindex=-1
-unit.1.1.port.2.s.3.visible=1
-unit.1.1.port.2.s.3.display=1
-unit.1.1.port.2.s.3.persistance=0
-unit.1.1.port.2.s.3.value=0
-unit.1.1.port.2.s.4.alias=unused4
-unit.1.1.port.2.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.4.name=SyncOut[4]
-unit.1.1.port.2.s.4.orderindex=-1
-unit.1.1.port.2.s.4.visible=1
-unit.1.1.port.2.s.4.display=1
-unit.1.1.port.2.s.4.persistance=0
-unit.1.1.port.2.s.4.value=0
-unit.1.1.port.2.s.5.alias=unused5
-unit.1.1.port.2.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.5.name=SyncOut[5]
-unit.1.1.port.2.s.5.orderindex=-1
-unit.1.1.port.2.s.5.visible=1
-unit.1.1.port.2.s.5.display=1
-unit.1.1.port.2.s.5.persistance=0
-unit.1.1.port.2.s.5.value=0
-unit.1.1.port.2.s.6.alias=unused6
-unit.1.1.port.2.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.6.name=SyncOut[6]
-unit.1.1.port.2.s.6.orderindex=-1
-unit.1.1.port.2.s.6.visible=1
-unit.1.1.port.2.s.6.display=1
-unit.1.1.port.2.s.6.persistance=0
-unit.1.1.port.2.s.6.value=0
-unit.1.1.port.2.s.7.alias=unused7
-unit.1.1.port.2.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.7.name=SyncOut[7]
-unit.1.1.port.2.s.7.orderindex=-1
-unit.1.1.port.2.s.7.visible=1
-unit.1.1.port.2.s.7.display=1
-unit.1.1.port.2.s.7.persistance=0
-unit.1.1.port.2.s.7.value=0
-unit.1.1.port.2.s.8.alias=unused8
-unit.1.1.port.2.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.8.name=SyncOut[8]
-unit.1.1.port.2.s.8.orderindex=-1
-unit.1.1.port.2.s.8.visible=1
-unit.1.1.port.2.s.8.display=1
-unit.1.1.port.2.s.8.persistance=0
-unit.1.1.port.2.s.8.value=0
-unit.1.1.port.2.s.9.alias=unused9
-unit.1.1.port.2.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.9.name=SyncOut[9]
-unit.1.1.port.2.s.9.orderindex=-1
-unit.1.1.port.2.s.9.visible=1
-unit.1.1.port.2.s.9.display=1
-unit.1.1.port.2.s.9.persistance=0
-unit.1.1.port.2.s.9.value=0
-unit.1.1.port.2.s.10.alias=unused10
-unit.1.1.port.2.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.10.name=SyncOut[10]
-unit.1.1.port.2.s.10.orderindex=-1
-unit.1.1.port.2.s.10.visible=1
-unit.1.1.port.2.s.10.display=1
-unit.1.1.port.2.s.10.persistance=0
-unit.1.1.port.2.s.10.value=0
-unit.1.1.port.2.s.11.alias=unused11
-unit.1.1.port.2.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.11.name=SyncOut[11]
-unit.1.1.port.2.s.11.orderindex=-1
-unit.1.1.port.2.s.11.visible=1
-unit.1.1.port.2.s.11.display=1
-unit.1.1.port.2.s.11.persistance=0
-unit.1.1.port.2.s.11.value=0
-unit.1.1.port.2.s.12.alias=unused12
-unit.1.1.port.2.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.12.name=SyncOut[12]
-unit.1.1.port.2.s.12.orderindex=-1
-unit.1.1.port.2.s.12.visible=1
-unit.1.1.port.2.s.12.display=1
-unit.1.1.port.2.s.12.persistance=0
-unit.1.1.port.2.s.12.value=0
-unit.1.1.port.2.s.13.alias=unused13
-unit.1.1.port.2.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.13.name=SyncOut[13]
-unit.1.1.port.2.s.13.orderindex=-1
-unit.1.1.port.2.s.13.visible=1
-unit.1.1.port.2.s.13.display=1
-unit.1.1.port.2.s.13.persistance=0
-unit.1.1.port.2.s.13.value=0
-unit.1.1.port.2.s.14.alias=unused14
-unit.1.1.port.2.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.14.name=SyncOut[14]
-unit.1.1.port.2.s.14.orderindex=-1
-unit.1.1.port.2.s.14.visible=1
-unit.1.1.port.2.s.14.display=1
-unit.1.1.port.2.s.14.persistance=0
-unit.1.1.port.2.s.14.value=0
-unit.1.1.port.2.s.15.alias=unused15
-unit.1.1.port.2.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.15.name=SyncOut[15]
-unit.1.1.port.2.s.15.orderindex=-1
-unit.1.1.port.2.s.15.visible=1
-unit.1.1.port.2.s.15.display=1
-unit.1.1.port.2.s.15.persistance=0
-unit.1.1.port.2.s.15.value=0
-unit.1.1.port.2.s.16.alias=unused16
-unit.1.1.port.2.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.16.name=SyncOut[16]
-unit.1.1.port.2.s.16.orderindex=-1
-unit.1.1.port.2.s.16.visible=1
-unit.1.1.port.2.s.16.display=1
-unit.1.1.port.2.s.16.persistance=0
-unit.1.1.port.2.s.16.value=0
-unit.1.1.port.2.s.17.alias=unused17
-unit.1.1.port.2.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.17.name=SyncOut[17]
-unit.1.1.port.2.s.17.orderindex=-1
-unit.1.1.port.2.s.17.visible=1
-unit.1.1.port.2.s.17.display=1
-unit.1.1.port.2.s.17.persistance=0
-unit.1.1.port.2.s.17.value=0
-unit.1.1.port.2.s.18.alias=unused18
-unit.1.1.port.2.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.18.name=SyncOut[18]
-unit.1.1.port.2.s.18.orderindex=-1
-unit.1.1.port.2.s.18.visible=1
-unit.1.1.port.2.s.18.display=1
-unit.1.1.port.2.s.18.persistance=0
-unit.1.1.port.2.s.18.value=0
-unit.1.1.port.2.s.19.alias=unused19
-unit.1.1.port.2.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.19.name=SyncOut[19]
-unit.1.1.port.2.s.19.orderindex=-1
-unit.1.1.port.2.s.19.visible=1
-unit.1.1.port.2.s.19.display=1
-unit.1.1.port.2.s.19.persistance=0
-unit.1.1.port.2.s.19.value=0
-unit.1.1.port.2.s.20.alias=unused20
-unit.1.1.port.2.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.20.name=SyncOut[20]
-unit.1.1.port.2.s.20.orderindex=-1
-unit.1.1.port.2.s.20.visible=1
-unit.1.1.port.2.s.20.display=1
-unit.1.1.port.2.s.20.persistance=0
-unit.1.1.port.2.s.20.value=0
-unit.1.1.port.2.s.21.alias=unused21
-unit.1.1.port.2.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.21.name=SyncOut[21]
-unit.1.1.port.2.s.21.orderindex=-1
-unit.1.1.port.2.s.21.visible=1
-unit.1.1.port.2.s.21.display=1
-unit.1.1.port.2.s.21.persistance=0
-unit.1.1.port.2.s.21.value=0
-unit.1.1.port.2.s.22.alias=unused22
-unit.1.1.port.2.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.22.name=SyncOut[22]
-unit.1.1.port.2.s.22.orderindex=-1
-unit.1.1.port.2.s.22.visible=1
-unit.1.1.port.2.s.22.display=1
-unit.1.1.port.2.s.22.persistance=0
-unit.1.1.port.2.s.22.value=0
-unit.1.1.port.2.s.23.alias=unused23
-unit.1.1.port.2.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.23.name=SyncOut[23]
-unit.1.1.port.2.s.23.orderindex=-1
-unit.1.1.port.2.s.23.visible=1
-unit.1.1.port.2.s.23.display=1
-unit.1.1.port.2.s.23.persistance=0
-unit.1.1.port.2.s.23.value=0
-unit.1.1.port.2.s.24.alias=unused24
-unit.1.1.port.2.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.24.name=SyncOut[24]
-unit.1.1.port.2.s.24.orderindex=-1
-unit.1.1.port.2.s.24.visible=1
-unit.1.1.port.2.s.24.display=1
-unit.1.1.port.2.s.24.persistance=0
-unit.1.1.port.2.s.24.value=0
-unit.1.1.port.2.s.25.alias=unused25
-unit.1.1.port.2.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.25.name=SyncOut[25]
-unit.1.1.port.2.s.25.orderindex=-1
-unit.1.1.port.2.s.25.visible=1
-unit.1.1.port.2.s.25.display=1
-unit.1.1.port.2.s.25.persistance=0
-unit.1.1.port.2.s.25.value=0
-unit.1.1.port.2.s.26.alias=unused26
-unit.1.1.port.2.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.26.name=SyncOut[26]
-unit.1.1.port.2.s.26.orderindex=-1
-unit.1.1.port.2.s.26.visible=1
-unit.1.1.port.2.s.26.display=1
-unit.1.1.port.2.s.26.persistance=0
-unit.1.1.port.2.s.26.value=0
-unit.1.1.port.2.s.27.alias=unused27
-unit.1.1.port.2.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.27.name=SyncOut[27]
-unit.1.1.port.2.s.27.orderindex=-1
-unit.1.1.port.2.s.27.visible=1
-unit.1.1.port.2.s.27.display=1
-unit.1.1.port.2.s.27.persistance=0
-unit.1.1.port.2.s.27.value=0
-unit.1.1.port.2.s.28.alias=unused28
-unit.1.1.port.2.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.28.name=SyncOut[28]
-unit.1.1.port.2.s.28.orderindex=-1
-unit.1.1.port.2.s.28.visible=1
-unit.1.1.port.2.s.28.display=1
-unit.1.1.port.2.s.28.persistance=0
-unit.1.1.port.2.s.28.value=0
-unit.1.1.port.2.s.29.alias=unused29
-unit.1.1.port.2.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.29.name=SyncOut[29]
-unit.1.1.port.2.s.29.orderindex=-1
-unit.1.1.port.2.s.29.visible=1
-unit.1.1.port.2.s.29.display=1
-unit.1.1.port.2.s.29.persistance=0
-unit.1.1.port.2.s.29.value=0
-unit.1.1.port.2.s.30.alias=unused30
-unit.1.1.port.2.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.30.name=SyncOut[30]
-unit.1.1.port.2.s.30.orderindex=-1
-unit.1.1.port.2.s.30.visible=1
-unit.1.1.port.2.s.30.display=1
-unit.1.1.port.2.s.30.persistance=0
-unit.1.1.port.2.s.30.value=0
-unit.1.1.port.2.s.31.alias=unused31
-unit.1.1.port.2.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.1.port.2.s.31.name=SyncOut[31]
-unit.1.1.port.2.s.31.orderindex=-1
-unit.1.1.port.2.s.31.visible=1
-unit.1.1.port.2.s.31.display=1
-unit.1.1.port.2.s.31.persistance=0
-unit.1.1.port.2.s.31.value=0
-unit.1.1.port.3.buscount=0
-unit.1.1.port.3.channelcount=0
-unit.1.1.vio.count=4
-unit.1.1.vio.posn.0.channel=31
-unit.1.1.vio.posn.0.name=DataPort[31]
-unit.1.1.vio.posn.0.port=-1
-unit.1.1.vio.posn.0.type=signal
-unit.1.1.vio.posn.1.channel=30
-unit.1.1.vio.posn.1.name=DataPort[30]
-unit.1.1.vio.posn.1.port=-1
-unit.1.1.vio.posn.1.type=signal
-unit.1.1.vio.posn.2.name=txdlyalignmonitor
-unit.1.1.vio.posn.2.channel=2147483646
-unit.1.1.vio.posn.2.type=bus
-unit.1.1.vio.posn.2.radix=0
-unit.1.1.vio.posn.2.port=-1
-unit.1.1.vio.posn.3.channel=31
-unit.1.1.vio.posn.3.name=DataPort[31]
-unit.1.1.vio.posn.3.port=1
-unit.1.1.vio.posn.3.type=signal
-unit.1.1.vio.readperiod=0
-unit.1.2.6.HEIGHT6=0.3133998
-unit.1.2.6.WIDTH6=0.35989717
-unit.1.2.6.X6=0.6426735
-unit.1.2.6.Y6=0.0
-unit.1.2.coretype=VIO
-unit.1.2.portcount=3
-unit.1.2.username=MYVIO2
-unit.1.2.port.-1.b.0.alias=rxdlyalignmonitor
-unit.1.2.port.-1.b.0.channellist=22 23 24 25 26 27 28 29
-unit.1.2.port.-1.b.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.b.0.name=rxdlyalignmonitor
-unit.1.2.port.-1.b.0.orderindex=-1
-unit.1.2.port.-1.b.0.radix=Hex
-unit.1.2.port.-1.b.0.signedOffset=0.0
-unit.1.2.port.-1.b.0.signedPrecision=0
-unit.1.2.port.-1.b.0.signedScaleFactor=1.0
-unit.1.2.port.-1.b.0.tokencount=0
-unit.1.2.port.-1.b.0.unsignedOffset=0.0
-unit.1.2.port.-1.b.0.unsignedPrecision=0
-unit.1.2.port.-1.b.0.unsignedScaleFactor=1.0
-unit.1.2.port.-1.b.0.visible=1
-unit.1.2.port.-1.b.0.display=0
-unit.1.2.port.-1.b.0.value=00000000
-unit.1.2.port.-1.buscount=1
-unit.1.2.port.-1.channelcount=32
-unit.1.2.port.-1.s.31.alias=rxplllkdet
-unit.1.2.port.-1.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.31.name=AsyncIn[31]
-unit.1.2.port.-1.s.31.orderindex=-1
-unit.1.2.port.-1.s.31.visible=1
-unit.1.2.port.-1.s.31.display=14
-unit.1.2.port.-1.s.31.persistance=0
-unit.1.2.port.-1.s.31.value=0
-unit.1.2.port.-1.s.30.alias=rxresetdone
-unit.1.2.port.-1.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.30.name=AsyncIn[30]
-unit.1.2.port.-1.s.30.orderindex=-1
-unit.1.2.port.-1.s.30.visible=1
-unit.1.2.port.-1.s.30.display=14
-unit.1.2.port.-1.s.30.persistance=0
-unit.1.2.port.-1.s.30.value=0
-unit.1.2.port.-1.s.29.alias=rxdlyalignmonitor[7]
-unit.1.2.port.-1.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.29.name=AsyncIn[29]
-unit.1.2.port.-1.s.29.orderindex=-1
-unit.1.2.port.-1.s.29.visible=1
-unit.1.2.port.-1.s.29.display=0
-unit.1.2.port.-1.s.29.persistance=0
-unit.1.2.port.-1.s.29.value=0
-unit.1.2.port.-1.s.28.alias=rxdlyalignmonitor[6]
-unit.1.2.port.-1.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.28.name=AsyncIn[28]
-unit.1.2.port.-1.s.28.orderindex=-1
-unit.1.2.port.-1.s.28.visible=1
-unit.1.2.port.-1.s.28.display=0
-unit.1.2.port.-1.s.28.persistance=0
-unit.1.2.port.-1.s.28.value=0
-unit.1.2.port.-1.s.27.alias=rxdlyalignmonitor[5]
-unit.1.2.port.-1.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.27.name=AsyncIn[27]
-unit.1.2.port.-1.s.27.orderindex=-1
-unit.1.2.port.-1.s.27.visible=1
-unit.1.2.port.-1.s.27.display=0
-unit.1.2.port.-1.s.27.persistance=0
-unit.1.2.port.-1.s.27.value=0
-unit.1.2.port.-1.s.26.alias=rxdlyalignmonitor[4]
-unit.1.2.port.-1.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.26.name=AsyncIn[26]
-unit.1.2.port.-1.s.26.orderindex=-1
-unit.1.2.port.-1.s.26.visible=1
-unit.1.2.port.-1.s.26.display=0
-unit.1.2.port.-1.s.26.persistance=0
-unit.1.2.port.-1.s.26.value=0
-unit.1.2.port.-1.s.25.alias=rxdlyalignmonitor[3]
-unit.1.2.port.-1.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.25.name=AsyncIn[25]
-unit.1.2.port.-1.s.25.orderindex=-1
-unit.1.2.port.-1.s.25.visible=1
-unit.1.2.port.-1.s.25.display=0
-unit.1.2.port.-1.s.25.persistance=0
-unit.1.2.port.-1.s.25.value=0
-unit.1.2.port.-1.s.24.alias=rxdlyalignmonitor[2]
-unit.1.2.port.-1.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.24.name=AsyncIn[24]
-unit.1.2.port.-1.s.24.orderindex=-1
-unit.1.2.port.-1.s.24.visible=1
-unit.1.2.port.-1.s.24.display=0
-unit.1.2.port.-1.s.24.persistance=0
-unit.1.2.port.-1.s.24.value=0
-unit.1.2.port.-1.s.23.alias=rxdlyalignmonitor[1]
-unit.1.2.port.-1.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.23.name=AsyncIn[23]
-unit.1.2.port.-1.s.23.orderindex=-1
-unit.1.2.port.-1.s.23.visible=1
-unit.1.2.port.-1.s.23.display=0
-unit.1.2.port.-1.s.23.persistance=0
-unit.1.2.port.-1.s.23.value=0
-unit.1.2.port.-1.s.22.alias=rxdlyalignmonitor[0]
-unit.1.2.port.-1.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.22.name=AsyncIn[22]
-unit.1.2.port.-1.s.22.orderindex=-1
-unit.1.2.port.-1.s.22.visible=1
-unit.1.2.port.-1.s.22.display=0
-unit.1.2.port.-1.s.22.persistance=0
-unit.1.2.port.-1.s.22.value=0
-unit.1.2.port.-1.s.0.alias=unused0
-unit.1.2.port.-1.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.0.name=AsyncIn[0]
-unit.1.2.port.-1.s.0.orderindex=-1
-unit.1.2.port.-1.s.0.visible=1
-unit.1.2.port.-1.s.0.display=14
-unit.1.2.port.-1.s.0.persistance=0
-unit.1.2.port.-1.s.0.value=0
-unit.1.2.port.-1.s.1.alias=unused1
-unit.1.2.port.-1.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.1.name=AsyncIn[1]
-unit.1.2.port.-1.s.1.orderindex=-1
-unit.1.2.port.-1.s.1.visible=1
-unit.1.2.port.-1.s.1.display=14
-unit.1.2.port.-1.s.1.persistance=0
-unit.1.2.port.-1.s.1.value=0
-unit.1.2.port.-1.s.2.alias=unused2
-unit.1.2.port.-1.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.2.name=AsyncIn[2]
-unit.1.2.port.-1.s.2.orderindex=-1
-unit.1.2.port.-1.s.2.visible=1
-unit.1.2.port.-1.s.2.display=14
-unit.1.2.port.-1.s.2.persistance=0
-unit.1.2.port.-1.s.2.value=0
-unit.1.2.port.-1.s.3.alias=unused3
-unit.1.2.port.-1.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.3.name=AsyncIn[3]
-unit.1.2.port.-1.s.3.orderindex=-1
-unit.1.2.port.-1.s.3.visible=1
-unit.1.2.port.-1.s.3.display=14
-unit.1.2.port.-1.s.3.persistance=0
-unit.1.2.port.-1.s.3.value=0
-unit.1.2.port.-1.s.4.alias=unused4
-unit.1.2.port.-1.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.4.name=AsyncIn[4]
-unit.1.2.port.-1.s.4.orderindex=-1
-unit.1.2.port.-1.s.4.visible=1
-unit.1.2.port.-1.s.4.display=14
-unit.1.2.port.-1.s.4.persistance=0
-unit.1.2.port.-1.s.4.value=0
-unit.1.2.port.-1.s.5.alias=unused5
-unit.1.2.port.-1.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.5.name=AsyncIn[5]
-unit.1.2.port.-1.s.5.orderindex=-1
-unit.1.2.port.-1.s.5.visible=1
-unit.1.2.port.-1.s.5.display=14
-unit.1.2.port.-1.s.5.persistance=0
-unit.1.2.port.-1.s.5.value=0
-unit.1.2.port.-1.s.6.alias=unused6
-unit.1.2.port.-1.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.6.name=AsyncIn[6]
-unit.1.2.port.-1.s.6.orderindex=-1
-unit.1.2.port.-1.s.6.visible=1
-unit.1.2.port.-1.s.6.display=14
-unit.1.2.port.-1.s.6.persistance=0
-unit.1.2.port.-1.s.6.value=0
-unit.1.2.port.-1.s.7.alias=unused7
-unit.1.2.port.-1.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.7.name=AsyncIn[7]
-unit.1.2.port.-1.s.7.orderindex=-1
-unit.1.2.port.-1.s.7.visible=1
-unit.1.2.port.-1.s.7.display=14
-unit.1.2.port.-1.s.7.persistance=0
-unit.1.2.port.-1.s.7.value=0
-unit.1.2.port.-1.s.8.alias=unused8
-unit.1.2.port.-1.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.8.name=AsyncIn[8]
-unit.1.2.port.-1.s.8.orderindex=-1
-unit.1.2.port.-1.s.8.visible=1
-unit.1.2.port.-1.s.8.display=14
-unit.1.2.port.-1.s.8.persistance=0
-unit.1.2.port.-1.s.8.value=0
-unit.1.2.port.-1.s.9.alias=unused9
-unit.1.2.port.-1.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.9.name=AsyncIn[9]
-unit.1.2.port.-1.s.9.orderindex=-1
-unit.1.2.port.-1.s.9.visible=1
-unit.1.2.port.-1.s.9.display=14
-unit.1.2.port.-1.s.9.persistance=0
-unit.1.2.port.-1.s.9.value=0
-unit.1.2.port.-1.s.10.alias=unused10
-unit.1.2.port.-1.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.10.name=AsyncIn[10]
-unit.1.2.port.-1.s.10.orderindex=-1
-unit.1.2.port.-1.s.10.visible=1
-unit.1.2.port.-1.s.10.display=14
-unit.1.2.port.-1.s.10.persistance=0
-unit.1.2.port.-1.s.10.value=0
-unit.1.2.port.-1.s.11.alias=unused11
-unit.1.2.port.-1.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.11.name=AsyncIn[11]
-unit.1.2.port.-1.s.11.orderindex=-1
-unit.1.2.port.-1.s.11.visible=1
-unit.1.2.port.-1.s.11.display=14
-unit.1.2.port.-1.s.11.persistance=0
-unit.1.2.port.-1.s.11.value=0
-unit.1.2.port.-1.s.12.alias=unused12
-unit.1.2.port.-1.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.12.name=AsyncIn[12]
-unit.1.2.port.-1.s.12.orderindex=-1
-unit.1.2.port.-1.s.12.visible=1
-unit.1.2.port.-1.s.12.display=14
-unit.1.2.port.-1.s.12.persistance=0
-unit.1.2.port.-1.s.12.value=0
-unit.1.2.port.-1.s.13.alias=unused13
-unit.1.2.port.-1.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.13.name=AsyncIn[13]
-unit.1.2.port.-1.s.13.orderindex=-1
-unit.1.2.port.-1.s.13.visible=1
-unit.1.2.port.-1.s.13.display=14
-unit.1.2.port.-1.s.13.persistance=0
-unit.1.2.port.-1.s.13.value=0
-unit.1.2.port.-1.s.14.alias=unused14
-unit.1.2.port.-1.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.14.name=AsyncIn[14]
-unit.1.2.port.-1.s.14.orderindex=-1
-unit.1.2.port.-1.s.14.visible=1
-unit.1.2.port.-1.s.14.display=14
-unit.1.2.port.-1.s.14.persistance=0
-unit.1.2.port.-1.s.14.value=0
-unit.1.2.port.-1.s.15.alias=unused15
-unit.1.2.port.-1.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.15.name=AsyncIn[15]
-unit.1.2.port.-1.s.15.orderindex=-1
-unit.1.2.port.-1.s.15.visible=1
-unit.1.2.port.-1.s.15.display=14
-unit.1.2.port.-1.s.15.persistance=0
-unit.1.2.port.-1.s.15.value=0
-unit.1.2.port.-1.s.16.alias=unused16
-unit.1.2.port.-1.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.16.name=AsyncIn[16]
-unit.1.2.port.-1.s.16.orderindex=-1
-unit.1.2.port.-1.s.16.visible=1
-unit.1.2.port.-1.s.16.display=14
-unit.1.2.port.-1.s.16.persistance=0
-unit.1.2.port.-1.s.16.value=0
-unit.1.2.port.-1.s.17.alias=unused17
-unit.1.2.port.-1.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.17.name=AsyncIn[17]
-unit.1.2.port.-1.s.17.orderindex=-1
-unit.1.2.port.-1.s.17.visible=1
-unit.1.2.port.-1.s.17.display=14
-unit.1.2.port.-1.s.17.persistance=0
-unit.1.2.port.-1.s.17.value=0
-unit.1.2.port.-1.s.18.alias=unused18
-unit.1.2.port.-1.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.18.name=AsyncIn[18]
-unit.1.2.port.-1.s.18.orderindex=-1
-unit.1.2.port.-1.s.18.visible=1
-unit.1.2.port.-1.s.18.display=14
-unit.1.2.port.-1.s.18.persistance=0
-unit.1.2.port.-1.s.18.value=0
-unit.1.2.port.-1.s.19.alias=unused19
-unit.1.2.port.-1.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.19.name=AsyncIn[19]
-unit.1.2.port.-1.s.19.orderindex=-1
-unit.1.2.port.-1.s.19.visible=1
-unit.1.2.port.-1.s.19.display=14
-unit.1.2.port.-1.s.19.persistance=0
-unit.1.2.port.-1.s.19.value=0
-unit.1.2.port.-1.s.20.alias=unused20
-unit.1.2.port.-1.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.20.name=AsyncIn[20]
-unit.1.2.port.-1.s.20.orderindex=-1
-unit.1.2.port.-1.s.20.visible=1
-unit.1.2.port.-1.s.20.display=14
-unit.1.2.port.-1.s.20.persistance=0
-unit.1.2.port.-1.s.20.value=0
-unit.1.2.port.-1.s.21.alias=unused21
-unit.1.2.port.-1.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.-1.s.21.name=AsyncIn[21]
-unit.1.2.port.-1.s.21.orderindex=-1
-unit.1.2.port.-1.s.21.visible=1
-unit.1.2.port.-1.s.21.display=14
-unit.1.2.port.-1.s.21.persistance=0
-unit.1.2.port.-1.s.21.value=0
-unit.1.2.port.0.buscount=0
-unit.1.2.port.0.channelcount=0
-unit.1.2.port.0.buscount=0
-unit.1.2.port.0.channelcount=32
-unit.1.2.port.0.s.0.alias=unused0
-unit.1.2.port.0.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.0.name=SyncIn[0]
-unit.1.2.port.0.s.0.orderindex=-1
-unit.1.2.port.0.s.0.visible=1
-unit.1.2.port.0.s.0.display=14
-unit.1.2.port.0.s.0.persistance=0
-unit.1.2.port.0.s.0.value=0
-unit.1.2.port.0.s.1.alias=unused1
-unit.1.2.port.0.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.1.name=SyncIn[1]
-unit.1.2.port.0.s.1.orderindex=-1
-unit.1.2.port.0.s.1.visible=1
-unit.1.2.port.0.s.1.display=14
-unit.1.2.port.0.s.1.persistance=0
-unit.1.2.port.0.s.1.value=0
-unit.1.2.port.0.s.2.alias=unused2
-unit.1.2.port.0.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.2.name=SyncIn[2]
-unit.1.2.port.0.s.2.orderindex=-1
-unit.1.2.port.0.s.2.visible=1
-unit.1.2.port.0.s.2.display=14
-unit.1.2.port.0.s.2.persistance=0
-unit.1.2.port.0.s.2.value=0
-unit.1.2.port.0.s.3.alias=unused3
-unit.1.2.port.0.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.3.name=SyncIn[3]
-unit.1.2.port.0.s.3.orderindex=-1
-unit.1.2.port.0.s.3.visible=1
-unit.1.2.port.0.s.3.display=14
-unit.1.2.port.0.s.3.persistance=0
-unit.1.2.port.0.s.3.value=0
-unit.1.2.port.0.s.4.alias=unused4
-unit.1.2.port.0.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.4.name=SyncIn[4]
-unit.1.2.port.0.s.4.orderindex=-1
-unit.1.2.port.0.s.4.visible=1
-unit.1.2.port.0.s.4.display=14
-unit.1.2.port.0.s.4.persistance=0
-unit.1.2.port.0.s.4.value=0
-unit.1.2.port.0.s.5.alias=unused5
-unit.1.2.port.0.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.5.name=SyncIn[5]
-unit.1.2.port.0.s.5.orderindex=-1
-unit.1.2.port.0.s.5.visible=1
-unit.1.2.port.0.s.5.display=14
-unit.1.2.port.0.s.5.persistance=0
-unit.1.2.port.0.s.5.value=0
-unit.1.2.port.0.s.6.alias=unused6
-unit.1.2.port.0.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.6.name=SyncIn[6]
-unit.1.2.port.0.s.6.orderindex=-1
-unit.1.2.port.0.s.6.visible=1
-unit.1.2.port.0.s.6.display=14
-unit.1.2.port.0.s.6.persistance=0
-unit.1.2.port.0.s.6.value=0
-unit.1.2.port.0.s.7.alias=unused7
-unit.1.2.port.0.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.7.name=SyncIn[7]
-unit.1.2.port.0.s.7.orderindex=-1
-unit.1.2.port.0.s.7.visible=1
-unit.1.2.port.0.s.7.display=14
-unit.1.2.port.0.s.7.persistance=0
-unit.1.2.port.0.s.7.value=0
-unit.1.2.port.0.s.8.alias=unused8
-unit.1.2.port.0.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.8.name=SyncIn[8]
-unit.1.2.port.0.s.8.orderindex=-1
-unit.1.2.port.0.s.8.visible=1
-unit.1.2.port.0.s.8.display=14
-unit.1.2.port.0.s.8.persistance=0
-unit.1.2.port.0.s.8.value=0
-unit.1.2.port.0.s.9.alias=unused9
-unit.1.2.port.0.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.9.name=SyncIn[9]
-unit.1.2.port.0.s.9.orderindex=-1
-unit.1.2.port.0.s.9.visible=1
-unit.1.2.port.0.s.9.display=14
-unit.1.2.port.0.s.9.persistance=0
-unit.1.2.port.0.s.9.value=0
-unit.1.2.port.0.s.10.alias=unused10
-unit.1.2.port.0.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.10.name=SyncIn[10]
-unit.1.2.port.0.s.10.orderindex=-1
-unit.1.2.port.0.s.10.visible=1
-unit.1.2.port.0.s.10.display=14
-unit.1.2.port.0.s.10.persistance=0
-unit.1.2.port.0.s.10.value=0
-unit.1.2.port.0.s.11.alias=unused11
-unit.1.2.port.0.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.11.name=SyncIn[11]
-unit.1.2.port.0.s.11.orderindex=-1
-unit.1.2.port.0.s.11.visible=1
-unit.1.2.port.0.s.11.display=14
-unit.1.2.port.0.s.11.persistance=0
-unit.1.2.port.0.s.11.value=0
-unit.1.2.port.0.s.12.alias=unused12
-unit.1.2.port.0.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.12.name=SyncIn[12]
-unit.1.2.port.0.s.12.orderindex=-1
-unit.1.2.port.0.s.12.visible=1
-unit.1.2.port.0.s.12.display=14
-unit.1.2.port.0.s.12.persistance=0
-unit.1.2.port.0.s.12.value=0
-unit.1.2.port.0.s.13.alias=unused13
-unit.1.2.port.0.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.13.name=SyncIn[13]
-unit.1.2.port.0.s.13.orderindex=-1
-unit.1.2.port.0.s.13.visible=1
-unit.1.2.port.0.s.13.display=14
-unit.1.2.port.0.s.13.persistance=0
-unit.1.2.port.0.s.13.value=0
-unit.1.2.port.0.s.14.alias=unused14
-unit.1.2.port.0.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.14.name=SyncIn[14]
-unit.1.2.port.0.s.14.orderindex=-1
-unit.1.2.port.0.s.14.visible=1
-unit.1.2.port.0.s.14.display=14
-unit.1.2.port.0.s.14.persistance=0
-unit.1.2.port.0.s.14.value=0
-unit.1.2.port.0.s.15.alias=unused15
-unit.1.2.port.0.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.15.name=SyncIn[15]
-unit.1.2.port.0.s.15.orderindex=-1
-unit.1.2.port.0.s.15.visible=1
-unit.1.2.port.0.s.15.display=14
-unit.1.2.port.0.s.15.persistance=0
-unit.1.2.port.0.s.15.value=0
-unit.1.2.port.0.s.16.alias=unused16
-unit.1.2.port.0.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.16.name=SyncIn[16]
-unit.1.2.port.0.s.16.orderindex=-1
-unit.1.2.port.0.s.16.visible=1
-unit.1.2.port.0.s.16.display=14
-unit.1.2.port.0.s.16.persistance=0
-unit.1.2.port.0.s.16.value=0
-unit.1.2.port.0.s.17.alias=unused17
-unit.1.2.port.0.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.17.name=SyncIn[17]
-unit.1.2.port.0.s.17.orderindex=-1
-unit.1.2.port.0.s.17.visible=1
-unit.1.2.port.0.s.17.display=14
-unit.1.2.port.0.s.17.persistance=0
-unit.1.2.port.0.s.17.value=0
-unit.1.2.port.0.s.18.alias=unused18
-unit.1.2.port.0.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.18.name=SyncIn[18]
-unit.1.2.port.0.s.18.orderindex=-1
-unit.1.2.port.0.s.18.visible=1
-unit.1.2.port.0.s.18.display=14
-unit.1.2.port.0.s.18.persistance=0
-unit.1.2.port.0.s.18.value=0
-unit.1.2.port.0.s.19.alias=unused19
-unit.1.2.port.0.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.19.name=SyncIn[19]
-unit.1.2.port.0.s.19.orderindex=-1
-unit.1.2.port.0.s.19.visible=1
-unit.1.2.port.0.s.19.display=14
-unit.1.2.port.0.s.19.persistance=0
-unit.1.2.port.0.s.19.value=0
-unit.1.2.port.0.s.20.alias=unused20
-unit.1.2.port.0.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.20.name=SyncIn[20]
-unit.1.2.port.0.s.20.orderindex=-1
-unit.1.2.port.0.s.20.visible=1
-unit.1.2.port.0.s.20.display=14
-unit.1.2.port.0.s.20.persistance=0
-unit.1.2.port.0.s.20.value=0
-unit.1.2.port.0.s.21.alias=unused21
-unit.1.2.port.0.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.21.name=SyncIn[21]
-unit.1.2.port.0.s.21.orderindex=-1
-unit.1.2.port.0.s.21.visible=1
-unit.1.2.port.0.s.21.display=14
-unit.1.2.port.0.s.21.persistance=0
-unit.1.2.port.0.s.21.value=0
-unit.1.2.port.0.s.22.alias=unused22
-unit.1.2.port.0.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.22.name=SyncIn[22]
-unit.1.2.port.0.s.22.orderindex=-1
-unit.1.2.port.0.s.22.visible=1
-unit.1.2.port.0.s.22.display=14
-unit.1.2.port.0.s.22.persistance=0
-unit.1.2.port.0.s.22.value=0
-unit.1.2.port.0.s.23.alias=unused23
-unit.1.2.port.0.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.23.name=SyncIn[23]
-unit.1.2.port.0.s.23.orderindex=-1
-unit.1.2.port.0.s.23.visible=1
-unit.1.2.port.0.s.23.display=14
-unit.1.2.port.0.s.23.persistance=0
-unit.1.2.port.0.s.23.value=0
-unit.1.2.port.0.s.24.alias=unused24
-unit.1.2.port.0.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.24.name=SyncIn[24]
-unit.1.2.port.0.s.24.orderindex=-1
-unit.1.2.port.0.s.24.visible=1
-unit.1.2.port.0.s.24.display=14
-unit.1.2.port.0.s.24.persistance=0
-unit.1.2.port.0.s.24.value=0
-unit.1.2.port.0.s.25.alias=unused25
-unit.1.2.port.0.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.25.name=SyncIn[25]
-unit.1.2.port.0.s.25.orderindex=-1
-unit.1.2.port.0.s.25.visible=1
-unit.1.2.port.0.s.25.display=14
-unit.1.2.port.0.s.25.persistance=0
-unit.1.2.port.0.s.25.value=0
-unit.1.2.port.0.s.26.alias=unused26
-unit.1.2.port.0.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.26.name=SyncIn[26]
-unit.1.2.port.0.s.26.orderindex=-1
-unit.1.2.port.0.s.26.visible=1
-unit.1.2.port.0.s.26.display=14
-unit.1.2.port.0.s.26.persistance=0
-unit.1.2.port.0.s.26.value=0
-unit.1.2.port.0.s.27.alias=unused27
-unit.1.2.port.0.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.27.name=SyncIn[27]
-unit.1.2.port.0.s.27.orderindex=-1
-unit.1.2.port.0.s.27.visible=1
-unit.1.2.port.0.s.27.display=14
-unit.1.2.port.0.s.27.persistance=0
-unit.1.2.port.0.s.27.value=0
-unit.1.2.port.0.s.28.alias=unused28
-unit.1.2.port.0.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.28.name=SyncIn[28]
-unit.1.2.port.0.s.28.orderindex=-1
-unit.1.2.port.0.s.28.visible=1
-unit.1.2.port.0.s.28.display=14
-unit.1.2.port.0.s.28.persistance=0
-unit.1.2.port.0.s.28.value=0
-unit.1.2.port.0.s.29.alias=unused29
-unit.1.2.port.0.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.29.name=SyncIn[29]
-unit.1.2.port.0.s.29.orderindex=-1
-unit.1.2.port.0.s.29.visible=1
-unit.1.2.port.0.s.29.display=14
-unit.1.2.port.0.s.29.persistance=0
-unit.1.2.port.0.s.29.value=0
-unit.1.2.port.0.s.30.alias=unused30
-unit.1.2.port.0.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.30.name=SyncIn[30]
-unit.1.2.port.0.s.30.orderindex=-1
-unit.1.2.port.0.s.30.visible=1
-unit.1.2.port.0.s.30.display=14
-unit.1.2.port.0.s.30.persistance=0
-unit.1.2.port.0.s.30.value=0
-unit.1.2.port.0.s.31.alias=unused31
-unit.1.2.port.0.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.0.s.31.name=SyncIn[31]
-unit.1.2.port.0.s.31.orderindex=-1
-unit.1.2.port.0.s.31.visible=1
-unit.1.2.port.0.s.31.display=14
-unit.1.2.port.0.s.31.persistance=0
-unit.1.2.port.0.s.31.value=0
-unit.1.2.port.1.buscount=0
-unit.1.2.port.1.channelcount=0
-unit.1.2.port.1.buscount=0
-unit.1.2.port.1.channelcount=32
-unit.1.2.port.1.s.31.alias=pllrxreset
-unit.1.2.port.1.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.31.name=AsyncOut[31]
-unit.1.2.port.1.s.31.orderindex=-1
-unit.1.2.port.1.s.31.visible=1
-unit.1.2.port.1.s.31.display=1
-unit.1.2.port.1.s.31.persistance=0
-unit.1.2.port.1.s.31.value=0
-unit.1.2.port.1.s.30.alias=rxcdrreset
-unit.1.2.port.1.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.30.name=AsyncOut[30]
-unit.1.2.port.1.s.30.orderindex=-1
-unit.1.2.port.1.s.30.visible=1
-unit.1.2.port.1.s.30.display=1
-unit.1.2.port.1.s.30.persistance=0
-unit.1.2.port.1.s.30.value=0
-unit.1.2.port.1.s.29.alias=rxdlyalignoverride
-unit.1.2.port.1.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.29.name=AsyncOut[29]
-unit.1.2.port.1.s.29.orderindex=-1
-unit.1.2.port.1.s.29.visible=1
-unit.1.2.port.1.s.29.display=1
-unit.1.2.port.1.s.29.persistance=0
-unit.1.2.port.1.s.29.value=0
-unit.1.2.port.1.s.0.alias=unused0
-unit.1.2.port.1.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.0.name=AsyncOut[0]
-unit.1.2.port.1.s.0.orderindex=-1
-unit.1.2.port.1.s.0.visible=1
-unit.1.2.port.1.s.0.display=1
-unit.1.2.port.1.s.0.persistance=0
-unit.1.2.port.1.s.0.value=0
-unit.1.2.port.1.s.1.alias=unused1
-unit.1.2.port.1.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.1.name=AsyncOut[1]
-unit.1.2.port.1.s.1.orderindex=-1
-unit.1.2.port.1.s.1.visible=1
-unit.1.2.port.1.s.1.display=1
-unit.1.2.port.1.s.1.persistance=0
-unit.1.2.port.1.s.1.value=0
-unit.1.2.port.1.s.2.alias=unused2
-unit.1.2.port.1.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.2.name=AsyncOut[2]
-unit.1.2.port.1.s.2.orderindex=-1
-unit.1.2.port.1.s.2.visible=1
-unit.1.2.port.1.s.2.display=1
-unit.1.2.port.1.s.2.persistance=0
-unit.1.2.port.1.s.2.value=0
-unit.1.2.port.1.s.3.alias=unused3
-unit.1.2.port.1.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.3.name=AsyncOut[3]
-unit.1.2.port.1.s.3.orderindex=-1
-unit.1.2.port.1.s.3.visible=1
-unit.1.2.port.1.s.3.display=1
-unit.1.2.port.1.s.3.persistance=0
-unit.1.2.port.1.s.3.value=0
-unit.1.2.port.1.s.4.alias=unused4
-unit.1.2.port.1.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.4.name=AsyncOut[4]
-unit.1.2.port.1.s.4.orderindex=-1
-unit.1.2.port.1.s.4.visible=1
-unit.1.2.port.1.s.4.display=1
-unit.1.2.port.1.s.4.persistance=0
-unit.1.2.port.1.s.4.value=0
-unit.1.2.port.1.s.5.alias=unused5
-unit.1.2.port.1.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.5.name=AsyncOut[5]
-unit.1.2.port.1.s.5.orderindex=-1
-unit.1.2.port.1.s.5.visible=1
-unit.1.2.port.1.s.5.display=1
-unit.1.2.port.1.s.5.persistance=0
-unit.1.2.port.1.s.5.value=0
-unit.1.2.port.1.s.6.alias=unused6
-unit.1.2.port.1.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.6.name=AsyncOut[6]
-unit.1.2.port.1.s.6.orderindex=-1
-unit.1.2.port.1.s.6.visible=1
-unit.1.2.port.1.s.6.display=1
-unit.1.2.port.1.s.6.persistance=0
-unit.1.2.port.1.s.6.value=0
-unit.1.2.port.1.s.7.alias=unused7
-unit.1.2.port.1.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.7.name=AsyncOut[7]
-unit.1.2.port.1.s.7.orderindex=-1
-unit.1.2.port.1.s.7.visible=1
-unit.1.2.port.1.s.7.display=1
-unit.1.2.port.1.s.7.persistance=0
-unit.1.2.port.1.s.7.value=0
-unit.1.2.port.1.s.8.alias=unused8
-unit.1.2.port.1.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.8.name=AsyncOut[8]
-unit.1.2.port.1.s.8.orderindex=-1
-unit.1.2.port.1.s.8.visible=1
-unit.1.2.port.1.s.8.display=1
-unit.1.2.port.1.s.8.persistance=0
-unit.1.2.port.1.s.8.value=0
-unit.1.2.port.1.s.9.alias=unused9
-unit.1.2.port.1.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.9.name=AsyncOut[9]
-unit.1.2.port.1.s.9.orderindex=-1
-unit.1.2.port.1.s.9.visible=1
-unit.1.2.port.1.s.9.display=1
-unit.1.2.port.1.s.9.persistance=0
-unit.1.2.port.1.s.9.value=0
-unit.1.2.port.1.s.10.alias=unused10
-unit.1.2.port.1.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.10.name=AsyncOut[10]
-unit.1.2.port.1.s.10.orderindex=-1
-unit.1.2.port.1.s.10.visible=1
-unit.1.2.port.1.s.10.display=1
-unit.1.2.port.1.s.10.persistance=0
-unit.1.2.port.1.s.10.value=0
-unit.1.2.port.1.s.11.alias=unused11
-unit.1.2.port.1.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.11.name=AsyncOut[11]
-unit.1.2.port.1.s.11.orderindex=-1
-unit.1.2.port.1.s.11.visible=1
-unit.1.2.port.1.s.11.display=1
-unit.1.2.port.1.s.11.persistance=0
-unit.1.2.port.1.s.11.value=0
-unit.1.2.port.1.s.12.alias=unused12
-unit.1.2.port.1.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.12.name=AsyncOut[12]
-unit.1.2.port.1.s.12.orderindex=-1
-unit.1.2.port.1.s.12.visible=1
-unit.1.2.port.1.s.12.display=1
-unit.1.2.port.1.s.12.persistance=0
-unit.1.2.port.1.s.12.value=0
-unit.1.2.port.1.s.13.alias=unused13
-unit.1.2.port.1.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.13.name=AsyncOut[13]
-unit.1.2.port.1.s.13.orderindex=-1
-unit.1.2.port.1.s.13.visible=1
-unit.1.2.port.1.s.13.display=1
-unit.1.2.port.1.s.13.persistance=0
-unit.1.2.port.1.s.13.value=0
-unit.1.2.port.1.s.14.alias=unused14
-unit.1.2.port.1.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.14.name=AsyncOut[14]
-unit.1.2.port.1.s.14.orderindex=-1
-unit.1.2.port.1.s.14.visible=1
-unit.1.2.port.1.s.14.display=1
-unit.1.2.port.1.s.14.persistance=0
-unit.1.2.port.1.s.14.value=0
-unit.1.2.port.1.s.15.alias=unused15
-unit.1.2.port.1.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.15.name=AsyncOut[15]
-unit.1.2.port.1.s.15.orderindex=-1
-unit.1.2.port.1.s.15.visible=1
-unit.1.2.port.1.s.15.display=1
-unit.1.2.port.1.s.15.persistance=0
-unit.1.2.port.1.s.15.value=0
-unit.1.2.port.1.s.16.alias=unused16
-unit.1.2.port.1.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.16.name=AsyncOut[16]
-unit.1.2.port.1.s.16.orderindex=-1
-unit.1.2.port.1.s.16.visible=1
-unit.1.2.port.1.s.16.display=1
-unit.1.2.port.1.s.16.persistance=0
-unit.1.2.port.1.s.16.value=0
-unit.1.2.port.1.s.17.alias=unused17
-unit.1.2.port.1.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.17.name=AsyncOut[17]
-unit.1.2.port.1.s.17.orderindex=-1
-unit.1.2.port.1.s.17.visible=1
-unit.1.2.port.1.s.17.display=1
-unit.1.2.port.1.s.17.persistance=0
-unit.1.2.port.1.s.17.value=0
-unit.1.2.port.1.s.18.alias=unused18
-unit.1.2.port.1.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.18.name=AsyncOut[18]
-unit.1.2.port.1.s.18.orderindex=-1
-unit.1.2.port.1.s.18.visible=1
-unit.1.2.port.1.s.18.display=1
-unit.1.2.port.1.s.18.persistance=0
-unit.1.2.port.1.s.18.value=0
-unit.1.2.port.1.s.19.alias=unused19
-unit.1.2.port.1.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.19.name=AsyncOut[19]
-unit.1.2.port.1.s.19.orderindex=-1
-unit.1.2.port.1.s.19.visible=1
-unit.1.2.port.1.s.19.display=1
-unit.1.2.port.1.s.19.persistance=0
-unit.1.2.port.1.s.19.value=0
-unit.1.2.port.1.s.20.alias=unused20
-unit.1.2.port.1.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.20.name=AsyncOut[20]
-unit.1.2.port.1.s.20.orderindex=-1
-unit.1.2.port.1.s.20.visible=1
-unit.1.2.port.1.s.20.display=1
-unit.1.2.port.1.s.20.persistance=0
-unit.1.2.port.1.s.20.value=0
-unit.1.2.port.1.s.21.alias=unused21
-unit.1.2.port.1.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.21.name=AsyncOut[21]
-unit.1.2.port.1.s.21.orderindex=-1
-unit.1.2.port.1.s.21.visible=1
-unit.1.2.port.1.s.21.display=1
-unit.1.2.port.1.s.21.persistance=0
-unit.1.2.port.1.s.21.value=0
-unit.1.2.port.1.s.22.alias=unused22
-unit.1.2.port.1.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.22.name=AsyncOut[22]
-unit.1.2.port.1.s.22.orderindex=-1
-unit.1.2.port.1.s.22.visible=1
-unit.1.2.port.1.s.22.display=1
-unit.1.2.port.1.s.22.persistance=0
-unit.1.2.port.1.s.22.value=0
-unit.1.2.port.1.s.23.alias=unused23
-unit.1.2.port.1.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.23.name=AsyncOut[23]
-unit.1.2.port.1.s.23.orderindex=-1
-unit.1.2.port.1.s.23.visible=1
-unit.1.2.port.1.s.23.display=1
-unit.1.2.port.1.s.23.persistance=0
-unit.1.2.port.1.s.23.value=0
-unit.1.2.port.1.s.24.alias=unused24
-unit.1.2.port.1.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.24.name=AsyncOut[24]
-unit.1.2.port.1.s.24.orderindex=-1
-unit.1.2.port.1.s.24.visible=1
-unit.1.2.port.1.s.24.display=1
-unit.1.2.port.1.s.24.persistance=0
-unit.1.2.port.1.s.24.value=0
-unit.1.2.port.1.s.25.alias=unused25
-unit.1.2.port.1.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.25.name=AsyncOut[25]
-unit.1.2.port.1.s.25.orderindex=-1
-unit.1.2.port.1.s.25.visible=1
-unit.1.2.port.1.s.25.display=1
-unit.1.2.port.1.s.25.persistance=0
-unit.1.2.port.1.s.25.value=0
-unit.1.2.port.1.s.26.alias=unused26
-unit.1.2.port.1.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.26.name=AsyncOut[26]
-unit.1.2.port.1.s.26.orderindex=-1
-unit.1.2.port.1.s.26.visible=1
-unit.1.2.port.1.s.26.display=1
-unit.1.2.port.1.s.26.persistance=0
-unit.1.2.port.1.s.26.value=0
-unit.1.2.port.1.s.27.alias=unused27
-unit.1.2.port.1.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.27.name=AsyncOut[27]
-unit.1.2.port.1.s.27.orderindex=-1
-unit.1.2.port.1.s.27.visible=1
-unit.1.2.port.1.s.27.display=1
-unit.1.2.port.1.s.27.persistance=0
-unit.1.2.port.1.s.27.value=0
-unit.1.2.port.1.s.28.alias=unused28
-unit.1.2.port.1.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.1.s.28.name=AsyncOut[28]
-unit.1.2.port.1.s.28.orderindex=-1
-unit.1.2.port.1.s.28.visible=1
-unit.1.2.port.1.s.28.display=1
-unit.1.2.port.1.s.28.persistance=0
-unit.1.2.port.1.s.28.value=0
-unit.1.2.port.2.buscount=0
-unit.1.2.port.2.channelcount=0
-unit.1.2.port.2.buscount=0
-unit.1.2.port.2.channelcount=32
-unit.1.2.port.2.s.0.alias=unused0
-unit.1.2.port.2.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.0.name=SyncOut[0]
-unit.1.2.port.2.s.0.orderindex=-1
-unit.1.2.port.2.s.0.visible=1
-unit.1.2.port.2.s.0.display=1
-unit.1.2.port.2.s.0.persistance=0
-unit.1.2.port.2.s.0.value=0
-unit.1.2.port.2.s.1.alias=unused1
-unit.1.2.port.2.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.1.name=SyncOut[1]
-unit.1.2.port.2.s.1.orderindex=-1
-unit.1.2.port.2.s.1.visible=1
-unit.1.2.port.2.s.1.display=1
-unit.1.2.port.2.s.1.persistance=0
-unit.1.2.port.2.s.1.value=0
-unit.1.2.port.2.s.2.alias=unused2
-unit.1.2.port.2.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.2.name=SyncOut[2]
-unit.1.2.port.2.s.2.orderindex=-1
-unit.1.2.port.2.s.2.visible=1
-unit.1.2.port.2.s.2.display=1
-unit.1.2.port.2.s.2.persistance=0
-unit.1.2.port.2.s.2.value=0
-unit.1.2.port.2.s.3.alias=unused3
-unit.1.2.port.2.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.3.name=SyncOut[3]
-unit.1.2.port.2.s.3.orderindex=-1
-unit.1.2.port.2.s.3.visible=1
-unit.1.2.port.2.s.3.display=1
-unit.1.2.port.2.s.3.persistance=0
-unit.1.2.port.2.s.3.value=0
-unit.1.2.port.2.s.4.alias=unused4
-unit.1.2.port.2.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.4.name=SyncOut[4]
-unit.1.2.port.2.s.4.orderindex=-1
-unit.1.2.port.2.s.4.visible=1
-unit.1.2.port.2.s.4.display=1
-unit.1.2.port.2.s.4.persistance=0
-unit.1.2.port.2.s.4.value=0
-unit.1.2.port.2.s.5.alias=unused5
-unit.1.2.port.2.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.5.name=SyncOut[5]
-unit.1.2.port.2.s.5.orderindex=-1
-unit.1.2.port.2.s.5.visible=1
-unit.1.2.port.2.s.5.display=1
-unit.1.2.port.2.s.5.persistance=0
-unit.1.2.port.2.s.5.value=0
-unit.1.2.port.2.s.6.alias=unused6
-unit.1.2.port.2.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.6.name=SyncOut[6]
-unit.1.2.port.2.s.6.orderindex=-1
-unit.1.2.port.2.s.6.visible=1
-unit.1.2.port.2.s.6.display=1
-unit.1.2.port.2.s.6.persistance=0
-unit.1.2.port.2.s.6.value=0
-unit.1.2.port.2.s.7.alias=unused7
-unit.1.2.port.2.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.7.name=SyncOut[7]
-unit.1.2.port.2.s.7.orderindex=-1
-unit.1.2.port.2.s.7.visible=1
-unit.1.2.port.2.s.7.display=1
-unit.1.2.port.2.s.7.persistance=0
-unit.1.2.port.2.s.7.value=0
-unit.1.2.port.2.s.8.alias=unused8
-unit.1.2.port.2.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.8.name=SyncOut[8]
-unit.1.2.port.2.s.8.orderindex=-1
-unit.1.2.port.2.s.8.visible=1
-unit.1.2.port.2.s.8.display=1
-unit.1.2.port.2.s.8.persistance=0
-unit.1.2.port.2.s.8.value=0
-unit.1.2.port.2.s.9.alias=unused9
-unit.1.2.port.2.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.9.name=SyncOut[9]
-unit.1.2.port.2.s.9.orderindex=-1
-unit.1.2.port.2.s.9.visible=1
-unit.1.2.port.2.s.9.display=1
-unit.1.2.port.2.s.9.persistance=0
-unit.1.2.port.2.s.9.value=0
-unit.1.2.port.2.s.10.alias=unused10
-unit.1.2.port.2.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.10.name=SyncOut[10]
-unit.1.2.port.2.s.10.orderindex=-1
-unit.1.2.port.2.s.10.visible=1
-unit.1.2.port.2.s.10.display=1
-unit.1.2.port.2.s.10.persistance=0
-unit.1.2.port.2.s.10.value=0
-unit.1.2.port.2.s.11.alias=unused11
-unit.1.2.port.2.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.11.name=SyncOut[11]
-unit.1.2.port.2.s.11.orderindex=-1
-unit.1.2.port.2.s.11.visible=1
-unit.1.2.port.2.s.11.display=1
-unit.1.2.port.2.s.11.persistance=0
-unit.1.2.port.2.s.11.value=0
-unit.1.2.port.2.s.12.alias=unused12
-unit.1.2.port.2.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.12.name=SyncOut[12]
-unit.1.2.port.2.s.12.orderindex=-1
-unit.1.2.port.2.s.12.visible=1
-unit.1.2.port.2.s.12.display=1
-unit.1.2.port.2.s.12.persistance=0
-unit.1.2.port.2.s.12.value=0
-unit.1.2.port.2.s.13.alias=unused13
-unit.1.2.port.2.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.13.name=SyncOut[13]
-unit.1.2.port.2.s.13.orderindex=-1
-unit.1.2.port.2.s.13.visible=1
-unit.1.2.port.2.s.13.display=1
-unit.1.2.port.2.s.13.persistance=0
-unit.1.2.port.2.s.13.value=0
-unit.1.2.port.2.s.14.alias=unused14
-unit.1.2.port.2.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.14.name=SyncOut[14]
-unit.1.2.port.2.s.14.orderindex=-1
-unit.1.2.port.2.s.14.visible=1
-unit.1.2.port.2.s.14.display=1
-unit.1.2.port.2.s.14.persistance=0
-unit.1.2.port.2.s.14.value=0
-unit.1.2.port.2.s.15.alias=unused15
-unit.1.2.port.2.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.15.name=SyncOut[15]
-unit.1.2.port.2.s.15.orderindex=-1
-unit.1.2.port.2.s.15.visible=1
-unit.1.2.port.2.s.15.display=1
-unit.1.2.port.2.s.15.persistance=0
-unit.1.2.port.2.s.15.value=0
-unit.1.2.port.2.s.16.alias=unused16
-unit.1.2.port.2.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.16.name=SyncOut[16]
-unit.1.2.port.2.s.16.orderindex=-1
-unit.1.2.port.2.s.16.visible=1
-unit.1.2.port.2.s.16.display=1
-unit.1.2.port.2.s.16.persistance=0
-unit.1.2.port.2.s.16.value=0
-unit.1.2.port.2.s.17.alias=unused17
-unit.1.2.port.2.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.17.name=SyncOut[17]
-unit.1.2.port.2.s.17.orderindex=-1
-unit.1.2.port.2.s.17.visible=1
-unit.1.2.port.2.s.17.display=1
-unit.1.2.port.2.s.17.persistance=0
-unit.1.2.port.2.s.17.value=0
-unit.1.2.port.2.s.18.alias=unused18
-unit.1.2.port.2.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.18.name=SyncOut[18]
-unit.1.2.port.2.s.18.orderindex=-1
-unit.1.2.port.2.s.18.visible=1
-unit.1.2.port.2.s.18.display=1
-unit.1.2.port.2.s.18.persistance=0
-unit.1.2.port.2.s.18.value=0
-unit.1.2.port.2.s.19.alias=unused19
-unit.1.2.port.2.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.19.name=SyncOut[19]
-unit.1.2.port.2.s.19.orderindex=-1
-unit.1.2.port.2.s.19.visible=1
-unit.1.2.port.2.s.19.display=1
-unit.1.2.port.2.s.19.persistance=0
-unit.1.2.port.2.s.19.value=0
-unit.1.2.port.2.s.20.alias=unused20
-unit.1.2.port.2.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.20.name=SyncOut[20]
-unit.1.2.port.2.s.20.orderindex=-1
-unit.1.2.port.2.s.20.visible=1
-unit.1.2.port.2.s.20.display=1
-unit.1.2.port.2.s.20.persistance=0
-unit.1.2.port.2.s.20.value=0
-unit.1.2.port.2.s.21.alias=unused21
-unit.1.2.port.2.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.21.name=SyncOut[21]
-unit.1.2.port.2.s.21.orderindex=-1
-unit.1.2.port.2.s.21.visible=1
-unit.1.2.port.2.s.21.display=1
-unit.1.2.port.2.s.21.persistance=0
-unit.1.2.port.2.s.21.value=0
-unit.1.2.port.2.s.22.alias=unused22
-unit.1.2.port.2.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.22.name=SyncOut[22]
-unit.1.2.port.2.s.22.orderindex=-1
-unit.1.2.port.2.s.22.visible=1
-unit.1.2.port.2.s.22.display=1
-unit.1.2.port.2.s.22.persistance=0
-unit.1.2.port.2.s.22.value=0
-unit.1.2.port.2.s.23.alias=unused23
-unit.1.2.port.2.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.23.name=SyncOut[23]
-unit.1.2.port.2.s.23.orderindex=-1
-unit.1.2.port.2.s.23.visible=1
-unit.1.2.port.2.s.23.display=1
-unit.1.2.port.2.s.23.persistance=0
-unit.1.2.port.2.s.23.value=0
-unit.1.2.port.2.s.24.alias=unused24
-unit.1.2.port.2.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.24.name=SyncOut[24]
-unit.1.2.port.2.s.24.orderindex=-1
-unit.1.2.port.2.s.24.visible=1
-unit.1.2.port.2.s.24.display=1
-unit.1.2.port.2.s.24.persistance=0
-unit.1.2.port.2.s.24.value=0
-unit.1.2.port.2.s.25.alias=unused25
-unit.1.2.port.2.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.25.name=SyncOut[25]
-unit.1.2.port.2.s.25.orderindex=-1
-unit.1.2.port.2.s.25.visible=1
-unit.1.2.port.2.s.25.display=1
-unit.1.2.port.2.s.25.persistance=0
-unit.1.2.port.2.s.25.value=0
-unit.1.2.port.2.s.26.alias=unused26
-unit.1.2.port.2.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.26.name=SyncOut[26]
-unit.1.2.port.2.s.26.orderindex=-1
-unit.1.2.port.2.s.26.visible=1
-unit.1.2.port.2.s.26.display=1
-unit.1.2.port.2.s.26.persistance=0
-unit.1.2.port.2.s.26.value=0
-unit.1.2.port.2.s.27.alias=unused27
-unit.1.2.port.2.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.27.name=SyncOut[27]
-unit.1.2.port.2.s.27.orderindex=-1
-unit.1.2.port.2.s.27.visible=1
-unit.1.2.port.2.s.27.display=1
-unit.1.2.port.2.s.27.persistance=0
-unit.1.2.port.2.s.27.value=0
-unit.1.2.port.2.s.28.alias=unused28
-unit.1.2.port.2.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.28.name=SyncOut[28]
-unit.1.2.port.2.s.28.orderindex=-1
-unit.1.2.port.2.s.28.visible=1
-unit.1.2.port.2.s.28.display=1
-unit.1.2.port.2.s.28.persistance=0
-unit.1.2.port.2.s.28.value=0
-unit.1.2.port.2.s.29.alias=unused29
-unit.1.2.port.2.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.29.name=SyncOut[29]
-unit.1.2.port.2.s.29.orderindex=-1
-unit.1.2.port.2.s.29.visible=1
-unit.1.2.port.2.s.29.display=1
-unit.1.2.port.2.s.29.persistance=0
-unit.1.2.port.2.s.29.value=0
-unit.1.2.port.2.s.30.alias=unused30
-unit.1.2.port.2.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.30.name=SyncOut[30]
-unit.1.2.port.2.s.30.orderindex=-1
-unit.1.2.port.2.s.30.visible=1
-unit.1.2.port.2.s.30.display=1
-unit.1.2.port.2.s.30.persistance=0
-unit.1.2.port.2.s.30.value=0
-unit.1.2.port.2.s.31.alias=unused31
-unit.1.2.port.2.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.2.port.2.s.31.name=SyncOut[31]
-unit.1.2.port.2.s.31.orderindex=-1
-unit.1.2.port.2.s.31.visible=1
-unit.1.2.port.2.s.31.display=1
-unit.1.2.port.2.s.31.persistance=0
-unit.1.2.port.2.s.31.value=0
-unit.1.2.port.3.buscount=0
-unit.1.2.port.3.channelcount=0
-unit.1.2.vio.count=6
-unit.1.2.vio.posn.0.channel=31
-unit.1.2.vio.posn.0.name=DataPort[31]
-unit.1.2.vio.posn.0.port=-1
-unit.1.2.vio.posn.0.type=signal
-unit.1.2.vio.posn.1.channel=30
-unit.1.2.vio.posn.1.name=DataPort[30]
-unit.1.2.vio.posn.1.port=-1
-unit.1.2.vio.posn.1.type=signal
-unit.1.2.vio.posn.2.name=rxdlyalignmonitor
-unit.1.2.vio.posn.2.channel=2147483646
-unit.1.2.vio.posn.2.type=bus
-unit.1.2.vio.posn.2.radix=0
-unit.1.2.vio.posn.2.port=-1
-unit.1.2.vio.posn.3.channel=31
-unit.1.2.vio.posn.3.name=DataPort[31]
-unit.1.2.vio.posn.3.port=1
-unit.1.2.vio.posn.3.type=signal
-unit.1.2.vio.posn.4.channel=30
-unit.1.2.vio.posn.4.name=DataPort[30]
-unit.1.2.vio.posn.4.port=1
-unit.1.2.vio.posn.4.type=signal
-unit.1.2.vio.posn.5.channel=29
-unit.1.2.vio.posn.5.name=DataPort[29]
-unit.1.2.vio.posn.5.port=1
-unit.1.2.vio.posn.5.type=signal
-unit.1.2.vio.readperiod=0
-unit.1.3.0.HEIGHT0=0.43632337
-unit.1.3.0.TriggerRow0=1
-unit.1.3.0.TriggerRow1=1
-unit.1.3.0.TriggerRow2=1
-unit.1.3.0.WIDTH0=1.0012796
-unit.1.3.0.X0=0.0012795905
-unit.1.3.0.Y0=0.56478405
-unit.1.3.1.HEIGHT1=0.5769657
-unit.1.3.1.WIDTH1=0.9980806
-unit.1.3.1.X1=0.0019193857
-unit.1.3.1.Y1=0.31007752
-unit.1.3.MFBitsA0=XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-unit.1.3.MFBitsB0=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-unit.1.3.MFCompareA0=0
-unit.1.3.MFCompareB0=999
-unit.1.3.MFCount=1
-unit.1.3.MFDisplay0=0
-unit.1.3.MFEventType0=3
-unit.1.3.SQCondition=All Data
-unit.1.3.SQContiguous0=0
-unit.1.3.SequencerOn=0
-unit.1.3.TCActive=0
-unit.1.3.TCAdvanced0=0
-unit.1.3.TCCondition0_0=M0
-unit.1.3.TCCondition0_1=
-unit.1.3.TCConditionType0=0
-unit.1.3.TCCount=1
-unit.1.3.TCEventCount0=1
-unit.1.3.TCEventType0=3
-unit.1.3.TCName0=TriggerCondition0
-unit.1.3.TCOutputEnable0=0
-unit.1.3.TCOutputHigh0=1
-unit.1.3.TCOutputMode0=0
-unit.1.3.browser_tree_state<Data\ Port>=1
-unit.1.3.coretype=ILA
-unit.1.3.eventCount0=1
-unit.1.3.username=MYILA3
-unit.1.3.port.-1.b.0.alias=rxdata
-unit.1.3.port.-1.b.0.channellist=74 75 76 77 78 79 80 81
-unit.1.3.port.-1.b.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.b.0.name=rxdata
-unit.1.3.port.-1.b.0.orderindex=-1
-unit.1.3.port.-1.b.0.radix=Hex
-unit.1.3.port.-1.b.0.signedOffset=0.0
-unit.1.3.port.-1.b.0.signedPrecision=0
-unit.1.3.port.-1.b.0.signedScaleFactor=1.0
-unit.1.3.port.-1.b.0.tokencount=0
-unit.1.3.port.-1.b.0.unsignedOffset=0.0
-unit.1.3.port.-1.b.0.unsignedPrecision=0
-unit.1.3.port.-1.b.0.unsignedScaleFactor=1.0
-unit.1.3.port.-1.b.0.visible=1
-unit.1.3.port.-1.b.1.alias=rxstatus
-unit.1.3.port.-1.b.1.channellist=71 72 73
-unit.1.3.port.-1.b.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.b.1.name=rxstatus
-unit.1.3.port.-1.b.1.orderindex=-1
-unit.1.3.port.-1.b.1.radix=Hex
-unit.1.3.port.-1.b.1.signedOffset=0.0
-unit.1.3.port.-1.b.1.signedPrecision=0
-unit.1.3.port.-1.b.1.signedScaleFactor=1.0
-unit.1.3.port.-1.b.1.tokencount=0
-unit.1.3.port.-1.b.1.unsignedOffset=0.0
-unit.1.3.port.-1.b.1.unsignedPrecision=0
-unit.1.3.port.-1.b.1.unsignedScaleFactor=1.0
-unit.1.3.port.-1.b.1.visible=1
-unit.1.3.port.-1.b.2.alias=rxlossofsync
-unit.1.3.port.-1.b.2.channellist=69 70
-unit.1.3.port.-1.b.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.b.2.name=rxlossofsync
-unit.1.3.port.-1.b.2.orderindex=-1
-unit.1.3.port.-1.b.2.radix=Hex
-unit.1.3.port.-1.b.2.signedOffset=0.0
-unit.1.3.port.-1.b.2.signedPrecision=0
-unit.1.3.port.-1.b.2.signedScaleFactor=1.0
-unit.1.3.port.-1.b.2.tokencount=0
-unit.1.3.port.-1.b.2.unsignedOffset=0.0
-unit.1.3.port.-1.b.2.unsignedPrecision=0
-unit.1.3.port.-1.b.2.unsignedScaleFactor=1.0
-unit.1.3.port.-1.b.2.visible=1
-unit.1.3.port.-1.b.3.alias=error_count
-unit.1.3.port.-1.b.3.channellist=60 61 62 63 64 65 66 67
-unit.1.3.port.-1.b.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.b.3.name=error_count
-unit.1.3.port.-1.b.3.orderindex=-1
-unit.1.3.port.-1.b.3.radix=Hex
-unit.1.3.port.-1.b.3.signedOffset=0.0
-unit.1.3.port.-1.b.3.signedPrecision=0
-unit.1.3.port.-1.b.3.signedScaleFactor=1.0
-unit.1.3.port.-1.b.3.tokencount=0
-unit.1.3.port.-1.b.3.unsignedOffset=0.0
-unit.1.3.port.-1.b.3.unsignedPrecision=0
-unit.1.3.port.-1.b.3.unsignedScaleFactor=1.0
-unit.1.3.port.-1.b.3.visible=1
-unit.1.3.port.-1.buscount=4
-unit.1.3.port.-1.channelcount=85
-unit.1.3.port.-1.s.84.alias=rxcharisk
-unit.1.3.port.-1.s.84.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.84.name=DataPort[84]
-unit.1.3.port.-1.s.84.orderindex=-1
-unit.1.3.port.-1.s.84.visible=1
-unit.1.3.port.-1.s.83.alias=rxdisperr
-unit.1.3.port.-1.s.83.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.83.name=DataPort[83]
-unit.1.3.port.-1.s.83.orderindex=-1
-unit.1.3.port.-1.s.83.visible=1
-unit.1.3.port.-1.s.82.alias=rxnotintable
-unit.1.3.port.-1.s.82.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.82.name=DataPort[82]
-unit.1.3.port.-1.s.82.orderindex=-1
-unit.1.3.port.-1.s.82.visible=1
-unit.1.3.port.-1.s.81.alias=rxdata[7]
-unit.1.3.port.-1.s.81.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.81.name=DataPort[81]
-unit.1.3.port.-1.s.81.orderindex=-1
-unit.1.3.port.-1.s.81.visible=1
-unit.1.3.port.-1.s.80.alias=rxdata[6]
-unit.1.3.port.-1.s.80.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.80.name=DataPort[80]
-unit.1.3.port.-1.s.80.orderindex=-1
-unit.1.3.port.-1.s.80.visible=1
-unit.1.3.port.-1.s.79.alias=rxdata[5]
-unit.1.3.port.-1.s.79.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.79.name=DataPort[79]
-unit.1.3.port.-1.s.79.orderindex=-1
-unit.1.3.port.-1.s.79.visible=1
-unit.1.3.port.-1.s.78.alias=rxdata[4]
-unit.1.3.port.-1.s.78.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.78.name=DataPort[78]
-unit.1.3.port.-1.s.78.orderindex=-1
-unit.1.3.port.-1.s.78.visible=1
-unit.1.3.port.-1.s.77.alias=rxdata[3]
-unit.1.3.port.-1.s.77.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.77.name=DataPort[77]
-unit.1.3.port.-1.s.77.orderindex=-1
-unit.1.3.port.-1.s.77.visible=1
-unit.1.3.port.-1.s.76.alias=rxdata[2]
-unit.1.3.port.-1.s.76.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.76.name=DataPort[76]
-unit.1.3.port.-1.s.76.orderindex=-1
-unit.1.3.port.-1.s.76.visible=1
-unit.1.3.port.-1.s.75.alias=rxdata[1]
-unit.1.3.port.-1.s.75.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.75.name=DataPort[75]
-unit.1.3.port.-1.s.75.orderindex=-1
-unit.1.3.port.-1.s.75.visible=1
-unit.1.3.port.-1.s.74.alias=rxdata[0]
-unit.1.3.port.-1.s.74.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.74.name=DataPort[74]
-unit.1.3.port.-1.s.74.orderindex=-1
-unit.1.3.port.-1.s.74.visible=1
-unit.1.3.port.-1.s.73.alias=rxstatus[2]
-unit.1.3.port.-1.s.73.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.73.name=DataPort[73]
-unit.1.3.port.-1.s.73.orderindex=-1
-unit.1.3.port.-1.s.73.visible=1
-unit.1.3.port.-1.s.72.alias=rxstatus[1]
-unit.1.3.port.-1.s.72.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.72.name=DataPort[72]
-unit.1.3.port.-1.s.72.orderindex=-1
-unit.1.3.port.-1.s.72.visible=1
-unit.1.3.port.-1.s.71.alias=rxstatus[0]
-unit.1.3.port.-1.s.71.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.71.name=DataPort[71]
-unit.1.3.port.-1.s.71.orderindex=-1
-unit.1.3.port.-1.s.71.visible=1
-unit.1.3.port.-1.s.70.alias=rxlossofsync[1]
-unit.1.3.port.-1.s.70.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.70.name=DataPort[70]
-unit.1.3.port.-1.s.70.orderindex=-1
-unit.1.3.port.-1.s.70.visible=1
-unit.1.3.port.-1.s.69.alias=rxlossofsync[0]
-unit.1.3.port.-1.s.69.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.69.name=DataPort[69]
-unit.1.3.port.-1.s.69.orderindex=-1
-unit.1.3.port.-1.s.69.visible=1
-unit.1.3.port.-1.s.68.alias=phystatus
-unit.1.3.port.-1.s.68.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.68.name=DataPort[68]
-unit.1.3.port.-1.s.68.orderindex=-1
-unit.1.3.port.-1.s.68.visible=1
-unit.1.3.port.-1.s.67.alias=error_count[7]
-unit.1.3.port.-1.s.67.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.67.name=DataPort[67]
-unit.1.3.port.-1.s.67.orderindex=-1
-unit.1.3.port.-1.s.67.visible=1
-unit.1.3.port.-1.s.66.alias=error_count[6]
-unit.1.3.port.-1.s.66.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.66.name=DataPort[66]
-unit.1.3.port.-1.s.66.orderindex=-1
-unit.1.3.port.-1.s.66.visible=1
-unit.1.3.port.-1.s.65.alias=error_count[5]
-unit.1.3.port.-1.s.65.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.65.name=DataPort[65]
-unit.1.3.port.-1.s.65.orderindex=-1
-unit.1.3.port.-1.s.65.visible=1
-unit.1.3.port.-1.s.64.alias=error_count[4]
-unit.1.3.port.-1.s.64.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.64.name=DataPort[64]
-unit.1.3.port.-1.s.64.orderindex=-1
-unit.1.3.port.-1.s.64.visible=1
-unit.1.3.port.-1.s.63.alias=error_count[3]
-unit.1.3.port.-1.s.63.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.63.name=DataPort[63]
-unit.1.3.port.-1.s.63.orderindex=-1
-unit.1.3.port.-1.s.63.visible=1
-unit.1.3.port.-1.s.62.alias=error_count[2]
-unit.1.3.port.-1.s.62.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.62.name=DataPort[62]
-unit.1.3.port.-1.s.62.orderindex=-1
-unit.1.3.port.-1.s.62.visible=1
-unit.1.3.port.-1.s.61.alias=error_count[1]
-unit.1.3.port.-1.s.61.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.61.name=DataPort[61]
-unit.1.3.port.-1.s.61.orderindex=-1
-unit.1.3.port.-1.s.61.visible=1
-unit.1.3.port.-1.s.60.alias=error_count[0]
-unit.1.3.port.-1.s.60.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.60.name=DataPort[60]
-unit.1.3.port.-1.s.60.orderindex=-1
-unit.1.3.port.-1.s.60.visible=1
-unit.1.3.port.-1.s.0.alias=unused0
-unit.1.3.port.-1.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.0.name=DataPort[0]
-unit.1.3.port.-1.s.0.orderindex=-1
-unit.1.3.port.-1.s.0.visible=1
-unit.1.3.port.-1.s.1.alias=unused1
-unit.1.3.port.-1.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.1.name=DataPort[1]
-unit.1.3.port.-1.s.1.orderindex=-1
-unit.1.3.port.-1.s.1.visible=1
-unit.1.3.port.-1.s.2.alias=unused2
-unit.1.3.port.-1.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.2.name=DataPort[2]
-unit.1.3.port.-1.s.2.orderindex=-1
-unit.1.3.port.-1.s.2.visible=1
-unit.1.3.port.-1.s.3.alias=unused3
-unit.1.3.port.-1.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.3.name=DataPort[3]
-unit.1.3.port.-1.s.3.orderindex=-1
-unit.1.3.port.-1.s.3.visible=1
-unit.1.3.port.-1.s.4.alias=unused4
-unit.1.3.port.-1.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.4.name=DataPort[4]
-unit.1.3.port.-1.s.4.orderindex=-1
-unit.1.3.port.-1.s.4.visible=1
-unit.1.3.port.-1.s.5.alias=unused5
-unit.1.3.port.-1.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.5.name=DataPort[5]
-unit.1.3.port.-1.s.5.orderindex=-1
-unit.1.3.port.-1.s.5.visible=1
-unit.1.3.port.-1.s.6.alias=unused6
-unit.1.3.port.-1.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.6.name=DataPort[6]
-unit.1.3.port.-1.s.6.orderindex=-1
-unit.1.3.port.-1.s.6.visible=1
-unit.1.3.port.-1.s.7.alias=unused7
-unit.1.3.port.-1.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.7.name=DataPort[7]
-unit.1.3.port.-1.s.7.orderindex=-1
-unit.1.3.port.-1.s.7.visible=1
-unit.1.3.port.-1.s.8.alias=unused8
-unit.1.3.port.-1.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.8.name=DataPort[8]
-unit.1.3.port.-1.s.8.orderindex=-1
-unit.1.3.port.-1.s.8.visible=1
-unit.1.3.port.-1.s.9.alias=unused9
-unit.1.3.port.-1.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.9.name=DataPort[9]
-unit.1.3.port.-1.s.9.orderindex=-1
-unit.1.3.port.-1.s.9.visible=1
-unit.1.3.port.-1.s.10.alias=unused10
-unit.1.3.port.-1.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.10.name=DataPort[10]
-unit.1.3.port.-1.s.10.orderindex=-1
-unit.1.3.port.-1.s.10.visible=1
-unit.1.3.port.-1.s.11.alias=unused11
-unit.1.3.port.-1.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.11.name=DataPort[11]
-unit.1.3.port.-1.s.11.orderindex=-1
-unit.1.3.port.-1.s.11.visible=1
-unit.1.3.port.-1.s.12.alias=unused12
-unit.1.3.port.-1.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.12.name=DataPort[12]
-unit.1.3.port.-1.s.12.orderindex=-1
-unit.1.3.port.-1.s.12.visible=1
-unit.1.3.port.-1.s.13.alias=unused13
-unit.1.3.port.-1.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.13.name=DataPort[13]
-unit.1.3.port.-1.s.13.orderindex=-1
-unit.1.3.port.-1.s.13.visible=1
-unit.1.3.port.-1.s.14.alias=unused14
-unit.1.3.port.-1.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.14.name=DataPort[14]
-unit.1.3.port.-1.s.14.orderindex=-1
-unit.1.3.port.-1.s.14.visible=1
-unit.1.3.port.-1.s.15.alias=unused15
-unit.1.3.port.-1.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.15.name=DataPort[15]
-unit.1.3.port.-1.s.15.orderindex=-1
-unit.1.3.port.-1.s.15.visible=1
-unit.1.3.port.-1.s.16.alias=unused16
-unit.1.3.port.-1.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.16.name=DataPort[16]
-unit.1.3.port.-1.s.16.orderindex=-1
-unit.1.3.port.-1.s.16.visible=1
-unit.1.3.port.-1.s.17.alias=unused17
-unit.1.3.port.-1.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.17.name=DataPort[17]
-unit.1.3.port.-1.s.17.orderindex=-1
-unit.1.3.port.-1.s.17.visible=1
-unit.1.3.port.-1.s.18.alias=unused18
-unit.1.3.port.-1.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.18.name=DataPort[18]
-unit.1.3.port.-1.s.18.orderindex=-1
-unit.1.3.port.-1.s.18.visible=1
-unit.1.3.port.-1.s.19.alias=unused19
-unit.1.3.port.-1.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.19.name=DataPort[19]
-unit.1.3.port.-1.s.19.orderindex=-1
-unit.1.3.port.-1.s.19.visible=1
-unit.1.3.port.-1.s.20.alias=unused20
-unit.1.3.port.-1.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.20.name=DataPort[20]
-unit.1.3.port.-1.s.20.orderindex=-1
-unit.1.3.port.-1.s.20.visible=1
-unit.1.3.port.-1.s.21.alias=unused21
-unit.1.3.port.-1.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.21.name=DataPort[21]
-unit.1.3.port.-1.s.21.orderindex=-1
-unit.1.3.port.-1.s.21.visible=1
-unit.1.3.port.-1.s.22.alias=unused22
-unit.1.3.port.-1.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.22.name=DataPort[22]
-unit.1.3.port.-1.s.22.orderindex=-1
-unit.1.3.port.-1.s.22.visible=1
-unit.1.3.port.-1.s.23.alias=unused23
-unit.1.3.port.-1.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.23.name=DataPort[23]
-unit.1.3.port.-1.s.23.orderindex=-1
-unit.1.3.port.-1.s.23.visible=1
-unit.1.3.port.-1.s.24.alias=unused24
-unit.1.3.port.-1.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.24.name=DataPort[24]
-unit.1.3.port.-1.s.24.orderindex=-1
-unit.1.3.port.-1.s.24.visible=1
-unit.1.3.port.-1.s.25.alias=unused25
-unit.1.3.port.-1.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.25.name=DataPort[25]
-unit.1.3.port.-1.s.25.orderindex=-1
-unit.1.3.port.-1.s.25.visible=1
-unit.1.3.port.-1.s.26.alias=unused26
-unit.1.3.port.-1.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.26.name=DataPort[26]
-unit.1.3.port.-1.s.26.orderindex=-1
-unit.1.3.port.-1.s.26.visible=1
-unit.1.3.port.-1.s.27.alias=unused27
-unit.1.3.port.-1.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.27.name=DataPort[27]
-unit.1.3.port.-1.s.27.orderindex=-1
-unit.1.3.port.-1.s.27.visible=1
-unit.1.3.port.-1.s.28.alias=unused28
-unit.1.3.port.-1.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.28.name=DataPort[28]
-unit.1.3.port.-1.s.28.orderindex=-1
-unit.1.3.port.-1.s.28.visible=1
-unit.1.3.port.-1.s.29.alias=unused29
-unit.1.3.port.-1.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.29.name=DataPort[29]
-unit.1.3.port.-1.s.29.orderindex=-1
-unit.1.3.port.-1.s.29.visible=1
-unit.1.3.port.-1.s.30.alias=unused30
-unit.1.3.port.-1.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.30.name=DataPort[30]
-unit.1.3.port.-1.s.30.orderindex=-1
-unit.1.3.port.-1.s.30.visible=1
-unit.1.3.port.-1.s.31.alias=unused31
-unit.1.3.port.-1.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.31.name=DataPort[31]
-unit.1.3.port.-1.s.31.orderindex=-1
-unit.1.3.port.-1.s.31.visible=1
-unit.1.3.port.-1.s.32.alias=unused32
-unit.1.3.port.-1.s.32.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.32.name=DataPort[32]
-unit.1.3.port.-1.s.32.orderindex=-1
-unit.1.3.port.-1.s.32.visible=1
-unit.1.3.port.-1.s.33.alias=unused33
-unit.1.3.port.-1.s.33.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.33.name=DataPort[33]
-unit.1.3.port.-1.s.33.orderindex=-1
-unit.1.3.port.-1.s.33.visible=1
-unit.1.3.port.-1.s.34.alias=unused34
-unit.1.3.port.-1.s.34.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.34.name=DataPort[34]
-unit.1.3.port.-1.s.34.orderindex=-1
-unit.1.3.port.-1.s.34.visible=1
-unit.1.3.port.-1.s.35.alias=unused35
-unit.1.3.port.-1.s.35.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.35.name=DataPort[35]
-unit.1.3.port.-1.s.35.orderindex=-1
-unit.1.3.port.-1.s.35.visible=1
-unit.1.3.port.-1.s.36.alias=unused36
-unit.1.3.port.-1.s.36.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.36.name=DataPort[36]
-unit.1.3.port.-1.s.36.orderindex=-1
-unit.1.3.port.-1.s.36.visible=1
-unit.1.3.port.-1.s.37.alias=unused37
-unit.1.3.port.-1.s.37.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.37.name=DataPort[37]
-unit.1.3.port.-1.s.37.orderindex=-1
-unit.1.3.port.-1.s.37.visible=1
-unit.1.3.port.-1.s.38.alias=unused38
-unit.1.3.port.-1.s.38.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.38.name=DataPort[38]
-unit.1.3.port.-1.s.38.orderindex=-1
-unit.1.3.port.-1.s.38.visible=1
-unit.1.3.port.-1.s.39.alias=unused39
-unit.1.3.port.-1.s.39.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.39.name=DataPort[39]
-unit.1.3.port.-1.s.39.orderindex=-1
-unit.1.3.port.-1.s.39.visible=1
-unit.1.3.port.-1.s.40.alias=unused40
-unit.1.3.port.-1.s.40.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.40.name=DataPort[40]
-unit.1.3.port.-1.s.40.orderindex=-1
-unit.1.3.port.-1.s.40.visible=1
-unit.1.3.port.-1.s.41.alias=unused41
-unit.1.3.port.-1.s.41.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.41.name=DataPort[41]
-unit.1.3.port.-1.s.41.orderindex=-1
-unit.1.3.port.-1.s.41.visible=1
-unit.1.3.port.-1.s.42.alias=unused42
-unit.1.3.port.-1.s.42.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.42.name=DataPort[42]
-unit.1.3.port.-1.s.42.orderindex=-1
-unit.1.3.port.-1.s.42.visible=1
-unit.1.3.port.-1.s.43.alias=unused43
-unit.1.3.port.-1.s.43.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.43.name=DataPort[43]
-unit.1.3.port.-1.s.43.orderindex=-1
-unit.1.3.port.-1.s.43.visible=1
-unit.1.3.port.-1.s.44.alias=unused44
-unit.1.3.port.-1.s.44.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.44.name=DataPort[44]
-unit.1.3.port.-1.s.44.orderindex=-1
-unit.1.3.port.-1.s.44.visible=1
-unit.1.3.port.-1.s.45.alias=unused45
-unit.1.3.port.-1.s.45.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.45.name=DataPort[45]
-unit.1.3.port.-1.s.45.orderindex=-1
-unit.1.3.port.-1.s.45.visible=1
-unit.1.3.port.-1.s.46.alias=unused46
-unit.1.3.port.-1.s.46.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.46.name=DataPort[46]
-unit.1.3.port.-1.s.46.orderindex=-1
-unit.1.3.port.-1.s.46.visible=1
-unit.1.3.port.-1.s.47.alias=unused47
-unit.1.3.port.-1.s.47.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.47.name=DataPort[47]
-unit.1.3.port.-1.s.47.orderindex=-1
-unit.1.3.port.-1.s.47.visible=1
-unit.1.3.port.-1.s.48.alias=unused48
-unit.1.3.port.-1.s.48.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.48.name=DataPort[48]
-unit.1.3.port.-1.s.48.orderindex=-1
-unit.1.3.port.-1.s.48.visible=1
-unit.1.3.port.-1.s.49.alias=unused49
-unit.1.3.port.-1.s.49.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.49.name=DataPort[49]
-unit.1.3.port.-1.s.49.orderindex=-1
-unit.1.3.port.-1.s.49.visible=1
-unit.1.3.port.-1.s.50.alias=unused50
-unit.1.3.port.-1.s.50.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.50.name=DataPort[50]
-unit.1.3.port.-1.s.50.orderindex=-1
-unit.1.3.port.-1.s.50.visible=1
-unit.1.3.port.-1.s.51.alias=unused51
-unit.1.3.port.-1.s.51.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.51.name=DataPort[51]
-unit.1.3.port.-1.s.51.orderindex=-1
-unit.1.3.port.-1.s.51.visible=1
-unit.1.3.port.-1.s.52.alias=unused52
-unit.1.3.port.-1.s.52.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.52.name=DataPort[52]
-unit.1.3.port.-1.s.52.orderindex=-1
-unit.1.3.port.-1.s.52.visible=1
-unit.1.3.port.-1.s.53.alias=unused53
-unit.1.3.port.-1.s.53.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.53.name=DataPort[53]
-unit.1.3.port.-1.s.53.orderindex=-1
-unit.1.3.port.-1.s.53.visible=1
-unit.1.3.port.-1.s.54.alias=unused54
-unit.1.3.port.-1.s.54.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.54.name=DataPort[54]
-unit.1.3.port.-1.s.54.orderindex=-1
-unit.1.3.port.-1.s.54.visible=1
-unit.1.3.port.-1.s.55.alias=unused55
-unit.1.3.port.-1.s.55.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.55.name=DataPort[55]
-unit.1.3.port.-1.s.55.orderindex=-1
-unit.1.3.port.-1.s.55.visible=1
-unit.1.3.port.-1.s.56.alias=unused56
-unit.1.3.port.-1.s.56.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.56.name=DataPort[56]
-unit.1.3.port.-1.s.56.orderindex=-1
-unit.1.3.port.-1.s.56.visible=1
-unit.1.3.port.-1.s.57.alias=unused57
-unit.1.3.port.-1.s.57.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.57.name=DataPort[57]
-unit.1.3.port.-1.s.57.orderindex=-1
-unit.1.3.port.-1.s.57.visible=1
-unit.1.3.port.-1.s.58.alias=unused58
-unit.1.3.port.-1.s.58.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.58.name=DataPort[58]
-unit.1.3.port.-1.s.58.orderindex=-1
-unit.1.3.port.-1.s.58.visible=1
-unit.1.3.port.-1.s.59.alias=unused59
-unit.1.3.port.-1.s.59.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.-1.s.59.name=DataPort[59]
-unit.1.3.port.-1.s.59.orderindex=-1
-unit.1.3.port.-1.s.59.visible=1
-unit.1.3.port.0.b.0.alias=
-unit.1.3.port.0.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 
-unit.1.3.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
-unit.1.3.port.0.b.0.name=TriggerPort0
-unit.1.3.port.0.b.0.orderindex=-1
-unit.1.3.port.0.b.0.radix=Hex
-unit.1.3.port.0.b.0.signedOffset=0.0
-unit.1.3.port.0.b.0.signedPrecision=0
-unit.1.3.port.0.b.0.signedScaleFactor=1.0
-unit.1.3.port.0.b.0.unsignedOffset=0.0
-unit.1.3.port.0.b.0.unsignedPrecision=0
-unit.1.3.port.0.b.0.unsignedScaleFactor=1.0
-unit.1.3.port.0.b.0.visible=1
-unit.1.3.port.0.buscount=1
-unit.1.3.port.0.channelcount=85
-unit.1.3.port.0.channelcount=85
-unit.1.3.port.0.s.84.alias=rxcharisk
-unit.1.3.port.0.s.84.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.84.name=TriggerPort0[84]
-unit.1.3.port.0.s.84.orderindex=-1
-unit.1.3.port.0.s.84.visible=1
-unit.1.3.port.0.s.83.alias=rxdisperr
-unit.1.3.port.0.s.83.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.83.name=TriggerPort0[83]
-unit.1.3.port.0.s.83.orderindex=-1
-unit.1.3.port.0.s.83.visible=1
-unit.1.3.port.0.s.82.alias=rxnotintable
-unit.1.3.port.0.s.82.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.82.name=TriggerPort0[82]
-unit.1.3.port.0.s.82.orderindex=-1
-unit.1.3.port.0.s.82.visible=1
-unit.1.3.port.0.s.81.alias=rxdata[7]
-unit.1.3.port.0.s.81.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.81.name=TriggerPort0[81]
-unit.1.3.port.0.s.81.orderindex=-1
-unit.1.3.port.0.s.81.visible=1
-unit.1.3.port.0.s.80.alias=rxdata[6]
-unit.1.3.port.0.s.80.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.80.name=TriggerPort0[80]
-unit.1.3.port.0.s.80.orderindex=-1
-unit.1.3.port.0.s.80.visible=1
-unit.1.3.port.0.s.79.alias=rxdata[5]
-unit.1.3.port.0.s.79.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.79.name=TriggerPort0[79]
-unit.1.3.port.0.s.79.orderindex=-1
-unit.1.3.port.0.s.79.visible=1
-unit.1.3.port.0.s.78.alias=rxdata[4]
-unit.1.3.port.0.s.78.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.78.name=TriggerPort0[78]
-unit.1.3.port.0.s.78.orderindex=-1
-unit.1.3.port.0.s.78.visible=1
-unit.1.3.port.0.s.77.alias=rxdata[3]
-unit.1.3.port.0.s.77.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.77.name=TriggerPort0[77]
-unit.1.3.port.0.s.77.orderindex=-1
-unit.1.3.port.0.s.77.visible=1
-unit.1.3.port.0.s.76.alias=rxdata[2]
-unit.1.3.port.0.s.76.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.76.name=TriggerPort0[76]
-unit.1.3.port.0.s.76.orderindex=-1
-unit.1.3.port.0.s.76.visible=1
-unit.1.3.port.0.s.75.alias=rxdata[1]
-unit.1.3.port.0.s.75.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.75.name=TriggerPort0[75]
-unit.1.3.port.0.s.75.orderindex=-1
-unit.1.3.port.0.s.75.visible=1
-unit.1.3.port.0.s.74.alias=rxdata[0]
-unit.1.3.port.0.s.74.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.74.name=TriggerPort0[74]
-unit.1.3.port.0.s.74.orderindex=-1
-unit.1.3.port.0.s.74.visible=1
-unit.1.3.port.0.s.73.alias=rxstatus[2]
-unit.1.3.port.0.s.73.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.73.name=TriggerPort0[73]
-unit.1.3.port.0.s.73.orderindex=-1
-unit.1.3.port.0.s.73.visible=1
-unit.1.3.port.0.s.72.alias=rxstatus[1]
-unit.1.3.port.0.s.72.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.72.name=TriggerPort0[72]
-unit.1.3.port.0.s.72.orderindex=-1
-unit.1.3.port.0.s.72.visible=1
-unit.1.3.port.0.s.71.alias=rxstatus[0]
-unit.1.3.port.0.s.71.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.71.name=TriggerPort0[71]
-unit.1.3.port.0.s.71.orderindex=-1
-unit.1.3.port.0.s.71.visible=1
-unit.1.3.port.0.s.70.alias=rxlossofsync[1]
-unit.1.3.port.0.s.70.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.70.name=TriggerPort0[70]
-unit.1.3.port.0.s.70.orderindex=-1
-unit.1.3.port.0.s.70.visible=1
-unit.1.3.port.0.s.69.alias=rxlossofsync[0]
-unit.1.3.port.0.s.69.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.69.name=TriggerPort0[69]
-unit.1.3.port.0.s.69.orderindex=-1
-unit.1.3.port.0.s.69.visible=1
-unit.1.3.port.0.s.68.alias=phystatus
-unit.1.3.port.0.s.68.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.68.name=TriggerPort0[68]
-unit.1.3.port.0.s.68.orderindex=-1
-unit.1.3.port.0.s.68.visible=1
-unit.1.3.port.0.s.67.alias=error_count[7]
-unit.1.3.port.0.s.67.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.67.name=TriggerPort0[67]
-unit.1.3.port.0.s.67.orderindex=-1
-unit.1.3.port.0.s.67.visible=1
-unit.1.3.port.0.s.66.alias=error_count[6]
-unit.1.3.port.0.s.66.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.66.name=TriggerPort0[66]
-unit.1.3.port.0.s.66.orderindex=-1
-unit.1.3.port.0.s.66.visible=1
-unit.1.3.port.0.s.65.alias=error_count[5]
-unit.1.3.port.0.s.65.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.65.name=TriggerPort0[65]
-unit.1.3.port.0.s.65.orderindex=-1
-unit.1.3.port.0.s.65.visible=1
-unit.1.3.port.0.s.64.alias=error_count[4]
-unit.1.3.port.0.s.64.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.64.name=TriggerPort0[64]
-unit.1.3.port.0.s.64.orderindex=-1
-unit.1.3.port.0.s.64.visible=1
-unit.1.3.port.0.s.63.alias=error_count[3]
-unit.1.3.port.0.s.63.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.63.name=TriggerPort0[63]
-unit.1.3.port.0.s.63.orderindex=-1
-unit.1.3.port.0.s.63.visible=1
-unit.1.3.port.0.s.62.alias=error_count[2]
-unit.1.3.port.0.s.62.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.62.name=TriggerPort0[62]
-unit.1.3.port.0.s.62.orderindex=-1
-unit.1.3.port.0.s.62.visible=1
-unit.1.3.port.0.s.61.alias=error_count[1]
-unit.1.3.port.0.s.61.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.61.name=TriggerPort0[61]
-unit.1.3.port.0.s.61.orderindex=-1
-unit.1.3.port.0.s.61.visible=1
-unit.1.3.port.0.s.60.alias=error_count[0]
-unit.1.3.port.0.s.60.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.60.name=TriggerPort0[60]
-unit.1.3.port.0.s.60.orderindex=-1
-unit.1.3.port.0.s.60.visible=1
-unit.1.3.port.0.s.0.alias=unused0
-unit.1.3.port.0.s.0.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.0.name=TriggerPort0[0]
-unit.1.3.port.0.s.0.orderindex=-1
-unit.1.3.port.0.s.0.visible=1
-unit.1.3.port.0.s.1.alias=unused1
-unit.1.3.port.0.s.1.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.1.name=TriggerPort0[1]
-unit.1.3.port.0.s.1.orderindex=-1
-unit.1.3.port.0.s.1.visible=1
-unit.1.3.port.0.s.2.alias=unused2
-unit.1.3.port.0.s.2.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.2.name=TriggerPort0[2]
-unit.1.3.port.0.s.2.orderindex=-1
-unit.1.3.port.0.s.2.visible=1
-unit.1.3.port.0.s.3.alias=unused3
-unit.1.3.port.0.s.3.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.3.name=TriggerPort0[3]
-unit.1.3.port.0.s.3.orderindex=-1
-unit.1.3.port.0.s.3.visible=1
-unit.1.3.port.0.s.4.alias=unused4
-unit.1.3.port.0.s.4.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.4.name=TriggerPort0[4]
-unit.1.3.port.0.s.4.orderindex=-1
-unit.1.3.port.0.s.4.visible=1
-unit.1.3.port.0.s.5.alias=unused5
-unit.1.3.port.0.s.5.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.5.name=TriggerPort0[5]
-unit.1.3.port.0.s.5.orderindex=-1
-unit.1.3.port.0.s.5.visible=1
-unit.1.3.port.0.s.6.alias=unused6
-unit.1.3.port.0.s.6.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.6.name=TriggerPort0[6]
-unit.1.3.port.0.s.6.orderindex=-1
-unit.1.3.port.0.s.6.visible=1
-unit.1.3.port.0.s.7.alias=unused7
-unit.1.3.port.0.s.7.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.7.name=TriggerPort0[7]
-unit.1.3.port.0.s.7.orderindex=-1
-unit.1.3.port.0.s.7.visible=1
-unit.1.3.port.0.s.8.alias=unused8
-unit.1.3.port.0.s.8.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.8.name=TriggerPort0[8]
-unit.1.3.port.0.s.8.orderindex=-1
-unit.1.3.port.0.s.8.visible=1
-unit.1.3.port.0.s.9.alias=unused9
-unit.1.3.port.0.s.9.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.9.name=TriggerPort0[9]
-unit.1.3.port.0.s.9.orderindex=-1
-unit.1.3.port.0.s.9.visible=1
-unit.1.3.port.0.s.10.alias=unused10
-unit.1.3.port.0.s.10.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.10.name=TriggerPort0[10]
-unit.1.3.port.0.s.10.orderindex=-1
-unit.1.3.port.0.s.10.visible=1
-unit.1.3.port.0.s.11.alias=unused11
-unit.1.3.port.0.s.11.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.11.name=TriggerPort0[11]
-unit.1.3.port.0.s.11.orderindex=-1
-unit.1.3.port.0.s.11.visible=1
-unit.1.3.port.0.s.12.alias=unused12
-unit.1.3.port.0.s.12.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.12.name=TriggerPort0[12]
-unit.1.3.port.0.s.12.orderindex=-1
-unit.1.3.port.0.s.12.visible=1
-unit.1.3.port.0.s.13.alias=unused13
-unit.1.3.port.0.s.13.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.13.name=TriggerPort0[13]
-unit.1.3.port.0.s.13.orderindex=-1
-unit.1.3.port.0.s.13.visible=1
-unit.1.3.port.0.s.14.alias=unused14
-unit.1.3.port.0.s.14.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.14.name=TriggerPort0[14]
-unit.1.3.port.0.s.14.orderindex=-1
-unit.1.3.port.0.s.14.visible=1
-unit.1.3.port.0.s.15.alias=unused15
-unit.1.3.port.0.s.15.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.15.name=TriggerPort0[15]
-unit.1.3.port.0.s.15.orderindex=-1
-unit.1.3.port.0.s.15.visible=1
-unit.1.3.port.0.s.16.alias=unused16
-unit.1.3.port.0.s.16.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.16.name=TriggerPort0[16]
-unit.1.3.port.0.s.16.orderindex=-1
-unit.1.3.port.0.s.16.visible=1
-unit.1.3.port.0.s.17.alias=unused17
-unit.1.3.port.0.s.17.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.17.name=TriggerPort0[17]
-unit.1.3.port.0.s.17.orderindex=-1
-unit.1.3.port.0.s.17.visible=1
-unit.1.3.port.0.s.18.alias=unused18
-unit.1.3.port.0.s.18.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.18.name=TriggerPort0[18]
-unit.1.3.port.0.s.18.orderindex=-1
-unit.1.3.port.0.s.18.visible=1
-unit.1.3.port.0.s.19.alias=unused19
-unit.1.3.port.0.s.19.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.19.name=TriggerPort0[19]
-unit.1.3.port.0.s.19.orderindex=-1
-unit.1.3.port.0.s.19.visible=1
-unit.1.3.port.0.s.20.alias=unused20
-unit.1.3.port.0.s.20.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.20.name=TriggerPort0[20]
-unit.1.3.port.0.s.20.orderindex=-1
-unit.1.3.port.0.s.20.visible=1
-unit.1.3.port.0.s.21.alias=unused21
-unit.1.3.port.0.s.21.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.21.name=TriggerPort0[21]
-unit.1.3.port.0.s.21.orderindex=-1
-unit.1.3.port.0.s.21.visible=1
-unit.1.3.port.0.s.22.alias=unused22
-unit.1.3.port.0.s.22.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.22.name=TriggerPort0[22]
-unit.1.3.port.0.s.22.orderindex=-1
-unit.1.3.port.0.s.22.visible=1
-unit.1.3.port.0.s.23.alias=unused23
-unit.1.3.port.0.s.23.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.23.name=TriggerPort0[23]
-unit.1.3.port.0.s.23.orderindex=-1
-unit.1.3.port.0.s.23.visible=1
-unit.1.3.port.0.s.24.alias=unused24
-unit.1.3.port.0.s.24.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.24.name=TriggerPort0[24]
-unit.1.3.port.0.s.24.orderindex=-1
-unit.1.3.port.0.s.24.visible=1
-unit.1.3.port.0.s.25.alias=unused25
-unit.1.3.port.0.s.25.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.25.name=TriggerPort0[25]
-unit.1.3.port.0.s.25.orderindex=-1
-unit.1.3.port.0.s.25.visible=1
-unit.1.3.port.0.s.26.alias=unused26
-unit.1.3.port.0.s.26.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.26.name=TriggerPort0[26]
-unit.1.3.port.0.s.26.orderindex=-1
-unit.1.3.port.0.s.26.visible=1
-unit.1.3.port.0.s.27.alias=unused27
-unit.1.3.port.0.s.27.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.27.name=TriggerPort0[27]
-unit.1.3.port.0.s.27.orderindex=-1
-unit.1.3.port.0.s.27.visible=1
-unit.1.3.port.0.s.28.alias=unused28
-unit.1.3.port.0.s.28.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.28.name=TriggerPort0[28]
-unit.1.3.port.0.s.28.orderindex=-1
-unit.1.3.port.0.s.28.visible=1
-unit.1.3.port.0.s.29.alias=unused29
-unit.1.3.port.0.s.29.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.29.name=TriggerPort0[29]
-unit.1.3.port.0.s.29.orderindex=-1
-unit.1.3.port.0.s.29.visible=1
-unit.1.3.port.0.s.30.alias=unused30
-unit.1.3.port.0.s.30.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.30.name=TriggerPort0[30]
-unit.1.3.port.0.s.30.orderindex=-1
-unit.1.3.port.0.s.30.visible=1
-unit.1.3.port.0.s.31.alias=unused31
-unit.1.3.port.0.s.31.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.31.name=TriggerPort0[31]
-unit.1.3.port.0.s.31.orderindex=-1
-unit.1.3.port.0.s.31.visible=1
-unit.1.3.port.0.s.32.alias=unused32
-unit.1.3.port.0.s.32.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.32.name=TriggerPort0[32]
-unit.1.3.port.0.s.32.orderindex=-1
-unit.1.3.port.0.s.32.visible=1
-unit.1.3.port.0.s.33.alias=unused33
-unit.1.3.port.0.s.33.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.33.name=TriggerPort0[33]
-unit.1.3.port.0.s.33.orderindex=-1
-unit.1.3.port.0.s.33.visible=1
-unit.1.3.port.0.s.34.alias=unused34
-unit.1.3.port.0.s.34.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.34.name=TriggerPort0[34]
-unit.1.3.port.0.s.34.orderindex=-1
-unit.1.3.port.0.s.34.visible=1
-unit.1.3.port.0.s.35.alias=unused35
-unit.1.3.port.0.s.35.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.35.name=TriggerPort0[35]
-unit.1.3.port.0.s.35.orderindex=-1
-unit.1.3.port.0.s.35.visible=1
-unit.1.3.port.0.s.36.alias=unused36
-unit.1.3.port.0.s.36.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.36.name=TriggerPort0[36]
-unit.1.3.port.0.s.36.orderindex=-1
-unit.1.3.port.0.s.36.visible=1
-unit.1.3.port.0.s.37.alias=unused37
-unit.1.3.port.0.s.37.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.37.name=TriggerPort0[37]
-unit.1.3.port.0.s.37.orderindex=-1
-unit.1.3.port.0.s.37.visible=1
-unit.1.3.port.0.s.38.alias=unused38
-unit.1.3.port.0.s.38.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.38.name=TriggerPort0[38]
-unit.1.3.port.0.s.38.orderindex=-1
-unit.1.3.port.0.s.38.visible=1
-unit.1.3.port.0.s.39.alias=unused39
-unit.1.3.port.0.s.39.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.39.name=TriggerPort0[39]
-unit.1.3.port.0.s.39.orderindex=-1
-unit.1.3.port.0.s.39.visible=1
-unit.1.3.port.0.s.40.alias=unused40
-unit.1.3.port.0.s.40.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.40.name=TriggerPort0[40]
-unit.1.3.port.0.s.40.orderindex=-1
-unit.1.3.port.0.s.40.visible=1
-unit.1.3.port.0.s.41.alias=unused41
-unit.1.3.port.0.s.41.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.41.name=TriggerPort0[41]
-unit.1.3.port.0.s.41.orderindex=-1
-unit.1.3.port.0.s.41.visible=1
-unit.1.3.port.0.s.42.alias=unused42
-unit.1.3.port.0.s.42.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.42.name=TriggerPort0[42]
-unit.1.3.port.0.s.42.orderindex=-1
-unit.1.3.port.0.s.42.visible=1
-unit.1.3.port.0.s.43.alias=unused43
-unit.1.3.port.0.s.43.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.43.name=TriggerPort0[43]
-unit.1.3.port.0.s.43.orderindex=-1
-unit.1.3.port.0.s.43.visible=1
-unit.1.3.port.0.s.44.alias=unused44
-unit.1.3.port.0.s.44.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.44.name=TriggerPort0[44]
-unit.1.3.port.0.s.44.orderindex=-1
-unit.1.3.port.0.s.44.visible=1
-unit.1.3.port.0.s.45.alias=unused45
-unit.1.3.port.0.s.45.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.45.name=TriggerPort0[45]
-unit.1.3.port.0.s.45.orderindex=-1
-unit.1.3.port.0.s.45.visible=1
-unit.1.3.port.0.s.46.alias=unused46
-unit.1.3.port.0.s.46.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.46.name=TriggerPort0[46]
-unit.1.3.port.0.s.46.orderindex=-1
-unit.1.3.port.0.s.46.visible=1
-unit.1.3.port.0.s.47.alias=unused47
-unit.1.3.port.0.s.47.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.47.name=TriggerPort0[47]
-unit.1.3.port.0.s.47.orderindex=-1
-unit.1.3.port.0.s.47.visible=1
-unit.1.3.port.0.s.48.alias=unused48
-unit.1.3.port.0.s.48.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.48.name=TriggerPort0[48]
-unit.1.3.port.0.s.48.orderindex=-1
-unit.1.3.port.0.s.48.visible=1
-unit.1.3.port.0.s.49.alias=unused49
-unit.1.3.port.0.s.49.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.49.name=TriggerPort0[49]
-unit.1.3.port.0.s.49.orderindex=-1
-unit.1.3.port.0.s.49.visible=1
-unit.1.3.port.0.s.50.alias=unused50
-unit.1.3.port.0.s.50.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.50.name=TriggerPort0[50]
-unit.1.3.port.0.s.50.orderindex=-1
-unit.1.3.port.0.s.50.visible=1
-unit.1.3.port.0.s.51.alias=unused51
-unit.1.3.port.0.s.51.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.51.name=TriggerPort0[51]
-unit.1.3.port.0.s.51.orderindex=-1
-unit.1.3.port.0.s.51.visible=1
-unit.1.3.port.0.s.52.alias=unused52
-unit.1.3.port.0.s.52.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.52.name=TriggerPort0[52]
-unit.1.3.port.0.s.52.orderindex=-1
-unit.1.3.port.0.s.52.visible=1
-unit.1.3.port.0.s.53.alias=unused53
-unit.1.3.port.0.s.53.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.53.name=TriggerPort0[53]
-unit.1.3.port.0.s.53.orderindex=-1
-unit.1.3.port.0.s.53.visible=1
-unit.1.3.port.0.s.54.alias=unused54
-unit.1.3.port.0.s.54.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.54.name=TriggerPort0[54]
-unit.1.3.port.0.s.54.orderindex=-1
-unit.1.3.port.0.s.54.visible=1
-unit.1.3.port.0.s.55.alias=unused55
-unit.1.3.port.0.s.55.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.55.name=TriggerPort0[55]
-unit.1.3.port.0.s.55.orderindex=-1
-unit.1.3.port.0.s.55.visible=1
-unit.1.3.port.0.s.56.alias=unused56
-unit.1.3.port.0.s.56.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.56.name=TriggerPort0[56]
-unit.1.3.port.0.s.56.orderindex=-1
-unit.1.3.port.0.s.56.visible=1
-unit.1.3.port.0.s.57.alias=unused57
-unit.1.3.port.0.s.57.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.57.name=TriggerPort0[57]
-unit.1.3.port.0.s.57.orderindex=-1
-unit.1.3.port.0.s.57.visible=1
-unit.1.3.port.0.s.58.alias=unused58
-unit.1.3.port.0.s.58.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.58.name=TriggerPort0[58]
-unit.1.3.port.0.s.58.orderindex=-1
-unit.1.3.port.0.s.58.visible=1
-unit.1.3.port.0.s.59.alias=unused59
-unit.1.3.port.0.s.59.color=java.awt.Color[r=0,g=0,b=255]
-unit.1.3.port.0.s.59.name=TriggerPort0[59]
-unit.1.3.port.0.s.59.orderindex=-1
-unit.1.3.port.0.s.59.visible=1
-unit.1.3.portcount=1
-unit.1.3.samplesPerTrigger=1
-unit.1.3.triggerCapture=1
-unit.1.3.triggerNSamplesTS=0
-unit.1.3.triggerPosition=0
-unit.1.3.triggerWindowCount=1
-unit.1.3.triggerWindowDepth=1024
-unit.1.3.triggerWindowTS=0
-unit.1.3.waveform.count=8
-unit.1.3.waveform.posn.0.channel=84
-unit.1.3.waveform.posn.0.name=DataPort[84]
-unit.1.3.waveform.posn.0.type=signal
-unit.1.3.waveform.posn.1.channel=83
-unit.1.3.waveform.posn.1.name=DataPort[83]
-unit.1.3.waveform.posn.1.type=signal
-unit.1.3.waveform.posn.2.channel=82
-unit.1.3.waveform.posn.2.name=DataPort[82]
-unit.1.3.waveform.posn.2.type=signal
-unit.1.3.waveform.posn.3.name=rxdata
-unit.1.3.waveform.posn.3.channel=2147483646
-unit.1.3.waveform.posn.3.type=bus
-unit.1.3.waveform.posn.3.radix=1
-unit.1.3.waveform.posn.4.name=rxstatus
-unit.1.3.waveform.posn.4.channel=2147483646
-unit.1.3.waveform.posn.4.type=bus
-unit.1.3.waveform.posn.4.radix=1
-unit.1.3.waveform.posn.5.name=rxlossofsync
-unit.1.3.waveform.posn.5.channel=2147483646
-unit.1.3.waveform.posn.5.type=bus
-unit.1.3.waveform.posn.5.radix=1
-unit.1.3.waveform.posn.6.channel=68
-unit.1.3.waveform.posn.6.name=DataPort[68]
-unit.1.3.waveform.posn.6.type=signal
-unit.1.3.waveform.posn.7.name=error_count
-unit.1.3.waveform.posn.7.channel=2147483646
-unit.1.3.waveform.posn.7.type=bus
-unit.1.3.waveform.posn.7.radix=1
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/data_vio.ngc b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/data_vio.ngc
deleted file mode 100644
index 465356a..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/data_vio.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
-$b254=7<2:;<=:401210>6688>0<;??1:07?77788=0??4FNQWW>DU^FJUBB1=>:1<22>552@D[YY4\YOA\MK:493:5=45<2;MVPUSS2HYRBNQ@UU>05?699118>7AZTQWW>V_IKVE^X1=>:1<22>512@DDYY4LOOVQKI:4=3:5869IFG33?2@ANOLMJKHIFGDEB4=?022;<=>?0108E54<I880M?<4A2:8ECGDI:K;n6O\YOA\MK:76j1J_T@L_HL?558d3HYRBNQFN=32:f=F[PDHSD@313<`?DU^FJUBB1?<>b9BW\HDW@D7=90l;@QZJFYNF5;>2n5NSXL@[LH;9?4h7L]VNB]JJ9706j1J_T@L_HL?5=8d3HYRBNQFN=3::g=F[PDHSD@31?a8EV_IKVCE0?>1c:CP]KEXAG69=3m4AR[MGZOI4;85o6O\YOA\MK:5;7i0M^WAC^KM8729k2KXUCMPIO>11;e<IZSEORGA<34=g>GTQGITEC2=7?a8EV_IKVCE0?61c:CP]KEXAG6953l4AR[MGZOI4;4h7L]VNB]JJ9576l1J_T@L_HL?74<76j1J_T@L_HL?748e3HYRBNQFN=1=f>GTQGITEC2;>c9BW\HDW@D793l4AR[MGZOI4?4i7L]VNB]JJ919j2KXUCMPIO>;:g=F[PDHSD@39?a8EV_IKVE^X1>1d:CP]KEXG\^7==0k;@QZJFYH]]6:=3j4AR[MGZIR\5;92i5NSXL@[JSS4895h6O\YOA\KPR;9=4o7L]VNB]LQQ:6=7n0M^WAC^MVP9716m1J_T@L_NWW8419l2KXUCMPOTV?5=8c3HYRBNQ@UU>2=;e<IZSEORAZT=3=`>GTQGITCXZ321<g?DU^FJUDYY2=1?f8EV_IKVE^X1<=>e9BW\HDWF__0?=1d:CP]KEXG\^7>90k;@QZJFYH]]6993j4AR[MGZIR\58=2i5NSXL@[JSS4;=5h6O\YOA\KPR;:14o7L]VNB]LQQ:517i0M^WAC^MVP949l2KXUCMPOTV?758a3HYRBNQ@UU>05?69l2KXUCMPOTV?748d3HYRBNQ@UU>0:f=F[PDHSB[[<5<`?DU^FJUDYY2:>b9BW\HDWF__0;0l;@QZJFYH]]6<2n5NSXL@[JSS414h7L]VNB]LQQ:>6=1I==77;CWP[LHAG81H>6MN2:AF57=D@LI@SAGLEOQF[Q_WM;1HE>5LLJ18GIT>3JEFADZ[EEc8GJHSZFF7<3l4CNLWVJJ;994i7NAATSMO8479j2IDBY\@L=31:g=DGG^YCA2>3?`8GJHSZFF7=90m;BMMPWIK48?5n6M@NUPLH9716k1HCCZ]OM>23;d<KFD_^BB319<a?FII\[EG0<71a:ALJQTHD5;5n6M@NUPLH9476k1HCCZ]OM>15;d<KFD_^BB323<a?FII\[EG0?=1b:ALJQTHD58?2o5LOOVQKI:5=7h0OB@[RNN?638e3JEEX_AC<35=f>EHF]XD@1<7>c9@KKRUGE6953o4CNLWVJJ;:7h0OB@[RNN?758e3JEEX_AC<23=f>EHF]XD@1==>c9@KKRUGE68?3l4CNLWVJJ;;=4o7NAATSMO863=87h0OB@[RNN?708f3JEEX_AC<2<b?FII\[EG090n;BMMPWIK4<4j7NAATSMO838f3JEEX_AC<6<b?FII\[EG050n;BMMPWIK404:86M@RD]DAKCUI]CDBRGAFN58GWCF\LN:7I<4DH78@ZEKC8:0JIL6EBC;3056>=8;86HKCD18BAC43ONY86HKRD:8BC@ANOLN=6I<;FLG2>NBIMUG=6G=;H21?L753@897D==;H61?L3>3@DBX^ZNTD18MKP53EC97AA8;MMDMFGK<2F^X<:4LTV10>JR\:>0@XZ;4:NVP02<D\^=;6CZXB[\H7=I8;1E=>5A3758J@RPG[A:7B?4P59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ1:S0?T7292X:7^84SNWQG@1<[[FH=;Kn;R[MGZOI494i7^WAC^KM8469j2YRBNQFN=32:g=TQGITEC2>2?`8W\HDW@D7=>0m;R[MGZOI48>5n6]VNB]JJ9726k1XUCMPIO>22;d<[PDHSD@316<a?V_IKVCE0<61b:QZJFYNF5;22l5\YOA\MK:66k1XUCMPIO>14;d<[PDHSD@320<a?V_IKVCE0?<1b:QZJFYNF5882o5\YOA\MK:5<7h0_T@L_HL?608e3ZSEORGA<34=f>U^FJUBB1<8>c9P]KEXAG6943l4SXL@[LH;:04j7^WAC^KM878e3ZSEORGA<22=`>U^FJUBB1=>:1<a?V_IKVCE0>?1a:QZJFYNF595m6]VNB]JJ929i2YRBNQFN=7=e>U^FJUBB181a:QZJFYNF5=5m6]VNB]JJ9>9i2YRBNQFN=;=f>U^FJUDYY2?>b9P]KEXG\^7==0l;R[MGZIR\5;:2n5\YOA\KPR;9;4h7^WAC^MVP9746j1XUCMPOTV?518d3ZSEORAZT=36:f=TQGITCXZ317<`?V_IKVE^X1?8>b9P]KEXG\^7=50l;R[MGZIR\5;22o5\YOA\KPR;97i0_T@L_NWW8769k2YRBNQ@UU>15;e<[PDHSB[[<30=g>U^FJUDYY2=3?a8W\HDWF__0?:1c:QZJFYH]]6993m4SXL@[JSS4;<5o6]VNB]LQQ:5?7i0_T@L_NWW87>9k2YRBNQ@UU>1=;d<[PDHSB[[<3<`?V_IKVE^X1=?>d9P]KEXG\^7?<4?>b9P]KEXG\^7?<0m;R[MGZIR\595n6]VNB]LQQ:36k1XUCMPOTV?1;d<[PDHSB[[<7<a?V_IKVE^X191b:QZJFYH]]632o5\YOA\KPR;17=0XCCPNDV7?Q_WM880Y=!F_WKL+DTJWygh?=;T2,MZPNG&NJXLQKOTV06>S7'@U]EB!HEO]BW\HDW@DP<P NSXL@[LHXKLFG#L]VNB]E[HS_;;1^<"GPVHM,C@HXIZSEORGA[1_-EV_IKVCESNKCL.CP]KEXZVG^T>:4U1-J[SOH'NOESL]VNB]JJ^6Z&HYRBNQFN^AFHI)TWHYRBNQI_SGD77=R8&CTZDA GDL\EV_IKVCEW=S!AR[MGZOIWJOG@"]PAR[MGZTBO:>0Y=!F_WKL+BCIWHYRBNQFNZ2^*DU^FJUBBRMJLM-P[DU^FJUYS_KH309V4*OX^@E$KH@PAR[MGZOIS9W%M^WAC^KM[FCKD&YTY^K]_SGD6c=R8&CTZDA GDL\EV_IKVCEW=S!AR[MGZOIWJOG@"[\ES]NQ]573\:$ERXFO.EFJZGTQGITECU?]/CP]KEXAGUHIAB U^DBHIOIO;l0Y=!F_WKL+BCIWHYRBNQFNZ2^*DU^FJUBBRMJLM-V[WOTAGM8>6[?/H]UMJ)@MGUJ_T@L_HLX4X(F[PDHSD@PCDNO+PYT\H^HAIQa379V4*OX^@E$KH@PAR[MGZOIS9W%M^WAC^KM[FCKD&kxucmPmtz\bZir|:<0Y=!F_WKL+BCIWHYRBNQFNZ2^*DU^FJUBBRMJLM-bw|hdWdsSQ`uu11?P6(AV\BC"IJN^CP]KEXAGQ;Q#O\YOA\MKYDMEF$jlbcioe\kpr5m2_;#DQYIN-DAKYF[PDHSD@T0\,BW\HDW@DTOHBC/gf2[jss:l1^<"GPVHM,C@HXIZSEORGA[1_-EV_IKVCESNKCL.dg6Zir|;o0Y=!F_WKL+BCIWHYRBNQFNZ2^*DU^FJUBBRMJLM-e`6Yh}}8m7X> I^TJK*ABFVKXUCMPIOY3Y+GTQGITECQLEMN,ip~6Wf?<5Z0.K\RLI(OLDTM^WAC^KM_5[)IZSEORGA_BGOH*tn{`dlSb{{319V4*OX^@E$KH@PAR[MGZOIS9W%M^WAC^KM[FCKD&xiQfn^l07>S7'@U]EB!HEO]BW\HDW@DP==S!AR[MGZOIWJOG@"O\YOA\BZKRP:90Y=!F_WKL+BCIWHYRBNQFNZ33Y+GTQGITECQLEMN,EV_IKVXTAXV<5:W3+LYQAF%LICQNSXL@[LH\99W%M^WAC^KM[FCKD&YTM^WAC^D\V@A4;2_;#DQYIN-DAKYF[PDHSD@T11_-EV_IKVCESNKCL.Q\EV_IKVXNK>;4U1-J[SOH'NOESL]VNB]JJ^77U'KXUCMPIO]@AIJ([VKXUCMPR^PFC64<]9%BS[G@/FGM[DU^FJUBBV??]/CP]KEXAGUHIAB S^WPAWYUMN9;7X> I^TJK*ABFVKXUCMPIOY24X(F[PDHSD@PCDNO+PUBZVG^T>?4U1-J[SOH'NOESL]VNB]JJ^77U'KXUCMPIO]@AIJ(]VLJ@AGAG228Q5)NW_CD#JKA_@QZJFYNFR;;Q#O\YOA\MKYDMEF$YR\FSHLD76=R8&CTZDA GDL\EV_IKVCEW<>R.@QZJFYNFVIN@A!Z_RVBPFKCWg9<7X> I^TJK*ABFVKXUCMPIOY24X(F[PDHSD@PCDNO+du~fjUfyuQi_nww72=R8&CTZDA GDL\EV_IKVCEW<>R.@QZJFYNFVIN@A!nsxl`[hsW{Udyy=<;T2,MZPNG&MNBRO\YOA\MK]68T$J_T@L_HL\G@JK'okg`d`h_nww6c=R8&CTZDA GDL\EV_IKVCEW<>R.@QZJFYNFVIN@A!id0]lqq4a3\:$ERXFO.EFJZGTQGITECU>0\,BW\HDW@DTOHBC/gf1[jss:o1^<"GPVHM,C@HXIZSEORGA[02^*DU^FJUBBRMJLM-e`6Yh}}9;7X> I^TJK*ABFVKXUCMPIOY24X(F[PDHSD@PCDNO+hs9Ve~x><4U1-J[SOH'NOESL]VNB]JJ^77U'KXUCMPIO]@AIJ(z`ybbjQ`uu12?P6(AV\BC"IJN^CP]KEXAGQ:<P NSXL@[LHXKLFG#x}jr^km[k543\:$ERXFO.EFJZGTQGITECU>1\,BW\HDW@DTOHBC/@QZJFYAWD_S?>5Z0.K\RLI(OLDTM^WAC^KM_47Z&HYRBNQFN^AFHI)F[PDHS_QBUY16?P6(AV\BC"IJN^CP]KEXAGQ:=P NSXL@[LHXKLFG#^QNSXL@[CYUMN987X> I^TJK*ABFVKXUCMPIOY25X(F[PDHSD@PCDNO+VYF[PDHS_KH349V4*OX^@E$KH@PAR[MGZOIS8;V"L]VNB]JJZEBDE%XSL]VNB]Q[WC@;;1^<"GPVHM,C@HXIZSEORGA[03^*DU^FJUBBRMJLM-P[PUBZVXNK>>4U1-J[SOH'NOESL]VNB]JJ^76U'KXUCMPIO]@AIJ(]ZOYS@[W309V4*OX^@E$KH@PAR[MGZOIS8;V"L]VNB]JJZEBDE%^SKOCLHLD75=R8&CTZDA GDL\EV_IKVCEW<?R.@QZJFYNFVIN@A!Z_SKPMKA4;2_;#DQYIN-DAKYF[PDHSD@T10_-EV_IKVCESNKCL.W\WQGSKDNTb>94U1-J[SOH'NOESL]VNB]JJ^76U'KXUCMPIO]@AIJ(izseoRczx^d\kpr4?2_;#DQYIN-DAKYF[PDHSD@T10_-EV_IKVCESNKCL.cp}keXe|rT~Razt218Q5)NW_CD#JKA_@QZJFYNFR;:Q#O\YOA\MKYDMEF$jlbcioe\kpr5n2_;#DQYIN-DAKYF[PDHSD@T10_-EV_IKVCESNKCL.dg5Zir|;l0Y=!F_WKL+BCIWHYRBNQFNZ32Y+GTQGITECQLEMN,ba4Xg|~9j6[?/H]UMJ)@MGUJ_T@L_HLX54[)IZSEORGA_BGOH*`c;Ve~x>>4U1-J[SOH'NOESL]VNB]JJ^76U'KXUCMPIO]@AIJ(e|r:Sb{{339V4*OX^@E$KH@PAR[MGZOIS8;V"L]VNB]JJZEBDE%ye~gag^mvp67<]9%BS[G@/FGM[DU^FJUBBV?>]/CP]KEXAGUHIAB urgq[lhXf:90Y=!F_WKL+BCIWHYRBNQFNZ31Y+GTQGITECQLEMN,EV_IKVLTAXV<3:W3+LYQAF%LICQNSXL@[LH\9;W%M^WAC^KM[FCKD&KXUCMPR^OV\63<]9%BS[G@/FGM[DU^FJUBBV?=]/CP]KEXAGUHIAB S^CP]KEXNVXNK>=4U1-J[SOH'NOESL]VNB]JJ^75U'KXUCMPIO]@AIJ([VKXUCMPRDE01>S7'@U]EB!HEO]BW\HDW@DP=?S!AR[MGZOIWJOG@"]PAR[MGZTXZLM8>6[?/H]UMJ)@MGUJ_T@L_HLX57[)IZSEORGA_BGOH*UX]ZOYS_KH319V4*OX^@E$KH@PAR[MGZOIS88V"L]VNB]JJZEBDE%^_H\PMTZ05>S7'@U]EB!HEO]BW\HDW@DP=?S!AR[MGZOIWJOG@"[PF@NOMKA482_;#DQYIN-DAKYF[PDHSD@T13_-EV_IKVCESNKCL.W\VLUNFN987X> I^TJK*ABFVKXUCMPIOY26X(F[PDHSD@PCDNO+PYT\H^HAIQa369V4*OX^@E$KH@PAR[MGZOIS88V"L]VNB]JJZEBDE%jt`l_lw{[cYh}}9<7X> I^TJK*ABFVKXUCMPIOY26X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww76=R8&CTZDA GDL\EV_IKVCEW<<R.@QZJFYNFVIN@A!iamnjjbYh}}8m7X> I^TJK*ABFVKXUCMPIOY26X(F[PDHSD@PCDNO+cb6Wf>k5Z0.K\RLI(OLDTM^WAC^KM_44Z&HYRBNQFN^AFHI)al;Udyy<i;T2,MZPNG&MNBRO\YOA\MK]6:T$J_T@L_HL\G@JK'on8Sb{{319V4*OX^@E$KH@PAR[MGZOIS88V"L]VNB]JJZEBDE%fyu?Potv06>S7'@U]EB!HEO]BW\HDW@DP=?S!AR[MGZOIWJOG@"|fshld[jss;81^<"GPVHM,C@HXIZSEORGA[00^*DU^FJUBBRMJLM-vw`tXagUe?>5Z0.K\RLI(OLDTM^WAC^KM_45Z&HYRBNQFN^AFHI)F[PDHSKQBUY10?P6(AV\BC"IJN^CP]KEXAGQ:?P NSXL@[LHXKLFG#L]VNB]Q[HS_;<1^<"GPVHM,C@HXIZSEORGA[01^*DU^FJUBBRMJLM-P[DU^FJUMS_KH329V4*OX^@E$KH@PAR[MGZOIS89V"L]VNB]JJZEBDE%XSL]VNB]QAB523\:$ERXFO.EFJZGTQGITECU>3\,BW\HDW@DTOHBC/R]BW\HDW[UYIJ==;T2,MZPNG&MNBRO\YOA\MK]6;T$J_T@L_HL\G@JK'ZU^_H\PRDE04>S7'@U]EB!HEO]BW\HDW@DP=>S!AR[MGZOIWJOG@"[\ES]NQ]563\:$ERXFO.EFJZGTQGITECU>3\,BW\HDW@DTOHBC/T]EEIJNFN9;7X> I^TJK*ABFVKXUCMPIOY27X(F[PDHSD@PCDNO+PYUAZCEK>=4U1-J[SOH'NOESL]VNB]JJ^74U'KXUCMPIO]@AIJ(]VY_MYMBD^l03>S7'@U]EB!HEO]BW\HDW@DP=>S!AR[MGZOIWJOG@"o|yoa\ip~XnVe~x>94U1-J[SOH'NOESL]VNB]JJ^74U'KXUCMPIO]@AIJ(izseoRczx^p\kpr4;2_;#DQYIN-DAKYF[PDHSD@T12_-EV_IKVCESNKCL.dbhioioVe~x?h4U1-J[SOH'NOESL]VNB]JJ^74U'KXUCMPIO]@AIJ(nm;Tcxz=f:W3+LYQAF%LICQNSXL@[LH\9:W%M^WAC^KM[FCKD&lo>Razt3d8Q5)NW_CD#JKA_@QZJFYNFR;8Q#O\YOA\MKYDMEF$ji=Potv04>S7'@U]EB!HEO]BW\HDW@DP=>S!AR[MGZOIWJOG@"czx0]lqq553\:$ERXFO.EFJZGTQGITECU>3\,BW\HDW@DTOHBC/skpmkaXg|~8=6[?/H]UMJ)@MGUJ_T@L_HLX56[)IZSEORGA_BGOH*stm{UbbR`<3:W3+LYQAF%LICQNSXL@[LH\9=W%M^WAC^KM[FCKD&KXUCMPF^OV\65<]9%BS[G@/FGM[DU^FJUBBV?;]/CP]KEXAGUHIAB AR[MGZTXE\R896[?/H]UMJ)@MGUJ_T@L_HLX51[)IZSEORGA_BGOH*UXIZSEORHPRDE07>S7'@U]EB!HEO]BW\HDW@DP=9S!AR[MGZOIWJOG@"]PAR[MGZTBO:?0Y=!F_WKL+BCIWHYRBNQFNZ37Y+GTQGITECQLEMN,WZGTQGIT^R\JG208Q5)NW_CD#JKA_@QZJFYNFR;?Q#O\YOA\MKYDMEF$_R[\ES]QAB573\:$ERXFO.EFJZGTQGITECU>4\,BW\HDW@DTOHBC/TQFVZKRP:;0Y=!F_WKL+BCIWHYRBNQFNZ37Y+GTQGITECQLEMN,QZ@FDECEK>>4U1-J[SOH'NOESL]VNB]JJ^73U'KXUCMPIO]@AIJ(]VXB_D@H329V4*OX^@E$KH@PAR[MGZOIS8>V"L]VNB]JJZEBDE%^S^ZNTBOG[k503\:$ERXFO.EFJZGTQGITECU>4\,BW\HDW@DTOHBC/`qzjfYj}qUmSb{{369V4*OX^@E$KH@PAR[MGZOIS8>V"L]VNB]JJZEBDE%jt`l_lw{[wYh}}987X> I^TJK*ABFVKXUCMPIOY20X(F[PDHSD@PCDNO+cgkd`dlSb{{2g9V4*OX^@E$KH@PAR[MGZOIS8>V"L]VNB]JJZEBDE%mh<Q`uu0e?P6(AV\BC"IJN^CP]KEXAGQ:8P NSXL@[LHXKLFG#kj=_nww6c=R8&CTZDA GDL\EV_IKVCEW<:R.@QZJFYNFVIN@A!id2]lqq573\:$ERXFO.EFJZGTQGITECU>4\,BW\HDW@DTOHBC/lw{5Zir|:80Y=!F_WKL+BCIWHYRBNQFNZ37Y+GTQGITECQLEMN,vlunfnUdyy=>;T2,MZPNG&MNBRO\YOA\MK]6<T$J_T@L_HL\G@JK'|yn~Rga_o10?P6(AV\BC"IJN^CP]KEXAGQ:9P NSXL@[LHXKLFG#L]VNB]E[HS_;:1^<"GPVHM,C@HXIZSEORGA[07^*DU^FJUBBRMJLM-BW\HDW[UFYU=:;T2,MZPNG&MNBRO\YOA\MK]6=T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB543\:$ERXFO.EFJZGTQGITECU>5\,BW\HDW@DTOHBC/R]BW\HDW[OL?85Z0.K\RLI(OLDTM^WAC^KM_43Z&HYRBNQFN^AFHI)TWHYRBNQ]_SGD77=R8&CTZDA GDL\EV_IKVCEW<;R.@QZJFYNFVIN@A!\_TQFVZTBO::0Y=!F_WKL+BCIWHYRBNQFNZ36Y+GTQGITECQLEMN,QVCUWD_S?<5Z0.K\RLI(OLDTM^WAC^KM_43Z&HYRBNQFN^AFHI)RWOKG@D@H319V4*OX^@E$KH@PAR[MGZOIS8?V"L]VNB]JJZEBDE%^S_G\IOE07>S7'@U]EB!HEO]BW\HDW@DP=8S!AR[MGZOIWJOG@"[PSUCWGHBXf:=0Y=!F_WKL+BCIWHYRBNQFNZ36Y+GTQGITECQLEMN,evikVg~tRhPotv03>S7'@U]EB!HEO]BW\HDW@DP=8S!AR[MGZOIWJOG@"o|yoa\ip~XzVe~x>=4U1-J[SOH'NOESL]VNB]JJ^72U'KXUCMPIO]@AIJ(nhfgeciPotv1b>S7'@U]EB!HEO]BW\HDW@DP=8S!AR[MGZOIWJOG@"hk1^mvp7`<]9%BS[G@/FGM[DU^FJUBBV?:]/CP]KEXAGUHIAB fe0\kpr5n2_;#DQYIN-DAKYF[PDHSD@T14_-EV_IKVCESNKCL.dg7Zir|::0Y=!F_WKL+BCIWHYRBNQFNZ36Y+GTQGITECQLEMN,ip~6Wf??5Z0.K\RLI(OLDTM^WAC^KM_43Z&HYRBNQFN^AFHI)uazcekRazt238Q5)NW_CD#JKA_@QZJFYNFR;>Q#O\YOA\MKYDMEF$y~k}_hl\j65<]9%BS[G@/FGM[DU^FJUBBV?9]/CP]KEXAGUHIAB AR[MGZ@XE\R8?6[?/H]UMJ)@MGUJ_T@L_HLX53[)IZSEORGA_BGOH*GTQGIT^RCZX278Q5)NW_CD#JKA_@QZJFYNFR;=Q#O\YOA\MKYDMEF$_RO\YOA\BZTBO:90Y=!F_WKL+BCIWHYRBNQFNZ35Y+GTQGITECQLEMN,WZGTQGIT^HI<5:W3+LYQAF%LICQNSXL@[LH\9?W%M^WAC^KM[FCKD&YTM^WAC^P\V@A4:2_;#DQYIN-DAKYF[PDHSD@T17_-EV_IKVCESNKCL.Q\QVCUW[OL?=5Z0.K\RLI(OLDTM^WAC^KM_40Z&HYRBNQFN^AFHI)R[LXTAXV<1:W3+LYQAF%LICQNSXL@[LH\9?W%M^WAC^KM[FCKD&_TJLBCIOE04>S7'@U]EB!HEO]BW\HDW@DP=;S!AR[MGZOIWJOG@"[PRHQJJB543\:$ERXFO.EFJZGTQGITECU>6\,BW\HDW@DTOHBC/T]PPDRDEMUe?:5Z0.K\RLI(OLDTM^WAC^KM_40Z&HYRBNQFN^AFHI)f{pdhS`{w_g]lqq503\:$ERXFO.EFJZGTQGITECU>6\,BW\HDW@DTOHBC/`qzjfYj}qUySb{{329V4*OX^@E$KH@PAR[MGZOIS8<V"L]VNB]JJZEBDE%mmabfnf]lqq4a3\:$ERXFO.EFJZGTQGITECU>6\,BW\HDW@DTOHBC/gf2[jss:o1^<"GPVHM,C@HXIZSEORGA[04^*DU^FJUBBRMJLM-e`7Yh}}8m7X> I^TJK*ABFVKXUCMPIOY22X(F[PDHSD@PCDNO+cb4Wf?=5Z0.K\RLI(OLDTM^WAC^KM_40Z&HYRBNQFN^AFHI)j}q;Tcxz<2:W3+LYQAF%LICQNSXL@[LH\9?W%M^WAC^KM[FCKD&xbd`h_nww74=R8&CTZDA GDL\EV_IKVCEW<8R.@QZJFYNFVIN@A!zsdp\mkYi;:1^<"GPVHM,C@HXIZSEORGA[05^*DU^FJUBBRMJLM-BW\HDWOUFYU=<;T2,MZPNG&MNBRO\YOA\MK]6?T$J_T@L_HL\G@JK'HYRBNQ]_LW[70=R8&CTZDA GDL\EV_IKVCEW<9R.@QZJFYNFVIN@A!\_@QZJFYAW[OL?>5Z0.K\RLI(OLDTM^WAC^KM_41Z&HYRBNQFN^AFHI)TWHYRBNQ]EF16?P6(AV\BC"IJN^CP]KEXAGQ:;P NSXL@[LHXKLFG#^QNSXL@[WYUMN997X> I^TJK*ABFVKXUCMPIOY23X(F[PDHSD@PCDNO+VYR[LXT^HI<0:W3+LYQAF%LICQNSXL@[LH\9>W%M^WAC^KM[FCKD&_XI_QBUY12?P6(AV\BC"IJN^CP]KEXAGQ:;P NSXL@[LHXKLFG#XQIAMNJJB573\:$ERXFO.EFJZGTQGITECU>7\,BW\HDW@DTOHBC/T]QMVOIO:90Y=!F_WKL+BCIWHYRBNQFNZ34Y+GTQGITECQLEMN,QZUSI]IFHR`<7:W3+LYQAF%LICQNSXL@[LH\9>W%M^WAC^KM[FCKD&kxucmPmtz\bZir|:=0Y=!F_WKL+BCIWHYRBNQFNZ34Y+GTQGITECQLEMN,evikVg~tR|Potv07>S7'@U]EB!HEO]BW\HDW@DP=:S!AR[MGZOIWJOG@"hnlmkmcZir|;l0Y=!F_WKL+BCIWHYRBNQFNZ34Y+GTQGITECQLEMN,ba7Xg|~9j6[?/H]UMJ)@MGUJ_T@L_HLX52[)IZSEORGA_BGOH*`c:Ve~x?h4U1-J[SOH'NOESL]VNB]JJ^70U'KXUCMPIO]@AIJ(nm9Tcxz<0:W3+LYQAF%LICQNSXL@[LH\9>W%M^WAC^KM[FCKD&g~t<Q`uu11?P6(AV\BC"IJN^CP]KEXAGQ:;P NSXL@[LHXKLFG#g|ioe\kpr492_;#DQYIN-DAKYF[PDHSD@T16_-EV_IKVCESNKCL.wpawYnfVd8?6[?/H]UMJ)@MGUJ_T@L_HLX5=[)IZSEORGA_BGOH*GTQGITJRCZX218Q5)NW_CD#JKA_@QZJFYNFR;3Q#O\YOA\MKYDMEF$M^WAC^P\IP^4=2_;#DQYIN-DAKYF[PDHSD@T19_-EV_IKVCESNKCL.Q\EV_IKVLT^HI<3:W3+LYQAF%LICQNSXL@[LH\91W%M^WAC^KM[FCKD&YTM^WAC^PFC63<]9%BS[G@/FGM[DU^FJUBBV?7]/CP]KEXAGUHIAB S^CP]KEXZVXNK><4U1-J[SOH'NOESL]VNB]JJ^7?U'KXUCMPIO]@AIJ([V_XI_Q]EF13?P6(AV\BC"IJN^CP]KEXAGQ:4P NSXL@[LHXKLFG#X]JR^OV\67<]9%BS[G@/FGM[DU^FJUBBV?7]/CP]KEXAGUHIAB U^DBHIOIO::0Y=!F_WKL+BCIWHYRBNQFNZ3;Y+GTQGITECQLEMN,QZTN[@DL?>5Z0.K\RLI(OLDTM^WAC^KM_4>Z&HYRBNQFN^AFHI)RWZ^JXNCK_o14?P6(AV\BC"IJN^CP]KEXAGQ:4P NSXL@[LHXKLFG#l}vnb]nq}YaWf?:5Z0.K\RLI(OLDTM^WAC^KM_4>Z&HYRBNQFN^AFHI)f{pdhS`{w_s]lqq543\:$ERXFO.EFJZGTQGITECU>8\,BW\HDW@DTOHBC/gcohlh`Wf>k5Z0.K\RLI(OLDTM^WAC^KM_4>Z&HYRBNQFN^AFHI)al8Udyy<i;T2,MZPNG&MNBRO\YOA\MK]60T$J_T@L_HL\G@JK'on9Sb{{2g9V4*OX^@E$KH@PAR[MGZOIS82V"L]VNB]JJZEBDE%mh>Q`uu13?P6(AV\BC"IJN^CP]KEXAGQ:4P NSXL@[LHXKLFG#`{w1^mvp64<]9%BS[G@/FGM[DU^FJUBBV?7]/CP]KEXAGUHIAB rhqjjbYh}}9:7X> I^TJK*ABFVKXUCMPIOY2<X(F[PDHSD@PCDNO+pubzVceSc=<;T2,MZPNG&MNBRO\YOA\MK]61T$J_T@L_HL\G@JK'HYRBNQI_LW[76=R8&CTZDA GDL\EV_IKVCEW<7R.@QZJFYNFVIN@A!NSXL@[WYJ]Q9>7X> I^TJK*ABFVKXUCMPIOY2=X(F[PDHSD@PCDNO+VYF[PDHSKQ]EF10?P6(AV\BC"IJN^CP]KEXAGQ:5P NSXL@[LHXKLFG#^QNSXL@[WC@;<1^<"GPVHM,C@HXIZSEORGA[0;^*DU^FJUBBRMJLM-P[DU^FJUYS_KH339V4*OX^@E$KH@PAR[MGZOIS83V"L]VNB]JJZEBDE%XSX]JR^PFC66<]9%BS[G@/FGM[DU^FJUBBV?6]/CP]KEXAGUHIAB URGQ[HS_;81^<"GPVHM,C@HXIZSEORGA[0;^*DU^FJUBBRMJLM-V[CGKD@DL?=5Z0.K\RLI(OLDTM^WAC^KM_4?Z&HYRBNQFN^AFHI)RW[CXECI<3:W3+LYQAF%LICQNSXL@[LH\90W%M^WAC^KM[FCKD&_T_YO[CLF\j61<]9%BS[G@/FGM[DU^FJUBBV?6]/CP]KEXAGUHIAB ar{mgZkrpVlTcxz<7:W3+LYQAF%LICQNSXL@[LH\90W%M^WAC^KM[FCKD&kxucmPmtz\vZir|:90Y=!F_WKL+BCIWHYRBNQFNZ3:Y+GTQGITECQLEMN,bdjkagmTcxz=f:W3+LYQAF%LICQNSXL@[LH\90W%M^WAC^KM[FCKD&lo=Razt3d8Q5)NW_CD#JKA_@QZJFYNFR;2Q#O\YOA\MKYDMEF$ji<Potv1b>S7'@U]EB!HEO]BW\HDW@DP=4S!AR[MGZOIWJOG@"hk3^mvp66<]9%BS[G@/FGM[DU^FJUBBV?6]/CP]KEXAGUHIAB mtz2[jss;;1^<"GPVHM,C@HXIZSEORGA[0;^*DU^FJUBBRMJLM-qmvoioVe~x>?4U1-J[SOH'NOESL]VNB]JJ^7>U'KXUCMPIO]@AIJ(}zoySd`Pn208Q5)NW_CD#JKA_@QZJFYNFR;V"L]VNB]JJZEBDE%J_T@L_G]NQ]553\:$ERXFO.EFJZGTQGITECU>]/CP]KEXAGUHIAB AR[MGZTXE\R886[?/H]UMJ)@MGUJ_T@L_HLX5X(F[PDHSD@PCDNO+VYF[PDHSKQ]EF11?P6(AV\BC"IJN^CP]KEXAGQ:Q#O\YOA\MKYDMEF$_RO\YOA\V@A4<2_;#DQYIN-DAKYF[PDHSD@T1\,BW\HDW@DTOHBC/R]BW\HDW[UYIJ=>;T2,MZPNG&MNBRO\YOA\MK]6U'KXUCMPIO]@AIJ([V_XI_Q]EF0e?P6(AV\BC"IJN^CP]KEXAGQ:Q#O\YOA\MKYDMEF$Y^K]_LW[75=R8&CTZDA GDL\EV_IKVCEW<S!AR[MGZOIWJOG@"[PF@NOMKA5n2_;#DQYIN-DAKYF[PDHSD@T1\,BW\HDW@DTOHBC/T]QMVOIO:80Y=!F_WKL+BCIWHYRBNQFNZ3^*DU^FJUBBRMJLM-V[VRF\JGOSc=9;T2,MZPNG&MNBRO\YOA\MK]6U'KXUCMPIO]@AIJ(izseoRczx^d\kpr4>2_;#DQYIN-DAKYF[PDHSD@T1\,BW\HDW@DTOHBC/`qzjfYj}qUySb{{339V4*OX^@E$KH@PAR[MGZOIS8W%M^WAC^KM[FCKD&lj`agag^mvp7c<]9%BS[G@/FGM[DU^FJUBBV?R.@QZJFYNFVIN@A!id0]lqq4b3\:$ERXFO.EFJZGTQGITECU>]/CP]KEXAGUHIAB fe0\kpr5m2_;#DQYIN-DAKYF[PDHSD@T1\,BW\HDW@DTOHBC/gf0[jss:o1^<"GPVHM,C@HXIZSEORGA[0_-EV_IKVCESNKCL.ov|4Yh}}9:7X> I^TJK*ABFVKXUCMPIOY2Y+GTQGITECQLEMN,vlunfnUdyy=?;T2,MZPNG&MNBRO\YOA\MK]6U'KXUCMPIO]@AIJ(}zoySd`Pn218Q5)NW_CD#JKA_@QZJFYNFR8;Q#O\YOA\MKYDMEF$M^WAC^D\IP^4;2_;#DQYIN-DAKYF[PDHSD@T21_-EV_IKVCESNKCL.CP]KEXZVG^T>;4U1-J[SOH'NOESL]VNB]JJ^47U'KXUCMPIO]@AIJ([VKXUCMPF^PFC65<]9%BS[G@/FGM[DU^FJUBBV<?]/CP]KEXAGUHIAB S^CP]KEXZLM896[?/H]UMJ)@MGUJ_T@L_HLX65[)IZSEORGA_BGOH*UXIZSEOR\PRDE06>S7'@U]EB!HEO]BW\HDW@DP>=S!AR[MGZOIWJOG@"]PURGQ[WC@;91^<"GPVHM,C@HXIZSEORGA[32^*DU^FJUBBRMJLM-VW@TXE\R8=6[?/H]UMJ)@MGUJ_T@L_HLX65[)IZSEORGA_BGOH*SXNHFGECI<0:W3+LYQAF%LICQNSXL@[LH\:9W%M^WAC^KM[FCKD&_T^D]FNF10?P6(AV\BC"IJN^CP]KEXAGQ9<P NSXL@[LHXKLFG#XQ\T@V@IAYi;>1^<"GPVHM,C@HXIZSEORGA[32^*DU^FJUBBRMJLM-bw|hdWdsSkQ`uu14?P6(AV\BC"IJN^CP]KEXAGQ9<P NSXL@[LHXKLFG#l}vnb]nq}YuWf?>5Z0.K\RLI(OLDTM^WAC^KM_76Z&HYRBNQFN^AFHI)aiefbbjQ`uu0e?P6(AV\BC"IJN^CP]KEXAGQ9<P NSXL@[LHXKLFG#kj>_nww6c=R8&CTZDA GDL\EV_IKVCEW?>R.@QZJFYNFVIN@A!id3]lqq4a3\:$ERXFO.EFJZGTQGITECU=0\,BW\HDW@DTOHBC/gf0[jss;91^<"GPVHM,C@HXIZSEORGA[32^*DU^FJUBBRMJLM-nq}7Xg|~8>6[?/H]UMJ)@MGUJ_T@L_HLX65[)IZSEORGA_BGOH*tn{`dlSb{{309V4*OX^@E$KH@PAR[MGZOIS;:V"L]VNB]JJZEBDE%~h|Pio]m76=R8&CTZDA GDL\EV_IKVCEW??R.@QZJFYNFVIN@A!NSXL@[CYJ]Q987X> I^TJK*ABFVKXUCMPIOY15X(F[PDHSD@PCDNO+DU^FJUYS@[W349V4*OX^@E$KH@PAR[MGZOIS;;V"L]VNB]JJZEBDE%XSL]VNB]E[WC@;:1^<"GPVHM,C@HXIZSEORGA[33^*DU^FJUBBRMJLM-P[DU^FJUYIJ=:;T2,MZPNG&MNBRO\YOA\MK]59T$J_T@L_HL\G@JK'ZUJ_T@L_S]QAB553\:$ERXFO.EFJZGTQGITECU=1\,BW\HDW@DTOHBC/R]VW@TXZLM8<6[?/H]UMJ)@MGUJ_T@L_HLX64[)IZSEORGA_BGOH*STM[UFYU=>;T2,MZPNG&MNBRO\YOA\MK]59T$J_T@L_HL\G@JK'\UMMABFNF13?P6(AV\BC"IJN^CP]KEXAGQ9=P NSXL@[LHXKLFG#XQ]IRKMC65<]9%BS[G@/FGM[DU^FJUBBV<>]/CP]KEXAGUHIAB U^QWEQEJLVd8;6[?/H]UMJ)@MGUJ_T@L_HLX64[)IZSEORGA_BGOH*gtqgiTaxvPf^mvp61<]9%BS[G@/FGM[DU^FJUBBV<>]/CP]KEXAGUHIAB ar{mgZkrpVxTcxz<3:W3+LYQAF%LICQNSXL@[LH\:8W%M^WAC^KM[FCKD&lj`agag^mvp7`<]9%BS[G@/FGM[DU^FJUBBV<>]/CP]KEXAGUHIAB fe3\kpr5n2_;#DQYIN-DAKYF[PDHSD@T20_-EV_IKVCESNKCL.dg6Zir|;l0Y=!F_WKL+BCIWHYRBNQFNZ02Y+GTQGITECQLEMN,ba5Xg|~8<6[?/H]UMJ)@MGUJ_T@L_HLX64[)IZSEORGA_BGOH*krp8Udyy==;T2,MZPNG&MNBRO\YOA\MK]59T$J_T@L_HL\G@JK'{cxeciPotv05>S7'@U]EB!HEO]BW\HDW@DP><S!AR[MGZOIWJOG@"{|es]jjZh4;2_;#DQYIN-DAKYF[PDHSD@T23_-EV_IKVCESNKCL.CP]KEXNVG^T>=4U1-J[SOH'NOESL]VNB]JJ^45U'KXUCMPIO]@AIJ(IZSEOR\PMTZ01>S7'@U]EB!HEO]BW\HDW@DP>?S!AR[MGZOIWJOG@"]PAR[MGZ@XZLM8?6[?/H]UMJ)@MGUJ_T@L_HLX67[)IZSEORGA_BGOH*UXIZSEOR\JG278Q5)NW_CD#JKA_@QZJFYNFR89Q#O\YOA\MKYDMEF$_RO\YOA\VZTBO:80Y=!F_WKL+BCIWHYRBNQFNZ01Y+GTQGITECQLEMN,WZSTM[UYIJ=?;T2,MZPNG&MNBRO\YOA\MK]5:T$J_T@L_HL\G@JK'\YN^RCZX238Q5)NW_CD#JKA_@QZJFYNFR89Q#O\YOA\MKYDMEF$YRHNLMKMC66<]9%BS[G@/FGM[DU^FJUBBV<=]/CP]KEXAGUHIAB U^PJWLH@;:1^<"GPVHM,C@HXIZSEORGA[30^*DU^FJUBBRMJLM-V[VRF\JGOSc=8;T2,MZPNG&MNBRO\YOA\MK]5:T$J_T@L_HL\G@JK'hyrbnQbuy]e[jss;>1^<"GPVHM,C@HXIZSEORGA[30^*DU^FJUBBRMJLM-bw|hdWdsSQ`uu10?P6(AV\BC"IJN^CP]KEXAGQ9>P NSXL@[LHXKLFG#koclhld[jss:o1^<"GPVHM,C@HXIZSEORGA[30^*DU^FJUBBRMJLM-e`4Yh}}8m7X> I^TJK*ABFVKXUCMPIOY16X(F[PDHSD@PCDNO+cb5Wf>k5Z0.K\RLI(OLDTM^WAC^KM_74Z&HYRBNQFN^AFHI)al:Udyy=?;T2,MZPNG&MNBRO\YOA\MK]5:T$J_T@L_HL\G@JK'ds=Razt208Q5)NW_CD#JKA_@QZJFYNFR89Q#O\YOA\MKYDMEF$~d}fnf]lqq563\:$ERXFO.EFJZGTQGITECU=2\,BW\HDW@DTOHBC/tqfvZoiWg987X> I^TJK*ABFVKXUCMPIOY17X(F[PDHSD@PCDNO+DU^FJUMS@[W329V4*OX^@E$KH@PAR[MGZOIS;9V"L]VNB]JJZEBDE%J_T@L_S]NQ]523\:$ERXFO.EFJZGTQGITECU=3\,BW\HDW@DTOHBC/R]BW\HDWOUYIJ=<;T2,MZPNG&MNBRO\YOA\MK]5;T$J_T@L_HL\G@JK'ZUJ_T@L_SGD70=R8&CTZDA GDL\EV_IKVCEW?=R.@QZJFYNFVIN@A!\_@QZJFYUW[OL??5Z0.K\RLI(OLDTM^WAC^KM_75Z&HYRBNQFN^AFHI)TW\YN^R\JG228Q5)NW_CD#JKA_@QZJFYNFR88Q#O\YOA\MKYDMEF$Y^K]_LW[74=R8&CTZDA GDL\EV_IKVCEW?=R.@QZJFYNFVIN@A!Z_GCOHLH@;91^<"GPVHM,C@HXIZSEORGA[31^*DU^FJUBBRMJLM-V[WOTAGM8?6[?/H]UMJ)@MGUJ_T@L_HLX66[)IZSEORGA_BGOH*SX[]K_O@JPn258Q5)NW_CD#JKA_@QZJFYNFR88Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8;6[?/H]UMJ)@MGUJ_T@L_HLX66[)IZSEORGA_BGOH*gtqgiTaxvPr^mvp65<]9%BS[G@/FGM[DU^FJUBBV<<]/CP]KEXAGUHIAB f`nomkaXg|~9j6[?/H]UMJ)@MGUJ_T@L_HLX66[)IZSEORGA_BGOH*`c9Ve~x?h4U1-J[SOH'NOESL]VNB]JJ^44U'KXUCMPIO]@AIJ(nm8Tcxz=f:W3+LYQAF%LICQNSXL@[LH\::W%M^WAC^KM[FCKD&lo?Razt228Q5)NW_CD#JKA_@QZJFYNFR88Q#O\YOA\MKYDMEF$axv>_nww77=R8&CTZDA GDL\EV_IKVCEW?=R.@QZJFYNFVIN@A!}irkmcZir|:;0Y=!F_WKL+BCIWHYRBNQFNZ00Y+GTQGITECQLEMN,qvcuW`dTb>=4U1-J[SOH'NOESL]VNB]JJ^43U'KXUCMPIO]@AIJ(IZSEORHPMTZ07>S7'@U]EB!HEO]BW\HDW@DP>9S!AR[MGZOIWJOG@"O\YOA\VZKRP:?0Y=!F_WKL+BCIWHYRBNQFNZ07Y+GTQGITECQLEMN,WZGTQGITJR\JG218Q5)NW_CD#JKA_@QZJFYNFR8?Q#O\YOA\MKYDMEF$_RO\YOA\V@A4=2_;#DQYIN-DAKYF[PDHSD@T25_-EV_IKVCESNKCL.Q\EV_IKVXT^HI<2:W3+LYQAF%LICQNSXL@[LH\:=W%M^WAC^KM[FCKD&YTY^K]_SGD75=R8&CTZDA GDL\EV_IKVCEW?:R.@QZJFYNFVIN@A!ZSDP\IP^492_;#DQYIN-DAKYF[PDHSD@T25_-EV_IKVCESNKCL.W\BDJKAGM8<6[?/H]UMJ)@MGUJ_T@L_HLX61[)IZSEORGA_BGOH*SXZ@YBBJ=<;T2,MZPNG&MNBRO\YOA\MK]5<T$J_T@L_HL\G@JK'\UXXLZLME]m72=R8&CTZDA GDL\EV_IKVCEW?:R.@QZJFYNFVIN@A!nsxl`[hsWoUdyy=8;T2,MZPNG&MNBRO\YOA\MK]5<T$J_T@L_HL\G@JK'hyrbnQbuy]q[jss;:1^<"GPVHM,C@HXIZSEORGA[36^*DU^FJUBBRMJLM-eeijnfnUdyy<i;T2,MZPNG&MNBRO\YOA\MK]5<T$J_T@L_HL\G@JK'on:Sb{{2g9V4*OX^@E$KH@PAR[MGZOIS;>V"L]VNB]JJZEBDE%mh?Q`uu0e?P6(AV\BC"IJN^CP]KEXAGQ98P NSXL@[LHXKLFG#kj<_nww75=R8&CTZDA GDL\EV_IKVCEW?:R.@QZJFYNFVIN@A!buy3\kpr4:2_;#DQYIN-DAKYF[PDHSD@T25_-EV_IKVCESNKCL.pjwlh`Wf?<5Z0.K\RLI(OLDTM^WAC^KM_72Z&HYRBNQFN^AFHI)r{lxTecQa329V4*OX^@E$KH@PAR[MGZOIS;?V"L]VNB]JJZEBDE%J_T@L_G]NQ]543\:$ERXFO.EFJZGTQGITECU=5\,BW\HDW@DTOHBC/@QZJFYUWD_S?85Z0.K\RLI(OLDTM^WAC^KM_73Z&HYRBNQFN^AFHI)TWHYRBNQI_SGD76=R8&CTZDA GDL\EV_IKVCEW?;R.@QZJFYNFVIN@A!\_@QZJFYUMN9>7X> I^TJK*ABFVKXUCMPIOY11X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF11?P6(AV\BC"IJN^CP]KEXAGQ99P NSXL@[LHXKLFG#^QZSDP\V@A482_;#DQYIN-DAKYF[PDHSD@T24_-EV_IKVCESNKCL.WPAWYJ]Q9:7X> I^TJK*ABFVKXUCMPIOY11X(F[PDHSD@PCDNO+PYAIEFBBJ=?;T2,MZPNG&MNBRO\YOA\MK]5=T$J_T@L_HL\G@JK'\UYE^GAG218Q5)NW_CD#JKA_@QZJFYNFR8>Q#O\YOA\MKYDMEF$YR][AUAN@Zh4?2_;#DQYIN-DAKYF[PDHSD@T24_-EV_IKVCESNKCL.cp}keXe|rTjRazt258Q5)NW_CD#JKA_@QZJFYNFR8>Q#O\YOA\MKYDMEF$m~wac^ov|ZtXg|~8?6[?/H]UMJ)@MGUJ_T@L_HLX60[)IZSEORGA_BGOH*`fdecekRazt3d8Q5)NW_CD#JKA_@QZJFYNFR8>Q#O\YOA\MKYDMEF$ji?Potv1b>S7'@U]EB!HEO]BW\HDW@DP>8S!AR[MGZOIWJOG@"hk2^mvp7`<]9%BS[G@/FGM[DU^FJUBBV<:]/CP]KEXAGUHIAB fe1\kpr482_;#DQYIN-DAKYF[PDHSD@T24_-EV_IKVCESNKCL.ov|4Yh}}997X> I^TJK*ABFVKXUCMPIOY11X(F[PDHSD@PCDNO+wotagmTcxz<1:W3+LYQAF%LICQNSXL@[LH\:<W%M^WAC^KM[FCKD&xiQfn^l07>S7'@U]EB!HEO]BW\HDW@DP>;S!AR[MGZOIWJOG@"O\YOA\BZKRP:90Y=!F_WKL+BCIWHYRBNQFNZ05Y+GTQGITECQLEMN,EV_IKVXTAXV<5:W3+LYQAF%LICQNSXL@[LH\:?W%M^WAC^KM[FCKD&YTM^WAC^D\V@A4;2_;#DQYIN-DAKYF[PDHSD@T27_-EV_IKVCESNKCL.Q\EV_IKVXNK>;4U1-J[SOH'NOESL]VNB]JJ^41U'KXUCMPIO]@AIJ([VKXUCMPR^PFC64<]9%BS[G@/FGM[DU^FJUBBV<9]/CP]KEXAGUHIAB S^WPAWYUMN9;7X> I^TJK*ABFVKXUCMPIOY12X(F[PDHSD@PCDNO+PUBZVG^T>?4U1-J[SOH'NOESL]VNB]JJ^41U'KXUCMPIO]@AIJ(]VLJ@AGAG228Q5)NW_CD#JKA_@QZJFYNFR8=Q#O\YOA\MKYDMEF$YR\FSHLD76=R8&CTZDA GDL\EV_IKVCEW?8R.@QZJFYNFVIN@A!Z_RVBPFKCWg9<7X> I^TJK*ABFVKXUCMPIOY12X(F[PDHSD@PCDNO+du~fjUfyuQi_nww72=R8&CTZDA GDL\EV_IKVCEW?8R.@QZJFYNFVIN@A!nsxl`[hsW{Udyy=<;T2,MZPNG&MNBRO\YOA\MK]5>T$J_T@L_HL\G@JK'okg`d`h_nww6c=R8&CTZDA GDL\EV_IKVCEW?8R.@QZJFYNFVIN@A!id0]lqq4a3\:$ERXFO.EFJZGTQGITECU=6\,BW\HDW@DTOHBC/gf1[jss:o1^<"GPVHM,C@HXIZSEORGA[34^*DU^FJUBBRMJLM-e`6Yh}}9;7X> I^TJK*ABFVKXUCMPIOY12X(F[PDHSD@PCDNO+hs9Ve~x><4U1-J[SOH'NOESL]VNB]JJ^41U'KXUCMPIO]@AIJ(z`ybbjQ`uu12?P6(AV\BC"IJN^CP]KEXAGQ9:P NSXL@[LHXKLFG#x}jr^km[k543\:$ERXFO.EFJZGTQGITECU=7\,BW\HDW@DTOHBC/@QZJFYAWD_S?>5Z0.K\RLI(OLDTM^WAC^KM_71Z&HYRBNQFN^AFHI)F[PDHS_QBUY16?P6(AV\BC"IJN^CP]KEXAGQ9;P NSXL@[LHXKLFG#^QNSXL@[CYUMN987X> I^TJK*ABFVKXUCMPIOY13X(F[PDHSD@PCDNO+VYF[PDHS_KH349V4*OX^@E$KH@PAR[MGZOIS;=V"L]VNB]JJZEBDE%XSL]VNB]Q[WC@;;1^<"GPVHM,C@HXIZSEORGA[35^*DU^FJUBBRMJLM-P[PUBZVXNK>>4U1-J[SOH'NOESL]VNB]JJ^40U'KXUCMPIO]@AIJ(]ZOYS@[W309V4*OX^@E$KH@PAR[MGZOIS;=V"L]VNB]JJZEBDE%^SKOCLHLD75=R8&CTZDA GDL\EV_IKVCEW?9R.@QZJFYNFVIN@A!Z_SKPMKA4;2_;#DQYIN-DAKYF[PDHSD@T26_-EV_IKVCESNKCL.W\WQGSKDNTb>94U1-J[SOH'NOESL]VNB]JJ^40U'KXUCMPIO]@AIJ(izseoRczx^d\kpr4?2_;#DQYIN-DAKYF[PDHSD@T26_-EV_IKVCESNKCL.cp}keXe|rT~Razt218Q5)NW_CD#JKA_@QZJFYNFR8<Q#O\YOA\MKYDMEF$jlbcioe\kpr5n2_;#DQYIN-DAKYF[PDHSD@T26_-EV_IKVCESNKCL.dg5Zir|;l0Y=!F_WKL+BCIWHYRBNQFNZ04Y+GTQGITECQLEMN,ba4Xg|~9j6[?/H]UMJ)@MGUJ_T@L_HLX62[)IZSEORGA_BGOH*`c;Ve~x>>4U1-J[SOH'NOESL]VNB]JJ^40U'KXUCMPIO]@AIJ(e|r:Sb{{339V4*OX^@E$KH@PAR[MGZOIS;=V"L]VNB]JJZEBDE%ye~gag^mvp67<]9%BS[G@/FGM[DU^FJUBBV<8]/CP]KEXAGUHIAB urgq[lhXf:90Y=!F_WKL+BCIWHYRBNQFNZ0;Y+GTQGITECQLEMN,EV_IKVLTAXV<3:W3+LYQAF%LICQNSXL@[LH\:1W%M^WAC^KM[FCKD&KXUCMPR^OV\63<]9%BS[G@/FGM[DU^FJUBBV<7]/CP]KEXAGUHIAB S^CP]KEXNVXNK>=4U1-J[SOH'NOESL]VNB]JJ^4?U'KXUCMPIO]@AIJ([VKXUCMPRDE01>S7'@U]EB!HEO]BW\HDW@DP>5S!AR[MGZOIWJOG@"]PAR[MGZTXZLM8>6[?/H]UMJ)@MGUJ_T@L_HLX6=[)IZSEORGA_BGOH*UX]ZOYS_KH319V4*OX^@E$KH@PAR[MGZOIS;2V"L]VNB]JJZEBDE%^_H\PMTZ05>S7'@U]EB!HEO]BW\HDW@DP>5S!AR[MGZOIWJOG@"[PF@NOMKA482_;#DQYIN-DAKYF[PDHSD@T29_-EV_IKVCESNKCL.W\VLUNFN987X> I^TJK*ABFVKXUCMPIOY1<X(F[PDHSD@PCDNO+PYT\H^HAIQa369V4*OX^@E$KH@PAR[MGZOIS;2V"L]VNB]JJZEBDE%jt`l_lw{[cYh}}9<7X> I^TJK*ABFVKXUCMPIOY1<X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww76=R8&CTZDA GDL\EV_IKVCEW?6R.@QZJFYNFVIN@A!iamnjjbYh}}8m7X> I^TJK*ABFVKXUCMPIOY1<X(F[PDHSD@PCDNO+cb6Wf>k5Z0.K\RLI(OLDTM^WAC^KM_7>Z&HYRBNQFN^AFHI)al;Udyy<i;T2,MZPNG&MNBRO\YOA\MK]50T$J_T@L_HL\G@JK'on8Sb{{319V4*OX^@E$KH@PAR[MGZOIS;2V"L]VNB]JJZEBDE%fyu?Potv06>S7'@U]EB!HEO]BW\HDW@DP>5S!AR[MGZOIWJOG@"|fshld[jss;81^<"GPVHM,C@HXIZSEORGA[3:^*DU^FJUBBRMJLM-vw`tXagUe?>5Z0.K\RLI(OLDTM^WAC^KM_7?Z&HYRBNQFN^AFHI)F[PDHSKQBUY10?P6(AV\BC"IJN^CP]KEXAGQ95P NSXL@[LHXKLFG#L]VNB]Q[HS_;<1^<"GPVHM,C@HXIZSEORGA[3;^*DU^FJUBBRMJLM-P[DU^FJUMS_KH329V4*OX^@E$KH@PAR[MGZOIS;3V"L]VNB]JJZEBDE%XSL]VNB]QAB523\:$ERXFO.EFJZGTQGITECU=9\,BW\HDW@DTOHBC/R]BW\HDW[UYIJ==;T2,MZPNG&MNBRO\YOA\MK]51T$J_T@L_HL\G@JK'ZU^_H\PRDE04>S7'@U]EB!HEO]BW\HDW@DP>4S!AR[MGZOIWJOG@"[\ES]NQ]563\:$ERXFO.EFJZGTQGITECU=9\,BW\HDW@DTOHBC/T]EEIJNFN9;7X> I^TJK*ABFVKXUCMPIOY1=X(F[PDHSD@PCDNO+PYUAZCEK>=4U1-J[SOH'NOESL]VNB]JJ^4>U'KXUCMPIO]@AIJ(]VY_MYMBD^l03>S7'@U]EB!HEO]BW\HDW@DP>4S!AR[MGZOIWJOG@"o|yoa\ip~XnVe~x>94U1-J[SOH'NOESL]VNB]JJ^4>U'KXUCMPIO]@AIJ(izseoRczx^p\kpr4;2_;#DQYIN-DAKYF[PDHSD@T28_-EV_IKVCESNKCL.dbhioioVe~x?h4U1-J[SOH'NOESL]VNB]JJ^4>U'KXUCMPIO]@AIJ(nm;Tcxz=f:W3+LYQAF%LICQNSXL@[LH\:0W%M^WAC^KM[FCKD&lo>Razt3d8Q5)NW_CD#JKA_@QZJFYNFR82Q#O\YOA\MKYDMEF$ji=Potv04>S7'@U]EB!HEO]BW\HDW@DP>4S!AR[MGZOIWJOG@"czx0]lqq553\:$ERXFO.EFJZGTQGITECU=9\,BW\HDW@DTOHBC/skpmkaXg|~8=6[?/H]UMJ)@MGUJ_T@L_HLX6<[)IZSEORGA_BGOH*stm{UbbR`<2:W3+LYQAF%LICQNSXL@[LH\:T$J_T@L_HL\G@JK'HYRBNQI_LW[77=R8&CTZDA GDL\EV_IKVCEW?S!AR[MGZOIWJOG@"O\YOA\VZKRP:>0Y=!F_WKL+BCIWHYRBNQFNZ0^*DU^FJUBBRMJLM-P[DU^FJUMS_KH339V4*OX^@E$KH@PAR[MGZOIS;W%M^WAC^KM[FCKD&YTM^WAC^PFC62<]9%BS[G@/FGM[DU^FJUBBV<R.@QZJFYNFVIN@A!\_@QZJFYUW[OL?<5Z0.K\RLI(OLDTM^WAC^KM_7[)IZSEORGA_BGOH*UX]ZOYS_KH2g9V4*OX^@E$KH@PAR[MGZOIS;W%M^WAC^KM[FCKD&_XI_QBUY13?P6(AV\BC"IJN^CP]KEXAGQ9Q#O\YOA\MKYDMEF$YRHNLMKMC7`<]9%BS[G@/FGM[DU^FJUBBV<R.@QZJFYNFVIN@A!Z_SKPMKA4:2_;#DQYIN-DAKYF[PDHSD@T2\,BW\HDW@DTOHBC/T]PPDRDEMUe?;5Z0.K\RLI(OLDTM^WAC^KM_7[)IZSEORGA_BGOH*gtqgiTaxvPf^mvp60<]9%BS[G@/FGM[DU^FJUBBV<R.@QZJFYNFVIN@A!nsxl`[hsW{Udyy==;T2,MZPNG&MNBRO\YOA\MK]5U'KXUCMPIO]@AIJ(nhfgeciPotv1a>S7'@U]EB!HEO]BW\HDW@DP>P NSXL@[LHXKLFG#kj>_nww6`=R8&CTZDA GDL\EV_IKVCEW?S!AR[MGZOIWJOG@"hk2^mvp7c<]9%BS[G@/FGM[DU^FJUBBV<R.@QZJFYNFVIN@A!id2]lqq4a3\:$ERXFO.EFJZGTQGITECU=]/CP]KEXAGUHIAB mtz2[jss;81^<"GPVHM,C@HXIZSEORGA[3_-EV_IKVCESNKCL.pjwlh`Wf?=5Z0.K\RLI(OLDTM^WAC^KM_7[)IZSEORGA_BGOH*stm{UbbR`<3:W3+LYQAF%LICQNSXL@[LH\;9W%M^WAC^KM[FCKD&KXUCMPF^OV\65<]9%BS[G@/FGM[DU^FJUBBV=?]/CP]KEXAGUHIAB AR[MGZTXE\R896[?/H]UMJ)@MGUJ_T@L_HLX75[)IZSEORGA_BGOH*UXIZSEORHPRDE07>S7'@U]EB!HEO]BW\HDW@DP?=S!AR[MGZOIWJOG@"]PAR[MGZTBO:?0Y=!F_WKL+BCIWHYRBNQFNZ13Y+GTQGITECQLEMN,WZGTQGIT^R\JG208Q5)NW_CD#JKA_@QZJFYNFR9;Q#O\YOA\MKYDMEF$_R[\ES]QAB573\:$ERXFO.EFJZGTQGITECU<0\,BW\HDW@DTOHBC/TQFVZKRP:;0Y=!F_WKL+BCIWHYRBNQFNZ13Y+GTQGITECQLEMN,QZ@FDECEK>>4U1-J[SOH'NOESL]VNB]JJ^57U'KXUCMPIO]@AIJ(]VXB_D@H329V4*OX^@E$KH@PAR[MGZOIS::V"L]VNB]JJZEBDE%^S^ZNTBOG[k503\:$ERXFO.EFJZGTQGITECU<0\,BW\HDW@DTOHBC/`qzjfYj}qUmSb{{369V4*OX^@E$KH@PAR[MGZOIS::V"L]VNB]JJZEBDE%jt`l_lw{[wYh}}987X> I^TJK*ABFVKXUCMPIOY04X(F[PDHSD@PCDNO+cgkd`dlSb{{2g9V4*OX^@E$KH@PAR[MGZOIS::V"L]VNB]JJZEBDE%mh<Q`uu0e?P6(AV\BC"IJN^CP]KEXAGQ8<P NSXL@[LHXKLFG#kj=_nww6c=R8&CTZDA GDL\EV_IKVCEW>>R.@QZJFYNFVIN@A!id2]lqq573\:$ERXFO.EFJZGTQGITECU<0\,BW\HDW@DTOHBC/lw{5Zir|:80Y=!F_WKL+BCIWHYRBNQFNZ13Y+GTQGITECQLEMN,vlunfnUdyy=>;T2,MZPNG&MNBRO\YOA\MK]48T$J_T@L_HL\G@JK'|yn~Rga_o10?P6(AV\BC"IJN^CP]KEXAGQ8=P NSXL@[LHXKLFG#L]VNB]E[HS_;:1^<"GPVHM,C@HXIZSEORGA[23^*DU^FJUBBRMJLM-BW\HDW[UFYU=:;T2,MZPNG&MNBRO\YOA\MK]49T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB543\:$ERXFO.EFJZGTQGITECU<1\,BW\HDW@DTOHBC/R]BW\HDW[OL?85Z0.K\RLI(OLDTM^WAC^KM_67Z&HYRBNQFN^AFHI)TWHYRBNQ]_SGD77=R8&CTZDA GDL\EV_IKVCEW>?R.@QZJFYNFVIN@A!\_TQFVZTBO::0Y=!F_WKL+BCIWHYRBNQFNZ12Y+GTQGITECQLEMN,QVCUWD_S?<5Z0.K\RLI(OLDTM^WAC^KM_67Z&HYRBNQFN^AFHI)RWOKG@D@H319V4*OX^@E$KH@PAR[MGZOIS:;V"L]VNB]JJZEBDE%^S_G\IOE07>S7'@U]EB!HEO]BW\HDW@DP?<S!AR[MGZOIWJOG@"[PSUCWGHBXf:=0Y=!F_WKL+BCIWHYRBNQFNZ12Y+GTQGITECQLEMN,evikVg~tRhPotv03>S7'@U]EB!HEO]BW\HDW@DP?<S!AR[MGZOIWJOG@"o|yoa\ip~XzVe~x>=4U1-J[SOH'NOESL]VNB]JJ^56U'KXUCMPIO]@AIJ(nhfgeciPotv1b>S7'@U]EB!HEO]BW\HDW@DP?<S!AR[MGZOIWJOG@"hk1^mvp7`<]9%BS[G@/FGM[DU^FJUBBV=>]/CP]KEXAGUHIAB fe0\kpr5n2_;#DQYIN-DAKYF[PDHSD@T30_-EV_IKVCESNKCL.dg7Zir|::0Y=!F_WKL+BCIWHYRBNQFNZ12Y+GTQGITECQLEMN,ip~6Wf??5Z0.K\RLI(OLDTM^WAC^KM_67Z&HYRBNQFN^AFHI)uazcekRazt238Q5)NW_CD#JKA_@QZJFYNFR9:Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV=R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY0Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\;T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU<]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX7X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ8Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU<]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[2_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX7X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^5Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ8Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX7X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW>S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ1^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY0Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX7X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_6[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]4U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ8Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV:R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY7Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\<T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU;]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX0X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ?Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU;]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[5_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX0X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^2Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ?Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX0X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW9S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ6^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY7Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX0X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_1[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]3U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ?Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV;R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY6Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\=T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU:]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX1X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ>Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU:]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[4_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX1X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^3Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ>Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX1X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW8S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ7^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY6Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX1X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_0[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]2U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ>Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV8R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY5Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\>T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU9]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX2X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ=Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU9]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[7_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX2X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^0Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ=Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX2X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW;S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ4^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY5Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX2X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_3[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]1U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ=Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV9R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY4Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\?T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU8]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX3X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ<Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU8]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[6_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX3X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^1Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ<Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX3X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW:S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ5^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY4Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX3X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_2[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]0U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ<Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV6R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY;Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\0T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU7]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX<X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ3Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU7]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[9_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX<X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^>Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ3Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX<X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW5S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ:^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY;Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX<X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_=[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]?U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ3Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUBBV7R.@QZJFYNFVIN@A!NSXL@[CYJ]Q997X> I^TJK*ABFVKXUCMPIOY:Y+GTQGITECQLEMN,EV_IKVXTAXV<4:W3+LYQAF%LICQNSXL@[LH\1T$J_T@L_HL\G@JK'ZUJ_T@L_G]QAB553\:$ERXFO.EFJZGTQGITECU6]/CP]KEXAGUHIAB S^CP]KEXZLM886[?/H]UMJ)@MGUJ_T@L_HLX=X(F[PDHSD@PCDNO+VYF[PDHS_Q]EF12?P6(AV\BC"IJN^CP]KEXAGQ2Q#O\YOA\MKYDMEF$_R[\ES]QAB4a3\:$ERXFO.EFJZGTQGITECU6]/CP]KEXAGUHIAB URGQ[HS_;91^<"GPVHM,C@HXIZSEORGA[8_-EV_IKVCESNKCL.W\BDJKAGM9j6[?/H]UMJ)@MGUJ_T@L_HLX=X(F[PDHSD@PCDNO+PYUAZCEK><4U1-J[SOH'NOESL]VNB]JJ^?Z&HYRBNQFN^AFHI)RWZ^JXNCK_o15?P6(AV\BC"IJN^CP]KEXAGQ2Q#O\YOA\MKYDMEF$m~wac^ov|Z`Xg|~8:6[?/H]UMJ)@MGUJ_T@L_HLX=X(F[PDHSD@PCDNO+du~fjUfyuQ}_nww77=R8&CTZDA GDL\EV_IKVCEW4S!AR[MGZOIWJOG@"hnlmkmcZir|;o0Y=!F_WKL+BCIWHYRBNQFNZ;^*DU^FJUBBRMJLM-e`4Yh}}8n7X> I^TJK*ABFVKXUCMPIOY:Y+GTQGITECQLEMN,ba4Xg|~9i6[?/H]UMJ)@MGUJ_T@L_HLX=X(F[PDHSD@PCDNO+cb4Wf>k5Z0.K\RLI(OLDTM^WAC^KM_<[)IZSEORGA_BGOH*krp8Udyy=>;T2,MZPNG&MNBRO\YOA\MK]>U'KXUCMPIO]@AIJ(z`ybbjQ`uu13?P6(AV\BC"IJN^CP]KEXAGQ2Q#O\YOA\MKYDMEF$y~k}_hl\j64<]9%BS[G@/FGM[DU^FJUDYYU?]/CP]KEXG\^TOHBC/RJJBQYUMN9:7X> I^TJK*ABFVKXUCMPOTVX4X(F[PDHSB[[_BGOH*STM[UYIJ=<;T2,MZPNG&MNBRO\YOA\KPR\99W%M^WAC^MVPZEBDE%XDDH[_SGD77=R8&CTZDA GDL\EV_IKVE^XV??]/CP]KEXG\^TOHBC/TQFVZTBO:90Y=!F_WKL+BCIWHYRBNQ@UUY25X(F[PDHSB[[_BGOH*UOAO^T^HI<2:W3+LYQAF%LICQNSXL@[JSSS8;V"L]VNB]LQQYDMEF$Y^K]_SGD76=R8&CTZDA GDL\EV_IKVE^XV?=]/CP]KEXG\^TOHBC/RJJBQYUMN997X> I^TJK*ABFVKXUCMPOTVX57[)IZSEORAZT^AFHI)R[LXT^HI<3:W3+LYQAF%LICQNSXL@[JSSS89V"L]VNB]LQQYDMEF$_EGIT^PFC64<]9%BS[G@/FGM[DU^FJUDYYU>3\,BW\HDWF__SNKCL.WPAWYUMN987X> I^TJK*ABFVKXUCMPOTVX51[)IZSEORAZT^AFHI)T@@L_S_KH339V4*OX^@E$KH@PAR[MGZIR\R;?Q#O\YOA\KPRXKLFG#X]JR^PFC65<]9%BS[G@/FGM[DU^FJUDYYU>5\,BW\HDWF__SNKCL.QKMCRXZLM8>6[?/H]UMJ)@MGUJ_T@L_NWW_43Z&HYRBNQ@UU]@AIJ(]ZOYS_KH329V4*OX^@E$KH@PAR[MGZIR\R;=Q#O\YOA\KPRXKLFG#^FFFU]QAB553\:$ERXFO.EFJZGTQGITCXZT17_-EV_IKVE^XRMJLM-VW@TXZLM8?6[?/H]UMJ)@MGUJ_T@L_NWW_41Z&HYRBNQ@UU]@AIJ([ACMXR\JG208Q5)NW_CD#JKA_@QZJFYH]]Q:;P NSXL@[JSSWJOG@"[\ES]QAB543\:$ERXFO.EFJZGTQGITCXZT19_-EV_IKVE^XRMJLM-PLL@SW[OL??5Z0.K\RLI(OLDTM^WAC^MVP^7?U'KXUCMPOTV\G@JK'\YN^R\JG218Q5)NW_CD#JKA_@QZJFYH]]Q:5P NSXL@[JSSWJOG@"]GIGV\V@A4:2_;#DQYIN-DAKYF[PDHSB[[[0;^*DU^FJUDYYQLEMN,QVCUW[OL??5Z0.K\RLI(OLDTM^WAC^MVP^7Z&HYRBNQ@UU]@AIJ([ACMXR\JG238Q5)NW_CD#JKA_@QZJFYH]]Q:Q#O\YOA\KPRXKLFG#X]JR^PFC65<]9%BS[G@/FGM[DU^FJUDYYU=0\,BW\HDWF__SNKCL.QKMCRXZLM8>6[?/H]UMJ)@MGUJ_T@L_NWW_76Z&HYRBNQ@UU]@AIJ(]ZOYS_KH329V4*OX^@E$KH@PAR[MGZIR\R8:Q#O\YOA\KPRXKLFG#^FFFU]QAB553\:$ERXFO.EFJZGTQGITCXZT20_-EV_IKVE^XRMJLM-VW@TXZLM8?6[?/H]UMJ)@MGUJ_T@L_NWW_74Z&HYRBNQ@UU]@AIJ([ACMXR\JG208Q5)NW_CD#JKA_@QZJFYH]]Q9>P NSXL@[JSSWJOG@"[\ES]QAB543\:$ERXFO.EFJZGTQGITCXZT22_-EV_IKVE^XRMJLM-PLL@SW[OL??5Z0.K\RLI(OLDTM^WAC^MVP^44U'KXUCMPOTV\G@JK'\YN^R\JG218Q5)NW_CD#JKA_@QZJFYH]]Q98P NSXL@[JSSWJOG@"]GIGV\V@A4:2_;#DQYIN-DAKYF[PDHSB[[[36^*DU^FJUDYYQLEMN,QVCUW[OL?>5Z0.K\RLI(OLDTM^WAC^MVP^42U'KXUCMPOTV\G@JK'ZBBJYQ]EF11?P6(AV\BC"IJN^CP]KEXG\^P>8S!AR[MGZIR\VIN@A!ZSDP\V@A4;2_;#DQYIN-DAKYF[PDHSB[[[34^*DU^FJUDYYQLEMN,WMOA\VXNK><4U1-J[SOH'NOESL]VNB]LQQ]5>T$J_T@L_NWW[FCKD&_XI_Q]EF10?P6(AV\BC"IJN^CP]KEXG\^P>:S!AR[MGZIR\VIN@A!\HHDW[WC@;;1^<"GPVHM,C@HXIZSEORAZTZ04Y+GTQGITCXZPCDNO+PUBZVXNK>=4U1-J[SOH'NOESL]VNB]LQQ]50T$J_T@L_NWW[FCKD&YCEKZPRDE06>S7'@U]EB!HEO]BW\HDWF__W?6R.@QZJFYH]]UHIAB URGQ[WC@;:1^<"GPVHM,C@HXIZSEORAZTZ0:Y+GTQGITCXZPCDNO+VNNN]UYIJ==;T2,MZPNG&MNBRO\YOA\KPR\:0W%M^WAC^MVPZEBDE%^_H\PRDE06>S7'@U]EB!HEO]BW\HDWF__W?S!AR[MGZIR\VIN@A!\HHDW[WC@;81^<"GPVHM,C@HXIZSEORAZTZ0^*DU^FJUDYYQLEMN,QVCUW[OL?>5Z0.K\RLI(OLDTM^WAC^MVP^57U'KXUCMPOTV\G@JK'ZBBJYQ]EF11?P6(AV\BC"IJN^CP]KEXG\^P?=S!AR[MGZIR\VIN@A!ZSDP\V@A4;2_;#DQYIN-DAKYF[PDHSB[[[23^*DU^FJUDYYQLEMN,WMOA\VXNK><4U1-J[SOH'NOESL]VNB]LQQ]49T$J_T@L_NWW[FCKD&_XI_Q]EF11?P6(AV\BC"IJN^CP]KEXG\^P?P NSXL@[JSSWJOG@"]GIGV\V@A492_;#DQYIN-DAKYF[PDHSB[[[2_-EV_IKVE^XRMJLM-VW@TXZLM8>6[?/H]UMJ)@MGUJ_T@L_NWW_1[)IZSEORAZT^AFHI)T@@L_S_KH309V4*OX^@E$KH@PAR[MGZIR\R>V"L]VNB]LQQYDMEF$Y^K]_SGD77=R8&CTZDA GDL\EV_IKVE^XV;R.@QZJFYH]]UHIAB SIKEPZTBO:;0Y=!F_WKL+BCIWHYRBNQ@UUY6Y+GTQGITCXZPCDNO+PUBZVXNK><4U1-J[SOH'NOESL]VNB]LQQ]1U'KXUCMPOTV\G@JK'ZBBJYQ]EF12?P6(AV\BC"IJN^CP]KEXG\^P:P NSXL@[JSSWJOG@"[\ES]QAB553\:$ERXFO.EFJZGTQGITCXZT7\,BW\HDWF__SNKCL.QKMCRXZLM8=6[?/H]UMJ)@MGUJ_T@L_NWW_2[)IZSEORAZT^AFHI)R[LXT^HI<2:W3+LYQAF%LICQNSXL@[JSSS1W%M^WAC^MVPZEBDE%XDDH[_SGD74=R8&CTZDA GDL\EV_IKVE^XV6R.@QZJFYH]]UHIAB URGQ[WC@;;1^<"GPVHM,C@HXIZSEORAZTZ;^*DU^FJUDYYQLEMN,WMOA\VXNK>?4U1-J[SOH'NOESL]VNB]LQQ]>U'KXUCMPOTV\G@JK'\YN^R\JG238Q5)NW_CD#JKA_R[MGZOIS:8V"^WAC^KM[FCKD&KXUCMPF^OV\67<]9%BS[G@/FGM[V_IKVCEW><R.R[MGZOIWJOG@"O\YOA\VZKRP;l0Y=!F_WKL+BCIWZSEORGA[20^*V_IKVCESNKCL.QKMCRXZLM8<6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,W\HDWOUFYU=?;T2,MZPNG&MNBR]VNB]JJ^55U'YRBNQFN^AFHI)TQGIT^RCZX218Q5)NW_CD#JKA_R[MGZOIS:8V"^WAC^KM[FCKD&YTM^WAC^D\V@A4;2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB S^CP]KEXZVXNK><4U1-J[SOH'NOES^WAC^KM_64Z&ZSEORGA_BGOH*UX[PDHSKQ]EF11?P6(AV\BC"IJN^QZJFYNFR99Q#]VNB]JJZEBDE%XS^WAC^P\V@A4:2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB URGQ[FJLW[OL>h5Z0.K\RLI(OLDT_T@L_HLX77[)[PDHSD@PCDNO+PUBZVG^T?k4U1-J[SOH'NOES^WAC^KM_64Z&ZSEORGA_BGOH*STM[UYIJ<i;T2,MZPNG&MNBR]VNB]JJ^55U'YRBNQFN^AFHI)RWOKG@D@H2d9V4*OX^@E$KH@PSXL@[LH\;;W%_T@L_HL\G@JK'\UYE^GAG238Q5)NW_CD#JKA_R[MGZOIS:8V"^WAC^KM[FCKD&_T_YO[CLF\j7c<]9%BS[G@/FGM[V_IKVCEW><R.R[MGZOIWJOG@"[PSXL@[C4b3\:$ERXFO.EFJZU^FJUBBV==]/QZJFYNFVIN@A!Z_R[MGZT4=2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB ar{mgZkrpVlTcxz<5:W3+LYQAF%LICQ\YOA\MK]4:T$XUCMPIO]@AIJ(izseoRczx^p\kpr5l2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB cmm`o`b5l2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB f`nomka492_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB f`nomkaXg|~9h6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ba7Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ba4Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ba5Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ba2Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ba3Xg|~9i6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,ip~6Wf>n5Z0.K\RLI(OLDT_T@L_HLX77[)[PDHSD@PCDNO+wotagm8<6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,vlunfnUdyy=j;T2,MZPNG&MNBR]VNB]JJ^55U'YRBNQFN^AFHI)tqgiTjRkkgd-J[M4K&\UOCXZ<9:W3+LYQAF%LICQ\YOA\MK]4:T$XUCMPIO]@AIJ({pdhSkQjdfg,QZBH]]:856[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,w|hdWoUnhjk U^FLQQ74i2_;#DQYIN-DAKYTQGITECU<2\,P]KEXAGUHIAB sxl`[cYblno$eIAZT=2=7d=R8&CTZDA GDL\W\HDW@DP??S!SXL@[LHXKLFG#~wac^d\aaab'`NDYY2>>228Q5)NW_CD#JKA_R[MGZOIS:8V"^WAC^KM[FCKD&yrbnQi_nww71=R8&CTZDA GDL\W\HDW@DP??S!SXL@[LHXKLFG#~wac^ov|Z`Xg|~886[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,w|hdWdsSQ`uu1f?P6(AV\BC"IJN^QZJFYNFR99Q#]VNB]JJZEBDE%xucmPr^ggc`)NWE8C"XQKOTV0=>S7'@U]EB!HEO]P]KEXAGQ8>P \YOA\MKYDMEF$t`l_s]f`bc(]VNDYY><9:W3+LYQAF%LICQ\YOA\MK]4:T$XUCMPIO]@AIJ({pdhSQjdfg,QZBH]];8m6[?/H]UMJ)@MGUXUCMPIOY06X(TQGITECQLEMN,w|hdW{Unhjk iEMVP969;h1^<"GPVHM,C@HX[PDHSD@T33_-W\HDW@DTOHBC/r{mgZtXmmmn#dJ@UU>2:66<]9%BS[G@/FGM[V_IKVCEW><R.R[MGZOIWJOG@"}vnb]q[jss:o1^<"GPVHM,C@HX[PDHSD@T33_-W\HDW@DTOHBC/tqfvZoiWg9:7X> I^TJK*ABFVYRBNQFNZ10Y+U^FJUBBRMJLM-BW\HDWOUFYU=>;T2,MZPNG&MNBR]VNB]JJ^54U'YRBNQFN^AFHI)F[PDHS_QBUY0e?P6(AV\BC"IJN^QZJFYNFR98Q#]VNB]JJZEBDE%XDDH[_SGD75=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#^WAC^D\IP^482_;#DQYIN-DAKYTQGITECU<3\,P]KEXAGUHIAB SXL@[WYJ]Q987X> I^TJK*ABFVYRBNQFNZ10Y+U^FJUBBRMJLM-P[DU^FJUMS_KH329V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'ZUJ_T@L_S]QAB553\:$ERXFO.EFJZU^FJUBBV=<]/QZJFYNFVIN@A!\_R[MGZ@XZLM8>6[?/H]UMJ)@MGUXUCMPIOY07X(TQGITECQLEMN,WZU^FJUYS_KH339V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'\YN^RMCK^PFC7c<]9%BS[G@/FGM[V_IKVCEW>=R.R[MGZOIWJOG@"[\ES]NQ]4b3\:$ERXFO.EFJZU^FJUBBV=<]/QZJFYNFVIN@A!ZSDP\V@A5n2_;#DQYIN-DAKYTQGITECU<3\,P]KEXAGUHIAB U^DBHIOIO;o0Y=!F_WKL+BCIWZSEORGA[21^*V_IKVCESNKCL.W\VLUNFN9:7X> I^TJK*ABFVYRBNQFNZ10Y+U^FJUBBRMJLM-V[VRF\JGOSc<j;T2,MZPNG&MNBR]VNB]JJ^54U'YRBNQFN^AFHI)RWZSEORH=e:W3+LYQAF%LICQ\YOA\MK]4;T$XUCMPIO]@AIJ(]VYRBNQ]349V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'hyrbnQbuy]e[jss;<1^<"GPVHM,C@HX[PDHSD@T32_-W\HDW@DTOHBC/`qzjfYj}qUySb{{2e9V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'jfdofkk2e9V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'okg`d`h309V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'okg`d`h_nww6a=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#kj>_nww6a=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#kj=_nww6a=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#kj<_nww6a=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#kj;_nww6a=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#kj:_nww6`=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#`{w1^mvp7e<]9%BS[G@/FGM[V_IKVCEW>=R.R[MGZOIWJOG@"|fshld75=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#g|ioe\kpr4m2_;#DQYIN-DAKYTQGITECU<3\,P]KEXAGUHIAB sxl`[cYblno$ERF=L/W\@JSS;01^<"GPVHM,C@HX[PDHSD@T32_-W\HDW@DTOHBC/r{mgZ`Xmmmn#XQKOTV37<=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#~wac^d\aaab'\UOCXZ>3`9V4*OX^@E$KH@PSXL@[LH\;:W%_T@L_HL\G@JK'zseoRhPeeef+lBH]]6;2>o4U1-J[SOH'NOES^WAC^KM_65Z&ZSEORGA_BGOH*u~fjUmShjhe.kGKPR;979;7X> I^TJK*ABFVYRBNQFNZ10Y+U^FJUBBRMJLM-p}keXnVe~x>:4U1-J[SOH'NOES^WAC^KM_65Z&ZSEORGA_BGOH*u~fjUfyuQi_nww71=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#~wac^ov|ZtXg|~8i6[?/H]UMJ)@MGUXUCMPIOY07X(TQGITECQLEMN,w|hdW{Unhjk I^N1L+SXLF__?45Z0.K\RLI(OLDT_T@L_HLX76[)[PDHSD@PCDNO+vikVxTiiij/T]GKPR7;01^<"GPVHM,C@HX[PDHSD@T32_-W\HDW@DTOHBC/r{mgZtXmmmn#XQKOTV27d=R8&CTZDA GDL\W\HDW@DP?>S!SXL@[LHXKLFG#~wac^p\aaab'`NDYY2?>2c8Q5)NW_CD#JKA_R[MGZOIS:9V"^WAC^KM[FCKD&yrbnQ}_dfda*oCG\^7=3=?;T2,MZPNG&MNBR]VNB]JJ^54U'YRBNQFN^AFHI)tqgiT~Razt3d8Q5)NW_CD#JKA_R[MGZOIS:9V"^WAC^KM[FCKD&xiQfn^l05>S7'@U]EB!HEO]P]KEXAGQ88P \YOA\MKYDMEF$M^WAC^D\IP^492_;#DQYIN-DAKYTQGITECU<4\,P]KEXAGUHIAB AR[MGZTXE\R9j6[?/H]UMJ)@MGUXUCMPIOY00X(TQGITECQLEMN,WMOA\VXNK>>4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*U^FJUMS@[W319V4*OX^@E$KH@PSXL@[LH\;=W%_T@L_HL\G@JK'ZSEOR\PMTZ07>S7'@U]EB!HEO]P]KEXAGQ88P \YOA\MKYDMEF$_RO\YOA\BZTBO:90Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.Q\EV_IKVXT^HI<2:W3+LYQAF%LICQ\YOA\MK]4<T$XUCMPIO]@AIJ([VYRBNQI_SGD77=R8&CTZDA GDL\W\HDW@DP?9S!SXL@[LHXKLFG#^Q\YOA\VZTBO:80Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.WPAWYDDBUYIJ<j;T2,MZPNG&MNBR]VNB]JJ^53U'YRBNQFN^AFHI)R[LXTAXV=e:W3+LYQAF%LICQ\YOA\MK]4<T$XUCMPIO]@AIJ(]ZOYS_KH2g9V4*OX^@E$KH@PSXL@[LH\;=W%_T@L_HL\G@JK'\UMMABFNF0f?P6(AV\BC"IJN^QZJFYNFR9?Q#]VNB]JJZEBDE%^S_G\IOE05>S7'@U]EB!HEO]P]KEXAGQ88P \YOA\MKYDMEF$YR][AUAN@Zh5m2_;#DQYIN-DAKYTQGITECU<4\,P]KEXAGUHIAB U^QZJFYA:l1^<"GPVHM,C@HX[PDHSD@T35_-W\HDW@DTOHBC/T]P]KEXZ:?0Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.cp}keXe|rTjRazt278Q5)NW_CD#JKA_R[MGZOIS:>V"^WAC^KM[FCKD&kxucmPmtz\vZir|;n0Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.aokfmbl;n0Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.dbhioio:;0Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.dbhioioVe~x?j4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*`c9Ve~x?j4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*`c:Ve~x?j4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*`c;Ve~x?j4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*`c<Ve~x?j4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*`c=Ve~x?k4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*krp8Udyy<l;T2,MZPNG&MNBR]VNB]JJ^53U'YRBNQFN^AFHI)uazcek>>4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*tn{`dlSb{{3d9V4*OX^@E$KH@PSXL@[LH\;=W%_T@L_HL\G@JK'zseoRhPeeef+LYO:E$^SIAZT2;8Q5)NW_CD#JKA_R[MGZOIS:>V"^WAC^KM[FCKD&yrbnQi_dfda*SXLF__<>74U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*u~fjUmShjhe.W\@JSS9:k0Y=!F_WKL+BCIWZSEORGA[26^*V_IKVCESNKCL.qzjfYaWlnli"gKOTV?4;5f3\:$ERXFO.EFJZU^FJUBBV=;]/QZJFYNFVIN@A!|yoa\bZccol%bHB[[<0<04>S7'@U]EB!HEO]P]KEXAGQ88P \YOA\MKYDMEF$t`l_g]lqq533\:$ERXFO.EFJZU^FJUBBV=;]/QZJFYNFVIN@A!|yoa\ip~XnVe~x>:4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*u~fjUfyuQ}_nww7`=R8&CTZDA GDL\W\HDW@DP?9S!SXL@[LHXKLFG#~wac^p\aaab'@UG>E Z_EMVP6?<]9%BS[G@/FGM[V_IKVCEW>:R.R[MGZOIWJOG@"}vnb]q[`b`m&_THB[[02;8Q5)NW_CD#JKA_R[MGZOIS:>V"^WAC^KM[FCKD&yrbnQ}_dfda*SXLF__=>o4U1-J[SOH'NOES^WAC^KM_62Z&ZSEORGA_BGOH*u~fjUyShjhe.kGKPR;879j7X> I^TJK*ABFVYRBNQFNZ17Y+U^FJUBBRMJLM-p}keXzVookh!fDNWW848482_;#DQYIN-DAKYTQGITECU<4\,P]KEXAGUHIAB sxl`[wYh}}8m7X> I^TJK*ABFVYRBNQFNZ17Y+U^FJUBBRMJLM-vw`tXagUe?<5Z0.K\RLI(OLDT_T@L_HLX70[)[PDHSD@PCDNO+DU^FJUMS@[W309V4*OX^@E$KH@PSXL@[LH\;<W%_T@L_HL\G@JK'HYRBNQ]_LW[6c=R8&CTZDA GDL\W\HDW@DP?8S!SXL@[LHXKLFG#^FFFU]QAB573\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!\YOA\BZKRP::0Y=!F_WKL+BCIWZSEORGA[27^*V_IKVCESNKCL.QZJFYUWD_S?>5Z0.K\RLI(OLDT_T@L_HLX70[)[PDHSD@PCDNO+VYF[PDHSKQ]EF10?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%XSL]VNB]Q[WC@;;1^<"GPVHM,C@HX[PDHSD@T34_-W\HDW@DTOHBC/R]P]KEXNVXNK><4U1-J[SOH'NOES^WAC^KM_63Z&ZSEORGA_BGOH*UX[PDHS_Q]EF11?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%^_H\PCMI\V@A5m2_;#DQYIN-DAKYTQGITECU<5\,P]KEXAGUHIAB URGQ[HS_:l1^<"GPVHM,C@HX[PDHSD@T34_-W\HDW@DTOHBC/TQFVZTBO;l0Y=!F_WKL+BCIWZSEORGA[27^*V_IKVCESNKCL.W\BDJKAGM9i6[?/H]UMJ)@MGUXUCMPIOY01X(TQGITECQLEMN,QZTN[@DL?<5Z0.K\RLI(OLDT_T@L_HLX70[)[PDHSD@PCDNO+PYT\H^HAIQa2d9V4*OX^@E$KH@PSXL@[LH\;<W%_T@L_HL\G@JK'\UXUCMPF3g8Q5)NW_CD#JKA_R[MGZOIS:?V"^WAC^KM[FCKD&_T_T@L_S16?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%jt`l_lw{[cYh}}9>7X> I^TJK*ABFVYRBNQFNZ16Y+U^FJUBBRMJLM-bw|hdWdsSQ`uu0g?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%h`bmdee0g?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%mmabfnf12?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%mmabfnf]lqq4c3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!id0]lqq4c3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!id3]lqq4c3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!id2]lqq4c3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!id5]lqq4c3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!id4]lqq4b3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!buy3\kpr5k2_;#DQYIN-DAKYTQGITECU<5\,P]KEXAGUHIAB rhqjjb573\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!}irkmcZir|:o0Y=!F_WKL+BCIWZSEORGA[27^*V_IKVCESNKCL.qzjfYaWlnli"GPH3N-QZBH]]927X> I^TJK*ABFVYRBNQFNZ16Y+U^FJUBBRMJLM-p}keXnVookh!Z_EMVP55>3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!|yoa\bZccol%^SIAZT01b?P6(AV\BC"IJN^QZJFYNFR9>Q#]VNB]JJZEBDE%xucmPf^ggc`)nLF__0=0<a:W3+LYQAF%LICQ\YOA\MK]4=T$XUCMPIO]@AIJ({pdhSkQjdfg,mAIR\5;5?=5Z0.K\RLI(OLDT_T@L_HLX70[)[PDHSD@PCDNO+vikVlTcxz<4:W3+LYQAF%LICQ\YOA\MK]4=T$XUCMPIO]@AIJ({pdhS`{w_g]lqq533\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!|yoa\ip~XzVe~x>k4U1-J[SOH'NOES^WAC^KM_63Z&ZSEORGA_BGOH*u~fjUyShjhe.K\H7N)]VNDYY=6;T2,MZPNG&MNBR]VNB]JJ^52U'YRBNQFN^AFHI)tqgiT~Rkkgd-V[AIR\9927X> I^TJK*ABFVYRBNQFNZ16Y+U^FJUBBRMJLM-p}keXzVookh!Z_EMVP45f3\:$ERXFO.EFJZU^FJUBBV=:]/QZJFYNFVIN@A!|yoa\vZccol%bHB[[<1<0e>S7'@U]EB!HEO]P]KEXAGQ89P \YOA\MKYDMEF$t`l_s]f`bc(aME^X1?1319V4*OX^@E$KH@PSXL@[LH\;<W%_T@L_HL\G@JK'zseoR|Potv1b>S7'@U]EB!HEO]P]KEXAGQ89P \YOA\MKYDMEF$y~k}_hl\j67<]9%BS[G@/FGM[V_IKVCEW>8R.R[MGZOIWJOG@"O\YOA\BZKRP:;0Y=!F_WKL+BCIWZSEORGA[24^*V_IKVCESNKCL.CP]KEXZVG^T?h4U1-J[SOH'NOES^WAC^KM_60Z&ZSEORGA_BGOH*UOAO^T^HI<0:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ([PDHSKQBUY13?P6(AV\BC"IJN^QZJFYNFR9=Q#]VNB]JJZEBDE%XUCMPR^OV\65<]9%BS[G@/FGM[V_IKVCEW>8R.R[MGZOIWJOG@"]PAR[MGZ@XZLM8?6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,WZGTQGIT^R\JG208Q5)NW_CD#JKA_R[MGZOIS:<V"^WAC^KM[FCKD&YT_T@L_G]QAB553\:$ERXFO.EFJZU^FJUBBV=9]/QZJFYNFVIN@A!\_R[MGZTXZLM8>6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,QVCUWJF@S_KH2d9V4*OX^@E$KH@PSXL@[LH\;?W%_T@L_HL\G@JK'\YN^RCZX3g8Q5)NW_CD#JKA_R[MGZOIS:<V"^WAC^KM[FCKD&_XI_Q]EF0e?P6(AV\BC"IJN^QZJFYNFR9=Q#]VNB]JJZEBDE%^SKOCLHLD6`=R8&CTZDA GDL\W\HDW@DP?;S!SXL@[LHXKLFG#XQ]IRKMC67<]9%BS[G@/FGM[V_IKVCEW>8R.R[MGZOIWJOG@"[PSUCWGHBXf;o0Y=!F_WKL+BCIWZSEORGA[24^*V_IKVCESNKCL.W\W\HDWO8n7X> I^TJK*ABFVYRBNQFNZ15Y+U^FJUBBRMJLM-V[V_IKVX896[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,evikVg~tRhPotv01>S7'@U]EB!HEO]P]KEXAGQ8:P \YOA\MKYDMEF$m~wac^ov|ZtXg|~9h6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,giidcln9h6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,bdjkagm8=6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,bdjkagmTcxz=d:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(nm;Tcxz=d:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(nm8Tcxz=d:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(nm9Tcxz=d:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(nm>Tcxz=d:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(nm?Tcxz=e:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(e|r:Sb{{2b9V4*OX^@E$KH@PSXL@[LH\;?W%_T@L_HL\G@JK'{cxeci<0:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ(z`ybbjQ`uu1f?P6(AV\BC"IJN^QZJFYNFR9=Q#]VNB]JJZEBDE%xucmPf^ggc`)NWA8G"XQKOTV0=>S7'@U]EB!HEO]P]KEXAGQ8:P \YOA\MKYDMEF$t`l_g]f`bc(]VNDYY><9:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ({pdhSkQjdfg,QZBH]];8m6[?/H]UMJ)@MGUXUCMPIOY02X(TQGITECQLEMN,w|hdWoUnhjk iEMVP969;h1^<"GPVHM,C@HX[PDHSD@T37_-W\HDW@DTOHBC/r{mgZ`Xmmmn#dJ@UU>2:66<]9%BS[G@/FGM[V_IKVCEW>8R.R[MGZOIWJOG@"}vnb]e[jss;=1^<"GPVHM,C@HX[PDHSD@T37_-W\HDW@DTOHBC/r{mgZkrpVlTcxz<4:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ({pdhS`{w_s]lqq5b3\:$ERXFO.EFJZU^FJUBBV=9]/QZJFYNFVIN@A!|yoa\vZccol%BSA<G.T]GKPR412_;#DQYIN-DAKYTQGITECU<6\,P]KEXAGUHIAB sxl`[wYblno$YRJ@UU20=>S7'@U]EB!HEO]P]KEXAGQ8:P \YOA\MKYDMEF$t`l_s]f`bc(]VNDYY?<a:W3+LYQAF%LICQ\YOA\MK]4>T$XUCMPIO]@AIJ({pdhSQjdfg,mAIR\5:5?l5Z0.K\RLI(OLDT_T@L_HLX73[)[PDHSD@PCDNO+vikVxTiiij/hFLQQ:66::0Y=!F_WKL+BCIWZSEORGA[24^*V_IKVCESNKCL.qzjfYuWf>k5Z0.K\RLI(OLDT_T@L_HLX73[)[PDHSD@PCDNO+pubzVceSc=>;T2,MZPNG&MNBR]VNB]JJ^50U'YRBNQFN^AFHI)F[PDHSKQBUY12?P6(AV\BC"IJN^QZJFYNFR9<Q#]VNB]JJZEBDE%J_T@L_S]NQ]4a3\:$ERXFO.EFJZU^FJUBBV=8]/QZJFYNFVIN@A!\HHDW[WC@;91^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/R[MGZ@XE\R8<6[?/H]UMJ)@MGUXUCMPIOY03X(TQGITECQLEMN,W\HDW[UFYU=<;T2,MZPNG&MNBR]VNB]JJ^50U'YRBNQFN^AFHI)TWHYRBNQI_SGD76=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#^QNSXL@[WYUMN997X> I^TJK*ABFVYRBNQFNZ14Y+U^FJUBBRMJLM-P[V_IKVLT^HI<2:W3+LYQAF%LICQ\YOA\MK]4?T$XUCMPIO]@AIJ([VYRBNQ]_SGD77=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#X]JR^AOOZTBO;o0Y=!F_WKL+BCIWZSEORGA[25^*V_IKVCESNKCL.WPAWYJ]Q8n7X> I^TJK*ABFVYRBNQFNZ14Y+U^FJUBBRMJLM-VW@TXZLM9j6[?/H]UMJ)@MGUXUCMPIOY03X(TQGITECQLEMN,QZ@FDECEK?k4U1-J[SOH'NOES^WAC^KM_61Z&ZSEORGA_BGOH*SXZ@YBBJ=>;T2,MZPNG&MNBR]VNB]JJ^50U'YRBNQFN^AFHI)RWZ^JXNCK_o0f?P6(AV\BC"IJN^QZJFYNFR9<Q#]VNB]JJZEBDE%^S^WAC^D1a>S7'@U]EB!HEO]P]KEXAGQ8;P \YOA\MKYDMEF$YR]VNB]Q70=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#l}vnb]nq}YaWf?85Z0.K\RLI(OLDT_T@L_HLX72[)[PDHSD@PCDNO+du~fjUfyuQ}_nww6a=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#nb`cjgg6a=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#koclhld74=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#koclhld[jss:m1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/gf2[jss:m1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/gf1[jss:m1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/gf0[jss:m1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/gf7[jss:m1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/gf6[jss:l1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/lw{5Zir|;i0Y=!F_WKL+BCIWZSEORGA[25^*V_IKVCESNKCL.pjwlh`;91^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/skpmkaXg|~8i6[?/H]UMJ)@MGUXUCMPIOY03X(TQGITECQLEMN,w|hdWoUnhjk I^J1H+SXLF__?45Z0.K\RLI(OLDT_T@L_HLX72[)[PDHSD@PCDNO+vikVlTiiij/T]GKPR7;01^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/r{mgZ`Xmmmn#XQKOTV27d=R8&CTZDA GDL\W\HDW@DP?:S!SXL@[LHXKLFG#~wac^d\aaab'`NDYY2?>2c8Q5)NW_CD#JKA_R[MGZOIS:=V"^WAC^KM[FCKD&yrbnQi_dfda*oCG\^7=3=?;T2,MZPNG&MNBR]VNB]JJ^50U'YRBNQFN^AFHI)tqgiTjRazt268Q5)NW_CD#JKA_R[MGZOIS:=V"^WAC^KM[FCKD&yrbnQbuy]e[jss;=1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/r{mgZkrpVxTcxz<e:W3+LYQAF%LICQ\YOA\MK]4?T$XUCMPIO]@AIJ({pdhSQjdfg,MZJ5@'_THB[[389V4*OX^@E$KH@PSXL@[LH\;>W%_T@L_HL\G@JK'zseoR|Peeef+PYCG\^;?45Z0.K\RLI(OLDT_T@L_HLX72[)[PDHSD@PCDNO+vikVxTiiij/T]GKPR6;h1^<"GPVHM,C@HX[PDHSD@T36_-W\HDW@DTOHBC/r{mgZtXmmmn#dJ@UU>3:6g<]9%BS[G@/FGM[V_IKVCEW>9R.R[MGZOIWJOG@"}vnb]q[`b`m&cOCXZ31?13?P6(AV\BC"IJN^QZJFYNFR9<Q#]VNB]JJZEBDE%xucmPr^mvp7`<]9%BS[G@/FGM[V_IKVCEW>9R.R[MGZOIWJOG@"{|es]jjZh492_;#DQYIN-DAKYTQGITECU<8\,P]KEXAGUHIAB AR[MGZ@XE\R8=6[?/H]UMJ)@MGUXUCMPIOY0<X(TQGITECQLEMN,EV_IKVXTAXV=f:W3+LYQAF%LICQ\YOA\MK]40T$XUCMPIO]@AIJ([ACMXR\JG228Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&YRBNQI_LW[75=R8&CTZDA GDL\W\HDW@DP?5S!SXL@[LHXKLFG#^WAC^P\IP^4;2_;#DQYIN-DAKYTQGITECU<8\,P]KEXAGUHIAB S^CP]KEXNVXNK>=4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*UXIZSEOR\PRDE06>S7'@U]EB!HEO]P]KEXAGQ84P \YOA\MKYDMEF$_R]VNB]E[WC@;;1^<"GPVHM,C@HX[PDHSD@T39_-W\HDW@DTOHBC/R]P]KEXZVXNK><4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*STM[UH@FQ]EF0f?P6(AV\BC"IJN^QZJFYNFR93Q#]VNB]JJZEBDE%^_H\PMTZ1a>S7'@U]EB!HEO]P]KEXAGQ84P \YOA\MKYDMEF$Y^K]_SGD6c=R8&CTZDA GDL\W\HDW@DP?5S!SXL@[LHXKLFG#XQIAMNJJB4b3\:$ERXFO.EFJZU^FJUBBV=7]/QZJFYNFVIN@A!Z_SKPMKA492_;#DQYIN-DAKYTQGITECU<8\,P]KEXAGUHIAB U^QWEQEJLVd9i6[?/H]UMJ)@MGUXUCMPIOY0<X(TQGITECQLEMN,QZU^FJUM>h5Z0.K\RLI(OLDT_T@L_HLX7=[)[PDHSD@PCDNO+PYTQGIT^>;4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*gtqgiTaxvPf^mvp63<]9%BS[G@/FGM[V_IKVCEW>6R.R[MGZOIWJOG@"o|yoa\ip~XzVe~x?j4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*ekgjanh?j4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*`fdecek>?4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*`fdecekRazt3f8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&lo=Razt3f8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&lo>Razt3f8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&lo?Razt3f8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&lo8Razt3f8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&lo9Razt3g8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&g~t<Q`uu0`?P6(AV\BC"IJN^QZJFYNFR93Q#]VNB]JJZEBDE%ye~gag228Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&xbd`h_nww7`=R8&CTZDA GDL\W\HDW@DP?5S!SXL@[LHXKLFG#~wac^d\aaab'@UC>A Z_EMVP6?<]9%BS[G@/FGM[V_IKVCEW>6R.R[MGZOIWJOG@"}vnb]e[`b`m&_THB[[02;8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&yrbnQi_dfda*SXLF__=>o4U1-J[SOH'NOES^WAC^KM_6>Z&ZSEORGA_BGOH*u~fjUmShjhe.kGKPR;879j7X> I^TJK*ABFVYRBNQFNZ1;Y+U^FJUBBRMJLM-p}keXnVookh!fDNWW848482_;#DQYIN-DAKYTQGITECU<8\,P]KEXAGUHIAB sxl`[cYh}}9?7X> I^TJK*ABFVYRBNQFNZ1;Y+U^FJUBBRMJLM-p}keXe|rTjRazt268Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&yrbnQbuy]q[jss;l1^<"GPVHM,C@HX[PDHSD@T39_-W\HDW@DTOHBC/r{mgZtXmmmn#DQC2I,V[AIR\:30Y=!F_WKL+BCIWZSEORGA[2:^*V_IKVCESNKCL.qzjfYuWlnli"[PDNWW46?<]9%BS[G@/FGM[V_IKVCEW>6R.R[MGZOIWJOG@"}vnb]q[`b`m&_THB[[12c8Q5)NW_CD#JKA_R[MGZOIS:2V"^WAC^KM[FCKD&yrbnQ}_dfda*oCG\^7<3=n;T2,MZPNG&MNBR]VNB]JJ^5?U'YRBNQFN^AFHI)tqgiT~Rkkgd-j@JSS4848<6[?/H]UMJ)@MGUXUCMPIOY0<X(TQGITECQLEMN,w|hdW{Udyy<i;T2,MZPNG&MNBR]VNB]JJ^5?U'YRBNQFN^AFHI)r{lxTecQa309V4*OX^@E$KH@PSXL@[LH\;0W%_T@L_HL\G@JK'HYRBNQI_LW[74=R8&CTZDA GDL\W\HDW@DP?4S!SXL@[LHXKLFG#L]VNB]Q[HS_:o1^<"GPVHM,C@HX[PDHSD@T38_-W\HDW@DTOHBC/RJJBQYUMN9;7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-P]KEXNVG^T>>4U1-J[SOH'NOES^WAC^KM_6?Z&ZSEORGA_BGOH*U^FJUYS@[W329V4*OX^@E$KH@PSXL@[LH\;0W%_T@L_HL\G@JK'ZUJ_T@L_G]QAB543\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!\_@QZJFYUW[OL??5Z0.K\RLI(OLDT_T@L_HLX7<[)[PDHSD@PCDNO+VYTQGITJR\JG208Q5)NW_CD#JKA_R[MGZOIS:3V"^WAC^KM[FCKD&YT_T@L_S]QAB553\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!ZSDP\GIMXZLM9i6[?/H]UMJ)@MGUXUCMPIOY0=X(TQGITECQLEMN,QVCUWD_S>h5Z0.K\RLI(OLDT_T@L_HLX7<[)[PDHSD@PCDNO+PUBZVXNK?h4U1-J[SOH'NOES^WAC^KM_6?Z&ZSEORGA_BGOH*SXNHFGECI=e:W3+LYQAF%LICQ\YOA\MK]41T$XUCMPIO]@AIJ(]VXB_D@H309V4*OX^@E$KH@PSXL@[LH\;0W%_T@L_HL\G@JK'\UXXLZLME]m6`=R8&CTZDA GDL\W\HDW@DP?4S!SXL@[LHXKLFG#XQ\YOA\B7c<]9%BS[G@/FGM[V_IKVCEW>7R.R[MGZOIWJOG@"[PSXL@[W523\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!nsxl`[hsWoUdyy=:;T2,MZPNG&MNBR]VNB]JJ^5>U'YRBNQFN^AFHI)f{pdhS`{w_s]lqq4c3\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!llnahaa4c3\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!iamnjjb563\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!iamnjjbYh}}8o7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-e`4Yh}}8o7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-e`7Yh}}8o7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-e`6Yh}}8o7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-e`1Yh}}8o7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-e`0Yh}}8n7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-nq}7Xg|~9o6[?/H]UMJ)@MGUXUCMPIOY0=X(TQGITECQLEMN,vlunfn9;7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-qmvoioVe~x>k4U1-J[SOH'NOES^WAC^KM_6?Z&ZSEORGA_BGOH*u~fjUmShjhe.K\L7J)]VNDYY=6;T2,MZPNG&MNBR]VNB]JJ^5>U'YRBNQFN^AFHI)tqgiTjRkkgd-V[AIR\9927X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-p}keXnVookh!Z_EMVP45f3\:$ERXFO.EFJZU^FJUBBV=6]/QZJFYNFVIN@A!|yoa\bZccol%bHB[[<1<0e>S7'@U]EB!HEO]P]KEXAGQ85P \YOA\MKYDMEF$t`l_g]f`bc(aME^X1?1319V4*OX^@E$KH@PSXL@[LH\;0W%_T@L_HL\G@JK'zseoRhPotv00>S7'@U]EB!HEO]P]KEXAGQ85P \YOA\MKYDMEF$t`l_lw{[cYh}}9?7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-p}keXe|rT~Razt2g8Q5)NW_CD#JKA_R[MGZOIS:3V"^WAC^KM[FCKD&yrbnQ}_dfda*OXD;B%YRJ@UU1:?P6(AV\BC"IJN^QZJFYNFR92Q#]VNB]JJZEBDE%xucmPr^ggc`)RWME^X==6;T2,MZPNG&MNBR]VNB]JJ^5>U'YRBNQFN^AFHI)tqgiT~Rkkgd-V[AIR\89j7X> I^TJK*ABFVYRBNQFNZ1:Y+U^FJUBBRMJLM-p}keXzVookh!fDNWW8584i2_;#DQYIN-DAKYTQGITECU<9\,P]KEXAGUHIAB sxl`[wYblno$eIAZT=3=75=R8&CTZDA GDL\W\HDW@DP?4S!SXL@[LHXKLFG#~wac^p\kpr5n2_;#DQYIN-DAKYTQGITECU<9\,P]KEXAGUHIAB urgq[lhXf:;0Y=!F_WKL+BCIWZSEORGA[52^*V_IKVCESNKCL.CP]KEXNVG^T>?4U1-J[SOH'NOES^WAC^KM_16Z&ZSEORGA_BGOH*GTQGIT^RCZX3d8Q5)NW_CD#JKA_R[MGZOIS=:V"^WAC^KM[FCKD&YCEKZPRDE04>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$_T@L_G]NQ]573\:$ERXFO.EFJZU^FJUBBV:?]/QZJFYNFVIN@A!\YOA\VZKRP:90Y=!F_WKL+BCIWZSEORGA[52^*V_IKVCESNKCL.Q\EV_IKVLT^HI<3:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ([VKXUCMPR^PFC64<]9%BS[G@/FGM[V_IKVCEW9>R.R[MGZOIWJOG@"]PSXL@[CYUMN997X> I^TJK*ABFVYRBNQFNZ63Y+U^FJUBBRMJLM-P[V_IKVXT^HI<2:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ(]ZOYSNBD_SGD6`=R8&CTZDA GDL\W\HDW@DP8=S!SXL@[LHXKLFG#X]JR^OV\7c<]9%BS[G@/FGM[V_IKVCEW9>R.R[MGZOIWJOG@"[\ES]QAB4a3\:$ERXFO.EFJZU^FJUBBV:?]/QZJFYNFVIN@A!Z_GCOHLH@:l1^<"GPVHM,C@HX[PDHSD@T41_-W\HDW@DTOHBC/T]QMVOIO:;0Y=!F_WKL+BCIWZSEORGA[52^*V_IKVCESNKCL.W\WQGSKDNTb?k4U1-J[SOH'NOES^WAC^KM_16Z&ZSEORGA_BGOH*SX[PDHSK<j;T2,MZPNG&MNBR]VNB]JJ^27U'YRBNQFN^AFHI)RWZSEOR\<5:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ(izseoRczx^d\kpr4=2_;#DQYIN-DAKYTQGITECU;0\,P]KEXAGUHIAB ar{mgZkrpVxTcxz=d:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ(keehghj=d:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ(nhfgeci<1:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ(nhfgeciPotv1`>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$ji?Potv1`>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$ji<Potv1`>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$ji=Potv1`>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$ji:Potv1`>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$ji;Potv1a>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$axv>_nww6f=R8&CTZDA GDL\W\HDW@DP8=S!SXL@[LHXKLFG#g|ioe04>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$~d}fnf]lqq5b3\:$ERXFO.EFJZU^FJUBBV:?]/QZJFYNFVIN@A!|yoa\bZccol%BSE<C.T]GKPR412_;#DQYIN-DAKYTQGITECU;0\,P]KEXAGUHIAB sxl`[cYblno$YRJ@UU20=>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$t`l_g]f`bc(]VNDYY?<a:W3+LYQAF%LICQ\YOA\MK]38T$XUCMPIO]@AIJ({pdhSkQjdfg,mAIR\5:5?l5Z0.K\RLI(OLDT_T@L_HLX05[)[PDHSD@PCDNO+vikVlTiiij/hFLQQ:66::0Y=!F_WKL+BCIWZSEORGA[52^*V_IKVCESNKCL.qzjfYaWf?95Z0.K\RLI(OLDT_T@L_HLX05[)[PDHSD@PCDNO+vikVg~tRhPotv00>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$t`l_lw{[wYh}}9n7X> I^TJK*ABFVYRBNQFNZ63Y+U^FJUBBRMJLM-p}keXzVookh!F_M0K*PYCG\^856[?/H]UMJ)@MGUXUCMPIOY74X(TQGITECQLEMN,w|hdW{Unhjk U^FLQQ6412_;#DQYIN-DAKYTQGITECU;0\,P]KEXAGUHIAB sxl`[wYblno$YRJ@UU30e>S7'@U]EB!HEO]P]KEXAGQ?<P \YOA\MKYDMEF$t`l_s]f`bc(aME^X1>13`9V4*OX^@E$KH@PSXL@[LH\<9W%_T@L_HL\G@JK'zseoR|Peeef+lBH]]6:2>>4U1-J[SOH'NOES^WAC^KM_16Z&ZSEORGA_BGOH*u~fjUySb{{2g9V4*OX^@E$KH@PSXL@[LH\<9W%_T@L_HL\G@JK'|yn~Rga_o12?P6(AV\BC"IJN^QZJFYNFR>:Q#]VNB]JJZEBDE%J_T@L_G]NQ]563\:$ERXFO.EFJZU^FJUBBV:>]/QZJFYNFVIN@A!NSXL@[WYJ]Q8m7X> I^TJK*ABFVYRBNQFNZ62Y+U^FJUBBRMJLM-PLL@SW[OL?=5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+V_IKVLTAXV<0:W3+LYQAF%LICQ\YOA\MK]39T$XUCMPIO]@AIJ([PDHS_QBUY10?P6(AV\BC"IJN^QZJFYNFR>:Q#]VNB]JJZEBDE%XSL]VNB]E[WC@;:1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/R]BW\HDW[UYIJ==;T2,MZPNG&MNBR]VNB]JJ^26U'YRBNQFN^AFHI)TWZSEORHPRDE06>S7'@U]EB!HEO]P]KEXAGQ?=P \YOA\MKYDMEF$_R]VNB]Q[WC@;;1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/TQFVZEKCVXNK?k4U1-J[SOH'NOES^WAC^KM_17Z&ZSEORGA_BGOH*STM[UFYU<j;T2,MZPNG&MNBR]VNB]JJ^26U'YRBNQFN^AFHI)R[LXT^HI=f:W3+LYQAF%LICQ\YOA\MK]39T$XUCMPIO]@AIJ(]VLJ@AGAG3g8Q5)NW_CD#JKA_R[MGZOIS=;V"^WAC^KM[FCKD&_T^D]FNF12?P6(AV\BC"IJN^QZJFYNFR>:Q#]VNB]JJZEBDE%^S^ZNTBOG[k4b3\:$ERXFO.EFJZU^FJUBBV:>]/QZJFYNFVIN@A!Z_R[MGZ@5m2_;#DQYIN-DAKYTQGITECU;1\,P]KEXAGUHIAB U^QZJFYU;<1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/`qzjfYj}qUmSb{{349V4*OX^@E$KH@PSXL@[LH\<8W%_T@L_HL\G@JK'hyrbnQbuy]q[jss:m1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/bnlgncc:m1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/gcohlh`;81^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/gcohlh`Wf>i5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+cb6Wf>i5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+cb5Wf>i5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+cb4Wf>i5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+cb3Wf>i5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+cb2Wf>h5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+hs9Ve~x?m4U1-J[SOH'NOES^WAC^KM_17Z&ZSEORGA_BGOH*tn{`dl?=5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+wotagmTcxz<e:W3+LYQAF%LICQ\YOA\MK]39T$XUCMPIO]@AIJ({pdhSkQjdfg,MZN5D'_THB[[389V4*OX^@E$KH@PSXL@[LH\<8W%_T@L_HL\G@JK'zseoRhPeeef+PYCG\^;?45Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+vikVlTiiij/T]GKPR6;h1^<"GPVHM,C@HX[PDHSD@T40_-W\HDW@DTOHBC/r{mgZ`Xmmmn#dJ@UU>3:6g<]9%BS[G@/FGM[V_IKVCEW9?R.R[MGZOIWJOG@"}vnb]e[`b`m&cOCXZ31?13?P6(AV\BC"IJN^QZJFYNFR>:Q#]VNB]JJZEBDE%xucmPf^mvp62<]9%BS[G@/FGM[V_IKVCEW9?R.R[MGZOIWJOG@"}vnb]nq}YaWf?95Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+vikVg~tR|Potv0a>S7'@U]EB!HEO]P]KEXAGQ?=P \YOA\MKYDMEF$t`l_s]f`bc(AVF9D#[PDNWW7<=R8&CTZDA GDL\W\HDW@DP8<S!SXL@[LHXKLFG#~wac^p\aaab'\UOCXZ?389V4*OX^@E$KH@PSXL@[LH\<8W%_T@L_HL\G@JK'zseoR|Peeef+PYCG\^:?l5Z0.K\RLI(OLDT_T@L_HLX04[)[PDHSD@PCDNO+vikVxTiiij/hFLQQ:76:k0Y=!F_WKL+BCIWZSEORGA[53^*V_IKVCESNKCL.qzjfYuWlnli"gKOTV?5;573\:$ERXFO.EFJZU^FJUBBV:>]/QZJFYNFVIN@A!|yoa\vZir|;l0Y=!F_WKL+BCIWZSEORGA[53^*V_IKVCESNKCL.wpawYnfVd8=6[?/H]UMJ)@MGUXUCMPIOY76X(TQGITECQLEMN,EV_IKVLTAXV<1:W3+LYQAF%LICQ\YOA\MK]3:T$XUCMPIO]@AIJ(IZSEOR\PMTZ1b>S7'@U]EB!HEO]P]KEXAGQ?>P \YOA\MKYDMEF$_EGIT^PFC66<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"]VNB]E[HS_;91^<"GPVHM,C@HX[PDHSD@T43_-W\HDW@DTOHBC/R[MGZTXE\R8?6[?/H]UMJ)@MGUXUCMPIOY76X(TQGITECQLEMN,WZGTQGITJR\JG218Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&YTM^WAC^P\V@A4:2_;#DQYIN-DAKYTQGITECU;2\,P]KEXAGUHIAB S^QZJFYAW[OL??5Z0.K\RLI(OLDT_T@L_HLX07[)[PDHSD@PCDNO+VYTQGIT^R\JG208Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&_XI_QLLJ]QAB4b3\:$ERXFO.EFJZU^FJUBBV:=]/QZJFYNFVIN@A!ZSDP\IP^5m2_;#DQYIN-DAKYTQGITECU;2\,P]KEXAGUHIAB URGQ[WC@:o1^<"GPVHM,C@HX[PDHSD@T43_-W\HDW@DTOHBC/T]EEIJNFN8n7X> I^TJK*ABFVYRBNQFNZ61Y+U^FJUBBRMJLM-V[WOTAGM8=6[?/H]UMJ)@MGUXUCMPIOY76X(TQGITECQLEMN,QZUSI]IFHR`=e:W3+LYQAF%LICQ\YOA\MK]3:T$XUCMPIO]@AIJ(]VYRBNQI2d9V4*OX^@E$KH@PSXL@[LH\<;W%_T@L_HL\G@JK'\UXUCMPR278Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&kxucmPmtz\bZir|:?0Y=!F_WKL+BCIWZSEORGA[50^*V_IKVCESNKCL.cp}keXe|rT~Razt3f8Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&igcnejd3f8Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&lj`agag238Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&lj`agag^mvp7b<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"hk1^mvp7b<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"hk2^mvp7b<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"hk3^mvp7b<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"hk4^mvp7b<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"hk5^mvp7c<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"czx0]lqq4d3\:$ERXFO.EFJZU^FJUBBV:=]/QZJFYNFVIN@A!}irkmc66<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"|fshld[jss;l1^<"GPVHM,C@HX[PDHSD@T43_-W\HDW@DTOHBC/r{mgZ`Xmmmn#DQG2M,V[AIR\:30Y=!F_WKL+BCIWZSEORGA[50^*V_IKVCESNKCL.qzjfYaWlnli"[PDNWW46?<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"}vnb]e[`b`m&_THB[[12c8Q5)NW_CD#JKA_R[MGZOIS=8V"^WAC^KM[FCKD&yrbnQi_dfda*oCG\^7<3=n;T2,MZPNG&MNBR]VNB]JJ^25U'YRBNQFN^AFHI)tqgiTjRkkgd-j@JSS4848<6[?/H]UMJ)@MGUXUCMPIOY76X(TQGITECQLEMN,w|hdWoUdyy=;;T2,MZPNG&MNBR]VNB]JJ^25U'YRBNQFN^AFHI)tqgiTaxvPf^mvp62<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"}vnb]nq}YuWf?h5Z0.K\RLI(OLDT_T@L_HLX07[)[PDHSD@PCDNO+vikVxTiiij/H]O6M(RWME^X>74U1-J[SOH'NOES^WAC^KM_14Z&ZSEORGA_BGOH*u~fjUyShjhe.W\@JSS8:30Y=!F_WKL+BCIWZSEORGA[50^*V_IKVCESNKCL.qzjfYuWlnli"[PDNWW56g<]9%BS[G@/FGM[V_IKVCEW9<R.R[MGZOIWJOG@"}vnb]q[`b`m&cOCXZ30?1b?P6(AV\BC"IJN^QZJFYNFR>9Q#]VNB]JJZEBDE%xucmPr^ggc`)nLF__0<0<0:W3+LYQAF%LICQ\YOA\MK]3:T$XUCMPIO]@AIJ({pdhSQ`uu0e?P6(AV\BC"IJN^QZJFYNFR>9Q#]VNB]JJZEBDE%~h|Pio]m74=R8&CTZDA GDL\W\HDW@DP8>S!SXL@[LHXKLFG#L]VNB]E[HS_;81^<"GPVHM,C@HX[PDHSD@T42_-W\HDW@DTOHBC/@QZJFYUWD_S>k5Z0.K\RLI(OLDT_T@L_HLX06[)[PDHSD@PCDNO+VNNN]UYIJ=?;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)TQGITJRCZX228Q5)NW_CD#JKA_R[MGZOIS=9V"^WAC^KM[FCKD&YRBNQ]_LW[76=R8&CTZDA GDL\W\HDW@DP8>S!SXL@[LHXKLFG#^QNSXL@[CYUMN987X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-P[DU^FJUYS_KH339V4*OX^@E$KH@PSXL@[LH\<:W%_T@L_HL\G@JK'ZUXUCMPF^PFC64<]9%BS[G@/FGM[V_IKVCEW9=R.R[MGZOIWJOG@"]PSXL@[WYUMN997X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-VW@TXKEAT^HI=e:W3+LYQAF%LICQ\YOA\MK]3;T$XUCMPIO]@AIJ(]ZOYS@[W2d9V4*OX^@E$KH@PSXL@[LH\<:W%_T@L_HL\G@JK'\YN^R\JG3d8Q5)NW_CD#JKA_R[MGZOIS=9V"^WAC^KM[FCKD&_TJLBCIOE1a>S7'@U]EB!HEO]P]KEXAGQ??P \YOA\MKYDMEF$YR\FSHLD74=R8&CTZDA GDL\W\HDW@DP8>S!SXL@[LHXKLFG#XQ\T@V@IAYi:l1^<"GPVHM,C@HX[PDHSD@T42_-W\HDW@DTOHBC/T]P]KEXN;o0Y=!F_WKL+BCIWZSEORGA[51^*V_IKVCESNKCL.W\W\HDW[9>7X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-bw|hdWdsSkQ`uu16?P6(AV\BC"IJN^QZJFYNFR>8Q#]VNB]JJZEBDE%jt`l_lw{[wYh}}8o7X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-`hjelmm8o7X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-eeijnfn9:7X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-eeijnfnUdyy<k;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)al8Udyy<k;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)al;Udyy<k;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)al:Udyy<k;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)al=Udyy<k;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)al<Udyy<j;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)j}q;Tcxz=c:W3+LYQAF%LICQ\YOA\MK]3;T$XUCMPIO]@AIJ(z`ybbj=?;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)uazcekRazt2g8Q5)NW_CD#JKA_R[MGZOIS=9V"^WAC^KM[FCKD&yrbnQi_dfda*OX@;F%YRJ@UU1:?P6(AV\BC"IJN^QZJFYNFR>8Q#]VNB]JJZEBDE%xucmPf^ggc`)RWME^X==6;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)tqgiTjRkkgd-V[AIR\89j7X> I^TJK*ABFVYRBNQFNZ60Y+U^FJUBBRMJLM-p}keXnVookh!fDNWW8584i2_;#DQYIN-DAKYTQGITECU;3\,P]KEXAGUHIAB sxl`[cYblno$eIAZT=3=75=R8&CTZDA GDL\W\HDW@DP8>S!SXL@[LHXKLFG#~wac^d\kpr4<2_;#DQYIN-DAKYTQGITECU;3\,P]KEXAGUHIAB sxl`[hsWoUdyy=;;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)tqgiTaxvPr^mvp6c<]9%BS[G@/FGM[V_IKVCEW9=R.R[MGZOIWJOG@"}vnb]q[`b`m&CT@?F!U^FLQQ5>3\:$ERXFO.EFJZU^FJUBBV:<]/QZJFYNFVIN@A!|yoa\vZccol%^SIAZT11:?P6(AV\BC"IJN^QZJFYNFR>8Q#]VNB]JJZEBDE%xucmPr^ggc`)RWME^X<=n;T2,MZPNG&MNBR]VNB]JJ^24U'YRBNQFN^AFHI)tqgiT~Rkkgd-j@JSS4948m6[?/H]UMJ)@MGUXUCMPIOY77X(TQGITECQLEMN,w|hdW{Unhjk iEMVP979;91^<"GPVHM,C@HX[PDHSD@T42_-W\HDW@DTOHBC/r{mgZtXg|~9j6[?/H]UMJ)@MGUXUCMPIOY77X(TQGITECQLEMN,qvcuW`dTb>?4U1-J[SOH'NOES^WAC^KM_12Z&ZSEORGA_BGOH*GTQGITJRCZX238Q5)NW_CD#JKA_R[MGZOIS=>V"^WAC^KM[FCKD&KXUCMPR^OV\7`<]9%BS[G@/FGM[V_IKVCEW9:R.R[MGZOIWJOG@"]GIGV\V@A482_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB SXL@[CYJ]Q9;7X> I^TJK*ABFVYRBNQFNZ67Y+U^FJUBBRMJLM-P]KEXZVG^T>=4U1-J[SOH'NOES^WAC^KM_12Z&ZSEORGA_BGOH*UXIZSEORHPRDE07>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$_RO\YOA\VZTBO:80Y=!F_WKL+BCIWZSEORGA[56^*V_IKVCESNKCL.Q\W\HDWOUYIJ==;T2,MZPNG&MNBR]VNB]JJ^23U'YRBNQFN^AFHI)TWZSEOR\PRDE06>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$Y^K]_BNH[WC@:l1^<"GPVHM,C@HX[PDHSD@T45_-W\HDW@DTOHBC/TQFVZKRP;o0Y=!F_WKL+BCIWZSEORGA[56^*V_IKVCESNKCL.WPAWYUMN8m7X> I^TJK*ABFVYRBNQFNZ67Y+U^FJUBBRMJLM-V[CGKD@DL>h5Z0.K\RLI(OLDT_T@L_HLX01[)[PDHSD@PCDNO+PYUAZCEK>?4U1-J[SOH'NOES^WAC^KM_12Z&ZSEORGA_BGOH*SX[]K_O@JPn3g8Q5)NW_CD#JKA_R[MGZOIS=>V"^WAC^KM[FCKD&_T_T@L_G0f?P6(AV\BC"IJN^QZJFYNFR>?Q#]VNB]JJZEBDE%^S^WAC^P01>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$m~wac^ov|Z`Xg|~896[?/H]UMJ)@MGUXUCMPIOY70X(TQGITECQLEMN,evikVg~tR|Potv1`>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$oaalkdf1`>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$jlbcioe05>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$jlbcioe\kpr5l2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB fe3\kpr5l2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB fe0\kpr5l2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB fe1\kpr5l2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB fe6\kpr5l2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB fe7\kpr5m2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB mtz2[jss:j1^<"GPVHM,C@HX[PDHSD@T45_-W\HDW@DTOHBC/skpmka482_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB rhqjjbYh}}9n7X> I^TJK*ABFVYRBNQFNZ67Y+U^FJUBBRMJLM-p}keXnVookh!F_I0O*PYCG\^856[?/H]UMJ)@MGUXUCMPIOY70X(TQGITECQLEMN,w|hdWoUnhjk U^FLQQ6412_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB sxl`[cYblno$YRJ@UU30e>S7'@U]EB!HEO]P]KEXAGQ?8P \YOA\MKYDMEF$t`l_g]f`bc(aME^X1>13`9V4*OX^@E$KH@PSXL@[LH\<=W%_T@L_HL\G@JK'zseoRhPeeef+lBH]]6:2>>4U1-J[SOH'NOES^WAC^KM_12Z&ZSEORGA_BGOH*u~fjUmSb{{359V4*OX^@E$KH@PSXL@[LH\<=W%_T@L_HL\G@JK'zseoRczx^d\kpr4<2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB sxl`[hsW{Udyy=j;T2,MZPNG&MNBR]VNB]JJ^23U'YRBNQFN^AFHI)tqgiT~Rkkgd-J[I4O&\UOCXZ<9:W3+LYQAF%LICQ\YOA\MK]3<T$XUCMPIO]@AIJ({pdhSQjdfg,QZBH]]:856[?/H]UMJ)@MGUXUCMPIOY70X(TQGITECQLEMN,w|hdW{Unhjk U^FLQQ74i2_;#DQYIN-DAKYTQGITECU;4\,P]KEXAGUHIAB sxl`[wYblno$eIAZT=2=7d=R8&CTZDA GDL\W\HDW@DP89S!SXL@[LHXKLFG#~wac^p\aaab'`NDYY2>>228Q5)NW_CD#JKA_R[MGZOIS=>V"^WAC^KM[FCKD&yrbnQ}_nww6c=R8&CTZDA GDL\W\HDW@DP89S!SXL@[LHXKLFG#x}jr^km[k563\:$ERXFO.EFJZU^FJUBBV::]/QZJFYNFVIN@A!NSXL@[CYJ]Q9:7X> I^TJK*ABFVYRBNQFNZ66Y+U^FJUBBRMJLM-BW\HDW[UFYU<i;T2,MZPNG&MNBR]VNB]JJ^22U'YRBNQFN^AFHI)T@@L_S_KH319V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'ZSEORHPMTZ04>S7'@U]EB!HEO]P]KEXAGQ?9P \YOA\MKYDMEF$_T@L_S]NQ]543\:$ERXFO.EFJZU^FJUBBV::]/QZJFYNFVIN@A!\_@QZJFYAW[OL?>5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+VYF[PDHS_Q]EF11?P6(AV\BC"IJN^QZJFYNFR>>Q#]VNB]JJZEBDE%XS^WAC^D\V@A4:2_;#DQYIN-DAKYTQGITECU;5\,P]KEXAGUHIAB S^QZJFYUW[OL??5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+PUBZVIGGR\JG3g8Q5)NW_CD#JKA_R[MGZOIS=?V"^WAC^KM[FCKD&_XI_QBUY0f?P6(AV\BC"IJN^QZJFYNFR>>Q#]VNB]JJZEBDE%^_H\PRDE1b>S7'@U]EB!HEO]P]KEXAGQ?9P \YOA\MKYDMEF$YRHNLMKMC7c<]9%BS[G@/FGM[V_IKVCEW9;R.R[MGZOIWJOG@"[PRHQJJB563\:$ERXFO.EFJZU^FJUBBV::]/QZJFYNFVIN@A!Z_RVBPFKCWg8n7X> I^TJK*ABFVYRBNQFNZ66Y+U^FJUBBRMJLM-V[V_IKVL9i6[?/H]UMJ)@MGUXUCMPIOY71X(TQGITECQLEMN,QZU^FJUY?85Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+du~fjUfyuQi_nww70=R8&CTZDA GDL\W\HDW@DP88S!SXL@[LHXKLFG#l}vnb]nq}YuWf>i5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+fjhkboo>i5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+cgkd`dl?<5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+cgkd`dlSb{{2e9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'on:Sb{{2e9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'on9Sb{{2e9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'on8Sb{{2e9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'on?Sb{{2e9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'on>Sb{{2d9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'ds=Razt3a8Q5)NW_CD#JKA_R[MGZOIS=?V"^WAC^KM[FCKD&xbd`h319V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'{cxeciPotv0a>S7'@U]EB!HEO]P]KEXAGQ?9P \YOA\MKYDMEF$t`l_g]f`bc(AVB9@#[PDNWW7<=R8&CTZDA GDL\W\HDW@DP88S!SXL@[LHXKLFG#~wac^d\aaab'\UOCXZ?389V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'zseoRhPeeef+PYCG\^:?l5Z0.K\RLI(OLDT_T@L_HLX00[)[PDHSD@PCDNO+vikVlTiiij/hFLQQ:76:k0Y=!F_WKL+BCIWZSEORGA[57^*V_IKVCESNKCL.qzjfYaWlnli"gKOTV?5;573\:$ERXFO.EFJZU^FJUBBV::]/QZJFYNFVIN@A!|yoa\bZir|:>0Y=!F_WKL+BCIWZSEORGA[57^*V_IKVCESNKCL.qzjfYj}qUmSb{{359V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'zseoRczx^p\kpr4m2_;#DQYIN-DAKYTQGITECU;5\,P]KEXAGUHIAB sxl`[wYblno$ERB=H/W\@JSS;01^<"GPVHM,C@HX[PDHSD@T44_-W\HDW@DTOHBC/r{mgZtXmmmn#XQKOTV37<=R8&CTZDA GDL\W\HDW@DP88S!SXL@[LHXKLFG#~wac^p\aaab'\UOCXZ>3`9V4*OX^@E$KH@PSXL@[LH\<<W%_T@L_HL\G@JK'zseoR|Peeef+lBH]]6;2>o4U1-J[SOH'NOES^WAC^KM_13Z&ZSEORGA_BGOH*u~fjUyShjhe.kGKPR;979;7X> I^TJK*ABFVYRBNQFNZ66Y+U^FJUBBRMJLM-p}keXzVe~x?h4U1-J[SOH'NOES^WAC^KM_13Z&ZSEORGA_BGOH*stm{UbbR`<1:W3+LYQAF%LICQ\YOA\MK]3>T$XUCMPIO]@AIJ(IZSEORHPMTZ05>S7'@U]EB!HEO]P]KEXAGQ?:P \YOA\MKYDMEF$M^WAC^P\IP^5n2_;#DQYIN-DAKYTQGITECU;6\,P]KEXAGUHIAB SIKEPZTBO::0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.QZJFYAWD_S?=5Z0.K\RLI(OLDT_T@L_HLX03[)[PDHSD@PCDNO+V_IKVXTAXV<3:W3+LYQAF%LICQ\YOA\MK]3>T$XUCMPIO]@AIJ([VKXUCMPF^PFC65<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"]PAR[MGZTXZLM8>6[?/H]UMJ)@MGUXUCMPIOY72X(TQGITECQLEMN,WZU^FJUMS_KH339V4*OX^@E$KH@PSXL@[LH\<?W%_T@L_HL\G@JK'ZUXUCMPR^PFC64<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"[\ES]@HNYUMN8n7X> I^TJK*ABFVYRBNQFNZ65Y+U^FJUBBRMJLM-VW@TXE\R9i6[?/H]UMJ)@MGUXUCMPIOY72X(TQGITECQLEMN,QVCUW[OL>k5Z0.K\RLI(OLDT_T@L_HLX03[)[PDHSD@PCDNO+PYAIEFBBJ<j;T2,MZPNG&MNBR]VNB]JJ^21U'YRBNQFN^AFHI)RW[CXECI<1:W3+LYQAF%LICQ\YOA\MK]3>T$XUCMPIO]@AIJ(]VY_MYMBD^l1a>S7'@U]EB!HEO]P]KEXAGQ?:P \YOA\MKYDMEF$YR]VNB]E6`=R8&CTZDA GDL\W\HDW@DP8;S!SXL@[LHXKLFG#XQ\YOA\V63<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"o|yoa\ip~XnVe~x>;4U1-J[SOH'NOES^WAC^KM_10Z&ZSEORGA_BGOH*gtqgiTaxvPr^mvp7b<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"mcobif`7b<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"hnlmkmc67<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"hnlmkmcZir|;n0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.dg5Zir|;n0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.dg6Zir|;n0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.dg7Zir|;n0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.dg0Zir|;n0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.dg1Zir|;o0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.ov|4Yh}}8h7X> I^TJK*ABFVYRBNQFNZ65Y+U^FJUBBRMJLM-qmvoio::0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.pjwlh`Wf?h5Z0.K\RLI(OLDT_T@L_HLX03[)[PDHSD@PCDNO+vikVlTiiij/H]K6I(RWME^X>74U1-J[SOH'NOES^WAC^KM_10Z&ZSEORGA_BGOH*u~fjUmShjhe.W\@JSS8:30Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.qzjfYaWlnli"[PDNWW56g<]9%BS[G@/FGM[V_IKVCEW98R.R[MGZOIWJOG@"}vnb]e[`b`m&cOCXZ30?1b?P6(AV\BC"IJN^QZJFYNFR>=Q#]VNB]JJZEBDE%xucmPf^ggc`)nLF__0<0<0:W3+LYQAF%LICQ\YOA\MK]3>T$XUCMPIO]@AIJ({pdhSkQ`uu17?P6(AV\BC"IJN^QZJFYNFR>=Q#]VNB]JJZEBDE%xucmPmtz\bZir|:>0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.qzjfYj}qUySb{{3d9V4*OX^@E$KH@PSXL@[LH\<?W%_T@L_HL\G@JK'zseoR|Peeef+LYK:A$^SIAZT2;8Q5)NW_CD#JKA_R[MGZOIS=<V"^WAC^KM[FCKD&yrbnQ}_dfda*SXLF__<>74U1-J[SOH'NOES^WAC^KM_10Z&ZSEORGA_BGOH*u~fjUyShjhe.W\@JSS9:k0Y=!F_WKL+BCIWZSEORGA[54^*V_IKVCESNKCL.qzjfYuWlnli"gKOTV?4;5f3\:$ERXFO.EFJZU^FJUBBV:9]/QZJFYNFVIN@A!|yoa\vZccol%bHB[[<0<04>S7'@U]EB!HEO]P]KEXAGQ?:P \YOA\MKYDMEF$t`l_s]lqq4a3\:$ERXFO.EFJZU^FJUBBV:9]/QZJFYNFVIN@A!zsdp\mkYi;81^<"GPVHM,C@HX[PDHSD@T46_-W\HDW@DTOHBC/@QZJFYAWD_S?<5Z0.K\RLI(OLDT_T@L_HLX02[)[PDHSD@PCDNO+DU^FJUYS@[W2g9V4*OX^@E$KH@PSXL@[LH\<>W%_T@L_HL\G@JK'ZBBJYQ]EF13?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%XUCMPF^OV\66<]9%BS[G@/FGM[V_IKVCEW99R.R[MGZOIWJOG@"]VNB]Q[HS_;:1^<"GPVHM,C@HX[PDHSD@T46_-W\HDW@DTOHBC/R]BW\HDWOUYIJ=<;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)TWHYRBNQ]_SGD77=R8&CTZDA GDL\W\HDW@DP8:S!SXL@[LHXKLFG#^Q\YOA\BZTBO:80Y=!F_WKL+BCIWZSEORGA[55^*V_IKVCESNKCL.Q\W\HDW[UYIJ==;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)R[LXTOAEPRDE1a>S7'@U]EB!HEO]P]KEXAGQ?;P \YOA\MKYDMEF$Y^K]_LW[6`=R8&CTZDA GDL\W\HDW@DP8:S!SXL@[LHXKLFG#X]JR^PFC7`<]9%BS[G@/FGM[V_IKVCEW99R.R[MGZOIWJOG@"[PF@NOMKA5m2_;#DQYIN-DAKYTQGITECU;7\,P]KEXAGUHIAB U^PJWLH@;81^<"GPVHM,C@HX[PDHSD@T46_-W\HDW@DTOHBC/T]PPDRDEMUe>h5Z0.K\RLI(OLDT_T@L_HLX02[)[PDHSD@PCDNO+PYTQGITJ?k4U1-J[SOH'NOES^WAC^KM_11Z&ZSEORGA_BGOH*SX[PDHS_=:;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)f{pdhS`{w_g]lqq523\:$ERXFO.EFJZU^FJUBBV:8]/QZJFYNFVIN@A!nsxl`[hsW{Udyy<k;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)ddfi`ii<k;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)aiefbbj=>;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)aiefbbjQ`uu0g?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%mh<Q`uu0g?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%mh?Q`uu0g?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%mh>Q`uu0g?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%mh9Q`uu0g?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%mh8Q`uu0f?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%fyu?Potv1g>S7'@U]EB!HEO]P]KEXAGQ?;P \YOA\MKYDMEF$~d}fnf13?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%ye~gag^mvp6c<]9%BS[G@/FGM[V_IKVCEW99R.R[MGZOIWJOG@"}vnb]e[`b`m&CTD?B!U^FLQQ5>3\:$ERXFO.EFJZU^FJUBBV:8]/QZJFYNFVIN@A!|yoa\bZccol%^SIAZT11:?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%xucmPf^ggc`)RWME^X<=n;T2,MZPNG&MNBR]VNB]JJ^20U'YRBNQFN^AFHI)tqgiTjRkkgd-j@JSS4948m6[?/H]UMJ)@MGUXUCMPIOY73X(TQGITECQLEMN,w|hdWoUnhjk iEMVP979;91^<"GPVHM,C@HX[PDHSD@T46_-W\HDW@DTOHBC/r{mgZ`Xg|~886[?/H]UMJ)@MGUXUCMPIOY73X(TQGITECQLEMN,w|hdWdsSkQ`uu17?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%xucmPmtz\vZir|:o0Y=!F_WKL+BCIWZSEORGA[55^*V_IKVCESNKCL.qzjfYuWlnli"GPL3J-QZBH]]927X> I^TJK*ABFVYRBNQFNZ64Y+U^FJUBBRMJLM-p}keXzVookh!Z_EMVP55>3\:$ERXFO.EFJZU^FJUBBV:8]/QZJFYNFVIN@A!|yoa\vZccol%^SIAZT01b?P6(AV\BC"IJN^QZJFYNFR><Q#]VNB]JJZEBDE%xucmPr^ggc`)nLF__0=0<a:W3+LYQAF%LICQ\YOA\MK]3?T$XUCMPIO]@AIJ({pdhSQjdfg,mAIR\5;5?=5Z0.K\RLI(OLDT_T@L_HLX02[)[PDHSD@PCDNO+vikVxTcxz=f:W3+LYQAF%LICQ\YOA\MK]3?T$XUCMPIO]@AIJ(}zoySd`Pn238Q5)NW_CD#JKA_R[MGZOIS=2V"^WAC^KM[FCKD&KXUCMPF^OV\67<]9%BS[G@/FGM[V_IKVCEW96R.R[MGZOIWJOG@"O\YOA\VZKRP;l0Y=!F_WKL+BCIWZSEORGA[5:^*V_IKVCESNKCL.QKMCRXZLM8<6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,W\HDWOUFYU=?;T2,MZPNG&MNBR]VNB]JJ^2?U'YRBNQFN^AFHI)TQGIT^RCZX218Q5)NW_CD#JKA_R[MGZOIS=2V"^WAC^KM[FCKD&YTM^WAC^D\V@A4;2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB S^CP]KEXZVXNK><4U1-J[SOH'NOES^WAC^KM_1>Z&ZSEORGA_BGOH*UX[PDHSKQ]EF11?P6(AV\BC"IJN^QZJFYNFR>3Q#]VNB]JJZEBDE%XS^WAC^P\V@A4:2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB URGQ[FJLW[OL>h5Z0.K\RLI(OLDT_T@L_HLX0=[)[PDHSD@PCDNO+PUBZVG^T?k4U1-J[SOH'NOES^WAC^KM_1>Z&ZSEORGA_BGOH*STM[UYIJ<i;T2,MZPNG&MNBR]VNB]JJ^2?U'YRBNQFN^AFHI)RWOKG@D@H2d9V4*OX^@E$KH@PSXL@[LH\<1W%_T@L_HL\G@JK'\UYE^GAG238Q5)NW_CD#JKA_R[MGZOIS=2V"^WAC^KM[FCKD&_T_YO[CLF\j7c<]9%BS[G@/FGM[V_IKVCEW96R.R[MGZOIWJOG@"[PSXL@[C4b3\:$ERXFO.EFJZU^FJUBBV:7]/QZJFYNFVIN@A!Z_R[MGZT4=2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB ar{mgZkrpVlTcxz<5:W3+LYQAF%LICQ\YOA\MK]30T$XUCMPIO]@AIJ(izseoRczx^p\kpr5l2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB cmm`o`b5l2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB f`nomka492_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB f`nomkaXg|~9h6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ba7Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ba4Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ba5Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ba2Xg|~9h6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ba3Xg|~9i6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,ip~6Wf>n5Z0.K\RLI(OLDT_T@L_HLX0=[)[PDHSD@PCDNO+wotagm8<6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,vlunfnUdyy=j;T2,MZPNG&MNBR]VNB]JJ^2?U'YRBNQFN^AFHI)tqgiTjRkkgd-J[M4K&\UOCXZ<9:W3+LYQAF%LICQ\YOA\MK]30T$XUCMPIO]@AIJ({pdhSkQjdfg,QZBH]]:856[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,w|hdWoUnhjk U^FLQQ74i2_;#DQYIN-DAKYTQGITECU;8\,P]KEXAGUHIAB sxl`[cYblno$eIAZT=2=7d=R8&CTZDA GDL\W\HDW@DP85S!SXL@[LHXKLFG#~wac^d\aaab'`NDYY2>>228Q5)NW_CD#JKA_R[MGZOIS=2V"^WAC^KM[FCKD&yrbnQi_nww71=R8&CTZDA GDL\W\HDW@DP85S!SXL@[LHXKLFG#~wac^ov|Z`Xg|~886[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,w|hdWdsSQ`uu1f?P6(AV\BC"IJN^QZJFYNFR>3Q#]VNB]JJZEBDE%xucmPr^ggc`)NWE8C"XQKOTV0=>S7'@U]EB!HEO]P]KEXAGQ?4P \YOA\MKYDMEF$t`l_s]f`bc(]VNDYY><9:W3+LYQAF%LICQ\YOA\MK]30T$XUCMPIO]@AIJ({pdhSQjdfg,QZBH]];8m6[?/H]UMJ)@MGUXUCMPIOY7<X(TQGITECQLEMN,w|hdW{Unhjk iEMVP969;h1^<"GPVHM,C@HX[PDHSD@T49_-W\HDW@DTOHBC/r{mgZtXmmmn#dJ@UU>2:66<]9%BS[G@/FGM[V_IKVCEW96R.R[MGZOIWJOG@"}vnb]q[jss:o1^<"GPVHM,C@HX[PDHSD@T49_-W\HDW@DTOHBC/tqfvZoiWg9:7X> I^TJK*ABFVYRBNQFNZ6:Y+U^FJUBBRMJLM-BW\HDWOUFYU=>;T2,MZPNG&MNBR]VNB]JJ^2>U'YRBNQFN^AFHI)F[PDHS_QBUY0e?P6(AV\BC"IJN^QZJFYNFR>2Q#]VNB]JJZEBDE%XDDH[_SGD75=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#^WAC^D\IP^482_;#DQYIN-DAKYTQGITECU;9\,P]KEXAGUHIAB SXL@[WYJ]Q987X> I^TJK*ABFVYRBNQFNZ6:Y+U^FJUBBRMJLM-P[DU^FJUMS_KH329V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'ZUJ_T@L_S]QAB553\:$ERXFO.EFJZU^FJUBBV:6]/QZJFYNFVIN@A!\_R[MGZ@XZLM8>6[?/H]UMJ)@MGUXUCMPIOY7=X(TQGITECQLEMN,WZU^FJUYS_KH339V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'\YN^RMCK^PFC7c<]9%BS[G@/FGM[V_IKVCEW97R.R[MGZOIWJOG@"[\ES]NQ]4b3\:$ERXFO.EFJZU^FJUBBV:6]/QZJFYNFVIN@A!ZSDP\V@A5n2_;#DQYIN-DAKYTQGITECU;9\,P]KEXAGUHIAB U^DBHIOIO;o0Y=!F_WKL+BCIWZSEORGA[5;^*V_IKVCESNKCL.W\VLUNFN9:7X> I^TJK*ABFVYRBNQFNZ6:Y+U^FJUBBRMJLM-V[VRF\JGOSc<j;T2,MZPNG&MNBR]VNB]JJ^2>U'YRBNQFN^AFHI)RWZSEORH=e:W3+LYQAF%LICQ\YOA\MK]31T$XUCMPIO]@AIJ(]VYRBNQ]349V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'hyrbnQbuy]e[jss;<1^<"GPVHM,C@HX[PDHSD@T48_-W\HDW@DTOHBC/`qzjfYj}qUySb{{2e9V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'jfdofkk2e9V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'okg`d`h309V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'okg`d`h_nww6a=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#kj>_nww6a=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#kj=_nww6a=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#kj<_nww6a=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#kj;_nww6a=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#kj:_nww6`=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#`{w1^mvp7e<]9%BS[G@/FGM[V_IKVCEW97R.R[MGZOIWJOG@"|fshld75=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#g|ioe\kpr4m2_;#DQYIN-DAKYTQGITECU;9\,P]KEXAGUHIAB sxl`[cYblno$ERF=L/W\@JSS;01^<"GPVHM,C@HX[PDHSD@T48_-W\HDW@DTOHBC/r{mgZ`Xmmmn#XQKOTV37<=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#~wac^d\aaab'\UOCXZ>3`9V4*OX^@E$KH@PSXL@[LH\<0W%_T@L_HL\G@JK'zseoRhPeeef+lBH]]6;2>o4U1-J[SOH'NOES^WAC^KM_1?Z&ZSEORGA_BGOH*u~fjUmShjhe.kGKPR;979;7X> I^TJK*ABFVYRBNQFNZ6:Y+U^FJUBBRMJLM-p}keXnVe~x>:4U1-J[SOH'NOES^WAC^KM_1?Z&ZSEORGA_BGOH*u~fjUfyuQi_nww71=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#~wac^ov|ZtXg|~8i6[?/H]UMJ)@MGUXUCMPIOY7=X(TQGITECQLEMN,w|hdW{Unhjk I^N1L+SXLF__?45Z0.K\RLI(OLDT_T@L_HLX0<[)[PDHSD@PCDNO+vikVxTiiij/T]GKPR7;01^<"GPVHM,C@HX[PDHSD@T48_-W\HDW@DTOHBC/r{mgZtXmmmn#XQKOTV27d=R8&CTZDA GDL\W\HDW@DP84S!SXL@[LHXKLFG#~wac^p\aaab'`NDYY2?>2c8Q5)NW_CD#JKA_R[MGZOIS=3V"^WAC^KM[FCKD&yrbnQ}_dfda*oCG\^7=3=?;T2,MZPNG&MNBR]VNB]JJ^2>U'YRBNQFN^AFHI)tqgiT~Razt3d8Q5)NW_CD#JKA_R[MGZOIS=3V"^WAC^KM[FCKD&xiQfn^l05>S7'@U]EB!HEO]P]KEXAGQ><P \YOA\MKYDMEF$M^WAC^D\IP^492_;#DQYIN-DAKYTQGITECU:0\,P]KEXAGUHIAB AR[MGZTXE\R9j6[?/H]UMJ)@MGUXUCMPIOY64X(TQGITECQLEMN,WMOA\VXNK>>4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*U^FJUMS@[W319V4*OX^@E$KH@PSXL@[LH\=9W%_T@L_HL\G@JK'ZSEOR\PMTZ07>S7'@U]EB!HEO]P]KEXAGQ><P \YOA\MKYDMEF$_RO\YOA\BZTBO:90Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.Q\EV_IKVXT^HI<2:W3+LYQAF%LICQ\YOA\MK]28T$XUCMPIO]@AIJ([VYRBNQI_SGD77=R8&CTZDA GDL\W\HDW@DP9=S!SXL@[LHXKLFG#^Q\YOA\VZTBO:80Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.WPAWYDDBUYIJ<j;T2,MZPNG&MNBR]VNB]JJ^37U'YRBNQFN^AFHI)R[LXTAXV=e:W3+LYQAF%LICQ\YOA\MK]28T$XUCMPIO]@AIJ(]ZOYS_KH2g9V4*OX^@E$KH@PSXL@[LH\=9W%_T@L_HL\G@JK'\UMMABFNF0f?P6(AV\BC"IJN^QZJFYNFR?;Q#]VNB]JJZEBDE%^S_G\IOE05>S7'@U]EB!HEO]P]KEXAGQ><P \YOA\MKYDMEF$YR][AUAN@Zh5m2_;#DQYIN-DAKYTQGITECU:0\,P]KEXAGUHIAB U^QZJFYA:l1^<"GPVHM,C@HX[PDHSD@T51_-W\HDW@DTOHBC/T]P]KEXZ:?0Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.cp}keXe|rTjRazt278Q5)NW_CD#JKA_R[MGZOIS<:V"^WAC^KM[FCKD&kxucmPmtz\vZir|;n0Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.aokfmbl;n0Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.dbhioio:;0Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.dbhioioVe~x?j4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*`c9Ve~x?j4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*`c:Ve~x?j4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*`c;Ve~x?j4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*`c<Ve~x?j4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*`c=Ve~x?k4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*krp8Udyy<l;T2,MZPNG&MNBR]VNB]JJ^37U'YRBNQFN^AFHI)uazcek>>4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*tn{`dlSb{{3d9V4*OX^@E$KH@PSXL@[LH\=9W%_T@L_HL\G@JK'zseoRhPeeef+LYO:E$^SIAZT2;8Q5)NW_CD#JKA_R[MGZOIS<:V"^WAC^KM[FCKD&yrbnQi_dfda*SXLF__<>74U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*u~fjUmShjhe.W\@JSS9:k0Y=!F_WKL+BCIWZSEORGA[42^*V_IKVCESNKCL.qzjfYaWlnli"gKOTV?4;5f3\:$ERXFO.EFJZU^FJUBBV;?]/QZJFYNFVIN@A!|yoa\bZccol%bHB[[<0<04>S7'@U]EB!HEO]P]KEXAGQ><P \YOA\MKYDMEF$t`l_g]lqq533\:$ERXFO.EFJZU^FJUBBV;?]/QZJFYNFVIN@A!|yoa\ip~XnVe~x>:4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*u~fjUfyuQ}_nww7`=R8&CTZDA GDL\W\HDW@DP9=S!SXL@[LHXKLFG#~wac^p\aaab'@UG>E Z_EMVP6?<]9%BS[G@/FGM[V_IKVCEW8>R.R[MGZOIWJOG@"}vnb]q[`b`m&_THB[[02;8Q5)NW_CD#JKA_R[MGZOIS<:V"^WAC^KM[FCKD&yrbnQ}_dfda*SXLF__=>o4U1-J[SOH'NOES^WAC^KM_06Z&ZSEORGA_BGOH*u~fjUyShjhe.kGKPR;879j7X> I^TJK*ABFVYRBNQFNZ73Y+U^FJUBBRMJLM-p}keXzVookh!fDNWW848482_;#DQYIN-DAKYTQGITECU:0\,P]KEXAGUHIAB sxl`[wYh}}8m7X> I^TJK*ABFVYRBNQFNZ73Y+U^FJUBBRMJLM-vw`tXagUe?<5Z0.K\RLI(OLDT_T@L_HLX14[)[PDHSD@PCDNO+DU^FJUMS@[W309V4*OX^@E$KH@PSXL@[LH\=8W%_T@L_HL\G@JK'HYRBNQ]_LW[6c=R8&CTZDA GDL\W\HDW@DP9<S!SXL@[LHXKLFG#^FFFU]QAB573\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!\YOA\BZKRP::0Y=!F_WKL+BCIWZSEORGA[43^*V_IKVCESNKCL.QZJFYUWD_S?>5Z0.K\RLI(OLDT_T@L_HLX14[)[PDHSD@PCDNO+VYF[PDHSKQ]EF10?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%XSL]VNB]Q[WC@;;1^<"GPVHM,C@HX[PDHSD@T50_-W\HDW@DTOHBC/R]P]KEXNVXNK><4U1-J[SOH'NOES^WAC^KM_07Z&ZSEORGA_BGOH*UX[PDHS_Q]EF11?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%^_H\PCMI\V@A5m2_;#DQYIN-DAKYTQGITECU:1\,P]KEXAGUHIAB URGQ[HS_:l1^<"GPVHM,C@HX[PDHSD@T50_-W\HDW@DTOHBC/TQFVZTBO;l0Y=!F_WKL+BCIWZSEORGA[43^*V_IKVCESNKCL.W\BDJKAGM9i6[?/H]UMJ)@MGUXUCMPIOY65X(TQGITECQLEMN,QZTN[@DL?<5Z0.K\RLI(OLDT_T@L_HLX14[)[PDHSD@PCDNO+PYT\H^HAIQa2d9V4*OX^@E$KH@PSXL@[LH\=8W%_T@L_HL\G@JK'\UXUCMPF3g8Q5)NW_CD#JKA_R[MGZOIS<;V"^WAC^KM[FCKD&_T_T@L_S16?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%jt`l_lw{[cYh}}9>7X> I^TJK*ABFVYRBNQFNZ72Y+U^FJUBBRMJLM-bw|hdWdsSQ`uu0g?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%h`bmdee0g?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%mmabfnf12?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%mmabfnf]lqq4c3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!id0]lqq4c3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!id3]lqq4c3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!id2]lqq4c3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!id5]lqq4c3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!id4]lqq4b3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!buy3\kpr5k2_;#DQYIN-DAKYTQGITECU:1\,P]KEXAGUHIAB rhqjjb573\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!}irkmcZir|:o0Y=!F_WKL+BCIWZSEORGA[43^*V_IKVCESNKCL.qzjfYaWlnli"GPH3N-QZBH]]927X> I^TJK*ABFVYRBNQFNZ72Y+U^FJUBBRMJLM-p}keXnVookh!Z_EMVP55>3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!|yoa\bZccol%^SIAZT01b?P6(AV\BC"IJN^QZJFYNFR?:Q#]VNB]JJZEBDE%xucmPf^ggc`)nLF__0=0<a:W3+LYQAF%LICQ\YOA\MK]29T$XUCMPIO]@AIJ({pdhSkQjdfg,mAIR\5;5?=5Z0.K\RLI(OLDT_T@L_HLX14[)[PDHSD@PCDNO+vikVlTcxz<4:W3+LYQAF%LICQ\YOA\MK]29T$XUCMPIO]@AIJ({pdhS`{w_g]lqq533\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!|yoa\ip~XzVe~x>k4U1-J[SOH'NOES^WAC^KM_07Z&ZSEORGA_BGOH*u~fjUyShjhe.K\H7N)]VNDYY=6;T2,MZPNG&MNBR]VNB]JJ^36U'YRBNQFN^AFHI)tqgiT~Rkkgd-V[AIR\9927X> I^TJK*ABFVYRBNQFNZ72Y+U^FJUBBRMJLM-p}keXzVookh!Z_EMVP45f3\:$ERXFO.EFJZU^FJUBBV;>]/QZJFYNFVIN@A!|yoa\vZccol%bHB[[<1<0e>S7'@U]EB!HEO]P]KEXAGQ>=P \YOA\MKYDMEF$t`l_s]f`bc(aME^X1?1319V4*OX^@E$KH@PSXL@[LH\=8W%_T@L_HL\G@JK'zseoR|Potv1b>S7'@U]EB!HEO]P]KEXAGQ>=P \YOA\MKYDMEF$y~k}_hl\j67<]9%BS[G@/FGM[V_IKVCEW8<R.R[MGZOIWJOG@"O\YOA\BZKRP:;0Y=!F_WKL+BCIWZSEORGA[40^*V_IKVCESNKCL.CP]KEXZVG^T?h4U1-J[SOH'NOES^WAC^KM_04Z&ZSEORGA_BGOH*UOAO^T^HI<0:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ([PDHSKQBUY13?P6(AV\BC"IJN^QZJFYNFR?9Q#]VNB]JJZEBDE%XUCMPR^OV\65<]9%BS[G@/FGM[V_IKVCEW8<R.R[MGZOIWJOG@"]PAR[MGZ@XZLM8?6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,WZGTQGIT^R\JG208Q5)NW_CD#JKA_R[MGZOIS<8V"^WAC^KM[FCKD&YT_T@L_G]QAB553\:$ERXFO.EFJZU^FJUBBV;=]/QZJFYNFVIN@A!\_R[MGZTXZLM8>6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,QVCUWJF@S_KH2d9V4*OX^@E$KH@PSXL@[LH\=;W%_T@L_HL\G@JK'\YN^RCZX3g8Q5)NW_CD#JKA_R[MGZOIS<8V"^WAC^KM[FCKD&_XI_Q]EF0e?P6(AV\BC"IJN^QZJFYNFR?9Q#]VNB]JJZEBDE%^SKOCLHLD6`=R8&CTZDA GDL\W\HDW@DP9?S!SXL@[LHXKLFG#XQ]IRKMC67<]9%BS[G@/FGM[V_IKVCEW8<R.R[MGZOIWJOG@"[PSUCWGHBXf;o0Y=!F_WKL+BCIWZSEORGA[40^*V_IKVCESNKCL.W\W\HDWO8n7X> I^TJK*ABFVYRBNQFNZ71Y+U^FJUBBRMJLM-V[V_IKVX896[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,evikVg~tRhPotv01>S7'@U]EB!HEO]P]KEXAGQ>>P \YOA\MKYDMEF$m~wac^ov|ZtXg|~9h6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,giidcln9h6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,bdjkagm8=6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,bdjkagmTcxz=d:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(nm;Tcxz=d:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(nm8Tcxz=d:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(nm9Tcxz=d:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(nm>Tcxz=d:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(nm?Tcxz=e:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(e|r:Sb{{2b9V4*OX^@E$KH@PSXL@[LH\=;W%_T@L_HL\G@JK'{cxeci<0:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ(z`ybbjQ`uu1f?P6(AV\BC"IJN^QZJFYNFR?9Q#]VNB]JJZEBDE%xucmPf^ggc`)NWA8G"XQKOTV0=>S7'@U]EB!HEO]P]KEXAGQ>>P \YOA\MKYDMEF$t`l_g]f`bc(]VNDYY><9:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ({pdhSkQjdfg,QZBH]];8m6[?/H]UMJ)@MGUXUCMPIOY66X(TQGITECQLEMN,w|hdWoUnhjk iEMVP969;h1^<"GPVHM,C@HX[PDHSD@T53_-W\HDW@DTOHBC/r{mgZ`Xmmmn#dJ@UU>2:66<]9%BS[G@/FGM[V_IKVCEW8<R.R[MGZOIWJOG@"}vnb]e[jss;=1^<"GPVHM,C@HX[PDHSD@T53_-W\HDW@DTOHBC/r{mgZkrpVlTcxz<4:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ({pdhS`{w_s]lqq5b3\:$ERXFO.EFJZU^FJUBBV;=]/QZJFYNFVIN@A!|yoa\vZccol%BSA<G.T]GKPR412_;#DQYIN-DAKYTQGITECU:2\,P]KEXAGUHIAB sxl`[wYblno$YRJ@UU20=>S7'@U]EB!HEO]P]KEXAGQ>>P \YOA\MKYDMEF$t`l_s]f`bc(]VNDYY?<a:W3+LYQAF%LICQ\YOA\MK]2:T$XUCMPIO]@AIJ({pdhSQjdfg,mAIR\5:5?l5Z0.K\RLI(OLDT_T@L_HLX17[)[PDHSD@PCDNO+vikVxTiiij/hFLQQ:66::0Y=!F_WKL+BCIWZSEORGA[40^*V_IKVCESNKCL.qzjfYuWf>k5Z0.K\RLI(OLDT_T@L_HLX17[)[PDHSD@PCDNO+pubzVceSc=>;T2,MZPNG&MNBR]VNB]JJ^34U'YRBNQFN^AFHI)F[PDHSKQBUY12?P6(AV\BC"IJN^QZJFYNFR?8Q#]VNB]JJZEBDE%J_T@L_S]NQ]4a3\:$ERXFO.EFJZU^FJUBBV;<]/QZJFYNFVIN@A!\HHDW[WC@;91^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/R[MGZ@XE\R8<6[?/H]UMJ)@MGUXUCMPIOY67X(TQGITECQLEMN,W\HDW[UFYU=<;T2,MZPNG&MNBR]VNB]JJ^34U'YRBNQFN^AFHI)TWHYRBNQI_SGD76=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#^QNSXL@[WYUMN997X> I^TJK*ABFVYRBNQFNZ70Y+U^FJUBBRMJLM-P[V_IKVLT^HI<2:W3+LYQAF%LICQ\YOA\MK]2;T$XUCMPIO]@AIJ([VYRBNQ]_SGD77=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#X]JR^AOOZTBO;o0Y=!F_WKL+BCIWZSEORGA[41^*V_IKVCESNKCL.WPAWYJ]Q8n7X> I^TJK*ABFVYRBNQFNZ70Y+U^FJUBBRMJLM-VW@TXZLM9j6[?/H]UMJ)@MGUXUCMPIOY67X(TQGITECQLEMN,QZ@FDECEK?k4U1-J[SOH'NOES^WAC^KM_05Z&ZSEORGA_BGOH*SXZ@YBBJ=>;T2,MZPNG&MNBR]VNB]JJ^34U'YRBNQFN^AFHI)RWZ^JXNCK_o0f?P6(AV\BC"IJN^QZJFYNFR?8Q#]VNB]JJZEBDE%^S^WAC^D1a>S7'@U]EB!HEO]P]KEXAGQ>?P \YOA\MKYDMEF$YR]VNB]Q70=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#l}vnb]nq}YaWf?85Z0.K\RLI(OLDT_T@L_HLX16[)[PDHSD@PCDNO+du~fjUfyuQ}_nww6a=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#nb`cjgg6a=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#koclhld74=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#koclhld[jss:m1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/gf2[jss:m1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/gf1[jss:m1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/gf0[jss:m1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/gf7[jss:m1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/gf6[jss:l1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/lw{5Zir|;i0Y=!F_WKL+BCIWZSEORGA[41^*V_IKVCESNKCL.pjwlh`;91^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/skpmkaXg|~8i6[?/H]UMJ)@MGUXUCMPIOY67X(TQGITECQLEMN,w|hdWoUnhjk I^J1H+SXLF__?45Z0.K\RLI(OLDT_T@L_HLX16[)[PDHSD@PCDNO+vikVlTiiij/T]GKPR7;01^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/r{mgZ`Xmmmn#XQKOTV27d=R8&CTZDA GDL\W\HDW@DP9>S!SXL@[LHXKLFG#~wac^d\aaab'`NDYY2?>2c8Q5)NW_CD#JKA_R[MGZOIS<9V"^WAC^KM[FCKD&yrbnQi_dfda*oCG\^7=3=?;T2,MZPNG&MNBR]VNB]JJ^34U'YRBNQFN^AFHI)tqgiTjRazt268Q5)NW_CD#JKA_R[MGZOIS<9V"^WAC^KM[FCKD&yrbnQbuy]e[jss;=1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/r{mgZkrpVxTcxz<e:W3+LYQAF%LICQ\YOA\MK]2;T$XUCMPIO]@AIJ({pdhSQjdfg,MZJ5@'_THB[[389V4*OX^@E$KH@PSXL@[LH\=:W%_T@L_HL\G@JK'zseoR|Peeef+PYCG\^;?45Z0.K\RLI(OLDT_T@L_HLX16[)[PDHSD@PCDNO+vikVxTiiij/T]GKPR6;h1^<"GPVHM,C@HX[PDHSD@T52_-W\HDW@DTOHBC/r{mgZtXmmmn#dJ@UU>3:6g<]9%BS[G@/FGM[V_IKVCEW8=R.R[MGZOIWJOG@"}vnb]q[`b`m&cOCXZ31?13?P6(AV\BC"IJN^QZJFYNFR?8Q#]VNB]JJZEBDE%xucmPr^mvp7`<]9%BS[G@/FGM[V_IKVCEW8=R.R[MGZOIWJOG@"{|es]jjZh492_;#DQYIN-DAKYTQGITECU:4\,P]KEXAGUHIAB AR[MGZ@XE\R8=6[?/H]UMJ)@MGUXUCMPIOY60X(TQGITECQLEMN,EV_IKVXTAXV=f:W3+LYQAF%LICQ\YOA\MK]2<T$XUCMPIO]@AIJ([ACMXR\JG228Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&YRBNQI_LW[75=R8&CTZDA GDL\W\HDW@DP99S!SXL@[LHXKLFG#^WAC^P\IP^4;2_;#DQYIN-DAKYTQGITECU:4\,P]KEXAGUHIAB S^CP]KEXNVXNK>=4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*UXIZSEOR\PRDE06>S7'@U]EB!HEO]P]KEXAGQ>8P \YOA\MKYDMEF$_R]VNB]E[WC@;;1^<"GPVHM,C@HX[PDHSD@T55_-W\HDW@DTOHBC/R]P]KEXZVXNK><4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*STM[UH@FQ]EF0f?P6(AV\BC"IJN^QZJFYNFR??Q#]VNB]JJZEBDE%^_H\PMTZ1a>S7'@U]EB!HEO]P]KEXAGQ>8P \YOA\MKYDMEF$Y^K]_SGD6c=R8&CTZDA GDL\W\HDW@DP99S!SXL@[LHXKLFG#XQIAMNJJB4b3\:$ERXFO.EFJZU^FJUBBV;;]/QZJFYNFVIN@A!Z_SKPMKA492_;#DQYIN-DAKYTQGITECU:4\,P]KEXAGUHIAB U^QWEQEJLVd9i6[?/H]UMJ)@MGUXUCMPIOY60X(TQGITECQLEMN,QZU^FJUM>h5Z0.K\RLI(OLDT_T@L_HLX11[)[PDHSD@PCDNO+PYTQGIT^>;4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*gtqgiTaxvPf^mvp63<]9%BS[G@/FGM[V_IKVCEW8:R.R[MGZOIWJOG@"o|yoa\ip~XzVe~x?j4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*ekgjanh?j4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*`fdecek>?4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*`fdecekRazt3f8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&lo=Razt3f8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&lo>Razt3f8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&lo?Razt3f8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&lo8Razt3f8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&lo9Razt3g8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&g~t<Q`uu0`?P6(AV\BC"IJN^QZJFYNFR??Q#]VNB]JJZEBDE%ye~gag228Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&xbd`h_nww7`=R8&CTZDA GDL\W\HDW@DP99S!SXL@[LHXKLFG#~wac^d\aaab'@UC>A Z_EMVP6?<]9%BS[G@/FGM[V_IKVCEW8:R.R[MGZOIWJOG@"}vnb]e[`b`m&_THB[[02;8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&yrbnQi_dfda*SXLF__=>o4U1-J[SOH'NOES^WAC^KM_02Z&ZSEORGA_BGOH*u~fjUmShjhe.kGKPR;879j7X> I^TJK*ABFVYRBNQFNZ77Y+U^FJUBBRMJLM-p}keXnVookh!fDNWW848482_;#DQYIN-DAKYTQGITECU:4\,P]KEXAGUHIAB sxl`[cYh}}9?7X> I^TJK*ABFVYRBNQFNZ77Y+U^FJUBBRMJLM-p}keXe|rTjRazt268Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&yrbnQbuy]q[jss;l1^<"GPVHM,C@HX[PDHSD@T55_-W\HDW@DTOHBC/r{mgZtXmmmn#DQC2I,V[AIR\:30Y=!F_WKL+BCIWZSEORGA[46^*V_IKVCESNKCL.qzjfYuWlnli"[PDNWW46?<]9%BS[G@/FGM[V_IKVCEW8:R.R[MGZOIWJOG@"}vnb]q[`b`m&_THB[[12c8Q5)NW_CD#JKA_R[MGZOIS<>V"^WAC^KM[FCKD&yrbnQ}_dfda*oCG\^7<3=n;T2,MZPNG&MNBR]VNB]JJ^33U'YRBNQFN^AFHI)tqgiT~Rkkgd-j@JSS4848<6[?/H]UMJ)@MGUXUCMPIOY60X(TQGITECQLEMN,w|hdW{Udyy<i;T2,MZPNG&MNBR]VNB]JJ^33U'YRBNQFN^AFHI)r{lxTecQa309V4*OX^@E$KH@PSXL@[LH\=<W%_T@L_HL\G@JK'HYRBNQI_LW[74=R8&CTZDA GDL\W\HDW@DP98S!SXL@[LHXKLFG#L]VNB]Q[HS_:o1^<"GPVHM,C@HX[PDHSD@T54_-W\HDW@DTOHBC/RJJBQYUMN9;7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-P]KEXNVG^T>>4U1-J[SOH'NOES^WAC^KM_03Z&ZSEORGA_BGOH*U^FJUYS@[W329V4*OX^@E$KH@PSXL@[LH\=<W%_T@L_HL\G@JK'ZUJ_T@L_G]QAB543\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!\_@QZJFYUW[OL??5Z0.K\RLI(OLDT_T@L_HLX10[)[PDHSD@PCDNO+VYTQGITJR\JG208Q5)NW_CD#JKA_R[MGZOIS<?V"^WAC^KM[FCKD&YT_T@L_S]QAB553\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!ZSDP\GIMXZLM9i6[?/H]UMJ)@MGUXUCMPIOY61X(TQGITECQLEMN,QVCUWD_S>h5Z0.K\RLI(OLDT_T@L_HLX10[)[PDHSD@PCDNO+PUBZVXNK?h4U1-J[SOH'NOES^WAC^KM_03Z&ZSEORGA_BGOH*SXNHFGECI=e:W3+LYQAF%LICQ\YOA\MK]2=T$XUCMPIO]@AIJ(]VXB_D@H309V4*OX^@E$KH@PSXL@[LH\=<W%_T@L_HL\G@JK'\UXXLZLME]m6`=R8&CTZDA GDL\W\HDW@DP98S!SXL@[LHXKLFG#XQ\YOA\B7c<]9%BS[G@/FGM[V_IKVCEW8;R.R[MGZOIWJOG@"[PSXL@[W523\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!nsxl`[hsWoUdyy=:;T2,MZPNG&MNBR]VNB]JJ^32U'YRBNQFN^AFHI)f{pdhS`{w_s]lqq4c3\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!llnahaa4c3\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!iamnjjb563\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!iamnjjbYh}}8o7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-e`4Yh}}8o7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-e`7Yh}}8o7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-e`6Yh}}8o7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-e`1Yh}}8o7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-e`0Yh}}8n7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-nq}7Xg|~9o6[?/H]UMJ)@MGUXUCMPIOY61X(TQGITECQLEMN,vlunfn9;7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-qmvoioVe~x>k4U1-J[SOH'NOES^WAC^KM_03Z&ZSEORGA_BGOH*u~fjUmShjhe.K\L7J)]VNDYY=6;T2,MZPNG&MNBR]VNB]JJ^32U'YRBNQFN^AFHI)tqgiTjRkkgd-V[AIR\9927X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-p}keXnVookh!Z_EMVP45f3\:$ERXFO.EFJZU^FJUBBV;:]/QZJFYNFVIN@A!|yoa\bZccol%bHB[[<1<0e>S7'@U]EB!HEO]P]KEXAGQ>9P \YOA\MKYDMEF$t`l_g]f`bc(aME^X1?1319V4*OX^@E$KH@PSXL@[LH\=<W%_T@L_HL\G@JK'zseoRhPotv00>S7'@U]EB!HEO]P]KEXAGQ>9P \YOA\MKYDMEF$t`l_lw{[cYh}}9?7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-p}keXe|rT~Razt2g8Q5)NW_CD#JKA_R[MGZOIS<?V"^WAC^KM[FCKD&yrbnQ}_dfda*OXD;B%YRJ@UU1:?P6(AV\BC"IJN^QZJFYNFR?>Q#]VNB]JJZEBDE%xucmPr^ggc`)RWME^X==6;T2,MZPNG&MNBR]VNB]JJ^32U'YRBNQFN^AFHI)tqgiT~Rkkgd-V[AIR\89j7X> I^TJK*ABFVYRBNQFNZ76Y+U^FJUBBRMJLM-p}keXzVookh!fDNWW8584i2_;#DQYIN-DAKYTQGITECU:5\,P]KEXAGUHIAB sxl`[wYblno$eIAZT=3=75=R8&CTZDA GDL\W\HDW@DP98S!SXL@[LHXKLFG#~wac^p\kpr5n2_;#DQYIN-DAKYTQGITECU:5\,P]KEXAGUHIAB urgq[lhXf:;0Y=!F_WKL+BCIWZSEORGA[44^*V_IKVCESNKCL.CP]KEXNVG^T>?4U1-J[SOH'NOES^WAC^KM_00Z&ZSEORGA_BGOH*GTQGIT^RCZX3d8Q5)NW_CD#JKA_R[MGZOIS<<V"^WAC^KM[FCKD&YCEKZPRDE04>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$_T@L_G]NQ]573\:$ERXFO.EFJZU^FJUBBV;9]/QZJFYNFVIN@A!\YOA\VZKRP:90Y=!F_WKL+BCIWZSEORGA[44^*V_IKVCESNKCL.Q\EV_IKVLT^HI<3:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ([VKXUCMPR^PFC64<]9%BS[G@/FGM[V_IKVCEW88R.R[MGZOIWJOG@"]PSXL@[CYUMN997X> I^TJK*ABFVYRBNQFNZ75Y+U^FJUBBRMJLM-P[V_IKVXT^HI<2:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ(]ZOYSNBD_SGD6`=R8&CTZDA GDL\W\HDW@DP9;S!SXL@[LHXKLFG#X]JR^OV\7c<]9%BS[G@/FGM[V_IKVCEW88R.R[MGZOIWJOG@"[\ES]QAB4a3\:$ERXFO.EFJZU^FJUBBV;9]/QZJFYNFVIN@A!Z_GCOHLH@:l1^<"GPVHM,C@HX[PDHSD@T57_-W\HDW@DTOHBC/T]QMVOIO:;0Y=!F_WKL+BCIWZSEORGA[44^*V_IKVCESNKCL.W\WQGSKDNTb?k4U1-J[SOH'NOES^WAC^KM_00Z&ZSEORGA_BGOH*SX[PDHSK<j;T2,MZPNG&MNBR]VNB]JJ^31U'YRBNQFN^AFHI)RWZSEOR\<5:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ(izseoRczx^d\kpr4=2_;#DQYIN-DAKYTQGITECU:6\,P]KEXAGUHIAB ar{mgZkrpVxTcxz=d:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ(keehghj=d:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ(nhfgeci<1:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ(nhfgeciPotv1`>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$ji?Potv1`>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$ji<Potv1`>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$ji=Potv1`>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$ji:Potv1`>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$ji;Potv1a>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$axv>_nww6f=R8&CTZDA GDL\W\HDW@DP9;S!SXL@[LHXKLFG#g|ioe04>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$~d}fnf]lqq5b3\:$ERXFO.EFJZU^FJUBBV;9]/QZJFYNFVIN@A!|yoa\bZccol%BSE<C.T]GKPR412_;#DQYIN-DAKYTQGITECU:6\,P]KEXAGUHIAB sxl`[cYblno$YRJ@UU20=>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$t`l_g]f`bc(]VNDYY?<a:W3+LYQAF%LICQ\YOA\MK]2>T$XUCMPIO]@AIJ({pdhSkQjdfg,mAIR\5:5?l5Z0.K\RLI(OLDT_T@L_HLX13[)[PDHSD@PCDNO+vikVlTiiij/hFLQQ:66::0Y=!F_WKL+BCIWZSEORGA[44^*V_IKVCESNKCL.qzjfYaWf?95Z0.K\RLI(OLDT_T@L_HLX13[)[PDHSD@PCDNO+vikVg~tRhPotv00>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$t`l_lw{[wYh}}9n7X> I^TJK*ABFVYRBNQFNZ75Y+U^FJUBBRMJLM-p}keXzVookh!F_M0K*PYCG\^856[?/H]UMJ)@MGUXUCMPIOY62X(TQGITECQLEMN,w|hdW{Unhjk U^FLQQ6412_;#DQYIN-DAKYTQGITECU:6\,P]KEXAGUHIAB sxl`[wYblno$YRJ@UU30e>S7'@U]EB!HEO]P]KEXAGQ>:P \YOA\MKYDMEF$t`l_s]f`bc(aME^X1>13`9V4*OX^@E$KH@PSXL@[LH\=?W%_T@L_HL\G@JK'zseoR|Peeef+lBH]]6:2>>4U1-J[SOH'NOES^WAC^KM_00Z&ZSEORGA_BGOH*u~fjUySb{{2g9V4*OX^@E$KH@PSXL@[LH\=?W%_T@L_HL\G@JK'|yn~Rga_o12?P6(AV\BC"IJN^QZJFYNFR?<Q#]VNB]JJZEBDE%J_T@L_G]NQ]563\:$ERXFO.EFJZU^FJUBBV;8]/QZJFYNFVIN@A!NSXL@[WYJ]Q8m7X> I^TJK*ABFVYRBNQFNZ74Y+U^FJUBBRMJLM-PLL@SW[OL?=5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+V_IKVLTAXV<0:W3+LYQAF%LICQ\YOA\MK]2?T$XUCMPIO]@AIJ([PDHS_QBUY10?P6(AV\BC"IJN^QZJFYNFR?<Q#]VNB]JJZEBDE%XSL]VNB]E[WC@;:1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/R]BW\HDW[UYIJ==;T2,MZPNG&MNBR]VNB]JJ^30U'YRBNQFN^AFHI)TWZSEORHPRDE06>S7'@U]EB!HEO]P]KEXAGQ>;P \YOA\MKYDMEF$_R]VNB]Q[WC@;;1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/TQFVZEKCVXNK?k4U1-J[SOH'NOES^WAC^KM_01Z&ZSEORGA_BGOH*STM[UFYU<j;T2,MZPNG&MNBR]VNB]JJ^30U'YRBNQFN^AFHI)R[LXT^HI=f:W3+LYQAF%LICQ\YOA\MK]2?T$XUCMPIO]@AIJ(]VLJ@AGAG3g8Q5)NW_CD#JKA_R[MGZOIS<=V"^WAC^KM[FCKD&_T^D]FNF12?P6(AV\BC"IJN^QZJFYNFR?<Q#]VNB]JJZEBDE%^S^ZNTBOG[k4b3\:$ERXFO.EFJZU^FJUBBV;8]/QZJFYNFVIN@A!Z_R[MGZ@5m2_;#DQYIN-DAKYTQGITECU:7\,P]KEXAGUHIAB U^QZJFYU;<1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/`qzjfYj}qUmSb{{349V4*OX^@E$KH@PSXL@[LH\=>W%_T@L_HL\G@JK'hyrbnQbuy]q[jss:m1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/bnlgncc:m1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/gcohlh`;81^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/gcohlh`Wf>i5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+cb6Wf>i5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+cb5Wf>i5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+cb4Wf>i5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+cb3Wf>i5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+cb2Wf>h5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+hs9Ve~x?m4U1-J[SOH'NOES^WAC^KM_01Z&ZSEORGA_BGOH*tn{`dl?=5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+wotagmTcxz<e:W3+LYQAF%LICQ\YOA\MK]2?T$XUCMPIO]@AIJ({pdhSkQjdfg,MZN5D'_THB[[389V4*OX^@E$KH@PSXL@[LH\=>W%_T@L_HL\G@JK'zseoRhPeeef+PYCG\^;?45Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+vikVlTiiij/T]GKPR6;h1^<"GPVHM,C@HX[PDHSD@T56_-W\HDW@DTOHBC/r{mgZ`Xmmmn#dJ@UU>3:6g<]9%BS[G@/FGM[V_IKVCEW89R.R[MGZOIWJOG@"}vnb]e[`b`m&cOCXZ31?13?P6(AV\BC"IJN^QZJFYNFR?<Q#]VNB]JJZEBDE%xucmPf^mvp62<]9%BS[G@/FGM[V_IKVCEW89R.R[MGZOIWJOG@"}vnb]nq}YaWf?95Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+vikVg~tR|Potv0a>S7'@U]EB!HEO]P]KEXAGQ>;P \YOA\MKYDMEF$t`l_s]f`bc(AVF9D#[PDNWW7<=R8&CTZDA GDL\W\HDW@DP9:S!SXL@[LHXKLFG#~wac^p\aaab'\UOCXZ?389V4*OX^@E$KH@PSXL@[LH\=>W%_T@L_HL\G@JK'zseoR|Peeef+PYCG\^:?l5Z0.K\RLI(OLDT_T@L_HLX12[)[PDHSD@PCDNO+vikVxTiiij/hFLQQ:76:k0Y=!F_WKL+BCIWZSEORGA[45^*V_IKVCESNKCL.qzjfYuWlnli"gKOTV?5;573\:$ERXFO.EFJZU^FJUBBV;8]/QZJFYNFVIN@A!|yoa\vZir|;l0Y=!F_WKL+BCIWZSEORGA[45^*V_IKVCESNKCL.wpawYnfVd8=6[?/H]UMJ)@MGUXUCMPIOY6<X(TQGITECQLEMN,EV_IKVLTAXV<1:W3+LYQAF%LICQ\YOA\MK]20T$XUCMPIO]@AIJ(IZSEOR\PMTZ1b>S7'@U]EB!HEO]P]KEXAGQ>4P \YOA\MKYDMEF$_EGIT^PFC66<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"]VNB]E[HS_;91^<"GPVHM,C@HX[PDHSD@T59_-W\HDW@DTOHBC/R[MGZTXE\R8?6[?/H]UMJ)@MGUXUCMPIOY6<X(TQGITECQLEMN,WZGTQGITJR\JG218Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&YTM^WAC^P\V@A4:2_;#DQYIN-DAKYTQGITECU:8\,P]KEXAGUHIAB S^QZJFYAW[OL??5Z0.K\RLI(OLDT_T@L_HLX1=[)[PDHSD@PCDNO+VYTQGIT^R\JG208Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&_XI_QLLJ]QAB4b3\:$ERXFO.EFJZU^FJUBBV;7]/QZJFYNFVIN@A!ZSDP\IP^5m2_;#DQYIN-DAKYTQGITECU:8\,P]KEXAGUHIAB URGQ[WC@:o1^<"GPVHM,C@HX[PDHSD@T59_-W\HDW@DTOHBC/T]EEIJNFN8n7X> I^TJK*ABFVYRBNQFNZ7;Y+U^FJUBBRMJLM-V[WOTAGM8=6[?/H]UMJ)@MGUXUCMPIOY6<X(TQGITECQLEMN,QZUSI]IFHR`=e:W3+LYQAF%LICQ\YOA\MK]20T$XUCMPIO]@AIJ(]VYRBNQI2d9V4*OX^@E$KH@PSXL@[LH\=1W%_T@L_HL\G@JK'\UXUCMPR278Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&kxucmPmtz\bZir|:?0Y=!F_WKL+BCIWZSEORGA[4:^*V_IKVCESNKCL.cp}keXe|rT~Razt3f8Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&igcnejd3f8Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&lj`agag238Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&lj`agag^mvp7b<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"hk1^mvp7b<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"hk2^mvp7b<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"hk3^mvp7b<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"hk4^mvp7b<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"hk5^mvp7c<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"czx0]lqq4d3\:$ERXFO.EFJZU^FJUBBV;7]/QZJFYNFVIN@A!}irkmc66<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"|fshld[jss;l1^<"GPVHM,C@HX[PDHSD@T59_-W\HDW@DTOHBC/r{mgZ`Xmmmn#DQG2M,V[AIR\:30Y=!F_WKL+BCIWZSEORGA[4:^*V_IKVCESNKCL.qzjfYaWlnli"[PDNWW46?<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"}vnb]e[`b`m&_THB[[12c8Q5)NW_CD#JKA_R[MGZOIS<2V"^WAC^KM[FCKD&yrbnQi_dfda*oCG\^7<3=n;T2,MZPNG&MNBR]VNB]JJ^3?U'YRBNQFN^AFHI)tqgiTjRkkgd-j@JSS4848<6[?/H]UMJ)@MGUXUCMPIOY6<X(TQGITECQLEMN,w|hdWoUdyy=;;T2,MZPNG&MNBR]VNB]JJ^3?U'YRBNQFN^AFHI)tqgiTaxvPf^mvp62<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"}vnb]nq}YuWf?h5Z0.K\RLI(OLDT_T@L_HLX1=[)[PDHSD@PCDNO+vikVxTiiij/H]O6M(RWME^X>74U1-J[SOH'NOES^WAC^KM_0>Z&ZSEORGA_BGOH*u~fjUyShjhe.W\@JSS8:30Y=!F_WKL+BCIWZSEORGA[4:^*V_IKVCESNKCL.qzjfYuWlnli"[PDNWW56g<]9%BS[G@/FGM[V_IKVCEW86R.R[MGZOIWJOG@"}vnb]q[`b`m&cOCXZ30?1b?P6(AV\BC"IJN^QZJFYNFR?3Q#]VNB]JJZEBDE%xucmPr^ggc`)nLF__0<0<0:W3+LYQAF%LICQ\YOA\MK]20T$XUCMPIO]@AIJ({pdhSQ`uu0e?P6(AV\BC"IJN^QZJFYNFR?3Q#]VNB]JJZEBDE%~h|Pio]m74=R8&CTZDA GDL\W\HDW@DP94S!SXL@[LHXKLFG#L]VNB]E[HS_;81^<"GPVHM,C@HX[PDHSD@T58_-W\HDW@DTOHBC/@QZJFYUWD_S>k5Z0.K\RLI(OLDT_T@L_HLX1<[)[PDHSD@PCDNO+VNNN]UYIJ=?;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)TQGITJRCZX228Q5)NW_CD#JKA_R[MGZOIS<3V"^WAC^KM[FCKD&YRBNQ]_LW[76=R8&CTZDA GDL\W\HDW@DP94S!SXL@[LHXKLFG#^QNSXL@[CYUMN987X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-P[DU^FJUYS_KH339V4*OX^@E$KH@PSXL@[LH\=0W%_T@L_HL\G@JK'ZUXUCMPF^PFC64<]9%BS[G@/FGM[V_IKVCEW87R.R[MGZOIWJOG@"]PSXL@[WYUMN997X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-VW@TXKEAT^HI=e:W3+LYQAF%LICQ\YOA\MK]21T$XUCMPIO]@AIJ(]ZOYS@[W2d9V4*OX^@E$KH@PSXL@[LH\=0W%_T@L_HL\G@JK'\YN^R\JG3d8Q5)NW_CD#JKA_R[MGZOIS<3V"^WAC^KM[FCKD&_TJLBCIOE1a>S7'@U]EB!HEO]P]KEXAGQ>5P \YOA\MKYDMEF$YR\FSHLD74=R8&CTZDA GDL\W\HDW@DP94S!SXL@[LHXKLFG#XQ\T@V@IAYi:l1^<"GPVHM,C@HX[PDHSD@T58_-W\HDW@DTOHBC/T]P]KEXN;o0Y=!F_WKL+BCIWZSEORGA[4;^*V_IKVCESNKCL.W\W\HDW[9>7X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-bw|hdWdsSkQ`uu16?P6(AV\BC"IJN^QZJFYNFR?2Q#]VNB]JJZEBDE%jt`l_lw{[wYh}}8o7X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-`hjelmm8o7X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-eeijnfn9:7X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-eeijnfnUdyy<k;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)al8Udyy<k;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)al;Udyy<k;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)al:Udyy<k;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)al=Udyy<k;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)al<Udyy<j;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)j}q;Tcxz=c:W3+LYQAF%LICQ\YOA\MK]21T$XUCMPIO]@AIJ(z`ybbj=?;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)uazcekRazt2g8Q5)NW_CD#JKA_R[MGZOIS<3V"^WAC^KM[FCKD&yrbnQi_dfda*OX@;F%YRJ@UU1:?P6(AV\BC"IJN^QZJFYNFR?2Q#]VNB]JJZEBDE%xucmPf^ggc`)RWME^X==6;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)tqgiTjRkkgd-V[AIR\89j7X> I^TJK*ABFVYRBNQFNZ7:Y+U^FJUBBRMJLM-p}keXnVookh!fDNWW8584i2_;#DQYIN-DAKYTQGITECU:9\,P]KEXAGUHIAB sxl`[cYblno$eIAZT=3=75=R8&CTZDA GDL\W\HDW@DP94S!SXL@[LHXKLFG#~wac^d\kpr4<2_;#DQYIN-DAKYTQGITECU:9\,P]KEXAGUHIAB sxl`[hsWoUdyy=;;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)tqgiTaxvPr^mvp6c<]9%BS[G@/FGM[V_IKVCEW87R.R[MGZOIWJOG@"}vnb]q[`b`m&CT@?F!U^FLQQ5>3\:$ERXFO.EFJZU^FJUBBV;6]/QZJFYNFVIN@A!|yoa\vZccol%^SIAZT11:?P6(AV\BC"IJN^QZJFYNFR?2Q#]VNB]JJZEBDE%xucmPr^ggc`)RWME^X<=n;T2,MZPNG&MNBR]VNB]JJ^3>U'YRBNQFN^AFHI)tqgiT~Rkkgd-j@JSS4948m6[?/H]UMJ)@MGUXUCMPIOY6=X(TQGITECQLEMN,w|hdW{Unhjk iEMVP979;91^<"GPVHM,C@HX[PDHSD@T58_-W\HDW@DTOHBC/r{mgZtXg|~9j6[?/H]UMJ)@MGUXUCMPIOY6=X(TQGITECQLEMN,qvcuW`dTb>?4U1-J[SOH'NOES^WAC^KM_36Z&ZSEORGA_BGOH*GTQGITJRCZX238Q5)NW_CD#JKA_R[MGZOIS?:V"^WAC^KM[FCKD&KXUCMPR^OV\7`<]9%BS[G@/FGM[V_IKVCEW;>R.R[MGZOIWJOG@"]GIGV\V@A482_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB SXL@[CYJ]Q9;7X> I^TJK*ABFVYRBNQFNZ43Y+U^FJUBBRMJLM-P]KEXZVG^T>=4U1-J[SOH'NOES^WAC^KM_36Z&ZSEORGA_BGOH*UXIZSEORHPRDE07>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$_RO\YOA\VZTBO:80Y=!F_WKL+BCIWZSEORGA[72^*V_IKVCESNKCL.Q\W\HDWOUYIJ==;T2,MZPNG&MNBR]VNB]JJ^07U'YRBNQFN^AFHI)TWZSEOR\PRDE06>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$Y^K]_BNH[WC@:l1^<"GPVHM,C@HX[PDHSD@T61_-W\HDW@DTOHBC/TQFVZKRP;o0Y=!F_WKL+BCIWZSEORGA[72^*V_IKVCESNKCL.WPAWYUMN8m7X> I^TJK*ABFVYRBNQFNZ43Y+U^FJUBBRMJLM-V[CGKD@DL>h5Z0.K\RLI(OLDT_T@L_HLX25[)[PDHSD@PCDNO+PYUAZCEK>?4U1-J[SOH'NOES^WAC^KM_36Z&ZSEORGA_BGOH*SX[]K_O@JPn3g8Q5)NW_CD#JKA_R[MGZOIS?:V"^WAC^KM[FCKD&_T_T@L_G0f?P6(AV\BC"IJN^QZJFYNFR<;Q#]VNB]JJZEBDE%^S^WAC^P01>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$m~wac^ov|Z`Xg|~896[?/H]UMJ)@MGUXUCMPIOY54X(TQGITECQLEMN,evikVg~tR|Potv1`>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$oaalkdf1`>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$jlbcioe05>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$jlbcioe\kpr5l2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB fe3\kpr5l2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB fe0\kpr5l2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB fe1\kpr5l2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB fe6\kpr5l2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB fe7\kpr5m2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB mtz2[jss:j1^<"GPVHM,C@HX[PDHSD@T61_-W\HDW@DTOHBC/skpmka482_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB rhqjjbYh}}9n7X> I^TJK*ABFVYRBNQFNZ43Y+U^FJUBBRMJLM-p}keXnVookh!F_I0O*PYCG\^856[?/H]UMJ)@MGUXUCMPIOY54X(TQGITECQLEMN,w|hdWoUnhjk U^FLQQ6412_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB sxl`[cYblno$YRJ@UU30e>S7'@U]EB!HEO]P]KEXAGQ=<P \YOA\MKYDMEF$t`l_g]f`bc(aME^X1>13`9V4*OX^@E$KH@PSXL@[LH\>9W%_T@L_HL\G@JK'zseoRhPeeef+lBH]]6:2>>4U1-J[SOH'NOES^WAC^KM_36Z&ZSEORGA_BGOH*u~fjUmSb{{359V4*OX^@E$KH@PSXL@[LH\>9W%_T@L_HL\G@JK'zseoRczx^d\kpr4<2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB sxl`[hsW{Udyy=j;T2,MZPNG&MNBR]VNB]JJ^07U'YRBNQFN^AFHI)tqgiT~Rkkgd-J[I4O&\UOCXZ<9:W3+LYQAF%LICQ\YOA\MK]18T$XUCMPIO]@AIJ({pdhSQjdfg,QZBH]]:856[?/H]UMJ)@MGUXUCMPIOY54X(TQGITECQLEMN,w|hdW{Unhjk U^FLQQ74i2_;#DQYIN-DAKYTQGITECU90\,P]KEXAGUHIAB sxl`[wYblno$eIAZT=2=7d=R8&CTZDA GDL\W\HDW@DP:=S!SXL@[LHXKLFG#~wac^p\aaab'`NDYY2>>228Q5)NW_CD#JKA_R[MGZOIS?:V"^WAC^KM[FCKD&yrbnQ}_nww6c=R8&CTZDA GDL\W\HDW@DP:=S!SXL@[LHXKLFG#x}jr^km[k563\:$ERXFO.EFJZU^FJUBBV8>]/QZJFYNFVIN@A!NSXL@[CYJ]Q9:7X> I^TJK*ABFVYRBNQFNZ42Y+U^FJUBBRMJLM-BW\HDW[UFYU<i;T2,MZPNG&MNBR]VNB]JJ^06U'YRBNQFN^AFHI)T@@L_S_KH319V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'ZSEORHPMTZ04>S7'@U]EB!HEO]P]KEXAGQ==P \YOA\MKYDMEF$_T@L_S]NQ]543\:$ERXFO.EFJZU^FJUBBV8>]/QZJFYNFVIN@A!\_@QZJFYAW[OL?>5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+VYF[PDHS_Q]EF11?P6(AV\BC"IJN^QZJFYNFR<:Q#]VNB]JJZEBDE%XS^WAC^D\V@A4:2_;#DQYIN-DAKYTQGITECU91\,P]KEXAGUHIAB S^QZJFYUW[OL??5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+PUBZVIGGR\JG3g8Q5)NW_CD#JKA_R[MGZOIS?;V"^WAC^KM[FCKD&_XI_QBUY0f?P6(AV\BC"IJN^QZJFYNFR<:Q#]VNB]JJZEBDE%^_H\PRDE1b>S7'@U]EB!HEO]P]KEXAGQ==P \YOA\MKYDMEF$YRHNLMKMC7c<]9%BS[G@/FGM[V_IKVCEW;?R.R[MGZOIWJOG@"[PRHQJJB563\:$ERXFO.EFJZU^FJUBBV8>]/QZJFYNFVIN@A!Z_RVBPFKCWg8n7X> I^TJK*ABFVYRBNQFNZ42Y+U^FJUBBRMJLM-V[V_IKVL9i6[?/H]UMJ)@MGUXUCMPIOY55X(TQGITECQLEMN,QZU^FJUY?85Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+du~fjUfyuQi_nww70=R8&CTZDA GDL\W\HDW@DP:<S!SXL@[LHXKLFG#l}vnb]nq}YuWf>i5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+fjhkboo>i5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+cgkd`dl?<5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+cgkd`dlSb{{2e9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'on:Sb{{2e9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'on9Sb{{2e9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'on8Sb{{2e9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'on?Sb{{2e9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'on>Sb{{2d9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'ds=Razt3a8Q5)NW_CD#JKA_R[MGZOIS?;V"^WAC^KM[FCKD&xbd`h319V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'{cxeciPotv0a>S7'@U]EB!HEO]P]KEXAGQ==P \YOA\MKYDMEF$t`l_g]f`bc(AVB9@#[PDNWW7<=R8&CTZDA GDL\W\HDW@DP:<S!SXL@[LHXKLFG#~wac^d\aaab'\UOCXZ?389V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'zseoRhPeeef+PYCG\^:?l5Z0.K\RLI(OLDT_T@L_HLX24[)[PDHSD@PCDNO+vikVlTiiij/hFLQQ:76:k0Y=!F_WKL+BCIWZSEORGA[73^*V_IKVCESNKCL.qzjfYaWlnli"gKOTV?5;573\:$ERXFO.EFJZU^FJUBBV8>]/QZJFYNFVIN@A!|yoa\bZir|:>0Y=!F_WKL+BCIWZSEORGA[73^*V_IKVCESNKCL.qzjfYj}qUmSb{{359V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'zseoRczx^p\kpr4m2_;#DQYIN-DAKYTQGITECU91\,P]KEXAGUHIAB sxl`[wYblno$ERB=H/W\@JSS;01^<"GPVHM,C@HX[PDHSD@T60_-W\HDW@DTOHBC/r{mgZtXmmmn#XQKOTV37<=R8&CTZDA GDL\W\HDW@DP:<S!SXL@[LHXKLFG#~wac^p\aaab'\UOCXZ>3`9V4*OX^@E$KH@PSXL@[LH\>8W%_T@L_HL\G@JK'zseoR|Peeef+lBH]]6;2>o4U1-J[SOH'NOES^WAC^KM_37Z&ZSEORGA_BGOH*u~fjUyShjhe.kGKPR;979;7X> I^TJK*ABFVYRBNQFNZ42Y+U^FJUBBRMJLM-p}keXzVe~x?h4U1-J[SOH'NOES^WAC^KM_37Z&ZSEORGA_BGOH*stm{UbbR`<1:W3+LYQAF%LICQ\YOA\MK]1:T$XUCMPIO]@AIJ(IZSEORHPMTZ05>S7'@U]EB!HEO]P]KEXAGQ=>P \YOA\MKYDMEF$M^WAC^P\IP^5n2_;#DQYIN-DAKYTQGITECU92\,P]KEXAGUHIAB SIKEPZTBO::0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.QZJFYAWD_S?=5Z0.K\RLI(OLDT_T@L_HLX27[)[PDHSD@PCDNO+V_IKVXTAXV<3:W3+LYQAF%LICQ\YOA\MK]1:T$XUCMPIO]@AIJ([VKXUCMPF^PFC65<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"]PAR[MGZTXZLM8>6[?/H]UMJ)@MGUXUCMPIOY56X(TQGITECQLEMN,WZU^FJUMS_KH339V4*OX^@E$KH@PSXL@[LH\>;W%_T@L_HL\G@JK'ZUXUCMPR^PFC64<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"[\ES]@HNYUMN8n7X> I^TJK*ABFVYRBNQFNZ41Y+U^FJUBBRMJLM-VW@TXE\R9i6[?/H]UMJ)@MGUXUCMPIOY56X(TQGITECQLEMN,QVCUW[OL>k5Z0.K\RLI(OLDT_T@L_HLX27[)[PDHSD@PCDNO+PYAIEFBBJ<j;T2,MZPNG&MNBR]VNB]JJ^05U'YRBNQFN^AFHI)RW[CXECI<1:W3+LYQAF%LICQ\YOA\MK]1:T$XUCMPIO]@AIJ(]VY_MYMBD^l1a>S7'@U]EB!HEO]P]KEXAGQ=>P \YOA\MKYDMEF$YR]VNB]E6`=R8&CTZDA GDL\W\HDW@DP:?S!SXL@[LHXKLFG#XQ\YOA\V63<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"o|yoa\ip~XnVe~x>;4U1-J[SOH'NOES^WAC^KM_34Z&ZSEORGA_BGOH*gtqgiTaxvPr^mvp7b<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"mcobif`7b<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"hnlmkmc67<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"hnlmkmcZir|;n0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.dg5Zir|;n0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.dg6Zir|;n0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.dg7Zir|;n0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.dg0Zir|;n0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.dg1Zir|;o0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.ov|4Yh}}8h7X> I^TJK*ABFVYRBNQFNZ41Y+U^FJUBBRMJLM-qmvoio::0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.pjwlh`Wf?h5Z0.K\RLI(OLDT_T@L_HLX27[)[PDHSD@PCDNO+vikVlTiiij/H]K6I(RWME^X>74U1-J[SOH'NOES^WAC^KM_34Z&ZSEORGA_BGOH*u~fjUmShjhe.W\@JSS8:30Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.qzjfYaWlnli"[PDNWW56g<]9%BS[G@/FGM[V_IKVCEW;<R.R[MGZOIWJOG@"}vnb]e[`b`m&cOCXZ30?1b?P6(AV\BC"IJN^QZJFYNFR<9Q#]VNB]JJZEBDE%xucmPf^ggc`)nLF__0<0<0:W3+LYQAF%LICQ\YOA\MK]1:T$XUCMPIO]@AIJ({pdhSkQ`uu17?P6(AV\BC"IJN^QZJFYNFR<9Q#]VNB]JJZEBDE%xucmPmtz\bZir|:>0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.qzjfYj}qUySb{{3d9V4*OX^@E$KH@PSXL@[LH\>;W%_T@L_HL\G@JK'zseoR|Peeef+LYK:A$^SIAZT2;8Q5)NW_CD#JKA_R[MGZOIS?8V"^WAC^KM[FCKD&yrbnQ}_dfda*SXLF__<>74U1-J[SOH'NOES^WAC^KM_34Z&ZSEORGA_BGOH*u~fjUyShjhe.W\@JSS9:k0Y=!F_WKL+BCIWZSEORGA[70^*V_IKVCESNKCL.qzjfYuWlnli"gKOTV?4;5f3\:$ERXFO.EFJZU^FJUBBV8=]/QZJFYNFVIN@A!|yoa\vZccol%bHB[[<0<04>S7'@U]EB!HEO]P]KEXAGQ=>P \YOA\MKYDMEF$t`l_s]lqq4a3\:$ERXFO.EFJZU^FJUBBV8=]/QZJFYNFVIN@A!zsdp\mkYi;81^<"GPVHM,C@HX[PDHSD@T62_-W\HDW@DTOHBC/@QZJFYAWD_S?<5Z0.K\RLI(OLDT_T@L_HLX26[)[PDHSD@PCDNO+DU^FJUYS@[W2g9V4*OX^@E$KH@PSXL@[LH\>:W%_T@L_HL\G@JK'ZBBJYQ]EF13?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%XUCMPF^OV\66<]9%BS[G@/FGM[V_IKVCEW;=R.R[MGZOIWJOG@"]VNB]Q[HS_;:1^<"GPVHM,C@HX[PDHSD@T62_-W\HDW@DTOHBC/R]BW\HDWOUYIJ=<;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)TWHYRBNQ]_SGD77=R8&CTZDA GDL\W\HDW@DP:>S!SXL@[LHXKLFG#^Q\YOA\BZTBO:80Y=!F_WKL+BCIWZSEORGA[71^*V_IKVCESNKCL.Q\W\HDW[UYIJ==;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)R[LXTOAEPRDE1a>S7'@U]EB!HEO]P]KEXAGQ=?P \YOA\MKYDMEF$Y^K]_LW[6`=R8&CTZDA GDL\W\HDW@DP:>S!SXL@[LHXKLFG#X]JR^PFC7`<]9%BS[G@/FGM[V_IKVCEW;=R.R[MGZOIWJOG@"[PF@NOMKA5m2_;#DQYIN-DAKYTQGITECU93\,P]KEXAGUHIAB U^PJWLH@;81^<"GPVHM,C@HX[PDHSD@T62_-W\HDW@DTOHBC/T]PPDRDEMUe>h5Z0.K\RLI(OLDT_T@L_HLX26[)[PDHSD@PCDNO+PYTQGITJ?k4U1-J[SOH'NOES^WAC^KM_35Z&ZSEORGA_BGOH*SX[PDHS_=:;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)f{pdhS`{w_g]lqq523\:$ERXFO.EFJZU^FJUBBV8<]/QZJFYNFVIN@A!nsxl`[hsW{Udyy<k;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)ddfi`ii<k;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)aiefbbj=>;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)aiefbbjQ`uu0g?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%mh<Q`uu0g?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%mh?Q`uu0g?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%mh>Q`uu0g?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%mh9Q`uu0g?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%mh8Q`uu0f?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%fyu?Potv1g>S7'@U]EB!HEO]P]KEXAGQ=?P \YOA\MKYDMEF$~d}fnf13?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%ye~gag^mvp6c<]9%BS[G@/FGM[V_IKVCEW;=R.R[MGZOIWJOG@"}vnb]e[`b`m&CTD?B!U^FLQQ5>3\:$ERXFO.EFJZU^FJUBBV8<]/QZJFYNFVIN@A!|yoa\bZccol%^SIAZT11:?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%xucmPf^ggc`)RWME^X<=n;T2,MZPNG&MNBR]VNB]JJ^04U'YRBNQFN^AFHI)tqgiTjRkkgd-j@JSS4948m6[?/H]UMJ)@MGUXUCMPIOY57X(TQGITECQLEMN,w|hdWoUnhjk iEMVP979;91^<"GPVHM,C@HX[PDHSD@T62_-W\HDW@DTOHBC/r{mgZ`Xg|~886[?/H]UMJ)@MGUXUCMPIOY57X(TQGITECQLEMN,w|hdWdsSkQ`uu17?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%xucmPmtz\vZir|:o0Y=!F_WKL+BCIWZSEORGA[71^*V_IKVCESNKCL.qzjfYuWlnli"GPL3J-QZBH]]927X> I^TJK*ABFVYRBNQFNZ40Y+U^FJUBBRMJLM-p}keXzVookh!Z_EMVP55>3\:$ERXFO.EFJZU^FJUBBV8<]/QZJFYNFVIN@A!|yoa\vZccol%^SIAZT01b?P6(AV\BC"IJN^QZJFYNFR<8Q#]VNB]JJZEBDE%xucmPr^ggc`)nLF__0=0<a:W3+LYQAF%LICQ\YOA\MK]1;T$XUCMPIO]@AIJ({pdhSQjdfg,mAIR\5;5?=5Z0.K\RLI(OLDT_T@L_HLX26[)[PDHSD@PCDNO+vikVxTcxz=f:W3+LYQAF%LICQ\YOA\MK]1;T$XUCMPIO]@AIJ(}zoySd`Pn248Q5)NW_CD#JKA_R[MGZIR\R99Q#]VNB]LQQYDMEF$ER]]L^V1*PYTZE8m7X> I^TJK*ABFVYRBNQ@UUY06X(TQGITCXZPCDNO+ISSWF__?;5Z0.K\RLI(OLDT_T@L_NWW_64Z&ZSEORAZT^AFHI)T@@L_SB[[_ugnt66<]9%BS[G@/FGM[V_IKVE^XV==]/QZJFYH]]UHIAB URGQ[WC@;91^<"GPVHM,C@HX[PDHSB[[[20^*V_IKVE^XRMJLM-lqqYsmdz8:6[?/H]UMJ)@MGUXUCMPOTVX76[)[PDHSB[[_BGOH*OX[[FTX? Z_RPO6c=R8&CTZDA GDL\W\HDWF__W>=R.R[MGZIR\VIN@A!CUU]LQQ513\:$ERXFO.EFJZU^FJUDYYU<3\,P]KEXG\^TOHBC/RJJBQYH]]Ui`~<0:W3+LYQAF%LICQ\YOA\KPR\;:W%_T@L_NWW[FCKD&_XI_Q]EF13?P6(AV\BC"IJN^QZJFYH]]Q8?P \YOA\KPRXKLFG#b{{_ugnt60<]9%BS[G@/FGM[V_IKVE^XV=;]/QZJFYH]]UHIAB I^QQHZR5&\UX^A<i;T2,MZPNG&MNBR]VNB]LQQ]4<T$XUCMPOTV\G@JK'E__SB[[379V4*OX^@E$KH@PSXL@[JSSS:>V"^WAC^MVPZEBDE%XDDH[_NWW[qcjx::0Y=!F_WKL+BCIWZSEORAZTZ17Y+U^FJUDYYQLEMN,QVCUW[OL?=5Z0.K\RLI(OLDT_T@L_NWW_62Z&ZSEORAZT^AFHI)h}}Ui`~<6:W3+LYQAF%LICQ\YOA\KPR\;<W%_T@L_NWW[FCKD&CT__BPT3,V[VTK:o1^<"GPVHM,C@HX[PDHSB[[[27^*V_IKVE^XRMJLM-OQQYH]]9=7X> I^TJK*ABFVYRBNQ@UUY01X(TQGITCXZPCDNO+VNNN]UDYYQ{elr04>S7'@U]EB!HEO]P]KEXG\^P?8S!SXL@[JSSWJOG@"[\ES]QAB573\:$ERXFO.EFJZU^FJUDYYU<5\,P]KEXG\^TOHBC/nww[qcjx:<0Y=!F_WKL+BCIWZSEORAZTZ15Y+U^FJUDYYQLEMN,MZUUDV^9"XQ\RM0e?P6(AV\BC"IJN^QZJFYH]]Q8:P \YOA\KPRXKLFG#A[[_NWW73=R8&CTZDA GDL\W\HDWF__W>8R.R[MGZIR\VIN@A!\HHDW[JSSW}of|>>4U1-J[SOH'NOES^WAC^MVP^51U'YRBNQ@UU]@AIJ(]ZOYS_KH319V4*OX^@E$KH@PSXL@[JSSS:<V"^WAC^MVPZEBDE%dyyQ{elr02>S7'@U]EB!HEO]P]KEXG\^P?:S!SXL@[JSSWJOG@"GPSSN\P7(RWZXG>k5Z0.K\RLI(OLDT_T@L_NWW_61Z&ZSEORAZT^AFHI)K]]UDYY=9;T2,MZPNG&MNBR]VNB]LQQ]4?T$XUCMPOTV\G@JK'ZBBJYQ@UU]wahv482_;#DQYIN-DAKYTQGITCXZT36_-W\HDWF__SNKCL.WPAWYUMN9;7X> I^TJK*ABFVYRBNQ@UUY03X(TQGITCXZPCDNO+jssW}of|>84U1-J[SOH'NOES^WAC^MVP^5?U'YRBNQ@UU]@AIJ(AVYY@RZ=.T]PVI4a3\:$ERXFO.EFJZU^FJUDYYU<8\,P]KEXG\^TOHBC/MWW[JSS;?1^<"GPVHM,C@HX[PDHSB[[[2:^*V_IKVE^XRMJLM-PLL@SWF__Sykbp228Q5)NW_CD#JKA_R[MGZIR\R93Q#]VNB]LQQYDMEF$Y^K]_SGD75=R8&CTZDA GDL\W\HDWF__W>6R.R[MGZIR\VIN@A!`uu]wahv4>2_;#DQYIN-DAKYTQGITCXZT38_-W\HDWF__SNKCL.K\WWJX\;$^S^\C2g9V4*OX^@E$KH@PSXL@[JSSS:3V"^WAC^MVPZEBDE%GYYQ@UU15?P6(AV\BC"IJN^QZJFYH]]Q85P \YOA\KPRXKLFG#^FFFU]LQQYsmdz8<6[?/H]UMJ)@MGUXUCMPOTVX7<[)[PDHSB[[_BGOH*STM[UYIJ=?;T2,MZPNG&MNBR]VNB]LQQ]41T$XUCMPOTV\G@JK'fSykbp248Q5)NW_CD#JKA_R[MGZIR\R>;Q#]VNB]LQQYDMEF$ER]]L^V1*PYTZE8m7X> I^TJK*ABFVYRBNQ@UUY74X(TQGITCXZPCDNO+ISSWF__?;5Z0.K\RLI(OLDT_T@L_NWW_16Z&ZSEORAZT^AFHI)T@@L_SB[[_ugnt66<]9%BS[G@/FGM[V_IKVE^XV:?]/QZJFYH]]UHIAB URGQ[WC@;91^<"GPVHM,C@HX[PDHSB[[[52^*V_IKVE^XRMJLM-lqqYsmdz8:6[?/H]UMJ)@MGUXUCMPOTVX04[)[PDHSB[[_BGOH*OX[[FTX? Z_RPO6c=R8&CTZDA GDL\W\HDWF__W9?R.R[MGZIR\VIN@A!CUU]LQQ513\:$ERXFO.EFJZU^FJUDYYU;1\,P]KEXG\^TOHBC/RJJBQYH]]Ui`~<0:W3+LYQAF%LICQ\YOA\KPR\<8W%_T@L_NWW[FCKD&_XI_Q]EF13?P6(AV\BC"IJN^QZJFYH]]Q?=P \YOA\KPRXKLFG#b{{_ugnt60<]9%BS[G@/FGM[V_IKVE^XV:=]/QZJFYH]]UHIAB I^QQHZR5&\UX^A<i;T2,MZPNG&MNBR]VNB]LQQ]3:T$XUCMPOTV\G@JK'E__SB[[379V4*OX^@E$KH@PSXL@[JSSS=8V"^WAC^MVPZEBDE%XDDH[_NWW[qcjx::0Y=!F_WKL+BCIWZSEORAZTZ61Y+U^FJUDYYQLEMN,QVCUW[OL?=5Z0.K\RLI(OLDT_T@L_NWW_14Z&ZSEORAZT^AFHI)h}}Ui`~<6:W3+LYQAF%LICQ\YOA\KPR\<:W%_T@L_NWW[FCKD&CT__BPT3,V[VTK:o1^<"GPVHM,C@HX[PDHSB[[[51^*V_IKVE^XRMJLM-OQQYH]]9=7X> I^TJK*ABFVYRBNQ@UUY77X(TQGITCXZPCDNO+VNNN]UDYYQ{elr04>S7'@U]EB!HEO]P]KEXG\^P8>S!SXL@[JSSWJOG@"[\ES]QAB573\:$ERXFO.EFJZU^FJUDYYU;3\,P]KEXG\^TOHBC/nww[qcjx:<0Y=!F_WKL+BCIWZSEORAZTZ67Y+U^FJUDYYQLEMN,MZUUDV^9"XQ\RM0e?P6(AV\BC"IJN^QZJFYH]]Q?8P \YOA\KPRXKLFG#A[[_NWW73=R8&CTZDA GDL\W\HDWF__W9:R.R[MGZIR\VIN@A!\HHDW[JSSW}of|>>4U1-J[SOH'NOES^WAC^MVP^23U'YRBNQ@UU]@AIJ(]ZOYS_KH319V4*OX^@E$KH@PSXL@[JSSS=>V"^WAC^MVPZEBDE%dyyQ{elr02>S7'@U]EB!HEO]P]KEXG\^P88S!SXL@[JSSWJOG@"GPSSN\P7(RWZXG>k5Z0.K\RLI(OLDT_T@L_NWW_13Z&ZSEORAZT^AFHI)K]]UDYY=9;T2,MZPNG&MNBR]VNB]LQQ]3=T$XUCMPOTV\G@JK'ZBBJYQ@UU]wahv482_;#DQYIN-DAKYTQGITCXZT44_-W\HDWF__SNKCL.WPAWYUMN9;7X> I^TJK*ABFVYRBNQ@UUY71X(TQGITCXZPCDNO+jssW}of|>84U1-J[SOH'NOES^WAC^MVP^21U'YRBNQ@UU]@AIJ(AVYY@RZ=.T]PVI4a3\:$ERXFO.EFJZU^FJUDYYU;6\,P]KEXG\^TOHBC/MWW[JSS;?1^<"GPVHM,C@HX[PDHSB[[[54^*V_IKVE^XRMJLM-PLL@SWF__Sykbp228Q5)NW_CD#JKA_R[MGZIR\R>=Q#]VNB]LQQYDMEF$Y^K]_SGD75=R8&CTZDA GDL\W\HDWF__W98R.R[MGZIR\VIN@A!`uu]wahv4>2_;#DQYIN-DAKYTQGITCXZT46_-W\HDWF__SNKCL.K\WWJX\;$^S^\C2g9V4*OX^@E$KH@PSXL@[JSSS==V"^WAC^MVPZEBDE%GYYQ@UU15?P6(AV\BC"IJN^QZJFYH]]Q?;P \YOA\KPRXKLFG#^FFFU]LQQYsmdz8<6[?/H]UMJ)@MGUXUCMPOTVX02[)[PDHSB[[_BGOH*STM[UYIJ=?;T2,MZPNG&MNBR]VNB]LQQ]3?T$XUCMPOTV\G@JK'fSykbp248Q5)NW_CD#JKA_R[MGZIR\R>3Q#]VNB]LQQYDMEF$ER]]L^V1*PYTZE8m7X> I^TJK*ABFVYRBNQ@UUY7<X(TQGITCXZPCDNO+ISSWF__?;5Z0.K\RLI(OLDT_T@L_NWW_1>Z&ZSEORAZT^AFHI)T@@L_SB[[_ugnt66<]9%BS[G@/FGM[V_IKVE^XV:7]/QZJFYH]]UHIAB URGQ[WC@;91^<"GPVHM,C@HX[PDHSB[[[5:^*V_IKVE^XRMJLM-lqqYsmdz8:6[?/H]UMJ)@MGUXUCMPOTVX0<[)[PDHSB[[_BGOH*OX[[FTX? Z_RPO6c=R8&CTZDA GDL\W\HDWF__W97R.R[MGZIR\VIN@A!CUU]LQQ513\:$ERXFO.EFJZU^FJUDYYU;9\,P]KEXG\^TOHBC/RJJBQYH]]Ui`~<0:W3+LYQAF%LICQ\YOA\KPR\<0W%_T@L_NWW[FCKD&_XI_Q]EF13?P6(AV\BC"IJN^QZJFYH]]Q?5P \YOA\KPRXKLFG#b{{_ugnt60<]9%BS[G@/FGM[V_IKVE^XV;?]/QZJFYH]]UHIAB I^QQHZR5&\UX^A<i;T2,MZPNG&MNBR]VNB]LQQ]28T$XUCMPOTV\G@JK'E__SB[[379V4*OX^@E$KH@PSXL@[JSSS<:V"^WAC^MVPZEBDE%XDDH[_NWW[qcjx::0Y=!F_WKL+BCIWZSEORAZTZ73Y+U^FJUDYYQLEMN,QVCUW[OL?=5Z0.K\RLI(OLDT_T@L_NWW_06Z&ZSEORAZT^AFHI)h}}Ui`~<6:W3+LYQAF%LICQ\YOA\KPR\=8W%_T@L_NWW[FCKD&CT__BPT3,V[VTK:o1^<"GPVHM,C@HX[PDHSB[[[43^*V_IKVE^XRMJLM-OQQYH]]9=7X> I^TJK*ABFVYRBNQ@UUY65X(TQGITCXZPCDNO+VNNN]UDYYQ{elr04>S7'@U]EB!HEO]P]KEXG\^P9<S!SXL@[JSSWJOG@"[\ES]QAB573\:$ERXFO.EFJZU^FJUDYYU:1\,P]KEXG\^TOHBC/nww[qcjx:<0Y=!F_WKL+BCIWZSEORAZTZ71Y+U^FJUDYYQLEMN,MZUUDV^9"XQ\RM0e?P6(AV\BC"IJN^QZJFYH]]Q>>P \YOA\KPRXKLFG#A[[_NWW73=R8&CTZDA GDL\W\HDWF__W8<R.R[MGZIR\VIN@A!\HHDW[JSSW}of|>>4U1-J[SOH'NOES^WAC^MVP^35U'YRBNQ@UU]@AIJ(]ZOYS_KH319V4*OX^@E$KH@PSXL@[JSSS<8V"^WAC^MVPZEBDE%dyyQ{elr02>S7'@U]EB!HEO]P]KEXG\^P9>S!SXL@[JSSWJOG@"GPSSN\P7(RWZXG>k5Z0.K\RLI(OLDT_T@L_NWW_05Z&ZSEORAZT^AFHI)K]]UDYY=9;T2,MZPNG&MNBR]VNB]LQQ]2;T$XUCMPOTV\G@JK'ZBBJYQ@UU]wahv482_;#DQYIN-DAKYTQGITCXZT52_-W\HDWF__SNKCL.WPAWYUMN9;7X> I^TJK*ABFVYRBNQ@UUY67X(TQGITCXZPCDNO+jssW}of|>84U1-J[SOH'NOES^WAC^MVP^33U'YRBNQ@UU]@AIJ(AVYY@RZ=.T]PVI4a3\:$ERXFO.EFJZU^FJUDYYU:4\,P]KEXG\^TOHBC/MWW[JSS;?1^<"GPVHM,C@HX[PDHSB[[[46^*V_IKVE^XRMJLM-PLL@SWF__Sykbp228Q5)NW_CD#JKA_R[MGZIR\R??Q#]VNB]LQQYDMEF$Y^K]_SGD75=R8&CTZDA GDL\W\HDWF__W8:R.R[MGZIR\VIN@A!`uu]wahv4>2_;#DQYIN-DAKYTQGITCXZT54_-W\HDWF__SNKCL.K\WWJX\;$^S^\C2g9V4*OX^@E$KH@PSXL@[JSSS<?V"^WAC^MVPZEBDE%GYYQ@UU15?P6(AV\BC"IJN^QZJFYH]]Q>9P \YOA\KPRXKLFG#^FFFU]LQQYsmdz8<6[?/H]UMJ)@MGUXUCMPOTVX10[)[PDHSB[[_BGOH*STM[UYIJ=?;T2,MZPNG&MNBR]VNB]LQQ]2=T$XUCMPOTV\G@JK'fSykbp248Q5)NW_CD#JKA_R[MGZIR\R?=Q#]VNB]LQQYDMEF$ER]]L^V1*PYTZE8m7X> I^TJK*ABFVYRBNQ@UUY62X(TQGITCXZPCDNO+ISSWF__?;5Z0.K\RLI(OLDT_T@L_NWW_00Z&ZSEORAZT^AFHI)T@@L_SB[[_ugnt66<]9%BS[G@/FGM[V_IKVE^XV;9]/QZJFYH]]UHIAB URGQ[WC@;91^<"GPVHM,C@HX[PDHSB[[[44^*V_IKVE^XRMJLM-lqqYsmdz8:6[?/H]UMJ)@MGUXUCMPOTVX12[)[PDHSB[[_BGOH*OX[[FTX? Z_RPO6c=R8&CTZDA GDL\W\HDWF__W89R.R[MGZIR\VIN@A!CUU]LQQ513\:$ERXFO.EFJZU^FJUDYYU:7\,P]KEXG\^TOHBC/RJJBQYH]]Ui`~<0:W3+LYQAF%LICQ\YOA\KPR\=>W%_T@L_NWW[FCKD&_XI_Q]EF13?P6(AV\BC"IJN^QZJFYH]]Q>;P \YOA\KPRXKLFG#b{{_ugnt60<]9%BS[G@/FGM[V_IKVE^XV;7]/QZJFYH]]UHIAB I^QQHZR5&\UX^A<i;T2,MZPNG&MNBR]VNB]LQQ]20T$XUCMPOTV\G@JK'E__SB[[379V4*OX^@E$KH@PSXL@[JSSS<2V"^WAC^MVPZEBDE%XDDH[_NWW[qcjx::0Y=!F_WKL+BCIWZSEORAZTZ7;Y+U^FJUDYYQLEMN,QVCUW[OL?=5Z0.K\RLI(OLDT_T@L_NWW_0>Z&ZSEORAZT^AFHI)h}}Ui`~<6:W3+LYQAF%LICQ\YOA\KPR\=0W%_T@L_NWW[FCKD&CT__BPT3,V[VTK:o1^<"GPVHM,C@HX[PDHSB[[[4;^*V_IKVE^XRMJLM-OQQYH]]9=7X> I^TJK*ABFVYRBNQ@UUY6=X(TQGITCXZPCDNO+VNNN]UDYYQ{elr04>S7'@U]EB!HEO]P]KEXG\^P94S!SXL@[JSSWJOG@"[\ES]QAB573\:$ERXFO.EFJZU^FJUDYYU:9\,P]KEXG\^TOHBC/nww[qcjx:<0Y=!F_WKL+BCIWZSEORAZTZ43Y+U^FJUDYYQLEMN,MZUUDV^9"XQ\RM0e?P6(AV\BC"IJN^QZJFYH]]Q=<P \YOA\KPRXKLFG#A[[_NWW73=R8&CTZDA GDL\W\HDWF__W;>R.R[MGZIR\VIN@A!\HHDW[JSSW}of|>>4U1-J[SOH'NOES^WAC^MVP^07U'YRBNQ@UU]@AIJ(]ZOYS_KH319V4*OX^@E$KH@PSXL@[JSSS?:V"^WAC^MVPZEBDE%dyyQ{elr02>S7'@U]EB!HEO]P]KEXG\^P:<S!SXL@[JSSWJOG@"GPSSN\P7(RWZXG>k5Z0.K\RLI(OLDT_T@L_NWW_37Z&ZSEORAZT^AFHI)K]]UDYY=9;T2,MZPNG&MNBR]VNB]LQQ]19T$XUCMPOTV\G@JK'ZBBJYQ@UU]wahv482_;#DQYIN-DAKYTQGITCXZT60_-W\HDWF__SNKCL.WPAWYUMN9;7X> I^TJK*ABFVYRBNQ@UUY55X(TQGITCXZPCDNO+jssW}of|>84U1-J[SOH'NOES^WAC^MVP^05U'YRBNQ@UU]@AIJ(AVYY@RZ=.T]PVI4a3\:$ERXFO.EFJZU^FJUDYYU92\,P]KEXG\^TOHBC/MWW[JSS;?1^<"GPVHM,C@HX[PDHSB[[[70^*V_IKVE^XRMJLM-PLL@SWF__Sykbp228Q5)NW_CD#JKA_R[MGZIR\R<9Q#]VNB]LQQYDMEF$Y^K]_SGD75=R8&CTZDA GDL\W\HDWF__W;<R.R[MGZIR\VIN@A!`uu]wahv4>2_;#DQYIN-DAKYTQGITCXZT62_-W\HDWF__SNKCL.K\WWJX\;$^S^\C2g9V4*OX^@E$KH@PSXL@[JSSS?9V"^WAC^MVPZEBDE%GYYQ@UU15?P6(AV\BC"IJN^QZJFYH]]Q=?P \YOA\KPRXKLFG#^FFFU]LQQYsmdz8<6[?/H]UMJ)@MGUXUCMPOTVX26[)[PDHSB[[_BGOH*STM[UYIJ=?;T2,MZPNG&MNBR]VNB]LQQ]1;T$XUCMPOTV\G@JK'fSykbp268Q5)NW_CD#JKA_R[MGZIR\VKOH_ \YOA\KPRXIMNY#NAZNU-@M979;=1^<"GPVHM,C@HX[PDHSB[[_@FGV+U^FJUDYYQNDEP,GJSI\&IB0?0<4:W3+LYQAF%LICQ\YOA\KPRXIMNY"^WAC^MVPZGCL[%HCX@[/BK?7;543\:$ERXFO.EFJZU^FJUDYYQNDEP-W\HDWF__SLJKR.ALQKR(L5:5?>5Z0.K\RLI(OLDT_T@L_NWW[DBCZ'YRBNQ@UU]B@AT(KF_EX"J31?10?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"M@UOV,@949;:1^<"GPVHM,C@HX[PDHSB[[_@FGV+U^FJUDYYQNDEP,GJSI\&N7?3=i;T2,MZPNG&MNBR]VNB]LQQYFLMX%_T@L_NWW[DBCZ&IDYCZ GZ2^*BhO&\UFYUMV3`9V4*OX^@E$KH@PSXL@[JSSWHNO^#]VNB]LQQYFLMX$OB[AT.EX4X(RWONYI>74U1-J[SOH'NOES^WAC^MVPZGCL[$XUCMPOTV\EABU'JE^BY!H[1_-QZJR\:h0Y=!F_WKL+BCIWZSEORAZT^CG@W(TQGITCXZPAEFQ+FIRF]%LW=S!U^ZLVF_4n2_;#DQYIN-DAKYTQGITCXZPAEFQ*V_IKVE^XROKDS-@KPHS'NQ:Q#IaH/W\IP^DQ:k0Y=!F_WKL+BCIWZSEORAZT^CG@W(TQGITCXZPAEFQ+FIRF]%LW<S!U^DGV@5>3\:$ERXFO.EFJZU^FJUDYYQNDEP-W\HDWF__SLJKR.ALQKR(OR;V"XQCUU1a?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"M@UOV,C^7Z&\USC_MV3g9V4*OX^@E$KH@PSXL@[JSSWHNO^#]VNB]LQQYFLMX$OB[AT.EX6X(@fA$^S@[WCX1b?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"M@UOV,C^4Z&\UMH_K<9:W3+LYQAF%LICQ\YOA\KPRXIMNY"^WAC^MVPZGCL[%HCX@[/FY1Y+SXD\^8n6[?/H]UMJ)@MGUXUCMPOTV\EABU&ZSEORAZT^CG@W)DG\D_#JU=]/W\\JTDQ:k0Y=!F_WKL+BCIWZSEORAZT^CG@W(TQGITCXZPAEFQ+FIRF]%LW>S!U^DGV@5>3\:$ERXFO.EFJZU^FJUDYYQNDEP-W\HDWF__SLJKR.ALQKR(OR9V"XQCUU1a?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"M@UOV,C^5Z&\USC_MV329V4*OX^@E$KH@PSXL@[JSSWHNO^#]VNB]LQQYFLMX$OB[AT.Q?4;543\:$ERXFO.EFJZU^FJUDYYQNDEP-W\HDWF__SLJKR.ALQKR([5;5?>5Z0.K\RLI(OLDT_T@L_NWW[DBCZ'YRBNQ@UU]B@AT(KF_EX"]32?10?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"M@UOV,W959;81^<"GPVHM,C@HX[PDHSB[[_@FGV+U^FJUDYYQNDEP,@I_6W[OL?<5Z0.K\RLI(OLDT_T@L_NWW[DBCZ'YRBNQ@UU]B@AT(LES9S_KH2g9V4*OX^@E$KH@PSXL@[JSSWHNO^#]VNB]LQQYFLMX$@XZPCD13?P6(AV\BC"IJN^QZJFYH]]UJHI\!SXL@[JSSWHNO^"BZT^MVP67<]9%BS[G@/FGM[V_IKVE^XROKDS,P]KEXG\^TMIJ]/`pn[aj~9:;0Y=!F_WKL+BCIWZSEORAZT^CG@W(TQGITCXZPAEFQ+dtjWmfr>?h4U1-J[SOH'NOES^WAC^MVPZGCL[$XUCMPOTV\EABU'jdSnk<2:W3+LYQAF%LICQ\YOA\KPRXIMNY"^WAC^MVPZGCL[%hbyQ}ergw65=R8&CTZDA GDL\PWGI['_TM_C U^AOADT6n2_;#DQYIN-DAKYSZHDX"XQNRL-V[AIR\;:0Y=!F_WKL+BCIW]XJB^ Z_@PN+PYCG\^;>=5Z0.K\RLI(OLDTX_OAS/W\EWK(]VNDYY?=c:W3+LYQAF%LICQ[R@LP*PYFZD%^SJKA_EGOE\]6U'_TJI<?;T2,MZPNG&MNBRZ]AOQ-QZGUE&_T^KJ]E328Q5)NW_CD#JKA_UPBJV(RWHXF#XQ[FEPF61=R8&CTZDA GDL\PWGI['_TM_C dhl\hdrd`ln:h6[?/H]UMJ)@MGU_^L@\.T]BVH)nKEX9<6[?/H]UMJ)@MGU_^L@\.T]BVH)nL@D7<3<?;T2,MZPNG&MNBRZ]AOQ-QZGUE&cOEC2>>378Q5)NW_CD#JKA_UPBJV(RWHXF#dJ@UU]gh|:76;?0Y=!F_WKL+BCIW]XJB^ Z_@PN+lBH]]Uo`t2>>2;8Q5)NW_CD#JKA_TRGEQCXG\^P==>R.TRGEQCXKLFG#JKA_BNH*PUBZVXNK><4U1-J[SOH'NOESX^KAUG\KPR\99:V"X^KAUG\G@JK'ZBBJYQ]EF1:?P6(AV\BC"IJN^WS@DRBWF__W<>>]/WS@DRBWJOG@"IJN^AOO+STM[UYIJ==;T2,MZPNG&MNBR[_D@VF[JSSS8::Q#[_D@VF[FCKD&YCEKZPRDE0=>S7'@U]EB!HEO]VTAGSMVE^XV??2\,VTAGSMVIN@A!HEO]@HN(R[LXT^HI<2:W3+LYQAF%LICQZPECWAZIR\R;;>P ZPECWAZEBDE%XDDH[_SGD7<=R8&CTZDA GDL\QUBF\LUDYYU>02_-QUBF\LUHIAB GDL\GIM)]ZOYS_KH339V4*OX^@E$KH@PUQFBP@YH]]Q:<>S!UQFBP@YDMEF$_EGIT^PFC6?<]9%BS[G@/FGM[PVCI]OTCXZT116^*PVCI]OTOHBC/FGM[FJL&\YN^R\JG208Q5)NW_CD#JKA_TRGEQCXG\^P==:R.TRGEQCXKLFG#^FFFU]QAB5>3\:$ERXFO.EFJZSWLH^NSB[[[026Y+SWLH^NSNKCL.EFJZEKC'_XI_Q]EF11?P6(AV\BC"IJN^WS@DRBWF__W<>:]/WS@DRBWJOG@"]GIGV\V@A412_;#DQYIN-DAKYRXMK_IRAZTZ332X(RXMK_IRMJLM-DAKYDDB$^_H\PRDE06>S7'@U]EB!HEO]VTAGSMVE^XV??6\,VTAGSMVIN@A!\HHDW[WC@;01^<"GPVHM,C@HX]YNJXHQ@UUY242[)]YNJXHQLEMN,C@HXKEA%Y^K]_SGD77=R8&CTZDA GDL\QUBF\LUDYYU>06_-QUBF\LUHIAB SIKEPZTBO:30Y=!F_WKL+BCIW\ZOMYKPOTVX55>Z&\ZOMYKPCDNO+BCIWJF@"X]JR^PFC64<]9%BS[G@/FGM[PVCI]OTCXZT11:^*PVCI]OTOHBC/RJJBQYUMN927X> I^TJK*ABFV_[HLZJ_NWW_46>U'_[HLZJ_BGOH*ABFVIGG#[\ES]QAB553\:$ERXFO.EFJZSWLH^NSB[[[02:Y+SWLH^NSNKCL.QKMCRXZLM856[?/H]UMJ)@MGU^\IO[E^MVP^768T$^\IO[E^AFHI)@MGUH@F ZSDP\V@A4:2_;#DQYIN-DAKYRXMK_IRAZTZ324X(RXMK_IRMJLM-PLL@SW[OL?45Z0.K\RLI(OLDTY]JNTD]LQQ]698W%Y]JNTD]@AIJ(OLDTOAE!URGQ[WC@;;1^<"GPVHM,C@HX]YNJXHQ@UUY254[)]YNJXHQLEMN,WMOA\VXNK>74U1-J[SOH'NOESX^KAUG\KPR\988V"X^KAUG\G@JK'NOESNBD.TQFVZTBO:80Y=!F_WKL+BCIW\ZOMYKPOTVX544Z&\ZOMYKPCDNO+VNNN]UYIJ=6;T2,MZPNG&MNBR[_D@VF[JSSS8;8Q#[_D@VF[FCKD&MNBRMCK/WPAWYUMN997X> I^TJK*ABFV_[HLZJ_NWW_474U'_[HLZJ_BGOH*UOAO^T^HI<9:W3+LYQAF%LICQZPECWAZIR\R;:8P ZPECWAZEBDE%LICQLLJ,VW@TXZLM8>6[?/H]UMJ)@MGU^\IO[E^MVP^76<T$^\IO[E^AFHI)T@@L_S_KH389V4*OX^@E$KH@PUQFBP@YH]]Q:=8S!UQFBP@YDMEF$KH@PCMI-QVCUW[OL??5Z0.K\RLI(OLDTY]JNTD]LQQ]69<W%Y]JNTD]@AIJ([ACMXR\JG2;8Q5)NW_CD#JKA_TRGEQCXG\^P=<8R.TRGEQCXKLFG#JKA_BNH*PUBZVXNK><4U1-J[SOH'NOESX^KAUG\KPR\98<V"X^KAUG\G@JK'ZBBJYQ]EF1:?P6(AV\BC"IJN^WS@DRBWF__W<?8]/WS@DRBWJOG@"IJN^AOO+STM[UYIJ==;T2,MZPNG&MNBR[_D@VF[JSSS8;<Q#[_D@VF[FCKD&YCEKZPRDE0=>S7'@U]EB!HEO]VTAGSMVE^XV?>8\,VTAGSMVIN@A!HEO]@HN(R[LXT^HI<2:W3+LYQAF%LICQZPECWAZIR\R;:4P ZPECWAZEBDE%XDDH[_SGD7<=R8&CTZDA GDL\QUBF\LUDYYU>18_-QUBF\LUHIAB GDL\GIM)]ZOYS_KH339V4*OX^@E$KH@PUQFBP@YH]]Q:=4S!UQFBP@YDMEF$_EGIT^PFC6?<]9%BS[G@/FGM[PVCI]OTCXZT132^*PVCI]OTOHBC/FGM[FJL&\YN^R\JG208Q5)NW_CD#JKA_TRGEQCXG\^P=?>R.TRGEQCXKLFG#^FFFU]QAB5>3\:$ERXFO.EFJZSWLH^NSB[[[002Y+SWLH^NSNKCL.EFJZEKC'_XI_Q]EF11?P6(AV\BC"IJN^WS@DRBWF__W<<>]/WS@DRBWJOG@"]GIGV\V@A412_;#DQYIN-DAKYRXMK_IRAZTZ316X(RXMK_IRMJLM-DAKYDDB$^_H\PRDE06>S7'@U]EB!HEO]VTAGSMVE^XV?=2\,VTAGSMVIN@A!\HHDW[WC@;01^<"GPVHM,C@HX]YNJXHQ@UUY266[)]YNJXHQLEMN,C@HXKEA%Y^K]_SGD77=R8&CTZDA GDL\QUBF\LUDYYU>22_-QUBF\LUHIAB SIKEPZTBO:30Y=!F_WKL+BCIW\ZOMYKPOTVX572Z&\ZOMYKPCDNO+BCIWJF@"X]JR^PFC64<]9%BS[G@/FGM[PVCI]OTCXZT136^*PVCI]OTOHBC/RJJBQYUMN927X> I^TJK*ABFV_[HLZJ_NWW_442U'_[HLZJ_BGOH*ABFVIGG#[\ES]QAB553\:$ERXFO.EFJZSWLH^NSB[[[006Y+SWLH^NSNKCL.QKMCRXZLM856[?/H]UMJ)@MGU^\IO[E^MVP^75>T$^\IO[E^AFHI)@MGUH@F ZSDP\V@A4:2_;#DQYIN-DAKYRXMK_IRAZTZ312X(RXMK_IRMJLM-PLL@SW[OL?45Z0.K\RLI(OLDTY]JNTD]LQQ]6:>W%Y]JNTD]@AIJ(OLDTOAE!URGQ[WC@;;1^<"GPVHM,C@HX]YNJXHQ@UUY262[)]YNJXHQLEMN,WMOA\VE^X><4U1-J[SOH'NOESX^KAUG\KPR\9;=V"X^KAUG\G@JK'ZBBJYQ]EF1a?P6(AV\BC"IJN^WS@DRBWF__W;:R.TRGEQCXKLFG#JKA_OM\GIM)]ZOYS_KH309V4*OX^@E$KH@PUQFBP@YH]]Q=8P ZPECWAZEBDE%XDDH[_SGD7g=R8&CTZDA GDL\QUBF\LUDYYU95\,VTAGSMVIN@A!HEO]MKZEKC'_XI_Q]EF12?P6(AV\BC"IJN^WS@DRBWF__W;;R.TRGEQCXKLFG#^FFFU]QAB5e3\:$ERXFO.EFJZSWLH^NSB[[[74^*PVCI]OTOHBC/FGM[KIXKEA%Y^K]_SGD74=R8&CTZDA GDL\QUBF\LUDYYU96\,VTAGSMVIN@A!\HHDW[WC@;k1^<"GPVHM,C@HX]YNJXHQ@UUY53X(RXMK_IRMJLM-DAKYIGVIGG#[\ES]QAB563\:$ERXFO.EFJZSWLH^NSB[[[75^*PVCI]OTOHBC/RJJBQYUMN9i7X> I^TJK*ABFV_[HLZJ_NWW_3>Z&\ZOMYKPCDNO+BCIWGETOAE!URGQ[WC@;81^<"GPVHM,C@HX]YNJXHQ@UUY5<X(RXMK_IRMJLM-PLL@SW[OL?o5Z0.K\RLI(OLDTY]JNTD]LQQ]11T$^\IO[E^AFHI)@MGUECRMCK/WPAWYUMN9:7X> I^TJK*ABFV_[HLZJ_NWW_3?Z&\ZOMYKPCDNO+VNNN]UYIJ=m;T2,MZPNG&MNBR[_D@VF[JSSS>:V"X^KAUG\G@JK'NOESCAPCMI-QVCUW[OL?<5Z0.K\RLI(OLDTY]JNTD]LQQ]08T$^\IO[E^AFHI)T@@L_S_KH3c9V4*OX^@E$KH@PUQFBP@YH]]Q<=P ZPECWAZEBDE%LICQAO^AOO+STM[UYIJ=>;T2,MZPNG&MNBR[_D@VF[JSSS>;V"X^KAUG\G@JK'ZBBJYQ]EF1a?P6(AV\BC"IJN^WS@DRBWF__W:<R.TRGEQCXKLFG#JKA_OM\GIM)]ZOYS_KH309V4*OX^@E$KH@PUQFBP@YH]]Q<>P ZPECWAZEBDE%XDDH[_SGD7g=R8&CTZDA GDL\QUBF\LUDYYU83\,VTAGSMVIN@A!HEO]MKZEKC'_XI_Q]EF12?P6(AV\BC"IJN^WS@DRBWF__W:=R.TRGEQCXKLFG#^FFFU]QAB5e3\:$ERXFO.EFJZSWLH^NSB[[[66^*PVCI]OTOHBC/FGM[KIXKEA%Y^K]_SGD74=R8&CTZDA GDL\QUBF\LUDYYU84\,VTAGSMVIN@A!\HHDW[WC@;k1^<"GPVHM,C@HX]YNJXHQ@UUY41X(RXMK_IRMJLM-DAKYIGVIGG#[\ES]QAB563\:$ERXFO.EFJZSWLH^NSB[[[67^*PVCI]OTOHBC/RJJBQYUMN9i7X> I^TJK*ABFV_[HLZJ_NWW_20Z&\ZOMYKPCDNO+BCIWGETOAE!URGQ[WC@;81^<"GPVHM,C@HX]YNJXHQ@UUY42X(RXMK_IRMJLM-PLL@SW[OL?o5Z0.K\RLI(OLDTY]JNTD]LQQ]0?T$^\IO[E^AFHI)@MGUECRMCK/WPAWYUMN9:7X> I^TJK*ABFV_[HLZJ_NWW_21Z&\ZOMYKPCDNO+VNNN]UYIJ=m;T2,MZPNG&MNBR[_D@VF[JSSS>2V"X^KAUG\G@JK'NOESCAPCMI-QVCUW[OL?<5Z0.K\RLI(OLDTY]JNTD]LQQ]00T$^\IO[E^AFHI)T@@L_S_KH3c9V4*OX^@E$KH@PUQFBP@YH]]Q<5P ZPECWAZEBDE%LICQAO^AOO+STM[UYIJ=>;T2,MZPNG&MNBR[_D@VF[JSSS>3V"X^KAUG\G@JK'ZBBJYQ]EF1a?P6(AV\BC"IJN^WS@DRBWF__W5>R.TRGEQCXKLFG#JKA_OM\GIM)]ZOYS_KH309V4*OX^@E$KH@PUQFBP@YH]]Q3<P ZPECWAZEBDE%XDDH[_SGD7g=R8&CTZDA GDL\QUBF\LUDYYU71\,VTAGSMVIN@A!HEO]MKZEKC'_XI_Q]EF12?P6(AV\BC"IJN^WS@DRBWF__W5?R.TRGEQCXKLFG#^FFFU]QAB5e3\:$ERXFO.EFJZSWLH^NSB[[[90^*PVCI]OTOHBC/FGM[KIXKEA%Y^K]_SGD74=R8&CTZDA GDL\QUBF\LUDYYU72\,VTAGSMVIN@A!\HHDW[WC@;k1^<"GPVHM,C@HX]YNJXHQ@UUY;7X(RXMK_IRMJLM-DAKYIGVIGG#[\ES]QAB563\:$ERXFO.EFJZSWLH^NSB[[[91^*PVCI]OTOHBC/RJJBQYUMN9i7X> I^TJK*ABFV_[HLZJ_NWW_=2Z&\ZOMYKPCDNO+BCIWGETOAE!URGQ[WC@;81^<"GPVHM,C@HX]YNJXHQ@UUY;0X(RXMK_IRMJLM-PLL@SW[OL?o5Z0.K\RLI(OLDTY]JNTD]LQQ]?=T$^\IO[E^AFHI)@MGUECRMCK/WPAWYUMN9:7X> I^TJK*ABFV_[HLZJ_NWW_=3Z&\ZOMYKPCDNO+VNNN]UYIJ=m;T2,MZPNG&MNBR[_D@VF[JSSS1<V"X^KAUG\G@JK'NOESCAPCMI-QVCUW[OL?<5Z0.K\RLI(OLDTY]JNTD]LQQ]?>T$^\IO[E^AFHI)T@@L_S_KH3c9V4*OX^@E$KH@PUQFBP@YH]]Q3;P ZPECWAZEBDE%LICQAO^AOO+STM[UYIJ=>;T2,MZPNG&MNBR[_D@VF[JSSS1=V"X^KAUG\G@JK'ZBBJYQ]EF1a?P6(AV\BC"IJN^WS@DRBWF__W56R.TRGEQCXKLFG#JKA_OM\GIM)]ZOYS_KH309V4*OX^@E$KH@PUQFBP@YH]]Q34P ZPECWAZEBDE%XDDH[_SGD7g=R8&CTZDA GDL\QUBF\LUDYYU79\,VTAGSMVIN@A!HEO]MKZEKC'_XI_Q]EF12?P6(AV\BC"IJN^WS@DRBWF__W57R.TRGEQCXKLFG#^FFFU]QAB5e3\:$ERXFO.EFJZSWLH^NSB[[[82^*PVCI]OTOHBC/FGM[KIXKEA%Y^K]_SGD74=R8&CTZDA GDL\QUBF\LUDYYU60\,VTAGSMVIN@A!\HHDW[WC@;k1^<"GPVHM,C@HX]YNJXHQ@UUY:5X(RXMK_IRMJLM-DAKYIGVIGG#[\ES]QAB563\:$ERXFO.EFJZSWLH^NSB[[[83^*PVCI]OTOHBC/RJJBQYUMN9i7X> I^TJK*ABFV_[HLZJ_NWW_<4Z&\ZOMYKPCDNO+BCIWGETOAE!URGQ[WC@;81^<"GPVHM,C@HX]YNJXHQ@UUY:6X(RXMK_IRMJLM-PLL@SW[OL?o5Z0.K\RLI(OLDTY]JNTD]LQQ]>;T$^\IO[E^AFHI)@MGUECRMCK/WPAWYUMN9:7X> I^TJK*ABFV_[HLZJ_NWW_<5Z&\ZOMYKPCDNO+VNNN]UYIJ=m;T2,MZPNG&MNBR[_D@VF[JSSS0>V"X^KAUG\G@JK'NOESCAPCMI-QVCUW[OL?<5Z0.K\RLI(OLDTY]JNTD]LQQ]><T$^\IO[E^AFHI)T@@L_S_KH3c9V4*OX^@E$KH@PUQFBP@YH]]Q29P ZPECWAZEBDE%LICQAO^AOO+STM[UYIJ=>;T2,MZPNG&MNBR[_D@VF[JSSS0?V"X^KAUG\G@JK'ZBBJYQ]EF1;?P6(AV\BC"IJN^WS@DRBWF__W48R.TRGEQCXKLFG#JKA_BNH*PUBZVXNK>?4U1-J[SOH'NOESX^KAUG\KPR\1?W%Y]JNTD]@AIJ([ACMXR\JG2:8Q5)NW_CD#JKA_TRGEQCXG\^P5:S!UQFBP@YDMEF$KH@PCMI-QVCUW[OL?<5Z0.K\RLI(OLDTY]JNTD]LQQ]>?T$^\IO[E^AFHI)T@@L_S_KH399V4*OX^@E$KH@PUQFBP@YH]]Q24P ZPECWAZEBDE%LICQLLJ,VW@TXZLM8=6[?/H]UMJ)@MGU^\IO[E^MVP^??U'_[HLZJ_BGOH*UOAO^T^HI<8:W3+LYQAF%LICQZPECWAZIR\R32Q#[_D@VF[FCKD&MNBRMCK/WPAWYUMN9:7X> I^TJK*ABFV_[HLZJ_NWW_<?Z&\ZOMYKPCDNO+VNNN]UYIJ?7;T2,MZPNG&CE\XZPSIKEP9776820Y=!F_WKL+LHW]]UXDDH[<03=5==R8&CTZDA IORVPZUOAO^7=?0>8:W3+LYQAF%BB][[_RJJBQ:6;7;37X> I^TJK*OIX\^T_EGIT=37:4><]9%BS[G@/HLSQQYT@@L_0<;1199V4*OX^@E$EC^ZT^QKMCR;9?4:46[?/H]UMJ)NFY__S^FFFU>23;7?3\:$ERXFO.KMTPRX[ACMX1?7>0:8Q5)NW_CD#D@_UU]PLL@S4835=:5Z0.K\RLI(AGZ^XR]GIGV?5;7?3\:$ERXFO.KMTPRX[ACMX1<?>0:8Q5)NW_CD#D@_UU]PLL@S4;;5=55Z0.K\RLI(AGZ^XR]GIGV?678602_;#DQYIN-JJUSSWZBBJY2=3?3;?P6(AV\BC"GAPTV\WMOA\58?2<64U1-J[SOH'@D[YYQ\HHDW8739911^<"GPVHM,MKVR\VYCEKZ327<2<>S7'@U]EB!FNQWW[VNNN]69;3?7;T2,MZPNG&CE\XZPSIKEP94?6820Y=!F_WKL+LHW]]UXDDH[<3;=52=R8&CTZDA IORVPZUOAO^7>3?7;T2,MZPNG&CE\XZPSIKEP9576820Y=!F_WKL+LHW]]UXDDH[<23=5==R8&CTZDA IORVPZUOAO^7??0>8:W3+LYQAF%BB][[_RJJBQ:4;7;37X> I^TJK*OIX\^T_EGIT=17:4><]9%BS[G@/HLSQQYT@@L_0>;1199V4*OX^@E$EC^ZT^QKMCR;;?4:46[?/H]UMJ)NFY__S^FFFU>03;7?3\:$ERXFO.KMTPRX[ACMX1=7>0:8Q5)NW_CD#D@_UU]PLL@S4:35=:5Z0.K\RLI(AGZ^XR]GIGV?7;7?3\:$ERXFO.KMTPRX[ACMX1:?>0:8Q5)NW_CD#D@_UU]PLL@S4=;5=55Z0.K\RLI(AGZ^XR]GIGV?078602_;#DQYIN-JJUSSWZBBJY2;3?3;?P6(AV\BC"GAPTV\WMOA\5>?2<64U1-J[SOH'@D[YYQ\HHDW8139911^<"GPVHM,MKVR\VYCEKZ347<2<>S7'@U]EB!FNQWW[VNNN]6?;3?7;T2,MZPNG&CE\XZPSIKEP92?6820Y=!F_WKL+LHW]]UXDDH[<5;=52=R8&CTZDA IORVPZUOAO^783?7;T2,MZPNG&CE\XZPSIKEP9376820Y=!F_WKL+LHW]]UXDDH[<43=5==R8&CTZDA IORVPZUOAO^79?0>8:W3+LYQAF%BB][[_RJJBQ:2;7;37X> I^TJK*OIX\^T_EGIT=77:4><]9%BS[G@/HLSQQYT@@L_08;1199V4*OX^@E$EC^ZT^QKMCR;=?4:46[?/H]UMJ)NFY__S^FFFU>63;7?3\:$ERXFO.KMTPRX[ACMX1;7>0:8Q5)NW_CD#D@_UU]PLL@S4<35=:5Z0.K\RLI(AGZ^XR]GIGV?1;7?3\:$ERXFO.KMTPRX[ACMX18?>0:8Q5)NW_CD#D@_UU]PLL@S4?;5=55Z0.K\RLI(AGZ^XR]GIGV?278602_;#DQYIN-JJUSSWZBBJY293?3;?P6(AV\BC"GAPTV\WMOA\5<?2<94U1-J[SOH'@D[YYQ\HHDW8386?2_;#DQYIN-JJUSSWZBBJY28>058Q5)NW_CD#D@_UU]PLL@S414:;6[?/H]UMJ)NFY__S^FFFU>::4g<]9%BS[G@/NWWTPRX[ACMX1??0?3b?P6(AV\BC"AZTQWW[VNNN]6:<<0>a:W3+LYQAF%DYY^ZT^QKMCR;9985=l5Z0.K\RLI(G\^[YYQ\HHDW846468k0Y=!F_WKL+JSSX\^T_EGIT=330;7f3\:$ERXFO.MVPUSSWZBBJY2>04<2e>S7'@U]EB!@UURVPZUOAO^7==811`9V4*OX^@E$CXZ_UU]PLL@S48:<2<o4U1-J[SOH'F__\XZPSIKEP97707;j7X> I^TJK*IR\Y__S^FFFU>24<8612_;#DQYIN-LQQVR\VYCEKZ311<2e>S7'@U]EB!@UURVPZUOAO^7=<>11`9V4*OX^@E$CXZ_UU]PLL@S48;:2<o4U1-J[SOH'F__\XZPSIKEP976:7;j7X> I^TJK*IR\Y__S^FFFU>25686i2_;#DQYIN-LQQVR\VYCEKZ3106=5d=R8&CTZDA OTVSQQYT@@L_0<?:>0c8Q5)NW_CD#B[[PTV\WMOA\5;::3?n;T2,MZPNG&E^X][[_RJJBQ:69>4:m6[?/H]UMJ)H]]Z^XR]GIGV?54>99h1^<"GPVHM,KPRW]]UXDDH[<03::4?<]9%BS[G@/NWWTPRX[ACMX1?>>0c8Q5)NW_CD#B[[PTV\WMOA\5;9<3?n;T2,MZPNG&E^X][[_RJJBQ:6:84:m6[?/H]UMJ)H]]Z^XR]GIGV?57499h1^<"GPVHM,KPRW]]UXDDH[<000:4g<]9%BS[G@/NWWTPRX[ACMX1?=4?3b?P6(AV\BC"AZTQWW[VNNN]6:>80>a:W3+LYQAF%DYY^ZT^QKMCR;9;<5=l5Z0.K\RLI(G\^[YYQ\HHDW84406830Y=!F_WKL+JSSX\^T_EGIT=31:4?<]9%BS[G@/NWWTPRX[ACMX1?<>0;8Q5)NW_CD#B[[PTV\WMOA\5;?2<74U1-J[SOH'F__\XZPSIKEP9726830Y=!F_WKL+JSSX\^T_EGIT=35:4?<]9%BS[G@/NWWTPRX[ACMX1?8>0;8Q5)NW_CD#B[[PTV\WMOA\5;32<74U1-J[SOH'F__\XZPSIKEP97>6820Y=!F_WKL+JSSX\^T_EGIT=3=5<=R8&CTZDA OTVSQQYT@@L_0?>1189V4*OX^@E$CXZ_UU]PLL@S4;;5=45Z0.K\RLI(G\^[YYQ\HHDW8749901^<"GPVHM,KPRW]]UXDDH[<31=5<=R8&CTZDA OTVSQQYT@@L_0?:1189V4*OX^@E$CXZ_UU]PLL@S4;?5=45Z0.K\RLI(G\^[YYQ\HHDW8709901^<"GPVHM,KPRW]]UXDDH[<35=5<=R8&CTZDA OTVSQQYT@@L_0?61189V4*OX^@E$CXZ_UU]PLL@S4;35=55Z0.K\RLI(G\^[YYQ\HHDW878612_;#DQYIN-LQQVR\VYCEKZ331<2=>S7'@U]EB!@UURVPZUOAO^7?<0>9:W3+LYQAF%DYY^ZT^QKMCR;;;4:56[?/H]UMJ)H]]Z^XR]GIGV?768612_;#DQYIN-LQQVR\VYCEKZ335<2=>S7'@U]EB!@UURVPZUOAO^7?80>9:W3+LYQAF%DYY^ZT^QKMCR;;?4:56[?/H]UMJ)H]]Z^XR]GIGV?728612_;#DQYIN-LQQVR\VYCEKZ339<2=>S7'@U]EB!@UURVPZUOAO^7?40>8:W3+LYQAF%DYY^ZT^QKMCR;;7;27X> I^TJK*IR\Y__S^FFFU>74;7>3\:$ERXFO.MVPUSSWZBBJY2;1?3:?P6(AV\BC"AZTQWW[VNNN]6?>3?6;T2,MZPNG&E^X][[_RJJBQ:3;7;27X> I^TJK*IR\Y__S^FFFU>70;7>3\:$ERXFO.MVPUSSWZBBJY2;5?3:?P6(AV\BC"AZTQWW[VNNN]6?:3?6;T2,MZPNG&E^X][[_RJJBQ:3?7;27X> I^TJK*IR\Y__S^FFFU>7<;7>3\:$ERXFO.MVPUSSWZBBJY2;9?3;?P6(AV\BC"AZTQWW[VNNN]6?2<74U1-J[SOH'F__\XZPSIKEP9376830Y=!F_WKL+JSSX\^T_EGIT=72:4?<]9%BS[G@/NWWTPRX[ACMX1;=>0;8Q5)NW_CD#B[[PTV\WMOA\5?82<74U1-J[SOH'F__\XZPSIKEP9336830Y=!F_WKL+JSSX\^T_EGIT=76:4?<]9%BS[G@/NWWTPRX[ACMX1;9>0;8Q5)NW_CD#B[[PTV\WMOA\5?<2<74U1-J[SOH'F__\XZPSIKEP93?6830Y=!F_WKL+JSSX\^T_EGIT=7::4><]9%BS[G@/NWWTPRX[ACMX1;1189V4*OX^@E$CXZ_UU]PLL@S4?:5=45Z0.K\RLI(G\^[YYQ\HHDW8379901^<"GPVHM,KPRW]]UXDDH[<70=5<=R8&CTZDA OTVSQQYT@@L_0;=1189V4*OX^@E$CXZ_UU]PLL@S4?>5=45Z0.K\RLI(G\^[YYQ\HHDW8339901^<"GPVHM,KPRW]]UXDDH[<74=5<=R8&CTZDA OTVSQQYT@@L_0;91189V4*OX^@E$CXZ_UU]PLL@S4?25=45Z0.K\RLI(G\^[YYQ\HHDW83?9911^<"GPVHM,KPRW]]UXDDH[<7<2=>S7'@U]EB!@UURVPZUOAO^7;=0>9:W3+LYQAF%DYY^ZT^QKMCR;?84:56[?/H]UMJ)H]]Z^XR]GIGV?378612_;#DQYIN-LQQVR\VYCEKZ372<2=>S7'@U]EB!@UURVPZUOAO^7;90>9:W3+LYQAF%DYY^ZT^QKMCR;?<4:56[?/H]UMJ)H]]Z^XR]GIGV?338612_;#DQYIN-LQQVR\VYCEKZ376<2=>S7'@U]EB!@UURVPZUOAO^7;50>9:W3+LYQAF%DYY^ZT^QKMCR;?04:46[?/H]UMJ)H]]Z^XR]GIGV?3;7>3\:$ERXFO.MVPUSSWZBBJY270?3:?P6(AV\BC"AZTQWW[VNNN]63=3?6;T2,MZPNG&E^X][[_RJJBQ:?:7;27X> I^TJK*IR\Y__S^FFFU>;7;7>3\:$ERXFO.MVPUSSWZBBJY274?3:?P6(AV\BC"AZTQWW[VNNN]6393?6;T2,MZPNG&E^X][[_RJJBQ:?>7;27X> I^TJK*IR\Y__S^FFFU>;3;7>3\:$ERXFO.MVPUSSWZBBJY278?3:?P6(AV\BC"AZTQWW[VNNN]6353?7;T2,MZPNG&E^X][[_RJJBQ:?6830Y=!F_WKL+JSSX\^T_EGIT=;3:4?<]9%BS[G@/NWWTPRX[ACMX17>>0;8Q5)NW_CD#B[[PTV\WMOA\5392<74U1-J[SOH'F__\XZPSIKEP9?46830Y=!F_WKL+JSSX\^T_EGIT=;7:4?<]9%BS[G@/NWWTPRX[ACMX17:>0;8Q5)NW_CD#B[[PTV\WMOA\53=2<74U1-J[SOH'F__\XZPSIKEP9?06830Y=!F_WKL+JSSX\^T_EGIT=;;:4?<]9%BS[G@/NWWTPRX[ACMX176>0:8Q5)NW_CD#B[[PTV\WMOA\535i6[?/H]UMJ)UMZO_=?5Z0.K\RLI([]K_SIAZT008Q5)NW_CD#X^KAUG?4;743\:$ERXFO.WS@DRB48:5=>5Z0.K\RLI(]YNJXH2>1?30?P6(AV\BC"[_D@VF84499:1^<"GPVHM,QUBF\L6:?3?<;T2,MZPNG&_[HLZJ<06=56=R8&CTZDA UQFBP@:6=7;87X> I^TJK*SWLH^N0<81129V4*OX^@E$Y]JNTD>23;743\:$ERXFO.WS@DRB4825=>5Z0.K\RLI(]YNJXH2>9?31?P6(AV\BC"[_D@VF8486;2_;#DQYIN-VTAGSM58;2<=4U1-J[SOH'\ZOMYK320<27>S7'@U]EB!ZPECWA9456890Y=!F_WKL+PVCI]O7>>0>3:W3+LYQAF%^\IO[E=07:45<]9%BS[G@/TRGEQC;:<4:?6[?/H]UMJ)RXMK_I1<9>018Q5)NW_CD#X^KAUG?6286;2_;#DQYIN-VTAGSM5832<=4U1-J[SOH'\ZOMYK328<26>S7'@U]EB!ZPECWA9499:1^<"GPVHM,QUBF\L68<3?<;T2,MZPNG&_[HLZJ<23=56=R8&CTZDA UQFBP@:4:7;87X> I^TJK*SWLH^N0>=1129V4*OX^@E$Y]JNTD>00;743\:$ERXFO.WS@DRB4:?5=>5Z0.K\RLI(]YNJXH2<6?30?P6(AV\BC"[_D@VF86199:1^<"GPVHM,QUBF\L6843?<;T2,MZPNG&_[HLZJ<2;=57=R8&CTZDA UQFBP@:46890Y=!F_WKL+PVCI]O78=0>3:W3+LYQAF%^\IO[E=62:45<]9%BS[G@/TRGEQC;<;4:?6[?/H]UMJ)RXMK_I1:<>018Q5)NW_CD#X^KAUG?0186;2_;#DQYIN-VTAGSM5>>2<=4U1-J[SOH'\ZOMYK347<27>S7'@U]EB!ZPECWA9206890Y=!F_WKL+PVCI]O7850>3:W3+LYQAF%^\IO[E=6::44<]9%BS[G@/TRGEQC;<7;87X> I^TJK*SWLH^N08>1129V4*OX^@E$Y]JNTD>65;743\:$ERXFO.WS@DRB4<85=>5Z0.K\RLI(]YNJXH2:3?30?P6(AV\BC"[_D@VF80299:1^<"GPVHM,QUBF\L6>93?<;T2,MZPNG&_[HLZJ<44=56=R8&CTZDA UQFBP@:2?7;87X> I^TJK*SWLH^N0861129V4*OX^@E$Y]JNTD>6=;753\:$ERXFO.WS@DRB4<4:?6[?/H]UMJ)RXMK_I18?>018Q5)NW_CD#X^KAUG?2486;2_;#DQYIN-VTAGSM5<92<=4U1-J[SOH'\ZOMYK362<26>S7'@U]EB!ZPECWA9099;1^<"GPVHM,QUBF\L6<2<<4U1-J[SOH'\ZOMYK38?31?P6(AV\BC"[_D@VF8<86;2_;#DQYIN-V[AGSIVE^Xk5Z0.K\RLI(]VNDYY?n;T2,MZPNG&_T_YO[UR-@BBYDMVd956[?/H]UMJ)RWZ^JXX] F^QWEQ]7U'CT_YO[.T]PPDR512_;#DQYIN-V[VRF\\Y$JR][AUY2Y+OX[]K_"XQ\T@V1=>S7'@U]EB!Z_RVBPPU(NVY_MYU=]/K\WQGS&\UXXLZ=9:W3+LYQAF%^S^ZNTTQ,BZUSI]Q8Q#GPSUCW*PYT\H^956[?/H]UMJ)RWZ^JXX] F^QWEQ]3U'CT_YO[.T]PPDR512_;#DQYIN-V[VRF\\Y$JR][AUY6Y+OX[]K_"XQ\T@V1=>S7'@U]EB!Z_RVBPPU(NVY_MYU9]/K\WQGS&\UXXLZ=9:W3+LYQAF%^S^ZNTTQ,BZUSI]Q<Q#GPSUCW*PYT\H^:m6[?/H]UMJ)RWZ^JXX] TEM\j`~s911^<"GPVHM,QZUSI]_X#XQLE^l03>S7'@U]EB!Z_RVBPPU(]VYFYU!Z_BQ\IP^(A=$^S@[W17-Nip~XG1;94>94U1-J[SOH'\UXXLZZS.W\WHS_'\UH_RCZX.K7*PYJ]Q;=#@czx^M;5324?2_;#DQYIN-V[VRF\\Y$YR]BUY-V[FUXE\R$E9 Z_LW[53)Je|rTC5<902`8Q5)NW_CD#XQ\T@VVW*SX[D_S#XQLS^OV\*O3&\UFYU?9/Lov|ZI?:?:T_Z><7:W3+LYQAF%^S^ZNTTQ,QZUJ]Q%^SN]PMTZ,M1(RWD_S=;!Bmtz\K=40?:=0Y=!F_WKL+PYT\H^^_"[PSLW[+PYD[VG^T"G;.T]NQ]71'Dg~tRA735402>S7'@U]EB!Z_RVBPPU(]VYFYU!Z_BQ\IP^(A=$^S@[W17-Nip~XG19>?:5Z0.K\RLI(]VY_MY[\/T]PIP^(]VIXS@[W/H6-QZKRP8<$A`{w_N:0=<503\:$ERXFO.W\WQGS]Z%^S^CZX.W\GVYJ]Q%B8#[PMTZ22*Kj}qUD49;=379V4*OX^@E$YR][AUWP+PYTE\R$YRM\_LW[+L2)]VG^T<8 Mlw{[J>09;80Y=!F_WKL+PYT\H^^_"[PSUCW[FHS'JC7=3<=;T2,MZPNG&_T_YO[UR-V[VRF\VIEX"MF<3<16>S7'@U]EB!Z_RVBPPU(]VY_MYQLNU-@M959:;1^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(K@6?2?<4U1-J[SOH'\UXXLZZS.W\WQGSWJD_#NG35?01?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.AJ8385:2_;#DQYIN-V[VRF\\Y$YR][AU]@JQ)DA5=5><5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$H1>1209V4*OX^@E$YR][AUWP+PYT\H^TOCZ D=3=64=R8&CTZDA U^QWEQST'\UXXLZPCOV,@949:81^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(L595><5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$H1:1209V4*OX^@E$YR][AUWP+PYT\H^TOCZ D=7=64=R8&CTZDA U^QWEQST'\UXXLZPCOV,@909:81^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(L5=5>i5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$KV>R.FlK*PYJ]QIR>55Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$KV>R.T]E@WC5?2_;#DQYIN-V[VRF\\Y$YR][AU]@JQ)@S9W%YRBZT3;8Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/FY3Y+SXPFXHU?j4U1-J[SOH'\UXXLZZS.W\WQGSWJD_#JU>]/EmL+SXE\RHU?64U1-J[SOH'\UXXLZZS.W\WQGSWJD_#JU>]/W\BATB:>1^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(OR;V"XQCUU0:?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.EX5X(RWQEYOT<k;T2,MZPNG&_T_YO[UR-V[VRF\VIEX"IT2\,DjM(RWD_SOT<7;T2,MZPNG&_T_YO[UR-V[VRF\VIEX"IT2\,V[CBUM;=0Y=!F_WKL+PYT\H^^_"[PSUCW[FHS'NQ9Q#[PLTV1=>S7'@U]EB!Z_RVBPPU(]VY_MYQLNU-D_7[)]VRD^NW=d:W3+LYQAF%^S^ZNTTQ,QZUSI]UHBY!H[2_-CkN)]VG^TNW=8:W3+LYQAF%^S^ZNTTQ,QZUSI]UHBY!H[2_-QZ@CZL8<7X> I^TJK*SX[]K_Y^!Z_RVBPZEI\&MP?P Z_MWW6<=R8&CTZDA U^QWEQST'\UXXLZPCOV,C^5Z&\USC_MV2e9V4*OX^@E$YR][AUWP+PYT\H^TOCZ GZ6^*BhO&\UFYUMV299V4*OX^@E$YR][AUWP+PYT\H^TOCZ GZ6^*PYAL[O9;6[?/H]UMJ)RWZ^JXX] U^QWEQYDF]%LW9S!U^NVP7?<]9%BS[G@/T]PPDRR[&_T_YO[_BLW+B]3U'_TTB\LY3f8Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/FY6Y+Ai@'_TAXVLY3:8Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/FY6Y+SXNMXN>:5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$KV;R.T]OQQ4>3\:$ERXFO.W\WQGS]Z%^S^ZNT^AMP*A\=T$^SUA]CX0g?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.EX2X(@fA$^S@[WCX0;?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.EX2X(RWONYI?94U1-J[SOH'\UXXLZZS.W\WQGSWJD_#JU9]/W\HPR512_;#DQYIN-V[VRF\\Y$YR][AU]@JQ)@S?W%YRV@RB[1<>S7'@U]EB!Z_RVBPPU(]VY_MYQLNU-D_2[)]VLO^H<8;T2,MZPNG&_T_YO[UR-V[VRF\VIEX"IT7\,V[ISS:01^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(OR=V"XQWOSAZ64=R8&CTZDA U^QWEQST'\UXXLZPCOV,W969:81^<"GPVHM,QZUSI]_X#XQ\T@V\GKR([5;5><5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$_1<1209V4*OX^@E$YR][AUWP+PYT\H^TOCZ S=1=64=R8&CTZDA U^QWEQST'\UXXLZPCOV,W929:81^<"GPVHM,QZUSI]_X#XQ\T@V\GKR([5?5><5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$_181209V4*OX^@E$YR][AUWP+PYT\H^TOCZ S=5=52=R8&CTZDA U^QWEQST'\U_HB?n;T2,MZPNG&_T_YO[UR-jWQGS494:m6[?/H]UMJ)RWZ^JXX] iRVBP9799h1^<"GPVHM,QZUSI]_X#d][AU>1:4g<]9%BS[G@/T]PPDRR[&cXXLZ33?3b?P6(AV\BC"[PSUCWQV)n[]K_090>a:W3+LYQAF%^S^ZNTTQ,mVRF\5?5=l5Z0.K\RLI(]VY_MY[\/hQWEQ:168k0Y=!F_WKL+PYT\H^^_"g\T@V?3;7b3\:$ERXFO.W\WQGS]Z%b_YO[_BLW8586m2_;#DQYIN-V[VRF\\Y$e^ZNT^AMP9799l1^<"GPVHM,QZUSI]_X#d][AU]@JQ:568o0Y=!F_WKL+PYT\H^^_"g\T@V\GKR;;7;n7X> I^TJK*SX[]K_Y^!fSUCW[FHS4=4:i6[?/H]UMJ)RWZ^JXX] iRVBPZEI\5?5=h5Z0.K\RLI(]VY_MY[\/hQWEQYDF]6=2<k4U1-J[SOH'\UXXLZZS.kPPDRXKG^7;3??;T2,MZPNG&koh2?>028Q5)NW_CD#ljkr=3=55=R8&CTZDA aefq878682_;#DQYIN-b`at;;7897X> I^TJK*tb{l~TjRkkgd-J[M4K&\UOCXZ>d:W3+LYQAF%yi~k{_g]f`bc(]VNDYY>>d:W3+LYQAF%yi~k{_g]f`bc(]VNDYY?>e:W3+LYQAF%yi~k{_g]f`bc(aME^X1>11d9V4*OX^@E$~h}jt^d\aaab'`NDYY2>>b9VW@TX^@YBNAK<;WA@=>PNM^U_U]K>d:ZJHLH_%QNI,= > RVVF%6)9)KXODG:;YMQG\0<PZ^GEO94XRV\CKB03QY_S[MLb:Z\GJTBW@DMC;5Wdc]J`46<PmgTAld`rWgqwlii991Sh`QBiomqR`ttafd87U}{309`llvtkfznS{g`_w3\46Yf$)Rb`d`w BMQA%Abflxjxb|/10,2<>bf|hU}eb<7;ecweZpng%ice}}loqg\rliX~8U;?Ro#NNLF(KIIM;io7io{a^tjk)eoayyhc}kPvhm\r4Y7;Vk'wnQwcn]omvr:Kfg{cckat^Lbi`;ci}kTzda4Eocah`YTqgic~b``ur]JjussWYeyx0z}ud9FjddkmVYrbnf}oomvwZIr|yS]a}t<vqq`=BfhhgiRO|yoakvjhh}zUBb}{{_Qmqp8ru}l1Nbllce^Cp}keozfddy~Q@uurvpZVhz}7~xk4Sxl`lwiig|yTEc~zt^RlvqYPam~c1><4Sxl`lwiig|yTCxzuu]SkwrX_`nd0==;@qzjfnugge~RGaptv\TjtsW^coxe3<2:Cp}keozfddy~Q@uurvpZVhz}U\eizg=208Mkpbz}UH`bmd_Hlsqq;aieyn nQwddtjg``fe`fr1{g}tdz5(fYdg{oTxt~j=8.`[h``W`n6=!mPm`hlvZpbzzcdb0?>,b]nmkiuWoydaa=0.`[gsndmUyi{g|inl>4)eXkfxnS`oeos]uaw;6$jUhckPmhllvZpbz48'oRm`rd]nmkiuWhf{dlQyes?:3)eX{{f::Rzvpd?1(fYr{lUbb{Qllj?3(fYr{lUjt`l_hl>5)eX}zoTm~wac^mvp87+kVxiR}vnb]jj87+kVxiR}vnb]lqq;6$jUjt`l_hl\slbs`499 nQnsxl`[jssW~coxe3<2-a\w|hdW`dT{dj{h<11(fYtqgiTcxzPwhfwl855$t;:7um9vmz41q+an>2?!?sO@q0:g2=GHqi;>7H52;3xW=1=k9:15>4>33:g24<5kk>2wclie;38jg`a2<1/nkj5bg58yV072j:;64=5120;`37=:jh?j6jl0383>4<6sZ2<6n>?:819564?l?;1>nl;9:tWf1<7280:6;?7{R:4>f672091=><7d7396fd312.ij;46f:&b`?e7=2hh<?4?:`791<2=>82pDoh;;%d:>f653S?368u8:98a><<f2t.ijn4l009'1f<d8:1/4;4l059j6`<72-km6?j4n`g94>=n:j0;6)oi:3f8jdc=921b>l4?:%ce>7b<fho1>65f2883>!ga2;n0blk53:9j6=<72-km6?j4n`g90>=n:>0;6)oi:3f8jdc==21b>;4?:%ce>7b<fho1:65f2483>!ga2;n0blk57:9j61<72-km6?j4n`g9<>=n::0;6)oi:3f8jdc=121b>?4?:%ce>7b<fho1m65f2083>!ga2;n0blk5b:9j5c<72-km6?j4n`g9g>=n9l0;6)oi:3f8jdc=l21b=i4?:%ce>7b<fho1i65f1b83>!ga2;n0blk5f:9j5g<72-km6?j4n`g955=<a8k1<7*nf;0g?kgb28;07d?6:18'ec<5l2dji7?=;:k2<?6=,hl1>i5aad827>=n9>0;6)oi:3f8jdc=9=10e<850;&bb?4c3gkn6<;4;h16>5<#io09h6`ne;35?>o4<3:1(lh52e9me`<6?21b?>4?:%ce>7b<fho1=554i2094?"fn38o7coj:0;8?l56290/mk4=d:lba?7f32c8<7>5$`d96a=iil0:n65f2g83>!ga2;n0blk51b98m7d=83.jj7<k;ocf>4b<3`8;6=4+ag81`>hfm3;n76g>5;29 d`=:m1emh4>f:9jgc<72-km6nk4n`g94>=nkm0;6)oi:bg8jdc=921boo4?:%ce>fc<fho1>65fc`83>!ga2jo0blk53:9jg<<72-km6nk4n`g90>=nk10;6)oi:bg8jdc==21bo:4?:%ce>fc<fho1:65fc783>!ga2jo0blk57:9jg0<72-km6nk4n`g9<>=nk=0;6)oi:bg8jdc=121bo>4?:%ce>fc<fho1m65fc383>!ga2jo0blk5b:9jg5<72-km6nk4n`g9g>=njo0;6)oi:bg8jdc=l21bnh4?:%ce>fc<fho1i65fbe83>!ga2jo0blk5f:9jff<72-km6nk4n`g955=<akh1<7*nf;af?kgb28;07dln:18'ec<dm2dji7?=;:ka=?6=,hl1oh5aad827>=nj10;6)oi:bg8jdc=9=10eo950;&bb?eb3gkn6<;4;hf5>5<#io0hi6`ne;35?>oc=3:1(lh5cd9me`<6?21bh94?:%ce>fc<fho1=554ie194?"fn3in7coj:0;8?lb5290/mk4le:lba?7f32co=7>5$`d9g`=iil0:n65fd183>!ga2jo0blk51b98mfe=83.jj7mj;ocf>4b<3`i:6=4+ag8`a>hfm3;n76gm6;29 d`=kl1emh4>f:9(3`<72-km6:j4n`g94>=,?j0;6)oi:6f8jdc=921 ;o4?:%ce>2b<fho1>65$7`83>!ga2>n0blk53:9(3<<72-km6:j4n`g90>=,?10;6)oi:6f8jdc==21 ;;4?:%ce>2b<fho1:65$7483>!ga2>n0blk57:9(31<72-km6:j4n`g9<>=,?:0;6)oi:6f8jdc=121 ;?4?:%ce>2b<fho1m65$7083>!ga2>n0blk5b:9(35<72-km6:j4n`g9g>=,>o0;6)oi:6f8jdc=l21 :h4?:%ce>2b<fho1i65$6e83>!ga2>n0blk5f:9(2g<72-km6:j4n`g955=<#?k1<7*nf;5g?kgb28;07&86:18'ec<0l2dji7?=;:)5<?6=,hl1;i5aad827>=,>>0;6)oi:6f8jdc=9=10';850;&bb?1c3gkn6<;4;*46>5<#io0<h6`ne;35?>-1<3:1(lh57e9me`<6?21 :>4?:%ce>2b<fho1=554+7094?"fn3=o7coj:0;8?.>2290/mk48d:lba?7f32!387>5$`d93a=iil0:n65$8283>!ga2>n0blk51b98/=4=83.jj79k;ocf>4b<3"2:6=4+ag84`>hfm3;n76%70;29 d`=?m1emh4>f:9(32<72-km6:j4n`g964=<#?i1<7*nf;5g?kgb2;807&8>:18'ec<0l2dji7<<;:k6a?6=3f>m6=4+ag87a>hfm3:07b:k:18'ec<3m2dji7?4;n6a>5<#io0?i6`ne;08?j2f290/mk4;e:lba?5<3f>26=4+ag87a>hfm3>07b:7:18'ec<3m2dji7;4;n64>5<#io0?i6`ne;48?j21290/mk4;e:lba?1<3f>>6=4+ag87a>hfm3207b:;:18'ec<3m2dji774;n60>5<#io0?i6`ne;c8?j25290/mk4;e:lba?d<3f>;6=4+ag87a>hfm3i07b=i:18'ec<3m2dji7j4;n1f>5<#io0?i6`ne;g8?j5c290/mk4;e:lba?`<3f9h6=4+ag87a>hfm3;;76a<b;29 d`=<l1emh4>1:9l7d<72-km69k4n`g957=<g:31<7*nf;6f?kgb28907b=7:18'ec<3m2dji7?;;:m03?6=,hl18h5aad821>=h=?0;6)oi:5g8jdc=9?10c8;50;&bb?2b3gkn6<94;n77>5<#io0?i6`ne;3;?>i2;3:1(lh54d9me`<6121d9?4?:%ce>1c<fho1=l54o4394?"fn3>n7coj:0`8?j37290/mk4;e:lba?7d32e?o7>5$`d90`=iil0:h65`4083>!ga2=o0blk51d98k60=83.jj7:j;ocf>4`<3fl;6=4+ag8fb>hfm3:07bkj:18'ec<bn2dji7?4;ng`>5<#io0nj6`ne;08?jce290/mk4jf:lba?5<3foj6=4+ag8fb>hfm3>07bk6:18'ec<bn2dji7;4;ng;>5<#io0nj6`ne;48?jc0290/mk4jf:lba?1<3fo=6=4+ag8fb>hfm3207bk::18'ec<bn2dji774;ng7>5<#io0nj6`ne;c8?jc4290/mk4jf:lba?d<3fo:6=4+ag8fb>hfm3i07bk?:18'ec<bn2dji7j4;nfe>5<#io0nj6`ne;g8?jbb290/mk4jf:lba?`<3fno6=4+ag8fb>hfm3;;76akc;29 d`=mo1emh4>1:9l`g<72-km6hh4n`g957=<gmk1<7*nf;ge?kgb28907bj6:18'ec<bn2dji7?;;:mg<?6=,hl1ik5aad821>=hn>0;6)oi:dd8jdc=9?10ck850;&bb?ca3gkn6<94;nd6>5<#io0nj6`ne;3;?>ia<3:1(lh5eg9me`<6121dj>4?:%ce>``<fho1=l54og094?"fn3om7coj:0`8?j`6290/mk4jf:lba?7d32enh7>5$`d9ac=iil0:h65`e383>!ga2ll0blk51d98ka1=83.jj7ki;ocf>4`<3"=m6=4+ag84`>hfm38;76lmf`83>4<729q/j4462:Jab<=Ojo>0c4?50;9~fg`e290:6=4?{%d:>g`23Ahm56Fmf59lef<722wi5>m50;;94?6|,o31n85Gbg;8Lg`33-3i6<5f1183>>o693:17d?=:188m45=831b9o4?::k6a?6=3`236=44oc294?=hj80;66sm92f94?5=83:p(k75a09Kfc?<@kl?7)7m:d9j=0<722c2:7>5;nca>5<<uk3?=7>59;294~"a13h>7Eli9:Jab1=#1k0:7d??:188m47=831b=?4?::k27?6=3`?i6=44i4g94?=n010;66am0;29?jd62900qo7;2;297?6=8r.m57o>;I`e=>Nen=1/5o4j;h;6>5<<a0<1<75`ac83>>{e1=<1<7750;2x c?=j<1Cnk74Hcd7?!?e281b==4?::k25?6=3`;96=44i0194?=n=k0;66g:e;29?l>?2900co>50;9lf4<722wi59950;194?6|,o31m<5Gbg;8Lg`33-3i6h5f9483>>o>>3:17bom:188yg?3j3:157>50z&e=?d23Ahm56Fmf59'=g<63`;;6=44i0394?=n9;0;66g>3;29?l3e2900e8k50;9j<=<722ei<7>5;n`2>5<<uk3?o7>53;294~"a13k:7Eli9:Jab1=#1k0n7d7::188m<0=831dmo4?::a=06=8331<7>t$g;9f0=Ojo30Doh;;%;a>4=n990;66g>1;29?l752900e<=50;9j1g<722c>i7>5;h:;>5<<gk:1<75`b083>>{e1<;1<7=50;2x c?=i81Cnk74Hcd7?!?e2l1b584?::k:2?6=3fki6=44}c;61?6=13:1<v*i9;`6?Mda12Bij95+9c82?l772900e<?50;9j57<722c:?7>5;h7a>5<<a<o1<75f8983>>ie83:17bl>:188yg?2>3:1?7>50z&e=?g63Ahm56Fmf59'=g<b3`3>6=44i8494?=hik0;66sm94c94??=83:p(k75b49Kfc?<@kl?7)7m:09j55<722c:=7>5;h31>5<<a891<75f5c83>>o2m3:17d67:188kg6=831dn<4?::a=0d=8391<7>t$g;9e4=Ojo30Doh;;%;a>`=n1<0;66g66;29?jge2900qo7:f;29=?6=8r.m57l:;I`e=>Nen=1/5o4>;h33>5<<a8;1<75f1383>>o6;3:17d;m:188m0c=831b454?::ma4?6=3fh:6=44}c;54?6=;3:1<v*i9;c2?Mda12Bij95+9c8f?l?22900e4850;9leg<722wi5;:50;;94?6|,o31n85Gbg;8Lg`33-3i6<5f1183>>o693:17d?=:188m45=831b9o4?::k6a?6=3`236=44oc294?=hj80;66sm97794?5=83:p(k75a09Kfc?<@kl?7)7m:d9j=0<722c2:7>5;nca>5<<uk3=57>59;294~"a13h>7Eli9:Jab1=#1k0:7d??:188m47=831b=?4?::k27?6=3`?i6=44i4g94?=n010;66am0;29?jd62900qo79a;297?6=8r.m57o>;I`e=>Nen=1/5o4j;h;6>5<<a0<1<75`ac83>>{e1?o1<7750;2x c?=j<1Cnk74Hcd7?!?e281b==4?::k25?6=3`;96=44i0194?=n=k0;66g:e;29?l>?2900co>50;9lf4<722wi5;h50;194?6|,o31m<5Gbg;8Lg`33-3i6h5f9483>>o>>3:17bom:188yg?0;3:157>50z&e=?d23Ahm56Fmf59'=g<63`;;6=44i0394?=n9;0;66g>3;29?l3e2900e8k50;9j<=<722ei<7>5;n`2>5<<uk3<87>53;294~"a13k:7Eli9:Jab1=#1k0n7d7::188m<0=831dmo4?::a=2>=8331<7>t$g;9f0=Ojo30Doh;;%;a>4=n990;66g>1;29?l752900e<=50;9j1g<722c>i7>5;h:;>5<<gk:1<75`b083>>{e1>31<7=50;2x c?=i81Cnk74Hcd7?!?e2l1b584?::k:2?6=3fki6=44}c;4`?6=13:1<v*i9;`6?Mda12Bij95+9c82?l772900e<?50;9j57<722c:?7>5;h7a>5<<a<o1<75f8983>>ie83:17bl>:188yg?0m3:1?7>50z&e=?g63Ahm56Fmf59'=g<b3`3>6=44i8494?=hik0;66sm99094??=83:p(k75b49Kfc?<@kl?7)7m:09j55<722c:=7>5;h31>5<<a891<75f5c83>>o2m3:17d67:188kg6=831dn<4?::a==5=8391<7>t$g;9e4=Ojo30Doh;;%;a>`=n1<0;66g66;29?jge2900qo777;29=?6=8r.m57l:;I`e=>Nen=1/5o4>;h33>5<<a8;1<75f1383>>o6;3:17d;m:188m0c=831b454?::ma4?6=3fh:6=44}c;;<?6=;3:1<v*i9;c2?Mda12Bij95+9c8f?l?22900e4850;9leg<722wi55m50;;94?6|,o31n85Gbg;8Lg`33-3i6<5f1183>>o693:17d?=:188m45=831b9o4?::k6a?6=3`236=44oc294?=hj80;66sm99f94?5=83:p(k75a09Kfc?<@kl?7)7m:d9j=0<722c2:7>5;nca>5<<uk32=7>59;294~"a13h>7Eli9:Jab1=#1k0:7d??:188m47=831b=?4?::k27?6=3`?i6=44i4g94?=n010;66am0;29?jd62900qo762;297?6=8r.m57o>;I`e=>Nen=1/5o4j;h;6>5<<a0<1<75`ac83>>{e10<1<7750;2x c?=j<1Cnk74Hcd7?!?e281b==4?::k25?6=3`;96=44i0194?=n=k0;66g:e;29?l>?2900co>50;9lf4<722wi54950;194?6|,o31m<5Gbg;8Lg`33-3i6h5f9483>>o>>3:17bom:188yg?>j3:157>50z&e=?d23Ahm56Fmf59'=g<63`;;6=44i0394?=n9;0;66g>3;29?l3e2900e8k50;9j<=<722ei<7>5;n`2>5<<uk32o7>53;294~"a13k:7Eli9:Jab1=#1k0n7d7::188m<0=831dmo4?::a=d6=8331<7>t$g;9f0=Ojo30Doh;;%;a>4=n990;66g>1;29?l752900e<=50;9j1g<722c>i7>5;h:;>5<<gk:1<75`b083>>{e1h;1<7=50;2x c?=i81Cnk74Hcd7?!?e2l1b584?::k:2?6=3fki6=44}c;b1?6=13:1<v*i9;`6?Mda12Bij95+9c82?l772900e<?50;9j57<722c:?7>5;h7a>5<<a<o1<75f8983>>ie83:17bl>:188yg?f>3:1?7>50z&e=?g63Ahm56Fmf59'=g<b3`3>6=44i8494?=hik0;66sm9`c94??=83:p(k75b49Kfc?<@kl?7)7m:09j55<722c:=7>5;h31>5<<a891<75f5c83>>o2m3:17d67:188kg6=831dn<4?::a=dd=8391<7>t$g;9e4=Ojo30Doh;;%;a>`=n1<0;66g66;29?jge2900qo7nf;29=?6=8r.m57l:;I`e=>Nen=1/5o4>;h33>5<<a8;1<75f1383>>o6;3:17d;m:188m0c=831b454?::ma4?6=3fh:6=44}c;a4?6=;3:1<v*i9;c2?Mda12Bij95+9c8f?l?22900e4850;9leg<722wi5o:50;;94?6|,o31n85Gbg;8Lg`33-3i6<5f1183>>o693:17d?=:188m45=831b9o4?::k6a?6=3`236=44oc294?=hj80;66sm9c794?5=83:p(k75a09Kfc?<@kl?7)7m:d9j=0<722c2:7>5;nca>5<<uk3i57>59;294~"a13h>7Eli9:Jab1=#1k0:7d??:188m47=831b=?4?::k27?6=3`?i6=44i4g94?=n010;66am0;29?jd62900qo7ma;297?6=8r.m57o>;I`e=>Nen=1/5o4j;h;6>5<<a0<1<75`ac83>>{e1ko1<7750;2x c?=j<1Cnk74Hcd7?!?e281b==4?::k25?6=3`;96=44i0194?=n=k0;66g:e;29?l>?2900co>50;9lf4<722wi5oh50;194?6|,o31m<5Gbg;8Lg`33-3i6h5f9483>>o>>3:17bom:188yg?d;3:157>50z&e=?d23Ahm56Fmf59'=g<63`;;6=44i0394?=n9;0;66g>3;29?l3e2900e8k50;9j<=<722ei<7>5;n`2>5<<uk3h87>53;294~"a13k:7Eli9:Jab1=#1k0n7d7::188m<0=831dmo4?::a=f>=8331<7>t$g;9f0=Ojo30Doh;;%;a>4=n990;66g>1;29?l752900e<=50;9j1g<722c>i7>5;h:;>5<<gk:1<75`b083>>{e1j31<7=50;2x c?=i81Cnk74Hcd7?!?e2l1b584?::k:2?6=3fki6=44}c;``?6=13:1<v*i9;`6?Mda12Bij95+9c82?l772900e<?50;9j57<722c:?7>5;h7a>5<<a<o1<75f8983>>ie83:17bl>:188yg?dm3:1?7>50z&e=?g63Ahm56Fmf59'=g<b3`3>6=44i8494?=hik0;66sm9e094??=83:p(k75b49Kfc?<@kl?7)7m:09j55<722c:=7>5;h31>5<<a891<75f5c83>>o2m3:17d67:188kg6=831dn<4?::a=a5=8391<7>t$g;9e4=Ojo30Doh;;%;a>`=n1<0;66g66;29?jge2900qo7k7;29=?6=8r.m57l:;I`e=>Nen=1/5o4>;h33>5<<a8;1<75f1383>>o6;3:17d;m:188m0c=831b454?::ma4?6=3fh:6=44}c;g<?6=;3:1<v*i9;c2?Mda12Bij95+9c8f?l?22900e4850;9leg<722wi5k750;194?6|,o31m<5Gbg;8Lg`33-3i685f9483>>o>>3:17bom:188yg?a03:197>50z&e=?g43Ahm56Fmf59'=g<d3`3>6=44i8494?=n1>0;66g68;29?jge2900qo7ie;297?6=8r.m57o>;I`e=>Nen=1/5o4:;h;6>5<<a0<1<75`ac83>>{ej1o1<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk9>o7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th89i4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi?:<50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>9<:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=78;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<8883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm39g94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb2:e>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c1:4?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0=4<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a7<4=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f6?4290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg5><3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd41<0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e;0<1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:3<6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9247>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8544?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi?4o50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>7m:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=:e;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<5g83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm37294?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb242>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c156?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`026<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a732=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f602290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg51>3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4>>0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e;?21<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:<26=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9=m7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8:o4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi?;m50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>8k:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=9e;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<6g83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm36294?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb252>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c140?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`030<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a720=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f610290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg5003:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4?00;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e;>k1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:=i6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9<o7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8;i4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi?:k50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>9i:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=70;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<8083>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm39094?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb2:0>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c1;0?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0<0<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a7=0=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f6>0290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg5?i3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd40k0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e;1i1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:2o6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<ukhm<7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thij<4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722winhh50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vnl6::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qoo74;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygg??3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xdf0?0;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pln8883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sma9:94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{ei1h1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zjh2j6=4::183!`>21l0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;h`1>5<<gk:1<75rb`2`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}cc3f?6==3:1<v*i9;:e?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ci>7>5;n`3>5<<ukk;i7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thj<i4?:483>5}#n003j6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9jf7<722ei<7>5;|`b55<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::ae5`=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wim<<50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vnl?>:186>5<7s-l265h4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?ld52900co>50;9~fd73290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188ygg6;3:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qoo>6;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pln1483>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xdf910;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{ei8=1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sma0c94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb`3:>5<2290;w)h6:9d8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3`h96=44oc294?=zjh;h6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<ukk:n7>55;294~"a132m7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ka6?6=3fh;6=44}cc2a?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`b5a<72<0;6=u+f88;b>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831bn?4?::ma4?6=3thj>=4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wim<h50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::ae74=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~fd46290>6=4?{%d:>=`<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17dl=:188kg6=831vnl<;:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qoo=3;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygg5>3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xdf:<0;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pln2983>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sma3594?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{ei;k1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zjh826=4::183!`>21l0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;h`1>5<<gk:1<75rb`0`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}cc1f?6==3:1<v*i9;:e?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ci>7>5;n`3>5<<ukk9i7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thj>i4?:483>5}#n003j6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9jf7<722ei<7>5;|`b75<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::ae7`=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wim><50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vnl=>:186>5<7s-l265h4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?ld52900co>50;9~fd53290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188ygg4;3:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qoo<6;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pln3483>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xdf;10;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{ei:=1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sma2c94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb`1:>5<2290;w)h6:9d8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3`h96=44oc294?=zjh9h6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<ukk8n7>55;294~"a132m7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ka6?6=3fh;6=44}cc0a?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`b7a<72<0;6=u+f88;b>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831bn?4?::ma4?6=3thj8=4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wim>h50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::ae15=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~fd26290>6=4?{%d:>=`<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17dl=:188kg6=831vnl:::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qoo;4;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygg3?3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xdf<?0;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pln4883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sma5:94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{ei=h1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zjh>j6=4::183!`>21l0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;h`1>5<<gk:1<75rb`6g>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}cc7g?6==3:1<v*i9;:e?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ci>7>5;n`3>5<<ukk?j7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thj8h4?:483>5}#n003j6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9jf7<722ei<7>5;|`b14<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::ae06=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wim8=50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vnl;=:186>5<7s-l265h4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?ld52900co>50;9~fd32290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188ygg2<3:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qoo:7;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pln5783>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xdf=00;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{ei<21<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sma4`94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb`7b>5<2290;w)h6:9d8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3`h96=44oc294?=zjh?o6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<ukk>o7>55;294~"a132m7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ka6?6=3fh;6=44}cc6b?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`b1`<72<0;6=u+f88;b>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831bn?4?::ma4?6=3thj:<4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wim;>50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::ae35=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~fd05290>6=4?{%d:>=`<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17dl=:188kg6=831vnl8::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qoo94;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygg1?3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xdf>?0;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pln6883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sma7:94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{ei?h1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zjh<j6=4::183!`>21l0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;h`1>5<<gk:1<75rb`4g>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}cc5g?6==3:1<v*i9;:e?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ci>7>5;n`3>5<<ukk=j7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thj:h4?:483>5}#n003j6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9jf7<722ei<7>5;|`b34<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::ae26=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wim:=50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vnl9=:186>5<7s-l265h4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?ld52900co>50;9~fd12290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188ygg0<3:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qoo87;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pln7783>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xdf?00;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{ei>21<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sma6`94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb`5b>5<2290;w)h6:9d8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3`h96=44oc294?=zjh=o6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<ukk<o7>55;294~"a132m7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ka6?6=3fh;6=44}cc4b?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`b3`<72<0;6=u+f88;b>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831bn?4?::ma4?6=3thj4<4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wim5>50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::ae=5=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~fd>5290>6=4?{%d:>=`<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17dl=:188kg6=831vn4=i:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo7;4;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl64883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm95g94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb870>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c;6<?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`:1a<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a=34=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f<00290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg?1k3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd>?80;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e1><1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj0=i6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk33<7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th2484?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi55o50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn46i:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo764;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl69883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm98g94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb8c0>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c;b<?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`:ea<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a=g4=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f<d0290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg?ek3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd>k80;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e1j<1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj0ii6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk3o<7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th2h84?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi5io50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn4h9:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo7i7;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pln0583>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xdf890;684?:1y'b<<?k2Bij45Gbg68 <d=82c>57>5;h7a>5<<a<l1<75f8983>>ie83:17pln0083>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xd>no0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{ei991<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sma1094?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rbc:g>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c`:4?6==3:1<v*i9;c0?Mda12Bij95+9c80?l?22900e4850;9j=2<722c247>5;nca>5<<ukh2=7>55;294~"a13k87Eli9:Jab1=#1k0>;6g65;29?l?12900e4950;9j==<722ejn7>5;|`a=7<72<0;6=u+f88b7>Nen01Cnk:4$8`92>o>=3:17d79:188m<1=831b554?::mbf?6=3thi5>4?:483>5}#n00j?6Fmf89Kfc2<,0h186g65;29?l?12900e4950;9j==<722ejn7>5;|`a=1<72<0;6=u+f88b7>Nen01Cnk:4$8`96>o>=3:17d79:188m<1=831b554?::mbf?6=3thi584?:483>5}#n00j?6Fmf89Kfc2<,0h1>6g65;29?l?12900e4950;9j==<722ejn7>5;|`a=3<72<0;6=u+f88b7>Nen01Cnk:4$8`96>o>=3:17d79:188m<1=831b554?::mbf?6=3thi5:4?:483>5}#n00j?6Fmf89Kfc2<,0h1>6g65;29?l?12900e4950;9j==<722ejn7>5;|`a=<<72;0;6=u+f88:g>Nen01Cnk:4i8694?=hik0;66smbec94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rbc`5>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygde;3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbc`b>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygde?3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbc`f>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygdej3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbca1>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygden3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbca5>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygdd;3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbcab>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygdd?3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbcaf>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygddj3:187>50z&e=?g13Ahm56Fmf59j1a<722c357>5;h`0>5<<g0o1<75rbcf2>5<4290;w)h6:cd;?Mda12Bij95f5e83>>o>l3:17bom:188ygde=3:1>7>50z&e=?g73Ahm56Fmf59'=g<23`3>6=44o``94?=zjkh26=4=:183!`>2h:0Doh6;I`e0>">j3?0e4;50;9leg<722winoj50;094?6|,o31m=5Gbg;8Lg`33-3i685f9483>>ifj3:17plmc083>7<729q/j44n0:Jab<=Ojo>0(4l55:k:1?6=3fki6=44}c``1?6=:3:1<v*i9;c3?Mda12Bij95+9c86?l?22900cll50;9~fge>29096=4?{%d:>d6<@kl27Eli4:&:f?3<a0?1<75`ac83>>{ejjn1<7<50;2x c?=i91Cnk74Hcd7?!?e2<1b584?::mbf?6=3thih=4?:383>5}#n00j<6Fmf89Kfc2<,0h196g65;29?jge2900qolm4;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygde03:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qolmc;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygdd83:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qoll4;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygdd03:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qollc;291?6=8r.m576i;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>oe:3:17bl?:188ygddn3:197>50z&e=?>a3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66gm2;29?jd72900qo7j6;297?6=8r.m57li8:Jab<=Ojo>0e8j50;9j=a<722ejn7>5;|`:a6<72=0;6=u+f88b2>Nen01Cnk:4i4f94?=n000;66gm3;29?j?b2900qo7ja;297?6=8r.m57li8:Jab<=Ojo>0e8j50;9j=a<722ejn7>5;|`:a2<72=0;6=u+f88b2>Nen01Cnk:4i4f94?=n000;66gm3;29?j?b2900qo7je;297?6=8r.m57li8:Jab<=Ojo>0e8j50;9j=a<722ejn7>5;|`:ag<72=0;6=u+f88b2>Nen01Cnk:4i4f94?=n000;66gm3;29?j?b2900qo7i1;297?6=8r.m57li8:Jab<=Ojo>0e8j50;9j=a<722ejn7>5;|`:a0<72;0;6=u+f88b4>Nen01Cnk:4$8`91>o>=3:17bom:188yg?b13:1>7>50z&e=?g73Ahm56Fmf59'=g<23`3>6=44o``94?=zj0oo6=4=:183!`>2h:0Doh6;I`e0>">j3?0e4;50;9leg<722wi5k>50;094?6|,o31m=5Gbg;8Lg`33-3i685f9483>>ifj3:17pl6e583>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xd>m10;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pl6eb83>0<729q/j447f:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=nj;0;66am0;29?xd>mo0;684?:1y'b<<?n2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75fb383>>ie83:17pl61383>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb830>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`:4c<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f<77290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd>900;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj0;o6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg?5m3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd>:o0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e1;n1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj09=6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk38;7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th2?84?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi5<l50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a=4e=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi5<k50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a=4`=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi5<650;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn4?>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo7>6;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl61683>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm90694?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb836>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c;2e?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;a0<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f=c1290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd?m;0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj1o86=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th3in4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn5h?:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk3;=7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th2<?4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi5=>50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn4>6:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo7?a;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl60983>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm8dg94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e0ll1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm8g394?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e0o81<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm8d`94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb9g7>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c:f=?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;ad<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a<`1=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f=c?290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg>bl3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd?j10;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj1h26=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th3n84?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn5l9:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl7bg83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb9a0>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo6k4;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl7d483>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm8e194?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb9f`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c:g`?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;`g<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a<f7=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi4n<50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a<f2=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi4n;50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a<gc=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f=d0290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg>ek3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd?jm0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e0kk1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj1hi6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk2h<7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th34o4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn56l:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl78983>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb9::>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`;=7<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f=?129096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c:b3?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;e=<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a<d0=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f=ga290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg>e83:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd?il0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e00>1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm88794?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e00=1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm88:94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e00;1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj12j6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk23j7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th35=4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi45j50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn56j:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo663;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl75d83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb97e>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`;1g<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f=3d290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd?><0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj1<26=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg>0i3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd??k0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e0>31<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj1296=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk23?7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th34<4?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi4;950;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a<3>=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi4;o50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a<3d=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi4;:50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn5;k:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo692;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl76283>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm87294?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb942>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c:52?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;74<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f=55290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd?:l0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj18m6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th3?54?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn5=l:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk2?h7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th38h4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi49m50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn5;::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo6:6;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl75583>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm82c94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e0:h1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm82f94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e0:o1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm82594?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb913>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c:01?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;73<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a<65=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f=53290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg>413:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd?8=0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj1:>6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th3<<4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn5>=:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl70c83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb92e>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo6=0;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl72083>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm80d94?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb90;>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c:1=?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`;62<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a<5b=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi4=k50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a<46=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi4<?50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a<5g=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f=64290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg>703:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd?800;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e09<1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj1:<6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk2;o7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<h:4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn:j7:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl8d583>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb6f6>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`4``<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f2c529096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c5e7?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`4b1<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a3c4=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f2`e290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg1ak3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd0nh0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e?l:1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm7d394?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e?l91<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm7d694?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e?mn1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj>n=6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk=on7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<hn4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi;i750;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn:jn:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo9kf;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl8a`83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb6ca>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`4e2<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f2g?290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd0j80;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj>h>6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg1d>3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd0k>0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e?j?1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj>in6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk=hj7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<oi4?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi;o=50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a3g2=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi;o850;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a3g1=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi;o>50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn:o6:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo9ne;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl8ag83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm7`a94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb6cg>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c5a6?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`43a<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f21b290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd0?h0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj>=i6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th<494?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn:67:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk=257>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<5l4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi;4650;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn:o>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo9n2;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl8a183>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm79494?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e?1=1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm79;94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e?1k1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm79194?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb65`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c5;5?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`4<7<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a32`=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f2>7290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg1?=3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd0=90;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj>?:6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th<8i4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn::j:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl85683>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb67a>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo99c;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl86e83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm77`94?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb657>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c541?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`436<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a30?=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi;8o50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a30e=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi;8j50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a300=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f22a290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg12<3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd0=<0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e?<81<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj>?86=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk=>47>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<>>4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn:<;:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl82183>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb602>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`46d<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f24b29096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c50b?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`405<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a36c=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f220290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg1303:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd0<?0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e?;i1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm73f94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e?;l1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm72294?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e?;31<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj>896=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk=9;7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<>54?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi;?;50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn:<9:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo9=b;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl9f783>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb7d4>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`5b6<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f3`3290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd1nm0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj>::6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg16:3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd09:0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e?8;1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj>;j6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk=:n7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th<=44?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi:kh50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a356=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi;=<50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a355=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi:km50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn;h::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo8ia;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl9fc83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm6g:94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb7d:>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c4ea?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`5g<<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f3ef290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd1k?0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj?i<6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th=h=4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn;j;:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk<n97>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th=i;4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi:h:50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn;kk:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo8je;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl9eb83>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm6e094?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e>m91<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm6e794?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e>m<1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm6bd94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb7a;>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c4``?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`5g`<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a2fd=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f3ed290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg0c93:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd11j0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj?3o6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th=544?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn;7n:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl9a283>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb7c4>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo8m8;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl9b883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm6c594?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb7a3>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c4`5?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`5fc<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a2d3=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi:l850;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a2d>=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi:l750;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a2d4=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f3?e290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg0f83:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd1i80;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e>0o1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj?3m6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk<j87>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th=:k4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn;9?:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl96b83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb74g>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`533<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f31f29096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c4;f?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`5<f<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a2=g=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f3?4290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg0><3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd11;0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e>>21<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm66;94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e>>h1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm66a94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e>>?1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj?<n6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk<<?7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th=;94?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi::?50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn;9=:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo887;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl94383>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb760>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`57c<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f327290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd1<00;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj?>o6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg02m3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd1=o0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e><n1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj?<=6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk<=;7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th=:84?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi:9l50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a21e=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi:9k50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a21`=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi:9650;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn;:>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo8;6;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl94683>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm65694?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb766>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c47e?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`550<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f371290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd19;0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj?;86=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th==n4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn;<?:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk<8=7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th=??4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi:>>50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn;=6:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo8<a;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl93983>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm60g94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e>8l1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm63394?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e>;81<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm60`94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb737>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c42=?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`55d<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a241=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f37?290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg06l3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2m10;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj<o26=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th>i84?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn8k9:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl:eg83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb4d0>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo8?4;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl90483>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm61194?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb72`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c43`?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`54g<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a1c7=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi9k<50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a1c2=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi9k;50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a1`c=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f0c0290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg3bk3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2mm0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e=lk1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj<oi6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk?m<7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th>no4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn8ll:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl:b983>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb4`:>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`6g7<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f0e129096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c7g3?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`6`=<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a1a0=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f0ba290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg3b83:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2ll0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e=j>1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm5b794?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e=j=1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm5b:94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e=j;1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj<hj6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk?ij7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th>o=4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi9oj50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn8lj:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo;l3;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl:8d83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb4:e>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`6<g<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f0>d290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd21<0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj<326=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg3fi3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2ik0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e=h31<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj<h96=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk?i?7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th>n<4?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi94950;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a1<>=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi94o50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a1<d=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi94:50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn86k:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo;62;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl:9283>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm58294?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb4;2>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c7:2?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`624<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f005290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd2=l0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj<?m6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th>:54?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn88l:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk?<h7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th>;h4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi9:m50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn86::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo;76;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl:8583>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm57c94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e=?h1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm57f94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e=?o1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm57594?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb443>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c751?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`623<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a135=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f003290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg3113:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2;=0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj<9>6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th>?<4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn8==:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl:3c83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb41e>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo;:0;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl:5083>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm55d94?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb47;>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c76=?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`612<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a16b=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi9>k50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a116=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi99?50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a16g=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f054290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg3403:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2;00;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e=:<1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj<9<6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk?8o7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th><:4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn8>7:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl:0583>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb426>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`64`<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f07529096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c717?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`661<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a174=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f04e290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg35k3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd2:h0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e=8:1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm50394?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e=891<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm50694?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e=9n1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj<:=6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk?;n7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th><n4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi9=750;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn8>n:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo;?f;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;d`83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb5fa>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`7`2<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f1b?290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd3m80;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj=o>6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg2a>3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd3n>0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e<o?1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj=ln6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk>mj7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?ji4?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi8h=50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a0`2=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi8h850;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a0`1=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi8h>50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn9j6:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo:ke;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;dg83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm4ea94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb5fg>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c6f6?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`7ea<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f1gb290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd3ih0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj=ki6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th?n94?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn9l7:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk>h57>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?ol4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi8n650;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn9j>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo:k2;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;d183>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm4c494?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e<k=1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm4c;94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e<kk1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm4c194?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb5c`>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c6a5?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`7f7<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a0d`=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f1d7290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg2e=3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd3090;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj=2:6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th?;i4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn99j:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl;8683>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb5:a>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo:6c;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;9e83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm48`94?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb5c7>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c6b1?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`7e6<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a0=?=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi85o50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a0=e=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi85j50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a0=0=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f11a290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg2?<3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd30<0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e<181<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj=286=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk>347>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?9>4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn9;;:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl;5183>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb572>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`71d<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f13b29096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c65b?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`735<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a03c=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f110290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg2003:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd3??0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e<<i1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm44f94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e<<l1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm47294?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e<<31<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj=?96=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk>>;7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?954?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi88;50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn9;9:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo::b;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;2783>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb504>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`766<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f143290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd3:m0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj=9:6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg23:3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd3<:0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e<=;1<7:50;2x c?=0l1Cnk74Hcd7?!?e291b944?::k;<?6=3`h96=44oc294?=zj=>j6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk>?n7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?844?:583>5}#n003i6Fmf89Kfc2<,0h1<6g:9;29?l>?2900eo<50;9lf5<722wi8?h50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a066=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi8><50;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a065=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi8?m50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn9<::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo:=a;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;2c83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm43:94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb50:>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c61a?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0b<<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f6`f290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd4n?0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj:l<6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th?<=4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn9>;:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk>:97>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th?=;4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi8<:50;694?6|,o314h5Gbg;8Lg`33-3i6=5f5883>>o?03:17dl=:188kg6=831vn9?k:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo:>e;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl;1b83>1<729q/j447e:Jab<=Ojo>0(4l50:k6=?6=3`236=44ic094?=hj90;66sm41094?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e<991<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm41794?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e<9<1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm3gd94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb2d;>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c1e`?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0b`<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a7cd=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f6`d290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg2793:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4kj0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj:io6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th8o44?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn>mn:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl<d283>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb2f4>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo=j8;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<e883>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm3d594?2=83:p(k758d9Kfc?<@kl?7)7m:19j1<<722c347>5;h`1>5<<gk:1<75rb2d3>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c1e5?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0ac<72=0;6=u+f88;a>Nen01Cnk:4$8`94>o213:17d67:188mg4=831dn=4?::a7a3=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi?i850;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a7a>=83?1<7>t$g;9<c=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900eo<50;9lf5<722wi?i750;794?6|,o314k5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188mg4=831dn=4?::a7a4=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f6ee290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg5c83:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4l80;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e;jo1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:im6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9o87>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th85k4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn>o?:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl<9b83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb2;g>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`0e3<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f6gf29096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c1af?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`0ff<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a7gg=83>1<7>t$g;9<`=Ojo30Doh;;%;a>5=n=00;66g78;29?ld52900co>50;9~f6e4290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg5d<3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4k;0;694?:1y'b<<?m2Bij45Gbg68 <d=82c>57>5;h:;>5<<ak81<75`b183>>{e;h21<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm3`;94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e;hh1<7;50;2x c?=0o1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44ic094?=hj90;66sm3`a94?3=83:p(k758g9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<ak81<75`b183>>{e;h?1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:3n6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9j?7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8m94?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi?l?50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>o=:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=n7;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl=c583>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb3a6>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`1ga<72;0;6=u+f88:g>Nen01Cnk:4i8694?=hik0;66sm2bc94?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c0`f?6==3:1<v*i9;:`?Mda12Bij95+9c83?l3>2900e8l50;9j1c<722c347>5;n`3>5<<uk8ho7>55;294~"a132h7Eli9:Jab1=#1k0;7d;6:188m0d=831b9k4?::k;<?6=3fh;6=44}c0`3?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`1g3<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a6f>=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f7e>290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg4e93:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e:k81<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk8im7>52;294~"a133h7Eli9:Jab1=n1=0;66anb;29?xd5j>0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj;h36=4::183!`>21i0Doh6;I`e0>">j3:0e8750;9j1g<722c>j7>5;h:;>5<<gk:1<75rb3`:>5<2290;w)h6:9a8Lg`>3Ahm86*6b;28m0?=831b9o4?::k6b?6=3`236=44oc294?=zj;h?6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk8i?7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th9n84?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi>o850;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn?6m:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl=8b83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb3;7>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo<61;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm28094?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e:091<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm29g94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb3:g>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c0;b?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`1=5<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a62>=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg4013:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e:1;1<7<50;2x c?=1j1Cnk74Hcd7?l?32900cll50;9~f71b290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd5?o0;684?:1y'b<<?k2Bij45Gbg68 <d=82c>57>5;h7a>5<<a<l1<75f8983>>ie83:17pl=8183>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xd5?k0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e:>k1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj;=h6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk8<h7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th9:84?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn?89:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl=6d83>7<729q/j446c:Jab<=Ojo>0e4:50;9leg<722wi>;l50;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo<9c;291?6=8r.m576l;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f5g83>>o?03:17bl?:188yg41l3:197>50z&e=?>d3Ahm56Fmf59'=g<73`?26=44i4`94?=n=o0;66g78;29?jd72900qo<98;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl=6683>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm27;94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb34b>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c066?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a605=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg42j3:1>7>50z&e=??d3Ahm56Fmf59j=1<722ejn7>5;|`11=<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f73>290>6=4?{%d:>=e<@kl27Eli4:&:f?6<a<31<75f5c83>>o2n3:17d67:188kg6=831vn?;n:186>5<7s-l265m4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g:f;29?l>?2900co>50;9~f732290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg42<3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd5=?0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e:<=1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj;9m6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th98=4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn?:7:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk8?97>54;294~"a13k97Eli9:Jab1=#1k0>m6g65;29?l?12900e4950;9leg<722wi>9850;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a611=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi>9<50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn?:>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo<;3;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl=4583>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm23a94?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c01`?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a663=8381<7>t$g;9=f=Ojo30Doh;;h;7>5<<ghh1<75rb311>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`176<72<0;6=u+f88;g>Nen01Cnk:4$8`94>o213:17d;m:188m0`=831b454?::ma4?6=3th9?94?:483>5}#n003o6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e8h50;9j<=<722ei<7>5;|`16c<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a67c=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f757290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg4493:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd5900;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj;;j6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th9>?4?:383>5}#n002o6Fmf89Kfc2<a0>1<75`ac83>>{e:8l1<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk89<7>55;294~"a132h7Eli9:Jab1=#1k0;7d;6:188m0d=831b9k4?::k;<?6=3fh;6=44}c015?6==3:1<v*i9;:`?Mda12Bij95+9c83?l3>2900e8l50;9j1c<722c347>5;n`3>5<<uk8:o7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th9=o4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi><j50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn??j:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo<?6;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm21594?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c03b?6=:3:1<v*i9;;`?Mda12Bij95f9583>>ifj3:17pl=0b83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb32g>5<2290;w)h6:9a8Lg`>3Ahm86*6b;28m0?=831b9o4?::k6b?6=3`236=44oc294?=zj;:n6=4::183!`>21i0Doh6;I`e0>">j3:0e8750;9j1g<722c>j7>5;h:;>5<<gk:1<75rb32:>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c03<?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`14d<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a65d=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f4`4290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd6n=0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj8lh6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg7a13:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e9ok1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm1g`94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e9o<1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj8l>6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk;m;7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th:j54?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi=h>50;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo?j1;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm1d;94?4=83:p(k759b9Kfc?<@kl?7d7;:188kdd=831vn<k9:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl>e683>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xd6m10;684?:1y'b<<?k2Bij45Gbg68 <d=82c>57>5;h7a>5<<a<l1<75f8983>>ie83:17pl>e283>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm1d094?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb0g7>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c3f1?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`2fd<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f4de290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd6k:0;6?4?:1y'b<<>k2Bij45Gbg68m<2=831dmo4?::a5f6=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg7d93:197>50z&e=?>d3Ahm56Fmf59'=g<73`?26=44i4`94?=n=o0;66g78;29?jd72900qo?l2;291?6=8r.m576l;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f5g83>>o?03:17bl?:188yg7el3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd6jj0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e9ko1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj8hm6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk;j;7>54;294~"a13k97Eli9:Jab1=#1k0>m6g65;29?l?12900e4950;9leg<722wi=l650;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo?m0;296?6=8r.m577l;I`e=>Nen=1b594?::mbf?6=3th:mi4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn<oj:186>5<7s-l265m4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g:f;29?l>?2900co>50;9~f4ga290>6=4?{%d:>=e<@kl27Eli4:&:f?6<a<31<75f5c83>>o2n3:17d67:188kg6=831vn<on:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo?n9;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl>ac83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm1`a94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb0;7>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`2=0<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f4?c29096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c3:e?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a5<d=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi=4m50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a5<1=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f4?1290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg7>03:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd6100;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e91;1<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk;3>7>54;294~"a13k97Eli9:Jab1=#1k0>m6g65;29?l?12900e4950;9leg<722wi=5o50;094?6|,o315n5Gbg;8Lg`33`3?6=44o``94?=zj82<6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th:454?:483>5}#n003o6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e8h50;9j<=<722ei<7>5;|`2<<<72<0;6=u+f88;g>Nen01Cnk:4$8`94>o213:17d;m:188m0`=831b454?::ma4?6=3th:494?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi=5=50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn<6::187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo?76;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl>6d83>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb04e>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`232<72;0;6=u+f88:g>Nen01Cnk:4i8694?=hik0;66sm16694?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c341?6==3:1<v*i9;:`?Mda12Bij95+9c83?l3>2900e8l50;9j1c<722c347>5;n`3>5<<uk;<:7>55;294~"a132h7Eli9:Jab1=#1k0;7d;6:188m0d=831b9k4?::k;<?6=3fh;6=44}c345?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`235<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a524=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f414290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg72j3:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e9<i1<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk;=87>52;294~"a133h7Eli9:Jab1=n1=0;66anb;29?xd6>80;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj8<96=4::183!`>21i0Doh6;I`e0>">j3:0e8750;9j1g<722c>j7>5;h:;>5<<gk:1<75rb040>5<2290;w)h6:9a8Lg`>3Ahm86*6b;28m0?=831b9o4?::k6b?6=3`236=44oc294?=zj8?n6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk;>h7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th:9k4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi=;>50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn<:7:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl>4883>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb072>5<5290;w)h6:8a8Lg`>3Ahm86g64;29?jge2900qo?;e;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm15d94?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e9<:1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm15`94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb06b>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c37g?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`20a<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a563=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg74>3:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e9:o1<7<50;2x c?=1j1Cnk74Hcd7?l?32900cll50;9~f45e290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd6;j0;684?:1y'b<<?k2Bij45Gbg68 <d=82c>57>5;h7a>5<<a<l1<75f8983>>ie83:17pl>3e83>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xd6;10;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e9:=1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj8926=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk;8m7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th:>?4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn<<<:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl>2c83>7<729q/j446c:Jab<=Ojo>0e4:50;9leg<722wi=?650;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo?=9;291?6=8r.m576l;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f5g83>>o?03:17bl?:188yg75i3:197>50z&e=?>d3Ahm56Fmf59'=g<73`?26=44i4`94?=n=o0;66g78;29?jd72900qo?=5;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl>2583>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm13494?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb004>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c33b?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a546=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg7603:1>7>50z&e=??d3Ahm56Fmf59j=1<722ejn7>5;|`250<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f471290>6=4?{%d:>=e<@kl27Eli4:&:f?6<a<31<75f5c83>>o2n3:17d67:188kg6=831vn<?8:186>5<7s-l265m4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g:f;29?l>?2900co>50;9~f475290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg7693:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd69:0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e98>1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj:>26=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th88l4?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn>;=:181>5<7s-l264m4Hcd:?Mda<2c287>5;nca>5<<uk9?j7>54;294~"a13k97Eli9:Jab1=#1k0>m6g65;29?l?12900e4950;9leg<722wi?8>50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a707=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi?9m50;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn>:m:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=;d;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl<4d83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm32494?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c103?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a76`=8381<7>t$g;9=f=Ojo30Doh;;h;7>5<<ghh1<75rb21`>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`07a<72<0;6=u+f88;g>Nen01Cnk:4$8`94>o213:17d;m:188m0`=831b454?::ma4?6=3th8?h4?:483>5}#n003o6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e8h50;9j<=<722ei<7>5;|`07<<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a76>=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f65f290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg54j3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd4::0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj:8?6=4;:183!`>2h80Doh6;I`e0>">j3?j7d7::188m<0=831b5:4?::mbf?6=3th8>n4?:383>5}#n002o6Fmf89Kfc2<a0>1<75`ac83>>{e;;31<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk99m7>55;294~"a132h7Eli9:Jab1=#1k0;7d;6:188m0d=831b9k4?::k;<?6=3fh;6=44}c11f?6==3:1<v*i9;:`?Mda12Bij95+9c83?l3>2900e8l50;9j1c<722c347>5;n`3>5<<uk99:7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8>84?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi??950;694?6|,o314i5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d67:188kg6=831vn><7:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo=>0;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm30394?2=83:p(k75a39Kfc?<@kl?7)7m:4c8m<3=831b5;4?::k:3?6=3fki6=44}c12=?6=:3:1<v*i9;;`?Mda12Bij95f9583>>ifj3:17pl<1783>1<729q/j44n2:Jab<=Ojo>0(4l55`9j=0<722c2:7>5;h;4>5<<ghh1<75rb234>5<2290;w)h6:9a8Lg`>3Ahm86*6b;28m0?=831b9o4?::k6b?6=3`236=44oc294?=zj:;36=4::183!`>21i0Doh6;I`e0>">j3:0e8750;9j1g<722c>j7>5;h:;>5<<gk:1<75rb230>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c126?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`051<72=0;6=u+f88;`>Nen01Cnk:4$8`94>o213:17d;m:188m=>=831dn=4?::a743=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f7`c290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd5nl0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj::=6=4=:183!`>20i0Doh6;I`e0>o><3:17bom:188yg57;3:187>50z&e=?g53Ahm56Fmf59'=g<2i2c297>5;h;5>5<<a0=1<75`ac83>>{e;9>1<7;50;2x c?=0j1Cnk74Hcd7?!?e291b944?::k6f?6=3`?m6=44i9:94?=hj90;66sm31794?3=83:p(k758b9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h7e>5<<a121<75`b183>>{e;9:1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj;lm6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk9;=7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3th8<?4?:583>5}#n003h6Fmf89Kfc2<,0h1<6g:9;29?l3e2900e5650;9lf5<722wi>ho50;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo<jb;290?6=8r.m57o=;I`e=>Nen=1/5o4:a:k:1?6=3`3=6=44i8594?=hik0;66sm2g194?4=83:p(k759b9Kfc?<@kl?7d7;:188kdd=831vn?h?:187>5<7s-l26l<4Hcd:?Mda<2.2n7;n;h;6>5<<a0<1<75f9683>>ifj3:17pl=f083>0<729q/j447c:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i4d94?=n010;66am0;29?xd5n;0;684?:1y'b<<?k2Bij45Gbg68 <d=82c>57>5;h7a>5<<a<l1<75f8983>>ie83:17pl=ee83>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm2da94?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb3gf>5<3290;w)h6:9f8Lg`>3Ahm86*6b;28m0?=831b9o4?::k;<?6=3fh;6=44}c0fb?6=<3:1<v*i9;:g?Mda12Bij95+9c83?l3>2900e8l50;9j<=<722ei<7>5;|`1`2<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f7b?290?6=4?{%d:>d4<@kl27Eli4:&:f?3f3`3>6=44i8494?=n1>0;66anb;29?xd5m90;6?4?:1y'b<<>k2Bij45Gbg68m<2=831dmo4?::a6ab=83>1<7>t$g;9e7=Ojo30Doh;;%;a>0g<a0?1<75f9783>>o>?3:17bom:188yg4cm3:197>50z&e=?>d3Ahm56Fmf59'=g<73`?26=44i4`94?=n=o0;66g78;29?jd72900qo<kf;291?6=8r.m576l;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f5g83>>o?03:17bl?:188yg4ci3:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd5l00;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{e:mh1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj;nh6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk82i7>54;294~"a13k97Eli9:Jab1=#1k0>m6g65;29?l?12900e4950;9leg<722wi>4h50;694?6|,o31m?5Gbg;8Lg`33-3i68o4i8794?=n1?0;66g67;29?jge2900qo<n7;296?6=8r.m577l;I`e=>Nen=1b594?::mbf?6=3th9m94?:583>5}#n00j>6Fmf89Kfc2<,0h19l5f9483>>o>>3:17d78:188kdd=831vn?o::186>5<7s-l265m4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g:f;29?l>?2900co>50;9~f7g1290>6=4?{%d:>=e<@kl27Eli4:&:f?6<a<31<75f5c83>>o2n3:17d67:188kg6=831vn?o>:187>5<7s-l265j4Hcd:?Mda<2.2n7>4i4;94?=n=k0;66g78;29?jd72900qo<n0;290?6=8r.m576k;I`e=>Nen=1/5o4?;h7:>5<<a<h1<75f8983>>ie83:17pl=a383>1<729q/j447d:Jab<=Ojo>0(4l50:k6=?6=3`?i6=44i9:94?=hj90;66sm2`194?2=83:p(k758e9Kfc?<@kl?7)7m:19j1<<722c>n7>5;h:;>5<<gk:1<75rb0ag>5<3290;w)h6:`08Lg`>3Ahm86*6b;7b?l?22900e4850;9j=2<722ejn7>5;|`2g`<72=0;6=u+f88b6>Nen01Cnk:4$8`91d=n1<0;66g66;29?l?02900cll50;9~f4b129096=4?{%d:><e<@kl27Eli4:k:0?6=3fki6=44}c3g7?6=<3:1<v*i9;c1?Mda12Bij95+9c86e>o>=3:17d79:188m<1=831dmo4?::a5a2=83?1<7>t$g;9<f=Ojo30Doh;;%;a>5=n=00;66g:b;29?l3a2900e5650;9lf5<722wi=i;50;794?6|,o314n5Gbg;8Lg`33-3i6=5f5883>>o2j3:17d;i:188m=>=831dn=4?::a5a6=83>1<7>t$g;9<a=Ojo30Doh;;%;a>5=n=00;66g:b;29?l>?2900co>50;9~f4ea290?6=4?{%d:>=b<@kl27Eli4:&:f?6<a<31<75f5c83>>o?03:17bl?:188yg7c93:187>50z&e=?>c3Ahm56Fmf59'=g<73`?26=44i4`94?=n010;66am0;29?xd6l;0;694?:1y'b<<?l2Bij45Gbg68 <d=82c>57>5;h7a>5<<a121<75`b183>>{enj0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zjon1<7:50;2x c?=i;1Cnk74Hcd7?!?e2<k0e4;50;9j=3<722c2;7>5;nca>5<<uk;;97>52;294~"a133h7Eli9:Jab1=n1=0;66anb;29?xd68;0;694?:1y'b<<f:2Bij45Gbg68 <d==h1b584?::k:2?6=3`3<6=44o``94?=zj8:86=4::183!`>21i0Doh6;I`e0>">j3:0e8750;9j1g<722c>j7>5;h:;>5<<gk:1<75rb027>5<2290;w)h6:9a8Lg`>3Ahm86*6b;28m0?=831b9o4?::k6b?6=3`236=44oc294?=zjol1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zjoo1<7:50;2x c?=0m1Cnk74Hcd7?!?e291b944?::k6f?6=3`236=44oc294?=zj8:;6=4;:183!`>21n0Doh6;I`e0>">j3:0e8750;9j1g<722c347>5;n`3>5<<uk;;=7>54;294~"a132o7Eli9:Jab1=#1k0;7d;6:188m0d=831b454?::ma4?6=3thim=4?:683>5}#n00j96Fmf89Kfc2<,0h1h6g65;29?l?12900e4950;9j==<722c257>5;h;b>5<<ghh1<75rbcc0>5<0290;w)h6:`78Lg`>3Ahm86*6b;f8m<3=831b5;4?::k:3?6=3`336=44i8;94?=n1h0;66anb;29?xde1h0;6:4?:1y'b<<f=2Bij45Gbg68 <d=l2c297>5;h;5>5<<a0=1<75f9983>>o>13:17d7n:188kdd=831vno7m:184>5<7s-l26l;4Hcd:?Mda<2.2n7j4i8794?=n1?0;66g67;29?l??2900e4750;9j=d<722ejn7>5;|`a=`<72?0;6=u+f88b0>Nen01Cnk:4$8`9=5=n1<0;66g66;29?l?02900e4650;9j=<<722ejn7>5;|`a=c<72>0;6=u+f88b1>Nen01Cnk:4$8`9<g=n1<0;66g66;29?l?02900e4650;9j=<<722c2m7>5;nca>5<<ukhj=7>57;294~"a13k>7Eli9:Jab1=#1k03n6g65;29?l?12900e4950;9j==<722c257>5;h;b>5<<ghh1<75rbcc1>5<1290;w)h6:`68Lg`>3Ahm86*6b;37?l?22900e4850;9j=2<722c247>5;h;:>5<<ghh1<75rbc;g>5<1290;w)h6:`68Lg`>3Ahm86*6b;d8m<3=831b5;4?::k:3?6=3`336=44i8;94?=hik0;66smb8a94?1=83:p(k75a49Kfc?<@kl?7)7m:e9j=0<722c2:7>5;h;4>5<<a021<75f9883>>o>i3:17bom:188yv72290?wS?:;<330?3>34;;>77:;<331??33ty::7>54z\22>;69>0>563>148:1>;6910286s|1683>1}Y9>16=?o5589>57>=1<16=?l5959~w4>=83>pR<64=01g>0?<589i64;4=01f><2<uz;26=4;{_3:?87283?270?;e;;6?872933?7p}>a;290~X6i27::>4:9:?224<>=27::9464:p5g<72=qU=o5216491<=:9>>158521659=1=z{8i1<7:t^0a894>>2<301<68:87894>f20>0q~?k:187[7c34;2o7;6;<3:e??234;2h77;;|q2a?6=<rT:i63>ag86=>;6im02963>b18:0>{t9o0;69uQ1g9>5f4==016=n>5949>5f5=1=1v?>50;6xZ76<58n>6874=0f0><3<58n=64:4}r02>5<3sW8:70?j8;7:?87b>33>70?j9;;7?xu5:3:18vP=2:?2bg<2127:j4465:?2bf<><2wx>>4?:5y]66=::9o1945221a9=0=::9l1595rs3694?2|V;>01?<>:4;8977a20?01?<=:868yv42290?wS<:;<000?3>3488>77:;<001??33ty9:7>54z\12>;5<>0>563=448:1>;5<10286s|2683>1}Y:>16>8o5589>60>=1<16>8l5959~w7>=83>pR?64=34g>0?<5;<i64;4=34f><2<uz826=4;{_0:?84?83?270<8e;;6?84?933?7p}=a;290~X5i2795>4:9:?1=4<>=27959464:p6g<72=qU>o522`491<=::h>158522`59=1=z{;i1<7:t^3a897d>2<301?l8:87897df20>0q~<j:187[4b348ho7;6;<0`e??2348hh77;;|q1b?6=<rT9j63=dg86=>;5lm02963=e18:0>{t;90;69uQ319>6c4==016>k>5949>6c5=1=1v>?50;6xZ67<5::>6874=220><3<5::=64:4}r11>5<3sW9970=>8;7:?856>33>70=>9;;7?xu4;3:18vP<3:?06g<21278>4465:?06f<><2wx?94?:5y]71=:;:o1945232a9=0=:;:l1595rs2794?2|V:?01>;>:4;8962a20?01>;=:868yv512909wS=9;<16`?d73ty8;7>52z\03>;4=o0i<6s|3983>7}Y;116?;?5b19~w6?=838pR>74=240>g6<uz9j6=4={_1b?851=3h;7p}<b;296~X4j278::4m0:p7f<72;qU?n5237;9f5=z{:n1<7<t^2f8960e2k:0q~=j:181[5b349=h7l?;|q0b?6=:rT8j63<6g8a4>{t<90;6?uQ419>727=j91v9?50;0xZ17<5:=86o>4}r61>5<5sW>970=85;`3?xu3;3:1>vP;3:?032<e82wx894?:3y]01=:;>31n=5rs5794?4|V=?01>9m:c28yv212909wS:9;<14`?d73ty?;7>52z\73>;4?o0i<6s|4983>7}Y<116?5?5b19~w1?=838pR974=2:0>g6<uz>j6=4={_6b?85?=3h;7p};b;296~X3j2784:4m0:p0f<72;qU8n5239;9f5=z{=n1<7<t^5f896>e2k:0q~:i:181[2a3493h7l?;|q64?6=:rT><63<8g8a4>{t=80;6?uQ509>7<7=j91v8<50;0xZ04<5:386o>4}r70>5<5sW?870=65;`3?xu2<3:1>vP:4:?0=2<e82wx984?:3y]10=:;031n=5rs4494?4|V<<01>7m:c28yv3b290::nuQ5d9>e56==016m=?5589>=c`==016m==5589>e54==0165k85589>=c1==0165io5589>=a3==0165i>5589>=fd==0165n85589>=f7==0165om5589>=g1==0165o<5589>=db==0165l65589>=d5==01654k5589>=<?==01654:5589>==`==01655o5589>==3==01655>5589>=2d==0165:85589>=27==0165;m5589>=31==0165;<5589>=0b==0165865589>=05==01659k5589>=1?==01659:5589>=6`==016m9?5589>e6`==016m>j5589>e6d==016m>75589>e61==016m>;5589>e65==016m>?5589>e7`==016m?j5589>e7d==016m?75589>e71==016m?;5589>e75==016m??5589>e4`==016m<j5589>e4d==016m<75589>e41==016m<;5589>e45==016m<?5589>e5`==016m=j5589>e5d==016m5o5589>e=>==016m585589>e=2==0165hh5589>=`e==0165h65589>=`2==0165<65589>=4`==0165<k5589>=60==0165>95589>=63==0165?k5589>=7`==0165?j5589><`d==0164k<5589><c7==0165=75589>=5g==0165=65589>=57==0165=<5589>=56==0164ok5589><f3==0164n:5589><ae==0164ij5589><ad==0164i:5589><a3==0164i=5589><<7==0164465589><<1==0164lh5589><g6==0164lk5589><d1==0164l65589><d0==0164;:5589><3d==0164;o5589><=4==01645=5589><=7==0164:o5589><2d==0164:75589><61==0164>k5589><6b==01648;5589><00==01648:5589><1b==01649k5589><1e==0164=o5589><47==0164<>5589><7>==0164?75589><71==0164?>5589><77==0164<h5589>3ab==016;h:5589>3`5==016;kl5589>3ce==016;ko5589>3c5==016;k:5589>3c4==016;o>5589>3g1==016;o85589>3fc==016;nh5589>3fb==016;n85589>3f1==016;n;5589>3=5==016;5o5589>3=?==016;l?5589>3d4==016;l>5589>3<?==016;4o5589>3<>==016;885589>30b==016;8m5589>322==016;:;5589>325==016;;m5589>33b==016;;l5589>37?==016;>>5589>37`==016;995589>31>==016;985589>36`==016;9>5589>36c==016:km5589>355==016;=<5589>34g==016;<l5589>34?==016;<<5589>345==016;<?5589>2f`==016:i85589>2a3==016:hj5589>2`c==016:hm5589>2`3==016:h85589>2`2==016:l<5589>2d?==016:l65589>2f6==016:n?5589>2g`==016:o65589>2g?==016:o95589>223==016::m5589>22d==016:4=5589>2<2==016:4<5589>2=d==016:5m5589>2=g==016:965589>21`==016:9k5589>230==016:;95589>233==016:8k5589>20`==016:8j5589>24d==016:?<5589>277==016:>75589>26g==016:>65589>267==016:><5589>266==0169hk5589>1c3==0169k:5589>25e==016:=j5589>25d==016:=:5589>253==016:==5589>1f7==0169n65589>1f1==0169ih5589>1`6==0169ik5589>1a1==0169i65589>1a0==01694:5589>1<d==01694o5589>1g4==0169o=5589>1g7==0169lo5589>1dd==0169l75589>131==0169;k5589>13b==01695;5589>1=0==01695:5589>12b==0169:k5589>12e==0169>o5589>117==01699>5589>10>==0169875589>101==01698>5589>107==01699h5589>15b==0169<:5589>145==0169?l5589>17e==0169?o5589>175==0169?:5589>174==0168h>5589>0`1==0168h85589>0cc==0168kh5589>0cb==0168k85589>0c1==0168k;5589>0g5==0168oo5589>0g?==0168i?5589>0a4==0168i>5589>0f?==0168no5589>0f>==0168585589>0=b==01685m5589>0d2==0168l;5589>0d5==01684m5589>0<b==01684l5589>00?==0168;>5589>00`==0168:95589>02>==0168:85589>03`==0168:>5589>03c==0168?m5589>065==0168><5589>01g==01689l5589>01?==01689<5589>015==01689?5589>7c`==0168=85589>053==0168<j5589>04c==0168<m5589>043==0168<85589>042==016?i<5589>7a?==016?i65589>7c6==016?k?5589>7``==016?h65589>7`?==016?h95589>7d3==016?lm5589>7dd==016?n=5589>7f2==016?n<5589>7gd==016?om5589>7gg==01v;?50;03b~X1927i4i4:9:?b41<2127j4>4:9:?b<7<2127j4<4:9:?b<5<2127j;k4:9:?b3`<2127j;i4:9:?b3f<2127j;o4:9:?b3d<2127j;44:9:?b3=<2127j;:4:9:?b33<2127j;84:9:?b31<2127j;>4:9:?b37<2127j;<4:9:?b35<2127j:k4:9:?b2`<2127j:i4:9:?b2f<2127j:o4:9:?b2d<2127j:44:9:?b2=<2127j::4:9:?b23<2127j:84:9:?b21<2127j:>4:9:?b27<2127j:<4:9:?b25<2127j9k4:9:?b1`<2127j9i4:9:?b1f<2127j9o4:9:?b1d<2127j944:9:?b1=<2127j9:4:9:?b13<2127j984:9:?b11<2127j9>4:9:?b17<2127j9<4:9:?b15<2127j8k4:9:?b0`<2127j8i4:9:?b0f<2127j8o4:9:?b0d<2127j844:9:?b0=<2127j8:4:9:?b03<2127j884:9:?b01<2127j8>4:9:?b05<2127j?h4:9:?b7f<2127j?l4:9:?b7=<2127j?;4:9:?b71<2127j??4:9:?b75<2127j>h4:9:?b6f<2127j>l4:9:?b6=<2127j>;4:9:?b61<2127j>?4:9:?b65<2127j=h4:9:?b5f<2127j=l4:9:?b5=<2127j=;4:9:?b51<2127j=?4:9:?b55<2127j<h4:9:?b4f<2127j4o4:9:?b<<<2127j4:4:9:?b<0<2127ij=4:9:?ab4<2127iik4:9:?0<f<212784i4:9:?0<d<212784o4:9:?0<3<212784:4:9:?0<1<21278484:9:?0<7<212784>4:9:?0<5<212784<4:9:?03`<21278;k4:9:?03f<21278;i4:9:?03d<21278;o4:9:?03=<21278;44:9:?033<21278;:4:9:?031<21278;84:9:?035<21278;<4:9:?02`<21278:k4:9:?02f<21278:i4:9:?02d<21278:o4:9:?02=<21278:44:9:?023<21278::4:9:?021<21278:84:9:?027<21278:>4:9:?025<21278:<4:9:?01`<212789k4:9:?0=d<212785o4:9:?0==<21278544:9:?0=3<212785:4:9:?0=1<21278584:9:?0=7<212785>4:9:?0=5<212785<4:9:?0<`<212784k4:9:?0<=<21278444:9:?037<21278;>4:9:?01f<212789i4:9:?:`2<2m272h?4:e:?:ga<2m272o54:e:?:g6<2m272nh4:e:?:f<<2m272n94:e:?:ec<2m272ml4:e:?:e0<2m272m=4:e:?:=g<2m2725;4:e:?:=4<2m2724n4:e:?:<2<2m2724?4:e:?:3a<2m272;54:e:?:36<2m272:h4:e:?:2<<2m272:94:e:?:1c<2m2729l4:e:?:10<2m2729=4:e:?:0g<2m2728;4:e:?:04<2m272?n4:e:?a`d<2127iok4:9:?agf<2127io54:9:?ag1<2127io=4:9:?aff<2127in54:9:?af1<21272=l4:9:?:50<21272=94:9:?:52<21272=;4:9:?:54<21273ii4:9:?;a=<21273i:4:9:?;ad<21273i44:9:?;a1<21273o=4:9:?;fg<21273nl4:9:?;fa<21273nn4:9:?;f2<212735>4:9:?;<`<212734i4:9:?;=5<212734k4:9:?;<d<21273:;4:9:?;24<21273:=4:9:?;26<21273:?4:9:?;1a<21273?44:9:?;71<21273?>4:9:?;73<21273?84:9:?;75<21273<n4:9:?;42<21273<;4:9:?;4<<21273<54:9:?;46<2127<hk4:9:?4`d<2127<h44:9:?4`f<2127<ho4:9:?4`3<2127<n?4:9:?4ea<2127<mn4:9:?4ec<2127<mh4:9:?4e<<2127<484:9:?4<5<2127<;k4:9:?4<7<2127<4<4:9:?43f<2127<954:9:?416<2127<9?4:9:?410<2127<994:9:?40c<2127<>o4:9:?463<2127<>84:9:?46=<2127<>:4:9:?467<2127=jh4:9:?5b<<2127=j54:9:?5bg<2127=jl4:9:?5b0<2127=h<4:9:?5gf<2127=oo4:9:?5g`<2127=oi4:9:?5g=<2127=m94:9:?5=c<2127=5h4:9:?5e4<2127=m=4:9:?5=g<2127=;:4:9:?537<2127=;<4:9:?531<2127=;>4:9:?52`<2127=8l4:9:?500<2127=894:9:?502<2127=8;4:9:?504<2127==i4:9:?55=<2127==:4:9:?55d<2127==44:9:?551<2127>j=4:9:?6ag<2127>il4:9:?6aa<2127>in4:9:?6a2<2127>o>4:9:?6f`<2127>ni4:9:?6g5<2127>nk4:9:?6fd<2127>5;4:9:?6=4<2127>5=4:9:?6=6<2127>5?4:9:?6<a<2127>:44:9:?621<2127>:>4:9:?623<2127>:84:9:?625<2127>?n4:9:?672<2127>?;4:9:?67<<2127>?54:9:?676<2127><k4:9:?64d<2127><44:9:?64f<2127><o4:9:?643<2127?i?4:9:?7`a<2127?hn4:9:?7`c<2127?hh4:9:?7`<<2127?n84:9:?7f5<2127?mk4:9:?7f7<2127?n<4:9:?7ef<2127?454:9:?7<6<2127?4?4:9:?7<0<2127?494:9:?73c<2127?9o4:9:?713<2127?984:9:?71=<2127?9:4:9:?717<2127?>h4:9:?76<<2127?>54:9:?76g<2127?>l4:9:?760<2127?<<4:9:?0bf<21278jo4:9:?0b`<21278ji4:9:?0b=<21278h94:9:?0gc<21278oh4:9:?0`4<21278h=4:9:?0gg<21278m:4:9:?0e7<21278m<4:9:?0e1<21278m>4:9:?0=`<21279o44:9:?1g=<21279o;4:9:?1g2<21279n;4:9:?1f0<21279n>4:9:?1f1<212795=4:9:?1<c<212794i4:9:?1<`<21279;i4:9:?13f<21279;l4:9:?13g<21279:l4:9:?12<<21279::4:9:?12=<212799:4:9:?113<21279994:9:?110<21279894:9:?106<212798<4:9:?107<21279?<4:9:?175<21279>h4:9:?16c<21279=h4:9:?15a<21279=o4:9:?15f<21279<o4:9:?14d<21279<54:9:?14<<2127:j54:9:?2b2<2127:j84:9:?2b3<2127:i84:9:?2a1<2127:i?4:9:?2a6<2127:nk4:9:?2f`<2127:nn4:9:?2fa<2127:mn4:9:?2eg<2127:m44:9:?2ed<2127:544:9:?2==<2127:5;4:9:?2=2<2127:4;4:9:?2<0<2127:4>4:9:?2<1<2127:;>4:9:?237<2127:;=4:9:?234<2127::=4:9:?21c<2127:9i4:9:?21`<2127:8i4:9:?20f<2127:8l4:9:?20g<2127:?l4:9:?27<<2127:?:4:9:?27=<2127:>:4:9:?263<2127:>94:9:?260<2127:=94:9:?256<2127:=<4:9:?257<212788h4:9:?00a<212788o4:9:?00f<21278?o4:9:?07d<21278?54:9:?07<<21278>54:9:?062<21278>84:9:?063<21278=84:9:?051<21278=?4:9:?056<21278<?4:9:?044<21279jk4:9:?045<21279ik4:9:?1a`<21279in4:9:?1aa<21279hn4:9:?1`g<21279h44:9:?1`d<21279m>4:9:?1e7<21279m=4:9:?1e4<2127:h?4:9:?2`4<2127:ok4:9:?2`5<2127:<<4:9:?245<2127mi7;6;<de>0?<uz<96=4={_41?8d>j33<7p}93;296~X1;27i5o468:p21<72;qU:952b8`9=<=z{??1<7<t^7789g?e20k0q~89:181[0134hj<779;|q53?6=:rT=;63ma18:1>{t>10;6?uQ699>fd6=1>1v;750;0xZ3?<5kk;6464}r4b>5<5sW<j70ln0;;:?xu1j3:1>vP9b:?ae5<>i2wx:n4?:2y]2f=:;<i14552b8c9=3=z{?n1<7<t^7f89gg420<0q~8j:181[0b34hj?77:;|q5b?6=:rT=j63ma28:3>{t?90;6?uQ719>fd5=111v:?50;0xZ27<5kk86474}r51>5<5sW=970ln3;;b?xu0;3:1>vP83:?a=f<>=2wx;94?:3y]31=:j0i15;5rs6794?4|V>?01o7l:858yv112909wS99;<`:g???3ty<;7>52z\43>;e1h0296s|7983>7}Y?116n4m5989~w2?=838pR:74=c;g><3<uz=j6=4={_5b?8d>l33=7p}8b;296~X0j27i5i467:p3f<72;qU;n52b8f9===z{>o1<7<t^6g89g?c2030q~9i:181[1a34h3i7om;|q;4?6=;rT3<63m988:0>;e1h02;6s|8083>`4|V1;01l6<:4`89d>52k801l6>:4`89d>72k801l9i:4`89d1b2k801l9k:4`89d1d2k801l9m:4`89d1f2k801l96:4`89d1?2k801l98:4`89d112k801l9::4`89d132k801l9<:4`89d152k801l9>:4`89d172k801l8i:4`89d0b2k801l8k:4`89d0d2k801l8m:4`89d0f2k801l86:4`89d0?2k801l88:4`89d012k801l8::4`89d032k801l8<:4`89d052k801l8>:4`89d072k801l;i:4`89d3b2k801l;k:4`89d3d2k801l;m:4`89d3f2k801l;6:4`89d3?2k801l;8:4`89d312k801l;::4`89d332k801l;<:4`89d352k801l;>:4`89d372k801l:i:4`89d2b2k801l:k:4`89d2d2k801l:m:4`89d2f2k801l:6:4`89d2?2k801l:8:4`89d212k801l:::4`89d232k801l:<:4`89d262k801l:?:4`89d5a2k801l=j:4`89d5c2k801l=l:4`89d5e2k801l=n:4`89d5>2k801l=7:4`89d502k801l=9:4`89d522k801l=;:4`89d542k801l==:4`89d562k801l=?:4`89d4a2k801l<j:4`89d4c2k801l<l:4`89d4e2k801l<n:4`89d4>2k801l<7:4`89d402k801l<9:4`89d422k801l<;:4`89d442k801l<=:4`89d462k801l<?:4`89d7a2k801l?j:4`89d7c2k801l?l:4`89d7e2k801l?n:4`89d7>2k801l?7:4`89d702k801l?9:4`89d722k801l?;:4`89d742k801l?=:4`89d762k801l??:4`89d6a2k801l>j:4`89d6c2k801l>l:4`89d6e2k801l6m:4`89d>f2k801l66:4`89d>?2k801l68:4`89d>12k801l6::4`89d>32k801>6l:4`896>f2<h01>69:4`896>32<h01>6=:4`896>72<h01>9j:4`8961d2<h01>9n:4`8961?2<h01>99:4`896132<h01>9?:4`8960b2<h01>8l:4`8960f2<h01>87:4`896012<h01>8;:4`896052<h01>8?:4`8963b2<h01>7n:4`896??2<h01>79:4`896?32<h01>7=:4`896?72<h01>6j:4`896>?2<h01>9=:4`8963d2<h014j7:8789<b02<h014j<:8789<b52<h014mj:8789<ec2<h014m6:8789<e?2<h014m;:8789<e42<h014li:8789<db2<h014ln:8789<d>2<h014l::8789<d32<h014l?:8789<ga2<h014om:8789<gf2<h014o9:8789<g22<h014o>:8789<g72<h0147l:8789<?e2<h01478:8789<?12<h0147=:8789<?62<h0146k:8789<>d2<h01467:8789<>02<h0146<:8789<>52<h0149j:8789<1c2<h01496:8789<1?2<h0149;:8789<142<h0148i:8789<0b2<h0148n:8789<0>2<h0148::8789<032<h0148?:8789<3a2<h014;m:8789<3f2<h014;9:8789<322<h014;>:8789<372<h014:l:8789<2e2<h014:8:8789<212<h014:=:8789<262<h014=k:8789<5d2<h01o7n:8:8yv>529099vP72:?b41<2j27j<9478:?b<7<2j27j4=4:b:?b3`<2j27j;n4:b:?b3d<2j27j;54:b:?b33<2j27j;94:b:?b37<2j27j;=4:b:?b2`<2j27j:n4:b:?b2d<2j27j:54:b:?b23<2j27j:94:b:?b27<2j27j:=4:b:?b1`<2j27j9n4:b:?b1d<2j27j954:b:?b13<2j27j994:b:?b17<2j27j9=4:b:?b0`<2j27j8n4:b:?b0d<2j27j854:b:?b03<2j27j894:b:?:b`<>>27i5l469:p<6<728:?wS6<;<`e4?>?34h3i778;<;2=??0343:<778;<;3b??0343:?778;<;26??0342no778;<:f7??0342n>778;<:f2??0342n9778;<:ab??0342i:778;<:a1??0342i5778;<:a<??03422>778;<:;=??034234778;<:;g??03423n778;<:51??0342>o778;<:6f??0342>j778;<:6a??034284778;<:1b??03429i778;<:06??03428=778;<:3f??0342;>778;<:35??0342;9778;<:30??034=oi778;<5g1??034=o8778;<5g<??034=o;778;<5a5??034=j4778;<5b3??034=jn778;<5be??034=38778;<54f??034=<m778;<54a??034=<h778;<563??034=?i778;<57`??034=>=778;<564??034=9m778;<515??034=9<778;<510??034=9?778;<4e`??034<m8778;<4e7??034<m;778;<4e2??034<o<778;<4`3??034<h:778;<4`e??034<h5778;<4b7??034<2m778;<4:=??034<2h778;<4:g??034<<:778;<45`??034<=o778;<444??034<=j778;<47=??034<?<778;<40b??034<??778;<476??034<:o778;<427??034<:>778;<422??034<:9778;<7fb??034?n:778;<7f1??034?n5778;<7f<??034?h>778;<7a=??034?i4778;<7ag??034?in778;<7:1??034?3o778;<7;f??034?3j778;<7;a??034?=4778;<76b??034?>i778;<756??034?==778;<70f??034?8>778;<705??034?89778;<700??034?;i778;<731??034?;8778;<73<??034?;;778;<6f5??034>o4778;<6g3??034>on778;<6ge??034>i8778;<6bf??034>jm778;<6ba??034>jh778;<6;3??034><i778;<64`??034>3=778;<6;4??034>>m778;<665??034>><778;<660??034>>?778;<61`??034>98778;<617??034>9;778;<612??034>;<778;<1e3??0349m:778;<1ee??0349m5778;<1g7??0349hm778;<1`=??0349hh778;<1`g??0349j:778;<1:`??03492o778;<1b4??03492j778;<0`e??0348h9778;<0`0??0348i;778;<0a6??0348i=778;<0:5??03483o778;<0;f??0348<i778;<04=??0348<4778;<05f??0348=:778;<051??0348>4778;<067??0348>>778;<071??0348?<778;<00b??03488>778;<01`??03489o778;<02b??0348:m778;<02=??0348;o778;<033??0348;:778;<3e=??034;m8778;<3e7??034;n:778;<3f5??034;n<778;<3`4??034;in778;<3ae??034;jh778;<3b<??034;j;778;<3:e??034;29778;<3:0??034;3;778;<3;6??034;3=778;<340??034;=j778;<35a??034;==778;<36g??034;>n778;<37a??034;?5778;<37<??034;8n778;<302??034;89778;<31<??034;9?778;<316??034;:9778;<324??034;;j778;<17b??0349?m778;<17=??03498o778;<103??03498:778;<11=??034998778;<117??0349::778;<125??0349:<778;<137??0348mi778;<0e`??0348m<778;<0ff??0348nm778;<0g`??0348o4778;<0g3??0348j8778;<0:b??03482i778;<3g7??034;hi778;<3``??034;;>778;<dg><1<5oi15:52b8c9=d=z{1>1<7<t^9689g?e20<0q~6::181[>234h2n77:;|qb3?6=kr7ijl461:?agg<?127io:479:?ag6<?127ink479:?afg<?127in:479:?af6<?1272io479:?:a2<?1272i>479:?247<>>2wxm54?:2158daj3kh70l7d;7a?8g783?i70o?1;7a?8g7:3?i707i6;7a?8?a?3?i70li0;7a?8da93?i70lka;7a?8ddn3?i70llc;7a?8dd03?i70ll4;7a?8dd83?i70lmc;7a?8de03?i70lm4;7a?8de;3?o70lm6;7g?8?b;3?o707j6;7g?8?6i3?i707>5;7a?8?6<3?i707>7;7a?8?6>3?i707>1;7a?8?603?i707>f;:;?8?6m323707>c;7a?8?6k323707>b;7a?8?6j323707<6;7a?8?4?3?i707=e;7a?8?5n3?i706jd;7a?8>b03?i706j7;7a?8>bi3?i706j9;7a?8>b<3?i706jb;7a?8>a:323706i1;:;?8>bn3?i706jf;:;?8>bm3?i706je;:;?8?713?i707?a;7a?8?793?i707?2;7a?8>d83?i706mb;7a?8>ei3?i706md;7a?8>ek3?i706m7;7a?8>em3?i706l5;:;?8>d<323706l2;7a?8>d:323706l1;7a?8>d9323706kc;7a?8>cl3?i706k4;7a?8>c=3?i70663;7a?8>?m3?i7067d;7a?8>>83?i7067f;7a?8>?i3?i70661;7a?8>>032370667;:;?8>>=3?i70665;:;?8>><3?i70664;:;?8>fn3?i706m0;7a?8>f?3?i706n8;7a?8>1>3?i70691;7a?8>183?i70693;7a?8>1:3?i706:d;7a?8>1<3?i7069b;:;?8>1i32370698;7a?8>1032370697;7a?8>1?32370672;7a?8>?;3?i7068a;7a?8>0j3?i706<9;7a?8>4<3?i706<3;7a?8>4>3?i706<5;7a?8>483?i706<7;7a?8>4m323706<d;:;?8>4j3?i706<b;:;?8>4i3?i706<a;:;?8>2=3?i706:6;7a?8>3l3?i706;e;7a?8>7k3?i706?7;7a?8>7>3?i706?9;7a?8>703?i706?3;7a?8>7i3?i706>1;:;?8>68323706?e;7a?8>7m323706?d;7a?8>7l323706=8;7a?8>513?i706=0;7a?8>593?i709kf;7a?81ci3?i709k9;7a?81ck3?i709kb;7a?81c>3?i709kd;7a?81b<323709j3;:;?81b93?i709j1;:;?81b83?i709j0;:;?81aj3?i709ic;7a?81a;3?i709i4;7a?81e:3?i709nd;7a?81fk3?i709nf;7a?81fm3?i709n9;7a?81e83?i709m7;:;?81e>323709m4;7a?81e<323709m3;7a?81e;323709le;7a?81dn3?i709l6;7a?81d?3?i70975;7a?81?83?i7098f;7a?81?:3?i70971;7a?810k3?i70973;7a?81?i32370979;:;?81??3?i70977;:;?81?>3?i70976;:;?81f93?i709n2;7a?81>13?i7096a;7a?81203?i709:3;7a?812:3?i709:5;7a?812<3?i709;f;7a?812>3?i709:d;:;?812k323709:a;7a?812i323709:9;7a?812132370984;7a?810=3?i7099c;7a?811l3?i709=b;7a?815>3?i709=5;7a?81503?i709=7;7a?815:3?i709=9;7a?8148323709=f;:;?815l3?i709=d;:;?815k3?i709=c;:;?813?3?i709;8;7a?814n3?i709;0;7a?80am3?i708i9;7a?80a03?i708ib;7a?80ai3?i708i5;7a?80ak3?i709?3;:;?817:323709?0;7a?8178323708if;7a?80an323709>a;7a?816j3?i709>2;7a?816;3?i708k1;7a?80dk3?i708lb;7a?80dm3?i708ld;7a?80d03?i708lf;7a?80c>323708k5;:;?80c;3?i708k3;:;?80c:3?i708k2;:;?80bl3?i708je;7a?80b=3?i708j6;7a?80f<3?i7086f;7a?80>m3?i708n1;7a?80f83?i7086b;7a?80f:3?i708n9;:;?80f0323708n6;7a?80f>323708n5;7a?80f=323708l0;7a?80d93?i708m8;7a?80e13?i70887;7a?800:3?i70881;7a?800<3?i70883;7a?801m3?i70885;7a?800k3237088b;:;?80013?i70889;:;?80003?i70888;:;?80>;3?i70864;7a?80?j3?i7087c;7a?803i3?i708;5;7a?803<3?i708;7;7a?803>3?i708;1;7a?80303?i708;f;:;?803m323708;c;7a?803k323708;b;7a?803j32370896;7a?801?3?i708:e;7a?802n3?i708>d;7a?80603?i708>7;7a?806i3?i708>9;7a?806<3?i708>b;7a?805:323708=1;:;?806n3?i708>f;:;?806m3?i708>e;:;?80413?i708<a;7a?80493?i708<2;7a?83a83?i70;jb;7a?83bi3?i70;jd;7a?83bk3?i70;j7;7a?83bm3?i70;i5;:;?83a<32370;i2;7a?83a:32370;i1;7a?83a9323708?c;7a?807l3?i708?4;7a?807=3?i70;l3;7a?83em3?i70;md;7a?83d83?i70;mf;7a?83ei3?i70;l1;7a?83d032370;l7;:;?83d=3?i70;l5;:;?83d<3?i70;l4;:;?83cn3?i70;j0;7a?83c?3?i70;k8;7a?83>>3?i70;61;7a?83>83?i70;63;7a?83>:3?i70;7d;7a?83><3?i70;6b;:;?83>i32370;68;7a?83>032370;67;7a?83>?32370;m2;7a?83e;3?i70;na;7a?83fj3?i70;99;7a?831<3?i70;93;7a?831>3?i70;95;7a?83183?i70;97;7a?831m32370;9d;:;?831j3?i70;9b;:;?831i3?i70;9a;:;?83?=3?i70;76;7a?830l3?i70;8e;7a?834k3?i70;<7;7a?834>3?i70;<9;7a?83403?i70;<3;7a?834i3?i70;;1;:;?833832370;<e;7a?834m32370;<d;7a?834l32370;:8;7a?83213?i70;:0;7a?83293?i70;?f;7a?837i3?i70;?9;7a?837k3?i70;?b;7a?837>3?i70;?d;7a?836<32370;>3;:;?83693?i70;>1;:;?83683?i70;>0;:;?835j3?i70;=c;7a?835;3?i70;=4;7a?82b:3?i70:kd;7a?82ck3?i70:kf;7a?82cm3?i70:k9;7a?82b83?i70:j7;:;?82b>32370:j4;7a?82b<32370:j3;7a?82b;32370:ie;7a?82an3?i70:i6;7a?82a?3?i70:m5;7a?82e83?i70:nf;7a?82e:3?i70:m1;7a?82fk3?i70:m3;7a?82ei32370:m9;:;?82e?3?i70:m7;:;?82e>3?i70:m6;:;?82c93?i70:k2;7a?82d13?i70:la;7a?82?03?i70:73;7a?82?:3?i70:75;7a?82?<3?i70:8f;7a?82?>3?i70:7d;:;?82?k32370:7a;7a?82?i32370:79;7a?82?132370:n4;7a?82f=3?i70:6c;7a?82>l3?i70::b;7a?822>3?i70::5;7a?82203?i70::7;7a?822:3?i70::9;7a?821832370::f;:;?822l3?i70::d;:;?822k3?i70::c;:;?820?3?i70:88;7a?821n3?i70:80;7a?825m3?i70:=9;7a?82503?i70:=b;7a?825i3?i70:=5;7a?825k3?i70:<3;:;?824:32370:<0;7a?824832370:=f;7a?825n32370:;a;7a?823j3?i70:;2;7a?823;3?i70:?1;7a?85ak3?i70=ib;7a?85am3?i70=id;7a?85a03?i70=if;7a?827>32370:?5;:;?827;3?i70:?3;:;?827:3?i70:?2;:;?826l3?i70:>e;7a?826=3?i70:>6;7a?85c<3?i70=lf;7a?85dm3?i70=k1;7a?85c83?i70=lb;7a?85c:3?i70=k9;:;?85c032370=k6;7a?85c>32370=k5;7a?85c=32370=i0;7a?85a93?i70=j8;7a?85b13?i70=n7;7a?85f:3?i70=n1;7a?85f<3?i70=n3;7a?85>m3?i70=n5;7a?85fk32370=nb;:;?85f13?i70=n9;:;?85f03?i70=n8;:;?85d;3?i70=l4;7a?85ej3?i70=mc;7a?84d13?i70<l8;7a?84d>3?i70<l7;7a?84dk3?i70<lc;:;?84dj3?i70<lb;:;?84e>3?i70<m5;7a?84e;3?i70<m4;7a?84e13?i70<m9;:;?84e03?i70<m8;:;?84>83?i70<7f;7a?84?l3?i70<7e;7a?84>;3?i70<63;:;?84>:3?i70<62;:;?840l3?i70<8c;7a?840i3?i70<8b;7a?84?83?i70<70;:;?840n3?i70<8f;:;?841i3?i70<99;7a?841?3?i70<98;7a?841l3?i70<9d;:;?841k3?i70<9c;:;?842?3?i70<:6;7a?842<3?i70<:5;7a?842i3?i70<:a;:;?84213?i70<:9;:;?843<3?i70<;3;7a?84393?i70<;2;7a?843?3?i70<;7;:;?843>3?i70<;6;:;?84493?i70<<0;7a?845m3?i70<=f;7a?844<3?i70<<4;:;?844;3?i70<<3;:;?846m3?i70<>d;7a?846j3?i70<>c;7a?84593?i70<=1;:;?84583?i70<=0;:;?847j3?i70<?a;7a?84703?i70<?9;7a?847m3?i70<?e;:;?847l3?i70<?d;:;?87a03?i70?i7;7a?87a=3?i70?i6;7a?87aj3?i70?ib;:;?87ai3?i70?ia;:;?87b=3?i70?j4;7a?87b:3?i70?j3;7a?87b03?i70?j8;:;?87b?3?i70?j7;:;?87en3?i70?me;7a?87ek3?i70?md;7a?87d:3?i70?l2;:;?87d93?i70?l1;:;?87fk3?i70?nb;7a?87f13?i70?na;7a?87fn3?i70?nf;:;?87fm3?i70?ne;:;?87>13?i70?68;7a?87>>3?i70?67;7a?87>k3?i70?6c;:;?87>j3?i70?6b;:;?87?>3?i70?75;7a?87?;3?i70?74;7a?87?13?i70?79;:;?87?03?i70?78;:;?870;3?i70?82;7a?87083?i70?81;7a?870>3?i70?86;:;?870=3?i70?85;:;?87183?i70?:f;7a?872l3?i70?:e;7a?871;3?i70?93;:;?871:3?i70?92;:;?873l3?i70?;c;7a?873i3?i70?;b;7a?87283?i70?:0;:;?873n3?i70?;f;:;?874i3?i70?<9;7a?874?3?i70?<8;7a?874l3?i70?<d;:;?874k3?i70?<c;:;?875?3?i70?=6;7a?875<3?i70?=5;7a?875i3?i70?=a;:;?87513?i70?=9;:;?876<3?i70?>3;7a?87693?i70?>2;7a?876?3?i70?>7;:;?876>3?i70?>6;:;?853m3?i70=;d;7a?853j3?i70=;c;7a?85293?i70=:1;:;?85283?i70=:0;:;?854j3?i70=<a;7a?85403?i70=<9;7a?854m3?i70=<e;:;?854l3?i70=<d;:;?85503?i70==7;7a?855=3?i70==6;7a?855j3?i70==b;:;?855i3?i70==a;:;?856=3?i70=>4;7a?856:3?i70=>3;7a?85603?i70=>8;:;?856?3?i70=>7;:;?857:3?i70=?1;7a?84an3?i70=?0;7a?857=3?i70=?5;:;?857<3?i70=?4;:;?84bn3?i70<je;7a?84bk3?i70<jd;7a?84a:3?i70<i2;:;?84a93?i70<i1;:;?84ck3?i70<kb;7a?84c13?i70<ka;7a?84cn3?i70<kf;:;?84cm3?i70<ke;:;?84f;3?i70<n2;7a?84f83?i70<n1;7a?84f>3?i70<n6;:;?84f=3?i70<n5;:;?87c:3?i70?k1;7a?87dn3?i70?k0;7a?87c=3?i70?k5;:;?87c<3?i70?k4;:;?87793?i70??0;7a?8`b2<h01kh55c9>552==k16==:5899>555==k16===5899~wd?=838p1o7k:``89g?d20k0q~l9:185[d1349j9767;<1b=?3>349h?767;<1af?>?349jm77;;|qa3?6=>rTi;63:668;<>;2>k0>563:848;<>;2?m03463:6b8:0>{tj10;6;uQb99>1<2=01169465589>1g4=01169lo5899>1<?=1=1vo750;4xZg?<5<i:6564=4a6>0?<5<nm6564=4f4>=><5<i=64:4}r`b>5<1sWhj70;je;:;?83a:3?2708?c;:;?807<32370;i3;;7?xuej3:1:vPmb:?55g<?027==k4:9:?57<<?027=?<478:?565<><2wxnn4?:7y]ff=:>=21455265a91<=:>?<1455264g9<==:>=n1595rscf94?0|Vkn01;9::9:8931>2<301;7<:9:893>e21201;9n:868yvdb290=wSlj;<4b6?>?34<j:7;6;<4`4?>?34<i4767;<4b3??33tyij7>56z\ab>;1ko034639d286=>;1mm034639e48;<>;1l=0286s|c183>3}Yk916:km5899>356==016;<o5899>344=0116;=?5959~wf7=83<pRn?4=2f1>=><5:n=6874=2d3>=><5:o36564=2f4><2<uzi96=49{_a1?8151323709=d;7:?813?323709<f;:;?815m33?7p}l3;292~Xd;27<9;478:?41d<2127<;9478:?42f<?027<9o464:pg1<72?qUo9527919<==:?1=194527`39<==:?031455279:9=1=z{j?1<78t^b7892d721201:l;:4;892eb21201:m9:9:892d220>0q~m9:185[e134=oh767;<5f5?3>34=mn767;<5e7?>?34=n>77;;|q`3?6=>rTh;6370`8;<>;?8l0>5637298;<>;?:90346370g8:0>{tk10;6;uQc99><61=01164>l5589><03=011649j5899><6e=1=1vn750;4xZf?<51<?6564=94;>0?<51296564=95b>=><51<264:4}rab>5<1sWij70661;:;?8>>=3?2706nf;:;?8>f?32370666;;7?xudj3:1:vPlb:?;f`<?0273o?4:9:?;`f<?0273h9478:?;g6<><2wxon4?:7y]gf=:;ol1455241191<=:<8n145524079<==:<9>1595rsbf94?0|Vjn015km:9:89=ca2<3014>6:9:89<66212015h?:868yvea290=wSmi;<;2<?>?343:o7;6;<;02?>?3439i767;<;2`??33tyo<7>56z\g4>;3:j03463;3186=>;3<h03463;438;<>;3;80286s|d083>3}Yl8168875899>00b==0168:95899>03`=011688k5959~wa4=83<pRi<4=5:5>=><5=2j6874=5c7>=><5=3h6564=5:a><2<uzn86=49{_f0?82e;32370:m7;7:?82c932370:l9;:;?82e033?7p}k4;292~Xc<27?i=478:?7a1<2127?jh478:?7b3<?027?i8464:p`0<72?qUh85251f9<==:=8;1945253`9<==:=;9145525009=1=z{m<1<78t^e48905f212018=j:4;8903?212018;?:9:8905a20>0q~j8:181[b03438j7l?;|qg<?6=:rTo4636708a4>{tl00;6?uQd89>=20=j91vio50;0xZag<50=i6o>4}rfa>5<5sWni70770;`3?xuck3:1>vPkc:?:<0<e82wxhi4?:3y]`a=:11k1n=5rseg94?4|Vmo0146i:c28yvba2909wSji;<;:0?d73tyn<7>52z\f4>;>100i<6s|e083>7}Ym81654k5b19~w`4=838pRh<4=867>g6<uzo86=4={_g0?8?f;3h;7p}j4;296~Xb<272m54m0:pa0<72;qUi8529`f9f5=z{l<1<7<t^d489<d52k:0q~k8:181[c0343i;7l?;|qf<?6=:rTn4636bb8a4>{tm00;6?uQe89>=f7=j91vho50;0xZ`g<50i=6o>4}rga>5<5sWoi707lb;`3?xubk3:1>vPjc:?:`5<e82wxii4?:3y]aa=:1=31n=5rsdg94?4|Vlo014j::c28yv`72909wSh?;<;ge?d73tym=7>52z\e5>;><l0i<6s|f383>7}Yn;1658=5b19~wc5=838pRk=4=87;>g6<uzl?6=4={_d7?8?2l3h;7p}i5;296~Xa=272:?4m0:pb3<72;qUj;529759f5=z{o=1<7<t^g589<0d2k:0q~hn:1810~;>no0i<63n0286f>;f8:034636f78;<>;f<80>n63n3g86f>;f;m0>n63n3c86f>;f;00>n63n3686f>;f;<0>n63n3286f>;f;80>n63n2g86f>;f:m0>n63n2c86f>;f:00>n63n2686f>;f:<0>n63n2286f>;f:80>n63n1g86f>;f9m0>n63n1c86f>;f900>n63n1686f>;f9<0>n63n1286f>;f980>n63n0g86f>;f8m0>n63n0c86f>;f0h0>n63n8986f>;f0?0>n63n8586f>{tnk0;6?u2b9f9f5=:j1o15;5rs025>5<5s4ln6564=ga9eg=z{8:<6=4={<334?>?34lo6ll4}r33<?6=:r7:<>4m0:?eg??23ty:<44?:3y>557=j916ji466:p55g=838p1<>?:c289ce=1?1v<>m:1818`b2k:01kh5899~w46d2909w0??1;:;?877:3ki7p}>0e83>7}:99>1n=52fe8:1>{t99o1<7<t=020>0?<58:>6ll4}r32=?6=:r7:=<478:?24c<fj2wx=<o50;0x947421201<??:``8yv76j3:1>v3>178a4>;68o0296s|10a94?4|58;?6o>4=033><0<uz;:h7>52z?256<e827:<k466:p54c=838p1<?>:c2894752120q~?>f;296~;69=03463>148bf>{t9;:1<7<t=034>g6<58;;64;4}r315?6=:r7:=;4:9:?25=<fj2wx=?m50;0x944321201<<=:``8yv75l3:1>v3>278;<>;6::0jn6s|13g94?4|58826o>4=001><3<uz;9j7>52z?262<e827:>>466:p566=838p1<<9:c28944520<0q~?<1;296~;6:=0i<63>248;<>{t9:81<7<t=004>=><58836ll4}r307?6=:r7:>l4m0:?266<>=2wx=>:50;0x944>2<301<<m:``8yv74n3:1>v3>368;<>;6;<0jn6s|15294?4|58926564=015>dd<uz;?=7>52z?27f<e827:?8465:p514=838p1<=n:c28945120<0q~?;3;296~;6;00i<63>348:2>{t9=>1<7<t=014>g6<58936564}r371?6=:r7:?l478:?27g<fj2wx=9850;0x945c2k:01<=9:878yv73?3:1>v3>3b86=>;6;l0jn6s|14094?4|58>j6564=06;>dd<uz;>?7>52z?20f<?027:844nb:p502=838p1<:i:c28942?20?0q~?:5;296~;6<m0i<63>488:2>{t9<<1<7<t=06`>g6<58>36484}r363?6=:r7:8l4m0:?20g<?02wx=8650;0x942c21201<:j:``8yv7213:1>v3>518a4>;6<00296s|14c94?4|58>m6874=072>dd<uz;=97>52z?21a<?027:9o4nb:p530=838p1<;i:9:8943d2hh0q~?97;296~;6>;0i<63>5c8:1>{t9?21<7<t=043>g6<58?h6484}r35=?6=:r7:9k4m0:?21g<>>2wx=;o50;0x943c2k:01<;j:9:8yv71j3:1>v3>618;<>;6>80jn6s|17a94?4|58<86o>4=07`><3<uz;=h7>52z?227<2127::94nb:p52>=838p1<9?:9:8940b2hh0q~?89;296~;6?;03463>6g8bf>{t9>k1<7<t=056>g6<58<n64;4}r34f?6=:r7:;>4m0:?22c<>>2wx=:m50;0x94152k:01<8j:848yv70l3:1>v3>718a4>;6?80346s|16g94?4|58=86564=057>dd<uz;<j7>52z?233<e827::k465:p5=6=838p1<9::4;894102hh0q~?7b;296~;60:03463>808bf>{t91i1<7<t=0:6>=><58296ll4}r3;`?6=:r7:454m0:?2<4<>=2wx=5k50;0x94>12k:01<6=:848yv7?n3:1>v3>848a4>;60802:6s|18294?4|58286o>4=0:7>=><uz;2=7>52z?2<3<?027:4:4nb:p5<4=838p1<66:c2894>520?0q~?63;296~;6010>563>8`8bf>{t90o1<7<t=0;5>=><583?6ll4}r3:b?6=:r7:55478:?2=0<fj2wx=l>50;0x94?e2k:01<7;:878yv7f93:1>v3>988a4>;61<02:6s|1`094?4|58336o>4=0;7><0<uz;j?7>52z?2=3<e827:5:478:p5d2=838p1<76:9:894?f2hh0q~?n5;296~;61j0i<63>948:1>{t9h<1<7<t=0;a>0?<583o6ll4}r3a5?6=:r7:m4478:?2e2<fj2wx=o<50;0x94ge21201<o7:``8yv7e;3:1>v3>ad8a4>;6i>0296s|1c694?4|58kh6o>4=0c;><0<uz;i97>52z?2eg<e827:m:466:p5g0=838p1<o6:c2894gf2120q~?m7;296~;6ij03463>ae8bf>{t9k21<7<t=0ce>g6<58k364;4}r3a=?6=:r7:mh4:9:?2f5<fj2wx=n:50;0x94dd21201<ln:``8yv7d=3:1>v3>bd8;<>;6jk0jn6s|1b494?4|58i:6o>4=0`b><3<uz;h;7>52z?2fc<e827:no466:p5f>=838p1<lj:c2894df20<0q~?l9;296~;6jj0i<63>be8;<>{t9jk1<7<t=0`e>=><58i;6ll4}r3`f?6=:r7:o?4m0:?2fg<>=2wx=nm50;0x94e62<301<m<:``8yv7c?3:1>v3>cg8;<>;6km0jn6s|1e:94?4|58n:6564=0af>dd<uz;o57>52z?2`1<e827:oi465:p5ag=838p1<j=:c2894eb20<0q~?kb;296~;6l80i<63>ce8:2>{t9mi1<7<t=0ae>g6<58n;6564}r3g`?6=:r7:h?478:?2`6<fj2wx=ik50;0x94b22k:01<mj:878yv7cn3:1>v3>d586=>;6l?0jn6s|1dc94?4|58o96564=0g3>dd<uz;nn7>52z?2a1<?027:i<4nb:p5`e=838p1<k8:c2894c720?0q~?jd;296~;6m<0i<63>e08:2>{t9lo1<7<t=0g7>g6<58o;6484}r3fb?6=:r7:i?4m0:?2a6<?02wx=k>50;0x94c221201<k9:``8yv7a93:1>v3>e98a4>;6m80296s|1g094?4|58o<6874=0g:>dd<uz;mh7>52z?2b0<?027:j>4nb:p5cc=838p1<h8:9:894`32hh0q~?if;296~;6nh0i<63>f28:1>{t:9:1<7<t=0d;>g6<58l?6484}r035?6=:r7:j:4m0:?2b6<>>2wx>=<50;0x94`22k:01<h9:9:8yv47;3:1>v3>f98;<>;6n00jn6s|21694?4|58li6o>4=0d7><3<uz8;97>52z?2bd<2127:jn4nb:p646=838p1?>7:9:897612hh0q~<>1;296~;58h03463=068bf>{t:881<7<t=32g>g6<5;:=64;4}r027?6=:r79<o4m0:?142<>>2wx><:50;0x976f2k:01?>9:848yv46=3:1>v3=098a4>;5800346s|20494?4|5;:i6564=32`>dd<uz8:;7>52z?14`<e8279<:465:p64>=838p1?>k:4;8976a2hh0q~<=3;296~;59k03463=188bf>{t:;>1<7<t=33g>=><5;;j6ll4}r011?6=:r79>=4m0:?15<<>=2wx>?850;0x977b2k:01??n:848yv45?3:1>v3=1e8a4>;59002:6s|23:94?4|5;;i6o>4=33`>=><uz8957>52z?15`<?0279=k4nb:p67g=838p1?<>:c28977f20?0q~<=b;296~;5:90>563=238bf>{t::<1<7<t=30f>=><5;8h6ll4}r003?6=:r79?=478:?16a<fj2wx>>650;0x97542k:01?<l:878yv4413:1>v3=308a4>;5:m02:6s|22c94?4|5;9;6o>4=30`><0<uz88n7>52z?16`<e8279>k478:p66e=838p1?=>:9:897552hh0q~<<d;296~;5;=0i<63=2e8:1>{t::o1<7<t=310>0?<5;9>6ll4}r07=?6=:r798<478:?17c<fj2wx>9o50;0x972421201?:?:``8yv43j3:1>v3=478a4>;5;o0296s|25a94?4|5;>?6o>4=363><0<uz8?h7>52z?106<e8279?k466:p61c=838p1?:>:c2897252120q~<;f;296~;5<=03463=448bf>{t:<:1<7<t=364>g6<5;>;64;4}r065?6=:r798;4:9:?10=<fj2wx>8m50;0x973321201?;=:``8yv42l3:1>v3=578;<>;5=:0jn6s|24g94?4|5;?26o>4=371><3<uz8>j7>52z?112<e82799>466:p636=838p1?;9:c28973520<0q~<91;296~;5==0i<63=548;<>{t:?81<7<t=374>=><5;?36ll4}r057?6=:r799l4m0:?116<>=2wx>;:50;0x973>2<301?;m:``8yv41n3:1>v3=668;<>;5><0jn6s|26294?4|5;<26564=345>dd<uz8<=7>52z?12f<e8279:8465:p624=838p1?8n:c28970120<0q~<83;296~;5>00i<63=648:2>{t:>>1<7<t=344>g6<5;<36564}r041?6=:r79:l478:?12g<fj2wx>:850;0x970c2k:01?89:878yv40?3:1>v3=6b86=>;5>l0jn6s|29094?4|5;=j6564=35;>dd<uz83?7>52z?13f<?0279;44nb:p6=2=838p1?9i:c28971?20?0q~<75;296~;5?m0i<63=788:2>{t:1<1<7<t=35`>g6<5;=36484}r0;3?6=:r79;l4m0:?13g<?02wx>5650;0x971c21201?9j:``8yv4?13:1>v3=818a4>;5?00296s|29c94?4|5;=m6874=3:2>dd<uz8297>52z?1<a<?02794o4nb:p6<0=838p1?6i:9:897>d2hh0q~<67;296~;51;0i<63=8c8:1>{t:021<7<t=3;3>g6<5;2h6484}r0:=?6=:r794k4m0:?1<g<>>2wx>4o50;0x97>c2k:01?6j:9:8yv4>j3:1>v3=918;<>;5180jn6s|28a94?4|5;386o>4=3:`><3<uz82h7>52z?1=7<21279594nb:p6d>=838p1?o?:9:897?b2hh0q~<n9;296~;5i;03463=9g8bf>{t:hk1<7<t=3c6>g6<5;3n64;4}r0bf?6=:r79m>4m0:?1=c<>>2wx>lm50;0x97g52k:01?7j:848yv4fl3:1>v3=a18a4>;5i80346s|2`g94?4|5;k86564=3c7>dd<uz8jj7>52z?1e3<e82795k465:p6g6=838p1?o::4;897g02hh0q~<mb;296~;5j:03463=b08bf>{t:ki1<7<t=3`6>=><5;h96ll4}r0a`?6=:r79n54m0:?1f4<>=2wx>ok50;0x97d12k:01?l=:848yv4en3:1>v3=b48a4>;5j802:6s|2b294?4|5;h86o>4=3`7>=><uz8h=7>52z?1f3<?0279n:4nb:p6f4=838p1?l6:c2897d520?0q~<l3;296~;5j10>563=b`8bf>{t:jo1<7<t=3a5>=><5;i?6ll4}r0`b?6=:r79o5478:?1g0<fj2wx>i>50;0x97ee2k:01?m;:878yv4c93:1>v3=c88a4>;5k<02:6s|2e094?4|5;i36o>4=3a7><0<uz8o?7>52z?1g3<e8279o:478:p6a2=838p1?m6:9:897ef2hh0q~<k5;296~;5kj0i<63=c48:1>{t:m<1<7<t=3aa>0?<5;io6ll4}r0f5?6=:r79h4478:?1`2<fj2wx>h<50;0x97be21201?j7:``8yv4b;3:1>v3=dd8a4>;5l>0296s|2d694?4|5;nh6o>4=3f;><0<uz8n97>52z?1`g<e8279h:466:p6`0=838p1?j6:c2897bf2120q~<j7;296~;5lj03463=de8bf>{t:l21<7<t=3fe>g6<5;n364;4}r0f=?6=:r79hh4:9:?1a5<fj2wx>k:50;0x97cd21201?kn:``8yv4a=3:1>v3=ed8;<>;5mk0jn6s|2g494?4|5;l:6o>4=3gb><3<uz8m;7>52z?1ac<e8279io466:p6c>=838p1?kj:c2897cf20<0q~<i9;296~;5mj0i<63=ee8;<>{t:ok1<7<t=3ge>=><5;l;6ll4}r0ef?6=:r79j?4m0:?1ag<>=2wx>km50;0x97`62<301?h<:``8yv57?3:1>v3=fg8;<>;5nm0jn6s|31:94?4|5:::6564=3df>dd<uz9;57>52z?041<e8279ji465:p75g=838p1>>=:c2897`b20<0q~=?b;296~;4880i<63=fe8:2>{t;9i1<7<t=3de>g6<5::;6564}r13`?6=:r78<?478:?046<fj2wx?=k50;0x96622k:01?hj:878yv57n3:1>v3<0586=>;48?0jn6s|30c94?4|5:;96564=233>dd<uz9:n7>52z?051<?0278=<4nb:p74e=838p1>?8:c28967720?0q~=>d;296~;49<0i<63<108:2>{t;8o1<7<t=237>g6<5:;;6484}r12b?6=:r78=?4m0:?056<?02wx??>50;0x967221201>?9:``8yv5593:1>v3<198a4>;4980296s|33094?4|5:;<6874=23:>dd<uz99h7>52z?060<?0278>>4nb:p77c=838p1><8:9:896432hh0q~==f;296~;4:h0i<63<228:1>{t;::1<7<t=20;>g6<5:8?6484}r105?6=:r78>:4m0:?066<>>2wx?><50;0x96422k:01><9:9:8yv54;3:1>v3<298;<>;4:00jn6s|32694?4|5:8i6o>4=207><3<uz9897>52z?06d<21278>n4nb:p716=838p1>=7:9:896512hh0q~=;1;296~;4;h03463<368bf>{t;=81<7<t=21g>g6<5:9=64;4}r177?6=:r78?o4m0:?072<>>2wx?9:50;0x965f2k:01>=9:848yv53=3:1>v3<398a4>;4;00346s|35494?4|5:9i6564=21`>dd<uz9?;7>52z?07`<e8278?:465:p71>=838p1>=k:4;8965a2hh0q~=:3;296~;4<k03463<488bf>{t;<>1<7<t=26g>=><5:>j6ll4}r161?6=:r789=4m0:?00<<>=2wx?8850;0x962b2k:01>:n:848yv52?3:1>v3<4e8a4>;4<002:6s|34:94?4|5:>i6o>4=26`>=><uz9>57>52z?00`<?02788k4nb:p70g=838p1>;>:c28962f20?0q~=:b;296~;4=90>563<538bf>{t;hn1<7<t=2c2>=><5:3h6ll4}r1ba?6=:r78m?478:?0=a<fj2wx?lh50;0x96g22k:01>o9:878yv5e83:1>v3<ac86f>;4jh0i<6s|3c394?4|5:k36o>4=2;`><3<uz9i>7>52z?0e2<e82785i466:p7g5=838p1>o=:c2896?d20<0q~=m4;296~;4i80i<63<a18:2>{t;k?1<7<t=2c7>g6<5:3m6484}r1a2?6=:r78m>4m0:?0=`<?02wx?o950;0x96g021201>o9:``8yv5e03:1>v3<ab86f>;4k;0i<6s|3c;94?4|5:k26o>4=2;g><3<uz9ih7>53z?0fg<e8278nn478:?0fd<e:2wx?ok50;0x96dd2k:01>ln:9:8yv5en3:1>v3<ac8a4>;41o0296s|3b294?4|5:k86564=2;e>dd<uz9h=7>52z?0e1<?0278m=4nb:p7f3=839p1>m<:c2896e321201>m=:9:8yv5d>3:1>v3<c58a4>;4k;0i>6s|3b594?4|5:kh6o>4=2c3><3<uz9h47>52z?0e=<21278ml4nb:p7ag=838p1>mj:9:896e>2hh0q~=kb;296~;4ko03463<c`8bf>{t;mi1<7<t=2f1>g6<5:n864;4}r1g`?6=:r78h54:b:?0a2<e82wx?ik50;0x96b22k:01>m6:878yv5cn3:1>v3<d58a4>;4kh02:6s|3d294?4|5:im6o>4=2a:><0<uz9n=7>52z?0g`<e8278oi466:p7`4=838p1>j>:c2896ed20<0q~=j3;296~;4l90i<63<cc8;<>{t;l>1<7<t=2f7>=><5:n86ll4}r1f1?6=:r78h44:b:?0ac<e82wx?h850;0x96b12k:01>mn:878yv5bi3:1?v3<e98a4>;4m003463<e68a6>{t;lh1<7<t=2g:>g6<5:o<6564}r1fg?6=:r78h54m0:?0gf<>=2wx?hj50;0x96b721201>ml:``8yv5bm3:1>v3<d08;<>;4km0jn6s|3g094?5|5:l;6o>4=2d2>=><5:om6564}r1e7?6=:r78j<4m0:?0ac<e:2wx?k:50;0x96b>2k:01>mk:878yv5a=3:1>v3<d486=>;4l>0jn6s|41594?4|5:li6564=2d5>dd<uz>;47>52z?0bf<?0278j:4nb:p05?=838p1>hi:c28916720?0q~:?a;296~;38<0>n63;158a4>{t<9h1<7<t=521>g6<5:l=64;4}r63g?6=:r7?<<4m0:?0b2<>>2wx8=j50;0x96`d2k:01>h9:848yv27m3:1>v3<fc8a4>;4nh02:6s|41d94?4|5:ln6o>4=2d:><0<uz>:<7>52z?0ba<e8278j5478:p047=838p19>>:9:891672hh0q~:>2;296~;38?0>n63;1b8a4>{t<891<7<t=520>g6<5:l<64;4}r623?6=;r7?=84m0:?753<?027?=94m2:p04>=838p19?9:c2891732120q~:>9;296~;38<0i<63<f88:1>{t<8k1<7<t=2dg>=><5:l26ll4}r62f?6=:r78jh478:?0bd<fj2wx8<h50;1x917c2k:019?j:9:8917d2120q~:=0;296~;39l0i<63;1b8a6>{t<;;1<7<t=525>g6<5:lj64;4}r616?6=:r7?<?4:9:?741<fj2wx8>:50;0x914?212019<<:``8yv24=3:1>v3;288;<>;3:=0jn6s|42494?4|5=8h6o>4=50g><3<uz>8;7>52z?777<2j27?8<4m0:p06>=838p19<i:c28914420?0q~:<9;296~;3:l0i<63;258:2>{t<:k1<7<t=50:>g6<5=886484}r60f?6=:r7?>54m0:?762<>>2wx8>m50;0x914e2k:019<9:848yv24l3:1>v3;2`8a4>;3:<0346s|42g94?4|5=8n6564=50g>dd<uz>8j7>52z?776<2j27?844m0:p016=838p19=?:c28914320?0q~:;4;297~;3<;0i<63;428;<>;3<80i>6s|45794?4|5=>86o>4=562>=><uz>?:7>52z?777<e827?>;465:p011=838p19<n:9:891412hh0q~:;8;296~;3:k03463;268bf>{t<=i1<7=t=56b>g6<5=>i6564=56:>=><uz>?h7>52z?70g<e827?844m2:p01c=838p19=<:c28914020?0q~:;f;296~;3:o0>563;308bf>{t<?;1<7<t=576>=><5=?;6ll4}r656?6=:r7?9;478:?714<fj2wx8;=50;0x913>2k:019;n:878yv21<3:1>v3;5g86f>;3>l0i<6s|47794?4|5=?h6o>4=573><3<uz>=:7>52z?71g<e827?9<466:p031=838p19;9:c28913720<0q~:98;296~;3=<0i<63;558:2>{t<?31<7<t=57;>g6<5=?86484}r65e?6=:r7?9:4m0:?717<?02wx8;l50;0x913e212019;n:``8yv21k3:1>v3;6186f>;3??0i<6s|47f94?4|5=?o6o>4=572><3<uz><=7>53z?72c<e827?;=478:?72`<e:2wx8:<50;0x91172k:0198j:9:8yv20;3:1>v3;5g8a4>;3=:0296s|46694?4|5=?<6564=570>dd<uz><97>52z?71=<?027?994nb:p02?=839p1998:c28911?21201999:9:8yv20i3:1>v3;798a4>;3??0i>6s|46`94?4|5=<;6o>4=577><3<uz><o7>52z?71f<2127?9h4nb:p0=c=838p196=:9:8911c2hh0q~:7f;296~;30:03463;7d8bf>{t<0:1<7<t=5:5>g6<5=2<64;4}r6:5?6=:r7?4n4:b:?7=g<e82wx84<50;0x91>>2k:0199k:878yv2>;3:1>v3;898a4>;3?l02:6s|48694?4|5=286o>4=55g><0<uz>297>52z?7<7<e827?4<466:p0<0=838p196::c2891>720<0q~:67;296~;30=0i<63;7g8;<>{t<021<7<t=5:;>=><5=2<6ll4}r6:=?6=:r7?4i4:b:?7e6<e82wx84o50;0x91>f2k:0199j:878yv2>m3:1?v3;9b8a4>;31m03463;9c8a6>{t<0l1<7<t=5;g>g6<5=3i6564}r6b4?6=:r7?4n4m0:?7<5<>=2wx8l?50;0x91>32120196?:``8yv2f:3:1>v3;848;<>;3080jn6s|4`494?5|5=k?6o>4=5c6>=><5=k86564}r6b3?6=:r7?m84m0:?7e6<e:2wx8l650;0x91>c2k:0196>:878yv2f13:1>v3;8886=>;30k0jn6s|4c`94?4|5=km6564=5cb>dd<uz>io7>52z?7f5<?027?mo4nb:p0gb=838p19l<:c2891d320?0q~:me;296~;3j00>n63;c98a4>{t<kl1<7<t=5`5>g6<5=kj64;4}r6`4?6=:r7?n84m0:?7eg<>>2wx8n?50;0x91d72k:019on:848yv2d:3:1>v3;ag8a4>;3il02:6s|4b194?4|5=h96o>4=5cg><0<uz>h87>52z?7f4<e827?mn478:p0f3=838p19l::9:891d32hh0q~:l6;296~;3jh0>n63;d18a4>{t<j=1<7<t=5`4>g6<5=ki64;4}r6`f?6=;r7?o44m0:?7gd<?027?o54m2:p0fe=838p19mn:c2891e?2120q~:ld;296~;3j00i<63;ae8:1>{t<jo1<7<t=5`2>=><5=ko6ll4}r6`b?6=:r7?n?478:?7e`<fj2wx8i=50;1x91b62k:019j=:9:891b72120q~:k4;296~;3l;0i<63;d18a6>{t<m?1<7<t=5`b>g6<5=kn64;4}r6g2?6=:r7?n;4:9:?7f=<fj2wx8h650;0x91bd212019j8:``8yv2b13:1>v3;de8;<>;3l10jn6s|4dc94?4|5=o;6o>4=5g2><3<uz>nn7>52z?7a3<2j27?j84m0:p0`e=838p19k<:c2891b020?0q~:jd;296~;3m;0i<63;d98:2>{t<lo1<7<t=5fg>g6<5=n<6484}r6fb?6=:r7?hn4m0:?7`g<>>2wx8k>50;0x91ba2k:019jn:848yv2a93:1>v3;dd8a4>;3l00346s|4g094?4|5=o96564=5g2>dd<uz>m?7>52z?7a2<2j27?ji4m0:p0c2=838p19k;:c2891b?20?0q~:i8;297~;3n?0i<63;f68;<>;3n<0i>6s|4g;94?4|5=l<6o>4=5d6>=><uz>mm7>52z?7a3<e827?hl465:p0cd=838p19jj:9:891bf2hh0q~:ic;296~;3lo03463;dc8bf>{t=9:1<7=t=5df>g6<5=lm6564=5dg>=><uz?;=7>52z?7bc<e827?ji4m2:p154=838p19k8:c2891be20?0q~;?3;296~;3m:0>563;e48bf>{t=8?1<7<t=42:>=><5<:?6ll4}r722?6=:r7><l478:?640<fj2wx9<950;0x906c2k:018>j:878yv3603:1>v3:1286f>;2:;0i<6s|50;94?4|5<;;6o>4=427><3<uz?:m7>52z?64c<e827><8466:p14d=838p18>n:c28906320<0q~;>c;296~;2800i<63:098:2>{t=8n1<7<t=42`>g6<5<:<6484}r72a?6=:r7><o4m0:?643<?02wx9<h50;0x906a212018>j:``8yv3583:1>v3:1586f>;2:h0i<6s|53394?4|5<;:6o>4=426><3<uz?997>53z?666<e827>>9478:?667<e:2wx9?850;0x90432k:018<=:9:8yv35?3:1>v3:128a4>;28>0296s|53:94?4|5<:i6564=424>dd<uz?957>52z?64f<?027><54nb:p17b=839p18<m:c28904d212018<n:9:8yv35m3:1>v3:2b8a4>;2:h0i>6s|53d94?4|5<;?6o>4=42;><3<uz?8<7>52z?655<2127>=?4nb:p114=838p18=9:9:890562hh0q~;;3;296~;2;>03463:338bf>{t==>1<7<t=41b>g6<5<9i64;4}r771?6=:r7>8=4:b:?60c<e82wx99850;0x905c2k:018=>:878yv33?3:1>v3:3b8a4>;2;;02:6s|55:94?4|5<9<6o>4=412><0<uz??57>52z?673<e827>?8466:p11g=838p18=6:c28905320<0q~;;b;296~;2;10i<63:328;<>{t==i1<7<t=41`>=><5<9i6ll4}r77`?6=:r7>8<4:b:?612<e82wx99k50;0x905b2k:018==:878yv32:3:1?v3:518a4>;2=803463:4g8a6>{t=<91<7<t=472>g6<5<>m6564}r760?6=:r7>8=4m0:?671<>=2wx98;50;0x905?212018=;:``8yv32>3:1>v3:388;<>;2;<0jn6s|54c94?5|5<?36o>4=47:>=><5<?<6564}r76f?6=:r7>944m0:?612<e:2wx98m50;0x90262k:018=::878yv32l3:1>v3:3e86=>;2;o0jn6s|57d94?4|5<<86564=47f>dd<uz?<<7>52z?621<?027>9k4nb:p127=838p1888:c28900?20?0q~;82;296~;2>m0>n63:7b8a4>{t=>91<7<t=44b>g6<5<?n64;4}r740?6=:r7>:44m0:?61c<>>2wx9:;50;0x90032k:018;j:848yv30>3:1>v3:628a4>;2>;02:6s|56594?4|5<<=6o>4=442><0<uz?<47>52z?620<e827>:=478:p12?=838p1886:9:8900?2hh0q~;8a;296~;2>l0>n63:858a4>{t=>h1<7<t=44a>g6<5<?m64;4}r74b?6=;r7>;i4m0:?63`<?027>;n4m2:p1=6=838p189j:c28901d2120q~;71;296~;2>m0i<63:608:1>{t=181<7<t=446>=><5<<:6ll4}r7;7?6=:r7>:;478:?627<fj2wx95950;1x90>22k:01869:9:890>32120q~;78;296~;20?0i<63:858a6>{t=131<7<t=44f>g6<5<<964;4}r7;e?6=:r7>:l4:9:?62f<fj2wx94m50;0x90?72120186m:``8yv3>l3:1>v3:908;<>;20j0jn6s|58g94?4|5<3?6o>4=4;6><3<uz?2j7>52z?6=d<2j27>m44m0:p1d6=838p1878:c2890>e20?0q~;n1;296~;21?0i<63:8b8:2>{t=h81<7<t=4;2>g6<5<2i6484}r7b7?6=:r7>5=4m0:?6<c<>>2wx9l:50;0x90?42k:0186j:848yv3f=3:1>v3:938a4>;20m0346s|5`494?4|5<3=6564=4;6>dd<uz?j;7>52z?6=g<2j27>n<4m0:p1d>=838p1877:c2890>d20?0q~;nc;297~;2ih0i<63:ac8;<>;2i00i>6s|5`f94?4|5<ki6o>4=4c:>=><uz?ji7>52z?6=d<e827>4h465:p1d`=838p187=:9:890>b2hh0q~;m0;296~;21:03463:8g8bf>{t=k>1<7=t=4`1>g6<5<h86564=4`2>=><uz?i97>52z?6f6<e827>n<4m2:p1g0=838p187m:c2890>a20?0q~;m7;296~;21>0>563:988bf>{t=j31<7<t=4`g>=><5<h36ll4}r7`e?6=:r7>nh478:?6f<<fj2wx9nl50;0x90e62k:018m=:878yv3dk3:1>v3:c686f>;2l?0i<6s|5bf94?4|5<i?6o>4=4`;><3<uz?hi7>52z?6g6<e827>n4466:p1f`=838p18lj:c2890d?20<0q~;k0;296~;2jm0i<63:bb8:2>{t=m;1<7<t=4a3>g6<5<hi6484}r7g6?6=:r7>nk4m0:?6fd<?02wx9i=50;0x90e4212018m=:``8yv3c<3:1>v3:c986f>;2ll0i<6s|5e794?4|5<i>6o>4=4`:><3<uz?o57>53z?6`2<e827>h5478:?6`3<e:2wx9io50;0x90b?2k:018j9:9:8yv3cj3:1>v3:c68a4>;2jk0296s|5ea94?4|5<hm6564=4`a>dd<uz?oh7>52z?6g5<?027>nn4nb:p1`7=839p18ji:c2890c7212018jj:9:8yv3b:3:1>v3:e18a4>;2ll0i>6s|5d194?4|5<i36o>4=4``><3<uz?n87>52z?6g1<2127>o;4nb:p1c0=838p18kn:9:890c22hh0q~;i7;296~;2mk03463:e78bf>{t=o21<7<t=4gf>g6<5<om64;4}r7e=?6=:r7>j94:b:?546<e82wx9ko50;0x90`62k:018k::878yv3aj3:1>v3:f18a4>;2m?02:6s|5ga94?4|5<oi6o>4=4g6><0<uz?mh7>52z?6ad<e827>i4466:p1cc=838p18kk:c2890c?20<0q~;if;296~;2mj0i<63:e68;<>{t>9:1<7<t=4d3>=><5<om6ll4}r435?6=:r7>j84:b:?54g<e82wx:=<50;0x90`52k:018k9:878yv07>3:1?v39058a4>;18<034639028a6>{t>9=1<7<t=726>g6<5?:86564}r43<?6=:r7>j94m0:?6a=<>=2wx:=750;0x90cd212018k7:``8yv07i3:1>v3:ee8;<>;2m00jn6s|61g94?5|5?:h6o>4=72g>=><5?:i6564}r43b?6=:r7=<i4m0:?54g<e:2wx:<>50;0x90`22k:018k6:878yv0693:1>v3:f086=>;2n:0jn6s|63194?4|5?;<6564=731>dd<uz<987>52z?55=<?027==>4nb:p273=838p1;?m:c28937d20?0q~8=6;296~;1:80>n639318a4>{t>;=1<7<t=73f>g6<5?;964;4}r41<?6=:r7==i4m0:?556<>>2wx:?750;0x937?2k:01;?=:848yv05i3:1>v39168a4>;19?02:6s|63`94?4|5?;j6o>4=736><0<uz<9o7>52z?55<<e827==9478:p27b=838p1;?k:9:8937d2hh0q~8=e;296~;1:;0>n639398a4>{t>;l1<7<t=73e>g6<5?;864;4}r407?6=;r7=?<4m0:?577<?027=?=4m2:p262=838p1;==:c2893572120q~8<5;296~;1:80i<639148:1>{t>:<1<7<t=73:>=><5?;>6ll4}r403?6=:r7==l478:?553<fj2wx:>l50;1x935>2k:01;=n:9:8935?2120q~8<c;296~;1;h0i<639398a6>{t>:n1<7<t=701>g6<5?;=64;4}r40a?6=:r7==h4:9:?565<fj2wx:8>50;0x932321201;=i:``8yv0293:1>v39448;<>;1<90jn6s|64094?4|5?>36o>4=76:><3<uz<>?7>52z?50`<2j27=9i4m0:p202=838p1;:m:c28935a20?0q~8:5;296~;1<h0i<639418:2>{t><<1<7<t=766>g6<5?9m6484}r463?6=:r7=894m0:?506<>>2wx:8650;0x93202k:01;:=:848yv0213:1>v39478a4>;1<80346s|64c94?4|5?>j6564=76:>dd<uz<>n7>52z?50c<2j27=:84m0:p20e=838p1;:l:c28932720?0q~890;297~;1=l0i<6395g8;<>;1=m0i>6s|67394?4|5??m6o>4=77g>=><uz<=>7>52z?50`<e827=8?465:p235=838p1;:9:9:893252hh0q~894;296~;1<>034639428bf>{t>?21<7=t=745>g6<5?<<6564=746>=><uz<=57>52z?522<e827=:84m2:p23g=838p1;:i:c28932420?0q~89b;296~;1<k0>56394e8bf>{t>>n1<7<t=752>=><5?<h6ll4}r44a?6=:r7=;?478:?52a<fj2wx::h50;0x93122k:01;99:878yv0?83:1>v397c86f>;10h0i<6s|69394?4|5?=36o>4=74`><3<uz<3>7>52z?532<e827=:i466:p2=5=838p1;9=:c28930d20<0q~874;296~;1?80i<639718:2>{t>1?1<7<t=757>g6<5?<m6484}r4;2?6=:r7=;>4m0:?52`<?02wx:5950;0x931021201;99:``8yv0?03:1>v397b86f>;11;0i<6s|69;94?4|5?=26o>4=74g><3<uz<3h7>53z?5<g<e827=4n478:?5<d<e:2wx:5k50;0x93>d2k:01;6n:9:8yv0?n3:1>v397c8a4>;1>o0296s|68294?4|5?=86564=74e>dd<uz<2=7>52z?531<?027=;=4nb:p2<3=839p1;7<:c2893?321201;7=:9:8yv0>>3:1>v39958a4>;11;0i>6s|68594?4|5?=h6o>4=753><3<uz<247>52z?53=<2127=;l4nb:p2dg=838p1;7j:9:893?>2hh0q~8nb;296~;11o0346399`8bf>{t>hi1<7<t=7c1>g6<5?k864;4}r4b`?6=:r7=m54:b:?5f2<e82wx:lk50;0x93g22k:01;76:878yv0fn3:1>v39a58a4>;11h02:6s|6c294?4|5?3m6o>4=7;:><0<uz<i=7>52z?5=`<e827=5i466:p2g4=838p1;o>:c2893?d20<0q~8m3;296~;1i90i<6399c8;<>{t>k>1<7<t=7c7>=><5?k86ll4}r4a1?6=:r7=m44:b:?5fc<e82wx:o850;0x93g12k:01;7n:878yv0ei3:1?v39b98a4>;1j0034639b68a6>{t>kh1<7<t=7`:>g6<5?h<6564}r4ag?6=:r7=m54m0:?5=f<>=2wx:oj50;0x93g721201;7l:``8yv0em3:1>v39a08;<>;11m0jn6s|6b094?5|5?i;6o>4=7a2>=><5?hm6564}r4`7?6=:r7=o<4m0:?5fc<e:2wx:n:50;0x93g>2k:01;7k:878yv0d=3:1>v39a486=>;1i>0jn6s|6e594?4|5?ii6564=7a5>dd<uz<o47>52z?5gf<?027=o:4nb:p2a?=838p1;mi:c2893b720?0q~8ka;296~;1l<0>n639e58a4>{t>mh1<7<t=7f1>g6<5?i=64;4}r4gg?6=:r7=h<4m0:?5g2<>>2wx:ij50;0x93ed2k:01;m9:848yv0cm3:1>v39cc8a4>;1kh02:6s|6ed94?4|5?in6o>4=7a:><0<uz<n<7>52z?5ga<e827=o5478:p2`7=838p1;j>:9:893b72hh0q~8j2;296~;1l?0>n639eb8a4>{t>l91<7<t=7f0>g6<5?i<64;4}r4f3?6=;r7=i84m0:?5a3<?027=i94m2:p2`>=838p1;k9:c2893c32120q~8j9;296~;1l<0i<639c88:1>{t>lk1<7<t=7ag>=><5?i26ll4}r4ff?6=:r7=oh478:?5gd<fj2wx:hh50;1x93cc2k:01;kj:9:893cd2120q~8i0;296~;1ml0i<639eb8a6>{t>o;1<7<t=7f5>g6<5?ij64;4}r4e6?6=:r7=h?4:9:?5`1<fj2wx;=:50;0x93`?21201;h<:``8yv17=3:1>v39f88;<>;1n=0jn6s|71494?4|5?lh6o>4=7dg><3<uz=;;7>52z?447<2j27<=<4m0:p35>=838p1;hi:c2893`420?0q~9?9;296~;1nl0i<639f58:2>{t?9k1<7<t=7d:>g6<5?l86484}r53f?6=:r7=j54m0:?5b2<>>2wx;=m50;0x93`e2k:01;h9:848yv17l3:1>v39f`8a4>;1n<0346s|71g94?4|5?ln6564=7dg>dd<uz=;j7>52z?446<2j27<=44m0:p346=838p1:>?:c2893`320?0q~9>4;297~;09;0i<638128;<>;0980i>6s|70794?4|5>;86o>4=632>=><uz=::7>52z?447<e827=j;465:p341=838p1;hn:9:893`12hh0q~9>8;296~;1nk034639f68bf>{t?8i1<7=t=63b>g6<5>;i6564=63:>=><uz=:h7>52z?45g<e827<=44m2:p34c=838p1:><:c2893`020?0q~9>f;296~;1no0>5638008bf>{t?:;1<7<t=606>=><5>8;6ll4}r506?6=:r7<>;478:?464<fj2wx;>=50;0x924>2k:01:<n:878yv14<3:1>v382g86f>;0;l0i<6s|72794?4|5>8h6o>4=603><3<uz=8:7>52z?46g<e827<><466:p361=838p1:<9:c28924720<0q~9<8;296~;0:<0i<638258:2>{t?:31<7<t=60;>g6<5>886484}r50e?6=:r7<>:4m0:?467<?02wx;>l50;0x924e21201:<n:``8yv14k3:1>v383186f>;0<?0i<6s|72f94?4|5>8o6o>4=602><3<uz=?=7>53z?47c<e827<8=478:?47`<e:2wx;9<50;0x92272k:01:=j:9:8yv13;3:1>v382g8a4>;0::0296s|75694?4|5>8<6564=600>dd<uz=?97>52z?46=<?027<>94nb:p31?=839p1::8:c28922?21201::9:9:8yv13i3:1>v38498a4>;0<?0i>6s|75`94?4|5>9;6o>4=607><3<uz=?o7>52z?46f<2127<>h4nb:p30c=838p1:;=:9:8922c2hh0q~9:f;296~;0=:0346384d8bf>{t??:1<7<t=675>g6<5>?<64;4}r555?6=:r7<9n4:b:?42g<e82wx;;<50;0x923>2k:01::k:878yv11;3:1>v38598a4>;0<l02:6s|77694?4|5>?86o>4=66g><0<uz==97>52z?417<e827<9<466:p330=838p1:;::c28923720<0q~997;296~;0==0i<6384g8;<>{t??21<7<t=67;>=><5>?<6ll4}r55=?6=:r7<9i4:b:?436<e82wx;;o50;0x923f2k:01::j:878yv11m3:1?v386b8a4>;0>m0346386c8a6>{t??l1<7<t=64g>g6<5><i6564}r544?6=:r7<9n4m0:?415<>=2wx;:?50;0x923321201:;?:``8yv10:3:1>v38548;<>;0=80jn6s|76494?5|5>=?6o>4=656>=><5>=86564}r543?6=:r7<;84m0:?436<e:2wx;:650;0x923c2k:01:;>:878yv1013:1>v385886=>;0=k0jn6s|79`94?4|5>=m6564=65b>dd<uz=3o7>52z?4<5<?027<;o4nb:p3=b=838p1:6<:c2892>320?0q~97e;296~;0000>n638998a4>{t?1l1<7<t=6:5>g6<5>=j64;4}r5:4?6=:r7<484m0:?43g<>>2wx;4?50;0x92>72k:01:9n:848yv1>:3:1>v387g8a4>;0?l02:6s|78194?4|5>296o>4=65g><0<uz=287>52z?4<4<e827<;n478:p3<3=838p1:6::9:892>32hh0q~966;296~;00h0>n638a18a4>{t?0=1<7<t=6:4>g6<5>=i64;4}r5:f?6=;r7<544m0:?4=d<?027<554m2:p3<e=838p1:7n:c2892??2120q~96d;296~;0000i<6387e8:1>{t?0o1<7<t=6:2>=><5>=o6ll4}r5:b?6=:r7<4?478:?43`<fj2wx;l=50;1x92g62k:01:o=:9:892g72120q~9n4;296~;0i;0i<638a18a6>{t?h?1<7<t=6:b>g6<5>=n64;4}r5b2?6=:r7<4;4:9:?4<=<fj2wx;o650;0x92gd21201:o8:``8yv1e13:1>v38ae8;<>;0i10jn6s|7cc94?4|5>h;6o>4=6`2><3<uz=in7>52z?4f3<2j27<o84m0:p3ge=838p1:l<:c2892g020?0q~9md;296~;0j;0i<638a98:2>{t?ko1<7<t=6cg>g6<5>k<6484}r5ab?6=:r7<mn4m0:?4eg<>>2wx;n>50;0x92ga2k:01:on:848yv1d93:1>v38ad8a4>;0i00346s|7b094?4|5>h96564=6`2>dd<uz=h?7>52z?4f2<2j27<oi4m0:p3f2=838p1:l;:c2892g?20?0q~9l8;297~;0k?0i<638c68;<>;0k<0i>6s|7b;94?4|5>i<6o>4=6a6>=><uz=hm7>52z?4f3<e827<ml465:p3fd=838p1:oj:9:892gf2hh0q~9lc;296~;0io034638ac8bf>{t?m:1<7=t=6af>g6<5>im6564=6ag>=><uz=o=7>52z?4gc<e827<oi4m2:p3a4=838p1:l8:c2892ge20?0q~9k3;296~;0j:0>5638b48bf>{t?l?1<7<t=6f:>=><5>n?6ll4}r5f2?6=:r7<hl478:?4`0<fj2wx;h950;0x92bc2k:01:jj:878yv1b03:1>v38e286f>;0n;0i<6s|7d;94?4|5>o;6o>4=6f7><3<uz=nm7>52z?4`c<e827<h8466:p3`d=838p1:jn:c2892b320<0q~9jc;296~;0l00i<638d98:2>{t?ln1<7<t=6f`>g6<5>n<6484}r5fa?6=:r7<ho4m0:?4`3<?02wx;hh50;0x92ba21201:jj:``8yv1a83:1>v38e586f>;0nh0i<6s|7g394?4|5>o:6o>4=6f6><3<uz=m97>53z?4b6<e827<j9478:?4b7<e:2wx;k850;0x92`32k:01:h=:9:8yv1a?3:1>v38e28a4>;0l>0296s|7g:94?4|5>ni6564=6f4>dd<uz=m57>52z?4`f<?027<h54nb:p3cb=839p1:hm:c2892`d21201:hn:9:8yv1am3:1>v38fb8a4>;0nh0i>6s|7gd94?4|5>o?6o>4=6f;><3<uz2;<7>52z?4a5<2127<i?4nb:p<44=838p15>9:9:89=662hh0q~6>3;296~;?8>034637038bf>{t08>1<7<t=92b>g6<51:i64;4}r:21?6=:r73==4:b:?;5c<e82wx4<850;0x9=6c2k:015>>:878yv>6?3:1>v370b8a4>;?8;02:6s|80:94?4|51:<6o>4=922><0<uz2:57>52z?;43<e8273<8466:p<4g=838p15>6:c289=6320<0q~6>b;296~;?810i<637028;<>{t08i1<7<t=92`>=><51:i6ll4}r:2`?6=:r73=<4:b:?;62<e82wx4<k50;0x9=6b2k:015>=:878yv>5:3:1?v37218a4>;?:80346371g8a6>{t0;91<7<t=902>g6<51;m6564}r:10?6=:r73==4m0:?;41<>=2wx4?;50;0x9=6?212015>;:``8yv>5>3:1>v37088;<>;?8<0jn6s|83c94?5|51836o>4=90:>=><518<6564}r:1f?6=:r73>44m0:?;62<e:2wx4?m50;0x9=762k:015>::878yv>5l3:1>v370e86=>;?8o0jn6s|82d94?4|51986564=90f>dd<uz2?<7>52z?;71<?0273>k4nb:p<17=838p15=8:c289=5?20?0q~6;2;296~;?;m0>n6374b8a4>{t0=91<7<t=91b>g6<518n64;4}r:70?6=:r73?44m0:?;6c<>>2wx49;50;0x9=532k:015<j:848yv>3>3:1>v37328a4>;?;;02:6s|85594?4|519=6o>4=912><0<uz2?47>52z?;70<e8273?=478:p<1?=838p15=6:9:89=5?2hh0q~6;a;296~;?;l0>n637558a4>{t0=h1<7<t=91a>g6<518m64;4}r:7b?6=;r738i4m0:?;0`<?02738n4m2:p<06=838p15:j:c289=2d2120q~6:1;296~;?;m0i<637308:1>{t0<81<7<t=916>=><519:6ll4}r:67?6=:r73?;478:?;77<fj2wx48950;1x9=322k:015;9:9:89=332120q~6:8;296~;?=?0i<637558a6>{t0<31<7<t=91f>g6<519964;4}r:6e?6=:r73?l4:9:?;7f<fj2wx4;m50;0x9=07212015;m:``8yv>1l3:1>v37608;<>;?=j0jn6s|87g94?4|51<?6o>4=946><3<uz2=j7>52z?;2d<2j273;44m0:p<26=838p1588:c289=3e20?0q~681;296~;?>?0i<6375b8:2>{t0>81<7<t=942>g6<51?i6484}r:47?6=:r73:=4m0:?;1c<>>2wx4::50;0x9=042k:015;j:848yv>0=3:1>v37638a4>;?=m0346s|86494?4|51<=6564=946>dd<uz2<;7>52z?;2g<2j2734<4m0:p<2>=838p1587:c289=3d20?0q~68c;297~;??h0i<6377c8;<>;??00i>6s|86f94?4|51=i6o>4=95:>=><uz2<i7>52z?;2d<e82739h465:p<2`=838p158=:9:89=3b2hh0q~670;296~;?>:0346375g8bf>{t01>1<7=t=9:1>g6<51286564=9:2>=><uz2397>52z?;<6<e82734<4m2:p<=0=838p158m:c289=3a20?0q~677;296~;?>>0>5637688bf>{t0031<7<t=9:g>=><51236ll4}r::e?6=:r734h478:?;<<<fj2wx44l50;0x9=?62k:0157=:878yv>>k3:1>v379686f>;?i?0i<6s|88f94?4|513?6o>4=9:;><3<uz22i7>52z?;=6<e827344466:p<<`=838p156j:c289=>?20<0q~6n0;296~;?0m0i<6378b8:2>{t0h;1<7<t=9;3>g6<512i6484}r:b6?6=:r734k4m0:?;<d<?02wx4l=50;0x9=?42120157=:``8yv>f<3:1>v379986f>;?il0i<6s|8`794?4|513>6o>4=9::><3<uz2j57>53z?;e2<e8273m5478:?;e3<e:2wx4lo50;0x9=g?2k:015o9:9:8yv>fj3:1>v37968a4>;?0k0296s|8`a94?4|512m6564=9:a>dd<uz2jh7>52z?;=5<?02734n4nb:p<g7=839p15oi:c289=d7212015oj:9:8yv>e:3:1>v37b18a4>;?il0i>6s|8c194?4|51336o>4=9:`><3<uz2i87>52z?;=1<212735;4nb:p<f0=838p15ln:9:89=d22hh0q~6l7;296~;?jk034637b78bf>{t0j21<7<t=9`f>g6<51hm64;4}r:`=?6=:r73o94:b:?;`6<e82wx4no50;0x9=e62k:015l::878yv>dj3:1>v37c18a4>;?j?02:6s|8ba94?4|51hi6o>4=9`6><0<uz2hh7>52z?;fd<e8273n4466:p<fc=838p15lk:c289=d?20<0q~6lf;296~;?jj0i<637b68;<>{t0m:1<7<t=9a3>=><51hm6ll4}r:g5?6=:r73o84:b:?;`g<e82wx4i<50;0x9=e52k:015l9:878yv>c>3:1?v37d58a4>;?l<034637d28a6>{t0m=1<7<t=9f6>g6<51n86564}r:g<?6=:r73o94m0:?;f=<>=2wx4i750;0x9=dd212015l7:``8yv>ci3:1>v37be8;<>;?j00jn6s|8eg94?5|51nh6o>4=9fg>=><51ni6564}r:gb?6=:r73hi4m0:?;`g<e:2wx4h>50;0x9=e22k:015l6:878yv>b93:1>v37c086=>;?k:0jn6s|8g194?4|51o<6564=9g1>dd<uz2m87>52z?;a=<?0273i>4nb:p<c3=838p15km:c289=cd20?0q~6i6;296~;?n80>n636018a4>{t0o=1<7<t=9gf>g6<51o964;4}r:e<?6=:r73ii4m0:?;a6<>>2wx4k750;0x9=c?2k:015k=:848yv>ai3:1>v37e68a4>;?m?02:6s|8g`94?4|51oj6o>4=9g6><0<uz2mo7>52z?;a<<e8273i9478:p<cb=838p15kk:9:89=cd2hh0q~6ie;296~;?n;0>n636098a4>{t0ol1<7<t=9ge>g6<51o864;4}r;37?6=;r72<<4m0:?:47<?0272<=4m2:p=52=838p14>=:c289<672120q~7?5;296~;?n80i<637e48:1>{t19<1<7<t=9g:>=><51o>6ll4}r;33?6=:r73il478:?;a3<fj2wx5=l50;1x9<6>2k:014>n:9:89<6?2120q~7?c;296~;>8h0i<636098a6>{t19n1<7<t=9d1>g6<51o=64;4}r;3a?6=:r73ih4:9:?;b5<fj2wx5?>50;0x9<73212014>i:``8yv?593:1>v36148;<>;>990jn6s|93094?4|50;36o>4=83:><3<uz39?7>52z?:5`<2j272>i4m0:p=72=838p14?m:c289<6a20?0q~7=5;296~;>9h0i<636118:2>{t1;<1<7<t=836>g6<50:m6484}r;13?6=:r72=94m0:?:56<>>2wx5?650;0x9<702k:014?=:848yv?513:1>v36178a4>;>980346s|93c94?4|50;j6564=83:>dd<uz39n7>52z?:5c<2j272?84m0:p=7e=838p14?l:c289<7720?0q~7<0;297~;>:l0i<6362g8;<>;>:m0i>6s|92394?4|508m6o>4=80g>=><uz38>7>52z?:5`<e8272=?465:p=65=838p14?9:9:89<752hh0q~7<4;296~;>9>034636128bf>{t1:21<7=t=815>g6<509<6564=816>=><uz3857>52z?:72<e8272?84m2:p=6g=838p14?i:c289<7420?0q~7<b;296~;>9k0>56361e8bf>{t1:o1<7<t=81g><0<509h6o?4}r;74?6=:r72?k478:?:7f<e82wx59=50;0x9<2520<014:>:c38yv?3=3:1>v36458;<>;><80i<6s|95:94?4|50><6484=865>g7<uz3?m7>52z?:0<<?02728;4m0:p=1b=838p14:l:8489<2e2k;0q~7;f;296~;><l0346364c8a4>{t1<81<7<t=872><0<50?;6o?4}r;60?6=:r729>478:?:15<e82wx58950;0x9<3120<014;::c38yv?213:1>v36598;<>;>=<0i<6s|94a94?4|50?i6484=87b>g7<uz3>i7>52z?:1a<?02729l4m0:p=37=838p148?:8489<3a2k;0q~793;296~;>>;0346365g8a4>{t1?<1<7<t=846><0<50<?6o?4}r;5<?6=:r72::478:?:21<e82wx5;l50;0x9<0f20<01486:c38yv?1l3:1>v366b8;<>;>>00i<6s|96294?4|50<m6484=84f>g7<uz3<>7>52z?:34<?0272:h4m0:p=23=838p149;:8489<142k;0q~787;296~;>??034636728a4>{t1>k1<7<t=85:><0<50=36o?4}r;4g?6=:r72;o478:?:3=<e82wx5:h50;0x9<1b20<0149k:c38yv??93:1>v36818;<>;>?m0i<6s|99694?4|50286484=8:1>g7<uz33:7>52z?:<0<?02724?4m0:p==?=838p1467:8489<>02k;0q~77b;296~;>0h034636868a4>{t11o1<7<t=8:g><0<502h6o?4}r;:4?6=:r724k478:?:<f<e82wx54=50;0x9<?520<0147>:c38yv?>=3:1>v36958;<>;>180i<6s|98:94?4|503<6484=8;5>g7<uz32m7>52z?:=<<?02725;4m0:p=<b=838p147l:8489<?e2k;0q~76f;296~;>1l0346369c8a4>{t1h81<7<t=8c2><0<50k;6o?4}r;b0?6=:r72m>478:?:e5<e82wx5l950;0x9<g120<014o::c38yv?f13:1>v36a98;<>;>i<0i<6s|9`a94?4|50ki6484=8cb>g7<uz3ji7>52z?:ea<?0272ml4m0:p=g7=838p14l?:8489<ga2k;0q~7m3;296~;>j;034636ag8a4>{t1k<1<7<t=8`6><0<50h?6o?4}r;a<?6=:r72n:478:?:f1<e82wx5ol50;0x9<df20<014l6:c38yv?el3:1>v36bb8;<>;>j00i<6s|9b294?4|50hm6484=8`f>g7<uz3h>7>52z?:g4<?0272nh4m0:p=f3=838p14m;:8489<e42k;0q~7l7;296~;>k?034636c28a4>{t1jk1<7<t=8a:><0<50i36o?4}r;`g?6=:r72oo478:?:g=<e82wx5nh50;0x9<eb20<014mk:c38yv?c93:1>v36d18;<>;>km0i<6s|9e694?4|50n86484=8f1>g7<uz3o:7>52z?:`0<?0272h?4m0:p=a?=838p14j7:8489<b02k;0q~7kb;296~;>lh034636d68a4>{t1mi1<7=t=8g4>0b<50oj68j4=8g0><c<uz3oh7>53z?:ag<2l272ih4:d:?:a2<>m2wx5ik50;0x9<`62<n014km:8g8yv?cn3:1>v36e58;<>;>m?0jn6s|9d294?4|50o36564=8gb>dd<uz3n=7>52z?:af<?0272ih4nb:p=`4=838p14ki:9:89<`62hh0q~7i2;297~;>m<0jn636e28a7>;>m?02h6s|9g194?5|50o26ll4=8g4>g5<50oj64j4}r;e0?6=;r72ii4nb:?:ag<e;272ih46d:p=c3=838p14h?:``89<`620n0q~7ia;297~;>n?0i<636f68;<>;>n002:6s|9g`94?4|50l<6o>4=8d:><3<uz3mo7>55z?:b=<fj272ik4:b:?:af<2j272i54:b:?:a1<2j2wx5kj50;7x9<`>2hh014ki:c089<cd2k8014k7:c089<c32k80q~o?5;296~;f8=0i<63n018;<>{ti9<1<7;t=`27>0`<5h:;68h4=`22>0`<5h:868h4=8df>dd<uzk;;7>53z?b45<e827j<<478:?:bc<?02wxm=650;0x9d662k:014hi:c08yvg713:1>v3n028a4>;f8;0346s|a1c94?4|5h:96o>4=8df><3<uzk?>7>52z?b06<e827j8<478:pe=e=838p1<?::848962d2k:0q~o7d;296~;6:102:63>138a4>{ti1o1<7<t=01a><0<588>6o>4}rc;b?6=:r7:8h466:?27=<e82wxm4>50;0x940620<01<:m:c28yvg>93:1>v3>758:2>;6=l0i<6s|a8094?4|582<6484=052>g6<uzk2?7>52z?2=d<>>27:494m0:pe<2=838p1<ok:84894?02k:0q~o65;296~;6k902:63>a`8a4>{ti0<1<7<t=0f0><0<5ol1n=5rs`;4>5<5s4;n:779;<3a`?d73tyj554?:3y>5c?=1?16=h=5b19~wd?>2909w0<?c;;5?87a>3h;7p}n9`83>7}::8l15;5221;9f5=z{h3i6=4={<006??1348:o7l?;|qb=f<72;q6>9;5979>67`=j91vl7k:181842033=70<;2;`3?xuf1l0;6?u227`9=3=::<?1n=5rs`;e>5<5s48<i779;<05<?d73tyjm=4?:3y>6<7=1?16>:l5b19~wdg62909w0<n4;;5?87c83h;7p}na383>7}::k=15;5229g9f5=z{hk86=4={<0`e??1348i87l?;|qbe1<72;q6?l85979>6f1=j91vlo::18185c;33=70=6e;`3?xufi?0;6?u24129=3=:;jh1n=5rs`c4>5<5s4>9h779;<1e<?d73tyjm54?:3y>00g=1?168?;5b19~wdg>2909w0:77;;5?822:3h;7p}na`83>7}:<k>15;5246d9f5=z{hki6=4={<6f5??134>jo7l?;|qbef<72;q6>ij5979>6d7=j91vlok:181837m33=70:k9;`3?xufil0;6?u252`9=3=:=9<1n=5rs`ce>5<5s4?=4779;<707?d73tyjn=4?:3y>1<3=1?169;>5b19~wdd62909w0;l2;;5?83?l3h;7p}nb383>7}:=ll15;525cc9f5=z{hh86=4={<42g??134?n;7l?;|qbf1<72;q6:975979>242=j91vll::181800>33=708;1;`3?xufj?0;6?u26`19=3=:>?o1n=5rs``4>5<5s48m<779;<0ge?d73tyjn54?:3y>2a6=1?16:4l5b19~wdd>2909w08id;;5?80d03h;7p}nb`83>7}:?;k15;526g79f5=z{hhi6=4={<563??134=9>7l?;|qbff<72;q6;5:5979>31`=j91vllk:18181e933=7098c;`3?xufjl0;6?u27eg9=3=:?h31n=5rs``e>5<5s42;n779;<5g2?d73tyjo=4?:3y><6>=1?164==5b19~wde62909w0695;;5?8>483h;7p}nc383>7}:;9915;522df9f5=z{hi86=4={<::6??1342>h7l?;|qbg1<72;q64oh5979><=g=j91vlm::1818>bk33=706m7;`3?xufk?0;6?u290;9=3=:0l>1n=5rs`a4>5<5s4h3h767;<;25?d73tyjo54?:3y>740=1?16?=>5b19~wde>2909w0==9;;5?856;3h;7p}nc`83>7}:;:i15;523349f5=z{hii6=4={<17b??1349857l?;|qbgf<72:q6m=m5899>e=d=j916m5o5899~wdec2908w0o?e;:;?8g7k3h;70o?b;:;?xufkl0;6>u2a029<==:i9o1n=52a1f9<==z{him6=4<{<c26?>?34k:<7l?;<c3b?>?3tyjh=4?:2y>e42=0116m<<5b19>e47=011vlj>:1808g6>32370o>4;`3?8g6;3237p}nd383>6}:i8214552a049f5=:i8?1455rs`f0>5<4s4k:m767;<c2<?d734k:;767;|qb`1<72:q6m<m5899>e4g=j916m<75899~wdb22908w0o>e;:;?8g6k3h;70o>b;:;?xufl?0;6>u234g9<==:;0k1n=5238`9<==z{hn<6=4<{<c14?>?34k:i7l?;<c2`?>?3tyjh54?:2y>e74=0116m?>5b19>e4`=011vlj6:1808g5<32370o=2;`3?8g593237p}nd`83>6}:i;<14552a369f5=:i;91455rs`fa>5<4s4k94767;<c12?d734k99767;|qb`f<72:q6m?o5899>e7>=j916m?95899~wdbc2908w0o=c;:;?8g5i3h;70o=9;:;?xufll0;6>u2a3g9<==:i;i1n=52a3`9<==z{hnm6=4<{<c04?>?34k9i7l?;<c1`?>?3tyji=4?:2y>e64=0116m>>5b19>e7`=011vlk>:180851832370=:e;`3?852n3237p}ne383>6}:i:>14552a209f5=:i:;1455rs`g0>5<4s4k8:767;<c00?d734k8?767;|qba1<72:q6m>65899>e60=j916m>;5899~wdc22908w0o<a;:;?8g403h;70o<7;:;?xufm?0;6>u2a2a9<==:i:k1n=52a2;9<==z{ho<6=4<{<c0a?>?34k8o7l?;<c0f?>?3tyji54?:2y>e16=0116m>k5b19>e6b=011vlk6:1808g3;32370o;0;`3?8g4n3237p}ne`83>6}:;?8145523729f5=:;?;1455rs`ga>5<4s49=8767;<156?d7349=?767;|qbaf<72:q6?;85899>732=j916?;;5899~wdcc2908w0=98;:;?851>3h;70=97;:;?xufml0;6>u237c9<==:;?21n=5237;9<==z{hom6=4<{<15g?>?349=m7l?;<15f?>?3tyjj=4?:2y>73c=0116?;m5b19>73b=011vlh>:180850832370=9e;`3?851n3237p}nf383>6}:;>81455234a9f5=:;<n1455rs`d0>5<4s49<8767;<144?d7349<=767;|qbb1<72:q6?:85899>722=j916?:;5899~wd`22908w0=88;:;?850>3h;70=87;:;?xufn?0;6>u236c9<==:;>21n=5236;9<==z{hl<6=4<{<14g?>?349<m7l?;<14f?>?3tyjj54?:2y>72c=0116?:m5b19>72b=011vlh6:18085?832370=8e;`3?850n3237p}nf`83>6}:;18145523929f5=:;1;1455rs`da>5<4s4938767;<1;6?d73493?767;|qbbf<72:q6?585899>7=2=j916?5;5899~wd`c2908w0=78;:;?850:3h;70=83;:;?xufnl0;6>u239c9<==:;1<1n=523959<==z{hlm6=4<{<1;g?>?3493m7l?;<1;f?>?3tyi<=4?:2y>7=e=j916?5j5899>=6e=011vo>>:1818?39323707<d;ca?xue8;0;6?u29549<==:1=81mo5rsc20>5<5s43?n767;<;73?ge3tyi<94?:3y>=06=011659m5ac9~wg622909w07:5;:;?8?293ki7p}m0783>7}:1<k145529449eg=z{k:<6=4={<;6b?>?343>n7om;|qa4=<72:q6?5k5899>7=>=j916?575899~wg6>2909w0794;:;?8?183ki7p}m0`83>7}:1?3145529779eg=z{k:i6=4={<;5a?>?343=m7om;|qa4f<72;q65:=5899>=3`=ik1vo>k:1818?0032370784;ca?xue8l0;6?u296f9<==:1>31mo5rsc2e>5<5s433>767;<;4a?ge3tyi==4?:3y>==1=011655=5ac9~wg762909w077c;:;?8??03ki7p}m1383>7}:10;1455299f9eg=z{k;86=4<{<1:4?>?3493i7l?;<1;b?>?3tyi=94?:3y>=<0=011654<5ac9~wg722909w076b;:;?8?>?3ki7p}m1783>7}:1h:1455298a9eg=z{k;<6=4={<;b1?>?343j=7om;|qa5=<72;q65lo5899>=d0=ik1vo?6:1818?fn323707nb;ca?xue9h0;6?u29c69<==:1k:1mo5rsc3a>5<5s43i5767;<;a1?ge3tyi=n4?:3y>=gc=01165oo5ac9~wg7c2909w07l3;:;?8?en3ki7p}m1d83>6}:;08145523829f5=:;0;1455rsc3e>5<5s43h4767;<;`0?ge3tyi>=4?:3y>=fb=01165n75ac9~wg462909w07k2;:;?8?dm3ki7p}m2383>7}:1m=145529e19eg=z{k886=4={<c71?>?343o47om;|qa61<72:q6m995899>e13=j916m9:5899~wg422908w0o;9;:;?8g3?3h;70o;6;:;?xue:?0;6>u2a5`9<==:i=31n=52a5:9<==z{k8<6=4<{<c7`?>?34k?n7l?;<c7e?>?3tyi>54?:2y>e1`=0116m9j5b19>e1e=011vo<6:18085><32370=62;`3?85>;3237p}m2`83>6}:i<;14552a5d9f5=:i=o1455rsc0a>5<4s4k>?767;<c65?d734k><767;|qa6f<72:q6m8;5899>e05=j916m8<5899~wg4c2908w0o:7;:;?8g2=3h;70o:4;:;?xue:l0;6>u2a4;9<==:i<=1n=52a449<==z{k8m6=4<{<c6f?>?34k>57l?;<c6<?>?3tyi?=4?:2y>e0b=0116m8l5b19>e0g=011vo=>:1808g2n32370o:d;`3?8g2k3237p}m3383>6}:i?;14552a4d9f5=:i<o1455rsc10>5<4s4k=?767;<c55?d734k=<767;|qa71<72:q6?485899>7<2=j916?4;5899~wg522908w0o95;:;?8g1;3h;70o92;:;?xue;?0;6>u2a759<==:i??1n=52a769<==z{k9<6=4<{<c5=?>?34k=;7l?;<c52?>?3tyi?54?:2y>e3d=0116m;75b19>e3>=011vo=6:1808g1l32370o9b;`3?8g1i3237p}m3`83>6}:i?l14552a7f9f5=:i?i1455rsc1a>5<4s4k<=767;<c5b?d734k=i767;|qa7f<72:q6m:=5899>e27=j916m:>5899~wg5c2908w0o85;:;?8g0;3h;70o82;:;?xue;l0;6>u2a659<==:i>?1n=52a669<==z{k9m6=4<{<1:<?>?3492:7l?;<1:3?>?3tyi8=4?:2y>e2?=0116m:95b19>e20=011vo:>:1808g0j32370o89;`3?8g003237p}m4383>6}:i>n14552a6`9f5=:i>k1455rsc60>5<4s4k<j767;<c4`?d734k<o767;|qa01<72:q6m5?5899>e2`=j916m:k5899~wg222908w0o73;:;?8g?93h;70o70;:;?xue<?0;6>u2a919f5=:i1814552a979<==z{k><6=4<{<c;3?>?34k397l?;<c;0?>?3tyi854?:2y>e=?=0116m595b19>e=0=011vo:6:1808g?j32370o79;`3?8g?03237p}m4`83>6}:;0k1455238:9f5=:;031455rsc6a>5<d9r7iik4m0:?:5c<e:272=h4m2:?:5f<2n272=o4:f:?;b7<e:273j<4m2:?;ac<2n273ih4:f:?;g0<e:273o94m2:?;g7<2n273o<4:f:?;==<e:2735:4m2:?;=0<2n273594:f:?;2g<e:273:l4m2:?;2=<2n273::4:f:?;7`<e:273?i4m2:?;7g<2n273?l4:f:?;54<e:273==4m2:?;4`<2n273<i4:f:?4a1<e:27<i>4m2:?4a4<2n27<i=4:f:?4f2<e:27<n;4m2:?4f1<2n27<n>4:f:?4<d<e:27<444m2:?4<2<2n27<4;4:f:?41a<e:27<9n4m2:?41d<2n27<944:f:?475<e:27<>k4m2:?46a<2n27<>n4:f:?446<e:27<<?4m2:?445<2n27=jk4:f:?5`3<e:27=h84m2:?5`6<2n27=h?4:f:?5e<<e:27=m54m2:?5e3<2n27=m84:f:?53f<e:27=;o4m2:?53<<2n27=;54:f:?50c<e:27=8h4m2:?50f<2n27=8o4:f:?567<e:27=><4m2:?55c<2n27==h4:f:?6b0<e:27>j94m2:?6b7<2n27>j<4:f:?6g=<e:27>o:4m2:?6g0<2n27>o94:f:?6=g<e:27>5l4m2:?6==<2n27>5:4:f:?62`<e:27>:i4m2:?62g<2n27>:l4:f:?604<e:27>8=4m2:?67`<2n27>?i4:f:?651<e:27>=>4m2:?654<2n27>==4:f:?7a2<e:27?i;4m2:?7a1<2n27?i>4:f:?7fd<e:27?n44m2:?7f2<2n27?n;4:f:?7<a<e:27?4n4m2:?7<d<2n27?444:f:?725<e:27?9k4m2:?71a<2n27?9n4:f:?776<e:27???4m2:?775<2n27?>k4:f:?743<e:27?<84m2:?746<2n27?<?4:f:?0`<<e:278h54m2:?0`3<2n278h84:f:?0ef<e:278mo4m2:?0e<<2n278m54:f:?1gf<2n279oo4:f:?1f<<2n279n54:f:?1=6<2n2795?4:f:?1<5<2n279;k4:f:?12a<2n279:n4:f:?11d<2n279944:f:?102<2n2798;4:f:?171<2n279?>4:f:?164<2n279>=4:f:?14`<2n279<i4:f:?2bg<2n27:jl4:f:?2a=<2n27:i:4:f:?2g7<2n27:o<4:f:?2ec<2n27:mh4:f:?2=f<2n27:5o4:f:?2<<<2n27:454:f:?233<2n27:;84:f:?226<2n27::?4:f:?215<2n27:8k4:f:?27a<2n27:?n4:f:?26d<2n27:>44:f:?252<2n27:=;4:f:?014<2n2789=4:f:?07`<2n278?i4:f:?06g<2n278>l4:f:?05=<2n278=:4:f:?040<2n278<94:f:?1b7<2n279j<4:f:?1`c<2n279hh4:f:?1e3<2n279m84:f:?2`0<2n27:h94:f:?241<2n27:<>4:f:pf1e=838p1o6j:8789gbf2k:0q~l;d;296~;f<=0i<63<5e86f>{tj=o1<7<t=`7;>g6<5:?m68l4}r`7b?6=:r7j9l4m0:?024<2j2wxn8>50;0x9d3d2k:01>8<:4`8yvd293:1>v3n5d8a4>;4><0>n6s|b4094?4|5h<;6o>4=244>0d<uzh>?7>52z?b27<e8278:44:b:pf02=838p1l8;:c28960e2<h0q~l:5;296~;f>?0i<63<6e86f>{tj<<1<7<t=`4;>g6<5:<m68l4}r`63?6=:r7j:l4m0:?034<2j2wxn8650;0x9d212k:01>9<:4`8yvd213:1>v3n6b8a4>;4?<0>n6s|b4c94?4|5h<n6o>4=254>0d<uzh>n7>52z?b35<e8278;44:b:pf0e=838p1l9=:c28961e2<h0q~l:d;296~;f?=0i<63<7e86f>{tj<o1<7<t=`55>g6<5:=m68l4}r`6b?6=:r7j;54m0:?0<4<2j2wxn;>50;0x9d1f2k:01>6<:4`8yvd193:1>v3n7b8a4>;40<0>n6s|b7094?4|5h=n6o>4=2:4>0d<uzh=?7>52z?b0=<e8278444:b:pf32=838p1l6?:c2896>e2<h0q~l95;296~;f0;0i<63<8e86f>{tj?<1<7<t=81e>0d<5h2?6o>4}r`53?6=:r72894:b:?b<3<e82wxn;650;0x9<2>2<h01l67:c28yvd113:1>v364d86f>;f0h0i<6s|b7c94?4|50?868l4=`2a>g6<uzh=n7>52z?:1=<2j27j<i4m0:pf3e=838p14;k:4`89d6a2k:0q~l9d;296~;>>;0>n63n108a4>{tj?o1<7<t=`6b>g6<5:2m68l4}r`5b?6=:r72::4:b:?b56<e82wxn:>50;0x9<0d2<h01l?::c28yvd093:1>v367086f>;f9>0i<6s|b6094?4|50==68l4=`3:>g6<uzh<?7>52z?:3g<2j27j=o4m0:pf22=838p146?:4`89d7c2k:0q~l85;296~;>0<0>n63n1g8a4>{tj><1<7<t=8:b>0d<5h8:6o>4}r`43?6=:r724k4:b:?b66<e82wxn:650;0x9<?32<h01l<::c28yvd013:1>v3n4b8a4>;4180>n6s|b6c94?4|503268l4=`04>g6<uzh<n7>52z?:=`<2j27j>44m0:pf2e=838p14o<:4`89d4e2k:0q~l8d;296~;>i10>n63n2e8a4>{tj>o1<7<t=8cg>0d<5h8m6o>4}r`4b?6=:r72n?4:b:?b74<e82wxn5>50;0x9<d02<h01l=<:c28yvd?93:1>v36bb86f>;f;<0i<6s|b9094?4|50i:68l4=`14>g6<uzh3?7>52z?:g3<2j27j?44m0:pf=2=838p1l:j:c2896?42<h0q~l75;296~;>kk0>n63n3c8a4>{tj1<1<7<t=8f3>0d<5h9o6o>4}r`;3?6=:r72h84:b:?b7c<e82wxn5650;0x9<bf2<h01l:>:c28yvd?13:1>v3n518a4>;41<0>n6s|b9c94?4|5h?96o>4=2;4>0d<uzh3n7>52z?b11<e8278544:b:pf=e=838p1l;9:c2896?e2<h0q~l7f;29=~;e100jn63mcg8a6>;ekj0i>63mc98a6>;ek=0i>63mc18a6>;ejj0i>63mb98a6>;ej=0i>6s|b8:94?4|5knj6564=cc1>dd<uzh2m7>52z?a=d<fj27i5h467:pf<d=838p1o7m:``89g?b2020q~l6c;296~;e1l02563m9b8bf>{tj0o1<7<t=c;f>dd<5kk964;4}r`:b?6=:r7i5k4nb:?ae7<>12wxnl>50;0x9gg72hh01o7j:878yvdf93:1>v3ma08bf>;ei;0246s|b`194?4|5kk86ll4=c;f><0<uzhj87>53z?af2<2l27inl4:d:?af6<>m2wxnl;50;1x9gde2<n01olj:4f89gd020o0q~ln6;297~;ejo0>h63mc386`>;ejk02i6s|b`594?5|5ki868j4=ca5>0b<5khm64k4}r`b<?6=;r7io:4:d:?agd<2l27io>46e:pfd?=839p1omm:4f89geb2<n01om8:8g8yvdfi3:1>v3md086`>;ekk02i6s|b``94?4|5kh?6564=c`5>dd<uzhjo7>52z?af=<?027inl4nb:pfdb=838p1oll:9:89gdb2hh0q~lne;296~;ek903463mc38bf>{tjhl1<7<t=ca7>=><5ki=6ll4}r`a4?6=:r7io5478:?agd<fj2wxno?50;0x9ged21201omj:``8yvde:3:1>v3mcg8;<>;el80jn6s|be094?5|5kh>6ll4=c`0>g5<5kh=64j4}r`g7?6=;r7in44nb:?af2<e;27inl46d:pfa2=839p1olk:``89gde2k901olj:8f8yvdc=3:1?v3mc08bf>;ejo0i?63mc38:`>{tjm<1<7=t=ca6>dd<5ki86o=4=ca5><b<uzho;7>53z?ag<<fj27io:4m3:?agd<>l2wxni650;1x9gec2hh01omm:c189geb20n0q~lk9;296~;el90jn63md08:`>{tjmh1<7<t=c;3>dd<5kk:6474}r`gg?6=:r7i5<4nb:?ae4<>02wxnij50;0x9g?52hh01oo>:858yvdcm3:1>v3m928bf>;ei802m6s|bed94?4|5k3?6ll4=c;e><?<uzhn<7>52z?a=0<fj27i5k468:pf`7=838p1o79:``89g?a20=0q~lj2;296~;e1>0jn63m9g8:e>{tjl91<7ot=c;4><3<5k3=64;4=c;6><3<5k3?64;4=c;0><3<5k3964;4=c;2><3<5k3;64;4=c`7>g6<5kh>64;4}r`f0?6=ir7i5:466:?a=3<>>27i58466:?a=1<>>27i5>466:?a=7<>>27i5<466:?a=5<>>27in54m0:?af<<>=2wxnh;50;cx9g?020=01o79:8589g?220=01o7;:8589g?420=01o7=:8589g?620=01o7?:8589gdd2k:01olk:878yvdb>3:1mv3m968:<>;e1?02463m948:<>;e1=02463m928:<>;e1;02463m908:<>;e1902463mc18a4>;ek80296s|bd594?2|5ki?6o>4=ca6><3<5k3m6484=cc2><0<uzhn47>54z?ag=<e827io4465:?a=c<>=27im<465:pf`?=839p1oml:c289gec20?01oo=:848yvdbi3:1?v3mcg8a4>;el902963ma38:3>{tjlh1<7<<{<;e<??2343o;7??;<;g6?77343hh7??;<;`<?77343h?7??;<;aa?77343i57??;<;a0?77343jj7??;<;be?77343j97??;<;b4?773432n7??;<;:2?773432=7??;<;;g?773433;7??;<;;6?77343<h7??;<;4<?77343<?7??;<;5a?77343=57??;<;50?77343>j7??;<;6e?77343>97??;<;64?77343?n7??;<;72?77343?=7??;<;0g?77343n87l?;<;f1??23tyiin4?:31x9<`?20<014j8:0389<b528;014mk:0389<e?28;014m<:0389<db28;014l6:0389<d328;014oi:0389<gf28;014o::0389<g728;0147m:0389<?128;0147>:0389<>d28;01468:0389<>528;0149k:0389<1?28;0149<:0389<0b28;01486:0389<0328;014;i:0389<3f28;014;::0389<3728;014:m:0389<2128;014:>:0389<5d28;014k7:c289<c>20?0q~ljd;2966}:1o215:529e5957=:1m81=?529bf957=:1j21=?529b1957=:1ko1=?529c;957=:1k>1=?529`d957=:1hk1=?529`7957=:1h:1=?5298`957=:10<1=?52983957=:11i1=?52995957=:1181=?5296f957=:1>21=?52961957=:1?o1=?5297;957=:1?>1=?5294d957=:1<k1=?52947957=:1<:1=?5295`957=:1=<1=?52953957=:1:i1=?529da9f5=:1ln1585rscgf>5<5;r72j5468:?:`2<6;272h?4>3:?:ga<6;272o54>3:?:g6<6;272nh4>3:?:f<<6;272n94>3:?:ec<6;272ml4>3:?:e0<6;272m=4>3:?:=g<6;2725;4>3:?:=4<6;2724n4>3:?:<2<6;2724?4>3:?:3a<6;272;54>3:?:36<6;272:h4>3:?:2<<6;272:94>3:?:1c<6;2729l4>3:?:10<6;2729=4>3:?:0g<6;2728;4>3:?:04<6;272?n4>3:?:ac<e8272j=465:pfc4=839p1oh?:c289g`621201oki:c08yvda;3:1>v3mf08a4>;emo0346srn0f:3?6=9rBij95rn0f:<?6=9rBij95rn0f:=?6=9rBij95rn0f:e?6=9rBij95rn0f:f?6=9rBij95rn0f:g?6=9rBij95rn0f:`?6=9rBij95rn0f:a?6=9rBij95rn0f:b?6=9rBij95rn0fb4?6=9rBij95rn0fb5?6=9rBij95rn0fb6?6=9rBij95rn0fb7?6=9rBij95rn0fb0?6=9rBij95rn0fb1?6=9rBij95rn0fb2?6=9rBij95rn0fb3?6=9rBij95rn0fb<?6=9rBij95rn0fb=?6=9rBij95rn0fbe?6=9rBij95rn0fbf?6=9rBij95rn0fbg?6=9rBij95rn0fb`?6=9rBij95rn0fba?6=9rBij95rn0fbb?6=9rBij95rn0fa4?6=9rBij95rn0fa5?6=9rBij95rn0fa6?6=9rBij95rn0fa7?6=9rBij95rn0fa0?6=9rBij95rn0fa1?6=9rBij95rn0fa2?6=9rBij95rn0fa3?6=9rBij95rn0fa<?6=9rBij95rn0fa=?6=9rBij95rn0fae?6=9rBij95rn0faf?6=9rBij95rn0fag?6=9rBij95rn0fa`?6=9rBij95rn0faa?6=9rBij95rn0fab?6=9rBij95rn0f`4?6=9rBij95rn0f`5?6=9rBij95rn0f`6?6=9rBij95rn0f`7?6=9rBij95rn0f`0?6=9rBij95rn0f`1?6=9rBij95rn0f`2?6=9rBij95rn0f`3?6=9rBij95rn0f`<?6=9rBij95rn0f`=?6=9rBij95rn0f`e?6=9rBij95rn0f`f?6=9rBij95rn0f`g?6=9rBij95rn0f``?6=9rBij95rn0f`a?6=9rBij95rn0f`b?6=9rBij95rn0fg4?6=9rBij95rn0fg5?6=9rBij95rn0fg6?6=9rBij95rn0fg7?6=9rBij95rn0fg0?6=9rBij95rn0fg1?6=9rBij95rn0fg2?6=9rBij95rn0fg3?6=9rPm47?t8`8~Lg`33td:hi650;3xLg`33td:hi750;3xLg`33td:hio50;3xLg`33td:hil50;3xLg`33td:him50;3xLg`33td:hij50;3xLg`33td:hik50;3xLg`33td:hih50;3xLg`33td:hh>50;3xLg`33td:hh?50;3xLg`33td:hh<50;3xLg`33td:hh=50;3xLg`33td:hh:50;3xLg`33td:hh;50;3xLg`33td:hh850;3xLg`33td:hh950;3xLg`33td:hh650;3xLg`33td:hh750;3xLg`33td:hho50;3xLg`33td:hhl50;3xLg`33td:hhm50;3xLg`33td:hhj50;3xLg`33td:hhk50;3xLg`33td:hhh50;3xLg`33td:hk>50;3xLg`33td:hk?50;3xLg`33td:hk<50;3xLg`33td:hk=50;3xLg`33td:hk:50;3xLg`33td:hk;50;3xLg`33td:hk850;3xLg`33td:hk950;3xLg`33td:hk650;3xLg`33td:hk750;3xLg`33td:hko50;3xLg`33td:hkl50;3xLg`33td:hkm50;3xLg`33td:hkj50;3xLg`33td:hkk50;3xLg`33td:hkh50;3xLg`33td:i=>50;3xLg`33td:i=?50;3xLg`33td:i=<50;3xLg`33td:i==50;3xLg`33td:i=:50;3xLg`33td:i=;50;3xLg`33td:i=850;3xLg`33td:i=950;3xLg`33td:i=650;3xLg`33td:i=750;3xLg`33td:i=o50;3xLg`33td:i=l50;3xLg`33td:i=m50;3xLg`33td:i=j50;3xLg`33td:i=k50;3xLg`33td:i=h50;3xLg`33td:i<>50;3xLg`33td:i<?50;3xLg`33td:i<<50;3xLg`33td:i<=50;3xLg`33td:i<:50;3xLg`33td:i<;50;3xLg`33td:i<850;3xLg`33td:i<950;3xLg`33td:i<650;3xLg`33td:i<750;3xLg`33td:i<o50;3xLg`33td:i<l50;3xLg`33td:i<m50;3xLg`33td:i<j50;3xLg`33td:i<k50;3xLg`33td:i<h50;3xLg`33td:i?>50;3xLg`33td:i??50;3xLg`33td:i?<50;3xLg`33td:i?=50;3xLg`33td:i?:50;3xLg`33td:i?;50;3xLg`33td:i?850;3xLg`33td:i?950;3xLg`33td:i?650;3xLg`33td:i?750;3xLg`33td:i?o50;3xLg`33td:i?l50;3xLg`33td:i?m50;3xLg`33td:i?j50;3xLg`33td:i?k50;3xLg`33td:i?h50;3xLg`33td:i>>50;3xLg`33td:i>?50;3xLg`33td:i><50;3xLg`33td:i>=50;3xLg`33td:i>:50;3xLg`33td:i>;50;3xLg`33td:i>850;3xLg`33td:i>950;3xLg`33td:i>650;3xLg`33td:i>750;3xLg`33td:i>o50;3xLg`33td:i>l50;3xLg`33td:i>m50;3xLg`33td:i>j50;3xLg`33td:i>k50;3xLg`33td:i>h50;3xLg`33td:i9>50;3xLg`33td:i9?50;3xLg`33td:i9<50;3xLg`33td:i9=50;3xLg`33td:i9:50;3xLg`33td:i9;50;3xLg`33td:i9850;3xLg`33td:i9950;3xLg`33td:i9650;3xLg`33td:i9750;3xLg`33td:i9o50;3xLg`33td:i9l50;3xLg`33td:i9m50;3xLg`33td:i9j50;3xLg`33td:i9k50;3xLg`33td:i9h50;3xLg`33td:i8>50;3xLg`33td:i8?50;3xLg`33td:i8<50;3xLg`33td:i8=50;3xLg`33td:i8:50;3xLg`33td:i8;50;3xLg`33td:i8850;3xLg`33td:i8950;3xLg`33td:i8650;3xLg`33td:i8750;3xLg`33td:i8o50;3xLg`33td:i8l50;3xLg`33td:i8m50;3xLg`33td:i8j50;3xLg`33td:i8k50;3xLg`33td:i8h50;3xLg`33td:i;>50;3xLg`33td:i;?50;3xLg`33td:i;<50;3xLg`33td:i;=50;3xLg`33td:i;:50;3xLg`33td:i;;50;3xLg`33td:i;850;3xLg`33td:i;950;3xLg`33td:i;650;3xLg`33td:i;750;3xLg`33td:i;o50;3xLg`33td:i;l50;3xLg`33td:i;m50;3xLg`33td:i;j50;3xLg`33td:i;k50;3xLg`33td:i;h50;3xLg`33td:i:>50;3xLg`33td:i:?50;3xLg`33td:i:<50;3xLg`33td:i:=50;3xLg`33td:i::50;3xLg`33td:i:;50;3xLg`33td:i:850;3xLg`33td:i:950;3xLg`33td:i:650;3xLg`33td:i:750;3xLg`33td:i:o50;3xLg`33td:i:l50;3xLg`33td:i:m50;3xLg`33td:i:j50;3xLg`33td:i:k50;3xLg`33td:i:h50;3xLg`33td:i5>50;3xLg`33td:i5?50;3xLg`33td:i5<50;3xLg`33td:i5=50;3xLg`33td:i5:50;3xLg`33td:i5;50;3xLg`33td:i5850;3xLg`33td:i5950;3xLg`33td:i5650;3xLg`33td:i5750;3xLg`33td:i5o50;3xLg`33td:i5l50;3xLg`33td:i5m50;3xLg`33td:i5j50;3xLg`33td:i5k50;3xLg`33td:i5h50;3xLg`33td:i4>50;3xLg`33td:i4?50;3xLg`33td:i4<50;3xLg`33td:i4=50;3xLg`33td:i4:50;3xLg`33td:i4;50;3xLg`33td:i4850;3xLg`33td:i4950;3xLg`33td:i4650;3xLg`33td:i4750;3xLg`33td:i4o50;3xLg`33td:i4l50;3xLg`33td:i4m50;3xLg`33td:i4j50;3xLg`33td:i4k50;3xLg`33td:i4h50;3xLg`33td:il>50;3xLg`33td:il?50;3xLg`33td:il<50;3xLg`33td:il=50;3xLg`33td:il:50;3xLg`33td:il;50;3xLg`33td:il850;3xLg`33td:il950;3xLg`33td:il650;3xLg`33td:il750;3xLg`33td:ilo50;3xLg`33td:ill50;3xLg`33td:ilm50;3xLg`33td:ilj50;3xLg`33td:ilk50;3xLg`33td:ilh50;3xLg`33td:io>50;3xLg`33td:io?50;3xLg`33td:io<50;3xLg`33td:io=50;3xLg`33td:io:50;3xLg`33td:io;50;3xLg`33td:io850;3xLg`33td:io950;3xLg`33td:io650;3xLg`33td:io750;3xLg`33td:ioo50;3xLg`33td:iol50;3xLg`33td:iom50;3xLg`33td:ioj50;3xLg`33td:iok50;3xLg`33td:ioh50;3xLg`33td:in>50;3xLg`33td:in?50;3xLg`33td:in<50;3xLg`33td:in=50;3xLg`33td:in:50;3xLg`33td:in;50;3xLg`33td:in850;3xLg`33td:in950;3xLg`33td:in650;3xLg`33td:in750;3xLg`33td:ino50;3xLg`33td:inl50;3xLg`33td:inm50;3xLg`33td:inj50;3xLg`33td:ink50;3xLg`33td:inh50;3xLg`33td:ii>50;3xLg`33td:ii?50;3xLg`33td:ii<50;3xLg`33td:ii=50;3xLg`33td:ii:50;3xLg`33td:ii;50;3xLg`33td:ii850;3xLg`33td:ii950;3xLg`33td:ii650;3xLg`33td:ii750;3xLg`33td:iio50;3xLg`33td:iil50;3xLg`33td:iim50;3xLg`33td:iij50;3xLg`33td:iik50;3xLg`33td:iih50;3xLg`33td:ih>50;3xLg`33td:ih?50;3xLg`33td:ih<50;3xLg`33td:ih=50;3xLg`33td:ih:50;3xLg`33td:ih;50;3xLg`33td:ih850;3xLg`33td:ih950;3xLg`33td:ih650;3xLg`33td:ih750;3xLg`33td:iho50;3xLg`33td:ihl50;3xLg`33td:ihm50;3xLg`33td:ihj50;3xLg`33td:ihk50;3xLg`33td:ihh50;3xLg`33td:ik>50;3xLg`33td:ik?50;3xLg`33td:ik<50;3xLg`33td:ik=50;3xLg`33td:ik:50;3xLg`33td:ik;50;3xLg`33td:ik850;3xLg`33td:ik950;3xLg`33td:ik650;3xLg`33td:ik750;3xLg`33td:iko50;3xLg`33td:ikl50;3xLg`33td:ikm50;3xLg`33td:ikj50;3xLg`33td:ikk50;3xLg`33td:ikh50;3xLg`33td:j=>50;3xLg`33td:j=?50;3xLg`33td:j=<50;3xLg`33td:j==50;3xLg`33td:j=:50;3xLg`33td:j=;50;3xLg`33td:j=850;3xLg`33td:j=950;3xLg`33td:j=650;3xLg`33td:j=750;3xLg`33td:j=o50;3xLg`33td:j=l50;3xLg`33td:j=m50;3xLg`33td:j=j50;3xLg`33td:j=k50;3xLg`33td:j=h50;3xLg`33td:j<>50;3xLg`33td:j<?50;3xLg`33td:j<<50;3xLg`33td:j<=50;3xLg`33td:j<:50;3xLg`33td:j<;50;3xLg`33td:j<850;3xLg`33td:j<950;3xLg`33td:j<650;3xLg`33td:j<750;3xLg`33td:j<o50;3xLg`33td:j<l50;3xLg`33td:j<m50;3xLg`33td:j<j50;3xLg`33td:j<k50;3xLg`33td:j<h50;3xLg`33td:j?>50;3xLg`33td:j??50;3xLg`33td:j?<50;3xLg`33td:j?=50;3xLg`33td:j?:50;3xLg`33td:j?;50;3xLg`33td:j?850;3xLg`33td:j?950;3xLg`33td:j?650;3xLg`33td:j?750;3xLg`33td:j?o50;3xLg`33td:j?l50;3xLg`33td:j?m50;3xLg`33td:j?j50;3xLg`33td:j?k50;3xLg`33td:j?h50;3xLg`33td:j>>50;3xLg`33td:j>?50;3xLg`33td:j><50;3xLg`33td:j>=50;3xLg`33td:j>:50;3xLg`33td:j>;50;3xLg`33td:j>850;3xLg`33td:j>950;3xLg`33td:j>650;3xLg`33td:j>750;3xLg`33td:j>o50;3xLg`33td:j>l50;3xLg`33td:j>m50;3xLg`33td:j>j50;3xLg`33td:j>k50;3xLg`33td:j>h50;3xLg`33td:j9>50;3xLg`33td:j9?50;3xLg`33td:j9<50;3xLg`33td:j9=50;3xLg`33td:j9:50;3xLg`33td:j9;50;3xLg`33td:j9850;3xLg`33td:j9950;3xLg`33td:j9650;3xLg`33td:j9750;3xLg`33td:j9o50;3xLg`33td:j9l50;3xLg`33td:j9m50;3xLg`33td:j9j50;3xLg`33td:j9k50;3xLg`33td:j9h50;3xLg`33td:j8>50;3xLg`33td:j8?50;3xLg`33td:j8<50;3xLg`33td:j8=50;3xLg`33td:j8:50;3xLg`33td:j8;50;3xLg`33td:j8850;3xLg`33td:j8950;3xLg`33td:j8650;3xLg`33td:j8750;3xLg`33td:j8o50;3xLg`33td:j8l50;3xLg`33td:j8m50;3xLg`33td:j8j50;3xLg`33td:j8k50;3xLg`33td:j8h50;3xLg`33td:j;>50;3xLg`33td:j;?50;3xLg`33td:j;<50;3xLg`33td:j;=50;3xLg`33td:j;:50;3xLg`33td:j;;50;3xLg`33td:j;850;3xLg`33td:j;950;3xLg`33td:j;650;3xLg`33td:j;750;3xLg`33td:j;o50;3xLg`33td:j;l50;3xLg`33td:j;m50;3xLg`33td:j;j50;3xLg`33td:j;k50;3xLg`33td:j;h50;3xLg`33td:j:>50;3xLg`33td:j:?50;3xLg`33td:j:<50;3xLg`33td:j:=50;3xLg`33td:j::50;3xLg`33td:j:;50;3xLg`33td:j:850;3xLg`33td:j:950;3xLg`33td:j:650;3xLg`33td:j:750;3xLg`33td:j:o50;3xLg`33td:j:l50;3xLg`33td:j:m50;3xLg`33td:j:j50;3xLg`33td:j:k50;3xLg`33td:j:h50;3xLg`33td:j5>50;3xLg`33td:j5?50;3xLg`33td:j5<50;3xLg`33td:j5=50;3xLg`33td:j5:50;3xLg`33td:j5;50;3xLg`33td:j5850;3xLg`33td:j5950;3xLg`33td:j5650;3xLg`33td:j5750;3xLg`33td:j5o50;3xLg`33td:j5l50;3xLg`33td:j5m50;3xLg`33td:j5j50;3xLg`33td:j5k50;3xLg`33td:j5h50;3xLg`33td:j4>50;3xLg`33td:j4?50;3xLg`33td:j4<50;3xLg`33td:j4=50;3xLg`33td:j4:50;3xLg`33td:j4;50;3xLg`33td:j4850;3xLg`33td:j4950;3xLg`33td:j4650;3xLg`33td:j4750;3xLg`33td:j4o50;3xLg`33td:j4l50;3xLg`33td:j4m50;3xLg`33td:j4j50;3xLg`33td:j4k50;3xLg`33td:j4h50;3xLg`33td:jl>50;3xLg`33td:jl?50;3xLg`33td:jl<50;3xLg`33td:jl=50;3xLg`33td:jl:50;3xLg`33td:jl;50;3xLg`33td:jl850;3xLg`33td:jl950;3xLg`33td:jl650;3xLg`33td:jl750;3xLg`33td:jlo50;3xLg`33td:jll50;3xLg`33td:jlm50;3xLg`33td:jlj50;3xLg`33td:jlk50;3xLg`33td:jlh50;3xLg`33td:jo>50;3xLg`33td:jo?50;3xLg`33td:jo<50;3xLg`33td:jo=50;3xLg`33td:jo:50;3xLg`33td:jo;50;3xLg`33td:jo850;3xLg`33td:jo950;3xLg`33td:jo650;3xLg`33td:jo750;3xLg`33td:joo50;3xLg`33td:jol50;3xLg`33td:jom50;3xLg`33td:joj50;3xLg`33td:jok50;3xLg`33td:joh50;3xLg`33td:jn>50;3xLg`33td:jn?50;3xLg`33td:jn<50;3xLg`33td:jn=50;3xLg`33td:jn:50;3xLg`33td:jn;50;3xLg`33td:jn850;3xLg`33td:jn950;3xLg`33td:jn650;3xLg`33td:jn750;3xLg`33td:jno50;3xLg`33td:jnl50;3xLg`33td:jnm50;3xLg`33td:jnj50;3xLg`33td:jnk50;3xLg`33td:jnh50;3xLg`33td:ji>50;3xLg`33td:ji?50;3xLg`33td:ji<50;3xLg`33td:ji=50;3xLg`33td:ji:50;3xLg`33td:ji;50;3xLg`33td:ji850;3xLg`33td:ji950;3xLg`33td:ji650;3xLg`33td:ji750;3xLg`33td:jio50;3xLg`33td:jil50;3xLg`33td:jim50;3xLg`33td:jij50;3xLg`33td:jik50;3xLg`33td:jih50;3xLg`33td:jh>50;3xLg`33td:jh?50;3xLg`33td:jh<50;3xLg`33td:jh=50;3xLg`33td:jh:50;3xLg`33td:jh;50;3xLg`33td:jh850;3xLg`33td:jh950;3xLg`33td:jh650;3xLg`33td:jh750;3xLg`33td:jho50;3xLg`33td:jhl50;3xLg`33td:jhm50;3xLg`33td:jhj50;3xLg`33td:jhk50;3xLg`33td:jhh50;3xLg`33td:jk>50;3xLg`33td:jk?50;3xLg`33td:jk<50;3xLg`33td:jk=50;3xLg`33td:jk:50;3xLg`33td:jk;50;3xLg`33td:jk850;3xLg`33td:jk950;3xLg`33td:jk650;3xLg`33td:jk750;3xLg`33td:jko50;3xLg`33td:jkl50;3xLg`33td:jkm50;3xLg`33td:jkj50;3xLg`33td:jkk50;3xLg`33td:jkh50;3xLg`33td9<=>50;3xLg`33td9<=?50;3xLg`33td9<=<50;3xLg`33td9<==50;3xLg`33td9<=:50;3xLg`33td9<=;50;3xLg`33td9<=850;3xLg`33td9<=950;3xLg`33td9<=650;3xLg`33td9<=750;3xLg`33td9<=o50;3xLg`33td9<=l50;3xLg`33td9<=m50;3xLg`33td9<=j50;3xLg`33td9<=k50;3xLg`33td9<=h50;3xLg`33td9<<>50;3xLg`33td9<<?50;3xLg`33td9<<<50;3xLg`33td9<<=50;3xLg`33td9<<:50;3xLg`33td9<<;50;3xLg`33td9<<850;3xLg`33td9<<950;3xLg`33td9<<650;3xLg`33td9<<750;3xLg`33td9<<o50;3xLg`33td9<<l50;3xLg`33td9<<m50;3xLg`33td9<<j50;3xLg`33td9<<k50;3xLg`33td9<<h50;3xLg`33td9<?>50;3xLg`33td9<??50;3xLg`33td9<?<50;3xLg`33td9<?=50;3xLg`33td9<?:50;3xLg`33td9<?;50;3xLg`33td9<?850;3xLg`33td9<?950;3xLg`33td9<?650;3xLg`33td9<?750;3xLg`33td9<?o50;3xLg`33td9<?l50;3xLg`33td9<?m50;3xLg`33td9<?j50;3xLg`33td9<?k50;3xLg`33td9<?h50;3xLg`33td9<>>50;3xLg`33td9<>?50;3xLg`33td9<><50;3xLg`33td9<>=50;3xLg`33td9<>:50;3xLg`33td9<>;50;3xLg`33td9<>850;3xLg`33td9<>950;3xLg`33td9<>650;3xLg`33td9<>750;3xLg`33td9<>o50;3xLg`33td9<>l50;3xLg`33td9<>m50;3xLg`33td9<>j50;3xLg`33td9<>k50;3xLg`33td9<>h50;3xLg`33td9<9>50;3xLg`33td9<9?50;3xLg`33td9<9<50;3xLg`33td9<9=50;3xLg`33td9<9:50;3xLg`33td9<9;50;3xLg`33td9<9850;3xLg`33td9<9950;3xLg`33td9<9650;3xLg`33td9<9750;3xLg`33td9<9o50;3xLg`33td9<9l50;3xLg`33td9<9m50;3xLg`33td9<9j50;3xLg`33td9<9k50;3xLg`33td9<9h50;3xLg`33td9<8>50;3xLg`33td9<8?50;3xLg`33td9<8<50;3xLg`33td9<8=50;3xLg`33td9<8:50;3xLg`33td9<8;50;3xLg`33td9<8850;3xLg`33td9<8950;3xLg`33td9<8650;3xLg`33td9<8750;3xLg`33td9<8o50;3xLg`33td9<8l50;3xLg`33td9<8m50;3xLg`33td9<8j50;3xLg`33td9<8k50;3xLg`33td9<8h50;3xLg`33td9<;>50;3xLg`33td9<;?50;3xLg`33td9<;<50;3xLg`33td9<;=50;3xLg`33td9<;:50;3xLg`33td9<;;50;3xLg`33td9<;850;3xLg`33td9<;950;3xLg`33td9<;650;3xLg`33td9<;750;3xLg`33td9<;o50;3xLg`33td9<;l50;3xLg`33td9<;m50;3xLg`33td9<;j50;3xLg`33td9<;k50;3xLg`33td9<;h50;3xLg`33td9<:>50;3xLg`33td9<:?50;3xLg`33td9<:<50;3xLg`33td9<:=50;3xLg`33td9<::50;3xLg`33td9<:;50;3xLg`33td9<:850;3xLg`33td9<:950;3xLg`33td9<:650;3xLg`33td9<:750;3xLg`33td9<:o50;3xLg`33td9<:l50;3xLg`33td9<:m50;3xLg`33td9<:j50;3xLg`33td9<:k50;3xLg`33td9<:h50;3xLg`33td9<5>50;3xLg`33td9<5?50;3xLg`33td9<5<50;3xLg`33td9<5=50;3xLg`33td9<5:50;3xLg`33td9<5;50;3xLg`33td9<5850;3xLg`33td9<5950;3xLg`33td9<5650;3xLg`33td9<5750;3xLg`33td9<5o50;3xLg`33td9<5l50;3xLg`33td9<5m50;3xLg`33td9<5j50;3xLg`33td9<5k50;3xLg`33td9<5h50;3xLg`33td9<4>50;3xLg`33td9<4?50;3xLg`33td9<4<50;3xLg`33td9<4=50;3xLg`33td9<4:50;3xLg`33td9<4;50;3xLg`33td9<4850;3xLg`33td9<4950;3xLg`33td9<4650;3xLg`33td9<4750;3xLg`33td9<4o50;3xLg`33td9<4l50;3xLg`33td9<4m50;3xLg`33td9<4j50;3xLg`33td9<4k50;3xLg`33td9<4h50;3xLg`33td9<l>50;3xLg`33td9<l?50;3xLg`33td9<l<50;3xLg`33td9<l=50;3xLg`33td9<l:50;3xLg`33td9<l;50;3xLg`33td9<l850;3xLg`33td9<l950;3xLg`33td9<l650;3xLg`33td9<l750;3xLg`33td9<lo50;3xLg`33td9<ll50;3xLg`33td9<lm50;3xLg`33td9<lj50;3xLg`33td9<lk50;3xLg`33td9<lh50;3xLg`33td9<o>50;3xLg`33td9<o?50;3xLg`33td9<o<50;3xLg`33td9<o=50;3xLg`33td9<o:50;3xLg`33td9<o;50;3xLg`33td9<o850;3xLg`33td9<o950;3xLg`33td9<o650;3xLg`33td9<o750;3xLg`33td9<oo50;3xLg`33td9<ol50;3xLg`33td9<om50;3xLg`33td9<oj50;3xLg`33td9<ok50;3xLg`33td9<oh50;3xLg`33td9<n>50;3xLg`33td9<n?50;3xLg`33td9<n<50;3xLg`33td9<n=50;3xLg`33td9<n:50;3xLg`33td9<n;50;3xLg`33td9<n850;3xLg`33td9<n950;3xLg`33td9<n650;3xLg`33td9<n750;3xLg`33td9<no50;3xLg`33td9<nl50;3xLg`33td9<nm50;3xLg`33td9<nj50;3xLg`33td9<nk50;3xLg`33td9<nh50;3xLg`33td9<i>50;3xLg`33td9<i?50;3xLg`33td9<i<50;3xLg`33td9<i=50;3xLg`33td9<i:50;3xLg`33td9<i;50;3xLg`33td9<i850;3xLg`33td9<i950;3xLg`33td9<i650;3xLg`33td9<i750;3xLg`33td9<io50;3xLg`33td9<il50;3xLg`33td9<im50;3xLg`33td9<ij50;3xLg`33td9<ik50;3xLg`33td9<ih50;3xLg`33td9<h>50;3xLg`33td9<h?50;3xLg`33td9<h<50;3xLg`33td9<h=50;3xLg`33td9<h:50;3xLg`33td9<h;50;3xLg`33td9<h850;3xLg`33td9<h950;3xLg`33td9<h650;3xLg`33td9<h750;3xLg`33td9<ho50;3xLg`33td9<hl50;3xLg`33td9<hm50;3xLg`33td9<hj50;3xLg`33td9<hk50;3xLg`33td9<hh50;3xLg`33td9<k>50;3xLg`33td9<k?50;3xLg`33td9<k<50;3xLg`33td9<k=50;3xLg`33td9<k:50;3xLg`33td9<k;50;3xLg`33td9<k850;3xLg`33td9<k950;3xLg`33td9<k650;3xLg`33td9<k750;3xLg`33td9<ko50;3xLg`33td9<kl50;3xLg`33td9<km50;3xLg`33td9<kj50;3xLg`33td9<kk50;3xLg`33td9<kh50;3xLg`33td9==>50;3xLg`33td9==?50;3xLg`33td9==<50;3xLg`33td9===50;3xLg`33td9==:50;3xLg`33td9==;50;3xLg`33td9==850;3xLg`33td9==950;3xLg`33td9==650;3xLg`33td9==750;3xLg`33td9==o50;3xLg`33td9==l50;3xLg`33td9==m50;3xLg`33td9==j50;3xLg`33td9==k50;3xLg`33td9==h50;3xLg`33td9=<>50;3xLg`33td9=<?50;3xLg`33td9=<<50;3xLg`33td9=<=50;3xLg`33td9=<:50;3xLg`33td9=<;50;3xLg`33td9=<850;3xLg`33td9=<950;3xLg`33td9=<650;3xLg`33td9=<750;3xLg`33td9=<o50;3xLg`33td9=<l50;3xLg`33td9=<m50;3xLg`33td9=<j50;3xLg`33td9=<k50;3xLg`33td9=<h50;3xLg`33td9=?>50;3xLg`33td9=??50;3xLg`33td9=?<50;3xLg`33td9=?=50;3xLg`33td9=?:50;3xLg`33td9=?;50;3xLg`33td9=?850;3xLg`33td9=?950;3xLg`33td9=?650;3xLg`33td9=?750;3xLg`33td9=?o50;3xLg`33td9=?l50;3xLg`33td9=?m50;3xLg`33td9=?j50;3xLg`33td9=?k50;3xLg`33td9=?h50;3xLg`33td9=>>50;3xLg`33td9=>?50;3xLg`33td9=><50;3xLg`33td9=>=50;3xLg`33td9=>:50;3xLg`33td9=>;50;3xLg`33td9=>850;3xLg`33td9=>950;3xLg`33td9=>650;3xLg`33td9=>750;3xLg`33td9=>o50;3xLg`33td9=>l50;3xLg`33td9=>m50;3xLg`33td9=>j50;3xLg`33td9=>k50;3xLg`33td9=>h50;3xLg`33td9=9>50;3xLg`33td9=9?50;3xLg`33td9=9<50;3xLg`33td9=9=50;3xLg`33td9=9:50;3xLg`33td9=9;50;3xLg`33td9=9850;3xLg`33td9=9950;3xLg`33td9=9650;3xLg`33td9=9750;3xLg`33td9=9o50;3xLg`33td9=9l50;3xLg`33td9=9m50;3xLg`33td9=9j50;3xLg`33td9=9k50;3xLg`33td9=9h50;3xLg`33td9=8>50;3xLg`33td9=8?50;3xLg`33td9=8<50;3xLg`33td9=8=50;3xLg`33td9=8:50;3xLg`33td9=8;50;3xLg`33td9=8850;3xLg`33td9=8950;3xLg`33td9=8650;3xLg`33td9=8750;3xLg`33td9=8o50;3xLg`33td9=8l50;3xLg`33td9=8m50;3xLg`33td9=8j50;3xLg`33td9=8k50;3xLg`33td9=8h50;3xLg`33td9=;>50;3xLg`33td9=;?50;3xLg`33td9=;<50;3xLg`33td9=;=50;3xLg`33td9=;:50;3xLg`33td9=;;50;3xLg`33td9=;850;3xLg`33td9=;950;3xLg`33td9=;650;3xLg`33td9=;750;3xLg`33td9=;o50;3xLg`33td9=;l50;3xLg`33td9=;m50;3xLg`33td9=;j50;3xLg`33td9=;k50;3xLg`33td9=;h50;3xLg`33td9=:>50;3xLg`33td9=:?50;3xLg`33td9=:<50;3xLg`33td9=:=50;3xLg`33td9=::50;3xLg`33td9=:;50;3xLg`33td9=:850;3xLg`33td9=:950;3xLg`33td9=:650;3xLg`33td9=:750;3xLg`33td9=:o50;3xLg`33td9=:l50;3xLg`33td9=:m50;3xLg`33td9=:j50;3xLg`33td9=:k50;3xLg`33td9=:h50;3xLg`33td9=5>50;3xLg`33td9=5?50;3xLg`33td9=5<50;3xLg`33td9=5=50;3xLg`33td9=5:50;3xLg`33td9=5;50;3xLg`33td9=5850;3xLg`33td9=5950;3xLg`33td9=5650;3xLg`33td9=5750;3xLg`33td9=5o50;3xLg`33td9=5l50;3xLg`33td9=5m50;3xLg`33td9=5j50;3xLg`33td9=5k50;3xLg`33td9=5h50;3xLg`33td9=4>50;3xLg`33td9=4?50;3xLg`33td9=4<50;3xLg`33td9=4=50;3xLg`33td9=4:50;3xLg`33td9=4;50;3xLg`33td9=4850;3xLg`33td9=4950;3xLg`33td9=4650;3xLg`33td9=4750;3xLg`33td9=4o50;3xLg`33td9=4l50;3xLg`33td9=4m50;3xLg`33td9=4j50;3xLg`33td9=4k50;3xLg`33td9=4h50;3xLg`33td9=l>50;3xLg`33td9=l?50;3xLg`33td9=l<50;3xLg`33td9=l=50;3xLg`33td9=l:50;3xLg`33td9=l;50;3xLg`33td9=l850;3xLg`33td9=l950;3xLg`33td9=l650;3xLg`33td9=l750;3xLg`33td9=lo50;3xLg`33td9=ll50;3xLg`33td9=lm50;3xLg`33td9=lj50;3xLg`33td9=lk50;3xLg`33td9=lh50;3xLg`33td9=o>50;3xLg`33td9=o?50;3xLg`33td9=o<50;3xLg`33td9=o=50;3xLg`33td9=o:50;3xLg`33td9=o;50;3xLg`33td9=o850;3xLg`33td9=o950;3xLg`33td9=o650;3xLg`33td9=o750;3xLg`33td9=oo50;3xLg`33td9=ol50;3xLg`33td9=om50;3xLg`33td9=oj50;3xLg`33td9=ok50;3xLg`33td9=oh50;3xLg`33td9=n>50;3xLg`33td9=n?50;3xLg`33td9=n<50;3xLg`33td9=n=50;3xLg`33td9=n:50;3xLg`33td9=n;50;3xLg`33td9=n850;3xLg`33td9=n950;3xLg`33td9=n650;3xLg`33td9=n750;3xLg`33td9=no50;3xLg`33td9=nl50;3xLg`33td9=nm50;3xLg`33td9=nj50;3xLg`33td9=nk50;3xLg`33td9=nh50;3xLg`33td9=i>50;3xLg`33td9=i?50;3xLg`33td9=i<50;3xLg`33td9=i=50;3xLg`33td9=i:50;3xLg`33td9=i;50;3xLg`33td9=i850;3xLg`33td9=i950;3xLg`33td9=i650;3xLg`33td9=i750;3xLg`33td9=io50;3xLg`33td9=il50;3xLg`33td9=im50;3xLg`33td9=ij50;3xLg`33td9=ik50;3xLg`33td9=ih50;3xLg`33td9=h>50;3xLg`33td9=h?50;3xLg`33td9=h<50;3xLg`33td9=h=50;3xLg`33td9=h:50;3xLg`33td9=h;50;3xLg`33td9=h850;3xLg`33td9=h950;3xLg`33td9=h650;3xLg`33td9=h750;3xLg`33td9=ho50;3xLg`33td9=hl50;3xLg`33td9=hm50;3xLg`33td9=hj50;3xLg`33td9=hk50;3xLg`33td9=hh50;3xLg`33td9=k>50;3xLg`33td9=k?50;3xLg`33td9=k<50;3xLg`33td9=k=50;3xLg`33td9=k:50;3xLg`33td9=k;50;3xLg`33td9=k850;3xLg`33td9=k950;3xLg`33td9=k650;3xLg`33td9=k750;3xLg`33td9=ko50;3xLg`33td9=kl50;3xLg`33td9=km50;3xLg`33td9=kj50;3xLg`33td9=kk50;3xLg`33td9=kh50;3xLg`33td9>=>50;3xLg`33td9>=?50;3xLg`33td9>=<50;3xLg`33td9>==50;3xLg`33td9>=:50;3xLg`33td9>=;50;3xLg`33td9>=850;3xLg`33td9>=950;3xLg`33td9>=650;3xLg`33td9>=750;3xLg`33td9>=o50;3xLg`33td9>=l50;3xLg`33td9>=m50;3xLg`33td9>=j50;3xLg`33td9>=k50;3xLg`33td9>=h50;3xLg`33td9><>50;3xLg`33td9><?50;3xLg`33td9><<50;3xLg`33td9><=50;3xLg`33td9><:50;3xLg`33td9><;50;3xLg`33td9><850;3xLg`33td9><950;3xLg`33td9><650;3xLg`33td9><750;3xLg`33td9><o50;3xLg`33td9><l50;3xLg`33td9><m50;3xLg`33td9><j50;3xLg`33td9><k50;3xLg`33td9><h50;3xLg`33td9>?>50;3xLg`33td9>??50;3xLg`33td9>?<50;3xLg`33td9>?=50;3xLg`33td9>?:50;3xLg`33td9>?;50;3xLg`33td9>?850;3xLg`33td9>?950;3xLg`33td9>?650;3xLg`33td9>?750;3xLg`33td9>?o50;3xLg`33td9>?l50;3xLg`33td9>?m50;3xLg`33td9>?j50;3xLg`33td9>?k50;3xLg`33td9>?h50;3xLg`33td9>>>50;3xLg`33td9>>?50;3xLg`33td9>><50;3xLg`33td9>>=50;3xLg`33td9>>:50;3xLg`33td9>>;50;3xLg`33td9>>850;3xLg`33td9>>950;3xLg`33td9>>650;3xLg`33td9>>750;3xLg`33td9>>o50;3xLg`33td9>>l50;3xLg`33td9>>m50;3xLg`33td9>>j50;3xLg`33td9>>k50;3xLg`33td9>>h50;3xLg`33td9>9>50;3xLg`33td9>9?50;3xLg`33td9>9<50;3xLg`33td9>9=50;3xLg`33td9>9:50;3xLg`33td9>9;50;3xLg`33td9>9850;3xLg`33td9>9950;3xLg`33td9>9650;3xLg`33td9>9750;3xLg`33td9>9o50;3xLg`33td9>9l50;3xLg`33td9>9m50;3xLg`33td9>9j50;3xLg`33td9>9k50;3xLg`33td9>9h50;3xLg`33td9>8>50;3xLg`33td9>8?50;3xLg`33td9>8<50;3xLg`33td9>8=50;3xLg`33td9>8:50;3xLg`33td9>8;50;3xLg`33td9>8850;3xLg`33td9>8950;3xLg`33td9>8650;3xLg`33td9>8750;3xLg`33td9>8o50;3xLg`33td9>8l50;3xLg`33td9>8m50;3xLg`33td9>8j50;3xLg`33td9>8k50;3xLg`33td9>8h50;3xLg`33td9>;>50;3xLg`33td9>;?50;3xLg`33td9>;<50;3xLg`33td9>;=50;3xLg`33td9>;:50;3xLg`33td9>;;50;3xLg`33td9>;850;3xLg`33td9>;950;3xLg`33td9>;650;3xLg`33td9>;750;3xLg`33td9>;o50;3xLg`33td9>;l50;3xLg`33td9>;m50;3xLg`33td9>;j50;3xLg`33td9>;k50;3xLg`33td9>;h50;3xLg`33td9>:>50;3xLg`33td9>:?50;3xLg`33td9>:<50;3xLg`33td9>:=50;3xLg`33td9>::50;3xLg`33td9>:;50;3xLg`33td9>:850;3xLg`33td9>:950;3xLg`33td9>:650;3xLg`33td9>:750;3xLg`33td9>:o50;3xLg`33td9>:l50;3xLg`33td9>:m50;3xLg`33td9>:j50;3xLg`33td9>:k50;3xLg`33td9>:h50;3xLg`33td9>5>50;3xLg`33td9>5?50;3xLg`33td9>5<50;3xLg`33td9>5=50;3xLg`33td9>5:50;3xLg`33td9>5;50;3xLg`33td9>5850;3xLg`33td9>5950;3xLg`33td9>5650;3xLg`33td9>5750;3xLg`33td9>5o50;3xLg`33td9>5l50;3xLg`33td9>5m50;3xLg`33td9>5j50;3xLg`33td9>5k50;3xLg`33td9>5h50;3xLg`33td9>4>50;3xLg`33td9>4?50;3xLg`33td9>4<50;3xLg`33td9>4=50;3xLg`33td9>4:50;3xLg`33td9>4;50;3xLg`33td9>4850;3xLg`33td9>4950;3xLg`33td9>4650;3xLg`33td9>4750;3xLg`33td9>4o50;3xLg`33td9>4l50;3xLg`33td9>4m50;3xLg`33td9>4j50;3xLg`33td9>4k50;3xLg`33td9>4h50;3xLg`33td9>l>50;3xLg`33td9>l?50;3xLg`33td9>l<50;3xLg`33td9>l=50;3xLg`33td9>l:50;3xLg`33td9>l;50;3xLg`33td9>l850;3xLg`33td9>l950;3xLg`33td9>l650;3xLg`33td9>l750;3xLg`33td9>lo50;3xLg`33td9>ll50;3xLg`33td9>lm50;3xLg`33td9>lj50;3xLg`33td9>lk50;3xLg`33td9>lh50;3xLg`33td9>o>50;3xLg`33td9>o?50;3xLg`33td9>o<50;3xLg`33td9>o=50;3xLg`33td9>o:50;3xLg`33td9>o;50;3xLg`33td9>o850;3xLg`33td9>o950;3xLg`33td9>o650;3xLg`33td9>o750;3xLg`33td9>oo50;3xLg`33td9>ol50;3xLg`33td9>om50;3xLg`33td9>oj50;3xLg`33td9>ok50;3xLg`33td9>oh50;3xLg`33td9>n>50;3xLg`33td9>n?50;3xLg`33td9>n<50;3xLg`33td9>n=50;3xLg`33td9>n:50;3xLg`33td9>n;50;3xLg`33td9>n850;3xLg`33td9>n950;3xLg`33td9>n650;3xLg`33td9>n750;3xLg`33td9>no50;3xLg`33td9>nl50;3xLg`33td9>nm50;3xLg`33td9>nj50;3xLg`33td9>nk50;3xLg`33td9>nh50;3xLg`33td9>i>50;3xLg`33td9>i?50;3xLg`33td9>i<50;3xLg`33td9>i=50;3xLg`33td9>i:50;3xLg`33td9>i;50;3xLg`33td9>i850;3xLg`33td9>i950;3xLg`33td9>i650;3xLg`33td9>i750;3xLg`33td9>io50;3xLg`33td9>il50;3xLg`33td9>im50;3xLg`33td9>ij50;3xLg`33td9>ik50;3xLg`33td9>ih50;3xLg`33td9>h>50;3xLg`33td9>h?50;3xLg`33td9>h<50;3xLg`33td9>h=50;3xLg`33td9>h:50;3xLg`33td9>h;50;3xLg`33td9>h850;3xLg`33td9>h950;3xLg`33td9>h650;3xLg`33td9>h750;3xLg`33td9>ho50;3xLg`33td9>hl50;3xLg`33td9>hm50;3xLg`33td9>hj50;3xLg`33td9>hk50;3xLg`33td9>hh50;3xLg`33td9>k>50;3xLg`33td9>k?50;3xLg`33td9>k<50;3xLg`33td9>k=50;3xLg`33td9>k:50;3xLg`33td9>k;50;3xLg`33td9>k850;3xLg`33td9>k950;3xLg`33td9>k650;3xLg`33td9>k750;3xLg`33td9>ko50;3xLg`33td9>kl50;3xLg`33td9>km50;3xLg`33td9>kj50;3xLg`33td9>kk50;3xLg`33td9>kh50;3xLg`33td9?=>50;3xLg`33td9?=?50;3xLg`33td9?=<50;3xLg`33td9?==50;3xLg`33td9?=:50;3xLg`33td9?=;50;3xLg`33td9?=850;3xLg`33td9?=950;3xLg`33td9?=650;3xLg`33td9?=750;3xLg`33td9?=o50;3xLg`33td9?=l50;3xLg`33td9?=m50;3xLg`33td9?=j50;3xLg`33td9?=k50;3xLg`33td9?=h50;3xLg`33td9?<>50;3xLg`33td9?<?50;3xLg`33td9?<<50;3xLg`33td9?<=50;3xLg`33td9?<:50;3xLg`33td9?<;50;3xLg`33td9?<850;3xLg`33td9?<950;3xLg`33td9?<650;3xLg`33td9?<750;3xLg`33td9?<o50;3xLg`33td9?<l50;3xLg`33td9?<m50;3xLg`33td9?<j50;3xLg`33td9?<k50;3xLg`33td9?<h50;3xLg`33td9??>50;3xLg`33td9???50;3xLg`33td9??<50;3xLg`33td9??=50;3xLg`33td9??:50;3xLg`33td9??;50;3xLg`33td9??850;3xLg`33td9??950;3xLg`33td9??650;3xLg`33td9??750;3xLg`33td9??o50;3xLg`33td9??l50;3xLg`33td9??m50;3xLg`33td9??j50;3xLg`33td9??k50;3xLg`33td9??h50;3xLg`33td9?>>50;3xLg`33td9?>?50;3xLg`33td9?><50;3xLg`33td9?>=50;3xLg`33td9?>:50;3xLg`33td9?>;50;3xLg`33td9?>850;3xLg`33td9?>950;3xLg`33td9?>650;3xLg`33td9?>750;3xLg`33td9?>o50;3xLg`33td9?>l50;3xLg`33td9?>m50;3xLg`33td9?>j50;3xLg`33td9?>k50;3xLg`33td9?>h50;3xLg`33td9?9>50;3xLg`33td9?9?50;3xLg`33td9?9<50;3xLg`33td9?9=50;3xLg`33td9?9:50;3xLg`33td9?9;50;3xLg`33td9?9850;3xLg`33td9?9950;3xLg`33td9?9650;3xLg`33td9?9750;3xLg`33td9?9o50;3xLg`33td9?9l50;3xLg`33td9?9m50;3xLg`33td9?9j50;3xLg`33td9?9k50;3xLg`33td9?9h50;3xLg`33td9?8>50;3xLg`33td9?8?50;3xLg`33td9?8<50;3xLg`33td9?8=50;3xLg`33td9?8:50;3xLg`33td9?8;50;3xLg`33td9?8850;3xLg`33td9?8950;3xLg`33td9?8650;3xLg`33td9?8750;3xLg`33td9?8o50;3xLg`33td9?8l50;3xLg`33td9?8m50;3xLg`33td9?8j50;3xLg`33td9?8k50;3xLg`33td9?8h50;3xLg`33td9?;>50;3xLg`33td9?;?50;3xLg`33td9?;<50;3xLg`33td9?;=50;3xLg`33td9?;:50;3xLg`33td9?;;50;3xLg`33td9?;850;3xLg`33td9?;950;3xLg`33td9?;650;3xLg`33td9?;750;3xLg`33td9?;o50;3xLg`33td9?;l50;3xLg`33td9?;m50;3xLg`33td9?;j50;3xLg`33td9?;k50;3xLg`33td9?;h50;3xLg`33td9?:>50;3xLg`33td9?:?50;3xLg`33td9?:<50;3xLg`33td9?:=50;3xLg`33td9?::50;3xLg`33td9?:;50;3xLg`33td9?:850;3xLg`33td9?:950;3xLg`33td9?:650;3xLg`33td9?:750;3xLg`33td9?:o50;3xLg`33td9?:l50;3xLg`33td9?:m50;3xLg`33td9?:j50;3xLg`33td9?:k50;3xLg`33td9?:h50;3xLg`33td9?5>50;3xLg`33td9?5?50;3xLg`33td9?5<50;3xLg`33td9?5=50;3xLg`33td9?5:50;3xLg`33td9?5;50;3xLg`33td9?5850;3xLg`33td9?5950;3xLg`33td9?5650;3xLg`33td9?5750;3xLg`33td9?5o50;3xLg`33td9?5l50;3xLg`33td9?5m50;3xLg`33td9?5j50;3xLg`33td9?5k50;3xLg`33td9?5h50;3xLg`33td9?4>50;3xLg`33td9?4?50;3xLg`33td9?4<50;3xLg`33td9?4=50;3xLg`33td9?4:50;3xLg`33td9?4;50;3xLg`33td9?4850;3xLg`33td9?4950;3xLg`33td9?4650;3xLg`33td9?4750;3xLg`33td9?4o50;3xLg`33td9?4l50;3xLg`33td9?4m50;3xLg`33td9?4j50;3xLg`33td9?4k50;3xLg`33td9?4h50;3xLg`33td9?l>50;3xLg`33td9?l?50;3xLg`33td9?l<50;3xLg`33td9?l=50;3xLg`33td9?l:50;3xLg`33td9?l;50;3xLg`33td9?l850;3xLg`33td9?l950;3xLg`33td9?l650;3xLg`33td9?l750;3xLg`33td9?lo50;3xLg`33td9?ll50;3xLg`33td9?lm50;3xLg`33td9?lj50;3xLg`33td9?lk50;3xLg`33twvqMNL{3;`3?7f>123:isO@Cy3yEFWstJK
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/icon.ngc b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/icon.ngc
deleted file mode 100644
index f18d9c0..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/icon.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
-$3:75=6:2.Yi{g|inl9$4(581*/=6>;;12351=7898?7=>?459345>339::<95?0327?5638=1;<5>;;13341=799;?7=<?09937577:9:?7=:?0593<56638>0==>?1:07?7678=19==>>7:15>LHH]]0HCCZ]OM2?70<768=0?;4FNNWW>FII\[EG=1=::1<23>512@DDYY4LOOVQKI4;;<0;2<94378JJJSS2JEEX_AC3=16>5863=>08=>?4:6555c<>fs;8zif6:7)77<0=13<=>>0::0<4>509:8<<>=0168F466l2HXOL@PVHPWA]033K_MK55MUR]JJCI63J=0OL^[USG1?FC6:2ICINEPLHAFJVCX\PZN>6MF3:AOV<=DGDGBXYKKb:ALJQTHD96;2n5LOOVQKI6;994h7NAATSMO49766j1HCCZ]OM2?578d3JEEX_AC0=30:f=DGG^YCA>315<`?FII\[EG<1?:>b9@KKRUGE:7=;0l;BMMPWIK85;<2n5LOOVQKI6;914h7NAATSMO497>6k1HCCZ]OM2?5;e<KFD_^BB?<32=g>EHF]XD@=2=1?a8GJHSZFF;0?<1c:ALJQTHD969?3m4CNLWVJJ74;>5o6M@NUPLH5:5=7i0OB@[RNN38709k2IDBY\@L1>13;e<KFD_^BB?<3:=g>EHF]XD@=2=9?`8GJHSZFF;0?0l;BMMPWIK859;2n5LOOVQKI6;;84h7NAATSMO49556j1HCCZ]OM2?768d3JEEX_AC0=17:`=DGG^YCA>33483:f=DGG^YCA>334<a?FII\[EG<1=1b:ALJQTHD96?2o5LOOVQKI6;=7h0OB@[RNN3838e3JEEX_AC0=5=f>EHF]XD@=27>c9@KKRUGE:753l4CNLWVJJ6494h7NAATSMO59776j1HCCZ]OM3?548d3JEEX_AC1=31:f=DGG^YCA?312<`?FII\[EG=1?;>b9@KKRUGE;7=80l;BMMPWIK95;=2n5LOOVQKI7;9>4h7NAATSMO597?6j1HCCZ]OM3?5<8e3JEEX_AC1=3=g>EHF]XD@<2=0?a8GJHSZFF:0??1c:ALJQTHD869>3m4CNLWVJJ64;95o6M@NUPLH4:5<7i0OB@[RNN28739k2IDBY\@L0>12;e<KFD_^BB><35=g>EHF]XD@<2=8?a8GJHSZFF:0?71b:ALJQTHD8692n5LOOVQKI7;;94h7NAATSMO59566j1HCCZ]OM3?778d3JEEX_AC1=10:f=DGG^YCA?335<f?FII\[EG=1=::1<`?FII\[EG=1=:>c9@KKRUGE;7?3l4CNLWVJJ64=4i7NAATSMO5939j2IDBY\@L0>5:g=DGG^YCA?37?`8GJHSZFF:050m;BMMPWIK9535n6M@NUPLH7:76j1HCCZ]OM0?558d3JEEX_AC2=32:f=DGG^YCA<313<`?FII\[EG>1?<>b9@KKRUGE87=90l;BMMPWIK:5;>2n5LOOVQKI4;9?4h7NAATSMO69706j1HCCZ]OM0?5=8d3JEEX_AC2=3::g=DGG^YCA<31?a8GJHSZFF90?>1c:ALJQTHD;69=3m4CNLWVJJ54;85o6M@NUPLH7:5;7i0OB@[RNN18729k2IDBY\@L3>11;e<KFD_^BB=<34=g>EHF]XD@?2=7?a8GJHSZFF90?61c:ALJQTHD;6953l4CNLWVJJ54;4h7NAATSMO69576j1HCCZ]OM0?748d3JEEX_AC2=11:f=DGG^YCA<332<`?FII\[EG>1=;>d9@KKRUGE87?84?>b9@KKRUGE87?80m;BMMPWIK:595n6M@NUPLH7:36k1HCCZ]OM0?1;d<KFD_^BB=<7<a?FII\[EG>191b:ALJQTHD;632o5LOOVQKI4;17h0OB@[RNN0858d3JEEX_AC3=33:f=DGG^YCA=310<`?FII\[EG?1?=>b9@KKRUGE97=>0l;BMMPWIK;5;?2n5LOOVQKI5;9<4h7NAATSMO79716j1HCCZ]OM1?528d3JEEX_AC3=3;:f=DGG^YCA=318<a?FII\[EG?1?1c:ALJQTHD:69<3m4CNLWVJJ44;;5o6M@NUPLH6:5:7i0OB@[RNN08759k2IDBY\@L2>10;e<KFD_^BB<<37=g>EHF]XD@>2=6?a8GJHSZFF80?91c:ALJQTHD:6943m4CNLWVJJ44;35n6M@NUPLH6:56j1HCCZ]OM1?758d3JEEX_AC3=12:f=DGG^YCA=333<`?FII\[EG?1=<>b9@KKRUGE97?90j;BMMPWIK;59>6=0l;BMMPWIK;59>2o5LOOVQKI5;;7h0OB@[RNN0818e3JEEX_AC3=7=f>EHF]XD@>29>c9@KKRUGE97;3l4CNLWVJJ4414i7NAATSMO79?99=1HC_KPGDLFVDRNGGUBBKA8;BPFEQCC92N97IGl;EKPEGJBWC^JK95KRBI6?CGK[L90JIM;;GF@A6=ALL90JI\;;GFQA4d<N[EF,/JPCMI!$QI'*CUH@F,/THE2f>@UGD*)FRMCK#"WK%$CWJF@.-ZFG358BWIJ(+_TOAE- UM#&OYDDB(+=8>?0/234567(yY9;6H]OL"!QZEKC+*_C-,Z_BNH&%7289:%<=>?01"sW4=@;2MEH;5GE@F\H4=N:2C;>6G>2:K16>O4:2C?>6G:9:KMMQUSI]O87D@Ya:HWEBYD@HCE96DPCMI1?IO53EE=7AANDDF4?II@AJKG86BZT068HPR5<2F^X9:4LTV60>JR\?=0AXVLY^N6?HS_N<?0AXVI649NQ]@0k2Gjfb|Yesqjkke<E`dd~[k}shmm6>H7<2D:98:4N0750>H61:>0B<7;4:L2=02<F;8386@=2868J757<2D9:>:4N3470>H5><>0B?774:L1=<2<F::;;6@JTVMQO3=IGJFB\:5AOLGQC@7<G81[86^NRU0e?UCUAFN+.GQLLJ #75678':;<=>? qQ#LLAO(<:%<=>?01"&e>VNFVH^_DJWb:RJJZDR[GKFI45_K^JOQQHJ92[:7_;4RDQFP2=U]G^N_Y?4S29PAI3<[ACMX;5\OTP@A6=SKB90XIG<;UFL<>RBZDCEMA=4THE;?QOJMZZNO>5[MR58PKKXFL^27Y]PD^VL[O><\ZUASNBD9:VP[OYSGVN27Y]PU^VL[O?<\ZU^SYAPU59W]UC4=2_;#XQFCNL,MZ_B[VHXOL@!U^@P+LYR[LUXCKZMSBCM[@W7&\UIYKI<d:W3+PYNKFD$ERWJS^@PGDH)]VHX#DQY6/KP]K(NW\YNS^AITCQ@EKYBY9$^SO]=6:W3+PYNKFD$ERWJS^@PGDH)]VHX#dJ]CJ]OKFGK:k1^<"[PIBMM+PYDEM%LSYO]GDVX55[)AVDN<#[PT@PDAQ4e3\:$YRGLOO-V[FKC'NU_M_IJTZ32Y+OXFL:%YRZNRFGW6g=R8&_TENAA/T]@IA)@W]KYKHZT13_-MZHB8'_TXL\HEU0a?P6(]VCHCC!Z_BOG+BYSI[MNXV?<]/K\J@6)]V^J^JK[2c9V4*SXAJEE#XQLME-D[QGUOL^P=9S!I^LF4+SX\HXLIY<m;T2,QZODGG%^SNCK/F]WEWAB\R;>Q#GPEP2-QZRFZNO_>l5Z0.W\MFII'\UHAI!H_UCQC@R\>T$BSCK?.T]WEWAB\;k0Y=!Z_HALJ*SXKDN$KRZNRFGW_2[)AVDN<#[PT@PDAQ4f3\:$YRGLOO-V[FKC'NU_M_IJTZ:^*LYIM9$^SYO]GDV1e>S7'\UBOB@ U^AN@*AX\HXLIYU6]/K\J@6)]V^J^JK[2b9V4*SXAJEE#XQLME-V[FIJEHDOS^KC/H6-BL]7U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^77U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^76U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^75U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^74U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^73U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^72U'_T@XZ=c:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^7Z&\UGYY<l;T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_7[)]VF^X?m4U1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX7X(RWE__>n5Z0.W\MFII'\UHAI!Z_BMNIDHCWZOG#D:!FHY7Y+SXD\^9o6[?/T]JGJH(]VIFH"[PCNONEKBX[LF$E9 IIZ7^*PYK]]8h7X> U^K@KK)RWJGO#XQLOLOBJAYTME%B8#HF[7_-QZJR\;i0Y=!Z_HALJ*SXKDN$YRM@MLCM@ZUBD&C?"KGT7\,V[ISS:j1^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU7]/W\HPR5k2_;#XQFCNL,QZEJL&_TOBCBAOF\W@J(A=$MEV7R.T]OQQ4d3\:$YRGLOO-V[FKC'\UHC_KPIE]PAI)N<'LBW=S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP==S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=<S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=?S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=>S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=9S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=8S!U^NVP7e<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=P Z_MWW6f=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q9Q#[PLTV1g>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR9V"XQCUU0`?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS=W%YRBZT3a8Q5)RW@IDB"[PCLF,QZEHZLUBHR]JL.K7*CO\=T$^SA[[2b9V4*SXAJEE#XQLME-V[FIUMVCOS^KC/H6-BL]1U'_T@XZ=c:W3+PYNKFD$YRMBD.W\GJTBW@NT_HB I5,EM^1Z&\UGYY<l;T2,QZODGG%^SNCK/T]@KWCXAMUXIA!F4/DJ_=[)]VF^X?m4U1-V[LEHF&_TO@J U^ALV@YNLVYN@"G;.GKX=X(RWE__=:5Z0.W\MFII'\UHAI!Z_RGO[k7e3\:$YRGLOO-V[FKC'\U_M_IJT^AF53=R8&_TENAA/T]@IA)n[LFTb<l4U1-V[LEHF&_TO@J iUCQC@R;994:n6[?/T]JGJH(]VIFH"g[ASEFP97668k0Y=!Z_HALJ*SXKDN$eYO]GDV?<;7f3\:$YRGLOO-V[FKC'`^J^JK[<8<2e>S7'\UBOB@ U^AN@*oSI[MNXRMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V>R.G]@IA]7U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^6Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_46Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_46Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_47Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_47Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_44Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_44Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_45Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_45Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_42Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_42Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_43Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_43Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_4[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX5X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY1Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ0^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\8T$MSNCK[2_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]7U'LTO@JT3\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^6Z&OUHAIU;]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV:R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX4X(AWJGOW8S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY3Y+@XKDNP9P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ2^*CYDEMQ=Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[1_-BZEJLR<V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T0\,E[FKCS>W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\?T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V>R.G]@IA]?U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^>Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_<[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX=X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR;V"KQLMEY3Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS8W%JRMBDZ2^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[02^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[02^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[03^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[03^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[00^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[00^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[01^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[01^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[06^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[06^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[07^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[07^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[0_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]6U'LTO@JT1\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU=]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_4[)NVIFHV<R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX5X(AWJGOW>S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY2Y+@XKDNP?P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ3^*CYDEMQ?Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[0_-BZEJLR>V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T1\,E[FKCS<W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U>]/D\GHB\=T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V?R.G]@IA]1U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W<S!F^AN@^0Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP=P I_BOG_2[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ:Q#HPCLFX3X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR;V"KQLMEY;Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS8W%JRMBDZ:^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[8_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]6U'LTO@JT9\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^4Z&OUHAIU?]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_7[)NVIFHV>R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<>R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<>R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<?R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<?R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<<R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<<R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<=R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<=R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<:R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<:R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<;R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<;R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY1Y+@XKDNP=P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ9Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[3_-BZEJLR8V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T2\,E[FKCS:W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U=]/D\GHB\;T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V<R.G]@IA]3U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W?S!F^AN@^2Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP>P I_BOG_0[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ9Q#HPCLFX1X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR8V"KQLMEY5Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS;W%JRMBDZ4^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\:T$MSNCK[6_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]5U'LTO@JT7\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^4Z&OUHAIU7]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_7[)NVIFHV6R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW4S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY1Y+@XKDNP5P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ1^*CYDEMQ;Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[2_-BZEJLR:V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8:V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8:V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8;V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8;V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS88V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS88V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS89V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS89V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8>V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8>V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8?V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8?V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U<]/D\GHB\9T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]5U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W>S!F^AN@^4Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP?P I_BOG_6[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ8Q#HPCLFX7X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR9V"KQLMEY7Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS:W%JRMBDZ6^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\;T$MSNCK[4_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]4U'LTO@JT5\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^5Z&OUHAIU9]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_6[)NVIFHV8R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX7X(AWJGOW:S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY0Y+@XKDNP;P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ1^*CYDEMQ3Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[2_-BZEJLR2V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS0W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U<]/D\GHB\1T$^SAMJ1d9V4*SXAJEE#XQLTSN\KPR(]VIFHJ\_00g8Q5)RW@IDB"[PCUPO[JSS'\UHAII]P002?P6(]VCHCC!Z_BVQHZIR\&_THLZN_WCOMA4?3\:$YRGLOO-V[FRUDVE^X"gLOLOBJAY@ZYUXIA2?>3:8Q5)RW@IDB"[PCUPO[JSS'`IDA@OAD^EQTZUBD5;5>=5Z0.W\MFII'\UHX_BPOTV,mAGSIV\J@DJ=1:W3+PYNKFD$YR][AU-E[VRF\R:V"XQ\T@V15>S7'\UBOB@ U^QWEQ)AWZ^JXV?R.T]PPDR592_;#XQFCNL,QZUSI]%MS^ZNTZ0^*PYT\H^9=6[?/T]JGJH(]VY_MY!I_RVBP^5Z&\UXXLZ>a:W3+PYNKFD$YR][AU-V[FKCO[Z;=i5Z0.W\MFII'\UXXLZ U^FBPDYQIECO=l5Z0.W\MFII'\UXXLZ U^QWEQEJL8i0Y=!Z_HALJ*SX[]K_#XQ\T@V@IAYi:81^<"[PIBMM+PYT\H^$YR][AU]@JQ)DA5;5><5Z0.W\MFII'\UXXLZ U^QWEQYDF]%HE1<1209V4*SXAJEE#XQ\T@V,QZUSI]UHBY!LI=1=64=R8&_TENAA/T]PPDR(]VY_MYQLNU-@M929:81^<"[PIBMM+PYT\H^$YR][AU]@JQ)DA5?5>=5Z0.W\MFII'\UXXLZ U^QWEQYDF]%O0=0=0:W3+PYNKFD$YR][AU-V[VRF\VIEX"J31?03?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/E>1:76<]9%^SDM@N.W\WQGS'\UXXLZPCOV,@959:91^<"[PIBMM+PYT\H^$YR][AU]@JQ)C4=49<6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&N793<l;T2,QZODGG%^S^ZNT.W\WQGSWJD_#JU?]/EmL+SXE\RHU?94U1-V[LEHF&_T_YO[/T]PPDRXKG^$KV>R.T]E@WC5>2_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\8T$^SA[[299V4*SXAJEE#XQ\T@V,QZUSI]UHBY!H[1_-QZ^HZJS9o6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&MP=P HnI,V[HS_KP8<7X> U^K@KK)RWZ^JX"[PSUCW[FHS'NQ:Q#[PFEPF63=R8&_TENAA/T]PPDR(]VY_MYQLNU-D_4[)]VF^X?64U1-V[LEHF&_T_YO[/T]PPDRXKG^$KV?R.T][KWE^:j1^<"[PIBMM+PYT\H^$YR][AU]@JQ)@S;W%KcF!U^OV\F_5?2_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\:T$^SKJ]E348Q5)RW@IDB"[PSUCW+PYT\H^TOCZ GZ0^*PYK]]837X> U^K@KK)RWZ^JX"[PSUCW[FHS'NQ9Q#[PXNP@]7e<]9%^SDM@N.W\WQGS'\UXXLZPCOV,C^5Z&NdC"XQBUYAZ62=R8&_TENAA/T]PPDR(]VY_MYQLNU-D_6[)]VLO^H<9;T2,QZODGG%^S^ZNT.W\WQGSWJD_#JU<]/W\HPR502_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\;T$^SUA]CX0`?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/FY7Y+Ai@'_TAXVLY358Q5)RW@IDB"[PSUCW+PYT\H^TOCZ GZ6^*PYAL[O9:6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&MP8P Z_MWW6==R8&_TENAA/T]PPDR(]VY_MYQLNU-D_1[)]VRD^NW=7:W3+PYNKFD$YR][AU-V[VRF\VIEX"IT5\,V[CBUM;<0Y=!Z_HALJ*SX[]K_#XQ\T@V\GKR(OR?V"XQCUU0;?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/FY6Y+SXPFXHU?>4U1-V[LEHF&_T_YO[/T]PPDRXKG^$_1>1219V4*SXAJEE#XQ\T@V,QZUSI]UHBY!\<0<14>S7'\UBOB@ U^QWEQ)RWZ^JXRMAT.Q?6;473\:$YRGLOO-V[VRF\&_T_YO[_BLW+V:46;:0Y=!Z_HALJ*SX[]K_#XQ\T@V\GKR([5>5>=5Z0.W\MFII'\UXXLZ U^QWEQYDF]%X080>c:W3+PYNKFD$YR][AU-V[VRF\VBBKE?m;T2,QZODGG%^S^ZNT.W\WQGSWEE\=;5Z0.W\MFII'\UXXLZ U^VGK4d<]9%^SDM@N.W\WQGS'\U_HBQaeyv2a>S7'\UBOB@ U^QWEQ)nKDNTK_^?_RGO5f=R8&_TENAA/T]PPDR(aMK_MRXNLHF2=>S7'\UBOB@ U^QWEQ)n[]K_0=0>9:W3+PYNKFD$YR][AU-jWQGS484:56[?/T]JGJH(]VY_MY!fSUCW878612_;#XQFCNL,QZUSI]%b_YO[<2<2g>S7'\UBOB@ U^QWEQ)n[]K_O@JPCD3f?P6(]VCHCC!Z_RVBP*oT\H^HAIQLE^l2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<1<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<0<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<3<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<2<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<5<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<4<2f>S7'\UBOB@ U^QWEQ)n[]K_SEGHH0c8Q5)RW@IDB"[PSUCW+lUSI]UGCZ?n;T2,QZODGG%^S^ZNT.kW@JYimq~9n6[?/T]JGJH(]VYRBN!H_R[MGZQHZMQ;Q#GPND2-QZ@CZ;h0Y=!Z_HALJ*SX[PDH#JQ\YOA\SJTCS8W%ER@J0/W\BAT5j2_;#XQFCNL,QZU^FJ%LS^WAC^ULVA]5U'CTBH>!U^DGV7d<]9%^SDM@N.W\W\HD'NUXUCMPWNPG_6[)AVDN<#[PFEP1f>S7'\UBOB@ U^QZJF)@WZSEORY@REY7Y+OXFL:%YRHKR3`8Q5)RW@IDB"[PSXL@+BYTQGIT[B\K[4_-MZHB8'_TJI\=b:W3+PYNKFD$YR]VNB-D[V_IKV]D^IU9]/K\AT6)]VLO^<l4U1-V[LEHF&_T_T@L/T]DKQYTQGI:h6[?/T]JGJH(]VYRBN!Z_FMW[V_IKVB:h6[?/T]JGJH(]VYRBN!Z_FMW[V_IKVF:;6[?/T]JGJH(]VYRBN!Z_R[MG4c<]9%^SDM@N.W\W\HD'\UbHLZN_BOG[k7d3\:$YRGLOO-V[V_IK&cOMYOPCLF\j4g<]9%^SDM@N.W\W\HD'`MDXR]VNB3e?P6(]VCHCC!Z_R[MG*o@G]UXUCMPHHEK5`=R8&_TENAA/T]P]KE(aNE_S^WAC^NLS4c<]9%^SDM@N.W\W\HD'`YRBNQXOSF?4;7b3\:$YRGLOO-V[V_IK&cXUCMPWNPG8486m2_;#XQFCNL,QZU^FJ%b_T@L_VMQ@9499l1^<"[PIBMM+PYTQGI$e^WAC^ULVA:468o0Y=!Z_HALJ*SX[PDH#d]VNB]TKWB;<7;n7X> U^K@KK)RWZSEO"g\YOA\SJTC4<4:i6[?/T]JGJH(]VYRBN!fSXL@[RIUL5<5=>5Z0.W\MFII'\U_HDQ}ef0e?P6(]VCHCC!Z_UFL[HS_'\UH_RCZX.K7*PYJ]Q;=#@czx^M774=R8&_TENAA/T]W@JYJ]Q%^SN]PMTZ,M1(RWD_S=;!Bmtz\K1YA;81^<"[PIBMM+PYSLFUFYU!Z_BQ\IP^(A=$^S@[W17-Nip~XG=UL=>5Z0.W\MFII'\U_HBQ}ef36?P6(]VCHCC!Z_hFBPDYDEM;<7X> U^K@KK)RW`NJXLQLME]m57=R8&_TENAA/T]jW@JXf830Y=!Z_HALJ*oDGDGJBIQHRQ>3:4?<]9%^SDM@N.k@KHKFFMUL^]2>>0;8Q5)RW@IDB"gLOLOBJAYTME6;2<o4U1-V[LEHF&cHC@CNNE]PAI:687;j7X> U^K@KK)nKFGFMCJPSDN?5486i2_;#XQFCNL,mFIJEHDOS^KC<00=5d=R8&_TENAA/hALIHGILVYN@1?<>0c8Q5)RW@IDB"gLOLOBJAYTME6:83?n;T2,QZODGG%bOBCBAOF\W@J;9<4:56[?/T]JGJH(aJEFAL@K_RGO848612_;#XQFCNL,mFIJEHDOS^KC<3<2=>S7'\UBOB@ iBMNIDHCWZOG0>0>9:W3+PYNKFD$eNABM@LG[VCK4=4:56[?/T]JGJH(aJEFAL@K_RGO808612_;#XQFCNL,mFIJEHDOS^KC<7<2=>S7'\UBOB@ iBMNIDHCWZOG0:0>9:W3+PYNKFD$eNABM@LG[VCK414:56[?/T]JGJH(aJEFAL@K_RGO8<86=2_;#XQFCNL,mFIUMVCO0=0>5:W3+PYNKFD$eNA]E^KG8486=2_;#XQFCNL,mFIUMVCO0?0>5:W3+PYNKFD$eNA]E^KG868612_;#XQFCNL,mFIUMVCOS^KC<1<2e>S7'\UBOB@ iBMQAZOCWZOG0<;1189V4*SXAJEE#dM@RD]J@ZUBD5;5=45Z0.W\MFII'`ID^HQFD^QFH949901^<"[PIBMM+lEHZLUBHR]JL=1=56=R8&_TENAA/hFBPDYDEM;>7X> U^K@KK)nLH^JSNCK_og8Q5)RW@IDB"g\EM33?P6(]VCHCC!fSDN\jc=R8&_TENAA/hQZJFc<]9%^SDM@N.kW@Lc<]9%^SDM@N.kW@J713\:$YRGLOO-jPAIX^LI7=80>3:W3+PYNKFD$eYJ@_og{pa=R8&cXDDH[_NWWa>S7'`_[HLZJ_NWW2>SWLH^No6[\ES]UMVOEDL?0YRMCK29UGF?<^@O\SYW_E0f8\LJNFQ'SHO.?.0"PPPD'8';+M^MFI49[KWE^>2RXXAGM7:ZPPZAIL>1S_YQYCB`8\ZEHZLUBBKA9;Yfa[Lba3QncS]|fmWgqwlii991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc=4Xrv0f>YXWQFEARQP0^]\Q5)RW@IDB"[PCLF,QZEHEDKEHR]JL.K7*CO\98W%YRBZT2`8[ZY_DGGTSR??_^]V4*SXAJEE#XQLME-V[FIUMVCOS^KC/H6-BL]6U'_T@XZ<b:]\[]JIEVUT=<QP_T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_0[)]VF^X>o4_^][HKKXWV;TSR[?/T]JGJH(]VIFH"[PCNONEKBX[LF$E9 IIZ6^*PYK]]9j7RQPXMLN[ZY5WVU^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU8]/W\HPR4i2UTSUBAM^]\7ZYX]9%^SDM@N.W\GHB(]VIDA@OAD^QFH*O3&OCP5P Z_MWW6==XWVRGB@QP_5]\[P6(]VCHCC!Z_RVBP*SXKDNL^]>=b:]\[]JIEVUT9RQPU1-V[LEHF&_T_YO[/T]GEQGX^HFBH>o4_^][HKKXWV<TSR[?/T]JGJH(]VIFH"[PCNPF[LBX[LF$E9 IIZ1^*PYK]]9j7RQPXMLN[ZY0WVU^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU9]/W\HPR4i2UTSUBAM^]\<ZYX]9%^SDM@N.W\GHB(]VIDA@OAD^QFH*O3&OCP>P Z_MWW7d=XWVRGB@QP_8]\[P6(]VCHCC!Z_BOG+PYDGDGJBIQ\EM-J0+@NS9W%YRBZT208gmow{je{iRgloo]u5Z63Wh&+Tdbfny"@KWC'Oldn~lz`r!32*42<ajee>85fcnl/gmow{je{iRgloo]u5Z63Wh&ECCK#NNLF6c4<ajee nffpralt`YnkfdTz<Q?4^c/fYkfUge~z2NtoaawYDgg~ycaQ_osvp91=R{lUNtyQMsbcm9cgk{l1^h|PSbcm[Fnfag7^_H\>;DlbficXB}klSO{ig<vqq`=R{lU^bx}jd^@pgdh:nhfxi6[|e^Qlbqdtkhd6jlb|e-a\|acqajomm`gcy<tjvqc>%iTob|j_u{sa87+kVgjfb|Pvdppmjh:98&hS`gaos]uawungg7: nQmuhng[wcqazcdb0>#c^alv`YjiceyS{k}=0.`[fiumVgbbb|Pvdp>6)eXkfxnS`gaos]bhunfWoy149#c^oecZoc58&hSx}j_rkn95*dW|ynS~aitcq`ek;7$jU{mzPieal``Yumncxxh|20-a\qvcXb}klSo{ig<3/gZhreVidby|`l^rlvqu:<%iTy~kPcnlwvjj758&hSx}j_bmmpwik94;'oR{|e^aljqthd;7: nQzsd]`kkruge96=!mPurg\gjhszff?1="l_tqf[fii|{eg90>#c^wpaZehf}xd`;3?,b]vw`Ydgg~yca920-a\qvcXkfd~bb7=1.`[pubWjeexac9<2/gZstmVidby|`l02>4)eX}zoTob`{rnn2586+kVxiRm`nuplh44:8%iTy~kPcnlwvjj6;4:'oR{|e^aljqthd8>6<!mPurg\a}rXjzijb0>#c^wpaZsi}zooSo}lao?3(fYr{lxTnoa_bjbmk;6$t;:7dm`n^VJI@UWMJUEOK?>;haljZRNELY[INQWSU:8jbee}`foqMN7`c8DE~5?l0M694>{Ra2>7172m81=><7d7396f1cnrd9:h4>;o05b?3<,;<h6?89;|Q1f?4083n96<==8e42>7e0m;1Xi=4=8282>4550m<:6?m8ec9P6g<50:0:6<==8e42>7e?9l1o>:k50;395~Ud938<<7j=:011<a062;i<hk5yT02g>5<6280m<v]l1;044?b528994i8>:3a4`c=#:??1i<5Y27f96~sbj3;0yhm50:'557=9m1i>:k50;;3>`e=n9qC>;<4$03a>71b3S8?69u>6;34>4>=900v(?8m:35g?!4?2;=m7)m?:3:3?.2f290/==:5499m555=:910';h50;&241<1l2d:<>4=0:9(=1<72-;;877=;o337?4732!i57>5$027>g1<f8:86?>4;*6:>5<#99>1855a11194>=,<>0;6)??4;6;?k77;3;07&:9:18'552=<11e===52:9(00<72-;;87:7;o337?5<3">?6=4+11690==i9991865$4283>!77<3>37c??3;78?.26290/==:5499m555=>21 8=4?:%330?2?3g;;?794;*1e>5<#99>1855a1119<>=,;l0;6)??4;6;?k77;3307&=k:18'552=<11e===5a:9(7f<72-;;87:7;o337?d<3"9i6=4+11690==i9991o65$3`83>!77<3>37c??3;f8?.5>290/==:5499m555=m21 ?54?:%330?2?3g;;?7h4;*15>5<#99>1855a111955=<#:?1<7*>0587<>h68:0:=65$3583>!77<3>37c??3;31?>-4;3:1(<>;:5:8j46428907&==:18'552=<11e===51598/67=83.:<94;8:l246<6=21 ?=4?:%330?2?3g;;?7?9;:)1b?6=,8:?6964n020>41<3"8n6=4+11690==i9991=554+3f94?"68=0?46`>0282=>=,=90;6)??4;6;?k77;3;j76%;f;29 4632=20b<><:0`8?.2b290/==:5499m555=9j10'9j50;&241<302d:<>4>d:9(0f<72-;;87:7;o337?7b32!?n7>5$027>1><f8:86<h4;*61>5<#99>1855a111964=<#:=1<7*>0587<>h68:09>65$2b83>!77<3>37c??3;00?>-1m3:1(<>;:7f8j4642910';m50;&241<1l2d:<>4>;:)5f?6=,8:?6;j4n020>7=<#?k1<7*>0585`>h68:0876%99;29 4632?n0b<><:598/3>=83.:<949d:l246<232!=:7>5$027>3b<f8:86;54+7794?"68=0=h6`>0284?>-1<3:1(<>;:7f8j4642110';=50;&241<1l2d:<>46;:)56?6=,8:?6;j4n020>d=<#?;1<7*>0585`>h68:0i76%90;29 4632?n0b<><:b98/0`=83.:<949d:l246<c32!>i7>5$027>3b<f8:86h54+4f94?"68=0=h6`>028e?>-2j3:1(<>;:7f8j46428:07&;n:18'552=>m1e===51098/0?=83.:<949d:l246<6:21 954?:%330?0c3g;;?7?<;:)63?6=,8:?6;j4n020>42<3"?=6=4+11692a=i9991=854+4794?"68=0=h6`>02822>=,==0;6)??4;4g?k77;3;<76%:3;29 4632?n0b<><:0:8?.35290/==:56e9m555=9010':;50;&241<1l2d:<>4>a:9(31<72-;;878k;o337?7e32!<?7>5$027>3b<f8:86<m4;*51>5<#99>1:i5a11195a=<#>;1<7*>0585`>h68:0:i65$7183>!77<3<o7c??3;3e?>-1?3:1(<>;:7f8j4642;;07&;l:18'552=>m1e===52398/07=83.:<949d:l246<5;21 5>4?:%330??53g;;?7>4;*;2>5<#99>15?5a11195>=,190;6)??4;;1?k77;3807&6i:18'552=1;1e===53:9(<`<72-;;877=;o337?2<3"2o6=4+1169=7=i9991965$8c83>!77<3397c??3;48?.>f290/==:5939m555=?21 444?:%330??53g;;?764;*:;>5<#99>15?5a1119=>=,0>0;6)??4;;1?k77;3k07&69:18'552=1;1e===5b:9(<0<72-;;877=;o337?e<3"2?6=4+1169=7=i9991h65$8283>!77<3397c??3;g8?.>5290/==:5939m555=n21 4=4?:%330??53g;;?7??;:)4b?6=,8:?64<4n020>47<3"=n6=4+1169=7=i9991=?54+6f94?"68=02>6`>02827>=,?j0;6)??4;;1?k77;3;?76%8b;29 4632080b<><:078?.1f290/==:5939m555=9?10':750;&241<>:2d:<>4>7:9(3=<72-;;877=;o337?7?32!<;7>5$027><4<f8:86<74;*;b>5<#99>15?5a11195d=<#031<7*>058:6>h68:0:n65$9983>!77<3397c??3;3`?>->?3:1(<>;:808j46428n07&79:18'552=1;1e===51d98/<3=83.:<9462:l246<6n21 4n4?:%330??53g;;?7<>;:);5?6=,8:?64<4n020>74<3"==6=4+1169=7=i9991>>54+c:94?"68=0i;6`>0283?>-e>3:1(<>;:c58j4642810'o;50;&241<e?2d:<>4=;:)a0?6=,8:?6o94n020>6=<#k91<7*>058a3>h68:0?76%m2;29 4632k=0b<><:498/g6=83.:<94m7:l246<132!jj7>5$027>g1<f8:86:54+`g94?"68=0i;6`>028;?>-fl3:1(<>;:c58j4642010'lm50;&241<e?2d:<>4n;:)bf?6=,8:?6o94n020>g=<#hk1<7*>058a3>h68:0h76%n9;29 4632k=0b<><:e98/d>=83.:<94m7:l246<b32!j;7>5$027>g1<f8:86k54+`794?"68=0i;6`>02824>=,i=0;6)??4;`4?k77;3;:76%n3;29 4632k=0b<><:008?.g5290/==:5b69m555=9:10'l?50;&241<e?2d:<>4>4:9(e5<72-;;87l8;o337?7232!2j7>5$027>g1<f8:86<84;*;f>5<#99>1n:5a111952=<#0n1<7*>058a3>h68:0:465$9b83>!77<3h<7c??3;3:?>-en3:1(<>;:c58j46428k07&lj:18'552=j>1e===51c98/gb=83.:<94m7:l246<6k21 nn4?:%330?d03g;;?7?k;:)af?6=,8:?6o94n020>4c<3"hj6=4+1169f2=i9991=k54+c394?"68=0i;6`>02815>=,i?0;6)??4;`4?k77;38976%6b;29 4632k=0b<><:318?g41i3:1=7>50z&25g<5>=1C>;64H341?j7783:17pl=6883>4<729q/=<l5d09K63><@;<97bj?:188yg76l3:1n7>50z&25g<5:2B9:55G2708jae=92.h87m9;n33g?6=3f;;j7>5;n33a?6=3f;;57>5;n055?6=3f;;47>5;n33f?6=3`;:<7>5;n05>5<<g8;?6=44ob794?=zj8;h6=4=:183!76j3887E<98:J127=hno0;66gk3;29?xd5;00;6?4?:1y'54d=lk1C>;64H341?lb42900ckh50;9~f75f29096=4?{%32f?be3A8=46F=639j`6<722emj7>5;|`176<72=0;6=u+10`9g<=O:?20D?8=;%fb>7=n:<0;66g=7;29?le52900c<>9:188yg4403:187>50z&25g<d?2B9:55G2708 ag=:2c997>5;h0b>5<<aj81<75`11494?=zj;9<6=4;:183!76j3i27E<98:J127=#lh097d<::188m71=831bo?4?::m243<722wi=9750;094?6|,8;i6il4H34;?M41:2co?7>5;nde>5<<uk;?m7>53;294~"69k0n?6F=699K634<,mk1=l5fd583>>oc=3:17bhi:188yg75=3:197>50z&25g<d02B9:55G2708 ag=:2c997>5;h04>5<<a;k1<75fc383>>i68?0;66sm13494?3=83:p(<?m:b:8L70?3A8=>6*ka;08m73=831b>:4?::k1e?6=3`i96=44o025>5<<uk;9;7>55;294~"69k0h46F=699K634<,mk1>6g=5;29?l402900e?o50;9jg7<722e:<;4?::a57>=83?1<7>t$03a>f><@;<37E<92:&ge?4<a;?1<75f2683>>o5i3:17dm=:188k4612900qo?>f;291?6=8r.:=o4l8:J12==O:?80(io52:k11?6=3`8<6=44i3c94?=nk;0;66a>0783>>{e9;:1<7;50;2x 47e2j20D?87;I056>"ci380e?;50;9j62<722c9m7>5;ha1>5<<g8:=6=44}c315?6==3:1<v*>1c8`<>N5>11C>;<4$ec96>o5=3:17d<8:188m7g=831bo?4?::m243<722wi=?<50;794?6|,8;i6n64H34;?M41:2.om7<4i3794?=n:>0;66g=a;29?le52900c<>9:188yg75;3:197>50z&25g<d02B9:55G2708 ag=:2c997>5;h04>5<<a;k1<75fc383>>i68?0;66sm13694?3=83:p(<?m:b:8L70?3A8=>6*ka;08m73=831b>:4?::k1e?6=3`i96=44o025>5<<uk;9j7>55;294~"69k0n86F=699K634<,mk1=k5+1179627<am>1<75fd483>>oc>3:17dj8:188kc`=831vn<<j:186>5<7s-;:n7k;;I05<>N5>;1/hl4>b:&240<5?<1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm13f94?3=83:p(<?m:d68L70?3A8=>6*ka;37?!77=38<86gk4;29?lb22900ei850;9j`2<722emj7>5;|`26f<72<0;6=u+10`9a1=O:?20D?8=;%fb>44<,8:>6?9<;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg75j3:197>50z&25g<b<2B9:55G2708 ag=991/==;52638ma2=831bh84?::kg2?6=3`n<6=44ogd94?=zj88j6=4::183!76j3o?7E<98:J127=#lh0m7)??5;042>oc<3:17dj::188ma0=831bh:4?::meb?6=3th:?54?:483>5}#98h1i95G27:8L7053-nj6i5+1179620<am>1<75fd483>>oc>3:17dj8:188kc`=831vn<=8:186>5<7s-;:n7k;;I05<>N5>;1/hl4m;%331?40i2co87>5;hf6>5<<am<1<75fd683>>ian3:17pl>3783>0<729q/=<l5e59K63><@;<97)jn:`9'553=:>?0ei:50;9j`0<722co:7>5;hf4>5<<gol1<75rb016>5<2290;w)?>b;g7?M4102B9:?5+d`8:?!77=38<m6gk4;29?lb22900ei850;9j`2<722emj7>5;|`271<72<0;6=u+10`9a1=O:?20D?8=;%fb>==#99?1>:=4ie694?=nl<0;66gk6;29?lb02900ckh50;9~f454290>6=4?{%32f?c33A8=46F=639'`d<03-;;97<84:kg0?6=3`n>6=44ie494?=nl>0;66aif;29?xd6;;0;684?:1y'54d=m=1C>;64H341?!bf2?1/==;526`8ma2=831bh84?::kg2?6=3`n<6=44ogd94?=zj89:6=4::183!76j3o?7E<98:J127=#lh0>7)??5;04f>oc<3:17dj::188ma0=831bh:4?::meb?6=3th:?=4?:483>5}#98h1i95G27:8L7053-nj695+117962e<am>1<75fd483>>oc>3:17dj8:188kc`=831vn<<6:186>5<7s-;:n7k;;I05<>N5>;1/hl4<;%331?40k2co87>5;hf6>5<<am<1<75fd683>>ian3:17pl>3g83>0<729q/=<l5e59K63><@;<97)jn:0d8 4622;=27dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c30a?6==3:1<v*>1c8f0>N5>11C>;<4$ec95g=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=>j50;794?6|,8;i6h:4H34;?M41:2.om7?;;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg74k3:197>50z&25g<b<2B9:55G2708 ag=9;1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm12`94?3=83:p(<?m:d68L70?3A8=>6*ka;33?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;8m7>55;294~"69k0n86F=699K634<,mk1j6gk4;29?lb22900ei850;9j`2<722emj7>5;|`20=<72<0;6=u+10`9a1=O:?20D?8=;%fb>a=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=9950;794?6|,8;i6h:4H34;?M41:2.om7l4ie694?=nl<0;66gk6;29?lb02900ckh50;9~f421290>6=4?{%32f?c33A8=46F=639'`d<f3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?;5;291?6=8r.:=o4j4:J12==O:?80(io59:kg0?6=3`n>6=44ie494?=nl>0;66aif;29?xd6<=0;684?:1y'54d=m=1C>;64H341?!bf211bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm15194?3=83:p(<?m:d68L70?3A8=>6*ka;58ma2=831bh84?::kg2?6=3`n<6=44ogd94?=zj8>96=4::183!76j3o?7E<98:J127=#lh0=7)??5;04=>oc<3:17dj::188ma0=831bh:4?::meb?6=3th:8<4?:483>5}#98h1i95G27:8L7053-nj685+1179624<am>1<75fd483>>oc>3:17dj8:188kc`=831vn<:?:186>5<7s-;:n7k;;I05<>N5>;1/hl4;;%331?40:2co87>5;hf6>5<<am<1<75fd683>>ian3:17pl>3883>0<729q/=<l5e59K63><@;<97)jn:29j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9<;1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c366?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=8h50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7183:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm17394?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;=>7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a535=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?94;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9??1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c352?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=;950;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7103:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm17;94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;=m7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a53d=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?9c;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9?n1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c35a?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=;h50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7083:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm14194?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;>87>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a503=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?:6;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9<=1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c36<?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=8750;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg72i3:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm14`94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;>o7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a50b=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?:e;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9>;1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c346?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=:h50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7?83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm19394?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;3>7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5=5=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?74;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e91?1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3;2?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=5950;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7?03:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm19;94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;3m7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5=d=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?7c;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e91n1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3;a?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=5h50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7>83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm16194?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;<87>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a523=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?86;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9>=1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c34<?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=:750;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg70i3:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm16`94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;<o7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a52b=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?8e;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e90;1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3:6?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=4h50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7f83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1`394?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;j>7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5d5=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?n4;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9h?1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3b2?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=l950;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7f03:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1`;94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;jm7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5dd=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?nc;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9hn1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3ba?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=lh50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7e83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm18194?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;287>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5<3=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?66;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e90=1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3:<?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=4750;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7>i3:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm18`94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;2o7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5<b=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?6e;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9k;1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3a6?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=oh50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7d83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1b394?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;h>7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5f5=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?l4;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9j?1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3`2?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=n950;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7d03:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1b;94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;hm7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5fd=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?lc;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9jn1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3`a?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=nh50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7c83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1c194?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;i87>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5g3=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?m6;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9k=1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3a<?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=o750;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7ei3:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1c`94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;io7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5gb=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?me;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9m81<7=50;2x 47e2l90D?87;I056>"ci3;87dj;:188ma3=831djk4?::a5a7=8391<7>t$03a>`5<@;<37E<92:&ge?763-;;97<87:kg0?6=3`n>6=44ogd94?=zj8n86=4<:183!76j3o87E<98:J127=#lh0:i6*>04813==nl=0;66gk5;29?j`a2900qo<?a;290?6=8r.:=o4j9:J12==O:?80ei:50;9j`0<722c:<l4?::meb?6=3th9<54?:583>5}#98h1i55G27:8L7053`n?6=44ie794?=n99k1<75`fg83>>{e:9=1<7:50;2x 47e2l20D?87;I056>oc<3:17dj::188m46f2900ckh50;9~f4b0290>6=4?{%32f?c33A8=46F=639'`d<d3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?k8;291?6=8r.:=o4j4:J12==O:?80(io5209j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9m31<7;50;2x 47e2l>0D?87;I056>"ci3;>7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3ge?6==3:1<v*>1c8f0>N5>11C>;<4$ec95f=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=ik50;094?6|,8;i6il4H34;?M41:2co?7>5;nde>5<<uk;on7>53;294~"69k0n?6F=699K634<,mk1=<5+1179621<am>1<75fd483>>ian3:17pl>de83>0<729q/=<l5e59K63><@;<97)jn:0d8ma2=831bh84?::kg2?6=3`n<6=44ogd94?=zj8nh6=4<:183!76j3o87E<98:J127=#lh0:i6*>04813==nl=0;66gk5;29?j`a2900qo<?9;290?6=8r.:=o4l9:J12==O:?80(io52:k11?6=3`8<6=44ib094?=h99<1<75rb0gg>5<4290;w)?>b;053>N5>11C>;<4i3;94?=nll0;66aif;29?xd6mh0;694?:1y'54d=m>1C>;64H341?l4>2900en=50;9j55g=831dhk4?::a5c7=8391<7>t$03a>7003A8=46F=639j6<<722coi7>5;nde>5<<uk;ni7>54;294~"69k0n;6F=699K634<a;31<75fc283>>o68h0;66akf;29?xd6n<0;6>4?:1y'54d=:?=0D?87;I056>o513:17djj:188kc`=831vn<h=:187>5<7s-;:n7k8;I05<>N5>;1b>44?::k`7?6=3`;;m7>5;nfe>5<<uk;m57>53;294~"69k09::5G27:8L7053`826=44ieg94?=hno0;66sm1g494?2=83:p(<?m:d58L70?3A8=>6g=9;29?le42900e<>n:188ka`=831vn<hk:180>5<7s-;:n7<97:J12==O:?80e?750;9j``<722emj7>5;|`2bd<72=0;6=u+10`9a2=O:?20D?8=;h0:>5<<aj91<75f11c94?=hlo0;66sm21294?5=83:p(<?m:344?M4102B9:?5f2883>>ocm3:17bhi:188yg7bk3:1>7>50z&25g<b:2B9:55G2708 ag=9:1bh94?::meb?6=3th:j=4?:383>5}#98h1i?5G27:8L7053-nj6<=4ie694?=hno0;66sm1g694?4=83:p(<?m:d08L70?3A8=>6*ka;30?lb32900ckh50;9~f4`?29096=4?{%32f?c53A8=46F=639'`d<6;2co87>5;nde>5<<uk;mo7>52;294~"69k0n>6F=699K634<,mk1=>5fd583>>ian3:17pl>fg83>7<729q/=<l5e39K63><@;<97)jn:018ma2=831djk4?::a5`d=83?1<7>t$03a>fd<@;<37E<92:&ge?4<a;?1<75f2683>>od:3:17d??7;29?j77>3:17pl>eg83>0<729q/=<l5cc9K63><@;<97)jn:39j60<722c9;7>5;ha1>5<<a8:<6=44o025>5<<uk;m?7>55;294~"69k0hn6F=699K634<,mk1>6g=5;29?l402900en<50;9j551=831d==850;9~f4`0290>6=4?{%32f?ee3A8=46F=639'`d<53`8>6=44i3594?=nk;0;66g>0683>>i68?0;66sm1g`94?3=83:p(<?m:b`8L70?3A8=>6*ka;08m73=831b>:4?::k`6?6=3`;;;7>5;n332?6=3th:jh4?:483>5}#98h1oo5G27:8L7053-nj6?5f2483>>o5?3:17dm=:188m4602900c<>9:188yg45=3:197>50z&25g<b<2B9:55G2708 ag=l2co87>5;hf6>5<<am<1<75fd683>>ian3:17pl=2283>6<729q/=<l5e29K63><@;<97)jn:0g8ma2=831bh84?::meb?6=3th9>:4?:383>5}#98h1ho5G27:8L7053`n86=44ogd94?=zj;8?6=4::183!76j3o?7E<98:J127=#lh0m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c012?6==3:1<v*>1c8`f>N5>11C>;<4$ec96>o5=3:17d<8:188mf4=831b==950;9l550=831vn??l:187>5<7s-;:n7mn;I05<>N5>;1/hl4=;h06>5<<aj81<75f11594?=h99<1<75rb33g>5<3290;w)?>b;ab?M4102B9:?5+d`81?l422900en<50;9j551=831d==850;9~f77b290?6=4?{%32f?ef3A8=46F=639'`d<53`8>6=44ib094?=n99=1<75`11494?=zj;;m6=4;:183!76j3ij7E<98:J127=#lh097d<::188mf4=831b==950;9l550=831vn?<?:187>5<7s-;:n7mn;I05<>N5>;1/hl4=;h06>5<<aj81<75f11594?=h99<1<75rb302>5<3290;w)?>b;ab?M4102B9:?5+d`81?l422900en<50;9j551=831d==850;9~f745290?6=4?{%32f?ef3A8=46F=639'`d<53`8>6=44ib094?=n99=1<75`11494?=zj;296=4?:183M41:2.:=o4>129O545=;r.:=:4>039'54?=kl1/=<o5cg9~yg44<3:187>50z&25g<bi2B9:55G2708ma2=831bh84?::k24d<722emj7>5;|`170<72?0;6=u+10`9a0=O:?20D?8=;%fb>`=nl=0;66gk5;29?lb12900ei950;9j`=<722emj7>5;|`173<72>0;6=u+10`9a3=O:?20D?8=;%fb>76<am>1<75fd483>>oc>3:17dj8:188ma>=831bh44?::meb?6=3th94<4?:183>5}#98h1=<=4H032?I76;38p(<?7:bf8 4712ji0qp}=d;296~X5l27::l4if:p6`<72;qU>h5217a9bc=z{;l1<7<t^3d8940b2ol0q~=?:181[5734;<<7hi;|q05?6=:rT8=63>558eb>{t;;0;6?uQ339>500=no1v>=50;0xZ65<58?36kh4}r17>5<5sW9?70?:a;de?xu4=3:1>vP<5:?21f<an2wx?;4?:3y]73=:9<o1jk5rs2:94?4|V:201<;>:gd8yv5>2909wS=6;<36b?`a3ty8m7>52z\0e>;6>80mj6s|3c83>7}Y;k16=;=5fg9~w6e=838pR>m4=046>c`<uz9o6=4={_1g?871?3lm7p}<e;296~X4m27::44if:p7c<72;qU?k5217`9bc=z{=:1<7<t^528940c2ol0q~:>:181[2634;=j7hi;|q77?6=:rT??63>528eb>{t<=0;6?uQ459>503=no1v9;50;0xZ13<58?<6kh4}r65>5<5sW>=70?:9;de?xu3?3:1>vP;7:?21g<an2wx844?:3y]0<=:9<n1jk5rs5c94?4|V=k01?=::e:8yv2e2909wS:m;<366?`a3ty?o7>52z\7g>;6>90mj6s|4e83>7}Y<m16=;<5fg9~w1c=838pR9k4=047>c`<uz>m6=4={_6e?871>3lm7p}:0;296~X2827::54if:p17<72;qU9?5219c9bc=z{<91<7<t^41894>d2ol0q~;;:181[3334;3i7hi;|q61?6=:rT>963>918eb>{t=?0;6?uQ579>522=no1v8950;0xZ01<58==6kh4}r7;>5<5sW?370?88;de?xu213:1>vP:9:?23d<an2wx9l4?:3y]1d=:9>i1jk5rs4`94?4|V<h01<9j:gd8yv3c2909wS;k;<345?`a3ty>i7>52z\6a>;6?o0mj6s|5g83>7}Y=o16=5?5fg9~w36=838pR;>4=0:0>c`<uz<:6=4={_42?87?=3lm7p}92;296~X1:27:4:4if:p26<72;qU:>5219;9bc=z{?>1<7<t^76894>e2ol0q~8::181[0234;3h7hi;|q52?6=:rT=:63>8g8eb>{t>10;6?uQ699>525=no1v;750;0xZ3?<58=>6kh4}r4b>5<5sW<j70?87;de?xu1j3:1>vP9b:?23<<an2wx:n4?:3y]2f=:9>h1jk5rs7g94?4|V?o01<9k:gd8yv0a2909wS8i;<002?b?3ty<<7>52z\44>;6?;0mj6s|7083>7}Y?816=5>5fg9~w24=838pR:<4=0:1>c`<uz=86=4={_50?87?<3lm7p}84;296~X0<27:4;4if:p30<72;qU;85219:9bc=z{>=1<7<t^65894gf2ol0q~97:181[1?34;jo7hi;|q4=?6=:rT<563>ad8eb>{t?h0;6?uQ7`9>5g6=no1v:l50;0xZ2d<583?6kh4}r5`>5<5sW=h70?66;de?xu0l3:1>vP8d:?2==<an2wx;h4?:3y]3`=:90k1jk5rs6d94?4|V>l01<7l:gd8yv>72909wS6?;<3:a?`a3ty3>7>52z\;6>;6180mj6s|8283>7}Y0:16=4h5fg9~w=2=838pR5:4=0c2>c`<uz2>6=4={_:6?87f;3lm7p}76;296~X?>27:m84if:p<2<72;qU4:521`59bc=z{121<7<t^9:894g>2ol0q~66:181[>>34;jn7hi;|q;e?6=:rT3m63>ae8eb>{t0k0;6?uQ8c9>5d`=no1v5j50;0xZ=b<58386kh4}r:f>5<5sW2n70?65;de?xu?n3:1>vP7f:?2=2<an2wx5=4?:3y]=5=:9031jk5rs8394?4|V0;01<7m:gd8yv?42909wS7<;<3:`?`a3ty287>52z\:0>;5;<0o;6s|9483>7}Y1<16=4<5fg9~w<0=838pR484=0c3>c`<uz3<6=4={_;4?87f:3lm7p}68;296~X>027:m94if:p=<<72;qU54521`49bc=z{0k1<7<t^8c894g?2ol0q~7l:181[?d34;hm7hi;|q:`?6=:rT2h63>cb8eb>{t1l0;6?uQ9d9>5fc=no1v4h50;0xZ<`<58n;6kh4}rc3>5<5sWk;70?m4;de?xuf93:1>vPn1:?2f3<an2wxm?4?:3y]e7=:9k21jk5rs`194?4|Vh901<ln:gd8yvg32909wSo;;<3ag?`a3tyj97>52z\b1>;6jl0mj6s|a683>7}Yi>16=o?5fg9~wd>=838pRl64=0`e>c`<uzk26=4={_c:?87d93lm7p}na;296~Xfi27:o>4if:peg<72;qUmo521b79bc=z{hi1<7<t^`a894e02ol0q~ok:181[gc34;h57hi;|qba?6=:rTji63>cc8eb>{tio0;6?uQag9>5fb=no1vo>50;0xZg6<58im6kh4}r`1>5<5sWh970?m3;de?xue;3:1>vPm3:?2f0<an2wxn94?:3y]f1=:9k=1jk5rsc794?4|Vk?01<l6:gd8yvd12909wSl9;<3af?`a3tyi47>52z\a<>;6jm0mj6s|b883>7}Yj016>>85d69~wgg=838pRoo4=0`1>c`<uzhi6=4={_`a?87d83lm7p}mc;296~Xek27:o?4if:pfa<72;qUni521b69bc=z{ko1<7<t^cg894e12ol0q~li:181[da34;h47hi;|qf`?6=lr79:l4>019>661=:>16>>=5269>65?=:>16=kk5269>5cd=:>16=k95269>5c5=:>16=hh5269>5`d=:>16=ho5289>5`b=:016>?85c39~w`c=838p1?=::gd897532m>0q~ki:181844>3lm70<<4;f6?xua83:1<vs|f083>5}z{o81<7>t}rd0>5<7stym87>50zpb0<729qvk850;2xyv`0290;wp}i8;294~{tn00;6luQ439]22=Y0j16=ko5c29>5c0=k:16=k<5c29>5`c=k:16=ho5c29>63?=l91Un<5rsgc94?>|V:=0R8m4^93894432j801?<=:b0897432m=0Rl84=310>4613tymn7>521y]6f=Y=81U;;52225960=:::91>852136960=:9;91>852130960=:9;;1>852132960=:98l1>85213:960=:9;=1>852134960=:9;?1>85221;960=:9oo1>8521g`960=:9o=1>8521g1960=:9ll1>8521d`960=::;81>852233960=::;:1>85220d960=::8o1>85220f960=::8i1>852234960=Y1k16=<m5fg9~w47b2909w0?>c;f0?876l3i>7p}>4c83>g}:9;>1>l5213196d=:9;81>l5213396d=:9;:1>l5210d96d=:9;21>l5213596d=:9;<1>l5213796d=:9=31jk5rs06`>5<6:r7:=k4>079>57>=k;16=?75d79>566=l?16=>?5d79>564=l?16=>=5d79>562=l?16=>;5d79>560=l?16=>95d79>56>=l?16=?o5d79>57d=l?16=?m5d79>57b=l?16=?k5d79>57`=l?1v<:k:1826~;6:90:<;5210d9g7=:9;31h:521229`2=:9:;1h:521209`2=:9:91h:521269`2=:9:?1h:521249`2=:9:=1h:5212:9`2=:9;k1h:5213`9`2=:9;i1h:5213f9`2=:9;o1h:5213d9`2=z{8>n6=4>2z?262<68?16=?85c39>57?=l=16=>>5d59>567=l=16=><5d59>565=l=16=>:5d59>563=l=16=>85d59>561=l=16=>65d59>57g=l=16=?l5d59>57e=l=16=?j5d59>57c=l=16=?h5d59~w42a290:>v3>298243=:9;=1o?5213;9`0=:9::1h8521239`0=:9:81h8521219`0=:9:>1h8521279`0=:9:<1h8521259`0=:9:21h85213c9`0=:9;h1h85213a9`0=:9;n1h85213g9`0=:9;l1h85rs073>5<es4;987<8;<317?4034;9>7<8;<315?4034;9<7<8;<32b?4034;947<8;<313?4034;9:7<8;<311?4034;?m7hi;|q2`1<72=;p1<j>:gd894db2m=01<ll:e5894df2m=01<l7:e5894d12m=01<l;:e5894b72m=01<mj:e5894ed2m=01<mn:e5894e?2m=01<m9:e5894e32m=01<m=:e5894e72m=01<l=:e5894?b2m=01<7l:e5894?f2m=01<77:e5894?12m=01<7;:e5894d72m=01<oj:e5894gd2m=01<on:e5894g?2m=01<o9:e5894g32m=01<o=:e5894g72m=01<7=:e58941b2m=01<9l:e58941f2m=01<97:e5894112m=01<9;:e5894?72m=01<6j:e5894>d2m=01<6n:e5894>?2m=01<69:e5894>32m=01<6=:e5894>72m=01<9=:e58943b2m=01<;l:e58943f2m=01<;7:e5894312m=01<;;:e5894172m=01<8j:e58940d2m=01<8n:e58940?2m=01<89:e5894032m=01<8=:e5894072m=01<;=:e58yv7c=3:18<u21e09bc=:9kn1h:521c`9`2=:9k31h:521c59`2=:9k?1h:521c19`2=:9jl1h:521bf9`2=:9jh1h:521b;9`2=:9j=1h:521b79`2=:9j91h:521b39`2=:9kl1h:521c39`2=:90n1h:5218`9`2=:9031h:521859`2=:90?1h:521819`2=:9hl1h:521`f9`2=:9hh1h:521`;9`2=:9h=1h:521`79`2=:9h91h:521`39`2=:90l1h:521839`2=:9>n1h:5216`9`2=:9>31h:521659`2=:9>?1h:521619`2=:91l1h:5219f9`2=:91h1h:5219;9`2=:91=1h:521979`2=:9191h:521939`2=:9>l1h:521639`2=:9<n1h:5214`9`2=:9<31h:521459`2=:9<?1h:521419`2=:9?l1h:5217f9`2=:9?h1h:5217;9`2=:9?=1h:521779`2=:9?91h:521739`2=:9<l1h:521439`2=z{8n=6=471z?2`6<an27:nh4k4:?2fa<c<27:nn4k4:?2fg<c<27:nl4k4:?2f<<c<27:n54k4:?2f2<c<27:n;4k4:?2f0<c<27:n94k4:?2f6<c<27:h=4k4:?2gc<c<27:oh4k4:?2ga<c<27:on4k4:?2gg<c<27:ol4k4:?2g<<c<27:o54k4:?2g2<c<27:o;4k4:?2g0<c<27:o94k4:?2g6<c<27:o?4k4:?2g4<c<27:o=4k4:?2fc<c<27:n?4k4:?2f4<c<27:5h4k4:?2=a<c<27:5n4k4:?2=g<c<27:5l4k4:?2=<<c<27:554k4:?2=2<c<27:5;4k4:?2=0<c<27:594k4:?2=6<c<27:n=4k4:?2ec<c<27:mh4k4:?2ea<c<27:mn4k4:?2eg<c<27:ml4k4:?2e<<c<27:m54k4:?2e2<c<27:m;4k4:?2e0<c<27:m94k4:?2e6<c<27:m?4k4:?2e4<c<27:m=4k4:?2=c<c<27:5?4k4:?2=4<c<27:;h4k4:?23a<c<27:;n4k4:?23g<c<27:;l4k4:?23<<c<27:;54k4:?232<c<27:;;4k4:?230<c<27:;94k4:?236<c<27:5=4k4:?2<c<c<27:4h4k4:?2<a<c<27:4n4k4:?2<g<c<27:4l4k4:?2<<<c<27:454k4:?2<2<c<27:4;4k4:?2<0<c<27:494k4:?2<6<c<27:4?4k4:?2<4<c<27:4=4k4:?23c<c<27:;?4k4:?234<c<27:9h4k4:?21a<c<27:9n4k4:?21g<c<27:9l4k4:?21<<c<27:954k4:?212<c<27:9;4k4:?210<c<27:994k4:?216<c<27:;=4k4:?22c<c<27::h4k4:?22a<c<27::n4k4:?22g<c<27::l4k4:?22<<c<27::54k4:?222<c<27::;4k4:?220<c<27::94k4:?226<c<27::?4k4:?224<c<27::=4k4:?21c<c<27:9?4k4:?214<c<2wx=ih50;1x94cb2;301<h>:3;894cf2ml0q~?j0;297~;6n;09563>f481=>;6ml0oj6s|1d394?5|58l=6?74=0d:>7?<58l96ih4}r3f6?6=;r7:jl4=9:?2ba<5127:j;4kf:p5`5=838p1?>?:3;894`f2ml0q~?j4;296~;6mk0h>63>ee8eb>{t9l?1<7<t=0ge>f4<58l:6kh4}r3f2?6=:r7:j>4l2:?2b0<an2wx=h950;0x94`02j801<h6:gd8yv7b03:1>v3>fc8`6>;6nm0mj6s|1d;94?4|58ln6n<4=323>c`<uz8;=7>53z?2af<an27:il4>0`9>5`b=ll1v?>=:18087a83lm70?je;33e>;6n80oi6s|21194?5|58l?6kh4=0d1>46f34;m97jj;|q141<72:q6=k65fg9>5c0=99k01<h6:eg8yv47=3:1?v3>fb8eb>;6nh0:<l521gf9``=z{;:=6=4={<3eb?`a348;<7jj;|q14g<72;q6=ij5d69>5ad=no1v?>l:18187ck3lm70?kd;f7?xu58m0;6?u21e59bc=::921h95rs32f>5<5s4;o47hi;<03<?b23ty9<k4?:3y>5a?=no16>=95d59~w7772909w0?ka;de?847?3n>7p}=1083>7}:9mn1jk521eg9`6=z{;;96=48{<3ga?`a34;mi7??7:?2bg<68>16=k95115894`428:<70?jf;333>;6mk0:<:5rs330>5<1s4;om7j;;<3g=?b334;o47j;;<3g3?b334;nn7??6:?2af<c<2wx><:50;4x94bf2m?01<j6:e7894b?2m?01<j8:e7894ca28:=70?i0;f7?xu59<0;6;u21ec9`3=:9m31h;521e:9`3=:9m=1h;521g19550<58l?6i:4}r022?6=>r7:hl4k7:?2`<<c?27:h54k7:?2`2<c?27:j:4>079>5c>=l=1v??8:187847?3;;m63=09824d=:9oh1==84=0d`>a2<uz8:47>53z?14d<68h16=kk5114894`a2m>0q~<>9;296~;58>0mj63=0`8g1>{t:8k1<7<t=32;>c`<5;:j6i:4}r02f?6=:r79<44l2:?14d<an2wx>?650;;x974528:<70<=1;333>;5:90:<:5220d9551<5;;n6<>8;<02`?77?279=n4>069>670=99=01?<8:gd8yv4513:1>v3=27813>;5::0mj6s|23c94?4|5;8?6kh4=300>a3<uz89n7>52z?166<c<279>84if:p67e=838p1??l:025?845=3n?7p}=2e83>6}::8n1==84=33`>f4<5;8>6i;4}r01a?6=;r79=h4>079>64b=k;16>?;5d79~w74a2908w0<>f;332>;59l0h>63=248g3>{t:::1<7=t=303>461348:j7m=;<010?b33ty9?<4?:2y>677=99<01?<?:b0897432m?0q~<<2;297~;5:;0:<;522339g7=::;>1h;5rs31a>5<3s4;997??6:?2`4<c<27:h?4k4:?2`g<c<2wx>>m50;7x944128:=70?=5;a1?87c93n>70?k2;f6?87cj3n>7p}=3e83>d}:9;31jk521c09`0=:9k;1h8521809`0=:90;1h8521609`0=:9>;1h8521409`0=:9<;1h8521ef9`0=z{;9n6=46{<31e?`a34;i87j:;<3a7?b234;287j:;<3:7?b234;<87j:;<347?b234;>87j:;<367?b23ty9?k4?:8y>57d=no16=o85d49>5g3=l<16=485d49>5<3=l<16=:85d49>523=l<16=885d49>503=l<1v?:?:18:875k3lm70?m8;f6?87e?3n>70?68;f6?87>?3n>70?88;f6?870?3n>70?:8;f6?872?3n>7p}=4083><}:9;n1jk521cc9`0=:9k31h85218c9`0=:9031h85216c9`0=:9>31h85214c9`0=:9<31h85rs361>5<>s4;9i7hi;<3ag?b234;in7j:;<3:g?b234;2n7j:;<34g?b234;<n7j:;<36g?b234;>n7j:;|q106<720q6=?h5fg9>5gc=l<16=oj5d49>5<c=l<16=4j5d49>52c=l<16=:j5d49>50c=l<16=8j5d49~w7232902w0?<0;de?87d83n>70?mf;f6?87f83n>70?6f;f6?87?83n>70?8f;f6?87183n>70?:f;f6?xu5<<0;64u21239bc=:9j81h8521b39`0=:9h81h8521`39`0=:9181h8521939`0=:9?81h8521739`0=z{;>=6=46{<306?`a34;h87j:;<3`7?b234;j87j:;<3b7?b234;387j:;<3;7?b234;=87j:;<357?b23ty98:4?:8y>565=no16=n85d49>5f3=l<16=l85d49>5d3=l<16=585d49>5=3=l<16=;85d49>533=l<1v?:7:18:874<3lm70?l8;f6?87d?3n>70?n8;f6?87f?3n>70?78;f6?87??3n>70?98;f6?871?3n>7p}=4883><}:9:?1jk521bc9`0=:9j31h8521`c9`0=:9h31h85219c9`0=:9131h85217c9`0=:9?31h85rs36b>5<>s4;8:7hi;<3`g?b234;hn7j:;<3bg?b234;jn7j:;<3;g?b234;3n7j:;<35g?b234;=n7j:;|q10g<720q6=>95fg9>5fc=l<16=nj5d49>5dc=l<16=lj5d49>5=c=l<16=5j5d49>53c=l<16=;j5d49~w72d2902w0?<8;de?87c83n>70?lf;f6?87e83n>70?nf;f6?87>83n>70?7f;f6?87083n>70?9f;f6?xu5<m0;6<=t=002>46134;9<7m=;<30=?b334;?<7j;;<375?b334;?>7j;;<377?b334;?87j;;<371?b334;?:7j;;<373?b334;?47j;;<30e?b334;8n7j;;<30g?b334;8h7j;;<30a?b334;8j7j;;<000?77i2wx>9k50;37875:3;;:63>208`6>;6;00o963>418g1>;6<80o963>438g1>;6<:0o963>458g1>;6<<0o963>478g1>;6<>0o963>498g1>;6;h0o963>3c8g1>;6;j0o963>3e8g1>;6;l0o963>3g8g1>;5;<0o863=378g0>{t:=l1<7?;{<317?77>27:>?4l2:?27<<c>27:8=4k6:?204<c>27:8?4k6:?206<c>27:894k6:?200<c>27:8;4k6:?202<c>27:854k6:?27d<c>27:?o4k6:?27f<c>27:?i4k6:?27`<c>27:?k4k6:?170<c=279?;4k5:p606=83;?w0?=4;332>;6::0h>63>388g3>;6<90o;63>408g3>;6<;0o;63>428g3>;6<=0o;63>448g3>;6<?0o;63>468g3>;6<10o;63>3`8g3>;6;k0o;63>3b8g3>;6;m0o;63>3d8g3>;6;o0o;63=348g2>;5;?0o:6s|24394?46s4;857hi;<36a?b134;>h7j9;<36g?b134;>n7j9;<36e?b134;>57j9;<36<?b134;>;7j9;<362?b134;>97j9;<360?b134;>?7j9;<344?b134;=j7j9;<35a?b134;=h7j9;<35g?b134;=n7j9;<35e?b134;=57j9;<35<?b134;=;7j9;<352?b134;=97j9;<350?b134;=?7j9;<356?b134;==7j9;<354?b134;>j7j9;<366?b134;>=7j9;|q117<72;q6=>h5fg9>5ab=l?1v?;<:1815~;6<90mj63>7d8g2>;6?m0o:63>7b8g2>;6?k0o:63>7`8g2>;6?00o:63>798g2>;6?>0o:63>778g2>;6?<0o:63>758g2>;6?:0o:63>918g2>;60o0o:63>8d8g2>;60m0o:63>8b8g2>;60k0o:63>8`8g2>;6000o:63>898g2>;60>0o:63>878g2>;60<0o:63>858g2>;60:0o:63>838g2>;6080o:63>818g2>;6?o0o:63>738g2>;6?80o:6s|24694?46s4;?=7hi;<3:a?b134;2h7j9;<3:g?b134;2n7j9;<3:e?b134;257j9;<3:<?b134;2;7j9;<3:2?b134;297j9;<3:0?b134;2?7j9;<3a4?b134;jj7j9;<3ba?b134;jh7j9;<3bg?b134;jn7j9;<3be?b134;j57j9;<3b<?b134;j;7j9;<3b2?b134;j97j9;<3b0?b134;j?7j9;<3b6?b134;j=7j9;<3b4?b134;2j7j9;<3:6?b134;2=7j9;|q110<72;;p1<:=:gd894db2m<01<lk:e4894dd2m<01<lm:e4894df2m<01<l6:e4894d?2m<01<l8:e4894d12m<01<l::e4894d32m<01<l<:e4894b72m<01<mi:e4894eb2m<01<mk:e4894ed2m<01<mm:e4894ef2m<01<m6:e4894e?2m<01<m8:e4894e12m<01<m::e4894e32m<01<m<:e4894e52m<01<m>:e4894e72m<01<li:e4894d52m<01<l>:e48yv42>3:18v3=398243=:::31h>5215c9`1=::;=1h>5rs374>5<5s48847m=;<00=?`a3ty9954?:2y>66g=l:16=<j511`8942>2m90q~<:9;296~;5;109m63=3`8eb>{t:<k1<7=t=0f0>a2<58nh6i:4=305>4613ty99o4?:3y>665=k;16=<j511d8yv42k3:1>v3=368243=:98n1=<>4}r06`?6=:r79<44>079>660=l01v?;j:181844?3i970<<4;de?xu5=o0;69u210f955e<58>j6i;4=0f0>a3<58nh6i;4}r054?6=:r79?54=5:?25a<5>81vqc;la;295~N5>;1vb8mm:182M41:2we9nm50;3xL7053td>oi4?:0yK634<ug?hi7>51zJ127=zf<im6=4>{I056>{i=m:1<7?tH341?xh2l80;6<uG2708yk3c:3:1=vF=639~j0b4290:wE<92:m1a2=83;pD?8=;|l6`0<728qC>;<4}o7g2?6=9rB9:?5rn4f4>5<6sA8=>6sa5e:94?7|@;<97p`:d883>4}O:?80qc;ka;295~N5>;1vb8jm:182M41:2we9im50;3xL7053td>hi4?:0yK634<ug?oi7>51zJ127=zf<nm6=4>{I056>{i=l:1<7?tH341?xh2m80;6<uG2708yk3b:3:1=vF=639~j0c4290:wE<92:m1`2=83;pD?8=;|l6a0<728qC>;<4}o7f2?6=9rB9:?5rn4g4>5<6sA8=>6sa5d:94?7|@;<97p`:e883>4}O:?80qc;ja;295~N5>;1vb8km:182M41:2we9hm50;3xL7053td>ii4?:0yK634<ug?ni7>51zJ127=zf<om6=4>{I056>{i=o:1<7?tH341?xh2n80;6<uG2708yk3a:3:1=vF=639~j0`4290:wE<92:m1c2=83;pD?8=;|l6b0<728qC>;<4}o7e2?6=9rB9:?5rn4d4>5<6sA8=>6sa5g:94?7|@;<97p`:f883>4}O:?80qc;ia;295~N5>;1vb8hm:182M41:2we9km50;3xL7053td>ji4?:0yK634<ug?mi7>51zJ127=zf<lm6=4>{I056>{i>9:1<7?tH341?xh1880;6<uG2708yk07:3:1=vF=639~j364290:wE<92:m252=83;pD?8=;|l540<728qC>;<4}o432?6=9rB9:?5rn724>5<6sA8=>6sa61:94?7|@;<97p`90883>4}O:?80qc8?a;295~N5>;1vb;>m:182M41:2we:=m50;3xL7053td=<i4?:0yK634<ug<;i7>51zJ127=zf?:m6=4>{I056>{i>8:1<7?tH341?xh1980;6<uG2708yk06:3:1=vF=639~j374290:wE<92:m242=83;pD?8=;|l550<728qC>;<4}o422?6=9rB9:?5rn734>5<6sA8=>6sa60:94?7|@;<97p`91883>4}O:?80qc8>a;295~N5>;1vb;?m:182M41:2we:<m50;3xL7053td==i4?:0yK634<ug<:i7>51zJ127=zf?;m6=4>{I056>{i>;:1<7?tH341?xh1:80;6<uG2708yk05:3:1=vF=639~j344290:wE<92:m272=83;pD?8=;|l560<728qC>;<4}o412?6=9rB9:?5rn704>5<6sA8=>6sa63:94?7|@;<97p`92883>4}O:?80qc8=a;295~N5>;1vb;<m:182M41:2we:?m50;3xL7053td=>i4?:0yK634<ug<9i7>51zJ127=zf?8m6=4>{I056>{i>::1<7?tH341?xh1;80;6<uG2708yk04:3:1=vF=639~j354290:wE<92:m262=83;pD?8=;|l570<728qC>;<4}o402?6=9rB9:?5rn714>5<6sA8=>6sa62:94?7|@;<97p`93883>4}O:?80qc8<a;295~N5>;1vb;=m:182M41:2we:>m50;3xL7053td=?i4?:0yK634<ug<8i7>51zJ127=zf?9m6=4>{I056>{i>=:1<7?tH341?xh1<80;6<uG2708yk03:3:1=vF=639~j324290:wE<92:m212=83;pD?8=;|l500<728qC>;<4}o472?6=9rB9:?5rn764>5<6sA8=>6sa65:94?7|@;<97p`94883>4}O:?80qc8;a;295~N5>;1vb;:m:182M41:2we:9m50;3xL7053td=8i4?:0yK634<ug<?i7>51zJ127=zf?>m6=4>{I056>{i><:1<7?tH341?xh1=80;6<uG2708yk02:3:1=vF=639~j334290:wE<92:m202=83;pD?8=;|l510<728qC>;<4}o462?6=9rB9:?5rn774>5<6sA8=>6sa64:94?7|@;<97p`95883>4}O:?80qc8:a;295~N5>;1vb;;m:182M41:2we:8m50;3xLcb<@oo0V<?::0yg`?{O:?80qc8:d;295~N5>;1vb;;j:182M41:2we:8h50;3xL7053td=:=4?:0yK634<ug<==7>51zJ127=zf?<96=4>{I056>{i>?91<7?tH341?xh1>=0;6<uG2708yk01=3:1=vF=639~j301290:wE<92:m231=83;pD?8=;|l52=<728qC>;<4}o45=?6=9rB9:?5rn74b>5<6sA8=>6sa67`94?7|@;<97p`96b83>4}O:?80qc89d;295~N5>;1vb;8j:182M41:2we:;h50;3xL7053td=;=4?:0yK634<ug<<=7>51zJ127=zf?=96=4>{I056>{i>>91<7?tH341?xh1?=0;6<uG2708yk00=3:1=vF=639~j311290:wE<92:m221=83;pD?8=;|l53=<728qC>;<4}o44=?6=9rB9:?5rn75b>5<6sA8=>6sa66`94?7|@;<97p`97b83>4}O:?80qc88d;295~N5>;1vb;9j:182M41:2we::h50;3xL7053td=4=4?:0yK634<ug<3=7>51zJ127=zf?296=4>{I056>{i>191<7?tH341?xh10=0;6<uG2708yk0?=3:1=vF=639~j3>1290:wE<92:m2=1=83;pD?8=;|l5<=<728qC>;<4}o4;=?6=9rB9:?5rn7:b>5<6sA8=>6sa69`94?7|@;<97p`98b83>4}O:?80qc87d;295~N5>;1vb;6j:182M41:2we:5h50;3xL7053td=5=4?:0yK634<ug<2=7>51zJ127=zf?396=4>{I056>{i>091<7?tH341?xh11=0;6<uG2708yk0>=3:1=vF=639~j3?1290:wE<92:m2<1=83;pD?8=;|l5==<728qC>;<4}o4:=?6=9rB9:?5rn7;b>5<6sA8=>6sa68`94?7|@;<97p`99b83>4}O:?80qc86d;295~N5>;1vb;7j:182M41:2we:4h50;3xL7053td=m=4?:0yK634<ug<j=7>51zJ127=zf?k96=4>{I056>{i>h91<7?tH341?xh1i=0;6<uG2708yk0f=3:1=vF=639~j3g1290:wE<92:m2d1=83;pD?8=;|l5e=<728qC>;<4}o4b=?6=9rB9:?5rn7cb>5<6sA8=>6sa6``94?7|@;<97p`9ab83>4}O:?80qc8nd;295~N5>;1vb;oj:182M41:2we:lh50;3xL7053td=n=4?:0yK634<ug<i=7>51zJ127=zf?h96=4>{I056>{i>k91<7?tH341?xh1j=0;6<uG2708yk0e=3:1=vF=639~j3d1290:wE<92:m2g1=83;pD?8=;|l5f=<728qCjh5Gfe9Y544=9r:1qE<92:m2g?=83;pDkj4Hgg8^47228q9:>4rH341?x{zuIJHw:on:d;3e4379tJKNv>r@ARxyEF
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/ila.ngc b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/ila.ngc
deleted file mode 100644
index 77eca7a..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/ila.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
-$c`e41<,[o}e~g`n;"2*776&=$:=-*>;1684567=2:;<=>7;1234567801;<=>?012305=789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456682:;<=>?0123656789;;7=>?0023456789:;<95?0167?564N=1;==?7;1036547I=1;99>;;1G301=7N;8:7<??;022E436NK:IMO;MF06855<NFY__6JOAD^K?=?699h1:87GAPTV9EABUI[NJHI\31283:4g<9=0BB][[:@FGVGQUIMNY0<=50?37?40=AGZ^X7OKDSC?50<768>0=;4FNQWW>DBCZK6:97>115922?OIX\^1HDOKI=36>586<2;=6D@_UU8GMGBN48?1<3?:;049KPRW]]0OCLJ@<0794;7238<1CXZ_UU8GKGBH48?1<3?<;08JJUSS2NKEHRG30;2=5>453;:::6<?:HLSQQ<TZEUJSD2>9;2=0>4689;<7?<?:HLSQQ<@IGNTE1<>9;2=6>4090196D@_UU8B@ATF\@OCEJF31;2=5<=52@D[YY4NDEPAPLCOANB7=7>11591>LHW]]0OE]OKIQ>2>586<281EC^ZT;FJTGBNX5;1<3?:;38LQQVR\3ND\LJ@P=394;723;0DYY^ZT;FLTGBHX5;1<3:4302E57=4:3CE\XZ5DHC?74<76880??4FNQWW>AOE4:;1<3?<;209KPRW]]0OCL2<1;2=56=4:3E^X][[:EMA867=87;=7>85IOMVP?EHF]XD@1=::1<2?12<<?;;=<5;:HLSQQ<CAYK7?7>11097>LHW]]0OE]L33;2=55=32@D[YY4XE@>0>58682>1EC^ZT;UFF95=87;9794@UURVP?BHXH686=0>2:69KPRW]]0OC]L33;2=55=2?<?>;8;:7473656b3<0BB][[:@>7>58682<}`u?>5ude5431%;20;>8=5063<>1ANOLMJK??;6DEBC@ANOLMJKHIF09;<>>789:;<=?;;979MKVR\3^YEJ>38583:44<03CE\XZ5WD@TA91=8780M=<4A008E74<I:>0M1>14:C?5;2<I58586O33?48E92=87>0M1:14:CB<5773HKJMK=L0GDEB5678=1JOKH7;@FGVD:7601JHI\N<02==>GCL[K7=<06;@FGVD:6:730MIJ]A=30:<=FLMXJ0<:1b:CG@WG;9<0;245NDEPB843902KOH_O31?:8EABUI58546OKDSC?7;><IMNYM1:18:CG@WG;=720MIJ]A=4=<>GCL[K7;364AEFQE9>902KOH_O39?g8EABUI[NJHI\30?d8EABUI[NJHI\311<e?DBCZHXOMIJ]<03=b>GCL[KYHLJKR=31:47<IMNYM_JNDEP?56<76o1JHI\NRECG@W:6;7o0MIJ]ASFB@AT;97o0MIJ]ASFB@AT;:7o0MIJ]ASFB@AT;;7o0MIJ]ASFB@AT;<7o0MIJ]ASFB@AT;=7o0MIJ]ASFB@AT;>7o0MIJ]ASFB@AT;?7o0MIJ]ASFB@AT;07o0MIJ]ASFB@AT;17l0MIJ]AUKFLLAO494:=6OKDSCWM@NNOA6:6=0i;@FGVDRNMACLD1?18:CG@WD;8730MIJ]B=33:<=FLMXI0<?19:CG@WD;9;427LJKRC>27;?<IMNYN1?;>c9B@ATE48?1<374AEFQF972611JHI\M<0<;?DBCZK69255NDEPA868?3HNO^O2;>99B@ATE4<437LJKRC>5:==FLMXI0:07;@FGVG:?611JHI\M<8<e?DBCZK^BIEGHH=2=54=FLMXIXDKGIFJ?5?69n2KOH_L[IDJJCM:66l1JHI\MWSCG@W:76o1JHI\MWSCG@W:687l0MIJ]BVPB@AT;984m7LJKRCUQEABU4885=<5NDEPASWGCL[6:?7>1f:CG@WDPZHNO^1?<>d9B@ATE_[KOH_2>>d9B@ATE_[KOH_2=>d9B@ATE_[KOH_2<>d9B@ATE_[KOH_2;>d9B@ATE_[KOH_2:>d9B@ATE_[KOH_29>d9B@ATE_[KOH_28>d9B@ATE_[KOH_27>d9B@ATE_[KOH_26>99BBF@7N9L87LBC4:@147773KHINOL?BC@AFG>7011IY^QFNGM2?F2<K1>;>6MNd:ABWFGCM@DGMYOk;BCPGDBBAGFJXOj4C@Q@EACNF[OLMi5LARAB@@OIZLMIi6MNSBCGAJSSDH^Ji6MNSBCGAJSSDH^Ii6MNSBCGAJSSZLMJi6MNSBCGAJSSZLMI==5LCBA@4F6DK12H<5>=;BG26>EOMJAT@DMJNRG\P\VB:2IB?6MCK59@HNG>3JF@M_JLLJ68GIME12IGGOY]CMI6?FJLW@90OA\6;BMNILRSMMk0OB@[RNN?4;d<KFD_^BB311<a?FII\[EG0<?1b:ALJQTHD5;92o5LOOVQKI:6;7h0OB@[RNN?518e3JEEX_AC<07=f>EHF]XD@1?9>c9@KKRUGE6:;3l4CNLWVJJ;914i7NAATSMO84?9i2IDBY\@L=3=f>EHF]XD@1<?>c9@KKRUGE69=3l4CNLWVJJ;:;4i7NAATSMO8759j2IDBY\@L=07:g=DGG^YCA2=5?`8GJHSZFF7>;0m;BMMPWIK4;=5n6M@NUPLH94?6k1HCCZ]OM>1=;g<KFD_^BB32?`8GJHSZFF7?=0m;BMMPWIK4:;5n6M@NUPLH9556k1HCCZ]OM>07;d<KFD_^BB335<g?FII\[EG0>;50?`8GJHSZFF7?80n;BMMPWIK4:4j7NAATSMO818f3JEEX_AC<4<b?FII\[EG0;0n;BMMPWIK4>4j7NAATSMO8=8f3JEEX_AC<8<20>EHZLULICK]AUKLJZOINF=0O_KNTDF2?A4<L@<0HDO30?58@LG;994<7IGN<03=3>BNI5;92:5KI@>27;1<L@K7=908;EKB8439?2NBM1?9>69GMD:6?7=0HDO319<4?AOF4835:6JFA=3=3>BNI58;2:5KI@>15;1<L@K7>?08;EKB8759?2NBM1<;>69GMD:5=7=0HDO327<4?AOF4;=5;6JFA=0;:2=CAH695384DHC?6;1<L@K7?=06;EKB867=87=0HDO330<5?AOF4:4=7IGN<5<5?AOF4<4=7IGN<7<5?AOF4>4=7IGN<9<5?AOF40437IGNDH>3:<=CAHNB0<>19:FJEAO;98427IGNDH>26;?<L@KOE1?<>89GMDBN48>5n6JFAEK?50<7601OELJF<07=<>BNIMC7=364DHCGM94902NBMIG33?:8@LGCA5>546JFAEK?1;><L@KOE1818:FJEAO;?720HDOKI=:=<>BNIMC75384DH@?4;1<L@H7==08;EKA8479?2NBN1?=>69GMG:6;7=0HDL315<4?AOE48?5;6JFB=35:2=CAK6:;394DH@?5=803MCI0<716:FJF979?2NBN1<?>69GMG:597=0HDL323<4?AOE4;95;6JFB=07:2=CAK699394DH@?63803MCI0?917:FJF94?6>1OEO2=9?48@LD;:7=0HDL331<:?AOE4:;1<394DH@?74813MCI0>09;EKA81813MCI0809;EKA83813MCI0:09;EKA8=813MCI0407;EKA@L:7601OEOJF<02==>BNJMC7=<06;EKA@L:6:730HDLKI=30:<=CAKNB0<:1b:FJFAO;9<0;245KICFJ843902NBNIG31?:8@LDCA58546JFBEK?7;><L@HOE1:18:FJFAO;=720HDLKI=4=<>BNJMC7;364DH@GM9>902NBNIG39?58@LVF494<7IG_A=3=3>BNXH69245KIQC?7?69?2NB\L2<>`9GMUGCAY6;2n5KIQCGMU:6294j7IG_AEKS84803MC[N1>17:FJTG:66>1OE]L32?;8@LVE4:0;2:5KIQ@?7;g<L@ZIHD^30?a8@LVEL@Z7=7>1a:FJTGBNX5;5:6J@A=2=3>BHI5;;2:5KO@>25;1<LFK7=?08;EMB8459?2NDM1?;>69GKD:6=7=0HBO317<4?AIF48=5;6J@A=3;:2=CGH6:5384DNC?5;1<LFK7>=08;EMB8779?2NDM1<=>69GKD:5;7=0HBO325<4?AIF4;?5;6J@A=05:2=CGH69;394DNC?6=803MEJ0?716:FLE949?2NDM1=?>89GKD:493:5;6J@A=12:3=CGH682;5KO@>7:3=CGH6>2;5KO@>5:3=CGH6<2;5KO@>;:3=CGH62255KO@FL858>3MEJHB2>0?;8@JGCG5;:245KO@FL844912NDMIA312<:?AIFLF6:83l4DNCGK97229427IANDN>21;><LFKOC1?18:FLEAI;:720HBOKO=1=<>BHIME78364DNCGK93902NDMIA36?:8@JGCG5=546J@AEM?<;><LFKOC1717:FLEZTBO?1OCO2?>69GKG:687=0HBL310<4?AIE4885;6J@B=30:2=CGK6:8394DN@?50803MEI0<817:FLF9706>1OCO2>8?58@JD;904=7IAM<0<4?AIE4;:5;6J@B=02:2=CGK69>394DN@?66803MEI0?:17:FLF9426>1OCO2=6?58@JD;:>4<7IAM<3:=3>BHJ5822;5KOC>1:2=CGK68<374DN@?74<76>1OCO2<1?48@JD;;7<0HBL34?48@JD;=7<0HBL36?48@JD;?7<0HBL38?48@JD;1720HBLKO=2==>BHJME7==06;EMA@J:69730HBLKO=31:<=CGKND0<=19:FLFAI;9=4i7IAMDN>21?6912NDNIA314<;?AIELF6:255KOCFL878?3MEIHB2<>99GKGBH4=437IAMDN>6:==CGKND0;07;EMA@J:0611OCOJ@<9<;?AIELF622:5KOC]QAB1<LFZJ0=08;EMSE979?2ND\L2=>89GKUG;;3:5;6J@P@>0:d=CGYKOC]2?>b9GKUGCGY6:6=0n;EMSEAIW484<7IA_B=2=3>BHXK6:2:5KOQ@?6;?<LFZI0>4?>69GKUD;;7k0HB^MDNR?4;e<LFZIHB^31;2=e>BHXKND\1?15:F\GIM63L80I9??;D6B45678=>;<=>?0028AF67I1:;:9>?21236>CA<2OM8K??;DDF1@GB8=L?99O;029FJD1<MGKYHH@<;DLA3>CIJ^XNB95I01724>@7NOL;JKM?CBD3ED3<NHFXI?5IB39E@46<NMK3M5O7DE:;<=>?<2LOOH=4FEG24>@CNMLHJIHKFEDGBA5<NMZ?7KJ_E29E@W2<NMXN?6HKS028BC32NO?>JK>:FG2755=ANJIMJK>NA@CEBC@33OLM<95IFGF7?C@AM8:0JKHIC0D2BC@AKMLO46HIFGDEBA773OLMJKHIF1631G@FN11M^BCPNBD2?B?<OHDOSNGPIc9DEKBXA5:1<374G@LG[L:76k1LMCJPI=334;d<OHDOSD2>00<a?BGILVC7==<1b:EBJAYN48:82o5HAOF\M977<7h0KL@K_H>2408e3NKEHRG3114=f>AFFMUB0<>8>c9DEKBXA5;;43l4G@LG[L:6804j7JOAD^K?558e3NKEHRG3102=f>AFFMUB0<?>>c9DEKBXA5;:>3l4G@LG[L:69:4i7JOAD^K?5429j2MJBIQF<036:g=@IGNTE1?>6?`8CDHCW@6:=:0m;FCM@ZO;9825n6INNE]J847>6h1LMCJPI=32:g=@IGNTE1?=0?`8CDHCW@6:><0m;FCM@ZO;9;85n6INNE]J84446k1LMCJPI=310;d<OHDOSD2>24<a?BGILVC7=?81b:EBJAYN488<2o5HAOF\M97507h0KL@K_H>26<8f3NKEHRG313<a?BGILVC7=>>1b:EBJAYN489:2o5HAOF\M974:7h0KL@K_H>2768e3NKEHRG3126=f>AFFMUB0<=:>c9DEKBXA5;8:3l4G@LG[L:6;>4i7JOAD^K?56>9j2MJBIQF<01::d=@IGNTE1?<>c9DEKBXA5;?<3l4G@LG[L:6<84i7JOAD^K?5149j2MJBIQF<060:g=@IGNTE1?;4?`8CDHCW@6:880m;FCM@ZO;9=<5n6INNE]J84206k1LMCJPI=37<;d<OHDOSD2>48<b?BGILVC7=90m;FCM@ZO;9<:5n6INNE]J84366k1LMCJPI=366;d<OHDOSD2>52<a?BGILVC7=8:1b:EBJAYN48?>2o5HAOF\M972>7h0KL@K_H>2128e3NKEHRG314:=f>AFFMUB0<;6>`9DEKBXA5;>2o5HAOF\M97187h0KL@K_H>2248e3NKEHRG3170=f>AFFMUB0<8<>c9DEKBXA5;=83l4G@LG[L:6><4i7JOAD^K?5309j2MJBIQF<044:g=@IGNTE1?98?`8CDHCW@6::40n;FCM@ZO;9?4i7JOAD^K?5269j2MJBIQF<052:g=@IGNTE1?82?`8CDHCW@6:;>0m;FCM@ZO;9>>5n6INNE]J84126k1LMCJPI=342;d<OHDOSD2>76<a?BGILVC7=:61b:EBJAYN48=22l5HAOF\M9706k1LMCJPI=3;4;d<OHDOSD2>80<a?BGILVC7=5<1b:EBJAYN48282o5HAOF\M97?<7h0KL@K_H>2<08e3NKEHRG3194=f>AFFMUB0<68>c9DEKBXA5;343l4G@LG[L:6004j7JOAD^K?5=8e3NKEHRG3182=f>AFFMUB0<7>>c9DEKBXA5;2>3l4G@LG[L:61:4i7JOAD^K?5<29j2MJBIQF<0;6:g=@IGNTE1?66?`8CDHCW@6:5:0m;FCM@ZO;9025n6INNE]J84?>6h1LMCJPI=3::<=@IGNTE1?1b:EBJAYN4;:;2o5HAOF\M94797h0KL@K_H>1478e3NKEHRG3211=f>AFFMUB0?>;>c9DEKBXA58;93l4G@LG[L:58?4i7JOAD^K?6519j2MJBIQF<32;:g=@IGNTE1<?9?c8CDHCW@69<3l4G@LG[L:5994i7JOAD^K?6479j2MJBIQF<331:g=@IGNTE1<>3?`8CDHCW@69=90m;FCM@ZO;:8?5n6INNE]J87716k1LMCJPI=023;d<OHDOSD2=19<g?BGILVC7><750?`8CDHCW@69=40n;FCM@ZO;:84j7JOAD^K?678f3NKEHRG322<b?BGILVC7>90n;FCM@ZO;:<4j7JOAD^K?638f3NKEHRG326<b?BGILVC7>50n;FCM@ZO;:0427JOAD^K?6;g<OHDOSD2<0?c8CDHCW@68=3o4G@LG[L:4:7k0KL@K_H>07;g<OHDOSD2<4?c8CDHCW@6893o4G@LG[L:4>7k0KL@K_H>03;g<OHDOSD2<8?c8CDHCW@685374G@LG[L:46h1LMCJPI=63:d=@IGNTE1:>>`9DEKBXA5>92l5HAOF\M9246h1LMCJPI=67:d=@IGNTE1::>`9DEKBXA5>=2l5HAOF\M9206h1LMCJPI=6;:d=@IGNTE1:6>89DEKBXA5>5m6INNE]J8069i2MJBIQF<43=e>AFFMUB08<1a:EBJAYN4<95m6INNE]J8029i2MJBIQF<47=e>AFFMUB0881a:EBJAYN4<=5m6INNE]J80>9i2MJBIQF<4;==>AFFMUB080n;FCM@ZO;>94j7JOAD^K?248f3NKEHRG363<b?BGILVC7:>0n;FCM@ZO;>=4j7JOAD^K?208f3NKEHRG367<b?BGILVC7::0n;FCM@ZO;>14j7JOAD^K?2<8>3NKEHRG36?c8CDHCW@6<<3o4G@LG[L:097k0KL@K_H>46;g<OHDOSD283?c8CDHCW@6<83o4G@LG[L:0=7k0KL@K_H>42;g<OHDOSD287?c8CDHCW@6<43o4G@LG[L:01730KL@K_H>4:d=@IGNTE16?>`9DEKBXA52:2l5HAOF\M9>56h1LMCJPI=:0:d=@IGNTE16;>`9DEKBXA52>2l5HAOF\M9>16h1LMCJPI=:4:d=@IGNTE167>`9DEKBXA522245HAOF\M9>9i2MJBIQF<82=e>AFFMUB04?1a:EBJAYN4085m6INNE]J8<59i2MJBIQF<86=e>AFFMUB04;1a:EBJAYN40<5m6INNE]J8<19i2MJBIQF<8:=e>AFFMUB0471b:EBJAYN400;245HAOF\M9?9>2MJBIQ@3:EM@3=O]VYNX<5F2:K36>O6:2C9>6G<2:K76>O202CEEY^P01:8MKOSXV::46GAIUR\47><AGC_\R><8:KMMQVX8=20ECG[P^26<>OIA]ZT<;64IOKWTZ6002CEEY^P09:8MKOSXV:246GAIUR\4D><AGC_\R>M8:KMMQVX8J20ECG[P^2G<>OIA]ZT<H64IOKWTZ6A12CEEY][AUG4?LHN\V:;;6GAIU]352=NF@^T<?94IOKW[5503@DBXR>;7:KMMQY7=>1BBDZP0758MKOSW9=<7D@FT^2;3>OIA]U;5:5FNHV\4D1<AGC_S=L8;HLJPZ6D?2CEEYQ?D69JJLRX8L=0ECG[_1D4?LHN\V;;;6GAIU]252=NF@^T=?94IOKW[4503@DBXR?;7:KMMQY6=>1BBDZP1758MKOSW8=<7D@FT^3;3>OIA]U:5:5FNHV\5D1<AGC_S<L8;HLJPZ7D?2CEEYQ>D69JJLRX9L=0ECG[_0D4?LHN\V8;;6GAIU]152=NF@^T>?94IOKW[7503@DBXR<;7:KMMQY5=>1BBDZP2758MKOSW;=<7D@FT^0;3>OIA]U95:5FNHV\6D1<AGC_S?L8;HLJPZ4D?2CEEYQ=D69JJLRX:L=0ECG[_3D4?LHN\V9;;6GAIU]052=NF@^T??94IOKW[6503@DBXR=;7:KMMQY4=>1BBDZP3758MKOSW:=<7D@FT^1;3>OIA]U85:5FNHV\7D1<AGC_S>L8;HLJPZ5D?2CEEYQ<D69JJLRX;L=0ECG[_2D4?LHN\V>;;6GAIU]752=NF@^T8?94IOKW[1503@DBXR:;7:KMMQY3=>1BBDZP4758MKOSW==<7D@FT^6;3>OIA]U?5:5FNHV\0D1<AGC_S9L8;HLJPZ2D?2CEEYQ;D69JJLRX<L=0ECG[_5D4?LHN\V?;;6GAIU]652=NF@^T9?94IOKW[0503@DBXR;;7:KMMQY2=>1BBDZP5758MKOSW<=<7D@FT^7;3>OIA]U>5:5FNHV\1D1<AGC_S8L8;HLJPZ3D?2CEEYQ:D69JJLRX=L=0ECG[_4D4?LHN\V<;;6GAIU]552=NF@^T:?94IOKW[3503@DBXR8;7:KMMQY1=>1BBDZP6758MKOSW?=<7D@FT^4;3>OIA]U=5:5FNHV\2D1<AGC_S;L8;HLJPZ0D?2CEEYQ9D69JJLRX>L=0ECG[_7D4?LHN\V=;;6GAIU]452=NF@^T;?94IOKW[2503@DBXR9;7:KMMQY0=>1BBDZP7758MKOSW>=<7D@FT^5;3>OIA]U<5:5FNHV\3D1<AGC_S:L8;HLJPZ1D?2CEEYQ8D69JJLRX?L=0ECG[_6D5?LHN\VK=7D@FT^@:?LHN\VLB@H=4IOT02>OXAZU_I_CFN@VJKKYTD@INSCK?.H]VW@YH]]Z^XR\JG^LF4+SXG[OL><5F_HQ\P@TJAGK_EB@PSMK@AZHB8'_TAXVI219J[UGU\@KGS^BFCD,V[BGILVYY@R]CIBG1`>OX_AEGIR]CIBG-CZUKAJOTEIVT0\,V[BGILVYY@R]CIBG1a>OX_AEGIR]CIBG-CZUKAJOTEIVT11_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[0_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[3_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[2_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[5_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[4_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[7_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[6_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[9_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[8_-QZAFFMUX^AQ\LHAF0>MBMY<0@#:;_M18HAE53EC97AA9;MMB@@B03EELENOC4:NVP42<D\^986BZT268HPR3<2F^X8:4LTV53>KRPJST@85BUYD41>KRPO2h7@oeosTfvvohfj1Feca}Vdppmjh53G:97C?<;O1;7>H41:1E8<=4N570?K20;2D?5:5AEUULVN0<FFIGE]94NNOFVBC33GEEI<5@1:R7?UGU\h1[ECQMURKG\g=WAGUIY^@NMD18TWC63X90]<;<;P125>T?3[KFN<6J179QEHD4>o1YM@QJXUGMWLIIWHl0^LCPEYVFJVOHFVH37_OB_LMGAf=UMHNT[DJ[H^C`?WCFLV]BHYFPB49QABEB>2XNKNKNb:PFCFCFZLMHI;5]EFAFFa=UMNIGGL\KRBNH3>TBOJF@N:5]ERGW[L2<ZEEHh6\\TSCNEWUSZHG<7_][R@OA`>TT\[OLM_][RDE4?WUSZLMI=<5]SUPFCZVUAFXBXTQN109QWQTBOVZYEB\FTX]A5>U33ZKMI55\AWGGEQG6;2YBARM@LMKPMJHXKAOHG55\IL]NKAC?3ZAB\R^FN79PKPTDM<1X^A?96:QQH40B?2YY@N?9E69PVIE4:Lk0__BPA^K?4;d<[[FTMRG311<a?VTKWHUB0<?1b:QQHZGXA5;92o5\RM]B[L:6;7h0__BPA^K?518e3ZXGSLQF<07=f>UUDVKTE1?9>c9PVIYFW@6:;3l4SSN\EZO;914o7^\C_@]J84?=87h0__BPA^K?5<8f3ZXGSLQF<0<b?VTKWHUB0?0n;RPO[DYN4:4j7^\C_@]J818f3ZXGSLQF<4<b?VTKWHUB0;0n;RPO[DYN4>4j7^\C_@]J8=8f3ZXGSLQF<8<;?VTKWJOTE45\RM]@HNYN?2YY@RJPI69PVIYVWF=0__XNL^C4?VTQIEUI86]\R@68WVTE;2^O\:5[NL]MAQ><\[CL<1>19:VQMB6;99427Y\FG1>25;?<\[CL<1?=>89WVLA7489556Z]IF2?518>3]XBK=2>5?;8PWO@85;=245[RHE3841912^YEJ>319<:?QTNO96:5364TSKD497912^YEJ>321<:?QTNO969=374TSKD4945601_^DI?<31==>RUAN:7>906;UPJC5:5=730X_GH0=05:<=SZ@M;0?919:VQMB6;:1427Y\FG1>1=;><\[CL<1<19:VQMB6;;9427Y\FG1>05;?<\[CL<1==>89WVLA74:9556Z]IF2?718>3]XBK=2<5?;8PWO@859=245[RHE3861912^YEJ>339<:?QTNO9685364TSKD495912^YEJ>341<:?QTNO96?=374TSKD4925601_^DI?<51==>RUAN:78906;UPJC5:3=730X_GH0=65:<=SZ@M;09919:VQMB6;<1427Y\FG1>7=;><\[CL<1:19:VQMB6;=9427Y\FG1>65;?<\[CL<1;=>89WVLA74<9556Z]IF2?118>3]XBK=2:5?;8PWO@85?=245[RHE3801912^YEJ>359<:?QTNO96>5364TSKD493912^YEJ>361<:?QTNO96==374TSKD4905601_^DI?<71==>RUAN:7:906;UPJC5:1=730X_GH0=45:<=SZ@M;0;919:VQMB6;>1427Y\FG1>5=;><\[CL<1819:VQMB6;?9427Y\FG1>45;?<\[CL<19=>89WVLA74>9556Z]IF2?318>3]XBK=285?;8PWO@85==245[RHE3821912^YEJ>379<:?QTNO96<5364TSKD491912^YEJ>381<:?QTNO963=374TSKD49>5601_^DI?<91=f>RUAN:7494?>89WVLA741>546Z]IF2?<;><\[CL<1714:VQQ@2<\PZN?h5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR:V"DQ\RMV\J@Y7&MFR5>m4U1-J[KIXL'_TEAO I^FR*PYCYX%O@TQ6.ENZ[<Y@MGQ;Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;;Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP==S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=<S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?>]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?=]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T13_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T12_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ30Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ37Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX51[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX50[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^72U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^71U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9?W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9>W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;<Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;3Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=5S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=4S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?6]/K\WWJSWGOT<#HI3d9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?R.H]PVIRXFLU;"IBV92a8Q5)NWGETH#[PIMC,MZBV&\UO]\!KLX]:*AJ^W0ULICU>]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<?]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T21_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T20_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ02Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ01Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX67[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX66[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^44U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^43U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\:=W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\:<W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR8>Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR8=Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>;S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>:S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<8]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<7]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T29_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T28_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ0:Y+OX[[F_SCKP0/DE7`=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ0^*LYTZE^TBHQ?.ENZ=6e<]9%BSCAPD/W\MIG(AVNZ"XQKQP-GH\Y>&MFRS4QHEOY1Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ13Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX75[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX74[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^56U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^55U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;;W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;:W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR98Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR9?Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP?9S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP?8S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV=:]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV=9]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T37_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T36_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ14Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ1;Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX7=[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX7<[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^5>U'CT__B[_OG\4+@A;l1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^5Z&@UX^AZPND]3*AJ^1:i0Y=!F_OM\@+SXAEK$ERJ^.T]GUT)CDPU2"IBV_8]DAK]4U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^27U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<9W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<8W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>:Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>9Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP8?S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP8>S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV:<]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV:;]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T45_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T44_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ66Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ65Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX03[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX02[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^20U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^2?U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<1W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<0W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>2Q#GPSSNW[KCX8'LM?h5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>V"DQ\RMV\J@Y7&MFR5>m4U1-J[KIXL'_TEAO I^FR*PYCYX%O@TQ6.ENZ[<Y@MGQ?Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR?;Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP9=S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP9<S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;>]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;=]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T53_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T52_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ70Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ77Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX11[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX10[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^32U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^31U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\=?W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\=>W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR?<Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR?3Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP95S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP94S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;6]/K\WWJSWGOT<#HI3d9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;R.H]PVIRXFLU;"IBV92a8Q5)NWGETH#[PIMC,MZBV&\UO]\!KLX]:*AJ^W0ULICU:]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV8?]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T61_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T60_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ42Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ41Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX27[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX26[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^04U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^03U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\>=W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\><W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR<>Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR<=Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP:;S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP::S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV88]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV87]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T69_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T68_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ4:Y+OX[[F_SCKP0/DE7`=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ4^*LYTZE^TBHQ?.ENZ=6e<]9%BSCAPD/W\MIG(AVNZ"XQKQP-GH\Y>&MFRS4QHEOY5Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ53Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX35[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX34[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^16U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^15U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\?;W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\?:W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR=8Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR=?Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP;9S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP;8S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV9:]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV99]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T77_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T76_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ54Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ5;Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX3=[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX3<[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^1>U'CT__B[_OG\4+@A;l1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^1Z&@UX^AZPND]3*AJ^1:i0Y=!F_OM\@+SXAEK$ERJ^.T]GUT)CDPU2"IBV_8]DAK]0U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^>7U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\09W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\08W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR2:Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR29Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP4?S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP4>S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV6<]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV6;]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T85_-MZUUD]UEIR>!FG1f?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T8\,J[VTK\VDNS= KLX;0g>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[9_-MZUUD]UEIR>!FG1f?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T9\,J[VTK\VDNS= KLX;0g>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[8_-MZUUD]UEIR>!FG01?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8585;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5;;2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~310<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9756;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7=>0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=37:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;9<49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1?9>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?5285;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5;32?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~318<16>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt979::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey69<3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<33=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:5:7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0?=1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>10;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4;?5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2=6?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8719::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6943<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<3;=67=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:56;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7?=0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=12:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;;;49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1=<>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?7185;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx59>2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~337<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9506;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7?50=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=1::74<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;;7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{09>1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>75;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4=85>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2;3?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8129::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6?93<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<54=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:3?7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0961229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>7=;453\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4=49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1;?>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?1485;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5?92?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~352<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9336;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7980=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=75:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;=>49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1;7>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?1<85:2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5?5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}290?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8379::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6=>3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<71=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:1<7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0;;1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>52;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4?=5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}298?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos83?9:;1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6=2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~371<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9166;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7;?0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=50:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;?=49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|19:>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?3385;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5=<2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~379<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt91>6;80Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7;3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<92=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:?97887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{05<1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>;7;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw41>5>?5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}27>308Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?=;343\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[POS]Q@ZTH_VOE945Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZIUW[Y_S_JPRNU\SLBB>:1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO I^UJ@QNX?'Txn9:;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*OX_@N_DR9!u^v`[5)^MZUGYY8!U^NVP3023\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"GPWHFWLZ1)}V~hS<;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~7<3;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~7=3;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~7>3;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~7?3;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~783;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~793;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~7:3;7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*tt|<o0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/ua\r`e;87?n7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.v`[scd484=<6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'JC7=38?;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$OD2=>728Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYF'|Uhby!LI=1=25=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.AJ818182_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!z_blw+FO;=7<;7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(K@6=28h4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%O0=0:f:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[D)rWjd#I2>>4d8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYF'|Uhby!K<3<6b>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWH%~Sn`{/E>0:0`<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UJ#xQlnu-G8182n2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!z_blw+A:26<l0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/t]`jq)C4?4=n6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'NQ;Q#IaH/W\IP^DQ?<0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/t]`jq)@S9W%YRHKRD46?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz GZ2^*PYK]]<<7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(OR:V"XQWOSAZ2g=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.EX5X(@fA$^S@[WCX45?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz GZ3^*PYAL[O=96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'NQ:Q#[PLTV53>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWH%~Sn`{/FY2Y+SXPFXHU;l4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%LW?S!GoJ-QZKRPJS=:6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'NQ9Q#[PFEPF20=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.EX6X(RWE__::5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&MP>P Z_YMQG\0e3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,C^5Z&NdC"XQBUYAZ23=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.EX7X(RWONYI;;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%LW>S!U^NVP31<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UJ#xQlnu-D_6[)]VRD^NW9b:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[D)rWjd#JU;]/EmL+SXE\RHU;84U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%LW9S!U^DGV@023\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,C^2Z&\UGYY88;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$KV:R.T][KWE^>k1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*A\=T$LbE Z_LW[G\013\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,C^3Z&\UMH_K95:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[D)rWjd#JU:]/W\HPR1?2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!z_blw+B]2U'_TTB\LY748Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYF'|Uhby!H[7_-QZ@CZL<>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(OR<V"XQCUU44?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz GZ4^*PY_G[IR9k5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&Y7<3;i;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$_1?15g9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZG(}Viex"]32?7e?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz S=1=1c=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.Q?0;3a3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,W939=o1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*U;>7?j7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\vvr0;2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!F_VKGPMY1&|Uo"WJS^NVP3(RWE__:864U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]A+wus>91^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RL u^amp*EN484=<6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'JC7>38?;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\F*sXkg~$OD2<>728Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!LI=6=25=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVH$yRmat.AJ8082n2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_blw+A:76<l0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QM/t]`jq)C484>j6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'M6928h4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]A+pYdf}%O0>0:f:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[G)rWjd#I2;>4d8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!K<4<5f>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/FY3Y+Ai@'_TAXVLY748Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!H[1_-QZ@CZL<>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PB.w\gkr(OR:V"XQCUU44?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXJ&Tocz GZ2^*PY_G[IR:o5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&MP=P HnI,V[HS_KP<=7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PB.w\gkr(OR;V"XQIDSG51>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/FY2Y+SXD\^=;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'NQ:Q#[PXNP@]3d<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-D_7[)OgB%YRCZXB[52>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/FY1Y+SXNMXN:85Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&MP>P Z_MWW22=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVH$yRmat.EX6X(RWQEYOT8m;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\F*sXkg~$KV=R.FlK*PYJ]QIR:;5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&MP?P Z_GFQA33<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-D_6[)]VF^X;94U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]A+pYdf}%LW>S!U^ZLVF_1j2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_blw+B]3U'MeD#[PMTZ@]30<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-D_1[)]VLO^H8:;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\F*sXkg~$KV:R.T]OQQ003\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTN"{Pcov,C^2Z&\USC_MV679V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZD(}Viex"IT5\,V[CBUM??0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QM/t]`jq)@S<W%YRBZT758Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!H[4_-QZ^HZJS>j6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'Z6;28h4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]A+pYdf}%X0<0:f:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[G)rWjd#^2=>4d8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!\<2<6b>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/R>7:0`<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-P8082i2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_sqw2d=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVNGU"IPRDE\FLR\8T$^SKJ]E7c8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYCDP%LS_KH_CKW_4[)]VLO^H8n;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\@I_(OVXNKRLFTZ0^*PYAL[O=m6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_ENZ+BYUMNUIEYU<]/W\BATB>h1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RJCY.E\V@AXJ@^P8P Z_GFQA3g<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UO@T!H_SGD[GOSS<W%YRHKRD;1?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SCN+LYQ>'_TO^QMR@O\GDUDIMOTZ;!F_EGSPMYK\L[T??E!U^QAVDKX8&CTN<6DGU2-qZtfek;3#XQ]AL@2<@7>k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTFE&CTZ; Z_BQ\FWGJWJKXOLJJ_W4,MZBBX]BT@YK^_20H*PYTJ[KFS=!F_C15OBR7&NUYM@L<6Z2^*pYuidh8:"[PR@OA73?d3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WGJ'@U]:#[PCR]AVDKXKHYHMIKPV7-J[ACW\AUGXH_P33I-QZUEZHGT<"GPB24HCQ6)OVXJAO=9[0_-qZtfek9=#XQ]AL@020d<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYDGEUFYU!F6/W\IP^1<&GfyuQ@_026f>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[FIKWD_S#D8!U^OV\32(EdsSBQ>14a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]@KIYJ]Q%B:#[PMTZ50*Kj}qUDS<?>5b9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^ALHZKRP&C="XQBUY47+HkrpVET=<<:b:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_BMO[HS_'@<%YRCZX76,IhsWFU:>8m4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQLOM]NQ])N>'_TAXV94.Onq}YHW88:9n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHRM@L^OV\*O1&\UFYU8;/Lov|ZIX9;8>o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOSNAC_LW[+L0)]VG^T;: Mlw{[JY6::?i7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NTOBBPMTZ,M3(RWD_S:9!Bmtz\KZ74=j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K5*PYJ]Q<?#@czx^M\5672k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H4-QZKRP?>$A`{w_N]2773e3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXKFFTAXV I7,V[HS_>=%FaxvPO^371a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZEHDVG^T"G9.T]NQ]03'Dg~tRAP5^d41d=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZEHDVG^T"G9.T]NQ]03'Dg~tRAP64f8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]@KIYJ]Q%B:#[PMTZ50*Kj}qUDS;Qi74c8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]@KIYJ]Q%B:#[PMTZ50*Kj}qUDS:;n;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPCNN\IP^(A?$^S@[W65-Nip~XGV2?i6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN48:58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5;58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5858i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5958i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5>58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5?58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5<58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5=58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5258i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5358n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)C494?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*B;994?o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*B;97>h7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+A:56=i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,@959<j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-G8183k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.F?1;2d3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/E>5:1e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ D=5=0f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!K<9<7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"J39?7;?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU?]/EmL+SXE\RHU8=4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR:V"XQIDSG66>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT0\,V[ISS==1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_5[)]VRD^NW:4:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP==S!U^DGV@343\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY24X(RWE__985Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S8:V"XQWOSAZ1==R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[0_-CkN)]VG^TNW:3:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP=P Z_GFQA04<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ3^*PYK]]??7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]6U'_TTB\LY4:8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV<R.FlK*PYJ]QIR9>5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S;W%YRHKRD71?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU=]/W\HPR2<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX6X(RWQEYOT;7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ8Q#IaH/W\IP^DQ<90Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^5Z&\UMH_K:2:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP?P Z_MWW11=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[2_-QZ^HZJS>46[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\<T$LbE Z_LW[G\343\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY7Y+SXNMXN9?5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S=W%YRBZT468Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV:R.T][KWE^=11^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_0[)OgB%YRCZXB[67>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT5\,V[CBUM<80Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^3Z&\UGYY;;;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ>Q#[PXNP@]0><]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ4^*BhO&\UFYUMV529V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW;S!U^DGV@353\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY5Y+SXD\^>86[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\>T$^SUA]CX7;?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU8]/EmL+SXE\RHU8=4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR=V"XQIDSG66>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT7\,V[ISS==1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_2[)]VRD^NW:8:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP4P HnI,V[HS_KP?87X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]?U'_TJI\J539V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW5S!U^NVP02<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ:^*PY_G[IR955Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S0W%KcF!U^OV\F_2;2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX=X(RWONYI8<4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR3V"XQCUU77?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU6]/W\\JTDQ=i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,W969<m1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-P8469<j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-P8483k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.Q?6;2d3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/R>0:1e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ S=6=0f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!\<4<7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"]36?6`?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#^28>5a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$_1614b9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%X040;6:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QNDEP\M969<?1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+RTXIMNYSD2>>548Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"Y]_@FGVZO;:7>=7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVKOH_QF<2<72>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]B@ATXA5>58;5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTMIJ]_H>6:10<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.UQ[DBCZVC7:3:9;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%\^ROKDS]J8283>2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,SWYFLMXTE161479V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PAEFQ[L:>6=<0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG30?64?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!XR^FBPDYN48:58:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>25;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0<<1469V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:6;7><7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVNJXLQF<06=02=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/VP\@DRFW@6:93:8;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%\^RJNT@]J8409<>1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+RTXLH^JSD2>7?64?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!XR^FBPDYN48258:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>2=;213\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0<0;7:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QKAUC\M9476==0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG320<73>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA5892994U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&]YSIO[A^K?6683?2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,SWYCI]KTE1<;>558Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"Y]_ECWEZO;:<4?;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(_[UOMYOPI=05:11<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.UQ[AGSIVC7>:0;7:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QKAUC\M94?6==0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG328<72>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA5858:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>04;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0>?1469V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:4:7><7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVNJXLQF<21=02=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/VP\@DRFW@6883:8;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%\^RJNT@]J8639<?1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+RTXLH^JSD2<>558Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"Y]_ECWEZO;<<4?;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(_[UOMYOPI=65:11<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.UQ[AGSIVC78:0;7:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QKAUC\M92?6==0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG348<72>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA5>58:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>64;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB08?1469V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:2:7><7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVNJXLQF<41=02=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/VP\@DRFW@6>83:8;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%\^RJNT@]J8039<>1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+RTXLH^JSD2:6?64?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!XR^FBPDYN4<=58:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>6<;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0871479V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:26==0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG361<73>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA5<:2994U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&]YSIO[A^K?2783?2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,SWYCI]KTE18<>558Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"Y]_ECWEZO;>=4?;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(_[UOMYOPI=46:11<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.UQ[AGSIVC7:;0;7:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QKAUC\M9006==0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG369<73>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA5<22984U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&]YSIO[A^K?2;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0:>1469V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:097><7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVNJXLQF<60=02=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/VP\@DRFW@6<?3:8;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%\^RJNT@]J8229<>1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+RTXLH^JSD285?64?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!XR^FBPDYN4><58:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>43;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0:61469V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:017>=7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVNJXLQF<6<73>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA52;2984U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&]YSIO[A^K?<;213\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB040;1:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QJN^K7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]`kiYflmxThaw30?6`?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^alhZgcl{Uo`t2>>5a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_bmo[dbczVngu1<14b9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPcnn\eabuWmfr0>0;c:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQlom]b`atXles783:l;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRm`l^cg`wYcdp6>29j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZbkq5?5=9j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6;29j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6:29j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6929j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6829j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6?29j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6>29k4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnllUyy:;;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>3:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;;29;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=32:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;929;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=30:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;?29;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=36:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;=29;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=34:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;329;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=3::12<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<32=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4;;5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<30=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4;95885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<36=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4;?5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<34=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4;=5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<3:=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4;35895Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<3<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;94?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo330<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;;4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo332<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;=4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo334<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;?4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo336<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;14?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo338<70>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2;0?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:397>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2;2?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:3;7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2;4?67?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:36=>0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1;1459V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPd`vb8383<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k7;3:;;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>;:12<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi535855Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nT~byPaefq858312_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYug~Ujhi|311<7<>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]qkrYflmx7=3:7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhR|`w^cg`w:56=20Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcW{e|Sljkr=1=0==R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\vjqXimny090;8:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQ}ov]b`at;=7>37X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVxd{Rokds>5:1><]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[wipWhno~191499V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPrnu\eabu414?46[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUyczQndep?=;243\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`ZthVoe885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nT~byPeo]b00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\vjqXmgUi=;5Z0.K\JJYC&\UB@L!Z_EMVP7d<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&IF\R\JSDV01>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVCEXNO__G,V[FGW_L:896[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^KMPFGWWO$^SNO_WD36g>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZECGGO$ERWJSMWW2+OXQLYT^]C!I^[FWZIUMN$DYYQ]EF72?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[FBHFL%BSTK\LTV5*LY^MZUY\@ Z_LW[B2343\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWJNDBH!F_XGPHPR1&@URI^Q]PL,V[VTK;;UJ9>5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQLDNLF+LY^MZF^X; F_XGP[WVJ&\UX^A==_C64?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[FBHFL%BSTK\LTV5*VTKWD_S8:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQLDNLF+LY^MZF^X; \RM]R742?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWJNDBH!F_XGPHPR1&ZXGS\2?>5:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\GAIIM&CTUH]CUU4-WWJXY5;5995Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQLMQPFW@R(AVSN_A[[6/K\]@UXZYG%YRCZXG562>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZEJX[OXIY!F_XGPHPR1&@URI^Q]PL,V[VTK;;UJ9;5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQLMQPFW@R(AVSN_A[[6/K\]@UXZYG%YR]]L20\F1g<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXKDZYI^K[/H]ZAVJR\?$X^AQ^306a?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[FKWZLYNX"GPYDQOQQ0)[[FT]1>14c9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]@IUTB[L^$ERWJSMWW2+UUDV[7=3;n;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_OQ3+LY^MZF^X; F_XGP[WVJ&@URI^Q@RDE-KPRXZLM>>6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR@\0.K\]@UK]]<%ERWJS^PSI+SXE\RM;ROM539V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW5)NWPOX@XZ9.H]ZAVYUXD$^S@[WF6]@@1`<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXFZ:$ERWJSMWW2+OXQLYT^]C!U^OV\C>292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX<"GPYDQOQQ0)AVSN_R\_M/W\WWJ4:VK>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR@\0.K\]@UK]]<%ERWJS^PSI+SX[[F8>RL:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP4*OXQLYGYY8!I^[FWZTWE'_T__B<2^A65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT8&CTUH]CUU4-MZ_B[VX[A#[PSSN06ZB312_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX<"GPYDQOQQ0)[[FTAXV8<1<7=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT8&CTUH]CUU4-WWJXE\R<0<0;6:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP4*OXQLYGYY8!SSN\IP^?<11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UE_=!F_XGPHPR1&ZXGS\=><1<7<>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT8&CTUH]CUU4-WWJXY:;7=3:7;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_OQ3+LY^MZF^X; \RM]R74:56=<0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_TB^> I^[FWISS>'YY@R_30?65?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU7'@URI^BZT7,PVIYV484?:6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR@\0.K\]@UK]]<%__BPQ=0=03=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[9%BSTK\LTV5*VTKWX6828o4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR3,MZ_B[E__:#GPYDQ\VUK)AVSN_RA]EF,LQQYUMN?97X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]>/H]ZAVJR\?$BSTK\_SRN*PYJ]QL<SLL:2:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP5*OXQLYGYY8!I^[FWZTWE'_TAXVI7^AG0c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[8%BSTK\LTV5*LY^MZUY\@ Z_LW[B=363\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWGY:#DQVERNVP3(NWPOXS_^B.T]PVI55WH?:7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]>/H]ZAVJR\?$BSTK\_SRN*PYTZE99SO;>;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_OQ2+LY^MZF^X; F_XGP[WVJ&\UX^A==_B72?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU6'@URI^BZT7,J[\CTW[ZF"XQ\RM11[A2>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWGY:#DQVERNVP3(TZEUFYU930?6:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU6'@URI^BZT7,PVIYJ]Q=7=3:9;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_OQ2+LY^MZF^X; \RM]NQ]>302_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX="GPYDQOQQ0)[[FT]>?30?6;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU6'@URI^BZT7,PVIYV;86:2964U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR3,MZ_B[E__:#]]L^S05949<?1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UE_<!F_XGPHPR1&ZXGS\2?>548Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\JV7(AVSN_A[[6/QQHZW;97>=7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]>/H]ZAVJR\?$X^AQ^<3<72>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT9&CTUH]CUU4-WWJXY5958:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQ\CD-J[\CTD\^="XQ\RMA22@2?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWZIF\NK I^[FWISS>'_T__B<2438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\WFTT\&CTUH]CUU4-MZ_B[VX[A#[PMTZE305<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SX[JXXX"GPYDQOQQ0)AVSN_R\_M/W\WWJ4:VK>?6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR]LRRV,MZ_B[E__:#GPYDQ\VUK)]VYY@><PB558Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\WFTT\&CTUH]CUU4-WWJXY:;?46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR]LRRV,MZ_B[E__:#]]L^S?4;2?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWZIY_Y!F_XGPHPR1&ZXGS\2>>558Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\SFC(AVSN_A[[6/W\WWJD9?O?56[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YRYGCLR@A*OXQLYGYY8!U^QQH64312_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]V]GO@^LE.K\]@UK]]<%YR]]L201=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ([JD_SNK=a:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,WFHSWJG[>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/RAMPZEJXVIN>n5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/RAMPZEJXV[9o6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B SBLW[WCTM]>;7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#NO__@FGVZhbp}6;29>4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ C@R\EABUWgosx1?1419V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-@EUYFLMXTbhv{<3<74>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*EFXVKOH_Qaeyv?7;273\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'JK[SLJKR^lf|q:36=:0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$OL^PAEFQ[kc|5?58=5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!LAQ]B@ATXflr0;0;0:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.ABTZGCL[Ueiuz37?63?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+FGWWHNO^R`jxu>;:16<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(KHZTMIJ]_og{p9?9<01^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS=Q[O^47O+@X[LFP<P Z_RGO0d=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW9U_CR8;K/D\W@J\99W%YR]JL5c8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZ6X\FU=8F I_RGO_47Z&\UXIA:n;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]3[QIX>=A%JR]JLZ31Y+SX[LF?m6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GP0^VL[32L&OUXIAU>3\,V[VCK<h1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS=Q[O^47O+@X[LFP=9S!U^QFH1g<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AV:TXBQ94J,E[VCKS8?V"XQ\EM6:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LY7W]ET:9E!F^QFH^7Z&\UXIA:6;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]3[QIX>=A%JR]JLZ0^*PYTME>27X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ?_UM\21M)NVYN@V=R.T]PAI2>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@U;SYAP65I-BZUBDR>V"XQ\EM6:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LY7W]ET:9E!F^QFH^3Z&\UXIA:6;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]3[QIX>=A%JR]JLZ4^*PYTME>27X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ?_UM\21M)NVYN@V9R.T]PAI2>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@U;SYAP65I-BZUBDR2V"XQ\EM6:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LY7W]ET:9E!F^QFH^?Z&\UXIA:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]3[QIX>=A%ER]]L/W\W@J_=81^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSD@[C@R-BZEFXVKOH_U?]/W\GDVXIMNY985Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY3Y+SXKHZTMIJ]_LW[17=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW@D_OL^!F^ABTZGCL[Q;Q#[PiBCS[DBCZ<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ERGATBCS*CYDIYUJHI\T1\,V[FGWWHNO^8;4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX5X(RWJK[SLJKR^OV\04<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVCEXNO_.G]@EUYFLMXP=P Z_hABTZGCL[?:7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQFNUABT+@XKHZTMIJ][3_-QZEFXVKOH_;:;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_7[)]VIJ\ROKDS]NQ]353\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UBBYMNP/D\GDVXIMNYW?S!U^k@EUYFLMX>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPIOV@EU(AWJK[SLJKRZ1^*PYDIYUJHI\:5:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^5Z&\UHM]QNDEP\IP^2:2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTECZLAQ,E[FGWWHNO^V=R.T]jGDVXIMNY9<5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY7Y+SXKHZTMIJ]549V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[LHSKHZ%JRMNP^CG@W]3U'_TOL^PAEFQ[HS_=;1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSD@[C@R-BZEFXVKOH_U;]/W\mFGWWHNO^8?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX1X(RWJK[SLJKR478Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZOI\JK["KQLAQ]B@AT\=T$^SNO__@FGVZKRP<80Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ERGATBCS*CYDIYUJHI\T5\,V[lEFXVKOH_;>;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_3[)]VIJ\ROKDS76?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYNF]IJ\#HPC@R\EABUS?W%YRMNP^CG@WYJ]Q?97X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQFNUABT+@XKHZTMIJ][7_-QZoDIYUJHI\:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^1Z&\UHM]QNDEP61>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXAG^HM] I_BCS[DBCZR=V"XQLAQ]B@ATXE\R>>6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPIOV@EU(AWJK[SLJKRZ5^*PYnKHZTMIJ]509V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[LHSKHZ%JRMNP^CG@W]?U'_TOL^PAEFQ10=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW@D_OL^!F^ABTZGCL[Q3Q#[PC@R\EABUWD_S9?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY;Y+SXaJK[SLJKR438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZOI\JK["KQLAQ]B@AT\1T$^SNO__@FGV03<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVCEXNO_.G]@EUYFLMXP5P Z_BCS[DBCZVG^T8<4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX=X(RW`IJ\ROKDS71?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.AJ8482:2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)DA5859?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$OD2<>408Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/BK?0;353\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*EN4<4>>6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%HE181539V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ CH>4:04<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+FO;07?97X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&IB040:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!K<1<65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-G848292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)C4;4>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%O0>0:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!K<5<65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-G808292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)C4?4>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%O0:0:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!K<9<65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-G8<82l2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S9W%KcF!U^OV\F_202_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S9W%YRHKRD74?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX4X(RWE__945Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV>R.T][KWE^=m1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(OR;V"J`G.T]NQ]E^=11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(OR;V"XQIDSG63>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-D_4[)]VF^X874U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU>]/W\\JTDQ<n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ9Q#IaH/W\IP^DQ<20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ9Q#[PFEPF12=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,C^4Z&\UGYY;6;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT2\,V[]IUKP?o7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP?P HnI,V[HS_KP?37X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP?P Z_GFQA01<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+B]4U'_T@XZ:9:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[2_-QZ^HZJS>h6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW9S!GoJ-QZKRPJS>46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW9S!U^DGV@303\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*A\<T$^SA[[589V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ6^*PY_G[IR9i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV;R.FlK*PYJ]QIR955Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV;R.T]E@WC2?2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S<W%YRBZT4;8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY6Y+SXPFXHU8j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU9]/EmL+SXE\RHU864U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU9]/W\BATB=>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(OR<V"XQCUU7:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX2X(RWQEYOT;k;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT7\,DjM(RWD_SOT;7;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT7\,V[CBUM<=0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ<Q#[PLTV6=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-D_2[)]VRD^NW:d:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[9_-CkN)]VG^TNW:8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[9_-QZ@CZL?<7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP4P Z_MWW1<=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,C^>Z&\USC_MV599V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ;^*PYAL[O>;6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW4S!U^NVP0?<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+B]>U'_TTB\LY438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/R>3:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+V:66<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'Z6928?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#^2<>438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/R>7:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+V:26<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'Z6=28?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#^28>438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/R>;:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+V:>6=20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!LI=3=0==R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&IB0?0;8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+FO;;7>37X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ CH>7:1><]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%HE1;1499V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*EN4?4?46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/BK?3;2?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$OD27>5:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)DA5358:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.F?4;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$H1?1469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*B;:7><7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ D=1=02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&N783:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,@939<>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"J36?64?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(L5=58:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.F?<;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$H171529V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\8T$LbE Z_LW[G\2b3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV>R.T]E@WC3l2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU?]/W\HPR3n2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU?]/W\\JTDQ<90Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[0_-CkN)]VG^TNW;e:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]6U'_TJI\J4e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\9T$^SA[[4g9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\9T$^SUA]CX70?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR8V"J`G.T]NQ]E^<l1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"IT2\,V[CBUM=n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[3_-QZJR\=l0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[3_-QZ^HZJS>?6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY0Y+Ai@'_TAXVLY5g8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S:W%YRHKRD6g?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR9V"XQCUU6e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR9V"XQWOSAZ16=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP8P HnI,V[HS_KP>n7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ GZ6^*PYAL[O?h6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY7Y+SXD\^?j6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY7Y+SXPFXHU8=4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_0[)OgB%YRCZXB[7a>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'NQ>Q#[PFEPF0a=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP9P Z_MWW0c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP9P Z_YMQG\343\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV8R.FlK*PYJ]QIR8h5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.EX2X(RWONYI9j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_3[)]VF^X9h4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_3[)]VRD^NW:3:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]0U'MeD#[PMTZ@]1c<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%LW:S!U^DGV@2c3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV9R.T]OQQ2a3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV9R.T][KWE^=:1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"IT8\,DjM(RWD_SOT:j;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,C^>Z&\UMH_K;d:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]?U'_T@XZ;f:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]?U'_TTB\LY5g8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S0W%YRHKRD6g?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR3V"XQCUU6e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR3V"XQWOSAZ02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&Y7<3:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,W979<>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"]32?64?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR([5958:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.Q?0;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$_1;1469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*U;>7><7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ S=5=02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&Y743:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,W9?9;?1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%^SO\D0248Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,QZDUC82>7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#XQ\COV\GHV(AVIXSJOAD/W\GVY@IGNT__B I^T5*PYD[VMJBIQ\RM]U2*OX]ZOT^]CPND2-QZAFFMUX^AQ\EU:b?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+PYTKG^TO@^ I^AP[BGIL'_TO^QHAOF\WWJ(AV\="XQLS^EBJAYTZEU]:"GPURG\VUKXFL:%YRINNE]PVIYTM]UF_HZ76:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.W\SFHSWAIF\"GPCR]DEKB)]VIXSJOAD^QQH*OX^?$^SN]PG@LG[VTKW_<$ER[\E^PSIZHB8'_TKL@K_RPO[VCS0k1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%^SZMAT^J@IU)NWJYTKL@K.T]@WZAFFMUX^A!F_W4-QZETWNKEHR]]L^T5+LYR[LUY\@QAE1,V[BGILVYY@R]JT^OPAQ>13\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'\U\OCZPLBOS+LYD[VMJBI Z_BQ\CDHCWZXG#DQY6/W\GVY@IGNT__BPV7-J[PUBW[ZFSCK?.T]DEKBX[[FT_HZ7b:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.W\SFHSWEIF\"GPCR]DEKB)]VIXSJOAD^QQH*OX^?$^SN]PG@LG[VTKW_<$ER[\E^PSIZHB8'_TKL@K_RPO[VCSWDYNX>l4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ cge\`drf4948n6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"mig^fbpd:66:h0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$okiPd`vb8784j2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&imkRjnt`>0:6d<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(komThlzn<5<74>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*eaoVnjxlQyeb>24;273\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'jllSio{a^tfg9766=:0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$okiPd`vb[scd48858=5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!lff]geqgX~li7=>0;0:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.aecZbf|hU}in2>4?63?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+f``WmkmRxjc=36:16<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(komThlzn_wg`8409;o1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%hjjQkauc\r`e;979m7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#nhh_ecweZpbk585?k5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!lff]geqgX~li7?3=i;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/bdd[agsiV|no1:13g9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-`bbYci}kTzhm35?1e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+f``WmkmRxjc=4=7c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)dnnUomyoPvda?3;5a3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'jllSio{a^tfg9>9;o1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%hjjQkauc\r`e;179h7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#dMNP^CG@W:76:i0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$eNO__@FGV979;j1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%bOL^PAEFQ8784k2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&cHM]QNDEP?7;5d3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'`IJ\ROKDS>7:6e<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(aJK[SLJKR=7=7f=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)nKHZTMIJ]<7<0g>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*oDIYUJHI\37?1`?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+lEFXVKOH_27>2a8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,mFGWWHNO^171399V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-jWFHS494846[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"g\COV?5;5?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'`YHBY2=>2:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,mVEI\595?55Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!fSBLW818402_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&cXOCZ35?1;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+lUDF]6=2>64U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ iRAMP919;11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%b_N@[<9<0<>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*oTKG^753<j;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[VEI\VIF\R_=8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZRUAN827X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_UPJC54>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SY\FG00e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RW^IEXRFLMQ]R6c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\U\OCZPLBOS[T4>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%\OCZPCD0a?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)PKG^TDNC_2d9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+REI\VBHA]QLE3f8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*QDF]UCO@^PQ3`8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*QDF]UGO@^=e:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,SFHSWEIF\RMJ2e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+REI\VFHA]Q^2e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1>12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1?12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1<12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1=12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1:12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1;12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1812e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1912e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1612e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1712b9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+lEFXV]YSH@=d:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,mQTNONOYSD@=e:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,mQTNONOYSB[[3`9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO[LYTZE^TBHQ>.T]@@JHBWDYNX>j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L^K\WWJSWGOT=#[PCLRQAVCSWDYNX>64U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L^K\WWJSWGOT=#[PNR2\IVCS;11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XGSDQ\RMV\J@Y6&\UE_<QBSDV0e>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJXAVYY@YQAE^3-QZUDZZ^TA^K[259V4*OXFFUO"XQFL@-V[WUS'NUY_YU?]/W\VVR5<2_;#DQAO^F-QZOKI&_T^^Z G^PPP^7Z&\UY_Y<;;T2,MZHHWM$^SDBN/T]QWQ)@W[Y_W?S!U^PPP72<]9%BSCAPD/W\MIG(]VXXX"IPRRVX7X(RW[Y_>95Z0.K\JJYC&\UB@L!Z_SQW+BYU[]Q?Q#[PRRV10>S7'@UECRJ!U^KOE*SXZZ^$KR\\TZ7^*PYU[]8?7X> I^LL[A(RW@FJ#XQ]SU-D[WUSS?W%YR\\T368Q5)NWGETH#[PIMC,QZTT\&MT^^ZT7\,V[WUS:91^<"GPNN]G*PYNDH%^S_][/ICOPZvrdzo:56[?/H]MKZB)]VCGM"[PRRV,TJT582_;#DQAO^F-QZOKI&_T^^Z PSG\V@UB\98;7X> I^LL[A(RW@FJ#XQ]SU-SV@YUMZO_=?64U1-J[KIXL'_TEAO U^PPP*SXI[GTTKK]/T]@H@GU:>1^<"GPNN]G*PYNDH%^S_][/T]BVHY_NLX$YRJ@UU0;?P6(AVDDSI Z_HNB+PYU[]%^SL\B_YDFV*SXLF__<?64U1-J[KIXL'_TEAO U^PPP*SXI[GTTKK]/T]GKPR6;=1^<"GPNN]G*PYNDH%^S_][/T]BVHY_NLX$YRIJN^FFHD_\9T$^SKJ<4:W3+LYIGVN%YRGCA.W\VVR(]VKYARVIES-V[BCIWMOGMTU=]/W\BA533\:$ER@@_E,V[LJF'\UY_Y!Z_@PN[]@BZ&_TKH@PDDNB]^5Z&\UMH>:4U1-J[KIXL'_TEAO U^PPP*SXI[GTTKK]/T]DAKYCMEKRW9S!U^DG6==R8&CTBBQK.T]JHD)RW[Y_#XQNRL][B@T(]VXMH_K=8:W3+LYIGVN%YRGCA.W\VVR(]VKYARVIES-V[Q@CZL8h7X> I^LL[A(RW@FJ#XQ]SU-V[DTJWQLN^"jfn^nbpfnbl;?0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#dMCR3:8Q5)NWGETH#[PIMC,QZTT\&_TM_CPXGGQ+lBNF5:5>55Z0.K\JJYC&\UB@L!Z_SQW+PYFZDUSJH\ iEKM8485>2_;#DQAO^F-QZOKI&_T^^Z U^CQIZ^AM[%bHB[[2e9V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,mAIR\Vngu1>12e9V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,mAIR\Vngu1?12e9V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,mAIR\Vngu1<12e9V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,mAIR\Vngu1:1289V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+PYDDLKY>55Z0.K\JJYC&\UB@L!Z_SQW+PYOIE^TTKK]/T]GKPR512_;#DQAO^F-QZOKI&_T^^Z U^JBHQY_NLX$YRJ@UU21=>S7'@UECRJ!U^KOE*SXZZ^$YRFNLU][B@T(]VNDYY?<5:W3+LYIGVN%YRGCA.W\VVR(]VBJ@YQWFDP,QZABFVNN@LWT1\,V[CB4=2_;#DQAO^F-QZOKI&_T^^Z U^JBHQY_NLX$YRIJN^FFHD_\:T$^SKJ=9:W3+LYIGVN%YRGCA.W\VVR(]VBJ@YQWFDP,QZTAL[O956[?/H]MKZB)]VCGM"[PRRV,QZNFD]USJH\ U^VE@WC5l2_;#DQAO^F-QZOKI&_T^^Z U^JBHQY_NLX$hd`Pl`v`l`b5>2_;#DQAO^F-QZOKI&_T^^Z U^JBHQY_NLX$eNB]289V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+lBNF5:5>45Z0.K\JJYC&\UB@L!Z_SQW+PYOIE^TTKK]/hFJJ979:>1^<"GPNN]G*PYNDH%^S_][/T]KEIRXPOOY#dJ@UU0f?P6(AVDDSI Z_HNB+PYU[]%^SEOCT^ZEAW)nLF__Sibv<1<1a>S7'@UECRJ!U^KOE*SXZZ^$YRFNLU][B@T(aME^XRjcy=0=5g=R8&CTBBQK.T]JHD)RW[Y_#XQ_OS3g?P6(AVDDSI Z_HNB+PYU[]%^S]\\T13g?P6(AVDDSI Z_HNB+PYU[]%^S]\\T03`?P6(AVDDSI Z_HNB+PYU[]%^S_][00d8Q5)NWGETH#[PIMC,QZTT\&cYI^K[<1<11>S7'@UECRJ!U^KOE*SX[]K_#LM[RDQFPZvrdzo9<6[?/H]MKZB)]VCGM"[PSUCW+DESWmymy<:;T2,MZHHWM$^SDBN/T]PPDR(KHZT^H]JT^fo}47a3\:$ER@@_E,V[LJF'\UXXLZ DHPW]ZB79o1^<"GPNN]G*PYNDH%^S^ZNT.FJVQ_XL88;7X> I^LL[A(RW@FJ#XQ\T@V,@LTSQVYN@?<4U1-J[KIXL'_TEAO U^QWEQ)CA[^RSi}{au07?P6(AVDDSI Z_HNB+PYT\H^$H^ZNT^gm[aj~9;>0Y=!F_OM\@+SXAEK$YR][AU-GWQGSWldThaw=259V4*OXFFUO"XQFL@-V[VRF\&NXXLZPeo]gh|5592_;#DQAO^F-QZOKI&_T_YO[/EQWEQYkghn9j6[?/H]MKZB)]VCGM"[PSUCW+CYT[]K_W=S!I^QWEQ(RWZ^JX>>4U1-J[KIXL'_TEAO U^QWEQ)AWZY_MYU>0\,J[VRF\'_T_YO[2g9V4*OXFFUO"XQFL@-V[VRF\&LT_^ZNTZ3^*LYT\H^%YR][AU0e?P6(AVDDSI Z_HNB+PYT\H^$JR]\T@VX6X(NWZ^JX#[PSUCW6c=R8&CTBBQK.T]JHD)RWZ^JX"HPSRVBP^5Z&@UXXLZ!U^QWEQ4a3\:$ER@@_E,V[LJF'\UXXLZ F^QPPDR\<T$BS^ZNT/W\WQGS:o1^<"GPNN]G*PYNDH%^S^ZNT.D\WVRF\R?V"DQ\T@V-QZUSI]8m7X> I^LL[A(RW@FJ#XQ\T@V,BZUT\H^P:P F_RVBP+SX[]K_>k5Z0.K\JJYC&\UB@L!Z_RVBP*@X[Z^JXV9R.H]PPDR)]VY_MY<i;T2,MZHHWM$^SDBN/T]PPDR(NVYXXLZT8\,J[VRF\'_T_YO[2g9V4*OXFFUO"XQFL@-V[VRF\&LT_^ZNTZ;^*LYT\H^%YR][AU07?P6(AVDDSI Z_HNB+PYT\H^$KR@\[1_-QZHTY;>0Y=!F_OM\@+SXAEK$YR][AU-D[KU\9T$^SC]^259V4*OXFFUO"XQFL@-V[VRF\&MTB^U=]/W\JVW5<2_;#DQAO^F-QZOKI&_T_YO[/F]MW^5Z&\UE_\<;;T2,MZHHWM$^SDBN/T]PPDR(OVDXW9S!U^LPU72<]9%BSCAPD/W\MIG(]VY_MY!H_OQX1X(RWGYZ>95Z0.K\JJYC&\UB@L!Z_RVBP*AXFZQ=Q#[PNRS10>S7'@UECRJ!U^KOE*SX[]K_#JQASZ5^*PYI[X8?7X> I^LL[A(RW@FJ#XQ\T@V,CZHTS1W%YR@\Q368Q5)NWGETH#[PIMC,QZUSI]%LSC]T9\,V[KUV:01^<"GPNN]G*PYNDH%^S^ZNT.Onq}YCA[^RSi}{au3267=R8&CTBBQK.T]JHD)RWZ^JX"@\_eqweq:76;80Y=!F_OM\@+SXAEK$YR][AU-MWZbt|h~7=3<=;T2,MZHHWM$^SDBN/T]PPDR(FZUoyo{<3<16>S7'@UECRJ!U^KOE*SX[]K_#C]Pdrvbp959:;1^<"GPNN]G*PYNDH%^S^ZNT.LP[ausi}6?2?<4U1-J[KIXL'_TEAO U^QWEQ)I[Vnxxlz35?01?P6(AVDDSI Z_HNB+PYT\H^$B^Qksucw8385:2_;#DQAO^F-QZOKI&_T_YO[/OQ\`vrf|5=5>?5Z0.K\JJYC&\UB@L!Z_RVBP*HTWmymy27>308Q5)NWGETH#[PIMC,QZUSI]%E_Rj|t`v?=;7b3\:$ER@@_E,V[LJF'\UXXLZ NR]okdb5=2_;#DQAO^F-QZOKI&_T_YO[/RVBP@Yc{}k0=0=5:W3+LYIGVN%YRGCA.W\WQGS'Z^JXHQksucw8486n2_;#DQAO^F-QZOKI&_T_YO[/UFL[kc|8i0Y=!F_OM\@+SXAEK$YR][AU-V[DTJ9k1^<"GPNN]G*PYNDH%^S^ZNT.W\GW443\:$ER@@_E,V[LJF'\UXXLZ U^FJVQ_XNMIN>>5Z0.K\JJYC&\UB@L!Z_RVBP*SXL@X_URHKPD01?P6(AVDDSI Z_HNB+PYT\H^$YRJFRU[\HAE6k2_;#DQAO^F-QZOKI&_T_YO[/T]GWI423\:$ER@@_E,V[LJF'\UXXLZ U^FPH4)RWJFNM_<;;T2,MZHHWM$^SDBN/T]PPDR(]VNX@<!Z_EMVP73<]9%BSCAPD/W\MIG(]VY_MY!Z_EQO5*SXLF__<?;4U1-J[KIXL'_TEAO U^QWEQ)RWMYG="[PDNWW567<]9%BSCAPD/W\MIG(]VY_MY!Z_EQO5*SXOLDTHHBNYZ3^*PYAL;?0Y=!F_OM\@+SXAEK$YR][AU-V[AUK9&_T^KJ]E378Q5)NWGETH#[PIMC,QZUSI]%^SI]C1.W\PCBUM;30Y=!F_OM\@+SXAEK$YR][AU-V[AUK9&nbbRbntbjf`74<]9%BSCAPD/W\MIG(]VY_MY!Z_EQO5*oDD[8>7X> I^LL[A(RW@FJ#XQ\T@V,QZBTD8%bHD@30?06?P6(AVDDSI Z_HNB+PYT\H^$YRJ\L0-j@LH;978j7X> I^LL[A(RW@FJ#XQ\T@V,QZBTD8%bHB[[_enz8585i2_;#DQAO^F-QZOKI&_T_YO[/T]GWI7(aME^XRjcy=3=5a=R8&CTBBQK.T]JHD)RWZ^JX"[PDRN15a=R8&CTBBQK.T]JHD)RWZ^JX"[PDRN05f=R8&CTBBQK.T]JHD)RWZ^JX"[PDRP2g>S7'@UECRJ!U^KOE*SX[]K_#XQJCS3g?P6(AVDDSI Z_HNB+PYT\H^$YRHZLM1b?P6(AVDDSI Z_HNB+PYT\H^$YRCZX.W\GVYJ]Q%B=#[PMTZ1+HkrpVE:=>?<e:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH989:S^Y?3`9V4*OXFFUO"XQFL@-V[VRF\&_TAXV U^AP[HS_'@;%YRCZX3-Nip~XG8;<=>k4U1-J[KIXL'_TEAO U^QWEQ)RWD_S#XQLS^OV\*O6&\UFYU< Mlw{[J76?8UX[==n;T2,MZHHWM$^SDBN/T]PPDR(]VG^T"[PCR]NQ])N9'_TAXV=/Lov|ZI691?8m6[?/H]MKZB)]VCGM"[PSUCW+PYJ]Q%^SN]PMTZ,M4(RWD_S>"Cbuy]L5761;01^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO0027d=R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<<<92c8Q5)NWGETH#[PIMC,QZUSI]%^S@[W/T]@WZKRP&C:"XQBUY0,IhsWF;9:==n;T2,MZHHWM$^SDBN/T]PPDR(]VG^T"[PCR]NQ])N9'_TAXV=/Lov|ZI6:088m6[?/H]MKZB)]VCGM"[PSUCW+PYJ]Q%^SN]PMTZ,M4(RWD_S>"Cbuy]L5654;h1^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO01646g<]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?<891b?P6(AVDDSI Z_HNB+PYT\H^$YRCZX.W\GVYJ]Q%B=#[PMTZ1+HkrpVE:8=;<a:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH9=>8?l5Z0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K421<:k0Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N36405>3\:$ER@@_E,V[LJF'\UXXLZ U^OV\*SXKZUFYU!F1/W\IP^5'Dg~tRA>521b?P6(AVDDSI Z_HNB+PYT\H^$YRCZX.W\GVYJ]Q%B=#[PMTZ1+HkrpVE:9>><a:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH9<>;?l5Z0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K432::k0Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N361=5f3\:$ER@@_E,V[LJF'\UXXLZ U^OV\*SXKZUFYU!F1/W\IP^5'Dg~tRA>59;0=>S7'@UECRJ!U^KOE*SX[]K_#XQBUY-V[FUXE\R$E< Z_LW[6*Kj}qUD=;:;2:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH9?=?S^Y?_RU37`=R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<884^QT56c<]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?981]PS55b3\:$ER@@_E,V[LJF'\UXXLZ U^OV\*SXKZUFYU!F1/W\IP^5'Dg~tRA>692\WR74i2_;#DQAO^F-QZOKI&_T_YO[/T]NQ])RWJYTAXV I0,V[HS_:&GfyuQ@16247==R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<6<9:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH90::o6[?/H]MKZB)]VCGM"[PSUCW+PYI[E9;7X> I^LL[A(RW@FJ#XQ\T@V,QZTB[L^TIIIJ/H]K6I(RWME^X?l4U1-J[KIXL'_TEAO U^QWEQ)RW[OXIYQJDFG,QZBH]]:9n6[?/H]MKZB)]VCGM"[PSUCW+PYUMZO_SHJHE.W\@JSS9;i0Y=!F_OM\@+SXAEK$YR][AU-V[WCTM]UNHJK iEMVP969:j1^<"GPNN]G*PYNDH%^S^ZNT.W\V@UB\VOOKH!fDNWW8486n2_;#DQAO^F-QZOKI&_T_YO[/T]QMVOIO;:0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\JGO>?5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_O@JPn0d8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNTD22b>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@VF571<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&IB0<0=7:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,GL:56;=0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"MF<2<13>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(K@6?2?94U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.AJ8085?2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$OD29>358Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*EN4>49;6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ CH>;:71<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&IB040=6:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,@969:?1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#I2>>348Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*B;:78=7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!K<2<12>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(L5>5>;5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/E>6:70<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&N7:3<9;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-G8285>2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$H161279V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+A:>6:80Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"IT0\,DjM(RWD_SOT<k;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-D_5[)]VLO^H<l;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-D_5[)]VF^X?k4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX4X(RWQEYOT==;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-D_4[)OgB%YRCZXB[1`>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR;V"XQIDSG1g>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR;V"XQCUU0f?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S8W%YRV@RB[06>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR8V"J`G.T]NQ]E^:m1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU=]/W\BATB:j1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU=]/W\HPR5m2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV<R.T][KWE^;;1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU<]/EmL+SXE\RHU?j4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX7X(RWONYI?m4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX7X(RWE__>h5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY0Y+SXPFXHU><4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX0X(@fA$^S@[WCX0g?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S=W%YRHKRD0`?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S=W%YRBZT3g8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\<T$^SUA]CX11?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S<W%KcF!U^OV\F_5l2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV;R.T]E@WC5k2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV;R.T]OQQ4b3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW8S!U^ZLVF_4:2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV8R.FlK*PYJ]QIR>i5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY5Y+SXNMXN>n5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY5Y+SXD\^9i6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ4^*PY_G[IR??5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY4Y+Ai@'_TAXVLY3f8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\?T$^SKJ]E3a8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\?T$^SA[[2d9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]0U'_TTB\LY208Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\0T$LbE Z_LW[G\4c3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW5S!U^DGV@4d3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW5S!U^NVP7c<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP4P Z_YMQG\4c3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW4S!U^DGV@4d3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW4S!U^NVP7c<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP5P Z_YMQG\413\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%X0=0=6:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,W979:?1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#^2=>348Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*U;;78=7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!\<5<12>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR([5?5>;5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/R>5:70<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&Y7;3<9;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-P8=85>2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$_1711b9V4*OXFFUO"XQFL@-V[VRF\&_TXIA=0:W3+LYIGVN%YRGCA.W\WQGS'\U_^DIHES3e?P6(AVDDSI Z_HNB+PYT\H^$e^ZNT=2=65=R8&CTBBQK.T]JHD)RWZ^JX"g\T@V?5586n2_;#DQAO^F-QZOKI&_T_YO[/hQWEQ:668l0Y=!F_OM\@+SXAEK$YR][AU-jWQGS4;4:j6[?/H]MKZB)]VCGM"[PSUCW+lUSI]682<h4U1-J[KIXL'_TEAO U^QWEQ)n[]K_090>f:W3+LYIGVN%YRGCA.W\WQGS'`Y_MY2:>0d8Q5)NWGETH#[PIMC,QZUSI]%b_YO[<7<2b>S7'@UECRJ!U^KOE*SX[]K_#d][AU>4:4`<]9%BSCAPD/W\MIG(]VY_MY!fSUCW8=86n2_;#DQAO^F-QZOKI&_T_YO[/hQWEQ:>6;80Y=!F_OM\@+SXAEK$YR][AU-jWQGSKDNTOH<;;T2,MZHHWM$^SDBN/T]PPDR(aZ^JXNCK_BG\j75<]9%BSCAPD/W\MIG(]VY_MY!fSUCW[FHS4949?6[?/H]MKZB)]VCGM"[PSUCW+lUSI]UHBY2>>318Q5)NWGETH#[PIMC,QZUSI]%b_YO[_BLW8785;2_;#DQAO^F-QZOKI&_T_YO[/hQWEQYDF]682?=4U1-J[KIXL'_TEAO U^QWEQ)n[]K_SN@[<5<17>S7'@UECRJ!U^KOE*SX[]K_#d][AU]@JQ:26;90Y=!F_OM\@+SXAEK$YR][AU-jWQGSWJD_0;0=3:W3+LYIGVN%YRGCA.W\WQGS'`Y_MYQLNU>4:75<]9%BSCAPD/W\MIG(]VY_MY!fSUCW[FHS4149?6[?/H]MKZB)]VCGM"[PSUCW+lUSI]UHBY26>348Q5)NWGETH#[PIMC,QZRUAN%MSCAPTBO@*PYAL[997X> I^LL[A(RW@FJ#XQ[RHE,QZRD'@UXXB\NGD]RQDJ)]VIJ\RL<4:W3+LYIGVN%YRGCA.W\PWO@'\U_O"GPSUMQEBCXY\KG"XQLAQ]GH\1b3\:$ER@@_E,V[LJF'\U_^DI U^V@+LYT\FXJKHQ^U@N-QZUSG[KLIR_ZAM-J[VTK\VDNS< F_OOV[4YSGV>%YRZLL.K\JHSXMX;%YRgKOTV,MZ_B[E__:#[PSSN@53C102_;#DQAO^F-QZOKI&_TX_GH/T]WG*OX[]EYMJKPQTCO*PYT\FXJKHQ^U@N,MZUUD]UEIR?!I^LNQZ7X\FU?"XQ[CM-J[JSSZLM%YRJ@UU7f?P6(AVDDSI Z_HNB+PYSZ@M$YRZL/H]PPJTFOLUZYLB!U^QWKWG@MV[^MA!F_RPOPZHBW8$BSCCZ_0]WKZ2)]V^H@"gKOTV6e>S7'@UECRJ!U^KOE*SX\[CL#XQ[C.K\WQIUINOT]XOC.T]PPJTFOLUZYLB I^QQHQYIMV;%ER@BU^3\PJY3&\U_^DI^439V4*OXFFUO"XQFL@-V[QTNO&_TXN!F_RVLVDABWX_J@#[PSUMQEBCXY\KG#dZ]IFEFV2g<]9%BSCAPD/W\MIG(]V^YEJ!Z_UA,MZRTMXUEI\<!U^V@[@WRI]CDB"GPSSNW[KCX9'CTB@[P1^VL[1(RW]IG#DQAMT]FU4(RW`NDYY!F_XGPHPR1&\UX^AM>6D47?P6(AVDDSI Z_HNB+PYSZ@M$YRZL/H]WW@WXFL[9"XQ[C^GRQDRNGG%BS^\CT^LF[4(NWGG^S<Q[O^6-QZRDD&CTCXZ]EF,V[AIR\<k0Y=!F_OM\@+SXAEK$YRZ]IF-V[QE(AV^XI\QAEP0-QZRDWL[^MYG@N.K\WWJSWGOT=#GPNLW\5ZRHW=$^SYMC/hFLQQ313\:$ER@@_E,V[LJF'\U_^DI U^V@+LYS[L[TBH_=.T]WGZCV]H^BCC!F_RPOPZHBW8$BSCCZ_0]WKZ2)]V^YEJ_<e:W3+LYIGVN%YRGCA.W\PWO@'\U_O"GPTRGR[KCV:'_TXNQJQTCWMJH(a]XBKJK]259V4*OXFFUO"XQFL@-V[QTNO&_TXN!fC@RWQWC502_;#DQAO^F-QZOKI&_TX_GH/T]WG*oDNNUOMYO30?63?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"GPMB]ZAV(RWDI$HB[[_gnbc37<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/H]NGZ_B['_TAN!F_RPOPZHBW8$BSIAZT^doebYTZEI::#[PDNWW[cjfo<n0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+LYJKVSN_#[PMB-J[VTK\VDNS< F_LAMPZciWZXGO<8!U^O@JQYbf<l0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+LYJKVSN_#[PMB-J[VTK\VDNS< F_LAMPZtt|VYY@N?9.T]NGKRXzz~?56[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)NWDITUH]!U^O@+LYTZE^TBHQ>.T]AVN6312_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-J[HEXQLY%YRCL/H]PVIRXFLU:"XQMRJ37f>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!F_LA\]@U)]VGH#DQ\RMV\J@Y6&\UFOCZ D478Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#DQBC^[FW+SXEJ%BS^\CT^LF[4(RWDIEX"IT0\,V[CBUM<>0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+LYJKVSN_#[PMB-J[VTK\VDNS< Z_LAMP*A\8T$^SA[[579V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$ERCL_XGP*PYJK&CT__B[_OG\5+SXEJD_#JU?]/W\\JTDQ=h0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+LYJKVSN_#[PMB-J[VTK\VDNS< Z_LAMP*U4j2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-J[HEXQLY%YRCL/LAMP6c<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/H]NGZ_B['_TAN!BCOV\ak253\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.K\IFY^MZ$^S@M MBLW[`wXief8j6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)NWDITUH]!U^O@+HEI\Vxxx>j4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'@UFORWJS/W\IF)RWKX@>>j4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'@UFORWJS/W\IF)RWME^X5k4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'@UFORWJS/W\IF)RWNKEHRCNTBJ,MZETWNKEH#[PCR]DEKBX[[F$ERX9.T]@WZAFFMUX^AQY6.K\QVCXZYGTBH>!U^EBJAYTZEUXIY7<;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&CTANQVER,V[HE(]VMJBIQBAUAK+LYD[VMJBI Z_BQ\CDHCWZXG#DQY6/W\GVY@IGNT__BPV7-J[PUBW[ZFSCK?.T]DEKBX[[FT_HZPMRGW07=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC I^O@[\CT&\UFO"mig^fbpd:66=80Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+LYJKVSN_#[PMB-`bbYci}k7>3:=;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&CTANQVER,V[HE(komThlzn<2<76>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!F_LA\]@U)]VGH#nhh_ecwe929<;1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,MZKDWPOX"XQBC.aecZbf|h6>29<4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'@UFORWJS/W\IF)dnnUomyo36?15?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-GKPRX|dzjo6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W=S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P==S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=<S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=?S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=>S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=9S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=8S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=;S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=:S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=5S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=4S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8kh7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9<P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9=P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9>P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9?P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q98P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q99P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9:P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9;P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q94P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q95P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hi0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9;Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9:Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R99Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R98Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9?Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9>Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9=Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9<Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R93Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R92Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6ij1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=:V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=;V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=8V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=9V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=>V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=?V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=<V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S==V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=2V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=3V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fk2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=9W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=8W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=;W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=:W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\==W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=<W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=?W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=>W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=1W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=0W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gd3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]18T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]19T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1:T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1;T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1<T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1=T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1>T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1?T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]10T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]11T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5de<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^17U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^16U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^15U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^14U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^13U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^12U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^11U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^10U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^1?U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^1>U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ef=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^1Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3b`>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=6Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3b`>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=7Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3b`>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=4Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3b`>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=5Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3b`>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=2Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3bg>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=[)AVCES_OAGD,J[PUBW@D[YYQ]EF]MA5(RWNKEHRJCY0c`?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX3X=X(NW@DT^L@HE/K\QVCXAGZ^XR\JG^LF4+SXOHDOSIBV18:8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y3Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V??]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R;:Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^75U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z30Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V?;]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R;>Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^71U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z34Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V?7]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R;2Q#GPIO]QEKAB&\ULMCJPDM[1===R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^7Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[32^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W??R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S;8V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_75Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[36^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W?;R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S;<V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_71Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[3:^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W?7R.H]JJZTFFNO%YRINNE]GH\4>02_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S;W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X75[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T30_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P??S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\;:W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X71[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T34_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P?;S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\;>W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X7=[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T38_-MZOIW[KEKH Z_FCM@ZBKQ;337X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P?P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]38T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y75X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U;2\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q??P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]3<T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y71X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U;6\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q?;P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]30T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y7=X(NW@DT^L@HE/W\CDHCWMFR>464U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U;]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R?;Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^36U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z71Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V;<]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R??Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^32U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z75Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V;8]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R?3Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^3>U'CTECQ]AOEF*PY@IGNTHAW=999V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z7^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W;>R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S?;V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_34Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[71^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W;:R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S??V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_30Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[75^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W;6R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S?3V"DQFN^PBJBC)]VMJBIQKLX0:<>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_3[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T71_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P;<S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\?;W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X36[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T75_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P;8S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\??W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X32[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T79_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P;4S!I^KM[WGIOL$^SJOAD^FO]7??3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\?T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y;4X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U71\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q3>P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]?;T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y;0X(NW@DT^L@HE/W\CDHCWMFR>464U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U7]/K\MKYUIGMN"XQHAOF\@I_5111^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R3V"DQFN^PBJBC)]VMJBIQKLX0b4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'\UH_RINNE]PVIYQ>&CTY^KPRQO\J@6)]VMJBIQ\RM]PAQg23\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$YRM\_FCM@ZUUDV\=#DQZSD]QTHYIM9$^SJOAD^QQHZUB\VGXIY9i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1>1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?311<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>25;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz597561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i648954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7=9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2>5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=35:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28419091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;9143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86:539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1?1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?321<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>15;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz594561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64;954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7>9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2=5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=05:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28719091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;:143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq869539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1<1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?331<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>05;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz595561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64:954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7?9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2<5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=15:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28619091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;;143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq868539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1=1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?341<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>75;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz592561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64=954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;789070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2;5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=65:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28119091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;<143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86?539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1:1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?351<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>65;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz593561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64<954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;799070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2:5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=75:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28019091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;=143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86>539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?361<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>55;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz590561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64?954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7:9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<295?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=45:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28319091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;>143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86=539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=181819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?371<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>45;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz591561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64>954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7;9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<285?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=55:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28219091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;?143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86<539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=191819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?381<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>;5;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz59>561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i641954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;74908f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<27>6d8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><8<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>3:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18469091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;9843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6:>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1?<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<06=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?508?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:6>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5;<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90<61819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<318<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>2:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18769091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;:843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;69>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1<<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<36=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?608?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:5>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:58<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90?61819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<328<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>1:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18669091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;;843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;68>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1=<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<26=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?708?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:4>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:59<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90>61819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<338<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>0:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18169091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;<843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6?>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1:<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<56=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?008?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:3>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5><25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90961819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<348<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>7:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18069091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;=843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6>>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1;<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<46=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?108?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:2>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5?<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90861819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<358<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>6:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18369091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;>843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6=>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>18<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<76=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?208?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:1>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5<<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90;61819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<368<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>5:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18269091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;?843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6<>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>19<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<66=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?308?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:0>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5=<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90:61819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<378<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>4:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18=69091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;0843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;63>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>16<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<96=3c=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?<;1a3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz69?9<?1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UD^HI!I^[FWZIUMN$^SB\JG268Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#nhh_ecwe969;81^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,`jssW}g{><5Z0.K\JJYC&\UB@L!Z_UPJC*ruanIdbiGa239V4*OXFFUO"XQFL@-V[QTNO&~yejM`neMvp42<]9%BSCAPD/W\MIG(aHXF=55Z0.K\JJYC&\UB@L!fC@RWQWC612_;#DQAO^F-QZOKI&cHM]QKOOG17>S7'@UECRJ!U^KOE*oDIYUEY@Q\ALROAV:76;90Y=!F_OM\@+SXAEK$eNO__OWN[VGJXEOX0<0=3:W3+LYIGVN%YRGCA.k@EUYI]DUXM@^CER>1:75<]9%BSCAPD/W\MIG(aJK[SC[B_RCNTICT4:49?6[?/H]MKZB)]VCGM"gLAQ]MQHYTIDZGI^2;>318Q5)NWGETH#[PIMC,mFGWWG_FS^OBPMGP8085;2_;#DQAO^F-QZOKI&cHM]QAUL]PEHVKMZ6=2?=4U1-J[KIXL'_TEAO iBCS[KSJWZKF\AK\<6<17>S7'@UECRJ!U^KOE*oDIYUEY@Q\ALROAV:?6;90Y=!F_OM\@+SXAEK$eNO__OWN[VGJXEOX040>d:W3+LYIGVN%YRGCA.k@EUYT\H^N0=0>d:W3+LYIGVN%YRGCA.k@EUYT\H^N0<0>9:W3+LYIGVN%YRGCA.kGEQG;;<4:56[?/H]MKZB)]VCGM"gKAUC?738612_;#DQAO^F-QZOKI&cOMYO336<2=>S7'@UECRJ!U^KOE*oCI]K7?50>9:W3+LYIGVN%YRGCA.kGEQG;;04:56[?/H]MKZB)]VCGM"gKAUC?058612_;#DQAO^F-QZOKI&cOMYO340<2=>S7'@UECRJ!U^KOE*oCI]K78?0>9:W3+LYIGVN%YRGCA.kGEQG;<:4:56[?/H]MKZB)]VCGM"gKAUC?<58612_;#DQAO^F-QZOKI&cOMYO380<2=>S7'@UECRJ!U^KOE*oCI]K74?0>9:W3+LYIGVN%YRGCA.kGEQG;0:4:56[?/H]MKZB)]VCGM"gKAUC?<186i2_;#DQAO^F-QZOKI&cOMYOPDNWW5<=R8&CTBBQK.T]JHD)nZLYNX1>1189V4*OXFFUO"XQFL@-jV@UB\5;5=45Z0.K\JJYC&\UB@L!fRDQFP949901^<"GPNN]G*PYNDH%b^H]JT=1=5<=R8&CTBBQK.T]JHD)nZLYNX1:1189V4*OXFFUO"XQFL@-jV@UB\5?5=45Z0.K\JJYC&\UB@L!fRDQFP909901^<"GPNN]G*PYNDH%b^H]JT=5=5d=R8&CTBBQK.T]JHD)n[]K_SIAZT0:8Q5)NWGETH#[PIMC,mQTNONOY=85Z0.K\PT6)OV^\W=S!U^VR53=R8&CTX\>!G^VT_46Z&\U_]<84U1-J[QW7&NU_[V?>]/W\PT713\:$ERZ^0/E\PR]6:T$^SY_>6:W3+LYSY9$LSYYT12_-QZRV9?1^<"GPTP2-CZRPS8>V"XQ[Q048Q5)NW][;"JQ[WZ36Y+SX\X;=7X> I^VR4+AX\^Q::P Z_US22>S7'@U_]= H_UUX52[)]V^Z=;5Z0.K\PT6)OV^\W<6R.T]WU40<]9%BSY_?.F]WS^7>U'_TX\?:;T2,MZRV8'MTXZU>]/W\PT713\:$ERZ^0/E\PR]58T$^SY_>6:W3+LYSY9$LSYYT20_-QZRV9?1^<"GPTP2-CZRPS;8V"XQ[Q048Q5)NW][;"JQ[WZ00Y+SX\X;=7X> I^VR4+AX\^Q98P Z_US22>S7'@U_]= H_UUX60[)]V^Z=;5Z0.K\PT6)OV^\W?8R.T]WU40<]9%BSY_?.F]WS^40U'_TX\?9;T2,MZRV8'MTXZU=8\,V[QW6>2_;#DQ[Q1,D[QQ\:0W%YRZ^149V4*OX\X:%KRZX[3_-QZRV9?1^<"GPTP2-CZRPS::V"XQ[Q048Q5)NW][;"JQ[WZ12Y+SX\X;=7X> I^VR4+AX\^Q8>P Z_US22>S7'@U_]= H_UUX76[)]V^Z=;5Z0.K\PT6)OV^\W>:R.T]WU40<]9%BSY_?.F]WS^52U'_TX\?9;T2,MZRV8'MTXZU<6\,V[QW6>2_;#DQ[Q1,D[QQ\;>W%YRZ^179V4*OX\X:%KRZX[2:^*PYSY8<0Y=!F_US3*BYS_R92Q#[PTP36?P6(AV^Z<#IPTVY0Y+SX\X;=7X> I^VR4+AX\^Q?<P Z_US22>S7'@U_]= H_UUX04[)]V^Z=;5Z0.K\PT6)OV^\W9<R.T]WU40<]9%BSY_?.F]WS^24U'_TX\?9;T2,MZRV8'MTXZU;4\,V[QW6>2_;#DQ[Q1,D[QQ\<<W%YRZ^179V4*OX\X:%KRZX[54^*PYSY8<0Y=!F_US3*BYS_R><Q#[PTP35?P6(AV^Z<#IPTVY7<X(RW][::6[?/H]WU5(@W]]P84S!U^VR50=R8&CTX\>!G^VT_1[)]V^Z=;5Z0.K\PT6)OV^\W8>R.T]WU40<]9%BSY_?.F]WS^36U'_TX\?9;T2,MZRV8'MTXZU:2\,V[QW6>2_;#DQ[Q1,D[QQ\=:W%YRZ^179V4*OX\X:%KRZX[46^*PYSY8<0Y=!F_US3*BYS_R?>Q#[PTP35?P6(AV^Z<#IPTVY62X(RW][::6[?/H]WU5(@W]]P9:S!U^VR53=R8&CTX\>!G^VT_0>Z&\U_]<84U1-J[QW7&NU_[V;6]/W\PT723\:$ERZ^0/E\PR]2U'_TX\?9;T2,MZRV8'MTXZU90\,V[QW6>2_;#DQ[Q1,D[QQ\>8W%YRZ^179V4*OX\X:%KRZX[70^*PYSY8<0Y=!F_US3*BYS_R<8Q#[PTP35?P6(AV^Z<#IPTVY50X(RW][::6[?/H]WU5(@W]]P:8S!U^VR53=R8&CTX\>!G^VT_30Z&\U_]<84U1-J[QW7&NU_[V88]/W\PT713\:$ERZ^0/E\PR]10T$^SY_>6:W3+LYSY9$LSYYT68_-QZRV9<1^<"GPTP2-CZRPS?W%YRZ^179V4*OX\X:%KRZX[62^*PYSY8<0Y=!F_US3*BYS_R=:Q#[PTP35?P6(AV^Z<#IPTVY46X(RW][::6[?/H]WU5(@W]]P;>S!U^VR53=R8&CTX\>!G^VT_22Z&\U_]<84U1-J[QW7&NU_[V9:]/W\PT713\:$ERZ^0/E\PR]0>T$^SY_>6:W3+LYSY9$LSYYT76_-QZRV9?1^<"GPTP2-CZRPS>2V"XQ[Q048Q5)NW][;"JQ[WZ5:Y+SX\X;>7X> I^VR4+AX\^Q<Q#[PTP35?P6(AV^Z<#IPTVY;4X(RW][::6[?/H]WU5(@W]]P4<S!U^VR53=R8&CTX\>!G^VT_=4Z&\U_]<84U1-J[QW7&NU_[V6<]/W\PT713\:$ERZ^0/E\PR]?<T$^SY_>5:W3+LYSY9$LSYYT8\,V[QW6=2_;#DQ[Q1,D[QQ\1T$^SY_j;T2,mQTNOVCE0=0i;T2,mQTNOVCE0<>1f:W3+lRUANUBB1?>>g9V4*oSZ@MTEC2>2?d8Q5)n\[CLSD@312<e?P6(a]XBKRGA<06=b>S7'`^YEJQFN=36:c=R8&c_^DIPIO>22;`<]9%bX_GH_HL?528a3\:$eY\FG^KM84>9n2_;#dZ]IF]JJ97>6l1^<"g[RHE\MK:66o1^<"g[RHE\MK:587l0Y=!fTSKD[LH;:84m7X> iUPJCZOI4;85j6[?/hVQMBYNF5882k5Z0.kWVLAXAG6983h4U1-jPWO@W@D7>80i;T2,mQTNOVCE0?81f:W3+lRUANUBB1<8>g9V4*oSZ@MTEC2=8?d8Q5)n\[CLSD@328<f?P6(a]XBKRGA<3<e?P6(a]XBKRGA<22=b>S7'`^YEJQFN=12:c=R8&c_^DIPIO>06;`<]9%bX_GH_HL?768a3\:$eY\FG^KM8629n2_;#dZ]IF]JJ9526o1^<"g[RHE\MK:4>7l0Y=!fTSKD[LH;;>4m7X> iUPJCZOI4:25j6[?/hVQMBYNF5922h5Z0.kWVLAXAG682k5Z0.kWVLAXAG6?<3h4U1-jPWO@W@D78<0i;T2,mQTNOVCE09<1f:W3+lRUANUBB1:<>g9V4*oSZ@MTEC2;4?d8Q5)n\[CLSD@344<e?P6(a]XBKRGA<54=b>S7'`^YEJQFN=64:c=R8&c_^DIPIO>7<;`<]9%bX_GH_HL?0<8b3\:$eY\FG^KM818a3\:$eY\FG^KM8069n2_;#dZ]IF]JJ9366o1^<"g[RHE\MK:2:7l0Y=!fTSKD[LH;=:4m7X> iUPJCZOI4<>5j6[?/hVQMBYNF5?>2k5Z0.kWVLAXAG6>:3h4U1-jPWO@W@D79:0i;T2,mQTNOVCE0861f:W3+lRUANUBB1;6>d9V4*oSZ@MTEC2:>g9V4*oSZ@MTEC290?d8Q5)n\[CLSD@360<e?P6(a]XBKRGA<70=b>S7'`^YEJQFN=40:c=R8&c_^DIPIO>50;`<]9%bX_GH_HL?208a3\:$eY\FG^KM8309n2_;#dZ]IF]JJ9006o1^<"g[RHE\MK:107l0Y=!fTSKD[LH;>04n7X> iUPJCZOI4?4m7X> iUPJCZOI4>:5j6[?/hVQMBYNF5=:2k5Z0.kWVLAXAG6<>3h4U1-jPWO@W@D7;>0i;T2,mQTNOVCE0::1f:W3+lRUANUBB19:>g9V4*oSZ@MTEC286?d8Q5)n\[CLSD@376<e?P6(a]XBKRGA<6:=b>S7'`^YEJQFN=5::`=R8&c_^DIPIO>4:c=R8&c_^DIPIO>;4;`<]9%bX_GH_HL?<48a3\:$eY\FG^KM8=49n2_;#dZ]IF]JJ9>46o1^<"g[RHE\MK:?<7o0Y=!fTSKD[LH;07o0Y=!fTSKD[LH;17i0Y^K]_WKPMGJB02_XIR\COB48QZKRPH<0YRCZXC48QZKRPJ<0YRCZXE48QZUUDH<0YR]]LC48QZUUDJ<0YR]]LE18RFE>3_CN[RZVPDa8SDTIAGMTCCBV6:UFE969>2]NM1?16:UFE94902]NM1=50?48S@G;;7<0[HL30?48S@D;97<0[HL32?:8S@D;;3:5:6YJB=1=<>QBJ^O7<364WD@TA97902]NNZK32?:8S@DPM59546YJBVG?0;><_LH\I1;18:UFFRC;>7k0[HLXE=594;><_LH\I191b:UQMQCXN@XXXn5XRHVF[HICMVKh7Z\FTD]NKACXJm1\^DZJ_VKGPMYFl2]YEYKPWHFWLZD33Q:R<95W0X36?]6^99?0T=W>159[4\433Q:R?95W0X67?]6^==1S<T8;;Y2Z31=_8P2?7U>V90f8\LJNFQ'SHO.?.0"PPPD'8';+M^MFI49[KWE^>2RXXAGM7:ZPPZAIL>1S_YQYCB`8\ZEHZLUBBKA9;Yfa[Lba3QncS]|fmWgqwlii991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc=4Xrv05>eoayyhc}kPimc\r4Y7;Vk',Ugcioz#GJTB(Noeio{os"25+4602ixSjoad^qqhZp1W{zfS~k{_03;?fuXohdoS~|c_w4\vukX{l~T><64cr]dekbX{{fTz;Q}pl]paqY49?1hRinne]pviYq>VygenkP1058gvY`ignTbPv7]phlebW8::;6m|_fcm`ZuudV|=S~bfcd]2541<kzUlmcjPssn\r3Ytd`inS<<>6:ap[bgilVyy`Rx9_rnjg`Y59?1hRinne]pviYq>VygenkP3048gvY`ignTbPv7]phlebW=;=7n}Pg`lg[vtkW<Tagle^722>etWnkehR}}l^t5[vjnklU==;5ls^ebjaYtzeU}:R}cibg\340<kzUlmcjPssn\r3Ytd`inS5?9;bq\cdhcWzxgS{8Psmk`aZ?c3nkehRmnrs{?4;c<ohdoSno}rx>24;b<ohdoSno}rx>2:a=`ignTol|}y=0=`>affmUhm|v<2<g?bgilVij~w34?f8cdhcWjky~t2:>e9dekbXkhxyu181d:ebjaYdi{xr0:0k;fcm`Zefz{s743j4g`lg[fguzp62255hltg\w`r>3nf~iR}jt0;8cisbWzo>45hltg\w`r4;2cgm?=4imc/gmow{je{iRgca^t2[55Xi%DDBH"AOOG25=c<aek'oegsbmsaZokiV|:S==Pa-y`[}ehWecxx0M`mqmmakrXFhgn1dbn;Ownf`tXGoU_~dihes]Skwrt581FmuQ\epwfjfcXDl|n`~3>;Tqf[WVJ{4~yyh5Jn``oaZRuanmn~RAztqww[Uiu|4lj`~k4S`osh`YHf4Xbd`h;RcnticXLh~jSIkti?2472<Mgki`hQ\tnpbc`YV}hfbjdmnthmm9qtrm2NjxlQ\alg\EvYSz`mli3{rtg8@drfWYeyxRYfduj>4>Ruanmn~R^`ru]TmaroW87396Cntbj\Qkos{V;6=6M`uovfvZQnl}bT=0?4M`v`lZR~xlU:1oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX94lj`~k4Tskdc`tXXfxSZgkti]19==Ji}icSX`ftr]194=Dg|diQXievk[7;Cazki`hj4M`v`lZR~xlU91oo|ib9F|fjrllUM~bcPD`vb[VrhzhmnS?3iamqf?QtnonoyS]a}t^Uj`qnX;420Alzlh^WmmquX;4;0Ob{atdp\Slbs`V96Hd}nbmgg?HgskaU_u}kP3<`bwle<MqigyikPFsmn[AgsiVYcohe^1>bdjtm2^yejijr^RlvqYPam~cS937;LcwgmYRf`~xS93>;BmvjqcuW^coxeQ;=Ekpegjbl2GjxnfPTxrf[1;eizch7Hvlltff[CtheVNjxlQ\tnpbc`Y35okgh5[rhedawYWg{~T[dj{h^7><>Kf|jbTYcg{s^7>5>Eh}g~n~RYfduj\18Bn{hhgii5Bauak[QwmV?6nl}fc:G{giscmVLyc`QKauc\WqiuinoT90hnlrg8Pwo`olxT\b|{_VkgpmY1511Fmymg_TljpvY1581Hcx`{es]TmaroW?7Oe~omldf8Idrd`V^r|hQ9=ccpmf=Bpjf~hhQIrno\@drfWZ~d~lij_7?eeiub3]xbkjk}_QmqpZQnl}bT;064M`v`lZSia}yT;0?4Cnwmp`tX_`ndR92Dhqbficc3DkoeQ[yqg\38df{`i0Iumcueg\BwijWMkmR]{oscdaZ1:nhfxi6Z}ifefvZVhz}U\eizg_9?;?HgskaU^bdz|_9?2?Firf}oySZgkti];9Aotikfnh6Cntbj\P|vbW17im~gl;Dz`hpbbWOxdaRJnt`]PpjtfolU31kocsd9Wvla`m{U[czPWhfwlZ?:02GjxnfPUokwwZ?:92Idyczjr^Uj`qnX14Nbllcee9NeqeoW]s{iR72b`qjg>CkeoiRH}ol]GeqgX[}eymjkP9<dbhvc<\{clkh|PPnpw[Roc|aU:<064M`v`lZSia}yT==3>;BmvjqcuW^coxeQ>0<Fjwddkmm1Fmymg_U{saZ775kkxen5Jxbnv``YAzfgTHlzn_RvlvdabW8:6jlb|e:VqmbabzVZd~yQXievk[47:02GjxnfPUokwwZ76581Hcx`{es]TmaroW8;6Hd}nbmgg?HgskaU_u}kP10?aevod3Lrh`xjj_GpliZBf|hUXxb|ngd]258`fdzo0Xghgdp\TjtsW^coxeQ>2<:8Idrd`V_eey}P13?2?Firf}oySZgkti]268Bn{hhgii5Bauak[QwmV;91oo|ib9F|fjrllUM~bcPD`vb[VrhzhmnS<<2f`npa>Ruanmn~R^`ru]TmaroW89646Cntbj\Qkos{V;81<5LotlwawYPam~cS<=2Dhqbficc3DkoeQ[yqg\56;eizch7Hvlltff[CtheVNjxlQ\tnpbc`Y6;4lj`~k4Tskdc`tXXfxSZgkti]208><Eh~hdR[aiuq\51;63Je~byk}_VkgpmY6<4Nbllcee9NeqeoW]s{iR?;=ccpmf=Bpjf~hhQIrno\@drfWZ~d~lij_06>bdjtm2^yejijr^RlvqYPam~cS<;28:ObpfnX]gcR?:=09@kphsm{U\eizg_07>@lufjeoo7@o{ci]W}ucX9<7im~gl;Dz`hpbbWOxdaRJnt`]PpjtfolU:90hnlrg8Pwo`olxT\b|{_VkgpmY6>420Alzlh^WmmquX9?7:7Naznugq[Roc|aU::0Jfs``oaa=Ji}icSYwe^359ggtaj1Ntnbzdd]EvjkXLh~jS^z`r`ef[40:nhfxi!mPxegumfcaidcgu0xfrug{2)eXkfxnSywe<0/gZkaoVco1<"l_lcikwYqm{ybcc3>1-a\ilhhzV|n~~g`n<0/gZdraenT~hxfshmm95*dWjeyiRcnjnp\r`t:9%iTob|j_lkmkwYqm{79 nQlosg\ilhhzVkg|eoPvdp>=2*dW{kfSywe<3/gZuud8<Txt~j=3.`[pubW`d}Snbd=1.`[pubW{zf1<"l_tqf[qtnoVe~x0>#c^wpaZgskViggd`20-a\qvcXlh~j1="l_tqf[qtno97: nQzsd]wvla659&hSx}j_upjc7;7$jU~hQ{rhe095*dW|ynSy|fg5?3(fYr{lU~di:=1.`[pubW}xbk;3?,b]vw`Ysz`m<1="l_tqf[qtno17; nQzsd]wvla>59&hSx}j_upjc46:8%iTy~kPtskd54;7$jU~hQ{rhe2686+kVxiRz}if3095*dW|ynSy|fg06>4)eX}zoTxgh14?3(fYr{lU~dikauc394*dW|ynSy|fgecwe4;7$jU~hQ{rhegeqg559&hSx}j_upjcagsi:7; nQzsd]wvlaci}k?1="l_tqf[qtnomkm83?,b]vw`Ysz`momyo9=1.`[pubW}xbkio{a6?3(fYr{lU~dikauc;95*dW|ynSy|fgecwe<;7$jU~hQ{rhegeqg684:'oR{|e^vqmbbf|h;:1="l_tqf[qtnomkm<<20-a\qvcX|{clhlzn12?3(fYr{lU~dikauc2086+kVxiRz}iffbpd7259&hSio{a^uj`qn:9%iThlzn_egspm;68;>'oR{|e^ebt86+kV~bah}{alr\p|vb59&hSygbervbiuYpam~c1><#c^vji`usidzThh~{h<726)eX}zoTya}afg\upgk58&hSy}jq^vzt`;7$jUey`Q{sds\gkr:8%iTx~k~_blw5Zqnl}b6=!mPtrgr[fhs8V}bhyf21-a\jpkX|zozS~zntdq>5)eX}zoTxnQbcov>4)eX|jUfoczPwhfwl87+kVosxRmnp^pbp`Yjgmo6<!mPeyv\gdvXx`dTabjj=1.`[ksjWlrSno_qkmw8>+kVosxRmnp^wpaZtbo4;'oR`zm^obpfnX}gc0?#c^vqmb6X`nd06:,b]wvla6W~coxe3>,b]wvla5W~coxe3>,b]wvla4W~coxe3>,b]wvla3W~coxe3>,b]wvla2W~coxe3>,b]wvla1W~coxe3>,b]wvla0W~coxe3>,b]wvla?W~coxe3>,b]wvla>W~coxe3>,b]wvla68V}bhyf21-a\pwo`98U|eizg=0.`[qtno88T{dj{h<3/gZruan;8Szgkti?2(fYsz`m:8Ryfduj>5)eX|{cl=8Qxievk94*dWd:Tx}gk=1.`[h7X|yco1<"l_l0\puoc5;&hS`=Ptqkg96*dWd>Tx}gk=5.`[h3X|yco18"l_l4\puoc5?&hS`9Ptqkg92*dWd2Tx}gk=9.`[h?X|yco14"l_l33[qvnl4;; nQb10]wtlb:98&hS`?=_urj`875$jUf=>Q{phf>56*dWd;?Sy~fd<37(fYj9<U|dj214.`[h6X|pzn1<"l_l3\p|vb59&hS`<Ptxrf95*dWd9Txt~j=1.`[h2X|pzn1="l_l7\p|vb59&hS`8Ptxrf95*dWd=Txt~j=1.`[h>X|pzn1="l_l;\p|vb59&hS`??_u{sa86+kVg:=Rzvpd?3(fYj9;Uu}k20-a\i45X|pzn1="l_l37[qwm4:'oRc>5^vzt`;7$jU~hQbcov394*dW|ynS`mat0?3(fYr{lUfocz==1.`[pubWdiex>3?,b]vw`Yjkg~?1="l_tqf[hei|<7; nQzsd]ngkr159&hSx}j_lamp2;7$jU~hQbcov;95*dW|ynS`mat8?3(fYr{lUfocz>0<2/gZstmVghby?>=1.`[pubWdiex<<20-a\qvcXejd=>3?,b]vw`Yjkg~:80>#c^wpaZkdf};>1="l_lamp5Ypam~c1<"l_lamp4Ypam~c1<"l_lamp7Ypam~c1<"l_lamp6Ypam~c1<"l_lamp1Ypam~c1<"l_lamp0Ypam~c1<"l_lamp3Ypam~c1<"l_lamp2Ypam~c1<"l_lamp=Ypam~c1<"l_lamp<Ypam~c1<"l_lamp46X`nd0?#c^o`jq76W~coxe3>,b]ngkr6:V}bhyf21-a\ifhs9:U|eizg=0.`[hei|8>T{dj{h<3/gZkdf};>Szgkti?2(xe<djfTbPq=2=g>jddVyy`R31?a8hfjX{{fT}1<1b:ov|fXdf6;2o5buyaz[ii;97h0axvly^nl878e3dsotQco=1=f>krpjsT`b2;>b9nq}e~Wzog0=0l;lw{g|Ytme6:2n5buyaz[vck4;4h7`{wcx]pai:4611eknlzimf:?vtkWx6:<364ssn\u97902yy`R32?:8wwjXy59546}}l^s?0;><{{fT}1;18:qqhZw;>720bPq=5=<>uudV{74364ssn\u9?9uIJ{>47i;AB{fd3=N3>1=v]k5;`;1?50<3;8>5k67;173=0|fk286<5ab9691>"e080i;o5rS`g9f=3=;>>1=><7e859711>;2Y8;54mb583>4550l3<6>:8999Pe`<ej=0;6<==8d;4>620i91onl;50;395~Uc=3h397=84;306=c>?39?;584vU1a2?6=93;19=7tSe79f=3=;>>1=><7e859711?>2.i984<789Uf=4=:r84>4>;t1;0?6<u-92?7=7;c`b1?6=?h08484;41yKf1g<,=9:6oo:;[;4>7}4m38o6p*m818a<3=#i<0im;5+d58ae2=n<;n1<7*<94876f=i;0>1<65f43`94?"41<0?>n5a38695>=n<;k1<7*<94876f=i;0>1>65f43;94?"41<0?>n5a38697>=n<;21<7*<94876f=i;0>1865f43494?"41<0?>n5a38691>=n<;?1<7*<94876f=i;0>1:65f43694?"41<0?>n5a38693>=n<;91<7*<94876f=i;0>1465f43094?"41<0?>n5a3869=>=n<;;1<7*<94876f=i;0>1m65f43294?"41<0?>n5a3869f>=n<8l1<7*<94876f=i;0>1o65f40g94?"41<0?>n5a3869`>=n<8n1<7*<94876f=i;0>1i65f40`94?"41<0?>n5a3869b>=n<8k1<7*<94876f=i;0>1==54i53:>5<#;0?18?m4n2;7>47<3`>:47>5$2;6>14d3g9287?=;:k752<72-9297:=c:l0=1<6;21b8<850;&0=0<3:j1e?4:51598m172290/?4;543a8j6?328?07d:>4;29 6?22=8h7c=64;35?>o39:0;6)=65;61g>h41=0:;65f40094?"41<0?>n5a38695==<a=;;6=4+387907e<f:3?6<74;h63b?6=,:3>69<l;o1:0?7f32c?<h4?:%1:1?25k2d8594>b:9j05b=83.8584;2b9m7<2=9j10e9>l:18'7<3=<;i0b>7;:0f8?l27j3:1(>7::50`?k5><3;n76g;0`83>!5>=3>9o6`<9582b>=n<931<7*<94876f=i;0>1>=54i52;>5<#;0?18?m4n2;7>77<3`>;;7>5$2;6>14d3g9287<=;:k740<72-9297:=c:l0=1<5;21b8=:50;&0=0<3:j1e?4:52598m164290/?4;543a8j6?32;?07d:?2;29 6?22=8h7c=64;05?>o3880;6)=65;61g>h41=09;65f41294?"41<0?>n5a38696==<a:lm6=4+387907e<f:3?6?74;h1ea?6=,:3>69<l;o1:0?4f32c8ji4?:%1:1?25k2d8594=b:9j7ce=83.8584;2b9m7<2=:j10e>hn:18'7<3=<;i0b>7;:3f8?l5a13:1(>7::50`?k5><38n76g<f983>!5>=3>9o6`<9581b>=n;o=1<7*<94876f=i;0>1?=54i2d5>5<#;0?18?m4n2;7>67<3`9m97>5$2;6>14d3g9287==;:k0b1<72-9297:=c:l0=1<4;21b?k=50;&0=0<3:j1e?4:53598m6`5290/?4;543a8j6?32:?07d=i1;29 6?22=8h7c=64;15?>o4mo0;6)=65;61g>h41=08;65f3dg94?"41<0?>n5a38697==<a:oo6=4+387907e<f:3?6>74;h1fg?6=,:3>69<l;o1:0?5f32c8io4?:%1:1?25k2d8594<b:9j7`g=83.8584;2b9m7<2=;j10e>k6:18'7<3=<;i0b>7;:2f8?l5b03:1(>7::50`?k5><39n76g<e683>!5>=3>9o6`<9580b>=n;l<1<7*<94876f=i;0>18=54i2g7>5<#;0?18?m4n2;7>17<3`9n?7>5$2;6>14d3g9287:=;:k0a7<72-9297:=c:l0=1<3;21b?h?50;&0=0<3:j1e?4:54598m6c7290/?4;543a8j6?32=?07d=kf;29 6?22=8h7c=64;65?>o4ll0;6)=65;61g>h41=0?;65f3ef94?"41<0?>n5a38690==<a:nh6=4+387907e<f:3?6974;h1gf?6=,:3>69<l;o1:0?2f32c?>k4?:%1:1?25k2d8594;b:9j07c=83.8584;2b9m7<2=<j10e9<8:18'7<3=<;i0b>7;:5f8?l26k3:1(>7::50`?k5><3>n76g;1083>!5>=3>9o6`<9587b>=n<9<1<7*<94876f=i;0>19=54i2da>5<#;0?18?m4n2;7>07<3`9m<7>5$2;6>14d3g9287;=;:k0a0<72-9297:=c:l0=1<2;21b?io50;&0=0<3:j1e?4:55598/fe=83.8584lb:l0=1<732!hm7>5$2;6>fd<f:3?6<54+b;94?"41<0hn6`<9581?>-d03:1(>7::b`8j6?32:10'n950;&0=0<dj2d8594;;:)`2?6=,:3>6nl4n2;7>0=<#j>1<7*<948`f>h41=0=76%l3;29 6?22jh0b>7;:698/f4=83.8584lb:l0=1<?32!h=7>5$2;6>fd<f:3?6454+b294?"41<0hn6`<958b?>-en3:1(>7::b`8j6?32k10'ok50;&0=0<dj2d8594l;:)a`?6=,:3>6nl4n2;7>a=<#ki1<7*<948`f>h41=0n76%mb;29 6?22jh0b>7;:g98/g?=83.8584lb:l0=1<6821 n54?:%1:1?ee3g9287?>;:)a3?6=,:3>6nl4n2;7>44<3"h=6=4+3879gg=i;0>1=>54+c794?"41<0hn6`<95820>=,j=0;6)=65;aa?k5><3;>76%m3;29 6?22jh0b>7;:048?.d5290/?4;5cc9m7<2=9>10'o?50;&0=0<dj2d8594>8:9(f5<72-9297mm;o1:0?7>32!o?7>5$2;6>fd<f:3?6<o4;*f1>5<#;0?1oo5a38695g=<#m;1<7*<948`f>h41=0:o65$d183>!5>=3ii7c=64;3g?>-dn3:1(>7::b`8j6?328o07&mj:18'7<3=kk1e?4:51g98/f3=83.8584lb:l0=1<5921 nl4?:%1:1?ee3g9287<=;:)bb?6=,:3>6nl4n2;7>75<3`k<6=44+bf94?"41<0hn6`<95814>=ej>l1<7?50;2x 1562k??7El8d:Ja0d=h;081<75rbc5f>5<6290;w):<1;0`3>Ne?m1Cn9o4o0g6>5<<uk2m;7>59;294~"3;808n45Gb6f8Lg2f3-8n<7<4i5294?=n<80;66g;2;29?l242900el:50;9je2<722co:7>5;n1:3?6=3f9247>5;|`;bf<7200;6=u+42397g?<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg32900el950;9j`3<722e85:4?::m0==<722wi4k;50;094?6|,=9:6>9n;I`4`>Ne<h1/>h>5119j6fg=831d?4?50;9~f3?d290?6=4?{%605?50k2Bi;i5Gb5c8 7c720k0e?mn:188m7ee2900e?ml:188k6?62900qo6id;290?6=8r.??<4>d89Kf2b<@k>j7)<j0;38m<>=831bh;4?::k0=d<722e85:4?::a<c>=83>1<7>t$512>4b>3Ah<h6Fm4`9'6`6=92c247>5;hf5>5<<a:3j6=44o2;4>5<<uk2mm7>54;294~"3;80:h45Gb6f8Lg2f3-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66sm8gd94?2=83:p(9=>:0f:?Md0l2Bi8l5+2d295>o>03:17dj9:188m6?f2900c>78:188yg>a>3:187>50z&774<6l01Cn:j4Hc6b?!4b83;0e4650;9j`3<722c85l4?::m0=2<722wim:=50;794?6|,=9:6<j7;I`4`>Ne<h1/>h>5119j==<722cj87>5;hf5>5<<a:3=6=44o2;4>5<<uk2m87>54;294~"3;80:h45Gb6f8Lg2f3-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66smag094?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdfn80;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qooi0;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fdca290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wimhk50;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`baf<72=0;6=u+42395a1<@k=o7El;a:&1a5<682c247>5;hf5>5<<a:3=6=44o2;4>5<<ukknn7>54;294~"3;80:h:5Gb6f8Lg2f3-8n<7??;h;;>5<<am<1<75f38494?=h;0=1<75rb`gb>5<3290;w):<1;3g3>Ne?m1Cn9o4$3g3>46<a021<75fd783>>o41?0;66a<9683>>{eil31<7:50;2x 15628n<7El8d:Ja0d=#:l:1==5f9983>>oc>3:17d=66;29?j5>?3:17plne983>1<729q/8>?51e58Lg1c3Ah?m6*=e1824>o>03:17dj9:188m6?12900c>78:188yggb?3:187>50z&774<6l>1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?4850;9l7<1=831vnlk9:187>5<7s->8=7?k7:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0=3<722e85:4?::ae`3=83>1<7>t$512>4b03Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`92:7>5;n1:3?6=3thji94?:583>5}#<:;1=i94Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2;5>5<<g:3<6=44}ccf7?6=<3:1<v*;3082`2=Oj>n0Do:n;%0f4?773`336=44ie494?=n;0<1<75`38594?=zjho:6=4;:183!2493;o;6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<9783>>i41>0;66smad294?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdflo0;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qooke;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fdbc290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wimim50;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`b`g<72=0;6=u+42395a1<@k=o7El;a:&1a5<682c247>5;hf5>5<<a:3=6=44o2;4>5<<ukkom7>54;294~"3;80:h:5Gb6f8Lg2f3-8n<7??;h;;>5<<am<1<75f38494?=h;0=1<75rb`f:>5<3290;w):<1;3g3>Ne?m1Cn9o4$3g3>46<a021<75fd783>>o41?0;66a<9683>>{eim21<7:50;2x 15628n<7El8d:Ja0d=#:l:1==5f9983>>oc>3:17d=66;29?j5>?3:17plnd783>1<729q/8>?51e58Lg1c3Ah?m6*=e1824>o>03:17dj9:188m6?12900c>78:188yggc=3:187>50z&774<6l>1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?4850;9l7<1=831vnlj;:187>5<7s->8=7?k7:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0=3<722e85:4?::aea5=83>1<7>t$512>4b03Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`92:7>5;n1:3?6=3thjh?4?:583>5}#<:;1=i94Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2;5>5<<g:3<6=44}ccg5?6=<3:1<v*;3082`2=Oj>n0Do:n;%0f4?773`336=44ie494?=n;0<1<75`38594?=zjhn;6=4;:183!2493;o;6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<9783>>i41>0;66smabd94?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdfkl0;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qoold;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fdee290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wimno50;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`bg<<72=0;6=u+42395a1<@k=o7El;a:&1a5<682c247>5;hf5>5<<a:3=6=44o2;4>5<<ukkh47>54;294~"3;80:h:5Gb6f8Lg2f3-8n<7??;h;;>5<<am<1<75f38494?=h;0=1<75rb`a4>5<3290;w):<1;3g3>Ne?m1Cn9o4$3g3>46<a021<75fd783>>o41?0;66a<9683>>{eij<1<7:50;2x 15628n<7El8d:Ja0d=#:l:1==5f9983>>oc>3:17d=66;29?j5>?3:17plnc483>1<729q/8>?51e58Lg1c3Ah?m6*=e1824>o>03:17dj9:188m6?12900c>78:188yggd<3:187>50z&774<6l>1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?4850;9l7<1=831vnlm<:187>5<7s->8=7?k7:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0=3<722e85:4?::aef4=83>1<7>t$512>4b03Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`92:7>5;n1:3?6=3thjo=4?:583>5}#<:;1=i94Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2;5>5<<g:3<6=44}ccab?6=<3:1<v*;3082`2=Oj>n0Do:n;%0f4?773`336=44ie494?=n;0<1<75`38594?=zjhhn6=4;:183!2493;o;6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<9783>>i41>0;66smacf94?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdfjj0;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qoomb;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fddf290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wimo750;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`bf=<72=0;6=u+42395a1<@k=o7El;a:&1a5<682c247>5;hf5>5<<a:3=6=44o2;4>5<<ukki;7>54;294~"3;80:h:5Gb6f8Lg2f3-8n<7??;h;;>5<<am<1<75f38494?=h;0=1<75rb``6>5<3290;w):<1;3g3>Ne?m1Cn9o4$3g3>46<a021<75fd783>>o41?0;66a<9683>>{eik>1<7:50;2x 15628n<7El8d:Ja0d=#:l:1==5f9983>>oc>3:17d=66;29?j5>?3:17plnb283>1<729q/8>?51e58Lg1c3Ah?m6*=e1824>o>03:17dj9:188m6?12900c>78:188ygge:3:187>50z&774<6l>1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?4850;9l7<1=831vnll>:187>5<7s->8=7?k7:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0=3<722e85:4?::aeg6=83>1<7>t$512>4b03Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`92:7>5;n1:3?6=3thjmk4?:583>5}#<:;1=i94Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2;5>5<<g:3<6=44}ccba?6=<3:1<v*;3082`2=Oj>n0Do:n;%0f4?773`336=44ie494?=n;0<1<75`38594?=zjhko6=4;:183!2493;o;6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<9783>>i41>0;66sma`a94?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdfih0;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qoon9;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fdg?290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wiml950;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`be3<72=0;6=u+42395a1<@k=o7El;a:&1a5<682c247>5;hf5>5<<a:3=6=44o2;4>5<<ukkj97>54;294~"3;80:h:5Gb6f8Lg2f3-8n<7??;h;;>5<<am<1<75f38494?=h;0=1<75rb`c7>5<3290;w):<1;3g3>Ne?m1Cn9o4$3g3>46<a021<75fd783>>o41?0;66a<9683>>{eih91<7:50;2x 15628n<7El8d:Ja0d=#:l:1==5f9983>>oc>3:17d=66;29?j5>?3:17plna383>1<729q/8>?51e58Lg1c3Ah?m6*=e1824>o>03:17dj9:188m6?12900c>78:188yggf93:187>50z&774<6l>1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?4850;9l7<1=831vnlh;:187>5<7s->8=7?k7:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0=3<722e85:4?::aec5=83>1<7>t$512>4b03Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`92:7>5;n1:3?6=3thjii4?:583>5}#<:;1=i94Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2;5>5<<g:3<6=44}ccf6?6=<3:1<v*;3082`2=Oj>n0Do:n;%0f4?773`336=44ie494?=n;0<1<75`38594?=zjhn<6=4;:183!2493;o;6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<9783>>i41>0;66smaba94?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdfk80;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qoom6;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fdge290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wiml>50;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`7`3<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9j;:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3l;0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5f3>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?oh4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1ef290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;c983>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=i=6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`7g1<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9m=:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3k90;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5`f>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?nn4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1df290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;b983>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=h?6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`7f7<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9l?:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3il0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5c`>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?ml4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1g?290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;a783>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=k?6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`7e7<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn97j:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd31j0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5;b>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?554?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1?1290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;9583>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=396=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`7=5<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn96j:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd30j0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5:;>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?4;4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1>3290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;8383>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=2;6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`73`<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn99l:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3?h0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb55;>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?;;4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f115290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;7183>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=<n6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`72f<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn98n:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3>10;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb545>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?:94?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f105290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;6183>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=?h6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`71d<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9;7:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3=?0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb577>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?9?4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f137290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;4d83>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=>h6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`70d<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9:9:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3<=0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb561>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?8=4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f15b290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;3b83>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=9j6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`77=<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9=9:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3;=0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5fb>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?h54?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1ed290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;b783>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=k;6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`7<d<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn99;:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3=l0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb56;>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th???4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1b029086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`7`0<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb5f0>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;d083>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9mi:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?oo4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=i26=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3k>0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f1e229086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`7g6<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb5a2>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;bg83>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9lk:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?no4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=h26=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3j<0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f1d429086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`7f4<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb5ce>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;ae83>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9om:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?m44?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=k<6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3i<0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f1g429086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`7=c<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb5;g>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;9c83>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn976:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?5:4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=3>6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd31:0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f1?629086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`7<c<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb5:g>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;8883>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn968:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?484?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=286=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3080;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f11a29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`73a<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb55a>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;7883>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn998:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?;>4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj==:6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3>o0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f10c29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`72g<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb54:>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;6683>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn98::180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?:>4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=<:6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3=m0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f13e29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`71<<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb574>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;5483>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9;<:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?9<4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=>m6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3<m0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f12e29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`702<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb566>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;4283>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9:>:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th??k4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=9o6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3;k0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f15>29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`772<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb516>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;dc83>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9j6:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?oi4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=h<6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3i80;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f1>e29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`730<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb57e>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;4883>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9=<:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th2;?4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0=o6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>010;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<?4290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:=`<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8c:>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl6b583>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4li:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2o84?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0i=6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>?:0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<13290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:30<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb855>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl67683>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn497:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2;44?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0=j6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>?k0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<1d290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:3`<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb85e>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl68183>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn46>:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th24?4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0286=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>0=0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<>2290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:<3<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8:4>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl68883>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn46n:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th24o4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj02h6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>0m0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<>b290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:<c<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8;3>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl69083>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn47=:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2594?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj03>6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>1?0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<?0290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:==<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8;:>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl69`83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn47m:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th25n4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj03o6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>1o0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<g7290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:e4<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8c1>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl6a283>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4o;:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2m84?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0k=6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>i>0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<g?290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:ed<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8ca>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl6ab83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4ok:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2mh4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0km6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>j90;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<d6290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:f7<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8`0>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl6b483>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4l9:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2n:4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0h36=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>j00;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<df290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:fg<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8``>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl6be83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4lj:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2o=4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0i:6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>k;0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<e4290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:g1<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb83g>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl62983>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4=<:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2?h4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0>26=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>==0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<3a290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:2d<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb853>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl67083>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4?j:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2=k4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj08;6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>:80;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<45290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:66<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb807>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl62483>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4<9:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2>:4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0826=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>:h0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<4e290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:6f<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb80g>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl62d83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4<i:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2?=4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj09:6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>;;0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<53290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:70<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb815>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl63683>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4=7:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2?44?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj09j6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>;k0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<5d290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:7a<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb81e>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl64183>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4:>:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th28?4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0>86=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd><=0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<22290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:03<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb864>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl64983>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4:n:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th28o4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0>h6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd><m0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<2b290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:0c<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb873>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl65083>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4;=:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th29>4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0?>6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>=?0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<30290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:1=<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb87:>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl65`83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4;m:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th29n4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0?o6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>=l0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<07290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:24<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb841>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl66283>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn48;:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2:84?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0<=6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>>>0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<0?290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:2<<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb84a>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl66b83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn48k:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2:h4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0<m6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>k>0;6h=5c;d;Md3i2.??<4m869Y=2<6s;:1q)l;b;604>o5>m0;6)=65;05g>h41=0;76g=6c83>!5>=38=o6`<9582?>o5>h0;6)=65;05g>h41=0976g=6883>!5>=38=o6`<9580?>o5>10;6)=65;05g>h41=0?76g=6683>!5>=38=o6`<9586?>o5>?0;6)=65;05g>h41=0=76g=6483>!5>=38=o6`<9584?>o5>=0;6)=65;05g>h41=0376g=6283>!5>=38=o6`<958:?>o5>80;6)=65;05g>h41=0j76g=6183>!5>=38=o6`<958a?>o5=o0;6)=65;05g>h41=0h76g=5d83>!5>=38=o6`<958g?>o5=m0;6)=65;05g>h41=0n76g=5b83>!5>=38=o6`<958e?>o5=k0;6)=65;05g>h41=0:<65f24c94?"41<09:n5a386954=<a;?26=4+387963e<f:3?6<<4;h06<?6=,:3>6?8l;o1:0?7432c9984?:%1:1?41k2d8594>4:9j602=83.8584=6b9m7<2=9<10e?;<:18'7<3=:?i0b>7;:048?l42:3:1(>7::34`?k5><3;<76g=5083>!5>=38=o6`<9582<>=n:<:1<7*<94812f=i;0>1=454i36e>5<#;0?1>;m4n2;7>4g<3`8?i7>5$2;6>70d3g9287?m;:k10a<72-9297<9c:l0=1<6k21b>9m50;&0=0<5>j1e?4:51e98m72f290/?4;527a8j6?328o07d<;9;29 6?22;<h7c=64;3e?>o5<10;6)=65;05g>h41=09<65f25594?"41<09:n5a386964=<a;>=6=4+387963e<f:3?6?<4;h071?6=,:3>6?8l;o1:0?4432c9894?:%1:1?41k2d8594=4:9j615=83.8584=6b9m7<2=:<10e?:=:18'7<3=:?i0b>7;:348?l4393:1(>7::34`?k5><38<76g=3g83>!5>=38=o6`<9581<>=n::o1<7*<94812f=i;0>1>454i31g>5<#;0?1>;m4n2;7>7g<3`88o7>5$2;6>70d3g9287<m;:k17g<72-9297<9c:l0=1<5k21b>>o50;&0=0<5>j1e?4:52e98m75>290/?4;527a8j6?32;o07d<<8;29 6?22;<h7c=64;0e?>o5;>0;6)=65;05g>h41=08<65f22494?"41<09:n5a386974=<a;9?6=4+387963e<f:3?6><4;h007?6=,:3>6?8l;o1:0?5432c9??4?:%1:1?41k2d8594<4:9j667=83.8584=6b9m7<2=;<10e?=?:18'7<3=:?i0b>7;:248?l45n3:1(>7::34`?k5><39<76g=2d83>!5>=38=o6`<9580<>=n:;n1<7*<94812f=i;0>1?454i30`>5<#;0?1>;m4n2;7>6g<3`89n7>5$2;6>70d3g9287=m;:k16<<72-9297<9c:l0=1<4k21b>?650;&0=0<5>j1e?4:53e98m740290/?4;527a8j6?32:o07d<=6;29 6?22;<h7c=64;1e?>o5:<0;6)=65;05g>h41=0?<65f23694?"41<09:n5a386904=<a;886=4+387963e<f:3?69<4;h016?6=,:3>6?8l;o1:0?2432c9><4?:%1:1?41k2d8594;4:9j676=83.8584=6b9m7<2=<<10e??j:18'7<3=:?i0b>7;:548?l46l3:1(>7::34`?k5><3><76g=1b83>!5>=38=o6`<9587<>=n:8h1<7*<94812f=i;0>18454i33b>5<#;0?1>;m4n2;7>1g<3`8:57>5$2;6>70d3g9287:m;:k15=<72-9297<9c:l0=1<3k21b><950;&0=0<5>j1e?4:54e98m771290/?4;527a8j6?32=o07d<>5;29 6?22;<h7c=64;6e?>o59:0;6)=65;05g>h41=0><65f20094?"41<09:n5a386914=<a;;:6=4+387963e<f:3?68<4;h024?6=,:3>6?8l;o1:0?3432c9<k4?:%1:1?41k2d8594:4:9j65c=83.8584=6b9m7<2==<10e?>k:18'7<3=:?i0b>7;:448?l47k3:1(>7::34`?k5><3?<76g=0c83>!5>=38=o6`<9586<>=n:9k1<7*<94812f=i;0>19454i32;>5<#;0?1>;m4n2;7>0g<3`8;;7>5$2;6>70d3g9287;m;:k143<72-9297<9c:l0=1<2k21b>=;50;&0=0<5>j1e?4:55e98m763290/?4;527a8j6?32<o07d<?3;29 6?22;<h7c=64;7e?>o58;0;6)=65;05g>h41=0=<65f21394?"41<09:n5a386924=<a;:;6=4+387963e<f:3?6;<4;h3eb?6=,:3>6?8l;o1:0?0432c:ji4?:%1:1?41k2d859494:9j5ce=83.8584=6b9m7<2=><10e<hm:18'7<3=:?i0b>7;:748?l7ai3:1(>7::34`?k5><3<<76g>f883>!5>=38=o6`<9585<>=n9o21<7*<94812f=i;0>1:454i0d4>5<#;0?1>;m4n2;7>3g<3`;m:7>5$2;6>70d3g92878m;:k2b0<72-9297<9c:l0=1<1k21b=k:50;&0=0<5>j1e?4:56e98m4`5290/?4;527a8j6?32?o07d?i1;29 6?22;<h7c=64;4e?>o6n90;6)=65;05g>h41=0<<65f1dd94?"41<09:n5a386934=<a8on6=4+387963e<f:3?6:<4;h3f`?6=,:3>6?8l;o1:0?1432c:in4?:%1:1?41k2d859484:9j5`d=83.8584=6b9m7<2=?<10e<kn:18'7<3=:?i0b>7;:648?l7b13:1(>7::34`?k5><3=<76g=c283>!5>=38=o6`<9584<>=n:j81<7*<94812f=i;0>1;454i3a2>5<#;0?1>;m4n2;7>2g<3`8h<7>5$2;6>70d3g92879m;:k1fc<72-9297<9c:l0=1<0k21b>ok50;&0=0<5>j1e?4:57e98m7dc290/?4;527a8j6?32>o07d<mc;29 6?22;<h7c=64;5e?>o5jk0;6)=65;05g>h41=03<65f2cc94?"41<09:n5a3869<4=<a;h36=4+387963e<f:3?65<4;h0a3?6=,:3>6?8l;o1:0?>432c9n;4?:%1:1?41k2d859474:9j6g3=83.8584=6b9m7<2=0<10e?l;:18'7<3=:?i0b>7;:948?l4e;3:1(>7::34`?k5><32<76g=b383>!5>=38=o6`<958;<>=n:k;1<7*<94812f=i;0>14454i3`3>5<#;0?1>;m4n2;7>=g<3`8jj7>5$2;6>70d3g92876m;:k1ea<72-9297<9c:l0=1<?k21b>lm50;&0=0<5>j1e?4:58e98m7ge290/?4;527a8j6?321o07d<na;29 6?22;<h7c=64;:e?>o5i00;6)=65;05g>h41=02<65f2`:94?"41<09:n5a3869=4=<a;k<6=4+387963e<f:3?64<4;h0b2?6=,:3>6?8l;o1:0??432c9m84?:%1:1?41k2d859464:9j6d2=83.8584=6b9m7<2=1<10e?o=:18'7<3=:?i0b>7;:848?l4f93:1(>7::34`?k5><33<76g=a183>!5>=38=o6`<958:<>=n:0l1<7*<94812f=i;0>15454i3;f>5<#;0?1>;m4n2;7><g<3`82h7>5$2;6>70d3g92877m;:k1=f<72-9297<9c:l0=1<>k21b>4l50;&0=0<5>j1e?4:59e98m7?f290/?4;527a8j6?320o07d<69;29 6?22;<h7c=64;;e?>o51>0;6)=65;05g>h41=0j<65f28494?"41<09:n5a3869e4=<a;3>6=4+387963e<f:3?6l<4;h0:0?6=,:3>6?8l;o1:0?g432c95>4?:%1:1?41k2d8594n4:9j6<4=83.8584=6b9m7<2=i<10e?7>:18'7<3=:?i0b>7;:`48?l4>83:1(>7::34`?k5><3k<76g=8g83>!5>=38=o6`<958b<>=n:1o1<7*<94812f=i;0>1m454i3:`>5<#;0?1>;m4n2;7>dg<3`83n7>5$2;6>70d3g9287om;:k1<d<72-9297<9c:l0=1<fk21b>5750;&0=0<5>j1e?4:5ae98m7>?290/?4;527a8j6?32ho07d<77;29 6?22;<h7c=64;ce?>o50?0;6)=65;05g>h41=0i<65f29794?"41<09:n5a3869f4=<a;2?6=4+387963e<f:3?6o<4;h0;7?6=,:3>6?8l;o1:0?d432c94<4?:%1:1?41k2d8594m4:9j6=6=83.8584=6b9m7<2=j<10e?9i:18'7<3=:?i0b>7;:c48?l40m3:1(>7::34`?k5><3h<76g=7e83>!5>=38=o6`<958a<>=n:>i1<7*<94812f=i;0>1n454i35a>5<#;0?1>;m4n2;7>gg<3`8<m7>5$2;6>70d3g9287lm;:k13<<72-9297<9c:l0=1<ek21b>:650;&0=0<5>j1e?4:5be98m711290/?4;527a8j6?32ko07d<85;29 6?22;<h7c=64;`e?>o5?=0;6)=65;05g>h41=0h<65f26194?"41<09:n5a3869g4=<a;=96=4+387963e<f:3?6n<4;h045?6=,:3>6?8l;o1:0?e432c9;=4?:%1:1?41k2d8594l4:9j63`=83.8584=6b9m7<2=k<10e?8j:18'7<3=:?i0b>7;:b48?l41:3:1(>7::34`?k5><3i<76g=5783>!5>=38=o6`<958`<>=n:=h1<7*<94812f=i;0>1o454i363>5<#;0?1>;m4n2;7>fg<3`8897>5$2;6>70d3g9287mm;:k16d<72-9297<9c:l0=1<dk21b><h50;&0=0<5>j1e?4:5ce98m773290/?4;527a8j6?32jo07d<?9;29 6?22;<h7c=64;ae?>o6nl0;6)=65;05g>h41=0o<65f1g194?"41<09:n5a3869`4=<a;i>6=4+387963e<f:3?6i<4;h0a=?6=,:3>6?8l;o1:0?b432c9mh4?:%1:1?41k2d8594k4:9j6d5=83.8584=6b9m7<2=l<10e?77:18'7<3=:?i0b>7;:e48?l4?l3:1(>7::34`?k5><3n<76g=8383>!5>=38=o6`<958g<>=n:>=1<7*<94812f=i;0>1h454i374>5<#;0?1>;m4n2;7>ag<3`;n47>5$2;6>70d3g9287jm;:kbg?6=3`9j47>5;h1g5?6=3`9o<7>5;h1g6?6=3f9o?7>5;n0`2?6=3kh<j7>51;294~"3;80i995Gb6f8Lg2f3f92>7>5;|`02=<728i157<:{I`7e>"3;80i4l5U96824c=u-8h477l8:k0g3<72-9297=l5:l0=1<732c8o94?:%1:1?5d=2d8594>;:k0g6<72-9297=l5:l0=1<532c8o?4?:%1:1?5d=2d8594<;:k0g4<72-9297=l5:l0=1<332c8o=4?:%1:1?5d=2d8594:;:k0fc<72-9297=l5:l0=1<132c8nh4?:%1:1?5d=2d85948;:k0fa<72-9297=l5:l0=1<?32c8nn4?:%1:1?5d=2d85946;:k0gc<72-9297=l5:l0=1<f32c8oh4?:%1:1?5d=2d8594m;:k0ga<72-9297=l5:l0=1<d32c8on4?:%1:1?5d=2d8594k;:k0gg<72-9297=l5:l0=1<b32c8ol4?:%1:1?5d=2d8594i;:k0g<<72-9297=l5:l0=1<6821b?n650;&0=0<4k<1e?4:51098m6e0290/?4;53b78j6?328807d=mb;29 6?22:i>7c=64;30?>ofk3:17d=n8;29?l7b>3:17d=k1;29?l5c83:17d=k2;29?j5c;3:17b<l6;29?gd0m3:1=7>50z&774<5k>1Cn:j4Hc6b?j7b=3:17plm4b83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xde=:0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g0a3-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg35290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a2c=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a14<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c4e?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc73>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm4e83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xde<o0;694?:1y'067=;1:0Do9k;I`7e>"4i00i:k5fa783>>oc?3:17d=m0;29?j50?3:17plm4d83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xu6m?0;6?uQ1d489g2d2h<0q~<l6;296~X5k?16n9h53658yv5?>3:19v3m7d82a0=:j=i1h:52b5f9`2=:j=l1h:52b5g9`2=z{:hi6=4={_1af>;e=90?86s|3ca94?4|V:hh70l:2;67?xu4jm0;6?uQ3cf89g352=?0q~=me;296~X4jl16n8<5479~w6da2909wS=mf:?a17<3?2wx?n>50;0xZ6e734h>>7:6;|q0g4<72;qU?n?4=c70>12<uz9h>7>52z\0g7=:j<91885rs2a0>5<5sW9h?63m52872>{t;j>1<7<t^2a7?8d2;3><7p}<c783>7}Y;j<01o;<:5;8yv5d?3:1>vP<c69>f06=<<1v>m7:181[5d027i9=4;6:p7f?=838pR>m6;<`64?203ty8ol4?:3y]7fg<5k?;6974}r1`f?6=:rT8oo52b43901=z{:ih6=4={_1`g>;e=80?96s|3bf94?4|V:io70l:1;65?xu4kl0;6?uQ3bg89g362==0q~=lf;296~X4ko16n8?5489~w6b7290>wS=k0:?a16<f<27i9?4n4:?a14<f<27i9=4n4:p7a7=83?pR>j>;<`67?g034h>>7o8;<`65?g034h><7o8;|q0`7<72;qU?i<4=c70>a0<uz9o?7>52z\0`6=:j<:1?474}r`b<?6=:r7i9<4<989>f06=l?1voo6:1818d2:392563m508g2>{tjhk1<7<t=c70>6?>34h>>7j9;|qaeg<72;q6n9m536589g2c2h<0q~lnc;296~;e<m08;:52b5g9e3=z{kko6=4={<`7b?g134h?i7=87:pfg6=838p1o:l:2`3?8d28392;6s|bc394?4|5k?:6>78;<`7`?5e82wxno<50;0x9g352:3<70l;e;1a4>{tjk91<7<t=c70>6?034h?j7=m0:~f60f290:o77524yKf1g<,=9:6o6j;[;4>4}6m3w/>n659b:8m6e1290/?4;53b78j6?32910e>m;:18'7<3=;j?0b>7;:098m6e4290/?4;53b78j6?32;10e>m=:18'7<3=;j?0b>7;:298m6e6290/?4;53b78j6?32=10e>m?:18'7<3=;j?0b>7;:498m6da290/?4;53b78j6?32?10e>lj:18'7<3=;j?0b>7;:698m6dc290/?4;53b78j6?32110e>ll:18'7<3=;j?0b>7;:898m6ea290/?4;53b78j6?32h10e>mj:18'7<3=;j?0b>7;:c98m6ec290/?4;53b78j6?32j10e>ml:18'7<3=;j?0b>7;:e98m6ee290/?4;53b78j6?32l10e>mn:18'7<3=;j?0b>7;:g98m6e>290/?4;53b78j6?328:07d=l8;29 6?22:i>7c=64;32?>o4k>0;6)=65;1`1>h41=0:>65f3c`94?"41<08o85a386956=<ahi1<75f3`:94?=n9l<1<75f3e394?=n;m:1<75f3e094?=h;m91<75`2b494?=ej>o1<7?50;2x 1562;i<7El8d:Ja0d=h9l?1<75rbc6`>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g173`k=6=44ie594?=n;k:1<75`36594?=zjk?86=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&0e<<e?91/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xde=;0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g173-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg36290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a35=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a15<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c53?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc6g>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g173`k=6=44ie594?=n;k:1<75`36594?=zjk>m6=4;:183!249393<6Fm7e9Kf1g<,:k26o9?;hc5>5<<am=1<75f3c294?=h;>=1<75rbc6f>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g173`k=6=44ie594?=n;k:1<75`36594?=z{8o=6=4={_3f2>;e<j0j:6s|2b494?4|V;i=70l;f;143>{t;1<1<7;t=c5f>4c234h?o7j8;<`7`?b034h?j7j8;<`7a?b03ty8no4?:3y]7gd<5k?;69:4}r1ag?6=:rT8nn52b40901=z{:ho6=4={_1a`>;e=;0?96s|3cg94?4|V:hn70l:2;65?xu4jo0;6?uQ3cd89g352==0q~=l0;296~X4k916n8<5489~w6e62909wS=l1:?a16<3<2wx?n<50;0xZ6e534h>?7::;|q0g6<72;qU?n=4=c70>10<uz9h87>52z\0g1=:j<918:5rs2a5>5<5sW9h:63m5287=>{t;j=1<7<t^2a4?8d283>>7p}<c983>7}Y;j201o;?:548yv5d13:1>vP<c89>f06=<>1v>mn:181[5di27i9=4;9:p7fd=838pR>mm;<`65?233ty8on4?:3y]7fe<5k?:69;4}r1``?6=:rT8oi52b43903=z{:in6=4={_1`a>;e=80?;6s|3bd94?4|V:im70l:1;6:?xu4l90;68uQ3e289g342h>01o;=:`689g362h>01o;?:`68yv5c93:19vP<d09>f05=i>16n8<5a69>f07=i>16n8>5a69~w6b52909wS=k2:?a16<c>2wx?i=50;0xZ6b434h><7=69:pfd>=838p1o;>:2;:?8d283n=7p}ma883>7}:j<81?474=c72>a0<uzhjm7>52z?a16<41016n8<5d79~wgge2909w0l;c;143>;e<m0j:6s|b`a94?4|5k>o6>98;<`7a?g13tyimi4?:3y>f1`=i?16n9k53658yvde83:1>v3m4b80f5=:j<:1?494}r`a5?6=:r7i9<4<969>f1b=;k:0q~lm2;296~;e=;085:52b5g97g6<uzhi?7>52z?a16<41>16n9h53c28yxd4>k0;6<m59;06Md3i2.??<4m8g9Y=2<6s8o1q)<l8;;`<>o4k?0;6)=65;1`1>h41=0;76g<c583>!5>=39h96`<9582?>o4k:0;6)=65;1`1>h41=0976g<c383>!5>=39h96`<9580?>o4k80;6)=65;1`1>h41=0?76g<c183>!5>=39h96`<9586?>o4jo0;6)=65;1`1>h41=0=76g<bd83>!5>=39h96`<9584?>o4jm0;6)=65;1`1>h41=0376g<bb83>!5>=39h96`<958:?>o4ko0;6)=65;1`1>h41=0j76g<cd83>!5>=39h96`<958a?>o4km0;6)=65;1`1>h41=0h76g<cb83>!5>=39h96`<958g?>o4kk0;6)=65;1`1>h41=0n76g<c`83>!5>=39h96`<958e?>o4k00;6)=65;1`1>h41=0:<65f3b:94?"41<08o85a386954=<a:i<6=4+38797f3<f:3?6<<4;h1af?6=,:3>6>m:;o1:0?7432cjo7>5;h1b<?6=3`;n:7>5;h1g5?6=3`9o<7>5;h1g6?6=3f9o?7>5;n0`2?6=3kh<i7>51;294~"3;809o:5Gb6f8Lg2f3f;n97>5;|`a0f<72=0;6=u+42397=6<@k=o7El;a:&0e<<e?:1bm;4?::kg3?6=3`9i<7>5;n143?6=3thi9>4?:`83>5}#<:;1?oo4Hc5g?Md3i2P2;7?t368~ 6g>2k=87)<j0;68md1=831bh;4?::kb0?6=3f92;7>5;n1:=?6=3`>26=4+38790==i;0>1<65f4683>!5>=3>37c=64;38?l21290/?4;5499m7<2=:21b884?:%1:1?2?3g9287=4;h67>5<#;0?1855a38690>=zjk?96=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&0e<<e?:1/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xde=80;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g143-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg37290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a36=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a0a<72=0;6=u+42397=6<@k=o7El;a:&0e<<e?:1bm;4?::kg3?6=3`9i<7>5;n143?6=3thi8k4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m729je3<722co;7>5;h1a4?6=3f9<;7>5;|`a0`<72=0;6=u+42397=6<@k=o7El;a:&0e<<e?:1bm;4?::kg3?6=3`9i<7>5;n143?6=3ty:i;4?:3y]5`0<5k>h6l84}r0`2?6=:rT9o;52b5d9721<uz93:7>55z?a3`<6m<16n9m5d69>f1b=l>16n9h5d69>f1c=l>1v>lm:181[5ej27i9=4;4:p7ge=838pR>ll;<`66?233ty8ni4?:3y]7gb<5k?969;4}r1aa?6=:rT8nh52b40903=z{:hm6=4={_1ab>;e=;0?;6s|3b294?4|V:i;70l:2;6:?xu4k80;6?uQ3b389g342=>0q~=l2;296~X4k;16n8=5449~w6e42909wS=l3:?a16<3>2wx?n:50;0xZ6e334h>?7:8;|q0g3<72;qU?n84=c70>1?<uz9h;7>52z\0g2=:j<:1885rs2a;>5<5sW9h463m51872>{t;j31<7<t^2a:?8d283><7p}<c`83>7}Y;jk01o;?:5;8yv5dj3:1>vP<cc9>f07=<=1v>ml:181[5dk27i9<4;5:p7fb=838pR>mk;<`65?213ty8oh4?:3y]7fc<5k?:6994}r1`b?6=:rT8ok52b4390<=z{:n;6=4:{_1g4>;e=:0j863m538b0>;e=80j863m518b0>{t;m;1<7;t^2f2?8d2;3k<70l:2;c4?8d293k<70l:0;c4?xu4l;0;6?uQ3e089g342m<0q~=k3;296~X4l:16n8>538;8yvdf03:1>v3m5080=<=:j<:1h;5rscc:>5<5s4h>>7=69:?a14<c>2wxnlo50;0x9g342:3270l:2;f5?xueik0;6?u2b5a9721<5k>o6l84}r`bg?6=:r7i8i4<769>f1c=i?1vook:1818d3n3k=70l;e;143>{tjk:1<7<t=c6`>6d734h><7=67:pfg7=838p1o;>:2;4?8d3l39i<6s|bc094?4|5k?96>78;<`7a?5e82wxno=50;0x9g342:3<70l;f;1a4>{zj:<h6=4>c;;960}Oj=k0(9=>:c;3?_?028q:i7s+2b:9=f><a:i=6=4+38797f3<f:3?6=54i2a7>5<#;0?1?n;4n2;7>4=<a:i86=4+38797f3<f:3?6?54i2a1>5<#;0?1?n;4n2;7>6=<a:i:6=4+38797f3<f:3?6954i2a3>5<#;0?1?n;4n2;7>0=<a:hm6=4+38797f3<f:3?6;54i2`f>5<#;0?1?n;4n2;7>2=<a:ho6=4+38797f3<f:3?6554i2``>5<#;0?1?n;4n2;7><=<a:im6=4+38797f3<f:3?6l54i2af>5<#;0?1?n;4n2;7>g=<a:io6=4+38797f3<f:3?6n54i2a`>5<#;0?1?n;4n2;7>a=<a:ii6=4+38797f3<f:3?6h54i2ab>5<#;0?1?n;4n2;7>c=<a:i26=4+38797f3<f:3?6<>4;h1`<?6=,:3>6>m:;o1:0?7632c8o:4?:%1:1?5d=2d8594>2:9j7gd=83.8584<c49m7<2=9:10elm50;9j7d>=831b=h850;9j7a7=831b?i>50;9j7a4=831d?i=50;9l6f0=831in:k50;394?6|,=9:6?m8;I`4`>Ne<h1d=h;50;9~fg2d290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k=?7do9:188ma1=831b?o>50;9l721=831vno;<:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"4i00i;95+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3thi9?4?:`83>5}#<:;1?oo4Hc5g?Md3i2P2;7?t368~ 6g>2k=?7)<j0;68md1=831bh;4?::kb0?6=3f92;7>5;n1:=?6=3`>26=4+38790==i;0>1<65f4683>!5>=3>37c=64;38?l21290/?4;5499m7<2=:21b884?:%1:1?2?3g9287=4;h67>5<#;0?1855a38690>=zjk?:6=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&0e<<e?=1/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xde=90;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g133-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg2c290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k=?7do9:188ma1=831b?o>50;9l721=831vno:i:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c57?lg12900ei950;9j7g6=831d?:950;9~fg2b290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k=?7do9:188ma1=831b?o>50;9l721=831v<k9:181[7b>27i8n4n6:p6f0=838pR?m9;<`7b?50?2wx?5850;7x9g1b28o>70l;c;f4?8d3l3n<70l;f;f4?8d3m3n<7p}<bc83>7}Y;kh01o;?:568yv5ek3:1>vP<bb9>f04=<=1v>lk:181[5el27i9?4;5:p7gc=838pR>lj;<`66?213ty8nk4?:3y]7g`<5k?96994}r1`4?6=:rT8o=52b4090<=z{:i:6=4={_1`5>;e=:0?86s|3b094?4|V:i970l:3;66?xu4k:0;6?uQ3b189g342=<0q~=l4;296~X4k=16n8=5469~w6e12909wS=l6:?a16<312wx?n950;0xZ6e034h><7::;|q0g=<72;qU?n64=c73>10<uz9h57>52z\0g<=:j<:18:5rs2ab>5<5sW9hm63m5187=>{t;jh1<7<t^2aa?8d293>?7p}<cb83>7}Y;ji01o;>:578yv5dl3:1>vP<ce9>f07=<?1v>mj:181[5dm27i9<4;7:p7f`=838pR>mi;<`65?2>3ty8h=4?:4y]7a6<5k?86l:4=c71>d2<5k?:6l:4=c73>d2<uz9o=7>55z\0`4=:j<91m:52b409e2=:j<;1m:52b429e2=z{:n96=4={_1g6>;e=:0o:6s|3e194?4|V:n870l:0;1:=>{tjh21<7<t=c72>6?>34h><7j9;|qae<<72;q6n8<538;89g362m<0q~lna;296~;e=:085452b409`3=z{kki6=4={<`7g?50?27i8i4n6:pfde=838p1o:k:254?8d3m3k=7p}mae83>7}:j=l1m;52b5g9721<uzhi<7>52z?a0f<4j916n8>53858yvde93:1>v3m5080=2=:j=n1?o>4}r`a6?6=:r7i9?4<969>f1c=;k:0q~lm3;296~;e=:085:52b5d97g6<uth8:i4?:0a9=?42sAh?m6*;308a=4=]1>0:w<k5}%0`<??d02c8o;4?:%1:1?5d=2d8594?;:k0g1<72-9297=l5:l0=1<632c8o>4?:%1:1?5d=2d8594=;:k0g7<72-9297=l5:l0=1<432c8o<4?:%1:1?5d=2d8594;;:k0g5<72-9297=l5:l0=1<232c8nk4?:%1:1?5d=2d85949;:k0f`<72-9297=l5:l0=1<032c8ni4?:%1:1?5d=2d85947;:k0ff<72-9297=l5:l0=1<>32c8ok4?:%1:1?5d=2d8594n;:k0g`<72-9297=l5:l0=1<e32c8oi4?:%1:1?5d=2d8594l;:k0gf<72-9297=l5:l0=1<c32c8oo4?:%1:1?5d=2d8594j;:k0gd<72-9297=l5:l0=1<a32c8o44?:%1:1?5d=2d8594>0:9j7f>=83.8584<c49m7<2=9810e>m8:18'7<3=;j?0b>7;:008?l5ej3:1(>7::2a6?k5><3;876gnc;29?l5f03:17d?j6;29?l5c93:17d=k0;29?l5c:3:17b=k3;29?j4d>3:17ol8e;295?6=8r.??<4=c69Kf2b<@k>j7b?j5;29?xde<j0;694?:1y'067=;1:0Do9k;I`7e>"4i00i;85fa783>>oc?3:17d=m0;29?j50?3:17plm5283>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o9:;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno;=:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"4i00i;85+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3thi9<4?:`83>5}#<:;1?oo4Hc5g?Md3i2P2;7?t368~ 6g>2k=>7)<j0;68md1=831bh;4?::kb0?6=3f92;7>5;n1:=?6=3`>26=4+38790==i;0>1<65f4683>!5>=3>37c=64;38?l21290/?4;5499m7<2=:21b884?:%1:1?2?3g9287=4;h67>5<#;0?1855a38690>=zjk?;6=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&0e<<e?<1/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xde<m0;694?:1y'067=;1:0Do9k;I`7e>"4i00i;85fa783>>oc?3:17d=m0;29?j50?3:17plm4g83>1<729q/8>?53928Lg1c3Ah?m6*<a88a30=ni?0;66gk7;29?l5e83:17b=87;29?xde<l0;694?:1y'067=;1:0Do9k;I`7e>"4i00i;85fa783>>oc?3:17d=m0;29?j50?3:17p}>e783>7}Y9l<01o:l:`48yv4d>3:1>vP=c79>f1`=;>=0q~=76;291~;e?l0:i852b5a9`2=:j=n1h:52b5d9`2=:j=o1h:5rs2`a>5<5sW9in63m51870>{t;ki1<7<t^2``?8d2:3>?7p}<be83>7}Y;kn01o;=:578yv5em3:1>vP<bd9>f04=<?1v>li:181[5en27i9?4;7:p7f6=838pR>m?;<`66?2>3ty8o<4?:3y]7f7<5k?869:4}r1`6?6=:rT8o?52b41900=z{:i86=4={_1`7>;e=:0?:6s|3b694?4|V:i?70l:3;64?xu4k?0;6?uQ3b489g342=30q~=l7;296~X4k>16n8>5449~w6e?2909wS=l8:?a15<3>2wx?n750;0xZ6e>34h><7:8;|q0gd<72;qU?no4=c73>1?<uz9hn7>52z\0gg=:j<;1895rs2a`>5<5sW9ho63m50871>{t;jn1<7<t^2ag?8d293>=7p}<cd83>7}Y;jo01o;>:558yv5dn3:1>vP<cg9>f07=<01v>j?:186[5c827i9>4n4:?a17<f<27i9<4n4:?a15<f<2wx?i?50;7xZ6b634h>?7o8;<`66?g034h>=7o8;<`64?g03ty8h?4?:3y]7a4<5k?86i84}r1g7?6=:rT8h>52b4297<?<uzhj47>52z?a14<41016n8>5d79~wgg>2909w0l:2;1:=>;e=80o:6s|b`c94?4|5k?86>76;<`66?b13tyimo4?:3y>f1e=;>=01o:k:`48yvdfk3:1>v3m4e8032=:j=o1m;5rsccg>5<5s4h?j7o9;<`7a?50?2wxno>50;0x9g2d2:h;70l:0;1:3>{tjk;1<7<t=c72>6?034h?h7=m0:pfg4=838p1o;=:2;4?8d3m39i<6s|bc194?4|5k?86>78;<`7b?5e82wvn>8j:182g??=:<qCn9o4$512>g?53S3<6<u>e;'6f>=1j20e>m9:18'7<3=;j?0b>7;:198m6e3290/?4;53b78j6?32810e>m<:18'7<3=;j?0b>7;:398m6e5290/?4;53b78j6?32:10e>m>:18'7<3=;j?0b>7;:598m6e7290/?4;53b78j6?32<10e>li:18'7<3=;j?0b>7;:798m6db290/?4;53b78j6?32>10e>lk:18'7<3=;j?0b>7;:998m6dd290/?4;53b78j6?32010e>mi:18'7<3=;j?0b>7;:`98m6eb290/?4;53b78j6?32k10e>mk:18'7<3=;j?0b>7;:b98m6ed290/?4;53b78j6?32m10e>mm:18'7<3=;j?0b>7;:d98m6ef290/?4;53b78j6?32o10e>m6:18'7<3=;j?0b>7;:028?l5d03:1(>7::2a6?k5><3;:76g<c683>!5>=39h96`<95826>=n;kh1<7*<9480g0=i;0>1=>54i`a94?=n;h21<75f1d494?=n;m;1<75f3e294?=n;m81<75`3e194?=h:j<1<75mb6g94?7=83:p(9=>:3a4?Md0l2Bi8l5`1d794?=zjk>h6=4;:183!249393<6Fm7e9Kf1g<,:k26o99;hc5>5<<am=1<75f3c294?=h;>=1<75rbc70>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m779'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm5383>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o99;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno;>:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"4i00i;;5+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3thi9=4?:`83>5}#<:;1?oo4Hc5g?Md3i2P2;7?t368~ 6g>2k==7)<j0;68md1=831bh;4?::kb0?6=3f92;7>5;n1:=?6=3`>26=4+38790==i;0>1<65f4683>!5>=3>37c=64;38?l21290/?4;5499m7<2=:21b884?:%1:1?2?3g9287=4;h67>5<#;0?1855a38690>=zjk>o6=4;:183!249393<6Fm7e9Kf1g<,:k26o99;hc5>5<<am=1<75f3c294?=h;>=1<75rbc6e>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g113`k=6=44ie594?=n;k:1<75`36594?=zjk>n6=4;:183!249393<6Fm7e9Kf1g<,:k26o99;hc5>5<<am=1<75f3c294?=h;>=1<75rs0g5>5<5sW;n:63m4b8b2>{t:j<1<7<t^3a5?8d3n39<;6s|39494?3|5k=n6<k:;<`7g?b034h?h7j8;<`7b?b034h?i7j8;|q0fg<72;qU?ol4=c73>12<uz9io7>52z\0ff=:j<81895rs2`g>5<5sW9ih63m53871>{t;ko1<7<t^2`f?8d2:3>=7p}<bg83>7}Y;kl01o;=:558yv5d83:1>vP<c19>f04=<01v>m>:181[5d927i9>4;4:p7f4=838pR>m=;<`67?223ty8o>4?:3y]7f5<5k?86984}r1`0?6=:rT8o952b41902=z{:i=6=4={_1`2>;e=:0?56s|3b594?4|V:i<70l:0;66?xu4k10;6?uQ3b:89g372=<0q~=l9;296~X4k016n8>5469~w6ef2909wS=la:?a15<312wx?nl50;0xZ6ee34h>=7:;;|q0gf<72;qU?nm4=c72>13<uz9hh7>52z\0ga=:j<;18;5rs2af>5<5sW9hi63m50873>{t;jl1<7<t^2ae?8d293>27p}<d183>0}Y;m:01o;<:`689g352h>01o;>:`689g372h>0q~=k1;291~X4l816n8=5a69>f04=i>16n8?5a69>f06=i>1v>j=:181[5c:27i9>4k6:p7a5=838pR>j<;<`64?5>12wxnl650;0x9g362:3270l:0;f5?xuei00;6?u2b4097<?<5k?:6i84}r`be?6=:r7i9>4<989>f04=l?1voom:1818d3k39<;63m4e8b2>{tjhi1<7<t=c6g>61034h?i7o9;|qaea<72;q6n9h5a79>f1c=;>=0q~lm0;296~;e<j08n=52b4297<1<uzhi=7>52z?a14<41>16n9j53c28yvde:3:1>v3m5380=2=:j=o1?o>4}r`a7?6=:r7i9>4<969>f1`=;k:0qpl<6g83>4e=138>wEl;a:&774<e1:1Q5:4>{0g9y!4d033h46g<c783>!5>=39h96`<9583?>o4k=0;6)=65;1`1>h41=0:76g<c283>!5>=39h96`<9581?>o4k;0;6)=65;1`1>h41=0876g<c083>!5>=39h96`<9587?>o4k90;6)=65;1`1>h41=0>76g<bg83>!5>=39h96`<9585?>o4jl0;6)=65;1`1>h41=0<76g<be83>!5>=39h96`<958;?>o4jj0;6)=65;1`1>h41=0276g<cg83>!5>=39h96`<958b?>o4kl0;6)=65;1`1>h41=0i76g<ce83>!5>=39h96`<958`?>o4kj0;6)=65;1`1>h41=0o76g<cc83>!5>=39h96`<958f?>o4kh0;6)=65;1`1>h41=0m76g<c883>!5>=39h96`<95824>=n;j21<7*<9480g0=i;0>1=<54i2a4>5<#;0?1?n;4n2;7>44<3`9in7>5$2;6>6e23g9287?<;:kbg?6=3`9j47>5;h3f2?6=3`9o=7>5;h1g4?6=3`9o>7>5;n1g7?6=3f8h:7>5;c`4a?6=93:1<v*;3081g2=Oj>n0Do:n;n3f1?6=3thi8n4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m769je3<722co;7>5;h1a4?6=3f9<;7>5;|`a16<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c54?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc71>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m769'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm5083>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o98;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno;?:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"4i00i;:5+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3thi8i4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m769je3<722co;7>5;h1a4?6=3f9<;7>5;|`a0c<72=0;6=u+42397=6<@k=o7El;a:&0e<<e?>1bm;4?::kg3?6=3`9i<7>5;n143?6=3thi8h4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m769je3<722co;7>5;h1a4?6=3f9<;7>5;|q2a3<72;qU=h84=c6`>d0<uz8h:7>52z\1g3=:j=l1?:94}r1;2?6==r7i;h4>e49>f1e=l>16n9j5d69>f1`=l>16n9k5d69~w6de2909wS=mb:?a15<3<2wx?om50;0xZ6dd34h>>7:;;|q0fa<72;qU?oj4=c71>13<uz9ii7>52z\0f`=:j<818;5rs2`e>5<5sW9ij63m53873>{t;j:1<7<t^2a3?8d2:3>27p}<c083>7}Y;j;01o;<:568yv5d:3:1>vP<c39>f05=<<1v>m<:181[5d;27i9>4;6:p7f2=838pR>m;;<`67?203ty8o;4?:3y]7f0<5k?86974}r1`3?6=:rT8o:52b42900=z{:i36=4={_1`<>;e=90?:6s|3b;94?4|V:i270l:0;64?xu4kh0;6?uQ3bc89g372=30q~=lb;296~X4kk16n8?5459~w6ed2909wS=lc:?a14<3=2wx?nj50;0xZ6ec34h>=7:9;|q0g`<72;qU?nk4=c72>11<uz9hj7>52z\0gc=:j<;1845rs2f3>5<2sW9o<63m528b0>;e=;0j863m508b0>;e=90j86s|3e394?3|V:n:70l:3;c4?8d2:3k<70l:1;c4?8d283k<7p}<d383>7}Y;m801o;<:e48yv5c;3:1>vP<d29>f06=;030q~ln8;296~;e=8085452b429`3=z{kk26=4={<`66?5>127i9<4k6:pfdg=838p1o;<:2;:?8d2:3n=7p}mac83>7}:j=i1?:94=c6g>d0<uzhjo7>52z?a0a<4?>16n9k5a79~wggc2909w0l;f;c5?8d3m39<;6s|bc294?4|5k>h6>l?;<`64?5>?2wxno?50;0x9g362:3<70l;d;1a4>{tjk81<7<t=c71>6?034h?i7=m0:pfg5=838p1o;<:2;4?8d3n39i<6srb253>5<6k331>8uGb5c8 1562k3?7W78:0y2a?{#:j215n64i2a5>5<#;0?1?n;4n2;7>5=<a:i?6=4+38797f3<f:3?6<54i2a0>5<#;0?1?n;4n2;7>7=<a:i96=4+38797f3<f:3?6>54i2a2>5<#;0?1?n;4n2;7>1=<a:i;6=4+38797f3<f:3?6854i2`e>5<#;0?1?n;4n2;7>3=<a:hn6=4+38797f3<f:3?6:54i2`g>5<#;0?1?n;4n2;7>==<a:hh6=4+38797f3<f:3?6454i2ae>5<#;0?1?n;4n2;7>d=<a:in6=4+38797f3<f:3?6o54i2ag>5<#;0?1?n;4n2;7>f=<a:ih6=4+38797f3<f:3?6i54i2aa>5<#;0?1?n;4n2;7>`=<a:ij6=4+38797f3<f:3?6k54i2a:>5<#;0?1?n;4n2;7>46<3`9h47>5$2;6>6e23g9287?>;:k0g2<72-9297=l5:l0=1<6:21b?ol50;&0=0<4k<1e?4:51298mde=831b?l650;9j5`0=831b?i?50;9j7a6=831b?i<50;9l7a5=831d>n850;9af2c=83;1<7>t$512>7e03Ah<h6Fm4`9l5`3=831vno:l:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c5;?lg12900ei950;9j7g6=831d?:950;9~fg34290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a3==#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a17<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c5;?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc72>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m799'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm5183>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o97;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno:k:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c5;?lg12900ei950;9j7g6=831d?:950;9~fg2a290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k=37do9:188ma1=831b?o>50;9l721=831vno:j:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c5;?lg12900ei950;9j7g6=831d?:950;9~w4c12909wS?j6:?a0f<f>2wx>n850;0xZ7e134h?j7=87:p7=0=83?p1o9j:0g6?8d3k3n<70l;d;f4?8d3n3n<70l;e;f4?xu4jk0;6?uQ3c`89g372=>0q~=mc;296~X4jj16n8<5459~w6dc2909wS=md:?a17<3=2wx?ok50;0xZ6db34h>>7:9;|q0fc<72;qU?oh4=c71>11<uz9h<7>52z\0g5=:j<81845rs2a2>5<5sW9h=63m52870>{t;j81<7<t^2a1?8d2;3>>7p}<c283>7}Y;j901o;<:548yv5d<3:1>vP<c59>f05=<>1v>m9:181[5d>27i9>4;9:p7f1=838pR>m8;<`64?223ty8o54?:3y]7f><5k?;6984}r1`=?6=:rT8o452b42902=z{:ij6=4={_1`e>;e=90?56s|3b`94?4|V:ii70l:1;67?xu4kj0;6?uQ3ba89g362=?0q~=ld;296~X4km16n8?5479~w6eb2909wS=le:?a14<3?2wx?nh50;0xZ6ea34h>=7:6;|q0`5<72<qU?i>4=c70>d2<5k?96l:4=c72>d2<5k?;6l:4}r1g5?6==rT8h<52b419e2=:j<81m:52b439e2=:j<:1m:5rs2f1>5<5sW9o>63m528g2>{t;m91<7<t^2f0?8d2839256s|b`:94?4|5k?:6>76;<`64?b13tyim44?:3y>f04=;0301o;>:e48yvdfi3:1>v3m5280=<=:j<81h;5rscca>5<5s4h?o7=87:?a0a<f>2wxnlm50;0x9g2c2:=<70l;e;c5?xueim0;6?u2b5d9e3=:j=o1?:94}r`a4?6=:r7i8n4<b19>f06=;0=0q~lm1;296~;e=8085:52b5f97g6<uzhi>7>52z?a17<41>16n9k53c28yvde;3:1>v3m5280=2=:j=l1?o>4}|`034<728i157<:{I`7e>"3;80i585U96824c=u-8h477l8:k0g3<72-9297=l5:l0=1<732c8o94?:%1:1?5d=2d8594>;:k0g6<72-9297=l5:l0=1<532c8o?4?:%1:1?5d=2d8594<;:k0g4<72-9297=l5:l0=1<332c8o=4?:%1:1?5d=2d8594:;:k0fc<72-9297=l5:l0=1<132c8nh4?:%1:1?5d=2d85948;:k0fa<72-9297=l5:l0=1<?32c8nn4?:%1:1?5d=2d85946;:k0gc<72-9297=l5:l0=1<f32c8oh4?:%1:1?5d=2d8594m;:k0ga<72-9297=l5:l0=1<d32c8on4?:%1:1?5d=2d8594k;:k0gg<72-9297=l5:l0=1<b32c8ol4?:%1:1?5d=2d8594i;:k0g<<72-9297=l5:l0=1<6821b?n650;&0=0<4k<1e?4:51098m6e0290/?4;53b78j6?328807d=mb;29 6?22:i>7c=64;30?>ofk3:17d=n8;29?l7b>3:17d=k1;29?l5c83:17d=k2;29?j5c;3:17b<l6;29?gd0m3:1=7>50z&774<5k>1Cn:j4Hc6b?j7b=3:17plm4b83>1<729q/8>?53928Lg1c3Ah?m6*<a88a3<=ni?0;66gk7;29?l5e83:17b=87;29?xde=:0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g1>3-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg35290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a3<=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a14<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c5:?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc73>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m789'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm4e83>1<729q/8>?53928Lg1c3Ah?m6*<a88a3<=ni?0;66gk7;29?l5e83:17b=87;29?xde<o0;694?:1y'067=;1:0Do9k;I`7e>"4i00i;45fa783>>oc?3:17d=m0;29?j50?3:17plm4d83>1<729q/8>?53928Lg1c3Ah?m6*<a88a3<=ni?0;66gk7;29?l5e83:17b=87;29?xu6m?0;6?uQ1d489g2d2h<0q~<l6;296~X5k?16n9h53658yv5?>3:19v3m7d82a0=:j=i1h:52b5f9`2=:j=l1h:52b5g9`2=z{:hi6=4={_1af>;e=90?86s|3ca94?4|V:hh70l:2;67?xu4jm0;6?uQ3cf89g352=?0q~=me;296~X4jl16n8<5479~w6da2909wS=mf:?a17<3?2wx?n>50;0xZ6e734h>>7:6;|q0g4<72;qU?n?4=c70>12<uz9h>7>52z\0g7=:j<91885rs2a0>5<5sW9h?63m52872>{t;j>1<7<t^2a7?8d2;3><7p}<c783>7}Y;j<01o;<:5;8yv5d?3:1>vP<c69>f06=<<1v>m7:181[5d027i9=4;6:p7f?=838pR>m6;<`64?203ty8ol4?:3y]7fg<5k?;6974}r1`f?6=:rT8oo52b43901=z{:ih6=4={_1`g>;e=80?96s|3bf94?4|V:io70l:1;65?xu4kl0;6?uQ3bg89g362==0q~=lf;296~X4ko16n8?5489~w6b7290>wS=k0:?a16<f<27i9?4n4:?a14<f<27i9=4n4:p7a7=83?pR>j>;<`67?g034h>>7o8;<`65?g034h><7o8;|q0`7<72;qU?i<4=c70>a0<uz9o?7>52z\0`6=:j<:1?474}r`b<?6=:r7i9<4<989>f06=l?1voo6:1818d2:392563m508g2>{tjhk1<7<t=c70>6?>34h>>7j9;|qaeg<72;q6n9m536589g2c2h<0q~lnc;296~;e<m08;:52b5g9e3=z{kko6=4={<`7b?g134h?i7=87:pfg6=838p1o:l:2`3?8d28392;6s|bc394?4|5k?:6>78;<`7`?5e82wxno<50;0x9g352:3<70l;e;1a4>{tjk91<7<t=c70>6?034h?j7=m0:~f615290:o77524yKf1g<,=9:6o6m;[;4>4}6m3w/>n659b:8m6e1290/?4;53b78j6?32910e>m;:18'7<3=;j?0b>7;:098m6e4290/?4;53b78j6?32;10e>m=:18'7<3=;j?0b>7;:298m6e6290/?4;53b78j6?32=10e>m?:18'7<3=;j?0b>7;:498m6da290/?4;53b78j6?32?10e>lj:18'7<3=;j?0b>7;:698m6dc290/?4;53b78j6?32110e>ll:18'7<3=;j?0b>7;:898m6ea290/?4;53b78j6?32h10e>mj:18'7<3=;j?0b>7;:c98m6ec290/?4;53b78j6?32j10e>ml:18'7<3=;j?0b>7;:e98m6ee290/?4;53b78j6?32l10e>mn:18'7<3=;j?0b>7;:g98m6e>290/?4;53b78j6?328:07d=l8;29 6?22:i>7c=64;32?>o4k>0;6)=65;1`1>h41=0:>65f3c`94?"41<08o85a386956=<ahi1<75f3`:94?=n9l<1<75f3e394?=n;m:1<75f3e094?=h;m91<75`2b494?=ej>o1<7?50;2x 1562;i<7El8d:Ja0d=h9l?1<75rbc6`>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g1f3`k=6=44ie594?=n;k:1<75`36594?=zjk?86=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&0e<<e?h1/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xde=;0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g1f3-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg36290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a3d=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a15<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c5b?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc6g>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g1f3`k=6=44ie594?=n;k:1<75`36594?=zjk>m6=4;:183!249393<6Fm7e9Kf1g<,:k26o9n;hc5>5<<am=1<75f3c294?=h;>=1<75rbc6f>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g1f3`k=6=44ie594?=n;k:1<75`36594?=z{8o=6=4={_3f2>;e<j0j:6s|2b494?4|V;i=70l;f;143>{t;1<1<7;t=c5f>4c234h?o7j8;<`7`?b034h?j7j8;<`7a?b03ty8no4?:3y]7gd<5k?;69:4}r1ag?6=:rT8nn52b40901=z{:ho6=4={_1a`>;e=;0?96s|3cg94?4|V:hn70l:2;65?xu4jo0;6?uQ3cd89g352==0q~=l0;296~X4k916n8<5489~w6e62909wS=l1:?a16<3<2wx?n<50;0xZ6e534h>?7::;|q0g6<72;qU?n=4=c70>10<uz9h87>52z\0g1=:j<918:5rs2a5>5<5sW9h:63m5287=>{t;j=1<7<t^2a4?8d283>>7p}<c983>7}Y;j201o;?:548yv5d13:1>vP<c89>f06=<>1v>mn:181[5di27i9=4;9:p7fd=838pR>mm;<`65?233ty8on4?:3y]7fe<5k?:69;4}r1``?6=:rT8oi52b43903=z{:in6=4={_1`a>;e=80?;6s|3bd94?4|V:im70l:1;6:?xu4l90;68uQ3e289g342h>01o;=:`689g362h>01o;?:`68yv5c93:19vP<d09>f05=i>16n8<5a69>f07=i>16n8>5a69~w6b52909wS=k2:?a16<c>2wx?i=50;0xZ6b434h><7=69:pfd>=838p1o;>:2;:?8d283n=7p}ma883>7}:j<81?474=c72>a0<uzhjm7>52z?a16<41016n8<5d79~wgge2909w0l;c;143>;e<m0j:6s|b`a94?4|5k>o6>98;<`7a?g13tyimi4?:3y>f1`=i?16n9k53658yvde83:1>v3m4b80f5=:j<:1?494}r`a5?6=:r7i9<4<969>f1b=;k:0q~lm2;296~;e=;085:52b5g97g6<uzhi?7>52z?a16<41>16n9h53c28yxd4>00;6<m5c;0bMd3i2.??<4m8b9Y=2<6s8o1q)<l8;;`<>o4k?0;6)=65;1`1>h41=0;76g<c583>!5>=39h96`<9582?>o4k:0;6)=65;1`1>h41=0976g<c383>!5>=39h96`<9580?>o4k80;6)=65;1`1>h41=0?76g<c183>!5>=39h96`<9586?>o4jo0;6)=65;1`1>h41=0=76g<bd83>!5>=39h96`<9584?>o4jm0;6)=65;1`1>h41=0376g<bb83>!5>=39h96`<958:?>o4ko0;6)=65;1`1>h41=0j76g<cd83>!5>=39h96`<958a?>o4km0;6)=65;1`1>h41=0h76g<cb83>!5>=39h96`<958g?>o4kk0;6)=65;1`1>h41=0n76g<c`83>!5>=39h96`<958e?>o4k00;6)=65;1`1>h41=0:<65f3b:94?"41<08o85a386954=<a:i<6=4+38797f3<f:3?6<<4;h1af?6=,:3>6>m:;o1:0?7432cjo7>5;h1b<?6=3`;n:7>5;h1g5?6=3`9o<7>5;h1g6?6=3f9o?7>5;n0`2?6=3kh<j7>51;294~"3;80i995Gb6f8Lg2f3f92>7>5;|`a3`<7280;6=u+42396f1<@k=o7El;a:m2a0<722wi?;;50;694?6|,=9:6<jm;I`4`>Ne<h1/?l75b608 7c728:0e4650;9j`3<722c8n=4?::m0=2<722win9m50;694?6|,=9:6>6?;I`4`>Ne<h1/?l75b638md0=831bh:4?::k0f5<722e8;:4?::af05=83k1<7>t$512>6df3Ah<h6Fm4`9Y=2<6s:=1q)=n9;`45>"5m90?7do8:188ma0=831bm94?::m0=2<722e8544?::k7=?6=,:3>6964n2;7>5=<a==1<7*<9487<>h41=0:76g;6;29 6?22=20b>7;:398m13=83.8584;8:l0=1<432c?87>5$2;6>1><f:3?6954}c`66?6=i3:1<v*;3080fd=Oj>n0Do:n;[;4>4}4?3w/?l75b638 7c72=1bm:4?::kg2?6=3`k?6=44o2;4>5<<g:326=44i5;94?"41<0?46`<9583?>o3?3:1(>7::5:8j6?32810e9850;&0=0<302d8594=;:k71?6=,:3>6964n2;7>6=<a=>1<7*<9487<>h41=0?76smb4394?g=83:p(9=>:2`b?Md0l2Bi8l5U968261=u-9j57l81:&1a5<33`k<6=44ie494?=ni=0;66a<9683>>i4100;66g;9;29 6?22=20b>7;:198m11=83.8584;8:l0=1<632c?:7>5$2;6>1><f:3?6?54i5794?"41<0?46`<9580?>o3<3:1(>7::5:8j6?32=10qol:0;29e?6=8r.??<4<b`9Kf2b<@k>j7W78:0y03?{#;h31n:?4$3g3>1=ni>0;66gk6;29?lg32900c>78:188k6?>2900e9750;&0=0<302d8594?;:k73?6=,:3>6964n2;7>4=<a=<1<7*<9487<>h41=0976g;5;29 6?22=20b>7;:298m12=83.8584;8:l0=1<332win9j50;694?6|,=9:6>6?;I`4`>Ne<h1/?l75b638md0=831bh:4?::k0f5<722e8;:4?::af1`=83>1<7>t$512>6>73Ah<h6Fm4`9'7d?=j>;0el850;9j`2<722c8n=4?::m032<722win9k50;694?6|,=9:6>6?;I`4`>Ne<h1/?l75b638md0=831bh:4?::k0f5<722e8;:4?::a730=83>1<7>t$512>6>73Ah<h6Fm4`9'7d?=j>80el850;9j`2<722c8n=4?::m032<722wxmn4?:3y]ef=:;??1555rs0g5>5<5sW;n:63m4b8b2>{t:j<1<7<t^3a5?851=392;6s|39794?4|5k=m6>7=;<152?5e82wx?5850;4x9g1b28o>70l;c;f4?8d3l3n<70l;f;f4?8d3m3n<70=96;f4?xu4i10;6?uQ3`:896022:h;7p}<bc83>7}Y;kh01o;?:568yv5ek3:1>vP<bb9>f04=<=1v>lk:181[5el27i9?4;5:p7gc=838pR>lj;<`66?213ty8nk4?:3y]7g`<5k?96994}r1`4?6=:rT8o=52b4090<=z{:i:6=4={_1`5>;e=:0?86s|3b094?4|V:i970l:3;66?xu4k:0;6?uQ3b189g342=<0q~=l4;296~X4k=16n8=5469~w6e12909wS=l6:?a16<312wx?n950;0xZ6e034h><7::;|q0g=<72;qU?n64=c73>10<uz9h57>52z\0g<=:j<:18:5rs2ab>5<5sW9hm63m5187=>{t;jh1<7<t^2aa?8d293>?7p}<cb83>7}Y;ji01o;>:578yv5dl3:1>vP<ce9>f07=<?1v>mj:181[5dm27i9<4;7:p7f`=838pR>mi;<`65?2>3ty8h=4?:4y]7a6<5k?86l:4=c71>d2<5k?:6l:4=c73>d2<uz9o=7>55z\0`4=:j<91m:52b409e2=:j<;1m:52b429e2=z{:n96=4={_1g6>;e=:0o:6s|3e194?4|V:n870l:0;1:=>{tjh21<7<t=c72>6?>34h><7j9;|qae<<72;q6n8<538;89g362m<0q~lna;296~;e=:085452b409`3=z{kki6=4={<`7g?50?27i8i4n6:pfde=838p1o:k:254?8d3m3k=7p}mae83>7}:j=l1m;52b5g9721<uzhji7>52z?a0c<4?>16?;85a79~wgga2909w0=95;f5?851>39<;6s|bc294?4|5k>h6>l?;<`64?5>?2wxno?50;0x9g362:3<70l;d;1a4>{tjk81<7<t=c71>6?034h?i7=m0:pfg5=838p1o;<:2;4?8d3n39i<6srs`a94?e|Vhi01>87:`a8960f2hi01>8m:`a8960d2hi01>8k:`a8960b2hi01>8i:`a896172hi01>9>:`a896152hi01>86:`a8yv7b03:1>vP>e99>73>=;kh0q~?j9;296~X6m016?;k53c`8yv7bi3:1>vP>e`9>73c=;j=0q~?jb;296~X6mk16?;k53b:8yv7bk3:1>vP>eb9>73c=;j30q~?jd;296~X6mm16?;k53bc8yv7bm3:1>vP>ed9>73c=;jh0q~?jf;296~X6mo16?;k53ba8yv7a83:1>vP>f19>73c=;jn0q~?i1;296~X6n816?;k53bg8yv7a:3:1>vP>f39>73c=;jl0q~?i3;296~X6n:16?;653ca8yv7a<3:1>vP>f59>73c=;ki0q~?i5;296~X6n<16?;k53cf8yv7a>3:1>vP>f79>73c=;ko0q~?i7;296~X6n>16?;k53cd8yv7a03:1>vP>f99>73c=;j:0q~?i9;296~X6n016?;k53b38yv7ai3:1>vP>f`9>73c=;j80q~?ib;296~X6nk16?;k53b18yv7ak3:1>vP>fb9>73c=;j>0q~?id;296~X6nm16?;k53b48yv7am3:1>vP>fd9>73>=;kn0q~?if;296~X6no16?;h53c`8yv4783:1>vP=019>73`=;j=0q~<?1;296~X58816?;h53b:8yv47:3:1>vP=039>73`=;j30q~<?3;296~X58:16?;h53bc8yv47<3:1>vP=059>73`=;jh0q~<?5;296~X58<16?;h53ba8yv47>3:1>vP=079>73`=;jn0q~<?7;296~X58>16?;h53bg8yv4703:1>vP=099>73`=;jl0q~<?9;296~X58016?;653cg8yv47i3:1>vP=0`9>73`=;ki0q~<?b;296~X58k16?;h53cf8yv47k3:1>vP=0b9>73`=;ko0q~<?d;296~X58m16?;h53cd8yv47m3:1>vP=0d9>73`=;j:0q~<?f;296~X58o16?;h53b38yv4683:1>vP=119>73`=;j80q~<>1;296~X59816?;h53b18yv46:3:1>vP=139>73`=;j>0q~<>3;296~X59:16?;h53b48yv46<3:1>vP=159>73>=;kl0q~<>5;296~X59<16?:>53c`8yv46>3:1>vP=179>726=;j=0q~<>7;296~X59>16?:>53b:8yv4603:1>vP=199>726=;j30q~<>9;296~X59016?:>53bc8yv46i3:1>vP=1`9>726=;jh0q~<>b;296~X59k16?:>53ba8yv46k3:1>vP=1b9>726=;jn0q~<>d;296~X59m16?:>53bg8yv46m3:1>vP=1d9>726=;jl0q~<>f;296~X59o16?;653b28yv4583:1>vP=219>726=;ki0q~<=1;296~X5:816?:>53cf8yv45:3:1>vP=239>726=;ko0q~<=3;296~X5::16?:>53cd8yv45<3:1>vP=259>726=;j:0q~<=5;296~X5:<16?:>53b38yv45>3:1>vP=279>726=;j80q~<=7;296~X5:>16?:>53b18yv4503:1>vP=299>726=;j>0q~<=9;296~X5:016?:>53b48yv45i3:1>vP=2`9>73>=;j;0q~<=b;296~X5:k16?:?53c`8yv45k3:1>vP=2b9>727=;j=0q~<=d;296~X5:m16?:?53b:8yv45m3:1>vP=2d9>727=;j30q~<=f;296~X5:o16?:?53bc8yv4483:1>vP=319>727=;jh0q~<<1;296~X5;816?:?53ba8yv44:3:1>vP=339>727=;jn0q~<<3;296~X5;:16?:?53bg8yv44<3:1>vP=359>727=;jl0q~<<5;296~X5;<16?;653b08yv44>3:1>vP=379>727=;ki0q~<<7;296~X5;>16?:?53cf8yv4403:1>vP=399>727=;ko0q~<<9;296~X5;016?:?53cd8yv44i3:1>vP=3`9>727=;j:0q~<<b;296~X5;k16?:?53b38yv44k3:1>vP=3b9>727=;j80q~<<d;296~X5;m16?:?53b18yv44m3:1>vP=3d9>727=;j>0q~<<f;296~X5;o16?:?53b48yv4383:1>vP=419>73>=;j90q~<;1;296~X5<816?:<53c`8yv43:3:1>vP=439>724=;j=0q~<;3;296~X5<:16?:<53b:8yv43<3:1>vP=459>724=;j30q~<;5;296~X5<<16?:<53bc8yv43>3:1>vP=479>724=;jh0q~<;7;296~X5<>16?:<53ba8yv4303:1>vP=499>724=;jn0q~<;9;296~X5<016?:<53bg8yv43i3:1>vP=4`9>724=;jl0q~<;b;296~X5<k16?;653b68yv43k3:1>vP=4b9>724=;ki0q~<;d;296~X5<m16?:<53cf8yv43m3:1>vP=4d9>724=;ko0q~<;f;296~X5<o16?:<53cd8yv4283:1>vP=519>724=;j:0q~<:1;296~X5=816?:<53b38yv42:3:1>vP=539>724=;j80q~<:3;296~X5=:16?:<53b18yv42<3:1>vP=559>724=;j>0q~<:5;296~X5=<16?:<53b48yv42>3:1>vP=579>73>=;j<0q~<:7;296~X5=>16?;653b58yv4203:1>vP=599>73?=;kh0q~<:9;296~X5=016?;753b58yv42i3:1>vP=5`9>73?=;j20q~<:b;296~X5=k16?;753b;8yv42k3:1>vP=5b9>73?=;jk0q~<:d;296~X5=m16?;753b`8yv42m3:1>vP=5d9>73?=;ji0q~<:f;296~X5=o16?;753bf8yv4183:1>vP=619>73?=;jo0q~<91;296~X5>816?;753bd8yv41:3:1>vP=639>73g=;kh0q~<93;296~X5>:16?;753ca8yv41<3:1>vP=659>73?=;kn0q~<95;296~X5><16?;753cg8yv41>3:1>vP=679>73?=;kl0q~<97;296~X5>>16?;753b28yv4103:1>vP=699>73?=;j;0q~<99;296~X5>016?;753b08yv41i3:1>vP=6`9>73?=;j90q~<9b;296~X5>k16?;753b68yv41l3:1>vP=6e9>73?=;j<0q~<9e;296~X5>l16?;o53b58yv41n3:1>vP=6g9>73g=;j20q~<80;296~X5?916?;o53b;8yv4093:1>vP=709>73g=;jk0q~<82;296~X5?;16?;o53b`8yv40;3:1>vP=729>73g=;ji0q~<84;296~X5?=16?;o53bf8yv40=3:1>vP=749>73g=;jo0q~<86;296~X5??16?;o53bd8yv40?3:1>vP=769>73>=;j20q~<88;296~X5?116?;o53ca8yv4013:1>vP=789>73g=;kn0q~<8a;296~X5?h16?;o53cg8yv40j3:1>vP=7c9>73g=;kl0q~<8c;296~X5?j16?;o53b28yv40l3:1>vP=7e9>73g=;j;0q~<8e;296~X5?l16?;o53b08yv40n3:1>vP=7g9>73g=;j90q~<70;296~X50916?;o53b68yv4?93:1>vP=809>73g=;j<0q~<72;296~X50;16?;653b;8yv4?;3:1>vP=829>73d=;kh0q~<74;296~X50=16?;l53b58yv4?=3:1>vP=849>73d=;j20q~<76;296~X50?16?;l53b;8yv4??3:1>vP=869>73d=;jk0q~<78;296~X50116?;l53b`8yv4?13:1>vP=889>73d=;ji0q~<7a;296~X50h16?;l53bf8yv4?j3:1>vP=8c9>73d=;jo0q~<7c;296~X50j16?;l53bd8yv4?l3:1>vP=8e9>73>=;jk0q~<7e;296~X50l16?;l53ca8yv4?n3:1>vP=8g9>73d=;kn0q~<60;296~X51916?;l53cg8yv4>93:1>vP=909>73d=;kl0q~<62;296~X51;16?;l53b28yv4>;3:1>vP=929>73d=;j;0q~<64;296~X51=16?;l53b08yv4>=3:1>vP=949>73d=;j90q~<66;296~X51?16?;l53b68yv4>?3:1>vP=969>73d=;j<0q~<68;296~X51116?;653b`8yv4>13:1>vP=989>73e=;kh0q~<6a;296~X51h16?;m53b58yv4>j3:1>vP=9c9>73e=;j20q~<6c;296~X51j16?;m53b;8yv4>l3:1>vP=9e9>73e=;jk0q~<6e;296~X51l16?;m53b`8yv4>n3:1>vP=9g9>73e=;ji0q~<n0;296~X5i916?;m53bf8yv4f93:1>vP=a09>73e=;jo0q~<n2;296~X5i;16?;m53bd8yv4f;3:1>vP=a29>73>=;ji0q~<n4;296~X5i=16?;m53ca8yv4f=3:1>vP=a49>73e=;kn0q~<n6;296~X5i?16?;m53cg8yv4f?3:1>vP=a69>73e=;kl0q~<n8;296~X5i116?;m53b28yv4f13:1>vP=a89>73e=;j;0q~<na;296~X5ih16?;m53b08yv4fj3:1>vP=ac9>73e=;j90q~<nc;296~X5ij16?;m53b68yv4fl3:1>vP=ae9>73e=;j<0q~<ne;296~X5il16?;653bf8yv4fn3:1>vP=ag9>73b=;kh0q~<m0;296~X5j916?;j53b58yv4e93:1>vP=b09>73b=;j20q~<m2;296~X5j;16?;j53b;8yv4e;3:1>vP=b29>73b=;jk0q~<m4;296~X5j=16?;j53b`8yv4e=3:1>vP=b49>73b=;ji0q~<m6;296~X5j?16?;j53bf8yv4e?3:1>vP=b69>73b=;jo0q~<m8;296~X5j116?;j53bd8yv4e13:1>vP=b89>73>=;jo0q~<ma;296~X5jh16?;j53ca8yv4ej3:1>vP=bc9>73b=;kn0q~<mc;296~X5jj16?;j53cg8yv4el3:1>vP=be9>73b=;kl0q~<me;296~X5jl16?;j53b28yv4en3:1>vP=bg9>73b=;j;0q~<l0;296~X5k916?;j53b08yv4d93:1>vP=c09>73b=;j90q~<l2;296~X5k;16?;j53b68yv4d;3:1>vP=c29>73b=;j<0q~<l5;296~X5k<16?;653bd8yv4d>3:1>vP=c79>73?=:j<0q~=n8;29g~X4i116?;653`:8960f2:k370=9b;1b<>;4>j08m55237f97d><5:<n6>o7;<15b?5f0278;=4<a99>727=;h201>9=:2c;?851139j46s|3e294?e|V:n;70=98;1g4>;4>h08h=5237`97a6<5:<h6>j?;<15`?5c8278:h4<d19>73`=;m:01>9?:2f3?850939o<63<7380`5=:;?31?i>4}r1g5?6=krT8h<5237:97a7<5:<j6>j>;<15f?5c9278:n4<d09>73b=;m;01>8j:2f2?851n39o=63<7180`4=:;>;1?i?4=251>6b6349=57=k1:p7a4=838pR>j=;<15=?5c:2wx?i=50;0xZ6b4349=47=k3:pf<0=838p1o9i:2;1?85103;n:6s|b8594?4|5:=96?m9;<15=?7b>2wxn4650;0x960?2;i=70=9a;3f2>{tj031<7<t=24b>7e1349=n7?j6:pf<g=838p1>8m:3a5?851k3;n:6s|b8`94?4|5:<h6?m9;<15`?7b>2wxn4m50;0x960c2;i=70=9e;3f2>{tj0n1<7<t=24f>7e1349=j7?j6:pf<c=838p1>8i:3a5?85083;n:6s|b8d94?4|5:=;6?m9;<145?7b>2wxnl>50;0x96162;i=70=82;3f2>{tjk?1<7<t=251>6b5349=57=k3:pfg0=838p1>87:2f1?851i39o?6s|bc594?4|5:<j6>j=;<15f?5c;2wxno650;0x960e2:n970=9c;1g7>{tjk31<7<t=24`>6b5349=h7=k3:pfgg=838p1>8k:2f1?851m39o?6s|bc`94?4|5:<n6>j=;<15b?5c;2wxnom50;0x960a2:n970=80;1g7>{tjkn1<7<t=253>6b5349<=7=k3:pfgc=838p1>9>:2f1?850:39o?6srb82a>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk3;o7>53;294~"3;80i;n5Gb6f8Lg2f3`k=6=44i255>5<<g:3:6=44}c;26?6=;3:1<v*;30803g=Oj>n0Do:n;%0f4?5d3`8hm7>5;h0`f?6=3f92=7>5;|`:4=<72:0;6=u+423972d<@k=o7El;a:&1a5<4k2c9ol4?::k1gg<722e85<4?::a=51=8391<7>t$512>61e3Ah<h6Fm4`9'6`6=;j1b>no50;9j6fd=831d?4?50;9~f<6229026=4?{%605?5e12Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni=0;66gn7;29?lb12900c>78:188k6??2900qo7?4;29=?6=8r.??<4<b89Kf2b<@k>j7)<j0;08m16=831b8<4?::k76?6=3`>86=44i`694?=ni>0;66gk6;29?j5>?3:17b=68;29?xd>8?0;644?:1y'067=;k30Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k?6=44i`594?=nl?0;66a<9683>>i4110;66sm91c94?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn4?<:187>5<7s->8=7?k9:Ja3a=Oj=k0(?k?:09j==<722co:7>5;h1:e?6=3f92;7>5;|`:51<7210964uGb5c8 1562k237W78:0y2f?{#j=h18>>4i0g;>5<#;0?1=h94n2;7>5=<ahi1<75f3`:94?=n;m;1<75f3e294?=n;m81<75`3e194?=h:j<1<75mb6d94?7=83:p(9=>:c77?Md0l2Bi8l5`38094?=zj:<<6=4>c;`962}Oj=k0(9=>:c:g?_?028q:i7s+2b:9=43<a:i=6=4+38797f3<f:3?6=54i2a7>5<#;0?1?n;4n2;7>4=<a:i86=4+38797f3<f:3?6?54i2a1>5<#;0?1?n;4n2;7>6=<a:i:6=4+38797f3<f:3?6954i2a3>5<#;0?1?n;4n2;7>0=<a:hm6=4+38797f3<f:3?6;54i2`f>5<#;0?1?n;4n2;7>2=<a:ho6=4+38797f3<f:3?6554i2``>5<#;0?1?n;4n2;7><=<a:im6=4+38797f3<f:3?6l54i2af>5<#;0?1?n;4n2;7>g=<a:io6=4+38797f3<f:3?6n54i2a`>5<#;0?1?n;4n2;7>a=<a:ii6=4+38797f3<f:3?6h54i2ab>5<#;0?1?n;4n2;7>c=<a:i26=4+38797f3<f:3?6<>4;h1`<?6=,:3>6>m:;o1:0?7632c8o:4?:%1:1?5d=2d8594>2:9j7gd=83.8584<c49m7<2=9:10elm50;9j7d>=831b=h850;9j7a7=831b?i>50;9j7a4=831d?i=50;9l6f0=831in:h50;394?6|,=9:6o;;;I`4`>Ne<h1d?4<50;9~fg1b290:6=4?{%605?4d?2Bi;i5Gb5c8k4c22900qol;c;290?6=8r.??<4<819Kf2b<@k>j7)=n9;`5b>of>3:17dj8:188m6d72900c>98:188ygd2;3:1m7>50z&774<4jh1Cn:j4Hc6b?_?028q8;7s+3`;9f3`<,;o;695fa683>>oc>3:17do;:188k6?02900c>76:188m1?=83.8584;8:l0=1<732c?;7>5$2;6>1><f:3?6<54i5494?"41<0?46`<9581?>o3=3:1(>7::5:8j6?32:10e9:50;&0=0<302d8594;;:af04=83k1<7>t$512>6df3Ah<h6Fm4`9Y=2<6s:=1q)=n9;`5b>"5m90?7do8:188ma0=831bm94?::m0=2<722e8544?::k7=?6=,:3>6964n2;7>5=<a==1<7*<9487<>h41=0:76g;6;29 6?22=20b>7;:398m13=83.8584;8:l0=1<432c?87>5$2;6>1><f:3?6954}c`65?6=i3:1<v*;3080fd=Oj>n0Do:n;[;4>4}4?3w/?l75b7d8 7c72=1bm:4?::kg2?6=3`k?6=44o2;4>5<<g:326=44i5;94?"41<0?46`<9583?>o3?3:1(>7::5:8j6?32810e9850;&0=0<302d8594=;:k71?6=,:3>6964n2;7>6=<a=>1<7*<9487<>h41=0?76smb4294?g=83:p(9=>:2`b?Md0l2Bi8l5U968261=u-9j57l9f:&1a5<33`k<6=44ie494?=ni=0;66a<9683>>i4100;66g;9;29 6?22=20b>7;:198m11=83.8584;8:l0=1<632c?:7>5$2;6>1><f:3?6?54i5794?"41<0?46`<9580?>o3<3:1(>7::5:8j6?32=10qol;d;290?6=8r.??<4<819Kf2b<@k>j7)=n9;`5b>of>3:17dj8:188m6d72900c>98:188ygd3n3:187>50z&774<4091Cn:j4Hc6b?!5f13h=j6gn6;29?lb02900e>l?:188k6102900qol;e;290?6=8r.??<4<819Kf2b<@k>j7)=n9;`5b>of>3:17dj8:188m6d72900c>98:188yg51>3:187>50z&774<4091Cn:j4Hc6b?!5f13h<<6gn6;29?lb02900e>l?:188k6102900q~?j6;296~X6m?16n9m5a79~w7e12909wS<l6:?023<4?>1v>6::1818d0n392>63<6780f5=z{:2=6=49{<`4a?7b=27i8n4k7:?a0a<c?27i8k4k7:?a0`<c?278:;4k7:p7gd=838pR>lm;<`64?233ty8nn4?:3y]7ge<5k?969:4}r1a`?6=:rT8ni52b40900=z{:hn6=4={_1aa>;e=;0?:6s|3cd94?4|V:hm70l:2;64?xu4k90;6?uQ3b289g352=30q~=l1;296~X4k816n8=5459~w6e52909wS=l2:?a16<3=2wx?n=50;0xZ6e434h>?7:9;|q0g1<72;qU?n:4=c70>11<uz9h:7>52z\0g3=:j<91845rs2a4>5<5sW9h;63m51871>{t;j21<7<t^2a;?8d283>=7p}<c883>7}Y;j301o;?:558yv5di3:1>vP<c`9>f06=<01v>mm:181[5dj27i9<4;4:p7fe=838pR>ml;<`65?223ty8oi4?:3y]7fb<5k?:6984}r1`a?6=:rT8oh52b43902=z{:im6=4={_1`b>;e=80?56s|3e294?3|V:n;70l:3;c7?8d2:3k?70l:1;c7?8d283k?7p}<d083>0}Y;m;01o;<:`589g352h=01o;>:`589g372h=0q~=k2;296~X4l;16n8=5d79~w6b42909wS=k3:?a15<4101voo7:1818d29392563m518g2>{tjh31<7<t=c71>6?>34h>=7j9;|qaed<72;q6n8=538;89g352m<0q~lnb;296~;e<j08;:52b5f9e3=z{kkh6=4={<`7`?50?27i8h4n6:pfdb=838p1o:i:`489g2b2:=<7p}mad83>7}:j=l1?:94=245>d0<uzhi<7>52z?a0f<4j916n8>53858yvde93:1>v3m5080=2=:j=n1?o>4}r`a6?6=:r7i9?4<969>f1c=;k:0q~lm3;296~;e=:085:52b5d97g6<utyjo7>52z\bg>;4>>0jo6s|1d:94?4|V8o370=97;1af>{t:j<1<7<t^3a5?851?38h:6s|3`:94?4|V:k370=97;1b<>{t;m:1<7<t^2f3?851?39o<6s|3e394?4|V:n:70=97;1g5>{t;m81<7<t^2f1?851?39o>6s|3e194?4|V:n870=97;1g7>{tj0<1<7?:{<`4b?5>:278::4<c79>731=;j>01>88:2a0?851?39h>63<6680g4=:;?=1?n>4=244>6da349=;7=me:?022<4jm16?;953ca896002:im70=97;1`a>;4>>08oi5237597fe<5:<<6>mm;<153?5di278::4<c89>731=;j201>88:2a4?851?3;n:6srb97a>5<4290;w):<1;14f>Ne?m1Cn9o4$3g3>4e<a;ij6=44i3aa>5<<g:3:6=44}c:05?6==3:1<v*;30803a=Oj>n0Do:n;%0f4?d<a;ij6=44i3aa>5<<a;ih6=44i3ag>5<<g:3:6=44}c:07?6==3:1<v*;30803a=Oj>n0Do:n;%0f4??23`8hm7>5;h0`f?6=3`8ho7>5;h0``?6=3f92=7>5;|`;71<72<0;6=u+423972b<@k=o7El;a:&1a5<6n2c9ol4?::k1gg<722c9on4?::k1ga<722e85<4?::a<63=83?1<7>t$512>61c3Ah<h6Fm4`9'6`6=:o1b>no50;9j6fd=831b>nm50;9j6fb=831d?4?50;9~f=51290>6=4?{%605?50l2Bi;i5Gb5c8 7c728in7d<la;29?l4dj3:17d<lc;29?l4dl3:17b=61;29?xd?;>0;684?:1y'067=;>n0Do9k;I`7e>"5m90j7d<la;29?l4dj3:17d<lc;29?l4dl3:17b=61;29?xd?;10;684?:1y'067=;>n0Do9k;I`7e>"5m9097d<la;29?l4dj3:17d<lc;29?l4dl3:17b=61;29?xd?;00;684?:1y'067=;>n0Do9k;I`7e>"5m9027d<la;29?l4dj3:17d<lc;29?l4dl3:17b=61;29?xd?;h0;684?:1y'067=;>n0Do9k;I`7e>"5m90:hh5f2bc94?=n:jh1<75f2ba94?=n:jn1<75`38394?=zj19i6=4::183!24939<h6Fm7e9Kf1g<,;o;6?64i3ab>5<<a;ii6=44i3a`>5<<a;io6=44o2;2>5<<uk28>7>55;294~"3;808;i5Gb6f8Lg2f3-8n<7j4i3ab>5<<a;ii6=44i3a`>5<<a;io6=44o2;2>5<<uk2287>52;294~"3;808:95Gb6f8Lg2f3`8h57>5;n1:5?6=3th3:l4?:283>5}#<:;1?:l4Hc5g?Md3i2.9i=4>c:k1gd<722c9oo4?::m0=4<722wi48o50;194?6|,=9:6>9m;I`4`>Ne<h1/>h>52d9j6fg=831b>nl50;9l7<7=831vn57<:180>5<7s->8=7=8b:Ja3a=Oj=k0(?k?:0a0?l4di3:17d<lb;29?j5>93:17pl78b83>0<729q/8>?536f8Lg1c3Ah?m6*=e18e?l4di3:17d<lb;29?l4dk3:17d<ld;29?j5>93:17pl78d83>1<729q/8>?51e78Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722e85:4?::a<=`=83>1<7>t$512>4b23Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75`38594?=zj12o6=4;:183!2493;o56Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17d=6a;29?j5>?3:17pl76083>0<729q/8>?51e68Lg1c3Ah?m6*=e182?l??2900el:50;9jea<722co:7>5;n1:3?6=3th39i4?:483>5}#<:;1=i:4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fae83>>oc>3:17b=67;29?xd?=l0;684?:1y'067=9m>0Do9k;I`7e>"5m90:7d77:188md2=831bmi4?::kg2?6=3f92;7>5;|`;1f<72=0;6=u+42395a?<@k=o7El;a:&1a5<63`336=44ie494?=n;0k1<75`38594?=zj1<;6=4::183!2493;o86Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dok:188ma0=831d?4950;9~f=3a290?6=4?{%605?7c=2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44o2;4>5<<uk2on7>54;294~"3;80:h85Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?j5>?3:17pl75983>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn5;6:187>5<7s->8=7=85:Ja3a=Oj=k0(?k?:09jea<722co:7>5;h3f1?6=3f92;7>5;|`;12<72<0;6=u+42395a2<@k=o7El;a:&1a5<63`336=44i`694?=nim0;66gk6;29?j5>?3:17pl79383>0<729q/8>?51e68Lg1c3Ah?m6*=e182?l??2900el:50;9jea<722co:7>5;n1:3?6=3th3584?:483>5}#<:;1=io4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fd783>>o41h0;66a<9683>>{e00<1<7;50;2x 15628nj7El8d:Ja0d=#:l:1=6g68;29?lg32900ei850;9j7<g=831d?4950;9~f=5d290>6=4?{%605?7ci2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44i2;b>5<<g:3<6=44}c:0`?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl73d83>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi4>h50;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj1>;6=4::183!2493;om6Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188m6?f2900c>78:188yg>393:197>50z&774<6lh1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;h1:e?6=3f92;7>5;|`;07<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm85194?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn5:;:186>5<7s->8=7?ka:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<a:3j6=44o2;4>5<<uk2?97>55;294~"3;80:hl5Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?l5>i3:17b=67;29?xd?=?0;694?:1y'067=9m?0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::m0=2<722wi4;750;694?6|,=9:6<j:;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=h;0=1<75rb94;>5<3290;w):<1;3g1>Ne?m1Cn9o4$3g3>4=n110;66gn4;29?lb12900c>78:188yg>fl3:1?7>50z&774<e?j1Cn:j4Hc6b?lg12900e>99:188k6?62900qo6na;290?6=8r.??<4<819Kf2b<@k>j7do9:188ma1=831b?o>50;9l721=831vn5l>:180>5<7s->8=7l8c:Ja3a=Oj=k0el850;9j720=831d?4?50;9~f=gb290?6=4?{%605?5?82Bi;i5Gb5c8md0=831bh:4?::k0f5<722e8;:4?::a<g3=8391<7>t$512>g1d3Ah<h6Fm4`9je3<722c8;;4?::m0=4<722wi4o<50;694?6|,=9:6>6?;I`4`>Ne<h1bm;4?::kg3?6=3`9i<7>5;n143?6=3th3n44?:283>5}#<:;1n:m4Hc5g?Md3i2cj:7>5;h142?6=3f92=7>5;|`;f3<72=0;6=u+42397=6<@k=o7El;a:kb2?6=3`n<6=44i2`3>5<<g:=<6=44}c:a`?6=;3:1<v*;308a3f=Oj>n0Do:n;hc5>5<<a:==6=44o2;2>5<<uk2im7>54;294~"3;8084=5Gb6f8Lg2f3`k=6=44ie594?=n;k:1<75`36594?=zj1i:6=4<:183!2493h<o6Fm7e9Kf1g<ah<1<75f36494?=h;0;1<75rb9`f>5<3290;w):<1;1;4>Ne?m1Cn9o4i`494?=nl>0;66g<b183>>i4?>0;66sm8b794?5=83:p(9=>:c5`?Md0l2Bi8l5fa783>>o4??0;66a<9083>>{e0j81<7:50;2x 1562:2;7El8d:Ja0d=ni?0;66gk7;29?l5e83:17b=87;29?xd?k00;6>4?:1y'067=j>i0Do9k;I`7e>of>3:17d=86;29?j5>93:17pl7c783>1<729q/8>?53928Lg1c3Ah?m6gn6;29?lb02900e>l?:188k6102900qo6ld;297?6=8r.??<4m7b9Kf2b<@k>j7do9:188m6112900c>7>:188yg>di3:187>50z&774<4091Cn:j4Hc6b?lg12900ei950;9j7g6=831d?:950;9~f=b729086=4?{%605?d0k2Bi;i5Gb5c8md0=831b?:850;9l7<7=831vn5ol:181>5<7s->8=7=8a:Ja3a=Oj=k0(?k?:0a8m7ef2900c>7>:188yg>e83:1>7>50z&774<4?h1Cn:j4Hc6b?!4b83;h7d<la;29?j5>93:17pl7b583>7<729q/8>?536c8Lg1c3Ah?m6*=e182g>o5kh0;66a<9083>>{e0k21<7<50;2x 1562:=j7El8d:Ja0d=#:l:1=n5f2bc94?=h;0;1<75rb9``>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk2h<7>52;294~"3;808;l5Gb6f8Lg2f3-8n<7?l;h0`e?6=3f92=7>5;|`;g1<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi4n650;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f=ed29096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo6lf;296?6=8r.??<4<7`9Kf2b<@k>j7)<j0;3`?l4di3:17b=61;29?xd?ik0;684?:1y'067=9mk0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::k0=d<722e85:4?::a<d`=83?1<7>t$512>4bf3Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75f38c94?=h;0=1<75rb9`0>5<2290;w):<1;3ge>Ne?m1Cn9o4$3g3>4=n110;66gn4;29?lb12900e>7n:188k6?02900qo6m7;291?6=8r.??<4>d`9Kf2b<@k>j7)<j0;38m<>=831bm94?::kg2?6=3`92m7>5;n1:3?6=3th3no4?:483>5}#<:;1=io4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fd783>>o41h0;66a<9683>>{e0kl1<7;50;2x 15628nj7El8d:Ja0d=#:l:1=6g68;29?lg32900ei850;9j7<g=831d?4950;9~f=e4290>6=4?{%605?7ci2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44i2;b>5<<g:3<6=44}c:`3?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl7cc83>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi4nk50;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj18?6=4<:183!24939<n6Fm7e9Kf1g<,;o;6?k4i3ab>5<<a;ii6=44o2;2>5<<uk29?7>54;294~"3;808;n5Gb6f8Lg2f3-8n<7?l7:k1gd<722c9oo4?::k1gf<722e85<4?::a<74=83?1<7>t$512>61c3Ah<h6Fm4`9'6`6=9l:0e?mn:188m7ee2900e?ml:188m7ec2900c>7>:188yg1ai3:187>50z&774<6lk1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?o>50;9l7<1=831vn:h6:187>5<7s->8=7?kb:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0f5<722e85:4?::a3c>=83>1<7>t$512>4be3Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`9i<7>5;n1:3?6=3th<j:4?:583>5}#<:;1=il4Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2`3>5<<g:3<6=44}c5e2?6=<3:1<v*;3082`g=Oj>n0Do:n;%0f4?773`336=44ie494?=n;k:1<75`38594?=zj>l>6=4;:183!2493;on6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<b183>>i41>0;66sm7g694?2=83:p(9=>:0fa?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5e83:17b=67;29?xd0n:0;694?:1y'067=9mh0Do9k;I`7e>"5m90:<6g68;29?lb12900e>l?:188k6?02900qo6=1;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~f=7529086=4?{%605?50j2Bi;i5Gb5c8 7c728i0e?mn:188m7ee2900c>7>:188yg>6?3:187>50z&774<6l<1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;n1:3?6=3th3=;4?:583>5}#<:;1=i;4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fd783>>i41>0;66sm80:94?3=83:p(9=>:0f7?Md0l2Bi8l5+2d295>o>03:17do;:188mdb=831bh;4?::m0=2<722wi4<=50;694?6|,=9:6<j6;I`4`>Ne<h1/>h>51:k:<?6=3`n=6=44i2;b>5<<g:3<6=44}c:21?6==3:1<v*;3082`1=Oj>n0Do:n;%0f4?7<a021<75fa583>>ofl3:17dj9:188k6?02900qo6>4;291?6=8r.??<4>d59Kf2b<@k>j7)<j0;38m<>=831bm94?::kb`?6=3`n=6=44o2;4>5<<uk2:57>55;294~"3;80:h95Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gnd;29?lb12900c>78:188yg1an3:1?7>50z&774<4?k1Cn:j4Hc6b?!4b83;h7d<la;29?l4dj3:17b=61;29?xd?8?0;694?:1y'067=9m?0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::m0=2<722wi4=;50;694?6|,=9:6<j:;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=h;0=1<75rb927>5<3290;w):<1;3g1>Ne?m1Cn9o4$3g3>4=n110;66gn4;29?lb12900c>78:188yg>7;3:187>50z&774<6l<1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;n1:3?6=3th3<:4?:483>5}#<:;1=i:4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fae83>>oc>3:17b=67;29?xd?890;694?:1y'067=9m30Do9k;I`7e>"5m90:7d77:188ma0=831b?4o50;9l7<1=831vn5>=:186>5<7s->8=7?k4:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hcg>5<<am<1<75`38594?=zj1::6=4::183!2493;o86Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dok:188ma0=831d?4950;9~f=6?290>6=4?{%605?7c<2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`ko6=44ie494?=h;0=1<75rb7f0>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.9i=4;;hc4>5<<am<1<75fa583>>i41>0;66a<9883>>o313:1(>7::5:8j6?32910e9950;&0=0<302d8594>;:k72?6=,:3>6964n2;7>7=<a=?1<7*<9487<>h41=0876g;4;29 6?22=20b>7;:598yg0ck3:1m7>50z&774<4jh1Cn:j4Hc6b?_?028q8;7s+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3th=ho4?:`83>5}#<:;1?oo4Hc5g?Md3i2P2;7?t368~ 7c72=1bm:4?::kg2?6=3`k?6=44o2;4>5<<g:326=44i5;94?"41<0?46`<9583?>o3?3:1(>7::5:8j6?32810e9850;&0=0<302d8594=;:k71?6=,:3>6964n2;7>6=<a=>1<7*<9487<>h41=0?76sm6`194?g=83:p(9=>:2`b?Md0l2Bi8l5U968261=u-8h479je:&0e<<e>o1/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xd1i;0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$3a;>2cb3-9j57l9f:&1a5<33`k<6=44ie494?=ni=0;66a<9683>>i4100;66g;9;29 6?22=20b>7;:198m11=83.8584;8:l0=1<632c?:7>5$2;6>1><f:3?6?54i5794?"41<0?46`<9580?>o3<3:1(>7::5:8j6?32=10qo8n1;290?6=8r.??<4<809Kf2b<@k>j7)<l8;5fa>"4i00i:k5f2bc94?=n:jh1<75f3c294?=h;0;1<75rb7f5>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.9o548f39'7d?=j?l0(?k?:59je2<722co:7>5;hc7>5<<g:3<6=44o2;:>5<<a=31<7*<9487<>h41=0;76g;7;29 6?22=20b>7;:098m10=83.8584;8:l0=1<532c?97>5$2;6>1><f:3?6>54i5694?"41<0?46`<9587?>{e>m?1<7o50;2x 1562:hj7El8d:Ja0d=]1>0:w>95}%0`<?1a:2.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07pl9d583>1<729q/8>?53938Lg1c3Ah?m6*=c984b7=#;h31n;h4i3ab>5<<a;ii6=44i2`3>5<<g:3:6=44}c4be?6=i3:1<v*;3080fd=Oj>n0Do:n;[;4>4}4?3w/>n657dd8 6g>2k<m7)<j0;68md1=831bh;4?::kb0?6=3f92;7>5;n1:=?6=3`>26=4+38790==i;0>1<65f4683>!5>=3>37c=64;38?l21290/?4;5499m7<2=:21b884?:%1:1?2?3g9287=4;h67>5<#;0?1855a38690>=zj?k26=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&1g=<0mo1/?l75b7d8 7c72=1bm:4?::kg2?6=3`k?6=44o2;4>5<<g:326=44i5;94?"41<0?46`<9583?>o3?3:1(>7::5:8j6?32810e9850;&0=0<302d8594=;:k71?6=,:3>6964n2;7>6=<a=>1<7*<9487<>h41=0?76sm6`:94?2=83:p(9=>:2:2?Md0l2Bi8l5+2b:93``<,:k26o8i;h0`e?6=3`8hn7>5;h1a4?6=3f92=7>5;|`5g2<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(?m7:6d2?!5f13h=j6*=e187?lg02900ei850;9je1<722e85:4?::m0=<<722c?57>5$2;6>1><f:3?6=54i5594?"41<0?46`<9582?>o3>3:1(>7::5:8j6?32;10e9;50;&0=0<302d8594<;:k70?6=,:3>6964n2;7>1=<uk<h:7>5a;294~"3;808nl5Gb6f8Lg2f3S3<6<u<7;'6f>=?o;0(>o6:c4e?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rb7a6>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.9o548f09'7d?=j?l0(?k?:59je2<722co:7>5;hc7>5<<g:3<6=44o2;:>5<<a=31<7*<9487<>h41=0;76g;7;29 6?22=20b>7;:098m10=83.8584;8:l0=1<532c?97>5$2;6>1><f:3?6>54i5694?"41<0?46`<9587?>{e>j>1<7o50;2x 1562:hj7El8d:Ja0d=]1>0:w>95}%0`<?1a92.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07pl9c083>1<729q/8>?53938Lg1c3Ah?m6*=c984b4=#;h31n;h4i3ab>5<<a;ii6=44i2`3>5<<g:3:6=44}c4`6?6=<3:1<v*;3080<4=Oj>n0Do:n;%0`<?1a92.8m44m6g9j6fg=831b>nl50;9j7g6=831d?4?50;9~f3e4290?6=4?{%605?5?:2Bi;i5Gb5c8 7e?2>l:7)=n9;`5b>o5kh0;66g=cc83>>o4j90;66a<9083>>{e>k?1<7o50;2x 1562:hj7El8d:Ja0d=]1>0:w>95}%0`<?1a82.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07pl9b583>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,;i36:h?;%1b=?d1n2.9i=4;;hc4>5<<am<1<75fa583>>i41>0;66a<9883>>o313:1(>7::5:8j6?32910e9950;&0=0<302d8594>;:k72?6=,:3>6964n2;7>7=<a=?1<7*<9487<>h41=0876g;4;29 6?22=20b>7;:598yg0e;3:1m7>50z&774<4jh1Cn:j4Hc6b?_?028q8;7s+2b:93c6<,:k26o8i;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vn;l=:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"5k10<j=5+3`;9f3`<,;o;695fa683>>oc>3:17do;:188k6?02900c>76:188m1?=83.8584;8:l0=1<732c?;7>5$2;6>1><f:3?6<54i5494?"41<0?46`<9581?>o3=3:1(>7::5:8j6?32:10e9:50;&0=0<302d8594;;:a2d`=83>1<7>t$512>6>63Ah<h6Fm4`9'6f>=?o:0(>o6:c4e?l4di3:17d<lb;29?l5e83:17b=61;29?xd1j90;694?:1y'067=;1;0Do9k;I`7e>"5k10<j=5+3`;9f3`<a;ij6=44i3aa>5<<a:h;6=44o2;2>5<<uk<i=7>54;294~"3;8084?5Gb6f8Lg2f3-8h479i0:&0e<<e>o1b>no50;9j6fd=831b?o>50;9l7<7=831vn;jn:18:>5<7s->8=7=m9:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa583>>of?3:17dj9:188k6?02900c>77:188yg0c:3:157>50z&774<4j01Cn:j4Hc6b?!4b8380e9>50;9j04<722c?>7>5;h60>5<<ah>1<75fa683>>oc>3:17b=67;29?j5>03:17pl8d483>1<729q/8>?536a8Lg1c3Ah?m6*=e182`>o5kh0;66g=cc83>>o5kj0;66a<9083>>{e>h:1<7:50;2x 15628n27El8d:Ja0d=#:j21;hk4$2c:>g173-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66sm6b294?2=83:p(9=>:0f:?Md0l2Bi8l5+2b:93c7<,:k26o9?;%0f4?7<a021<75fd783>>o41h0;66a<9683>>{e>ho1<7:50;2x 15628n27El8d:Ja0d=#:j21;k>4$2c:>g173-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66sm7e594?2=83:p(9=>:0f:?Md0l2Bi8l5+2d295>o>03:17dj9:188m6?f2900c>78:188yg1c>3:187>50z&774<6l01Cn:j4Hc6b?!4b83;0e4650;9j`3<722c85l4?::m0=2<722wi:4h50;694?6|,=9:6<j6;I`4`>Ne<h1/>h>51:k:<?6=3`n=6=44i2;b>5<<g:3<6=44}c4:a?6=<3:1<v*;3082`<=Oj>n0Do:n;%0f4?7<a021<75fd783>>o41h0;66a<9683>>{e?m>1<7;50;2x 15628nj7El8d:Ja0d=#:l:1=6g68;29?lg32900ei850;9j7<g=831d?4950;9~f2b>290>6=4?{%605?7ci2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44i2;b>5<<g:3<6=44}c5g<?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl85383>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi;9h50;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj>>i6=4::183!2493;om6Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188m6?f2900c>78:188yg13?3:197>50z&774<6lh1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;h1:e?6=3f92;7>5;|`406<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm72d94?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn:=m:186>5<7s->8=7?ka:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<a:3j6=44o2;4>5<<uk=8;7>55;294~"3;80:hl5Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?l5>i3:17b=67;29?xd0;:0;684?:1y'067=9mk0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::k0=d<722e85:4?::a37`=83?1<7>t$512>4bf3Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75f38c94?=h;0=1<75rb670>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk=><7>52;294~"3;808;l5Gb6f8Lg2f3-8n<7?l;h0`e?6=3f92=7>5;|`40f<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi;9650;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f22329096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo9;0;296?6=8r.??<4<7`9Kf2b<@k>j7)<j0;3`?l4di3:17b=61;29?xd0;j0;6?4?:1y'067=;>k0Do9k;I`7e>"5m90:o6g=c`83>>i4180;66sm72:94?4=83:p(9=>:25b?Md0l2Bi8l5+2d295f=n:jk1<75`38394?=zj>9?6=4=:183!24939<m6Fm7e9Kf1g<,;o;6<m4i3ab>5<<g:3:6=44}c504?6=:3:1<v*;30803d=Oj>n0Do:n;%0f4?7d3`8hm7>5;n1:5?6=3th<994?:283>5}#<:;1n:m4Hc5g?Md3i2cj:7>5;h142?6=3f92=7>5;|`40`<72=0;6=u+42397=6<@k=o7El;a:kb2?6=3`n<6=44i2`3>5<<g:=<6=44}c565?6=;3:1<v*;308a3f=Oj>n0Do:n;hc5>5<<a:==6=44o2;2>5<<uk=?m7>54;294~"3;8084=5Gb6f8Lg2f3`k=6=44ie594?=n;k:1<75`36594?=zj>>o6=4<:183!2493h<o6Fm7e9Kf1g<ah<1<75f36494?=h;0;1<75rb665>5<3290;w):<1;1;4>Ne?m1Cn9o4i`494?=nl>0;66g<b183>>i4?>0;66sm75;94?5=83:p(9=>:c5`?Md0l2Bi8l5fa783>>o4??0;66a<9083>>{e?=81<7:50;2x 1562:2;7El8d:Ja0d=ni?0;66gk7;29?l5e83:17b=87;29?xd0<<0;6>4?:1y'067=j>i0Do9k;I`7e>of>3:17d=86;29?j5>93:17pl83d83>1<729q/8>?53928Lg1c3Ah?m6gn6;29?lb02900e>l?:188k6102900qo9;1;297?6=8r.??<4m7b9Kf2b<@k>j7do9:188m6112900c>7>:188yg14i3:187>50z&774<4091Cn:j4Hc6b?lg12900ei950;9j7g6=831d?:950;9~f25c29086=4?{%605?d0k2Bi;i5Gb5c8md0=831b?:850;9l7<7=831vn:=9:187>5<7s->8=7=70:Ja3a=Oj=k0el850;9j`2<722c8n=4?::m032<722wi;>750;194?6|,=9:6o9l;I`4`>Ne<h1bm;4?::k033<722e85<4?::a364=83>1<7>t$512>6>73Ah<h6Fm4`9je3<722co;7>5;h1a4?6=3f9<;7>5;|`470<72:0;6=u+4239f2e<@k=o7El;a:kb2?6=3`9<:7>5;n1:5?6=3th<>h4?:583>5}#<:;1?5>4Hc5g?Md3i2cj:7>5;hf4>5<<a:h;6=44o254>5<<uk=8=7>53;294~"3;80i;n5Gb6f8Lg2f3`k=6=44i255>5<<g:3:6=44}c5:2?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl89283>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi;5h50;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj>2i6=4::183!2493;om6Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188m6?f2900c>78:188yg1??3:197>50z&774<6lh1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;h1:e?6=3f92;7>5;|`4<6<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm76d94?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn:9m:186>5<7s->8=7?ka:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<a:3j6=44o2;4>5<<uk=<;7>55;294~"3;80:hl5Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?l5>i3:17b=67;29?xd0?:0;684?:1y'067=9mk0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::k0=d<722e85:4?::a3<1=8381<7>t$512>61f3Ah<h6Fm4`9'6`6=9j1b>no50;9l7<7=831vn:7;:181>5<7s->8=7=8a:Ja3a=Oj=k0(?k?:0a8m7ef2900c>7>:188yg1>83:1>7>50z&774<4?h1Cn:j4Hc6b?!4b83;h7d<la;29?j5>93:17pl88b83>7<729q/8>?536c8Lg1c3Ah?m6*=e182g>o5kh0;66a<9083>>{e?121<7<50;2x 1562:=j7El8d:Ja0d=#:l:1=n5f2bc94?=h;0;1<75rb6:7>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk=3<7>52;294~"3;808;l5Gb6f8Lg2f3-8n<7?l;h0`e?6=3f92=7>5;|`43f<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi;:650;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f21329096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo968;297?6=8r.??<4m7b9Kf2b<@k>j7do9:188m6112900c>7>:188yg1>:3:187>50z&774<4091Cn:j4Hc6b?lg12900ei950;9j7g6=831d?:950;9~f2?229086=4?{%605?d0k2Bi;i5Gb5c8md0=831b?:850;9l7<7=831vn:6j:187>5<7s->8=7=70:Ja3a=Oj=k0el850;9j`2<722c8n=4?::m032<722wi;4?50;194?6|,=9:6o9l;I`4`>Ne<h1bm;4?::k033<722e85<4?::a3=g=83>1<7>t$512>6>73Ah<h6Fm4`9je3<722co;7>5;h1a4?6=3f9<;7>5;|`4<a<72:0;6=u+4239f2e<@k=o7El;a:kb2?6=3`9<:7>5;n1:5?6=3th<4;4?:583>5}#<:;1?5>4Hc5g?Md3i2cj:7>5;hf4>5<<a:h;6=44o254>5<<uk=357>53;294~"3;80i;n5Gb6f8Lg2f3`k=6=44i255>5<<g:3:6=44}c5;6?6=<3:1<v*;3080<5=Oj>n0Do:n;hc5>5<<am=1<75f3c294?=h;>=1<75rb6:6>5<4290;w):<1;`4g>Ne?m1Cn9o4i`494?=n;><1<75`38394?=zj>=n6=4;:183!249393<6Fm7e9Kf1g<ah<1<75fd683>>o4j90;66a<7683>>{e?1;1<7=50;2x 1562k=h7El8d:Ja0d=ni?0;66g<7783>>i4180;66sm76c94?2=83:p(9=>:2:3?Md0l2Bi8l5fa783>>oc?3:17d=m0;29?j50?3:17pl87e83>6<729q/8>?5b6a8Lg1c3Ah?m6gn6;29?l50>3:17b=61;29?xd0??0;694?:1y'067=;1:0Do9k;I`7e>of>3:17dj8:188m6d72900c>98:188yg1013:1?7>50z&774<e?j1Cn:j4Hc6b?lg12900e>99:188k6?62900qo982;290?6=8r.??<4<819Kf2b<@k>j7do9:188ma1=831b?o>50;9l721=831vn:9::180>5<7s->8=7l8c:Ja3a=Oj=k0el850;9j720=831d?4?50;9~f27>290?6=4?{%605?50k2Bi;i5Gb5c8 7c720k0e?mn:188m7ee2900e?ml:188k6?62900qo9>6;290?6=8r.??<4<7b9Kf2b<@k>j7)<j0;;b?l4di3:17d<lb;29?l4dk3:17b=61;29?xd09:0;694?:1y'067=;>i0Do9k;I`7e>"5m902m6g=c`83>>o5kk0;66g=cb83>>i4180;66sm70294?2=83:p(9=>:25`?Md0l2Bi8l5+2d29=d=n:jk1<75f2b`94?=n:ji1<75`38394?=zj>:o6=4;:183!24939<o6Fm7e9Kf1g<,;o;64o4i3ab>5<<a;ii6=44i3a`>5<<g:3:6=44}c53e?6=<3:1<v*;30803f=Oj>n0Do:n;%0f4??f3`8hm7>5;h0`f?6=3`8ho7>5;n1:5?6=3th<<:4?:583>5}#<:;1?:m4Hc5g?Md3i2.9i=46a:k1gd<722c9oo4?::k1gf<722e85<4?::a352=83>1<7>t$512>61d3Ah<h6Fm4`9'6`6=1h1b>no50;9j6fd=831b>nm50;9l7<7=831vn:>>:187>5<7s->8=7=8c:Ja3a=Oj=k0(?k?:8c8m7ef2900e?mm:188m7ed2900c>7>:188yg0am3:187>50z&774<4?j1Cn:j4Hc6b?!4b833j7d<la;29?l4dj3:17d<lc;29?j5>93:17pl8a583>6<729q/8>?536`8Lg1c3Ah?m6*=e180g>o5kh0;66g=cc83>>i4180;66sm7`194?5=83:p(9=>:25a?Md0l2Bi8l5+2d297f=n:jk1<75f2b`94?=h;0;1<75rb7d`>5<?290;w):<1;1a<>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je1<722cj;7>5;hf5>5<<g:3<6=44}c4e6?6=<3:1<v*;3082`0=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17b=67;29?xd1n80;694?:1y'067=9m?0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::m0=2<722wi:k>50;694?6|,=9:6<j:;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=h;0=1<75rb7ge>5<3290;w):<1;3g1>Ne?m1Cn9o4$3g3>4=n110;66gn4;29?lb12900c>78:188yg0bm3:187>50z&774<6l<1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;n1:3?6=3th=ii4?:583>5}#<:;1=i;4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fd783>>i41>0;66sm6g`94?2=83:p(9=>:0f6?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831d?4950;9~f3`f290?6=4?{%605?7c=2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44o2;4>5<<uk<m57>54;294~"3;80:h85Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?j5>?3:17pl9f983>1<729q/8>?51e78Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722e85:4?::a2c1=83>1<7>t$512>4b23Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75`38594?=zj?l=6=4;:183!2493;o96Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188k6?02900qo8i5;290?6=8r.??<4>d49Kf2b<@k>j7)<j0;38m<>=831bm94?::kg2?6=3f92;7>5;|`5b1<72=0;6=u+42395a3<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66a<9683>>{e>o91<7:50;2x 15628n>7El8d:Ja0d=#:l:1=6g68;29?lg32900ei850;9l7<1=831vn;kl:187>5<7s->8=7?k5:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<g:3<6=44}c52<?6=<3:1<v*;3082`<=Oj>n0Do:n;%0f4?7<a021<75fd783>>o41h0;66a<9683>>{e?8k1<7:50;2x 15628n27El8d:Ja0d=#:l:1=6g68;29?lb12900e>7n:188k6?02900qo9>5;290?6=8r.??<4>d89Kf2b<@k>j7)<j0;38m<>=831bh;4?::k0=d<722e85:4?::a341=83>1<7>t$512>4b>3Ah<h6Fm4`9'6`6=92c247>5;hf5>5<<a:3j6=44o2;4>5<<uk=:>7>54;294~"3;80:h45Gb6f8Lg2f3-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66sm70694?2=83:p(9=>:0f:?Md0l2Bi8l5+2d295>o>03:17dj9:188m6?f2900c>78:188yg17n3:187>50z&774<6l01Cn:j4Hc6b?!4b83;0e4650;9j`3<722c85l4?::m0=2<722wi;<?50;694?6|,=9:6<j6;I`4`>Ne<h1/>h>51:k:<?6=3`n=6=44i2;b>5<<g:3<6=44}c53g?6=<3:1<v*;3082`<=Oj>n0Do:n;%0f4?7<a021<75fd783>>o41h0;66a<9683>>{e?9o1<7:50;2x 15628n27El8d:Ja0d=#:l:1=6g68;29?lb12900e>7n:188k6?02900qo9?9;290?6=8r.??<4>d89Kf2b<@k>j7)<j0;38m<>=831bh;4?::k0=d<722e85:4?::a35d=83>1<7>t$512>4b>3Ah<h6Fm4`9'6`6=92c247>5;hf5>5<<a:3j6=44o2;4>5<<uk=;:7>54;294~"3;80:h45Gb6f8Lg2f3-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66sm71:94?2=83:p(9=>:0f:?Md0l2Bi8l5+2d295>o>03:17dj9:188m6?f2900c>78:188yg17;3:187>50z&774<6l01Cn:j4Hc6b?!4b83;0e4650;9j`3<722c85l4?::m0=2<722wi;=;50;694?6|,=9:6<j6;I`4`>Ne<h1/>h>51:k:<?6=3`n=6=44i2;b>5<<g:3<6=44}c534?6=<3:1<v*;3082`<=Oj>n0Do:n;%0f4?7<a021<75fd783>>o41h0;66a<9683>>{e?981<7:50;2x 15628n27El8d:Ja0d=#:l:1=6g68;29?lb12900e>7n:188k6?02900qo8id;290?6=8r.??<4>d89Kf2b<@k>j7)<j0;38m<>=831bh;4?::k0=d<722e85:4?::a2c`=83>1<7>t$512>4b>3Ah<h6Fm4`9'6`6=92c247>5;hf5>5<<a:3j6=44o2;4>5<<uk=j97>51081>44|@k>j7):<1;`;=>\>?3;p=?4r$c6a>1573`8h97>5$2;6>7e33g9287>4;h0a=?6=,:3>6?m;;o1:0?7<3`8ji7>5$2;6>7e33g9287<4;h0b7?6=,:3>6?m;;o1:0?5<3`8247>5$2;6>7e33g9287:4;h0;`?6=,:3>6?m;;o1:0?3<3`83>7>5$2;6>7e33g928784;h043?6=,:3>6?m;;o1:0?1<3`8>;7>5$2;6>7e33g928764;h3f<?6=,:3>6?m;;o1:0??<3`kh6=44i2c;>5<<a:n:6=44i2f3>5<<a:n96=44o2f0>5<<g;i=6=44bc5e>5<6290;w):<1;`60>Ne?m1Cn9o4o2;1>5<<uk9=;7>51b8a>71|@k>j7):<1;`;`>\>?3;p=h4r$3a;>2g13`9h:7>5$2;6>6e23g9287>4;h1`0?6=,:3>6>m:;o1:0?7<3`9h?7>5$2;6>6e23g9287<4;h1`6?6=,:3>6>m:;o1:0?5<3`9h=7>5$2;6>6e23g9287:4;h1`4?6=,:3>6>m:;o1:0?3<3`9ij7>5$2;6>6e23g928784;h1aa?6=,:3>6>m:;o1:0?1<3`9ih7>5$2;6>6e23g928764;h1ag?6=,:3>6>m:;o1:0??<3`9hj7>5$2;6>6e23g9287o4;h1`a?6=,:3>6>m:;o1:0?d<3`9hh7>5$2;6>6e23g9287m4;h1`g?6=,:3>6>m:;o1:0?b<3`9hn7>5$2;6>6e23g9287k4;h1`e?6=,:3>6>m:;o1:0?`<3`9h57>5$2;6>6e23g9287??;:k0g=<72-9297=l5:l0=1<6921b?n950;&0=0<4k<1e?4:51398m6de290/?4;53b78j6?328907dol:188m6g?2900e<k9:188m6b62900e>j?:188m6b52900c>j<:188k7e12900no9i:182>5<7s->8=7l:4:Ja3a=Oj=k0c>7=:188ygd0m3:1=7>50z&774<5k>1Cn:j4Hc6b?j7b=3:17plm4b83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xde=:0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g0a3-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg35290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a2c=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a14<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c4e?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc73>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm4e83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xde<o0;694?:1y'067=;1:0Do9k;I`7e>"4i00i:k5fa783>>oc?3:17d=m0;29?j50?3:17plm4d83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xd4>?0;694?:1y'067=;1:0Do9k;I`7e>"4i00i;=5fa783>>oc?3:17d=m0;29?j50?3:17p}>e783>7}Y9l<01o:l:`48yv4d>3:1>vP=c79>730=;>=0q~=75;296~;e?o085?5237497g6<uz93:7>56z?a3`<6m<16n9m5d69>f1b=l>16n9h5d69>f1c=l>16?;85d69~w6de2909wS=mb:?a15<3<2wx?om50;0xZ6dd34h>>7:;;|q0fa<72;qU?oj4=c71>13<uz9ii7>52z\0f`=:j<818;5rs2`e>5<5sW9ij63m53873>{t;j:1<7<t^2a3?8d2:3>27p}<c083>7}Y;j;01o;<:568yv5d:3:1>vP<c39>f05=<<1v>m<:181[5d;27i9>4;6:p7f2=838pR>m;;<`67?203ty8o;4?:3y]7f0<5k?86974}r1`3?6=:rT8o:52b42900=z{:i36=4={_1`<>;e=90?:6s|3b;94?4|V:i270l:0;64?xu4kh0;6?uQ3bc89g372=30q~=lb;296~X4kk16n8?5459~w6ed2909wS=lc:?a14<3=2wx?nj50;0xZ6ec34h>=7:9;|q0g`<72;qU?nk4=c72>11<uz9hj7>52z\0gc=:j<;1845rs2f3>5<2sW9o<63m528b0>;e=;0j863m508b0>;e=90j86s|3e394?3|V:n:70l:3;c4?8d2:3k<70l:1;c4?8d283k<7p}<d383>7}Y;m801o;<:e48yv5c;3:1>vP<d29>f06=;030q~ln8;296~;e=8085452b429`3=z{kk26=4={<`66?5>127i9<4k6:pfdg=838p1o;<:2;:?8d2:3n=7p}mac83>7}:j=i1?:94=c6g>d0<uzhjo7>52z?a0a<4?>16n9k5a79~wggc2909w0l;f;c5?8d3m39<;6s|b`g94?4|5k>m6>98;<152?g13tyin=4?:3y>f1e=;k:01o;?:2;4?xuej80;6?u2b4397<1<5k>o6>l?;|qaf7<72;q6n8<538589g2b2:h;7p}mb283>7}:j<91?494=c6e>6d73twxmn4?:3y]ef=:;?=1mn5rs0g;>5<5sW;n463<6680fg=z{;?<6=4={_063>;4>>08o:5rs354>5<5sW8<;63<6680g==z{;296=4={_0;6>;4>>08o45rs3:g>5<5sW83h63<6680gd=z{;336=4={_0:<>;4>>08oo5rs3c0>5<5sW8j?63<6680gf=z{;kn6=4={_0ba>;4>>08oi5rs3`:>5<5sW8i563<6680g`=z{;i>6=4={_0`1>;4>>08ok5rs3a5>5<5sW8h:63<6681g3=z{:k36=4={_1b<>;4>>08m55rs2f3>5<5sW9o<63<6680`5=z{:n:6=4={_1g5>;4>>08h<5rs2f1>5<5sW9o>63<6680`7=z{:n86=4={_1g7>;4>>08h>5rsc;5>5<ds4h<j7=62:?022<4k?16?;953b6896002:i870=97;1`6>;4>>08o<5237597f6<5:<<6>li;<153?5em278::4<be9>731=;ki01>88:0g5?x{e?h=1<7?>:3826~Ne<h1/8>?5b9;8^<1=9r;96p*m4c8775=n:j?1<7*<9481g1=i;0>1<65f2c;94?"41<09o95a38695>=n:ho1<7*<9481g1=i;0>1>65f2`194?"41<09o95a38697>=n:021<7*<9481g1=i;0>1865f29f94?"41<09o95a38691>=n:181<7*<9481g1=i;0>1:65f26594?"41<09o95a38693>=n:<=1<7*<9481g1=i;0>1465f1d:94?"41<09o95a3869=>=nij0;66g<a983>>o4l80;66g<d183>>o4l;0;66a<d283>>i5k?0;66lm7g83>4<729q/8>?5b468Lg1c3Ah?m6a<9383>>{e;?=1<7?l:c813~Ne<h1/8>?5b9f8^<1=9r;n6p*=c984e==n;j<1<7*<9480g0=i;0>1<65f3b694?"41<08o85a38695>=n;j91<7*<9480g0=i;0>1>65f3b094?"41<08o85a38697>=n;j;1<7*<9480g0=i;0>1865f3b294?"41<08o85a38691>=n;kl1<7*<9480g0=i;0>1:65f3cg94?"41<08o85a38693>=n;kn1<7*<9480g0=i;0>1465f3ca94?"41<08o85a3869=>=n;jl1<7*<9480g0=i;0>1m65f3bg94?"41<08o85a3869f>=n;jn1<7*<9480g0=i;0>1o65f3ba94?"41<08o85a3869`>=n;jh1<7*<9480g0=i;0>1i65f3bc94?"41<08o85a3869b>=n;j31<7*<9480g0=i;0>1==54i2a;>5<#;0?1?n;4n2;7>47<3`9h;7>5$2;6>6e23g9287?=;:k0fg<72-9297=l5:l0=1<6;21bmn4?::k0e=<722c:i;4?::k0`4<722c8h=4?::k0`7<722e8h>4?::m1g3<722hi;k4?:083>5}#<:;1n8:4Hc5g?Md3i2e85?4?::af2c=83;1<7>t$512>7e03Ah<h6Fm4`9l5`3=831vno:l:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c4e?lg12900ei950;9j7g6=831d?:950;9~fg34290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a2c=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a17<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c4e?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc72>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm5183>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o8i;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno:k:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c4e?lg12900ei950;9j7g6=831d?:950;9~fg2a290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k<m7do9:188ma1=831b?o>50;9l721=831vno:j:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c4e?lg12900ei950;9j7g6=831d?:950;9~f601290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k=;7do9:188ma1=831b?o>50;9l721=831v<k9:181[7b>27i8n4n6:p6f0=838pR?m9;<152?50?2wx?5;50;0x9g1a2:3970=96;1a4>{t;1<1<78t=c5f>4c234h?o7j8;<`7`?b034h?j7j8;<`7a?b0349=:7j8;|q0fg<72;qU?ol4=c73>12<uz9io7>52z\0ff=:j<81895rs2`g>5<5sW9ih63m53871>{t;ko1<7<t^2`f?8d2:3>=7p}<bg83>7}Y;kl01o;=:558yv5d83:1>vP<c19>f04=<01v>m>:181[5d927i9>4;4:p7f4=838pR>m=;<`67?223ty8o>4?:3y]7f5<5k?86984}r1`0?6=:rT8o952b41902=z{:i=6=4={_1`2>;e=:0?56s|3b594?4|V:i<70l:0;66?xu4k10;6?uQ3b:89g372=<0q~=l9;296~X4k016n8>5469~w6ef2909wS=la:?a15<312wx?nl50;0xZ6ee34h>=7:;;|q0gf<72;qU?nm4=c72>13<uz9hh7>52z\0ga=:j<;18;5rs2af>5<5sW9hi63m50873>{t;jl1<7<t^2ae?8d293>27p}<d183>0}Y;m:01o;<:`689g352h>01o;>:`689g372h>0q~=k1;291~X4l816n8=5a69>f04=i>16n8?5a69>f06=i>1v>j=:181[5c:27i9>4k6:p7a5=838pR>j<;<`64?5>12wxnl650;0x9g362:3270l:0;f5?xuei00;6?u2b4097<?<5k?:6i84}r`be?6=:r7i9>4<989>f04=l?1voom:1818d3k39<;63m4e8b2>{tjhi1<7<t=c6g>61034h?i7o9;|qaea<72;q6n9h5a79>f1c=;>=0q~lne;296~;e<o08;:523749e3=z{kh;6=4={<`7g?5e827i9=4<969~wgd62909w0l:1;1:3>;e<m08n=5rsc`1>5<5s4h>>7=67:?a0`<4j91vol<:1818d2;392;63m4g80f5=zuzkh6=4={_c`?851?3kh7p}>e983>7}Y9l201>88:2`a?xu5=>0;6?uQ245896002:i<7p}=7683>7}Y:>=01>88:2a;?xu50;0;6?uQ290896002:i27p}=8e83>7}Y:1n01>88:2ab?xu5110;6?uQ28:896002:ii7p}=a283>7}Y:h901>88:2a`?xu5il0;6?uQ2`g896002:io7p}=b883>7}Y:k301>88:2af?xu5k<0;6?uQ2b7896002:im7p}=c783>7}Y:j<01>88:3a5?xu4i10;6?uQ3`:896002:k37p}<d183>7}Y;m:01>88:2f3?xu4l80;6?uQ3e3896002:n:7p}<d383>7}Y;m801>88:2f1?xu4l:0;6?uQ3e1896002:n87p}m9783>f}:j>l1?4<4=244>6e1349=;7=l4:?022<4k:16?;953b0896002:i:70=97;1`4>;4>>08nk5237597gc<5:<<6>lk;<153?5ek278::4>e79~yg1f13:1=<4=:00xLg2f3->8=7l79:X:3?7|9;0v(o:m:513?l4d=3:1(>7::3a7?k5><3:07d<m9;29 6?22;i?7c=64;38?l4fm3:1(>7::3a7?k5><3807d<n3;29 6?22;i?7c=64;18?l4>03:1(>7::3a7?k5><3>07d<7d;29 6?22;i?7c=64;78?l4?:3:1(>7::3a7?k5><3<07d<87;29 6?22;i?7c=64;58?l42?3:1(>7::3a7?k5><3207d?j8;29 6?22;i?7c=64;;8?lgd2900e>o7:188m6b62900e>j?:188m6b52900c>j<:188k7e12900no9i:182>5<7s->8=7l:4:Ja3a=Oj=k0c>7=:188yg51?3:1=n4m:35xLg2f3->8=7l7d:X:3?7|9l0v(?m7:6cb?l5d>3:1(>7::2a6?k5><3:07d=l4;29 6?22:i>7c=64;38?l5d;3:1(>7::2a6?k5><3807d=l2;29 6?22:i>7c=64;18?l5d93:1(>7::2a6?k5><3>07d=l0;29 6?22:i>7c=64;78?l5en3:1(>7::2a6?k5><3<07d=me;29 6?22:i>7c=64;58?l5el3:1(>7::2a6?k5><3207d=mc;29 6?22:i>7c=64;;8?l5dn3:1(>7::2a6?k5><3k07d=le;29 6?22:i>7c=64;`8?l5dl3:1(>7::2a6?k5><3i07d=lc;29 6?22:i>7c=64;f8?l5dj3:1(>7::2a6?k5><3o07d=la;29 6?22:i>7c=64;d8?l5d13:1(>7::2a6?k5><3;;76g<c983>!5>=39h96`<95825>=n;j=1<7*<9480g0=i;0>1=?54i2`a>5<#;0?1?n;4n2;7>45<3`kh6=44i2c;>5<<a8o=6=44i2f2>5<<a:n;6=44i2f1>5<<g:n86=44o3a5>5<<jk=m6=4>:183!2493h>86Fm7e9Kf1g<g:396=44}c`4a?6=93:1<v*;3081g2=Oj>n0Do:n;n3f1?6=3thi8n4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m6g9je3<722co;7>5;h1a4?6=3f9<;7>5;|`a16<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c4e?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc71>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm5083>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o8i;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno;?:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"4i00i:k5+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3thi8i4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m6g9je3<722co;7>5;h1a4?6=3f9<;7>5;|`a0c<72=0;6=u+42397=6<@k=o7El;a:&0e<<e>o1bm;4?::kg3?6=3`9i<7>5;n143?6=3thi8h4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m6g9je3<722co;7>5;h1a4?6=3f9<;7>5;|`023<72=0;6=u+42397=6<@k=o7El;a:&0e<<e?91bm;4?::kg3?6=3`9i<7>5;n143?6=3ty:i;4?:3y]5`0<5k>h6l84}r0`2?6=:rT9o;523749721<uz9397>52z?a3c<41;16?;853c28yv5?>3:1:v3m7d82a0=:j=i1h:52b5f9`2=:j=l1h:52b5g9`2=:;?<1h:5rs2`a>5<5sW9in63m51870>{t;ki1<7<t^2``?8d2:3>?7p}<be83>7}Y;kn01o;=:578yv5em3:1>vP<bd9>f04=<?1v>li:181[5en27i9?4;7:p7f6=838pR>m?;<`66?2>3ty8o<4?:3y]7f7<5k?869:4}r1`6?6=:rT8o?52b41900=z{:i86=4={_1`7>;e=:0?:6s|3b694?4|V:i?70l:3;64?xu4k?0;6?uQ3b489g342=30q~=l7;296~X4k>16n8>5449~w6e?2909wS=l8:?a15<3>2wx?n750;0xZ6e>34h><7:8;|q0gd<72;qU?no4=c73>1?<uz9hn7>52z\0gg=:j<;1895rs2a`>5<5sW9ho63m50871>{t;jn1<7<t^2ag?8d293>=7p}<cd83>7}Y;jo01o;>:558yv5dn3:1>vP<cg9>f07=<01v>j?:186[5c827i9>4n4:?a17<f<27i9<4n4:?a15<f<2wx?i?50;7xZ6b634h>?7o8;<`66?g034h>=7o8;<`64?g03ty8h?4?:3y]7a4<5k?86i84}r1g7?6=:rT8h>52b4297<?<uzhj47>52z?a14<41016n8>5d79~wgg>2909w0l:2;1:=>;e=80o:6s|b`c94?4|5k?86>76;<`66?b13tyimo4?:3y>f1e=;>=01o:k:`48yvdfk3:1>v3m4e8032=:j=o1m;5rsccg>5<5s4h?j7o9;<`7a?50?2wxnlk50;0x9g2a2:=<70=96;c5?xuej90;6?u2b5a97g6<5k?;6>78;|qaf4<72;q6n8?538589g2c2:h;7p}mb383>7}:j<81?494=c6f>6d73tyin>4?:3y>f05=;0=01o:i:2`3?x{tij0;6?uQab9>731=ij1v<k7:181[7b0278::4<bc9~w7302909wS<:7:?022<4k>1v?98:181[40?278::4<c99~w7>52909wS<72:?022<4k01v?6k:181[4?l278::4<c`9~w7??2909wS<68:?022<4kk1v?o<:181[4f;278::4<cb9~w7gb2909wS<ne:?022<4km1v?l6:181[4e1278::4<cd9~w7e22909wS<l5:?022<4ko1v?m9:181[4d>278::4=c79~w6g?2909wS=n8:?022<4i11v>j?:181[5c8278::4<d19~w6b62909wS=k1:?022<4l81v>j=:181[5c:278::4<d39~w6b42909wS=k3:?022<4l:1vo79:18`8d0n392>63<6680g3=:;?=1?n:4=244>6e4349=;7=l2:?022<4k816?;953b2896002:hm70=97;1aa>;4>>08ni5237597ge<5:<<6<k9;|a126=83=1<7>t$512>61a3Ah<h6Fm4`9'6`6=02c9ol4?::k1gg<722c9on4?::k1ga<722c9oh4?::k1gc<722e85<4?::a1<g=8391<7>t$512>61e3Ah<h6Fm4`9'6`6=9j90e?mn:188m7ee2900c>7>:188yg34<3:1;7>50z&774<4?o1Cn:j4Hc6b?!4b83=0e?mn:188m7ee2900e?ml:188m7ec2900e?mj:188m7ea2900c>7>:188yg31n3:1?7>50z&774<4?k1Cn:j4Hc6b?!4b83;h?6g=c`83>>o5kk0;66a<9083>>{e=:?1<7<50;2x 1562:=j7El8d:Ja0d=#:l:1=n5f2bc94?=h;0;1<75rb410>5<4290;w):<1;14f>Ne?m1Cn9o4$3g3>6e<a;ij6=44i3aa>5<<g:3:6=44}c705?6=;3:1<v*;30803g=Oj>n0Do:n;%0f4?7d;2c9ol4?::k1gg<722e85<4?::a164=8391<7>t$512>61e3Ah<h6Fm4`9'6`6=9j90e?mn:188m7ee2900c>7>:188yg3f<3:1;7>50z&774<4?o1Cn:j4Hc6b?!4b83;:7d<la;29?l4dj3:17d<lc;29?l4dl3:17d<le;29?l4dn3:17b=61;29?xd2i<0;6:4?:1y'067=;>l0Do9k;I`7e>"5m90:=6g=c`83>>o5kk0;66g=cb83>>o5km0;66g=cd83>>o5ko0;66a<9083>>{e=h<1<7950;2x 1562:=m7El8d:Ja0d=#:l:1=<5f2bc94?=n:jh1<75f2ba94?=n:jn1<75f2bg94?=n:jl1<75`38394?=zj<k36=48:183!24939<j6Fm7e9Kf1g<,;o;6<?4i3ab>5<<a;ii6=44i3a`>5<<a;io6=44i3af>5<<a;im6=44o2;2>5<<uk?i=7>57;294~"3;808;k5Gb6f8Lg2f3-8n<7?l9:k1gd<722c9oo4?::k1gf<722c9oi4?::k1g`<722c9ok4?::m0=4<722wi9l950;594?6|,=9:6>9i;I`4`>Ne<h1/>h>5109j6fg=831b>nl50;9j6fe=831b>nj50;9j6fc=831b>nh50;9l7<7=831vn8o6:184>5<7s->8=7=8f:Ja3a=Oj=k0(?k?:038m7ef2900e?mm:188m7ed2900e?mk:188m7eb2900e?mi:188k6?62900qo;na;293?6=8r.??<4<7g9Kf2b<@k>j7)<j0;32?l4di3:17d<lb;29?l4dk3:17d<ld;29?l4dm3:17d<lf;29?j5>93:17pl:ab83>2<729q/8>?536d8Lg1c3Ah?m6*=e1825>o5kh0;66g=cc83>>o5kj0;66g=ce83>>o5kl0;66g=cg83>>i4180;66sm5c194?1=83:p(9=>:25e?Md0l2Bi8l5+2d295f?<a;ij6=44i3aa>5<<a;ih6=44i3ag>5<<a;in6=44i3ae>5<<g:3:6=44}c7a4?6=<3:1<v*;3080<4=Oj>n0Do:n;h0`e?6=3`8hn7>5;h1a4?6=3f92=7>5;|`6eg<72>0;6=u+423972`<@k=o7El;a:&1a5<692c9ol4?::k1gg<722c9on4?::k1ga<722c9oh4?::k1gc<722e85<4?::a1db=83=1<7>t$512>61a3Ah<h6Fm4`9'6`6=981b>no50;9j6fd=831b>nm50;9j6fb=831b>nk50;9j6f`=831d?4?50;9~f0gb290<6=4?{%605?50n2Bi;i5Gb5c8 7c728;0e?mn:188m7ee2900e?ml:188m7ec2900e?mj:188m7ea2900c>7>:188yg3fn3:187>50z&774<4?j1Cn:j4Hc6b?!4b83;o=6g=c`83>>o5kk0;66g=cb83>>i4180;66sm5c694?1=83:p(9=>:25e?Md0l2Bi8l5+2d295f?<a;ij6=44i3aa>5<<a;ih6=44i3ag>5<<a;in6=44i3ae>5<<g:3:6=44}c7a6?6=<3:1<v*;3080<4=Oj>n0Do:n;h0`e?6=3`8hn7>5;h1a4?6=3f92=7>5;|`6e5<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm58d94?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn87j:186>5<7s->8=7?ka:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<a:3j6=44o2;4>5<<uk?2h7>55;294~"3;80:hl5Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?l5>i3:17b=67;29?xd21j0;684?:1y'067=9mk0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::k0=d<722e85:4?::a1<d=83?1<7>t$512>4bf3Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75f38c94?=h;0=1<75rb4ag>5<4290;w):<1;`4g>Ne?m1Cn9o4i`494?=n;><1<75`38394?=zj<ij6=4;:183!249393<6Fm7e9Kf1g<ah<1<75fd683>>o4j90;66a<7683>>{e=m>1<7=50;2x 1562k=h7El8d:Ja0d=ni?0;66g<7783>>i4180;66sm5e394?2=83:p(9=>:2:3?Md0l2Bi8l5fa783>>oc?3:17d=m0;29?j50?3:17pl:d983>6<729q/8>?5b6a8Lg1c3Ah?m6gn6;29?l50>3:17b=61;29?xd2l<0;694?:1y'067=;1:0Do9k;I`7e>of>3:17dj8:188m6d72900c>98:188yg3ck3:1?7>50z&774<e?j1Cn:j4Hc6b?lg12900e>99:188k6?62900qo;k9;290?6=8r.??<4<819Kf2b<@k>j7do9:188ma1=831b?o>50;9l721=831vn8k?:180>5<7s->8=7l8c:Ja3a=Oj=k0el850;9j720=831d?4?50;9~f0bc290?6=4?{%605?5?82Bi;i5Gb5c8md0=831bh:4?::k0f5<722e8;:4?::a1`2=8391<7>t$512>g1d3Ah<h6Fm4`9je3<722c8;;4?::m0=4<722wi9h?50;694?6|,=9:6>6?;I`4`>Ne<h1bm;4?::kg3?6=3`9i<7>5;n143?6=3th>i54?:283>5}#<:;1n:m4Hc5g?Md3i2cj:7>5;h142?6=3f92=7>5;|`6a0<72=0;6=u+42397=6<@k=o7El;a:kb2?6=3`n<6=44i2`3>5<<g:=<6=44}c7fg?6=;3:1<v*;308a3f=Oj>n0Do:n;hc5>5<<a:==6=44o2;2>5<<uk?n57>54;294~"3;8084=5Gb6f8Lg2f3`k=6=44ie594?=n;k:1<75`36594?=zj<l;6=4<:183!2493h<o6Fm7e9Kf1g<ah<1<75f36494?=h;0;1<75rb4gg>5<3290;w):<1;1;4>Ne?m1Cn9o4i`494?=nl>0;66g<b183>>i4?>0;66sm5g694?5=83:p(9=>:c5`?Md0l2Bi8l5fa783>>o4??0;66a<9083>>{e=o;1<7:50;2x 1562:2;7El8d:Ja0d=ni?0;66gk7;29?l5e83:17b=87;29?xd2l90;6>4?:1y'067=j>i0Do9k;I`7e>of>3:17d=86;29?j5>93:17pl:cb83>7<729q/8>?536c8Lg1c3Ah?m6*=e182g>o5kh0;66a<9083>>{e=m91<7<50;2x 1562:=j7El8d:Ja0d=#:l:1=n5f2bc94?=h;0;1<75rb4f4>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk?on7>52;294~"3;808;l5Gb6f8Lg2f3-8n<7?l;h0`e?6=3f92=7>5;|`6`c<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi9h=50;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f0c029096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo;jb;296?6=8r.??<4<7`9Kf2b<@k>j7)<j0;3`?l4di3:17b=61;29?xd2mo0;6?4?:1y'067=;>k0Do9k;I`7e>"5m90:o6g=c`83>>i4180;66sm5g194?4=83:p(9=>:25b?Md0l2Bi8l5+2d295f=n:jk1<75`38394?=zj<im6=4=:183!24939<m6Fm7e9Kf1g<,;o;6<m4i3ab>5<<g:3:6=44}c7`f?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl:d383>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi9i850;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj<nj6=4::183!2493;om6Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188m6?f2900c>78:188yg3cm3:197>50z&774<6lh1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;h1:e?6=3f92;7>5;|`6a7<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm5d494?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn8kn:186>5<7s->8=7?ka:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<a:3j6=44o2;4>5<<uk?ni7>55;294~"3;80:hl5Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?l5>i3:17b=67;29?xd2n;0;684?:1y'067=9mk0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::k0=d<722e85:4?::a1fc=83?1<7>t$512>4bf3Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75f38c94?=h;0=1<75rb473>5<4290;w):<1;`4g>Ne?m1Cn9o4i`494?=n;><1<75`38394?=zj<>o6=4;:183!249393<6Fm7e9Kf1g<ah<1<75fd683>>o4j90;66a<7683>>{e=<>1<7=50;2x 1562k=h7El8d:Ja0d=ni?0;66g<7783>>i4180;66sm54394?2=83:p(9=>:2:3?Md0l2Bi8l5fa783>>oc?3:17d=m0;29?j50?3:17pl:5983>6<729q/8>?5b6a8Lg1c3Ah?m6gn6;29?l50>3:17b=61;29?xd2=<0;694?:1y'067=;1:0Do9k;I`7e>of>3:17dj8:188m6d72900c>98:188yg32k3:1?7>50z&774<e?j1Cn:j4Hc6b?lg12900e>99:188k6?62900qo;:9;290?6=8r.??<4<819Kf2b<@k>j7do9:188ma1=831b?o>50;9l721=831vn88?:180>5<7s->8=7l8c:Ja3a=Oj=k0el850;9j720=831d?4?50;9~f03c290?6=4?{%605?5?82Bi;i5Gb5c8md0=831bh:4?::k0f5<722e8;:4?::a132=8391<7>t$512>g1d3Ah<h6Fm4`9je3<722c8;;4?::m0=4<722wi9;?50;694?6|,=9:6>6?;I`4`>Ne<h1bm;4?::kg3?6=3`9i<7>5;n143?6=3th>::4?:283>5}#<:;1n:m4Hc5g?Md3i2cj:7>5;h142?6=3f92=7>5;|`60c<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi98=50;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f03029096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo;:b;296?6=8r.??<4<7`9Kf2b<@k>j7)<j0;3`?l4di3:17b=61;29?xd2=o0;6?4?:1y'067=;>k0Do9k;I`7e>"5m90:o6g=c`83>>i4180;66sm57194?4=83:p(9=>:25b?Md0l2Bi8l5+2d295f=n:jk1<75`38394?=zj<<=6=4=:183!24939<m6Fm7e9Kf1g<,;o;6<m4i3ab>5<<g:3:6=44}c77a?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl:5383>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi98850;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj<?j6=4::183!2493;om6Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188m6?f2900c>78:188yg32m3:197>50z&774<6lh1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;h1:e?6=3f92;7>5;|`627<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm57794?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn86?:180>5<7s->8=7l8c:Ja3a=Oj=k0el850;9j720=831d?4?50;9~f01c290?6=4?{%605?5?82Bi;i5Gb5c8md0=831bh:4?::k0f5<722e8;:4?::a1=2=8391<7>t$512>g1d3Ah<h6Fm4`9je3<722c8;;4?::m0=4<722wi95?50;694?6|,=9:6>6?;I`4`>Ne<h1bm;4?::kg3?6=3`9i<7>5;n143?6=3th>454?:283>5}#<:;1n:m4Hc5g?Md3i2cj:7>5;h142?6=3f92=7>5;|`6<0<72=0;6=u+42397=6<@k=o7El;a:kb2?6=3`n<6=44i2`3>5<<g:=<6=44}c7;g?6=;3:1<v*;308a3f=Oj>n0Do:n;hc5>5<<a:==6=44o2;2>5<<uk?357>54;294~"3;8084=5Gb6f8Lg2f3`k=6=44ie594?=n;k:1<75`36594?=zj<3;6=4<:183!2493h<o6Fm7e9Kf1g<ah<1<75f36494?=h;0;1<75rb4:g>5<3290;w):<1;1;4>Ne?m1Cn9o4i`494?=nl>0;66g<b183>>i4?>0;66sm58194?5=83:p(9=>:c5`?Md0l2Bi8l5fa783>>o4??0;66a<9083>>{e=>l1<7<50;2x 1562:=j7El8d:Ja0d=#:l:1=n5f2bc94?=h;0;1<75rb4:0>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk?3;7>52;294~"3;808;l5Gb6f8Lg2f3-8n<7?l;h0`e?6=3f92=7>5;|`6<g<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi95h50;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f0?529096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo;8e;291?6=8r.??<4>d`9Kf2b<@k>j7)<j0;38m<>=831bm94?::kg2?6=3`92m7>5;n1:3?6=3th>4?4?:483>5}#<:;1=io4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fd783>>o41h0;66a<9683>>{e=1<1<7;50;2x 15628nj7El8d:Ja0d=#:l:1=6g68;29?lg32900ei850;9j7<g=831d?4950;9~f0>f290>6=4?{%605?7ci2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44i2;b>5<<g:3<6=44}c7;a?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl:9083>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi49850;694?6|,=9:6>9l;I`4`>Ne<h1/>h>51b68m7ef2900e?mm:188m7ed2900c>7>:188yg0213:187>50z&774<4?j1Cn:j4Hc6b?!4b838:7d<la;29?l4dj3:17d<lc;29?j5>93:17pl78`83>3<729q/8>?536g8Lg1c3Ah?m6*=e180e>o5kh0;66g=cc83>>o5kj0;66g=ce83>>o5kl0;66a<9083>>{e0>91<7950;2x 1562:=m7El8d:Ja0d=#:l:1?o5f2bc94?=n:jh1<75f2ba94?=n:jn1<75f2bg94?=n:jl1<75`38394?=zj1=n6=48:183!24939<j6Fm7e9Kf1g<,;o;6>l4i3ab>5<<a;ii6=44i3a`>5<<a;io6=44i3af>5<<a;im6=44o2;2>5<<uk2387>57;294~"3;808;k5Gb6f8Lg2f3-8n<7=m;h0`e?6=3`8hn7>5;h0`g?6=3`8hh7>5;h0`a?6=3`8hj7>5;n1:5?6=3th34o4?:783>5}#<:;1?:k4Hc5g?Md3i2.9i=4>e39j6fg=831b>nl50;9j6fe=831b>nj50;9j6fc=831d?4?50;9~f=16290=6=4?{%605?50m2Bi;i5Gb5c8 7c72090e?mn:188m7ee2900e?ml:188m7ec2900e?mj:188k6?62900qo682;293?6=8r.??<4<7g9Kf2b<@k>j7)<j0;3g`>o5kh0;66g=cc83>>o5kj0;66g=ce83>>o5kl0;66g=cg83>>i4180;66sm86694?5=83:p(9=>:25a?Md0l2Bi8l5+2d295f5<a;ij6=44i3aa>5<<g:3:6=44}c:41?6=?3:1<v*;30803c=Oj>n0Do:n;%0f4?2e3`8hm7>5;h0`f?6=3`8ho7>5;h0``?6=3`8hi7>5;h0`b?6=3f92=7>5;|`;32<72<0;6=u+423972b<@k=o7El;a:&1a5<3k2c9ol4?::k1gg<722c9on4?::k1ga<722e85<4?::a<2>=83=1<7>t$512>61a3Ah<h6Fm4`9'6`6=1?1b>no50;9j6fd=831b>nm50;9j6fb=831b>nk50;9j6f`=831d?4?50;9~f=1>290>6=4?{%605?50l2Bi;i5Gb5c8 7c728i37d<la;29?l4dj3:17d<lc;29?l4dl3:17b=61;29?xd??h0;6:4?:1y'067=;>l0Do9k;I`7e>"5m90:ok5f2bc94?=n:jh1<75f2ba94?=n:jn1<75f2bg94?=n:jl1<75`38394?=zj1=i6=49:183!24939<i6Fm7e9Kf1g<,;o;6n5f2bc94?=n:jh1<75f2ba94?=n:jn1<75f2bg94?=h;0;1<75rb95`>5<0290;w):<1;14b>Ne?m1Cn9o4$3g3>4e23`8hm7>5;h0`f?6=3`8ho7>5;h0``?6=3`8hi7>5;h0`b?6=3f92=7>5;|`;3a<72>0;6=u+423972`<@k=o7El;a:&1a5<6lj1b>no50;9j6fd=831b>nm50;9j6fb=831b>nk50;9j6f`=831d?4?50;9~f=1a29086=4?{%605?50j2Bi;i5Gb5c8 7c728i0e?mn:188m7ee2900c>7>:188yg>?83:1;7>50z&774<4?o1Cn:j4Hc6b?!4b83;h:6g=c`83>>o5kk0;66g=cb83>>o5km0;66g=cd83>>o5ko0;66a<9083>>{e01;1<7;50;2x 1562:=o7El8d:Ja0d=#:l:1545f2bc94?=n:jh1<75f2ba94?=n:jn1<75`38394?=zj1296=4::183!24939<h6Fm7e9Kf1g<,;o;6h5f2bc94?=n:jh1<75f2ba94?=n:jn1<75`38394?=zj1<i6=4;:183!2493;o56Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17d=6a;29?j5>?3:17pl76b83>1<729q/8>?51e;8Lg1c3Ah?m6*=e182?l??2900ei850;9j7<g=831d?4950;9~fgg529086=4?{%605?50j2Bi;i5Gb5c8 7c728i87d<la;29?l4dj3:17b=61;29?xd?lj0;694?:1y'067=9m30Do9k;I`7e>"5m90:7d77:188ma0=831b?4o50;9l7<1=831vnoo<:180>5<7s->8=7=8b:Ja3a=Oj=k0(?k?:0a0?l4di3:17d<lb;29?j5>93:17pl75483>1<729q/8>?51e;8Lg1c3Ah?m6*=e182?l??2900ei850;9j7<g=831d?4950;9~fgg329086=4?{%605?50j2Bi;i5Gb5c8 7c728i87d<la;29?l4dj3:17b=61;29?xd?0:0;6:4?:1y'067=;>l0Do9k;I`7e>"5m908:6g=c`83>>o5kk0;66g=cb83>>o5km0;66g=cd83>>o5ko0;66a<9083>>{e0131<7950;2x 1562:=m7El8d:Ja0d=#:l:1=h=4i3ab>5<<a;ii6=44i3a`>5<<a;io6=44i3af>5<<a;im6=44o2;2>5<<uk2<:7>57;294~"3;808;k5Gb6f8Lg2f3-8n<7?k3:k1gd<722c9oo4?::k1gf<722c9oi4?::k1g`<722c9ok4?::m0=4<722wi4:>50;794?6|,=9:6>9k;I`4`>Ne<h1/>h>54`9j6fg=831b>nl50;9j6fe=831b>nj50;9l7<7=831vn58i:184>5<7s->8=7=8f:Ja3a=Oj=k0(?k?:`18m7ef2900e?mm:188m7ed2900e?mk:188m7eb2900e?mi:188k6?62900qo676;292?6=8r.??<4<7d9Kf2b<@k>j7)<j0;1:?l4di3:17d<lb;29?l4dk3:17d<ld;29?l4dm3:17b=61;29?xd?010;6:4?:1y'067=;>l0Do9k;I`7e>"5m90:h;5f2bc94?=n:jh1<75f2ba94?=n:jn1<75f2bg94?=n:jl1<75`38394?=zj12>6=4::183!24939<h6Fm7e9Kf1g<,;o;6<ji;h0`e?6=3`8hn7>5;h0`g?6=3`8hh7>5;n1:5?6=3th34:4?:683>5}#<:;1?:h4Hc5g?Md3i2.9i=4>e09j6fg=831b>nl50;9j6fe=831b>nj50;9j6fc=831b>nh50;9l7<7=831vn58j:185>5<7s->8=7=8e:Ja3a=Oj=k0(?k?:2f8m7ef2900e?mm:188m7ed2900e?mk:188m7eb2900c>7>:188yg>1l3:1;7>50z&774<4?o1Cn:j4Hc6b?!4b839i7d<la;29?l4dj3:17d<lc;29?l4dl3:17d<le;29?l4dn3:17b=61;29?xd2i80;65>50;2x 1562:3i7El8d:Ja0d=]1>0nw<=523817?7328=1=54=4;06>4?=9h09:7<8:2097c<zf8=n6=5a1c394>"4j;0:h=5+3e697>"5l90=7)<k1;48 7b52?1/>i=56:&1`1<13-8o9784$3f5>3=#:m=1:6*=e085?!4b:3<0(?k<:79'6`2=>2.9i849;%0f2?0<,;o<6;5+2d:92>"5m00=7)<ja;48 7ce2?1/>hm56:&1aa<13-8ni784$3ge>3=#:o:1:6*=f085?!4a:3<0(?h<:79'6c2=>2.9j849;%0e2?0<,;l<6;5+2g:92>"5n00=7)<ia;48 7`e2?1/>km56:&1ba<13-8mi784$3de>3=#;9:1:6*<0085?!57:3<0(>><:79'752=>2.8<849;%132?0<,::<6;5+31:92>"4800=7)=?a;48 66e2?1/?=m56:&04a<13-9;i784$22e>3=#;8:1:6*<1085?!56:3<0(>?<:79'742=>2.8=849;%122?0<,:;<6;5+30:92>"4900=7)=>a;48 67e2?1/?<m56:&05a<13-9:i784$23e>3=#;;:1:6*<6280=5=#;0l1?i64n2c3><=i;h;1=?5+3`g97d4<,:km6>o=;%1a7?d2>2.8:<4<;%156?5<,k<i6o8n;%`5g?d1i2di:i46;o`5a?753-9o97=4i`;94?=nik0;66g>cc83>>o6km0;66g<a583>>o4i<0;66g<a783>M5e=21b?l950;J0f0=<a:kj6=44i2ca>5<<a:kh6=44i2cg>5<<a?91<7*<94856>h41=0;76g91;29 6?22?80b>7;:098m36=83.858492:l0=1<532c>j7>5$2;6>34<f:3?6>54i7a94?"41<0=>6`<9587?>o1j3:1(>7::708j6?32<10e;o50;&0=0<1:2d85949;:k5=?6=,:3>6;<4n2;7>2=<a?21<7*<94856>h41=0376g97;29 6?22?80b>7;:898m30=83.858492:l0=1<f32c=97>5$2;6>34<f:3?6o54i7694?"41<0=>6`<958`?>o2m3:1(>7::708j6?32m10e;h50;&0=0<1m2d8594?;I1a1>=n>m0;6)=65;4f?k5><3;0D>l:;:k;7?6=,:3>65<4n2;7>5=O;k?07d6>:18'7<3=0;1e?4:51:J0f0=<a131<7*<948;<>h41=0;76g77;29 6?22120b>7;:098m=0=83.858478:l0=1<532c397>5$2;6>=><f:3?6>54i8094?"41<0346`<9587?>o>93:1(>7::9:8j6?32<10e4>50;&0=0<?02d85949;:k;b?6=,:3>6564n2;7>2=<a1o1<7*<948;<>h41=0376g7d;29 6?22120b>7;:898m=e=83.858478:l0=1<f32c3n7>5$2;6>=><f:3?6o54i9c94?"41<0346`<958`?>o?<3:1(>7::9:8j6?32m10e<>?:18'7<3=no1e?4:50:9jb`<72-9297hi;o1:0?7<3`lo6=4+3879bc=i;0>1>65ffb83>!5>=3lm7c=64;18?l`e290/?4;5fg9m7<2=<21bjl4?:%1:1?`a3g9287;4;h33=?6=,:3>6kh4n2;7>3=<a8:36=4+3879bc=i;0>1;65f11594?"41<0mj6`<958;?>o68?0;6)=65;de?k5><3307d??5;29 6?22ol0b>7;:`98m463290/?4;5fg9m7<2=j21b===50;&0=0<an2d8594l;:k247<72-9297hi;o1:0?b<3`;;=7>5$2;6>c`<f:3?6h54ig;94?"41<0mj6`<958e?>o6;;0;6)=65;305>h41=0;76g>3183>!5>=3;8=6`<9582?>o6:o0;6)=65;305>h41=0976g>2d83>!5>=3;8=6`<9580?>o6:m0;6)=65;305>h41=0?76g>2b83>!5>=3;8=6`<9586?>o6;k0;6)=65;305>h41=0=76g>3`83>!5>=3;8=6`<9584?>o6;00;6)=65;305>h41=0376g>3983>!5>=3;8=6`<958:?>o6;>0;6)=65;305>h41=0j76g>3783>!5>=3;8=6`<958a?>o6;<0;6)=65;305>h41=0h76g>3583>!5>=3;8=6`<958g?>o6;:0;6)=65;305>h41=0n76g>2c83>!5>=3;8=6`<958e?>o6<:0;6)=65;376>h41=0;76g>4083>!5>=3;?>6`<9582?>o6<k0;6)=65;37e>h41=0;76g>4883>!5>=3;?m6`<9582?>i6?=0;6)=65;347>h41=0;76a>7383>!5>=3;<?6`<9582?>i6?80;6)=65;347>h41=0976a>7183>!5>=3;<?6`<9580?>i6>o0;6)=65;347>h41=0?76a>6d83>!5>=3;<?6`<9586?>i6?m0;6)=65;347>h41=0=76a>7b83>!5>=3;<?6`<9584?>i6?k0;6)=65;347>h41=0376a>7`83>!5>=3;<?6`<958:?>i6?00;6)=65;347>h41=0j76a>7983>!5>=3;<?6`<958a?>i6?>0;6)=65;347>h41=0h76a>7783>!5>=3;<?6`<958g?>i6?<0;6)=65;347>h41=0n76a>6e83>!5>=3;<?6`<958e?>i6i>0;6)=65;3b2>h41=0;76a>a483>!5>=3;j:6`<9582?>i6i=0;6)=65;3b2>h41=0976a>a283>!5>=3;j:6`<9580?>i6i;0;6)=65;3b2>h41=0?76a>a083>!5>=3;j:6`<9586?>i6j90;6)=65;3b2>h41=0=76a>ag83>!5>=3;j:6`<9584?>i6il0;6)=65;3b2>h41=0376a>ae83>!5>=3;j:6`<958:?>i6ij0;6)=65;3b2>h41=0j76a>ac83>!5>=3;j:6`<958a?>i6ih0;6)=65;3b2>h41=0h76a>a883>!5>=3;j:6`<958g?>i6i10;6)=65;3b2>h41=0n76a>a183>!5>=3;j:6`<958e?>i6j00;6)=65;3a<>h41=0;76a>b683>!5>=3;i46`<9582?>i6k80;6)=65;3`4>h41=0;76a>bg83>!5>=3;h<6`<9582?>oe=k0;6)=65;`6e>h41=0;7E=m5:9jf0?=83.8584m5`9m7<2=92B8n854ic7;>5<#;0?1n8o4n2;7>7=<ak?<6=4+3879f0g<f:3?6>54ic4:>5<#;0?1n;64n2;7>5=O;k?07dl97;29 6?22k<37c=64;38L6d232ci:;4?:%1:1?d102d8594=;I1a1>=nj??1<7*<948a2==i;0>1?6F<b498mg03290/?4;5b7:8j6?32=10eo8<:18'7<3=j?20b>7;:498mg05290/?4;5b7:8j6?32?10eo8>:18'7<3=j?20b>7;:698yg3f:3:1o54?:1yKf1g<,=9:6>7l;[;4>f}483996?o52c800?562:?1=84=c;35>65=:00vb<9j:19m5g7=82.8h84:;%133?0<,:?36;5+2d692>"5n=0=7)<kd;48 7b72?1/>hj56:&1b5<13-9>5784$20`>3=#;?8196*<5185?!56>3<0(>?=:79'705=>2.89<49;%11<?0<,::m6;5+31f92>"4;;0=7)=<d;48 6722?1/?>=56:&01c<13-8no784$212>3=#;8:1:6*=d485?!57>3<0(?h>:79'6ce=>2.88:49;%110?0<,::36;5+2g;92>"5l;0=7)=>c;48 6312?1/?=:56:&1a3<13-9:i784$3g2>3=#;=<1:6*=eg85?!5193?0(>=8:79'70b=>2.8=o49;%0ea?0<,;oi6;5+32492>"4;=0=7)=<a;48 62c2?1/>ko56:&1ad<13-99:784$262>3=#:l=1:6*=fg85?!5403<0(?h=:79'6c5=>2.8<o49;%0f1?0<,;lo6;5+37292>"4::0=7)<ka;48 6462?1/>i:56:&05=<13-9>i784$3f5>3=#;:?1:6*<1885?!4cn3<0(>:6:79'71d=>2.9ih49;%131?0<,:;m6;5+2g`92>"5l80=7)<ke;48 66d2?1/?8l56:&062<13-9?>784$3d5>3=#;8n1:6*<4985?!5383<0(>:;:79'76e=>2.89l49;%104?0<,:>>6;5+34a92>"49:0=7)=>a;48 64b2?1/>k656:&04`<13-8o?784$26`>3=#;;81:6*<d586?!53n3<0(?h::79'77?=>2.8<>49;%0gg?0<,;n<6;5+33292>"5lk0=7)=;3;48 7`02?1/?>756:&1`=<13-9>;784$206>3=#;<?1:6*<2e85?!56?3<0(?j6:79'71g=>2.8<449;%11b?0<,:8j6;5+31092>"49=0=7)=?a;48 62b2?1/?<?56:&07g<13-8n?784$277>3=#:l81:6*<3d85?!5783<0(><m:79'6`?=>2.9i549;%157?5>82.85i4<919'7<c=;0:0b>o?:008j6g62;>0(>l<:868 6d32:h:7)=:2;48 65a2?1/n;l5b7c8 g0d2k<j7cl9d;31?kd1m38?7)=?1;48ma>=83.8584i0:l0=1<6n21bn8950;&0=0<e=h1e?4:53:9je=<722cjm7>5;h3`e?6=3`;9?7>5$2;6>4453g9287>4;h315?6=,:3>6<<=;o1:0?7<3`;:j7>5$2;6>4453g9287<4;h32a?6=,:3>6<<=;o1:0?5<3`;:h7>5$2;6>4453g9287:4;h32g?6=,:3>6<<=;o1:0?3<3`;:n7>5$2;6>4453g928784;h32e?6=,:3>6<<=;o1:0?1<3`;:57>5$2;6>4453g928764;h32<?6=,:3>6<<=;o1:0??<3`;:;7>5$2;6>4453g9287o4;h322?6=,:3>6<<=;o1:0?d<3`;:87>5$2;6>4453g9287m4;h327?6=,:3>6<<=;o1:0?b<3`;:>7>5$2;6>4453g9287k4;h325?6=,:3>6<<=;o1:0?`<3`;:<7>5$2;6>4453g9287??;:k24c<72-9297?=2:l0=1<6921b==k50;&0=0<6:;1e?4:51398m46c290/?4;51308j6?328907d??c;29 6?228897c=64;37?>o68k0;6)=65;316>h41=0:965f13c94?"41<0:>?5a386953=<a8826=4+3879574<f:3?6<94;h31<?6=,:3>6<<=;o1:0?7?32c:>:4?:%1:1?75:2d8594>9:9j570=83.8584>239m7<2=9h10e<<::18'7<3=9;80b>7;:0`8?l75<3:1(>7::001?k5><3;h76g>2183>!5>=3;9>6`<9582`>=n98?1<7*<948267=i;0>1=h54i02b>5<#;0?1=?<4n2;7>4`<3f;>>7>5$2;6>4033g9287??;:m214<72-9297?94:l0=1<6921d=8>50;&0=0<6>=1e?4:51398k42a290/?4;51768j6?328907b?;e;29 6?228<?7c=64;37?>i6<m0;6)=65;350>h41=0:965`17a94?"41<0::95a386953=<g8<i6=4+3879532<f:3?6<94;n35e?6=,:3>6<8;;o1:0?7?32e::44?:%1:1?71<2d8594>9:9l53>=83.8584>659m7<2=9h10c<88:18'7<3=9?>0b>7;:0`8?j71>3:1(>7::047?k5><3;h76a>6383>!5>=3;=86`<9582`>=h9<=1<7*<948221=i;0>1=h54o06`>5<#;0?1=;:4n2;7>4`<3f;i?7>5$2;6>4d23g9287<4;n3a6?6=,:3>6<l:;o1:0?5<3`;?47>5$2;6>4203g9287>4;h372?6=,:3>6<:8;o1:0?7<3`;?97>5$2;6>4203g9287<4;h370?6=,:3>6<:8;o1:0?5<3`?96=4+387916=i;0>1=65f5083>!5>=3?87c=64;08?l37290/?4;5529m7<2=;21b8k4?:%1:1?343g9287:4;h6f>5<#;0?19>5a38691>=n=m0;6)=65;70?k5><3<07d;l:18'7<3==:1e?4:57:9j1g<72-9297;<;o1:0?><3`?j6=4+387916=i;0>1565f5883>!5>=3?87c=64;c8?l3?290/?4;5529m7<2=j21b;84?:%1:1?113g9287?4;h57>5<#;0?1;;5a38696>=n?:0;6)=65;55?k5><3907d9=:18'7<3=??1e?4:54:9j34<72-929799;o1:0?3<3`2;6=4+387933=i;0>1:65f7g83>!5>=3==7c=64;58?l1b290/?4;5779m7<2=021b;i4?:%1:1?113g928774;h5`>5<#;0?1;;5a3869e>=nj<i1<7*<948a1c=i;0>1?65`a083>>if83:17d=n3;29?jg52900e>j8:188k<`=831b5n4?::k2gf<722c2n7>5;h;f>5<<a:n=6=44i8f94?=n;h?1<75f15294?"41<0:?k5a38694>=n9:o1<7*<94827c=i;0>1=65f12f94?"41<0:?k5a38696>=n9:i1<7*<94827c=i;0>1?65fb4`94?"41<0i9l5a38694>=nj<31<7*<948a1d=i;0>1=65fb4:94?"41<0i9l5a38696>=h9??1<7*<948221=i;0>1<65`17194?"41<0::95a38695>=h9?;1<7*<948221=i;0>1>65`17294?"41<0::95a38697>=h9<l1<7*<948221=i;0>1865`14g94?"41<0::95a38691>=h9<n1<7*<948221=i;0>1:65`14a94?"41<0::95a38693>=h9<h1<7*<948221=i;0>1465`14c94?"41<0::95a3869=>=h9<31<7*<948221=i;0>1m65`14:94?"41<0::95a3869f>=h9<<1<7*<948221=i;0>1o65`14794?"41<0::95a3869`>=h9<>1<7*<948221=i;0>1i65`14194?"41<0::95a3869b>=h9k<1<7*<9482f0=i;0>1<65`1c694?"41<0:n85a38695>=h9ko1<7*<9482fa=i;0>1<65`1ca94?"41<0:ni5a38695>=h9kh1<7*<9482fa=i;0>1>65`1cc94?"41<0:ni5a38697>=n==0;6)=65;70?k5><3:07d;8:18'7<3==:1e?4:5c:9j13<72-9297;<;o1:0?b<3`?>6=4+387916=i;0>1i65f4e83>!5>=3?87c=64;d8?j7>03:1(>7::0;4?k5><3:07b?66;29 6?2283<7c=64;38?j7><3:1(>7::0;4?k5><3807b?63;29 6?2283<7c=64;18?j7>:3:1(>7::0;4?k5><3>07b?61;29 6?2283<7c=64;78?j7>83:1(>7::0;4?k5><3<07b?7f;29 6?2283<7c=64;58?j7?m3:1(>7::0;4?k5><3207b?7d;29 6?2283<7c=64;;8?j7?k3:1(>7::0;4?k5><3k07b?7b;29 6?2283<7c=64;`8?j7?13:1(>7::0;4?k5><3i07b?78;29 6?2283<7c=64;f8?j7??3:1(>7::0;4?k5><3o07b?76;29 6?2283<7c=64;d8?j7?=3:1(>7::0;4?k5><3;;76a>8583>!5>=3;2;6`<95825>=h9191<7*<9482=2=i;0>1=?54o0:1>5<#;0?1=494n2;7>45<3f;3=7>5$2;6>4?03g9287?;;:m2<5<72-9297?67:l0=1<6=21d=4h50;&0=0<61>1e?4:51798k4?b290/?4;51858j6?328=07b?6d;29 6?2283<7c=64;3;?>i61j0;6)=65;3:3>h41=0:565`18`94?"41<0:5:5a38695d=<g83j6=4+38795<1<f:3?6<l4;n3:=?6=,:3>6<78;o1:0?7d32e:584?:%1:1?7>?2d8594>d:9l5=g=83.8584>969m7<2=9l10c<9i:18'7<3=90=0b>7;:0d8?l10290/?4;5779m7<2=821b;o4?:%1:1?113g9287l4;h5b>5<#;0?1;;5a3869g>=n?00;6)=65;55?k5><3n07d97:18'7<3=??1e?4:5e:9j35<72-929799;o1:0?`<3`h=<7>5$2;6>g3a3g9287>4;h`6a?6=,:3>6o;i;o1:0?7<3`h>h7>5$2;6>g3a3g9287<4;hd2>5<#;0?1j=5a38694>=nmo0;6)=65;d3?k5><3;07dkk:18'7<3=n91e?4:52:9jaf<72-9297h?;o1:0?5<3`oi6=4+3879b5=i;0>1865fe`83>!5>=3l;7c=64;78?lc>290/?4;5f19m7<2=>21bi54?:%1:1?`73g928794;hg4>5<#;0?1j=5a3869<>=nm?0;6)=65;d3?k5><3307dk::18'7<3=n91e?4:5a:9ja1<72-9297h?;o1:0?d<3`o96=4+3879b5=i;0>1o65fe083>!5>=3l;7c=64;f8?lc7290/?4;5f19m7<2=m21bhk4?:%1:1?`73g9287h4;hff>5<#;0?1j=5a386955=<amn1<7*<948e4>h41=0:=65fdb83>!5>=3l;7c=64;31?>ocj3:1(>7::g28j6?328907djn:18'7<3=n91e?4:51598ma?=83.8584i0:l0=1<6=21bj54?:%1:1?`73g9287?9;:ke3?6=,:3>6k>4n2;7>41<3`l=6=4+3879b5=i;0>1=554ig794?"41<0m<6`<9582=>=nn=0;6)=65;d3?k5><3;j76gi3;29 6?22o:0b>7;:0`8?l`5290/?4;5f19m7<2=9j10ehk50;&0=0<a82d8594>d:9ja6<72-9297h?;o1:0?7b32wi9l=50;a;>5<7sAh?m6*;3080=f=]1>0hw>>53381e?4e2:>1?<4<5;36>7e=9?08?7<6:|l23`<73g;i=7>4$2f6>0=#;9=1:6*<5985?!4b<3<0(?h;:79'6ab=>2.9h=49;%0f`?0<,;l;6;5+34;92>"4:j0=7)=92;78 6372?1/?<856:&057<13-9>?784$272>3=#;;21:6*<0g85?!57l3<0(>==:79'76b=>2.8=849;%107?0<,:?m6;5+2da92>"4;80=7)=>0;48 7b22?1/?=856:&1b4<13-8mo784$264>3=#;;>1:6*<0985?!4a13<0(?j=:79'74e=>2.89;49;%130?0<,;o=6;5+30g92>"5m80=7)=;6;48 7ca2?1/?;?55:&072<13-9>h784$23a>3=#:oo1:6*=ec85?!54>3<0(>=;:79'76g=>2.88i49;%0ee?0<,;oj6;5+33492>"4<80=7)<j7;48 7`a2?1/?>656:&1b7<13-8m?784$22a>3=#:l?1:6*=fe85?!5183<0(><<:79'6ag=>2.8><49;%0g0?0<,:;36;5+34g92>"5l?0=7)=<5;48 67>2?1/>ih56:&00<<13-9?n784$3gf>3=#;9?1:6*<1g85?!4aj3<0(?j>:79'6ac=>2.8<n49;%16f?0<,:8<6;5+35092>"5n?0=7)=>d;48 62?2?1/?9>56:&001<13-98o784$27b>3=#;::1:6*<4485?!52k3<0(>?<:79'74g=>2.8>h49;%0e<?0<,::n6;5+2e192>"4<j0=7)==2;48 6b32<1/?9h56:&1b0<13-995784$220>3=#:mi1:6*=d685?!5583<0(?jm:79'715=>2.9j:49;%10=?0<,;n36;5+34592>"4:<0=7)=:5;48 64c2?1/?<956:&1`<<13-9?m784$22:>3=#;;l1:6*<2`85?!57:3<0(>?;:79'75g=>2.88h49;%125?0<,:9i6;5+2d192>"4==0=7)<j2;48 65b2?1/?=>56:&06g<13-8n5784$3g;>3=#;?91?4>4$2;g>6?73-92i7=60:l0e5<6:2d8m<4=4:&0f6<><2.8n94<b09'704=>2.8?k49;%`5f?d1i2.i:n4m6`9mf3b=9;1en;k5259'757=>2co47>5$2;6>c6<f:3?6<h4;h`63?6=,:3>6o;n;o1:0?5<3`k36=44i`c94?=n9jk1<75f13194?"41<0:>?5a38694>=n9;;1<7*<948267=i;0>1=65f10d94?"41<0:>?5a38696>=n98o1<7*<948267=i;0>1?65f10f94?"41<0:>?5a38690>=n98i1<7*<948267=i;0>1965f10`94?"41<0:>?5a38692>=n98k1<7*<948267=i;0>1;65f10;94?"41<0:>?5a3869<>=n9821<7*<948267=i;0>1565f10594?"41<0:>?5a3869e>=n98<1<7*<948267=i;0>1n65f10694?"41<0:>?5a3869g>=n9891<7*<948267=i;0>1h65f10094?"41<0:>?5a3869a>=n98;1<7*<948267=i;0>1j65f10294?"41<0:>?5a386955=<a8:m6=4+3879574<f:3?6<?4;h33a?6=,:3>6<<=;o1:0?7532c:<i4?:%1:1?75:2d8594>3:9j55e=83.8584>239m7<2=9=10e<>m:18'7<3=9;80b>7;:078?l75i3:1(>7::001?k5><3;=76g>2883>!5>=3;9>6`<95823>=n9;21<7*<948267=i;0>1=554i004>5<#;0?1=?<4n2;7>4?<3`;9:7>5$2;6>4453g9287?n;:k260<72-9297?=2:l0=1<6j21b=?:50;&0=0<6:;1e?4:51b98m447290/?4;51308j6?328n07d?>5;29 6?228897c=64;3f?>o68h0;6)=65;316>h41=0:j65`14094?"41<0::95a386955=<g8?:6=4+3879532<f:3?6<?4;n364?6=,:3>6<8;;o1:0?7532e:8k4?:%1:1?71<2d8594>3:9l51c=83.8584>659m7<2=9=10c<:k:18'7<3=9?>0b>7;:078?j71k3:1(>7::047?k5><3;=76a>6c83>!5>=3;=86`<95823>=h9?k1<7*<948221=i;0>1=554o04:>5<#;0?1=;:4n2;7>4?<3f;=47>5$2;6>4033g9287?n;:m222<72-9297?94:l0=1<6j21d=;850;&0=0<6>=1e?4:51b98k405290/?4;51768j6?328n07b?:7;29 6?228<?7c=64;3f?>i6<j0;6)=65;350>h41=0:j65`1c194?"41<0:n85a38696>=h9k81<7*<9482f0=i;0>1?65f15:94?"41<0:8:5a38694>=n9=<1<7*<948202=i;0>1=65f15794?"41<0:8:5a38696>=n9=>1<7*<948202=i;0>1?65f5383>!5>=3?87c=64;38?l36290/?4;5529m7<2=:21b9=4?:%1:1?343g9287=4;h6e>5<#;0?19>5a38690>=n<l0;6)=65;70?k5><3?07d;k:18'7<3==:1e?4:56:9j1f<72-9297;<;o1:0?1<3`?i6=4+387916=i;0>1465f5`83>!5>=3?87c=64;;8?l3>290/?4;5529m7<2=i21b954?:%1:1?343g9287l4;h56>5<#;0?1;;5a38695>=n?=0;6)=65;55?k5><3807d9<:18'7<3=??1e?4:53:9j37<72-929799;o1:0?2<3`=:6=4+387933=i;0>1965f8183>!5>=3==7c=64;48?l1a290/?4;5779m7<2=?21b;h4?:%1:1?113g928764;h5g>5<#;0?1;;5a3869=>=n?j0;6)=65;55?k5><3k07dl:c;29 6?22k?m7c=64;18?jg62900cl>50;9j7d5=831dm?4?::k0`2<722e2j7>5;h;`>5<<a8ih6=44i8`94?=n1l0;66g<d783>>o>l3:17d=n5;29?l7383:1(>7::01e?k5><3:07d?<e;29 6?2289m7c=64;38?l74l3:1(>7::01e?k5><3807d?<c;29 6?2289m7c=64;18?ld2j3:1(>7::c7b?k5><3:07dl:9;29 6?22k?j7c=64;38?ld203:1(>7::c7b?k5><3807b?95;29 6?228<?7c=64;28?j71;3:1(>7::047?k5><3;07b?91;29 6?228<?7c=64;08?j7183:1(>7::047?k5><3907b?:f;29 6?228<?7c=64;68?j72m3:1(>7::047?k5><3?07b?:d;29 6?228<?7c=64;48?j72k3:1(>7::047?k5><3=07b?:b;29 6?228<?7c=64;:8?j72i3:1(>7::047?k5><3307b?:9;29 6?228<?7c=64;c8?j7203:1(>7::047?k5><3h07b?:6;29 6?228<?7c=64;a8?j72=3:1(>7::047?k5><3n07b?:4;29 6?228<?7c=64;g8?j72;3:1(>7::047?k5><3l07b?m6;29 6?228h>7c=64;28?j7e<3:1(>7::0`6?k5><3;07b?me;29 6?228ho7c=64;28?j7ek3:1(>7::0`g?k5><3;07b?mb;29 6?228ho7c=64;08?j7ei3:1(>7::0`g?k5><3907d;;:18'7<3==:1e?4:50:9j12<72-9297;<;o1:0?e<3`?=6=4+387916=i;0>1h65f5483>!5>=3?87c=64;g8?l2c290/?4;5529m7<2=n21d=4650;&0=0<61>1e?4:50:9l5<0=83.8584>969m7<2=921d=4:50;&0=0<61>1e?4:52:9l5<5=83.8584>969m7<2=;21d=4<50;&0=0<61>1e?4:54:9l5<7=83.8584>969m7<2==21d=4>50;&0=0<61>1e?4:56:9l5=`=83.8584>969m7<2=?21d=5k50;&0=0<61>1e?4:58:9l5=b=83.8584>969m7<2=121d=5m50;&0=0<61>1e?4:5a:9l5=d=83.8584>969m7<2=j21d=5750;&0=0<61>1e?4:5c:9l5=>=83.8584>969m7<2=l21d=5950;&0=0<61>1e?4:5e:9l5=0=83.8584>969m7<2=n21d=5;50;&0=0<61>1e?4:51198k4>3290/?4;51858j6?328;07b?73;29 6?2283<7c=64;31?>i60;0;6)=65;3:3>h41=0:?65`19394?"41<0:5:5a386951=<g82;6=4+38795<1<f:3?6<;4;n3:b?6=,:3>6<78;o1:0?7132e:5h4?:%1:1?7>?2d8594>7:9l5<b=83.8584>969m7<2=9110c<7l:18'7<3=90=0b>7;:0;8?j7>j3:1(>7::0;4?k5><3;j76a>9`83>!5>=3;2;6`<9582f>=h9031<7*<9482=2=i;0>1=n54o0;6>5<#;0?1=494n2;7>4b<3f;3m7>5$2;6>4?03g9287?j;:m23c<72-9297?67:l0=1<6n21b;:4?:%1:1?113g9287>4;h5a>5<#;0?1;;5a3869f>=n?h0;6)=65;55?k5><3i07d96:18'7<3=??1e?4:5d:9j3=<72-929799;o1:0?c<3`=;6=4+387933=i;0>1j65fb7294?"41<0i9k5a38694>=nj<o1<7*<948a1c=i;0>1=65fb4f94?"41<0i9k5a38696>=nn80;6)=65;d3?k5><3:07dki:18'7<3=n91e?4:51:9jaa<72-9297h?;o1:0?4<3`oh6=4+3879b5=i;0>1?65fec83>!5>=3l;7c=64;68?lcf290/?4;5f19m7<2==21bi44?:%1:1?`73g928784;hg;>5<#;0?1j=5a38693>=nm>0;6)=65;d3?k5><3207dk9:18'7<3=n91e?4:59:9ja0<72-9297h?;o1:0?g<3`o?6=4+3879b5=i;0>1n65fe383>!5>=3l;7c=64;a8?lc6290/?4;5f19m7<2=l21bi=4?:%1:1?`73g9287k4;hfe>5<#;0?1j=5a3869b>=nll0;6)=65;d3?k5><3;;76gkd;29 6?22o:0b>7;:038?lbd290/?4;5f19m7<2=9;10eil50;&0=0<a82d8594>3:9j`d<72-9297h?;o1:0?7332co57>5$2;6>c6<f:3?6<;4;hd;>5<#;0?1j=5a386953=<ao=1<7*<948e4>h41=0:;65ff783>!5>=3l;7c=64;3;?>oa=3:1(>7::g28j6?328307dh;:18'7<3=n91e?4:51`98mc5=83.8584i0:l0=1<6j21bj?4?:%1:1?`73g9287?l;:kfa?6=,:3>6k>4n2;7>4b<3`o86=4+3879b5=i;0>1=h54}rc4>5<59mqUm:52a`29===:ihh15552ac49===:ij;15552aba9===:im=15552ad09===:iln15552ag19===:io>15552a`39===:ih815552a`19===:ih>15552a`79===:ih<15552a`59===:ih215552a`;9===:ihk15552a`a9===:ihn15552a`g9===:ihl15552ac29===:ik;15552ac09===:ik915552ac69===:ik?15552ac59===:ik215552ac;9===:ikk15552ac`9===:iki15552acf9===:iko15552acd9===:ij:15552ab09===:ij915552ab69===:ij?15552ab49===:ij=15552ab:9===:ij315552abc9===:ijh15552abf9===:ijo15552abd9===:im:15552ae39===:im815552ae19===:im>15552ae79===:im<15552ae:9===:im315552aec9===:imh15552aea9===:imn15552aeg9===:iml15552ad29===:il;15552ad19===:il>15552ad79===:il<15552ad59===:il215552ad;9===:ilk15552ad`9===:ili15552adg9===:ill15552ag29===:io;15552ag09===:0o>15552a619===:0o<155528gd9===:0ok155528g:9===:0on155524219===:<=31555244d9===:<>?1555249`9===:<h;155524c59===:<jn155524e;9===:<mh155524279===:<:=1555242;9===:<:h1555242f9===:<:l155524539===:<=9155524579===:<==1555245`9===:<=n1555245d9===:<<;155524419===:<<?155524459===:<<31555244`9===:<<n155524739===:<?9155524779===:<?=1555247;9===:<?h1555247f9===:<?l155524639===:<>9155524659===:<>31555246`9===:<>n1555246d9===:<1;155524919===:<1?155524959===:<131555249f9===:<1l155524839===:<09155524879===:<0=1555248;9===:<0h1555248f9===:<0l155524`19===:<h?155524`59===:<h3155524``9===:<hn155524`d9===:<k;155524c19===:<k?155524c;9===:<kh155524cf9===:<kl155524b39===:<j9155524b79===:<j=155524b;9===:<jh155524bd9===:<m;155524e19===:<m?155524e59===:<:81m:5245:9e2=:<<o1m:524669e2=:<1k1m:524`29e2=:<k<1m:524ba9e2=:<m21m:524ec9e2=:<:>1m:524249e2=:<:21m:5242c9e2=:<:i1m:5242g9e2=:<=:1m:524509e2=:<=>1m:524549e2=:<=k1m:5245a9e2=:<=o1m:524429e2=:<<81m:524469e2=:<<<1m:5244:9e2=:<<k1m:5244a9e2=:<?:1m:524709e2=:<?>1m:524749e2=:<?21m:5247c9e2=:<?i1m:5247g9e2=:<>:1m:524609e2=:<><1m:5246:9e2=:<>k1m:5246a9e2=:<>o1m:524929e2=:<181m:524969e2=:<1<1m:5249:9e2=:<1i1m:5249g9e2=:<0:1m:524809e2=:<0>1m:524849e2=:<021m:5248c9e2=:<0i1m:5248g9e2=:<h81m:524`69e2=:<h<1m:524`:9e2=:<hk1m:524`a9e2=:<ho1m:524c29e2=:<k81m:524c69e2=:<k21m:524cc9e2=:<ki1m:524cg9e2=:<j:1m:524b09e2=:<j>1m:524b49e2=:<j21m:524bc9e2=:<jo1m:524e29e2=:<m81m:524e69e2=:<m<1m:5297d9===:1?o1555297f9===:1?i1555297`9===:1?31555297:9===:1?=155529749===:1??155529769===:1?9155529709===:1?;155529729===:1<o1555294f9===:1<i1555294`9===:1<k1555294;9===:1<2155529459===:1<<155529479===:1<9155529409===:1<;155529429===:1=l1555295g9===:1=n1555295a9===:1=h1555295c9===:1=2155529559===:1=<155529579===:1=>155529519===:1=8155529539===:1=:1555292d9===:1:n1555292a9===:1:h1555292c9===:1:31555292:9===:1:=155529249===:1:?155529269===:1:8155529239===:1::1555293d9===:1;o1555293f9===:1;i1555293`9===:1;k1555293;9===:1;=155529349===:1;?155529369===:1;9155529309===:1;;155529329===:18l1555290g9===:1>;155529629===:1?k1555294d9===:1<>1555295;9===:1:o155529219===:1;21555290f9===:1j>155529b19===:1j8155529b39===:1j:155529cg9===:1kn155529ca9===:1kh155529cc9===:1k3155529c:9===:1k=155529c49===:1k?155529c19===:1k8155529c39===:1k:155529`d9===:1ho155529`f9===:1hi155529``9===:1hk155529`:9===:1h=155529`49===:1h?155529`69===:1h9155529`09===:1h;155529`29===:10l1555298f9===:10i1555298`9===:10k1555298;9===:102155529859===:10<155529879===:10>155529809===:10;155529829===:11l1555299g9===:11n1555299a9===:11h1555299c9===:113155529959===:11<155529979===:11>155529919===:118155529939===:11:1555296d9===:1>o1555296a9===:1>h1555296c9===:1>31555296:9===:1>=155529649===:1>?155529669===:1>9155529b49===:1j?155529cd9===:1k>155529`;9===:10o155529819===:1121555296f9===:1>8155529b59ef=:1891555291c9===:18>1mn5287:9===:0?3155528449===:0=?155528569===:0=9155528509===:0=;155528529===:0:l1555282g9===:0:n1555282a9===:00<155528879===:0081555284f9===:0<o1555284a9===:0?:1555284d9===:0;;155527g19===:?o>155527g79===:?o<155527g59===:?o2155527g;9===:?ok155528069===:08?155528019===:082155528049===:08=155528139===:098155528129===:09=155528119===:09>155528179===:09<155527e:9===:?m3155527e69===:>0o1555268d9===:?m<155527e59===:>ho155526b29===:>h:155526gd9===:>on155527109===:?9:155527179===:?991555271:9===:?9<1555271`9===:?931555271g9===:?9i155527039===:?9l155527069===:?88155527059===:?8?1555270c9===:?82155527849===:?091555279d9===:?1h155527959===:?191555276d9===:?>h155527659===:?>9155527409===:?=l1555275`9===:?==155527519===:?:l1555272`9===:?:=155527219===:?;l155527`79ef=:?h=1mn527`;9ef=:0?h1555287a9===:0mi155528479===:=h;1mo525`09ed=:=h91ml5rs`d94?04sWkm706ic;c4?8>a?3k<707l7;1g5>;>8?0j;636058b3>;>8<0j;6361580`4=:0<=1555284:9===:0mh155528739===:01o1555289d9===:01n155528bg9===:0jh155528b59===:0j9155528cd9===:0kh155528c59===:0k9155528`d9===:0hh1555280;9===:092155526e09e2=:>mk1m:526c09e2=:>k91m:526c69e2=:>k?1m:526b69e2=:>j?1m:526b49e2=:>j=1m:526`;9e2=:>hk1m:526e79e2=:>m<1m:526`09e2=:>h91m:526e`9e2=:>mi1m:526e19e2=:>li155526g19===:>o>155526g79===:>o<155526g59===:>o2155526g;9===:>ok155526g`9===:>ln155526dg9===:>ll155526g29===:>o;155526g09===:>oi1m:527`797a7<5>k<6>j>;<5b=?5c927>m=468:?6=c<>027>5h468:?6=a<>027>5n468:?6=g<>027>oh468:?6b7<>027>ih468:?6ad<>027>i;468:?6a7<>027>hh468:?6`d<>027>h;468:?6`7<>027>oo468:?620<>027>:?468:?61`<>027>9l468:?613<>027>9?468:?60`<>027>5<468:?6<`<>027>4l468:?6<3<>027>4?468:?63`<>027>m<4n9:?6e7<f027>m>4n8:pf5<72;qUn=5289c96fd<uzh:6=4={_`2?8>?i38hm6s|b383>0}Yj;164=65a59><5>=l?16;kh52b`89=>f2;ih7p}m3;293~Xe;273944>e49><0>=;0<015?6:`689=7>2m<015?=:3aa?8>?i38hh6s|b583>43|Vk>018o?:2;b?83>n392m63:9d80=d=:=0n1?4o4=4;`>6?f34?2n7=6a:?677<5kh169;h52b`890eb2:3j70;i2;1:e>;2ml085l525dc97<g<5<o=6>7n;<7f6?5>i27>hh4<9`9>1ag=;0k018j9:2;b?83c:392m63:cc80=d=:0?n1>no4}r`6>5<5sWh>7069d;0`f>{tj?0;6?uQb79><3b=:ji0q~l8:181[d0342=h7<ld:pf=<72;qUn55287f96fc<uzh26=4={_`:?8>1m38hm6s|b`83>0}Yjh164km5d79>=f1=;m801;kl:e489=>f2;in7p}mb;29f1}Yjk165;h538489<0b2:3=7079d;1:2>;>>j085;5297`97<0<50<26>79;<;5<?5>>272::4<979>=30=;0<0148::2;5?8?1<392:6366280=3=:1?81?484=842>6?1343=<7=66:?:1`<41?1658j538489<3d2:3=707:b;1:2>;>=h085;5294;97<0<50?36>79;<;63?5>>2729;4<979>=03=;0<014;<:2;5?8?2:392:6365080=3=:1<:1?484=86e>6?1343?i7=66:?:0a<41?1659m538489<2e2:3=707;a;1:2>;><1085;5295597<0<50>=6>79;<;71?5>>272894<979>=15=;0<014:=:2;5?8?39392:6364180=3=:1:l1?484=81g>6?13438o7=66:?:7g<41?165>o538489<5>2:3=707<8;1:2>;>;>085;5292497<0<509>6>79;<;00?5>>272??4<979>=67=;0<014=?:2;5?8?5n392:6362d80=3=:1;n1?484=80`>6?13439n7=66:?:6d<41?165?7538489<402:3=707=6;1:2>;>:<085;5293697<0<50886>79;<;16?5>>272><4<979>=76=;0<014?i:2;5?8?6m392:6367080=3=:1>:1?484=84b>6?1343>j7=66:?:11<41?16597538489<5b2:3=707<3;1:2>;>:1085;5290f97<0<50i?6>79;<;`7?5>>272o?4<979>=f7=;0<014m?:2;5?8?em392:636be80=3=:1ki1?484=8`a>6?1343im7=66:?:f<<41?165o6538489<d02:3=707m6;1:2>;>j<085;529c197<0<50h96>79;<;a5?5>>272n=4<979>=d`=;0<014oj:2;5?8?fl392:636ab80=3=:1hh1?484=8cb>6?1343j47=66:?:e2<41?165l8538489<g22:3=707n4;1:2>;>i:085;529`097<0<50k:6>79;<;b4?5>>2725k4<979>=<b=;0<0147l:2;5?8?>j392:6369`80=3=:1031?484=8;;>6?13432;7=66:?:=3<41?1654;538489<?32:3=70762;1:2>;>18085;5298297<0<502m6>79;<;;a?5>>2724i4<979>==e=;0<0146m:2;5?8??i392:6368880=3=:11=1?484=8:5>6?1343397=66:?:<1<41?1655=538489<>52:3=70771;1:2>;>09085;5296d97<0<50=n6>79;<;4g?5>>272;o4<979>=2g=;0<01496:2;5?8?00392:6367680=3=:1><1?484=856>6?1343<87=66:?:36<41?165n8538489<e22:3=707mf;1:2>;>j=085;529`;97<0<503n6>79;<;:7?5>>272454<979>=2b=;0<0149=:2;5?8?d?39o<636078b0>;>8=0j8636048b0>;>8>09oo5291:96fd<50;96?mm;<;20?5c8273;>4=cd9~wge=838pRom4=950>7ea3tyih7>52z\a`>;?>l09oo5rscg94?4|Vko0158j:3a`?xuen3:1>vPmf:?;2`<5km1vn>50;0xZf6<51<n6?mj;|q`5?6=:rTh=6377d81g`=z{j81<7<t^b089=1b2;im7p}l3;296~Xd;273494=cc9~wf2=838pRn:4=9:7>7ef3tyh97>52z\`1>;?0k09ol5rsb494?4|Vj<0156;:3a`?xud?3:1>vPl7:?;<1<5km1vn650;0xZf><51=n6?mm;|q`=?6=:rTh56377d81gd=z{jk1<7<t^bc89=1b2;ih7p}lc;296~Xdk273;h4=ce9~wfb=838pRnj4=7;`>6?63tyhi7>56z\`a>;?1:09ol5286196fd<51<m6?mm;<:;<?4di273;i4=c`9~wf`=83=pRnh4=942>d2<51<:6i84=9:f>a0<51386?mm;<:6f?4dj273;>4=c`9~wa6=83;2wSj?;<4:g?4dk27>m=4n4:?6=c<f<27>5h4n4:?6=a<f<27>5n4n4:?6=g<f<27>:84n4:?627<f<27>9h4n4:?61d<f<27>9;4n4:?617<f<27>8h4n4:?6=4<f<27>4h4n4:?6<d<f<27>4;4n4:?6<7<f<27>;h4n4:?;36<5kj169l?51b`890g528ij70;n3;3`e>{tl80;6?uQd09><25=:jn0q~j=:187[b5342mo7o;;<:e3?g3342387<le:p`6<72;hpRi=4=7f1>d2<5?nj6l:4=7`1>d2<5?h86l:4=7`7>d2<5?h>6l:4=7a7>d2<5?i>6l:4=7a5>d2<5?i<6l:4=7c:>d2<5?kj6l:4=7f6>d2<5?n=6l:4=7c1>d2<5?k86l:4=7fa>d2<5?nh6l:4=7f0>d2<5?oh6l:4=7d0>d2<5?l?6l:4=7d6>d2<5?l=6l:4=7d4>d2<5?l36l:4=7d:>d2<5?lj6l:4=7da>d2<5?oo6l:4=7gf>d2<5?om6l:4=7d3>d2<5?l:6l:4=7d1>d2<5?lh6l:4=6c0>7ee34=j87<lb:?4e0<4l916;l953e2892g>2:n;70674;0`b>{t;1<1<7h9{<`4a?7b=27jm=4<979>edd=;0<01ll9:2;5?8gd9392:63ncb80=3=:im=1?484=`g1>6?134knh7=66:?bb6<41?16mk:538489dg62:3=70on2;1:2>;fi:085;52a`697<0<5hk>6>79;<cb2?5>>27jm:4<979>ed>=;0<01lo6:2;5?8gfi392:63nab80=3=:ihn1?484=`cf>6?134kjj7=66:?bf5<41?16mo?538489dd52:3=70om3;1:2>;fj=085;52ac797<0<5hh<6>79;<ca<?5>>27jn44<979>egg=;0<01llm:2;5?8gek392:63nbe80=3=:iko1?484=``e>6?134kh<7=66:?bg7<41?16mn=538489de32:3=70ol5;1:2>;fk?085;52ab597<0<5hi36>79;<c`=?5>>27jol4<979>efd=;0<01lmk:2;5?8gdm392:63ncg80=3=:im:1?484=`f2>6?134ko>7=66:?b`6<41?16mi:538489db22:3=70ok6;1:2>;fl1085;52ae;97<0<5hnj6>79;<cgf?5>>27jhn4<979>eab=;0<01ljj:2;5?8gcn392:63ne180=3=:il;1?484=`g0>6?134kn87=66:?ba0<41?16mh8538489dc02:3=70oj8;1:2>;fm0085;52adc97<0<5hoi6>79;<cfg?5>>27jih4<979>e``=;0<01lh?:2;5?8ga9392:63nf380=3=:<:818>5245:906=:<<o18>52466906=:<1k18>524`2906=:<k<18>524ba906=:<m218>524ec906=:<:>18>52424906=:<:218>5242c906=:<:i18>5242g906=:<=:18>52450906=:<=>18>52454906=:<=k18>5245a906=:<=o18>52442906=:<<818>52446906=:<<<18>5244:906=:<<k18>5244a906=:<?:18>52470906=:<?>18>52474906=:<?218>5247c906=:<?i18>5247g906=:<>:18>52460906=:<><18>5246:906=:<>k18>5246a906=:<>o18>52492906=:<1818>52496906=:<1<18>5249:906=:<1i18>5249g906=:<0:18>52480906=:<0>18>52484906=:<0218>5248c906=:<0i18>5248g906=:<h818>524`6906=:<h<18>524`:906=:<hk18>524`a906=:<ho18>524c2906=:<k818>524c6906=:<k218>524cc906=:<ki18>524cg906=:<j:18>524b0906=:<j>18>524b4906=:<j218>524bc906=:<jo18>524e2906=:<m818>524e6906=:<m<18>528bc9`2=:0j<1h:528b09`2=:0ko1h:528cc9`2=:0k<1h:528c09`2=:0ho1h:528`c9`2=:0;;1h;5283397<0<51896?mn;<:16?4dk27=m=4<9`9>3<4=l>16;5k5d69>3=g=l>16;585d69>3=4=l>16;:k5d69>32g=l>16;:85d69>324=l>16;9k5d69>31g=l>16;985d69>314=l>16;>k5d69>36g=l>16;>85d69>364=l>16;?k5d69>1c7=l>169hj5d69>1`?=l>169h;5d69>1`7=l>169ij5d69>1a?=l>169i;5d69>1a7=l>169no5d69>137=l>1698j5d69>10?=l>1698;5d69>107=l>1699j5d69>1=b=l>169575d69>1=3=l>1695?5d69>12b=l>169l?5120890g6289;70;n1;31b>;2i80:8o525`39f0><5<k:6o;8;<7b5?5fi27>m<4<ac9>1d7=;hi018o>:2cg?83f:3h>;63:a380`2=:=h81?i84=4c1>g3e34?j>7l:9:?6e7<e=1169l=5b45890g42:n<70;n3;1g2>;2i:0i9o525`19f0?<5<k86o;7;|q0<2<72;q645752ba89=>02:3:7p}<8983>7}:0131>nk4=9:;>6?63ty8444?:3y><26=;0;0158i:3ae?xu40h0;6?u289497<7<51236?mi;|q0<g<72;q645;538389=>02;in7p}<8b83>7}:0?o1?4?4=94g>7ea3ty8hl4?:3y]7ag<5hk;6i84}r1gf?6=:rT8ho52a`39`3=z{:nh6=4={_1gg>;fi;0o:6s|3ef94?4|V:no70on3;f5?xu4ll0;6?uQ3eg89dg32m<0q~=kf;296~X4lo16ml;5d79~w6c72909wS=j0:?be3<c>2wx?h?50;0xZ6c634kj;7j9;|q0a7<72;qU?h<4=`c;>a0<uz9n?7>52z\0a6=:ih31h;5rs2g7>5<5sW9n863na`8g2>{t;l?1<7<t^2g6?8gfj3n=7p}<e783>7}Y;l<01lol:e48yv5b?3:1>vP<e69>edb=l?1v>k7:181[5b027jmh4k6:p7`?=838pR>k6;<cbb?b13ty8il4?:3y]7`g<5hh;6i84}r1ff?6=:rT8io52ac39`3=z{:oh6=4={_1fg>;fj;0o:6s|3df94?4|V:oo70om3;f5?xu4ml0;6?uQ3dg89dd32m<0q~=jf;296~X4mo16mo;5d79~w6`72909wS=i0:?bf3<c>2wx?k?50;0xZ6`634ki;7j9;|q0b7<72;qU?k<4=``;>a0<uz9m?7>52z\0b6=:ik31h;5rs2d7>5<5sW9m863nb`8g2>{t;o?1<7<t^2d6?8gej3n=7p}<f783>7}Y;o<01lll:e48yv5a?3:1>vP<f69>egb=l?1v>h7:181[5a027jnh4k6:p7c?=838pR>h6;<cab?b13ty8jl4?:3y]7cg<5hi;6i84}r1ef?6=:rT8jo52ab39`3=z{:lh6=4={_1eg>;fk;0o:6s|3gf94?4|V:lo70ol3;f5?xu4nl0;6?uQ3gg89de32m<0q~=if;296~X4no16mn;5d79~w1672909wS:?0:?bg3<c>2wx8=?50;0xZ16634kh;7j9;|q747<72;qU8=<4=`a;>a0<uz>;?7>52z\746=:ij31h;5rs527>5<5sW>;863nc`8g2>{t<9?1<7<t^526?8gdj3n=7p};0783>7}Y<9<01lml:e48yv27?3:1>vP;069>efb=l?1v9>7:181[27027joh4k6:p05?=838pR9>6;<c`b?b13ty?<l4?:3y]05g<5hn;6i84}r63f?6=:rT?<o52ae39`3=z{=:h6=4={_63g>;fl;0o:6s|41f94?4|V=:o70ok3;f5?xu38l0;6?uQ41g89db32m<0q~:?f;296~X38o16mi;5d79~w1772909wS:>0:?b`3<c>2wx8<?50;0xZ17634ko;7j9;|q757<72;qU8<<4=`f;>a0<uz>:?7>52z\756=:im31h;5rs537>5<5sW>:863nd`8g2>{t<8?1<7<t^536?8gcj3n=7p};1783>7}Y<8<01ljl:e48yv26?3:1>vP;169>eab=l?1v9?7:181[26027jhh4k6:p04?=838pR9?6;<cgb?b13ty?=l4?:3y]04g<5ho;6i84}r62f?6=:rT?=o52ad39`3=z{=;h6=4={_62g>;fm;0o:6s|40f94?4|V=;o70oj3;f5?xu39l0;6?uQ40g89dc32m<0q~:>f;296~X39o16mh;5d79~w1472909wS:=0:?ba3<c>2wx8??50;0xZ14634kn;7j9;|q767<72;qU8?<4=`g;>a0<uz>9?7>52z\766=:il31h;5rs507>5<5sW>9863ne`8g2>{t<;?1<7<t^506?8gbj3n=7p};2783>7}Y<;<01lkl:e48yv25?3:1>vP;269>e`b=l?1v9<7:181[25027jih4k6:p07?=838pR9<6;<cfb?b13ty?>l4?:3y]07g<5hl;6i84}r61f?6=:rT?>o52ag39`3=z{=8o6=4={_61`>;fn;0o:6s|43g94?4|V=8n70oi3;f5?xu3:o0;6?uQ43d89d`32m<0q~:kc;296~;3;:0o:63;3380=2=z{=no6=4={<601?b134>887=67:p0ac=838p19=8:e4891512:3<7p};dg83>7}:<:31h;5242:97<1<uz>n<7>52z?77g<c>27??l4<969~w1c62909w0:<d;f5?824k392;6s|4d094?4|5=9m6i84=51f>6?03ty?i>4?:3y>017=l?1689>53858yv2b<3:1>v3;428g2>;3<;085:5rs5g6>5<5s4>?97j9;<670?5>?2wx8h850;0x91202m<019:9:2;4?xu3m>0;6?u245;9`3=:<=21?494}r6f<?6=:r7?8o4k6:?70d<41>1v9k6:181823l3n=70:;c;1:3>{t<lk1<7<t=56e>a0<5=>n6>78;|q7ag<72;q688?5d79>006=;0=0q~:jc;296~;3=:0o:63;5380=2=z{=oo6=4={<661?b134>>87=67:p0`c=838p19;8:e4891312:3<7p};eg83>7}:<<31h;5244:97<1<uz>m<7>52z?71g<c>27?9l4<969~w1`62909w0::d;f5?822k392;6s|4g094?4|5=?m6i84=57f>6?03ty?j>4?:3y>037=l?168;>53858yv2a<3:1>v3;628g2>;3>;085:5rs5d6>5<5s4>=97j9;<650?5>?2wx8k850;0x91002m<01989:2;4?xu3n>0;6?u247;9`3=:<?21?494}r6e<?6=:r7?:o4k6:?72d<41>1v9h6:181821l3n=70:9c;1:3>{t<ok1<7<t=54e>a0<5=<n6>78;|q7bg<72;q68:?5d79>026=;0=0q~:ic;296~;3?:0o:63;7380=2=z{=lo6=4={<641?b134><87=67:p0cc=838p1998:e4891112:3<7p};fg83>7}:<>31h;5246:97<1<uz?;<7>52z?73g<c>27?;l4<969~w0662909w0:8d;f5?820k392;6s|51094?4|5==m6i84=55f>6?03ty><>4?:3y>0=7=l?1685>53858yv37<3:1>v3;828g2>;30;085:5rs426>5<5s4>397j9;<6;0?5>?2wx9=850;0x91>02m<01969:2;4?xu28>0;6?u249;9`3=:<121?494}r73<?6=:r7?4o4k6:?7<d<41>1v8>6:18182?l3n=70:7c;1:3>{t=9k1<7<t=5:e>a0<5=2n6>78;|q64g<72;q684?5d79>0<6=;0=0q~;?c;296~;31:0o:63;9380=2=z{<:o6=4={<6:1?b134>287=67:p15c=838p1978:e4891?12:3<7p}:0g83>7}:<031h;5248:97<1<uz?:<7>52z?7=g<c>27?5l4<969~w0762909w0:6d;f5?82>k392;6s|50094?4|5=3m6i84=5;f>6?03ty>=>4?:3y>0d7=l?168l>53858yv36<3:1>v3;a28g2>;3i;085:5rs436>5<5s4>j97j9;<6b0?5>?2wx9<850;0x91g02m<019o9:2;4?xu29>0;6?u24`;9`3=:<h21?494}r72<?6=:r7?mo4k6:?7ed<41>1v8?6:18182fl3n=70:nc;1:3>{t=8k1<7<t=5ce>a0<5=kn6>78;|q65g<72;q68o?5d79>0g6=;0=0q~;>c;296~;3j:0o:63;b380=2=z{<;o6=4={<6a1?b134>i87=67:p14c=838p19l8:e4891d12:3<7p}:1g83>7}:<k31h;524c:97<1<uz?9<7>52z?7fg<c>27?nl4<969~w0462909w0:md;f5?82ek392;6s|53094?4|5=hm6i84=5`f>6?03ty>>>4?:3y>0f7=l?168n>53858yv35<3:1>v3;c28g2>;3k;085:5rs406>5<5s4>h97j9;<6`0?5>?2wx9?850;0x91e02m<019m9:2;4?xu2:>0;6?u24b;9`3=:<j21?494}r71<?6=:r7?oo4k6:?7gd<41>1v8<6:18182dl3n=70:lc;1:3>{t=;k1<7<t=5ae>a0<5=in6>78;|q66g<72;q68i?5d79>0a6=;0=0q~;=c;296~;3l:0o:63;d380=2=z{<8o6=4={<6g1?b134>o87=67:p17c=838p19j8:e4891b12:3<7p}:2g83>7}:<m31h;524e:97<1<uz?8<7>52z?7`g<c>27?hl4<969~w0512908w0;<4;0`e>;2<l085:5255d96fg<uz?8;7>53z?671<5kk1698<5385890342;ij7p}:3983>6}:=:>1>nm4=475>6?034?>;7<la:p16?=839p18=;:3ag?832i392;63:5c81gd=z{<9j6=4<{<700?4dm27>9h4<969>10`=:jk0q~;<b;297~;2;=09ok5257097<1<5<<86?mn;|q67f<72:q69>;52bc890022:3<70;96;0`e>{t=:n1<76t=44e>6?634?=97=6a:?627<41h1698k538c8903f2:3j70;:6;1:e>;2=;085l5255g97<g<uz?8i7>52z?676<5kh169>:53838yv34n3:1>v3:3281gg=:=:?1?4?4}r774?6=;r7>9<4n6:?611<f>27>8i4<769~w0262908w0;:5;c5?83203k=70;:1;143>{t==81<7=t=47:>d0<5<?h6l84=476>6103ty>8>4?:2y>10b=i?169;>5a79>10?=;>=0q~;;4;297~;2>80j:63:658b2>;2=m08;:5rs466>5<5s4?=;7o9;<755?50?2wx99850;0x902b2m<018;?:2;2?xu2<>0;6?u25409`3=:=<>1?4?4}r77<?6=:r7>9;4k6:?61=<4181v8:6:181832i3n=70;:c;1:5>{t==k1<7<t=47f>a0<5<<;6>7>;|q60g<72;q69;<5d79>132=;0;0q~;;c;296~;2><0o:63:6680=4=z{<<36=4<{<77b?5>927>8i4<b19>106=;><0q~;99;297~;2=:085<5254397g6<5<??6>99;|q62d<72:q69895383890322:h;70;:8;142>{t=?h1<7=t=47a>6?634?>57=m0:?61f<4??1v88l:180832n392=63:5e80f5=:=?:1?:84}r75`?6=;r7>:>4<909>137=;k:0188;:255?xu2>l0;6?u257497<7<5<<<6>99;|q634<72>q694o5383890?62:3j70;7e;1:e>;20h085l5259497<g<5<296>7n;<74a?5>i2wx9:<50;1x90>62h<0186;:`48901c2:=<7p}:7283>6}:=1?1m;5259:9e3=:=1;1?:94}r740?6=;r7>444n6:?6<f<f>27>484<769~w0122908w0;7d;c5?83>83k=70;79;143>{t=><1<7<t=4;0>d0<5<2o6>98;|q632<72;q69:k5d79>1=6=;0;0q~;88;296~;20;0o:63:8580=4=z{<=26=4={<7;2?b134?347=61:p12g=838p186n:e4890>d2:3:7p}:7c83>7}:=1o1h;5258297<7<uz?<o7>52z?6=4<c>27>5>4<909~w0?32908w0;8f;1:5>;2?m08n=525929720<uz?297>53z?6<6<4181695?53c2890>32:==7p}:9783>6}:=1=1?4?4=4:6>6d734?347=86:p1<1=839p186m:2;2?83?139i<63:8b8033=z{<336=4<{<7;b?5>927>4i4<b19>1<6=;><0q~;69;296~;21;085<525819720<uz?j87>52z?6e1<418169o?52bg8yv3f=3:1>v3:a480=4=:=k;1>nj4}r7b2?6=:r7>m;4<909>1g7=:jh0q~;n7;296~;2i>085<525c196fc<uz?j47>52z?6e=<418169o?52bd8yv3f13:1>v3:a880=4=:=k91>nj4}r7be?6=:r7>ml4<909>1g5=:jh0q~;nb;296~;2ik085<525c696fc<uz?jo7>52z?6ef<418169o=52bd8yv3fl3:1>v3:ae80=4=:=k>1>nj4}r7ba?6=:r7>mh4<909>1g2=:jh0q~;nf;296~;2io085<525c696f`<uz?i<7>52z?6f5<41816:8752ba8yv3e93:1>v3:b080=4=:=k:1>nl4}r7a6?6=:r7>n?4<909>20?=:jh0q~;m3;296~;2j:085<525c296fg<uz?i87>52z?6f1<418169o<52bc8yv3e=3:1>v3:d18b2>;2n808;:5rs4`5>5<4s4?o=7o9;<7g0?g134?hm7=87:p1g1=839p18j::`4890b?2h<018j>:254?xu2j10;6>u25e;9e3=:=mi1m;525e79721<uz?i57>53z?6`a<f>27>i=4n6:?6`<<4?>1v8ln:18083b93k=70;j4;c5?83cl39<;6s|5c`94?5|5<o>6l84=4g;>d0<5<o:6>98;|q6ff<72:q69h75a79>1`e=i?169h;53658yv3el3:1?v3:ee8b2>;2n90j:63:e88032=z{<hn6=4<{<7e5?g134?m87o9;<7f`?50?2wx9oh50;0x90ee2m<018mk:2;2?xu2k90;6?u25bg9`3=:=m:1?4?4}r7`5?6=:r7>h?4k6:?6`1<4181v8m=:18183c>3n=70;k8;1:5>{t=j91<7<t=4fb>a0<5<nh6>7>;|q6g1<72;q69ik5d79>1`6=;0;0q~;l5;296~;2m;0o:63:e580=4=z{<i=6=4={<7f2?b134?n47=61:p1f1=838p18kn:e4890cd2:3:7p}:c983>7}:=lo1h;525g297<7<uz?h57>52z?6b7<c>27>j94<909~w0`22908w0;lc;1:5>;2kh08n=525bf9720<uz?m:7>52z?6gc<418169i>53648yv3a?3:1?v3:d280=4=:=m;1?o>4=4f7>6113ty>j54?:2y>1a1=;0;018j::2`3?83c039<:6s|5g;94?5|5<ni6>7>;<7g=?5e827>hn4<779~w0`f2908w0;kf;1:5>;2lm08n=525d29720<uz?mn7>53z?6a6<418169h?53c2890c32:==7p}:fb83>6}:=l=1?4?4=4g6>6d734?n47=86:p1cb=839p18km:2;2?83b139i<63:eb8033=z{<ln6=4<{<7fb?5>927>ii4<b19>1c6=;><0q~;if;297~;2n:085<525g397g6<5<l?6>99;|q545<72=q6:kj5385890g621n018o=:6a890g42>i0q~8?1;290~;089085:525`39<`=:=h81;i525`193a=z{?:96=4;{<537?5>?27>m<47f:?6e7<0m27>m>48e:p255=83>p1:>9:2;4?83f933;70;n2;5e?83f;3=m7p}90583>1}:?931?494=4c2><7<5<k965>4=4c0>=6<uz<;97>54z?44f<41>169l?5939>1d4=?8169l=5709~w361290?w09?f;1:3>;2i803963:a3846>;2i:0<>6s|61594?2|5>;96>78;<7b5?>134?j>79<;<7b7?143ty=<54?:5y>343=;0=018o>:95890g52>>018o<:668yv0713:18v381980=2=:=h;144525`0930=:=h91;85rs72b>5<4s4=o;7=67:?ae6<5kk169l<511c8yv07j3:1>v3;dc80=2=:=h81=?o4}r43g?6=:r7??84<969>1d4=99h0q~8?d;296~;3;>085:525`0955e<uz<;i7>52z?77<<41>169l<511f8yv07n3:1>v3;3c80=2=:=h81==k4}r424?6=:r7??i4<969>1d4=99l0q~8>1;296~;3;o085:525`09546<uz<:>7>52z?704<41>169l<51578yv06;3:1>v3;4280=2=:=h91==o4}r420?6=:r7?884<969>1d5=98?0q~8>5;296~;3;:085:525`09543<uz<::7>52z?702<41>169l=51328yv06?3:1>v3;4c80=2=:=h91=?:4}r42<?6=:r7?8i4<969>1d5=9;?0q~8>9;296~;3<o085:525`19570<uz<:m7>52z?714<41>169l=51358yv06j3:1>v3;5280=2=:=h91=?64}r42g?6=:r7?984<969>1d5=9=>0q~8>d;296~;3=>085:525`1957?<uz<:i7>52z?71<<41>169l=513c8yv06n3:1>v3;5c80=2=:=h91==l4}r414?6=:r7?844<969>1d4=9;:0q~8=1;296~;3=m085:525`1955e<uz<9>7>52z?724<41>169l=511f8yv05;3:1>v3;6280=2=:=h91==k4}r410?6=:r7?:84<969>1d5=99l0q~8=5;296~;3>>085:525`19546<uz<9:7>52z?72<<41>169l=51578yv05?3:1>v3;5g80=2=:=h81=?:4}r41<?6=:r7?;k4<969>1d4=98;0q~8=9;296~;308085:525`09544<uz<9m7>52z?7<6<41>169l<51018yv05j3:1>v3;8480=2=:=h81=<:4}r41g?6=:r7?4:4<969>1d4=98<0q~8=d;296~;3?<085:525`09573<uz<9i7>52z?7<<<41>169l<51058yv05n3:1>v3;8e80=2=:=h81=<64}r404?6=:r7?4k4<969>1d4=9830q~8<1;296~;318085:525`09510<uz<8>7>52z?7=6<41>169l<510c8yv04;3:1>v3;9480=2=:=h81=<l4}r400?6=:r7?5:4<969>1d4=98i0q~8<5;296~;310085:525`0954b<uz<8:7>52z?7=g<41>169l<510g8yv04?3:1>v3;9e80=2=:=h81=<h4}r40<?6=:r7?4o4<969>1d4=9;<0q~8<9;296~;31o085:525`09577<uz<8m7>52z?7e6<41>169l<51318yv04j3:1>v3;a480=2=:=h81=964}r40g?6=:r7?m:4<969>1d5=98;0q~8<d;296~;3i0085:525`19544<uz<8i7>52z?7eg<41>169l=51018yv04n3:1>v3;ae80=2=:=h91=<:4}r474?6=:r7?mk4<969>1d5=98<0q~8;1;296~;3j8085:525`19541<uz<?>7>52z?7f6<41>169l=510:8yv03;3:1>v3;a080=2=:=h81=?94}r470?6=:r7?n84<969>1d5=9830q~8;5;296~;3j0085:525`19510<uz<?:7>52z?7fg<41>169l=510c8yv03?3:1>v3;be80=2=:=h91=<l4}r47<?6=:r7?nk4<969>1d5=98i0q~8;9;296~;3k8085:525`1954b<uz<?m7>52z?7g6<41>169l=510g8yv03j3:1>v3;c480=2=:=h91=<h4}r47g?6=:r7?o:4<969>1d5=9;;0q~8;d;296~;3k0085:525`19575<uz<?i7>52z?7f2<41>169l<513:8yv03n3:1>v3;cc80=2=:=h91=964}r464?6=:r7?oi4<969>1d4=9=>0q~8:1;296~;3l0085:525`0957?<uz<>>7>5dz?5=c<41>169l?5b76890g62k<870;n1;`56>;2i80i:<525`09f0e<5<k96o8?;<7b6?d2m27>m?4m5e9>1d5=j<i018o<:c43?83f;3h>i63:a28a1a=z{??86=4k{<7:f?5>?27>m94=c`9>1d3=:jk018o9:3ab?83f038hm63:a681gd=:=h31>no4=4cb>7ef34?jo7<la:?6eg<5kh169lj52bc890gb2;ij70;nf;0`e>{t><>1<7jt=4;`>6?034?j87<lc:?6e0<5kj169l852ba890g?2;ih70;n7;0`g>;2i009on525`c96fe<5<kh6?ml;<7bf?4dk27>mi4=cb9>1dc=:ji018oi:3a`?xu1=<0;69u258f97<1<5<h:6?mn;<7a7?4di27>n94=c`9~w331290?w0;6e;1:3>;2j809on525c196fe<5<h?6?ml;|q512<72:q694h5385890d72:h;70;m2;1a4>{t><21<7<t=4c3>6?034<>57<la:p20g=83>p187m:e4890172;ij70;8e;1:3>;2?o09ol5rs77a>5<3s4?2o7j9;<744?4dj27>4?4<969>1=5=:jk0q~8:c;290~;21m0o:63:7181gf=:=1<1?494=4:4>7ef3ty=9i4?:5y>1<c=l?169:>52bf890>f2:3<70;7b;0`e>{t><o1<7:t=4;e>a0<5<=;6?mj;<7;a?5>?27>4k4=c`9~w33a290?w0;n0;f5?830838hj63:9080=2=:=081>no4}r454?6=:r7>??4<909>1<g=:jh0q~891;296~;2i>09oh525`0951e<uz<=>7>52z?6ed<5kk169l<517a8yv01;3:1>v3:a`81gc=:=h81=9j4}r450?6=:r7>mn4=cd9>1d4=9=o0q~895;296~;2ij09oi525`0951`<uz<=:7>52z?6ef<5kk169l<51428yv01?3:1>v3:ab81gc=:=h81=8?4}r45<?6=:r7>m94=cd9>1d4=9<80q~899;296~;2i=09oi525`095g5<uz<=m7>52z?6e1<5kk169l=515a8yv01j3:1>v3:a581gc=:=h91=894}r45g?6=:r7>m:4=ce9>1d4=9<=0q~89d;296~;2i<09oh525`19534<uz<=i7>52z?6e0<5km169l=51748yv01n3:1>v3:a481gg=:=h91=;94}r444?6=:r7>m84=cg9>1d5=9?20q~881;296~;2i?09oh525`1953?<uz<<>7>52z?6e3<5km169l=517c8yv00;3:1>v3:a781gg=:=h91=o<4}r440?6=:r7>m;4=cg9>1d5=9?h0q~885;296~;2i109oh525`1953e<uz<<:7>52z?6e=<5km169l=515f8yv00?3:1>v3:a681gg=:=h81=;<4}r44<?6=:r7>m54=cc9>1d5=9=o0q~889;296~;2i109ok525`1951`<uz<<m7>52z?6eg<5kl169l=51428yv00j3:1>v3:ac81ga=:=h91=8?4}r44g?6=:r7>mo4=cc9>1d5=9<80q~88d;296~;2ik09ok525`195g5<uz<<i7>52z?6ea<5kl169l?517f8yv00n3:1>v3:ae81ga=:=h;1=:;4}r4;4?6=:r7>mi4=cc9>1d7=9><0q~871;296~;2im09ok525`39521<uz<3>7>52z?6e2<5ko169l<51748yv0?;3:1>v3:ad81g`=:=h;1=:64}r4;0?6=:r7>mh4=ce9>1d7=9>30q~875;296~;2il09oo525`3952g<uz<3:7>52z?6e`<5ko169l?516`8yv0??3:1>v3:ag81gg=:=h;1=o94}r4;<?6=:r7>m44=cd9>1d4=9?=0q~879;296~;2i009oi525`0953><uz<3m7>52z?6e<<5kk169l<517;8yv0?j3:1>v3:a881gc=:=h81=;o4}r4;g?6=:r7>ml4=cd9>1d4=9k80q~87d;296~;2ih09oi525`0953d<uz<3i7>55z?6gg<41>169nm52bc890g62?<018o=:4:890g42<20q~87f;291~;2kl085:525bd96fg<5<k:6;=4=4c1>04<5<k868<4}r4:4?6==r7>h?4<969>1a5=:jk018o>:75890g52<3018o<:4;8yv0>93:19v3:d780=2=:=m=1>no4=4c2>3><5<k968o4=4c0>0g<uz<2>7>55z?6`d<41>169il52bc890g62?3018o=:4`890g42<h0q~863;291~;2ll085:525ed96fg<5<k:6;o4=4c1>0e<5<k868m4}r4:0?6==r7>i?4<969>1`5=:jk018o>:7`890g52<n018o<:4f8yv0>=3:19v3:e780=2=:=l=1>no4=4c2>3e<5<k969k4=4c0>1c<uz<2:7>55z?6ad<41>169hl52bc890g62<l018o=:5d890g42=l0q~867;291~;2ml085:525dd96fg<5<k:6;>4=4c1>06<5<k868>4}r4:<?6==r7>j?4<969>1c5=:jk018o>:73890g52<;018o<:438yv0>13:1ov3:3080=4=:=jo1m9525g09e1=:=lo1m9525dc9e1=:=l<1m9525d09e1=:=mo1m9525ec9e1=:=m<1m9525e09e1=:=jh1m95rs7;b>5<3s4?8>7<lb:?674<5kh169>=53838900a2;ij7p}99c83>6}:=:;1>nl4=4;b>7ef34?<<7=61:p2<b=83>p1:j7:2;b?81c1392m638d580=d=:>h21?4?4}r4b0?6=:r7=m=4k6:?5e4<4181v;o::18180f:3n=708n3;1:=>{t>h<1<7<t=7c2>7ef34<j?7=67:p2d1=838p1;o>:3aa?80f:392;6s|6``94?4|5?k26i84=7cb>6?>3ty=mn4?:3y>2d>=:jk01;on:2;4?xu1im0;6?u26`:96fd<5?k26>78;|q5f3<72;q6:o?52bc893ga2:3:7p}9b683>7}:>k;1>nl4=7`3>6?63ty=n54?:3y>2dc=l?16:o?53838yv0e13:1>v39b58g2>;1j<08545rs7`b>5<5s4<i?7j9;<4a0?5>12wx:ol50;0x93d52m<01;l<:2;:?xu1jj0;6?u26`d96fg<5?h>6>78;|q5fa<72;q6:lh52b`893d32:3<7p}9bd83>7}:>k:1>no4=7`0>6?03ty=nk4?:3y>2g6=:jh01;l=:2;4?xu1k10;6?u26b196fg<5?i:6>7>;|q5g<<72;q6:n=52b`893e52:3:7p}9c`83>7}:>j:1h;526b197<7<uz<hn7>52z?5g3<c>27=o:4<989~w3ed2909w08l5;f5?80d>39256s|6bf94?4|5?i?6i84=7a6>6?>3ty=oh4?:3y>2f7=:jk01;m8:2;4?xu1ko0;6?u26b396fd<5?i=6>78;|q5`5<72;q6:n<52bc893e22:3<7p}9d083>7}:>j81>nl4=7a7>6?03ty=h:4?:3y>2a3=l?16:i8538;8yv0c03:1>v39d581gd=:>m<1?494}r4g=?6=:r7=h94=cc9>2a3=;0=0q~8kd;29g~;11l0o:639d380=2=:?<81m95275d9e1=:?=h1m9527559e1=:?=91m95272d9e1=:?:h1m9527259e1=:?:91m95273d9e1=z{?nn6=4={<5g0?b134=j97<l6:p2a`=838p1:j;:`6893b42:3<7p}9e183>f}:?m>1?494=7`1>1?<5?h86974=7`7>1?<5?h>6974=7a7>1?<5?i>6974=7a5>1?<5?i<6974=7c;>6d734<o87=m0:?5`6<312wx:h?50;`x93b32:3:709:2;1:e>;0<o085l5275`97<g<5>><6>7n;<577?5>i27<?k4<9`9>36d=;0k01:=8:2;b?814;392m6382g80=d=z{?o96=4={<4eb?b134<mi7=61:p2`5=838p1:>=:e4892662:3:7p}9e583>7}:?9?1h;5271697<7<uz<n97>52z?44=<c>27<<:4<909~w3c12909w09?b;f5?817i392=6s|6d594?4|5>:n6i84=62g>6?63ty=i54?:3y>347=l?16;<>53838yv0b13:1>v38158g2>;09:085<5rs7gb>5<5s4=:;7j9;<522?5>92wx:hl50;0x927f2m<01:?6:2;2?xu09k0;6>u27209e3=:?:?1m;5273g9721<uz=:o7>53z?473<f>27<?44n6:?477<4?>1v:?k:180814i3k=709<d;c5?814>39<;6s|70g94?5|5>9n6l84=662>d0<5>9j6>98;|q45c<72:q6;9<5a79>313=i?16;>k53658yv1583:1?v38478b2>;0<00j:638438032=z{>8:6=4<{<57e?g134=?h7o9;<572?50?2wx;?<50;1x922b2h<01:;>:`48922f2:=<7p}82283>7}:?<>1m;5275g9721<uz=987>52z?46c<c>27<?<4<909~w2422909w09<3;f5?814=392=6s|73494?4|5>9<6i84=61:>6?63ty<>:4?:3y>36d=l?16;>j53838yv1503:1>v383g8g2>;0<8085<5rs60:>5<5s4=??7j9;<571?5>92wx;?o50;0x92202m<01::6:2;2?xu0:k0;6?u275`9`3=:?=n1?4?4}r51g?6=:r7<8k4k6:?414<4181v:<k:181812:3n=709:4;1:5>{t?<?1<7=t=613>6?634=9i7=m0:?474<4??1v:;9:180814<392=6383380f5=:?:?1?:84}r563?6=;r7<?54<909>360=;k:01:=6:255?xu0=10;6>u272a97<7<5>9j6>l?;<50`?50>2wx;8750;1x92272:3:709<e;1a4>;0<808;;5rs67b>5<4s4=?87=61:?407<4j916;9;53648yv12j3:1?v384980=4=:?=<1?o>4=66:>6113ty<9n4?:2y>31e=;0;01::n:2`3?813l39<:6s|74f94?5|5>?;6>7>;<57a?5e827<9<4<779~w23b2909w09:3;1:5>;0==08;;5rs67e>5<4s4=<:7o9;<54=?g134=<>7=87:p336=839p1:9n:`48921c2h<01:99:254?xu0>80;6>u276g9e3=:?1;1m;5276c9721<uz==>7>53z?4<7<f>27<484n6:?43`<4?>1v:8<:18081?>3k=70979;c5?81?:39<;6s|77694?5|5>2j6l84=6:g>d0<5>2=6>98;|q420<72:q6;5k5a79>3<7=i?16;5o53658yv11>3:1?v38938b2>;01<0j:6388d8032=z{><<6=4={<5:<?g134=2>7=87:p33>=838p1:9<:e4892122:3:7p}86883>7}:?>=1h;5276;97<7<uz==m7>52z?43g<c>27<;i4<909~w20e2909w098f;f5?81?9392=6s|77a94?4|5>286i84=6:6>6?63ty<:i4?:3y>3=1=l?16;5753838yv11m3:1>v388c8g2>;00m085<5rs64e>5<5s4=3j7j9;<5:5?5>92wx;:>50;0x92?42m<01:7::2;2?xu0?80;6?u27849`3=:?021?4?4}r5:=?6=;r7<;94<909>324=;k:01:9::255?xu01h0;6>u276:97<7<5>==6>l?;<54=?50>2wx;4l50;1x921d2:3:7098a;1a4>;0?m08;;5rs6;`>5<4s4=3<7=61:?43`<4j916;5?53648yv1>l3:1?v388580=4=:?181?o>4=6:6>6113ty<5h4?:2y>3=>=;0;01:69:2`3?81?139<:6s|78d94?5|5>2h6>7>;<5;e?5e827<4i4<779~w2g72908w0960;1:5>;00l08n=527839720<uz=j=7>53z?4=1<41816;4<53c2892?22:==7p}8a383>7}:?0=1?4?4=6;;>6113ty<mo4?:3y>2ce=;0=01:o::2f1?xu0ij0;6?u27`196fg<5>k>6>j<;|q4ea<72;q6;l=5383892g02:n97p}8ad83>7}:?h>1>no4=6c4>6b43ty<mk4?:3y>3d2=;0;01:o6:2f1?xu0j90;6>u26g`97<1<5?oo6i84=63:>7ed3ty<n<4?:3y>2`b=;0=01;kj:e48yv1e:3:1>v39ed80=2=:>ll1h;5rs6`0>5<5s4<nj7=67:?5b5<c>2wx;o:50;0x93`72:3<708i1;f5?xu0j<0;6?u26g397<1<5?l96i84}r5a2?6=:r7=j?4<969>2ce=l?1v:l8:18080bk392;639f28g2>;1nl09on5rs6`;>5<4s4<m?7=67:?5b1<c>27<<<4=cb9~w2d>2908w08i4;1:3>;1n<0o:6380581gf=z{>hj6=4<{<4e1?5>?27=j;4k6:?442<5kj1v:lm:18080a>392;639f68g2>;08h09on5rs6``>5<4s4<m;7=67:?5b=<c>27<<i4=cb9~w2dc2908w08i8;1:3>;1n00o:6381181gf=z{>hn6=4<{<4e=?5>?27=jl4k6:?456<5kj1v:li:18080ai392;639fc8g2>;09?09on5rs6a3>5<5s4<mj7=67:?5ba<c>2wx;n?50;0x92652:3<709?0;f5?xu0k;0;6?u271797<1<5>:86i84}r5`7?6=:r7<<54<969>350=l?1v:m;:181817j392;638088g2>{t?j?1<7<t=62f>6?034=;o7j9;|q4g3<72;q6;<?53858926a2m<0q~9l7;296~;09=085:527009`3=z{>i36=4={<523?5>?27<=84k6:p3f?=838p1:?n:2;4?81603n=7p}8c`83>1}:>oo1>nl4=60e>6?034=8<7<la:?4e0<6m11v:mm:187817938hn6383280=2=:?:>1>no4=6c6>7303ty<on4?:5y>352=:jh01:=8:2;4?814038hm638a48132=z{>io6=4;{<533?4dj27<?o4<969>36e=:jk01:o::3:1?xu0kl0;69u271c96fd<5>9m6>78;<574?4di27<m84=8e9~w2ea290?w09?d;0`f>;0<:085:5275696fg<5>k>6?77;|q4`5<72=q6;<>52b`892202:3<709;8;0`e>;0i<09m>5rs6f2>5<3s4=:?7<lb:?40g<41>16;9m52bc892g22;kn7p}8d383>1}:?8<1>nl4=66e>6?034=><7<la:?4e0<5j01v:j<:187816138hn6385380=2=:?<91>no4=6c6>7e23ty<hl4?:cy>2ag=;0=01:79:`6892?42h>01:6i:`6892>e2h>01:68:`6892>42h>01:9i:`68921e2h>01:98:`6892142h>0q~9kb;296~;0l10o:638a681g3=z{>nh6=4={<5g<?g334<on7=67:p3ab=83?p1:j7:2;4?80e939i<639c280f5=:>h;1?o>4=7fa>1?<uz=oi7>52z?4`<<c>27<m44=c79~w2ba2909w09k9;c7?80ck392;6s|7d294?e|5>n26>78;<4a4?5e827=mk4<b19>2f4=;k:01;m>:2`3?80f13>2708na;6:?80c=3>2708k6;6:?80f:3>2708n3;6:?80ck3>27p}8e083>7}:>j=1h;527`;97a5<uz=n>7>52z?5f0<c>27=o94<989~w2c42909w08m2;1:=>;1l?0o:6s|7d694?4|5?nj6i84=7f6>6?>3ty<i84?:3y>2a4=l?16:io538:8yv1b>3:1>v39d380===:>hk1h;5rs6g4>5<5s4<j57=69:?5e6<c>2wx;h650;0x93g52:32708k3;f5?xu0m00;6?u26ea9`3=:>m91?474}r5fe?6=:r7=ho4k6:?5`f<4101v:km:18180>m392;6399g8g2>{t?li1<7<t=6f5>a0<5>n>6>7>;|q4aa<72;q6;i85385892b02m<0q~9ib;297~;?::09ol5280497<1<51;<6i84}r5eg?6=:r73><4<969><75=:jh0q~9id;29=~;0n:08n=527g697g6<5>l>6>l?;<5e2?5e827<j:4<b19>3c>=;k:01:h6:2`3?81ai39i<6372380=4=z{>ln6=4={<:16?4dl273>>4<909~w=6>2909w06?8;1:3>;?880o:6s|81c94?3|51:36lj4=922>db<51:96lj4=924>db<5>lm6>7>;|q;4g<72:q64=?538589=652m<015>?:e48yv>7k3:1>v370380=2=:09:1?4o4}r:3`?6=;r73<=4<969><51=i=164=95d79~w=6b2909w06?7;1:3>;?8:0o:6s|81d94?4|51:86>78;<:30?b13ty3==4?:3y><52=;0=015>::e48yv>693:1>v370780=2=:?ol1>no4}r:2e?6=:r73=44<969><42=l?1v5?m:1868>613ko706>4;cg?8>6=3ko706>8;cg?8>6:392=6s|80a94?5|51;?6>78;<:21?b1342:?7j9;|q;5a<72;q64<;538589=742:3j7p}71d83>6}:0891?494=93;>d2<51;36i84}r:2b?6=:r73=54<969><40=l?1v5<?:1818>6?392;6371381gd=z{18>6=4={<5e7?b1342987=61:p<70=838p157=:`f89=>c2:3<7p}72683>7}:0081?494=956>7ef3ty3>54?:3y><00=;0=0156l:3a`?xu?:00;6>u284597<1<51>=6?mm;<:41?4dl2wx4?o50;1x9=3?2:3<706;6;0`g>;??<09on5rs90a>5<4s42>57=67:?;03<5kh164:;52b`8yv>5k3:1?v37568g2>;?=10o:6374780=4=z{18o6=4;{<:5<?b1342>o7=67:?;25<f<273:=4k6:p<7c=83?p1587:2;4?8>113n=7067c;0`f>;?=h09oo5287c96fd<uz29j7>54z?;2<<41>1645m52bc89=3f2;ij7069a;0`e>{t0::1<7=t=9;5>d2<513>6l:4=97b>6?63ty38:4?:3y><6e=;0=0159n:3ab?xu?<10;6?u282f97<1<51=36?mi;|q;0<<72;q64>k538589=1>2;ii7p}74`83>7}:0:l1?494=954>7ee3ty38o4?:3y><16=;0=0159n:3aa?xu?<j0;6?u285397<1<51=36?mk;|q;0a<72;q649<538589=1>2;io7p}74d83>7}:0=91?494=954>7ef3ty38k4?:3y><12=;0=0159n:3a`?xu?=90;6?u285797<1<51=36?mn;|q;14<72kq649;5a59><12=i=1649=5a59><14=i=1649?5a59><16=i=164>h5a59><6c=i=164>j5a59><6e=i=1645m53838yv>2:3:1>v379480=2=:0>81>nl4}r:67?6=:r735;4<969><27=:jk0q~6:4;296~;?lk0o:6378880=4=z{1?>6=4<{<:61?5>?27im94=c`9><24=:ji0q~692;296~;?>8085:5284f9`3=z{1<86=4:{<:55?gc342>h7ok;<:6a?gc342=<7ok;<:6f?5>92wx4;:50;1x9=3c2:3<706:e;f5?8>2k3n=7p}76483>7}:0<o1?494=97`>6?f3ty3:;4?:3y><36=;0=015;i:e48yv>1?3:1>v375g80=2=:0<h1>no4}r:5f?6=:r73;94=c`9><3d=;0=0q~69c;297~;?>j085:52b`096fg<51=96?mn;|q;2a<72;q64;h52ba89=0c2:3:7p}76g83>7}:0?l1?4?4=95g>7ec3ty3;<4?:3y><27=;0;01599:3ag?xu??;0;6?u286097<7<51==6?mj;|q;36<72;q64:=538389=>e2;ih7p}77583>7}:0>>1?4?4=955>7ed3ty3;84?:3y><23=;0;01599:3ae?xu???0;6?u286497<7<51=o6?mj;|q;32<72;q64:9538389=1d2;ih7p}77983>7}:0>21?4?4=95`>7ea3ty3;44?:3y><2?=;0;0159l:3ag?xu??h0;6?u286c97<7<51=h6?mm;|q;3g<72;q64:l538389=1d2;in7p}77b83>7}:0>i1?4?4=95g>7ea3ty3;i4?:3y><2b=;0;01566:3ae?xu??l0;6?u286g97<7<512i6?mk;|q;3c<72;q64:h538389=>72;io7p}78183>7}:01:1?4?4=9::>7ef3ty34<4?:3y><=7=;0;0156<:3af?xu?0;0;6?u289097<7<51286?mi;|q;<6<72;q645=538389=>>2;io7p}78583>7}:01>1?4?4=9:a>7eb3ty34l4?:3y><=g=;0;0156m:3aa?xu?0k0;6?u289`97<7<51<m6?mj;|q;=5<72:q645k538589=>a2m<0156k:2;b?xu?180;6?u289d97<1<512o6i84}r::3?6=;r73mh4n6:?;f4<f>273ml4<769~w=??2908w06m2;c5?8>e=3k=706ne;143>{t0031<7=t=9`5>d0<51h26l84=9`1>6103ty35l4?:2y><gg=i?164oj5a79><g0=;>=0q~66b;297~;?jl0j:637c08b2>;?jh08;:5rs9;`>5<4s42h>7o9;<:`1?g1342ii7=87:p<<b=839p15m9:`489=e>2h<015m=:254?xu?1l0;6>u28bc9e3=:0jn1m;528b49721<uz22j7>52z?;`5<f>273ol4<769~w=g72909w06nb;f5?8>fl392=6s|8`394?4|51km6i84=9`2>6?63ty3m?4?:3y><g5=l?164o;53838yv>f;3:1>v37b68g2>;?j0085<5rs9c7>5<5s42in7j9;<:a`?5>92wx4l;50;0x9=da2m<015m>:2;2?xu?i?0;6?u28b19`3=:0j?1?4?4}r:b3?6=:r73o:4k6:?;g<<4181v5o7:1818>dj3n=706ld;1:5>{t0h31<7<t=9af>a0<51n;6>7>;|q;`4<72:q64lm538389=gf2:h;706nd;142>{t0m81<7=t=9`3>6?6342ji7=m0:?;f4<4??1v5j<:1808>e<392=637b380f5=:0k?1?:84}r:g0?6=;r73n54<909><g0=;k:015l6:255?xu?l<0;6>u28ca97<7<51hj6>l?;<:a`?50>2wx4i850;1x9=e72:3:706me;1a4>;?k808;;5rs9f4>5<4s42h87=61:?;g7<4j9164n;53648yv>c03:1?v37c980=4=:0j<1?o>4=9a:>6113ty3h44?:2y><fe=;0;015mn:2`3?8>dl39<:6s|8ec94?4|51im6>7>;<:g4?50>2wx4im50;1x9=bd2:3<70ln3;0`e>;??809oo5rs9fg>5<5s428=7=61:?;<7<5kk1v5jj:1818>4:392=6378081ga=z{1nm6=4<{<:07?5>92734;4=ce9><=1=:jk0q~6j0;296~;?;=085<5289396fe<uz2n=7>52z?;70<4181645>52ba8yv>b:3:1>v373780=4=:0191>nj4}r:f7?6=;r73?:4<909><=0=:ji01568:3ae?xu?m=0;6?u282:97<7<512;6?mj;|q;a0<72;q64>7538389=>72;im7p}7e783>7}:0:k1?4?4=9:1>7ec3ty3i:4?:2y><6d=;0;01569:3af?8>??38hh6s|8d:94?4|51386>7>;<::0?4d12wx4h750;`x9=?32:3:706le;1:e>;?kk085l528b597<g<51i86>7n;<:ab?5>i273no4<9`9><g1=;0k015l<:2;b?8>fn392m637ac80=d=z{1oj6=4>1z?;77<5kh164>l52bc89=5f2;ij706<9;0`e>;?;109ol5282596fg<519=6?mn;<:01?4di273?94=c`9><65=:jk015=>:3ab?8>fj392;637ab81gd=:0>i1>no4=952>7ed342<>7<ld:?;30<5kl1v5km:1822~;?;;09oo5282`96fd<519j6?mm;<:0=?4dj273?54=cc9><61=:jh015=9:3aa?8>4=38hn6373581gg=:0:91>nl4=912>7ee342jj7=67:?;f5<5kh164::52b`89=1?2;in70689;0`g>;??k09oi5286396fc<51=96?mi;<:41?4dn273;:4=ce9><2g=:jl0q~6jc;2950}:0:81>nm4=91a>7ed3428m7<lc:?;7<<5kj164>652ba89=502;ih706<6;0`g>;?;<09on5282696fe<51986?ml;<:05?4dk273n>4<969><g2=:jk01597:3a`?8>0138hm6377c81g`=:0>;1>nj4=951>7eb342<;7<lc:?;3d<5kl164:852b`8yv>bl3:1=<u282096fb<519i6?mk;<:0e?4dl273?44=ce9><6>=:jn015=8:3ag?8>4>38hh6373481ga=:0:>1>nj4=910>7ec3428=7<ld:?;f2<41>164o652bc89=1?2;ii7068b;0`f>;???09ol5286c96fb<uz2ni7>59z?;fg<41>164om52bc89=1e2;ih70670;0`e>;?0009oo5286296fe<512>6?mn;<:4`?4dj273454=ce9~w=ca290iw06mf;1:3>;?k909ol5286`96fg<51=m6?mn;<:;5?4dj2734?4=cb9><26=:jh0156::3aa?8>0l38ho6378281gf=:0121>nk4}r:e4?6=?r73o>4<969><f2=:jk0156?:3aa?8>?;38hm6377181ga=:01<1>nl4=9:4>7ee3ty3j<4?:8y><f1=;0=015m7:3ab?8>0n38hn6378081gd=:0181>no4=953>7ef3423:7<la:?;<2<5kj1645=52b`8yv>a:3:19v37cc80=2=:0ji1>no4=94e>7ec342397<ld:?;<=<5kk1v5h<:1868>dm392;637cg81gd=:0?l1>no4=9:6>7ed342347<lc:p<c?=838p15h7:e489=`02:3<7p}7fc83>7}:0ok1h;528g:97<1<uz2mi7>52z?;ba<c>273jn4<969~w<672909w06if;f5?8>al392;6s|91394?5|51l=6i84=9db>6?0342m97<la:p=54=838p15hl:2;;?8>a?3n=7p}60283>7}:1891h;5291697<1<uz3;57>52z?:4d<c>272<n4<909~w<6c2909w07?c;142>;>8k085<5rs82f>5<4s43;m7=67:?:4g<5kh165<:51d:8yv?7n3:1>v360`8b0>;>8<085:5rs833>5<3s43;:7:=;<;30?27343;97:>;<;20?4d>2wx5<?50;0x9<6f2:3j707?6;1:3>{t18<1<7<t=825>a0<50:<6>7>;|q:52<72;q65=8538:89<622m<0q~7>8;296~;>8=0o:6360480===z{0;26=4={<;30?5>0272<54=c`9~w<7f2909w07?8;1:5>;>9=08h?5rs83a>5<5s43:>7<la:?:51<4l:1v4?l:1818g0;3n=707l7;0`2>{t1j31<7=t=83g>6?0343<>7j9;<;`3?7b02wx5no50;1x9<7b2:3<70783;f5?8?d?38<>6s|9b`94?5|50;m6>78;<;40?b1343h;7<84:p=fe=839p14<?:2;4?8?0=3n=707l7;04<>{t1jn1<7=t=802>6?0343<:7j9;<;`3?40i2wx5nk50;1x9<452:3<70787;f5?8?d?38<h6s|9bd94?5|50886>78;<;4<?b1343h;7<8f:p=a6=839p14<;:2;4?8?013n=707l7;0;7>{t1m;1<7=t=806>6?0343<m7j9;<;`3?4?=2wx5i<50;1x9<412:3<7078b;f5?8?d?38346s|9e194?5|508<6>78;<;4g?b1343h;7<7a:p=a2=839p14<7:2;4?8?0l3n=707l7;043>{t1m?1<7=t=80:>6?0343<i7j9;<;`3?4?m2wx5i850;1x9<4f2:3<7078f;f5?8?d?382<6s|9e594?5|508i6>78;<;;4?b1343h;7<63:p=a>=839p14<l:2;4?8??93n=707l7;0:1>{t1m31<7=t=80g>6?03433>7j9;<;`3?4>12wx5io50;1x9<4b2:3<70773;f5?8?d?382n6s|9e`94?5|508m6>78;<;;0?b1343h;7<6e:p=ae=839p14=?:2;4?8??=3n=707l7;0b4>{t1mn1<7=t=812>6?03433:7j9;<;`3?4f<2wx5ik50;1x9<552:3<70777;f5?8?d?38j:6s|9ed94?5|50986>78;<;;<?b1343h;7<68:p=`6=839p14=;:2;4?8??13n=707l7;0b=>{t1l;1<7=t=816>6?03433m7j9;<;`3?4fj2wx5h<50;1x9<512:3<7077b;f5?8?d?38jj6s|9d194?5|509<6>78;<;;g?b1343h;7<m1:p=`2=839p14=7:2;4?8??l3n=707l7;0a0>{t1l?1<7=t=81:>6?03433i7j9;<;`3?4e>2wx5h850;1x9<5f2:3<7077f;f5?8?d?38im6s|9d594?5|509i6>78;<;:4?b1343h;7<mc:p=`>=839p14=l:2;4?8?>93n=707l7;0ab>{t1l31<7=t=81g>6?03432>7j9;<;`3?4d92wx5ho50;1x9<5b2:3<70763;f5?8?d?38ji6s|9d`94?5|509m6>78;<;:0?b1343h;7?j9:p=`e=839p14:?:2;4?8?>=3n=707l7;3ff>{t1ln1<7=t=862>6?03432:7j9;<;`3?7bm2wx5hk50;1x9<252:3<70767;f5?8?d?3;m<6s|9dd94?5|50>86>78;<;:<?b1343h;7?i4:p=c6=839p14:;:2;4?8?>13n=707l7;3e2>{t1o;1<7=t=866>6?03432m7j9;<;`3?7a12wx5k<50;1x9<212:3<7076b;f5?8?d?3;mn6s|9g194?5|50><6>78;<;:g?b1343h;7?if:p=c2=839p14:7:2;4?8?>l3n=707l7;035>{t1o?1<7=t=86:>6?03432i7j9;<;`3?7a;2wx5k850;1x9<2f2:3<7076f;f5?8?d?38;86s|9g594?5|50>i6>78;<;b4?b1343h;7<?6:p=c>=839p14:l:2;4?8?f93n=707l7;03e>{t1o31<7=t=86g>6?0343j>7j9;<;`3?47k2wx5ko50;1x9<2b2:3<707n3;f5?8?d?38;j6s|9g`94?5|50>m6>78;<;b0?b1343h;7<>1:p=ce=839p14;?:2;4?8?f=3n=707l7;021>{t1on1<7=t=872>6?0343j:7j9;<;`3?46?2wx5kk50;1x9<352:3<707n7;f5?8?d?38:m6s|9gd94?5|50?86>78;<;b<?b1343h;7<>c:pe56=839p14;;:2;4?8?f13n=707l7;03=>{ti9;1<7=t=876>6?0343jm7j9;<;`3?4582wxm=<50;1x9<312:3<707nb;f5?8?d?389>6s|a1194?5|50?<6>78;<;bg?b1343h;7<=5:pe52=839p14;7:2;4?8?fl3n=707l7;013>{ti9?1<7=t=87:>6?0343ji7j9;<;`3?45j2wxm=850;1x9<3f2:3<707nf;f5?8?d?389h6s|a1594?5|50?i6>78;<;a4?b1343h;7<<0:pe5>=839p14;l:2;4?8?e93n=707l7;006>{ti931<7=t=87g>6?0343i>7j9;<;`3?44>2wxm=o50;1x9<3b2:3<707m3;f5?8?d?38846s|a1`94?5|50?m6>78;<;a0?b1343h;7<=a:pe5e=839p148?:2;4?8?e=3n=707l7;00f>{ti9n1<7=t=842>6?0343i:7j9;<;`3?44l2wxm=k50;1x9<052:3<707m7;f5?8?d?38?=6s|a1d94?5|50<86>78;<;a<?b1343h;7<;3:pe46=839p148;:2;4?8?e13n=707l7;072>{ti8;1<7=t=846>6?0343im7j9;<;`3?4302wxm<<50;1x9<012:3<707mb;f5?8?d?38?o6s|a0194?5|50<<6>78;<;ag?b1343h;7<;e:pe42=839p1487:2;4?8?el3n=707l7;065>{ti8?1<7=t=84:>6?0343ii7j9;<;`3?42;2wxm<850;1x9<0f2:3<707mf;f5?8?d?38?<6s|a0594?5|50<i6>78;<;`4?b1343h;7<:8:pe4>=839p148l:2;4?8?d93n=707l7;06e>{ti831<7=t=84g>6?0343h>7j9;<;`3?42l2wxm<o50;1x9<0b2:3<707l3;f5?8?d?38>j6s|a0`94?5|50<m6>78;<;`0?b1343h;7<93:pe4e=839p149?:2;4?8?d=3n=707l7;056>{ti8n1<7=t=852>6?0343h:7j9;<;`3?41n2wxm<k50;0x9<152:3<707l7;063>{ti8l1<7<t=850>6?0343h;7<83:pe76=838p149;:2;4?8?d?38<96s|a3394?4|50=>6>78;<;`3?4012wxm?<50;0x9<112:3<707l7;04f>{ti;91<7<t=854>6?0343h;7<8e:pe72=838p1497:2;4?8?d?383<6s|a3794?4|50=26>78;<;`3?4?<2wxm?850;0x9<1f2:3<707l7;0;2>{ti;=1<7<t=85a>6?0343h;7<79:pe7>=838p149l:2;4?8?d?383n6s|a3;94?4|50=o6>78;<;`3?4?:2wxm?o50;0x9<1b2:3<707l7;0;b>{ti;h1<7<t=85e>6?0343h;7<61:pe7e=838p146?:2;4?8?d?38286s|a3f94?4|502:6>78;<;`3?4>>2wxm?k50;0x9<>52:3<707l7;0:e>{ti;l1<7<t=8:0>6?0343h;7<6c:pe66=838p146;:2;4?8?d?382j6s|a2394?4|502>6>78;<;`3?4f92wxm><50;0x9<>12:3<707l7;0b1>{ti:91<7<t=8:4>6?0343h;7<n7:pe62=838p1467:2;4?8?d?38j?6s|a2794?4|50226>78;<;`3?4fi2wxm>850;0x9<>f2:3<707l7;0bg>{ti:=1<7<t=8:a>6?0343h;7<m0:pe6>=838p146l:2;4?8?d?38i>6s|a2;94?4|502o6>78;<;`3?4e=2wxm>o50;0x9<>b2:3<707l7;0a3>{ti:h1<7<t=8:e>6?0343h;7<mb:pe6e=838p147?:2;4?8?d?38ih6s|a2f94?4|503:6>78;<;`3?4d82wxm>k50;0x9<?52:3<707l7;0`6>{ti:l1<7<t=8;0>6?0343h;7<m9:pe16=838p147;:2;4?8?d?3;nm6s|a5394?4|503>6>78;<;`3?7bk2wxm9<50;0x9<?12:3<707l7;3fb>{ti=91<7<t=8;4>6?0343h;7?i1:pe12=838p1477:2;4?8?d?3;m96s|a5794?4|50326>78;<;`3?7a?2wxm9850;0x9<?f2:3<707l7;3ee>{ti==1<7<t=8;a>6?0343h;7?ic:pe1>=838p147l:2;4?8?d?38;<6s|a5;94?4|503o6>78;<;`3?47:2wxm9o50;0x9<?b2:3<707l7;3ea>{ti=h1<7<t=8;e>6?0343h;7<?5:pe1e=838p14o?:2;4?8?d?38;;6s|a5f94?4|50k:6>78;<;`3?47j2wxm9k50;0x9<g52:3<707l7;03`>{ti=l1<7<t=8c0>6?0343h;7<>0:pe06=838p14o;:2;4?8?d?38:>6s|a4394?4|50k>6>78;<;`3?46>2wxm8<50;0x9<g12:3<707l7;02<>{ti<91<7<t=8c4>6?0343h;7<>b:pe02=838p14o7:2;4?8?d?38:h6s|a4794?4|50k26>78;<;`3?46<2wxm8850;0x9<gf2:3<707l7;015>{ti<=1<7<t=8ca>6?0343h;7<=3:pe0>=838p14ol:2;4?8?d?389:6s|a4;94?4|50ko6>78;<;`3?4502wxm8o50;0x9<gb2:3<707l7;01g>{ti<h1<7<t=8ce>6?0343h;7<=e:pe0e=838p14l?:2;4?8?d?388=6s|a4f94?4|50h:6>78;<;`3?44;2wxm8k50;0x9<d52:3<707l7;003>{ti<l1<7<t=8`0>6?0343h;7<<9:pe36=838p14l;:2;4?8?d?38896s|a7394?4|50h>6>78;<;`3?44k2wxm;<50;0x9<d12:3<707l7;00a>{ti?91<7<t=8`4>6?0343h;7<;2:pe32=838p14l7:2;4?8?d?38?86s|a7794?4|50h26>78;<;`3?43?2wxm;850;0x9<df2:3<707l7;07=>{ti?=1<7<t=8`a>6?0343h;7<;d:pe3>=838p14ll:2;4?8?d?38?j6s|a7;94?4|50ho6>78;<;`3?42:2wxm;o50;0x9<db2:3<707l7;060>{ti?h1<7<t=8`e>6?0343h;7<;b:pe3e=838p14m?:2;4?8?d?38>56s|a7f94?4|50i:6>78;<;`3?42j2wxm;k50;0x9<e52:3<707l7;06a>{ti?l1<7<t=8a0>6?0343h;7<90:pe26=838p14m;:2;4?8?d?38=86s|a6394?4|50i>6>78;<;`3?41m2wxm:<50;0x9<e12:3<707l7;044>{ti>>1<7<t=8a4>6b4343;;7<la:pe23=83>p1l9<:2;4?8?7>3>:707?4;62?8?7=3>;7p}n7783>1}:0oi18=528g5905=:1891?494=827>14<uzk<;7>54z?;b1<c>273jk4<969>=50=<:165=:5429~wd1?290:8v374480=d=:0=>1?4o4=960>6?f342?>7=6a:?;04<41h1649>538c89=5a2:3j706<e;1:e>;?;m085l5282a97<g<513=6>7n;<::1?5>i2739:4nd:?;1<<fl273>94=c`9><53=;0=015>9:e489=0e2:3j7069c;1:e>;ei=09oo5rs`5:>5<6<r73j;4<969>2a4=<:16:io5429>2g4=<>16:o=5469>2g2=<>16:o;5469>2f2=<>16:n;5469>2f0=<>16:n95469>2d?=<>16:lo5469>2a3=<>16:i85469>2d4=<>16:l=5469>2ad=<>16:im5469>2a5=<>1vl9n:1808>5:38hn639a180=2=:jh81>nl4}rc4f?6=>r73?n4k6:?5b`<5kh16;:=5385892132;ij709n7;3f<>;0i00:i55rs`5`>5<1s428h7j9;<535?4di27<;:4<969>32>=:jk01:o8:374?81f138>;6s|a6f94?0|519n6i84=627>7ef34=<n7=67:?43f<5kh16;l95265892g>2;=<7p}n7d83>3}:0:l1h;5271596fg<5>=m6>78;<5;4?4di27<m:4=839>3d?=:180q~o8f;292~;?<90o:6380`81gd=:?191?494=6:7>7ef34=j;7<7d:?4e<<50m1vl6?:1858>393n=709?d;0`e>;00>085:5279:96fg<5>k<6?77;<5b=?4>02wxm5?50;4x9=252m<01:??:3ab?81?j392;6388b81gd=:?h=1>l=4=6c:>7g43tyj4?4?:7y><15=l?16;<=52bc892>a2:3<70960;0`e>;0i>09mh527`;96dc<uzk3?7>56z?;01<c>27<=;4=c`9>3<5=;0=01:7;:3ab?81f?38i5638a881f<=z{h2?6=49{<:71?b134=:57<la:?4=3<41>16;4952bc892g02;i>709n9;0`1>{ti1?1<7?9{<::1?b134<ji7=67:?4`0<5kk16:i<5419>2ag=<916:o<5459>2g5=<=16:o:5459>2g3=<=16:n:5459>2f3=<=16:n85459>2f1=<=16:l75459>2dg=<=16:i;5459>2a0=<=16:l<5459>2d5=<=16:il5459>2ae=<=16:i=5459~wd>1290::v37978g2>;1k9085:527e796fe<5?n969?4=7fb>17<5?h969;4=7`0>13<5?h?69;4=7`6>13<5?i?69;4=7a6>13<5?i=69;4=7a4>13<5?k269;4=7cb>13<5?n>69;4=7f5>13<5?k969;4=7c0>13<5?ni69;4=7f`>13<5?n869;4}rc;3?6=:r7?:o4<969>1d7=9;h0q~o78;296~;3>m085:525`39565<uzk357>52z?72c<41>169l?51268yvg?i3:1>v3;7080=2=:=h;1=>;4}rc;f?6=:r7?;>4<969>1d7=9:<0q~o7c;296~;3?>085:525`39561<uzk3h7>52z?73<<41>169l?512:8yvg?m3:1>v3;7c80=2=:=h;1=>74}rc;b?6=:r7?;i4<969>1d7=9=30q~o60;296~;3ko085:525`3956g<uzk2=7>52z?7`4<41>169l?512`8yvg>:3:1>v3;d280=2=:=h;1=?m4}rc:7?6=:r7?h84<969>1d7=9;n0q~o64;296~;3l>085:525`3957c<uzk297>52z?5=f<5kk16:8753838yvg>>3:14v36c680e==:0<<1h;5289a96fb<5>l86>78;<5e0?b1342987<lb:?;`f<41h1648;538c8yvg>?3:1?v3n7280=3=:?o>1?494=6d6>a0<uzk247>55z?:56<41h165=85419>=42=;h201:h::2;4?81a>3n=7p}n9883>0}:0o<1?4o4=9d;>6?f342mh7=6a:?4b3<41>16;k95d79~wd?f290?w06if;1:e>;?nh085l527g597<1<5>l36i84}rc:f?6=;r73j94<9`9>3c>=;0=01:h6:e48yvg>k3:1>:u27g;97<1<5>lj6i84=7;f>6?f34=o:7=6a:?5e`<41h16:n>538c893`a2:3j708id;1:e>;08;085l5271297<g<5>:>6>7n;<537?5>i27<<54<9`9>350=;0k01:>m:2;b?8171392m6380d80=d=:?9i1?4o4=632>6?f34=;j7=6a:?451<41h16;<<538c892702:3j709>5;1:e>;09h085l5270:97<g<5>3=6>7n;<5:7?5>i27<4k4<9`9>3=d=;0k01:68:2;b?81?;392m6387g80=d=:?>h1?4o4=654>6?f34=<?7=6a:?4e0<4i116;l953`:892g>2:k37p}n9e83>6}:?ok1?494=7;e>6?f34=o;7=6a:pe<c=838p1;7l:3ab?8>cj392;6s|a8d94?72s42m87=67:?4`0<5kh16:i<5439>2ag=<;16:o<5479>2g5=<?16:o:5479>2g3=<?16:n:5479>2f3=<?16:n85479>2f1=<?16:l75479>2dg=<?16:i;5479>2a0=<?16:l<5479>2d5=<?16:il5479>2ae=<?16:i=5479~wd`22908w0on0;1:3>;3;;0o:6361e8g2>{tio<1<7=t=`c2>6?034>887j9;<;2a?b13tyjj:4?:2y>ed4=;0=019=9:e489<7a2m<0q~oi8;297~;fi:085:5242:9`3=:1;:1h;5rs`d:>5<4s4kj87=67:?77d<c>272><4k6:pecg=839p1lo::2;4?824k3n=707=2;f5?xufnk0;6>u2a`497<1<5=9n6i84=800>a0<uzkmo7>53z?be2<41>1689>5d79>=72=l?1vlhk:1808gf0392;63;438g2>;>:<0o:6s|agg94?5|5hk26>78;<670?b13439:7j9;|qbbc<72:q6mlo5385891212m<014<8:e48yvd783:1?v3nac80=2=:<=21h;5293:9`3=z{k::6=4<{<cbg?5>?27?8l4k6:?:6<<c>2wxn=<50;1x9dgc2:3<70:;c;f5?8?5i3n=7p}m0283>6}:iho1?494=56f>a0<508i6i84}r`30?6=;r7jmk4<969>006=l?165?m5d79~wg622908w0om0;1:3>;3=;0o:6362e8g2>{tj9<1<7=t=``2>6?034>>87j9;<;1a?b13tyi<:4?:2y>eg4=;0=019;9:e489<4a2m<0q~l?8;297~;fj:085:5244:9`3=:1::1h;5rsc2:>5<4s4ki87=67:?71d<c>272?<4k6:pf5g=839p1ll::2;4?822k3n=707<2;f5?xue8k0;6>u2ac497<1<5=?n6i84=810>a0<uzh;o7>53z?bf2<41>168;>5d79>=62=l?1vo>k:1808ge0392;63;638g2>;>;<0o:6s|b1g94?5|5hh26>78;<650?b13438:7j9;|qa4c<72:q6moo5385891012m<014=8:e48yvd683:1?v3nbc80=2=:<?21h;5292:9`3=z{k;:6=4<{<cag?5>?27?:l4k6:?:7<<c>2wxn<<50;1x9ddc2:3<70:9c;f5?8?4i3n=7p}m1283>6}:iko1?494=54f>a0<509i6i84}r`20?6=;r7jnk4<969>026=l?165>m5d79~wg722908w0ol0;1:3>;3?;0o:6363e8g2>{tj8<1<7=t=`a2>6?034><87j9;<;0a?b13tyi=:4?:2y>ef4=;0=01999:e489<5a2m<0q~l>8;297~;fk:085:5246:9`3=:1=:1h;5rsc3:>5<4s4kh87=67:?73d<c>2728<4k6:pf4g=839p1lm::2;4?820k3n=707;2;f5?xue9k0;6>u2ab497<1<5==n6i84=860>a0<uzh:o7>53z?bg2<41>1685>5d79>=12=l?1vo?k:1808gd0392;63;838g2>;><<0o:6s|b0g94?5|5hi26>78;<6;0?b1343?:7j9;|qa5c<72:q6mno5385891>12m<014:8:e48yvd583:1?v3ncc80=2=:<121h;5295:9`3=z{k8:6=4<{<c`g?5>?27?4l4k6:?:0<<c>2wxn?<50;1x9dec2:3<70:7c;f5?8?3i3n=7p}m2283>6}:ijo1?494=5:f>a0<50>i6i84}r`10?6=;r7jok4<969>0<6=l?1659m5d79~wg422908w0ok0;1:3>;31;0o:6364e8g2>{tj;<1<7=t=`f2>6?034>287j9;<;7a?b13tyi>:4?:2y>ea4=;0=01979:e489<2a2m<0q~l=8;297~;fl:085:5248:9`3=:1<:1h;5rsc0:>5<4s4ko87=67:?7=d<c>2729<4k6:pf7g=839p1lj::2;4?82>k3n=707:2;f5?xue:k0;6>u2ae497<1<5=3n6i84=870>a0<uzh9o7>53z?b`2<41>168l>5d79>=02=l?1vo<k:1808gc0392;63;a38g2>;>=<0o:6s|b3g94?5|5hn26>78;<6b0?b1343>:7j9;|qa6c<72:q6mio5385891g12m<014;8:e48yvd483:1?v3ndc80=2=:<h21h;5294:9`3=z{k9:6=4<{<cgg?5>?27?ml4k6:?:1<<c>2wxn><50;1x9dbc2:3<70:nc;f5?8?2i3n=7p}m3283>6}:imo1?494=5cf>a0<50?i6i84}r`00?6=;r7jhk4<969>0g6=l?1658m5d79~wg522908w0oj0;1:3>;3j;0o:6365e8g2>{tj:<1<7=t=`g2>6?034>i87j9;<;6a?b13tyi?:4?:2y>e`4=;0=019l9:e489<3a2m<0q~l<8;297~;fm:085:524c:9`3=:1?:1h;5rsc1:>5<4s4kn87=67:?7fd<c>272:<4k6:pf6g=839p1lk::2;4?82ek3n=70792;f5?xue;k0;6>u2ad497<1<5=hn6i84=840>a0<uzh8o7>53z?ba2<41>168n>5d79>=32=l?1vo=k:1808gb0392;63;c38g2>;>><0o:6s|b2g94?5|5ho26>78;<6`0?b1343=:7j9;|qa7c<72:q6mho5385891e12m<01488:e48yvd383:1?v3nec80=2=:<j21h;5297:9`3=z{k>:6=4<{<cfg?5>?27?ol4k6:?:2<<c>2wxn9<50;1x9dcc2:3<70:lc;f5?8?1i3n=7p}m4283>6}:ilo1?494=5af>a0<50<i6i84}r`70?6=;r7jik4<969>0a6=l?165;m5d79~wg222908w0oi0;1:3>;3l;0o:6366e8g2>{tj=<1<7=t=`d2>6?034>o87j9;<;5a?b13tyi8:4?:2y>ec4=;0=019j9:e489<0a2m<0q~l;8;297~;fn:085:524e:9`3=:1>:1h;5rsc6:>5<4s4km87=67:?7`d<c>272;<4k6:pfd7=838j?v376c8g2>;e?o085?52a619e1=:0oi18<528ga907=:0oi18>528g5904=:0o=18?528g5906=:<:818=52420904=:<:818?5245:905=:<=218<5245:907=:<<o18=5244g904=:<<o18?52466905=:<>>18<52466907=:<1k18=5249c904=:<1k18?524`2905=:<h:18<524`2907=:<k<18=524c4904=:<k<18?524ba905=:<ji18<524ba907=:<m218=524e:904=:<m218?524ec905=:<mk18<524ec907=:<:>18=52426904=:<:>18?52424905=:<:<18<52424907=:<:218=5242:904=:<:218?5242c905=:<:k18<5242c907=:<:i18=5242a904=:<:i18?5242g905=:<:o18<5242g907=:<=:18=52452904=:<=:18?52450905=:<=818<52450907=:<=>18=52456904=:<=>18?52454905=:<=<18<52454907=:<=k18=5245c904=:<=k18?5245a905=:<=i18<5245a907=:<=o18=5245g904=:<=o18?52442905=:<<:18<52442907=:<<818=52440904=:<<818?52446905=:<<>18<52446907=:<<<18=52444904=:<<<18?5244:905=:<<218<5244:907=:<<k18=5244c904=:<<k18?5244a905=:<<i18<5244a907=:<?:18=52472904=:<?:18?52470905=:<?818<52470907=:<?>18=52476904=:<?>18?52474905=:<?<18<52474907=:<?218=5247:904=:<?218?5247c905=:<?k18<5247c907=:<?i18=5247a904=:<?i18?5247g905=:<?o18<5247g907=:<>:18=52462904=:<>:18?52460905=:<>818<52460907=:<><18=52464904=:<><18?5246:905=:<>218<5246:907=:<>k18=5246c904=:<>k18?5246a905=:<>i18<5246a907=:<>o18=5246g904=:<>o18?52492905=:<1:18<52492907=:<1818=52490904=:<1818?52496905=:<1>18<52496907=:<1<18=52494904=:<1<18?5249:905=:<1218<5249:907=:<1i18=5249a904=:<1i18?5249g905=:<1o18<5249g907=:<0:18=52482904=:<0:18?52480905=:<0818<52480907=:<0>18=52486904=:<0>18?52484905=:<0<18<52484907=:<0218=5248:904=:<0218?5248c905=:<0k18<5248c907=:<0i18=5248a904=:<0i18?5248g905=:<0o18<5248g907=:<h818=524`0904=:<h818?524`6905=:<h>18<524`6907=:<h<18=524`4904=:<h<18?524`:905=:<h218<524`:907=:<hk18=524`c904=:<hk18?524`a905=:<hi18<524`a907=:<ho18=524`g904=:<ho18?524c2905=:<k:18<524c2907=:<k818=524c0904=:<k818?524c6905=:<k>18<524c6907=:<k218=524c:904=:<k218?524cc905=:<kk18<524cc907=:<ki18=524ca904=:<ki18?524cg905=:<ko18<524cg907=:<j:18=524b2904=:<j:18?524b0905=:<j818<524b0907=:<j>18=524b6904=:<j>18?524b4905=:<j<18<524b4907=:<j218=524b:904=:<j218?524bc905=:<jk18<524bc907=:<jo18=524bg904=:<jo18?524e2905=:<m:18<524e2907=:<m818=524e0904=:<m818?524e6905=:<m>18<524e6907=:<m<18=524e4904=:<m<18?5297d9e1=:1?o1m95297f9e1=:1?i1m95297`9e1=:1?31m95297:9e1=:1?=1m9529749e1=:1??1m9529769e1=:1?91m9529709e1=:1?;1m9529729e1=:1<o1m95294f9e1=:1<i1m95294`9e1=:1<k1m95294;9e1=:1<21m9529459e1=:1<<1m9529479e1=:1<91m9529409e1=:1<;1m9529429e1=:1=l1m95295g9e1=:1=n1m95295a9e1=:1=h1m95295c9e1=:1=21m9529559e1=:1=<1m9529579e1=:1=>1m9529519e1=:1=81m9529539e1=:1=:1m95292d9e1=:1:n1m95292a9e1=:1:h1m95292c9e1=:1:31m95292:9e1=:1:=1m9529249e1=:1:?1m9529269e1=:1:81m9529239e1=:1::1m95293d9e1=:1;o1m95293f9e1=:1;i1m95293`9e1=:1;k1m95293;9e1=:1;=1m9529349e1=:1;?1m9529369e1=:1;91m9529309e1=:1;;1m9529329e1=:18l1m95290g9e1=:1>;1m9529629e1=:1?k1m95294d9e1=:1<>1m95295;9e1=:1:o1m9529219e1=:1;21m95290f9e1=:1j>1m9529b19e1=:1j81m9529b39e1=:1j:1m9529cg9e1=:1kn1m9529ca9e1=:1kh1m9529cc9e1=:1k31m9529c:9e1=:1k=1m9529c49e1=:1k?1m9529c19e1=:1k81m9529c39e1=:1k:1m9529`d9e1=:1ho1m9529`f9e1=:1hi1m9529``9e1=:1hk1m9529`:9e1=:1h=1m9529`49e1=:1h?1m9529`69e1=:1h91m9529`09e1=:1h;1m9529`29e1=:10l1m95298f9e1=:10i1m95298`9e1=:10k1m95298;9e1=:1021m9529859e1=:10<1m9529879e1=:10>1m9529809e1=:10;1m9529829e1=:11l1m95299g9e1=:11n1m95299a9e1=:11h1m95299c9e1=:1131m9529959e1=:11<1m9529979e1=:11>1m9529919e1=:1181m9529939e1=:11:1m95296d9e1=:1>o1m95296a9e1=:1>h1m95296c9e1=:1>31m95296:9e1=:1>=1m9529649e1=:1>?1m9529669e1=:1>91m9529b49e1=:1j?1m9529cd9e1=:1k>1m9529`;9e1=:10o1m9529819e1=:1121m95296f9e1=:1>81m9529b5963b<50i<6?8m;<;`3?41i272o:4=689>=f1=:?2014m8:344?8?d?38=:636c68120=:1j=1>;?4=8a4>73d343h;7<:5:?:g2<5=9165n9525c89<e02;>>707l7;00b>;>k>09?l529b59662<50i<6?<i;<;`3?451272o:4=259>=f1=:8o014m8:33:?8?d?38:?636c6814`=:1j=1>=64=8a4>764343h;7?id:?:g2<6n1165n951g089<e028oo707l7;0`7>;>k>09nh529b596g><50i<6?l<;<;`3?4fl272o:4=a99>=f1=:h8014m8:3;g?8?d?382;636c681=7=:1j=1>5m4=8a4>7>0343h;7<71:?:g2<5?j165n9526489<e02;=:707l7;062>;>k>09=k529b596f3<50i<6?6k;<;31?25343;97:<;<;3g?g1342=47o;;<:5=?g3342>:7o;;<::6?g33422>7j9;<:63?g3342>57j9;<:6<?g3342on7o;;<:6`?g3342>i7o;;<:6b?g33423i7o;;<:;b?g3342hi7o;;<:`f?g3342h;7o;;<:`7?g3342ij7o;;<:af?g3342i;7o;;<:a7?g3342jj7o;;<:bf?g3342jm7o9;<:b`?g13429?7<lc:?;51<f<273=84n4:?;53<f<273=:4n4:?;44<f<273<?4n4:?;46<f<273<94n4:?;40<f<273<;4n4:?5bf<3827=jn4;1:?5bf<3:27=jn4;3:?437<f>27<;84n6:?46`<f>27<?<4n6:?6f7<5kk169no5a79>1fb=i?1699j5a79>106=i?169:j5a79>1=6=i?169l?5649>1d7=>=169l?55d9>1d7=0j169l?58c9>1d7=0h169l?5859>1d7=99:018o>:gg890g62on018o>:ga890g62oh018o>:gc890g628:270;n1;33<>;2i80:<:525`39550<5<k:6<>:;<7b5?77<27>m<4>029>1d7=998018o>:022?83f93l270;n1;377>;2i80:8<525`395fb<5<k:6>o;;<7b5?5f=27>m?4k8:?6e7<4i:169l<59b9>1d4=9ji018o=:8`890g520o018o=:8f890g52:k>70;n2;374>;2i;0:?h525`0956b<5<k96<=l;<7b6?3334?j>7;8;<7b6?3134?j>7;:;<7b6?2c34?j>798;<7b6?1e34?j>79n;<7b6?1>34?j>797;<7b6?1734?j>7h>;<7b6?ca34?j>7kk;<7b6?cd34?j>7km;<7b6?cf34?j>7k6;<7b6?c?34?j>7k8;<7b6?c134?j>7k:;<7b6?c334?j>7k=;<7b6?c634?j>7k?;<7b6?ba34?j>7jj;<7b6?bc34?j>7jl;<7b6?be34?j>7jn;<7b6?b>34?j>7h7;<7b6?`034?j>7h9;<7b6?`234?j>7h;;<7b6?`434?j>7h=;<7b6?cb34?j>7k<;<7b7?b?34?j?7=n3:?6e6<>k27>m>4>cb9>1d5=1k169l=59d9>1d5=1m169l=53`7890g428>;70;n3;30a>;2i:0:?i525`1956e<5<k868:4=4c0>01<5<k86884=4c0>03<5<k869j4=4c0>21<5<k86:l4=4c0>2g<5<k86:74=4c0>2><5<k86:>4=4c0>c7<5<k86hh4=4c0>`b<5<k86hm4=4c0>`d<5<k86ho4=4c0>`?<5<k86h64=4c0>`1<5<k86h84=4c0>`3<5<k86h:4=4c0>`4<5<k86h?4=4c0>`6<5<k86ih4=4c0>ac<5<k86ij4=4c0>ae<5<k86il4=4c0>ag<5<k86i74=4c0>c><5<k86k94=4c0>c0<5<k86k;4=4c0>c2<5<k86k=4=4c0>c4<5<k86hk4=4c0>`5<uzhj>7>52z?ae7<418164;m5d79~wgg42909w0ln3;1:5>;?lj0o:6s|b`694?4|5kk?6>7>;<:61?b13twe>=;9:184Md3i2P8h44>{0a1>x\6m=0:w>j6:|m6530290:9vFm4`9~j76203:1=vFm4`9~j76213:1=vFm4`9~j762i3:1=vFm4`9~j762j3:1=vFm4`9~j762k3:1=vFm4`9~j762l3:1=vFm4`9~j762m3:1=vFm4`9~j762n3:1=vFm4`9~j76183:1=vFm4`9~j76193:1=vFm4`9~j761:3:1?vFm4`9~j761;3:1jvFm4`9~j761<3:1=vFm4`9~j761=3:1=vFm4`9~j761>3:1=vFm4`9~j761?3:1=vFm4`9~j76103:1=vFm4`9~j76113:1=vFm4`9~j761i3:1=vFm4`9~j761j3:1=vFm4`9~j761k3:1=vFm4`9~j761l3:1=vFm4`9~j761m3:1=vFm4`9~j761n3:1=vFm4`9~j76083:1=vFm4`9~j76093:1=vFm4`9~j760:3:1=vFm4`9~j760;3:1=vFm4`9~j760<3:1=vFm4`9~j760=3:1=vFm4`9~j760>3:1=vFm4`9~j760?3:1=vFm4`9~j76003:1=vFm4`9~j76013:1=vFm4`9~j760i3:1;vFm4`9~j760j3:1=vFm4`9~j760k3:1=vFm4`9~j760l3:1=vFm4`9~j760m3:1=vFm4`9~j760n3:1=vFm4`9~j76?83:1=vFm4`9~j76?93:1=vFm4`9~j76?:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=09194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:387>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14=3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>76;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh581=1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32;<?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<5750;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76?i3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=09`94?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:3o7>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14=b=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>7e;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh581l1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32:4?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<4?50;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76>:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=08194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:287>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14<3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>66;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh580=1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32:<?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<4750;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76>i3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=08`94?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:2o7>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14<b=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>6e;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh580l1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32b4?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<l?50;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76f:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0`194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:j87>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14d3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>n6;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58h=1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32b<?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<l750;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76fi3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0``94?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:jo7>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14db=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>ne;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58hl1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32a4?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<o?50;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76e:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0c194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:i87>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14g3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>m6;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58k=1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32a<?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<o750;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76ei3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0c`94?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:io7>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14gb=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>me;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58kl1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32`4?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<n?50;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76d:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0b194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:h87>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14f3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>l6;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58j=1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32`<?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<n750;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76di3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0b`94?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:ho7>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14fb=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>le;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58jl1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32g4?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<i?50;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76c:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0e194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:o87>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14a3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>k6;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58m=1<7?tHc6b?xh58m21<7?tHc6b?xh58m31<7?tHc6b?xh58mk1<7?tHc6b?xh58mh1<7?tHc6b?xh58mi1<7?tHc6b?xh58mn1<7?tHc6b?xh58mo1<7?tHc6b?xh58ml1<7?tHc6b?xh58l:1<7?tHc6b?xh58l;1<7?tHc6b?xh58l81<7?tHc6b?xh58l91<7?tHc6b?xh58l>1<7?tHc6b?xh58l?1<7?tHc6b?xh58l<1<7?tHc6b?xh58l=1<7?tHc6b?xh58l21<7?tHc6b?xh58l31<7?tHc6b?xh58lk1<7?tHc6b?xh58lh1<7?tHc6b?xh58li1<7?tHc6b?xh58ln1<7?tHc6b?xh58lo1<7?tHc6b?xh58ll1<7?tHc6b?xh58o:1<7?tHc6b?xh58o;1<7?tHc6b?xh58o81<7?tHc6b?xh58o91<7?tHc6b?xh58o>1<7?tHc6b?xh58o?1<7?tHc6b?xh58o<1<7?tHc6b?xh58o=1<7?tHc6b?xh58o21<7?tHc6b?xh58o31<7?tHc6b?xh58ok1<7?tHc6b?xh58oh1<7?tHc6b?xh58oi1<7?tHc6b?xh58on1<7?tHc6b?xh58oo1<7?tHc6b?xh58ol1<7?tHc6b?xh599:1<7?tHc6b?xh599;1<7?tHc6b?xh59981<7?tHc6b?xh59991<7?tHc6b?xh599>1<7?tHc6b?xh599?1<7?tHc6b?xh599<1<7?tHc6b?xh599=1<7?tHc6b?xh59921<7?tHc6b?xh59931<7?tHc6b?xh599k1<7?tHc6b?xh599h1<7?tHc6b?xh599i1<7?tHc6b?xh599n1<7?tHc6b?xh599o1<7?tHc6b?xh599l1<7?tHc6b?xh598:1<7?tHc6b?xh598;1<7?tHc6b?xh59881<7?tHc6b?xh59891<7?tHc6b?xh598>1<7?tHc6b?xh598?1<7?tHc6b?xh598<1<7?tHc6b?xh598=1<7?tHc6b?xh59821<7?tHc6b?xh59831<7?tHc6b?xh598k1<7?tHc6b?xh598h1<7?tHc6b?xh598i1<7?tHc6b?xh598n1<7?tHc6b?xh598o1<7?tHc6b?xh598l1<7?tHc6b?xh59;:1<7?tHc6b?xh59;;1<7?tHc6b?xh59;81<7?tHc6b?xh59;91<7?tHc6b?xh59;>1<7?tHc6b?xh59;?1<7?tHc6b?xh59;<1<7?tHc6b?xh59;=1<7?tHc6b?xh59;21<7?tHc6b?xh59;31<7?tHc6b?xh59;k1<7?tHc6b?xh59;h1<7?tHc6b?xh59;i1<7?tHc6b?xh59;n1<7?tHc6b?xh59;o1<7?tHc6b?xh59;l1<7?tHc6b?xh59::1<7?tHc6b?xh59:;1<7?tHc6b?xh59:81<7?tHc6b?xh59:91<7?tHc6b?xh59:>1<7?tHc6b?xh59:?1<7?tHc6b?xh59:<1<7?tHc6b?xh59:=1<7?tHc6b?xh59:21<7?tHc6b?xh59:31<7?tHc6b?xh59:k1<7?tHc6b?xh59:h1<7?tHc6b?xh59:i1<7?tHc6b?xh59:n1<7?tHc6b?xh59:o1<7?tHc6b?xh59:l1<7?tHc6b?xh59=:1<7?tHc6b?xh59=;1<7?tHc6b?xh59=81<7?tHc6b?xh59=91<7?tHc6b?xh59=>1<7?tHc6b?xh59=?1<7?tHc6b?xh59=<1<7?tHc6b?xh59==1<7?tHc6b?xh59=21<7?tHc6b?xh59=31<7?tHc6b?xh59=k1<7?tHc6b?xh59=h1<7?tHc6b?xh59=i1<7?tHc6b?xh59=n1<7?tHc6b?xh59=o1<7?tHc6b?xh59=l1<7?tHc6b?xh59<:1<7?tHc6b?xh59<;1<7?tHc6b?xh59<81<7?tHc6b?xh59<91<7?tHc6b?xh59<>1<7?tHc6b?xh59<?1<7?tHc6b?xh59<<1<7?tHc6b?xh59<=1<7?tHc6b?xh59<21<7?tHc6b?xh59<31<7?tHc6b?xh59<k1<7?tHc6b?xh59<h1<7?tHc6b?xh59<i1<7?tHc6b?xh59<n1<7?tHc6b?xh59<o1<7?tHc6b?xh59<l1<7?tHc6b?xh59?:1<7?tHc6b?xh59?;1<7?tHc6b?xh59?81<7?tHc6b?xh59?91<7?tHc6b?xh59?>1<7?tHc6b?xh59??1<7?tHc6b?xh59?<1<7?tHc6b?xh59?=1<7?tHc6b?xh59?21<7?tHc6b?xh59?31<7?tHc6b?xh59?k1<7?tHc6b?xh59?h1<7?tHc6b?xh59?i1<7?tHc6b?xh59?n1<7?tHc6b?xh59?o1<7?tHc6b?xh59?l1<7?tHc6b?xh59>:1<7?tHc6b?xh59>;1<7?tHc6b?xh59>81<7?tHc6b?xh59>91<7?tHc6b?xh59>>1<7?tHc6b?xh59>?1<7?tHc6b?xh59><1<7?tHc6b?xh59>=1<7?tHc6b?xh59>21<7?tHc6b?xh59>31<7?tHc6b?xh59>k1<7?tHc6b?xh59>h1<7?tHc6b?xh59>i1<7?tHc6b?xh59>n1<7?tHc6b?xh59>o1<7?tHc6b?xh59>l1<7?tHc6b?xh591:1<7?tHc6b?xh591;1<7?tHc6b?xh59181<7?tHc6b?xh59191<7?tHc6b?xh591>1<7?tHc6b?xh591?1<7?tHc6b?xh591<1<7?tHc6b?xh591=1<7?tHc6b?xh59121<7?tHc6b?xh59131<7?tHc6b?xh591k1<7?tHc6b?xh591h1<7?tHc6b?xh591i1<7?tHc6b?xh591n1<7?tHc6b?xh591o1<7?tHc6b?xh591l1<7?tHc6b?xh590:1<7?tHc6b?xh590;1<7?tHc6b?xh59081<7?tHc6b?xh59091<7?tHc6b?xh590>1<7?tHc6b?xh590?1<7?tHc6b?xh590<1<7?tHc6b?xh590=1<7?tHc6b?xh59021<7?tHc6b?xh59031<7?tHc6b?xh590k1<7?tHc6b?xh590h1<7?tHc6b?xh590i1<7?tHc6b?xh590n1<7?tHc6b?xh590o1<7?tHc6b?xh590l1<7?tHc6b?xh59h:1<7?tHc6b?xh59h;1<7?tHc6b?xh59h81<7?tHc6b?xh59h91<7?tHc6b?xh59h>1<7?tHc6b?xh59h?1<7?tHc6b?xh59h<1<7?tHc6b?xh59h=1<7?tHc6b?xh59h21<7?tHc6b?xh59h31<7?tHc6b?xh59hk1<7?tHc6b?xh59hh1<7?tHc6b?xh59hi1<7?tHc6b?xh59hn1<7?tHc6b?xh59ho1<7?tHc6b?xh59hl1<7?tHc6b?xh59k:1<7?tHc6b?xh59k;1<7?tHc6b?xh59k81<7?tHc6b?xh59k91<7?tHc6b?xh59k>1<7?tHc6b?xh59k?1<7?tHc6b?xh59k<1<7?tHc6b?xh59k=1<7?tHc6b?xh59k21<7?tHc6b?xh59k31<7?tHc6b?xh59kk1<7?tHc6b?xh59kh1<7?tHc6b?xh59ki1<7?tHc6b?xh59kn1<7?tHc6b?xh59ko1<7?tHc6b?xh59kl1<7?tHc6b?xh59j:1<7?tHc6b?xh59j;1<7?tHc6b?xh59j81<7?tHc6b?xh59j91<7?tHc6b?xh59j>1<7?tHc6b?xh59j?1<7?tHc6b?xh59j<1<7?tHc6b?xh59j=1<7?tHc6b?xh59j21<7?tHc6b?xh59j31<7?tHc6b?xh59jk1<7?tHc6b?xh59jh1<7?tHc6b?xh59ji1<7?tHc6b?xh59jn1<7?tHc6b?xh59jo1<7?tHc6b?xh59jl1<7?tHc6b?xh59m:1<7?tHc6b?xh59m;1<7?tHc6b?xh59m81<7?tHc6b?xh59m91<7?tHc6b?xh59m>1<7?tHc6b?xh59m?1<7?tHc6b?xh59m<1<7?tHc6b?xh59m=1<7?tHc6b?xh59m21<7?tHc6b?xh59m31<7?tHc6b?xh59mk1<7?tHc6b?xh59mh1<7?tHc6b?xh59mi1<7?tHc6b?xh59mn1<7?tHc6b?xh59mo1<7?tHc6b?xh59ml1<7?tHc6b?xh59l:1<7?tHc6b?xh59l;1<7?tHc6b?xh59l81<7?tHc6b?xh59l91<7?tHc6b?xh59l>1<7?tHc6b?xh59l?1<7?tHc6b?xh59l<1<7?tHc6b?xh59l=1<7?tHc6b?xh59l21<7?tHc6b?xh59l31<7?tHc6b?xh59lk1<7?tHc6b?xh59lh1<7?tHc6b?xh59li1<7?tHc6b?xh59ln1<7?tHc6b?xh59lo1<7?tHc6b?xh59ll1<7?tHc6b?xh59o:1<7?tHc6b?xh59o;1<7?tHc6b?xh59o81<7?tHc6b?xh59o91<7?tHc6b?xh59o>1<7?tHc6b?xh59o?1<7?tHc6b?xh59o<1<7?tHc6b?xh59o=1<7?tHc6b?xh59o21<7?tHc6b?xh59o31<7?tHc6b?xh59ok1<7?tHc6b?xh59oh1<7?tHc6b?xh59oi1<7?tHc6b?xh59on1<7?tHc6b?xh59oo1<7?tHc6b?xh59ol1<7?tHc6b?xh5:9:1<7?tHc6b?xh5:9;1<7?tHc6b?xh5:981<7?tHc6b?xh5:991<7?tHc6b?xh5:9>1<7?tHc6b?xh5:9?1<7?tHc6b?xh5:9<1<7?tHc6b?xh5:9=1<7?tHc6b?xh5:921<7?tHc6b?xh5:931<7?tHc6b?xh5:9k1<7?tHc6b?xh5:9h1<7?tHc6b?xh5:9i1<7?tHc6b?xh5:9n1<7?tHc6b?xh5:9o1<7?tHc6b?xh5:9l1<7?tHc6b?xh5:8:1<7?tHc6b?xh5:8;1<7?tHc6b?xh5:881<7?tHc6b?xh5:891<7?tHc6b?xh5:8>1<7?tHc6b?xh5:8?1<7?tHc6b?xh5:8<1<7?tHc6b?xh5:8=1<7?tHc6b?xh5:821<7?tHc6b?xh5:831<7?tHc6b?xh5:8k1<7?tHc6b?xh5:8h1<7?tHc6b?xh5:8i1<7?tHc6b?xh5:8n1<7?tHc6b?xh5:8o1<7?tHc6b?xh5:8l1<7?tHc6b?xh5:;:1<7?tHc6b?xh5:;;1<7?tHc6b?xh5:;81<7?tHc6b?xh5:;91<7?tHc6b?xh5:;>1<7?tHc6b?xh5:;?1<7?tHc6b?xh5:;<1<7?tHc6b?xh5:;=1<7?tHc6b?xh5:;21<7?tHc6b?xh5:;31<7?tHc6b?xh5:;k1<7?tHc6b?xh5:;h1<7?tHc6b?xh5:;i1<7?tHc6b?xh5:;n1<7?tHc6b?xh5:;o1<7?tHc6b?xh5:;l1<7?tHc6b?xh5:::1<7?tHc6b?xh5::;1<7?tHc6b?xh5::81<7?tHc6b?xh5::91<7?tHc6b?xh5::>1<7?tHc6b?xh5::?1<7?tHc6b?xh5::<1<7?tHc6b?xh5::=1<7?tHc6b?xh5::21<7?tHc6b?xh5::31<7?tHc6b?xh5::k1<7?tHc6b?xh5::h1<7?tHc6b?xh5::i1<7?tHc6b?xh5::n1<7?tHc6b?xh5::o1<7?tHc6b?xh5::l1<7?tHc6b?xh5:=:1<7?tHc6b?xh5:=;1<7?tHc6b?xh5:=81<7?tHc6b?xh5:=91<7?tHc6b?xh5:=>1<7?tHc6b?xh5:=?1<7?tHc6b?xh5:=<1<7?tHc6b?xh5:==1<7?tHc6b?xh5:=21<7=tHc6b?xh5:=31<7?tHc6b?xh5:=k1<7?tHc6b?xh5:=h1<7?tHc6b?xh5:=i1<7?tHc6b?xh5:=n1<7?tHc6b?xh5:=o1<7?tHc6b?xh5:=l1<7?tHc6b?xh5:<:1<7?tHc6b?xh5:<;1<7?tHc6b?xh5:<81<7?tHc6b?xh5:<91<7?tHc6b?xh5:<>1<7?tHc6b?xh5:<?1<7?tHc6b?xh5:<<1<7?tHc6b?xh5:<=1<7?tHc6b?xh5:<21<7?tHc6b?xh5:<31<7?tHc6b?xh5:<k1<7?tHc6b?xh5:<h1<7?tHc6b?xh5:<i1<7?tHc6b?xh5:<n1<7?tHc6b?xh5:<o1<7?tHc6b?xh5:<l1<7?tHc6b?xh5:?:1<7?tHc6b?xh5:?;1<7?tHc6b?xh5:?81<7?tHc6b?xh5:?91<7?tHc6b?xh5:?>1<7?tHc6b?xh5:??1<7?tHc6b?xh5:?<1<7?tHc6b?xh5:?=1<7?tHc6b?xh5:?21<7?tHc6b?xh5:?31<7?tHc6b?xh5:?k1<7?tHc6b?xh5:?h1<7?tHc6b?xh5:?i1<7?tHc6b?xh5:?n1<7?tHc6b?xh5:?o1<7?tHc6b?xh5:?l1<7?tHc6b?xh5:>:1<7?tHc6b?xh5:>;1<7?tHc6b?xh5:>81<7?tHc6b?xh5:>91<7?tHc6b?xh5:>>1<7?tHc6b?xh5:>?1<7?tHc6b?xh5:><1<7?tHc6b?xh5:>=1<7?tHc6b?xh5:>21<7?tHc6b?xh5:>31<7?tHc6b?xh5:>k1<7?tHc6b?xh5:>h1<7?tHc6b?xh5:>i1<7?tHc6b?xh5:>n1<7?tHc6b?xh5:>o1<7?tHc6b?xh5:>l1<7?tHc6b?xh5:1:1<7?tHc6b?xh5:1;1<7?tHc6b?xh5:181<7?tHc6b?xh5:191<7?tHc6b?xh5:1>1<7?tHc6b?xh5:1?1<7?tHc6b?xh5:1<1<7?tHc6b?xh5:1=1<7?tHc6b?xh5:121<7?tHc6b?xh5:131<7?tHc6b?xh5:1k1<7?tHc6b?xh5:1h1<7?tHc6b?xh5:1i1<7?tHc6b?xh5:1n1<7?tHc6b?xh5:1o1<7?tHc6b?xh5:1l1<7?tHc6b?xh5:0:1<7=tHc6b?xh5:0;1<7=tHc6b?xh5:081<7=tHc6b?xh5:091<7=tHc6b?xh5:0>1<7=tHc6b?xh5:0?1<7?tHc6b?xh5:0<1<7?tHc6b?xh5:0=1<7?tHc6b?xh5:021<7?tHc6b?xh5:031<7?tHc6b?xh5:0k1<7?tHc6b?xh5:0h1<7?tHc6b?xh5:0i1<7?tHc6b?xh5:0n1<7?tHc6b?xh5:0o1<7?tHc6b?xh5:0l1<7?tHc6b?xh5:h:1<7?tHc6b?xh5:h;1<7?tHc6b?xh5:h81<7?tHc6b?xh5:h91<7?tHc6b?xh5:h>1<7?tHc6b?xh5:h?1<7?tHc6b?xh5:h<1<7?tHc6b?xh5:h=1<7?tHc6b?xh5:h21<7?tHc6b?xh5:h31<7?tHc6b?xh5:hk1<7?tHc6b?xh5:hh1<7?tHc6b?xh5:hi1<7?tHc6b?xh5:hn1<7?tHc6b?xh5:ho1<7?tHc6b?xh5:hl1<7=tHc6b?xh5:k:1<7=tHc6b?xh5:k;1<7=tHc6b?xh5:k81<7=tHc6b?xh5:k91<7=tHc6b?xh5:k>1<7=tHc6b?xh5:k?1<7=tHc6b?xh5:k<1<7=tHc6b?xh5:k=1<7=tHc6b?xh5:k21<7=tHc6b?xh5:k31<7?tHc6b?xh5:kk1<7=tHc6b?xh5:kh1<7?tHc6b?xh5:ki1<7?tHc6b?xh5:kn1<7=tHc6b?xh5:ko1<7?tHc6b?xh5:kl1<7?tHc6b?xh5:j:1<7=tHc6b?xh5:j;1<7?tHc6b?xh5:j81<7?tHc6b?xh5:j91<7?tHc6b?xh5:j>1<7?tHc6b?xh5:j?1<7?tHc6b?xh5:j<1<7?tHc6b?xh5:j=1<7?tHc6b?xh5:j21<7?tHc6b?xh5:j31<7?tHc6b?xh5:jk1<7?tHc6b?xh5:jh1<7?tHc6b?xh5:ji1<7?tHc6b?xh5:jn1<7?tHc6b?xh5:jo1<7?tHc6b?xh5:jl1<7?tHc6b?xh5:m:1<7?tHc6b?xh5:m;1<7?tHc6b?xh5:m81<7?tHc6b?xh5:m91<7?tHc6b?xh5:m>1<7?tHc6b?xh5:m?1<7?tHc6b?xh5:m<1<7?tHc6b?xh5:m=1<7?tHc6b?xh5:m21<7?tHc6b?xh5:m31<7?tHc6b?xh5:mk1<7?tHc6b?xh5:mh1<7?tHc6b?xh5:mi1<7?tHc6b?xh5:mn1<7?tHc6b?xh5:mo1<7?tHc6b?xh5:ml1<7?tHc6b?xh5:l:1<7?tHc6b?xh5:l;1<7?tHc6b?xh5:l81<7?tHc6b?xh5:l91<7?tHc6b?xh5:l>1<7?tHc6b?xh5:l?1<7?tHc6b?xh5:l<1<7?tHc6b?xh5:l=1<7?tHc6b?xh5:l21<7?tHc6b?xh5:l31<7?tHc6b?xh5:lk1<7?tHc6b?xh5:lh1<7?tHc6b?xh5:li1<7?tHc6b?xh5:ln1<7?tHc6b?xh5:lo1<7?tHc6b?xh5:ll1<7?tHc6b?xh5:o:1<7?tHc6b?xh5:o;1<7?tHc6b?xh5:o81<7?tHc6b?xh5:o91<7?tHc6b?xh5:o>1<7?tHc6b?xh5:o?1<7?tHc6b?xh5:o<1<7?tHc6b?xh5:o=1<7?tHc6b?xh5:o21<7?tHc6b?xh5:o31<7?tHc6b?xh5:ok1<7?tHc6b?xh5:oh1<7?tHc6b?xh5:oi1<7?tHc6b?xh5:on1<7?tHc6b?xh5:oo1<7?tHc6b?xh5:ol1<7?tHc6b?xh5;9:1<7?tHc6b?xh5;9;1<7?tHc6b?xh5;981<7?tHc6b?xh5;991<7?tHc6b?xh5;9>1<7?tHc6b?xh5;9?1<7?tHc6b?xh5;9<1<7?tHc6b?xh5;9=1<7?tHc6b?xh5;921<7?tHc6b?xh5;931<7?tHc6b?xh5;9k1<7?tHc6b?xh5;9h1<7?tHc6b?xh5;9i1<7?tHc6b?xh5;9n1<7?tHc6b?xh5;9o1<7?tHc6b?xh5;9l1<7?tHc6b?xh5;8:1<7?tHc6b?xh5;8;1<7?tHc6b?xh5;881<7?tHc6b?xh5;891<7?tHc6b?xh5;8>1<7?tHc6b?xh5;8?1<7?tHc6b?xh5;8<1<7?tHc6b?xh5;8=1<7?tHc6b?xh5;821<7?tHc6b?xh5;831<7?tHc6b?xh5;8k1<7?tHc6b?xh5;8h1<7?tHc6b?xh5;8i1<7?tHc6b?xh5;8n1<7?tHc6b?xh5;8o1<7?tHc6b?xh5;8l1<7?tHc6b?xh5;;:1<7?tHc6b?xh5;;;1<7?tHc6b?xh5;;81<7?tHc6b?xh5;;91<7?tHc6b?xh5;;>1<7?tHc6b?xh5;;?1<7?tHc6b?xh5;;<1<7?tHc6b?xh5;;=1<7?tHc6b?xh5;;21<7?tHc6b?xh5;;31<7?tHc6b?xh5;;k1<7?tHc6b?xh5;;h1<7?tHc6b?xh5;;i1<7?tHc6b?xh5;;n1<7?tHc6b?xh5;;o1<7?tHc6b?xh5;;l1<7?tHc6b?xh5;::1<7?tHc6b?xh5;:;1<7?tHc6b?xh5;:81<7?tHc6b?xh5;:91<7?tHc6b?xh5;:>1<7?tHc6b?xh5;:?1<7?tHc6b?xh5;:<1<7?tHc6b?xh5;:=1<7?tHc6b?xh5;:21<7?tHc6b?xh5;:31<7?tHc6b?xh5;:k1<7?tHc6b?xh5;:h1<7?tHc6b?xh5;:i1<7?tHc6b?xh5;:n1<7?tHc6b?xh5;:o1<7?tHc6b?xh5;:l1<7?tHc6b?xh5;=:1<7?tHc6b?xh5;=;1<7?tHc6b?xh5;=81<7?tHc6b?xh5;=91<7?tHc6b?xh5;=>1<7?tHc6b?xh5;=?1<7?tHc6b?xh5;=<1<7?tHc6b?xh5;==1<7?tHc6b?xh5;=21<7?tHc6b?xh5;=31<7?tHc6b?xh5;=k1<7?tHc6b?xh5;=h1<7?tHc6b?xh5;=i1<7?tHc6b?xh5;=n1<7?tHc6b?xh5;=o1<7?tHc6b?xh5;=l1<7?tHc6b?xh5;<:1<7?tHc6b?xh5;<;1<7?tHc6b?xh5;<81<7?tHc6b?xh5;<91<7?tHc6b?xh5;<>1<7?tHc6b?xh5;<?1<7?tHc6b?xh5;<<1<7?tHc6b?xh5;<=1<7?tHc6b?xh5;<21<7?tHc6b?xh5;<31<7?tHc6b?xh5;<k1<7?tHc6b?xh5;<h1<7?tHc6b?xh5;<i1<7=tHc6b?xh5;<n1<7?tHc6b?xh5;<o1<7=tHc6b?xh5;<l1<7?tHc6b?xh5;?:1<7?tHc6b?xh5;?;1<7?tHc6b?xh5;?81<7?tHc6b?xh5;?91<7?tHc6b?xh5;?>1<7=tHc6b?xh5;??1<7=tHc6b?xh5;?<1<7=tHc6b?xh5;?=1<7=tHc6b?xh5;?21<7=tHc6b?xh5;?31<7=tHc6b?xh5;?k1<7=tHc6b?xh5;?h1<7=tHc6b?xh5;?i1<7=tHc6b?xh5;?n1<7=tHc6b?xh5;?o1<7=tHc6b?xh5;?l1<7=tHc6b?xh5;>:1<7=tHc6b?xh5;>;1<7=tHc6b?xh5;>81<7=tHc6b?xh5;>91<7=tHc6b?xh5;>>1<7=tHc6b?xh5;>?1<7=tHc6b?xh5;><1<7=tHc6b?xh5;>=1<7=tHc6b?xh5;>21<7=tHc6b?xh5;>31<7=tHc6b?xh5;>k1<7=tHc6b?xh5;>h1<7=tHc6b?xh5;>i1<7=tHc6b?xh5;>n1<7=tHc6b?xh5;>o1<7=tHc6b?xh5;>l1<7=tHc6b?xh5;1:1<7=tHc6b?xh5;1;1<7=tHc6b?xh5;181<7=tHc6b?xh5;191<7=tHc6b?xh5;1>1<7=tHc6b?xh5;1?1<7=tHc6b?xh5;1<1<7=tHc6b?xh5;1=1<7=tHc6b?xh5;121<7=tHc6b?xh5;131<7=tHc6b?xh5;1k1<7=tHc6b?xh5;1h1<7=tHc6b?xh5;1i1<7=tHc6b?xh5;1n1<7=tHc6b?xh5;1o1<7=tHc6b?xh5;1l1<7=tHc6b?xh5;0:1<7=tHc6b?xh5;0;1<7=tHc6b?xh5;081<7=tHc6b?xh5;091<7=tHc6b?xh5;0>1<7=tHc6b?xh5;0?1<7=tHc6b?xh5;0<1<7=tHc6b?xh5;0=1<7=tHc6b?xh5;021<7=tHc6b?xh5;031<7=tHc6b?xh5;0k1<7=tHc6b?xh5;0h1<7=tHc6b?xh5;0i1<7=tHc6b?xh5;0n1<7=tHc6b?xh5;0o1<7=tHc6b?xh5;0l1<7=tHc6b?xh5;h:1<7=tHc6b?xh5;h;1<7=tHc6b?xh5;h81<7=tHc6b?xh5;h91<7=tHc6b?xh5;h>1<7=tHc6b?xh5;h?1<7=tHc6b?xh5;h<1<7=tHc6b?xh5;h=1<7=tHc6b?xh5;h21<7=tHc6b?xh5;h31<7=tHc6b?xh5;hk1<7=tHc6b?xh5;hh1<7=tHc6b?xh5;hi1<7=tHc6b?xh5;hn1<7=tHc6b?xh5;ho1<7=tHc6b?xh5;hl1<7=tHc6b?xh5;k:1<7=tHc6b?xh5;k;1<7=tHc6b?xh5;k81<7=tHc6b?xh5;k91<7=tHc6b?xh5;k>1<7=tHc6b?xh5;k?1<7=tHc6b?xh5;k<1<7=tHc6b?xh5;k=1<7=tHc6b?xh5;k21<7=tHc6b?xh5;k31<7=tHc6b?xh5;kk1<7=tHc6b?xh5;kh1<7=tHc6b?xh5;ki1<7=tHc6b?xh5;kn1<7=tHc6b?xh5;ko1<7=tHc6b?xh5;kl1<7=tHc6b?xh5;j:1<7=tHc6b?xh5;j;1<7=tHc6b?xh5;j81<7=tHc6b?xh5;j91<7=tHc6b?xh5;j>1<7=tHc6b?xh5;j?1<7=tHc6b?xh5;j<1<7=tHc6b?xh5;j=1<7=tHc6b?xh5;j21<7=tHc6b?xh5;j31<7=tHc6b?xh5;jk1<7=tHc6b?xh5;jh1<7=tHc6b?xh5;ji1<7=tHc6b?xh5;jn1<7=tHc6b?xh5;jo1<7=tHc6b?xh5;jl1<7=tHc6b?xh5;m:1<7=tHc6b?xh5;m;1<7=tHc6b?xh5;m81<7=tHc6b?xh5;m91<7=tHc6b?xh5;m>1<7=tHc6b?xh5;m?1<7=tHc6b?xh5;m<1<7=tHc6b?xh5;m=1<7=tHc6b?xh5;m21<7=tHc6b?xh5;m31<7=tHc6b?xh5;mk1<7=tHc6b?xh5;mh1<7=tHc6b?xh5;mi1<7=tHc6b?xh5;mn1<7=tHc6b?xh5;mo1<7=tHc6b?xh5;ml1<7=tHc6b?xh5;l:1<7=tHc6b?xh5;l;1<7=tHc6b?xh5;l81<7=tHc6b?xh5;l91<7=tHc6b?xh5;l>1<7=tHc6b?xh5;l?1<7=tHc6b?xh5;l<1<7=tHc6b?xh5;l=1<7=tHc6b?xh5;l21<7=tHc6b?xh5;l31<7=tHc6b?xh5;lk1<7=tHc6b?xh5;lh1<7=tHc6b?xh5;li1<7=tHc6b?xh5;ln1<7=tHc6b?xh5;lo1<7=tHc6b?xh5;ll1<7=tHc6b?xh5;o:1<7=tHc6b?xh5;o;1<7=tHc6b?xh5;o81<7=tHc6b?xh5;o91<7=tHc6b?xh5;o>1<7=tHc6b?xh5;o?1<7=tHc6b?xh5;o<1<7=tHc6b?xh5;o=1<7=tHc6b?xh5;o21<7=tHc6b?xh5;o31<7=tHc6b?xh5;ok1<7=tHc6b?xh5;oh1<7=tHc6b?xh5;oi1<7=tHc6b?xh5;on1<7=tHc6b?xh5;oo1<7=tHc6b?xh5;ol1<7=tHc6b?xh5<9:1<7=tHc6b?xh5<9;1<7=tHc6b?xh5<981<7=tHc6b?xh5<991<7=tHc6b?xh5<9>1<7=tHc6b?xh5<9?1<7=tHc6b?xh5<9<1<7=tHc6b?xh5<9=1<7=tHc6b?xh5<921<7=tHc6b?xh5<931<7=tHc6b?xh5<9k1<7=tHc6b?xh5<9h1<7=tHc6b?xh5<9i1<7=tHc6b?xh5<9n1<7=tHc6b?xh5<9o1<7=tHc6b?xh5<9l1<7=tHc6b?xh5<8:1<7=tHc6b?xh5<8;1<7=tHc6b?xh5<881<7?tHc6b?xh5<891<7?tHc6b?xh5<8>1<7?tHc6b?xh5<8?1<7?tHc6b?xh5<8<1<7?tHc6b?xh5<8=1<7?tHc6b?xh5<821<7;tHc6b?xh5<831<7;tHc6b?xh5<8k1<7;tHc6b?xh5<8h1<7;tHc6b?xh5<8i1<7;tHc6b?xh5<8n1<7;tHc6b?xh5<8o1<7;tHc6b?xh5<8l1<7;tHc6b?xh5<;:1<7;tHc6b?xh5<;;1<7;tHc6b?xh5<;81<7?tHc6b?xh5<;91<7?tHc6b?xh5<;>1<7?tHc6b?xh5<;?1<7?tHc6b?xh5<;<1<7?tHc6b?xh5<;=1<7?tHc6b?xh5<;21<7?tHc6b?xh5<;31<7?tHc6b?xh5<;k1<7?tHc6b?xh5<;h1<7?tHc6b?xh5<;i1<7?tHc6b?xh5<;n1<7?tHc6b?xh5<;o1<7?tHc6b?xh5<;l1<7?tHc6b?xh5<::1<7?tHc6b?xh5<:;1<7?tHc6b?xh5<:81<7?tHc6b?xh5<:91<7=tHc6b?xh5<:>1<7?tHc6b?xh5<:?1<7<tHc6b?xh5<:<1<7?tHc6b?xh5<:=1<7?tHc6b?xh5<:21<7?tHc6b?xh5<:31<7:tHc6b?xh5<:k1<7?tHc6b?xh5<:h1<7?tHc6b?xh5<:i1<7?tHc6b?xh5<:n1<7?tHc6b?xh5<:o1<7?tHc6b?xh5<:l1<7?tHc6b?xh5<=:1<7?tHc6b?xh5<=;1<7?tHc6b?xh5<=81<7?tHc6b?xh5<=91<7?tHc6b?xh5<=>1<7?tHc6b?xh5<=?1<7?tHc6b?xh5<=<1<7?tHc6b?xh5<==1<7?tHc6b?xh5<=21<7?tHc6b?xh5<=31<7?tHc6b?xh5<=k1<7?tHc6b?xh5<=h1<7?tHc6b?xh5<=i1<7?tHc6b?xh5<=n1<7?tHc6b?xh5<=o1<7?tHc6b?xh5<=l1<7?tHc6b?xh5<<:1<7?tHc6b?xh5<<;1<7?tHc6b?xh5<<81<7?tHc6b?xh5<<91<7?tHc6b?xh5<<>1<7?tHc6b?xh5<<?1<7?tHc6b?xh5<<<1<7?tHc6b?xh5<<=1<7?tHc6b?xh5<<21<7?tHc6b?xh5<<31<7?tHc6b?xh5<<k1<7?tHc6b?xh5<<h1<7?tHc6b?xh5<<i1<7?tHc6b?xh5<<n1<7?tHc6b?xh5<<o1<7?tHc6b?xh5<<l1<7?tHc6b?xh5<?:1<7?tHc6b?xh5<?;1<7?tHc6b?xh5<?81<7?tHc6b?xh5<?91<7?tHc6b?xh5<?>1<7?tHc6b?xh5<??1<7?tHc6b?xh5<?<1<7?tHc6b?xh5<?=1<7?tHc6b?xh5<?21<7?tHc6b?xh5<?31<7?tHc6b?xh5<?k1<7?tHc6b?xh5<?h1<7?tHc6b?xh5<?i1<7?tHc6b?xh5<?n1<7?tHc6b?xh5<?o1<7?tHc6b?xh5<?l1<7?tHc6b?xh5<>:1<7?tHc6b?xh5<>;1<7?tHc6b?xh5<>81<7?tHc6b?xh5<>91<7?tHc6b?xh5<>>1<7?tHc6b?xh5<>?1<7?tHc6b?xh5<><1<7?tHc6b?xh5<>=1<7?tHc6b?xh5<>21<7?tHc6b?xh5<>31<7?tHc6b?xh5<>k1<7?tHc6b?xh5<>h1<7?tHc6b?xh5<>i1<7?tHc6b?xh5<>n1<7?tHc6b?xh5<>o1<7?tHc6b?xh5<>l1<7?tHc6b?xh5<1:1<7?tHc6b?xh5<1;1<7?tHc6b?xh5<181<7?tHc6b?xh5<191<7?tHc6b?xh5<1>1<7?tHc6b?xh5<1?1<7?tHc6b?xh5<1<1<7?tHc6b?xh5<1=1<7?tHc6b?xh5<121<7?tHc6b?xh5<131<7?tHc6b?xh5<1k1<7?tHc6b?xh5<1h1<7?tHc6b?xh5<1i1<7?tHc6b?xh5<1n1<7?tHc6b?xh5<1o1<7?tHc6b?xh5<1l1<7?tHc6b?xh5<0:1<7?tHc6b?xh5<0;1<7?tHc6b?xh5<081<78:{I`7e>{i:=386=4>{I`7e>{i:=3?6=4>{I`7e>{i:=3>6=4>{I`7e>{i98l;6=4={I`7e>{i98l:6=4<{I`7e>{i98l96=4<{I`7e>{i98l86=4<{I`7e>{i98l?6=4<{I`7e>{i98l>6=4<{I`7e>{i98l=6=4<{I`7e>{i98l<6=4<{I`7e>{i98l36=4<{I`7e>{i98l26=4<{I`7e>{i98lj6=4<{I`7e>{i98li6=4<{I`7e>{i98lh6=4<{I`7e>{i98lo6=4<{I`7e>{i98ln6=4<{I`7e>{i98lm6=4<{I`7e>{i9;:;6=4<{I`7e>{i9;::6=4<{I`7e>{i9;:96=4<{I`7e>{i9;:86=4<{I`7e>{i9;:?6=4<{I`7e>{ijk;1<7?tHc6b?xhekh0;6<uGb5c8ykddj3:1=vFm4`9~jged290:wEl;a:mffb=83;pDo:n;|lag`<728qCn9o4}o``b?6=9rBi8l5rncf3>5<6sAh?m6sabe394?7|@k>j7p`md383>4}Oj=k0qclk3;295~Ne<h1vbn=::182Md3i2weo9k50;3xLg2f3tdh8k4?:0yKf1g<ugi><7>51zJa0d=zfj?:6=4>{I`7e>{ik<81<7?tHc6b?xhd=:0;6<uGb5c8yke2<3:1=vFm4`9~jf32290:wEl;a:mg00=83;pDo:n;|l`12<728qCn9o4}oaa=?6=9rBi8l5rnbf1>5<6sAh?m6sace194?7|@k>j7p`ld583>4}Oj=k0qcmk5;295~Ne<h1vbnj9:182Md3i2weoi950;3xLg2f3tdhh54?:0yKf1g<ugio57>51zJa0d=zfjnj6=4>{I`7e>{ikmh1<7?tHc6b?xhc;m0;6<uGb5c8ykb2>3:1=vFm4`9~ja30290:wEl;a:m`0>=83;pDo:n;|lg1<<728qCn9o4}of6e?6=9rBi8l5rne7a>5<6sAh?m6sad4a94?7|@k>j7p`k5e83>4}Oj=k0qcj:e;295~Ne<h1vbi;i:182Md3i2wehn?50;3xLg2f3tdohl4?:0yKf1g<ugnon7>51zJa0d=zfmnh6=4>{I`7e>{ilmn1<7?tHc6b?xhcll0;6<uGb5c8ykbcn3:1=vFm4`9~jac7290:wEl;a:m``7=83;pDo:n;|lga7<728qCn9o4}off7?6=9rBi8l5rnd66>5<6sAh?m6sae4g94?7|@k>j7p`j5g83>4}Oj=k0qck90;295~Ne<h1vbh8>:182Md3i2wei;<50;3xLg2f3tdn:>4?:0yKf1g<ugo=87>51zJa0d=zfl<>6=4>{I`7e>{im?<1<7?tHc6b?xhb>>0;6<uGb5c8ykcd13:1=vFm4`9~j`c5290:wEl;a:ma`5=83;pDo:n;|lfa1<728qCn9o4}ogf1?6=9rBi8l5rndg5>5<6sAh?m6saed594?7|@k>j7p`je983>4}Oj=k0qckj9;295~Ne<h1vbhkn:182Md3i2weihl50;3xLg2f3tdm8i4?:0yKf1g<ugl=:7>51zJa0d=zfo<<6=4>{I`7e>{in?21<7?tHc6b?xha>00;6<uGb5c8yk`1i3:1=vFm4`9~jc0e290:wEl;a:mb3e=83;pDo:n;|le2a<728qCn9o4}od5a?6=9rBi8l5rng4e>5<6sAh?m6safe394?7|@k>j7p`ie`83>4}Oj=k0qchjb;295~Ne<h1vbkkl:182Md3i2wejhj50;3xLg2f3tdmih4?:0yKf1g<uglnj7>51zJa0d=zfol;6=4>{I`7e>{ino;1<7?tHc6b?xhan;0;6<uGb5c8yk`a;3:1=vFm4`9~j462=3:1=vFm4`9~j461m3:1=vFm4`9~j461n3:1=vFm4`9~j46083:1=vFm4`9~j46093:1=vFm4`9~j460:3:1=vFm4`9~j460;3:1=vFm4`9~j460<3:1=vFm4`9~j460=3:1=vFm4`9~j460>3:1=vFm4`9~j460?3:1=vFm4`9~j46b>3:1=vFm4`9~j46b?3:1=vFm4`9~j47793:1=vFm4`9~j477:3:1=vFm4`9~j477;3:1=vFm4`9~j477<3:1=vFm4`9~j477=3:1=vFm4`9~j477>3:1=vFm4`9~j477?3:1=vFm4`9~j47703:1=vFm4`9~j47713:1=vFm4`9~j477i3:1=vFm4`9~j477j3:1=vFm4`9~j477k3:1=vFm4`9~j44b93:1=8uGb5c8yk75j=0;6<uGb5c8yk75j<0;6<uGb5c8yk75kl0;6<uGb5c8yk75ko0;6<uGb5c8yk75l90;6<uGb5c8yk75l80;6<uGb5c8yk75l;0;6<uGb5c8yk75l:0;6<uGb5c8yk75l=0;6<uGb5c8yk75l<0;6<uGb5c8yk75l?0;6<uGb5c8yk75l>0;6<uGb5c8yk75l10;6<uGb5c8yk7>>00;6nuGb5c8yk7>;:0;6<uGb5c8yk7>;=0;6<uGb5c8yk7><m0;6<uGb5c8yk7><l0;6<uGb5c8yk7><o0;6<uGb5c8yk7>=90;6<uGb5c8yk7>=80;6<uGb5c8yk7>=;0;6<uGb5c8yk7>=:0;6<uGb5c8yk7>==0;6<uGb5c8yk7>=<0;6<uGb5c8yk7>=?0;6<uGb5c8yk7>=>0;6<uGb5c8yk7f9j0;6nuGb5c8yk7>m?0;6<uGb5c8yk7>m>0;6<uGb5c8yk7f890;6<uGb5c8yk7f880;6<uGb5c8yk7f8;0;6<uGb5c8yk7f8:0;6<uGb5c8yk7f8=0;6<uGb5c8yk7f8<0;6<uGb5c8yk7f8?0;6<uGb5c8yk7f8>0;6<uGb5c8yk7f810;6<uGb5c8yk7f800;6<uGb5c8yk7f8h0;6<uGb5c8yk7fko0;6nuGb5c8yk7f100;6<uGb5c8yk7f1h0;6<uGb5c8yk7fj:0;6<uGb5c8yk7fj=0;6<uGb5c8yk7fj<0;6<uGb5c8yk7fj?0;6<uGb5c8yk7fj>0;6<uGb5c8yk7fj10;6<uGb5c8yk7fj00;6<uGb5c8yk7fjh0;6<uGb5c8yk7fjk0;6<uGb5c8yk7fjj0;6<uGb5c8yk7fjm0;6<uGb5c8yx{zHIIp>47i:5;;20`1itJKNv>r@ARxyEF
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement.bat b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement.bat
deleted file mode 100755
index 61448ec..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement.bat
+++ /dev/null
@@ -1,122 +0,0 @@
-
-REM
-REM   ____  ____
-REM  /   /\/   /
-REM /___/  \  /    Vendor: Xilinx
-REM \   \   \/     Version : 1.12
-REM  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-REM  /   /         Filename : implement_bat.ejava
-REM /___/   /\     
-REM \   \  /  \
-REM  \___\/\___\
-REM
-REM
-REM implement.sh script
-REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-REM
-REM
-REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-REM 
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and 
-REM international copyright and other intellectual property
-REM laws.
-REM 
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-
-REM Set XST as default synthesizer
-
-REM Read command line arguments
-
-REM Change CWD to results
-
-REM Clean results directory
-REM Create results directory
-REM Change current directory to results
-ECHO WARNING: Removing existing results directory
-RMDIR /S /Q results
-MKDIR results
-COPY xst.prj      .\results\
-COPY xst.scr      .\results\
-COPY *.ngc        .\results\
-
-REM Run Synthesis
-
-ECHO "### Running Xst - "
-xst -ifn xst.scr
-
-COPY gtxVirtex6FEE80_top.ngc .\results
-cd .\results
-
-REM Run ngdbuild
-
-ngdbuild -uc ..\..\example_design\gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.ngc gtxVirtex6FEE80_top.ngd
-
-REM end run ngdbuild section
-
-REM Run map
-
-ECHO 'Running NGD'
-map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd
-
-REM Run par
-
-ECHO 'Running par'
-par mapped.ncd routed.ncd 
-
-REM Report par results
-
-ECHO 'Running design through bitgen'
-bitgen -w routed.ncd
-
-REM Trace Report
-
-ECHO 'Running trce'
-trce -e 10 routed.ncd mapped.pcf -o routed
-
-REM Run netgen
-
-ECHO 'Running netgen to create gate level VHDL model'
-netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd
-
-REM Change directory to implement
-
-CD ..
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement.sh b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement.sh
deleted file mode 100644
index 542de01..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement.sh
+++ /dev/null
@@ -1,123 +0,0 @@
-#!/bin/bash
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : implement_sh.ejava 
-## /___/   /\     
-## \   \  /  \
-##  \___\/\___\
-##
-##
-## implement.sh script 
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the GTX wizard
-#-----------------------------------------------------------------------------
-
-##---------------------Change CWD to results-------------------------------------
-
-#Clean results directory
-#Create results directory
-#Change current directory to results
-echo "WARNING: Removing existing results directory"
-rm -rf results
-mkdir results
-cp xst.prj      ./results
-cp xst.scr      ./results
-cp *.ngc        ./results
-
-##-----------------------------Run Synthesis-------------------------------------
-
-echo "### Running Xst - "
-xst -ifn xst.scr
-
-cp gtxVirtex6FEE80_top.ngc ./results
-cd ./results
-
-##-------------------------------Run ngdbuild---------------------------------------
-
-echo 'Running ngdbuild'
-ngdbuild -uc ../../example_design/gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.ngc gtxVirtex6FEE80_top.ngd
-
-#end run ngdbuild section
-
-##-------------------------------Run map-------------------------------------------
-
-echo 'Running map'
-map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd
-
-##-------------------------------Run par-------------------------------------------
-
-echo 'Running par'
-par mapped.ncd routed.ncd
-
-##---------------------------Report par results-------------------------------------
-
-echo 'Running design through bitgen'
-bitgen -w routed.ncd
-
-##-------------------------------Trace Report---------------------------------------
-
-echo 'Running trce'
-trce -e 10 routed.ncd mapped.pcf -o routed 
-
-##-------------------------------Run netgen------------------------------------------
-
-echo 'Running netgen to create gate level VHDL model'
-netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd
-
-#Change directory to implement
-
-cd ..
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement_synplify.bat b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement_synplify.bat
deleted file mode 100755
index 9370a54..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement_synplify.bat
+++ /dev/null
@@ -1,120 +0,0 @@
-
-REM
-REM   ____  ____
-REM  /   /\/   /
-REM /___/  \  /    Vendor: Xilinx
-REM \   \   \/     Version : 1.12
-REM  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-REM  /   /         Filename : implement_synplify_bat.ejava
-REM /___/   /\     
-REM \   \  /  \
-REM  \___\/\___\
-REM
-REM
-REM implement_synplify.bat script
-REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-REM
-REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-REM 
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and 
-REM international copyright and other intellectual property
-REM laws.
-REM 
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-
-REM Set XST as default synthesizer
-
-REM Read command line arguments
-
-REM Change CWD to results
-
-REM Clean results directory
-REM Create results directory
-REM Change current directory to results
-ECHO WARNING: Removing existing results directory
-RMDIR /S /Q results
-MKDIR results
-COPY synplify.prj   .\results\
-COPY *.ngc          .\results\
-
-REM Run Synthesis
-
-ECHO "### Running Synplify Pro - "
-synplify_pro -batch synplify.prj
-
-COPY gtxVirtex6FEE80_top.edf .\results
-cd .\results
-
-REM Run ngdbuild
-
-ngdbuild -uc ..\..\example_design\gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.edf gtxVirtex6FEE80_top.ngd
-
-REM end run ngdbuild section
-
-REM Run map
-
-ECHO 'Running NGD'
-map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd
-
-REM Run par
-
-ECHO 'Running par'
-par mapped.ncd routed.ncd 
-
-REM Report par results
-
-ECHO 'Running design through bitgen'
-bitgen -w routed.ncd
-
-REM Trace Report
-
-ECHO 'Running trce'
-trce -e 10 routed.ncd mapped.pcf -o routed
-
-REM Run netgen
-
-ECHO 'Running netgen to create gate level VHDL model'
-netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd
-
-REM Change directory to implement
-
-CD ..
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement_synplify.sh b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement_synplify.sh
deleted file mode 100644
index a0ff10e..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/implement_synplify.sh
+++ /dev/null
@@ -1,122 +0,0 @@
-#!/bin/bash
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : implement_synplify_sh.ejava 
-## /___/   /\     
-## \   \  /  \
-##  \___\/\___\
-##
-##
-## implement_synplify.sh script 
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-#-----------------------------------------------------------------------------
-# Script to synthesize and implement the RTL provided for the GTX wizard
-#-----------------------------------------------------------------------------
-
-##---------------------Change CWD to results-------------------------------------
-
-#Clean results directory
-#Create results directory
-#Change current directory to results
-echo "WARNING: Removing existing results directory"
-rm -rf results
-mkdir results
-cp synplify.prj    ./results
-cp *.ngc           ./results
-
-##-----------------------------Run Synthesis-------------------------------------
-
-echo "### Running Synplify Pro - "
-synplify_pro -batch synplify.prj
-
-cp gtxVirtex6FEE80_top.edf ./results
-cd ./results
-
-##-------------------------------Run ngdbuild---------------------------------------
-
-echo 'Running ngdbuild'
-ngdbuild -uc ../../example_design/gtxVirtex6FEE80_top.ucf -p xc6vlx130t-ff484-3 gtxVirtex6FEE80_top.edf gtxVirtex6FEE80_top.ngd
-
-#end run ngdbuild section
-
-##-------------------------------Run map-------------------------------------------
-
-echo 'Running map'
-map -p xc6vlx130t-ff484-3 -o mapped.ncd gtxVirtex6FEE80_top.ngd
-
-##-------------------------------Run par-------------------------------------------
-
-echo 'Running par'
-par mapped.ncd routed.ncd
-
-##---------------------------Report par results-------------------------------------
-
-echo 'Running design through bitgen'
-bitgen -w routed.ncd
-
-##-------------------------------Trace Report---------------------------------------
-
-echo 'Running trce'
-trce -e 10 routed.ncd mapped.pcf -o routed 
-
-##-------------------------------Run netgen------------------------------------------
-
-echo 'Running netgen to create gate level VHDL model'
-netgen -ofmt vhdl -sim -dir . -tm gtxVirtex6FEE80_top -w routed.ncd routed.vhd
-
-#Change directory to implement
-
-cd ..
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/planAhead_ise.bat b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/planAhead_ise.bat
deleted file mode 100755
index b613a87..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/planAhead_ise.bat
+++ /dev/null
@@ -1,71 +0,0 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : planAhead_ise.bat 
-## /___/   /\     
-## \   \  /  \
-##  \___\/\___\
-##
-##
-## planAhead_ise.bat script 
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-## planAhead_ise.bat script 
-##
-################################################################################
-
-#-----------------------------------------------------------------------------
-# Command to run the planAhead in batch mode 
-#-----------------------------------------------------------------------------
-planAhead -mode batch -source planAhead_ise.tcl
-#end
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/planAhead_ise.sh b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/planAhead_ise.sh
deleted file mode 100644
index b17a4eb..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/planAhead_ise.sh
+++ /dev/null
@@ -1,71 +0,0 @@
-#!/bin/bash
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : planAhead_ise.sh 
-## /___/   /\     
-## \   \  /  \
-##  \___\/\___\
-##
-##
-## planAhead_ise.sh script 
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-##
-################################################################################
-
-#-----------------------------------------------------------------------------
-# Command to run the planAhead in batch mode 
-#-----------------------------------------------------------------------------
-planAhead -mode batch -source ./planAhead_ise.tcl
-#end
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/planAhead_ise.tcl b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/planAhead_ise.tcl
deleted file mode 100644
index 1a986c3..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/planAhead_ise.tcl
+++ /dev/null
@@ -1,127 +0,0 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : planAhead_ise.tcl 
-## /___/   /\     
-## \   \  /  \
-##  \___\/\___\
-##
-##
-## planAhead_ise.tcl script 
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-##
-##
-################################################################################
-
-## Environment Setup
-set projDir  [file dirname [info script]]
-set projName gtxVirtex6FEE80
-set topName  gtxVirtex6FEE80_top
-set device   xc6vlx130t-ff484-3
-
-## if the project directory exists, delete it and create a new clean one
-if {[file exists $projDir/$projName]} {
-file delete -force $projDir/$projName
-}
-
-## Create Project
-create_project $projName $projDir/$projName -part $device
-
-## Project Option
-set_property design_mode RTL [get_filesets sources_1]
-
-## Source Files
-add_files -norecurse ../example_design/mgt_usrclk_source_mmcm.vhd
-add_files -norecurse ../example_design/gtxvirtex6fee80_tx_sync.vhd
-add_files -norecurse ../example_design/gtxvirtex6fee80_rx_sync.vhd
-add_files -norecurse ../example_design/double_reset.vhd
-add_files -norecurse ../example_design/frame_gen.vhd
-add_files -norecurse ../example_design/frame_check.vhd
-add_files -norecurse ../../gtxvirtex6fee80_gtx.vhd
-add_files -norecurse ../../gtxvirtex6fee80.vhd
-add_files -norecurse ../example_design/gtxvirtex6fee80_top.vhd
-
-## UCF Files
-import_files -fileset [get_filesets constrs_1] -force -norecurse ../example_design/gtxVirtex6FEE80_top.ucf
-import_files -fileset [get_filesets constrs_1] -force -norecurse ../example_design/gtx_attributes.ucf
-
-## NGC Files
-import_files -fileset [get_filesets sources_1] -force -norecurse ../implement/data_vio.ngc 
-import_files -fileset [get_filesets sources_1] -force -norecurse ../implement/ila.ngc 
-import_files -fileset [get_filesets sources_1] -force -norecurse ../implement/icon.ngc
- 
- 
-
-## Set the Top module
-set_property top $topName [get_property srcset [current_run]]
-
-## Run Synthesis
-launch_runs -runs synth_1
-wait_on_run synth_1
-
-## Run Implementation
-set_property strategy {ISE Defaults} [get_runs impl_1]
-
-
-#config_run -run impl_1 -program par -option -ol -value high
-
-launch_runs -runs impl_1
-wait_on_run impl_1
-
-## Run BitGen
-set_property add_step Bitgen [get_runs impl_1]
-launch_runs -runs impl_1
-wait_on_run impl_1
-
-exit
-## End
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/rx_phase_align_fifo.ngc b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/rx_phase_align_fifo.ngc
deleted file mode 100644
index 29e63a0..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/rx_phase_align_fifo.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
-$66741<,[o}e~g`n;"2*776&=$:;-*>;1784567801;<=>?012305=789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456682:;J>76FC2345?>10;0=>5>.13:?45=G\^[YY4]D@FGV@ED4881<3?;;06:>LHW]]0oec2>4983:40<9=31CXZ_UU8gkpr;9=21<3?n;069MKVR\3KOH_O]D@FGV974294:m6?;:HLSQQ<FLMXI[_OKDS>27?699k1:97GAPTV9EABUI[NJHI\Z<0694;7e38?1EC^ZT;CG@WDPZHNO^X2>4;2=5d=6>3CE\XZ5AEFQEWBFLMX7=84?>0`853<NFY__6LJKR@PGEABUD5;>6=0>a:35>LHW]]0JHI\MWSCG@W:6=3:5=o5>6;KMTPR=IMNYNZ\NDEPO843=87;?7<85IORVP?BNIMC7=84?>06853<NFY__6IGMDH>21?699<1::7AZTQWW>AIFLF6:97>114922?IR\Y__6IAMDN>21?69928:56<5IORVP?GCL[K_EHFFGI>2>5861281EC^ZT;CG@WDSALBBKE2>:1<20>4=AGZ^X7JFP@FJT97=87;?7?4FNQWW>AOWJMC[0<4?>0786?IR\Y__6IA_AEMS84<768?0>7AZTQWW>AIWJME[0<4?>06877<NFY__6IGNDH>05?699=18>7GAPTV9@LDCA59:6=0>5:11>JSSX\^1HBOKO=12>586=2996B[[PTV9@JDCG59:6=0>4:69MKVR\3NB\LJFP=194;733=0BB][[:EKSFAOW4:0;2<>44;KMTPR=_LK7?7>11097>LHW]]0\ILB33;2=54=32@D[YY4XE@W?7?699l1?6D@_UU8svjaXmdzuRzgrdqk86<76;?087GAPTV9twi`Wlg{xtQ{hsgplZgt{lx0>4?>3780?OIX\^1|ah_dosp|Ys`{oxdR`jg`vf86<768n087GAPTV9twi`Wog`Rzgrdqk86<76;>087GAPTV9twi`Wog`Rzgrdqk[dutm{~7?7>12597>LHW]]0{~biPftno[qnumzbTbhintd>0>586=2>1CXZ_UU8GKUGCGY686=0>5:69KPRW]]0OC]LKOQ>0>58602>1CXZ_UU8geqgXkfex1=50?3a?1<H]]Z^X7|k_ecweZeh}g~7?7>11c97>JSSX\^1{Qkauc\gjsi|591<3?46595=<053?K?7;ONA0282C@1NOLMJKHI6GD555=1~er:?=zif0362(468229<=>?83A04567K:;;75<7212;6F5D;9:H?<<48;KMTPR=_LH\I1950?30?=<NFY__6ZKMWDN?3?699:136D@_UU8TAGQB]5=1<3?8;98LQQVR\3OHO]O]IU[?3?69:23=867608g8EABUI[NJHI\30?d8EABUI[NJHI\311<e?DBCZHXOMIJ]<03=b>GCL[KYHLJKR=31:47<IMNYM_JNDEP?56<76o1JHI\NRECG@W:6;7l0MIJ]ASFB@AT;9=4:=6OKDSCQ@DBCZ5;>6=0i;@FGVDTCIMNY0<;1e:CG@WGULHNO^1?1e:CG@WGULHNO^1<1e:CG@WGULHNO^1=1e:CG@WGULHNO^1:1e:CG@WGULHNO^1;1e:CG@WGULHNO^181e:CG@WGULHNO^191e:CG@WGULHNO^161e:CG@WGULHNO^171f:CG@WGULHNO^A2?>028EABUI[NJHI\C<02=55=FLMXJ^IOKDSN?548682KOH_O]D@FGVI:6:7;;7LJKR@PGEABUD5;82<>4AEFQEWBFLMXG0<:1139B@ATFZMKOH_B31483:46<IMNYM_JNDEPO8439n2KOH_O]D@FGVI:66o1JHI\NRECG@WJ;:7l0MIJ]ASFB@ATK4:4m7LJKR@PGEABUD5>5j6OKDSCQ@DBCZE6>2k5NDEPBVAGCL[F7:3h4AEFQEWBFLMXG0:0i;@FGVDTCIMNY@161f:CG@WGULHNO^A26>g9B@ATFZMKOH_[30?33?DBCZHXOMIJ]U=33:46<IMNYM_JNDEPV8479991JHI\NRECG@WS;9;4:<6OKDSCQ@DBCZ\6:?3?=;@FGVDTCIMNYY1?;:1<24>GCL[KYHLJKRT>20;`<IMNYM_JNDEPV848a3HNO^L\KAEFQQ949n2KOH_O]D@FGVP:46o1JHI\NRECG@WS;<7l0MIJ]ASFB@ATR4<4m7LJKR@PGEABU]5<5j6OKDSCQ@DBCZ\6<2k5NDEPBVAGCL[_743h4AEFQEWBFLMX^040i;@FGVDRNMACLD1>1109B@ATF\@OCEJF31;2=b>GCL[K_EHFFGI>2:c=FLMXIXDKGIFJ?4;763HNO^OZFEIKDL97=87l0MIJ]BUKFLLAO484n7LJKRCUQEABU494m7LJKRCUQEABU48:5j6OKDS@TVDBCZ5;:2k5NDEPASWGCL[6:>3?>;@FGVGQUIMNY0<=50?d8EABUJ^XJHI\312<e?DBCZK]YMIJ]<06=54=FLMXI[_OKDS>21?69n2KOH_LXR@FGV9726l1JHI\MWSCG@W:66l1JHI\MWSCG@W:56l1JHI\MWSCG@W:46l1JHI\MWSCG@W:36l1JHI\MWSCG@W:26l1JHI\MWSCG@W:16l1JHI\MWSCG@W:06l1JHI\MWSCG@W:?6l1JHI\MWSCG@W:>6o1JHI\MWSCG@WJ;87;;7LJKRCUQEABUD5;;2<>4AEFQFRTFLMXG0<?1119B@ATE_[KOH_B313<24>GCL[H\^LJKRM>27;773HNO^OY]AEFQH9736880MIJ]BVPB@ATK48?1<3??;@FGVGQUIMNY@1?:>g9B@ATE_[KOH_B31?d8EABUJ^XJHI\C<3<e?DBCZK]YMIJ]L=1=b>GCL[H\^LJKRM>7:c=FLMXI[_OKDSN?1;`<IMNYNZ\NDEPO838a3HNO^OY]AEFQH919n2KOH_LXR@FGVI:?6o1JHI\MWSCG@WJ;17l0MIJ]BVPB@ATR494:<6OKDS@TVDBCZ\6:<3??;@FGVGQUIMNYY1?>>028EABUJ^XJHI\Z<00=55=FLMXI[_OKDSW?5686:2KOH_LXR@FGVP:6<3:5==5NDEPASWGCL[_7=90i;@FGVGQUIMNYY1?1f:CG@WDPZHNO^X2=>g9B@ATE_[KOH_[33?d8EABUJ^XJHI\Z<5<e?DBCZK]YMIJ]U=7=b>GCL[H\^LJKRT>5:c=FLMXI[_OKDSW?3;`<IMNYNZ\NDEPV8=8a3HNO^OY]AEFQQ9?9;2KG@45NSXL@[WC@;2H^>55MUR]JJCI63Jk0OL]LAEGJJDg<KHYHMIKFNC`8GDUDIMODYYOm;BCPGDBBG\^I>6MJ139@L@ELWECHIC]J_U[SA<=DDBKYHNBDa:AOODTCKEAGm6MCK@PGGIMR12IGGOY]CMIb?FJLJ^XH@FBn;BNHFRTDDB_87NB]9:ALIHOS\LN:86M@RD]DAKCUI]CDBRGAFN58GWCF\LN:7I94DCKWAWT?3MCJHD2?>89GMDBN48:556JFAEK?548>3MCJHD2>2?;8@LGCA5;8245KI@FJ8429j2NBMIG31483:<=CAHNB0<;19:FJEAO;9?427IGNDH>23;?<L@KOE1?7>89GMDBN483546JFAEK?5;?<L@KOE1<?>89GMDBN4;;556JFAEK?678>3MCJHD2=3?;8@LGCA58?245KI@FJ873912NBMIG327<:?AOFL@69;374DHCGM94?601OELJF<3;=<>BNIMC7>374DHCGM9576k1OELJF<2394;?<L@KOE1=>>99GMDBN4:437IGNDH>7:==CAHNB0807;EKB@L:1611OELJF<6<;?AOFL@63255KI@FJ8<8?3MCIHD2?>89GMGBN48:556JFBEK?548>3MCIHD2>2?;8@LDCA5;8245KICFJ8429j2NBNIG31483:<=CAKNB0<;19:FJFAO;9?427IGMDH>23;?<L@HOE1?7>89GMGBN483546JFBEK?5;?<L@HOE1<?>89GMGBN4;;556JFBEK?678>3MCIHD2=3?;8@LDCA58?245KICFJ873912NBNIG327<:?AOEL@69;374DH@GM94?601OEOJF<3;=<>BNJMC7>374DH@GM9576k1OEOJF<2394;?<L@HOE1=>>99GMGBN4:437IGMDH>7:==CAKNB0807;EKA@L:1611OEOJF<6<;?AOEL@63255KICFJ8<8f3MC[MIG_<1<`?AOWIMC[0<4?>`9GMUGCAY6:2l5KIQCGMU:56j1OE]OKIQ>0>58f3MC[MIG_<2<b?AOWJMC[0=0l;EKSFAOW480;2l5KIQ@GMU:66h1OE]LKIQ>1:f=CAYHOE]2<:1<b?AOWJMC[0>07;EMB@J:7601OCLJ@<02==>BHIME7=<06;EMB@J:6:730HBOKO=30:<=CGHND0<:1b:FLEAI;9<0;245KO@FL843912NDMIA317<:?AIFLF6:;374DNCGK97?601OCLJ@<0;=<>BHIME7=374DNCGK947601OCLJ@<33==>BHIME7>?06;EMB@J:5;730HBOKO=07:<=CGHND0?;19:FLEAI;:?427IANDN>13;?<LFKOC1<7>89GKDBH4;3546J@AEM?6;?<LFKOC1=?>c9GKDBH4:;1<374DNCGK956611OCLJ@<2<;?AIFLF6?255KO@FL808?3MEJHB29>99GKDBH4>437IANDN>;:==CGHND0408;EMB[WC@02NDNIA30?;8@JDCG5;;245KOCFL847912NDNIA313<:?AIELF6:?374DN@GK9736k1OCOJ@<0794;?<LFHOC1?:>89GKGBH48<556J@BEM?528>3MEIHB2>8?;8@JDCG5;2255KOCFL848>3MEIHB2=0?;8@JDCG58:245KOCFL874912NDNIA322<:?AIELF698374DN@GK942601OCOJ@<34==>BHJME7>:06;EMA@J:50730HBLKO=0::==CGKND0?06;EMA@J:487h0HBLKO=12>58>3MEIHB2<1?:8@JDCG59546J@BEM?0;><LFHOC1;18:FLFAI;>720HBLKO=5=<>BHJME74364DN@GK9?9?2NDNR\JG`9GKUGCGY6;2n5KOQCGKU:6294j7IA_AEMS848f3ME[MIA_<3<`?AIWIME[0>4?>`9GKUGCGY682l5KOQ@GKU:76j1OC]LKOQ>2>58f3ME[NIA_<0<b?AIWJME[0?0l;EMSFAIW4:0;2l5KOQ@GKU:46j1NON^NRHVZ858d3LIH\L\FTX>2:f=BKJZJ^DZV<3<`?@EDXHXBXT2<>b9FGFVFZ@^R090l;DA@TDTN\P6>2n5JCBRBVLR^4?4n7HMLP@PJP\:0294h7HMLP@PJP\:06>1NBL\KEO:8AKGULLDG46KAASFFJP1<MGH\^H@7;DLASWCID11NBOY]EOWa?@HXMJIT^HOKc:GM[@EDW^XBXH<4F378BDJTM;1MH>5IDB68BAEB;2LO\95IDQG24>@A:9LM<=<?212345773OLMJKHIF6F4@C@0L81L?6IAD09J6>O7:2C:>6G=2:K06>O3:2C>46GAIUR\45><AGC_\R>>8:KMMQVX8;20ECG[P^20<>OIA]ZT<964IOKWTZ6202CEEY^P07:8MKOSXV:<46GAIUR\4=><AGC_\R>68:KMMQVX8H20ECG[P^2A<>OIA]ZT<N64IOKWTZ6C02CEEY^P0D:8MKOSXV:M56GAIUQWEQC03@DBXR>?7:KMMQY79>1BBDZP0358MKOSW99<7D@FT^273>OIA]U;9:5FNHV\431<AGC_S=98;HLJPZ6??2CEEYQ?969JJLRX8H=0ECG[_1@4?LHN\V:H;6GAIU]3@2=NF@^T<H94IOKW[5@03@DBXR??7:KMMQY69>1BBDZP1358MKOSW89<7D@FT^373>OIA]U:9:5FNHV\531<AGC_S<98;HLJPZ7??2CEEYQ>969JJLRX9H=0ECG[_0@4?LHN\V;H;6GAIU]2@2=NF@^T=H94IOKW[4@03@DBXR<?7:KMMQY59>1BBDZP2358MKOSW;9<7D@FT^073>OIA]U99:5FNHV\631<AGC_S?98;HLJPZ4??2CEEYQ=969JJLRX:H=0ECG[_3@4?LHN\V8H;6GAIU]1@2=NF@^T>H94IOKW[7@03@DBXR=?7:KMMQY49>1BBDZP3358MKOSW:9<7D@FT^173>OIA]U89:5FNHV\731<AGC_S>98;HLJPZ5??2CEEYQ<969JJLRX;H=0ECG[_2@4?LHN\V9H;6GAIU]0@2=NF@^T?H94IOKW[6@03@DBXR:?7:KMMQY39>1BBDZP4358MKOSW=9<7D@FT^673>OIA]U?9:5FNHV\031<AGC_S998;HLJPZ2??2CEEYQ;969JJLRX<H=0ECG[_5@4?LHN\V>H;6GAIU]7@2=NF@^T8H94IOKW[1@03@DBXR;?7:KMMQY29>1BBDZP5358MKOSW<9<7D@FT^773>OIA]U>9:5FNHV\131<AGC_S898;HLJPZ3??2CEEYQ:969JJLRX=H=0ECG[_4@4?LHN\V?H;6GAIU]6@2=NF@^T9H94IOKW[0@03@DBXR8?7:KMMQY19>1BBDZP6358MKOSW?9<7D@FT^473>OIA]U=9:5FNHV\231<AGC_S;98;HLJPZ0??2CEEYQ9969JJLRX>H=0ECG[_7@4?LHN\V<H;6GAIU]5@2=NF@^T:H94IOKW[3@03@DBXR9?7:KMMQY09>1BBDZP7358MKOSW>9<7D@FT^573>OIA]U<9:5FNHV\331<AGC_S:98;HLJPZ1??2CEEYQ8969JJLRX?H=0ECG[_6@4?LHN\V=H;6GAIU]4@2=NF@^T;H94IOKW[2@13@DBXRO9;HLJPZD>3@DBXRHFLDf8MKLBK]NIEYK]Re9JJOCD\ZHBXH\]3:KMR3=KGHNNH:5COFK@EI2<D\^986BZT268HPR3<2F^X;;4MRELJf=JiceyZh||inl`?Hoig{\n~~g`n29M444<F8>0B<>?4:L2442<F8:986@>0268J463<2D:<8:4N0250>H68>>0B<>74:L24<5<F8;?7C?>059M54733G;:>95A1017?K76<=1E=<;;;O3221=I98=?7C?>859M54?43G;986@>2168J446<2D:>?:4N0000>H6:=>0B<<:4:L2632<F88<86@>2968J44>;2D:?95A1227?K749=1E=><;;O3071=I9:>?7C?<559M56033G;8;95A12:7?K741:1E=9:4N0630>H6<8>0B<:=4:L2062<F8>?86@>4468J421<2D:8::4N06;0>H6<090B<;;;O3641=I9<;?7C?:259M50533G;>895A1477?K72>=1E=89;;O36<1=I9<387C?94:L2252<F8<:?6@>729M5=2<F822?6@>959M5<633G;2=95A1807?K7>;=1E=4:;;O3:11=I90<?7C?6759M5<>33G;25?5A229M652<F;:;86@=0068J765<2D9<>:4N3270>H58<>0B?>94:L1422<F;:386@=0818J7733G8:<95A2037?K46:=1E><=;;O0201=I:8??7C<>659M64133G8:495A20;0?K45<2D9>=:4N3020>H5:;>0B?<<4:L1612<F;8>86@=2768J740<2D9>5:4N30:7>H5;=1E>>>;;O0051=I::8?7C<<359M66233G88995A2247?K44?=1E>>6;;O00=6=I:=>0B?:?4:L1042<F;>986@=4268J723<2D988:4N3650>H5<>>0B?:74:L10<5<F;??7C<:059M60733G8>>95A2417?K42<=1E>8;;;O0621=I:<=?7C<:859M60?43G8=86@=6168J706<2D9:?:4N3400>H5>=>0B?8:4:L1232<F;<<86@=6968J70>;2D9;95A2627?K409=1E>:<;;O0471=I:>>?7C<8559M62033G8<;95A26:7?K401:1E>5:4N3:30>H508>0B?6=4:L1<62<F;2?86@=8468J7>1<2D94::4N3:;0>H50090B?7;;O0:41=I:0;?7C<6259M6<533G82895A2877?K4>>=1E>49;;O0:<1=I:0387C=?4:L0452<F:::86@<0368J664<2D8<9:4N2260>H48?>0B>>84:L04=2<F::2?6@<159M74633G9:=95A3007?K56;=1E?<:;;O1211=I;8<?7C=>759M74>33G9:5>5A3368J647<2D8><:4N2010>H4::>0B><;4:L0602<F:8=86@<2668J64?<2D8>4=4N217?K548=1E?>?;;O1061=I;:9?7C=<459M76333G98:95A3257?K540:1E?9:4N2617>H4=:1E?;=4N250?K5?;2D85?5A429M055<F=;87C:=3:L776=I<=90B9;<;O657>H3?:1E85=4N5;1?K343G?;?6@:129M175<F<987C;;3:L616=I=?90B89<;O7;7>H21:1E:==4N730?K05;2D=?>5A6518J3343G<=?6@9729M2=5<F?397C9<;O537>H09:1E;?=4N610?K13;2D<9>5A7718J2143G=3?6@8929M<55<F1;87C6=3:L;76=I0=90B5;<;O:57>H??:1E45=4N9;1?K?43G3;?6@6129M=75<F0987C7;3:L:16=I1?90B49<;O;;7>H>1o1ENRLZSQKM[UTHXZ=0BHZXOSI7?KIIM81D>6AD1:R7?UGU\h1[ECQMURKG\g=WAGUIY^@NMD;8TNYOD\^EA>5_RD38U==UIDH:4H?7;SCNF60B9o1YM@QJXUGMWLIIWHl0^LCPEYVFJVOHFVH37_OB_LMGAf=ULHNO^HML<1<g?WBFLMXNON2>0?f8VAGCL[OHO1?>>g9Q@DBCZLIH0<<50?f8VAGCL[OHO1?=>b9Q@DBCZLIH0<0l;SFB@ATBKJ692n5]D@FGV@ED4:4h7_JNDEPFGF:36j1YHLJKRDA@808d3[NJHI\JCB>5:f=ULHNO^HML<6<`?WBFLMXNON27>b9Q@DBCZLIH040n;SGB@Z@NZZ^h7_KND^UJ@QNXIj1YILJPWHFWLZD23[OLOHl4RDE@ADTBOJOh7_KHCDCQABEBDj1YIJMJASGDG@S13[OLOHL8;SGDG@DK?2XNKNKMUe9QABEKCHXO^NBDe:PFCFJLI[NYOAECe:PFCFJLI[NYOAEZ7:PFCFJLJ11YIJMCKCN;?WC@KEAIYi5]SUPBIDTT\[KFi6\\TSCNEWUSZHGGi6\\TSCNEWUSZHG^;6\\TSCNF==U[]XJAOB7;SQWVDKE]m1Y_Y\JG@PPPWC@m2XXX_KHASQWV@AKm2XXX_KHASQWV@AR?2XXX_KHB99QWQTBOKF37_][RDEAQ47<ZZ^YIJQ_RHMQMQ_XI8;0^^Z]EF]SVLIUA]STN55\AWGGEQG03ZHBXH\]3:QGT45<[@GTOBBCIRKLJZEOMJA37^EFP^RJJ3=TG\XHI:5\RWCO[D1<[[\J@RL;;UPVA1=SQYO986[?/fpe*w`(ojr%oaew/LzlvZh789>Ttb2?>007?P6(o{l%~k!hcy,`hn~(EqeySc>?04]{k9699;>0Y=!hrg,qb*adp'iggu!Bxnp\j567>Vrd0=0>259V4*aun'xm#jmw.bnh|*Kg{Ue<==?_ym?4;75<2_;#j|i.sd,cf~)keas#@v`r^l3467Xpf6;2<<;;T2,cw`)zo%lou lljz,I}iuWg:;??Qwo=2=54><]9%l~k }f.e`|+ekcq%e<=>;199V4*aun'xm#jmw.bnh|*h789?:46[?/fpe*w`(ojr%oaew/o23437?3\:$kh!rg-dg}(ddbr$b=>=20;8Q5)`zo$yj"ilx/aoo})i8989=<64U1-dvc(un&mht#mcky-m4544901^<"i}f/pe+be&jf`t"`?03125==R8&myj#|i/fa{*fjlp&d;<?:>8:W3+bta&{l$knv!cmi{+k67;9;37X> gsd-vc)`kq$h`fv n12054><]9%l~k }f.e`|+ekcq%e<===199V4*aun'xm#jmw.bnh|*h78=2:56[?/fpe*w`(ojr%oaew/o230=7602_;#j|i.sd,cf~)keas#c>?483:?P6(o{l%~k!hcy,`hn~(f9:?5<?7;T2,cw`)zo%lou lljz,j5628;;0Y=!hrg,qb*adp'iggu!}d^rmpwYeag6;2??4U1-dvc(un&mht#mcky-q`Zvi|{Uiec2>>338Q5)`zo$yj"ilx/aoo})ulVzexQmio>1:77<]9%l~k }f.e`|+ekcq%yhR~ats]amk:46;:0Y=!hrg,qb*adp'iggu!}d^rmpwYeagU;>=5Z0.eqb+ta'nis"nbdx.pg[uhszVhbbR?=0:W3+bta&{l$knv!cmi{+wbXxg~ySoga_303?P6(o{l%~k!hcy,`hn~(zmU{by|Pbhl\776<]9%l~k }f.e`|+ekcq%yhR~ats]dg969:91^<"i}f/pe+be&jf`t"|k_qlwvZad4849<6[?/fpe*w`(ojr%oaew/sf\tkruWni7>3<?;T2,cw`)zo%lou lljz,vaYwf}xTkn2<>0d8Q5)`zo$yj"ilx/aoo})ulVzexQhc^22b>S7'nxm"h gbz-gim'{nT|cz}_fa\54`<]9%l~k }f.e`|+ekcq%yhR~ats]dgZ46n2_;#j|i.sd,cf~)keas#jPpovq[beX;;<0Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hi30?05?P6(o{l%~k!hcy,`hn~(zmU{by|Pgb]bwwc`4849:6[?/fpe*w`(ojr%oaew/sf\tkruWniTm~|jg=0=63=R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumn682?;4U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\473<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmT=?;4U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\673<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmT??74U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\`4:76;30Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hiPd0>2:7?<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmTh<2=>3;8Q5)`zo$yj"ilx/aoo})ulVzexQhc^cpv`aXl8682?64U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\`4Y7:11^<"i}f/pe+be&jf`t"|k_qlwvZadWhyyijQk1^31<>S7'nxm"h gbz-gim'{nT|cz}_fa\evtboVn:S?<7;T2,cw`)zo%lou lljz,vaYwf}xTknQnssgd[a7X;;20Y=!hrg,qb*adp'iggu!}eew`aZ~hzV;:=Rv`<1<26==R8&myj#|i/fa{*fjlp&xnhxmj_ymq[776Wqe7<3?=1:W3+bta&{l$knv!cmi{+rtXxg~ySoga<1<15>S7'nxm"h gbz-gim'~xT|cz}_ckm848592_;#j|i.sd,cf~)keas#z|Ppovq[goi4;49=6[?/fpe*w`(ojr%oaew/vp\tkruWkce0>0=0:W3+bta&{l$knv!cmi{+rtXxg~ySoga_103?P6(o{l%~k!hcy,`hn~({U{by|Pbhl\576<]9%l~k }f.e`|+ekcq%|~R~ats]amkY5:91^<"i}f/pe+be&jf`t"y}_qlwvZdnfV99<6[?/fpe*w`(ojr%oaew/vp\tkruWni7<3<?;T2,cw`)zo%lou lljz,swYwf}xTkn2>>328Q5)`zo$yj"ilx/aoo})pzVzexQhc=0=65=R8&myj#|i/fa{*fjlp&}yS}`{r^e`8686n2_;#j|i.sd,cf~)keas#z|Ppovq[beX88l0Y=!hrg,qb*adp'iggu!xr^rmpwY`kV;:j6[?/fpe*w`(ojr%oaew/vp\tkruWniT><h4U1-dvc(un&mht#mcky-tvZvi|{UloR==6:W3+bta&{l$knv!cmi{+rtXxg~ySjmParpfc969:?1^<"i}f/pe+be&jf`t"y}_qlwvZadWhyyij2>>348Q5)`zo$yj"ilx/aoo})pzVzexQhc^cpv`a;:78=7X> gsd-vc)`kq$h`fv ws]sjqtXojUjkh<2<11>S7'nxm"h gbz-gim'~xT|cz}_fa\evtboV:996[?/fpe*w`(ojr%oaew/vp\tkruWniTm~|jg^311>S7'nxm"h gbz-gim'~xT|cz}_fa\evtboV8996[?/fpe*w`(ojr%oaew/vp\tkruWniTm~|jg^11=>S7'nxm"h gbz-gim'~xT|cz}_fa\evtboVn:0=0=9:W3+bta&{l$knv!cmi{+rtXxg~ySjmParpfcZb6484956[?/fpe*w`(ojr%oaew/vp\tkruWniTm~|jg^f2878512_;#j|i.sd,cf~)keas#z|Ppovq[beXizxnkRj><2<1<>S7'nxm"h gbz-gim'~xT|cz}_fa\evtboVn:S=<7;T2,cw`)zo%lou lljz,swYwf}xTknQnssgd[a7X9;20Y=!hrg,qb*adp'iggu!xr^rmpwY`kVkx~hiPd0]16==R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumnUo=R==0:W3+bta&{l$ka>!re-dvdu)zz~x#c>?3104?P6(o{l%~k!hl1,q`*auiz$yy} n1204473WZ];>>5Z0.eqb+ta'nf;"j gscp*wus{&d;<>>>3301?P6(o{l%~k!hl1,q`*auiz$yy} n120412592_;#j|i.sd,ci6)zm%l~l}!rrvp+k67;9=9>6[?/fpe*w`(oe:%~i!hr`q-vvrt'g:;?=78289V4*aun'xm#jb?.sf,cwgt&{y"|nm^gntqXnkUb>;5Z0.eqb+ta'nf;"j gscp*wus{&xjaRkbpu{\m4b<]9%l~k }f.eo4+tc'{kfSjPeo]j57?<]9%l~k }f.eo4+tc'{zex!Bmtz\j566=8;TECXP0318Q5)`zo$yj"ic0/pg+wvi|{%FaxvPn1221775;2_;#j|i.sd,ci6)zm%y|cz}/fa3*firf}6;2?=4U1-dvc(un&mg<#|k/srmpw)`k9$hcx`{<0<17>S7'nxm"h gm2-va)uxg~y#jm?.bmvjq:56;90Y=!hrg,qb*ak8'xo#~ats-dg5(dg|d0>0=2:W3+bta&{l$ka>!re-qtkru'ni;"naznu]367=R8&myj#|i/fn3*wb(zyd~"il0/alqkrX9;80Y=!hrg,qb*ak8'xo#~ats-dg5(dg|dS?<=;T2,cw`)zo%l`= }d.psjqt(oj:%ob{at^112>S7'nxm"h gm2-va)uxg~y#jm?.bmvjqYc95:5>;5Z0.eqb+ta'nf;"j rqlwv*ad8'idyczPd0>2:70<]9%l~k }f.eo4+tc'{zex!hc1,`kphsWm;7>3<9;T2,cw`)zo%l`= }d.psjqt(oj:%ob{at^f28685=2_;#j|i.sd,ci6)zm%y|cz}/fa3*firf}Uo=R>=5:W3+bta&{l$ka>!re-qtkru'ni;"naznu]g5Z75=2_;#j|i.sd,ci6)zm%y|cz}/fa3*firf}Uo=R<=5:W3+bta&{l$ka>!re-qtkru'ni;"naznu]g5Z56n2_;#j|i.sd,ci6)zm%y|cz}/o2350:768l0Y=!hrg,qb*ak8'xo#~ats-m4572484:j6[?/fpe*w`(oe:%~i!}povq+k679<692?>4U1-dvc(un&mg<#|k/srmpw)i89;>0?0>1g9V4*aun'xm#jb?.sf,vuhsz&d;<<;33?03?P6(o{l%~k!hl1,q`*twf}x$b=>>5=1=576<]9%l~k }f.eo4+qu'n}j#y|tr-m4557::1^<"i}f/pe+bj7&~x$kzo|.vqww*h78:::>8<8;T2,cw`)zo%l`= xr.etev(p{}y$b=><0006[VQ7:>1^<"i}f/pe+bj7&~x$kzo|.vqww*h78:::>8Q\W001?P6(o{l%~k!hl1,tv*apiz$|y} n1204=7502_;#j|i.sd,ci6){%l{l}!wrvp+wgjWog`Rhm_h06?P6(o{l%~k!hl1,tv*apiz$|y} r`o\bpjkW`;o7X> gsd-vc)`d9$|~"|nm^uq[`hXa8827X> gsd-vc)`d9$|~"ynup,IhsWg:;=8?>_HLU[5443\:$kh!rg-dh5(pz&}{by| Mlw{[k679<8:>55Z0.eqb+ta'nf;"z| wqlwv*ank9$lo= lotlw858502_;#j|i.sd,ci6){%||cz}/fk`4+ad8'idycz31?0;?P6(o{l%~k!hl1,tv*qwf}x$kdm?.fa3*firf}692?64U1-dvc(un&mg<#y}/vrmpw)`aj:%kn>!cnwmp959:>1^<"i}f/pe+bj7&~x${}`{r.ejg5(`k9$hcx`{_104?P6(o{l%~k!hl1,tv*qwf}x$kdm?.fa3*firf}U:>:5Z0.eqb+ta'nf;"z| wqlwv*ank9$lo= lotlw[7403\:$kh!rg-dh5(pz&}{by| gha3*be7&je~byQ<2c9V4*aun'xm#jb?.vp,suhsz&mbo= hc1,`kphsWm;7<3<m;T2,cw`)zo%l`= xr.usjqt(o`i;"jm?.bmvjqYc95;5>o5Z0.eqb+ta'nf;"z| wqlwv*ank9$lo= lotlw[a7;:78i7X> gsd-vc)`d9$|~"ynup,cle7&ni;"naznu]g5959:h1^<"i}f/pe+bj7&~x${}`{r.ejg5(`k9$hcx`{_e3\47g<]9%l~k }f.eo4+qu'~zex!hib2-cf6)kfexRj>_00b?P6(o{l%~k!hl1,tv*qwf}x$kdm?.fa3*firf}Uo=R<=a:W3+bta&{l$ka>!ws-ttkru'nch<#il0/alqkrXl8U8>o5Z0.eqb+ta'nf;"z| wqlwv*ank9$lo= lotlw[a4;878i7X> gsd-vc)`d9$|~"ynup,cle7&ni;"naznu]g6979:k1^<"i}f/pe+bj7&~x${}`{r.ejg5(`k9$hcx`{_e0?6;4e3\:$kh!rg-dh5(pz&}{by| gha3*be7&je~byQk2=1=6d=R8&myj#|i/fn3*rt(yd~"ifc1,dg5(dg|dSi<P03c8Q5)`zo$yj"ic0/uq+rvi|{%len>!gb2-gjsi|Vn9S<<n;T2,cw`)zo%l`= xr.usjqt(o`i;"jm?.bmvjqYc:V89m6[?/fpe*w`(oe:%{!xpovq+bod8'mh<#m`uov\`7Y49o1^<"i}f/pe+bj7&~x${}`{r.l3443;87;m7X> gsd-vc)`d9$|~"ynup,j566=5;5=k5Z0.eqb+ta'nf;"z| wqlwv*h788?7>3<?;T2,cw`)zo%l`= xr.usjqt(f9::91<110d8Q5)`zo$yj"ic0/uq+rvi|{%e<=?:<2<14>S7'nxm"h gm2-sw)pxg~y#c>?14>0:4113\:$kh!rg-nah)`jd$ln`i!gcode+h`mji%n`i bmi\i`kXoldn~lz`r.tbhlb)kz~y#oblnms_5[)zhg%~"x9_omjjlr)zhg$_I^!WHFF[UTNE82%~lc86:W3+bta&{l$ahc gco-cgk`&nhfkl agda`*gk`'kf`S`kb_fgmawgsg{%}magk.bqwv*tfeeed|V?R.scn*w)q>Vddecg{.scn+VBW&^COIR^]IL15*wgj??1^<"i}f/pe+hcj'nhf"jlbg/eaibg)fnoho#lbg.`ooZkbeVmnbh|ntnp,rdjnl'ixx!}alnlku]5U'xja#| v7]mklhn|'xja"]KP/UJ@@YWZ@G8:#|nm0d8Q5)`zo$yj"cjm.eai+rjxVxjaR|k_dl14>S7'nxm"h mdo,cgk)|dzT~lcPre]fj4743\:$kh!rg-qehYulVoe=>5Z0.eqb+ta'{kfSz|Peo0`?P6(o{l%~k!}su`oo*h`{nyy hrrv-vaYu{}Uyij2?>3a8Q5)`zo$yj"||tcnh+kapzmxxx#i}su,q`Ztt|Vxnk1?12b9V4*aun'xm#}{bmi,jbqul{y"j||t/pg[wusW{ol0?0=b:W3+bta&{l$~~zmlj-mcrtczz~%k}{.sf\vvrXzlmT<?l4U1-dvc(un&xxxobd/oetvatt|'myy }d^pppZtboV;9n6[?/fpe*w`(zz~i`f!agvpgvvr)o{y"jPrrv\v`aX:;i0Y=!hrg,qb*tt|kf`#cixreppp+au{}$|~R||t^pfc969:j1^<"i}f/pe+wusjea$bjy}dsqw*btt|'}yS}{_sgd8485j2_;#j|i.sd,vvredb%ekz|krrv-cwus&~xT~~zPrde\47d<]9%l~k }f.pppgjl'gm|~i||t/eqwq(pzVxxxR|jg^32`>S7'nxm"h rrvahn)ulVxxxRo|rde14>S7'nxm"h rrvahn)ulVxxxRo|rde\`4473\:$kh!rg-qwqdkc&xoS}{_`qqabYc:8i0Y=!hrg,qb*tt|kf`#jPrrv\gjke9m1^<"i}f/pe+wusjea$~iQ}su]`khd69m1^<"i}f/pe+wusjea${Q}su]bwwc`:91^<"i}f/pe+wusjea${Q}su]bwwc`Wm;9<6[?/fpe*w`(zz~i`f!xr^pppZgtzlmTh??l;T2,cw`)zo%yylck.uq[wusWjefn<j4U1-dvc(un&xxxobd/vp\vvrXkfgi=l5ZSDP\EIOF[j1^_H\PVHQJFIC43_IH56XFEV]W]UC13^OJ0=09;VGB84813^OJ0?07;VGB86<76?1\IL2<>69TADJ;87=0[HOC<0<4?RCFD58556YJAM>0>5803^OJ@1=17:UFEP:76>1\IL[31?58S@GR4;427ZKNU=194;1<_LK^0>07;VGAS@:7611\IOYJ<0<;?RCE_L69255XECUF868?3^OI[H2;>99TAGQB4<437ZKMWD>5:d=PMK]N0:4?>99TAGQB4>427ZKMWDN?4;?<_LH\IA2>>89TAGQBD58556YJBVGO868>3^OI[HB34?;8S@DPME6>245XECUFH909j2]NNZKC<683:<=PMK]N@1919:UFFRCR49427ZKMWDW?5;?<_LH\IX2=>89TAGQB]59556YJBVGV818>3^OI[H[35?;8S@DPM\6=2o5XECUFQ91=8730[HLXET>4:f=PZ@^NS@AKE^C`?RTN\LUFCIKPBe9TVLRBW^COXEQNd:UQMQCX_@N_DRL>d:ZJHLH_%QNI,= > RVVF%6)9)KXODG9;YQWHLD03QY_SJ@K7:ZPPZPDKk1SSNA]E^KMBJ0<PmhTEih4Xej\Twoj^lxxeb`>0:ZgiZKfbfx]i}foo33?]bjWDcecXjrrklj7c<WVUS@CCP_^2\[ZS7'nxm"h gm2-va)uxg~y#c>?14>0:44b3VUTTA@B_^]2[ZYR8&myj#|i/fn3*rt(yd~"`?007?7;75?2UTSUBAM^]\6ZYX]9%l~k }f.e`|+ekcq%e<=:61358[ZY_DGGTSR=P_^W3+bta&{l$knv!cmi{+k67::;h7lbborv\ahvsqk1j``a|t^dvhi0<jhi`y}j4b`ahquYji{an~>5lljf8`drfWje~by&?)e9geqgXkfex%?&d:fbpdYdg|d$?'k;ecweZeh}g~#?$h4d`vb[firf}686=08;e`jp`tu>2nbb%>&6:fjj-7.?2nbb%??)99gmk.689#37iga(022-==cag":<?'7;ekm,464!11oec&>05+;?aoi 8:>%55kio*243/?3mce$<>8)99gmk.681#37iga(02:-2=cag":=$64dhl+546.02nbb%?>1(:8`lh/988"46jfn)327,><l`d#=<:&8:fjj-76= 20hd`'104*<>bnf!;:;$64dhl+54>.02nbb%?>9(58`lh/9;#37iga(003-==cag":><'7;ekm,445!11oec&>22+;?aoi 88?%55kio*260/?3mce$<<9)99gmk.6:>#37iga(00;-==cag":>4'8;ekm,45.02nbb%?<0(:8`lh/9:;"46jfn)306,><l`d#=>=&8:fjj-74< 20hd`'127*<>bnf!;8:$64dhl+561.02nbb%?<8(:8`lh/9:3";6jfn)37-==cag":8='7;ekm,426!11oec&>43+;?aoi 8>8%55kio*201/?3mce$<::)99gmk.6<?#37iga(064-==cag":85'8;ekm,43.?2nbb%?9)69gmk.6? =0hd`'19+4?aoi 83":6jfn)0*3>bnf!8;%:5kio*15,1<l`d#>?'8;ekm,75.?2nbb%<;)69gmk.5= =0hd`'27+4?aoi ;=";6jfn)0;-2=cag"95$84dhl+7,1<l`d#?='8;ekm,67.?2nbb%==)69gmk.4; =0hd`'35+4?aoi :?";6jfn)15-2=cag"8;$94dhl+7=/03mce$>7&6:fjj-2.?2nbb%:?)69gmk.39 =0hd`'43+4?aoi =9";6jfn)67-2=cag"?9$94dhl+03/03mce$99&7:fjj-2?!>1oec&;9(48`lh/= =0hd`'51+4?aoi <;";6jfn)71-2=cag">?$94dhl+11/03mce$8;&7:fjj-31!>1oec&:7(58`lh/=1#<7iga(4;*2>bnf!<";6jfn)43-2=cag"==$94dhl+27/03mce$;=&7:fjj-03!>1oec&95(58`lh/>?#<7iga(75*3>bnf!<3%:5kio*5=,0<l`d#;$94dhl+35/03mce$:?&7:fjj-15!>1oec&83(58`lh/?=#<7iga(67*3>bnf!==%:5kio*43,1<l`d#;5'8;ekm,2?.>2nbb%6&7:fjj->7!>1oec&71(58`lh/0;#<7iga(91*3>bnf!2?%:5kio*;1,1<l`d#4;'8;ekm,=1.?2nbb%67)69gmk.?1 <0hd`'9(58`lh/19#<7iga(83*3>bnf!39%:5kio*:7,1<l`d#59'8;ekm,<3.?2nbb%79)69gmk.>? =0hd`'99+4?aoi 03":6jfn=2=<>bnf5;;<364dhl?557902nbb1??2?:8`lh;999546jfn=330;><l`d7==;18:fjj977>720hd`3115=<>bnf5;;4364dhl?55?9?2nbb1??>99gmk:699437iga<032:==cag6:=?07;ekm8474611oec2>15<;?aoi48;>255kio>2538?3mce0<?8>99gmk:691437iga<03::2=cag6:=364dhl?576902nbb1?=1?:8`lh;9;8546jfn=317;><l`d7=?:18:fjj975=720hd`3134=<>bnf5;9;364dhl?57>902nbb1?=9?58`lh;9;437iga<013:==cag6:?<07;ekm8455611oec2>32<;?aoi489?255kio>2708?3mce0<=9>99gmk:6;>437iga<01;:==cag6:?408;ekm845902nbb1?;0?:8`lh;9=;546jfn=376;><l`d7=9=18:fjj973<720hd`3157=<>bnf5;?:364dhl?5119i2nbb1?;8;2=<>bnf5;?4394dhl?51803mce0<;17:fjj9716>1oec2>7?58`lh;914<7iga<0;=2>bnf5;5;6jfn=03:2=cag69=394dhl?67803mce0?=17:fjj9436>1oec2=5?58`lh;:?4<7iga<35=3>bnf5832:5kio>1=;0<l`d7>394dhl?75803mce0>?17:fjj9556>1oec2<3?58`lh;;=4<7iga<27=3>bnf59=2:5kio>03;1<l`d7?508;ekm86?9>2nbb1=17:fjj9276>1oec2;1?58`lh;<;4<7iga<51=3>bnf5>?2:5kio>71;1<l`d78;08;ekm8119?2nbb1:7>69gmk:317<0hd`34?58`lh;=94<7iga<43=3>bnf5?92:5kio>67;1<l`d79908;ekm8039?2nbb1;9>69gmk:2?7=0hd`359<4?aoi4<35:6jfn=7=3>bnf5<;2:5kio>55;1<l`d7:?08;ekm8359?2nbb18;>69gmk:1=7=0hd`367<4?aoi4?=5;6jfn=4;:2=cag6=5384dhl?2;1<l`d7;=08;ekm8279?2nbb19=>69gmk:0;7=0hd`375<4?aoi4>?5;6jfn=55:2=cag6<;394dhl?3=803mce0:716:fjj919?2nbb16?>69gmk:?97=0hd`383<4?aoi4195;6jfn=:7:2=cag639394dhl?<3803mce05917:fjj9>?6>1oec279?48`lh;07=0hd`391<4?aoi40;5;6jfn=;1:2=cag62?394dhl?=1803mce04;17:fjj9?16>1oec267?58`lh;114<7iga<8;=2>bnf535;6j`uu*3-2=cg|~#=$64dnww,46.12ndyy&>01+:?air|!;;=$74dnww,465!01ocxz'111*=>bh}}":<9'6;emvp-77= 30hb{{(025-<=cg|~#==9&9:flqq.681#27iazt)33=,><lf$<?&9:flqq.699#27iazt)325,?<lf$<?=)89gkpr/989"56j`uu*251/>3me~x%?>5(;8`jss 8;=%45kotv+541.12ndyy&>19+:?air|!;:5$64dnww,44.12ndyy&>21+:?air|!;9=$74dnww,445!01ocxz'131*=>bh}}":>9'6;emvp-75= 30hb{{(005-<=cg|~#=?9&9:flqq.6:1#27iazt)31=,><lf$<=&9:flqq.6;9#27iazt)305,?<lf$<==)89gkpr/9:9"56j`uu*271/>3me~x%?<5(;8`jss 89=%45kotv+561.12ndyy&>39+:?air|!;85$64dnww,42.12ndyy&>41+:?air|!;?=$74dnww,425!01ocxz'151*=>bh}}":89'6;emvp-73= 30hb{{(065-<=cg|~#=99&9:flqq.6<1#37iazt)36-==cg|~#=;'7;emvp-70!11ocxz'19+;?air|!;2%:5kotv+6,><lf$?>&8:flqq.59 20hb{{(30*<>bh}}"9?$64dnww,72.02ndyy&=5(:8`jss ;<"46j`uu*13,><lf$?6&8:flqq.51 =0hb{{(2+;?air|!9;%55kotv+74/?3me~x%==)99gkpr/;:#37iazt)17-==cg|~#?8'7;emvp-51!11ocxz'36+;?air|!93%55kotv+7</03me~x%:&8:flqq.38 20hb{{(53*<>bh}}"?>$64dnww,15.02ndyy&;4(:8`jss =?"46j`uu*72,><lf$99&8:flqq.30 20hb{{(5;*3>bh}}">%55kotv+15/?3me~x%;>)99gkpr/=;#37iazt)70-==cg|~#99'7;emvp-32!11ocxz'57+;?air|!?<%55kotv+1=/?3me~x%;6)69gkpr/> 20hb{{(72*<>bh}}"==$64dnww,34.02ndyy&93(:8`jss ?>"46j`uu*51,><lf$;8&8:flqq.1? 20hb{{(7:*<>bh}}"=5$94dnww,2/?3me~x%9?)99gkpr/?8#37iazt)51-==cg|~#;>'7;emvp-13!11ocxz'74+;?air|!==%55kotv+32/?3me~x%97)99gkpr/?0#<7iazt):*<>bh}}"3<$64dnww,=7.02ndyy&72(:8`jss 19"46j`uu*;0,><lf$5;&8:flqq.?> 20hb{{(95*<>bh}}"34$64dnww,=?.?2ndyy&6)99gkpr/19#37iazt);2-==cg|~#5?'7;emvp-?4!11ocxz'95+;?air|!3>%55kotv+=3/?3me~x%78)99gkpr/11#37iazt);:-2=cg|~7<374dnww8467601ocxz3113==>bh}}6:<?06;emvp977;730hb{{<027:<=cg|~7==;19:flqq:68?427iazt=333;?<lf0<>7>89gkpr;993546j`uu>24;?<lf0<??>89gkpr;98;556j`uu>2578>3me~x1?>3?;8`jss48;?245kotv?543912ndyy2>17<:?air|5;:;374dnww847?601ocxz310;=<>bh}}6:=374dnww8447601ocxz3133==>bh}}6:>?06;emvp975;730hb{{<007:<=cg|~7=?;19:flqq:6:?427iazt=313;?<lf0<<7>89gkpr;9;3546j`uu>26;?<lf0<=?>89gkpr;9:;556j`uu>2778>3me~x1?<3?;8`jss489?245kotv?563912ndyy2>37<:?air|5;8;374dnww845?601ocxz312;=<>bh}}6:?374dnww8427601ocxz3153==>bh}}6:8?06;emvp973;730hb{{<067:<=cg|~7=9;19:flqq:6<?427iazt=373;d<lf0<:7:1<:?air|5;?4364dnww842902ndyy2>5?:8`jss48<546j`uu>23;><lf0<618:flqq:617=0hb{{<0<;?air|58;255kotv?648?3me~x1<=>99gkpr;::437iazt=07:==cg|~7>807;emvp941611ocxz326<;?air|583255kotv?6<803me~x1<18:flqq:48720hb{{<23=<>bh}}68>364dnww865902ndyy2<4?:8`jss4:?546j`uu>02;><lf0>918:flqq:40720hb{{<2;=3>bh}}68255kotv?058?3me~x1:>>99gkpr;<;437iazt=60:==cg|~78907;emvp922611ocxz347<;?air|5><255kotv?0=8?3me~x1:6>69gkpr;<720hb{{<42=<>bh}}6>=364dnww804902ndyy2:3?:8`jss4<>546j`uu>61;><lf08818:flqq:2?720hb{{<4:=<>bh}}6>5394dnww808?3me~x18?>99gkpr;>8437iazt=41:==cg|~7:>07;emvp903611ocxz364<;?air|5<=255kotv?228?3me~x187>99gkpr;>04<7iazt=4=<>bh}}6<<364dnww827902ndyy282?:8`jss4>9546j`uu>40;><lf0:;18:flqq:0>720hb{{<65=<>bh}}6<4364dnww82?9?2ndyy28>99gkpr;09437iazt=:2:==cg|~74?07;emvp9>4611ocxz385<;?air|52>255kotv?<38?3me~x168>99gkpr;01437iazt=:::2=cg|~74364dnww8<6902ndyy261?:8`jss408546j`uu>:7;><lf04:18:flqq:>=720hb{{<84=<>bh}}62;364dnww8<>902ndyy269?58`jss40437hjff3ld`0=bey~r>k5iigm\c`hbzh~d~Rx:_2.#\ljnfq*HC_K/Gdlfvdrhz);:">:4ftno`>oiblihog{espg?lhmmj~xndzjrs58mkrXkea37cilbtko`==h~lxm`byn;qplcZcjx}s:86~}of]fiur~W}byi~f'0(37?uthoVof|ywPtipfwm.6!8>0|ah_dosp|Ys`{oxd%<&159svjaXmdzuRzgrdqk,6/6>2zycjQjmqvz[qnumzb7?7>11c9svjaXmdzuRzgrdqk[dutm{~#<$?m;qplcZcjx}sTxe|jsi]bwvcu|!;"=o5rne\ahvsqV~c~h}g_`qpawr/: ;i7}|`g^gntqX|axneQnsrgqp-5.9m1{~biPelrw}ZrozlycSl}|esv?7?699k1{~biPelrw}ZrozlycSckhaug+4,7e3yxdkRkbpu{\pmtb{aUeijo{e)3*5g=wzfmTi`~{y^vkv`uoWgolmyk'2(3a?uthoVof|ywPtipfwmYimnki%=&1e9svjaXmdzuRzgrdqk[kc`i}o7?7>19:rqkbYa}ef:?6~}of]eqijX|axne&?)018twi`Wog`Rzgrdqk,4/6;2zycjQiumn\pmtb{a"9%<=4psmd[cskdV~c~h}g(2+21>vugnUmyabPtipfwm:4294:m6~}of]eqijX|axneQnsrgqp-6.9h1{~biPftno[qnumzbTm~}jru*2-4g<x{elSk{cl^vkv`uoWhyxiz'2(3b?uthoVl~`aQ{hsgplZgt{lx$>'>c:rqkbYa}efTxe|jsi]bwvcu|591<3?n;qplcZ`rdeUdk|h^lfcdrb 9#:m6~}of]eqijX|axneQaefcwa-7.9h1{~biPftno[qnumzbTbhintd*1-4g<x{elSk{cl^vkv`uoWgolmyk'3(3`?uthoVl~`aQ{hsgplZhboh~n0>4?>79q`Zekc8:0~iQkauc\gjsi|!:"==5}d^fbpdYdg|d$<'>0:pg[agsiVidycz'2(33?wbXlh~jSnaznu*0-44<zmUomyoPcnwmp95=87?0~iQjn79q`Ztt|:1yy?<;sz\tmgtmVkgej`Pfhdl74=upVzcm~kPamkdjZ`nnf&mekaPgdlfvdrhzV|>S>"AOOG/JJHB;lk0~uQh`qf[djnogUmeka#fhdl[bcim{kcQy5^1/fYoizUbbyQllj?3(fYoizUx~~z20-a\vaYazl{6=!mPeocah`Yu{}Uxucm21-a\lduXzmUomyoPcnwmp86+kVnbbRyfduj>51?+kVbjRy}_ecweZeh}g~6<!mPftno[cjfozUyyQyam?2(fYneyfnah`{aukljZr~xl79 nQzsd]figccllnT~hi20-a\swYazl{6=!mPurg\`jssW{y1<"l_tlgaw`kg~Ugcz3?,b]kevYh~lxm`by20-a\twckghnT`lzjnb{>5)eXlfSzgkti?20<*dWdylccQyam?2(fYulVnn|yf217.`[`tug{Ubbgklthmm[qwm4:'oRfns^wm``tadf}6<!mPh`q\eikh{}Umyab20-a\lduXzz~6=!mPd`vb[firf}U|eizg=5.`[mgtW~xTmne20-a\qvcXmji6<!mPcnonkkYddfi`1="l_vp\efmXdf}6<!mPre]sjqtX`nd0:#c^wpaZ`pn}UomyoPcnwmp86+kVbjRocmnqw[`kw|p7; nQ}d^fbpdYdg|dSzgkti?7(fYh~lxm`byPlnu>4)eX{U{by|Pwhfwl82+kVzycjQjmqvz[qwm4:'oRy}_ecweZeh}g~T{dj{h<6/gZvumeejhR|jgr?3(fYcg|~T~~zPv`n>4)eX`hyThlzn_bmvjq;7$jU{~biPftno[qnumzbTbhintd]uei;6:%iT{Qkeqvk940+kVzycjQjmqvz[qnumzbTbhintd]uei;4$jU{~biPelrw}ZrozlycSl}|esv\rdj::%iTdl}Pv`nj`86+kVzycjQiumn\pmtb{aUj~k}t^tbh874$jef|b`jnu]mehc:zqU{dl}j_`njckYaaoe'oRxnlhf\hjq:8%iT|gb_gkekZr~xl7>=?v82-a\twi`Wog`Rzvpd?3(fYjmdeyuRzvpd?2(x4c3{rT|eo|e^combhXn`ldSkgio^efj`tf|fxTz8Q<_yqw[41<{kci|;;rppp4`<|dz$Sni ry]sldubWhfbkcQiigm-jbi>3|doihcov78rdjnl?1|~Rolk79tvZekc8:0{Qkauc\gjsi|!:"==5xr^fbpdYdg|d$<'>0:uq[agsiVidycz'2(33?rtXlh~jSnaznu*0-44<{UomyoPcnwmp95=87?0{Qjn79tvZtt|tJK|n:<;AB{36>=N3>1=v]l0;534?1=9:82<<95f`::k2>13;0b97n:49'0<1=<080q^lj:623>2<6;;3;=:4ia9;8W77a2>:<6=4>33;352<ai1k0_ok571594?74:0::;7hn8e9g364=83;1=v]l0;534?1=9:82<<95f`::?sR41o0;6<4>:0;5Ve72>:;6:4>33;352<ai130(98<:303?S2>038py?<9:09v671=82w/?;=5369a364=83;8=7=5123xL1063Skm6?un:88~ 6g42>997):66;536>o0:o0;66g84383>>i08:0;66a80083>>o0;j0;66g83083>>i18j0;6)=95;4:b>h4>=0;76a90c83>!51=3<2j6`<6582?>i18h0;6)=95;4:b>h4>=0976a90883>!51=3<2j6`<6580?>i1810;6)=95;4:b>h4>=0?76a90683>!51=3<2j6`<6586?>i18?0;6)=95;4:b>h4>=0=76a90483>!51=3<2j6`<6584?>i18=0;6)=95;4:b>h4>=0376a90383>!51=3<2j6`<658:?>i1880;6)=95;4:b>h4>=0j76a90183>!51=3<2j6`<658a?>i2no0;6)=95;4:b>h4>=0h76a:fd83>!51=3<2j6`<658g?>i2nm0;6)=95;4:b>h4>=0n76a:fb83>!51=3<2j6`<658e?>i2nk0;6)=95;4:b>h4>=0:<65`5gc94?"4><0=5k5a376954=<g<l26=4+37792<`<f:<?6<<4;n7e3?6=,:<>6;7i;o150?7432e>j;4?:%151?0>n2d8:94>4:9l1c3=83.8:8499g9m732=9<10c8h;:18'733=>0l0b>8;:048?j3a;3:1(>8::7;e?k51<3;<76a:f383>!51=3<2j6`<6582<>=h=o;1<7*<6485=c=i;?>1=454o4d3>5<#;??1:4h4n247>4g<3f?nj7>5$246>3?a3g9=87?m;:m6a`<72-9=9786f:l021<6k21d9hm50;&020<11o1e?;:51e98k0ce290/?;;568d8j60328o07b;ja;29 6022?3m7c=94;3e?>i2m00;6)=95;4:b>h4>=09<65`5d:94?"4><0=5k5a376964=<g<o<6=4+37792<`<f:<?6?<4;n7f2?6=,:<>6;7i;o150?4432e>i84?:%151?0>n2d8:94=4:9l1`2=83.8:8499g9m732=:<10c8k<:18'733=>0l0b>8;:348?j3b93:1(>8::7;e?k51<38<76a:e183>!51=3<2j6`<6581<>=h=ml1<7*<6485=c=i;?>1>454o4ff>5<#;??1:4h4n247>7g<3f?oh7>5$246>3?a3g9=87<m;:m6`f<72-9=9786f:l021<5k21d9il50;&020<11o1e?;:52e98k0bf290/?;;568d8j6032;o07b;k9;29 6022?3m7c=94;0e?>i2l10;6)=95;4:b>h4>=08<65`67;94?"4><0=5k5a376974=<g?<36=4+37792<`<f:<?6><4;n453?6=,:<>6;7i;o150?5432e=:;4?:%151?0>n2d8:94<4:9l233=83.8:8499g9m732=;<10c;8;:18'733=>0l0b>8;:248?j01;3:1(>8::7;e?k51<39<76a96383>!51=3<2j6`<6580<>=h>?;1<7*<6485=c=i;?>1?454o743>5<#;??1:4h4n247>6g<3f<>i7>5$246>3?a3g9=87=m;:m51a<72-9=9786f:l021<4k21d:8m50;&020<11o1e?;:53e98k33e290/?;;568d8j6032:o07b8:a;29 6022?3m7c=94;1e?>i1=00;6)=95;4:b>h4>=0?<65`64:94?"4><0=5k5a376904=<g??<6=4+37792<`<f:<?69<4;n462?6=,:<>6;7i;o150?2432e=984?:%151?0>n2d8:94;4:9l205=83.8:8499g9m732=<<10c;;=:18'733=>0l0b>8;:548?j0293:1(>8::7;e?k51<3><76a95183>!51=3<2j6`<6587<>=h>=l1<7*<6485=c=i;?>18454o76f>5<#;??1:4h4n247>1g<3f<?h7>5$246>3?a3g9=87:m;:m50f<72-9=9786f:l021<3k21d:9l50;&020<11o1e?;:54e98k32f290/?;;568d8j6032=o07b8;8;29 6022?3m7c=94;6e?>i1<>0;6)=95;4:b>h4>=0><65`65494?"4><0=5k5a376914=<g?>>6=4+37792<`<f:<?68<4;n470?6=,:<>6;7i;o150?3432e=8>4?:%151?0>n2d8:94:4:9l214=83.8:8499g9m732==<10c;:>:18'733=>0l0b>8;:448?j0383:1(>8::7;e?k51<3?<76a93g83>!51=3<2j6`<6586<>=h>:n1<7*<6485=c=i;?>19454o71`>5<#;??1:4h4n247>0g<3f<8n7>5$246>3?a3g9=87;m;:m57d<72-9=9786f:l021<2k21d:>750;&020<11o1e?;:55e98k35?290/?;;568d8j6032<o07b8<7;29 6022?3m7c=94;7e?>i1;?0;6)=95;4:b>h4>=0=<65`62794?"4><0=5k5a376924=<g?9?6=4+37792<`<f:<?6;<4;n406?6=,:<>6;7i;o150?0432e=?<4?:%151?0>n2d8:9494:9l266=83.8:8499g9m732=><10c;<i:18'733=>0l0b>8;:748?j05m3:1(>8::7;e?k51<3<<76a92e83>!51=3<2j6`<6585<>=h>;i1<7*<6485=c=i;?>1:454o70a>5<#;??1:4h4n247>3g<3f<9m7>5$246>3?a3g9=878m;:m56<<72-9=9786f:l021<1k21d:?950;&020<11o1e?;:56e98k341290/?;;568d8j6032?o07b8=5;29 6022?3m7c=94;4e?>i1:=0;6)=95;4:b>h4>=0<<65`63194?"4><0=5k5a376934=<g?896=4+37792<`<f:<?6:<4;n415?6=,:<>6;7i;o150?1432e=>=4?:%151?0>n2d8:9484:9l24`=83.8:8499g9m732=?<10c;?j:18'733=>0l0b>8;:648?j06k3:1(>8::7;e?k51<3=<76a91c83>!51=3<2j6`<6584<>=h>8k1<7*<6485=c=i;?>1;454o73:>5<#;??1:4h4n247>2g<3f<:47>5$246>3?a3g9=879m;:m552<72-9=9786f:l021<0k21d:<850;&020<11o1e?;:57e98k372290/?;;568d8j6032>o07b8>4;29 6022?3m7c=94;5e?>i19:0;6)=95;4:b>h4>=03<65`60394?"4><0=5k5a3769<4=<g?;;6=4+37792<`<f:<?65<4;n43b?6=,:<>6;7i;o150?>432e=<h4?:%151?0>n2d8:9474:9l25b=83.8:8499g9m732=0<10c;><:18'733=>0l0b>8;:948?j3a03:1(>8::7;e?k51<32<76a:ee83>!51=3<2j6`<658;<>=h=l81<7*<6485=c=i;?>14454o4f4>5<#;??1:4h4n247>=g<3f<>j7>5$246>3?a3g9=876m;:m511<72-9=9786f:l021<?k21d:9750;&020<11o1e?;:58e98k35b290/?;;568d8j60321o07b8<3;29 6022?3m7c=94;:e?>i1:10;6)=95;4:b>h4>=02<65`60f94?"4><0=5k5a3769=4=<g?;96=4+37792<`<f:<?64<4;n7g2?6=,:<>6;7i;o150??432e>h84?:%151?0>n2d8:9464:9j0`7=83.8:84:759m732=821b8h>50;&020<2?=1e?;:51:9j0a`=83.8:84:759m732=:21b8ik50;&020<2?=1e?;:53:9j0ab=83.8:84:759m732=<21b8im50;&020<2?=1e?;:55:9j0ad=83.8:84:759m732=>21b8io50;&020<2?=1e?;:57:9j0a?=83.8:84:759m732=021b8i950;&020<2?=1e?;:59:9j0a0=83.8:84:759m732=i21b8i;50;&020<2?=1e?;:5b:9j0a2=83.8:84:759m732=k21b8i=50;&020<2?=1e?;:5d:9j0a4=83.8:84:759m732=m21b8i?50;&020<2?=1e?;:5f:9j0a6=83.8:84:759m732=9910e9mi:18'733==>>0b>8;:038?l2dm3:1(>8::457?k51<3;976g;cb83>!51=3?<86`<65827>=n<jh1<7*<648631=i;?>1=954i5ab>5<#;??19::4n247>43<3`>h57>5$246>0133g9=87?9;:k7g=<72-9=97;84:l021<6?21b8n950;&020<2?=1e?;:51998m1e1290/?;;55668j60328307d:l5;29 6022<=?7c=94;3b?>o3k=0;6)=95;740>h4>=0:n65f4b194?"4><0>;95a37695f=<a=i:6=4+3779122<f:<?6<j4;h6`4?6=,:<>689;;o150?7b32c?nk4?:%151?30<2d8:94>f:9j0gc=83.8:84:759m732=:910e9lk:18'733==>>0b>8;:338?l2ek3:1(>8::457?k51<38976g;bc83>!51=3?<86`<65817>=n<kk1<7*<648631=i;?>1>954i5`:>5<#;??19::4n247>73<3`>i47>5$246>0133g9=87<9;:k7f3<72-9=97;84:l021<5?21b8o;50;&020<2?=1e?;:52998m1d3290/?;;55668j6032;307d:m3;29 6022<=?7c=94;0b?>o3j;0;6)=95;740>h4>=09n65f4c394?"4><0>;95a37696f=<a=h;6=4+3779122<f:<?6?j4;h6bb?6=,:<>689;;o150?4b32c?mh4?:%151?30<2d8:94=f:9j0db=83.8:84:759m732=;910e8=j:18'733==>>0b>8;:238?l34l3:1(>8::457?k51<39976g:3b83>!51=3?<86`<65807>=n=:h1<7*<648631=i;?>1?954i41b>5<#;??19::4n247>63<3`?857>5$246>0133g9=87=9;:k67=<72-9=97;84:l021<4?21b9>950;&020<2?=1e?;:53998m051290/?;;55668j6032:307d;<5;29 6022<=?7c=94;1b?>o2;:0;6)=95;740>h4>=08n65f52094?"4><0>;95a37697f=<a<9:6=4+3779122<f:<?6>j4;h704?6=,:<>689;;o150?5b32c>>k4?:%151?30<2d8:94<f:9j17c=83.8:84:759m732=<910e8<k:18'733==>>0b>8;:538?l35k3:1(>8::457?k51<3>976g:2c83>!51=3?<86`<65877>=n=;k1<7*<648631=i;?>18954i40;>5<#;??19::4n247>13<3`?9;7>5$246>0133g9=87:9;:k663<72-9=97;84:l021<3?21b9?;50;&020<2?=1e?;:54998m043290/?;;55668j6032=307d;=3;29 6022<=?7c=94;6b?>o2:;0;6)=95;740>h4>=0?n65f53394?"4><0>;95a37690f=<a<8;6=4+3779122<f:<?69j4;h72b?6=,:<>689;;o150?2b32c>=i4?:%151?30<2d8:94;f:9j14e=83.8:84:759m732==910e8?m:18'733==>>0b>8;:438?l36i3:1(>8::457?k51<3?976g:1883>!51=3?<86`<65867>=n=821<7*<648631=i;?>19954i434>5<#;??19::4n247>03<3`?::7>5$246>0133g9=87;9;:k650<72-9=97;84:l021<2?21b9<:50;&020<2?=1e?;:55998m075290/?;;55668j6032<307d;>1;29 6022<=?7c=94;7b?>o2990;6)=95;740>h4>=0>n65f51d94?"4><0>;95a37691f=<a<:n6=4+3779122<f:<?68j4;h73`?6=,:<>689;;o150?3b32c><n4?:%151?30<2d8:94:f:9j15d=83.8:84:759m732=>910e8>n:18'733==>>0b>8;:738?l3713:1(>8::457?k51<3<976g:0683>!51=3?<86`<65857>=n=9<1<7*<648631=i;?>1:954i426>5<#;??19::4n247>33<3`?;87>5$246>0133g9=8789;:k646<72-9=97;84:l021<1?21b9=<50;&020<2?=1e?;:56998m066290/?;;55668j6032?307d;?0;29 6022<=?7c=94;4b?>o3no0;6)=95;740>h4>=0=n65f4gg94?"4><0>;95a37692f=<a=lh6=4+3779122<f:<?6;j4;h6ef?6=,:<>689;;o150?0b32c?jl4?:%151?30<2d8:949f:9j0c?=83.8:84:759m732=?910e9h7:18'733==>>0b>8;:638?l2a?3:1(>8::457?k51<3=976g;f783>!51=3?<86`<65847>=n<o?1<7*<648631=i;?>1;954i5d7>5<#;??19::4n247>23<3`>m?7>5$246>0133g9=8799;:k7b4<72-9=97;84:l021<0?21b8k>50;&020<2?=1e?;:57998m1ca290/?;;55668j6032>307d:je;29 6022<=?7c=94;5b?>o3mm0;6)=95;740>h4>=0<n65f4da94?"4><0>;95a37693f=<a=oi6=4+3779122<f:<?6:j4;h6fe?6=,:<>689;;o150?1b32c?i44?:%151?30<2d8:948f:9j0`>=83.8:84:759m732=0910e9k9:18'733==>>0b>8;:938?l2b=3:1(>8::457?k51<32976g;e583>!51=3?<86`<658;7>=n<l91<7*<648631=i;?>14954i5g1>5<#;??19::4n247>=3<3`>o47>5$246>0133g9=8769;:k7ga<72-9=97;84:l021<??21b8n<50;&020<2?=1e?;:58998m1d0290/?;;55668j60321307d:nc;29 6022<=?7c=94;:b?>o2;=0;6)=95;740>h4>=03n65f53;94?"4><0>;95a3769<f=<a<;n6=4+3779122<f:<?65j4;h727?6=,:<>689;;o150?>b32c><54?:%151?30<2d8:947f:9j0cb=83.8:84:759m732=1910e9h=:18'733==>>0b>8;:838?l2b?3:1(>8::457?k51<33976g;ac83>!51=3?<86`<658:7>=n<hk1<7*<648631=i;?>15954i60:>5<<j=<96=4>:183M2192.8m>4;639l734=831vn<6?:182>5<7sA>==6*<a282<5=h9>l1<75rb`g94?7103<j6<79{I655>\fn3;=w?652681=?4a2;k1>o4=c;c9=?572:;157<8:3:96<<5i38i6?m52g8b>66=;80v(>o<:616?!d12>987)li:617?!52l39==6g81383>!51=3=:?6`<6583?>o0980;6)=95;527>h4>=0:76g81183>!51=3=:?6`<6581?>o08o0;6)=95;527>h4>=0876g80483>>o0;90;66g83683>>i0;h0;66g80e83>!51=3=;i6`<6583?>o08j0;6)=95;53a>h4>=0:76g80c83>!51=3=;i6`<6581?>o08h0;6)=95;53a>h4>=0876g82g83>>i0810;66g81683>!51=3=:46`<6583?>o09?0;6)=95;52<>h4>=0:76g81483>!51=3=:46`<6581?>o09=0;6)=95;52<>h4>=0876a;a183>>i3i>0;6)=95;6b<>h4>=0;76a;a783>!51=3>j46`<6582?>i3i<0;6)=95;6b<>h4>=0976a;a583>!51=3>j46`<6580?>i0900;66g84383>>o09m0;6)=95;52a>h4>=0;76g81b83>!51=3=:i6`<6582?>o09k0;6)=95;52a>h4>=0976g81`83>!51=3=:i6`<6580?>i08:0;66a80083>>o0;j0;66g;a383>>o0:;0;6)=95;517>h4>=0;76g82083>!51=3=9?6`<6582?>o0:90;6)=95;517>h4>=0976g81g83>!51=3=9?6`<6580?>o0:>0;6)=95;51<>h4>=0;76g82783>!51=3=946`<6582?>o0:<0;6)=95;51<>h4>=0976g82583>!51=3=946`<6580?>i31o0;66g80783>>o3i:0;66g84283>>i0;?0;66a83c83>>o0;80;66a90b83>!51=3<2j6`<6583?>i18k0;6)=95;4:b>h4>=0:76a90`83>!51=3<2j6`<6581?>i1800;6)=95;4:b>h4>=0876a90983>!51=3<2j6`<6587?>i18>0;6)=95;4:b>h4>=0>76a90783>!51=3<2j6`<6585?>i18<0;6)=95;4:b>h4>=0<76a90583>!51=3<2j6`<658;?>i18;0;6)=95;4:b>h4>=0276a90083>!51=3<2j6`<658b?>i1890;6)=95;4:b>h4>=0i76a:fg83>!51=3<2j6`<658`?>i2nl0;6)=95;4:b>h4>=0o76a:fe83>!51=3<2j6`<658f?>i2nj0;6)=95;4:b>h4>=0m76a:fc83>!51=3<2j6`<65824>=h=ok1<7*<6485=c=i;?>1=<54o4d:>5<#;??1:4h4n247>44<3f?m;7>5$246>3?a3g9=87?<;:m6b3<72-9=9786f:l021<6<21d9k;50;&020<11o1e?;:51498k0`3290/?;;568d8j60328<07b;i3;29 6022?3m7c=94;34?>i2n;0;6)=95;4:b>h4>=0:465`5g394?"4><0=5k5a37695<=<g<l;6=4+37792<`<f:<?6<o4;n7fb?6=,:<>6;7i;o150?7e32e>ih4?:%151?0>n2d8:94>c:9l1`e=83.8:8499g9m732=9m10c8km:18'733=>0l0b>8;:0g8?j3bi3:1(>8::7;e?k51<3;m76a:e883>!51=3<2j6`<65814>=h=l21<7*<6485=c=i;?>1><54o4g4>5<#;??1:4h4n247>74<3f?n:7>5$246>3?a3g9=87<<;:m6a0<72-9=9786f:l021<5<21d9h:50;&020<11o1e?;:52498k0c4290/?;;568d8j6032;<07b;j1;29 6022?3m7c=94;04?>i2m90;6)=95;4:b>h4>=09465`5ed94?"4><0=5k5a37696<=<g<nn6=4+37792<`<f:<?6?o4;n7g`?6=,:<>6;7i;o150?4e32e>hn4?:%151?0>n2d8:94=c:9l1ad=83.8:8499g9m732=:m10c8jn:18'733=>0l0b>8;:3g8?j3c13:1(>8::7;e?k51<38m76a:d983>!51=3<2j6`<65804>=h>?31<7*<6485=c=i;?>1?<54o74;>5<#;??1:4h4n247>64<3f<=;7>5$246>3?a3g9=87=<;:m523<72-9=9786f:l021<4<21d:;;50;&020<11o1e?;:53498k303290/?;;568d8j6032:<07b893;29 6022?3m7c=94;14?>i1>;0;6)=95;4:b>h4>=08465`67394?"4><0=5k5a37697<=<g?<;6=4+37792<`<f:<?6>o4;n46a?6=,:<>6;7i;o150?5e32e=9i4?:%151?0>n2d8:94<c:9l20e=83.8:8499g9m732=;m10c;;m:18'733=>0l0b>8;:2g8?j02i3:1(>8::7;e?k51<39m76a95883>!51=3<2j6`<65874>=h><21<7*<6485=c=i;?>18<54o774>5<#;??1:4h4n247>14<3f<>:7>5$246>3?a3g9=87:<;:m510<72-9=9786f:l021<3<21d:8=50;&020<11o1e?;:54498k335290/?;;568d8j6032=<07b8:1;29 6022?3m7c=94;64?>i1=90;6)=95;4:b>h4>=0?465`65d94?"4><0=5k5a37690<=<g?>n6=4+37792<`<f:<?69o4;n47`?6=,:<>6;7i;o150?2e32e=8n4?:%151?0>n2d8:94;c:9l21d=83.8:8499g9m732=<m10c;:n:18'733=>0l0b>8;:5g8?j0303:1(>8::7;e?k51<3>m76a94683>!51=3<2j6`<65864>=h>=<1<7*<6485=c=i;?>19<54o766>5<#;??1:4h4n247>04<3f<?87>5$246>3?a3g9=87;<;:m506<72-9=9786f:l021<2<21d:9<50;&020<11o1e?;:55498k326290/?;;568d8j6032<<07b8;0;29 6022?3m7c=94;74?>i1;o0;6)=95;4:b>h4>=0>465`62f94?"4><0=5k5a37691<=<g?9h6=4+37792<`<f:<?68o4;n40f?6=,:<>6;7i;o150?3e32e=?l4?:%151?0>n2d8:94:c:9l26?=83.8:8499g9m732==m10c;=7:18'733=>0l0b>8;:4g8?j04?3:1(>8::7;e?k51<3?m76a93783>!51=3<2j6`<65854>=h>:?1<7*<6485=c=i;?>1:<54o717>5<#;??1:4h4n247>34<3f<8>7>5$246>3?a3g9=878<;:m574<72-9=9786f:l021<1<21d:>>50;&020<11o1e?;:56498k34a290/?;;568d8j6032?<07b8=e;29 6022?3m7c=94;44?>i1:m0;6)=95;4:b>h4>=0=465`63a94?"4><0=5k5a37692<=<g?8i6=4+37792<`<f:<?6;o4;n41e?6=,:<>6;7i;o150?0e32e=>44?:%151?0>n2d8:949c:9l271=83.8:8499g9m732=>m10c;<9:18'733=>0l0b>8;:7g8?j05=3:1(>8::7;e?k51<3<m76a92583>!51=3<2j6`<65844>=h>;91<7*<6485=c=i;?>1;<54o701>5<#;??1:4h4n247>24<3f<9=7>5$246>3?a3g9=879<;:m565<72-9=9786f:l021<0<21d:<h50;&020<11o1e?;:57498k37b290/?;;568d8j6032><07b8>c;29 6022?3m7c=94;54?>i19k0;6)=95;4:b>h4>=0<465`60c94?"4><0=5k5a37693<=<g?;26=4+37792<`<f:<?6:o4;n42<?6=,:<>6;7i;o150?1e32e==:4?:%151?0>n2d8:948c:9l240=83.8:8499g9m732=?m10c;?::18'733=>0l0b>8;:6g8?j06<3:1(>8::7;e?k51<3=m76a91283>!51=3<2j6`<658;4>=h>8;1<7*<6485=c=i;?>14<54o733>5<#;??1:4h4n247>=4<3f<;j7>5$246>3?a3g9=876<;:m54`<72-9=9786f:l021<?<21d:=j50;&020<11o1e?;:58498k364290/?;;568d8j60321<07b;i8;29 6022?3m7c=94;:4?>i2mm0;6)=95;4:b>h4>=03465`5d094?"4><0=5k5a3769<<=<g<n<6=4+37792<`<f:<?65o4;n46b?6=,:<>6;7i;o150?>e32e=994?:%151?0>n2d8:947c:9l21?=83.8:8499g9m732=0m10c;=j:18'733=>0l0b>8;:9g8?j04;3:1(>8::7;e?k51<32m76a92983>!51=3<2j6`<658:4>=h>8n1<7*<6485=c=i;?>15<54o731>5<#;??1:4h4n247><4<3f?o:7>5$246>3?a3g9=877<;:m6`0<72-9=9786f:l021<><21b8h?50;&020<2?=1e?;:50:9j0`6=83.8:84:759m732=921b8ih50;&020<2?=1e?;:52:9j0ac=83.8:84:759m732=;21b8ij50;&020<2?=1e?;:54:9j0ae=83.8:84:759m732==21b8il50;&020<2?=1e?;:56:9j0ag=83.8:84:759m732=?21b8i750;&020<2?=1e?;:58:9j0a1=83.8:84:759m732=121b8i850;&020<2?=1e?;:5a:9j0a3=83.8:84:759m732=j21b8i:50;&020<2?=1e?;:5c:9j0a5=83.8:84:759m732=l21b8i<50;&020<2?=1e?;:5e:9j0a7=83.8:84:759m732=n21b8i>50;&020<2?=1e?;:51198m1ea290/?;;55668j60328;07d:le;29 6022<=?7c=94;31?>o3kj0;6)=95;740>h4>=0:?65f4b`94?"4><0>;95a376951=<a=ij6=4+3779122<f:<?6<;4;h6`=?6=,:<>689;;o150?7132c?o54?:%151?30<2d8:94>7:9j0f1=83.8:84:759m732=9110e9m9:18'733==>>0b>8;:0;8?l2d=3:1(>8::457?k51<3;j76g;c583>!51=3?<86`<6582f>=n<j91<7*<648631=i;?>1=n54i5a2>5<#;??19::4n247>4b<3`>h<7>5$246>0133g9=87?j;:k7fc<72-9=97;84:l021<6n21b8ok50;&020<2?=1e?;:52198m1dc290/?;;55668j6032;;07d:mc;29 6022<=?7c=94;01?>o3jk0;6)=95;740>h4>=09?65f4cc94?"4><0>;95a376961=<a=h26=4+3779122<f:<?6?;4;h6a<?6=,:<>689;;o150?4132c?n;4?:%151?30<2d8:94=7:9j0g3=83.8:84:759m732=:110e9l;:18'733==>>0b>8;:3;8?l2e;3:1(>8::457?k51<38j76g;b383>!51=3?<86`<6581f>=n<k;1<7*<648631=i;?>1>n54i5`3>5<#;??19::4n247>7b<3`>jj7>5$246>0133g9=87<j;:k7e`<72-9=97;84:l021<5n21b8lj50;&020<2?=1e?;:53198m05b290/?;;55668j6032:;07d;<d;29 6022<=?7c=94;11?>o2;j0;6)=95;740>h4>=08?65f52`94?"4><0>;95a376971=<a<9j6=4+3779122<f:<?6>;4;h70=?6=,:<>689;;o150?5132c>?54?:%151?30<2d8:94<7:9j161=83.8:84:759m732=;110e8=9:18'733==>>0b>8;:2;8?l34=3:1(>8::457?k51<39j76g:3283>!51=3?<86`<6580f>=n=:81<7*<648631=i;?>1?n54i412>5<#;??19::4n247>6b<3`?8<7>5$246>0133g9=87=j;:k66c<72-9=97;84:l021<4n21b9?k50;&020<2?=1e?;:54198m04c290/?;;55668j6032=;07d;=c;29 6022<=?7c=94;61?>o2:k0;6)=95;740>h4>=0??65f53c94?"4><0>;95a376901=<a<836=4+3779122<f:<?69;4;h713?6=,:<>689;;o150?2132c>>;4?:%151?30<2d8:94;7:9j173=83.8:84:759m732=<110e8<;:18'733==>>0b>8;:5;8?l35;3:1(>8::457?k51<3>j76g:2383>!51=3?<86`<6587f>=n=;;1<7*<648631=i;?>18n54i403>5<#;??19::4n247>1b<3`?:j7>5$246>0133g9=87:j;:k65a<72-9=97;84:l021<3n21b9<m50;&020<2?=1e?;:55198m07e290/?;;55668j6032<;07d;>a;29 6022<=?7c=94;71?>o2900;6)=95;740>h4>=0>?65f50:94?"4><0>;95a376911=<a<;<6=4+3779122<f:<?68;4;h722?6=,:<>689;;o150?3132c>=84?:%151?30<2d8:94:7:9j142=83.8:84:759m732==110e8?=:18'733==>>0b>8;:4;8?l3693:1(>8::457?k51<3?j76g:1183>!51=3?<86`<6586f>=n=9l1<7*<648631=i;?>19n54i42f>5<#;??19::4n247>0b<3`?;h7>5$246>0133g9=87;j;:k64f<72-9=97;84:l021<2n21b9=l50;&020<2?=1e?;:56198m06f290/?;;55668j6032?;07d;?9;29 6022<=?7c=94;41?>o28>0;6)=95;740>h4>=0=?65f51494?"4><0>;95a376921=<a<:>6=4+3779122<f:<?6;;4;h730?6=,:<>689;;o150?0132c><>4?:%151?30<2d8:9497:9j154=83.8:84:759m732=>110e8>>:18'733==>>0b>8;:7;8?l3783:1(>8::457?k51<3<j76g;fg83>!51=3?<86`<6585f>=n<oo1<7*<648631=i;?>1:n54i5d`>5<#;??19::4n247>3b<3`>mn7>5$246>0133g9=878j;:k7bd<72-9=97;84:l021<1n21b8k750;&020<2?=1e?;:57198m1`?290/?;;55668j6032>;07d:i7;29 6022<=?7c=94;51?>o3n?0;6)=95;740>h4>=0<?65f4g794?"4><0>;95a376931=<a=l?6=4+3779122<f:<?6:;4;h6e7?6=,:<>689;;o150?1132c?j<4?:%151?30<2d8:9487:9j0c6=83.8:84:759m732=?110e9ki:18'733==>>0b>8;:6;8?l2bm3:1(>8::457?k51<3=j76g;ee83>!51=3?<86`<6584f>=n<li1<7*<648631=i;?>1;n54i5ga>5<#;??19::4n247>2b<3`>nm7>5$246>0133g9=879j;:k7a<<72-9=97;84:l021<0n21b8h650;&020<2?=1e?;:58198m1c1290/?;;55668j60321;07d:j5;29 6022<=?7c=94;:1?>o3m=0;6)=95;740>h4>=03?65f4d194?"4><0>;95a3769<1=<a=o96=4+3779122<f:<?65;4;h6g<?6=,:<>689;;o150?>132c?oi4?:%151?30<2d8:9477:9j0f4=83.8:84:759m732=0110e9l8:18'733==>>0b>8;:9;8?l2fk3:1(>8::457?k51<32j76g:3583>!51=3?<86`<658;f>=n=;31<7*<648631=i;?>14n54i43f>5<#;??19::4n247>=b<3`?:?7>5$246>0133g9=876j;:k64=<72-9=97;84:l021<?n21b8kj50;&020<2?=1e?;:59198m1`5290/?;;55668j60320;07d:j7;29 6022<=?7c=94;;1?>o3ik0;6)=95;740>h4>=02?65f4`c94?"4><0>;95a3769=1=<a=k:6=44o60g>5<#;??1;?k4n247>5=<g>8h6=4+377937c<f:<?6<54o60a>5<#;??1;?k4n247>7=<g>8j6=4+377937c<f:<?6>54o663>5<#;??1;9?4n247>5=<g>9m6=4+3779317<f:<?6<54o61f>5<#;??1;9?4n247>7=<g>9o6=4+3779317<f:<?6>54o62:>5<<a>:?6=44o5c:>5<<a>826=44o61:>5<<j=3?6=4>:183!5f;3;3<6F;929K037<g8=m6=44}c6:1?6=93:1<v*<a28727=O<090D98>;n156?6=3th?<>4?:583>5}#;h91=:l4H5;0?M2192.:5549;h`3>5<<aj;1<75f37594?=h;?21<75rb521>5<3290;w)=n3;34f>N31:1C8;?4$0;;>3=nj90;66gl1;29?l51?3:17b=98;29?xd3::0;694?:1y'7d5=9>h0D97<;I655>"6110=7dl?:188mf7=831b?;950;9l73>=831vn9<=:187>5<7s-9j?7?8b:J7=6=O<?;0(<77:79jf5<722ch=7>5;h153?6=3f9=47>5;|`71=<72:0;6=u+3`1952><@=387E:91:Jb`>"5:<08m?5+18:95>oe83:17dm>:188k60?2900qo::d;297?6=8r.8m>4>799K0<5<@=<:7Eok;%011?5f:2.:554>;h`3>5<<aj;1<75`37:94?=zj=?<6=4<:183!5f;3;<46F;929K037<@hn0(?<::2c1?!7>03;0eo>50;9jg4<722e8:54?::a00e=8391<7>t$2c0>41?3A>2?6F;609Kea=#:;?1?l<4$0;;>4=nj90;66gl1;29?j5103:17pl;5783>0<729q/?l=516a8L1?43A>==6Fnd:&160<4i;1bn=4?::ka1?6=3`i:6=44i244>5<<g:<36=44}c665?6=<3:1<v*<a2823g=O<090D98>;%3:<?0<ak:1<75fc083>>o4>>0;66a<6983>>{e<<:1<7:50;2x 6g428=i7E:63:J724=#9021:6gm0;29?le62900e>88:188k60?2900qo:;f;290?6=8r.8m>4>7c9K0<5<@=<:7)?68;48mg6=831bo<4?::k022<722e8:54?::a00d=83?1<7>t$2c0>41d3A>2?6F;609Kea=#:;?1?l<4ic294?=nj<0;66gl1;29?l51?3:17b=98;29?xd3=<0;694?:1y'7d5=9>h0D97<;I655>"6110=7dl?:188mf7=831b?;950;9l73>=831vn9;;:187>5<7s-9j?7?8b:J7=6=O<?;0(<77:79jf5<722ch=7>5;h153?6=3f9=47>5;|`753<72<0;6=u+3`1952g<@=387E:91:&2==<63`h;6=44ic794?=njm0;66gl1;29?j5103:17pl;1483>0<729q/?l=516c8L1?43A>==6*>9982?ld72900eo;50;9jfa<722ch=7>5;n15<?6=3th?=94?:483>5}#;h91=:o4H5;0?M2192.:554>;h`3>5<<ak?1<75fbe83>>od93:17b=98;29?xd39:0;684?:1y'7d5=9>k0D97<;I655>"6110:7dl?:188mg3=831bni4?::k`5?6=3f9=47>5;|`74`<72<0;6=u+3`1952g<@=387E:91:&2==<63`h;6=44ic794?=njm0;66gl1;29?j5103:17pl;0e83>0<729q/?l=516c8L1?43A>==6*>9982?ld72900eo;50;9jfa<722ch=7>5;n15<?6=3th?<n4?:483>5}#;h91=:o4H5;0?M2192.:554>;h`3>5<<ak?1<75fbe83>>od93:17b=98;29?xd38k0;684?:1y'7d5=9>i0D97<;I655>"6110=7dl?:188mg3=831bo<4?::k022<722e8:54?::a06c=83?1<7>t$2c0>41f3A>2?6F;609'5<>=92ci<7>5;h`6>5<<akn1<75fc083>>i4>10;66sm42f94?3=83:p(>o<:05b?M2>;2B?:<5+18:95>oe83:17dl::188mgb=831bo<4?::m02=<722wi8>m50;794?6|,:k86<9n;I6:7>N3>81/=4651:ka4?6=3`h>6=44icf94?=nk80;66a<6983>>{e<:h1<7;50;2x 6g428=j7E:63:J724=#9021=6gm0;29?ld22900eoj50;9jg4<722e8:54?::a060=83?1<7>t$2c0>41f3A>2?6F;609'5<>=92ci<7>5;h`6>5<<akn1<75fc083>>i4>10;66sm42794?3=83:p(>o<:05b?M2>;2B?:<5+18:95>oe83:17dl::188mgb=831bo<4?::m02=<722wi8>:50;794?6|,:k86<9n;I6:7>N3>81/=4651:ka4?6=3`h>6=44icf94?=nk80;66a<6983>>{e<:91<7;50;2x 6g428=h7E:63:J724=#9021:6gm0;29?ld22900en?50;9j731=831d?;650;9~f14b290>6=4?{%1b7?70i2B?5>5G4738 4??281bn=4?::ka1?6=3`ho6=44ib394?=h;?21<75rb50g>5<2290;w)=n3;34e>N31:1C8;?4$0;;>4=nj90;66gm5;29?ldc2900en?50;9l73>=831vn9<l:186>5<7s-9j?7?8c:J7=6=O<?;0(<77:79jf5<722ci97>5;ha2>5<<a:<<6=44o24;>5<<uk>9n7>55;294~"4i:0:;l5G4818L1063-;247?4ic294?=nj<0;66gmd;29?le62900c>87:188yg5b;3:187>50z&0e6<6?01C84=4H542?!7>03;0eo>50;9jfa<722ch=7>5;n15<?6=3th8i?4?:583>5}#;h91=:74H5;0?M2192.:554>;h`3>5<<akn1<75fc083>>i4>10;66sm3d394?2=83:p(>o<:05:?M2>;2B?:<5+18:95>oe83:17dlk:188mf7=831d?;650;9~f6c7290?6=4?{%1b7?7012B?5>5G4738 4??281bn=4?::ka`?6=3`i:6=44o24;>5<<uk9h=7>54;294~"4i:0:;45G4818L1063-;247?4ic294?=njm0;66gl1;29?j5103:17pl<c183>1<729q/?l=516;8L1?43A>==6*>9982?ld72900eoj50;9jg4<722e8:54?::a7g`=83>1<7>t$2c0>41>3A>2?6F;609'5<>=92ci<7>5;h`g>5<<aj;1<75`37:94?=zj:hn6=4;:183!5f;3;<56F;929K037<,8336<5fb183>>oel3:17dm>:188k60?2900qo=ib;290?6=8r.8m>4>789K0<5<@=<:7)?68;38mg6=831bni4?::k`5?6=3f9=47>5;|`0bd<72=0;6=u+3`1952?<@=387E:91:&2==<63`h;6=44icf94?=nk80;66a<6983>>{e;o31<7:50;2x 6g428=27E:63:J724=#9021=6gm0;29?ldc2900en?50;9l73>=831vn>h7:187>5<7s-9j?7?89:J7=6=O<?;0(<77:09jf5<722cih7>5;ha2>5<<g:<36=44}c1g=?6=<3:1<v*<a2823<=O<090D98>;%3:<?7<ak:1<75fbe83>>od93:17b=98;29?xd4l10;694?:1y'7d5=9>30D97<;I655>"6110:7dl?:188mgb=831bo<4?::m02=<722wi?i950;694?6|,:k86<96;I6:7>N3>81/=4651:ka4?6=3`ho6=44ib394?=h;?21<75rb2f5>5<3290;w)=n3;34=>N31:1C8;?4$0;;>4=nj90;66gmd;29?le62900c>87:188yg5a;3:187>50z&0e6<6?01C84=4H542?Mgc3-8997=n2:&2==<63`h;6=44icf94?=nk80;66a<6983>>{e;o81<7:50;2x 6g428=27E:63:J724=Oim1/>?;53`08 4??281bn=4?::ka`?6=3`i:6=44o24;>5<<uk9m=7>54;294~"4i:0:;45G4818L1063Ako7)<=5;1b6>"6110:7dl?:188mgb=831bo<4?::m02=<722wi?k>50;694?6|,:k86<96;I6:7>N3>81Cmi5+23797d4<,8336<5fb183>>oel3:17dm>:188k60?2900qo=k1;290?6=8r.8m>4>789K0<5<@=<:7Eok;%011?5f:2.:554>;h`3>5<<akn1<75fc083>>i4>10;66sm3e294?2=83:p(>o<:05:?M2>;2B?:<5Gae9'673=;h80(<77:09jf5<722cih7>5;ha2>5<<g:<36=44}c1`b?6=<3:1<v*<a2823<=O<090D98>;Icg?!45=39j>6*>9982?ld72900eoj50;9jg4<722e8:54?::a7fc=83>1<7>t$2c0>41>3A>2?6F;609Kea=#:;?1?l<4$0;;>4=nj90;66gmd;29?le62900c>87:188yg5d13:187>50z&0e6<6?01C84=4H542?!7>03;0eo>50;9jfa<722ch=7>5;n15<?6=3th8o54?:583>5}#;h91=:74H5;0?M2192.:554>;h`3>5<<akn1<75fc083>>i4>10;66sm3b594?2=83:p(>o<:05:?M2>;2B?:<5+18:95>oe83:17dlk:188mf7=831d?;650;9~f6e1290?6=4?{%1b7?7012B?5>5G4738 4??281bn=4?::ka`?6=3`i:6=44o24;>5<<uk9nn7>54;294~"4i:0:;45G4818L1063-;247?4ic294?=njm0;66gl1;29?j5103:17pl<e`83>1<729q/?l=516;8L1?43A>==6*>9982?ld72900eoj50;9jg4<722e8:54?::a7`?=83>1<7>t$2c0>41>3A>2?6F;609'5<>=92ci<7>5;h`g>5<<aj;1<75`37:94?=zj:o36=4;:183!5f;3;<56F;929K037<,8336<5fb183>>oel3:17dm>:188k60?2900qo:?4;297?6=8r.8m>4=209K0<5<@=<:7)?68;34?l7?:3:17d?73;29?j5183:17pl;2583>6<729q/?l=52338L1?43A>==6*>99823>o60;0;66g>8283>>i4>90;66sm45;94?2=83:p(>o<:301?M2>;2B?:<5+18:9520<a8296=44i0:0>5<<a82?6=44o243>5<<uk>>m7>53;294~"4i:09><5G4818L1063-;247?8;h3;6?6=3`;3?7>5;n154?6=3th?9k4?:283>5}#;h91>??4H5;0?M2192.:554>7:k2<7<722c:4>4?::m025<722wi8<o50;694?6|,:k86?<=;I6:7>N3>81/=465359'730=<0h0e<6=:188m4>42900e<6;:188k6072900qo:>c;291?6=8r.8m>4=229K0<5<@=<:7)?68;16?!51>3>2n6g>8383>>o60:0;66g>8583>>o60<0;66a<6183>>{e<9<1<7=50;2x 6g42;8:7E:63:J724=#9021??5f19094?=n9191<75`37294?=zj=>96=4;:183!5f;389>6F;929K037<,8336>:4$245>1?d3`;3>7>5;h3;7?6=3`;387>5;n154?6=3th?894?:483>5}#;h91>?=4H5;0?M2192.:554<5:&023<31j1b=5<50;9j5=5=831b=5:50;9j5=3=831d?;>50;9~f14129086=4?{%1b7?4592B?5>5G4738 4??2:80e<6=:188m4>42900c>8?:188yg5e>3:1?7>50z&0e6<5:81C84=4H542?!7>03997)=96;6:`>o60;0;66g>8283>>i4>90;66sm3c:94?2=83:p(>o<:301?M2>;2B?:<5+18:97`=#;?<184j4i0:1>5<<a8286=44i0:7>5<<g:<;6=44}c1ba?6=;3:1<v*<a28164=O<090D98>;%3:<?553-9=:7:6e:k2<7<722c:4>4?::m025<722wi?o>50;694?6|,:k86?<=;I6:7>N3>81/=4653d9'730=<0o0e<6=:188m4>42900e<6;:188k6072900qo=n4;297?6=8r.8m>4=209K0<5<@=<:7)?68;11?l7?:3:17d?73;29?j5183:17pl<a683>6<729q/?l=52338L1?43A>==6*>99806>o60;0;66g>8283>>i4>90;66sm3`794?5=83:p(>o<:302?M2>;2B?:<5+18:977=n9181<75f19194?=h;?:1<75rb2c5>5<4290;w)=n3;015>N31:1C8;?4$0;;>64<a8296=44i0:0>5<<g:<;6=44}c1b<?6=;3:1<v*<a28164=O<090D98>;%3:<?553`;3>7>5;h3;7?6=3f9=<7>5;|`0e<<72:0;6=u+3`19677<@=387E:91:&2==<4:2c:4?4?::k2<6<722e8:=4?::a7ad=83?1<7>t$2c0>7443A>2?6F;609'5<>=;:1b=5<50;9j5=5=831b=5:50;9j5=3=831d?;>50;9~f6bf290>6=4?{%1b7?45;2B?5>5G4738 4??2:90e<6=:188m4>42900e<6;:188m4>22900c>8?:188yg2593:1;7>50z&0e6<5:=1C84=4H542?!7>03927d?72;29?l7?;3:17d?74;29?l7?=3:17d?76;29?l7??3:17b=90;29?xd3890;684?:1y'7d5=:;90D97<;I655>"61108j6g>8383>>o60:0;66g>8583>>o60<0;66a<6183>>{e;ol1<7950;2x 6g42;8?7E:63:J724=#9021?55f19094?=n9191<75f19694?=n91?1<75f19494?=n91=1<75`37294?=zj=::6=48:183!5f;38986F;929K037<,8336>64i0:1>5<<a8286=44i0:7>5<<a82>6=44i0:5>5<<a82<6=44o243>5<<uk9mh7>55;294~"4i:09>>5G4818L1063-;247=i;h3;6?6=3`;3?7>5;h3;0?6=3`;397>5;n154?6=3th?=k4?:683>5}#;h91>?:4H5;0?M2192.:554<6:k2<7<722c:4>4?::k2<1<722c:484?::k2<3<722c:4:4?::m025<722wi?kk50;594?6|,:k86?<;;I6:7>N3>81/=46516f8m4>52900e<6<:188m4>32900e<6::188m4>12900e<68:188k6072900qo:=0;293?6=8r.8m>4=259K0<5<@=<:7)?68;34a>o60;0;66g>8283>>o60=0;66g>8483>>o60?0;66g>8683>>i4>90;66sm40g94?1=83:p(>o<:307?M2>;2B?:<5+18:91>o60;0;66g>8283>>o60=0;66g>8483>>o60?0;66g>8683>>i4>90;66sm41794?4=83:p(>o<:33f?M2>;2B?:<5f19394?=h;?:1<75rb506>5<5290;w)=n3;02a>N31:1C8;?4i0:2>5<<g:<;6=44}c671?6=090;6=u+3`1973?<@=387E:91:Xbb?c|j3;36<75c;30>42=9h0:n7?::0495f<6l38?6>o5}o301?6<f8?36=5+38c9521<,:k;6?5+19:90>"6000?7)?7a;68 4>e2=1/=5m54:&2<a<33-;3i7:4$0:e>1=#903186*>9`87?!7>j3>0(<7l:59'5<b=<2.:5h4;;%3:b?2<,8k;695+1`390>"6i;0?7)?n3;68 4g32=1/=l;54:&2e3<33-;j;7:4$0c;>1=#9h3186*>a`87?!7fj3>0(<ol:59'5db=<2.:mh4;;%3bb?2<,8h;695+1c390>"6j;0?7)?m3;68 4d32=1/=o;54:&2f3<33-;i;7:4$0`;>1=#9k3186*>b`87?!7ej3>0(<ll:59'5gb=<2.:nh4;;%3ab?2<,8i;695+1b390>"6k;0?7)?l3;68 4e32=1/=n;54:&2g3<33-;h;7:4$0a;>1=#9j3186*>c`87?!7dj3>0(<ml:59'5fb=<2.:oh4;;%3`b?2<,8n;695+1e390>"6l;0?7)?k3;68 4b32=1/=i;54:&2`3<33-;o;7:4$0f;>1=#:8h1?8h4$24g>6?d3g9<h7<;;o14a?6<,:336>9i;%1:=?50n2.85i4nc:&15<<53-8:m7<4$5:f>61d3->3j7=8c:l7=5<73g>2=7<;;%1b5?4<ak=1<75fb`83>>o6>l0;66g>7083>>o4090;66g<8283>>o40?0;6E=6e:9j7=?=83B85h54i2:`>5<<a:2m6=44i2;1>5<<a:3>6=44i5794?"4><0?86`<6583?>o3;3:1(>8::568j6032810e9<50;&020<3<2d8:94=;:k75?6=,:<>69:4n247>6=<a<;1<7*<64870>h4>=0?76g:0;29 6022=>0b>8;:498m1`=83.8:84;4:l021<132c?i7>5$246>12<f:<?6:54i5f94?"4><0?86`<658;?>o3k3:1(>8::568j6032010e9l50;&020<3<2d8:94n;:k7e?6=,:<>69:4n247>g=<a=31<7*<64870>h4>=0h76g;0;29 6022=>0b>8;:e98m23=83.8:8484:l021<73A92i65f7283>!51=3=?7c=94;38L6?b32c<47>5$246>21<f:<?6=5G38g8?l11290/?;;5769m732=92B85h54i6g94?"4><0<h6`<6583?>o0k3:1(>8::6f8j6032810e:l50;&020<0l2d8:94=;:k4e?6=,:<>6:j4n247>6=<a1k1<7*<6484`>h4>=0?76g79;29 6022>n0b>8;:498m=>=83.8:848d:l021<132c3;7>5$246>2b<f:<?6:54i9494?"4><0<h6`<658;?>o?=3:1(>8::6f8j6032010e5:50;&020<0l2d8:94n;:k;7?6=,:<>6:j4n247>g=<a181<7*<6484`>h4>=0h76g89;29 6022>n0b>8;:e98mfg=83.8:84l9:l021<732ch47>5$246>f?<f:<?6<54ib594?"4><0h56`<6581?>od>3:1(>8::b;8j6032:10en;50;&020<d12d8:94;;:k`0?6=,:<>6n74n247>0=<al>1<7*<648`=>h4>=0=76gj3;29 6022j30b>8;:698m`4=83.8:84l9:l021<?32cn=7>5$246>f?<f:<?6454id294?"4><0h56`<658b?>ocn3:1(>8::b;8j6032k10eik50;&020<d12d8:94l;:kge?6=,:<>6n74n247>a=<ajl1<7*<648`=>h4>=0n76gl3;29 6022j30b>8;:g98m`e=83.8:84jb:l021<732cnm7>5$246>`d<f:<?6<54id;94?"4><0nn6`<6581?>ob03:1(>8::d`8j6032:10eh950;&020<bj2d8:94;;:kf2?6=,:<>6hl4n247>0=<a8:=6=4+3779ag=i;?>1:65f11794?"4><0nn6`<6584?>o68=0;6)=95;ga?k51<3207d??3;29 6022lh0b>8;:898m465290/?;;5ec9m732=i21b==?50;&020<bj2d8:94m;:k245<72-9=97km;o150?e<3`lh6=4+3779ag=i;?>1h65ff083>!51=3oi7c=94;g8?lc2290/?;;5ec9m732=n21b==750;&020<6811e?;:50:9j551=83.8:84>099m732=921b==h50;&020<68l1e?;:50:9j55b=83.8:84>0d9m732=921d=<o50;&020<6901e?;:50:9l54>=83.8:84>189m732=921d=<950;&020<6901e?;:52:9l540=83.8:84>189m732=;21d=<;50;&020<6901e?;:54:9l542=83.8:84>189m732==21d=>:50;&020<6901e?;:56:9l565=83.8:84>189m732=?21d=><50;&020<6901e?;:58:9l567=83.8:84>189m732=121d=>>50;&020<6901e?;:5a:9l57`=83.8:84>189m732=j21d=?k50;&020<6901e?;:5c:9l57g=83.8:84>189m732=l21d=<h50;&020<6901e?;:5e:9l545=83.8:84>189m732=n21d=>j50;&020<6;j1e?;:50:9l56d=83.8:84>3b9m732=921d=>o50;&020<6;j1e?;:52:9l56?=83.8:84>3b9m732=;21d=>650;&020<6;j1e?;:54:9l561=83.8:84>3b9m732==21d=8950;&020<6;j1e?;:56:9l500=83.8:84>3b9m732=?21d=8;50;&020<6;j1e?;:58:9l502=83.8:84>3b9m732=121d=8=50;&020<6;j1e?;:5a:9l504=83.8:84>3b9m732=j21d=8?50;&020<6;j1e?;:5c:9l51b=83.8:84>3b9m732=l21d=9<50;&020<6;j1e?;:5e:9l560=83.8:84>3b9m732=n21d=8l50;&020<6=h1e?;:50:9l50?=83.8:84>5`9m732=921d=;?50;&020<6>91e?;:50:9l50`=83.8:84>619m732=921b8;650;&020<3>>1e?;:50:J0=`=<a=<=6=4+3779031<f:<?6<5G38g8?l21=3:1(>8::544?k51<3807d:94;29 6022=<<7c=94;18?l20j3:1(>8::55b?k51<3:0D>7j;:k73<<72-9=97:8a:l021<63A92i65f46:94?"4><0?;l5a37696>N41l10e998:18'733=<>k0b>8;:29K7<c<3`><:7>5$246>11f3g9=87:4;h641?6=,:<>699n;o150?3<3`><87>5$246>11f3g9=8784;h647?6=,:<>699n;o150?1<3th?8;4?:072>5<7s-9j?7=9a:J7=6=O<?;0Vlh517ye>46=l3;:6<<5e;3f>4`=:;09?7<?:3396a<5m39o654=4;06>70=;h08n7=l:|l270<73g;>47>4$057>4103-;<97?87:&0=d<6?>1/?l>53:&2<=<33-;357:4$0:b>1=#91h186*>8b87?!7?l3>0(<6j:59'5=`=<2.:5=4;;%3:5?2<,839695+18190>"61=0?7)?65;68 4?12=1/=4954:&2=<<33-;2m7:4$0;a>1=#90i186*>9e87?!7>m3>0(<7i:59'5d6=<2.:m<4;;%3b6?2<,8k8695+1`690>"6i<0?7)?n6;68 4g02=1/=l654:&2e<<33-;jm7:4$0ca>1=#9hi186*>ae87?!7fm3>0(<oi:59'5g6=<2.:n<4;;%3a6?2<,8h8695+1c690>"6j<0?7)?m6;68 4d02=1/=o654:&2f<<33-;im7:4$0`a>1=#9ki186*>be87?!7em3>0(<li:59'5f6=<2.:o<4;;%3`6?2<,8i8695+1b690>"6k<0?7)?l6;68 4e02=1/=n654:&2g<<33-;hm7:4$0aa>1=#9ji186*>ce87?!7dm3>0(<mi:59'5a6=<2.:h<4;;%3g6?2<,8n8695+1e690>"6l<0?7)?k6;68 4b02=1/=i654:&2`<<33-;om7:4$0fa>1=#9mi186*>de87?!7cm3>0(<ji:59'5`6=<2.:i<4;;%3f6?2<,8o8695+1d690>"6m<0?7)?j6;68 4c02=1/=h654:&2a<<33-;nm7:4$0ga>1=#9li186*>ee87?!7bm3>0(<ki:59'5c6=<2.:j<4;;%3e6?2<,8l8695+1g690>"6n<0?7)?i6;68 4`02=1/=k654:&2b<<33-;mm7:4$0da>1=#9oi186*>fe87?!7am3>0(<hi:59'656=<2.9<<4;;%036?2<,;:8695+21690>"58<0?7)<?6;68 7602=1/>=654:&14<<33-8;m7:4$32a>1=#:9i186*=0e87?!47m3>0(?>i:59'646=<2.9=<4;;%026?2<,;;8695+20690>"59<0?7)<>6;68 7702=1/><654:&15g<4=o1/?;l534d8 60d2:?m7)=9d;1:g>h4?m0?46`<7d83?!5>039<j6*<98803c=#;0n1mn5+20;97>"59h087):7e;14g>"30o08;n5a48294>h3180?46*<a080?ld62900eo<50;9lf6<722ei87>5;h`4>5<<ak21<7F<9d98mg?=83B85h54icc94?=njk0;6E=6e:9jff<72A92i65`c383>>o6>l0;66g>6g83>M5>m21b=:>50;J0=`=<a8=:6=44i051>5<O;0o07d?83;29L6?b32c9=n4?::k15a<722c84=4?::k0<4<72A92i65f39094?N41l10e>6<:188m6>3290C?4k4;h1;1?6=@:3n76g<8683>M5>m21b?5650;J0=`=<a:2j6=4G38g8?l5?j3:1D>7j;:k0<f<722c84i4?:I1:a>=n;1o1<7F<9d98m6>a2900e>7?:18K7<c<3`92=7>5H2;f?>o41;0;66g<9283>M5>m21b?4:50;J0=`=<a:3>6=44i2;5>5<O;0o07d=67;29L6?b32e85o4?::k7<?6=,:<>6994n247>5=<a=<1<7*<64873>h4>=0:76g;5;29 6022==0b>8;:398m15=83.8:84;7:l021<432c?>7>5$246>11<f:<?6954i5394?"4><0?;6`<6586?>o293:1(>8::558j6032?10e8>50;&020<3?2d8:948;:k7b?6=,:<>6994n247>==<a=o1<7*<64873>h4>=0276g;d;29 6022==0b>8;:`98m1e=83.8:84;7:l021<e32c?n7>5$246>11<f:<?6n54i5c94?"4><0?;6`<658g?>o313:1(>8::558j6032l10e9>50;&020<3?2d8:94i;:k6=?6=,:<>6864n247>5=O;0o07d;8:18'733==11e?;:51:J0=`=<a<<1<7*<6486<>h4>=097E=6e:9j10<72-9=97;7;o150?5<@:3n76g:4;29 6022<20b>8;:59K7<c<3`?86=4+37791==i;?>196F<9d98m34=83.8:84:8:l021<13A92i65f6083>!51=3?37c=94;58L6?b32c=<7>5$246>0><f:<?655G38g8?l3a290/?;;5599m732=12B85h54i4g94?"4><0>46`<658b?M5>m21b9i4?:%151?3?3g9=87l4H2;f?>o2k3:1(>8::4:8j6032j1C?4k4;h7a>5<#;??1955a3769`>N41l10e8o50;&020<202d8:94j;I1:a>=n=;0;6)=95;7;?k51<3l0D>7j;:k5=?6=,:<>6;64n247>5=O;0o07d88:18'733=>11e?;:51:J0=`=<a?<1<7*<6485<>h4>=097E=6e:9j20<72-9=9787;o150?5<@:3n76g94;29 6022?20b>8;:59K7<c<3`=96=4+37792==i;?>196F<9d98m27=83.8:8498:l021<13A92i65f7183>!51=3<37c=94;58L6?b32c=j7>5$246>3><f:<?655G38g8?l0b290/?;;5699m732=12B85h54i7f94?"4><0=46`<658b?M5>m21b:n4?:%151?0?3g9=87l4H2;f?>o1j3:1(>8::7:8j6032j1C?4k4;h4b>5<#;??1:55a3769`>N41l10e;=50;&020<102d8:94j;I1:a>=n080;6)=95;:3?k51<3:07d9i:18'733=091e?;:51:9j3`<72-9=976?;o150?4<3`=h6=4+3779<5=i;?>1?65f7c83>!51=32;7c=94;68?l1f290/?;;5819m732==21b4l4?:%151?>73g9=8784;h::>5<#;??14=5a37693>=n010;6)=95;:3?k51<3207d68:18'733=091e?;:59:9j<3<72-9=976?;o150?g<3`2>6=4+3779<5=i;?>1n65f8583>!51=32;7c=94;a8?l>4290/?;;5819m732=l21b4?4?:%151?>73g9=87k4;h5:>5<#;??14=5a3769b>=n1;0;6)=95;;2?k51<3:0D>7j;:k:4?6=,:<>64?4n247>4=O;0o07d6i:18'733=181e?;:52:J0=`=<a1o1<7*<648:5>h4>=087E=6e:9j<a<72-9=977>;o150?2<@:3n76g7c;29 60220;0b>8;:49K7<c<3`3i6=4+3779=4=i;?>1:6F<9d98m<g=83.8:8461:l021<03A92i65f9883>!51=33:7c=94;:8L6?b32c247>5$246><7<f:<?645G38g8?l?0290/?;;5909m732=i2B85h54i8494?"4><02=6`<658a?M5>m21b584?:%151??63g9=87m4H2;f?>o><3:1(>8::838j6032m1C?4k4;h;0>5<#;??15<5a3769a>N41l10e5l50;&020<>92d8:94i;I1:a>=ni;0;6)=95;c2?k51<3:0D>7j;:kb4?6=,:<>6l?4n247>4=O;0o07d7i:18'733=i81e?;:52:J0=`=<a0o1<7*<648b5>h4>=087E=6e:9j=a<72-9=97o>;o150?2<@:3n76gnb;29 6022h;0b>8;:49K7<c<3`kj6=4+3779e4=i;?>1:6F<9d98md?=83.8:84n1:l021<03A92i65fa983>!51=3k:7c=94;:8L6?b32cj;7>5$246>d7<f:<?645G38g8?lg1290/?;;5a09m732=i2B85h54i`794?"4><0j=6`<658a?M5>m21bm94?:%151?g63g9=87m4H2;f?>of;3:1(>8::`38j6032m1C?4k4;h;`>5<#;??1m<5a3769a>N41l10eij50;&020<ck2d8:94?;:kgf?6=,:<>6im4n247>4=<am31<7*<648gg>h4>=0976gk8;29 6022mi0b>8;:298ma1=83.8:84kc:l021<332co:7>5$246>ae<f:<?6854ie794?"4><0oo6`<6585?>oc<3:1(>8::ea8j6032>10ei=50;&020<ck2d8:947;:kg6?6=,:<>6im4n247><=<am;1<7*<648gg>h4>=0j76gk0;29 6022mi0b>8;:c98mfc=83.8:84kc:l021<d32chh7>5$246>ae<f:<?6i54iba94?"4><0oo6`<658f?>odj3:1(>8::ea8j6032o10eno50;&020<ck2d8:94>0:9jg=<72-9=97jl;o150?7632ch;7>5$246>ae<f:<?6<<4;ha5>5<#;??1hn5a376956=<aj?1<7*<648gg>h4>=0:865fc583>!51=3nh7c=94;36?>ob<3:1(>8::ea8j60328<07dk<:18'733=lj1e?;:51698m`4=83.8:84kc:l021<6021bi<4?:%151?bd3g9=87?6;:kf4?6=,:<>6im4n247>4g<3`nm6=4+3779`f=i;?>1=o54ieg94?"4><0oo6`<6582g>=nlh0;6)=95;f`?k51<3;o76glf;29 6022mi0b>8;:0g8?le4290/?;;5db9m732=9o10ekh50;&020<am2d8:94?;:ke`?6=,:<>6kk4n247>4=<aoh1<7*<648ea>h4>=0976gia;29 6022oo0b>8;:298mc?=83.8:84ie:l021<332cm47>5$246>cc<f:<?6854ig594?"4><0mi6`<6585?>oa>3:1(>8::gg8j6032>10ek;50;&020<am2d8:947;:ke0?6=,:<>6kk4n247><=<ao91<7*<648ea>h4>=0j76gi2;29 6022oo0b>8;:c98mc6=83.8:84ie:l021<d32cnj7>5$246>cc<f:<?6i54idg94?"4><0mi6`<658f?>obl3:1(>8::gg8j6032o10ehm50;&020<am2d8:94>0:9jad<72-9=97hj;o150?7632cn57>5$246>cc<f:<?6<<4;hg;>5<#;??1jh5a376956=<al=1<7*<648ea>h4>=0:865fe783>!51=3ln7c=94;36?>o68?0;6)=95;df?k51<3;=76g>0483>!51=3ln7c=94;34?>o68=0;6)=95;df?k51<3;376g>0283>!51=3ln7c=94;3:?>o68;0;6)=95;df?k51<3;j76g>0083>!51=3ln7c=94;3a?>o6890;6)=95;df?k51<3;h76gic;29 6022oo0b>8;:0f8?l`6290/?;;5fd9m732=9l10eh;50;&020<am2d8:94>f:9j55e=83.8:84>0c9m732=821b==o50;&020<68k1e?;:51:9j55?=83.8:84>0c9m732=:21b==950;&020<68k1e?;:53:9j544=83.8:84>109m732=821b=<>50;&020<6981e?;:51:9j55`=83.8:84>109m732=:21b==j50;&020<6981e?;:53:9l57b=83.8:84>2b9m732=821d=?l50;&020<6:j1e?;:51:9l57?=83.8:84>2b9m732=:21d=?650;&020<6:j1e?;:53:9l571=83.8:84>2b9m732=<21d=?850;&020<6:j1e?;:55:9l573=83.8:84>2b9m732=>21d=?:50;&020<6:j1e?;:57:9l575=83.8:84>2b9m732=021d=?<50;&020<6:j1e?;:59:9l577=83.8:84>2b9m732=i21d=?>50;&020<6:j1e?;:5b:9l54c=83.8:84>2b9m732=k21d=<j50;&020<6:j1e?;:5d:9l54e=83.8:84>2b9m732=m21d=<l50;&020<6:j1e?;:5f:9l54g=83.8:84>2b9m732=9910c<?7:18'733=9;i0b>8;:038?j76?3:1(>8::00`?k51<3;976a>1783>!51=3;9o6`<65827>=h98?1<7*<64826f=i;?>1=954o037>5<#;??1=?m4n247>43<3f;887>5$246>44d3g9=87?9;:m276<72-9=97?=c:l021<6?21d=><50;&020<6:j1e?;:51998k456290/?;;513a8j60328307b?<0;29 602288h7c=94;3b?>i6:o0;6)=95;31g>h4>=0:n65`13g94?"4><0:>n5a37695f=<g88j6=4+377957e<f:<?6<j4;n32b?6=,:<>6<<l;o150?7b32e:=>4?:%151?75k2d8:94>f:9l506=83.8:84>4g9m732=821d=9k50;&020<6<o1e?;:51:9l51e=83.8:84>4g9m732=:21d=9l50;&020<6<o1e?;:53:9l51g=83.8:84>4g9m732=<21d=9750;&020<6<o1e?;:55:9l51>=83.8:84>4g9m732=>21d=9950;&020<6<o1e?;:57:9l510=83.8:84>4g9m732=021d=9;50;&020<6<o1e?;:59:9l512=83.8:84>4g9m732=i21d=9=50;&020<6<o1e?;:5b:9l517=83.8:84>4g9m732=k21d=9>50;&020<6<o1e?;:5d:9l56`=83.8:84>4g9m732=m21d=>k50;&020<6<o1e?;:5f:9l56b=83.8:84>4g9m732=9910c<=m:18'733=9=l0b>8;:038?j74i3:1(>8::06e?k51<3;976a>3883>!51=3;?j6`<65827>=h9:21<7*<64820c=i;?>1=954o014>5<#;??1=9h4n247>43<3f;>;7>5$246>42a3g9=87?9;:m213<72-9=97?;f:l021<6?21d=8;50;&020<6<o1e?;:51998k433290/?;;515d8j60328307b?:3;29 60228>m7c=94;3b?>i6=;0;6)=95;37b>h4>=0:n65`14394?"4><0:8k5a37695f=<g8>o6=4+377951`<f:<?6<j4;n376?6=,:<>6<:i;o150?7b32e:?;4?:%151?73n2d8:94>f:9l50c=83.8:84>5e9m732=821d=8m50;&020<6=m1e?;:51:9l50d=83.8:84>5e9m732=:21d=8750;&020<6=m1e?;:53:9l532=83.8:84>629m732=821d=;<50;&020<6>:1e?;:51:9l537=83.8:84>629m732=:21d=8h50;&020<6>:1e?;:53:9l53b=83.8:84>6b9m732=821d=;l50;&020<6>j1e?;:51:9l53g=83.8:84>6b9m732=:21d=;750;&020<6>j1e?;:53:9l53>=83.8:84>6b9m732=<21d=;950;&020<6>j1e?;:55:9l530=83.8:84>6b9m732=>21d=;;50;&020<6>j1e?;:57:9l724=83.8:84<709m732=82B85h54o253>5<#;??1?:?4n247>4=O;0o07b=9f;29 6022:=:7c=94;08L6?b32e8;o4?:%151?5092d8:94<;I1:a>=h;>k1<7*<648034=i;?>1865`36;94?"4><08;<5a37691>=h;>21<7*<648034=i;?>1:65`36594?"4><08;<5a37693>=h;><1<7*<648034=i;?>1465`36794?"4><08;<5a3769=>=h;>>1<7*<648034=i;?>1m65`36194?"4><08;<5a3769f>=h;?o1<7*<648034=i;?>1o65f47:94?"4><0?::5a37694>=n<?<1<7*<648722=i;?>1=65f47794?"4><0?::5a37696>=n<?>1<7*<648722=i;?>1?65f47f94?"4><0?:n5a37694>N41l10e98m:18'733=<?i0b>8;:09K7<c<3`>=m7>5$246>10d3g9=87<4H2;f?>o3>00;6)=95;65g>h4>=087E=6e:9j024=83.8:84;709m732=82B85h54i553>5<#;??18:?4n247>4=O;0o07d:9f;29 6022==:7c=94;08L6?b32c?:h4?:%151?2092d8:94<;I1:a>=n<>h1<7*<64873d=i;?>1<65f46;94?"4><0?;l5a37695>=n<>21<7*<64873d=i;?>1>65f46594?"4><0?;l5a37697>=n<><1<7*<64873d=i;?>1865f46794?"4><0?;l5a37691>=n<>>1<7*<64873d=i;?>1:65f46194?"4><0?;l5a37693>=n<1>1<7*<6487<6=i;?>1<6F<9d98m1>5290/?;;54918j603281C?4k4;h6;5?6=,:<>696<;o150?4<@:3n76g;8183>!51=3>3?6`<6580?M5>m21b8:h50;&020<30:1e?;:54:J0=`=<a==n6=4+37790=5<f:<?685G38g8?l20l3:1(>8::5:0?k51<3<0D>7j;:k73f<72-9=97:73:l021<03A92i65f49f94?"4><0?4n5a37694>N41l10e96m:18'733=<1i0b>8;:09K7<c<3`>3m7>5$246>1>d3g9=87<4H2;f?>o3000;6)=95;6;g>h4>=087E=6e:9j0=>=83.8:84;8b9m732=<2B85h54i5:4>5<#;??185m4n247>0=O;0o07d:76;29 6022=2h7c=94;48L6?b32c?484?:%151?2?k2d8:948;I1:a>=zj=><6=4>5083>5}#;h91?;o4H5;0?M2192Pjj7?9{g824?b=980:>7k51d82b?452;91>=4=1;0g>7c=;m036?:524812?5f2:h1?n4rn016>5=i9<21<6*>758232=#9>?1=:94$2;b>4103-9j<7=4$0:;>1=#913186*>8`87?!7?j3>0(<6l:59'5=b=<2.:4h4;;%3;b?2<,83;695+18390>"61;0?7)?63;68 4?32=1/=4;54:&2=3<33-;2;7:4$0;:>1=#90k186*>9c87?!7>k3>0(<7k:59'5<c=<2.:5k4;;%3b4?2<,8k:695+1`090>"6i:0?7)?n4;68 4g22=1/=l854:&2e2<33-;j47:4$0c:>1=#9hk186*>ac87?!7fk3>0(<ok:59'5dc=<2.:mk4;;%3a4?2<,8h:695+1c090>"6j:0?7)?m4;68 4d22=1/=o854:&2f2<33-;i47:4$0`:>1=#9kk186*>bc87?!7ek3>0(<lk:59'5gc=<2.:nk4;;%3`4?2<,8i:695+1b090>"6k:0?7)?l4;68 4e22=1/=n854:&2g2<33-;h47:4$0a:>1=#9jk186*>cc87?!7dk3>0(<mk:59'5fc=<2.:ok4;;%3g4?2<,8n:695+1e090>"6l:0?7)?k4;68 4b22=1/=i854:&2`2<33-;o47:4$0f:>1=#9mk186*>dc87?!7ck3>0(<jk:59'5ac=<2.:hk4;;%3f4?2<,8o:695+1d090>"6m:0?7)?j4;68 4c22=1/=h854:&2a2<33-;n47:4$0g:>1=#9lk186*>ec87?!7bk3>0(<kk:59'5`c=<2.:ik4;;%3e4?2<,8l:695+1g090>"6n:0?7)?i4;68 4`22=1/=k854:&2b2<33-;m47:4$0d:>1=#9ok186*>fc87?!7ak3>0(<hk:59'5cc=<2.:jk4;;%034?2<,;::695+21090>"58:0?7)<?4;68 7622=1/>=854:&142<33-8;47:4$32:>1=#:9k186*=0c87?!47k3>0(?>k:59'65c=<2.9<k4;;%024?2<,;;:695+20090>"59:0?7)<>4;68 7722=1/><854:&152<33-8:47:4$33a>63a3-9=n7=:f:&02f<4=o1/?;j538a8j61c2=20b>9j:19'7<>=;>l0(>76:25e?!5>l3kh7)<>9;18 77f2:1/85k536a8 1>a2:=h7c:60;28j1?62=20(>o>:29jf4<722ci>7>5;n`0>5<<gk>1<75fb683>>oe03:1D>7j;:ka=?6=@:3n76gma;29?lde290C?4k4;h``>5<O;0o07bm=:188m40b2900e<8i:18K7<c<3`;<<7>5H2;f?>o6?80;66g>7383>M5>m21b=:=50;J0=`=<a;;h6=44i33g>5<<a:2;6=44i2:2>5<O;0o07d=72;29L6?b32c84>4?::k0<1<72A92i65f39794?N41l10e>68:18K7<c<3`9347>5H2;f?>o40h0;6E=6e:9j7=d=83B85h54i2:`>5<<a:2o6=4G38g8?l5?m3:1D>7j;:k0<c<722c85=4?:I1:a>=n;0;1<7F<9d98m6?52900e>7<:18K7<c<3`9287>5H2;f?>o41<0;66g<9783>M5>m21b?4950;J0=`=<g:3i6=44i5:94?"4><0?;6`<6583?>o3>3:1(>8::558j6032810e9;50;&020<3?2d8:94=;:k77?6=,:<>6994n247>6=<a=81<7*<64873>h4>=0?76g;1;29 6022==0b>8;:498m07=83.8:84;7:l021<132c><7>5$246>11<f:<?6:54i5d94?"4><0?;6`<658;?>o3m3:1(>8::558j6032010e9j50;&020<3?2d8:94n;:k7g?6=,:<>6994n247>g=<a=h1<7*<64873>h4>=0h76g;a;29 6022==0b>8;:e98m1?=83.8:84;7:l021<b32c?<7>5$246>11<f:<?6k54i4;94?"4><0>46`<6583?M5>m21b9:4?:%151?3?3g9=87?4H2;f?>o2>3:1(>8::4:8j6032;1C?4k4;h76>5<#;??1955a37697>N41l10e8:50;&020<202d8:94;;I1:a>=n=:0;6)=95;7;?k51<3?0D>7j;:k56?6=,:<>6864n247>3=O;0o07d8>:18'733==11e?;:57:J0=`=<a?:1<7*<6486<>h4>=037E=6e:9j1c<72-9=97;7;o150??<@:3n76g:e;29 6022<20b>8;:`9K7<c<3`?o6=4+37791==i;?>1n6F<9d98m0e=83.8:84:8:l021<d3A92i65f5c83>!51=3?37c=94;f8L6?b32c>m7>5$246>0><f:<?6h5G38g8?l35290/?;;5599m732=n2B85h54i7;94?"4><0=46`<6583?M5>m21b::4?:%151?0?3g9=87?4H2;f?>o1>3:1(>8::7:8j6032;1C?4k4;h46>5<#;??1:55a37697>N41l10e;:50;&020<102d8:94;;I1:a>=n?;0;6)=95;4;?k51<3?0D>7j;:k45?6=,:<>6;64n247>3=O;0o07d9?:18'733=>11e?;:57:J0=`=<a?l1<7*<6485<>h4>=037E=6e:9j2`<72-9=9787;o150??<@:3n76g9d;29 6022?20b>8;:`9K7<c<3`<h6=4+37792==i;?>1n6F<9d98m3d=83.8:8498:l021<d3A92i65f6`83>!51=3<37c=94;f8L6?b32c=?7>5$246>3><f:<?6h5G38g8?l>6290/?;;5819m732=821b;k4?:%151?>73g9=87?4;h5f>5<#;??14=5a37696>=n?j0;6)=95;:3?k51<3907d9m:18'733=091e?;:54:9j3d<72-9=976?;o150?3<3`2j6=4+3779<5=i;?>1:65f8883>!51=32;7c=94;58?l>?290/?;;5819m732=021b4:4?:%151?>73g9=8774;h:5>5<#;??14=5a3769e>=n0<0;6)=95;:3?k51<3h07d6;:18'733=091e?;:5c:9j<6<72-9=976?;o150?b<3`296=4+3779<5=i;?>1i65f7883>!51=32;7c=94;d8?l?5290/?;;5909m732=82B85h54i8294?"4><02=6`<6582?M5>m21b4k4?:%151??63g9=87<4H2;f?>o?m3:1(>8::838j6032:1C?4k4;h:g>5<#;??15<5a37690>N41l10e5m50;&020<>92d8:94:;I1:a>=n1k0;6)=95;;2?k51<3<0D>7j;:k:e?6=,:<>64?4n247>2=O;0o07d76:18'733=181e?;:58:J0=`=<a021<7*<648:5>h4>=027E=6e:9j=2<72-9=977>;o150?g<@:3n76g66;29 60220;0b>8;:c9K7<c<3`3>6=4+3779=4=i;?>1o6F<9d98m<2=83.8:8461:l021<c3A92i65f9283>!51=33:7c=94;g8L6?b32c3n7>5$246><7<f:<?6k5G38g8?lg5290/?;;5a09m732=82B85h54i`294?"4><0j=6`<6582?M5>m21b5k4?:%151?g63g9=87<4H2;f?>o>m3:1(>8::`38j6032:1C?4k4;h;g>5<#;??1m<5a37690>N41l10ell50;&020<f92d8:94:;I1:a>=nih0;6)=95;c2?k51<3<0D>7j;:kb=?6=,:<>6l?4n247>2=O;0o07do7:18'733=i81e?;:58:J0=`=<ah=1<7*<648b5>h4>=027E=6e:9je3<72-9=97o>;o150?g<@:3n76gn5;29 6022h;0b>8;:c9K7<c<3`k?6=4+3779e4=i;?>1o6F<9d98md5=83.8:84n1:l021<c3A92i65f9b83>!51=3k:7c=94;g8L6?b32coh7>5$246>ae<f:<?6=54ie`94?"4><0oo6`<6582?>oc13:1(>8::ea8j6032;10ei650;&020<ck2d8:94<;:kg3?6=,:<>6im4n247>1=<am<1<7*<648gg>h4>=0>76gk5;29 6022mi0b>8;:798ma2=83.8:84kc:l021<032co?7>5$246>ae<f:<?6554ie094?"4><0oo6`<658:?>oc93:1(>8::ea8j6032h10ei>50;&020<ck2d8:94m;:k`a?6=,:<>6im4n247>f=<ajn1<7*<648gg>h4>=0o76glc;29 6022mi0b>8;:d98mfd=83.8:84kc:l021<a32chm7>5$246>ae<f:<?6<>4;ha;>5<#;??1hn5a376954=<aj=1<7*<648gg>h4>=0:>65fc783>!51=3nh7c=94;30?>od=3:1(>8::ea8j60328>07dm;:18'733=lj1e?;:51498m`2=83.8:84kc:l021<6>21bi>4?:%151?bd3g9=87?8;:kf6?6=,:<>6im4n247>4><3`o:6=4+3779`f=i;?>1=454id294?"4><0oo6`<6582e>=nlo0;6)=95;f`?k51<3;i76gke;29 6022mi0b>8;:0a8?lbf290/?;;5db9m732=9m10enh50;&020<ck2d8:94>e:9jg6<72-9=97jl;o150?7a32cmj7>5$246>cc<f:<?6=54igf94?"4><0mi6`<6582?>oaj3:1(>8::gg8j6032;10eko50;&020<am2d8:94<;:ke=?6=,:<>6kk4n247>1=<ao21<7*<648ea>h4>=0>76gi7;29 6022oo0b>8;:798mc0=83.8:84ie:l021<032cm97>5$246>cc<f:<?6554ig694?"4><0mi6`<658:?>oa;3:1(>8::gg8j6032h10ek<50;&020<am2d8:94m;:ke4?6=,:<>6kk4n247>f=<all1<7*<648ea>h4>=0o76gje;29 6022oo0b>8;:d98m`b=83.8:84ie:l021<a32cno7>5$246>cc<f:<?6<>4;hgb>5<#;??1jh5a376954=<al31<7*<648ea>h4>=0:>65fe983>!51=3ln7c=94;30?>ob?3:1(>8::gg8j60328>07dk9:18'733=nl1e?;:51498m461290/?;;5fd9m732=9?10e<>::18'733=nl1e?;:51698m463290/?;;5fd9m732=9110e<><:18'733=nl1e?;:51898m465290/?;;5fd9m732=9h10e<>>:18'733=nl1e?;:51c98m467290/?;;5fd9m732=9j10ekm50;&020<am2d8:94>d:9jb4<72-9=97hj;o150?7b32cn97>5$246>cc<f:<?6<h4;h33g?6=,:<>6<>m;o150?6<3`;;m7>5$246>46e3g9=87?4;h33=?6=,:<>6<>m;o150?4<3`;;;7>5$246>46e3g9=87=4;h326?6=,:<>6<?>;o150?6<3`;:<7>5$246>4763g9=87?4;h33b?6=,:<>6<?>;o150?4<3`;;h7>5$246>4763g9=87=4;n31`?6=,:<>6<<l;o150?6<3f;9n7>5$246>44d3g9=87?4;n31=?6=,:<>6<<l;o150?4<3f;947>5$246>44d3g9=87=4;n313?6=,:<>6<<l;o150?2<3f;9:7>5$246>44d3g9=87;4;n311?6=,:<>6<<l;o150?0<3f;987>5$246>44d3g9=8794;n317?6=,:<>6<<l;o150?><3f;9>7>5$246>44d3g9=8774;n315?6=,:<>6<<l;o150?g<3f;9<7>5$246>44d3g9=87l4;n32a?6=,:<>6<<l;o150?e<3f;:h7>5$246>44d3g9=87j4;n32g?6=,:<>6<<l;o150?c<3f;:n7>5$246>44d3g9=87h4;n32e?6=,:<>6<<l;o150?7732e:=54?:%151?75k2d8:94>1:9l541=83.8:84>2b9m732=9;10c<?9:18'733=9;i0b>8;:018?j76=3:1(>8::00`?k51<3;?76a>1583>!51=3;9o6`<65821>=h9:>1<7*<64826f=i;?>1=;54o010>5<#;??1=?m4n247>41<3f;8>7>5$246>44d3g9=87?7;:m274<72-9=97?=c:l021<6121d=>>50;&020<6:j1e?;:51`98k44a290/?;;513a8j60328h07b?=e;29 602288h7c=94;3`?>i6:h0;6)=95;31g>h4>=0:h65`10d94?"4><0:>n5a37695`=<g8;86=4+377957e<f:<?6<h4;n364?6=,:<>6<:i;o150?6<3f;?i7>5$246>42a3g9=87?4;n37g?6=,:<>6<:i;o150?4<3f;?n7>5$246>42a3g9=87=4;n37e?6=,:<>6<:i;o150?2<3f;?57>5$246>42a3g9=87;4;n37<?6=,:<>6<:i;o150?0<3f;?;7>5$246>42a3g9=8794;n372?6=,:<>6<:i;o150?><3f;?97>5$246>42a3g9=8774;n370?6=,:<>6<:i;o150?g<3f;??7>5$246>42a3g9=87l4;n375?6=,:<>6<:i;o150?e<3f;?<7>5$246>42a3g9=87j4;n30b?6=,:<>6<:i;o150?c<3f;8i7>5$246>42a3g9=87h4;n30`?6=,:<>6<:i;o150?7732e:?o4?:%151?73n2d8:94>1:9l56g=83.8:84>4g9m732=9;10c<=6:18'733=9=l0b>8;:018?j7403:1(>8::06e?k51<3;?76a>3683>!51=3;?j6`<65821>=h9<=1<7*<64820c=i;?>1=;54o075>5<#;??1=9h4n247>41<3f;>97>5$246>42a3g9=87?7;:m211<72-9=97?;f:l021<6121d=8=50;&020<6<o1e?;:51`98k435290/?;;515d8j60328h07b?:1;29 60228>m7c=94;3`?>i6<m0;6)=95;37b>h4>=0:h65`15094?"4><0:8k5a37695`=<g89=6=4+377951`<f:<?6<h4;n36a?6=,:<>6<;k;o150?6<3f;>o7>5$246>43c3g9=87?4;n36f?6=,:<>6<;k;o150?4<3f;>57>5$246>43c3g9=87=4;n350?6=,:<>6<8<;o150?6<3f;=>7>5$246>4043g9=87?4;n355?6=,:<>6<8<;o150?4<3f;>j7>5$246>4043g9=87=4;n35`?6=,:<>6<8l;o150?6<3f;=n7>5$246>40d3g9=87?4;n35e?6=,:<>6<8l;o150?4<3f;=57>5$246>40d3g9=87=4;n35<?6=,:<>6<8l;o150?2<3f;=;7>5$246>40d3g9=87;4;n352?6=,:<>6<8l;o150?0<3f;=97>5$246>40d3g9=8794;n146?6=,:<>6>9>;o150?6<@:3n76a<7183>!51=39<=6`<6582?M5>m21d?;h50;&020<4?81e?;:52:J0=`=<g:=i6=4+3779727<f:<?6>5G38g8?j50i3:1(>8::252?k51<3>07b=89;29 6022:=:7c=94;78?j5003:1(>8::252?k51<3<07b=87;29 6022:=:7c=94;58?j50>3:1(>8::252?k51<3207b=85;29 6022:=:7c=94;;8?j50<3:1(>8::252?k51<3k07b=83;29 6022:=:7c=94;`8?j51m3:1(>8::252?k51<3i07d:98;29 6022=<<7c=94;28?l21>3:1(>8::544?k51<3;07d:95;29 6022=<<7c=94;08?l21<3:1(>8::544?k51<3907d:9d;29 6022=<h7c=94;28L6?b32c?:o4?:%151?21k2d8:94>;I1:a>=n<?k1<7*<64872f=i;?>1>6F<9d98m10>290/?;;547a8j6032:1C?4k4;h646?6=,:<>699>;o150?6<@:3n76g;7183>!51=3><=6`<6582?M5>m21b8;h50;&020<3?81e?;:52:J0=`=<a=<n6=4+3779027<f:<?6>5G38g8?l20j3:1(>8::55b?k51<3:07d:89;29 6022==j7c=94;38?l2003:1(>8::55b?k51<3807d:87;29 6022==j7c=94;18?l20>3:1(>8::55b?k51<3>07d:85;29 6022==j7c=94;78?l20<3:1(>8::55b?k51<3<07d:83;29 6022==j7c=94;58?l2?<3:1(>8::5:0?k51<3:0D>7j;:k7<7<72-9=97:73:l021<63A92i65f49394?"4><0?4>5a37696>N41l10e96?:18'733=<190b>8;:29K7<c<3`><j7>5$246>1>43g9=87:4H2;f?>o3?l0;6)=95;6;7>h4>=0>7E=6e:9j02b=83.8:84;829m732=>2B85h54i55`>5<#;??185=4n247>2=O;0o07d:7d;29 6022=2h7c=94;28L6?b32c?4o4?:%151?2?k2d8:94>;I1:a>=n<1k1<7*<6487<f=i;?>1>6F<9d98m1>>290/?;;549a8j6032:1C?4k4;h6;<?6=,:<>696l;o150?2<@:3n76g;8683>!51=3>3o6`<6586?M5>m21b85850;&020<30j1e?;:56:J0=`=<a=2>6=4+37790=e<f:<?6:5G38g8?xu2?<0;6?uQ4d3891202ok0q~;83;296~X3m9168995f89~w0152909wS:kf:?702<a02wx9:?50;0xZ1bb34>?;7h8;|q635<72;qU8ij4=564>c0<uz?=j7>52z\7`f=:<==1j?5rs44f>5<5sW>on63;468e4>{t=?n1<7<t^5fb?823?3om7p}:6b83>7}Y<m3019:8:dg8yv31i3:1>vP;d69>011=mm1v886:181[2c>27?8:4j8:p13>=838pR9j:;<673?c03ty>::4?:3y]0a2<5=><6h84}r752?6=:rT?h>524559550<uz?=97>52z\7`7=:<==1==;4}r750?6=:rT?h<524559557<uz?=?7>52z\7`5=:<==1==>4}r756?6=:rT?ok524559bf=z{<<:6=4={_6`a>;3<>0m=6s|54d94?4|V=ih70:;7;g6?xu2=l0;6?uQ4b`891202m20q~;:d;296~X3kh168995d69~w03d2909wS:l9:?702<c>2wx98l50;0xZ1e?34>?;7j:;|q61d<72;qU8n94=564>a2<uz?>57>52z\7g3=:<==1h=5rs47;>5<5sW>h963;468`a>{t=<=1<7<t^5a7?823?3io7p}:5783>7}Y<j9019:8:ba8yv32<3:1>vP;c09>011=kk1v8;<:181[2d827?8:4l6:p104=838pR9li;<673?e23ty>9<4?:3y]0gc<5=><6n:4}r764?6=:rT?ni524559a1=z{<>m6=4={_6ag>;3<>0n?6s|55g94?4|V=hi70:;7;g3?xu2<m0;6?uQ4cc891202ml0q~;;c;296~X3j0168995dd9~w02e2909wS:m8:?702<ci2wx99750;0xZ1d134>?;7mi;|q60=<72;qU8o;4=564>f5<uz??;7>52z\7f1=:<=<1=<<4}r772?6=:rT?n>524549bc=z{<>>6=4={_6a6>;3<?0mh6s|55694?4|V=h:70:;6;da?xu2<:0;6?uQ4c2891212ok0q~;;2;296~X3io168985f89~w0262909wS:ne:?703<a02wx99>50;0xZ1gc34>?:7h8;|q6`6<72;qU9>k4=565>c0<uz?o>7>52z\67a=:<=<1=<>4}r7g5?6=:rT>?n524549b0=z{<n;6=4={_70f>;3<?0m86s|5bd94?4|V<9j70:;6;d0?xu2kl0;6?uQ52;891212o80q~;ld;296~X2;1168985f19~w0ed2909wS;<7:?703<bn2wx9nl50;0xZ05134>?:7kj;|q6gd<72;qU9>;4=565>`b<uz?h47>52z\676=:<=<1==h4}r7`3?6=:rT>??524549af=z{<i=6=4={_705>;3<?0nm6s|5b794?4|V<9;70:;6;g:?xu2k=0;6?uQ53d891212l20q~;l3;296~X2:l168985e69~w0e52909wS;=d:?703<b>2wx9n?50;0xZ04d34>?:7??6:p1f6=838pR8<m;<672?77=2wx9oh50;0xZ04f34>?:7??d:p1gb=838pR8<7;<672?77<2wx9om50;0xZ04034>?:7??3:p1gd=838pR8<9;<672?77:2wx9oo50;0xZ04234>?:7??1:p1g?=838pR8<;;<672?7782wx9o650;0xZ04434>?:7hl;|q6f2<72;qU9?<4=565>c7<uz?i:7>52z\664=:<=<1i85rs4`6>5<5sW?9<63;47824f=z{<h?6=4={_72b>;3<?0oh6s|5c094?4|V<;o70:;6;fa?xu2j80;6?uQ50a891212m30q~;m0;296~X29k168985d99~w0ga2909wS;>a:?703<c?2wx9lk50;0xZ07>34>?:7j9;|q6ea<72;qU9<64=565>a3<uz?jo7>52z\652=:<=<1h95rs4ca>5<5sW?::63;47824d=z{<kj6=4={_721>;3<?0o?6s|5`;94?4|V<;?70:;6;f1?xu2i>0;6?uQ500891212m;0q~;n6;296~X298168985d19~w0g22909wS;>0:?703<dm2wx9l:50;0xZ06a34>?:7mk;|q6e6<72;qU9=k4=565>fe<uz?j>7>52z\64a=:<=<1oo5rs4c2>5<5sW?;o63;47824<=z{<k;6=4={_73f>;3<?0hm6s|58d94?4|V<:j70:;6;a;?xu21l0;6?uQ51;891212j=0q~;6c;296~X28>168985c79~w0?e2909wS;?6:?703<d=2wx94o50;0xZ06234>?:7m;;|q6=<<72;qU9=:4=565>`2<uz?247>52z\646=:<=<1i>5rs4;4>5<5sW?;>63;478242=z{<3=6=4={_735>;3<?0n>6s|58794?4|V<:;70:;6;g2?xu21=0;6?uQ4gd891212l:0q~;63;296~X3nl168985dg9~w0?62909wS:ic:?703<cm2wx94>50;0xZ1`e34>?:7jn;|q6<c<72;qU8ko4=565>f`<uz?3i7>52z\7b<=:<=<1o>5rs4:g>5<5sW>m463;44824c=z{<2h6=4={_6e3>;3<<0no6s|59`94?4|V=l=70:;5;gb?xu20h0;6?uQ4g7891222l30q~;79;296~X3n=1689;5e99~w0>?2909wS:i3:?700<b?2wx95850;0xZ1`634>?97k9;|q6<0<72;qU8k>4=566>4613ty>494?:3y]0``<5=>>6<>:;|q6<6<72;qU8hk4=566>46c3ty>4?4?:3y]0`b<5=>>6<>;;|q6<4<72;qU8hm4=566>4643ty>4=4?:3y]0`d<5=>>6<>=;|q63c<72;qU8ho4=566>4663ty>;h4?:3y]0`?<5=>>6<>?;|q63a<72;qU8h64=566>ce<uz?<n7>52z\7a3=:<=?1j<5rs45b>5<5sW>n963;448f1>{t=>31<7<t^5g7?823=3;;56s|56:94?4|V=o870:;5;ab?xu2?>0;6?uQ4d0891222j20q~;86;296~X3l11689;5c69~w00e2909wS:ld:?700<d>2wx9;>50;0xZ1e534>?97m:;|q610<72;qU8o94=566>f2<uz??m7>52z\7ef=:<=?1i95rs4f7>5<5sW?8863;448f7>{t=j31<7<t^40:?823=3;;;6s|5cg94?4|V<;n70:;5;g1?xu2j:0;6?uQ501891222l;0q~;n8;296~X2811689;5e19~w0?c2909wS:id:?700<cn2wx94<50;0xZ1`534>?97jj;|q6<2<72;qU8h94=566>ag<uz?<o7>52z\7eg=:<=?1ok5rs41e>5<5sW>jm63;448`7>{t?;31<7<;{_51=>;38:0i<63;038a4>;3=10i<63;568a4>;3=?0i<63;508a4>;3=90i<63;4g8a4>;39?0i<63;148a4>;39=0i<63;128a4>;38l0i<63;0e8a4>;38j0i<63;0c8a4>;4m:0i<63<e38a4>;4m80i<63<e18a4>;4nk0i<63<f`8a4>;4n00i<63<f98a4>;4n:0i<63<f38a4>;4n80i<63<f18a4>;4k00i<63<c98a4>;4k>0i<63<c78a4>;3<<0i;63;478a3>;3<>0i;6s|73d94?2|V>8m70:?4;3;6>;3<00:4?523gg95=4<uz=8=7>53z\474=:<<<1?;94=57a>6003ty<?n4?:35xZ25d34>9?7l?;<616?d734>>h7l?;<66g?d734>>n7l?;<661?d734>>87l?;<60a?d734>8h7l?;<60g?d734>8n7l?;<602?d734>897l?;<600?d734>8?7l?;<61a?d734>9h7l?;<61g?d734>9n7l?;<1`5?d7349h<7l?;<1ab?d7349ii7l?;<1g=?d7349o47l?;<1g3?d7349o:7l?;<1g5?d7349o<7l?;<1`b?d7349hi7l?;<1ff?d7349nm7l?;<1f=?d7349n47l?;<671?df34>?:7ln;<673?df3ty<8?4?:2y]314<5=8?6<6=;<614?7?:2wx8l750;;a[2f?2T?m;5Q4`78Z1g33W=9h6P82b9]37d<V>8j7S9;0:\47c=Y?:o0R:=k;_6:b>X3i91U;=64^62:?[1612T<?l5Q72;8Z25e3W=8:6P;a89>0<2=9>l019;9:b3891362j;019;?:b38912a2j;019;m:b3891322j;019;;:b3891222:2;70:;5;1;7>;3<<085?5245797<3<5=>>69;4=566>15<5=>>69<4=566>17<5=>>68?4=566>1e<5=>>69l4=566>1g<5=>>6974=566>16<5=>>6:k4=566>2e<5=>>6:l4=566>2g<5=>>65o4=566>=3<5=>>65:4=566>=5<5=>>65<4=566>2?<5=>>698:;<671?21<27?8;4m1:?703<e:27?8;4=1b9>010=:8n019:9:2:3?823>393?63;4780=7=:<=<1?4;4=565>10<5=>=69;4=565>15<5=>=69<4=565>17<5=>=69j4=565>1e<5=>=69l4=565>1g<5=>=6974=565>16<5=>=6:h4=565>2c<5=>=6:m4=565>2d<5=>=6:o4=565>=0<5=>=65;4=565>=2<5=>=65=4=565>=4<5=>=6:74=565>10?34>?:7:96:?703<3><168985476891202k;019:8:c0891202;;h70:;7;02`>;3<>084=5245597=5<5=><6>7=;<673?5>=27?8:4;6:?702<3=27?8:4;3:?702<3:27?8:4;1:?702<3l27?8:4;c:?702<3j27?8:4;a:?702<3127?8:4;0:?702<0n27?8:48e:?702<0k27?8:48b:?702<0i27?8:476:?702<?=27?8:474:?702<?;27?8:472:?702<0127?8:4kd:?702<cj27?8:4k9:?702<c;27?8:4k2:?702<c927?8:4la:?702<d027?8:4l7:?702<b:27?8:4j1:?702<an27?8:4id:?702<aj27?8:4i5:?702<a<27?8:4i3:?702<bk27?8:4ja:?702<b127?8:4>059>011=999019:8:021?823?3;;o63;46824d=:<==1==74=564>46034>?;7?>2:?702<69916899511d8912028:o70:;7;65<>;3<>0?:;524559033<5=><698;;|q5e5<72;qU:=m4=564>42e3ty=5h4?:3y]25d<5=><6<:n;|q5=a<72;qU:=o4=564>42>3ty=5n4?:3y]25?<5=><6<:7;|q5=g<72;qU:=64=564>4203ty=5l4?:3y]251<5=><6<:<;|q5=<<72;qU:=84=564>4263ty=554?:3y]253<5=><6<:?;|q5=2<72;qU:=:4=564>45a3ty=584?:3y]254<5=><6<=j;|q5=1<72;qU:=?4=564>45>3ty=5>4?:3y]256<5=><6<=7;|q5=7<72;qU9kh4=564>4503ty=5<4?:3y]1cc<5=><6<;8;|q5=5<72;qU9kj4=564>4313ty=4k4?:3y]1ce<5=><6<;=;|q5<`<72;qU9kl4=564>4363ty=4i4?:3y]1cg<5=><6<:k;|q5<f<72;qU9k74=564>4253ty=4l4?:3y]1c1<5=><6<=9;|q5<<<72;qU9k84=564>44?3ty=454?:3y]1c3<5=><6<<8;|q5<2<72;qU9k:4=564>4413ty=4;4?:3y]1c5<5=><6<<:;|q5<0<72;qU9k<4=564>4433ty=494?:3y]1c7<5=><6<<?;|q5<6<72;qU9k>4=564>47b3ty=4?4?:3y]1``<5=><6<?k;|q5<4<72;qU9hk4=564>47d3ty=;k4?:3y]1`e<5=><6<?m;|q53`<72;qU9hl4=564>4713ty=;i4?:3y]1`g<5=><6<?:;|q53f<72;qU9h74=564>4733ty=;o4?:3y]1`><5=><6<=;;|q53d<72;qU9h94=564>4543ty=;44?:3y]1`0<5=><6<=?;|q53=<72;qU9h;4=564>44a3ty=;:4?:3y]1`2<5=><6<<j;|q533<72;qU9h=4=564>44f3ty=;94?:3y]1`7<5=><6<?i;|q536<72;qU9h>4=564>4743ty=;?4?:3y]1a`<5=>=6<8;;|q534<72;qU9ik4=565>4373ty=;=4?:3y]1ab<5=>=6<:j;|q52c<72;qU9im4=565>42d3ty=:h4?:3y]1ad<5=>=6<:m;|q52a<72;qU9io4=565>42f3ty=:n4?:3y]1a?<5=>=6<:6;|q52g<72;qU9i64=565>42?3ty=jh4?:3y]23?<5=>=6<:8;|q5ba<72;qU:;64=565>4053ty=jn4?:3y]231<5=>=6<:9;|q5bg<72;qU:;84=565>4223ty=jl4?:3y]233<5=>=6<:;;|q5b<<72;qU:;:4=565>4243ty=j54?:3y]235<5=>=6<:>;|q5b2<72;qU:;<4=565>4273ty=j;4?:3y]237<5=>=6<=i;|q5b0<72;qU:;>4=565>45b3ty=j>4?:3y]20c<5=>=6<8>;|q5b7<72;qU:8j4=565>45c3ty=j<4?:3y]20e<5=>=6<=m;|q5b5<72;qU:8l4=565>45f3ty=ik4?:3y]20g<5=>=6<=6;|q5a`<72;qU:874=565>45?3ty=ii4?:3y]20><5=>=6<=8;|q5af<72;qU:894=565>4303ty=io4?:3y]200<5=>=6<;9;|q5ad<72;qU:8;4=565>43a3ty=i54?:3y]205<5=>=6<;:;|q5a2<72;qU:8<4=565>4333ty=i;4?:3y]207<5=>=6<;<;|q5a0<72;qU:8>4=565>4353ty=i94?:3y]21`<5=>=6<;>;|q5a6<72;qU:9k4=565>42c3ty=i?4?:3y]21b<5=>=6<:=;|q5a4<72;qU:9m4=565>4513ty=i=4?:3y]21d<5=>=6<;j;|q5`c<72;qU:9o4=565>44c3ty=hi4?:3y]21><5=>=6<<m;|q5`f<72;qU:994=565>44>3ty=ho4?:3y]210<5=>=6<<7;|q5`d<72;qU:9;4=565>4403ty=h44?:3y]212<5=>=6<<9;|q5`=<72;qU:9=4=565>4423ty=h:4?:3y]214<5=>=6<<;;|q5`3<72;qU:9?4=565>43d3ty=h84?:3y]216<5=>=6<<<;|q5`1<72;qU:>h4=565>4453ty=h?4?:3y]26b<5=>=6<<>;|q5`4<72;qU:>m4=565>4473ty=h=4?:3y]26d<5=>=6<?j;|q5gc<72;qU:>o4=565>47c3ty=oh4?:3y]26?<5=>=6<?l;|q5ga<72;qU:>64=565>47e3ty=on4?:3y]261<5=>=6<;m;|q5gg<72;qU:>84=565>47f3ty=ol4?:3y]263<5=>=6<?7;|q5g<<72;qU:>:4=565>4703ty=o:4?:3y]264<5=>=6<?9;|q5g3<72;qU:>?4=565>4723ty=o84?:3y]266<5=>=6<?;;|q5g1<72;qU:?h4=565>4533ty=o>4?:3y]27c<5=>=6<=<;|q5g7<72;qU:?j4=565>43>3ty=o<4?:3y]27e<5=>=6<==;|q5g5<72;qU:?l4=565>4563ty=nk4?:3y]27g<5=>=6<=?;|q5f`<72;qU:?74=565>44a3ty=nn4?:3y]271<5=>=6<<j;|q5fg<72;qU:?84=565>44f3ty=nl4?:3y]273<5=>=6<?i;|q5f<<72;qU:?:4=565>4743ty=n54?:3y]275<5=>>6<8>;|q5f2<72;qU:?<4=566>45c3ty=n;4?:3y]277<5=>>6<=m;|q5f0<72;qU:?>4=566>45f3ty=n94?:3y]24`<5=>>6<=6;|q5f6<72;qU:<k4=566>45?3ty=n<4?:3y]24e<5=>>6<=8;|q5f5<72;qU:<l4=566>4303ty=mk4?:3y]24g<5=>>6<;9;|q5e`<72;qU:<74=566>43a3ty=mi4?:3y]24><5=>>6<;:;|q5ef<72;qU:<94=566>4333ty=mo4?:3y]240<5=>>6<;<;|q5ed<72;qU:<;4=566>4353ty=m44?:3y]242<5=>>6<;>;|q5e=<72;qU:<=4=566>42c3ty=m;4?:3y]247<5=>>6<:=;|q5e0<72;qU:<>4=566>4513ty=m94?:3y]25`<5=>>6<;m;|q5e6<72;qU:=k4=566>47f3ty=m?4?:3y]25b<5=>>6<?7;|q5e4<72;qU:==4=566>4703ty=5;4?:3y]1c><5=>>6<?9;|q5<g<72;qU9hj4=566>4723ty=4=4?:3y]1`4<5=>>6<?;;|q530<72;qU9i94=566>4533ty=jk4?:3y]20`<5=>>6<=<;|q5b1<72;qU:8:4=566>43>3ty=i44?:3y]21?<5=>>6<==;|q5``<72;qU:>k4=566>4563ty=h>4?:3y]265<5=>>6<=?;|q5g=<72;qU:?64=566>44a3ty=ni4?:3y]24b<5=>>6<<j;|q5f7<72;qU:<<4=566>44f3ty=m:4?:3y]1a0<5=>>6<?i;|q52d<72;qU9i;4=566>4743ty?<>4?:3y]357<5=:86>87;|q766<72;qU;==4=500>60?3ty9>44?:4y>0<3=;?8019:9:5:8912121;019:8:5:8912021;0q~=ic;297~;38:0h=63;038`5>;4nl08:=5rs56f>5<es4>;?7=97:?747<4>>1688?537:891712kn019?::cf891732kn019?<:cf8916b2kn019>k:cf8916d2kn019>m:244?xu38;0;69u2410973><5=:?6<6<;<67=?7?;278jh4>829~w17c2908w0:=3;a2?825:3i:70:>e;154>{t<<91<7ht=500>60034>9>7=97:?710<4>1168>k5be9>06b=jm168>m5be9>06d=jm168>85be9>063=jm168>:5be9>065=;?=019<j:cf8914c2kn019<l:244?825j3ho7p};2383>6}:<;81?;64=507>4>434>9<7?77:p001=839p19;7:b3891302:<370::6;`6?xu3=10;6?u244:973><5=?j6<6<;|q71f<72:q688j5c09>00e=;?2019;m:c78yv22l3:1>v3;5e802==:<<l1=5=4}r662?6=;r7?9:4l1:?713<4>11688o51908yv22j3:1?v3;5b8`5>;3=k08:55244d95=4<uz>>57>54z?714<4>>1688>53758912a2:<<70::a;154>{t<=n1<7?>{<664?510278i>4md:?0a7<el278i<4md:?0a5<el278jo4md:?0bd<el278j44md:?0b=<el278j>4md:?0b7<el278j<4md:?0b5<el278o44md:?0g=<el278o:4md:?0g3<el2wx89m50;:x912a2:<370:;9;3;0>;3<<084n5245797=`<5=>=6>6l;<672?5?n27?8:4<8b9>011=;1l0q~::e;297~;3=<08::524469731<5=?m6>8?;|q717<728;p19;;:24;?85d93ho70=l0;`g?85en3ho70=me;`g?85c13ho70=k8;`g?85c?3ho70=k6;`g?85c93ho70=k0;`g?85dn3ho70=le;`g?85bj3ho70=ja;`g?85b13ho70=j8;`g?xu3<h0;64u24049f0=:<8?1n8524069f0=:<891n85241g9f0=:<9n1n85241a9f0=:<9h1n8524169736<uz>;m7>54z?753<d927?<h4<699>04e=91801>hk:0:1?xu39;0;65u2404973><5:i26n?4=2c4>4>434>;<7?75:?0bc<60>1689;5519>010==8168995509~w16>290>w0:>5;a2?827l39=463;1`82<7=:<8i1=5=4=522>4>43ty?=<4?:6y>043=;?201>o8:0:1?85f03;3?63;0182<7=:<=?18k52454915=:<==19=5rs52;>5<1s4>:87m>;<63g?51027?=l4>859>04e=91?019>9:0:1?82793;3:6s|40294?1|5=;?6>87;<1b<?7?:278m44>829>7c`=919019:::5g891212=l019:8:5d8yv27?3:14v3;128`5>;38k08:55240c95=5<5=;h6<6;;<632?7?;27?<<4>869>7cb=91?019>::0:2?xu38o0;6;u2401973><5:k26<6=;<1eb?7?>27?884;d:?703<3m27?8:4;e:p04d=838p19>j:b38917d2:<;7p};1883>7}:<9n1o<5240c9736<uz>:47>52z?74f<d927?<;4<619~w1702909w0:?b;a2?827=39=<6s|45`94?43s4>8i7l:;<60`?d234>8o7l:;<60f?d234>8:7l:;<601?d234>887l:;<607?d234>9i7l:;<61`?d234>9o7l:;<61f?d234>987=90:?700<6?81689;5464891222==>70:;5;640>;3<<0?;>524549527<5=>=699m;<672?20127?8;4;799>010=<>=019:9:555?823>3><963;478731=:<=<18:=4=564>41634>?;7:8b:?702<3?016899546:891202==<70:;7;642>;3<>0?;8524559022<5=><699<;|q777<72:q68>k5c09>060=;?2019?j:0:1?xu3;h0;6;u242g973><5:oi6n?4=2c7>4>434>?9766;<672?>f34>?;76n;|q774<72:q68>j5c09>063=;?2019?i:0:4?xu3;00;6;u242f973><5:k?6<6=;<1b1?7?;27?88478:?703<?127?8:479:p066=839p19=l:b3891532:<370:>f;3;1>{t<:21<78t=51`>60?349j97?72:?0e3<60:1689;5869>010=01168995899~w14a2908w0:<b;a2?824;39=463;1g82<6=z{=9<6=4:{<60f?510278m;4>839>013=0?168985869>011=0>1v9<n:186824>3i:70:=e;15<>;3<=0:4?5243395=1<5=;n6<6;;|q76<<72<q68>;5c09>07b=;?2019:=:0:1?823<3;3?63;2182<1=z{=836=48{<600?e634>9o7=98:?707<60=1689:519789141282970:=1;3;2>;3:90:485rs504>5<0s4>8?7m>;<61f?51027?8?4>829>012=91>019<9:0:0?82593;3863;2482<4=z{=>86=4={<61a?e634>?87=90:p017=838p19<k:b3891252:<;7p};4183>7}:<;i1o<524349736<uz>8j7>52z?76g<d927?>84<619~w6`0290>w0=j3;a2?85aj39=463<ad82<6=:;k:1=5:4=2fb>4>23ty8hk4?:5y>7`5=;?2019>?:0:7?85an3;3>63<fe82<6=z{:ko6=4={<1f6?e6349ji7=90:p7ac=839p1>k=:24;?82783;3?63;0082<1=z{:km6=4={<1f5?e6349i<7=90:p7ab=839p1>k>:24;?85an3;3863;0082<0=z{:h:6=4={<1f4?e6349om7=90:p7ae=83>p1>k?:24;?85an3;3963;0082<7=:;on1=5:4}r1g1?6==r78o<4l1:?0`<<4>116?o85191896d?282870=kb;3;1>{t;kn1<7=t=2a2>60?34>9=7?72:?75`<60:1v>l::18185d83i:70=m6;154>{t;ki1<7=t=2a3>60?34>:j7?76:?765<60:1v>l8:18185en3i:70=m8;154>{t;kh1<7:t=2`e>60?34>9=7?75:?75c<60=168?>51948yv5e13:1>v3<bd8`5>;4lk08:=5rs2`b>5<4s49ii7=98:?764<60:168<h51908yv5bn3:1>v3<fc8`5>;4n:08:55rs2gf>5<5s49mm7m>;<1e6?5102wx?k850;6x96`f2:<370=ne;3;6>;4j90:4>523ec95=2<uz9nh7>52z?0b<<d9278j<4<699~w6`22908w0=i9;15<>;4j90:4?523ec95=5<uz9no7>52z?0b=<d9278j=4<699~w6`32909w0=i8;15<>;4lh0:4?5rs2ag>5<5s49o57m>;<1g5?5102wx?nm50;0x96b?2j;01>j?:24;?xu4l=0;69u23e:973><5:h=6<6=;<1a<?7?:278ho4>859~w6ee2909w0=k7;a2?85dn39=46s|3e194?5|5:n<6>87;<1a<?7?<278ho4>829~w6ef2909w0=k6;a2?85dm39=46s|3e094?4|5:n=6>87;<1gf?7?:2wx?h950;0x96`42j;01>km:24;?xu4m?0;6?u23g09g4=:;lk1?;64}r1f1?6=:r78j<4l1:?0a<<4>11v>k;:18185a83i:70=j8;15<>{t;j?1<7<t=2f2>f7<5:i26>87;|q0g1<72;q6?i>5c09>7f>=;?20q~=l3;296~;4ko0h=63<c6802==z{:i96=4={<1`a?e6349h:7=98:p7g4=838p1>m7:b3896g02:<;7p}<b283>7}:;j=1o<523`:9736<uz9i87>52z?0g3<d9278m44<619~w6gf2909w0=ja;a2?85f<39=<6s|3``94?4|5:o26n?4=2c6>6073ty8mn4?:3y>7`>=k816?l853728yv2303:18v3;488025=:<=?1=;k4=565>40b34>?;7?9e:p077=838p19<>:243?826m3;3;6s|41294?4|5=:;6>8?;<1ea?7?=2wx?kh50;0x96`a2:<;70=ie;3;3>{t<9;1<7<t=522>607349mi7?76:p67>=838p1>hk:243?85am3;386s|26a94?4|5=;m6>8?;<62a?7?>2wx?<j50;0x91472:<;70:>e;3;1>{z{>9:6=4={_505>;fm3=8=6*;61806==z{>9h6=4={_50g>;fm3=8o6*;61807a=z{>826=4={_51=>;fm3=956*;618017=z{<=>6=4={_6f5>;fm3>n=6*;618171=z{<=86=4={_6f4>;fm3>n<6*;61817c=z{<=96=4={_6gb>;fm3>oj6*;61810d=z{<=:6=4={_6ga>;fm3>oi6*;618110=z{<=;6=4={_6g`>;fm3>oh6*;618125=z{<<m6=4={_6gg>;fm3>oo6*;61812g=z{<<n6=4={_6gf>;fm3>on6*;61812`=z{<<o6=4={_6ge>;fm3>om6*;61812c=z{<<h6=4={_6g=>;fm3>o56*;618134=z{<<j6=4={_6g3>;fm3>o;6*;61813a=z{<<26=4={_6g2>;fm3>o:6*;6181<==z{<<36=4={_6g1>;fm3>o96*;6181=6=z{<<<6=4={_6g0>;fm3>o86*;6181=`=z{<<=6=4={_6g7>;fm3>o?6*;6181e<=z{<<>6=4={_6g6>;fm3>o>6*;6181f1=z{<<?6=4={_6g5>;fm3>o=6*;6181fc=z{<<86=4={_6g4>;fm3>o<6*;6181gd=z{<<96=4={_6`b>;fm3>hj6*;6181`0=z{<<:6=4={_6`a>;fm3>hi6*;6181a5=z{<?m6=4={_6`g>;fm3>ho6*;6181ag=z{<?n6=4={_6`f>;fm3>hn6*;6181b3=z{<?o6=4={_6`e>;fm3>hm6*;618044=z{<?h6=4={_6`=>;fm3>h56*;61804f=z{<?i6=4={_6`<>;fm3>h46*;618053=z{<?j6=4={_6`3>;fm3>h;6*;61805==z{<?26=4={_6`2>;fm3>h:6*;61805<=z{<?36=4={_6`1>;fm3>h96*;61805d=z{<?<6=4={_6`0>;fm3>h86*;61805g=z{<?=6=4={_6`7>;fm3>h?6*;61805f=z{<??6=4={_6`5>;fm3>h=6*;61805`=z{<?86=4={_6`4>;fm3>h<6*;61805c=z{<?96=4={_6ab>;fm3>ij6*;618065=z{<?:6=4={_6aa>;fm3>ii6*;618064=z{<?;6=4={_6a`>;fm3>ih6*;618067=z{<>m6=4={_6ag>;fm3>io6*;618066=z{<>n6=4={_6af>;fm3>in6*;618061=z{<>o6=4={_6ae>;fm3>im6*;618060=z{<>h6=4={_6a=>;fm3>i56*;618063=z{<>i6=4={_6a<>;fm3>i46*;618062=z{<>26=4={_6a2>;fm3>i:6*;61806<=z{<>36=4={_6a1>;fm3>i96*;61806d=z{<><6=4={_6a0>;fm3>i86*;61806g=z{<>=6=4={_6a7>;fm3>i?6*;61806f=z{<>>6=4={_6a6>;fm3>i>6*;61806a=z{<>?6=4={_6a5>;fm3>i=6*;61806`=z{<>86=4={_6a4>;fm3>i<6*;61806c=z{<>96=4={_6bb>;fm3>jj6*;618075=z{<>:6=4={_6ba>;fm3>ji6*;618074=z{<>;6=4={_6b`>;fm3>jh6*;618077=z{<n86=4={_70a>;fm3?8i6*;618076=z{<n96=4={_70`>;fm3?8h6*;618071=z{<n:6=4={_70g>;fm3?8o6*;618070=z{<n;6=4={_70f>;fm3?8n6*;618073=z{<im6=4={_70e>;fm3?8m6*;618072=z{<in6=4={_70=>;fm3?856*;61807==z{<io6=4={_70<>;fm3?846*;61807<=z{<ih6=4={_703>;fm3?8;6*;61807d=z{<ii6=4={_702>;fm3?8:6*;61807g=z{<ij6=4={_701>;fm3?896*;61807f=z{<i36=4={_707>;fm3?8?6*;61807`=z{<i<6=4={_706>;fm3?8>6*;61807c=z{<i=6=4={_705>;fm3?8=6*;618005=z{<i>6=4={_704>;fm3?8<6*;618004=z{<i?6=4={_71b>;fm3?9j6*;618007=z{<i86=4={_71a>;fm3?9i6*;618006=z{<i96=4={_71`>;fm3?9h6*;618001=z{<i:6=4={_71g>;fm3?9o6*;618000=z{<i;6=4={_71f>;fm3?9n6*;618003=z{<hm6=4={_71e>;fm3?9m6*;618002=z{<ho6=4={_71<>;fm3?946*;61800==z{<hh6=4={_713>;fm3?9;6*;61800<=z{<hi6=4={_712>;fm3?9:6*;61800d=z{<hj6=4={_711>;fm3?996*;61800g=z{<h26=4={_710>;fm3?986*;61800f=z{<h36=4={_717>;fm3?9?6*;61800a=z{<h<6=4={_716>;fm3?9>6*;61800`=z{<h=6=4={_715>;fm3?9=6*;61800c=z{<h>6=4={_714>;fm3?9<6*;618015=z{<h?6=4={_72b>;fm3?:j6*;618014=z{<h96=4={_72`>;fm3?:h6*;618016=z{<h:6=4={_72g>;fm3?:o6*;618011=z{<h;6=4={_72f>;fm3?:n6*;618010=z{<km6=4={_72e>;fm3?:m6*;618013=z{<kn6=4={_72=>;fm3?:56*;618012=z{<ko6=4={_72<>;fm3?:46*;61801==z{<kh6=4={_723>;fm3?:;6*;61801<=z{<ki6=4={_722>;fm3?::6*;61801d=z{<kj6=4={_721>;fm3?:96*;61801g=z{<k26=4={_720>;fm3?:86*;61801f=z{<k<6=4={_726>;fm3?:>6*;61816d=z{<k=6=4={_725>;fm3?:=6*;61816g=z{<k>6=4={_724>;fm3?:<6*;61816f=z{<k?6=4={_73b>;fm3?;j6*;61816a=z{<k86=4={_73a>;fm3?;i6*;61816`=z{<k96=4={_73`>;fm3?;h6*;61816c=z{<k:6=4={_73g>;fm3?;o6*;618175=z{<k;6=4={_73f>;fm3?;n6*;618174=z{<3m6=4={_73e>;fm3?;m6*;618177=z{<3n6=4={_73=>;fm3?;56*;618176=z{<3h6=4={_733>;fm3?;;6*;618170=z{<3i6=4={_732>;fm3?;:6*;618173=z{<3j6=4={_731>;fm3?;96*;618172=z{<326=4={_730>;fm3?;86*;61817==z{<336=4={_737>;fm3?;?6*;61817<=z{<3<6=4={_736>;fm3?;>6*;61817d=z{<3=6=4={_735>;fm3?;=6*;61817g=z{<3>6=4={_734>;fm3?;<6*;61817f=z{<3?6=4={_6eb>;fm3>mj6*;61817a=z{<386=4={_6ea>;fm3>mi6*;61817`=z{<3:6=4={_6eg>;fm3>mo6*;618105=z{<3;6=4={_6ef>;fm3>mn6*;618104=z{<2m6=4={_6ee>;fm3>mm6*;618107=z{<2n6=4={_6e=>;fm3>m56*;618106=z{<2o6=4={_6e<>;fm3>m46*;618101=z{<2h6=4={_6e3>;fm3>m;6*;618100=z{<2i6=4={_6e2>;fm3>m:6*;618103=z{<2j6=4={_6e1>;fm3>m96*;618102=z{<226=4={_6e0>;fm3>m86*;61810==z{<236=4={_6e7>;fm3>m?6*;61810<=z{<2=6=4={_6e5>;fm3>m=6*;61810g=z{<2>6=4={_6e4>;fm3>m<6*;61810f=z{<2?6=4={_6fb>;fm3>nj6*;61810a=z{<286=4={_6fa>;fm3>ni6*;61810`=z{<296=4={_6f`>;fm3>nh6*;61810c=z{<2:6=4={_6fg>;fm3>no6*;618115=z{<2;6=4={_6ff>;fm3>nn6*;618114=z{<=m6=4={_6fe>;fm3>nm6*;618117=z{<=n6=4={_6f=>;fm3>n56*;618116=z{<=o6=4={_6f<>;fm3>n46*;618111=z{<=i6=4={_6f2>;fm3>n:6*;618113=z{<=j6=4={_6f1>;fm3>n96*;618112=z{<=26=4={_6f0>;fm3>n86*;61811==z{<=36=4={_6f7>;fm3>n?6*;61811<=z{<=<6=4={_6f6>;fm3>n>6*;61811d=z{<==6=4={_6g<>;fm3>o46*;61811g=z{<<i6=4={_6``>;fm3>hh6*;61811f=z{<<;6=4={_6`6>;fm3>h>6*;61811a=z{<?>6=4={_6a3>;fm3>i;6*;61811`=z{<>j6=4={_6bg>;fm3>jo6*;61811c=z{<n?6=4={_700>;fm3?886*;618124=z{<i26=4={_71=>;fm3?956*;618127=z{<hn6=4={_72a>;fm3?:i6*;618126=z{<h86=4={_727>;fm3?:?6*;618121=z{<k36=4={_73<>;fm3?;46*;618120=z{<3o6=4={_6e`>;fm3>mh6*;618123=z{<396=4={_6e6>;fm3>m>6*;618122=z{<2<6=4={_6f3>;fm3>n;6*;61812==z{<=h6=4={_6bf>;fm3>jn6*;61812<=z{<9m6=4={_6be>;fm3>jm6*;61812d=z{>>96=4={_576>;fm3=?>6*;61812f=z{>8m6=4={_51b>;fm3=9j6*;61812a=z{?k;6=4={_43g>;fm3<;o6*;618135=z{?3n6=4={_43f>;fm3<;n6*;618137=z{?3o6=4={_43e>;fm3<;m6*;618136=z{?3h6=4={_43=>;fm3<;56*;618131=z{?3i6=4={_43<>;fm3<;46*;618130=z{?3j6=4={_433>;fm3<;;6*;618133=z{?326=4={_432>;fm3<;:6*;618132=z{?336=4={_431>;fm3<;96*;61813==z{?3<6=4={_430>;fm3<;86*;61813<=z{?3>6=4={_436>;fm3<;>6*;61813d=z{?3?6=4={_435>;fm3<;=6*;61813g=z{?386=4={_434>;fm3<;<6*;61813`=z{?396=4={_7eb>;fm3?mj6*;61813c=z{?3:6=4={_7ea>;fm3?mi6*;6181<5=z{?3;6=4={_7e`>;fm3?mh6*;6181<4=z{?2m6=4={_7eg>;fm3?mo6*;6181<7=z{?2n6=4={_7ef>;fm3?mn6*;6181<6=z{?2o6=4={_7ee>;fm3?mm6*;6181<1=z{?2h6=4={_7e=>;fm3?m56*;6181<0=z{?2j6=4={_7e3>;fm3?m;6*;6181<3=z{?226=4={_7e2>;fm3?m:6*;6181<2=z{?236=4={_7e1>;fm3?m96*;6181<<=z{?2<6=4={_7e0>;fm3?m86*;6181<d=z{?2=6=4={_7e7>;fm3?m?6*;6181<g=z{?2>6=4={_7e6>;fm3?m>6*;6181<f=z{?2?6=4={_7e5>;fm3?m=6*;6181<a=z{?286=4={_7e4>;fm3?m<6*;6181<`=z{?296=4={_7fb>;fm3?nj6*;6181<c=z{?2:6=4={_7fa>;fm3?ni6*;6181=5=z{?=m6=4={_7fg>;fm3?no6*;6181=4=z{?=n6=4={_7ff>;fm3?nn6*;6181=7=z{?=o6=4={_7fe>;fm3?nm6*;6181=1=z{?=h6=4={_7f=>;fm3?n56*;6181=0=z{?=i6=4={_7f<>;fm3?n46*;6181=3=z{?=j6=4={_7f3>;fm3?n;6*;6181=2=z{?=26=4={_7f2>;fm3?n:6*;6181===z{?=36=4={_7f1>;fm3?n96*;6181=<=z{?=<6=4={_7f0>;fm3?n86*;6181=d=z{?==6=4={_7f7>;fm3?n?6*;6181=g=z{?=?6=4={_7f5>;fm3?n=6*;6181=f=z{?=86=4={_7f4>;fm3?n<6*;6181=a=z{?=96=4={_7gb>;fm3?oj6*;6181=c=z{?=:6=4={_7ga>;fm3?oi6*;6181e5=z{?=;6=4={_7g`>;fm3?oh6*;6181e4=z{?<m6=4={_7gg>;fm3?oo6*;6181e7=z{?<n6=4={_7gf>;fm3?on6*;6181e6=z{?<o6=4={_7ge>;fm3?om6*;6181e1=z{?<h6=4={_7g=>;fm3?o56*;6181e0=z{?<i6=4={_7g<>;fm3?o46*;6181e3=z{?ln6=4={_45=>;fm3<=56*;6181e2=z{?lo6=4={_45<>;fm3<=46*;6181e==z{?lh6=4={_453>;fm3<=;6*;6181ed=z{?li6=4={_452>;fm3<=:6*;6181eg=z{?lj6=4={_451>;fm3<=96*;6181ef=z{?l26=4={_450>;fm3<=86*;6181ea=z{?l36=4={_457>;fm3<=?6*;6181e`=z{?l<6=4={_456>;fm3<=>6*;6181ec=z{?l=6=4={_455>;fm3<==6*;6181f5=z{?l>6=4={_454>;fm3<=<6*;6181f4=z{?l86=4={_46a>;fm3<>i6*;6181f7=z{?l96=4={_46`>;fm3<>h6*;6181f6=z{?l:6=4={_46g>;fm3<>o6*;6181f0=z{?l;6=4={_46f>;fm3<>n6*;6181f3=z{?om6=4={_46e>;fm3<>m6*;6181f2=z{?on6=4={_46=>;fm3<>56*;6181f==z{?oo6=4={_46<>;fm3<>46*;6181f<=z{?oh6=4={_463>;fm3<>;6*;6181fd=z{?oi6=4={_462>;fm3<>:6*;6181fg=z{?oj6=4={_461>;fm3<>96*;6181ff=z{?o36=4={_467>;fm3<>?6*;6181fa=z{?o<6=4={_466>;fm3<>>6*;6181f`=z{?o=6=4={_465>;fm3<>=6*;6181g5=z{?o>6=4={_464>;fm3<><6*;6181g4=z{?o?6=4={_47b>;fm3<?j6*;6181g7=z{?o86=4={_47a>;fm3<?i6*;6181g6=z{?o96=4={_47`>;fm3<?h6*;6181g1=z{?o:6=4={_47g>;fm3<?o6*;6181g0=z{?o;6=4={_47f>;fm3<?n6*;6181g3=z{?nm6=4={_47e>;fm3<?m6*;6181g2=z{?no6=4={_47<>;fm3<?46*;6181g==z{?nh6=4={_473>;fm3<?;6*;6181g<=z{?ni6=4={_472>;fm3<?:6*;6181gg=z{?nj6=4={_471>;fm3<?96*;6181gf=z{?n26=4={_470>;fm3<?86*;6181ga=z{?n36=4={_477>;fm3<??6*;6181g`=z{?n<6=4={_476>;fm3<?>6*;6181gc=z{?n=6=4={_475>;fm3<?=6*;6181`5=z{?n>6=4={_474>;fm3<?<6*;6181`4=z{?n?6=4={_40b>;fm3<8j6*;6181`7=z{?n96=4={_40`>;fm3<8h6*;6181`6=z{?n:6=4={_40g>;fm3<8o6*;6181`1=z{?n;6=4={_40f>;fm3<8n6*;6181`3=z{?im6=4={_40e>;fm3<8m6*;6181`2=z{?in6=4={_40=>;fm3<856*;6181`==z{?io6=4={_40<>;fm3<846*;6181`<=z{?ih6=4={_403>;fm3<8;6*;6181`d=z{?ii6=4={_402>;fm3<8:6*;6181`g=z{?ij6=4={_401>;fm3<896*;6181`f=z{?i26=4={_400>;fm3<886*;6181`a=z{?i<6=4={_406>;fm3<8>6*;6181``=z{?i=6=4={_405>;fm3<8=6*;6181`c=z{?i>6=4={_404>;fm3<8<6*;6181a4=z{?i?6=4={_41b>;fm3<9j6*;6181a7=z{?i86=4={_41a>;fm3<9i6*;6181a6=z{?i96=4={_41`>;fm3<9h6*;6181a1=z{?i:6=4={_41g>;fm3<9o6*;6181a0=z{?i;6=4={_41f>;fm3<9n6*;6181a3=z{?hm6=4={_41e>;fm3<9m6*;6181a2=z{?hn6=4={_41=>;fm3<956*;6181a==z{?hh6=4={_413>;fm3<9;6*;6181a<=z{?hi6=4={_412>;fm3<9:6*;6181ad=z{?hj6=4={_411>;fm3<996*;6181af=z{?h26=4={_410>;fm3<986*;6181aa=z{?h36=4={_417>;fm3<9?6*;6181a`=z{?h<6=4={_416>;fm3<9>6*;6181ac=z{?h=6=4={_415>;fm3<9=6*;6181b5=z{?h>6=4={_414>;fm3<9<6*;6181b4=z{?h?6=4={_42b>;fm3<:j6*;6181b7=z{?h86=4={_42a>;fm3<:i6*;6181b6=z{?h:6=4={_42g>;fm3<:o6*;6181b1=z{?h;6=4={_42f>;fm3<:n6*;6181b0=z{?km6=4={_42e>;fm3<:m6*;6181b2=z{?kn6=4={_42=>;fm3<:56*;6181b==z{?ko6=4={_42<>;fm3<:46*;6181b<=z{?kh6=4={_423>;fm3<:;6*;6181bd=z{?ki6=4={_422>;fm3<::6*;6181bg=z{?kj6=4={_421>;fm3<:96*;6181bf=z{?k26=4={_420>;fm3<:86*;6181ba=z{?k36=4={_427>;fm3<:?6*;6181b`=z{?k=6=4={_425>;fm3<:=6*;6181bc=z{?k>6=4={_424>;fm3<:<6*;618045=z{?k?6=4={_43b>;fm3<;j6*;618047=z{?k86=4={_43a>;fm3<;i6*;618046=z{?k96=4={_43`>;fm3<;h6*;618041=z{?k:6=4={_437>;fm3<;?6*;618040=z{?3=6=4={_7e<>;fm3?m46*;618043=z{?2i6=4={_7f`>;fm3?nh6*;618042=z{?2;6=4={_7f6>;fm3?n>6*;61804==z{?=>6=4={_7g3>;fm3?o;6*;61804<=z{?lm6=4={_46b>;fm3<>j6*;61804d=z{?l?6=4={_460>;fm3<>86*;61804g=z{?o26=4={_47=>;fm3<?56*;61804a=z{?nn6=4={_40a>;fm3<8i6*;61804`=z{?n86=4={_407>;fm3<8?6*;61804c=z{?i36=4={_41<>;fm3<946*;618055=z{?ho6=4={_42`>;fm3<:h6*;618054=z{?h96=4={_426>;fm3<:>6*;618057=z{?k<6=4={_7g2>;fm3?o:6*;618056=z{?<j6=4={_7g1>;fm3?o96*;618051=z{>:86=4={_537>;fm3=;?6*;618050=z{>::6=4={_535>;fm3=;=6*;618052=zug3<o7>52zJ724=zf0=o6=4={I655>{i1>o1<7<tH542?xh>?o0;6?uG4738yk??83:1>vF;609~j<>62909wE:91:m==4=838pD98>;|l:<6<72;qC8;?4}o;;0?6=:rB?:<5rn8:6>5<5sA>==6sa99494?4|@=<:7p`68683>7}O<?;0qc778;296~N3>81vb466:181M2192we55o50;0xL1063td24o4?:3yK037<ug33o7>52zJ724=zf02o6=4={I655>{i11o1<7<tH542?xh>0o0;6?uG4738yk?>83:1>vF;609~j<?62909wE:91:m=<4=838pD98>;|l:=6<72;qC8;?4}o;:0?6=:rB?:<5rn8;6>5<5sA>==6sa98494?4|@=<:7p`69683>7}O<?;0qc768;296~N3>81vb476:181M2192we54o50;0xL1063td25o4?:3yK037<ug32o7>52zJ724=zf03o6=4={I655>{i10o1<7<tH542?xh>1o0;6?uG4738yk?f83:1>vF;609~j<g62909wE:91:m=d4=838pD98>;|l:e6<72;qC8;?4}o;b0?6=:rB?:<5rn8c6>5<5sA>==6sa9`494?4|@=<:7p`6a683>7}O<?;0qc7n8;296~N3>81vb4o6:181M2192we5lo50;0xL1063td2mo4?:3yK037<ug3jo7>52zJ724=zf0ko6=4={I655>{i1ho1<7<tH542?xh>io0;6?uG4738yk?e83:1>vF;609~j<d62909wE:91:m=g4=838pD98>;|l:f6<72;qC8;?4}o;a0?6=:rB?:<5rn8`6>5<5sA>==6sa9c494?4|@=<:7p`6b683>7}O<?;0qc7m8;296~N3>81vb4l6:181M2192we5oo50;0xL1063td2no4?:3yK037<ug3io7>52zJ724=zf0ho6=4={I655>{i1ko1<7<tH542?xh>jo0;6?uG4738yk?d83:1>vF;609~j<e62909wE:91:m=f4=838pD98>;|l:g6<72;qC8;?4}o;`0?6=:rB?:<5rn8a6>5<5sA>==6sa9b494?4|@=<:7p`6c683>7}O<?;0qc7l8;296~N3>81vb4m6:181M2192we5no50;0xL1063td2oo4?:3yK037<ug3ho7>52zJ724=zf0io6=4={I655>{i1jo1<7<tH542?xh>ko0;6?uG4738yk?c83:1>vF;609~j<b62909wE:91:m=a4=838pD98>;|l:`6<72;qC8;?4}o;g0?6=:rB?:<5rn8f6>5<5sA>==6sa9e494?4|@=<:7p`6d683>7}O<?;0qc7k8;296~N3>81vb4j6:181M2192we5io50;0xL1063td2ho4?:3yK037<ug3oo7>52zJ724=zf0no6=4={I655>{i1mo1<7<tH542?xh>lo0;6?uG4738yk?b83:1>vF;609~j<c62909wE:91:m=`4=838pD98>;|l:a6<72;qC8;?4}o;f0?6=:rB?:<5rn8g6>5<5sA>==6sa9d494?4|@=<:7p`6e683>7}O<?;0qc7j8;296~N3>81vb4k6:181M2192we5ho50;0xL1063td2io4?:3yK037<ug3no7>52zJ724=zf0oo6=4={I655>{i1lo1<7<tH542?xh>mo0;6?uG4738yk?a83:1>vF;609~j<`62909wE:91:m=c4=838pD98>;|l:b6<72;qC8;?4}o;e0?6=:rB?:<5rn8d6>5<5sA>==6sa9g494?4|@=<:7p`6f683>7}O<?;0qc7i8;296~N3>81vb4h6:181M2192we5ko50;0xL1063td2jo4?:3yK037<ug3mo7>52zJ724=zf0lo6=4={I655>{i1oo1<7<tH542?xh>no0;6?uG4738ykg783:1>vF;609~jd662909wE:91:me54=838pD98>;|lb46<72;qC8;?4}oc30?6=:rB?:<5rn`26>5<5sA>==6saa1494?4|@=<:7p`n0683>7}O<?;0qco?8;296~N3>81vbl>6:181M2192wem=o50;0xL1063tdj<o4?:3yK037<ugk;o7>52zJ724=zfh:o6=4={I655>{ii9o1<7<tH542?xhf8o0;6?uG4738ykg683:1>vF;609~jd762909wE:91:me44=838pD98>;|lb56<72;qC8;?4}oc20?6=:rB?:<5rn`36>5<5sA>==6saa0494?4|@=<:7p`n1683>7}O<?;0qco>8;296~N3>81vbl?6:181M2192wem<o50;0xL1063tdj=o4?:3yK037<ugk:o7>52zJ724=zfh;o6=4={I655>{ii8o1<7<tH542?xhf9o0;6?uG4738ykg583:1>vF;609~jd462909wE:91:me74=838pD98>;|lb66<72;qC8;?4}oc10?6=:rB?:<5rn`06>5<5sA>==6saa3494?4|@=<:7p`n2683>7}O<?;0qco=8;296~N3>81vbl<6:181M2192wem?o50;0xL1063tdj>o4?:3yK037<ugk9o7>52zJ724=zfh8o6=4={I655>{ii;o1<7<tH542?xhf:o0;6?uG4738ykg483:1>vF;609~jd562909wE:91:me64=838pD98>;|lb76<72;qC8;?4}oc00?6=:rB?:<5rn`16>5<5sA>==6saa2494?4|@=<:7p`n3683>7}O<?;0qco<8;296~N3>81vbl=6:181M2192wem>o50;0xL1063tdj?o4?:3yK037<ugk8o7>52zJ724=zfh9o6=4={I655>{ii:o1<7<tH542?xhf;o0;6?uG4738ykg383:1>vF;609~jd262909wE:91:me14=838pD98>;|lb06<72;qC8;?4}oc70?6=:rB?:<5rn`66>5<5sA>==6saa5494?4|@=<:7p`n4683>7}O<?;0qco;8;296~N3>81vbl:6:181M2192wem9o50;0xL1063tdj8o4?:3yK037<ugk?o7>52zJ724=zfh>o6=4={I655>{ii=o1<7<tH542?xhf<o0;6?uG4738ykg283:1>vF;609~jd362909wE:91:me04=838pD98>;|lb16<72;qC8;?4}oc60?6=:rB?:<5rn`76>5<5sA>==6saa4494?4|@=<:7p`n5683>7}O<?;0qco:8;296~N3>81vbl;6:181M2192wem8o50;0xL1063tdj9o4?:3yK037<ugk>o7>52zJ724=zfh?o6=4={I655>{ii<o1<7<tH542?xhf=o0;6?uG4738ykg183:1>vF;609~jd062909wE:91:me34=838pD98>;|lb26<72;qC8;?4}oc50?6=:rB?:<5rn`46>5<5sA>==6saa7494?4|@=<:7p`n6683>7}O<?;0qco98;296~N3>81vbl86:181M2192wem;o50;0xL1063tdj:o4?:3yK037<ugk=o7>52zJ724=zfh<o6=4={I655>{ii?o1<7<tH542?xhf>o0;6?uG4738ykg083:1>vF;609~jd162909wE:91:me24=838pD98>;|lb36<72;qC8;?4}oc40?6=:rB?:<5rn`56>5<5sA>==6saa6494?4|@=<:7p`n7683>7}O<?;0qco88;296~N3>81vbl96:181M2192wem:o50;0xL1063tdj;o4?:3yK037<ugk<o7>52zJ724=zfh=o6=4={I655>{ii>o1<7<tH542?xhf?o0;6?uG4738ykg?83:1>vF;609~jd>62909wE:91:me=4=838pD98>;|lb<6<72;qC8;?4}oc;0?6=:rB?:<5rn`:6>5<5sA>==6saa9494?4|@=<:7p`n8683>7}O<?;0qco78;296~N3>81vbl66:181M2192wem5o50;0xL1063tdj4o4?:3yK037<ugk3o7>52zJ724=zfh2o6=4={I655>{ii1o1<7<tH542?xhf0o0;6?uG4738ykg>83:1>vF;609~jd?62909wE:91:me<4=838pD98>;|lb=6<72;qC8;?4}oc:0?6=:rB?:<5rn`;6>5<5sA>==6saa8494?4|@=<:7p`n9683>7}O<?;0qco68;296~N3>81vbl76:181M2192wem4o50;0xL1063tdj5o4?:3yK037<ugk2o7>52zJ724=zfh3o6=4={I655>{ii0o1<7<tH542?xhf1o0;6?uG4738ykgf83:1>vF;609~jdg62909wE:91:med4=838pD98>;|lbe6<72;qC8;?4}ocb0?6=:rB?:<5rn`c6>5<5sA>==6saa`494?4|@=<:7p`na683>7}O<?;0qcon8;296~N3>81vblo6:181M2192wemlo50;0xL1063tdjmo4?:3yK037<ugkjo7>52zJ724=zf12;6=4>{I655>{i1821<7?tH542?xh>900;6<uG4738yk?6i3:1=vF;609~j<7e290:wE:91:m=4e=83;pD98>;|l:5a<728qC8;?4}o;2a?6=9rB?:<5rn83e>5<6sA>==6sa93294?7|@=<:7p`62083>4}O<?;0qc7=2;295~N3>81vb4<<:182M2192we5?:50;3xL1063td2>84?:0yK037<ug39:7>51zJ724=zf08<6=4>{I655>{i1;21<7?tH542?xh>:00;6<uG4738yk?5i3:1=vF;609~j<4e290:wE:91:m=7e=83;pD98>;|l:6a<728qC8;?4}o;1a?6=9rB?:<5rn80e>5<6sA>==6sa92294?7|@=<:7p`63083>4}O<?;0qc7<2;295~N3>81vb4=<:182M2192we5>:50;3xL1063td2?84?:0yK037<ug38:7>51zJ724=zf09<6=4>{I655>{i1:21<7?tH542?xh>;00;6<uG4738yk?4i3:1=vF;609~j<5e290:wE:91:m=6e=83;pD98>;|l:7a<728qC8;?4}o;0a?6=9rB?:<5rn81e>5<6sA>==6sa95294?7|@=<:7p`64083>4}O<?;0qc7;2;295~N3>81vb4:<:182M2192we59:50;3xL1063td2884?:0yK037<ug3?:7>51zJ724=zf0><6=4>{I655>{i1=21<7?tH542?xh><00;6<uG4738yk?3i3:1=vF;609~j<2e290:wE:91:m=1e=83;pD98>;|l:0a<728qC8;?4}o;7a?6=9rB?:<5rn86e>5<6sA>==6sa94294?7|@=<:7p`65083>4}O<?;0qc7:2;295~N3>81vb4;<:182M2192we58:50;3xL1063td2984?:0yK037<ug3>:7>51zJ724=zf0?<6=4>{I655>{i1<21<7?tH542?xh>=00;6<uG4738yk?2i3:1=vF;609~j<3e290:wE:91:m=0e=83;pD98>;|l:1a<728qC8;?4}o;6a?6=9rB?:<5rn87e>5<6sA>==6sa97294?7|@=<:7p`66083>4}O<?;0qc792;295~N3>81vb48<:182M2192we5;:50;3xL1063td2:84?:0yK037<ug3=:7>51zJ724=zf0<<6=4>{I655>{i1?21<7?tH542?xh>>00;6<uG4738yk?1i3:1=vF;609~j<0e290:wE:91:m=3e=83;pD98>;|l:2a<728qC8;?4}o;5a?6=9rB?:<5rn84e>5<6sA>==6sa96294?7|@=<:7p`67083>4}O<?;0qc782;295~N3>81vb49<:182M2192we5::50;3xL1063td2;84?:0yK037<ug3<:7>51zJ724=zf0=<6=4>{I655>{i1>21<7?tH542?xh>?00;6<uG4738yk?0i3:1=vF;609~j<1e290:wE:91:~yxFGKri??7jl0`7g=4{GHKq;qMN_{|BC
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/synplify.prj b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/synplify.prj
deleted file mode 100644
index 5c9b8dd..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/synplify.prj
+++ /dev/null
@@ -1,101 +0,0 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : synplify.prj 
-## /___/   /\     
-## \   \  /  \
-##  \___\/\___\
-##
-##
-## synplify.prj
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-add_file -vhdl "../example_design/mgt_usrclk_source_mmcm.vhd"
-add_file -vhdl "../example_design/gtxvirtex6fee80_tx_sync.vhd"
-add_file -vhdl "../example_design/gtxvirtex6fee80_rx_sync.vhd"
-add_file -vhdl "../example_design/double_reset.vhd"
-add_file -vhdl "../example_design/frame_gen.vhd"
-add_file -vhdl "../example_design/frame_check.vhd"
-add_file -vhdl "../../gtxvirtex6fee80_gtx.vhd"
-add_file -vhdl "../../gtxvirtex6fee80.vhd"
-add_file -vhdl "../example_design/gtxvirtex6fee80_top.vhd"
-
-add_file -constraint "../example_design/gtxvirtex6fee80_top.sdc"
-
-project -result_file "gtxvirtex6fee80_top.edf"
-set_option -top_module gtxVirtex6FEE80_top
-set_option -technology virtex6
-set_option -part xc6vlx130t
-set_option -package ff484
-set_option -speed_grade -3
-
-#compilation/mapping options
-set_option -default_enum_encoding default
-set_option -symbolic_fsm_compiler 1
-set_option -resource_sharing 1
-
-#map options
-set_option -frequency 160.000
-set_option -fanout_limit 100
-set_option -disable_io_insertion 0
-set_option -pipe 0
-set_option -retiming 0
-
-#simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 0
-set_option -vlog_std v2001
-
-#Do not generate ncf constraints file
-set_option -write_apr_constraint 0
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/tx_phase_align_fifo.ngc b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/tx_phase_align_fifo.ngc
deleted file mode 100644
index 0a643c3..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/tx_phase_align_fifo.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
-$40041<,[o}e~g`n;"2*776&=$:;-*>;1;8456789:;<9>40123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?11934C5>1OH;<=>698;2?45<9'::56?<:NWWTPR=ZMKOH_KLC=31>586j2;>6D@_UU8B@ATFZMKOH_[31583:4d<9<0BB][[:@FGVGQUIMNYY1?;:1<2e>712@D[YY4NDEPBVAGCL[6:97>11c922?OIX\^1MIJ]ASFB@ATK48?1<3?n;049MKVR\3KOH_LXR@FGV972294:n6?9:HLSQQ<FLMXI[_OKDSN?50<76819=95<2;KMTPR=L@KOE1=>:1<20>552@D[YY4KICFJ867=87;>7><5OTVSQQ<CGHND0>?50?36?64=G\^[YY4KOCFL867=87;?794FNQWW>AOWIMC[0>4?>0680?OIX\^1HD^MDHR?7?69991?6D@_UU8TAD:4294:=6:5IORVP?QBIE686=0>1:69MKVR\3]NMX2<:1<2a>2=AGZ^X7~}of]fiur~W}byi~f33;2=60=32@D[YY4rne\ahvsqV~c~h}g_`qpawr;;3:5>85;:HLSQQ<wzfmTi`~{y^vkv`uoWgolmyk33;2=5a=32@D[YY4rne\bpjkW}byi~f33;2=61=32@D[YY4rne\bpjkW}byi~fParqfvq:4294986:5IORVP?vugnUmyabPtipfwmYimnki1=50?36?1<H]]Z^X7J@P@FLT95=87;>794@UURVP?BHXKND\1=50?3;?1<H]]Z^X7jnt`]`kphs4:0;2<l44;MVPUSS2{nThlzn_bmvjq:4294:n6:5OTVSQQ<pzVnjxlQlotlw86<7681==?594;KMTPR=l`d7:>4?>06821<H]]Z^X7j`uu>57?69<2<25;<46@682DGF991=JK8IFGDEBC@1NO<:<68yly304q`a98?=!???;903456?:J9;<=>L3028<7>58929O>M<01A057=?2@D[YY4XECUF82<7689047GAPTV9S@DPME6<6=0>3::9MKVR\3]NNZKZ<683:41<03E^X][[:DA@TDTN\P6<6=0=;847?<?71l1JHI\NRECG@W:76o1JHI\NRECG@W:687l0MIJ]ASFB@AT;984m7LJKR@PGEABU4885j6OKDSCQ@DBCZ5;82k5NDEPBVAGCL[6:83?>;@FGVDTCIMNY0<;50?d8EABUI[NJHI\314<f?DBCZHXOMIJ]<0<f?DBCZHXOMIJ]<3<f?DBCZHXOMIJ]<2<f?DBCZHXOMIJ]<5<f?DBCZHXOMIJ]<4<f?DBCZHXOMIJ]<7<f?DBCZHXOMIJ]<6<f?DBCZHXOMIJ]<9<f?DBCZHXOMIJ]<8<e?DBCZHXOMIJ]L=2=55=FLMXJ^IOKDSN?558682KOH_O]D@FGVI:697;;7LJKR@PGEABUD5;92<>4AEFQEWBFLMXG0<=1119B@ATFZMKOH_B315<26>GCL[KYHLJKRM>21?69991JHI\NRECG@WJ;9<4m7LJKR@PGEABUD5;5j6OKDSCQ@DBCZE692k5NDEPBVAGCL[F7?3h4AEFQEWBFLMXG090i;@FGVDTCIMNY@1;1f:CG@WGULHNO^A29>g9B@ATFZMKOH_B37?d8EABUI[NJHI\C<9<e?DBCZHXOMIJ]L=;=b>GCL[KYHLJKRT>3:46<IMNYM_JNDEPV8469991JHI\NRECG@WS;984:<6OKDSCQ@DBCZ\6:>3??;@FGVDTCIMNYY1?<>008EABUI[NJHI\Z<0694;773HNO^L\KAEFQQ9736o1JHI\NRECG@WS;97l0MIJ]ASFB@ATR4;4m7LJKR@PGEABU]595j6OKDSCQ@DBCZ\6?2k5NDEPBVAGCL[_793h4AEFQEWBFLMX^0;0i;@FGVDTCIMNYY191f:CG@WGULHNO^X27>g9B@ATFZMKOH_[39?g8EABUJ^XJHI\30?d8EABUJ^XJHI\311<e?DBCZK]YMIJ]<03=b>GCL[H\^LJKR=31:c=FLMXI[_OKDS>27;`<IMNYNZ\NDEP?518692KOH_LXR@FGV972294m7LJKRCUQEABU48?5i6OKDS@TVDBCZ5;5i6OKDS@TVDBCZ585i6OKDS@TVDBCZ595i6OKDS@TVDBCZ5>5i6OKDS@TVDBCZ5?5i6OKDS@TVDBCZ5<5i6OKDS@TVDBCZ5=5i6OKDS@TVDBCZ525i6OKDS@TVDBCZ535j6OKDS@TVDBCZE6;2<>4AEFQFRTFLMXG0<>1119B@ATE_[KOH_B310<24>GCL[H\^LJKRM>26;773HNO^OY]AEFQH97468:0MIJ]BVPB@ATK48>5=?5NDEPASWGCL[F7=84?>028EABUJ^XJHI\C<07=b>GCL[H\^LJKRM>2:c=FLMXI[_OKDSN?6;`<IMNYNZ\NDEPO868a3HNO^OY]AEFQH929n2KOH_LXR@FGVI:26o1JHI\MWSCG@WJ;>7l0MIJ]BVPB@ATK4>4m7LJKRCUQEABUD525j6OKDS@TVDBCZE622k5NDEPASWGCL[_7<3??;@FGVGQUIMNYY1??>028EABUJ^XJHI\Z<03=55=FLMXI[_OKDSW?578682KOH_LXR@FGVP:6;7;97LJKRCUQEABU]5;?6=0>0:CG@WDPZHNO^X2>4?d8EABUJ^XJHI\Z<0<e?DBCZK]YMIJ]U=0=b>GCL[H\^LJKRT>0:c=FLMXI[_OKDSW?0;`<IMNYNZ\NDEPV808a3HNO^OY]AEFQQ909n2KOH_LXR@FGVP:06o1JHI\MWSCG@WS;07l0MIJ]BVPB@ATR40487LBC9:CP]KEXZLM87O[=8:@VWZOINF;0Ol5LARAB@@OIIh1HM^MNDDKMFg=DIZIJHHAZT@`8GDUDIMODYYL=;BG26>EOMJAT@DMJNRG\P\VB12IGGL\KCMIb?FJLI[NH@FBn;BNHEWBDDB_27NBDBVP@HNg<KEAI[_MCKMc8GIME_[IGGX=4CMP:?FIJE@^_II?;;BMQAZABFLXJXDAA_HLEK2=DZLK_II?4D69GFLRBZ[20HDOKI=2==>BNIMC7==06;EKB@L:69730HDOKI=31:<=CAHNB0<=19:FJEAO;9=427IGNDH>21;?<L@KOE1?9>89GMDBN48=556JFAEK?5=8>3MCJHD2>9?:8@LGCA5;556JFAEK?658>3MCJHD2=1?;8@LGCA589245KI@FJ875912NBMIG325<:?AOFL@699374DHCGM941601OELJF<35==>BNIMC7>506;EKB@L:51720HDOKI=0==>BNIMC7?=0m;EKB@L:493:556JFAEK?748?3MCJHD2<>99GMDBN4=437IGNDH>6:==CAHNB0;07;EKB@L:0611OELJF<9<;?AOFL@62255KICFJ858>3MCIHD2>0?;8@LDCA5;:245KICFJ844912NBNIG312<:?AOEL@6:8374DH@GM972601OEOJF<04==>BNJMC7=:06;EKA@L:60730HDLKI=3::==CAKNB0<06;EKA@L:58730HDLKI=02:<=CAKNB0?<19:FJFAO;::427IGMDH>10;?<L@HOE1<:>89GMGBN4;<556JFBEK?628>3MCIHD2=8?;8@LDCA582255KICFJ878>3MCIHD2<0?`8@LDCA59:6=06;EKA@L:49720HDLKI=1=<>BNJMC78364DH@GM93902NBNIG36?:8@LDCA5=546JFBEK?<;><L@HOE171a:FJTDBNX5:5m6JFP@FJT979i2NB\LJFP=0=g>BNXHNB\1=50?c8@LVFL@Z7?3o4DHRA@LV;87k0HD^MDHR?5;g<L@ZIHD^32?a8@LVEL@Z7?7>1a:FJTGBNX59546J@AEM?4;?<LFKOC1??>89GKDBH48;556J@AEM?578>3MEJHB2>3?;8@JGCG5;?245KO@FL843912NDMIA317<:?AIFLF6:;374DNCGK97?601OCLJ@<0;=<>BHIME7=374DNCGK947601OCLJ@<33==>BHIME7>?06;EMB@J:5;730HBOKO=07:<=CGHND0?;19:FLEAI;:?427IANDN>13;?<LFKOC1<7>89GKDBH4;3546J@AEM?6;?<LFKOC1=?>c9GKDBH4:;1<374DNCGK956611OCLJ@<2<;?AIFLF6?255KO@FL808?3MEJHB29>99GKDBH4>437IANDN>;:==CGHND0408;EMB[WC@02NDNIA30?;8@JDCG5;;245KOCFL847912NDNIA313<:?AIELF6:?374DN@GK973601OCOJ@<07==>BHJME7=;06;EMA@J:6?730HBLKO=3;:<=CGKND0<718:FLFAI;9730HBLKO=03:<=CGKND0??19:FLFAI;:;427IAMDN>17;?<LFHOC1<;>89GKGBH4;?556J@BEM?638>3MEIHB2=7?;8@JDCG583245KOCFL87?902NDNIA32?;8@JDCG59;2o5KOCFL867=8730HBLKO=12:==CGKND0>07;EMA@J:3611OCOJ@<4<;?AIELF6=255KOCFL828?3MEIHB27>99GKGBH404<7IAM_SGDe>BHXHND\1>1a:FLTDBHX5;5m6J@P@FLT949k2ND\LJ@P=194;g<LFZJHB^33?c8@JVELFZ7<3o4DNRA@JV;97k0HB^MDNR?6;e<LFZIHB^33;2=e>BHXKND\1=1c:G@GUGUA]S7<3m4EBASEWOSQ5;5o6KLCQCQMQ_;:7i0INM_ASKW]959k2OHO]O]IU[?0;e<MJI[M_G[Y=7=g>CDKYKYEYW36?g8AFEWI[C_U1950?a8AFEWI[C_U1917:GMEWBBF11NBL\KEON;?@HFZMOEY:5JNCUQAK><MGH\^H@C8:GMFRTBF\h0ICQJCB]QADBd3LDTINMPWSKWA0=AIEYN>6HK3:DGG1=ALJO87KJ_4:DGT@773OL9<KH?0321456788:0JKHIFGDE3A1CNO=O=6I<;FLG5>O53@:97D?=;H01?L553@>97D;7;HLJPUY7811BBDZ__13;?LHN\YU;>55FNHVS[55?3@DBX]Q?499JJLRWW9?37D@FTQ]32==NF@^[S=97;HLJPUY7011BBDZ__1;;?LHN\YU;M55FNHVS[5D?3@DBX]Q?C99JJLRWW9N37D@FTQ]3A==NF@^[S=H6;HLJPVRF\L=0ECG[_124?LHN\V::;6GAIU]362=NF@^T<>94IOKW[5203@DBXR>:7:KMMQY7>>1BBDZP0658MKOSW92<7D@FT^2:3>OIA]U;M:5FNHV\4G1<AGC_S=M8;HLJPZ6C?2CEEYQ?E69JJLRX8O=0ECG[_024?LHN\V;:;6GAIU]262=NF@^T=>94IOKW[4203@DBXR?:7:KMMQY6>>1BBDZP1658MKOSW82<7D@FT^3:3>OIA]U:M:5FNHV\5G1<AGC_S<M8;HLJPZ7C?2CEEYQ>E69JJLRX9O=0ECG[_324?LHN\V8:;6GAIU]162=NF@^T>>94IOKW[7203@DBXR<:7:KMMQY5>>1BBDZP2658MKOSW;2<7D@FT^0:3>OIA]U9M:5FNHV\6G1<AGC_S?M8;HLJPZ4C?2CEEYQ=E69JJLRX:O=0ECG[_224?LHN\V9:;6GAIU]062=NF@^T?>94IOKW[6203@DBXR=:7:KMMQY4>>1BBDZP3658MKOSW:2<7D@FT^1:3>OIA]U8M:5FNHV\7G1<AGC_S>M8;HLJPZ5C?2CEEYQ<E69JJLRX;O=0ECG[_524?LHN\V>:;6GAIU]762=NF@^T8>94IOKW[1203@DBXR::7:KMMQY3>>1BBDZP4658MKOSW=2<7D@FT^6:3>OIA]U?M:5FNHV\0G1<AGC_S9M8;HLJPZ2C?2CEEYQ;E69JJLRX<O=0ECG[_424?LHN\V?:;6GAIU]662=NF@^T9>94IOKW[0203@DBXR;:7:KMMQY2>>1BBDZP5658MKOSW<2<7D@FT^7:3>OIA]U>M:5FNHV\1G1<AGC_S8M8;HLJPZ3C?2CEEYQ:E69JJLRX=O=0ECG[_724?LHN\V<:;6GAIU]562=NF@^T:>94IOKW[3203@DBXR8:7:KMMQY1>>1BBDZP6658MKOSW?2<7D@FT^4:3>OIA]U=M:5FNHV\2G1<AGC_S;M8;HLJPZ0C?2CEEYQ9E69JJLRX>O=0ECG[_624?LHN\V=:;6GAIU]462=NF@^T;>94IOKW[2203@DBXR9:7:KMMQY0>>1BBDZP7658MKOSW>2<7D@FT^5:3>OIA]U<M:5FNHV\3G1<AGC_S:M8;HLJPZ1C?2CEEYQ8E69JJLRX?O<0ECG[_@48MKOSWK30ECG[_GKOAa=NFCOHXILFTDPQ`>OIBLI__OG[ESP0?LHQ>2FDMIKK7:NLCLEFD=1GYY<;;MWW71=K]]>?7A[[649NWBIIk2Gjfb|Yesqjkke<E`dd~[k}shmm7>H79;1E=95A1167?K77==1E==8;;O3331=I992?7C??929M542<F8;;86@>1068J475<2D:=>:4N0370>H69<>0B<?94:L2522<F8;386@>1818J4433G;9<95A1337?K75:=1E=?=;;O3101=I9;??7C?=659M57133G;9495A13;0?K74<2D:?=:4N0120>H6;;>0B<=<4:L2712<F89>86@>3768J450<2D:?5:4N01:7>H6<=1E=9>;;O3751=I9=8?7C?;359M51233G;?995A1547?K73?=1E=96;;O37=6=I9<>0B<;?4:L2142<F8?986@>5268J433<2D:98:4N0750>H6=>>0B<;74:L21<5<F8<?7C?9059M53733G;=>95A1717?K71<=1E=;;;;O3521=I9?=?7C?9829M522<F8=9?6@>829M5<4<F;90B?><;O027>H5::1E>>=4N360?K42;2D9:>5A2618J7>43G82?6@<029M745<F:887C=<3:L006=I;<90B>8<;O147>H40:1E?4<4N518J1643G>:?6@;229M065<F=>87C::3:L726=I<>90B96<;O6:6>H2;2D><>5A5018J0443G?8?6@:429M105<F<<87C;83:L6<6=I=090B;><;O427>H1::1E:>=4N760?K02;2D=:>5A6618J3>43G<2>6@83:L446=I?890B:<<;O507>H0<:1E;8=4N641?K?a3GHTNX]_IO]SVJVT?2DNXZA]K59MKKC63F80CF?4P59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ9:RH[MJR\GG87]\J1:S;?WGJJ:<N=k5]AL]F\QCI[@EESLh4R@O\A]RBFZCDBRL7;SCN[HICMj1YHLJKRDA@858c3[NJHI\JCB>24;b<ZMKOH_KLC=32:c=ULHNO^HML<0094;b<ZMKOH_KLC=31:f=ULHNO^HML<0<`?WBFLMXNON2=>b9Q@DBCZLIH0>0l;SFB@ATBKJ6?2n5]D@FGV@ED4<4h7_JNDEPFGF:16j1YHLJKRDA@828d3[NJHI\JCB>;:f=ULHNO^HML<8<b?WCFLVLB^^Zl;SGB@ZQNL]BTMn5]E@F\SLBS@VH>7_KHCD`8V@ADMHXNKNKl;SGDG@GUMNIN@n5]EFAFEWC@KL_=7_KHCD@4?WC@KLHG;6\JGBGAQ`=UMNIGGL\KRBNHH`=UMNIGGL\KRBNHQ==UMNIGGOB7;SGDGIME]m1Y_Y\NM@PPPWGJm2XXX_OBASQWVDKKm2XXX_OBASQWVDKR?2XXX_OBB99QWQTFEKF37_][R@OAQa=U[]XNKL\\TSGDa>TT\[OLM_][RDEOa>TT\[OLM_][RDEV3>TT\[OLN55]SUPFCGJ?3[Y_^HIMU038VVRUMNU[^DA]IU[\E47<ZZ^YIJQ_RHMQMQ_XJ11XM[KKAUC4?VDN\LXY?6]KP018WLKXKFFGE^G@N^AKAFM?3ZAB\R^FN79PKPTDM>1X^[OC_@58WWPFDVH?7Y\ZE59W]UC5<2_;#j|i.sd,cf~)keas#@v`r^l3452Xpf6;2<<;;T2,cw`)zo%lou lljz,I}iuWg:;<8Qwo=2=572<]9%l~k }f.e`|+ekcq%Ftb|Pn1232Z~h494:>95Z0.eqb+ta'nis"nbdx.O{kwYi899;Sua30?310>S7'nxm"h gbz-gim'Drd~R`?023\|j:7688?7X> gsd-vc)`kq$h`fv Mymq[k67;;Usc1>110:8Q5)`zo$yj"ilx/aoo})i89:?=55Z0.eqb+ta'nis"nbdx.l3453602_;#j|i.sd,cf~)keas#c>?073;?P6(o{l%~k!hcy,`hn~(f9:9><74U1-dvc(un&mht#mcky-m45459820Y=!hrg,qb*adp'iggu!a01005<=R8&myj#|i/fa{*fjlp&d;<?=>199V4*aun'xm#jmw.bnh|*h78;>:46[?/fpe*w`(ojr%oaew/o23757?3\:$kh!rg-dg}(ddbr$b=><10:8Q5)`zo$yj"ilx/aoo})i8999=55Z0.eqb+ta'nis"nbdx.l341>612_;#j|i.sd,cf~)keas#c>?4932<>S7'nxm"h gbz-gim'g:;84?6;T2,cw`)zo%lou lljz,j56318;37X> gsd-vc)`kq$h`fv n126477<]9%l~k }f.e`|+ekcq%yhR~ats]amk:76;;0Y=!hrg,qb*adp'iggu!}d^rmpwYeag6:2??4U1-dvc(un&mht#mcky-q`Zvi|{Uiec2=>338Q5)`zo$yj"ilx/aoo})ulVzexQmio>0:76<]9%l~k }f.e`|+ekcq%yhR~ats]amkY7:91^<"i}f/pe+be&jf`t"|k_qlwvZdnfV;9<6[?/fpe*w`(ojr%oaew/sf\tkruWkceS?<?;T2,cw`)zo%lou lljz,vaYwf}xTnd`P3328Q5)`zo$yj"ilx/aoo})ulVzexQhc=2=65=R8&myj#|i/fa{*fjlp&xoS}`{r^e`848582_;#j|i.sd,cf~)keas#jPpovq[be;:78;7X> gsd-vc)`kq$h`fv re]sjqtXoj682<h4U1-dvc(un&mht#mcky-q`Zvi|{UloR>>f:W3+bta&{l$knv!cmi{+wbXxg~ySjmP10d8Q5)`zo$yj"ilx/aoo})ulVzexQhc^02b>S7'nxm"h gbz-gim'{nT|cz}_fa\770<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlm7<3<9;T2,cw`)zo%lou lljz,vaYwf}xTknQnssgd8485>2_;#j|i.sd,cf~)keas#jPpovq[beXizxnk1<1279V4*aun'xm#jmw.bnh|*tcWyd~Ril_`qqab:46;?0Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hiP0378Q5)`zo$yj"ilx/aoo})ulVzexQhc^cpv`aX9;?0Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hiP2378Q5)`zo$yj"ilx/aoo})ulVzexQhc^cpv`aX;;30Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hiPd0>3:7?<]9%l~k }f.e`|+ekcq%yhR~ats]dgZgtzlmTh<2>>3;8Q5)`zo$yj"ilx/aoo})ulVzexQhc^cpv`aXl8692?74U1-dvc(un&mht#mcky-q`Zvi|{UloRo|rde\`4:46;20Y=!hrg,qb*adp'iggu!}d^rmpwY`kVkx~hiPd0]36==R8&myj#|i/fa{*fjlp&xoS}`{r^e`[duumnUo=R?=8:W3+bta&{l$knv!cmi{+wbXxg~ySjmParpfcZb6W;837X> gsd-vc)`kq$h`fv re]sjqtXojUjkh_e3\77><]9%l~k }f.e`|+ekcq%yii{le^zlvZ769Vrd0=0>299V4*aun'xm#jmw.bnh|*tbl|inSua}_332[}i;87;9=6[?/fpe*w`(ojr%oaew/vp\tkruWkce0=0=1:W3+bta&{l$knv!cmi{+rtXxg~ySoga<0<15>S7'nxm"h gbz-gim'~xT|cz}_ckm878592_;#j|i.sd,cf~)keas#z|Ppovq[goi4:49<6[?/fpe*w`(ojr%oaew/vp\tkruWkceS=<?;T2,cw`)zo%lou lljz,swYwf}xTnd`P1328Q5)`zo$yj"ilx/aoo})pzVzexQmio]165=R8&myj#|i/fa{*fjlp&}yS}`{r^`jjZ5582_;#j|i.sd,cf~)keas#z|Ppovq[be;878;7X> gsd-vc)`kq$h`fv ws]sjqtXoj6:2?>4U1-dvc(un&mht#mcky-tvZvi|{Ulo1<1219V4*aun'xm#jmw.bnh|*quWyd~Ril<2<2b>S7'nxm"h gbz-gim'~xT|cz}_fa\44`<]9%l~k }f.e`|+ekcq%|~R~ats]dgZ76n2_;#j|i.sd,cf~)keas#z|Ppovq[beX:8l0Y=!hrg,qb*adp'iggu!xr^rmpwY`kV99:6[?/fpe*w`(ojr%oaew/vp\tkruWniTm~|jg=2=63=R8&myj#|i/fa{*fjlp&}yS}`{r^e`[duumn6:2?84U1-dvc(un&mht#mcky-tvZvi|{UloRo|rde?6;413\:$kh!rg-dg}(ddbr${Qnup\cfYf{{ol0>0=5:W3+bta&{l$knv!cmi{+rtXxg~ySjmParpfcZ65=2_;#j|i.sd,cf~)keas#z|Ppovq[beXizxnkR?=5:W3+bta&{l$knv!cmi{+rtXxg~ySjmParpfcZ45=2_;#j|i.sd,cf~)keas#z|Ppovq[beXizxnkR==9:W3+bta&{l$knv!cmi{+rtXxg~ySjmParpfcZb6494956[?/fpe*w`(ojr%oaew/vp\tkruWniTm~|jg^f2848512_;#j|i.sd,cf~)keas#z|Ppovq[beXizxnkRj><3<1=>S7'nxm"h gbz-gim'~xT|cz}_fa\evtboVn:0>0=8:W3+bta&{l$knv!cmi{+rtXxg~ySjmParpfcZb6W9837X> gsd-vc)`kq$h`fv ws]sjqtXojUjkh_e3\57><]9%l~k }f.e`|+ekcq%|~R~ats]dgZgtzlmTh<Q=299V4*aun'xm#jmw.bnh|*quWyd~Ril_`qqabYc9V99<6[?/fpe*w`(oe:%~i!hr`q-vvrt'g:;?=<8;T2,cw`)zo%l`= }d.eqev(u{}y$b=><0037[VQ7::1^<"i}f/pe+bj7&{n$ko|.sqww*h78:::??<=;T2,cw`)zo%l`= }d.eqev(u{}y$b=><05615>S7'nxm"h gm2-va)`zhy%~~z|/o237515:2_;#j|i.sd,ci6)zm%l~l}!rrvp+k67;93<>45Z0.eqb+ta'nf;"j gscp*wus{&xjaRkbpu{\bgYn:?1^<"i}f/pe+bj7&{n$ko|.sqww*tfeVof|ywPi0f8Q5)`zo$yj"ic0/pg+wgjW{nTicQf13;8Q5)`zo$yj"ic0/pg+wvi|{%FaxvPn122147XAG\T<?=4U1-dvc(un&mg<#|k/srmpw)Je|rTb=>>53317>S7'nxm"h gm2-va)uxg~y#jm?.bmvjq:76;90Y=!hrg,qb*ak8'xo#~ats-dg5(dg|d0<0=3:W3+bta&{l$ka>!re-qtkru'ni;"naznu>1:75<]9%l~k }f.eo4+tc'{zex!hc1,`kphs4:49>6[?/fpe*w`(oe:%~i!}povq+be7&je~byQ?239V4*aun'xm#jb?.sf,vuhsz&mh<#m`uov\574<]9%l~k }f.eo4+tc'{zex!hc1,`kphsW;897X> gsd-vc)`d9$yh"|nup,cf6)kfexR==6:W3+bta&{l$ka>!re-qtkru'ni;"naznu]g5969:?1^<"i}f/pe+bj7&{n$~}`{r.e`4+eh}g~Th<2>>348Q5)`zo$yj"ic0/pg+wvi|{%lo= lotlw[a7;:78=7X> gsd-vc)`d9$yh"|nup,cf6)kfexRj><2<11>S7'nxm"h gm2-va)uxg~y#jm?.bmvjqYc9V:996[?/fpe*w`(oe:%~i!}povq+be7&je~byQk1^311>S7'nxm"h gm2-va)uxg~y#jm?.bmvjqYc9V8996[?/fpe*w`(oe:%~i!}povq+be7&je~byQk1^12b>S7'nxm"h gm2-va)uxg~y#c>?14>3:4`<]9%l~k }f.eo4+tc'{zex!a01368486n2_;#j|i.sd,ci6)zm%y|cz}/o2350:56;:0Y=!hrg,qb*ak8'xo#~ats-m45724;4:=k5Z0.eqb+ta'nf;"j rqlwv*h788?7?3<?;T2,cw`)zo%l`= }d.psjqt(f9::91=11328Q5)`zo$yj"ic0/uq+bqf{'}xx~!a011366=R8&myj#|i/fn3*rt(o~kx"z}{s.l34666:<8<7X> gsd-vc)`d9$|~"ixar,twqu(f9:8<<<:_RU362=R8&myj#|i/fn3*rt(o~kx"z}{s.l34666:<UX[<<=;T2,cw`)zo%l`= xr.etev(p{}y$b=><0931<>S7'nxm"h gm2-sw)`hy%{~z|/scn[cskdVliSd<:;T2,cw`)zo%l`= xr.etev(p{}y$~lcPftno[l7c3\:$kh!rg-dh5(pz&xjaRy}_dl\m44>3\:$kh!rg-dh5(pz&}{by| Mlw{[k679<;:SD@Y_100?P6(o{l%~k!hl1,tv*qwf}x$A`{w_o235046:11^<"i}f/pe+bj7&~x${}`{r.ejg5(`k9$hcx`{<1<1<>S7'nxm"h gm2-sw)pxg~y#jgl0/e`4+eh}g~7=3<7;T2,cw`)zo%l`= xr.usjqt(o`i;"jm?.bmvjq:56;20Y=!hrg,qb*ak8'}y#z~ats-dmf6)oj:%ob{at=1=62=R8&myj#|i/fn3*rt(yd~"ifc1,dg5(dg|dS=<8;T2,cw`)zo%l`= xr.usjqt(o`i;"jm?.bmvjqY6:>1^<"i}f/pe+bj7&~x${}`{r.ejg5(`k9$hcx`{_304?P6(o{l%~k!hl1,tv*qwf}x$kdm?.fa3*firf}U8>o5Z0.eqb+ta'nf;"z| wqlwv*ank9$lo= lotlw[a7;878i7X> gsd-vc)`d9$|~"ynup,cle7&ni;"naznu]g5979:k1^<"i}f/pe+bj7&~x${}`{r.ejg5(`k9$hcx`{_e3?6;4e3\:$kh!rg-dh5(pz&}{by| gha3*be7&je~byQk1=1=6d=R8&myj#|i/fn3*rt(yd~"ifc1,dg5(dg|dSi?P03c8Q5)`zo$yj"ic0/uq+rvi|{%len>!gb2-gjsi|Vn:S<<n;T2,cw`)zo%l`= xr.usjqt(o`i;"jm?.bmvjqYc9V89m6[?/fpe*w`(oe:%{!xpovq+bod8'mh<#m`uov\`4Y4:k1^<"i}f/pe+bj7&~x${}`{r.ejg5(`k9$hcx`{_e0?4;4e3\:$kh!rg-dh5(pz&}{by| gha3*be7&je~byQk2=3=6g=R8&myj#|i/fn3*rt(yd~"ifc1,dg5(dg|dSi<32?0a?P6(o{l%~k!hl1,tv*qwf}x$kdm?.fa3*firf}Uo>1=12`9V4*aun'xm#jb?.vp,suhsz&mbo= hc1,`kphsWm8T<?o4U1-dvc(un&mg<#y}/vrmpw)`aj:%kn>!cnwmpZb5W88j7X> gsd-vc)`d9$|~"ynup,cle7&ni;"naznu]g6Z45i2_;#j|i.sd,ci6){%||cz}/fk`4+ad8'idyczPd3]05c=R8&myj#|i/fn3*rt(yd~"`?007?4;7a3\:$kh!rg-dh5(pz&}{by| n12219799o1^<"i}f/pe+bj7&~x${}`{r.l3443;:78;7X> gsd-vc)`d9$|~"ynup,j566=585=<h4U1-dvc(un&mg<#y}/vrmpw)i89;>0>0=0:W3+bta&{l$ka>!ws-ttkru'g:;=82<>055?P6(o{l%~k!bel-dfh(`jdm%kocha/ldafe)jdm$naePmdo\c`hbzh~d~"xnlhf-gvru'{kf`ba[1_-vdk)z&|=Scafnhv-vdk([MZ%[DJJ_QPJI60)zhg:j6[?/fpe*w`(elg$koc!tlr\vdkXzmUnb?>4U1-dvc(un&gna"imm/vntZtfeVxoSh`>129V4*aun'xm#ob_sf\ak743\:$kh!rg-qehYpzVoe>n5Z0.eqb+ta'{ynae nfuq`wus&nxxx#|k_sqw[wc`4949o6[?/fpe*w`(zz~i`f!agvpgvvr)o{y"jPrrv\v`a;978h7X> gsd-vc)u{}hgg"`hwsfqwq(`zz~%~iQ}su]qab:56;h0Y=!hrg,qb*tt|kf`#cixreppp+au{}$yhR||t^pfcZ65j2_;#j|i.sd,vvredb%ekz|krrv-cwus&{nT~~zPrde\57d<]9%l~k }f.pppgjl'gm|~i||t/eqwq(ulVxxxR|jg^01g>S7'nxm"h rrvahn)io~xo~~z!gsqw*rtXzz~T~hi30?0`?P6(o{l%~k!}su`oo*h`{nyy hrrv-swYu{}Uyij2>>3`8Q5)`zo$yj"||tcnh+kapzmxxx#i}su,tvZtt|VxnkR>=b:W3+bta&{l$~~zmlj-mcrtczz~%k}{.vp\vvrXzlmT=<j4U1-dvc(un&xxxobd/sf\vvrXizxnk?>4U1-dvc(un&xxxobd/sf\vvrXizxnkRj>219V4*aun'xm#}{bmi,vaYu{}Ujkh_e02g>S7'nxm"h rrvahn)ulVxxxRm`mc3g?P6(o{l%~k!}su`oo*tcW{ySnabb03g?P6(o{l%~k!}su`oo*quW{ySl}}ef03?P6(o{l%~k!}su`oo*quW{ySl}}ef]g576<]9%l~k }f.pppgjl'~xT~~zParpfcZb59j1^<"i}f/pe+wusjea${Q}su]`khd6l2_;#j|i.sd,vvredb%|~R||t^alig7f3\YN^ROCI@Q`?PUBZV\B_DLCE29UGF?<^@O\SYW_E79TAD:76?1\IL2>>79TAD:5611\IL2<:1<5?RCF4:4<7ZKNL=2=3>QBIE6:2:5XE@N?6;?<_LKG0>4?>69TADJ;;7=0[HOZ<1<4?RCF]5;5;6YJAT>1:<=PMH_7?7>17:UFEP:4611\IOYJ<1<;?RCE_L6:255XECUF878?3^OI[H2<>99TAGQB4=437ZKMWD>6:==PMK]N0;0n;VGAS@:029437ZKMWD>4:<=PMK]N@1>19:UFFRCK48427ZKMWDN?6;?<_LH\IA2<>89TAGQBD5>556YJBVGO808>3^OI[HB36?`8S@DPME6<6=06;VGAS@J;?730[HLXET>3:<=PMK]NY1?19:UFFRCR4;427ZKMWDW?7;?<_LH\IX2;>89TAGQB]5?556YJBVGV838e3^OI[H[37;2==>QBJ^O^0:0l;VPJP@YJGMOTMn5XRHVF[HICMVHo7Z\FTD]TMAROWHn0[_G[E^UJ@QNXJ8n0TDBFNY/[@G&7&8*XXXL/0/3#EVENA?1S_YBFB69[WQY@FM=0T^ZPVBAa?]YDG[OTECH@6:ZgfZOcn2RodR^}ilTfvvohf8:0TicPM`hlvScu{`ee==5Wdl]Nmkiu^lxxeb`=e:]\[]JIEVUT<RQPU1-dvc(un&mg<#|k/srmpw)i89;>0>0>2d9\[Z^KFDUTS<QP_T2,cw`)zo%l`= xr.usjqt(f9::91=11358[ZY_DGGTSR<P_^W3+bta&{l$knv!cmi{+k67<0;9;6QP_YNMIZYX;VUTY=!hrg,qb*adp'iggu!a01005f=fddexxRkbpu{a?djjgz~Tjxbc6:`bgnswl2hjof{_lcqo`t43jf`h6jnt`]`kphs 9#o7io{a^alqkr/9 n0hlzn_bmvjq.5!m1omyoPcnwmp-5.n2njxlQlotlw86<76>1ondzjrs48`lh/8 <0hd`'1(58`lh/99#<7iga(03*3>bnf!;9%:5kio*27,1<l`d#=9'8;ekm,43.?2nbb%?9)69gmk.6? =0hd`'19+4?aoi 83":6jfn)0*3>bnf!8;%:5kio*15,1<l`d#>?'8;ekm,75.?2nbb%<;)69gmk.5= =0hd`'27+4?aoi ;=";6jfn)0;-2=cag"95$84dhl+7,1<l`d#?='8;ekm,67.?2nbb%==)69gmk.4; =0hd`'35+4?aoi :?";6jfn)15-2=cag"8;$94dhl+7=/03mce$>7&6:fjj-2.?2nbb%:?)69gmk.39 =0hd`'43+4?aoi =9";6jfn)67-2=cag"?9$94dhl+03/03mce$99&7:fjj-2?!>1oec&;9(48`lh/= =0hd`'51+4?aoi <;";6jfn)71-2=cag">?$94dhl+11/03mce$8;&7:fjj-31!>1oec&:7(58`lh/=1#<7iga(4;*2>bnf!<";6jfn)43-2=cag"==$94dhl+27/03mce$;=&6:fjj-1.>2nbb%6&6:fjj-?.>2nbb1>17:fjj9776>1oec2>1?58`lh;9;4<7iga<01=3>bnf5;?2:5kio>21;1<l`d7=;08;ekm8419?2nbb1?7>69gmk:617<0hd`31?58`lh;:94<7iga<33=3>bnf5892:5kio>17;1<l`d7>908;ekm8739?2nbb1<9>69gmk:5?7=0hd`329<4?aoi4;35:6jfn=0=3>bnf59;2:5kio>05;1<l`d7??08;ekm8659?2nbb1=;>69gmk:4=7=0hd`337<4?aoi4:=5;6jfn=1;:2=cag685384dhl?7;1<l`d78=08;ekm8179?2nbb1:=>69gmk:3;7=0hd`345<4?aoi4=?5;6jfn=65:2=cag6?;394dhl?0=803mce09716:fjj929?2nbb1;?>69gmk:297=0hd`353<4?aoi4<95;6jfn=77:2=cag6>9394dhl?13803mce08917:fjj93?6>1oec2:9?48`lh;=7=0hd`361<4?aoi4?;5;6jfn=41:<=cag6=?7>17:fjj9046?1oec29>79gmk:06?1oec27>79gmk:>6>1ocxz'0(58`jss 8#37iazt)33-==cg|~#=<'7;emvp-75!11ocxz'12+;?air|!;?%55kotv+50/?3me~x%?9)99gkpr/9>#37iazt)3;-==cg|~#=4'8;emvp-4.02ndyy&=0(:8`jss ;;"46j`uu*16,><lf$?=&8:flqq.5< 20hb{{(37*<>bh}}"9:$64dnww,71.02ndyy&=8(:8`jss ;3";6j`uu*0-==cg|~#?='7;emvp-56!11ocxz'33+;?air|!98%55kotv+71/?3me~x%=:)99gkpr/;?#37iazt)14-==cg|~#?5'7;emvp-5>!>1ocxz'4(:8`jss =:"46j`uu*75,><lf$9<&8:flqq.3; 20hb{{(56*<>bh}}"?9$64dnww,10.02ndyy&;7(:8`jss =2"46j`uu*7=,1<lf$8'7;emvp-37!11ocxz'50+;?air|!?9%55kotv+16/?3me~x%;;)99gkpr/=<#37iazt)75-==cg|~#9:'7;emvp-3?!11ocxz'58+4?air|!<"46j`uu*54,><lf$;?&8:flqq.1: 20hb{{(71*3>bh}}"<%:5kotv+<,1<lf$4'8;emvp96902ndyy2>0?:8`jss48;546j`uu>26;><lf0<=18:flqq:6<720hb{{<07=<>bh}}6::364dnww841902ndyy2>8?:8`jss4835;6j`uu>2:==cg|~7>=07;emvp946611ocxz323<;?air|588255kotv?618?3me~x1<:>99gkpr;:?437iazt=04:==cg|~7>507;emvp94>6>1ocxz32?:8`jss4::546j`uu>05;><lf0><18:flqq:4;720hb{{<26=<>bh}}689364dnww860902ndyy2<7?:8`jss4:2546j`uu>0=;1<lf0>07;emvp927611ocxz340<;?air|5>9255kotv?068?3me~x1:;>99gkpr;<<437iazt=65:==cg|~78:07;emvp92?611ocxz348<4?air|5>546j`uu>64;><lf08?18:flqq:2:720hb{{<41=<>bh}}6>8364dnww803902ndyy2:6?:8`jss4<=546j`uu>6<;><lf08717:flqq:2611ocxz361<;?air|5<:255kotv?278f3me~x18<:1<;?air|5<82:5kotv?2;1<lf0:08;emvp9>9?2ndyy26>99f`l`5fnn>7hctx0e?coagVmnbh|ntnp\r0Y4$)Rb`d`w BMQA%Abflxjxb|/10,00>`rden0ecdjcufamqcuzm1bbgkltr`jp`tu?2cexRmck99mcfdraen37bxjrgnlsd=wzfmTi`~{y068twi`Wlg{xtQ{hsgpl-6.9=1{~biPelrw}Zrozlyc$<'>4:rqkbYbey~rSyf}erj+6,733yxdkRkbpu{\pmtb{a"8%<84psmd[`kw|pUdk|h=194;7e3yxdkRkbpu{\pmtb{aUj~k}t)2*5g=wzfmTi`~{y^vkv`uoWhyxiz'1(3a?uthoVof|ywPtipfwmYf{zoyx%<&1c9svjaXmdzuRzgrdqk[dutm{~#?$?k;qplcZcjx}sTxe|jsi]bwvcu|591<3?m;qplcZcjx}sTxe|jsi]mabgsm!:"=o5rne\ahvsqV~c~h}g_ogdeqc/9 ;i7}|`g^gntqX|axneQaefcwa-4.9k1{~biPelrw}ZrozlycSckhaug+7,7c3yxdkRkbpu{\pmtb{aUeijo{e=194;?<x{elSk{cl018twi`Wog`Rzgrdqk,5/6;2zycjQiumn\pmtb{a":%<=4psmd[cskdV~c~h}g(3+27>vugnUmyabPtipfwm.4!8?0|ah_gwohZrozlyc0>4?>0c8twi`Wog`Rzgrdqk[dutm{~#<$?n;qplcZ`rdeUdk|h^cpw`ts 8#:m6~}of]eqijX|axneQnsrgqp-4.9h1{~biPftno[qnumzbTm~}jru*0-4e<x{elSk{cl^vkv`uoWhyxiz33;2=5d=wzfmTjxbc_ujqavnXflmjxh&?)0c8twi`Wog`Rzgrdqk[kc`i}o#=$?n;qplcZ`rdeUdk|h^lfcdrb ;#:m6~}of]eqijX|axneQaefcwa-5.9j1{~biPftno[qnumzbTbhintd>0>5813{nToae>0:pg[agsiVidycz'0(33?wbXlh~jSnaznu*2-46<zmUomyoPcnwmp-4.991yhRjnt`]`kphs :#:>6|k_ecweZeh}g~7?7>15:pg[`h13{nT~~z<;sqw3>uea}oy~95|rrv2b>rjx&Uhk"zw_qjbw`Yfd`meSkgio/ldk45<|qU{dl}j_`njckYaaoe8=6zw_qjbw`Yfd`meSkgio-djbjY`mgoymya}_w7\7)HHFL&ECCK<e99w|ZvoizoTmaghn^djbj*aaoeTkh`jr`vlvZp2W:&poRfns^kmpZekc4:'oRfns^qqwq;7$jUyhRh}ep?2(fYbfhhgiR||t^qzjf;6$jUcm~Q}d^fbpdYdg|d1="l_ekm[roc|a7=8!mPh`q\swYci}kTob{at<2/gZ`rdeUm`li|_sqw[sgk58&hSdcldofjqgsafdTxt~j=3.`[pubWlgiiijjd^pfc86+kV}ySk|jq<3/gZstmVndyyQ}su?2(fYrfmoyjaax_mmt95*dWakxSbxjrgnls86+kVzyiaand^nbp`hdq4;'oRj`uu]tmaro5?>'oRc|gnl\rdj:9%iT~iQkeqvk940+kVoy~b|PiohfgqohfV~r|h3?,b]kevYrfmoyjaax=1.`[mgtWhffc~zPftno95*dWakxS}{=0.`[agsiVidyczPwhfwl82+kVbjRy}_`ah95*dW|ynShml=1.`[fijefdToaalk<2/gZquWhi`Saax=1.`[wbXxg~ySzgkti?7(fYr{lUm{kzPd`vb[firf}7; nQgar]bhhit|Vof|yw20-a\vaYci}kTob{at^uj`qn:<%iTc{k}fmmt[iip59&hSz|Ppovq[roc|a7? nQrne\ahvsqV~r|h3?,b]tvZbf|hUhcx`{_vkgpm;3$jU{~hb`ae]qabu:8%iThb{{_sqw[sgk59&hSeo|_ecweZeh}g~6<!mPpsmd[cskdV~c~h}g_ogdeqcX~hf6=?"l_vp\``vs`4;= nQrne\ahvsqV~c~h}g_ogdeqcX~hf6?!mPpsmd[`kw|pUdk|h^cpw`tsWkg1?"l_icp[sgkam7; nQrne\bpjkW}byi~fParqfvqYqie7:?!m`mqmmakrXfhgn1yvPpicpaZgkandTjdh`,b]ueiocWee|1="l_qpjiZ`nnfUu}k2500{37*dWyxdkRhzlm]w}uc:8%iTahc`rx]w}uc:9%w9h6zw_qjbw`Yfd`meSkgio^djbjY`mgoymya}_w7\7Z~t|V;27x`kesdokr3<~hfbh;5xr^c`o3=pzVigg<>4ws]geqgXkfex%>&119tvZbf|hUhcx`{(0+24>quWmkmRm`uov+6,773~xThlzn_bmvjq.4!880{Qkauc\gjsi|591<3;4ws]fj3=pzVxxxpNOp63f?EF=891J7:51zQbf?2cn3<1=><60059b<64sg9ho7?4n2ag>0=#;jk1?n;4}Rc:>1ba2?0:??7?168e=55<[;::69k9:18277?79>0m5=:4S`;90`0=83;8>4>>7;d:4<=c=8>1<7?51zQbf?2cn3<1=><60059b<643^9h94?:082>`e|[hh18ih56;306<66?3l2<>5+3849654<^:ii6?uz21:95>s5800;7p*=9c81e>d29=0;65953;:4M5><2P2m7<t24810?{#:m219<:4$2a:>1c63`?;i7>5;h715?6=3f>n>7>5;n6f4?6=3`?:n7>5;h724?6=3f>2m7>5$3;g>1b>3g82o7>4;n6:=?6=,;3o69j6;o0:g?7<3f>247>5$3;g>1b>3g82o7<4;n6:3?6=,;3o69j6;o0:g?5<3f>297>5$3;g>1b>3g82o7:4;n6:0?6=,;3o69j6;o0:g?3<3f>2?7>5$3;g>1b>3g82o784;n6:6?6=,;3o69j6;o0:g?1<3f>2=7>5$3;g>1b>3g82o764;n6:4?6=,;3o69j6;o0:g??<3f>3j7>5$3;g>1b>3g82o7o4;n6;a?6=,;3o69j6;o0:g?d<3f>3h7>5$3;g>1b>3g82o7m4;n6;g?6=,;3o69j6;o0:g?b<3f>3m7>5$3;g>1b>3g82o7k4;n6;=?6=,;3o69j6;o0:g?`<3f>347>5$3;g>1b>3g82o7??;:m7<2<72-82h7:k9:l1=f<6921d85850;&1=a<3l01e>4m51398k1>2290/>4j54e;8j7?d28907b:74;29 7?c2=n27c<6c;37?>i30:0;6)<6d;6g=>h51j0:965`49094?"51m0?h45a28a953=<g=2:6=4+28f90a?<f;3h6<94;n64b?6=,;3o69j6;o0:g?7?32e?;h4?:%0:`?2c12d95n4>9:9l02b=83.95i4;d89m6<e=9h10c99l:18'6<b=<m30b?7l:0`8?j20j3:1(?7k:5f:?k4>k3;h76a;7`83>!4>l3>o56`=9b82`>=h<>31<7*=9e87`<=i:0i1=h54o55;>5<#:0n18i74n3;`>4`<3f><;7>5$3;g>1b>3g82o7<?;:m733<72-82h7:k9:l1=f<5921d8::50;&1=a<3l01e>4m52398k114290/>4j54e;8j7?d2;907b:82;29 7?c2=n27c<6c;07?>i3?80;6)<6d;6g=>h51j09965`46294?"51m0?h45a28a963=<g=<m6=4+28f90a?<f;3h6?94;n65a?6=,;3o69j6;o0:g?4?32e?:i4?:%0:`?2c12d95n4=9:9l03e=83.95i4;d89m6<e=:h10c98m:18'6<b=<m30b?7l:3`8?j2113:1(?7k:5f:?k4>k38h76a;6983>!4>l3>o56`=9b81`>=h<?=1<7*=9e87`<=i:0i1>h54o545>5<#:0n18i74n3;`>7`<3f>=97>5$3;g>1b>3g82o7=?;:m721<72-82h7:k9:l1=f<4921d8;=50;&1=a<3l01e>4m53398k105290/>4j54e;8j7?d2:907b:91;29 7?c2=n27c<6c;17?>i3>90;6)<6d;6g=>h51j08965`48f94?"51m0?h45a28a973=<g=3h6=4+28f90a?<f;3h6>94;n6:f?6=,;3o69j6;o0:g?5?32e?5;4?:%0:`?2c12d95n4<9:9l0=d=83.95i4;d89m6<e=;h10c96?:18'6<b=<m30b?7l:2`8?j20=3:1(?7k:5f:?k4>k39h76a;6`83>!4>l3>o56`=9b80`>=h<<l1<7*=9e87`<=i:0i1?h54o57f>5<#:0n18i74n3;`>6`<3`>:57>5$3;g>13?3g82o7>4;h62<?6=,;3o69;7;o0:g?7<3`>:;7>5$3;g>13?3g82o7<4;h622?6=,;3o69;7;o0:g?5<3`>:87>5$3;g>13?3g82o7:4;h627?6=,;3o69;7;o0:g?3<3`>:>7>5$3;g>13?3g82o784;h625?6=,;3o69;7;o0:g?1<3`>:<7>5$3;g>13?3g82o764;h63b?6=,;3o69;7;o0:g??<3`>;i7>5$3;g>13?3g82o7o4;h63`?6=,;3o69;7;o0:g?d<3`>;o7>5$3;g>13?3g82o7m4;h63f?6=,;3o69;7;o0:g?b<3`>;57>5$3;g>13?3g82o7k4;h63<?6=,;3o69;7;o0:g?`<3`>;;7>5$3;g>13?3g82o7??;:k743<72-82h7::8:l1=f<6921b8=;50;&1=a<3=11e>4m51398m163290/>4j544:8j7?d28907d:?3;29 7?c2=?37c<6c;37?>o38;0;6)<6d;66<>h51j0:965f41394?"51m0?955a28a953=<a=:;6=4+28f900><f;3h6<94;h1ea?6=,;3o69;7;o0:g?7?32c8ji4?:%0:`?2202d95n4>9:9j7ce=83.95i4;599m6<e=9h10e>hm:18'6<b=<<20b?7l:0`8?l5ai3:1(?7k:57;?k4>k3;h76g<f883>!4>l3>>46`=9b82`>=n;o21<7*=9e871==i:0i1=h54i2d4>5<#:0n18864n3;`>4`<3`9m:7>5$3;g>13?3g82o7<?;:k0b0<72-82h7::8:l1=f<5921b?k=50;&1=a<3=11e>4m52398m6`5290/>4j544:8j7?d2;907d=i1;29 7?c2=?37c<6c;07?>o4n90;6)<6d;66<>h51j09965f3dd94?"51m0?955a28a963=<a:on6=4+28f900><f;3h6?94;h1f`?6=,;3o69;7;o0:g?4?32c8in4?:%0:`?2202d95n4=9:9j7`d=83.95i4;599m6<e=:h10e>kn:18'6<b=<<20b?7l:3`8?l5b03:1(?7k:57;?k4>k38h76g<e683>!4>l3>>46`=9b81`>=n;l<1<7*=9e871==i:0i1>h54i2g6>5<#:0n18864n3;`>7`<3`9n87>5$3;g>13?3g82o7=?;:k0a6<72-82h7::8:l1=f<4921b?h<50;&1=a<3=11e>4m53398m6c6290/>4j544:8j7?d2:907d=j0;29 7?c2=?37c<6c;17?>o4lo0;6)<6d;66<>h51j08965f40a94?"51m0?955a28a973=<a=;i6=4+28f900><f;3h6>94;h62e?6=,;3o69;7;o0:g?5?32c?=84?:%0:`?2202d95n4<9:9j05g=83.95i4;599m6<e=;h10e>hi:18'6<b=<<20b?7l:2`8?l5a<3:1(?7k:57;?k4>k39h76g<e883>!4>l3>>46`=9b80`>=n;mo1<7*=9e871==i:0i1?h54i2fg>5<#:0n18864n3;`>6`<3`?;47>5;c1:1?6=93:1<vF<959'6a>=;0?0c?7n:188yg71:3:1=7>50zJ0=1=#:m21=;<4o042>5<<uk326=4me;4;>`e|@:3?7W7n:04x5<<603;j6?>51c82g?7c2;?1>94=1;01>72=910:57?n:0`95f<6l38;6?;520816?{#:m219<94$`39143<,hk19<84$3;6>7?>3`>m=7>5$3;g>1`53g82o7>4;h6e4?6=,;3o69h=;o0:g?7<3`>nj7>5$3;g>1`53g82o7<4;h6fa?6=,;3o69h=;o0:g?5<3`>n87>5;h73b?6=3`?:>7>5;n72=?6=3`>no7>5$3;g>1cc3g82o7>4;h6ff?6=,;3o69kk;o0:g?7<3`>nm7>5$3;g>1cc3g82o7<4;h6f=?6=,;3o69kk;o0:g?5<3`?;i7>5;n6f3?6=3`>m:7>5$3;g>1`03g82o7>4;h6e1?6=,;3o69h8;o0:g?7<3`>m87>5$3;g>1`03g82o7<4;h6e7?6=,;3o69h8;o0:g?5<3f9o?7>5;n1ge?6=,;3o6>jm;o0:g?6<3f9o57>5$3;g>6be3g82o7?4;n1g<?6=,;3o6>jm;o0:g?4<3f9o;7>5$3;g>6be3g82o7=4;n6e<?6=3`?9=7>5;h6eg?6=,;3o69hk;o0:g?6<3`>mn7>5$3;g>1`c3g82o7?4;h6ee?6=,;3o69hk;o0:g?4<3`>m57>5$3;g>1`c3g82o7=4;n6f6?6=3f>n<7>5;h72f?6=3`9o97>5;h735?6=,;3o68>=;o0:g?6<3`?;<7>5$3;g>0653g82o7?4;h6eb?6=,;3o68>=;o0:g?4<3`>mi7>5$3;g>0653g82o7=4;h732?6=,;3o68>8;o0:g?6<3`?;97>5$3;g>0603g82o7?4;h730?6=,;3o68>8;o0:g?4<3`?;?7>5$3;g>0603g82o7=4;n1g6?6=3`>n97>5;h1g2?6=3`?9>7>5;n725?6=3f?:m7>5;h724?6=3f>2m7>5$3;g>1b>3g82o7>4;n6:=?6=,;3o69j6;o0:g?7<3f>247>5$3;g>1b>3g82o7<4;n6:3?6=,;3o69j6;o0:g?5<3f>297>5$3;g>1b>3g82o7:4;n6:0?6=,;3o69j6;o0:g?3<3f>2?7>5$3;g>1b>3g82o784;n6:6?6=,;3o69j6;o0:g?1<3f>2=7>5$3;g>1b>3g82o764;n6:4?6=,;3o69j6;o0:g??<3f>3j7>5$3;g>1b>3g82o7o4;n6;a?6=,;3o69j6;o0:g?d<3f>3h7>5$3;g>1b>3g82o7m4;n6;g?6=,;3o69j6;o0:g?b<3f>3m7>5$3;g>1b>3g82o7k4;n6;=?6=,;3o69j6;o0:g?`<3f>347>5$3;g>1b>3g82o7??;:m7<2<72-82h7:k9:l1=f<6921d85850;&1=a<3l01e>4m51398k1>2290/>4j54e;8j7?d28907b:74;29 7?c2=n27c<6c;37?>i30:0;6)<6d;6g=>h51j0:965`49094?"51m0?h45a28a953=<g=2:6=4+28f90a?<f;3h6<94;n64b?6=,;3o69j6;o0:g?7?32e?;h4?:%0:`?2c12d95n4>9:9l02b=83.95i4;d89m6<e=9h10c99l:18'6<b=<m30b?7l:0`8?j20j3:1(?7k:5f:?k4>k3;h76a;7`83>!4>l3>o56`=9b82`>=h<>31<7*=9e87`<=i:0i1=h54o55;>5<#:0n18i74n3;`>4`<3f><;7>5$3;g>1b>3g82o7<?;:m733<72-82h7:k9:l1=f<5921d8::50;&1=a<3l01e>4m52398k114290/>4j54e;8j7?d2;907b:82;29 7?c2=n27c<6c;07?>i3?80;6)<6d;6g=>h51j09965`46294?"51m0?h45a28a963=<g=<m6=4+28f90a?<f;3h6?94;n65a?6=,;3o69j6;o0:g?4?32e?:i4?:%0:`?2c12d95n4=9:9l03e=83.95i4;d89m6<e=:h10c98m:18'6<b=<m30b?7l:3`8?j2113:1(?7k:5f:?k4>k38h76a;6983>!4>l3>o56`=9b81`>=h<?=1<7*=9e87`<=i:0i1>h54o545>5<#:0n18i74n3;`>7`<3f>=97>5$3;g>1b>3g82o7=?;:m721<72-82h7:k9:l1=f<4921d8;=50;&1=a<3l01e>4m53398k105290/>4j54e;8j7?d2:907b:91;29 7?c2=n27c<6c;17?>i3>90;6)<6d;6g=>h51j08965`48f94?"51m0?h45a28a973=<g=3h6=4+28f90a?<f;3h6>94;n6:f?6=,;3o69j6;o0:g?5?32e?5;4?:%0:`?2c12d95n4<9:9l0=d=83.95i4;d89m6<e=;h10c96?:18'6<b=<m30b?7l:2`8?j20=3:1(?7k:5f:?k4>k39h76a;6`83>!4>l3>o56`=9b80`>=h<<l1<7*=9e87`<=i:0i1?h54o57f>5<#:0n18i74n3;`>6`<3`>:57>5$3;g>13?3g82o7>4;h62<?6=,;3o69;7;o0:g?7<3`>:;7>5$3;g>13?3g82o7<4;h622?6=,;3o69;7;o0:g?5<3`>:87>5$3;g>13?3g82o7:4;h627?6=,;3o69;7;o0:g?3<3`>:>7>5$3;g>13?3g82o784;h625?6=,;3o69;7;o0:g?1<3`>:<7>5$3;g>13?3g82o764;h63b?6=,;3o69;7;o0:g??<3`>;i7>5$3;g>13?3g82o7o4;h63`?6=,;3o69;7;o0:g?d<3`>;o7>5$3;g>13?3g82o7m4;h63f?6=,;3o69;7;o0:g?b<3`>;57>5$3;g>13?3g82o7k4;h63<?6=,;3o69;7;o0:g?`<3`>;;7>5$3;g>13?3g82o7??;:k743<72-82h7::8:l1=f<6921b8=;50;&1=a<3=11e>4m51398m163290/>4j544:8j7?d28907d:?3;29 7?c2=?37c<6c;37?>o38;0;6)<6d;66<>h51j0:965f41394?"51m0?955a28a953=<a=:;6=4+28f900><f;3h6<94;h1ea?6=,;3o69;7;o0:g?7?32c8ji4?:%0:`?2202d95n4>9:9j7ce=83.95i4;599m6<e=9h10e>hm:18'6<b=<<20b?7l:0`8?l5ai3:1(?7k:57;?k4>k3;h76g<f883>!4>l3>>46`=9b82`>=n;o21<7*=9e871==i:0i1=h54i2d4>5<#:0n18864n3;`>4`<3`9m:7>5$3;g>13?3g82o7<?;:k0b0<72-82h7::8:l1=f<5921b?k=50;&1=a<3=11e>4m52398m6`5290/>4j544:8j7?d2;907d=i1;29 7?c2=?37c<6c;07?>o4n90;6)<6d;66<>h51j09965f3dd94?"51m0?955a28a963=<a:on6=4+28f900><f;3h6?94;h1f`?6=,;3o69;7;o0:g?4?32c8in4?:%0:`?2202d95n4=9:9j7`d=83.95i4;599m6<e=:h10e>kn:18'6<b=<<20b?7l:3`8?l5b03:1(?7k:57;?k4>k38h76g<e683>!4>l3>>46`=9b81`>=n;l<1<7*=9e871==i:0i1>h54i2g6>5<#:0n18864n3;`>7`<3`9n87>5$3;g>13?3g82o7=?;:k0a6<72-82h7::8:l1=f<4921b?h<50;&1=a<3=11e>4m53398m6c6290/>4j544:8j7?d2:907d=j0;29 7?c2=?37c<6c;17?>o4lo0;6)<6d;66<>h51j08965f40a94?"51m0?955a28a973=<a=;i6=4+28f900><f;3h6>94;h62e?6=,;3o69;7;o0:g?5?32c?=84?:%0:`?2202d95n4<9:9j05g=83.95i4;599m6<e=;h10e>hi:18'6<b=<<20b?7l:2`8?l5a<3:1(?7k:57;?k4>k39h76g<e883>!4>l3>>46`=9b80`>=n;mo1<7*=9e871==i:0i1?h54i2fg>5<#:0n18864n3;`>6`<3`9o87>5;n73g?6=,;3o68>k;o0:g?6<3f?;n7>5$3;g>06c3g82o7?4;n73e?6=,;3o68>k;o0:g?4<3f?;57>5$3;g>06c3g82o7=4;n72b?6=,;3o68<?;o0:g?6<3f?:i7>5$3;g>0473g82o7?4;n72`?6=,;3o68<?;o0:g?4<3f?:o7>5$3;g>0473g82o7=4;n6f<?6=3`>n?7>5;n1gg?6=3`?;47>5;n72<?6=3k9h;7>51;294~"5l10::?5G3b48L6?33f;==7>5;|`0g=<7280;6=u+2e:97<3<@:i=7E=64:m1=d<722wi?>650;694?6|,;n36<;k;I1`2>N41=1/=:o55:k:f?6=3`kh6=44i3;e>5<<g;k;6=44}c103?6=<3:1<v*=d9821a=O;j<0D>7;;%34e?3<a0h1<75fab83>>o51o0;66a=a183>>{e;<21<7:50;2x 7b?28?o7E=l6:J0=1=#9>k196g6b;29?lgd2900e?7i:188k7g72900qo=:7;290?6=8r.9h54>5e9K7f0<@:3?7)?8a;78m<d=831bmn4?::k1=c<722e9m=4?::a7=d=8391<7>t$3f;>43f3A9h:6F<959K===#:9=1>i94$05b>4=n1k0;66gnc;29?j4f83:17pl<9183>6<729q/>i6514c8L6e13A9286F68:&142<5l>1/=:o51:k:f?6=3`kh6=44o3c3>5<<uk93m7>53;294~"5l10:9l5G3b48L6?33A337)<?7;0g3>"6?h0:7d7m:188mde=831d>l>50;9~f6>a29086=4?{%0g<?72i2B8o;5G3868L<><,;:<6?j8;%34e?7<a0h1<75fab83>>i5i90;66sm39;94?3=83:p(?j7:07f?M5d>2B8595G999'651=:m=0e4l50;9je5<722cjo7>5;h0:b?6=3f8j<7>5;|`0<1<72=0;6=u+2e:950b<@:i=7E=64:&23d<23`3i6=44i`a94?=n:0l1<75`2`294?=zj:286=4;:183!4c03;>h6F<c79K7<2<,8=j685f9c83>>ofk3:17d<6f;29?j4f83:17pl<8383>1<729q/>i6514f8L6e13A9286*>7`86?l?e2900elm50;9j6<`=831d>l>50;9~f6>b290>6=4?{%0g<?72m2B8o;5G3868L<><,;:<6?j8;h;a>5<<ah:1<75fab83>>o51o0;66a=a183>>{e;121<7:50;2x 7b?28?o7E=l6:J0=1=#9>k196g6b;29?lgd2900e?7i:188k7g72900qo=77;290?6=8r.9h54>5e9K7f0<@:3?7)?8a;78m<d=831bmn4?::k1=c<722e9m=4?::a71d=83?1<7>t$3f;>43d3A9h:6F<959'52g=92c2n7>5;hc3>5<<ah21<75fab83>>i5i90;66sm35c94?3=83:p(?j7:07`?M5d>2B8595+16c95>o>j3:17do?:188md>=831bmn4?::m1e5<722wi?9750;794?6|,;n36<;l;I1`2>N41=1/=:o51:k:f?6=3`k;6=44i`:94?=nij0;66a=a183>>{e;=21<7;50;2x 7b?28?h7E=l6:J0=1=#9>k1=6g6b;29?lg72900el650;9jef<722e9m=4?::a715=83?1<7>t$3f;>43d3A9h:6F<959'52g=92c2n7>5;hc3>5<<ah21<75fab83>>i5i90;66sm35094?3=83:p(?j7:07`?M5d>2B8595+16c95>o>j3:17do?:188md>=831bmn4?::m1e5<722wi?9?50;794?6|,;n36<;l;I1`2>N41=1/=:o51:k:f?6=3`k;6=44i`:94?=nij0;66a=a183>>{e;=:1<7;50;2x 7b?28?n7E=l6:J0=1=#9>k196g6b;29?lg72900elm50;9j6<`=831d>l>50;9~f614290>6=4?{%0g<?72k2B8o;5G3868 41f281b5o4?::kb4?6=3`k36=44i`a94?=h:h:1<75rb251>5<2290;w)<k8;36g>N4k?1C?4:4$05b>4=n1k0;66gn0;29?lg?2900elm50;9l6d6=831vn>9>:186>5<7s-8o47?:c:J0g3=O;0>0(<9n:09j=g<722cj<7>5;hc;>5<<ahi1<75`2`294?=zj:=;6=4::183!4c03;>o6F<c79K7<2<,8=j6<5f9c83>>of83:17do7:188mde=831d>l>50;9~f60e290>6=4?{%0g<?72k2B8o;5G3868 41f281b5o4?::kb4?6=3`k36=44i`a94?=h:h:1<75rb24b>5<2290;w)<k8;36g>N4k?1C?4:4$05b>4=n1k0;66gn0;29?lg?2900elm50;9l6d6=831vn>86:186>5<7s-8o47?:c:J0g3=O;0>0(<9n:09j=g<722cj<7>5;hc;>5<<ahi1<75`2`294?=zj:<36=4::183!4c03;>i6F<c79K7<2<,8=j685f9c83>>of83:17dol:188m7?a2900c?o?:188yg51;3:197>50z&1`=<6=j1C?n84H2;7?!70i3;0e4l50;9je5<722cj47>5;hc`>5<<g;k;6=44}c156?6==3:1<v*=d9821f=O;j<0D>7;;%34e?7<a0h1<75fa183>>of03:17dol:188k7g72900qo=91;291?6=8r.9h54>5d9K7f0<@:3?7)?8a;78m<d=831bm=4?::kbg?6=3`82j7>5;n0b4?6=3th8:=4?:483>5}#:m21=8m4H2a5?M5><2.:;l4>;h;a>5<<ah:1<75fa983>>ofk3:17b<n0;29?xd4910;694?:1y'6a>=9<h0D>m9;I1:0>"6?h0:7d7m:188md>=831bmn4?::m1e5<722wi?<950;694?6|,;n36<;m;I1`2>N41=1/=:o51:k:f?6=3`k36=44i`a94?=h:h:1<75rb235>5<3290;w)<k8;36f>N4k?1C?4:4$05b>4=n1k0;66gn8;29?lgd2900c?o?:188yg56=3:187>50z&1`=<6=k1C?n84H2;7?!70i3;0e4l50;9je=<722cjo7>5;n0b4?6=3th9j;4?:583>5}#:m21=8l4H2a5?M5><2.:;l4>;h;a>5<<ah21<75fab83>>i5i90;66sm2g794?2=83:p(?j7:07a?M5d>2B8595+16c95>o>j3:17do7:188mde=831d>l>50;9~f7`3290?6=4?{%0g<?72j2B8o;5G3868 41f281b5o4?::kb<?6=3`kh6=44o3c3>5<<uk8m?7>54;294~"5l10:9o5G3b48L6?33-;<m7?4i8`94?=ni10;66gnc;29?j4f83:17pl<3183>1<729q/>i6514`8L6e13A9286*>7`82?l?e2900el650;9jef<722e9m=4?::a77`=83>1<7>t$3f;>43e3A9h:6F<959'52g=92c2n7>5;hc;>5<<ahi1<75`2`294?=zj:8n6=4;:183!4c03;>n6F<c79K7<2<,8=j6<5f9c83>>of03:17dol:188k7g72900qo==d;290?6=8r.9h54>5c9K7f0<@:3?7)?8a;38m<d=831bm54?::kbg?6=3f8j<7>5;|`04`<72=0;6=u+2e:950d<@:i=7E=64:&23d<63`3i6=44i`:94?=nij0;66a=a183>>{e;9n1<7:50;2x 7b?28?i7E=l6:J0=1=#9>k1=6g6b;29?lg?2900elm50;9l6d6=831vn>>l:187>5<7s-8o47?:b:J0g3=O;0>0(<9n:09j=g<722cj47>5;hc`>5<<g;k;6=44}c13f?6=<3:1<v*=d9821g=O;j<0D>7;;%34e?7<a0h1<75fa983>>ofk3:17b<n0;29?xd4:10;694?:1y'6a>=9<h0D>m9;I1:0>N>02.9<:4=d69'52g=92c2n7>5;hc;>5<<ahi1<75`2`294?=zj:8<6=4;:183!4c03;>n6F<c79K7<2<@020(?>8:3f4?!70i3;0e4l50;9je=<722cjo7>5;n0b4?6=3th8>;4?:583>5}#:m21=8l4H2a5?M5><2B246*=0681`2=#9>k1=6g6b;29?lg?2900elm50;9l6d6=831vn><::187>5<7s-8o47?:b:J0g3=O;0>0D464$324>7b03-;<m7?4i8`94?=ni10;66gnc;29?j4f83:17pl<0783>1<729q/>i6514`8L6e13A9286F68:&142<5l>1/=:o51:k:f?6=3`k36=44i`a94?=h:h:1<75rb226>5<3290;w)<k8;36f>N4k?1C?4:4H8:8 7602;n<7)?8a;38m<d=831bm54?::kbg?6=3f8j<7>5;|`041<72=0;6=u+2e:950d<@:i=7E=64:J:<>"58>09h:5+16c95>o>j3:17do7:188mde=831d>l>50;9~f664290?6=4?{%0g<?72j2B8o;5G3868L<><,;:<6?j8;%34e?7<a0h1<75fa983>>ofk3:17b<n0;29?xd5nl0;694?:1y'6a>=9<h0D>m9;I1:0>"6?h0:7d7m:188md>=831bmn4?::m1e5<722wi>kj50;694?6|,;n36<;m;I1`2>N41=1/=:o51:k:f?6=3`k36=44i`a94?=h:h:1<75rb3d`>5<3290;w)<k8;36f>N4k?1C?4:4$05b>4=n1k0;66gn8;29?lgd2900c?o?:188yg4aj3:187>50z&1`=<6=k1C?n84H2;7?!70i3;0e4l50;9je=<722cjo7>5;n0b4?6=3th8>=4?:583>5}#:m21=8l4H2a5?M5><2.:;l4>;h;a>5<<ah21<75fab83>>i5i90;66sm30d94?2=83:p(?j7:07a?M5d>2B8595+16c95>o>j3:17do7:188mde=831d>l>50;9~f67b290?6=4?{%0g<?72j2B8o;5G3868 41f281b5o4?::kb<?6=3`kh6=44o3c3>5<<uk9:h7>54;294~"5l10:9o5G3b48L6?33-;<m7?4i8`94?=ni10;66gnc;29?j4f83:17pl<3883>6<729q/>i652118L6e13A9286*>7`8f?l71<3:17d?95;29?j4>03:17pl<5883>6<729q/>i652118L6e13A9286*>7`8f?l71<3:17d?95;29?j4>03:17pl<7b83>1<729q/>i652168L6e13A9286*>7`8b4>o6>=0;66g>6483>>o6>?0;66a=9983>>{e;1n1<7=50;2x 7b?2;:87E=l6:J0=1=#9>k1i6g>6583>>o6><0;66a=9983>>{e;081<7=50;2x 7b?2;:87E=l6:J0=1=#9>k1i6g>6583>>o6><0;66a=9983>>{e;=l1<7:50;2x 7b?2;:?7E=l6:J0=1=#9>k1>:5+28g97fc<a8<?6=44i046>5<<a8<=6=44o3;;>5<<uk9>=7>55;294~"5l109<85G3b48L6?33-;<m7<7;%0:a?5dm2c::94?::k220<722c::;4?::k222<722e9554?::a76d=8391<7>t$3f;>7643A9h:6F<959'52g=::1b=;:50;9j533=831d>4650;9~f610290?6=4?{%0g<?47<2B8o;5G3868 41f2;=0(?7j:2ae?l71<3:17d?95;29?l71>3:17b<68;29?xd4?00;684?:1y'6a>=:9?0D>m9;I1:0>"6?h0946*=9d80gc=n9?>1<75f17794?=n9?<1<75f17594?=h:021<75rb27a>5<4290;w)<k8;037>N4k?1C?4:4$05b>75<a8<?6=44i046>5<<g;336=44}c0ff?6=;3:1<v*=d98146=O;j<0D>7;;%34e?443-82i7=k0:k221<722c::84?::m1==<722wi>hj50;694?6|,;n36?>;;I1`2>N41=1/=:o5309'6<c=;m:0e<8;:188m4022900e<89:188k7??2900qo<j3;297?6=8r.9h54=029K7f0<@:3?7)?8a;00?!4>m39o=6g>6583>>o6><0;66a=9983>>{e:l?1<7:50;2x 7b?2;:?7E=l6:J0=1=#9>k1?<5+28g97a7<a8<?6=44i046>5<<a8<=6=44o3;;>5<<uk8o57>53;294~"5l109<>5G3b48L6?33-;<m7<<;h350?6=3`;=97>5;n0:<?6=3th9hn4?:283>5}#:m21>==4H2a5?M5><2.:;l4=3:k221<722c::84?::m1==<722wi>io50;194?6|,;n36?><;I1`2>N41=1/=:o5229j532=831b=;;50;9l6<>=831vn?jm:180>5<7s-8o47<?3:J0g3=O;0>0(<9n:318m4032900e<8::188k7??2900qo<kd;297?6=8r.9h54=029K7f0<@:3?7)?8a;00?l71<3:17d?95;29?j4>03:17pl=dd83>6<729q/>i652118L6e13A9286*>7`817>o6>=0;66g>6483>>i5110;66sm30294?3=83:p(?j7:326?M5d>2B8595+16c963=n9?>1<75f17794?=n9?<1<75f17594?=h:021<75rb22e>5<2290;w)<k8;031>N4k?1C?4:4$05b>70<a8<?6=44i046>5<<a8<=6=44i044>5<<g;336=44}c162?6=?3:1<v*=d98143=O;j<0D>7;;%34e?4d3`;=87>5;h351?6=3`;=:7>5;h353?6=3`;=47>5;h35=?6=3f8247>5;|`070<72<0;6=u+2e:9653<@:i=7E=64:&23d<4:2c::94?::k220<722c::;4?::k222<722e9554?::a762=83=1<7>t$3f;>7613A9h:6F<959'52g=:k1b=;:50;9j533=831b=;850;9j531=831b=;650;9j53?=831d>4650;9~f651290<6=4?{%0g<?47>2B8o;5G3868 41f2;h0e<8;:188m4022900e<89:188m4002900e<87:188m40>2900c?77:188yg54:3:197>50z&1`=<58<1C?n84H2;7?!70i3997d?94;29?l71=3:17d?96;29?l71?3:17b<68;29?xd4==0;6:4?:1y'6a>=:9<0D>m9;I1:0>"6?h0956g>6583>>o6><0;66g>6783>>o6>>0;66g>6983>>o6>00;66a=9983>>{e;:91<7950;2x 7b?2;:=7E=l6:J0=1=#9>k1=8h4i047>5<<a8<>6=44i045>5<<a8<<6=44i04;>5<<a8<26=44o3;;>5<<uk9>97>57;294~"5l109<;5G3b48L6?33-;<m7?90:k221<722c::84?::k223<722c:::4?::k22=<722c::44?::m1==<722wi?8=50;594?6|,;n36?>9;I1`2>N41=1/=:o54:k221<722c::84?::k223<722c:::4?::k22=<722c::44?::m1==<722wi?>o50;094?6|,;n36?>?;I1`2>N41=1b=;=50;9l6<>=831vn>;n:181>5<7s-8o47<?0:J0g3=O;0>0e<8<:188k7??2900qo=8a;29507=83:p(?j7:3c2?M5d>2B8595U9`822~g=j321o7j59;d955<6;3;?6<?51382a?7a2::1;7?::04952<5l38n6?h5}o32f?6<f89o6=5+145950?<,8?36<;6;%0`b?7212.9h84=;%35e?5<,8<i6>5+17a97>"6>m087)?9e;18 40a2:1/=:>53:&234<43-;<>7=4$050>6=#9>>1?6*>7480?!70>390(<98:29'52>=;2.:;44<;%34f?5<,8=h6>5+16f97>"6?l087)?8f;18 4>72:1/=5?53:&2<7<43-;3?7=4$0:7>6=#91?1?6*>8780?!7??390(<67:29'5=?=;2.:4l4<;%3;f?5<,82h6>5+19f97>"60l087)?7f;18 4?72:1/=4?53:&2=7<43-;2?7=4$0;7>6=#90?1?6*>9780?!7>?390(<77:29'5<?=;2.:5l4<;%3:f?5<,83h6>5+18f97>"61l087)?6f;18 4g72:1/=l?53:&2e7<43-;j?7=4$0c7>6=#9h?1?6*>a780?!7f?390(<o7:29'5d?=;2.:ml4<;%3bf?5<,8kh6>5+1`f97>"6il087)?nf;18 4d72:1/=o?53:&2f7<43-;i?7=4$0`7>6=#9k?1?6*>b780?!7e?390(<l7:29'5g?=;2.:nl4<;%3af?5<,8hh6>5+1cf97>"6jl087)?mf;18 4e72:1/=n?53:&2g7<43-;h?7=4$0a7>6=#9j?1?6*>c780?!7d?390(<m7:29'5f?=;2.:ol4<;%3`f?5<,8ih6>5+1bf97>"6kl087)?lf;18 4b72:1/=i?53:&2`7<43-;o?7=4$0f7>6=#9m?1?6*>d780?!7c?390(<j7:29'5a?=;2.:hl4<;%3gf?5<,8nh6>5+1ef97>"6ll087)?kf;18 4c72:1/=h?53:&2a7<43-;n?7=4$0g7>6=#9l?1?6*>e780?!7b?390(<k7:29'5`?=;2.:il4<;%3ff?5<,8oh6>5+1df97>"6ml087)?jf;18 4`72:1/=k?53:&2b7<43-;m?7=4$0d7>6=#9o?1?6*>f780?!7a?390(<h7:29'5c?=;2.:jl4<;%3e`?4>?2.9m?4=969'6d5=:0=0(?o;:3f2?k4e<3>37c<m5;28 7ec2;h=7)<le;0a2>"5l;02;6*>fc81?!7ak380(>m>:3`0?!5d:38i?6`<c283?k5d<3>37)<k6;08m<e=831b5i4?::m:a?6=3f3m6=44i`094?=ni:0;6E<k3:9je1<72A8o?65fa483>>of>3:1D?j<;:kb3?6=@;n876and;29?l7293:17d?:2;29L7b432c:9>4?:I0g7>=n9<>1<75f14794?N5l:10e<;9:18K6a5<3`;mi7>5;h3eb?6=3`8i;7>5;h0a<?6=@;n876g=b883>M4c;21b>oo50;9j6gd=83B9h>54i3``>5<O:m907d<md;29L7b432c9nh4?:I0g7>=n:kl1<7F=d298m7e7290C>i=4;h0`5?6=3`8h>7>5H3f0?>o5k:0;6E<k3:9j6f2=831b>n;50;J1`6=<a;i=6=4G2e18?l4d?3:17d<l8;29L7b432c9o44?:I0g7>=n:jk1<75f2b`94?N5l:10e?ml:18K6a5<3f8o<7>5;h1b>5<#:0n1?45a28a94>=n;10;6)<6d;1:?k4>k3;07d=8:18'6<b=;01e>4m52:9j73<72-82h7=6;o0:g?5<3`9>6=4+28f97<=i:0i1865f3583>!4>l3927c<6c;78?l24290/>4j5389m6<e=>21b8?4?:%0:`?5>3g82o794;h62>5<#:0n1?45a28a9<>=n<90;6)<6d;1:?k4>k3307d=i:18'6<b=;01e>4m5a:9j7`<72-82h7=6;o0:g?d<3`9o6=4+28f97<=i:0i1o65f3b83>!4>l3927c<6c;f8?l5e290/>4j5389m6<e=m21b?>4?:%0:`?5>3g82o7h4;h6a>5<#:0n18l5a28a94>N5l:10e9750;&1=a<3i2d95n4>;I0g7>=n<10;6)<6d;6b?k4>k380D?j<;:k73?6=,;3o69o4n3;`>6=O:m907d:9:18'6<b=<h1e>4m54:J1`6=<a=?1<7*=9e87e>h51j0>7E<k3:9j11<72-82h7:n;o0:g?0<@;n876g:3;29 7?c2=k0b?7l:69K6a5<3`?96=4+28f90d=i:0i146F=d298m07=83.95i4;a:l1=f<>3A8o?65f5183>!4>l3>j7c<6c;c8L7b432c?j7>5$3;g>1g<f;3h6o5G2e18?l2b290/>4j54`9m6<e=k2B9h>54i5f94?"51m0?m6`=9b8g?M4c;21b8n4?:%0:`?2f3g82o7k4H3f0?>o3<3:1(?7k:5c8j7?d2o1C>i=4;h7a>5<#:0n19l5a28a94>N5l:10e8750;&1=a<2i2d95n4>;I0g7>=n=10;6)<6d;7b?k4>k380D?j<;:k63?6=,;3o68o4n3;`>6=O:m907d;9:18'6<b==h1e>4m54:J1`6=<a?>1<7*=9e86e>h51j0>7E<k3:9j26<72-82h7;n;o0:g?0<@;n876g92;29 7?c2<k0b?7l:69K6a5<3`<:6=4+28f91d=i:0i146F=d298m36=83.95i4:a:l1=f<>3A8o?65f5g83>!4>l3?j7c<6c;c8L7b432c>i7>5$3;g>0g<f;3h6o5G2e18?l3c290/>4j55`9m6<e=k2B9h>54i4a94?"51m0>m6`=9b8g?M4c;21b984?:%0:`?3f3g82o7k4H3f0?>o1k3:1(?7k:7`8j7?d2910e;o50;&1=a<1j2d95n4>;:k5=?6=,;3o6;l4n3;`>7=<a?21<7*=9e85f>h51j0876g97;29 7?c2?h0b?7l:598m30=83.95i49b:l1=f<232c<97>5$3;g>3d<f;3h6;54i6694?"51m0=n6`=9b84?>o0;3:1(?7k:7`8j7?d2110e:<50;&1=a<1j2d95n46;:k45?6=,;3o6;l4n3;`>d=<a>:1<7*=9e85f>h51j0i76g9f;29 7?c2?h0b?7l:b98m3c=83.95i49b:l1=f<c32c=h7>5$3;g>3d<f;3h6h54i7794?"51m0=n6`=9b8e?>o0l3:1(?7k:6a8j7?d291C>i=4;h5a>5<#:0n1;n5a28a95>N5l:10e:o50;&1=a<0k2d95n4=;I0g7>=n?00;6)<6d;5`?k4>k390D?j<;:k4<?6=,;3o6:m4n3;`>1=O:m907d98:18'6<b=?j1e>4m55:J1`6=<a1<1<7*=9e84g>h51j0=7E<k3:9j<0<72-82h79l;o0:g?1<@;n876g74;29 7?c2>i0b?7l:99K6a5<3`286=4+28f93f=i:0i156F=d298m=4=83.95i48c:l1=f<f3A8o?65f8083>!4>l3=h7c<6c;`8L7b432c3<7>5$3;g>2e<f;3h6n5G2e18?l1a290/>4j57b9m6<e=l2B9h>54i6g94?"51m0<o6`=9b8f?M4c;21b;;4?:%0:`?1d3g82o7h4H3f0?>o?l3:1(?7k:9a8j7?d291C>i=4;h:a>5<#:0n14n5a28a95>N5l:10e5o50;&1=a<?k2d95n4=;I0g7>=n000;6)<6d;:`?k4>k390D?j<;:k;<?6=,;3o65m4n3;`>1=O:m907d79:18'6<b=0j1e>4m55:J1`6=<a0?1<7*=9e8;g>h51j0=7E<k3:9j=1<72-82h76l;o0:g?1<@;n876g63;29 7?c21i0b?7l:99K6a5<3`396=4+28f9<f=i:0i156F=d298m<7=83.95i47c:l1=f<f3A8o?65f9183>!4>l32h7c<6c;`8L7b432c3j7>5$3;g>=e<f;3h6n5G2e18?l>b290/>4j58b9m6<e=l2B9h>54i9594?"51m03o6`=9b8f?M4c;21bo:4?:%0:`?e13g82o7>4;ha6>5<#:0n1o;5a28a95>=nk:0;6)<6d;a5?k4>k3807dm=:18'6<b=k?1e>4m53:9jg4<72-82h7m9;o0:g?2<3`i;6=4+28f9g3=i:0i1965fbg83>!4>l3i=7c<6c;48?ldb290/>4j5c79m6<e=?21bni4?:%0:`?e13g82o764;h``>5<#:0n1o;5a28a9=>=njk0;6)<6d;a5?k4>k3k07dln:18'6<b=k?1e>4m5b:9jf=<72-82h7m9;o0:g?e<3`h<6=4+28f9g3=i:0i1h65fb783>!4>l3i=7c<6c;g8?ld2290/>4j5c79m6<e=n21bn94?:%0:`?e13g82o7??;:ka7?6=,;3o6n84n3;`>47<3`h96=4+28f9g3=i:0i1=?54ic394?"51m0h:6`=9b827>=nj90;6)<6d;a5?k4>k3;?76gnf;29 7?c2j<0b?7l:078?leb290/>4j5c79m6<e=9?10enj50;&1=a<d>2d95n4>7:9jgf<72-82h7m9;o0:g?7?32chn7>5$3;g>f0<f;3h6<74;hab>5<#:0n1o;5a28a95d=<aj31<7*=9e8`2>h51j0:n65fc983>!4>l3i=7c<6c;3`?>od<3:1(?7k:b48j7?d28n07dl6:18'6<b=k?1e>4m51d98mdc=83.95i4l6:l1=f<6n21bi54?:%0:`?c03g82o7>4;hg5>5<#:0n1i:5a28a95>=nm=0;6)<6d;g4?k4>k3807dk<:18'6<b=m>1e>4m53:9ja7<72-82h7k8;o0:g?2<3`o:6=4+28f9a2=i:0i1965fe183>!4>l3o<7c<6c;48?lba290/>4j5e69m6<e=?21bhh4?:%0:`?c03g82o764;hfg>5<#:0n1i:5a28a9=>=nlj0;6)<6d;g4?k4>k3k07djm:18'6<b=m>1e>4m5b:9j`<<72-82h7k8;o0:g?e<3`n36=4+28f9a2=i:0i1h65fd683>!4>l3o<7c<6c;g8?lb1290/>4j5e69m6<e=n21bh84?:%0:`?c03g82o7??;:kg0?6=,;3o6h94n3;`>47<3`n86=4+28f9a2=i:0i1=?54ie094?"51m0n;6`=9b827>=nl80;6)<6d;g4?k4>k3;?76gk0;29 7?c2l=0b?7l:078?lca290/>4j5e69m6<e=9?10ehk50;&1=a<b?2d95n4>7:9jaa<72-82h7k8;o0:g?7?32cno7>5$3;g>`1<f;3h6<74;hga>5<#:0n1i:5a28a95d=<alk1<7*=9e8f3>h51j0:n65fe883>!4>l3o<7c<6c;3`?>ob=3:1(?7k:d58j7?d28n07djn:18'6<b=m>1e>4m51d98mf`=83.95i4j7:l1=f<6n21bj94?:%0:`?`43g82o7>4;hd1>5<#:0n1j>5a28a95>=nn80;6)<6d;d0?k4>k3807dh?:18'6<b=n:1e>4m53:9jb<<72-82h7h7;o0:g?6<3`l<6=4+28f9b==i:0i1=65ff783>!4>l3l37c<6c;08?l`2290/>4j5f99m6<e=;21d=<=50;&1=a<69;1e>4m50:9l547=83.95i4>139m6<e=921d==h50;&1=a<69;1e>4m52:9l55c=83.95i4>139m6<e=;21d==j50;&1=a<69;1e>4m54:9l55e=83.95i4>139m6<e==21d==l50;&1=a<69;1e>4m56:9l55g=83.95i4>139m6<e=?21d==750;&1=a<69;1e>4m58:9l55>=83.95i4>139m6<e=121d==950;&1=a<69;1e>4m5a:9l550=83.95i4>139m6<e=j21d==:50;&1=a<69;1e>4m5c:9l555=83.95i4>139m6<e=l21d==<50;&1=a<69;1e>4m5e:9l557=83.95i4>139m6<e=n21d==>50;&1=a<69;1e>4m51198kc`=83.95i4>139m6<e=9810ckk50;&1=a<69;1e>4m51398kcb=83.95i4>139m6<e=9:10ckm50;&1=a<69;1e>4m51598kcd=83.95i4>139m6<e=9<10c<?n:18'6<b=9880b?7l:048?j7613:1(?7k:031?k4>k3;<76a>1983>!4>l3;:>6`=9b82<>=h98=1<7*=9e8257=i:0i1=454o035>5<#:0n1=<<4n3;`>4g<3f;:97>5$3;g>4753g82o7?m;:m251<72-82h7?>2:l1=f<6k21d=<>50;&1=a<69;1e>4m51e98k462290/>4j51008j7?d28o07bhn:18'6<b=9880b?7l:0d8?j74=3:1(?7k:017?k4>k3:07b?<3;29 7?c289?7c<6c;38?j7493:1(?7k:017?k4>k3807b?<0;29 7?c289?7c<6c;18?j75n3:1(?7k:017?k4>k3>07b?=e;29 7?c289?7c<6c;78?j75l3:1(?7k:017?k4>k3<07b?=c;29 7?c289?7c<6c;58?j75j3:1(?7k:017?k4>k3207b?=a;29 7?c289?7c<6c;;8?j7513:1(?7k:017?k4>k3k07b?=8;29 7?c289?7c<6c;`8?j75>3:1(?7k:017?k4>k3i07b?=5;29 7?c289?7c<6c;f8?j75<3:1(?7k:017?k4>k3o07b?=3;29 7?c289?7c<6c;d8?j75:3:1(?7k:017?k4>k3;;76a>2083>!4>l3;886`=9b825>=h9;:1<7*=9e8271=i:0i1=?54o03e>5<#:0n1=>:4n3;`>45<3f;:i7>5$3;g>4533g82o7?;;:m25a<72-82h7?<4:l1=f<6=21d=>m50;&1=a<6;=1e>4m51798k45e290/>4j51268j7?d28=07b?<a;29 7?c289?7c<6c;3;?>i6;00;6)<6d;300>h51j0:565`12:94?"51m0:?95a28a95d=<g89<6=4+28f9562<f;3h6<l4;n302?6=,;3o6<=;;o0:g?7d32e:??4?:%0:`?74<2d95n4>d:9l571=83.95i4>359m6<e=9l10c<?l:18'6<b=9:>0b?7l:0d8?j73:3:1(?7k:062?k4>k3:07b?;0;29 7?c28>:7c<6c;38?j74n3:1(?7k:062?k4>k3807b?<e;29 7?c28>:7c<6c;18?j73?3:1(?7k:065?k4>k3:07b?;5;29 7?c28>=7c<6c;38?j73<3:1(?7k:065?k4>k3807b?;3;29 7?c28>=7c<6c;18?j7283:1(?7k:06e?k4>k3:07b?;e;29 7?c28>m7c<6c;38?j73l3:1(?7k:06e?k4>k3807b?;c;29 7?c28>m7c<6c;18?j73j3:1(?7k:06e?k4>k3>07b?;a;29 7?c28>m7c<6c;78?j7313:1(?7k:06e?k4>k3<07b?;8;29 7?c28>m7c<6c;58?j4f13:1(?7k:3c;?k4>k3:0D?j<;:m1e2<72-82h7<n8:l1=f<63A8o?65`2`494?"51m09m55a28a96>N5l:10c?l=:18'6<b=:h20b?7l:29K6a5<3f8i=7>5$3;g>7g?3g82o7:4;n0a4?6=,;3o6?o7;o0:g?3<3f8jj7>5$3;g>7g?3g82o784;n0ba?6=,;3o6?o7;o0:g?1<3f8jh7>5$3;g>7g?3g82o764;n0bg?6=,;3o6?o7;o0:g??<3f8jn7>5$3;g>7g?3g82o7o4;n0be?6=,;3o6?o7;o0:g?d<3f8j97>5$3;g>7g?3g82o7m4;h1:f?6=,;3o6>7n;o0:g?6<3`9257>5$3;g>6?f3g82o7?4;h1:<?6=,;3o6>7n;o0:g?4<3`92;7>5$3;g>6?f3g82o7=4;h1b4?6=,;3o6>7i;o0:g?6<@;n876g<9d83>!4>l392j6`=9b82?M4c;21b?4j50;&1=a<41o1e>4m52:J1`6=<a:3h6=4+28f97<`<f;3h6>5G2e18?l5f=3:1(?7k:2c7?k4>k3:0D?j<;:k0e6<72-82h7=n4:l1=f<63A8o?65f3`094?"51m08m95a28a96>N5l:10e>o>:18'6<b=;h>0b?7l:29K6a5<3`9ji7>5$3;g>6gc3g82o7>4;h1bg?6=,;3o6>ok;o0:g?7<3`9jn7>5$3;g>6gc3g82o7<4;h1be?6=,;3o6>ok;o0:g?5<3`9j57>5$3;g>6gc3g82o7:4;h1b<?6=,;3o6>ok;o0:g?3<3`9j;7>5$3;g>6gc3g82o784;h1b2?6=,;3o6>ok;o0:g?1<3`9i;7>5$3;g>6d13g82o7>4H3f0?>o4j<0;6)<6d;1a2>h51j0:7E<k3:9j7g2=83.95i4<b79m6<e=:2B9h>54i2`0>5<#:0n1?o84n3;`>6=O:m907d=m2;29 7?c2:h=7c<6c;68L7b432c8n<4?:%0:`?5e>2d95n4:;I0g7>=n;k:1<7*=9e80f3=i:0i1:6F=d298m6ga290/>4j53c48j7?d2>1C>i=4;h1`4?6=,;3o6>li;o0:g?6<@;n876g<bd83>!4>l39ij6`=9b82?M4c;21b?oj50;&1=a<4jo1e>4m52:J1`6=<a:hh6=4+28f97g`<f;3h6>5G2e18?l5ej3:1(?7k:2`e?k4>k3>0D?j<;:k0fd<72-82h7=mf:l1=f<23A8o?65f3c;94?"51m08nk5a28a92>N5l:10e>l7:18'6<b=;kl0b?7l:69K6a5<3ty?944?:3y]04?<5:=j6h64}r663?6=:rT?=55236c9a3=z{=?=6=4={_623>;4?h0n86s|44794?4|V=;=70=8a;g0?xu3=:0;6?uQ4068961f2l80q~::2;296~X39:16?:o5e09~w1362909wS:>2:?03d<b82wx88>50;0xZ176349<m7ji;|q70c<72;qU8<>4=25b>ac<uz>?i7>52z\74c=:;>k1hi5rs56g>5<5sW>;i63<7`8gg>{t<=i1<7<t^52g?850i3ni7p};4c83>7}Y<9i01>9n:e;8yv23i3:1>vP;0c9>72g=l11v9:7:181[271278;l4k7:p011=838pR9>7;<14e?b13ty?8;4?:3y]051<5:=j6i;4}r671?6=:rT?<;5236c9`1=z{=>?6=4={_631>;4?h0o?6s|45194?4|V=:?70=8a;f1?xu3<;0;6?uQ4118961f2m;0q~:;1;296~X38;16?:o5d19~w1272909wS:?1:?03d<bn2wx8>h50;0xZ167349<m7kj;|q77a<72;qU?kk4=25b>`b<uz>8o7>52z\0ba=:;>k1in5rs51a>5<5sW9mo63<7`8ff>{t<:k1<7<t^2da?850i3oj7p};3883>7}Y;ok01>9n:d;8yv2403:1>vP<f89>72g=m<1v9=8:181[5a0278;l4ka:p060=838pR>h8;<14e?ea3ty??84?:3y]7c0<5:=j6n94}r600?6=:rT8j85236c9g0=z{=996=4={_1e7>;4?h0h?6s|42394?4|V:l970=8a;a1?xu3;90;6?uQ3g38961f2j;0q~:=f;296~X4n916?:o5c19~w14b2909wS=jf:?03d<en2wx8?j50;0xZ6cb349<m7lj;|q76f<72;qU?hj4=25b>gb<uz>9n7>52z\0af=:;>k1nn5rs50b>5<5sW9nn63<7`8af>{t<;31<7<t^2gb?850i3hj7p};2683>7}Y;l201>9n:c:8yv25>3:1>vP<e69>72g=j>1v9<::181[5b>278;l4m6:p072=838pR>k:;<14e?d23ty?>>4?:3y]7`2<5:=j6o:4}r616?6=:rT8i>5236c9f6=z{=8:6=4={_1f6>;4?h0i>6s|43294?4|V:o:70=8a;`2?xu39o0;6?uQ3d28961f2k:0q~:>e;296~X4lo16?:o5ag9~w13c2909wS:>c:?03d<dm2wx88m50;0xZ17e349<m7mk;|q71g<72;qU8<o4=25b>fe<uz>>m7>52z\750=:;>k1oo5rs577>5<5sW>;m63<7`8`e>{t<=31<7<t^2de?850i3i27p};3d83>7}Y;o>01>9n:b:8yv24;3:1>vP<e89>72g=k=1v9<7:181[5cm278;l4m9:p04b=838pR>jk;<14e?gb3ty><54?:30xZ06?3498477m;<103??e3493n77m;<1;e??e3493577m;<1;0??e3493?77m;<1;6??e349?n77m;<17e??e349?577m;<17<??e349??77m;<176??e349?=77m;<174??e349:477m;<123??e349::77m;<121??e3498<77m;<11b??e3499i77m;<11`??e3499477m;<113??e3499:77m;<111??e348mi77m;<0e`??e348mo77m;<0ef??e349<m7o=;|q64`<72=qU9=k4=21:>403349<o7?94:?076<6>=1v8??:180[368278444=9g9>7=c=:0l0q~;>b;2960}Y=8h01>;7:8`8963020h01>7?:8`896>a20h01>6j:8`896>?20h01>68:8`8961420h01>9=:8`8961620h01>9?:8`8960e20h01>8n:8`8960>20h01>87:8`8960420h01>8=:8`8960620h01>8?:8`897`120h01?h::8`897`320h01?h<:8`8966b20h01>>k:8`8966d20h01>>m:8`8966120h01>>::8`8966320h01>><:8`8964720h01>?i:8`8967b20h01>?k:8`8961f2h?0q~;=1;297~X2:816?8751768963228<?7p}<db83>1>|V:nj7S=k9:\0`==Y;m=0R8>l;_73f>X28h1U9=74^43e?[36m2T>=i5Q50a8Z6b53W9o?6P;e69]0`><V=l37S;>9:\65==Y=8k0R8?>;_1gg>;4k>0::<5239;9ef=:;1>1mn523919ef=:;181mn5239g9ef=:;121mn523959ef=:;>k15n5236c9=a=:;>k1=kk4=25b>4`a349<m7<m7:?03d<5jh16?:o52b58961f2;ij70=8a;1;?850i39<70=8a;15?850i39>70=8a;17?850i39m70=8a;1f?850i39o70=8a;1`?850i39i70=8a;10?850i3<j70=8a;4:?850i3<370=8a;44?850i3<=70=8a;52?850i3=;70=8a;4e?850i3<n70=8a;4g?850i3<>70=8a;d7?850i3l970=8a;d2?850i3l;70=8a;d:?850i3l<70=8a;d5?850i3l>70=8a;1:f>;4?h08545236c97<><5:=j6>78;|q7`d<72;qU84o4=25b>4523ty?h54?:3y]0<?<5:=j6<=<;|q7`2<72;qU8464=25b>4563ty?h;4?:3y]0<1<5:=j6<=?;|q7`1<72;qU84;4=25b>44a3ty?h>4?:3y]0<2<5:=j6<<j;|q7`7<72;qU84=4=25b>44c3ty?h<4?:3y]0<4<5:=j6<<l;|q7`5<72;qU84?4=25b>44e3ty?ok4?:3y]0<6<5:=j6<<n;|q7g`<72;qU85h4=25b>44>3ty?oi4?:3y]0=c<5:=j6<<7;|q7gf<72;qU85j4=25b>4413ty?oo4?:3y]0=e<5:=j6<<:;|q7g<<72;qU85o4=25b>4433ty?o54?:3y]0=?<5:=j6<<<;|q7g2<72;qU8564=25b>4453ty?o;4?:3y]0=1<5:=j6<<>;|q7g0<72;qU8584=25b>4473ty?o94?:3y]0=3<5:=j6<?i;|q7g6<72;qU85:4=25b>47b3ty?o?4?:3y]0=5<5:=j6<?k;|q7g4<72;qU85<4=25b>45d3ty?o=4?:3y]0=7<5:=j6<=m;|q7f`<72;qU8:h4=25b>45f3ty?ni4?:3y]02c<5:=j6<=6;|q7ff<72;qU8:j4=25b>45?3ty?no4?:3y]02e<5:=j6<=8;|q7fd<72;qU8:l4=25b>4513ty?n44?:3y]02g<5:=j6<==;|q7f=<72;qU8:74=25b>4403ty?n:4?:3y]02><5:=j6<?l;|q7f3<72;qU8:94=25b>4743ty?n84?:3y]020<5:=j6<?>;|q7f6<72;qU8::4=25b>46a3ty?n?4?:3y]025<5:=j6<>j;|q7f4<72;qU8:<4=25b>46c3ty?n=4?:3y]027<5:=j6<>l;|q7ec<72;qU8:>4=25b>46e3ty?mh4?:3y]03`<5:=j6<>n;|q7ea<72;qU8;k4=25b>46>3ty?mn4?:3y]03b<5:=j6<>7;|q7eg<72;qU8;m4=25b>4603ty?ml4?:3y]03d<5:=j6<>9;|q7e=<72;qU8;74=25b>4633ty?m:4?:3y]03><5:=j6<><;|q7e3<72;qU8;94=25b>4653ty?m84?:3y]030<5:=j6<>>;|q7e1<72;qU8;;4=25b>4673ty?m>4?:3y]032<5:=j6kh4}r6b6?6=:rT?:>5236c9b`=z{=k:6=4={_656>;4?h0mh6s|4`294?4|V=<:70=8a;d`?xu31o0;6?uQ4728961f2oh0q~:ke;296~X31m16?:o510c8yv2cl3:1>vP;9b9>72g=9830q~:kc;296~X31k16?:o510:8yv2cj3:1>vP;979>72g=98=0q~:k5;296~X30k16?:o51048yv2di3:1>vP;819>72g=98?0q~:mf;296~X3?<16?:o51068yv2e<3:1>vP;6`9>72g=98:0q~:n9;296~X3=o16?:o51178yv2>m3:1>vP;5d9>72g=nh1v>=7:181[2b8278?54=a19~w63?2909wS:j2:?01=<5i91v?>m:18085d0382m63<7`80e>;4?h0=o6s|32394?5|5:936lm4=214>de<5:986?77;|q0<4<72kq6?>6528d896502;3m70=74;0b4>;4<k0j463<4`8b<>;4<00j463<498b<>;4<:0j463<438b<>;4<80j463<4181=c=z{:9<6=4;{<103?4f8278?44>649>72e=9?<01>=<:046?xu4=;0;6>u234:9ef=:;<=1mn5234196<><uz93:7>5fz?01=<51o16?89528d896>?2;k;70=83;c;?850:3k370=81;c;?85083k370=9b;c;?851i3k370=99;c;?8510382j63<628b<>;4>;0j463<6081=c=:;?:1m55rs274>5<4s49>;7<n0:?01<<6><16?8;517;8yv5?i3:1?v3<8c8bg>;40h09m=5239;9e5=z{:2i6=4={<1;f?4f82784i4>649~w6>a2908w0=60;c`?85?n38j<63<8d8b4>{t;0:1<7<t=2;3>7g73492>7?95:p7=?=839p1>6n:`a896>>2;k;70=7d;350>{t;1o1<7=t=2:e>de<5:2n6?o?;<1:6?71<2wx?5m50;6x96>32;3m70=73;0:b>;40;095k5239f96<><uz93<7>510y>7=5=:h:01>?7:`:896702h201>?9:`:896722h201>=?:`:8964a2h201><j:`:8964c2h201><7:`:896402h201><9:`:896422h201?hj:`:897`c2h201?hl:`:897`e2h20q~=8f;290~;40;09m=5236a9533<5:=j6?m>;<14e?4d<2wx?4?50;1x96>?2;3m70=77;0:b>;41;09555rs2:6>5<69r784:4=a19>6c0=i116>k;5a99>6c2=i116>k=5a99>75c=i116?=j5a99>75e=i116?=l5a99>750=i116?=;5a99>752=i116?==5a99>776=i116?<h5a99>74c=i116?<j5a99~w61c2902w0=;b;c3?853i3k;70=;9;c3?85303k;70=;3;c3?853:3k;70=;1;c3?85383k;70=<9;0:<>{t;:l1<7:t=26a>de<5:>86?o?;<165?71<278??4>659~w620290=w0=;b;0b4>;5nl0jo63=db8220=:;:?1=;94=217>40>349<m7:<;|q07`<72<q6?9o5ab9>714=:h:01>:i:047?85293;=963<378220=z{:>=6=4:{<17e?4f8279hn4>659>6ab=9??01>=::047?850i3>97p}<3e83>3}:;=31mn5235396d6<5:>m6<89;<165?71?278?o4>659>760=9?20q~=;5;291~;4<009m=522ef9532<5;nn6<8:;<100?71=278;l4;1:p76e=832p1>:7:`a896272;k;70=;f;351>;4=80::;5232`9533<5:9=6<86;<106?71?278?l4>629~w623290?w0=;8;0b4>;5ll0::952326953><5:=j69>4}r164?6=:r788>4nc:?014<5111v>:j:181853:3kh70=;f;0:<>{t;=n1<7<t=262>de<5:9i6?77;|q00f<72;q6?9>5ab9>76g=:020q~=8e;2953}:;>91m=523609e5=:;>;1m=523629e5=:;?h1m=5237c9e5=:;?31m=5237:9e5=:;?91m=523709e5=:;?;1m=523729e5=:;<31>464=25b>433349<m7=ne:?03d<4ij16?:o53``8961f2:kj70=8a;1b=>;4?h08m55236c97d1<5:=j6>o9;|q022<72:q6?:=5ab9>73d=:h:01>;<:047?xu4>o0;69u236196d6<5:8;6lm4=3f:>402349<m79:;|q023<72:q6?:<5ab9>73g=:h:01>;;:04:?xu4>l0;69u236096d6<5;n26<8;;<0ge?71=278;l484:p733=839p1>9>:`a8960>2;k;70=:4;353>{t;?n1<7:t=252>7g7348om7?94:?1`g<6><16?:o5729~w6032908w0=80;c`?851038j<63<558220=z{:<h6=4<{<144?4f8279ho4>659>72g=?;1v>;i:186851j3kh70=93;0b4>;4?00::952344953?<5:?86<89;|q01`<72<q6?;o5ab9>734=:h:01>98:047?85013;=963<548223=z{:?o6=48{<15=?gd349==7<n0:?032<6>?16?:751758963e28<?70=:6;35<>;4=<0:::5rs27`>5<0s49=47ol;<154?4f8278;:4>649>72?=9?<01>;m:046?852>3;=:63<5`8226=z{:=36=4={<157?gd349<57<68:p720=838p1>8=:`a896102;337p}<7483>7}:;?;1mn5234`96<><uz9<87>52z?025<fk2789l4=999~w64d290>w0=>8;c`?854838j<63=e28220=::l?1=;84=22e>4003ty8=94?:5y>74>=:h:01>=::045?854<3;=863<338220=z{;o96=4={<123?gd348n?7<68:p745=839p1>?8:3c3?854=3;=963<378223=z{;o?6=4={<122?gd348n97<68:p744=839p1>?9:3c3?854<3;=:63<378222=z{;o=6=4={<121?gd349;j7<68:p747=83>p1>?::3c3?854<3;=;63<378221=:;:81=;84}r13e?6==r79j;4nc:?04`<5i916>hl5177897cc28<>70=>0;353>{t:o81<7=t=3d5>7g7349>:7?94:?016<6><1v?kn:18184a=3kh70<jb;0:<>{t:o;1<7=t=3d6>7g7349>87?98:?010<6><1v?kl:18184a<3kh70<jd;0:<>{t:o:1<7:t=3d7>7g7349>:7?97:?011<6>?16?8;517:8yv4bm3:1>v3=f28bg>;49909555rs3ge>5<4s48m?7<n0:?013<6><16?8:51768yv55<3:1>v3<318bg>;4:109m=5rs200>5<5s499j7ol;<113?4f82wx??l50;6x964a2;k;70<j3;350>;5m<0::85231d9530<uz99>7>52z?06`<fk278>;4=a19~w64f2908w0==e;0b4>;5m<0::95231d9533<uz99=7>52z?06a<fk278>84=a19~w64>2909w0==d;0b4>;48o0::95rs221>5<5s49;i7ol;<132?4f82wx?=?50;0x966c2hi01>>::3c3?xu4800;69u231f96d6<5;oi6<8;;<0f`?71<278==4>679~w6672909w0=?c;c`?857<38j<6s|31:94?5|5::h6?o?;<0f`?71>278==4>649~w7`a2909w0=?b;c`?857;38j<6s|31594?4|5::i6?o?;<124?71<2wx?<m50;0x964?2hi01><?:3c3?xu49k0;6?u23359ef=:;8l1>l>4}r12e?6=:r78>;4nc:?05`<5i91v>?6:181855=3kh70=>d;0b4>{t:ok1<7<t=225>de<5;ln6?o?;|q1b<<72;q6?=;5ab9>6cb=:h:0q~<i8;296~;48=0jo63=fb81e5=z{;l<6=4={<137?gd348mn7<n0:p6`1=838p1?hk:`a897bd2;337p}=e983>7}::oi1mn522ef96<><uz8n57>52z?1bg<fk279hh4=999~w7ba2909w0=>f;c`?84c138246s|2d294?4|5:;n6lm4=3fb>7??3ty9i<4?:3y>74b=ij16>il528:8yv50j3:1>v3<7b81===:;>k1=8?4}r162?6=:r789;4=999>705=9?30q~=<5;296~;4;<0955523219531<uz9887>52z?071<51116?>=517;8yv54>3:1>v3<3781===:;:91=;64}r03e?6=:r78??4=999>765=9?<0q~<:7;296~;4==095552341953><uz8=o7>52z?010<51116?8=51758yxu2990;6?uQ50289<?==8:0(>7<:354?xu29k0;6?uQ50`89<?==8h0(>7<:3:`?xu2810;6?uQ51:89<?==920(>7<:3;7?xu3=00;6?uQ40;89<?=<830(>7<:331?xu3=>0;6?uQ40:89<?=<820(>7<:33g?xu3=?0;6?uQ40589<?=<8=0(>7<:30;?xu3=<0;6?uQ40489<?=<8<0(>7<:310?xu3=:0;6?uQ40689<?=<8>0(>7<:31f?xu3=;0;6?uQ40189<?=<890(>7<:36:?xu3=80;6?uQ40089<?=<880(>7<:370?xu3=90;6?uQ40389<?=<8;0(>7<:376?xu3<o0;6?uQ40289<?=<8:0(>7<:375?xu3<l0;6?uQ41d89<?=<9l0(>7<:37;?xu3<m0;6?uQ41g89<?=<9o0(>7<:37:?xu3<j0;6?uQ41f89<?=<9n0(>7<:37b?xu3<k0;6?uQ41a89<?=<9i0(>7<:37a?xu3<h0;6?uQ41`89<?=<9h0(>7<:37`?xu3<10;6?uQ41;89<?=<930(>7<:37g?xu3<>0;6?uQ41:89<?=<920(>7<:37f?xu3<?0;6?uQ41589<?=<9=0(>7<:37e?xu3<<0;6?uQ41489<?=<9<0(>7<:343?xu3<=0;6?uQ41789<?=<9?0(>7<:342?xu3<:0;6?uQ41689<?=<9>0(>7<:341?xu3<;0;6?uQ41189<?=<990(>7<:340?xu3<80;6?uQ41089<?=<980(>7<:347?xu3<90;6?uQ41389<?=<9;0(>7<:346?xu3;o0;6?uQ41289<?=<9:0(>7<:345?xu3;m0;6?uQ3gg89<?=;oo0(>7<:344?xu3;j0;6?uQ3gf89<?=;on0(>7<:34;?xu3;k0;6?uQ3ga89<?=;oi0(>7<:34:?xu3;h0;6?uQ3g`89<?=;oh0(>7<:34b?xu3;00;6?uQ3gc89<?=;ok0(>7<:34a?xu3;10;6?uQ3g;89<?=;o30(>7<:34g?xu3;>0;6?uQ3g:89<?=;o20(>7<:34f?xu3;?0;6?uQ3g589<?=;o=0(>7<:34e?xu3;<0;6?uQ3g489<?=;o<0(>7<:353?xu3;=0;6?uQ3g789<?=;o?0(>7<:352?xu3;;0;6?uQ3g189<?=;o90(>7<:351?xu3;80;6?uQ3g089<?=;o80(>7<:350?xu3;90;6?uQ3g389<?=;o;0(>7<:357?xu3:o0;6?uQ3g289<?=;o:0(>7<:356?xu3:l0;6?uQ3dd89<?=;ll0(>7<:355?xu3:m0;6?uQ3dg89<?=;lo0(>7<:35;?xu3:j0;6?uQ3df89<?=;ln0(>7<:35:?xu3:k0;6?uQ3da89<?=;li0(>7<:35b?xu3:h0;6?uQ3d`89<?=;lh0(>7<:35a?xu3:00;6?uQ3dc89<?=;lk0(>7<:35`?xu3:>0;6?uQ3d:89<?=;l20(>7<:35g?xu3:?0;6?uQ3d589<?=;l=0(>7<:35f?xu3:<0;6?uQ3d489<?=;l<0(>7<:35e?xu3:=0;6?uQ3d789<?=;l?0(>7<:3:3?xu3::0;6?uQ3d689<?=;l>0(>7<:3:2?xu3:;0;6?uQ3d189<?=;l90(>7<:3:1?xu3:80;6?uQ3d089<?=;l80(>7<:3:0?xu3:90;6?uQ3d389<?=;l;0(>7<:3:7?xu39o0;6?uQ3d289<?=;l:0(>7<:3:6?xu39l0;6?uQ3ed89<?=;ml0(>7<:3:5?xu3=m0;6?uQ40a89<?=<8i0(>7<:3:4?xu3=j0;6?uQ40`89<?=<8h0(>7<:3:;?xu3=k0;6?uQ40c89<?=<8k0(>7<:3::?xu3=h0;6?uQ40789<?=<8?0(>7<:3:b?xu3==0;6?uQ41c89<?=<9k0(>7<:3:a?xu3<00;6?uQ3gd89<?=;ol0(>7<:3:g?xu3;l0;6?uQ3g689<?=;o>0(>7<:3:f?xu3;:0;6?uQ3d;89<?=;l30(>7<:3:e?xu3:10;6?uQ3eg89<?=;mo0(>7<:3;3?xu39m0;6?uQ3ef89<?=;mn0(>7<:3;2?xu2:80;6?uQ53389<?==;;0(>7<:3;1?xu28l0;6?uQ51g89<?==9o0(>7<:3;0?xu3lh0;6?uQ48c89<?=<0k0(>7<:32`?xu3l10;6?uQ48;89<?=<030(>7<:32g?xu3l>0;6?uQ48:89<?=<020(>7<:32f?xu3l?0;6?uQ48589<?=<0=0(>7<:32e?xu3l=0;6?uQ48789<?=<0?0(>7<:333?xu3l:0;6?uQ48689<?=<0>0(>7<:332?xu3l;0;6?uQ48189<?=<090(>7<:330?xu3l80;6?uQ48089<?=<080(>7<:337?xu3l90;6?uQ48389<?=<0;0(>7<:336?xu3ko0;6?uQ48289<?=<0:0(>7<:335?xu3kl0;6?uQ49d89<?=<1l0(>7<:334?xu3km0;6?uQ49g89<?=<1o0(>7<:33;?xu3kj0;6?uQ49f89<?=<1n0(>7<:33:?xu3kk0;6?uQ49a89<?=<1i0(>7<:33b?xu3k00;6?uQ49c89<?=<1k0(>7<:33a?xu3k10;6?uQ49;89<?=<130(>7<:33`?xu3k>0;6?uQ49:89<?=<120(>7<:33f?xu3k?0;6?uQ49589<?=<1=0(>7<:33e?xu3k<0;6?uQ49489<?=<1<0(>7<:303?xu3k=0;6?uQ49789<?=<1?0(>7<:302?xu3k:0;6?uQ49689<?=<1>0(>7<:301?xu3k;0;6?uQ49189<?=<190(>7<:300?xu3k80;6?uQ49089<?=<180(>7<:307?xu3k90;6?uQ49389<?=<1;0(>7<:306?xu3jl0;6?uQ46d89<?=<>l0(>7<:305?xu3jm0;6?uQ46g89<?=<>o0(>7<:304?xu3jj0;6?uQ46f89<?=<>n0(>7<:30:?xu3jk0;6?uQ46a89<?=<>i0(>7<:30b?xu3jh0;6?uQ46`89<?=<>h0(>7<:30a?xu3j00;6?uQ46c89<?=<>k0(>7<:30`?xu3j10;6?uQ46;89<?=<>30(>7<:30g?xu3j>0;6?uQ46:89<?=<>20(>7<:30f?xu3j?0;6?uQ46589<?=<>=0(>7<:30e?xu3j<0;6?uQ46489<?=<><0(>7<:313?xu3j:0;6?uQ46689<?=<>>0(>7<:312?xu3j;0;6?uQ46189<?=<>90(>7<:311?xu3j80;6?uQ46089<?=<>80(>7<:317?xu3j90;6?uQ46389<?=<>;0(>7<:316?xu3io0;6?uQ46289<?=<>:0(>7<:315?xu3il0;6?uQ47d89<?=<?l0(>7<:314?xu3im0;6?uQ47g89<?=<?o0(>7<:31;?xu3ij0;6?uQ47f89<?=<?n0(>7<:31:?xu3ik0;6?uQ47a89<?=<?i0(>7<:31b?xu3ih0;6?uQ47`89<?=<?h0(>7<:31a?xu3i10;6?uQ47;89<?=<?30(>7<:31`?xu3i>0;6?uQ47:89<?=<?20(>7<:31g?xu3i?0;6?uQ47589<?=<?=0(>7<:31e?xu3i<0;6?uQ47489<?=<?<0(>7<:363?xu3i=0;6?uQ47789<?=<??0(>7<:362?xu3i:0;6?uQ47689<?=<?>0(>7<:361?xu3i;0;6?uQ47189<?=<?90(>7<:360?xu3i80;6?uQ47089<?=<?80(>7<:367?xu3i90;6?uQ47389<?=<?;0(>7<:366?xu31o0;6?uQ47289<?=<?:0(>7<:365?xu3ll0;6?uQ48f89<?=<0n0(>7<:364?xu3lm0;6?uQ48a89<?=<0i0(>7<:36;?xu3lj0;6?uQ48`89<?=<0h0(>7<:36b?xu3lk0;6?uQ48489<?=<0<0(>7<:36a?xu3l<0;6?uQ49`89<?=<1h0(>7<:36`?xu3kh0;6?uQ49289<?=<1:0(>7<:36g?xu3jo0;6?uQ46789<?=<>?0(>7<:36f?xu3j=0;6?uQ47c89<?=<?k0(>7<:36e?xu3i00;6?uQ44d89<?=<<l0(>7<:373?xu31l0;6?uQ44g89<?=<<o0(>7<:372?xu3m;0;6?uQ4d089<?=<l80(>7<:371?xu3m90;6?uQ4d289<?=<l:0(>7<:377?x{i=hh1<7<tH2;7?xh2ij0;6?uG3868yk3fl3:1>vF<959~j0gb2909wE=64:m1d`=838pD>7;;|l6f5<72;qC?4:4}o7a5?6=:rB8595rn4`1>5<5sA9286sa5c194?4|@:3?7p`:b583>7}O;0>0qc;m5;296~N41=1vb8l9:181M5><2we9o950;0xL6?33td>n54?:3yK7<2<ug?i57>52zJ0=1=zf<hj6=4={I1:0>{i=kh1<7<tH2;7?xh2jj0;6?uG3868yk3el3:1>vF<959~j0db2909wE=64:m1g`=838pD>7;;|l6g5<72;qC?4:4}o7`5?6=:rB8595rn4a1>5<5sA9286sa5b194?4|@:3?7p`:c583>7}O;0>0qc;l5;296~N41=1vb8m9:181M5><2we9n950;0xL6?33td>o54?:3yK7<2<ug?h57>52zJ0=1=zf<ij6=4={I1:0>{i=jh1<7<tH2;7?xh2kj0;6?uG3868yk3dl3:1>vF<959~j0eb2909wE=64:m1f`=838pD>7;;|l6`5<72;qC?4:4}o7g5?6=:rB8595rn4f1>5<5sA9286sa5e194?4|@:3?7p`:d583>7}O;0>0qc;k5;296~N41=1vb8j9:181M5><2we9i950;0xL6?33td>h54?:3yK7<2<ug?o57>52zJ0=1=zf<nj6=4={I1:0>{i=mh1<7<tH2;7?xh2lj0;6?uG3868yk3cl3:1>vF<959~j0bb2909wE=64:m1a`=838pD>7;;|l6a5<72;qC?4:4}o7f5?6=:rB8595rn4g1>5<5sA9286sa5d194?4|@:3?7p`:e583>7}O;0>0qc;j5;296~N41=1vb8k9:181M5><2we9h950;0xL6?33td>i54?:3yK7<2<ug?n57>52zJ0=1=zf<oj6=4={I1:0>{i=lh1<7<tH2;7?xh2mj0;6?uG3868yk3bl3:1>vF<959~j0cb2909wE=64:m1``=838pD>7;;|l6b5<72;qC?4:4}o7e5?6=:rB8595rn4d1>5<5sA9286sa5g194?4|@:3?7p`:f583>7}O;0>0qc;i5;296~N41=1vb8h9:181M5><2we9k950;0xL6?33td>j54?:3yK7<2<ug?m57>52zJ0=1=zf<lj6=4={I1:0>{i=oh1<7<tH2;7?xh2nj0;6?uG3868yk3al3:1>vF<959~j0`b2909wE=64:m1c`=838pD>7;;|l545<72;qC?4:4}o435?6=:rB8595rn721>5<5sA9286sa61194?4|@:3?7p`90583>7}O;0>0qc8?5;296~N41=1vb;>9:181M5><2we:=950;0xL6?33td=<54?:3yK7<2<ug<;57>52zJ0=1=zf?:j6=4={I1:0>{i>9h1<7<tH2;7?xh18j0;6?uG3868yk07l3:1>vF<959~j36b2909wE=64:m25`=838pD>7;;|l555<72;qC?4:4}o425?6=:rB8595rn731>5<5sA9286sa60194?4|@:3?7p`91583>7}O;0>0qc8>5;296~N41=1vb;?9:181M5><2we:<950;0xL6?33td==54?:3yK7<2<ug<:57>52zJ0=1=zf?;j6=4={I1:0>{i>8h1<7<tH2;7?xh19j0;6?uG3868yk06l3:1>vF<959~j37b2909wE=64:m24`=838pD>7;;|l565<72;qC?4:4}o415?6=:rB8595rn701>5<5sA9286sa63194?4|@:3?7p`92583>7}O;0>0qc8=5;296~N41=1vb;<9:181M5><2we:?950;0xL6?33td=>54?:3yK7<2<ug<957>52zJ0=1=zf?8j6=4={I1:0>{i>;h1<7<tH2;7?xh1:j0;6?uG3868yk05l3:1>vF<959~j34b2909wE=64:m27`=838pD>7;;|l575<72;qC?4:4}o405?6=:rB8595rn427>5<6sA9286sa55594?7|@:3?7p`:4983>4}O;0>0qc;;9;295~N41=1vb8:n:182M5><2we99l50;3xL6?33td>8n4?:0yK7<2<ug??h7>51zJ0=1=zf<>n6=4>{I1:0>{i==l1<7?tH2;7?xh2=90;6<uG3868yk3293:1=vF<959~j035290:wE=64:m105=83;pD>7;;|l611<728qC?4:4}o761?6=9rB8595rn475>5<6sA9286sa54594?7|@:3?7p`:5983>4}O;0>0qc;:9;295~N41=1vb8;n:182M5><2we98l50;3xL6?33td>9n4?:0yK7<2<ug?>h7>51zJ0=1=zf<?n6=4>{I1:0>{i=<l1<7?tH2;7?xh2>90;6<uG3868yk3193:1=vF<959~j005290:wE=64:m135=83;pD>7;;|l621<728qC?4:4}o751?6=9rB8595rn445>5<6sA9286sa57594?7|@:3?7p`:6983>4}O;0>0qc;99;295~N41=1vb88n:182M5><2we9;l50;3xL6?33td>:n4?:0yK7<2<ug?=h7>51zJ0=1=zf<<n6=4>{I1:0>{i=?l1<7?tH2;7?xh2?90;6<uG3868yk3093:1=vF<959~j015290:wE=64:m125=83;pD>7;;|l631<728qC?4:4}o741?6=9rB8595rn455>5<6sA9286sa56594?7|@:3?7p`:7983>4}O;0>0qc;89;295~N41=1vb89n:182M5><2we9:l50;3xL6?33td>;n4?:0yK7<2<ug?<h7>51zJ0=1=zf<=n6=4>{I1:0>{i=>l1<7?tH2;7?xh2090;6<uG3868yk3?93:1=vF<959~j0>5290:wE=64:m1=5=83;pD>7;;|l6<1<728qC?4:4}o7;1?6=9rB8595rn4:5>5<6sA9286sa59594?7|@:3?7p`:8983>4}O;0>0qc;79;295~N41=1vb86n:182M5><2we95l50;3xL6?33td>4n4?:0yK7<2<ug?3h7>51zJ0=1=zf<2n6=4>{I1:0>{i=1l1<7?tH2;7?xh2190;6<uG3868yk3>93:1=vF<959~j0?5290:wE=64:m1<5=83;pD>7;;|l6=1<728qC?4:4}o7:1?6=9rB8595rn4;5>5<6sA9286sa58594?7|@:3?7p`:9983>4}O;0>0qc;69;295~N41=1vb87n:182M5><2we94l50;3xL6?33td>5n4?:0yK7<2<ug?2h7>51zJ0=1=zf<3n6=4>{I1:0>{i=0l1<7?tH2;7?xh2i90;6<uG3868yk3f93:1=vF<959~j0g5290:wE=64:m1d5=83;pD>7;;|l6e1<728qC?4:4}o7b1?6=9rB8595rn4c5>5<6sA9286sa5`594?7|@:3?7p`:a983>4}O;0>0qc;n9;295~N41=1vb8on:182M5><2wvqpNOCz52a?4a8kho?=sO@Cy3yEFWstJK
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/xst.prj b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/xst.prj
deleted file mode 100644
index e5cec87..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/xst.prj
+++ /dev/null
@@ -1,72 +0,0 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : xst.prj 
-## /___/   /\     
-## \   \  /  \
-##  \___\/\___\
-##
-##
-## xst.prj
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-vhdl work "../example_design/mgt_usrclk_source_mmcm.vhd"
-vhdl work "../example_design/gtxvirtex6fee80_tx_sync.vhd"
-vhdl work "../example_design/gtxvirtex6fee80_rx_sync.vhd"
-vhdl work "../example_design/double_reset.vhd"
-vhdl work "../example_design/frame_gen.vhd"
-vhdl work "../example_design/frame_check.vhd"
-vhdl work "../../gtxvirtex6fee80_gtx.vhd"
-vhdl work "../../gtxvirtex6fee80.vhd"
-vhdl work "../example_design/gtxvirtex6fee80_top.vhd"
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/xst.scr b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/xst.scr
deleted file mode 100644
index acf8a5a..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/implement/xst.scr
+++ /dev/null
@@ -1,99 +0,0 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : xst.scr 
-## /___/   /\     
-## \   \  /  \
-##  \___\/\___\
-##
-##
-## xst.scr 
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-run
--ifn xst.prj
--ifmt mixed 
--ofn gtxVirtex6FEE80_top.ngc 
--ofmt NGC
--p xc6vlx130t-3ff484
--top gtxVirtex6FEE80_top
--opt_mode Speed
--opt_level 1
--iuc NO
--keep_hierarchy NO
--glob_opt AllClockNets
--rtlview Yes
--read_cores YES
--write_timing_constraints NO
--cross_clock_analysis NO
--hierarchy_separator /
--bus_delimiter ()
--case maintain
--slice_utilization_ratio 100
--fsm_extract YES
--fsm_encoding Auto
--ram_extract No
--ram_style Auto
--rom_extract No
--rom_style Auto
--shreg_extract YES
--resource_sharing YES
--mult_style auto
--iobuf YES
--max_fanout REDUCE
--bufg 16
--register_duplication YES
--signal_encoding user
--iob true
--slice_utilization_ratio_maxmargin 5
--uc ../example_design/gtxVirtex6FEE80_top.xcf
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/demo_tb.vhd b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/demo_tb.vhd
deleted file mode 100644
index 9421bcd..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/demo_tb.vhd
+++ /dev/null
@@ -1,266 +0,0 @@
---------------------------------------------------------------------------------
---   ____  ____ 
---  /   /\/   / 
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard 
---  /   /         Filename : demo_tb.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\ 
---
---
--- Module DEMO_TB
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard 
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-library std;                  -- for Printing
-use std.textio.all;
-
-entity DEMO_TB is
-end DEMO_TB;
-
-architecture RTL of DEMO_TB is
-
---*************************Parameter Declarations******************************
-
-    constant   TX_REFCLK_PERIOD        :   time :=  12.5 ns;
-    constant   RX_REFCLK_PERIOD        :   time :=  12.5 ns;    
-  
---**************************** Component Declarations *************************
-
-    component gtxVirtex6FEE80_top 
-    generic
-    (
-        EXAMPLE_CONFIG_INDEPENDENT_LANES: integer    := 1;
-        EXAMPLE_LANE_WITH_START_CHAR    : integer    := 0;
-        EXAMPLE_WORDS_IN_BRAM           : integer    := 512;
-        EXAMPLE_SIM_GTXRESET_SPEEDUP    : integer    := 1;
-        EXAMPLE_USE_CHIPSCOPE           : integer    := 0     --0 - drive resets from top level ports
-    );
-    port
-    (
-        Q3_CLK0_MGTREFCLK_PAD_N_IN   :   in std_logic;
-        Q3_CLK0_MGTREFCLK_PAD_P_IN   :   in std_logic;
-        GTXTXRESET_IN                     :   in std_logic;
-        GTXRXRESET_IN                     :   in std_logic;
-        TRACK_DATA_OUT                    :   out std_logic;
-        RXN_IN                            :   in std_logic;
-        RXP_IN                            :   in std_logic;
-        TXN_OUT                           :   out std_logic;
-        TXP_OUT                           :   out std_logic
-    );
-    end component;
-
-    component SIM_RESET_MGT_MODEL 
-    port 
-    (
-        GSR_IN     : in std_logic
-    );
-    end component;
-
---************************Internal Register Declarations***********************
-
---************************** Register Declarations ****************************        
-
-    signal  tx_refclk_n_r           :   std_logic;
-    signal  rx_refclk_n_r           :   std_logic;
-    signal  drp_clk_r               :   std_logic;
-    signal  tx_usrclk_r             :   std_logic;
-    signal  rx_usrclk_r             :   std_logic;
-    signal  gsr_r                   :   std_logic;
-    signal  gts_r                   :   std_logic;
-    signal  reset_i                 :   std_logic;
-    signal  track_data_high_r       :   std_logic;
-    signal  track_data_low_r        :   std_logic;    
-
---********************************Wire Declarations**********************************
-    
-    ----------------------------------- Global Signals ------------------------------
-    signal  tx_refclk_p_r           :   std_logic;
-    signal  rx_refclk_p_r           :   std_logic;    
-    signal  tied_to_ground_i        :   std_logic;
-    ---------------------------- Example Module Connections -------------------------
-    signal  rxn_in_i                :   std_logic;
-    signal  rxp_in_i                :   std_logic;
-    signal  txn_out_i               :   std_logic;
-    signal  txp_out_i               :   std_logic;
-
-
-    signal  gtx0_txplllkdet_i     :   std_logic;
-    signal  gtx0_rxplllkdet_i     :   std_logic;    
-
-    signal  track_data_i            :   std_logic;
-
-
---*********************************Main Body of Code**********************************
-begin
-
-    -- ------------------------------- Tie offs ------------------------------- 
-    
-    tied_to_ground_i        <=  '0';
-    
-    -- ------------------------- MGT Serial Connections -----------------------
-
-    rxn_in_i                <=  txn_out_i;
-    rxp_in_i                <=  txp_out_i;  
-
-    ------- Instantiate the ROC module for resetting the VHDL MGT Smart Model ------
-    ------- Instantiate SIM_RESET_MGT_MODEL module only for Functional simulation ------
-    ------- For Timing simulation please comment out the instance of SIM_RESET_MGT_MODEL ------
-
-    sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL  
-    port map    
-    (
-        GSR_IN           =>           reset_i
-    );
-
-    ---------------------- Generate Reference Clock input  --------------------
-    
-    process
-    begin
-        tx_refclk_n_r  <=  '1';
-        wait for TX_REFCLK_PERIOD/2;
-        tx_refclk_n_r  <=  '0';
-        wait for TX_REFCLK_PERIOD/2;
-    end process;
-
-    tx_refclk_p_r <= not tx_refclk_n_r;
-    
-    process
-    begin
-        rx_refclk_n_r  <=  '1';
-        wait for RX_REFCLK_PERIOD/2;
-        rx_refclk_n_r  <=  '0';
-        wait for RX_REFCLK_PERIOD/2;
-    end process;
-
-    rx_refclk_p_r <= not rx_refclk_n_r;
-                 
-
- 
-                
-    ----------------------------------- Resets ---------------------------------
-    
-    process
-    begin
-        reset_i <= '1';
-        wait for 100 ns;
-        reset_i <= '0';
-        wait; 
-    end process;
-
-    -------------------------------- Track Data --------------------------------
-    
-    process
-
-    procedure tbprint (message : in string) is
-      variable outline : line;
-    begin
-      write(outline, string'("## Time: "));
-      write(outline, NOW, RIGHT, 0, ps);
-      write(outline, string'("  "));
-      write(outline, string'(message)); 
-      writeline(output,outline);
-    end tbprint;
-
-
-    begin
-        track_data_high_r <= '0';
-        wait for 223 us;
-        if (track_data_i = '1') then
-            track_data_high_r <= '1';
-        end if;
-        wait for 2 us;
-        if ((track_data_high_r = '1') and (track_data_low_r = '0')) then
-            tbprint("------- TEST PASSED -------");
-            assert false report "Simulation Stopped." severity failure;
-        else
-            tbprint("####### ERROR: TEST FAILED ! #######");
-            assert false report "Test Failed." severity failure;
-        end if;
-    end process;
-    
-    process
-    begin
-        track_data_low_r <= '0';
-        wait for 223 us;
-        wait until track_data_i = '0';
-        track_data_low_r <= '1';
-    end process; 
-    ------------------- Instantiate an gtxVirtex6FEE80_top module  -----------------
-
-    gtxVirtex6FEE80_top_i : gtxVirtex6FEE80_top
-    generic map
-    (
-        EXAMPLE_SIM_GTXRESET_SPEEDUP=>  1,        -- Speedup is turned on for simulation
-        EXAMPLE_USE_CHIPSCOPE       =>  0         --1 - use chipscope to drive resets,
-                                                  --0 - drive resets from top level ports
-    )
-    port map
-    (
-        Q3_CLK0_MGTREFCLK_PAD_N_IN       =>  rx_refclk_n_r,
-        Q3_CLK0_MGTREFCLK_PAD_P_IN       =>  rx_refclk_p_r,
-        GTXTXRESET_IN               =>  reset_i,
-        GTXRXRESET_IN               =>  reset_i,
-        TRACK_DATA_OUT              =>  track_data_i,
-        RXN_IN                      =>  rxn_in_i,
-        RXP_IN                      =>  rxp_in_i,
-        TXN_OUT                     =>  txn_out_i,
-        TXP_OUT                     =>  txp_out_i
-    );
-
-end RTL;
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/demo_tb_imp.vhd b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/demo_tb_imp.vhd
deleted file mode 100644
index f5e41e3..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/demo_tb_imp.vhd
+++ /dev/null
@@ -1,251 +0,0 @@
---------------------------------------------------------------------------------
---   ____  ____ 
---  /   /\/   / 
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard 
---  /   /         Filename : demo_tb.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\ 
---
---
--- Module DEMO_TB_IMP
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard 
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-library std;                  -- for Printing
-use std.textio.all;
-
-entity DEMO_TB_IMP is
-end DEMO_TB_IMP;
-
-architecture RTL of DEMO_TB_IMP is
-
---*************************Parameter Declarations******************************
-
-    constant   TX_REFCLK_PERIOD        :   time :=  12.5 ns;
-    constant   RX_REFCLK_PERIOD        :   time :=  12.5 ns;    
-  
---**************************** Component Declarations *************************
-
-    component gtxVirtex6FEE80_top 
-    port
-    (
-        Q3_CLK0_MGTREFCLK_PAD_N_IN   :   in std_logic;
-        Q3_CLK0_MGTREFCLK_PAD_P_IN   :   in std_logic;
-        GTXTXRESET_IN                     :   in std_logic;
-        GTXRXRESET_IN                     :   in std_logic;
-        TRACK_DATA_OUT                    :   out std_logic;
-        RXN_IN                            :   in std_logic;
-        RXP_IN                            :   in std_logic;
-        TXN_OUT                           :   out std_logic;
-        TXP_OUT                           :   out std_logic
-    );
-    end component;
-
-    component SIM_RESET_MGT_MODEL 
-    port 
-    (
-        GSR_IN     : in std_logic
-    );
-    end component;
-
---************************Internal Register Declarations***********************
-
---************************** Register Declarations ****************************        
-
-    signal  tx_refclk_n_r           :   std_logic;
-    signal  rx_refclk_n_r           :   std_logic;
-    signal  drp_clk_r               :   std_logic;
-    signal  tx_usrclk_r             :   std_logic;
-    signal  rx_usrclk_r             :   std_logic;
-    signal  gsr_r                   :   std_logic;
-    signal  gts_r                   :   std_logic;
-    signal  reset_i                 :   std_logic;
-    signal  track_data_high_r       :   std_logic;
-    signal  track_data_low_r        :   std_logic;    
-
---********************************Wire Declarations**********************************
-    
-    ----------------------------------- Global Signals ------------------------------
-    signal  tx_refclk_p_r           :   std_logic;
-    signal  rx_refclk_p_r           :   std_logic;    
-    signal  tied_to_ground_i        :   std_logic;
-    ---------------------------- Example Module Connections -------------------------
-    signal  rxn_in_i                :   std_logic;
-    signal  rxp_in_i                :   std_logic;
-    signal  txn_out_i               :   std_logic;
-    signal  txp_out_i               :   std_logic;
-
-
-    signal  gtx0_txplllkdet_i     :   std_logic;
-    signal  gtx0_rxplllkdet_i     :   std_logic;    
-
-    signal  track_data_i            :   std_logic;
-
-
---*********************************Main Body of Code**********************************
-begin
-
-    -- ------------------------------- Tie offs ------------------------------- 
-    
-    tied_to_ground_i        <=  '0';
-    
-    -- ------------------------- MGT Serial Connections -----------------------
-
-    rxn_in_i                <=  txn_out_i;
-    rxp_in_i                <=  txp_out_i;  
-
-    ------- Instantiate the ROC module for resetting the VHDL MGT Smart Model ------
-    ------- Instantiate SIM_RESET_MGT_MODEL module only for Functional simulation ------
-    ------- For Timing simulation please comment out the instance of SIM_RESET_MGT_MODEL ------
-
-    sim_reset_mgt_model_i : SIM_RESET_MGT_MODEL  
-    port map    
-    (
-        GSR_IN           =>           reset_i
-    );
-
-    ---------------------- Generate Reference Clock input  --------------------
-    
-    process
-    begin
-        tx_refclk_n_r  <=  '1';
-        wait for TX_REFCLK_PERIOD/2;
-        tx_refclk_n_r  <=  '0';
-        wait for TX_REFCLK_PERIOD/2;
-    end process;
-
-    tx_refclk_p_r <= not tx_refclk_n_r;
-    
-    process
-    begin
-        rx_refclk_n_r  <=  '1';
-        wait for RX_REFCLK_PERIOD/2;
-        rx_refclk_n_r  <=  '0';
-        wait for RX_REFCLK_PERIOD/2;
-    end process;
-
-    rx_refclk_p_r <= not rx_refclk_n_r;
-                 
-
- 
-                
-    ----------------------------------- Resets ---------------------------------
-    
-    process
-    begin
-        reset_i <= '1';
-        wait for 100 ns;
-        reset_i <= '0';
-        wait; 
-    end process;
-
-    -------------------------------- Track Data --------------------------------
-    
-    process
-
-    procedure tbprint (message : in string) is
-      variable outline : line;
-    begin
-      write(outline, string'("## Time: "));
-      write(outline, NOW, RIGHT, 0, ps);
-      write(outline, string'("  "));
-      write(outline, string'(message)); 
-      writeline(output,outline);
-    end tbprint;
-
-    begin
-        track_data_high_r <= '0';
-        wait for 223 us;
-        if (track_data_i = '1') then
-            track_data_high_r <= '1';
-        end if;
-        wait for 2 us;
-        if ((track_data_high_r = '1') and (track_data_low_r = '0')) then
-            tbprint("------- TEST PASSED -------");
-            assert false report "Simulation Stopped." severity failure;
-        else
-            tbprint("####### ERROR: TEST FAILED ! #######");
-            assert false report "Test Failed." severity failure;
-        end if;
-    end process;
-    
-    process
-    begin
-        track_data_low_r <= '0';
-        wait for 223 us;
-        wait until track_data_i = '0';
-        track_data_low_r <= '1';
-    end process; 
-    ------------------- Instantiate an gtxVirtex6FEE80_top module  -----------------
-
-    gtxVirtex6FEE80_top_i : gtxVirtex6FEE80_top
-    port map
-    (
-        Q3_CLK0_MGTREFCLK_PAD_N_IN       =>  rx_refclk_n_r,
-        Q3_CLK0_MGTREFCLK_PAD_P_IN       =>  rx_refclk_p_r,
-        GTXTXRESET_IN               =>  reset_i,
-        GTXRXRESET_IN               =>  reset_i,
-        TRACK_DATA_OUT              =>  track_data_i,
-        RXN_IN                      =>  rxn_in_i,
-        RXP_IN                      =>  rxp_in_i,
-        TXN_OUT                     =>  txn_out_i,
-        TXP_OUT                     =>  txp_out_i
-    );
-
-end RTL;
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_isim.bat b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_isim.bat
deleted file mode 100755
index 10a0354..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_isim.bat
+++ /dev/null
@@ -1,92 +0,0 @@
-REM   ____  ____ 
-REM  /   /\/   / 
-REM /___/  \  /    Vendor: Xilinx 
-REM \   \   \/     Version : 1.12
-REM  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-REM  /   /         Filename : simulate_isim.bat
-REM /___/   /\     
-REM \   \  /  \ 
-REM  \___\/\___\ 
-REM
-REM
-REM Script SIMULATE_ISIM.BAT
-REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-REM
-REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-REM
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and
-REM international copyright and other intellectual property
-REM laws.
-REM
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM 
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-
-
-REM ***************************** Beginning of Script ***************************
-        
-REM Create and map work directory
-mkdir work
-
-REM MGT Wrapper
-vhpcomp -work work  ..\..\..\gtxvirtex6fee80_gtx.vhd
-vhpcomp -work work  ..\..\..\gtxvirtex6fee80.vhd
-
-
-REM Clock Modules 
-vhpcomp -work work  ..\..\example_design\mgt_usrclk_source_mmcm.vhd
-
-REM Example Design modules
-vhpcomp -work work  ..\..\example_design\gtxvirtex6fee80_tx_sync.vhd
-vhpcomp -work work  ..\..\example_design\gtxvirtex6fee80_rx_sync.vhd
-vhpcomp -work work  ..\..\example_design\double_reset.vhd
-vhpcomp -work work  ..\..\example_design\frame_gen.vhd
-vhpcomp -work work  ..\..\example_design\frame_check.vhd
-vhpcomp -work work  ..\..\example_design\gtxvirtex6fee80_top.vhd
-
-vhpcomp -work work  ..\demo_tb.vhd
-
-REM Other modules
-vhpcomp -work work ..\sim_reset_mgt_model.vhd
-
-REM Load Design
-fuse work.DEMO_TB -L unisim -L secureip -o demo_tb.exe
-
-.\demo_tb.exe -gui -tclbatch wave_isim.tcl -wdb wave_isim  
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_isim.sh b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_isim.sh
deleted file mode 100644
index 1419fef..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_isim.sh
+++ /dev/null
@@ -1,94 +0,0 @@
-#!/bin/sh
-################################################################################
-##   ____  ____ 
-##  /   /\/   / 
-## /___/  \  /    Vendor: Xilinx 
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : simulate_isim.sh
-## /___/   /\     
-## \   \  /  \ 
-##  \___\/\___\ 
-##
-##
-## Script SIMULATE_ISIM.SH
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-
-##***************************** Beginning of Script ***************************
-        
-## Create and map work directory
-mkdir work
-
-##MGT Wrapper
-vhpcomp -work work  ../../../gtxvirtex6fee80_gtx.vhd;
-vhpcomp -work work  ../../../gtxvirtex6fee80.vhd;
-
-
-##Clock Modules 
-vhpcomp -work work  ../../example_design/mgt_usrclk_source_mmcm.vhd;
-
-##Example Design modules
-vhpcomp -work work  ../../example_design/gtxvirtex6fee80_tx_sync.vhd;
-vhpcomp -work work  ../../example_design/gtxvirtex6fee80_rx_sync.vhd;
-vhpcomp -work work  ../../example_design/double_reset.vhd;
-vhpcomp -work work  ../../example_design/frame_gen.vhd;
-vhpcomp -work work  ../../example_design/frame_check.vhd;
-vhpcomp -work work  ../../example_design/gtxvirtex6fee80_top.vhd;
-
-vhpcomp -work work  ../demo_tb.vhd;
-
-##Other modules
-vhpcomp -work work ../sim_reset_mgt_model.vhd;
-
-##Load Design
-fuse work.DEMO_TB -L unisim -L secureip -o demo_tb.exe
-
-./demo_tb.exe -gui -tclbatch wave_isim.tcl -wdb wave_isim  
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_mti.do b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_mti.do
deleted file mode 100644
index 49ecfa8..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_mti.do
+++ /dev/null
@@ -1,119 +0,0 @@
-################################################################################
-##   ____  ____ 
-##  /   /\/   / 
-## /___/  \  /    Vendor: Xilinx 
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : simulate_mti.do
-## /___/   /\     
-## \   \  /  \ 
-##  \___\/\___\ 
-##
-##
-## Script SIMULATE_MTI.DO
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-##***************************** Beginning of Script ***************************
-        
-## If MTI_LIBS is defined, map unisim and simprim directories using MTI_LIBS
-## This mode of mapping the unisims libraries is provided for backward 
-## compatibility with previous wizard releases. If you don't set MTI_LIBS
-## the unisim libraries will be loaded from the paths set up by compxlib in
-## your modelsim.ini file
-
-set XILINX   $env(XILINX)
-if [info exists env(MTI_LIBS)] {    
-    set MTI_LIBS $env(MTI_LIBS)
-    vlib UNISIM
-    vlib SECUREIP
-    vmap UNISIM $MTI_LIBS/unisim
-    vmap SECUREIP $MTI_LIBS/secureip
-   
-}
-   
-
-## Create and map work directory
-vlib work
-vmap work work
-
-##MGT Wrapper
-vcom -93 -work work  ../../../gtxvirtex6fee80_gtx.vhd;
-vcom -93 -work work  ../../../gtxvirtex6fee80.vhd;
-
-
-##Clock Modules 
-vcom -93 -work work  ../../example_design/mgt_usrclk_source_mmcm.vhd;
-
-
-##Example Design modules
-vcom -93 -work work  ../../example_design/gtxvirtex6fee80_tx_sync.vhd;
-vcom -93 -work work  ../../example_design/gtxvirtex6fee80_rx_sync.vhd;
-vcom -93 -work work  ../../example_design/double_reset.vhd;
-vcom -93 -work work  ../../example_design/frame_gen.vhd;
-vcom -93 -work work  ../../example_design/frame_check.vhd;
-vcom -93 -work work  ../../example_design/gtxvirtex6fee80_top.vhd;
-
-vcom -93 -work work  ../demo_tb.vhd;
-
-##Other modules
-vcom -93 -work work ../sim_reset_mgt_model.vhd;
-
-##Load Design
-vsim -t 1ps work.DEMO_TB -voptargs="+acc" 
-
-
-##Load signals in wave window
-view wave
-do wave_mti.do
-
-##Run simulation
-run 226 us
-
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_ncsim.bat b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_ncsim.bat
deleted file mode 100755
index e8dcb49..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_ncsim.bat
+++ /dev/null
@@ -1,98 +0,0 @@
-REM ############################################################################
-REM   ____  ____ 
-REM  /   /\/   / 
-REM /___/  \  /    Vendor: Xilinx 
-REM \   \   \/     Version : 1.12
-REM  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-REM  /   /         Filename : simulate_ncsim.bat
-REM /___/   /\      
-REM \   \  /  \ 
-REM  \___\/\___\ 
-REM
-REM
-REM Script SIMULATE_NCSIM.BAT
-REM Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-REM
-REM (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-REM 
-REM This file contains confidential and proprietary information
-REM of Xilinx, Inc. and is protected under U.S. and 
-REM international copyright and other intellectual property
-REM laws.
-REM 
-REM DISCLAIMER
-REM This disclaimer is not a license and does not grant any
-REM rights to the materials distributed herewith. Except as
-REM otherwise provided in a valid license issued to you by
-REM Xilinx, and to the maximum extent permitted by applicable
-REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-REM (2) Xilinx shall not be liable (whether in contract or tort,
-REM including negligence, or under any other theory of
-REM liability) for any loss or damage of any kind or nature
-REM related to, arising under or in connection with these
-REM materials, including for any direct, or any indirect,
-REM special, incidental, or consequential loss or damage
-REM (including loss of data, profits, goodwill, or any type of
-REM loss or damage suffered as a result of any action brought
-REM by a third party) even if such damage or loss was
-REM reasonably foreseeable or Xilinx had been advised of the
-REM possibility of the same.
-REM
-REM CRITICAL APPLICATIONS
-REM Xilinx products are not designed or intended to be fail-
-REM safe, or for use in any application requiring fail-safe
-REM performance, such as life-support or safety devices or
-REM systems, Class III medical devices, nuclear facilities,
-REM applications related to the deployment of airbags, or any
-REM other applications that could lead to death, personal
-REM injury, or severe property or environmental damage
-REM (individually and collectively, "Critical
-REM Applications"). Customer assumes the sole risk and
-REM liability of any use of Xilinx products in Critical
-REM Applications, subject only to applicable laws and
-REM regulations governing limitations on product liability.
-REM
-REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-REM PART OF THIS FILE AT ALL TIMES.
-
-REM **************************** Beginning of Script ***************************
-
-        
-REM Ensure the follwoing
-REM The library paths for UNISIMS_VER, SIMPRIMS_VER, XILINXCORELIB_VER,
-REM UNISIM, SIMPRIM, XILINXCORELIB are set correctly in the cds.lib and hdl.var files.
-REM Variables LMC_HOME and XILINX are set 
-REM Define the mapping for the work library in cds.lib file. DEFINE work ./work
-
-mkdir work
-REM MGT Wrapper
-ncvhdl -RELAX -V93 -work work   ..\..\..\gtxvirtex6fee80_gtx.vhd
-ncvhdl -RELAX -V93 -work work   ..\..\..\gtxvirtex6fee80.vhd
-
-
- 
-REM Clock Modules 
-ncvhdl -RELAX -V93 -work work  ..\..\example_design\mgt_usrclk_source_mmcm.vhd
-
-REM Example Design modules
-ncvhdl -RELAX -V93 -work work  ..\..\example_design\gtxvirtex6fee80_tx_sync.vhd
-ncvhdl -RELAX -V93 -work work  ..\..\example_design\gtxvirtex6fee80_rx_sync.vhd
-ncvhdl -RELAX -V93 -work work  ..\..\example_design\double_reset.vhd
-ncvhdl -RELAX -V93 -work work  ..\..\example_design\frame_gen.vhd
-ncvhdl -RELAX -V93 -work work  ..\..\example_design\frame_check.vhd
-ncvhdl -RELAX -V93 -work work  ..\..\example_design\gtxvirtex6fee80_top.vhd
-
-ncvhdl -RELAX -V93 -work work  ..\demo_tb.vhd
-
-REM Other modules
-ncvhdl -RELAX -V93 -work work ..\sim_reset_mgt_model.vhd
-
-REM Elaborate Design
-ncelab -relax -TIMESCALE 1ns/1ps -ACCESS +rwc work.DEMO_TB
-
-ncsim +access+rw work.DEMO_TB -input @"simvision -input wave_ncsim.sv" 
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_ncsim.sh b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_ncsim.sh
deleted file mode 100644
index 51e9633..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_ncsim.sh
+++ /dev/null
@@ -1,99 +0,0 @@
-#!/bin/sh
-################################################################################
-##   ____  ____ 
-##  /   /\/   / 
-## /___/  \  /    Vendor: Xilinx 
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : simulate_ncsim.sh
-## /___/   /\      
-## \   \  /  \ 
-##  \___\/\___\ 
-##
-##
-## Script SIMULATE_NCSIM.SH
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-##***************************** Beginning of Script ***************************
-        
-#Ensure the follwoing
-#The library paths for UNISIMS_VER, SIMPRIMS_VER, XILINXCORELIB_VER,
-#UNISIM, SIMPRIM, XILINXCORELIB are set correctly in the cds.lib and hdl.var files.
-#Variables LMC_HOME and XILINX are set 
-#Define the mapping for the work library in cds.lib file. DEFINE work ./work
-
-mkdir work
-##MGT Wrapper
-ncvhdl -RELAX -V93 -work work   ../../../gtxvirtex6fee80_gtx.vhd;
-ncvhdl -RELAX -V93 -work work   ../../../gtxvirtex6fee80.vhd;
-
-
- 
-##Clock Modules 
-ncvhdl -RELAX -V93 -work work  ../../example_design/mgt_usrclk_source_mmcm.vhd;
-
-##Example Design modules
-ncvhdl -RELAX -V93 -work work  ../../example_design/gtxvirtex6fee80_tx_sync.vhd;
-ncvhdl -RELAX -V93 -work work  ../../example_design/gtxvirtex6fee80_rx_sync.vhd;
-ncvhdl -RELAX -V93 -work work  ../../example_design/double_reset.vhd;
-ncvhdl -RELAX -V93 -work work  ../../example_design/frame_gen.vhd;
-ncvhdl -RELAX -V93 -work work  ../../example_design/frame_check.vhd;
-ncvhdl -RELAX -V93 -work work  ../../example_design/gtxvirtex6fee80_top.vhd;
-
-ncvhdl -RELAX -V93 -work work  ../demo_tb.vhd;
-
-##Other modules
-ncvhdl -RELAX -V93 -work work ../sim_reset_mgt_model.vhd;
-
-##Elaborate Design
-ncelab -relax -TIMESCALE 1ns/1ps -ACCESS +rwc work.DEMO_TB
-
-ncsim +access+rw work.DEMO_TB -input @"simvision -input wave_ncsim.sv" 
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_vcs.sh b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_vcs.sh
deleted file mode 100644
index ddd4bfa..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/simulate_vcs.sh
+++ /dev/null
@@ -1,86 +0,0 @@
-#!/bin/sh
-################################################################################
-##   ____  ____ 
-##  /   /\/   / 
-## /___/  \  /    Vendor: Xilinx 
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : simulate_vcs.sh
-## /___/   /\     
-## \   \  /  \ 
-##  \___\/\___\ 
-##
-##
-## Script SIMULATE_VCS.SH
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-## 
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-## 
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-## 
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-##***************************** Beginning of Script ***************************
-
-
-rm -rf simv* csrc DVEfiles AN.DB
-
-vhdlan \
-            ../../../gtxvirtex6fee80_gtx.vhd \
-            ../../../gtxvirtex6fee80.vhd \
-            ../../example_design/mgt_usrclk_source_mmcm.vhd \
-            ../../example_design/gtxvirtex6fee80_tx_sync.vhd \
-            ../../example_design/gtxvirtex6fee80_rx_sync.vhd \
-            ../../example_design/double_reset.vhd \
-            ../../example_design/frame_gen.vhd \
-            ../../example_design/frame_check.vhd \
-            ../../example_design/gtxvirtex6fee80_top.vhd \
-            ../demo_tb.vhd
-
-vcs +vcs+lic+wait \
-    -debug \
-    DEMO_TB
-./simv -ucli -i ucli_commands.key
-dve -vpd vcdplus.vpd -session vcs_session.tcl
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/ucli_commands.key b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/ucli_commands.key
deleted file mode 100644
index 4ae3cc1..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/ucli_commands.key
+++ /dev/null
@@ -1,66 +0,0 @@
-################################################################################
-##   ____  ____ 
-##  /   /\/   / 
-## /___/  \  /    Vendor: Xilinx 
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : ucli_commands.key
-## /___/   /\     
-## \   \  /  \ 
-##  \___\/\___\ 
-##
-##
-## Script UCLI_COMMANDS.KEY
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-## 
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-## 
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-## 
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-call {$vcdpluson}
-run
-call {$vcdplusclose}
-quit
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/vcs_session.tcl b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/vcs_session.tcl
deleted file mode 100644
index 993cc0e..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/vcs_session.tcl
+++ /dev/null
@@ -1,136 +0,0 @@
-################################################################################
-##   ____  ____ 
-##  /   /\/   / 
-## /___/  \  /    Vendor: Xilinx 
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : vcs_session.tcl
-## /___/   /\     
-## \   \  /  \ 
-##  \___\/\___\ 
-##
-##
-##
-## Script VCS_SESSION.TCL
-## Generated by Xilinx Virtex-6 FPGA GTH Transceiver Wizard
-##
-## 
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-## 
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-## 
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-  gui_open_window Wave
-  gui_sg_create gtxVirtex6FEE80_Group
-  gui_list_add_group -id Wave.1 {gtxVirtex6FEE80_Group}
-
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{FRAME_CHECK_MODULE}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:begin_r}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:track_data_r}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:data_error_detected_r}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:start_of_packet_detected_r}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:RX_DATA}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtx0_frame_check:ERROR_COUNT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{GTX0_GTXVIRTEX6FEE80}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - 8b10b Decoder}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCHARISK_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDISPERR_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXNOTINTABLE_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - Comma Detection and Alignment}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENMCOMMAALIGN_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPCOMMAALIGN_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Data Path interface}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDATA_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRECCLK_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESET_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXUSRCLK2_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCDRRESET_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXN_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXP_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Elastic Buffer and Phase Alignment Ports}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNDISABLE_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONENB_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONITOR_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNOVERRIDE_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNRESET_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPMAPHASEALIGN_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPMASETPHASE_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXSTATUS_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Loss-of-sync State Machine}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXLOSSOFSYNC_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX PLL Ports}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXRXRESET_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:MGTREFCLKRX_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PLLRXRESET_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPLLLKDET_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESETDONE_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Receive Ports - RX Pipe Control for PCI Express}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PHYSTATUS_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - 8b10b Encoder Control Ports}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXCHARISK_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - GTX Ports}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTEST_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX Data Path interface}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDATA_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXOUTCLK_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESET_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXUSRCLK2_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX Driver and OOB signaling}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXN_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXP_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX Elastic Buffer and Phase Alignment Ports}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNDISABLE_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONENB_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONITOR_OUT}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNRESET_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXENPMAPHASEALIGN_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXPMASETPHASE_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {{Transmit Ports - TX PLL Ports}} -divider
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTXRESET_IN}
-  gui_sg_addsignal -group gtxVirtex6FEE80_Group {:gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESETDONE_OUT}
-
-
-  gui_zoom -window Wave.1 -full
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/wave_isim.tcl b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/wave_isim.tcl
deleted file mode 100644
index 310729b..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/wave_isim.tcl
+++ /dev/null
@@ -1,120 +0,0 @@
-###############################################################################
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-
-
-wcfg new
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/begin_r
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/track_data_r
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/data_error_detected_r
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/start_of_packet_detected_r
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/RX_DATA
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/ERROR_COUNT
-divider add "Receive Ports - 8b10b Decoder"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCHARISK_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDISPERR_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXNOTINTABLE_OUT
-divider add "Receive Ports - Comma Detection and Alignment"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENMCOMMAALIGN_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPCOMMAALIGN_IN
-divider add "Receive Ports - RX Data Path interface"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDATA_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRECCLK_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXUSRCLK2_IN
-divider add "Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCDRRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXN_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXP_IN
-divider add "Receive Ports - RX Elastic Buffer and Phase Alignment Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNDISABLE_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONENB_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONITOR_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNOVERRIDE_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPMAPHASEALIGN_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPMASETPHASE_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXSTATUS_OUT
-divider add "Receive Ports - RX Loss-of-sync State Machine"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXLOSSOFSYNC_OUT
-divider add "Receive Ports - RX PLL Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXRXRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/MGTREFCLKRX_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PLLRXRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPLLLKDET_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESETDONE_OUT
-divider add "Receive Ports - RX Pipe Control for PCI Express"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PHYSTATUS_OUT
-divider add "Transmit Ports - 8b10b Encoder Control Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXCHARISK_IN
-divider add "Transmit Ports - GTX Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTEST_IN
-divider add "Transmit Ports - TX Data Path interface"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDATA_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXOUTCLK_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXUSRCLK2_IN
-divider add "Transmit Ports - TX Driver and OOB signaling"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXN_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXP_OUT
-divider add "Transmit Ports - TX Elastic Buffer and Phase Alignment Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNDISABLE_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONENB_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONITOR_OUT
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXENPMAPHASEALIGN_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXPMASETPHASE_IN
-divider add "Transmit Ports - TX PLL Ports"
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTXRESET_IN
-wave add /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESETDONE_OUT
-
-run 226 us
-quit
-
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/wave_mti.do b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/wave_mti.do
deleted file mode 100644
index 3358923..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/wave_mti.do
+++ /dev/null
@@ -1,132 +0,0 @@
-###############################################################################
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -divider {FRAME CHECK MODULE gtx0_frame_check }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/begin_r
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/track_data_r
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/data_error_detected_r
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/start_of_packet_detected_r
-add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/RX_DATA
-add wave -noupdate -format Logic -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtx0_frame_check/ERROR_COUNT
-add wave -noupdate -divider {GTX0_GTXVIRTEX6FEE80 }
-add wave -noupdate -divider {Receive Ports - 8b10b Decoder }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCHARISK_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDISPERR_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXNOTINTABLE_OUT
-add wave -noupdate -divider {Receive Ports - Comma Detection and Alignment }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENMCOMMAALIGN_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPCOMMAALIGN_IN
-add wave -noupdate -divider {Receive Ports - RX Data Path interface }
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDATA_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRECCLK_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXUSRCLK2_IN
-add wave -noupdate -divider {Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXCDRRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXN_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXP_IN
-add wave -noupdate -divider {Receive Ports - RX Elastic Buffer and Phase Alignment Ports }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNDISABLE_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONENB_IN
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNMONITOR_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNOVERRIDE_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXDLYALIGNRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXENPMAPHASEALIGN_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPMASETPHASE_IN
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXSTATUS_OUT
-add wave -noupdate -divider {Receive Ports - RX Loss-of-sync State Machine }
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXLOSSOFSYNC_OUT
-add wave -noupdate -divider {Receive Ports - RX PLL Ports }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXRXRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/MGTREFCLKRX_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PLLRXRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXPLLLKDET_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/RXRESETDONE_OUT
-add wave -noupdate -divider {Receive Ports - RX Pipe Control for PCI Express }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/PHYSTATUS_OUT
-add wave -noupdate -divider {Transmit Ports - 8b10b Encoder Control Ports }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXCHARISK_IN
-add wave -noupdate -divider {Transmit Ports - GTX Ports }
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTEST_IN
-add wave -noupdate -divider {Transmit Ports - TX Data Path interface }
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDATA_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXOUTCLK_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXUSRCLK2_IN
-add wave -noupdate -divider {Transmit Ports - TX Driver and OOB signaling }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXN_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXP_OUT
-add wave -noupdate -divider {Transmit Ports - TX Elastic Buffer and Phase Alignment Ports }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNDISABLE_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONENB_IN
-add wave -noupdate -format Literal -radix hexadecimal /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNMONITOR_OUT
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXDLYALIGNRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXENPMAPHASEALIGN_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXPMASETPHASE_IN
-add wave -noupdate -divider {Transmit Ports - TX PLL Ports }
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/GTXTXRESET_IN
-add wave -noupdate -format Logic /DEMO_TB/gtxVirtex6FEE80_top_i/gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/TXRESETDONE_OUT
-
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {0 ps} 0}
-configure wave -namecolwidth 282
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {0 ps} {5236 ps}
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/wave_ncsim.sv b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/wave_ncsim.sv
deleted file mode 100644
index bbbe5e1..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/functional/wave_ncsim.sv
+++ /dev/null
@@ -1,120 +0,0 @@
-
-###############################################################################
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-  window new WaveWindow  -name  "Waves for Virtex-6 GTX Wizard Example Design"
-  waveform  using  "Waves for Virtex-6 GTX Wizard Example Design"
-  
-  waveform  add  -label FRAME_CHECK_MODULE -comment gtx0_frame_check
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtx0_frame_check:begin_r
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtx0_frame_check:track_data_r
-  waveform  add  -siganls  :gtxVirtex6FEE80_top_i:gtx0_frame_check:data_error_detected_r
-  wavefrom  add  -siganls  :gtxVirtex6FEE80_top_i:gtx0_frame_check:start_of_packet_detected_r
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtx0_frame_check:RX_DATA
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtx0_frame_check:ERROR_COUNT
-  waveform  add  -label GTX0_GTXVIRTEX6FEE80 -comment GTX0_GTXVIRTEX6FEE80
-  waveform  add  -label Receive_Ports_-_8b10b_Decoder  -comment  Receive_Ports_-_8b10b_Decoder
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCHARISK_OUT
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDISPERR_OUT
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXNOTINTABLE_OUT
-  waveform  add  -label Receive_Ports_-_Comma_Detection_and_Alignment  -comment  Receive_Ports_-_Comma_Detection_and_Alignment
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENMCOMMAALIGN_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPCOMMAALIGN_IN
-  waveform  add  -label Receive_Ports_-_RX_Data_Path_interface  -comment  Receive_Ports_-_RX_Data_Path_interface
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDATA_OUT
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRECCLK_OUT
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESET_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXUSRCLK2_IN
-  waveform  add  -label Receive_Ports_-_RX_Driver,OOB_signalling,Coupling_and_Eq.,CDR  -comment  Receive_Ports_-_RX_Driver,OOB_signalling,Coupling_and_Eq.,CDR
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXCDRRESET_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXN_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXP_IN
-  waveform  add  -label Receive_Ports_-_RX_Elastic_Buffer_and_Phase_Alignment_Ports  -comment  Receive_Ports_-_RX_Elastic_Buffer_and_Phase_Alignment_Ports
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNDISABLE_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONENB_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNMONITOR_OUT
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNOVERRIDE_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXDLYALIGNRESET_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXENPMAPHASEALIGN_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPMASETPHASE_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXSTATUS_OUT
-  waveform  add  -label Receive_Ports_-_RX_Loss-of-sync_State_Machine  -comment  Receive_Ports_-_RX_Loss-of-sync_State_Machine
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXLOSSOFSYNC_OUT
-  waveform  add  -label Receive_Ports_-_RX_PLL_Ports  -comment  Receive_Ports_-_RX_PLL_Ports
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXRXRESET_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:MGTREFCLKRX_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PLLRXRESET_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXPLLLKDET_OUT
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:RXRESETDONE_OUT
-  waveform  add  -label Receive_Ports_-_RX_Pipe_Control_for_PCI_Express  -comment  Receive_Ports_-_RX_Pipe_Control_for_PCI_Express
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:PHYSTATUS_OUT
-  waveform  add  -label Transmit_Ports_-_8b10b_Encoder_Control_Ports  -comment  Transmit_Ports_-_8b10b_Encoder_Control_Ports
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXCHARISK_IN
-  waveform  add  -label Transmit_Ports_-_GTX_Ports  -comment  Transmit_Ports_-_GTX_Ports
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTEST_IN
-  waveform  add  -label Transmit_Ports_-_TX_Data_Path_interface  -comment  Transmit_Ports_-_TX_Data_Path_interface
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDATA_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXOUTCLK_OUT
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESET_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXUSRCLK2_IN
-  waveform  add  -label Transmit_Ports_-_TX_Driver_and_OOB_signaling  -comment  Transmit_Ports_-_TX_Driver_and_OOB_signaling
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXN_OUT
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXP_OUT
-  waveform  add  -label Transmit_Ports_-_TX_Elastic_Buffer_and_Phase_Alignment_Ports  -comment  Transmit_Ports_-_TX_Elastic_Buffer_and_Phase_Alignment_Ports
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNDISABLE_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONENB_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNMONITOR_OUT
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXDLYALIGNRESET_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXENPMAPHASEALIGN_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXPMASETPHASE_IN
-  waveform  add  -label Transmit_Ports_-_TX_PLL_Ports  -comment  Transmit_Ports_-_TX_PLL_Ports
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:GTXTXRESET_IN
-  waveform  add  -signals  :gtxVirtex6FEE80_top_i:gtxVirtex6FEE80_i:gtx0_gtxVirtex6FEE80_i:TXRESETDONE_OUT
-
-  console submit -using simulator -wait no "run 226 us"
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/netlist/simulate_mti.do b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/netlist/simulate_mti.do
deleted file mode 100644
index 2a706a0..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/simulation/netlist/simulate_mti.do
+++ /dev/null
@@ -1,97 +0,0 @@
-################################################################################
-##   ____  ____ 
-##  /   /\/   / 
-## /___/  \  /    Vendor: Xilinx 
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : simulate_mti.do
-## /___/   /\     
-## \   \  /  \ 
-##  \___\/\___\ 
-##
-##
-## Script SIMULATE_MTI.DO
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-##***************************** Beginning of Script ***************************
-        
-## If MTI_LIBS is defined, map unisim and simprim directories using MTI_LIBS
-## This mode of mapping the unisims libraries is provided for backward 
-## compatibility with previous wizard releases. If you don't set MTI_LIBS
-## the unisim libraries will be loaded from the paths set up by compxlib in
-## your modelsim.ini file
-
-set XILINX   $env(XILINX)
-if [info exists env(MTI_LIBS)] {    
-    set MTI_LIBS $env(MTI_LIBS)
-    vlib SECUREIP
-    vlib SIMPRIM
-    vmap SIMPRIM $MTI_LIBS/simprim
-    vmap SECUREIP $MTI_LIBS/secureip
-   
-}
-   
-
-## Create and map work directory
-vlib work
-vmap work work
-
-vcom -93 -work work  ../../implement/results/routed.vhd;
-
-vcom -93 -work work ../sim_reset_mgt_model.vhd;
-vcom -93 -work work   ../demo_tb_imp.vhd;
-
-##Load Design
-vsim -t 1ps -L SECUREIP -L SIMPRIM -voptargs="+acc" -sdfmax DEMO_TB_IMP/gtxVirtex6FEE80_top_i=../../implement/results/routed.sdf +notimingchecks work.DEMO_TB_IMP
-
-##Run simulation
-run 226 us
-
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/v6_gtxwizard_v1_12_readme.txt b/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/v6_gtxwizard_v1_12_readme.txt
deleted file mode 100644
index 51cf252..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxVirtex6FEE80/v6_gtxwizard_v1_12_readme.txt
+++ /dev/null
@@ -1,153 +0,0 @@
-                Core name: Xilinx LogiCORE Virtex-6 GTX Transceiver Wizard
-                Version: 1.12
-                Release: 13.4
-                Release Date: January 18, 2012
-
-
-================================================================================
-
-This document contains the following sections:
-
-1. Introduction
-2. New Features
-3. Supported Devices
-4. Resolved Issues
-5. Known Issues
-6. Technical Support
-7. Core Release History
-8. Legal Disclaimer
-
-================================================================================
-
-
-1. INTRODUCTION
-
-For installation instructions for this release, please go to:
-
-  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
-
-For system requirements:
-
-   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
-
-This file contains release notes for the Xilinx LogiCORE IP Virtex-6 FPGA GTX
-Transceiver Wizard v1.12 solution. For the latest core updates, see the product page at:
-
-   http://www.xilinx.com/products/ipcenter/V6_GTX_Wizard.htm
-
-
-2. NEW FEATURES
-
-- ISE 13.4 software support
-- Auto Upgrade Support has been added. Older versions of the core- 1.4, 1.5, 16, 1.7,
-  1.8,1.9,1.10,1.11 can be upgraded to 1.12
-
-
-3. SUPPORTED DEVICES
- 
-The following device families are supported by the core for this release.
-
-Virtex-6 XC CXT/LXT/SXT/HXT
-Virtex-6 XQ LXT/SXT                                                       
-Virtex-6 -1L XC LXT/SXT 
-Virtex-6 -1L XQ LXT/SXT 
-
-
-4. RESOLVED ISSUES
-
-Format for each entry:
-
-  1. Updates to SRIO gen2 settings
-
-   Description: Attribute values for SRIO gen2 are updated based on the hw testing results
-   
-   Version(s) Fixed:  
-   CR 631978
-
-
-5. KNOWN ISSUES
-
-The most recent information, including known issues, workarounds, and
-resolutions for this version is provided in the IP Release Notes Guide
-located at
-
-   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
-
-
-6. TECHNICAL SUPPORT
-
-To obtain technical support, create a WebCase at www.xilinx.com/support.
-Questions are routed to a team with expertise using this product.
-
-Xilinx provides technical support for use of this product when used
-according to the guidelines described in the core documentation, and
-cannot guarantee timing, functionality, or support of this product for
-designs that do not follow specified guidelines.
-
-
-7. CORE RELEASE HISTORY
-Date        By            Version      Description
-================================================================================
-01/18/2012  Xilinx, Inc   1.12         ISE 13.4 support
-10/19/2011  Xilinx, Inc   1.11         ISE 13.3 support
-06/22/2011  Xilinx, Inc   1.10         ISE 13.2 support
-03/01/2011  Xilinx, Inc   1.9          ISE 13.1 support
-12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
-09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
-07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
-04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
-12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
-09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
-06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
-04/24/2009  Xilinx, Inc.  1.1          ISE 11.1 support
-================================================================================
-
-
-8. LEGAL DISCLAIMER
-
-(c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
-
-This file contains confidential and proprietary information
-of Xilinx, Inc. and is protected under U.S. and
-international copyright and other intellectual property
-laws.
-
-DISCLAIMER
-This disclaimer is not a license and does not grant any
-rights to the materials distributed herewith. Except as
-otherwise provided in a valid license issued to you by
-Xilinx, and to the maximum extent permitted by applicable
-law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-(2) Xilinx shall not be liable (whether in contract or tort,
-including negligence, or under any other theory of
-liability) for any loss or damage of any kind or nature
-related to, arising under or in connection with these
-materials, including for any direct, or any indirect,
-special, incidental, or consequential loss or damage
-(including loss of data, profits, goodwill, or any type of
-loss or damage suffered as a result of any action brought
-by a third party) even if such damage or loss was
-reasonably foreseeable or Xilinx had been advised of the
-possibility of the same.
-
-CRITICAL APPLICATIONS
-Xilinx products are not designed or intended to be fail-
-safe, or for use in any application requiring fail-safe
-performance, such as life-support or safety devices or
-systems, Class III medical devices, nuclear facilities,
-applications related to the deployment of airbags, or any
-other applications that could lead to death, personal
-injury, or severe property or environmental damage
-(individually and collectively, "Critical
-Applications"). Customer assumes the sole risk and
-liability of any use of Xilinx products in Critical
-Applications, subject only to applicable laws and
-regulations governing limitations on product liability.
-
-THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-PART OF THIS FILE AT ALL TIMES.
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtx_attributes.ucf b/FEE_ADC32board/project/ipcore_dir/gtx_attributes.ucf
deleted file mode 100644
index c2a09c5..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtx_attributes.ucf
+++ /dev/null
@@ -1,280 +0,0 @@
-################################################################################
-##   ____  ____
-##  /   /\/   /
-## /___/  \  /    Vendor: Xilinx
-## \   \   \/     Version : 1.12
-##  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
-##  /   /         Filename : gtx_attributes.ucf
-## /___/   /\      
-## \   \  /  \ 
-##  \___\/\___\
-##
-##
-## GTX ATTRIBUTES 
-## This file contains the attributes for the active GTX transceivers in the
-## design. If you would like to use this file in your design, please make
-## sure that the path to the GTX instance is correct.
-## Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
-##
-## (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
-##
-## This file contains confidential and proprietary information
-## of Xilinx, Inc. and is protected under U.S. and
-## international copyright and other intellectual property
-## laws.
-##
-## DISCLAIMER
-## This disclaimer is not a license and does not grant any
-## rights to the materials distributed herewith. Except as
-## otherwise provided in a valid license issued to you by
-## Xilinx, and to the maximum extent permitted by applicable
-## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-## (2) Xilinx shall not be liable (whether in contract or tort,
-## including negligence, or under any other theory of
-## liability) for any loss or damage of any kind or nature
-## related to, arising under or in connection with these
-## materials, including for any direct, or any indirect,
-## special, incidental, or consequential loss or damage
-## (including loss of data, profits, goodwill, or any type of
-## loss or damage suffered as a result of any action brought
-## by a third party) even if such damage or loss was
-## reasonably foreseeable or Xilinx had been advised of the
-## possibility of the same.
-##
-## CRITICAL APPLICATIONS
-## Xilinx products are not designed or intended to be fail-
-## safe, or for use in any application requiring fail-safe
-## performance, such as life-support or safety devices or
-## systems, Class III medical devices, nuclear facilities,
-## applications related to the deployment of airbags, or any
-## other applications that could lead to death, personal
-## injury, or severe property or environmental damage
-## (individually and collectively, "Critical
-## Applications"). Customer assumes the sole risk and
-## liability of any use of Xilinx products in Critical
-## Applications, subject only to applicable laws and
-## regulations governing limitations on product liability.
-## 
-## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-## PART OF THIS FILE AT ALL TIMES.
-
-############################## Active GTX Attributes #######################
- 
-##________________________ Attributes for GTX 0_____________________
- 
-
-##--------------------------TX PLL----------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK_SOURCE                          = "RXPLL";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_OVERSAMPLE_MODE                     = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_COM_CFG                          = 24'h21680a;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_CP_CFG                           = 8'h07;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_FB                        = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_OUT                       = 2;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL_REF                       = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_DIVSEL45_FB                      = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_LKDET_CFG                        = 3'b111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_CLK25_DIVIDER                       = 4;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXPLL_SATA                             = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_TDCC_CFG                            = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CAS_CLK_EN                         = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i POWER_SAVE                             = 10'b0000110100;
-
-##-----------------------TX Interface-------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_TXUSRCLK                           = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DATA_WIDTH                          = 10;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_USRCLK_CFG                          = 6'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_CTRL                          = "TXPLLREFCLK_DIV1";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXOUTCLK_DLY                           = 10'b0000000000;
-
-##------------TX Buffering and Phase Alignment----------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_PMADATA_OPT                         = 1'b1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_TX_CFG                             = 20'h80082;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BUFFER_USE                          = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_BYTECLK_CFG                         = 6'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_EN_RATE_RESET_BUF                   = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_XCLK_SEL                            = "TXUSR";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_CTRINC                     = 4'b0100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_LPFINC                     = 4'b0110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_MONSEL                     = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DLYALIGN_OVRDSETTING                = 8'b10000000;
-
-##-----------------------TX Gearbox---------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEARBOX_ENDEC                          = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXGEARBOX_USE                          = "FALSE";
-
-##--------------TX Driver and OOB Signalling------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DRIVE_MODE                          = "DIRECT";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_ASSERT_DELAY                   = 3'b101;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_IDLE_DEASSERT_DELAY                 = 3'b011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_HIZ                   = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TXDRIVE_LOOPBACK_PD                    = "FALSE";
-
-##------------TX Pipe Control for PCI Express/SATA------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COM_BURST_VAL                          = 4'b1111;
-
-##----------------TX Attributes for PCI Express---------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_0                            = 5'b11010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DEEMPH_1                            = 5'b10000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_0                       = 7'b1001110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_1                       = 7'b1001001;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_2                       = 7'b1000101;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_3                       = 7'b1000010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_FULL_4                       = 7'b1000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_0                        = 7'b1000110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_1                        = 7'b1000100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_2                        = 7'b1000010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_3                        = 7'b1000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_MARGIN_LOW_4                        = 7'b1000000;
-
-##--------------------------RX PLL----------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_OVERSAMPLE_MODE                     = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_COM_CFG                          = 24'h21680a;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_CP_CFG                           = 8'h07;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_FB                        = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_OUT                       = 2;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL_REF                       = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_DIVSEL45_FB                      = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPLL_LKDET_CFG                        = 3'b111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_CLK25_DIVIDER                       = 4;
-
-##-----------------------RX Interface-------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i GEN_RXUSRCLK                           = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DATA_WIDTH                          = 10;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_CTRL                          = "RXRECCLKPMA_DIV1";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXRECCLK_DLY                           = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXUSRCLK_DLY                           = 16'h0000;
-
-##--------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i AC_CAP_DIS                             = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CDR_PH_ADJ_TIME                        = 5'b10100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i OOBDETECT_THRESHOLD                    = 3'b011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CDR_SCAN                           = 27'h640404C;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RX_CFG                             = 25'h05ce008;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_GND                           = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RCV_TERM_VTTRX                         = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_CDR                    = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_FR                    = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_PH                    = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TX_DETECT_RX_CFG                       = 14'h1832;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_CTRL                       = 5'b00000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TERMINATION_OVRD                       = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CM_TRIM                                = 2'b01;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_RXSYNC_CFG                         = 7'h00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PMA_CFG                                = 76'h0040000040000000003;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BGTEST_CFG                             = 2'b00;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i BIAS_CFG                               = 17'h00000;
-
-##------------RX Decision Feedback Equalizer(DFE)-------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CAL_TIME                           = 5'b01100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DFE_CFG                                = 8'b00011011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_HOLD_DFE                    = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_OFFSET                          = 8'h4C;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EYE_SCANMODE                        = 2'b00;
-
-##-----------------------PRBS Detection-----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXPRBSERR_LOOPBACK                     = 1'b0;
-
-##----------------Comma Detection and Alignment---------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i ALIGN_COMMA_WORD                       = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_10B_ENABLE                       = 10'b1111111100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i COMMA_DOUBLE                           = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_MCOMMA_DETECT                      = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_PCOMMA_DETECT                      = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i DEC_VALID_COMMA_ONLY                   = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_10B_VALUE                       = 10'b1010000011;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i MCOMMA_DETECT                          = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_10B_VALUE                       = 10'b0101111100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCOMMA_DETECT                          = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DECODE_SEQ_MATCH                    = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_AUTO_WAIT                     = 5;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_SLIDE_MODE                          = "OFF";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SHOW_REALIGN_COMMA                     = "TRUE";
-
-##---------------RX Loss-of-sync State Machine----------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_INVALID_INCR                    = 8;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOS_THRESHOLD                       = 256;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_LOSS_OF_SYNC_FSM                    = "TRUE";
-
-##-----------------------RX Gearbox---------------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RXGEARBOX_USE                          = "FALSE";
-
-##-----------RX Elastic Buffer and Phase alignment------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_BUFFER_USE                          = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_IDLE_RESET_BUF                   = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_MODE_RESET_BUF                   = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_RATE_RESET_BUF                   = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF                = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_EN_REALIGN_RESET_BUF2               = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_FIFO_ADDR_MODE                      = "FAST";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_HI_CNT                         = 4'b1000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_IDLE_LO_CNT                         = 4'b0000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_XCLK_SEL                            = "RXUSR";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_CTRINC                     = 4'b1110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_EDGESET                    = 5'b00010;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_LPFINC                     = 4'b1110;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_MONSEL                     = 3'b000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i RX_DLYALIGN_OVRDSETTING                = 8'b10000000;
-
-##----------------------Clock Correction----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_ADJ_LEN                        = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_DET_LEN                        = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_INSERT_IDLE_FLAG               = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_KEEP_IDLE                      = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MAX_LAT                        = 16;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_MIN_LAT                        = 14;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_PRECEDENCE                     = "TRUE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_REPEAT_WAIT                    = 0;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_1                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_2                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_3                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_4                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_1_ENABLE                   = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_1                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_2                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_3                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_4                        = 10'b0100000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_ENABLE                   = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_COR_SEQ_2_USE                      = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CLK_CORRECT_USE                        = "FALSE";
-
-##----------------------Channel Bonding----------------------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_1_MAX_SKEW                   = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_2_MAX_SKEW                   = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_KEEP_ALIGN                   = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_1                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_2                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_3                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_4                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_1_ENABLE                 = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_1                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_2                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_3                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_4                      = 10'b0000000000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_CFG                    = 5'b00000;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_ENABLE                 = 4'b1111;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_2_USE                    = "FALSE";
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i CHAN_BOND_SEQ_LEN                      = 1;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i PCI_EXPRESS_MODE                       = "FALSE";
-
-##-----------RX Attributes for PCI Express/SATA/SAS----------
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MAX_COMSAS                         = 52;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SAS_MIN_COMSAS                         = 40;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_BURST_VAL                         = 3'b100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_IDLE_VAL                          = 3'b100;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_BURST                         = 11;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_INIT                          = 34;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MAX_WAKE                          = 11;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_BURST                         = 6;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_INIT                          = 19;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i SATA_MIN_WAKE                          = 6;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_FROM_P2                     = 12'h03c;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_NON_P2                      = 8'h19;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_RATE                        = 8'hff;
-INST gtxVirtex6FEE80_i/gtx0_gtxVirtex6FEE80_i/gtxe1_i TRANS_TIME_TO_P2                       = 10'h064;
-
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80.vhd b/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80.vhd
deleted file mode 100644
index 161dfc4..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80.vhd
+++ /dev/null
@@ -1,377 +0,0 @@
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor: Xilinx
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
---  /   /         Filename : gtxvirtex6fee80.vhd
--- /___/   /\     
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Module GTXVIRTEX6FEE80 (a GTX Wrapper)
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
-
---***************************** Entity Declaration ****************************
-
-entity gtxVirtex6FEE80 is
-generic
-(
-    -- Simulation attributes
-    WRAPPER_SIM_GTXRESET_SPEEDUP    : integer   := 0 -- Set to 1 to speed up sim reset
-);
-port
-(
-    
-    --_________________________________________________________________________
-    --_________________________________________________________________________
-    --GTX0  (X0Y12)
-    
-    GTX0_DOUBLE_RESET_CLK_IN                : in   std_logic;
-    ----------------------- Receive Ports - 8b10b Decoder ----------------------
-    GTX0_RXCHARISK_OUT                      : out  std_logic;
-    GTX0_RXDISPERR_OUT                      : out  std_logic;
-    GTX0_RXNOTINTABLE_OUT                   : out  std_logic;
-    --------------- Receive Ports - Comma Detection and Alignment --------------
-    GTX0_RXENMCOMMAALIGN_IN                 : in   std_logic;
-    GTX0_RXENPCOMMAALIGN_IN                 : in   std_logic;
-    ------------------- Receive Ports - RX Data Path interface -----------------
-    GTX0_RXDATA_OUT                         : out  std_logic_vector(7 downto 0);
-    GTX0_RXRECCLK_OUT                       : out  std_logic;
-    GTX0_RXRESET_IN                         : in   std_logic;
-    GTX0_RXUSRCLK2_IN                       : in   std_logic;
-    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-    GTX0_RXCDRRESET_IN                      : in   std_logic;
-    GTX0_RXN_IN                             : in   std_logic;
-    GTX0_RXP_IN                             : in   std_logic;
-    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-    GTX0_RXDLYALIGNDISABLE_IN               : in   std_logic;
-    GTX0_RXDLYALIGNMONENB_IN                : in   std_logic;
-    GTX0_RXDLYALIGNMONITOR_OUT              : out  std_logic_vector(7 downto 0);
-    GTX0_RXDLYALIGNOVERRIDE_IN              : in   std_logic;
-    GTX0_RXDLYALIGNRESET_IN                 : in   std_logic;
-    GTX0_RXENPMAPHASEALIGN_IN               : in   std_logic;
-    GTX0_RXPMASETPHASE_IN                   : in   std_logic;
-    GTX0_RXSTATUS_OUT                       : out  std_logic_vector(2 downto 0);
-    --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-    GTX0_RXLOSSOFSYNC_OUT                   : out  std_logic_vector(1 downto 0);
-    ------------------------ Receive Ports - RX PLL Ports ----------------------
-    GTX0_GTXRXRESET_IN                      : in   std_logic;
-    GTX0_MGTREFCLKRX_IN                     : in   std_logic;
-    GTX0_PLLRXRESET_IN                      : in   std_logic;
-    GTX0_RXPLLLKDET_OUT                     : out  std_logic;
-    GTX0_RXRESETDONE_OUT                    : out  std_logic;
-    -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-    GTX0_PHYSTATUS_OUT                      : out  std_logic;
-    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-    GTX0_TXCHARISK_IN                       : in   std_logic;
-    ------------------ Transmit Ports - TX Data Path interface -----------------
-    GTX0_TXDATA_IN                          : in   std_logic_vector(7 downto 0);
-    GTX0_TXOUTCLK_OUT                       : out  std_logic;
-    GTX0_TXRESET_IN                         : in   std_logic;
-    GTX0_TXUSRCLK2_IN                       : in   std_logic;
-    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-    GTX0_TXN_OUT                            : out  std_logic;
-    GTX0_TXP_OUT                            : out  std_logic;
-    -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-    GTX0_TXDLYALIGNDISABLE_IN               : in   std_logic;
-    GTX0_TXDLYALIGNMONENB_IN                : in   std_logic;
-    GTX0_TXDLYALIGNMONITOR_OUT              : out  std_logic_vector(7 downto 0);
-    GTX0_TXDLYALIGNRESET_IN                 : in   std_logic;
-    GTX0_TXENPMAPHASEALIGN_IN               : in   std_logic;
-    GTX0_TXPMASETPHASE_IN                   : in   std_logic;
-    ----------------------- Transmit Ports - TX PLL Ports ----------------------
-    GTX0_GTXTXRESET_IN                      : in   std_logic;
-    GTX0_TXRESETDONE_OUT                    : out  std_logic
-
-    
-);
-
-
-end gtxVirtex6FEE80;
-    
-architecture RTL of gtxVirtex6FEE80 is
-
-    attribute CORE_GENERATION_INFO : string;
-    attribute CORE_GENERATION_INFO of RTL : architecture is "gtxVirtex6FEE80,v6_gtxwizard_v1_12,{protocol_file=Start_from_scratch}";
-
---***************************** Signal Declarations *****************************
-
-    -- ground and tied_to_vcc_i signals
-    signal  tied_to_ground_i                :   std_logic;
-    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
-    signal  tied_to_vcc_i                   :   std_logic;
-
-    signal  gtx0_gtxtest_bit1        :   std_logic;
-    signal  gtx0_gtxtest_done        :   std_logic;
-    signal  gtx0_gtxtest_i           :   std_logic_vector(12 downto 0);
-    signal  gtx0_txreset_i           :   std_logic;
-    signal  gtx0_rxreset_i           :   std_logic;
-    signal  gtx0_rxplllkdet_i        :   std_logic;
-   
-
-  
-    signal  gtx0_share_rxpll_i           :   std_logic_vector(1 downto 0);
-    signal  gtx0_mgtrefclkrx_i           :   std_logic_vector(1 downto 0);
-   
---*************************** Component Declarations **************************
-component gtxVirtex6FEE80_gtx
-generic
-(
-    -- Simulation attributes
-    GTX_SIM_GTXRESET_SPEEDUP    : integer    := 0;
-    
-    -- Share RX PLL parameter
-    GTX_TX_CLK_SOURCE           : string     := "TXPLL";
-    -- Save power parameter
-    GTX_POWER_SAVE              : bit_vector := "0000000000"
-);
-port 
-(   
-    ----------------------- Receive Ports - 8b10b Decoder ----------------------
-    RXCHARISK_OUT                           : out  std_logic;
-    RXDISPERR_OUT                           : out  std_logic;
-    RXNOTINTABLE_OUT                        : out  std_logic;
-    --------------- Receive Ports - Comma Detection and Alignment --------------
-    RXENMCOMMAALIGN_IN                      : in   std_logic;
-    RXENPCOMMAALIGN_IN                      : in   std_logic;
-    ------------------- Receive Ports - RX Data Path interface -----------------
-    RXDATA_OUT                              : out  std_logic_vector(7 downto 0);
-    RXRECCLK_OUT                            : out  std_logic;
-    RXRESET_IN                              : in   std_logic;
-    RXUSRCLK2_IN                            : in   std_logic;
-    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-    RXCDRRESET_IN                           : in   std_logic;
-    RXN_IN                                  : in   std_logic;
-    RXP_IN                                  : in   std_logic;
-    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-    RXDLYALIGNDISABLE_IN                    : in   std_logic;
-    RXDLYALIGNMONENB_IN                     : in   std_logic;
-    RXDLYALIGNMONITOR_OUT                   : out  std_logic_vector(7 downto 0);
-    RXDLYALIGNOVERRIDE_IN                   : in   std_logic;
-    RXDLYALIGNRESET_IN                      : in   std_logic;
-    RXENPMAPHASEALIGN_IN                    : in   std_logic;
-    RXPMASETPHASE_IN                        : in   std_logic;
-    RXSTATUS_OUT                            : out  std_logic_vector(2 downto 0);
-    --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-    RXLOSSOFSYNC_OUT                        : out  std_logic_vector(1 downto 0);
-    ------------------------ Receive Ports - RX PLL Ports ----------------------
-    GTXRXRESET_IN                           : in   std_logic;
-    MGTREFCLKRX_IN                          : in   std_logic_vector(1 downto 0);
-    PLLRXRESET_IN                           : in   std_logic;
-    RXPLLLKDET_OUT                          : out  std_logic;
-    RXRESETDONE_OUT                         : out  std_logic;
-    -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-    PHYSTATUS_OUT                           : out  std_logic;
-    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-    TXCHARISK_IN                            : in   std_logic;
-    ------------------------- Transmit Ports - GTX Ports -----------------------
-    GTXTEST_IN                              : in   std_logic_vector(12 downto 0);
-    ------------------ Transmit Ports - TX Data Path interface -----------------
-    TXDATA_IN                               : in   std_logic_vector(7 downto 0);
-    TXOUTCLK_OUT                            : out  std_logic;
-    TXRESET_IN                              : in   std_logic;
-    TXUSRCLK2_IN                            : in   std_logic;
-    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-    TXN_OUT                                 : out  std_logic;
-    TXP_OUT                                 : out  std_logic;
-    -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-    TXDLYALIGNDISABLE_IN                    : in   std_logic;
-    TXDLYALIGNMONENB_IN                     : in   std_logic;
-    TXDLYALIGNMONITOR_OUT                   : out  std_logic_vector(7 downto 0);
-    TXDLYALIGNRESET_IN                      : in   std_logic;
-    TXENPMAPHASEALIGN_IN                    : in   std_logic;
-    TXPMASETPHASE_IN                        : in   std_logic;
-    ----------------------- Transmit Ports - TX PLL Ports ----------------------
-    GTXTXRESET_IN                           : in   std_logic;
-    MGTREFCLKTX_IN                          : in   std_logic_vector(1 downto 0);
-    PLLTXRESET_IN                           : in   std_logic;
-    TXPLLLKDET_OUT                          : out  std_logic;
-    TXRESETDONE_OUT                         : out  std_logic
-
-
-);
-end component;
-
-component DOUBLE_RESET
-port
-(
-        CLK                :   in    std_logic;
-        PLLLKDET           :   in    std_logic;
-        GTXTEST_DONE       :   out   std_logic;
-        GTXTEST_BIT1       :   out   std_logic
-
-);
-end component;
-
---********************************* Main Body of Code**************************
-
-begin                       
-
-    tied_to_ground_i                    <= '0';
-    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
-    tied_to_vcc_i                       <= '1';
-                     
-     gtx0_gtxtest_i        <= b"10000000000" & gtx0_gtxtest_bit1 & '0';
-     gtx0_txreset_i        <= gtx0_gtxtest_done or GTX0_TXRESET_IN;
-     gtx0_rxreset_i        <= GTX0_RXRESET_IN;
-     GTX0_RXPLLLKDET_OUT   <= gtx0_rxplllkdet_i;
-
-   
-    gtx0_mgtrefclkrx_i <= (tied_to_ground_i & GTX0_MGTREFCLKRX_IN);
-
- 
-    --------------------------- GTX Instances  -------------------------------   
-
-
-    --_________________________________________________________________________
-    --_________________________________________________________________________
-    --GTX0  (X0Y12)
-
-    gtx0_gtxVirtex6FEE80_i : gtxVirtex6FEE80_gtx
-    generic map
-    (
-        -- Simulation attributes
-        GTX_SIM_GTXRESET_SPEEDUP    => WRAPPER_SIM_GTXRESET_SPEEDUP,
-        
-        -- Share RX PLL parameter
-        GTX_TX_CLK_SOURCE           => "RXPLL",
-        -- Save power parameter
-        GTX_POWER_SAVE              => "0000110100"
-    )
-    port map
-    (
-        ----------------------- Receive Ports - 8b10b Decoder ----------------------
-        RXCHARISK_OUT                   =>      GTX0_RXCHARISK_OUT,
-        RXDISPERR_OUT                   =>      GTX0_RXDISPERR_OUT,
-        RXNOTINTABLE_OUT                =>      GTX0_RXNOTINTABLE_OUT,
-        --------------- Receive Ports - Comma Detection and Alignment --------------
-        RXENMCOMMAALIGN_IN              =>      GTX0_RXENMCOMMAALIGN_IN,
-        RXENPCOMMAALIGN_IN              =>      GTX0_RXENPCOMMAALIGN_IN,
-        ------------------- Receive Ports - RX Data Path interface -----------------
-        RXDATA_OUT                      =>      GTX0_RXDATA_OUT,
-        RXRECCLK_OUT                    =>      GTX0_RXRECCLK_OUT,
-        RXRESET_IN                      =>      gtx0_rxreset_i,
-        RXUSRCLK2_IN                    =>      GTX0_RXUSRCLK2_IN,
-        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-        RXCDRRESET_IN                   =>      GTX0_RXCDRRESET_IN,
-        RXN_IN                          =>      GTX0_RXN_IN,
-        RXP_IN                          =>      GTX0_RXP_IN,
-        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-        RXDLYALIGNDISABLE_IN            =>      GTX0_RXDLYALIGNDISABLE_IN,
-        RXDLYALIGNMONENB_IN             =>      GTX0_RXDLYALIGNMONENB_IN,
-        RXDLYALIGNMONITOR_OUT           =>      GTX0_RXDLYALIGNMONITOR_OUT,
-        RXDLYALIGNOVERRIDE_IN           =>      GTX0_RXDLYALIGNOVERRIDE_IN,
-        RXDLYALIGNRESET_IN              =>      GTX0_RXDLYALIGNRESET_IN,
-        RXENPMAPHASEALIGN_IN            =>      GTX0_RXENPMAPHASEALIGN_IN,
-        RXPMASETPHASE_IN                =>      GTX0_RXPMASETPHASE_IN,
-        RXSTATUS_OUT                    =>      GTX0_RXSTATUS_OUT,
-        --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-        RXLOSSOFSYNC_OUT                =>      GTX0_RXLOSSOFSYNC_OUT,
-        ------------------------ Receive Ports - RX PLL Ports ----------------------
-        GTXRXRESET_IN                   =>      GTX0_GTXRXRESET_IN,
-        MGTREFCLKRX_IN                  =>      gtx0_mgtrefclkrx_i,
-        PLLRXRESET_IN                   =>      GTX0_PLLRXRESET_IN,
-        RXPLLLKDET_OUT                  =>      gtx0_rxplllkdet_i,
-        RXRESETDONE_OUT                 =>      GTX0_RXRESETDONE_OUT,
-        -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-        PHYSTATUS_OUT                   =>      GTX0_PHYSTATUS_OUT,
-        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-        TXCHARISK_IN                    =>      GTX0_TXCHARISK_IN,
-        ------------------------- Transmit Ports - GTX Ports -----------------------
-        GTXTEST_IN                      =>      gtx0_gtxtest_i,
-        ------------------ Transmit Ports - TX Data Path interface -----------------
-        TXDATA_IN                       =>      GTX0_TXDATA_IN,
-        TXOUTCLK_OUT                    =>      GTX0_TXOUTCLK_OUT,
-        TXRESET_IN                      =>      gtx0_txreset_i,
-        TXUSRCLK2_IN                    =>      GTX0_TXUSRCLK2_IN,
-        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-        TXN_OUT                         =>      GTX0_TXN_OUT,
-        TXP_OUT                         =>      GTX0_TXP_OUT,
-        -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-        TXDLYALIGNDISABLE_IN            =>      GTX0_TXDLYALIGNDISABLE_IN,
-        TXDLYALIGNMONENB_IN             =>      GTX0_TXDLYALIGNMONENB_IN,
-        TXDLYALIGNMONITOR_OUT           =>      GTX0_TXDLYALIGNMONITOR_OUT,
-        TXDLYALIGNRESET_IN              =>      GTX0_TXDLYALIGNRESET_IN,
-        TXENPMAPHASEALIGN_IN            =>      GTX0_TXENPMAPHASEALIGN_IN,
-        TXPMASETPHASE_IN                =>      GTX0_TXPMASETPHASE_IN,
-        ----------------------- Transmit Ports - TX PLL Ports ----------------------
-        GTXTXRESET_IN                   =>      GTX0_GTXTXRESET_IN,
-        MGTREFCLKTX_IN                  =>      gtx0_mgtrefclkrx_i,
-        PLLTXRESET_IN                   =>      tied_to_ground_i,
-        TXPLLLKDET_OUT                  =>      open,
-        TXRESETDONE_OUT                 =>      GTX0_TXRESETDONE_OUT
-
-    );
-
-  
-  
-     gtx0_double_reset_i : DOUBLE_RESET
-     port map
-     (
-        CLK                             =>      GTX0_DOUBLE_RESET_CLK_IN,
-        PLLLKDET                        =>      gtx0_rxplllkdet_i,
-        GTXTEST_DONE                    =>      gtx0_gtxtest_done,
-        GTXTEST_BIT1                    =>      gtx0_gtxtest_bit1
-     );
-
-    
-
-     
-end RTL;
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_gtx.vhd b/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_gtx.vhd
deleted file mode 100644
index 89d3cfe..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_gtx.vhd
+++ /dev/null
@@ -1,639 +0,0 @@
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor: Xilinx
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
---  /   /         Filename : gtxvirtex6fee80_gtx.vhd
--- /___/   /\     
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Module GTXVIRTEX6FEE80_GTX (a GTX Wrapper)
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
---***************************** Entity Declaration ****************************
-
-entity gtxVirtex6FEE80_gtx is
-generic
-(
-    -- Simulation attributes
-    GTX_SIM_GTXRESET_SPEEDUP    : integer    := 0; -- Set to 1 to speed up sim reset
-    
-    -- Share RX PLL parameter
-    GTX_TX_CLK_SOURCE           : string     := "TXPLL";
-    -- Save power parameter
-    GTX_POWER_SAVE              : bit_vector := "0000000000"
-);
-port 
-(
-    ----------------------- Receive Ports - 8b10b Decoder ----------------------
-    RXCHARISK_OUT                           : out  std_logic;
-    RXDISPERR_OUT                           : out  std_logic;
-    RXNOTINTABLE_OUT                        : out  std_logic;
-    --------------- Receive Ports - Comma Detection and Alignment --------------
-    RXENMCOMMAALIGN_IN                      : in   std_logic;
-    RXENPCOMMAALIGN_IN                      : in   std_logic;
-    ------------------- Receive Ports - RX Data Path interface -----------------
-    RXDATA_OUT                              : out  std_logic_vector(7 downto 0);
-    RXRECCLK_OUT                            : out  std_logic;
-    RXRESET_IN                              : in   std_logic;
-    RXUSRCLK2_IN                            : in   std_logic;
-    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-    RXCDRRESET_IN                           : in   std_logic;
-    RXN_IN                                  : in   std_logic;
-    RXP_IN                                  : in   std_logic;
-    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-    RXDLYALIGNDISABLE_IN                    : in   std_logic;
-    RXDLYALIGNMONENB_IN                     : in   std_logic;
-    RXDLYALIGNMONITOR_OUT                   : out  std_logic_vector(7 downto 0);
-    RXDLYALIGNOVERRIDE_IN                   : in   std_logic;
-    RXDLYALIGNRESET_IN                      : in   std_logic;
-    RXENPMAPHASEALIGN_IN                    : in   std_logic;
-    RXPMASETPHASE_IN                        : in   std_logic;
-    RXSTATUS_OUT                            : out  std_logic_vector(2 downto 0);
-    --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-    RXLOSSOFSYNC_OUT                        : out  std_logic_vector(1 downto 0);
-    ------------------------ Receive Ports - RX PLL Ports ----------------------
-    GTXRXRESET_IN                           : in   std_logic;
-    MGTREFCLKRX_IN                          : in   std_logic_vector(1 downto 0);
-    PLLRXRESET_IN                           : in   std_logic;
-    RXPLLLKDET_OUT                          : out  std_logic;
-    RXRESETDONE_OUT                         : out  std_logic;
-    -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-    PHYSTATUS_OUT                           : out  std_logic;
-    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-    TXCHARISK_IN                            : in   std_logic;
-    ------------------------- Transmit Ports - GTX Ports -----------------------
-    GTXTEST_IN                              : in   std_logic_vector(12 downto 0);
-    ------------------ Transmit Ports - TX Data Path interface -----------------
-    TXDATA_IN                               : in   std_logic_vector(7 downto 0);
-    TXOUTCLK_OUT                            : out  std_logic;
-    TXRESET_IN                              : in   std_logic;
-    TXUSRCLK2_IN                            : in   std_logic;
-    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-    TXN_OUT                                 : out  std_logic;
-    TXP_OUT                                 : out  std_logic;
-    -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-    TXDLYALIGNDISABLE_IN                    : in   std_logic;
-    TXDLYALIGNMONENB_IN                     : in   std_logic;
-    TXDLYALIGNMONITOR_OUT                   : out  std_logic_vector(7 downto 0);
-    TXDLYALIGNRESET_IN                      : in   std_logic;
-    TXENPMAPHASEALIGN_IN                    : in   std_logic;
-    TXPMASETPHASE_IN                        : in   std_logic;
-    ----------------------- Transmit Ports - TX PLL Ports ----------------------
-    GTXTXRESET_IN                           : in   std_logic;
-    MGTREFCLKTX_IN                          : in   std_logic_vector(1 downto 0);
-    PLLTXRESET_IN                           : in   std_logic;
-    TXPLLLKDET_OUT                          : out  std_logic;
-    TXRESETDONE_OUT                         : out  std_logic
-
-
-);
-
-
-end gtxVirtex6FEE80_gtx;
-
-architecture RTL of gtxVirtex6FEE80_gtx is
-    
---**************************** Signal Declarations ****************************
-
-    -- ground and tied_to_vcc_i signals
-    signal  tied_to_ground_i                :   std_logic;
-    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
-    signal  tied_to_vcc_i                   :   std_logic;
-
-
-
-    -- RX Datapath signals
-    signal rxdata_i                         :   std_logic_vector(31 downto 0);      
-    signal rxchariscomma_float_i            :   std_logic_vector(2 downto 0);
-    signal rxcharisk_float_i                :   std_logic_vector(2 downto 0);
-    signal rxdisperr_float_i                :   std_logic_vector(2 downto 0);
-    signal rxnotintable_float_i             :   std_logic_vector(2 downto 0);
-    signal rxrundisp_float_i                :   std_logic_vector(2 downto 0);
-    
-
-
-    -- TX Datapath signals
-    signal txdata_i                         :   std_logic_vector(31 downto 0);
-    signal txkerr_float_i                   :   std_logic_vector(2 downto 0);
-    signal txrundisp_float_i                :   std_logic_vector(2 downto 0);
-
---******************************** Main Body of Code***************************
-                       
-begin                      
-
-    ---------------------------  Static signal Assignments ---------------------   
-
-    tied_to_ground_i                    <= '0';
-    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
-    tied_to_vcc_i                       <= '1';
-
-    -------------------  GTX Datapath byte mapping  -----------------
-
-    RXDATA_OUT    <=   rxdata_i(7 downto 0);
-
-    txdata_i    <=   (tied_to_ground_vec_i(23 downto 0) & TXDATA_IN);
-
-
-
-    ----------------------------- GTX Instance  --------------------------   
-
-    gtxe1_i :GTXE1
-    generic map
-    (
-
-        --_______________________ Simulation-Only Attributes ___________________
-
-        SIM_RECEIVER_DETECT_PASS   =>      (TRUE),
-        
-        SIM_GTXRESET_SPEEDUP       =>      (GTX_SIM_GTXRESET_SPEEDUP),
-
-        SIM_TX_ELEC_IDLE_LEVEL     =>      ("X"),
-
-        SIM_VERSION                =>      ("2.0"),
-        SIM_TXREFCLK_SOURCE        =>      ("000"),
-        SIM_RXREFCLK_SOURCE        =>      ("000"),
-        
-
-       ----------------------------TX PLL----------------------------
-        TX_CLK_SOURCE                           =>     (GTX_TX_CLK_SOURCE),
-        TX_OVERSAMPLE_MODE                      =>     (FALSE),
-        TXPLL_COM_CFG                           =>     (x"21680a"),
-        TXPLL_CP_CFG                            =>     (x"07"),
-        TXPLL_DIVSEL_FB                         =>     (5),
-        TXPLL_DIVSEL_OUT                        =>     (2),
-        TXPLL_DIVSEL_REF                        =>     (1),
-        TXPLL_DIVSEL45_FB                       =>     (5),
-        TXPLL_LKDET_CFG                         =>     ("111"),
-        TX_CLK25_DIVIDER                        =>     (4),
-        TXPLL_SATA                              =>     ("00"),
-        TX_TDCC_CFG                             =>     ("00"),
-        PMA_CAS_CLK_EN                          =>     (FALSE),
-        POWER_SAVE                              =>     (GTX_POWER_SAVE),
-
-       -------------------------TX Interface-------------------------
-        GEN_TXUSRCLK                            =>     (TRUE),
-        TX_DATA_WIDTH                           =>     (10),
-        TX_USRCLK_CFG                           =>     (x"00"),
-        TXOUTCLK_CTRL                           =>     ("TXPLLREFCLK_DIV1"),
-        TXOUTCLK_DLY                            =>     ("0000000000"),
-
-       --------------TX Buffering and Phase Alignment----------------
-        TX_PMADATA_OPT                          =>     ('1'),
-        PMA_TX_CFG                              =>     (x"80082"),
-        TX_BUFFER_USE                           =>     (FALSE),
-        TX_BYTECLK_CFG                          =>     (x"00"),
-        TX_EN_RATE_RESET_BUF                    =>     (TRUE),
-        TX_XCLK_SEL                             =>     ("TXUSR"),
-        TX_DLYALIGN_CTRINC                      =>     ("0100"),
-        TX_DLYALIGN_LPFINC                      =>     ("0110"),
-        TX_DLYALIGN_MONSEL                      =>     ("000"),
-        TX_DLYALIGN_OVRDSETTING                 =>     ("10000000"),
-
-       -------------------------TX Gearbox---------------------------
-        GEARBOX_ENDEC                           =>     ("000"),
-        TXGEARBOX_USE                           =>     (FALSE),
-
-       ----------------TX Driver and OOB Signalling------------------
-        TX_DRIVE_MODE                           =>     ("DIRECT"),
-        TX_IDLE_ASSERT_DELAY                    =>     ("101"),
-        TX_IDLE_DEASSERT_DELAY                  =>     ("011"),
-        TXDRIVE_LOOPBACK_HIZ                    =>     (FALSE),
-        TXDRIVE_LOOPBACK_PD                     =>     (FALSE),
-
-       --------------TX Pipe Control for PCI Express/SATA------------
-        COM_BURST_VAL                           =>     ("1111"),
-
-       ------------------TX Attributes for PCI Express---------------
-        TX_DEEMPH_0                             =>     ("11010"),
-        TX_DEEMPH_1                             =>     ("10000"),
-        TX_MARGIN_FULL_0                        =>     ("1001110"),
-        TX_MARGIN_FULL_1                        =>     ("1001001"),
-        TX_MARGIN_FULL_2                        =>     ("1000101"),
-        TX_MARGIN_FULL_3                        =>     ("1000010"),
-        TX_MARGIN_FULL_4                        =>     ("1000000"),
-        TX_MARGIN_LOW_0                         =>     ("1000110"),
-        TX_MARGIN_LOW_1                         =>     ("1000100"),
-        TX_MARGIN_LOW_2                         =>     ("1000010"),
-        TX_MARGIN_LOW_3                         =>     ("1000000"),
-        TX_MARGIN_LOW_4                         =>     ("1000000"),
-
-       ----------------------------RX PLL----------------------------
-        RX_OVERSAMPLE_MODE                      =>     (FALSE),
-        RXPLL_COM_CFG                           =>     (x"21680a"),
-        RXPLL_CP_CFG                            =>     (x"07"),
-        RXPLL_DIVSEL_FB                         =>     (5),
-        RXPLL_DIVSEL_OUT                        =>     (2),
-        RXPLL_DIVSEL_REF                        =>     (1),
-        RXPLL_DIVSEL45_FB                       =>     (5),
-        RXPLL_LKDET_CFG                         =>     ("111"),
-        RX_CLK25_DIVIDER                        =>     (4),
-
-       -------------------------RX Interface-------------------------
-        GEN_RXUSRCLK                            =>     (TRUE),
-        RX_DATA_WIDTH                           =>     (10),
-        RXRECCLK_CTRL                           =>     ("RXRECCLKPMA_DIV1"),
-        RXRECCLK_DLY                            =>     ("0000000000"),
-        RXUSRCLK_DLY                            =>     (x"0000"),
-
-       ----------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
-        AC_CAP_DIS                              =>     (TRUE),
-        CDR_PH_ADJ_TIME                         =>     ("10100"),
-        OOBDETECT_THRESHOLD                     =>     ("011"),
-        PMA_CDR_SCAN                            =>     (x"640404C"),
-        PMA_RX_CFG                              =>     (x"05ce008"),
-        RCV_TERM_GND                            =>     (FALSE),
-        RCV_TERM_VTTRX                          =>     (TRUE),
-        RX_EN_IDLE_HOLD_CDR                     =>     (FALSE),
-        RX_EN_IDLE_RESET_FR                     =>     (FALSE),
-        RX_EN_IDLE_RESET_PH                     =>     (FALSE),
-        TX_DETECT_RX_CFG                        =>     (x"1832"),
-        TERMINATION_CTRL                        =>     ("00000"),
-        TERMINATION_OVRD                        =>     (FALSE),
-        CM_TRIM                                 =>     ("01"),
-        PMA_RXSYNC_CFG                          =>     (x"00"),
-        PMA_CFG                                 =>     (x"0040000040000000003"),
-        BGTEST_CFG                              =>     ("00"),
-        BIAS_CFG                                =>     (x"00000"),
-
-       --------------RX Decision Feedback Equalizer(DFE)-------------
-        DFE_CAL_TIME                            =>     ("01100"),
-        DFE_CFG                                 =>     ("00011011"),
-        RX_EN_IDLE_HOLD_DFE                     =>     (TRUE),
-        RX_EYE_OFFSET                           =>     (x"4C"),
-        RX_EYE_SCANMODE                         =>     ("00"),
-
-       -------------------------PRBS Detection-----------------------
-        RXPRBSERR_LOOPBACK                      =>     ('0'),
-
-       ------------------Comma Detection and Alignment---------------
-        ALIGN_COMMA_WORD                        =>     (1),
-        COMMA_10B_ENABLE                        =>     ("1111111100"),
-        COMMA_DOUBLE                            =>     (FALSE),
-        DEC_MCOMMA_DETECT                       =>     (FALSE),
-        DEC_PCOMMA_DETECT                       =>     (FALSE),
-        DEC_VALID_COMMA_ONLY                    =>     (FALSE),
-        MCOMMA_10B_VALUE                        =>     ("1010000011"),
-        MCOMMA_DETECT                           =>     (TRUE),
-        PCOMMA_10B_VALUE                        =>     ("0101111100"),
-        PCOMMA_DETECT                           =>     (TRUE),
-        RX_DECODE_SEQ_MATCH                     =>     (TRUE),
-        RX_SLIDE_AUTO_WAIT                      =>     (5),
-        RX_SLIDE_MODE                           =>     ("OFF"),
-        SHOW_REALIGN_COMMA                      =>     (TRUE),
-
-       -----------------RX Loss-of-sync State Machine----------------
-        RX_LOS_INVALID_INCR                     =>     (8),
-        RX_LOS_THRESHOLD                        =>     (256),
-        RX_LOSS_OF_SYNC_FSM                     =>     (TRUE),
-
-       -------------------------RX Gearbox---------------------------
-        RXGEARBOX_USE                           =>     (FALSE),
-
-       -------------RX Elastic Buffer and Phase alignment------------
-        RX_BUFFER_USE                           =>     (FALSE),
-        RX_EN_IDLE_RESET_BUF                    =>     (FALSE),
-        RX_EN_MODE_RESET_BUF                    =>     (TRUE),
-        RX_EN_RATE_RESET_BUF                    =>     (TRUE),
-        RX_EN_REALIGN_RESET_BUF                 =>     (FALSE),
-        RX_EN_REALIGN_RESET_BUF2                =>     (FALSE),
-        RX_FIFO_ADDR_MODE                       =>     ("FAST"),
-        RX_IDLE_HI_CNT                          =>     ("1000"),
-        RX_IDLE_LO_CNT                          =>     ("0000"),
-        RX_XCLK_SEL                             =>     ("RXUSR"),
-        RX_DLYALIGN_CTRINC                      =>     ("1110"),
-        RX_DLYALIGN_EDGESET                     =>     ("00010"),
-        RX_DLYALIGN_LPFINC                      =>     ("1110"),
-        RX_DLYALIGN_MONSEL                      =>     ("000"),
-        RX_DLYALIGN_OVRDSETTING                 =>     ("10000000"),
-
-       ------------------------Clock Correction----------------------
-        CLK_COR_ADJ_LEN                         =>     (1),
-        CLK_COR_DET_LEN                         =>     (1),
-        CLK_COR_INSERT_IDLE_FLAG                =>     (FALSE),
-        CLK_COR_KEEP_IDLE                       =>     (FALSE),
-        CLK_COR_MAX_LAT                         =>     (16),
-        CLK_COR_MIN_LAT                         =>     (14),
-        CLK_COR_PRECEDENCE                      =>     (TRUE),
-        CLK_COR_REPEAT_WAIT                     =>     (0),
-        CLK_COR_SEQ_1_1                         =>     ("0100000000"),
-        CLK_COR_SEQ_1_2                         =>     ("0100000000"),
-        CLK_COR_SEQ_1_3                         =>     ("0100000000"),
-        CLK_COR_SEQ_1_4                         =>     ("0100000000"),
-        CLK_COR_SEQ_1_ENABLE                    =>     ("1111"),
-        CLK_COR_SEQ_2_1                         =>     ("0100000000"),
-        CLK_COR_SEQ_2_2                         =>     ("0100000000"),
-        CLK_COR_SEQ_2_3                         =>     ("0100000000"),
-        CLK_COR_SEQ_2_4                         =>     ("0100000000"),
-        CLK_COR_SEQ_2_ENABLE                    =>     ("1111"),
-        CLK_COR_SEQ_2_USE                       =>     (FALSE),
-        CLK_CORRECT_USE                         =>     (FALSE),
-
-       ------------------------Channel Bonding----------------------
-        CHAN_BOND_1_MAX_SKEW                    =>     (1),
-        CHAN_BOND_2_MAX_SKEW                    =>     (1),
-        CHAN_BOND_KEEP_ALIGN                    =>     (FALSE),
-        CHAN_BOND_SEQ_1_1                       =>     ("0000000000"),
-        CHAN_BOND_SEQ_1_2                       =>     ("0000000000"),
-        CHAN_BOND_SEQ_1_3                       =>     ("0000000000"),
-        CHAN_BOND_SEQ_1_4                       =>     ("0000000000"),
-        CHAN_BOND_SEQ_1_ENABLE                  =>     ("1111"),
-        CHAN_BOND_SEQ_2_1                       =>     ("0000000000"),
-        CHAN_BOND_SEQ_2_2                       =>     ("0000000000"),
-        CHAN_BOND_SEQ_2_3                       =>     ("0000000000"),
-        CHAN_BOND_SEQ_2_4                       =>     ("0000000000"),
-        CHAN_BOND_SEQ_2_CFG                     =>     ("00000"),
-        CHAN_BOND_SEQ_2_ENABLE                  =>     ("1111"),
-        CHAN_BOND_SEQ_2_USE                     =>     (FALSE),
-        CHAN_BOND_SEQ_LEN                       =>     (1),
-        PCI_EXPRESS_MODE                        =>     (FALSE),
-
-       -------------RX Attributes for PCI Express/SATA/SAS----------
-        SAS_MAX_COMSAS                          =>     (52),
-        SAS_MIN_COMSAS                          =>     (40),
-        SATA_BURST_VAL                          =>     ("100"),
-        SATA_IDLE_VAL                           =>     ("100"),
-        SATA_MAX_BURST                          =>     (11),
-        SATA_MAX_INIT                           =>     (34),
-        SATA_MAX_WAKE                           =>     (11),
-        SATA_MIN_BURST                          =>     (6),
-        SATA_MIN_INIT                           =>     (19),
-        SATA_MIN_WAKE                           =>     (6),
-        TRANS_TIME_FROM_P2                      =>     (x"03c"),
-        TRANS_TIME_NON_P2                       =>     (x"19"),
-        TRANS_TIME_RATE                         =>     (x"ff"),
-        TRANS_TIME_TO_P2                        =>     (x"064")
-
-
-     )
-     port map
-     (
-                      ------------------------ Loopback and Powerdown Ports ----------------------
-        LOOPBACK                        =>      tied_to_ground_vec_i(2 downto 0),
-        RXPOWERDOWN                     =>      "00",
-        TXPOWERDOWN                     =>      "00",
-        -------------- Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
-        RXDATAVALID                     =>      open,
-        RXGEARBOXSLIP                   =>      tied_to_ground_i,
-        RXHEADER                        =>      open,
-        RXHEADERVALID                   =>      open,
-        RXSTARTOFSEQ                    =>      open,
-        ----------------------- Receive Ports - 8b10b Decoder ----------------------
-        RXCHARISCOMMA                   =>      open,
-        RXCHARISK(3 downto 1)           =>      rxcharisk_float_i,
-        RXCHARISK(0)                    =>      RXCHARISK_OUT,
-        RXDEC8B10BUSE                   =>      tied_to_vcc_i,
-        RXDISPERR(3 downto 1)           =>      rxdisperr_float_i,
-        RXDISPERR(0)                    =>      RXDISPERR_OUT,
-        RXNOTINTABLE(3 downto 1)        =>      rxnotintable_float_i,
-        RXNOTINTABLE(0)                 =>      RXNOTINTABLE_OUT,
-        RXRUNDISP                       =>      open,
-        USRCODEERR                      =>      tied_to_ground_i,
-        ------------------- Receive Ports - Channel Bonding Ports ------------------
-        RXCHANBONDSEQ                   =>      open,
-        RXCHBONDI                       =>      tied_to_ground_vec_i(3 downto 0),
-        RXCHBONDLEVEL                   =>      tied_to_ground_vec_i(2 downto 0),
-        RXCHBONDMASTER                  =>      tied_to_ground_i,
-        RXCHBONDO                       =>      open,
-        RXCHBONDSLAVE                   =>      tied_to_ground_i,
-        RXENCHANSYNC                    =>      tied_to_ground_i,
-        ------------------- Receive Ports - Clock Correction Ports -----------------
-        RXCLKCORCNT                     =>      open,
-        --------------- Receive Ports - Comma Detection and Alignment --------------
-        RXBYTEISALIGNED                 =>      open,
-        RXBYTEREALIGN                   =>      open,
-        RXCOMMADET                      =>      open,
-        RXCOMMADETUSE                   =>      tied_to_vcc_i,
-        RXENMCOMMAALIGN                 =>      RXENMCOMMAALIGN_IN,
-        RXENPCOMMAALIGN                 =>      RXENPCOMMAALIGN_IN,
-        RXSLIDE                         =>      tied_to_ground_i,
-        ----------------------- Receive Ports - PRBS Detection ---------------------
-        PRBSCNTRESET                    =>      tied_to_ground_i,
-        RXENPRBSTST                     =>      tied_to_ground_vec_i(2 downto 0),
-        RXPRBSERR                       =>      open,
-        ------------------- Receive Ports - RX Data Path interface -----------------
-        RXDATA                          =>      rxdata_i,
-        RXRECCLK                        =>      RXRECCLK_OUT,
-        RXRECCLKPCS                     =>      open,
-        RXRESET                         =>      RXRESET_IN,
-        RXUSRCLK                        =>      tied_to_ground_i,
-        RXUSRCLK2                       =>      RXUSRCLK2_IN,
-        ------------ Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
-        DFECLKDLYADJ                    =>      tied_to_ground_vec_i(5 downto 0),
-        DFECLKDLYADJMON                 =>      open,
-        DFEDLYOVRD                      =>      tied_to_ground_i,
-        DFEEYEDACMON                    =>      open,
-        DFESENSCAL                      =>      open,
-        DFETAP1                         =>      tied_to_ground_vec_i(4 downto 0),
-        DFETAP1MONITOR                  =>      open,
-        DFETAP2                         =>      tied_to_ground_vec_i(4 downto 0),
-        DFETAP2MONITOR                  =>      open,
-        DFETAP3                         =>      tied_to_ground_vec_i(3 downto 0),
-        DFETAP3MONITOR                  =>      open,
-        DFETAP4                         =>      tied_to_ground_vec_i(3 downto 0),
-        DFETAP4MONITOR                  =>      open,
-        DFETAPOVRD                      =>      tied_to_vcc_i,
-        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-        GATERXELECIDLE                  =>      tied_to_vcc_i,
-        IGNORESIGDET                    =>      tied_to_vcc_i,
-        RXCDRRESET                      =>      RXCDRRESET_IN,
-        RXELECIDLE                      =>      open,
-        RXEQMIX                         =>      "0000000000",
-        RXN                             =>      RXN_IN,
-        RXP                             =>      RXP_IN,
-        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-        RXBUFRESET                      =>      tied_to_ground_i,
-        RXBUFSTATUS                     =>      open,
-        RXCHANISALIGNED                 =>      open,
-        RXCHANREALIGN                   =>      open,
-        RXDLYALIGNDISABLE               =>      RXDLYALIGNDISABLE_IN,
-        RXDLYALIGNMONENB                =>      RXDLYALIGNMONENB_IN,
-        RXDLYALIGNMONITOR               =>      RXDLYALIGNMONITOR_OUT,
-        RXDLYALIGNOVERRIDE              =>      RXDLYALIGNOVERRIDE_IN,
-        RXDLYALIGNRESET                 =>      RXDLYALIGNRESET_IN,
-        RXDLYALIGNSWPPRECURB            =>      tied_to_vcc_i,
-        RXDLYALIGNUPDSW                 =>      tied_to_ground_i,
-        RXENPMAPHASEALIGN               =>      RXENPMAPHASEALIGN_IN,
-        RXPMASETPHASE                   =>      RXPMASETPHASE_IN,
-        RXSTATUS                        =>      RXSTATUS_OUT,
-        --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-        RXLOSSOFSYNC                    =>      RXLOSSOFSYNC_OUT,
-        ---------------------- Receive Ports - RX Oversampling ---------------------
-        RXENSAMPLEALIGN                 =>      tied_to_ground_i,
-        RXOVERSAMPLEERR                 =>      open,
-        ------------------------ Receive Ports - RX PLL Ports ----------------------
-        GREFCLKRX                       =>      tied_to_ground_i,
-        GTXRXRESET                      =>      GTXRXRESET_IN,
-        MGTREFCLKRX                     =>      MGTREFCLKRX_IN,
-        NORTHREFCLKRX                   =>      tied_to_ground_vec_i(1 downto 0),
-        PERFCLKRX                       =>      tied_to_ground_i,
-        PLLRXRESET                      =>      PLLRXRESET_IN,
-        RXPLLLKDET                      =>      RXPLLLKDET_OUT,
-        RXPLLLKDETEN                    =>      tied_to_vcc_i,
-        RXPLLPOWERDOWN                  =>      tied_to_ground_i,
-        RXPLLREFSELDY                   =>      tied_to_ground_vec_i(2 downto 0),
-        RXRATE                          =>      tied_to_ground_vec_i(1 downto 0),
-        RXRATEDONE                      =>      open,
-        RXRESETDONE                     =>      RXRESETDONE_OUT,
-        SOUTHREFCLKRX                   =>      tied_to_ground_vec_i(1 downto 0),
-        -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-        PHYSTATUS                       =>      PHYSTATUS_OUT,
-        RXVALID                         =>      open,
-        ----------------- Receive Ports - RX Polarity Control Ports ----------------
-        RXPOLARITY                      =>      tied_to_ground_i,
-        --------------------- Receive Ports - RX Ports for SATA --------------------
-        COMINITDET                      =>      open,
-        COMSASDET                       =>      open,
-        COMWAKEDET                      =>      open,
-        ------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
-        DADDR                           =>      tied_to_ground_vec_i(7 downto 0),
-        DCLK                            =>      tied_to_ground_i,
-        DEN                             =>      tied_to_ground_i,
-        DI                              =>      tied_to_ground_vec_i(15 downto 0),
-        DRDY                            =>      open,
-        DRPDO                           =>      open,
-        DWE                             =>      tied_to_ground_i,
-        -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
-        TXGEARBOXREADY                  =>      open,
-        TXHEADER                        =>      tied_to_ground_vec_i(2 downto 0),
-        TXSEQUENCE                      =>      tied_to_ground_vec_i(6 downto 0),
-        TXSTARTSEQ                      =>      tied_to_ground_i,
-        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-        TXBYPASS8B10B                   =>      tied_to_ground_vec_i(3 downto 0),
-        TXCHARDISPMODE                  =>      tied_to_ground_vec_i(3 downto 0),
-        TXCHARDISPVAL                   =>      tied_to_ground_vec_i(3 downto 0),
-        TXCHARISK(3 downto 1)           =>      tied_to_ground_vec_i(2 downto 0),
-        TXCHARISK(0)                    =>      TXCHARISK_IN,
-        TXENC8B10BUSE                   =>      tied_to_vcc_i,
-        TXKERR                          =>      open,
-        TXRUNDISP                       =>      open,
-        ------------------------- Transmit Ports - GTX Ports -----------------------
-        GTXTEST                         =>      GTXTEST_IN,
-        MGTREFCLKFAB                    =>      open,
-        TSTCLK0                         =>      tied_to_ground_i,
-        TSTCLK1                         =>      tied_to_ground_i,
-        TSTIN                           =>      "11111111111111111111",
-        TSTOUT                          =>      open,
-        ------------------ Transmit Ports - TX Data Path interface -----------------
-        TXDATA                          =>      txdata_i,
-        TXOUTCLK                        =>      TXOUTCLK_OUT,
-        TXOUTCLKPCS                     =>      open,
-        TXRESET                         =>      TXRESET_IN,
-        TXUSRCLK                        =>      tied_to_ground_i,
-        TXUSRCLK2                       =>      TXUSRCLK2_IN,
-        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-        TXBUFDIFFCTRL                   =>      "100",
-        TXDIFFCTRL                      =>      "1000",
-        TXINHIBIT                       =>      tied_to_ground_i,
-        TXN                             =>      TXN_OUT,
-        TXP                             =>      TXP_OUT,
-        TXPOSTEMPHASIS                  =>      "00000",
-        --------------- Transmit Ports - TX Driver and OOB signalling --------------
-        TXPREEMPHASIS                   =>      "0000",
-        ----------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
-        TXBUFSTATUS                     =>      open,
-        -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-        TXDLYALIGNDISABLE               =>      TXDLYALIGNDISABLE_IN,
-        TXDLYALIGNMONENB                =>      TXDLYALIGNMONENB_IN,
-        TXDLYALIGNMONITOR               =>      TXDLYALIGNMONITOR_OUT,
-        TXDLYALIGNOVERRIDE              =>      tied_to_ground_i,
-        TXDLYALIGNRESET                 =>      TXDLYALIGNRESET_IN,
-        TXDLYALIGNUPDSW                 =>      tied_to_ground_i,
-        TXENPMAPHASEALIGN               =>      TXENPMAPHASEALIGN_IN,
-        TXPMASETPHASE                   =>      TXPMASETPHASE_IN,
-        ----------------------- Transmit Ports - TX PLL Ports ----------------------
-        GREFCLKTX                       =>      tied_to_ground_i,
-        GTXTXRESET                      =>      GTXTXRESET_IN,
-        MGTREFCLKTX                     =>      MGTREFCLKTX_IN,
-        NORTHREFCLKTX                   =>      tied_to_ground_vec_i(1 downto 0),
-        PERFCLKTX                       =>      tied_to_ground_i,
-        PLLTXRESET                      =>      PLLTXRESET_IN,
-        SOUTHREFCLKTX                   =>      tied_to_ground_vec_i(1 downto 0),
-        TXPLLLKDET                      =>      TXPLLLKDET_OUT,
-        TXPLLLKDETEN                    =>      tied_to_vcc_i,
-        TXPLLPOWERDOWN                  =>      tied_to_ground_i,
-        TXPLLREFSELDY                   =>      tied_to_ground_vec_i(2 downto 0),
-        TXRATE                          =>      tied_to_ground_vec_i(1 downto 0),
-        TXRATEDONE                      =>      open,
-        TXRESETDONE                     =>      TXRESETDONE_OUT,
-        --------------------- Transmit Ports - TX PRBS Generator -------------------
-        TXENPRBSTST                     =>      tied_to_ground_vec_i(2 downto 0),
-        TXPRBSFORCEERR                  =>      tied_to_ground_i,
-        -------------------- Transmit Ports - TX Polarity Control ------------------
-        TXPOLARITY                      =>      tied_to_ground_i,
-        ----------------- Transmit Ports - TX Ports for PCI Express ----------------
-        TXDEEMPH                        =>      tied_to_ground_i,
-        TXDETECTRX                      =>      tied_to_ground_i,
-        TXELECIDLE                      =>      tied_to_ground_i,
-        TXMARGIN                        =>      tied_to_ground_vec_i(2 downto 0),
-        TXPDOWNASYNCH                   =>      tied_to_ground_i,
-        TXSWING                         =>      tied_to_ground_i,
-        --------------------- Transmit Ports - TX Ports for SATA -------------------
-        COMFINISH                       =>      open,
-        TXCOMINIT                       =>      tied_to_ground_i,
-        TXCOMSAS                        =>      tied_to_ground_i,
-        TXCOMWAKE                       =>      tied_to_ground_i
-
-     );
- 
- end RTL;
-
-
- 
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_rx_sync.vhd b/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_rx_sync.vhd
deleted file mode 100644
index f3fd3cf..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_rx_sync.vhd
+++ /dev/null
@@ -1,244 +0,0 @@
-------------------------------------------------------------------------------
---   ____  ____ 
---  /   /\/   /
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard 
---  /   /         Filename : gtxvirtex6fee80_rx_sync.vhd
--- /___/   /\     
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Module gtxvirtex6fee80_rx_sync
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
-entity gtxvirtex6fee80_rx_sync is
-port
-(
-    RXENPMAPHASEALIGN    :   out   std_logic;
-    RXPMASETPHASE        :   out   std_logic;
-    RXDLYALIGNDISABLE    :   out   std_logic;
-    RXDLYALIGNOVERRIDE   :   out   std_logic;
-    RXDLYALIGNRESET      :   out   std_logic;
-    SYNC_DONE            :   out   std_logic;
-    USER_CLK             :   in    std_logic;
-    RESET                :   in    std_logic
-);
-
-
-end gtxvirtex6fee80_rx_sync;
-
-architecture RTL of gtxvirtex6fee80_rx_sync is
---***********************************Parameter Declarations********************
-
-    constant DLY : time := 1 ns;
-
---*******************************Register Declarations************************
-
-    signal   begin_r                        :   std_logic;
-    signal   phase_align_r                  :   std_logic;
-    signal   ready_r                        :   std_logic;
-    signal   sync_counter_r                 :   unsigned(5 downto 0);
-    signal   sync_done_count_r              :   unsigned(5 downto 0);
-    signal   align_reset_counter_r          :   unsigned(4 downto 0);
-    signal   wait_after_sync_r              :   std_logic;
-    signal   wait_before_setphase_counter_r :   unsigned(5 downto 0);
-    signal   wait_before_setphase_r         :   std_logic;
-    signal   align_reset_r                  :   std_logic;
-    
---*******************************Wire Declarations****************************
-    
-    signal   count_32_setphase_complete_r   :   std_logic;
-    signal   count_32_wait_complete_r       :   std_logic;
-    signal   count_align_reset_complete_r   :   std_logic;
-    signal   next_phase_align_c             :   std_logic;
-    signal   next_align_reset_c             :   std_logic;
-    signal   next_ready_c                   :   std_logic;
-    signal   next_wait_after_sync_c         :   std_logic;
-    signal   next_wait_before_setphase_c    :   std_logic;
-    signal   sync_32_times_done_r           :   std_logic;
-    
-    attribute max_fanout:string; 
-    attribute max_fanout of ready_r : signal is "2";
-
-begin
---*******************************Main Body of Code****************************
-
-    --________________________________ State machine __________________________    
-    -- This state machine manages the phase alingment procedure of the GTX on the
-    -- receive side. The module is held in reset till the usrclk source is stable
-    -- and RXRESETDONE is asserted. In the case that a MMCM is used to generate 
-    -- rxusrclk, the mmcm_locked signal is used to indicate a stable usrclk source.
-    -- Once RXRESETDONE and mmcm_locked are asserted, the state machine goes 
-    -- into the align_reset_r state where RXDLYALIGNRESET is asserted for 20 cycles. 
-    -- After this, it goes into the wait_before_setphase_r state for 32 cycles. 
-    -- After asserting RXENPMAPHASEALIGN and waiting 32 cycles, it enters the 
-    -- phase_align_r state where RXPMASETPHASE is asserted for 32 clock cycles. 
-    -- After the port is deasserted, the state machine goes into a wait state for
-    -- 32 cycles. This procedure is repeated 32 times.
-    
-    -- State registers
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(RESET='1') then
-                begin_r                 <=  '1' after DLY;
-                align_reset_r           <=  '0' after DLY;
-                wait_before_setphase_r  <=  '0' after DLY;
-                phase_align_r           <=  '0' after DLY;
-                wait_after_sync_r       <=  '0' after DLY;
-                ready_r                 <=  '0' after DLY;
-            else
-                begin_r                 <=  '0' after DLY;
-                align_reset_r           <=  next_align_reset_c after DLY;
-                wait_before_setphase_r  <=  next_wait_before_setphase_c after DLY;
-                phase_align_r           <=  next_phase_align_c after DLY;
-                wait_after_sync_r       <=  next_wait_after_sync_c after DLY;
-                ready_r                 <=  next_ready_c after DLY;
-            end if;
-        end if;
-    end process;
-
-    -- Next state logic
-    next_align_reset_c          <=  begin_r or
-                                    (align_reset_r and  not count_align_reset_complete_r);
-                                 
-    next_wait_before_setphase_c <=  (align_reset_r and count_align_reset_complete_r) or
-                                    (wait_before_setphase_r and not count_32_wait_complete_r);                                
-                                        
-    next_phase_align_c          <=  (wait_before_setphase_r and count_32_wait_complete_r) or
-                                    (phase_align_r and not count_32_setphase_complete_r) or
-                                    (wait_after_sync_r and count_32_wait_complete_r and not sync_32_times_done_r);
-                                        
-    next_wait_after_sync_c      <=  (phase_align_r and count_32_setphase_complete_r) or
-                                    (wait_after_sync_r and not count_32_wait_complete_r);
-
-    next_ready_c                <=  (wait_after_sync_r and count_32_wait_complete_r and sync_32_times_done_r) or
-                                    ready_r;
-
-    --______ Counter for holding RXDLYALIGNRESET for 20 RXUSRCLK2 cycles ______
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (align_reset_r='0') then
-                align_reset_counter_r <= (others=>'0') after DLY;
-            else
-                align_reset_counter_r <= align_reset_counter_r + 1 after DLY;
-            end if;
-        end if ;
-    end process;
-        
-    count_align_reset_complete_r <= align_reset_counter_r(4)
-                                    and align_reset_counter_r(2);
-                                    
-    --_______Counter for waiting 32 clock cycles before RXPMASETPHASE _________
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if ((wait_before_setphase_r='0') and (wait_after_sync_r='0')) then
-                wait_before_setphase_counter_r <= (others=>'0') after DLY;
-            else
-                wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-    count_32_wait_complete_r <= wait_before_setphase_counter_r(5);
-    
-    --_______________ Counter for holding SYNC for SYNC_CYCLES ________________
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (phase_align_r='0') then
-                sync_counter_r <= (others=>'0') after DLY;
-            else
-                sync_counter_r <= sync_counter_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-    count_32_setphase_complete_r <= sync_counter_r(5);
-
-    --__________ Counter for counting number of times sync is done ____________
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (RESET='1') then
-                sync_done_count_r <= (others=>'0') after DLY;
-            elsif((count_32_wait_complete_r ='1') and (phase_align_r = '1')) then
-                sync_done_count_r <= sync_done_count_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-    sync_32_times_done_r <= sync_done_count_r(5);
-
-    --_______________ Assign the phase align ports into the GTX _______________
-
-    RXDLYALIGNRESET      <=  align_reset_r;
-    RXENPMAPHASEALIGN    <=  (not begin_r) and (not align_reset_r);
-    RXPMASETPHASE        <=  phase_align_r;
-    RXDLYALIGNDISABLE    <=  '1';
-    RXDLYALIGNOVERRIDE   <=  '1';
-
-    --_______________________ Assign the sync_done port _______________________
-    
-    SYNC_DONE <= ready_r;
-    
-    
-end RTL;
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_top.vhd b/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_top.vhd
deleted file mode 100644
index c99700c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_top.vhd
+++ /dev/null
@@ -1,1373 +0,0 @@
-------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor: Xilinx
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard 
---  /   /         Filename : gtxvirtex6fee80_top.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Module gtxVirtex6FEE80_top
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
---***********************************Entity Declaration************************
-
-entity gtxVirtex6FEE80_top is
-generic
-(
-    EXAMPLE_CONFIG_INDEPENDENT_LANES        : integer   := 1;
-    EXAMPLE_LANE_WITH_START_CHAR            : integer   := 0;    -- specifies lane with unique start frame ch
-    EXAMPLE_WORDS_IN_BRAM                   : integer   := 512;  -- specifies amount of data in BRAM
-    EXAMPLE_SIM_GTXRESET_SPEEDUP            : integer   := 1;    -- simulation setting for GTX SecureIP model
-    EXAMPLE_USE_CHIPSCOPE                   : integer   := 1     -- Set to 1 to use Chipscope to drive resets
-);
-port
-(
-    Q3_CLK0_MGTREFCLK_PAD_N_IN              : in   std_logic;
-    Q3_CLK0_MGTREFCLK_PAD_P_IN              : in   std_logic;
-    GTXTXRESET_IN                           : in   std_logic;
-    GTXRXRESET_IN                           : in   std_logic;
-    TRACK_DATA_OUT                          : out  std_logic;
-    RXN_IN                                  : in   std_logic;
-    RXP_IN                                  : in   std_logic;
-    TXN_OUT                                 : out  std_logic;
-    TXP_OUT                                 : out  std_logic
-    
-);
-
-
-end gtxVirtex6FEE80_top;
-    
-architecture RTL of gtxVirtex6FEE80_top is
-
---**************************Component Declarations*****************************
-
-
-component gtxVirtex6FEE80 
-generic
-(
-    -- Simulation attributes
-    WRAPPER_SIM_GTXRESET_SPEEDUP    : integer   := 0 -- Set to 1 to speed up sim reset
-);
-port
-(
-
-    --_________________________________________________________________________
-    --_________________________________________________________________________
-    --GTX0  (X0_Y12)
-
-      GTX0_DOUBLE_RESET_CLK_IN                : in   std_logic;
-    ----------------------- Receive Ports - 8b10b Decoder ----------------------
-    GTX0_RXCHARISK_OUT                      : out  std_logic;
-    GTX0_RXDISPERR_OUT                      : out  std_logic;
-    GTX0_RXNOTINTABLE_OUT                   : out  std_logic;
-    --------------- Receive Ports - Comma Detection and Alignment --------------
-    GTX0_RXENMCOMMAALIGN_IN                 : in   std_logic;
-    GTX0_RXENPCOMMAALIGN_IN                 : in   std_logic;
-    ------------------- Receive Ports - RX Data Path interface -----------------
-    GTX0_RXDATA_OUT                         : out  std_logic_vector(7 downto 0);
-    GTX0_RXRECCLK_OUT                       : out  std_logic;
-    GTX0_RXRESET_IN                         : in   std_logic;
-    GTX0_RXUSRCLK2_IN                       : in   std_logic;
-    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-    GTX0_RXCDRRESET_IN                      : in   std_logic;
-    GTX0_RXN_IN                             : in   std_logic;
-    GTX0_RXP_IN                             : in   std_logic;
-    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-    GTX0_RXDLYALIGNDISABLE_IN               : in   std_logic;
-    GTX0_RXDLYALIGNMONENB_IN                : in   std_logic;
-    GTX0_RXDLYALIGNMONITOR_OUT              : out  std_logic_vector(7 downto 0);
-    GTX0_RXDLYALIGNOVERRIDE_IN              : in   std_logic;
-    GTX0_RXDLYALIGNRESET_IN                 : in   std_logic;
-    GTX0_RXENPMAPHASEALIGN_IN               : in   std_logic;
-    GTX0_RXPMASETPHASE_IN                   : in   std_logic;
-    GTX0_RXSTATUS_OUT                       : out  std_logic_vector(2 downto 0);
-    --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-    GTX0_RXLOSSOFSYNC_OUT                   : out  std_logic_vector(1 downto 0);
-    ------------------------ Receive Ports - RX PLL Ports ----------------------
-    GTX0_GTXRXRESET_IN                      : in   std_logic;
-    GTX0_MGTREFCLKRX_IN                     : in   std_logic;
-    GTX0_PLLRXRESET_IN                      : in   std_logic;
-    GTX0_RXPLLLKDET_OUT                     : out  std_logic;
-    GTX0_RXRESETDONE_OUT                    : out  std_logic;
-    -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-    GTX0_PHYSTATUS_OUT                      : out  std_logic;
-    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-    GTX0_TXCHARISK_IN                       : in   std_logic;
-    ------------------ Transmit Ports - TX Data Path interface -----------------
-    GTX0_TXDATA_IN                          : in   std_logic_vector(7 downto 0);
-    GTX0_TXOUTCLK_OUT                       : out  std_logic;
-    GTX0_TXRESET_IN                         : in   std_logic;
-    GTX0_TXUSRCLK2_IN                       : in   std_logic;
-    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-    GTX0_TXN_OUT                            : out  std_logic;
-    GTX0_TXP_OUT                            : out  std_logic;
-    -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-    GTX0_TXDLYALIGNDISABLE_IN               : in   std_logic;
-    GTX0_TXDLYALIGNMONENB_IN                : in   std_logic;
-    GTX0_TXDLYALIGNMONITOR_OUT              : out  std_logic_vector(7 downto 0);
-    GTX0_TXDLYALIGNRESET_IN                 : in   std_logic;
-    GTX0_TXENPMAPHASEALIGN_IN               : in   std_logic;
-    GTX0_TXPMASETPHASE_IN                   : in   std_logic;
-    ----------------------- Transmit Ports - TX PLL Ports ----------------------
-    GTX0_GTXTXRESET_IN                      : in   std_logic;
-    GTX0_TXRESETDONE_OUT                    : out  std_logic
-
-
-);
-end component;
-
-component MGT_USRCLK_SOURCE 
-generic
-(
-    FREQUENCY_MODE   : string   := "LOW";    
-    PERFORMANCE_MODE : string   := "MAX_SPEED"    
-);
-port
-(
-    DIV1_OUT                : out std_logic;
-    DIV2_OUT                : out std_logic;
-    DCM_LOCKED_OUT          : out std_logic;
-    CLK_IN                  : in  std_logic;
-    DCM_RESET_IN            : in  std_logic
-
-);
-end component;
-
-component FRAME_GEN 
-generic
-(
-    WORDS_IN_BRAM : integer    :=   256;
-    MEM_00       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_01       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_02       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_03       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_04       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_05       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_06       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_07       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_08       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_09       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_10       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_11       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_12       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_13       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_14       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_15       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_16       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_17       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_18       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_19       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_20       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_21       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_22       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_23       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_24       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_25       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_26       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_27       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_28       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_29       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_30       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_31       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_32       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_33       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_34       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_35       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_36       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_37       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_38       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_39       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_00      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_01      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_02      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_03      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_04      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_05      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_06      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_07      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000"
-);    
-port
-(
-    -- User Interface
-    TX_DATA             : out   std_logic_vector(39 downto 0);
-    TX_CHARISK          : out   std_logic_vector(3 downto 0); 
-
-    -- System Interface
-    USER_CLK            : in    std_logic;
-    SYSTEM_RESET        : in    std_logic
-); 
-end component;
-
-component FRAME_CHECK 
-generic
-(
-    RX_DATA_WIDTH            : integer := 16;
-    RXCTRL_WIDTH             : integer := 2;
-    USE_COMMA                : integer := 1;
-    NONE_MSB_FIRST_DEC       : integer := 0;
-    COMMA_DOUBLE_DEC         : integer := 0;
-    CHANBOND_SEQ_LEN         : integer := 1;
-    WORDS_IN_BRAM            : integer := 256;
-    CONFIG_INDEPENDENT_LANES : integer := 0;
-    START_OF_PACKET_CHAR     : std_logic_vector(15 downto 0) ;
-    COMMA_DOUBLE_CHAR        : std_logic_vector(15 downto 0) := x"f628";
-    MEM_00       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_01       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_02       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_03       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_04       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_05       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_06       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_07       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_08       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_09       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_0F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_10       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_11       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_12       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_13       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_14       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_15       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_16       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_17       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_18       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_19       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_1F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_20       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_21       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_22       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_23       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_24       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_25       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_26       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_27       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_28       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_29       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_2F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_30       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_31       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_32       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_33       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_34       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_35       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_36       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_37       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_38       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_39       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3A       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3B       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3C       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3D       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3E       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEM_3F       : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_00      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_01      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_02      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_03      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_04      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_05      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_06      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000";
-    MEMP_07      : bit_vector :=   X"0000000000000000000000000000000000000000000000000000000000000000"
-);
-port
-(
-    -- User Interface
-    RX_DATA                  : in  std_logic_vector((RX_DATA_WIDTH-1) downto 0);
- 
-    RXCTRL_IN                : in  std_logic_vector((RXCTRL_WIDTH-1) downto 0);  
-    RX_ENMCOMMA_ALIGN        : out std_logic;
-    RX_ENPCOMMA_ALIGN        : out std_logic;
- 
-    RX_ENCHAN_SYNC           : out std_logic; 
-    RX_CHANBOND_SEQ          : in  std_logic; 
-
-    -- Control Interface
-    INC_IN                   : in std_logic; 
-    INC_OUT                  : out std_logic; 
-    PATTERN_MATCH_N          : out std_logic;
-    RESET_ON_ERROR           : in std_logic; 
-    
-    -- Error Monitoring
-    ERROR_COUNT              : out std_logic_vector(7 downto 0);
-    
-    -- Track Data
-    TRACK_DATA               : out std_logic;
- 
-    -- System Interface
-    USER_CLK                 : in std_logic;
-    SYSTEM_RESET             : in std_logic
-  
-);
-end component;
-
-component MGT_USRCLK_SOURCE_MMCM
-generic
-(
-    MULT                 : real             := 2.0;
-    DIVIDE               : integer          := 2;    
-    CLK_PERIOD           : real             := 6.4;    
-    OUT0_DIVIDE          : real             := 2.0;
-    OUT1_DIVIDE          : integer          := 2;
-    OUT2_DIVIDE          : integer          := 2;
-    OUT3_DIVIDE          : integer          := 2
-);
-port
-(
-    CLKFBOUT                : out std_logic; 
-    CLK0_OUT                : out std_logic;
-    CLK1_OUT                : out std_logic;
-    CLK2_OUT                : out std_logic;
-    CLK3_OUT                : out std_logic;
-    CLK_IN                  : in  std_logic;
-    MMCM_LOCKED_OUT         : out std_logic;
-    MMCM_RESET_IN           : in  std_logic
-);
-end component;
-
-component gtxVirtex6FEE80_tx_sync
-generic
-(
-    -- Simulation attributes
-    SIM_TXPMASETPHASE_SPEEDUP    : integer   := 0 -- Set to 1 to speed up sim reset
-);
-port
-(
-    TXENPMAPHASEALIGN       : out std_logic;
-    TXPMASETPHASE           : out std_logic;
-    TXDLYALIGNDISABLE       : out std_logic;
-    TXDLYALIGNRESET         : out std_logic;
-    SYNC_DONE               : out std_logic;
-    USER_CLK                : in  std_logic;
-    RESET                   : in  std_logic
-);
-end component;
-
-component gtxVirtex6FEE80_rx_sync
-port
-(
-    RXENPMAPHASEALIGN       : out std_logic;
-    RXPMASETPHASE           : out std_logic;
-    RXDLYALIGNDISABLE       : out std_logic;
-    RXDLYALIGNOVERRIDE      : out std_logic;
-    RXDLYALIGNRESET         : out std_logic;
-    SYNC_DONE               : out std_logic;
-    USER_CLK                : in  std_logic;
-    RESET                   : in  std_logic
-);
-end component;
-
-
--- Chipscope modules
-attribute syn_black_box                : boolean;
-attribute syn_noprune                  : boolean;
-
-
-component data_vio
-port
-(
-    control                 : inout std_logic_vector(35 downto 0);
-    clk                     : in    std_logic;
-    async_in                : in    std_logic_vector(31 downto 0);
-    async_out               : out   std_logic_vector(31 downto 0);
-    sync_in                 : in    std_logic_vector(31 downto 0);
-    sync_out                : out   std_logic_vector(31 downto 0)
-);
-end component;
-attribute syn_black_box of data_vio : component is TRUE;
-attribute syn_noprune of data_vio   : component is TRUE;
-
-
-component icon
-port
-(
-    control0                : inout std_logic_vector(35 downto 0);
-    control1                : inout std_logic_vector(35 downto 0);
-    control2                : inout std_logic_vector(35 downto 0);
-    control3                : inout std_logic_vector(35 downto 0)
-);
-end component;
-attribute syn_black_box of icon : component is TRUE;
-attribute syn_noprune of icon   : component is TRUE;
-
-
-component ila
-port
-(
-    control                 : inout std_logic_vector(35 downto 0);
-    clk                     : in    std_logic;
-    trig0                   : in    std_logic_vector(84 downto 0)
-);
-end component;
-
-
-attribute syn_black_box of ila : component is TRUE;
-attribute syn_noprune of ila   : component is TRUE;
-
-
---***********************************Parameter Declarations********************
-
-    constant DLY : time := 1 ns;
- 
-    attribute max_fanout : string; 
-
---************************** Register Declarations ****************************
-
-    signal   gtx0_txresetdone_r              : std_logic;
-    signal   gtx0_txresetdone_r2             : std_logic;
-    signal   gtx0_rxresetdone_i_r            : std_logic;
-    signal   gtx0_rxresetdone_r              : std_logic;
-    signal   gtx0_rxresetdone_r2             : std_logic;
-    signal   gtx0_rxresetdone_r3             : std_logic;
-    attribute max_fanout of gtx0_rxresetdone_i_r : signal is "1";
-    signal   gtx0_rxdata_r                   : std_logic_vector(7 downto 0);
-    signal   gtx0_rxcharisk_r                : std_logic_vector(0 downto 0);    
-
-
---**************************** Wire Declarations ******************************
-    -------------------------- MGT Wrapper Wires ------------------------------
-    --________________________________________________________________________
-    --________________________________________________________________________
-    --GTX0   (X0Y12)
-
-    ----------------------- Receive Ports - 8b10b Decoder ----------------------
-    signal  gtx0_rxcharisk_i                : std_logic;
-    signal  gtx0_rxdisperr_i                : std_logic;
-    signal  gtx0_rxnotintable_i             : std_logic;
-    --------------- Receive Ports - Comma Detection and Alignment --------------
-    signal  gtx0_rxenmcommaalign_i          : std_logic;
-    signal  gtx0_rxenpcommaalign_i          : std_logic;
-    ------------------- Receive Ports - RX Data Path interface -----------------
-    signal  gtx0_rxdata_i                   : std_logic_vector(7 downto 0);
-    signal  gtx0_rxrecclk_i                 : std_logic;
-    signal  gtx0_rxreset_i                  : std_logic;
-    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-    signal  gtx0_rxcdrreset_i               : std_logic;
-    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-    signal  gtx0_rxdlyaligndisable_i        : std_logic;
-    signal  gtx0_rxdlyalignmonenb_i         : std_logic;
-    signal  gtx0_rxdlyalignmonitor_i        : std_logic_vector(7 downto 0);
-    signal  gtx0_rxdlyalignoverride_i       : std_logic;
-    signal  gtx0_rxdlyalignreset_i          : std_logic;
-    signal  gtx0_rxenpmaphasealign_i        : std_logic;
-    signal  gtx0_rxpmasetphase_i            : std_logic;
-    signal  gtx0_rxstatus_i                 : std_logic_vector(2 downto 0);
-    --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-    signal  gtx0_rxlossofsync_i             : std_logic_vector(1 downto 0);
-    ------------------------ Receive Ports - RX PLL Ports ----------------------
-    signal  gtx0_gtxrxreset_i               : std_logic;
-    signal  gtx0_pllrxreset_i               : std_logic;
-    signal  gtx0_rxplllkdet_i               : std_logic;
-    signal  gtx0_rxresetdone_i              : std_logic;
-    -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-    signal  gtx0_phystatus_i                : std_logic;
-    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-    signal  gtx0_txcharisk_i                : std_logic;
-    ------------------ Transmit Ports - TX Data Path interface -----------------
-    signal  gtx0_txdata_i                   : std_logic_vector(7 downto 0);
-    signal  gtx0_txoutclk_i                 : std_logic;
-    signal  gtx0_txreset_i                  : std_logic;
-    -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-    signal  gtx0_txdlyaligndisable_i        : std_logic;
-    signal  gtx0_txdlyalignmonenb_i         : std_logic;
-    signal  gtx0_txdlyalignmonitor_i        : std_logic_vector(7 downto 0);
-    signal  gtx0_txdlyalignreset_i          : std_logic;
-    signal  gtx0_txenpmaphasealign_i        : std_logic;
-    signal  gtx0_txpmasetphase_i            : std_logic;
-    ----------------------- Transmit Ports - TX PLL Ports ----------------------
-    signal  gtx0_gtxtxreset_i               : std_logic;
-    signal  gtx0_txresetdone_i              : std_logic;
-
-
-
-
-    signal  gtx0_tx_system_reset_c          : std_logic;
-    signal  gtx0_rx_system_reset_c          : std_logic;
-    signal  gtx0_double_reset_clk_i         : std_logic;
-    signal  tied_to_ground_i                : std_logic;
-    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
-    signal  tied_to_vcc_i                   : std_logic;
-    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
-    signal  drp_clk_in_i                    : std_logic;
- 
-
-    ----------------------------- User Clocks ---------------------------------
-
-    signal  gtx0_txusrclk2_i                : std_logic;
-    signal  gtx0_rxusrclk2_i                : std_logic;
-    signal  txoutclk_mmcm0_locked_i         : std_logic;
-    signal  txoutclk_mmcm0_reset_i          : std_logic;
-    signal  gtx0_txoutclk_to_mmcm_i         : std_logic;
-
-
-    ----------------------------- Reference Clocks ----------------------------
-    
-    signal    q3_clk0_refclk_i                : std_logic;
-    signal    q3_clk0_refclk_i_bufg           : std_logic;
-
-    ----------------------- Frame check/gen Module Signals --------------------
-    
-    signal    gtx0_matchn_i                   : std_logic;
-    
-    signal    gtx0_txcharisk_float_i          : std_logic_vector(2 downto 0);
-    
-    signal    gtx0_txdata_float_i             : std_logic_vector(31 downto 0);
-    
-    signal    gtx0_track_data_i               : std_logic;
-    signal    gtx0_block_sync_i               : std_logic;
-    signal    gtx0_error_count_i              : std_logic_vector(7 downto 0);
-    signal    gtx0_frame_check_reset_i        : std_logic;
-    signal    gtx0_inc_in_i                   : std_logic;
-    signal    gtx0_inc_out_i                  : std_logic;
-    signal    gtx0_unscrambled_data_i         : std_logic_vector(7 downto 0);
-
-    signal    reset_on_data_error_i           : std_logic;
-    signal    track_data_out_i                : std_logic;
- 
-    
-    ------------------------- Sync Module Signals -----------------------------
-
-    signal    gtx0_rx_sync_done_i             : std_logic;
-    signal    gtx0_reset_rxsync_c             : std_logic;
-
-
-    signal    gtx0_tx_sync_done_i             : std_logic;
-    signal    gtx0_reset_txsync_c             : std_logic;
-
-    ----------------------- Chipscope Signals ---------------------------------
-
-    signal  tx_data_vio_control_i           : std_logic_vector(35 downto 0);
-    signal  rx_data_vio_control_i           : std_logic_vector(35 downto 0);
-    signal  shared_vio_control_i            : std_logic_vector(35 downto 0);
-    signal  ila_control_i                   : std_logic_vector(35 downto 0);
-    signal  tx_data_vio_async_in_i          : std_logic_vector(31 downto 0);
-    signal  tx_data_vio_sync_in_i           : std_logic_vector(31 downto 0);
-    signal  tx_data_vio_async_out_i         : std_logic_vector(31 downto 0);
-    signal  tx_data_vio_sync_out_i          : std_logic_vector(31 downto 0);
-    signal  rx_data_vio_async_in_i          : std_logic_vector(31 downto 0);
-    signal  rx_data_vio_sync_in_i           : std_logic_vector(31 downto 0);
-    signal  rx_data_vio_async_out_i         : std_logic_vector(31 downto 0);
-    signal  rx_data_vio_sync_out_i          : std_logic_vector(31 downto 0);
-    signal  shared_vio_in_i                 : std_logic_vector(31 downto 0);
-    signal  shared_vio_out_i                : std_logic_vector(31 downto 0);
-    signal  ila_in_i                        : std_logic_vector(84 downto 0);
-
-    signal  gtx0_tx_data_vio_async_in_i     : std_logic_vector(31 downto 0);
-    signal  gtx0_tx_data_vio_sync_in_i      : std_logic_vector(31 downto 0);
-    signal  gtx0_tx_data_vio_async_out_i    : std_logic_vector(31 downto 0);
-    signal  gtx0_tx_data_vio_sync_out_i     : std_logic_vector(31 downto 0);
-    signal  gtx0_rx_data_vio_async_in_i     : std_logic_vector(31 downto 0);
-    signal  gtx0_rx_data_vio_sync_in_i      : std_logic_vector(31 downto 0);
-    signal  gtx0_rx_data_vio_async_out_i    : std_logic_vector(31 downto 0);
-    signal  gtx0_rx_data_vio_sync_out_i     : std_logic_vector(31 downto 0);
-    signal  gtx0_ila_in_i                   : std_logic_vector(84 downto 0);
-
-
-    signal    gtxtxreset_i                    : std_logic;
-    signal    gtxrxreset_i                    : std_logic;
-
-    signal    user_tx_reset_i                 : std_logic;
-    signal    user_rx_reset_i                 : std_logic;
-    signal    tx_vio_clk_i                    : std_logic;
-    signal    tx_vio_clk_mux_out_i            : std_logic;
-    signal    rx_vio_ila_clk_i                : std_logic;
-    signal    rx_vio_ila_clk_mux_out_i        : std_logic;
-
-    
---**************************** Main Body of Code *******************************
-begin
-
-    --  Static signal Assigments
-    tied_to_ground_i                             <= '0';
-    tied_to_ground_vec_i                         <= x"0000000000000000";
-    tied_to_vcc_i                                <= '1';
-    tied_to_vcc_vec_i                            <= x"ff";
-
-
-
-    
-  
-
-    -----------------------Dedicated GTX Reference Clock Inputs ---------------
-    -- The dedicated reference clock inputs you selected in the GUI are implemented using
-    -- IBUFDS_GTXE1 instances.
-    --
-    -- In the UCF file for this example design, you will see that each of
-    -- these IBUFDS_GTXE1 instances has been LOCed to a particular set of pins. By LOCing to these
-    -- locations, we tell the tools to use the dedicated input buffers to the GTX reference
-    -- clock network, rather than general purpose IOs. To select other pins, consult the 
-    -- Implementation chapter of UG___, or rerun the wizard.
-    --
-    -- This network is the highest performace (lowest jitter) option for providing clocks
-    -- to the GTX transceivers.
-    
-    q3_clk0_refclk_ibufds_i : IBUFDS_GTXE1
-    port map
-    (
-        O                               =>      q3_clk0_refclk_i,
-        ODIV2                           =>      open,
-        CEB                             =>      tied_to_ground_i,
-        I                               =>      Q3_CLK0_MGTREFCLK_PAD_P_IN,
-        IB                              =>      Q3_CLK0_MGTREFCLK_PAD_N_IN
-    );
-
- 
-
-   q3_clk0_refclk_bufg_i : BUFG
-    port map
-    (
-        I                               =>      q3_clk0_refclk_i,
-        O                               =>      q3_clk0_refclk_i_bufg
-    );
-
-    -----------------------Clock Input to Double Reset Module------------------
-     gtx0_double_reset_clk_i <= q3_clk0_refclk_i_bufg;
-
-
-    ----------------------------------- User Clocks ---------------------------
-    
-    -- The clock resources in this section were added based on userclk source selections on
-    -- the Latency, Buffering, and Clocking page of the GUI. A few notes about user clocks:
-    -- * The userclk and userclk2 for each GTX datapath (TX and RX) must be phase aligned to 
-    --   avoid data errors in the fabric interface whenever the datapath is wider than 10 bits
-    -- * To minimize clock resources, you can share clocks between GTXs. GTXs using the same frequency
-    --   or multiples of the same frequency can be accomadated using MMCMs. Use caution when
-    --   using RXRECCLK as a clock source, however - these clocks can typically only be shared if all
-    --   the channels using the clock are receiving data from TX channels that share a reference clock 
-    --   source with each other.
-
-    txoutclk_mmcm0_reset_i                       <= not gtx0_rxplllkdet_i;
-    txoutclk_mmcm0_i : MGT_USRCLK_SOURCE_MMCM
-    generic map
-    (
-        MULT                            =>      15.0,
-        DIVIDE                          =>      1,
-        CLK_PERIOD                      =>      12.5,
-        OUT0_DIVIDE                     =>      6.0,
-        OUT1_DIVIDE                     =>      1,
-        OUT2_DIVIDE                     =>      1,
-        OUT3_DIVIDE                     =>      1
-    )
-    port map
-    (
-        CLKFBOUT                        =>      open,
-        CLK0_OUT                        =>      gtx0_txusrclk2_i,
-        CLK1_OUT                        =>      open,
-        CLK2_OUT                        =>      open,
-        CLK3_OUT                        =>      open,
-        CLK_IN                          =>      gtx0_txoutclk_i,
-        MMCM_LOCKED_OUT                 =>      txoutclk_mmcm0_locked_i,
-        MMCM_RESET_IN                   =>      txoutclk_mmcm0_reset_i
-    );
-
-
-    rxrecclk_bufr1_i : BUFR
-    generic map
-    (
-        BUFR_DIVIDE                     =>      "BYPASS"
-    )
-    port map
-    (
-        CE                              =>      '1',
-        CLR                             =>      '0',
-        I                               =>      gtx0_rxrecclk_i,
-        O                               =>      gtx0_rxusrclk2_i
-    );
-
-
-
-
-    ----------------------------- The GTX Wrapper -----------------------------
-    
-    -- Use the instantiation template in the example directory to add the GTX wrapper to your design.
-    -- In this example, the wrapper is wired up for basic operation with a frame generator and frame 
-    -- checker. The GTXs will reset, then attempt to align and transmit data. If channel bonding is 
-    -- enabled, bonding should occur after alignment.
-
-
-    gtxVirtex6FEE80_i : gtxVirtex6FEE80
-    generic map
-    (
-        WRAPPER_SIM_GTXRESET_SPEEDUP    =>      EXAMPLE_SIM_GTXRESET_SPEEDUP
-    )
-    port map
-    (
-  
- 
- 
- 
-
-        --_____________________________________________________________________
-        --_____________________________________________________________________
-        --GTX0  (X0Y12)
-        GTX0_DOUBLE_RESET_CLK_IN        =>      gtx0_double_reset_clk_i,
-        ----------------------- Receive Ports - 8b10b Decoder ----------------------
-        GTX0_RXCHARISK_OUT              =>      gtx0_rxcharisk_i,
-        GTX0_RXDISPERR_OUT              =>      gtx0_rxdisperr_i,
-        GTX0_RXNOTINTABLE_OUT           =>      gtx0_rxnotintable_i,
-        --------------- Receive Ports - Comma Detection and Alignment --------------
-        GTX0_RXENMCOMMAALIGN_IN         =>      gtx0_rxenmcommaalign_i,
-        GTX0_RXENPCOMMAALIGN_IN         =>      gtx0_rxenpcommaalign_i,
-        ------------------- Receive Ports - RX Data Path interface -----------------
-        GTX0_RXDATA_OUT                 =>      gtx0_rxdata_i,
-        GTX0_RXRECCLK_OUT               =>      gtx0_rxrecclk_i,
-        GTX0_RXRESET_IN                 =>      gtx0_rxreset_i,
-        GTX0_RXUSRCLK2_IN               =>      gtx0_rxusrclk2_i,
-        ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
-        GTX0_RXCDRRESET_IN              =>      gtx0_rxcdrreset_i,
-        GTX0_RXN_IN                     =>      RXN_IN,
-        GTX0_RXP_IN                     =>      RXP_IN,
-        -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
-        GTX0_RXDLYALIGNDISABLE_IN       =>      gtx0_rxdlyaligndisable_i,
-        GTX0_RXDLYALIGNMONENB_IN        =>      gtx0_rxdlyalignmonenb_i,
-        GTX0_RXDLYALIGNMONITOR_OUT      =>      gtx0_rxdlyalignmonitor_i,
-        GTX0_RXDLYALIGNOVERRIDE_IN      =>      gtx0_rxdlyalignoverride_i,
-        GTX0_RXDLYALIGNRESET_IN         =>      gtx0_rxdlyalignreset_i,
-        GTX0_RXENPMAPHASEALIGN_IN       =>      gtx0_rxenpmaphasealign_i,
-        GTX0_RXPMASETPHASE_IN           =>      gtx0_rxpmasetphase_i,
-        GTX0_RXSTATUS_OUT               =>      gtx0_rxstatus_i,
-        --------------- Receive Ports - RX Loss-of-sync State Machine --------------
-        GTX0_RXLOSSOFSYNC_OUT           =>      gtx0_rxlossofsync_i,
-        ------------------------ Receive Ports - RX PLL Ports ----------------------
-        GTX0_GTXRXRESET_IN              =>      gtx0_gtxrxreset_i,
-        GTX0_MGTREFCLKRX_IN             =>      q3_clk0_refclk_i,
-        GTX0_PLLRXRESET_IN              =>      gtx0_pllrxreset_i,
-        GTX0_RXPLLLKDET_OUT             =>      gtx0_rxplllkdet_i,
-        GTX0_RXRESETDONE_OUT            =>      gtx0_rxresetdone_i,
-        -------------- Receive Ports - RX Pipe Control for PCI Express -------------
-        GTX0_PHYSTATUS_OUT              =>      gtx0_phystatus_i,
-        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
-        GTX0_TXCHARISK_IN               =>      gtx0_txcharisk_i,
-        ------------------ Transmit Ports - TX Data Path interface -----------------
-        GTX0_TXDATA_IN                  =>      gtx0_txdata_i,
-        GTX0_TXOUTCLK_OUT               =>      gtx0_txoutclk_i,
-        GTX0_TXRESET_IN                 =>      gtx0_txreset_i,
-        GTX0_TXUSRCLK2_IN               =>      gtx0_txusrclk2_i,
-        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
-        GTX0_TXN_OUT                    =>      TXN_OUT,
-        GTX0_TXP_OUT                    =>      TXP_OUT,
-        -------- Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
-        GTX0_TXDLYALIGNDISABLE_IN       =>      gtx0_txdlyaligndisable_i,
-        GTX0_TXDLYALIGNMONENB_IN        =>      gtx0_txdlyalignmonenb_i,
-        GTX0_TXDLYALIGNMONITOR_OUT      =>      gtx0_txdlyalignmonitor_i,
-        GTX0_TXDLYALIGNRESET_IN         =>      gtx0_txdlyalignreset_i,
-        GTX0_TXENPMAPHASEALIGN_IN       =>      gtx0_txenpmaphasealign_i,
-        GTX0_TXPMASETPHASE_IN           =>      gtx0_txpmasetphase_i,
-        ----------------------- Transmit Ports - TX PLL Ports ----------------------
-        GTX0_GTXTXRESET_IN              =>      gtx0_gtxtxreset_i,
-        GTX0_TXRESETDONE_OUT            =>      gtx0_txresetdone_i
-
-
-    );
-
-    -- Hold the TX in reset till the TX user clocks are stable
-    gtx0_txreset_i <= not txoutclk_mmcm0_locked_i;
-
-    -- Hold the RX in reset till the RX user clocks are stable
-  
-    gtx0_rxreset_i <= not gtx0_rxplllkdet_i;
-
-
-
-    ------------------------------ TXSYNC module ------------------------------
-    -- The TXSYNC module performs phase synchronization for all the active TX datapaths. It
-    -- waits for the user clocks to be stable, then drives the phase align signals on each
-    -- GTX. When phase synchronization is complete, it asserts SYNC_DONE
-    
-    -- Include the TX_SYNC module in your own design to perform phase synchronization if
-    -- your protocol bypasses the TX Buffers
-
-  
-    
-    gtx0_reset_txsync_c  <=  not gtx0_txresetdone_r2;  
-
-    -- SIM_TXPMASETPHASE_SPEEDUP is a simulation only attribute and MUST be set to 0 
-    -- during implementation      
-    gtx0_txsync_i : gtxVirtex6FEE80_tx_sync
-    generic map
-    (
-        SIM_TXPMASETPHASE_SPEEDUP       =>      EXAMPLE_SIM_GTXRESET_SPEEDUP
-    )
-    port map
-    (
-        TXENPMAPHASEALIGN               =>      gtx0_txenpmaphasealign_i,
-        TXPMASETPHASE                   =>      gtx0_txpmasetphase_i,
-        TXDLYALIGNDISABLE               =>      gtx0_txdlyaligndisable_i,
-        TXDLYALIGNRESET                 =>      gtx0_txdlyalignreset_i,
-        SYNC_DONE                       =>      gtx0_tx_sync_done_i,
-        USER_CLK                        =>      gtx0_txusrclk2_i,
-        RESET                           =>      gtx0_reset_txsync_c
-    );
-
-    ---------------------------- RXSYNC modules -------------------------------
-    -- The RXSYNC module performs phase synchronization for all the active RX datapaths. It
-    -- waits for the user clocks to be stable, then drives the RX phase align signals on each
-    -- GTX. When phase synchronization is complete, it asserts SYNC_DONE
-    
-    -- Include one RX_SYNC module per Buffer bypassed RX datapath in your own design. RX_SYNC modules
-    -- can also be shared, but when sharing, make sure to hold the module in reset until all lanes have 
-    -- a stable clock
-    
-  
-    gtx0_rxsync_i : gtxVirtex6FEE80_rx_sync
-    port map
-    (
-        RXENPMAPHASEALIGN               =>      gtx0_rxenpmaphasealign_i,
-        RXPMASETPHASE                   =>      gtx0_rxpmasetphase_i,
-        RXDLYALIGNDISABLE               =>      gtx0_rxdlyaligndisable_i,
-        RXDLYALIGNOVERRIDE              =>      gtx0_rxdlyalignoverride_i,
-        RXDLYALIGNRESET                 =>      gtx0_rxdlyalignreset_i,
-        SYNC_DONE                       =>      gtx0_rx_sync_done_i,
-        USER_CLK                        =>      gtx0_rxusrclk2_i,
-        RESET                           =>      gtx0_reset_rxsync_c
-    );
-    
-    gtx0_reset_rxsync_c       <= '1' when (gtx0_rxresetdone_r3 = '0') else '0';
-    
-
-
-    -------------------------- User Module Resets -----------------------------
-    -- All the User Modules i.e. FRAME_GEN, FRAME_CHECK and the sync modules
-    -- are held in reset till the RESETDONE goes high. 
-    -- The RESETDONE is registered a couple of times on USRCLK2 and connected 
-    -- to the reset of the modules
-    
-    process( gtx0_rxusrclk2_i)
-    begin
-         if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then
-            gtx0_rxresetdone_i_r  <= gtx0_rxresetdone_i   after DLY;
-         end if; 
-    end process; 
-
-    process( gtx0_rxusrclk2_i,gtx0_rxresetdone_i_r)
-    begin
-        if(gtx0_rxresetdone_i_r = '0') then
-            gtx0_rxresetdone_r    <= '0'   after DLY;
-            gtx0_rxresetdone_r2   <= '0'   after DLY;
-        elsif(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then
-            gtx0_rxresetdone_r    <= gtx0_rxresetdone_i_r after DLY;
-            gtx0_rxresetdone_r2   <= gtx0_rxresetdone_r   after DLY;
-        end if;
-    end process;
-
-    process( gtx0_rxusrclk2_i)
-    begin
-         if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i = '1') then
-            gtx0_rxresetdone_r3  <= gtx0_rxresetdone_r2   after DLY;
-         end if; 
-    end process; 
-
-    process( gtx0_txusrclk2_i,gtx0_txresetdone_i)
-    begin
-        if(gtx0_txresetdone_i = '0') then
-            gtx0_txresetdone_r  <= '0'   after DLY;
-            gtx0_txresetdone_r2 <= '0'   after DLY;
-        elsif(gtx0_txusrclk2_i'event and gtx0_txusrclk2_i = '1') then
-            gtx0_txresetdone_r  <= gtx0_txresetdone_i   after DLY;
-            gtx0_txresetdone_r2 <= gtx0_txresetdone_r   after DLY;
-        end if;
-    end process;
-
-
-    ------------------------------ Frame Generators ---------------------------
-    -- The example design uses Block RAM based frame generators to provide test
-    -- data to the GTXs for transmission. By default the frame generators are 
-    -- loaded with an incrementing data sequence that includes commas/alignment
-    -- characters for alignment. If your protocol uses channel bonding, the 
-    -- frame generator will also be preloaded with a channel bonding sequence.
-    
-    -- You can modify the data transmitted by changing the INIT values of the frame
-    -- generator in this file. Pay careful attention to bit order and the spacing
-    -- of your control and alignment characters.
-
-    gtx0_frame_gen : FRAME_GEN
-    generic map
-    (
-        WORDS_IN_BRAM                   =>      EXAMPLE_WORDS_IN_BRAM,
-        MEM_00                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_01                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_02                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_03                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_04                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_05                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_06                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_07                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_08                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_09                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_0A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_0B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_0C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_0D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_0E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_0F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_10                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_11                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_12                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_13                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_14                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_15                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_16                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_17                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_18                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_19                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_1A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_1B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_1C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_1D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_1E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_1F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_20                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_21                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_22                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_23                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_24                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_25                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_26                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_27                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_28                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_29                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_2A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_2B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_2C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_2D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_2E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_2F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_30                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_31                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_32                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_33                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_34                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_35                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_36                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_37                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_38                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_39                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_3A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_3B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_3C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_3D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_3E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_3F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEMP_00                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_01                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_02                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_03                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_04                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_05                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_06                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_07                  =>  x"0000000000000000000000000000000000000000000000000000000000000000"
-    )
-    port map
-    (
-        -- User Interface
-        TX_DATA(39 downto 8)            =>      gtx0_txdata_float_i,
-        TX_DATA(7 downto 0)             =>      gtx0_txdata_i,
- 
-        TX_CHARISK(3 downto 1)          =>      gtx0_txcharisk_float_i,
-        TX_CHARISK(0)                   =>      gtx0_txcharisk_i,
-        -- System Interface
-        USER_CLK                        =>      gtx0_txusrclk2_i,
-        SYSTEM_RESET                    =>      gtx0_tx_system_reset_c
-    );
-    
-
-
-    ---------------------------------- Frame Checkers -------------------------
-    -- The example design uses Block RAM based frame checkers to verify incoming  
-    -- data. By default the frame generators are loaded with a data sequence that 
-    -- matches the outgoing sequence of the frame generators for the TX ports.
-    
-    -- You can modify the expected data sequence by changing the INIT values of the frame
-    -- checkers in this file. Pay careful attention to bit order and the spacing
-    -- of your control and alignment characters.
-    
-    -- When the frame checker receives data, it attempts to synchronise to the 
-    -- incoming pattern by looking for the first sequence in the pattern. Once it 
-    -- finds the first sequence, it increments through the sequence, and indicates an 
-    -- error whenever the next value received does not match the expected value.
-
-    gtx0_frame_check_reset_i                     <= reset_on_data_error_i when (EXAMPLE_CONFIG_INDEPENDENT_LANES=0) else gtx0_matchn_i;
-
-    -- gtx0_frame_check0 is always connected to the lane with the start of char
-    -- and this lane starts off the data checking on all the other lanes. The INC_IN port is tied off
-    gtx0_inc_in_i                                <= '0';
-
-    process(gtx0_rxusrclk2_i)
-    begin 
-       if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then
-         gtx0_rxdata_r <= gtx0_rxdata_i   after DLY;
-       end if;
-    end process;
-
-    process(gtx0_rxusrclk2_i)
-    begin 
-       if(gtx0_rxusrclk2_i'event and gtx0_rxusrclk2_i='1') then
-         gtx0_rxcharisk_r(0) <= gtx0_rxcharisk_i   after DLY;
-       end if;
-    end process;
- 
-
- 
- 
-    gtx0_frame_check : FRAME_CHECK
-    generic map
-    (
-        RX_DATA_WIDTH                   =>      8,
-        RXCTRL_WIDTH                    =>      1,
-        USE_COMMA                       =>      1,
-        WORDS_IN_BRAM                   =>      EXAMPLE_WORDS_IN_BRAM,
-        CONFIG_INDEPENDENT_LANES        =>      1,
-        START_OF_PACKET_CHAR            =>      x"02bc",
-        MEM_00                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_01                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_02                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_03                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_04                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_05                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_06                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_07                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_08                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_09                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_0A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_0B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_0C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_0D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_0E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_0F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_10                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_11                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_12                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_13                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_14                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_15                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_16                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_17                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_18                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_19                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_1A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_1B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_1C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_1D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_1E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_1F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_20                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_21                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_22                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_23                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_24                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_25                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_26                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_27                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_28                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_29                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_2A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_2B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_2C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_2D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_2E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_2F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEM_30                  =>  x"0000000600000005000000040000000300000002000000bc0000000100000000",
-        MEM_31                  =>  x"0000000e0000000d0000000c0000000b0000000a000000090000000800000007",
-        MEM_32                  =>  x"000000160000001500000014000000130000001200000011000000100000000f",
-        MEM_33                  =>  x"0000001e0000001d0000001c0000001b0000001a000000190000001800000017",
-        MEM_34                  =>  x"000000260000002500000024000000230000002200000021000000200000001f",
-        MEM_35                  =>  x"0000002e0000002d0000002c0000002b0000002a000000290000002800000027",
-        MEM_36                  =>  x"000000360000003500000034000000330000003200000031000000300000002f",
-        MEM_37                  =>  x"0000003e0000003d0000003c0000003b0000003a000000390000003800000037",
-        MEM_38                  =>  x"000000460000004500000044000000430000004200000041000000400000003f",
-        MEM_39                  =>  x"0000004e0000004d0000004c0000004b0000004a000000490000004800000047",
-        MEM_3A                  =>  x"000000560000005500000054000000530000005200000051000000500000004f",
-        MEM_3B                  =>  x"0000005e0000005d0000005c0000005b0000005a000000590000005800000057",
-        MEM_3C                  =>  x"000000660000006500000064000000630000006200000061000000600000005f",
-        MEM_3D                  =>  x"0000006e0000006d0000006c0000006b0000006a000000690000006800000067",
-        MEM_3E                  =>  x"000000760000007500000074000000730000007200000071000000700000006f",
-        MEM_3F                  =>  x"0000007e0000007d0000007c0000007b0000007a000000790000007800000077",
-        MEMP_00                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_01                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_02                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_03                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_04                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_05                  =>  x"0000000000000000000000000000000000000000000000000000000000000000",
-        MEMP_06                  =>  x"0000000000000000000000000000000000000000000000000000000000000100",
-        MEMP_07                  =>  x"0000000000000000000000000000000000000000000000000000000000000000"
-    )
-    port map
-    (
-        -- MGT Interface
-        RX_DATA                         =>      gtx0_rxdata_r,
-        RXCTRL_IN                       =>      gtx0_rxcharisk_r,
-        RX_ENMCOMMA_ALIGN               =>      gtx0_rxenmcommaalign_i,
-        RX_ENPCOMMA_ALIGN               =>      gtx0_rxenpcommaalign_i,
-        RX_ENCHAN_SYNC                  =>      open,
-        RX_CHANBOND_SEQ                 =>      tied_to_ground_i,
-        -- Control Interface
-        INC_IN                          =>      gtx0_inc_in_i,
-        INC_OUT                         =>      gtx0_inc_out_i,
-        PATTERN_MATCH_N                 =>      gtx0_matchn_i,
-        RESET_ON_ERROR                  =>      gtx0_frame_check_reset_i,
-        -- System Interface
-        USER_CLK                        =>      gtx0_rxusrclk2_i,
-        SYSTEM_RESET                    =>      gtx0_rx_system_reset_c,
-        ERROR_COUNT                     =>      gtx0_error_count_i,
-        TRACK_DATA                      =>      gtx0_track_data_i
-    );
-        
-
-
-    TRACK_DATA_OUT                               <= track_data_out_i;
-
-    track_data_out_i                             <= 
-                                gtx0_track_data_i ;
-
-
-
-    ----------------------------- Chipscope Connections -----------------------
-    -- When the example design is run in hardware, it uses chipscope to allow the
-    -- example design and GTX wrapper to be controlled and monitored. The 
-    -- EXAMPLE_USE_CHIPSCOPE parameter allows chipscope to be removed for simulation.
-    
-chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
-    
-    
-    -- Shared VIO for all transievers 
-    shared_vio_i : data_vio
-    port map
-    (
-        control                         =>      shared_vio_control_i,
-        clk                             =>      tied_to_ground_i,
-        async_in                        =>      shared_vio_in_i,
-        async_out                       =>      shared_vio_out_i,
-        sync_in                         =>      tied_to_ground_vec_i(31 downto 0),
-        sync_out                        =>      open
-    );
-    
-    -- ICON for all VIOs 
-    i_icon : icon
-    port map
-    (
-        control0                        =>      shared_vio_control_i,
-        control1                        =>      tx_data_vio_control_i,
-        control2                        =>      rx_data_vio_control_i,
-        control3                        =>      ila_control_i
-    );
-
-    
-    -- TX VIO 
-    tx_data_vio_i : data_vio
-    port map
-    (
-        control                         =>      tx_data_vio_control_i,
-        clk                             =>      gtx0_txusrclk2_i,
-        async_in                        =>      tx_data_vio_async_in_i,
-        async_out                       =>      tx_data_vio_async_out_i,
-        sync_in                         =>      tx_data_vio_sync_in_i,
-        sync_out                        =>      tx_data_vio_sync_out_i
-    );
-    
-    -- RX VIO 
-    rx_data_vio_i : data_vio
-    port map
-    (
-        control                         =>      rx_data_vio_control_i,
-        clk                             =>      gtx0_rxusrclk2_i,
-        async_in                        =>      rx_data_vio_async_in_i,
-        async_out                       =>      rx_data_vio_async_out_i,
-        sync_in                         =>      rx_data_vio_sync_in_i,
-        sync_out                        =>      rx_data_vio_sync_out_i
-    );
-    
-    -- RX ILA
-    ila_i : ila
-    port map
-    (
-        control                         =>      ila_control_i,
-        clk                             =>      gtx0_rxusrclk2_i,
-        trig0                           =>      ila_in_i
-    );
-
-
-
-    -- assign resets for frame_gen modules
-    gtx0_tx_system_reset_c                       <= not gtx0_tx_sync_done_i or user_tx_reset_i;
-    -- assign resets for frame_check modules
-    gtx0_rx_system_reset_c                       <= not gtx0_rx_sync_done_i or user_rx_reset_i;
-
-    gtx0_gtxtxreset_i                            <= gtxtxreset_i or gtxrxreset_i;
-    gtx0_gtxrxreset_i                            <= gtxtxreset_i or gtxrxreset_i;
-
-    -- Shared VIO Outputs
-    gtxtxreset_i                                 <= shared_vio_out_i(31);
-    gtxrxreset_i                                 <= shared_vio_out_i(30);
-    user_tx_reset_i                              <= shared_vio_out_i(29);
-    user_rx_reset_i                              <= shared_vio_out_i(28);
-
-    -- Shared VIO Inputs
-    shared_vio_in_i(31 downto 0)                 <= "00000000000000000000000000000000";
-
-    -- Chipscope connections on GTX 0
-    gtx0_tx_data_vio_async_in_i(31)              <= '0';
-    gtx0_tx_data_vio_async_in_i(30)              <= gtx0_txresetdone_i;
-    gtx0_tx_data_vio_async_in_i(29 downto 22)    <= gtx0_txdlyalignmonitor_i;
-    gtx0_tx_data_vio_async_in_i(21 downto 0)     <= "0000000000000000000000";
-    gtx0_tx_data_vio_sync_in_i(31 downto 0)      <= "00000000000000000000000000000000";
-    gtx0_txdlyalignmonenb_i                      <= tx_data_vio_async_out_i(30);
-    gtx0_rx_data_vio_async_in_i(31)              <= gtx0_rxplllkdet_i;
-    gtx0_rx_data_vio_async_in_i(30)              <= gtx0_rxresetdone_i;
-    gtx0_rx_data_vio_async_in_i(29 downto 22)    <= gtx0_rxdlyalignmonitor_i;
-    gtx0_rx_data_vio_async_in_i(21 downto 0)     <= "0000000000000000000000";
-    gtx0_rx_data_vio_sync_in_i(31 downto 0)      <= "00000000000000000000000000000000";
-    gtx0_pllrxreset_i                            <= rx_data_vio_async_out_i(31);
-    gtx0_rxcdrreset_i                            <= rx_data_vio_async_out_i(30);
-    gtx0_ila_in_i(84)                            <= gtx0_rxcharisk_i;
-    gtx0_ila_in_i(83)                            <= gtx0_rxdisperr_i;
-    gtx0_ila_in_i(82)                            <= gtx0_rxnotintable_i;
-    gtx0_ila_in_i(81 downto 74)                  <= gtx0_rxdata_i;
-    gtx0_ila_in_i(73 downto 71)                  <= gtx0_rxstatus_i;
-    gtx0_ila_in_i(70 downto 69)                  <= gtx0_rxlossofsync_i;
-    gtx0_ila_in_i(68)                            <= gtx0_phystatus_i;
-    gtx0_ila_in_i(67 downto 60)                  <= gtx0_error_count_i;
-    gtx0_ila_in_i(59 downto 0)                   <= "000000000000000000000000000000000000000000000000000000000000";
-
-
-
-    tx_data_vio_async_in_i              <=      gtx0_tx_data_vio_async_in_i;
-
-
-    tx_data_vio_sync_in_i               <=      gtx0_tx_data_vio_sync_in_i;
-
-    rx_data_vio_async_in_i              <=      gtx0_rx_data_vio_async_in_i;
-
-
-    rx_data_vio_sync_in_i               <=      gtx0_rx_data_vio_sync_in_i;
-
-
-    ila_in_i                            <=      gtx0_ila_in_i;
-
-
-end generate chipscope;
-
-
-no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
-
-    -- If Chipscope is not being used, drive GTX reset signal
-    -- from the top level ports
-    gtx0_gtxtxreset_i                            <= GTXTXRESET_IN;
-    gtx0_gtxrxreset_i                            <= GTXRXRESET_IN;
-
-    -- assign resets for frame_gen modules
-    gtx0_tx_system_reset_c                       <= not gtx0_tx_sync_done_i;
-    -- assign resets for frame_check modules
-    gtx0_rx_system_reset_c                       <= not gtx0_rx_sync_done_i;
-
-    gtxtxreset_i                                 <= tied_to_ground_i;
-    gtxrxreset_i                                 <= tied_to_ground_i;
-    user_tx_reset_i                              <= tied_to_ground_i;
-    user_rx_reset_i                              <= tied_to_ground_i;
-    gtx0_txdlyalignmonenb_i                      <= tied_to_ground_i;
-    gtx0_pllrxreset_i                            <= tied_to_ground_i;
-    gtx0_rxcdrreset_i                            <= tied_to_ground_i;
-
-
-
-end generate no_chipscope;
-
-
-end RTL;
-
-
diff --git a/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_tx_sync.vhd b/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_tx_sync.vhd
deleted file mode 100644
index aa5cab4..0000000
--- a/FEE_ADC32board/project/ipcore_dir/gtxvirtex6fee80_tx_sync.vhd
+++ /dev/null
@@ -1,226 +0,0 @@
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor: Xilinx
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard
---  /   /         Filename : gtxvirtex6fee80_tx_sync.vhd
--- /___/   /\     
--- \   \  /  \ 
---  \___\/\___\
---
---
--- Module gtxvirtex6fee80_tx_sync
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
-entity gtxvirtex6fee80_tx_sync is
-generic
-(
-    SIM_TXPMASETPHASE_SPEEDUP   : integer:=0
-); 
-port
-(
-    TXENPMAPHASEALIGN    :   out    std_logic;
-    TXPMASETPHASE        :   out    std_logic;
-    TXDLYALIGNDISABLE    :   out    std_logic;
-    TXDLYALIGNRESET      :   out    std_logic;
-    SYNC_DONE            :   out    std_logic;
-    USER_CLK             :   in     std_logic;
-    RESET                :   in     std_logic
-);
-
-
-end gtxvirtex6fee80_tx_sync;
-
-architecture RTL of gtxvirtex6fee80_tx_sync is
---***********************************Parameter Declarations********************
-
-    constant DLY : time := 1 ns;
-
---*******************************Register Declarations************************
-
-    signal  begin_r                         :   std_logic;
-    signal  phase_align_r                   :   std_logic;
-    signal  ready_r                         :   std_logic;
-    signal  sync_counter_r                  :   unsigned(15 downto 0);
-    signal  wait_before_setphase_counter_r  :   unsigned(5 downto 0);
-    signal  align_reset_counter_r           :   unsigned(4 downto 0);
-    signal  wait_before_setphase_r          :   std_logic;
-    signal  align_reset_r                   :   std_logic;
-    
---*******************************Wire Declarations****************************
-    
-    signal   count_setphase_complete_r      :   std_logic;
-    signal   count_32_complete_r            :   std_logic;
-    signal   count_align_reset_complete_r   :   std_logic;
-    signal   next_phase_align_c             :   std_logic;
-    signal   next_ready_c                   :   std_logic;
-    signal   next_wait_before_setphase_c    :   std_logic;
-    signal   next_align_reset_c             :   std_logic;
-
-begin
---*******************************Main Body of Code****************************
-
-    --________________________________ State machine __________________________    
-    -- This state machine manages the TX phase alignment procedure of the GTX.
-    -- The module is held in reset till TXRESETDONE is asserted. Once TXRESETDONE 
-    -- is asserted, the state machine goes into the align_reset_r state, asserting
-    -- TXDLYALIGNRESET for 20 TXUSRCLK2 cycles. After this, it goes into the 
-    -- wait_before_setphase_r state for 32 cycles. After asserting TXENPMAPHASEALIGN and 
-    -- waiting 32 cycles, it goes into the phase_align_r state where the last 
-    -- part of the alignment procedure is completed. This involves asserting 
-    -- TXPMASETPHASE for 8192 (TXPLL_DIVSEL_OUT=1), 16384 (TXPLL_DIVSEL_OUT=2), 
-    -- or 32768 (TXPLL_DIVSEL_OUT=4) clock cycles. After completion of the phase 
-    -- alignment procedure, TXDLYALIGNDISABLE is deasserted.
-    
-    -- State registers
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if(RESET='1') then
-                begin_r                    <=  '1' after DLY;
-                align_reset_r              <=  '0' after DLY;
-                wait_before_setphase_r     <=  '0' after DLY;
-                phase_align_r              <=  '0' after DLY;
-                ready_r                    <=  '0' after DLY;
-            else
-                begin_r                    <=  '0' after DLY;
-                align_reset_r              <=  next_align_reset_c after DLY;
-                wait_before_setphase_r     <=  next_wait_before_setphase_c after DLY;
-                phase_align_r              <=  next_phase_align_c after DLY;
-                ready_r                    <=  next_ready_c after DLY;
-            end if;
-        end if;
-    end process;
-
-    -- Next state logic
-    next_align_reset_c              <=  begin_r or 
-                                        (align_reset_r and not count_align_reset_complete_r);
-    
-    next_wait_before_setphase_c     <=  (align_reset_r and count_align_reset_complete_r) or 
-                                        (wait_before_setphase_r and not count_32_complete_r);
-                                        
-    next_phase_align_c              <=  (wait_before_setphase_r and count_32_complete_r) or
-                                        (phase_align_r and not count_setphase_complete_r);
-                                        
-    next_ready_c                    <=  (phase_align_r and count_setphase_complete_r) or
-                                        ready_r;
-
-    --______ Counter for holding TXDLYALIGNRESET for 20 TXUSRCLK2 cycles ______
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (align_reset_r='0') then
-                align_reset_counter_r <= (others=>'0') after DLY;
-            else
-                align_reset_counter_r <= align_reset_counter_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-    
-    count_align_reset_complete_r <= align_reset_counter_r(4) 
-                                    and align_reset_counter_r(2);
-
-    --______ Counter for waiting 32 clock cycles before TXPMASETPHASE _________
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (wait_before_setphase_r='0') then
-                wait_before_setphase_counter_r <= (others=>'0') after DLY;
-            else
-                wait_before_setphase_counter_r <= wait_before_setphase_counter_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-    count_32_complete_r <= wait_before_setphase_counter_r(5);
-
-    --_______________ Counter for holding SYNC for SYNC_CYCLES ________________
-    process( USER_CLK )
-    begin
-        if(USER_CLK'event and USER_CLK = '1') then
-            if (phase_align_r='0') then
-                sync_counter_r <= (others=>'0') after DLY;
-            else
-                sync_counter_r <= sync_counter_r + 1 after DLY;
-            end if;
-        end if;
-    end process;
-
-fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=1) generate
-    -- 64 cycles of setphase for simulation
-    count_setphase_complete_r <= sync_counter_r(6);
-end generate fast_simulation;
-
-no_fast_simulation: if(SIM_TXPMASETPHASE_SPEEDUP=0) generate
-    -- 16384 cycles of setphase for output divider of 2
-    count_setphase_complete_r <= sync_counter_r(14);
-end generate no_fast_simulation;
-
-    --_______________ Assign the phase align ports into the GTX _______________
-
-    TXDLYALIGNRESET   <= '0';
-    TXENPMAPHASEALIGN <= (not begin_r) and (not align_reset_r);
-    TXPMASETPHASE     <= phase_align_r;
-    TXDLYALIGNDISABLE <= '1';
-
-    --_______________________ Assign the sync_done port _______________________
-    
-    SYNC_DONE <= ready_r;
-    
-    
-end RTL;
diff --git a/FEE_ADC32board/project/ipcore_dir/icon.ngc b/FEE_ADC32board/project/ipcore_dir/icon.ngc
deleted file mode 100644
index f18d9c0..0000000
--- a/FEE_ADC32board/project/ipcore_dir/icon.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
-$3:75=6:2.Yi{g|inl9$4(581*/=6>;;12351=7898?7=>?459345>339::<95?0327?5638=1;<5>;;13341=799;?7=<?09937577:9:?7=:?0593<56638>0==>?1:07?7678=19==>>7:15>LHH]]0HCCZ]OM2?70<768=0?;4FNNWW>FII\[EG=1=::1<23>512@DDYY4LOOVQKI4;;<0;2<94378JJJSS2JEEX_AC3=16>5863=>08=>?4:6555c<>fs;8zif6:7)77<0=13<=>>0::0<4>509:8<<>=0168F466l2HXOL@PVHPWA]033K_MK55MUR]JJCI63J=0OL^[USG1?FC6:2ICINEPLHAFJVCX\PZN>6MF3:AOV<=DGDGBXYKKb:ALJQTHD96;2n5LOOVQKI6;994h7NAATSMO49766j1HCCZ]OM2?578d3JEEX_AC0=30:f=DGG^YCA>315<`?FII\[EG<1?:>b9@KKRUGE:7=;0l;BMMPWIK85;<2n5LOOVQKI6;914h7NAATSMO497>6k1HCCZ]OM2?5;e<KFD_^BB?<32=g>EHF]XD@=2=1?a8GJHSZFF;0?<1c:ALJQTHD969?3m4CNLWVJJ74;>5o6M@NUPLH5:5=7i0OB@[RNN38709k2IDBY\@L1>13;e<KFD_^BB?<3:=g>EHF]XD@=2=9?`8GJHSZFF;0?0l;BMMPWIK859;2n5LOOVQKI6;;84h7NAATSMO49556j1HCCZ]OM2?768d3JEEX_AC0=17:`=DGG^YCA>33483:f=DGG^YCA>334<a?FII\[EG<1=1b:ALJQTHD96?2o5LOOVQKI6;=7h0OB@[RNN3838e3JEEX_AC0=5=f>EHF]XD@=27>c9@KKRUGE:753l4CNLWVJJ6494h7NAATSMO59776j1HCCZ]OM3?548d3JEEX_AC1=31:f=DGG^YCA?312<`?FII\[EG=1?;>b9@KKRUGE;7=80l;BMMPWIK95;=2n5LOOVQKI7;9>4h7NAATSMO597?6j1HCCZ]OM3?5<8e3JEEX_AC1=3=g>EHF]XD@<2=0?a8GJHSZFF:0??1c:ALJQTHD869>3m4CNLWVJJ64;95o6M@NUPLH4:5<7i0OB@[RNN28739k2IDBY\@L0>12;e<KFD_^BB><35=g>EHF]XD@<2=8?a8GJHSZFF:0?71b:ALJQTHD8692n5LOOVQKI7;;94h7NAATSMO59566j1HCCZ]OM3?778d3JEEX_AC1=10:f=DGG^YCA?335<f?FII\[EG=1=::1<`?FII\[EG=1=:>c9@KKRUGE;7?3l4CNLWVJJ64=4i7NAATSMO5939j2IDBY\@L0>5:g=DGG^YCA?37?`8GJHSZFF:050m;BMMPWIK9535n6M@NUPLH7:76j1HCCZ]OM0?558d3JEEX_AC2=32:f=DGG^YCA<313<`?FII\[EG>1?<>b9@KKRUGE87=90l;BMMPWIK:5;>2n5LOOVQKI4;9?4h7NAATSMO69706j1HCCZ]OM0?5=8d3JEEX_AC2=3::g=DGG^YCA<31?a8GJHSZFF90?>1c:ALJQTHD;69=3m4CNLWVJJ54;85o6M@NUPLH7:5;7i0OB@[RNN18729k2IDBY\@L3>11;e<KFD_^BB=<34=g>EHF]XD@?2=7?a8GJHSZFF90?61c:ALJQTHD;6953l4CNLWVJJ54;4h7NAATSMO69576j1HCCZ]OM0?748d3JEEX_AC2=11:f=DGG^YCA<332<`?FII\[EG>1=;>d9@KKRUGE87?84?>b9@KKRUGE87?80m;BMMPWIK:595n6M@NUPLH7:36k1HCCZ]OM0?1;d<KFD_^BB=<7<a?FII\[EG>191b:ALJQTHD;632o5LOOVQKI4;17h0OB@[RNN0858d3JEEX_AC3=33:f=DGG^YCA=310<`?FII\[EG?1?=>b9@KKRUGE97=>0l;BMMPWIK;5;?2n5LOOVQKI5;9<4h7NAATSMO79716j1HCCZ]OM1?528d3JEEX_AC3=3;:f=DGG^YCA=318<a?FII\[EG?1?1c:ALJQTHD:69<3m4CNLWVJJ44;;5o6M@NUPLH6:5:7i0OB@[RNN08759k2IDBY\@L2>10;e<KFD_^BB<<37=g>EHF]XD@>2=6?a8GJHSZFF80?91c:ALJQTHD:6943m4CNLWVJJ44;35n6M@NUPLH6:56j1HCCZ]OM1?758d3JEEX_AC3=12:f=DGG^YCA=333<`?FII\[EG?1=<>b9@KKRUGE97?90j;BMMPWIK;59>6=0l;BMMPWIK;59>2o5LOOVQKI5;;7h0OB@[RNN0818e3JEEX_AC3=7=f>EHF]XD@>29>c9@KKRUGE97;3l4CNLWVJJ4414i7NAATSMO79?99=1HC_KPGDLFVDRNGGUBBKA8;BPFEQCC92N97IGl;EKPEGJBWC^JK95KRBI6?CGK[L90JIM;;GF@A6=ALL90JI\;;GFQA4d<N[EF,/JPCMI!$QI'*CUH@F,/THE2f>@UGD*)FRMCK#"WK%$CWJF@.-ZFG358BWIJ(+_TOAE- UM#&OYDDB(+=8>?0/234567(yY9;6H]OL"!QZEKC+*_C-,Z_BNH&%7289:%<=>?01"sW4=@;2MEH;5GE@F\H4=N:2C;>6G>2:K16>O4:2C?>6G:9:KMMQUSI]O87D@Ya:HWEBYD@HCE96DPCMI1?IO53EE=7AANDDF4?II@AJKG86BZT068HPR5<2F^X9:4LTV60>JR\?=0AXVLY^N6?HS_N<?0AXVI649NQ]@0k2Gjfb|Yesqjkke<E`dd~[k}shmm6>H7<2D:98:4N0750>H61:>0B<7;4:L2=02<F;8386@=2868J757<2D9:>:4N3470>H5><>0B?774:L1=<2<F::;;6@JTVMQO3=IGJFB\:5AOLGQC@7<G81[86^NRU0e?UCUAFN+.GQLLJ #75678':;<=>? qQ#LLAO(<:%<=>?01"&e>VNFVH^_DJWb:RJJZDR[GKFI45_K^JOQQHJ92[:7_;4RDQFP2=U]G^N_Y?4S29PAI3<[ACMX;5\OTP@A6=SKB90XIG<;UFL<>RBZDCEMA=4THE;?QOJMZZNO>5[MR58PKKXFL^27Y]PD^VL[O><\ZUASNBD9:VP[OYSGVN27Y]PU^VL[O?<\ZU^SYAPU59W]UC4=2_;#XQFCNL,MZ_B[VHXOL@!U^@P+LYR[LUXCKZMSBCM[@W7&\UIYKI<d:W3+PYNKFD$ERWJS^@PGDH)]VHX#DQY6/KP]K(NW\YNS^AITCQ@EKYBY9$^SO]=6:W3+PYNKFD$ERWJS^@PGDH)]VHX#dJ]CJ]OKFGK:k1^<"[PIBMM+PYDEM%LSYO]GDVX55[)AVDN<#[PT@PDAQ4e3\:$YRGLOO-V[FKC'NU_M_IJTZ32Y+OXFL:%YRZNRFGW6g=R8&_TENAA/T]@IA)@W]KYKHZT13_-MZHB8'_TXL\HEU0a?P6(]VCHCC!Z_BOG+BYSI[MNXV?<]/K\J@6)]V^J^JK[2c9V4*SXAJEE#XQLME-D[QGUOL^P=9S!I^LF4+SX\HXLIY<m;T2,QZODGG%^SNCK/F]WEWAB\R;>Q#GPEP2-QZRFZNO_>l5Z0.W\MFII'\UHAI!H_UCQC@R\>T$BSCK?.T]WEWAB\;k0Y=!Z_HALJ*SXKDN$KRZNRFGW_2[)AVDN<#[PT@PDAQ4f3\:$YRGLOO-V[FKC'NU_M_IJTZ:^*LYIM9$^SYO]GDV1e>S7'\UBOB@ U^AN@*AX\HXLIYU6]/K\J@6)]V^J^JK[2b9V4*SXAJEE#XQLME-V[FIJEHDOS^KC/H6-BL]7U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^77U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^76U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^75U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^74U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^73U'_T@XZ=d:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^72U'_T@XZ=c:W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^7Z&\UGYY<l;T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_7[)]VF^X?m4U1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX7X(RWE__>n5Z0.W\MFII'\UHAI!Z_BMNIDHCWZOG#D:!FHY7Y+SXD\^9o6[?/T]JGJH(]VIFH"[PCNONEKBX[LF$E9 IIZ7^*PYK]]8h7X> U^K@KK)RWJGO#XQLOLOBJAYTME%B8#HF[7_-QZJR\;i0Y=!Z_HALJ*SXKDN$YRM@MLCM@ZUBD&C?"KGT7\,V[ISS:j1^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU7]/W\HPR5k2_;#XQFCNL,QZEJL&_TOBCBAOF\W@J(A=$MEV7R.T]OQQ4d3\:$YRGLOO-V[FKC'\UHC_KPIE]PAI)N<'LBW=S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP==S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=<S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=?S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=>S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=9S!U^NVP7b<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=8S!U^NVP7e<]9%^SDM@N.W\GHB(]VID^HQFD^QFH*O3&OCP=P Z_MWW6f=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q9Q#[PLTV1g>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR9V"XQCUU0`?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS=W%YRBZT3a8Q5)RW@IDB"[PCLF,QZEHZLUBHR]JL.K7*CO\=T$^SA[[2b9V4*SXAJEE#XQLME-V[FIUMVCOS^KC/H6-BL]1U'_T@XZ=c:W3+PYNKFD$YRMBD.W\GJTBW@NT_HB I5,EM^1Z&\UGYY<l;T2,QZODGG%^SNCK/T]@KWCXAMUXIA!F4/DJ_=[)]VF^X?m4U1-V[LEHF&_TO@J U^ALV@YNLVYN@"G;.GKX=X(RWE__=:5Z0.W\MFII'\UHAI!Z_RGO[k7e3\:$YRGLOO-V[FKC'\U_M_IJT^AF53=R8&_TENAA/T]@IA)n[LFTb<l4U1-V[LEHF&_TO@J iUCQC@R;994:n6[?/T]JGJH(]VIFH"g[ASEFP97668k0Y=!Z_HALJ*SXKDN$eYO]GDV?<;7f3\:$YRGLOO-V[FKC'`^J^JK[<8<2e>S7'\UBOB@ U^AN@*oSI[MNXRMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V>R.G]@IA]7U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^6Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_46Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_46Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_47Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_47Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_44Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_44Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_45Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_45Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_42Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_42Z&\UGOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_43Z&\UCOH<k;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_43Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_4[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX5X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY1Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ0^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\8T$MSNCK[2_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]7U'LTO@JT3\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^6Z&OUHAIU;]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV:R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX4X(AWJGOW8S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY3Y+@XKDNP9P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ2^*CYDEMQ=Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[1_-BZEJLR<V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T0\,E[FKCS>W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\?T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V>R.G]@IA]?U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^>Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_<[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX=X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR;V"KQLMEY3Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS8W%JRMBDZ2^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[02^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[02^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[03^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[03^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[00^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[00^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[01^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[01^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[06^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[06^*PYKKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[07^*PYOKL8o7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[07^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[0_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]6U'LTO@JT1\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU=]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_4[)NVIFHV<R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX5X(AWJGOW>S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY2Y+@XKDNP?P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ3^*CYDEMQ?Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[0_-BZEJLR>V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T1\,E[FKCS<W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U>]/D\GHB\=T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V?R.G]@IA]1U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W<S!F^AN@^0Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP=P I_BOG_2[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ:Q#HPCLFX3X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR;V"KQLMEY;Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS8W%JRMBDZ:^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[8_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]6U'LTO@JT9\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^4Z&OUHAIU?]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_7[)NVIFHV>R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<>R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<>R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<?R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<?R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<<R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<<R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<=R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<=R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<:R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<:R.T]OG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<;R.T]KG@4c3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<;R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY1Y+@XKDNP=P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ9Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[3_-BZEJLR8V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T2\,E[FKCS:W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U=]/D\GHB\;T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V<R.G]@IA]3U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W?S!F^AN@^2Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP>P I_BOG_0[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ9Q#HPCLFX1X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR8V"KQLMEY5Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS;W%JRMBDZ4^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\:T$MSNCK[6_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]5U'LTO@JT7\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^4Z&OUHAIU7]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_7[)NVIFHV6R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW4S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY1Y+@XKDNP5P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ1^*CYDEMQ;Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[2_-BZEJLR:V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8:V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8:V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8;V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8;V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS88V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS88V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS89V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS89V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8>V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8>V"XQCCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8?V"XQGCD0g?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8?V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U<]/D\GHB\9T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]5U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W>S!F^AN@^4Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP?P I_BOG_6[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ8Q#HPCLFX7X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR9V"KQLMEY7Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS:W%JRMBDZ6^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\;T$MSNCK[4_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]4U'LTO@JT5\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^5Z&OUHAIU9]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_6[)NVIFHV8R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX7X(AWJGOW:S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY0Y+@XKDNP;P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ1^*CYDEMQ3Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[2_-BZEJLR2V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS0W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U<]/D\GHB\1T$^SAMJ1d9V4*SXAJEE#XQLTSN\KPR(]VIFHJ\_00g8Q5)RW@IDB"[PCUPO[JSS'\UHAII]P002?P6(]VCHCC!Z_BVQHZIR\&_THLZN_WCOMA4?3\:$YRGLOO-V[FRUDVE^X"gLOLOBJAY@ZYUXIA2?>3:8Q5)RW@IDB"[PCUPO[JSS'`IDA@OAD^EQTZUBD5;5>=5Z0.W\MFII'\UHX_BPOTV,mAGSIV\J@DJ=1:W3+PYNKFD$YR][AU-E[VRF\R:V"XQ\T@V15>S7'\UBOB@ U^QWEQ)AWZ^JXV?R.T]PPDR592_;#XQFCNL,QZUSI]%MS^ZNTZ0^*PYT\H^9=6[?/T]JGJH(]VY_MY!I_RVBP^5Z&\UXXLZ>a:W3+PYNKFD$YR][AU-V[FKCO[Z;=i5Z0.W\MFII'\UXXLZ U^FBPDYQIECO=l5Z0.W\MFII'\UXXLZ U^QWEQEJL8i0Y=!Z_HALJ*SX[]K_#XQ\T@V@IAYi:81^<"[PIBMM+PYT\H^$YR][AU]@JQ)DA5;5><5Z0.W\MFII'\UXXLZ U^QWEQYDF]%HE1<1209V4*SXAJEE#XQ\T@V,QZUSI]UHBY!LI=1=64=R8&_TENAA/T]PPDR(]VY_MYQLNU-@M929:81^<"[PIBMM+PYT\H^$YR][AU]@JQ)DA5?5>=5Z0.W\MFII'\UXXLZ U^QWEQYDF]%O0=0=0:W3+PYNKFD$YR][AU-V[VRF\VIEX"J31?03?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/E>1:76<]9%^SDM@N.W\WQGS'\UXXLZPCOV,@959:91^<"[PIBMM+PYT\H^$YR][AU]@JQ)C4=49<6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&N793<l;T2,QZODGG%^S^ZNT.W\WQGSWJD_#JU?]/EmL+SXE\RHU?94U1-V[LEHF&_T_YO[/T]PPDRXKG^$KV>R.T]E@WC5>2_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\8T$^SA[[299V4*SXAJEE#XQ\T@V,QZUSI]UHBY!H[1_-QZ^HZJS9o6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&MP=P HnI,V[HS_KP8<7X> U^K@KK)RWZ^JX"[PSUCW[FHS'NQ:Q#[PFEPF63=R8&_TENAA/T]PPDR(]VY_MYQLNU-D_4[)]VF^X?64U1-V[LEHF&_T_YO[/T]PPDRXKG^$KV?R.T][KWE^:j1^<"[PIBMM+PYT\H^$YR][AU]@JQ)@S;W%KcF!U^OV\F_5?2_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\:T$^SKJ]E348Q5)RW@IDB"[PSUCW+PYT\H^TOCZ GZ0^*PYK]]837X> U^K@KK)RWZ^JX"[PSUCW[FHS'NQ9Q#[PXNP@]7e<]9%^SDM@N.W\WQGS'\UXXLZPCOV,C^5Z&NdC"XQBUYAZ62=R8&_TENAA/T]PPDR(]VY_MYQLNU-D_6[)]VLO^H<9;T2,QZODGG%^S^ZNT.W\WQGSWJD_#JU<]/W\HPR502_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\;T$^SUA]CX0`?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/FY7Y+Ai@'_TAXVLY358Q5)RW@IDB"[PSUCW+PYT\H^TOCZ GZ6^*PYAL[O9:6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&MP8P Z_MWW6==R8&_TENAA/T]PPDR(]VY_MYQLNU-D_1[)]VRD^NW=7:W3+PYNKFD$YR][AU-V[VRF\VIEX"IT5\,V[CBUM;<0Y=!Z_HALJ*SX[]K_#XQ\T@V\GKR(OR?V"XQCUU0;?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/FY6Y+SXPFXHU?>4U1-V[LEHF&_T_YO[/T]PPDRXKG^$_1>1219V4*SXAJEE#XQ\T@V,QZUSI]UHBY!\<0<14>S7'\UBOB@ U^QWEQ)RWZ^JXRMAT.Q?6;473\:$YRGLOO-V[VRF\&_T_YO[_BLW+V:46;:0Y=!Z_HALJ*SX[]K_#XQ\T@V\GKR([5>5>=5Z0.W\MFII'\UXXLZ U^QWEQYDF]%X080>c:W3+PYNKFD$YR][AU-V[VRF\VBBKE?m;T2,QZODGG%^S^ZNT.W\WQGSWEE\=;5Z0.W\MFII'\UXXLZ U^VGK4d<]9%^SDM@N.W\WQGS'\U_HBQaeyv2a>S7'\UBOB@ U^QWEQ)nKDNTK_^?_RGO5f=R8&_TENAA/T]PPDR(aMK_MRXNLHF2=>S7'\UBOB@ U^QWEQ)n[]K_0=0>9:W3+PYNKFD$YR][AU-jWQGS484:56[?/T]JGJH(]VY_MY!fSUCW878612_;#XQFCNL,QZUSI]%b_YO[<2<2g>S7'\UBOB@ U^QWEQ)n[]K_O@JPCD3f?P6(]VCHCC!Z_RVBP*oT\H^HAIQLE^l2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<1<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<0<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<3<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<2<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<5<2`>S7'\UBOB@ U^QWEQ)n[]K_SN@[<4<2f>S7'\UBOB@ U^QWEQ)n[]K_SEGHH0c8Q5)RW@IDB"[PSUCW+lUSI]UGCZ?n;T2,QZODGG%^S^ZNT.kW@JYimq~9n6[?/T]JGJH(]VYRBN!H_R[MGZQHZMQ;Q#GPND2-QZ@CZ;h0Y=!Z_HALJ*SX[PDH#JQ\YOA\SJTCS8W%ER@J0/W\BAT5j2_;#XQFCNL,QZU^FJ%LS^WAC^ULVA]5U'CTBH>!U^DGV7d<]9%^SDM@N.W\W\HD'NUXUCMPWNPG_6[)AVDN<#[PFEP1f>S7'\UBOB@ U^QZJF)@WZSEORY@REY7Y+OXFL:%YRHKR3`8Q5)RW@IDB"[PSXL@+BYTQGIT[B\K[4_-MZHB8'_TJI\=b:W3+PYNKFD$YR]VNB-D[V_IKV]D^IU9]/K\AT6)]VLO^<l4U1-V[LEHF&_T_T@L/T]DKQYTQGI:h6[?/T]JGJH(]VYRBN!Z_FMW[V_IKVB:h6[?/T]JGJH(]VYRBN!Z_FMW[V_IKVF:;6[?/T]JGJH(]VYRBN!Z_R[MG4c<]9%^SDM@N.W\W\HD'\UbHLZN_BOG[k7d3\:$YRGLOO-V[V_IK&cOMYOPCLF\j4g<]9%^SDM@N.W\W\HD'`MDXR]VNB3e?P6(]VCHCC!Z_R[MG*o@G]UXUCMPHHEK5`=R8&_TENAA/T]P]KE(aNE_S^WAC^NLS4c<]9%^SDM@N.W\W\HD'`YRBNQXOSF?4;7b3\:$YRGLOO-V[V_IK&cXUCMPWNPG8486m2_;#XQFCNL,QZU^FJ%b_T@L_VMQ@9499l1^<"[PIBMM+PYTQGI$e^WAC^ULVA:468o0Y=!Z_HALJ*SX[PDH#d]VNB]TKWB;<7;n7X> U^K@KK)RWZSEO"g\YOA\SJTC4<4:i6[?/T]JGJH(]VYRBN!fSXL@[RIUL5<5=>5Z0.W\MFII'\U_HDQ}ef0e?P6(]VCHCC!Z_UFL[HS_'\UH_RCZX.K7*PYJ]Q;=#@czx^M774=R8&_TENAA/T]W@JYJ]Q%^SN]PMTZ,M1(RWD_S=;!Bmtz\K1YA;81^<"[PIBMM+PYSLFUFYU!Z_BQ\IP^(A=$^S@[W17-Nip~XG=UL=>5Z0.W\MFII'\U_HBQ}ef36?P6(]VCHCC!Z_hFBPDYDEM;<7X> U^K@KK)RW`NJXLQLME]m57=R8&_TENAA/T]jW@JXf830Y=!Z_HALJ*oDGDGJBIQHRQ>3:4?<]9%^SDM@N.k@KHKFFMUL^]2>>0;8Q5)RW@IDB"gLOLOBJAYTME6;2<o4U1-V[LEHF&cHC@CNNE]PAI:687;j7X> U^K@KK)nKFGFMCJPSDN?5486i2_;#XQFCNL,mFIJEHDOS^KC<00=5d=R8&_TENAA/hALIHGILVYN@1?<>0c8Q5)RW@IDB"gLOLOBJAYTME6:83?n;T2,QZODGG%bOBCBAOF\W@J;9<4:56[?/T]JGJH(aJEFAL@K_RGO848612_;#XQFCNL,mFIJEHDOS^KC<3<2=>S7'\UBOB@ iBMNIDHCWZOG0>0>9:W3+PYNKFD$eNABM@LG[VCK4=4:56[?/T]JGJH(aJEFAL@K_RGO808612_;#XQFCNL,mFIJEHDOS^KC<7<2=>S7'\UBOB@ iBMNIDHCWZOG0:0>9:W3+PYNKFD$eNABM@LG[VCK414:56[?/T]JGJH(aJEFAL@K_RGO8<86=2_;#XQFCNL,mFIUMVCO0=0>5:W3+PYNKFD$eNA]E^KG8486=2_;#XQFCNL,mFIUMVCO0?0>5:W3+PYNKFD$eNA]E^KG868612_;#XQFCNL,mFIUMVCOS^KC<1<2e>S7'\UBOB@ iBMQAZOCWZOG0<;1189V4*SXAJEE#dM@RD]J@ZUBD5;5=45Z0.W\MFII'`ID^HQFD^QFH949901^<"[PIBMM+lEHZLUBHR]JL=1=56=R8&_TENAA/hFBPDYDEM;>7X> U^K@KK)nLH^JSNCK_og8Q5)RW@IDB"g\EM33?P6(]VCHCC!fSDN\jc=R8&_TENAA/hQZJFc<]9%^SDM@N.kW@Lc<]9%^SDM@N.kW@J713\:$YRGLOO-jPAIX^LI7=80>3:W3+PYNKFD$eYJ@_og{pa=R8&cXDDH[_NWWa>S7'`_[HLZJ_NWW2>SWLH^No6[\ES]UMVOEDL?0YRMCK29UGF?<^@O\SYW_E0f8\LJNFQ'SHO.?.0"PPPD'8';+M^MFI49[KWE^>2RXXAGM7:ZPPZAIL>1S_YQYCB`8\ZEHZLUBBKA9;Yfa[Lba3QncS]|fmWgqwlii991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc=4Xrv0f>YXWQFEARQP0^]\Q5)RW@IDB"[PCLF,QZEHEDKEHR]JL.K7*CO\98W%YRBZT2`8[ZY_DGGTSR??_^]V4*SXAJEE#XQLME-V[FIUMVCOS^KC/H6-BL]6U'_T@XZ<b:]\[]JIEVUT=<QP_T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_0[)]VF^X>o4_^][HKKXWV;TSR[?/T]JGJH(]VIFH"[PCNONEKBX[LF$E9 IIZ6^*PYK]]9j7RQPXMLN[ZY5WVU^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU8]/W\HPR4i2UTSUBAM^]\7ZYX]9%^SDM@N.W\GHB(]VIDA@OAD^QFH*O3&OCP5P Z_MWW6==XWVRGB@QP_5]\[P6(]VCHCC!Z_RVBP*SXKDNL^]>=b:]\[]JIEVUT9RQPU1-V[LEHF&_T_YO[/T]GEQGX^HFBH>o4_^][HKKXWV<TSR[?/T]JGJH(]VIFH"[PCNPF[LBX[LF$E9 IIZ1^*PYK]]9j7RQPXMLN[ZY0WVU^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU9]/W\HPR4i2UTSUBAM^]\<ZYX]9%^SDM@N.W\GHB(]VIDA@OAD^QFH*O3&OCP>P Z_MWW7d=XWVRGB@QP_8]\[P6(]VCHCC!Z_BOG+PYDGDGJBIQ\EM-J0+@NS9W%YRBZT208gmow{je{iRgloo]u5Z63Wh&+Tdbfny"@KWC'Oldn~lz`r!32*42<ajee>85fcnl/gmow{je{iRgloo]u5Z63Wh&ECCK#NNLF6c4<ajee nffpralt`YnkfdTz<Q?4^c/fYkfUge~z2NtoaawYDgg~ycaQ_osvp91=R{lUNtyQMsbcm9cgk{l1^h|PSbcm[Fnfag7^_H\>;DlbficXB}klSO{ig<vqq`=R{lU^bx}jd^@pgdh:nhfxi6[|e^Qlbqdtkhd6jlb|e-a\|acqajomm`gcy<tjvqc>%iTob|j_u{sa87+kVgjfb|Pvdppmjh:98&hS`gaos]uawungg7: nQmuhng[wcqazcdb0>#c^alv`YjiceyS{k}=0.`[fiumVgbbb|Pvdp>6)eXkfxnS`gaos]bhunfWoy149#c^oecZoc58&hSx}j_rkn95*dW|ynS~aitcq`ek;7$jU{mzPieal``Yumncxxh|20-a\qvcXb}klSo{ig<3/gZhreVidby|`l^rlvqu:<%iTy~kPcnlwvjj758&hSx}j_bmmpwik94;'oR{|e^aljqthd;7: nQzsd]`kkruge96=!mPurg\gjhszff?1="l_tqf[fii|{eg90>#c^wpaZehf}xd`;3?,b]vw`Ydgg~yca920-a\qvcXkfd~bb7=1.`[pubWjeexac9<2/gZstmVidby|`l02>4)eX}zoTob`{rnn2586+kVxiRm`nuplh44:8%iTy~kPcnlwvjj6;4:'oR{|e^aljqthd8>6<!mPurg\a}rXjzijb0>#c^wpaZsi}zooSo}lao?3(fYr{lxTnoa_bjbmk;6$t;:7dm`n^VJI@UWMJUEOK?>;haljZRNELY[INQWSU:8jbee}`foqMN7`c8DE~5?l0M694>{Ra2>7172m81=><7d7396f1cnrd9:h4>;o05b?3<,;<h6?89;|Q1f?4083n96<==8e42>7e0m;1Xi=4=8282>4550m<:6?m8ec9P6g<50:0:6<==8e42>7e?9l1o>:k50;395~Ud938<<7j=:011<a062;i<hk5yT02g>5<6280m<v]l1;044?b528994i8>:3a4`c=#:??1i<5Y27f96~sbj3;0yhm50:'557=9m1i>:k50;;3>`e=n9qC>;<4$03a>71b3S8?69u>6;34>4>=900v(?8m:35g?!4?2;=m7)m?:3:3?.2f290/==:5499m555=:910';h50;&241<1l2d:<>4=0:9(=1<72-;;877=;o337?4732!i57>5$027>g1<f8:86?>4;*6:>5<#99>1855a11194>=,<>0;6)??4;6;?k77;3;07&:9:18'552=<11e===52:9(00<72-;;87:7;o337?5<3">?6=4+11690==i9991865$4283>!77<3>37c??3;78?.26290/==:5499m555=>21 8=4?:%330?2?3g;;?794;*1e>5<#99>1855a1119<>=,;l0;6)??4;6;?k77;3307&=k:18'552=<11e===5a:9(7f<72-;;87:7;o337?d<3"9i6=4+11690==i9991o65$3`83>!77<3>37c??3;f8?.5>290/==:5499m555=m21 ?54?:%330?2?3g;;?7h4;*15>5<#99>1855a111955=<#:?1<7*>0587<>h68:0:=65$3583>!77<3>37c??3;31?>-4;3:1(<>;:5:8j46428907&==:18'552=<11e===51598/67=83.:<94;8:l246<6=21 ?=4?:%330?2?3g;;?7?9;:)1b?6=,8:?6964n020>41<3"8n6=4+11690==i9991=554+3f94?"68=0?46`>0282=>=,=90;6)??4;6;?k77;3;j76%;f;29 4632=20b<><:0`8?.2b290/==:5499m555=9j10'9j50;&241<302d:<>4>d:9(0f<72-;;87:7;o337?7b32!?n7>5$027>1><f8:86<h4;*61>5<#99>1855a111964=<#:=1<7*>0587<>h68:09>65$2b83>!77<3>37c??3;00?>-1m3:1(<>;:7f8j4642910';m50;&241<1l2d:<>4>;:)5f?6=,8:?6;j4n020>7=<#?k1<7*>0585`>h68:0876%99;29 4632?n0b<><:598/3>=83.:<949d:l246<232!=:7>5$027>3b<f8:86;54+7794?"68=0=h6`>0284?>-1<3:1(<>;:7f8j4642110';=50;&241<1l2d:<>46;:)56?6=,8:?6;j4n020>d=<#?;1<7*>0585`>h68:0i76%90;29 4632?n0b<><:b98/0`=83.:<949d:l246<c32!>i7>5$027>3b<f8:86h54+4f94?"68=0=h6`>028e?>-2j3:1(<>;:7f8j46428:07&;n:18'552=>m1e===51098/0?=83.:<949d:l246<6:21 954?:%330?0c3g;;?7?<;:)63?6=,8:?6;j4n020>42<3"?=6=4+11692a=i9991=854+4794?"68=0=h6`>02822>=,==0;6)??4;4g?k77;3;<76%:3;29 4632?n0b<><:0:8?.35290/==:56e9m555=9010':;50;&241<1l2d:<>4>a:9(31<72-;;878k;o337?7e32!<?7>5$027>3b<f8:86<m4;*51>5<#99>1:i5a11195a=<#>;1<7*>0585`>h68:0:i65$7183>!77<3<o7c??3;3e?>-1?3:1(<>;:7f8j4642;;07&;l:18'552=>m1e===52398/07=83.:<949d:l246<5;21 5>4?:%330??53g;;?7>4;*;2>5<#99>15?5a11195>=,190;6)??4;;1?k77;3807&6i:18'552=1;1e===53:9(<`<72-;;877=;o337?2<3"2o6=4+1169=7=i9991965$8c83>!77<3397c??3;48?.>f290/==:5939m555=?21 444?:%330??53g;;?764;*:;>5<#99>15?5a1119=>=,0>0;6)??4;;1?k77;3k07&69:18'552=1;1e===5b:9(<0<72-;;877=;o337?e<3"2?6=4+1169=7=i9991h65$8283>!77<3397c??3;g8?.>5290/==:5939m555=n21 4=4?:%330??53g;;?7??;:)4b?6=,8:?64<4n020>47<3"=n6=4+1169=7=i9991=?54+6f94?"68=02>6`>02827>=,?j0;6)??4;;1?k77;3;?76%8b;29 4632080b<><:078?.1f290/==:5939m555=9?10':750;&241<>:2d:<>4>7:9(3=<72-;;877=;o337?7?32!<;7>5$027><4<f8:86<74;*;b>5<#99>15?5a11195d=<#031<7*>058:6>h68:0:n65$9983>!77<3397c??3;3`?>->?3:1(<>;:808j46428n07&79:18'552=1;1e===51d98/<3=83.:<9462:l246<6n21 4n4?:%330??53g;;?7<>;:);5?6=,8:?64<4n020>74<3"==6=4+1169=7=i9991>>54+c:94?"68=0i;6`>0283?>-e>3:1(<>;:c58j4642810'o;50;&241<e?2d:<>4=;:)a0?6=,8:?6o94n020>6=<#k91<7*>058a3>h68:0?76%m2;29 4632k=0b<><:498/g6=83.:<94m7:l246<132!jj7>5$027>g1<f8:86:54+`g94?"68=0i;6`>028;?>-fl3:1(<>;:c58j4642010'lm50;&241<e?2d:<>4n;:)bf?6=,8:?6o94n020>g=<#hk1<7*>058a3>h68:0h76%n9;29 4632k=0b<><:e98/d>=83.:<94m7:l246<b32!j;7>5$027>g1<f8:86k54+`794?"68=0i;6`>02824>=,i=0;6)??4;`4?k77;3;:76%n3;29 4632k=0b<><:008?.g5290/==:5b69m555=9:10'l?50;&241<e?2d:<>4>4:9(e5<72-;;87l8;o337?7232!2j7>5$027>g1<f8:86<84;*;f>5<#99>1n:5a111952=<#0n1<7*>058a3>h68:0:465$9b83>!77<3h<7c??3;3:?>-en3:1(<>;:c58j46428k07&lj:18'552=j>1e===51c98/gb=83.:<94m7:l246<6k21 nn4?:%330?d03g;;?7?k;:)af?6=,8:?6o94n020>4c<3"hj6=4+1169f2=i9991=k54+c394?"68=0i;6`>02815>=,i?0;6)??4;`4?k77;38976%6b;29 4632k=0b<><:318?g41i3:1=7>50z&25g<5>=1C>;64H341?j7783:17pl=6883>4<729q/=<l5d09K63><@;<97bj?:188yg76l3:1n7>50z&25g<5:2B9:55G2708jae=92.h87m9;n33g?6=3f;;j7>5;n33a?6=3f;;57>5;n055?6=3f;;47>5;n33f?6=3`;:<7>5;n05>5<<g8;?6=44ob794?=zj8;h6=4=:183!76j3887E<98:J127=hno0;66gk3;29?xd5;00;6?4?:1y'54d=lk1C>;64H341?lb42900ckh50;9~f75f29096=4?{%32f?be3A8=46F=639j`6<722emj7>5;|`176<72=0;6=u+10`9g<=O:?20D?8=;%fb>7=n:<0;66g=7;29?le52900c<>9:188yg4403:187>50z&25g<d?2B9:55G2708 ag=:2c997>5;h0b>5<<aj81<75`11494?=zj;9<6=4;:183!76j3i27E<98:J127=#lh097d<::188m71=831bo?4?::m243<722wi=9750;094?6|,8;i6il4H34;?M41:2co?7>5;nde>5<<uk;?m7>53;294~"69k0n?6F=699K634<,mk1=l5fd583>>oc=3:17bhi:188yg75=3:197>50z&25g<d02B9:55G2708 ag=:2c997>5;h04>5<<a;k1<75fc383>>i68?0;66sm13494?3=83:p(<?m:b:8L70?3A8=>6*ka;08m73=831b>:4?::k1e?6=3`i96=44o025>5<<uk;9;7>55;294~"69k0h46F=699K634<,mk1>6g=5;29?l402900e?o50;9jg7<722e:<;4?::a57>=83?1<7>t$03a>f><@;<37E<92:&ge?4<a;?1<75f2683>>o5i3:17dm=:188k4612900qo?>f;291?6=8r.:=o4l8:J12==O:?80(io52:k11?6=3`8<6=44i3c94?=nk;0;66a>0783>>{e9;:1<7;50;2x 47e2j20D?87;I056>"ci380e?;50;9j62<722c9m7>5;ha1>5<<g8:=6=44}c315?6==3:1<v*>1c8`<>N5>11C>;<4$ec96>o5=3:17d<8:188m7g=831bo?4?::m243<722wi=?<50;794?6|,8;i6n64H34;?M41:2.om7<4i3794?=n:>0;66g=a;29?le52900c<>9:188yg75;3:197>50z&25g<d02B9:55G2708 ag=:2c997>5;h04>5<<a;k1<75fc383>>i68?0;66sm13694?3=83:p(<?m:b:8L70?3A8=>6*ka;08m73=831b>:4?::k1e?6=3`i96=44o025>5<<uk;9j7>55;294~"69k0n86F=699K634<,mk1=k5+1179627<am>1<75fd483>>oc>3:17dj8:188kc`=831vn<<j:186>5<7s-;:n7k;;I05<>N5>;1/hl4>b:&240<5?<1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm13f94?3=83:p(<?m:d68L70?3A8=>6*ka;37?!77=38<86gk4;29?lb22900ei850;9j`2<722emj7>5;|`26f<72<0;6=u+10`9a1=O:?20D?8=;%fb>44<,8:>6?9<;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg75j3:197>50z&25g<b<2B9:55G2708 ag=991/==;52638ma2=831bh84?::kg2?6=3`n<6=44ogd94?=zj88j6=4::183!76j3o?7E<98:J127=#lh0m7)??5;042>oc<3:17dj::188ma0=831bh:4?::meb?6=3th:?54?:483>5}#98h1i95G27:8L7053-nj6i5+1179620<am>1<75fd483>>oc>3:17dj8:188kc`=831vn<=8:186>5<7s-;:n7k;;I05<>N5>;1/hl4m;%331?40i2co87>5;hf6>5<<am<1<75fd683>>ian3:17pl>3783>0<729q/=<l5e59K63><@;<97)jn:`9'553=:>?0ei:50;9j`0<722co:7>5;hf4>5<<gol1<75rb016>5<2290;w)?>b;g7?M4102B9:?5+d`8:?!77=38<m6gk4;29?lb22900ei850;9j`2<722emj7>5;|`271<72<0;6=u+10`9a1=O:?20D?8=;%fb>==#99?1>:=4ie694?=nl<0;66gk6;29?lb02900ckh50;9~f454290>6=4?{%32f?c33A8=46F=639'`d<03-;;97<84:kg0?6=3`n>6=44ie494?=nl>0;66aif;29?xd6;;0;684?:1y'54d=m=1C>;64H341?!bf2?1/==;526`8ma2=831bh84?::kg2?6=3`n<6=44ogd94?=zj89:6=4::183!76j3o?7E<98:J127=#lh0>7)??5;04f>oc<3:17dj::188ma0=831bh:4?::meb?6=3th:?=4?:483>5}#98h1i95G27:8L7053-nj695+117962e<am>1<75fd483>>oc>3:17dj8:188kc`=831vn<<6:186>5<7s-;:n7k;;I05<>N5>;1/hl4<;%331?40k2co87>5;hf6>5<<am<1<75fd683>>ian3:17pl>3g83>0<729q/=<l5e59K63><@;<97)jn:0d8 4622;=27dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c30a?6==3:1<v*>1c8f0>N5>11C>;<4$ec95g=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=>j50;794?6|,8;i6h:4H34;?M41:2.om7?;;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg74k3:197>50z&25g<b<2B9:55G2708 ag=9;1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm12`94?3=83:p(<?m:d68L70?3A8=>6*ka;33?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;8m7>55;294~"69k0n86F=699K634<,mk1j6gk4;29?lb22900ei850;9j`2<722emj7>5;|`20=<72<0;6=u+10`9a1=O:?20D?8=;%fb>a=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=9950;794?6|,8;i6h:4H34;?M41:2.om7l4ie694?=nl<0;66gk6;29?lb02900ckh50;9~f421290>6=4?{%32f?c33A8=46F=639'`d<f3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?;5;291?6=8r.:=o4j4:J12==O:?80(io59:kg0?6=3`n>6=44ie494?=nl>0;66aif;29?xd6<=0;684?:1y'54d=m=1C>;64H341?!bf211bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm15194?3=83:p(<?m:d68L70?3A8=>6*ka;58ma2=831bh84?::kg2?6=3`n<6=44ogd94?=zj8>96=4::183!76j3o?7E<98:J127=#lh0=7)??5;04=>oc<3:17dj::188ma0=831bh:4?::meb?6=3th:8<4?:483>5}#98h1i95G27:8L7053-nj685+1179624<am>1<75fd483>>oc>3:17dj8:188kc`=831vn<:?:186>5<7s-;:n7k;;I05<>N5>;1/hl4;;%331?40:2co87>5;hf6>5<<am<1<75fd683>>ian3:17pl>3883>0<729q/=<l5e59K63><@;<97)jn:29j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9<;1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c366?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=8h50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7183:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm17394?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;=>7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a535=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?94;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9??1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c352?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=;950;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7103:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm17;94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;=m7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a53d=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?9c;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9?n1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c35a?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=;h50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7083:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm14194?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;>87>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a503=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?:6;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9<=1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c36<?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=8750;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg72i3:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm14`94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;>o7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a50b=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?:e;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9>;1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c346?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=:h50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7?83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm19394?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;3>7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5=5=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?74;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e91?1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3;2?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=5950;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7?03:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm19;94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;3m7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5=d=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?7c;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e91n1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3;a?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=5h50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7>83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm16194?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;<87>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a523=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?86;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9>=1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c34<?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=:750;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg70i3:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm16`94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;<o7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a52b=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?8e;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e90;1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3:6?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=4h50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7f83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1`394?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;j>7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5d5=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?n4;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9h?1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3b2?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=l950;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7f03:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1`;94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;jm7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5dd=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?nc;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9hn1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3ba?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=lh50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7e83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm18194?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;287>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5<3=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?66;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e90=1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3:<?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=4750;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7>i3:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm18`94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;2o7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5<b=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?6e;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9k;1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3a6?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=oh50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7d83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1b394?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;h>7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5f5=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?l4;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9j?1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3`2?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=n950;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7d03:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1b;94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;hm7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5fd=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?lc;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9jn1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3`a?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=nh50;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7c83:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1c194?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;i87>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5g3=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?m6;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9k=1<7;50;2x 47e2l>0D?87;I056>"ci3;m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3a<?6==3:1<v*>1c8f0>N5>11C>;<4$ec95c=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=o750;794?6|,8;i6h:4H34;?M41:2.om7?i;hf7>5<<am?1<75fd783>>oc?3:17bhi:188yg7ei3:197>50z&25g<b<2B9:55G2708 ag=9o1bh94?::kg1?6=3`n=6=44ie594?=hno0;66sm1c`94?3=83:p(<?m:d68L70?3A8=>6*ka;3e?lb32900ei;50;9j`3<722co;7>5;nde>5<<uk;io7>55;294~"69k0n86F=699K634<,mk1=k5fd583>>oc=3:17dj9:188ma1=831djk4?::a5gb=83?1<7>t$03a>`2<@;<37E<92:&ge?7a3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?me;291?6=8r.:=o4j4:J12==O:?80(io51g9j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9m81<7=50;2x 47e2l90D?87;I056>"ci3;87dj;:188ma3=831djk4?::a5a7=8391<7>t$03a>`5<@;<37E<92:&ge?763-;;97<87:kg0?6=3`n>6=44ogd94?=zj8n86=4<:183!76j3o87E<98:J127=#lh0:i6*>04813==nl=0;66gk5;29?j`a2900qo<?a;290?6=8r.:=o4j9:J12==O:?80ei:50;9j`0<722c:<l4?::meb?6=3th9<54?:583>5}#98h1i55G27:8L7053`n?6=44ie794?=n99k1<75`fg83>>{e:9=1<7:50;2x 47e2l20D?87;I056>oc<3:17dj::188m46f2900ckh50;9~f4b0290>6=4?{%32f?c33A8=46F=639'`d<d3`n?6=44ie794?=nl?0;66gk7;29?j`a2900qo?k8;291?6=8r.:=o4j4:J12==O:?80(io5209j`1<722co97>5;hf5>5<<am=1<75`fg83>>{e9m31<7;50;2x 47e2l>0D?87;I056>"ci3;>7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c3ge?6==3:1<v*>1c8f0>N5>11C>;<4$ec95f=nl=0;66gk5;29?lb12900ei950;9lbc<722wi=ik50;094?6|,8;i6il4H34;?M41:2co?7>5;nde>5<<uk;on7>53;294~"69k0n?6F=699K634<,mk1=<5+1179621<am>1<75fd483>>ian3:17pl>de83>0<729q/=<l5e59K63><@;<97)jn:0d8ma2=831bh84?::kg2?6=3`n<6=44ogd94?=zj8nh6=4<:183!76j3o87E<98:J127=#lh0:i6*>04813==nl=0;66gk5;29?j`a2900qo<?9;290?6=8r.:=o4l9:J12==O:?80(io52:k11?6=3`8<6=44ib094?=h99<1<75rb0gg>5<4290;w)?>b;053>N5>11C>;<4i3;94?=nll0;66aif;29?xd6mh0;694?:1y'54d=m>1C>;64H341?l4>2900en=50;9j55g=831dhk4?::a5c7=8391<7>t$03a>7003A8=46F=639j6<<722coi7>5;nde>5<<uk;ni7>54;294~"69k0n;6F=699K634<a;31<75fc283>>o68h0;66akf;29?xd6n<0;6>4?:1y'54d=:?=0D?87;I056>o513:17djj:188kc`=831vn<h=:187>5<7s-;:n7k8;I05<>N5>;1b>44?::k`7?6=3`;;m7>5;nfe>5<<uk;m57>53;294~"69k09::5G27:8L7053`826=44ieg94?=hno0;66sm1g494?2=83:p(<?m:d58L70?3A8=>6g=9;29?le42900e<>n:188ka`=831vn<hk:180>5<7s-;:n7<97:J12==O:?80e?750;9j``<722emj7>5;|`2bd<72=0;6=u+10`9a2=O:?20D?8=;h0:>5<<aj91<75f11c94?=hlo0;66sm21294?5=83:p(<?m:344?M4102B9:?5f2883>>ocm3:17bhi:188yg7bk3:1>7>50z&25g<b:2B9:55G2708 ag=9:1bh94?::meb?6=3th:j=4?:383>5}#98h1i?5G27:8L7053-nj6<=4ie694?=hno0;66sm1g694?4=83:p(<?m:d08L70?3A8=>6*ka;30?lb32900ckh50;9~f4`?29096=4?{%32f?c53A8=46F=639'`d<6;2co87>5;nde>5<<uk;mo7>52;294~"69k0n>6F=699K634<,mk1=>5fd583>>ian3:17pl>fg83>7<729q/=<l5e39K63><@;<97)jn:018ma2=831djk4?::a5`d=83?1<7>t$03a>fd<@;<37E<92:&ge?4<a;?1<75f2683>>od:3:17d??7;29?j77>3:17pl>eg83>0<729q/=<l5cc9K63><@;<97)jn:39j60<722c9;7>5;ha1>5<<a8:<6=44o025>5<<uk;m?7>55;294~"69k0hn6F=699K634<,mk1>6g=5;29?l402900en<50;9j551=831d==850;9~f4`0290>6=4?{%32f?ee3A8=46F=639'`d<53`8>6=44i3594?=nk;0;66g>0683>>i68?0;66sm1g`94?3=83:p(<?m:b`8L70?3A8=>6*ka;08m73=831b>:4?::k`6?6=3`;;;7>5;n332?6=3th:jh4?:483>5}#98h1oo5G27:8L7053-nj6?5f2483>>o5?3:17dm=:188m4602900c<>9:188yg45=3:197>50z&25g<b<2B9:55G2708 ag=l2co87>5;hf6>5<<am<1<75fd683>>ian3:17pl=2283>6<729q/=<l5e29K63><@;<97)jn:0g8ma2=831bh84?::meb?6=3th9>:4?:383>5}#98h1ho5G27:8L7053`n86=44ogd94?=zj;8?6=4::183!76j3o?7E<98:J127=#lh0m7dj;:188ma3=831bh;4?::kg3?6=3flm6=44}c012?6==3:1<v*>1c8`f>N5>11C>;<4$ec96>o5=3:17d<8:188mf4=831b==950;9l550=831vn??l:187>5<7s-;:n7mn;I05<>N5>;1/hl4=;h06>5<<aj81<75f11594?=h99<1<75rb33g>5<3290;w)?>b;ab?M4102B9:?5+d`81?l422900en<50;9j551=831d==850;9~f77b290?6=4?{%32f?ef3A8=46F=639'`d<53`8>6=44ib094?=n99=1<75`11494?=zj;;m6=4;:183!76j3ij7E<98:J127=#lh097d<::188mf4=831b==950;9l550=831vn?<?:187>5<7s-;:n7mn;I05<>N5>;1/hl4=;h06>5<<aj81<75f11594?=h99<1<75rb302>5<3290;w)?>b;ab?M4102B9:?5+d`81?l422900en<50;9j551=831d==850;9~f745290?6=4?{%32f?ef3A8=46F=639'`d<53`8>6=44ib094?=n99=1<75`11494?=zj;296=4?:183M41:2.:=o4>129O545=;r.:=:4>039'54?=kl1/=<o5cg9~yg44<3:187>50z&25g<bi2B9:55G2708ma2=831bh84?::k24d<722emj7>5;|`170<72?0;6=u+10`9a0=O:?20D?8=;%fb>`=nl=0;66gk5;29?lb12900ei950;9j`=<722emj7>5;|`173<72>0;6=u+10`9a3=O:?20D?8=;%fb>76<am>1<75fd483>>oc>3:17dj8:188ma>=831bh44?::meb?6=3th94<4?:183>5}#98h1=<=4H032?I76;38p(<?7:bf8 4712ji0qp}=d;296~X5l27::l4if:p6`<72;qU>h5217a9bc=z{;l1<7<t^3d8940b2ol0q~=?:181[5734;<<7hi;|q05?6=:rT8=63>558eb>{t;;0;6?uQ339>500=no1v>=50;0xZ65<58?36kh4}r17>5<5sW9?70?:a;de?xu4=3:1>vP<5:?21f<an2wx?;4?:3y]73=:9<o1jk5rs2:94?4|V:201<;>:gd8yv5>2909wS=6;<36b?`a3ty8m7>52z\0e>;6>80mj6s|3c83>7}Y;k16=;=5fg9~w6e=838pR>m4=046>c`<uz9o6=4={_1g?871?3lm7p}<e;296~X4m27::44if:p7c<72;qU?k5217`9bc=z{=:1<7<t^528940c2ol0q~:>:181[2634;=j7hi;|q77?6=:rT??63>528eb>{t<=0;6?uQ459>503=no1v9;50;0xZ13<58?<6kh4}r65>5<5sW>=70?:9;de?xu3?3:1>vP;7:?21g<an2wx844?:3y]0<=:9<n1jk5rs5c94?4|V=k01?=::e:8yv2e2909wS:m;<366?`a3ty?o7>52z\7g>;6>90mj6s|4e83>7}Y<m16=;<5fg9~w1c=838pR9k4=047>c`<uz>m6=4={_6e?871>3lm7p}:0;296~X2827::54if:p17<72;qU9?5219c9bc=z{<91<7<t^41894>d2ol0q~;;:181[3334;3i7hi;|q61?6=:rT>963>918eb>{t=?0;6?uQ579>522=no1v8950;0xZ01<58==6kh4}r7;>5<5sW?370?88;de?xu213:1>vP:9:?23d<an2wx9l4?:3y]1d=:9>i1jk5rs4`94?4|V<h01<9j:gd8yv3c2909wS;k;<345?`a3ty>i7>52z\6a>;6?o0mj6s|5g83>7}Y=o16=5?5fg9~w36=838pR;>4=0:0>c`<uz<:6=4={_42?87?=3lm7p}92;296~X1:27:4:4if:p26<72;qU:>5219;9bc=z{?>1<7<t^76894>e2ol0q~8::181[0234;3h7hi;|q52?6=:rT=:63>8g8eb>{t>10;6?uQ699>525=no1v;750;0xZ3?<58=>6kh4}r4b>5<5sW<j70?87;de?xu1j3:1>vP9b:?23<<an2wx:n4?:3y]2f=:9>h1jk5rs7g94?4|V?o01<9k:gd8yv0a2909wS8i;<002?b?3ty<<7>52z\44>;6?;0mj6s|7083>7}Y?816=5>5fg9~w24=838pR:<4=0:1>c`<uz=86=4={_50?87?<3lm7p}84;296~X0<27:4;4if:p30<72;qU;85219:9bc=z{>=1<7<t^65894gf2ol0q~97:181[1?34;jo7hi;|q4=?6=:rT<563>ad8eb>{t?h0;6?uQ7`9>5g6=no1v:l50;0xZ2d<583?6kh4}r5`>5<5sW=h70?66;de?xu0l3:1>vP8d:?2==<an2wx;h4?:3y]3`=:90k1jk5rs6d94?4|V>l01<7l:gd8yv>72909wS6?;<3:a?`a3ty3>7>52z\;6>;6180mj6s|8283>7}Y0:16=4h5fg9~w=2=838pR5:4=0c2>c`<uz2>6=4={_:6?87f;3lm7p}76;296~X?>27:m84if:p<2<72;qU4:521`59bc=z{121<7<t^9:894g>2ol0q~66:181[>>34;jn7hi;|q;e?6=:rT3m63>ae8eb>{t0k0;6?uQ8c9>5d`=no1v5j50;0xZ=b<58386kh4}r:f>5<5sW2n70?65;de?xu?n3:1>vP7f:?2=2<an2wx5=4?:3y]=5=:9031jk5rs8394?4|V0;01<7m:gd8yv?42909wS7<;<3:`?`a3ty287>52z\:0>;5;<0o;6s|9483>7}Y1<16=4<5fg9~w<0=838pR484=0c3>c`<uz3<6=4={_;4?87f:3lm7p}68;296~X>027:m94if:p=<<72;qU54521`49bc=z{0k1<7<t^8c894g?2ol0q~7l:181[?d34;hm7hi;|q:`?6=:rT2h63>cb8eb>{t1l0;6?uQ9d9>5fc=no1v4h50;0xZ<`<58n;6kh4}rc3>5<5sWk;70?m4;de?xuf93:1>vPn1:?2f3<an2wxm?4?:3y]e7=:9k21jk5rs`194?4|Vh901<ln:gd8yvg32909wSo;;<3ag?`a3tyj97>52z\b1>;6jl0mj6s|a683>7}Yi>16=o?5fg9~wd>=838pRl64=0`e>c`<uzk26=4={_c:?87d93lm7p}na;296~Xfi27:o>4if:peg<72;qUmo521b79bc=z{hi1<7<t^`a894e02ol0q~ok:181[gc34;h57hi;|qba?6=:rTji63>cc8eb>{tio0;6?uQag9>5fb=no1vo>50;0xZg6<58im6kh4}r`1>5<5sWh970?m3;de?xue;3:1>vPm3:?2f0<an2wxn94?:3y]f1=:9k=1jk5rsc794?4|Vk?01<l6:gd8yvd12909wSl9;<3af?`a3tyi47>52z\a<>;6jm0mj6s|b883>7}Yj016>>85d69~wgg=838pRoo4=0`1>c`<uzhi6=4={_`a?87d83lm7p}mc;296~Xek27:o?4if:pfa<72;qUni521b69bc=z{ko1<7<t^cg894e12ol0q~li:181[da34;h47hi;|qf`?6=lr79:l4>019>661=:>16>>=5269>65?=:>16=kk5269>5cd=:>16=k95269>5c5=:>16=hh5269>5`d=:>16=ho5289>5`b=:016>?85c39~w`c=838p1?=::gd897532m>0q~ki:181844>3lm70<<4;f6?xua83:1<vs|f083>5}z{o81<7>t}rd0>5<7stym87>50zpb0<729qvk850;2xyv`0290;wp}i8;294~{tn00;6luQ439]22=Y0j16=ko5c29>5c0=k:16=k<5c29>5`c=k:16=ho5c29>63?=l91Un<5rsgc94?>|V:=0R8m4^93894432j801?<=:b0897432m=0Rl84=310>4613tymn7>521y]6f=Y=81U;;52225960=:::91>852136960=:9;91>852130960=:9;;1>852132960=:98l1>85213:960=:9;=1>852134960=:9;?1>85221;960=:9oo1>8521g`960=:9o=1>8521g1960=:9ll1>8521d`960=::;81>852233960=::;:1>85220d960=::8o1>85220f960=::8i1>852234960=Y1k16=<m5fg9~w47b2909w0?>c;f0?876l3i>7p}>4c83>g}:9;>1>l5213196d=:9;81>l5213396d=:9;:1>l5210d96d=:9;21>l5213596d=:9;<1>l5213796d=:9=31jk5rs06`>5<6:r7:=k4>079>57>=k;16=?75d79>566=l?16=>?5d79>564=l?16=>=5d79>562=l?16=>;5d79>560=l?16=>95d79>56>=l?16=?o5d79>57d=l?16=?m5d79>57b=l?16=?k5d79>57`=l?1v<:k:1826~;6:90:<;5210d9g7=:9;31h:521229`2=:9:;1h:521209`2=:9:91h:521269`2=:9:?1h:521249`2=:9:=1h:5212:9`2=:9;k1h:5213`9`2=:9;i1h:5213f9`2=:9;o1h:5213d9`2=z{8>n6=4>2z?262<68?16=?85c39>57?=l=16=>>5d59>567=l=16=><5d59>565=l=16=>:5d59>563=l=16=>85d59>561=l=16=>65d59>57g=l=16=?l5d59>57e=l=16=?j5d59>57c=l=16=?h5d59~w42a290:>v3>298243=:9;=1o?5213;9`0=:9::1h8521239`0=:9:81h8521219`0=:9:>1h8521279`0=:9:<1h8521259`0=:9:21h85213c9`0=:9;h1h85213a9`0=:9;n1h85213g9`0=:9;l1h85rs073>5<es4;987<8;<317?4034;9>7<8;<315?4034;9<7<8;<32b?4034;947<8;<313?4034;9:7<8;<311?4034;?m7hi;|q2`1<72=;p1<j>:gd894db2m=01<ll:e5894df2m=01<l7:e5894d12m=01<l;:e5894b72m=01<mj:e5894ed2m=01<mn:e5894e?2m=01<m9:e5894e32m=01<m=:e5894e72m=01<l=:e5894?b2m=01<7l:e5894?f2m=01<77:e5894?12m=01<7;:e5894d72m=01<oj:e5894gd2m=01<on:e5894g?2m=01<o9:e5894g32m=01<o=:e5894g72m=01<7=:e58941b2m=01<9l:e58941f2m=01<97:e5894112m=01<9;:e5894?72m=01<6j:e5894>d2m=01<6n:e5894>?2m=01<69:e5894>32m=01<6=:e5894>72m=01<9=:e58943b2m=01<;l:e58943f2m=01<;7:e5894312m=01<;;:e5894172m=01<8j:e58940d2m=01<8n:e58940?2m=01<89:e5894032m=01<8=:e5894072m=01<;=:e58yv7c=3:18<u21e09bc=:9kn1h:521c`9`2=:9k31h:521c59`2=:9k?1h:521c19`2=:9jl1h:521bf9`2=:9jh1h:521b;9`2=:9j=1h:521b79`2=:9j91h:521b39`2=:9kl1h:521c39`2=:90n1h:5218`9`2=:9031h:521859`2=:90?1h:521819`2=:9hl1h:521`f9`2=:9hh1h:521`;9`2=:9h=1h:521`79`2=:9h91h:521`39`2=:90l1h:521839`2=:9>n1h:5216`9`2=:9>31h:521659`2=:9>?1h:521619`2=:91l1h:5219f9`2=:91h1h:5219;9`2=:91=1h:521979`2=:9191h:521939`2=:9>l1h:521639`2=:9<n1h:5214`9`2=:9<31h:521459`2=:9<?1h:521419`2=:9?l1h:5217f9`2=:9?h1h:5217;9`2=:9?=1h:521779`2=:9?91h:521739`2=:9<l1h:521439`2=z{8n=6=471z?2`6<an27:nh4k4:?2fa<c<27:nn4k4:?2fg<c<27:nl4k4:?2f<<c<27:n54k4:?2f2<c<27:n;4k4:?2f0<c<27:n94k4:?2f6<c<27:h=4k4:?2gc<c<27:oh4k4:?2ga<c<27:on4k4:?2gg<c<27:ol4k4:?2g<<c<27:o54k4:?2g2<c<27:o;4k4:?2g0<c<27:o94k4:?2g6<c<27:o?4k4:?2g4<c<27:o=4k4:?2fc<c<27:n?4k4:?2f4<c<27:5h4k4:?2=a<c<27:5n4k4:?2=g<c<27:5l4k4:?2=<<c<27:554k4:?2=2<c<27:5;4k4:?2=0<c<27:594k4:?2=6<c<27:n=4k4:?2ec<c<27:mh4k4:?2ea<c<27:mn4k4:?2eg<c<27:ml4k4:?2e<<c<27:m54k4:?2e2<c<27:m;4k4:?2e0<c<27:m94k4:?2e6<c<27:m?4k4:?2e4<c<27:m=4k4:?2=c<c<27:5?4k4:?2=4<c<27:;h4k4:?23a<c<27:;n4k4:?23g<c<27:;l4k4:?23<<c<27:;54k4:?232<c<27:;;4k4:?230<c<27:;94k4:?236<c<27:5=4k4:?2<c<c<27:4h4k4:?2<a<c<27:4n4k4:?2<g<c<27:4l4k4:?2<<<c<27:454k4:?2<2<c<27:4;4k4:?2<0<c<27:494k4:?2<6<c<27:4?4k4:?2<4<c<27:4=4k4:?23c<c<27:;?4k4:?234<c<27:9h4k4:?21a<c<27:9n4k4:?21g<c<27:9l4k4:?21<<c<27:954k4:?212<c<27:9;4k4:?210<c<27:994k4:?216<c<27:;=4k4:?22c<c<27::h4k4:?22a<c<27::n4k4:?22g<c<27::l4k4:?22<<c<27::54k4:?222<c<27::;4k4:?220<c<27::94k4:?226<c<27::?4k4:?224<c<27::=4k4:?21c<c<27:9?4k4:?214<c<2wx=ih50;1x94cb2;301<h>:3;894cf2ml0q~?j0;297~;6n;09563>f481=>;6ml0oj6s|1d394?5|58l=6?74=0d:>7?<58l96ih4}r3f6?6=;r7:jl4=9:?2ba<5127:j;4kf:p5`5=838p1?>?:3;894`f2ml0q~?j4;296~;6mk0h>63>ee8eb>{t9l?1<7<t=0ge>f4<58l:6kh4}r3f2?6=:r7:j>4l2:?2b0<an2wx=h950;0x94`02j801<h6:gd8yv7b03:1>v3>fc8`6>;6nm0mj6s|1d;94?4|58ln6n<4=323>c`<uz8;=7>53z?2af<an27:il4>0`9>5`b=ll1v?>=:18087a83lm70?je;33e>;6n80oi6s|21194?5|58l?6kh4=0d1>46f34;m97jj;|q141<72:q6=k65fg9>5c0=99k01<h6:eg8yv47=3:1?v3>fb8eb>;6nh0:<l521gf9``=z{;:=6=4={<3eb?`a348;<7jj;|q14g<72;q6=ij5d69>5ad=no1v?>l:18187ck3lm70?kd;f7?xu58m0;6?u21e59bc=::921h95rs32f>5<5s4;o47hi;<03<?b23ty9<k4?:3y>5a?=no16>=95d59~w7772909w0?ka;de?847?3n>7p}=1083>7}:9mn1jk521eg9`6=z{;;96=48{<3ga?`a34;mi7??7:?2bg<68>16=k95115894`428:<70?jf;333>;6mk0:<:5rs330>5<1s4;om7j;;<3g=?b334;o47j;;<3g3?b334;nn7??6:?2af<c<2wx><:50;4x94bf2m?01<j6:e7894b?2m?01<j8:e7894ca28:=70?i0;f7?xu59<0;6;u21ec9`3=:9m31h;521e:9`3=:9m=1h;521g19550<58l?6i:4}r022?6=>r7:hl4k7:?2`<<c?27:h54k7:?2`2<c?27:j:4>079>5c>=l=1v??8:187847?3;;m63=09824d=:9oh1==84=0d`>a2<uz8:47>53z?14d<68h16=kk5114894`a2m>0q~<>9;296~;58>0mj63=0`8g1>{t:8k1<7<t=32;>c`<5;:j6i:4}r02f?6=:r79<44l2:?14d<an2wx>?650;;x974528:<70<=1;333>;5:90:<:5220d9551<5;;n6<>8;<02`?77?279=n4>069>670=99=01?<8:gd8yv4513:1>v3=27813>;5::0mj6s|23c94?4|5;8?6kh4=300>a3<uz89n7>52z?166<c<279>84if:p67e=838p1??l:025?845=3n?7p}=2e83>6}::8n1==84=33`>f4<5;8>6i;4}r01a?6=;r79=h4>079>64b=k;16>?;5d79~w74a2908w0<>f;332>;59l0h>63=248g3>{t:::1<7=t=303>461348:j7m=;<010?b33ty9?<4?:2y>677=99<01?<?:b0897432m?0q~<<2;297~;5:;0:<;522339g7=::;>1h;5rs31a>5<3s4;997??6:?2`4<c<27:h?4k4:?2`g<c<2wx>>m50;7x944128:=70?=5;a1?87c93n>70?k2;f6?87cj3n>7p}=3e83>d}:9;31jk521c09`0=:9k;1h8521809`0=:90;1h8521609`0=:9>;1h8521409`0=:9<;1h8521ef9`0=z{;9n6=46{<31e?`a34;i87j:;<3a7?b234;287j:;<3:7?b234;<87j:;<347?b234;>87j:;<367?b23ty9?k4?:8y>57d=no16=o85d49>5g3=l<16=485d49>5<3=l<16=:85d49>523=l<16=885d49>503=l<1v?:?:18:875k3lm70?m8;f6?87e?3n>70?68;f6?87>?3n>70?88;f6?870?3n>70?:8;f6?872?3n>7p}=4083><}:9;n1jk521cc9`0=:9k31h85218c9`0=:9031h85216c9`0=:9>31h85214c9`0=:9<31h85rs361>5<>s4;9i7hi;<3ag?b234;in7j:;<3:g?b234;2n7j:;<34g?b234;<n7j:;<36g?b234;>n7j:;|q106<720q6=?h5fg9>5gc=l<16=oj5d49>5<c=l<16=4j5d49>52c=l<16=:j5d49>50c=l<16=8j5d49~w7232902w0?<0;de?87d83n>70?mf;f6?87f83n>70?6f;f6?87?83n>70?8f;f6?87183n>70?:f;f6?xu5<<0;64u21239bc=:9j81h8521b39`0=:9h81h8521`39`0=:9181h8521939`0=:9?81h8521739`0=z{;>=6=46{<306?`a34;h87j:;<3`7?b234;j87j:;<3b7?b234;387j:;<3;7?b234;=87j:;<357?b23ty98:4?:8y>565=no16=n85d49>5f3=l<16=l85d49>5d3=l<16=585d49>5=3=l<16=;85d49>533=l<1v?:7:18:874<3lm70?l8;f6?87d?3n>70?n8;f6?87f?3n>70?78;f6?87??3n>70?98;f6?871?3n>7p}=4883><}:9:?1jk521bc9`0=:9j31h8521`c9`0=:9h31h85219c9`0=:9131h85217c9`0=:9?31h85rs36b>5<>s4;8:7hi;<3`g?b234;hn7j:;<3bg?b234;jn7j:;<3;g?b234;3n7j:;<35g?b234;=n7j:;|q10g<720q6=>95fg9>5fc=l<16=nj5d49>5dc=l<16=lj5d49>5=c=l<16=5j5d49>53c=l<16=;j5d49~w72d2902w0?<8;de?87c83n>70?lf;f6?87e83n>70?nf;f6?87>83n>70?7f;f6?87083n>70?9f;f6?xu5<m0;6<=t=002>46134;9<7m=;<30=?b334;?<7j;;<375?b334;?>7j;;<377?b334;?87j;;<371?b334;?:7j;;<373?b334;?47j;;<30e?b334;8n7j;;<30g?b334;8h7j;;<30a?b334;8j7j;;<000?77i2wx>9k50;37875:3;;:63>208`6>;6;00o963>418g1>;6<80o963>438g1>;6<:0o963>458g1>;6<<0o963>478g1>;6<>0o963>498g1>;6;h0o963>3c8g1>;6;j0o963>3e8g1>;6;l0o963>3g8g1>;5;<0o863=378g0>{t:=l1<7?;{<317?77>27:>?4l2:?27<<c>27:8=4k6:?204<c>27:8?4k6:?206<c>27:894k6:?200<c>27:8;4k6:?202<c>27:854k6:?27d<c>27:?o4k6:?27f<c>27:?i4k6:?27`<c>27:?k4k6:?170<c=279?;4k5:p606=83;?w0?=4;332>;6::0h>63>388g3>;6<90o;63>408g3>;6<;0o;63>428g3>;6<=0o;63>448g3>;6<?0o;63>468g3>;6<10o;63>3`8g3>;6;k0o;63>3b8g3>;6;m0o;63>3d8g3>;6;o0o;63=348g2>;5;?0o:6s|24394?46s4;857hi;<36a?b134;>h7j9;<36g?b134;>n7j9;<36e?b134;>57j9;<36<?b134;>;7j9;<362?b134;>97j9;<360?b134;>?7j9;<344?b134;=j7j9;<35a?b134;=h7j9;<35g?b134;=n7j9;<35e?b134;=57j9;<35<?b134;=;7j9;<352?b134;=97j9;<350?b134;=?7j9;<356?b134;==7j9;<354?b134;>j7j9;<366?b134;>=7j9;|q117<72;q6=>h5fg9>5ab=l?1v?;<:1815~;6<90mj63>7d8g2>;6?m0o:63>7b8g2>;6?k0o:63>7`8g2>;6?00o:63>798g2>;6?>0o:63>778g2>;6?<0o:63>758g2>;6?:0o:63>918g2>;60o0o:63>8d8g2>;60m0o:63>8b8g2>;60k0o:63>8`8g2>;6000o:63>898g2>;60>0o:63>878g2>;60<0o:63>858g2>;60:0o:63>838g2>;6080o:63>818g2>;6?o0o:63>738g2>;6?80o:6s|24694?46s4;?=7hi;<3:a?b134;2h7j9;<3:g?b134;2n7j9;<3:e?b134;257j9;<3:<?b134;2;7j9;<3:2?b134;297j9;<3:0?b134;2?7j9;<3a4?b134;jj7j9;<3ba?b134;jh7j9;<3bg?b134;jn7j9;<3be?b134;j57j9;<3b<?b134;j;7j9;<3b2?b134;j97j9;<3b0?b134;j?7j9;<3b6?b134;j=7j9;<3b4?b134;2j7j9;<3:6?b134;2=7j9;|q110<72;;p1<:=:gd894db2m<01<lk:e4894dd2m<01<lm:e4894df2m<01<l6:e4894d?2m<01<l8:e4894d12m<01<l::e4894d32m<01<l<:e4894b72m<01<mi:e4894eb2m<01<mk:e4894ed2m<01<mm:e4894ef2m<01<m6:e4894e?2m<01<m8:e4894e12m<01<m::e4894e32m<01<m<:e4894e52m<01<m>:e4894e72m<01<li:e4894d52m<01<l>:e48yv42>3:18v3=398243=:::31h>5215c9`1=::;=1h>5rs374>5<5s48847m=;<00=?`a3ty9954?:2y>66g=l:16=<j511`8942>2m90q~<:9;296~;5;109m63=3`8eb>{t:<k1<7=t=0f0>a2<58nh6i:4=305>4613ty99o4?:3y>665=k;16=<j511d8yv42k3:1>v3=368243=:98n1=<>4}r06`?6=:r79<44>079>660=l01v?;j:181844?3i970<<4;de?xu5=o0;69u210f955e<58>j6i;4=0f0>a3<58nh6i;4}r054?6=:r79?54=5:?25a<5>81vqc;la;295~N5>;1vb8mm:182M41:2we9nm50;3xL7053td>oi4?:0yK634<ug?hi7>51zJ127=zf<im6=4>{I056>{i=m:1<7?tH341?xh2l80;6<uG2708yk3c:3:1=vF=639~j0b4290:wE<92:m1a2=83;pD?8=;|l6`0<728qC>;<4}o7g2?6=9rB9:?5rn4f4>5<6sA8=>6sa5e:94?7|@;<97p`:d883>4}O:?80qc;ka;295~N5>;1vb8jm:182M41:2we9im50;3xL7053td>hi4?:0yK634<ug?oi7>51zJ127=zf<nm6=4>{I056>{i=l:1<7?tH341?xh2m80;6<uG2708yk3b:3:1=vF=639~j0c4290:wE<92:m1`2=83;pD?8=;|l6a0<728qC>;<4}o7f2?6=9rB9:?5rn4g4>5<6sA8=>6sa5d:94?7|@;<97p`:e883>4}O:?80qc;ja;295~N5>;1vb8km:182M41:2we9hm50;3xL7053td>ii4?:0yK634<ug?ni7>51zJ127=zf<om6=4>{I056>{i=o:1<7?tH341?xh2n80;6<uG2708yk3a:3:1=vF=639~j0`4290:wE<92:m1c2=83;pD?8=;|l6b0<728qC>;<4}o7e2?6=9rB9:?5rn4d4>5<6sA8=>6sa5g:94?7|@;<97p`:f883>4}O:?80qc;ia;295~N5>;1vb8hm:182M41:2we9km50;3xL7053td>ji4?:0yK634<ug?mi7>51zJ127=zf<lm6=4>{I056>{i>9:1<7?tH341?xh1880;6<uG2708yk07:3:1=vF=639~j364290:wE<92:m252=83;pD?8=;|l540<728qC>;<4}o432?6=9rB9:?5rn724>5<6sA8=>6sa61:94?7|@;<97p`90883>4}O:?80qc8?a;295~N5>;1vb;>m:182M41:2we:=m50;3xL7053td=<i4?:0yK634<ug<;i7>51zJ127=zf?:m6=4>{I056>{i>8:1<7?tH341?xh1980;6<uG2708yk06:3:1=vF=639~j374290:wE<92:m242=83;pD?8=;|l550<728qC>;<4}o422?6=9rB9:?5rn734>5<6sA8=>6sa60:94?7|@;<97p`91883>4}O:?80qc8>a;295~N5>;1vb;?m:182M41:2we:<m50;3xL7053td==i4?:0yK634<ug<:i7>51zJ127=zf?;m6=4>{I056>{i>;:1<7?tH341?xh1:80;6<uG2708yk05:3:1=vF=639~j344290:wE<92:m272=83;pD?8=;|l560<728qC>;<4}o412?6=9rB9:?5rn704>5<6sA8=>6sa63:94?7|@;<97p`92883>4}O:?80qc8=a;295~N5>;1vb;<m:182M41:2we:?m50;3xL7053td=>i4?:0yK634<ug<9i7>51zJ127=zf?8m6=4>{I056>{i>::1<7?tH341?xh1;80;6<uG2708yk04:3:1=vF=639~j354290:wE<92:m262=83;pD?8=;|l570<728qC>;<4}o402?6=9rB9:?5rn714>5<6sA8=>6sa62:94?7|@;<97p`93883>4}O:?80qc8<a;295~N5>;1vb;=m:182M41:2we:>m50;3xL7053td=?i4?:0yK634<ug<8i7>51zJ127=zf?9m6=4>{I056>{i>=:1<7?tH341?xh1<80;6<uG2708yk03:3:1=vF=639~j324290:wE<92:m212=83;pD?8=;|l500<728qC>;<4}o472?6=9rB9:?5rn764>5<6sA8=>6sa65:94?7|@;<97p`94883>4}O:?80qc8;a;295~N5>;1vb;:m:182M41:2we:9m50;3xL7053td=8i4?:0yK634<ug<?i7>51zJ127=zf?>m6=4>{I056>{i><:1<7?tH341?xh1=80;6<uG2708yk02:3:1=vF=639~j334290:wE<92:m202=83;pD?8=;|l510<728qC>;<4}o462?6=9rB9:?5rn774>5<6sA8=>6sa64:94?7|@;<97p`95883>4}O:?80qc8:a;295~N5>;1vb;;m:182M41:2we:8m50;3xLcb<@oo0V<?::0yg`?{O:?80qc8:d;295~N5>;1vb;;j:182M41:2we:8h50;3xL7053td=:=4?:0yK634<ug<==7>51zJ127=zf?<96=4>{I056>{i>?91<7?tH341?xh1>=0;6<uG2708yk01=3:1=vF=639~j301290:wE<92:m231=83;pD?8=;|l52=<728qC>;<4}o45=?6=9rB9:?5rn74b>5<6sA8=>6sa67`94?7|@;<97p`96b83>4}O:?80qc89d;295~N5>;1vb;8j:182M41:2we:;h50;3xL7053td=;=4?:0yK634<ug<<=7>51zJ127=zf?=96=4>{I056>{i>>91<7?tH341?xh1?=0;6<uG2708yk00=3:1=vF=639~j311290:wE<92:m221=83;pD?8=;|l53=<728qC>;<4}o44=?6=9rB9:?5rn75b>5<6sA8=>6sa66`94?7|@;<97p`97b83>4}O:?80qc88d;295~N5>;1vb;9j:182M41:2we::h50;3xL7053td=4=4?:0yK634<ug<3=7>51zJ127=zf?296=4>{I056>{i>191<7?tH341?xh10=0;6<uG2708yk0?=3:1=vF=639~j3>1290:wE<92:m2=1=83;pD?8=;|l5<=<728qC>;<4}o4;=?6=9rB9:?5rn7:b>5<6sA8=>6sa69`94?7|@;<97p`98b83>4}O:?80qc87d;295~N5>;1vb;6j:182M41:2we:5h50;3xL7053td=5=4?:0yK634<ug<2=7>51zJ127=zf?396=4>{I056>{i>091<7?tH341?xh11=0;6<uG2708yk0>=3:1=vF=639~j3?1290:wE<92:m2<1=83;pD?8=;|l5==<728qC>;<4}o4:=?6=9rB9:?5rn7;b>5<6sA8=>6sa68`94?7|@;<97p`99b83>4}O:?80qc86d;295~N5>;1vb;7j:182M41:2we:4h50;3xL7053td=m=4?:0yK634<ug<j=7>51zJ127=zf?k96=4>{I056>{i>h91<7?tH341?xh1i=0;6<uG2708yk0f=3:1=vF=639~j3g1290:wE<92:m2d1=83;pD?8=;|l5e=<728qC>;<4}o4b=?6=9rB9:?5rn7cb>5<6sA8=>6sa6``94?7|@;<97p`9ab83>4}O:?80qc8nd;295~N5>;1vb;oj:182M41:2we:lh50;3xL7053td=n=4?:0yK634<ug<i=7>51zJ127=zf?h96=4>{I056>{i>k91<7?tH341?xh1j=0;6<uG2708yk0e=3:1=vF=639~j3d1290:wE<92:m2g1=83;pD?8=;|l5f=<728qCjh5Gfe9Y544=9r:1qE<92:m2g?=83;pDkj4Hgg8^47228q9:>4rH341?x{zuIJHw:on:d;3e4379tJKNv>r@ARxyEF
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/icon0.asy b/FEE_ADC32board/project/ipcore_dir/icon0.asy
deleted file mode 100644
index aca3227..0000000
--- a/FEE_ADC32board/project/ipcore_dir/icon0.asy
+++ /dev/null
@@ -1,25 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 icon0
-RECTANGLE Normal 32 32 544 864
-LINE Wide 576 112 544 112
-PIN 576 112 RIGHT 36
-PINATTR PinName control0[35:0]
-PINATTR Polarity BOTH
-LINE Wide 576 144 544 144
-PIN 576 144 RIGHT 36
-PINATTR PinName control1[35:0]
-PINATTR Polarity BOTH
-LINE Wide 576 176 544 176
-PIN 576 176 RIGHT 36
-PINATTR PinName control2[35:0]
-PINATTR Polarity BOTH
-LINE Wide 576 208 544 208
-PIN 576 208 RIGHT 36
-PINATTR PinName control3[35:0]
-PINATTR Polarity BOTH
-LINE Wide 576 240 544 240
-PIN 576 240 RIGHT 36
-PINATTR PinName control4[35:0]
-PINATTR Polarity BOTH
-
diff --git a/FEE_ADC32board/project/ipcore_dir/icon0.gise b/FEE_ADC32board/project/ipcore_dir/icon0.gise
deleted file mode 100644
index 0c33e27..0000000
--- a/FEE_ADC32board/project/ipcore_dir/icon0.gise
+++ /dev/null
@@ -1,32 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="icon0.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="icon0.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="icon0.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="icon0.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/icon0.ngc b/FEE_ADC32board/project/ipcore_dir/icon0.ngc
deleted file mode 100644
index 99ba409..0000000
--- a/FEE_ADC32board/project/ipcore_dir/icon0.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$2675=6:2.Yi{g|inl9$4(5=0*/>6#>1:27?5679=1;<=<;;12301=7892?7=>>0593476339:?<95?0927?5778=1;==?;;10341=7<9:?7=6?00920>7789;;7<;>4173047689;;<<5=4:03452<:8:;=:5<6;KMKPR=KFD_^BB?<2794;703:<1ECAZT;ALJQTHD86897>116902?OIG\^1OB@[RNN1863=87;<7>85IOMVP?EHF]XD@>2<5;2=52=4>3CECXZ5CNLWVJJ34:?1<3?4459745633<<:<k59vmz275ran=2?!>?4859;4566823:5=6>8132556689n0N^MNN^TJVQC_>=1IYKI7;CWP[LHAG81H;6MNPUWQA7=DM880OEKLK^NJG@HTMV^R\H<4CH68GIM7>2IGG<6?6:AOO717=2IGG?V7;BNH6]7?8<1H@F7?5:AOOD703JF@M<J=7:AOOD7C<>1H@FO>D978GIME9<1H@FM>5:AOOA723JF@H[m4CMIGRZBN^@NN96MCKGZ;?FJLNQ;3<>5LLS;8GJKJA]^NHo5LOOVQKI6;87i0OB@[RNN38469k2IDBY\@L1>25;e<KFD_^BB?<00=g>EHF]XD@=2>3?a8GJHSZFF;0<:1c:ALJQTHD96:93m4CNLWVJJ748<5o6M@NUPLH5:6?7i0OB@[RNN384>9k2IDBY\@L1>2=;d<KFD_^BB?<0<`?FII\[EG<1<?>b9@KKRUGE:7><0l;BMMPWIK85892n5LOOVQKI6;::4h7NAATSMO49436j1HCCZ]OM2?608d3JEEX_AC0=05:f=DGG^YCA>326<`?FII\[EG<1<7>b9@KKRUGE:7>40m;BMMPWIK8585o6M@NUPLH5:487i0OB@[RNN38679k2IDBY\@L1>06;e<KFD_^BB?<21=g>EHF]XD@=2<4?g8GJHSZFF;0>;50?a8GJHSZFF;0>;1b:ALJQTHD9682o5LOOVQKI6;<7h0OB@[RNN3808e3JEEX_AC0=4=f>EHF]XD@=28>c9@KKRUGE:743l4CNLWVJJ7404i7NAATSMO5969k2IDBY\@L0>24;e<KFD_^BB><03=g>EHF]XD@<2>2?a8GJHSZFF:0<=1c:ALJQTHD86:83m4CNLWVJJ648?5o6M@NUPLH4:6>7i0OB@[RNN28419k2IDBY\@L0>2<;e<KFD_^BB><0;=f>EHF]XD@<2>>b9@KKRUGE;7>=0l;BMMPWIK958:2n5LOOVQKI7;:;4h7NAATSMO59446j1HCCZ]OM3?618d3JEEX_AC1=06:f=DGG^YCA?327<`?FII\[EG=1<8>b9@KKRUGE;7>50l;BMMPWIK95822o5LOOVQKI7;:7i0OB@[RNN28669k2IDBY\@L0>05;e<KFD_^BB><20=g>EHF]XD@<2<3?a8GJHSZFF:0>:1e:ALJQTHD86897>1c:ALJQTHD86893l4CNLWVJJ64:4i7NAATSMO5929j2IDBY\@L0>6:g=DGG^YCA?36?`8GJHSZFF:0:0m;BMMPWIK9525n6M@NUPLH4:>6k1HCCZ]OM0?4;e<KFD_^BB=<02=g>EHF]XD@?2>1?a8GJHSZFF90<<1c:ALJQTHD;6:?3m4CNLWVJJ548>5o6M@NUPLH7:6=7i0OB@[RNN18409k2IDBY\@L3>23;e<KFD_^BB=<0:=g>EHF]XD@?2>9?`8GJHSZFF90<0l;BMMPWIK:58;2n5LOOVQKI4;:84h7NAATSMO69456j1HCCZ]OM0?668d3JEEX_AC2=07:f=DGG^YCA<324<`?FII\[EG>1<9>b9@KKRUGE87>:0l;BMMPWIK:5832n5LOOVQKI4;:04i7NAATSMO6949k2IDBY\@L3>04;e<KFD_^BB=<23=g>EHF]XD@?2<2?a8GJHSZFF90>=1c:ALJQTHD;6883k4CNLWVJJ54:?1<3m4CNLWVJJ54:?5n6M@NUPLH7:46k1HCCZ]OM0?0;d<KFD_^BB=<4<a?FII\[EG>181b:ALJQTHD;6<2o5LOOVQKI4;07h0OB@[RNN18<8e3JEEX_AC3=2=g>EHF]XD@>2>0?a8GJHSZFF80<?1c:ALJQTHD:6:>3m4CNLWVJJ44895o6M@NUPLH6:6<7i0OB@[RNN08439k2IDBY\@L2>22;e<KFD_^BB<<05=g>EHF]XD@>2>8?a8GJHSZFF80<71b:ALJQTHD:6:2n5LOOVQKI5;:94h7NAATSMO79466j1HCCZ]OM1?678d3JEEX_AC3=00:f=DGG^YCA=325<`?FII\[EG?1<:>b9@KKRUGE97>;0l;BMMPWIK;58<2n5LOOVQKI5;:14h7NAATSMO794>6k1HCCZ]OM1?6;e<KFD_^BB<<22=g>EHF]XD@>2<1?a8GJHSZFF80><1c:ALJQTHD:68?3m4CNLWVJJ44:>5i6M@NUPLH6:4=3:5o6M@NUPLH6:4=7h0OB@[RNN0868e3JEEX_AC3=6=f>EHF]XD@>2:>c9@KKRUGE97:3l4CNLWVJJ44>4i7NAATSMO79>9j2IDBY\@L2>::g=DGG^YCA:30?a8GJHSZFF?0<>1c:ALJQTHD=6:=3m4CNLWVJJ34885o6M@NUPLH1:6;7i0OB@[RNN78429k2IDBY\@L5>21;e<KFD_^BB;<04=g>EHF]XD@92>7?a8GJHSZFF?0<61c:ALJQTHD=6:53l4CNLWVJJ3484h7NAATSMO09476j1HCCZ]OM6?648d3JEEX_AC4=01:f=DGG^YCA:322<`?FII\[EG81<;>b9@KKRUGE>7>80l;BMMPWIK<58=2n5LOOVQKI2;:>4h7NAATSMO094?6j1HCCZ]OM6?6<8e3JEEX_AC4=0=g>EHF]XD@92<0?a8GJHSZFF?0>?1c:ALJQTHD=68>3m4CNLWVJJ34:95o6M@NUPLH1:4<7o0OB@[RNN7863=87i0OB@[RNN78639j2IDBY\@L5>0:g=DGG^YCA:34?`8GJHSZFF?080m;BMMPWIK<5<5n6M@NUPLH1:06k1HCCZ]OM6?<;d<KFD_^BB;<8<20>EHZLULICK]AUKLJZOINF=0O_KNTDF2?A4<L@i0HD]NBMG\NQG@<2NYOF:4E6221>@FDZO87KJL4:DGG@5<NMO87KJ]4:DGV@7e3OXDA-,K_BNH&%RH(+@TOAE- UKD5g=AZFG+.GQLLJ #PJ&%LVIGG/.[IF0b?CTHE)(^SNBD"!VL$'LXKEA),<;?01,3456789:;,}]=a:DQKH&%]VIGG/.[O! V[FJL*);><=>!012345678)zX46H]OL]MGC7<O:1LBI?4I39J47=N9;1B>?5F339J07=N=01BBDZ\T@VF7>OI^h1AXLIPCICJJ0=MWJF@>6BF2:NL2>JHIMOO:6B@CJGG3>JHO@IJ@95CUU37?ISS:=1GYY:;;MWW22=J]QIRSA;4MTZE10=J]QL=96CZXG5`?Hgmg{\n~~g`nb9Nmkiu^lxxeb`=;O27?K7?:=1E=5=;;O0151=I:;8?7C<=359M60033G8>;95A24:7?K4>9=1E>4<;;O0:71=I;;<?7C==759M77>33G9==95A3707?K51;>1EIYY@RJ48JJEKAY=0BBCJRFG2?J703FZ_E@GUE^RQMHOSA_OXSCIL1:R`?U(5889:<<=PL59SEWR4=2ZN^DAK #H\GIM%(::;<= ?01234567(yY+DDIG 42-456789:;<-+n;QKM[GSTAMRi7]GA_CWPJDKB12Z@SEBZTOO5?UUCGGO:7\?4R49QAVCS?2X^BYK\T09P7>UBD<1XDDH[109PLWC@WLR_^LM[_OE@a>UOZLMTAD@PSHXF2>UH][IN:6][AUWP7>RDC:1_HD=4TEM;?QCUE@DJ@>5[IF:8PLKB[YOH?6ZBS69WJHYIM]30X^QK_UM\N==S[V@TOAE6;UQ\NZRHWM30X^QZ_UM\N<=S[V_TXBQZ4:VZT@033\:$YRGLOO-J[\CTWKYHMC Z_CQ,MZSTMVYDJYL\C@L\AT6)AV_XIRV\T^V@OZQHZBKYCX@K_DS2*PYNKFDTN^MNN^@VBB)RWK_MK>j4U1-V[LEHF&CTUH]PBRABJ+SXJZ%BS[8!IR[M*LYR[LUXCKZMSBCM[@W7&\UI_?84U1-V[LEHF&CTUH]PBRABJ+SXJZ%bH_MD_MM@EI4e3\:$YRGLOO-V[FKC'NU_M_IJTZ33Y+OXFL:%YRZNRFGW6g=R8&_TENAA/T]@IA)@W]KYKHZT10_-MZHB8'_TXL\HEU0a?P6(]VCHCC!Z_BOG+BYSI[MNXV?=]/K\J@6)]V^J^JK[2c9V4*SXAJEE#XQLME-D[QGUOL^P=>S!I^LF4+SX\HXLIY<m;T2,QZODGG%^SNCK/F]WEWAB\R;?Q#GPND2-QZRFZNO_>o5Z0.W\MFII'\UHAI!H_UCQC@R\9<W%ERK^0/W\PDT@M]8j7X> U^K@KK)RWJGO#JQ[ASEFP^0Z&@UEI= Z_UCQC@R5i2_;#XQFCNL,QZEJL&MTXL\HEUY4Y+OXFL:%YRZNRFGW6d=R8&_TENAA/T]@IA)@W]KYKHZT8\,J[KC7&\U_M_IJT3c8Q5)RW@IDB"[PCLF,CZRFZNO_W4S!I^LF4+SX\HXLIY<l;T2,QZODGG%^SNCK/T]@KHKFFMUXIA!F4/DJ_5[)]VF^X?j4U1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX55[)]VF^X?j4U1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX54[)]VF^X?j4U1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX57[)]VF^X?j4U1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX56[)]VF^X?j4U1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX51[)]VF^X?j4U1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX50[)]VF^X?m4U1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX5X(RWE__>n5Z0.W\MFII'\UHAI!Z_BMNIDHCWZOG#D:!FHY1Y+SXD\^9o6[?/T]JGJH(]VIFH"[PCNONEKBX[LF$E9 IIZ1^*PYK]]8h7X> U^K@KK)RWJGO#XQLOLOBJAYTME%B8#HF[5_-QZJR\;i0Y=!Z_HALJ*SXKDN$YRM@MLCM@ZUBD&C?"KGT5\,V[ISS:j1^<"[PIBMM+PYDEM%^SNABM@LG[VCK'@>%JDU9]/W\HPR5k2_;#XQFCNL,QZEJL&_TOBCBAOF\W@J(A=$MEV9R.T]OQQ4d3\:$YRGLOO-V[FKC'\UHC@CNNE]PAI)N<'LBW5S!U^NVP7e<]9%^SDM@N.W\GHB(]VIDA@OAD^QFH*O3&OCP5P Z_MWW6f=R8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q;Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR;;Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR;:Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR;9Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR;8Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR;?Q#[PLTV1`>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR;>Q#[PLTV1g>S7'\UBOB@ U^AN@*SXKFXNSDJPSDN,M1(AAR;V"XQCUU0`?P6(]VCHCC!Z_BOG+PYDG[OTEIQ\EM-J0+@NS;W%YRBZT3a8Q5)RW@IDB"[PCLF,QZEHZLUBHR]JL.K7*CO\;T$^SA[[2b9V4*SXAJEE#XQLME-V[FIUMVCOS^KC/H6-BL]3U'_T@XZ=c:W3+PYNKFD$YRMBD.W\GJTBW@NT_HB I5,EM^3Z&\UGYY<l;T2,QZODGG%^SNCK/T]@KWCXAMUXIA!F4/DJ_3[)]VF^X?m4U1-V[LEHF&_TO@J U^ALV@YNLVYN@"G;.GKX3X(RWE__>n5Z0.W\MFII'\UHAI!Z_BMQAZOCWZOG#D:!FHY;Y+SXD\^9o6[?/T]JGJH(]VIFH"[PCNPF[LBX[LF$E9 IIZ;^*PYK]];<7X> U^K@KK)RWJGO#XQ\EM]m5g=R8&_TENAA/T]@IA)RW]KYKHZPCD35?P6(]VCHCC!Z_BOG+lUBDVd:n6[?/T]JGJH(]VIFH"g[ASEFP97768h0Y=!Z_HALJ*SXKDN$eYO]GDV?5486i2_;#XQFCNL,QZEJL&c_M_IJT=:=5d=R8&_TENAA/T]@IA)n\HXLIY26>0c8Q5)RW@IDB"[PCLF,mQGUOL^TOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_5[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX4X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY24X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY24X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY25X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY25X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY26X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY26X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY27X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY27X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY20X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY20X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY21X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY21X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY2Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ3^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\8T$MSNCK[3_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]7U'LTO@JT2\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^6Z&OUHAIU<]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV=R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX4X(AWJGOW9S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY3Y+@XKDNP8P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ2^*CYDEMQ>Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[1_-BZEJLR?V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T0\,E[FKCS?W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\>T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V>R.G]@IA]0U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^1Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_=[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX<X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR:V"KQLMEY:Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ;^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[1_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]6U'LTO@JT0\,V[IEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>0\,V[MEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>0\,V[IEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>1\,V[MEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>1\,V[IEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>2\,V[MEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>2\,V[IEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>3\,V[MEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>3\,V[IEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>4\,V[MEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>4\,V[IEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>5\,V[MEB:m1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>5\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU>]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_4[)NVIFHV?R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX5X(AWJGOW?S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY2Y+@XKDNP>P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ3^*CYDEMQ8Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[0_-BZEJLR9V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T1\,E[FKCS=W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U>]/D\GHB\<T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V?R.G]@IA]2U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W<S!F^AN@^3Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP=P I_BOG_3[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ:Q#HPCLFX2X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR;V"KQLMEY4Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS8W%JRMBDZ5^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[9_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]6U'LTO@JT8\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU6]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_4[)NVIFHV7R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW=S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY1Y+@XKDNP<P Z_MAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:<P Z_IAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:<P Z_MAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:=P Z_IAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:=P Z_MAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:>P Z_IAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:>P Z_MAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:?P Z_IAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:?P Z_MAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:8P Z_IAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:8P Z_MAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:9P Z_IAF6a=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:9P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ:Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[3_-BZEJLR;V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T2\,E[FKCS;W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U=]/D\GHB\:T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V<R.G]@IA]4U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W?S!F^AN@^5Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP>P I_BOG_1[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ9Q#HPCLFX0X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR8V"KQLMEY6Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS;W%JRMBDZ7^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\:T$MSNCK[7_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]5U'LTO@JT6\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^4Z&OUHAIU8]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_7[)NVIFHV9R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW5S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY1Y+@XKDNP4P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ2Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[3_-BZEJLR3V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS9W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U<]/D\GHB\8T$^SAMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]68T$^SEMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]68T$^SAMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]69T$^SEMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]69T$^SAMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]6:T$^SEMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]6:T$^SAMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]6;T$^SEMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]6;T$^SAMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]6<T$^SEMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]6<T$^SAMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]6=T$^SEMJ2e9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]6=T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]6U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W>S!F^AN@^7Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP?P I_BOG_7[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ8Q#HPCLFX6X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR9V"KQLMEY0Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS:W%JRMBDZ1^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\;T$MSNCK[5_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]4U'LTO@JT4\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^5Z&OUHAIU:]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_6[)NVIFHV;R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX7X(AWJGOW;S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY0Y+@XKDNP:P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ1^*CYDEMQ<Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[2_-BZEJLR=V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS1W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U<]/D\GHB\0T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]>U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W>S!F^AN@^?Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP8P I_BOG_5[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ?Q#HPCLFX4X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY24X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY24X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY25X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY25X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY26X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY26X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY27X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY27X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY20X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY20X(RWEIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY21X(RWAIN>i5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY21X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY2Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS=W%JRMBDZ3^*PYKKL8h7X> U^K@KK)RWJ^Y@RAZT.D\JFV\<T$MSNCK[3_-QZNDM;i0Y=!Z_HALJ*SXK]XGSB[[/G]MGU]3U'LTO@JT2\,V[IEB:j1^<"[PIBMM+PYD\[FTCXZ F^L@T^2Z&OUHAIU<]/W\LFC5k2_;#XQFCNL,QZESZEUDYY!I_OAS_1[)NVIFHV=R.T]OG@4d3\:$YRGLOO-V[FRUDVE^X"HPNBRX0X(AWJGOW9S!U^J@A7e<]9%^SDM@N.W\GQTKWF__#KQACQY7Y+@XKDNP8P Z_MAF6f=R8&_TENAA/T]@PWJXG\^$JR@LPZ6^*CYDEMQ>Q#[PHBG1g>S7'\UBOB@ U^AWVIYH]]%MSCM_[5_-BZEJLR?V"XQCCD0`?P6(]VCHCC!Z_BVQHZIR\&LTBN^T4\,E[FKCS?W%YRFLE3a8Q5)RW@IDB"[PCUPO[JSS'OUEO]U;]/D\GHB\>T$^SAMJ2b9V4*SXAJEE#XQLTSN\KPR(NVDH\V:R.G]@IA]0U'_TDNK=c:W3+PYNKFD$YRM[RM]LQQ)AWGI[W9S!F^AN@^1Z&\UGOH<l;T2,QZODGG%^SNZ]L^MVP*@XFJZP8P I_BOG_=[)]VBHI?m4U1-V[LEHF&_TOY\C_NWW+CYIKYQ?Q#HPCLFX<X(RWEIN>n5Z0.W\MFII'\UHX_BPOTV,BZHDXR>V"KQLMEY:Y+SX@JO9o6[?/T]JGJH(]VI_^AQ@UU-E[KEWS=W%JRMBDZ;^*PYKKL;n7X> U^K@KK)RWJ^Y@RAZT.W\GHB@ZY::i6[?/T]JGJH(]VI_^AQ@UU-V[FKCO[Z:><5Z0.W\MFII'\UHX_BPOTV,QZBF\HU]MAGK299V4*SXAJEE#XQLTSN\KPR(aJEFAL@K_FPS[VCK494946[?/T]JGJH(]VI_^AQ@UU-jGJKJIGNTK_^PSDN?5;473\:$YRGLOO-V[FRUDVE^X"gKAUC\RDJNL;;0Y=!Z_HALJ*SX[]K_#KQ\T@VX4X(RWZ^JX??4U1-V[LEHF&_T_YO[/G]PPDR\9T$^S^ZNT338Q5)RW@IDB"[PSUCW+CYT\H^P>P Z_RVBP77<]9%^SDM@N.W\WQGS'OUXXLZT3\,V[VRF\8k0Y=!Z_HALJ*SX[]K_#XQLMEEQT57c3\:$YRGLOO-V[VRF\&_THLZN_WCOMA7f3\:$YRGLOO-V[VRF\&_T_YO[CLF2g>S7'\UBOB@ U^QWEQ)RWZ^JXNCK_o02?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/BK?5;463\:$YRGLOO-V[VRF\&_T_YO[_BLW+FO;:78:7X> U^K@KK)RWZ^JX"[PSUCW[FHS'JC7?3<>;T2,QZODGG%^S^ZNT.W\WQGSWJD_#NG34?02?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/BK?1;473\:$YRGLOO-V[VRF\&_T_YO[_BLW+A:76;:0Y=!Z_HALJ*SX[]K_#XQ\T@V\GKR(L5;5>=5Z0.W\MFII'\UXXLZ U^QWEQYDF]%O0?0=0:W3+PYNKFD$YR][AU-V[VRF\VIEX"J33?03?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/E>7:76<]9%^SDM@N.W\WQGS'\UXXLZPCOV,@939:j1^<"[PIBMM+PYT\H^$YR][AU]@JQ)@S9W%KcF!U^OV\F_5?2_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\8T$^SKJ]E348Q5)RW@IDB"[PSUCW+PYT\H^TOCZ GZ2^*PYK]]837X> U^K@KK)RWZ^JX"[PSUCW[FHS'NQ;Q#[PXNP@]7e<]9%^SDM@N.W\WQGS'\UXXLZPCOV,C^7Z&NdC"XQBUYAZ62=R8&_TENAA/T]PPDR(]VY_MYQLNU-D_4[)]VLO^H<9;T2,QZODGG%^S^ZNT.W\WQGSWJD_#JU>]/W\HPR502_;#XQFCNL,QZUSI]%^S^ZNT^AMP*A\9T$^SUA]CX0`?P6(]VCHCC!Z_RVBP*SX[]K_SN@[/FY1Y+Ai@'_TAXVLY358Q5)RW@IDB"[PSUCW+PYT\H^TOCZ GZ0^*PYAL[O9:6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&MP>P Z_MWW6==R8&_TENAA/T]PPDR(]VY_MYQLNU-D_7[)]VRD^NW=c:W3+PYNKFD$YR][AU-V[VRF\VIEX"IT3\,DjM(RWD_SOT<8;T2,QZODGG%^S^ZNT.W\WQGSWJD_#JU<]/W\BATB:?1^<"[PIBMM+PYT\H^$YR][AU]@JQ)@S:W%YRBZT3:8Q5)RW@IDB"[PSUCW+PYT\H^TOCZ GZ1^*PY_G[IR>n5Z0.W\MFII'\UXXLZ U^QWEQYDF]%LW9S!GoJ-QZKRPJS9;6[?/T]JGJH(]VY_MY!Z_RVBPZEI\&MP8P Z_GFQA70<]9%^SDM@N.W\WQGS'\UXXLZPCOV,C^2Z&\UGYY<7;T2,QZODGG%^S^ZNT.W\WQGSWJD_#JU;]/W\\JTDQ;=0Y=!Z_HALJ*SX[]K_#XQ\T@V\GKR(OR?V"XQIDSG12>S7'\UBOB@ U^QWEQ)RWZ^JXRMAT.EX1X(RWE__>55Z0.W\MFII'\UXXLZ U^QWEQYDF]%LW8S!U^ZLVF_582_;#XQFCNL,QZUSI]%^S^ZNT^AMP*U;878;7X> U^K@KK)RWZ^JX"[PSUCW[FHS'Z6:2?>4U1-V[LEHF&_T_YO[/T]PPDRXKG^$_1<1219V4*SXAJEE#XQ\T@V,QZUSI]UHBY!\<2<14>S7'\UBOB@ U^QWEQ)RWZ^JXRMAT.Q?0;473\:$YRGLOO-V[VRF\&_T_YO[_BLW+V:268i0Y=!Z_HALJ*SX[]K_#XQ\T@V\LLAO9k1^<"[PIBMM+PYT\H^$YR][AU]OKR713\:$YRGLOO-V[VRF\&_TXIA>b:W3+PYNKFD$YR][AU-V[QBHWgosx<k4U1-V[LEHF&_T_YO[/hAN@ZAUX9UXIA?l;T2,QZODGG%^S^ZNT.kGEQGX^HFBH<74U1-V[LEHF&_T_YO[/hQWEQ:76830Y=!Z_HALJ*SX[]K_#d][AU>2:4?<]9%^SDM@N.W\WQGS'`Y_MY2=>0;8Q5)RW@IDB"[PSUCW+lUSI]682<m4U1-V[LEHF&_T_YO[/hQWEQEJLVIN=h5Z0.W\MFII'\UXXLZ iRVBPFKCWJOTb<j4U1-V[LEHF&_T_YO[/hQWEQYDF]6;2<j4U1-V[LEHF&_T_YO[/hQWEQYDF]6:2<j4U1-V[LEHF&_T_YO[/hQWEQYDF]692<j4U1-V[LEHF&_T_YO[/hQWEQYDF]682<j4U1-V[LEHF&_T_YO[/hQWEQYDF]6?2<j4U1-V[LEHF&_T_YO[/hQWEQYDF]6>2<l4U1-V[LEHF&_T_YO[/hQWEQYOANB:m6[?/T]JGJH(]VY_MY!fSUCW[IIP9h1^<"[PIBMM+PYT\H^$eYJ@_og{p7d<]9%^SDM@N.W\W\HD'NUXUCMPWNPG_5[)AVDN<#[PFEP1f>S7'\UBOB@ U^QZJF)@WZSEORY@REY2Y+OXFL:%YRHKR3`8Q5)RW@IDB"[PSXL@+BYTQGIT[B\K[3_-MZHB8'_TJI\=b:W3+PYNKFD$YR]VNB-D[V_IKV]D^IU<]/K\J@6)]VLO^?l4U1-V[LEHF&_T_T@L/F]P]KEX_FXOW9S!I^LF4+SXNMX9n6[?/T]JGJH(]VYRBN!H_R[MGZQHZMQ>Q#GPND2-QZ@CZ;h0Y=!Z_HALJ*SX[PDH#JQ\YOA\SJTCS?W%ERK^0/W\BAT6j2_;#XQFCNL,QZU^FJ%^SJA[_R[MG4b<]9%^SDM@N.W\W\HD'\ULCYQ\YOA\L4b<]9%^SDM@N.W\W\HD'\ULCYQ\YOA\H41<]9%^SDM@N.W\W\HD'\UXUCM>e:W3+PYNKFD$YR]VNB-V[lBF\HUHAIQa1b9V4*SXAJEE#XQ\YOA,mAGSIVIFHR`>a:W3+PYNKFD$YR]VNB-jCJRX[PDH=k5Z0.W\MFII'\UXUCM iFMW[V_IKVBBKE?j;T2,QZODGG%^S^WAC.kDKQYTQGIT@BY>e:W3+PYNKFD$YR]VNB-jW\HDW^EYH1>11d9V4*SXAJEE#XQ\YOA,mV_IKV]D^I2>>0g8Q5)RW@IDB"[PSXL@+lU^FJU\C_J32?3f?P6(]VCHCC!Z_R[MG*oTQGIT[B\K<2<2a>S7'\UBOB@ U^QZJF)n[PDHSZA]D=6=5`=R8&_TENAA/T]P]KE(aZSEORY@RE>6:4c<]9%^SDM@N.W\W\HD'`YRBNQXOSF?2;743\:$YRGLOO-V[QBNW{ol?=5Z0.W\MFII'\U_HBQBUY-V[FUXE\R$E9 Z_LW[53)Je|rTC?=<2:W3+PYNKFD$YRZKO^OV\*SXKZUFYU!F4/W\IP^6>&GfyuQ@22]E77=R8&_TENAA/T]W@JYJ]Q%^SN]PMTZ,M1(RWD_S=;!Bmtz\K75XO890Y=!Z_HALJ*SX\MET~hi>5:W3+PYNKFD$YRgKAUC\GHB6?2_;#XQFCNL,QZoCI]KTO@JPn008Q5)RW@IDB"[PiRGO[k7>3\:$YRGLOO-jGJKJIGNTK_^30?3:?P6(]VCHCC!fCNONEKBXO[Z7=3?6;T2,QZODGG%bOBCBAOF\W@J;87;j7X> U^K@KK)nKFGFMCJPSDN?5586i2_;#XQFCNL,mFIJEHDOS^KC<03=5d=R8&_TENAA/hALIHGILVYN@1?=>0c8Q5)RW@IDB"gLOLOBJAYTME6:?3?n;T2,QZODGG%bOBCBAOF\W@J;9=4:m6[?/T]JGJH(aJEFAL@K_RGO8439901^<"[PIBMM+lEHEDKEHR]JL=3=5<=R8&_TENAA/hALIHGILVYN@1<1189V4*SXAJEE#dM@MLCM@ZUBD595=45Z0.W\MFII'`IDA@OAD^QFH929901^<"[PIBMM+lEHEDKEHR]JL=7=5<=R8&_TENAA/hALIHGILVYN@181189V4*SXAJEE#dM@MLCM@ZUBD5=5=45Z0.W\MFII'`IDA@OAD^QFH9>9901^<"[PIBMM+lEHEDKEHR]JL=;=50=R8&_TENAA/hALV@YNL5:5=85Z0.W\MFII'`ID^HQFD=3=50=R8&_TENAA/hALV@YNL585=85Z0.W\MFII'`ID^HQFD=1=5<=R8&_TENAA/hALV@YNLVYN@1>11`9V4*SXAJEE#dM@RD]J@ZUBD5;>2<74U1-V[LEHF&cHC_KPIE]PAI:66830Y=!Z_HALJ*oDG[OTEIQ\EM>1:4?<]9%^SDM@N.k@KWCXAMUXIA2<>0;8Q5)RW@IDB"gLOSG\MAYTME6?2<=4U1-V[LEHF&cOMYOPCLF21>S7'\UBOB@ iECWEZEJLVdn7X> U^K@KK)n[LF:<6[?/T]JGJH(aZOGSch4U1-V[LEHF&cXUCMj;T2,QZODGG%bXIGj;T2,QZODGG%bXIA>6:W3+PYNKFD$eYJ@_WG@84399:1^<"[PIBMM+lRCGVdntyj4U1-jWMOA\VE^Xh5Z0.kVTAGSMVE^X;5ZPECWAf=R[LXTZD]FBMG6?PYDDB90ZNM6;WKFSZR^XL;o7UGCIOZ.\AD'8';+_Y[M 1,2$DUDA@?0TB\LY79[WQJNJ>1S_YQHNE58\VRX^JIi7UQLOSG\MK@H>2RonRGkf:ZglZVuad\n~~g`n028\akXEh`d~[k}shmm55=_ldUFeca}Vdppmjh43Qy?6Wjs2`8[ZY_DGGTSR>P_^W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^73U'_T@XZ<b:]\[]JIEVUT==QP_T2,QZODGG%^SNZ]L^MVP*@XFJZP=P I_BOG_5[)]VFHI>l4_^][HKKXWV;:SRQZ0.W\MFII'\UHX_BPOTV,BZHDXR8V"KQLMEY3Y+SXDJO8n6QP_YNMIZYX9;UTSX> U^K@KK)RWJ^Y@RAZT.D\JFV\;T$MSNCK[1_-QZJDM:h0SRQWLOO\[Z74WVU^<"[PIBMM+PYD\[FTCXZ F^L@T^2Z&OUHAIU?]/W\HFC4k2UTSUBAM^]\51YXW\:$YRGLOO-V[FRUDVE^X"HPNBRX4X(AWJGOW<>R.T]OG@5d3VUTTA@B_^]21ZYX]9%^SDM@N.W\GQTKWF__#KQACQY3Y+@XKDNP=<S!U^N@A6e<WVUS@CCP_^35[ZYR8&_TENAA/T]@PWJXG\^$JR@LPZ2^*CYDEMQ:>P Z_MAF7f=XWVRGB@QP_05\[ZS7'\UBOB@ U^AWVIYH]]%MSCM_[1_-BZEJLR;8Q#[PLBG0g>YXWQFEARQP19]\[P6(]VCHCC!Z_BVQHZIR\&LTBN^T0\,E[FKCS8>V"XQCCD1`?ZYXPEDFSRQ>9^]\Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\9<W%YRBLE2`8[ZY_DGGTSR?P_^W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^75U'_T@XZ<c:]\[]JIEVUT>=QP_T2,QZODGG%^SNZ]L^MVP*@XFJZP=P I_BOG_46Z&\UGOH=l;^]\\IHJWVU9=RQPU1-V[LEHF&_TOY\C_NWW+CYIKYQ:Q#HPCLFX54[)]VFHI>m4_^][HKKXWV89SRQZ0.W\MFII'\UHX_BPOTV,BZHDXR;V"KQLMEY26X(RWEIN?n5P_^ZOJHYXW;9TSR[?/T]JGJH(]VI_^AQ@UU-E[KEWS8W%JRMBDZ30Y+SXDJO8o6QP_YNMIZYX:=UTSX> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[06^*PYKKL9h7RQPXMLN[ZY5=VUTY=!Z_HALJ*SXK]XGSB[[/G]MGU]6U'LTO@JT14_-QZJDM:i0SRQWLOO\[Z41WVU^<"[PIBMM+PYD\[FTCXZ F^L@T^4Z&OUHAIU>0\,V[IEB;j1TSRVCNL]\[71XWV_;#XQFCNL,QZESZEUDYY!I_OAS_7[)NVIFHV?>]/W\HFC4k2UTSUBAM^]\6=YXW\:$YRGLOO-V[FRUDVE^X"HPNBRX6X(AWJGOW<<R.T]OG@5d3VUTTA@B_^]1=ZYX]9%^SDM@N.W\GQTKWF__#KQACQY1Y+@XKDNP=>S!U^N@A6d<WVUS@CCP_^0\[ZS7'\UBOB@ U^AN@*SXKFGFMCJPSDN,M1(AAR;;Q#[PLTV0g>YXWQFEARQP31]\[P6(]VCHCC!Z_BVQHZIR\&LTBN^T2\,E[FKCS8>V"XQCCD1`?ZYXPEDFSRQ<1^]\Q5)RW@IDB"[PCUPO[JSS'OUEO]U=]/D\GHB\9<W%YRBLE2a8[ZY_DGGTSR==_^]V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]68T$^SAMJ3b9\[Z^KFDUTS>=P_^W3+PYNKFD$YRM[RM]LQQ)AWGI[W>S!F^AN@^76U'_T@NK<c:]\[]JIEVUT?9QP_T2,QZODGG%^SNZ]L^MVP*@XFJZP?P I_BOG_44Z&\UGOH=l;^]\\IHJWVU89RQPU1-V[LEHF&_TOY\C_NWW+CYIKYQ8Q#HPCLFX56[)]VFHI>m4_^][HKKXWV9=SRQZ0.W\MFII'\UHX_BPOTV,BZHDXR9V"KQLMEY20X(RWEIN?n5P_^ZOJHYXW:=TSR[?/T]JGJH(]VI_^AQ@UU-E[KEWS:W%JRMBDZ36Y+SXDJO8o6QP_YNMIZYX;1UTSX> U^K@KK)RWJ^Y@RAZT.D\JFV\<T$MSNCK[02^*PYKKL9h7RQPXMLN[ZY41VUTY=!Z_HALJ*SXK]XGSB[[/G]MGU]3U'LTO@JT10_-QZJDM:k0SRQWLOO\[Z5XWV_;#XQFCNL,QZEJL&_TOB\J_HF\W@J(A=$MEV=R.T]OQQ5d3VUTTA@B_^]74ZYX]9%^SDM@N.W\GQTKWF__#KQACQY7Y+@XKDNP=?S!U^N@A6e<WVUS@CCP_^62[ZYR8&_TENAA/T]@PWJXG\^$JR@LPZ6^*CYDEMQ:?P Z_MAF7f=XWVRGB@QP_50\[ZS7'\UBOB@ U^AWVIYH]]%MSCM_[5_-BZEJLR;?Q#[PLBG0g>YXWQFEARQP42]\[P6(]VCHCC!Z_BVQHZIR\&LTBN^T4\,E[FKCS8?V"XQCCD1a?ZYXPEDFSRQ;4^]\Q5)RW@IDB"[PCUPO[JSS'OUEO]U?]/D\GHB\9T$^SAMJ3c9\[Z^KFDUTS9;P_^W3+PYNKFD$YRM[RM]LQQ)AWGI[W=S!F^AN@^4Z&\UGOH=m;^]\\IHJWVU?:RQPU1-V[LEHF&_TOY\C_NWW+CYIKYQ;Q#HPCLFX7X(RWEIN?o5P_^ZOJHYXW==TSR[?/T]JGJH(]VI_^AQ@UU-E[KEWS9W%JRMBDZ6^*PYKKL9i7RQPXMLN[ZY30VUTY=!Z_HALJ*SXK]XGSB[[/G]MGU]7U'LTO@JT5\,V[IEB;k1TSRVCNL]\[1?XWV_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV8R.T]OG@5f3VUTTA@B_^]7[ZYR8&_TENAA/T]@IA)RWJEYIRGK_RGO+L2)N@Q:Q#[PLTV0f>YXWQFEARQP51]\[P6(]VCHCC!Z_BVQHZIR\&LTBN^T0\,E[FKCS>W%YRBLE2`8[ZY_DGGTSR;>_^]V4*SXAJEE#XQLTSN\KPR(NVDH\V>R.G]@IA]?U'_T@NK<b:]\[]JIEVUT9?QP_T2,QZODGG%^SNZ]L^MVP*@XFJZP<P I_BOG_<[)]VFHI>l4_^][HKKXWV?8SRQZ0.W\MFII'\UHX_BPOTV,BZHDXR;V"KQLMEY2Y+SXDJO8n6QP_YNMIZYX==UTSX> U^K@KK)RWJ^Y@RAZT.D\JFV\9T$MSNCK[3_-QZJDM:h0SRQWLOO\[Z32WVU^<"[PIBMM+PYD\[FTCXZ F^L@T^7Z&OUHAIU<]/W\HFC4j2UTSUBAM^]\13YXW\:$YRGLOO-V[FRUDVE^X"HPNBRX5X(AWJGOW9S!U^N@A6d<WVUS@CCP_^74[ZYR8&_TENAA/T]@PWJXG\^$JR@LPZ3^*CYDEMQ>Q#[PLBG0f>YXWQFEARQP59]\[P6(]VCHCC!Z_BVQHZIR\&LTBN^T1\,E[FKCS?W%YRBLE2`8[ZY_DGGTSR;6_^]V4*SXAJEE#XQLTSN\KPR(NVDH\V?R.G]@IA]0U'_T@NK<a:]\[]JIEVUT9RQPU1-V[LEHF&_TO@J U^ALIHGILVYN@"G;.GKX<X(RWE__?o5P_^ZOJHYXW?:TSR[?/T]JGJH(]VI_^AQ@UU-E[KEWS8W%JRMBDZ:^*PYKKL9i7RQPXMLN[ZY19VUTY=!Z_HALJ*SXK]XGSB[[/G]MGU]6U'LTO@JT9\,V[IEB;k1TSRVCNL]\[34XWV_;#XQFCNL,QZESZEUDYY!I_OAS_7[)NVIFHV?R.T]OG@5e3VUTTA@B_^]57ZYX]9%^SDM@N.W\GQTKWF__#KQACQY1Y+@XKDNP>P Z_MAF7g=XWVRGB@QP_76\[ZS7'\UBOB@ U^AWVIYH]]%MSCM_[3_-BZEJLR9V"XQCCD1a?ZYXPEDFSRQ95^]\Q5)RW@IDB"[PCUPO[JSS'OUEO]U=]/D\GHB\<T$^SAMJ3c9\[Z^KFDUTS;8P_^W3+PYNKFD$YRM[RM]LQQ)AWGI[W?S!F^AN@^3Z&\UGOH=m;^]\\IHJWVU=;RQPU1-V[LEHF&_TOY\C_NWW+CYIKYQ9Q#HPCLFX2X(RWEIN?o5P_^ZOJHYXW?2TSR[?/T]JGJH(]VI_^AQ@UU-E[KEWS;W%JRMBDZ5^*PYKKL9i7RQPXMLN[ZY11VUTY=!Z_HALJ*SXK]XGSB[[/G]MGU]5U'LTO@JT8\,V[IEB;h1TSRVCNL]\[3YXW\:$YRGLOO-V[FKC'\UHC@CNNE]PAI)N<'LBW;S!U^NVP6d<WVUS@CCP_^53[ZYR8&_TENAA/T]@PWJXG\^$JR@LPZ0^*CYDEMQ2Q#[PLBG0f>YXWQFEARQP70]\[P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS8W%YRBLE2`8[ZY_DGGTSR9=_^]V4*SXAJEE#XQLTSN\KPR(NVDH\V=R.G]@IA]5U'_T@NK<b:]\[]JIEVUT;>QP_T2,QZODGG%^SNZ]L^MVP*@XFJZP?P I_BOG_6[)]VFHI>l4_^][HKKXWV=?SRQZ0.W\MFII'\UHX_BPOTV,BZHDXR9V"KQLMEY7Y+SXDJO8n6QP_YNMIZYX?<UTSX> U^K@KK)RWJ^Y@RAZT.D\JFV\;T$MSNCK[4_-QZJDM:h0SRQWLOO\[Z11WVU^<"[PIBMM+PYD\[FTCXZ F^L@T^5Z&OUHAIU9]/W\HFC4j2UTSUBAM^]\32YXW\:$YRGLOO-V[FRUDVE^X"HPNBRX7X(AWJGOW:S!U^N@A6d<WVUS@CCP_^5;[ZYR8&_TENAA/T]@PWJXG\^$JR@LPZ1^*CYDEMQ3Q#[PLBG0f>YXWQFEARQP78]\[P6(]VCHCC!Z_BVQHZIR\&LTBN^T3\,E[FKCS0W%YRBLE2c8[ZY_DGGTSR9P_^W3+PYNKFD$YRMBD.W\GJKJIGNT_HB I5,EM^2Z&\UGYY=m;^]\\IHJWVU3<RQPU1-V[LEHF&_TOY\C_NWW+CYIKYQ?Q#HPCLFX5X(RWEIN?o5P_^ZOJHYXW1;TSR[?/T]JGJH(]VI_^AQ@UU-E[KEWS=W%JRMBDZ0^*PYKKL9i7RQPXMLN[ZY?:VUTY=!Z_HALJ*SXK]XGSB[[/G]MGU]3U'LTO@JT3\,V[IEB;k1TSRVCNL]\[=5XWV_;#XQFCNL,QZESZEUDYY!I_OAS_1[)NVIFHV:R.T]OG@5e3VUTTA@B_^];0ZYX]9%^SDM@N.W\GQTKWF__#KQACQY7Y+@XKDNP9P Z_MAF7g=XWVRGB@QP_97\[ZS7'\UBOB@ U^AWVIYH]]%MSCM_[5_-BZEJLR<V"XQCCD1a?ZYXPEDFSRQ76^]\Q5)RW@IDB"[PCUPO[JSS'OUEO]U;]/D\GHB\?T$^SAMJ3c9\[Z^KFDUTS59P_^W3+PYNKFD$YRM[RM]LQQ)AWGI[W9S!F^AN@^>Z&\UGOH=m;^]\\IHJWVU34RQPU1-V[LEHF&_TOY\C_NWW+CYIKYQ?Q#HPCLFX=X(RWEIN>i5P_^ZOJHYXW13TSR[?/T]JGJH(]VI_^AQ@UU-V[FKCO[Z;?l5P_^ZOJHYXW1UTSX> U^K@KK)RWJGO#XQLOLOBJAYTME%B8#HF[3_-QZJR\::0SRQWLOO\[Z?7WVU^<"[PIBMM+PYD\[FTCXZ U^FBPDYQIECO>l5P_^ZOJHYXW0;TSR[?/T]JGJH(]VYRBN!Z_FMW[V_IK:k0SRQWLOO\[Z?XWV_;#XQFCNL,QZESZEUDYY!I_OAS_5[)NVIFHV>R.T]OG@b<izseoRjjcnffv<=f{pdhS`{we:akmuudgyoTenaa339`llvtkfznSdm`n^t2[50Xi%*Seagax!ALV@&@mgoymya} 06-32=dg|di84cr]nq}><kzUfyu?95:k`kk65>2chcc>#cikswfiwmVchccQy1^25[d*IGGO'BB@J3728mfii8%ice}}loqg\mfiiW;T<;Qn,za\qvcXfl}T|l||es?3(fYkfUge~z2NtoaawYDgg~ycaQ_osvp90=R{lUNtyQMsbcm9cgk{l1^h|PSbcm[Fnfag7^_H\>;DlbficXB}klSO{ig<vqq`=R{lU^bx}jd^@pgdh:nhfxi6[|e^Qlbqdtkhd6jlb|e-a\|acqajomm`gcy<tjvqc>%iTob|j_u{sa87+kVgjfb|Pvdppmjh:9=&hS`gaos]uawungg7< nQmuhng[wcqazcdb0>#c^alv`YjiceyS{k}=0.`[fiumVgbbb|Pvdp>6)eXkfxnS`gaos]bhunfWoy149#c^oecZoc58&hSx}j_cwev86+kVxiR}fm<2/gZstmVydjyl|c`l>4)eXxhxSdjloeg\v`an{}oy1="l_tqf[orfoVh~jj3>,b]mqhYdgg~ycaQosvp90*dW|ynSnaatsmo487+kVxiRm`nuplh4;6$jU~hQloovqki4:9%iTy~kPcnlwvjj458&hSx}j_bmmpwik<4;'oR{|e^aljqthd<7; nQzsd]`kkruge<6<!mPurg\gjhszff<1="l_tqf[fii|{eg40>#c^wpaZehf}xd`43?,b]vw`Ydgg~yca??=1.`[pubWjeexac10?3(fYr{lUhccz}om3195*dW|ynSnaatsmo56;7$jU~hQloovqki7359&hSx}j_dzw[gudig7; nQzsd]vjpublVhxol`20-a\qvcXpz~TxnePwnphewirfm7: nQjx`osh`Ycmzclb0hnlrg/gZehfz~ymd`{_u{sa8cjjlnoii"l_tqfvZudigUhdlga=0.~57=nkfd;SYGBERRFGZHDNh1bob`Pbrabjc=nkfdTn~mnn^`vbb`<ajeeSnck_eg`kac>3`idbRm`rdf8mfiiWj~y`Raztc9jgjhX{}ky~74ibmm[vik11eknlzimf1?kizHIz3h:5O@y103?@=<3;p_k652e0956b=9:9>89;519`g2~h5l90:7c<k1;48 7eb2;i37p]<d;0g6?74l3;8?8:;5;3;fad<[8;36>:=:0827633<<0:4ojj;R1g>625280:?>;;4482<gc53m98;7>51;3xWc>=:m81=>j51216013=91ho46x[15f94?7=93;:9v]i8;0g6?74l3;8?8:;5;3;fa><,;i<6<?n;W0`b?4|}8886<5z13694>{#9:o1=k5m32594?d328:i6<?:{I0`0>"6=j08?:5U248641=910:57?n:0`9y!4dl398?6*=9;10<>"a?39856*>4b81?!73j38o?6%:c;29 4262<k0b<:?:328?.>6290/=9?57g9m516=:910'l850;&204<f<2d:8=4=0:9(gg<72-;?=7m6;o374?4732!m<7>5$062>`c<f8>;6?>4;*7a>5<#9=;19l5a15294>=,=00;6)?;1;7b?k7383;07&;7:18'517==h1e=9>52:9(12<72-;?=7;n;o374?5<3"?=6=4+15391d=i9=:1865$5483>!7393?j7c?;0;78?.34290/=9?55`9m516=>21 9?4?:%375?3f3g;?<794;*72>5<#9=;19l5a1529<>=,=90;6)?;1;7b?k7383307&:i:18'517==h1e=9>5a:9(0`<72-;?=7;n;o374?d<3">o6=4+15391d=i9=:1o65$4b83>!7393?j7c?;0;f8?.2e290/=9?55`9m516=m21 8l4?:%375?3f3g;?<7h4;*6;>5<#9=;19l5a152955=<#==1<7*>4086e>h6<90:=65$4783>!7393?j7c?;0;31?>-3=3:1(<:>:4c8j42728907&:;:18'517==h1e=9>51598/15=83.:8<4:a:l205<6=21 8?4?:%375?3f3g;?<7?9;:)75?6=,8>:68o4n063>41<3">;6=4+15391d=i9=:1=554+2d94?"6<80>m6`>4182=>=,>;0;6)?;1;7b?k7383;j76%91;29 4262<k0b<:?:0`8?.07290/=9?55`9m516=9j10'8h50;&204<2i2d:8=4>d:9(1`<72-;?=7;n;o374?7b32!>h7>5$062>0g<f8>;6<h4;*77>5<#9=;19l5a152964=<#=31<7*>4086e>h6<909>65$3d83>!7393?j7c?;0;00?>-?83:1(<:>:6d8j4272910':k50;&204<0n2d:8=4>;:)4`?6=,8>:6:h4n063>7=<#>i1<7*>4084b>h6<90876%8b;29 4262>l0b<:?:598/2g=83.:8<48f:l205<232!<47>5$062>2`<f8>;6;54+6594?"6<80<j6`>4184?>-0>3:1(<:>:6d8j4272110':;50;&204<0n2d:8=46;:)40?6=,8>:6:h4n063>d=<#>91<7*>4084b>h6<90i76%82;29 4262>l0b<:?:b98/27=83.:8<48f:l205<c32!<<7>5$062>2`<f8>;6h54+7d94?"6<80<j6`>418e?>-1l3:1(<:>:6d8j42728:07&8l:18'517=?o1e=9>51098/3d=83.:8<48f:l205<6:21 :l4?:%375?1a3g;?<7?<;:)5=?6=,8>:6:h4n063>42<3"<36=4+15393c=i9=:1=854+7594?"6<80<j6`>41822>=,>?0;6)?;1;5e?k7383;<76%95;29 4262>l0b<:?:0:8?.03290/=9?57g9m516=9010'5950;&204<0n2d:8=4>a:9(<3<72-;?=79i;o374?7e32!397>5$062>2`<f8>;6<m4;*:7>5<#9=;1;k5a15295a=<#191<7*>4084b>h6<90:i65$8383>!7393=m7c?;0;3e?>-013:1(<:>:6d8j4272;;07&8j:18'517=?o1e=9>52398/35=83.:8<48f:l205<5;21 m84?:%375?g33g;?<7>4;*c0>5<#9=;1m95a15295>=,i;0;6)?;1;c7?k7383807&o>:18'517=i=1e=9>53:9(e5<72-;?=7o;;o374?2<3"3m6=4+1539e1=i9=:1965$9e83>!7393k?7c?;0;48?.?d290/=9?5a59m516=?21 5o4?:%375?g33g;?<764;*;b>5<#9=;1m95a1529=>=,100;6)?;1;c7?k7383k07&77:18'517=i=1e=9>5b:9(=2<72-;?=7o;;o374?e<3"3=6=4+1539e1=i9=:1h65$9483>!7393k?7c?;0;g8?.?3290/=9?5a59m516=n21 5?4?:%375?g33g;?<7??;:):5?6=,8>:6l:4n063>47<3"3;6=4+1539e1=i9=:1=?54+9d94?"6<80j86`>41827>=,0l0;6)?;1;c7?k7383;?76%7d;29 4262h>0b<:?:078?.>d290/=9?5a59m516=9?10'5l50;&204<f<2d:8=4>7:9(<d<72-;?=7o;;o374?7?32!357>5$062>d2<f8>;6<74;*c`>5<#9=;1m95a15295d=<#hh1<7*>408b0>h6<90:n65$a`83>!7393k?7c?;0;3`?>-f13:1(<:>:`68j42728n07&o7:18'517=i=1e=9>51d98/d1=83.:8<4n4:l205<6n21 5h4?:%375?g33g;?<7<>;:):7?6=,8>:6l:4n063>74<3"236=4+1539e1=i9=:1>>54+bc94?"6<80h56`>4183?>-d03:1(<:>:b;8j4272810'n950;&204<d12d:8=4=;:)`2?6=,8>:6n74n063>6=<#j?1<7*>408`=>h6<90?76%l4;29 4262j30b<:?:498/f4=83.:8<4l9:l205<132!h=7>5$062>f?<f8>;6:54+b294?"6<80h56`>418;?>-en3:1(<:>:b;8j4272010'ok50;&204<d12d:8=4n;:)a`?6=,8>:6n74n063>g=<#ki1<7*>408`=>h6<90h76%mb;29 4262j30b<:?:e98/gg=83.:8<4l9:l205<b32!i57>5$062>f?<f8>;6k54+c594?"6<80h56`>41824>=,j?0;6)?;1;a:?k7383;:76%m5;29 4262j30b<:?:008?.d3290/=9?5c89m516=9:10'o=50;&204<d12d:8=4>4:9(f7<72-;?=7m6;o374?7232!i=7>5$062>f?<f8>;6<84;*`3>5<#9=;1o45a152952=<#hl1<7*>408`=>h6<90:465$ad83>!7393i27c?;0;3:?>-c93:1(<:>:b;8j42728k07&j?:18'517=k01e=9>51c98/f`=83.:8<4l9:l205<6k21 oh4?:%375?e>3g;?<7?k;:)``?6=,8>:6n74n063>4c<3"ih6=4+1539g<=i9=:1=k54+b194?"6<80h56`>41815>=,j10;6)?;1;a:?k73838976%nd;29 4262j30b<:?:318?.ca290/=9?5ed9m516=821 ii4?:%375?cb3g;?<7?4;*g`>5<#9=;1ih5a15296>=,mk0;6)?;1;gf?k7383907&kn:18'517=ml1e=9>54:9(a<<72-;?=7kj;o374?3<3"o<6=4+1539a`=i9=:1:65$e783>!7393on7c?;0;58?.c2290/=9?5ed9m516=021 i94?:%375?cb3g;?<774;*g0>5<#9=;1ih5a1529e>=,m;0;6)?;1;gf?k7383h07&k>:18'517=ml1e=9>5c:9(a5<72-;?=7kj;o374?b<3"nm6=4+1539a`=i9=:1i65$dd83>!7393on7c?;0;d8?.bd290/=9?5ed9m516=9910'il50;&204<bm2d:8=4>1:9(`d<72-;?=7kj;o374?7532!o57>5$062>`c<f8>;6<=4;*f;>5<#9=;1ih5a152951=<#m=1<7*>408fa>h6<90:965$d783>!7393on7c?;0;35?>-c=3:1(<:>:dg8j42728=07&j;:18'517=ml1e=9>51998/a5=83.:8<4je:l205<6121 j;4?:%375?cb3g;?<7?n;:)e1?6=,8>:6hk4n063>4d<3"l?6=4+1539a`=i9=:1=n54+g194?"6<80ni6`>4182`>=,n;0;6)?;1;gf?k7383;n76%i1;29 4262lo0b<:?:0d8?.c?290/=9?5ed9m516=:810'ij50;&204<bm2d:8=4=2:9(`7<72-;?=7kj;o374?4432h9on4?:083>5}#9<i1>n84H3ab?M4d<2e:?n4?::a6fd=83;1<7>t$07`>46f3A8hm6F=c59l55?=831vn<;k:181>5<7s-;>o7<;;I0`e>N5k=1/=>l53518k45f2900e<>m:188yg72m3:1n7>50z&21f<5;2B9ol5G2b68j473281/jo4ie:m20d<722e:9=4?::m20c<722e:8:4?::m1g6<722e:8;4?::m20<<722c:9<4?::m13?6=3f;>97>5;nd`>5<<uk82m7>52;294~"6=j0:=>5G2bc8L7e33-;8n7=;3:k24g<722e:?l4?::a6<d=8381<7>t$07`>4743A8hm6F=c59'56d=;=90e<>m:188k45f2900qo<68;290?6=8r.:9n4>009K6fg<@;i?7)?<b;177>"69;087d<9:188m7>=831bj44?::m201<722wi>4:50;694?6|,8?h6<>>;I0`e>N5k=1/=>l53518 4752:1b>;4?::k1<?6=3`l26=44o067>5<<uk8257>54;294~"6=j0mj6F=c`9K6f2<,89i6>:<;%326?5<a;<1<75f3b83>>oa13:17b?;4;29?xd60h0;6?4?:1y'50e=9890D?mn;I0`0>"6;k088>5f11`94?=h9:k1<75rb0:a>5<4290;w)?:c;32g>N5kh1C>n:4$01a>6243-;:>7?l;%376?55m2c:<n4?::k24a<722e:?l4?::a530=83?1<7>t$07`>4673A8hm6F=c59'56d=;=90(<?=:29j63<722c947>5;h1`>5<<ao31<75`15694?=zj8<<6=4::183!72k3;;<6F=c`9K6f2<,89i6>:<;%326?5<a;<1<75f2983>>o4k3:17dh6:188k4232900qo?98;291?6=8r.:9n4>019K6fg<@;i?7)?<b;177>"69;087d<9:188m7>=831b?n4?::ke=?6=3f;?87>5;|`22<<72<0;6=u+14a9556<@;ij7E<l4:&27g<4<:1/=<<53:k12?6=3`836=44i2a94?=nn00;66a>4583>>{e9?:1<7;50;2x 43d28:;7E<la:J1g1=#9:h1?9=4$031>6=n:?0;66g=8;29?l5d2900ek750;9l512=831vn<8>:186>5<7s-;>o7??0:J1gd=O:j>0(<=m:260?!76:390e?850;9j6=<722c8o7>5;hd:>5<<g8>?6=44}c356?6==3:1<v*>5b8245=O:jk0D?m;;%30f?53;2.:=?4<;h05>5<<a;21<75f3b83>>oa13:17b?;4;29?xd6>:0;684?:1y'50e=99:0D?mn;I0`0>"6;k088>5+10097>o5>3:17d<7:188m6e=831bj44?::m201<722wi=;:50;794?6|,8?h6<>?;I0`e>N5k=1/=>l53518 4752:1b>;4?::k1<?6=3`9h6=44ig;94?=h9=>1<75rb046>5<2290;w)?:c;334>N5kh1C>n:4$01a>6243-;:>7=4i3494?=n:10;66g<c;29?l`>2900c<:;:188yg7083:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;09h95f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj8<m6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?7c3-;?>7<k4:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi=;k50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 47528?0(<:=:3fe?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl>6e83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881=?5+15096a`<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c35g?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4>0:&207<5mh1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f40e290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;d8 4252;oj7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd6?00;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+1009a>"6<;08<o5f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj8=36=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?e<,8>96>>m;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th:;:4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=j2.:8?4<179j55e=831b==j50;9j55c=831b==h50;9l56g=831vn<99:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:3k0(<:=:235?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl>7483>0<729q/=8m510f8L7ef3A8h86*>3c8006=#988156*>438064=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb057>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>764$061>6463`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`236<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<57:&207<4:j1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f415290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;48 4252:8h7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd6?80;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+10091>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm17c94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;9695f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj82;6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`23c<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<51e9j55e=831b==j50;9j55c=831b==h50;9l56g=831vn<9j:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:3;>7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd6?m0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100957=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb05`>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7??;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th:;o4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=n2c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a5=?=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:d9j55e=831b==j50;9j55c=831b==h50;9l56g=831vn<67:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:3i0e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg7??3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>138a?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl>8783>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881m6g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e91?1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031><=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb0:7>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>764$061>7`23`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`2<6<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<57:&207<5n<1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f4>5290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;48 4252::;7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd6080;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+10091>"6<;08<=5f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj8=j6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?2<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c3:6?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4=1:&207<4:o1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f4?4290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;02?!73:399j6g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e9h:1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031>77<,8>96?hn;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th:m<4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=:81/=9<52gc8m46d2900e<>k:188m46b2900e<>i:188k45f2900qo?n2;291?6=8r.:9n4>1e9K6fg<@;i?7)?<b;177>"69;09=6*>4381bg=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb0c0>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7<>;%376?4aj2c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a5d2=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338 4252;lh7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd6i<0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100964=#9=81>km4i02`>5<<a8:o6=44i02f>5<<a8:m6=44o01b>5<<uk;j:7>55;294~"6=j0:=i5G2bc8L7e33-;8n7=;3:&257<592.:8?4=fe9j55e=831b==j50;9j55c=831b==h50;9l56g=831vn<o8:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:38:7)?;2;0e`>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm1`:94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;96??4$061>7`b3`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`2e<<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5209'514=:oo0e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg7fi3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;09jk5f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj8ki6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463-;?>7<if:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi=lm50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 4752;;0(<:=:222?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl>ae83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881><5+1509757<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c3ba?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4=1:&207<48;1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f4ga290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;02?!73:39;>6g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e9k:1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031>77<,8>96>><;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th:n<4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=:81/=9<53118m46d2900e<>k:188m46b2900e<>i:188k45f2900qo?64;291?6=8r.:9n4>1e9K6fg<@;i?7)?<b;177>"69;09=6*>4381`<=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb0;6>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7<>;%376?4c12c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a5<0=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338 4252;nj7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd61>0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100964=#9=81>io4i02`>5<<a8:o6=44i02f>5<<a8:m6=44o01b>5<<uk;247>55;294~"6=j0:=i5G2bc8L7e33-;8n7=;3:&257<592.:8?4=dc9j55e=831b==j50;9j55c=831b==h50;9l56g=831vn<76:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:38:7)?;2;0gf>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm18c94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;96??4$061>7bd3`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`2=g<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5209'514=:mi0e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg7>k3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;09hi5f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj83o6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463-;?>7<kd:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi=4k50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 4752;;0(<:=:3ff?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl>9g83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881><5+15096ac<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c3a6?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4=1:&207<5l<1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f4d4290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;02?!73:38o96g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e9j:1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031>77<,8>96>>;;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th:o<4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=:81/=9<53168m46d2900e<>k:188m46b2900e<>i:188k45f2900qo?l2;291?6=8r.:9n4>1e9K6fg<@;i?7)?<b;177>"69;09=6*>438040=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb0a0>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7<>;%376?57=2c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a5f2=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338 4252::=7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd6k<0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100964=#9=81?=84i02`>5<<a8:o6=44i02f>5<<a8:m6=44o01b>5<<uk;h:7>55;294~"6=j0:=i5G2bc8L7e33-;8n7=;3:&257<592.:8?4<069j55e=831b==j50;9j55c=831b==h50;9l56g=831vn<m8:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:38:7)?;2;133>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm1b:94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;96??4$061>66?3`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`2g<<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5209'514=;920e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg7di3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;08<45f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj8ii6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463-;?>7=?9:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi=nm50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 4752;;0(<:=:22b?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl>ce83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881><5+150975g<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c3`a?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4=1:&207<48j1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f4ea290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;02?!73:39;o6g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e9m:1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031>77<,8>96>>k;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th:h<4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=:81/=9<531f8m46d2900e<>k:188m46b2900e<>i:188k45f2900qo?m4;291?6=8r.:9n4>1e9K6fg<@;i?7)?<b;177>"69;09=6*>4381a5=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb0`6>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7<>;%376?4b82c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a5g0=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338 4252;o:7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd6j>0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100964=#9=81>h?4i02`>5<<a8:o6=44i02f>5<<a8:m6=44o01b>5<<uk;i47>55;294~"6=j0:=i5G2bc8L7e33-;8n7=;3:&257<592.:8?4=e39j55e=831b==j50;9j55c=831b==h50;9l56g=831vn<l6:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:38:7)?;2;0f6>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm1cc94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;96??4$061>7c43`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`2fg<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5209'514=:l90e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg7ek3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;09i95f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj8ho6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463-;?>7<j4:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi=ok50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 4752;;0(<:=:3g6?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl>bg83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881><5+15096`3<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c3g6?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4=1:&207<5l?1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f4b4290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;02?!73:38o:6g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e9l:1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031>77<,8>96>>j;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th:i<4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=:81/=9<531g8m46d2900e<>k:188m46b2900e<>i:188k45f2900qo?j2;291?6=8r.:9n4>1e9K6fg<@;i?7)?<b;177>"69;09=6*>43804c=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb0g0>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7<>;%376?57n2c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a5`2=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338 4252:;;7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd6m<0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100964=#9=81?<>4i02`>5<<a8:o6=44i02f>5<<a8:m6=44o01b>5<<uk;n:7>55;294~"6=j0:=i5G2bc8L7e33-;8n7=;3:&257<592.:8?4<109j55e=831b==j50;9j55c=831b==h50;9l56g=831vn<k8:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:38:7)?;2;125>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm1d:94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;96??4$061>6753`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`2a<<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5209'514=;880e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg7bi3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;08=>5f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj8oi6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463-;?>7=>3:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi=hm50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 4752;;0(<:=:237?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl>ee83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881><5+1509742<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c3fa?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4=1:&207<49<1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f4ca290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;02?!73:39:96g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e9o:1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031>77<,8>96>?8;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th:j<4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=:81/=9<53058m46d2900e<>k:188m46b2900e<>i:188k45f2900qo?k4;291?6=8r.:9n4>1e9K6fg<@;i?7)?<b;177>"69;09=6*>4381a3=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb0f6>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7<>;%376?4b>2c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a5a0=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338 4252;o<7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd6l>0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100964=#9=81>h94i02`>5<<a8:o6=44i02f>5<<a8:m6=44o01b>5<<uk;o47>55;294~"6=j0:=i5G2bc8L7e33-;8n7=;3:&257<592.:8?4=e99j55e=831b==j50;9j55c=831b==h50;9l56g=831vn<j6:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:38:7)?;2;0f<>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm1ec94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;96??4$061>7c>3`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`2`g<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5209'514=:l30e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg7ck3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;09io5f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj8no6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463-;?>7<jb:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi=ik50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 4752;;0(<:=:3g`?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl>dg83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881><5+15096`e<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c3e6?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4=1:&207<5l>1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f4`4290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;02?!73:38o;6g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e:9:1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031>77<,8>96>?7;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th9<<4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=:81/=9<530:8m46d2900e<>k:188m46b2900e<>i:188k45f2900qo<?2;291?6=8r.:9n4>1e9K6fg<@;i?7)?<b;177>"69;09=6*>43805<=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb320>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7<>;%376?5612c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a652=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338 4252:;j7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd58<0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100964=#9=81?<o4i02`>5<<a8:o6=44i02f>5<<a8:m6=44o01b>5<<uk8;:7>55;294~"6=j0:=i5G2bc8L7e33-;8n7=;3:&257<592.:8?4<1c9j55e=831b==j50;9j55c=831b==h50;9l56g=831vn?>8:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:38:7)?;2;12f>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm21:94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;96??4$061>67d3`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`14<<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5209'514=;8i0e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg47i3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;08=i5f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj;:i6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463-;?>7=>d:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi>=m50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 4752;;0(<:=:23f?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl=0e83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881><5+150974c<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c03a?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4=1:&207<49o1b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f76a290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;02?!73:39:j6g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e:8:1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031>77<,8>96><?;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th9=<4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=:81/=9<53328m46d2900e<>k:188m46b2900e<>i:188k45f2900qo?i4;291?6=8r.:9n4>1e9K6fg<@;i?7)?<b;177>"69;09=6*>4381aa=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb0d6>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7<>;%376?4bl2c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a5c0=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338 4252;on7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd6n>0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100964=#9=81>hk4i02`>5<<a8:o6=44i02f>5<<a8:m6=44o01b>5<<uk;m47>55;294~"6=j0:=i5G2bc8L7e33-;8n7=;3:&257<592.:8?4=eg9j55e=831b==j50;9j55c=831b==h50;9l56g=831vn<h6:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:38:7)?;2;0fb>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm1gc94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;96??4$061>7`73`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`2bg<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5209'514=:o:0e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg7ak3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;09j<5f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj8lo6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463-;?>7<i1:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi=kk50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 4752;;0(<:=:3d1?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl>fg83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881><5+15096c4<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c026?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4=1:&207<5l11b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f774290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;02?!73:38o46g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e:;:1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031>77<,8>96><=;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th9><4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=:81/=9<53308m46d2900e<>k:188m46b2900e<>i:188k45f2900qo<=2;291?6=8r.:9n4>1e9K6fg<@;i?7)?<b;177>"69;09=6*>438066=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb300>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7<>;%376?55;2c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a672=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338 4252:8?7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd5:<0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100964=#9=81??:4i02`>5<<a8:o6=44i02f>5<<a8:m6=44o01b>5<<uk89:7>55;294~"6=j0:=i5G2bc8L7e33-;8n7=;3:&257<592.:8?4<249j55e=831b==j50;9j55c=831b==h50;9l56g=831vn?<8:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:38:7)?;2;111>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm23:94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;96??4$061>6413`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`16<<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5209'514=;;<0e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg45i3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;08>:5f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj;8i6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463-;?>7==7:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi>?m50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 4752;;0(<:=:20;?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl=2e83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881><5+150977><a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c01a?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4=1:&207<4:01b==m50;9j55b=831b==k50;9j55`=831d=>o50;9~f74a290>6=4?{%36g?76l2B9ol5G2b68 45e2:>87)?>2;02?!73:39956g>0b83>>o68m0;66g>0d83>>o68o0;66a>3`83>>{e:::1<7;50;2x 43d28;o7E<la:J1g1=#9:h1?9=4$031>77<,8>96><n;h33g?6=3`;;h7>5;h33a?6=3`;;j7>5;n30e?6=3th9?<4?:483>5}#9<i1=<j4H3ab?M4d<2.:?o4<429'544=:81/=9<533c8m46d2900e<>k:188m46b2900e<>i:188k45f2900qo<>4;291?6=8r.:9n4>1e9K6fg<@;i?7)?<b;177>"69;09=6*>4381b6=n99i1<75f11f94?=n99o1<75f11d94?=h9:k1<75rb336>5<2290;w)?:c;32`>N5kh1C>n:4$01a>6243-;:>7<>;%376?4a;2c:<n4?::k24a<722c:<h4?::k24c<722e:?l4?::a640=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338 4252;l?7d??c;29?l77l3:17d??e;29?l77n3:17b?<a;29?xd59>0;684?:1y'50e=98n0D?mn;I0`0>"6;k088>5+100964=#9=81>k:4i02`>5<<a8:o6=44i02f>5<<a8:m6=44o01b>5<<uk8:47>55;294~"6=j0:=i5G2bc8L7e33-;8n7=;3:&257<592.:8?4=f79j55e=831b==j50;9j55c=831b==h50;9l56g=831vn??6:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:38:7)?;2;0e2>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm20c94?3=83:p(<;l:03g?M4di2B9o95+12`9715<,8;96??4$061>7`03`;;o7>5;h33`?6=3`;;i7>5;h33b?6=3f;8m7>5;|`15g<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5209'514=:o=0e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg46k3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>13815>"6<;09j55f11a94?=n99n1<75f11g94?=n99l1<75`12c94?=zj;;o6=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?463-;?>7<i8:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi><k50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 4752;;0(<:=:3d:?l77k3:17d??d;29?l77m3:17d??f;29?j74i3:17pl=1g83>0<729q/=8m510f8L7ef3A8h86*>3c8006=#9881><5+15096c?<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c007?6=;3:1<v*>5b825f=O:jk0D?m;;%30f?53;2.:=?4>4:&207<4:k1b==m50;9j55b=831d=>o50;9~f75529086=4?{%36g?76k2B9ol5G2b68 45e2:>87)?>2;32?!73:399n6g>0b83>>o68m0;66a>3`83>>{e::>1<7=50;2x 43d28;h7E<la:J1g1=#9:h1?9=4$031>76<,8>96><k;h33g?6=3`;;h7>5;n30e?6=3th9:o4?:583>5}#9<i1=??4H3ab?M4d<2.:?o4<429j55e=831b==j50;9j51>=831d=>o50;9~f70>290?6=4?{%36g?7582B9ol5G2b68 45e2:>87d??c;29?l77l3:17d?;8;29?j74i3:17pl=6983>1<729q/=8m51328L7ef3A8h86*>3c8006=n99i1<75f11f94?=n9=21<75`12c94?=zj;936=4::183!72k3;:h6F=c`9K6f2<,89i6>:<;%326?b<a8:h6=44i02g>5<<a8:n6=44i02e>5<<g89j6=44}c00=?6==3:1<v*>5b825a=O:jk0D?m;;%30f?53;2.:=?4id:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi>>o50;794?6|,8?h6<?k;I0`e>N5k=1/=>l53518 47528<0e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg44j3:197>50z&21f<69m1C>no4H3a7?!74j39??6*>1382a>o68j0;66g>0e83>>o68l0;66g>0g83>>i6;h0;66sm22d94?4=83:p(<;l:030?M4di2B9o95+12`9715<a8:i6=44o01b>5<<uk88o7>53;294~"6=j0:=n5G2bc8L7e33-;8n7=;3:&257<692c:<n4?::k24a<722e:?l4?::a66c=83?1<7>t$07`>47c3A8hm6F=c59'56d=;=90(<?=:338m46d2900e<>k:188m46b2900e<>i:188k45f2900qo<<d;297?6=8r.:9n4>1b9K6fg<@;i?7)?<b;177>"69;09<6*>43806a=n99i1<75f11f94?=h9:k1<75rb34b>5<3290;w)?:c;335>N5kh1C>n:4$01a>6243-;:>7=4i3494?=n:10;66gi9;29?j73<3:17pl=4d83>6<729q/=8m52b;8L7ef3A8h86*>3c8006=n:h0;66g>1783>>i6;h0;66sm25`94?2=83:p(<;l:03e?M4di2B9o95+12`9715<a;k1<75ff`83>>o6<10;66a>1683>>{e:<81<7=50;2x 43d2;i27E<la:J1g1=#9:h1?9=4i3c94?=n98<1<75`12c94?=zj;>m6=4;:183!72k3;:j6F=c`9K6f2<,89i6>:<;h0b>5<<aok1<75f15:94?=h98=1<75rb375>5<4290;w)?:c;0`=>N5kh1C>n:4$01a>6243`8j6=44i035>5<<g89j6=44}c067?6=<3:1<v*>5b825c=O:jk0D?m;;%30f?53;2c9m7>5;hdb>5<<a8>36=44o034>5<<uk8>m7>53;294~"6=j09o45G2bc8L7e33-;8n7=;3:k1e?6=3`;::7>5;n30e?6=3th99:4?:583>5}#9<i1=<h4H3ab?M4d<2.:?o4<429j6d<722cmm7>5;h37<?6=3f;:;7>5;|`11`<72:0;6=u+14a96f?<@;ij7E<l4:&27g<4<:1b>l4?::k253<722e:?l4?::a60d=83>1<7>t$07`>47a3A8hm6F=c59'56d=;=90e?o50;9jbd<722c:854?::m252<722wi>;?50;194?6|,8?h6?m6;I0`e>N5k=1/=>l53518m7g=831b=<850;9l56g=831vn?:k:181>5<7s-;>o7?>b:J1gd=O:j>0(<=m:260?!76:3;?7d??c;29?j74i3:17pl=5083>7<729q/=8m510`8L7ef3A8h86*>3c8006=#9881=95f11a94?=h9:k1<75rb376>5<5290;w)?:c;32f>N5kh1C>n:4$01a>6243-;:>7?;;h33g?6=3f;8m7>5;|`11<<72;0;6=u+14a954d<@;ij7E<l4:&27g<4<:1/=<<5159j55e=831d=>o50;9~f73c29096=4?{%36g?76j2B9ol5G2b68 45e2:>87)?>2;37?l77k3:17b?<a;29?xd5>90;6?4?:1y'50e=98h0D?mn;I0`0>"6;k088>5+100951=n99i1<75`12c94?=zj;>h6=4::183!72k3;;?6F=c`9K6f2<,89i6>:<;%326?5<a;<1<75f2983>>oa13:17d?;5;29?j73<3:17pl=5183>0<729q/=8m51118L7ef3A8h86*>3c8006=#9881?6g=6;29?l4?2900ek750;9j513=831d=9:50;9~f733290>6=4?{%36g?77;2B9ol5G2b68 45e2:>87)?>2;18m70=831b>54?::ke=?6=3`;?97>5;n370?6=3th9954?:483>5}#9<i1===4H3ab?M4d<2.:?o4<429'544=;2c9:7>5;h0;>5<<ao31<75f15794?=h9=>1<75rb37`>5<2290;w)?:c;337>N5kh1C>n:4$01a>6243-;:>7=4i3494?=n:10;66gi9;29?l73=3:17b?;4;29?xd5=o0;684?:1y'50e=9990D?mn;I0`0>"6;k088>5+10097>o5>3:17d<7:188mc?=831b=9;50;9l512=831vn?69:186>5<7s-;>o7?>d:J1gd=O:j>0(<=m:260?!76:3o0e<>l:188m46c2900e<>j:188m46a2900c<=n:188yg4?<3:1?7>50z&21f<69j1C>no4H3a7?!74j39??6*>13814>"6<;08>h5f11a94?=n99n1<75`12c94?=zj;236=4=:183!72k3;:?6F=c`9K6f2<,89i6>:<;h33f?6=3f;8m7>5;|`1<0<72<0;6=u+14a954b<@;ij7E<l4:&27g<4<:1/=<<5f:k24f<722c:<i4?::k24`<722c:<k4?::m27d<722wi>5950;794?6|,8?h6<><;I0`e>N5k=1/=>l53518 4752:1b>;4?::k1<?6=3`l26=44i066>5<<g8>?6=44}c04`?6=<3:1<v*>5b8247=O:jk0D?m;;%30f?53;2.:=?4<;h05>5<<ao31<75f15794?=h9=>1<75rb35f>5<3290;w)?:c;336>N5kh1C>n:4$01a>6243-;:>7=4i3494?=nn00;66g>4483>>i6<=0;66sm26d94?2=83:p(<;l:021?M4di2B9o95+12`9715<,8;96>5f2783>>oa13:17d?;5;29?j73<3:17pl=8183>1<729q/=8m51108L7ef3A8h86*>3c8006=#9881?6g=6;29?l`>2900e<:::188k4232900qo<71;290?6=8r.:9n4>039K6fg<@;i?7)?<b;177>"69;087d<9:188mc?=831b=9;50;9l512=831vn?6=:187>5<7s-;>o7??2:J1gd=O:j>0(<=m:260?!76:390e?850;9jb<<722c:884?::m201<722wi>5=50;694?6|,8?h6<>=;I0`e>N5k=1/=>l53518 4752:1b>;4?::ke=?6=3`;?97>5;n370?6=3th9584?:583>5}#9<i1=?<4H3ab?M4d<2c:<n4?::k24a<722c:854?::m27d<722wi>4850;594?6|,8?h6<?j;I0`e>N5k=1/=<<5129j55e=831b==j50;9j55c=831b==h50;9j546=831b=<?50;9l56g=831vn?78:184>5<7s-;>o7?>e:J1gd=O:j>0(<?=:308m46d2900e<>k:188m46b2900e<>i:188m4772900e<?>:188k45f2900qo=<a;294?6=8r.:9n4>559K504<D8??68u+14:956`<,8?j6<>9;%36f?77?2.:944>049'501=99>0qp}:c;296~X2k2795;4>0g9~w=7=838pR5?4=3;5>4773tyj:7>52z\b2>;51>0:<k5rsb`94?4|Vjh01?78:033?xua83:1>vPi0:?1=3<6981v8l50;0xZ0d<583n6<=n;|q6=?6=:rT>563>9b827d=z{<21<7<t^4:894?f289j7p}:7;296~X2?27:554>3`9~w00=838pR884=0;5>45f3ty>97>52z\61>;61=0:?l5rs4194?4|V<901<l?:01b?xu2:3:1>vP:2:?2e`<6;h1v8?50;0xZ07<58kh6<=n;|q64?6=:rT><63>a`827d=z{=l1<7<t^5d894g?289j7p};e;296~X3m27:m;4>3`9~w1b=838pR9j4=0c7>45f3ty?o7>52z\7g>;6i;0:?l5rs5`94?4|V=h01<o?:01b?xu3i3:1>vP;a:?2=7<6;h1v9650;0xZ1><583m6<=n;|q73?6=:rT?;63>9e827d=z{=<1<7<t^54894?e289j7p};5;296~X3=27:544>3`9~w12=838pR9:4=0;4>45f3ty??7>52z\77>;61<0:?l5rs5094?4|V=801<l>:01b?xu393:1>vP;1:?2ec<6;h1v9>50;0xZ16<58ko6<=n;|q0b?6=:rT8j63>ac827d=z{?81<7<t^70894g>289j7p}91;296~X1927:m:4>3`9~w36=838pR;>4=0c6>45f3ty>j7>52z\6b>;6i:0:?l5rs4g94?4|V<o01<o>:01b?xu2l3:1>vP:d:?2=6<6;h1v5>50;0xZ=6<58hn6<=n;|q4a?6=:rT<i63>bb827d=z{>n1<7<t^6f894df289j7p}8c;296~X0k27:n54>3`9~w2d=838pR:l4=0`5>45f3ty<m7>52z\4e>;6j=0:?l5rs6:94?4|V>201<j?:01b?xu0?3:1>vP87:?2g`<6;h1v:850;0xZ20<58ih6<=n;|q41?6=:rT<963>c`827d=z{>>1<7<t^66894e?289j7p}83;296~X0;27:o;4>3`9~w24=838pR:<4=0a7>45f3ty<=7>52z\45>;6k;0:?l5rs6294?4|V>:01<m?:01b?xu1n3:1>vP9f:?2f7<6;h1v;j50;0xZ3b<58hm6<=n;|q5g?6=:rT=o63>be827d=z{?h1<7<t^7`894de289j7p}9a;296~X1i27:n44>3`9~w3?=838pR;74=0`4>45f3ty=47>52z\5<>;6j<0:?l5rs7594?4|V?=01<j>:01b?xu1>3:1>vP96:?2gc<6;h1v;;50;0xZ33<58io6<=n;|q50?6=:rT=863>cc827d=z{1=1<7<t^95894e>289j7p}76;296~X?>27:o:4>3`9~w=3=838pR5;4=0a6>45f3ty387>52z\;0>;6k:0:?l5rs9194?4|V1901<m>:01b?xu?:3:1>vP72:?2f6<6;h1vl;50;0xZd3<58nn6<=n;|qb7?6=:rTj?63>db827d=z{h81<7<t^`0894bf289j7p}n1;296~Xf927:h54>3`9~wd6=838pRl>4=0f5>45f3ty2j7>52z\:b>;6l=0:?l5rs8f94?4|V0n01<h?:01b?xu>k3:1>vP6c:?2a`<6;h1v4l50;0xZ<d<58oh6<=n;|q:e?6=:rT2m63>e`827d=z{031<7<t^8;894c?289j7p}68;296~X>027:i;4>3`9~w<1=838pR494=0g7>45f3ty2:7>52z\:2>;6m;0:?l5rs8794?4|V0?01<k?:01b?xu><3:1>vP64:?2`7<6;h1v4<50;0xZ<4<58nm6<=n;|q:5?6=:rT2=63>de827d=z{0:1<7<t^82894be289j7p}7f;296~X?n27:h44>3`9~w=c=838pR5k4=0f4>45f3ty3h7>52z\;`>;6l<0:?l5rs9a94?4|V1i01<h>:01b?xu?j3:1>vP7b:?2ac<6;h1v5o50;0xZ=g<58oo6<=n;|q;=?6=:rT3563>ec827d=z{hi1<7<t^`a894c>289j7p}nb;296~Xfj27:i:4>3`9~wdg=838pRlo4=0g6>45f3tyj57>52z\b=>;6m:0:?l5rs`:94?4|Vh201<k>:01b?xuf?3:1>vPn7:?2`6<6;h1vno50;0xZfg<58ln6<=n;|q`<?6=:rTh463>fb827d=z{j=1<7<t^b5894`f289j7p}l6;296~Xd>27:j54>3`9~wf3=838pRn;4=0d5>45f3tyh87>52z\`0>;6n=0:?l5rsb094?4|Vj801???:01b?xud93:1>vPl1:?14`<6;h1vn>50;0xZf6<5;:h6<=n;|qab?6=:rTij63=0`827d=z{ko1<7<t^cg8976?289j7p}md;296~Xel279<;4>3`9~wge=838pRom4=327>45f3tyin7>52z\af>;58;0:?l5rscc94?4|Vkk01?>?:01b?xue13:1>vPm9:?2b7<6;h1vo950;0xZg1<58lm6<=n;|qa2?6=:rTi:63>fe827d=z{k?1<7<t^c7894`e289j7p}m4;296~Xe<27:j44>3`9~wg5=838pRo=4=0d4>45f3tyi>7>52z\a6>;6n<0:?l5rsc394?4|Vk;01??>:01b?xue83:1>vPm0:?14c<6;h1vlh50;0xZd`<5;:o6<=n;|qba?6=:rTji63=0c827d=z{m;1<7<t^e38976>289j7p}k0;296~Xc8279<:4>3`9~wf`=838pRnh4=326>45f3tyhi7>52z\`a>;58:0:?l5rsbf94?4|Vjn01?>>:01b?xudk3:1>vPlc:?2b6<6;h1vhh50;0xZ``<5;;n6<=n;|qf`?6=:rTnh63=1b827d=z{li1<7<t^da8977f289j7p}jb;296~Xbj279=54>3`9~w`g=838pRho4=335>45f3tyn57>52z\f=>;59=0:?l5rsd594?4|Vl=01?=?:01b?xub>3:1>vPj6:?16`<6;h1vh;50;0xZ`3<5;8h6<=n;|qf0?6=:rTn863=2`827d=z{l91<7<t^d18974?289j7p}j2;296~Xb:279>;4>3`9~w`7=838pRh?4=307>45f3tyn<7>52z\f4>;5:;0:?l5rsed94?4|Vml01?<?:01b?xucm3:1>vPke:?157<6;h1vim50;0xZae<5;;m6<=n;|qgf?6=:rTon63=1e827d=z{mk1<7<t^ec8977e289j7p}k9;296~Xc1279=44>3`9~wa>=838pRi64=334>45f3tyo;7>52z\g3>;59<0:?l5rse494?4|Vm<01?=>:01b?xuc=3:1>vPk5:?16c<6;h1vi:50;0xZa2<5;8o6<=n;|qg7?6=:rTo?63=2c827d=z{o<1<7<t^g48974>289j7p}i5;296~Xa=279>:4>3`9~wc2=838pRk:4=306>45f3tym?7>52z\e7>;5::0:?l5rsg094?4|Vo801?<>:01b?xua93:1>vPi1:?156<6;h1v<<::18g84dk3;8o63=9581<>;51109463=6`81<>;5=o09463=5b81<>;5=109463=5581<>;5=909463=4b81<>;5<k09m63=4d81e>;50>0m56s|2b094?4|5;326?84=07f>7e43ty9o<4?:5y>5=d=99n01?=;:02g?844l3;;h63>5d820d=z{8?m6=4={<36a?`d34;>h7??b:p6g?=838p1?76:g;897?f289j7p}=bc83>7}::031?n5228`956g<uz8io7>53z?171<68j16>>j511a897>028>?7p}=bd83>7}::021=9:4=07f>4363ty9nk4?:3y>63g=9=>01?78:032?xu51l0;6nu217c956g<5;;86<>k;<026?77l27:j>4>0e9>5c4=99n01<j<:02g?87c:3;;h63>b2824a=:9k81==j4=0;0>46c34;2>7??d:?17`<68m1v?o::18a87093;8m63=20824a=::;:1==j4=322>46c348;<7??d:?2a4<68m16=h>511f894e628:o70?l0;33`>;6i80:<i521`2955b<uz8j:7>5bz?237<6;h16>?=511f8974528:o70<?3;33`>;58;0:<i521d1955b<58o96<>k;<3`7?77l27:o?4>0e9>5d5=99n01<o=:02g?xu5i>0;6ou2161956g<5;8>6<>k;<010?77l279<84>0e9>652=99n01<k::02g?87b<3;;h63>c4824a=:9j>1==j4=0c6>46c34;j87??d:p6d>=83hp1<9;:01b?845?3;;h63=27824a=::9=1==j4=325>46c34;n;7??d:?2a3<68m16=n9511f894e128:o70?n7;33`>;6i?0:<i5rs3c:>5<es4;<97?<a:?16<<68m16>?6511f8976>28:o70<?8;33`>;6m00:<i521d:955b<58i26<>k;<3`<?77l27:m44>0e9>5d>=99n0q~<na;29f~;6??0:?l5223`955b<5;8j6<>k;<03f?77l279<l4>0e9>5`d=99n01<kn:02g?87dj3;;h63>c`824a=:9hh1==j4=0cb>46c3ty9mo4?:cy>521=9:k01?<k:02g?845k3;;h63=0e824a=::9i1==j4=0gg>46c34;no7??d:?2ga<68m16=nm511f894gc28:o70?nc;33`>{t:hi1<7lt=05;>45f3489j7??d:?16`<68m16>=h511f8976b28:o70?jf;33`>;6ml0:<i521bd955b<58in6<>k;<3bb?77l27:mh4>0e9~w7gc290iw0?89;30e>;5;80:<i52222955b<5;;:6<>k;<024?77l27:j<4>0e9>5c6=99n01<j>:02g?87c83;;h63>b0824a=:9k:1==j4}r0:b?6=jr7::o4>3`9>643=99n01??;:02g?87a=3;;h63>f5824a=:9m?1==j4=0f7>46c34;i97??d:?2f1<68m16=4;511f894?328:o7p}=a183>g}:9?i1=>o4=334>46c348::7??d:?2b2<68m16=k8511f894b028:o70?k6;33`>;6j>0:<i521c4955b<583<6<>k;<3:2?77l2wx>l?50;`x940c289j70<>9;33`>;5910:<i521g;955b<58l36<>k;<3g=?77l27:h54>0e9>5g?=99n01<l7:02g?87>13;;h63>99824a=z{;k96=4m{<35a?74i279=o4>0e9>64g=99n01<hm:02g?87ai3;;h63>dc824a=:9mk1==j4=0`a>46c34;im7??d:?2=g<68m16=4o511f8yv4f;3:1nv3>6g827d=::8n1==j4=33`>46c34;mh7??d:?2bf<68m16=ij511f894bd28:o70?md;33`>;6jj0:<i5218f955b<583h6<>k;|q1e1<72kq6=:>512c8977a28:o70<>e;33`>;6no0:<i521gg955b<58nm6<>k;<3ga?77l27:nk4>0e9>5gc=99n01<7i:02g?87>m3;;h6s|2c094?46s4;<m7?<a:?2=c<68l16=4k511g894?c28:n70?6c;33a>;61k0:<h5218c955c<58326<>j;<3:<?77m27:5:4>0d9>5<0=99o01<7::02f?87><3;;i63>b0824`=:9k:1==k4=0ce>46b34;ji7??e:?2ea<68l16=lm511g894ge28:n70?na;33a>;6i00:<h521`:955c<58k<6<>j;<3b2?77m27:m84>0d9>5d2=99o01<o<:02f?87f:3;;i63>a0824`=:9h:1==k4=0;0>46b34;2>7??e:p6g2=838:w0?71;30e>;6jo0:<h521cg955c<58ho6<>j;<3ag?77m27:no4>0d9>5gg=99o01<l6:02f?87e03;;i63>b6824`=:9k<1==k4=0`6>46b34;i87??e:?2`4<68l16=i>511g894ea28:n70?le;33a>;6km0:<h521ba955c<58ii6<>j;<3`e?77m27:o44>0d9>5f>=99o01<m8:02f?87d>3;;i63>c4824`=:9j>1==k4=0a0>46b34;h>7??e:?2g4<68l16=n>511g894d428:n70?m2;33a>{t:k?1<7<>{<3;6?74i27:hk4>0d9>5ac=99o01<jk:02f?87ck3;;i63>dc824`=:9mk1==k4=0f:>46b34;o47??e:?2`2<68l16=i8511g894b228:n70?k4;33a>;6n80:<h521g2955c<58om6<>j;<3fa?77m27:ii4>0d9>5`e=99o01<km:02f?87bi3;;i63>e8824`=:9l21==k4=0g4>46b34;n:7??e:?2a0<68l16=h:511g894c428:n70?j2;33a>;6m80:<h521d2955c<58n86<>j;<3g6?77m2wx>o850;0287?;3;8m63>fg824`=:9oo1==k4=0dg>46b34;mo7??e:?2bg<68l16=ko511g894`>28:n70?i8;33a>;6n>0:<h521g4955c<58l>6<>j;<3e0?77m279=<4>0d9>646=99o01?>i:02f?847m3;;i63=0e824`=::9i1==k4=32a>46b348;m7??e:?14<<68l16>=6511g8976028:n70<?6;33a>;58<0:<h52216955c<5;:86<>j;<036?77m279<<4>0d9>656=99o01<h<:02f?87a:3;;i6s|2c594?46s4;387?<a:?15c<68l16><k511g8977c28:n70<>c;33a>;59k0:<h5220c955c<5;;26<>j;<02<?77m279=:4>0d9>640=99o01??::02f?846<3;;i63=30824`=::::1==k4=30e>46b3489i7??e:?16a<68l16>?m511g8974e28:n70<=a;33a>;5:00:<h5223:955c<5;8<6<>j;<012?77m279>84>0d9>672=99o01?<<:02f?845:3;;i63=20824`=::;:1==k4=330>46b348:>7??e:p6g5=838p1<6?:01b?844m3;;i6s|2`g94?73s4;=>7?;4:?224<a127:;l4>0b9>5=7=99i01<6=:02`?87?;3;;o63>85824f=:91?1==m4=0:5>46d34;3;7??c:?2<=<68j16=57511a8941e28:h70?8c;33g>;6?m0:<n5216g955e<58=m6<>l;<3;4?77k2795;4>0d9>6<1=99o0q~<nf;2956}:9?91=9:4=041>c?<58=j6<>k;<3;5?77l27:4?4>0e9>5=5=99n01<6;:02g?87?=3;;h63>87824a=:91=1==j4=0:;>46c34;357??d:?23g<68m16=:m511f8941c28:o70?8e;33`>;6?o0:<i52192955b<5;3>6<:7;|q1f5<728>p1<8;:067?871;3l270?8a;33a>;6080:<h52190955c<58286<>j;<3;0?77m27:484>0d9>5=0=99o01<68:02f?87?03;;i63>88824`=:9>h1==k4=05`>46b34;<h7??e:?23`<68l16=:h511g894>728:n70<66;33`>;51>0:<n5rs3`2>5<6<r7::84>459>532=n016=:o511d894>628:m70?72;33b>;60:0:<k52196955`<582>6<>i;<3;2?77n27:4:4>0g9>5=>=99l01<66:02e?870j3;;j63>7b824c=:9>n1==h4=05f>46a34;<j7??f:?2<5<68o16>48511a897?028:o7p}=9b83>1}:9?<1=9:4=311>46d3488?7??c:?17f<68j1v?7k:186871?3;?863>678e=>;5;;0:<i52221955b<5;9h6<>k;|q1f=<72=q6>475156897?f28:i70?7b;33g>;5010:<o5rs3a3>5<5s48247h6;<0:1?74i2wx>oo50;1x97?e28:i70?:e;37=>;60h0:<o5rs3`g>5<5s48287h6;<36a?7282wx=5m50;`x94022:i01<8;:2a894042:i01<8=:2a894062:i01<8?:2a8940>2:i01<87:2a894002:i01<89:2a894>f289j7p}>9083>g}:9??1>55217696==:9?91>55217096==:9?;1>55217296==:9?31>55217:96==:9?=1>55217496==:91h1=>o4}r3;b?6=9;q6=;65156894002o301<8n:02`?87093;;o63>73824f=:9>91==m4=057>46d34;<97??c:?233<68j16=:9511a8941?28:h70?89;33g>;6>k0:<n5217a955e<58<o6<>l;<35a?77k27::k4>0b9>526=99i0q~?60;2957}:9?31=9:4=04;>c?<58<j6<>k;<345?77l27:;?4>0e9>525=99n01<9;:02g?870=3;;h63>77824a=:9>=1==j4=05;>46c34;<57??d:?22g<68m16=;m511f8940c28:o70?9e;33`>;6>o0:<i52162955b<uz;3h7>513y>536=9=>01<86:g;8940f28:n70?81;33a>;6?;0:<h52161955c<58=?6<>j;<341?77m27:;;4>0d9>521=99o01<97:02f?87013;;i63>6c824`=:9?i1==k4=04g>46b34;=i7??e:?22c<68l16=:>511g8yv7?m3:1=?u21739512<58<;6k74=04b>46a34;<=7??f:?237<68o16=:=511d8941328:m70?85;33b>;6??0:<k52165955`<58=36<>i;<34=?77n27::o4>0g9>53e=99l01<8k:02e?871m3;;j63>6g824c=:9>:1==h4}r002?6==8q6>>=512c8977b28:m70<>c;33b>;59h0:<k5220:955`<5;;=6<>i;<020?77n279?=4>0g9>67c=99l01?<l:02e?845i3;;j63=29824c=::;<1==h4=307>46a3489>7??f:?165<68o16><<511d894`b28:m70?ic;33b>;6nh0:<k521g:955`<58l=6<>i;<3e0?77n279==4>0g9>65c=99l01?>l:02e?847i3;;j63=09824c=::9<1==h4=327>46a348;>7??f:?145<68o16=k<511d894bb28:m70?kc;33b>;6lh0:<k521e:955`<58n=6<>i;<3g0?77n27:j=4>0g9>5`c=99l01<kl:02e?87bi3;;j63>e9824c=:9l<1==h4=0g7>46a34;n>7??f:?2a5<68o16=i<511d894db28:m70?mc;33b>;6jh0:<k521c:955`<58h=6<>i;<3a0?77n27:h=4>0g9>5fc=99l01<ml:02e?87di3;;j63>c9824c=:9j<1==h4=0a7>46a34;h>7??f:?2g5<68o16=o<511d894?b28:m70?6c;33b>;61h0:<k5218:955`<583=6<>i;<3:0?77n27:n=4>0g9>5dc=99l01<ol:02e?87fi3;;j63>a9824c=:9h<1==h4=0c7>46a34;j>7??f:?2e5<68o16=4<511d8yv44=3:19<u2220956g<5;;m6<>i;<02`?77n279=o4>0g9>64?=99l01??8:02e?846=3;;j63=30824c=::;l1==h4=30g>46a3489n7??f:?16<<68o16>?9511d8974228:m70<=3;33b>;5:80:<k52201955`<58lm6<>i;<3e`?77n27:jo4>0g9>5c?=99l01<h8:02e?87a=3;;j63=10824c=::9l1==h4=32g>46a348;n7??f:?14<<68o16>=9511d8976228:m70<?3;33b>;5880:<k521g1955`<58nm6<>i;<3g`?77n27:ho4>0g9>5a?=99l01<j8:02e?87c=3;;j63>f0824c=:9ll1==h4=0gg>46a34;nn7??f:?2a<<68o16=h9511d894c228:m70?j3;33b>;6m80:<k521e1955`<58hm6<>i;<3a`?77n27:no4>0g9>5g?=99l01<l8:02e?87e=3;;j63>d0824c=:9jl1==h4=0ag>46a34;hn7??f:?2g<<68o16=n9511d894e228:m70?l3;33b>;6k80:<k521c1955`<583m6<>i;<3:`?77n27:5o4>0g9>5<?=99l01<78:02e?87>=3;;j63>b0824c=:9hl1==h4=0cg>46a34;jn7??f:?2e<<68o16=l9511d894g228:m70?n3;33b>;6i80:<k52181955`<uz88;7>5a0y>662=9:k01??i:02`?846m3;;o63=1e824f=::8i1==m4=33a>46d348:m7??c:?15<<68j16><6511a8977028:h70<>6;33g>;59<0:<n52206955e<5;9:6<>l;<004?77k279>k4>0b9>67c=99i01?<k:02`?845k3;;o63=2c824f=::;k1==m4=30:>46d348947??c:?162<68j16>?8511a8974228:h70<=4;33g>;5::0:<n52230955e<5;8:6<>l;<014?77k279=>4>0b9>644=99i01<hi:02`?87am3;;o63>fe824f=:9oi1==m4=0da>46d34;mm7??c:?2b<<68j16=k6511a894`028:h70?i6;33g>;6n<0:<n521g6955e<5;;:6<>l;<024?77k279<k4>0b9>65c=99i01?>k:02`?847k3;;o63=0c824f=::9k1==m4=32:>46d348;47??c:?142<68j16>=8511a8976228:h70<?4;33g>;58:0:<n52210955e<5;::6<>l;<034?77k27:j>4>0b9>5c4=99i01<ji:02`?87cm3;;o63>de824f=:9mi1==m4=0fa>46d34;om7??c:?2`<<68j16=i6511a894b028:h70?k6;33g>;6l<0:<n521e6955e<58l:6<>l;<3e4?77k27:ik4>0b9>5`c=99i01<kk:02`?87bk3;;o63>ec824f=:9lk1==m4=0g:>46d34;n47??c:?2a2<68j16=h8511a894c228:h70?j4;33g>;6m:0:<n521d0955e<58o:6<>l;<3f4?77k27:h>4>0b9>5a4=99i01<li:02`?87em3;;o63>be824f=:9ki1==m4=0`a>46d34;im7??c:?2f<<68j16=o6511a894d028:h70?m6;33g>;6j<0:<n521c6955e<58n:6<>l;<3g4?77k27:ok4>0b9>5fc=99i01<mk:02`?87dk3;;o63>cc824f=:9jk1==m4=0a:>46d34;h47??c:?2g2<68j16=n8511a894e228:h70?l4;33g>;6k:0:<n521b0955e<58i:6<>l;<3`4?77k27:n>4>0b9>5g4=99i01<7i:02`?87>m3;;o63>9e824f=:90i1==m4=0;a>46d34;2m7??c:?2=<<68j16=46511a894?028:h70?66;33g>;61<0:<n52186955e<58h:6<>l;<3a4?77k27:mk4>0b9>5dc=99i01<ok:02`?87fk3;;o63>ac824f=:9hk1==m4=0c:>46d34;j47??c:?2e2<68j16=l8511a894g228:h70?n4;33g>;6i:0:<n521`0955e<58k:6<>l;<3b4?77k27:5>4>0b9>5<4=99i0q~<8c;296~;5>h0m563=6c827d=z{;=i6=4={<05=?74i279:o4>0b9~w71f2909w0<98;30e>;5>k0:<i5rs34f>5<5s48847?<a:?12<<68j1v?8i:18184413;8m63=68824a=z{;=;6=4={<00e?74i279:54>0b9~w7162909w0<<b;30e>;5>10:<i5rs350>5<0s488j7?<a:?11c<6<<16>8m51578973?28>>70<:4;371>;5=90:885225a9513<uz8=o7>52z?17`<68o16>>m512c8yv40:3:1>v3=3d827d=:::l1==l4}r05`?6=:r79?i4>3`9>66c=99i0q~<89;297~;5>k0:855224d9512<5;<;6<>l;|q13=<72=q6>;6515:8970>28>370<:c;370>;5=m0:<n5rs354>5<1s488n7??f:?17d<68o16>>7511d8975?28:m70<:8;370>;5=00:<n5rs355>5<1s488n7??e:?17d<68l16>>7511g8975?28:n70<:4;370>;5=<0:<n5rs356>5<1s488n7??d:?17d<68m16>>7511f8975?28:o70<:0;370>;5=80:<n5rs357>5<1s488n7??c:?17d<68j16>>7511a8975?28:h70<;c;370>;5<m0:<n5rs366>5<5s48?o7h6;<07a?74i2wx>9>50;1x972a2;k01?;=:3c8972e28;<7p}=4783>7}::<:1j452240956g<uz8?=7>53z?116<5i2799;4=a:?10c<69>1v?:8:181842<3l270<:6;30e>{t:=81<7=t=374>7g<5;?j6?o4=370>4703ty9854?:3y>60>=n016>8o512c8yv43;3:1?v3=5c81e>;5=l09m63=568252=z{;>26=4={<06g?`>348>i7?<a:p612=838p1?8>:3c8973e28;<7p}=4`83>7}::<l1j452273956g<uz8=>7>53z?10a<6;h16>9l515:8972b28;=7p}=6283>6}::<;1=>o4=36e>42?348>>7?>6:p632=839p1?;::01b?842;3;?463=578253=z{;<>6=4<{<06=?74i2799:4>499>60g=98<0q~<96;297~;5=m0:?l5224`951><5;?n6<?9;|q122<72;q6>;>512c8970628;=7p}=8b83>7}::1>1==m4=3:5>45f3ty94l4?:3y>6=1=:116>5:512c8yv4?13:15v3=828200=::181=9;4=3:2>4223483<7?;5:?13c<6<<16>:k51578971c28>>70<77;371>;5010:?l5rs3:g>5<5s48<h7?;4:?1<3<68j1v?6j:180840m3;?863=7e8e=>;50?0:<i5rs3:e>5<4s48<j7?;4:?13`<a12794;4>0d9~w7?72908w0<70;370>;5?o0m563=87824c=z{;3:6=4<{<0;5?73<2794=4i9:?1<0<68j1v?7=:18084?:3;?863=808e=>;50<0:<i5rs3:a>5<5s48397?<a:?1<1<68m1v?7<:18084?;3;?863=838e=>;50<0:<h5rs005>5<5s482:7?<a:?1=0<68j1v<<8:18184>?3;8m63=94824a=z{8836=4?{|q26<<729qv<<n:183xu6:k0;6=urs00`>5<7sty:>i4?:1y~w44b290;wp}>2g83>5}z{89;6=4?{|q274<729qv<==:183xu6;:0;6=urs017>5<esW??7S96;_;f?[e4348>n7hn;<063?`f348>?7hn;<07b?`f348?n7hn;<0`f?7712Tn46s|12794??|V=30R;k4^818Zg><58<>6k74=3:0>c?<5;2>6<>i;_fg?84><3;?86s|12494?46sW9n7S8<;_:;?[gc348287<9;<0:<?4134;=97<9;<350?4134;=?7<9;<356?4134;==7<9;<354?4134;=57<9;<35<?4134;=;7<9;<352?41348=m7<9;<06b?41348>o7<9;<06<?41348>87<9;<064?41348?o7<9;<0;7?413483>7<9;<0;5?413483<7<9;<04b?41348<i7<9;<04`?413483;7<9;_f1?872l3;8m6srn7cg>5<6sA8h86sa6`g94?7|@;i?7p`9ag83>4}O:j>0qc8m0;295~N5k=1vb;l>:182M4d<2we:o<50;3xL7e33td=n>4?:0yK6f2<ug<i87>51zJ1g1=zf?h>6=4>{I0`0>{i>k<1<7?tH3a7?xh1j>0;6<uG2b68yk0e03:1=vF=c59~j3d>290:wE<l4:m2gg=83;pD?m;;|l5fg<728qC>n:4}o4ag?6=9rB9o95rn7`g>5<6sA8h86sa6cg94?7|@;i?7p`9bg83>4}O:j>0qc8l0;295~N5k=1vb;m>:182M4d<2we:n<50;3xL7e33td=o>4?:0yK6f2<ug<h87>51zJ1g1=zf?i>6=4>{I0`0>{i>j<1<7?tH3a7?xh1k>0;6<uG2b68yk0d03:1=vF=c59~j3e>290:wE<l4:m2fg=83;pD?m;;|l5gg<728qC>n:4}o4`g?6=9rB9o95rn7ag>5<6sA8h86sa6bg94?7|@;i?7p`9cg83>4}O:j>0qc8k0;295~N5k=1vb;j>:182M4d<2we:i<50;3xL7e33td=h>4?:0yK6f2<ug<o87>51zJ1g1=zf?n>6=4>{I0`0>{i>m<1<7?tH3a7?xh1l>0;6<uG2b68yk0c03:1=vF=c59~j3b>290:wE<l4:m2ag=83;pD?m;;|l5`g<728qC>n:4}o4gg?6=9rB9o95rn7fg>5<6sA8h86sa6eg94?7|@;i?7p`9dg83>4}O:j>0qc8j0;295~N5k=1vb;k>:182M4d<2we:h<50;3xL7e33td=i>4?:0yK6f2<ug<n87>51zJ1g1=zf?o>6=4>{I0`0>{i>l<1<7?tH3a7?xh1m>0;6<uG2b68yk0b03:1=vF=c59~j3c>290:wE<l4:m2`g=83;pD?m;;|l5ag<728qC>n:4}o4fg?6=9rB9o95rn7gg>5<6sA8h86sa6dg94?7|@;i?7p`9eg83>4}O:j>0qc8i0;295~N5k=1vb;h>:182M4d<2we:k<50;3xL7e33td=j>4?:0yK6f2<ug<m87>51zJ1g1=zf?l>6=4>{I0`0>{i>o<1<7?tH3a7?xh1n>0;6<uG2b68yk0a03:1=vF=c59~j3`>290:wE<l4:m2cg=83;pD?m;;|l5bg<728qC>n:4}o4eg?6=9rB9o95rn7dg>5<6sA8h86sa6gg94?7|@;i?7p`9fg83>4}O:j>0qc9?0;295~N5k=1vb:>>:182M4d<2we;=<50;3xL7e33td<<>4?:0yK6f2<ug=;87>51zJ1g1=zf>:>6=4>{I0`0>{i?9<1<7?tH3a7?xh08>0;6<uG2b68yk1703:1=vF=c59~j26>290:wE<l4:m35g=83;pD?m;;|l44g<728qC>n:4}o53g?6=9rB9o95rn62g>5<6sA8h86sa71g94?7|@;i?7p`80g83>4}O:j>0qc9>0;295~N5k=1vb:?>:182M4d<2we;<<50;3xL7e33td<=>4?:0yK6f2<ug=:87>51zJ1g1=zf>;>6=4>{I0`0>{i?8<1<7?tH3a7?xh09>0;6<uG2b68yk1603:1=vF=c59~j27>290:wE<l4:m34g=83;pD?m;;|l45g<728qC>n:4}o52g?6=9rB9o95rn63g>5<6sA8h86sa70g94?7|@;i?7p`81g83>4}O:j>0qc9=0;295~N5k=1vb:<>:182M4d<2we;?<50;3xL7e33td<>>4?:0yK6f2<ug=987>51zJ1g1=zf>8>6=4>{I0`0>{i?;<1<7?tH3a7?xh0:>0;6<uG2b68yk1503:1=vF=c59~j24>290:wE<l4:m37g=83;pD?m;;|l46g<728qC>n:4}o51g?6=9rB9o95rn60g>5<6sA8h86sa73g94?7|@;i?7p`82g83>4}O:j>0qc9<0;295~N5k=1vb:=>:182M4d<2we;><50;3xL7e33td<?>4?:0yK6f2<ug=887>51zJ1g1=zf>9>6=4>{I0`0>{i?:<1<7?tH3a7?xh0;>0;6<uG2b68yk1403:1=vF=c59~j25>290:wE<l4:m36g=83;pD?m;;|l47g<728qC>n:4}o50g?6=9rB9o95rn61g>5<6sA8h86sa72g94?7|@;i?7p`83g83>4}O:j>0qc9;0;295~N5k=1vb::>:182M4d<2we;9<50;3xL7e33td<8>4?:0yK6f2<ug=?87>51zJ1g1=zf>>>6=4>{I0`0>{i?=<1<7?tH3a7?xh0<>0;6<uG2b68yk1303:1=vF=c59~j22>290:wE<l4:m31g=83;pD?m;;|l40g<728qC>n:4}o57g?6=9rB9o95rn66g>5<6sA8h86sa75g94?7|@;i?7p`84g83>4}O:j>0qc9:0;295~N5k=1vb:;>:182M4d<2we;8<50;3xL7e33td<9>4?:0yK56?<@8937E<l4:X213<6s;i>6pT>09824312twe;8:50;3xL45>3A;846F=c59Y505=9r:1qp`85483>4}O:j>0V<;9:0y250<zR8:36<u>578~yk12>3:1=vF=c59~j230290:wE<l4:m30>=83;pD?m;;|l41<<728qC>n:4}o56e?6=9rB9o95rn67a>5<6sA8h86sa74a94?7|@;i?7p`85e83>4}O:j>0qc9:e;295~N5k=1vb:;i:182M4d<2we;;>50;3xL7e33td<:<4?:0yK6f2<ug==>7>51zJ1g1=zf><86=4>{I0`0>{i??>1<7?tH3a7?xh0><0;6<uG2b68yk11>3:1=vF=c59~j200290:wE<l4:m33>=83;pD?m;;|l42<<728qC>n:4}o55e?6=9rB9o95rn64a>5<6sA8h86sa77a94?7|@;i?7p`86e83>4}O:j>0qc99e;295~N5k=1vb:8i:182M4d<2we;:>50;3xL7e33td<;<4?:0yK6f2<ug=<>7>51zJ1g1=zf>=86=4>{I0`0>{i?>>1<7?tH3a7?xh0?<0;6<uG2b68yk10>3:1=vF=c59~j210290:wE<l4:m32>=83;pD?m;;|l43<<728qC>n:4}o54e?6=9rB9o95rn65a>5<6sA8h86sa76a94?7|@;i?7p`87e83>4}O:j>0qc98e;295~N5k=1vb:9i:182M4d<2we;5>50;3xL7e33td<4<4?:0yK6f2<ug=3>7>51zJ1g1=zf>286=4>{I0`0>{i?1>1<7?tH3a7?xh00<0;6<uG2b68yk1?>3:1=vF=c59~j2>0290:wE<l4:m3=>=83;pD?m;;|l4<<<728qC>n:4}o5;e?6=9rB9o95rn6:a>5<6sA8h86sa79a94?7|@;i?7p`88e83>4}O:j>0qc97e;295~N5k=1vb:6i:182M4d<2we;4>50;3xL7e33td<5<4?:0yK6f2<ug=2>7>51zJ1g1=zf>386=4>{I0`0>{i?0>1<7?tH3a7?xh01<0;6<uG2b68yk1>>3:1=vF=c59~j2?0290:wE<l4:m3<>=83;pD?m;;|l4=<<728qC>n:4}o5:e?6=9rB9o95rn6;a>5<6sA8h86sa78a94?7|@;i?7p`89e83>4}O:j>0qc96e;295~N5k=1vb:7i:182M4d<2we;l>50;3xL7e33td<m<4?:0yK6f2<ug=j>7>51zJ1g1=zf>k86=4>{I0`0>{i?h>1<7?tH3a7?xh0i<0;6<uG2b68yk1f>3:1=vF=c59~j2g0290:wE<l4:m3d>=83;pD?m;;|l4e<<728qC>n:4}o5be?6=9rB9o95rn6ca>5<6sA8h86sa7`a94?7|@;i?7p`8ae83>4}O:j>0qc9ne;295~N5k=1vb:oi:182M4d<2we;o>50;3xL7e33td<n<4?:0yK6f2<ug=i>7>51zJ1g1=zf>h86=4>{I0`0>{i?k>1<7?tH3a7?xh0j<0;6<uG2b68yk1e>3:1=vF=c59~j2d0290:wE<l4:m3g>=83;pD?m;;|l4f<<728qC>n:4}o5ae?6=9rB9o95rn6`a>5<6sA8h86sa7ca94?7|@;i?7p`8be83>4}O:j>0qc9me;295~N5k=1vb:li:182M4d<2we;n>50;3xL7e33td<o<4?:0yK56?<@8937E<l4:~yxFGKr2o;7?643g5b0{GHKq;qMN_{|BC
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/icon0.ucf b/FEE_ADC32board/project/ipcore_dir/icon0.ucf
deleted file mode 100644
index 0e944c3..0000000
--- a/FEE_ADC32board/project/ipcore_dir/icon0.ucf
+++ /dev/null
@@ -1,9 +0,0 @@
-NET "U0/U_ICON/*/iDRCK_LOCAL" TNM_NET = J_CLK ;
-TIMESPEC TS_J_CLK = PERIOD J_CLK 30 ns ;
-#Update Constraints
-NET "U0/iUPDATE_OUT" TNM_NET = U_CLK ;
-NET "U0/iSHIFT_OUT" TIG ;
-TIMESPEC TS_U_TO_J = FROM U_CLK TO J_CLK 15 ns ;
-TIMESPEC TS_U_TO_U = FROM U_CLK TO U_CLK 15 ns ;
-TIMESPEC TS_J_TO_D = FROM J_CLK TO D_CLK TIG ;
-TIMESPEC TS_D_TO_J = FROM D_CLK TO J_CLK TIG ;
diff --git a/FEE_ADC32board/project/ipcore_dir/icon0.vhd b/FEE_ADC32board/project/ipcore_dir/icon0.vhd
deleted file mode 100644
index ae45823..0000000
--- a/FEE_ADC32board/project/ipcore_dir/icon0.vhd
+++ /dev/null
@@ -1,33 +0,0 @@
--------------------------------------------------------------------------------
--- Copyright (c) 2014 Xilinx, Inc.
--- All Rights Reserved
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor     : Xilinx
--- \   \   \/     Version    : 14.7
---  \   \         Application: XILINX CORE Generator
---  /   /         Filename   : icon0.vhd
--- /___/   /\     Timestamp  : Tue Nov 25 11:13:40 W. Europe Standard Time 2014
--- \   \  /  \
---  \___\/\___\
---
--- Design Name: VHDL Synthesis Wrapper
--------------------------------------------------------------------------------
--- This wrapper is used to integrate with Project Navigator and PlanAhead
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-ENTITY icon0 IS
-  port (
-    CONTROL0: inout std_logic_vector(35 downto 0);
-    CONTROL1: inout std_logic_vector(35 downto 0);
-    CONTROL2: inout std_logic_vector(35 downto 0);
-    CONTROL3: inout std_logic_vector(35 downto 0);
-    CONTROL4: inout std_logic_vector(35 downto 0));
-END icon0;
-
-ARCHITECTURE icon0_a OF icon0 IS
-BEGIN
-
-END icon0_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/icon0.vho b/FEE_ADC32board/project/ipcore_dir/icon0.vho
deleted file mode 100644
index e68cf30..0000000
--- a/FEE_ADC32board/project/ipcore_dir/icon0.vho
+++ /dev/null
@@ -1,44 +0,0 @@
--------------------------------------------------------------------------------
--- Copyright (c) 2014 Xilinx, Inc.
--- All Rights Reserved
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor     : Xilinx
--- \   \   \/     Version    : 14.7
---  \   \         Application: Xilinx CORE Generator
---  /   /         Filename   : icon0.vho
--- /___/   /\     Timestamp  : Tue Nov 25 11:13:40 W. Europe Standard Time 2014
--- \   \  /  \
---  \___\/\___\
---
--- Design Name: ISE Instantiation template
--- Component Identifier: xilinx.com:ip:chipscope_icon:1.06.a
--------------------------------------------------------------------------------
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component icon0
-  PORT (
-    CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    CONTROL1 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    CONTROL2 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    CONTROL3 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    CONTROL4 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0));
-
-end component;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-
-your_instance_name : icon0
-  port map (
-    CONTROL0 => CONTROL0,
-    CONTROL1 => CONTROL1,
-    CONTROL2 => CONTROL2,
-    CONTROL3 => CONTROL3,
-    CONTROL4 => CONTROL4);
-
--- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/FEE_ADC32board/project/ipcore_dir/icon0.xco b/FEE_ADC32board/project/ipcore_dir/icon0.xco
deleted file mode 100644
index 0b9cf9c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/icon0.xco
+++ /dev/null
@@ -1,56 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Tue Nov 25 10:12:59 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:chipscope_icon:1.06.a
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Structural
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a
-# END Select
-# BEGIN Parameters
-CSET component_name=icon0
-CSET constraint_type=embedded
-CSET enable_jtag_bufg=true
-CSET example_design=false
-CSET number_control_ports=5
-CSET use_ext_bscan=false
-CSET use_softbscan=false
-CSET use_unused_bscan=false
-CSET user_scan_chain=USER1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2013-10-13T14:12:40Z
-# END Extra information
-GENERATE
-# CRC: e48a616b
diff --git a/FEE_ADC32board/project/ipcore_dir/icon0.xise b/FEE_ADC32board/project/ipcore_dir/icon0.xise
deleted file mode 100644
index 101b0c8..0000000
--- a/FEE_ADC32board/project/ipcore_dir/icon0.xise
+++ /dev/null
@@ -1,79 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="icon0.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="icon0.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-    </file>
-    <file xil_pn:name="icon0.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|icon0|icon0_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="icon0.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/icon0" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="icon0" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-11-25T11:13:50" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="21555AEE3F8341188AED62B4D711BFDF" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings>
-    <binding xil_pn:location="/icon0" xil_pn:name="icon0.ucf"/>
-  </bindings>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/icon0_readme.txt b/FEE_ADC32board/project/ipcore_dir/icon0_readme.txt
deleted file mode 100644
index 0b23619..0000000
--- a/FEE_ADC32board/project/ipcore_dir/icon0_readme.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-The following files were generated for 'icon0' in directory
-D:\Xilinx_proj\Panda\Xilinx\FrontEndElectronics\FEE_V2_ADC32board_SODA2\ipcore_dir\
-
-XCO file generator:
-   Generate an XCO file for compatibility with legacy flows.
-
-   * icon0.xco
-
-Creates an implementation netlist:
-   Creates an implementation netlist for the IP.
-
-   * icon0.ngc
-   * icon0.ucf
-   * icon0.vhd
-   * icon0.vho
-
-Creates an HDL instantiation template:
-   Creates an HDL instantiation template for the IP.
-
-   * icon0.vho
-
-IP Symbol Generator:
-   Generate an IP symbol based on the current project options'.
-
-   * icon0.asy
-
-SYM file generator:
-   Generate a SYM file for compatibility with legacy flows
-
-   * icon0.sym
-
-Generate ISE metadata:
-   Create a metadata file for use when including this core in ISE designs
-
-   * icon0_xmdf.tcl
-
-Generate ISE subproject:
-   Create an ISE subproject for use when including this core in ISE designs
-
-   * _xmsgs/pn_parser.xmsgs
-   * icon0.gise
-   * icon0.xise
-
-Deliver Readme:
-   Readme file for the IP.
-
-   * icon0_readme.txt
-
-Generate FLIST file:
-   Text file listing all of the output files produced when a customized core was
-   generated in the CORE Generator.
-
-   * icon0_flist.txt
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/FEE_ADC32board/project/ipcore_dir/ila.ngc b/FEE_ADC32board/project/ipcore_dir/ila.ngc
deleted file mode 100644
index 77eca7a..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.5e
-$c`e41<,[o}e~g`n;"2*776&=$:=-*>;1684567=2:;<=>7;1234567801;<=>?012305=789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456682:;<=>?0123656789;;7=>?0023456789:;<95?0167?564N=1;==?7;1036547I=1;99>;;1G301=7N;8:7<??;022E436NK:IMO;MF06855<NFY__6JOAD^K?=?699h1:87GAPTV9EABUI[NJHI\31283:4g<9=0BB][[:@FGVGQUIMNY0<=50?37?40=AGZ^X7OKDSC?50<768>0=;4FNQWW>DBCZK6:97>115922?OIX\^1HDOKI=36>586<2;=6D@_UU8GMGBN48?1<3?:;049KPRW]]0OCLJ@<0794;7238<1CXZ_UU8GKGBH48?1<3?<;08JJUSS2NKEHRG30;2=5>453;:::6<?:HLSQQ<TZEUJSD2>9;2=0>4689;<7?<?:HLSQQ<@IGNTE1<>9;2=6>4090196D@_UU8B@ATF\@OCEJF31;2=5<=52@D[YY4NDEPAPLCOANB7=7>11591>LHW]]0OE]OKIQ>2>586<281EC^ZT;FJTGBNX5;1<3?:;38LQQVR\3ND\LJ@P=394;723;0DYY^ZT;FLTGBHX5;1<3:4302E57=4:3CE\XZ5DHC?74<76880??4FNQWW>AOE4:;1<3?<;209KPRW]]0OCL2<1;2=56=4:3E^X][[:EMA867=87;=7>85IOMVP?EHF]XD@1=::1<2?12<<?;;=<5;:HLSQQ<CAYK7?7>11097>LHW]]0OE]L33;2=55=32@D[YY4XE@>0>58682>1EC^ZT;UFF95=87;9794@UURVP?BHXH686=0>2:69KPRW]]0OC]L33;2=55=2?<?>;8;:7473656b3<0BB][[:@>7>58682<}`u?>5ude5431%;20;>8=5063<>1ANOLMJK??;6DEBC@ANOLMJKHIF09;<>>789:;<=?;;979MKVR\3^YEJ>38583:44<03CE\XZ5WD@TA91=8780M=<4A008E74<I:>0M1>14:C?5;2<I58586O33?48E92=87>0M1:14:CB<5773HKJMK=L0GDEB5678=1JOKH7;@FGVD:7601JHI\N<02==>GCL[K7=<06;@FGVD:6:730MIJ]A=30:<=FLMXJ0<:1b:CG@WG;9<0;245NDEPB843902KOH_O31?:8EABUI58546OKDSC?7;><IMNYM1:18:CG@WG;=720MIJ]A=4=<>GCL[K7;364AEFQE9>902KOH_O39?g8EABUI[NJHI\30?d8EABUI[NJHI\311<e?DBCZHXOMIJ]<03=b>GCL[KYHLJKR=31:47<IMNYM_JNDEP?56<76o1JHI\NRECG@W:6;7o0MIJ]ASFB@AT;97o0MIJ]ASFB@AT;:7o0MIJ]ASFB@AT;;7o0MIJ]ASFB@AT;<7o0MIJ]ASFB@AT;=7o0MIJ]ASFB@AT;>7o0MIJ]ASFB@AT;?7o0MIJ]ASFB@AT;07o0MIJ]ASFB@AT;17l0MIJ]AUKFLLAO494:=6OKDSCWM@NNOA6:6=0i;@FGVDRNMACLD1?18:CG@WD;8730MIJ]B=33:<=FLMXI0<?19:CG@WD;9;427LJKRC>27;?<IMNYN1?;>c9B@ATE48?1<374AEFQF972611JHI\M<0<;?DBCZK69255NDEPA868?3HNO^O2;>99B@ATE4<437LJKRC>5:==FLMXI0:07;@FGVG:?611JHI\M<8<e?DBCZK^BIEGHH=2=54=FLMXIXDKGIFJ?5?69n2KOH_L[IDJJCM:66l1JHI\MWSCG@W:76o1JHI\MWSCG@W:687l0MIJ]BVPB@AT;984m7LJKRCUQEABU4885=<5NDEPASWGCL[6:?7>1f:CG@WDPZHNO^1?<>d9B@ATE_[KOH_2>>d9B@ATE_[KOH_2=>d9B@ATE_[KOH_2<>d9B@ATE_[KOH_2;>d9B@ATE_[KOH_2:>d9B@ATE_[KOH_29>d9B@ATE_[KOH_28>d9B@ATE_[KOH_27>d9B@ATE_[KOH_26>99BBF@7N9L87LBC4:@147773KHINOL?BC@AFG>7011IY^QFNGM2?F2<K1>;>6MNd:ABWFGCM@DGMYOk;BCPGDBBAGFJXOj4C@Q@EACNF[OLMi5LARAB@@OIZLMIi6MNSBCGAJSSDH^Ji6MNSBCGAJSSDH^Ii6MNSBCGAJSSZLMJi6MNSBCGAJSSZLMI==5LCBA@4F6DK12H<5>=;BG26>EOMJAT@DMJNRG\P\VB:2IB?6MCK59@HNG>3JF@M_JLLJ68GIME12IGGOY]CMI6?FJLW@90OA\6;BMNILRSMMk0OB@[RNN?4;d<KFD_^BB311<a?FII\[EG0<?1b:ALJQTHD5;92o5LOOVQKI:6;7h0OB@[RNN?518e3JEEX_AC<07=f>EHF]XD@1?9>c9@KKRUGE6:;3l4CNLWVJJ;914i7NAATSMO84?9i2IDBY\@L=3=f>EHF]XD@1<?>c9@KKRUGE69=3l4CNLWVJJ;:;4i7NAATSMO8759j2IDBY\@L=07:g=DGG^YCA2=5?`8GJHSZFF7>;0m;BMMPWIK4;=5n6M@NUPLH94?6k1HCCZ]OM>1=;g<KFD_^BB32?`8GJHSZFF7?=0m;BMMPWIK4:;5n6M@NUPLH9556k1HCCZ]OM>07;d<KFD_^BB335<g?FII\[EG0>;50?`8GJHSZFF7?80n;BMMPWIK4:4j7NAATSMO818f3JEEX_AC<4<b?FII\[EG0;0n;BMMPWIK4>4j7NAATSMO8=8f3JEEX_AC<8<20>EHZLULICK]AUKLJZOINF=0O_KNTDF2?A4<L@<0HDO30?58@LG;994<7IGN<03=3>BNI5;92:5KI@>27;1<L@K7=908;EKB8439?2NBM1?9>69GMD:6?7=0HDO319<4?AOF4835:6JFA=3=3>BNI58;2:5KI@>15;1<L@K7>?08;EKB8759?2NBM1<;>69GMD:5=7=0HDO327<4?AOF4;=5;6JFA=0;:2=CAH695384DHC?6;1<L@K7?=06;EKB867=87=0HDO330<5?AOF4:4=7IGN<5<5?AOF4<4=7IGN<7<5?AOF4>4=7IGN<9<5?AOF40437IGNDH>3:<=CAHNB0<>19:FJEAO;98427IGNDH>26;?<L@KOE1?<>89GMDBN48>5n6JFAEK?50<7601OELJF<07=<>BNIMC7=364DHCGM94902NBMIG33?:8@LGCA5>546JFAEK?1;><L@KOE1818:FJEAO;?720HDOKI=:=<>BNIMC75384DH@?4;1<L@H7==08;EKA8479?2NBN1?=>69GMG:6;7=0HDL315<4?AOE48?5;6JFB=35:2=CAK6:;394DH@?5=803MCI0<716:FJF979?2NBN1<?>69GMG:597=0HDL323<4?AOE4;95;6JFB=07:2=CAK699394DH@?63803MCI0?917:FJF94?6>1OEO2=9?48@LD;:7=0HDL331<:?AOE4:;1<394DH@?74813MCI0>09;EKA81813MCI0809;EKA83813MCI0:09;EKA8=813MCI0407;EKA@L:7601OEOJF<02==>BNJMC7=<06;EKA@L:6:730HDLKI=30:<=CAKNB0<:1b:FJFAO;9<0;245KICFJ843902NBNIG31?:8@LDCA58546JFBEK?7;><L@HOE1:18:FJFAO;=720HDLKI=4=<>BNJMC7;364DH@GM9>902NBNIG39?58@LVF494<7IG_A=3=3>BNXH69245KIQC?7?69?2NB\L2<>`9GMUGCAY6;2n5KIQCGMU:6294j7IG_AEKS84803MC[N1>17:FJTG:66>1OE]L32?;8@LVE4:0;2:5KIQ@?7;g<L@ZIHD^30?a8@LVEL@Z7=7>1a:FJTGBNX5;5:6J@A=2=3>BHI5;;2:5KO@>25;1<LFK7=?08;EMB8459?2NDM1?;>69GKD:6=7=0HBO317<4?AIF48=5;6J@A=3;:2=CGH6:5384DNC?5;1<LFK7>=08;EMB8779?2NDM1<=>69GKD:5;7=0HBO325<4?AIF4;?5;6J@A=05:2=CGH69;394DNC?6=803MEJ0?716:FLE949?2NDM1=?>89GKD:493:5;6J@A=12:3=CGH682;5KO@>7:3=CGH6>2;5KO@>5:3=CGH6<2;5KO@>;:3=CGH62255KO@FL858>3MEJHB2>0?;8@JGCG5;:245KO@FL844912NDMIA312<:?AIFLF6:83l4DNCGK97229427IANDN>21;><LFKOC1?18:FLEAI;:720HBOKO=1=<>BHIME78364DNCGK93902NDMIA36?:8@JGCG5=546J@AEM?<;><LFKOC1717:FLEZTBO?1OCO2?>69GKG:687=0HBL310<4?AIE4885;6J@B=30:2=CGK6:8394DN@?50803MEI0<817:FLF9706>1OCO2>8?58@JD;904=7IAM<0<4?AIE4;:5;6J@B=02:2=CGK69>394DN@?66803MEI0?:17:FLF9426>1OCO2=6?58@JD;:>4<7IAM<3:=3>BHJ5822;5KOC>1:2=CGK68<374DN@?74<76>1OCO2<1?48@JD;;7<0HBL34?48@JD;=7<0HBL36?48@JD;?7<0HBL38?48@JD;1720HBLKO=2==>BHJME7==06;EMA@J:69730HBLKO=31:<=CGKND0<=19:FLFAI;9=4i7IAMDN>21?6912NDNIA314<;?AIELF6:255KOCFL878?3MEIHB2<>99GKGBH4=437IAMDN>6:==CGKND0;07;EMA@J:0611OCOJ@<9<;?AIELF622:5KOC]QAB1<LFZJ0=08;EMSE979?2ND\L2=>89GKUG;;3:5;6J@P@>0:d=CGYKOC]2?>b9GKUGCGY6:6=0n;EMSEAIW484<7IA_B=2=3>BHXK6:2:5KOQ@?6;?<LFZI0>4?>69GKUD;;7k0HB^MDNR?4;e<LFZIHB^31;2=e>BHXKND\1?15:F\GIM63L80I9??;D6B45678=>;<=>?0028AF67I1:;:9>?21236>CA<2OM8K??;DDF1@GB8=L?99O;029FJD1<MGKYHH@<;DLA3>CIJ^XNB95I01724>@7NOL;JKM?CBD3ED3<NHFXI?5IB39E@46<NMK3M5O7DE:;<=>?<2LOOH=4FEG24>@CNMLHJIHKFEDGBA5<NMZ?7KJ_E29E@W2<NMXN?6HKS028BC32NO?>JK>:FG2755=ANJIMJK>NA@CEBC@33OLM<95IFGF7?C@AM8:0JKHIC0D2BC@AKMLO46HIFGDEBA773OLMJKHIF1631G@FN11M^BCPNBD2?B?<OHDOSNGPIc9DEKBXA5:1<374G@LG[L:76k1LMCJPI=334;d<OHDOSD2>00<a?BGILVC7==<1b:EBJAYN48:82o5HAOF\M977<7h0KL@K_H>2408e3NKEHRG3114=f>AFFMUB0<>8>c9DEKBXA5;;43l4G@LG[L:6804j7JOAD^K?558e3NKEHRG3102=f>AFFMUB0<?>>c9DEKBXA5;:>3l4G@LG[L:69:4i7JOAD^K?5429j2MJBIQF<036:g=@IGNTE1?>6?`8CDHCW@6:=:0m;FCM@ZO;9825n6INNE]J847>6h1LMCJPI=32:g=@IGNTE1?=0?`8CDHCW@6:><0m;FCM@ZO;9;85n6INNE]J84446k1LMCJPI=310;d<OHDOSD2>24<a?BGILVC7=?81b:EBJAYN488<2o5HAOF\M97507h0KL@K_H>26<8f3NKEHRG313<a?BGILVC7=>>1b:EBJAYN489:2o5HAOF\M974:7h0KL@K_H>2768e3NKEHRG3126=f>AFFMUB0<=:>c9DEKBXA5;8:3l4G@LG[L:6;>4i7JOAD^K?56>9j2MJBIQF<01::d=@IGNTE1?<>c9DEKBXA5;?<3l4G@LG[L:6<84i7JOAD^K?5149j2MJBIQF<060:g=@IGNTE1?;4?`8CDHCW@6:880m;FCM@ZO;9=<5n6INNE]J84206k1LMCJPI=37<;d<OHDOSD2>48<b?BGILVC7=90m;FCM@ZO;9<:5n6INNE]J84366k1LMCJPI=366;d<OHDOSD2>52<a?BGILVC7=8:1b:EBJAYN48?>2o5HAOF\M972>7h0KL@K_H>2128e3NKEHRG314:=f>AFFMUB0<;6>`9DEKBXA5;>2o5HAOF\M97187h0KL@K_H>2248e3NKEHRG3170=f>AFFMUB0<8<>c9DEKBXA5;=83l4G@LG[L:6><4i7JOAD^K?5309j2MJBIQF<044:g=@IGNTE1?98?`8CDHCW@6::40n;FCM@ZO;9?4i7JOAD^K?5269j2MJBIQF<052:g=@IGNTE1?82?`8CDHCW@6:;>0m;FCM@ZO;9>>5n6INNE]J84126k1LMCJPI=342;d<OHDOSD2>76<a?BGILVC7=:61b:EBJAYN48=22l5HAOF\M9706k1LMCJPI=3;4;d<OHDOSD2>80<a?BGILVC7=5<1b:EBJAYN48282o5HAOF\M97?<7h0KL@K_H>2<08e3NKEHRG3194=f>AFFMUB0<68>c9DEKBXA5;343l4G@LG[L:6004j7JOAD^K?5=8e3NKEHRG3182=f>AFFMUB0<7>>c9DEKBXA5;2>3l4G@LG[L:61:4i7JOAD^K?5<29j2MJBIQF<0;6:g=@IGNTE1?66?`8CDHCW@6:5:0m;FCM@ZO;9025n6INNE]J84?>6h1LMCJPI=3::<=@IGNTE1?1b:EBJAYN4;:;2o5HAOF\M94797h0KL@K_H>1478e3NKEHRG3211=f>AFFMUB0?>;>c9DEKBXA58;93l4G@LG[L:58?4i7JOAD^K?6519j2MJBIQF<32;:g=@IGNTE1<?9?c8CDHCW@69<3l4G@LG[L:5994i7JOAD^K?6479j2MJBIQF<331:g=@IGNTE1<>3?`8CDHCW@69=90m;FCM@ZO;:8?5n6INNE]J87716k1LMCJPI=023;d<OHDOSD2=19<g?BGILVC7><750?`8CDHCW@69=40n;FCM@ZO;:84j7JOAD^K?678f3NKEHRG322<b?BGILVC7>90n;FCM@ZO;:<4j7JOAD^K?638f3NKEHRG326<b?BGILVC7>50n;FCM@ZO;:0427JOAD^K?6;g<OHDOSD2<0?c8CDHCW@68=3o4G@LG[L:4:7k0KL@K_H>07;g<OHDOSD2<4?c8CDHCW@6893o4G@LG[L:4>7k0KL@K_H>03;g<OHDOSD2<8?c8CDHCW@685374G@LG[L:46h1LMCJPI=63:d=@IGNTE1:>>`9DEKBXA5>92l5HAOF\M9246h1LMCJPI=67:d=@IGNTE1::>`9DEKBXA5>=2l5HAOF\M9206h1LMCJPI=6;:d=@IGNTE1:6>89DEKBXA5>5m6INNE]J8069i2MJBIQF<43=e>AFFMUB08<1a:EBJAYN4<95m6INNE]J8029i2MJBIQF<47=e>AFFMUB0881a:EBJAYN4<=5m6INNE]J80>9i2MJBIQF<4;==>AFFMUB080n;FCM@ZO;>94j7JOAD^K?248f3NKEHRG363<b?BGILVC7:>0n;FCM@ZO;>=4j7JOAD^K?208f3NKEHRG367<b?BGILVC7::0n;FCM@ZO;>14j7JOAD^K?2<8>3NKEHRG36?c8CDHCW@6<<3o4G@LG[L:097k0KL@K_H>46;g<OHDOSD283?c8CDHCW@6<83o4G@LG[L:0=7k0KL@K_H>42;g<OHDOSD287?c8CDHCW@6<43o4G@LG[L:01730KL@K_H>4:d=@IGNTE16?>`9DEKBXA52:2l5HAOF\M9>56h1LMCJPI=:0:d=@IGNTE16;>`9DEKBXA52>2l5HAOF\M9>16h1LMCJPI=:4:d=@IGNTE167>`9DEKBXA522245HAOF\M9>9i2MJBIQF<82=e>AFFMUB04?1a:EBJAYN4085m6INNE]J8<59i2MJBIQF<86=e>AFFMUB04;1a:EBJAYN40<5m6INNE]J8<19i2MJBIQF<8:=e>AFFMUB0471b:EBJAYN400;245HAOF\M9?9>2MJBIQ@3:EM@3=O]VYNX<5F2:K36>O6:2C9>6G<2:K76>O202CEEY^P01:8MKOSXV::46GAIUR\47><AGC_\R><8:KMMQVX8=20ECG[P^26<>OIA]ZT<;64IOKWTZ6002CEEY^P09:8MKOSXV:246GAIUR\4D><AGC_\R>M8:KMMQVX8J20ECG[P^2G<>OIA]ZT<H64IOKWTZ6A12CEEY][AUG4?LHN\V:;;6GAIU]352=NF@^T<?94IOKW[5503@DBXR>;7:KMMQY7=>1BBDZP0758MKOSW9=<7D@FT^2;3>OIA]U;5:5FNHV\4D1<AGC_S=L8;HLJPZ6D?2CEEYQ?D69JJLRX8L=0ECG[_1D4?LHN\V;;;6GAIU]252=NF@^T=?94IOKW[4503@DBXR?;7:KMMQY6=>1BBDZP1758MKOSW8=<7D@FT^3;3>OIA]U:5:5FNHV\5D1<AGC_S<L8;HLJPZ7D?2CEEYQ>D69JJLRX9L=0ECG[_0D4?LHN\V8;;6GAIU]152=NF@^T>?94IOKW[7503@DBXR<;7:KMMQY5=>1BBDZP2758MKOSW;=<7D@FT^0;3>OIA]U95:5FNHV\6D1<AGC_S?L8;HLJPZ4D?2CEEYQ=D69JJLRX:L=0ECG[_3D4?LHN\V9;;6GAIU]052=NF@^T??94IOKW[6503@DBXR=;7:KMMQY4=>1BBDZP3758MKOSW:=<7D@FT^1;3>OIA]U85:5FNHV\7D1<AGC_S>L8;HLJPZ5D?2CEEYQ<D69JJLRX;L=0ECG[_2D4?LHN\V>;;6GAIU]752=NF@^T8?94IOKW[1503@DBXR:;7:KMMQY3=>1BBDZP4758MKOSW==<7D@FT^6;3>OIA]U?5:5FNHV\0D1<AGC_S9L8;HLJPZ2D?2CEEYQ;D69JJLRX<L=0ECG[_5D4?LHN\V?;;6GAIU]652=NF@^T9?94IOKW[0503@DBXR;;7:KMMQY2=>1BBDZP5758MKOSW<=<7D@FT^7;3>OIA]U>5:5FNHV\1D1<AGC_S8L8;HLJPZ3D?2CEEYQ:D69JJLRX=L=0ECG[_4D4?LHN\V<;;6GAIU]552=NF@^T:?94IOKW[3503@DBXR8;7:KMMQY1=>1BBDZP6758MKOSW?=<7D@FT^4;3>OIA]U=5:5FNHV\2D1<AGC_S;L8;HLJPZ0D?2CEEYQ9D69JJLRX>L=0ECG[_7D4?LHN\V=;;6GAIU]452=NF@^T;?94IOKW[2503@DBXR9;7:KMMQY0=>1BBDZP7758MKOSW>=<7D@FT^5;3>OIA]U<5:5FNHV\3D1<AGC_S:L8;HLJPZ1D?2CEEYQ8D69JJLRX?L=0ECG[_6D5?LHN\VK=7D@FT^@:?LHN\VLB@H=4IOT02>OXAZU_I_CFN@VJKKYTD@INSCK?.H]VW@YH]]Z^XR\JG^LF4+SXG[OL><5F_HQ\P@TJAGK_EB@PSMK@AZHB8'_TAXVI219J[UGU\@KGS^BFCD,V[BGILVYY@R]CIBG1`>OX_AEGIR]CIBG-CZUKAJOTEIVT0\,V[BGILVYY@R]CIBG1a>OX_AEGIR]CIBG-CZUKAJOTEIVT11_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[0_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[3_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[2_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[5_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[4_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[7_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[6_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[9_-QZAFFMUX^AQ\LHAF6a=NW^BD@HQ\LHAF*BYTD@INSDJW[8_-QZAFFMUX^AQ\LHAF0>MBMY<0@#:;_M18HAE53EC97AA9;MMB@@B03EELENOC4:NVP42<D\^986BZT268HPR3<2F^X8:4LTV53>KRPJST@85BUYD41>KRPO2h7@oeosTfvvohfj1Feca}Vdppmjh53G:97C?<;O1;7>H41:1E8<=4N570?K20;2D?5:5AEUULVN0<FFIGE]94NNOFVBC33GEEI<5@1:R7?UGU\h1[ECQMURKG\g=WAGUIY^@NMD18TWC63X90]<;<;P125>T?3[KFN<6J179QEHD4>o1YM@QJXUGMWLIIWHl0^LCPEYVFJVOHFVH37_OB_LMGAf=UMHNT[DJ[H^C`?WCFLV]BHYFPB49QABEB>2XNKNKNb:PFCFCFZLMHI;5]EFAFFa=UMNIGGL\KRBNH3>TBOJF@N:5]ERGW[L2<ZEEHh6\\TSCNEWUSZHG<7_][R@OA`>TT\[OLM_][RDE4?WUSZLMI=<5]SUPFCZVUAFXBXTQN109QWQTBOVZYEB\FTX]A5>U33ZKMI55\AWGGEQG6;2YBARM@LMKPMJHXKAOHG55\IL]NKAC?3ZAB\R^FN79PKPTDM<1X^A?96:QQH40B?2YY@N?9E69PVIE4:Lk0__BPA^K?4;d<[[FTMRG311<a?VTKWHUB0<?1b:QQHZGXA5;92o5\RM]B[L:6;7h0__BPA^K?518e3ZXGSLQF<07=f>UUDVKTE1?9>c9PVIYFW@6:;3l4SSN\EZO;914o7^\C_@]J84?=87h0__BPA^K?5<8f3ZXGSLQF<0<b?VTKWHUB0?0n;RPO[DYN4:4j7^\C_@]J818f3ZXGSLQF<4<b?VTKWHUB0;0n;RPO[DYN4>4j7^\C_@]J8=8f3ZXGSLQF<8<;?VTKWJOTE45\RM]@HNYN?2YY@RJPI69PVIYVWF=0__XNL^C4?VTQIEUI86]\R@68WVTE;2^O\:5[NL]MAQ><\[CL<1>19:VQMB6;99427Y\FG1>25;?<\[CL<1?=>89WVLA7489556Z]IF2?518>3]XBK=2>5?;8PWO@85;=245[RHE3841912^YEJ>319<:?QTNO96:5364TSKD497912^YEJ>321<:?QTNO969=374TSKD4945601_^DI?<31==>RUAN:7>906;UPJC5:5=730X_GH0=05:<=SZ@M;0?919:VQMB6;:1427Y\FG1>1=;><\[CL<1<19:VQMB6;;9427Y\FG1>05;?<\[CL<1==>89WVLA74:9556Z]IF2?718>3]XBK=2<5?;8PWO@859=245[RHE3861912^YEJ>339<:?QTNO9685364TSKD495912^YEJ>341<:?QTNO96?=374TSKD4925601_^DI?<51==>RUAN:78906;UPJC5:3=730X_GH0=65:<=SZ@M;09919:VQMB6;<1427Y\FG1>7=;><\[CL<1:19:VQMB6;=9427Y\FG1>65;?<\[CL<1;=>89WVLA74<9556Z]IF2?118>3]XBK=2:5?;8PWO@85?=245[RHE3801912^YEJ>359<:?QTNO96>5364TSKD493912^YEJ>361<:?QTNO96==374TSKD4905601_^DI?<71==>RUAN:7:906;UPJC5:1=730X_GH0=45:<=SZ@M;0;919:VQMB6;>1427Y\FG1>5=;><\[CL<1819:VQMB6;?9427Y\FG1>45;?<\[CL<19=>89WVLA74>9556Z]IF2?318>3]XBK=285?;8PWO@85==245[RHE3821912^YEJ>379<:?QTNO96<5364TSKD491912^YEJ>381<:?QTNO963=374TSKD49>5601_^DI?<91=f>RUAN:7494?>89WVLA741>546Z]IF2?<;><\[CL<1714:VQQ@2<\PZN?h5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR:V"DQ\RMV\J@Y7&MFR5>m4U1-J[KIXL'_TEAO I^FR*PYCYX%O@TQ6.ENZ[<Y@MGQ;Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;;Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP==S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=<S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?>]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?=]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T13_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T12_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ30Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ37Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX51[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX50[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^72U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^71U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9?W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9>W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;<Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;3Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=5S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=4S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?6]/K\WWJSWGOT<#HI3d9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?R.H]PVIRXFLU;"IBV92a8Q5)NWGETH#[PIMC,MZBV&\UO]\!KLX]:*AJ^W0ULICU>]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<?]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T21_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T20_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ02Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ01Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX67[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX66[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^44U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^43U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\:=W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\:<W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR8>Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR8=Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>;S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>:S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<8]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<7]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T29_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T28_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ0:Y+OX[[F_SCKP0/DE7`=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ0^*LYTZE^TBHQ?.ENZ=6e<]9%BSCAPD/W\MIG(AVNZ"XQKQP-GH\Y>&MFRS4QHEOY1Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ13Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX75[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX74[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^56U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^55U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;;W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;:W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR98Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR9?Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP?9S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP?8S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV=:]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV=9]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T37_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T36_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ14Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ1;Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX7=[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX7<[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^5>U'CT__B[_OG\4+@A;l1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^5Z&@UX^AZPND]3*AJ^1:i0Y=!F_OM\@+SXAEK$ERJ^.T]GUT)CDPU2"IBV_8]DAK]4U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^27U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<9W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<8W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>:Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>9Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP8?S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP8>S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV:<]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV:;]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T45_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T44_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ66Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ65Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX03[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX02[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^20U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^2?U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<1W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<0W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>2Q#GPSSNW[KCX8'LM?h5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>V"DQ\RMV\J@Y7&MFR5>m4U1-J[KIXL'_TEAO I^FR*PYCYX%O@TQ6.ENZ[<Y@MGQ?Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR?;Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP9=S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP9<S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;>]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;=]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T53_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T52_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ70Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ77Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX11[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX10[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^32U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^31U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\=?W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\=>W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR?<Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR?3Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP95S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP94S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;6]/K\WWJSWGOT<#HI3d9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;R.H]PVIRXFLU;"IBV92a8Q5)NWGETH#[PIMC,MZBV&\UO]\!KLX]:*AJ^W0ULICU:]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV8?]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T61_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T60_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ42Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ41Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX27[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX26[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^04U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^03U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\>=W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\><W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR<>Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR<=Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP:;S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP::S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV88]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV87]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T69_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T68_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ4:Y+OX[[F_SCKP0/DE7`=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ4^*LYTZE^TBHQ?.ENZ=6e<]9%BSCAPD/W\MIG(AVNZ"XQKQP-GH\Y>&MFRS4QHEOY5Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ53Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX35[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX34[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^16U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^15U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\?;W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\?:W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR=8Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR=?Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP;9S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP;8S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV9:]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV99]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T77_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T76_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ54Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ5;Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX3=[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX3<[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^1>U'CT__B[_OG\4+@A;l1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^1Z&@UX^AZPND]3*AJ^1:i0Y=!F_OM\@+SXAEK$ERJ^.T]GUT)CDPU2"IBV_8]DAK]0U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^>7U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\09W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\08W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR2:Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR29Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP4?S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP4>S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV6<]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV6;]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T85_-MZUUD]UEIR>!FG1f?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T8\,J[VTK\VDNS= KLX;0g>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[9_-MZUUD]UEIR>!FG1f?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T9\,J[VTK\VDNS= KLX;0g>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[8_-MZUUD]UEIR>!FG01?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8585;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5;;2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~310<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9756;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7=>0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=37:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;9<49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1?9>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?5285;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5;32?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~318<16>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt979::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey69<3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<33=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:5:7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0?=1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>10;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4;?5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2=6?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8719::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6943<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<3;=67=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:56;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7?=0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=12:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;;;49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1=<>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?7185;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx59>2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~337<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9506;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7?50=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=1::74<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;;7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{09>1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>75;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4=85>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2;3?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8129::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6?93<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<54=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:3?7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0961229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>7=;453\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4=49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1;?>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?1485;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5?92?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~352<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9336;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7980=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=75:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;=>49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1;7>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?1<85:2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5?5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}290?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8379::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6=>3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<71=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:1<7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0;;1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>52;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4?=5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}298?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos83?9:;1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6=2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~371<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9166;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7;?0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=50:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;?=49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|19:>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?3385;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5=<2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~379<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt91>6;80Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7;3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<92=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:?97887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{05<1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>;7;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw41>5>?5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}27>308Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?=;343\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[POS]Q@ZTH_VOE945Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZIUW[Y_S_JPRNU\SLBB>:1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO I^UJ@QNX?'Txn9:;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*OX_@N_DR9!u^v`[5)^MZUGYY8!U^NVP3023\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"GPWHFWLZ1)}V~hS<;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~7<3;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~7=3;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~7>3;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~7?3;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~783;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~793;k;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*eh}g~7:3;7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*tt|<o0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/ua\r`e;87?n7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.v`[scd484=<6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'JC7=38?;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$OD2=>728Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYF'|Uhby!LI=1=25=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.AJ818182_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!z_blw+FO;=7<;7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(K@6=28h4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%O0=0:f:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[D)rWjd#I2>>4d8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYF'|Uhby!K<3<6b>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWH%~Sn`{/E>0:0`<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UJ#xQlnu-G8182n2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!z_blw+A:26<l0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/t]`jq)C4?4=n6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'NQ;Q#IaH/W\IP^DQ?<0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/t]`jq)@S9W%YRHKRD46?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz GZ2^*PYK]]<<7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(OR:V"XQWOSAZ2g=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.EX5X(@fA$^S@[WCX45?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz GZ3^*PYAL[O=96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'NQ:Q#[PLTV53>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWH%~Sn`{/FY2Y+SXPFXHU;l4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%LW?S!GoJ-QZKRPJS=:6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'NQ9Q#[PFEPF20=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.EX6X(RWE__::5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&MP>P Z_YMQG\0e3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,C^5Z&NdC"XQBUYAZ23=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.EX7X(RWONYI;;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%LW>S!U^NVP31<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UJ#xQlnu-D_6[)]VRD^NW9b:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[D)rWjd#JU;]/EmL+SXE\RHU;84U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%LW9S!U^DGV@023\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,C^2Z&\UGYY88;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$KV:R.T][KWE^>k1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*A\=T$LbE Z_LW[G\013\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,C^3Z&\UMH_K95:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[D)rWjd#JU:]/W\HPR1?2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!z_blw+B]2U'_TTB\LY748Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYF'|Uhby!H[7_-QZ@CZL<>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(OR<V"XQCUU44?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz GZ4^*PY_G[IR9k5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&Y7<3;i;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$_1?15g9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZG(}Viex"]32?7e?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz S=1=1c=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.Q?0;3a3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,W939=o1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*U;>7?j7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\vvr0;2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!F_VKGPMY1&|Uo"WJS^NVP3(RWE__:864U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]A+wus>91^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RL u^amp*EN484=<6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'JC7>38?;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\F*sXkg~$OD2<>728Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!LI=6=25=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVH$yRmat.AJ8082n2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_blw+A:76<l0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QM/t]`jq)C484>j6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'M6928h4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]A+pYdf}%O0>0:f:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[G)rWjd#I2;>4d8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!K<4<5f>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/FY3Y+Ai@'_TAXVLY748Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!H[1_-QZ@CZL<>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PB.w\gkr(OR:V"XQCUU44?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXJ&Tocz GZ2^*PY_G[IR:o5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&MP=P HnI,V[HS_KP<=7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PB.w\gkr(OR;V"XQIDSG51>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/FY2Y+SXD\^=;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'NQ:Q#[PXNP@]3d<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-D_7[)OgB%YRCZXB[52>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/FY1Y+SXNMXN:85Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&MP>P Z_MWW22=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVH$yRmat.EX6X(RWQEYOT8m;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\F*sXkg~$KV=R.FlK*PYJ]QIR:;5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&MP?P Z_GFQA33<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-D_6[)]VF^X;94U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]A+pYdf}%LW>S!U^ZLVF_1j2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_blw+B]3U'MeD#[PMTZ@]30<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-D_1[)]VLO^H8:;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\F*sXkg~$KV:R.T]OQQ003\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTN"{Pcov,C^2Z&\USC_MV679V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZD(}Viex"IT5\,V[CBUM??0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QM/t]`jq)@S<W%YRBZT758Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!H[4_-QZ^HZJS>j6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'Z6;28h4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]A+pYdf}%X0<0:f:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[G)rWjd#^2=>4d8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!\<2<6b>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/R>7:0`<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-P8082i2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_sqw2d=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVNGU"IPRDE\FLR\8T$^SKJ]E7c8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYCDP%LS_KH_CKW_4[)]VLO^H8n;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\@I_(OVXNKRLFTZ0^*PYAL[O=m6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_ENZ+BYUMNUIEYU<]/W\BATB>h1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RJCY.E\V@AXJ@^P8P Z_GFQA3g<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UO@T!H_SGD[GOSS<W%YRHKRD;1?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SCN+LYQ>'_TO^QMR@O\GDUDIMOTZ;!F_EGSPMYK\L[T??E!U^QAVDKX8&CTN<6DGU2-qZtfek;3#XQ]AL@2<@7>k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTFE&CTZ; Z_BQ\FWGJWJKXOLJJ_W4,MZBBX]BT@YK^_20H*PYTJ[KFS=!F_C15OBR7&NUYM@L<6Z2^*pYuidh8:"[PR@OA73?d3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WGJ'@U]:#[PCR]AVDKXKHYHMIKPV7-J[ACW\AUGXH_P33I-QZUEZHGT<"GPB24HCQ6)OVXJAO=9[0_-qZtfek9=#XQ]AL@020d<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYDGEUFYU!F6/W\IP^1<&GfyuQ@_026f>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[FIKWD_S#D8!U^OV\32(EdsSBQ>14a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]@KIYJ]Q%B:#[PMTZ50*Kj}qUDS<?>5b9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^ALHZKRP&C="XQBUY47+HkrpVET=<<:b:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_BMO[HS_'@<%YRCZX76,IhsWFU:>8m4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQLOM]NQ])N>'_TAXV94.Onq}YHW88:9n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHRM@L^OV\*O1&\UFYU8;/Lov|ZIX9;8>o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOSNAC_LW[+L0)]VG^T;: Mlw{[JY6::?i7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NTOBBPMTZ,M3(RWD_S:9!Bmtz\KZ74=j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K5*PYJ]Q<?#@czx^M\5672k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H4-QZKRP?>$A`{w_N]2773e3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXKFFTAXV I7,V[HS_>=%FaxvPO^371a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZEHDVG^T"G9.T]NQ]03'Dg~tRAP5^d41d=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZEHDVG^T"G9.T]NQ]03'Dg~tRAP64f8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]@KIYJ]Q%B:#[PMTZ50*Kj}qUDS;Qi74c8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]@KIYJ]Q%B:#[PMTZ50*Kj}qUDS:;n;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPCNN\IP^(A?$^S@[W65-Nip~XGV2?i6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN48:58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5;58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5858i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5958i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5>58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5?58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5<58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5=58i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5258i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)DA5358n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)C494?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*B;994?o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*B;97>h7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+A:56=i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,@959<j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-G8183k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.F?1;2d3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/E>5:1e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ D=5=0f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!K<9<7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"J39?7;?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU?]/EmL+SXE\RHU8=4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR:V"XQIDSG66>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT0\,V[ISS==1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_5[)]VRD^NW:4:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP==S!U^DGV@343\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY24X(RWE__985Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S8:V"XQWOSAZ1==R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[0_-CkN)]VG^TNW:3:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP=P Z_GFQA04<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ3^*PYK]]??7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]6U'_TTB\LY4:8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV<R.FlK*PYJ]QIR9>5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S;W%YRHKRD71?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU=]/W\HPR2<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX6X(RWQEYOT;7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ8Q#IaH/W\IP^DQ<90Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^5Z&\UMH_K:2:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP?P Z_MWW11=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[2_-QZ^HZJS>46[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\<T$LbE Z_LW[G\343\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY7Y+SXNMXN9?5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S=W%YRBZT468Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV:R.T][KWE^=11^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_0[)OgB%YRCZXB[67>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT5\,V[CBUM<80Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^3Z&\UGYY;;;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ>Q#[PXNP@]0><]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ4^*BhO&\UFYUMV529V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW;S!U^DGV@353\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY5Y+SXD\^>86[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\>T$^SUA]CX7;?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU8]/EmL+SXE\RHU8=4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR=V"XQIDSG66>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT7\,V[ISS==1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_2[)]VRD^NW:8:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP4P HnI,V[HS_KP?87X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]?U'_TJI\J539V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW5S!U^NVP02<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ:^*PY_G[IR955Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S0W%KcF!U^OV\F_2;2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX=X(RWONYI8<4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR3V"XQCUU77?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU6]/W\\JTDQ=i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,W969<m1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-P8469<j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-P8483k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.Q?6;2d3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/R>0:1e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ S=6=0f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!\<4<7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"]36?6`?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#^28>5a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$_1614b9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%X040;6:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QNDEP\M969<?1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+RTXIMNYSD2>>548Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"Y]_@FGVZO;:7>=7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVKOH_QF<2<72>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]B@ATXA5>58;5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTMIJ]_H>6:10<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.UQ[DBCZVC7:3:9;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%\^ROKDS]J8283>2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,SWYFLMXTE161479V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PAEFQ[L:>6=<0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG30?64?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!XR^FBPDYN48:58:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>25;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0<<1469V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:6;7><7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVNJXLQF<06=02=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/VP\@DRFW@6:93:8;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%\^RJNT@]J8409<>1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+RTXLH^JSD2>7?64?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!XR^FBPDYN48258:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>2=;213\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0<0;7:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QKAUC\M9476==0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG320<73>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA5892994U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&]YSIO[A^K?6683?2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,SWYCI]KTE1<;>558Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"Y]_ECWEZO;:<4?;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(_[UOMYOPI=05:11<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.UQ[AGSIVC7>:0;7:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QKAUC\M94?6==0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG328<72>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA5858:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>04;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0>?1469V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:4:7><7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVNJXLQF<21=02=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/VP\@DRFW@6883:8;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%\^RJNT@]J8639<?1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+RTXLH^JSD2<>558Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"Y]_ECWEZO;<<4?;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(_[UOMYOPI=65:11<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.UQ[AGSIVC78:0;7:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QKAUC\M92?6==0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG348<72>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA5>58:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>64;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB08?1469V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:2:7><7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVNJXLQF<41=02=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/VP\@DRFW@6>83:8;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%\^RJNT@]J8039<>1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+RTXLH^JSD2:6?64?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!XR^FBPDYN4<=58:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>6<;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0871479V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:26==0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG361<73>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA5<:2994U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&]YSIO[A^K?2783?2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,SWYCI]KTE18<>558Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"Y]_ECWEZO;>=4?;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(_[UOMYOPI=46:11<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.UQ[AGSIVC7:;0;7:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QKAUC\M9006==0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*QUWMK_MRG369<73>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA5<22984U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&]YSIO[A^K?2;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0:>1469V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:097><7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVNJXLQF<60=02=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/VP\@DRFW@6<?3:8;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%\^RJNT@]J8229<>1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+RTXLH^JSD285?64?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!XR^FBPDYN4><58:5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'^XTHLZN_H>43;203\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB0:61469V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#Z\PD@VB[L:017>=7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)PZVNJXLQF<6<73>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ WS]GEQGXA52;2984U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&]YSIO[A^K?<;213\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-TVZBF\HUB040;1:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$[_QJN^K7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]`kiYflmxThaw30?6`?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^alhZgcl{Uo`t2>>5a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_bmo[dbczVngu1<14b9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPcnn\eabuWmfr0>0;c:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQlom]b`atXles783:l;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRm`l^cg`wYcdp6>29j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZbkq5?5=9j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6;29j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6:29j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6929j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6829j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6?29j4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnll6>29k4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZqnllUyy:;;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>3:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;;29;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=32:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;929;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=30:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;?29;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=36:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;=29;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=34:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;329;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=3::12<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5;5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<32=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4;;5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<30=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4;95885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<36=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4;?5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<34=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4;=5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<3:=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4;35895Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<3<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;94?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo330<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;;4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo332<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;=4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo334<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;?4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo336<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;14?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo338<70>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;;7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2;0?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:397>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2;2?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:3;7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2;4?67?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:36=>0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1;1459V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPd`vb8383<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k7;3:;;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>;:12<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi535855Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nT~byPaefq858312_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYug~Ujhi|311<7<>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]qkrYflmx7=3:7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhR|`w^cg`w:56=20Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcW{e|Sljkr=1=0==R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\vjqXimny090;8:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQ}ov]b`at;=7>37X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVxd{Rokds>5:1><]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[wipWhno~191499V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPrnu\eabu414?46[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUyczQndep?=;243\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`ZthVoe885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nT~byPeo]b00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\vjqXmgUi=;5Z0.K\JJYC&\UB@L!Z_EMVP7d<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&IF\R\JSDV01>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVCEXNO__G,V[FGW_L:896[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^KMPFGWWO$^SNO_WD36g>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZECGGO$ERWJSMWW2+OXQLYT^]C!I^[FWZIUMN$DYYQ]EF72?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[FBHFL%BSTK\LTV5*LY^MZUY\@ Z_LW[B2343\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWJNDBH!F_XGPHPR1&@URI^Q]PL,V[VTK;;UJ9>5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQLDNLF+LY^MZF^X; F_XGP[WVJ&\UX^A==_C64?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[FBHFL%BSTK\LTV5*VTKWD_S8:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQLDNLF+LY^MZF^X; \RM]R742?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWJNDBH!F_XGPHPR1&ZXGS\2?>5:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\GAIIM&CTUH]CUU4-WWJXY5;5995Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQLMQPFW@R(AVSN_A[[6/K\]@UXZYG%YRCZXG562>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZEJX[OXIY!F_XGPHPR1&@URI^Q]PL,V[VTK;;UJ9;5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQLMQPFW@R(AVSN_A[[6/K\]@UXZYG%YR]]L20\F1g<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXKDZYI^K[/H]ZAVJR\?$X^AQ^306a?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[FKWZLYNX"GPYDQOQQ0)[[FT]1>14c9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]@IUTB[L^$ERWJSMWW2+UUDV[7=3;n;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_OQ3+LY^MZF^X; F_XGP[WVJ&@URI^Q@RDE-KPRXZLM>>6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR@\0.K\]@UK]]<%ERWJS^PSI+SXE\RM;ROM539V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW5)NWPOX@XZ9.H]ZAVYUXD$^S@[WF6]@@1`<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXFZ:$ERWJSMWW2+OXQLYT^]C!U^OV\C>292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX<"GPYDQOQQ0)AVSN_R\_M/W\WWJ4:VK>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR@\0.K\]@UK]]<%ERWJS^PSI+SX[[F8>RL:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP4*OXQLYGYY8!I^[FWZTWE'_T__B<2^A65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT8&CTUH]CUU4-MZ_B[VX[A#[PSSN06ZB312_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX<"GPYDQOQQ0)[[FTAXV8<1<7=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT8&CTUH]CUU4-WWJXE\R<0<0;6:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP4*OXQLYGYY8!SSN\IP^?<11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UE_=!F_XGPHPR1&ZXGS\=><1<7<>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT8&CTUH]CUU4-WWJXY:;7=3:7;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_OQ3+LY^MZF^X; \RM]R74:56=<0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_TB^> I^[FWISS>'YY@R_30?65?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU7'@URI^BZT7,PVIYV484?:6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR@\0.K\]@UK]]<%__BPQ=0=03=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[9%BSTK\LTV5*VTKWX6828o4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR3,MZ_B[E__:#GPYDQ\VUK)AVSN_RA]EF,LQQYUMN?97X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]>/H]ZAVJR\?$BSTK\_SRN*PYJ]QL<SLL:2:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP5*OXQLYGYY8!I^[FWZTWE'_TAXVI7^AG0c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[8%BSTK\LTV5*LY^MZUY\@ Z_LW[B=363\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWGY:#DQVERNVP3(NWPOXS_^B.T]PVI55WH?:7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]>/H]ZAVJR\?$BSTK\_SRN*PYTZE99SO;>;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_OQ2+LY^MZF^X; F_XGP[WVJ&\UX^A==_B72?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU6'@URI^BZT7,J[\CTW[ZF"XQ\RM11[A2>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWGY:#DQVERNVP3(TZEUFYU930?6:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU6'@URI^BZT7,PVIYJ]Q=7=3:9;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_OQ2+LY^MZF^X; \RM]NQ]>302_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX="GPYDQOQQ0)[[FT]>?30?6;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU6'@URI^BZT7,PVIYV;86:2964U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR3,MZ_B[E__:#]]L^S05949<?1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UE_<!F_XGPHPR1&ZXGS\2?>548Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\JV7(AVSN_A[[6/QQHZW;97>=7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]>/H]ZAVJR\?$X^AQ^<3<72>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT9&CTUH]CUU4-WWJXY5958:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQ\CD-J[\CTD\^="XQ\RMA22@2?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWZIF\NK I^[FWISS>'_T__B<2438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\WFTT\&CTUH]CUU4-MZ_B[VX[A#[PMTZE305<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SX[JXXX"GPYDQOQQ0)AVSN_R\_M/W\WWJ4:VK>?6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR]LRRV,MZ_B[E__:#GPYDQ\VUK)]VYY@><PB558Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\WFTT\&CTUH]CUU4-WWJXY:;?46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR]LRRV,MZ_B[E__:#]]L^S?4;2?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWZIY_Y!F_XGPHPR1&ZXGS\2>>558Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\SFC(AVSN_A[[6/W\WWJD9?O?56[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YRYGCLR@A*OXQLYGYY8!U^QQH64312_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]V]GO@^LE.K\]@UK]]<%YR]]L201=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ([JD_SNK=a:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,WFHSWJG[>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/RAMPZEJXVIN>n5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/RAMPZEJXV[9o6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B SBLW[WCTM]>;7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#NO__@FGVZhbp}6;29>4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ C@R\EABUWgosx1?1419V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-@EUYFLMXTbhv{<3<74>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*EFXVKOH_Qaeyv?7;273\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'JK[SLJKR^lf|q:36=:0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$OL^PAEFQ[kc|5?58=5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!LAQ]B@ATXflr0;0;0:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.ABTZGCL[Ueiuz37?63?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+FGWWHNO^R`jxu>;:16<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(KHZTMIJ]_og{p9?9<01^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS=Q[O^47O+@X[LFP<P Z_RGO0d=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW9U_CR8;K/D\W@J\99W%YR]JL5c8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZ6X\FU=8F I_RGO_47Z&\UXIA:n;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]3[QIX>=A%JR]JLZ31Y+SX[LF?m6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GP0^VL[32L&OUXIAU>3\,V[VCK<h1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS=Q[O^47O+@X[LFP=9S!U^QFH1g<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AV:TXBQ94J,E[VCKS8?V"XQ\EM6:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LY7W]ET:9E!F^QFH^7Z&\UXIA:6;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]3[QIX>=A%JR]JLZ0^*PYTME>27X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ?_UM\21M)NVYN@V=R.T]PAI2>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@U;SYAP65I-BZUBDR>V"XQ\EM6:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LY7W]ET:9E!F^QFH^3Z&\UXIA:6;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]3[QIX>=A%JR]JLZ4^*PYTME>27X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ?_UM\21M)NVYN@V9R.T]PAI2>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@U;SYAP65I-BZUBDR2V"XQ\EM6:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LY7W]ET:9E!F^QFH^?Z&\UXIA:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]3[QIX>=A%ER]]L/W\W@J_=81^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSD@[C@R-BZEFXVKOH_U?]/W\GDVXIMNY985Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY3Y+SXKHZTMIJ]_LW[17=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW@D_OL^!F^ABTZGCL[Q;Q#[PiBCS[DBCZ<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ERGATBCS*CYDIYUJHI\T1\,V[FGWWHNO^8;4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX5X(RWJK[SLJKR^OV\04<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVCEXNO_.G]@EUYFLMXP=P Z_hABTZGCL[?:7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQFNUABT+@XKHZTMIJ][3_-QZEFXVKOH_;:;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_7[)]VIJ\ROKDS]NQ]353\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UBBYMNP/D\GDVXIMNYW?S!U^k@EUYFLMX>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPIOV@EU(AWJK[SLJKRZ1^*PYDIYUJHI\:5:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^5Z&\UHM]QNDEP\IP^2:2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTECZLAQ,E[FGWWHNO^V=R.T]jGDVXIMNY9<5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY7Y+SXKHZTMIJ]549V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[LHSKHZ%JRMNP^CG@W]3U'_TOL^PAEFQ[HS_=;1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSD@[C@R-BZEFXVKOH_U;]/W\mFGWWHNO^8?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX1X(RWJK[SLJKR478Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZOI\JK["KQLAQ]B@AT\=T$^SNO__@FGVZKRP<80Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ERGATBCS*CYDIYUJHI\T5\,V[lEFXVKOH_;>;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_3[)]VIJ\ROKDS76?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYNF]IJ\#HPC@R\EABUS?W%YRMNP^CG@WYJ]Q?97X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQFNUABT+@XKHZTMIJ][7_-QZoDIYUJHI\:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^1Z&\UHM]QNDEP61>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXAG^HM] I_BCS[DBCZR=V"XQLAQ]B@ATXE\R>>6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPIOV@EU(AWJK[SLJKRZ5^*PYnKHZTMIJ]509V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[LHSKHZ%JRMNP^CG@W]?U'_TOL^PAEFQ10=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW@D_OL^!F^ABTZGCL[Q3Q#[PC@R\EABUWD_S9?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY;Y+SXaJK[SLJKR438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZOI\JK["KQLAQ]B@AT\1T$^SNO__@FGV03<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVCEXNO_.G]@EUYFLMXP5P Z_BCS[DBCZVG^T8<4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX=X(RW`IJ\ROKDS71?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.AJ8482:2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)DA5859?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$OD2<>408Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/BK?0;353\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*EN4<4>>6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%HE181539V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ CH>4:04<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+FO;07?97X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&IB040:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!K<1<65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-G848292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)C4;4>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%O0>0:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!K<5<65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-G808292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)C4?4>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%O0:0:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!K<9<65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-G8<82l2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S9W%KcF!U^OV\F_202_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S9W%YRHKRD74?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX4X(RWE__945Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV>R.T][KWE^=m1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(OR;V"J`G.T]NQ]E^=11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(OR;V"XQIDSG63>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-D_4[)]VF^X874U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU>]/W\\JTDQ<n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ9Q#IaH/W\IP^DQ<20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ9Q#[PFEPF12=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,C^4Z&\UGYY;6;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT2\,V[]IUKP?o7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP?P HnI,V[HS_KP?37X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP?P Z_GFQA01<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+B]4U'_T@XZ:9:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[2_-QZ^HZJS>h6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW9S!GoJ-QZKRPJS>46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW9S!U^DGV@303\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*A\<T$^SA[[589V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ6^*PY_G[IR9i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV;R.FlK*PYJ]QIR955Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV;R.T]E@WC2?2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S<W%YRBZT4;8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY6Y+SXPFXHU8j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU9]/EmL+SXE\RHU864U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU9]/W\BATB=>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(OR<V"XQCUU7:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX2X(RWQEYOT;k;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT7\,DjM(RWD_SOT;7;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT7\,V[CBUM<=0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ<Q#[PLTV6=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-D_2[)]VRD^NW:d:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[9_-CkN)]VG^TNW:8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[9_-QZ@CZL?<7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP4P Z_MWW1<=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,C^>Z&\USC_MV599V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ;^*PYAL[O>;6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW4S!U^NVP0?<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+B]>U'_TTB\LY438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/R>3:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+V:66<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'Z6928?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#^2<>438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/R>7:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+V:26<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'Z6=28?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#^28>438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/R>;:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+V:>6=20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!LI=3=0==R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&IB0?0;8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+FO;;7>37X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ CH>7:1><]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%HE1;1499V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*EN4?4?46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/BK?3;2?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$OD27>5:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)DA5358:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.F?4;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$H1?1469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*B;:7><7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ D=1=02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&N783:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,@939<>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"J36?64?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(L5=58:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.F?<;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$H171529V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\8T$LbE Z_LW[G\2b3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV>R.T]E@WC3l2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU?]/W\HPR3n2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU?]/W\\JTDQ<90Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[0_-CkN)]VG^TNW;e:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]6U'_TJI\J4e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\9T$^SA[[4g9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\9T$^SUA]CX70?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR8V"J`G.T]NQ]E^<l1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"IT2\,V[CBUM=n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[3_-QZJR\=l0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[3_-QZ^HZJS>?6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY0Y+Ai@'_TAXVLY5g8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S:W%YRHKRD6g?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR9V"XQCUU6e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR9V"XQWOSAZ16=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP8P HnI,V[HS_KP>n7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ GZ6^*PYAL[O?h6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY7Y+SXD\^?j6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY7Y+SXPFXHU8=4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_0[)OgB%YRCZXB[7a>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'NQ>Q#[PFEPF0a=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP9P Z_MWW0c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP9P Z_YMQG\343\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV8R.FlK*PYJ]QIR8h5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.EX2X(RWONYI9j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_3[)]VF^X9h4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_3[)]VRD^NW:3:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]0U'MeD#[PMTZ@]1c<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%LW:S!U^DGV@2c3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV9R.T]OQQ2a3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV9R.T][KWE^=:1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"IT8\,DjM(RWD_SOT:j;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,C^>Z&\UMH_K;d:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]?U'_T@XZ;f:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]?U'_TTB\LY5g8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S0W%YRHKRD6g?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR3V"XQCUU6e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR3V"XQWOSAZ02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&Y7<3:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,W979<>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"]32?64?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR([5958:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.Q?0;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$_1;1469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*U;>7><7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ S=5=02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&Y743:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,W9?9;?1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%^SO\D0248Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,QZDUC82>7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#XQ\COV\GHV(AVIXSJOAD/W\GVY@IGNT__B I^T5*PYD[VMJBIQ\RM]U2*OX]ZOT^]CPND2-QZAFFMUX^AQ\EU:b?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+PYTKG^TO@^ I^AP[BGIL'_TO^QHAOF\WWJ(AV\="XQLS^EBJAYTZEU]:"GPURG\VUKXFL:%YRINNE]PVIYTM]UF_HZ76:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.W\SFHSWAIF\"GPCR]DEKB)]VIXSJOAD^QQH*OX^?$^SN]PG@LG[VTKW_<$ER[\E^PSIZHB8'_TKL@K_RPO[VCS0k1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%^SZMAT^J@IU)NWJYTKL@K.T]@WZAFFMUX^A!F_W4-QZETWNKEHR]]L^T5+LYR[LUY\@QAE1,V[BGILVYY@R]JT^OPAQ>13\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'\U\OCZPLBOS+LYD[VMJBI Z_BQ\CDHCWZXG#DQY6/W\GVY@IGNT__BPV7-J[PUBW[ZFSCK?.T]DEKBX[[FT_HZ7b:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.W\SFHSWEIF\"GPCR]DEKB)]VIXSJOAD^QQH*OX^?$^SN]PG@LG[VTKW_<$ER[\E^PSIZHB8'_TKL@K_RPO[VCSWDYNX>l4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ cge\`drf4948n6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"mig^fbpd:66:h0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$okiPd`vb8784j2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&imkRjnt`>0:6d<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(komThlzn<5<74>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*eaoVnjxlQyeb>24;273\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'jllSio{a^tfg9766=:0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$okiPd`vb[scd48858=5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!lff]geqgX~li7=>0;0:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.aecZbf|hU}in2>4?63?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+f``WmkmRxjc=36:16<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(komThlzn_wg`8409;o1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%hjjQkauc\r`e;979m7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#nhh_ecweZpbk585?k5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!lff]geqgX~li7?3=i;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/bdd[agsiV|no1:13g9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-`bbYci}kTzhm35?1e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+f``WmkmRxjc=4=7c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)dnnUomyoPvda?3;5a3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'jllSio{a^tfg9>9;o1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%hjjQkauc\r`e;179h7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#dMNP^CG@W:76:i0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$eNO__@FGV979;j1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%bOL^PAEFQ8784k2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&cHM]QNDEP?7;5d3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'`IJ\ROKDS>7:6e<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(aJK[SLJKR=7=7f=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)nKHZTMIJ]<7<0g>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*oDIYUJHI\37?1`?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+lEFXVKOH_27>2a8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,mFGWWHNO^171399V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-jWFHS494846[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"g\COV?5;5?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'`YHBY2=>2:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,mVEI\595?55Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!fSBLW818402_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&cXOCZ35?1;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+lUDF]6=2>64U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ iRAMP919;11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%b_N@[<9<0<>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*oTKG^753<j;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[VEI\VIF\R_=8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZRUAN827X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_UPJC54>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SY\FG00e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RW^IEXRFLMQ]R6c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\U\OCZPLBOS[T4>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%\OCZPCD0a?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)PKG^TDNC_2d9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+REI\VBHA]QLE3f8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*QDF]UCO@^PQ3`8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*QDF]UGO@^=e:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,SFHSWEIF\RMJ2e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+REI\VFHA]Q^2e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1>12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1?12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1<12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1=12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1:12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1;12e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1812e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1912e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1612e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+f``Wmkm1712b9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+lEFXV]YSH@=d:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,mQTNONOYSD@=e:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,mQTNONOYSB[[3`9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO[LYTZE^TBHQ>.T]@@JHBWDYNX>j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L^K\WWJSWGOT=#[PCLRQAVCSWDYNX>64U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L^K\WWJSWGOT=#[PNR2\IVCS;11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XGSDQ\RMV\J@Y6&\UE_<QBSDV0e>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJXAVYY@YQAE^3-QZUDZZ^TA^K[259V4*OXFFUO"XQFL@-V[WUS'NUY_YU?]/W\VVR5<2_;#DQAO^F-QZOKI&_T^^Z G^PPP^7Z&\UY_Y<;;T2,MZHHWM$^SDBN/T]QWQ)@W[Y_W?S!U^PPP72<]9%BSCAPD/W\MIG(]VXXX"IPRRVX7X(RW[Y_>95Z0.K\JJYC&\UB@L!Z_SQW+BYU[]Q?Q#[PRRV10>S7'@UECRJ!U^KOE*SXZZ^$KR\\TZ7^*PYU[]8?7X> I^LL[A(RW@FJ#XQ]SU-D[WUSS?W%YR\\T368Q5)NWGETH#[PIMC,QZTT\&MT^^ZT7\,V[WUS:91^<"GPNN]G*PYNDH%^S_][/ICOPZvrdzo:56[?/H]MKZB)]VCGM"[PRRV,TJT582_;#DQAO^F-QZOKI&_T^^Z PSG\V@UB\98;7X> I^LL[A(RW@FJ#XQ]SU-SV@YUMZO_=?64U1-J[KIXL'_TEAO U^PPP*SXI[GTTKK]/T]@H@GU:>1^<"GPNN]G*PYNDH%^S_][/T]BVHY_NLX$YRJ@UU0;?P6(AVDDSI Z_HNB+PYU[]%^SL\B_YDFV*SXLF__<?64U1-J[KIXL'_TEAO U^PPP*SXI[GTTKK]/T]GKPR6;=1^<"GPNN]G*PYNDH%^S_][/T]BVHY_NLX$YRIJN^FFHD_\9T$^SKJ<4:W3+LYIGVN%YRGCA.W\VVR(]VKYARVIES-V[BCIWMOGMTU=]/W\BA533\:$ER@@_E,V[LJF'\UY_Y!Z_@PN[]@BZ&_TKH@PDDNB]^5Z&\UMH>:4U1-J[KIXL'_TEAO U^PPP*SXI[GTTKK]/T]DAKYCMEKRW9S!U^DG6==R8&CTBBQK.T]JHD)RW[Y_#XQNRL][B@T(]VXMH_K=8:W3+LYIGVN%YRGCA.W\VVR(]VKYARVIES-V[Q@CZL8h7X> I^LL[A(RW@FJ#XQ]SU-V[DTJWQLN^"jfn^nbpfnbl;?0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#dMCR3:8Q5)NWGETH#[PIMC,QZTT\&_TM_CPXGGQ+lBNF5:5>55Z0.K\JJYC&\UB@L!Z_SQW+PYFZDUSJH\ iEKM8485>2_;#DQAO^F-QZOKI&_T^^Z U^CQIZ^AM[%bHB[[2e9V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,mAIR\Vngu1>12e9V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,mAIR\Vngu1?12e9V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,mAIR\Vngu1<12e9V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,mAIR\Vngu1:1289V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+PYDDLKY>55Z0.K\JJYC&\UB@L!Z_SQW+PYOIE^TTKK]/T]GKPR512_;#DQAO^F-QZOKI&_T^^Z U^JBHQY_NLX$YRJ@UU21=>S7'@UECRJ!U^KOE*SXZZ^$YRFNLU][B@T(]VNDYY?<5:W3+LYIGVN%YRGCA.W\VVR(]VBJ@YQWFDP,QZABFVNN@LWT1\,V[CB4=2_;#DQAO^F-QZOKI&_T^^Z U^JBHQY_NLX$YRIJN^FFHD_\:T$^SKJ=9:W3+LYIGVN%YRGCA.W\VVR(]VBJ@YQWFDP,QZTAL[O956[?/H]MKZB)]VCGM"[PRRV,QZNFD]USJH\ U^VE@WC5l2_;#DQAO^F-QZOKI&_T^^Z U^JBHQY_NLX$hd`Pl`v`l`b5>2_;#DQAO^F-QZOKI&_T^^Z U^JBHQY_NLX$eNB]289V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+lBNF5:5>45Z0.K\JJYC&\UB@L!Z_SQW+PYOIE^TTKK]/hFJJ979:>1^<"GPNN]G*PYNDH%^S_][/T]KEIRXPOOY#dJ@UU0f?P6(AVDDSI Z_HNB+PYU[]%^SEOCT^ZEAW)nLF__Sibv<1<1a>S7'@UECRJ!U^KOE*SXZZ^$YRFNLU][B@T(aME^XRjcy=0=5g=R8&CTBBQK.T]JHD)RW[Y_#XQ_OS3g?P6(AVDDSI Z_HNB+PYU[]%^S]\\T13g?P6(AVDDSI Z_HNB+PYU[]%^S]\\T03`?P6(AVDDSI Z_HNB+PYU[]%^S_][00d8Q5)NWGETH#[PIMC,QZTT\&cYI^K[<1<11>S7'@UECRJ!U^KOE*SX[]K_#LM[RDQFPZvrdzo9<6[?/H]MKZB)]VCGM"[PSUCW+DESWmymy<:;T2,MZHHWM$^SDBN/T]PPDR(KHZT^H]JT^fo}47a3\:$ER@@_E,V[LJF'\UXXLZ DHPW]ZB79o1^<"GPNN]G*PYNDH%^S^ZNT.FJVQ_XL88;7X> I^LL[A(RW@FJ#XQ\T@V,@LTSQVYN@?<4U1-J[KIXL'_TEAO U^QWEQ)CA[^RSi}{au07?P6(AVDDSI Z_HNB+PYT\H^$H^ZNT^gm[aj~9;>0Y=!F_OM\@+SXAEK$YR][AU-GWQGSWldThaw=259V4*OXFFUO"XQFL@-V[VRF\&NXXLZPeo]gh|5592_;#DQAO^F-QZOKI&_T_YO[/EQWEQYkghn9j6[?/H]MKZB)]VCGM"[PSUCW+CYT[]K_W=S!I^QWEQ(RWZ^JX>>4U1-J[KIXL'_TEAO U^QWEQ)AWZY_MYU>0\,J[VRF\'_T_YO[2g9V4*OXFFUO"XQFL@-V[VRF\&LT_^ZNTZ3^*LYT\H^%YR][AU0e?P6(AVDDSI Z_HNB+PYT\H^$JR]\T@VX6X(NWZ^JX#[PSUCW6c=R8&CTBBQK.T]JHD)RWZ^JX"HPSRVBP^5Z&@UXXLZ!U^QWEQ4a3\:$ER@@_E,V[LJF'\UXXLZ F^QPPDR\<T$BS^ZNT/W\WQGS:o1^<"GPNN]G*PYNDH%^S^ZNT.D\WVRF\R?V"DQ\T@V-QZUSI]8m7X> I^LL[A(RW@FJ#XQ\T@V,BZUT\H^P:P F_RVBP+SX[]K_>k5Z0.K\JJYC&\UB@L!Z_RVBP*@X[Z^JXV9R.H]PPDR)]VY_MY<i;T2,MZHHWM$^SDBN/T]PPDR(NVYXXLZT8\,J[VRF\'_T_YO[2g9V4*OXFFUO"XQFL@-V[VRF\&LT_^ZNTZ;^*LYT\H^%YR][AU07?P6(AVDDSI Z_HNB+PYT\H^$KR@\[1_-QZHTY;>0Y=!F_OM\@+SXAEK$YR][AU-D[KU\9T$^SC]^259V4*OXFFUO"XQFL@-V[VRF\&MTB^U=]/W\JVW5<2_;#DQAO^F-QZOKI&_T_YO[/F]MW^5Z&\UE_\<;;T2,MZHHWM$^SDBN/T]PPDR(OVDXW9S!U^LPU72<]9%BSCAPD/W\MIG(]VY_MY!H_OQX1X(RWGYZ>95Z0.K\JJYC&\UB@L!Z_RVBP*AXFZQ=Q#[PNRS10>S7'@UECRJ!U^KOE*SX[]K_#JQASZ5^*PYI[X8?7X> I^LL[A(RW@FJ#XQ\T@V,CZHTS1W%YR@\Q368Q5)NWGETH#[PIMC,QZUSI]%LSC]T9\,V[KUV:01^<"GPNN]G*PYNDH%^S^ZNT.Onq}YCA[^RSi}{au3267=R8&CTBBQK.T]JHD)RWZ^JX"@\_eqweq:76;80Y=!F_OM\@+SXAEK$YR][AU-MWZbt|h~7=3<=;T2,MZHHWM$^SDBN/T]PPDR(FZUoyo{<3<16>S7'@UECRJ!U^KOE*SX[]K_#C]Pdrvbp959:;1^<"GPNN]G*PYNDH%^S^ZNT.LP[ausi}6?2?<4U1-J[KIXL'_TEAO U^QWEQ)I[Vnxxlz35?01?P6(AVDDSI Z_HNB+PYT\H^$B^Qksucw8385:2_;#DQAO^F-QZOKI&_T_YO[/OQ\`vrf|5=5>?5Z0.K\JJYC&\UB@L!Z_RVBP*HTWmymy27>308Q5)NWGETH#[PIMC,QZUSI]%E_Rj|t`v?=;7b3\:$ER@@_E,V[LJF'\UXXLZ NR]okdb5=2_;#DQAO^F-QZOKI&_T_YO[/RVBP@Yc{}k0=0=5:W3+LYIGVN%YRGCA.W\WQGS'Z^JXHQksucw8486n2_;#DQAO^F-QZOKI&_T_YO[/UFL[kc|8i0Y=!F_OM\@+SXAEK$YR][AU-V[DTJ9k1^<"GPNN]G*PYNDH%^S^ZNT.W\GW443\:$ER@@_E,V[LJF'\UXXLZ U^FJVQ_XNMIN>>5Z0.K\JJYC&\UB@L!Z_RVBP*SXL@X_URHKPD01?P6(AVDDSI Z_HNB+PYT\H^$YRJFRU[\HAE6k2_;#DQAO^F-QZOKI&_T_YO[/T]GWI423\:$ER@@_E,V[LJF'\UXXLZ U^FPH4)RWJFNM_<;;T2,MZHHWM$^SDBN/T]PPDR(]VNX@<!Z_EMVP73<]9%BSCAPD/W\MIG(]VY_MY!Z_EQO5*SXLF__<?;4U1-J[KIXL'_TEAO U^QWEQ)RWMYG="[PDNWW567<]9%BSCAPD/W\MIG(]VY_MY!Z_EQO5*SXOLDTHHBNYZ3^*PYAL;?0Y=!F_OM\@+SXAEK$YR][AU-V[AUK9&_T^KJ]E378Q5)NWGETH#[PIMC,QZUSI]%^SI]C1.W\PCBUM;30Y=!F_OM\@+SXAEK$YR][AU-V[AUK9&nbbRbntbjf`74<]9%BSCAPD/W\MIG(]VY_MY!Z_EQO5*oDD[8>7X> I^LL[A(RW@FJ#XQ\T@V,QZBTD8%bHD@30?06?P6(AVDDSI Z_HNB+PYT\H^$YRJ\L0-j@LH;978j7X> I^LL[A(RW@FJ#XQ\T@V,QZBTD8%bHB[[_enz8585i2_;#DQAO^F-QZOKI&_T_YO[/T]GWI7(aME^XRjcy=3=5a=R8&CTBBQK.T]JHD)RWZ^JX"[PDRN15a=R8&CTBBQK.T]JHD)RWZ^JX"[PDRN05f=R8&CTBBQK.T]JHD)RWZ^JX"[PDRP2g>S7'@UECRJ!U^KOE*SX[]K_#XQJCS3g?P6(AVDDSI Z_HNB+PYT\H^$YRHZLM1b?P6(AVDDSI Z_HNB+PYT\H^$YRCZX.W\GVYJ]Q%B=#[PMTZ1+HkrpVE:=>?<e:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH989:S^Y?3`9V4*OXFFUO"XQFL@-V[VRF\&_TAXV U^AP[HS_'@;%YRCZX3-Nip~XG8;<=>k4U1-J[KIXL'_TEAO U^QWEQ)RWD_S#XQLS^OV\*O6&\UFYU< Mlw{[J76?8UX[==n;T2,MZHHWM$^SDBN/T]PPDR(]VG^T"[PCR]NQ])N9'_TAXV=/Lov|ZI691?8m6[?/H]MKZB)]VCGM"[PSUCW+PYJ]Q%^SN]PMTZ,M4(RWD_S>"Cbuy]L5761;01^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO0027d=R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<<<92c8Q5)NWGETH#[PIMC,QZUSI]%^S@[W/T]@WZKRP&C:"XQBUY0,IhsWF;9:==n;T2,MZHHWM$^SDBN/T]PPDR(]VG^T"[PCR]NQ])N9'_TAXV=/Lov|ZI6:088m6[?/H]MKZB)]VCGM"[PSUCW+PYJ]Q%^SN]PMTZ,M4(RWD_S>"Cbuy]L5654;h1^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO01646g<]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?<891b?P6(AVDDSI Z_HNB+PYT\H^$YRCZX.W\GVYJ]Q%B=#[PMTZ1+HkrpVE:8=;<a:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH9=>8?l5Z0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K421<:k0Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N36405>3\:$ER@@_E,V[LJF'\UXXLZ U^OV\*SXKZUFYU!F1/W\IP^5'Dg~tRA>521b?P6(AVDDSI Z_HNB+PYT\H^$YRCZX.W\GVYJ]Q%B=#[PMTZ1+HkrpVE:9>><a:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH9<>;?l5Z0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K432::k0Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N361=5f3\:$ER@@_E,V[LJF'\UXXLZ U^OV\*SXKZUFYU!F1/W\IP^5'Dg~tRA>59;0=>S7'@UECRJ!U^KOE*SX[]K_#XQBUY-V[FUXE\R$E< Z_LW[6*Kj}qUD=;:;2:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH9?=?S^Y?_RU37`=R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<884^QT56c<]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?981]PS55b3\:$ER@@_E,V[LJF'\UXXLZ U^OV\*SXKZUFYU!F1/W\IP^5'Dg~tRA>692\WR74i2_;#DQAO^F-QZOKI&_T_YO[/T]NQ])RWJYTAXV I0,V[HS_:&GfyuQ@16247==R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<6<9:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH90::o6[?/H]MKZB)]VCGM"[PSUCW+PYI[E9;7X> I^LL[A(RW@FJ#XQ\T@V,QZTB[L^TIIIJ/H]K6I(RWME^X?l4U1-J[KIXL'_TEAO U^QWEQ)RW[OXIYQJDFG,QZBH]]:9n6[?/H]MKZB)]VCGM"[PSUCW+PYUMZO_SHJHE.W\@JSS9;i0Y=!F_OM\@+SXAEK$YR][AU-V[WCTM]UNHJK iEMVP969:j1^<"GPNN]G*PYNDH%^S^ZNT.W\V@UB\VOOKH!fDNWW8486n2_;#DQAO^F-QZOKI&_T_YO[/T]QMVOIO;:0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\JGO>?5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_O@JPn0d8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNTD22b>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@VF571<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&IB0<0=7:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,GL:56;=0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"MF<2<13>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(K@6?2?94U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.AJ8085?2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$OD29>358Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*EN4>49;6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ CH>;:71<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&IB040=6:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,@969:?1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#I2>>348Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*B;:78=7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!K<2<12>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(L5>5>;5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/E>6:70<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&N7:3<9;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-G8285>2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$H161279V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+A:>6:80Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"IT0\,DjM(RWD_SOT<k;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-D_5[)]VLO^H<l;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-D_5[)]VF^X?k4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX4X(RWQEYOT==;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-D_4[)OgB%YRCZXB[1`>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR;V"XQIDSG1g>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR;V"XQCUU0f?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S8W%YRV@RB[06>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR8V"J`G.T]NQ]E^:m1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU=]/W\BATB:j1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU=]/W\HPR5m2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV<R.T][KWE^;;1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU<]/EmL+SXE\RHU?j4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX7X(RWONYI?m4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX7X(RWE__>h5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY0Y+SXPFXHU><4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX0X(@fA$^S@[WCX0g?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S=W%YRHKRD0`?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S=W%YRBZT3g8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\<T$^SUA]CX11?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S<W%KcF!U^OV\F_5l2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV;R.T]E@WC5k2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV;R.T]OQQ4b3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW8S!U^ZLVF_4:2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV8R.FlK*PYJ]QIR>i5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY5Y+SXNMXN>n5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY5Y+SXD\^9i6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ4^*PY_G[IR??5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY4Y+Ai@'_TAXVLY3f8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\?T$^SKJ]E3a8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\?T$^SA[[2d9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]0U'_TTB\LY208Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\0T$LbE Z_LW[G\4c3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW5S!U^DGV@4d3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW5S!U^NVP7c<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP4P Z_YMQG\4c3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW4S!U^DGV@4d3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW4S!U^NVP7c<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP5P Z_YMQG\413\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%X0=0=6:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,W979:?1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#^2=>348Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*U;;78=7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!\<5<12>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR([5?5>;5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/R>5:70<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&Y7;3<9;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-P8=85>2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$_1711b9V4*OXFFUO"XQFL@-V[VRF\&_TXIA=0:W3+LYIGVN%YRGCA.W\WQGS'\U_^DIHES3e?P6(AVDDSI Z_HNB+PYT\H^$e^ZNT=2=65=R8&CTBBQK.T]JHD)RWZ^JX"g\T@V?5586n2_;#DQAO^F-QZOKI&_T_YO[/hQWEQ:668l0Y=!F_OM\@+SXAEK$YR][AU-jWQGS4;4:j6[?/H]MKZB)]VCGM"[PSUCW+lUSI]682<h4U1-J[KIXL'_TEAO U^QWEQ)n[]K_090>f:W3+LYIGVN%YRGCA.W\WQGS'`Y_MY2:>0d8Q5)NWGETH#[PIMC,QZUSI]%b_YO[<7<2b>S7'@UECRJ!U^KOE*SX[]K_#d][AU>4:4`<]9%BSCAPD/W\MIG(]VY_MY!fSUCW8=86n2_;#DQAO^F-QZOKI&_T_YO[/hQWEQ:>6;80Y=!F_OM\@+SXAEK$YR][AU-jWQGSKDNTOH<;;T2,MZHHWM$^SDBN/T]PPDR(aZ^JXNCK_BG\j75<]9%BSCAPD/W\MIG(]VY_MY!fSUCW[FHS4949?6[?/H]MKZB)]VCGM"[PSUCW+lUSI]UHBY2>>318Q5)NWGETH#[PIMC,QZUSI]%b_YO[_BLW8785;2_;#DQAO^F-QZOKI&_T_YO[/hQWEQYDF]682?=4U1-J[KIXL'_TEAO U^QWEQ)n[]K_SN@[<5<17>S7'@UECRJ!U^KOE*SX[]K_#d][AU]@JQ:26;90Y=!F_OM\@+SXAEK$YR][AU-jWQGSWJD_0;0=3:W3+LYIGVN%YRGCA.W\WQGS'`Y_MYQLNU>4:75<]9%BSCAPD/W\MIG(]VY_MY!fSUCW[FHS4149?6[?/H]MKZB)]VCGM"[PSUCW+lUSI]UHBY26>348Q5)NWGETH#[PIMC,QZRUAN%MSCAPTBO@*PYAL[997X> I^LL[A(RW@FJ#XQ[RHE,QZRD'@UXXB\NGD]RQDJ)]VIJ\RL<4:W3+LYIGVN%YRGCA.W\PWO@'\U_O"GPSUMQEBCXY\KG"XQLAQ]GH\1b3\:$ER@@_E,V[LJF'\U_^DI U^V@+LYT\FXJKHQ^U@N-QZUSG[KLIR_ZAM-J[VTK\VDNS< F_OOV[4YSGV>%YRZLL.K\JHSXMX;%YRgKOTV,MZ_B[E__:#[PSSN@53C102_;#DQAO^F-QZOKI&_TX_GH/T]WG*OX[]EYMJKPQTCO*PYT\FXJKHQ^U@N,MZUUD]UEIR?!I^LNQZ7X\FU?"XQ[CM-J[JSSZLM%YRJ@UU7f?P6(AVDDSI Z_HNB+PYSZ@M$YRZL/H]PPJTFOLUZYLB!U^QWKWG@MV[^MA!F_RPOPZHBW8$BSCCZ_0]WKZ2)]V^H@"gKOTV6e>S7'@UECRJ!U^KOE*SX\[CL#XQ[C.K\WQIUINOT]XOC.T]PPJTFOLUZYLB I^QQHQYIMV;%ER@BU^3\PJY3&\U_^DI^439V4*OXFFUO"XQFL@-V[QTNO&_TXN!F_RVLVDABWX_J@#[PSUMQEBCXY\KG#dZ]IFEFV2g<]9%BSCAPD/W\MIG(]V^YEJ!Z_UA,MZRTMXUEI\<!U^V@[@WRI]CDB"GPSSNW[KCX9'CTB@[P1^VL[1(RW]IG#DQAMT]FU4(RW`NDYY!F_XGPHPR1&\UX^AM>6D47?P6(AVDDSI Z_HNB+PYSZ@M$YRZL/H]WW@WXFL[9"XQ[C^GRQDRNGG%BS^\CT^LF[4(NWGG^S<Q[O^6-QZRDD&CTCXZ]EF,V[AIR\<k0Y=!F_OM\@+SXAEK$YRZ]IF-V[QE(AV^XI\QAEP0-QZRDWL[^MYG@N.K\WWJSWGOT=#GPNLW\5ZRHW=$^SYMC/hFLQQ313\:$ER@@_E,V[LJF'\U_^DI U^V@+LYS[L[TBH_=.T]WGZCV]H^BCC!F_RPOPZHBW8$BSCCZ_0]WKZ2)]V^YEJ_<e:W3+LYIGVN%YRGCA.W\PWO@'\U_O"GPTRGR[KCV:'_TXNQJQTCWMJH(a]XBKJK]259V4*OXFFUO"XQFL@-V[QTNO&_TXN!fC@RWQWC502_;#DQAO^F-QZOKI&_TX_GH/T]WG*oDNNUOMYO30?63?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"GPMB]ZAV(RWDI$HB[[_gnbc37<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/H]NGZ_B['_TAN!F_RPOPZHBW8$BSIAZT^doebYTZEI::#[PDNWW[cjfo<n0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+LYJKVSN_#[PMB-J[VTK\VDNS< F_LAMPZciWZXGO<8!U^O@JQYbf<l0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+LYJKVSN_#[PMB-J[VTK\VDNS< F_LAMPZtt|VYY@N?9.T]NGKRXzz~?56[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)NWDITUH]!U^O@+LYTZE^TBHQ>.T]AVN6312_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-J[HEXQLY%YRCL/H]PVIRXFLU:"XQMRJ37f>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!F_LA\]@U)]VGH#DQ\RMV\J@Y6&\UFOCZ D478Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#DQBC^[FW+SXEJ%BS^\CT^LF[4(RWDIEX"IT0\,V[CBUM<>0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+LYJKVSN_#[PMB-J[VTK\VDNS< Z_LAMP*A\8T$^SA[[579V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$ERCL_XGP*PYJK&CT__B[_OG\5+SXEJD_#JU?]/W\\JTDQ=h0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+LYJKVSN_#[PMB-J[VTK\VDNS< Z_LAMP*U4j2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-J[HEXQLY%YRCL/LAMP6c<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/H]NGZ_B['_TAN!BCOV\ak253\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.K\IFY^MZ$^S@M MBLW[`wXief8j6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)NWDITUH]!U^O@+HEI\Vxxx>j4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'@UFORWJS/W\IF)RWKX@>>j4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'@UFORWJS/W\IF)RWME^X5k4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'@UFORWJS/W\IF)RWNKEHRCNTBJ,MZETWNKEH#[PCR]DEKBX[[F$ERX9.T]@WZAFFMUX^AQY6.K\QVCXZYGTBH>!U^EBJAYTZEUXIY7<;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&CTANQVER,V[HE(]VMJBIQBAUAK+LYD[VMJBI Z_BQ\CDHCWZXG#DQY6/W\GVY@IGNT__BPV7-J[PUBW[ZFSCK?.T]DEKBX[[FT_HZPMRGW07=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC I^O@[\CT&\UFO"mig^fbpd:66=80Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+LYJKVSN_#[PMB-`bbYci}k7>3:=;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&CTANQVER,V[HE(komThlzn<2<76>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!F_LA\]@U)]VGH#nhh_ecwe929<;1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,MZKDWPOX"XQBC.aecZbf|h6>29<4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'@UFORWJS/W\IF)dnnUomyo36?15?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-GKPRX|dzjo6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W=S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P==S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=<S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=?S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=>S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=9S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=8S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=;S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=:S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=5S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=4S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8kh7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9<P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9=P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9>P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9?P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q98P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q99P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9:P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9;P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q94P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q95P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hi0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q9Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9;Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9:Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R99Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R98Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9?Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9>Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9=Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9<Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R93Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R92Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6ij1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R9V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=:V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=;V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=8V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=9V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=>V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=?V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=<V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S==V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=2V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=3V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fk2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S=W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=9W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=8W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=;W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=:W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\==W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=<W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=?W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=>W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=1W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=0W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gd3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\=T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]18T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]19T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1:T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1;T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1<T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1=T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1>T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1?T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]10T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]11T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5de<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]1U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^17U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^16U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^15U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^14U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^13U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^12U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^11U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^10U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^1?U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ea=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^1>U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ef=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^1Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3b`>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=6Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3b`>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=7Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3b`>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=4Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3b`>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=5Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3b`>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=2Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3bg>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_=[)AVCES_OAGD,J[PUBW@D[YYQ]EF]MA5(RWNKEHRJCY0c`?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX3X=X(NW@DT^L@HE/K\QVCXAGZ^XR\JG^LF4+SXOHDOSIBV18:8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y3Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V??]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R;:Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^75U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z30Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V?;]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R;>Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^71U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z34Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V?7]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R;2Q#GPIO]QEKAB&\ULMCJPDM[1===R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^7Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[32^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W??R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S;8V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_75Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[36^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W?;R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S;<V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_71Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[3:^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W?7R.H]JJZTFFNO%YRINNE]GH\4>02_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S;W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X75[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T30_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P??S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\;:W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X71[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T34_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P?;S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\;>W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X7=[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T38_-MZOIW[KEKH Z_FCM@ZBKQ;337X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P?P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]38T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y75X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U;2\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q??P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]3<T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y71X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U;6\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q?;P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]30T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y7=X(NW@DT^L@HE/W\CDHCWMFR>464U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U;]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R?;Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^36U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z71Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V;<]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R??Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^32U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z75Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V;8]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R?3Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^3>U'CTECQ]AOEF*PY@IGNTHAW=999V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z7^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W;>R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S?;V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_34Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[71^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W;:R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S??V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_30Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[75^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W;6R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S?3V"DQFN^PBJBC)]VMJBIQKLX0:<>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_3[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T71_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P;<S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\?;W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X36[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T75_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P;8S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\??W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X32[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T79_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P;4S!I^KM[WGIOL$^SJOAD^FO]7??3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\?T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y;4X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U71\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q3>P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]?;T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y;0X(NW@DT^L@HE/W\CDHCWMFR>464U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U7]/K\MKYUIGMN"XQHAOF\@I_5111^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R3V"DQFN^PBJBC)]VMJBIQKLX0b4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'\UH_RINNE]PVIYQ>&CTY^KPRQO\J@6)]VMJBIQ\RM]PAQg23\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$YRM\_FCM@ZUUDV\=#DQZSD]QTHYIM9$^SJOAD^QQHZUB\VGXIY9i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1>1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?311<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>25;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz597561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i648954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7=9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2>5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=35:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28419091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;9143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86:539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1?1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?321<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>15;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz594561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64;954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7>9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2=5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=05:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28719091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;:143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq869539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1<1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?331<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>05;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz595561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64:954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7?9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2<5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=15:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28619091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;;143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq868539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1=1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?341<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>75;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz592561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64=954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;789070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2;5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=65:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28119091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;<143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86?539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1:1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?351<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>65;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz593561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64<954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;799070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2:5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=75:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28019091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;=143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86>539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?361<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>55;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz590561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64?954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7:9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<295?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=45:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28319091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;>143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86=539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=181819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?371<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>45;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz591561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64>954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7;9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<285?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=55:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28219091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;?143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86<539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=191819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?381<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>;5;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz59>561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i641954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;74908f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<27>6d8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><8<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>3:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18469091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;9843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6:>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1?<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<06=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?508?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:6>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5;<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90<61819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<318<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>2:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18769091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;:843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;69>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1<<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<36=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?608?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:5>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:58<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90?61819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<328<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>1:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18669091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;;843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;68>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1=<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<26=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?708?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:4>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:59<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90>61819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<338<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>0:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18169091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;<843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6?>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1:<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<56=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?008?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:3>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5><25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90961819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<348<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>7:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18069091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;=843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6>>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1;<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<46=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?108?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:2>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5?<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90861819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<358<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>6:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18369091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;>843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6=>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>18<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<76=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?208?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:1>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5<<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90;61819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<368<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>5:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18269091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;?843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6<>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>19<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<66=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?308?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:0>72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5=<25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90:61819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<378<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>4:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18=69091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;0843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;63>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>16<>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<96=3c=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?<;1a3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz69?9<?1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UD^HI!I^[FWZIUMN$^SB\JG268Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#nhh_ecwe969;81^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,`jssW}g{><5Z0.K\JJYC&\UB@L!Z_UPJC*ruanIdbiGa239V4*OXFFUO"XQFL@-V[QTNO&~yejM`neMvp42<]9%BSCAPD/W\MIG(aHXF=55Z0.K\JJYC&\UB@L!fC@RWQWC612_;#DQAO^F-QZOKI&cHM]QKOOG17>S7'@UECRJ!U^KOE*oDIYUEY@Q\ALROAV:76;90Y=!F_OM\@+SXAEK$eNO__OWN[VGJXEOX0<0=3:W3+LYIGVN%YRGCA.k@EUYI]DUXM@^CER>1:75<]9%BSCAPD/W\MIG(aJK[SC[B_RCNTICT4:49?6[?/H]MKZB)]VCGM"gLAQ]MQHYTIDZGI^2;>318Q5)NWGETH#[PIMC,mFGWWG_FS^OBPMGP8085;2_;#DQAO^F-QZOKI&cHM]QAUL]PEHVKMZ6=2?=4U1-J[KIXL'_TEAO iBCS[KSJWZKF\AK\<6<17>S7'@UECRJ!U^KOE*oDIYUEY@Q\ALROAV:?6;90Y=!F_OM\@+SXAEK$eNO__OWN[VGJXEOX040>d:W3+LYIGVN%YRGCA.k@EUYT\H^N0=0>d:W3+LYIGVN%YRGCA.k@EUYT\H^N0<0>9:W3+LYIGVN%YRGCA.kGEQG;;<4:56[?/H]MKZB)]VCGM"gKAUC?738612_;#DQAO^F-QZOKI&cOMYO336<2=>S7'@UECRJ!U^KOE*oCI]K7?50>9:W3+LYIGVN%YRGCA.kGEQG;;04:56[?/H]MKZB)]VCGM"gKAUC?058612_;#DQAO^F-QZOKI&cOMYO340<2=>S7'@UECRJ!U^KOE*oCI]K78?0>9:W3+LYIGVN%YRGCA.kGEQG;<:4:56[?/H]MKZB)]VCGM"gKAUC?<58612_;#DQAO^F-QZOKI&cOMYO380<2=>S7'@UECRJ!U^KOE*oCI]K74?0>9:W3+LYIGVN%YRGCA.kGEQG;0:4:56[?/H]MKZB)]VCGM"gKAUC?<186i2_;#DQAO^F-QZOKI&cOMYOPDNWW5<=R8&CTBBQK.T]JHD)nZLYNX1>1189V4*OXFFUO"XQFL@-jV@UB\5;5=45Z0.K\JJYC&\UB@L!fRDQFP949901^<"GPNN]G*PYNDH%b^H]JT=1=5<=R8&CTBBQK.T]JHD)nZLYNX1:1189V4*OXFFUO"XQFL@-jV@UB\5?5=45Z0.K\JJYC&\UB@L!fRDQFP909901^<"GPNN]G*PYNDH%b^H]JT=5=5d=R8&CTBBQK.T]JHD)n[]K_SIAZT0:8Q5)NWGETH#[PIMC,mQTNONOY=85Z0.K\PT6)OV^\W=S!U^VR53=R8&CTX\>!G^VT_46Z&\U_]<84U1-J[QW7&NU_[V?>]/W\PT713\:$ERZ^0/E\PR]6:T$^SY_>6:W3+LYSY9$LSYYT12_-QZRV9?1^<"GPTP2-CZRPS8>V"XQ[Q048Q5)NW][;"JQ[WZ36Y+SX\X;=7X> I^VR4+AX\^Q::P Z_US22>S7'@U_]= H_UUX52[)]V^Z=;5Z0.K\PT6)OV^\W<6R.T]WU40<]9%BSY_?.F]WS^7>U'_TX\?:;T2,MZRV8'MTXZU>]/W\PT713\:$ERZ^0/E\PR]58T$^SY_>6:W3+LYSY9$LSYYT20_-QZRV9?1^<"GPTP2-CZRPS;8V"XQ[Q048Q5)NW][;"JQ[WZ00Y+SX\X;=7X> I^VR4+AX\^Q98P Z_US22>S7'@U_]= H_UUX60[)]V^Z=;5Z0.K\PT6)OV^\W?8R.T]WU40<]9%BSY_?.F]WS^40U'_TX\?9;T2,MZRV8'MTXZU=8\,V[QW6>2_;#DQ[Q1,D[QQ\:0W%YRZ^149V4*OX\X:%KRZX[3_-QZRV9?1^<"GPTP2-CZRPS::V"XQ[Q048Q5)NW][;"JQ[WZ12Y+SX\X;=7X> I^VR4+AX\^Q8>P Z_US22>S7'@U_]= H_UUX76[)]V^Z=;5Z0.K\PT6)OV^\W>:R.T]WU40<]9%BSY_?.F]WS^52U'_TX\?9;T2,MZRV8'MTXZU<6\,V[QW6>2_;#DQ[Q1,D[QQ\;>W%YRZ^179V4*OX\X:%KRZX[2:^*PYSY8<0Y=!F_US3*BYS_R92Q#[PTP36?P6(AV^Z<#IPTVY0Y+SX\X;=7X> I^VR4+AX\^Q?<P Z_US22>S7'@U_]= H_UUX04[)]V^Z=;5Z0.K\PT6)OV^\W9<R.T]WU40<]9%BSY_?.F]WS^24U'_TX\?9;T2,MZRV8'MTXZU;4\,V[QW6>2_;#DQ[Q1,D[QQ\<<W%YRZ^179V4*OX\X:%KRZX[54^*PYSY8<0Y=!F_US3*BYS_R><Q#[PTP35?P6(AV^Z<#IPTVY7<X(RW][::6[?/H]WU5(@W]]P84S!U^VR50=R8&CTX\>!G^VT_1[)]V^Z=;5Z0.K\PT6)OV^\W8>R.T]WU40<]9%BSY_?.F]WS^36U'_TX\?9;T2,MZRV8'MTXZU:2\,V[QW6>2_;#DQ[Q1,D[QQ\=:W%YRZ^179V4*OX\X:%KRZX[46^*PYSY8<0Y=!F_US3*BYS_R?>Q#[PTP35?P6(AV^Z<#IPTVY62X(RW][::6[?/H]WU5(@W]]P9:S!U^VR53=R8&CTX\>!G^VT_0>Z&\U_]<84U1-J[QW7&NU_[V;6]/W\PT723\:$ERZ^0/E\PR]2U'_TX\?9;T2,MZRV8'MTXZU90\,V[QW6>2_;#DQ[Q1,D[QQ\>8W%YRZ^179V4*OX\X:%KRZX[70^*PYSY8<0Y=!F_US3*BYS_R<8Q#[PTP35?P6(AV^Z<#IPTVY50X(RW][::6[?/H]WU5(@W]]P:8S!U^VR53=R8&CTX\>!G^VT_30Z&\U_]<84U1-J[QW7&NU_[V88]/W\PT713\:$ERZ^0/E\PR]10T$^SY_>6:W3+LYSY9$LSYYT68_-QZRV9<1^<"GPTP2-CZRPS?W%YRZ^179V4*OX\X:%KRZX[62^*PYSY8<0Y=!F_US3*BYS_R=:Q#[PTP35?P6(AV^Z<#IPTVY46X(RW][::6[?/H]WU5(@W]]P;>S!U^VR53=R8&CTX\>!G^VT_22Z&\U_]<84U1-J[QW7&NU_[V9:]/W\PT713\:$ERZ^0/E\PR]0>T$^SY_>6:W3+LYSY9$LSYYT76_-QZRV9?1^<"GPTP2-CZRPS>2V"XQ[Q048Q5)NW][;"JQ[WZ5:Y+SX\X;>7X> I^VR4+AX\^Q<Q#[PTP35?P6(AV^Z<#IPTVY;4X(RW][::6[?/H]WU5(@W]]P4<S!U^VR53=R8&CTX\>!G^VT_=4Z&\U_]<84U1-J[QW7&NU_[V6<]/W\PT713\:$ERZ^0/E\PR]?<T$^SY_>5:W3+LYSY9$LSYYT8\,V[QW6=2_;#DQ[Q1,D[QQ\1T$^SY_j;T2,mQTNOVCE0=0i;T2,mQTNOVCE0<>1f:W3+lRUANUBB1?>>g9V4*oSZ@MTEC2>2?d8Q5)n\[CLSD@312<e?P6(a]XBKRGA<06=b>S7'`^YEJQFN=36:c=R8&c_^DIPIO>22;`<]9%bX_GH_HL?528a3\:$eY\FG^KM84>9n2_;#dZ]IF]JJ97>6l1^<"g[RHE\MK:66o1^<"g[RHE\MK:587l0Y=!fTSKD[LH;:84m7X> iUPJCZOI4;85j6[?/hVQMBYNF5882k5Z0.kWVLAXAG6983h4U1-jPWO@W@D7>80i;T2,mQTNOVCE0?81f:W3+lRUANUBB1<8>g9V4*oSZ@MTEC2=8?d8Q5)n\[CLSD@328<f?P6(a]XBKRGA<3<e?P6(a]XBKRGA<22=b>S7'`^YEJQFN=12:c=R8&c_^DIPIO>06;`<]9%bX_GH_HL?768a3\:$eY\FG^KM8629n2_;#dZ]IF]JJ9526o1^<"g[RHE\MK:4>7l0Y=!fTSKD[LH;;>4m7X> iUPJCZOI4:25j6[?/hVQMBYNF5922h5Z0.kWVLAXAG682k5Z0.kWVLAXAG6?<3h4U1-jPWO@W@D78<0i;T2,mQTNOVCE09<1f:W3+lRUANUBB1:<>g9V4*oSZ@MTEC2;4?d8Q5)n\[CLSD@344<e?P6(a]XBKRGA<54=b>S7'`^YEJQFN=64:c=R8&c_^DIPIO>7<;`<]9%bX_GH_HL?0<8b3\:$eY\FG^KM818a3\:$eY\FG^KM8069n2_;#dZ]IF]JJ9366o1^<"g[RHE\MK:2:7l0Y=!fTSKD[LH;=:4m7X> iUPJCZOI4<>5j6[?/hVQMBYNF5?>2k5Z0.kWVLAXAG6>:3h4U1-jPWO@W@D79:0i;T2,mQTNOVCE0861f:W3+lRUANUBB1;6>d9V4*oSZ@MTEC2:>g9V4*oSZ@MTEC290?d8Q5)n\[CLSD@360<e?P6(a]XBKRGA<70=b>S7'`^YEJQFN=40:c=R8&c_^DIPIO>50;`<]9%bX_GH_HL?208a3\:$eY\FG^KM8309n2_;#dZ]IF]JJ9006o1^<"g[RHE\MK:107l0Y=!fTSKD[LH;>04n7X> iUPJCZOI4?4m7X> iUPJCZOI4>:5j6[?/hVQMBYNF5=:2k5Z0.kWVLAXAG6<>3h4U1-jPWO@W@D7;>0i;T2,mQTNOVCE0::1f:W3+lRUANUBB19:>g9V4*oSZ@MTEC286?d8Q5)n\[CLSD@376<e?P6(a]XBKRGA<6:=b>S7'`^YEJQFN=5::`=R8&c_^DIPIO>4:c=R8&c_^DIPIO>;4;`<]9%bX_GH_HL?<48a3\:$eY\FG^KM8=49n2_;#dZ]IF]JJ9>46o1^<"g[RHE\MK:?<7o0Y=!fTSKD[LH;07o0Y=!fTSKD[LH;17i0Y^K]_WKPMGJB02_XIR\COB48QZKRPH<0YRCZXC48QZKRPJ<0YRCZXE48QZUUDH<0YR]]LC48QZUUDJ<0YR]]LE18RFE>3_CN[RZVPDa8SDTIAGMTCCBV6:UFE969>2]NM1?16:UFE94902]NM1=50?48S@G;;7<0[HL30?48S@D;97<0[HL32?:8S@D;;3:5:6YJB=1=<>QBJ^O7<364WD@TA97902]NNZK32?:8S@DPM59546YJBVG?0;><_LH\I1;18:UFFRC;>7k0[HLXE=594;><_LH\I191b:UQMQCXN@XXXn5XRHVF[HICMVKh7Z\FTD]NKACXJm1\^DZJ_VKGPMYFl2]YEYKPWHFWLZD33Q:R<95W0X36?]6^99?0T=W>159[4\433Q:R?95W0X67?]6^==1S<T8;;Y2Z31=_8P2?7U>V90f8\LJNFQ'SHO.?.0"PPPD'8';+M^MFI49[KWE^>2RXXAGM7:ZPPZAIL>1S_YQYCB`8\ZEHZLUBBKA9;Yfa[Lba3QncS]|fmWgqwlii991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc=4Xrv05>eoayyhc}kPimc\r4Y7;Vk',Ugcioz#GJTB(Noeio{os"25+4602ixSjoad^qqhZp1W{zfS~k{_03;?fuXohdoS~|c_w4\vukX{l~T><64cr]dekbX{{fTz;Q}pl]paqY49?1hRinne]pviYq>VygenkP1058gvY`ignTbPv7]phlebW8::;6m|_fcm`ZuudV|=S~bfcd]2541<kzUlmcjPssn\r3Ytd`inS<<>6:ap[bgilVyy`Rx9_rnjg`Y59?1hRinne]pviYq>VygenkP3048gvY`ignTbPv7]phlebW=;=7n}Pg`lg[vtkW<Tagle^722>etWnkehR}}l^t5[vjnklU==;5ls^ebjaYtzeU}:R}cibg\340<kzUlmcjPssn\r3Ytd`inS5?9;bq\cdhcWzxgS{8Psmk`aZ?c3nkehRmnrs{?4;c<ohdoSno}rx>24;b<ohdoSno}rx>2:a=`ignTol|}y=0=`>affmUhm|v<2<g?bgilVij~w34?f8cdhcWjky~t2:>e9dekbXkhxyu181d:ebjaYdi{xr0:0k;fcm`Zefz{s743j4g`lg[fguzp62255hltg\w`r>3nf~iR}jt0;8cisbWzo>45hltg\w`r4;2cgm?=4imc/gmow{je{iRgca^t2[55Xi%DDBH"AOOG25=c<aek'oegsbmsaZokiV|:S==Pa-y`[}ehWecxx0M`mqmmakrXFhgn1dbn;Ownf`tXGoU_~dihes]Skwrt581FmuQ\epwfjfcXDl|n`~3>;Tqf[WVJ{4~yyh5Jn``oaZRuanmn~RAztqww[Uiu|4lj`~k4S`osh`YHf4Xbd`h;RcnticXLh~jSIkti?2472<Mgki`hQ\tnpbc`YV}hfbjdmnthmm9qtrm2NjxlQ\alg\EvYSz`mli3{rtg8@drfWYeyxRYfduj>4>Ruanmn~R^`ru]TmaroW87396Cntbj\Qkos{V;6=6M`uovfvZQnl}bT=0?4M`v`lZR~xlU:1oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX94lj`~k4Tskdc`tXXfxSZgkti]19==Ji}icSX`ftr]194=Dg|diQXievk[7;Cazki`hj4M`v`lZR~xlU91oo|ib9F|fjrllUM~bcPD`vb[VrhzhmnS?3iamqf?QtnonoyS]a}t^Uj`qnX;420Alzlh^WmmquX;4;0Ob{atdp\Slbs`V96Hd}nbmgg?HgskaU_u}kP3<`bwle<MqigyikPFsmn[AgsiVYcohe^1>bdjtm2^yejijr^RlvqYPam~cS937;LcwgmYRf`~xS93>;BmvjqcuW^coxeQ;=Ekpegjbl2GjxnfPTxrf[1;eizch7Hvlltff[CtheVNjxlQ\tnpbc`Y35okgh5[rhedawYWg{~T[dj{h^7><>Kf|jbTYcg{s^7>5>Eh}g~n~RYfduj\18Bn{hhgii5Bauak[QwmV?6nl}fc:G{giscmVLyc`QKauc\WqiuinoT90hnlrg8Pwo`olxT\b|{_VkgpmY1511Fmymg_TljpvY1581Hcx`{es]TmaroW?7Oe~omldf8Idrd`V^r|hQ9=ccpmf=Bpjf~hhQIrno\@drfWZ~d~lij_7?eeiub3]xbkjk}_QmqpZQnl}bT;064M`v`lZSia}yT;0?4Cnwmp`tX_`ndR92Dhqbficc3DkoeQ[yqg\38df{`i0Iumcueg\BwijWMkmR]{oscdaZ1:nhfxi6Z}ifefvZVhz}U\eizg_9?;?HgskaU^bdz|_9?2?Firf}oySZgkti];9Aotikfnh6Cntbj\P|vbW17im~gl;Dz`hpbbWOxdaRJnt`]PpjtfolU31kocsd9Wvla`m{U[czPWhfwlZ?:02GjxnfPUokwwZ?:92Idyczjr^Uj`qnX14Nbllcee9NeqeoW]s{iR72b`qjg>CkeoiRH}ol]GeqgX[}eymjkP9<dbhvc<\{clkh|PPnpw[Roc|aU:<064M`v`lZSia}yT==3>;BmvjqcuW^coxeQ>0<Fjwddkmm1Fmymg_U{saZ775kkxen5Jxbnv``YAzfgTHlzn_RvlvdabW8:6jlb|e:VqmbabzVZd~yQXievk[47:02GjxnfPUokwwZ76581Hcx`{es]TmaroW8;6Hd}nbmgg?HgskaU_u}kP10?aevod3Lrh`xjj_GpliZBf|hUXxb|ngd]258`fdzo0Xghgdp\TjtsW^coxeQ>2<:8Idrd`V_eey}P13?2?Firf}oySZgkti]268Bn{hhgii5Bauak[QwmV;91oo|ib9F|fjrllUM~bcPD`vb[VrhzhmnS<<2f`npa>Ruanmn~R^`ru]TmaroW89646Cntbj\Qkos{V;81<5LotlwawYPam~cS<=2Dhqbficc3DkoeQ[yqg\56;eizch7Hvlltff[CtheVNjxlQ\tnpbc`Y6;4lj`~k4Tskdc`tXXfxSZgkti]208><Eh~hdR[aiuq\51;63Je~byk}_VkgpmY6<4Nbllcee9NeqeoW]s{iR?;=ccpmf=Bpjf~hhQIrno\@drfWZ~d~lij_06>bdjtm2^yejijr^RlvqYPam~cS<;28:ObpfnX]gcR?:=09@kphsm{U\eizg_07>@lufjeoo7@o{ci]W}ucX9<7im~gl;Dz`hpbbWOxdaRJnt`]PpjtfolU:90hnlrg8Pwo`olxT\b|{_VkgpmY6>420Alzlh^WmmquX9?7:7Naznugq[Roc|aU::0Jfs``oaa=Ji}icSYwe^359ggtaj1Ntnbzdd]EvjkXLh~jS^z`r`ef[40:nhfxi!mPxegumfcaidcgu0xfrug{2)eXkfxnSywe<0/gZkaoVco1<"l_lcikwYqm{ybcc3>1-a\ilhhzV|n~~g`n<0/gZdraenT~hxfshmm95*dWjeyiRcnjnp\r`t:9%iTob|j_lkmkwYqm{79 nQlosg\ilhhzVkg|eoPvdp>=2*dW{kfSywe<3/gZuud8<Txt~j=3.`[pubW`d}Snbd=1.`[pubW{zf1<"l_tqf[qtnoVe~x0>#c^wpaZgskViggd`20-a\qvcXlh~j1="l_tqf[qtno97: nQzsd]wvla659&hSx}j_upjc7;7$jU~hQ{rhe095*dW|ynSy|fg5?3(fYr{lU~di:=1.`[pubW}xbk;3?,b]vw`Ysz`m<1="l_tqf[qtno17; nQzsd]wvla>59&hSx}j_upjc46:8%iTy~kPtskd54;7$jU~hQ{rhe2686+kVxiRz}if3095*dW|ynSy|fg06>4)eX}zoTxgh14?3(fYr{lU~dikauc394*dW|ynSy|fgecwe4;7$jU~hQ{rhegeqg559&hSx}j_upjcagsi:7; nQzsd]wvlaci}k?1="l_tqf[qtnomkm83?,b]vw`Ysz`momyo9=1.`[pubW}xbkio{a6?3(fYr{lU~dikauc;95*dW|ynSy|fgecwe<;7$jU~hQ{rhegeqg684:'oR{|e^vqmbbf|h;:1="l_tqf[qtnomkm<<20-a\qvcX|{clhlzn12?3(fYr{lU~dikauc2086+kVxiRz}iffbpd7259&hSio{a^uj`qn:9%iThlzn_egspm;68;>'oR{|e^ebt86+kV~bah}{alr\p|vb59&hSygbervbiuYpam~c1><#c^vji`usidzThh~{h<726)eX}zoTya}afg\upgk58&hSy}jq^vzt`;7$jUey`Q{sds\gkr:8%iTx~k~_blw5Zqnl}b6=!mPtrgr[fhs8V}bhyf21-a\jpkX|zozS~zntdq>5)eX}zoTxnQbcov>4)eX|jUfoczPwhfwl87+kVosxRmnp^pbp`Yjgmo6<!mPeyv\gdvXx`dTabjj=1.`[ksjWlrSno_qkmw8>+kVosxRmnp^wpaZtbo4;'oR`zm^obpfnX}gc0?#c^vqmb6X`nd06:,b]wvla6W~coxe3>,b]wvla5W~coxe3>,b]wvla4W~coxe3>,b]wvla3W~coxe3>,b]wvla2W~coxe3>,b]wvla1W~coxe3>,b]wvla0W~coxe3>,b]wvla?W~coxe3>,b]wvla>W~coxe3>,b]wvla68V}bhyf21-a\pwo`98U|eizg=0.`[qtno88T{dj{h<3/gZruan;8Szgkti?2(fYsz`m:8Ryfduj>5)eX|{cl=8Qxievk94*dWd:Tx}gk=1.`[h7X|yco1<"l_l0\puoc5;&hS`=Ptqkg96*dWd>Tx}gk=5.`[h3X|yco18"l_l4\puoc5?&hS`9Ptqkg92*dWd2Tx}gk=9.`[h?X|yco14"l_l33[qvnl4;; nQb10]wtlb:98&hS`?=_urj`875$jUf=>Q{phf>56*dWd;?Sy~fd<37(fYj9<U|dj214.`[h6X|pzn1<"l_l3\p|vb59&hS`<Ptxrf95*dWd9Txt~j=1.`[h2X|pzn1="l_l7\p|vb59&hS`8Ptxrf95*dWd=Txt~j=1.`[h>X|pzn1="l_l;\p|vb59&hS`??_u{sa86+kVg:=Rzvpd?3(fYj9;Uu}k20-a\i45X|pzn1="l_l37[qwm4:'oRc>5^vzt`;7$jU~hQbcov394*dW|ynS`mat0?3(fYr{lUfocz==1.`[pubWdiex>3?,b]vw`Yjkg~?1="l_tqf[hei|<7; nQzsd]ngkr159&hSx}j_lamp2;7$jU~hQbcov;95*dW|ynS`mat8?3(fYr{lUfocz>0<2/gZstmVghby?>=1.`[pubWdiex<<20-a\qvcXejd=>3?,b]vw`Yjkg~:80>#c^wpaZkdf};>1="l_lamp5Ypam~c1<"l_lamp4Ypam~c1<"l_lamp7Ypam~c1<"l_lamp6Ypam~c1<"l_lamp1Ypam~c1<"l_lamp0Ypam~c1<"l_lamp3Ypam~c1<"l_lamp2Ypam~c1<"l_lamp=Ypam~c1<"l_lamp<Ypam~c1<"l_lamp46X`nd0?#c^o`jq76W~coxe3>,b]ngkr6:V}bhyf21-a\ifhs9:U|eizg=0.`[hei|8>T{dj{h<3/gZkdf};>Szgkti?2(xe<djfTbPq=2=g>jddVyy`R31?a8hfjX{{fT}1<1b:ov|fXdf6;2o5buyaz[ii;97h0axvly^nl878e3dsotQco=1=f>krpjsT`b2;>b9nq}e~Wzog0=0l;lw{g|Ytme6:2n5buyaz[vck4;4h7`{wcx]pai:4611eknlzimf:?vtkWx6:<364ssn\u97902yy`R32?:8wwjXy59546}}l^s?0;><{{fT}1;18:qqhZw;>720bPq=5=<>uudV{74364ssn\u9?9uIJ{>47i;AB{fd3=N3>1=v]k5;`;1?50<3;8>5k67;173=0|fk286<5ab9691>"e080i;o5rS`g9f=3=;>>1=><7e859711>;2Y8;54mb583>4550l3<6>:8999Pe`<ej=0;6<==8d;4>620i91onl;50;395~Uc=3h397=84;306=c>?39?;584vU1a2?6=93;19=7tSe79f=3=;>>1=><7e859711?>2.i984<789Uf=4=:r84>4>;t1;0?6<u-92?7=7;c`b1?6=?h08484;41yKf1g<,=9:6oo:;[;4>7}4m38o6p*m818a<3=#i<0im;5+d58ae2=n<;n1<7*<94876f=i;0>1<65f43`94?"41<0?>n5a38695>=n<;k1<7*<94876f=i;0>1>65f43;94?"41<0?>n5a38697>=n<;21<7*<94876f=i;0>1865f43494?"41<0?>n5a38691>=n<;?1<7*<94876f=i;0>1:65f43694?"41<0?>n5a38693>=n<;91<7*<94876f=i;0>1465f43094?"41<0?>n5a3869=>=n<;;1<7*<94876f=i;0>1m65f43294?"41<0?>n5a3869f>=n<8l1<7*<94876f=i;0>1o65f40g94?"41<0?>n5a3869`>=n<8n1<7*<94876f=i;0>1i65f40`94?"41<0?>n5a3869b>=n<8k1<7*<94876f=i;0>1==54i53:>5<#;0?18?m4n2;7>47<3`>:47>5$2;6>14d3g9287?=;:k752<72-9297:=c:l0=1<6;21b8<850;&0=0<3:j1e?4:51598m172290/?4;543a8j6?328?07d:>4;29 6?22=8h7c=64;35?>o39:0;6)=65;61g>h41=0:;65f40094?"41<0?>n5a38695==<a=;;6=4+387907e<f:3?6<74;h63b?6=,:3>69<l;o1:0?7f32c?<h4?:%1:1?25k2d8594>b:9j05b=83.8584;2b9m7<2=9j10e9>l:18'7<3=<;i0b>7;:0f8?l27j3:1(>7::50`?k5><3;n76g;0`83>!5>=3>9o6`<9582b>=n<931<7*<94876f=i;0>1>=54i52;>5<#;0?18?m4n2;7>77<3`>;;7>5$2;6>14d3g9287<=;:k740<72-9297:=c:l0=1<5;21b8=:50;&0=0<3:j1e?4:52598m164290/?4;543a8j6?32;?07d:?2;29 6?22=8h7c=64;05?>o3880;6)=65;61g>h41=09;65f41294?"41<0?>n5a38696==<a:lm6=4+387907e<f:3?6?74;h1ea?6=,:3>69<l;o1:0?4f32c8ji4?:%1:1?25k2d8594=b:9j7ce=83.8584;2b9m7<2=:j10e>hn:18'7<3=<;i0b>7;:3f8?l5a13:1(>7::50`?k5><38n76g<f983>!5>=3>9o6`<9581b>=n;o=1<7*<94876f=i;0>1?=54i2d5>5<#;0?18?m4n2;7>67<3`9m97>5$2;6>14d3g9287==;:k0b1<72-9297:=c:l0=1<4;21b?k=50;&0=0<3:j1e?4:53598m6`5290/?4;543a8j6?32:?07d=i1;29 6?22=8h7c=64;15?>o4mo0;6)=65;61g>h41=08;65f3dg94?"41<0?>n5a38697==<a:oo6=4+387907e<f:3?6>74;h1fg?6=,:3>69<l;o1:0?5f32c8io4?:%1:1?25k2d8594<b:9j7`g=83.8584;2b9m7<2=;j10e>k6:18'7<3=<;i0b>7;:2f8?l5b03:1(>7::50`?k5><39n76g<e683>!5>=3>9o6`<9580b>=n;l<1<7*<94876f=i;0>18=54i2g7>5<#;0?18?m4n2;7>17<3`9n?7>5$2;6>14d3g9287:=;:k0a7<72-9297:=c:l0=1<3;21b?h?50;&0=0<3:j1e?4:54598m6c7290/?4;543a8j6?32=?07d=kf;29 6?22=8h7c=64;65?>o4ll0;6)=65;61g>h41=0?;65f3ef94?"41<0?>n5a38690==<a:nh6=4+387907e<f:3?6974;h1gf?6=,:3>69<l;o1:0?2f32c?>k4?:%1:1?25k2d8594;b:9j07c=83.8584;2b9m7<2=<j10e9<8:18'7<3=<;i0b>7;:5f8?l26k3:1(>7::50`?k5><3>n76g;1083>!5>=3>9o6`<9587b>=n<9<1<7*<94876f=i;0>19=54i2da>5<#;0?18?m4n2;7>07<3`9m<7>5$2;6>14d3g9287;=;:k0a0<72-9297:=c:l0=1<2;21b?io50;&0=0<3:j1e?4:55598/fe=83.8584lb:l0=1<732!hm7>5$2;6>fd<f:3?6<54+b;94?"41<0hn6`<9581?>-d03:1(>7::b`8j6?32:10'n950;&0=0<dj2d8594;;:)`2?6=,:3>6nl4n2;7>0=<#j>1<7*<948`f>h41=0=76%l3;29 6?22jh0b>7;:698/f4=83.8584lb:l0=1<?32!h=7>5$2;6>fd<f:3?6454+b294?"41<0hn6`<958b?>-en3:1(>7::b`8j6?32k10'ok50;&0=0<dj2d8594l;:)a`?6=,:3>6nl4n2;7>a=<#ki1<7*<948`f>h41=0n76%mb;29 6?22jh0b>7;:g98/g?=83.8584lb:l0=1<6821 n54?:%1:1?ee3g9287?>;:)a3?6=,:3>6nl4n2;7>44<3"h=6=4+3879gg=i;0>1=>54+c794?"41<0hn6`<95820>=,j=0;6)=65;aa?k5><3;>76%m3;29 6?22jh0b>7;:048?.d5290/?4;5cc9m7<2=9>10'o?50;&0=0<dj2d8594>8:9(f5<72-9297mm;o1:0?7>32!o?7>5$2;6>fd<f:3?6<o4;*f1>5<#;0?1oo5a38695g=<#m;1<7*<948`f>h41=0:o65$d183>!5>=3ii7c=64;3g?>-dn3:1(>7::b`8j6?328o07&mj:18'7<3=kk1e?4:51g98/f3=83.8584lb:l0=1<5921 nl4?:%1:1?ee3g9287<=;:)bb?6=,:3>6nl4n2;7>75<3`k<6=44+bf94?"41<0hn6`<95814>=ej>l1<7?50;2x 1562k??7El8d:Ja0d=h;081<75rbc5f>5<6290;w):<1;0`3>Ne?m1Cn9o4o0g6>5<<uk2m;7>59;294~"3;808n45Gb6f8Lg2f3-8n<7<4i5294?=n<80;66g;2;29?l242900el:50;9je2<722co:7>5;n1:3?6=3f9247>5;|`;bf<7200;6=u+42397g?<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg32900el950;9j`3<722e85:4?::m0==<722wi4k;50;094?6|,=9:6>9n;I`4`>Ne<h1/>h>5119j6fg=831d?4?50;9~f3?d290?6=4?{%605?50k2Bi;i5Gb5c8 7c720k0e?mn:188m7ee2900e?ml:188k6?62900qo6id;290?6=8r.??<4>d89Kf2b<@k>j7)<j0;38m<>=831bh;4?::k0=d<722e85:4?::a<c>=83>1<7>t$512>4b>3Ah<h6Fm4`9'6`6=92c247>5;hf5>5<<a:3j6=44o2;4>5<<uk2mm7>54;294~"3;80:h45Gb6f8Lg2f3-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66sm8gd94?2=83:p(9=>:0f:?Md0l2Bi8l5+2d295>o>03:17dj9:188m6?f2900c>78:188yg>a>3:187>50z&774<6l01Cn:j4Hc6b?!4b83;0e4650;9j`3<722c85l4?::m0=2<722wim:=50;794?6|,=9:6<j7;I`4`>Ne<h1/>h>5119j==<722cj87>5;hf5>5<<a:3=6=44o2;4>5<<uk2m87>54;294~"3;80:h45Gb6f8Lg2f3-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66smag094?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdfn80;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qooi0;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fdca290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wimhk50;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`baf<72=0;6=u+42395a1<@k=o7El;a:&1a5<682c247>5;hf5>5<<a:3=6=44o2;4>5<<ukknn7>54;294~"3;80:h:5Gb6f8Lg2f3-8n<7??;h;;>5<<am<1<75f38494?=h;0=1<75rb`gb>5<3290;w):<1;3g3>Ne?m1Cn9o4$3g3>46<a021<75fd783>>o41?0;66a<9683>>{eil31<7:50;2x 15628n<7El8d:Ja0d=#:l:1==5f9983>>oc>3:17d=66;29?j5>?3:17plne983>1<729q/8>?51e58Lg1c3Ah?m6*=e1824>o>03:17dj9:188m6?12900c>78:188yggb?3:187>50z&774<6l>1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?4850;9l7<1=831vnlk9:187>5<7s->8=7?k7:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0=3<722e85:4?::ae`3=83>1<7>t$512>4b03Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`92:7>5;n1:3?6=3thji94?:583>5}#<:;1=i94Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2;5>5<<g:3<6=44}ccf7?6=<3:1<v*;3082`2=Oj>n0Do:n;%0f4?773`336=44ie494?=n;0<1<75`38594?=zjho:6=4;:183!2493;o;6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<9783>>i41>0;66smad294?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdflo0;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qooke;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fdbc290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wimim50;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`b`g<72=0;6=u+42395a1<@k=o7El;a:&1a5<682c247>5;hf5>5<<a:3=6=44o2;4>5<<ukkom7>54;294~"3;80:h:5Gb6f8Lg2f3-8n<7??;h;;>5<<am<1<75f38494?=h;0=1<75rb`f:>5<3290;w):<1;3g3>Ne?m1Cn9o4$3g3>46<a021<75fd783>>o41?0;66a<9683>>{eim21<7:50;2x 15628n<7El8d:Ja0d=#:l:1==5f9983>>oc>3:17d=66;29?j5>?3:17plnd783>1<729q/8>?51e58Lg1c3Ah?m6*=e1824>o>03:17dj9:188m6?12900c>78:188yggc=3:187>50z&774<6l>1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?4850;9l7<1=831vnlj;:187>5<7s->8=7?k7:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0=3<722e85:4?::aea5=83>1<7>t$512>4b03Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`92:7>5;n1:3?6=3thjh?4?:583>5}#<:;1=i94Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2;5>5<<g:3<6=44}ccg5?6=<3:1<v*;3082`2=Oj>n0Do:n;%0f4?773`336=44ie494?=n;0<1<75`38594?=zjhn;6=4;:183!2493;o;6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<9783>>i41>0;66smabd94?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdfkl0;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qoold;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fdee290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wimno50;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`bg<<72=0;6=u+42395a1<@k=o7El;a:&1a5<682c247>5;hf5>5<<a:3=6=44o2;4>5<<ukkh47>54;294~"3;80:h:5Gb6f8Lg2f3-8n<7??;h;;>5<<am<1<75f38494?=h;0=1<75rb`a4>5<3290;w):<1;3g3>Ne?m1Cn9o4$3g3>46<a021<75fd783>>o41?0;66a<9683>>{eij<1<7:50;2x 15628n<7El8d:Ja0d=#:l:1==5f9983>>oc>3:17d=66;29?j5>?3:17plnc483>1<729q/8>?51e58Lg1c3Ah?m6*=e1824>o>03:17dj9:188m6?12900c>78:188yggd<3:187>50z&774<6l>1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?4850;9l7<1=831vnlm<:187>5<7s->8=7?k7:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0=3<722e85:4?::aef4=83>1<7>t$512>4b03Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`92:7>5;n1:3?6=3thjo=4?:583>5}#<:;1=i94Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2;5>5<<g:3<6=44}ccab?6=<3:1<v*;3082`2=Oj>n0Do:n;%0f4?773`336=44ie494?=n;0<1<75`38594?=zjhhn6=4;:183!2493;o;6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<9783>>i41>0;66smacf94?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdfjj0;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qoomb;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fddf290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wimo750;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`bf=<72=0;6=u+42395a1<@k=o7El;a:&1a5<682c247>5;hf5>5<<a:3=6=44o2;4>5<<ukki;7>54;294~"3;80:h:5Gb6f8Lg2f3-8n<7??;h;;>5<<am<1<75f38494?=h;0=1<75rb``6>5<3290;w):<1;3g3>Ne?m1Cn9o4$3g3>46<a021<75fd783>>o41?0;66a<9683>>{eik>1<7:50;2x 15628n<7El8d:Ja0d=#:l:1==5f9983>>oc>3:17d=66;29?j5>?3:17plnb283>1<729q/8>?51e58Lg1c3Ah?m6*=e1824>o>03:17dj9:188m6?12900c>78:188ygge:3:187>50z&774<6l>1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?4850;9l7<1=831vnll>:187>5<7s->8=7?k7:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0=3<722e85:4?::aeg6=83>1<7>t$512>4b03Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`92:7>5;n1:3?6=3thjmk4?:583>5}#<:;1=i94Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2;5>5<<g:3<6=44}ccba?6=<3:1<v*;3082`2=Oj>n0Do:n;%0f4?773`336=44ie494?=n;0<1<75`38594?=zjhko6=4;:183!2493;o;6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<9783>>i41>0;66sma`a94?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdfih0;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qoon9;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fdg?290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wiml950;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`be3<72=0;6=u+42395a1<@k=o7El;a:&1a5<682c247>5;hf5>5<<a:3=6=44o2;4>5<<ukkj97>54;294~"3;80:h:5Gb6f8Lg2f3-8n<7??;h;;>5<<am<1<75f38494?=h;0=1<75rb`c7>5<3290;w):<1;3g3>Ne?m1Cn9o4$3g3>46<a021<75fd783>>o41?0;66a<9683>>{eih91<7:50;2x 15628n<7El8d:Ja0d=#:l:1==5f9983>>oc>3:17d=66;29?j5>?3:17plna383>1<729q/8>?51e58Lg1c3Ah?m6*=e1824>o>03:17dj9:188m6?12900c>78:188yggf93:187>50z&774<6l>1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?4850;9l7<1=831vnlh;:187>5<7s->8=7?k7:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0=3<722e85:4?::aec5=83>1<7>t$512>4b03Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`92:7>5;n1:3?6=3thjii4?:583>5}#<:;1=i94Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2;5>5<<g:3<6=44}ccf6?6=<3:1<v*;3082`2=Oj>n0Do:n;%0f4?773`336=44ie494?=n;0<1<75`38594?=zjhn<6=4;:183!2493;o;6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<9783>>i41>0;66smaba94?2=83:p(9=>:0f4?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5>>3:17b=67;29?xdfk80;694?:1y'067=9m=0Do9k;I`7e>"5m90:<6g68;29?lb12900e>79:188k6?02900qoom6;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~fdge290?6=4?{%605?7c?2Bi;i5Gb5c8 7c728:0e4650;9j`3<722c85;4?::m0=2<722wiml>50;694?6|,=9:6<j8;I`4`>Ne<h1/>h>5119j==<722co:7>5;h1:2?6=3f92;7>5;|`7`3<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9j;:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3l;0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5f3>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?oh4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1ef290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;c983>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=i=6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`7g1<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9m=:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3k90;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5`f>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?nn4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1df290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;b983>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=h?6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`7f7<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9l?:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3il0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5c`>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?ml4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1g?290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;a783>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=k?6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`7e7<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn97j:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd31j0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5;b>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?554?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1?1290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;9583>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=396=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`7=5<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn96j:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd30j0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5:;>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?4;4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1>3290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;8383>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=2;6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`73`<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn99l:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3?h0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb55;>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?;;4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f115290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;7183>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=<n6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`72f<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn98n:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3>10;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb545>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?:94?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f105290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;6183>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=?h6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`71d<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9;7:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3=?0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb577>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?9?4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f137290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;4d83>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=>h6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`70d<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9:9:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3<=0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb561>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?8=4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f15b290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;3b83>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=9j6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`77=<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn9=9:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3;=0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb5fb>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th?h54?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1ed290<6=4?{%605?5e?2Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni>0;66gk6;29?j5>?3:17pl;b783>2<729q/8>?53c58Lg1c3Ah?m6*=e181?l272900e9?50;9j07<722c??7>5;hc4>5<<am<1<75`38594?=zj=k;6=48:183!24939i;6Fm7e9Kf1g<,;o;6?5f4183>>o393:17d:=:188m15=831bm:4?::kg2?6=3f92;7>5;|`7<d<72>0;6=u+42397g1<@k=o7El;a:&1a5<53`>;6=44i5394?=n<;0;66g;3;29?lg02900ei850;9l7<1=831vn99;:184>5<7s->8=7=m7:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa683>>oc>3:17b=67;29?xd3=l0;6:4?:1y'067=;k=0Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k<6=44ie494?=h;0=1<75rb56;>5<0290;w):<1;1a3>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je2<722co:7>5;n1:3?6=3th???4?:683>5}#<:;1?o94Hc5g?Md3i2.9i=4=;h63>5<<a=;1<75f4383>>o3;3:17do8:188ma0=831d?4950;9~f1b029086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`7`0<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb5f0>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;d083>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9mi:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?oo4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=i26=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3k>0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f1e229086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`7g6<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb5a2>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;bg83>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9lk:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?no4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=h26=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3j<0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f1d429086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`7f4<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb5ce>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;ae83>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9om:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?m44?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=k<6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3i<0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f1g429086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`7=c<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb5;g>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;9c83>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn976:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?5:4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=3>6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd31:0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f1?629086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`7<c<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb5:g>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;8883>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn968:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?484?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=286=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3080;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f11a29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`73a<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb55a>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;7883>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn998:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?;>4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj==:6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3>o0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f10c29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`72g<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb54:>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;6683>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn98::180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?:>4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=<:6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3=m0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f13e29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`71<<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb574>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;5483>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9;<:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?9<4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=>m6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3<m0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f12e29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`702<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb566>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;4283>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9:>:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th??k4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=9o6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3;k0;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f15>29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`772<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb516>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;dc83>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9j6:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th?oi4?:283>5}#<:;1=i<4Hc5g?Md3i2.9i=4>;h;;>5<<am<1<75`38594?=zj=h<6=4<:183!2493;o>6Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17b=67;29?xd3i80;6>4?:1y'067=9m80Do9k;I`7e>"5m90:7d77:188ma0=831d?4950;9~f1>e29086=4?{%605?7c:2Bi;i5Gb5c8 7c7281b554?::kg2?6=3f92;7>5;|`730<72:0;6=u+42395a4<@k=o7El;a:&1a5<63`336=44ie494?=h;0=1<75rb57e>5<4290;w):<1;3g6>Ne?m1Cn9o4$3g3>4=n110;66gk6;29?j5>?3:17pl;4883>6<729q/8>?51e08Lg1c3Ah?m6*=e182?l??2900ei850;9l7<1=831vn9=<:180>5<7s->8=7?k2:Ja3a=Oj=k0(?k?:09j==<722co:7>5;n1:3?6=3th2;?4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0=o6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>010;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<?4290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:=`<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8c:>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl6b583>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4li:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2o84?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0i=6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>?:0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<13290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:30<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb855>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl67683>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn497:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2;44?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0=j6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>?k0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<1d290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:3`<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb85e>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl68183>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn46>:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th24?4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0286=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>0=0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<>2290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:<3<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8:4>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl68883>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn46n:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th24o4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj02h6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>0m0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<>b290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:<c<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8;3>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl69083>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn47=:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2594?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj03>6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>1?0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<?0290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:==<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8;:>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl69`83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn47m:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th25n4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj03o6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>1o0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<g7290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:e4<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8c1>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl6a283>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4o;:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2m84?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0k=6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>i>0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<g?290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:ed<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8ca>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl6ab83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4ok:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2mh4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0km6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>j90;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<d6290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:f7<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8`0>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl6b483>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4l9:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2n:4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0h36=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>j00;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<df290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:fg<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb8``>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl6be83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4lj:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2o=4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0i:6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>k;0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<e4290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:g1<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb83g>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl62983>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4=<:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2?h4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0>26=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>==0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<3a290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:2d<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb853>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl67083>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4?j:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2=k4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj08;6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>:80;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<45290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:66<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb807>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl62483>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4<9:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2>:4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0826=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>:h0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<4e290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:6f<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb80g>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl62d83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4<i:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2?=4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj09:6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>;;0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<53290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:70<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb815>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl63683>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4=7:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2?44?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj09j6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>;k0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<5d290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:7a<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb81e>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl64183>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4:>:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th28?4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0>86=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd><=0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<22290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:03<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb864>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl64983>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4:n:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th28o4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0>h6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd><m0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<2b290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:0c<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb873>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl65083>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4;=:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th29>4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0?>6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>=?0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<30290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:1=<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb87:>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl65`83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn4;m:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th29n4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0?o6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>=l0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<07290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:24<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb841>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl66283>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn48;:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2:84?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0<=6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>>>0;684?:1y'067=9m20Do9k;I`7e>"5m90:<6g68;29?lg32900ei850;9j7<0=831d?4950;9~f<0?290>6=4?{%605?7c02Bi;i5Gb5c8 7c728:0e4650;9je1<722co:7>5;h1:2?6=3f92;7>5;|`:2<<72<0;6=u+42395a><@k=o7El;a:&1a5<682c247>5;hc7>5<<am<1<75f38494?=h;0=1<75rb84a>5<2290;w):<1;3g<>Ne?m1Cn9o4$3g3>46<a021<75fa583>>oc>3:17d=66;29?j5>?3:17pl66b83>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn48k:186>5<7s->8=7?k8:Ja3a=Oj=k0(?k?:028m<>=831bm94?::kg2?6=3`92:7>5;n1:3?6=3th2:h4?:483>5}#<:;1=i64Hc5g?Md3i2.9i=4>0:k:<?6=3`k?6=44ie494?=n;0<1<75`38594?=zj0<m6=4::183!2493;o46Fm7e9Kf1g<,;o;6<>4i8:94?=ni=0;66gk6;29?l5>>3:17b=67;29?xd>k>0;6h=5c;d;Md3i2.??<4m869Y=2<6s;:1q)l;b;604>o5>m0;6)=65;05g>h41=0;76g=6c83>!5>=38=o6`<9582?>o5>h0;6)=65;05g>h41=0976g=6883>!5>=38=o6`<9580?>o5>10;6)=65;05g>h41=0?76g=6683>!5>=38=o6`<9586?>o5>?0;6)=65;05g>h41=0=76g=6483>!5>=38=o6`<9584?>o5>=0;6)=65;05g>h41=0376g=6283>!5>=38=o6`<958:?>o5>80;6)=65;05g>h41=0j76g=6183>!5>=38=o6`<958a?>o5=o0;6)=65;05g>h41=0h76g=5d83>!5>=38=o6`<958g?>o5=m0;6)=65;05g>h41=0n76g=5b83>!5>=38=o6`<958e?>o5=k0;6)=65;05g>h41=0:<65f24c94?"41<09:n5a386954=<a;?26=4+387963e<f:3?6<<4;h06<?6=,:3>6?8l;o1:0?7432c9984?:%1:1?41k2d8594>4:9j602=83.8584=6b9m7<2=9<10e?;<:18'7<3=:?i0b>7;:048?l42:3:1(>7::34`?k5><3;<76g=5083>!5>=38=o6`<9582<>=n:<:1<7*<94812f=i;0>1=454i36e>5<#;0?1>;m4n2;7>4g<3`8?i7>5$2;6>70d3g9287?m;:k10a<72-9297<9c:l0=1<6k21b>9m50;&0=0<5>j1e?4:51e98m72f290/?4;527a8j6?328o07d<;9;29 6?22;<h7c=64;3e?>o5<10;6)=65;05g>h41=09<65f25594?"41<09:n5a386964=<a;>=6=4+387963e<f:3?6?<4;h071?6=,:3>6?8l;o1:0?4432c9894?:%1:1?41k2d8594=4:9j615=83.8584=6b9m7<2=:<10e?:=:18'7<3=:?i0b>7;:348?l4393:1(>7::34`?k5><38<76g=3g83>!5>=38=o6`<9581<>=n::o1<7*<94812f=i;0>1>454i31g>5<#;0?1>;m4n2;7>7g<3`88o7>5$2;6>70d3g9287<m;:k17g<72-9297<9c:l0=1<5k21b>>o50;&0=0<5>j1e?4:52e98m75>290/?4;527a8j6?32;o07d<<8;29 6?22;<h7c=64;0e?>o5;>0;6)=65;05g>h41=08<65f22494?"41<09:n5a386974=<a;9?6=4+387963e<f:3?6><4;h007?6=,:3>6?8l;o1:0?5432c9??4?:%1:1?41k2d8594<4:9j667=83.8584=6b9m7<2=;<10e?=?:18'7<3=:?i0b>7;:248?l45n3:1(>7::34`?k5><39<76g=2d83>!5>=38=o6`<9580<>=n:;n1<7*<94812f=i;0>1?454i30`>5<#;0?1>;m4n2;7>6g<3`89n7>5$2;6>70d3g9287=m;:k16<<72-9297<9c:l0=1<4k21b>?650;&0=0<5>j1e?4:53e98m740290/?4;527a8j6?32:o07d<=6;29 6?22;<h7c=64;1e?>o5:<0;6)=65;05g>h41=0?<65f23694?"41<09:n5a386904=<a;886=4+387963e<f:3?69<4;h016?6=,:3>6?8l;o1:0?2432c9><4?:%1:1?41k2d8594;4:9j676=83.8584=6b9m7<2=<<10e??j:18'7<3=:?i0b>7;:548?l46l3:1(>7::34`?k5><3><76g=1b83>!5>=38=o6`<9587<>=n:8h1<7*<94812f=i;0>18454i33b>5<#;0?1>;m4n2;7>1g<3`8:57>5$2;6>70d3g9287:m;:k15=<72-9297<9c:l0=1<3k21b><950;&0=0<5>j1e?4:54e98m771290/?4;527a8j6?32=o07d<>5;29 6?22;<h7c=64;6e?>o59:0;6)=65;05g>h41=0><65f20094?"41<09:n5a386914=<a;;:6=4+387963e<f:3?68<4;h024?6=,:3>6?8l;o1:0?3432c9<k4?:%1:1?41k2d8594:4:9j65c=83.8584=6b9m7<2==<10e?>k:18'7<3=:?i0b>7;:448?l47k3:1(>7::34`?k5><3?<76g=0c83>!5>=38=o6`<9586<>=n:9k1<7*<94812f=i;0>19454i32;>5<#;0?1>;m4n2;7>0g<3`8;;7>5$2;6>70d3g9287;m;:k143<72-9297<9c:l0=1<2k21b>=;50;&0=0<5>j1e?4:55e98m763290/?4;527a8j6?32<o07d<?3;29 6?22;<h7c=64;7e?>o58;0;6)=65;05g>h41=0=<65f21394?"41<09:n5a386924=<a;:;6=4+387963e<f:3?6;<4;h3eb?6=,:3>6?8l;o1:0?0432c:ji4?:%1:1?41k2d859494:9j5ce=83.8584=6b9m7<2=><10e<hm:18'7<3=:?i0b>7;:748?l7ai3:1(>7::34`?k5><3<<76g>f883>!5>=38=o6`<9585<>=n9o21<7*<94812f=i;0>1:454i0d4>5<#;0?1>;m4n2;7>3g<3`;m:7>5$2;6>70d3g92878m;:k2b0<72-9297<9c:l0=1<1k21b=k:50;&0=0<5>j1e?4:56e98m4`5290/?4;527a8j6?32?o07d?i1;29 6?22;<h7c=64;4e?>o6n90;6)=65;05g>h41=0<<65f1dd94?"41<09:n5a386934=<a8on6=4+387963e<f:3?6:<4;h3f`?6=,:3>6?8l;o1:0?1432c:in4?:%1:1?41k2d859484:9j5`d=83.8584=6b9m7<2=?<10e<kn:18'7<3=:?i0b>7;:648?l7b13:1(>7::34`?k5><3=<76g=c283>!5>=38=o6`<9584<>=n:j81<7*<94812f=i;0>1;454i3a2>5<#;0?1>;m4n2;7>2g<3`8h<7>5$2;6>70d3g92879m;:k1fc<72-9297<9c:l0=1<0k21b>ok50;&0=0<5>j1e?4:57e98m7dc290/?4;527a8j6?32>o07d<mc;29 6?22;<h7c=64;5e?>o5jk0;6)=65;05g>h41=03<65f2cc94?"41<09:n5a3869<4=<a;h36=4+387963e<f:3?65<4;h0a3?6=,:3>6?8l;o1:0?>432c9n;4?:%1:1?41k2d859474:9j6g3=83.8584=6b9m7<2=0<10e?l;:18'7<3=:?i0b>7;:948?l4e;3:1(>7::34`?k5><32<76g=b383>!5>=38=o6`<958;<>=n:k;1<7*<94812f=i;0>14454i3`3>5<#;0?1>;m4n2;7>=g<3`8jj7>5$2;6>70d3g92876m;:k1ea<72-9297<9c:l0=1<?k21b>lm50;&0=0<5>j1e?4:58e98m7ge290/?4;527a8j6?321o07d<na;29 6?22;<h7c=64;:e?>o5i00;6)=65;05g>h41=02<65f2`:94?"41<09:n5a3869=4=<a;k<6=4+387963e<f:3?64<4;h0b2?6=,:3>6?8l;o1:0??432c9m84?:%1:1?41k2d859464:9j6d2=83.8584=6b9m7<2=1<10e?o=:18'7<3=:?i0b>7;:848?l4f93:1(>7::34`?k5><33<76g=a183>!5>=38=o6`<958:<>=n:0l1<7*<94812f=i;0>15454i3;f>5<#;0?1>;m4n2;7><g<3`82h7>5$2;6>70d3g92877m;:k1=f<72-9297<9c:l0=1<>k21b>4l50;&0=0<5>j1e?4:59e98m7?f290/?4;527a8j6?320o07d<69;29 6?22;<h7c=64;;e?>o51>0;6)=65;05g>h41=0j<65f28494?"41<09:n5a3869e4=<a;3>6=4+387963e<f:3?6l<4;h0:0?6=,:3>6?8l;o1:0?g432c95>4?:%1:1?41k2d8594n4:9j6<4=83.8584=6b9m7<2=i<10e?7>:18'7<3=:?i0b>7;:`48?l4>83:1(>7::34`?k5><3k<76g=8g83>!5>=38=o6`<958b<>=n:1o1<7*<94812f=i;0>1m454i3:`>5<#;0?1>;m4n2;7>dg<3`83n7>5$2;6>70d3g9287om;:k1<d<72-9297<9c:l0=1<fk21b>5750;&0=0<5>j1e?4:5ae98m7>?290/?4;527a8j6?32ho07d<77;29 6?22;<h7c=64;ce?>o50?0;6)=65;05g>h41=0i<65f29794?"41<09:n5a3869f4=<a;2?6=4+387963e<f:3?6o<4;h0;7?6=,:3>6?8l;o1:0?d432c94<4?:%1:1?41k2d8594m4:9j6=6=83.8584=6b9m7<2=j<10e?9i:18'7<3=:?i0b>7;:c48?l40m3:1(>7::34`?k5><3h<76g=7e83>!5>=38=o6`<958a<>=n:>i1<7*<94812f=i;0>1n454i35a>5<#;0?1>;m4n2;7>gg<3`8<m7>5$2;6>70d3g9287lm;:k13<<72-9297<9c:l0=1<ek21b>:650;&0=0<5>j1e?4:5be98m711290/?4;527a8j6?32ko07d<85;29 6?22;<h7c=64;`e?>o5?=0;6)=65;05g>h41=0h<65f26194?"41<09:n5a3869g4=<a;=96=4+387963e<f:3?6n<4;h045?6=,:3>6?8l;o1:0?e432c9;=4?:%1:1?41k2d8594l4:9j63`=83.8584=6b9m7<2=k<10e?8j:18'7<3=:?i0b>7;:b48?l41:3:1(>7::34`?k5><3i<76g=5783>!5>=38=o6`<958`<>=n:=h1<7*<94812f=i;0>1o454i363>5<#;0?1>;m4n2;7>fg<3`8897>5$2;6>70d3g9287mm;:k16d<72-9297<9c:l0=1<dk21b><h50;&0=0<5>j1e?4:5ce98m773290/?4;527a8j6?32jo07d<?9;29 6?22;<h7c=64;ae?>o6nl0;6)=65;05g>h41=0o<65f1g194?"41<09:n5a3869`4=<a;i>6=4+387963e<f:3?6i<4;h0a=?6=,:3>6?8l;o1:0?b432c9mh4?:%1:1?41k2d8594k4:9j6d5=83.8584=6b9m7<2=l<10e?77:18'7<3=:?i0b>7;:e48?l4?l3:1(>7::34`?k5><3n<76g=8383>!5>=38=o6`<958g<>=n:>=1<7*<94812f=i;0>1h454i374>5<#;0?1>;m4n2;7>ag<3`;n47>5$2;6>70d3g9287jm;:kbg?6=3`9j47>5;h1g5?6=3`9o<7>5;h1g6?6=3f9o?7>5;n0`2?6=3kh<j7>51;294~"3;80i995Gb6f8Lg2f3f92>7>5;|`02=<728i157<:{I`7e>"3;80i4l5U96824c=u-8h477l8:k0g3<72-9297=l5:l0=1<732c8o94?:%1:1?5d=2d8594>;:k0g6<72-9297=l5:l0=1<532c8o?4?:%1:1?5d=2d8594<;:k0g4<72-9297=l5:l0=1<332c8o=4?:%1:1?5d=2d8594:;:k0fc<72-9297=l5:l0=1<132c8nh4?:%1:1?5d=2d85948;:k0fa<72-9297=l5:l0=1<?32c8nn4?:%1:1?5d=2d85946;:k0gc<72-9297=l5:l0=1<f32c8oh4?:%1:1?5d=2d8594m;:k0ga<72-9297=l5:l0=1<d32c8on4?:%1:1?5d=2d8594k;:k0gg<72-9297=l5:l0=1<b32c8ol4?:%1:1?5d=2d8594i;:k0g<<72-9297=l5:l0=1<6821b?n650;&0=0<4k<1e?4:51098m6e0290/?4;53b78j6?328807d=mb;29 6?22:i>7c=64;30?>ofk3:17d=n8;29?l7b>3:17d=k1;29?l5c83:17d=k2;29?j5c;3:17b<l6;29?gd0m3:1=7>50z&774<5k>1Cn:j4Hc6b?j7b=3:17plm4b83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xde=:0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g0a3-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg35290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a2c=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a14<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c4e?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc73>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm4e83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xde<o0;694?:1y'067=;1:0Do9k;I`7e>"4i00i:k5fa783>>oc?3:17d=m0;29?j50?3:17plm4d83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xu6m?0;6?uQ1d489g2d2h<0q~<l6;296~X5k?16n9h53658yv5?>3:19v3m7d82a0=:j=i1h:52b5f9`2=:j=l1h:52b5g9`2=z{:hi6=4={_1af>;e=90?86s|3ca94?4|V:hh70l:2;67?xu4jm0;6?uQ3cf89g352=?0q~=me;296~X4jl16n8<5479~w6da2909wS=mf:?a17<3?2wx?n>50;0xZ6e734h>>7:6;|q0g4<72;qU?n?4=c70>12<uz9h>7>52z\0g7=:j<91885rs2a0>5<5sW9h?63m52872>{t;j>1<7<t^2a7?8d2;3><7p}<c783>7}Y;j<01o;<:5;8yv5d?3:1>vP<c69>f06=<<1v>m7:181[5d027i9=4;6:p7f?=838pR>m6;<`64?203ty8ol4?:3y]7fg<5k?;6974}r1`f?6=:rT8oo52b43901=z{:ih6=4={_1`g>;e=80?96s|3bf94?4|V:io70l:1;65?xu4kl0;6?uQ3bg89g362==0q~=lf;296~X4ko16n8?5489~w6b7290>wS=k0:?a16<f<27i9?4n4:?a14<f<27i9=4n4:p7a7=83?pR>j>;<`67?g034h>>7o8;<`65?g034h><7o8;|q0`7<72;qU?i<4=c70>a0<uz9o?7>52z\0`6=:j<:1?474}r`b<?6=:r7i9<4<989>f06=l?1voo6:1818d2:392563m508g2>{tjhk1<7<t=c70>6?>34h>>7j9;|qaeg<72;q6n9m536589g2c2h<0q~lnc;296~;e<m08;:52b5g9e3=z{kko6=4={<`7b?g134h?i7=87:pfg6=838p1o:l:2`3?8d28392;6s|bc394?4|5k?:6>78;<`7`?5e82wxno<50;0x9g352:3<70l;e;1a4>{tjk91<7<t=c70>6?034h?j7=m0:~f60f290:o77524yKf1g<,=9:6o6j;[;4>4}6m3w/>n659b:8m6e1290/?4;53b78j6?32910e>m;:18'7<3=;j?0b>7;:098m6e4290/?4;53b78j6?32;10e>m=:18'7<3=;j?0b>7;:298m6e6290/?4;53b78j6?32=10e>m?:18'7<3=;j?0b>7;:498m6da290/?4;53b78j6?32?10e>lj:18'7<3=;j?0b>7;:698m6dc290/?4;53b78j6?32110e>ll:18'7<3=;j?0b>7;:898m6ea290/?4;53b78j6?32h10e>mj:18'7<3=;j?0b>7;:c98m6ec290/?4;53b78j6?32j10e>ml:18'7<3=;j?0b>7;:e98m6ee290/?4;53b78j6?32l10e>mn:18'7<3=;j?0b>7;:g98m6e>290/?4;53b78j6?328:07d=l8;29 6?22:i>7c=64;32?>o4k>0;6)=65;1`1>h41=0:>65f3c`94?"41<08o85a386956=<ahi1<75f3`:94?=n9l<1<75f3e394?=n;m:1<75f3e094?=h;m91<75`2b494?=ej>o1<7?50;2x 1562;i<7El8d:Ja0d=h9l?1<75rbc6`>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g173`k=6=44ie594?=n;k:1<75`36594?=zjk?86=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&0e<<e?91/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xde=;0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g173-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg36290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a35=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a15<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c53?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc6g>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g173`k=6=44ie594?=n;k:1<75`36594?=zjk>m6=4;:183!249393<6Fm7e9Kf1g<,:k26o9?;hc5>5<<am=1<75f3c294?=h;>=1<75rbc6f>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g173`k=6=44ie594?=n;k:1<75`36594?=z{8o=6=4={_3f2>;e<j0j:6s|2b494?4|V;i=70l;f;143>{t;1<1<7;t=c5f>4c234h?o7j8;<`7`?b034h?j7j8;<`7a?b03ty8no4?:3y]7gd<5k?;69:4}r1ag?6=:rT8nn52b40901=z{:ho6=4={_1a`>;e=;0?96s|3cg94?4|V:hn70l:2;65?xu4jo0;6?uQ3cd89g352==0q~=l0;296~X4k916n8<5489~w6e62909wS=l1:?a16<3<2wx?n<50;0xZ6e534h>?7::;|q0g6<72;qU?n=4=c70>10<uz9h87>52z\0g1=:j<918:5rs2a5>5<5sW9h:63m5287=>{t;j=1<7<t^2a4?8d283>>7p}<c983>7}Y;j201o;?:548yv5d13:1>vP<c89>f06=<>1v>mn:181[5di27i9=4;9:p7fd=838pR>mm;<`65?233ty8on4?:3y]7fe<5k?:69;4}r1``?6=:rT8oi52b43903=z{:in6=4={_1`a>;e=80?;6s|3bd94?4|V:im70l:1;6:?xu4l90;68uQ3e289g342h>01o;=:`689g362h>01o;?:`68yv5c93:19vP<d09>f05=i>16n8<5a69>f07=i>16n8>5a69~w6b52909wS=k2:?a16<c>2wx?i=50;0xZ6b434h><7=69:pfd>=838p1o;>:2;:?8d283n=7p}ma883>7}:j<81?474=c72>a0<uzhjm7>52z?a16<41016n8<5d79~wgge2909w0l;c;143>;e<m0j:6s|b`a94?4|5k>o6>98;<`7a?g13tyimi4?:3y>f1`=i?16n9k53658yvde83:1>v3m4b80f5=:j<:1?494}r`a5?6=:r7i9<4<969>f1b=;k:0q~lm2;296~;e=;085:52b5g97g6<uzhi?7>52z?a16<41>16n9h53c28yxd4>k0;6<m59;06Md3i2.??<4m8g9Y=2<6s8o1q)<l8;;`<>o4k?0;6)=65;1`1>h41=0;76g<c583>!5>=39h96`<9582?>o4k:0;6)=65;1`1>h41=0976g<c383>!5>=39h96`<9580?>o4k80;6)=65;1`1>h41=0?76g<c183>!5>=39h96`<9586?>o4jo0;6)=65;1`1>h41=0=76g<bd83>!5>=39h96`<9584?>o4jm0;6)=65;1`1>h41=0376g<bb83>!5>=39h96`<958:?>o4ko0;6)=65;1`1>h41=0j76g<cd83>!5>=39h96`<958a?>o4km0;6)=65;1`1>h41=0h76g<cb83>!5>=39h96`<958g?>o4kk0;6)=65;1`1>h41=0n76g<c`83>!5>=39h96`<958e?>o4k00;6)=65;1`1>h41=0:<65f3b:94?"41<08o85a386954=<a:i<6=4+38797f3<f:3?6<<4;h1af?6=,:3>6>m:;o1:0?7432cjo7>5;h1b<?6=3`;n:7>5;h1g5?6=3`9o<7>5;h1g6?6=3f9o?7>5;n0`2?6=3kh<i7>51;294~"3;809o:5Gb6f8Lg2f3f;n97>5;|`a0f<72=0;6=u+42397=6<@k=o7El;a:&0e<<e?:1bm;4?::kg3?6=3`9i<7>5;n143?6=3thi9>4?:`83>5}#<:;1?oo4Hc5g?Md3i2P2;7?t368~ 6g>2k=87)<j0;68md1=831bh;4?::kb0?6=3f92;7>5;n1:=?6=3`>26=4+38790==i;0>1<65f4683>!5>=3>37c=64;38?l21290/?4;5499m7<2=:21b884?:%1:1?2?3g9287=4;h67>5<#;0?1855a38690>=zjk?96=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&0e<<e?:1/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xde=80;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g143-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg37290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a36=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a0a<72=0;6=u+42397=6<@k=o7El;a:&0e<<e?:1bm;4?::kg3?6=3`9i<7>5;n143?6=3thi8k4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m729je3<722co;7>5;h1a4?6=3f9<;7>5;|`a0`<72=0;6=u+42397=6<@k=o7El;a:&0e<<e?:1bm;4?::kg3?6=3`9i<7>5;n143?6=3ty:i;4?:3y]5`0<5k>h6l84}r0`2?6=:rT9o;52b5d9721<uz93:7>55z?a3`<6m<16n9m5d69>f1b=l>16n9h5d69>f1c=l>1v>lm:181[5ej27i9=4;4:p7ge=838pR>ll;<`66?233ty8ni4?:3y]7gb<5k?969;4}r1aa?6=:rT8nh52b40903=z{:hm6=4={_1ab>;e=;0?;6s|3b294?4|V:i;70l:2;6:?xu4k80;6?uQ3b389g342=>0q~=l2;296~X4k;16n8=5449~w6e42909wS=l3:?a16<3>2wx?n:50;0xZ6e334h>?7:8;|q0g3<72;qU?n84=c70>1?<uz9h;7>52z\0g2=:j<:1885rs2a;>5<5sW9h463m51872>{t;j31<7<t^2a:?8d283><7p}<c`83>7}Y;jk01o;?:5;8yv5dj3:1>vP<cc9>f07=<=1v>ml:181[5dk27i9<4;5:p7fb=838pR>mk;<`65?213ty8oh4?:3y]7fc<5k?:6994}r1`b?6=:rT8ok52b4390<=z{:n;6=4:{_1g4>;e=:0j863m538b0>;e=80j863m518b0>{t;m;1<7;t^2f2?8d2;3k<70l:2;c4?8d293k<70l:0;c4?xu4l;0;6?uQ3e089g342m<0q~=k3;296~X4l:16n8>538;8yvdf03:1>v3m5080=<=:j<:1h;5rscc:>5<5s4h>>7=69:?a14<c>2wxnlo50;0x9g342:3270l:2;f5?xueik0;6?u2b5a9721<5k>o6l84}r`bg?6=:r7i8i4<769>f1c=i?1vook:1818d3n3k=70l;e;143>{tjk:1<7<t=c6`>6d734h><7=67:pfg7=838p1o;>:2;4?8d3l39i<6s|bc094?4|5k?96>78;<`7a?5e82wxno=50;0x9g342:3<70l;f;1a4>{zj:<h6=4>c;;960}Oj=k0(9=>:c;3?_?028q:i7s+2b:9=f><a:i=6=4+38797f3<f:3?6=54i2a7>5<#;0?1?n;4n2;7>4=<a:i86=4+38797f3<f:3?6?54i2a1>5<#;0?1?n;4n2;7>6=<a:i:6=4+38797f3<f:3?6954i2a3>5<#;0?1?n;4n2;7>0=<a:hm6=4+38797f3<f:3?6;54i2`f>5<#;0?1?n;4n2;7>2=<a:ho6=4+38797f3<f:3?6554i2``>5<#;0?1?n;4n2;7><=<a:im6=4+38797f3<f:3?6l54i2af>5<#;0?1?n;4n2;7>g=<a:io6=4+38797f3<f:3?6n54i2a`>5<#;0?1?n;4n2;7>a=<a:ii6=4+38797f3<f:3?6h54i2ab>5<#;0?1?n;4n2;7>c=<a:i26=4+38797f3<f:3?6<>4;h1`<?6=,:3>6>m:;o1:0?7632c8o:4?:%1:1?5d=2d8594>2:9j7gd=83.8584<c49m7<2=9:10elm50;9j7d>=831b=h850;9j7a7=831b?i>50;9j7a4=831d?i=50;9l6f0=831in:k50;394?6|,=9:6?m8;I`4`>Ne<h1d=h;50;9~fg2d290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k=?7do9:188ma1=831b?o>50;9l721=831vno;<:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"4i00i;95+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3thi9?4?:`83>5}#<:;1?oo4Hc5g?Md3i2P2;7?t368~ 6g>2k=?7)<j0;68md1=831bh;4?::kb0?6=3f92;7>5;n1:=?6=3`>26=4+38790==i;0>1<65f4683>!5>=3>37c=64;38?l21290/?4;5499m7<2=:21b884?:%1:1?2?3g9287=4;h67>5<#;0?1855a38690>=zjk?:6=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&0e<<e?=1/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xde=90;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g133-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg2c290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k=?7do9:188ma1=831b?o>50;9l721=831vno:i:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c57?lg12900ei950;9j7g6=831d?:950;9~fg2b290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k=?7do9:188ma1=831b?o>50;9l721=831v<k9:181[7b>27i8n4n6:p6f0=838pR?m9;<`7b?50?2wx?5850;7x9g1b28o>70l;c;f4?8d3l3n<70l;f;f4?8d3m3n<7p}<bc83>7}Y;kh01o;?:568yv5ek3:1>vP<bb9>f04=<=1v>lk:181[5el27i9?4;5:p7gc=838pR>lj;<`66?213ty8nk4?:3y]7g`<5k?96994}r1`4?6=:rT8o=52b4090<=z{:i:6=4={_1`5>;e=:0?86s|3b094?4|V:i970l:3;66?xu4k:0;6?uQ3b189g342=<0q~=l4;296~X4k=16n8=5469~w6e12909wS=l6:?a16<312wx?n950;0xZ6e034h><7::;|q0g=<72;qU?n64=c73>10<uz9h57>52z\0g<=:j<:18:5rs2ab>5<5sW9hm63m5187=>{t;jh1<7<t^2aa?8d293>?7p}<cb83>7}Y;ji01o;>:578yv5dl3:1>vP<ce9>f07=<?1v>mj:181[5dm27i9<4;7:p7f`=838pR>mi;<`65?2>3ty8h=4?:4y]7a6<5k?86l:4=c71>d2<5k?:6l:4=c73>d2<uz9o=7>55z\0`4=:j<91m:52b409e2=:j<;1m:52b429e2=z{:n96=4={_1g6>;e=:0o:6s|3e194?4|V:n870l:0;1:=>{tjh21<7<t=c72>6?>34h><7j9;|qae<<72;q6n8<538;89g362m<0q~lna;296~;e=:085452b409`3=z{kki6=4={<`7g?50?27i8i4n6:pfde=838p1o:k:254?8d3m3k=7p}mae83>7}:j=l1m;52b5g9721<uzhi<7>52z?a0f<4j916n8>53858yvde93:1>v3m5080=2=:j=n1?o>4}r`a6?6=:r7i9?4<969>f1c=;k:0q~lm3;296~;e=:085:52b5d97g6<uth8:i4?:0a9=?42sAh?m6*;308a=4=]1>0:w<k5}%0`<??d02c8o;4?:%1:1?5d=2d8594?;:k0g1<72-9297=l5:l0=1<632c8o>4?:%1:1?5d=2d8594=;:k0g7<72-9297=l5:l0=1<432c8o<4?:%1:1?5d=2d8594;;:k0g5<72-9297=l5:l0=1<232c8nk4?:%1:1?5d=2d85949;:k0f`<72-9297=l5:l0=1<032c8ni4?:%1:1?5d=2d85947;:k0ff<72-9297=l5:l0=1<>32c8ok4?:%1:1?5d=2d8594n;:k0g`<72-9297=l5:l0=1<e32c8oi4?:%1:1?5d=2d8594l;:k0gf<72-9297=l5:l0=1<c32c8oo4?:%1:1?5d=2d8594j;:k0gd<72-9297=l5:l0=1<a32c8o44?:%1:1?5d=2d8594>0:9j7f>=83.8584<c49m7<2=9810e>m8:18'7<3=;j?0b>7;:008?l5ej3:1(>7::2a6?k5><3;876gnc;29?l5f03:17d?j6;29?l5c93:17d=k0;29?l5c:3:17b=k3;29?j4d>3:17ol8e;295?6=8r.??<4=c69Kf2b<@k>j7b?j5;29?xde<j0;694?:1y'067=;1:0Do9k;I`7e>"4i00i;85fa783>>oc?3:17d=m0;29?j50?3:17plm5283>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o9:;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno;=:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"4i00i;85+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3thi9<4?:`83>5}#<:;1?oo4Hc5g?Md3i2P2;7?t368~ 6g>2k=>7)<j0;68md1=831bh;4?::kb0?6=3f92;7>5;n1:=?6=3`>26=4+38790==i;0>1<65f4683>!5>=3>37c=64;38?l21290/?4;5499m7<2=:21b884?:%1:1?2?3g9287=4;h67>5<#;0?1855a38690>=zjk?;6=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&0e<<e?<1/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xde<m0;694?:1y'067=;1:0Do9k;I`7e>"4i00i;85fa783>>oc?3:17d=m0;29?j50?3:17plm4g83>1<729q/8>?53928Lg1c3Ah?m6*<a88a30=ni?0;66gk7;29?l5e83:17b=87;29?xde<l0;694?:1y'067=;1:0Do9k;I`7e>"4i00i;85fa783>>oc?3:17d=m0;29?j50?3:17p}>e783>7}Y9l<01o:l:`48yv4d>3:1>vP=c79>f1`=;>=0q~=76;291~;e?l0:i852b5a9`2=:j=n1h:52b5d9`2=:j=o1h:5rs2`a>5<5sW9in63m51870>{t;ki1<7<t^2``?8d2:3>?7p}<be83>7}Y;kn01o;=:578yv5em3:1>vP<bd9>f04=<?1v>li:181[5en27i9?4;7:p7f6=838pR>m?;<`66?2>3ty8o<4?:3y]7f7<5k?869:4}r1`6?6=:rT8o?52b41900=z{:i86=4={_1`7>;e=:0?:6s|3b694?4|V:i?70l:3;64?xu4k?0;6?uQ3b489g342=30q~=l7;296~X4k>16n8>5449~w6e?2909wS=l8:?a15<3>2wx?n750;0xZ6e>34h><7:8;|q0gd<72;qU?no4=c73>1?<uz9hn7>52z\0gg=:j<;1895rs2a`>5<5sW9ho63m50871>{t;jn1<7<t^2ag?8d293>=7p}<cd83>7}Y;jo01o;>:558yv5dn3:1>vP<cg9>f07=<01v>j?:186[5c827i9>4n4:?a17<f<27i9<4n4:?a15<f<2wx?i?50;7xZ6b634h>?7o8;<`66?g034h>=7o8;<`64?g03ty8h?4?:3y]7a4<5k?86i84}r1g7?6=:rT8h>52b4297<?<uzhj47>52z?a14<41016n8>5d79~wgg>2909w0l:2;1:=>;e=80o:6s|b`c94?4|5k?86>76;<`66?b13tyimo4?:3y>f1e=;>=01o:k:`48yvdfk3:1>v3m4e8032=:j=o1m;5rsccg>5<5s4h?j7o9;<`7a?50?2wxno>50;0x9g2d2:h;70l:0;1:3>{tjk;1<7<t=c72>6?034h?h7=m0:pfg4=838p1o;=:2;4?8d3m39i<6s|bc194?4|5k?86>78;<`7b?5e82wvn>8j:182g??=:<qCn9o4$512>g?53S3<6<u>e;'6f>=1j20e>m9:18'7<3=;j?0b>7;:198m6e3290/?4;53b78j6?32810e>m<:18'7<3=;j?0b>7;:398m6e5290/?4;53b78j6?32:10e>m>:18'7<3=;j?0b>7;:598m6e7290/?4;53b78j6?32<10e>li:18'7<3=;j?0b>7;:798m6db290/?4;53b78j6?32>10e>lk:18'7<3=;j?0b>7;:998m6dd290/?4;53b78j6?32010e>mi:18'7<3=;j?0b>7;:`98m6eb290/?4;53b78j6?32k10e>mk:18'7<3=;j?0b>7;:b98m6ed290/?4;53b78j6?32m10e>mm:18'7<3=;j?0b>7;:d98m6ef290/?4;53b78j6?32o10e>m6:18'7<3=;j?0b>7;:028?l5d03:1(>7::2a6?k5><3;:76g<c683>!5>=39h96`<95826>=n;kh1<7*<9480g0=i;0>1=>54i`a94?=n;h21<75f1d494?=n;m;1<75f3e294?=n;m81<75`3e194?=h:j<1<75mb6g94?7=83:p(9=>:3a4?Md0l2Bi8l5`1d794?=zjk>h6=4;:183!249393<6Fm7e9Kf1g<,:k26o99;hc5>5<<am=1<75f3c294?=h;>=1<75rbc70>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m779'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm5383>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o99;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno;>:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"4i00i;;5+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3thi9=4?:`83>5}#<:;1?oo4Hc5g?Md3i2P2;7?t368~ 6g>2k==7)<j0;68md1=831bh;4?::kb0?6=3f92;7>5;n1:=?6=3`>26=4+38790==i;0>1<65f4683>!5>=3>37c=64;38?l21290/?4;5499m7<2=:21b884?:%1:1?2?3g9287=4;h67>5<#;0?1855a38690>=zjk>o6=4;:183!249393<6Fm7e9Kf1g<,:k26o99;hc5>5<<am=1<75f3c294?=h;>=1<75rbc6e>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g113`k=6=44ie594?=n;k:1<75`36594?=zjk>n6=4;:183!249393<6Fm7e9Kf1g<,:k26o99;hc5>5<<am=1<75f3c294?=h;>=1<75rs0g5>5<5sW;n:63m4b8b2>{t:j<1<7<t^3a5?8d3n39<;6s|39494?3|5k=n6<k:;<`7g?b034h?h7j8;<`7b?b034h?i7j8;|q0fg<72;qU?ol4=c73>12<uz9io7>52z\0ff=:j<81895rs2`g>5<5sW9ih63m53871>{t;ko1<7<t^2`f?8d2:3>=7p}<bg83>7}Y;kl01o;=:558yv5d83:1>vP<c19>f04=<01v>m>:181[5d927i9>4;4:p7f4=838pR>m=;<`67?223ty8o>4?:3y]7f5<5k?86984}r1`0?6=:rT8o952b41902=z{:i=6=4={_1`2>;e=:0?56s|3b594?4|V:i<70l:0;66?xu4k10;6?uQ3b:89g372=<0q~=l9;296~X4k016n8>5469~w6ef2909wS=la:?a15<312wx?nl50;0xZ6ee34h>=7:;;|q0gf<72;qU?nm4=c72>13<uz9hh7>52z\0ga=:j<;18;5rs2af>5<5sW9hi63m50873>{t;jl1<7<t^2ae?8d293>27p}<d183>0}Y;m:01o;<:`689g352h>01o;>:`689g372h>0q~=k1;291~X4l816n8=5a69>f04=i>16n8?5a69>f06=i>1v>j=:181[5c:27i9>4k6:p7a5=838pR>j<;<`64?5>12wxnl650;0x9g362:3270l:0;f5?xuei00;6?u2b4097<?<5k?:6i84}r`be?6=:r7i9>4<989>f04=l?1voom:1818d3k39<;63m4e8b2>{tjhi1<7<t=c6g>61034h?i7o9;|qaea<72;q6n9h5a79>f1c=;>=0q~lm0;296~;e<j08n=52b4297<1<uzhi=7>52z?a14<41>16n9j53c28yvde:3:1>v3m5380=2=:j=o1?o>4}r`a7?6=:r7i9>4<969>f1`=;k:0qpl<6g83>4e=138>wEl;a:&774<e1:1Q5:4>{0g9y!4d033h46g<c783>!5>=39h96`<9583?>o4k=0;6)=65;1`1>h41=0:76g<c283>!5>=39h96`<9581?>o4k;0;6)=65;1`1>h41=0876g<c083>!5>=39h96`<9587?>o4k90;6)=65;1`1>h41=0>76g<bg83>!5>=39h96`<9585?>o4jl0;6)=65;1`1>h41=0<76g<be83>!5>=39h96`<958;?>o4jj0;6)=65;1`1>h41=0276g<cg83>!5>=39h96`<958b?>o4kl0;6)=65;1`1>h41=0i76g<ce83>!5>=39h96`<958`?>o4kj0;6)=65;1`1>h41=0o76g<cc83>!5>=39h96`<958f?>o4kh0;6)=65;1`1>h41=0m76g<c883>!5>=39h96`<95824>=n;j21<7*<9480g0=i;0>1=<54i2a4>5<#;0?1?n;4n2;7>44<3`9in7>5$2;6>6e23g9287?<;:kbg?6=3`9j47>5;h3f2?6=3`9o=7>5;h1g4?6=3`9o>7>5;n1g7?6=3f8h:7>5;c`4a?6=93:1<v*;3081g2=Oj>n0Do:n;n3f1?6=3thi8n4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m769je3<722co;7>5;h1a4?6=3f9<;7>5;|`a16<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c54?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc71>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m769'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm5083>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o98;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno;?:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"4i00i;:5+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3thi8i4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m769je3<722co;7>5;h1a4?6=3f9<;7>5;|`a0c<72=0;6=u+42397=6<@k=o7El;a:&0e<<e?>1bm;4?::kg3?6=3`9i<7>5;n143?6=3thi8h4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m769je3<722co;7>5;h1a4?6=3f9<;7>5;|q2a3<72;qU=h84=c6`>d0<uz8h:7>52z\1g3=:j=l1?:94}r1;2?6==r7i;h4>e49>f1e=l>16n9j5d69>f1`=l>16n9k5d69~w6de2909wS=mb:?a15<3<2wx?om50;0xZ6dd34h>>7:;;|q0fa<72;qU?oj4=c71>13<uz9ii7>52z\0f`=:j<818;5rs2`e>5<5sW9ij63m53873>{t;j:1<7<t^2a3?8d2:3>27p}<c083>7}Y;j;01o;<:568yv5d:3:1>vP<c39>f05=<<1v>m<:181[5d;27i9>4;6:p7f2=838pR>m;;<`67?203ty8o;4?:3y]7f0<5k?86974}r1`3?6=:rT8o:52b42900=z{:i36=4={_1`<>;e=90?:6s|3b;94?4|V:i270l:0;64?xu4kh0;6?uQ3bc89g372=30q~=lb;296~X4kk16n8?5459~w6ed2909wS=lc:?a14<3=2wx?nj50;0xZ6ec34h>=7:9;|q0g`<72;qU?nk4=c72>11<uz9hj7>52z\0gc=:j<;1845rs2f3>5<2sW9o<63m528b0>;e=;0j863m508b0>;e=90j86s|3e394?3|V:n:70l:3;c4?8d2:3k<70l:1;c4?8d283k<7p}<d383>7}Y;m801o;<:e48yv5c;3:1>vP<d29>f06=;030q~ln8;296~;e=8085452b429`3=z{kk26=4={<`66?5>127i9<4k6:pfdg=838p1o;<:2;:?8d2:3n=7p}mac83>7}:j=i1?:94=c6g>d0<uzhjo7>52z?a0a<4?>16n9k5a79~wggc2909w0l;f;c5?8d3m39<;6s|bc294?4|5k>h6>l?;<`64?5>?2wxno?50;0x9g362:3<70l;d;1a4>{tjk81<7<t=c71>6?034h?i7=m0:pfg5=838p1o;<:2;4?8d3n39i<6srb253>5<6k331>8uGb5c8 1562k3?7W78:0y2a?{#:j215n64i2a5>5<#;0?1?n;4n2;7>5=<a:i?6=4+38797f3<f:3?6<54i2a0>5<#;0?1?n;4n2;7>7=<a:i96=4+38797f3<f:3?6>54i2a2>5<#;0?1?n;4n2;7>1=<a:i;6=4+38797f3<f:3?6854i2`e>5<#;0?1?n;4n2;7>3=<a:hn6=4+38797f3<f:3?6:54i2`g>5<#;0?1?n;4n2;7>==<a:hh6=4+38797f3<f:3?6454i2ae>5<#;0?1?n;4n2;7>d=<a:in6=4+38797f3<f:3?6o54i2ag>5<#;0?1?n;4n2;7>f=<a:ih6=4+38797f3<f:3?6i54i2aa>5<#;0?1?n;4n2;7>`=<a:ij6=4+38797f3<f:3?6k54i2a:>5<#;0?1?n;4n2;7>46<3`9h47>5$2;6>6e23g9287?>;:k0g2<72-9297=l5:l0=1<6:21b?ol50;&0=0<4k<1e?4:51298mde=831b?l650;9j5`0=831b?i?50;9j7a6=831b?i<50;9l7a5=831d>n850;9af2c=83;1<7>t$512>7e03Ah<h6Fm4`9l5`3=831vno:l:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c5;?lg12900ei950;9j7g6=831d?:950;9~fg34290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a3==#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a17<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c5;?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc72>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m799'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm5183>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o97;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno:k:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c5;?lg12900ei950;9j7g6=831d?:950;9~fg2a290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k=37do9:188ma1=831b?o>50;9l721=831vno:j:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c5;?lg12900ei950;9j7g6=831d?:950;9~w4c12909wS?j6:?a0f<f>2wx>n850;0xZ7e134h?j7=87:p7=0=83?p1o9j:0g6?8d3k3n<70l;d;f4?8d3n3n<70l;e;f4?xu4jk0;6?uQ3c`89g372=>0q~=mc;296~X4jj16n8<5459~w6dc2909wS=md:?a17<3=2wx?ok50;0xZ6db34h>>7:9;|q0fc<72;qU?oh4=c71>11<uz9h<7>52z\0g5=:j<81845rs2a2>5<5sW9h=63m52870>{t;j81<7<t^2a1?8d2;3>>7p}<c283>7}Y;j901o;<:548yv5d<3:1>vP<c59>f05=<>1v>m9:181[5d>27i9>4;9:p7f1=838pR>m8;<`64?223ty8o54?:3y]7f><5k?;6984}r1`=?6=:rT8o452b42902=z{:ij6=4={_1`e>;e=90?56s|3b`94?4|V:ii70l:1;67?xu4kj0;6?uQ3ba89g362=?0q~=ld;296~X4km16n8?5479~w6eb2909wS=le:?a14<3?2wx?nh50;0xZ6ea34h>=7:6;|q0`5<72<qU?i>4=c70>d2<5k?96l:4=c72>d2<5k?;6l:4}r1g5?6==rT8h<52b419e2=:j<81m:52b439e2=:j<:1m:5rs2f1>5<5sW9o>63m528g2>{t;m91<7<t^2f0?8d2839256s|b`:94?4|5k?:6>76;<`64?b13tyim44?:3y>f04=;0301o;>:e48yvdfi3:1>v3m5280=<=:j<81h;5rscca>5<5s4h?o7=87:?a0a<f>2wxnlm50;0x9g2c2:=<70l;e;c5?xueim0;6?u2b5d9e3=:j=o1?:94}r`a4?6=:r7i8n4<b19>f06=;0=0q~lm1;296~;e=8085:52b5f97g6<uzhi>7>52z?a17<41>16n9k53c28yvde;3:1>v3m5280=2=:j=l1?o>4}|`034<728i157<:{I`7e>"3;80i585U96824c=u-8h477l8:k0g3<72-9297=l5:l0=1<732c8o94?:%1:1?5d=2d8594>;:k0g6<72-9297=l5:l0=1<532c8o?4?:%1:1?5d=2d8594<;:k0g4<72-9297=l5:l0=1<332c8o=4?:%1:1?5d=2d8594:;:k0fc<72-9297=l5:l0=1<132c8nh4?:%1:1?5d=2d85948;:k0fa<72-9297=l5:l0=1<?32c8nn4?:%1:1?5d=2d85946;:k0gc<72-9297=l5:l0=1<f32c8oh4?:%1:1?5d=2d8594m;:k0ga<72-9297=l5:l0=1<d32c8on4?:%1:1?5d=2d8594k;:k0gg<72-9297=l5:l0=1<b32c8ol4?:%1:1?5d=2d8594i;:k0g<<72-9297=l5:l0=1<6821b?n650;&0=0<4k<1e?4:51098m6e0290/?4;53b78j6?328807d=mb;29 6?22:i>7c=64;30?>ofk3:17d=n8;29?l7b>3:17d=k1;29?l5c83:17d=k2;29?j5c;3:17b<l6;29?gd0m3:1=7>50z&774<5k>1Cn:j4Hc6b?j7b=3:17plm4b83>1<729q/8>?53928Lg1c3Ah?m6*<a88a3<=ni?0;66gk7;29?l5e83:17b=87;29?xde=:0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g1>3-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg35290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a3<=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a14<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c5:?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc73>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m789'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm4e83>1<729q/8>?53928Lg1c3Ah?m6*<a88a3<=ni?0;66gk7;29?l5e83:17b=87;29?xde<o0;694?:1y'067=;1:0Do9k;I`7e>"4i00i;45fa783>>oc?3:17d=m0;29?j50?3:17plm4d83>1<729q/8>?53928Lg1c3Ah?m6*<a88a3<=ni?0;66gk7;29?l5e83:17b=87;29?xu6m?0;6?uQ1d489g2d2h<0q~<l6;296~X5k?16n9h53658yv5?>3:19v3m7d82a0=:j=i1h:52b5f9`2=:j=l1h:52b5g9`2=z{:hi6=4={_1af>;e=90?86s|3ca94?4|V:hh70l:2;67?xu4jm0;6?uQ3cf89g352=?0q~=me;296~X4jl16n8<5479~w6da2909wS=mf:?a17<3?2wx?n>50;0xZ6e734h>>7:6;|q0g4<72;qU?n?4=c70>12<uz9h>7>52z\0g7=:j<91885rs2a0>5<5sW9h?63m52872>{t;j>1<7<t^2a7?8d2;3><7p}<c783>7}Y;j<01o;<:5;8yv5d?3:1>vP<c69>f06=<<1v>m7:181[5d027i9=4;6:p7f?=838pR>m6;<`64?203ty8ol4?:3y]7fg<5k?;6974}r1`f?6=:rT8oo52b43901=z{:ih6=4={_1`g>;e=80?96s|3bf94?4|V:io70l:1;65?xu4kl0;6?uQ3bg89g362==0q~=lf;296~X4ko16n8?5489~w6b7290>wS=k0:?a16<f<27i9?4n4:?a14<f<27i9=4n4:p7a7=83?pR>j>;<`67?g034h>>7o8;<`65?g034h><7o8;|q0`7<72;qU?i<4=c70>a0<uz9o?7>52z\0`6=:j<:1?474}r`b<?6=:r7i9<4<989>f06=l?1voo6:1818d2:392563m508g2>{tjhk1<7<t=c70>6?>34h>>7j9;|qaeg<72;q6n9m536589g2c2h<0q~lnc;296~;e<m08;:52b5g9e3=z{kko6=4={<`7b?g134h?i7=87:pfg6=838p1o:l:2`3?8d28392;6s|bc394?4|5k?:6>78;<`7`?5e82wxno<50;0x9g352:3<70l;e;1a4>{tjk91<7<t=c70>6?034h?j7=m0:~f615290:o77524yKf1g<,=9:6o6m;[;4>4}6m3w/>n659b:8m6e1290/?4;53b78j6?32910e>m;:18'7<3=;j?0b>7;:098m6e4290/?4;53b78j6?32;10e>m=:18'7<3=;j?0b>7;:298m6e6290/?4;53b78j6?32=10e>m?:18'7<3=;j?0b>7;:498m6da290/?4;53b78j6?32?10e>lj:18'7<3=;j?0b>7;:698m6dc290/?4;53b78j6?32110e>ll:18'7<3=;j?0b>7;:898m6ea290/?4;53b78j6?32h10e>mj:18'7<3=;j?0b>7;:c98m6ec290/?4;53b78j6?32j10e>ml:18'7<3=;j?0b>7;:e98m6ee290/?4;53b78j6?32l10e>mn:18'7<3=;j?0b>7;:g98m6e>290/?4;53b78j6?328:07d=l8;29 6?22:i>7c=64;32?>o4k>0;6)=65;1`1>h41=0:>65f3c`94?"41<08o85a386956=<ahi1<75f3`:94?=n9l<1<75f3e394?=n;m:1<75f3e094?=h;m91<75`2b494?=ej>o1<7?50;2x 1562;i<7El8d:Ja0d=h9l?1<75rbc6`>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g1f3`k=6=44ie594?=n;k:1<75`36594?=zjk?86=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&0e<<e?h1/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xde=;0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g1f3-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg36290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a3d=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a15<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c5b?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc6g>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g1f3`k=6=44ie594?=n;k:1<75`36594?=zjk>m6=4;:183!249393<6Fm7e9Kf1g<,:k26o9n;hc5>5<<am=1<75f3c294?=h;>=1<75rbc6f>5<3290;w):<1;1;4>Ne?m1Cn9o4$2c:>g1f3`k=6=44ie594?=n;k:1<75`36594?=z{8o=6=4={_3f2>;e<j0j:6s|2b494?4|V;i=70l;f;143>{t;1<1<7;t=c5f>4c234h?o7j8;<`7`?b034h?j7j8;<`7a?b03ty8no4?:3y]7gd<5k?;69:4}r1ag?6=:rT8nn52b40901=z{:ho6=4={_1a`>;e=;0?96s|3cg94?4|V:hn70l:2;65?xu4jo0;6?uQ3cd89g352==0q~=l0;296~X4k916n8<5489~w6e62909wS=l1:?a16<3<2wx?n<50;0xZ6e534h>?7::;|q0g6<72;qU?n=4=c70>10<uz9h87>52z\0g1=:j<918:5rs2a5>5<5sW9h:63m5287=>{t;j=1<7<t^2a4?8d283>>7p}<c983>7}Y;j201o;?:548yv5d13:1>vP<c89>f06=<>1v>mn:181[5di27i9=4;9:p7fd=838pR>mm;<`65?233ty8on4?:3y]7fe<5k?:69;4}r1``?6=:rT8oi52b43903=z{:in6=4={_1`a>;e=80?;6s|3bd94?4|V:im70l:1;6:?xu4l90;68uQ3e289g342h>01o;=:`689g362h>01o;?:`68yv5c93:19vP<d09>f05=i>16n8<5a69>f07=i>16n8>5a69~w6b52909wS=k2:?a16<c>2wx?i=50;0xZ6b434h><7=69:pfd>=838p1o;>:2;:?8d283n=7p}ma883>7}:j<81?474=c72>a0<uzhjm7>52z?a16<41016n8<5d79~wgge2909w0l;c;143>;e<m0j:6s|b`a94?4|5k>o6>98;<`7a?g13tyimi4?:3y>f1`=i?16n9k53658yvde83:1>v3m4b80f5=:j<:1?494}r`a5?6=:r7i9<4<969>f1b=;k:0q~lm2;296~;e=;085:52b5g97g6<uzhi?7>52z?a16<41>16n9h53c28yxd4>00;6<m5c;0bMd3i2.??<4m8b9Y=2<6s8o1q)<l8;;`<>o4k?0;6)=65;1`1>h41=0;76g<c583>!5>=39h96`<9582?>o4k:0;6)=65;1`1>h41=0976g<c383>!5>=39h96`<9580?>o4k80;6)=65;1`1>h41=0?76g<c183>!5>=39h96`<9586?>o4jo0;6)=65;1`1>h41=0=76g<bd83>!5>=39h96`<9584?>o4jm0;6)=65;1`1>h41=0376g<bb83>!5>=39h96`<958:?>o4ko0;6)=65;1`1>h41=0j76g<cd83>!5>=39h96`<958a?>o4km0;6)=65;1`1>h41=0h76g<cb83>!5>=39h96`<958g?>o4kk0;6)=65;1`1>h41=0n76g<c`83>!5>=39h96`<958e?>o4k00;6)=65;1`1>h41=0:<65f3b:94?"41<08o85a386954=<a:i<6=4+38797f3<f:3?6<<4;h1af?6=,:3>6>m:;o1:0?7432cjo7>5;h1b<?6=3`;n:7>5;h1g5?6=3`9o<7>5;h1g6?6=3f9o?7>5;n0`2?6=3kh<j7>51;294~"3;80i995Gb6f8Lg2f3f92>7>5;|`a3`<7280;6=u+42396f1<@k=o7El;a:m2a0<722wi?;;50;694?6|,=9:6<jm;I`4`>Ne<h1/?l75b608 7c728:0e4650;9j`3<722c8n=4?::m0=2<722win9m50;694?6|,=9:6>6?;I`4`>Ne<h1/?l75b638md0=831bh:4?::k0f5<722e8;:4?::af05=83k1<7>t$512>6df3Ah<h6Fm4`9Y=2<6s:=1q)=n9;`45>"5m90?7do8:188ma0=831bm94?::m0=2<722e8544?::k7=?6=,:3>6964n2;7>5=<a==1<7*<9487<>h41=0:76g;6;29 6?22=20b>7;:398m13=83.8584;8:l0=1<432c?87>5$2;6>1><f:3?6954}c`66?6=i3:1<v*;3080fd=Oj>n0Do:n;[;4>4}4?3w/?l75b638 7c72=1bm:4?::kg2?6=3`k?6=44o2;4>5<<g:326=44i5;94?"41<0?46`<9583?>o3?3:1(>7::5:8j6?32810e9850;&0=0<302d8594=;:k71?6=,:3>6964n2;7>6=<a=>1<7*<9487<>h41=0?76smb4394?g=83:p(9=>:2`b?Md0l2Bi8l5U968261=u-9j57l81:&1a5<33`k<6=44ie494?=ni=0;66a<9683>>i4100;66g;9;29 6?22=20b>7;:198m11=83.8584;8:l0=1<632c?:7>5$2;6>1><f:3?6?54i5794?"41<0?46`<9580?>o3<3:1(>7::5:8j6?32=10qol:0;29e?6=8r.??<4<b`9Kf2b<@k>j7W78:0y03?{#;h31n:?4$3g3>1=ni>0;66gk6;29?lg32900c>78:188k6?>2900e9750;&0=0<302d8594?;:k73?6=,:3>6964n2;7>4=<a=<1<7*<9487<>h41=0976g;5;29 6?22=20b>7;:298m12=83.8584;8:l0=1<332win9j50;694?6|,=9:6>6?;I`4`>Ne<h1/?l75b638md0=831bh:4?::k0f5<722e8;:4?::af1`=83>1<7>t$512>6>73Ah<h6Fm4`9'7d?=j>;0el850;9j`2<722c8n=4?::m032<722win9k50;694?6|,=9:6>6?;I`4`>Ne<h1/?l75b638md0=831bh:4?::k0f5<722e8;:4?::a730=83>1<7>t$512>6>73Ah<h6Fm4`9'7d?=j>80el850;9j`2<722c8n=4?::m032<722wxmn4?:3y]ef=:;??1555rs0g5>5<5sW;n:63m4b8b2>{t:j<1<7<t^3a5?851=392;6s|39794?4|5k=m6>7=;<152?5e82wx?5850;4x9g1b28o>70l;c;f4?8d3l3n<70l;f;f4?8d3m3n<70=96;f4?xu4i10;6?uQ3`:896022:h;7p}<bc83>7}Y;kh01o;?:568yv5ek3:1>vP<bb9>f04=<=1v>lk:181[5el27i9?4;5:p7gc=838pR>lj;<`66?213ty8nk4?:3y]7g`<5k?96994}r1`4?6=:rT8o=52b4090<=z{:i:6=4={_1`5>;e=:0?86s|3b094?4|V:i970l:3;66?xu4k:0;6?uQ3b189g342=<0q~=l4;296~X4k=16n8=5469~w6e12909wS=l6:?a16<312wx?n950;0xZ6e034h><7::;|q0g=<72;qU?n64=c73>10<uz9h57>52z\0g<=:j<:18:5rs2ab>5<5sW9hm63m5187=>{t;jh1<7<t^2aa?8d293>?7p}<cb83>7}Y;ji01o;>:578yv5dl3:1>vP<ce9>f07=<?1v>mj:181[5dm27i9<4;7:p7f`=838pR>mi;<`65?2>3ty8h=4?:4y]7a6<5k?86l:4=c71>d2<5k?:6l:4=c73>d2<uz9o=7>55z\0`4=:j<91m:52b409e2=:j<;1m:52b429e2=z{:n96=4={_1g6>;e=:0o:6s|3e194?4|V:n870l:0;1:=>{tjh21<7<t=c72>6?>34h><7j9;|qae<<72;q6n8<538;89g362m<0q~lna;296~;e=:085452b409`3=z{kki6=4={<`7g?50?27i8i4n6:pfde=838p1o:k:254?8d3m3k=7p}mae83>7}:j=l1m;52b5g9721<uzhji7>52z?a0c<4?>16?;85a79~wgga2909w0=95;f5?851>39<;6s|bc294?4|5k>h6>l?;<`64?5>?2wxno?50;0x9g362:3<70l;d;1a4>{tjk81<7<t=c71>6?034h?i7=m0:pfg5=838p1o;<:2;4?8d3n39i<6srs`a94?e|Vhi01>87:`a8960f2hi01>8m:`a8960d2hi01>8k:`a8960b2hi01>8i:`a896172hi01>9>:`a896152hi01>86:`a8yv7b03:1>vP>e99>73>=;kh0q~?j9;296~X6m016?;k53c`8yv7bi3:1>vP>e`9>73c=;j=0q~?jb;296~X6mk16?;k53b:8yv7bk3:1>vP>eb9>73c=;j30q~?jd;296~X6mm16?;k53bc8yv7bm3:1>vP>ed9>73c=;jh0q~?jf;296~X6mo16?;k53ba8yv7a83:1>vP>f19>73c=;jn0q~?i1;296~X6n816?;k53bg8yv7a:3:1>vP>f39>73c=;jl0q~?i3;296~X6n:16?;653ca8yv7a<3:1>vP>f59>73c=;ki0q~?i5;296~X6n<16?;k53cf8yv7a>3:1>vP>f79>73c=;ko0q~?i7;296~X6n>16?;k53cd8yv7a03:1>vP>f99>73c=;j:0q~?i9;296~X6n016?;k53b38yv7ai3:1>vP>f`9>73c=;j80q~?ib;296~X6nk16?;k53b18yv7ak3:1>vP>fb9>73c=;j>0q~?id;296~X6nm16?;k53b48yv7am3:1>vP>fd9>73>=;kn0q~?if;296~X6no16?;h53c`8yv4783:1>vP=019>73`=;j=0q~<?1;296~X58816?;h53b:8yv47:3:1>vP=039>73`=;j30q~<?3;296~X58:16?;h53bc8yv47<3:1>vP=059>73`=;jh0q~<?5;296~X58<16?;h53ba8yv47>3:1>vP=079>73`=;jn0q~<?7;296~X58>16?;h53bg8yv4703:1>vP=099>73`=;jl0q~<?9;296~X58016?;653cg8yv47i3:1>vP=0`9>73`=;ki0q~<?b;296~X58k16?;h53cf8yv47k3:1>vP=0b9>73`=;ko0q~<?d;296~X58m16?;h53cd8yv47m3:1>vP=0d9>73`=;j:0q~<?f;296~X58o16?;h53b38yv4683:1>vP=119>73`=;j80q~<>1;296~X59816?;h53b18yv46:3:1>vP=139>73`=;j>0q~<>3;296~X59:16?;h53b48yv46<3:1>vP=159>73>=;kl0q~<>5;296~X59<16?:>53c`8yv46>3:1>vP=179>726=;j=0q~<>7;296~X59>16?:>53b:8yv4603:1>vP=199>726=;j30q~<>9;296~X59016?:>53bc8yv46i3:1>vP=1`9>726=;jh0q~<>b;296~X59k16?:>53ba8yv46k3:1>vP=1b9>726=;jn0q~<>d;296~X59m16?:>53bg8yv46m3:1>vP=1d9>726=;jl0q~<>f;296~X59o16?;653b28yv4583:1>vP=219>726=;ki0q~<=1;296~X5:816?:>53cf8yv45:3:1>vP=239>726=;ko0q~<=3;296~X5::16?:>53cd8yv45<3:1>vP=259>726=;j:0q~<=5;296~X5:<16?:>53b38yv45>3:1>vP=279>726=;j80q~<=7;296~X5:>16?:>53b18yv4503:1>vP=299>726=;j>0q~<=9;296~X5:016?:>53b48yv45i3:1>vP=2`9>73>=;j;0q~<=b;296~X5:k16?:?53c`8yv45k3:1>vP=2b9>727=;j=0q~<=d;296~X5:m16?:?53b:8yv45m3:1>vP=2d9>727=;j30q~<=f;296~X5:o16?:?53bc8yv4483:1>vP=319>727=;jh0q~<<1;296~X5;816?:?53ba8yv44:3:1>vP=339>727=;jn0q~<<3;296~X5;:16?:?53bg8yv44<3:1>vP=359>727=;jl0q~<<5;296~X5;<16?;653b08yv44>3:1>vP=379>727=;ki0q~<<7;296~X5;>16?:?53cf8yv4403:1>vP=399>727=;ko0q~<<9;296~X5;016?:?53cd8yv44i3:1>vP=3`9>727=;j:0q~<<b;296~X5;k16?:?53b38yv44k3:1>vP=3b9>727=;j80q~<<d;296~X5;m16?:?53b18yv44m3:1>vP=3d9>727=;j>0q~<<f;296~X5;o16?:?53b48yv4383:1>vP=419>73>=;j90q~<;1;296~X5<816?:<53c`8yv43:3:1>vP=439>724=;j=0q~<;3;296~X5<:16?:<53b:8yv43<3:1>vP=459>724=;j30q~<;5;296~X5<<16?:<53bc8yv43>3:1>vP=479>724=;jh0q~<;7;296~X5<>16?:<53ba8yv4303:1>vP=499>724=;jn0q~<;9;296~X5<016?:<53bg8yv43i3:1>vP=4`9>724=;jl0q~<;b;296~X5<k16?;653b68yv43k3:1>vP=4b9>724=;ki0q~<;d;296~X5<m16?:<53cf8yv43m3:1>vP=4d9>724=;ko0q~<;f;296~X5<o16?:<53cd8yv4283:1>vP=519>724=;j:0q~<:1;296~X5=816?:<53b38yv42:3:1>vP=539>724=;j80q~<:3;296~X5=:16?:<53b18yv42<3:1>vP=559>724=;j>0q~<:5;296~X5=<16?:<53b48yv42>3:1>vP=579>73>=;j<0q~<:7;296~X5=>16?;653b58yv4203:1>vP=599>73?=;kh0q~<:9;296~X5=016?;753b58yv42i3:1>vP=5`9>73?=;j20q~<:b;296~X5=k16?;753b;8yv42k3:1>vP=5b9>73?=;jk0q~<:d;296~X5=m16?;753b`8yv42m3:1>vP=5d9>73?=;ji0q~<:f;296~X5=o16?;753bf8yv4183:1>vP=619>73?=;jo0q~<91;296~X5>816?;753bd8yv41:3:1>vP=639>73g=;kh0q~<93;296~X5>:16?;753ca8yv41<3:1>vP=659>73?=;kn0q~<95;296~X5><16?;753cg8yv41>3:1>vP=679>73?=;kl0q~<97;296~X5>>16?;753b28yv4103:1>vP=699>73?=;j;0q~<99;296~X5>016?;753b08yv41i3:1>vP=6`9>73?=;j90q~<9b;296~X5>k16?;753b68yv41l3:1>vP=6e9>73?=;j<0q~<9e;296~X5>l16?;o53b58yv41n3:1>vP=6g9>73g=;j20q~<80;296~X5?916?;o53b;8yv4093:1>vP=709>73g=;jk0q~<82;296~X5?;16?;o53b`8yv40;3:1>vP=729>73g=;ji0q~<84;296~X5?=16?;o53bf8yv40=3:1>vP=749>73g=;jo0q~<86;296~X5??16?;o53bd8yv40?3:1>vP=769>73>=;j20q~<88;296~X5?116?;o53ca8yv4013:1>vP=789>73g=;kn0q~<8a;296~X5?h16?;o53cg8yv40j3:1>vP=7c9>73g=;kl0q~<8c;296~X5?j16?;o53b28yv40l3:1>vP=7e9>73g=;j;0q~<8e;296~X5?l16?;o53b08yv40n3:1>vP=7g9>73g=;j90q~<70;296~X50916?;o53b68yv4?93:1>vP=809>73g=;j<0q~<72;296~X50;16?;653b;8yv4?;3:1>vP=829>73d=;kh0q~<74;296~X50=16?;l53b58yv4?=3:1>vP=849>73d=;j20q~<76;296~X50?16?;l53b;8yv4??3:1>vP=869>73d=;jk0q~<78;296~X50116?;l53b`8yv4?13:1>vP=889>73d=;ji0q~<7a;296~X50h16?;l53bf8yv4?j3:1>vP=8c9>73d=;jo0q~<7c;296~X50j16?;l53bd8yv4?l3:1>vP=8e9>73>=;jk0q~<7e;296~X50l16?;l53ca8yv4?n3:1>vP=8g9>73d=;kn0q~<60;296~X51916?;l53cg8yv4>93:1>vP=909>73d=;kl0q~<62;296~X51;16?;l53b28yv4>;3:1>vP=929>73d=;j;0q~<64;296~X51=16?;l53b08yv4>=3:1>vP=949>73d=;j90q~<66;296~X51?16?;l53b68yv4>?3:1>vP=969>73d=;j<0q~<68;296~X51116?;653b`8yv4>13:1>vP=989>73e=;kh0q~<6a;296~X51h16?;m53b58yv4>j3:1>vP=9c9>73e=;j20q~<6c;296~X51j16?;m53b;8yv4>l3:1>vP=9e9>73e=;jk0q~<6e;296~X51l16?;m53b`8yv4>n3:1>vP=9g9>73e=;ji0q~<n0;296~X5i916?;m53bf8yv4f93:1>vP=a09>73e=;jo0q~<n2;296~X5i;16?;m53bd8yv4f;3:1>vP=a29>73>=;ji0q~<n4;296~X5i=16?;m53ca8yv4f=3:1>vP=a49>73e=;kn0q~<n6;296~X5i?16?;m53cg8yv4f?3:1>vP=a69>73e=;kl0q~<n8;296~X5i116?;m53b28yv4f13:1>vP=a89>73e=;j;0q~<na;296~X5ih16?;m53b08yv4fj3:1>vP=ac9>73e=;j90q~<nc;296~X5ij16?;m53b68yv4fl3:1>vP=ae9>73e=;j<0q~<ne;296~X5il16?;653bf8yv4fn3:1>vP=ag9>73b=;kh0q~<m0;296~X5j916?;j53b58yv4e93:1>vP=b09>73b=;j20q~<m2;296~X5j;16?;j53b;8yv4e;3:1>vP=b29>73b=;jk0q~<m4;296~X5j=16?;j53b`8yv4e=3:1>vP=b49>73b=;ji0q~<m6;296~X5j?16?;j53bf8yv4e?3:1>vP=b69>73b=;jo0q~<m8;296~X5j116?;j53bd8yv4e13:1>vP=b89>73>=;jo0q~<ma;296~X5jh16?;j53ca8yv4ej3:1>vP=bc9>73b=;kn0q~<mc;296~X5jj16?;j53cg8yv4el3:1>vP=be9>73b=;kl0q~<me;296~X5jl16?;j53b28yv4en3:1>vP=bg9>73b=;j;0q~<l0;296~X5k916?;j53b08yv4d93:1>vP=c09>73b=;j90q~<l2;296~X5k;16?;j53b68yv4d;3:1>vP=c29>73b=;j<0q~<l5;296~X5k<16?;653bd8yv4d>3:1>vP=c79>73?=:j<0q~=n8;29g~X4i116?;653`:8960f2:k370=9b;1b<>;4>j08m55237f97d><5:<n6>o7;<15b?5f0278;=4<a99>727=;h201>9=:2c;?851139j46s|3e294?e|V:n;70=98;1g4>;4>h08h=5237`97a6<5:<h6>j?;<15`?5c8278:h4<d19>73`=;m:01>9?:2f3?850939o<63<7380`5=:;?31?i>4}r1g5?6=krT8h<5237:97a7<5:<j6>j>;<15f?5c9278:n4<d09>73b=;m;01>8j:2f2?851n39o=63<7180`4=:;>;1?i?4=251>6b6349=57=k1:p7a4=838pR>j=;<15=?5c:2wx?i=50;0xZ6b4349=47=k3:pf<0=838p1o9i:2;1?85103;n:6s|b8594?4|5:=96?m9;<15=?7b>2wxn4650;0x960?2;i=70=9a;3f2>{tj031<7<t=24b>7e1349=n7?j6:pf<g=838p1>8m:3a5?851k3;n:6s|b8`94?4|5:<h6?m9;<15`?7b>2wxn4m50;0x960c2;i=70=9e;3f2>{tj0n1<7<t=24f>7e1349=j7?j6:pf<c=838p1>8i:3a5?85083;n:6s|b8d94?4|5:=;6?m9;<145?7b>2wxnl>50;0x96162;i=70=82;3f2>{tjk?1<7<t=251>6b5349=57=k3:pfg0=838p1>87:2f1?851i39o?6s|bc594?4|5:<j6>j=;<15f?5c;2wxno650;0x960e2:n970=9c;1g7>{tjk31<7<t=24`>6b5349=h7=k3:pfgg=838p1>8k:2f1?851m39o?6s|bc`94?4|5:<n6>j=;<15b?5c;2wxnom50;0x960a2:n970=80;1g7>{tjkn1<7<t=253>6b5349<=7=k3:pfgc=838p1>9>:2f1?850:39o?6srb82a>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk3;o7>53;294~"3;80i;n5Gb6f8Lg2f3`k=6=44i255>5<<g:3:6=44}c;26?6=;3:1<v*;30803g=Oj>n0Do:n;%0f4?5d3`8hm7>5;h0`f?6=3f92=7>5;|`:4=<72:0;6=u+423972d<@k=o7El;a:&1a5<4k2c9ol4?::k1gg<722e85<4?::a=51=8391<7>t$512>61e3Ah<h6Fm4`9'6`6=;j1b>no50;9j6fd=831d?4?50;9~f<6229026=4?{%605?5e12Bi;i5Gb5c8 7c72;1b8=4?::k75?6=3`>96=44i5194?=ni=0;66gn7;29?lb12900c>78:188k6??2900qo7?4;29=?6=8r.??<4<b89Kf2b<@k>j7)<j0;08m16=831b8<4?::k76?6=3`>86=44i`694?=ni>0;66gk6;29?j5>?3:17b=68;29?xd>8?0;644?:1y'067=;k30Do9k;I`7e>"5m9097d:?:188m17=831b8?4?::k77?6=3`k?6=44i`594?=nl?0;66a<9683>>i4110;66sm91c94?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn4?<:187>5<7s->8=7?k9:Ja3a=Oj=k0(?k?:09j==<722co:7>5;h1:e?6=3f92;7>5;|`:51<7210964uGb5c8 1562k237W78:0y2f?{#j=h18>>4i0g;>5<#;0?1=h94n2;7>5=<ahi1<75f3`:94?=n;m;1<75f3e294?=n;m81<75`3e194?=h:j<1<75mb6d94?7=83:p(9=>:c77?Md0l2Bi8l5`38094?=zj:<<6=4>c;`962}Oj=k0(9=>:c:g?_?028q:i7s+2b:9=43<a:i=6=4+38797f3<f:3?6=54i2a7>5<#;0?1?n;4n2;7>4=<a:i86=4+38797f3<f:3?6?54i2a1>5<#;0?1?n;4n2;7>6=<a:i:6=4+38797f3<f:3?6954i2a3>5<#;0?1?n;4n2;7>0=<a:hm6=4+38797f3<f:3?6;54i2`f>5<#;0?1?n;4n2;7>2=<a:ho6=4+38797f3<f:3?6554i2``>5<#;0?1?n;4n2;7><=<a:im6=4+38797f3<f:3?6l54i2af>5<#;0?1?n;4n2;7>g=<a:io6=4+38797f3<f:3?6n54i2a`>5<#;0?1?n;4n2;7>a=<a:ii6=4+38797f3<f:3?6h54i2ab>5<#;0?1?n;4n2;7>c=<a:i26=4+38797f3<f:3?6<>4;h1`<?6=,:3>6>m:;o1:0?7632c8o:4?:%1:1?5d=2d8594>2:9j7gd=83.8584<c49m7<2=9:10elm50;9j7d>=831b=h850;9j7a7=831b?i>50;9j7a4=831d?i=50;9l6f0=831in:h50;394?6|,=9:6o;;;I`4`>Ne<h1d?4<50;9~fg1b290:6=4?{%605?4d?2Bi;i5Gb5c8k4c22900qol;c;290?6=8r.??<4<819Kf2b<@k>j7)=n9;`5b>of>3:17dj8:188m6d72900c>98:188ygd2;3:1m7>50z&774<4jh1Cn:j4Hc6b?_?028q8;7s+3`;9f3`<,;o;695fa683>>oc>3:17do;:188k6?02900c>76:188m1?=83.8584;8:l0=1<732c?;7>5$2;6>1><f:3?6<54i5494?"41<0?46`<9581?>o3=3:1(>7::5:8j6?32:10e9:50;&0=0<302d8594;;:af04=83k1<7>t$512>6df3Ah<h6Fm4`9Y=2<6s:=1q)=n9;`5b>"5m90?7do8:188ma0=831bm94?::m0=2<722e8544?::k7=?6=,:3>6964n2;7>5=<a==1<7*<9487<>h41=0:76g;6;29 6?22=20b>7;:398m13=83.8584;8:l0=1<432c?87>5$2;6>1><f:3?6954}c`65?6=i3:1<v*;3080fd=Oj>n0Do:n;[;4>4}4?3w/?l75b7d8 7c72=1bm:4?::kg2?6=3`k?6=44o2;4>5<<g:326=44i5;94?"41<0?46`<9583?>o3?3:1(>7::5:8j6?32810e9850;&0=0<302d8594=;:k71?6=,:3>6964n2;7>6=<a=>1<7*<9487<>h41=0?76smb4294?g=83:p(9=>:2`b?Md0l2Bi8l5U968261=u-9j57l9f:&1a5<33`k<6=44ie494?=ni=0;66a<9683>>i4100;66g;9;29 6?22=20b>7;:198m11=83.8584;8:l0=1<632c?:7>5$2;6>1><f:3?6?54i5794?"41<0?46`<9580?>o3<3:1(>7::5:8j6?32=10qol;d;290?6=8r.??<4<819Kf2b<@k>j7)=n9;`5b>of>3:17dj8:188m6d72900c>98:188ygd3n3:187>50z&774<4091Cn:j4Hc6b?!5f13h=j6gn6;29?lb02900e>l?:188k6102900qol;e;290?6=8r.??<4<819Kf2b<@k>j7)=n9;`5b>of>3:17dj8:188m6d72900c>98:188yg51>3:187>50z&774<4091Cn:j4Hc6b?!5f13h<<6gn6;29?lb02900e>l?:188k6102900q~?j6;296~X6m?16n9m5a79~w7e12909wS<l6:?023<4?>1v>6::1818d0n392>63<6780f5=z{:2=6=49{<`4a?7b=27i8n4k7:?a0a<c?27i8k4k7:?a0`<c?278:;4k7:p7gd=838pR>lm;<`64?233ty8nn4?:3y]7ge<5k?969:4}r1a`?6=:rT8ni52b40900=z{:hn6=4={_1aa>;e=;0?:6s|3cd94?4|V:hm70l:2;64?xu4k90;6?uQ3b289g352=30q~=l1;296~X4k816n8=5459~w6e52909wS=l2:?a16<3=2wx?n=50;0xZ6e434h>?7:9;|q0g1<72;qU?n:4=c70>11<uz9h:7>52z\0g3=:j<91845rs2a4>5<5sW9h;63m51871>{t;j21<7<t^2a;?8d283>=7p}<c883>7}Y;j301o;?:558yv5di3:1>vP<c`9>f06=<01v>mm:181[5dj27i9<4;4:p7fe=838pR>ml;<`65?223ty8oi4?:3y]7fb<5k?:6984}r1`a?6=:rT8oh52b43902=z{:im6=4={_1`b>;e=80?56s|3e294?3|V:n;70l:3;c7?8d2:3k?70l:1;c7?8d283k?7p}<d083>0}Y;m;01o;<:`589g352h=01o;>:`589g372h=0q~=k2;296~X4l;16n8=5d79~w6b42909wS=k3:?a15<4101voo7:1818d29392563m518g2>{tjh31<7<t=c71>6?>34h>=7j9;|qaed<72;q6n8=538;89g352m<0q~lnb;296~;e<j08;:52b5f9e3=z{kkh6=4={<`7`?50?27i8h4n6:pfdb=838p1o:i:`489g2b2:=<7p}mad83>7}:j=l1?:94=245>d0<uzhi<7>52z?a0f<4j916n8>53858yvde93:1>v3m5080=2=:j=n1?o>4}r`a6?6=:r7i9?4<969>f1c=;k:0q~lm3;296~;e=:085:52b5d97g6<utyjo7>52z\bg>;4>>0jo6s|1d:94?4|V8o370=97;1af>{t:j<1<7<t^3a5?851?38h:6s|3`:94?4|V:k370=97;1b<>{t;m:1<7<t^2f3?851?39o<6s|3e394?4|V:n:70=97;1g5>{t;m81<7<t^2f1?851?39o>6s|3e194?4|V:n870=97;1g7>{tj0<1<7?:{<`4b?5>:278::4<c79>731=;j>01>88:2a0?851?39h>63<6680g4=:;?=1?n>4=244>6da349=;7=me:?022<4jm16?;953ca896002:im70=97;1`a>;4>>08oi5237597fe<5:<<6>mm;<153?5di278::4<c89>731=;j201>88:2a4?851?3;n:6srb97a>5<4290;w):<1;14f>Ne?m1Cn9o4$3g3>4e<a;ij6=44i3aa>5<<g:3:6=44}c:05?6==3:1<v*;30803a=Oj>n0Do:n;%0f4?d<a;ij6=44i3aa>5<<a;ih6=44i3ag>5<<g:3:6=44}c:07?6==3:1<v*;30803a=Oj>n0Do:n;%0f4??23`8hm7>5;h0`f?6=3`8ho7>5;h0``?6=3f92=7>5;|`;71<72<0;6=u+423972b<@k=o7El;a:&1a5<6n2c9ol4?::k1gg<722c9on4?::k1ga<722e85<4?::a<63=83?1<7>t$512>61c3Ah<h6Fm4`9'6`6=:o1b>no50;9j6fd=831b>nm50;9j6fb=831d?4?50;9~f=51290>6=4?{%605?50l2Bi;i5Gb5c8 7c728in7d<la;29?l4dj3:17d<lc;29?l4dl3:17b=61;29?xd?;>0;684?:1y'067=;>n0Do9k;I`7e>"5m90j7d<la;29?l4dj3:17d<lc;29?l4dl3:17b=61;29?xd?;10;684?:1y'067=;>n0Do9k;I`7e>"5m9097d<la;29?l4dj3:17d<lc;29?l4dl3:17b=61;29?xd?;00;684?:1y'067=;>n0Do9k;I`7e>"5m9027d<la;29?l4dj3:17d<lc;29?l4dl3:17b=61;29?xd?;h0;684?:1y'067=;>n0Do9k;I`7e>"5m90:hh5f2bc94?=n:jh1<75f2ba94?=n:jn1<75`38394?=zj19i6=4::183!24939<h6Fm7e9Kf1g<,;o;6?64i3ab>5<<a;ii6=44i3a`>5<<a;io6=44o2;2>5<<uk28>7>55;294~"3;808;i5Gb6f8Lg2f3-8n<7j4i3ab>5<<a;ii6=44i3a`>5<<a;io6=44o2;2>5<<uk2287>52;294~"3;808:95Gb6f8Lg2f3`8h57>5;n1:5?6=3th3:l4?:283>5}#<:;1?:l4Hc5g?Md3i2.9i=4>c:k1gd<722c9oo4?::m0=4<722wi48o50;194?6|,=9:6>9m;I`4`>Ne<h1/>h>52d9j6fg=831b>nl50;9l7<7=831vn57<:180>5<7s->8=7=8b:Ja3a=Oj=k0(?k?:0a0?l4di3:17d<lb;29?j5>93:17pl78b83>0<729q/8>?536f8Lg1c3Ah?m6*=e18e?l4di3:17d<lb;29?l4dk3:17d<ld;29?j5>93:17pl78d83>1<729q/8>?51e78Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722e85:4?::a<=`=83>1<7>t$512>4b23Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75`38594?=zj12o6=4;:183!2493;o56Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17d=6a;29?j5>?3:17pl76083>0<729q/8>?51e68Lg1c3Ah?m6*=e182?l??2900el:50;9jea<722co:7>5;n1:3?6=3th39i4?:483>5}#<:;1=i:4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fae83>>oc>3:17b=67;29?xd?=l0;684?:1y'067=9m>0Do9k;I`7e>"5m90:7d77:188md2=831bmi4?::kg2?6=3f92;7>5;|`;1f<72=0;6=u+42395a?<@k=o7El;a:&1a5<63`336=44ie494?=n;0k1<75`38594?=zj1<;6=4::183!2493;o86Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dok:188ma0=831d?4950;9~f=3a290?6=4?{%605?7c=2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44o2;4>5<<uk2on7>54;294~"3;80:h85Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?j5>?3:17pl75983>0<729q/8>?51e:8Lg1c3Ah?m6*=e1824>o>03:17do;:188ma0=831b?4850;9l7<1=831vn5;6:187>5<7s->8=7=85:Ja3a=Oj=k0(?k?:09jea<722co:7>5;h3f1?6=3f92;7>5;|`;12<72<0;6=u+42395a2<@k=o7El;a:&1a5<63`336=44i`694?=nim0;66gk6;29?j5>?3:17pl79383>0<729q/8>?51e68Lg1c3Ah?m6*=e182?l??2900el:50;9jea<722co:7>5;n1:3?6=3th3584?:483>5}#<:;1=io4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fd783>>o41h0;66a<9683>>{e00<1<7;50;2x 15628nj7El8d:Ja0d=#:l:1=6g68;29?lg32900ei850;9j7<g=831d?4950;9~f=5d290>6=4?{%605?7ci2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44i2;b>5<<g:3<6=44}c:0`?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl73d83>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi4>h50;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj1>;6=4::183!2493;om6Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188m6?f2900c>78:188yg>393:197>50z&774<6lh1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;h1:e?6=3f92;7>5;|`;07<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm85194?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn5:;:186>5<7s->8=7?ka:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<a:3j6=44o2;4>5<<uk2?97>55;294~"3;80:hl5Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?l5>i3:17b=67;29?xd?=?0;694?:1y'067=9m?0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::m0=2<722wi4;750;694?6|,=9:6<j:;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=h;0=1<75rb94;>5<3290;w):<1;3g1>Ne?m1Cn9o4$3g3>4=n110;66gn4;29?lb12900c>78:188yg>fl3:1?7>50z&774<e?j1Cn:j4Hc6b?lg12900e>99:188k6?62900qo6na;290?6=8r.??<4<819Kf2b<@k>j7do9:188ma1=831b?o>50;9l721=831vn5l>:180>5<7s->8=7l8c:Ja3a=Oj=k0el850;9j720=831d?4?50;9~f=gb290?6=4?{%605?5?82Bi;i5Gb5c8md0=831bh:4?::k0f5<722e8;:4?::a<g3=8391<7>t$512>g1d3Ah<h6Fm4`9je3<722c8;;4?::m0=4<722wi4o<50;694?6|,=9:6>6?;I`4`>Ne<h1bm;4?::kg3?6=3`9i<7>5;n143?6=3th3n44?:283>5}#<:;1n:m4Hc5g?Md3i2cj:7>5;h142?6=3f92=7>5;|`;f3<72=0;6=u+42397=6<@k=o7El;a:kb2?6=3`n<6=44i2`3>5<<g:=<6=44}c:a`?6=;3:1<v*;308a3f=Oj>n0Do:n;hc5>5<<a:==6=44o2;2>5<<uk2im7>54;294~"3;8084=5Gb6f8Lg2f3`k=6=44ie594?=n;k:1<75`36594?=zj1i:6=4<:183!2493h<o6Fm7e9Kf1g<ah<1<75f36494?=h;0;1<75rb9`f>5<3290;w):<1;1;4>Ne?m1Cn9o4i`494?=nl>0;66g<b183>>i4?>0;66sm8b794?5=83:p(9=>:c5`?Md0l2Bi8l5fa783>>o4??0;66a<9083>>{e0j81<7:50;2x 1562:2;7El8d:Ja0d=ni?0;66gk7;29?l5e83:17b=87;29?xd?k00;6>4?:1y'067=j>i0Do9k;I`7e>of>3:17d=86;29?j5>93:17pl7c783>1<729q/8>?53928Lg1c3Ah?m6gn6;29?lb02900e>l?:188k6102900qo6ld;297?6=8r.??<4m7b9Kf2b<@k>j7do9:188m6112900c>7>:188yg>di3:187>50z&774<4091Cn:j4Hc6b?lg12900ei950;9j7g6=831d?:950;9~f=b729086=4?{%605?d0k2Bi;i5Gb5c8md0=831b?:850;9l7<7=831vn5ol:181>5<7s->8=7=8a:Ja3a=Oj=k0(?k?:0a8m7ef2900c>7>:188yg>e83:1>7>50z&774<4?h1Cn:j4Hc6b?!4b83;h7d<la;29?j5>93:17pl7b583>7<729q/8>?536c8Lg1c3Ah?m6*=e182g>o5kh0;66a<9083>>{e0k21<7<50;2x 1562:=j7El8d:Ja0d=#:l:1=n5f2bc94?=h;0;1<75rb9``>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk2h<7>52;294~"3;808;l5Gb6f8Lg2f3-8n<7?l;h0`e?6=3f92=7>5;|`;g1<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi4n650;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f=ed29096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo6lf;296?6=8r.??<4<7`9Kf2b<@k>j7)<j0;3`?l4di3:17b=61;29?xd?ik0;684?:1y'067=9mk0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::k0=d<722e85:4?::a<d`=83?1<7>t$512>4bf3Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75f38c94?=h;0=1<75rb9`0>5<2290;w):<1;3ge>Ne?m1Cn9o4$3g3>4=n110;66gn4;29?lb12900e>7n:188k6?02900qo6m7;291?6=8r.??<4>d`9Kf2b<@k>j7)<j0;38m<>=831bm94?::kg2?6=3`92m7>5;n1:3?6=3th3no4?:483>5}#<:;1=io4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fd783>>o41h0;66a<9683>>{e0kl1<7;50;2x 15628nj7El8d:Ja0d=#:l:1=6g68;29?lg32900ei850;9j7<g=831d?4950;9~f=e4290>6=4?{%605?7ci2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44i2;b>5<<g:3<6=44}c:`3?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl7cc83>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi4nk50;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj18?6=4<:183!24939<n6Fm7e9Kf1g<,;o;6?k4i3ab>5<<a;ii6=44o2;2>5<<uk29?7>54;294~"3;808;n5Gb6f8Lg2f3-8n<7?l7:k1gd<722c9oo4?::k1gf<722e85<4?::a<74=83?1<7>t$512>61c3Ah<h6Fm4`9'6`6=9l:0e?mn:188m7ee2900e?ml:188m7ec2900c>7>:188yg1ai3:187>50z&774<6lk1Cn:j4Hc6b?!4b83;;7d77:188ma0=831b?o>50;9l7<1=831vn:h6:187>5<7s->8=7?kb:Ja3a=Oj=k0(?k?:028m<>=831bh;4?::k0f5<722e85:4?::a3c>=83>1<7>t$512>4be3Ah<h6Fm4`9'6`6=991b554?::kg2?6=3`9i<7>5;n1:3?6=3th<j:4?:583>5}#<:;1=il4Hc5g?Md3i2.9i=4>0:k:<?6=3`n=6=44i2`3>5<<g:3<6=44}c5e2?6=<3:1<v*;3082`g=Oj>n0Do:n;%0f4?773`336=44ie494?=n;k:1<75`38594?=zj>l>6=4;:183!2493;on6Fm7e9Kf1g<,;o;6<>4i8:94?=nl?0;66g<b183>>i41>0;66sm7g694?2=83:p(9=>:0fa?Md0l2Bi8l5+2d2955=n110;66gk6;29?l5e83:17b=67;29?xd0n:0;694?:1y'067=9mh0Do9k;I`7e>"5m90:<6g68;29?lb12900e>l?:188k6?02900qo6=1;290?6=8r.??<4>d69Kf2b<@k>j7)<j0;33?l??2900ei850;9j7<0=831d?4950;9~f=7529086=4?{%605?50j2Bi;i5Gb5c8 7c728i0e?mn:188m7ee2900c>7>:188yg>6?3:187>50z&774<6l<1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;n1:3?6=3th3=;4?:583>5}#<:;1=i;4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fd783>>i41>0;66sm80:94?3=83:p(9=>:0f7?Md0l2Bi8l5+2d295>o>03:17do;:188mdb=831bh;4?::m0=2<722wi4<=50;694?6|,=9:6<j6;I`4`>Ne<h1/>h>51:k:<?6=3`n=6=44i2;b>5<<g:3<6=44}c:21?6==3:1<v*;3082`1=Oj>n0Do:n;%0f4?7<a021<75fa583>>ofl3:17dj9:188k6?02900qo6>4;291?6=8r.??<4>d59Kf2b<@k>j7)<j0;38m<>=831bm94?::kb`?6=3`n=6=44o2;4>5<<uk2:57>55;294~"3;80:h95Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gnd;29?lb12900c>78:188yg1an3:1?7>50z&774<4?k1Cn:j4Hc6b?!4b83;h7d<la;29?l4dj3:17b=61;29?xd?8?0;694?:1y'067=9m?0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::m0=2<722wi4=;50;694?6|,=9:6<j:;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=h;0=1<75rb927>5<3290;w):<1;3g1>Ne?m1Cn9o4$3g3>4=n110;66gn4;29?lb12900c>78:188yg>7;3:187>50z&774<6l<1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;n1:3?6=3th3<:4?:483>5}#<:;1=i:4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fae83>>oc>3:17b=67;29?xd?890;694?:1y'067=9m30Do9k;I`7e>"5m90:7d77:188ma0=831b?4o50;9l7<1=831vn5>=:186>5<7s->8=7?k4:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hcg>5<<am<1<75`38594?=zj1::6=4::183!2493;o86Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dok:188ma0=831d?4950;9~f=6?290>6=4?{%605?7c<2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`ko6=44ie494?=h;0=1<75rb7f0>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.9i=4;;hc4>5<<am<1<75fa583>>i41>0;66a<9883>>o313:1(>7::5:8j6?32910e9950;&0=0<302d8594>;:k72?6=,:3>6964n2;7>7=<a=?1<7*<9487<>h41=0876g;4;29 6?22=20b>7;:598yg0ck3:1m7>50z&774<4jh1Cn:j4Hc6b?_?028q8;7s+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3th=ho4?:`83>5}#<:;1?oo4Hc5g?Md3i2P2;7?t368~ 7c72=1bm:4?::kg2?6=3`k?6=44o2;4>5<<g:326=44i5;94?"41<0?46`<9583?>o3?3:1(>7::5:8j6?32810e9850;&0=0<302d8594=;:k71?6=,:3>6964n2;7>6=<a=>1<7*<9487<>h41=0?76sm6`194?g=83:p(9=>:2`b?Md0l2Bi8l5U968261=u-8h479je:&0e<<e>o1/>h>54:kb3?6=3`n=6=44i`694?=h;0=1<75`38;94?=n<00;6)=65;6;?k5><3:07d:8:18'7<3=<11e?4:51:9j03<72-9297:7;o1:0?4<3`>>6=4+38790==i;0>1?65f4583>!5>=3>37c=64;68?xd1i;0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$3a;>2cb3-9j57l9f:&1a5<33`k<6=44ie494?=ni=0;66a<9683>>i4100;66g;9;29 6?22=20b>7;:198m11=83.8584;8:l0=1<632c?:7>5$2;6>1><f:3?6?54i5794?"41<0?46`<9580?>o3<3:1(>7::5:8j6?32=10qo8n1;290?6=8r.??<4<809Kf2b<@k>j7)<l8;5fa>"4i00i:k5f2bc94?=n:jh1<75f3c294?=h;0;1<75rb7f5>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.9o548f39'7d?=j?l0(?k?:59je2<722co:7>5;hc7>5<<g:3<6=44o2;:>5<<a=31<7*<9487<>h41=0;76g;7;29 6?22=20b>7;:098m10=83.8584;8:l0=1<532c?97>5$2;6>1><f:3?6>54i5694?"41<0?46`<9587?>{e>m?1<7o50;2x 1562:hj7El8d:Ja0d=]1>0:w>95}%0`<?1a:2.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07pl9d583>1<729q/8>?53938Lg1c3Ah?m6*=c984b7=#;h31n;h4i3ab>5<<a;ii6=44i2`3>5<<g:3:6=44}c4be?6=i3:1<v*;3080fd=Oj>n0Do:n;[;4>4}4?3w/>n657dd8 6g>2k<m7)<j0;68md1=831bh;4?::kb0?6=3f92;7>5;n1:=?6=3`>26=4+38790==i;0>1<65f4683>!5>=3>37c=64;38?l21290/?4;5499m7<2=:21b884?:%1:1?2?3g9287=4;h67>5<#;0?1855a38690>=zj?k26=4n:183!24939im6Fm7e9Kf1g<R0=1=v=8:|&1g=<0mo1/?l75b7d8 7c72=1bm:4?::kg2?6=3`k?6=44o2;4>5<<g:326=44i5;94?"41<0?46`<9583?>o3?3:1(>7::5:8j6?32810e9850;&0=0<302d8594=;:k71?6=,:3>6964n2;7>6=<a=>1<7*<9487<>h41=0?76sm6`:94?2=83:p(9=>:2:2?Md0l2Bi8l5+2b:93``<,:k26o8i;h0`e?6=3`8hn7>5;h1a4?6=3f92=7>5;|`5g2<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(?m7:6d2?!5f13h=j6*=e187?lg02900ei850;9je1<722e85:4?::m0=<<722c?57>5$2;6>1><f:3?6=54i5594?"41<0?46`<9582?>o3>3:1(>7::5:8j6?32;10e9;50;&0=0<302d8594<;:k70?6=,:3>6964n2;7>1=<uk<h:7>5a;294~"3;808nl5Gb6f8Lg2f3S3<6<u<7;'6f>=?o;0(>o6:c4e?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rb7a6>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.9o548f09'7d?=j?l0(?k?:59je2<722co:7>5;hc7>5<<g:3<6=44o2;:>5<<a=31<7*<9487<>h41=0;76g;7;29 6?22=20b>7;:098m10=83.8584;8:l0=1<532c?97>5$2;6>1><f:3?6>54i5694?"41<0?46`<9587?>{e>j>1<7o50;2x 1562:hj7El8d:Ja0d=]1>0:w>95}%0`<?1a92.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07pl9c083>1<729q/8>?53938Lg1c3Ah?m6*=c984b4=#;h31n;h4i3ab>5<<a;ii6=44i2`3>5<<g:3:6=44}c4`6?6=<3:1<v*;3080<4=Oj>n0Do:n;%0`<?1a92.8m44m6g9j6fg=831b>nl50;9j7g6=831d?4?50;9~f3e4290?6=4?{%605?5?:2Bi;i5Gb5c8 7e?2>l:7)=n9;`5b>o5kh0;66g=cc83>>o4j90;66a<9083>>{e>k?1<7o50;2x 1562:hj7El8d:Ja0d=]1>0:w>95}%0`<?1a82.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07pl9b583>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,;i36:h?;%1b=?d1n2.9i=4;;hc4>5<<am<1<75fa583>>i41>0;66a<9883>>o313:1(>7::5:8j6?32910e9950;&0=0<302d8594>;:k72?6=,:3>6964n2;7>7=<a=?1<7*<9487<>h41=0876g;4;29 6?22=20b>7;:598yg0e;3:1m7>50z&774<4jh1Cn:j4Hc6b?_?028q8;7s+2b:93c6<,:k26o8i;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vn;l=:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"5k10<j=5+3`;9f3`<,;o;695fa683>>oc>3:17do;:188k6?02900c>76:188m1?=83.8584;8:l0=1<732c?;7>5$2;6>1><f:3?6<54i5494?"41<0?46`<9581?>o3=3:1(>7::5:8j6?32:10e9:50;&0=0<302d8594;;:a2d`=83>1<7>t$512>6>63Ah<h6Fm4`9'6f>=?o:0(>o6:c4e?l4di3:17d<lb;29?l5e83:17b=61;29?xd1j90;694?:1y'067=;1;0Do9k;I`7e>"5k10<j=5+3`;9f3`<a;ij6=44i3aa>5<<a:h;6=44o2;2>5<<uk<i=7>54;294~"3;8084?5Gb6f8Lg2f3-8h479i0:&0e<<e>o1b>no50;9j6fd=831b?o>50;9l7<7=831vn;jn:18:>5<7s->8=7=m9:Ja3a=Oj=k0(?k?:39j05<722c?=7>5;h61>5<<a=91<75fa583>>of?3:17dj9:188k6?02900c>77:188yg0c:3:157>50z&774<4j01Cn:j4Hc6b?!4b8380e9>50;9j04<722c?>7>5;h60>5<<ah>1<75fa683>>oc>3:17b=67;29?j5>03:17pl8d483>1<729q/8>?536a8Lg1c3Ah?m6*=e182`>o5kh0;66g=cc83>>o5kj0;66a<9083>>{e>h:1<7:50;2x 15628n27El8d:Ja0d=#:j21;hk4$2c:>g173-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66sm6b294?2=83:p(9=>:0f:?Md0l2Bi8l5+2b:93c7<,:k26o9?;%0f4?7<a021<75fd783>>o41h0;66a<9683>>{e>ho1<7:50;2x 15628n27El8d:Ja0d=#:j21;k>4$2c:>g173-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66sm7e594?2=83:p(9=>:0f:?Md0l2Bi8l5+2d295>o>03:17dj9:188m6?f2900c>78:188yg1c>3:187>50z&774<6l01Cn:j4Hc6b?!4b83;0e4650;9j`3<722c85l4?::m0=2<722wi:4h50;694?6|,=9:6<j6;I`4`>Ne<h1/>h>51:k:<?6=3`n=6=44i2;b>5<<g:3<6=44}c4:a?6=<3:1<v*;3082`<=Oj>n0Do:n;%0f4?7<a021<75fd783>>o41h0;66a<9683>>{e?m>1<7;50;2x 15628nj7El8d:Ja0d=#:l:1=6g68;29?lg32900ei850;9j7<g=831d?4950;9~f2b>290>6=4?{%605?7ci2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44i2;b>5<<g:3<6=44}c5g<?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl85383>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi;9h50;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj>>i6=4::183!2493;om6Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188m6?f2900c>78:188yg13?3:197>50z&774<6lh1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;h1:e?6=3f92;7>5;|`406<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm72d94?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn:=m:186>5<7s->8=7?ka:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<a:3j6=44o2;4>5<<uk=8;7>55;294~"3;80:hl5Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?l5>i3:17b=67;29?xd0;:0;684?:1y'067=9mk0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::k0=d<722e85:4?::a37`=83?1<7>t$512>4bf3Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75f38c94?=h;0=1<75rb670>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk=><7>52;294~"3;808;l5Gb6f8Lg2f3-8n<7?l;h0`e?6=3f92=7>5;|`40f<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi;9650;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f22329096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo9;0;296?6=8r.??<4<7`9Kf2b<@k>j7)<j0;3`?l4di3:17b=61;29?xd0;j0;6?4?:1y'067=;>k0Do9k;I`7e>"5m90:o6g=c`83>>i4180;66sm72:94?4=83:p(9=>:25b?Md0l2Bi8l5+2d295f=n:jk1<75`38394?=zj>9?6=4=:183!24939<m6Fm7e9Kf1g<,;o;6<m4i3ab>5<<g:3:6=44}c504?6=:3:1<v*;30803d=Oj>n0Do:n;%0f4?7d3`8hm7>5;n1:5?6=3th<994?:283>5}#<:;1n:m4Hc5g?Md3i2cj:7>5;h142?6=3f92=7>5;|`40`<72=0;6=u+42397=6<@k=o7El;a:kb2?6=3`n<6=44i2`3>5<<g:=<6=44}c565?6=;3:1<v*;308a3f=Oj>n0Do:n;hc5>5<<a:==6=44o2;2>5<<uk=?m7>54;294~"3;8084=5Gb6f8Lg2f3`k=6=44ie594?=n;k:1<75`36594?=zj>>o6=4<:183!2493h<o6Fm7e9Kf1g<ah<1<75f36494?=h;0;1<75rb665>5<3290;w):<1;1;4>Ne?m1Cn9o4i`494?=nl>0;66g<b183>>i4?>0;66sm75;94?5=83:p(9=>:c5`?Md0l2Bi8l5fa783>>o4??0;66a<9083>>{e?=81<7:50;2x 1562:2;7El8d:Ja0d=ni?0;66gk7;29?l5e83:17b=87;29?xd0<<0;6>4?:1y'067=j>i0Do9k;I`7e>of>3:17d=86;29?j5>93:17pl83d83>1<729q/8>?53928Lg1c3Ah?m6gn6;29?lb02900e>l?:188k6102900qo9;1;297?6=8r.??<4m7b9Kf2b<@k>j7do9:188m6112900c>7>:188yg14i3:187>50z&774<4091Cn:j4Hc6b?lg12900ei950;9j7g6=831d?:950;9~f25c29086=4?{%605?d0k2Bi;i5Gb5c8md0=831b?:850;9l7<7=831vn:=9:187>5<7s->8=7=70:Ja3a=Oj=k0el850;9j`2<722c8n=4?::m032<722wi;>750;194?6|,=9:6o9l;I`4`>Ne<h1bm;4?::k033<722e85<4?::a364=83>1<7>t$512>6>73Ah<h6Fm4`9je3<722co;7>5;h1a4?6=3f9<;7>5;|`470<72:0;6=u+4239f2e<@k=o7El;a:kb2?6=3`9<:7>5;n1:5?6=3th<>h4?:583>5}#<:;1?5>4Hc5g?Md3i2cj:7>5;hf4>5<<a:h;6=44o254>5<<uk=8=7>53;294~"3;80i;n5Gb6f8Lg2f3`k=6=44i255>5<<g:3:6=44}c5:2?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl89283>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi;5h50;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj>2i6=4::183!2493;om6Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188m6?f2900c>78:188yg1??3:197>50z&774<6lh1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;h1:e?6=3f92;7>5;|`4<6<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm76d94?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn:9m:186>5<7s->8=7?ka:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<a:3j6=44o2;4>5<<uk=<;7>55;294~"3;80:hl5Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?l5>i3:17b=67;29?xd0?:0;684?:1y'067=9mk0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::k0=d<722e85:4?::a3<1=8381<7>t$512>61f3Ah<h6Fm4`9'6`6=9j1b>no50;9l7<7=831vn:7;:181>5<7s->8=7=8a:Ja3a=Oj=k0(?k?:0a8m7ef2900c>7>:188yg1>83:1>7>50z&774<4?h1Cn:j4Hc6b?!4b83;h7d<la;29?j5>93:17pl88b83>7<729q/8>?536c8Lg1c3Ah?m6*=e182g>o5kh0;66a<9083>>{e?121<7<50;2x 1562:=j7El8d:Ja0d=#:l:1=n5f2bc94?=h;0;1<75rb6:7>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk=3<7>52;294~"3;808;l5Gb6f8Lg2f3-8n<7?l;h0`e?6=3f92=7>5;|`43f<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi;:650;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f21329096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo968;297?6=8r.??<4m7b9Kf2b<@k>j7do9:188m6112900c>7>:188yg1>:3:187>50z&774<4091Cn:j4Hc6b?lg12900ei950;9j7g6=831d?:950;9~f2?229086=4?{%605?d0k2Bi;i5Gb5c8md0=831b?:850;9l7<7=831vn:6j:187>5<7s->8=7=70:Ja3a=Oj=k0el850;9j`2<722c8n=4?::m032<722wi;4?50;194?6|,=9:6o9l;I`4`>Ne<h1bm;4?::k033<722e85<4?::a3=g=83>1<7>t$512>6>73Ah<h6Fm4`9je3<722co;7>5;h1a4?6=3f9<;7>5;|`4<a<72:0;6=u+4239f2e<@k=o7El;a:kb2?6=3`9<:7>5;n1:5?6=3th<4;4?:583>5}#<:;1?5>4Hc5g?Md3i2cj:7>5;hf4>5<<a:h;6=44o254>5<<uk=357>53;294~"3;80i;n5Gb6f8Lg2f3`k=6=44i255>5<<g:3:6=44}c5;6?6=<3:1<v*;3080<5=Oj>n0Do:n;hc5>5<<am=1<75f3c294?=h;>=1<75rb6:6>5<4290;w):<1;`4g>Ne?m1Cn9o4i`494?=n;><1<75`38394?=zj>=n6=4;:183!249393<6Fm7e9Kf1g<ah<1<75fd683>>o4j90;66a<7683>>{e?1;1<7=50;2x 1562k=h7El8d:Ja0d=ni?0;66g<7783>>i4180;66sm76c94?2=83:p(9=>:2:3?Md0l2Bi8l5fa783>>oc?3:17d=m0;29?j50?3:17pl87e83>6<729q/8>?5b6a8Lg1c3Ah?m6gn6;29?l50>3:17b=61;29?xd0??0;694?:1y'067=;1:0Do9k;I`7e>of>3:17dj8:188m6d72900c>98:188yg1013:1?7>50z&774<e?j1Cn:j4Hc6b?lg12900e>99:188k6?62900qo982;290?6=8r.??<4<819Kf2b<@k>j7do9:188ma1=831b?o>50;9l721=831vn:9::180>5<7s->8=7l8c:Ja3a=Oj=k0el850;9j720=831d?4?50;9~f27>290?6=4?{%605?50k2Bi;i5Gb5c8 7c720k0e?mn:188m7ee2900e?ml:188k6?62900qo9>6;290?6=8r.??<4<7b9Kf2b<@k>j7)<j0;;b?l4di3:17d<lb;29?l4dk3:17b=61;29?xd09:0;694?:1y'067=;>i0Do9k;I`7e>"5m902m6g=c`83>>o5kk0;66g=cb83>>i4180;66sm70294?2=83:p(9=>:25`?Md0l2Bi8l5+2d29=d=n:jk1<75f2b`94?=n:ji1<75`38394?=zj>:o6=4;:183!24939<o6Fm7e9Kf1g<,;o;64o4i3ab>5<<a;ii6=44i3a`>5<<g:3:6=44}c53e?6=<3:1<v*;30803f=Oj>n0Do:n;%0f4??f3`8hm7>5;h0`f?6=3`8ho7>5;n1:5?6=3th<<:4?:583>5}#<:;1?:m4Hc5g?Md3i2.9i=46a:k1gd<722c9oo4?::k1gf<722e85<4?::a352=83>1<7>t$512>61d3Ah<h6Fm4`9'6`6=1h1b>no50;9j6fd=831b>nm50;9l7<7=831vn:>>:187>5<7s->8=7=8c:Ja3a=Oj=k0(?k?:8c8m7ef2900e?mm:188m7ed2900c>7>:188yg0am3:187>50z&774<4?j1Cn:j4Hc6b?!4b833j7d<la;29?l4dj3:17d<lc;29?j5>93:17pl8a583>6<729q/8>?536`8Lg1c3Ah?m6*=e180g>o5kh0;66g=cc83>>i4180;66sm7`194?5=83:p(9=>:25a?Md0l2Bi8l5+2d297f=n:jk1<75f2b`94?=h;0;1<75rb7d`>5<?290;w):<1;1a<>Ne?m1Cn9o4$3g3>7=n<90;66g;1;29?l252900e9=50;9je1<722cj;7>5;hf5>5<<g:3<6=44}c4e6?6=<3:1<v*;3082`0=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17b=67;29?xd1n80;694?:1y'067=9m?0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::m0=2<722wi:k>50;694?6|,=9:6<j:;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=h;0=1<75rb7ge>5<3290;w):<1;3g1>Ne?m1Cn9o4$3g3>4=n110;66gn4;29?lb12900c>78:188yg0bm3:187>50z&774<6l<1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;n1:3?6=3th=ii4?:583>5}#<:;1=i;4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fd783>>i41>0;66sm6g`94?2=83:p(9=>:0f6?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831d?4950;9~f3`f290?6=4?{%605?7c=2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44o2;4>5<<uk<m57>54;294~"3;80:h85Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?j5>?3:17pl9f983>1<729q/8>?51e78Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722e85:4?::a2c1=83>1<7>t$512>4b23Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75`38594?=zj?l=6=4;:183!2493;o96Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188k6?02900qo8i5;290?6=8r.??<4>d49Kf2b<@k>j7)<j0;38m<>=831bm94?::kg2?6=3f92;7>5;|`5b1<72=0;6=u+42395a3<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66a<9683>>{e>o91<7:50;2x 15628n>7El8d:Ja0d=#:l:1=6g68;29?lg32900ei850;9l7<1=831vn;kl:187>5<7s->8=7?k5:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<g:3<6=44}c52<?6=<3:1<v*;3082`<=Oj>n0Do:n;%0f4?7<a021<75fd783>>o41h0;66a<9683>>{e?8k1<7:50;2x 15628n27El8d:Ja0d=#:l:1=6g68;29?lb12900e>7n:188k6?02900qo9>5;290?6=8r.??<4>d89Kf2b<@k>j7)<j0;38m<>=831bh;4?::k0=d<722e85:4?::a341=83>1<7>t$512>4b>3Ah<h6Fm4`9'6`6=92c247>5;hf5>5<<a:3j6=44o2;4>5<<uk=:>7>54;294~"3;80:h45Gb6f8Lg2f3-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66sm70694?2=83:p(9=>:0f:?Md0l2Bi8l5+2d295>o>03:17dj9:188m6?f2900c>78:188yg17n3:187>50z&774<6l01Cn:j4Hc6b?!4b83;0e4650;9j`3<722c85l4?::m0=2<722wi;<?50;694?6|,=9:6<j6;I`4`>Ne<h1/>h>51:k:<?6=3`n=6=44i2;b>5<<g:3<6=44}c53g?6=<3:1<v*;3082`<=Oj>n0Do:n;%0f4?7<a021<75fd783>>o41h0;66a<9683>>{e?9o1<7:50;2x 15628n27El8d:Ja0d=#:l:1=6g68;29?lb12900e>7n:188k6?02900qo9?9;290?6=8r.??<4>d89Kf2b<@k>j7)<j0;38m<>=831bh;4?::k0=d<722e85:4?::a35d=83>1<7>t$512>4b>3Ah<h6Fm4`9'6`6=92c247>5;hf5>5<<a:3j6=44o2;4>5<<uk=;:7>54;294~"3;80:h45Gb6f8Lg2f3-8n<7?4i8:94?=nl?0;66g<9`83>>i41>0;66sm71:94?2=83:p(9=>:0f:?Md0l2Bi8l5+2d295>o>03:17dj9:188m6?f2900c>78:188yg17;3:187>50z&774<6l01Cn:j4Hc6b?!4b83;0e4650;9j`3<722c85l4?::m0=2<722wi;=;50;694?6|,=9:6<j6;I`4`>Ne<h1/>h>51:k:<?6=3`n=6=44i2;b>5<<g:3<6=44}c534?6=<3:1<v*;3082`<=Oj>n0Do:n;%0f4?7<a021<75fd783>>o41h0;66a<9683>>{e?981<7:50;2x 15628n27El8d:Ja0d=#:l:1=6g68;29?lb12900e>7n:188k6?02900qo8id;290?6=8r.??<4>d89Kf2b<@k>j7)<j0;38m<>=831bh;4?::k0=d<722e85:4?::a2c`=83>1<7>t$512>4b>3Ah<h6Fm4`9'6`6=92c247>5;hf5>5<<a:3j6=44o2;4>5<<uk=j97>51081>44|@k>j7):<1;`;=>\>?3;p=?4r$c6a>1573`8h97>5$2;6>7e33g9287>4;h0a=?6=,:3>6?m;;o1:0?7<3`8ji7>5$2;6>7e33g9287<4;h0b7?6=,:3>6?m;;o1:0?5<3`8247>5$2;6>7e33g9287:4;h0;`?6=,:3>6?m;;o1:0?3<3`83>7>5$2;6>7e33g928784;h043?6=,:3>6?m;;o1:0?1<3`8>;7>5$2;6>7e33g928764;h3f<?6=,:3>6?m;;o1:0??<3`kh6=44i2c;>5<<a:n:6=44i2f3>5<<a:n96=44o2f0>5<<g;i=6=44bc5e>5<6290;w):<1;`60>Ne?m1Cn9o4o2;1>5<<uk9=;7>51b8a>71|@k>j7):<1;`;`>\>?3;p=h4r$3a;>2g13`9h:7>5$2;6>6e23g9287>4;h1`0?6=,:3>6>m:;o1:0?7<3`9h?7>5$2;6>6e23g9287<4;h1`6?6=,:3>6>m:;o1:0?5<3`9h=7>5$2;6>6e23g9287:4;h1`4?6=,:3>6>m:;o1:0?3<3`9ij7>5$2;6>6e23g928784;h1aa?6=,:3>6>m:;o1:0?1<3`9ih7>5$2;6>6e23g928764;h1ag?6=,:3>6>m:;o1:0??<3`9hj7>5$2;6>6e23g9287o4;h1`a?6=,:3>6>m:;o1:0?d<3`9hh7>5$2;6>6e23g9287m4;h1`g?6=,:3>6>m:;o1:0?b<3`9hn7>5$2;6>6e23g9287k4;h1`e?6=,:3>6>m:;o1:0?`<3`9h57>5$2;6>6e23g9287??;:k0g=<72-9297=l5:l0=1<6921b?n950;&0=0<4k<1e?4:51398m6de290/?4;53b78j6?328907dol:188m6g?2900e<k9:188m6b62900e>j?:188m6b52900c>j<:188k7e12900no9i:182>5<7s->8=7l:4:Ja3a=Oj=k0c>7=:188ygd0m3:1=7>50z&774<5k>1Cn:j4Hc6b?j7b=3:17plm4b83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xde=:0;6l4?:1y'067=;kk0Do9k;I`7e>\>?3;p?:4r$2c:>g0a3-8n<7:4i`594?=nl?0;66gn4;29?j5>?3:17b=69;29?l2>290/?4;5499m7<2=821b8:4?:%1:1?2?3g9287?4;h65>5<#;0?1855a38696>=n<<0;6)=65;6;?k5><3907d:;:18'7<3=<11e?4:54:9~fg35290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a2c=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a14<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c4e?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc73>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm4e83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xde<o0;694?:1y'067=;1:0Do9k;I`7e>"4i00i:k5fa783>>oc?3:17d=m0;29?j50?3:17plm4d83>1<729q/8>?53928Lg1c3Ah?m6*<a88a2c=ni?0;66gk7;29?l5e83:17b=87;29?xd4>?0;694?:1y'067=;1:0Do9k;I`7e>"4i00i;=5fa783>>oc?3:17d=m0;29?j50?3:17p}>e783>7}Y9l<01o:l:`48yv4d>3:1>vP=c79>730=;>=0q~=75;296~;e?o085?5237497g6<uz93:7>56z?a3`<6m<16n9m5d69>f1b=l>16n9h5d69>f1c=l>16?;85d69~w6de2909wS=mb:?a15<3<2wx?om50;0xZ6dd34h>>7:;;|q0fa<72;qU?oj4=c71>13<uz9ii7>52z\0f`=:j<818;5rs2`e>5<5sW9ij63m53873>{t;j:1<7<t^2a3?8d2:3>27p}<c083>7}Y;j;01o;<:568yv5d:3:1>vP<c39>f05=<<1v>m<:181[5d;27i9>4;6:p7f2=838pR>m;;<`67?203ty8o;4?:3y]7f0<5k?86974}r1`3?6=:rT8o:52b42900=z{:i36=4={_1`<>;e=90?:6s|3b;94?4|V:i270l:0;64?xu4kh0;6?uQ3bc89g372=30q~=lb;296~X4kk16n8?5459~w6ed2909wS=lc:?a14<3=2wx?nj50;0xZ6ec34h>=7:9;|q0g`<72;qU?nk4=c72>11<uz9hj7>52z\0gc=:j<;1845rs2f3>5<2sW9o<63m528b0>;e=;0j863m508b0>;e=90j86s|3e394?3|V:n:70l:3;c4?8d2:3k<70l:1;c4?8d283k<7p}<d383>7}Y;m801o;<:e48yv5c;3:1>vP<d29>f06=;030q~ln8;296~;e=8085452b429`3=z{kk26=4={<`66?5>127i9<4k6:pfdg=838p1o;<:2;:?8d2:3n=7p}mac83>7}:j=i1?:94=c6g>d0<uzhjo7>52z?a0a<4?>16n9k5a79~wggc2909w0l;f;c5?8d3m39<;6s|b`g94?4|5k>m6>98;<152?g13tyin=4?:3y>f1e=;k:01o;?:2;4?xuej80;6?u2b4397<1<5k>o6>l?;|qaf7<72;q6n8<538589g2b2:h;7p}mb283>7}:j<91?494=c6e>6d73twxmn4?:3y]ef=:;?=1mn5rs0g;>5<5sW;n463<6680fg=z{;?<6=4={_063>;4>>08o:5rs354>5<5sW8<;63<6680g==z{;296=4={_0;6>;4>>08o45rs3:g>5<5sW83h63<6680gd=z{;336=4={_0:<>;4>>08oo5rs3c0>5<5sW8j?63<6680gf=z{;kn6=4={_0ba>;4>>08oi5rs3`:>5<5sW8i563<6680g`=z{;i>6=4={_0`1>;4>>08ok5rs3a5>5<5sW8h:63<6681g3=z{:k36=4={_1b<>;4>>08m55rs2f3>5<5sW9o<63<6680`5=z{:n:6=4={_1g5>;4>>08h<5rs2f1>5<5sW9o>63<6680`7=z{:n86=4={_1g7>;4>>08h>5rsc;5>5<ds4h<j7=62:?022<4k?16?;953b6896002:i870=97;1`6>;4>>08o<5237597f6<5:<<6>li;<153?5em278::4<be9>731=;ki01>88:0g5?x{e?h=1<7?>:3826~Ne<h1/8>?5b9;8^<1=9r;96p*m4c8775=n:j?1<7*<9481g1=i;0>1<65f2c;94?"41<09o95a38695>=n:ho1<7*<9481g1=i;0>1>65f2`194?"41<09o95a38697>=n:021<7*<9481g1=i;0>1865f29f94?"41<09o95a38691>=n:181<7*<9481g1=i;0>1:65f26594?"41<09o95a38693>=n:<=1<7*<9481g1=i;0>1465f1d:94?"41<09o95a3869=>=nij0;66g<a983>>o4l80;66g<d183>>o4l;0;66a<d283>>i5k?0;66lm7g83>4<729q/8>?5b468Lg1c3Ah?m6a<9383>>{e;?=1<7?l:c813~Ne<h1/8>?5b9f8^<1=9r;n6p*=c984e==n;j<1<7*<9480g0=i;0>1<65f3b694?"41<08o85a38695>=n;j91<7*<9480g0=i;0>1>65f3b094?"41<08o85a38697>=n;j;1<7*<9480g0=i;0>1865f3b294?"41<08o85a38691>=n;kl1<7*<9480g0=i;0>1:65f3cg94?"41<08o85a38693>=n;kn1<7*<9480g0=i;0>1465f3ca94?"41<08o85a3869=>=n;jl1<7*<9480g0=i;0>1m65f3bg94?"41<08o85a3869f>=n;jn1<7*<9480g0=i;0>1o65f3ba94?"41<08o85a3869`>=n;jh1<7*<9480g0=i;0>1i65f3bc94?"41<08o85a3869b>=n;j31<7*<9480g0=i;0>1==54i2a;>5<#;0?1?n;4n2;7>47<3`9h;7>5$2;6>6e23g9287?=;:k0fg<72-9297=l5:l0=1<6;21bmn4?::k0e=<722c:i;4?::k0`4<722c8h=4?::k0`7<722e8h>4?::m1g3<722hi;k4?:083>5}#<:;1n8:4Hc5g?Md3i2e85?4?::af2c=83;1<7>t$512>7e03Ah<h6Fm4`9l5`3=831vno:l:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c4e?lg12900ei950;9j7g6=831d?:950;9~fg34290j6=4?{%605?5ei2Bi;i5Gb5c8^<1=9r9<6p*<a88a2c=#:l:186gn7;29?lb12900el:50;9l7<1=831d?4750;9j0<<72-9297:7;o1:0?6<3`><6=4+38790==i;0>1=65f4783>!5>=3>37c=64;08?l22290/?4;5499m7<2=;21b894?:%1:1?2?3g9287:4;|`a17<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c4e?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc72>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm5183>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o8i;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno:k:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c4e?lg12900ei950;9j7g6=831d?:950;9~fg2a290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k<m7do9:188ma1=831b?o>50;9l721=831vno:j:187>5<7s->8=7=70:Ja3a=Oj=k0(>o6:c4e?lg12900ei950;9j7g6=831d?:950;9~f601290?6=4?{%605?5?82Bi;i5Gb5c8 6g>2k=;7do9:188ma1=831b?o>50;9l721=831v<k9:181[7b>27i8n4n6:p6f0=838pR?m9;<152?50?2wx?5;50;0x9g1a2:3970=96;1a4>{t;1<1<78t=c5f>4c234h?o7j8;<`7`?b034h?j7j8;<`7a?b0349=:7j8;|q0fg<72;qU?ol4=c73>12<uz9io7>52z\0ff=:j<81895rs2`g>5<5sW9ih63m53871>{t;ko1<7<t^2`f?8d2:3>=7p}<bg83>7}Y;kl01o;=:558yv5d83:1>vP<c19>f04=<01v>m>:181[5d927i9>4;4:p7f4=838pR>m=;<`67?223ty8o>4?:3y]7f5<5k?86984}r1`0?6=:rT8o952b41902=z{:i=6=4={_1`2>;e=:0?56s|3b594?4|V:i<70l:0;66?xu4k10;6?uQ3b:89g372=<0q~=l9;296~X4k016n8>5469~w6ef2909wS=la:?a15<312wx?nl50;0xZ6ee34h>=7:;;|q0gf<72;qU?nm4=c72>13<uz9hh7>52z\0ga=:j<;18;5rs2af>5<5sW9hi63m50873>{t;jl1<7<t^2ae?8d293>27p}<d183>0}Y;m:01o;<:`689g352h>01o;>:`689g372h>0q~=k1;291~X4l816n8=5a69>f04=i>16n8?5a69>f06=i>1v>j=:181[5c:27i9>4k6:p7a5=838pR>j<;<`64?5>12wxnl650;0x9g362:3270l:0;f5?xuei00;6?u2b4097<?<5k?:6i84}r`be?6=:r7i9>4<989>f04=l?1voom:1818d3k39<;63m4e8b2>{tjhi1<7<t=c6g>61034h?i7o9;|qaea<72;q6n9h5a79>f1c=;>=0q~lne;296~;e<o08;:523749e3=z{kh;6=4={<`7g?5e827i9=4<969~wgd62909w0l:1;1:3>;e<m08n=5rsc`1>5<5s4h>>7=67:?a0`<4j91vol<:1818d2;392;63m4g80f5=zuzkh6=4={_c`?851?3kh7p}>e983>7}Y9l201>88:2`a?xu5=>0;6?uQ245896002:i<7p}=7683>7}Y:>=01>88:2a;?xu50;0;6?uQ290896002:i27p}=8e83>7}Y:1n01>88:2ab?xu5110;6?uQ28:896002:ii7p}=a283>7}Y:h901>88:2a`?xu5il0;6?uQ2`g896002:io7p}=b883>7}Y:k301>88:2af?xu5k<0;6?uQ2b7896002:im7p}=c783>7}Y:j<01>88:3a5?xu4i10;6?uQ3`:896002:k37p}<d183>7}Y;m:01>88:2f3?xu4l80;6?uQ3e3896002:n:7p}<d383>7}Y;m801>88:2f1?xu4l:0;6?uQ3e1896002:n87p}m9783>f}:j>l1?4<4=244>6e1349=;7=l4:?022<4k:16?;953b0896002:i:70=97;1`4>;4>>08nk5237597gc<5:<<6>lk;<153?5ek278::4>e79~yg1f13:1=<4=:00xLg2f3->8=7l79:X:3?7|9;0v(o:m:513?l4d=3:1(>7::3a7?k5><3:07d<m9;29 6?22;i?7c=64;38?l4fm3:1(>7::3a7?k5><3807d<n3;29 6?22;i?7c=64;18?l4>03:1(>7::3a7?k5><3>07d<7d;29 6?22;i?7c=64;78?l4?:3:1(>7::3a7?k5><3<07d<87;29 6?22;i?7c=64;58?l42?3:1(>7::3a7?k5><3207d?j8;29 6?22;i?7c=64;;8?lgd2900e>o7:188m6b62900e>j?:188m6b52900c>j<:188k7e12900no9i:182>5<7s->8=7l:4:Ja3a=Oj=k0c>7=:188yg51?3:1=n4m:35xLg2f3->8=7l7d:X:3?7|9l0v(?m7:6cb?l5d>3:1(>7::2a6?k5><3:07d=l4;29 6?22:i>7c=64;38?l5d;3:1(>7::2a6?k5><3807d=l2;29 6?22:i>7c=64;18?l5d93:1(>7::2a6?k5><3>07d=l0;29 6?22:i>7c=64;78?l5en3:1(>7::2a6?k5><3<07d=me;29 6?22:i>7c=64;58?l5el3:1(>7::2a6?k5><3207d=mc;29 6?22:i>7c=64;;8?l5dn3:1(>7::2a6?k5><3k07d=le;29 6?22:i>7c=64;`8?l5dl3:1(>7::2a6?k5><3i07d=lc;29 6?22:i>7c=64;f8?l5dj3:1(>7::2a6?k5><3o07d=la;29 6?22:i>7c=64;d8?l5d13:1(>7::2a6?k5><3;;76g<c983>!5>=39h96`<95825>=n;j=1<7*<9480g0=i;0>1=?54i2`a>5<#;0?1?n;4n2;7>45<3`kh6=44i2c;>5<<a8o=6=44i2f2>5<<a:n;6=44i2f1>5<<g:n86=44o3a5>5<<jk=m6=4>:183!2493h>86Fm7e9Kf1g<g:396=44}c`4a?6=93:1<v*;3081g2=Oj>n0Do:n;n3f1?6=3thi8n4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m6g9je3<722co;7>5;h1a4?6=3f9<;7>5;|`a16<72h0;6=u+42397gg<@k=o7El;a:X:3?7|;>0v(>o6:c4e?!4b83>0el950;9j`3<722cj87>5;n1:3?6=3f9257>5;h6:>5<#;0?1855a38694>=n<>0;6)=65;6;?k5><3;07d:9:18'7<3=<11e?4:52:9j00<72-9297:7;o1:0?5<3`>?6=4+38790==i;0>1865rbc71>5<f290;w):<1;1ae>Ne?m1Cn9o4Z8595~502t.8m44m6g9'6`6=<2cj;7>5;hf5>5<<ah>1<75`38594?=h;031<75f4883>!5>=3>37c=64;28?l20290/?4;5499m7<2=921b8;4?:%1:1?2?3g9287<4;h66>5<#;0?1855a38697>=n<=0;6)=65;6;?k5><3>07plm5083>d<729q/8>?53cc8Lg1c3Ah?m6T67;3x72<z,:k26o8i;%0f4?2<ah=1<75fd783>>of<3:17b=67;29?j5>13:17d:6:18'7<3=<11e?4:50:9j02<72-9297:7;o1:0?7<3`>=6=4+38790==i;0>1>65f4483>!5>=3>37c=64;18?l23290/?4;5499m7<2=<21vno;?:18b>5<7s->8=7=ma:Ja3a=Oj=k0V4951z14>x"4i00i:k5+2d290>of?3:17dj9:188md2=831d?4950;9l7<?=831b844?:%1:1?2?3g9287>4;h64>5<#;0?1855a38695>=n<?0;6)=65;6;?k5><3807d:::18'7<3=<11e?4:53:9j01<72-9297:7;o1:0?2<3thi8i4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m6g9je3<722co;7>5;h1a4?6=3f9<;7>5;|`a0c<72=0;6=u+42397=6<@k=o7El;a:&0e<<e>o1bm;4?::kg3?6=3`9i<7>5;n143?6=3thi8h4?:583>5}#<:;1?5>4Hc5g?Md3i2.8m44m6g9je3<722co;7>5;h1a4?6=3f9<;7>5;|`023<72=0;6=u+42397=6<@k=o7El;a:&0e<<e?91bm;4?::kg3?6=3`9i<7>5;n143?6=3ty:i;4?:3y]5`0<5k>h6l84}r0`2?6=:rT9o;523749721<uz9397>52z?a3c<41;16?;853c28yv5?>3:1:v3m7d82a0=:j=i1h:52b5f9`2=:j=l1h:52b5g9`2=:;?<1h:5rs2`a>5<5sW9in63m51870>{t;ki1<7<t^2``?8d2:3>?7p}<be83>7}Y;kn01o;=:578yv5em3:1>vP<bd9>f04=<?1v>li:181[5en27i9?4;7:p7f6=838pR>m?;<`66?2>3ty8o<4?:3y]7f7<5k?869:4}r1`6?6=:rT8o?52b41900=z{:i86=4={_1`7>;e=:0?:6s|3b694?4|V:i?70l:3;64?xu4k?0;6?uQ3b489g342=30q~=l7;296~X4k>16n8>5449~w6e?2909wS=l8:?a15<3>2wx?n750;0xZ6e>34h><7:8;|q0gd<72;qU?no4=c73>1?<uz9hn7>52z\0gg=:j<;1895rs2a`>5<5sW9ho63m50871>{t;jn1<7<t^2ag?8d293>=7p}<cd83>7}Y;jo01o;>:558yv5dn3:1>vP<cg9>f07=<01v>j?:186[5c827i9>4n4:?a17<f<27i9<4n4:?a15<f<2wx?i?50;7xZ6b634h>?7o8;<`66?g034h>=7o8;<`64?g03ty8h?4?:3y]7a4<5k?86i84}r1g7?6=:rT8h>52b4297<?<uzhj47>52z?a14<41016n8>5d79~wgg>2909w0l:2;1:=>;e=80o:6s|b`c94?4|5k?86>76;<`66?b13tyimo4?:3y>f1e=;>=01o:k:`48yvdfk3:1>v3m4e8032=:j=o1m;5rsccg>5<5s4h?j7o9;<`7a?50?2wxnlk50;0x9g2a2:=<70=96;c5?xuej90;6?u2b5a97g6<5k?;6>78;|qaf4<72;q6n8?538589g2c2:h;7p}mb383>7}:j<81?494=c6f>6d73tyin>4?:3y>f05=;0=01o:i:2`3?x{tij0;6?uQab9>731=ij1v<k7:181[7b0278::4<bc9~w7302909wS<:7:?022<4k>1v?98:181[40?278::4<c99~w7>52909wS<72:?022<4k01v?6k:181[4?l278::4<c`9~w7??2909wS<68:?022<4kk1v?o<:181[4f;278::4<cb9~w7gb2909wS<ne:?022<4km1v?l6:181[4e1278::4<cd9~w7e22909wS<l5:?022<4ko1v?m9:181[4d>278::4=c79~w6g?2909wS=n8:?022<4i11v>j?:181[5c8278::4<d19~w6b62909wS=k1:?022<4l81v>j=:181[5c:278::4<d39~w6b42909wS=k3:?022<4l:1vo79:18`8d0n392>63<6680g3=:;?=1?n:4=244>6e4349=;7=l2:?022<4k816?;953b2896002:hm70=97;1aa>;4>>08ni5237597ge<5:<<6<k9;|a126=83=1<7>t$512>61a3Ah<h6Fm4`9'6`6=02c9ol4?::k1gg<722c9on4?::k1ga<722c9oh4?::k1gc<722e85<4?::a1<g=8391<7>t$512>61e3Ah<h6Fm4`9'6`6=9j90e?mn:188m7ee2900c>7>:188yg34<3:1;7>50z&774<4?o1Cn:j4Hc6b?!4b83=0e?mn:188m7ee2900e?ml:188m7ec2900e?mj:188m7ea2900c>7>:188yg31n3:1?7>50z&774<4?k1Cn:j4Hc6b?!4b83;h?6g=c`83>>o5kk0;66a<9083>>{e=:?1<7<50;2x 1562:=j7El8d:Ja0d=#:l:1=n5f2bc94?=h;0;1<75rb410>5<4290;w):<1;14f>Ne?m1Cn9o4$3g3>6e<a;ij6=44i3aa>5<<g:3:6=44}c705?6=;3:1<v*;30803g=Oj>n0Do:n;%0f4?7d;2c9ol4?::k1gg<722e85<4?::a164=8391<7>t$512>61e3Ah<h6Fm4`9'6`6=9j90e?mn:188m7ee2900c>7>:188yg3f<3:1;7>50z&774<4?o1Cn:j4Hc6b?!4b83;:7d<la;29?l4dj3:17d<lc;29?l4dl3:17d<le;29?l4dn3:17b=61;29?xd2i<0;6:4?:1y'067=;>l0Do9k;I`7e>"5m90:=6g=c`83>>o5kk0;66g=cb83>>o5km0;66g=cd83>>o5ko0;66a<9083>>{e=h<1<7950;2x 1562:=m7El8d:Ja0d=#:l:1=<5f2bc94?=n:jh1<75f2ba94?=n:jn1<75f2bg94?=n:jl1<75`38394?=zj<k36=48:183!24939<j6Fm7e9Kf1g<,;o;6<?4i3ab>5<<a;ii6=44i3a`>5<<a;io6=44i3af>5<<a;im6=44o2;2>5<<uk?i=7>57;294~"3;808;k5Gb6f8Lg2f3-8n<7?l9:k1gd<722c9oo4?::k1gf<722c9oi4?::k1g`<722c9ok4?::m0=4<722wi9l950;594?6|,=9:6>9i;I`4`>Ne<h1/>h>5109j6fg=831b>nl50;9j6fe=831b>nj50;9j6fc=831b>nh50;9l7<7=831vn8o6:184>5<7s->8=7=8f:Ja3a=Oj=k0(?k?:038m7ef2900e?mm:188m7ed2900e?mk:188m7eb2900e?mi:188k6?62900qo;na;293?6=8r.??<4<7g9Kf2b<@k>j7)<j0;32?l4di3:17d<lb;29?l4dk3:17d<ld;29?l4dm3:17d<lf;29?j5>93:17pl:ab83>2<729q/8>?536d8Lg1c3Ah?m6*=e1825>o5kh0;66g=cc83>>o5kj0;66g=ce83>>o5kl0;66g=cg83>>i4180;66sm5c194?1=83:p(9=>:25e?Md0l2Bi8l5+2d295f?<a;ij6=44i3aa>5<<a;ih6=44i3ag>5<<a;in6=44i3ae>5<<g:3:6=44}c7a4?6=<3:1<v*;3080<4=Oj>n0Do:n;h0`e?6=3`8hn7>5;h1a4?6=3f92=7>5;|`6eg<72>0;6=u+423972`<@k=o7El;a:&1a5<692c9ol4?::k1gg<722c9on4?::k1ga<722c9oh4?::k1gc<722e85<4?::a1db=83=1<7>t$512>61a3Ah<h6Fm4`9'6`6=981b>no50;9j6fd=831b>nm50;9j6fb=831b>nk50;9j6f`=831d?4?50;9~f0gb290<6=4?{%605?50n2Bi;i5Gb5c8 7c728;0e?mn:188m7ee2900e?ml:188m7ec2900e?mj:188m7ea2900c>7>:188yg3fn3:187>50z&774<4?j1Cn:j4Hc6b?!4b83;o=6g=c`83>>o5kk0;66g=cb83>>i4180;66sm5c694?1=83:p(9=>:25e?Md0l2Bi8l5+2d295f?<a;ij6=44i3aa>5<<a;ih6=44i3ag>5<<a;in6=44i3ae>5<<g:3:6=44}c7a6?6=<3:1<v*;3080<4=Oj>n0Do:n;h0`e?6=3`8hn7>5;h1a4?6=3f92=7>5;|`6e5<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm58d94?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn87j:186>5<7s->8=7?ka:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<a:3j6=44o2;4>5<<uk?2h7>55;294~"3;80:hl5Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?l5>i3:17b=67;29?xd21j0;684?:1y'067=9mk0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::k0=d<722e85:4?::a1<d=83?1<7>t$512>4bf3Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75f38c94?=h;0=1<75rb4ag>5<4290;w):<1;`4g>Ne?m1Cn9o4i`494?=n;><1<75`38394?=zj<ij6=4;:183!249393<6Fm7e9Kf1g<ah<1<75fd683>>o4j90;66a<7683>>{e=m>1<7=50;2x 1562k=h7El8d:Ja0d=ni?0;66g<7783>>i4180;66sm5e394?2=83:p(9=>:2:3?Md0l2Bi8l5fa783>>oc?3:17d=m0;29?j50?3:17pl:d983>6<729q/8>?5b6a8Lg1c3Ah?m6gn6;29?l50>3:17b=61;29?xd2l<0;694?:1y'067=;1:0Do9k;I`7e>of>3:17dj8:188m6d72900c>98:188yg3ck3:1?7>50z&774<e?j1Cn:j4Hc6b?lg12900e>99:188k6?62900qo;k9;290?6=8r.??<4<819Kf2b<@k>j7do9:188ma1=831b?o>50;9l721=831vn8k?:180>5<7s->8=7l8c:Ja3a=Oj=k0el850;9j720=831d?4?50;9~f0bc290?6=4?{%605?5?82Bi;i5Gb5c8md0=831bh:4?::k0f5<722e8;:4?::a1`2=8391<7>t$512>g1d3Ah<h6Fm4`9je3<722c8;;4?::m0=4<722wi9h?50;694?6|,=9:6>6?;I`4`>Ne<h1bm;4?::kg3?6=3`9i<7>5;n143?6=3th>i54?:283>5}#<:;1n:m4Hc5g?Md3i2cj:7>5;h142?6=3f92=7>5;|`6a0<72=0;6=u+42397=6<@k=o7El;a:kb2?6=3`n<6=44i2`3>5<<g:=<6=44}c7fg?6=;3:1<v*;308a3f=Oj>n0Do:n;hc5>5<<a:==6=44o2;2>5<<uk?n57>54;294~"3;8084=5Gb6f8Lg2f3`k=6=44ie594?=n;k:1<75`36594?=zj<l;6=4<:183!2493h<o6Fm7e9Kf1g<ah<1<75f36494?=h;0;1<75rb4gg>5<3290;w):<1;1;4>Ne?m1Cn9o4i`494?=nl>0;66g<b183>>i4?>0;66sm5g694?5=83:p(9=>:c5`?Md0l2Bi8l5fa783>>o4??0;66a<9083>>{e=o;1<7:50;2x 1562:2;7El8d:Ja0d=ni?0;66gk7;29?l5e83:17b=87;29?xd2l90;6>4?:1y'067=j>i0Do9k;I`7e>of>3:17d=86;29?j5>93:17pl:cb83>7<729q/8>?536c8Lg1c3Ah?m6*=e182g>o5kh0;66a<9083>>{e=m91<7<50;2x 1562:=j7El8d:Ja0d=#:l:1=n5f2bc94?=h;0;1<75rb4f4>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk?on7>52;294~"3;808;l5Gb6f8Lg2f3-8n<7?l;h0`e?6=3f92=7>5;|`6`c<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi9h=50;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f0c029096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo;jb;296?6=8r.??<4<7`9Kf2b<@k>j7)<j0;3`?l4di3:17b=61;29?xd2mo0;6?4?:1y'067=;>k0Do9k;I`7e>"5m90:o6g=c`83>>i4180;66sm5g194?4=83:p(9=>:25b?Md0l2Bi8l5+2d295f=n:jk1<75`38394?=zj<im6=4=:183!24939<m6Fm7e9Kf1g<,;o;6<m4i3ab>5<<g:3:6=44}c7`f?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl:d383>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi9i850;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj<nj6=4::183!2493;om6Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188m6?f2900c>78:188yg3cm3:197>50z&774<6lh1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;h1:e?6=3f92;7>5;|`6a7<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm5d494?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn8kn:186>5<7s->8=7?ka:Ja3a=Oj=k0(?k?:09j==<722cj87>5;hf5>5<<a:3j6=44o2;4>5<<uk?ni7>55;294~"3;80:hl5Gb6f8Lg2f3-8n<7?4i8:94?=ni=0;66gk6;29?l5>i3:17b=67;29?xd2n;0;684?:1y'067=9mk0Do9k;I`7e>"5m90:7d77:188md2=831bh;4?::k0=d<722e85:4?::a1fc=83?1<7>t$512>4bf3Ah<h6Fm4`9'6`6=92c247>5;hc7>5<<am<1<75f38c94?=h;0=1<75rb473>5<4290;w):<1;`4g>Ne?m1Cn9o4i`494?=n;><1<75`38394?=zj<>o6=4;:183!249393<6Fm7e9Kf1g<ah<1<75fd683>>o4j90;66a<7683>>{e=<>1<7=50;2x 1562k=h7El8d:Ja0d=ni?0;66g<7783>>i4180;66sm54394?2=83:p(9=>:2:3?Md0l2Bi8l5fa783>>oc?3:17d=m0;29?j50?3:17pl:5983>6<729q/8>?5b6a8Lg1c3Ah?m6gn6;29?l50>3:17b=61;29?xd2=<0;694?:1y'067=;1:0Do9k;I`7e>of>3:17dj8:188m6d72900c>98:188yg32k3:1?7>50z&774<e?j1Cn:j4Hc6b?lg12900e>99:188k6?62900qo;:9;290?6=8r.??<4<819Kf2b<@k>j7do9:188ma1=831b?o>50;9l721=831vn88?:180>5<7s->8=7l8c:Ja3a=Oj=k0el850;9j720=831d?4?50;9~f03c290?6=4?{%605?5?82Bi;i5Gb5c8md0=831bh:4?::k0f5<722e8;:4?::a132=8391<7>t$512>g1d3Ah<h6Fm4`9je3<722c8;;4?::m0=4<722wi9;?50;694?6|,=9:6>6?;I`4`>Ne<h1bm;4?::kg3?6=3`9i<7>5;n143?6=3th>::4?:283>5}#<:;1n:m4Hc5g?Md3i2cj:7>5;h142?6=3f92=7>5;|`60c<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi98=50;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f03029096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo;:b;296?6=8r.??<4<7`9Kf2b<@k>j7)<j0;3`?l4di3:17b=61;29?xd2=o0;6?4?:1y'067=;>k0Do9k;I`7e>"5m90:o6g=c`83>>i4180;66sm57194?4=83:p(9=>:25b?Md0l2Bi8l5+2d295f=n:jk1<75`38394?=zj<<=6=4=:183!24939<m6Fm7e9Kf1g<,;o;6<m4i3ab>5<<g:3:6=44}c77a?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl:5383>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi98850;794?6|,=9:6<jn;I`4`>Ne<h1/>h>51:k:<?6=3`k?6=44ie494?=n;0k1<75`38594?=zj<?j6=4::183!2493;om6Fm7e9Kf1g<,;o;6<5f9983>>of<3:17dj9:188m6?f2900c>78:188yg32m3:197>50z&774<6lh1Cn:j4Hc6b?!4b83;0e4650;9je1<722co:7>5;h1:e?6=3f92;7>5;|`627<72<0;6=u+42395ag<@k=o7El;a:&1a5<63`336=44i`694?=nl?0;66g<9`83>>i41>0;66sm57794?3=83:p(9=>:0fb?Md0l2Bi8l5+2d295>o>03:17do;:188ma0=831b?4o50;9l7<1=831vn86?:180>5<7s->8=7l8c:Ja3a=Oj=k0el850;9j720=831d?4?50;9~f01c290?6=4?{%605?5?82Bi;i5Gb5c8md0=831bh:4?::k0f5<722e8;:4?::a1=2=8391<7>t$512>g1d3Ah<h6Fm4`9je3<722c8;;4?::m0=4<722wi95?50;694?6|,=9:6>6?;I`4`>Ne<h1bm;4?::kg3?6=3`9i<7>5;n143?6=3th>454?:283>5}#<:;1n:m4Hc5g?Md3i2cj:7>5;h142?6=3f92=7>5;|`6<0<72=0;6=u+42397=6<@k=o7El;a:kb2?6=3`n<6=44i2`3>5<<g:=<6=44}c7;g?6=;3:1<v*;308a3f=Oj>n0Do:n;hc5>5<<a:==6=44o2;2>5<<uk?357>54;294~"3;8084=5Gb6f8Lg2f3`k=6=44ie594?=n;k:1<75`36594?=zj<3;6=4<:183!2493h<o6Fm7e9Kf1g<ah<1<75f36494?=h;0;1<75rb4:g>5<3290;w):<1;1;4>Ne?m1Cn9o4i`494?=nl>0;66g<b183>>i4?>0;66sm58194?5=83:p(9=>:c5`?Md0l2Bi8l5fa783>>o4??0;66a<9083>>{e=>l1<7<50;2x 1562:=j7El8d:Ja0d=#:l:1=n5f2bc94?=h;0;1<75rb4:0>5<5290;w):<1;14e>Ne?m1Cn9o4$3g3>4e<a;ij6=44o2;2>5<<uk?3;7>52;294~"3;808;l5Gb6f8Lg2f3-8n<7?l;h0`e?6=3f92=7>5;|`6<g<72;0;6=u+423972g<@k=o7El;a:&1a5<6k2c9ol4?::m0=4<722wi95h50;094?6|,=9:6>9n;I`4`>Ne<h1/>h>51b9j6fg=831d?4?50;9~f0?529096=4?{%605?50i2Bi;i5Gb5c8 7c728i0e?mn:188k6?62900qo;8e;291?6=8r.??<4>d`9Kf2b<@k>j7)<j0;38m<>=831bm94?::kg2?6=3`92m7>5;n1:3?6=3th>4?4?:483>5}#<:;1=io4Hc5g?Md3i2.9i=4>;h;;>5<<ah>1<75fd783>>o41h0;66a<9683>>{e=1<1<7;50;2x 15628nj7El8d:Ja0d=#:l:1=6g68;29?lg32900ei850;9j7<g=831d?4950;9~f0>f290>6=4?{%605?7ci2Bi;i5Gb5c8 7c7281b554?::kb0?6=3`n=6=44i2;b>5<<g:3<6=44}c7;a?6==3:1<v*;3082`d=Oj>n0Do:n;%0f4?7<a021<75fa583>>oc>3:17d=6a;29?j5>?3:17pl:9083>0<729q/8>?51ec8Lg1c3Ah?m6*=e182?l??2900el:50;9j`3<722c85l4?::m0=2<722wi49850;694?6|,=9:6>9l;I`4`>Ne<h1/>h>51b68m7ef2900e?mm:188m7ed2900c>7>:188yg0213:187>50z&774<4?j1Cn:j4Hc6b?!4b838:7d<la;29?l4dj3:17d<lc;29?j5>93:17pl78`83>3<729q/8>?536g8Lg1c3Ah?m6*=e180e>o5kh0;66g=cc83>>o5kj0;66g=ce83>>o5kl0;66a<9083>>{e0>91<7950;2x 1562:=m7El8d:Ja0d=#:l:1?o5f2bc94?=n:jh1<75f2ba94?=n:jn1<75f2bg94?=n:jl1<75`38394?=zj1=n6=48:183!24939<j6Fm7e9Kf1g<,;o;6>l4i3ab>5<<a;ii6=44i3a`>5<<a;io6=44i3af>5<<a;im6=44o2;2>5<<uk2387>57;294~"3;808;k5Gb6f8Lg2f3-8n<7=m;h0`e?6=3`8hn7>5;h0`g?6=3`8hh7>5;h0`a?6=3`8hj7>5;n1:5?6=3th34o4?:783>5}#<:;1?:k4Hc5g?Md3i2.9i=4>e39j6fg=831b>nl50;9j6fe=831b>nj50;9j6fc=831d?4?50;9~f=16290=6=4?{%605?50m2Bi;i5Gb5c8 7c72090e?mn:188m7ee2900e?ml:188m7ec2900e?mj:188k6?62900qo682;293?6=8r.??<4<7g9Kf2b<@k>j7)<j0;3g`>o5kh0;66g=cc83>>o5kj0;66g=ce83>>o5kl0;66g=cg83>>i4180;66sm86694?5=83:p(9=>:25a?Md0l2Bi8l5+2d295f5<a;ij6=44i3aa>5<<g:3:6=44}c:41?6=?3:1<v*;30803c=Oj>n0Do:n;%0f4?2e3`8hm7>5;h0`f?6=3`8ho7>5;h0``?6=3`8hi7>5;h0`b?6=3f92=7>5;|`;32<72<0;6=u+423972b<@k=o7El;a:&1a5<3k2c9ol4?::k1gg<722c9on4?::k1ga<722e85<4?::a<2>=83=1<7>t$512>61a3Ah<h6Fm4`9'6`6=1?1b>no50;9j6fd=831b>nm50;9j6fb=831b>nk50;9j6f`=831d?4?50;9~f=1>290>6=4?{%605?50l2Bi;i5Gb5c8 7c728i37d<la;29?l4dj3:17d<lc;29?l4dl3:17b=61;29?xd??h0;6:4?:1y'067=;>l0Do9k;I`7e>"5m90:ok5f2bc94?=n:jh1<75f2ba94?=n:jn1<75f2bg94?=n:jl1<75`38394?=zj1=i6=49:183!24939<i6Fm7e9Kf1g<,;o;6n5f2bc94?=n:jh1<75f2ba94?=n:jn1<75f2bg94?=h;0;1<75rb95`>5<0290;w):<1;14b>Ne?m1Cn9o4$3g3>4e23`8hm7>5;h0`f?6=3`8ho7>5;h0``?6=3`8hi7>5;h0`b?6=3f92=7>5;|`;3a<72>0;6=u+423972`<@k=o7El;a:&1a5<6lj1b>no50;9j6fd=831b>nm50;9j6fb=831b>nk50;9j6f`=831d?4?50;9~f=1a29086=4?{%605?50j2Bi;i5Gb5c8 7c728i0e?mn:188m7ee2900c>7>:188yg>?83:1;7>50z&774<4?o1Cn:j4Hc6b?!4b83;h:6g=c`83>>o5kk0;66g=cb83>>o5km0;66g=cd83>>o5ko0;66a<9083>>{e01;1<7;50;2x 1562:=o7El8d:Ja0d=#:l:1545f2bc94?=n:jh1<75f2ba94?=n:jn1<75`38394?=zj1296=4::183!24939<h6Fm7e9Kf1g<,;o;6h5f2bc94?=n:jh1<75f2ba94?=n:jn1<75`38394?=zj1<i6=4;:183!2493;o56Fm7e9Kf1g<,;o;6<5f9983>>oc>3:17d=6a;29?j5>?3:17pl76b83>1<729q/8>?51e;8Lg1c3Ah?m6*=e182?l??2900ei850;9j7<g=831d?4950;9~fgg529086=4?{%605?50j2Bi;i5Gb5c8 7c728i87d<la;29?l4dj3:17b=61;29?xd?lj0;694?:1y'067=9m30Do9k;I`7e>"5m90:7d77:188ma0=831b?4o50;9l7<1=831vnoo<:180>5<7s->8=7=8b:Ja3a=Oj=k0(?k?:0a0?l4di3:17d<lb;29?j5>93:17pl75483>1<729q/8>?51e;8Lg1c3Ah?m6*=e182?l??2900ei850;9j7<g=831d?4950;9~fgg329086=4?{%605?50j2Bi;i5Gb5c8 7c728i87d<la;29?l4dj3:17b=61;29?xd?0:0;6:4?:1y'067=;>l0Do9k;I`7e>"5m908:6g=c`83>>o5kk0;66g=cb83>>o5km0;66g=cd83>>o5ko0;66a<9083>>{e0131<7950;2x 1562:=m7El8d:Ja0d=#:l:1=h=4i3ab>5<<a;ii6=44i3a`>5<<a;io6=44i3af>5<<a;im6=44o2;2>5<<uk2<:7>57;294~"3;808;k5Gb6f8Lg2f3-8n<7?k3:k1gd<722c9oo4?::k1gf<722c9oi4?::k1g`<722c9ok4?::m0=4<722wi4:>50;794?6|,=9:6>9k;I`4`>Ne<h1/>h>54`9j6fg=831b>nl50;9j6fe=831b>nj50;9l7<7=831vn58i:184>5<7s->8=7=8f:Ja3a=Oj=k0(?k?:`18m7ef2900e?mm:188m7ed2900e?mk:188m7eb2900e?mi:188k6?62900qo676;292?6=8r.??<4<7d9Kf2b<@k>j7)<j0;1:?l4di3:17d<lb;29?l4dk3:17d<ld;29?l4dm3:17b=61;29?xd?010;6:4?:1y'067=;>l0Do9k;I`7e>"5m90:h;5f2bc94?=n:jh1<75f2ba94?=n:jn1<75f2bg94?=n:jl1<75`38394?=zj12>6=4::183!24939<h6Fm7e9Kf1g<,;o;6<ji;h0`e?6=3`8hn7>5;h0`g?6=3`8hh7>5;n1:5?6=3th34:4?:683>5}#<:;1?:h4Hc5g?Md3i2.9i=4>e09j6fg=831b>nl50;9j6fe=831b>nj50;9j6fc=831b>nh50;9l7<7=831vn58j:185>5<7s->8=7=8e:Ja3a=Oj=k0(?k?:2f8m7ef2900e?mm:188m7ed2900e?mk:188m7eb2900c>7>:188yg>1l3:1;7>50z&774<4?o1Cn:j4Hc6b?!4b839i7d<la;29?l4dj3:17d<lc;29?l4dl3:17d<le;29?l4dn3:17b=61;29?xd2i80;65>50;2x 1562:3i7El8d:Ja0d=]1>0nw<=523817?7328=1=54=4;06>4?=9h09:7<8:2097c<zf8=n6=5a1c394>"4j;0:h=5+3e697>"5l90=7)<k1;48 7b52?1/>i=56:&1`1<13-8o9784$3f5>3=#:m=1:6*=e085?!4b:3<0(?k<:79'6`2=>2.9i849;%0f2?0<,;o<6;5+2d:92>"5m00=7)<ja;48 7ce2?1/>hm56:&1aa<13-8ni784$3ge>3=#:o:1:6*=f085?!4a:3<0(?h<:79'6c2=>2.9j849;%0e2?0<,;l<6;5+2g:92>"5n00=7)<ia;48 7`e2?1/>km56:&1ba<13-8mi784$3de>3=#;9:1:6*<0085?!57:3<0(>><:79'752=>2.8<849;%132?0<,::<6;5+31:92>"4800=7)=?a;48 66e2?1/?=m56:&04a<13-9;i784$22e>3=#;8:1:6*<1085?!56:3<0(>?<:79'742=>2.8=849;%122?0<,:;<6;5+30:92>"4900=7)=>a;48 67e2?1/?<m56:&05a<13-9:i784$23e>3=#;;:1:6*<6280=5=#;0l1?i64n2c3><=i;h;1=?5+3`g97d4<,:km6>o=;%1a7?d2>2.8:<4<;%156?5<,k<i6o8n;%`5g?d1i2di:i46;o`5a?753-9o97=4i`;94?=nik0;66g>cc83>>o6km0;66g<a583>>o4i<0;66g<a783>M5e=21b?l950;J0f0=<a:kj6=44i2ca>5<<a:kh6=44i2cg>5<<a?91<7*<94856>h41=0;76g91;29 6?22?80b>7;:098m36=83.858492:l0=1<532c>j7>5$2;6>34<f:3?6>54i7a94?"41<0=>6`<9587?>o1j3:1(>7::708j6?32<10e;o50;&0=0<1:2d85949;:k5=?6=,:3>6;<4n2;7>2=<a?21<7*<94856>h41=0376g97;29 6?22?80b>7;:898m30=83.858492:l0=1<f32c=97>5$2;6>34<f:3?6o54i7694?"41<0=>6`<958`?>o2m3:1(>7::708j6?32m10e;h50;&0=0<1m2d8594?;I1a1>=n>m0;6)=65;4f?k5><3;0D>l:;:k;7?6=,:3>65<4n2;7>5=O;k?07d6>:18'7<3=0;1e?4:51:J0f0=<a131<7*<948;<>h41=0;76g77;29 6?22120b>7;:098m=0=83.858478:l0=1<532c397>5$2;6>=><f:3?6>54i8094?"41<0346`<9587?>o>93:1(>7::9:8j6?32<10e4>50;&0=0<?02d85949;:k;b?6=,:3>6564n2;7>2=<a1o1<7*<948;<>h41=0376g7d;29 6?22120b>7;:898m=e=83.858478:l0=1<f32c3n7>5$2;6>=><f:3?6o54i9c94?"41<0346`<958`?>o?<3:1(>7::9:8j6?32m10e<>?:18'7<3=no1e?4:50:9jb`<72-9297hi;o1:0?7<3`lo6=4+3879bc=i;0>1>65ffb83>!5>=3lm7c=64;18?l`e290/?4;5fg9m7<2=<21bjl4?:%1:1?`a3g9287;4;h33=?6=,:3>6kh4n2;7>3=<a8:36=4+3879bc=i;0>1;65f11594?"41<0mj6`<958;?>o68?0;6)=65;de?k5><3307d??5;29 6?22ol0b>7;:`98m463290/?4;5fg9m7<2=j21b===50;&0=0<an2d8594l;:k247<72-9297hi;o1:0?b<3`;;=7>5$2;6>c`<f:3?6h54ig;94?"41<0mj6`<958e?>o6;;0;6)=65;305>h41=0;76g>3183>!5>=3;8=6`<9582?>o6:o0;6)=65;305>h41=0976g>2d83>!5>=3;8=6`<9580?>o6:m0;6)=65;305>h41=0?76g>2b83>!5>=3;8=6`<9586?>o6;k0;6)=65;305>h41=0=76g>3`83>!5>=3;8=6`<9584?>o6;00;6)=65;305>h41=0376g>3983>!5>=3;8=6`<958:?>o6;>0;6)=65;305>h41=0j76g>3783>!5>=3;8=6`<958a?>o6;<0;6)=65;305>h41=0h76g>3583>!5>=3;8=6`<958g?>o6;:0;6)=65;305>h41=0n76g>2c83>!5>=3;8=6`<958e?>o6<:0;6)=65;376>h41=0;76g>4083>!5>=3;?>6`<9582?>o6<k0;6)=65;37e>h41=0;76g>4883>!5>=3;?m6`<9582?>i6?=0;6)=65;347>h41=0;76a>7383>!5>=3;<?6`<9582?>i6?80;6)=65;347>h41=0976a>7183>!5>=3;<?6`<9580?>i6>o0;6)=65;347>h41=0?76a>6d83>!5>=3;<?6`<9586?>i6?m0;6)=65;347>h41=0=76a>7b83>!5>=3;<?6`<9584?>i6?k0;6)=65;347>h41=0376a>7`83>!5>=3;<?6`<958:?>i6?00;6)=65;347>h41=0j76a>7983>!5>=3;<?6`<958a?>i6?>0;6)=65;347>h41=0h76a>7783>!5>=3;<?6`<958g?>i6?<0;6)=65;347>h41=0n76a>6e83>!5>=3;<?6`<958e?>i6i>0;6)=65;3b2>h41=0;76a>a483>!5>=3;j:6`<9582?>i6i=0;6)=65;3b2>h41=0976a>a283>!5>=3;j:6`<9580?>i6i;0;6)=65;3b2>h41=0?76a>a083>!5>=3;j:6`<9586?>i6j90;6)=65;3b2>h41=0=76a>ag83>!5>=3;j:6`<9584?>i6il0;6)=65;3b2>h41=0376a>ae83>!5>=3;j:6`<958:?>i6ij0;6)=65;3b2>h41=0j76a>ac83>!5>=3;j:6`<958a?>i6ih0;6)=65;3b2>h41=0h76a>a883>!5>=3;j:6`<958g?>i6i10;6)=65;3b2>h41=0n76a>a183>!5>=3;j:6`<958e?>i6j00;6)=65;3a<>h41=0;76a>b683>!5>=3;i46`<9582?>i6k80;6)=65;3`4>h41=0;76a>bg83>!5>=3;h<6`<9582?>oe=k0;6)=65;`6e>h41=0;7E=m5:9jf0?=83.8584m5`9m7<2=92B8n854ic7;>5<#;0?1n8o4n2;7>7=<ak?<6=4+3879f0g<f:3?6>54ic4:>5<#;0?1n;64n2;7>5=O;k?07dl97;29 6?22k<37c=64;38L6d232ci:;4?:%1:1?d102d8594=;I1a1>=nj??1<7*<948a2==i;0>1?6F<b498mg03290/?4;5b7:8j6?32=10eo8<:18'7<3=j?20b>7;:498mg05290/?4;5b7:8j6?32?10eo8>:18'7<3=j?20b>7;:698yg3f:3:1o54?:1yKf1g<,=9:6>7l;[;4>f}483996?o52c800?562:?1=84=c;35>65=:00vb<9j:19m5g7=82.8h84:;%133?0<,:?36;5+2d692>"5n=0=7)<kd;48 7b72?1/>hj56:&1b5<13-9>5784$20`>3=#;?8196*<5185?!56>3<0(>?=:79'705=>2.89<49;%11<?0<,::m6;5+31f92>"4;;0=7)=<d;48 6722?1/?>=56:&01c<13-8no784$212>3=#;8:1:6*=d485?!57>3<0(?h>:79'6ce=>2.88:49;%110?0<,::36;5+2g;92>"5l;0=7)=>c;48 6312?1/?=:56:&1a3<13-9:i784$3g2>3=#;=<1:6*=eg85?!5193?0(>=8:79'70b=>2.8=o49;%0ea?0<,;oi6;5+32492>"4;=0=7)=<a;48 62c2?1/>ko56:&1ad<13-99:784$262>3=#:l=1:6*=fg85?!5403<0(?h=:79'6c5=>2.8<o49;%0f1?0<,;lo6;5+37292>"4::0=7)<ka;48 6462?1/>i:56:&05=<13-9>i784$3f5>3=#;:?1:6*<1885?!4cn3<0(>:6:79'71d=>2.9ih49;%131?0<,:;m6;5+2g`92>"5l80=7)<ke;48 66d2?1/?8l56:&062<13-9?>784$3d5>3=#;8n1:6*<4985?!5383<0(>:;:79'76e=>2.89l49;%104?0<,:>>6;5+34a92>"49:0=7)=>a;48 64b2?1/>k656:&04`<13-8o?784$26`>3=#;;81:6*<d586?!53n3<0(?h::79'77?=>2.8<>49;%0gg?0<,;n<6;5+33292>"5lk0=7)=;3;48 7`02?1/?>756:&1`=<13-9>;784$206>3=#;<?1:6*<2e85?!56?3<0(?j6:79'71g=>2.8<449;%11b?0<,:8j6;5+31092>"49=0=7)=?a;48 62b2?1/?<?56:&07g<13-8n?784$277>3=#:l81:6*<3d85?!5783<0(><m:79'6`?=>2.9i549;%157?5>82.85i4<919'7<c=;0:0b>o?:008j6g62;>0(>l<:868 6d32:h:7)=:2;48 65a2?1/n;l5b7c8 g0d2k<j7cl9d;31?kd1m38?7)=?1;48ma>=83.8584i0:l0=1<6n21bn8950;&0=0<e=h1e?4:53:9je=<722cjm7>5;h3`e?6=3`;9?7>5$2;6>4453g9287>4;h315?6=,:3>6<<=;o1:0?7<3`;:j7>5$2;6>4453g9287<4;h32a?6=,:3>6<<=;o1:0?5<3`;:h7>5$2;6>4453g9287:4;h32g?6=,:3>6<<=;o1:0?3<3`;:n7>5$2;6>4453g928784;h32e?6=,:3>6<<=;o1:0?1<3`;:57>5$2;6>4453g928764;h32<?6=,:3>6<<=;o1:0??<3`;:;7>5$2;6>4453g9287o4;h322?6=,:3>6<<=;o1:0?d<3`;:87>5$2;6>4453g9287m4;h327?6=,:3>6<<=;o1:0?b<3`;:>7>5$2;6>4453g9287k4;h325?6=,:3>6<<=;o1:0?`<3`;:<7>5$2;6>4453g9287??;:k24c<72-9297?=2:l0=1<6921b==k50;&0=0<6:;1e?4:51398m46c290/?4;51308j6?328907d??c;29 6?228897c=64;37?>o68k0;6)=65;316>h41=0:965f13c94?"41<0:>?5a386953=<a8826=4+3879574<f:3?6<94;h31<?6=,:3>6<<=;o1:0?7?32c:>:4?:%1:1?75:2d8594>9:9j570=83.8584>239m7<2=9h10e<<::18'7<3=9;80b>7;:0`8?l75<3:1(>7::001?k5><3;h76g>2183>!5>=3;9>6`<9582`>=n98?1<7*<948267=i;0>1=h54i02b>5<#;0?1=?<4n2;7>4`<3f;>>7>5$2;6>4033g9287??;:m214<72-9297?94:l0=1<6921d=8>50;&0=0<6>=1e?4:51398k42a290/?4;51768j6?328907b?;e;29 6?228<?7c=64;37?>i6<m0;6)=65;350>h41=0:965`17a94?"41<0::95a386953=<g8<i6=4+3879532<f:3?6<94;n35e?6=,:3>6<8;;o1:0?7?32e::44?:%1:1?71<2d8594>9:9l53>=83.8584>659m7<2=9h10c<88:18'7<3=9?>0b>7;:0`8?j71>3:1(>7::047?k5><3;h76a>6383>!5>=3;=86`<9582`>=h9<=1<7*<948221=i;0>1=h54o06`>5<#;0?1=;:4n2;7>4`<3f;i?7>5$2;6>4d23g9287<4;n3a6?6=,:3>6<l:;o1:0?5<3`;?47>5$2;6>4203g9287>4;h372?6=,:3>6<:8;o1:0?7<3`;?97>5$2;6>4203g9287<4;h370?6=,:3>6<:8;o1:0?5<3`?96=4+387916=i;0>1=65f5083>!5>=3?87c=64;08?l37290/?4;5529m7<2=;21b8k4?:%1:1?343g9287:4;h6f>5<#;0?19>5a38691>=n=m0;6)=65;70?k5><3<07d;l:18'7<3==:1e?4:57:9j1g<72-9297;<;o1:0?><3`?j6=4+387916=i;0>1565f5883>!5>=3?87c=64;c8?l3?290/?4;5529m7<2=j21b;84?:%1:1?113g9287?4;h57>5<#;0?1;;5a38696>=n?:0;6)=65;55?k5><3907d9=:18'7<3=??1e?4:54:9j34<72-929799;o1:0?3<3`2;6=4+387933=i;0>1:65f7g83>!5>=3==7c=64;58?l1b290/?4;5779m7<2=021b;i4?:%1:1?113g928774;h5`>5<#;0?1;;5a3869e>=nj<i1<7*<948a1c=i;0>1?65`a083>>if83:17d=n3;29?jg52900e>j8:188k<`=831b5n4?::k2gf<722c2n7>5;h;f>5<<a:n=6=44i8f94?=n;h?1<75f15294?"41<0:?k5a38694>=n9:o1<7*<94827c=i;0>1=65f12f94?"41<0:?k5a38696>=n9:i1<7*<94827c=i;0>1?65fb4`94?"41<0i9l5a38694>=nj<31<7*<948a1d=i;0>1=65fb4:94?"41<0i9l5a38696>=h9??1<7*<948221=i;0>1<65`17194?"41<0::95a38695>=h9?;1<7*<948221=i;0>1>65`17294?"41<0::95a38697>=h9<l1<7*<948221=i;0>1865`14g94?"41<0::95a38691>=h9<n1<7*<948221=i;0>1:65`14a94?"41<0::95a38693>=h9<h1<7*<948221=i;0>1465`14c94?"41<0::95a3869=>=h9<31<7*<948221=i;0>1m65`14:94?"41<0::95a3869f>=h9<<1<7*<948221=i;0>1o65`14794?"41<0::95a3869`>=h9<>1<7*<948221=i;0>1i65`14194?"41<0::95a3869b>=h9k<1<7*<9482f0=i;0>1<65`1c694?"41<0:n85a38695>=h9ko1<7*<9482fa=i;0>1<65`1ca94?"41<0:ni5a38695>=h9kh1<7*<9482fa=i;0>1>65`1cc94?"41<0:ni5a38697>=n==0;6)=65;70?k5><3:07d;8:18'7<3==:1e?4:5c:9j13<72-9297;<;o1:0?b<3`?>6=4+387916=i;0>1i65f4e83>!5>=3?87c=64;d8?j7>03:1(>7::0;4?k5><3:07b?66;29 6?2283<7c=64;38?j7><3:1(>7::0;4?k5><3807b?63;29 6?2283<7c=64;18?j7>:3:1(>7::0;4?k5><3>07b?61;29 6?2283<7c=64;78?j7>83:1(>7::0;4?k5><3<07b?7f;29 6?2283<7c=64;58?j7?m3:1(>7::0;4?k5><3207b?7d;29 6?2283<7c=64;;8?j7?k3:1(>7::0;4?k5><3k07b?7b;29 6?2283<7c=64;`8?j7?13:1(>7::0;4?k5><3i07b?78;29 6?2283<7c=64;f8?j7??3:1(>7::0;4?k5><3o07b?76;29 6?2283<7c=64;d8?j7?=3:1(>7::0;4?k5><3;;76a>8583>!5>=3;2;6`<95825>=h9191<7*<9482=2=i;0>1=?54o0:1>5<#;0?1=494n2;7>45<3f;3=7>5$2;6>4?03g9287?;;:m2<5<72-9297?67:l0=1<6=21d=4h50;&0=0<61>1e?4:51798k4?b290/?4;51858j6?328=07b?6d;29 6?2283<7c=64;3;?>i61j0;6)=65;3:3>h41=0:565`18`94?"41<0:5:5a38695d=<g83j6=4+38795<1<f:3?6<l4;n3:=?6=,:3>6<78;o1:0?7d32e:584?:%1:1?7>?2d8594>d:9l5=g=83.8584>969m7<2=9l10c<9i:18'7<3=90=0b>7;:0d8?l10290/?4;5779m7<2=821b;o4?:%1:1?113g9287l4;h5b>5<#;0?1;;5a3869g>=n?00;6)=65;55?k5><3n07d97:18'7<3=??1e?4:5e:9j35<72-929799;o1:0?`<3`h=<7>5$2;6>g3a3g9287>4;h`6a?6=,:3>6o;i;o1:0?7<3`h>h7>5$2;6>g3a3g9287<4;hd2>5<#;0?1j=5a38694>=nmo0;6)=65;d3?k5><3;07dkk:18'7<3=n91e?4:52:9jaf<72-9297h?;o1:0?5<3`oi6=4+3879b5=i;0>1865fe`83>!5>=3l;7c=64;78?lc>290/?4;5f19m7<2=>21bi54?:%1:1?`73g928794;hg4>5<#;0?1j=5a3869<>=nm?0;6)=65;d3?k5><3307dk::18'7<3=n91e?4:5a:9ja1<72-9297h?;o1:0?d<3`o96=4+3879b5=i;0>1o65fe083>!5>=3l;7c=64;f8?lc7290/?4;5f19m7<2=m21bhk4?:%1:1?`73g9287h4;hff>5<#;0?1j=5a386955=<amn1<7*<948e4>h41=0:=65fdb83>!5>=3l;7c=64;31?>ocj3:1(>7::g28j6?328907djn:18'7<3=n91e?4:51598ma?=83.8584i0:l0=1<6=21bj54?:%1:1?`73g9287?9;:ke3?6=,:3>6k>4n2;7>41<3`l=6=4+3879b5=i;0>1=554ig794?"41<0m<6`<9582=>=nn=0;6)=65;d3?k5><3;j76gi3;29 6?22o:0b>7;:0`8?l`5290/?4;5f19m7<2=9j10ehk50;&0=0<a82d8594>d:9ja6<72-9297h?;o1:0?7b32wi9l=50;a;>5<7sAh?m6*;3080=f=]1>0hw>>53381e?4e2:>1?<4<5;36>7e=9?08?7<6:|l23`<73g;i=7>4$2f6>0=#;9=1:6*<5985?!4b<3<0(?h;:79'6ab=>2.9h=49;%0f`?0<,;l;6;5+34;92>"4:j0=7)=92;78 6372?1/?<856:&057<13-9>?784$272>3=#;;21:6*<0g85?!57l3<0(>==:79'76b=>2.8=849;%107?0<,:?m6;5+2da92>"4;80=7)=>0;48 7b22?1/?=856:&1b4<13-8mo784$264>3=#;;>1:6*<0985?!4a13<0(?j=:79'74e=>2.89;49;%130?0<,;o=6;5+30g92>"5m80=7)=;6;48 7ca2?1/?;?55:&072<13-9>h784$23a>3=#:oo1:6*=ec85?!54>3<0(>=;:79'76g=>2.88i49;%0ee?0<,;oj6;5+33492>"4<80=7)<j7;48 7`a2?1/?>656:&1b7<13-8m?784$22a>3=#:l?1:6*=fe85?!5183<0(><<:79'6ag=>2.8><49;%0g0?0<,:;36;5+34g92>"5l?0=7)=<5;48 67>2?1/>ih56:&00<<13-9?n784$3gf>3=#;9?1:6*<1g85?!4aj3<0(?j>:79'6ac=>2.8<n49;%16f?0<,:8<6;5+35092>"5n?0=7)=>d;48 62?2?1/?9>56:&001<13-98o784$27b>3=#;::1:6*<4485?!52k3<0(>?<:79'74g=>2.8>h49;%0e<?0<,::n6;5+2e192>"4<j0=7)==2;48 6b32<1/?9h56:&1b0<13-995784$220>3=#:mi1:6*=d685?!5583<0(?jm:79'715=>2.9j:49;%10=?0<,;n36;5+34592>"4:<0=7)=:5;48 64c2?1/?<956:&1`<<13-9?m784$22:>3=#;;l1:6*<2`85?!57:3<0(>?;:79'75g=>2.88h49;%125?0<,:9i6;5+2d192>"4==0=7)<j2;48 65b2?1/?=>56:&06g<13-8n5784$3g;>3=#;?91?4>4$2;g>6?73-92i7=60:l0e5<6:2d8m<4=4:&0f6<><2.8n94<b09'704=>2.8?k49;%`5f?d1i2.i:n4m6`9mf3b=9;1en;k5259'757=>2co47>5$2;6>c6<f:3?6<h4;h`63?6=,:3>6o;n;o1:0?5<3`k36=44i`c94?=n9jk1<75f13194?"41<0:>?5a38694>=n9;;1<7*<948267=i;0>1=65f10d94?"41<0:>?5a38696>=n98o1<7*<948267=i;0>1?65f10f94?"41<0:>?5a38690>=n98i1<7*<948267=i;0>1965f10`94?"41<0:>?5a38692>=n98k1<7*<948267=i;0>1;65f10;94?"41<0:>?5a3869<>=n9821<7*<948267=i;0>1565f10594?"41<0:>?5a3869e>=n98<1<7*<948267=i;0>1n65f10694?"41<0:>?5a3869g>=n9891<7*<948267=i;0>1h65f10094?"41<0:>?5a3869a>=n98;1<7*<948267=i;0>1j65f10294?"41<0:>?5a386955=<a8:m6=4+3879574<f:3?6<?4;h33a?6=,:3>6<<=;o1:0?7532c:<i4?:%1:1?75:2d8594>3:9j55e=83.8584>239m7<2=9=10e<>m:18'7<3=9;80b>7;:078?l75i3:1(>7::001?k5><3;=76g>2883>!5>=3;9>6`<95823>=n9;21<7*<948267=i;0>1=554i004>5<#;0?1=?<4n2;7>4?<3`;9:7>5$2;6>4453g9287?n;:k260<72-9297?=2:l0=1<6j21b=?:50;&0=0<6:;1e?4:51b98m447290/?4;51308j6?328n07d?>5;29 6?228897c=64;3f?>o68h0;6)=65;316>h41=0:j65`14094?"41<0::95a386955=<g8?:6=4+3879532<f:3?6<?4;n364?6=,:3>6<8;;o1:0?7532e:8k4?:%1:1?71<2d8594>3:9l51c=83.8584>659m7<2=9=10c<:k:18'7<3=9?>0b>7;:078?j71k3:1(>7::047?k5><3;=76a>6c83>!5>=3;=86`<95823>=h9?k1<7*<948221=i;0>1=554o04:>5<#;0?1=;:4n2;7>4?<3f;=47>5$2;6>4033g9287?n;:m222<72-9297?94:l0=1<6j21d=;850;&0=0<6>=1e?4:51b98k405290/?4;51768j6?328n07b?:7;29 6?228<?7c=64;3f?>i6<j0;6)=65;350>h41=0:j65`1c194?"41<0:n85a38696>=h9k81<7*<9482f0=i;0>1?65f15:94?"41<0:8:5a38694>=n9=<1<7*<948202=i;0>1=65f15794?"41<0:8:5a38696>=n9=>1<7*<948202=i;0>1?65f5383>!5>=3?87c=64;38?l36290/?4;5529m7<2=:21b9=4?:%1:1?343g9287=4;h6e>5<#;0?19>5a38690>=n<l0;6)=65;70?k5><3?07d;k:18'7<3==:1e?4:56:9j1f<72-9297;<;o1:0?1<3`?i6=4+387916=i;0>1465f5`83>!5>=3?87c=64;;8?l3>290/?4;5529m7<2=i21b954?:%1:1?343g9287l4;h56>5<#;0?1;;5a38695>=n?=0;6)=65;55?k5><3807d9<:18'7<3=??1e?4:53:9j37<72-929799;o1:0?2<3`=:6=4+387933=i;0>1965f8183>!5>=3==7c=64;48?l1a290/?4;5779m7<2=?21b;h4?:%1:1?113g928764;h5g>5<#;0?1;;5a3869=>=n?j0;6)=65;55?k5><3k07dl:c;29 6?22k?m7c=64;18?jg62900cl>50;9j7d5=831dm?4?::k0`2<722e2j7>5;h;`>5<<a8ih6=44i8`94?=n1l0;66g<d783>>o>l3:17d=n5;29?l7383:1(>7::01e?k5><3:07d?<e;29 6?2289m7c=64;38?l74l3:1(>7::01e?k5><3807d?<c;29 6?2289m7c=64;18?ld2j3:1(>7::c7b?k5><3:07dl:9;29 6?22k?j7c=64;38?ld203:1(>7::c7b?k5><3807b?95;29 6?228<?7c=64;28?j71;3:1(>7::047?k5><3;07b?91;29 6?228<?7c=64;08?j7183:1(>7::047?k5><3907b?:f;29 6?228<?7c=64;68?j72m3:1(>7::047?k5><3?07b?:d;29 6?228<?7c=64;48?j72k3:1(>7::047?k5><3=07b?:b;29 6?228<?7c=64;:8?j72i3:1(>7::047?k5><3307b?:9;29 6?228<?7c=64;c8?j7203:1(>7::047?k5><3h07b?:6;29 6?228<?7c=64;a8?j72=3:1(>7::047?k5><3n07b?:4;29 6?228<?7c=64;g8?j72;3:1(>7::047?k5><3l07b?m6;29 6?228h>7c=64;28?j7e<3:1(>7::0`6?k5><3;07b?me;29 6?228ho7c=64;28?j7ek3:1(>7::0`g?k5><3;07b?mb;29 6?228ho7c=64;08?j7ei3:1(>7::0`g?k5><3907d;;:18'7<3==:1e?4:50:9j12<72-9297;<;o1:0?e<3`?=6=4+387916=i;0>1h65f5483>!5>=3?87c=64;g8?l2c290/?4;5529m7<2=n21d=4650;&0=0<61>1e?4:50:9l5<0=83.8584>969m7<2=921d=4:50;&0=0<61>1e?4:52:9l5<5=83.8584>969m7<2=;21d=4<50;&0=0<61>1e?4:54:9l5<7=83.8584>969m7<2==21d=4>50;&0=0<61>1e?4:56:9l5=`=83.8584>969m7<2=?21d=5k50;&0=0<61>1e?4:58:9l5=b=83.8584>969m7<2=121d=5m50;&0=0<61>1e?4:5a:9l5=d=83.8584>969m7<2=j21d=5750;&0=0<61>1e?4:5c:9l5=>=83.8584>969m7<2=l21d=5950;&0=0<61>1e?4:5e:9l5=0=83.8584>969m7<2=n21d=5;50;&0=0<61>1e?4:51198k4>3290/?4;51858j6?328;07b?73;29 6?2283<7c=64;31?>i60;0;6)=65;3:3>h41=0:?65`19394?"41<0:5:5a386951=<g82;6=4+38795<1<f:3?6<;4;n3:b?6=,:3>6<78;o1:0?7132e:5h4?:%1:1?7>?2d8594>7:9l5<b=83.8584>969m7<2=9110c<7l:18'7<3=90=0b>7;:0;8?j7>j3:1(>7::0;4?k5><3;j76a>9`83>!5>=3;2;6`<9582f>=h9031<7*<9482=2=i;0>1=n54o0;6>5<#;0?1=494n2;7>4b<3f;3m7>5$2;6>4?03g9287?j;:m23c<72-9297?67:l0=1<6n21b;:4?:%1:1?113g9287>4;h5a>5<#;0?1;;5a3869f>=n?h0;6)=65;55?k5><3i07d96:18'7<3=??1e?4:5d:9j3=<72-929799;o1:0?c<3`=;6=4+387933=i;0>1j65fb7294?"41<0i9k5a38694>=nj<o1<7*<948a1c=i;0>1=65fb4f94?"41<0i9k5a38696>=nn80;6)=65;d3?k5><3:07dki:18'7<3=n91e?4:51:9jaa<72-9297h?;o1:0?4<3`oh6=4+3879b5=i;0>1?65fec83>!5>=3l;7c=64;68?lcf290/?4;5f19m7<2==21bi44?:%1:1?`73g928784;hg;>5<#;0?1j=5a38693>=nm>0;6)=65;d3?k5><3207dk9:18'7<3=n91e?4:59:9ja0<72-9297h?;o1:0?g<3`o?6=4+3879b5=i;0>1n65fe383>!5>=3l;7c=64;a8?lc6290/?4;5f19m7<2=l21bi=4?:%1:1?`73g9287k4;hfe>5<#;0?1j=5a3869b>=nll0;6)=65;d3?k5><3;;76gkd;29 6?22o:0b>7;:038?lbd290/?4;5f19m7<2=9;10eil50;&0=0<a82d8594>3:9j`d<72-9297h?;o1:0?7332co57>5$2;6>c6<f:3?6<;4;hd;>5<#;0?1j=5a386953=<ao=1<7*<948e4>h41=0:;65ff783>!5>=3l;7c=64;3;?>oa=3:1(>7::g28j6?328307dh;:18'7<3=n91e?4:51`98mc5=83.8584i0:l0=1<6j21bj?4?:%1:1?`73g9287?l;:kfa?6=,:3>6k>4n2;7>4b<3`o86=4+3879b5=i;0>1=h54}rc4>5<59mqUm:52a`29===:ihh15552ac49===:ij;15552aba9===:im=15552ad09===:iln15552ag19===:io>15552a`39===:ih815552a`19===:ih>15552a`79===:ih<15552a`59===:ih215552a`;9===:ihk15552a`a9===:ihn15552a`g9===:ihl15552ac29===:ik;15552ac09===:ik915552ac69===:ik?15552ac59===:ik215552ac;9===:ikk15552ac`9===:iki15552acf9===:iko15552acd9===:ij:15552ab09===:ij915552ab69===:ij?15552ab49===:ij=15552ab:9===:ij315552abc9===:ijh15552abf9===:ijo15552abd9===:im:15552ae39===:im815552ae19===:im>15552ae79===:im<15552ae:9===:im315552aec9===:imh15552aea9===:imn15552aeg9===:iml15552ad29===:il;15552ad19===:il>15552ad79===:il<15552ad59===:il215552ad;9===:ilk15552ad`9===:ili15552adg9===:ill15552ag29===:io;15552ag09===:0o>15552a619===:0o<155528gd9===:0ok155528g:9===:0on155524219===:<=31555244d9===:<>?1555249`9===:<h;155524c59===:<jn155524e;9===:<mh155524279===:<:=1555242;9===:<:h1555242f9===:<:l155524539===:<=9155524579===:<==1555245`9===:<=n1555245d9===:<<;155524419===:<<?155524459===:<<31555244`9===:<<n155524739===:<?9155524779===:<?=1555247;9===:<?h1555247f9===:<?l155524639===:<>9155524659===:<>31555246`9===:<>n1555246d9===:<1;155524919===:<1?155524959===:<131555249f9===:<1l155524839===:<09155524879===:<0=1555248;9===:<0h1555248f9===:<0l155524`19===:<h?155524`59===:<h3155524``9===:<hn155524`d9===:<k;155524c19===:<k?155524c;9===:<kh155524cf9===:<kl155524b39===:<j9155524b79===:<j=155524b;9===:<jh155524bd9===:<m;155524e19===:<m?155524e59===:<:81m:5245:9e2=:<<o1m:524669e2=:<1k1m:524`29e2=:<k<1m:524ba9e2=:<m21m:524ec9e2=:<:>1m:524249e2=:<:21m:5242c9e2=:<:i1m:5242g9e2=:<=:1m:524509e2=:<=>1m:524549e2=:<=k1m:5245a9e2=:<=o1m:524429e2=:<<81m:524469e2=:<<<1m:5244:9e2=:<<k1m:5244a9e2=:<?:1m:524709e2=:<?>1m:524749e2=:<?21m:5247c9e2=:<?i1m:5247g9e2=:<>:1m:524609e2=:<><1m:5246:9e2=:<>k1m:5246a9e2=:<>o1m:524929e2=:<181m:524969e2=:<1<1m:5249:9e2=:<1i1m:5249g9e2=:<0:1m:524809e2=:<0>1m:524849e2=:<021m:5248c9e2=:<0i1m:5248g9e2=:<h81m:524`69e2=:<h<1m:524`:9e2=:<hk1m:524`a9e2=:<ho1m:524c29e2=:<k81m:524c69e2=:<k21m:524cc9e2=:<ki1m:524cg9e2=:<j:1m:524b09e2=:<j>1m:524b49e2=:<j21m:524bc9e2=:<jo1m:524e29e2=:<m81m:524e69e2=:<m<1m:5297d9===:1?o1555297f9===:1?i1555297`9===:1?31555297:9===:1?=155529749===:1??155529769===:1?9155529709===:1?;155529729===:1<o1555294f9===:1<i1555294`9===:1<k1555294;9===:1<2155529459===:1<<155529479===:1<9155529409===:1<;155529429===:1=l1555295g9===:1=n1555295a9===:1=h1555295c9===:1=2155529559===:1=<155529579===:1=>155529519===:1=8155529539===:1=:1555292d9===:1:n1555292a9===:1:h1555292c9===:1:31555292:9===:1:=155529249===:1:?155529269===:1:8155529239===:1::1555293d9===:1;o1555293f9===:1;i1555293`9===:1;k1555293;9===:1;=155529349===:1;?155529369===:1;9155529309===:1;;155529329===:18l1555290g9===:1>;155529629===:1?k1555294d9===:1<>1555295;9===:1:o155529219===:1;21555290f9===:1j>155529b19===:1j8155529b39===:1j:155529cg9===:1kn155529ca9===:1kh155529cc9===:1k3155529c:9===:1k=155529c49===:1k?155529c19===:1k8155529c39===:1k:155529`d9===:1ho155529`f9===:1hi155529``9===:1hk155529`:9===:1h=155529`49===:1h?155529`69===:1h9155529`09===:1h;155529`29===:10l1555298f9===:10i1555298`9===:10k1555298;9===:102155529859===:10<155529879===:10>155529809===:10;155529829===:11l1555299g9===:11n1555299a9===:11h1555299c9===:113155529959===:11<155529979===:11>155529919===:118155529939===:11:1555296d9===:1>o1555296a9===:1>h1555296c9===:1>31555296:9===:1>=155529649===:1>?155529669===:1>9155529b49===:1j?155529cd9===:1k>155529`;9===:10o155529819===:1121555296f9===:1>8155529b59ef=:1891555291c9===:18>1mn5287:9===:0?3155528449===:0=?155528569===:0=9155528509===:0=;155528529===:0:l1555282g9===:0:n1555282a9===:00<155528879===:0081555284f9===:0<o1555284a9===:0?:1555284d9===:0;;155527g19===:?o>155527g79===:?o<155527g59===:?o2155527g;9===:?ok155528069===:08?155528019===:082155528049===:08=155528139===:098155528129===:09=155528119===:09>155528179===:09<155527e:9===:?m3155527e69===:>0o1555268d9===:?m<155527e59===:>ho155526b29===:>h:155526gd9===:>on155527109===:?9:155527179===:?991555271:9===:?9<1555271`9===:?931555271g9===:?9i155527039===:?9l155527069===:?88155527059===:?8?1555270c9===:?82155527849===:?091555279d9===:?1h155527959===:?191555276d9===:?>h155527659===:?>9155527409===:?=l1555275`9===:?==155527519===:?:l1555272`9===:?:=155527219===:?;l155527`79ef=:?h=1mn527`;9ef=:0?h1555287a9===:0mi155528479===:=h;1mo525`09ed=:=h91ml5rs`d94?04sWkm706ic;c4?8>a?3k<707l7;1g5>;>8?0j;636058b3>;>8<0j;6361580`4=:0<=1555284:9===:0mh155528739===:01o1555289d9===:01n155528bg9===:0jh155528b59===:0j9155528cd9===:0kh155528c59===:0k9155528`d9===:0hh1555280;9===:092155526e09e2=:>mk1m:526c09e2=:>k91m:526c69e2=:>k?1m:526b69e2=:>j?1m:526b49e2=:>j=1m:526`;9e2=:>hk1m:526e79e2=:>m<1m:526`09e2=:>h91m:526e`9e2=:>mi1m:526e19e2=:>li155526g19===:>o>155526g79===:>o<155526g59===:>o2155526g;9===:>ok155526g`9===:>ln155526dg9===:>ll155526g29===:>o;155526g09===:>oi1m:527`797a7<5>k<6>j>;<5b=?5c927>m=468:?6=c<>027>5h468:?6=a<>027>5n468:?6=g<>027>oh468:?6b7<>027>ih468:?6ad<>027>i;468:?6a7<>027>hh468:?6`d<>027>h;468:?6`7<>027>oo468:?620<>027>:?468:?61`<>027>9l468:?613<>027>9?468:?60`<>027>5<468:?6<`<>027>4l468:?6<3<>027>4?468:?63`<>027>m<4n9:?6e7<f027>m>4n8:pf5<72;qUn=5289c96fd<uzh:6=4={_`2?8>?i38hm6s|b383>0}Yj;164=65a59><5>=l?16;kh52b`89=>f2;ih7p}m3;293~Xe;273944>e49><0>=;0<015?6:`689=7>2m<015?=:3aa?8>?i38hh6s|b583>43|Vk>018o?:2;b?83>n392m63:9d80=d=:=0n1?4o4=4;`>6?f34?2n7=6a:?677<5kh169;h52b`890eb2:3j70;i2;1:e>;2ml085l525dc97<g<5<o=6>7n;<7f6?5>i27>hh4<9`9>1ag=;0k018j9:2;b?83c:392m63:cc80=d=:0?n1>no4}r`6>5<5sWh>7069d;0`f>{tj?0;6?uQb79><3b=:ji0q~l8:181[d0342=h7<ld:pf=<72;qUn55287f96fc<uzh26=4={_`:?8>1m38hm6s|b`83>0}Yjh164km5d79>=f1=;m801;kl:e489=>f2;in7p}mb;29f1}Yjk165;h538489<0b2:3=7079d;1:2>;>>j085;5297`97<0<50<26>79;<;5<?5>>272::4<979>=30=;0<0148::2;5?8?1<392:6366280=3=:1?81?484=842>6?1343=<7=66:?:1`<41?1658j538489<3d2:3=707:b;1:2>;>=h085;5294;97<0<50?36>79;<;63?5>>2729;4<979>=03=;0<014;<:2;5?8?2:392:6365080=3=:1<:1?484=86e>6?1343?i7=66:?:0a<41?1659m538489<2e2:3=707;a;1:2>;><1085;5295597<0<50>=6>79;<;71?5>>272894<979>=15=;0<014:=:2;5?8?39392:6364180=3=:1:l1?484=81g>6?13438o7=66:?:7g<41?165>o538489<5>2:3=707<8;1:2>;>;>085;5292497<0<509>6>79;<;00?5>>272??4<979>=67=;0<014=?:2;5?8?5n392:6362d80=3=:1;n1?484=80`>6?13439n7=66:?:6d<41?165?7538489<402:3=707=6;1:2>;>:<085;5293697<0<50886>79;<;16?5>>272><4<979>=76=;0<014?i:2;5?8?6m392:6367080=3=:1>:1?484=84b>6?1343>j7=66:?:11<41?16597538489<5b2:3=707<3;1:2>;>:1085;5290f97<0<50i?6>79;<;`7?5>>272o?4<979>=f7=;0<014m?:2;5?8?em392:636be80=3=:1ki1?484=8`a>6?1343im7=66:?:f<<41?165o6538489<d02:3=707m6;1:2>;>j<085;529c197<0<50h96>79;<;a5?5>>272n=4<979>=d`=;0<014oj:2;5?8?fl392:636ab80=3=:1hh1?484=8cb>6?1343j47=66:?:e2<41?165l8538489<g22:3=707n4;1:2>;>i:085;529`097<0<50k:6>79;<;b4?5>>2725k4<979>=<b=;0<0147l:2;5?8?>j392:6369`80=3=:1031?484=8;;>6?13432;7=66:?:=3<41?1654;538489<?32:3=70762;1:2>;>18085;5298297<0<502m6>79;<;;a?5>>2724i4<979>==e=;0<0146m:2;5?8??i392:6368880=3=:11=1?484=8:5>6?1343397=66:?:<1<41?1655=538489<>52:3=70771;1:2>;>09085;5296d97<0<50=n6>79;<;4g?5>>272;o4<979>=2g=;0<01496:2;5?8?00392:6367680=3=:1><1?484=856>6?1343<87=66:?:36<41?165n8538489<e22:3=707mf;1:2>;>j=085;529`;97<0<503n6>79;<;:7?5>>272454<979>=2b=;0<0149=:2;5?8?d?39o<636078b0>;>8=0j8636048b0>;>8>09oo5291:96fd<50;96?mm;<;20?5c8273;>4=cd9~wge=838pRom4=950>7ea3tyih7>52z\a`>;?>l09oo5rscg94?4|Vko0158j:3a`?xuen3:1>vPmf:?;2`<5km1vn>50;0xZf6<51<n6?mj;|q`5?6=:rTh=6377d81g`=z{j81<7<t^b089=1b2;im7p}l3;296~Xd;273494=cc9~wf2=838pRn:4=9:7>7ef3tyh97>52z\`1>;?0k09ol5rsb494?4|Vj<0156;:3a`?xud?3:1>vPl7:?;<1<5km1vn650;0xZf><51=n6?mm;|q`=?6=:rTh56377d81gd=z{jk1<7<t^bc89=1b2;ih7p}lc;296~Xdk273;h4=ce9~wfb=838pRnj4=7;`>6?63tyhi7>56z\`a>;?1:09ol5286196fd<51<m6?mm;<:;<?4di273;i4=c`9~wf`=83=pRnh4=942>d2<51<:6i84=9:f>a0<51386?mm;<:6f?4dj273;>4=c`9~wa6=83;2wSj?;<4:g?4dk27>m=4n4:?6=c<f<27>5h4n4:?6=a<f<27>5n4n4:?6=g<f<27>:84n4:?627<f<27>9h4n4:?61d<f<27>9;4n4:?617<f<27>8h4n4:?6=4<f<27>4h4n4:?6<d<f<27>4;4n4:?6<7<f<27>;h4n4:?;36<5kj169l?51b`890g528ij70;n3;3`e>{tl80;6?uQd09><25=:jn0q~j=:187[b5342mo7o;;<:e3?g3342387<le:p`6<72;hpRi=4=7f1>d2<5?nj6l:4=7`1>d2<5?h86l:4=7`7>d2<5?h>6l:4=7a7>d2<5?i>6l:4=7a5>d2<5?i<6l:4=7c:>d2<5?kj6l:4=7f6>d2<5?n=6l:4=7c1>d2<5?k86l:4=7fa>d2<5?nh6l:4=7f0>d2<5?oh6l:4=7d0>d2<5?l?6l:4=7d6>d2<5?l=6l:4=7d4>d2<5?l36l:4=7d:>d2<5?lj6l:4=7da>d2<5?oo6l:4=7gf>d2<5?om6l:4=7d3>d2<5?l:6l:4=7d1>d2<5?lh6l:4=6c0>7ee34=j87<lb:?4e0<4l916;l953e2892g>2:n;70674;0`b>{t;1<1<7h9{<`4a?7b=27jm=4<979>edd=;0<01ll9:2;5?8gd9392:63ncb80=3=:im=1?484=`g1>6?134knh7=66:?bb6<41?16mk:538489dg62:3=70on2;1:2>;fi:085;52a`697<0<5hk>6>79;<cb2?5>>27jm:4<979>ed>=;0<01lo6:2;5?8gfi392:63nab80=3=:ihn1?484=`cf>6?134kjj7=66:?bf5<41?16mo?538489dd52:3=70om3;1:2>;fj=085;52ac797<0<5hh<6>79;<ca<?5>>27jn44<979>egg=;0<01llm:2;5?8gek392:63nbe80=3=:iko1?484=``e>6?134kh<7=66:?bg7<41?16mn=538489de32:3=70ol5;1:2>;fk?085;52ab597<0<5hi36>79;<c`=?5>>27jol4<979>efd=;0<01lmk:2;5?8gdm392:63ncg80=3=:im:1?484=`f2>6?134ko>7=66:?b`6<41?16mi:538489db22:3=70ok6;1:2>;fl1085;52ae;97<0<5hnj6>79;<cgf?5>>27jhn4<979>eab=;0<01ljj:2;5?8gcn392:63ne180=3=:il;1?484=`g0>6?134kn87=66:?ba0<41?16mh8538489dc02:3=70oj8;1:2>;fm0085;52adc97<0<5hoi6>79;<cfg?5>>27jih4<979>e``=;0<01lh?:2;5?8ga9392:63nf380=3=:<:818>5245:906=:<<o18>52466906=:<1k18>524`2906=:<k<18>524ba906=:<m218>524ec906=:<:>18>52424906=:<:218>5242c906=:<:i18>5242g906=:<=:18>52450906=:<=>18>52454906=:<=k18>5245a906=:<=o18>52442906=:<<818>52446906=:<<<18>5244:906=:<<k18>5244a906=:<?:18>52470906=:<?>18>52474906=:<?218>5247c906=:<?i18>5247g906=:<>:18>52460906=:<><18>5246:906=:<>k18>5246a906=:<>o18>52492906=:<1818>52496906=:<1<18>5249:906=:<1i18>5249g906=:<0:18>52480906=:<0>18>52484906=:<0218>5248c906=:<0i18>5248g906=:<h818>524`6906=:<h<18>524`:906=:<hk18>524`a906=:<ho18>524c2906=:<k818>524c6906=:<k218>524cc906=:<ki18>524cg906=:<j:18>524b0906=:<j>18>524b4906=:<j218>524bc906=:<jo18>524e2906=:<m818>524e6906=:<m<18>528bc9`2=:0j<1h:528b09`2=:0ko1h:528cc9`2=:0k<1h:528c09`2=:0ho1h:528`c9`2=:0;;1h;5283397<0<51896?mn;<:16?4dk27=m=4<9`9>3<4=l>16;5k5d69>3=g=l>16;585d69>3=4=l>16;:k5d69>32g=l>16;:85d69>324=l>16;9k5d69>31g=l>16;985d69>314=l>16;>k5d69>36g=l>16;>85d69>364=l>16;?k5d69>1c7=l>169hj5d69>1`?=l>169h;5d69>1`7=l>169ij5d69>1a?=l>169i;5d69>1a7=l>169no5d69>137=l>1698j5d69>10?=l>1698;5d69>107=l>1699j5d69>1=b=l>169575d69>1=3=l>1695?5d69>12b=l>169l?5120890g6289;70;n1;31b>;2i80:8o525`39f0><5<k:6o;8;<7b5?5fi27>m<4<ac9>1d7=;hi018o>:2cg?83f:3h>;63:a380`2=:=h81?i84=4c1>g3e34?j>7l:9:?6e7<e=1169l=5b45890g42:n<70;n3;1g2>;2i:0i9o525`19f0?<5<k86o;7;|q0<2<72;q645752ba89=>02:3:7p}<8983>7}:0131>nk4=9:;>6?63ty8444?:3y><26=;0;0158i:3ae?xu40h0;6?u289497<7<51236?mi;|q0<g<72;q645;538389=>02;in7p}<8b83>7}:0?o1?4?4=94g>7ea3ty8hl4?:3y]7ag<5hk;6i84}r1gf?6=:rT8ho52a`39`3=z{:nh6=4={_1gg>;fi;0o:6s|3ef94?4|V:no70on3;f5?xu4ll0;6?uQ3eg89dg32m<0q~=kf;296~X4lo16ml;5d79~w6c72909wS=j0:?be3<c>2wx?h?50;0xZ6c634kj;7j9;|q0a7<72;qU?h<4=`c;>a0<uz9n?7>52z\0a6=:ih31h;5rs2g7>5<5sW9n863na`8g2>{t;l?1<7<t^2g6?8gfj3n=7p}<e783>7}Y;l<01lol:e48yv5b?3:1>vP<e69>edb=l?1v>k7:181[5b027jmh4k6:p7`?=838pR>k6;<cbb?b13ty8il4?:3y]7`g<5hh;6i84}r1ff?6=:rT8io52ac39`3=z{:oh6=4={_1fg>;fj;0o:6s|3df94?4|V:oo70om3;f5?xu4ml0;6?uQ3dg89dd32m<0q~=jf;296~X4mo16mo;5d79~w6`72909wS=i0:?bf3<c>2wx?k?50;0xZ6`634ki;7j9;|q0b7<72;qU?k<4=``;>a0<uz9m?7>52z\0b6=:ik31h;5rs2d7>5<5sW9m863nb`8g2>{t;o?1<7<t^2d6?8gej3n=7p}<f783>7}Y;o<01lll:e48yv5a?3:1>vP<f69>egb=l?1v>h7:181[5a027jnh4k6:p7c?=838pR>h6;<cab?b13ty8jl4?:3y]7cg<5hi;6i84}r1ef?6=:rT8jo52ab39`3=z{:lh6=4={_1eg>;fk;0o:6s|3gf94?4|V:lo70ol3;f5?xu4nl0;6?uQ3gg89de32m<0q~=if;296~X4no16mn;5d79~w1672909wS:?0:?bg3<c>2wx8=?50;0xZ16634kh;7j9;|q747<72;qU8=<4=`a;>a0<uz>;?7>52z\746=:ij31h;5rs527>5<5sW>;863nc`8g2>{t<9?1<7<t^526?8gdj3n=7p};0783>7}Y<9<01lml:e48yv27?3:1>vP;069>efb=l?1v9>7:181[27027joh4k6:p05?=838pR9>6;<c`b?b13ty?<l4?:3y]05g<5hn;6i84}r63f?6=:rT?<o52ae39`3=z{=:h6=4={_63g>;fl;0o:6s|41f94?4|V=:o70ok3;f5?xu38l0;6?uQ41g89db32m<0q~:?f;296~X38o16mi;5d79~w1772909wS:>0:?b`3<c>2wx8<?50;0xZ17634ko;7j9;|q757<72;qU8<<4=`f;>a0<uz>:?7>52z\756=:im31h;5rs537>5<5sW>:863nd`8g2>{t<8?1<7<t^536?8gcj3n=7p};1783>7}Y<8<01ljl:e48yv26?3:1>vP;169>eab=l?1v9?7:181[26027jhh4k6:p04?=838pR9?6;<cgb?b13ty?=l4?:3y]04g<5ho;6i84}r62f?6=:rT?=o52ad39`3=z{=;h6=4={_62g>;fm;0o:6s|40f94?4|V=;o70oj3;f5?xu39l0;6?uQ40g89dc32m<0q~:>f;296~X39o16mh;5d79~w1472909wS:=0:?ba3<c>2wx8??50;0xZ14634kn;7j9;|q767<72;qU8?<4=`g;>a0<uz>9?7>52z\766=:il31h;5rs507>5<5sW>9863ne`8g2>{t<;?1<7<t^506?8gbj3n=7p};2783>7}Y<;<01lkl:e48yv25?3:1>vP;269>e`b=l?1v9<7:181[25027jih4k6:p07?=838pR9<6;<cfb?b13ty?>l4?:3y]07g<5hl;6i84}r61f?6=:rT?>o52ag39`3=z{=8o6=4={_61`>;fn;0o:6s|43g94?4|V=8n70oi3;f5?xu3:o0;6?uQ43d89d`32m<0q~:kc;296~;3;:0o:63;3380=2=z{=no6=4={<601?b134>887=67:p0ac=838p19=8:e4891512:3<7p};dg83>7}:<:31h;5242:97<1<uz>n<7>52z?77g<c>27??l4<969~w1c62909w0:<d;f5?824k392;6s|4d094?4|5=9m6i84=51f>6?03ty?i>4?:3y>017=l?1689>53858yv2b<3:1>v3;428g2>;3<;085:5rs5g6>5<5s4>?97j9;<670?5>?2wx8h850;0x91202m<019:9:2;4?xu3m>0;6?u245;9`3=:<=21?494}r6f<?6=:r7?8o4k6:?70d<41>1v9k6:181823l3n=70:;c;1:3>{t<lk1<7<t=56e>a0<5=>n6>78;|q7ag<72;q688?5d79>006=;0=0q~:jc;296~;3=:0o:63;5380=2=z{=oo6=4={<661?b134>>87=67:p0`c=838p19;8:e4891312:3<7p};eg83>7}:<<31h;5244:97<1<uz>m<7>52z?71g<c>27?9l4<969~w1`62909w0::d;f5?822k392;6s|4g094?4|5=?m6i84=57f>6?03ty?j>4?:3y>037=l?168;>53858yv2a<3:1>v3;628g2>;3>;085:5rs5d6>5<5s4>=97j9;<650?5>?2wx8k850;0x91002m<01989:2;4?xu3n>0;6?u247;9`3=:<?21?494}r6e<?6=:r7?:o4k6:?72d<41>1v9h6:181821l3n=70:9c;1:3>{t<ok1<7<t=54e>a0<5=<n6>78;|q7bg<72;q68:?5d79>026=;0=0q~:ic;296~;3?:0o:63;7380=2=z{=lo6=4={<641?b134><87=67:p0cc=838p1998:e4891112:3<7p};fg83>7}:<>31h;5246:97<1<uz?;<7>52z?73g<c>27?;l4<969~w0662909w0:8d;f5?820k392;6s|51094?4|5==m6i84=55f>6?03ty><>4?:3y>0=7=l?1685>53858yv37<3:1>v3;828g2>;30;085:5rs426>5<5s4>397j9;<6;0?5>?2wx9=850;0x91>02m<01969:2;4?xu28>0;6?u249;9`3=:<121?494}r73<?6=:r7?4o4k6:?7<d<41>1v8>6:18182?l3n=70:7c;1:3>{t=9k1<7<t=5:e>a0<5=2n6>78;|q64g<72;q684?5d79>0<6=;0=0q~;?c;296~;31:0o:63;9380=2=z{<:o6=4={<6:1?b134>287=67:p15c=838p1978:e4891?12:3<7p}:0g83>7}:<031h;5248:97<1<uz?:<7>52z?7=g<c>27?5l4<969~w0762909w0:6d;f5?82>k392;6s|50094?4|5=3m6i84=5;f>6?03ty>=>4?:3y>0d7=l?168l>53858yv36<3:1>v3;a28g2>;3i;085:5rs436>5<5s4>j97j9;<6b0?5>?2wx9<850;0x91g02m<019o9:2;4?xu29>0;6?u24`;9`3=:<h21?494}r72<?6=:r7?mo4k6:?7ed<41>1v8?6:18182fl3n=70:nc;1:3>{t=8k1<7<t=5ce>a0<5=kn6>78;|q65g<72;q68o?5d79>0g6=;0=0q~;>c;296~;3j:0o:63;b380=2=z{<;o6=4={<6a1?b134>i87=67:p14c=838p19l8:e4891d12:3<7p}:1g83>7}:<k31h;524c:97<1<uz?9<7>52z?7fg<c>27?nl4<969~w0462909w0:md;f5?82ek392;6s|53094?4|5=hm6i84=5`f>6?03ty>>>4?:3y>0f7=l?168n>53858yv35<3:1>v3;c28g2>;3k;085:5rs406>5<5s4>h97j9;<6`0?5>?2wx9?850;0x91e02m<019m9:2;4?xu2:>0;6?u24b;9`3=:<j21?494}r71<?6=:r7?oo4k6:?7gd<41>1v8<6:18182dl3n=70:lc;1:3>{t=;k1<7<t=5ae>a0<5=in6>78;|q66g<72;q68i?5d79>0a6=;0=0q~;=c;296~;3l:0o:63;d380=2=z{<8o6=4={<6g1?b134>o87=67:p17c=838p19j8:e4891b12:3<7p}:2g83>7}:<m31h;524e:97<1<uz?8<7>52z?7`g<c>27?hl4<969~w0512908w0;<4;0`e>;2<l085:5255d96fg<uz?8;7>53z?671<5kk1698<5385890342;ij7p}:3983>6}:=:>1>nm4=475>6?034?>;7<la:p16?=839p18=;:3ag?832i392;63:5c81gd=z{<9j6=4<{<700?4dm27>9h4<969>10`=:jk0q~;<b;297~;2;=09ok5257097<1<5<<86?mn;|q67f<72:q69>;52bc890022:3<70;96;0`e>{t=:n1<76t=44e>6?634?=97=6a:?627<41h1698k538c8903f2:3j70;:6;1:e>;2=;085l5255g97<g<uz?8i7>52z?676<5kh169>:53838yv34n3:1>v3:3281gg=:=:?1?4?4}r774?6=;r7>9<4n6:?611<f>27>8i4<769~w0262908w0;:5;c5?83203k=70;:1;143>{t==81<7=t=47:>d0<5<?h6l84=476>6103ty>8>4?:2y>10b=i?169;>5a79>10?=;>=0q~;;4;297~;2>80j:63:658b2>;2=m08;:5rs466>5<5s4?=;7o9;<755?50?2wx99850;0x902b2m<018;?:2;2?xu2<>0;6?u25409`3=:=<>1?4?4}r77<?6=:r7>9;4k6:?61=<4181v8:6:181832i3n=70;:c;1:5>{t==k1<7<t=47f>a0<5<<;6>7>;|q60g<72;q69;<5d79>132=;0;0q~;;c;296~;2><0o:63:6680=4=z{<<36=4<{<77b?5>927>8i4<b19>106=;><0q~;99;297~;2=:085<5254397g6<5<??6>99;|q62d<72:q69895383890322:h;70;:8;142>{t=?h1<7=t=47a>6?634?>57=m0:?61f<4??1v88l:180832n392=63:5e80f5=:=?:1?:84}r75`?6=;r7>:>4<909>137=;k:0188;:255?xu2>l0;6?u257497<7<5<<<6>99;|q634<72>q694o5383890?62:3j70;7e;1:e>;20h085l5259497<g<5<296>7n;<74a?5>i2wx9:<50;1x90>62h<0186;:`48901c2:=<7p}:7283>6}:=1?1m;5259:9e3=:=1;1?:94}r740?6=;r7>444n6:?6<f<f>27>484<769~w0122908w0;7d;c5?83>83k=70;79;143>{t=><1<7<t=4;0>d0<5<2o6>98;|q632<72;q69:k5d79>1=6=;0;0q~;88;296~;20;0o:63:8580=4=z{<=26=4={<7;2?b134?347=61:p12g=838p186n:e4890>d2:3:7p}:7c83>7}:=1o1h;5258297<7<uz?<o7>52z?6=4<c>27>5>4<909~w0?32908w0;8f;1:5>;2?m08n=525929720<uz?297>53z?6<6<4181695?53c2890>32:==7p}:9783>6}:=1=1?4?4=4:6>6d734?347=86:p1<1=839p186m:2;2?83?139i<63:8b8033=z{<336=4<{<7;b?5>927>4i4<b19>1<6=;><0q~;69;296~;21;085<525819720<uz?j87>52z?6e1<418169o?52bg8yv3f=3:1>v3:a480=4=:=k;1>nj4}r7b2?6=:r7>m;4<909>1g7=:jh0q~;n7;296~;2i>085<525c196fc<uz?j47>52z?6e=<418169o?52bd8yv3f13:1>v3:a880=4=:=k91>nj4}r7be?6=:r7>ml4<909>1g5=:jh0q~;nb;296~;2ik085<525c696fc<uz?jo7>52z?6ef<418169o=52bd8yv3fl3:1>v3:ae80=4=:=k>1>nj4}r7ba?6=:r7>mh4<909>1g2=:jh0q~;nf;296~;2io085<525c696f`<uz?i<7>52z?6f5<41816:8752ba8yv3e93:1>v3:b080=4=:=k:1>nl4}r7a6?6=:r7>n?4<909>20?=:jh0q~;m3;296~;2j:085<525c296fg<uz?i87>52z?6f1<418169o<52bc8yv3e=3:1>v3:d18b2>;2n808;:5rs4`5>5<4s4?o=7o9;<7g0?g134?hm7=87:p1g1=839p18j::`4890b?2h<018j>:254?xu2j10;6>u25e;9e3=:=mi1m;525e79721<uz?i57>53z?6`a<f>27>i=4n6:?6`<<4?>1v8ln:18083b93k=70;j4;c5?83cl39<;6s|5c`94?5|5<o>6l84=4g;>d0<5<o:6>98;|q6ff<72:q69h75a79>1`e=i?169h;53658yv3el3:1?v3:ee8b2>;2n90j:63:e88032=z{<hn6=4<{<7e5?g134?m87o9;<7f`?50?2wx9oh50;0x90ee2m<018mk:2;2?xu2k90;6?u25bg9`3=:=m:1?4?4}r7`5?6=:r7>h?4k6:?6`1<4181v8m=:18183c>3n=70;k8;1:5>{t=j91<7<t=4fb>a0<5<nh6>7>;|q6g1<72;q69ik5d79>1`6=;0;0q~;l5;296~;2m;0o:63:e580=4=z{<i=6=4={<7f2?b134?n47=61:p1f1=838p18kn:e4890cd2:3:7p}:c983>7}:=lo1h;525g297<7<uz?h57>52z?6b7<c>27>j94<909~w0`22908w0;lc;1:5>;2kh08n=525bf9720<uz?m:7>52z?6gc<418169i>53648yv3a?3:1?v3:d280=4=:=m;1?o>4=4f7>6113ty>j54?:2y>1a1=;0;018j::2`3?83c039<:6s|5g;94?5|5<ni6>7>;<7g=?5e827>hn4<779~w0`f2908w0;kf;1:5>;2lm08n=525d29720<uz?mn7>53z?6a6<418169h?53c2890c32:==7p}:fb83>6}:=l=1?4?4=4g6>6d734?n47=86:p1cb=839p18km:2;2?83b139i<63:eb8033=z{<ln6=4<{<7fb?5>927>ii4<b19>1c6=;><0q~;if;297~;2n:085<525g397g6<5<l?6>99;|q545<72=q6:kj5385890g621n018o=:6a890g42>i0q~8?1;290~;089085:525`39<`=:=h81;i525`193a=z{?:96=4;{<537?5>?27>m<47f:?6e7<0m27>m>48e:p255=83>p1:>9:2;4?83f933;70;n2;5e?83f;3=m7p}90583>1}:?931?494=4c2><7<5<k965>4=4c0>=6<uz<;97>54z?44f<41>169l?5939>1d4=?8169l=5709~w361290?w09?f;1:3>;2i803963:a3846>;2i:0<>6s|61594?2|5>;96>78;<7b5?>134?j>79<;<7b7?143ty=<54?:5y>343=;0=018o>:95890g52>>018o<:668yv0713:18v381980=2=:=h;144525`0930=:=h91;85rs72b>5<4s4=o;7=67:?ae6<5kk169l<511c8yv07j3:1>v3;dc80=2=:=h81=?o4}r43g?6=:r7??84<969>1d4=99h0q~8?d;296~;3;>085:525`0955e<uz<;i7>52z?77<<41>169l<511f8yv07n3:1>v3;3c80=2=:=h81==k4}r424?6=:r7??i4<969>1d4=99l0q~8>1;296~;3;o085:525`09546<uz<:>7>52z?704<41>169l<51578yv06;3:1>v3;4280=2=:=h91==o4}r420?6=:r7?884<969>1d5=98?0q~8>5;296~;3;:085:525`09543<uz<::7>52z?702<41>169l=51328yv06?3:1>v3;4c80=2=:=h91=?:4}r42<?6=:r7?8i4<969>1d5=9;?0q~8>9;296~;3<o085:525`19570<uz<:m7>52z?714<41>169l=51358yv06j3:1>v3;5280=2=:=h91=?64}r42g?6=:r7?984<969>1d5=9=>0q~8>d;296~;3=>085:525`1957?<uz<:i7>52z?71<<41>169l=513c8yv06n3:1>v3;5c80=2=:=h91==l4}r414?6=:r7?844<969>1d4=9;:0q~8=1;296~;3=m085:525`1955e<uz<9>7>52z?724<41>169l=511f8yv05;3:1>v3;6280=2=:=h91==k4}r410?6=:r7?:84<969>1d5=99l0q~8=5;296~;3>>085:525`19546<uz<9:7>52z?72<<41>169l=51578yv05?3:1>v3;5g80=2=:=h81=?:4}r41<?6=:r7?;k4<969>1d4=98;0q~8=9;296~;308085:525`09544<uz<9m7>52z?7<6<41>169l<51018yv05j3:1>v3;8480=2=:=h81=<:4}r41g?6=:r7?4:4<969>1d4=98<0q~8=d;296~;3?<085:525`09573<uz<9i7>52z?7<<<41>169l<51058yv05n3:1>v3;8e80=2=:=h81=<64}r404?6=:r7?4k4<969>1d4=9830q~8<1;296~;318085:525`09510<uz<8>7>52z?7=6<41>169l<510c8yv04;3:1>v3;9480=2=:=h81=<l4}r400?6=:r7?5:4<969>1d4=98i0q~8<5;296~;310085:525`0954b<uz<8:7>52z?7=g<41>169l<510g8yv04?3:1>v3;9e80=2=:=h81=<h4}r40<?6=:r7?4o4<969>1d4=9;<0q~8<9;296~;31o085:525`09577<uz<8m7>52z?7e6<41>169l<51318yv04j3:1>v3;a480=2=:=h81=964}r40g?6=:r7?m:4<969>1d5=98;0q~8<d;296~;3i0085:525`19544<uz<8i7>52z?7eg<41>169l=51018yv04n3:1>v3;ae80=2=:=h91=<:4}r474?6=:r7?mk4<969>1d5=98<0q~8;1;296~;3j8085:525`19541<uz<?>7>52z?7f6<41>169l=510:8yv03;3:1>v3;a080=2=:=h81=?94}r470?6=:r7?n84<969>1d5=9830q~8;5;296~;3j0085:525`19510<uz<?:7>52z?7fg<41>169l=510c8yv03?3:1>v3;be80=2=:=h91=<l4}r47<?6=:r7?nk4<969>1d5=98i0q~8;9;296~;3k8085:525`1954b<uz<?m7>52z?7g6<41>169l=510g8yv03j3:1>v3;c480=2=:=h91=<h4}r47g?6=:r7?o:4<969>1d5=9;;0q~8;d;296~;3k0085:525`19575<uz<?i7>52z?7f2<41>169l<513:8yv03n3:1>v3;cc80=2=:=h91=964}r464?6=:r7?oi4<969>1d4=9=>0q~8:1;296~;3l0085:525`0957?<uz<>>7>5dz?5=c<41>169l?5b76890g62k<870;n1;`56>;2i80i:<525`09f0e<5<k96o8?;<7b6?d2m27>m?4m5e9>1d5=j<i018o<:c43?83f;3h>i63:a28a1a=z{??86=4k{<7:f?5>?27>m94=c`9>1d3=:jk018o9:3ab?83f038hm63:a681gd=:=h31>no4=4cb>7ef34?jo7<la:?6eg<5kh169lj52bc890gb2;ij70;nf;0`e>{t><>1<7jt=4;`>6?034?j87<lc:?6e0<5kj169l852ba890g?2;ih70;n7;0`g>;2i009on525`c96fe<5<kh6?ml;<7bf?4dk27>mi4=cb9>1dc=:ji018oi:3a`?xu1=<0;69u258f97<1<5<h:6?mn;<7a7?4di27>n94=c`9~w331290?w0;6e;1:3>;2j809on525c196fe<5<h?6?ml;|q512<72:q694h5385890d72:h;70;m2;1a4>{t><21<7<t=4c3>6?034<>57<la:p20g=83>p187m:e4890172;ij70;8e;1:3>;2?o09ol5rs77a>5<3s4?2o7j9;<744?4dj27>4?4<969>1=5=:jk0q~8:c;290~;21m0o:63:7181gf=:=1<1?494=4:4>7ef3ty=9i4?:5y>1<c=l?169:>52bf890>f2:3<70;7b;0`e>{t><o1<7:t=4;e>a0<5<=;6?mj;<7;a?5>?27>4k4=c`9~w33a290?w0;n0;f5?830838hj63:9080=2=:=081>no4}r454?6=:r7>??4<909>1<g=:jh0q~891;296~;2i>09oh525`0951e<uz<=>7>52z?6ed<5kk169l<517a8yv01;3:1>v3:a`81gc=:=h81=9j4}r450?6=:r7>mn4=cd9>1d4=9=o0q~895;296~;2ij09oi525`0951`<uz<=:7>52z?6ef<5kk169l<51428yv01?3:1>v3:ab81gc=:=h81=8?4}r45<?6=:r7>m94=cd9>1d4=9<80q~899;296~;2i=09oi525`095g5<uz<=m7>52z?6e1<5kk169l=515a8yv01j3:1>v3:a581gc=:=h91=894}r45g?6=:r7>m:4=ce9>1d4=9<=0q~89d;296~;2i<09oh525`19534<uz<=i7>52z?6e0<5km169l=51748yv01n3:1>v3:a481gg=:=h91=;94}r444?6=:r7>m84=cg9>1d5=9?20q~881;296~;2i?09oh525`1953?<uz<<>7>52z?6e3<5km169l=517c8yv00;3:1>v3:a781gg=:=h91=o<4}r440?6=:r7>m;4=cg9>1d5=9?h0q~885;296~;2i109oh525`1953e<uz<<:7>52z?6e=<5km169l=515f8yv00?3:1>v3:a681gg=:=h81=;<4}r44<?6=:r7>m54=cc9>1d5=9=o0q~889;296~;2i109ok525`1951`<uz<<m7>52z?6eg<5kl169l=51428yv00j3:1>v3:ac81ga=:=h91=8?4}r44g?6=:r7>mo4=cc9>1d5=9<80q~88d;296~;2ik09ok525`195g5<uz<<i7>52z?6ea<5kl169l?517f8yv00n3:1>v3:ae81ga=:=h;1=:;4}r4;4?6=:r7>mi4=cc9>1d7=9><0q~871;296~;2im09ok525`39521<uz<3>7>52z?6e2<5ko169l<51748yv0?;3:1>v3:ad81g`=:=h;1=:64}r4;0?6=:r7>mh4=ce9>1d7=9>30q~875;296~;2il09oo525`3952g<uz<3:7>52z?6e`<5ko169l?516`8yv0??3:1>v3:ag81gg=:=h;1=o94}r4;<?6=:r7>m44=cd9>1d4=9?=0q~879;296~;2i009oi525`0953><uz<3m7>52z?6e<<5kk169l<517;8yv0?j3:1>v3:a881gc=:=h81=;o4}r4;g?6=:r7>ml4=cd9>1d4=9k80q~87d;296~;2ih09oi525`0953d<uz<3i7>55z?6gg<41>169nm52bc890g62?<018o=:4:890g42<20q~87f;291~;2kl085:525bd96fg<5<k:6;=4=4c1>04<5<k868<4}r4:4?6==r7>h?4<969>1a5=:jk018o>:75890g52<3018o<:4;8yv0>93:19v3:d780=2=:=m=1>no4=4c2>3><5<k968o4=4c0>0g<uz<2>7>55z?6`d<41>169il52bc890g62?3018o=:4`890g42<h0q~863;291~;2ll085:525ed96fg<5<k:6;o4=4c1>0e<5<k868m4}r4:0?6==r7>i?4<969>1`5=:jk018o>:7`890g52<n018o<:4f8yv0>=3:19v3:e780=2=:=l=1>no4=4c2>3e<5<k969k4=4c0>1c<uz<2:7>55z?6ad<41>169hl52bc890g62<l018o=:5d890g42=l0q~867;291~;2ml085:525dd96fg<5<k:6;>4=4c1>06<5<k868>4}r4:<?6==r7>j?4<969>1c5=:jk018o>:73890g52<;018o<:438yv0>13:1ov3:3080=4=:=jo1m9525g09e1=:=lo1m9525dc9e1=:=l<1m9525d09e1=:=mo1m9525ec9e1=:=m<1m9525e09e1=:=jh1m95rs7;b>5<3s4?8>7<lb:?674<5kh169>=53838900a2;ij7p}99c83>6}:=:;1>nl4=4;b>7ef34?<<7=61:p2<b=83>p1:j7:2;b?81c1392m638d580=d=:>h21?4?4}r4b0?6=:r7=m=4k6:?5e4<4181v;o::18180f:3n=708n3;1:=>{t>h<1<7<t=7c2>7ef34<j?7=67:p2d1=838p1;o>:3aa?80f:392;6s|6``94?4|5?k26i84=7cb>6?>3ty=mn4?:3y>2d>=:jk01;on:2;4?xu1im0;6?u26`:96fd<5?k26>78;|q5f3<72;q6:o?52bc893ga2:3:7p}9b683>7}:>k;1>nl4=7`3>6?63ty=n54?:3y>2dc=l?16:o?53838yv0e13:1>v39b58g2>;1j<08545rs7`b>5<5s4<i?7j9;<4a0?5>12wx:ol50;0x93d52m<01;l<:2;:?xu1jj0;6?u26`d96fg<5?h>6>78;|q5fa<72;q6:lh52b`893d32:3<7p}9bd83>7}:>k:1>no4=7`0>6?03ty=nk4?:3y>2g6=:jh01;l=:2;4?xu1k10;6?u26b196fg<5?i:6>7>;|q5g<<72;q6:n=52b`893e52:3:7p}9c`83>7}:>j:1h;526b197<7<uz<hn7>52z?5g3<c>27=o:4<989~w3ed2909w08l5;f5?80d>39256s|6bf94?4|5?i?6i84=7a6>6?>3ty=oh4?:3y>2f7=:jk01;m8:2;4?xu1ko0;6?u26b396fd<5?i=6>78;|q5`5<72;q6:n<52bc893e22:3<7p}9d083>7}:>j81>nl4=7a7>6?03ty=h:4?:3y>2a3=l?16:i8538;8yv0c03:1>v39d581gd=:>m<1?494}r4g=?6=:r7=h94=cc9>2a3=;0=0q~8kd;29g~;11l0o:639d380=2=:?<81m95275d9e1=:?=h1m9527559e1=:?=91m95272d9e1=:?:h1m9527259e1=:?:91m95273d9e1=z{?nn6=4={<5g0?b134=j97<l6:p2a`=838p1:j;:`6893b42:3<7p}9e183>f}:?m>1?494=7`1>1?<5?h86974=7`7>1?<5?h>6974=7a7>1?<5?i>6974=7a5>1?<5?i<6974=7c;>6d734<o87=m0:?5`6<312wx:h?50;`x93b32:3:709:2;1:e>;0<o085l5275`97<g<5>><6>7n;<577?5>i27<?k4<9`9>36d=;0k01:=8:2;b?814;392m6382g80=d=z{?o96=4={<4eb?b134<mi7=61:p2`5=838p1:>=:e4892662:3:7p}9e583>7}:?9?1h;5271697<7<uz<n97>52z?44=<c>27<<:4<909~w3c12909w09?b;f5?817i392=6s|6d594?4|5>:n6i84=62g>6?63ty=i54?:3y>347=l?16;<>53838yv0b13:1>v38158g2>;09:085<5rs7gb>5<5s4=:;7j9;<522?5>92wx:hl50;0x927f2m<01:?6:2;2?xu09k0;6>u27209e3=:?:?1m;5273g9721<uz=:o7>53z?473<f>27<?44n6:?477<4?>1v:?k:180814i3k=709<d;c5?814>39<;6s|70g94?5|5>9n6l84=662>d0<5>9j6>98;|q45c<72:q6;9<5a79>313=i?16;>k53658yv1583:1?v38478b2>;0<00j:638438032=z{>8:6=4<{<57e?g134=?h7o9;<572?50?2wx;?<50;1x922b2h<01:;>:`48922f2:=<7p}82283>7}:?<>1m;5275g9721<uz=987>52z?46c<c>27<?<4<909~w2422909w09<3;f5?814=392=6s|73494?4|5>9<6i84=61:>6?63ty<>:4?:3y>36d=l?16;>j53838yv1503:1>v383g8g2>;0<8085<5rs60:>5<5s4=??7j9;<571?5>92wx;?o50;0x92202m<01::6:2;2?xu0:k0;6?u275`9`3=:?=n1?4?4}r51g?6=:r7<8k4k6:?414<4181v:<k:181812:3n=709:4;1:5>{t?<?1<7=t=613>6?634=9i7=m0:?474<4??1v:;9:180814<392=6383380f5=:?:?1?:84}r563?6=;r7<?54<909>360=;k:01:=6:255?xu0=10;6>u272a97<7<5>9j6>l?;<50`?50>2wx;8750;1x92272:3:709<e;1a4>;0<808;;5rs67b>5<4s4=?87=61:?407<4j916;9;53648yv12j3:1?v384980=4=:?=<1?o>4=66:>6113ty<9n4?:2y>31e=;0;01::n:2`3?813l39<:6s|74f94?5|5>?;6>7>;<57a?5e827<9<4<779~w23b2909w09:3;1:5>;0==08;;5rs67e>5<4s4=<:7o9;<54=?g134=<>7=87:p336=839p1:9n:`48921c2h<01:99:254?xu0>80;6>u276g9e3=:?1;1m;5276c9721<uz==>7>53z?4<7<f>27<484n6:?43`<4?>1v:8<:18081?>3k=70979;c5?81?:39<;6s|77694?5|5>2j6l84=6:g>d0<5>2=6>98;|q420<72:q6;5k5a79>3<7=i?16;5o53658yv11>3:1?v38938b2>;01<0j:6388d8032=z{><<6=4={<5:<?g134=2>7=87:p33>=838p1:9<:e4892122:3:7p}86883>7}:?>=1h;5276;97<7<uz==m7>52z?43g<c>27<;i4<909~w20e2909w098f;f5?81?9392=6s|77a94?4|5>286i84=6:6>6?63ty<:i4?:3y>3=1=l?16;5753838yv11m3:1>v388c8g2>;00m085<5rs64e>5<5s4=3j7j9;<5:5?5>92wx;:>50;0x92?42m<01:7::2;2?xu0?80;6?u27849`3=:?021?4?4}r5:=?6=;r7<;94<909>324=;k:01:9::255?xu01h0;6>u276:97<7<5>==6>l?;<54=?50>2wx;4l50;1x921d2:3:7098a;1a4>;0?m08;;5rs6;`>5<4s4=3<7=61:?43`<4j916;5?53648yv1>l3:1?v388580=4=:?181?o>4=6:6>6113ty<5h4?:2y>3=>=;0;01:69:2`3?81?139<:6s|78d94?5|5>2h6>7>;<5;e?5e827<4i4<779~w2g72908w0960;1:5>;00l08n=527839720<uz=j=7>53z?4=1<41816;4<53c2892?22:==7p}8a383>7}:?0=1?4?4=6;;>6113ty<mo4?:3y>2ce=;0=01:o::2f1?xu0ij0;6?u27`196fg<5>k>6>j<;|q4ea<72;q6;l=5383892g02:n97p}8ad83>7}:?h>1>no4=6c4>6b43ty<mk4?:3y>3d2=;0;01:o6:2f1?xu0j90;6>u26g`97<1<5?oo6i84=63:>7ed3ty<n<4?:3y>2`b=;0=01;kj:e48yv1e:3:1>v39ed80=2=:>ll1h;5rs6`0>5<5s4<nj7=67:?5b5<c>2wx;o:50;0x93`72:3<708i1;f5?xu0j<0;6?u26g397<1<5?l96i84}r5a2?6=:r7=j?4<969>2ce=l?1v:l8:18080bk392;639f28g2>;1nl09on5rs6`;>5<4s4<m?7=67:?5b1<c>27<<<4=cb9~w2d>2908w08i4;1:3>;1n<0o:6380581gf=z{>hj6=4<{<4e1?5>?27=j;4k6:?442<5kj1v:lm:18080a>392;639f68g2>;08h09on5rs6``>5<4s4<m;7=67:?5b=<c>27<<i4=cb9~w2dc2908w08i8;1:3>;1n00o:6381181gf=z{>hn6=4<{<4e=?5>?27=jl4k6:?456<5kj1v:li:18080ai392;639fc8g2>;09?09on5rs6a3>5<5s4<mj7=67:?5ba<c>2wx;n?50;0x92652:3<709?0;f5?xu0k;0;6?u271797<1<5>:86i84}r5`7?6=:r7<<54<969>350=l?1v:m;:181817j392;638088g2>{t?j?1<7<t=62f>6?034=;o7j9;|q4g3<72;q6;<?53858926a2m<0q~9l7;296~;09=085:527009`3=z{>i36=4={<523?5>?27<=84k6:p3f?=838p1:?n:2;4?81603n=7p}8c`83>1}:>oo1>nl4=60e>6?034=8<7<la:?4e0<6m11v:mm:187817938hn6383280=2=:?:>1>no4=6c6>7303ty<on4?:5y>352=:jh01:=8:2;4?814038hm638a48132=z{>io6=4;{<533?4dj27<?o4<969>36e=:jk01:o::3:1?xu0kl0;69u271c96fd<5>9m6>78;<574?4di27<m84=8e9~w2ea290?w09?d;0`f>;0<:085:5275696fg<5>k>6?77;|q4`5<72=q6;<>52b`892202:3<709;8;0`e>;0i<09m>5rs6f2>5<3s4=:?7<lb:?40g<41>16;9m52bc892g22;kn7p}8d383>1}:?8<1>nl4=66e>6?034=><7<la:?4e0<5j01v:j<:187816138hn6385380=2=:?<91>no4=6c6>7e23ty<hl4?:cy>2ag=;0=01:79:`6892?42h>01:6i:`6892>e2h>01:68:`6892>42h>01:9i:`68921e2h>01:98:`6892142h>0q~9kb;296~;0l10o:638a681g3=z{>nh6=4={<5g<?g334<on7=67:p3ab=83?p1:j7:2;4?80e939i<639c280f5=:>h;1?o>4=7fa>1?<uz=oi7>52z?4`<<c>27<m44=c79~w2ba2909w09k9;c7?80ck392;6s|7d294?e|5>n26>78;<4a4?5e827=mk4<b19>2f4=;k:01;m>:2`3?80f13>2708na;6:?80c=3>2708k6;6:?80f:3>2708n3;6:?80ck3>27p}8e083>7}:>j=1h;527`;97a5<uz=n>7>52z?5f0<c>27=o94<989~w2c42909w08m2;1:=>;1l?0o:6s|7d694?4|5?nj6i84=7f6>6?>3ty<i84?:3y>2a4=l?16:io538:8yv1b>3:1>v39d380===:>hk1h;5rs6g4>5<5s4<j57=69:?5e6<c>2wx;h650;0x93g52:32708k3;f5?xu0m00;6?u26ea9`3=:>m91?474}r5fe?6=:r7=ho4k6:?5`f<4101v:km:18180>m392;6399g8g2>{t?li1<7<t=6f5>a0<5>n>6>7>;|q4aa<72;q6;i85385892b02m<0q~9ib;297~;?::09ol5280497<1<51;<6i84}r5eg?6=:r73><4<969><75=:jh0q~9id;29=~;0n:08n=527g697g6<5>l>6>l?;<5e2?5e827<j:4<b19>3c>=;k:01:h6:2`3?81ai39i<6372380=4=z{>ln6=4={<:16?4dl273>>4<909~w=6>2909w06?8;1:3>;?880o:6s|81c94?3|51:36lj4=922>db<51:96lj4=924>db<5>lm6>7>;|q;4g<72:q64=?538589=652m<015>?:e48yv>7k3:1>v370380=2=:09:1?4o4}r:3`?6=;r73<=4<969><51=i=164=95d79~w=6b2909w06?7;1:3>;?8:0o:6s|81d94?4|51:86>78;<:30?b13ty3==4?:3y><52=;0=015>::e48yv>693:1>v370780=2=:?ol1>no4}r:2e?6=:r73=44<969><42=l?1v5?m:1868>613ko706>4;cg?8>6=3ko706>8;cg?8>6:392=6s|80a94?5|51;?6>78;<:21?b1342:?7j9;|q;5a<72;q64<;538589=742:3j7p}71d83>6}:0891?494=93;>d2<51;36i84}r:2b?6=:r73=54<969><40=l?1v5<?:1818>6?392;6371381gd=z{18>6=4={<5e7?b1342987=61:p<70=838p157=:`f89=>c2:3<7p}72683>7}:0081?494=956>7ef3ty3>54?:3y><00=;0=0156l:3a`?xu?:00;6>u284597<1<51>=6?mm;<:41?4dl2wx4?o50;1x9=3?2:3<706;6;0`g>;??<09on5rs90a>5<4s42>57=67:?;03<5kh164:;52b`8yv>5k3:1?v37568g2>;?=10o:6374780=4=z{18o6=4;{<:5<?b1342>o7=67:?;25<f<273:=4k6:p<7c=83?p1587:2;4?8>113n=7067c;0`f>;?=h09oo5287c96fd<uz29j7>54z?;2<<41>1645m52bc89=3f2;ij7069a;0`e>{t0::1<7=t=9;5>d2<513>6l:4=97b>6?63ty38:4?:3y><6e=;0=0159n:3ab?xu?<10;6?u282f97<1<51=36?mi;|q;0<<72;q64>k538589=1>2;ii7p}74`83>7}:0:l1?494=954>7ee3ty38o4?:3y><16=;0=0159n:3aa?xu?<j0;6?u285397<1<51=36?mk;|q;0a<72;q649<538589=1>2;io7p}74d83>7}:0=91?494=954>7ef3ty38k4?:3y><12=;0=0159n:3a`?xu?=90;6?u285797<1<51=36?mn;|q;14<72kq649;5a59><12=i=1649=5a59><14=i=1649?5a59><16=i=164>h5a59><6c=i=164>j5a59><6e=i=1645m53838yv>2:3:1>v379480=2=:0>81>nl4}r:67?6=:r735;4<969><27=:jk0q~6:4;296~;?lk0o:6378880=4=z{1?>6=4<{<:61?5>?27im94=c`9><24=:ji0q~692;296~;?>8085:5284f9`3=z{1<86=4:{<:55?gc342>h7ok;<:6a?gc342=<7ok;<:6f?5>92wx4;:50;1x9=3c2:3<706:e;f5?8>2k3n=7p}76483>7}:0<o1?494=97`>6?f3ty3:;4?:3y><36=;0=015;i:e48yv>1?3:1>v375g80=2=:0<h1>no4}r:5f?6=:r73;94=c`9><3d=;0=0q~69c;297~;?>j085:52b`096fg<51=96?mn;|q;2a<72;q64;h52ba89=0c2:3:7p}76g83>7}:0?l1?4?4=95g>7ec3ty3;<4?:3y><27=;0;01599:3ag?xu??;0;6?u286097<7<51==6?mj;|q;36<72;q64:=538389=>e2;ih7p}77583>7}:0>>1?4?4=955>7ed3ty3;84?:3y><23=;0;01599:3ae?xu???0;6?u286497<7<51=o6?mj;|q;32<72;q64:9538389=1d2;ih7p}77983>7}:0>21?4?4=95`>7ea3ty3;44?:3y><2?=;0;0159l:3ag?xu??h0;6?u286c97<7<51=h6?mm;|q;3g<72;q64:l538389=1d2;in7p}77b83>7}:0>i1?4?4=95g>7ea3ty3;i4?:3y><2b=;0;01566:3ae?xu??l0;6?u286g97<7<512i6?mk;|q;3c<72;q64:h538389=>72;io7p}78183>7}:01:1?4?4=9::>7ef3ty34<4?:3y><=7=;0;0156<:3af?xu?0;0;6?u289097<7<51286?mi;|q;<6<72;q645=538389=>>2;io7p}78583>7}:01>1?4?4=9:a>7eb3ty34l4?:3y><=g=;0;0156m:3aa?xu?0k0;6?u289`97<7<51<m6?mj;|q;=5<72:q645k538589=>a2m<0156k:2;b?xu?180;6?u289d97<1<512o6i84}r::3?6=;r73mh4n6:?;f4<f>273ml4<769~w=??2908w06m2;c5?8>e=3k=706ne;143>{t0031<7=t=9`5>d0<51h26l84=9`1>6103ty35l4?:2y><gg=i?164oj5a79><g0=;>=0q~66b;297~;?jl0j:637c08b2>;?jh08;:5rs9;`>5<4s42h>7o9;<:`1?g1342ii7=87:p<<b=839p15m9:`489=e>2h<015m=:254?xu?1l0;6>u28bc9e3=:0jn1m;528b49721<uz22j7>52z?;`5<f>273ol4<769~w=g72909w06nb;f5?8>fl392=6s|8`394?4|51km6i84=9`2>6?63ty3m?4?:3y><g5=l?164o;53838yv>f;3:1>v37b68g2>;?j0085<5rs9c7>5<5s42in7j9;<:a`?5>92wx4l;50;0x9=da2m<015m>:2;2?xu?i?0;6?u28b19`3=:0j?1?4?4}r:b3?6=:r73o:4k6:?;g<<4181v5o7:1818>dj3n=706ld;1:5>{t0h31<7<t=9af>a0<51n;6>7>;|q;`4<72:q64lm538389=gf2:h;706nd;142>{t0m81<7=t=9`3>6?6342ji7=m0:?;f4<4??1v5j<:1808>e<392=637b380f5=:0k?1?:84}r:g0?6=;r73n54<909><g0=;k:015l6:255?xu?l<0;6>u28ca97<7<51hj6>l?;<:a`?50>2wx4i850;1x9=e72:3:706me;1a4>;?k808;;5rs9f4>5<4s42h87=61:?;g7<4j9164n;53648yv>c03:1?v37c980=4=:0j<1?o>4=9a:>6113ty3h44?:2y><fe=;0;015mn:2`3?8>dl39<:6s|8ec94?4|51im6>7>;<:g4?50>2wx4im50;1x9=bd2:3<70ln3;0`e>;??809oo5rs9fg>5<5s428=7=61:?;<7<5kk1v5jj:1818>4:392=6378081ga=z{1nm6=4<{<:07?5>92734;4=ce9><=1=:jk0q~6j0;296~;?;=085<5289396fe<uz2n=7>52z?;70<4181645>52ba8yv>b:3:1>v373780=4=:0191>nj4}r:f7?6=;r73?:4<909><=0=:ji01568:3ae?xu?m=0;6?u282:97<7<512;6?mj;|q;a0<72;q64>7538389=>72;im7p}7e783>7}:0:k1?4?4=9:1>7ec3ty3i:4?:2y><6d=;0;01569:3af?8>??38hh6s|8d:94?4|51386>7>;<::0?4d12wx4h750;`x9=?32:3:706le;1:e>;?kk085l528b597<g<51i86>7n;<:ab?5>i273no4<9`9><g1=;0k015l<:2;b?8>fn392m637ac80=d=z{1oj6=4>1z?;77<5kh164>l52bc89=5f2;ij706<9;0`e>;?;109ol5282596fg<519=6?mn;<:01?4di273?94=c`9><65=:jk015=>:3ab?8>fj392;637ab81gd=:0>i1>no4=952>7ed342<>7<ld:?;30<5kl1v5km:1822~;?;;09oo5282`96fd<519j6?mm;<:0=?4dj273?54=cc9><61=:jh015=9:3aa?8>4=38hn6373581gg=:0:91>nl4=912>7ee342jj7=67:?;f5<5kh164::52b`89=1?2;in70689;0`g>;??k09oi5286396fc<51=96?mi;<:41?4dn273;:4=ce9><2g=:jl0q~6jc;2950}:0:81>nm4=91a>7ed3428m7<lc:?;7<<5kj164>652ba89=502;ih706<6;0`g>;?;<09on5282696fe<51986?ml;<:05?4dk273n>4<969><g2=:jk01597:3a`?8>0138hm6377c81g`=:0>;1>nj4=951>7eb342<;7<lc:?;3d<5kl164:852b`8yv>bl3:1=<u282096fb<519i6?mk;<:0e?4dl273?44=ce9><6>=:jn015=8:3ag?8>4>38hh6373481ga=:0:>1>nj4=910>7ec3428=7<ld:?;f2<41>164o652bc89=1?2;ii7068b;0`f>;???09ol5286c96fb<uz2ni7>59z?;fg<41>164om52bc89=1e2;ih70670;0`e>;?0009oo5286296fe<512>6?mn;<:4`?4dj273454=ce9~w=ca290iw06mf;1:3>;?k909ol5286`96fg<51=m6?mn;<:;5?4dj2734?4=cb9><26=:jh0156::3aa?8>0l38ho6378281gf=:0121>nk4}r:e4?6=?r73o>4<969><f2=:jk0156?:3aa?8>?;38hm6377181ga=:01<1>nl4=9:4>7ee3ty3j<4?:8y><f1=;0=015m7:3ab?8>0n38hn6378081gd=:0181>no4=953>7ef3423:7<la:?;<2<5kj1645=52b`8yv>a:3:19v37cc80=2=:0ji1>no4=94e>7ec342397<ld:?;<=<5kk1v5h<:1868>dm392;637cg81gd=:0?l1>no4=9:6>7ed342347<lc:p<c?=838p15h7:e489=`02:3<7p}7fc83>7}:0ok1h;528g:97<1<uz2mi7>52z?;ba<c>273jn4<969~w<672909w06if;f5?8>al392;6s|91394?5|51l=6i84=9db>6?0342m97<la:p=54=838p15hl:2;;?8>a?3n=7p}60283>7}:1891h;5291697<1<uz3;57>52z?:4d<c>272<n4<909~w<6c2909w07?c;142>;>8k085<5rs82f>5<4s43;m7=67:?:4g<5kh165<:51d:8yv?7n3:1>v360`8b0>;>8<085:5rs833>5<3s43;:7:=;<;30?27343;97:>;<;20?4d>2wx5<?50;0x9<6f2:3j707?6;1:3>{t18<1<7<t=825>a0<50:<6>7>;|q:52<72;q65=8538:89<622m<0q~7>8;296~;>8=0o:6360480===z{0;26=4={<;30?5>0272<54=c`9~w<7f2909w07?8;1:5>;>9=08h?5rs83a>5<5s43:>7<la:?:51<4l:1v4?l:1818g0;3n=707l7;0`2>{t1j31<7=t=83g>6?0343<>7j9;<;`3?7b02wx5no50;1x9<7b2:3<70783;f5?8?d?38<>6s|9b`94?5|50;m6>78;<;40?b1343h;7<84:p=fe=839p14<?:2;4?8?0=3n=707l7;04<>{t1jn1<7=t=802>6?0343<:7j9;<;`3?40i2wx5nk50;1x9<452:3<70787;f5?8?d?38<h6s|9bd94?5|50886>78;<;4<?b1343h;7<8f:p=a6=839p14<;:2;4?8?013n=707l7;0;7>{t1m;1<7=t=806>6?0343<m7j9;<;`3?4?=2wx5i<50;1x9<412:3<7078b;f5?8?d?38346s|9e194?5|508<6>78;<;4g?b1343h;7<7a:p=a2=839p14<7:2;4?8?0l3n=707l7;043>{t1m?1<7=t=80:>6?0343<i7j9;<;`3?4?m2wx5i850;1x9<4f2:3<7078f;f5?8?d?382<6s|9e594?5|508i6>78;<;;4?b1343h;7<63:p=a>=839p14<l:2;4?8??93n=707l7;0:1>{t1m31<7=t=80g>6?03433>7j9;<;`3?4>12wx5io50;1x9<4b2:3<70773;f5?8?d?382n6s|9e`94?5|508m6>78;<;;0?b1343h;7<6e:p=ae=839p14=?:2;4?8??=3n=707l7;0b4>{t1mn1<7=t=812>6?03433:7j9;<;`3?4f<2wx5ik50;1x9<552:3<70777;f5?8?d?38j:6s|9ed94?5|50986>78;<;;<?b1343h;7<68:p=`6=839p14=;:2;4?8??13n=707l7;0b=>{t1l;1<7=t=816>6?03433m7j9;<;`3?4fj2wx5h<50;1x9<512:3<7077b;f5?8?d?38jj6s|9d194?5|509<6>78;<;;g?b1343h;7<m1:p=`2=839p14=7:2;4?8??l3n=707l7;0a0>{t1l?1<7=t=81:>6?03433i7j9;<;`3?4e>2wx5h850;1x9<5f2:3<7077f;f5?8?d?38im6s|9d594?5|509i6>78;<;:4?b1343h;7<mc:p=`>=839p14=l:2;4?8?>93n=707l7;0ab>{t1l31<7=t=81g>6?03432>7j9;<;`3?4d92wx5ho50;1x9<5b2:3<70763;f5?8?d?38ji6s|9d`94?5|509m6>78;<;:0?b1343h;7?j9:p=`e=839p14:?:2;4?8?>=3n=707l7;3ff>{t1ln1<7=t=862>6?03432:7j9;<;`3?7bm2wx5hk50;1x9<252:3<70767;f5?8?d?3;m<6s|9dd94?5|50>86>78;<;:<?b1343h;7?i4:p=c6=839p14:;:2;4?8?>13n=707l7;3e2>{t1o;1<7=t=866>6?03432m7j9;<;`3?7a12wx5k<50;1x9<212:3<7076b;f5?8?d?3;mn6s|9g194?5|50><6>78;<;:g?b1343h;7?if:p=c2=839p14:7:2;4?8?>l3n=707l7;035>{t1o?1<7=t=86:>6?03432i7j9;<;`3?7a;2wx5k850;1x9<2f2:3<7076f;f5?8?d?38;86s|9g594?5|50>i6>78;<;b4?b1343h;7<?6:p=c>=839p14:l:2;4?8?f93n=707l7;03e>{t1o31<7=t=86g>6?0343j>7j9;<;`3?47k2wx5ko50;1x9<2b2:3<707n3;f5?8?d?38;j6s|9g`94?5|50>m6>78;<;b0?b1343h;7<>1:p=ce=839p14;?:2;4?8?f=3n=707l7;021>{t1on1<7=t=872>6?0343j:7j9;<;`3?46?2wx5kk50;1x9<352:3<707n7;f5?8?d?38:m6s|9gd94?5|50?86>78;<;b<?b1343h;7<>c:pe56=839p14;;:2;4?8?f13n=707l7;03=>{ti9;1<7=t=876>6?0343jm7j9;<;`3?4582wxm=<50;1x9<312:3<707nb;f5?8?d?389>6s|a1194?5|50?<6>78;<;bg?b1343h;7<=5:pe52=839p14;7:2;4?8?fl3n=707l7;013>{ti9?1<7=t=87:>6?0343ji7j9;<;`3?45j2wxm=850;1x9<3f2:3<707nf;f5?8?d?389h6s|a1594?5|50?i6>78;<;a4?b1343h;7<<0:pe5>=839p14;l:2;4?8?e93n=707l7;006>{ti931<7=t=87g>6?0343i>7j9;<;`3?44>2wxm=o50;1x9<3b2:3<707m3;f5?8?d?38846s|a1`94?5|50?m6>78;<;a0?b1343h;7<=a:pe5e=839p148?:2;4?8?e=3n=707l7;00f>{ti9n1<7=t=842>6?0343i:7j9;<;`3?44l2wxm=k50;1x9<052:3<707m7;f5?8?d?38?=6s|a1d94?5|50<86>78;<;a<?b1343h;7<;3:pe46=839p148;:2;4?8?e13n=707l7;072>{ti8;1<7=t=846>6?0343im7j9;<;`3?4302wxm<<50;1x9<012:3<707mb;f5?8?d?38?o6s|a0194?5|50<<6>78;<;ag?b1343h;7<;e:pe42=839p1487:2;4?8?el3n=707l7;065>{ti8?1<7=t=84:>6?0343ii7j9;<;`3?42;2wxm<850;1x9<0f2:3<707mf;f5?8?d?38?<6s|a0594?5|50<i6>78;<;`4?b1343h;7<:8:pe4>=839p148l:2;4?8?d93n=707l7;06e>{ti831<7=t=84g>6?0343h>7j9;<;`3?42l2wxm<o50;1x9<0b2:3<707l3;f5?8?d?38>j6s|a0`94?5|50<m6>78;<;`0?b1343h;7<93:pe4e=839p149?:2;4?8?d=3n=707l7;056>{ti8n1<7=t=852>6?0343h:7j9;<;`3?41n2wxm<k50;0x9<152:3<707l7;063>{ti8l1<7<t=850>6?0343h;7<83:pe76=838p149;:2;4?8?d?38<96s|a3394?4|50=>6>78;<;`3?4012wxm?<50;0x9<112:3<707l7;04f>{ti;91<7<t=854>6?0343h;7<8e:pe72=838p1497:2;4?8?d?383<6s|a3794?4|50=26>78;<;`3?4?<2wxm?850;0x9<1f2:3<707l7;0;2>{ti;=1<7<t=85a>6?0343h;7<79:pe7>=838p149l:2;4?8?d?383n6s|a3;94?4|50=o6>78;<;`3?4?:2wxm?o50;0x9<1b2:3<707l7;0;b>{ti;h1<7<t=85e>6?0343h;7<61:pe7e=838p146?:2;4?8?d?38286s|a3f94?4|502:6>78;<;`3?4>>2wxm?k50;0x9<>52:3<707l7;0:e>{ti;l1<7<t=8:0>6?0343h;7<6c:pe66=838p146;:2;4?8?d?382j6s|a2394?4|502>6>78;<;`3?4f92wxm><50;0x9<>12:3<707l7;0b1>{ti:91<7<t=8:4>6?0343h;7<n7:pe62=838p1467:2;4?8?d?38j?6s|a2794?4|50226>78;<;`3?4fi2wxm>850;0x9<>f2:3<707l7;0bg>{ti:=1<7<t=8:a>6?0343h;7<m0:pe6>=838p146l:2;4?8?d?38i>6s|a2;94?4|502o6>78;<;`3?4e=2wxm>o50;0x9<>b2:3<707l7;0a3>{ti:h1<7<t=8:e>6?0343h;7<mb:pe6e=838p147?:2;4?8?d?38ih6s|a2f94?4|503:6>78;<;`3?4d82wxm>k50;0x9<?52:3<707l7;0`6>{ti:l1<7<t=8;0>6?0343h;7<m9:pe16=838p147;:2;4?8?d?3;nm6s|a5394?4|503>6>78;<;`3?7bk2wxm9<50;0x9<?12:3<707l7;3fb>{ti=91<7<t=8;4>6?0343h;7?i1:pe12=838p1477:2;4?8?d?3;m96s|a5794?4|50326>78;<;`3?7a?2wxm9850;0x9<?f2:3<707l7;3ee>{ti==1<7<t=8;a>6?0343h;7?ic:pe1>=838p147l:2;4?8?d?38;<6s|a5;94?4|503o6>78;<;`3?47:2wxm9o50;0x9<?b2:3<707l7;3ea>{ti=h1<7<t=8;e>6?0343h;7<?5:pe1e=838p14o?:2;4?8?d?38;;6s|a5f94?4|50k:6>78;<;`3?47j2wxm9k50;0x9<g52:3<707l7;03`>{ti=l1<7<t=8c0>6?0343h;7<>0:pe06=838p14o;:2;4?8?d?38:>6s|a4394?4|50k>6>78;<;`3?46>2wxm8<50;0x9<g12:3<707l7;02<>{ti<91<7<t=8c4>6?0343h;7<>b:pe02=838p14o7:2;4?8?d?38:h6s|a4794?4|50k26>78;<;`3?46<2wxm8850;0x9<gf2:3<707l7;015>{ti<=1<7<t=8ca>6?0343h;7<=3:pe0>=838p14ol:2;4?8?d?389:6s|a4;94?4|50ko6>78;<;`3?4502wxm8o50;0x9<gb2:3<707l7;01g>{ti<h1<7<t=8ce>6?0343h;7<=e:pe0e=838p14l?:2;4?8?d?388=6s|a4f94?4|50h:6>78;<;`3?44;2wxm8k50;0x9<d52:3<707l7;003>{ti<l1<7<t=8`0>6?0343h;7<<9:pe36=838p14l;:2;4?8?d?38896s|a7394?4|50h>6>78;<;`3?44k2wxm;<50;0x9<d12:3<707l7;00a>{ti?91<7<t=8`4>6?0343h;7<;2:pe32=838p14l7:2;4?8?d?38?86s|a7794?4|50h26>78;<;`3?43?2wxm;850;0x9<df2:3<707l7;07=>{ti?=1<7<t=8`a>6?0343h;7<;d:pe3>=838p14ll:2;4?8?d?38?j6s|a7;94?4|50ho6>78;<;`3?42:2wxm;o50;0x9<db2:3<707l7;060>{ti?h1<7<t=8`e>6?0343h;7<;b:pe3e=838p14m?:2;4?8?d?38>56s|a7f94?4|50i:6>78;<;`3?42j2wxm;k50;0x9<e52:3<707l7;06a>{ti?l1<7<t=8a0>6?0343h;7<90:pe26=838p14m;:2;4?8?d?38=86s|a6394?4|50i>6>78;<;`3?41m2wxm:<50;0x9<e12:3<707l7;044>{ti>>1<7<t=8a4>6b4343;;7<la:pe23=83>p1l9<:2;4?8?7>3>:707?4;62?8?7=3>;7p}n7783>1}:0oi18=528g5905=:1891?494=827>14<uzk<;7>54z?;b1<c>273jk4<969>=50=<:165=:5429~wd1?290:8v374480=d=:0=>1?4o4=960>6?f342?>7=6a:?;04<41h1649>538c89=5a2:3j706<e;1:e>;?;m085l5282a97<g<513=6>7n;<::1?5>i2739:4nd:?;1<<fl273>94=c`9><53=;0=015>9:e489=0e2:3j7069c;1:e>;ei=09oo5rs`5:>5<6<r73j;4<969>2a4=<:16:io5429>2g4=<>16:o=5469>2g2=<>16:o;5469>2f2=<>16:n;5469>2f0=<>16:n95469>2d?=<>16:lo5469>2a3=<>16:i85469>2d4=<>16:l=5469>2ad=<>16:im5469>2a5=<>1vl9n:1808>5:38hn639a180=2=:jh81>nl4}rc4f?6=>r73?n4k6:?5b`<5kh16;:=5385892132;ij709n7;3f<>;0i00:i55rs`5`>5<1s428h7j9;<535?4di27<;:4<969>32>=:jk01:o8:374?81f138>;6s|a6f94?0|519n6i84=627>7ef34=<n7=67:?43f<5kh16;l95265892g>2;=<7p}n7d83>3}:0:l1h;5271596fg<5>=m6>78;<5;4?4di27<m:4=839>3d?=:180q~o8f;292~;?<90o:6380`81gd=:?191?494=6:7>7ef34=j;7<7d:?4e<<50m1vl6?:1858>393n=709?d;0`e>;00>085:5279:96fg<5>k<6?77;<5b=?4>02wxm5?50;4x9=252m<01:??:3ab?81?j392;6388b81gd=:?h=1>l=4=6c:>7g43tyj4?4?:7y><15=l?16;<=52bc892>a2:3<70960;0`e>;0i>09mh527`;96dc<uzk3?7>56z?;01<c>27<=;4=c`9>3<5=;0=01:7;:3ab?81f?38i5638a881f<=z{h2?6=49{<:71?b134=:57<la:?4=3<41>16;4952bc892g02;i>709n9;0`1>{ti1?1<7?9{<::1?b134<ji7=67:?4`0<5kk16:i<5419>2ag=<916:o<5459>2g5=<=16:o:5459>2g3=<=16:n:5459>2f3=<=16:n85459>2f1=<=16:l75459>2dg=<=16:i;5459>2a0=<=16:l<5459>2d5=<=16:il5459>2ae=<=16:i=5459~wd>1290::v37978g2>;1k9085:527e796fe<5?n969?4=7fb>17<5?h969;4=7`0>13<5?h?69;4=7`6>13<5?i?69;4=7a6>13<5?i=69;4=7a4>13<5?k269;4=7cb>13<5?n>69;4=7f5>13<5?k969;4=7c0>13<5?ni69;4=7f`>13<5?n869;4}rc;3?6=:r7?:o4<969>1d7=9;h0q~o78;296~;3>m085:525`39565<uzk357>52z?72c<41>169l?51268yvg?i3:1>v3;7080=2=:=h;1=>;4}rc;f?6=:r7?;>4<969>1d7=9:<0q~o7c;296~;3?>085:525`39561<uzk3h7>52z?73<<41>169l?512:8yvg?m3:1>v3;7c80=2=:=h;1=>74}rc;b?6=:r7?;i4<969>1d7=9=30q~o60;296~;3ko085:525`3956g<uzk2=7>52z?7`4<41>169l?512`8yvg>:3:1>v3;d280=2=:=h;1=?m4}rc:7?6=:r7?h84<969>1d7=9;n0q~o64;296~;3l>085:525`3957c<uzk297>52z?5=f<5kk16:8753838yvg>>3:14v36c680e==:0<<1h;5289a96fb<5>l86>78;<5e0?b1342987<lb:?;`f<41h1648;538c8yvg>?3:1?v3n7280=3=:?o>1?494=6d6>a0<uzk247>55z?:56<41h165=85419>=42=;h201:h::2;4?81a>3n=7p}n9883>0}:0o<1?4o4=9d;>6?f342mh7=6a:?4b3<41>16;k95d79~wd?f290?w06if;1:e>;?nh085l527g597<1<5>l36i84}rc:f?6=;r73j94<9`9>3c>=;0=01:h6:e48yvg>k3:1>:u27g;97<1<5>lj6i84=7;f>6?f34=o:7=6a:?5e`<41h16:n>538c893`a2:3j708id;1:e>;08;085l5271297<g<5>:>6>7n;<537?5>i27<<54<9`9>350=;0k01:>m:2;b?8171392m6380d80=d=:?9i1?4o4=632>6?f34=;j7=6a:?451<41h16;<<538c892702:3j709>5;1:e>;09h085l5270:97<g<5>3=6>7n;<5:7?5>i27<4k4<9`9>3=d=;0k01:68:2;b?81?;392m6387g80=d=:?>h1?4o4=654>6?f34=<?7=6a:?4e0<4i116;l953`:892g>2:k37p}n9e83>6}:?ok1?494=7;e>6?f34=o;7=6a:pe<c=838p1;7l:3ab?8>cj392;6s|a8d94?72s42m87=67:?4`0<5kh16:i<5439>2ag=<;16:o<5479>2g5=<?16:o:5479>2g3=<?16:n:5479>2f3=<?16:n85479>2f1=<?16:l75479>2dg=<?16:i;5479>2a0=<?16:l<5479>2d5=<?16:il5479>2ae=<?16:i=5479~wd`22908w0on0;1:3>;3;;0o:6361e8g2>{tio<1<7=t=`c2>6?034>887j9;<;2a?b13tyjj:4?:2y>ed4=;0=019=9:e489<7a2m<0q~oi8;297~;fi:085:5242:9`3=:1;:1h;5rs`d:>5<4s4kj87=67:?77d<c>272><4k6:pecg=839p1lo::2;4?824k3n=707=2;f5?xufnk0;6>u2a`497<1<5=9n6i84=800>a0<uzkmo7>53z?be2<41>1689>5d79>=72=l?1vlhk:1808gf0392;63;438g2>;>:<0o:6s|agg94?5|5hk26>78;<670?b13439:7j9;|qbbc<72:q6mlo5385891212m<014<8:e48yvd783:1?v3nac80=2=:<=21h;5293:9`3=z{k::6=4<{<cbg?5>?27?8l4k6:?:6<<c>2wxn=<50;1x9dgc2:3<70:;c;f5?8?5i3n=7p}m0283>6}:iho1?494=56f>a0<508i6i84}r`30?6=;r7jmk4<969>006=l?165?m5d79~wg622908w0om0;1:3>;3=;0o:6362e8g2>{tj9<1<7=t=``2>6?034>>87j9;<;1a?b13tyi<:4?:2y>eg4=;0=019;9:e489<4a2m<0q~l?8;297~;fj:085:5244:9`3=:1::1h;5rsc2:>5<4s4ki87=67:?71d<c>272?<4k6:pf5g=839p1ll::2;4?822k3n=707<2;f5?xue8k0;6>u2ac497<1<5=?n6i84=810>a0<uzh;o7>53z?bf2<41>168;>5d79>=62=l?1vo>k:1808ge0392;63;638g2>;>;<0o:6s|b1g94?5|5hh26>78;<650?b13438:7j9;|qa4c<72:q6moo5385891012m<014=8:e48yvd683:1?v3nbc80=2=:<?21h;5292:9`3=z{k;:6=4<{<cag?5>?27?:l4k6:?:7<<c>2wxn<<50;1x9ddc2:3<70:9c;f5?8?4i3n=7p}m1283>6}:iko1?494=54f>a0<509i6i84}r`20?6=;r7jnk4<969>026=l?165>m5d79~wg722908w0ol0;1:3>;3?;0o:6363e8g2>{tj8<1<7=t=`a2>6?034><87j9;<;0a?b13tyi=:4?:2y>ef4=;0=01999:e489<5a2m<0q~l>8;297~;fk:085:5246:9`3=:1=:1h;5rsc3:>5<4s4kh87=67:?73d<c>2728<4k6:pf4g=839p1lm::2;4?820k3n=707;2;f5?xue9k0;6>u2ab497<1<5==n6i84=860>a0<uzh:o7>53z?bg2<41>1685>5d79>=12=l?1vo?k:1808gd0392;63;838g2>;><<0o:6s|b0g94?5|5hi26>78;<6;0?b1343?:7j9;|qa5c<72:q6mno5385891>12m<014:8:e48yvd583:1?v3ncc80=2=:<121h;5295:9`3=z{k8:6=4<{<c`g?5>?27?4l4k6:?:0<<c>2wxn?<50;1x9dec2:3<70:7c;f5?8?3i3n=7p}m2283>6}:ijo1?494=5:f>a0<50>i6i84}r`10?6=;r7jok4<969>0<6=l?1659m5d79~wg422908w0ok0;1:3>;31;0o:6364e8g2>{tj;<1<7=t=`f2>6?034>287j9;<;7a?b13tyi>:4?:2y>ea4=;0=01979:e489<2a2m<0q~l=8;297~;fl:085:5248:9`3=:1<:1h;5rsc0:>5<4s4ko87=67:?7=d<c>2729<4k6:pf7g=839p1lj::2;4?82>k3n=707:2;f5?xue:k0;6>u2ae497<1<5=3n6i84=870>a0<uzh9o7>53z?b`2<41>168l>5d79>=02=l?1vo<k:1808gc0392;63;a38g2>;>=<0o:6s|b3g94?5|5hn26>78;<6b0?b1343>:7j9;|qa6c<72:q6mio5385891g12m<014;8:e48yvd483:1?v3ndc80=2=:<h21h;5294:9`3=z{k9:6=4<{<cgg?5>?27?ml4k6:?:1<<c>2wxn><50;1x9dbc2:3<70:nc;f5?8?2i3n=7p}m3283>6}:imo1?494=5cf>a0<50?i6i84}r`00?6=;r7jhk4<969>0g6=l?1658m5d79~wg522908w0oj0;1:3>;3j;0o:6365e8g2>{tj:<1<7=t=`g2>6?034>i87j9;<;6a?b13tyi?:4?:2y>e`4=;0=019l9:e489<3a2m<0q~l<8;297~;fm:085:524c:9`3=:1?:1h;5rsc1:>5<4s4kn87=67:?7fd<c>272:<4k6:pf6g=839p1lk::2;4?82ek3n=70792;f5?xue;k0;6>u2ad497<1<5=hn6i84=840>a0<uzh8o7>53z?ba2<41>168n>5d79>=32=l?1vo=k:1808gb0392;63;c38g2>;>><0o:6s|b2g94?5|5ho26>78;<6`0?b1343=:7j9;|qa7c<72:q6mho5385891e12m<01488:e48yvd383:1?v3nec80=2=:<j21h;5297:9`3=z{k>:6=4<{<cfg?5>?27?ol4k6:?:2<<c>2wxn9<50;1x9dcc2:3<70:lc;f5?8?1i3n=7p}m4283>6}:ilo1?494=5af>a0<50<i6i84}r`70?6=;r7jik4<969>0a6=l?165;m5d79~wg222908w0oi0;1:3>;3l;0o:6366e8g2>{tj=<1<7=t=`d2>6?034>o87j9;<;5a?b13tyi8:4?:2y>ec4=;0=019j9:e489<0a2m<0q~l;8;297~;fn:085:524e:9`3=:1>:1h;5rsc6:>5<4s4km87=67:?7`d<c>272;<4k6:pfd7=838j?v376c8g2>;e?o085?52a619e1=:0oi18<528ga907=:0oi18>528g5904=:0o=18?528g5906=:<:818=52420904=:<:818?5245:905=:<=218<5245:907=:<<o18=5244g904=:<<o18?52466905=:<>>18<52466907=:<1k18=5249c904=:<1k18?524`2905=:<h:18<524`2907=:<k<18=524c4904=:<k<18?524ba905=:<ji18<524ba907=:<m218=524e:904=:<m218?524ec905=:<mk18<524ec907=:<:>18=52426904=:<:>18?52424905=:<:<18<52424907=:<:218=5242:904=:<:218?5242c905=:<:k18<5242c907=:<:i18=5242a904=:<:i18?5242g905=:<:o18<5242g907=:<=:18=52452904=:<=:18?52450905=:<=818<52450907=:<=>18=52456904=:<=>18?52454905=:<=<18<52454907=:<=k18=5245c904=:<=k18?5245a905=:<=i18<5245a907=:<=o18=5245g904=:<=o18?52442905=:<<:18<52442907=:<<818=52440904=:<<818?52446905=:<<>18<52446907=:<<<18=52444904=:<<<18?5244:905=:<<218<5244:907=:<<k18=5244c904=:<<k18?5244a905=:<<i18<5244a907=:<?:18=52472904=:<?:18?52470905=:<?818<52470907=:<?>18=52476904=:<?>18?52474905=:<?<18<52474907=:<?218=5247:904=:<?218?5247c905=:<?k18<5247c907=:<?i18=5247a904=:<?i18?5247g905=:<?o18<5247g907=:<>:18=52462904=:<>:18?52460905=:<>818<52460907=:<><18=52464904=:<><18?5246:905=:<>218<5246:907=:<>k18=5246c904=:<>k18?5246a905=:<>i18<5246a907=:<>o18=5246g904=:<>o18?52492905=:<1:18<52492907=:<1818=52490904=:<1818?52496905=:<1>18<52496907=:<1<18=52494904=:<1<18?5249:905=:<1218<5249:907=:<1i18=5249a904=:<1i18?5249g905=:<1o18<5249g907=:<0:18=52482904=:<0:18?52480905=:<0818<52480907=:<0>18=52486904=:<0>18?52484905=:<0<18<52484907=:<0218=5248:904=:<0218?5248c905=:<0k18<5248c907=:<0i18=5248a904=:<0i18?5248g905=:<0o18<5248g907=:<h818=524`0904=:<h818?524`6905=:<h>18<524`6907=:<h<18=524`4904=:<h<18?524`:905=:<h218<524`:907=:<hk18=524`c904=:<hk18?524`a905=:<hi18<524`a907=:<ho18=524`g904=:<ho18?524c2905=:<k:18<524c2907=:<k818=524c0904=:<k818?524c6905=:<k>18<524c6907=:<k218=524c:904=:<k218?524cc905=:<kk18<524cc907=:<ki18=524ca904=:<ki18?524cg905=:<ko18<524cg907=:<j:18=524b2904=:<j:18?524b0905=:<j818<524b0907=:<j>18=524b6904=:<j>18?524b4905=:<j<18<524b4907=:<j218=524b:904=:<j218?524bc905=:<jk18<524bc907=:<jo18=524bg904=:<jo18?524e2905=:<m:18<524e2907=:<m818=524e0904=:<m818?524e6905=:<m>18<524e6907=:<m<18=524e4904=:<m<18?5297d9e1=:1?o1m95297f9e1=:1?i1m95297`9e1=:1?31m95297:9e1=:1?=1m9529749e1=:1??1m9529769e1=:1?91m9529709e1=:1?;1m9529729e1=:1<o1m95294f9e1=:1<i1m95294`9e1=:1<k1m95294;9e1=:1<21m9529459e1=:1<<1m9529479e1=:1<91m9529409e1=:1<;1m9529429e1=:1=l1m95295g9e1=:1=n1m95295a9e1=:1=h1m95295c9e1=:1=21m9529559e1=:1=<1m9529579e1=:1=>1m9529519e1=:1=81m9529539e1=:1=:1m95292d9e1=:1:n1m95292a9e1=:1:h1m95292c9e1=:1:31m95292:9e1=:1:=1m9529249e1=:1:?1m9529269e1=:1:81m9529239e1=:1::1m95293d9e1=:1;o1m95293f9e1=:1;i1m95293`9e1=:1;k1m95293;9e1=:1;=1m9529349e1=:1;?1m9529369e1=:1;91m9529309e1=:1;;1m9529329e1=:18l1m95290g9e1=:1>;1m9529629e1=:1?k1m95294d9e1=:1<>1m95295;9e1=:1:o1m9529219e1=:1;21m95290f9e1=:1j>1m9529b19e1=:1j81m9529b39e1=:1j:1m9529cg9e1=:1kn1m9529ca9e1=:1kh1m9529cc9e1=:1k31m9529c:9e1=:1k=1m9529c49e1=:1k?1m9529c19e1=:1k81m9529c39e1=:1k:1m9529`d9e1=:1ho1m9529`f9e1=:1hi1m9529``9e1=:1hk1m9529`:9e1=:1h=1m9529`49e1=:1h?1m9529`69e1=:1h91m9529`09e1=:1h;1m9529`29e1=:10l1m95298f9e1=:10i1m95298`9e1=:10k1m95298;9e1=:1021m9529859e1=:10<1m9529879e1=:10>1m9529809e1=:10;1m9529829e1=:11l1m95299g9e1=:11n1m95299a9e1=:11h1m95299c9e1=:1131m9529959e1=:11<1m9529979e1=:11>1m9529919e1=:1181m9529939e1=:11:1m95296d9e1=:1>o1m95296a9e1=:1>h1m95296c9e1=:1>31m95296:9e1=:1>=1m9529649e1=:1>?1m9529669e1=:1>91m9529b49e1=:1j?1m9529cd9e1=:1k>1m9529`;9e1=:10o1m9529819e1=:1121m95296f9e1=:1>81m9529b5963b<50i<6?8m;<;`3?41i272o:4=689>=f1=:?2014m8:344?8?d?38=:636c68120=:1j=1>;?4=8a4>73d343h;7<:5:?:g2<5=9165n9525c89<e02;>>707l7;00b>;>k>09?l529b59662<50i<6?<i;<;`3?451272o:4=259>=f1=:8o014m8:33:?8?d?38:?636c6814`=:1j=1>=64=8a4>764343h;7?id:?:g2<6n1165n951g089<e028oo707l7;0`7>;>k>09nh529b596g><50i<6?l<;<;`3?4fl272o:4=a99>=f1=:h8014m8:3;g?8?d?382;636c681=7=:1j=1>5m4=8a4>7>0343h;7<71:?:g2<5?j165n9526489<e02;=:707l7;062>;>k>09=k529b596f3<50i<6?6k;<;31?25343;97:<;<;3g?g1342=47o;;<:5=?g3342>:7o;;<::6?g33422>7j9;<:63?g3342>57j9;<:6<?g3342on7o;;<:6`?g3342>i7o;;<:6b?g33423i7o;;<:;b?g3342hi7o;;<:`f?g3342h;7o;;<:`7?g3342ij7o;;<:af?g3342i;7o;;<:a7?g3342jj7o;;<:bf?g3342jm7o9;<:b`?g13429?7<lc:?;51<f<273=84n4:?;53<f<273=:4n4:?;44<f<273<?4n4:?;46<f<273<94n4:?;40<f<273<;4n4:?5bf<3827=jn4;1:?5bf<3:27=jn4;3:?437<f>27<;84n6:?46`<f>27<?<4n6:?6f7<5kk169no5a79>1fb=i?1699j5a79>106=i?169:j5a79>1=6=i?169l?5649>1d7=>=169l?55d9>1d7=0j169l?58c9>1d7=0h169l?5859>1d7=99:018o>:gg890g62on018o>:ga890g62oh018o>:gc890g628:270;n1;33<>;2i80:<:525`39550<5<k:6<>:;<7b5?77<27>m<4>029>1d7=998018o>:022?83f93l270;n1;377>;2i80:8<525`395fb<5<k:6>o;;<7b5?5f=27>m?4k8:?6e7<4i:169l<59b9>1d4=9ji018o=:8`890g520o018o=:8f890g52:k>70;n2;374>;2i;0:?h525`0956b<5<k96<=l;<7b6?3334?j>7;8;<7b6?3134?j>7;:;<7b6?2c34?j>798;<7b6?1e34?j>79n;<7b6?1>34?j>797;<7b6?1734?j>7h>;<7b6?ca34?j>7kk;<7b6?cd34?j>7km;<7b6?cf34?j>7k6;<7b6?c?34?j>7k8;<7b6?c134?j>7k:;<7b6?c334?j>7k=;<7b6?c634?j>7k?;<7b6?ba34?j>7jj;<7b6?bc34?j>7jl;<7b6?be34?j>7jn;<7b6?b>34?j>7h7;<7b6?`034?j>7h9;<7b6?`234?j>7h;;<7b6?`434?j>7h=;<7b6?cb34?j>7k<;<7b7?b?34?j?7=n3:?6e6<>k27>m>4>cb9>1d5=1k169l=59d9>1d5=1m169l=53`7890g428>;70;n3;30a>;2i:0:?i525`1956e<5<k868:4=4c0>01<5<k86884=4c0>03<5<k869j4=4c0>21<5<k86:l4=4c0>2g<5<k86:74=4c0>2><5<k86:>4=4c0>c7<5<k86hh4=4c0>`b<5<k86hm4=4c0>`d<5<k86ho4=4c0>`?<5<k86h64=4c0>`1<5<k86h84=4c0>`3<5<k86h:4=4c0>`4<5<k86h?4=4c0>`6<5<k86ih4=4c0>ac<5<k86ij4=4c0>ae<5<k86il4=4c0>ag<5<k86i74=4c0>c><5<k86k94=4c0>c0<5<k86k;4=4c0>c2<5<k86k=4=4c0>c4<5<k86hk4=4c0>`5<uzhj>7>52z?ae7<418164;m5d79~wgg42909w0ln3;1:5>;?lj0o:6s|b`694?4|5kk?6>7>;<:61?b13twe>=;9:184Md3i2P8h44>{0a1>x\6m=0:w>j6:|m6530290:9vFm4`9~j76203:1=vFm4`9~j76213:1=vFm4`9~j762i3:1=vFm4`9~j762j3:1=vFm4`9~j762k3:1=vFm4`9~j762l3:1=vFm4`9~j762m3:1=vFm4`9~j762n3:1=vFm4`9~j76183:1=vFm4`9~j76193:1=vFm4`9~j761:3:1?vFm4`9~j761;3:1jvFm4`9~j761<3:1=vFm4`9~j761=3:1=vFm4`9~j761>3:1=vFm4`9~j761?3:1=vFm4`9~j76103:1=vFm4`9~j76113:1=vFm4`9~j761i3:1=vFm4`9~j761j3:1=vFm4`9~j761k3:1=vFm4`9~j761l3:1=vFm4`9~j761m3:1=vFm4`9~j761n3:1=vFm4`9~j76083:1=vFm4`9~j76093:1=vFm4`9~j760:3:1=vFm4`9~j760;3:1=vFm4`9~j760<3:1=vFm4`9~j760=3:1=vFm4`9~j760>3:1=vFm4`9~j760?3:1=vFm4`9~j76003:1=vFm4`9~j76013:1=vFm4`9~j760i3:1;vFm4`9~j760j3:1=vFm4`9~j760k3:1=vFm4`9~j760l3:1=vFm4`9~j760m3:1=vFm4`9~j760n3:1=vFm4`9~j76?83:1=vFm4`9~j76?93:1=vFm4`9~j76?:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=09194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:387>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14=3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>76;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh581=1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32;<?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<5750;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76?i3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=09`94?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:3o7>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14=b=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>7e;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh581l1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32:4?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<4?50;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76>:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=08194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:287>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14<3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>66;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh580=1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32:<?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<4750;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76>i3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=08`94?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:2o7>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14<b=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>6e;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh580l1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32b4?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<l?50;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76f:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0`194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:j87>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14d3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>n6;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58h=1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32b<?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<l750;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76fi3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0``94?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:jo7>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14db=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>ne;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58hl1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32a4?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<o?50;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76e:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0c194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:i87>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14g3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>m6;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58k=1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32a<?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<o750;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76ei3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0c`94?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:io7>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14gb=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>me;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58kl1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32`4?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<n?50;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76d:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0b194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:h87>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14f3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>l6;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58j=1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32`<?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<n750;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76di3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0b`94?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:ho7>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14fb=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>le;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58jl1<7?tHc6b?M5?m2P:i94={2`3>6142tB84k5rn32g4?6=9rBi8l5G39g8^4c32;q8n=4<728~L6>a3td9<i?50;3xLg2f3A93i6T>e5816d72:=86pF<8g9~j76c:3:1=vFm4`9K7=c<R8o?6?u<b18036<z@:2m7p`=0e194?7|@k>j7E=7e:X2a1<5s:h;6>9<:|J0<c=zf;:o87>51zJa0d=O;1o0V<k;:3y0f5<4?:0vD>6i;|l14a3=83;pDo:n;I1;a>\6m=09w>l?:250>xN40o1vb?>k6;295~Ne<h1C?5k4Z0g7>7}4j908;>4rH2:e?xh58m=1<7?tHc6b?xh58m21<7?tHc6b?xh58m31<7?tHc6b?xh58mk1<7?tHc6b?xh58mh1<7?tHc6b?xh58mi1<7?tHc6b?xh58mn1<7?tHc6b?xh58mo1<7?tHc6b?xh58ml1<7?tHc6b?xh58l:1<7?tHc6b?xh58l;1<7?tHc6b?xh58l81<7?tHc6b?xh58l91<7?tHc6b?xh58l>1<7?tHc6b?xh58l?1<7?tHc6b?xh58l<1<7?tHc6b?xh58l=1<7?tHc6b?xh58l21<7?tHc6b?xh58l31<7?tHc6b?xh58lk1<7?tHc6b?xh58lh1<7?tHc6b?xh58li1<7?tHc6b?xh58ln1<7?tHc6b?xh58lo1<7?tHc6b?xh58ll1<7?tHc6b?xh58o:1<7?tHc6b?xh58o;1<7?tHc6b?xh58o81<7?tHc6b?xh58o91<7?tHc6b?xh58o>1<7?tHc6b?xh58o?1<7?tHc6b?xh58o<1<7?tHc6b?xh58o=1<7?tHc6b?xh58o21<7?tHc6b?xh58o31<7?tHc6b?xh58ok1<7?tHc6b?xh58oh1<7?tHc6b?xh58oi1<7?tHc6b?xh58on1<7?tHc6b?xh58oo1<7?tHc6b?xh58ol1<7?tHc6b?xh599:1<7?tHc6b?xh599;1<7?tHc6b?xh59981<7?tHc6b?xh59991<7?tHc6b?xh599>1<7?tHc6b?xh599?1<7?tHc6b?xh599<1<7?tHc6b?xh599=1<7?tHc6b?xh59921<7?tHc6b?xh59931<7?tHc6b?xh599k1<7?tHc6b?xh599h1<7?tHc6b?xh599i1<7?tHc6b?xh599n1<7?tHc6b?xh599o1<7?tHc6b?xh599l1<7?tHc6b?xh598:1<7?tHc6b?xh598;1<7?tHc6b?xh59881<7?tHc6b?xh59891<7?tHc6b?xh598>1<7?tHc6b?xh598?1<7?tHc6b?xh598<1<7?tHc6b?xh598=1<7?tHc6b?xh59821<7?tHc6b?xh59831<7?tHc6b?xh598k1<7?tHc6b?xh598h1<7?tHc6b?xh598i1<7?tHc6b?xh598n1<7?tHc6b?xh598o1<7?tHc6b?xh598l1<7?tHc6b?xh59;:1<7?tHc6b?xh59;;1<7?tHc6b?xh59;81<7?tHc6b?xh59;91<7?tHc6b?xh59;>1<7?tHc6b?xh59;?1<7?tHc6b?xh59;<1<7?tHc6b?xh59;=1<7?tHc6b?xh59;21<7?tHc6b?xh59;31<7?tHc6b?xh59;k1<7?tHc6b?xh59;h1<7?tHc6b?xh59;i1<7?tHc6b?xh59;n1<7?tHc6b?xh59;o1<7?tHc6b?xh59;l1<7?tHc6b?xh59::1<7?tHc6b?xh59:;1<7?tHc6b?xh59:81<7?tHc6b?xh59:91<7?tHc6b?xh59:>1<7?tHc6b?xh59:?1<7?tHc6b?xh59:<1<7?tHc6b?xh59:=1<7?tHc6b?xh59:21<7?tHc6b?xh59:31<7?tHc6b?xh59:k1<7?tHc6b?xh59:h1<7?tHc6b?xh59:i1<7?tHc6b?xh59:n1<7?tHc6b?xh59:o1<7?tHc6b?xh59:l1<7?tHc6b?xh59=:1<7?tHc6b?xh59=;1<7?tHc6b?xh59=81<7?tHc6b?xh59=91<7?tHc6b?xh59=>1<7?tHc6b?xh59=?1<7?tHc6b?xh59=<1<7?tHc6b?xh59==1<7?tHc6b?xh59=21<7?tHc6b?xh59=31<7?tHc6b?xh59=k1<7?tHc6b?xh59=h1<7?tHc6b?xh59=i1<7?tHc6b?xh59=n1<7?tHc6b?xh59=o1<7?tHc6b?xh59=l1<7?tHc6b?xh59<:1<7?tHc6b?xh59<;1<7?tHc6b?xh59<81<7?tHc6b?xh59<91<7?tHc6b?xh59<>1<7?tHc6b?xh59<?1<7?tHc6b?xh59<<1<7?tHc6b?xh59<=1<7?tHc6b?xh59<21<7?tHc6b?xh59<31<7?tHc6b?xh59<k1<7?tHc6b?xh59<h1<7?tHc6b?xh59<i1<7?tHc6b?xh59<n1<7?tHc6b?xh59<o1<7?tHc6b?xh59<l1<7?tHc6b?xh59?:1<7?tHc6b?xh59?;1<7?tHc6b?xh59?81<7?tHc6b?xh59?91<7?tHc6b?xh59?>1<7?tHc6b?xh59??1<7?tHc6b?xh59?<1<7?tHc6b?xh59?=1<7?tHc6b?xh59?21<7?tHc6b?xh59?31<7?tHc6b?xh59?k1<7?tHc6b?xh59?h1<7?tHc6b?xh59?i1<7?tHc6b?xh59?n1<7?tHc6b?xh59?o1<7?tHc6b?xh59?l1<7?tHc6b?xh59>:1<7?tHc6b?xh59>;1<7?tHc6b?xh59>81<7?tHc6b?xh59>91<7?tHc6b?xh59>>1<7?tHc6b?xh59>?1<7?tHc6b?xh59><1<7?tHc6b?xh59>=1<7?tHc6b?xh59>21<7?tHc6b?xh59>31<7?tHc6b?xh59>k1<7?tHc6b?xh59>h1<7?tHc6b?xh59>i1<7?tHc6b?xh59>n1<7?tHc6b?xh59>o1<7?tHc6b?xh59>l1<7?tHc6b?xh591:1<7?tHc6b?xh591;1<7?tHc6b?xh59181<7?tHc6b?xh59191<7?tHc6b?xh591>1<7?tHc6b?xh591?1<7?tHc6b?xh591<1<7?tHc6b?xh591=1<7?tHc6b?xh59121<7?tHc6b?xh59131<7?tHc6b?xh591k1<7?tHc6b?xh591h1<7?tHc6b?xh591i1<7?tHc6b?xh591n1<7?tHc6b?xh591o1<7?tHc6b?xh591l1<7?tHc6b?xh590:1<7?tHc6b?xh590;1<7?tHc6b?xh59081<7?tHc6b?xh59091<7?tHc6b?xh590>1<7?tHc6b?xh590?1<7?tHc6b?xh590<1<7?tHc6b?xh590=1<7?tHc6b?xh59021<7?tHc6b?xh59031<7?tHc6b?xh590k1<7?tHc6b?xh590h1<7?tHc6b?xh590i1<7?tHc6b?xh590n1<7?tHc6b?xh590o1<7?tHc6b?xh590l1<7?tHc6b?xh59h:1<7?tHc6b?xh59h;1<7?tHc6b?xh59h81<7?tHc6b?xh59h91<7?tHc6b?xh59h>1<7?tHc6b?xh59h?1<7?tHc6b?xh59h<1<7?tHc6b?xh59h=1<7?tHc6b?xh59h21<7?tHc6b?xh59h31<7?tHc6b?xh59hk1<7?tHc6b?xh59hh1<7?tHc6b?xh59hi1<7?tHc6b?xh59hn1<7?tHc6b?xh59ho1<7?tHc6b?xh59hl1<7?tHc6b?xh59k:1<7?tHc6b?xh59k;1<7?tHc6b?xh59k81<7?tHc6b?xh59k91<7?tHc6b?xh59k>1<7?tHc6b?xh59k?1<7?tHc6b?xh59k<1<7?tHc6b?xh59k=1<7?tHc6b?xh59k21<7?tHc6b?xh59k31<7?tHc6b?xh59kk1<7?tHc6b?xh59kh1<7?tHc6b?xh59ki1<7?tHc6b?xh59kn1<7?tHc6b?xh59ko1<7?tHc6b?xh59kl1<7?tHc6b?xh59j:1<7?tHc6b?xh59j;1<7?tHc6b?xh59j81<7?tHc6b?xh59j91<7?tHc6b?xh59j>1<7?tHc6b?xh59j?1<7?tHc6b?xh59j<1<7?tHc6b?xh59j=1<7?tHc6b?xh59j21<7?tHc6b?xh59j31<7?tHc6b?xh59jk1<7?tHc6b?xh59jh1<7?tHc6b?xh59ji1<7?tHc6b?xh59jn1<7?tHc6b?xh59jo1<7?tHc6b?xh59jl1<7?tHc6b?xh59m:1<7?tHc6b?xh59m;1<7?tHc6b?xh59m81<7?tHc6b?xh59m91<7?tHc6b?xh59m>1<7?tHc6b?xh59m?1<7?tHc6b?xh59m<1<7?tHc6b?xh59m=1<7?tHc6b?xh59m21<7?tHc6b?xh59m31<7?tHc6b?xh59mk1<7?tHc6b?xh59mh1<7?tHc6b?xh59mi1<7?tHc6b?xh59mn1<7?tHc6b?xh59mo1<7?tHc6b?xh59ml1<7?tHc6b?xh59l:1<7?tHc6b?xh59l;1<7?tHc6b?xh59l81<7?tHc6b?xh59l91<7?tHc6b?xh59l>1<7?tHc6b?xh59l?1<7?tHc6b?xh59l<1<7?tHc6b?xh59l=1<7?tHc6b?xh59l21<7?tHc6b?xh59l31<7?tHc6b?xh59lk1<7?tHc6b?xh59lh1<7?tHc6b?xh59li1<7?tHc6b?xh59ln1<7?tHc6b?xh59lo1<7?tHc6b?xh59ll1<7?tHc6b?xh59o:1<7?tHc6b?xh59o;1<7?tHc6b?xh59o81<7?tHc6b?xh59o91<7?tHc6b?xh59o>1<7?tHc6b?xh59o?1<7?tHc6b?xh59o<1<7?tHc6b?xh59o=1<7?tHc6b?xh59o21<7?tHc6b?xh59o31<7?tHc6b?xh59ok1<7?tHc6b?xh59oh1<7?tHc6b?xh59oi1<7?tHc6b?xh59on1<7?tHc6b?xh59oo1<7?tHc6b?xh59ol1<7?tHc6b?xh5:9:1<7?tHc6b?xh5:9;1<7?tHc6b?xh5:981<7?tHc6b?xh5:991<7?tHc6b?xh5:9>1<7?tHc6b?xh5:9?1<7?tHc6b?xh5:9<1<7?tHc6b?xh5:9=1<7?tHc6b?xh5:921<7?tHc6b?xh5:931<7?tHc6b?xh5:9k1<7?tHc6b?xh5:9h1<7?tHc6b?xh5:9i1<7?tHc6b?xh5:9n1<7?tHc6b?xh5:9o1<7?tHc6b?xh5:9l1<7?tHc6b?xh5:8:1<7?tHc6b?xh5:8;1<7?tHc6b?xh5:881<7?tHc6b?xh5:891<7?tHc6b?xh5:8>1<7?tHc6b?xh5:8?1<7?tHc6b?xh5:8<1<7?tHc6b?xh5:8=1<7?tHc6b?xh5:821<7?tHc6b?xh5:831<7?tHc6b?xh5:8k1<7?tHc6b?xh5:8h1<7?tHc6b?xh5:8i1<7?tHc6b?xh5:8n1<7?tHc6b?xh5:8o1<7?tHc6b?xh5:8l1<7?tHc6b?xh5:;:1<7?tHc6b?xh5:;;1<7?tHc6b?xh5:;81<7?tHc6b?xh5:;91<7?tHc6b?xh5:;>1<7?tHc6b?xh5:;?1<7?tHc6b?xh5:;<1<7?tHc6b?xh5:;=1<7?tHc6b?xh5:;21<7?tHc6b?xh5:;31<7?tHc6b?xh5:;k1<7?tHc6b?xh5:;h1<7?tHc6b?xh5:;i1<7?tHc6b?xh5:;n1<7?tHc6b?xh5:;o1<7?tHc6b?xh5:;l1<7?tHc6b?xh5:::1<7?tHc6b?xh5::;1<7?tHc6b?xh5::81<7?tHc6b?xh5::91<7?tHc6b?xh5::>1<7?tHc6b?xh5::?1<7?tHc6b?xh5::<1<7?tHc6b?xh5::=1<7?tHc6b?xh5::21<7?tHc6b?xh5::31<7?tHc6b?xh5::k1<7?tHc6b?xh5::h1<7?tHc6b?xh5::i1<7?tHc6b?xh5::n1<7?tHc6b?xh5::o1<7?tHc6b?xh5::l1<7?tHc6b?xh5:=:1<7?tHc6b?xh5:=;1<7?tHc6b?xh5:=81<7?tHc6b?xh5:=91<7?tHc6b?xh5:=>1<7?tHc6b?xh5:=?1<7?tHc6b?xh5:=<1<7?tHc6b?xh5:==1<7?tHc6b?xh5:=21<7=tHc6b?xh5:=31<7?tHc6b?xh5:=k1<7?tHc6b?xh5:=h1<7?tHc6b?xh5:=i1<7?tHc6b?xh5:=n1<7?tHc6b?xh5:=o1<7?tHc6b?xh5:=l1<7?tHc6b?xh5:<:1<7?tHc6b?xh5:<;1<7?tHc6b?xh5:<81<7?tHc6b?xh5:<91<7?tHc6b?xh5:<>1<7?tHc6b?xh5:<?1<7?tHc6b?xh5:<<1<7?tHc6b?xh5:<=1<7?tHc6b?xh5:<21<7?tHc6b?xh5:<31<7?tHc6b?xh5:<k1<7?tHc6b?xh5:<h1<7?tHc6b?xh5:<i1<7?tHc6b?xh5:<n1<7?tHc6b?xh5:<o1<7?tHc6b?xh5:<l1<7?tHc6b?xh5:?:1<7?tHc6b?xh5:?;1<7?tHc6b?xh5:?81<7?tHc6b?xh5:?91<7?tHc6b?xh5:?>1<7?tHc6b?xh5:??1<7?tHc6b?xh5:?<1<7?tHc6b?xh5:?=1<7?tHc6b?xh5:?21<7?tHc6b?xh5:?31<7?tHc6b?xh5:?k1<7?tHc6b?xh5:?h1<7?tHc6b?xh5:?i1<7?tHc6b?xh5:?n1<7?tHc6b?xh5:?o1<7?tHc6b?xh5:?l1<7?tHc6b?xh5:>:1<7?tHc6b?xh5:>;1<7?tHc6b?xh5:>81<7?tHc6b?xh5:>91<7?tHc6b?xh5:>>1<7?tHc6b?xh5:>?1<7?tHc6b?xh5:><1<7?tHc6b?xh5:>=1<7?tHc6b?xh5:>21<7?tHc6b?xh5:>31<7?tHc6b?xh5:>k1<7?tHc6b?xh5:>h1<7?tHc6b?xh5:>i1<7?tHc6b?xh5:>n1<7?tHc6b?xh5:>o1<7?tHc6b?xh5:>l1<7?tHc6b?xh5:1:1<7?tHc6b?xh5:1;1<7?tHc6b?xh5:181<7?tHc6b?xh5:191<7?tHc6b?xh5:1>1<7?tHc6b?xh5:1?1<7?tHc6b?xh5:1<1<7?tHc6b?xh5:1=1<7?tHc6b?xh5:121<7?tHc6b?xh5:131<7?tHc6b?xh5:1k1<7?tHc6b?xh5:1h1<7?tHc6b?xh5:1i1<7?tHc6b?xh5:1n1<7?tHc6b?xh5:1o1<7?tHc6b?xh5:1l1<7?tHc6b?xh5:0:1<7=tHc6b?xh5:0;1<7=tHc6b?xh5:081<7=tHc6b?xh5:091<7=tHc6b?xh5:0>1<7=tHc6b?xh5:0?1<7?tHc6b?xh5:0<1<7?tHc6b?xh5:0=1<7?tHc6b?xh5:021<7?tHc6b?xh5:031<7?tHc6b?xh5:0k1<7?tHc6b?xh5:0h1<7?tHc6b?xh5:0i1<7?tHc6b?xh5:0n1<7?tHc6b?xh5:0o1<7?tHc6b?xh5:0l1<7?tHc6b?xh5:h:1<7?tHc6b?xh5:h;1<7?tHc6b?xh5:h81<7?tHc6b?xh5:h91<7?tHc6b?xh5:h>1<7?tHc6b?xh5:h?1<7?tHc6b?xh5:h<1<7?tHc6b?xh5:h=1<7?tHc6b?xh5:h21<7?tHc6b?xh5:h31<7?tHc6b?xh5:hk1<7?tHc6b?xh5:hh1<7?tHc6b?xh5:hi1<7?tHc6b?xh5:hn1<7?tHc6b?xh5:ho1<7?tHc6b?xh5:hl1<7=tHc6b?xh5:k:1<7=tHc6b?xh5:k;1<7=tHc6b?xh5:k81<7=tHc6b?xh5:k91<7=tHc6b?xh5:k>1<7=tHc6b?xh5:k?1<7=tHc6b?xh5:k<1<7=tHc6b?xh5:k=1<7=tHc6b?xh5:k21<7=tHc6b?xh5:k31<7?tHc6b?xh5:kk1<7=tHc6b?xh5:kh1<7?tHc6b?xh5:ki1<7?tHc6b?xh5:kn1<7=tHc6b?xh5:ko1<7?tHc6b?xh5:kl1<7?tHc6b?xh5:j:1<7=tHc6b?xh5:j;1<7?tHc6b?xh5:j81<7?tHc6b?xh5:j91<7?tHc6b?xh5:j>1<7?tHc6b?xh5:j?1<7?tHc6b?xh5:j<1<7?tHc6b?xh5:j=1<7?tHc6b?xh5:j21<7?tHc6b?xh5:j31<7?tHc6b?xh5:jk1<7?tHc6b?xh5:jh1<7?tHc6b?xh5:ji1<7?tHc6b?xh5:jn1<7?tHc6b?xh5:jo1<7?tHc6b?xh5:jl1<7?tHc6b?xh5:m:1<7?tHc6b?xh5:m;1<7?tHc6b?xh5:m81<7?tHc6b?xh5:m91<7?tHc6b?xh5:m>1<7?tHc6b?xh5:m?1<7?tHc6b?xh5:m<1<7?tHc6b?xh5:m=1<7?tHc6b?xh5:m21<7?tHc6b?xh5:m31<7?tHc6b?xh5:mk1<7?tHc6b?xh5:mh1<7?tHc6b?xh5:mi1<7?tHc6b?xh5:mn1<7?tHc6b?xh5:mo1<7?tHc6b?xh5:ml1<7?tHc6b?xh5:l:1<7?tHc6b?xh5:l;1<7?tHc6b?xh5:l81<7?tHc6b?xh5:l91<7?tHc6b?xh5:l>1<7?tHc6b?xh5:l?1<7?tHc6b?xh5:l<1<7?tHc6b?xh5:l=1<7?tHc6b?xh5:l21<7?tHc6b?xh5:l31<7?tHc6b?xh5:lk1<7?tHc6b?xh5:lh1<7?tHc6b?xh5:li1<7?tHc6b?xh5:ln1<7?tHc6b?xh5:lo1<7?tHc6b?xh5:ll1<7?tHc6b?xh5:o:1<7?tHc6b?xh5:o;1<7?tHc6b?xh5:o81<7?tHc6b?xh5:o91<7?tHc6b?xh5:o>1<7?tHc6b?xh5:o?1<7?tHc6b?xh5:o<1<7?tHc6b?xh5:o=1<7?tHc6b?xh5:o21<7?tHc6b?xh5:o31<7?tHc6b?xh5:ok1<7?tHc6b?xh5:oh1<7?tHc6b?xh5:oi1<7?tHc6b?xh5:on1<7?tHc6b?xh5:oo1<7?tHc6b?xh5:ol1<7?tHc6b?xh5;9:1<7?tHc6b?xh5;9;1<7?tHc6b?xh5;981<7?tHc6b?xh5;991<7?tHc6b?xh5;9>1<7?tHc6b?xh5;9?1<7?tHc6b?xh5;9<1<7?tHc6b?xh5;9=1<7?tHc6b?xh5;921<7?tHc6b?xh5;931<7?tHc6b?xh5;9k1<7?tHc6b?xh5;9h1<7?tHc6b?xh5;9i1<7?tHc6b?xh5;9n1<7?tHc6b?xh5;9o1<7?tHc6b?xh5;9l1<7?tHc6b?xh5;8:1<7?tHc6b?xh5;8;1<7?tHc6b?xh5;881<7?tHc6b?xh5;891<7?tHc6b?xh5;8>1<7?tHc6b?xh5;8?1<7?tHc6b?xh5;8<1<7?tHc6b?xh5;8=1<7?tHc6b?xh5;821<7?tHc6b?xh5;831<7?tHc6b?xh5;8k1<7?tHc6b?xh5;8h1<7?tHc6b?xh5;8i1<7?tHc6b?xh5;8n1<7?tHc6b?xh5;8o1<7?tHc6b?xh5;8l1<7?tHc6b?xh5;;:1<7?tHc6b?xh5;;;1<7?tHc6b?xh5;;81<7?tHc6b?xh5;;91<7?tHc6b?xh5;;>1<7?tHc6b?xh5;;?1<7?tHc6b?xh5;;<1<7?tHc6b?xh5;;=1<7?tHc6b?xh5;;21<7?tHc6b?xh5;;31<7?tHc6b?xh5;;k1<7?tHc6b?xh5;;h1<7?tHc6b?xh5;;i1<7?tHc6b?xh5;;n1<7?tHc6b?xh5;;o1<7?tHc6b?xh5;;l1<7?tHc6b?xh5;::1<7?tHc6b?xh5;:;1<7?tHc6b?xh5;:81<7?tHc6b?xh5;:91<7?tHc6b?xh5;:>1<7?tHc6b?xh5;:?1<7?tHc6b?xh5;:<1<7?tHc6b?xh5;:=1<7?tHc6b?xh5;:21<7?tHc6b?xh5;:31<7?tHc6b?xh5;:k1<7?tHc6b?xh5;:h1<7?tHc6b?xh5;:i1<7?tHc6b?xh5;:n1<7?tHc6b?xh5;:o1<7?tHc6b?xh5;:l1<7?tHc6b?xh5;=:1<7?tHc6b?xh5;=;1<7?tHc6b?xh5;=81<7?tHc6b?xh5;=91<7?tHc6b?xh5;=>1<7?tHc6b?xh5;=?1<7?tHc6b?xh5;=<1<7?tHc6b?xh5;==1<7?tHc6b?xh5;=21<7?tHc6b?xh5;=31<7?tHc6b?xh5;=k1<7?tHc6b?xh5;=h1<7?tHc6b?xh5;=i1<7?tHc6b?xh5;=n1<7?tHc6b?xh5;=o1<7?tHc6b?xh5;=l1<7?tHc6b?xh5;<:1<7?tHc6b?xh5;<;1<7?tHc6b?xh5;<81<7?tHc6b?xh5;<91<7?tHc6b?xh5;<>1<7?tHc6b?xh5;<?1<7?tHc6b?xh5;<<1<7?tHc6b?xh5;<=1<7?tHc6b?xh5;<21<7?tHc6b?xh5;<31<7?tHc6b?xh5;<k1<7?tHc6b?xh5;<h1<7?tHc6b?xh5;<i1<7=tHc6b?xh5;<n1<7?tHc6b?xh5;<o1<7=tHc6b?xh5;<l1<7?tHc6b?xh5;?:1<7?tHc6b?xh5;?;1<7?tHc6b?xh5;?81<7?tHc6b?xh5;?91<7?tHc6b?xh5;?>1<7=tHc6b?xh5;??1<7=tHc6b?xh5;?<1<7=tHc6b?xh5;?=1<7=tHc6b?xh5;?21<7=tHc6b?xh5;?31<7=tHc6b?xh5;?k1<7=tHc6b?xh5;?h1<7=tHc6b?xh5;?i1<7=tHc6b?xh5;?n1<7=tHc6b?xh5;?o1<7=tHc6b?xh5;?l1<7=tHc6b?xh5;>:1<7=tHc6b?xh5;>;1<7=tHc6b?xh5;>81<7=tHc6b?xh5;>91<7=tHc6b?xh5;>>1<7=tHc6b?xh5;>?1<7=tHc6b?xh5;><1<7=tHc6b?xh5;>=1<7=tHc6b?xh5;>21<7=tHc6b?xh5;>31<7=tHc6b?xh5;>k1<7=tHc6b?xh5;>h1<7=tHc6b?xh5;>i1<7=tHc6b?xh5;>n1<7=tHc6b?xh5;>o1<7=tHc6b?xh5;>l1<7=tHc6b?xh5;1:1<7=tHc6b?xh5;1;1<7=tHc6b?xh5;181<7=tHc6b?xh5;191<7=tHc6b?xh5;1>1<7=tHc6b?xh5;1?1<7=tHc6b?xh5;1<1<7=tHc6b?xh5;1=1<7=tHc6b?xh5;121<7=tHc6b?xh5;131<7=tHc6b?xh5;1k1<7=tHc6b?xh5;1h1<7=tHc6b?xh5;1i1<7=tHc6b?xh5;1n1<7=tHc6b?xh5;1o1<7=tHc6b?xh5;1l1<7=tHc6b?xh5;0:1<7=tHc6b?xh5;0;1<7=tHc6b?xh5;081<7=tHc6b?xh5;091<7=tHc6b?xh5;0>1<7=tHc6b?xh5;0?1<7=tHc6b?xh5;0<1<7=tHc6b?xh5;0=1<7=tHc6b?xh5;021<7=tHc6b?xh5;031<7=tHc6b?xh5;0k1<7=tHc6b?xh5;0h1<7=tHc6b?xh5;0i1<7=tHc6b?xh5;0n1<7=tHc6b?xh5;0o1<7=tHc6b?xh5;0l1<7=tHc6b?xh5;h:1<7=tHc6b?xh5;h;1<7=tHc6b?xh5;h81<7=tHc6b?xh5;h91<7=tHc6b?xh5;h>1<7=tHc6b?xh5;h?1<7=tHc6b?xh5;h<1<7=tHc6b?xh5;h=1<7=tHc6b?xh5;h21<7=tHc6b?xh5;h31<7=tHc6b?xh5;hk1<7=tHc6b?xh5;hh1<7=tHc6b?xh5;hi1<7=tHc6b?xh5;hn1<7=tHc6b?xh5;ho1<7=tHc6b?xh5;hl1<7=tHc6b?xh5;k:1<7=tHc6b?xh5;k;1<7=tHc6b?xh5;k81<7=tHc6b?xh5;k91<7=tHc6b?xh5;k>1<7=tHc6b?xh5;k?1<7=tHc6b?xh5;k<1<7=tHc6b?xh5;k=1<7=tHc6b?xh5;k21<7=tHc6b?xh5;k31<7=tHc6b?xh5;kk1<7=tHc6b?xh5;kh1<7=tHc6b?xh5;ki1<7=tHc6b?xh5;kn1<7=tHc6b?xh5;ko1<7=tHc6b?xh5;kl1<7=tHc6b?xh5;j:1<7=tHc6b?xh5;j;1<7=tHc6b?xh5;j81<7=tHc6b?xh5;j91<7=tHc6b?xh5;j>1<7=tHc6b?xh5;j?1<7=tHc6b?xh5;j<1<7=tHc6b?xh5;j=1<7=tHc6b?xh5;j21<7=tHc6b?xh5;j31<7=tHc6b?xh5;jk1<7=tHc6b?xh5;jh1<7=tHc6b?xh5;ji1<7=tHc6b?xh5;jn1<7=tHc6b?xh5;jo1<7=tHc6b?xh5;jl1<7=tHc6b?xh5;m:1<7=tHc6b?xh5;m;1<7=tHc6b?xh5;m81<7=tHc6b?xh5;m91<7=tHc6b?xh5;m>1<7=tHc6b?xh5;m?1<7=tHc6b?xh5;m<1<7=tHc6b?xh5;m=1<7=tHc6b?xh5;m21<7=tHc6b?xh5;m31<7=tHc6b?xh5;mk1<7=tHc6b?xh5;mh1<7=tHc6b?xh5;mi1<7=tHc6b?xh5;mn1<7=tHc6b?xh5;mo1<7=tHc6b?xh5;ml1<7=tHc6b?xh5;l:1<7=tHc6b?xh5;l;1<7=tHc6b?xh5;l81<7=tHc6b?xh5;l91<7=tHc6b?xh5;l>1<7=tHc6b?xh5;l?1<7=tHc6b?xh5;l<1<7=tHc6b?xh5;l=1<7=tHc6b?xh5;l21<7=tHc6b?xh5;l31<7=tHc6b?xh5;lk1<7=tHc6b?xh5;lh1<7=tHc6b?xh5;li1<7=tHc6b?xh5;ln1<7=tHc6b?xh5;lo1<7=tHc6b?xh5;ll1<7=tHc6b?xh5;o:1<7=tHc6b?xh5;o;1<7=tHc6b?xh5;o81<7=tHc6b?xh5;o91<7=tHc6b?xh5;o>1<7=tHc6b?xh5;o?1<7=tHc6b?xh5;o<1<7=tHc6b?xh5;o=1<7=tHc6b?xh5;o21<7=tHc6b?xh5;o31<7=tHc6b?xh5;ok1<7=tHc6b?xh5;oh1<7=tHc6b?xh5;oi1<7=tHc6b?xh5;on1<7=tHc6b?xh5;oo1<7=tHc6b?xh5;ol1<7=tHc6b?xh5<9:1<7=tHc6b?xh5<9;1<7=tHc6b?xh5<981<7=tHc6b?xh5<991<7=tHc6b?xh5<9>1<7=tHc6b?xh5<9?1<7=tHc6b?xh5<9<1<7=tHc6b?xh5<9=1<7=tHc6b?xh5<921<7=tHc6b?xh5<931<7=tHc6b?xh5<9k1<7=tHc6b?xh5<9h1<7=tHc6b?xh5<9i1<7=tHc6b?xh5<9n1<7=tHc6b?xh5<9o1<7=tHc6b?xh5<9l1<7=tHc6b?xh5<8:1<7=tHc6b?xh5<8;1<7=tHc6b?xh5<881<7?tHc6b?xh5<891<7?tHc6b?xh5<8>1<7?tHc6b?xh5<8?1<7?tHc6b?xh5<8<1<7?tHc6b?xh5<8=1<7?tHc6b?xh5<821<7;tHc6b?xh5<831<7;tHc6b?xh5<8k1<7;tHc6b?xh5<8h1<7;tHc6b?xh5<8i1<7;tHc6b?xh5<8n1<7;tHc6b?xh5<8o1<7;tHc6b?xh5<8l1<7;tHc6b?xh5<;:1<7;tHc6b?xh5<;;1<7;tHc6b?xh5<;81<7?tHc6b?xh5<;91<7?tHc6b?xh5<;>1<7?tHc6b?xh5<;?1<7?tHc6b?xh5<;<1<7?tHc6b?xh5<;=1<7?tHc6b?xh5<;21<7?tHc6b?xh5<;31<7?tHc6b?xh5<;k1<7?tHc6b?xh5<;h1<7?tHc6b?xh5<;i1<7?tHc6b?xh5<;n1<7?tHc6b?xh5<;o1<7?tHc6b?xh5<;l1<7?tHc6b?xh5<::1<7?tHc6b?xh5<:;1<7?tHc6b?xh5<:81<7?tHc6b?xh5<:91<7=tHc6b?xh5<:>1<7?tHc6b?xh5<:?1<7<tHc6b?xh5<:<1<7?tHc6b?xh5<:=1<7?tHc6b?xh5<:21<7?tHc6b?xh5<:31<7:tHc6b?xh5<:k1<7?tHc6b?xh5<:h1<7?tHc6b?xh5<:i1<7?tHc6b?xh5<:n1<7?tHc6b?xh5<:o1<7?tHc6b?xh5<:l1<7?tHc6b?xh5<=:1<7?tHc6b?xh5<=;1<7?tHc6b?xh5<=81<7?tHc6b?xh5<=91<7?tHc6b?xh5<=>1<7?tHc6b?xh5<=?1<7?tHc6b?xh5<=<1<7?tHc6b?xh5<==1<7?tHc6b?xh5<=21<7?tHc6b?xh5<=31<7?tHc6b?xh5<=k1<7?tHc6b?xh5<=h1<7?tHc6b?xh5<=i1<7?tHc6b?xh5<=n1<7?tHc6b?xh5<=o1<7?tHc6b?xh5<=l1<7?tHc6b?xh5<<:1<7?tHc6b?xh5<<;1<7?tHc6b?xh5<<81<7?tHc6b?xh5<<91<7?tHc6b?xh5<<>1<7?tHc6b?xh5<<?1<7?tHc6b?xh5<<<1<7?tHc6b?xh5<<=1<7?tHc6b?xh5<<21<7?tHc6b?xh5<<31<7?tHc6b?xh5<<k1<7?tHc6b?xh5<<h1<7?tHc6b?xh5<<i1<7?tHc6b?xh5<<n1<7?tHc6b?xh5<<o1<7?tHc6b?xh5<<l1<7?tHc6b?xh5<?:1<7?tHc6b?xh5<?;1<7?tHc6b?xh5<?81<7?tHc6b?xh5<?91<7?tHc6b?xh5<?>1<7?tHc6b?xh5<??1<7?tHc6b?xh5<?<1<7?tHc6b?xh5<?=1<7?tHc6b?xh5<?21<7?tHc6b?xh5<?31<7?tHc6b?xh5<?k1<7?tHc6b?xh5<?h1<7?tHc6b?xh5<?i1<7?tHc6b?xh5<?n1<7?tHc6b?xh5<?o1<7?tHc6b?xh5<?l1<7?tHc6b?xh5<>:1<7?tHc6b?xh5<>;1<7?tHc6b?xh5<>81<7?tHc6b?xh5<>91<7?tHc6b?xh5<>>1<7?tHc6b?xh5<>?1<7?tHc6b?xh5<><1<7?tHc6b?xh5<>=1<7?tHc6b?xh5<>21<7?tHc6b?xh5<>31<7?tHc6b?xh5<>k1<7?tHc6b?xh5<>h1<7?tHc6b?xh5<>i1<7?tHc6b?xh5<>n1<7?tHc6b?xh5<>o1<7?tHc6b?xh5<>l1<7?tHc6b?xh5<1:1<7?tHc6b?xh5<1;1<7?tHc6b?xh5<181<7?tHc6b?xh5<191<7?tHc6b?xh5<1>1<7?tHc6b?xh5<1?1<7?tHc6b?xh5<1<1<7?tHc6b?xh5<1=1<7?tHc6b?xh5<121<7?tHc6b?xh5<131<7?tHc6b?xh5<1k1<7?tHc6b?xh5<1h1<7?tHc6b?xh5<1i1<7?tHc6b?xh5<1n1<7?tHc6b?xh5<1o1<7?tHc6b?xh5<1l1<7?tHc6b?xh5<0:1<7?tHc6b?xh5<0;1<7?tHc6b?xh5<081<78:{I`7e>{i:=386=4>{I`7e>{i:=3?6=4>{I`7e>{i:=3>6=4>{I`7e>{i98l;6=4={I`7e>{i98l:6=4<{I`7e>{i98l96=4<{I`7e>{i98l86=4<{I`7e>{i98l?6=4<{I`7e>{i98l>6=4<{I`7e>{i98l=6=4<{I`7e>{i98l<6=4<{I`7e>{i98l36=4<{I`7e>{i98l26=4<{I`7e>{i98lj6=4<{I`7e>{i98li6=4<{I`7e>{i98lh6=4<{I`7e>{i98lo6=4<{I`7e>{i98ln6=4<{I`7e>{i98lm6=4<{I`7e>{i9;:;6=4<{I`7e>{i9;::6=4<{I`7e>{i9;:96=4<{I`7e>{i9;:86=4<{I`7e>{i9;:?6=4<{I`7e>{ijk;1<7?tHc6b?xhekh0;6<uGb5c8ykddj3:1=vFm4`9~jged290:wEl;a:mffb=83;pDo:n;|lag`<728qCn9o4}o``b?6=9rBi8l5rncf3>5<6sAh?m6sabe394?7|@k>j7p`md383>4}Oj=k0qclk3;295~Ne<h1vbn=::182Md3i2weo9k50;3xLg2f3tdh8k4?:0yKf1g<ugi><7>51zJa0d=zfj?:6=4>{I`7e>{ik<81<7?tHc6b?xhd=:0;6<uGb5c8yke2<3:1=vFm4`9~jf32290:wEl;a:mg00=83;pDo:n;|l`12<728qCn9o4}oaa=?6=9rBi8l5rnbf1>5<6sAh?m6sace194?7|@k>j7p`ld583>4}Oj=k0qcmk5;295~Ne<h1vbnj9:182Md3i2weoi950;3xLg2f3tdhh54?:0yKf1g<ugio57>51zJa0d=zfjnj6=4>{I`7e>{ikmh1<7?tHc6b?xhc;m0;6<uGb5c8ykb2>3:1=vFm4`9~ja30290:wEl;a:m`0>=83;pDo:n;|lg1<<728qCn9o4}of6e?6=9rBi8l5rne7a>5<6sAh?m6sad4a94?7|@k>j7p`k5e83>4}Oj=k0qcj:e;295~Ne<h1vbi;i:182Md3i2wehn?50;3xLg2f3tdohl4?:0yKf1g<ugnon7>51zJa0d=zfmnh6=4>{I`7e>{ilmn1<7?tHc6b?xhcll0;6<uGb5c8ykbcn3:1=vFm4`9~jac7290:wEl;a:m``7=83;pDo:n;|lga7<728qCn9o4}off7?6=9rBi8l5rnd66>5<6sAh?m6sae4g94?7|@k>j7p`j5g83>4}Oj=k0qck90;295~Ne<h1vbh8>:182Md3i2wei;<50;3xLg2f3tdn:>4?:0yKf1g<ugo=87>51zJa0d=zfl<>6=4>{I`7e>{im?<1<7?tHc6b?xhb>>0;6<uGb5c8ykcd13:1=vFm4`9~j`c5290:wEl;a:ma`5=83;pDo:n;|lfa1<728qCn9o4}ogf1?6=9rBi8l5rndg5>5<6sAh?m6saed594?7|@k>j7p`je983>4}Oj=k0qckj9;295~Ne<h1vbhkn:182Md3i2weihl50;3xLg2f3tdm8i4?:0yKf1g<ugl=:7>51zJa0d=zfo<<6=4>{I`7e>{in?21<7?tHc6b?xha>00;6<uGb5c8yk`1i3:1=vFm4`9~jc0e290:wEl;a:mb3e=83;pDo:n;|le2a<728qCn9o4}od5a?6=9rBi8l5rng4e>5<6sAh?m6safe394?7|@k>j7p`ie`83>4}Oj=k0qchjb;295~Ne<h1vbkkl:182Md3i2wejhj50;3xLg2f3tdmih4?:0yKf1g<uglnj7>51zJa0d=zfol;6=4>{I`7e>{ino;1<7?tHc6b?xhan;0;6<uGb5c8yk`a;3:1=vFm4`9~j462=3:1=vFm4`9~j461m3:1=vFm4`9~j461n3:1=vFm4`9~j46083:1=vFm4`9~j46093:1=vFm4`9~j460:3:1=vFm4`9~j460;3:1=vFm4`9~j460<3:1=vFm4`9~j460=3:1=vFm4`9~j460>3:1=vFm4`9~j460?3:1=vFm4`9~j46b>3:1=vFm4`9~j46b?3:1=vFm4`9~j47793:1=vFm4`9~j477:3:1=vFm4`9~j477;3:1=vFm4`9~j477<3:1=vFm4`9~j477=3:1=vFm4`9~j477>3:1=vFm4`9~j477?3:1=vFm4`9~j47703:1=vFm4`9~j47713:1=vFm4`9~j477i3:1=vFm4`9~j477j3:1=vFm4`9~j477k3:1=vFm4`9~j44b93:1=8uGb5c8yk75j=0;6<uGb5c8yk75j<0;6<uGb5c8yk75kl0;6<uGb5c8yk75ko0;6<uGb5c8yk75l90;6<uGb5c8yk75l80;6<uGb5c8yk75l;0;6<uGb5c8yk75l:0;6<uGb5c8yk75l=0;6<uGb5c8yk75l<0;6<uGb5c8yk75l?0;6<uGb5c8yk75l>0;6<uGb5c8yk75l10;6<uGb5c8yk7>>00;6nuGb5c8yk7>;:0;6<uGb5c8yk7>;=0;6<uGb5c8yk7><m0;6<uGb5c8yk7><l0;6<uGb5c8yk7><o0;6<uGb5c8yk7>=90;6<uGb5c8yk7>=80;6<uGb5c8yk7>=;0;6<uGb5c8yk7>=:0;6<uGb5c8yk7>==0;6<uGb5c8yk7>=<0;6<uGb5c8yk7>=?0;6<uGb5c8yk7>=>0;6<uGb5c8yk7f9j0;6nuGb5c8yk7>m?0;6<uGb5c8yk7>m>0;6<uGb5c8yk7f890;6<uGb5c8yk7f880;6<uGb5c8yk7f8;0;6<uGb5c8yk7f8:0;6<uGb5c8yk7f8=0;6<uGb5c8yk7f8<0;6<uGb5c8yk7f8?0;6<uGb5c8yk7f8>0;6<uGb5c8yk7f810;6<uGb5c8yk7f800;6<uGb5c8yk7f8h0;6<uGb5c8yk7fko0;6nuGb5c8yk7f100;6<uGb5c8yk7f1h0;6<uGb5c8yk7fj:0;6<uGb5c8yk7fj=0;6<uGb5c8yk7fj<0;6<uGb5c8yk7fj?0;6<uGb5c8yk7fj>0;6<uGb5c8yk7fj10;6<uGb5c8yk7fj00;6<uGb5c8yk7fjh0;6<uGb5c8yk7fjk0;6<uGb5c8yk7fjj0;6<uGb5c8yk7fjm0;6<uGb5c8yx{zHIIp>47i:5;;20`1itJKNv>r@ARxyEF
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/ila128.asy b/FEE_ADC32board/project/ipcore_dir/ila128.asy
deleted file mode 100644
index d0b8295..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila128.asy
+++ /dev/null
@@ -1,17 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 ila128
-RECTANGLE Normal 32 32 288 704
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName control[35:0]
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Wide 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName trig0[127:0]
-PINATTR Polarity IN
-
diff --git a/FEE_ADC32board/project/ipcore_dir/ila128.gise b/FEE_ADC32board/project/ipcore_dir/ila128.gise
deleted file mode 100644
index e5369c2..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila128.gise
+++ /dev/null
@@ -1,53 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ila128.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="ila128.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ila128.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="ila128.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1343040841" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1343040841">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="7245039326120553826" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-8847945868067621726" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="4772126188279592210" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/ila128.ngc b/FEE_ADC32board/project/ipcore_dir/ila128.ngc
deleted file mode 100644
index be8fe10..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila128.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$ed:40<,[o}e~g`n;"2*731&=$:,)<4-03841=789:37=>?01234<=789:;<=>?4193456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?01224>6789:;<=>?0123447739:;<=>?0123456?88:0<=>?0122446788::86>?0568455A<2::<<??;132556699;;==>?1393646<8;2J8;MJ12;A12BA<2:<J=:40G015>7682;;==??0123556789;;7<>>002244668<>:<<:4118JJUSS2NKEHRG39;2=0>768O;=7<<7:HLSQQ<SZ@M;0<<8:1<20>712@D[YY4NDEPB843=87;?7<85IORVP?GCL[H7=84?>0916>479?19<7GAPTV9WWJXIVC7=44?>0286D6F:1:3>?>=212352=4:90BB][[:FCM@ZO;;831<3?=;209MKVR\3NBM1=>:1<26>552@D[YY4KIC>05?699:18>7AZTQWW>AIF4:;1<3?<;209KPRW]]0OCO2<1;2=53=4>3CECXZ5CNLWVJJ;;<0;2<5;4:6245763=0BB][[:EKSE95=87;:794FNQWW>AOWJ591<3??;58JJUSS2^OJ0>4?>0280?OIX\^1[HL33;2=57=32F__\XZ5DNRB86<7688087AZTQWW>AIWJ591<3??;4761023<OLMJKKJEd96>LHW]]0J094?>g95ri~6;9~mj96;-2683C@A991<JKHIFGDEBC@ANOL:75<4A108E44<I;80M>??;@:B47>58123<=6?059B85833H6:295N<3<7?D:46?1J094?>59B81853HH37LJKR@>3:<=FLMXJ0<>19:CG@WG;98427LJKR@>26;?<IMNYM1?<>89B@ATF48>5n6OKDSC?50<7601JHI\N<07=<>GCL[K7=364AEFQE94902KOH_O33?:8EABUI5>546OKDSC?1;><IMNYM1818:CG@WG;?720MIJ]A=:=<>GCL[K75364AEFQF96912KOH_L311<:?DBCZK6:=374AEFQF975601JHI\M<01==>GCL[H7=90m;@FGVG:6=3:556OKDS@?508?3HNO^O2>>99B@ATE4;437LJKRC>0:==FLMXI0907;@FGVG:2611JHI\M<7<;?DBCZK6<255NDEPA8=8?3HNO^O26>29BHI><J\YTECH@1:A1?FGc3JKXOLJJIONBPDb<KHYHMIKFNMCWFa=DIZIJHHGARDEB`>EF[JKOID@]EF@f?FGTKHNNCXZCAUCf?FGTKHNNCXZCAU@f?FGTKHNNCXZ]EFCf?FGTKHNNCXZ]EF@1?FC6:2ICINEPLHAFJVCX\PZN>6MF3:AOO1=DDB:=7NBD1925?FJL:>:>7NBD2Y:8GIM5P82;96MCK827?FJLI<1H@FO>7:AOOD7C:>1H@FO>D558GIMF9M2?7NBDB49@HND6=2IGGN?:;BNH@43<KEAOZn5LLJFU[AOQAMO>7NBDFY:8GIMAP82;96MCK^K0?FJU12IDA@G[TDFb?FII\[EG0=0m;BMMPWIK48:5n6M@NUPLH9766k1HCCZ]OM>26;d<KFD_^BB312<a?FII\[EG0<:1b:ALJQTHD5;>2o5LOOVQKI:6>7h0OB@[RNN?528e3JEEX_AC<0:=f>EHF]XD@1?6>`9@KKRUGE6:2o5LOOVQKI:587h0OB@[RNN?648e3JEEX_AC<30=f>EHF]XD@1<<>c9@KKRUGE6983l4CNLWVJJ;:<4i7NAATSMO8709j2IDBY\@L=04:g=DGG^YCA2=8?`8GJHSZFF7>40n;BMMPWIK4;4i7NAATSMO8669j2IDBY\@L=12:g=DGG^YCA2<2?`8GJHSZFF7?>0m;BMMPWIK4:>5h6M@NUPLH952294i7NAATSMO8639i2IDBY\@L=1=e>EHF]XD@1:1a:ALJQTHD5?5m6M@NUPLH909i2IDBY\@L=5=e>EHF]XD@161a:ALJQTHD535=95LOSG\C@HBZH^BCCQFNGM4?FTBI]OO=6J9;E0\GIM33M9;>?5KI79GMD:76>1OEL2>0?58@LG;984<7IGN<00=3>BNI5;82:5KI@>20;1<L@K7=808;EKB8409?2NBM1?8>69GMD:607=0HDO318<5?AOF484<7IGN<32=3>BNI58:2:5KI@>16;1<L@K7>>08;EKB8729?2NBM1<:>69GMD:5>7=0HDO326<4?AOF4;25;6JFA=0::3=CAH692:5KI@>04;?<L@K7?<4?>69GMD:497<0HDO33?48@LG;<7<0HDO35?48@LG;>7<0HDO37?48@LG;07<0HDO39?48@LD;87=0HDL311<4?AOE48;5;6JFB=31:2=CAK6:?394DH@?51803MCI0<;17:FJF9716>1OEO2>7?58@LD;914<7IGM<0;=2>BNJ5;5;6JFB=03:2=CAK69=394DH@?67803MCI0?=17:FJF9436>1OEO2=5?58@LD;:?4<7IGM<35=3>BNJ5832:5KIC>1=;0<L@H7>394DH@?758>3MCI0>?50?58@LD;;84=7IGM<2<5?AOE4=4=7IGM<4<5?AOE4?4=7IGM<6<5?AOE414=7IGM<8<4?AOWI5:5;6JFP@>2:2=CAYK7>374DHRB86<76>1OE]O33?58@LVE494<7IG_B=3=3>BNXK69245KIQ@?7?69?2NB\O2<>79GKD:76>1OCL2>0?58@JG;984<7IAN<00=3>BHI5;82:5KO@>20;1<LFK7=808;EMB8409?2NDM1?8>69GKD:607=0HBO318<5?AIF484<7IAN<32=3>BHI58:2:5KO@>16;1<LFK7>>08;EMB8729?2NDM1<:>69GKD:5>7=0HBO326<4?AIF4;25;6J@A=0::3=CGH692:5KO@>04;?<LFK7?<4?>69GKD:497<0HBO33?48@JG;<7<0HBO35?48@JG;>7<0HBO37?48@JG;07<0HBO39?58@JGXZLM=7IAM<1<4?AIE48:5;6J@B=32:2=CGK6:>394DN@?56803MEI0<:17:FLF9726>1OCO2>6?58@JD;9>4<7IAM<0:=3>BHJ5;22;5KOC>2:2=CGK69<394DN@?64803MEI0?<17:FLF9446>1OCO2=4?58@JD;:<4<7IAM<34=3>BHJ58<2:5KOC>1<;1<LFH7>409;EMA87803MEI0>>19:FLF956294<7IAM<23=2>BHJ595:6J@B=6=2>BHJ5?5:6J@B=4=2>BHJ5=5:6J@B=:=2>BHJ535;6J@B^PFC2=CGYK7<394DNRB84803ME[M1<19:FLTD:4294<7IA_A=1=3>BHXK6;2:5KOQ@?5;1<LFZI0?06;EMSF95=87=0HB^M<2<6?AYDDB;0I?5J439FB6=BFH90ICL;;G2331=A>8:97KJ>0:DG30D>;8OH:9O72133?CB0=ON<9KJ85@:146=ALJ>0JIMJ3:DGA==ALO23H56<;GFS7>@CZ=1MH_K<;GFP55=ANLKNMHO:552741633OLM<95IFGG24>@ANO;:==?>113255773OLMJKHIF4761526=8:0JKHIFGDE<D>?0123==5IFGDEBC@ANOLJM5>>0:DEBC@ANOLMJKHIFD3;?CTHE)(O>RMCK#"WK%@A[)^BK<64FSMN$C@T(]E+.I<PCMI!$QO@02LYC@QACG38C<=@IGNTODQF9:EBJAYN494i7JOAD^K?5569j2MJBIQF<022:g=@IGNTE1??2?`8CDHCW@6:<>0m;FCM@ZO;99>5n6INNE]J84626k1LMCJPI=332;d<OHDOSD2>06<a?BGILVC7==61b:EBJAYN48:22l5HAOF\M9776k1LMCJPI=324;d<OHDOSD2>10<a?BGILVC7=<<1b:EBJAYN48;82o5HAOF\M976<7h0KL@K_H>2508e3NKEHRG3104=f>AFFMUB0<?8>c9DEKBXA5;:43l4G@LG[L:6904j7JOAD^K?548e3NKEHRG3132=f>AFFMUB0<<>>c9DEKBXA5;9>3l4G@LG[L:6::4i7JOAD^K?5729j2MJBIQF<006:g=@IGNTE1?=6?`8CDHCW@6:>:0m;FCM@ZO;9;25n6INNE]J844>6h1LMCJPI=31:g=@IGNTE1?<0?`8CDHCW@6:?<0m;FCM@ZO;9:85n6INNE]J84546k1LMCJPI=300;d<OHDOSD2>34<a?BGILVC7=>81b:EBJAYN489<2o5HAOF\M97407h0KL@K_H>27<8f3NKEHRG312<a?BGILVC7=9>1b:EBJAYN48>:2o5HAOF\M973:7h0KL@K_H>2068e3NKEHRG3156=f>AFFMUB0<::>c9DEKBXA5;?:3l4G@LG[L:6<>4i7JOAD^K?51>9j2MJBIQF<06::d=@IGNTE1?;>c9DEKBXA5;><3l4G@LG[L:6=84i7JOAD^K?5049j2MJBIQF<070:g=@IGNTE1?:4?`8CDHCW@6:980m;FCM@ZO;9<<5n6INNE]J84306k1LMCJPI=36<;d<OHDOSD2>58<b?BGILVC7=80m;FCM@ZO;9?:5n6INNE]J84066k1LMCJPI=356;d<OHDOSD2>62<a?BGILVC7=;:1b:EBJAYN48<>2o5HAOF\M971>7h0KL@K_H>2228e3NKEHRG317:=f>AFFMUB0<86>`9DEKBXA5;=2o5HAOF\M97087h0KL@K_H>2348e3NKEHRG3160=f>AFFMUB0<9<>c9DEKBXA5;<83l4G@LG[L:6?<4i7JOAD^K?5209j2MJBIQF<054:g=@IGNTE1?88?`8CDHCW@6:;40n;FCM@ZO;9>4i7JOAD^K?5=69j2MJBIQF<0:2:g=@IGNTE1?72?`8CDHCW@6:4>0m;FCM@ZO;91>5n6INNE]J84>26k1LMCJPI=3;2;d<OHDOSD2>86<a?BGILVC7=561b:EBJAYN48222l5HAOF\M97?6k1LMCJPI=3:4;d<OHDOSD2>90<a?BGILVC7=4<1b:EBJAYN48382o5HAOF\M97><7h0KL@K_H>2=08e3NKEHRG3184=f>AFFMUB0<78>c9DEKBXA5;243l4G@LG[L:6104j7JOAD^K?5<8>3NKEHRG31?`8CDHCW@69<=0m;FCM@ZO;:9;5n6INNE]J87656k1LMCJPI=037;d<OHDOSD2=05<a?BGILVC7>=;1b:EBJAYN4;:=2o5HAOF\M947?7h0KL@K_H>14=8e3NKEHRG321;=e>AFFMUB0?>1b:EBJAYN4;;;2o5HAOF\M94697h0KL@K_H>1578e3NKEHRG3201=f>AFFMUB0??;>c9DEKBXA58:93l4G@LG[L:59?4i7JOAD^K?6419j2MJBIQF<33;:g=@IGNTE1<>9?c8CDHCW@69=3l4G@LG[L:5:94i7JOAD^K?6779j2MJBIQF<301:g=@IGNTE1<=3?`8CDHCW@69>90m;FCM@ZO;:;?5n6INNE]J87416k1LMCJPI=013;d<OHDOSD2=29<a?BGILVC7>?71a:EBJAYN4;85n6INNE]J87576k1LMCJPI=005;d<OHDOSD2=33<a?BGILVC7>>=1b:EBJAYN4;9?2o5HAOF\M944=7h0KL@K_H>1738e3NKEHRG3225=f>AFFMUB0?=7>c9DEKBXA58853o4G@LG[L:5;7h0KL@K_H>1058e3NKEHRG3253=f>AFFMUB0?:=>c9DEKBXA58??3l4G@LG[L:5<=4i7JOAD^K?6139j2MJBIQF<365:g=@IGNTE1<;7?`8CDHCW@69850m;FCM@ZO;:=35m6INNE]J8729j2MJBIQF<373:g=@IGNTE1<:1?`8CDHCW@699?0m;FCM@ZO;:<95n6INNE]J87336k1LMCJPI=061;d<OHDOSD2=57<a?BGILVC7>891b:EBJAYN4;?32o5HAOF\M94217k0KL@K_H>11;d<OHDOSD2=61<a?BGILVC7>;?1b:EBJAYN4;<92o5HAOF\M941;7h0KL@K_H>1218e3NKEHRG3277=f>AFFMUB0?89>c9DEKBXA58=;3l4G@LG[L:5>14i7JOAD^K?63?9i2MJBIQF<34=f>AFFMUB0?9?>c9DEKBXA58<=3l4G@LG[L:5?;4i7JOAD^K?6259j2MJBIQF<357:g=@IGNTE1<85?`8CDHCW@69;;0m;FCM@ZO;:>=5n6INNE]J871?6k1LMCJPI=04=;g<OHDOSD2=7?`8CDHCW@694=0m;FCM@ZO;:1;5n6INNE]J87>56k1LMCJPI=0;7;d<OHDOSD2=85<a?BGILVC7>5;1b:EBJAYN4;2=2o5HAOF\M94??7h0KL@K_H>1<=8e3NKEHRG329;=e>AFFMUB0?61b:EBJAYN4;3;2o5HAOF\M94>97h0KL@K_H>1=78e3NKEHRG3281=f>AFFMUB0?7;>c9DEKBXA58293l4G@LG[L:51?4i7JOAD^K?6<19j2MJBIQF<3;;:g=@IGNTE1<69?c8CDHCW@695374G@LG[L:56k1LMCJPI=134;d<OHDOSD2<00<a?BGILVC7?=<1b:EBJAYN4::82o5HAOF\M957<7h0KL@K_H>0408e3NKEHRG3314=f>AFFMUB0>>8>c9DEKBXA59;43l4G@LG[L:4804j7JOAD^K?758e3NKEHRG3302=f>AFFMUB0>?>>c9DEKBXA59:>3l4G@LG[L:49:4i7JOAD^K?7429j2MJBIQF<236:g=@IGNTE1=>6?`8CDHCW@68=:0m;FCM@ZO;;825h6INNE]J867>294i7JOAD^K?74?9i2MJBIQF<23=e>AFFMUB0><1a:EBJAYN4:95m6INNE]J8629i2MJBIQF<27=e>AFFMUB0>81a:EBJAYN4:=5m6INNE]J86>9i2MJBIQF<2;==>AFFMUB0>0n;FCM@ZO;<94j7JOAD^K?048f3NKEHRG343<b?BGILVC78>0n;FCM@ZO;<=4j7JOAD^K?008f3NKEHRG347<b?BGILVC78:0n;FCM@ZO;<14j7JOAD^K?0<8>3NKEHRG34?c8CDHCW@6><3o4G@LG[L:297k0KL@K_H>66;g<OHDOSD2:3?c8CDHCW@6>83o4G@LG[L:2=7k0KL@K_H>62;g<OHDOSD2:7?c8CDHCW@6>43o4G@LG[L:21730KL@K_H>6:d=@IGNTE18?>`9DEKBXA5<:2l5HAOF\M9056h1LMCJPI=40:d=@IGNTE18;>`9DEKBXA5<>2l5HAOF\M9016h1LMCJPI=44:d=@IGNTE187>`9DEKBXA5<2245HAOF\M909i2MJBIQF<62=e>AFFMUB0:?1a:EBJAYN4>85m6INNE]J8259i2MJBIQF<66=e>AFFMUB0:;1a:EBJAYN4><5m6INNE]J8219i2MJBIQF<6:=e>AFFMUB0:719:EBJAYN4>4j7JOAD^K?<58f3NKEHRG380<b?BGILVC74?0n;FCM@ZO;0:4j7JOAD^K?<18f3NKEHRG384<b?BGILVC74;0n;FCM@ZO;0>4j7JOAD^K?<=8f3NKEHRG388<:?BGILVC743o4G@LG[L:>87k0KL@K_H>:5;g<OHDOSD262?c8CDHCW@62?3o4G@LG[L:><7k0KL@K_H>:1;g<OHDOSD266?c8CDHCW@62;3o4G@LG[L:>07k0KL@K_H>:=;d<OHDOSD26:1<:?BGILVC75384G@LG[J5<OGN=7E[PSDV2?L4<A980E<<4I308M64<A=80E864IOKWTZ6702CEEY^P00:8MKOSXV:946GAIUR\46><AGC_\R>;8:KMMQVX8<20ECG[P^25<>OIA]ZT<:64IOKWTZ6?02CEEY^P08:8MKOSXV:J46GAIUR\4G><AGC_\R>L8:KMMQVX8M20ECG[P^2F<>OIA]ZT<K74IOKWWQGSM>1BBDZP0158MKOSW9;<7D@FT^213>OIA]U;?:5FNHV\411<AGC_S=;8;HLJPZ61?2CEEYQ?769JJLRX81=0ECG[_1;4?LHN\V:J;6GAIU]3F2=NF@^T<N94IOKW[5B03@DBXR>J7:KMMQY7N>1BBDZP1158MKOSW8;<7D@FT^313>OIA]U:?:5FNHV\511<AGC_S<;8;HLJPZ71?2CEEYQ>769JJLRX91=0ECG[_0;4?LHN\V;J;6GAIU]2F2=NF@^T=N94IOKW[4B03@DBXR?J7:KMMQY6N>1BBDZP2158MKOSW;;<7D@FT^013>OIA]U9?:5FNHV\611<AGC_S?;8;HLJPZ41?2CEEYQ=769JJLRX:1=0ECG[_3;4?LHN\V8J;6GAIU]1F2=NF@^T>N94IOKW[7B03@DBXR<J7:KMMQY5N>1BBDZP3158MKOSW:;<7D@FT^113>OIA]U8?:5FNHV\711<AGC_S>;8;HLJPZ51?2CEEYQ<769JJLRX;1=0ECG[_2;4?LHN\V9J;6GAIU]0F2=NF@^T?N94IOKW[6B03@DBXR=J7:KMMQY4N>1BBDZP4158MKOSW=;<7D@FT^613>OIA]U??:5FNHV\011<AGC_S9;8;HLJPZ21?2CEEYQ;769JJLRX<1=0ECG[_5;4?LHN\V>J;6GAIU]7F2=NF@^T8N94IOKW[1B03@DBXR:J7:KMMQY3N>1BBDZP5158MKOSW<;<7D@FT^713>OIA]U>?:5FNHV\111<AGC_S8;8;HLJPZ31?2CEEYQ:769JJLRX=1=0ECG[_4;4?LHN\V?J;6GAIU]6F2=NF@^T9N94IOKW[0B03@DBXR;J7:KMMQY2N>1BBDZP6158MKOSW?;<7D@FT^413>OIA]U=?:5FNHV\211<AGC_S;;8;HLJPZ01?2CEEYQ9769JJLRX>1=0ECG[_7;4?LHN\V<J;6GAIU]5F2=NF@^T:N94IOKW[3B03@DBXR8J7:KMMQY1N>1BBDZP7158MKOSW>;<7D@FT^513>OIA]U<?:5FNHV\311<AGC_S:;8;HLJPZ11?2CEEYQ8769JJLRX?1=0ECG[_6;4?LHN\V=J;6GAIU]4F2=NF@^T;N94IOKW[2B03@DBXR9J7:KMMQY0N?1BBDZPA79JJLRXJ01BBDZPFHNF7>OI^:<0ERG\_UGQILHF\@EES^BFCD]MA5(NW\YNSB[[PTV\V@AXFL:%YRA]EF02?LYN[V^N^@GAAUKLJZUKAJOTBH>!U^OV\C473@U[M_ZFAM]PHLEB&\ULMCJPSSN\WIODM;n0ERYGOMG\WIODM'MT_AGLE^KG\^6Z&\ULMCJPSSN\WIODM;o0ERYGOMG\WIODM'MT_AGLE^KG\^77U'_TKL@K_RPO[VJNKL8n7DQXHNNF[VJNKL$LS^BFCD]J@]]69T$^SJOAD^QQHZUKAJO9i6GPWIMOAZUKAJO%KR]CIBG\MA^\9;W%YRINNE]PVIYTD@IN>h5F_VJLH@YTD@IN"JQ\LHAF[LB_S89V"XQHAOF\WWJX[ECHI?k4I^UKKICX[ECHI#IPSMK@AZOCPR;?Q#[PG@LG[VTKWZFBOH<j;H]TLJJBWZFBOH H_RNJG@YNLQQ:9P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP=P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP>P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP?P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP8P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP9P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP:P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP;P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP4P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP5P Z_FCM@ZUUDVYGENK;;JGFT6=KLJ80@D<4LN48HJGCMM<0@BMDEE58HJANKHF?7A[[159OQQ433E__?95CUU67?ISS==1GYY8;;LQFP2=J]QIRSA;4MTZE30=J]QL3o6CnjnpUawunggi0Ad``rWgqwlii:2D;>6@>3:L0<6=I<990B9?<;O613>HB\^EYG;5AOBNJT2=IGDOYKH:4NNLF5>I?3F$<:ujPL09S0>VFZ]k0\D@PBTQJ@]d<X@DTNX]AALG:?UMX@E__B@=4PSG5?UUCGGO:7\=4Q070?T5692X=7_OBB24e?WGJWLR_IC]FOO]Bb>TFEVOSXH@\INL\Ff=UMHNT[DJ[H^C`?WCFLV]BHYFPB79QABEBI?1YIJMJB69QAVCSW@>0^AAL1:Q7?VGAM8;0_E\JG^G[PWGD\VDLOh5\HSGD[HOIWZCQI<=4SHO\GJJKAZCDBRMGEBI;?VOJWDEOI;5\OTP@A0=TZE;=:6]]L04F3>UUDJ;=I:5\RMA06@g<[[FTMRG30?`8WWJXIVC7==0m;RPO[DYN48;5n6]]L^C\M9756k1X^AQN_H>27;d<[[FTMRG315<a?VTKWHUB0<;1b:QQHZGXA5;=2o5\RM]B[L:6?7h0__BPA^K?5=8c3ZXGSLQF<0;94;d<[[FTMRG318<b?VTKWHUB0<0n;RPO[DYN4;4j7^\C_@]J868f3ZXGSLQF<5<b?VTKWHUB080n;RPO[DYN4?4j7^\C_@]J828f3ZXGSLQF<9<b?VTKWHUB0407;RPO[FCXA01X^AQLLJ]J3>UUDVNTE:5\RM]R[J1<[[\J@RO8;RPUEIYE<2YX^L:4SRPA2>USI]_X46ZJRLKMEI><\@GN_]KL3:VMI2=SFDUEIY64TSKD4969i2^YEJ>3112=e>RUAN:7==?1a:VQMB6;9985m6Z]IF2?5559i2^YEJ>3116=e>RUAN:7==;1a:VQMB6;99<5m6Z]IF2?5519i2^YEJ>311:=e>RUAN:7==719:VQMB6;994j7Y\FG1>2558f3]XBK=2>10<b?QTNO96:=?0n;UPJC5:69:4j7Y\FG1>2518f3]XBK=2>14<b?QTNO96:=;0n;UPJC5:69>4j7Y\FG1>25=8f3]XBK=2>18<:?QTNO96:=3o4TSKD497587k0X_GH0=315;g<\[CL<1?=2?c8PWO@85;9?3o4TSKD4975<7k0X_GH0=311;g<\[CL<1?=6?a8PWO@85;9;7>1a:VQMB6;9;=556Z]IF2?578>3]XBK=2>3?;8PWO@85;?245[RHE3843912^YEJ>317<:?QTNO96:;374TSKD497?601_^DI?<0;=<>RUAN:7=374TSKD4947601_^DI?<33==>RUAN:7>?06;UPJC5:5;730X_GH0=07:<=SZ@M;0?;19:VQMB6;:?427Y\FG1>13;?<\[CL<1<7>89WVLA74;3546Z]IF2?6;?<\[CL<1=?>89WVLA74:;556Z]IF2?778>3]XBK=2<3?;8PWO@859?245[RHE3863912^YEJ>337<:?QTNO968;374TSKD495?601_^DI?<2;=<>RUAN:7?374TSKD4927601_^DI?<53==>RUAN:78?06;UPJC5:3;730X_GH0=67:<=SZ@M;09;19:VQMB6;<?427Y\FG1>73;?<\[CL<1:7>89WVLA74=3546Z]IF2?0;?<\[CL<1;?>89WVLA74<;556Z]IF2?178>3]XBK=2:3?;8PWO@85??245[RHE3803912^YEJ>357<:?QTNO96>;374TSKD493?601_^DI?<4;=<>RUAN:79374TSKD4907601_^DI?<73==>RUAN:7:?06;UPJC5:1;730X_GH0=47:<=SZ@M;0;;19:VQMB6;>?427Y\FG1>53;?<\[CL<187>89WVLA74?3546Z]IF2?2;?<\[CL<19?>89WVLA74>;556Z]IF2?378>3]XBK=283?;8PWO@85=?245[RHE3823912^YEJ>377<:?QTNO96<;374TSKD491?601_^DI?<6;=<>RUAN:7;374TSKD49>7601_^DI?<93==>RUAN:74?06;UPJC5:?;730X_GH0=:7:<=SZ@M;05;19:VQMB6;0?427Y\FG1>;3;?<\[CL<167>89WVLA7413546Z]IF2?<;?<\[CL<17?>89WVLA740;556Z]IF2?=78>3]XBK=263?;8PWO@853?245[RHE38<3912^YEJ>397<:?QTNO962;374TSKD49??601_^DI?<8;=<>RUAN:753:4TSWFf>RTWM8TXBQ[2c9WWZL5W]ETH?l4TR]I7ZRHWM8i7Y]PJ5]WKZB5<2^R\H=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP<P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW=S!I^QQHQYIMV:%JK:?;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP==>R.H]PVIRXFLU;"IBV92g8Q5)NWGETH#[PIMC,MZBV&\UO]\!KLX]:*AJ^W0ULICU>01_-MZUUD]UEIR>!FG63?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T113^*LYTZE^TBHQ?.ENZ=6c<]9%BSCAPD/W\MIG(AVNZ"XQKQP-GH\Y>&MFRS4QHEOY244[)AVYY@YQAE^2-BC273\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX554Z&@UX^AZPND]3*AJ^1:o0Y=!F_OM\@+SXAEK$ERJ^.T]GUT)CDPU2"IBV_8]DAK]68;W%ER]]LU]MAZ6)NO>;7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\999V"DQ\RMV\J@Y7&MFR5>k4U1-J[KIXL'_TEAO I^FR*PYCYX%O@TQ6.ENZ[<Y@MGQ:<>S!I^QQHQYIMV:%JK:?;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP==:R.H]PVIRXFLU;"IBV92g8Q5)NWGETH#[PIMC,MZBV&\UO]\!KLX]:*AJ^W0ULICU>05_-MZUUD]UEIR>!FG63?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T117^*LYTZE^TBHQ?.ENZ=6c<]9%BSCAPD/W\MIG(AVNZ"XQKQP-GH\Y>&MFRS4QHEOY240[)AVYY@YQAE^2-BC273\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX550Z&@UX^AZPND]3*AJ^1:o0Y=!F_OM\@+SXAEK$ERJ^.T]GUT)CDPU2"IBV_8]DAK]68?W%ER]]LU]MAZ6)NO>;7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\99=V"DQ\RMV\J@Y7&MFR5>k4U1-J[KIXL'_TEAO I^FR*PYCYX%O@TQ6.ENZ[<Y@MGQ:<:S!I^QQHQYIMV:%JK:?;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP==6R.H]PVIRXFLU;"IBV92g8Q5)NWGETH#[PIMC,MZBV&\UO]\!KLX]:*AJ^W0ULICU>09_-MZUUD]UEIR>!FG63?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T11;^*LYTZE^TBHQ?.ENZ=6c<]9%BSCAPD/W\MIG(AVNZ"XQKQP-GH\Y>&MFRS4QHEOY24<[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX55[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^77U'CT__B[_OG\4+@A<91^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^768T$BS^\CT^LF[5(CDP38i6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS8;;Q#GPSSNW[KCX8'LM8=5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;:=P F_RPOPZHBW9$O@T7<e:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW<?>]/K\WWJSWGOT<#HI419V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?>2\,J[VTK\VDNS= KLX;0a>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[031Y+OX[[F_SCKP0/DE05=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ327X(NWZXGXR@J_1,GH\?4m2_;#DQAO^F-QZOKI&CTH\ Z_ESR+AJ^W0$O@TQ6_FGM_474U'CT__B[_OG\4+@A<91^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^76<T$BS^\CT^LF[5(CDP38i6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS8;?Q#GPSSNW[KCX8'LM8=5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;:9P F_RPOPZHBW9$O@T7<e:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW<?:]/K\WWJSWGOT<#HI419V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?>6\,J[VTK\VDNS= KLX;0a>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[035Y+OX[[F_SCKP0/DE05=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ323X(NWZXGXR@J_1,GH\?4m2_;#DQAO^F-QZOKI&CTH\ Z_ESR+AJ^W0$O@TQ6_FGM_470U'CT__B[_OG\4+@A<91^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^760T$BS^\CT^LF[5(CDP38i6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS8;3Q#GPSSNW[KCX8'LM8=5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;:5P F_RPOPZHBW9$O@T7<e:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW<?6]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?>]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T10_-MZUUD]UEIR>!FG63?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T132^*LYTZE^TBHQ?.ENZ=6c<]9%BSCAPD/W\MIG(AVNZ"XQKQP-GH\Y>&MFRS4QHEOY265[)AVYY@YQAE^2-BC273\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX577Z&@UX^AZPND]3*AJ^1:o0Y=!F_OM\@+SXAEK$ERJ^.T]GUT)CDPU2"IBV_8]DAK]6:8W%ER]]LU]MAZ6)NO>;7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9;8V"DQ\RMV\J@Y7&MFR5>k4U1-J[KIXL'_TEAO I^FR*PYCYX%O@TQ6.ENZ[<Y@MGQ:>?S!I^QQHQYIMV:%JK:?;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=?=R.H]PVIRXFLU;"IBV92g8Q5)NWGETH#[PIMC,MZBV&\UO]\!KLX]:*AJ^W0ULICU>22_-MZUUD]UEIR>!FG63?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T136^*LYTZE^TBHQ?.ENZ=6c<]9%BSCAPD/W\MIG(AVNZ"XQKQP-GH\Y>&MFRS4QHEOY261[)AVYY@YQAE^2-BC273\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX573Z&@UX^AZPND]3*AJ^1:o0Y=!F_OM\@+SXAEK$ERJ^.T]GUT)CDPU2"IBV_8]DAK]6:<W%ER]]LU]MAZ6)NO>;7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9;<V"DQ\RMV\J@Y7&MFR5>k4U1-J[KIXL'_TEAO I^FR*PYCYX%O@TQ6.ENZ[<Y@MGQ:>;S!I^QQHQYIMV:%JK:?;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=?9R.H]PVIRXFLU;"IBV92g8Q5)NWGETH#[PIMC,MZBV&\UO]\!KLX]:*AJ^W0ULICU>26_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T13_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ31Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ30Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX56[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX51[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^73U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^72U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9<W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9?W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;=Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;<Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=:S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=5S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?7]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?6]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T18_-MZUUD]UEIR>!FG1f?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T1\,J[VTK\VDNS= KLX;0g>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[0_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T21_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ03Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ02Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX64[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX67[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^45U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^44U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\::W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\:=W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR8?Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR8>Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>8S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>;S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<9]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<8]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T26_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T29_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ0;Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ0:Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX6<[)AVYY@YQAE^2-BC5b3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX6X(NWZXGXR@J_1,GH\?4k2_;#DQAO^F-QZOKI&CTH\ Z_ESR+AJ^W0$O@TQ6_FGM_7[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX75[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^57U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^56U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;8W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;;W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR99Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR98Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP?>S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP?9S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV=;]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV=:]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T34_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T37_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ15Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ14Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX72[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX7=[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^5?U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^5>U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;0W%ER]]LU]MAZ6)NO9n7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;T$BS^\CT^LF[5(CDP38o6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS:W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<9W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>;Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>:Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP8<S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP8?S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV:=]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV:<]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T42_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T45_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ67Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ66Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX00[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX03[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^21U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^20U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<>W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\<1W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>3Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR>2Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP84S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP8P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW9S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP9=S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;?]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;>]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T50_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T53_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ71Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ70Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX16[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX11[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^33U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^32U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\=<W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\=?W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR?=Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR?<Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP9:S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP95S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;7]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV;6]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T58_-MZUUD]UEIR>!FG1f?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T5\,J[VTK\VDNS= KLX;0g>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[4_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T61_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ43Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ42Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX24[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX27[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^05U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^04U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\>:W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\>=W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR<?Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR<>Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP:8S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP:;S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV89]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV88]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T66_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T69_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ4;Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ4:Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX2<[)AVYY@YQAE^2-BC5b3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX2X(NWZXGXR@J_1,GH\?4k2_;#DQAO^F-QZOKI&CTH\ Z_ESR+AJ^W0$O@TQ6_FGM_3[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX35[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^17U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^16U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\?8W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\?;W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR=9Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR=8Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP;>S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP;9S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV9;]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV9:]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T74_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T77_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ55Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ54Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX32[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX3=[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^1?U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^1>U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\?0W%ER]]LU]MAZ6)NO9n7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\?T$BS^\CT^LF[5(CDP38o6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS>W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\09W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR2;Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR2:Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP4<S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP4?S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV6=]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV6<]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T82_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T85_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ:7Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ:6Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX<0[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX<3[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^>1U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^>0U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\0>W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\01W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR23Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR22Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP44S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP4P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW5S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP5=S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV7?]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV7>]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T90_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T93_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ;1Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ;0Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX=6[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX=1[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^?3U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^?2U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\1<W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\1?W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR3=Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR3<Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP5:S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP55S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV77]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV76]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T98_-MZUUD]UEIR>!FG1f?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T9\,J[VTK\VDNS= KLX;0g>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[8_-MZUUD]UEIR>!FG01?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8585<2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5;;<3<;;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<022:72<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;9985>95Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2>02<10>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt977<78?7X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0<>:>368Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?5509:=1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6:<:0=4:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=33<;433\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw48:22?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~311<10>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt976878?7X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0<?>>368Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?5449:=1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6:=>0=4:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=320;433\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw48;>2?:4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~3104=61=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:69>4986[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1?>8?07?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos847>6;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7=<0=4:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=314;433\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw488:2?:4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~3130=61=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:6::4986[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1?=4?07?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos84426;>0Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7=?81259V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>26285;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5;92?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~312<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9736;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7=80=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=35:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;9>49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1?7>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?5<85:2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5;5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2=0?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8779::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey69>3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<31=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:5<7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0?;1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>12;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4;=5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2=8?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos87?9:;1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey692?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~331<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9566;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7??0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=10:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;;=49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1=:>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?7385;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx59<2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~339<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt95>6;80Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7?3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<52=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:397887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{09<1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>77;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4=>5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2;5?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8109::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6?;3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<5:=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:317897X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{090=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=73:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;=849?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1;=>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?1685;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5??2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~354<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9316;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz79:0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=7;:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;=049>6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1;1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>54;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4?;5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}292?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8359::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6=83<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<77=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:1>7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0;91229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>5<;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4?35>?5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}29>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?3585;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5=:2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~373<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9146;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7;90=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=56:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;??49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|198>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?3=85;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5=22?<4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~37?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8=69::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey63=3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<90=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:?;7887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{05:1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>;1;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw41<5>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}277?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8=>9::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6353<=;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<9<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9?76;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz75<0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=;1:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;1:49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|17;>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?=085;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx53=2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~396<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9??6;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7540=2:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=;=16=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YRA]_SF\VJQXMG?27X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\KWYU[]UYHR\@W^UJ@@043\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"GPWHFWLZ>)}V~h;85Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,MZQNL]BT4#{Ptb]3+\CTWE__:#[PLTV520=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$ERYFDUJ\<+sX|jU:9i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,gjsi|5:59i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,gjsi|5;59i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,gjsi|5859i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,gjsi|5959i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,gjsi|5>59i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,gjsi|5?59i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,gjsi|5<59i5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,gjsi|5=5955Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,vvr2m2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!{c^tfg969=l1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO tb]uaf:66?:0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/t]`jq)DA5;5:=5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&IB0?090:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[D)rWjd#NG33?43?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz CH>7:36<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UJ#xQlnu-@M939>91^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*EN4?4=<6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'JC7;3;i;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$H1>15g9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZG(}Viex"J31?7e?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz D=0=1c=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.F?7;3a3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,@929=o1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*B;=7?m7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(L5<59k5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&N7;38m;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$KV>R.FlK*PYJ]QIR:;5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&MP<P Z_GFQA33<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UJ#xQlnu-D_5[)]VF^X;94U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%LW=S!U^ZLVF_1j2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!z_blw+B]6U'MeD#[PMTZ@]30<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UJ#xQlnu-D_4[)]VLO^H8:;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$KV?R.T]OQQ003\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,C^7Z&\USC_MV6c9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZG(}Viex"IT2\,DjM(RWD_SOT89;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$KV<R.T]E@WC1=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!z_blw+B]5U'_T@XZ97:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[D)rWjd#JU=]/W\\JTDQ?h0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/t]`jq)@S:W%KcF!U^OV\F_1>2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!z_blw+B]4U'_TJI\J649V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZG(}Viex"IT3\,V[ISS>>1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*A\;T$^SUA]CX4a?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz GZ6^*BhO&\UFYUMV679V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZG(}Viex"IT4\,V[CBUM??0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/t]`jq)@S=W%YRBZT758Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYF'|Uhby!H[5_-QZ^HZJS=n6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'NQ>Q#IaH/W\IP^DQ?<0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/t]`jq)@S<W%YRHKRD46?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz GZ7^*PYK]]<<7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(OR?V"XQWOSAZ2g=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.EX2X(@fA$^S@[WCX45?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz GZ4^*PYAL[O=96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'NQ=Q#[PLTV53>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWH%~Sn`{/FY5Y+SXPFXHU;84U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%LW:S!U^DGV@023\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,C^1Z&\UGYY88;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$KV9R.T][KWE^=o1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*U;87?m7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr([5;59k5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&Y7>3;i;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$_1=15g9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZG(}Viex"]34?7e?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz S=7=1c=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.Q?2;3a3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,W919=h1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^ppp35<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#DQXIEVK[2(rW}i<96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-J[ROC\AU<"xQ{c^2,]@UXD\^="XQCUU451>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%BSZGKTI]4*pYskV;>46[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-qwq3b3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTN"zl_wg`8582m2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!{c^tfg979>91^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RL u^amp*EN484=<6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'JC7>38?;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\F*sXkg~$OD2<>728Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!LI=6=25=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVH$yRmat.AJ808182_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_blw+FO;>7?m7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PB.w\gkr(L5:59k5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&N7=3;i;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\F*sXkg~$H1<15g9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZD(}Viex"J33?7e?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXJ&Tocz D=6=1c=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVH$yRmat.F?1;3a3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTN"{Pcov,@909>k1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RL u^amp*A\8T$LbE Z_LW[G\013\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTN"{Pcov,C^6Z&\UMH_K95:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[G)rWjd#JU?]/W\HPR1?2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_blw+B]7U'_TTB\LY7`8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!H[0_-CkN)]VG^TNW96:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[G)rWjd#JU>]/W\BATB><1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RL u^amp*A\9T$^SA[[669V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZD(}Viex"IT1\,V[]IUKP<i7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PB.w\gkr(OR8V"J`G.T]NQ]E^>?1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RL u^amp*A\:T$^SKJ]E778Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!H[3_-QZJR\?=0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QM/t]`jq)@S;W%YRV@RB[5f>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/FY0Y+Ai@'_TAXVLY748Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!H[2_-QZ@CZL<>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PB.w\gkr(OR9V"XQCUU44?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXJ&Tocz GZ1^*PY_G[IR:o5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&MP8P HnI,V[HS_KP<=7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PB.w\gkr(OR>V"XQIDSG51>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/FY7Y+SXD\^=;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'NQ?Q#[PXNP@]3d<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-D_0[)OgB%YRCZXB[52>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/FY6Y+SXNMXN:85Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&MP9P Z_MWW22=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVH$yRmat.EX1X(RWQEYOT89;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\F*sXkg~$KV8R.T]E@WC1=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_blw+B]1U'_T@XZ97:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[G)rWjd#JU9]/W\\JTDQ<l0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QM/t]`jq)T494>j6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'Z6:28h4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]A+pYdf}%X0?0:f:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[G)rWjd#^2<>4d8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!\<5<6b>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/R>6:0`<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-P8382i2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_sqw2d=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVNGU"IPRDE\FLR\8T$^SKJ]E7c8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYCDP%LS_KH_CKW_4[)]VLO^H8n;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\@I_(OVXNKRLFTZ0^*PYAL[O=m6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_ENZ+BYUMNUIEYU<]/W\BATB>h1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RJCY.E\V@AXJ@^P8P Z_GFQA3g<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UO@T!H_SGD[GOSS<W%YRHKRD4b?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXLES$KR\JG^@JP^0Z&\UMH_K6c:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\NM.K\R3(RWJYTN_OB_BCPGDBBW_<$ERJJPUJ\HQCVW:8@"XQ\BSCN[5)NWK9=GJZ?.F]QEHD4>R:V"xQ}al`02*SXZHGI?;7l;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_OB/H]U2+SXKZUI^LCPC@Q@EACX^?%BSIK_TI]OP@WX;;A%YR]MR@O\4*OXJ:<@KY>!G^PBIG51S8W%yR|nmc15+PYUIDH8:4m4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^LC I^T5*PYD[VHYM@QLARAB@@YQ>&CTHH^[H^NWATY4:B$^S^L]AL]3+LYE;?ALX= H_SCNF60\:T$~Sobb24,QZTFEK9=5n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYM@!F_W4-QZETWKXJARMNSBCGAZP1'@UOI]ZG_MVFUZ55C'_T_O\NM^2,MZD4>BM_<#IPR@OA73]4U'T~lcm37-V[WGJJ:<>o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOSNAC_LW[+L1)]VG^T<<7/Lov|ZIX99?o7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NTOBBPMTZ,M2(RWD_S=?6 Mlw{[JY688?h7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NTOBBPMTZ,M2(RWD_S=?6 Mlw{[JY6:<i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUHCAQBUY-J3+SXE\R:>5!Bmtz\KZ74=m1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K4*PYJ]Q;94"Cbuy]L[456=m1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K4*PYJ]Q;94"Cbuy]L[455=m1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K4*PYJ]Q;94"Cbuy]L[454=j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K4*PYJ]Q;94"Cbuy]L[422l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\5172l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\5142l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\5152l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\5122l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\5132k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H5-QZKRP883#@czx^M\503c3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXKFFTAXV I6,V[HS_9;2$A`{w_N]2143c3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXKFFTAXV I6,V[HS_9;2$A`{w_N]2173c3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXKFFTAXV I6,V[HS_9;2$A`{w_N]2163d3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXKFFTAXV I6,V[HS_9;2$A`{w_N]220c<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYDGEUFYU!F7/W\IP^6:1%FaxvPO^0\b23e3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXKFFTAXV I6,V[HS_9;2$A`{w_N]01f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZEHDVG^T"G8.T]NQ]750&GfyuQ@_236f>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[FIKWD_S#D9!U^OV\44?'Dg~tRAP44a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]@KIYJ]Q%B;#[PMTZ26=)Je|rTCR:>5c9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^ALHZKRP&C<"XQBUY31<*Kj}qUDS5;m;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPCNN\IP^(A>$^S@[W13:,IhsWFU29n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHRM@L^OV\*O0&\UFYU?=8.Onq}YHW0;>o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOSNAC_LW[+L1)]VG^T<<7/Lov|ZIX1;>n7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+FO;994?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN484?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4;4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4:4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4=4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4<4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4?4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN4>4?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN414?h6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*EN404?o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*B;87>o7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+A:687>h7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+A:66=i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,@949<j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-G8683k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.F?0;2d3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/E>6:1e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ D=4=0f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!K<6<7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"J38?6`?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#I26>4:8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV>R.FlK*PYJ]QIR9>5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S9W%YRHKRD71?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU?]/W\HPR2<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX4X(RWQEYOT;;;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ:<P Z_GFQA05<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ33Y+SXD\^>96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\99W%YRV@RB[6<>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT1\,DjM(RWD_SOT;<;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ:Q#[PFEPF17=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[0_-QZJR\<>0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^7Z&\USC_MV599V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW?S!GoJ-QZKRPJS>?6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\:T$^SKJ]E408Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV<R.T]OQQ333\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY1Y+SXPFXHU864U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR9V"J`G.T]NQ]E^=:1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_6[)]VLO^H;=;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ8Q#[PLTV60>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT3\,V[]IUKP?37X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]3U'MeD#[PMTZ@]05<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ6^*PYAL[O>>6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\<T$^SA[[559V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW9S!U^ZLVF_202_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX1X(@fA$^S@[WCX70?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU:]/W\BATB=;1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_0[)]VF^X8:4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR?V"XQWOSAZ1==R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[7_-CkN)]VG^TNW:3:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP:P Z_GFQA04<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ4^*PYK]]??7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]1U'_TTB\LY4:8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV9R.FlK*PYJ]QIR9>5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S>W%YRHKRD71?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU8]/W\HPR2<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX3X(RWQEYOT;7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ3Q#IaH/W\IP^DQ<90Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^>Z&\UMH_K:2:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP4P Z_MWW11=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[9_-QZ^HZJS>46[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\1T$LbE Z_LW[G\343\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY:Y+SXNMXN9?5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S0W%YRBZT468Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV7R.T][KWE^<j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-P8583l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.Q?5583k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.Q?5;2d3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/R>1:1e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ S=1=0f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!\<5<7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"]35?6`?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#^29>5a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$_1914b9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%X050;c:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&Y753:l;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRm`l^cg`wYcdp6;29m4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSnac_`fgvZbkq5;58n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nTobbPaefq[aj~4;4?o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUhcaQndep\`i;;7>h7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVid`Rokds]gh|:36=i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWjegSljkr^fo}939<j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+wbXkffTmij}_enz8383l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYdgeUjhi|Pwhff8583l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYdgeUjhi|Pwhff8483l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYdgeUjhi|Pwhff8783l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYdgeUjhi|Pwhff8683l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYdgeUjhi|Pwhff8183l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYdgeUjhi|Pwhff8083l2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYdgeUjhi|Pwhff8383m2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYdgeUjhi|Pwhff[wus<=1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+wbXlh~j0=0;5:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?5583=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k7=<0;5:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?5783=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k7=>0;5:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?5183=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k7=80;5:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?5383=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k7=:0;5:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?5=83=2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k7=40;4:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQkauc?5;223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h69<3::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>15;223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h69>3::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>17;223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h6983::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>11;223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h69:3::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>13;223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h6943::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>1=;233\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`Zbf|h6929;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=13:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi59:29;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=11:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi59829;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=17:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi59>29;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=15:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi59<29;4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=1;:13<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi59229:4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSio{a=1=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4=:5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<53=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4=85885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<51=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4=>5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<57=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4=<5885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<55=00=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4=25885Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<5;=01=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\`drf4=4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo351<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;=84?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo353<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;=:4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo355<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;=<4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo357<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;=>4?96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo359<71>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;=04?86[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUomyo35?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:187>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl291?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:1:7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl293?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:1<7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl295?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:1>7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl297?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:107>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl299?67?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:16=?0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm19?>578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_ecwe9166=>0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm191459V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPd`vb8=83<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k753:7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhR|`w^cg`w:76=30Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcW{e|Sljkr=33:1><]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[wipWhno~1?1499V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPrnu\eabu4;4?46[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUyczQndep?7;2?3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`ZthVkoh2;>5:8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_smt[dbcz5?5855Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nT~byPaefq838302_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYug~Ujhi|37?6;?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^plsZgcl{632964U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&xoSax_`fgv9?9<:1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+wbXzf}Tic::;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhR|`w^gm[d223\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`ZthVoeSo?9;T2,MZHHWM$^SDBN/T]GKPR5j2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$O@^PRDQFP63<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CTECZLAQ]E*PYDIY]N<>;4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\MKRDIYUM"XQLAQUF50e<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXKMEEI"GPYDQOQQ0)AVSN_R\_M/K\]@UXG[OL"B[[_SGD14=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYDLFDN#DQVERNVP3(NWPOXS_^B.T]NQ]@0=:1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UHHB@J/H]ZAVJR\?$BSTK\_SRN*PYTZE99SL;<;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_BFLJ@)NWPOX@XZ9.H]ZAVYUXD$^S^\C33]A02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYDLFDN#DQVERNVP3(TZEUFYU:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_BFLJ@)NWPOX@XZ9.RPO[T56<11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UHHB@J/H]ZAVJR\?$X^AQ^<1<7<>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZECGGO$ERWJSMWW2+UUDV[7=3;;;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_BOSV@UB\&CTUH]CUU4-MZ_B[VX[A#[PMTZE300<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXKDZYI^K[/H]ZAVJR\?$BSTK\_SRN*PYTZE99SL;9;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_BOSV@UB\&CTUH]CUU4-MZ_B[VX[A#[PSSN06ZD3i2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VIF\_K\EU-J[\CTD\^="^\C_P120g=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYDEYXN_HZ I^[FWISS>'YY@R_30?6a?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[FKWZLYNX"GPYDQOQQ0)[[FT]1?15`9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW5)NWPOX@XZ9.H]ZAVYUXD$BSTK\_NPFC+IR\VXNK8<4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR2,MZ_B[E__:#GPYDQ\VUK)]VG^TK9PAC71?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU7'@URI^BZT7,J[\CTW[ZF"XQBUYD4[FB3n2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX<"GPYDQOQQ0)AVSN_R\_M/W\IP^A0<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_TB^> I^[FWISS>'CTUH]PRQO-QZUUD:8TM8?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR2,MZ_B[E__:#GPYDQ\VUK)]VYY@><PB438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\JV6(AVSN_A[[6/K\]@UXZYG%YR]]L20\G07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXFZ:$ERWJSMWW2+OXQLYT^]C!U^QQH64XL=30Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_TB^> I^[FWISS>'YY@RCZX6>3:1?<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXFZ:$ERWJSMWW2+UUDVG^T:2>>548Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\JV6(AVSN_A[[6/QQHZKRP1>37X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]?/H]ZAVJR\?$X^AQ^30>3:1><]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXFZ:$ERWJSMWW2+UUDV[8=1?1499V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW5)NWPOX@XZ9.RPO[T564;4?:6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR@\0.K\]@UK]]<%__BPQ=2=03=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[9%BSTK\LTV5*VTKWX6:2984U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR2,MZ_B[E__:#]]L^S?6;213\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWGY;#DQVERNVP3(TZEUZ0>0:a:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP5*OXQLYGYY8!I^[FWZTWE'CTUH]POSGD*JSSW[OL9?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQAS0-J[\CTD\^="DQVER]QTH(RWD_SJ:QNB408Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\JV7(AVSN_A[[6/K\]@UXZYG%YRCZXG5\GA2a3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWGY:#DQVERNVP3(NWPOXS_^B.T]NQ]@?=81^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UE_<!F_XGPHPR1&@URI^Q]PL,V[VTK;;UJ9<5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQAS0-J[\CTD\^="DQVER]QTH(RWZXG??QM509V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW4)NWPOX@XZ9.H]ZAVYUXD$^S^\C33]@14=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[8%BSTK\LTV5*LY^MZUY\@ Z_RPO77YC<01^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UE_<!F_XGPHPR1&ZXGS@[W7=2=0<=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[8%BSTK\LTV5*VTKWD_S;1?1479V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW4)NWPOX@XZ9.RPO[HS_0=20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_TB^? I^[FWISS>'YY@R_<1=2=0==R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[8%BSTK\LTV5*VTKWX9:0<0;8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP5*OXQLYGYY8!SSN\U67;:7>=7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]>/H]ZAVJR\?$X^AQ^<1<72>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT9&CTUH]CUU4-WWJXY5;58;5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQAS0-J[\CTD\^="^\C_P>1:10<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXFZ;$ERWJSMWW2+UUDV[7?3:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_RAF+LY^MZF^X; Z_RPOG40B<11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UXO@^LE.K\]@UK]]<%YR]]L2065>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZUDZZ^$ERWJSMWW2+OXQLYT^]C!U^OV\C12;2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VYH^^Z I^[FWISS>'CTUH]PRQO-QZUUD:8TM8=4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PSBPPP*OXQLYGYY8!I^[FWZTWE'_T__B<2^@73>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZUDZZ^$ERWJSMWW2+UUDV[8=964U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PSBPPP*OXQLYGYY8!SSN\U969<11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UXO_][/H]ZAVJR\?$X^AQ^<0<73>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZQDM&CTUH]CUU4-QZUUDJ;=I974U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PWIANTFC(AVSN_A[[6/W\WWJ4:=30Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_T[AMBPBG,MZ_B[E__:#[PSSN067?<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&YHBYQLE3c8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*UDF]UHA]<k;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-PGKRXKDZTOH<l;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-PGKRXKDZT]?m4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.Q@JQYUMZO_8=5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!LAQ]B@ATXflr0=0;0:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.ABTZGCL[Ueiuz31?63?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+FGWWHNO^R`jxu>1:16<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(KHZTMIJ]_og{p959<91^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%HM]QNDEP\j`~s4=4?<6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"MNP^CG@WYimq~793:?;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/BCS[DBCZVdnty29>528Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,GDVXIMNYSckwt=5=05=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)DIYUJHI\Pndzw8=8382_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&IJ\ROKDS]ma}r;17>27X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ?_UM\21M)NVYN@V>R.T]PAI2f3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@U;SYAP65I-BZUBDR;;Q#[PSDN7e>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX8V^DS;:D.G]PAI]69T$^S^KC4`9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[5YSGV<?G#HPSDNX57[)]VYN@9o4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^2\PJY1<B$MS^KC[01^*PYTME>j7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ?_UM\21M)NVYN@V?;]/W\W@J3i2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT<RZ@_76H*CYTMEQ:9P Z_RGO0<=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW9U_CR8;K/D\W@J\9T$^S^KC489V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[5YSGV<?G#HPSDNX6X(RWZOG845Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_1]WKZ03C'LT_HBT3\,V[VCK<01^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS=Q[O^47O+@X[LFP8P Z_RGO0<=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW9U_CR8;K/D\W@J\=T$^S^KC489V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[5YSGV<?G#HPSDNX2X(RWZOG845Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_1]WKZ03C'LT_HBT7\,V[VCK<01^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS=Q[O^47O+@X[LFP4P Z_RGO0<=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW9U_CR8;K/D\W@J\1T$^S^KC469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[5YSGV<?G#GPSSN-QZUBDQ?:7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQFNUABT+@XKHZTMIJ][1_-QZEFXVKOH_;:;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_5[)]VIJ\ROKDS]NQ]353\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UBBYMNP/D\GDVXIMNYW=S!U^k@EUYFLMX>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPIOV@EU(AWJK[SLJKRZ3^*PYDIYUJHI\:5:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^7Z&\UHM]QNDEP\IP^2:2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTECZLAQ,E[FGWWHNO^V?R.T]jGDVXIMNY9<5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY1Y+SXKHZTMIJ]549V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[LHSKHZ%JRMNP^CG@W]5U'_TOL^PAEFQ[HS_=;1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSD@[C@R-BZEFXVKOH_U=]/W\mFGWWHNO^8?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX7X(RWJK[SLJKR478Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZOI\JK["KQLAQ]B@AT\;T$^SNO__@FGVZKRP<80Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ERGATBCS*CYDIYUJHI\T3\,V[lEFXVKOH_;>;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_1[)]VIJ\ROKDS76?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYNF]IJ\#HPC@R\EABUS=W%YRMNP^CG@WYJ]Q?97X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQFNUABT+@XKHZTMIJ][5_-QZoDIYUJHI\:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^3Z&\UHM]QNDEP61>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXAG^HM] I_BCS[DBCZR?V"XQLAQ]B@ATXE\R>>6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPIOV@EU(AWJK[SLJKRZ7^*PYnKHZTMIJ]509V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[LHSKHZ%JRMNP^CG@W]1U'_TOL^PAEFQ10=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW@D_OL^!F^ABTZGCL[Q=Q#[PC@R\EABUWD_S9?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY5Y+SXaJK[SLJKR438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZOI\JK["KQLAQ]B@AT\?T$^SNO__@FGV03<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVCEXNO_.G]@EUYFLMXP;P Z_BCS[DBCZVG^T8<4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX3X(RW`IJ\ROKDS72?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYNF]IJ\#HPC@R\EABUS1W%YRMNP^CG@W323\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UBBYMNP/D\GDVXIMNYW5S!U^ABTZGCL[UFYU;=;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_=[)]VcHM]QNDEP65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXAG^HM] I_BCS[DBCZR3V"XQLAQ]B@AT2=2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTECZLAQ,E[FGWWHNO^V7R.T]@EUYFLMXTAXV:2:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^?Z&\UbOL^PAEFQ17=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,GL:66<80Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'JC7>3;=;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"MF<2<66>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-@M929=;1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(K@6>28<4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#NG36?71?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.AJ8282:2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)DA5259?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$OD26>438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/E>3:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+A:66<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'M6928?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#I2<>438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/E>7:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+A:26<;0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'M6=28?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#I28>438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/E>;:07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+A:>6<n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ;Q#IaH/W\IP^DQ<20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ;Q#[PFEPF12=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,C^6Z&\UGYY;6;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT0\,V[]IUKP?o7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP=P HnI,V[HS_KP?37X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP=P Z_GFQA01<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+B]6U'_T@XZ:9:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[0_-QZ^HZJS>h6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW?S!GoJ-QZKRPJS>46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW?S!U^DGV@303\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*A\:T$^SA[[589V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ0^*PY_G[IR9i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV=R.FlK*PYJ]QIR955Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV=R.T]E@WC2?2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S:W%YRBZT4;8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY0Y+SXPFXHU8j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU;]/EmL+SXE\RHU864U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU;]/W\BATB=>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(OR>V"XQCUU7:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX0X(RWQEYOT;k;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT5\,DjM(RWD_SOT;7;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT5\,V[CBUM<=0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ>Q#[PLTV6=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-D_0[)]VRD^NW:d:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[7_-CkN)]VG^TNW:8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[7_-QZ@CZL?<7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP:P Z_MWW1<=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,C^0Z&\USC_MV5e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ5^*BhO&\UFYUMV599V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ5^*PYAL[O>;6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW:S!U^NVP0?<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+B]0U'_TTB\LY4f8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY;Y+Ai@'_TAXVLY4:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY;Y+SXNMXN9:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV6R.T]OQQ3>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*A\0T$^SUA]CX7;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX=X(RWONYI894U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU6]/W\HPR212_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S0W%YRV@RB[65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-P858292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)T484>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%X0?0:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!\<2<65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-P818292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)T4<4>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%X0;0:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!\<6<65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-P8=8292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)T404?46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/BK?5;2?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$OD2=>5:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)DA595855Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.AJ818302_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#NG35?6;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(K@6=2964U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-@M919<11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"MF<9<7<>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'JC753:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,@969<>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"J31?64?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(L5858:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.F?7;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$H1:1469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*B;=7><7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ D=4=02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&N7;3:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,@9>9<>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"J39?70?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR:V"J`G.T]NQ]E^<l1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"IT0\,V[CBUM=n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[1_-QZJR\=l0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[1_-QZ^HZJS>?6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY2Y+Ai@'_TAXVLY5g8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S8W%YRHKRD6g?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR;V"XQCUU6e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR;V"XQWOSAZ16=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP>P HnI,V[HS_KP>n7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ GZ0^*PYAL[O?h6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY1Y+SXD\^?j6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY1Y+SXPFXHU8=4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_6[)OgB%YRCZXB[7a>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'NQ8Q#[PFEPF0a=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP?P Z_MWW0c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP?P Z_YMQG\343\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV:R.FlK*PYJ]QIR8h5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.EX0X(RWONYI9j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_1[)]VF^X9h4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_1[)]VRD^NW:3:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]2U'MeD#[PMTZ@]1c<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%LW8S!U^DGV@2c3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV;R.T]OQQ2a3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV;R.T][KWE^=:1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"IT6\,DjM(RWD_SOT:j;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,C^0Z&\UMH_K;d:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]1U'_T@XZ;f:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]1U'_TTB\LY418Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S>W%KcF!U^OV\F_3m2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU8]/W\BATB<m1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"IT7\,V[ISS<o1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"IT7\,V[]IUKP?87X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ GZ:^*BhO&\UFYUMV4d9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\0T$^SKJ]E5f8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S1W%YRBZT5d8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S1W%YRV@RB[7a>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'NQ2Q#[PFEPF0a=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP5P Z_MWW0c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP5P Z_YMQG\203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$_1>1469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*U;97><7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ S=0=02=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&Y7?3:8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,W929<>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"]35?64?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR([5<58:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.Q?3;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$_161469V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*U;179=7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#XQMRJ202>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*SXJ[A:485Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!Z_RAMPZEJX&CTO^QHAOF-QZETWNKEHR]]L.K\R3(RWJYTKL@K_RPO[S0(AV_XIR\_M^LF4+SXOHDOS^\C_RGW<3=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)RW^IEXRFLMQ-J[FUXOHDO"XQLS^EBJAYTZE%BS[8!U^AP[BGILVYY@RX9/H]VW@YUXDUEI= Z_FCM@ZUUDVYNX584U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ U^U@JQYKKDZ$ERM\_FCM@+SXKZULMCJPSSN,MZP1&\UH_RINNE]PVIYQ>&CTY^KPRQO\J@6)]VMJBIQ\RM]PAQ5e3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'jllSio{a=2=7g=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)dnnUomyo31?1a?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+f``Wmkm1<13c9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-`bbYci}k7?3=m;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/bdd[agsi5>58=5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!lff]geqgX~li7==0;0:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.aecZbf|hU}in2>1?63?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+f``WmkmRxjc=31:16<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(komThlzn_wg`8459<91^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%hjjQkauc\r`e;9=4?<6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"mig^fbpdYqmj6:93:?;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/bdd[agsiV|no1?9>2d8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,gcaXlh~jS{kl<0<0b>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*eaoVnjxlQyeb>1:6`<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(komThlzn_wg`8684n2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&imkRjnt`]uaf:36:l0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$okiPd`vb[scd4<48j6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"mig^fbpdYqmj6=2>h4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ cge\`drfWoh0:0<f:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.aecZbf|hU}in27>2d8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,gcaXlh~jS{kl<8<0g>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*oDIYUJHI\30?1`?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+lEFXVKOH_2>>2a8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,mFGWWHNO^1<13b9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-jGDVXIMNY0>0<c:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.k@EUYFLMX783=l;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/hABTZGCL[6>2>m4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ iBCS[DBCZ5<5?n5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!fC@R\EABU4>48o6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"gLAQ]B@AT;079h7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#dMNP^CG@W:>6:20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$e^MAT=2=7==R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)n[JD_0<0<8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.kPGKR;:7937X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#d]LNU>0:6><]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(aZIEX1:1399V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-jWFHS4<4846[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"g\COV?2;5?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'`YHBY28>2:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,mVEI\525?55Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!fSBLW8<85m2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YR]LNU]@IUYV:11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQ[RHE1=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]V^YEJ>=9:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZRUAN;9j6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^U@JQYOKDZT]?h4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\SFHSWEIF\R_=9:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,SFHSWJO9n6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B WBLW[MEJX;o0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"YLNU]KGHVXKL8o7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!XCOV\LFKWWX8i7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!XCOV\HFKW:l1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#ZMAT^N@IUYDM;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"YLNU]OGHVXY;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"mig^fbpd:76;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"mig^fbpd:66;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"mig^fbpd:56;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"mig^fbpd:46;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"mig^fbpd:36;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"mig^fbpd:26;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"mig^fbpd:16;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"mig^fbpd:06;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"mig^fbpd:?6;n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"mig^fbpd:>6;i0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"gLAQ]TVZCI:m1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#dZ]IFEFVZOI:l1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#dZ]IFEFVZIR\:k0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@RGPSSNW[KCX9'_TOIAAE^OPAQ5c3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZEUBS^\CT^LF[4(RWJG[^H]JT^OPAQ5?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZEUBS^\CT^LF[4(RWGY;S@]JT2:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQHZOX[[F_SCKP1/W\JV7XEZO_?l5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C_H]PVIRXFLU:"XQ\CSQW[HUB\;>0Y=!F_OM\@+SXAEK$YR\\T.E\VVR\8T$^S_][259V4*OXFFUO"XQFL@-V[WUS'NUY_YU>]/W\VVR5<2_;#DQAO^F-QZOKI&_T^^Z G^PPP^4Z&\UY_Y<;;T2,MZHHWM$^SDBN/T]QWQ)@W[Y_W>S!U^PPP72<]9%BSCAPD/W\MIG(]VXXX"IPRRVX0X(RW[Y_>95Z0.K\JJYC&\UB@L!Z_SQW+BYU[]Q>Q#[PRRV10>S7'@UECRJ!U^KOE*SXZZ^$KR\\TZ4^*PYU[]8?7X> I^LL[A(RW@FJ#XQ]SU-D[WUSS>W%YR\\T328Q5)NWGETH#[PIMC,QZTT\&BJ@YQumqf5<=R8&CTBBQK.T]JHD)RW[Y_#]A]219V4*OXFFUO"XQFL@-V[WUS'YXNS_K\EU214>S7'@UECRJ!U^KOE*SXZZ^$\_KPRDQFP44?3\:$ER@@_E,V[LJF'\UY_Y!Z_@PN[]@BZ&_TOAKNR358Q5)NWGETH#[PIMC,QZTT\&_TM_CPXGGQ+PYCG\^946[?/H]MKZB)]VCGM"[PRRV,QZGUEVRMI_!Z_EMVP54?3\:$ER@@_E,V[LJF'\UY_Y!Z_@PN[]@BZ&_THB[[1268Q5)NWGETH#[PIMC,QZTT\&_TM_CPXGGQ+PY@MGUOIAOV[0_-QZ@C;=1^<"GPNN]G*PYNDH%^S_][/T]BVHY_NLX$YRIJN^FFHD_\:T$^SKJ<4:W3+LYIGVN%YRGCA.W\VVR(]VKYARVIES-V[BCIWMOGMTU<]/W\BA533\:$ER@@_E,V[LJF'\UY_Y!Z_@PN[]@BZ&_TKH@PDDNB]^2Z&\UMH?64U1-J[KIXL'_TEAO U^PPP*SXI[GTTKK]/T]QBATB:11^<"GPNN]G*PYNDH%^S_][/T]BVHY_NLX$YRZIDSG1g>S7'@UECRJ!U^KOE*SXZZ^$YRO]M^ZEAW)cagUgmymgee06?P6(AVDDSI Z_HNB+PYU[]%^SL\B_YDFV*oDD[837X> I^LL[A(RW@FJ#XQ]SU-V[DTJWQLN^"gKIO>3:7><]9%BSCAPD/W\MIG(]VXXX"[PASO\\CCU'`NBB1?1279V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,mAIR\;n0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#dJ@UU]gh|:76;n0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#dJ@UU]gh|:66;n0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#dJ@UU]gh|:56;n0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#dJ@UU]gh|:36;30Y=!F_OM\@+SXAEK$YR\\T.W\LDJSWQLN^"[PCMGBV7><]9%BSCAPD/W\MIG(]VXXX"[PH@NW[]@BZ&_THB[[289V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+PYCG\^;>45Z0.K\JJYC&\UB@L!Z_SQW+PYOIE^TTKK]/T]GKPR6;<1^<"GPNN]G*PYNDH%^S_][/T]KEIRXPOOY#XQHEO]GAIG^S8W%YRHK349V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+PY@MGUOIAOV[3_-QZ@C:01^<"GPNN]G*PYNDH%^S_][/T]KEIRXPOOY#XQ]FEPF6<=R8&CTBBQK.T]JHD)RW[Y_#XQGAMV\\CCU'\U_JI\J2e9V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+aoiWekoekk279V4*OXFFUO"XQFL@-V[WUS'\UCMAZPXGGQ+lEKZ;30Y=!F_OM\@+SXAEK$YR\\T.W\LDJSWQLN^"gKIO>3:7?<]9%BSCAPD/W\MIG(]VXXX"[PH@NW[]@BZ&cOEC2>>358Q5)NWGETH#[PIMC,QZTT\&_TDLB[_YDFV*oCG\^9i6[?/H]MKZB)]VCGM"[PRRV,QZNFD]USJH\ iEMVPZbkq5:5>h5Z0.K\JJYC&\UB@L!Z_SQW+PYOIE^TTKK]/hFLQQYcdp692<l4U1-J[KIXL'_TEAO U^PPP*SXXFX:h6[?/H]MKZB)]VCGM"[PRRV,QZVU[]::h6[?/H]MKZB)]VCGM"[PRRV,QZVU[];:o6[?/H]MKZB)]VCGM"[PRRV,QZTT\9;m7X> I^LL[A(RW@FJ#XQ]SU-jV@UB\5:5>85Z0.K\JJYC&\UB@L!Z_RVBP*GD\[OXIYQumqf65=R8&CTBBQK.T]JHD)RWZ^JX"OLT^fppdr582_;#DQAO^F-QZOKI&_T_YO[/@PN[ausi}8>7X> I^LL[A(RW@FJ#XQ\T@V,GDVXZLYNXRjcy03e?P6(AVDDSI Z_HNB+PYT\H^$HD\[Y^F35c=R8&CTBBQK.T]JHD)RWZ^JX"JFRU[\@4473\:$ER@@_E,V[LJF'\UXXLZ DHPW]ZUBD;80Y=!F_OM\@+SXAEK$YR][AU-GMWR^Wmymy<;;T2,MZHHWM$^SDBN/T]PPDR(LZ^JXRka_enz572<]9%BSCAPD/W\MIG(]VY_MY!KSUCW[`hXles9>95Z0.K\JJYC&\UB@L!Z_RVBP*BT\H^TicQklx115>S7'@UECRJ!U^KOE*SX[]K_#I][AU]okdb512_;#DQAO^F-QZOKI&_T_YO[/DZWGDVXZLKOURj|t`v15>S7'@UECRJ!U^KOE*SX[]K_#K[CL^fppdr5n2_;#DQAO^F-QZOKI&_T_YO[/G]PWQGSS9W%ER][AU,V[VRF\::0Y=!F_OM\@+SXAEK$YR][AU-E[VUSI]Q:<P F_RVBP+SX[]K_>k5Z0.K\JJYC&\UB@L!Z_RVBP*@X[Z^JXV?R.H]PPDR)]VY_MY<i;T2,MZHHWM$^SDBN/T]PPDR(NVYXXLZT2\,J[VRF\'_T_YO[2g9V4*OXFFUO"XQFL@-V[VRF\&LT_^ZNTZ1^*LYT\H^%YR][AU0e?P6(AVDDSI Z_HNB+PYT\H^$JR]\T@VX0X(NWZ^JX#[PSUCW6c=R8&CTBBQK.T]JHD)RWZ^JX"HPSRVBP^3Z&@UXXLZ!U^QWEQ4a3\:$ER@@_E,V[LJF'\UXXLZ F^QPPDR\>T$BS^ZNT/W\WQGS:o1^<"GPNN]G*PYNDH%^S^ZNT.D\WVRF\R=V"DQ\T@V-QZUSI]8m7X> I^LL[A(RW@FJ#XQ\T@V,BZUT\H^P4P F_RVBP+SX[]K_>k5Z0.K\JJYC&\UB@L!Z_RVBP*@X[Z^JXV7R.H]PPDR)]VY_MY<;;T2,MZHHWM$^SDBN/T]PPDR(OVDXW=S!U^LPU72<]9%BSCAPD/W\MIG(]VY_MY!H_OQX5X(RWGYZ>95Z0.K\JJYC&\UB@L!Z_RVBP*AXFZQ9Q#[PNRS10>S7'@UECRJ!U^KOE*SX[]K_#JQASZ1^*PYI[X8?7X> I^LL[A(RW@FJ#XQ\T@V,CZHTS=W%YR@\Q368Q5)NWGETH#[PIMC,QZUSI]%LSC]T5\,V[KUV:=1^<"GPNN]G*PYNDH%^S^ZNT.E\JV]1U'_TB^_=4:W3+LYIGVN%YRGCA.W\WQGS'NUE_V9R.T]MWT433\:$ER@@_E,V[LJF'\UXXLZ G^LP_=[)]VDX]?:4U1-J[KIXL'_TEAO U^QWEQ)@WGYP5P Z_OQR6<=R8&CTBBQK.T]JHD)RWZ^JX"Cbuy]GMWR^Wmymy?>239V4*OXFFUO"XQFL@-V[VRF\&DXSi}{au>3:74<]9%BSCAPD/W\MIG(]VY_MY!AS^fppdr;97897X> I^LL[A(RW@FJ#XQ\T@V,JVYc{}k0?0=2:W3+LYIGVN%YRGCA.W\WQGS'GYTh~znt=1=67=R8&CTBBQK.T]JHD)RWZ^JX"@\_eqweq:36;80Y=!F_OM\@+SXAEK$YR][AU-MWZbt|h~793<=;T2,MZHHWM$^SDBN/T]PPDR(FZUoyo{<7<16>S7'@UECRJ!U^KOE*SX[]K_#C]Pdrvbp919:;1^<"GPNN]G*PYNDH%^S^ZNT.LP[ausi}632?<4U1-J[KIXL'_TEAO U^QWEQ)I[Vnxxlz39?3f?P6(AVDDSI Z_HNB+PYT\H^$B^Qco`f11>S7'@UECRJ!U^KOE*SX[]K_#^ZNTD]gwqgs494996[?/H]MKZB)]VCGM"[PSUCW+VRF\LUoyo{<0<2b>S7'@UECRJ!U^KOE*SX[]K_#YJ@_og{p72<]9%BSCAPD/W\MIG(]VY_MY![RHEDAWYc{}k=n5Z0.K\JJYC&\UB@L!Z_RVBP*SXI[G996[?/H]MKZB)]VCGM"[PSUCW+PYFZDUl`xkPsdv2f>S7'@UECRJ!U^KOE*SX[]K_#XQLR318Q5)NWGETH#[PIMC,QZUSI]%^SIG]TX]E@FC5;2_;#DQAO^F-QZOKI&_T_YO[/T]GMWR^WON[I?<4U1-J[KIXL'_TEAO U^QWEQ)RWMCYXTQCDB1b?P6(AVDDSI Z_HNB+PYT\H^$YRJBUY6,QZETWD_S#D=!U^OV\=)Je|rTCR=<a:W3+LYIGVN%YRGCA.W\WQGS'\UOAXV;/T]@WZKRP&C8"XQBUY:,IhsWFU?=n5Z0.K\JJYC&\UB@L!Z_RVBP*SXLZF996[?/H]MKZB)]VCGM"[PSUCW+PYC[E;$YRMCE@P10>S7'@UECRJ!U^KOE*SX[]K_#XQKSM3,QZBH]]8>7X> I^LL[A(RW@FJ#XQ\T@V,QZBTD8%^SIAZT106?P6(AVDDSI Z_HNB+PYT\H^$YRJ\L0-V[AIR\89:7X> I^LL[A(RW@FJ#XQ\T@V,QZBTD8%^SJKA_EGOE\]6U'_TJI<:;T2,MZHHWM$^SDBN/T]PPDR(]VNX@<!Z_SDGV@423\:$ER@@_E,V[LJF'\UXXLZ U^FPH4)RW]LO^H<6;T2,MZHHWM$^SDBN/T]PPDR(]VNX@<!kio]oeqeomm897X> I^LL[A(RW@FJ#XQ\T@V,QZBTD8%bOA\=5:W3+LYIGVN%YRGCA.W\WQGS'\UO_A? iEKM8585=2_;#DQAO^F-QZOKI&_T_YO[/T]GWI7(aMCE0<0=a:W3+LYIGVN%YRGCA.W\WQGS'\UO_A? iEMVPZbkq5:5>l5Z0.K\JJYC&\UB@L!Z_RVBP*SXLZF:#dJ@UU]gh|:668n0Y=!F_OM\@+SXAEK$YR][AU-V[AUK:8n0Y=!F_OM\@+SXAEK$YR][AU-V[AUK;8i0Y=!F_OM\@+SXAEK$YR][AU-V[AUU9j1^<"GPNN]G*PYNDH%^S^ZNT.W\AFT5=2_;#DQAO^F-QZOKI&_T_YO[/T]FGWY`d|oThz>d:W3+LYIGVN%YRGCA.W\WQGS'\UMYAB=6:W3+LYIGVN%YRGCA.W\WQGS'\UMYABPgmwf[vcs;>1^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO01;?P6(AVDDSI Z_HNB+PYT\H^$YRCZX.W\GVYJ]Q%B=#[PMTZ1+HkrpVE:=>74U1-J[KIXL'_TEAO U^QWEQ)RWD_S#XQLS^OV\*O6&\UFYU< Mlw{[J768:30Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N3256?<]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?>22;8Q5)NWGETH#[PIMC,QZUSI]%^S@[W/T]@WZKRP&C:"XQBUY0,IhsWF;:?>74U1-J[KIXL'_TEAO U^QWEQ)RWD_S#XQLS^OV\*O6&\UFYU< Mlw{[J76<:30Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N3216?<]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?>62;8Q5)NWGETH#[PIMC,QZUSI]%^S@[W/T]@WZKRP&C:"XQBUY0,IhsWF;:;>74U1-J[KIXL'_TEAO U^QWEQ)RWD_S#XQLS^OV\*O6&\UFYU< Mlw{[J760:30Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N32=6><]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?=389V4*OXFFUO"XQFL@-V[VRF\&_TAXV U^AP[HS_'@;%YRCZX3-Nip~XG88;?45Z0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K446;m1^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO002[VQ7;01^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO0017<=R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<<<399V4*OXFFUO"XQFL@-V[VRF\&_TAXV U^AP[HS_'@;%YRCZX3-Nip~XG89846[?/H]MKZB)]VCGM"[PSUCW+PYJ]Q%^SN]PMTZ,M4(RWD_S>"Cbuy]L515?3\:$ER@@_E,V[LJF'\UXXLZ U^OV\*SXKZUFYU!F1/W\IP^5'Dg~tRA>52:8Q5)NWGETH#[PIMC,QZUSI]%^S@[W/T]@WZKRP&C:"XQBUY0,IhsWF;=?55Z0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K414k2_;#DQAO^F-QZOKI&_T_YO[/T]NQ])RWJYTAXV I0,V[HS_:&GfyuQ@16]PS55d3\:$ER@@_E,V[LJF'\UXXLZ U^OV\*SXKZUFYU!F1/W\IP^5'Dg~tRA>7^QT56e<]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?8_RU17==R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<6<8:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH90;h7X> I^LL[A(RW@FJ#XQ\T@V,QZHTD::0Y=!F_OM\@+SXAEK$YR][AU-V[WCTM]UNHJK I^J1H+SXLF__>o5Z0.K\JJYC&\UB@L!Z_RVBP*SXZLYNXRKKGD-V[AIR\98i7X> I^LL[A(RW@FJ#XQ\T@V,QZTB[L^TIIIJ/T]GKPR6:j1^<"GPNN]G*PYNDH%^S^ZNT.W\V@UB\VOOKH!fDNWW8585k2_;#DQAO^F-QZOKI&_T_YO[/T]QAVCSWLNLI"gKOTV?5;7a3\:$ER@@_E,V[LJF'\UXXLZ U^PJWLH@:91^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSKDN9>6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^HAIQa1g9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[E13e?P6(AVDDSI Z_HNB+PYT\H^$YR][AUG262=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'JC7=3<8;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-@M949:>1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#NG33?04?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)DA5>5>:5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/BK?1;403\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%HE181269V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+FO;?78<7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!LI=:=62=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'JC753<9;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-G8585>2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$H1?1279V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+A:56;<0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"J33?05?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)C4=49:6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ D=7=63=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'M6=2?84U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.F?3;413\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%O050=6:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,@9?9;;1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU?]/EmL+SXE\RHU?j4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX4X(RWONYI?m4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX4X(RWE__>h5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY3Y+SXPFXHU><4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX5X(@fA$^S@[WCX0g?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S8W%YRHKRD0`?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S8W%YRBZT3g8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\9T$^SUA]CX11?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S;W%KcF!U^OV\F_5l2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV<R.T]E@WC5k2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV<R.T]OQQ4b3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW?S!U^ZLVF_4:2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV=R.FlK*PYJ]QIR>i5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY0Y+SXNMXN>n5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY0Y+SXD\^9i6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ1^*PY_G[IR??5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/FY7Y+Ai@'_TAXVLY3f8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\<T$^SKJ]E3a8Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\<T$^SA[[2d9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]3U'_TTB\LY208Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*A\=T$LbE Z_LW[G\4c3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW8S!U^DGV@4d3\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW8S!U^NVP7c<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP9P Z_YMQG\553\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%LW;S!GoJ-QZKRPJS9h6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ4^*PYAL[O9o6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ4^*PYK]]8n7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!H[7_-QZ^HZJS8>6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ5^*BhO&\UFYUMV2e9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]0U'_TJI\J2b9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]0U'_T@XZ=e:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,C^1Z&\USC_MV339V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]?U'MeD#[PMTZ@]7b<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP4P Z_GFQA7e<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP4P Z_MWW6`=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'NQ3Q#[PXNP@]7b<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP5P Z_GFQA7e<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP5P Z_MWW6`=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'NQ2Q#[PXNP@]70<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&Y7<3<9;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-P8485>2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$_1<1279V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+V:46;<0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"]34?05?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)T4<49:6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ S=4=63=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'Z6<2?84U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.Q?<;413\:$ER@@_E,V[LJF'\UXXLZ U^QWEQYDF]%X040>c:W3+LYIGVN%YRGCA.W\WQGS'\U_HB<?;T2,MZHHWM$^SDBN/T]PPDR(]V^YEJIJR3;8Q5)NWGETH#[PIMC,QZUSI]%^SY\FGFGQ[bjrmVynx<h4U1-J[KIXL'_TEAO U^QWEQ)n[]K_0=0=0:W3+LYIGVN%YRGCA.W\WQGS'`Y_MY2>0?3e?P6(AVDDSI Z_HNB+PYT\H^$e^ZNT=3=5c=R8&CTBBQK.T]JHD)RWZ^JX"g\T@V?6;7a3\:$ER@@_E,V[LJF'\UXXLZ iRVBP9599o1^<"GPNN]G*PYNDH%^S^ZNT.kPPDR;<7;m7X> I^LL[A(RW@FJ#XQ\T@V,mVRF\5?5=k5Z0.K\JJYC&\UB@L!Z_RVBP*oT\H^7:3?i;T2,MZHHWM$^SDBN/T]PPDR(aZ^JX1911g9V4*OXFFUO"XQFL@-V[VRF\&cXXLZ38?3e?P6(AVDDSI Z_HNB+PYT\H^$e^ZNT=;=67=R8&CTBBQK.T]JHD)RWZ^JX"g\T@V@IAYDM;>0Y=!F_OM\@+SXAEK$YR][AU-jWQGSKDNTOHQa229V4*OXFFUO"XQFL@-V[VRF\&cXXLZPCOV?4;443\:$ER@@_E,V[LJF'\UXXLZ iRVBPZEI\5;5>>5Z0.K\JJYC&\UB@L!Z_RVBP*oT\H^TOCZ32?00?P6(AVDDSI Z_HNB+PYT\H^$e^ZNT^AMP959::1^<"GPNN]G*PYNDH%^S^ZNT.kPPDRXKG^783<<;T2,MZHHWM$^SDBN/T]PPDR(aZ^JXRMAT=7=66=R8&CTBBQK.T]JHD)RWZ^JX"g\T@V\GKR;>7887X> I^LL[A(RW@FJ#XQ\T@V,mVRF\VIEX191229V4*OXFFUO"XQFL@-V[VRF\&cXXLZPCOV?<;443\:$ER@@_E,V[LJF'\UXXLZ iRVBPZEI\535>;5Z0.K\JJYC&\UB@L!Z_UPJC*@XFFU_O@M!U^DGV64<]9%BSCAPD/W\MIG(]V^YEJ!Z_UA,MZUSG[KLIR_ZAM,V[FGWWK9?7X> I^LL[A(RW@FJ#XQ[RHE,QZRD'@UXXB\NGD]RQDJ)]VIJ\RJCY6g8Q5)NWGETH#[PIMC,QZRUAN%^SYM I^QWKWG@MV[^MA Z_RVLVDABWX_J@"GPSSNW[KCX9'CTB@[P1^VL[1(RW]IG#DQAMT]FU4(RW`NDYY!F_XGPHPR1&\UX^AM>6D4;?P6(AVDDSI Z_HNB+PYSZ@M$YRZL/H]PPJTFOLUZYLB!U^QWKWG@MV[^MA!F_RPOPZHBW8$BSCCZ_0]WKZ2)]V^H@"GPOTVQAB(RWME^X8k4U1-J[KIXL'_TEAO U^VQMB)RW]I$ER][OSCDAZWRIE$^S^Z@R@EF[TSFD&CT__B[_OG\5+OXFD_T=RZ@_5,V[QEK'`NDYY;n;T2,MZHHWM$^SDBN/T]WVLA(]V^H#DQ\TNPBC@YV]HF%YR][OSCDAZWRIE%BS^\CT^LF[4(NWGG^S<Q[O^6-QZRUAN[?>6[?/H]MKZB)]VCGM"[PTSKD+PYSK&CT_YA]AFG\UPGK&\UXXB\NGD]RQDJ(a]XBKJK]7`9V4*OXFFUO"XQFL@-V[QTNO&_TXN!F_UQFUZHBY;$^SYMPEPWBPLII'@UX^AZPND]2*LYIE\U:SYAP4/W\PFJ(AVDFYRK^1/W\mAIR\&CTUH]CUU4-QZUUDJ;=I;:4U1-J[KIXL'_TEAO U^VQMB)RW]I$ERZ\EP]MAT4)]V^HSH_ZAUKLJ*OX[[F_SCKP1/K\JHSX9V^DS9 Z_UAO+LYH]]XNK#[PDNWW1d=R8&CTBBQK.T]JHD)RW]XBK"[PTB-J[QUBYVDN]? Z_UA\ATSF\@EE#DQ\RMV\J@Y6&@UEAXQ>_UM\0+SX\JF$eIAZT448Q5)NWGETH#[PIMC,QZRUAN%^SYM I^VPATYIMX8%YRZL_DSVEQOHF&CT__B[_OG\5+OXFD_T=RZ@_5,V[QTNOX9n7X> I^LL[A(RW@FJ#XQ[RHE,QZRD'@U__H_PNDS1*PYSKVOZYLZFOO-jPWO@OLX986[?/H]MKZB)]VCGM"[PTSKD+PYSK&cHM]ZZRD0;?P6(AVDDSI Z_HNB+PYSZ@M$YRZL/hAECZBF\H6;2>m4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'@UFOR@@.T]MKZKDW[OL?;5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#IAZT^vntde<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]7U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2e`=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^778T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5dc<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]688W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gb3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\998V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fm2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S8:8Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6il1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R;;8P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9ho0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q:<8S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8kn7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P==8R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;ji6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W<>8]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mh5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V??8\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lk4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U>08_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T11_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<oj;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T102^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?ne:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[032Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ad9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z326X(NW@DT^L@HE/K\QVCXAGZ^XR\JG^LF4+SXOHDOSIBV1`g8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY0Y256[)AVCES_OAGD,J[PUBW@D[YYQ]EF]MA5(RWNKEHRJCY0cf?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX3X542Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3ba>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_472U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2e`=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^76>T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5dc<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]69>W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gb3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\982V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fm2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S8;2Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R;:Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6il1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R;9<P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9ho0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q:><S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8kn7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P=?<R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;ji6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W<<<]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mh5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V?=4\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lk4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U>24_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<oj;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T134^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?ne:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[004Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ae9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z31Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ae9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z30Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ae9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z37Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ae9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z36Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ae9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z35Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ae9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z34Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ae9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z3;Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ae9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z3:Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ab9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z3^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[32^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[33^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[30^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[31^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[36^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[37^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[34^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[35^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[3:^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nd:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[3;^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nc:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[3_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T31_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T30_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T33_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T32_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T35_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T34_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T37_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T36_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T39_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ok;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T38_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<ol;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T?T3\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lj4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;0\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lj4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;1\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lj4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;2\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lj4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;3\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lj4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;4\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lj4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;5\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lj4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;6\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lj4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;7\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lj4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;8\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lj4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;9\,J[LHXZHDLI#GPURG\MKVR\VXNKR@J0/W\CDHCWMFR=lm4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU<U;]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;?]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;>]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;=]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;<]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;;]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;:]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;9]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;8]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;7]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mi5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;6]/K\MKYUIGMN"DQZSD]JJUSSW[OLSCK?.T]DEKBXLES:mn5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR=V;R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;>R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;?R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;<R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;=R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;:R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;;R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;8R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;9R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;6R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jh6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;7R.H]JJZTFFNO%ER[\E^KMTPRXZLMTBH>!U^EBJAYCDP;jo6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES:W;S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;=S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;<S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;?S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;>S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;9S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;8S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;;S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;:S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;5S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8ko7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;4S!I^KM[WGIOL$BSX]J_HLSQQYUMNUEI= Z_FCM@ZBKQ8kh7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP;P;P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q3<P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q3=P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q3>P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q3?P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q38P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q39P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q3:P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q3;P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q34P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hn0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q35P F_HL\VDH@M'CTY^KPIORVPZTBOVDN<#[PG@LG[AJ^9hi0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ8Q3Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R3;Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R3:Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R39Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R38Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R3?Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R3>Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R3=Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R3<Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R33Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6im1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R32Q#GPIO]QEKAB&@U^_HQFNQWW[WC@WGO;"XQHAOF\@I_6ij1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R3V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7>02_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S9W%ERGA_SCMC@(RWNKEHRJCY3;b?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X556Z&@UBBR\NNFG-QZAFFMUO@T<6a:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[022Y+OXAGUYMCIJ.T]DEKBXLES95l5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V??2\,J[LHXZHDLI#[PG@LG[AJ^:0k0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q:<>S!I^KM[WGIOL$^SJOAD^FO]7?f3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\99>V"DQFN^PBJBC)]VMJBIQKLX0:e>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_462U'CTECQ]AOEF*PY@IGNTHAW=9`9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z332X(NW@DT^L@HE/W\CDHCWMFR>4o4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U>06_-MZOIW[KEKH Z_FCM@ZBKQ;3j7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P==6R.H]JJZTFFNO%YRINNE]GH\4>i2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S8:2Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^77U'CTECQ]AOEF*PY@IGNTHAW=9`9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z324X(NW@DT^L@HE/W\CDHCWMFR>4o4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U>10_-MZOIW[KEKH Z_FCM@ZBKQ;3j7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P=<<R.H]JJZTFFNO%YRINNE]GH\4>i2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S8;8Q#GPIO]QEKAB&\ULMCJPDM[1=d=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^76<T$BSD@PR@LDA+SXOHDOSIBV28c8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y250[)AVCES_OAGD,V[BGILVNGU?7n;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T104^*LYNFVXJBJK!U^EBJAYCDP82m6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W<?8]/K\MKYUIGMN"XQHAOF\@I_51h1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R;:4P F_HL\VDH@M'_TKL@K_ENZ6<g<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]690W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X54[)AVCES_OAGD,V[BGILVNGU?7n;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T132^*LYNFVXJBJK!U^EBJAYCDP82m6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W<<>]/K\MKYUIGMN"XQHAOF\@I_51h1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R;9>P F_HL\VDH@M'_TKL@K_ENZ6<g<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]6::W%ERGA_SCMC@(RWNKEHRJCY3;b?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X572Z&@UBBR\NNFG-QZAFFMUO@T<6a:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[006Y+OXAGUYMCIJ.T]DEKBXLES95l5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V?=6\,J[LHXZHDLI#[PG@LG[AJ^:0k0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q:>:S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\9;W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X56[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T15_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P=8S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\9?W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X52[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T19_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P=4S!I^KM[WGIOL$^SJOAD^FO]7??3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\9T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y14X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U=1\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q9>P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]5;T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y10X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U=5\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q9:P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]5?T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y1<X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U=9\,J[LHXZHDLI#[PG@LG[AJ^:020Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q9Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^57U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z12Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V==]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R98Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^53U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z16Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V=9]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R9<Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^5?U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z1:Y+OXAGUYMCIJ.T]DEKBXLES9555Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V=R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S=:V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_17Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[50^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W9=R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S=>V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_13Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[54^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W99R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S=2V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_1?Z&@UBBR\NNFG-QZAFFMUO@T<68:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[5_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P9=S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\=8W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X17[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T52_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P99S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\=<W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X13[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T56_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P95S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\=0W%ERGA_SCMC@(RWNKEHRJCY3;;?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X1X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U90\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q==P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]1:T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y57X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U94\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q=9P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]1>T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y53X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U98\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q=5P F_HL\VDH@M'_TKL@K_ENZ6<><]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]1U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z53Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V9>]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R=9Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^14U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z57Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V9:]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R==Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^10U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z5;Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V96]/K\MKYUIGMN"XQHAOF\@I_5111^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R=V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_=6Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[93^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W5<R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S19V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_=2Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[97^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W58R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S1=V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_=>Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[9;^*LYNFVXJBJK!U^EBJAYCDP8246[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W5S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\19W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X=4[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T93_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P5>S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\1=W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X=0[)AVCES_OAGD,V[BGILVNGU?76;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T97_-MZOIW[KEKH Z_FCM@ZBKQ;327X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 G^EBJAYCDP8P5:S!I^KM[WGIOL$^SJOAD^FO]7?>3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\4\11W%ERGA_SCMC@(RWNKEHRJCY3;:?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X=<[)AVCES_OAGD,V[BGILVNGU?77;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T9\,J[LHXZHDLI#[PG@LG[AJ^:h:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!Z_BQ\CDHCWZXGS[8 I^WPAZTWEVDN<#[PG@LG[VTKWZO_;k5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7<36>;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1??0?:2?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=335;>63\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz5977:72:7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~95;;?36>;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1??4?:2?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=331;>63\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz5977>72:7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~95;;;36>;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1??8?:2?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=33=;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz597761;0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i648;;25?4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:0<?>>938Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><031:=7<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{2847461;0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i648;?25?4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:0<?:>938Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><035:=7<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{2847061;0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i648;325?4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:0<?6>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><03=<4=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?5769081^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;9;;54<5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7=?<1809V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?3131=<4=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?5729081^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;9;?54<5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7=?81809V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?3135=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?578?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:6;72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~95;?25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:0<;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?317<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>23;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz597?61:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64835;k5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7=36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1<?>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><33=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?678?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:5;72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~958?25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:0?;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?327<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>13;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz594?61:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64;35;k5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7>36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1=?>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><23=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?778?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:4;72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~959?25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:0>;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?337<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>03;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz595?61:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64:35;k5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7?36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1:?>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><53=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?078?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:3;72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~95>?25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:09;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?347<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>73;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz592?61:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64=35;k5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7836?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1;?>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><43=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?178?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:2;72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~95??25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:08;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?357<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>63;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz593?61:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64<35;k5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7936?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=18?>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><73=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?278?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:1;72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~95<?25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:0;;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?367<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>53;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz590?61:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64?35;k5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7:36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=19?>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><63=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?378?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:0;72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~95=?25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:0:;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?377<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>43;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz591?61:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64>35;k5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7;36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=16?>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><93=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?<78?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:?;72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~952?25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:05;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?387<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>;3;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz59>?61:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64135;k5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7436?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=17?>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><83=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?=78?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:>;72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~953?25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:04;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t?397<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>:3;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz59??61:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64035;k5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1>1809V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<3112=<4=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?5579081^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;99854<5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp87===1809V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<3116=<4=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?5539081^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;99<54<5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp87==91809V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<311:=<4=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?55?9091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;9943=6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6:==071:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?2>10<;5>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>2578?92_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:69:43=6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6:=9071:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?2>14<;5>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>2538?92_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:69>43=6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6:=5071:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?2>18<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>25;>63\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz6975872:7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5;9=36>;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1?=2?:2?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=317;>63\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz6975<72:7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5;9936>;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1?=6?:2?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=313;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz697561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i548954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp87=9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?2>5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=35:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18419091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;9143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6:539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1?1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<321<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>15;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz694561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i54;954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp87>9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?2=5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=05:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18719091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;:143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;69539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1<1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<331<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>05;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz695561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i54:954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp87?9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?2<5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=15:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18619091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;;143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;68539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1=1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<341<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>75;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz692561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i54=954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp8789070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?2;5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=65:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18119091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;<143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6?539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1:1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<351<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>65;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz693561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i54<954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp8799070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?2:5?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=75:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18019091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;=143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6>539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1;1819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<361<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>55;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz690561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i54?954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp87:9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?295?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=45:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18319091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;>143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6=539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>181819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<371<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>45;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz691561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i54>954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp87;9070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?285?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=55:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18219091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;?143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6<539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>191819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<381<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>;5;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz69>561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i541954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp8749070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?275?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=:5:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18=19091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;0143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;63539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>161819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<391<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>:5;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz69?561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i540954=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp8759070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?265?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv2=;5:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18<19091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|4;1143<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;62539i;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>171479V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]LV@A)AVSN_RA]EF,V[JTBO:;0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+air|V~f|??4U1-J[KIXL'_TEAO U^VQMB)sz`mHccjFn308Q5)NWGETH#[PIMC,QZRUAN%~diLoofLqq733\:$ER@@_E,V[LJF'`KYA<64U1-J[KIXL'_TEAO iBCSPPTB901^<"GPNN]G*PYNDH%bOL^PDNLF66=R8&CTBBQK.T]JHD)nKHZTBXCPS@OSH@U;87887X> I^LL[A(RW@FJ#dMNP^LVIZUFEYFN_1?1229V4*OXFFUO"XQFL@-jGDVXF\GT_LC_LDQ?6;443\:$ER@@_E,V[LJF'`IJ\R@ZM^QBIUJB[595>>5Z0.K\JJYC&\UB@L!fC@R\JPKX[HG[@H]34?00?P6(AVDDSI Z_HNB+lEFXVD^AR]NMQNFW939::1^<"GPNN]G*PYNDH%bOL^PNTO\WDKWDLY7:3<<;T2,MZHHWM$^SDBN/hABTZHREVYJA]BJS=5=66=R8&CTBBQK.T]JHD)nKHZTBXCPS@OSH@U;07887X> I^LL[A(RW@FJ#dMNP^LVIZUFEYFN_1711e9V4*OXFFUO"XQFL@-jGDVX[]K_I1>11e9V4*OXFFUO"XQFL@-jGDVX[]K_I1?1219V4*OXFFUO"XQFL@-jGDVX\[CLKH\POTV2b>S7'@UECRJ!U^KOE*oDIYU\^ROKDS>3:4`<]9%BSCAPD/W\MIG(aJK[SZ\PAEFQ8486n2_;#DQAO^F-QZOKI&cHM]QXR^CG@W:568l0Y=!F_OM\@+SXAEK$eNO__VP\EABU4:4:j6[?/H]MKZB)]VCGM"gLAQ]TVZGCL[6?2<h4U1-J[KIXL'_TEAO iBCS[RTXIMNY080>f:W3+LYIGVN%YRGCA.k@EUYPZVKOH_29>0d8Q5)NWGETH#[PIMC,mFGWW^XTMIJ]<6<2b>S7'@UECRJ!U^KOE*oDIYU\^ROKDS>;:4`<]9%BSCAPD/W\MIG(aJK[SZ\PAEFQ8<86i2_;#DQAO^F-QZOKI&cHM]QXR^GM5==R8&CTBBQK.T]JHD)nLH^J0=0>a:W3+LYIGVN%YRGCA.kGEQG;99:5=l5Z0.K\JJYC&\UB@L!fD@VB846668k0Y=!F_OM\@+SXAEK$eIO[A=336;7f3\:$ER@@_E,V[LJF'`NJXL2>02<2e>S7'@UECRJ!U^KOE*oCI]K7==:11`9V4*OXFFUO"XQFL@-j@DRF48:>2<o4U1-J[KIXL'_TEAO iECWE977>7;j7X> I^LL[A(RW@FJ#dJNT@>24286i2_;#DQAO^F-QZOKI&cOMYO311:=5d=R8&CTBBQK.T]JHD)nLH^J0<>6>0;8Q5)NWGETH#[PIMC,mAGSI5;;2<o4U1-J[KIXL'_TEAO iECWE97687;j7X> I^LL[A(RW@FJ#dJNT@>25486i2_;#DQAO^F-QZOKI&cOMYO3100=5d=R8&CTBBQK.T]JHD)nLH^J0<?<>0c8Q5)NWGETH#[PIMC,mAGSI5;:83?n;T2,MZHHWM$^SDBN/hFBPD:69<4:m6[?/H]MKZB)]VCGM"gKAUC?54099h1^<"GPNN]G*PYNDH%bHLZN<034:4g<]9%BSCAPD/W\MIG(aMK_M1?>8?3b?P6(AVDDSI Z_HNB+lBF\H6:=40>9:W3+LYIGVN%YRGCA.kGEQG;984:m6[?/H]MKZB)]VCGM"gKAUC?57699h1^<"GPNN]G*PYNDH%bHLZN<002:4g<]9%BSCAPD/W\MIG(aMK_M1?=2?3b?P6(AVDDSI Z_HNB+lBF\H6:>>0>a:W3+LYIGVN%YRGCA.kGEQG;9;>5=l5Z0.K\JJYC&\UB@L!fD@VB844268k0Y=!F_OM\@+SXAEK$eIO[A=312;7f3\:$ER@@_E,V[LJF'`NJXL2>26<2=>S7'@UECRJ!U^KOE*oCI]K7=?0>9:W3+LYIGVN%YRGCA.kGEQG;9:4:56[?/H]MKZB)]VCGM"gKAUC?518612_;#DQAO^F-QZOKI&cOMYO314<2=>S7'@UECRJ!U^KOE*oCI]K7=;0>9:W3+LYIGVN%YRGCA.kGEQG;9>4:56[?/H]MKZB)]VCGM"gKAUC?5=8612_;#DQAO^F-QZOKI&cOMYO318<2<>S7'@UECRJ!U^KOE*oCI]K7=3?6;T2,MZHHWM$^SDBN/hFBPD:587;27X> I^LL[A(RW@FJ#dJNT@>15;7>3\:$ER@@_E,V[LJF'`NJXL2=2?3:?P6(AVDDSI Z_HNB+lBF\H69?3?6;T2,MZHHWM$^SDBN/hFBPD:5<7;27X> I^LL[A(RW@FJ#dJNT@>11;7>3\:$ER@@_E,V[LJF'`NJXL2=6?3:?P6(AVDDSI Z_HNB+lBF\H69;3?6;T2,MZHHWM$^SDBN/hFBPD:507;27X> I^LL[A(RW@FJ#dJNT@>1=;7?3\:$ER@@_E,V[LJF'`NJXL2=>0;8Q5)NWGETH#[PIMC,mAGSI59;2<74U1-J[KIXL'_TEAO iECWE9566830Y=!F_OM\@+SXAEK$eIO[A=11:4?<]9%BSCAPD/W\MIG(aMK_M1=<>0;8Q5)NWGETH#[PIMC,mAGSI59?2<74U1-J[KIXL'_TEAO iECWE9526830Y=!F_OM\@+SXAEK$eIO[A=15:4?<]9%BSCAPD/W\MIG(aMK_M1=8>0;8Q5)NWGETH#[PIMC,mAGSI5932<74U1-J[KIXL'_TEAO iECWE95>6820Y=!F_OM\@+SXAEK$eIO[A=1=5<=R8&CTBBQK.T]JHD)nLH^J09>1189V4*OXFFUO"XQFL@-j@DRF4=;5=45Z0.K\JJYC&\UB@L!fD@VB8149901^<"GPNN]G*PYNDH%bHLZN<51=5<=R8&CTBBQK.T]JHD)nLH^J09:1189V4*OXFFUO"XQFL@-j@DRF4=?5=45Z0.K\JJYC&\UB@L!fD@VB8109901^<"GPNN]G*PYNDH%bHLZN<55=5<=R8&CTBBQK.T]JHD)nLH^J0961189V4*OXFFUO"XQFL@-j@DRF4=35=55Z0.K\JJYC&\UB@L!fD@VB818612_;#DQAO^F-QZOKI&cOMYO351<2=>S7'@UECRJ!U^KOE*oCI]K79<0>9:W3+LYIGVN%YRGCA.kGEQG;=;4:56[?/H]MKZB)]VCGM"gKAUC?168612_;#DQAO^F-QZOKI&cOMYO355<2=>S7'@UECRJ!U^KOE*oCI]K7980>9:W3+LYIGVN%YRGCA.kGEQG;=?4:56[?/H]MKZB)]VCGM"gKAUC?128612_;#DQAO^F-QZOKI&cOMYO359<2=>S7'@UECRJ!U^KOE*oCI]K7940>8:W3+LYIGVN%YRGCA.kGEQG;=7;27X> I^LL[A(RW@FJ#dJNT@>54;7>3\:$ER@@_E,V[LJF'`NJXL291?3:?P6(AVDDSI Z_HNB+lBF\H6=>3?6;T2,MZHHWM$^SDBN/hFBPD:1;7;27X> I^LL[A(RW@FJ#dJNT@>50;7>3\:$ER@@_E,V[LJF'`NJXL295?3:?P6(AVDDSI Z_HNB+lBF\H6=:3?6;T2,MZHHWM$^SDBN/hFBPD:1?7;27X> I^LL[A(RW@FJ#dJNT@>5<;7>3\:$ER@@_E,V[LJF'`NJXL299?3;?P6(AVDDSI Z_HNB+lBF\H6=2<74U1-J[KIXL'_TEAO iECWE9176830Y=!F_OM\@+SXAEK$eIO[A=52:4?<]9%BSCAPD/W\MIG(aMK_M19=>0;8Q5)NWGETH#[PIMC,mAGSI5=82<74U1-J[KIXL'_TEAO iECWE9136830Y=!F_OM\@+SXAEK$eIO[A=56:4?<]9%BSCAPD/W\MIG(aMK_M199>0;8Q5)NWGETH#[PIMC,mAGSI5=<2<74U1-J[KIXL'_TEAO iECWE91?6830Y=!F_OM\@+SXAEK$eIO[A=5::4><]9%BSCAPD/W\MIG(aMK_M191189V4*OXFFUO"XQFL@-j@DRF41:5=45Z0.K\JJYC&\UB@L!fD@VB8=79901^<"GPNN]G*PYNDH%bHLZN<90=5<=R8&CTBBQK.T]JHD)nLH^J05=1189V4*OXFFUO"XQFL@-j@DRF41>5=45Z0.K\JJYC&\UB@L!fD@VB8=39901^<"GPNN]G*PYNDH%bHLZN<94=5<=R8&CTBBQK.T]JHD)nLH^J0591189V4*OXFFUO"XQFL@-j@DRF4125=45Z0.K\JJYC&\UB@L!fD@VB8=?9911^<"GPNN]G*PYNDH%bHLZN<9<2=>S7'@UECRJ!U^KOE*oCI]K75=0>9:W3+LYIGVN%YRGCA.kGEQG;184:56[?/H]MKZB)]VCGM"gKAUC?=78612_;#DQAO^F-QZOKI&cOMYO392<2=>S7'@UECRJ!U^KOE*oCI]K7590>9:W3+LYIGVN%YRGCA.kGEQG;1<4:56[?/H]MKZB)]VCGM"gKAUC?=38612_;#DQAO^F-QZOKI&cOMYO396<2=>S7'@UECRJ!U^KOE*oCI]K7550>9:W3+LYIGVN%YRGCA.kGEQG;104:46[?/H]MKZB)]VCGM"gKAUC?=;7f3\:$ER@@_E,V[LJF'`NJXLQKOTV2=>S7'@UECRJ!U^KOE*oUMZO_0=0>9:W3+LYIGVN%YRGCA.kQAVCS484:56[?/H]MKZB)]VCGM"g]ERGW878612_;#DQAO^F-QZOKI&cYI^K[<2<2=>S7'@UECRJ!U^KOE*oUMZO_090>9:W3+LYIGVN%YRGCA.kQAVCS4<4:56[?/H]MKZB)]VCGM"g]ERGW838612_;#DQAO^F-QZOKI&cYI^K[<6<2e>S7'@UECRJ!U^KOE*oT\H^THB[[199V4*OXFFUO"XQFL@-jPWO@OLX:96[?/H]WU5(@W]]P<P Z_US23>S7'@U_]= H_UUX556Z&\U_]<94U1-J[QW7&NU_[V??1\,V[QW6?2_;#DQ[Q1,D[QQ\998V"XQ[Q058Q5)NW][;"JQ[WZ337X(RW][:;6[?/H]WU5(@W]]P==:R.T]WU41<]9%BSY_?.F]WS^77=T$^SY_>7:W3+LYSY9$LSYYT114^*PYSY8=0Y=!F_US3*BYS_R;;;P Z_US23>S7'@U_]= H_UUX55>Z&\U_]<94U1-J[QW7&NU_[V??9\,V[QW6>2_;#DQ[Q1,D[QQ\99W%YRZ^169V4*OX\X:%KRZX[033Y+SX\X;<7X> I^VR4+AX\^Q:=<S!U^VR52=R8&CTX\>!G^VT_475U'_TX\?8;T2,MZRV8'MTXZU>12_-QZRV9>1^<"GPTP2-CZRPS8;?Q#[PTP34?P6(AV^Z<#IPTVY250[)]V^Z=:5Z0.K\PT6)OV^\W<?9]/W\PT703\:$ERZ^0/E\PR]69>W%YRZ^169V4*OX\X:%KRZX[03;Y+SX\X;<7X> I^VR4+AX\^Q:=4S!U^VR53=R8&CTX\>!G^VT_47Z&\U_]<94U1-J[QW7&NU_[V?=0\,V[QW6?2_;#DQ[Q1,D[QQ\9;;V"XQ[Q058Q5)NW][;"JQ[WZ316X(RW][:;6[?/H]WU5(@W]]P=?=R.T]WU41<]9%BSY_?.F]WS^75<T$^SY_>7:W3+LYSY9$LSYYT137^*PYSY8=0Y=!F_US3*BYS_R;9:P Z_US23>S7'@U_]= H_UUX571Z&\U_]<84U1-J[QW7&NU_[V?=]/W\PT713\:$ERZ^0/E\PR]6;T$^SY_>6:W3+LYSY9$LSYYT15_-QZRV9?1^<"GPTP2-CZRPS8?V"XQ[Q048Q5)NW][;"JQ[WZ35Y+SX\X;=7X> I^VR4+AX\^Q:;P Z_US22>S7'@U_]= H_UUX5=[)]V^Z=;5Z0.K\PT6)OV^\W<7R.T]WU43<]9%BSY_?.F]WS^7Z&\U_]<84U1-J[QW7&NU_[V<?]/W\PT713\:$ERZ^0/E\PR]59T$^SY_>6:W3+LYSY9$LSYYT23_-QZRV9?1^<"GPTP2-CZRPS;9V"XQ[Q048Q5)NW][;"JQ[WZ07Y+SX\X;=7X> I^VR4+AX\^Q99P Z_US22>S7'@U_]= H_UUX63[)]V^Z=;5Z0.K\PT6)OV^\W?9R.T]WU40<]9%BSY_?.F]WS^4?U'_TX\?9;T2,MZRV8'MTXZU=9\,V[QW6=2_;#DQ[Q1,D[QQ\:T$^SY_>6:W3+LYSY9$LSYYT31_-QZRV9?1^<"GPTP2-CZRPS:;V"XQ[Q048Q5)NW][;"JQ[WZ11Y+SX\X;=7X> I^VR4+AX\^Q8?P Z_US22>S7'@U_]= H_UUX71[)]V^Z=;5Z0.K\PT6)OV^\W>;R.T]WU40<]9%BSY_?.F]WS^51U'_TX\?9;T2,MZRV8'MTXZU<7\,V[QW6>2_;#DQ[Q1,D[QQ\;1W%YRZ^179V4*OX\X:%KRZX[2;^*PYSY8?0Y=!F_US3*BYS_R9V"XQ[Q048Q5)NW][;"JQ[WZ63Y+SX\X;=7X> I^VR4+AX\^Q?=P Z_US22>S7'@U_]= H_UUX07[)]V^Z=;5Z0.K\PT6)OV^\W9=R.T]WU40<]9%BSY_?.F]WS^23U'_TX\?9;T2,MZRV8'MTXZU;5\,V[QW6>2_;#DQ[Q1,D[QQ\<?W%YRZ^179V4*OX\X:%KRZX[55^*PYSY8<0Y=!F_US3*BYS_R>3Q#[PTP35?P6(AV^Z<#IPTVY7=X(RW][:96[?/H]WU5(@W]]P8P Z_US22>S7'@U_]= H_UUX15[)]V^Z=;5Z0.K\PT6)OV^\W8?R.T]WU40<]9%BSY_?.F]WS^35U'_TX\?9;T2,MZRV8'MTXZU:3\,V[QW6>2_;#DQ[Q1,D[QQ\==W%YRZ^179V4*OX\X:%KRZX[47^*PYSY8<0Y=!F_US3*BYS_R?=Q#[PTP35?P6(AV^Z<#IPTVY63X(RW][::6[?/H]WU5(@W]]P95S!U^VR53=R8&CTX\>!G^VT_0?Z&\U_]<;4U1-J[QW7&NU_[V;R.T]WU40<]9%BSY_?.F]WS^07U'_TX\?9;T2,MZRV8'MTXZU91\,V[QW6>2_;#DQ[Q1,D[QQ\>;W%YRZ^179V4*OX\X:%KRZX[71^*PYSY8<0Y=!F_US3*BYS_R<?Q#[PTP35?P6(AV^Z<#IPTVY51X(RW][::6[?/H]WU5(@W]]P:;S!U^VR53=R8&CTX\>!G^VT_31Z&\U_]<84U1-J[QW7&NU_[V87]/W\PT713\:$ERZ^0/E\PR]11T$^SY_>5:W3+LYSY9$LSYYT6\,V[QW6>2_;#DQ[Q1,D[QQ\?9W%YRZ^179V4*OX\X:%KRZX[63^*PYSY8<0Y=!F_US3*BYS_R=9Q#[PTP35?P6(AV^Z<#IPTVY47X(RW][::6[?/H]WU5(@W]]P;9S!U^VR53=R8&CTX\>!G^VT_23Z&\U_]<84U1-J[QW7&NU_[V99]/W\PT713\:$ERZ^0/E\PR]0?T$^SY_>6:W3+LYSY9$LSYYT79_-QZRV9?1^<"GPTP2-CZRPS>3V"XQ[Q078Q5)NW][;"JQ[WZ5^*PYSY8<0Y=!F_US3*BYS_R2;Q#[PTP35?P6(AV^Z<#IPTVY;5X(RW][::6[?/H]WU5(@W]]P4?S!U^VR53=R8&CTX\>!G^VT_=5Z&\U_]<84U1-J[QW7&NU_[V6;]/W\PT713\:$ERZ^0/E\PR]?=T$^SY_>6:W3+LYSY9$LSYYT87_-QZRV9?1^<"GPTP2-CZRPS1=V"XQ[Q048Q5)NW][;"JQ[WZ:;Y+SX\X;=7X> I^VR4+AX\^Q35P Z_US21>S7'@U_]= H_UUX<X(RW][::6[?/H]WU5(@W]]P5=S!U^VR53=R8&CTX\>!G^VT_<7Z&\U_]<84U1-J[QW7&NU_[V7=]/W\PT713\:$ERZ^0/E\PR]>;T$^SY_>6:W3+LYSY9$LSYYT95_-QZRV9?1^<"GPTP2-CZRPS0?V"XQ[Q048Q5)NW][;"JQ[WZ;5Y+SX\X;=7X> I^VR4+AX\^Q2;P Z_US22>S7'@U_]= H_UUX==[)]V^Z=;5Z0.K\PT6)OV^\W47R.T]WU43<]9%BSY_?.F]WS^?Z&\U_]h5Z0.kWVLAXAG6;2<>4U1-jPWO@W@D7==>1119V4*oSZ@MTEC2>00<24>S7'`^YEJQFN=336;773\:$eY\FG^KM846468:0Y=!fTSKD[LH;99>5==5Z0.kWVLAXAG6:<80>0:W3+lRUANUBB1??6?33?P6(a]XBKRGA<024:46<]9%bX_GH_HL?55>9991^<"g[RHE\MK:6804m7X> iUPJCZOI48:5==5Z0.kWVLAXAG6:==0>0:W3+lRUANUBB1?>1?33?P6(a]XBKRGA<031:46<]9%bX_GH_HL?5459991^<"g[RHE\MK:69=4:<6[?/hVQMBYNF5;:93??;T2,mQTNOVCE0<?9>028Q5)n\[CLSD@3105=55=R8&c_^DIPIO>25=8682_;#dZ]IF]JJ97617l0Y=!fTSKD[LH;984:<6[?/hVQMBYNF5;9<3??;T2,mQTNOVCE0<<>>028Q5)n\[CLSD@3130=55=R8&c_^DIPIO>2668682_;#dZ]IF]JJ975<7;;7X> iUPJCZOI488>2<>4U1-jPWO@W@D7=?81119V4*oSZ@MTEC2>26<e?P6(a]XBKRGA<00=b>S7'`^YEJQFN=30:c=R8&c_^DIPIO>20;`<]9%bX_GH_HL?508a3\:$eY\FG^KM8409n2_;#dZ]IF]JJ9706o1^<"g[RHE\MK:607l0Y=!fTSKD[LH;904n7X> iUPJCZOI484m7X> iUPJCZOI4;:5j6[?/hVQMBYNF58:2k5Z0.kWVLAXAG69>3h4U1-jPWO@W@D7>>0i;T2,mQTNOVCE0?:1f:W3+lRUANUBB1<:>g9V4*oSZ@MTEC2=6?d8Q5)n\[CLSD@326<e?P6(a]XBKRGA<3:=b>S7'`^YEJQFN=0::`=R8&c_^DIPIO>1:c=R8&c_^DIPIO>04;`<]9%bX_GH_HL?748a3\:$eY\FG^KM8649n2_;#dZ]IF]JJ9546o1^<"g[RHE\MK:4<7l0Y=!fTSKD[LH;;<4m7X> iUPJCZOI4:<5j6[?/hVQMBYNF59<2k5Z0.kWVLAXAG6843h4U1-jPWO@W@D7?40j;T2,mQTNOVCE0>0i;T2,mQTNOVCE09>1f:W3+lRUANUBB1:>>g9V4*oSZ@MTEC2;2?d8Q5)n\[CLSD@342<e?P6(a]XBKRGA<56=b>S7'`^YEJQFN=66:c=R8&c_^DIPIO>72;`<]9%bX_GH_HL?028a3\:$eY\FG^KM81>9n2_;#dZ]IF]JJ92>6l1^<"g[RHE\MK:36o1^<"g[RHE\MK:287l0Y=!fTSKD[LH;=84m7X> iUPJCZOI4<85j6[?/hVQMBYNF5?82k5Z0.kWVLAXAG6>83h4U1-jPWO@W@D7980i;T2,mQTNOVCE0881f:W3+lRUANUBB1;8>g9V4*oSZ@MTEC2:8?d8Q5)n\[CLSD@358<f?P6(a]XBKRGA<4<e?P6(a]XBKRGA<72=b>S7'`^YEJQFN=42:c=R8&c_^DIPIO>56;`<]9%bX_GH_HL?268a3\:$eY\FG^KM8329n2_;#dZ]IF]JJ9026o1^<"g[RHE\MK:1>7l0Y=!fTSKD[LH;>>4m7X> iUPJCZOI4?25j6[?/hVQMBYNF5<22h5Z0.kWVLAXAG6=2k5Z0.kWVLAXAG6<<3h4U1-jPWO@W@D7;<0i;T2,mQTNOVCE0:<1f:W3+lRUANUBB19<>g9V4*oSZ@MTEC284?d8Q5)n\[CLSD@374<e?P6(a]XBKRGA<64=b>S7'`^YEJQFN=54:c=R8&c_^DIPIO>4<;`<]9%bX_GH_HL?3<8b3\:$eY\FG^KM828a3\:$eY\FG^KM8=69n2_;#dZ]IF]JJ9>66o1^<"g[RHE\MK:?:7l0Y=!fTSKD[LH;0:4m7X> iUPJCZOI41>5j6[?/hVQMBYNF52>2k5Z0.kWVLAXAG63:3h4U1-jPWO@W@D74:0i;T2,mQTNOVCE0561f:W3+lRUANUBB166>d9V4*oSZ@MTEC27>g9V4*oSZ@MTEC260?d8Q5)n\[CLSD@390<e?P6(a]XBKRGA<80=b>S7'`^YEJQFN=;0:c=R8&c_^DIPIO>:0;`<]9%bX_GH_HL?=08a3\:$eY\FG^KM8<09n2_;#dZ]IF]JJ9?06o1^<"g[RHE\MK:>07l0Y=!fTSKD[LH;104n7X> iUPJCZOI404h7X]JR^TJWLDKM11^_HQ]LNA5?PYJ]QK=7XQBUY@5?PYJ]QI=7XQBUYF56>SXZHG$ERX9.T]@WZDUIDUHM^MNDD]U2*OXLLZ_DRB[EP]06N(RWZHYM@Q?/H]A73M@\9$LS_OBB24X4X(rW{kfn>8 U^PBIG51>;1^S_OB/H]U2+SXKZUI^LCPC@Q@EACX^?%BSIK_TI]OP@WX;;A%YR]MR@O\4*OXJ:<@KY>!G^PBIG51S8W%yR|nmc15+PYUIDH8:;<4U^PBI*OX^?$^SN]PBSCN[FGTKHNNS[8 I^FFTQNXD]OZS><D.T]PFWGJW9%BSO=9KFV3*BYUIDH8:V<R.t]qehd4>&_T^LCM3741?PYUID%BS[8!U^AP[GTFEVIJ_NOKE^T5+LYCMY^CSAZJQ^11O+SX[KXJAR> I^@02NAS8'MT^LCM37Y0Y+sXzhgi?;!Z_SCNF6013\UX^AO9;T]PVID13\UX^AM9;T]PVIB43_IH56XFEV]W]UC13^OJ0=09;VGB84813^OJ0?07;VGB86<76?1\IL2<>79TAG:76?1\IO2>>79TAG:5611\IO2<:1<5?RCE4:4i7Z\FTD]EMWUSk2]YEYKPMNFF[De<_[C_IRC@DD]A`>QUA]OT[DJ[H^Cg?RTN\LU\EIZG_C68\5_7<2R;U<;4X1[240=_8P;:96V?Y006?]6^9:?0T=W>449[4\72=2R;U<8;;Y2Z61=_8P9?7U>V459[4\333Q:R:95W0X57?]6^0=1S<T7>d:ZJHLH_%QNI,= > RVVF%6)9)KXODG:;YMQG\0<PZ^GEO94XRV\CKB03QY_S[MLb:Z\GJTBW@DMC;5Wdc]J`c=_laU[~dcYesqjkk773QnfS@oeosTfvvohf8:0TicPMhllvScu{`ee?6V|t29Zav5c3VUTTA@B_^]3[ZYR8&CTBBQK.T]JHD)RWZ^JX"HPSRVBP^4Z&@UXXLZ!U^QWEQ4a3VUTTA@B_^]24ZYX]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPFKC:j1TSRVCNL]\[47XWV_;#DQAO^F-QZOKI&_T^^Z U^RQWQ65j2UTSUBAM^]\57YXW\:$ER@@_E,V[LJF'\UY_Y!Z_SQW46><WVUS@CCP_^30[ZYR8&CTBBQK.T]JHD)RWZ^JX"[PTSKDC@TXoenS~k{3e9\[Z^KFDUTS<QP_T2,MZHHWM$^SDBN/T]PPDR(NVYXXLZT5\,J[VRF\'_T_YO[3e9\[Z^KFDUTS?QP_T2,MZHHWM$^SDBN/T]PPDR(NVYXXLZT6\,J[VRF\'_T_YO[3d9\[Z^KFDUTS>QP_T2,MZHHWM$^SDBN/T]PPDR(NVYXXLZT11_-MZUSI]$^S^ZNT2f8[ZY_DGGTSR:P_^W3+LYIGVN%YRGCA.W\WQGS'OUX_YO[[8_-MZUSI]$^S^ZNT758[ZY_DGGTSR;P_^W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RWFXT^^ZPRE]QKRYPAMO?m6QP_YNMIZYX>VUTY=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N34[VQ7:h1TSRVCNL]\[2YXW\:$ER@@_E,V[LJF'\UXXLZ U^LPH10<WVUS@CCP_^:\[ZS7'@UECRJ!U^KOE*SX[]K_#XQBUY-V[FUXE\R$E< Z_LW[6*Kj}qUD=<:;;^]\\IHJWVU2SRQZ0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!Z_CPH4g=f{pdhS`{w_0`8evikVg~tR<m;`qzjfYj}qU8==5nsxl`[qtffzln~R?>0:cp}keX|{kekk}_333?du~fjU~l`|fdp\7a=d``zxob~j_hnb74=d``zxob~j_hnb[s7X8<Uj -Vflhl{$FIUM)Mnbh|ntnp#56(412idyczjr^3:?firf}oyS?74cnwmp`tX;01hcx`{es]7b>etWkxjaRmnsbcga44<kzUi~lcPc`q`eacX~?;:7n}Pbscn[vojxeoTz;?7;bq\fwgjWzcf|akPv7]qehd4>h1hRmigmww0d=d{Vimka{{5b9`wZeaoe:R?l;bq\gcak}}<T>l5ls^aeciss?8h0o~Qloovqkidr{Vrxxza}k`plqkb692ixSnaznugq[hiccV;:=6m|_bmvjqcuWdeogR<m;bq\cdhcWzxg==5ls^ebjaYtzeU}:R?>0:ap[bgilVyy`Rx9_33;?fuXohdoS~|c_w4\vukX{l~T=<64cr]dekbX{{fTz;Q}pl]paqY59?1hRinne]pviYq>VygenkP1058gvY`ignTbPv7]phlebW8::;6m|_fcm`ZuudV|=S~bfcd]2541<kzUlmcjPssn\r3Ytd`inS<<>7:ap[bgilVyy`Rx9_rnjg`Y6;8=0o~Qhaof\wwjX~?Ux`dmj_0623>etWnkehR}}l^t5[vjnklU:9<94cr]dekbX{{fTz;Q|lhaf[406?2ixSjoad^qqhZp1WzfbohQ>7048gvY`ignTbPv7]phlebW;;=7n}Pg`lg[vtkW<Tagle^122>etWnkehR}}l^t5[vjnklU?=;5ls^ebjaYtzeU}:R}cibg\140<kzUlmcjPssn\r3Ytd`inS;?9;bq\cdhcWzxgS{8Psmk`aZ16>2ixSjoad^qqhZp1WzfbohQ7179`wZaffmUx~aQy6^qomfcX1j1hRinnez\wwja3jyTkl`kx^qqhZp112ixSa{{6^3:?fuXd|~=S?74cr]nq}750>1hRczx3:8gvYj}q<?;6m|_lw{<==d{Vg~tR?7;bq\ip~X:11hRczx^1;?fuXe|rT8o5ls^pfclusm{90hick;dfdaZbb|licj4g`lg[fguzp6;2h5haof\gdtuq5;;2h5haof\gdtuq5;:2h5haof\gdtuq5;92h5haof\gdtuq5;82h5haof\gdtuq5;?2h5haof\gdtuq5;>2i5haof\gdtuq5;5h6inne]`ewt~4;4o7joad^abvw;;7n0kl`k_bcqv|:36m1lmcjPc`pq}939l2mjbiQlaspz838c3nkehRmnrs{?3;b<ohdoSno}rx>;:a=`ignTol|}y=;=2>oki883>;5fl`31<)eoayyhc}kPimc\r4Y7=Vk'BB@J,OMMA440<2cgm<<7,bjjtvehxlUb`lQy1^26[d*|kVrhcRbfsu?@khvhfldSCobe<koe44?3Gfnh|POg]Wvla`m{U[cz|=09Ne}YTmxnbnkPLdtfhv;63\ynS_^Bs<vqq`=BfhhgiRZ}ifefvZIr|yS]a}t<dbhvc<[hg{`hQ@n<Pjwlh`3Zkf|akPD`vb[Acw|a7:<?:4Eocah`YT|fxjkhQ^u`njblef|`ee1y|ze:FbpdYTidoTM~Q[rhedaw;sz|o0Hlzn_QmqpZQnl}b6<6Z}ifefvZVhz}U\eizg_0?26==Ji}icSX`ftr]294=Dg|diQXievk[4;Cazki`hj4M`v`lZR~xlU:1oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX94lj`~k4Tskdc`tXXfxSZgkti]19==Ji}icSX`ftr]194=Dg|diQXievk[7;Cazki`hj4M`v`lZR~xlU91oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX:4lj`~k4Tskdc`tXXfxSZgkti]09==Ji}icSX`ftr]094=Dg|diQXievk[6;Cazki`hj4M`v`lZR~xlU81oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX;4lj`~k4Tskdc`tXXfxSZgkti]79==Ji}icSX`ftr]794=Dg|diQXievk[1;Cazki`hj4M`v`lZR~xlU?1oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX<4lj`~k4Tskdc`tXXfxSZgkti]69==Ji}icSX`ftr]694=Dg|diQXievk[0;Cazki`hj4M`v`lZR~xlU>1oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX=4lj`~k4Tskdc`tXXfxSZgkti]59==Ji}icSX`ftr]594=Dg|diQXievk[3;Cazki`hj4M`v`lZR~xlU=1oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX>4lj`~k4Tskdc`tXXfxSZgkti]49==Ji}icSX`ftr]494=Dg|diQXievk[2;Cazki`hj4M`v`lZR~xlU<1oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX?4lj`~k4Tskdc`tXXfxSZgkti];9==Ji}icSX`ftr];94=Dg|diQXievk[=;Cazki`hj4M`v`lZR~xlU31oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX04lj`~k4Tskdc`tXXfxSZgkti]:9==Ji}icSX`ftr]:94=Dg|diQXievk[<;Cazki`hj4M`v`lZR~xlU21oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX14lj`~k4Tskdc`tXXfxSZgkti]248><Eh~hdR[aiuq\55;63Je~byk}_VkgpmY684Nbllcee9NeqeoW]s{iR??=ccpmfYpa}bTiiijs:G{giscmVLyc`QKauc\WqiuinoT==3iamqf?QtnonoyS]a}t^Uj`qnX98737@o{ci]VjlrtW8;6=6M`uovfvZQnl}bT=<3Kircah`b<Eh~hdRZvpd]258df{`iT{dzg_dfdav=Bpjf~hhQIrno\@drfWZ~d~lij_03>bdjtm2^yejijr^RlvqYPam~cS<<28:ObpfnX]gcR?==09@kphsm{U\eizg_00>@lufjeoo7@o{ci]W}ucX9;7im~gl_vkwlZccoly0Iumcueg\BwijWMkmR]{oscdaZ755okgh5[rhedawYWg{~T[dj{h^309==Ji}icSX`ftr]2787<Kfexh|PWhfwlZ745Mcxmobjd:ObpfnX\pznS<=2b`qjgZqn|aUnhjk|;Dz`hpbbWOxdaRJnt`]PpjtfolU:?0hnlrg8Pwo`olxT\b|{_VkgpmY6<420Alzlh^WmmquX9=7:7Naznugq[Roc|aU:80Jfs``oaa=Ji}icSYwe^379ggtajU|eyfPeeefw>CkeoiRH}ol]GeqgX[}eymjkP15?eeiub3]xbkjk}_QmqpZQnl}bT=837;LcwgmYRf`~xS<;21:AlqkrbzV]bhyfP14?Gmvgedln0Alzlh^Vzt`Y6=4hjdmPwhvk[`b`mz1Ntnbzdd]EvjkXLh~jS^z`r`ef[43:nhfxi6Z}ifefvZVhz}U\eizg_04><>Kf|jbTYcg{s^3594=Dg|diQXievk[40:L`yjnakk;LcwgmYSqyoT=;3mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV;=1kocsd.`[}bb~`injlcflx?umwrbp?&hSna}e^vzt`;5$jUfjjQfd<3/gZkfbfxTzh||inl>56*dWdcecQyesqjkk;4$jUiydbk_sgumvohf4:'oRm`rd]neoiuWoy1<"l_bmqaZknffxTzh|24-a\gjtbWdcecQnlqjb[scu50='oR|nm^vzt`;6$jUx~a?9_u{sa84+kVxiRgav^aoo86+kVxiR|m<3/gZstmV~yejQ`uu?3(fYr{lUjxnQlljkm95*dW|ynSio{a<2/gZstmV~yej>21-a\qvcX|{cl=0>#c^wpaZruan86<!mPurg\pwo`;4:'oR{|e^vqmb2:8%iTy~kPtskd186+kVxiRz}if4>4)eX}zoTxgh7<2/gZstmV~yej620-a\qvcX|{cl50>#c^wpaZruan;;1="l_tqf[qtno8;6<!mPurg\pwo`9;7; nQzsd]wvla6;4:'oR{|e^vqmb7359&hSx}j_upjc43:8%iTy~kPtskd`drf84;'oR{|e^vqmbbf|h;6<!mPurg\pwo`lh~j>0>#c^wpaZruannjxl=20-a\qvcX|{clhlzn4<2/gZstmV~yejjnt`7>4)eX}zoTxghd`vb286+kVxiRz}iffbpd1:8%iTy~kPtskd`drf04:'oR{|e^vqmbbf|h36<!mPurg\pwo`lh~j==3?,b]vw`Ysz`momyo>1<2/gZstmV~yejjnt`3195*dW|ynSy|fgecwe45:8%iTy~kPtskd`drf9=7; nQzsd]wvlaci}k:90>#c^fbpdYpam~c1<"l_ecweZbbx}b6==<;,b]vw`Y`iy7; nQ{ilgppdkwW}s{i0>#c^vji`usidzT{dj{h<11(fYsadoxxlc_egspm;29;&hSx}j_rvlvdabWxj`0?#c^vpatYsqyo6<!mPnto\pvcvWjd1="l_uqfuZei|8U|eizg=0.`[qubyViex=Qxievk94*dWgfSy}jq^qweqct58&hSx}j_ua\ifhs59&hSymPmblw[roc|a7: nQjxu]`euYui}oTabjj=1.`[`~sWjk{S}ga_lmga86+kVd~aRkwt^abtZvnfz73 nQjxu]`euYr{lUyij3>,b]mqhYji}icSx`ftr?2(fYsz`m;Szgkti?26=*dW}xbk<Qxievk94*dW}xbk?Qxievk94*dW}xbk>Qxievk94*dW}xbk9Qxievk94*dW}xbk8Qxievk94*dW}xbk;Qxievk94*dW}xbk:Qxievk94*dW}xbk5Qxievk94*dW}xbk4Qxievk94*dW}xbk<>Pwhfwl87+kV~yej?>_vkgpm;6$jU~di>2^uj`qn:9%iTxgh12]tmaro58&hSy|fg06\slbs`4;'oRz}if36[roc|a7: nQb0^vsma;7$jUf=Rzie?2(fYj:V~{ei3=,b]n7Zrwam78 nQb4^vsma;3$jUf9Rzie?6(fYj>V~{ei39,b]n3Zrwam7< nQb8^vsma;?$jUf5Rzie?:(fYj99U|dj211.`[h76W}zbh0?>,b]n57Ysx`n6=?"l_l30[qvnl4;8 nQb15]wtlb:9=&hS`?:_urj`872$jUf<Rzvpd?2(fYj9V~r|h3?,b]n6Zr~xl7; nQb3^vzt`;7$jUf8Rzvpd?3(fYj=V~r|h3?,b]n2Zr~xl7; nQb7^vzt`;7$jUf4Rzvpd?3(fYj1V~r|h3?,b]n55Ysqyo6<!mPm03\p|vb59&hS`?=_u{sa86+kVg:?Rzvpd?3(fYj9=Uu}k20-a\i43X|pzn1="l_tqf[hei|97; nQzsd]ngkr659&hSx}j_lamp7;7$jU~hQbcov095*dW|ynS`mat5?3(fYr{lUfocz:=1.`[pubWdiex;3?,b]vw`Yjkg~<1="l_tqf[hei|17; nQzsd]ngkr>59&hSx}j_lamp46:8%iTy~kPmblw54;7$jU~hQbcov2686+kVxiRclnu3095*dW|ynS`mat06>4)eX}zoTan`{14?3(fYjkg~;Szgkti?2(fYjkg~:Szgkti?2(fYjkg~9Szgkti?2(fYjkg~8Szgkti?2(fYjkg~?Szgkti?2(fYjkg~>Szgkti?2(fYjkg~=Szgkti?2(fYjkg~<Szgkti?2(fYjkg~3Szgkti?2(fYjkg~2Szgkti?2(fYjkg~:<Ryfduj>5)eXejd=<Qxievk94*dWdiex<<Pwhfwl87+kVghby?<_vkgpm;6$jUfocz>4^uj`qn:9%iTan`{14]tmaro58&hSnaasupbmkrX|pzn1hcmeeff`)eXmqkf|akPddqjck;aieyn p?<;hnb57>X\@GN_]KL_OAEb>okiVij|Rokdsefj44<aekTol~Pcupo[b4X{xl0eaoPc`r\wqiuino37dbn_bmqa<=ndhUfmymg109jhdYji}icSnabbhlfb>okiVgjxnfPcnoak`=ndhUfmymg_fcm`c=ndhUfmymg_fcm`}c<aekT~h}jt^awvig<aekTyo{ur33?ljfW}xjohQmugdfv`=ndhU~diPm`v`lf=ndhU~diloof24>okiV~yejm`ne]oqqd<aekTxghgdp`?iekWzxgS|2?>b9ogiYtzeUz0<0l;mao[vtkWx692o5buyaz[ii;87h0axvly^nl848e3dsotQco=0=f>krpjsT`b2<>c9nq}e~Wee783m4mtz`}Zubd5:5o6czxb{\w`j;97i0axvly^qfh949k2g~tnwPsdn?7;><fniiydbk139svjauidgjnakPddnb}<=tzeUz0<>19:qqhZw;98427~|c_p>26;?<{{fT}1?<>89pviYv48>556}}l^s?508?3zxgS|2>>99pviYv4;437~|c_p>0:==tzeUz0907;rpo[t:2611x~aQ~<7<;?vtkWx6<255|rm]r8=8?3zxgS|26>|BCt65?=2JKtim7:G87>4}Tij0o:o4<7e8276630o0:n:kj{of5=?7<fm<j6;5+d759`37<uZ2>6i8m:25g>4548=2m6<l7009P735=ll21<7?<316;b?7e0990_5;5dd:94?74;9>3j7?m8158`ae?290:6<u\ab8g2g<4?m0:?>>;8g82f2`e3^8554?:082>33fsZkh6i8m:25g>4548=2m6<l8fc9'`16=;??0Zi87:3yv726=928;<4?;|&03c<5m2hoo54?:`79034==<npDi=>;%671?bd02P==7<t16817?{#l?<1h5<4$7f9`f?<,hh1hno4$2;6>4=#;0>1h;m4i2ff>5<#;1;1?ij4n2:3>5=<a:nh6=4+39397ab<f:2;6<54i2fa>5<#;1;1?ij4n2:3>7=<a:nj6=4+39397ab<f:2;6>54i2f:>5<#;1;1?ij4n2:3>1=<a:n36=4+39397ab<f:2;6854i2f4>5<#;1;1?ij4n2:3>3=<a:n=6=4+39397ab<f:2;6:54i2f7>5<#;1;1?ij4n2:3>==<a:n86=4+39397ab<f:2;6454i2f1>5<#;1;1?ij4n2:3>d=<a:n:6=4+39397ab<f:2;6o54i2f3>5<#;1;1?ij4n2:3>f=<a:im6=4+39397ab<f:2;6i54i2af>5<#;1;1?ij4n2:3>`=<a:io6=4+39397ab<f:2;6k54i2a`>5<#;1;1?ij4n2:3>46<3`9hn7>5$2:2>6bc3g93<7?>;:k0g<<72-93=7=kd:l0<5<6:21b?n650;&0<4<4lm1e?5>51298m6e0290/?5?53ef8j6>728>07d=l6;29 6>62:no7c=70;36?>o4k<0;6)=71;1g`>h4090::65f3b694?"40808hi5a392952=<a:i86=4+39397ab<f:2;6<64;h1`6?6=,:2:6>jk;o1;4?7>32c8o<4?:%1;5?5cl2d84=4>a:9j7f6=83.84<4<de9m7=6=9k10e9=j:18'7=7=;mn0b>6?:0a8?l24l3:1(>6>:2fg?k5?83;o76g;3b83>!5?939oh6`<8182a>=n<:h1<7*<8080`a=i;1:1=k54i51b>5<#;1;1?ij4n2:3>76<3`>857>5$2:2>6bc3g93<7<>;:k77=<72-93=7=kd:l0<5<5:21b8>950;&0<4<4lm1e?5>52298m151290/?5?53ef8j6>72;>07d:<5;29 6>62:no7c=70;06?>o3;:0;6)=71;1g`>h40909:65f42094?"40808hi5a392962=<a=9:6=4+39397ab<f:2;6?64;h604?6=,:2:6>jk;o1;4?4>32c?>k4?:%1;5?5cl2d84=4=a:9j07c=83.84<4<de9m7=6=:k10e9<k:18'7=7=;mn0b>6?:3a8?l25k3:1(>6>:2fg?k5?838o76g;2c83>!5?939oh6`<8181a>=n<;k1<7*<8080`a=i;1:1>k54i50;>5<#;1;1?ij4n2:3>66<3`>9;7>5$2:2>6bc3g93<7=>;:k763<72-93=7=kd:l0<5<4:21b8?;50;&0<4<4lm1e?5>53298m143290/?5?53ef8j6>72:>07d:=3;29 6>62:no7c=70;16?>o3:;0;6)=71;1g`>h40908:65f43394?"40808hi5a392972=<a=8;6=4+39397ab<f:2;6>64;h62b?6=,:2:6>jk;o1;4?5>32c?=i4?:%1;5?5cl2d84=4<a:9j04e=83.84<4<de9m7=6=;k10e9?m:18'7=7=;mn0b>6?:2a8?l26i3:1(>6>:2fg?k5?839o76g;1883>!5?939oh6`<8180a>=n<821<7*<8080`a=i;1:1?k54i534>5<#;1;1?ij4n2:3>16<3`>::7>5$2:2>6bc3g93<7:>;:k750<72-93=7=kd:l0<5<3:21b8<:50;&0<4<4lm1e?5>54298m175290/?5?53ef8j6>72=>07d:>1;29 6>62:no7c=70;66?>o3990;6)=71;1g`>h4090?:65f41d94?"40808hi5a392902=<a=:n6=4+39397ab<f:2;6964;h63`?6=,:2:6>jk;o1;4?2>32c?<n4?:%1;5?5cl2d84=4;a:9j05d=83.84<4<de9m7=6=<k10e9>n:18'7=7=;mn0b>6?:5a8?l2713:1(>6>:2fg?k5?83>o76g;0683>!5?939oh6`<8187a>=n<9<1<7*<8080`a=i;1:18k54i526>5<#;1;1?ij4n2:3>06<3`>;87>5$2:2>6bc3g93<7;>;:k746<72-93=7=kd:l0<5<2:21b8=<50;&0<4<4lm1e?5>55298m166290/?5?53ef8j6>72<>07d:?0;29 6>62:no7c=70;76?>o4no0;6)=71;1g`>h4090>:65f3gg94?"40808hi5a392912=<a:lh6=4+39397ab<f:2;6864;h1ef?6=,:2:6>jk;o1;4?3>32c8jl4?:%1;5?5cl2d84=4:a:9j7c?=83.84<4<de9m7=6==k10e>h7:18'7=7=;mn0b>6?:4a8?l5a?3:1(>6>:2fg?k5?83?o76g<f783>!5?939oh6`<8186a>=n;o?1<7*<8080`a=i;1:19k54i2d7>5<#;1;1?ij4n2:3>36<3`9m?7>5$2:2>6bc3g93<78>;:k0b4<72-93=7=kd:l0<5<1:21b?k>50;&0<4<4lm1e?5>56298m6ca290/?5?53ef8j6>72?>07d=je;29 6>62:no7c=70;46?>o4mm0;6)=71;1g`>h4090=:65f3da94?"40808hi5a392922=<a:oi6=4+39397ab<f:2;6;64;h1fe?6=,:2:6>jk;o1;4?0>32c8i44?:%1;5?5cl2d84=49a:9j7`>=83.84<4<de9m7=6=>k10e>k9:18'7=7=;mn0b>6?:7a8?l5b=3:1(>6>:2fg?k5?83<o76g<e583>!5?939oh6`<8185a>=n;l91<7*<8080`a=i;1:1:k54i2g1>5<#;1;1?ij4n2:3>26<3`9n=7>5$2:2>6bc3g93<79>;:k0a5<72-93=7=kd:l0<5<0:21b?ih50;&0<4<4lm1e?5>57298m6b2290/?5?53ef8j6>72>>07d=la;29 6>62:no7c=70;56?>o3;o0;6)=71;1g`>h4090<:65f42694?"40808hi5a392932=<a=826=4+39397ab<f:2;6:64;h62a?6=,:2:6>jk;o1;4?1>32c?=>4?:%1;5?5cl2d84=48a:9j05>=83.84<4<de9m7=6=?k10e>hk:18'7=7=;mn0b>6?:6a8?l5a:3:1(>6>:2fg?k5?83=o76g<e683>!5?939oh6`<8184a>=n;kl1<7*<8080`a=i;1:1;k54+`194?"4080j>6`<8183?>-f93:1(>6>:`08j6>72810'l>50;&0<4<f:2d84=4=;:):b?6=,:2:6l<4n2:3>6=<#0o1<7*<808b6>h4090?76%6d;29 6>62h80b>6?:498/<d=83.84<4n2:l0<5<132!2m7>5$2:2>d4<f:2;6:54+8;94?"4080j>6`<818;?>->03:1(>6>:`08j6>72010'4950;&0<4<f:2d84=4n;:):2?6=,:2:6l<4n2:3>g=<#0?1<7*<808b6>h4090h76%64;29 6>62h80b>6?:e98/<5=83.84<4n2:l0<5<b32!2>7>5$2:2>d4<f:2;6k54+8294?"4080j>6`<81824>=,0o0;6)=71;c1?k5?83;:76%7e;29 6>62h80b>6?:008?.>c290/?5?5a39m7=6=9:10'5m50;&0<4<f:2d84=4>4:9(<g<72-93=7o=;o1;4?7232!3m7>5$2:2>d4<f:2;6<84;*::>5<#;1;1m?5a392952=<#121<7*<808b6>h4090:465$8683>!5?93k97c=70;3:?>-fi3:1(>6>:`08j6>728k07&o6:18'7=7=i;1e?5>51c98/d>=83.84<4n2:l0<5<6k21 m:4?:%1;5?g53g93<7?k;:)b2?6=,:2:6l<4n2:3>4c<3"k>6=4+3939e7=i;1:1=k54+8a94?"4080j>6`<81815>=,180;6)=71;c1?k5?838976%76;29 6>62h80b>6?:318?l0a2900'l:50;&0<4<f:2d84=4=0:9a`33=83;1<7>t$566>a5a3An=?6Fk309l72c=831vni8;:182>5<7s->?97<ne:Jg26=Ol:;0c<86:188yg?003:157>50z&700<41k1Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?i1<75f6g83>>ofl3:17b=75;29?j5?>3:17pl67e83><<729q/89;538`8La043An8=6*=c680?l552900e>=50;9j71<722c897>5;h4`>5<<a?l1<75fae83>>i40<0;66a<8783>>{e1><1<7<50;2x 1222:<=7Ej93:Jg74=#:j=1=?5f2c394?=h;>i1<75rb63:>5<3290;w):;5;15<>Nc>:1Ch>?4$3a4>35<,:296i9>;h0a5?6=3`8i>7>5;h0a7?6=3f9<o7>5;|`:3`<72=0;6=u+457950d<@m<87Ej<1:&1g2<53`<96=44i`f94?=n;121<75`39794?=zj0=26=4;:183!23=3;>n6Fk629K`67<,;i<6?5f6383>>ofl3:17d=78;29?j5?=3:17pl67c83>1<729q/89;514`8La043An8=6*=c681?l052900elj50;9j7=>=831d?5;50;9~f<>7290?6=4?{%671?72j2Bo:>5Gd238 7e02;1b:?4?::kb`?6=3`9347>5;n1;1?6=3th2;:4?:583>5}#<=?1=8l4He40?Mb492.9o:4=;h41>5<<ahn1<75f39:94?=h;1?1<75rb8:7>5<3290;w):;5;36`>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o41;0;66a<8483>>{e1>?1<7:50;2x 12228?i7Ej93:Jg74=#:j=1>6g92;29?lgc2900e>67:188k6>22900qo:72;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<1:1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c64a?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi8:m50;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg20i3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm46:94?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk><:7>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a022=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:80;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<?o1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c65g?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi8;o50;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg2103:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm47494?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk>=87>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a034=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:90;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<<o1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c66e?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi88650;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg22>3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm44694?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk>>>7>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a006=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:;e;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<=i1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c67e?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi89650;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg33:3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm55294?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk?8i7>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a16e=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo;<a;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e=:21<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c702?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi9>:50;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg34:3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm52294?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk?9o7>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a17g=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo;=8;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e=;<1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c710?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi9?<50;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg3583:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm50g94?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk?:o7>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a14g=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo;>6;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e=8>1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c726?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi9<>50;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg37m3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm51a94?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk?;m7>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a15>=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo;?6;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e=9>1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c734?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi8kk50;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg2ak3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm4gc94?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk>m47>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a0c0=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:i4;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<o81<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c6e4?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi8hk50;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg2bi3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm4d:94?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk>n:7>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a0`2=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:j2;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<l:1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c6ga?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi8im50;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg2ci3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm4e:94?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk>o87>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a0a4=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:k0;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<jo1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c6`g?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi8no50;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg2d03:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm4b494?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk>h87>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a0f4=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:me;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<ki1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c6ae?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi8o650;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg2e>3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm4c694?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk>i>7>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a0g6=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:ne;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<hi1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c6b<?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi8l850;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg2f<3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm4`094?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk>j<7>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a0<c=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:6c;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<0k1<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c6:<?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi84850;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg2>:3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm48294?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk>3i7>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a0=e=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:7a;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e<121<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c6;2?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi85:50;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg20:3:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm44a94?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk??87>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a17c=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo;>8;293?6=8r.?884<989K`35<@m9:7)<l7;18m64=831b?>4?::k00?6=3`9>6=44i7d94?=nim0;66a<8483>>{e=981<7950;2x 1222:327Ej93:Jg74=#:j=1?6g<2;29?l542900e>:50;9j70<722c=j7>5;hcg>5<<g:2>6=44}c6fg?6=?3:1<v*;4480=<=Ol?90Di=>;%0`3?5<a:81<75f3283>>o4<3:17d=::188m3`=831bmi4?::m0<0<722wi8i850;594?6|,=>>6>76;If57>Nc;81/>n953:k06?6=3`986=44i2694?=n;<0;66g9f;29?lgc2900c>6::188yg2d83:1;7>50z&700<4101Ch;=4He12?!4d?390e><50;9j76<722c887>5;h16>5<<a?l1<75fae83>>i40<0;66sm4`c94?1=83:p(9:::2;:?Mb1;2Bo?<5+2b597>o4:3:17d=<:188m62=831b?84?::k5b?6=3`ko6=44o2:6>5<<uk>287>57;294~"3<<08545Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;h50;9jea<722e8484?::a010=83=1<7>t$566>6?>3An=?6Fk309'6f1=;2c8>7>5;h10>5<<a:>1<75f3483>>o1n3:17dok:188k6>22900qo:73;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi85?50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk><j7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<>n1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg20j3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a02?=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c643?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm46794?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo:81;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi8;h50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>=h7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<?h1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg2113:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a031=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c651?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm47194?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo:91;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi88h50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>>n7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<<31<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg22?3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a003=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c667?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm44394?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo:;f;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi89j50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>?n7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<=31<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg33;3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a117=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c70b?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm52f94?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo;<b;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi9>750;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk?8;7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e=:?1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg34;3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a167=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c71`?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm53`94?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo;=9;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi9?950;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk?997>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e=;91<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg3593:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a14`=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c72`?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm50`94?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo;>7;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi9<;50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk?:?7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e=8;1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg37n3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a15b=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c73f?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm51;94?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo;?7;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi9=;50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk?;=7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<ol1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg2al3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a0cd=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c6e=?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm4g594?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo:i5;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi8k=50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>m=7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<ll1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg2bj3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a0`?=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c6f3?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm4d794?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo:j3;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi8h?50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>oj7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<mn1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg2cj3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a0a?=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c6g1?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm4e194?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo:k1;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi8nh50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>hh7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<jh1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg2d13:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a0f1=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c6`1?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm4b194?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo:mf;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi8oj50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>in7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<k31<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg2e?3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a0g3=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c6a7?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm4c394?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo:nf;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi8lj50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>j57>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<h=1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg2f=3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a0d5=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c6b5?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm48d94?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo:6d;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi84l50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>257>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<0=1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg2>;3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a0<7=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c6;b?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm49f94?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo:7b;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi85750;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>3;7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<1?1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg20;3:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a00b=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c771?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm53d94?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qo;>9;297?6=8r.?884>529K`35<@m9:7)<l7;08m34=831bmi4?::m0<0<722wi9==50;194?6|,=>>6<;<;If57>Nc;81/>n952:k56?6=3`ko6=44o2:6>5<<uk>nh7>53;294~"3<<0:9>5Gd718La563-8h;7<4i7094?=nim0;66a<8483>>{e<m=1<7=50;2x 12228?87Ej93:Jg74=#:j=1>6g92;29?lgc2900c>6::188yg2d93:1?7>50z&700<6=:1Ch;=4He12?!4d?380e;<50;9jea<722e8484?::a0dd=8391<7>t$566>4343An=?6Fk309'6f1=:2c=>7>5;hcg>5<<g:2>6=44}c6:1?6=;3:1<v*;448216=Ol?90Di=>;%0`3?4<a?81<75fae83>>i40<0;66sm45594?5=83:p(9:::070?Mb1;2Bo?<5+2b596>o1:3:17dok:188k6>22900qoo76;29511=990::8uGd238 1222m3=7W8>:0y2a?{#l:8189>4i37e>5<#;1;1>8k4n2:3>5=<a;?o6=4+393960c<f:2;6<54i37`>5<#;1;1>8k4n2:3>7=<a;?i6=4+393960c<f:2;6>54i37b>5<#;1;1>8k4n2:3>1=<a;?26=4+393960c<f:2;6854i37;>5<#;1;1>8k4n2:3>3=<a;?<6=4+393960c<f:2;6:54i375>5<#;1;1>8k4n2:3>==<a;?>6=4+393960c<f:2;6454i370>5<#;1;1>8k4n2:3>d=<a;?96=4+393960c<f:2;6o54i372>5<#;1;1>8k4n2:3>f=<a;?;6=4+393960c<f:2;6i54i36e>5<#;1;1>8k4n2:3>`=<a;>n6=4+393960c<f:2;6k54i36g>5<#;1;1>8k4n2:3>46<3`8?o7>5$2:2>73b3g93<7?>;:k10g<72-93=7<:e:l0<5<6:21b>9o50;&0<4<5=l1e?5>51298m720290/?5?524g8j6>728>07d<;6;29 6>62;?n7c=70;36?>o5<<0;6)=71;06a>h4090::65f25694?"408099h5a392952=<a;>86=4+393960c<f:2;6<64;h076?6=,:2:6?;j;o1;4?7>32c98<4?:%1;5?42m2d84=4>a:9j616=83.84<4=5d9m7=6=9k10e?=i:18'7=7=:<o0b>6?:0a8?l44m3:1(>6>:37f?k5?83;o76g=3b83>!5?938>i6`<8182a>=n::h1<7*<80811`=i;1:1=k54i31b>5<#;1;1>8k4n2:3>76<3`8857>5$2:2>73b3g93<7<>;:k17=<72-93=7<:e:l0<5<5:21b>>950;&0<4<5=l1e?5>52298m751290/?5?524g8j6>72;>07d<<5;29 6>62;?n7c=70;06?>o5;=0;6)=71;06a>h40909:65f22194?"408099h5a392962=<a;9:6=4+393960c<f:2;6?64;h004?6=,:2:6?;j;o1;4?4>32c9>k4?:%1;5?42m2d84=4=a:9j67c=83.84<4=5d9m7=6=:k10e?<k:18'7=7=:<o0b>6?:3a8?l45k3:1(>6>:37f?k5?838o76g=2c83>!5?938>i6`<8181a>=n:;k1<7*<80811`=i;1:1>k54i30:>5<#;1;1>8k4n2:3>66<3`8947>5$2:2>73b3g93<7=>;:k163<72-93=7<:e:l0<5<4:21b>?;50;&0<4<5=l1e?5>53298m743290/?5?524g8j6>72:>07d<=3;29 6>62;?n7c=70;16?>o5:;0;6)=71;06a>h40908:65f23394?"408099h5a392972=<a;8;6=4+393960c<f:2;6>64;h02b?6=,:2:6?;j;o1;4?5>32c9=h4?:%1;5?42m2d84=4<a:9j64b=83.84<4=5d9m7=6=;k10e??m:18'7=7=:<o0b>6?:2a8?l46i3:1(>6>:37f?k5?839o76g=1883>!5?938>i6`<8180a>=n:821<7*<80811`=i;1:1?k54i334>5<#;1;1>8k4n2:3>16<3`8::7>5$2:2>73b3g93<7:>;:k150<72-93=7<:e:l0<5<3:21b><:50;&0<4<5=l1e?5>54298m774290/?5?524g8j6>72=>07d<>2;29 6>62;?n7c=70;66?>o5990;6)=71;06a>h4090?:65f21d94?"408099h5a392902=<a;:n6=4+393960c<f:2;6964;h03`?6=,:2:6?;j;o1;4?2>32c9<n4?:%1;5?42m2d84=4;a:9j65d=83.84<4=5d9m7=6=<k10e?>n:18'7=7=:<o0b>6?:5a8?l4713:1(>6>:37f?k5?83>o76g=0983>!5?938>i6`<8187a>=n:9=1<7*<80811`=i;1:18k54i326>5<#;1;1>8k4n2:3>06<3`8;87>5$2:2>73b3g93<7;>;:k146<72-93=7<:e:l0<5<2:21b>=<50;&0<4<5=l1e?5>55298m766290/?5?524g8j6>72<>07d<?0;29 6>62;?n7c=70;76?>o6no0;6)=71;06a>h4090>:65f1gg94?"408099h5a392912=<a8lo6=4+393960c<f:2;6864;h3eg?6=,:2:6?;j;o1;4?3>32c:jl4?:%1;5?42m2d84=4:a:9j5c?=83.84<4=5d9m7=6==k10e<h7:18'7=7=:<o0b>6?:4a8?l7a?3:1(>6>:37f?k5?83?o76g>f783>!5?938>i6`<8186a>=n9o?1<7*<80811`=i;1:19k54i0d7>5<#;1;1>8k4n2:3>36<3`;m?7>5$2:2>73b3g93<78>;:k2b7<72-93=7<:e:l0<5<1:21b=k?50;&0<4<5=l1e?5>56298m4ca290/?5?524g8j6>72?>07d?je;29 6>62;?n7c=70;46?>o6mm0;6)=71;06a>h4090=:65f1da94?"408099h5a392922=<a8oi6=4+393960c<f:2;6;64;h3fe?6=,:2:6?;j;o1;4?0>32c:i44?:%1;5?42m2d84=49a:9j5`>=83.84<4=5d9m7=6=>k10e<k8:18'7=7=:<o0b>6?:7a8?l7b>3:1(>6>:37f?k5?83<o76g>e583>!5?938>i6`<8185a>=n9l91<7*<80811`=i;1:1:k54i0g1>5<#;1;1>8k4n2:3>26<3`;n=7>5$2:2>73b3g93<79>;:k2a5<72-93=7<:e:l0<5<0:21b=ih50;&0<4<5=l1e?5>57298m4bb290/?5?524g8j6>72>>07d?kd;29 6>62;?n7c=70;56?>o6lj0;6)=71;06a>h4090<:65f1e`94?"408099h5a392932=<a8n36=4+393960c<f:2;6:64;h3g3?6=,:2:6?;j;o1;4?1>32c:h;4?:%1;5?42m2d84=48a:9j5a3=83.84<4=5d9m7=6=?k10e<j;:18'7=7=:<o0b>6?:6a8?l7c;3:1(>6>:37f?k5?83=o76g>d383>!5?938>i6`<8184a>=n9m;1<7*<80811`=i;1:1;k54i0f3>5<#;1;1>8k4n2:3>=6<3`;hj7>5$2:2>73b3g93<76>;:k2ga<72-93=7<:e:l0<5<?:21b=nm50;&0<4<5=l1e?5>58298m4ee290/?5?524g8j6>721>07d?la;29 6>62;?n7c=70;:6?>o6k00;6)=71;06a>h40903:65f1b:94?"408099h5a3929<2=<a8i<6=4+393960c<f:2;6564;h3`2?6=,:2:6?;j;o1;4?>>32c:o84?:%1;5?42m2d84=47a:9j5f2=83.84<4=5d9m7=6=0k10e<m=:18'7=7=:<o0b>6?:9a8?l7d93:1(>6>:37f?k5?832o76g>c183>!5?938>i6`<818;a>=n9kl1<7*<80811`=i;1:14k54i0`f>5<#;1;1>8k4n2:3><6<3`;ih7>5$2:2>73b3g93<77>;:k2ff<72-93=7<:e:l0<5<>:21b=ol50;&0<4<5=l1e?5>59298m4df290/?5?524g8j6>720>07d?m9;29 6>62;?n7c=70;;6?>o6j>0;6)=71;06a>h40902:65f1c494?"408099h5a3929=2=<a8h>6=4+393960c<f:2;6464;h3a0?6=,:2:6?;j;o1;4??>32c:n>4?:%1;5?42m2d84=46a:9j5g4=83.84<4=5d9m7=6=1k10e<l>:18'7=7=:<o0b>6?:8a8?l7e83:1(>6>:37f?k5?833o76g>ag83>!5?938>i6`<818:a>=n9ho1<7*<80811`=i;1:15k54i0c`>5<#;1;1>8k4n2:3>d6<3`;jn7>5$2:2>73b3g93<7o>;:k2ed<72-93=7<:e:l0<5<f:21b=l750;&0<4<5=l1e?5>5a298m4g?290/?5?524g8j6>72h>07d?n7;29 6>62;?n7c=70;c6?>o6i?0;6)=71;06a>h4090j:65f1`794?"408099h5a3929e2=<a8k?6=4+393960c<f:2;6l64;h3b7?6=,:2:6?;j;o1;4?g>32c:m<4?:%1;5?42m2d84=4na:9j5d6=83.84<4=5d9m7=6=ik10e<7i:18'7=7=:<o0b>6?:`a8?l7>m3:1(>6>:37f?k5?83ko76g>9e83>!5?938>i6`<818ba>=n90i1<7*<80811`=i;1:1mk54i0;a>5<#;1;1>8k4n2:3>g6<3`;2m7>5$2:2>73b3g93<7l>;:k2=<<72-93=7<:e:l0<5<e:21b=4650;&0<4<5=l1e?5>5b298m4?1290/?5?524g8j6>72k>07d?65;29 6>62;?n7c=70;`6?>o61=0;6)=71;06a>h4090i:65f18194?"408099h5a3929f2=<a8396=4+393960c<f:2;6o64;h3:5?6=,:2:6?;j;o1;4?d>32c:5=4?:%1;5?42m2d84=4ma:9j5=`=83.84<4=5d9m7=6=jk10e<6j:18'7=7=:<o0b>6?:ca8?l7?l3:1(>6>:37f?k5?83ho76g>8c83>!5?938>i6`<818aa>=n91k1<7*<80811`=i;1:1nk54i0::>5<#;1;1>8k4n2:3>f6<3`;347>5$2:2>73b3g93<7m>;:k2<2<72-93=7<:e:l0<5<d:21b=5850;&0<4<5=l1e?5>5c298m4>2290/?5?524g8j6>72j>07d?74;29 6>62;?n7c=70;a6?>o60:0;6)=71;06a>h4090h:65f19094?"408099h5a3929g2=<a82;6=4+393960c<f:2;6n64;h34b?6=,:2:6?;j;o1;4?e>32c:;h4?:%1;5?42m2d84=4la:9j52b=83.84<4=5d9m7=6=kk10e<9l:18'7=7=:<o0b>6?:ba8?l70j3:1(>6>:37f?k5?83io76g>7`83>!5?938>i6`<818`a>=n9>31<7*<80811`=i;1:1ok54i05;>5<#;1;1>8k4n2:3>a6<3`;<;7>5$2:2>73b3g93<7j>;:k230<72-93=7<:e:l0<5<c:21b=::50;&0<4<5=l1e?5>5d298m414290/?5?524g8j6>72m>07d?82;29 6>62;?n7c=70;f6?>o6?80;6)=71;06a>h4090o:65f16294?"408099h5a3929`2=<a8<m6=4+393960c<f:2;6i64;h35a?6=,:2:6?;j;o1;4?b>32c::i4?:%1;5?42m2d84=4ka:9j53e=83.84<4=5d9m7=6=lk10e?on:18'7=7=:<o0b>6?:ea8?l4f13:1(>6>:37f?k5?83no76g=a983>!5?938>i6`<818ga>=n:h=1<7*<80811`=i;1:1hk54i3c5>5<#;1;1>8k4n2:3>`6<3`8j97>5$2:2>73b3g93<7k>;:k1e1<72-93=7<:e:l0<5<b:21b>l=50;&0<4<5=l1e?5>5e298m7g5290/?5?524g8j6>72l>07d<n1;29 6>62;?n7c=70;g6?>o51o0;6)=71;06a>h4090n:65f28g94?"408099h5a3929a2=<a;3o6=4+393960c<f:2;6h64;h0:g?6=,:2:6?;j;o1;4?c>32c95o4?:%1;5?42m2d84=4ja:9j6<g=83.84<4=5d9m7=6=mk10e?76:18'7=7=:<o0b>6?:da8?l4>03:1(>6>:37f?k5?83oo76g=9683>!5?938>i6`<818fa>=n:0<1<7*<80811`=i;1:1ik54i3;7>5<#;1;1>8k4n2:3>c6<3`82?7>5$2:2>73b3g93<7h>;:k1=7<72-93=7<:e:l0<5<a:21b>4?50;&0<4<5=l1e?5>5f298m7?7290/?5?524g8j6>72o>07d<7f;29 6>62;?n7c=70;d6?>o50l0;6)=71;06a>h4090m:65f29f94?"408099h5a3929b2=<a;2h6=4+393960c<f:2;6k64;h0;f?6=,:2:6?;j;o1;4?`>32c9444?:%1;5?42m2d84=4ia:9j6=>=83.84<4=5d9m7=6=nk10e?68:18'7=7=:<o0b>6?:ga8?l4?>3:1(>6>:37f?k5?83lo76g=8483>!5?938>i6`<818ea>=n:1>1<7*<80811`=i;1:1jk54i3:0>5<#;1;1>8k4n2:3>46732c94?4?:%1;5?42m2d84=4>0098m7>6290/?5?524g8j6>728:976g=8183>!5?938>i6`<818246=<a;=n6=4+393960c<f:2;6<>;;:k13a<72-93=7<:e:l0<5<68<10e?9l:18'7=7=:<o0b>6?:025?>o5?k0;6)=71;06a>h4090:<:54i35b>5<#;1;1>8k4n2:3>46?32c9;44?:%1;5?42m2d84=4>0898m71?290/?5?524g8j6>728:j76g=7683>!5?938>i6`<81824g=<a;==6=4+393960c<f:2;6<>l;:k130<72-93=7<:e:l0<5<68m10e?9<:18'7=7=:<o0b>6?:02f?>o5?;0;6)=71;06a>h4090:<k54i352>5<#;1;1>8k4n2:3>47732c9;=4?:%1;5?42m2d84=4>1098m70a290/?5?524g8j6>728;976g=6d83>!5?938>i6`<818256=<a;<o6=4+393960c<f:2;6<?;;:k12f<72-93=7<:e:l0<5<69<10e?8m:18'7=7=:<o0b>6?:035?>o5>h0;6)=71;06a>h4090:=:54i34;>5<#;1;1>8k4n2:3>47?32c9::4?:%1;5?42m2d84=4>1898m701290/?5?524g8j6>728;j76g=6483>!5?938>i6`<81825g=<a;<?6=4+393960c<f:2;6<?l;:k126<72-93=7<:e:l0<5<69m10e?8=:18'7=7=:<o0b>6?:03f?>o5>80;6)=71;06a>h4090:=k54i343>5<#;1;1>8k4n2:3>44732c9994?:%1;5?42m2d84=4>2098m72?290/?5?524g8j6>7288976g=3e83>!5?938>i6`<818266=<a;996=4+393960c<f:2;6<<;;:k162<72-93=7<:e:l0<5<6:<10e??l:18'7=7=:<o0b>6?:005?>o5980;6)=71;06a>h4090:>:54i325>5<#;1;1>8k4n2:3>44?32c:jo4?:%1;5?42m2d84=4>2898m4`7290/?5?524g8j6>7288j76g>e483>!5?938>i6`<81826g=<a8n26=4+393960c<f:2;6<<l;:k2g`<72-93=7<:e:l0<5<6:m10e<m<:18'7=7=:<o0b>6?:00f?>o6j10;6)=71;06a>h4090:>k54i0cg>5<#;1;1>8k4n2:3>45732c:m?4?:%1;5?42m2d84=4>3098m4?0290/?5?524g8j6>7289976g>8b83>!5?938>i6`<818276=<a82:6=4+393960c<f:2;6<=;;:k233<72-93=7<:e:l0<5<6;<10e?ol:18'7=7=:<o0b>6?:015?>o5i90;6)=71;06a>h4090:?:54i3;6>5<#;1;1>8k4n2:3>45?32c94l4?:%1;5?42m2d84=4>3898m71a290/?5?524g8j6>7289j76g=7583>!5?938>i6`<81827g=<a;<26=4+393960c<f:2;6<=l;:k10<<72-93=7<:e:l0<5<6;m10e<jn:18'7=7=:<o0b>6?:01f?>o6>k0;6)=71;06a>h4090:?k54i9194?=n;0:1<75f3c194?=n;k81<75f3c694?=h;k?1<75`2`f94?=e;=l1<7?l:`811~Nc;81/89;5d8:8^37=9r;h6p*=ag802f=n;h21<7*<8080e2=i;1:1<65f3`494?"40808m:5a39295>=n;h?1<7*<8080e2=i;1:1>65f3`694?"40808m:5a39297>=n;h91<7*<8080e2=i;1:1865f3`094?"40808m:5a39291>=n;h;1<7*<8080e2=i;1:1:65f3`294?"40808m:5a39293>=n;0l1<7*<8080e2=i;1:1465f38g94?"40808m:5a3929=>=n;k;1<7*<8080e2=i;1:1m65f3c294?"40808m:5a3929f>=n;hl1<7*<8080e2=i;1:1o65f3`g94?"40808m:5a3929`>=n;hn1<7*<8080e2=i;1:1i65f3`a94?"40808m:5a3929b>=n;hh1<7*<8080e2=i;1:1==54i2cb>5<#;1;1?l94n2:3>47<3`9j57>5$2:2>6g03g93<7?=;:k0=a<72-93=7=n7:l0<5<6;21b4>4?::k0=5<722c::l4?::k0f6<722c8n?4?::k0f1<722e8n84?::m1ea<722ho:84?:083>5}#<=?1h>h4He40?Mb492e8;h4?::a`32=83;1<7>t$566>7gb3An=?6Fk309l53?=831vni=j:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"4180o9=5+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3tho?i4?:`83>5}#<=?1?4m4He40?Mb492P==7?t2e8~ 6?62m?;7)<l7;68m3`=831bmi4?::k5g?6=3f9397>5;n1;3?6=3`9h6=4+39397g=i;1:1<65f3`83>!5?939i7c=70;38?l5>290/?5?53c9m7=6=:21b?54?:%1;5?5e3g93<7=4;h14>5<#;1;1?o5a39290>=zjm9h6=4n:183!23=392o6Fk629K`67<R?;1=v<k:|&0=4<c=91/>n954:k5b?6=3`ko6=44i7a94?=h;1?1<75`39594?=n;j0;6)=71;1a?k5?83:07d=n:18'7=7=;k1e?5>51:9j7<<72-93=7=m;o1;4?4<3`936=4+39397g=i;1:1?65f3683>!5?939i7c=70;68?xdc;k0;6l4?:1y'013=;0i0Di8<;If05>\193;p>i4r$2;2>a373-8h;7:4i7d94?=nim0;66g9c;29?j5?=3:17b=77;29?l5d290/?5?53c9m7=6=821b?l4?:%1;5?5e3g93<7?4;h1:>5<#;1;1?o5a39296>=n;10;6)=71;1a?k5?83907d=8:18'7=7=;k1e?5>54:9~fa51290?6=4?{%671?51l2Bo:>5Gd238 6?62m?;7d8j:188mg6=831b?4<50;9l734=831vni=::187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e73?l0b2900eo>50;9j7<4=831d?;<50;9~fa53290?6=4?{%671?51l2Bo:>5Gd238 6?62m?;7d8j:188mg6=831b?4<50;9l734=831vni=<:187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e73?l0b2900eo>50;9j7<4=831d?;<50;9~w6g?2909wS=n8:?g7`<4k2wx?l850;0xZ6g134n8i7=n;|q0e0<72;qU?l;4=e1f>6?<uz9j87>52z\0e1=:l:o1?55rs2c0>5<5sW9j?63k3d803>{t;h81<7<t^2c1?8b4l39h7p}<a083>7}Y;h;01i=k:2c8yv5f83:1>vP<a19>`6b=;01v>7i:181[5>n27o?i4<8:p7<c=838pR>7j;<f0`?503ty8n<4?:3y]7g7<5m9h6>m4}r1a4?6=:rT8n=52d2a97d=z{:km6=4={_1bb>;c;j0856s|3`g94?4|V:kn70j<c;1;?xu4im0;6?uQ3`f89a5d2:=0q~=nc;296~X4ij16h>l53b9~w6ge2909wS=nb:?g7g<4i2wx?lo50;0xZ6gf34n8n7=6;|q0e<<72;qU?l74=e1a>6><uz92h7>52z\0=a=:l:h1?:5rs2`0>5<2sW9i?63k3d85b>;c;m0=j63k3b85b>;c;k0=j6s|3c094?3|V:h970j<e;4`?8b4l3<h70j<c;4`?8b4j3<h7p}<b583>7}Y;k>01i=j:`f8yvbb?3:1>v3k3d80<0=:l:<1?4<4}rfga?6=:r7o?h4<869>`6b=im1vik9:1818b4l393963k3480=7=z{mno6=4={<f0`?5??27o?n4nd:p``3=838p1i=l:2:6?8b4<392>6s|dea94?4|5m9h6>68;<f0f?gc3tyoi94?:3y>`6d=;1?01i=<:2;1?xu4j<0;6?uQ3c789a5e2:2<7p}=ae83>7}Y:hn01i=9:241?xucm80;6?u2d2492`=:l:?1?;<4}rff4?6=:r7o?849e:?g71<4>;1viji:1818b4<3<n70j<3;156>{t9?k1<7<t=e46>61b34n8?78j;|q036<72<q6h;:517;89a512k:01i=::c289a532k:01i=<:c28yxd4=?0;6<m59;06Mb492.?884ka09Y24<6s8i1q)<nf;15g>o4i10;6)=71;1b3>h4090;76g<a783>!5?939j;6`<8182?>o4i<0;6)=71;1b3>h4090976g<a583>!5?939j;6`<8180?>o4i:0;6)=71;1b3>h4090?76g<a383>!5?939j;6`<8186?>o4i80;6)=71;1b3>h4090=76g<a183>!5?939j;6`<8184?>o41o0;6)=71;1b3>h4090376g<9d83>!5?939j;6`<818:?>o4j80;6)=71;1b3>h4090j76g<b183>!5?939j;6`<818a?>o4io0;6)=71;1b3>h4090h76g<ad83>!5?939j;6`<818g?>o4im0;6)=71;1b3>h4090n76g<ab83>!5?939j;6`<818e?>o4ik0;6)=71;1b3>h4090:<65f3`c94?"40808m:5a392954=<a:k26=4+39397d1<f:2;6<<4;h1:`?6=,:2:6>o8;o1;4?7432c3?7>5;h1:4?6=3`;=m7>5;h1a7?6=3`9i>7>5;h1a0?6=3f9i97>5;n0b`?6=3kn=87>51;294~"3<<09mh5Gd718La563f;=57>5;|`g76<72=0;6=u+457973b<@m<87Ej<1:&0=4<c=81b:h4?::ka4?6=3`92>7>5;n156?6=3tho?h4?:`83>5}#<=?1?4m4He40?Mb492P==7?t2e8~ 6?62m?:7)<l7;68m3`=831bmi4?::k5g?6=3f9397>5;n1;3?6=3`9h6=4+39397g=i;1:1<65f3`83>!5?939i7c=70;38?l5>290/?5?53c9m7=6=:21b?54?:%1;5?5e3g93<7=4;h14>5<#;1;1?o5a39290>=zjm9o6=4n:183!23=392o6Fk629K`67<R?;1=v<k:|&0=4<c=81/>n954:k5b?6=3`ko6=44i7a94?=h;1?1<75`39594?=n;j0;6)=71;1a?k5?83:07d=n:18'7=7=;k1e?5>51:9j7<<72-93=7=m;o1;4?4<3`936=4+39397g=i;1:1?65f3683>!5?939i7c=70;68?xdc;j0;6l4?:1y'013=;0i0Di8<;If05>\193;p>i4r$2;2>a363-8h;7:4i7d94?=nim0;66g9c;29?j5?=3:17b=77;29?l5d290/?5?53c9m7=6=821b?l4?:%1;5?5e3g93<7?4;h1:>5<#;1;1?o5a39296>=n;10;6)=71;1a?k5?83907d=8:18'7=7=;k1e?5>54:9~fa5e290j6=4?{%671?5>k2Bo:>5Gd238^37=9r8o6p*<908g14=#:j=186g9f;29?lgc2900e;m50;9l7=3=831d?5950;9j7f<72-93=7=m;o1;4?6<3`9j6=4+39397g=i;1:1=65f3883>!5?939i7c=70;08?l5?290/?5?53c9m7=6=;21b?:4?:%1;5?5e3g93<7:4;|`g71<72=0;6=u+457973b<@m<87Ej<1:&0=4<c=81b:h4?::ka4?6=3`92>7>5;n156?6=3tho?;4?:583>5}#<=?1?;j4He40?Mb492.85<4k509j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`g70<72=0;6=u+457973b<@m<87Ej<1:&0=4<c=81b:h4?::ka4?6=3`92>7>5;n156?6=3ty8m54?:3y]7d><5m9n6>m4}r1b2?6=:rT8m;52d2g97d=z{:k>6=4={_1b1>;c;l0856s|3`694?4|V:k?70j<e;1;?xu4i:0;6?uQ3`189a5b2:=0q~=n2;296~X4i;16h>j53b9~w6g62909wS=n1:?g7a<4i2wx?l>50;0xZ6g734n8h7=6;|q0=c<72;qU?4h4=e1g>6><uz92i7>52z\0=`=:l:n1?:5rs2`2>5<5sW9i=63k3b80g>{t;k:1<7<t^2`3?8b4k39j7p}<ag83>7}Y;hl01i=l:2;8yv5fm3:1>vP<ad9>`6e=;11v>ok:181[5fl27o?n4<7:p7de=838pR>ol;<f0f?5d3ty8mo4?:3y]7dd<5m9i6>o4}r1be?6=:rT8ml52d2`97<=z{:k26=4={_1b=>;c;k0846s|38f94?4|V:3o70j<b;14?xu6>h0;6?uQ17c89a542?o0q~=m3;291~X4j:16h>k56g9>`6b=>o16h>m56g9>`6d=>o1v>l=:186[5e:27o?h49c:?g7a<1k27o?n49c:?g7g<1k2wx?o:50;0xZ6d334n8i7ok;|qg`c<72;q6h>=537089a532?o0q~jj7;296~;c;l084852d2497<4<uznoi7>52z?g7`<40>16h>j5ae9~wac12909w0j<d;1;1>;c;<085?5rsefg>5<5s4n8h7=77:?g7f<fl2wxhh;50;0x9a5d2:2>70j<4;1:6>{tlmi1<7<t=e1`>6>034n8n7ok;|qga1<72;q6h>=538089a5e2:2>7p}<b483>7}Y;k?01i=m:2:4?xucm90;6?u2d269734<5m9>6;k4}r0b`?6=:rT9mi52d249734<uznn=7>52z?g73<1m27o?84<639~w614290>w0j94;35=>;c;:0i<63k358a4>;c;?0i<63k348a4>{zj:?<6=4>c;;960}Ol:;0(9:::ec1?_0628q:o7s+2`d973e<a:k36=4+39397d1<f:2;6=54i2c5>5<#;1;1?l94n2:3>4=<a:k>6=4+39397d1<f:2;6?54i2c7>5<#;1;1?l94n2:3>6=<a:k86=4+39397d1<f:2;6954i2c1>5<#;1;1?l94n2:3>0=<a:k:6=4+39397d1<f:2;6;54i2c3>5<#;1;1?l94n2:3>2=<a:3m6=4+39397d1<f:2;6554i2;f>5<#;1;1?l94n2:3><=<a:h:6=4+39397d1<f:2;6l54i2`3>5<#;1;1?l94n2:3>g=<a:km6=4+39397d1<f:2;6n54i2cf>5<#;1;1?l94n2:3>a=<a:ko6=4+39397d1<f:2;6h54i2c`>5<#;1;1?l94n2:3>c=<a:ki6=4+39397d1<f:2;6<>4;h1be?6=,:2:6>o8;o1;4?7632c8m44?:%1;5?5f?2d84=4>2:9j7<b=83.84<4<a69m7=6=9:10e5=50;9j7<6=831b=;o50;9j7g5=831b?o<50;9j7g2=831d?o;50;9l6db=831ih;:50;394?6|,=>>6?oj;If57>Nc;81d=;750;9~fa54290?6=4?{%671?51l2Bo:>5Gd238 6?62m?27d8j:188mg6=831b?4<50;9l734=831vni=j:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"4180o945+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3tho?i4?:`83>5}#<=?1?4m4He40?Mb492P==7?t2e8~ 6?62m?27)<l7;68m3`=831bmi4?::k5g?6=3f9397>5;n1;3?6=3`9h6=4+39397g=i;1:1<65f3`83>!5?939i7c=70;38?l5>290/?5?53c9m7=6=:21b?54?:%1;5?5e3g93<7=4;h14>5<#;1;1?o5a39290>=zjm9h6=4n:183!23=392o6Fk629K`67<R?;1=v<k:|&0=4<c=01/>n954:k5b?6=3`ko6=44i7a94?=h;1?1<75`39594?=n;j0;6)=71;1a?k5?83:07d=n:18'7=7=;k1e?5>51:9j7<<72-93=7=m;o1;4?4<3`936=4+39397g=i;1:1?65f3683>!5?939i7c=70;68?xdc;k0;6l4?:1y'013=;0i0Di8<;If05>\193;p>i4r$2;2>a3>3-8h;7:4i7d94?=nim0;66g9c;29?j5?=3:17b=77;29?l5d290/?5?53c9m7=6=821b?l4?:%1;5?5e3g93<7?4;h1:>5<#;1;1?o5a39296>=n;10;6)=71;1a?k5?83907d=8:18'7=7=;k1e?5>54:9~fa53290?6=4?{%671?51l2Bo:>5Gd238 6?62m?27d8j:188mg6=831b?4<50;9l734=831vni=9:187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e7:?l0b2900eo>50;9j7<4=831d?;<50;9~fa52290?6=4?{%671?51l2Bo:>5Gd238 6?62m?27d8j:188mg6=831b?4<50;9l734=831v>o7:181[5f027o?h4<c:p7d0=838pR>o9;<f0a?5f3ty8m84?:3y]7d3<5m9n6>74}r1b0?6=:rT8m952d2g97==z{:k86=4={_1b7>;c;l08;6s|3`094?4|V:k970j<d;1`?xu4i80;6?uQ3`389a5c2:k0q~=n0;296~X4i916h>j5389~w6?a2909wS=6f:?g7a<402wx?4k50;0xZ6?b34n8h7=8;|q0f4<72;qU?o?4=e1`>6e<uz9i<7>52z\0f5=:l:i1?l5rs2ce>5<5sW9jj63k3b80=>{t;ho1<7<t^2cf?8b4k3937p}<ae83>7}Y;hn01i=l:258yv5fk3:1>vP<ab9>`6d=;j1v>om:181[5fj27o?o4<a:p7dg=838pR>on;<f0f?5>3ty8m44?:3y]7d?<5m9i6>64}r1:`?6=:rT85i52d2`972=z{8<j6=4={_35e>;c;:0=i6s|3c194?3|V:h870j<e;4e?8b4l3<m70j<c;4e?8b4j3<m7p}<b383>0}Y;k801i=j:7a89a5c2?i01i=l:7a89a5e2?i0q~=m4;296~X4j=16h>k5ae9~waba2909w0j<3;156>;c;=0=i6s|dd594?4|5m9n6>6:;<f02?5>:2wxhik50;0x9a5b2:2<70j<d;cg?xucm?0;6?u2d2f97=3<5m9>6>7=;|qg`a<72;q6h>j539589a5d2hn0q~jj5;296~;c;j084852d2697<4<uznoo7>52z?g7f<40>16h>l5ae9~wac32909w0j<3;1:6>;c;k08485rs2`6>5<5sW9i963k3c80<2=z{mo;6=4={<f00?51:27o?849e:p6db=838pR?ok;<f02?51:2wxhh?50;0x9a512?o01i=::241?xu4?:0;68u2d76953?<5m986o>4=e17>g6<5m9=6o>4=e16>g6<uth8954?:0a9=?42sAn8=6*;448ge6=]>80:w<m5}%0bb?51k2c8m54?:%1;5?5f?2d84=4?;:k0e3<72-93=7=n7:l0<5<632c8m84?:%1;5?5f?2d84=4=;:k0e1<72-93=7=n7:l0<5<432c8m>4?:%1;5?5f?2d84=4;;:k0e7<72-93=7=n7:l0<5<232c8m<4?:%1;5?5f?2d84=49;:k0e5<72-93=7=n7:l0<5<032c85k4?:%1;5?5f?2d84=47;:k0=`<72-93=7=n7:l0<5<>32c8n<4?:%1;5?5f?2d84=4n;:k0f5<72-93=7=n7:l0<5<e32c8mk4?:%1;5?5f?2d84=4l;:k0e`<72-93=7=n7:l0<5<c32c8mi4?:%1;5?5f?2d84=4j;:k0ef<72-93=7=n7:l0<5<a32c8mo4?:%1;5?5f?2d84=4>0:9j7dg=83.84<4<a69m7=6=9810e>o6:18'7=7=;h=0b>6?:008?l5>l3:1(>6>:2c4?k5?83;876g73;29?l5>83:17d?9a;29?l5e;3:17d=m2;29?l5e<3:17b=m5;29?j4fl3:17oj94;295?6=8r.?884=ad9K`35<@m9:7b?99;29?xdc;:0;694?:1y'013=;?n0Di8<;If05>"4180o9l5f6d83>>oe83:17d=62;29?j51:3:17plk3d83>d<729q/89;538a8La043An8=6T91;3x6a<z,:3:6i;n;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vni=k:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"4180o9l5+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3tho?n4?:`83>5}#<=?1?4m4He40?Mb492P==7?t2e8~ 6?62m?j7)<l7;68m3`=831bmi4?::k5g?6=3f9397>5;n1;3?6=3`9h6=4+39397g=i;1:1<65f3`83>!5?939i7c=70;38?l5>290/?5?53c9m7=6=:21b?54?:%1;5?5e3g93<7=4;h14>5<#;1;1?o5a39290>=zjm9i6=4n:183!23=392o6Fk629K`67<R?;1=v<k:|&0=4<c=h1/>n954:k5b?6=3`ko6=44i7a94?=h;1?1<75`39594?=n;j0;6)=71;1a?k5?83:07d=n:18'7=7=;k1e?5>51:9j7<<72-93=7=m;o1;4?4<3`936=4+39397g=i;1:1?65f3683>!5?939i7c=70;68?xdc;=0;694?:1y'013=;?n0Di8<;If05>"4180o9l5f6d83>>oe83:17d=62;29?j51:3:17plk3783>1<729q/89;537f8La043An8=6*<908g1d=n>l0;66gm0;29?l5>:3:17b=92;29?xdc;<0;694?:1y'013=;?n0Di8<;If05>"4180o9l5f6d83>>oe83:17d=62;29?j51:3:17p}<a983>7}Y;h201i=j:2a8yv5f>3:1>vP<a79>`6c=;h1v>o::181[5f=27o?h4<9:p7d2=838pR>o;;<f0a?5?3ty8m>4?:3y]7d5<5m9n6>94}r1b6?6=:rT8m?52d2f97f=z{:k:6=4={_1b5>;c;m08m6s|3`294?4|V:k;70j<d;1:?xu41o0;6?uQ38d89a5c2:20q~=6e;296~X41l16h>j5369~w6d62909wS=m1:?g7f<4k2wx?o>50;0xZ6d734n8o7=n;|q0ec<72;qU?lh4=e1`>6?<uz9ji7>52z\0e`=:l:i1?55rs2cg>5<5sW9jh63k3b803>{t;hi1<7<t^2c`?8b4j39h7p}<ac83>7}Y;hh01i=m:2c8yv5fi3:1>vP<a`9>`6d=;01v>o6:181[5f127o?o4<8:p7<b=838pR>7k;<f0f?503ty::l4?:3y]53g<5m986;k4}r1a7?6==rT8n>52d2g92c=:l:n1:k52d2a92c=:l:h1:k5rs2`1>5<2sW9i>63k3d85g>;c;m0=o63k3b85g>;c;k0=o6s|3c694?4|V:h?70j<e;cg?xuclo0;6?u2d219734<5m9?6;k4}rff3?6=:r7o?h4<849>`60=;080q~jke;296~;c;l084:52d2f9ea=z{mo=6=4={<f0`?5?=27o?84<939~wabc2909w0j<d;1;3>;c;j0jh6s|dd794?4|5m9h6>6:;<f00?5>:2wxhim50;0x9a5d2:2<70j<b;cg?xucm=0;6?u2d2197<4<5m9i6>6:;|q0f0<72;qU?o;4=e1a>6>03tyoi=4?:3y>`62=;?801i=::7g8yv4fl3:1>vP=ae9>`60=;?80q~jj1;296~;c;?0=i63k348027=z{:=86=4:{<f50?71127o?>4m0:?g71<e827o?;4m0:?g70<e82wvn>;6:182g??=:<qCh>?4$566>ag33S<:6<u>c;'6d`=;?i0e>o7:18'7=7=;h=0b>6?:198m6g1290/?5?53`58j6>72810e>o::18'7=7=;h=0b>6?:398m6g3290/?5?53`58j6>72:10e>o<:18'7=7=;h=0b>6?:598m6g5290/?5?53`58j6>72<10e>o>:18'7=7=;h=0b>6?:798m6g7290/?5?53`58j6>72>10e>7i:18'7=7=;h=0b>6?:998m6?b290/?5?53`58j6>72010e>l>:18'7=7=;h=0b>6?:`98m6d7290/?5?53`58j6>72k10e>oi:18'7=7=;h=0b>6?:b98m6gb290/?5?53`58j6>72m10e>ok:18'7=7=;h=0b>6?:d98m6gd290/?5?53`58j6>72o10e>om:18'7=7=;h=0b>6?:028?l5fi3:1(>6>:2c4?k5?83;:76g<a883>!5?939j;6`<81826>=n;0n1<7*<8080e2=i;1:1=>54i9194?=n;0:1<75f17c94?=n;k91<75f3c094?=n;k>1<75`3c794?=h:hn1<75md7694?7=83:p(9:::3cf?Mb1;2Bo?<5`17;94?=zjm986=4;:183!23=39=h6Fk629K`67<,:3:6i;m;h4f>5<<ak:1<75f38094?=h;?81<75rbe1f>5<f290;w):;5;1:g>Nc>:1Ch>?4Z7395~4c2t.85<4k5c9'6f1=<2c=j7>5;hcg>5<<a?i1<75`39794?=h;1=1<75f3b83>!5?939i7c=70;28?l5f290/?5?53c9m7=6=921b?44?:%1;5?5e3g93<7<4;h1;>5<#;1;1?o5a39297>=n;>0;6)=71;1a?k5?83>07plk3e83>d<729q/89;538a8La043An8=6T91;3x6a<z,:3:6i;m;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vni=l:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"4180o9o5+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3tho?o4?:`83>5}#<=?1?4m4He40?Mb492P==7?t2e8~ 6?62m?i7)<l7;68m3`=831bmi4?::k5g?6=3f9397>5;n1;3?6=3`9h6=4+39397g=i;1:1<65f3`83>!5?939i7c=70;38?l5>290/?5?53c9m7=6=:21b?54?:%1;5?5e3g93<7=4;h14>5<#;1;1?o5a39290>=zjm9?6=4;:183!23=39=h6Fk629K`67<,:3:6i;m;h4f>5<<ak:1<75f38094?=h;?81<75rbe15>5<3290;w):;5;15`>Nc>:1Ch>?4$2;2>a3e3`<n6=44ic294?=n;081<75`37094?=zjm9>6=4;:183!23=39=h6Fk629K`67<,:3:6i;m;h4f>5<<ak:1<75f38094?=h;?81<75rs2c;>5<5sW9j463k3d80g>{t;h<1<7<t^2c5?8b4m39j7p}<a483>7}Y;h?01i=j:2;8yv5f<3:1>vP<a59>`6c=;11v>o<:181[5f;27o?h4<7:p7d4=838pR>o=;<f0`?5d3ty8m<4?:3y]7d7<5m9o6>o4}r1b4?6=:rT8m=52d2f97<=z{:3m6=4={_1:b>;c;m0846s|38g94?4|V:3n70j<d;14?xu4j80;6?uQ3c389a5d2:i0q~=m0;296~X4j916h>m53`9~w6ga2909wS=nf:?g7f<412wx?lk50;0xZ6gb34n8o7=7;|q0ea<72;qU?lj4=e1`>61<uz9jo7>52z\0ef=:l:h1?n5rs2ca>5<5sW9jn63k3c80e>{t;hk1<7<t^2cb?8b4j3927p}<a883>7}Y;h301i=m:2:8yv5>l3:1>vP<9e9>`6d=;>1v<8n:181[71i27o?>49e:p7g5=83?pR>l<;<f0a?0a34n8h78i;<f0g?0a34n8n78i;|q0f7<72<qU?o<4=e1f>3e<5m9o6;m4=e1`>3e<5m9i6;m4}r1a0?6=:rT8n952d2g9ea=z{mnm6=4={<f07?51:27o?949e:p``1=838p1i=j:2:6?8b4>392>6s|deg94?4|5m9n6>68;<f0`?gc3tyoi;4?:3y>`6b=;1?01i=::2;1?xuclm0;6?u2d2f97=1<5m9h6lj4}rff1?6=:r7o?n4<849>`62=;080q~jkc;296~;c;j084:52d2`9ea=z{mo?6=4={<f07?5>:27o?o4<849~w6d22909wS=m5:?g7g<40>1vik?:1818b4<39=>63k3485a>{t:hn1<7<t^3cg?8b4>39=>6s|dd394?4|5m9=6;k4=e16>6053ty8;>4?:4y>`32=9?301i=<:c289a532k:01i=9:c289a522k:0qpl<5`83>4e=138>wEj<1:&700<ci<1Q:<4>{0a9y!4fn39=o6g<a983>!5?939j;6`<8183?>o4i?0;6)=71;1b3>h4090:76g<a483>!5?939j;6`<8181?>o4i=0;6)=71;1b3>h4090876g<a283>!5?939j;6`<8187?>o4i;0;6)=71;1b3>h4090>76g<a083>!5?939j;6`<8185?>o4i90;6)=71;1b3>h4090<76g<9g83>!5?939j;6`<818;?>o41l0;6)=71;1b3>h4090276g<b083>!5?939j;6`<818b?>o4j90;6)=71;1b3>h4090i76g<ag83>!5?939j;6`<818`?>o4il0;6)=71;1b3>h4090o76g<ae83>!5?939j;6`<818f?>o4ij0;6)=71;1b3>h4090m76g<ac83>!5?939j;6`<81824>=n;hk1<7*<8080e2=i;1:1=<54i2c:>5<#;1;1?l94n2:3>44<3`92h7>5$2:2>6g03g93<7?<;:k;7?6=3`92<7>5;h35e?6=3`9i?7>5;h1a6?6=3`9i87>5;n1a1?6=3f8jh7>5;cf50?6=93:1<v*;4481e`=Ol?90Di=>;n35=?6=3tho?>4?:583>5}#<=?1?;j4He40?Mb492.85<4k5b9j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`g7`<72h0;6=u+45797<e<@m<87Ej<1:X55?7|:m0v(>7>:e7`?!4d?3>0e;h50;9jea<722c=o7>5;n1;1?6=3f93;7>5;h1`>5<#;1;1?o5a39294>=n;h0;6)=71;1a?k5?83;07d=6:18'7=7=;k1e?5>52:9j7=<72-93=7=m;o1;4?5<3`9<6=4+39397g=i;1:1865rbe1g>5<f290;w):;5;1:g>Nc>:1Ch>?4Z7395~4c2t.85<4k5b9'6f1=<2c=j7>5;hcg>5<<a?i1<75`39794?=h;1=1<75f3b83>!5?939i7c=70;28?l5f290/?5?53c9m7=6=921b?44?:%1;5?5e3g93<7<4;h1;>5<#;1;1?o5a39297>=n;>0;6)=71;1a?k5?83>07plk3b83>d<729q/89;538a8La043An8=6T91;3x6a<z,:3:6i;l;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vni=m:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"4180o9n5+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3tho?94?:583>5}#<=?1?;j4He40?Mb492.85<4k5b9j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`g73<72=0;6=u+457973b<@m<87Ej<1:&0=4<c=j1b:h4?::ka4?6=3`92>7>5;n156?6=3tho?84?:583>5}#<=?1?;j4He40?Mb492.85<4k5b9j2`<722ci<7>5;h1:6?6=3f9=>7>5;|q0e=<72;qU?l64=e1f>6e<uz9j:7>52z\0e3=:l:o1?l5rs2c6>5<5sW9j963k3d80=>{t;h>1<7<t^2c7?8b4m3937p}<a283>7}Y;h901i=j:258yv5f:3:1>vP<a39>`6b=;j1v>o>:181[5f927o?i4<a:p7d6=838pR>o?;<f0`?5>3ty85k4?:3y]7<`<5m9o6>64}r1:a?6=:rT85h52d2f972=z{:h:6=4={_1a5>;c;j08o6s|3c294?4|V:h;70j<c;1b?xu4io0;6?uQ3`d89a5d2:30q~=ne;296~X4il16h>m5399~w6gc2909wS=nd:?g7f<4?2wx?lm50;0xZ6gd34n8n7=l;|q0eg<72;qU?ll4=e1a>6g<uz9jm7>52z\0ed=:l:h1?45rs2c:>5<5sW9j563k3c80<>{t;0n1<7<t^2;g?8b4j39<7p}>6`83>7}Y9?k01i=<:7g8yv5e;3:19vP<b29>`6c=>o16h>j56g9>`6e=>o16h>l56g9~w6d5290>wS=m2:?g7`<1k27o?i49c:?g7f<1k27o?o49c:p7g2=838pR>l;;<f0a?gc3tyohk4?:3y>`65=;?801i=;:7g8yvbb?3:1>v3k3d80<0=:l:<1?4<4}rfga?6=:r7o?h4<869>`6b=im1vik9:1818b4l393963k3480=7=z{mno6=4={<f0`?5??27o?n4nd:p``3=838p1i=l:2:6?8b4<392>6s|dea94?4|5m9h6>68;<f0f?gc3tyoi94?:3y>`65=;0801i=m:2:6?xu4j<0;6?uQ3c789a5e2:2<7p}ke183>7}:l:>1?;<4=e16>3c<uz8jh7>52z\1ea=:l:<1?;<4}rff5?6=:r7o?;49e:?g70<4>;1v>9<:1868b1<3;=563k328a4>;c;=0i<63k378a4>;c;<0i<6srb27a>5<6k331>8uGd238 1222mk=7W8>:0y2g?{#:hl1?;m4i2c;>5<#;1;1?l94n2:3>5=<a:k=6=4+39397d1<f:2;6<54i2c6>5<#;1;1?l94n2:3>7=<a:k?6=4+39397d1<f:2;6>54i2c0>5<#;1;1?l94n2:3>1=<a:k96=4+39397d1<f:2;6854i2c2>5<#;1;1?l94n2:3>3=<a:k;6=4+39397d1<f:2;6:54i2;e>5<#;1;1?l94n2:3>==<a:3n6=4+39397d1<f:2;6454i2`2>5<#;1;1?l94n2:3>d=<a:h;6=4+39397d1<f:2;6o54i2ce>5<#;1;1?l94n2:3>f=<a:kn6=4+39397d1<f:2;6i54i2cg>5<#;1;1?l94n2:3>`=<a:kh6=4+39397d1<f:2;6k54i2ca>5<#;1;1?l94n2:3>46<3`9jm7>5$2:2>6g03g93<7?>;:k0e<<72-93=7=n7:l0<5<6:21b?4j50;&0<4<4i>1e?5>51298m=5=831b?4>50;9j53g=831b?o=50;9j7g4=831b?o:50;9l7g3=831d>lj50;9a`32=83;1<7>t$566>7gb3An=?6Fk309l53?=831vni=<:187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e7g?l0b2900eo>50;9j7<4=831d?;<50;9~fa5b290j6=4?{%671?5>k2Bo:>5Gd238^37=9r8o6p*<908g1a=#:j=186g9f;29?lgc2900e;m50;9l7=3=831d?5950;9j7f<72-93=7=m;o1;4?6<3`9j6=4+39397g=i;1:1=65f3883>!5?939i7c=70;08?l5?290/?5?53c9m7=6=;21b?:4?:%1;5?5e3g93<7:4;|`g7a<72h0;6=u+45797<e<@m<87Ej<1:X55?7|:m0v(>7>:e7g?!4d?3>0e;h50;9jea<722c=o7>5;n1;1?6=3f93;7>5;h1`>5<#;1;1?o5a39294>=n;h0;6)=71;1a?k5?83;07d=6:18'7=7=;k1e?5>52:9j7=<72-93=7=m;o1;4?5<3`9<6=4+39397g=i;1:1865rbe1`>5<f290;w):;5;1:g>Nc>:1Ch>?4Z7395~4c2t.85<4k5e9'6f1=<2c=j7>5;hcg>5<<a?i1<75`39794?=h;1=1<75f3b83>!5?939i7c=70;28?l5f290/?5?53c9m7=6=921b?44?:%1;5?5e3g93<7<4;h1;>5<#;1;1?o5a39297>=n;>0;6)=71;1a?k5?83>07plk3c83>d<729q/89;538a8La043An8=6T91;3x6a<z,:3:6i;k;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vni=;:187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e7g?l0b2900eo>50;9j7<4=831d?;<50;9~fa51290?6=4?{%671?51l2Bo:>5Gd238 6?62m?o7d8j:188mg6=831b?4<50;9l734=831vni=::187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e7g?l0b2900eo>50;9j7<4=831d?;<50;9~w6g?2909wS=n8:?g7`<4k2wx?l850;0xZ6g134n8i7=n;|q0e0<72;qU?l;4=e1f>6?<uz9j87>52z\0e1=:l:o1?55rs2c0>5<5sW9j?63k3d803>{t;h81<7<t^2c1?8b4l39h7p}<a083>7}Y;h;01i=k:2c8yv5f83:1>vP<a19>`6b=;01v>7i:181[5>n27o?i4<8:p7<c=838pR>7j;<f0`?503ty8n<4?:3y]7g7<5m9h6>m4}r1a4?6=:rT8n=52d2a97d=z{:km6=4={_1bb>;c;j0856s|3`g94?4|V:kn70j<c;1;?xu4im0;6?uQ3`f89a5d2:=0q~=nc;296~X4ij16h>l53b9~w6ge2909wS=nb:?g7g<4i2wx?lo50;0xZ6gf34n8n7=6;|q0e<<72;qU?l74=e1a>6><uz92h7>52z\0=a=:l:h1?:5rs04b>5<5sW;=m63k3285a>{t;k91<7;t^2`0?8b4m3<m70j<d;4e?8b4k3<m70j<b;4e?xu4j;0;68uQ3c089a5b2?i01i=k:7a89a5d2?i01i=m:7a8yv5e<3:1>vP<b59>`6c=im1viji:1818b4;39=>63k3585a>{tll=1<7<t=e1f>6>234n8:7=62:p`ac=838p1i=j:2:4?8b4l3ko7p}ke783>7}:l:n1?5;4=e16>6?53tyohi4?:3y>`6b=;1=01i=l:`f8yvbb=3:1>v3k3b80<0=:l:>1?4<4}rfgg?6=:r7o?n4<869>`6d=im1vik;:1818b4;392>63k3c80<0=z{:h>6=4={_1a1>;c;k084:5rseg3>5<5s4n887=92:?g70<1m2wx>lj50;0xZ7gc34n8:7=92:p``7=838p1i=9:7g89a522:<97p}<7283>0}:l?>1=;74=e10>g6<5m9?6o>4=e15>g6<5m9>6o>4}|`01f<728i157<:{If05>"3<<0om:5U60824e=u-8jj7=9c:k0e=<72-93=7=n7:l0<5<732c8m;4?:%1;5?5f?2d84=4>;:k0e0<72-93=7=n7:l0<5<532c8m94?:%1;5?5f?2d84=4<;:k0e6<72-93=7=n7:l0<5<332c8m?4?:%1;5?5f?2d84=4:;:k0e4<72-93=7=n7:l0<5<132c8m=4?:%1;5?5f?2d84=48;:k0=c<72-93=7=n7:l0<5<?32c85h4?:%1;5?5f?2d84=46;:k0f4<72-93=7=n7:l0<5<f32c8n=4?:%1;5?5f?2d84=4m;:k0ec<72-93=7=n7:l0<5<d32c8mh4?:%1;5?5f?2d84=4k;:k0ea<72-93=7=n7:l0<5<b32c8mn4?:%1;5?5f?2d84=4i;:k0eg<72-93=7=n7:l0<5<6821b?lo50;&0<4<4i>1e?5>51098m6g>290/?5?53`58j6>728807d=6d;29 6>62:k<7c=70;30?>o?;3:17d=60;29?l71i3:17d=m3;29?l5e:3:17d=m4;29?j5e=3:17b<nd;29?gb1<3:1=7>50z&700<5il1Ch;=4He12?j7113:17plk3283>1<729q/89;537f8La043An8=6*<908g1`=n>l0;66gm0;29?l5>:3:17b=92;29?xdc;l0;6l4?:1y'013=;0i0Di8<;If05>\193;p>i4r$2;2>a3b3-8h;7:4i7d94?=nim0;66g9c;29?j5?=3:17b=77;29?l5d290/?5?53c9m7=6=821b?l4?:%1;5?5e3g93<7?4;h1:>5<#;1;1?o5a39296>=n;10;6)=71;1a?k5?83907d=8:18'7=7=;k1e?5>54:9~fa5c290j6=4?{%671?5>k2Bo:>5Gd238^37=9r8o6p*<908g1`=#:j=186g9f;29?lgc2900e;m50;9l7=3=831d?5950;9j7f<72-93=7=m;o1;4?6<3`9j6=4+39397g=i;1:1=65f3883>!5?939i7c=70;08?l5?290/?5?53c9m7=6=;21b?:4?:%1;5?5e3g93<7:4;|`g7f<72h0;6=u+45797<e<@m<87Ej<1:X55?7|:m0v(>7>:e7f?!4d?3>0e;h50;9jea<722c=o7>5;n1;1?6=3f93;7>5;h1`>5<#;1;1?o5a39294>=n;h0;6)=71;1a?k5?83;07d=6:18'7=7=;k1e?5>52:9j7=<72-93=7=m;o1;4?5<3`9<6=4+39397g=i;1:1865rbe1a>5<f290;w):;5;1:g>Nc>:1Ch>?4Z7395~4c2t.85<4k5d9'6f1=<2c=j7>5;hcg>5<<a?i1<75`39794?=h;1=1<75f3b83>!5?939i7c=70;28?l5f290/?5?53c9m7=6=921b?44?:%1;5?5e3g93<7<4;h1;>5<#;1;1?o5a39297>=n;>0;6)=71;1a?k5?83>07plk3583>1<729q/89;537f8La043An8=6*<908g1`=n>l0;66gm0;29?l5>:3:17b=92;29?xdc;?0;694?:1y'013=;?n0Di8<;If05>"4180o9h5f6d83>>oe83:17d=62;29?j51:3:17plk3483>1<729q/89;537f8La043An8=6*<908g1`=n>l0;66gm0;29?l5>:3:17b=92;29?xu4i10;6?uQ3`:89a5b2:i0q~=n6;296~X4i?16h>k53`9~w6g22909wS=n5:?g7`<412wx?l:50;0xZ6g334n8i7=7;|q0e6<72;qU?l=4=e1f>61<uz9j>7>52z\0e7=:l:n1?n5rs2c2>5<5sW9j=63k3e80e>{t;h:1<7<t^2c3?8b4l3927p}<9g83>7}Y;0l01i=k:2:8yv5>m3:1>vP<9d9>`6b=;>1v>l>:181[5e927o?n4<c:p7g6=838pR>l?;<f0g?5f3ty8mk4?:3y]7d`<5m9h6>74}r1ba?6=:rT8mh52d2a97==z{:ko6=4={_1b`>;c;j08;6s|3`a94?4|V:kh70j<b;1`?xu4ik0;6?uQ3``89a5e2:k0q~=na;296~X4ih16h>l5389~w6g>2909wS=n9:?g7g<402wx?4j50;0xZ6?c34n8n7=8;|q22d<72;qU=;o4=e10>3c<uz9i?7>55z\0f6=:l:o1:k52d2f92c=:l:i1:k52d2`92c=z{:h96=4:{_1a6>;c;l0=o63k3e85g>;c;j0=o63k3c85g>{t;k>1<7<t^2`7?8b4m3ko7p}kdg83>7}:l:91?;<4=e17>3c<uznn;7>52z?g7`<40<16h>853808yvbcm3:1>v3k3d80<2=:l:n1mi5rseg5>5<5s4n8h7=75:?g70<41;1vijk:1818b4l393;63k3b8b`>{tll?1<7<t=e1`>6>234n887=62:p`ae=838p1i=l:2:4?8b4j3ko7p}ke583>7}:l:91?4<4=e1a>6>23ty8n84?:3y]7g3<5m9i6>68;|qga5<72;q6h>:537089a522?o0q~<nd;296~X5im16h>853708yvbb93:1>v3k3785a>;c;<08:?5rs250>5<2s4n=87?99:?g76<e827o?94m0:?g73<e827o?84m0:~f63c290:o77524yK`67<,=>>6io7;[42>4}6k3w/>lh537a8m6g?290/?5?53`58j6>72910e>o9:18'7=7=;h=0b>6?:098m6g2290/?5?53`58j6>72;10e>o;:18'7=7=;h=0b>6?:298m6g4290/?5?53`58j6>72=10e>o=:18'7=7=;h=0b>6?:498m6g6290/?5?53`58j6>72?10e>o?:18'7=7=;h=0b>6?:698m6?a290/?5?53`58j6>72110e>7j:18'7=7=;h=0b>6?:898m6d6290/?5?53`58j6>72h10e>l?:18'7=7=;h=0b>6?:c98m6ga290/?5?53`58j6>72j10e>oj:18'7=7=;h=0b>6?:e98m6gc290/?5?53`58j6>72l10e>ol:18'7=7=;h=0b>6?:g98m6ge290/?5?53`58j6>728:07d=na;29 6>62:k<7c=70;32?>o4i00;6)=71;1b3>h4090:>65f38f94?"40808m:5a392956=<a191<75f38294?=n9?k1<75f3c194?=n;k81<75f3c694?=h;k?1<75`2`f94?=el?>1<7?50;2x 1222;kn7Ej93:Jg74=h9?31<75rbe10>5<3290;w):;5;15`>Nc>:1Ch>?4$2;2>a3a3`<n6=44ic294?=n;081<75`37094?=zjm9n6=4n:183!23=392o6Fk629K`67<R?;1=v<k:|&0=4<c=o1/>n954:k5b?6=3`ko6=44i7a94?=h;1?1<75`39594?=n;j0;6)=71;1a?k5?83:07d=n:18'7=7=;k1e?5>51:9j7<<72-93=7=m;o1;4?4<3`936=4+39397g=i;1:1?65f3683>!5?939i7c=70;68?xdc;m0;6l4?:1y'013=;0i0Di8<;If05>\193;p>i4r$2;2>a3a3-8h;7:4i7d94?=nim0;66g9c;29?j5?=3:17b=77;29?l5d290/?5?53c9m7=6=821b?l4?:%1;5?5e3g93<7?4;h1:>5<#;1;1?o5a39296>=n;10;6)=71;1a?k5?83907d=8:18'7=7=;k1e?5>54:9~fa5d290j6=4?{%671?5>k2Bo:>5Gd238^37=9r8o6p*<908g1c=#:j=186g9f;29?lgc2900e;m50;9l7=3=831d?5950;9j7f<72-93=7=m;o1;4?6<3`9j6=4+39397g=i;1:1=65f3883>!5?939i7c=70;08?l5?290/?5?53c9m7=6=;21b?:4?:%1;5?5e3g93<7:4;|`g7g<72h0;6=u+45797<e<@m<87Ej<1:X55?7|:m0v(>7>:e7e?!4d?3>0e;h50;9jea<722c=o7>5;n1;1?6=3f93;7>5;h1`>5<#;1;1?o5a39294>=n;h0;6)=71;1a?k5?83;07d=6:18'7=7=;k1e?5>52:9j7=<72-93=7=m;o1;4?5<3`9<6=4+39397g=i;1:1865rbe17>5<3290;w):;5;15`>Nc>:1Ch>?4$2;2>a3a3`<n6=44ic294?=n;081<75`37094?=zjm9=6=4;:183!23=39=h6Fk629K`67<,:3:6i;i;h4f>5<<ak:1<75f38094?=h;?81<75rbe16>5<3290;w):;5;15`>Nc>:1Ch>?4$2;2>a3a3`<n6=44ic294?=n;081<75`37094?=z{:k36=4={_1b<>;c;l08o6s|3`494?4|V:k=70j<e;1b?xu4i<0;6?uQ3`789a5b2:30q~=n4;296~X4i=16h>k5399~w6g42909wS=n3:?g7`<4?2wx?l<50;0xZ6g534n8h7=l;|q0e4<72;qU?l?4=e1g>6g<uz9j<7>52z\0e5=:l:n1?45rs2;e>5<5sW92j63k3e80<>{t;0o1<7<t^2;f?8b4l39<7p}<b083>7}Y;k;01i=l:2a8yv5e83:1>vP<b19>`6e=;h1v>oi:181[5fn27o?n4<9:p7dc=838pR>oj;<f0g?5?3ty8mi4?:3y]7db<5m9h6>94}r1bg?6=:rT8mn52d2`97f=z{:ki6=4={_1bf>;c;k08m6s|3`c94?4|V:kj70j<b;1:?xu4i00;6?uQ3`;89a5e2:20q~=6d;296~X41m16h>l5369~w40f2909wS?9a:?g76<1m2wx?o=50;7xZ6d434n8i78i;<f0`?0a34n8o78i;<f0f?0a3ty8n?4?:4y]7g4<5m9n6;m4=e1g>3e<5m9h6;m4=e1a>3e<uz9i87>52z\0f1=:l:o1mi5rsefe>5<5s4n8?7=92:?g71<1m2wxhh950;0x9a5b2:2>70j<6;1:6>{tlmo1<7<t=e1f>6>034n8h7ok;|qga3<72;q6h>j539789a522:397p}kde83>7}:l:n1?594=e1`>db<uznn97>52z?g7f<40<16h>:53808yvbck3:1>v3k3b80<2=:l:h1mi5rseg7>5<5s4n8?7=62:?g7g<40<1v>l::181[5e=27o?o4<869~wac72909w0j<4;156>;c;<0=i6s|2`f94?4|V;ko70j<6;156>{tll;1<7<t=e15>3c<5m9>6>8=;|q036<72<q6h;:517;89a542k:01i=;:c289a512k:01i=::c28yxd4=l0;6<m59;06Mb492.?884k989Y24<6s8i1q)<nf;15g>o4i10;6)=71;1b3>h4090;76g<a783>!5?939j;6`<8182?>o4i<0;6)=71;1b3>h4090976g<a583>!5?939j;6`<8180?>o4i:0;6)=71;1b3>h4090?76g<a383>!5?939j;6`<8186?>o4i80;6)=71;1b3>h4090=76g<a183>!5?939j;6`<8184?>o41o0;6)=71;1b3>h4090376g<9d83>!5?939j;6`<818:?>o4j80;6)=71;1b3>h4090j76g<b183>!5?939j;6`<818a?>o4io0;6)=71;1b3>h4090h76g<ad83>!5?939j;6`<818g?>o4im0;6)=71;1b3>h4090n76g<ab83>!5?939j;6`<818e?>o4ik0;6)=71;1b3>h4090:<65f3`c94?"40808m:5a392954=<a:k26=4+39397d1<f:2;6<<4;h1:`?6=,:2:6>o8;o1;4?7432c3?7>5;h1:4?6=3`;=m7>5;h1a7?6=3`9i>7>5;h1a0?6=3f9i97>5;n0b`?6=3kn=87>51;294~"3<<09mh5Gd718La563f;=57>5;|`g76<72=0;6=u+457973b<@m<87Ej<1:&0=4<c>91b:h4?::ka4?6=3`92>7>5;n156?6=3tho?h4?:`83>5}#<=?1?4m4He40?Mb492P==7?t2e8~ 6?62m<;7)<l7;68m3`=831bmi4?::k5g?6=3f9397>5;n1;3?6=3`9h6=4+39397g=i;1:1<65f3`83>!5?939i7c=70;38?l5>290/?5?53c9m7=6=:21b?54?:%1;5?5e3g93<7=4;h14>5<#;1;1?o5a39290>=zjm9o6=4n:183!23=392o6Fk629K`67<R?;1=v<k:|&0=4<c>91/>n954:k5b?6=3`ko6=44i7a94?=h;1?1<75`39594?=n;j0;6)=71;1a?k5?83:07d=n:18'7=7=;k1e?5>51:9j7<<72-93=7=m;o1;4?4<3`936=4+39397g=i;1:1?65f3683>!5?939i7c=70;68?xdc;j0;6l4?:1y'013=;0i0Di8<;If05>\193;p>i4r$2;2>a073-8h;7:4i7d94?=nim0;66g9c;29?j5?=3:17b=77;29?l5d290/?5?53c9m7=6=821b?l4?:%1;5?5e3g93<7?4;h1:>5<#;1;1?o5a39296>=n;10;6)=71;1a?k5?83907d=8:18'7=7=;k1e?5>54:9~fa5e290j6=4?{%671?5>k2Bo:>5Gd238^37=9r8o6p*<908g25=#:j=186g9f;29?lgc2900e;m50;9l7=3=831d?5950;9j7f<72-93=7=m;o1;4?6<3`9j6=4+39397g=i;1:1=65f3883>!5?939i7c=70;08?l5?290/?5?53c9m7=6=;21b?:4?:%1;5?5e3g93<7:4;|`g71<72=0;6=u+457973b<@m<87Ej<1:&0=4<c>91b:h4?::ka4?6=3`92>7>5;n156?6=3tho?;4?:583>5}#<=?1?;j4He40?Mb492.85<4k619j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`g70<72=0;6=u+457973b<@m<87Ej<1:&0=4<c>91b:h4?::ka4?6=3`92>7>5;n156?6=3ty8m54?:3y]7d><5m9n6>m4}r1b2?6=:rT8m;52d2g97d=z{:k>6=4={_1b1>;c;l0856s|3`694?4|V:k?70j<e;1;?xu4i:0;6?uQ3`189a5b2:=0q~=n2;296~X4i;16h>j53b9~w6g62909wS=n1:?g7a<4i2wx?l>50;0xZ6g734n8h7=6;|q0=c<72;qU?4h4=e1g>6><uz92i7>52z\0=`=:l:n1?:5rs2`2>5<5sW9i=63k3b80g>{t;k:1<7<t^2`3?8b4k39j7p}<ag83>7}Y;hl01i=l:2;8yv5fm3:1>vP<ad9>`6e=;11v>ok:181[5fl27o?n4<7:p7de=838pR>ol;<f0f?5d3ty8mo4?:3y]7dd<5m9i6>o4}r1be?6=:rT8ml52d2`97<=z{:k26=4={_1b=>;c;k0846s|38f94?4|V:3o70j<b;14?xu6>h0;6?uQ17c89a542?o0q~=m3;291~X4j:16h>k56g9>`6b=>o16h>m56g9>`6d=>o1v>l=:186[5e:27o?h49c:?g7a<1k27o?n49c:?g7g<1k2wx?o:50;0xZ6d334n8i7ok;|qg`c<72;q6h>=537089a532?o0q~jj7;296~;c;l084852d2497<4<uznoi7>52z?g7`<40>16h>j5ae9~wac12909w0j<d;1;1>;c;<085?5rsefg>5<5s4n8h7=77:?g7f<fl2wxhh;50;0x9a5d2:2>70j<4;1:6>{tlmi1<7<t=e1`>6>034n8n7ok;|qga1<72;q6h>=538089a5e2:2>7p}<b483>7}Y;k?01i=m:2:4?xucm90;6?u2d269734<5m9>6;k4}r0b`?6=:rT9mi52d249734<uznn=7>52z?g73<1m27o?84<639~w614290>w0j94;35=>;c;:0i<63k358a4>;c;?0i<63k348a4>{zj:?;6=4>c;;960}Ol:;0(9:::e;b?_0628q:o7s+2`d973e<a:k36=4+39397d1<f:2;6=54i2c5>5<#;1;1?l94n2:3>4=<a:k>6=4+39397d1<f:2;6?54i2c7>5<#;1;1?l94n2:3>6=<a:k86=4+39397d1<f:2;6954i2c1>5<#;1;1?l94n2:3>0=<a:k:6=4+39397d1<f:2;6;54i2c3>5<#;1;1?l94n2:3>2=<a:3m6=4+39397d1<f:2;6554i2;f>5<#;1;1?l94n2:3><=<a:h:6=4+39397d1<f:2;6l54i2`3>5<#;1;1?l94n2:3>g=<a:km6=4+39397d1<f:2;6n54i2cf>5<#;1;1?l94n2:3>a=<a:ko6=4+39397d1<f:2;6h54i2c`>5<#;1;1?l94n2:3>c=<a:ki6=4+39397d1<f:2;6<>4;h1be?6=,:2:6>o8;o1;4?7632c8m44?:%1;5?5f?2d84=4>2:9j7<b=83.84<4<a69m7=6=9:10e5=50;9j7<6=831b=;o50;9j7g5=831b?o<50;9j7g2=831d?o;50;9l6db=831ih;:50;394?6|,=>>6?oj;If57>Nc;81d=;750;9~fa54290?6=4?{%671?51l2Bo:>5Gd238 6?62m?97d8j:188mg6=831b?4<50;9l734=831vni=j:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"4180o9?5+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3tho?i4?:`83>5}#<=?1?4m4He40?Mb492P==7?t2e8~ 6?62m?97)<l7;68m3`=831bmi4?::k5g?6=3f9397>5;n1;3?6=3`9h6=4+39397g=i;1:1<65f3`83>!5?939i7c=70;38?l5>290/?5?53c9m7=6=:21b?54?:%1;5?5e3g93<7=4;h14>5<#;1;1?o5a39290>=zjm9h6=4n:183!23=392o6Fk629K`67<R?;1=v<k:|&0=4<c=;1/>n954:k5b?6=3`ko6=44i7a94?=h;1?1<75`39594?=n;j0;6)=71;1a?k5?83:07d=n:18'7=7=;k1e?5>51:9j7<<72-93=7=m;o1;4?4<3`936=4+39397g=i;1:1?65f3683>!5?939i7c=70;68?xdc;k0;6l4?:1y'013=;0i0Di8<;If05>\193;p>i4r$2;2>a353-8h;7:4i7d94?=nim0;66g9c;29?j5?=3:17b=77;29?l5d290/?5?53c9m7=6=821b?l4?:%1;5?5e3g93<7?4;h1:>5<#;1;1?o5a39296>=n;10;6)=71;1a?k5?83907d=8:18'7=7=;k1e?5>54:9~fa53290?6=4?{%671?51l2Bo:>5Gd238 6?62m?97d8j:188mg6=831b?4<50;9l734=831vni=9:187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e71?l0b2900eo>50;9j7<4=831d?;<50;9~fa52290?6=4?{%671?51l2Bo:>5Gd238 6?62m?97d8j:188mg6=831b?4<50;9l734=831v>o7:181[5f027o?h4<c:p7d0=838pR>o9;<f0a?5f3ty8m84?:3y]7d3<5m9n6>74}r1b0?6=:rT8m952d2g97==z{:k86=4={_1b7>;c;l08;6s|3`094?4|V:k970j<d;1`?xu4i80;6?uQ3`389a5c2:k0q~=n0;296~X4i916h>j5389~w6?a2909wS=6f:?g7a<402wx?4k50;0xZ6?b34n8h7=8;|q0f4<72;qU?o?4=e1`>6e<uz9i<7>52z\0f5=:l:i1?l5rs2ce>5<5sW9jj63k3b80=>{t;ho1<7<t^2cf?8b4k3937p}<ae83>7}Y;hn01i=l:258yv5fk3:1>vP<ab9>`6d=;j1v>om:181[5fj27o?o4<a:p7dg=838pR>on;<f0f?5>3ty8m44?:3y]7d?<5m9i6>64}r1:`?6=:rT85i52d2`972=z{8<j6=4={_35e>;c;:0=i6s|3c194?3|V:h870j<e;4e?8b4l3<m70j<c;4e?8b4j3<m7p}<b383>0}Y;k801i=j:7a89a5c2?i01i=l:7a89a5e2?i0q~=m4;296~X4j=16h>k5ae9~waba2909w0j<3;156>;c;=0=i6s|dd594?4|5m9n6>6:;<f02?5>:2wxhik50;0x9a5b2:2<70j<d;cg?xucm?0;6?u2d2f97=3<5m9>6>7=;|qg`a<72;q6h>j539589a5d2hn0q~jj5;296~;c;j084852d2697<4<uznoo7>52z?g7f<40>16h>l5ae9~wac32909w0j<3;1:6>;c;k08485rs2`6>5<5sW9i963k3c80<2=z{mo;6=4={<f00?51:27o?849e:p6db=838pR?ok;<f02?51:2wxhh?50;0x9a512?o01i=::241?xu4?:0;68u2d76953?<5m986o>4=e17>g6<5m9=6o>4=e16>g6<uth89<4?:0a9=?42sAn8=6*;448g=g=]>80:w<m5}%0bb?51k2c8m54?:%1;5?5f?2d84=4?;:k0e3<72-93=7=n7:l0<5<632c8m84?:%1;5?5f?2d84=4=;:k0e1<72-93=7=n7:l0<5<432c8m>4?:%1;5?5f?2d84=4;;:k0e7<72-93=7=n7:l0<5<232c8m<4?:%1;5?5f?2d84=49;:k0e5<72-93=7=n7:l0<5<032c85k4?:%1;5?5f?2d84=47;:k0=`<72-93=7=n7:l0<5<>32c8n<4?:%1;5?5f?2d84=4n;:k0f5<72-93=7=n7:l0<5<e32c8mk4?:%1;5?5f?2d84=4l;:k0e`<72-93=7=n7:l0<5<c32c8mi4?:%1;5?5f?2d84=4j;:k0ef<72-93=7=n7:l0<5<a32c8mo4?:%1;5?5f?2d84=4>0:9j7dg=83.84<4<a69m7=6=9810e>o6:18'7=7=;h=0b>6?:008?l5>l3:1(>6>:2c4?k5?83;876g73;29?l5>83:17d?9a;29?l5e;3:17d=m2;29?l5e<3:17b=m5;29?j4fl3:17oj94;295?6=8r.?884=ad9K`35<@m9:7b?99;29?xdc;:0;694?:1y'013=;?n0Di8<;If05>"4180o9>5f6d83>>oe83:17d=62;29?j51:3:17plk3d83>d<729q/89;538a8La043An8=6T91;3x6a<z,:3:6i;<;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vni=k:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"4180o9>5+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3tho?n4?:`83>5}#<=?1?4m4He40?Mb492P==7?t2e8~ 6?62m?87)<l7;68m3`=831bmi4?::k5g?6=3f9397>5;n1;3?6=3`9h6=4+39397g=i;1:1<65f3`83>!5?939i7c=70;38?l5>290/?5?53c9m7=6=:21b?54?:%1;5?5e3g93<7=4;h14>5<#;1;1?o5a39290>=zjm9i6=4n:183!23=392o6Fk629K`67<R?;1=v<k:|&0=4<c=:1/>n954:k5b?6=3`ko6=44i7a94?=h;1?1<75`39594?=n;j0;6)=71;1a?k5?83:07d=n:18'7=7=;k1e?5>51:9j7<<72-93=7=m;o1;4?4<3`936=4+39397g=i;1:1?65f3683>!5?939i7c=70;68?xdc;=0;694?:1y'013=;?n0Di8<;If05>"4180o9>5f6d83>>oe83:17d=62;29?j51:3:17plk3783>1<729q/89;537f8La043An8=6*<908g16=n>l0;66gm0;29?l5>:3:17b=92;29?xdc;<0;694?:1y'013=;?n0Di8<;If05>"4180o9>5f6d83>>oe83:17d=62;29?j51:3:17p}<a983>7}Y;h201i=j:2a8yv5f>3:1>vP<a79>`6c=;h1v>o::181[5f=27o?h4<9:p7d2=838pR>o;;<f0a?5?3ty8m>4?:3y]7d5<5m9n6>94}r1b6?6=:rT8m?52d2f97f=z{:k:6=4={_1b5>;c;m08m6s|3`294?4|V:k;70j<d;1:?xu41o0;6?uQ38d89a5c2:20q~=6e;296~X41l16h>j5369~w6d62909wS=m1:?g7f<4k2wx?o>50;0xZ6d734n8o7=n;|q0ec<72;qU?lh4=e1`>6?<uz9ji7>52z\0e`=:l:i1?55rs2cg>5<5sW9jh63k3b803>{t;hi1<7<t^2c`?8b4j39h7p}<ac83>7}Y;hh01i=m:2c8yv5fi3:1>vP<a`9>`6d=;01v>o6:181[5f127o?o4<8:p7<b=838pR>7k;<f0f?503ty::l4?:3y]53g<5m986;k4}r1a7?6==rT8n>52d2g92c=:l:n1:k52d2a92c=:l:h1:k5rs2`1>5<2sW9i>63k3d85g>;c;m0=o63k3b85g>;c;k0=o6s|3c694?4|V:h?70j<e;cg?xuclo0;6?u2d219734<5m9?6;k4}rff3?6=:r7o?h4<849>`60=;080q~jke;296~;c;l084:52d2f9ea=z{mo=6=4={<f0`?5?=27o?84<939~wabc2909w0j<d;1;3>;c;j0jh6s|dd794?4|5m9h6>6:;<f00?5>:2wxhim50;0x9a5d2:2<70j<b;cg?xucm=0;6?u2d2197<4<5m9i6>6:;|q0f0<72;qU?o;4=e1a>6>03tyoi=4?:3y>`62=;?801i=::7g8yv4fl3:1>vP=ae9>`60=;?80q~jj1;296~;c;?0=i63k348027=z{:=86=4:{<f50?71127o?>4m0:?g71<e827o?;4m0:?g70<e82wvn>;=:182g??=:<qCh>?4$566>a?d3S<:6<u>c;'6d`=;?i0e>o7:18'7=7=;h=0b>6?:198m6g1290/?5?53`58j6>72810e>o::18'7=7=;h=0b>6?:398m6g3290/?5?53`58j6>72:10e>o<:18'7=7=;h=0b>6?:598m6g5290/?5?53`58j6>72<10e>o>:18'7=7=;h=0b>6?:798m6g7290/?5?53`58j6>72>10e>7i:18'7=7=;h=0b>6?:998m6?b290/?5?53`58j6>72010e>l>:18'7=7=;h=0b>6?:`98m6d7290/?5?53`58j6>72k10e>oi:18'7=7=;h=0b>6?:b98m6gb290/?5?53`58j6>72m10e>ok:18'7=7=;h=0b>6?:d98m6gd290/?5?53`58j6>72o10e>om:18'7=7=;h=0b>6?:028?l5fi3:1(>6>:2c4?k5?83;:76g<a883>!5?939j;6`<81826>=n;0n1<7*<8080e2=i;1:1=>54i9194?=n;0:1<75f17c94?=n;k91<75f3c094?=n;k>1<75`3c794?=h:hn1<75md7694?7=83:p(9:::3cf?Mb1;2Bo?<5`17;94?=zjm986=4;:183!23=39=h6Fk629K`67<,:3:6i;;;h4f>5<<ak:1<75f38094?=h;?81<75rbe1f>5<f290;w):;5;1:g>Nc>:1Ch>?4Z7395~4c2t.85<4k559'6f1=<2c=j7>5;hcg>5<<a?i1<75`39794?=h;1=1<75f3b83>!5?939i7c=70;28?l5f290/?5?53c9m7=6=921b?44?:%1;5?5e3g93<7<4;h1;>5<#;1;1?o5a39297>=n;>0;6)=71;1a?k5?83>07plk3e83>d<729q/89;538a8La043An8=6T91;3x6a<z,:3:6i;;;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vni=l:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"4180o995+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3tho?o4?:`83>5}#<=?1?4m4He40?Mb492P==7?t2e8~ 6?62m??7)<l7;68m3`=831bmi4?::k5g?6=3f9397>5;n1;3?6=3`9h6=4+39397g=i;1:1<65f3`83>!5?939i7c=70;38?l5>290/?5?53c9m7=6=:21b?54?:%1;5?5e3g93<7=4;h14>5<#;1;1?o5a39290>=zjm9?6=4;:183!23=39=h6Fk629K`67<,:3:6i;;;h4f>5<<ak:1<75f38094?=h;?81<75rbe15>5<3290;w):;5;15`>Nc>:1Ch>?4$2;2>a333`<n6=44ic294?=n;081<75`37094?=zjm9>6=4;:183!23=39=h6Fk629K`67<,:3:6i;;;h4f>5<<ak:1<75f38094?=h;?81<75rs2c;>5<5sW9j463k3d80g>{t;h<1<7<t^2c5?8b4m39j7p}<a483>7}Y;h?01i=j:2;8yv5f<3:1>vP<a59>`6c=;11v>o<:181[5f;27o?h4<7:p7d4=838pR>o=;<f0`?5d3ty8m<4?:3y]7d7<5m9o6>o4}r1b4?6=:rT8m=52d2f97<=z{:3m6=4={_1:b>;c;m0846s|38g94?4|V:3n70j<d;14?xu4j80;6?uQ3c389a5d2:i0q~=m0;296~X4j916h>m53`9~w6ga2909wS=nf:?g7f<412wx?lk50;0xZ6gb34n8o7=7;|q0ea<72;qU?lj4=e1`>61<uz9jo7>52z\0ef=:l:h1?n5rs2ca>5<5sW9jn63k3c80e>{t;hk1<7<t^2cb?8b4j3927p}<a883>7}Y;h301i=m:2:8yv5>l3:1>vP<9e9>`6d=;>1v<8n:181[71i27o?>49e:p7g5=83?pR>l<;<f0a?0a34n8h78i;<f0g?0a34n8n78i;|q0f7<72<qU?o<4=e1f>3e<5m9o6;m4=e1`>3e<5m9i6;m4}r1a0?6=:rT8n952d2g9ea=z{mnm6=4={<f07?51:27o?949e:p``1=838p1i=j:2:6?8b4>392>6s|deg94?4|5m9n6>68;<f0`?gc3tyoi;4?:3y>`6b=;1?01i=::2;1?xuclm0;6?u2d2f97=1<5m9h6lj4}rff1?6=:r7o?n4<849>`62=;080q~jkc;296~;c;j084:52d2`9ea=z{mo?6=4={<f07?5>:27o?o4<849~w6d22909wS=m5:?g7g<40>1vik?:1818b4<39=>63k3485a>{t:hn1<7<t^3cg?8b4>39=>6s|dd394?4|5m9=6;k4=e16>6053ty8;>4?:4y>`32=9?301i=<:c289a532k:01i=9:c289a522k:0qpl<5283>4e=138>wEj<1:&700<c1m1Q:<4>{0a9y!4fn39=o6g<a983>!5?939j;6`<8183?>o4i?0;6)=71;1b3>h4090:76g<a483>!5?939j;6`<8181?>o4i=0;6)=71;1b3>h4090876g<a283>!5?939j;6`<8187?>o4i;0;6)=71;1b3>h4090>76g<a083>!5?939j;6`<8185?>o4i90;6)=71;1b3>h4090<76g<9g83>!5?939j;6`<818;?>o41l0;6)=71;1b3>h4090276g<b083>!5?939j;6`<818b?>o4j90;6)=71;1b3>h4090i76g<ag83>!5?939j;6`<818`?>o4il0;6)=71;1b3>h4090o76g<ae83>!5?939j;6`<818f?>o4ij0;6)=71;1b3>h4090m76g<ac83>!5?939j;6`<81824>=n;hk1<7*<8080e2=i;1:1=<54i2c:>5<#;1;1?l94n2:3>44<3`92h7>5$2:2>6g03g93<7?<;:k;7?6=3`92<7>5;h35e?6=3`9i?7>5;h1a6?6=3`9i87>5;n1a1?6=3f8jh7>5;cf50?6=93:1<v*;4481e`=Ol?90Di=>;n35=?6=3tho?>4?:583>5}#<=?1?;j4He40?Mb492.85<4k549j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`g7`<72h0;6=u+45797<e<@m<87Ej<1:X55?7|:m0v(>7>:e76?!4d?3>0e;h50;9jea<722c=o7>5;n1;1?6=3f93;7>5;h1`>5<#;1;1?o5a39294>=n;h0;6)=71;1a?k5?83;07d=6:18'7=7=;k1e?5>52:9j7=<72-93=7=m;o1;4?5<3`9<6=4+39397g=i;1:1865rbe1g>5<f290;w):;5;1:g>Nc>:1Ch>?4Z7395~4c2t.85<4k549'6f1=<2c=j7>5;hcg>5<<a?i1<75`39794?=h;1=1<75f3b83>!5?939i7c=70;28?l5f290/?5?53c9m7=6=921b?44?:%1;5?5e3g93<7<4;h1;>5<#;1;1?o5a39297>=n;>0;6)=71;1a?k5?83>07plk3b83>d<729q/89;538a8La043An8=6T91;3x6a<z,:3:6i;:;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vni=m:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"4180o985+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3tho?94?:583>5}#<=?1?;j4He40?Mb492.85<4k549j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`g73<72=0;6=u+457973b<@m<87Ej<1:&0=4<c=<1b:h4?::ka4?6=3`92>7>5;n156?6=3tho?84?:583>5}#<=?1?;j4He40?Mb492.85<4k549j2`<722ci<7>5;h1:6?6=3f9=>7>5;|q0e=<72;qU?l64=e1f>6e<uz9j:7>52z\0e3=:l:o1?l5rs2c6>5<5sW9j963k3d80=>{t;h>1<7<t^2c7?8b4m3937p}<a283>7}Y;h901i=j:258yv5f:3:1>vP<a39>`6b=;j1v>o>:181[5f927o?i4<a:p7d6=838pR>o?;<f0`?5>3ty85k4?:3y]7<`<5m9o6>64}r1:a?6=:rT85h52d2f972=z{:h:6=4={_1a5>;c;j08o6s|3c294?4|V:h;70j<c;1b?xu4io0;6?uQ3`d89a5d2:30q~=ne;296~X4il16h>m5399~w6gc2909wS=nd:?g7f<4?2wx?lm50;0xZ6gd34n8n7=l;|q0eg<72;qU?ll4=e1a>6g<uz9jm7>52z\0ed=:l:h1?45rs2c:>5<5sW9j563k3c80<>{t;0n1<7<t^2;g?8b4j39<7p}>6`83>7}Y9?k01i=<:7g8yv5e;3:19vP<b29>`6c=>o16h>j56g9>`6e=>o16h>l56g9~w6d5290>wS=m2:?g7`<1k27o?i49c:?g7f<1k27o?o49c:p7g2=838pR>l;;<f0a?gc3tyohk4?:3y>`65=;?801i=;:7g8yvbb?3:1>v3k3d80<0=:l:<1?4<4}rfga?6=:r7o?h4<869>`6b=im1vik9:1818b4l393963k3480=7=z{mno6=4={<f0`?5??27o?n4nd:p``3=838p1i=l:2:6?8b4<392>6s|dea94?4|5m9h6>68;<f0f?gc3tyoi94?:3y>`65=;0801i=m:2:6?xu4j<0;6?uQ3c789a5e2:2<7p}ke183>7}:l:>1?;<4=e16>3c<uz8jh7>52z\1ea=:l:<1?;<4}rff5?6=:r7o?;49e:?g70<4>;1v>9<:1868b1<3;=563k328a4>;c;=0i<63k378a4>;c;<0i<6srb277>5<6k331>8uGd238 1222m3n7W8>:0y2g?{#:hl1?;m4i2c;>5<#;1;1?l94n2:3>5=<a:k=6=4+39397d1<f:2;6<54i2c6>5<#;1;1?l94n2:3>7=<a:k?6=4+39397d1<f:2;6>54i2c0>5<#;1;1?l94n2:3>1=<a:k96=4+39397d1<f:2;6854i2c2>5<#;1;1?l94n2:3>3=<a:k;6=4+39397d1<f:2;6:54i2;e>5<#;1;1?l94n2:3>==<a:3n6=4+39397d1<f:2;6454i2`2>5<#;1;1?l94n2:3>d=<a:h;6=4+39397d1<f:2;6o54i2ce>5<#;1;1?l94n2:3>f=<a:kn6=4+39397d1<f:2;6i54i2cg>5<#;1;1?l94n2:3>`=<a:kh6=4+39397d1<f:2;6k54i2ca>5<#;1;1?l94n2:3>46<3`9jm7>5$2:2>6g03g93<7?>;:k0e<<72-93=7=n7:l0<5<6:21b?4j50;&0<4<4i>1e?5>51298m=5=831b?4>50;9j53g=831b?o=50;9j7g4=831b?o:50;9l7g3=831d>lj50;9a`32=83;1<7>t$566>7gb3An=?6Fk309l53?=831vni=<:187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e75?l0b2900eo>50;9j7<4=831d?;<50;9~fa5b290j6=4?{%671?5>k2Bo:>5Gd238^37=9r8o6p*<908g13=#:j=186g9f;29?lgc2900e;m50;9l7=3=831d?5950;9j7f<72-93=7=m;o1;4?6<3`9j6=4+39397g=i;1:1=65f3883>!5?939i7c=70;08?l5?290/?5?53c9m7=6=;21b?:4?:%1;5?5e3g93<7:4;|`g7a<72h0;6=u+45797<e<@m<87Ej<1:X55?7|:m0v(>7>:e75?!4d?3>0e;h50;9jea<722c=o7>5;n1;1?6=3f93;7>5;h1`>5<#;1;1?o5a39294>=n;h0;6)=71;1a?k5?83;07d=6:18'7=7=;k1e?5>52:9j7=<72-93=7=m;o1;4?5<3`9<6=4+39397g=i;1:1865rbe1`>5<f290;w):;5;1:g>Nc>:1Ch>?4Z7395~4c2t.85<4k579'6f1=<2c=j7>5;hcg>5<<a?i1<75`39794?=h;1=1<75f3b83>!5?939i7c=70;28?l5f290/?5?53c9m7=6=921b?44?:%1;5?5e3g93<7<4;h1;>5<#;1;1?o5a39297>=n;>0;6)=71;1a?k5?83>07plk3c83>d<729q/89;538a8La043An8=6T91;3x6a<z,:3:6i;9;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vni=;:187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e75?l0b2900eo>50;9j7<4=831d?;<50;9~fa51290?6=4?{%671?51l2Bo:>5Gd238 6?62m?=7d8j:188mg6=831b?4<50;9l734=831vni=::187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e75?l0b2900eo>50;9j7<4=831d?;<50;9~w6g?2909wS=n8:?g7`<4k2wx?l850;0xZ6g134n8i7=n;|q0e0<72;qU?l;4=e1f>6?<uz9j87>52z\0e1=:l:o1?55rs2c0>5<5sW9j?63k3d803>{t;h81<7<t^2c1?8b4l39h7p}<a083>7}Y;h;01i=k:2c8yv5f83:1>vP<a19>`6b=;01v>7i:181[5>n27o?i4<8:p7<c=838pR>7j;<f0`?503ty8n<4?:3y]7g7<5m9h6>m4}r1a4?6=:rT8n=52d2a97d=z{:km6=4={_1bb>;c;j0856s|3`g94?4|V:kn70j<c;1;?xu4im0;6?uQ3`f89a5d2:=0q~=nc;296~X4ij16h>l53b9~w6ge2909wS=nb:?g7g<4i2wx?lo50;0xZ6gf34n8n7=6;|q0e<<72;qU?l74=e1a>6><uz92h7>52z\0=a=:l:h1?:5rs04b>5<5sW;=m63k3285a>{t;k91<7;t^2`0?8b4m3<m70j<d;4e?8b4k3<m70j<b;4e?xu4j;0;68uQ3c089a5b2?i01i=k:7a89a5d2?i01i=m:7a8yv5e<3:1>vP<b59>`6c=im1viji:1818b4;39=>63k3585a>{tll=1<7<t=e1f>6>234n8:7=62:p`ac=838p1i=j:2:4?8b4l3ko7p}ke783>7}:l:n1?5;4=e16>6?53tyohi4?:3y>`6b=;1=01i=l:`f8yvbb=3:1>v3k3b80<0=:l:>1?4<4}rfgg?6=:r7o?n4<869>`6d=im1vik;:1818b4;392>63k3c80<0=z{:h>6=4={_1a1>;c;k084:5rseg3>5<5s4n887=92:?g70<1m2wx>lj50;0xZ7gc34n8:7=92:p``7=838p1i=9:7g89a522:<97p}<7283>0}:l?>1=;74=e10>g6<5m9?6o>4=e15>g6<5m9>6o>4}|`010<728i1o7<n{If05>"3<<0o5k5U60824e=u-8jj7=9c:k0e=<72-93=7=n7:l0<5<732c8m;4?:%1;5?5f?2d84=4>;:k0e0<72-93=7=n7:l0<5<532c8m94?:%1;5?5f?2d84=4<;:k0e6<72-93=7=n7:l0<5<332c8m?4?:%1;5?5f?2d84=4:;:k0e4<72-93=7=n7:l0<5<132c8m=4?:%1;5?5f?2d84=48;:k0=c<72-93=7=n7:l0<5<?32c85h4?:%1;5?5f?2d84=46;:k0f4<72-93=7=n7:l0<5<f32c8n=4?:%1;5?5f?2d84=4m;:k0ec<72-93=7=n7:l0<5<d32c8mh4?:%1;5?5f?2d84=4k;:k0ea<72-93=7=n7:l0<5<b32c8mn4?:%1;5?5f?2d84=4i;:k0eg<72-93=7=n7:l0<5<6821b?lo50;&0<4<4i>1e?5>51098m6g>290/?5?53`58j6>728807d=6d;29 6>62:k<7c=70;30?>o?;3:17d=60;29?l71i3:17d=m3;29?l5e:3:17d=m4;29?j5e=3:17b<nd;29?gb1=3:1=7>50z&700<c;o1Ch;=4He12?j50m3:17plk6583>4<729q/89;52`g8La043An8=6a>6883>>{e;=i1<7:50;2x 12228?o7Ej93:Jg74=#;0;1h864$3a4>44<a?81<75fae83>>o41;0;66a<8483>>{el:91<7:50;2x 1222:<o7Ej93:Jg74=#;0;1h894i7g94?=nj90;66g<9383>>i4>;0;66smd2g94?g=83:p(9:::2;`?Mb1;2Bo?<5U60827b=u-92=7j:7:&1g2<33`<m6=44i`f94?=n>j0;66a<8483>>i40>0;66g<c;29 6>62:h0b>6?:198m6g=83.84<4<b:l0<5<632c857>5$2:2>6d<f:2;6?54i2:94?"40808n6`<8180?>o4?3:1(>6>:2`8j6>72=10qoj<d;29e?6=8r.?884<9b9K`35<@m9:7W8>:0y1`?{#;0;1h894$3a4>1=n>o0;66gnd;29?l0d2900c>6::188k6>02900e>m50;&0<4<4j2d84=4?;:k0e?6=,:2:6>l4n2:3>4=<a:31<7*<8080f>h4090976g<8;29 6>62:h0b>6?:298m61=83.84<4<b:l0<5<332wih>m50;c94?6|,=>>6>7l;If57>Nc;81Q:<4>{3f9y!5>93n>;6*=c687?l0a2900elj50;9j2f<722e8484?::m0<2<722c8o7>5$2:2>6d<f:2;6=54i2c94?"40808n6`<8182?>o413:1(>6>:2`8j6>72;10e>650;&0<4<4j2d84=4<;:k03?6=,:2:6>l4n2:3>1=<ukn8n7>5a;294~"3<<085n5Gd718La563S<:6<u=d;'7<7=l<=0(?m8:59j2c<722cjh7>5;h4`>5<<g:2>6=44o2:4>5<<a:i1<7*<8080f>h4090;76g<a;29 6>62:h0b>6?:098m6?=83.84<4<b:l0<5<532c847>5$2:2>6d<f:2;6>54i2594?"40808n6`<8187?>{el:>1<7:50;2x 1222:<o7Ej93:Jg74=#;0;1h894i7g94?=nj90;66g<9383>>i4>;0;66smd2494?2=83:p(9:::24g?Mb1;2Bo?<5+3839`01<a?o1<75fb183>>o41;0;66a<6383>>{el:?1<7:50;2x 1222:<o7Ej93:Jg74=#;0;1h894i7g94?=nj90;66g<9383>>i4>;0;66sm35f94?2=83:p(9:::24g?Mb1;2Bo?<5+3839`0><a?o1<75fb183>>o41;0;66a<6383>>{t;h21<7<t^2c;?8b4m39h7p}<a783>7}Y;h<01i=j:2c8yv5f=3:1>vP<a49>`6c=;01v>o;:181[5f<27o?h4<8:p7d5=838pR>o<;<f0a?503ty8m?4?:3y]7d4<5m9o6>m4}r1b5?6=:rT8m<52d2f97d=z{:k;6=4={_1b4>;c;m0856s|38d94?4|V:3m70j<d;1;?xu41l0;6?uQ38g89a5c2:=0q~=m1;296~X4j816h>m53b9~w6d72909wS=m0:?g7f<4i2wx?lh50;0xZ6ga34n8o7=6;|q0e`<72;qU?lk4=e1`>6><uz9jh7>52z\0ea=:l:i1?:5rs2c`>5<5sW9jo63k3c80g>{t;hh1<7<t^2ca?8b4j39j7p}<a`83>7}Y;hk01i=m:2;8yv5f13:1>vP<a89>`6d=;11v>7k:181[5>l27o?o4<7:p<6<72;qU4>5235a927=z{:3;6=4={_1:4>;4<j085?5rs04b>5<5sW;=m63k3285a>{t;k91<7;t^2`0?8b4m3<m70j<d;4e?8b4k3<m70j<b;4e?xu4j;0;68uQ3c089a5b2?i01i=k:7a89a5d2?i01i=m:7a8yv5e<3:1>vP<b59>`6c=im1v?ok:181[4fl2788n4<849~waba2909w0j<3;156>;c;=0=i6s|dd594?4|5m9n6>6:;<f02?5>:2wxhik50;0x9a5b2:2<70j<d;cg?xucm?0;6?u2d2f97=3<5m9>6>7=;|qg`a<72;q6h>j539589a5d2hn0q~jj5;296~;c;j084852d2697<4<uznoo7>52z?g7f<40>16h>l5ae9~wac32909w0j<3;1:6>;c;k08485rs2`6>5<5sW9i963k3c80<2=z{mo;6=4={<f00?51:27o?849e:p``4=838p1i=9:241?853l3<n7p}ke083>7}:l:<1:h52d279734<uznn?7>52z?00f<fl2788i4<639~w6152909w0j95;14a>;4<m085?5rs250>5<1s4n=87?99:?g76<e827o?94m0:?g73<e827o?84m0:?00a<e82wv<j6:181[7c12788k4<a99~w4eb2909wS?le:?00c<4i?1v<m<:181[7d;2788k4<a49~w4d?2909wS?m8:?00c<4i=1v<ok:181[7fl2788k4<a29~w4g52909wS?n2:?00c<4i;1v<78:181[7>?2788k4<a09~w4>d2909wS?7c:?00c<4i91v<6>:181[7?92788k4<9g9~w4112909wS?86:?00c<41l1v?ol:181[4fk2788k4<b09~w7g72909wS<n0:?00c<4j91v?7::181[4>=2788k4<ag9~w7>f2909wS<7a:?00c<4il1v?9i:181[40n2788k4<ae9~w7132909wS<84:?00c<4ij1v?86:181[4112788k4<ac9~w72>2909wS<;9:?00c<4ih1v<jn:181[7ci2788k4<a89~w40e2909wS?9b:?00c<41m1v?87:181[4102789;4<a99~w7002909wS<97:?013<4i?1v?89:181[41>2789;4<a49~w7022909wS<95:?013<4i=1v?8;:181[41<2789;4<a29~w7042909wS<93:?013<4i;1v?8=:181[41:2789;4<a09~w7062909wS<91:?013<4i91v?8?:181[4182789;4<9g9~w7332909wS<:4:?013<41l1v?:7:181[4302789;4<b09~w75c2909wS<<d:?013<4j91v?==:181[44:2789;4<ag9~w7402909wS<=7:?013<4il1v??l:181[46k2789;4<ae9~w7762909wS<>1:?013<4ij1v?>9:181[47>2789;4<ac9~w4`e2909wS?ib:?013<4ih1v<h?:181[7a82789;4<a89~w4c22909wS?j5:?013<41m1v?9j:181[40m2789:4<a99~w71c2909wS<8d:?012<4i?1v?9l:181[40k2789:4<a49~w71e2909wS<8b:?012<4i=1v?9n:181[40i2789:4<a29~w71>2909wS<89:?012<4i;1v?97:181[4002789:4<a09~w7102909wS<87:?012<4i91v?99:181[40>2789:4<9g9~w7122909wS<85:?012<41l1v?9<:181[40;2789:4<b09~w7152909wS<82:?012<4j91v?9>:181[4092789:4<ag9~w7172909wS<80:?012<4il1v?8i:181[41n2789:4<ae9~w70b2909wS<9e:?012<4ij1v?8k:181[41l2789:4<ac9~w70d2909wS<9c:?012<4ih1v?8m:181[41j2789:4<a89~w70f2909wS<9a:?012<41m1v?7;:181[4><278954<a99~w7?42909wS<63:?01=<4i?1v?7=:181[4>:278954<a49~w7?62909wS<61:?01=<4i=1v?7?:181[4>8278954<a29~w7>a2909wS<7f:?01=<4i;1v?6j:181[4?m278954<a09~w7>c2909wS<7d:?01=<4i91v?6l:181[4?k278954<9g9~w7>e2909wS<7b:?01=<41l1v?66:181[4?1278954<b09~w7>?2909wS<78:?01=<4j91v?68:181[4??278954<ag9~w7>12909wS<76:?01=<4il1v?6::181[4?=278954<ae9~w7>32909wS<74:?01=<4ij1v?6<:181[4?;278954<ac9~w7>52909wS<72:?01=<4ih1v?6>:181[4?9278954<a89~w7>72909wS<70:?01=<41m1v?on:181[4fi278944<a99~w7g>2909wS<n9:?01<<4i?1v?o7:181[4f0278944<a49~w7g02909wS<n7:?01<<4i=1v?o9:181[4f>278944<a29~w7g22909wS<n5:?01<<4i;1v?o;:181[4f<278944<a09~w7g42909wS<n3:?01<<4i91v?o=:181[4f:278944<9g9~w7g62909wS<n1:?01<<41l1v?7i:181[4>n278944<b09~w7?b2909wS<6e:?01<<4j91v?7k:181[4>l278944<ag9~w7?d2909wS<6c:?01<<4il1v?7m:181[4>j278944<ae9~w7?f2909wS<6a:?01<<4ij1v?76:181[4>1278944<ac9~w7??2909wS<68:?01<<4ih1v?78:181[4>?278944<a89~w7?12909wS<66:?01<<41m1v<6?:181[7?82789l4<a99~w41a2909wS?8f:?01d<4i?1v<9j:181[70m2789l4<a49~w41c2909wS?8d:?01d<4i=1v<9l:181[70k2789l4<a29~w41e2909wS?8b:?01d<4i;1v<9n:181[70i2789l4<a09~w41>2909wS?89:?01d<4i91v<97:181[7002789l4<9g9~w4102909wS?87:?01d<41l1v<9::181[70=2789l4<b09~w4132909wS?84:?01d<4j91v<9<:181[70;2789l4<ag9~w4152909wS?82:?01d<4il1v<9>:181[7092789l4<ae9~w4172909wS?80:?01d<4ij1v<8i:181[71n2789l4<ac9~w40b2909wS?9e:?01d<4ih1v<8k:181[71l2789l4<a89~w40d2909wS?9c:?01d<41m1v<79:181[7>>2789o4<a99~w4?22909wS?65:?01g<4i?1v<7;:181[7><2789o4<a49~w4?42909wS?63:?01g<4i=1v<7=:181[7>:2789o4<a29~w4?62909wS?61:?01g<4i;1v<7?:181[7>82789o4<a09~w4>a2909wS?7f:?01g<4i91v<6j:181[7?m2789o4<9g9~w4>c2909wS?7d:?01g<41l1v<6m:181[7?j2789o4<b09~w4>f2909wS?7a:?01g<4j91v<66:181[7?12789o4<ag9~w4>?2909wS?78:?01g<4il1v<68:181[7??2789o4<ae9~w4>12909wS?76:?01g<4ij1v<6::181[7?=2789o4<ac9~w4>32909wS?74:?01g<4ih1v<6<:181[7?;2789o4<a89~w4>52909wS?72:?01g<41m1v<ol:181[7fk2789n4<a99~w4ge2909wS?nb:?01f<4i?1v<on:181[7fi2789n4<a49~w4g>2909wS?n9:?01f<4i=1v<o7:181[7f02789n4<a29~w4g02909wS?n7:?01f<4i;1v<o9:181[7f>2789n4<a09~w4g22909wS?n5:?01f<4i91v<o;:181[7f<2789n4<9g9~w4g42909wS?n3:?01f<41l1v<o>:181[7f92789n4<b09~w4g72909wS?n0:?01f<4j91v<7i:181[7>n2789n4<ag9~w4?b2909wS?6e:?01f<4il1v<7k:181[7>l2789n4<ae9~w4?d2909wS?6c:?01f<4ij1v<7m:181[7>j2789n4<ac9~w4?f2909wS?6a:?01f<4ih1v<76:181[7>12789n4<a89~w4??2909wS?68:?01f<41m1v<m=:181[7d:2789i4<a99~w4e62909wS?l1:?01a<4i?1v<m?:181[7d82789i4<a49~w4da2909wS?mf:?01a<4i=1v<lj:181[7em2789i4<a29~w4dc2909wS?md:?01a<4i;1v<ll:181[7ek2789i4<a09~w4de2909wS?mb:?01a<4i91v<ln:181[7ei2789i4<9g9~w4d>2909wS?m9:?01a<41l1v<l8:181[7e?2789i4<b09~w4d12909wS?m6:?01a<4j91v<l::181[7e=2789i4<ag9~w4d32909wS?m4:?01a<4il1v<l<:181[7e;2789i4<ae9~w4d52909wS?m2:?01a<4ij1v<l>:181[7e92789i4<ac9~w4d72909wS?m0:?01a<4ih1v<oi:181[7fn2789i4<a89~w4gb2909wS?ne:?01a<41m1v<j7:181[7c02789h4<a99~w4b02909wS?k7:?01`<4i?1v<j9:181[7c>2789h4<a49~w4b22909wS?k5:?01`<4i=1v<j;:181[7c<2789h4<a29~w4b42909wS?k3:?01`<4i;1v<j=:181[7c:2789h4<a09~w4b62909wS?k1:?01`<4i91v<j?:181[7c82789h4<9g9~w4ea2909wS?lf:?01`<41l1v<mk:181[7dl2789h4<b09~w4ed2909wS?lc:?01`<4j91v<mm:181[7dj2789h4<ag9~w4ef2909wS?la:?01`<4il1v<m6:181[7d12789h4<ae9~w4e?2909wS?l8:?01`<4ij1v<m8:181[7d?2789h4<ac9~w4e12909wS?l6:?01`<4ih1v<m::181[7d=2789h4<a89~w4e32909wS?l4:?01`<41m1v<ki:181[7bn2789=4<a99~w4cb2909wS?je:?015<4i?1v<kk:181[7bl2789=4<a49~w4cd2909wS?jc:?015<4i=1v<km:181[7bj2789=4<a29~w4cf2909wS?ja:?015<4i;1v<k6:181[7b12789=4<a09~w4c?2909wS?j8:?015<4i91v<k8:181[7b?2789=4<9g9~w4c12909wS?j6:?015<41l1v<k;:181[7b<2789=4<b09~w4c42909wS?j3:?015<4j91v<k=:181[7b:2789=4<ag9~w4c62909wS?j1:?015<4il1v<k?:181[7b82789=4<ae9~w4ba2909wS?kf:?015<4ij1v<jj:181[7cm2789=4<ac9~w4bc2909wS?kd:?015<4ih1v<jl:181[7ck2789=4<a89~w4be2909wS?kb:?015<41m1v?>::181[47=2789<4<a99~w7632909wS<?4:?014<4i?1v?><:181[47;2789<4<a49~w7652909wS<?2:?014<4i=1v?>>:181[4792789<4<a29~w7672909wS<?0:?014<4i;1v<hi:181[7an2789<4<a09~w4`b2909wS?ie:?014<4i91v<hk:181[7al2789<4<9g9~w4`d2909wS?ic:?014<41l1v<hn:181[7ai2789<4<b09~w4`>2909wS?i9:?014<4j91v<h7:181[7a02789<4<ag9~w4`02909wS?i7:?014<4il1v<h9:181[7a>2789<4<ae9~w4`22909wS?i5:?014<4ij1v<h;:181[7a<2789<4<ac9~w4`42909wS?i3:?014<4ih1v<h=:181[7a:2789<4<a89~w4`62909wS?i1:?014<41m1v??m:181[46j2789?4<a99~w77f2909wS<>a:?017<4i?1v??6:181[4612789?4<a49~w77?2909wS<>8:?017<4i=1v??8:181[46?2789?4<a29~w7712909wS<>6:?017<4i;1v??::181[46=2789?4<a09~w7732909wS<>4:?017<4i91v??<:181[46;2789?4<9g9~w7752909wS<>2:?017<41l1v???:181[4682789?4<b09~w76a2909wS<?f:?017<4j91v?>j:181[47m2789?4<ag9~w76c2909wS<?d:?017<4il1v?>l:181[47k2789?4<ae9~w76e2909wS<?b:?017<4ij1v?>n:181[47i2789?4<ac9~w76>2909wS<?9:?017<4ih1v?>7:181[4702789?4<a89~w7602909wS<?7:?017<41m1v?=>:181[4492789>4<a99~w7572909wS<<0:?016<4i?1v?<i:181[45n2789>4<a49~w74b2909wS<=e:?016<4i=1v?<k:181[45l2789>4<a29~w74d2909wS<=c:?016<4i;1v?<m:181[45j2789>4<a09~w74f2909wS<=a:?016<4i91v?<6:181[4512789>4<9g9~w74?2909wS<=8:?016<41l1v?<9:181[45>2789>4<b09~w7422909wS<=5:?016<4j91v?<;:181[45<2789>4<ag9~w7442909wS<=3:?016<4il1v?<=:181[45:2789>4<ae9~w7462909wS<=1:?016<4ij1v?<?:181[4582789>4<ac9~w77a2909wS<>f:?016<4ih1v??j:181[46m2789>4<a89~w77c2909wS<>d:?016<41m1v?:8:181[43?278994<a99~w7212909wS<;6:?011<4i?1v?:::181[43=278994<a49~w7232909wS<;4:?011<4i=1v?:<:181[43;278994<a29~w7252909wS<;2:?011<4i;1v?:>:181[439278994<a09~w7272909wS<;0:?011<4i91v?=i:181[44n278994<9g9~w75b2909wS<<e:?011<41l1v?=l:181[44k278994<b09~w75e2909wS<<b:?011<4j91v?=n:181[44i278994<ag9~w75>2909wS<<9:?011<4il1v?=7:181[440278994<ae9~w7502909wS<<7:?011<4ij1v?=9:181[44>278994<ac9~w7522909wS<<5:?011<4ih1v?=;:181[44<278994<a89~w7542909wS<<3:?011<41m1v?;i:181[42n278984<a99~w73c2909wS<:d:?010<4i?1v?;l:181[42k278984<a49~w73e2909wS<:b:?010<4i=1v?;n:181[42i278984<a29~w73>2909wS<:9:?010<4i;1v?;7:181[420278984<a09~w7302909wS<:7:?010<4i91v?;9:181[42>278984<9g9~w7322909wS<:5:?010<41l1v?;<:181[42;278984<b09~w7352909wS<:2:?010<4j91v?;>:181[429278984<ag9~w7372909wS<:0:?010<4il1v?:i:181[43n278984<ae9~w72b2909wS<;e:?010<4ij1v?:k:181[43l278984<ac9~w72d2909wS<;c:?010<4ih1v?:m:181[43j278984<a89~w72f2909wS<;a:?010<41m1v5=50;32[>4349?j76<;<162?>4349>;76<;<16<?>4349>576<;<16e?>4349>n76<;<16g?>4349>h76<;<16a?>4349><76<;<165?>4349>>76<;<167?>4349>876<;<161?>43ty85=4?:03xZ6?7349?j7=60:?013<41916?8953828963?2:3;70=:9;1:4>;4=h085=5234`97<6<5:?h6>7?;<16`?5>82789h4<919>706=;0:01>;>:2;3?852:392<63<5280=5=:;<>1?4>4=276>6?73ty8n>4?:03xZ6d4349?j7=m3:?013<4j:16?8953c18963?2:h870=:9;1a7>;4=h08n>5234`97g5<5:?h6>l<;<16`?5e;2789h4<b29>706=;k901>;>:2`0?852:39i?63<5280f6=:;<>1?o=4=276>6d43ty8n?4?:03xZ6d5349?j7=m2:?013<4j;16?8953c08963?2:h970=:9;1a6>;4=h08n?5234`97g4<5:?h6>l=;<16`?5e:2789h4<b39>706=;k801>;>:2`1?852:39i>63<5280f7=:;<>1?o<4=276>6d53ty8n94?:3y]7g2<5:?>6>l;;|q0f0<72;qU?o;4=26e>6d23tyonk4?:3y>71`=:hn01>;9:04b?xucn90;6?u235d97g2<5:?=6>l:;|qgg5<72;q6?8852`f8963028<j7p}kf083>7}:;<<1?o:4=274>6d23tyoo<4?:3y>701=:hn01>;7:04b?xucn;0;6?u234597g2<5:?36>l:;|qgg7<72;q6?8652`f8963>28<j7p}kf283>7}:;<21?o:4=27:>6d23tyoo>4?:3y>70?=:hn01>;n:04b?xucn=0;6?u234;97g2<5:?j6>l:;|qgg1<72;q6?8o52`f8963e28<j7p}kf483>7}:;<k1?o:4=27a>6d23tyoo84?:3y>70d=:hn01>;l:04b?xucn?0;6?u234`97g2<5:?h6>l:;|qgg3<72;q6?8m52`f8963c28<j7p}kf683>7}:;<i1?o:4=27g>6d23tyoo:4?:3y>70b=:hn01>;j:04b?xucn10;6?u234f97g2<5:?n6>l:;|qgf<<72;q6?8k52`f8963728<j7p}ke`83>7}:;<o1?o:4=273>6d23tyonl4?:3y>706=:hn01>;>:04b?xucmk0;6?u234297g2<5:?:6>l:;|qgfg<72;q6?8?52`f8963528<j7p}keb83>7}:;<;1?o:4=271>6d23tyonn4?:3y>704=:hn01>;<:04b?xucmm0;6?u234097g2<5:?86>l:;|qgfa<72;q6?8=52`f8963328<j7p}ked83>7}:;<91?o:4=277>6d23tyonh4?:3y>702=:hn01>;::04b?xucmo0;6?u234697g2<5:?>6>l:;|q1ea<72;qU>lj4=276>7gc3twi4im50;194?6|,=>>6>88;If57>Nc;81/>n951`9'7=4=l?o0e?l>:188m7d52900c>9l:188yg>fm3:197>50z&700<4>01Ch;=4He12?!4d?3i0(>6=:e4g?l4e93:17d<m2;29?l4e;3:17d<m4;29?j50k3:17pl7b183>0<729q/89;537;8La043An8=6*=c68bb>"40;0o;?5f2c394?=n:k81<75f2c194?=n:k>1<75`36a94?=zj1h:6=4::183!23=39=56Fk629K`67<,;i<6?;4$2:1>a0c3`8i=7>5;h0a6?6=3`8i?7>5;h0a0?6=3f9<o7>5;|`;f7<72<0;6=u+457973?<@m<87Ej<1:&1g2<6=;1/?5<5d618m7d62900e?l=:188m7d42900e?l;:188k61d2900qo6m3;291?6=8r.?884<689K`35<@m9:7)<l7;365>o5j80;66g=b383>>o5j:0;66g=b583>>i4?j0;66sm8c694?3=83:p(9:::24:?Mb1;2Bo?<5+2b59f>"40;0o;?5f2c394?=n:k81<75f2c194?=n:k>1<75`36a94?=zj1h>6=4::183!23=39=56Fk629K`67<,;i<6>5+3909`25<a;h:6=44i3`1>5<<a;h86=44i3`7>5<<g:=h6=44}c:a2?6==3:1<v*;44802<=Ol?90Di=>;%0`3?g<,:296i9:;h0a5?6=3`8i>7>5;h0a7?6=3`8i87>5;n14g?6=3th3n:4?:483>5}#<=?1?;74He40?Mb492.9o:4>5g9'7=4=l>>0e?l>:188m7d52900e?l<:188m7d32900c>9l:188yg>e03:197>50z&700<4>01Ch;=4He12?!4d?3;=7)=72;f41>o5j80;66g=b383>>o5j:0;66g=b583>>i4?j0;66sm8`d94?3=83:p(9:::24:?Mb1;2Bo?<5+2b5955=#;181h::4i3`2>5<<a;h96=44i3`0>5<<a;h?6=44o25`>5<<uk3:87>52;294~"3<<088o5Gd718La563`8i<7>5;n14g?6=3th3io4?:283>5}#<=?1?;94He40?Mb492.9o:4>a:k1f4<722c9n?4?::m03f<722wi4il50;194?6|,=>>6>88;If57>Nc;81/>n95259'7=4=l>20e?l>:188m7d52900c>9l:188yg?6;3:1?7>50z&700<4>>1Ch;=4He12?!4d?3;?o6*<838g2`=n:k;1<75f2c094?=h;>i1<75rb82`>5<2290;w):;5;15=>Nc>:1Ch>?4$3a4>47<,:296i97;h0a5?6=3`8i>7>5;h0a7?6=3`8i87>5;n14g?6=3th3h44?:683>5}#<=?1?;l4He40?Mb492.9o:4>559j6g7=831b>o<50;9j6g5=831b>o:50;9j6g3=831b>o850;9l72e=831vn5jn:184>5<7s->?97=9b:Jg26=Ol:;0(?m8:077?l4e93:17d<m2;29?l4e;3:17d<m4;29?l4e=3:17d<m6;29?j50k3:17pl60d83>1<729q/89;514:8La043An8=6*=c681?l052900e;m50;9jea<722e8484?::a=5`=83>1<7>t$566>43?3An=?6Fk309'6f1=:2c=>7>5;h4`>5<<ahn1<75`39794?=zj0:o6=4;:183!23=3;>n6Fk629K`67<,;i<6?5f6383>>ofl3:17d=78;29?j5?=3:17pl7e383>0<729q/89;51458La043An8=6*=c681?l052900e;m50;9j<1<722cjh7>5;n1;1?6=3th3hi4?:583>5}#<=?1=8l4He40?Mb492.9o:4=;h41>5<<ahn1<75f39:94?=h;1?1<75rb9g2>5<2290;w):;5;363>Nc>:1Ch>?4$3a4>7=n>;0;66g9c;29?l>32900elj50;9l7=3=831vn5k?:187>5<7s->?97?:8:Jg26=Ol:;0(?m8:39j27<722c=o7>5;hcg>5<<g:2>6=44}c;6f?6=<3:1<v*;44821==Ol?90Di=>;%0`3?4<a?81<75f6b83>>ofl3:17b=75;29?xd?l10;694?:1y'013=;?:0Di8<;If05>"5k>097W=md;3xe`<zR8<36<u<be8~m=2=831bmi4?::k22<<722e8484?::a=43=83?1<7>t$566>43d3An=?6Fk309'6f1=:2c=>7>5;h4`>5<<ahn1<75f39:94?=h;1?1<75rb835>5<2290;w):;5;36g>Nc>:1Ch>?4$3a4>7=n>;0;66g9c;29?lgc2900e>67:188k6>22900qo6m9;291?6=8r.?884>5b9K`35<@m9:7)<l7;08m34=831b:n4?::kb`?6=3`9347>5;n1;1?6=3th3nl4?:483>5}#<=?1=8m4He40?Mb492.9o:4=;h41>5<<a?i1<75fae83>>o4010;66a<8483>>{e0kh1<7;50;2x 12228?h7Ej93:Jg74=#:j=1>6g92;29?l0d2900elj50;9j7=>=831d?5;50;9~f=dd290>6=4?{%671?72k2Bo:>5Gd238 7e02;1b:?4?::k5g?6=3`ko6=44i2:;>5<<g:2>6=44}c:a`?6==3:1<v*;44821f=Ol?90Di=>;%0`3?4<a?81<75f6b83>>ofl3:17d=78;29?j5?=3:17pl7bd83>0<729q/89;514a8La043An8=6*=c681?l052900e;m50;9jea<722c8454?::m0<0<722wi4oh50;794?6|,=>>6<;l;If57>Nc;81/>n952:k56?6=3`<h6=44i`f94?=n;121<75`39794?=zj1i;6=4::183!23=3;>o6Fk629K`67<,;i<6?5f6383>>o1k3:17dok:188m6>?2900c>6::188yg>d93:197>50z&700<6=j1Ch;=4He12?!4d?380e;<50;9j2f<722cjh7>5;h1;<?6=3f9397>5;|`;g7<72<0;6=u+457950e<@m<87Ej<1:&1g2<53`<96=44i7a94?=nim0;66g<8983>>i40<0;66sm8e794?2=83:p(9:::07;?Mb1;2Bo?<5+2b596>o1:3:17d8l:188mdb=831d?5;50;9~f=cf290?6=4?{%671?7202Bo:>5Gd238 7e02;1b:?4?::k5g?6=3`ko6=44o2:6>5<<uk2n57>54;294~"3<<0:955Gd718La563-8h;7<4i7094?=n>j0;66gnd;29?j5?=3:17pl62e83>6<729q/89;5d708La043An8=6g9e;29?l5193:17b=8c;29?xd>:h0;694?:1y'013=;?n0Di8<;If05>o1m3:17dl?:188m6?52900c>8=:188yg?493:1?7>50z&700<c>;1Ch;=4He12?l0b2900e>8>:188k61d2900qo7=e;290?6=8r.?884<6e9K`35<@m9:7d8j:188mg6=831b?4<50;9l734=831vn4=::180>5<7s->?97j92:Jg26=Ol:;0e;k50;9j737=831d?:m50;9~f<55290?6=4?{%671?51l2Bo:>5Gd238m3c=831bn=4?::k0=7<722e8:?4?::a=6?=8391<7>t$566>a053An=?6Fk309j2`<722c8:<4?::m03f<722wi5>850;694?6|,=>>6>8k;If57>Nc;81b:h4?::ka4?6=3`92>7>5;n156?6=3th2?i4?:283>5}#<=?1h;<4He40?Mb492c=i7>5;h155?6=3f9<o7>5;|`:7d<72=0;6=u+457973b<@m<87Ej<1:k5a?6=3`h;6=44i2;1>5<<g:<96=44}c;75?6=;3:1<v*;448g27=Ol?90Di=>;h4f>5<<a:<:6=44o25`>5<<uk38i7>54;294~"3<<08:i5Gd718La563`<n6=44ic294?=n;081<75`37094?=zj0>>6=4<:183!23=3n=>6Fk629K`67<a?o1<75f37394?=h;>i1<75rb861>5<3290;w):;5;15`>Nc>:1Ch>?4i7g94?=nj90;66g<9383>>i4>;0;66sm95;94?5=83:p(9:::e41?Mb1;2Bo?<5f6d83>>o4>80;66a<7b83>>{e1=<1<7:50;2x 1222:<o7Ej93:Jg74=n>l0;66gm0;29?l5>:3:17b=92;29?xd><m0;6>4?:1y'013=l?80Di8<;If05>o1m3:17d=91;29?j50k3:17pl64`83>1<729q/89;537f8La043An8=6g9e;29?ld72900e>7=:188k6052900qo7:0;297?6=8r.?884k639K`35<@m9:7d8j:188m6062900c>9l:188yg?5k3:1>7>50z&700<4>?1Ch;=4He12?!4d?3;j7d<m1;29?j50k3:17pl63183>7<729q/89;53748La043An8=6*=c682e>o5j80;66a<7b83>>{e1:>1<7<50;2x 1222:<=7Ej93:Jg74=#:j=1=l5f2c394?=h;>i1<75rb81;>5<5290;w):;5;152>Nc>:1Ch>?4$3a4>4g<a;h:6=44o25`>5<<uk38o7>52;294~"3<<08:;5Gd718La563-8h;7?n;h0a5?6=3f9<o7>5;|`:05<72;0;6=u+4579730<@m<87Ej<1:&1g2<6i2c9n<4?::m03f<722wi59:50;094?6|,=>>6>89;If57>Nc;81/>n951`9j6g7=831d?:m50;9~f<2?29096=4?{%671?51>2Bo:>5Gd238 7e028k0e?l>:188k61d2900qo7;c;296?6=8r.?884<679K`35<@m9:7)<l7;3b?l4e93:17b=8c;29?xd><o0;6?4?:1y'013=;?<0Di8<;If05>"5k>0:m6g=b083>>i4?j0;66sm93`94?3=83:p(9:::07`?Mb1;2Bo?<5+2b596>o1:3:17d8l:188mdb=831b?5650;9l7=3=831vn4<i:186>5<7s->?97?:c:Jg26=Ol:;0(?m8:39j27<722c=o7>5;hcg>5<<a:236=44o2:6>5<<uk38?7>55;294~"3<<0:9n5Gd718La563-8h;7<4i7094?=n>j0;66gnd;29?l5?03:17b=75;29?xd>;>0;684?:1y'013=9<i0Di8<;If05>"5k>097d8=:188m3e=831bmi4?::k0<=<722e8484?::a=6d=83?1<7>t$566>43d3An=?6Fk309'6f1=:2c=>7>5;h4`>5<<ahn1<75f39:94?=h;1?1<75rb81e>5<2290;w):;5;36g>Nc>:1Ch>?4$3a4>7=n>;0;66g9c;29?lgc2900e>67:188k6>22900qo7;3;291?6=8r.?884>5b9K`35<@m9:7)<l7;08m34=831b:n4?::kb`?6=3`9347>5;n1;1?6=3th28:4?:483>5}#<=?1=8m4He40?Mb492.9o:4=;h41>5<<a?i1<75fae83>>o4010;66a<8483>>{e1=h1<7;50;2x 12228?h7Ej93:Jg74=#:j=1>6g92;29?l0d2900elj50;9j7=>=831d?5;50;9~f<2b290>6=4?{%671?72k2Bo:>5Gd238 7e02;1b:?4?::k5g?6=3`ko6=44i2:;>5<<g:2>6=44}c::a?6=;3:1<v*;448022=Ol?90Di=>;%0`3?433-93>7j80:k1f4<722c9n?4?::m03f<722wi44j50;694?6|,=>>6>87;If57>Nc;81/>n9515g8m7d62900e?l=:188m7d42900c>9l:188yg>>k3:197>50z&700<4>01Ch;=4He12?!4d?3;=<6*<838g2c=n:k;1<75f2c094?=n:k91<75f2c694?=h;>i1<75rb957>5<3290;w):;5;36`>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o41;0;66a<8483>>{e0>91<7:50;2x 12228?o7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=62;29?j5?=3:17pl77383>1<729q/89;514f8La043An8=6*=c6826>o1:3:17dok:188m6?52900c>6::188yg>093:187>50z&700<6=m1Ch;=4He12?!4d?3;97d8=:188mdb=831b?4<50;9l7=3=831vn59?:187>5<7s->?97?:d:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0=7<722e8484?::a<3`=83>1<7>t$566>43c3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`92>7>5;n1;1?6=3th3:h4?:583>5}#<=?1=8j4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2;1>5<<g:2>6=44}c:5`?6=<3:1<v*;44821a=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;081<75`39794?=zj12h6=4<:183!23=39=;6Fk629K`67<,;i<6<o4i3`2>5<<a;h96=44o25`>5<<uk22=7>54;294~"3<<0:955Gd718La563-8h;7<4i7094?=n>j0;66gnd;29?j5?=3:17pl79183>1<729q/89;514:8La043An8=6*=c681?l052900e;m50;9jea<722e8484?::a<<4=83?1<7>t$566>4303An=?6Fk309'6f1=:2c=>7>5;h4`>5<<a1>1<75fae83>>i40<0;66sm89f94?2=83:p(9:::07a?Mb1;2Bo?<5+2b596>o1:3:17dok:188m6>?2900c>6::188yg>>;3:197>50z&700<6=>1Ch;=4He12?!4d?380e;<50;9j2f<722c387>5;hcg>5<<g:2>6=44}c:4=?6=;3:1<v*;448022=Ol?90Di=>;%0`3?7f3`8i=7>5;h0a6?6=3f9<o7>5;|`;<5<72=0;6=u+457950><@m<87Ej<1:&1g2<53`<96=44i7a94?=nim0;66a<8483>>{e0>l1<7:50;2x 12228?37Ej93:Jg74=#:j=1>6g92;29?l0d2900elj50;9l7=3=831vn59j:187>5<7s->?97?:8:Jg26=Ol:;0(?m8:39j27<722c=o7>5;hcg>5<<g:2>6=44}c:4`?6=<3:1<v*;44821==Ol?90Di=>;%0`3?4<a?81<75f6b83>>ofl3:17b=75;29?xd?080;684?:1y'013=9<=0Di8<;If05>"5k>097d8=:188m3e=831b494?::kb`?6=3f9397>5;|`;3d<72=0;6=u+457950d<@m<87Ej<1:&1g2<53`<96=44i`f94?=n;121<75`39794?=zj1296=4::183!23=3;>;6Fk629K`67<,;i<6?5f6383>>o1k3:17d6;:188mdb=831d?5;50;9~f237290j6=4?{%671?5>k2Bo:>5Gd238^37=9r8o6p*=c687?l0a2900elj50;9j2f<722e8484?::m0<2<722c8o7>5$2:2>6d<f:2;6=54i2c94?"40808n6`<8182?>o413:1(>6>:2`8j6>72;10e>650;&0<4<4j2d84=4<;:k03?6=,:2:6>l4n2:3>1=<uk=>57>5a;294~"3<<085n5Gd718La563S<:6<u=d;'6f1=<2c=j7>5;hcg>5<<a?i1<75`39794?=h;1=1<75f3b83>!5?939i7c=70;28?l5f290/?5?53c9m7=6=921b?44?:%1;5?5e3g93<7<4;h1;>5<#;1;1?o5a39297>=n;>0;6)=71;1a?k5?83>07pl85983>d<729q/89;538a8La043An8=6T91;3x6a<z,;i<695f6g83>>ofl3:17d8l:188k6>22900c>68:188m6e=83.84<4<b:l0<5<732c8m7>5$2:2>6d<f:2;6<54i2;94?"40808n6`<8181?>o403:1(>6>:2`8j6>72:10e>950;&0<4<4j2d84=4;;:a376=83k1<7>t$566>6?d3An=?6Fk309Y24<6s;n1q)<nf;:5<>"4180o9=5+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3th<=k4?:`83>5}#<=?1?4m4He40?Mb492P==7?t2e8~ 7ga21<37)=61;f64>"5k>0?7d8i:188mdb=831b:n4?::m0<0<722e84:4?::k0g?6=,:2:6>l4n2:3>5=<a:k1<7*<8080f>h4090:76g<9;29 6>62:h0b>6?:398m6>=83.84<4<b:l0<5<432c8;7>5$2:2>6d<f:2;6954}c52a?6=<3:1<v*;44802`=Ol?90Di=>;%0bb?>102.85<4k519j6g7=831b>o<50;9j7<4=831d?:m50;9~f234290j6=4?{%671?5>k2Bo:>5Gd238^37=9r8o6p*=ag8;2f=#;0;1h8>4$3a4>1=n>o0;66gnd;29?l0d2900c>6::188k6>02900e>m50;&0<4<4j2d84=4?;:k0e?6=,:2:6>l4n2:3>4=<a:31<7*<8080f>h4090976g<8;29 6>62:h0b>6?:298m61=83.84<4<b:l0<5<332wi;8<50;c94?6|,=>>6>7l;If57>Nc;81Q:<4>{3f9y!4fn32=o6*<908g15=#:j=186g9f;29?lgc2900e;m50;9l7=3=831d?5950;9j7f<72-93=7=m;o1;4?6<3`9j6=4+39397g=i;1:1=65f3883>!5?939i7c=70;08?l5?290/?5?53c9m7=6=;21b?:4?:%1;5?5e3g93<7:4;|`414<72=0;6=u+457973c<@m<87Ej<1:&1ec<?>j1/?4?5d428m7d62900e?l=:188m6?52900c>9l:188yg15?3:1m7>50z&700<41j1Ch;=4He12?_0628q9h7s+2`d9<3?<,:3:6i;?;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vn:<9:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"5io03:45+3839`06<,;i<695f6g83>>ofl3:17d8l:188k6>22900c>68:188m6e=83.84<4<b:l0<5<732c8m7>5$2:2>6d<f:2;6<54i2;94?"40808n6`<8181?>o403:1(>6>:2`8j6>72:10e>950;&0<4<4j2d84=4;;:a373=83>1<7>t$566>60b3An=?6Fk309'6d`=0?30(>7>:e73?l4e93:17d<m2;29?l5>:3:17b=8c;29?xd0<=0;6l4?:1y'013=;0i0Di8<;If05>\193;p>i4r$3ce>=0e3-92=7j:0:&1g2<33`<m6=44i`f94?=n>j0;66a<8483>>i40>0;66g<c;29 6>62:h0b>6?:198m6g=83.84<4<b:l0<5<632c857>5$2:2>6d<f:2;6?54i2:94?"40808n6`<8180?>o4?3:1(>6>:2`8j6>72=10qo9;3;29e?6=8r.?884<9b9K`35<@m9:7W8>:0y1`?{#:hl14;l4$2;2>a373-8h;7:4i7d94?=nim0;66g9c;29?j5?=3:17b=77;29?l5d290/?5?53c9m7=6=821b?l4?:%1;5?5e3g93<7?4;h1:>5<#;1;1?o5a39296>=n;10;6)=71;1a?k5?83907d=8:18'7=7=;k1e?5>54:9~f225290j6=4?{%671?5>k2Bo:>5Gd238^37=9r8o6p*=ag8;2g=#;0;1h8>4$3a4>1=n>o0;66gnd;29?l0d2900c>6::188k6>02900e>m50;&0<4<4j2d84=4?;:k0e?6=,:2:6>l4n2:3>4=<a:31<7*<8080f>h4090976g<8;29 6>62:h0b>6?:298m61=83.84<4<b:l0<5<332wi;9?50;c94?6|,=>>6>7l;If57>Nc;81Q:<4>{3f9y!4fn32=n6*<908g15=#:j=186g9f;29?lgc2900e;m50;9l7=3=831d?5950;9j7f<72-93=7=m;o1;4?6<3`9j6=4+39397g=i;1:1=65f3883>!5?939i7c=70;08?l5?290/?5?53c9m7=6=;21b?:4?:%1;5?5e3g93<7:4;|`47`<72=0;6=u+457973c<@m<87Ej<1:&1ec<?>k1/?4?5d428m7d62900e?l=:188m6?52900c>9l:188yg14n3:187>50z&700<4>l1Ch;=4He12?!4fn32=n6*<908g15=n:k;1<75f2c094?=n;081<75`36a94?=zj>>;6=4;:183!23=39=j6Fk629K`67<,;km658m;%1:5?b282c9n<4?::k1f7<722c85?4?::m03f<722wi;><50;c94?6|,=>>6>7l;If57>Nc;81Q:<4>{3f9y!4fn32=m6*<908g15=#:j=186g9f;29?lgc2900e;m50;9l7=3=831d?5950;9j7f<72-93=7=m;o1;4?6<3`9j6=4+39397g=i;1:1=65f3883>!5?939i7c=70;08?l5?290/?5?53c9m7=6=;21b?:4?:%1;5?5e3g93<7:4;|`474<72h0;6=u+45797<e<@m<87Ej<1:X55?7|:m0v(?oi:94b?!5>93n><6*=c687?l0a2900elj50;9j2f<722e8484?::m0<2<722c8o7>5$2:2>6d<f:2;6=54i2c94?"40808n6`<8182?>o413:1(>6>:2`8j6>72;10e>650;&0<4<4j2d84=4<;:k03?6=,:2:6>l4n2:3>1=<uk=8<7>5a;294~"3<<085n5Gd718La563S<:6<u=d;'6d`=0?k0(>7>:e73?!4d?3>0e;h50;9jea<722c=o7>5;n1;1?6=3f93;7>5;h1`>5<#;1;1?o5a39294>=n;h0;6)=71;1a?k5?83;07d=6:18'7=7=;k1e?5>52:9j7=<72-93=7=m;o1;4?5<3`9<6=4+39397g=i;1:1865rb60e>5<f290;w):;5;1:g>Nc>:1Ch>?4Z7395~4c2t.9mk476`9'7<7=l<:0(?m8:59j2c<722cjh7>5;h4`>5<<g:2>6=44o2:4>5<<a:i1<7*<8080f>h4090;76g<a;29 6>62:h0b>6?:098m6?=83.84<4<b:l0<5<532c847>5$2:2>6d<f:2;6>54i2594?"40808n6`<8187?>{e?;i1<7:50;2x 1222:<n7Ej93:Jg74=#:hl14;o4$2;2>a373`8i=7>5;h0a6?6=3`92>7>5;n14g?6=3th<>i4?:583>5}#<=?1?;k4He40?Mb492.9mk476`9'7<7=l<:0e?l>:188m7d52900e>7=:188k61d2900qo9=e;290?6=8r.?884<6g9K`35<@m9:7)<nf;:5e>"4180o9=5f2c394?=n:k81<75f38094?=h;>i1<75rb674>5<>290;w):;5;1:f>Nc>:1Ch>?4$3a4>6=n;;0;66g<3;29?l532900e>;50;9j2f<722c=j7>5;hcg>5<<g:2>6=44o2:5>5<<uk=?j7>59;294~"3<<085o5Gd718La563-8h;7=4i2094?=n;:0;66g<4;29?l522900e;m50;9j2c<722cjh7>5;n1;1?6=3f93:7>5;|`;0c<72=0;6=u+457973><@m<87Ej<1:&1g2<6j2c9n<4?::k1f7<722c9n>4?::m03f<722wi;<j50;694?6|,=>>6<;m;If57>Nc;81/>lh587:8 6?62m?:7)<l7;08m34=831bmi4?::k0<=<722e8484?::a36b=83>1<7>t$566>43e3An=?6Fk309'6d`=0?h0(>7>:e72?!4d?380e;<50;9jea<722c8454?::m0<0<722wi;?l50;694?6|,=>>6<;m;If57>Nc;81/>lh587c8 6?62m?:7)<l7;08m34=831bmi4?::k0<=<722e8484?::a<07=83>1<7>t$566>43e3An=?6Fk309'6f1=:2c=>7>5;hcg>5<<a:236=44o2:6>5<<uk2><7>54;294~"3<<0:9o5Gd718La563-8h;7<4i7094?=nim0;66g<8983>>i40<0;66sm70a94?2=83:p(9:::07a?Mb1;2Bo?<5+2b596>o1:3:17dok:188m6>?2900c>6::188yg16j3:187>50z&700<6=k1Ch;=4He12?!4d?380e;<50;9jea<722c8454?::m0<0<722wi49k50;794?6|,=>>6<;l;If57>Nc;81/>n952:k56?6=3`<h6=44i`f94?=n;121<75`39794?=zj1?86=4::183!23=3;>o6Fk629K`67<,;i<6?5f6383>>o1k3:17dok:188m6>?2900c>6::188yg>2:3:197>50z&700<6=j1Ch;=4He12?!4d?380e;<50;9j2f<722cjh7>5;h1;<?6=3f9397>5;|`4gc<72<0;6=u+457950e<@m<87Ej<1:&1g2<53`<96=44i7a94?=nim0;66g<8983>>i40<0;66sm7ba94?3=83:p(9:::07`?Mb1;2Bo?<5+2b596>o1:3:17d8l:188mdb=831b?5650;9l7=3=831vn:m7:186>5<7s->?97?:c:Jg26=Ol:;0(?m8:39j27<722c=o7>5;hcg>5<<a:236=44o2:6>5<<uk=h87>55;294~"3<<0:9n5Gd718La563-8h;7<4i7094?=n>j0;66gnd;29?l5?03:17b=75;29?xd0k90;684?:1y'013=9<i0Di8<;If05>"5k>097d8=:188m3e=831bmi4?::k0<=<722e8484?::a3ge=83?1<7>t$566>43d3An=?6Fk309'6f1=:2c=>7>5;h4`>5<<ahn1<75f39:94?=h;1?1<75rb6`;>5<2290;w):;5;36g>Nc>:1Ch>?4$3a4>7=n>;0;66g9c;29?lgc2900e>67:188k6>22900qo9m4;291?6=8r.?884>5b9K`35<@m9:7)<l7;08m34=831b:n4?::kb`?6=3`9347>5;n1;1?6=3th<n=4?:483>5}#<=?1=8m4He40?Mb492.9o:4=;h41>5<<a?i1<75fae83>>o4010;66a<8483>>{e?hi1<7;50;2x 12228?h7Ej93:Jg74=#:j=1>6g92;29?l0d2900elj50;9j7=>=831d?5;50;9~f2b729096=4?{%671?51>2Bo:>5Gd238 7e028k0e?l>:188k61d2900qo9ld;296?6=8r.?884<679K`35<@m9:7)<l7;3b?l4e93:17b=8c;29?xd0k00;6?4?:1y'013=;?<0Di8<;If05>"5k>0:m6g=b083>>i4?j0;66sm7b794?4=83:p(9:::245?Mb1;2Bo?<5+2b595d=n:k;1<75`36a94?=zj>i:6=4=:183!23=39=:6Fk629K`67<,;i<6<o4i3`2>5<<g:=h6=44}c5a`?6=:3:1<v*;448023=Ol?90Di=>;%0`3?7f3`8i=7>5;n14g?6=3th<n44?:383>5}#<=?1?;84He40?Mb492.9o:4>a:k1f4<722e8;n4?::a3g3=8381<7>t$566>6013An=?6Fk309'6f1=9h1b>o?50;9l72e=831vn:l>:181>5<7s->?97=96:Jg26=Ol:;0(?m8:0c8m7d62900c>9l:188yg1fl3:1>7>50z&700<4>?1Ch;=4He12?!4d?3;j7d<m1;29?j50k3:17pl8d083>6<729q/89;5d708La043An8=6g9e;29?l5193:17b=8c;29?xd0kk0;694?:1y'013=;?n0Di8<;If05>o1m3:17dl?:188m6?52900c>8=:188yg1dm3:1?7>50z&700<c>;1Ch;=4He12?l0b2900e>8>:188k61d2900qo9l7;290?6=8r.?884<6e9K`35<@m9:7d8j:188mg6=831b?4<50;9l734=831vn:mn:180>5<7s->?97j92:Jg26=Ol:;0e;k50;9j737=831d?:m50;9~f2e4290?6=4?{%671?51l2Bo:>5Gd238m3c=831bn=4?::k0=7<722e8:?4?::a3f0=8391<7>t$566>a053An=?6Fk309j2`<722c8:<4?::m03f<722wi;oh50;694?6|,=>>6>8k;If57>Nc;81b:h4?::ka4?6=3`92>7>5;n156?6=3th<o?4?:283>5}#<=?1h;<4He40?Mb492c=i7>5;h155?6=3f9<o7>5;|`4fg<72=0;6=u+457973b<@m<87Ej<1:k5a?6=3`h;6=44i2;1>5<<g:<96=44}c5aa?6=;3:1<v*;448g27=Ol?90Di=>;h4f>5<<a:<:6=44o25`>5<<uk=i;7>54;294~"3<<08:i5Gd718La563`<n6=44ic294?=n;081<75`37094?=zj>hj6=4<:183!23=3n=>6Fk629K`67<a?o1<75f37394?=h;>i1<75rb6`0>5<3290;w):;5;15`>Nc>:1Ch>?4i7g94?=nj90;66g<9383>>i4>;0;66sm7c494?5=83:p(9:::e41?Mb1;2Bo?<5f6d83>>o4>80;66a<7b83>>{e?hl1<7:50;2x 1222:<o7Ej93:Jg74=n>l0;66gm0;29?l5>:3:17b=92;29?xd0j;0;6>4?:1y'013=l?80Di8<;If05>o1m3:17d=91;29?j50k3:17pl8ac83>1<729q/89;537f8La043An8=6g9e;29?ld72900e>7=:188k6052900qo9ne;297?6=8r.?884k639K`35<@m9:7d8j:188m6062900c>9l:188yg>6;3:197>50z&700<6=j1Ch;=4He12?!4d?380e;<50;9j2f<722cjh7>5;h1;<?6=3f9397>5;|`;55<72<0;6=u+457950e<@m<87Ej<1:&1g2<53`<96=44i7a94?=nim0;66g<8983>>i40<0;66sm81a94?3=83:p(9:::07`?Mb1;2Bo?<5+2b596>o1:3:17d8l:188mdb=831b?5650;9l7=3=831vn5>7:186>5<7s->?97?:c:Jg26=Ol:;0(?m8:39j27<722c=o7>5;hcg>5<<a:236=44o2:6>5<<uk2;87>55;294~"3<<0:9n5Gd718La563-8h;7<4i7094?=n>j0;66gnd;29?l5?03:17b=75;29?xd?890;684?:1y'013=9<i0Di8<;If05>"5k>097d8=:188m3e=831bmi4?::k0<=<722e8484?::a3ce=83?1<7>t$566>43d3An=?6Fk309'6f1=:2c=>7>5;h4`>5<<ahn1<75f39:94?=h;1?1<75rb6d;>5<2290;w):;5;36g>Nc>:1Ch>?4$3a4>7=n>;0;66g9c;29?lgc2900e>67:188k6>22900qo9i4;291?6=8r.?884>5b9K`35<@m9:7)<l7;08m34=831b:n4?::kb`?6=3`9347>5;n1;1?6=3th<j=4?:483>5}#<=?1=8m4He40?Mb492.9o:4=;h41>5<<a?i1<75fae83>>o4010;66a<8483>>{e08>1<7<50;2x 1222:<=7Ej93:Jg74=#:j=1=l5f2c394?=h;>i1<75rb932>5<5290;w):;5;152>Nc>:1Ch>?4$3a4>4g<a;h:6=44o25`>5<<uk2;h7>52;294~"3<<08:;5Gd718La563-8h;7?n;h0a5?6=3f9<o7>5;|`;4<<72;0;6=u+4579730<@m<87Ej<1:&1g2<6i2c9n<4?::m03f<722wi4=;50;094?6|,=>>6>89;If57>Nc;81/>n951`9j6g7=831d?:m50;9~f=6629096=4?{%671?51>2Bo:>5Gd238 7e028k0e?l>:188k61d2900qo9id;296?6=8r.?884<679K`35<@m9:7)<l7;3b?l4e93:17b=8c;29?xd0n00;6?4?:1y'013=;?<0Di8<;If05>"5k>0:m6g=b083>>i4?j0;66sm7g794?4=83:p(9:::245?Mb1;2Bo?<5+2b595d=n:k;1<75`36a94?=zj>l:6=4=:183!23=39=:6Fk629K`67<,;i<6<o4i3`2>5<<g:=h6=44}c:21?6=;3:1<v*;448g27=Ol?90Di=>;h4f>5<<a:<:6=44o25`>5<<uk2;j7>54;294~"3<<08:i5Gd718La563`<n6=44ic294?=n;081<75`37094?=zj1;96=4<:183!23=3n=>6Fk629K`67<a?o1<75f37394?=h;>i1<75rb92a>5<3290;w):;5;15`>Nc>:1Ch>?4i7g94?=nj90;66g<9383>>i4>;0;66sm81g94?5=83:p(9:::e41?Mb1;2Bo?<5f6d83>>o4>80;66a<7b83>>{e09=1<7:50;2x 1222:<o7Ej93:Jg74=n>l0;66gm0;29?l5>:3:17b=92;29?xd?8h0;6>4?:1y'013=l?80Di8<;If05>o1m3:17d=91;29?j50k3:17pl70283>1<729q/89;537f8La043An8=6g9e;29?ld72900e>7=:188k6052900qo6?6;297?6=8r.?884k639K`35<@m9:7d8j:188m6062900c>9l:188yg1an3:187>50z&700<4>m1Ch;=4He12?l0b2900eo>50;9j7<4=831d?;<50;9~f=6529086=4?{%671?b1:2Bo:>5Gd238m3c=831b?;?50;9l72e=831vn:hm:187>5<7s->?97=9d:Jg26=Ol:;0e;k50;9jf5<722c85?4?::m027<722wi;kk50;194?6|,=>>6i8=;If57>Nc;81b:h4?::k024<722e8;n4?::a3c1=83>1<7>t$566>60c3An=?6Fk309j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`4bd<72:0;6=u+4579`34<@m<87Ej<1:k5a?6=3`9==7>5;n14g?6=3th<j>4?:583>5}#<=?1?;j4He40?Mb492c=i7>5;h`3>5<<a:396=44o241>5<<uk=m:7>53;294~"3<<0o:?5Gd718La563`<n6=44i242>5<<g:=h6=44}c5fb?6=<3:1<v*;44802a=Ol?90Di=>;h4f>5<<ak:1<75f38094?=h;?81<75rb6d1>5<4290;w):;5;f56>Nc>:1Ch>?4i7g94?=n;?;1<75`36a94?=zj>3=6=4;:183!23=39=46Fk629K`67<,;i<6;=4i3`2>5<<a;h96=44i3`0>5<<g:=h6=44}c5:7?6=<3:1<v*;44802==Ol?90Di=>;%0`3?043`8i=7>5;h0a6?6=3`8i?7>5;n14g?6=3th<5=4?:583>5}#<=?1?;64He40?Mb492.9o:493:k1f4<722c9n?4?::k1f6<722e8;n4?::a3=b=83>1<7>t$566>60?3An=?6Fk309'6f1=>:1b>o?50;9j6g4=831b>o=50;9l72e=831vn:6n:187>5<7s->?97=98:Jg26=Ol:;0(?m8:718m7d62900e?l=:188m7d42900c>9l:188yg1??3:187>50z&700<4>11Ch;=4He12?!4d?3<87d<m1;29?l4e:3:17d<m3;29?j50k3:17pl88583>1<729q/89;537:8La043An8=6*=c6857>o5j80;66g=b383>>o5j:0;66a<7b83>>{e?1;1<7:50;2x 1222:<37Ej93:Jg74=#:j=1:>5f2c394?=n:k81<75f2c194?=h;>i1<75rb65f>5<3290;w):;5;15<>Nc>:1Ch>?4$3a4>35<a;h:6=44i3`1>5<<a;h86=44o25`>5<<uk=<n7>54;294~"3<<08:55Gd718La563-8h;78<;h0a5?6=3`8i>7>5;h0a7?6=3f9<o7>5;|`;64<72:0;6=u+4579731<@m<87Ej<1:&1g2<492.84?4k7`9j6g7=831b>o<50;9l72e=831vn5<?:180>5<7s->?97=97:Jg26=Ol:;0(?m8:238 6>52m=j7d<m1;29?l4e:3:17b=8c;29?xd0?00;654?:1y'013=;0k0Di8<;If05>"5k>087d==:188m65=831b?94?::k01?6=3`<h6=44i7d94?=nim0;66a<8483>>{e??l1<7:50;2x 12228?37Ej93:Jg74=#:j=1>6g92;29?l0d2900elj50;9l7=3=831vn:8j:187>5<7s->?97?:8:Jg26=Ol:;0(?m8:39j27<722c=o7>5;hcg>5<<g:2>6=44}c55`?6=<3:1<v*;44821==Ol?90Di=>;%0`3?4<a?81<75f6b83>>ofl3:17b=75;29?xd0>j0;694?:1y'013=9<20Di8<;If05>"5k>097d8=:188m3e=831bmi4?::m0<0<722wi;;l50;694?6|,=>>6<;7;If57>Nc;81/>n952:k56?6=3`<h6=44i`f94?=h;1?1<75rb64b>5<3290;w):;5;36<>Nc>:1Ch>?4$3a4>7=n>;0;66g9c;29?lgc2900c>6::188yg1003:187>50z&700<6=11Ch;=4He12?!4d?380e;<50;9j2f<722cjh7>5;n1;1?6=3th<;:4?:583>5}#<=?1=864He40?Mb492.9o:4=;h41>5<<a?i1<75fae83>>i40<0;66sm76494?2=83:p(9:::07;?Mb1;2Bo?<5+2b596>o1:3:17d8l:188mdb=831d?5;50;9~f212290?6=4?{%671?7202Bo:>5Gd238 7e02;1b:?4?::k5g?6=3`ko6=44o2:6>5<<uk=<87>54;294~"3<<0:955Gd718La563-8h;7<4i7094?=n>j0;66gnd;29?j5?=3:17pl87283>1<729q/89;514:8La043An8=6*=c681?l052900e;m50;9jea<722e8484?::a324=83>1<7>t$566>43?3An=?6Fk309'6f1=:2c=>7>5;h4`>5<<ahn1<75`39794?=zj>=:6=4;:183!23=3;>46Fk629K`67<,;i<6?5f6383>>o1k3:17dok:188k6>22900qo980;290?6=8r.?884>599K`35<@m9:7)<l7;08m34=831b:n4?::kb`?6=3f9397>5;|`42<<72=0;6=u+457950><@m<87Ej<1:&1g2<53`<96=44i7a94?=nim0;66a<8483>>{e?0?1<7:50;2x 12228?i7Ej93:Jg74=#:j=1>6g92;29?lgc2900e>67:188k6>22900qo967;290?6=8r.?884>5c9K`35<@m9:7)<l7;08m34=831bmi4?::k0<=<722e8484?::a3<4=83>1<7>t$566>43e3An=?6Fk309'6f1=:2c=>7>5;hcg>5<<a:236=44o2:6>5<<uk=287>54;294~"3<<0:9o5Gd718La563-8h;7<4i7094?=nim0;66g<8983>>i40<0;66sm79d94?2=83:p(9:::07a?Mb1;2Bo?<5+2b596>o1:3:17dok:188m6>?2900c>6::188yg1>93:187>50z&700<6=k1Ch;=4He12?!4d?380e;<50;9jea<722c8454?::m0<0<722wi;5m50;694?6|,=>>6<;m;If57>Nc;81/>n952:k56?6=3`ko6=44i2:;>5<<g:2>6=44}c5;a?6=<3:1<v*;44821g=Ol?90Di=>;%0`3?4<a?81<75fae83>>o4010;66a<8483>>{e?131<7:50;2x 12228?i7Ej93:Jg74=#:j=1>6g92;29?lgc2900e>67:188k6>22900qo97b;290?6=8r.?884>5c9K`35<@m9:7)<l7;08m34=831bmi4?::k0<=<722e8484?::a3=0=83>1<7>t$566>43e3An=?6Fk309'6f1=:2c=>7>5;hcg>5<<a:236=44o2:6>5<<uk=347>54;294~"3<<0:9o5Gd718La563-8h;7<4i7094?=nim0;66g<8983>>i40<0;66sm79194?2=83:p(9:::07a?Mb1;2Bo?<5+2b596>o1:3:17dok:188m6>?2900c>6::188yg1?=3:187>50z&700<6=k1Ch;=4He12?!4d?380e;<50;9jea<722c8454?::m0<0<722wi;5>50;694?6|,=>>6<;m;If57>Nc;81/>n952:k56?6=3`ko6=44i2:;>5<<g:2>6=44}c5;6?6=<3:1<v*;44821g=Ol?90Di=>;%0`3?4<a?81<75fae83>>o4010;66a<8483>>{e?>n1<7:50;2x 12228?i7Ej93:Jg74=#:j=1>6g92;29?lgc2900e>67:188k6>22900qo98f;290?6=8r.?884>5c9K`35<@m9:7)<l7;08m34=831bmi4?::k0<=<722e8484?::a32g=83>1<7>t$566>43e3An=?6Fk309'6f1=:2c=>7>5;hcg>5<<a:236=44o2:6>5<<uk=<o7>54;294~"3<<0:9o5Gd718La563-8h;7<4i7094?=nim0;66g<8983>>i40<0;66sm83094?762;0:>vFk309'013=l0=0V;?51z36>x"c;;0?8=5f2`a94?"40809mo5a39294>=n:h:1<7*<8081eg=i;1:1=65f28794?"40809mo5a39296>=n:1k1<7*<8081eg=i;1:1?65f26d94?"40809mo5a39290>=n:>>1<7*<8081eg=i;1:1965f27;94?"40809mo5a39292>=n:=31<7*<8081eg=i;1:1;65f1ec94?"40809mo5a3929<>=n9?h1<7*<8081eg=i;1:1565f8283>>o4190;66g<b283>>o4j;0;66g<b583>>i4j<0;66a=ae83>>dc><0;6<4?:1y'013=l:l0Di8<;If05>i4?l0;66sm35g94?7d2k09:vFk309'013=lh:0V;?51z3`>x"5io08:n5f3`:94?"40808m:5a39294>=n;h<1<7*<8080e2=i;1:1=65f3`794?"40808m:5a39296>=n;h>1<7*<8080e2=i;1:1?65f3`194?"40808m:5a39290>=n;h81<7*<8080e2=i;1:1965f3`394?"40808m:5a39292>=n;h:1<7*<8080e2=i;1:1;65f38d94?"40808m:5a3929<>=n;0o1<7*<8080e2=i;1:1565f3c394?"40808m:5a3929e>=n;k:1<7*<8080e2=i;1:1n65f3`d94?"40808m:5a3929g>=n;ho1<7*<8080e2=i;1:1h65f3`f94?"40808m:5a3929a>=n;hi1<7*<8080e2=i;1:1j65f3``94?"40808m:5a392955=<a:kj6=4+39397d1<f:2;6<?4;h1b=?6=,:2:6>o8;o1;4?7532c85i4?:%1;5?5f?2d84=4>3:9j<6<722c85=4?::k22d<722c8n>4?::k0f7<722c8n94?::m0f0<722e9mi4?::`g20<7280;6=u+4579`6`<@m<87Ej<1:m03`<722wih;:50;394?6|,=>>6?oj;If57>Nc;81d=;750;9~fa5b290j6=4?{%671?5>k2Bo:>5Gd238^37=9r8o6p*<908g15=#:j=186g9f;29?lgc2900e;m50;9l7=3=831d?5950;9j7f<72-93=7=m;o1;4?6<3`9j6=4+39397g=i;1:1=65f3883>!5?939i7c=70;08?l5?290/?5?53c9m7=6=;21b?:4?:%1;5?5e3g93<7:4;|`g7a<72h0;6=u+45797<e<@m<87Ej<1:X55?7|:m0v(>7>:e73?!4d?3>0e;h50;9jea<722c=o7>5;n1;1?6=3f93;7>5;h1`>5<#;1;1?o5a39294>=n;h0;6)=71;1a?k5?83;07d=6:18'7=7=;k1e?5>52:9j7=<72-93=7=m;o1;4?5<3`9<6=4+39397g=i;1:1865rbe1`>5<f290;w):;5;1:g>Nc>:1Ch>?4Z7395~4c2t.85<4k519'6f1=<2c=j7>5;hcg>5<<a?i1<75`39794?=h;1=1<75f3b83>!5?939i7c=70;28?l5f290/?5?53c9m7=6=921b?44?:%1;5?5e3g93<7<4;h1;>5<#;1;1?o5a39297>=n;>0;6)=71;1a?k5?83>07plk3c83>d<729q/89;538a8La043An8=6T91;3x6a<z,:3:6i;?;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vni=9:187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e73?l0b2900eo>50;9j7<4=831d?;<50;9~fa52290?6=4?{%671?51l2Bo:>5Gd238 6?62m?;7d8j:188mg6=831b?4<50;9l734=831vni=;:187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e73?l0b2900eo>50;9j7<4=831d?;<50;9~fa54290?6=4?{%671?51l2Bo:>5Gd238 6?62m?;7d8j:188mg6=831b?4<50;9l734=831vn>:k:187>5<7s->?97=9d:Jg26=Ol:;0(>7>:e72?l0b2900eo>50;9j7<4=831d?;<50;9~w6g?2909wS=n8:?g7`<4k2wx?l850;0xZ6g134n8i7=n;|q0e0<72;qU?l;4=e1f>6?<uz9j87>52z\0e1=:l:o1?55rs2c0>5<5sW9j?63k3d803>{t;h81<7<t^2c1?8b4l39h7p}<a083>7}Y;h;01i=k:2c8yv5f83:1>vP<a19>`6b=;01v>7i:181[5>n27o?i4<8:p7<c=838pR>7j;<f0`?503ty8n<4?:3y]7g7<5m9h6>m4}r1a4?6=:rT8n=52d2a97d=z{:km6=4={_1bb>;c;j0856s|3`g94?4|V:kn70j<c;1;?xu4im0;6?uQ3`f89a5d2:=0q~=nc;296~X4ij16h>l53b9~w6ge2909wS=nb:?g7g<4i2wx?lo50;0xZ6gf34n8n7=6;|q0e<<72;qU?l74=e1a>6><uz92h7>52z\0=a=:l:h1?:5rs2`0>5<2sW9i?63k3d85b>;c;m0=j63k3b85b>;c;k0=j6s|3c094?3|V:h970j<e;4`?8b4l3<h70j<c;4`?8b4j3<h7p}<b583>7}Y;k>01i=j:`f8yvbb?3:1>v3k3d80<0=:l:<1?4<4}rfga?6=:r7o?h4<869>`6b=im1vik9:1818b4l393963k3480=7=z{mno6=4={<f0`?5??27o?n4nd:p``3=838p1i=l:2:6?8b4<392>6s|dea94?4|5m9h6>68;<f0f?gc3tyoi94?:3y>`6d=;1?01i=<:2;1?xu4j<0;6?uQ3c789a5e2:2<7p}ke383>7}:l:<1?;<4=26g>3c<uznn=7>52z?g73<1m27o?84<639~wac72909w0j<5;4f?8b4<39=>6s|ded94?4|5m9?6;k4=e10>6053ty9mi4?:3y]6db<5:>o6>8=;|q22d<72:q6h;;536g89a542?o01>:k:2;1?xu4?:0;6;u2d76953?<5m9=6o>4=e16>g6<5m9?6o>4=e10>g6<5:>o6o>4}|q1ef<72;qU>lm4=26f>6d63ty9m=4?:3y]6d6<5:>n6>l?;|q1=0<72;qU>4;4=26f>6ga3ty94l4?:3y]6=g<5:>n6>oj;|q13c<72;qU>:h4=26f>6gc3ty9;94?:3y]622<5:>n6>ol;|q12<<72;qU>;74=26f>6ge3ty9844?:3y]61?<5:>n6>on;|q2`d<72;qU=io4=26f>6g>3ty::o4?:3y]53d<5:>n6>7k;|q;7?6=:rT3?63<4d8;7>{t;0:1<7<t^2;3?853m392<6s|3c194?4|V:h870=;e;1a7>{t;k81<7<t^2`1?853m39i>6s|3c694?4|V:h?70=;e;1a0>{t;k?1<7<t^2`6?853m39i96s|2`f94?4|V;ko70=;e;0b`>{tlk21<7mt=e46>61b349?i7=n8:?00`<4i?16?9k53`78962b2:k?70=;e;1b7>;4<l08m?5235g97d7<5:>n6>o?;<17a?5>n2788h4<9d9>71c=9?k0qpl72283>47=:3;9wEj<1:&700<c1>1Q:<4>{079y!b4:3>?<6g=ab83>!5?938jn6`<8183?>o5i90;6)=71;0bf>h4090:76g=9483>!5?938jn6`<8181?>o50h0;6)=71;0bf>h4090876g=7g83>!5?938jn6`<8187?>o5?=0;6)=71;0bf>h4090>76g=6883>!5?938jn6`<8185?>o5<00;6)=71;0bf>h4090<76g>d`83>!5?938jn6`<818;?>o6>k0;6)=71;0bf>h4090276g73;29?l5>83:17d=m3;29?l5e:3:17d=m4;29?j5e=3:17b<nd;29?gb1=3:1=7>50z&700<c;o1Ch;=4He12?j50m3:17pl<4d83>4e=j38=wEj<1:&700<ci91Q:<4>{0a9y!4fn39=o6g<a983>!5?939j;6`<8183?>o4i?0;6)=71;1b3>h4090:76g<a483>!5?939j;6`<8181?>o4i=0;6)=71;1b3>h4090876g<a283>!5?939j;6`<8187?>o4i;0;6)=71;1b3>h4090>76g<a083>!5?939j;6`<8185?>o4i90;6)=71;1b3>h4090<76g<9g83>!5?939j;6`<818;?>o41l0;6)=71;1b3>h4090276g<b083>!5?939j;6`<818b?>o4j90;6)=71;1b3>h4090i76g<ag83>!5?939j;6`<818`?>o4il0;6)=71;1b3>h4090o76g<ae83>!5?939j;6`<818f?>o4ij0;6)=71;1b3>h4090m76g<ac83>!5?939j;6`<81824>=n;hk1<7*<8080e2=i;1:1=<54i2c:>5<#;1;1?l94n2:3>44<3`92h7>5$2:2>6g03g93<7?<;:k;7?6=3`92<7>5;h35e?6=3`9i?7>5;h1a6?6=3`9i87>5;n1a1?6=3f8jh7>5;cf51?6=93:1<v*;448g7c=Ol?90Di=>;n14a?6=3tho:94?:083>5}#<=?1>lk4He40?Mb492e::44?::a`6c=83k1<7>t$566>6?d3An=?6Fk309Y24<6s;n1q)=61;f64>"5k>0?7d8i:188mdb=831b:n4?::m0<0<722e84:4?::k0g?6=,:2:6>l4n2:3>5=<a:k1<7*<8080f>h4090:76g<9;29 6>62:h0b>6?:398m6>=83.84<4<b:l0<5<432c8;7>5$2:2>6d<f:2;6954}cf0`?6=i3:1<v*;4480=f=Ol?90Di=>;[42>4}5l3w/?4?5d428 7e02=1b:k4?::kb`?6=3`<h6=44o2:6>5<<g:2<6=44i2a94?"40808n6`<8183?>o4i3:1(>6>:2`8j6>72810e>750;&0<4<4j2d84=4=;:k0<?6=,:2:6>l4n2:3>6=<a:=1<7*<8080f>h4090?76smd2a94?g=83:p(9:::2;`?Mb1;2Bo?<5U60827b=u-92=7j:0:&1g2<33`<m6=44i`f94?=n>j0;66a<8483>>i40>0;66g<c;29 6>62:h0b>6?:198m6g=83.84<4<b:l0<5<632c857>5$2:2>6d<f:2;6?54i2:94?"40808n6`<8180?>o4?3:1(>6>:2`8j6>72=10qoj<b;29e?6=8r.?884<9b9K`35<@m9:7W8>:0y1`?{#;0;1h8>4$3a4>1=n>o0;66gnd;29?l0d2900c>6::188k6>02900e>m50;&0<4<4j2d84=4?;:k0e?6=,:2:6>l4n2:3>4=<a:31<7*<8080f>h4090976g<8;29 6>62:h0b>6?:298m61=83.84<4<b:l0<5<332wih>850;694?6|,=>>6>8k;If57>Nc;81/?4?5d428m3c=831bn=4?::k0=7<722e8:?4?::a`63=83>1<7>t$566>60c3An=?6Fk309'7<7=l<:0e;k50;9jf5<722c85?4?::m027<722wih>:50;694?6|,=>>6>8k;If57>Nc;81/?4?5d428m3c=831bn=4?::k0=7<722e8:?4?::a`65=83>1<7>t$566>60c3An=?6Fk309'7<7=l<:0e;k50;9jf5<722c85?4?::m027<722wi?9j50;694?6|,=>>6>8k;If57>Nc;81/?4?5d438m3c=831bn=4?::k0=7<722e8:?4?::p7d>=838pR>o7;<f0a?5d3ty8m;4?:3y]7d0<5m9n6>o4}r1b1?6=:rT8m852d2g97<=z{:k?6=4={_1b0>;c;l0846s|3`194?4|V:k870j<e;14?xu4i;0;6?uQ3`089a5c2:i0q~=n1;296~X4i816h>j53`9~w6g72909wS=n0:?g7a<412wx?4h50;0xZ6?a34n8h7=7;|q0=`<72;qU?4k4=e1g>61<uz9i=7>52z\0f4=:l:i1?n5rs2`3>5<5sW9i<63k3b80e>{t;hl1<7<t^2ce?8b4k3927p}<ad83>7}Y;ho01i=l:2:8yv5fl3:1>vP<ae9>`6e=;>1v>ol:181[5fk27o?o4<c:p7dd=838pR>om;<f0f?5f3ty8ml4?:3y]7dg<5m9i6>74}r1b=?6=:rT8m452d2`97==z{:3o6=4={_1:`>;c;k08;6s|3c194?3|V:h870j<e;4e?8b4l3<m70j<c;4e?8b4j3<m7p}<b383>0}Y;k801i=j:7a89a5c2?i01i=l:7a89a5e2?i0q~=m4;296~X4j=16h>k5ae9~wac02909w0j<e;1;1>;c;?085?5rseff>5<5s4n8i7=77:?g7a<fl2wxhh850;0x9a5c2:2>70j<5;1:6>{tlmn1<7<t=e1g>6>034n8o7ok;|qga0<72;q6h>m539789a532:397p}kdb83>7}:l:i1?594=e1a>db<uznn87>52z?g7g<40<16h>=53808yv5e=3:1>vP<b49>`6d=;1=0q~jj2;296~;c;?08:?5235f92`=z{mo:6=4={<f02?0b34n897=92:p``6=838p1i=::7g89a532:<97p}kdg83>7}:l:>1:h52d219734<uz8jh7>52z\1ea=:;=n1?;<4}r35e?6=;r7o:84<7d9>`65=>l16?9j53808yv50;3:1:v3k65822<=:l:<1n=52d279f5=:l:>1n=52d219f5=:;=n1n=5r}r0bg?6=:rT9mn5235g97g7<uz8j<7>52z\1e5=:;=o1?o>4}r0:1?6=:rT9585235g97d`<uz83m7>52z\1<d=:;=o1?lk4}r04b?6=:rT9;k5235g97db<uz8<87>52z\131=:;=o1?lm4}r05=?6=:rT9:45235g97dd<uz8?57>52z\10<=:;=o1?lo4}r3ge?6=:rT:hl5235g97d?<uz;=n7>52z\22g=:;=o1?4j4}r:0>5<5sW2870=;e;:0?xu4190;6?uQ3828962b2:3;7p}<b283>7}Y;k901>:j:2`0?xu4j;0;6?uQ3c08962b2:h97p}<b583>7}Y;k>01>:j:2`7?xu4j<0;6?uQ3c78962b2:h>7p}=ae83>7}Y:hn01>:j:3cg?xucj10;6nu2d77972c<5:>n6>o7;<17a?5f>2788h4<a49>71c=;h>01>:j:2c0?853m39j>63<4d80e4=:;=o1?l>4=26f>6?a349?i7=6e:?00`<6>h1vqo6=4;2954<5288pDi=>;%671?b>?2P==7?t148~ a552=>;7d<nc;29 6>62;ki7c=70;28?l4f83:1(>6>:3ca?k5?83;07d<65;29 6>62;ki7c=70;08?l4?i3:1(>6>:3ca?k5?83907d<8f;29 6>62;ki7c=70;68?l40<3:1(>6>:3ca?k5?83?07d<99;29 6>62;ki7c=70;48?l4313:1(>6>:3ca?k5?83=07d?ka;29 6>62;ki7c=70;:8?l71j3:1(>6>:3ca?k5?83307d6<:188m6?72900e>l<:188m6d52900e>l;:188k6d22900c?ok:188fa02290:6=4?{%671?b4n2Bo:>5Gd238k61b2900qo=;e;295f<e2;<pDi=>;%671?bf82P==7?t1b8~ 7ga2:<h7d=n8;29 6>62:k<7c=70;28?l5f>3:1(>6>:2c4?k5?83;07d=n5;29 6>62:k<7c=70;08?l5f<3:1(>6>:2c4?k5?83907d=n3;29 6>62:k<7c=70;68?l5f:3:1(>6>:2c4?k5?83?07d=n1;29 6>62:k<7c=70;48?l5f83:1(>6>:2c4?k5?83=07d=6f;29 6>62:k<7c=70;:8?l5>m3:1(>6>:2c4?k5?83307d=m1;29 6>62:k<7c=70;c8?l5e83:1(>6>:2c4?k5?83h07d=nf;29 6>62:k<7c=70;a8?l5fm3:1(>6>:2c4?k5?83n07d=nd;29 6>62:k<7c=70;g8?l5fk3:1(>6>:2c4?k5?83l07d=nb;29 6>62:k<7c=70;33?>o4ih0;6)=71;1b3>h4090:=65f3`;94?"40808m:5a392957=<a:3o6=4+39397d1<f:2;6<=4;h:0>5<<a:3;6=44i04b>5<<a:h86=44i2`1>5<<a:h?6=44o2`6>5<<g;ko6=44be46>5<6290;w):;5;f0b>Nc>:1Ch>?4o25f>5<<ukn=87>51;294~"3<<09mh5Gd718La563f;=57>5;|`g7`<72h0;6=u+45797<e<@m<87Ej<1:X55?7|:m0v(>7>:e73?!4d?3>0e;h50;9jea<722c=o7>5;n1;1?6=3f93;7>5;h1`>5<#;1;1?o5a39294>=n;h0;6)=71;1a?k5?83;07d=6:18'7=7=;k1e?5>52:9j7=<72-93=7=m;o1;4?5<3`9<6=4+39397g=i;1:1865rbe1g>5<f290;w):;5;1:g>Nc>:1Ch>?4Z7395~4c2t.85<4k519'6f1=<2c=j7>5;hcg>5<<a?i1<75`39794?=h;1=1<75f3b83>!5?939i7c=70;28?l5f290/?5?53c9m7=6=921b?44?:%1;5?5e3g93<7<4;h1;>5<#;1;1?o5a39297>=n;>0;6)=71;1a?k5?83>07plk3b83>d<729q/89;538a8La043An8=6T91;3x6a<z,:3:6i;?;%0`3?2<a?l1<75fae83>>o1k3:17b=75;29?j5??3:17d=l:18'7=7=;k1e?5>50:9j7d<72-93=7=m;o1;4?7<3`926=4+39397g=i;1:1>65f3983>!5?939i7c=70;18?l50290/?5?53c9m7=6=<21vni=m:18b>5<7s->?97=6c:Jg26=Ol:;0V;?51z0g>x"4180o9=5+2b590>o1n3:17dok:188m3e=831d?5;50;9l7=1=831b?n4?:%1;5?5e3g93<7>4;h1b>5<#;1;1?o5a39295>=n;00;6)=71;1a?k5?83807d=7:18'7=7=;k1e?5>53:9j72<72-93=7=m;o1;4?2<3tho?;4?:583>5}#<=?1?;j4He40?Mb492.85<4k519j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`g70<72=0;6=u+457973b<@m<87Ej<1:&0=4<c=91b:h4?::ka4?6=3`92>7>5;n156?6=3tho?94?:583>5}#<=?1?;j4He40?Mb492.85<4k519j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`g76<72=0;6=u+457973b<@m<87Ej<1:&0=4<c=91b:h4?::ka4?6=3`92>7>5;n156?6=3th88i4?:583>5}#<=?1?;j4He40?Mb492.85<4k509j2`<722ci<7>5;h1:6?6=3f9=>7>5;|q0e=<72;qU?l64=e1f>6e<uz9j:7>52z\0e3=:l:o1?l5rs2c6>5<5sW9j963k3d80=>{t;h>1<7<t^2c7?8b4m3937p}<a283>7}Y;h901i=j:258yv5f:3:1>vP<a39>`6b=;j1v>o>:181[5f927o?i4<a:p7d6=838pR>o?;<f0`?5>3ty85k4?:3y]7<`<5m9o6>64}r1:a?6=:rT85h52d2f972=z{:h:6=4={_1a5>;c;j08o6s|3c294?4|V:h;70j<c;1b?xu4io0;6?uQ3`d89a5d2:30q~=ne;296~X4il16h>m5399~w6gc2909wS=nd:?g7f<4?2wx?lm50;0xZ6gd34n8n7=l;|q0eg<72;qU?ll4=e1a>6g<uz9jm7>52z\0ed=:l:h1?45rs2c:>5<5sW9j563k3c80<>{t;0n1<7<t^2;g?8b4j39<7p}<b283>0}Y;k901i=j:7d89a5c2?l01i=l:7d89a5e2?l0q~=m2;291~X4j;16h>k56b9>`6b=>j16h>m56b9>`6d=>j1v>l;:181[5e<27o?h4nd:p``1=838p1i=j:2:6?8b4>392>6s|deg94?4|5m9n6>68;<f0`?gc3tyoi;4?:3y>`6b=;1?01i=::2;1?xuclm0;6?u2d2f97=1<5m9h6lj4}rff1?6=:r7o?n4<849>`62=;080q~jkc;296~;c;j084:52d2`9ea=z{mo?6=4={<f0f?5?=27o?>4<939~w6d22909wS=m5:?g7g<40>1vik=:1818b4>39=>63<4e85a>{tll;1<7<t=e15>3c<5m9>6>8=;|qga5<72;q6h>;56d9>`62=;?80q~jkf;296~;c;=0=i63k328027=z{;ko6=4={_0b`>;4<m08:?5rs04b>5<4s4n=97=8e:?g76<1m2788i4<939~w614290=w0j94;35=>;c;?0i<63k348a4>;c;=0i<63k328a4>;4<m0i<6srs3c`>5<5sW8jo63<4d80f4=z{;k;6=4={_0b4>;4<l08n=5rs3;6>5<5sW82963<4d80ec=z{;2j6=4={_0;e>;4<l08mh5rs35e>5<5sW8<j63<4d80ea=z{;=?6=4={_040>;4<l08mn5rs34:>5<5sW8=563<4d80eg=z{;>26=4={_07=>;4<l08ml5rs0fb>5<5sW;om63<4d80e<=z{8<i6=4={_35f>;4<l085i5rs9194?4|V1901>:j:918yv5>83:1>vP<919>71c=;0:0q~=m3;296~X4j:16?9k53c18yv5e:3:1>vP<b39>71c=;k80q~=m4;296~X4j=16?9k53c68yv5e=3:1>vP<b49>71c=;k?0q~<nd;296~X5im16?9k52`f8yvbe03:1ov3k64803`=:;=o1?l64=26f>6g1349?i7=n5:?00`<4i=16?9k53`18962b2:k970=;e;1b5>;4<l08m=5235g97<`<5:>n6>7j;<17a?71i2wvn;>j:184>5<7s->?97=9b:Jg26=Ol:;0(?m8:99j6g7=831b>o<50;9j6g5=831b>o:50;9j6g3=831b>o850;9l72e=831vn;:=:180>5<7s->?97=97:Jg26=Ol:;0(?m8:06`?l4e93:17d<m2;29?j50k3:17pl90g83>7<729q/89;53748La043An8=6*=c682e>o5j80;66a<7b83>>{e>9n1<7=50;2x 1222:<<7Ej93:Jg74=#:j=1?<5f2c394?=n:k81<75`36a94?=zj<i26=48:183!23=39=n6Fk629K`67<,;i<6:5f2c394?=n:k81<75f2c194?=n:k>1<75f2c794?=n:k<1<75`36a94?=zj?:h6=4<:183!23=39=;6Fk629K`67<,;i<6<:l;%1;6?b0>2c9n<4?::k1f7<722e8;n4?::a1fg=8391<7>t$566>6003An=?6Fk309'6f1=:=1b>o?50;9j6g4=831d?:m50;9~f0e?29086=4?{%671?51?2Bo:>5Gd238 7e02:;0e?l>:188m7d52900c>9l:188yg3d>3:1?7>50z&700<4>>1Ch;=4He12?!4d?3;?o6g=b083>>o5j;0;66a<7b83>>{e=j=1<7=50;2x 1222:<<7Ej93:Jg74=#:j=1=9m4$2:1>a113`8i=7>5;h0a6?6=3f9<o7>5;|`523<72>0;6=u+457973d<@m<87Ej<1:&1g2<a3`8i=7>5;h0a6?6=3`8i?7>5;h0a0?6=3`8i97>5;h0a2?6=3f9<o7>5;|`50`<72>0;6=u+457973d<@m<87Ej<1:&1g2<a3`8i=7>5;h0a6?6=3`8i?7>5;h0a0?6=3`8i97>5;h0a2?6=3f9<o7>5;|`515<72>0;6=u+457973d<@m<87Ej<1:&1g2<a3`8i=7>5;h0a6?6=3`8i?7>5;h0a0?6=3`8i97>5;h0a2?6=3f9<o7>5;|`514<72>0;6=u+457973d<@m<87Ej<1:&1g2<a3`8i=7>5;h0a6?6=3`8i?7>5;h0a0?6=3`8i97>5;h0a2?6=3f9<o7>5;|`517<72>0;6=u+457973d<@m<87Ej<1:&1g2<a3`8i=7>5;h0a6?6=3`8i?7>5;h0a0?6=3`8i97>5;h0a2?6=3f9<o7>5;|`510<72>0;6=u+457973d<@m<87Ej<1:&1g2<a3`8i=7>5;h0a6?6=3`8i?7>5;h0a0?6=3`8i97>5;h0a2?6=3f9<o7>5;|`520<72>0;6=u+457973d<@m<87Ej<1:&1g2<6==1b>o?50;9j6g4=831b>o=50;9j6g2=831b>o;50;9j6g0=831d?:m50;9~f334290<6=4?{%671?51j2Bo:>5Gd238 7e02o1b>o?50;9j6g4=831b>o=50;9j6g2=831b>o;50;9j6g0=831d?:m50;9~f331290<6=4?{%671?51j2Bo:>5Gd238 7e02o1b>o?50;9j6g4=831b>o=50;9j6g2=831b>o;50;9j6g0=831d?:m50;9~f330290<6=4?{%671?51j2Bo:>5Gd238 7e02o1b>o?50;9j6g4=831b>o=50;9j6g2=831b>o;50;9j6g0=831d?:m50;9~f33e290<6=4?{%671?51j2Bo:>5Gd238 7e02o1b>o?50;9j6g4=831b>o=50;9j6g2=831b>o;50;9j6g0=831d?:m50;9~f300290<6=4?{%671?51j2Bo:>5Gd238 7e028??7d<m1;29?l4e:3:17d<m3;29?l4e<3:17d<m5;29?l4e>3:17b=8c;29?xd1==0;6:4?:1y'013=;?h0Di8<;If05>"5k>0m7d<m1;29?l4e:3:17d<m3;29?l4e<3:17d<m5;29?l4e>3:17b=8c;29?xd1=10;6:4?:1y'013=;?h0Di8<;If05>"5k>0m7d<m1;29?l4e:3:17d<m3;29?l4e<3:17d<m5;29?l4e>3:17b=8c;29?xd1=00;6:4?:1y'013=;?h0Di8<;If05>"5k>0m7d<m1;29?l4e:3:17d<m3;29?l4e<3:17d<m5;29?l4e>3:17b=8c;29?xd1=j0;6:4?:1y'013=;?h0Di8<;If05>"5k>0m7d<m1;29?l4e:3:17d<m3;29?l4e<3:17d<m5;29?l4e>3:17b=8c;29?xd1>10;6:4?:1y'013=;?h0Di8<;If05>"5k>0:995f2c394?=n:k81<75f2c194?=n:k>1<75f2c794?=n:k<1<75`36a94?=zj??j6=48:183!23=39=n6Fk629K`67<,;i<6k5f2c394?=n:k81<75f2c194?=n:k>1<75f2c794?=n:k<1<75`36a94?=zj??o6=48:183!23=39=n6Fk629K`67<,;i<6k5f2c394?=n:k81<75f2c194?=n:k>1<75f2c794?=n:k<1<75`36a94?=zj??n6=48:183!23=39=n6Fk629K`67<,;i<6k5f2c394?=n:k81<75f2c194?=n:k>1<75f2c794?=n:k<1<75`36a94?=zj??m6=48:183!23=39=n6Fk629K`67<,;i<6k5f2c394?=n:k81<75f2c194?=n:k>1<75f2c794?=n:k<1<75`36a94?=zj?>m6=48:183!23=39=n6Fk629K`67<,;i<6<;;;h0a5?6=3`8i>7>5;h0a7?6=3`8i87>5;h0a1?6=3`8i:7>5;n14g?6=3th=:=4?:583>5}#<=?1?;k4He40?Mb492c9n<4?::k1f7<722c85?4?::m03f<722wi:9750;794?6|,=>>6<;l;If57>Nc;81/>n952:k56?6=3`<h6=44i`f94?=n;121<75`39794?=zj?>36=4::183!23=3;>o6Fk629K`67<,;i<6?5f6383>>o1k3:17dok:188m6>?2900c>6::188yg03?3:197>50z&700<6=j1Ch;=4He12?!4d?380e;<50;9j2f<722cjh7>5;h1;<?6=3f9397>5;|`503<72<0;6=u+457950e<@m<87Ej<1:&1g2<53`<96=44i7a94?=nim0;66g<8983>>i40<0;66sm65794?3=83:p(9:::07`?Mb1;2Bo?<5+2b596>o1:3:17d8l:188mdb=831b?5650;9l7=3=831vn;:;:186>5<7s->?97?:c:Jg26=Ol:;0(?m8:39j27<722c=o7>5;hcg>5<<a:236=44o2:6>5<<uk<??7>55;294~"3<<0:9n5Gd718La563-8h;7<4i7094?=n>j0;66gnd;29?l5?03:17b=75;29?xd1080;6>4?:1y'013=l?80Di8<;If05>o1m3:17d=91;29?j50k3:17pl97d83>1<729q/89;537f8La043An8=6g9e;29?ld72900e>7=:188k6052900qo878;297?6=8r.?884k639K`35<@m9:7d8j:188m6062900c>9l:188yg0?=3:187>50z&700<4>m1Ch;=4He12?l0b2900eo>50;9j7<4=831d?;<50;9~f3>d29086=4?{%671?b1:2Bo:>5Gd238m3c=831b?;?50;9l72e=831vn;66:187>5<7s->?97=9d:Jg26=Ol:;0e;k50;9jf5<722c85?4?::m027<722wi:4>50;194?6|,=>>6i8=;If57>Nc;81b:h4?::k024<722e8;n4?::a2=b=83>1<7>t$566>60c3An=?6Fk309j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`5=1<72:0;6=u+4579`34<@m<87Ej<1:k5a?6=3`9==7>5;n14g?6=3th=5<4?:583>5}#<=?1?;j4He40?Mb492c=i7>5;h`3>5<<a:396=44o241>5<<uk<247>53;294~"3<<0o:?5Gd718La563`<n6=44i242>5<<g:=h6=44}c4:1?6=<3:1<v*;44802a=Ol?90Di=>;h4f>5<<ak:1<75f38094?=h;?81<75rb7;`>5<4290;w):;5;f56>Nc>:1Ch>?4i7g94?=n;?;1<75`36a94?=zj?326=4;:183!23=39=h6Fk629K`67<a?o1<75fb183>>o41;0;66a<6383>>{e>h:1<7=50;2x 1222m<97Ej93:Jg74=n>l0;66g<6083>>i4?j0;66sm68f94?2=83:p(9:::24g?Mb1;2Bo?<5f6d83>>oe83:17d=62;29?j51:3:17pl9a583>6<729q/89;5d708La043An8=6g9e;29?l5193:17b=8c;29?xd1i80;694?:1y'013=;?n0Di8<;If05>o1m3:17dl?:188m6?52900c>8=:188yg0f03:1?7>50z&700<c>;1Ch;=4He12?l0b2900e>8>:188k61d2900qo8n5;290?6=8r.?884<6e9K`35<@m9:7d8j:188mg6=831b?4<50;9l734=831vn;6;:180>5<7s->?97j92:Jg26=Ol:;0e;k50;9j737=831d?:m50;9~f3>729096=4?{%671?51>2Bo:>5Gd238 7e028k0e?l>:188k61d2900qo877;296?6=8r.?884<679K`35<@m9:7)<l7;3b?l4e93:17b=8c;29?xd10k0;6?4?:1y'013=;?<0Di8<;If05>"5k>0:m6g=b083>>i4?j0;66sm69d94?4=83:p(9:::245?Mb1;2Bo?<5+2b595d=n:k;1<75`36a94?=zj?386=4=:183!23=39=:6Fk629K`67<,;i<6<o4i3`2>5<<g:=h6=44}c4:3?6=:3:1<v*;448023=Ol?90Di=>;%0`3?7f3`8i=7>5;n14g?6=3th=5o4?:383>5}#<=?1?;84He40?Mb492.9o:4>a:k1f4<722e8;n4?::a2<`=8381<7>t$566>6013An=?6Fk309'6f1=9h1b>o?50;9l72e=831vn;o<:181>5<7s->?97=96:Jg26=Ol:;0(?m8:0c8m7d62900c>9l:188yg0f?3:1>7>50z&700<4>?1Ch;=4He12?!4d?3;j7d<m1;29?j50k3:17pl98283>7<729q/89;53748La043An8=6*=c682e>o5j80;66a<7b83>>{e>>l1<7;50;2x 12228?h7Ej93:Jg74=#:j=1>6g92;29?l0d2900elj50;9j7=>=831d?5;50;9~f3>1290>6=4?{%671?72k2Bo:>5Gd238 7e02;1b:?4?::k5g?6=3`ko6=44i2:;>5<<g:2>6=44}c4;e?6==3:1<v*;44821f=Ol?90Di=>;%0`3?4<a?81<75f6b83>>ofl3:17d=78;29?j5?=3:17pl98d83>0<729q/89;514a8La043An8=6*=c681?l052900e;m50;9jea<722c8454?::m0<0<722wi:4<50;794?6|,=>>6<;l;If57>Nc;81/>n952:k56?6=3`<h6=44i`f94?=n;121<75`39794?=zj?3=6=4::183!23=3;>o6Fk629K`67<,;i<6?5f6383>>o1k3:17dok:188m6>?2900c>6::188yg0>i3:197>50z&700<6=j1Ch;=4He12?!4d?380e;<50;9j2f<722cjh7>5;h1;<?6=3f9397>5;|`5=`<72<0;6=u+457950e<@m<87Ej<1:&1g2<53`<96=44i7a94?=nim0;66g<8983>>i40<0;66sm6`094?3=83:p(9:::07`?Mb1;2Bo?<5+2b596>o1:3:17d8l:188mdb=831b?5650;9l7=3=831vn;o9:186>5<7s->?97?:c:Jg26=Ol:;0(?m8:39j27<722c=o7>5;hcg>5<<a:236=44o2:6>5<<uk<3>7>55;294~"3<<0:9n5Gd718La563-8h;7<4i7094?=n>j0;66gnd;29?l5?03:17b=75;29?xd2m10;6>4?:1y'013=l?80Di8<;If05>o1m3:17d=91;29?j50k3:17pl:e483>1<729q/89;537f8La043An8=6g9e;29?ld72900e>7=:188k6052900qo;jc;297?6=8r.?884k639K`35<@m9:7d8j:188m6062900c>9l:188yg3b13:187>50z&700<4>m1Ch;=4He12?l0b2900eo>50;9j7<4=831d?;<50;9~f0`729086=4?{%671?b1:2Bo:>5Gd238m3c=831b?;?50;9l72e=831vn8kk:187>5<7s->?97=9d:Jg26=Ol:;0e;k50;9jf5<722c85?4?::m027<722wi9k:50;194?6|,=>>6i8=;If57>Nc;81b:h4?::k024<722e8;n4?::a1c7=83>1<7>t$566>60c3An=?6Fk309j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`6b=<72:0;6=u+4579`34<@m<87Ej<1:k5a?6=3`9==7>5;n14g?6=3th>j84?:583>5}#<=?1?;j4He40?Mb492c=i7>5;h`3>5<<a:396=44o241>5<<uk?mo7>53;294~"3<<0o:?5Gd718La563`<n6=44i242>5<<g:=h6=44}c7e=?6=<3:1<v*;44802a=Ol?90Di=>;h4f>5<<ak:1<75f38094?=h;?81<75rb723>5<4290;w):;5;f56>Nc>:1Ch>?4i7g94?=n;?;1<75`36a94?=zj<lo6=4;:183!23=39=h6Fk629K`67<a?o1<75fb183>>o41;0;66a<6383>>{e>991<7=50;2x 1222m<97Ej93:Jg74=n>l0;66g<6083>>i4?j0;66sm5d594?4=83:p(9:::245?Mb1;2Bo?<5+2b595d=n:k;1<75`36a94?=zj<oi6=4=:183!23=39=:6Fk629K`67<,;i<6<o4i3`2>5<<g:=h6=44}c7fb?6=:3:1<v*;448023=Ol?90Di=>;%0`3?7f3`8i=7>5;n14g?6=3th>j>4?:383>5}#<=?1?;84He40?Mb492.9o:4>a:k1f4<722e8;n4?::a1c1=8381<7>t$566>6013An=?6Fk309'6f1=9h1b>o?50;9l72e=831vn8hm:181>5<7s->?97=96:Jg26=Ol:;0(?m8:0c8m7d62900c>9l:188yg3an3:1>7>50z&700<4>?1Ch;=4He12?!4d?3;j7d<m1;29?j50k3:17pl90383>7<729q/89;53748La043An8=6*=c682e>o5j80;66a<7b83>>{e=l<1<7;50;2x 12228?h7Ej93:Jg74=#:j=1>6g92;29?l0d2900elj50;9j7=>=831d?5;50;9~f0cf290>6=4?{%671?72k2Bo:>5Gd238 7e02;1b:?4?::k5g?6=3`ko6=44i2:;>5<<g:2>6=44}c7fa?6==3:1<v*;44821f=Ol?90Di=>;%0`3?4<a?81<75f6b83>>ofl3:17d=78;29?j5?=3:17pl:f383>0<729q/89;514a8La043An8=6*=c681?l052900e;m50;9jea<722c8454?::m0<0<722wi9k850;794?6|,=>>6<;l;If57>Nc;81/>n952:k56?6=3`<h6=44i`f94?=n;121<75`39794?=zj<lj6=4::183!23=3;>o6Fk629K`67<,;i<6?5f6383>>o1k3:17dok:188m6>?2900c>6::188yg3am3:197>50z&700<6=j1Ch;=4He12?!4d?380e;<50;9j2f<722cjh7>5;h1;<?6=3f9397>5;|`544<72<0;6=u+457950e<@m<87Ej<1:&1g2<53`<96=44i7a94?=nim0;66g<8983>>i40<0;66sm63194?5=83:p(9:::e41?Mb1;2Bo?<5f6d83>>o4>80;66a<7b83>>{e>;:1<7:50;2x 1222:<o7Ej93:Jg74=n>l0;66gm0;29?l5>:3:17b=92;29?xd1:>0;6>4?:1y'013=l?80Di8<;If05>o1m3:17d=91;29?j50k3:17pl92583>1<729q/89;537f8La043An8=6g9e;29?ld72900e>7=:188k6052900qo8=b;297?6=8r.?884k639K`35<@m9:7d8j:188m6062900c>9l:188yg0503:187>50z&700<4>m1Ch;=4He12?l0b2900eo>50;9j7<4=831d?;<50;9~f34a29086=4?{%671?b1:2Bo:>5Gd238m3c=831b?;?50;9l72e=831vn;<l:187>5<7s->?97=9d:Jg26=Ol:;0e;k50;9jf5<722c85?4?::m027<722wi:>=50;194?6|,=>>6i8=;If57>Nc;81b:h4?::k024<722e8;n4?::a266=83>1<7>t$566>60c3An=?6Fk309j2`<722ci<7>5;h1:6?6=3f9=>7>5;|`572<72:0;6=u+4579`34<@m<87Ej<1:k5a?6=3`9==7>5;n14g?6=3th=?94?:583>5}#<=?1?;j4He40?Mb492c=i7>5;h`3>5<<a:396=44o241>5<<uk<8m7>53;294~"3<<0o:?5Gd718La563`<n6=44i242>5<<g:=h6=44}c416?6=:3:1<v*;448023=Ol?90Di=>;%0`3?7f3`8i=7>5;n14g?6=3th=>;4?:383>5}#<=?1?;84He40?Mb492.9o:4>a:k1f4<722e8;n4?::a27g=8381<7>t$566>6013An=?6Fk309'6f1=9h1b>o?50;9l72e=831vn;<j:181>5<7s->?97=96:Jg26=Ol:;0(?m8:0c8m7d62900c>9l:188yg04:3:1>7>50z&700<4>?1Ch;=4He12?!4d?3;j7d<m1;29?j50k3:17pl93783>7<729q/89;53748La043An8=6*=c682e>o5j80;66a<7b83>>{e>:31<7<50;2x 1222:<=7Ej93:Jg74=#:j=1=l5f2c394?=h;>i1<75rb702>5<2290;w):;5;36g>Nc>:1Ch>?4$3a4>7=n>;0;66g9c;29?lgc2900e>67:188k6>22900qo8=5;291?6=8r.?884>5b9K`35<@m9:7)<l7;08m34=831b:n4?::kb`?6=3`9347>5;n1;1?6=3th=>44?:483>5}#<=?1=8m4He40?Mb492.9o:4=;h41>5<<a?i1<75fae83>>o4010;66a<8483>>{e>;n1<7;50;2x 12228?h7Ej93:Jg74=#:j=1>6g92;29?l0d2900elj50;9j7=>=831d?5;50;9~f356290>6=4?{%671?72k2Bo:>5Gd238 7e02;1b:?4?::k5g?6=3`ko6=44i2:;>5<<g:2>6=44}c401?6==3:1<v*;44821f=Ol?90Di=>;%0`3?4<a?81<75f6b83>>ofl3:17d=78;29?j5?=3:17pl93983>0<729q/89;514a8La043An8=6*=c681?l052900e;m50;9jea<722c8454?::m0<0<722wi4n=50;694?6|,=>>6>87;If57>Nc;81/>n9515f8m7d62900e?l=:188m7d42900c>9l:188yg>a93:1?7>50z&700<4>>1Ch;=4He12?!4d?3;j7)=72;f4=>o5j80;66g=b383>>i4?j0;66sm8ga94?1=83:p(9:::24a?Mb1;2Bo?<5+2b595a=n:k;1<75f2c094?=n:k91<75f2c694?=n:k?1<75f2c494?=h;>i1<75rb821>5<4290;w):;5;153>Nc>:1Ch>?4$3a4>4g<,:296i96;h0a5?6=3`8i>7>5;n14g?6=3th2<>4?:683>5}#<=?1?;l4He40?Mb492.9o:4<6:k1f4<722c9n?4?::k1f6<722c9n94?::k1f0<722c9n;4?::m03f<722wi5=:50;594?6|,=>>6>8m;If57>Nc;81/>n951468m7d62900e?l=:188m7d42900e?l;:188m7d22900e?l9:188k61d2900qo7?5;293?6=8r.?884<6c9K`35<@m9:7)<l7;37?l4e93:17d<m2;29?l4e;3:17d<m4;29?l4e=3:17d<m6;29?j50k3:17pl60`83>2<729q/89;537`8La043An8=6*=c6804>o5j80;66g=b383>>o5j:0;66g=b583>>o5j<0;66g=b783>>i4?j0;66sm91`94?1=83:p(9:::24a?Mb1;2Bo?<5+2b5975=n:k;1<75f2c094?=n:k91<75f2c694?=n:k?1<75f2c494?=h;>i1<75rb9d1>5<0290;w):;5;15f>Nc>:1Ch>?4$3a4>66<a;h:6=44i3`1>5<<a;h86=44i3`7>5<<a;h>6=44i3`5>5<<g:=h6=44}c:e7?6=?3:1<v*;44802g=Ol?90Di=>;%0`3?573`8i=7>5;h0a6?6=3`8i?7>5;h0a0?6=3`8i97>5;h0a2?6=3f9<o7>5;|`;b1<72>0;6=u+457973d<@m<87Ej<1:&1g2<482c9n<4?::k1f7<722c9n>4?::k1f1<722c9n84?::k1f3<722e8;n4?::a<c3=83?1<7>t$566>60>3An=?6Fk309'6f1=:o1b>o?50;9j6g4=831b>o=50;9j6g2=831d?:m50;9~f=`1290<6=4?{%671?51j2Bo:>5Gd238 7e028<>7d<m1;29?l4e:3:17d<m3;29?l4e<3:17d<m5;29?l4e>3:17b=8c;29?xd?n>0;6:4?:1y'013=;?h0Di8<;If05>"5k>0::95f2c394?=n:k81<75f2c194?=n:k>1<75f2c794?=n:k<1<75`36a94?=zj1l36=48:183!23=39=n6Fk629K`67<,;i<6<=4i3`2>5<<a;h96=44i3`0>5<<a;h?6=44i3`6>5<<a;h=6=44o25`>5<<uk2m57>57;294~"3<<08:o5Gd718La563-8h;7?93:k1f4<722c9n?4?::k1f6<722c9n94?::k1f0<722c9n;4?::m03f<722wi4ko50;594?6|,=>>6>8m;If57>Nc;81/>n95d:k1f4<722c9n?4?::k1f6<722c9n94?::k1f0<722c9n;4?::m03f<722wi4kl50;494?6|,=>>6>8n;If57>Nc;81/>n9514;8m7d62900e?l=:188m7d42900e?l;:188m7d22900c>9l:188yg>al3:1;7>50z&700<4>k1Ch;=4He12?!4d?3;>i6g=b083>>o5j;0;66g=b283>>o5j=0;66g=b483>>o5j?0;66a<7b83>>{e0li1<7:50;2x 12228?i7Ej93:Jg74=#:j=1>6g92;29?lgc2900e>67:188k6>22900qo6je;290?6=8r.?884>5c9K`35<@m9:7)<l7;08m34=831bmi4?::k0<=<722e8484?::a<``=8391<7>t$566>6003An=?6Fk309'6f1=9=i0(>6=:e4e?l4e93:17d<m2;29?j50k3:17pl65b83>1<729q/89;514`8La043An8=6*=c681?l052900elj50;9j7=>=831d?5;50;9~f<3c29086=4?{%671?51?2Bo:>5Gd238 7e028>h7)=72;f45>o5j80;66g=b383>>i4?j0;66sm8e194?2=83:p(9:::07a?Mb1;2Bo?<5+2b596>o1:3:17dok:188m6>?2900c>6::188yg>c<3:1?7>50z&700<4>>1Ch;=4He12?!4d?3;?o6*<838g35=n:k;1<75f2c094?=h;>i1<75rb823>5<0290;w):;5;15f>Nc>:1Ch>?4$3a4>7e<a;h:6=44i3`1>5<<a;h86=44i3`7>5<<a;h>6=44i3`5>5<<g:=h6=44}c:eb?6=?3:1<v*;44802g=Ol?90Di=>;%0`3?71:2c9n<4?::k1f7<722c9n>4?::k1f1<722c9n84?::k1f3<722e8;n4?::a=51=83>1<7>t$566>60?3An=?6Fk309'6f1=m2.84?4k769j6g7=831b>o<50;9j6g5=831d?:m50;9~f<6?290<6=4?{%671?51j2Bo:>5Gd238 7e028<:7d<m1;29?l4e:3:17d<m3;29?l4e<3:17d<m5;29?l4e>3:17b=8c;29?xd>880;6:4?:1y'013=;?h0Di8<;If05>"5k>0:985f2c394?=n:k81<75f2c194?=n:k>1<75f2c794?=n:k<1<75`36a94?=zjk2<6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66smc5d94?5=83:p(9:::070?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?j5?=3:17pll4d83>6<729q/89;51418La043An8=6*=c6826>o1:3:17dok:188k6>22900qom;d;297?6=8r.?884>529K`35<@m9:7)<l7;31?l052900elj50;9l7=3=831vnn:l:180>5<7s->?97?:3:Jg26=Ol:;0(?m8:008m34=831bmi4?::m0<0<722wio9l50;194?6|,=>>6<;<;If57>Nc;81/>n95139j27<722cjh7>5;n1;1?6=3thh8l4?:283>5}#<=?1=8=4He40?Mb492.9o:4>2:k56?6=3`ko6=44o2:6>5<<uki?57>53;294~"3<<0:9>5Gd718La563-8h;7?=;h41>5<<ahn1<75`39794?=zjj>36=4<:183!23=3;>?6Fk629K`67<,;i<6<<4i7094?=nim0;66a<8483>>{ek=<1<7=50;2x 12228?87Ej93:Jg74=#:j=1=?5f6383>>ofl3:17b=75;29?xdd<<0;6>4?:1y'013=9<90Di8<;If05>"5k>0:>6g92;29?lgc2900c>6::188yge3<3:1?7>50z&700<6=:1Ch;=4He12?!4d?3;97d8=:188mdb=831d?5;50;9~ff2429086=4?{%671?72;2Bo:>5Gd238 7e02880e;<50;9jea<722e8484?::ag14=8391<7>t$566>4343An=?6Fk309'6f1=9;1b:?4?::kb`?6=3f9397>5;|``04<72:0;6=u+4579505<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<g:2>6=44}ca74?6=;3:1<v*;448216=Ol?90Di=>;%0`3?753`<96=44i`f94?=h;1?1<75rbb1e>5<4290;w):;5;367>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>i40<0;66smc2g94?5=83:p(9:::070?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?j5?=3:17pll3e83>6<729q/89;51418La043An8=6*=c6826>o1:3:17dok:188k6>22900qom<b;297?6=8r.?884>529K`35<@m9:7)<l7;31?l052900elj50;9l7=3=831vnn=n:180>5<7s->?97?:3:Jg26=Ol:;0(?m8:008m34=831bmi4?::m0<0<722wio>750;194?6|,=>>6<;<;If57>Nc;81/>n95139j27<722cjh7>5;n1;1?6=3thh?54?:283>5}#<=?1=8=4He40?Mb492.9o:4>2:k56?6=3`ko6=44o2:6>5<<uki8;7>53;294~"3<<0:9>5Gd718La563-8h;7?=;h41>5<<ahn1<75`39794?=zjj9=6=4<:183!23=3;>?6Fk629K`67<,;i<6<<4i7094?=nim0;66a<8483>>{ek:?1<7=50;2x 12228?87Ej93:Jg74=#:j=1=?5f6383>>ofl3:17b=75;29?xdd;=0;6>4?:1y'013=9<90Di8<;If05>"5k>0:>6g92;29?lgc2900c>6::188yge4;3:1?7>50z&700<6=:1Ch;=4He12?!4d?3;97d8=:188mdb=831d?5;50;9~ff5529086=4?{%671?72;2Bo:>5Gd238 7e02880e;<50;9jea<722e8484?::agd`=8391<7>t$566>4343An=?6Fk309'6f1=9;1b:?4?::kb`?6=3f9397>5;|``e`<72:0;6=u+4579505<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<g:2>6=44}cab`?6=;3:1<v*;448216=Ol?90Di=>;%0`3?753`<96=44i`f94?=h;1?1<75rbbc`>5<4290;w):;5;367>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>i40<0;66smc``94?5=83:p(9:::070?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?j5?=3:17plla`83>6<729q/89;51418La043An8=6*=c6826>o1:3:17dok:188k6>22900qomn9;297?6=8r.?884>529K`35<@m9:7)<l7;31?l052900elj50;9l7=3=831vnno7:180>5<7s->?97?:3:Jg26=Ol:;0(?m8:008m34=831bmi4?::m0<0<722wiol950;194?6|,=>>6<;<;If57>Nc;81/>n95139j27<722cjh7>5;n1;1?6=3thhm;4?:283>5}#<=?1=8=4He40?Mb492.9o:4>2:k56?6=3`ko6=44o2:6>5<<ukij87>53;294~"3<<0:9>5Gd718La563-8h;7?=;h41>5<<ahn1<75`39794?=zjjk86=4<:183!23=3;>?6Fk629K`67<,;i<6<<4i7094?=nim0;66a<8483>>{ekh81<7=50;2x 12228?87Ej93:Jg74=#:j=1=?5f6383>>ofl3:17b=75;29?xddi80;6>4?:1y'013=9<90Di8<;If05>"5k>0:>6g92;29?lgc2900c>6::188ygef83:1?7>50z&700<6=:1Ch;=4He12?!4d?3;97d8=:188mdb=831d?5;50;9~ff?a29086=4?{%671?72;2Bo:>5Gd238 7e02880e;<50;9jea<722e8484?::ag<c=8391<7>t$566>4343An=?6Fk309'6f1=9;1b:?4?::kb`?6=3f9397>5;|``=a<72:0;6=u+4579505<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<g:2>6=44}ca:g?6=;3:1<v*;448216=Ol?90Di=>;%0`3?753`<96=44i`f94?=h;1?1<75rbb;a>5<4290;w):;5;367>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>i40<0;66smc8;94?5=83:p(9:::070?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?j5?=3:17pll9983>6<729q/89;51418La043An8=6*=c6826>o1:3:17dok:188k6>22900qom67;297?6=8r.?884>529K`35<@m9:7)<l7;31?l052900elj50;9l7=3=831vnn79:180>5<7s->?97?:3:Jg26=Ol:;0(?m8:008m34=831bmi4?::m0<0<722wio4;50;194?6|,=>>6<;<;If57>Nc;81/>n95139j27<722cjh7>5;n1;1?6=3thh594?:283>5}#<=?1=8=4He40?Mb492.9o:4>2:k56?6=3`ko6=44o2:6>5<<uki2?7>53;294~"3<<0:9>5Gd718La563-8h;7?=;h41>5<<ahn1<75`39794?=zjj396=4<:183!23=3;>?6Fk629K`67<,;i<6<<4i7094?=nim0;66a<8483>>{ek0;1<7=50;2x 12228?87Ej93:Jg74=#:j=1=?5f6383>>ofl3:17b=75;29?xdd190;6>4?:1y'013=9<90Di8<;If05>"5k>0:>6g92;29?lgc2900c>6::188yge?m3:1?7>50z&700<6=:1Ch;=4He12?!4d?3;97d8=:188mdb=831d?5;50;9~ff>c29086=4?{%671?72;2Bo:>5Gd238 7e02880e;<50;9jea<722e8484?::ag=e=8391<7>t$566>4343An=?6Fk309'6f1=9;1b:?4?::kb`?6=3f9397>5;|``<g<72:0;6=u+4579505<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<g:2>6=44}ca;e?6=;3:1<v*;448216=Ol?90Di=>;%0`3?753`<96=44i`f94?=h;1?1<75rbb::>5<4290;w):;5;367>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>i40<0;66smc9:94?5=83:p(9:::070?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?j5?=3:17pll8683>6<729q/89;51418La043An8=6*=c6826>o1:3:17dok:188k6>22900qom76;297?6=8r.?884>529K`35<@m9:7)<l7;31?l052900elj50;9l7=3=831vnn6::180>5<7s->?97?:3:Jg26=Ol:;0(?m8:008m34=831bmi4?::m0<0<722wio5=50;194?6|,=>>6<;<;If57>Nc;81/>n95139j27<722cjh7>5;n1;1?6=3thh4?4?:283>5}#<=?1=8=4He40?Mb492.9o:4>2:k56?6=3`ko6=44o2:6>5<<uki3=7>53;294~"3<<0:9>5Gd718La563-8h;7?=;h41>5<<ahn1<75`39794?=zjj2;6=4<:183!23=3;>?6Fk629K`67<,;i<6<<4i7094?=nim0;66a<8483>>{ek>l1<7=50;2x 12228?87Ej93:Jg74=#:j=1=?5f6383>>ofl3:17b=75;29?xdd?l0;6>4?:1y'013=9<90Di8<;If05>"5k>0:>6g92;29?lgc2900c>6::188yge0l3:1?7>50z&700<6=:1Ch;=4He12?!4d?3;97d8=:188mdb=831d?5;50;9~ff1d29086=4?{%671?72;2Bo:>5Gd238 7e02880e;<50;9jea<722e8484?::ag2d=8391<7>t$566>4343An=?6Fk309'6f1=9;1b:?4?::kb`?6=3f9397>5;|``3d<72:0;6=u+4579505<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<g:2>6=44}ca4<?6=;3:1<v*;448216=Ol?90Di=>;%0`3?753`<96=44i`f94?=h;1?1<75rbb54>5<4290;w):;5;367>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>i40<0;66smc6494?5=83:p(9:::070?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?j5?=3:17pll7483>6<729q/89;51418La043An8=6*=c6826>o1:3:17dok:188k6>22900qom84;297?6=8r.?884>529K`35<@m9:7)<l7;31?l052900elj50;9l7=3=831vnn9<:180>5<7s->?97?:3:Jg26=Ol:;0(?m8:008m34=831bmi4?::m0<0<722wio:<50;194?6|,=>>6<;<;If57>Nc;81/>n95139j27<722cjh7>5;n1;1?6=3thh;<4?:283>5}#<=?1=8=4He40?Mb492.9o:4>2:k56?6=3`ko6=44o2:6>5<<uki<<7>53;294~"3<<0:9>5Gd718La563-8h;7?=;h41>5<<ahn1<75`39794?=zjj<m6=4<:183!23=3;>?6Fk629K`67<,;i<6<<4i7094?=nim0;66a<8483>>{ek?n1<7=50;2x 12228?87Ej93:Jg74=#:j=1=?5f6383>>ofl3:17b=75;29?xdd>j0;6>4?:1y'013=9<90Di8<;If05>"5k>0:>6g92;29?lgc2900c>6::188yge1j3:1?7>50z&700<6=:1Ch;=4He12?!4d?3;97d8=:188mdb=831d?5;50;9~ff0f29086=4?{%671?72;2Bo:>5Gd238 7e02880e;<50;9jea<722e8484?::ag3?=8391<7>t$566>4343An=?6Fk309'6f1=9;1b:?4?::kb`?6=3f9397>5;|``2=<72:0;6=u+4579505<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<g:2>6=44}ca53?6=;3:1<v*;448216=Ol?90Di=>;%0`3?753`<96=44i`f94?=h;1?1<75rbb45>5<4290;w):;5;367>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>i40<0;66smc7794?5=83:p(9:::070?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?j5?=3:17pll6583>6<729q/89;51418La043An8=6*=c6826>o1:3:17dok:188k6>22900qom92;297?6=8r.?884>529K`35<@m9:7)<l7;31?l052900elj50;9l7=3=831vnn8>:180>5<7s->?97?:3:Jg26=Ol:;0(?m8:008m34=831bmi4?::m0<0<722wio;>50;194?6|,=>>6<;<;If57>Nc;81/>n95139j27<722cjh7>5;n1;1?6=3thh9k4?:283>5}#<=?1=8=4He40?Mb492.9o:4>2:k56?6=3`ko6=44o2:6>5<<uki>i7>53;294~"3<<0:9>5Gd718La563-8h;7?=;h41>5<<ahn1<75`39794?=zjj?o6=4<:183!23=3;>?6Fk629K`67<,;i<6<<4i7094?=nim0;66a<8483>>{ek<i1<7=50;2x 12228?87Ej93:Jg74=#:j=1=?5f6383>>ofl3:17b=75;29?xdd=k0;6>4?:1y'013=9<90Di8<;If05>"5k>0:>6g92;29?lgc2900c>6::188yge2i3:1?7>50z&700<6=:1Ch;=4He12?!4d?3;97d8=:188mdb=831d?5;50;9~ff3>29086=4?{%671?72;2Bo:>5Gd238 7e02880e;<50;9jea<722e8484?::ag01=8391<7>t$566>4343An=?6Fk309'6f1=9;1b:?4?::kb`?6=3f9397>5;|``13<72:0;6=u+4579505<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<g:2>6=44}ca61?6=;3:1<v*;448216=Ol?90Di=>;%0`3?753`<96=44i`f94?=h;1?1<75rbb77>5<4290;w):;5;367>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>i40<0;66smc4194?5=83:p(9:::070?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?j5?=3:17pll5383>6<729q/89;51418La043An8=6*=c6826>o1:3:17dok:188k6>22900qom:1;297?6=8r.?884>529K`35<@m9:7)<l7;31?l052900elj50;9l7=3=831vnn;?:180>5<7s->?97?:3:Jg26=Ol:;0(?m8:008m34=831bmi4?::m0<0<722wio9950;194?6|,=>>6<;<;If57>Nc;81/>n95139j27<722cjh7>5;n1;1?6=3thh?n4?:283>5}#<=?1=8=4He40?Mb492.9o:4>2:k56?6=3`ko6=44o2:6>5<<ukii<7>53;294~"3<<0:9>5Gd718La563-8h;7?=;h41>5<<ahn1<75`39794?=zjjk>6=4<:183!23=3;>?6Fk629K`67<,;i<6<<4i7094?=nim0;66a<8483>>{ek0k1<7=50;2x 12228?87Ej93:Jg74=#:j=1=?5f6383>>ofl3:17b=75;29?xdd0o0;6>4?:1y'013=9<90Di8<;If05>"5k>0:>6g92;29?lgc2900c>6::188yge?<3:1?7>50z&700<6=:1Ch;=4He12?!4d?3;97d8=:188mdb=831d?5;50;9~ff1>29086=4?{%671?72;2Bo:>5Gd238 7e02880e;<50;9jea<722e8484?::ag3c=8391<7>t$566>4343An=?6Fk309'6f1=9;1b:?4?::kb`?6=3f9397>5;|``26<72:0;6=u+4579505<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<g:2>6=44}ca6<?6=;3:1<v*;448216=Ol?90Di=>;%0`3?753`<96=44i`f94?=h;1?1<75rbb12>5<4290;w):;5;367>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>i40<0;66sma1494?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xdf:m0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qoo<8;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~fd24290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wim9k50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`b1<<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<ukk=87>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb`4e>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{ei>k1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pln8483>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188ygg693:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vnl?l:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::ae73=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3thj>;4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}cc13?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zjh836=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sma3;94?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xdf:h0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qoo=b;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~fd4d290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wim?k50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`b6c<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<ukk8<7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb`12>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{ei:81<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pln3283>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188ygg4<3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vnl=::187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::ae60=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3thj?:4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}cc0=?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zjh9j6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sma2`94?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xdf;j0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qoo<d;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~fd5b290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wim>h50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`b05<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<ukk?=7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb`61>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{ei=>1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pln4483>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188ygg3>3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vnl:8:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::ae1>=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3thj844?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}cc7e?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zjh>i6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sma5a94?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xdf<m0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qoo;f;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~fd37290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wim8?50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`b17<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<ukk>?7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb`77>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{ei<?1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pln5783>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188ygg2?3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vnl;7:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::ae0g=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3thj9o4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}cc6g?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zjh?o6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sma4g94?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xdf=o0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qoo90;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~fd06290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wim;<50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`b26<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<ukk=97>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb`45>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{ei?=1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pln6983>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188ygg113:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vnl8n:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::ae3d=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3thj:n4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}cc5`?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zjh<n6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sma6294?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xdf?80;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qoo82;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~fd14290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wim::50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`b30<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<ukk<:7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb`54>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{ei>21<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pln7883>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188ygg0j3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vnl9l:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::ae2b=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3thj;h4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}cc4b?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zjh2;6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sma9394?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xdf0;0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qoo73;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~fd>3290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wim=950;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`b4=<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<ukk;57>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb`2b>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{ei9h1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pln0b83>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188ygg7l3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vnl>j:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::ae5`=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3thj==4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}cc26?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zjh;86=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sma0694?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xdf9<0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qoo>6;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~fd70290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wim<650;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`b5<<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<ukk:m7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb`3a>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{ei8n1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pln1d83>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188ygg6n3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vnl<?:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::ae77=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3thj>?4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}cc17?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zjh8?6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sm99494?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xd>im0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qo7m8;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~f<e4290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wi5nk50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`:`<<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<uk3n87>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb8ge>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{e1ok1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pln0483>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188yg?>93:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vn47l:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::a=d3=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3th2m;4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}c;b3?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zj0k36=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sm9`;94?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xd>ih0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qo7nb;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~f<gd290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wi5lk50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`:ec<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<uk3i<7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb8`2>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{e1k81<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pl6b283>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188yg?e<3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vn4l::187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::a=g0=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3th2n:4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}c;a=?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zj0hj6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sm9c`94?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xd>jj0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qo7md;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~f<db290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wi5oh50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`:g5<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<uk3h=7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb8a1>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{e1j>1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pl6c483>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188yg?d>3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vn4m8:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::a=f>=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3th2o44?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}c;`e?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zj0ii6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sm9ba94?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xd>km0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qo7lf;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~f<b7290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wi5i?50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`:`7<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<uk3o?7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb8f7>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{e1m?1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pl6d783>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188yg?c?3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vn4j7:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::a=ag=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3th2ho4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}c;gg?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zj0no6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sm9eg94?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xd>lo0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qo7j0;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~f<c6290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wi5h<50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`:a6<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<uk3n97>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb8g5>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{e1l=1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pl6e983>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188yg?b13:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vn4kn:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::a=`d=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3th2in4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}c;f`?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zj0on6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sm9g294?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xd>n80;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qo7i2;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~f<`4290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wi5k:50;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`:b0<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<uk3m:7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb8d4>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{e1o21<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pl6f883>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188yg?aj3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vn4hl:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::a=cb=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3th2jh4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}c;eb?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zjh:;6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sma1394?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xdf8;0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qoo?3;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~fd63290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wi55950;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`:<=<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<uk3357>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb8:b>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{e11h1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pl68b83>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188yg??l3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vn46j:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::a==`=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3th25=4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}c;:6?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zj0386=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sm98694?2=83:p(9:::07b?Mb1;2Bo?<5+2b5957=n>;0;66gnd;29?l5?;3:17b=75;29?xd>1<0;694?:1y'013=9<k0Di8<;If05>"5k>0:>6g92;29?lgc2900e>6<:188k6>22900qo766;290?6=8r.?884>5`9K`35<@m9:7)<l7;31?l052900elj50;9j7=5=831d?5;50;9~f<?0290?6=4?{%671?72i2Bo:>5Gd238 7e02880e;<50;9jea<722c84>4?::m0<0<722wi54650;694?6|,=>>6<;n;If57>Nc;81/>n95139j27<722cjh7>5;h1;7?6=3f9397>5;|`:=<<72=0;6=u+457950g<@m<87Ej<1:&1g2<6:2c=>7>5;hcg>5<<a:286=44o2:6>5<<uk32m7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb8;a>5<3290;w):;5;36e>Nc>:1Ch>?4$3a4>44<a?81<75fae83>>o40:0;66a<8483>>{e10n1<7:50;2x 12228?j7Ej93:Jg74=#:j=1=?5f6383>>ofl3:17d=73;29?j5?=3:17pl69d83>1<729q/89;514c8La043An8=6*=c6826>o1:3:17dok:188m6>42900c>6::188yg?>n3:187>50z&700<6=h1Ch;=4He12?!4d?3;97d8=:188mdb=831b?5=50;9l7=3=831vn4o?:187>5<7s->?97?:a:Jg26=Ol:;0(?m8:008m34=831bmi4?::k0<6<722e8484?::a=d7=83>1<7>t$566>43f3An=?6Fk309'6f1=9;1b:?4?::kb`?6=3`93?7>5;n1;1?6=3th2m?4?:583>5}#<=?1=8o4He40?Mb492.9o:4>2:k56?6=3`ko6=44i2:0>5<<g:2>6=44}c;b7?6=<3:1<v*;44821d=Ol?90Di=>;%0`3?753`<96=44i`f94?=n;191<75`39794?=zj0k?6=4;:183!23=3;>m6Fk629K`67<,;i<6<<4i7094?=nim0;66g<8283>>i40<0;66sm8eg94?2=83:p(9:::075?Mb1;2Bo?<5+2b596>o1:3:17d6;:188mdb=831d?5;50;9~f=ba290?6=4?{%671?72>2Bo:>5Gd238 7e02;1b:?4?::k;0?6=3`ko6=44o2:6>5<<uk2o;7>54;294~"3<<0:9l5Gd718La563-8h;7?=;h41>5<<ahn1<75f39194?=h;1?1<75rb9f5>5<3290;w):;5;362>Nc>:1Ch>?4$3a4>7=n>;0;66g74;29?lgc2900c>6::188yg?6:3:187>50z&700<6=?1Ch;=4He12?!4d?380e;<50;9j<1<722cjh7>5;n1;1?6=3th35o4?:283>5}#<=?1=8=4He40?Mb492.9o:4>2:k56?6=3`ko6=44o2:6>5<<uk23j7>54;294~"3<<0:9;5Gd718La563-8h;7<4i7094?=n0=0;66gnd;29?j5?=3:17pl78d83>1<729q/89;51448La043An8=6*=c681?l052900e5:50;9jea<722e8484?::a<2e=83>1<7>t$566>4313An=?6Fk309'6f1=:2c=>7>5;h:7>5<<ahn1<75`39794?=zj1=i6=4;:183!23=3;>:6Fk629K`67<,;i<6?5f6383>>o?<3:17dok:188k6>22900qo7?9;290?6=8r.?884<699K`35<@m9:7)<l7;1g?!5?:3n<;6g=b083>>o5j;0;66g=b283>>i4?j0;66sm67694?1=83:p(9:::24a?Mb1;2Bo?<5+2b59b>o5j80;66g=b383>>o5j:0;66g=b583>>o5j<0;66g=b783>>i4?j0;66sm67094?1=83:p(9:::24a?Mb1;2Bo?<5+2b59=>o5j80;66g=b383>>o5j:0;66g=b583>>o5j<0;66g=b783>>i4?j0;66sm65c94?e?290;wEj<1:&700<4001Q:<4l{0:95<<5>38j6?952c81<?472;;1>?4=9;3e>xh69l0;7c?;0;28 7d02?1/>o656:&1f<<13-8im784$3`a>3=#:ki1:6*=be85?!4em3<0(?li:79'6f6=>2.9o<49;%0`6?0<,;i86;5+2b692>"5k<0=7)<l6;48 7e?2?1/>n756:&1gd<13-8hn784$3a`>3=#:jn1:6*=cd85?!4dn3<0(?j?:79'6a7=>2.9h?49;%0g7?0<,;n?6;5+2e792>"5l?0=7)<k7;48 7b?2?1/>i756:&1`d<13-8on784$3f`>3=#:mn1:6*=dd85?!4cn3<0(?k?:79'6`7=>2.9i?49;%0f7?0<,;o?6;5+2d792>"5m?0=7)<j7;48 7c?2?1/>h756:&1ad<13-8nn784$3g`>3=#:ln1:6*=ed85?!4bn3<0(?h?:79'6c7=>2.9j?49;%0e7?0<,;l?6;5+2g792>"5n?0=7)<i7;48 7`?2?1/>k756:&1bd<13-8mn784$3d`>3=#:on1:6*=fd85?!4an3<0(>>?:79'757=>2.8<?49;%137?0<,::?6;5+31792>"48?0=7)=?7;48 66?2?1/?=756:&04d<13-9;n784$22`>3=#;9n1:6*<0d85?!57n3<0(>??:79'747=>2.8=?49;%127?0<,:;?6;5+30792>"49?0=7)=>7;48 67?2?1/?<756:&05d<13-9:n784$23`>3=#;8n1:6*<1d85?!56n3<0(><?:79'777=>2.8>?49;%117?0<,:8?6;5+33792>"4:?0=7)==7;48 64?2?1/??756:&06d<13-99n784$20`>3=#;;n1:6*<2d85?!55n3<0(>=?:79'767=>2.8??49;%107?0<,:9?6;5+32792>"4;?0=7)=<7;48 65?2?1/?>756:&07d<13-98n784$21`>3=#;:n1:6*<3d85?!54n3<0(>:?:79'717=>2.88?49;%177?0<,:>?6;5+35792>"4<?0=7)=;7;48 62?2<1/?9755:&00d<4?k1/?5o536`8 6>e2:=i7c=7c;31?k5?l38?7)=66;43?!5>?392?6*<b786?!5e?3?0(i:l:e6a?!b3l3n?n6`k4d826>hc<o0986gm1;29 6>62j30b>6?:0d8?lb393:1(>6>:e67?k5?83907d99:188m2d=831b=9h50;9jag<72-93=7kn;o1;4?6<3`o26=4+3939ad=i;1:1=65fe683>!5?93oj7c=70;08?lc1290/?5?5e`9m7=6=;21bi84?:%1;5?cf3g93<7:4;hg7>5<#;1;1il5a39291>=nm:0;6)=71;gb?k5?83<07dk=:18'7=7=mh1e?5>57:9ja4<72-93=7kn;o1;4?><3`o;6=4+3939ad=i;1:1565fdg83>!5?93oj7c=70;c8?lbb290/?5?5e`9m7=6=j21bhn4?:%1;5?cf3g93<7m4;hfa>5<#;1;1il5a3929`>=nlh0;6)=71;gb?k5?83o07dj6:18'7=7=mh1e?5>5f:9j`=<72-93=7kn;o1;4?7732co;7>5$2:2>`g<f:2;6<?4;hf5>5<#;1;1il5a392957=<am?1<7*<808fe>h4090:?65fd583>!5?93oj7c=70;37?>oc;3:1(>6>:dc8j6>728?07dh=:18'7=7=mh1e?5>51798mc7=83.84<4ja:l0<5<6?21bj=4?:%1;5?cf3g93<7?7;:kfb?6=,:2:6ho4n2:3>4?<3`on6=4+3939ad=i;1:1=l54idf94?"4080nm6`<8182f>=nmj0;6)=71;gb?k5?83;h76gj8;29 6>62lk0b>6?:0f8?lbc290/?5?5e`9m7=6=9l10ei<50;&0<4<bi2d84=4>f:9l555=83.84<4>149m7=6=9910c<>=:18'7=7=98?0b>6?:038?j7793:1(>6>:036?k5?83;976a>0183>!5?93;:96`<81827>=hno0;6)=71;321>h4090:865`fd83>!5?93;:96`<81821>=h98n1<7*<808250=i;1:1=;54o03`>5<#;1;1=<;4n2:3>41<3f;:n7>5$2:2>4723g93<7?7;:m25d<72-93=7?>5:l0<5<6121d=<750;&0<4<69<1e?5>51`98k47?290/?5?51078j6>728h07b?>7;29 6>628;>7c=70;3`?>i69:0;6)=71;321>h4090:h65`11:94?"4080:=85a39295`=<gon1<7*<808250=i;1:1=k54o061>5<#;1;1=9:4n2:3>7=<g8>:6=4+3939512<f:2;6>54iga94?"4080mn6`<8183?>oai3:1(>6>:g`8j6>72810ek750;&0<4<aj2d84=4=;:ke<?6=,:2:6kl4n2:3>6=<a=91<7*<80870>h4090:76g;2;29 6>62=>0b>6?:398m17=83.84<4;4:l0<5<432c?<7>5$2:2>12<f:2;6954i2d94?"4080?86`<8186?>o3m3:1(>6>:568j6>72?10e9j50;&0<4<3<2d84=48;:k7g?6=,:2:69:4n2:3>==<a=h1<7*<80870>h4090276g;a;29 6>62=>0b>6?:`98m1?=83.84<4;4:l0<5<e32c>87>5$2:2>03<f:2;6<54i4194?"4080>96`<8181?>o2:3:1(>6>:478j6>72:10e8?50;&0<4<2=2d84=4;;:k64?6=,:2:68;4n2:3>0=<a<l1<7*<80861>h4090=76g:e;29 6>62<?0b>6?:698m0b=83.84<4:5:l0<5<?32c>o7>5$2:2>03<f:2;6454i4`94?"4080>96`<818b?>oc<?0;6)=71;f7=>h4090876a9a;29?j0>2900e>6j:188k3d=831b?o750;9l2=<722c=97>5;h364?6=3`<?6=44i7594?=n;k21<75f6783>>o40o0;66gi7;29 6>62o<0b>6?:198mc3=83.84<4i6:l0<5<632cm87>5$2:2>c0<f:2;6?54ig194?"4080m:6`<8180?>oc<<0;6)=71;f70>h4090;76gk4283>!5?93n?86`<8182?>oc<;0;6)=71;f70>h4090976a>1783>!5?93;:96`<8183?>i69=0;6)=71;321>h4090:76a>1383>!5?93;:96`<8181?>i6980;6)=71;321>h4090876a>1183>!5?93;:96`<8187?>i68o0;6)=71;321>h4090>76a>0d83>!5?93;:96`<8185?>i68m0;6)=71;321>h4090<76a>0b83>!5?93;:96`<818;?>i68k0;6)=71;321>h4090276a>0`83>!5?93;:96`<818b?>i6800;6)=71;321>h4090i76a>0683>!5?93;:96`<818`?>i68?0;6)=71;321>h4090o76a>0483>!5?93;:96`<818f?>i68=0;6)=71;321>h4090m76a>4483>!5?93;?86`<8183?>i6<:0;6)=71;370>h4090:76a>4`83>!5?93;?56`<8183?>i6<10;6)=71;37=>h4090:76a>4683>!5?93;?56`<8181?>i6<?0;6)=71;37=>h4090876g;5;29 6>62=>0b>6?:198m1>=83.84<4;4:l0<5<d32c?;7>5$2:2>12<f:2;6i54i5494?"4080?86`<818f?>o4m3:1(>6>:568j6>72o10c<=7:18'7=7=9:=0b>6?:198k451290/?5?51258j6>72810c<=;:18'7=7=9:=0b>6?:398k454290/?5?51258j6>72:10c<==:18'7=7=9:=0b>6?:598k456290/?5?51258j6>72<10c<=?:18'7=7=9:=0b>6?:798k44a290/?5?51258j6>72>10c<<j:18'7=7=9:=0b>6?:998k44c290/?5?51258j6>72010c<<l:18'7=7=9:=0b>6?:`98k44e290/?5?51258j6>72k10c<<6:18'7=7=9:=0b>6?:b98k44?290/?5?51258j6>72m10c<<8:18'7=7=9:=0b>6?:d98k441290/?5?51258j6>72o10c<<::18'7=7=9:=0b>6?:028?j75<3:1(>6>:014?k5?83;:76a>2283>!5?93;8;6`<81826>=h9;81<7*<808272=i;1:1=>54o002>5<#;1;1=>94n2:3>42<3f;9<7>5$2:2>4503g93<7?:;:m27c<72-93=7?<7:l0<5<6>21d=>k50;&0<4<6;>1e?5>51698k45c290/?5?51258j6>728207b?<c;29 6>6289<7c=70;3:?>i6;k0;6)=71;303>h4090:m65`12c94?"4080:?:5a39295g=<g8926=4+3939561<f:2;6<m4;n301?6=,:2:6<=8;o1;4?7c32e:>l4?:%1;5?74?2d84=4>e:9l54`=83.84<4>369m7=6=9o10e8850;&0<4<2=2d84=4?;:k6e?6=,:2:68;4n2:3>g=<a<31<7*<80861>h4090h76g:8;29 6>62<?0b>6?:e98m01=83.84<4:5:l0<5<b32c?j7>5$2:2>03<f:2;6k54ie6b>5<#;1;1h974n2:3>5=<am>36=4+3939`1?<f:2;6<54ie64>5<#;1;1h974n2:3>7=<ajk1<7*<808`=>h4090;76gl8;29 6>62j30b>6?:098mf0=83.84<4l9:l0<5<532ch97>5$2:2>f?<f:2;6>54ib694?"4080h56`<8187?>od;3:1(>6>:b;8j6>72<10en<50;&0<4<d12d84=49;:k`5?6=,:2:6n74n2:3>2=<aj:1<7*<808`=>h4090376gmf;29 6>62j30b>6?:898mgc=83.84<4l9:l0<5<f32cih7>5$2:2>f?<f:2;6o54ic`94?"4080h56`<818`?>oei3:1(>6>:b;8j6>72m10eo750;&0<4<d12d84=4j;:ka<?6=,:2:6n74n2:3>c=<ak=1<7*<808`=>h4090:<65fb783>!5?93i27c=70;32?>oe=3:1(>6>:b;8j6>728807dl;:18'7=7=k01e?5>51298mg5=83.84<4l9:l0<5<6<21bn?4?:%1;5?e>3g93<7?:;:kg5?6=,:2:6n74n2:3>40<3`n;6=4+3939g<=i;1:1=:54ibd94?"4080h56`<8182<>=nkl0;6)=71;a:?k5?83;276gld;29 6>62j30b>6?:0c8?led290/?5?5c89m7=6=9k10enl50;&0<4<d12d84=4>c:9jg2<72-93=7m6;o1;4?7c32cio7>5$2:2>f?<f:2;6<k4;|`50g<72j21<7>tHe12?!23=39356T91;ax5=<6138=6?o52681f?4?2;:1><4=2;0:>4`=ug;:i7>4n063>5=#:k=1:6*=b985?!4e13<0(?ln:79'6gd=>2.9nn49;%0a`?0<,;hn6;5+2cd92>"5k90=7)<l1;48 7e52?1/>n=56:&1g1<13-8h9784$3a5>3=#:j21:6*=c885?!4di3<0(?mm:79'6fe=>2.9oi49;%0`a?0<,;im6;5+2e292>"5l80=7)<k2;48 7b42?1/>i:56:&1`0<13-8o:784$3f4>3=#:m21:6*=d885?!4ci3<0(?jm:79'6ae=>2.9hi49;%0ga?0<,;nm6;5+2d292>"5m80=7)<j2;48 7c42?1/>h:56:&1a0<13-8n:784$3g4>3=#:l21:6*=e885?!4bi3<0(?km:79'6`e=>2.9ii49;%0fa?0<,;om6;5+2g292>"5n80=7)<i2;48 7`42?1/>k:56:&1b0<13-8m:784$3d4>3=#:o21:6*=f885?!4ai3<0(?hm:79'6ce=>2.9ji49;%0ea?0<,;lm6;5+31292>"4880=7)=?2;48 6642?1/?=:56:&040<13-9;:784$224>3=#;921:6*<0885?!57i3<0(>>m:79'75e=>2.8<i49;%13a?0<,::m6;5+30292>"4980=7)=>2;48 6742?1/?<:56:&050<13-9::784$234>3=#;821:6*<1885?!56i3<0(>?m:79'74e=>2.8=i49;%12a?0<,:;m6;5+33292>"4:80=7)==2;48 6442?1/??:56:&060<13-99:784$204>3=#;;21:6*<2885?!55i3<0(><m:79'77e=>2.8>i49;%11a?0<,:8m6;5+32292>"4;80=7)=<2;48 6542?1/?>:56:&070<13-98:784$214>3=#;:21:6*<3885?!54i3<0(>=m:79'76e=>2.8?i49;%10a?0<,:9m6;5+35292>"4<80=7)=;2;48 6242?1/?9:56:&000<13-9?:784$264>3=#;=2196*<4886?!53i39<n6*<8`803g=#;1h1?:l4n2:`>44<f:2o6?:4$2;5>36<,:3<6>7<;%1a2?3<,:h<685+d5a9`1d<,m>o6i:m;of7a?753gn?j7<;;h`2>5<#;1;1o45a39295c=<am>:6=4+3939`12<f:2;6>54i6494?=n?k0;66g>4g83>>obj3:1(>6>:dc8j6>72910eh750;&0<4<bi2d84=4>;:kf3?6=,:2:6ho4n2:3>7=<al<1<7*<808fe>h4090876gj5;29 6>62lk0b>6?:598m`2=83.84<4ja:l0<5<232cn?7>5$2:2>`g<f:2;6;54id094?"4080nm6`<8184?>ob93:1(>6>:dc8j6>72110eh>50;&0<4<bi2d84=46;:kgb?6=,:2:6ho4n2:3>d=<amo1<7*<808fe>h4090i76gkc;29 6>62lk0b>6?:b98mad=83.84<4ja:l0<5<c32com7>5$2:2>`g<f:2;6h54ie;94?"4080nm6`<818e?>oc03:1(>6>:dc8j6>728:07dj8:18'7=7=mh1e?5>51098ma0=83.84<4ja:l0<5<6:21bh84?:%1;5?cf3g93<7?<;:kg0?6=,:2:6ho4n2:3>42<3`n86=4+3939ad=i;1:1=854ig094?"4080nm6`<81822>=nn80;6)=71;gb?k5?83;<76gi0;29 6>62lk0b>6?:0:8?lca290/?5?5e`9m7=6=9010ehk50;&0<4<bi2d84=4>a:9jaa<72-93=7kn;o1;4?7e32cno7>5$2:2>`g<f:2;6<m4;hg;>5<#;1;1il5a39295a=<amn1<7*<808fe>h4090:i65fd383>!5?93oj7c=70;3e?>i68:0;6)=71;321>h4090:<65`11094?"4080:=85a392954=<g8::6=4+3939543<f:2;6<<4;n334?6=,:2:6<?:;o1;4?7432emj7>5$2:2>4723g93<7?;;:mea?6=,:2:6<?:;o1;4?7232e:=i4?:%1;5?76=2d84=4>6:9l54e=83.84<4>149m7=6=9>10c<?m:18'7=7=98?0b>6?:0:8?j76i3:1(>6>:036?k5?83;276a>1883>!5?93;:96`<8182e>=h9821<7*<808250=i;1:1=o54o034>5<#;1;1=<;4n2:3>4e<3f;:?7>5$2:2>4723g93<7?k;:m24=<72-93=7?>5:l0<5<6m21dji4?:%1;5?76=2d84=4>f:9l514=83.84<4>459m7=6=:21d=9?50;&0<4<6<=1e?5>53:9jbf<72-93=7hm;o1;4?6<3`lj6=4+3939bg=i;1:1=65ff883>!5?93li7c=70;08?l`?290/?5?5fc9m7=6=;21b8>4?:%1;5?233g93<7?4;h61>5<#;1;1895a39296>=n<80;6)=71;67?k5?83907d:?:18'7=7=<=1e?5>54:9j7c<72-93=7:;;o1;4?3<3`>n6=4+393901=i;1:1:65f4e83>!5?93>?7c=70;58?l2d290/?5?5459m7=6=021b8o4?:%1;5?233g93<774;h6b>5<#;1;1895a3929e>=n<00;6)=71;67?k5?83h07d;;:18'7=7==<1e?5>51:9j16<72-93=7;:;o1;4?4<3`?96=4+393910=i;1:1?65f5083>!5?93?>7c=70;68?l37290/?5?5549m7=6==21b9k4?:%1;5?323g93<784;h7f>5<#;1;1985a39293>=n=m0;6)=71;76?k5?83207d;l:18'7=7==<1e?5>59:9j1g<72-93=7;:;o1;4?g<3`n?:7>5$2:2>a2>3g93<7=4;n4b>5<<g?31<75f39g94?=h>k0;66g<b883>>i103:17d8::188m4372900e;:50;9j22<722c8n54?::k52?6=3`93j7>5;hd4>5<#;1;1j;5a39294>=nn<0;6)=71;d5?k5?83;07dh;:18'7=7=n?1e?5>52:9jb6<72-93=7h9;o1;4?5<3`n?97>5$2:2>a233g93<7>4;hf77?6=,:2:6i:;;o1;4?7<3`n?>7>5$2:2>a233g93<7<4;n322?6=,:2:6<?:;o1;4?6<3f;:87>5$2:2>4723g93<7?4;n326?6=,:2:6<?:;o1;4?4<3f;:=7>5$2:2>4723g93<7=4;n324?6=,:2:6<?:;o1;4?2<3f;;j7>5$2:2>4723g93<7;4;n33a?6=,:2:6<?:;o1;4?0<3f;;h7>5$2:2>4723g93<794;n33g?6=,:2:6<?:;o1;4?><3f;;n7>5$2:2>4723g93<774;n33e?6=,:2:6<?:;o1;4?g<3f;;57>5$2:2>4723g93<7l4;n333?6=,:2:6<?:;o1;4?e<3f;;:7>5$2:2>4723g93<7j4;n331?6=,:2:6<?:;o1;4?c<3f;;87>5$2:2>4723g93<7h4;n371?6=,:2:6<:;;o1;4?6<3f;??7>5$2:2>4233g93<7?4;n37e?6=,:2:6<:6;o1;4?6<3f;?47>5$2:2>42>3g93<7?4;n373?6=,:2:6<:6;o1;4?4<3f;?:7>5$2:2>42>3g93<7=4;h66>5<#;1;1895a39294>=n<10;6)=71;67?k5?83i07d:8:18'7=7=<=1e?5>5d:9j03<72-93=7:;;o1;4?c<3`9n6=4+393901=i;1:1j65`12:94?"4080:?:5a39294>=h9:<1<7*<808272=i;1:1=65`12694?"4080:?:5a39296>=h9:91<7*<808272=i;1:1?65`12094?"4080:?:5a39290>=h9:;1<7*<808272=i;1:1965`12294?"4080:?:5a39292>=h9;l1<7*<808272=i;1:1;65`13g94?"4080:?:5a3929<>=h9;n1<7*<808272=i;1:1565`13a94?"4080:?:5a3929e>=h9;h1<7*<808272=i;1:1n65`13;94?"4080:?:5a3929g>=h9;21<7*<808272=i;1:1h65`13594?"4080:?:5a3929a>=h9;<1<7*<808272=i;1:1j65`13794?"4080:?:5a392955=<g88?6=4+3939561<f:2;6<?4;n317?6=,:2:6<=8;o1;4?7532e:>?4?:%1;5?74?2d84=4>3:9l577=83.84<4>369m7=6=9=10c<<?:18'7=7=9:=0b>6?:078?j74n3:1(>6>:014?k5?83;=76a>3d83>!5?93;8;6`<81823>=h9:n1<7*<808272=i;1:1=554o01`>5<#;1;1=>94n2:3>4?<3f;8n7>5$2:2>4503g93<7?n;:m27d<72-93=7?<7:l0<5<6j21d=>750;&0<4<6;>1e?5>51b98k452290/?5?51258j6>728n07b?=a;29 6>6289<7c=70;3f?>i69o0;6)=71;303>h4090:j65f5783>!5?93?>7c=70;28?l3f290/?5?5549m7=6=j21b944?:%1;5?323g93<7m4;h7;>5<#;1;1985a3929`>=n=>0;6)=71;76?k5?83o07d:i:18'7=7==<1e?5>5f:9j`1g=83.84<4k489m7=6=821bh9650;&0<4<c<01e?5>51:9j`11=83.84<4k489m7=6=:21bol4?:%1;5?e>3g93<7>4;ha;>5<#;1;1o45a39295>=nk?0;6)=71;a:?k5?83807dm::18'7=7=k01e?5>53:9jg1<72-93=7m6;o1;4?2<3`i86=4+3939g<=i;1:1965fc383>!5?93i27c=70;48?le6290/?5?5c89m7=6=?21bo=4?:%1;5?e>3g93<764;h`e>5<#;1;1o45a3929=>=njl0;6)=71;a:?k5?83k07dlk:18'7=7=k01e?5>5b:9jfg<72-93=7m6;o1;4?e<3`hj6=4+3939g<=i;1:1h65fb883>!5?93i27c=70;g8?ld?290/?5?5c89m7=6=n21bn:4?:%1;5?e>3g93<7??;:ka2?6=,:2:6n74n2:3>47<3`h>6=4+3939g<=i;1:1=?54ic694?"4080h56`<81827>=nj:0;6)=71;a:?k5?83;?76gm2;29 6>62j30b>6?:078?lb6290/?5?5c89m7=6=9?10ei>50;&0<4<d12d84=4>7:9jgc<72-93=7m6;o1;4?7?32chi7>5$2:2>f?<f:2;6<74;hag>5<#;1;1o45a39295d=<aji1<7*<808`=>h4090:n65fcc83>!5?93i27c=70;3`?>od?3:1(>6>:b;8j6>728n07dll:18'7=7=k01e?5>51d98yg03k3:1o54?:1yK`67<,=>>6>66;[42>f}603;26?852`813?4e2;21>=4=1;01>7?=9o0vb<?j:19m516=82.9n:49;%0a<?0<,;h26;5+2cc92>"5jk0=7)<mc;48 7dc2?1/>ok56:&1fc<13-8h<784$3a2>3=#:j81:6*=c285?!4d<3<0(?m::79'6f0=>2.9o549;%0`=?0<,;ij6;5+2b`92>"5kj0=7)<ld;48 7eb2?1/>nh56:&1`5<13-8o=784$3f1>3=#:m91:6*=d585?!4c=3<0(?j9:79'6a1=>2.9h549;%0g=?0<,;nj6;5+2e`92>"5lj0=7)<kd;48 7bb2?1/>ih56:&1a5<13-8n=784$3g1>3=#:l91:6*=e585?!4b=3<0(?k9:79'6`1=>2.9i549;%0f=?0<,;oj6;5+2d`92>"5mj0=7)<jd;48 7cb2?1/>hh56:&1b5<13-8m=784$3d1>3=#:o91:6*=f585?!4a=3<0(?h9:79'6c1=>2.9j549;%0e=?0<,;lj6;5+2g`92>"5nj0=7)<id;48 7`b2?1/>kh56:&045<13-9;=784$221>3=#;991:6*<0585?!57=3<0(>>9:79'751=>2.8<549;%13=?0<,::j6;5+31`92>"48j0=7)=?d;48 66b2?1/?=h56:&055<13-9:=784$231>3=#;891:6*<1585?!56=3<0(>?9:79'741=>2.8=549;%12=?0<,:;j6;5+30`92>"49j0=7)=>d;48 67b2?1/?<h56:&065<13-99=784$201>3=#;;91:6*<2585?!55=3<0(><9:79'771=>2.8>549;%11=?0<,:8j6;5+33`92>"4:j0=7)==d;48 64b2?1/??h56:&075<13-98=784$211>3=#;:91:6*<3585?!54=3<0(>=9:79'761=>2.8?549;%10=?0<,:9j6;5+32`92>"4;j0=7)=<d;48 65b2?1/?>h56:&005<13-9?=784$261>3=#;=91:6*<4585?!53=3<0(>:9:79'711=>2.8854:;%17=?3<,:>j6>9m;%1;e?50j2.84o4<7c9m7=e=9;1e?5j5259'7<0=>91/?4953818 6d12<1/?o955:&g0f<c<k1/h9j5d5`8ja2b2880bi:i:368mg7=83.84<4l9:l0<5<6n21bh9?50;&0<4<c<=1e?5>53:9j33<722c<n7>5;h37b?6=3`oi6=4+3939ad=i;1:1<65fe883>!5?93oj7c=70;38?lc0290/?5?5e`9m7=6=:21bi;4?:%1;5?cf3g93<7=4;hg6>5<#;1;1il5a39290>=nm=0;6)=71;gb?k5?83?07dk<:18'7=7=mh1e?5>56:9ja7<72-93=7kn;o1;4?1<3`o:6=4+3939ad=i;1:1465fe183>!5?93oj7c=70;;8?lba290/?5?5e`9m7=6=i21bhh4?:%1;5?cf3g93<7l4;hf`>5<#;1;1il5a3929g>=nlk0;6)=71;gb?k5?83n07djn:18'7=7=mh1e?5>5e:9j`<<72-93=7kn;o1;4?`<3`n36=4+3939ad=i;1:1==54ie594?"4080nm6`<81825>=nl?0;6)=71;gb?k5?83;976gk5;29 6>62lk0b>6?:018?lb3290/?5?5e`9m7=6=9=10ei=50;&0<4<bi2d84=4>5:9jb7<72-93=7kn;o1;4?7132cm=7>5$2:2>`g<f:2;6<94;hd3>5<#;1;1il5a39295==<all1<7*<808fe>h4090:565fed83>!5?93oj7c=70;3b?>obl3:1(>6>:dc8j6>728h07dkl:18'7=7=mh1e?5>51b98m`>=83.84<4ja:l0<5<6l21bhi4?:%1;5?cf3g93<7?j;:kg6?6=,:2:6ho4n2:3>4`<3f;;?7>5$2:2>4723g93<7??;:m247<72-93=7?>5:l0<5<6921d==?50;&0<4<69<1e?5>51398k467290/?5?51078j6>728907bhi:18'7=7=98?0b>6?:068?j`b290/?5?51078j6>728?07b?>d;29 6>628;>7c=70;35?>i69j0;6)=71;321>h4090:;65`10`94?"4080:=85a39295==<g8;j6=4+3939543<f:2;6<74;n32=?6=,:2:6<?:;o1;4?7f32e:=54?:%1;5?76=2d84=4>b:9l541=83.84<4>149m7=6=9j10c<?<:18'7=7=98?0b>6?:0f8?j7703:1(>6>:036?k5?83;n76aid;29 6>628;>7c=70;3e?>i6<;0;6)=71;370>h4090976a>4083>!5?93;?86`<8180?>oak3:1(>6>:g`8j6>72910eko50;&0<4<aj2d84=4>;:ke=?6=,:2:6kl4n2:3>7=<ao21<7*<808ef>h4090876g;3;29 6>62=>0b>6?:098m14=83.84<4;4:l0<5<532c?=7>5$2:2>12<f:2;6>54i5294?"4080?86`<8187?>o4n3:1(>6>:568j6>72<10e9k50;&0<4<3<2d84=49;:k7`?6=,:2:69:4n2:3>2=<a=i1<7*<80870>h4090376g;b;29 6>62=>0b>6?:898m1g=83.84<4;4:l0<5<f32c?57>5$2:2>12<f:2;6o54i4694?"4080>96`<8182?>o2;3:1(>6>:478j6>72;10e8<50;&0<4<2=2d84=4<;:k65?6=,:2:68;4n2:3>1=<a<:1<7*<80861>h4090>76g:f;29 6>62<?0b>6?:798m0c=83.84<4:5:l0<5<032c>h7>5$2:2>03<f:2;6554i4a94?"4080>96`<818:?>o2j3:1(>6>:478j6>72h10ei:9:18'7=7=l=30b>6?:298k3g=831d:44?::k0<`<722e=n7>5;h1a=?6=3f<36=44i7794?=n9<:1<75f6583>>o1?3:17d=m8;29?l012900e>6i:188mc1=83.84<4i6:l0<5<732cm97>5$2:2>c0<f:2;6<54ig694?"4080m:6`<8181?>oa;3:1(>6>:g48j6>72:10ei:::18'7=7=l=>0b>6?:198ma24290/?5?5d568j6>72810ei:=:18'7=7=l=>0b>6?:398k471290/?5?51078j6>72910c<?;:18'7=7=98?0b>6?:098k475290/?5?51078j6>72;10c<?>:18'7=7=98?0b>6?:298k477290/?5?51078j6>72=10c<>i:18'7=7=98?0b>6?:498k46b290/?5?51078j6>72?10c<>k:18'7=7=98?0b>6?:698k46d290/?5?51078j6>72110c<>m:18'7=7=98?0b>6?:898k46f290/?5?51078j6>72h10c<>6:18'7=7=98?0b>6?:c98k460290/?5?51078j6>72j10c<>9:18'7=7=98?0b>6?:e98k462290/?5?51078j6>72l10c<>;:18'7=7=98?0b>6?:g98k422290/?5?51568j6>72910c<:<:18'7=7=9=>0b>6?:098k42f290/?5?515;8j6>72910c<:7:18'7=7=9=30b>6?:098k420290/?5?515;8j6>72;10c<:9:18'7=7=9=30b>6?:298m13=83.84<4;4:l0<5<732c?47>5$2:2>12<f:2;6n54i5594?"4080?86`<818g?>o3>3:1(>6>:568j6>72l10e>k50;&0<4<3<2d84=4i;:m27=<72-93=7?<7:l0<5<732e:?;4?:%1;5?74?2d84=4>;:m271<72-93=7?<7:l0<5<532e:?>4?:%1;5?74?2d84=4<;:m277<72-93=7?<7:l0<5<332e:?<4?:%1;5?74?2d84=4:;:m275<72-93=7?<7:l0<5<132e:>k4?:%1;5?74?2d84=48;:m26`<72-93=7?<7:l0<5<?32e:>i4?:%1;5?74?2d84=46;:m26f<72-93=7?<7:l0<5<f32e:>o4?:%1;5?74?2d84=4m;:m26<<72-93=7?<7:l0<5<d32e:>54?:%1;5?74?2d84=4k;:m262<72-93=7?<7:l0<5<b32e:>;4?:%1;5?74?2d84=4i;:m260<72-93=7?<7:l0<5<6821d=?:50;&0<4<6;>1e?5>51098k444290/?5?51258j6>728807b?=2;29 6>6289<7c=70;30?>i6:80;6)=71;303>h4090:865`13294?"4080:?:5a392950=<g89m6=4+3939561<f:2;6<84;n30a?6=,:2:6<=8;o1;4?7032e:?i4?:%1;5?74?2d84=4>8:9l56e=83.84<4>369m7=6=9010c<=m:18'7=7=9:=0b>6?:0c8?j74i3:1(>6>:014?k5?83;i76a>3883>!5?93;8;6`<8182g>=h9:?1<7*<808272=i;1:1=i54o00b>5<#;1;1=>94n2:3>4c<3f;:j7>5$2:2>4503g93<7?i;:k62?6=,:2:68;4n2:3>5=<a<k1<7*<80861>h4090i76g:9;29 6>62<?0b>6?:b98m0>=83.84<4:5:l0<5<c32c>;7>5$2:2>03<f:2;6h54i5d94?"4080>96`<818e?>oc<h0;6)=71;f7=>h4090;76gk4983>!5?93n?56`<8182?>oc<>0;6)=71;f7=>h4090976gla;29 6>62j30b>6?:198mf>=83.84<4l9:l0<5<632ch:7>5$2:2>f?<f:2;6?54ib794?"4080h56`<8180?>od<3:1(>6>:b;8j6>72=10en=50;&0<4<d12d84=4:;:k`6?6=,:2:6n74n2:3>3=<aj;1<7*<808`=>h4090<76gl0;29 6>62j30b>6?:998mg`=83.84<4l9:l0<5<>32cii7>5$2:2>f?<f:2;6l54icf94?"4080h56`<818a?>oej3:1(>6>:b;8j6>72j10eoo50;&0<4<d12d84=4k;:ka=?6=,:2:6n74n2:3>`=<ak21<7*<808`=>h4090m76gm7;29 6>62j30b>6?:028?ld1290/?5?5c89m7=6=9810eo;50;&0<4<d12d84=4>2:9jf1<72-93=7m6;o1;4?7432ci?7>5$2:2>f?<f:2;6<:4;h`1>5<#;1;1o45a392950=<am;1<7*<808`=>h4090::65fd183>!5?93i27c=70;34?>odn3:1(>6>:b;8j6>728207dmj:18'7=7=k01e?5>51898mfb=83.84<4l9:l0<5<6i21bon4?:%1;5?e>3g93<7?m;:k`f?6=,:2:6n74n2:3>4e<3`i<6=4+3939g<=i;1:1=i54ica94?"4080h56`<8182a>=zj?>o6=4l8;294~Nc;81/89;539;8^37=kr;36<752781e?402;h1>54=0;02>74=:00:j7sa10g94>h6<90;7)<m7;48 7d?2?1/>o756:&1fd<13-8in784$3``>3=#:kn1:6*=bd85?!4en3<0(?m?:79'6f7=>2.9o?49;%0`7?0<,;i?6;5+2b792>"5k?0=7)<l8;48 7e>2?1/>no56:&1gg<13-8ho784$3ag>3=#:jo1:6*=cg85?!4c83<0(?j>:79'6a4=>2.9h>49;%0g0?0<,;n>6;5+2e492>"5l>0=7)<k8;48 7b>2?1/>io56:&1`g<13-8oo784$3fg>3=#:mo1:6*=dg85?!4b83<0(?k>:79'6`4=>2.9i>49;%0f0?0<,;o>6;5+2d492>"5m>0=7)<j8;48 7c>2?1/>ho56:&1ag<13-8no784$3gg>3=#:lo1:6*=eg85?!4a83<0(?h>:79'6c4=>2.9j>49;%0e0?0<,;l>6;5+2g492>"5n>0=7)<i8;48 7`>2?1/>ko56:&1bg<13-8mo784$3dg>3=#:oo1:6*=fg85?!5783<0(>>>:79'754=>2.8<>49;%130?0<,::>6;5+31492>"48>0=7)=?8;48 66>2?1/?=o56:&04g<13-9;o784$22g>3=#;9o1:6*<0g85?!5683<0(>?>:79'744=>2.8=>49;%120?0<,:;>6;5+30492>"49>0=7)=>8;48 67>2?1/?<o56:&05g<13-9:o784$23g>3=#;8o1:6*<1g85?!5583<0(><>:79'774=>2.8>>49;%110?0<,:8>6;5+33492>"4:>0=7)==8;48 64>2?1/??o56:&06g<13-99o784$20g>3=#;;o1:6*<2g85?!5483<0(>=>:79'764=>2.8?>49;%100?0<,:9>6;5+32492>"4;>0=7)=<8;48 65>2?1/?>o56:&07g<13-98o784$21g>3=#;:o1:6*<3g85?!5383<0(>:>:79'714=>2.88>49;%170?0<,:>>6;5+35492>"4<>0=7)=;8;78 62>2<1/?9o536`8 6>f2:=i7)=7b;14f>h40j0:>6`<8e810>"41?0=<6*<9680=6=#;k<196*<b686?!b3k3n?n6*k4e8g0g=il=o1=?5ad5d961=nj80;6)=71;a:?k5?83;m76gia;29 6>62oh0b>6?:098m20=831b;o4?::k20c<722con7>5$2:2>`g<f:2;6i54iec94?"4080nm6`<818f?>oc13:1(>6>:dc8j6>72o10ei650;&0<4<bi2d84=4>0:9j`2<72-93=7kn;o1;4?7632co:7>5$2:2>`g<f:2;6<<4;hf6>5<#;1;1il5a392956=<am>1<7*<808fe>h4090:865fd283>!5?93oj7c=70;36?>oa:3:1(>6>:dc8j6>728<07dh>:18'7=7=mh1e?5>51698mc6=83.84<4ja:l0<5<6021bik4?:%1;5?cf3g93<7?6;:kfa?6=,:2:6ho4n2:3>4g<3`oo6=4+3939ad=i;1:1=o54ida94?"4080nm6`<8182g>=nm10;6)=71;gb?k5?83;o76gkd;29 6>62lk0b>6?:0g8?lb5290/?5?5e`9m7=6=9o10c<><:18'7=7=98?0b>6?:028?j77:3:1(>6>:036?k5?83;:76a>0083>!5?93;:96`<81826>=h99:1<7*<808250=i;1:1=>54ogd94?"4080:=85a392951=<goo1<7*<808250=i;1:1=854o03g>5<#;1;1=<;4n2:3>40<3f;:o7>5$2:2>4723g93<7?8;:m25g<72-93=7?>5:l0<5<6021d=<o50;&0<4<69<1e?5>51898k47>290/?5?51078j6>728k07b?>8;29 6>628;>7c=70;3a?>i69>0;6)=71;321>h4090:o65`10194?"4080:=85a39295a=<g8:36=4+3939543<f:2;6<k4;ndg>5<#;1;1=<;4n2:3>4`<3f;?>7>5$2:2>4233g93<7<4;n375?6=,:2:6<:;;o1;4?5<3`l26=4+3939bg=i;1:1>65ff983>!5?93li7c=70;18?l24290/?5?5459m7=6=921b8?4?:%1;5?233g93<7<4;h62>5<#;1;1895a39297>=n<90;6)=71;67?k5?83>07d=i:18'7=7=<=1e?5>55:9j0`<72-93=7:;;o1;4?0<3`>o6=4+393901=i;1:1;65f4b83>!5?93>?7c=70;:8?l2e290/?5?5459m7=6=121b8l4?:%1;5?233g93<7o4;h6:>5<#;1;1895a3929f>=n==0;6)=71;76?k5?83;07d;<:18'7=7==<1e?5>52:9j17<72-93=7;:;o1;4?5<3`?:6=4+393910=i;1:1865f5183>!5?93?>7c=70;78?l3a290/?5?5549m7=6=>21b9h4?:%1;5?323g93<794;h7g>5<#;1;1985a3929<>=n=j0;6)=71;76?k5?83307d;m:18'7=7==<1e?5>5a:9j`10=83.84<4k489m7=6=;21d:l4?::m5=?6=3`93i7>5;n4a>5<<a:h26=44o7:94?=n><0;66g>5183>>o1<3:17d88:188m6d?2900e;850;9j7=`=831bj:4?:%1;5?`13g93<7>4;hd6>5<#;1;1j;5a39295>=nn=0;6)=71;d5?k5?83807dh<:18'7=7=n?1e?5>53:9j`13=83.84<4k459m7=6=821bh9=50;&0<4<c<=1e?5>51:9j`14=83.84<4k459m7=6=:21bh9?50;&0<4<c<=1e?5>53:9jag<72-93=7kn;o1;4?6<3`o26=4+3939ad=i;1:1=65fe683>!5?93oj7c=70;08?lc1290/?5?5e`9m7=6=;21bi84?:%1;5?cf3g93<7:4;hg7>5<#;1;1il5a39291>=nm:0;6)=71;gb?k5?83<07dk=:18'7=7=mh1e?5>57:9ja4<72-93=7kn;o1;4?><3`o;6=4+3939ad=i;1:1565fdg83>!5?93oj7c=70;c8?lbb290/?5?5e`9m7=6=j21bhn4?:%1;5?cf3g93<7m4;n322?6=,:2:6<?:;o1;4?6<3f;:87>5$2:2>4723g93<7?4;n326?6=,:2:6<?:;o1;4?4<3f;:=7>5$2:2>4723g93<7=4;n324?6=,:2:6<?:;o1;4?2<3f;;j7>5$2:2>4723g93<7;4;n33a?6=,:2:6<?:;o1;4?0<3f;;h7>5$2:2>4723g93<794;n33g?6=,:2:6<?:;o1;4?><3f;;n7>5$2:2>4723g93<774;n33e?6=,:2:6<?:;o1;4?g<3f;;57>5$2:2>4723g93<7l4;n333?6=,:2:6<?:;o1;4?e<3f;;:7>5$2:2>4723g93<7j4;n331?6=,:2:6<?:;o1;4?c<3f;;87>5$2:2>4723g93<7h4;n371?6=,:2:6<:;;o1;4?6<3f;??7>5$2:2>4233g93<7?4;hd`>5<#;1;1jo5a39294>=h9=k1<7*<80820<=i;1:1<65`15:94?"4080:845a39295>=h9==1<7*<80820<=i;1:1>65`15494?"4080:845a39297>=n<<0;6)=71;67?k5?83:07d:7:18'7=7=<=1e?5>5c:9j02<72-93=7:;;o1;4?b<3`>=6=4+393901=i;1:1i65f3d83>!5?93>?7c=70;d8?j7403:1(>6>:014?k5?83:07b?<6;29 6>6289<7c=70;38?j74<3:1(>6>:014?k5?83807b?<3;29 6>6289<7c=70;18?j74:3:1(>6>:014?k5?83>07b?<1;29 6>6289<7c=70;78?j7483:1(>6>:014?k5?83<07b?=f;29 6>6289<7c=70;58?j75m3:1(>6>:014?k5?83207b?=d;29 6>6289<7c=70;;8?j75k3:1(>6>:014?k5?83k07b?=b;29 6>6289<7c=70;`8?j7513:1(>6>:014?k5?83i07b?=8;29 6>6289<7c=70;f8?j75?3:1(>6>:014?k5?83o07b?=6;29 6>6289<7c=70;d8?j75=3:1(>6>:014?k5?83;;76a>2583>!5?93;8;6`<81825>=h9;91<7*<808272=i;1:1=?54o001>5<#;1;1=>94n2:3>45<3f;9=7>5$2:2>4503g93<7?;;:m265<72-93=7?<7:l0<5<6=21d=>h50;&0<4<6;>1e?5>51798k45b290/?5?51258j6>728=07b?<d;29 6>6289<7c=70;3;?>i6;j0;6)=71;303>h4090:565`12`94?"4080:?:5a39295d=<g89j6=4+3939561<f:2;6<l4;n30=?6=,:2:6<=8;o1;4?7d32e:?84?:%1;5?74?2d84=4>d:9l57g=83.84<4>369m7=6=9l10c<?i:18'7=7=9:=0b>6?:0d8?l31290/?5?5549m7=6=821b9l4?:%1;5?323g93<7l4;h7:>5<#;1;1985a3929g>=n=10;6)=71;76?k5?83n07d;8:18'7=7==<1e?5>5e:9j0c<72-93=7;:;o1;4?`<3`n?m7>5$2:2>a2>3g93<7>4;hf7<?6=,:2:6i:6;o1;4?7<3`n?;7>5$2:2>a2>3g93<7<4;hab>5<#;1;1o45a39294>=nk10;6)=71;a:?k5?83;07dm9:18'7=7=k01e?5>52:9jg0<72-93=7m6;o1;4?5<3`i?6=4+3939g<=i;1:1865fc283>!5?93i27c=70;78?le5290/?5?5c89m7=6=>21bo<4?:%1;5?e>3g93<794;ha3>5<#;1;1o45a3929<>=njo0;6)=71;a:?k5?83307dlj:18'7=7=k01e?5>5a:9jfa<72-93=7m6;o1;4?d<3`hi6=4+3939g<=i;1:1o65fb`83>!5?93i27c=70;f8?ld>290/?5?5c89m7=6=m21bn54?:%1;5?e>3g93<7h4;h`4>5<#;1;1o45a392955=<ak<1<7*<808`=>h4090:=65fb483>!5?93i27c=70;31?>oe<3:1(>6>:b;8j6>728907dl<:18'7=7=k01e?5>51598mg4=83.84<4l9:l0<5<6=21bh<4?:%1;5?e>3g93<7?9;:kg4?6=,:2:6n74n2:3>41<3`im6=4+3939g<=i;1:1=554ibg94?"4080h56`<8182=>=nkm0;6)=71;a:?k5?83;j76glc;29 6>62j30b>6?:0`8?lee290/?5?5c89m7=6=9j10en950;&0<4<d12d84=4>d:9jff<72-93=7m6;o1;4?7b32wihnl50;294?6|,=>>6>ll;I1af>J4jj0?w):;1;352>"3<;0:::5+4519531<,=>?6<88;|p7ac=838pR>jj;<a7b?gc3ty8hn4?:3y]7ae<5j>n6lj4}r1gf?6=:rT8ho52c5f9ea=z{:nj6=4={_1ge>;d<j0jh6s|3e;94?4|V:n270m;b;cg?xu4l10;6?uQ3e:89f2f2hn0q~=k7;296~X4l>16o975ae9~w6b12909wS=k6:?`0=<fl2wx?i:50;0xZ6b334i?:7ok;|q0`6<72;qU?i=4=b66>db<uz9o>7>52z\0`7=:k=>1mi5rs2f2>5<5sW9o=63l428b`>{t;m:1<7<t^2f3?8e3:3ko7p}<cg83>7}Y;jl01n:>:`f8yv5dm3:1>vP<cd9>g16=im1v>mk:181[5dl27h?k4nd:p7fe=838pR>ml;<a0a?gc3ty8oo4?:3y]7fd<5j9o6lj4}r1`=?6=:rT8o452c2`9ea=z{:i36=4={_1`<>;d;h0jh6s|3b594?4|V:i<70m<9;cg?xu4k?0;6?uQ3b489f5?2hn0q~=l5;296~X4k<16o>95ae9~w6e32909wS=l4:?`73<fl2wx?n=50;0xZ6e434i897ok;|q0g7<72;qU?n<4=b17>db<uz9h=7>52z\0g4=:k:91mi5rs2a3>5<5sW9h<63l338b`>{t<:o1<7<t^51f?8efn3ko7p};3e83>7}Y<:n01noj:`f8yv24k3:1>vP;3b9>gdb=im1v9=m:181[24j27hmn4nd:p06g=838pR9=n;<abf?gc3ty??44?:3y]06?<5jkj6lj4}r60<?6=:rT??552c`;9ea=z{=9<6=4={_603>;di10jh6s|42494?4|V=9=70mn7;cg?xu3;<0;6?uQ42789fg12hn0q~:<3;296~X3;:16ol:5ae9~w1552909wS:<2:?`e6<fl2wx8>?50;0xZ15634ij>7ok;|q775<72;qU8>>4=bc2>db<uz>9j7>52z\76c=:kh:1mi5rs50f>5<5sW>9i63l9g8b`>{t<;n1<7<t^50g?8e>m3ko7p};2b83>7}Y<;i01n7k:`f8yv25j3:1>vP;2c9>g<e=im1v9<n:181[25i27h5o4nd:p07>=838pR9<7;<a:=?gc3ty?>:4?:3y]071<5j336lj4}r612?6=:rT?>;52c859ea=z{=8>6=4={_611>;d1?0jh6s|43694?4|V=8?70m65;cg?xu3::0;6?uQ43189f?32hn0q~:=2;296~X3:;16o4=5ae9~w1462909wS:=1:?`=7<fl2wx8?>50;0xZ14734i2=7ok;|q75c<72;qU8<h4=b;3>db<uz>:h7>52z\75a=:k1o1mi5rs53`>5<5sW>:o63l8e8b`>{t<8h1<7<t^53a?8e?k3ko7p};1`83>7}Y<8k01n6m:`f8yv2613:1>vP;189>g=g=im1v9?7:181[26027h444nd:p041=838pR9?8;<a;<?gc3ty?=;4?:3y]040<5j2<6lj4}r621?6=:rT?=852c949ea=z{=;?6=4={_620>;d0<0jh6s|40094?4|V=;970m73;cg?xu3980;6?uQ40389f>52hn0q~:>0;296~X39916o5?5ae9~w16a2909wS:?f:?`<5<fl2wx8=k50;0xZ16b34i<j7ok;|q74a<72;qU8=j4=b5f>db<uz>;o7>52z\74f=:k>n1mi5rs52a>5<5sW>;n63l7b8b`>{t<9k1<7<t^52b?8e0j3ko7p};0883>7}Y<9301n9n:`f8yv27?3:1>vP;069>g2>=im1v9>9:181[27>27h;:4nd:p053=838pR9>:;<a42?gc3ty?<94?:3y]052<5j=>6lj4}r637?6=:rT?<>52c669ea=z{=:96=4={_636>;d?:0jh6s|41394?4|V=::70m82;cg?xu3890;6?uQ41289f162hn0q~=if;296~X4no16o:>5ae9~w6`b2909wS=ie:?`2c<fl2wx?km50;0xZ6`d34i=h7ok;|q0bg<72;qU?kl4=b4`>db<uz9mm7>52z\0bd=:k?h1mi5rs2d:>5<5sW9m563l6`8b`>{t;o21<7<t^2d;?8e113ko7p}<f683>7}Y;o=01n87:`f8yv5a>3:1>vP<f79>g31=im1v>h::181[5a=27h:;4nd:p7c2=838pR>h;;<a51?gc3ty8j>4?:3y]7c5<5j<?6lj4}r1e5?6=:rT8j<52c709ea=z{:l;6=4={_1e4>;d>80jh6s|3dd94?4|V:om70m90;cg?xu4ml0;6?uQ3dg89f3a2hn0q~=jd;296~X4mm16o8k5ae9~w6cd2909wS=jc:?`1a<fl2wx?hl50;0xZ6ce34i>o7ok;|q0ad<72;qU?ho4=b7a>db<uz9n57>52z\0a<=:k<k1mi5rs2g;>5<5sW9n463l588b`>{t;l<1<7<t^2g5?8e2?3ko7p}<e483>7}Y;l?01n;9:`f8yv5b<3:1>vP<e59>g03=im1v>k<:181[5b;27h994nd:p7`4=838pR>k=;<a67?gc3ty8i<4?:3y]7`7<5j?96lj4}r1f4?6=:rT8i=52c439ea=z{:nm6=4={_1gb>;d=90jh6s|3e794?4|V:n>70m;7;cg?xu4kh0;6?uQ3bc89f5d2hn0q~:<f;296~X3;o16oo>5ae9~w1532909wS:<4:?`e0<fl2wx8?750;0xZ14>34i2m7ok;|q75`<72;qU8<k4=b:e>db<uz>:?7>52z\756=:k1>1mi5rs52;>5<5sW>;463l788b`>{t;on1<7<t^2dg?8e1m3ko7p}<f383>7}Y;o801n8<:`f8yv5b?3:1>vP<e69>g0>=im1v>li:181[5en27h?<4nd:pe6<72;qUm>528g796g2<uzk:6=4={_c2?8>a=38i?6s|a183>7}Yi9164k;52c38yv?a2909wS7i;<:e1?4e:2wx5h4?:3y]=`=:0o>1>o84}r;g>5<5sW3o706i4;0a1>{t1k0;6?uQ9c9><c2=:k>0q~7n:181[?f342m87<m3:p=<<72;qU54528g696g7<uz336=4={_;;?8>a<38i>6s|9683>7}Y1>165=l52c48yv?12909wS79;<;3f?4e=2wx584?:3y]=0=:19h1>o:4}r;7>5<5sW3?707?b;0a7>{t1:0;6?uQ929>=5d=:k;0q~7=:18246}Y1;16m5853c089<6e2;h970o?6;1;7>;f:m084>52a2:97=5<5h>86>6<;<c7a?5?;27j944<829>e32=;1901l8i:2:0?8g0i393?63n8480<6=:i8;1?5=4=`3`>6>434k997=73:?b63<40:16m?9539189d4?2:2870o=9;1;7>;f:h084>52a3`97=5<5h8h6>6<;<c1a?5?;27j>k4<829>e66=;1901l=>:2:0?8g4:393?63n3280<6=:i:>1?5=4=`16>6>434k8:7=73:?b72<40:16m>7539189d5f2:2870o<b;1;7>;f;j084>52a2f97=5<5h9n6>6<;<c0b?5?;27j8=4<829>e17=;1901l:=:2:0?8g3<393?63n4480<6=:i=<1?5=4=`64>6>434k?47=73:?b0<<40:16m9o539189d2e2:2870o;c;1;7>;f<m084>52a5d97=5<5h?;6>6<;<c65?5?;27j9?4<829>e05=;1901l;;:2:0?8g2=393?63n5780<6=:i<=1?5=4=`7;>6>434k>m7=73:?b1g<40:16m8m539189d3c2:2870o:e;1;7>;f=o084>52a7297=5<5h<:6>6<;<c56?5?;27j:>4<829>e33=;1901l89:2:0?8g1?393?63n6980<6=:i?31?5=4=`4b>6>434k=n7=73:?b2f<40:16m;j539189d0b2:2870o80;1;7>;f?8084>52a6097=5<5h=86>6<;<c40?5?;27j;84<829>e20=;1901l98:2:0?8g00393?63n7880<6=:i>h1?5=4=`5`>6>434k<h7=73:?b3`<40:16m:h539189d>72:2870o71;1;7>;f0;084>52a9197=5<5h2?6>6<;<c33?5?;27j<54<829>e5?=;1901l>n:2:0?8g7j393?63n0b80<6=:i9n1?5=4=`2f>6>434k;j7=73:?b55<40:16m<<539189d742:2870o>4;1;7>;f9<084>52a0497=5<5h;<6>6<;<c2<?5?;27j=44<829>e4g=;1901l?m:2:0?8g6l393?63n1d80<6=:i8l1?5=4=`03>6>434k9=7=73:?b67<40:16m?=539189d432:2870776;1;7>;>im084>529c:97=5<50i86>6<;<;`a?5?;272h44<829>=`2=;19014ki:2:0?8?ai393?63n0480<6=:10;1?5=4=8;`>6>4343j97=73:?:e3<40:165l9539189<g?2:28707n9;1;7>;>ih084>529``97=5<50kh6>6<;<;ba?5?;272mk4<829>=g6=;19014l>:2:0?8?e:393?636b280<6=:1k>1?5=4=8`6>6>4343i:7=73:?:f2<40:165o7539189<df2:28707mb;1;7>;>jj084>529cf97=5<50hn6>6<;<;ab?5?;272o=4<829>=f7=;19014m=:2:0?8?d<393?636c480<6=:1j<1?5=4=8a4>6>4343h47=73:?:g<<40:165no539189<ee2:28707lc;1;7>;>km084>529bd97=5<50n;6>6<;<;g5?5?;272h?4<829>=a5=;19014j;:2:0?8?c=393?636d780<6=:1m=1?5=4=8f;>6>4343om7=73:?:`g<40:165im539189<bc2:28707ke;1;7>;>lo084>529d297=5<50o:6>6<;<;f6?5?;272i>4<829>=`3=;19014k9:2:0?8?b?393?636e980<6=:1l31?5=4=8gb>6>4343nn7=73:?:af<40:165hj539189<cb2:28707i0;1;7>;>n8084>529g097=5<50l86>6<;<;e0?5?;272j84<829>=c0=;19014h8:2:0?8?a0393?636f880<6=:1oh1?5=4=8d`>6>4343mh7=73:?:b`<40:165kh539189d672:2870o?1;1;7>;f8;084>52a1197=5<5h:?6>6<;<;;3?5?;272454<829>==?=;190146n:2:0?8??j393?6368b80<6=:11n1?5=4=8:f>6>43433j7=73:?:=5<40:1654<539189<?42:2870764;1;7>;>1<084>5298497=5<503<6>6<;<;:<?5?;272544<829>=<g=;190147m:2:0?8?>l393?6369d80<6=:10l1?5=4=8c3>6>4343j=7=73:?:e7<40:165l=539189<g32:287p}60;296~X>8272<l4=b79~w=`=838pR5h4=82b>7d23ty3i7>52z\;a>;>8h09n95rs9f94?4|V1n014>n:3`0?xu?k3:1>vP7c:?:4d<5j81v5l50;35[>e34<?57=78:?50=<40116:99539:893212:23708;5;1;<>;1<=08455265197=><5<i<6?l>;<43g?4e:27=4?4<899>2d0=;1201;o=:2:;?80>m39346399`80<==:>0<1?564=7;1>6>?34<3i7=78:?5<d<40116:58539:8931a2:23707?a;0a6>{t0h0;6:uQ8`9><a>=9?30157<:7a89=?42hn0156l:3`1?8>a;38i:637d680<6=z{131<7;t^9;89=>52?i0156=:`f89=1>2;h9706i3;0a1>{t010;6?uQ899><c5=:k>0q~68:181[>0342m?7<m3:ped<72;hpRlo4=66e>3e<5>?<6;m4=60e>3e<5>9;6;m4=612>3e<5>996;m4=662>3e<5>>96;m4=660>3e<5>>?6;m4=605>3e<5>8<6;m4=671>3e<5>?86;m4=63e>3e<5>8;6;m4=67;>3e<5>?26;m4=673>3e<5><26;m4=653>3e<5>=:6;m4=651>3e<5>=86;m4=657>3e<5>=>6;m4=655>3e<5>=<6;m4=65;>3e<5><j6;m4=64a>3e<5><h6;m4=64g>3e<5><n6;m4=64e>3e<5>=26;m4=903>7d53429=7<m2:?;67<4j;164?=53c089=432:h9706i3;0a5>{ti00;69uQa89>=2b=>j165:656b9><c5=:k80q~o7:181[g?342m>7<m6:pe2<728npRl94=63:>7d434<?578l;<47<?0d34<?;78l;<472?0d34<?978l;<470?0d34<??78l;<435?0d34?mi78l;<7ee?0d34?m:78l;<7e6?0d34?ni78l;<7fe?0d34?n:78l;<40<?0d34<8978l;<405?0d34<9h78l;<41=?0d34<9978l;<415?0d342m>7<m5:?50d<6<o16:9l515d8932d28>m708;d;37b>{ti?0;6:uQa79><`4=>j164h<5ae9>=5c=im165<=52c089=bd2;h9706i2;0a0>{ti<0;69uQa49>=45=:k;015h=:3`0?8?7938i=6s|9b83>7}Y1j164k<52c38yv?6290>wS7>;<;4`?gc34k3:7=m4:?42<<fl273j?4=b39~w=0=83<8wS69;<;4`?0a343<478i;<c;2?5e;2729o492:?;a7<1:272<h492:?:4c<1:272<i492:?:0`<1:2728o492:?:02<1:2728>492:?:7c<1:272?o492:?:72<1:272?>492:?:6c<1:272>o492:?;=6<1:2734?492:?40c<1n27<9:49f:?46c<1n27<?=49f:?474<1n27<??49f:?404<1n27<8?49f:?406<1n27<8949f:?463<1n27<>:49f:?417<1n27<9>49f:?45c<1n27<>=49f:?41=<1n27<9449f:?415<1n27<:4492:?435<1:27<;<492:?437<1:27<;>492:?431<1:27<;8492:?433<1:27<;:492:?43=<1:27<:l492:?42g<1:27<:n492:?42a<1:27<:h492:?42c<1:27<;449f:?;67<4j:164?=53c189=432:h8708;9;41?80303<9708;7;41?803>3<9708;5;41?803<3<9708;3;41?80?:3<9708n6;41?80f:3<97086e;41?80>i3<970866;41?80>:3<97087e;41?80?i3<970876;41?800n3<9708?1;41?83am3<970;ia;41?83a>3<970;i2;41?83bm3<970;ja;41?83b>3<9708<8;41?804=3<9708<1;41?805l3<9708=9;41?805=3<9708=1;41?8>c?3<9706k6;41?803i3==708;b;55?803k3==708;d;55?xu1n3:1>k=t^7d89<122?80146;:7089<102?80146?:7089<1e2?801496:7089<1b2?8019:8:70891?22?8019om:70891e62?8019j8:70891cc2?8018><:708907>2?8018<i:70890222?8019;k:70891142?80196::70891>02?801966:70891>e2?80196k:70891>a2?80197>:70891?42?801978:70891?>2?80197m:70891?c2?80197i:70891g62?8019o<:70891g22?8019o8:70891g>2?8019ok:70891ga2?8019l>:70891d42?8019l::70891d02?8019l6:70891de2?8019lk:70891da2?8019m<:70891e22?8019m8:70891e>2?8019mm:70891ec2?8019mi:70891b62?8019j<:70891b22?8019j6:70891be2?8019jk:70891ba2?8019k>:70891c42?8019k::70891c02?8019k6:70891ce2?8019ki:70891`62?8019h<:70891`22?8019h8:70891`>2?8019hm:70891`c2?8019hi:70890662?8018>::70890602?8018>6:708906e2?8018>k:708906a2?8018?>:70890742?8018?::70890702?8018?m:708907c2?8018?i:70890462?8018<<:70890422?8018<8:708904>2?8018<m:708904c2?8018=>:70890542?8018=::70890502?8018=6:708905e2?8018=k:708905a2?8018:>:70890242?8019:6:708912e2?8019:k:708912a2?8019;>:70891342?8019;::70891302?8019;6:708913e2?8019;i:70891062?80198<:70891022?801988:708910>2?80198m:708910c2?80198i:70891162?80199::70891102?801996:708911e2?80199k:708911a2?80196>:70891>42?8019:9:7d891?32?l019on:7d891e72?l019j9:7d891cd2?l018>=:7d8907?2?l018<j:7d890232?l019;l:7d891152?l0196;:7d891>12?l01967:7d891>f2?l0196l:7d891>b2?l0197?:7d891?52?l01979:7d891??2?l0197n:7d891?d2?l0197j:7d891g72?l019o=:7d891g32?l019o9:7d891g?2?l019ol:7d891gb2?l019l?:7d891d52?l019l;:7d891d12?l019l7:7d891df2?l019ll:7d891db2?l019m=:7d891e32?l019m9:7d891e?2?l019mn:7d891ed2?l019mj:7d891b72?l019j=:7d891b32?l019j7:7d891bf2?l019jl:7d891bb2?l019k?:7d891c52?l019k;:7d891c12?l019k7:7d891cf2?l019kj:7d891`72?l019h=:7d891`32?l019h9:7d891`?2?l019hn:7d891`d2?l019hj:7d890672?l018>;:7d890612?l018>7:7d8906f2?l018>l:7d8906b2?l018??:7d890752?l018?;:7d890712?l018?n:7d8907d2?l018?j:7d890472?l018<=:7d890432?l018<9:7d8904?2?l018<n:7d8904d2?l018=?:7d890552?l018=;:7d890512?l018=7:7d8905f2?l018=l:7d8905b2?l018:?:7d890252?l019:7:7d8912f2?l019:l:7d8912b2?l019;?:7d891352?l019;;:7d891312?l019;7:7d8913f2?l019;j:7d891072?l0198=:7d891032?l01989:7d8910?2?l0198n:7d8910d2?l0198j:7d891172?l0199;:7d891112?l01997:7d8911f2?l0199l:7d8911b2?l0196?:7d891>52?l01l69:9189=c>2?8015kn:7089=b22?8015m=:7089=e62?8015m?:7089=da2?8015lj:7089=dc2?8015ll:7089=de2?8015ln:7089=d>2?8014?9:7089<722?8015jk:7089=c62?8015k?:7089=0c2?80158j:7089=0a2?80159?:7089=162?80159=:7089=142?80159;:7089=>c2?80157=:7089=?72?80157>:7089=1f2?80156>:7089=1c2?80159j:7089=1a2?80156?:7089=352?8015;<:7089=2b2?801:?m:708927d2?8015;?:7089=362?801:<m:708925c2?801:?k:708921d2?801:9n:708921a2?801:9k:70892>52?801:6?:70892>22?801:6<:70892>?2?801:69:70892>e2?801:66:70892>b2?801:6l:70892?62?801:6i:70892?32?801:7=:70892?02?801:7::7089=742?8015??:7089=6d2?8015>7:7089=632?8015>?:70892`d2?801:h7:70892`32?801:h?:70892ea2?801:ml:70892e?2?801:m;:70892e72?801:ll:70892d?2?801:l;:70892d72?801:ol:7089=45219015<<:9189=43219015kl:7089=cb2?8014;l:7089=b42?801o68:7089f2a2?801n:j:7089f2c2?801n:l:7089f2e2?801n:n:7089f2>2?801n:7:7089f212?801n:::7089f232?801n:<:7089f252?801n:>:7089f272?801n=i:7089f5b2?801n=k:7089f5e2?801n=n:7089f5>2?801n=7:7089f502?801n=9:7089f522?801n=;:7089f542?801n==:7089fga2?801noj:7089fgc2?801nol:7089fge2?801non:7089fg>2?801no7:7089fg02?801no9:7089fg32?801no<:7089fg52?801no>:7089fg72?801n7i:7089f?b2?801n7k:7089f?d2?801n7m:7089f?>2?801n77:7089f?02?801n79:7089f?22?801n7;:7089f?42?801n7=:7089f?62?801n7?:7089f>b2?801n6k:7089f>d2?801n6m:7089f>f2?801n66:7089f>?2?801n68:7089f>12?801n6::7089f>42?801n6=:7089f>62?801n6?:7089f1a2?801n9j:7089f1c2?801n9l:7089f1e2?801n9n:7089f1?2?801n98:7089f112?801n9::7089f132?801n9<:7089f152?801n9>:7089f172?801n8i:7089f0c2?801n8l:7089f0e2?801n8n:7089f0>2?801n87:7089f002?801n89:7089f022?801n8;:7089f052?801n8>:7089f072?801n;i:7089f3b2?801n;k:7089f3d2?801n;m:7089f3f2?801n;6:7089f302?801n;9:7089f322?801n;;:7089f342?801n;=:7089f362?801n;?:7089f202?801n=l:7089fd72?801no::7089f?f2?801n6i:7089f>32?801n96:7089f0b2?801n8<:7089f3?2?801n=>:7089d612?801l<k:7089d5?2?801l:<:7089d2b2?801l;6:7089d032?801l8i:7089d1f2?801l6::7089d762?801l?l:7089d422?801l<9:7089d402?801l<7:7089d4>2?801l<n:7089d4e2?801l<l:7089d4b2?801l<i:7089d572?801l=>:7089d552?801l=<:7089d532?801l=::7089d512?801l=8:7089d5>2?801l=n:7089d5e2?801l=l:7089d5c2?801l=j:7089d5a2?801l:?:7089d262?801l:=:7089d232?801l:::7089d212?801l:8:7089d2?2?801l:6:7089d2f2?801l:m:7089d2d2?801l:k:7089d2a2?801l;?:7089d362?801l;=:7089d342?801l;;:7089d322?801l;9:7089d302?801l;7:7089d3f2?801l;m:7089d3d2?801l;k:7089d3b2?801l;i:7089d072?801l8>:7089d052?801l8<:7089d022?801l89:7089d002?801l87:7089d0>2?801l8n:7089d0e2?801l8l:7089d0c2?801l8j:7089d172?801l9>:7089d152?801l9<:7089d132?801l9::7089d112?801l98:7089d1?2?801l96:7089d1e2?801l9l:7089d1c2?801l9j:7089d1a2?801l6?:7089d>62?801l6=:7089d>42?801l6;:7089d602?801l>7:7089d6>2?801l>n:7089d6e2?801l>l:7089d6c2?801l>j:7089d6a2?801l??:7089d752?801l?<:7089d732?801l?::7089d712?801l?8:7089d7?2?801l?6:7089d7f2?801l?m:7089d7c2?801l?j:7089d7a2?801l<?:7089d462?801l<=:7089d442?801l<;:7089<>12?8014ok:7089<d?2?8014m<:7089<eb2?8014j6:7089<c32?8014ki:7089<`f2?801l>::7089<?62?80147l:7089<g22?8014o9:7089<g02?8014o7:7089<g>2?8014on:7089<ge2?8014ol:7089<gb2?8014oi:7089<d72?8014l>:7089<d52?8014l<:7089<d32?8014l::7089<d12?8014l8:7089<d>2?8014ln:7089<de2?8014ll:7089<dc2?8014lj:7089<da2?8014m?:7089<e62?8014m=:7089<e32?8014m::7089<e12?8014m8:7089<e?2?8014m6:7089<ef2?8014mm:7089<ed2?8014mk:7089<ea2?8014j?:7089<b62?8014j=:7089<b42?8014j;:7089<b22?8014j9:7089<b02?8014j7:7089<bf2?8014jm:7089<bd2?8014jk:7089<bb2?8014ji:7089<c72?8014k>:7089<c52?8014k<:7089<c22?8014k9:7089<c02?8014k7:7089<c>2?8014kn:7089<ce2?8014kl:7089<cc2?8014kj:7089<`72?8014h>:7089<`52?8014h<:7089<`32?8014h::7089<`12?8014h8:7089<`?2?8014h6:7089<`e2?8014hl:7089<`c2?8014hj:7089<`a2?801l>?:7089d662?801l>=:7089d642?801l>;:7089<>02?801467:7089<>>2?80146n:7089<>e2?80146l:7089<>c2?80146j:7089<>a2?80147?:7089<?52?80147<:7089<?32?80147::7089<?12?801478:7089<??2?801476:7089<?f2?80147m:7089<?c2?80147j:7089<?a2?8014o?:7089<g62?8014o=:7089<g42?8014o;:7089=bb2?8015ji:7089<752?80157m:7089=>a2?80156j:7089=1d2?80159m:708932f2>h01;:m:6`8932d2>h01;:k:6`8yvg32909wSo;;<52=?50k2wx?:=50;ff8b1<3;=563;47801>;31=08963;a`801>;3k908963;d7801>;3mj08963:03801>;29108963:2d801>;2<=08963;5b801>;3?;08963;85801>;30?08963;89801>;30h08963;8b801>;30l08963;91801>;31;08963;97801>;31108963;9`801>;31j08963;9d801>;3i908963;a3801>;3i=08963;a7801>;3i108963;ab801>;3il08963;b1801>;3j;08963;b5801>;3j?08963;b9801>;3jh08963;bb801>;3jl08963;c3801>;3k=08963;c7801>;3k108963;c`801>;3kj08963;cd801>;3l908963;d3801>;3l=08963;d9801>;3lh08963;db801>;3ll08963;e1801>;3m;08963;e5801>;3m?08963;e9801>;3mh08963;ed801>;3n908963;f3801>;3n=08963;f7801>;3n108963;f`801>;3nj08963;fd801>;28908963:05801>;28?08963:09801>;28h08963:0b801>;28l08963:11801>;29;08963:15801>;29?08963:1`801>;29j08963:1d801>;2:908963:23801>;2:=08963:27801>;2:108963:2`801>;2:j08963:31801>;2;;08963:35801>;2;?08963:39801>;2;h08963:3b801>;2;l08963:41801>;2<;08963;49801>;3<h08963;4b801>;3<l08963;51801>;3=;08963;55801>;3=?08963;59801>;3=h08963;5d801>;3>908963;63801>;3>=08963;67801>;3>108963;6`801>;3>j08963;6d801>;3?908963;75801>;3??08963;79801>;3?h08963;7b801>;3?l08963;81801>;30;0896364`8a4>;><?0i<636438a4>;>;l0i<6363`8a4>;>;?0i<636338a4>;>:l0i<6362`8a4>;?1j09n<5288a96g5<5>;o6>67;<:3b?d7342;n7l?;<:33?d7342;?7l?;<5eb?d734=mn7l?;<5e3?d734=m?7l?;<5fb?d734=hn7l?;<5`3?d734=h?7l?;<5ab?d734=in7l?;<5a3?d734=i?7l?;<5bb?d734=jn7l?;<4b1?d734<j=7l?;<4:`?d734<257l?;<4:1?d734<2=7l?;<4;`?d734<357l?;<4;1?d734<<i7l?;<7e`?d734?m57l?;<7e1?d734?m=7l?;<7f`?d734?n57l?;<7f1?d734<887l?;<404?d734<9o7l?;<41<?d734<987l?;<414?d73422n7ok;<47e?b3927=8l4<b89>21g=;k201;:n:e66?803i3n??6394`8g07=:>=h1h9?4=76a>6d>34<?n7=m8:?50g<c<<16:9l5d518932e2m>9708;c;f75>;1<j08n45265a97g><5?>h6i::;<47g?b3;27=8n4k439>21b=nh16:9j53c;8932c2:h3708;d;f71>;1<m0o8>5265f9`14<5?>o6i:>;<47`?ce34<?h7k6;<47`?c034<?h7k9;<47`?c234<?h7k;;<47`?c434<?h7k=;<47`?c634<?h7k?;<47`?ba34<?h7jj;<47`?bd34<?h7hl;|q:3c<72;q65:k5ae9>=2b=;1?0q~78a;296~;>?00jh6367980<0=z{0=h6=4={<;4f?gc343<57=75:p==7=838p146?:`f89<1b2:2>7p}68383>6}:1>=1mi5296`97=3<50==6?l>;|q:<6<72;q65:j539489<1?2hn0q~775;296~;f0?09mi52b959ea=z{k236=4={<;;0?gc34h3;7=75:pf=?=839p146;:2:6?8?0l39970788;11?xue0h0;6?u29679ea=:11:1?5;4}r``0?6=:r7?4>4<849>21b=lk1vom<:18182?939396394e8ge>{tjj81<7<t=55e>6>234<?h7j6;|qag4<72;q68:j53978932d2oi0q~ll0;296~;3?k08485265a9ag=z{khm6=4={<64=?5?=27=8n4j9:pfgc=838p1998:2:6?803k3o<7p}mbe83>7}:<>?1?5;4=76`>`0<uzhin7>52z?734<40<16:9m5e49~wgdf2909w0:9f;1;1>;1<j0n86s|bc;94?4|5=<o6>6:;<47g?c43tyin54?:3y>03d=;1?01;:l:d08yvde?3:1>v3;6880<0=:>=i1jl5rsc`5>5<5s4>=;7=75:?50f<b92wxno;50;0x91022:2>708;c;g3?xuej=0;6?u247197=3<5?>h6ih4}r`a7?6=:r7?:<4<849>21e=ll1vol=:181822n39396394b8gg>{tjk:1<7<t=57a>6>234<?o7jm;|qaec<72;q688753978932d2mk0q~lne;296~;3=>08485265a9`<=z{kko6=4={<661?5?=27=8o4ic:pfde=838p19;<:2:6?803j3oi7p}mac83>7}:<<;1?5;4=76a>`?<uzhjm7>52z?70c<40<16:9l5e69~wgg>2909w0:;d;1;1>;1<k0n:6s|b`:94?4|5=>i6>6:;<47f?c23tyim:4?:3y>01?=;1?01;:m:d68yve5<3:1>v3:4280<0=:>=h1i>5rsb00>5<5s4??=7=75:?50g<b:2wxo?<50;0x905a2:2>708;b;db?xud:80;6?u252f97=3<5?>i6h?4}ra14?6=:r7>?o4<849>21d=m91vn?i:181834139396394c8gb>{tk8o1<7<t=414>6>234<?n7jj;|q`5a<72;q69>;53978932e2mi0q~m>c;296~;2;:08485265`9`g=z{j;i6=4={<705?5?=27=8o4ka:pg4?=838p18<k:2:6?803j3n27p}l1983>7}:=;h1?5;4=76b>ce<uzi:;7>52z?66<<40<16:9o5ec9~wf712909w0;=7;1;1>;1<h0n56s|c0794?4|5<8>6>6:;<47e?c03tyh=94?:3y>175=;1?01;:n:d48yve6;3:1>v3:2080<0=:>=k1i85rsb31>5<5s4?:j7=75:?50d<b<2wxo<?50;0x907c2:2>708;a;g0?xud990;6?u250`97=3<5?>j6h<4}ra3a?6=:r7>=:4<849>21g=nh1vn>k:181836=39396394`8f5>{tk9i1<7<t=430>6>234<?m7k?;|q`4g<72;q69<?53978932f2ml0q~m?a;296~;28o08485265c9``=z{j:26=4={<73`?5?=27=8l4kc:pg5>=838p18>m:2:6?803i3ni7p}l0683>7}:=931?5;4=76b>ag<uzi;:7>52z?642<40<16:9o5d89~wf622909w0;?5;1;1>;1<m0m56s|c1194?4|5<::6>6:;<47`?b?3tyh<?4?:3y>0c`=;1?01;:k:e58yve793:1>v3;fe80<0=:>=n1h;5rsb23>5<5s4>mn7=75:?50a<c=2wxnkh50;0x91`>2:2>708;d;f7?xuenl0;6?u24g597=3<5?>o6i=4}r`e`?6=:r7?j84<849>21b=n;1vohl:18182a;39396394e8e5>{tjoh1<7<t=5d2>6>234<?h7h7;|qabd<72;q68hh53978932c2o:0q~li8;296~;3mk08485265f9ac=z{kl<6=4={<6f=?5?=27=8i4je:pfc0=838p19k8:2:6?803l3oo7p}mf483>7}:<l?1?5;4=76g>`e<uzhm87>52z?7a6<40<16:9j5e99~wg`42909w0:j1;1;1>;1<m0oh6s|bg094?4|5=nm6>6:;<47`?b53tyij<4?:3y>0ab=;1?01;:l:g;8yvda83:1>v3;dc80<0=:>=i1h55rscge>5<5s4>o57=75:?50f<c?2wxnhj50;0x91b22:2>708;c;f5?xuemj0;6?u24e197=3<5?>h6i;4}r`ff?6=:r7?h<4<849>21e=l=1vokn:18182dn39396394b8g7>{tjl31<7<t=5ag>6>234<?o7h=;|qaa=<72;q68nl53978932d2o;0q~lj7;296~;3k008485265a9b==z{ko=6=4={<6`3?5?=27=8n4i0:pf`3=838p19m::2:6?803k3om7p}me583>7}:<j91?5;4=76`>`c<uzhn>7>52z?7fc<40<16:9m5ee9~wgc62909w0:md;1;1>;1<j0no6s|bd294?4|5=hi6>6:;<47g?c?3tyihk4?:3y>0g?=;1?01;:l:ef8yvdcm3:1>v3;b680<0=:>=i1h?5rscfg>5<5s4>i97=75:?50g<a12wxnim50;0x91d42:2>708;b;f;?xuelk0;6?u24c397=3<5?>i6i94}r`ge?6=:r7?mk4<849>21d=l?1voj6:18182fl39396394c8g1>{tjm=1<7<t=5c:>6>234<?n7j;;|qa`3<72;q68l953978932e2m90q~lk5;296~;3i<08485265`9b7=z{kn?6=4={<6b7?5?=27=8o4i1:pfa5=838p19o>:2:6?803j3l37p}md383>7}:<0l1?5;4=76a>c6<uzho=7>52z?7=a<40<16:9l5eg9~wgb72909w0:6b;1;1>;1<k0ni6s|bbd94?4|5=326>6:;<47f?cc3tyioh4?:3y>0<1=;1?01;:m:da8yvddk3:1>v3;9280<0=:>=h1i55rscaa>5<5s4>2=7=75:?50g<cl2wxnno50;0x91>a2:2>708;b;f1?xuek00;6?u249f97=3<5?>j6k74}r``<?6=:r7?4o4<849>21g=l11vom8:18182?139396394`8g3>{tjj<1<7<t=5:4>6>234<?m7j9;|qag0<72;q685;53978932f2m?0q~lmc;296~;3?:08485265c9`1=z{kh:6=4={<66`?5?=27=8l4k3:pg73=838p18:::2:6?803i3l97p}l1`83>7}:=;l1?5;4=76b>c7<uzi;j7>52z?65<<40<16:9o5f99~wf632909w0;?3;1;1>;1<h0m<6s|bg;94?4|5=oo6>6:;<47e?ca3tyiih4?:3y>0a1=;1?01;:n:dg8yvdb;3:1>v3;c080<0=:>=k1ii5rscf;>5<5s4>jn7=75:?50d<bk2wxnnj50;0x91?22:2>708;a;g;?xuei?0;6?u245597=3<5?>j6ij4}ra04?6=9<q65:;539789=2a2;h:709;f;17?812?39?709=f;1:?8148392709<1;1:?814:392709;1;1:?813:392709;3;1:?813<392709=6;1:?815?392709:2;1:?812;392709>f;1:?8158392709:8;1:?8121392709:0;1:?xue0j0;6<:t=854>6>234=?j7=:;<563?5234=9j7=n;<504?5f34=8=7=n;<506?5f34=?=7=n;<576?5f34=??7=n;<570?5f34=9:7=n;<513?5f34=>>7=n;<567?5f34=:j7=n;<514?5f34=>47=n;<56=?5f34=><7=n;|q`6c<72;q6;<752c389<3e2:2>7p}l2b83>6}:1>?1?564=951>6>2342<?7ok;|q`6g<72=q655>539:89<1e2:2370681;1;1>;??;0jh6s|c3c94?3|50=<6>67;<;4=?5?0272;h4<899><26=;1?0159>:`f8yve513:1?v368580=7=:0?l1?5;4=953>db<uzi947>53z?;2`<40<164;h5ae9>f=1=;190q~m=7;29<~;f0?085=528e79ea=:19i1>o:4=94g>6>2342=i7ok;<::a?4e:2729n4<899><a5=;120q~m=e;297~;??=08485270a97=><51?:6>67;|q`6a<72;=p159<:2:6?8>0<3ko709>b;1;<>;?=908455273`97=><5>9o6>67;<54g?5?027<;l4<899>32`=;1201:9k:2:;?81?:39346388180<==:?1?1?564=6:0>6>?34=347=78:?4<3<40116;5l539:892>>2:237097e;1;<>;00j08455278397=><5>2m6>67;<5:0?5?027<5?4<899>3<1=;1201:7::2:;?8>6;39346371180<==:09i1?564=92;>6>?342;87=78:?;45<40116;km539:892`?2:23709i4;1;<>;0n908455283097<6<51886>7?;<:10?5>82wxn5l50;378>d:3934637c080<==:0j:1?564=9`e>6>?342ii7=78:?;fa<401164om539:89=de2:23706ma;1;<>;?j008455290497=><50;>6>67;<:g<?>33422i7<m1:?;3c<40<1645>5ae9><`e=;12015kj:2:;?8>c<38i>637d78;0>{tjh>1<7;t=6;6>6>234<?m7;;;<47f?3334<?o7;;;<47`?333tyim>4?:4y>3<4=;1?01;:n:418932e2<901;:l:418932c2<90q~ln2;291~;00o08485265c917=:>=h19?5265a917=:>=n19?5rscc2>5<2s4=3o7=75:?50d<2927=8o4:1:?50f<2927=8i4:1:pfd6=83?p1:66:2:6?803i3?;708;b;73?803k3?;708;d;73?xue1o0;68u279497=3<5?>j68h4=76a>0`<5?>h68h4=76g>0`<uzh2i7>55z?4<6<40<16:9o55d9>21d==l16:9m55d9>21b==l1vo7k:18681?839396394`86`>;1<k0>h6394b86`>;1<m0>h6s|b8a94?3|5>=o6>6:;<47e?3d34<?n7;l;<47g?3d34<?h7;l;|qa=g<72<q6;:o53978932f2<h01;:m:4`8932d2<h01;:k:4`8yvd>13:1=;u29049ea=:?:n1?5;4=96e>7d434=?j7=<;<563?5434=9j7=7;<504?5?34=8=7=7;<506?5?34=?=7=7;<576?5?34=??7=7;<570?5?34=9:7=7;<513?5?34=>>7=7;<567?5?34=:j7=7;<514?5?34=>47=7;<56=?5?34=><7=7;|qa==<728<p14?::`f8924e2:2>706;f;0a6>;0<o08>63856806>;0:o08;63831803>;0;808;63833803>;0<808;63843803>;0<:08;63845803>;0:?08;63826803>;0=;08;63852803>;09o08;63821803>;0=108;63858803>;0=908;6s|b8594?0|51i96lj4=6;5>7d6342:?7=75:?;51<5j8164?=52`a89=432;kh7p}m9783>3}:0j;1mi5278196g7<51;;6>6:;<:25?4e9273>>4=a19><72=:h:0q~l65;292~;?k90jh6389181f4=:09i1?5;4=92g>7d63429?7<65:?;61<51<1vo7;:1858>en3ko7097d;0a5>;?8108485281;96g7<51886?6n;<:10?4?i2wxn4=50;4x9=db2hn01:6n:3`2?8>7<39396370481f4=:0;91>:h4=907>71a3tyi5?4?:7y><gb=im16;5952c389=672:2>706?1;0a5>;?::09;9528369622<uzh2=7>56z?;ff<fl27<494=b09>3ce=;1?01:hk:3`2?8>5;38=563725812<=z{k3;6=49{<:af?gc34=3=7<m1:?4b=<40<16;k752c389=442;>2706=4;07=>{tj1l1<78t=9`b>db<5>=n6?l>;<5e0?5?=27<j84=b09><75=9mk015<;:0fb?xue0l0;6;u28c;9ea=:?>h1>o?4=6d3>6>234=m=7<m1:?;66<6>k164?:517`8yvdf=3:1=<u270a97=3<5?>j6i:9;<47e?b3i27=8l4k499>21g=l==01;:m:e65?803j3n?m6394c8g0==:>=h1h994=76`>a2134<?o7j;a:?50f<c<116:9m5d558932c2m>=708;d;f7e>;1<m0o855265f9`11<uzh2m7>53z?;14<40<1658j52c08932f2m80q~l7d;297~;?1j09n?5270f97=3<51om6?l=;|q`63<72;q6;<752c0893072:=h7p}lcg83>6}:<181mi52c5d97=3<50k?6lj4}ra`a?6=;r7?4=4nd:?`0`<40<165l=5ae9~wfec2908w0:8e;cg?8e3l3939636a38b`>{tkji1<7=t=55`>db<5j>h6>6:;<;b5?gc3tyhoo4?:2y>02g=im16o9l539789<g72hn0q~mla;297~;3?10jh63l4`80<0=:10l1mi5rsba:>5<4s4><:7ok;<a7=?5?=2725h4nd:pgf>=839p199;:`f89f2?2:2>7076d;cg?xudk?0;6>u24629ea=:k=<1?5;4=8;a>db<uzih97>53z?72`<fl27h884<849>=<g=im1vnm;:180821k3ko70m;4;1;1>;>100jh6s|cb194?5|5=<j6lj4=b60>6>2343247ok;|q`g7<72:q68;65ae9>g14=;1?01478:`f8yved93:1?v3;678b`>;d<80848529849ea=z{ji;6=4<{<650?gc34i?<7=75:?:=0<fl2wxooh50;1x91052hn01n=i:2:6?8?><3ko7p}lbd83>6}:<?:1mi52c2g97=3<50386lj4}raa`?6=;r7?9h4nd:?`7a<40<1654<5ae9~wfde2908w0::a;cg?8e4j3939636918b`>{tkkk1<7=t=57;>db<5j9j6>6:;<;;b?gc3tyhn44?:2y>000=im16o>7539789<>b2hn0q~mm8;297~;3==0jh63l3980<0=:11n1mi5rsb`4>5<4s4>>>7ok;<a03?5?=2724n4nd:pgg0=839p19;?:`f89f512:2>7077b;cg?xudj<0;6>u245g9ea=:k:?1?5;4=8:b>db<uzii87>53z?70f<fl27h?94<849>==?=im1vnl<:180823i3ko70m<3;1;1>;>010jh6s|cc094?5|5=>36lj4=b11>6>23433;7ok;|qg6c<72:q699<5ae9>gd`=;1?01l>;:`f8yvb5m3:1?v3:418b`>;dil084852a119ea=z{m8o6=4<{<70a?gc34ijh7=75:?b47<fl2wxh?m50;1x905d2hn01nol:2:6?8g793ko7p}k2c83>6}:=:k1mi52c``97=3<5h:;6lj4}rf1e?6=;r7>?54nd:?`ed<40<165kh5ae9~wa4>2908w0;<6;cg?8ef13939636fd8b`>{tl;21<7=t=417>db<5jk36>6:;<;e`?gc3tyo>:4?:2y>164=im16ol9539789<`d2hn0q~j=6;297~;2;90jh63la780<0=:1oh1mi5rse07>5<4s4?9o7ok;<ab0?5?=272j44nd:p`75=839p18<n:`f89fg42:2>707i8;cg?xuc:;0;6>u253:9ea=:kh81?5;4=8d4>db<uzn9=7>53z?663<fl27hm<4<849>=c0=im1vi<?:180835<3ko70mn0;1;1>;>n<0jh6s|d0d94?5|5<896lj4=b;e>6>2343m87ok;|qg5`<72:q69?>5ae9>g<c=;1?014h<:`f8yvb6l3:1?v3:1d8b`>;d1m0848529g09ea=z{m;h6=4<{<72g?gc34i2o7=75:?:b4<fl2wxh<l50;1x907f2hn01n7m:2:6?8?a83ko7p}k1883>6}:=8<1mi52c8;97=3<50on6lj4}rf2<?6=;r7>=94nd:?`==<40<165hj5ae9~wa702908w0;>2;cg?8e>?3939636eb8b`>{tl8<1<7=t=433>db<5j3=6>6:;<;ff?gc3tyo=84?:2y>15c=im16o4;539789<cf2hn0q~j>4;297~;28j0jh63l9580<0=:1l31mi5rse30>5<4s4?;m7ok;<a:7?5?=272i54nd:p`44=839p18>7:`f89f?52:2>707j7;cg?xuc980;6>u25149ea=:k0;1?5;4=8g5>db<uzn:<7>53z?641<fl27h5=4<849>=`3=im1vi>j:18083783ko70m7e;1;1>;>m:0jh6s|d1f94?5|5=ln6lj4=b:g>6>2343n>7ok;|qg4f<72:q68km5ae9>g=e=;1?014k>:`f8yvb7j3:1?v3;f`8b`>;d0k0848529d29ea=z{m:j6=4<{<6e<?gc34i3m7=75:?:`c<fl2wxh=750;1x91`12hn01n66:2:6?8?cm3ko7p}k0983>6}:<o>1mi52c9:97=3<50no6lj4}rf33?6=;r7?j?4nd:?`<2<40<165im5ae9~wa612908w0:i0;cg?8e?>3939636dc8b`>{tl9?1<7=t=5gf>db<5j2>6>6:;<;ge?gc3tyo<>4?:2y>0`g=im16o5=539789<b?2hn0q~j?2;297~;3m10jh63l8380<0=:1m=1mi5rse22>5<4s4>n:7ok;<a;5?5?=272h;4nd:p`56=839p19k;:`f89f>72:2>707k5;cg?xudno0;6>u24d09ea=:k>l1?5;4=8f7>db<uzimi7>53z?7a5<fl27h;h4<849>=a5=im1vnhk:18082cm3ko70m8d;1;1>;>l;0jh6s|cga94?5|5=nh6lj4=b5`>6>2343o=7ok;|q`bg<72:q68io5ae9>g2d=;1?014j?:`f8yveai3:1?v3;d98b`>;d?h0848529bd9ea=z{jl36=4<{<6g0?gc34i<47=75:?:ga<fl2wxok950;1x91b52hn01n98:2:6?8?dk3ko7p}lf783>6}:<m:1mi52c6497=3<50ii6lj4}rae1?6=;r7?oh4nd:?`30<40<165no5ae9~wf`32908w0:lc;cg?8e0<3939636c88b`>{tko91<7=t=5ab>db<5j=86>6:;<;`<?gc3tyhj?4?:2y>0f>=im16o:<539789<e02hn0q~mi1;297~;3k?0jh63l7080<0=:1j<1mi5rsbd3>5<4s4>h87ok;<a44?5?=272o84nd:pg``=839p19m=:`f89f0a2:2>707l4;cg?xudmm0;6>u24cg9ea=:k?n1?5;4=8a1>db<uzino7>53z?7ff<fl27h:n4<849>=f7=im1vnkm:18082ei3ko70m9b;1;1>;>k90jh6s|cdc94?5|5=h36lj4=b4b>6>2343ij7ok;|q`a<<72:q68o85ae9>g3?=;1?014lj:`f8yveb03:1?v3;b58b`>;d>10848529cf9ea=z{jo<6=4<{<6a6?gc34i=;7=75:?:ff<fl2wxoh850;1x91d72hn01n89:2:6?8?ej3ko7p}le483>6}:<ho1mi52c7797=3<50hj6lj4}raf0?6=;r7?mn4nd:?`21<40<165o75ae9~wfc52908w0:n8;cg?8e1:3939636b68b`>{tkl;1<7=t=5c5>db<5j<:6>6:;<;a2?gc3tyhi=4?:2y>0d2=im16o;>539789<d22hn0q~mkf;297~;3i;0jh63l5g80<0=:1k>1mi5rsbff>5<4s4>j<7ok;<a6a?5?=272n>4nd:pgab=839p197j:`f89f3c2:2>707m2;cg?xudlj0;6>u248a9ea=:k<i1?5;4=8`2>db<uzion7>53z?7=d<fl27h9o4<849>=g6=im1vnjn:18082>03ko70m:a;1;1>;>io0jh6s|ce;94?5|5=3=6lj4=b7:>6>2343ji7ok;|q``2<72:q684<5ae9>g01=;1?014ol:`f8yvec>3:1?v3;918b`>;d=?0848529``9ea=z{jn>6=4<{<6;a?gc34i>97=75:?:ed<fl2wxoi:50;1x91>d2hn01n;;:2:6?8?f13ko7p}ld283>6}:<1k1mi52c4197=3<50k36lj4}rag6?6=;r7?454nd:?`17<40<165l95ae9~wfb62908w0:76;cg?8e293939636a78b`>{tkm:1<7=t=5:7>db<5j?;6>6:;<;b1?gc3tyho:4?:2y>024=im16o99539789<?d2hn0q~mmc;297~;3=j0jh63l3b80<0=:10;1mi5rse13>5<4s4??87ok;<aa4?5?=27j<84nd:p`73=839p18<j:`f89fg22:2>707ia;cg?xuc9h0;6>u250:9ea=:k0k1?5;4=8ge>db<uzn;j7>53z?647<fl27h4k4<849>=`2=im1vi>;:18082bk3ko70m74;1;1>;>l00jh6s|cg;94?5|5=n=6lj4=b5:>6>2343hi7ok;|q`a`<72:q68n>5ae9>g3c=;1?014m<:`f8yveb;3:1?v3;a`8b`>;d>:0848529c:9ea=z{jn36=4<{<6:0?gc34i>47=75:?:ea<fl2wxoo?50;1x91212hn01n=>:2:6?8??>3ko7p}:6583>7}:<191mi5249097=3<uz?=?7>52z?7<4<fl27?4=4<849~w0052909w0:8f;cg?820m39396s|57394?4|5==o6lj4=55`>6>23ty>:=4?:3y>02d=im168:o53978yv32n3:1>v3;788b`>;3?108485rs47f>5<5s4><;7ok;<642?5?=2wx98j50;0x91122hn0199;:2:6?xu2=k0;6?u24639ea=:<>:1?5;4}r76e?6=:r7?:k4nd:?72`<40<1v8;6:181821l3ko70:9c;1;1>{t=<21<7<t=54a>db<5=<j6>6:;|q612<72;q68;75ae9>03>=;1?0q~;:6;296~;3>>0jh63;6780<0=z{<?>6=4={<651?gc34>=87=75:p102=838p198<:`f891052:2>7p}:5283>7}:<?;1mi5247297=3<uz?>>7>52z?71c<fl27?9h4<849~w0372909w0::b;cg?822i39396s|55d94?4|5=?26lj4=57;>6>23ty>8h4?:3y>001=im1688853978yv33l3:1>v3;548b`>;3==08485rs46`>5<5s4>>?7ok;<666?5?=2wx99l50;0x91362hn019;?:2:6?xu2<h0;6?u245d9ea=:<=o1?5;4}r77=?6=:r7?8i4nd:?70f<40<1v8:7:181823j3ko70:;a;1;1>{t===1<7<t=56:>db<5=>36>6:;|q6g1<72;q699=5ae9>114=;1?0q~;l3;296~;2<80jh63:4180<0=z{<i96=4={<70b?gc34?8i7=75:p1f7=838p18=k:`f8905d2:2>7p}:c183>7}:=:h1mi5252c97=3<uz?ij7>52z?67<<fl27>?54<849~w0db2909w0;<7;cg?834>39396s|5cf94?4|5<9>6lj4=417>6>23ty>nn4?:3y>165=im169><53978yv3ej3:1>v3:308b`>;2;908485rs4`:>5<5s4?9h7ok;<71g?5?=2wx9o650;0x904e2hn018<n:2:6?xu2j>0;6?u253;9ea=:=;21?5;4}r7a2?6=:r7>>:4nd:?663<40<1v8l::181835=3ko70;=4;1;1>{t=k>1<7<t=400>db<5<896>6:;|q6f6<72;q69??5ae9>176=;1?0q~;m2;296~;29o0jh63:1d80<0=z{<h:6=4={<72`?gc34?:o7=75:p1g6=838p18?m:`f8907f2:2>7p}:ad83>7}:=8=1mi5250497=3<uz?jh7>52z?650<fl27>=94<849~w0gd2909w0;>3;cg?836:39396s|5``94?4|5<;:6lj4=433>6>23ty>ml4?:3y>15`=im169=k53978yv3f13:1>v3:0e8b`>;28j08485rs4c;>5<5s4?;n7ok;<73e?5?=2wx9l950;0x906>2hn018>7:2:6?xu2i?0;6?u25159ea=:=9<1?5;4}r7b1?6=:r7><84nd:?641<40<1v8o<:18183793ko70;?0;1;1>{t=h81<7<t=5de>db<5=ln6>6:;|q6e4<72;q68kj5ae9>0ce=;1?0q~;n0;296~;3nk0jh63;f`80<0=z{<3m6=4={<6e=?gc34>m47=75:p1<c=838p19h8:`f891`12:2>7p}:9e83>7}:<o?1mi524g697=3<uz?2o7>52z?7b6<fl27?j?4<849~w0?e2909w0:i1;cg?82a839396s|58c94?4|5=om6lj4=5gf>6>23ty>554?:3y>0`d=im168ho53978yv3>?3:1>v3;e88b`>;3m108485rs4;5>5<5s4>n;7ok;<6f2?5?=2wx94;50;0x91c22hn019k;:2:6?xu21=0;6?u24d19ea=:<l81?5;4}r7:7?6=:r7?i<4nd:?7a5<40<1v87=:18182cn3ko70:ke;1;1>{t=0;1<7<t=5fg>db<5=nh6>6:;|q6=5<72;q68il5ae9>0ag=;1?0q~;7f;296~;3l00jh63;d980<0=z{<2o6=4={<6g1?gc34>o87=75:p1=e=838p19j<:`f891b52:2>7p}:8c83>7}:<m;1mi524e297=3<uz?3m7>52z?7gc<fl27?oh4<849~w0>>2909w0:ld;cg?82dk39396s|59:94?4|5=ii6lj4=5ab>6>23ty>4:4?:3y>0f?=im168n653978yv3?>3:1>v3;c68b`>;3k?08485rs4:6>5<5s4>h97ok;<6`0?5?=2wx95:50;0x91e42hn019m=:2:6?xu20;0;6?u24cd9ea=:<ko1?5;4}r7;5?6=:r7?ni4nd:?7ff<40<1v86?:18182ej3ko70:ma;1;1>{t=>l1<7<t=5`:>db<5=h36>6:;|q63`<72;q68o95ae9>0g0=;1?0q~;8d;296~;3j<0jh63;b580<0=z{<=h6=4={<6a7?gc34>i>7=75:p12d=838p19l>:`f891d72:2>7p}:7`83>7}:<hl1mi524`g97=3<uz?<57>52z?7ea<fl27?mn4<849~w0102909w0:n9;cg?82f039396s|56494?4|5=k<6lj4=5c5>6>23ty>;84?:3y>0d3=im168l:53978yv30<3:1>v3;a28b`>;3i;08485rs450>5<5s4>j=7ok;<6b4?5?=2wx9:<50;0x91?a2hn0197j:2:6?xu2?80;6?u248f9ea=:<0i1?5;4}r744?6=:r7?5o4nd:?7=d<40<1v88i:18182>13ko70:68;1;1>{t=?o1<7<t=5;4>db<5=3=6>6:;|q62f<72;q684=5ae9>0<4=;1?0q~;9b;296~;3180jh63;9180<0=z{<<j6=4={<6;b?gc34>3i7=75:p13?=838p196k:`f891>d2:2>7p}:6983>7}:<1h1mi5249c97=3<uz?=;7>52z?7<<<fl27?454<849~w0012909w0:77;cg?82?>39396s|57794?4|5=2>6lj4=5:7>6>23ty>9n4?:3y>025=im168:<53978yv3293:1>v3;5e8b`>;3=j08485rs4a6>5<5s4??97ok;<770?5?=2wx9oo50;0x904a2hn018<j:2:6?xu2io0;6?u250;9ea=:=821?5;4}r7b0?6=:r7><>4nd:?647<40<1v876:18182bl3ko70:jc;1;1>{t=1o1<7<t=5f4>db<5=n=6>6:;|q6<6<72;q68n?5ae9>0f6=;1?0q~;88;296~;3ik0jh63;a`80<0=z{<<o6=4={<6:1?gc34>287=75:p110=838p19:8:`f891212:2>7p}m0683>7}:i1<1=io4=`25>6>23tyi>h4?:3y>e=0=:?301l<k:2:6?xue;00;6?u2a9496=g<5h936>6:;|qa01<72;q6m5852`289d242:2>7p}m4g83>7}:i1<1=5?4=`6f>6>23tyi9l4?:3y>e=0=90=01l;6:2:6?xue><0;6?u2a9495g><5h<?6>6:;|qa35<72;q6m5851bg89d0a2:2>7p}m7c83>7}:i1<1=k>4=`5b>6>23tyi4;4?:3y>e=0=:9<01l6::2:6?xue9;0;6?u2a949671<5h;:6>6:;|qa5a<72;q6m58522f89d7d2:2>7p}m2783>7}:i1<1>;>4=`06>6>23tyi>:4?:3y>e=0=:?801l<9:2:6?xue:10;6?u2a949633<5h8<6>6:;|qa6<<72;q6m58527589d4?2:2>7p}m2`83>7}:i1<1>;l4=`0:>6>23tyi>o4?:3y>e=0=:?n01l<n:2:6?xue:j0;6?u2a949626<5h8i6>6:;|qa6a<72;q6m58526089d4d2:2>7p}m2g83>7}:i1<1>:84=`0f>6>23tyi?=4?:3y>e=0=:>201l<i:2:6?xue;80;6?u2a94962d<5h9;6>6:;|qa77<72;q6m58526f89d562:2>7p}m3283>7}:i1<1>5?4=`11>6>23tyi?94?:3y>e=0=:1901l=<:2:6?xue;<0;6?u2a9496=0<5h9?6>6:;|qa73<72;q6m58529:89d522:2>7p}m3683>7}:i1<1>5m4=`15>6>23tyi?54?:3y>e=0=:1o01l=8:2:6?xue;h0;6?u2a9496<7<5h926>6:;|qa7g<72;q6m58528189d5f2:2>7p}m3b83>7}:i1<1>494=`1a>6>23tyi?i4?:3y>e=0=:0301l=l:2:6?xue;l0;6?u2a9496<e<5h9o6>6:;|qa7c<72;q6m58528g89d5b2:2>7p}m4183>7}:i1<1>l<4=`1e>6>23tyi8<4?:3y>e=0=:h>01l:?:2:6?xue<;0;6?u2a9496d1<5h>:6>6:;|qa06<72;q6m5852`;89d252:2>7p}m4483>7}:i1<1=;j4=`67>6>23tyi8;4?:3y>e=0=9?l01l:::2:6?xue<>0;6?u2a949524<5h>=6>6:;|qa0=<72;q6m58516689d202:2>7p}m4883>7}:i1<1=:64=`6;>6>23tyi8l4?:3y>e=0=9>k01l:6:2:6?xue<k0;6?u2a94952b<5h>j6>6:;|qa0f<72;q6m58516d89d2e2:2>7p}m4e83>7}:i1<1=5=4=`6`>6>23tyi8h4?:3y>e=0=91?01l:k:2:6?xue=90;6?u2a9495=><5h>m6>6:;|qa14<72;q6m58519c89d372:2>7p}m5383>7}:i1<1=5k4=`72>6>23tyi9>4?:3y>e=0=90:01l;=:2:6?xue==0;6?u2a9495<5<5h?86>6:;|qa10<72;q6m58518789d332:2>7p}m5783>7}:i1<1=474=`76>6>23tyi9:4?:3y>e=0=90h01l;9:2:6?xue=10;6?u2a9495<c<5h?<6>6:;|qa1<<72;q6m5851`289d3?2:2>7p}m5c83>7}:i1<1=l:4=`7b>6>23tyi9n4?:3y>e=0=9h<01l;m:2:6?xue=m0;6?u2a9495d?<5h?h6>6:;|qa1`<72;q6m5851``89d3c2:2>7p}m5g83>7}:i1<1=lh4=`7f>6>23tyi:=4?:3y>e=0=9k;01l;i:2:6?xue>80;6?u2a9495g2<5h<;6>6:;|qa27<72;q6m5851c489d062:2>7p}m6283>7}:i1<1=oo4=`41>6>23tyi:94?:3y>e=0=9ki01l8<:2:6?xue>?0;6?u2a9495g`<5h<>6>6:;|qa22<72;q6m5851b389d012:2>7p}m6983>7}:i1<1=n;4=`44>6>23tyi:44?:3y>e=0=9j=01l87:2:6?xue>h0;6?u2a9495fg<5h<26>6:;|qa2g<72;q6m5851ba89d0f2:2>7p}m6b83>7}:i1<1=i>4=`4a>6>23tyi:i4?:3y>e=0=9m801l8l:2:6?xue>l0;6?u2a9495a3<5h<o6>6:;|qa2c<72;q6m5851e589d0b2:2>7p}m7083>7}:i1<1=im4=`53>6>23tyi;?4?:3y>e=0=9mo01l9>:2:6?xue?:0;6?u2a9495`7<5h=96>6:;|qa31<72;q6m5851d189d142:2>7p}m7483>7}:i1<1=h94=`57>6>23tyi;;4?:3y>e=0=9l301l9::2:6?xue?>0;6?u2a9495`e<5h==6>6:;|qa3=<72;q6m5851dg89d102:2>7p}m7883>7}:i1<1=k<4=`5;>6>23tyi;l4?:3y>e=0=9o>01l96:2:6?xue?j0;6?u2a9495c1<5h=i6>6:;|qa3a<72;q6m5851g;89d1d2:2>7p}m7d83>7}:i1<1=kj4=`5g>6>23tyi;k4?:3y>e=0=9ol01l9j:2:6?xue090;6?u2a949654<5h=m6>6:;|qa<4<72;q6m58521689d>72:2>7p}m8383>7}:i1<1>=64=`:2>6>23tyi4>4?:3y>e=0=:9k01l6=:2:6?xue0=0;6?u2a94965b<5h286>6:;|qa<0<72;q6m58521d89d>32:2>7p}m0983>7}:i1<1><=4=`24>6>23tyi<44?:3y>e=0=:8?01l>7:2:6?xue8h0;6?u2a94964><5h:26>6:;|qa4g<72;q6m58520c89d6f2:2>7p}m0b83>7}:i1<1><k4=`2a>6>23tyi<i4?:3y>e=0=:;:01l>l:2:6?xue8l0;6?u2a949675<5h:o6>6:;|qa4c<72;q6m58523789d6b2:2>7p}m1183>7}:i1<1>?74=`2e>6>23tyi=<4?:3y>e=0=:;h01l??:2:6?xue9:0;6?u2a94967c<5h;96>6:;|qa51<72;q6m58522289d742:2>7p}m1483>7}:i1<1>>:4=`37>6>23tyi=;4?:3y>e=0=::<01l?::2:6?xue9>0;6?u2a94966?<5h;=6>6:;|qa5=<72;q6m58522`89d702:2>7p}m1883>7}:i1<1>>h4=`3;>6>23tyi=l4?:3y>e=0=:=;01l?6:2:6?xue9k0;6?u2a949612<5h;j6>6:;|qa5f<72;q6m58525489d7e2:2>7p}m1d83>7}:i1<1>9l4=`3g>6>23tyi=k4?:3y>e=0=:=n01l?j:2:6?xue:90;6?u2a949606<5h;m6>6:;|qa64<72;q6m58524089d472:2>7p}m2383>7}:i1<1>884=`02>6>23tyi>>4?:3y>e=0=:<201l<=:2:6?xue:=0;6?u2a94960d<5h886>6:;|qa60<72;q6m58524f89d432:2>7p}n8683>6}:i1<1=;l4=`25>db<502=6>6:;|qbe`<72:q6m58525;89d4c2hn014ok:2:6?xufj00;6>u2a94962`<5h936lj4=8`;>6>23tyjo94?:2y>e=0=:0?01l:<:`f89<e42:2>7p}ncg83>6}:i1<1=:84=`6f>db<50in6>6:;|qb`d<72:q6m58519a89d3>2hn014j6:2:6?xufm<0;6>u2a9495db<5h<?6lj4=8g7>6>23tyjj=4?:2y>e=0=9j901l8i:`f89<ca2:2>7p}nfc83>6}:i1<1=h;4=`5b>db<50lj6>6:;|qa43<72:q6m5851g`89d>22hn01l>::2:6?xuf1;0;6>u2a94964e<5h;:6lj4=8;2>6>23tyj5i4?:2y>e=0=::801l?l:`f89<?d2:2>7p}na783>6}:i1<1>8:4=`06>db<50k>6>6:;|qbe2<72:q6m58527389d412hn014o9:2:6?xufi10;6>u2a949632<5h8<6lj4=8c4>6>23tyjm44?:2y>e=0=:?<01l<7:`f89<g?2:2>7p}na`83>6}:i1<1>;o4=`0:>db<50k26>6:;|qbeg<72:q6m58527a89d4f2hn014on:2:6?xufij0;6>u2a94963`<5h8i6lj4=8ca>6>23tyjmi4?:2y>e=0=:>;01l<l:`f89<gd2:2>7p}nag83>6}:i1<1>:;4=`0f>db<50kn6>6:;|qbf5<72:q6m58526589d4a2hn014oi:2:6?xufj80;6>u2a94962g<5h9;6lj4=8`3>6>23tyjn?4?:2y>e=0=:>i01l=>:`f89<d62:2>7p}nb283>6}:i1<1>5>4=`11>db<50h96>6:;|qbf1<72:q6m58529089d542hn014l<:2:6?xufj<0;6>u2a9496=3<5h9?6lj4=8`7>6>23tyjn;4?:2y>e=0=:1=01l=::`f89<d22:2>7p}nb683>6}:i1<1>5l4=`15>db<50h=6>6:;|qbf=<72:q6m58529f89d502hn014l8:2:6?xufjh0;6>u2a9496<6<5h926lj4=8`:>6>23tyjno4?:2y>e=0=:0801l=n:`f89<df2:2>7p}nbb83>6}:i1<1>484=`1a>db<50hi6>6:;|qbfa<72:q6m58528:89d5d2hn014ll:2:6?xufjl0;6>u2a9496<d<5h9o6lj4=8`g>6>23tyjnk4?:2y>e=0=:0n01l=j:`f89<db2:2>7p}nc183>6}:i1<1>l?4=`1e>db<50hm6>6:;|qbg4<72:q6m5852`189d272hn014m?:2:6?xufk;0;6>u2a9496d0<5h>:6lj4=8a2>6>23tyjo>4?:2y>e=0=:h201l:=:`f89<e52:2>7p}nc483>6}:i1<1=;m4=`67>db<50i?6>6:;|qbg3<72:q6m58517g89d222hn014m::2:6?xufk>0;6>u2a949527<5h>=6lj4=8a5>6>23tyjo54?:2y>e=0=9>901l:8:`f89<e02:2>7p}nc883>6}:i1<1=:94=`6;>db<50i36>6:;|qbgd<72:q6m58516;89d2>2hn014m6:2:6?xufkk0;6>u2a94952e<5h>j6lj4=8ab>6>23tyjon4?:2y>e=0=9>o01l:m:`f89<ee2:2>7p}nce83>6}:i1<1=5<4=`6`>db<50ih6>6:;|qbg`<72:q6m58519689d2c2hn014mk:2:6?xufl90;6>u2a9495=1<5h>m6lj4=8ae>6>23tyjh<4?:2y>e=0=91301l;?:`f89<b72:2>7p}nd383>6}:i1<1=5j4=`72>db<50n:6>6:;|qb`6<72:q6m58519d89d352hn014j=:2:6?xufl=0;6>u2a9495<4<5h?86lj4=8f0>6>23tyjh84?:2y>e=0=90>01l;;:`f89<b32:2>7p}nd783>6}:i1<1=464=`76>db<50n>6>6:;|qb`2<72:q6m58518c89d312hn014j9:2:6?xufl10;6>u2a9495<b<5h?<6lj4=8f4>6>23tyjh44?:2y>e=0=90l01l;7:`f89<b?2:2>7p}ndc83>6}:i1<1=l=4=`7b>db<50nj6>6:;|qb`f<72:q6m5851`789d3e2hn014jm:2:6?xuflm0;6>u2a9495d><5h?h6lj4=8f`>6>23tyjhh4?:2y>e=0=9hk01l;k:`f89<bc2:2>7p}ndg83>6}:i1<1=lk4=`7f>db<50nn6>6:;|qba5<72:q6m5851c289d3a2hn014ji:2:6?xufm80;6>u2a9495g5<5h<;6lj4=8g3>6>23tyji?4?:2y>e=0=9k?01l8>:`f89<c62:2>7p}ne283>6}:i1<1=o74=`41>db<50o96>6:;|qba1<72:q6m5851c`89d042hn014k<:2:6?xufm?0;6>u2a9495gc<5h<>6lj4=8g6>6>23tyji:4?:2y>e=0=9j:01l89:`f89<c12:2>7p}ne983>6}:i1<1=n:4=`44>db<50o<6>6:;|qba<<72:q6m5851b489d0?2hn014k7:2:6?xufmh0;6>u2a9495f?<5h<26lj4=8g:>6>23tyjio4?:2y>e=0=9jh01l8n:`f89<cf2:2>7p}neb83>6}:i1<1=nh4=`4a>db<50oi6>6:;|qbaa<72:q6m5851e389d0d2hn014kl:2:6?xufml0;6>u2a9495a2<5h<o6lj4=8gg>6>23tyjik4?:2y>e=0=9m<01l8j:`f89<cb2:2>7p}nf083>6}:i1<1=il4=`53>db<50l;6>6:;|qbb7<72:q6m5851ef89d162hn014h>:2:6?xufn:0;6>u2a9495`6<5h=96lj4=8d1>6>23tyjj94?:2y>e=0=9l801l9<:`f89<`42:2>7p}nf483>6}:i1<1=h84=`57>db<50l?6>6:;|qbb3<72:q6m5851d:89d122hn014h::2:6?xufn>0;6>u2a9495`d<5h==6lj4=8d5>6>23tyjj54?:2y>e=0=9ln01l98:`f89<`02:2>7p}nf883>6}:i1<1=k?4=`5;>db<50l36>6:;|qbbd<72:q6m5851g189d1>2hn014h6:2:6?xufnj0;6>u2a9495c0<5h=i6lj4=8da>6>23tyjji4?:2y>e=0=9o201l9l:`f89<`d2:2>7p}nfd83>6}:i1<1=km4=`5g>db<50lo6>6:;|qbbc<72:q6m5851gg89d1b2hn014hj:2:6?xue890;6>u2a949657<5h=m6lj4=8de>6>23tyi<<4?:2y>e=0=:9901l6?:`f89d672:2>7p}m0383>6}:i1<1>=94=`:2>db<5h::6>6:;|qa46<72:q6m58521;89d>52hn01l>=:2:6?xue8=0;6>u2a94965e<5h286lj4=`20>6>23tyi<84?:2y>e=0=:9o01l6;:`f89d632:2>7p}n8983>6}:i1<1><<4=`24>db<502<6>6:;|qb<<<72:q6m58520689d6?2hn01467:2:6?xuf0h0;6>u2a949641<5h:26lj4=8::>6>23tyj4o4?:2y>e=0=:8301l>n:`f89<>f2:2>7p}n8b83>6}:i1<1><j4=`2a>db<502i6>6:;|qb<a<72:q6m58520d89d6d2hn0146l:2:6?xuf0l0;6>u2a949674<5h:o6lj4=8:g>6>23tyj4k4?:2y>e=0=:;>01l>j:`f89<>b2:2>7p}n9183>6}:i1<1>?64=`2e>db<502m6>6:;|qb=4<72:q6m58523c89d772hn0147?:2:6?xuf1:0;6>u2a94967b<5h;96lj4=8;1>6>23tyj594?:2y>e=0=:;l01l?<:`f89<?42:2>7p}n9483>6}:i1<1>>=4=`37>db<503?6>6:;|qb=3<72:q6m58522789d722hn0147::2:6?xuf1>0;6>u2a94966><5h;=6lj4=8;5>6>23tyj554?:2y>e=0=::k01l?8:`f89<?02:2>7p}n9883>6}:i1<1>>k4=`3;>db<50336>6:;|qb=d<72:q6m58525289d7>2hn01476:2:6?xuf1k0;6>u2a949615<5h;j6lj4=8;b>6>23tyj5n4?:2y>e=0=:=?01l?m:`f89<?e2:2>7p}n9d83>6}:i1<1>9o4=`3g>db<503o6>6:;|qb=c<72:q6m58525a89d7b2hn0147j:2:6?xufi90;6>u2a94961`<5h;m6lj4=8;e>6>23tyjm<4?:2y>e=0=:<;01l<?:`f89<g72:2>7p}na383>6}:i1<1>8;4=`02>db<50k:6>6:;|qbe6<72:q6m58524589d452hn014o=:2:6?xufi=0;6>u2a94960g<5h886lj4=8c0>6>23tyjm84?:2y>e=0=:<i01l<;:`f89<g32:2>7p}7d883>7}:0m31?:m4=9de>7d43ty3hl4?:3y><ag=;>i015hi:3`7?xu>990;6>u291g97=3<50:m6lj4=82g>6>?3ty2=<4?:3y>=5`=;1?014>k:`f8yv>b;3:1>v37e380<0=:0mo1mi5rs9g6>5<4s42oh7ok;<:ga?5?=273hk4nd:p<`0=838p15jk:2:;?8>cn39396s|8d594?4|51o:6>6:;<:f4?gc3ty3i54?:3y><`6=;1?015jl:3`2?xu?m=0;68u28d09<1=:0l;149528ea972e<51nn65:4=9fe>=2<uz3>i7>52z?;e`<4?j165=:52c48yv?183:1>v37b1803f=:0oi1>o;4}r;55?6=:r73n<4<7b9>=52=:k90q~792;296~;?j;08;n5291196g2<uz3=?7>52z?;f6<4?j165=;52c68yv?1<3:1>v37b5803f=:0oi1>o84}r;51?6=:r73n84<7b9>=55=:k<0q~796;296~;?j?08;n5291196g3<uz3=;7>52z?;f2<4?j165=:52c78yv?103:1>v37b9803f=:0oi1>o:4}r;6b?6=:r73mk4<7b9>=52=:k>0q~79a;29f~;>9=08;n5295g97=><50>i6>67;<;73?5?02728>4<899>=6`=;12014=m:2:;?8?4?39346363280<==:1;l1?564=80a>6>?3ty3m:4?:5y><f5=;>i015hk:3`1?8>c?3ko706k6;cg?xu?ik0;6>u290492f=:18?1:n528e`972e<uz2o=7>52z?:1g<fl272<<4<7b9~w<0>2909w07>3;14g>;>9=09n=5rs9c3>5<5s43;h7=75:?:57<?<2wx5:?50;4x9<242:2>707;4;0a5>;?nj09n?5291196g5<50:>6?l=;<:e3?4e<2wx5:<50;5x9<202:2>707;8;0a5>;?nj09n>5291096g4<50:?6?l=;<;31?4e>273j:4=b09~w<14290=w07;b;1;1>;><j09n<528g596g3<50:<6?l=;<;3<?4e9272<44=b39~w<13290=w07;e;1;1>;><o09n<528g596g0<50:<6?l<;<;3<?4e:272<44=b29~w<0b290:?v37ag81f1=:0k21>o:4=9`4>7d3342i:7<m4:?;f0<5j=164o:52c689=d42;h?706m2;0a0>;?j809n9528c296g2<51kn6?l;;<;03?5?=272?54=b09><c>=:k9015h6:3`2?8>ai38i=637fc81f6=:0on1>o=4=9de>7d23ty2:k4?:9y>=6d=;1?014=l:3`2?8>a938i=6360281f7=:19?1>o?4=9d4>7d5342m57<m6:?;bc<5j?1v49?:18;8?4n39396364181f4=:0o;1>o<4=821>7d6343;87<m1:?:40<5j<164k952c189<672;h:7p}66c83>45|51n26?l=;<:ge?4e:273mk4=b09><g>=:k;015l8:3`2?8>e>38i=637b481f4=:0k>1>o?4=9`0>7d6342i>7<m1:?;f4<5j8164o>52c389=gb2;h:707=b;1;1>;>:j09n<528g:96g2<51l26?l:;<:ee?4e:273ji4=b09~w<0d290:?v37d881f4=:0mk1>o?4=9ce>7d5342i47<m2:?;f2<5j;164o852c089=d22;h9706m4;0a6>;?j:09n?528c096g4<51h:6?l=;<:a4?4e:273mh4=b39>=7`=;1?014=?:3`2?8>a038i>637f881f6=:0ok1>o=4=823>7d43ty2:i4?:01x9=ga2;h8706m8;0a7>;?j>09n>528c496g5<51h>6?l<;<:a0?4e;273n>4=b29><g4=:k9015l>:3`0?8>e838i?637ad81f6=:1:91?5;4=817>7d6342m47<m1:?;b<<5j;164ko52c689=`e2;h:706id;0a0>;?no09n?5rs9c6>5<5s42h?7<m3:?;`2<40<1v5o9:1818>c03939637c281f4=z{1k?6=4={<:`7?4e:273h;4<849~w=eb290iw06l2;4`?8>d93<h706l0;4`?8>en3<h706me;4`?8>el3<h706mc;4`?8>ej3<h706ma;4`?8>e13<h707?c;14g>{t0h;1<7<t=9da>7d2343:>7=75:p<de=838p15h6:3`7?8>bk39396s|8`f94?5|51lj6?l:;<:fa?5?=273ik4=b09~w=b52908w06ib;0a0>;>=j08485294f96g7<uz2j>7>53z?;bd<5j?164i=539789=b32;h:7p}7cg83>7}:18?1?5;4=9dg>7d23ty3h=4?:3y>=40=;1?015hm:3`1?xu?k=0;6?u28c;97=3<51nj6?l9;|q;g0<72;q64oo539789=bf2;h>7p}7c783>7}:0kh1?5;4=9fb>7d43ty3o:4?:3y><ge=;1?015jn:3`7?xu?k10;6?u28cf97=3<51n26?l9;|q;g<<72;q64ok539789=b>2;h>7p}7c`83>7}:0kl1?5;4=9f:>7d43ty3oo4?:3y><f6=;1?015j6:3`7?xu?kj0;6?u28b397=3<51l36?l:;|q;ga<72;q64n<539789=`?2;h=7p}7a283>7}:0m?1?5;4=82`>7d43ty3ml4?:5y><`g=;1?014>l:3`2?8>cj38i=637ec81f4=z{1k26=4:{<:f=?5?=273il4nd:?:4f<5j;164il52c089=ce2;h97p}7a983>1}:0l31mi528ef97=3<51o:6;m4=9g2>db<uz39<7>52z?:6g<fl272>i4<7b9~w<702908w07=e;4f?8?493<n707=a;156>{t1;;1<7<t=80e>db<509:6>9l;|q:5=<72:q65><56d9>=63=>l165?k53708yv?5:3:1>v36328b`>;>;<08;n5rs83:>5<4s438:78j;<;0=?0b3438>7=92:p=75=838p14=8:`f89<5>2:=h7p}61`83>6}:1:k1:h5292f92`=:1:<1?;<4}r;10?6=:r72?o4nd:?:7a<4?j1v4?m:1808?4m3<n707;1;4f?8?4i39=>6s|93794?4|509m6lj4=862>61d3ty2=n4?:2y>=14=>l1659;56d9>=6c=;?80q~7=6;296~;><:0jh63644803f=z{0;o6=4<{<;72?0b343?578j;<;76?51:2wx5?950;0x9<202hn014:6:25`?xu>9l0;6>u295c92`=:1=n1:h529549734<uz3947>52z?:0g<fl2728i4<7b9~w<7a2909w07:0;4f?8?3i39=>6s|93;94?4|50>n6lj4=873>61d3ty29<4?:2y>=7e=;>i014<n:2;1?8?5l39==6s|94094?5|509;6>9l;<;1a?5>:272?<4<609~w<342908w07<4;14g>;>;;085?529279737<uz3>87>53z?:7=<4?j165>8538089<5>2:<:7p}65483>6}:1:i1?:m4=81b>6?53438h7=91:p=00=839p14:?:25`?8?4m392>636408024=z{0?<6=4<{<;70?50k2728?4<939>=13=;?;0q~7:8;297~;><108;n5295497<4<50>26>8>;|q:1<<72:q659m536a89<2f2:39707;d;155>{t1<k1<7<t=86e>61d343><7=91:p<<`=838p158k:`f89=?b2:=h7p}77983>7}:00i1>o:4=9;g>61d3ty3;:4?:8y><3b=;080158j:2;1?8>1n392>6377180=7=:0>;1?4<4=951>6?5342<?7=62:?;31<41;1644m536a8yv>0=3:1?v379e81f4=:00:1?5;4=9;2>db<uz2<:7>52z?;=a<5j;1644l53978yv>>=3:19v37928;0>;?1;0386378b803f=:01l1495289g9<1=z{13j6=4={<::5?5?=2734n4=b09~w=?>2909w0662;1;1>;?190jh6s|88:94?5|512o6>6:;<::6?0d3422>7ok;|q;=2<72;q645j539:89=>a2:2>7p}79783>6}:01n1mi5289d9ea=:01o1?5;4}r::0?6=:r735>4<849><=c=im1v56;:1868>?:32?70671;:7?8>0139<o6377b8;0>;??k0386s|89`94?4|512;6>6:;<:4=?4e92wx45o50;0x9=1b2:2>7068f;cg?xu?000;6?u286f97=3<51=n6lj4}r:;<?6=:r734<4<849><2b=im1v568:1808>0i39396378085g>;?080jh6s|89494?4|51=j6>67;<:4g?5?=2wx45;50;1x9=1f2hn0159l:`f89=1e2:2>7p}78283>7}:0181?5;4=95a>db<uz=9?7>52z?45`<5j816;?>53978yv15:3:1>v381g8b`>;0:9084:5rs607>5<5s4=:i7<m2:?45c<40<1v:<>:181816l3ko709>e;14g>{t?<?1<7<t=672>7d634=>?7=75:p302=838p1:;=:`f892342:2<7p}85783>7}:?<;1>o<4=671>6>23ty<>44?:3y>373=:k;01:<8:2:6?xu0:10;6?u27349ea=:?;=1?594}r51e?6=:r7<>84=b39>370=;1?0q~9;b;296~;0;l09n<5275697=3<uz=?47>52z?406<fl27<894<869~w22d2909w09<e;0a6>;0<:08485rs66:>5<5s4=?>7ok;<577?5??2wx;9j50;0x925a2;h:709;2;1;1>{t?=k1<7<t=662>db<5>>96>68;|q40`<72;q6;>h52c0892262:2>7p}84483>7}:?=:1>o?4=61f>61d3ty<8;4?:3y>316=:k801:=i:25`?xu0<>0;6?u272f9ea=:?=:1?:m4}r50=?6=:r7<>n4=b09>364=;1?0q~9<6;296~;0;80jh6383380<2=z{>9j6=4={<51g?4e:27<?<4<849~w2502909w09<0;cg?8149393;6s|72`94?4|5>8o6?l>;<504?5?=2wx;>650;0x924a2hn01:=?:2:4?xu0;j0;6?u273f96g4<5>8m6>6:;|q476<72;q6;?k52c38924d2:=h7p}83583>7}:?;o1>o<4=60g>61d3ty<?84?:3y>37d=im16;?k536a8yv12i3:1ov381c8b`>;0<o0848527bd92f=:?ji1:n527b:92f=:?j>1:n527b292f=:?ki1:n527c:92f=:?k>1:n527c292f=:?hi1:n5rs943>5<5s4=?j7=76:?462<fl2wx48:50;`x92302:2>706>3;4`?8>683<h706?c;4`?8>703<h706?4;4`?8>783<h709ic;4`?81a03<h709i4;4`?81a83<h7p}75g83>7}:?=l1mi5274597=0<uz2=:7>52z?;15<fl2738k4<7b9~w=002909w06:0;1;1>;?=80jh6s|87794?4|5>;i6>6:;<52g?gc3ty39;4?:3y><04=>j16;8653978yv>213:1>v375285g>;0=008485rs947>5<5s4=>47ok;<56=?5??2wx;8m50;0x9=2b2?i01:;?:2:6?xu?>:0;6?u274;9ea=:?<:1?594}r:56?6=:r7<=k4<869>306=im1v:?n:1878>2:39346375280<==:0=o1?564=606>61d3ty3:<4?:3y>370=;1=01:<?:`f8yv12m3:1nv3850803f=:?jl1?564=6a`>6>?34=h47=78:?4g1<40116;n>539:892dd2:23709m8;1;<>;0j=0845527c297=><5>kh6>67;|q;1`<72;q6;895ae9>304=;1=0q~6:d;296~;0:o084:527419ea=z{1?h6=4={<506?gc34=?=7=77:p30b=83ip15:j:2:6?815n39h709<0;1`?814939h709<2;1`?813939h709;2;1`?813;39h709;4;1`?815=392>6385080=7=:?<:1?n5rs97b>5<ds42>?7=75:?46a<41;16;?m53808925a2:39709<e;1:6>;0:?08o6382680g>;0=;08o6385280g>;09o08o6382180g>;0=008o6s|84594?3|51?96>6:;<51a?5>:27<8=4<939>34c=;0801:;7:2a8yv>2j3:1>v38458b`>;?:=08n85rs97;>5<5s42>?7ok;<:10?4fl2wx48;50;0x9=352hn015<<:3cg?xu0=k0;6?u285g9ea=:0;81>lj4}r5gf?6=:r7<h=4<7b9>3a7=;?;0q~9ka;297~;0km08;n527b`97<4<5>in6>8>;|q4`<<72:q6;n7536a892e02:39709la;155>{t?m21<7=t=6a6>61d34=h?7=62:?4g3<4>81v:j8:18081d939<o638bg80=7=:?j81?;?4}r5g2?6=;r7<ni4<7b9>3gd=;0801:lj:242?xu0l<0;6>u27c;972e<5>h<6>7=;<5ae?5192wx;i:50;1x92d22:=h709m3;1:6>;0j?08:<5rs6f0>5<4s4=i=7=8c:?4ec<41;16;o<53738yv1c:3:1?v38ae803f=:?hh1?4<4=6cf>6063ty<ml4?:3y>3f`=im16;i?536a8yv1f83:1>v38d085a>;0kk08:?5rs6c:>5<5s4=ho7ok;<5`a?50k2wx;4h50;1x92ee2?o01:mj:7g892e02:<97p}8a983>7}:?j21mi527bc972e<uz=2i7>53z?4g2<1m27<ol49e:?4g6<4>;1v:o8:18181d<3ko709l6;14g>{t?0n1<7=t=6a0>3c<5>i=6;k4=6`e>6053ty<m;4?:3y>3f6=im16;n<536a8yv1>k3:1?v38bg85a>;0k;0=i638bc8027=z{>k>6=4={<5ag?gc34=ii7=8c:p3<d=839p1:lm:7g892db2?o01:l8:241?xu0i=0;6?u27c:9ea=:?kk1?:m4}r5:e?6=;r7<n:49e:?4fd<1m27<n>4<639~w2g42909w09m4;cg?81e>39<o6s|78;94?5|5>h86;k4=6`5>3c<5>km6>8=;|q4e7<72;q6;o>5ae9>3g4=;>i0q~968;297~;0io0=i638b385a>;0ik08:?5rs6c2>5<5s4=jo7ok;<5ba?50k2wx4<h50;0x9=732:=h706>5;155>{t08o1<7=t=932>61d342;j7=62:?;57<4>81v5?k:1808>7l39<o6370c80=7=:09o1?;?4}r:2g?6=;r73<44<7b9><51=;08015>n:242?xu?9k0;6>u2817972e<51:86>7=;<:32?5192wx4<o50;1x9=662:=h709if;1:6>;?8;08:<5rs93:>5<4s4=mh7=8c:?4bg<41;16;kk53738yv>603:1?v38f8803f=:?o=1?4<4=6db>6063ty3=:4?:2y>3c3=;>i01:h<:2;1?81a>39==6s|80494?5|5>l:6>9l;<5fb?5>:27<j?4<609~w2cb2909w06>3;cg?8>6=39<o6s|7d694?4|51;>6;k4=92e>6053ty<ii4?:3y><46=im164<<536a8yv1b;3:1?v370g85a>;?9;0=i6370c8027=z{>oh6=4={<:3g?gc342;i7=8c:p3`4=839p15>m:7g89=6b2?o015>8:241?xu0mk0;6?u281:9ea=:09k1?:m4}r5f5?6=;r73<:49e:?;4d<1m273<>4<639~w2cf2909w06?4;cg?8>7>39<o6s|7d294?5|51:86;k4=925>3c<5>lm6>8=;|q4a<<72;q64=>5ae9><54=;>i0q~9kf;297~;0no0=i6370385a>;0nk08:?5rs6g;>5<5s4=mo7ok;<5ea?50k2wx;ik50;1x92`e2?o01:hj:7g892`02:<97p}8e683>7}:?o21mi527gc972e<uz=oh7>53z?4b2<1m27<jl49e:?4b6<4>;1v:k9:18181a<3ko709i6;14g>{t?mi1<7=t=6d0>3c<5>l=6;k4=6ge>6053ty<i84?:3y>3c6=im16;k<536a8yv1103:1>v38968b`>;01?08;n5rs644>5<5s4=287ok;<5:7?50k2wx;;850;0x92?62hn01:7?:25`?xu0><0;6?u279g9ea=:?1n1?:m4}r550?6=:r7<4o4nd:?4<d<4?j1v:8<:18181?03ko70977;14g>{t??81<7<t=6:6>db<5>2?6>9l;|q424<72;q6;5<5ae9>3=7=;>i0q~990;296~;0?o0jh6387d803f=z{>?m6=4={<54g?gc34=<n7=8c:p<7?=838p15<>:25`?8>5<39i86s|83594?4|518;6>9l;<:17?5e<2wx4?;50;0x921>2:2>706=2;1a0>{t0::1<7<t=64e>6>234=<57ok;|q;6c<72;q6;;k53978920a2hn0q~6=e;296~;0>m08485277g9ea=z{18o6=4={<55g?5?=27<:i4nd:p<7e=838p1:8m:2:6?811k3ko7p}72c83>7}:??k1?5;4=64a>db<uz29m7>53z?43=<40<16;;o5ae9>3<0=:k90q~6<9;297~;0?>08485276:9ea=:?091>o=4}r:0<?6=;r7<;;4<849>321=im16;4>52c18yv>4?3:1?v387480<0=:?><1mi5279f96g5<uz28:7>53z?431<40<16;:;5ae9>3=g=:k90q~6<5;297~;0?:0848527669ea=:?1=1>o=4}r:00?6=;r7<;?4<849>325=im16;5:52c18yv>4;3:1?v387080<0=:?>81mi5279396g5<uz28>7>53z?435<40<16;:?5ae9>32c=:k90q~6<1;297~;0>00848527629ea=:?>h1>o=4}r:1<?6=:r73><4=b09><75=;k?0q~6=6;296~;?:909n<5283097g3<uz2?h7>54z?4=3<5j;16;nh5397892b72;h:706=2;0bg>{t0=i1<7:t=6;0>7d534=ho7=75:?4ga<5j8164?<52`28yv>3j3:18v389181f7=:?j21?5;4=6a:>7d63429>7<65:p<1g=83>p1:6k:3`1?81d<3939638c481f4=:0;81>5o4}r:7=?6=<r7<4l4=b39>3f6=;1?01:m>:3`2?8>5:38<j6s|85:94?2|5>2<6?l=;<5ag?5?=27<ni4=b09><74=:>>0q~6;7;290~;00=09n?527c:97=3<5>h26?l>;<:16?4112wx49850;6x92>62;h9709m4;1;1>;0j<09n<52830961?<uz2?97>54z?43`<5j;16;o>5397892d62;h:706=2;3ge>{t0=>1<7:t=65a>7d534=jo7=75:?4ea<5j8164?<517`8yv>3;3:1>v389680<0=:?0?1mi5rs961>5<5s4=287=75:?4=7<fl2wx49?50;0x92?62:2>7097f;cg?xu?<90;6?u279g97=3<5>2h6lj4}r:0b?6=:r7<4o4<849>3=?=im1v5=j:18181?03939638878b`>{t0:n1<7<t=6:6>6>234=3?7ok;|q;7f<72;q6;5<5397892>72hn0q~6<b;296~;0?o08485276f9ea=z{19j6=4={<54g?5?=27<;l4nd:p230=838p1;89:25`?801:38i96s|65g94?4|5?>n6>9l;<456?4e>2wx:;?50;0x93072;h970892;14g>{t><:1<7<t=773>61d34<=97<m6:p207=838p1;;>:25`?801=38i96s|64094?4|5??96>9l;<451?4e;2wx:8;50;0x93322:=h70895;0a0>{t>??1<7<t=746>61d34<=87<m6:p205=838p1;;<:25`?801?38i:6s|64494?4|5??=6>9l;<453?4e=2wx:8950;0x93302:=h70897;0a7>{t><h1<7<t=77a>61d34<=;7<m4:p231=838p1;88:25`?801<38i96s|64694?4|5???6>9l;<45<?4e>2wx:8650;0x933?2:=h70898;0a1>{t><31<7<t=77:>61d34<=47<m3:p20e=838p1;;l:25`?801038i86s|67:94?4|5?<36>9l;<450?4e;2wx:8o50;0x933f2:=h708;f;0a2>{t><n1<7<t=77g>61d34<?j7<m5:p20c=838p1;;j:25`?803n38i?6s|64d94?4|5??m6>9l;<47b?4e<2wx:9h50;0x932a2:=h70894;0a0>{t>?91<7<t=743>7d634<=87=8c:p246=832p1;:=:25`?804039346393480<==:>:;1?564=70g>6>?34<957=78:?560<40116:??539:8yv0693:1>v390e81f4=:>9o1?:m4}r426?6=:r7=<i4=b39>25`=;>i0q~;k0;297~;2k009n;525gc97=3<5<li6?l>;|q6gc<72:q69n752c7890`12:2>70;i7;0a5>{t=jo1<7=t=4a:>7d334?m>7=75:?6b6<5j81v8mk:18083d138i?63:ed80<0=:=ll1>o?4}r7`g?6=;r7>o44=b39>1`g=;1?018km:3`2?xu2kk0;6>u25b;96g7<5<o=6>6:;<7f3?4e92wx9i?50;1x90ef2;h:70;ie;1;1>;2no09n<5rs4f1>5<4s4?hm7<m2:?544<40<16:=<52c38yv3c;3:15v390b803f=:>9;1?564=4df>6>?34?mm7=78:?6b3<401169k<539:890cb2:2370;ja;1;<>;2m?08455rs4f7>5<5s4?h47<m1:?6g<<4?j1v8j::18183d038i>63:c`803f=z{>;=6=4l{<7`2?50k27=4?49c:?5e3<1k27=m?49c:?5=`<1k27=5l49c:?5=3<1k27=5?49c:?5<`<1k27=4l49c:?5<3<1k27=;k49c:p2f4=838p18m8:25`?803:38i>6s|6c694?74s4<??7=75:?523<5j816:9k52c3893372;h:708:1;0a5>;1=;09n<5264796g7<5??86?l>;<462?4e927=9:4=b09>20d=:k;01;;;:3`2?802038i=6395881f4=:><i1>o?4=77b>7d634<>h7<m1:?51`<5j816:8h52c38yv0e=3:1=>u265697=3<5?<=6?l=;<47a?4e:27=9=4=b39>207=:k801;;=:3`1?802=38i>6395281f7=:><<1>o<4=774>7d534<>n7<m2:?511<5j;16:8652c08933>2;h9708:c;0a6>;1=h09n?5264f96g4<5??n6?l=;<46b?4e:2wx:o850;4x93222:2>70895;0a6>;1>>09n?5267:96g4<5?>m6?l=;<456?4e<2wx:o950;4x93212:2>70895;0a5>;1>>09n<5267:96g7<5?>m6?l>;<456?4e;2wx:o650;1x93202:2>70894;0a6>;1>;09n<5rs7`:>5<4s4<?47=75:?521<5j816:;<52c08yv0ei3:1>v394880<0=:>?:1?4<4}r52<?6=;r7>o;4=b39>25b=;>i01;:=:3`2?xu1jk0;69u26519ea=:>9o1>o?4=702>6>234<9>7<m1:p2ge=83>p1;:;:`f8936b2;h9708=5;1;1>;1:?09n<5rs7`g>5<3s4<?97ok;<43a?4e;27=>44<849>27g=:k;0q~8me;290~;1<?0jh6390d81f1=:>;n1?5;4=70f>7d63ty=nk4?:5y>211=im16:=k52c7893562:2>708<2;0a5>{t>j:1<7:t=76;>db<5?:n6?l9;<401?5?=27=?;4=b09~w3e6290?w08;9;cg?807n38i=6393980<0=:>:31>o?4}r523?6=<r7>o:4=b39>1f0=:k;018m7:25`?807k38i=6s|71`94?0|5?2;6?l>;<44b?5?=27=8l4;9:?50g<3127=8n4;9:?50a<312wx;=j50;4x93>02;h:70876;1;1>;1<h0?m6394c87e>;1<j0?m6394e87e>{t?9o1<78t=7:a>7d634<3m7=75:?50d<3j27=8o4;b:?50f<3j27=8i4;b:p35`=83<p1;6i:3`2?80?m39396394`87g>;1<k0?o6394b87g>;1<m0?o6s|70294?0|5?386?l>;<4:6?5?=27=8l4;d:?50g<3l27=8n4;d:?50a<3l2wx;<?50;4x93?02;h:70866;1;1>;1<h0?i6394c87a>;1<j0?i6394e87a>{t?881<78t=7;a>7d634<2m7=75:?50d<4n27=8o4<f:?50f<4n27=8i4<f:p345=83<p1;7i:3`2?80>m39396394`874>;1<k0?<6394b874>;1<m0?<6s|70694?0|5?k86?l>;<4b6?5?=27=8l4;1:?50g<3927=8n4;1:?50a<392wx;<;50;4x93g02;h:708n6;1;1>;1<h0?>6394c876>;1<j0?>6394e876>{t?9i1<78t=7:0>7d634<3>7=75:?50d<3;27=8o4;3:?50f<3;27=8i4;3:p2f5=838p1;;?:3`5?803i3lo7p}9cd83>7}:><:1>o=4=76b>46?3ty=h44?:3y>206=:k?01;:n:030?xu1m=0;6?u264296g2<5?>j6<?8;|q5ac<72;q6:8?52c48932f28;37p}9f`83>7}:><;1>o=4=76b>47>3ty<<84?:3y>207=:k?01;:n:03b?xu0810;6?u264396g2<5?>j6<?m;|q44<<72;q6:8<52c48932f28>:7p}80`83>7}:><81>o=4=76b>47d3ty=o94?:3y>204=:k?01;:n:03g?xu1k<0;6?u264096g2<5?>j6kk4}r4`2?6=:r7=984=b79>21g=no1v;m8:181802=38i?6394`8245=z{?i36=4={<461?4e=27=8l4>009~w3e>2909w08:5;0a0>;1<h0:<?5rs7ab>5<5s4<>?7<m6:?50d<68:1v;mm:181802;38i?6394`8207=z{?ih6=4={<467?4e=27=8o4id:p2fb=838p1;;<:3`7?803j3;;46s|6bd94?4|5??=6?l9;<47f?76;2wx:i>50;0x93312;h8708;b;323>{t>m;1<7<t=775>7d234<?n7?>8:p2a4=838p1;;9:3`7?803j3;:56s|6e194?4|5??<6?l9;<47f?76i2wx:i:50;0x93302;h8708;b;32f>{t>m?1<7<t=774>7d234<?n7?;1:p2a0=838p1;;8:3`7?803j3;:o6s|6e594?4|5??i6?l9;<47f?76l2wx:i650;0x933e2;h8708;b;df?xu1lh0;6?u264`96g3<5?>i6kh4}r4gf?6=:r7=9o4=b59>21d=99:0q~8kc;296~;1==09n;5265`9557<uz<oh7>52z?511<5j:16:9l51108yv0cm3:1>v395581f0=:>=h1===4}r4gb?6=:r7=994=b59>21d=9=80q~8j0;296~;1=109n;5265a9ba=z{?o:6=4={<46<?4e;27=8n4>099~w3c52909w08:8;0a1>;1<j0:=>5rs7g0>5<5s4<>47<m4:?50f<69>1v;k::181802138i:6394b825==z{?o=6=4={<46=?4e;27=8n4>189~w3c02909w08:9;0a1>;1<j0:=l5rs7g;>5<5s4<>57<m4:?50f<69k1v;k6:181802k38i:6394b8204=z{?oj6=4={<46g?4e;27=8n4>1b9~w3ce2909w08:c;0a1>;1<j0:=i5rs7g`>5<5s4<>o7<m4:?50f<am2wx:hj50;0x933f2;h=708;c;de?xu1ml0;6?u264c96g5<5?>h6<>?;|q5b5<72;q6:8o52c78932d28::7p}9f083>7}:><k1>o:4=76`>4653ty=j?4?:3y>20b=:k<01;:l:020?xu1n:0;6?u264f96g5<5?>h6<:=;|q5b1<72;q6:8j52c78932c2on0q~8i5;296~;1=m09n95265f955><uz<m:7>52z?51`<5j?16:9j51018yv0a?3:1>v395d81f6=:>=n1=<94}r4e<?6=:r7=9h4=b49>21b=9820q~8i9;296~;1=l09n95265f954?<uz<mn7>52z?51c<5j?16:9j510c8yv0ak3:1>v395g81f6=:>=n1=<l4}r4e`?6=:r7=9k4=b49>21b=9=;0q~8ie;296~;1=o09n95265f954e<uz<mj7>52z?523<5j?16:9j510f8yv1783:1>v396781f6=:>=n1jh5rs622>5<5s4<=:7<m5:?50a<an2wx;=<50;0x93012;h?708;d;334>{t?991<7<t=76f>7d134<?h7??1:p352=838p1;:j:3`0?803l3;;>6s|71494?4|5?>n6?l:;<47`?77;2wx;=950;0x932b2;h?708;d;376>{t>>91<7<t=75e>db<5?2:6>9l;|q52d<72:q6:5;56d9>2=>=>l16::k53708yv00=3:1>v39878b`>;10108;n5rs74a>5<4s4<3578j;<4;g?0b34<397=92:p220=838p1;6n:`f893>d2:=h7p}96b83>6}:>1n1:h5268292`=:>131?;<4}r443?6=:r7=4h4nd:?5=5<4?j1v;8k:18080>93<n70864;4f?80?l39=>6s|66:94?4|5?396lj4=7;7>61d3ty=:h4?:2y>2<3=>l16:4656d9>2<7=;?80q~889;296~;11?0jh63999803f=z{?<m6=4<{<4:=?0b34<2o78j;<4:1?51:2wx::o50;0x93?f2hn01;7l:25`?xu1?90;6>u268f92`=:>h:1:h5268;9734<uz<<n7>52z?5=`<fl27=m=4<7b9~w3162908w08n1;4f?80f<3<n7086d;156>{t>>i1<7<t=7c1>db<5?k?6>9l;|q537<72:q6:l;56d9>2d>=>l16:l?53708yv00l3:1>v39a78b`>;1i108;n5rs74:>5<5s4<3878j;<4b1?51:2wx:::50;0x93>52hn01;6;:25`?xu1i00;6>u2692972e<5?=n6>7=;<4;5?5192wx:ll50;1x93>02:=h70875;1:6>;10108:<5rs7c`>5<4s4<3n7=8c:?5<<<41;16:5m53738yv0fl3:1?v398g803f=:>1n1?4<4=7;3>6063ty=mh4?:2y>2<5=;>i01;7>:2;1?80><39==6s|6`d94?5|5?3<6>9l;<4:1?5>:27=554<609~w3d72908w086b;14g>;110085?5268a9737<uz<i=7>53z?5=c<4?j16:4j5380893g72:<:7p}9b383>6}:>h91?:m4=7c2>6?534<j87=91:p2g5=839p1;o8:25`?80f=392>639a98024=z{?kj6=4={<4;7?50k27=494<609~w0bc2909w0;j6;cg?83b039<o6s|5e494?5|5<o26;k4=4g`>3c<5<o>6>8=;|q6``<72;q69ho5ae9>1`e=;>i0q~;k7;297~;2mm0=i63:f185a>;2m008:?5rs4fe>5<5s4?ni7ok;<7e4?50k2wx9i650;1x90`62?o018h;:7g890cc2:<97p}:e183>7}:=o81mi525g6972e<uz?o57>53z?6b0<1m27>j549e:?6b4<4>;1v8k>:18183a>3ko70;i8;14g>{t=mk1<7=t=4d:>3c<5<lh6;k4=4d6>6053ty>i?4?:3y>1cg=im169km536a8yv3cj3:1?v3:fe85a>;1890=i63:f88027=z{<o86=4={<7ea?gc34<;<7=8c:p1ae=838p1;><:7g890`c2:<97p}:e583>7}:>9;1mi52611972e<uz<;87>53z?6a2<4?j169h;5380890c?2:<:7p}90483>6}:=lh1?:m4=4g:>6?534?no7=91:p250=839p18ki:25`?83bl392>63:f18024=z{?:<6=4<{<7e7?50k27>j<4<939>1c2=;?;0q~8?8;297~;2n>08;n525g797<4<5<l36>8>;|q54<<72:q69kl536a890`>2:3970;ic;155>{t>9k1<7=t=4de>61d34?mh7=62:?545<4>81v;>m:181807:39<o639028024=z{?;26=4={<415?gc34<9?7=8c:p245=839p1;<;:7g893402?o01;<?:241?xu19h0;6?u26379ea=:>;=1?:m4}r420?6=;r7=>549e:?56g<1m27=>94<639~w37e2909w08=9;cg?805j39<o6s|60794?5|5?8h6;k4=70e>3c<5?836>8=;|q55f<72;q6:?j5ae9>27`=;>i0q~8>6;297~;1;90=i6393285a>;1:j08:?5rs73g>5<5s4<8=7ok;<407?50k2wx:<950;1x93532?o01;=8:7g893572:<97p}91d83>7}:>:?1mi52625972e<uz<:47>52z?57d<1m27=?94<639~w37a2909w08<8;cg?804i39<o6s|62`94?5|5?896>9l;<414?5>:27=>>4<609~w35d2908w08=6;14g>;1:=085?526359737<uz<8h7>53z?56d<4?j16:?653808934e2:<:7p}93d83>6}:>;o1?:m4=70`>6?534<9j7=91:p26`=839p1;==:25`?8048392>639328024=z{?>;6=4<{<402?50k27=?94<939>261=;?;0q~8;1;296~;1;008;n5262c9737<uz2m<7>52z?;b4<4?j164km52c38yv>a93:1?v37fb803f=:19=1>o?4=82;>7d33ty3jn4?:3y>=54=;>i014><:3`2?xu>8;0;6?u2911972e<50:36?l<;|q:46<72;q65=:536a89<622;h87p}60583>7}:19?1?:m4=822>7d53ty2<;4?:3y>=5g=;>i015h9:3`2?xu>8h0;6?u291`972e<51l=6?l=;|q:4g<72;q64k<536a89=`12;h87p}7f383>7}:0o91?:m4=9d5>7d33ty3j>4?:3y><c2=;>i015h9:3`6?xu?n=0;6?u28g7972e<51l=6?l9;|q;b0<72:q64k8536a89<6?2;h=707?9;0a5>{t0o<1<7<t=9d4>61d343;47<m5:p<c1=838p15h7:25`?8>an38i=6s|8g:94?4|51l26>9l;<;34?4e=2wx4k750;0x9=`f2:=h707?0;0a6>{t0ok1<7<t=9da>61d342mh7<m6:p<cd=838p15hk:25`?8?7838i86s|8gg94?4|50:;6>9l;<;35?4e=2wx4hj50;0`e~;?mj0jh63k64803`=:1>n1?>5296f971=:1>n1?85296:976=:1>21?95296:970=:<=<1??52454976=:<=<1?952486977=:<0>1?>52486971=:<hk1??524`c976=:<hk1?9524b2977=:<j:1?>524b2971=:<m<1??524e4976=:<m<1?9524da977=:<li1?>524da971=:=981??52510976=:=981?95250:977=:=821?>5250:971=:=;o1??5253g976=:=;o1?952556977=:==>1?>52556971=:<<i1??5244a976=:<<i1?952460977=:<>81?>52460971=:<1>1??52496976=:<1>1?952494977=:<1<1?>52494971=:<121??5249:976=:<121?95249c977=:<1k1?>5249c971=:<1i1??5249a976=:<1i1?95249g977=:<1o1?>5249g971=:<0:1??52482976=:<0:1?952480977=:<081?>52480971=:<0<1??52484976=:<0<1?95248:977=:<021?>5248:971=:<0k1??5248c976=:<0k1?95248a977=:<0i1?>5248a971=:<0o1??5248g976=:<0o1?9524`2977=:<h:1?>524`2971=:<h81??524`0976=:<h81?9524`6977=:<h>1?>524`6971=:<h<1??524`4976=:<h<1?9524`:977=:<h21?>524`:971=:<hi1??524`a976=:<hi1?9524`g977=:<ho1?>524`g971=:<k:1??524c2976=:<k:1?9524c0977=:<k81?>524c0971=:<k>1??524c6976=:<k>1?9524c4977=:<k<1?>524c4971=:<k21??524c:976=:<k21?9524cc977=:<kk1?>524cc971=:<ki1??524ca976=:<ki1?9524cg977=:<ko1?>524cg971=:<j81??524b0976=:<j81?9524b6977=:<j>1?>524b6971=:<j<1??524b4976=:<j<1?9524b:977=:<j21?>524b:971=:<jk1??524bc976=:<jk1?9524ba977=:<ji1?>524ba971=:<jo1??524bg976=:<jo1?9524e2977=:<m:1?>524e2971=:<m81??524e0976=:<m81?9524e6977=:<m>1?>524e6971=:<m21??524e:976=:<m21?9524ec977=:<mk1?>524ec971=:<mi1??524ea976=:<mi1?9524eg977=:<mo1?>524eg971=:<l:1??524d2976=:<l:1?9524d0977=:<l81?>524d0971=:<l>1??524d6976=:<l>1?9524d4977=:<l<1?>524d4971=:<l21??524d:976=:<l21?9524dc977=:<lk1?>524dc971=:<lo1??524dg976=:<lo1?9524g2977=:<o:1?>524g2971=:<o81??524g0976=:<o81?9524g6977=:<o>1?>524g6971=:<o<1??524g4976=:<o<1?9524g:977=:<o21?>524g:971=:<ok1??524gc976=:<ok1?9524ga977=:<oi1?>524ga971=:<oo1??524gg976=:<oo1?952512977=:=9:1?>52512971=:=9>1??52516976=:=9>1?952514977=:=9<1?>52514971=:=921??5251:976=:=921?95251c977=:=9k1?>5251c971=:=9i1??5251a976=:=9i1?95251g977=:=9o1?>5251g971=:=8:1??52502976=:=8:1?952500977=:=881?>52500971=:=8>1??52506976=:=8>1?952504977=:=8<1?>52504971=:=8k1??5250c976=:=8k1?95250a977=:=8i1?>5250a971=:=8o1??5250g976=:=8o1?952532977=:=;:1?>52532971=:=;81??52530976=:=;81?952536977=:=;>1?>52536971=:=;<1??52534976=:=;<1?95253:977=:=;21?>5253:971=:=;k1??5253c976=:=;k1?95253a977=:=;i1?>5253a971=:=::1??52522976=:=::1?952520977=:=:81?>52520971=:=:>1??52526976=:=:>1?952524977=:=:<1?>52524971=:=:21??5252:976=:=:21?95252c977=:=:k1?>5252c971=:=:i1??5252a976=:=:i1?95252g977=:=:o1?>5252g971=:==:1??52552976=:==:1?952550977=:==81?>52550971=:<=21??5245:976=:<=21?95245c977=:<=k1?>5245c971=:<=i1??5245a976=:<=i1?95245g977=:<=o1?>5245g971=:<<:1??52442976=:<<:1?952440977=:<<81?>52440971=:<<>1??52446976=:<<>1?952444977=:<<<1?>52444971=:<<21??5244:976=:<<21?95244c977=:<<k1?>5244c971=:<<o1??5244g976=:<<o1?952472977=:<?:1?>52472971=:<?81??52470976=:<?81?952476977=:<?>1?>52476971=:<?<1??52474976=:<?<1?95247:977=:<?21?>5247:971=:<?k1??5247c976=:<?k1?95247a977=:<?i1?>5247a971=:<?o1??5247g976=:<?o1?952462977=:<>:1?>52462971=:<>>1??52466976=:<>>1?952464977=:<><1?>52464971=:<>21??5246:976=:<>21?95246c977=:<>k1?>5246c971=:<>i1??5246a976=:<>i1?95246g977=:<>o1?>5246g971=:<1:1??52492976=:<1:1?952490977=:<181?>52490971=:i1<1>8h4=`:5>73>34k3:7<:3:?b<3<5<l16m58525589d>12;>970o76;00g>;f0?09?:52a949667<5h2=6?<l;<c;2?45>27j4;4=209>e=0=:8h01l69:335?8g?>38:<63n87814g=:i1<1>=;4=`:5>76734k3:7?ia:?b<3<6n<16m5851dd89d>128oj70o76;3f0>;f0?0:hk52a9495a><5h2=6<j<;<c;2?7dl27j4;4>c99>e=0=9j801l69:0`g?8g?>3;i;63n8782f7=:i1<1=lm4=`:5>4g034k3:7?n1:?b<3<61j16m58518489d>1283:70o76;3;f>;f0?0:4;52a9495=6<5h2=6<9m;<c;2?70=27j4;4>719>e=0=:hk01l69:3c6?8g?>382j63n8781=d=:i1<1>4:4=`:5>7>a34k3:7<79:?b<3<50=16m58526g89d>12;=270o76;047>;f0?09:h52a94963><5h2=6?8<;<c;2?43027j4;4=109>e=0=9m301l69:0c1?8g?>38jo63n878131=:0l31:n528dc92f=:0m?1:n528e:9ea=:1<h1:n528d292f=:19o1:n5291d92f=:1=o1:n5295`92f=:1==1:n5295192f=:1:l1:n5292`92f=:1:=1:n5292192f=:1;l1:n5293`92f=:1;k1:h5293f92`=:00n1>o=4=9;3>3e<513:6;m4=95g>3e<51=n6;m4=95e>3e<512;6;m4=65:>64<5>=26>=4=65:>62<5>=26>;4=6ge>3c<5>l96;k4=6ca>3c<5>kn6;k4=75f>3c<5?2:6;k4=4g6>3c<5<o36;k4=703>3c<5?886;k4=831>db<5?>j6o?4=76b>6>b34<?m78:;<47e?72827=8l494:?50d<1?27=8l496:?50d<40o16:9o5f69>21g=n<16:9o5f59>21g=n:16:9o5449>21g=<116:9o5469>21g=<?16:9o53d9>21g==?16:9o55`9>21g==016:9o5599>21g==>16:9o54g9>21g=kh16:9o5c99>21g=k?16:9o5c49>21g=k=16:9o5c29>21g=k;16:9o5c09>21g=k916:9o5bg9>21g=jl16:9o5be9>21g=jk16:9o5b`9>21g=j016:9o5b99>21g=j>16:9o5b79>21g=j<16:9o5b59>21g=j:16:9o5b39>21g=l816:9o5d19>21g=ko16:9o5cd9>21g=km16:9o5cb9>21g=kk16:9o5c69>21g=jj16:9l5b09>21d=;1o01;:m:778932e28?;708;b;47?803j3<<708;b;45?803j393j6394c8e3>;1<k0m96394c8e0>;1<k0m?6394c871>;1<k0?46394c873>;1<k0?:6394c80a>;1<k0>:6394c86e>;1<k0>56394c86<>;1<k0>;6394c87b>;1<k0hm6394c8`<>;1<k0h:6394c8`1>;1<k0h86394c8`7>;1<k0h>6394c8`5>;1<k0h<6394c8ab>;1<k0ii6394c8a`>;1<k0in6394c8ae>;1<k0i56394c8a<>;1<k0i;6394c8a2>;1<k0i96394c8a0>;1<k0i?6394c8a6>;1<k0o=6394c8g4>;1<k0hj6394c8`a>;1<k0hh6394c8`g>;1<k0hn6394c8`3>;1<k0io6394b8a5>;1<j084h5265a920=:>=i1=8>4=76`>32<5?>h6;94=76`>30<5?>h6>6i;<47g?`034<?o7h:;<47g?`334<?o7h<;<47g?2234<?o7:7;<47g?2034<?o7:9;<47g?5b34<?o7;9;<47g?3f34<?o7;6;<47g?3?34<?o7;8;<47g?2a34<?o7mn;<47g?e?34<?o7m9;<47g?e234<?o7m;;<47g?e434<?o7m=;<47g?e634<?o7m?;<47g?da34<?o7lj;<47g?dc34<?o7lm;<47g?df34<?o7l6;<47g?d?34<?o7l8;<47g?d134<?o7l:;<47g?d334<?o7l<;<47g?d534<?o7j>;<47g?b734<?o7mi;<47g?eb34<?o7mk;<47g?ed34<?o7mm;<47g?e034<?o7ll;<47`?d634<?h7=7e:?50a<1=27=8i4>519>21b=>=16:9j5669>21b=>?16:9j539d8932c2o=01;:k:g78932c2o>01;:k:g18932c2=?01;:k:5:8932c2==01;:k:548932c2:o01;:k:448932c2<k01;:k:4;8932c2<201;:k:458932c2=l01;:k:bc8932c2j201;:k:b48932c2j?01;:k:b68932c2j901;:k:b08932c2j;01;:k:b28932c2kl01;:k:cg8932c2kn01;:k:c`8932c2kk01;:k:c;8932c2k201;:k:c58932c2k<01;:k:c78932c2k>01;:k:c18932c2k801;:k:e38932c2m:01;:k:bd8932c2jo01;:k:bf8932c2ji01;:k:b`8932c2j=01;:k:ca8yv>bn3:1>v37eg803f=:0lo1mi5rs87g>5<5s43>h7=8c:?:1f<fl2wx4i:50;0x9=b32:=h706k3;cg?xu4?=0;6?u291296g0<51lm6>9l;|q030<72;q65=9536a89<662;h=7p}<7783>7}:1921?:m4=822>7d43ty8;:4?:3y>=57=:k>014>6:25`?x{i:>in6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o04gc<728qCh>?4H25:?_71038p?4<534d9yM50i2we>:j?:182Mb492B8;45U17:96~5>:39>j7sG36c8yk40l80;6<uGd238L61>3S;=47<t380970`=uA9<m6sa26f1>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug8<h>4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m62b3290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<8d483>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:>n=6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o04`2<728qCh>?4H25:?_71038p?4<534d9yM50i2we>:j7:182Mb492B8;45U17:96~5>:39>j7sG36c8yk40l00;6<uGd238L61>3S;=47<t380970`=uA9<m6sa26fb>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug8<ho4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m62bd290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<8de83>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:>nn6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o04`c<728qCh>?4H25:?_71038p?4<534d9yM50i2we>:k?:182Mb492B8;45U17:96~5>:39>j7sG36c8yk40m80;6<uGd238L61>3S;=47<t380970`=uA9<m6sa26g1>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug8<i>4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m62c3290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<8e483>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:>o=6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o04a2<728qCh>?4H25:?_71038p?4<534d9yM50i2we>:k7:182Mb492B8;45U17:96~5>:39>j7sG36c8yk40m00;6<uGd238L61>3S;=47<t380970`=uA9<m6sa26gb>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug8<io4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m62cd290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<8ee83>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:>on6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o04ac<728qCh>?4H25:?_71038p?4<534d9yM50i2we>:h?:182Mb492B8;45U17:96~5>:39>j7sG36c8yk40n80;6<uGd238L61>3S;=47<t380970`=uA9<m6sa26d1>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug8<j>4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m62`3290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<8f483>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:>l=6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o04b2<728qCh>?4H25:?_71038p?4<534d9yM50i2we>:h7:182Mb492B8;45U17:96~5>:39>j7sG36c8yk40n00;6<uGd238L61>3S;=47<t380970`=uA9<m6sa26db>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug8<jo4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m62`d290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<8fe83>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:>ln6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o04bc<728qCh>?4H25:?_71038p?4<534d9yM50i2we>5>?:182Mb492B8;45U17:96~5>:39>j7sG36c8yk4?880;6<uGd238L61>3S;=47<t380970`=uA9<m6sa2921>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug83<>4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m6=63290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<70483>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:1:=6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o0;42<728qCh>?4H25:?_71038p?4<534d9yM50i2we>5>7:182Mb492B8;45U17:96~5>:39>j7sG36c8yk4?800;6<uGd238L61>3S;=47<t380970`=uA9<m6sa292b>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug83<o4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m6=6d290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<70e83>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:1:n6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o0;4c<728qCh>?4H25:?_71038p?4<534d9yM50i2we>5??:182Mb492B8;45U17:96~5>:39>j7sG36c8yk4?980;6<uGd238L61>3S;=47<t380970`=uA9<m6sa2931>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug83=>4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m6=73290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<71483>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:1;=6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o0;52<728qCh>?4H25:?_71038p?4<534d9yM50i2we>5?7:182Mb492B8;45U17:96~5>:39>j7sG36c8yk4?900;6<uGd238L61>3S;=47<t380970`=uA9<m6sa293b>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug83=o4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m6=7d290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<71e83>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:1;n6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o0;5c<728qCh>?4H25:?_71038p?4<534d9yM50i2we>5<?:182Mb492B8;45U17:96~5>:39>j7sG36c8yk4?:80;6<uGd238L61>3S;=47<t380970`=uA9<m6sa2901>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug83>>4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m6=43290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<72483>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:18=6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o0;62<728qCh>?4H25:?_71038p?4<534d9yM50i2we>5<7:182Mb492B8;45U17:96~5>:39>j7sG36c8yk4?:00;6<uGd238L61>3S;=47<t380970`=uA9<m6sa290b>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug83>o4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m6=4d290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<72e83>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:18n6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o0;6c<728qCh>?4H25:?_71038p?4<534d9yM50i2we>5=?:182Mb492B8;45U17:96~5>:39>j7sG36c8yk4?;80;6<uGd238L61>3S;=47<t380970`=uA9<m6sa2911>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug83?>4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m6=53290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<73483>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:19=6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o0;72<728qCh>?4H25:?_71038p?4<534d9yM50i2we>5=7:182Mb492B8;45U17:96~5>:39>j7sG36c8yk4?;00;6<uGd238L61>3S;=47<t380970`=uA9<m6sa291b>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug83?o4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m6=5d290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<73e83>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:19n6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o0;7c<728qCh>?4H25:?_71038p?4<534d9yM50i2we>5:?:182Mb492B8;45U17:96~5>:39>j7sG36c8yk4?<80;6<uGd238L61>3S;=47<t380970`=uA9<m6sa2961>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug838>4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m6=23290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<74483>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:1>=6=4>{If05>N4?01Q=;652z1:6?52n3wC?:o4}o0;02<728qCh>?4H25:?_71038p?4<534d9yM50i2we>5:7:182Mb492B8;45U17:96~5>:39>j7sG36c8yk4?<00;6<uGd238L61>3S;=47<t380970`=uA9<m6sa296b>5<6sAn8=6F<789Y53>=:r92>7=:f;K72g<ug838o4?:0yK`67<@:=27W?98;0x7<4=;<l1qE=8a:m6=2d290:wEj<1:J03<=]9?21>v=62;16b?{O;>k0qc<74e83>4}Ol:;0D>96;[35<?4|;081?8h5}I14e>{i:1>n6=4>{If05>{i:1>m6=4>{If05>{i:1?;6=4>{If05>{i:1?:6=4>{If05>{i:1?96=4>{If05>{i:1?86=4>{If05>{i:1??6=4>{If05>{i:1?>6=4>{If05>{i:1?=6=4>{If05>{i:1?<6=4>{If05>{i:1?36=4>{If05>{i:1?26=4>{If05>{i:1?j6=4>{If05>{i:1?i6=4>{If05>{i:1?h6=4>{If05>{i:1?o6=4>2zJg74=zf;2>i7>51zJg74=zf;2>j7>51zJg74=zf;2=<7>51zJg74=zf;2==7>51zJg74=zf;2=>7>51zJg74=zf;2=?7>51zJg74=zf;2=87>51zJg74=zf;2=97>51zJg74=zf;2=:7>51zJg74=zf;2=;7>51zJg74=zf;2=47>57zJg74=zf;2=57>51zJg74=zf;2=m7>51zJg74=zf;2=n7>51zJg74=zf;2=o7>51zJg74=zf;2=h7>51zJg74=zf;2=i7>51zJg74=zf;2=j7>53zJg74=zf;2<<7>519yK`67<ug83;<4?:7yK`67<R:hn6<u>4c8~^40?28q8nh4r}o0;37<728qCh>?4}o0;36<728qCh>?4}o0;31<728qCh>?4}o0;30<728qCh>?4}o0;33<728qCh>?4}o0;32<728qCh>?4}o0;3=<728qCh>?4}o0;3<<728qCh>?4}o0;3d<72:qCh>?4}o0;3g<728qCh>?4}o0;3f<728qCh>?4}o0;3a<728qCh>?4}o0;3`<728qCh>?4}o0;3c<728qCh>?4}o0;<5<728qCh>?4}o0;<4<728qCh>?4}o0;<7<728qCh>?4}o0;<6<728qCh>?4}o0;<1<728qCh>?4}o0;<0<728qCh>?4}o0;<3<728qCh>?4}o0;<2<728qCh>?4}o0;<=<728qCh>?4}o0;<<<728qCh>?4}o0;<d<728qCh>?4}o0;<g<728qCh>?4}o0;<f<728qCh>?4}o0;<a<728qCh>?4}o0;<`<728qCh>?4}o0;<c<728qCh>?4}o0;=5<728qCh>?4}o0;=4<728qCh>?4}o0;=7<728qCh>?4}o0;=6<728qCh>?4}o0;=1<728qCh>?4}o0;=0<728qCh>?4}o0;=3<728qCh>?4}o0;=2<728qCh>?4}o0;==<728qCh>?4}o0;=<<728qCh>?4}o0;=d<728qCh>?4}o0;=g<728qCh>?4}o0;=f<728qCh>?4}o0;=a<728qCh>?4}o0;=`<728qCh>?4}o0;=c<728qCh>?4}o0;e5<728qCh>?4}o0;e4<728qCh>?4}o0;e7<728qCh>?4}o0;e6<728qCh>?4}o0;e1<728qCh>?4}o0;e0<728qCh>?4}o0;e3<728qCh>?4}o0;e2<728qCh>?4}o0;e=<728qCh>?4}o0;e<<728qCh>?4}o0;ed<728qCh>?4}o0;eg<728qCh>?4}o0;ef<728qCh>?4}o0;ea<728qCh>?4}o0;e`<728qCh>?4}o0;ec<728qCh>?4}o0;f5<728qCh>?4}o0;f4<728qCh>?4}o0;f7<728qCh>?4}o0;f6<728qCh>?4}o0;f1<728qCh>?4}o0;f0<728qCh>?4}o0;f3<728qCh>?4}o0;f2<728qCh>?4}o0;f=<728qCh>?4}o0;f<<728qCh>?4}o0;fd<728qCh>?4}o0;fg<728qCh>?4}o0;ff<728qCh>?4}o0;fa<728qCh>?4}o0;f`<728qCh>?4}o0;fc<728qCh>?4}o0;g5<728qCh>?4}o0;g4<728qCh>?4}o0;g7<728qCh>?4}o0;g6<728qCh>?4}o0;g1<728qCh>?4}o0;g0<728qCh>?4}o0;g3<728qCh>?4}o0;g2<728qCh>?4}o0;g=<728qCh>?4}o0;g<<728qCh>?4}o0;gd<728qCh>?4}o0;gg<728qCh>?4}o0;gf<728qCh>?4}o0;ga<728qCh>?4}o0;g`<728qCh>?4}o0;gc<728qCh>?4}o0;`5<728qCh>?4}o0;`4<728qCh>?4}o0;`7<728qCh>?4}o0;`6<728qCh>?4}o0;`1<728qCh>?4}o0;`0<728qCh>?4}o0;`3<728qCh>?4}o0;`2<728qCh>?4}o0;`=<728qCh>?4}o0;`<<728qCh>?4}o0;`d<728qCh>?4}o0;`g<728qCh>?4}o0;`f<728qCh>?4}o0;`a<728qCh>?4}o0;``<728qCh>?4}o0;`c<728qCh>?4}o0;a5<728qCh>?4}o0;a4<728qCh>?4}o0;a7<728qCh>?4}o0;a6<728qCh>?4}o0;a1<728qCh>?4}o0;a0<728qCh>?4}o0;a3<728qCh>?4}o0;a2<728qCh>?4}o0;a=<728qCh>?4}o0;a<<728qCh>?4}o0;ad<728qCh>?4}o0;ag<728qCh>?4}o0;af<728qCh>?4}o0;aa<728qCh>?4}o0;a`<728qCh>?4}o0;ac<728qCh>?4}o0;b5<728qCh>?4}o0;b4<728qCh>?4}o0;b7<728qCh>?4}o0;b6<728qCh>?4}o0;b1<728qCh>?4}o0;b0<728qCh>?4}o0;b3<728qCh>?4}o0;b2<728qCh>?4}o0;b=<728qCh>?4}o0;b<<728qCh>?4}o0;bd<728qCh>?4}o0;bg<728qCh>?4}o0;bf<728qCh>?4}o0;ba<728qCh>?4}o0;b`<728qCh>?4}o0;bc<728qCh>?4}o0:45<728qCh>?4}o0:44<728qCh>?4}o0:47<728qCh>?4}o0:46<728qCh>?4}o0:41<728qCh>?4}o0:40<728qCh>?4}o0:43<72:qCh>?4}o0:42<728qCh>?4}o0:4=<72=qCh>?4}o0:4<<728qCh>?4}o0:4d<728qCh>?4}o0:4g<728qCh>?4}o0:4f<728qCh>?4}o0:4a<728qCh>?4}o0:4`<728qCh>?4}o0:4c<728qCh>?4}o0:55<728qCh>?4}o0:54<728qCh>?4}o0:57<728qCh>?4}o0:56<728qCh>?4}o0:51<728qCh>?4}o0:50<728qCh>?4}o0:53<72<qCh>?4}o0:52<72<qCh>?4}o0:5=<72<qCh>?4}o0:5<<72<qCh>?4}o0:5d<72<qCh>?4}o0:5g<72<qCh>?4}o0:5f<72<qCh>?4}o0:5a<72<qCh>?4}o0:5`<72<qCh>?4}o0:5c<72<qCh>?4}o0:65<728qCh>?4}o0:64<728qCh>?4}o0:67<728qCh>?4}o0:66<728qCh>?4}o0:61<728qCh>?4}o0:60<728qCh>?4}o0:63<728qCh>?4}o0:62<728qCh>?4}o0:6=<728qCh>?4}o0:6<<728qCh>?4}o0:6d<728qCh>?4}o0:6g<728qCh>?4}o0:6f<728qCh>?4}o0:6a<728qCh>?4}o0:6`<728qCh>?4}o0:6c<728qCh>?4}o0:75<728qCh>?4}o0:74<728qCh>?4}o0:77<728qCh>?4}o0:76<728qCh>?4}o0:71<728qCh>?4}o0:70<728qCh>?4}o0:73<728qCh>?4}o0:72<728qCh>?4}o0:7=<728qCh>?4}o0:7<<728qCh>?4}o0:7d<728qCh>?4}o0:7g<728qCh>?4}o0:7f<728qCh>?4}o0:7a<728qCh>?4}o0:7`<728qCh>?4}o0:7c<728qCh>?4}o0:05<728qCh>?4}o0:04<728qCh>?4}o0:07<728qCh>?4}o0:06<728qCh>?4}o0:01<728qCh>?4}o0:00<728qCh>?4}o0:03<728qCh>?4}o0:02<728qCh>?4}o0:0=<728qCh>?4}o0:0<<728qCh>?4}o0:0d<728qCh>?4}o0:0g<728qCh>?4}o0:0f<728qCh>?4}o0:0a<728qCh>?4}o0:0`<728qCh>?4}o0:0c<728qCh>?4}o0:15<728qCh>?4}o0:14<728qCh>?4}o0:17<728qCh>?4}o0:16<728qCh>?4}o0:11<728qCh>?4}o0:10<728qCh>?4}o0:13<728qCh>?4}o0:12<728qCh>?4}o0:1=<728qCh>?4}o0:1<<728qCh>?4}o0:1d<728qCh>?4}o0:1g<728qCh>?4}o0:1f<728qCh>?4}o0:1a<728qCh>?4}o0:1`<728qCh>?4}o0:1c<728qCh>?4}o0:25<728qCh>?4}o0:24<728qCh>?4}o0:27<728qCh>?4}o0:26<728qCh>?4}o0:21<728qCh>?4}o0:20<728qCh>?4}o0:23<728qCh>?4}o0:22<728qCh>?4}o0:2=<728qCh>?4}o0:2<<728qCh>?4}o0:2d<728qCh>?4}o0:2g<728qCh>?4}o0:2f<728qCh>?4}o0:2a<728qCh>?4}o0:2`<728qCh>?4}o0:2c<728qCh>?4}o0:35<728qCh>?4}o0:34<728qCh>?4}o0:37<728qCh>?4}o0:36<728qCh>?4}o0:31<728qCh>?4}o0:30<728qCh>?4}o0:33<728qCh>?4}o0:32<728qCh>?4}o0:3=<728qCh>?4}o0:3<<728qCh>?4}o0:3d<728qCh>?4}o0:3g<728qCh>?4}o0:3f<728qCh>?4}o0:3a<728qCh>?4}o0:3`<728qCh>?4}o0:3c<728qCh>?4}o0:<5<728qCh>?4}o0:<4<728qCh>?4}o0:<7<728qCh>?4}o0:<6<728qCh>?4}o0:<1<728qCh>?4}o0:<0<728qCh>?4}o0:<3<728qCh>?4}o0:<2<728qCh>?4}o0:<=<728qCh>?4}o0:<<<728qCh>?4}o0:<d<728qCh>?4}o0:<g<728qCh>?4}o0:<f<728qCh>?4}o0:<a<728qCh>?4}o0:<`<728qCh>?4}o0:<c<728qCh>?4}o0:=5<728qCh>?4}o0:=4<728qCh>?4}o0:=7<728qCh>?4}o0:=6<728qCh>?4}o0:=1<728qCh>?4}o0:=0<728qCh>?4}o0:=3<728qCh>?4}o0:=2<728qCh>?4}o0:==<728qCh>?4}o0:=<<728qCh>?4}o0:=d<728qCh>?4}o0:=g<728qCh>?4}o0:=f<728qCh>?4}o0:=a<728qCh>?4}o0:=`<728qCh>?4}o0:=c<728qCh>?4}o0:e5<728qCh>?4}o0:e4<728qCh>?4}o0:e7<728qCh>?4}o0:e6<728qCh>?4}o0:e1<728qCh>?4}o0:e0<728qCh>?4}o0:e3<728qCh>?4}o0:e2<728qCh>?4}o0:e=<728qCh>?4}o0:e<<728qCh>?4}o0:ed<728qCh>?4}o0:eg<728qCh>?4}o0:ef<728qCh>?4}o0:ea<728qCh>?4}o0:e`<728qCh>?4}o0:ec<728qCh>?4}o0:f5<728qCh>?4}o0:f4<728qCh>?4}o0:f7<728qCh>?4}o0:f6<728qCh>?4}o0:f1<728qCh>?4}o0:f0<728qCh>?4}o0:f3<728qCh>?4}o0:f2<728qCh>?4}o0:f=<728qCh>?4}o0:f<<728qCh>?4}o0:fd<728qCh>?4}o0:fg<728qCh>?4}o0:ff<728qCh>?4}o0:fa<728qCh>?4}o0:f`<728qCh>?4}o0:fc<728qCh>?4}o0:g5<728qCh>?4}o0:g4<728qCh>?4}o0:g7<728qCh>?4}o0:g6<728qCh>?4}o0:g1<728qCh>?4}o0:g0<728qCh>?4}o0:g3<728qCh>?4}o0:g2<728qCh>?4}o0:g=<728qCh>?4}o0:g<<728qCh>?4}o0:gd<728qCh>?4}o0:gg<728qCh>?4}o0:gf<728qCh>?4}o0:ga<728qCh>?4}o0:g`<728qCh>?4}o0:gc<728qCh>?4}o0:`5<728qCh>?4}o0:`4<728qCh>?4}o0:`7<728qCh>?4}o0:`6<728qCh>?4}o0:`1<728qCh>?4}o0:`0<728qCh>?4}o0:`3<728qCh>?4}o0:`2<728qCh>?4}o0:`=<728qCh>?4}o0:`<<728qCh>?4}o0:`d<728qCh>?4}o0:`g<728qCh>?4}o0:`f<728qCh>?4}o0:`a<728qCh>?4}o0:``<728qCh>?4}o0:`c<728qCh>?4}o0:a5<728qCh>?4}o0:a4<728qCh>?4}o0:a7<728qCh>?4}o0:a6<728qCh>?4}o0:a1<728qCh>?4}o0:a0<728qCh>?4}o0:a3<728qCh>?4}o0:a2<728qCh>?4}o0:a=<728qCh>?4}o0:a<<728qCh>?4}o0:ad<728qCh>?4}o0:ag<728qCh>?4}o0:af<728qCh>?4}o0:aa<728qCh>?4}o0:a`<728qCh>?4}o0:ac<728qCh>?4}o0:b5<728qCh>?4}o0:b4<728qCh>?4}o0:b7<728qCh>?4}o0:b6<728qCh>?4}o0:b1<728qCh>?4}o0:b0<728qCh>?4}o0:b3<728qCh>?4}o0:b2<728qCh>?4}o0:b=<728qCh>?4}o0:b<<728qCh>?4}o0:bd<728qCh>?4}o0:bg<728qCh>?4}o0:bf<728qCh>?4}o0:ba<728qCh>?4}o0:b`<728qCh>?4}o0:bc<728qCh>?4}o0b45<728qCh>?4}o0b44<728qCh>?4}o0b47<728qCh>?4}o0b46<728qCh>?4}o0b41<728qCh>?4}o0b40<728qCh>?4}o0b43<728qCh>?4}o0b42<728qCh>?4}o0b4=<728qCh>?4}o0b4<<728qCh>?4}o0b4d<728qCh>?4}o0b4g<728qCh>?4}o0b4f<728qCh>?4}o0b4a<728qCh>?4}o0b4`<728qCh>?4}o0b4c<728qCh>?4}o0b55<728qCh>?4}o0b54<728qCh>?4}o0b57<728qCh>?4}o0b56<728qCh>?4}o0b51<728qCh>?4}o0b50<728qCh>?4}o0b53<728qCh>?4}o0b52<728qCh>?4}o0b5=<728qCh>?4}o0b5<<728qCh>?4}o0b5d<728qCh>?4}o0b5g<728qCh>?4}o0b5f<728qCh>?4}o0b5a<728qCh>?4}o0b5`<728qCh>?4}o0b5c<728qCh>?4}o0b65<728qCh>?4}o0b64<728qCh>?4}o0b67<728qCh>?4}o0b66<728qCh>?4}o0b61<72:qCh>?4}o0b60<72:qCh>?4}o0b63<72:qCh>?4}o0b62<72:qCh>?4}o0b6=<72:qCh>?4}o0b6<<72:qCh>?4}o0b6d<72:qCh>?4}o0b6g<72:qCh>?4}o0b6f<72:qCh>?4}o0b6a<72:qCh>?4}o0b6`<72:qCh>?4}o0b6c<72:qCh>?4}o0b75<72:qCh>?4}o0b74<72:qCh>?4}o0b77<72:qCh>?4}o0b76<72:qCh>?4}o0b71<72:qCh>?4}o0b70<72:qCh>?4}o0b73<72:qCh>?4}o0b72<72:qCh>?4}o0b7=<72:qCh>?4}o0b7<<72:qCh>?4}o0b7d<72:qCh>?4}o0b7g<72:qCh>?4}o0b7f<72:qCh>?4}o0b7a<72:qCh>?4}o0b7`<72:qCh>?4}o0b7c<72:qCh>?4}o0b05<72:qCh>?4}o0b04<72:qCh>?4}o0b07<72:qCh>?4}o0b06<72:qCh>?4}o0b01<72:qCh>?4}o0b00<72:qCh>?4}o0b03<72:qCh>?4}o0b02<72:qCh>?4}o0b0=<72:qCh>?4}o0b0<<72:qCh>?4}o0b0d<72:qCh>?4}o0b0g<72:qCh>?4}o0b0f<72:qCh>?4}o0b0a<72:qCh>?4}o0b0`<72:qCh>?4}o0b0c<72:qCh>?4}o0b15<72:qCh>?4}o0b14<72:qCh>?4}o0b17<72:qCh>?4}o0b16<72:qCh>?4}o0b11<72:qCh>?4}o0b10<72:qCh>?4}o0b13<72:qCh>?4}o0b12<72:qCh>?4}o0b1=<72:qCh>?4}o0b1<<72:qCh>?4}o0b1d<72:qCh>?4}o0b1g<72:qCh>?4}o0b1f<72:qCh>?4}o0b1a<72:qCh>?4}o0b1`<72:qCh>?4}o0b1c<72:qCh>?4}o0b25<72:qCh>?4}o0b24<72:qCh>?4}o0b27<72:qCh>?4}o0b26<72:qCh>?4}o0b21<72:qCh>?4}o0b20<72:qCh>?4}o0b23<72:qCh>?4}o0b22<72:qCh>?4}o0b2=<72:qCh>?4}o0b2<<72:qCh>?4}o0b2d<72:qCh>?4}o0b2g<72:qCh>?4}o0b2f<72:qCh>?4}o0b2a<72:qCh>?4}o0b2`<72:qCh>?4}o0b2c<72:qCh>?4}o0b35<72:qCh>?4}o0b34<72:qCh>?4}o0b37<72:qCh>?4}o0b36<72:qCh>?4}o0b31<72:qCh>?4}o0b30<72:qCh>?4}o0b33<72:qCh>?4}o0b32<72:qCh>?4}o0b3=<72:qCh>?4}o0b3<<72:qCh>?4}o0b3d<72:qCh>?4}o0b3g<72:qCh>?4}o0b3f<72:qCh>?4}o0b3a<72:qCh>?4}o0b3`<72:qCh>?4}o0b3c<72:qCh>?4}o0b<5<72:qCh>?4}o0b<4<72:qCh>?4}o0b<7<72:qCh>?4}o0b<6<72:qCh>?4}o0b<1<72:qCh>?4}o0b<0<72:qCh>?4}o0b<3<72:qCh>?4}o0b<2<72:qCh>?4}o0b<=<72:qCh>?4}o0b<<<72:qCh>?4}o0b<d<72:qCh>?4}o0b<g<72:qCh>?4}o0b<f<72:qCh>?4}o0b<a<72:qCh>?4}o0b<`<72:qCh>?4}o0b<c<72:qCh>?4}o0b=5<72:qCh>?4}o0b=4<72:qCh>?4}o0b=7<72:qCh>?4}o0b=6<72:qCh>?4}o0b=1<72:qCh>?4}o0b=0<72:qCh>?4}o0b=3<72:qCh>?4}o0b=2<72:qCh>?4}o0b==<72:qCh>?4}o0b=<<72:qCh>?4}o0b=d<72:qCh>?4}o0b=g<72:qCh>?4}o0b=f<72:qCh>?4}o0b=a<72:qCh>?4}o0b=`<72:qCh>?4}o0b=c<72:qCh>?4}o0be5<72:qCh>?4}o0be4<72:qCh>?4}o0be7<72:qCh>?4}o0be6<72:qCh>?4}o0be1<72:qCh>?4}o0be0<72:qCh>?4}o0be3<72:qCh>?4}o0be2<72:qCh>?4}o0be=<72:qCh>?4}o0be<<72:qCh>?4}o0bed<72:qCh>?4}o0beg<72:qCh>?4}o0bef<72:qCh>?4}o0bea<72:qCh>?4}o0be`<72:qCh>?4}o0bec<72:qCh>?4}o0bf5<72:qCh>?4}o0bf4<72:qCh>?4}o0bf7<72:qCh>?4}o0bf6<72:qCh>?4}o0bf1<72:qCh>?4}o0bf0<72:qCh>?4}o0bf3<72:qCh>?4}o0bf2<72:qCh>?4}o0bf=<72:qCh>?4}o0bf<<72:qCh>?4}o0bfd<72:qCh>?4}o0bfg<72:qCh>?4}o0bff<72:qCh>?4}o0bfa<72:qCh>?4}o0bf`<72:qCh>?4}o0bfc<72:qCh>?4}o0bg5<72:qCh>?4}o0bg4<72:qCh>?4}o0bg7<72:qCh>?4}o0bg6<72:qCh>?4}o0bg1<72:qCh>?4}o0bg0<72:qCh>?4}o0bg3<72:qCh>?4}o0bg2<72:qCh>?4}o0bg=<72:qCh>?4}o0bg<<72:qCh>?4}o0bgd<72:qCh>?4}o0bgg<72:qCh>?4}o0bgf<72:qCh>?4}o0bga<72:qCh>?4}o0bg`<72:qCh>?4}o0bgc<72:qCh>?4}o0b`5<72:qCh>?4}o0b`4<72:qCh>?4}o0b`7<72:qCh>?4}o0b`6<72:qCh>?4}o0b`1<72:qCh>?4}o0b`0<72:qCh>?4}o0b`3<72:qCh>?4}o0b`2<72:qCh>?4}o0b`=<72:qCh>?4}o0b`<<72:qCh>?4}o0b`d<72:qCh>?4}o0b`g<72:qCh>?4}o0b`f<72:qCh>?4}o0b`a<72:qCh>?4}o0b``<72:qCh>?4}o0b`c<72:qCh>?4}o0ba5<72:qCh>?4}o0ba4<72:qCh>?4}o0ba7<72:qCh>?4}o0ba6<72:qCh>?4}o0ba1<72:qCh>?4}o0ba0<72:qCh>?4}o0ba3<72:qCh>?4}o0ba2<72:qCh>?4}o0ba=<72:qCh>?4}o0ba<<72:qCh>?4}o0bad<72:qCh>?4}o0bag<72:qCh>?4}o0baf<72:qCh>?4}o0baa<72:qCh>?4}o0ba`<72:qCh>?4}o0bac<72:qCh>?4}o0bb5<72:qCh>?4}o0bb4<72:qCh>?4}o0bb7<72:qCh>?4}o0bb6<72:qCh>?4}o0bb1<72:qCh>?4}o0bb0<72:qCh>?4}o0bb3<72:qCh>?4}o0bb2<72:qCh>?4}o0bb=<72:qCh>?4}o0bb<<72:qCh>?4}o0bbd<72:qCh>?4}o0bbg<72:qCh>?4}o0bbf<72:qCh>?4}o0bba<72:qCh>?4}o0bb`<72:qCh>?4}o0bbc<72:qCh>?4}o0a45<72:qCh>?4}o0a44<72:qCh>?4}o0a47<72:qCh>?4}o0a46<72:qCh>?4}o0a41<72:qCh>?4}o0a40<72:qCh>?4}o0a43<72:qCh>?4}o0a42<72:qCh>?4}o0a4=<72:qCh>?4}o0a4<<72:qCh>?4}o0a4d<72:qCh>?4}o0a4g<72:qCh>?4}o0a4f<72:qCh>?4}o0a4a<72:qCh>?4}o0a4`<72:qCh>?4}o0a4c<72:qCh>?4}o0a55<72:qCh>?4}o0a54<72:qCh>?4}o0a57<72:qCh>?4}o0a56<72:qCh>?4}o0a51<72:qCh>?4}o0a50<72:qCh>?4}o0a53<72:qCh>?4}o0a52<72:qCh>?4}o0a5=<72:qCh>?4}o0a5<<72:qCh>?4}o0a5d<72:qCh>?4}o0a5g<72:qCh>?4}o0a5f<72:qCh>?4}o0a5a<72:qCh>?4}o0a5`<72:qCh>?4}o0a5c<72:qCh>?4}o0a65<72:qCh>?4}o0a64<72:qCh>?4}o0a67<72:qCh>?4}o0a66<72:qCh>?4}o0a61<728qCh>?4}o0a60<728qCh>?4}o0a63<728qCh>?4}o0a62<728qCh>?4}o0a6=<728qCh>?4}o0a6<<728qCh>?4}o0a6d<728qCh>?4}o0a6g<728qCh>?4}o0a6f<728qCh>?4}o0a6a<728qCh>?4}o0a6`<728qCh>?4}o0a6c<728qCh>?4}o0a75<728qCh>?4}o0a74<728qCh>?4}o0a77<728qCh>?4}o0a76<728qCh>?4}o0a71<728qCh>?4}o0a70<728qCh>?4}o0a73<728qCh>?4}o0a72<728qCh>?4}o0a7=<728qCh>?4}o0a7<<728qCh>?4}o0a7d<728qCh>?4}o0a7g<728qCh>?4}o0a7f<728qCh>?4}o0a7a<728qCh>?4}o0a7`<728qCh>?4}o0a7c<728qCh>?4}o0a05<728qCh>?4}o0a04<728qCh>?4}o0a07<728qCh>?4}o0a06<728qCh>?4}o0a01<728qCh>?4}o0a00<728qCh>?4}o0a03<728qCh>?4}o0a02<728qCh>?4}o0a0=<728qCh>?4}o0a0<<728qCh>?4}o0a0d<728qCh>?4}o0a0g<728qCh>?4}o0a0f<728qCh>?4}o0a0a<728qCh>?4}o0a0`<728qCh>?4}o0a0c<728qCh>?4}o0a15<728qCh>?4}o0a14<728qCh>?4}o0a17<728qCh>?4}o0a16<728qCh>?4}o0a11<728qCh>?4}o0a10<728qCh>?4}o0a13<728qCh>?4}o0a12<728qCh>?4}o0a1=<728qCh>?4}o0a1<<728qCh>?4}o0a1d<728qCh>?4}o0a1g<728qCh>?4}o0a1f<728qCh>?4}o0a1a<728qCh>?4}o0a1`<728qCh>?4}o0a1c<728qCh>?4}o0a25<728qCh>?4}o0a24<728qCh>?4}o0a27<728qCh>?4}o0a26<728qCh>?4}o0a21<728qCh>?4}o0a20<728qCh>?4}o0a23<728qCh>?4}o0a22<728qCh>?4}o0a2=<728qCh>?4}o0a2<<728qCh>?4}o0a2d<728qCh>?4}o0a2g<728qCh>?4}o0a2f<728qCh>?4}o0a2a<728qCh>?4}o0a2`<728qCh>?4}o0a2c<728qCh>?4}o0a35<728qCh>?4}o0a34<728qCh>?4}o0a37<728qCh>?4}o0a36<728qCh>?4}o0a31<728qCh>?4}o0a30<728qCh>?4}o0a33<728qCh>?4}o0a32<728qCh>?4}o0a3=<728qCh>?4}o0a3<<728qCh>?4}o0a3d<728qCh>?4}o0a3g<728qCh>?4}o0a3f<728qCh>?4}o0a3a<728qCh>?4}o0a3`<728qCh>?4}o0a3c<728qCh>?4}o0a<5<728qCh>?4}o0a<4<728qCh>?4}o0a<7<728qCh>?4}o0a<6<728qCh>?4}o0a<1<728qCh>?4}o0a<0<728qCh>?4}o0a<3<728qCh>?4}o0a<2<728qCh>?4}o0a<=<728qCh>?4}o0a<<<728qCh>?4}o0a<d<728qCh>?4}o0a<g<728qCh>?4}o0a<f<728qCh>?4}o0a<a<728qCh>?4}o0a<`<728qCh>?4}o0a<c<728qCh>?4}o0a=5<728qCh>?4}o0a=4<728qCh>?4}o0a=7<728qCh>?4}o0a=6<728qCh>?4}o0a=1<728qCh>?4}o0a=0<728qCh>?4}o0a=3<728qCh>?4}o0a=2<728qCh>?4}o0a==<728qCh>?4}o0a=<<728qCh>?4}o0a=d<728qCh>?4}o0a=g<728qCh>?4}o0a=f<728qCh>?4}o0a=a<728qCh>?4}o0a=`<728qCh>?4}o0a=c<728qCh>?4}o0ae5<728qCh>?4}o0ae4<728qCh>?4}o0ae7<728qCh>?4}o0ae6<728qCh>?4}o0ae1<728qCh>?4}o0ae0<728qCh>?4}o0ae3<728qCh>?4}o0ae2<728qCh>?4}o0ae=<728qCh>?4}o0ae<<728qCh>?4}o0aed<728qCh>?4}o0aeg<728qCh>?4}o0aef<728qCh>?4}o0aea<728qCh>?4}o0ae`<728qCh>?4}o0aec<728qCh>?4}o0af5<728qCh>?4}o0af4<728qCh>?4}o0af7<728qCh>?4}o0af6<728qCh>?4}o0af1<728qCh>?4}o0af0<728qCh>?4}o0af3<728qCh>?4}o0af2<728qCh>?4}o0af=<728qCh>?4}o0af<<728qCh>?4}o0afd<728qCh>?4}o0afg<728qCh>?4}o0aff<728qCh>?4}o0afa<728qCh>?4}o0af`<728qCh>?4}o0afc<728qCh>?4}o0ag5<728qCh>?4}o0ag4<728qCh>?4}o0ag7<728qCh>?4}o0ag6<728qCh>?4}o0ag1<728qCh>?4}o0ag0<728qCh>?4}o0ag3<728qCh>?4}o0ag2<728qCh>?4}o0ag=<72:qCh>?4}o0ag<<72:qCh>?4}o0agd<72:qCh>?4}o0agg<72:qCh>?4}o0agf<728qCh>?4}o0aga<728qCh>?4}o0ag`<728qCh>?4}o0agc<728qCh>?4}o0a`5<728qCh>?4}o0a`4<728qCh>?4}o0a`7<728qCh>?4}o0a`6<728qCh>?4}o0a`1<728qCh>?4}o0a`0<728qCh>?4}o0a`3<728qCh>?4}o0a`2<728qCh>?4}o0a`=<728qCh>?4}o0a`<<728qCh>?4}o0a`d<728qCh>?4}o0a`g<728qCh>?4}o0a`f<728qCh>?4}o0a`a<728qCh>?4}o0a``<728qCh>?4}o0a`c<728qCh>?4}o0aa5<728qCh>?4}o0aa4<728qCh>?4}o0aa7<728qCh>?4}o0aa6<728qCh>?4}o0aa1<728qCh>?4}o0aa0<728qCh>?4}o0aa3<728qCh>?4}o0aa2<728qCh>?4}o0aa=<728qCh>?4}o0aa<<728qCh>?4}o0aad<728qCh>?4}o0aag<728qCh>?4}o0aaf<728qCh>?4}o0aaa<728qCh>?4}o0aa`<728qCh>?4}o0aac<728qCh>?4}o0ab5<728qCh>?4}o0ab4<728qCh>?4}o0ab7<728qCh>?4}o0ab6<728qCh>?4}o0ab1<728qCh>?4}o0ab0<728qCh>?4}o0ab3<728qCh>?4}o0ab2<728qCh>?4}o0ab=<728qCh>?4}o0ab<<728qCh>?4}o0abd<728qCh>?4}o0abg<728qCh>?4}o0abf<728qCh>?4}o0aba<728qCh>?4}o0ab`<728qCh>?4}o0abc<728qCh>?4}o0`45<728qCh>?4}o0`44<728qCh>?4}o0`47<728qCh>?4}o0`46<728qCh>?4}o0`41<728qCh>?4}o0`40<728qCh>?4}o0`43<728qCh>?4}o0`42<728qCh>?4}o0`4=<728qCh>?4}o0`4<<728qCh>?4}o0`4d<728qCh>?4}o0`4g<728qCh>?4}o0`4f<728qCh>?4}o0`4a<728qCh>?4}o0`4`<728qCh>?4}o0`4c<728qCh>?4}o0`55<72:qCh>?4}o0`54<72:qCh>?4}o0`57<72:qCh>?4}o0`56<728qCh>?4}o0`51<728qCh>?4}o0`50<728qCh>?4}o0`53<728qCh>?4}o0`52<728qCh>?4}o0`5=<728qCh>?4}o0`5<<728qCh>?4}o0`5d<728qCh>?4}o0`5g<728qCh>?4}o0`5f<728qCh>?4}o0`5a<728qCh>?4}o0`5`<728qCh>?4}o0`5c<728qCh>?4}o0`65<728qCh>?4}o0`64<728qCh>?4}o0`67<728qCh>?4}o0`66<72:qCh>?4}o0`61<72:qCh>?4}o0`60<72:qCh>?4}o0`63<72:qCh>?4}o0`62<72:qCh>?4}o0`6=<72:qCh>?4}o0`6<<72:qCh>?4}o0`6d<72:qCh>?4}o0`6g<72:qCh>?4}o0`6f<72:qCh>?4}o0`6a<72:qCh>?4}o0`6`<72:qCh>?4}o0`6c<728qCh>?4}o0`75<728qCh>?4}o0`74<728qCh>?4}o0`77<728qCh>?4}o0`76<728qCh>?4}o0`71<728qCh>?4}o0`70<728qCh>?4}o0`73<728qCh>?4}o0`72<728qCh>?4}o0`7=<728qCh>?4}o0`7<<728qCh>?4}o0`7d<728qCh>?4}o0`7g<728qCh>?4}o0`7f<728qCh>?4}o0`7a<728qCh>?4}o0`7`<728qCh>?4}o0`7c<728qCh>?4}o0`05<728qCh>?4}o0`04<728qCh>?4}o0`07<728qCh>?4}o0`06<728qCh>?4}o0`01<728qCh>?4}o0`00<728qCh>?4}o0`03<728qCh>?4}o0`02<728qCh>?4}o0`0=<728qCh>?4}o0`0<<728qCh>?4}o0`0d<728qCh>?4}o0`0g<728qCh>?4}o0`0f<728qCh>?4}o0`0a<728qCh>?4}o0`0`<728qCh>?4}o0`0c<728qCh>?4}o0`15<728qCh>?4}o0`14<728qCh>?4}o0`17<728qCh>?4}o0`16<728qCh>?4}o0`11<728qCh>?4}o0`10<728qCh>?4}o0`13<728qCh>?4}o0`12<728qCh>?4}o0`1=<728qCh>?4}o0`1<<728qCh>?4}o0`1d<728qCh>?4}o0`1g<728qCh>?4}o0`1f<728qCh>?4}o0`1a<728qCh>?4}o0`1`<728qCh>?4}o0`1c<728qCh>?4}o0`25<728qCh>?4}o0`24<728qCh>?4}o0`27<728qCh>?4}o0`26<728qCh>?4}o0`21<728qCh>?4}o0`20<728qCh>?4}o0`23<728qCh>?4}o0`22<728qCh>?4}o0`2=<728qCh>?4}o0`2<<728qCh>?4}o0`2d<728qCh>?4}o0`2g<728qCh>?4}o0`2f<728qCh>?4}o0`2a<728qCh>?4}o0`2`<728qCh>?4}o0`2c<728qCh>?4}o0`35<728qCh>?4}o0`34<728qCh>?4}o0`37<728qCh>?4}o0`36<728qCh>?4}o0`31<728qCh>?4}o0`30<728qCh>?4}o0`33<728qCh>?4}o0`32<728qCh>?4}o0`3=<728qCh>?4}o0`3<<728qCh>?4}o0`3d<728qCh>?4}o0`3g<728qCh>?4}o0`3f<728qCh>?4}o0`3a<728qCh>?4}o0`3`<728qCh>?4}o0`3c<728qCh>?4}o0`<5<728qCh>?4}o0`<4<728qCh>?4}o0`<7<728qCh>?4}o0`<6<728qCh>?4}o0`<1<728qCh>?4}o0`<0<728qCh>?4}o0`<3<728qCh>?4}o0`<2<728qCh>?4}o0`<=<728qCh>?4}o0`<<<728qCh>?4}o0`<d<728qCh>?4}o0`<g<728qCh>?4}o0`<f<728qCh>?4}o0`<a<728qCh>?4}o0`<`<728qCh>?4}o0`<c<728qCh>?4}o0`=5<728qCh>?4}o0`=4<728qCh>?4}o0`=7<728qCh>?4}o0`=6<728qCh>?4}o0`=1<728qCh>?4}o0`=0<728qCh>?4}o0`=3<728qCh>?4}o0`=2<728qCh>?4}o0`==<728qCh>?4}o0`=<<728qCh>?4}o0`=d<728qCh>?4}o0`=g<728qCh>?4}o0`=f<728qCh>?4}o0`=a<728qCh>?4}o0`=`<728qCh>?4}o0`=c<728qCh>?4}o0`e5<728qCh>?4}o0`e4<728qCh>?4}o0`e7<728qCh>?4}o0`e6<728qCh>?4}o0`e1<728qCh>?4}o0`e0<728qCh>?4}o0`e3<728qCh>?4}o0`e2<728qCh>?4}o0`e=<728qCh>?4}o0`e<<728qCh>?4}o0`ed<728qCh>?4}o0`eg<728qCh>?4}o0`ef<728qCh>?4}o0`ea<728qCh>?4}o0`e`<728qCh>?4}o0`ec<728qCh>?4}o0`f5<728qCh>?4}o0`f4<728qCh>?4}o0`f7<728qCh>?4}o0`f6<728qCh>?4}o0`f1<728qCh>?4}o0`f0<728qCh>?4}o0`f3<728qCh>?4}o0`f2<728qCh>?4}o0`f=<728qCh>?4}o0`f<<728qCh>?4}o0`fd<728qCh>?4}o0`fg<728qCh>?4}o0`ff<728qCh>?4}o0`fa<728qCh>?4}o0`f`<728qCh>?4}o0`fc<728qCh>?4}o0`g5<728qCh>?4}o0`g4<728qCh>?4}o0`g7<728qCh>?4}o0`g6<728qCh>?4}o0`g1<728qCh>?4}o0`g0<728qCh>?4}o0`g3<728qCh>?4}o0`g2<728qCh>?4}o0`g=<728qCh>?4}o0`g<<728qCh>?4}o0`gd<728qCh>?4}o0`gg<728qCh>?4}o0`gf<728qCh>?4}o0`ga<728qCh>?4}o0`g`<728qCh>?4}o0`gc<728qCh>?4}o0``5<728qCh>?4}o0``4<728qCh>?4}o0``7<728qCh>?4}o0``6<728qCh>?4}o0``1<728qCh>?4}o0``0<728qCh>?4}o0``3<728qCh>?4}o0``2<728qCh>?4}o0``=<728qCh>?4}o0``<<728qCh>?4}o0``d<728qCh>?4}o0``g<728qCh>?4}o0``f<728qCh>?4}o0``a<728qCh>?4}o0```<728qCh>?4}o0``c<728qCh>?4}o0`a5<728qCh>?4}o0`a4<728qCh>?4}o0`a7<728qCh>?4}o0`a6<728qCh>?4}o0`a1<728qCh>?4}o0`a0<728qCh>?4}o0`a3<728qCh>?4}o0`a2<728qCh>?4}o0`a=<728qCh>?4}o0`a<<728qCh>?4}o0`ad<728qCh>?4}o0`ag<728qCh>?4}o0`af<728qCh>?4}o0`aa<728qCh>?4}o0`a`<728qCh>?4}o0`ac<728qCh>?4}o0`b5<728qCh>?4}o0`b4<728qCh>?4}o0`b7<728qCh>?4}o0`b6<728qCh>?4}o0`b1<728qCh>?4}o0`b0<728qCh>?4}o0`b3<728qCh>?4}o0`b2<728qCh>?4}o0`b=<728qCh>?4}o0`b<<728qCh>?4}o0`bd<728qCh>?4}o0`bg<728qCh>?4}o0`bf<728qCh>?4}o0`ba<728qCh>?4}o0`b`<728qCh>?4}o0`bc<728qCh>?4}o0g45<728qCh>?4}o0g44<728qCh>?4}o0g47<728qCh>?4}o0g46<728qCh>?4}o0g41<728qCh>?4}o0g40<728qCh>?4}o0g43<728qCh>?4}o0g42<728qCh>?4}o0g4=<728qCh>?4}o0g4<<728qCh>?4}o0g4d<728qCh>?4}o0g4g<728qCh>?4}o0g4f<728qCh>?4}o0g4a<728qCh>?4}o0g4`<728qCh>?4}o0g4c<728qCh>?4}o0g55<728qCh>?4}o0g54<728qCh>?4}o0g57<728qCh>?4}o0g56<728qCh>?4}o0g51<728qCh>?4}o0g50<728qCh>?4}o0g53<728qCh>?4}o0g52<728qCh>?4}o0g5=<728qCh>?4}o0g5<<728qCh>?4}o0g5d<728qCh>?4}o0g5g<728qCh>?4}o0g5f<728qCh>?4}o0g5a<728qCh>?4}o0g5`<728qCh>?4}o0g5c<728qCh>?4}o0g65<728qCh>?4}o0g64<728qCh>?4}o0g67<728qCh>?4}o0g66<721;pDi=>;|l1`72=83;pDi=>;|l1`73=83;pDi=>;|l1`70=83;pDi=>;|l1`71=83;pDi=>;|l1`7>=83;pDi=>;|l1`7?=83;pDi=>;|l1`7g=83;pDi=>;|l25a5=838pDi=>;|l25a2=839pDi=>;|l25a3=839pDi=>;|l25a0=839pDi=>;|l25a1=839pDi=>;|l25a>=839pDi=>;|l25a?=839pDi=>;|l25ag=839pDi=>;|l25ad=839pDi=>;|l25ae=839pDi=>;|l25ab=839pDi=>;|l25ac=839pDi=>;|l25a`=839pDi=>;|l25`6=839pDi=>;|l25`7=839pDi=>;|l25`4=839pDi=>;|l25`5=839pDi=>;|l25`2=839pDi=>;|l25`3=839pDi=>;|l25`0=839pDi=>;|l25`1=839pDi=>;|l25`>=839pDi=>;|l25`?=839pDi=>;|l25`g=839pDi=>;|l25`d=839pDi=>;|l25`e=839pDi=>;|l25`b=839pDi=>;|l25`c=839pDi=>;|l25``=839pDi=>;|l25c6=839pDi=>;|l25c7=839pDi=>;|l;f6<728qCh>?4}o:a0?6=9rBo?<5rn9`6>5<6sAn8=6sa8c494?7|@m9:7p`7b683>4}Ol:;0qc6m8;295~Nc;81vb5l6:182Mb492we4om50;3xLa563td3ni4?:0yK`67<ug2ii7>51zJg74=zf1hm6=4>{If05>{i0j:1<7?tHe12?xh>;10;6<uGd238yk?413:1=vFk309~j<5f290:wEj<1:m=6d=83;pDi=>;|l:7f<728qCh>?4}o;0`?6=9rBo?<5rn81f>5<6sAn8=6sa92d94?7|@m9:7p`64083>4}Ol:;0qc7;3;295~Nc;81vb4:;:182Mb492we5om50;3xLa563td2ni4?:0yK`67<ug3ii7>51zJg74=zf0hm6=4>{If05>{i1j:1<7?tHe12?xh>k80;6<uGd238yk?d:3:1=vFk309~j<e4290:wEj<1:m=f3=83;pDi=>;|l:g2<728qCh>?4}o;`<?6=9rBo?<5rn`63>5<6sAn8=6saa5394?7|@m9:7p`n4383>4}Ol:;0qco;3;295~Nc;81vbl:;:182Mb492wem9;50;3xLa563tdj8;4?:0yK`67<ugk?;7>51zJg74=zfh>26=4>{If05>{ii=h1<7?tHe12?xhf<j0;6<uGd238ykgd<3:1=vFk309~jde2290:wEj<1:mef0=83;pDi=>;|lbg2<728qCh>?4}oc`<?6=9rBo?<5rn`a:>5<6sAn8=6saabc94?7|@m9:7p`ncc83>4}Ol:;0qcold;295~Nc;81vblmi:182Mb492wemi>50;3xLa563tdi854?:0yK`67<ugh?57>51zJg74=zfk>j6=4>{If05>{ij=h1<7?tHe12?xhe<j0;6<uGd238ykd3l3:1=vFk309~jg2b290:wEj<1:mf1`=83;pDi=>;|la14<728qCh>?4}o`67?6=9rBo?<5rnc77>5<6sAn8=6sabba94?7|@m9:7p`mce83>4}Ol:;0qclle;295~Nc;81vbomi:182Mb492weni>50;3xLa563tdih<4?:0yK`67<ugho>7>51zJg74=zfkn86=4>{If05>{ijm?1<7?tHe12?xhel>0;6<uGd238ykdc03:1=vFk309~jf37290:wEj<1:mg07=83;pDi=>;|l`17<728qCh>?4}oa67?6=9rBo?<5rnb77>5<6sAn8=6sac4794?7|@m9:7p`l5783>4}Ol:;0qcm:7;295~Nc;81vbn;6:182Mb492weo8l50;3xLa563tdh9n4?:0yK`67<ugio87>51zJg74=zfjn>6=4>{If05>{ikm<1<7?tHe12?xhdl>0;6<uGd238ykec03:1=vFk309~jfb>290:wEj<1:mgag=83;pDi=>;|l``g<728qCh>?4}oag`?6=9rBo?<5rnbfe>5<6sAn8=6sacd294?7|@m9:7p`k5983>4}Ol:;0qcj:9;295~Nc;81vbi;n:182Mb492weh8l50;3xLa563tdo9n4?:0yK`67<ugn>h7>51zJg74=zfm?n6=4>{If05>{il<l1<7?tHe12?xhc>80;6<uGd238ykb1;3:1=vFk309~ja03290:wEj<1:m`ae=83;pDi=>;|lg`a<728qCh>?4}ofga?6=9rBo?<5rnefe>5<6sAn8=6sadd294?7|@m9:7p`ke083>4}Ol:;0qcjj2;295~Nc;81vbik<:182Mb492wehh;50;3xLa563tdoi:4?:0yK`67<ugnn47>51zJg74=zfl<;6=4>{If05>{im?;1<7?tHe12?xhb>;0;6<uGd238ykc1;3:1=vFk309~j`03290:wEj<1:ma33=83;pDi=>;|lf23<728qCh>?4}og53?6=9rBo?<5rnd4:>5<6sAn8=6sae7`94?7|@m9:7p`j6b83>4}Ol:;0qckj4;295~Nc;81vbhk::182Mb492weih850;3xLa563tdni:4?:0yK`67<ugon47>51zJg74=zflo26=4>{If05>{imlk1<7?tHe12?xhbmk0;6<uGd238ykcbl3:1=vFk309~j`ca290:wEj<1:mac6=83;pDi=>;|le2=<728qCh>?4}od5=?6=9rBo?<5rng4b>5<6sAn8=6saf7`94?7|@m9:7p`i6b83>4}Ol:;0qch9d;295~Nc;81vbk8j:182Mb492wej;h50;3xLa563tdm;<4?:0yK`67<ugl<?7>51zJg74=zfo=?6=4>{If05>{inli1<7?tHe12?xhamm0;6<uGd238yk`bm3:1=vFk309~jcca290:wEj<1:mbc6=83;pDi=>;|leb4<728qCh>?4}ode6?6=9rBo?<5rngd0>5<6sAn8=6safg794?7|@m9:7p`if683>4}Ol:;0qchi8;295~Nc;81vb<>8f;295~Nc;81vb<>70;295~Nc;81vb<>71;295~Nc;81vb<>72;295~Nc;81vb<>73;295~Nc;81vb<>74;295~Nc;81vb<>75;295~Nc;81vb<>76;295~Nc;81vb<>78;295~Nc;81vb<>79;295~Nc;81vb<>7a;295~Nc;81vb<>7b;295~Nc;81vb<>7c;295~Nc;81vb<>7d;295~Nc;81vb<6;e;29f~Nc;81vb<6=e;295~Nc;81vb<6=f;295~Nc;81vb<6<0;295~Nc;81vb<6<1;295~Nc;81vb<6<2;295~Nc;81vb<6<3;295~Nc;81vb<6<4;295~Nc;81vb<6<6;295~Nc;81vb<6<7;295~Nc;81vb<6<8;295~Nc;81vb<6<9;295~Nc;81vb<6<b;295~Nc;81vb<6<c;295~Nc;81vb<7?0;29f~Nc;81vb<6j0;295~Nc;81vb<6j1;295~Nc;81vb<6j2;295~Nc;81vb<6j3;295~Nc;81vb<6j4;295~Nc;81vb<6j5;295~Nc;81vb<6j6;295~Nc;81vb<6j8;295~Nc;81vb<6j9;295~Nc;81vb<6ja;295~Nc;81vb<6jb;295~Nc;81vb<6jd;295~Nc;81vb<6je;295~Nc;81vb<7m2;29f~Nc;81vb<762;295~Nc;81vb<763;295~Nc;81vb<764;295~Nc;81vb<765;295~Nc;81vb<766;295~Nc;81vb<767;295~Nc;81vb<768;295~Nc;81vb<76a;295~Nc;81vb<76b;295~Nc;81vb<76c;295~Nc;81vb<76d;295~Nc;81vb<76f;295~Nc;81vb<7n0;295~Nc;81vqpsO@By07=3=l8n>?nlk}ABA5{GHYqvLM
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/ila128.vhd b/FEE_ADC32board/project/ipcore_dir/ila128.vhd
deleted file mode 100644
index ab1c82d..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila128.vhd
+++ /dev/null
@@ -1,31 +0,0 @@
--------------------------------------------------------------------------------
--- Copyright (c) 2012 Xilinx, Inc.
--- All Rights Reserved
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor     : Xilinx
--- \   \   \/     Version    : 13.3
---  \   \         Application: XILINX CORE Generator
---  /   /         Filename   : ila128.vhd
--- /___/   /\     Timestamp  : Thu Jul 19 13:26:41 W. Europe Daylight Time 2012
--- \   \  /  \
---  \___\/\___\
---
--- Design Name: VHDL Synthesis Wrapper
--------------------------------------------------------------------------------
--- This wrapper is used to integrate with Project Navigator and PlanAhead
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-ENTITY ila128 IS
-  port (
-    CONTROL: inout std_logic_vector(35 downto 0);
-    CLK: in std_logic;
-    TRIG0: in std_logic_vector(127 downto 0));
-END ila128;
-
-ARCHITECTURE ila128_a OF ila128 IS
-BEGIN
-
-END ila128_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/ila128.vho b/FEE_ADC32board/project/ipcore_dir/ila128.vho
deleted file mode 100644
index 79edc8c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila128.vho
+++ /dev/null
@@ -1,40 +0,0 @@
--------------------------------------------------------------------------------
--- Copyright (c) 2012 Xilinx, Inc.
--- All Rights Reserved
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor     : Xilinx
--- \   \   \/     Version    : 13.3
---  \   \         Application: Xilinx CORE Generator
---  /   /         Filename   : ila128.vho
--- /___/   /\     Timestamp  : Thu Jul 19 13:26:41 W. Europe Daylight Time 2012
--- \   \  /  \
---  \___\/\___\
---
--- Design Name: ISE Instantiation template
--- Component Identifier: xilinx.com:ip:chipscope_ila:1.05.a
--------------------------------------------------------------------------------
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component ila128
-  PORT (
-    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    CLK : IN STD_LOGIC;
-    TRIG0 : IN STD_LOGIC_VECTOR(127 DOWNTO 0));
-
-end component;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-
-your_instance_name : ila128
-  port map (
-    CONTROL => CONTROL,
-    CLK => CLK,
-    TRIG0 => TRIG0);
-
--- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/FEE_ADC32board/project/ipcore_dir/ila128.xco b/FEE_ADC32board/project/ipcore_dir/ila128.xco
deleted file mode 100644
index 78e418e..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila128.xco
+++ /dev/null
@@ -1,138 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.3
-# Date: Thu Jul 19 11:24:45 2012
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Structural
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
-# END Select
-# BEGIN Parameters
-CSET check_bramcount=false
-CSET component_name=ila128
-CSET constraint_type=embedded
-CSET counter_width_1=Disabled
-CSET counter_width_10=Disabled
-CSET counter_width_11=Disabled
-CSET counter_width_12=Disabled
-CSET counter_width_13=Disabled
-CSET counter_width_14=Disabled
-CSET counter_width_15=Disabled
-CSET counter_width_16=Disabled
-CSET counter_width_2=Disabled
-CSET counter_width_3=Disabled
-CSET counter_width_4=Disabled
-CSET counter_width_5=Disabled
-CSET counter_width_6=Disabled
-CSET counter_width_7=Disabled
-CSET counter_width_8=Disabled
-CSET counter_width_9=Disabled
-CSET data_port_width=0
-CSET data_same_as_trigger=true
-CSET disable_save_keep=false
-CSET enable_storage_qualification=true
-CSET enable_trigger_output_port=false
-CSET example_design=false
-CSET exclude_from_data_storage_1=false
-CSET exclude_from_data_storage_10=false
-CSET exclude_from_data_storage_11=false
-CSET exclude_from_data_storage_12=false
-CSET exclude_from_data_storage_13=false
-CSET exclude_from_data_storage_14=false
-CSET exclude_from_data_storage_15=false
-CSET exclude_from_data_storage_16=false
-CSET exclude_from_data_storage_2=false
-CSET exclude_from_data_storage_3=false
-CSET exclude_from_data_storage_4=false
-CSET exclude_from_data_storage_5=false
-CSET exclude_from_data_storage_6=false
-CSET exclude_from_data_storage_7=false
-CSET exclude_from_data_storage_8=false
-CSET exclude_from_data_storage_9=false
-CSET match_type_1=basic_with_edges
-CSET match_type_10=basic_with_edges
-CSET match_type_11=basic_with_edges
-CSET match_type_12=basic_with_edges
-CSET match_type_13=basic_with_edges
-CSET match_type_14=basic_with_edges
-CSET match_type_15=basic_with_edges
-CSET match_type_16=basic_with_edges
-CSET match_type_2=basic_with_edges
-CSET match_type_3=basic_with_edges
-CSET match_type_4=basic_with_edges
-CSET match_type_5=basic_with_edges
-CSET match_type_6=basic_with_edges
-CSET match_type_7=basic_with_edges
-CSET match_type_8=basic_with_edges
-CSET match_type_9=basic_with_edges
-CSET match_units_1=1
-CSET match_units_10=1
-CSET match_units_11=1
-CSET match_units_12=1
-CSET match_units_13=1
-CSET match_units_14=1
-CSET match_units_15=1
-CSET match_units_16=1
-CSET match_units_2=1
-CSET match_units_3=1
-CSET match_units_4=1
-CSET match_units_5=1
-CSET match_units_6=1
-CSET match_units_7=1
-CSET match_units_8=1
-CSET match_units_9=1
-CSET max_sequence_levels=1
-CSET number_of_trigger_ports=1
-CSET sample_data_depth=1024
-CSET sample_on=Rising
-CSET trigger_port_width_1=128
-CSET trigger_port_width_10=8
-CSET trigger_port_width_11=8
-CSET trigger_port_width_12=8
-CSET trigger_port_width_13=8
-CSET trigger_port_width_14=8
-CSET trigger_port_width_15=8
-CSET trigger_port_width_16=8
-CSET trigger_port_width_2=8
-CSET trigger_port_width_3=8
-CSET trigger_port_width_4=8
-CSET trigger_port_width_5=8
-CSET trigger_port_width_6=8
-CSET trigger_port_width_7=8
-CSET trigger_port_width_8=8
-CSET trigger_port_width_9=8
-CSET use_rpms=true
-# END Parameters
-GENERATE
-# CRC: 6cc4b31f
diff --git a/FEE_ADC32board/project/ipcore_dir/ila128.xise b/FEE_ADC32board/project/ipcore_dir/ila128.xise
deleted file mode 100644
index 0fc2cc0..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila128.xise
+++ /dev/null
@@ -1,72 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="ila128.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="ila128.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ila128|ila128_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="ila128.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ila128" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="ila128" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-19T13:26:50" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1DE8ABD5641346EB8572BE2AB4C22B42" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/ila128_readme.txt b/FEE_ADC32board/project/ipcore_dir/ila128_readme.txt
deleted file mode 100644
index 1e6f826..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila128_readme.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-The following files were generated for 'ila128' in directory
-D:\Xilinx_proj\Panda\test_seradc\ipcore_dir\
-
-XCO file generator:
-   Generate an XCO file for compatibility with legacy flows.
-
-   * ila128.xco
-
-Creates an implementation netlist:
-   Creates an implementation netlist for the IP.
-
-   * ila128.cdc
-   * ila128.ngc
-   * ila128.vhd
-   * ila128.vho
-
-Creates an HDL instantiation template:
-   Creates an HDL instantiation template for the IP.
-
-   * ila128.vho
-
-IP Symbol Generator:
-   Generate an IP symbol based on the current project options'.
-
-   * ila128.asy
-
-SYM file generator:
-   Generate a SYM file for compatibility with legacy flows
-
-   * ila128.sym
-
-Generate ISE metadata:
-   Create a metadata file for use when including this core in ISE designs
-
-   * ila128_xmdf.tcl
-
-Generate ISE subproject:
-   Create an ISE subproject for use when including this core in ISE designs
-
-   * _xmsgs/pn_parser.xmsgs
-   * ila128.gise
-   * ila128.xise
-
-Deliver Readme:
-   Readme file for the IP.
-
-   * ila128_readme.txt
-
-Generate FLIST file:
-   Text file listing all of the output files produced when a customized core was
-   generated in the CORE Generator.
-
-   * ila128_flist.txt
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/FEE_ADC32board/project/ipcore_dir/ila36.asy b/FEE_ADC32board/project/ipcore_dir/ila36.asy
deleted file mode 100644
index b14c26f..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila36.asy
+++ /dev/null
@@ -1,17 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 ila36
-RECTANGLE Normal 32 32 288 704
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName control[35:0]
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Wide 0 176 32 176
-PIN 0 176 LEFT 36
-PINATTR PinName trig0[35:0]
-PINATTR Polarity IN
-
diff --git a/FEE_ADC32board/project/ipcore_dir/ila36.gise b/FEE_ADC32board/project/ipcore_dir/ila36.gise
deleted file mode 100644
index 16eeb48..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila36.gise
+++ /dev/null
@@ -1,53 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="ila36.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="ila36.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ila36.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="ila36.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1343040841" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1343040841">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="9113925850006466910" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-3435590971552100386" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="3403158479962426638" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/ila36.ngc b/FEE_ADC32board/project/ipcore_dir/ila36.ngc
deleted file mode 100644
index 8a5fb2f..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila36.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$80a40<,[o}e~g`n;"2*731&=$:,)<4-03841=789:>7=>?01:8456789:;56>?0123456382:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789;;7=>?012345678HI;<<>40123457789:;<=>?4:23412<899M==5?04534037898;<=>;;133546<88;:<=?>00224566<2:9?=??;10;E10DM892N89KF993056789:?7=H=20926>779?1:<=4FNQWW>BGILVC7544?>06855<NFY__6JOAD^K?=?69<2;:<K?n;069MKVR\3KOH_O]D@FGV974294:m6?;:HLSQQ<FLMXI[_OKDS>27?699=1::7GAPTV9EABUI5;>6=0>4:35>LHW]]0JHI\M<0794;7338<1EC^ZT;FJEAO;9<0;2<:4178JJUSS2MCIHD2>5;2=50=6>3E^X][[:EMB@J:6=3:5=85>6;MVPUSS2MEIHB2>5;2=6>7E92897?>>6:03>LHW]]0X^AQN_H>2=?6990196D@_UU8B@ATF\@OCEJF31;2=5<=52@D[YY4NDEPAPLCOANB7=7>11591>LHW]]0OE]OKIQ>2>586<281EC^ZT;FJTGBNX5;1<3?:;38LQQVR\3ND\LJ@P=394;723;0DYY^ZT;FLTGBHX5;1<3??;3C3E7>70;8;>?>?000877<NFY__6IGN<2394;753:81EC^ZT;FJF956294:?6==:NWWTPR=LFK7?<4?>01877<H]]Z^X7J@B=12>5833:<:<<84378JJJSS2JEEX_AC<2794;733:<1EC^ZT;VQMB6;;<0;2<5;4:6245763=0BB][[:EKSE95=87;:794FNQWW>AOWJ591<3??;58JJUSS2^OJ0>4?>0280?OIX\^1[HL33;2=57=32F__\XZ5DNRB86<7688087AZTQWW>AIWJ591<3??;4760C@AM<?><KHIAd96>LHW]]0J094?>g95ri~6;9~mj96;-2683C@A991<JKHIFGDEBC@ANOL:75?=;98JJUSS2^OI[H28:1<1?D653H;97L<=;@124>G?I983>=67812;452<I5:586O31?68E949<2K7?384A=694;2<I5>5==5NA@CFACCFIHKNJKH=;@@24>GE8:KI<>OM02CB45><IMNYM1>19:CG@WG;99427LJKR@>25;?<IMNYM1?=>89B@ATF489556OKDSC?518e3HNO^L2>5;2==>GCL[K7=807;@FGVD:6611JHI\N<3<;?DBCZH68255NDEPB818?3HNO^L2:>99B@ATF4?437LJKR@>4:==FLMXJ0507;@FGVD:>6l1JHI\NRECG@W:76o1JHI\NRECG@W:687l0MIJ]ASFB@AT;984m7LJKR@PGEABU4885=<5NDEPBVAGCL[6:?7>1f:CG@WGULHNO^1?<>d9B@ATFZMKOH_2>>d9B@ATFZMKOH_2=>d9B@ATFZMKOH_2<>d9B@ATFZMKOH_2;>d9B@ATFZMKOH_2:>d9B@ATFZMKOH_29>d9B@ATFZMKOH_28>d9B@ATFZMKOH_27>d9B@ATFZMKOH_26>g9B@ATF\@OCEJF30?32?DBCZH^BIEGHH=394;`<IMNYMYGJHHEK848?3HNO^O2?>89B@ATE48:556OKDS@?548>3HNO^O2>2?;8EABUJ5;8245NDEPA8429j2KOH_L31483:<=FLMXI0<;18:CG@WD;9720MIJ]B=0=<>GCL[H7?364AEFQF92902KOH_L35?:8EABUJ5<546OKDS@?3;><IMNYN1618:CG@WD;17l0MIJ]BUKFLLAO494:=6OKDS@WM@NNOA6:6=0i;@FGVGRNMACLD1?1e:CG@WDPZHNO^1>1f:CG@WDPZHNO^1??>g9B@ATE_[KOH_2>1?d8EABUJ^XJHI\313<25>GCL[H\^LJKR=30>58a3HNO^OY]AEFQ8459m2KOH_LXR@FGV979m2KOH_LXR@FGV949m2KOH_LXR@FGV959m2KOH_LXR@FGV929m2KOH_LXR@FGV939m2KOH_LXR@FGV909m2KOH_LXR@FGV919m2KOH_LXR@FGV9>9m2KOH_LXR@FGV9?9;2KG@55MUR]JJCI63J80OLj4C@Q@EACNFEK_Mi5LARAB@@OIDH^Ih6MNSBCGALHUMNKo7NO\C@FFMKTBOKo0OL]LAEGLQQJF\Ho0OL]LAEGLQQJF\Ko0OL]LAEGLQQTBOHo0OL]LAEGLQQTBOK80OH?=;BJFGNYKAJOE_HQ[YQG1?FO43JF@86MCK148GIM609<0OAE=7178GIM5P11H@F<W1926?FJL19>0OAEN5:AOOD703JF@M<J=7:AOOD7C<>1H@FO>D9;8GIMFZMIGG95LLJ@6?FJLJ830OAEMWSAOO0=DDBI:96MCKE36?FJLL_i0OAEKV^FJRLBB=2IGGKV7;BNHB]7?8<1H@FQF3:AOV<=DGDGBXYKKa:ALJQTHD5:5n6M@NUPLH9776k1HCCZ]OM>25;d<KFD_^BB313<a?FII\[EG0<=1b:ALJQTHD5;?2o5LOOVQKI:6=7h0OB@[RNN?538e3JEEX_AC<05=f>EHF]XD@1?7>c9@KKRUGE6:53o4CNLWVJJ;97h0OB@[RNN?658e3JEEX_AC<33=f>EHF]XD@1<=>c9@KKRUGE69?3l4CNLWVJJ;:=4i7NAATSMO8739j2IDBY\@L=05:g=DGG^YCA2=7?`8GJHSZFF7>50m;BMMPWIK4;35m6M@NUPLH949j2IDBY\@L=13:g=DGG^YCA2<1?`8GJHSZFF7??0m;BMMPWIK4:95n6M@NUPLH9536m1HCCZ]OM>01?69j2IDBY\@L=16:d=DGG^YCA2<>`9@KKRUGE6?2l5LOOVQKI:26h1HCCZ]OM>5:d=DGG^YCA28>`9@KKRUGE632l5LOOVQKI:>68>0OB\J_FGMAWGSAFDTECH@7:AQADRBL81O:6J=_BNH0>B48;;;7IJK8EFG<C@AI<?><i5KEMCZAAYPZ@^N>6JF6:FJE969?2NBM1??>69GMD:697=0HDO313<4?AOF4895;6JFA=37:2=CAH6:9394DHC?53803MCJ0<917:FJE97?6>1OEL2>9?48@LG;97=0HDO321<4?AOF4;;5;6JFA=01:2=CAH69?394DHC?61803MCJ0?;17:FJE9416>1OEL2=7?58@LG;:14<7IGN<3;=2>BNI585;6JFA=13:<=CAH68=7>17:FJE9566?1OEL2<>79GMD:36?1OEL2:>79GMD:16?1OEL28>79GMD:?6?1OEL26>99GMDBN49427IGNDH>24;?<L@KOE1?>>89GMDBN488556JFAEK?568>3MCJHD2>4?`8@LGCA5;>6=06;EKB@L:6=720HDOKI=3=<>BNIMC7>364DHCGM95902NBMIG34?:8@LGCA5?546JFAEK?2;><L@KOE1918:FJEAO;0720HDOKI=;=2>BNJ5:5;6JFB=33:2=CAK6:=394DH@?57803MCI0<=17:FJF9736>1OEO2>5?58@LD;9?4<7IGM<05=3>BNJ5;32:5KIC>2=;0<L@H7=394DH@?65803MCI0??17:FJF9456>1OEO2=3?58@LD;:=4<7IGM<37=3>BNJ58=2:5KIC>13;1<L@H7>508;EKA87?9>2NBN1<17:FJF957601OEO2<1;2=3>BNJ59:2;5KIC>0:3=CAK6?2;5KIC>6:3=CAK6=2;5KIC>4:3=CAK632;5KIC>::==CAKNB0=06;EKA@L:68730HDLKI=32:<=CAKNB0<<19:FJFAO;9:427IGMDH>20;d<L@HOE1?::1<:?AOEL@6:9364DH@GM97902NBNIG32?:8@LDCA59546JFBEK?0;><L@HOE1;18:FJFAO;>720HDLKI=5=<>BNJMC74364DH@GM9?9?2NB\L2?>69GMUG;97=0HD^N<3<:?AOWI591<394DHRB868f3MC[MIG_<1<`?AOWIMC[0<4?>`9GMUGCAY6:2:5KIQ@?4;1<L@ZI0<08;EKSF94912NB\O2<:1<4?AOWJ595m6JFPCFJT969k2NB\OJFP=394;g<L@ZIHD^31?48@JG;87=0HBO311<4?AIF48;5;6J@A=31:2=CGH6:?394DNC?51803MEJ0<;17:FLE9716>1OCL2>7?58@JG;914<7IAN<0;=2>BHI5;5;6J@A=03:2=CGH69=394DNC?67803MEJ0?=17:FLE9436>1OCL2=5?58@JG;:?4<7IAN<35=3>BHI5832:5KO@>1=;0<LFK7>394DNC?758>3MEJ0>?50?58@JG;;84=7IAN<2<5?AIF4=4=7IAN<4<5?AIF4?4=7IAN<6<5?AIF414=7IAN<8<;?AIFLF6;245KO@FL846912NDMIA310<:?AIFLF6:>374DNCGK974601OCLJ@<06=f>BHIME7=84?>89GKDBH48?546J@AEM?5;><LFKOC1<18:FLEAI;;720HBOKO=6=<>BHIME79364DNCGK90902NDMIA37?:8@JGCG52546J@AEM?=;1<LFKT^HI9;EMA85803MEI0<>17:FLF9766>1OCO2>2?58@JD;9:4<7IAM<06=3>BHJ5;>2:5KOC>22;1<LFH7=:08;EMA84>9?2NDN1?6>79GKG:66>1OCO2=0?58@JD;:84<7IAM<30=3>BHJ5882:5KOC>10;1<LFH7>808;EMA8709?2NDN1<8>69GKG:507=0HBL328<5?AIE4;4<7IAM<22==>BHJ59:6=08;EMA8679>2NDN1=16:FLF929>2NDN1;16:FLF909>2NDN1916:FLF9>9>2NDN1718:FLFAI;8730HBLKO=33:<=CGKND0<?19:FLFAI;9;427IAMDN>27;?<LFHOC1?;>c9GKGBH48?1<374DN@GK972611OCOJ@<0<;?AIELF69255KOCFL868?3MEIHB2;>99GKGBH4<437IAMDN>5:==CGKND0:07;EMA@J:?611OCOJ@<8<4?AIEW[OL;6J@P@>3:2=CGYK7=394DNRB878>3ME[M1=50?58@JVF4:4j7IA_AEMS858d3ME[MIA_<083:d=CGYKOC]2>>69GKUD;87=0HB^M<0<4?AIWJ58556J@PC>0>5803ME[N1=1a:FLTGBHX5:5o6J@PCFLT97=87k0HB^MDNR?5;3<LVIGG<5J2:G76>CA;2OEM:5JN@PGAK5<MGH<7H@MWSGM0>@78;;;7K>I0GD34FEDKHKJM55IAG2BEFE23OKG_H<4FE33?CB0=K38=HM94@:146=ALJ>0JIMJ3:DGA6=ALY90JI\;;GFQA6=ALZ>0JKH?119EBC>AN12;<K6?09:7?C@AM8:0JKHIFGDE<D>?0123==5IFGDEBC@F:H=M>K9>0:DEBC@ANOLMJKON8133?C@ANOLMJKHIFGDEA4><N[EF,/J=_BNH&%RH(OLX,YGH199EVJK'NOY+XB.-D3]@HN$'\@M37K\@M^L@B4=@12MJBIQLI^K:?BGILVC7<3o4G@LG[L:687k0KL@K_H>25;g<OHDOSD2>2?c8CDHCW@6:?3o4G@LG[L:6<7k0KL@K_H>21;g<OHDOSD2>6?c8CDHCW@6:;3o4G@LG[L:607k0KL@K_H>2=;?<OHDOSD2>>`9DEKBXA58;2l5HAOF\M9466h1LMCJPI=01:d=@IGNTE1<<>`9DEKBXA58?2l5HAOF\M9426h1LMCJPI=05:d=@IGNTE1<8>`9DEKBXA5832l5HAOF\M94>601LMCJPI=0=e>AFFMUB0>>1a:EBJAYN4:;5m6INNE]J8649i2MJBIQF<21=e>AFFMUB0>:1a:EBJAYN4:?5m6INNE]J8609i2MJBIQF<25=e>AFFMUB0>61a:EBJAYN4:3556INNE]J868f3NKEHRG341<b?BGILVC78<0n;FCM@ZO;<;4j7JOAD^K?068f3NKEHRG345<b?BGILVC7880n;FCM@ZO;<?4j7JOAD^K?028f3NKEHRG349<b?BGILVC78406;FCM@ZO;<7k0KL@K_H>64;g<OHDOSD2:1?c8CDHCW@6>>3o4G@LG[L:2;7k0KL@K_H>60;g<OHDOSD2:5?c8CDHCW@6>:3o4G@LG[L:2?7k0KL@K_H>6<;g<OHDOSD2:9?;8CDHCW@6>2l5HAOF\M9076h1LMCJPI=42:d=@IGNTE18=>`9DEKBXA5<82l5HAOF\M9036h1LMCJPI=46:d=@IGNTE189>`9DEKBXA5<<2l5HAOF\M90?6h1LMCJPI=4::<=@IGNTE181a:EBJAYN4>:5m6INNE]J8279i2MJBIQF<60=e>AFFMUB0:=1a:EBJAYN4>>5m6INNE]J8239i2MJBIQF<64=e>AFFMUB0:91a:EBJAYN4>25m6INNE]J82?912MJBIQF<6<b?BGILVC74=0n;FCM@ZO;084j7JOAD^K?<78f3NKEHRG382<b?BGILVC7490n;FCM@ZO;0<4j7JOAD^K?<38f3NKEHRG386<b?BGILVC7450n;FCM@ZO;00427JOAD^K?<;g<OHDOSD260?c8CDHCW@62=3o4G@LG[L:>:7k0KL@K_H>:7;g<OHDOSD264?c8CDHCW@6293o4G@LG[L:>>7k0KL@K_H>:3;g<OHDOSD268?a8CDHCW@6257>1a:EBJAYN4035n6INNE]J8<<7601LMCJPI=;=2>AFFMUD?6IAD79KQZUB\81B>6G?2:K26>O5:2C8>6G;2:K6<>OIA]ZT<=64IOKWTZ6602CEEY^P03:8MKOSXV:846GAIUR\41><AGC_\R>:8:KMMQVX8?20ECG[P^24<>OIA]ZT<564IOKWTZ6>02CEEY^P0@:8MKOSXV:I46GAIUR\4F><AGC_\R>K8:KMMQVX8L20ECG[P^2E=>OIA]Y_MYK8;HLJPZ67?2CEEYQ?169JJLRX8;=0ECG[_114?LHN\V:?;6GAIU]312=NF@^T<;94IOKW[5103@DBXR>77:KMMQY71>1BBDZP0@58MKOSW9H<7D@FT^2@3>OIA]U;H:5FNHV\4@1<AGC_S=H8;HLJPZ77?2CEEYQ>169JJLRX9;=0ECG[_014?LHN\V;?;6GAIU]212=NF@^T=;94IOKW[4103@DBXR?77:KMMQY61>1BBDZP1@58MKOSW8H<7D@FT^3@3>OIA]U:H:5FNHV\5@1<AGC_S<H8;HLJPZ47?2CEEYQ=169JJLRX:;=0ECG[_314?LHN\V8?;6GAIU]112=NF@^T>;94IOKW[7103@DBXR<77:KMMQY51>1BBDZP2@58MKOSW;H<7D@FT^0@3>OIA]U9H:5FNHV\6@1<AGC_S?H8;HLJPZ57?2CEEYQ<169JJLRX;;=0ECG[_214?LHN\V9?;6GAIU]012=NF@^T?;94IOKW[6103@DBXR=77:KMMQY41>1BBDZP3@58MKOSW:H<7D@FT^1@3>OIA]U8H:5FNHV\7@1<AGC_S>H8;HLJPZ27?2CEEYQ;169JJLRX<;=0ECG[_514?LHN\V>?;6GAIU]712=NF@^T8;94IOKW[1103@DBXR:77:KMMQY31>1BBDZP4@58MKOSW=H<7D@FT^6@3>OIA]U?H:5FNHV\0@1<AGC_S9H8;HLJPZ37?2CEEYQ:169JJLRX=;=0ECG[_414?LHN\V??;6GAIU]612=NF@^T9;94IOKW[0103@DBXR;77:KMMQY21>1BBDZP5@58MKOSW<H<7D@FT^7@3>OIA]U>H:5FNHV\1@1<AGC_S8H8;HLJPZ07?2CEEYQ9169JJLRX>;=0ECG[_714?LHN\V<?;6GAIU]512=NF@^T:;94IOKW[3103@DBXR877:KMMQY11>1BBDZP6@58MKOSW?H<7D@FT^4@3>OIA]U=H:5FNHV\2@1<AGC_S;H8;HLJPZ17?2CEEYQ8169JJLRX?;=0ECG[_614?LHN\V=?;6GAIU]412=NF@^T;;94IOKW[2103@DBXR977:KMMQY01>1BBDZP7@58MKOSW>H<7D@FT^5@3>OIA]U<H:5FNHV\3@1<AGC_S:H9;HLJPZG13@DBXRL6;HLJPZ@NDL90ECX<6:K\MVYSM[GBBLZFOO]PHLEBWGO;"DQZSD]LQQVR\VXNKR@J0/W\KWC@:81BSD]PTDPNMKGSAFDT_AGLE^LF4+SXE\RM>=5F_QCQPLGKWZFBOH Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP<P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP=P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP>P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP?P Z_FCM@ZUUDVYGENK=d:K\SMIKMVYGENK!G^QOMFCXAMRP8P Z_FCM@ZUUDVYGENK;;JGFT6=KLJ80@D<4LN48HJGCMM<0@BMDEE58HJANKHF?7A[[159OQQ433E__?95CUU67?ISS==1GYY8;;LQFP2=J]QIRSA;4MTZE30=J]QL3o6CnjnpUawunggi0Ad``rWgqwlii:2D;>6@>3:L0<6=I<990B9?<;O613>HB\^EYG;5AOBNJT2=IGDOYKH:4NNLF5>I?3F$<:ujPL09S0>VFZ]k0\D@PBTQJ@]d<X@DTNX]AALG:?UMX@E__B@=4PSG5?UUCGGO:7\=4Q070?T5692X37_OBB0:F53=UIDH8:k5]AL]F\QCI[@EESLh4R@O\A]RBFZCDBRL7;SCN[HICM830^IOKDS]@KIJN[@EESEYLOODJCf=UMHNT[DJ[H^C`?WCFLV]BHYFPB49QABEB>2XNKNKNb:PFCFCFZLMHI;5]EFAFFa=UMNIGGL\KRBNH3>TBOJF@N:5]ERGW[L2<ZEEHh6\\TSCNEWUSZHG<7_][R@OA`>TT\[OLM_][RDE4?WUSZLMI=<5]SUPFCZVUAFXBXTQN109QWQTBOVZYEB\FTX]A5>U33ZKMI55\AWGGEQG692YC^HIPEYVQEFRXFNIn7^F]EF]NMKYTASO:?6]FM^ALHIOTAFDTOEKLK99PMHYJGMO37^EFP^RJJ3=TG\XHI85\RM352>UUD8<N;6]]LB35A2=TZEI8>Ho4SSN\EZO;87h0__BPA^K?558e3ZXGSLQF<03=f>UUDVKTE1?=>c9PVIYFW@6:?3l4SSN\EZO;9=4i7^\C_@]J8439j2YY@ROPI=35:g=TZEUJSD2>7?`8WWJXIVC7=50k;RPO[DYN4831<3l4SSN\EZO;904j7^\C_@]J848f3ZXGSLQF<3<b?VTKWHUB0>0n;RPO[DYN4=4j7^\C_@]J808f3ZXGSLQF<7<b?VTKWHUB0:0n;RPO[DYN414j7^\C_@]J8<8?3ZXGSNKPI89PVIYDDBUB;6]]L^F\M2=TZEUZSB94SSTBHZG03ZX]MAQM4:QPVD2<[ZXI:6][AUWP7>RCX11_I_CFN@N;?QOJMZZNO>5[NL58PKKXFL^37Y\FG1>3:<=SZ@M;0<>19:VQMB6;98427Y\FG1>26;?<\[CL<1?<>89WVLA748>556Z]IF2?508>3]XBK=2>6?;8PWO@85;<245[RHE384>912^YEJ>318<;?QTNO96:245[RHE3876912^YEJ>320<:?QTNO969>374TSKD4944601_^DI?<36==>RUAN:7>806;UPJC5:5>730X_GH0=04:<=SZ@M;0?619:VQMB6;:0437Y\FG1>1:<=SZ@M;0>>19:VQMB6;;8427Y\FG1>06;?<\[CL<1=<>89WVLA74:>5n6Z]IF2?70<7601_^DI?<27=<>RUAN:7?364TSKD492902^YEJ>35?:8PWO@85<546Z]IF2?3;><\[CL<1618:VQMB6;17>0X_[Jb:VP[A4X\FU_>o5[S^H1[QIXL;h0X^QE3^VL[A4e3]YTF9Q[O^F10>R^XL9n7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\8T$BS^\CT^LF[5(CDP38o6[?/H]MKZB)]VCGM"GPDP,V[AWV'MFRS4 KLX]:[BCIS9W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\99W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;;Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;:Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=<S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=?S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?=]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV?<]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T12_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T15_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ37Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ36Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX50[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX53[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^71U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^70U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\9>W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\91W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;3Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR;2Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=4S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP=P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW<S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>=S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<?]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<>]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T20_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T23_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ01Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ00Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX66[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX61[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^43U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^42U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\:<W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\:?W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR8=Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR8<Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>:S!I^QQHQYIMV:%JK=i;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP>5S!I^QQHQYIMV:%HAW63e9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<7]/K\WWJSWGOT<#HI3g9V4*OXFFUO"XQFL@-J[AW)]VNZ]"JCY^;-@I_X1VMNBV<6]/K\WWJSWGOT<#JCY81g?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T28_-MZUUD]UEIR>!FG1f?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T2\,J[VTK\VDNS= KLX;0g>S7'@UECRJ!U^KOE*OXLX$^SI_^/ENZ[<(CDPU2SJKA[3_-MZUUD]UEIR>!FG1e?P6(AVDDSI Z_HNB+LYCY'_TH\_ DM[\=+BKQV3TKH@T31_-MZUUD]UEIR>!DM[:7a=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ13Y+OX[[F_SCKP0/DE7c=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.FO]Z?)LEST5RIJNZ12Y+OX[[F_SCKP0/FO]<5c3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX74[)AVYY@YQAE^2-BC5a3\:$ER@@_E,V[LJF'@UO]#[PDPS,@I_X1'NGUR7PGDLX77[)AVYY@YQAE^2-@I_>;m1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^55U'CT__B[_OG\4+@A;o1^<"GPNN]G*PYNDH%BSI_!U^FRU*BKQV3%HAWP9^EFJ^54U'CT__B[_OG\4+BKQ09o7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;:W%ER]]LU]MAZ6)NO9m7X> I^LL[A(RW@FJ#DQKQ/W\@TW(LEST5#JCY^;\C@H\;=W%ER]]LU]MAZ6)LES2?i5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR9?Q#GPSSNW[KCX8'LM?k5Z0.K\JJYC&\UB@L!F_ES-QZBVY&NGUR7!DM[\=ZABFR9>Q#GPSSNW[KCX8'NGU4=k;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP?8S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP?P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW>S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP8P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW9S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP9P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW8S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP:P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW;S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP;P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW:S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP4P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW5S!I^QQHQYIMV:%JK=j;T2,MZHHWM$^SDBN/H]GU+SXLX[$HAWP9/FO]Z?XOLDP5P F_RPOPZHBW9$O@T7<c:W3+LYIGVN%YRGCA.K\@T(RWM[Z#IBV_8,GH\Y>WNOEW4S!I^QQHQYIMV:%JK<=;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<1<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9776;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7=<0=3:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=31:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;9:49?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1?;>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?5085;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5;=2?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~316<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt97?6;90Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7=40=2:W3+LYIGVN%YRGCA.K\@T(RWM[Z#ykbp=3=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:587887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0??1229V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>16;443\:$ER@@_E,V[LJF'@UO]#[PDPS,p`kw4;95>>5Z0.K\JJYC&\UB@L!F_ES-QZBVY&~na}2=4?00?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8739::1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey69:3<<;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<35=66=R8&CTBBQK.T]JHD)NWM[%YRJ^Q.vfiu:507887X> I^LL[A(RW@FJ#DQKQ/W\@TW(|lg{0?71239V4*OXFFUO"XQFL@-J[AW)]VNZ]"zjmq>1:75<]9%BSCAPD/W\MIG(AVNZ"XQKQP-wahv;;949?6[?/H]MKZB)]VCGM"GPDP,V[AWV'}of|1=>>318Q5)NWGETH#[PIMC,MZBV&\UO]\!{elr?7785;2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5982?=4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~335<17>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt9526;80Y=!F_OM\@+SXAEK$ERJ^.T]GUT)smdz7?3<=;T2,MZHHWM$^SDBN/H]GU+SXLX[$xhc<5<16>S7'@UECRJ!U^KOE*OXLX$^SI_^/ugnt939:;1^<"GPNN]G*PYNDH%BSI_!U^FRU*rbey6=2?<4U1-J[KIXL'_TEAO I^FR*PYCYX%i`~37?01?P6(AVDDSI Z_HNB+LYCY'_TH\_ tdos8=85:2_;#DQAO^F-QZOKI&CTH\ Z_ESR+qcjx5359>5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZIUW[NT^BYPEO7:?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_TC_Q]SU]Q@ZTH_V]BHH9<;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*OX_@N_DR8!u^v`+\CTWE__:#[PLTV51a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$ob{at=2=1a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$ob{at=3=1a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$ob{at=0=1a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$ob{at=1=1a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$ob{at=6=1a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$ob{at=7=1==R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$~~z90:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[D)rWjd#NG31?43?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz CH>1:36<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UJ#xQlnu-@M959>91^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*EN4=4=<6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'JC793;i;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$H1>15g9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZG(}Viex"J31?7e?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz D=0=1c=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.F?7;3a3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,@929=o1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*B;=7<i7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(OR:V"J`G.T]NQ]E^>?1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*A\8T$^SKJ]E778Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYF'|Uhby!H[1_-QZJR\?=0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QN/t]`jq)@S9W%YRV@RB[5f>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWH%~Sn`{/FY2Y+Ai@'_TAXVLY748Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYF'|Uhby!H[0_-QZ@CZL<>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(OR;V"XQCUU44?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz GZ3^*PY_G[IR:o5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&MP>P HnI,V[HS_KP<=7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr(OR8V"XQIDSG51>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWH%~Sn`{/FY1Y+SXD\^=;6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_@-v[fhs'NQ9Q#[PXNP@]3d<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UJ#xQlnu-D_6[)OgB%YRCZXB[52>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWH%~Sn`{/FY0Y+SXNMXN:85Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&MP?P Z_MWW22=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.EX7X(RWQEYOT8m;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXkg~$KV:R.FlK*PYJ]QIR:;5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&MP8P Z_GFQA33<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UJ#xQlnu-D_1[)]VF^X;94U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]B+pYdf}%LW9S!U^ZLVF_1>2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSL!z_blw+B]2U'_TJI\J649V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZG(}Viex"IT5\,V[ISS>>1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*A\=T$^SUA]CX7e?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXI&Tocz S=2=1c=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVK$yRmat.Q?5;3a3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTM"{Pcov,W949=o1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RO u^amp*U;;7?m7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PA.w\gkr([5>59k5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^C,qZei|&Y793;n;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\E*sXzz~<?6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-J[ROC\AU>"xQ{c.[FWZJR\?$^SA[[54:8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'{y:=5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&IB0<090:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[G)rWjd#NG32?43?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXJ&Tocz CH>0:36<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-@M929=o1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RL u^amp*B;87?m7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PB.w\gkr(L5;59k5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&N7>3;i;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%BS@[CT^PLS+SXZMUHCAQNDEP\F*sXkg~$H1=15g9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZD(}Viex"J34?4a?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXJ&Tocz GZ2^*BhO&\UFYUMV679V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#DQBUMV\VJQ)]VXOSNAC_@FGVZD(}Viex"IT0\,V[CBUM??0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QM/t]`jq)@S9W%YRBZT758Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!H[1_-QZ^HZJS=n6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'NQ:Q#IaH/W\IP^DQ?<0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QM/t]`jq)@S8W%YRHKRD46?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXJ&Tocz GZ3^*PYK]]<<7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)NWD_GXR\@W/W\VAYDGEUJHI\PB.w\gkr(OR;V"XQWOSAZ2g=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVH$yRmat.EX6X(@fA$^S@[WCX45?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXJ&Tocz GZ0^*PYAL[O=96[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'NQ9Q#[PLTV53>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/FY1Y+SXPFXHU;l4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&CTAXB[_SMT*PYULVID@ROKDS]A+pYdf}%LW>S!GoJ-QZKRPJS=:6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[fhs'NQ8Q#[PFEPF20=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/H]NQIRXZF]%YR\K_BMO[DBCZVH$yRmat.EX7X(RWE__::5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^@,qZei|&MP?P Z_YMQG\013\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-J[HSK\VXD[#[PRE]@KIYFLMXTN"{Pcov,C^2Z&\UMH_K95:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[G)rWjd#JU;]/W\HPR1?2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_blw+B]3U'_TTB\LY4d8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"GPMTNW[WIP&\UYHRM@L^CG@WYE'|Uhby!\<1<6b>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ I^OVHQYUG^$^S_JPCNN\EABUWK%~Sn`{/R>2:0`<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UI#xQlnu-P8782n2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,MZKRD]UYCZ Z_SF\GJJXIMNYSO!z_blw+V:46<l0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*OXE\F_S_AX.T]Q@ZEHDVKOH_QM/t]`jq)T4=4>m6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(AVG^@YQ]OV,V[WBXKFFTMIJ]_C-v[wus>h1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+LYJ]E^T^BY!U^PG[FIKWHNO^RJCY.E\V@AXJ@^P<P Z_GFQA3g<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.K\IPJSW[E\"XQ]D^ALHZGCL[UO@T!H_SGD[GOSS8W%YRHKRD4b?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_T^IQLOM]B@ATXLES$KR\JG^@JP^4Z&\UMH_K9a:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RW[NTOBBPAEFQ[AJ^'NUYIJQMIUY0Y+SXNMXN:l5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'@UFYAZPRNU-QZTCWJEGSLJKR^FO]*AXZLMTNDZT4\,V[CBUM080Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZHG$ERX9.T]@WZDUIDUHM^MNDD]U2*OXLLZ_DRB[EP]06N(RWZHYM@Q?/H]A5=M@\9$~Sobb0:,QZTFEK;3I<7l;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_OB/H]U2+SXKZUI^LCPC@Q@EACX^?%BSIK_TI]OP@WX;;A%YR]MR@O\4*OXJ82@KY>!u^pbig7?'\UYM@L>8D3\mkurdh~n<4m4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^LC I^T5*PYD[VHYM@QLARAB@@YQ>&CTHH^[H^NWATY4:B$^S^L]AL]3+LYE;?ALX= H_SCNF60\8T$~Sobb24,QZTFEK9=9o5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHRM@L^OV\*O2&\UFYU==/Lov|ZIX99?o7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NTOBBPMTZ,M0(RWD_S??!Bmtz\KZ4Xn>?j7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NTOBBPMTZ,M0(RWD_S??!Bmtz\KZ52j2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCWJEGS@[W/H7-QZKRP:8$A`{w_N]050g<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYDGEUFYU!F5/W\IP^4:&GfyuQ@_57a?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\GJJXE\R$E8 Z_LW[77)Je|rTCR:>5e9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^ALHZKRP&C>"XQBUY11+HkrpVET:Rh85`9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^ALHZKRP&C>"XQBUY11+HkrpVET;8o4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQLOM]NQ])N='_TAXV<2.Onq}YHW1?i7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NTOBBPMTZ,M0(RWD_S??!Bmtz\KZ>6=h1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVID@RCZX.K6*PYJ]Q99#@czx^M\=0d<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYDGEUFYU!F5/W\IP^4:&GfyuQ@_837a>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"MF<02=0a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!LI=3=0a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!LI=0=0a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!LI=1=0a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!LI=6=0a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!LI=7=0a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!LI=4=0a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!LI=5=0a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!LI=:=0a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!LI=;=0f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!K<1<7`>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"J311<7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"J31?6`?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#I2=>5a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$H1=14b9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%O090;c:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&N793:l;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'M6=29m4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(L5=58n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)C414?o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*B;17?37X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]7U'MeD#[PMTZ@]05<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ2^*PYAL[O>>6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\8T$^SA[[559V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW=S!U^ZLVF_2<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX55[)]VLO^H;<;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ:<P Z_MWW10=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[02^*PY_G[IR955Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S8W%KcF!U^OV\F_2;2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX5X(RWONYI8<4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR;V"XQCUU77?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU>]/W\\JTDQ<20Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^4Z&NdC"XQBUYAZ16=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[3_-QZ@CZL?97X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]5U'_T@XZ:4:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP>P Z_YMQG\3?3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY0Y+Ai@'_TAXVLY418Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV=R.T]E@WC2:2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX7X(RWE__995Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)@S:W%YRV@RB[6<>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT4\,DjM(RWD_SOT;<;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ?Q#[PFEPF17=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[5_-QZJR\<>0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,C^2Z&\USC_MV599V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW8S!GoJ-QZKRPJS>?6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\=T$^SKJ]E408Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$KV;R.T]OQQ333\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-V[WBXZF]TMIJ]/FY6Y+SXPFXHU864U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR<V"J`G.T]NQ]E^=:1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_3[)]VLO^H;=;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'NQ=Q#[PLTV60>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ U^PG[WIPWHNO^"IT6\,V[]IUKP?37X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]0U'MeD#[PMTZ@]05<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ5^*PYAL[O>>6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*A\?T$^SA[[559V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%LW:S!U^ZLVF_202_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,QZTCW[E\SLJKR.EX<X(@fA$^S@[WCX70?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!Z_SF\VJQXIMNY#JU7]/W\BATB=;1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-D_=[)]VF^X8:4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT(OR2V"XQWOSAZ1==R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/T]Q@ZTH_VKOH_!H[8_-CkN)]VG^TNW:3:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&MP5P Z_GFQA04<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.W\VAYUG^UJHI\ GZ;^*PYK]]??7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+B]>U'_TTB\LY5a8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"[PRE]QKRYFLMX$_1>14e9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%X0<>14b9V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#XQ]D^PLSZGCL[%X0<0;c:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$YR\K_SMT[DBCZ&Y7>3:l;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%^S_JPRNU\EABU'Z6829m4U1-J[KIXL'_TEAO U^ABTVRHZ&CTOL]J1/K\]@UX\K$^SY\NCD]AQC@BZ&_T^IQ]OV]B@AT([5>58n5Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'\UYHR\@W^CG@W)T4<4?o6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(]VXOS_AX_@FGV*U;>7>h7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)RW[NT^BYPAEFQ+V:06=i0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*SXZMUYCZQNDEP,W9>9<j1^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+PYULVXD[ROKDS-P8<83k2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYdgeUjhi|Pdm{?4;2d3\:$ER@@_E,V[LJF'\UHM]][OS-J[FGTM8$BSTK\_U@-QZRUIJOTNXHIES-q`ZehdVkohQklx>2:1e<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[fikWhno~Rjcy=0=0a=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\gjjXimnySibv<3<20f=R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\gjjXimnySibv<2<7g>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]`kiYflmxThaw34?6g?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^alhZgcl{U|eik30?6g?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^alhZgcl{U|eik31?6g?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^alhZgcl{U|eik32?6g?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^alhZgcl{U|eik33?6g?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^alhZgcl{U|eik34?6f?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^alhZgcl{U|eikPrrv70>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;87>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2>0?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:697>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2>2?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:6;7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2>4?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:6=7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2>6?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:6?7>>7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2>8?66?P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!}d^fbpd:617>?7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl2>>578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_ecwe9476=?0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1<>>578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_ecwe9456=?0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1<<>578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_ecwe9436=?0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1<:>578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_ecwe9416=>0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcWmkm1<1459V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPd`vb8683<2_;#DQAO^F-QZOKI&_TOL^\TNP,MZEF[L;%ERWJS^VA*PYSZHINSO[IFDP,vaYci}k783:;;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhRjnt`>6:12<]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[agsi5<5895Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nThlzn<6<70>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]geqg;07>?7X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVnjxl26>5:8Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_smt[dbcz5:5845Z0.K\JJYC&\UB@L!Z_BCSWQIU'@UHM^K>.H]ZAVYSJ'_TX_OLE^@VBCCU'{nT~byPaefq8469<11^<"GPNN]G*PYNDH%^SNO_SUMQ+LYDIZO:"DQVER]WF+SX\[KHIRLZFGGQ+wbXzf}Tmij}<0<7<>S7'@UECRJ!U^KOE*SXKHZXXB\ I^ABW@7)AVSN_RZM.T]WVDEBWK_MJH\ re]qkrYflmx7>3:7;T2,MZHHWM$^SDBN/T]@EUUSG[%BSNO\E0,J[\CTW]H%YRZ]ABG\FP@AM[%yhR|`w^cg`w:46=20Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcW{e|Sljkr=6=0==R8&CTBBQK.T]JHD)RWJK[_YA]/H]@EVC6&@URI^Q[B/W\PWGDMVH^JKK]/sf\vjqXimny080;8:W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$~iQ}ov]b`at;>7>37X> I^LL[A(RW@FJ#XQLAQQWKW)NWJKXI< F_XGP[QD)]V^YMNKPBTDEAW)ulVxd{Rokds>4:1><]9%BSCAPD/W\MIG(]VIJ\^Z@R.K\GDUB9'CTUH]PTC,V[QTFKLUIYKHJR.pg[wipWhno~161499V4*OXFFUO"XQFL@-V[FGW[]EY#DQLARG2*LY^MZU_N#[PTSC@AZDRNOOY#jPrnu\eabu404??6[?/H]MKZB)]VCGM"[PC@RPPJT(AVIJ_H?!I^[FWZRE&\U_^LMJ_CWEB@T(zmUyczQjn578Q5)NWGETH#[PIMC,QZEFXZ^D^"GPC@QF5+OXQLYTXO Z_UPBG@YE]OLN^"|k_smt[`hXi=?0Y=!F_OM\@+SXAEK$YRMNPRVLV*OXKHYN=#GPYDQ\PG(RW]XJOHQMUGDFV*tcW{e|Sh`Pb048Q5)NWGETH#[PIMC,QZBH]]8i7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!LMQ]QAVCS;<1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQFNUABTZ@)]VIJ\ZK?349V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYNF]IJ\RH!U^ABTRC6=j1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UHHB@J/H]ZAVJR\?$BSTK\_SRN*LY^MZUD^HI!OTV\V@A292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VIOCCK I^[FWISS>'CTUH]PRQO-QZKRPO=>?6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YRMKOOG,MZ_B[E__:#GPYDQ\VUK)]VYY@><PA418Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\GAIIM&CTUH]CUU4-MZ_B[VX[A#[PSSN06ZD3?2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VIOCCK I^[FWISS>'YY@RCZX558Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\GAIIM&CTUH]CUU4-WWJXY:;?46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YRMKOOG,MZ_B[E__:#]]L^S?4;2?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWJNDBH!F_XGPHPR1&ZXGS\2>>468Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\GHVUMZO_#DQVERNVP3(NWPOXS_^B.T]NQ]@0=?1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UHA]\JSDV,MZ_B[E__:#GPYDQ\VUK)]VYY@><PA448Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\GHVUMZO_#DQVERNVP3(NWPOXS_^B.T]PVI55WK>j7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SNC_RDQFP*OXQLYGYY8!SSN\U673j2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VIF\_K\EU-J[\CTD\^="^\C_P>3:1d<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXKDZYI^K[/H]ZAVJR\?$X^AQ^<0<6e>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT8&CTUH]CUU4-MZ_B[VX[A#GPYDQ\KWC@&F__S_KH539V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW5)NWPOX@XZ9.H]ZAVYUXD$^S@[WF6]BF04<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&CT__B[_OG\5+SXFZ:$ERWJSMWW2+OXQLYT^]C!U^OV\C1XKM>m7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^SC]?/H]ZAVJR\?$BSTK\_SRN*PYJ]QL39<5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQAS1-J[\CTD\^="DQVER]QTH(RWZXG??QN509V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW5)NWPOX@XZ9.H]ZAVYUXD$^S^\C33]A14=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[9%BSTK\LTV5*LY^MZUY\@ Z_RPO77YD=81^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UE_=!F_XGPHPR1&@URI^Q]PL,V[VTK;;UO845Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQAS1-J[\CTD\^="^\C_LW[3969<01^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UE_=!F_XGPHPR1&ZXGS@[W7=3=03=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[9%BSTK\LTV5*VTKWD_S4964U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR2,MZ_B[E__:#]]L^S05969<11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UE_=!F_XGPHPR1&ZXGS\=><0<7<>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT8&CTUH]CUU4-WWJXY:;7>3:9;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-J[VTK\VDNS< Z_OQ3+LY^MZF^X; \RM]R8583>2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX<"GPYDQOQQ0)[[FT]1?1479V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]MW5)NWPOX@XZ9.RPO[T:56=<0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_TB^> I^[FWISS>'YY@R_33?7b?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU6'@URI^BZT7,J[\CTW[ZF"DQVER]LV@A)G\^T^HI:2:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP5*OXQLYGYY8!I^[FWZTWE'_TAXVI7^CA17=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'@UX^AZPND]2*PYI[8%BSTK\LTV5*LY^MZUY\@ Z_LW[B2YDL=l0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"GPSSNW[KCX9'_TB^? I^[FWISS>'CTUH]PRQO-QZKRPO2>=6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR@\1.K\]@UK]]<%ERWJS^PSI+SX[[F8>RO:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP5*OXQLYGYY8!I^[FWZTWE'_T__B<2^@65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT9&CTUH]CUU4-MZ_B[VX[A#[PSSN06ZE292_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX="GPYDQOQQ0)AVSN_R\_M/W\WWJ4:VN?56[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR@\1.K\]@UK]]<%__BPMTZ4858312_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX="GPYDQOQQ0)[[FTAXV8<0<72>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(AVYY@YQAE^3-QZHT9&CTUH]CUU4-WWJXE\R3855Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQAS0-J[\CTD\^="^\C_P12858302_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$ER]]LU]MAZ7)]VDX="GPYDQOQQ0)[[FT]>?31?6;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)NWZXGXR@J_0,V[KU6'@URI^BZT7,PVIYV;8692984U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.K\WWJSWGOT=#[PNR3,MZ_B[E__:#]]L^S?4;213\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWGY:#DQVERNVP3(TZEUZ0<0;6:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,MZUUD]UEIR?!U^LP5*OXQLYGYY8!SSN\U949<?1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#DQ\RMV\J@Y6&\UE_<!F_XGPHPR1&ZXGS\2<>558Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*OX[[F_SCKP1/W\WFC(AVSN_A[[6/W\WWJD9?O?46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR]LMQAF+LY^MZF^X; Z_RPO77363\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWZIY_Y!F_XGPHPR1&@URI^Q]PL,V[HS_N>?87X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!F_RPOPZHBW8$^S^M]SU-J[\CTD\^="DQVER]QTH(RWZXG??QN529V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]PGWUS'@URI^BZT7,J[\CTW[ZF"XQ\RM11[G203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RWZIY_Y!F_XGPHPR1&ZXGS\=>499V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]PGWUS'@URI^BZT7,PVIYV494?46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B I^QQHQYIMV;%YR]LRRV,MZ_B[E__:#]]L^S?5;203\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%BS^\CT^LF[4(RW^IN#DQVERNVP3(RWZXGO<8J489V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+LYTZE^TBHQ>.T]TLFKWKL%BSTK\LTV5*PYTZE99845Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/H]PVIRXFLU:"XQXLBOSG@)NWPOX@XZ9.T]PVI55:01^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#^MAT^AF6d=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'ZIEXRMBP3f8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*UDF]UHA]QLE3a8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*UDF]UHA]Q^2b9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+VEI\VXN_HZ;0:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.ABTZGCL[Ueiuz30?63?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+FGWWHNO^R`jxu>2:16<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(KHZTMIJ]_og{p949<91^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%HM]QNDEP\j`~s4:4?<6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"MNP^CG@WYimq~783:?;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/BCS[DBCZVdnty2:>528Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,GDVXIMNYSckwt=4=05=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)DIYUJHI\Pndzw828382_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&IJ\ROKDS]ma}r;07>;7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#NO__@FGVZhbp}622974U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^2\PJY1<B$MS^KC[1_-QZUBD=k0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER>PTN]50N(AWZOGW<>R.T]PAI2f3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@U;SYAP65I-BZUBDR;:Q#[PSDN7e>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX8V^DS;:D.G]PAI]6:T$^S^KC4`9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[5YSGV<?G#HPSDNX56[)]VYN@9o4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^2\PJY1<B$MS^KC[06^*PYTME>j7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ?_UM\21M)NVYN@V?:]/W\W@J312_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT<RZ@_76H*CYTMEQ:Q#[PSDN7=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX8V^DS;:D.G]PAI]5U'_T_HB;9:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\4ZRHW?>@"KQ\EMY0Y+SX[LF?56[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GP0^VL[32L&OUXIAU;]/W\W@J312_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT<RZ@_76H*CYTMEQ>Q#[PSDN7=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX8V^DS;:D.G]PAI]1U'_T_HB;9:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\4ZRHW?>@"KQ\EMY4Y+SX[LF?56[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GP0^VL[32L&OUXIAU7]/W\W@J312_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT<RZ@_76H*CYTMEQ2Q#[PSDN73>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX8V^DS;:D.H]PVI(RWZOGT8?4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX4X(RWJK[SLJKR478Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZOI\JK["KQLAQ]B@AT\8T$^SNO__@FGVZKRP<80Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ERGATBCS*CYDIYUJHI\T0\,V[lEFXVKOH_;>;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_4[)]VIJ\ROKDS76?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYNF]IJ\#HPC@R\EABUS8W%YRMNP^CG@WYJ]Q?97X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQFNUABT+@XKHZTMIJ][0_-QZoDIYUJHI\:1:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^4Z&\UHM]QNDEP61>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXAG^HM] I_BCS[DBCZR8V"XQLAQ]B@ATXE\R>>6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPIOV@EU(AWJK[SLJKRZ0^*PYnKHZTMIJ]509V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[LHSKHZ%JRMNP^CG@W]4U'_TOL^PAEFQ10=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW@D_OL^!F^ABTZGCL[Q8Q#[PC@R\EABUWD_S9?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_HLWGDV)NVIJ\ROKDSY0Y+SXaJK[SLJKR438Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZOI\JK["KQLAQ]B@AT\<T$^SNO__@FGV03<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVCEXNO_.G]@EUYFLMXP8P Z_BCS[DBCZVG^T8<4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^KMPFGW&OUHM]QNDEPX0X(RW`IJ\ROKDS72?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYNF]IJ\#HPC@R\EABUS<W%YRMNP^CG@W323\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UBBYMNP/D\GDVXIMNYW8S!U^ABTZGCL[UFYU;=;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]JJQEFX'LTOL^PAEFQ_0[)]VcHM]QNDEP65>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXAG^HM] I_BCS[DBCZR<V"XQLAQ]B@AT2=2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTECZLAQ,E[FGWWHNO^V8R.T]@EUYFLMXTAXV:2:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\MKRDIY$MSNO__@FGV^0Z&\UbOL^PAEFQ14=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NW@D_OL^!F^ABTZGCL[Q<Q#[PC@R\EABU=<1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSD@[C@R-BZEFXVKOH_U8]/W\GDVXIMNYS@[W539V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[LHSKHZ%JRMNP^CG@W]0U'_TeNO__@FGV07<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVCEXNO_.G]@EUYFLMXP4P Z_BCS[DBCZ<?0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ERGATBCS*CYDIYUJHI\T8\,V[FGWWHNO^RCZX408Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZOI\JK["KQLAQ]B@AT\0T$^SdMNP^CG@W363\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UBBYMNP/D\GDVXIMNYW4S!U^ABTZGCL[?>7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQFNUABT+@XKHZTMIJ][8_-QZEFXVKOH_QBUY71?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYNF]IJ\#HPC@R\EABUS0W%YRgLAQ]B@AT2:2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)DA5;59?5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$OD2=>408Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/BK?7;353\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*EN4=4>>6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%HE1;1539V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ CH>5:04<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+FO;?7?97X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&IB050:2:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!LI=;=14=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,@969=81^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(L5;59<5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$H1<1509V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ D=1=14=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,@929=81^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(L5?59<5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$H181509V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ D=5=14=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,@9>9=81^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(L5359i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV>R.FlK*PYJ]QIR955Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV>R.T]E@WC2?2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S9W%YRBZT4;8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY3Y+SXPFXHU8j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU>]/EmL+SXE\RHU864U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU>]/W\BATB=>1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(OR;V"XQCUU7:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX5X(RWQEYOT;k;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT2\,DjM(RWD_SOT;7;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT2\,V[CBUM<=0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ9Q#[PLTV6=>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-D_7[)]VRD^NW:d:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[2_-CkN)]VG^TNW:8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[2_-QZ@CZL?<7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP?P Z_MWW1<=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,C^5Z&\USC_MV5e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ6^*BhO&\UFYUMV599V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ6^*PYAL[O>;6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPNN]WW@W)AVYY@YQAE^3-QZUDF]%LW9S!U^NVP0?<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+B]3U'_TTB\LY4f8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY6Y+Ai@'_TAXVLY4:8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZHHW]YN]#GPSSNW[KCX9'_T_N@[/FY6Y+SXNMXN9:5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_OM\PVCV&@UX^AZPND]2*PYTKG^$KV;R.T]OQQ3>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*A\=T$^SUA]CX7g?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX2X(@fA$^S@[WCX7;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.EX2X(RWONYI894U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^LL[QUBY'CT__B[_OG\5+SX[JD_#JU9]/W\HPR212_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CTBBQ[SDS-MZUUD]UEIR?!U^Q@JQ)@S?W%YRV@RB[6`>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-D_2[)OgB%YRCZXB[6<>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OXFFU__H_!I^QQHQYIMV;%YR]LNU-D_2[)]VLO^H;8;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"IT7\,V[ISS=01^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BSCAPTRGR*LYTZE^TBHQ>.T]PGKR(OR=V"XQWOSAZ1a=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,C^>Z&NdC"XQBUYAZ1==R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWGETX^K^.H]PVIRXFLU:"XQ\COV,C^>Z&\UMH_K:7:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\JJYS[L[%ER]]LU]MAZ7)]VYHBY!H[9_-QZJR\<30Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER@@_UQFU+OX[[F_SCKP1/W\WFHS'NQ3Q#[PXNP@]0><]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVDDSY]JQ/K\WWJSWGOT=#[PSBLW+B]>U'_TJI\J569V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[KIX\ZOZ"DQ\RMV\J@Y6&\UXOCZ GZ;^*PYK]]?27X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&MP5P Z_YMQG\363\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*U;87?:7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&Y7=3;>;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"]32?72?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.Q?7;363\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*U;<7?:7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&Y793;>;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]MKZRTMX$BS^\CT^LF[4(RWZIEX"]36?72?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYIGV^XI\ F_RPOPZHBW8$^S^MAT.Q?3;363\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UECRZ\EP,J[VTK\VDNS< Z_RAMP*U;07?:7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQAO^VPAT(NWZXGXR@J_0,V[VEI\&Y753:7;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,GL:66=20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!LI=0=0==R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&IB0>0;8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+FO;<7>37X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ CH>6:1><]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%HE181499V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*EN4>4?46[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/BK?<;2?3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$OD26>558Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)C494?;6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/E>2:11<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%O0?0;7:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+A:46==0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!K<5<73>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'M6>2994U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-G8383?2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#I28>558Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)C414?;6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/E>::05<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%LW=S!GoJ-QZKRPJS?i6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY3Y+SXNMXN8i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.EX4X(RWE__8k5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!F_RPOPZHBW8$^SZMAT.EX4X(RWQEYOT;<;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,C^7Z&NdC"XQBUYAZ0`=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP=P Z_GFQA1b<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%LW<S!U^NVP1`<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%LW<S!U^ZLVF_2;2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU=]/EmL+SXE\RHU9k4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_7[)]VLO^H:k;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,C^4Z&\UGYY:i;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/H]PVIRXFLU:"XQXCOV,C^4Z&\USC_MV529V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\;T$LbE Z_LW[G\2b3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV=R.T]E@WC3l2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU<]/W\HPR3n2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU<]/W\\JTDQ<90Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[5_-CkN)]VG^TNW;e:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+B]3U'_TJI\J4e9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\<T$^SA[[4g9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-J[VTK\VDNS< Z_VAMP*A\<T$^SUA]CX70?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR?V"J`G.T]NQ]E^<l1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%BS^\CT^LF[4(RW^IEX"IT5\,V[CBUM=n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[4_-QZJR\=l0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!H[4_-QZ^HZJS>?6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY5Y+Ai@'_TAXVLY5g8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)@S?W%YRHKRD6g?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR<V"XQCUU6e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+LYTZE^TBHQ>.T]TGKR(OR<V"XQWOSAZ16=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP;P HnI,V[HS_KP>n7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#DQ\RMV\J@Y6&\U\OCZ GZ5^*PYAL[O?h6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY4Y+SXD\^?j6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/FY4Y+SXPFXHU8=4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-D_=[)OgB%YRCZXB[7a>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'NQ3Q#[PFEPF0a=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP4P Z_MWW0c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)NWZXGXR@J_0,V[REI\&MP4P Z_YMQG\2b3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'@UX^AZPND]2*PYPKG^$KV7R.T]E@WC3l2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU6]/W\HPR3n2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#JU6]/W\\JTDQ==0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!\<1<73>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'Z6:2994U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ I^QQHQYIMV;%YRYLNU-P8783?2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&CT__B[_OG\5+SX_JD_#^2<>558Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,MZUUD]UEIR?!U^U@JQ)T4=4?;6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"GPSSNW[KCX9'_T[N@[/R>6:11<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(AVYY@YQAE^3-QZQDF]%X0;0;7:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.K\WWJSWGOT=#[PWBLW+V:06==0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$ER]]LU]MAZ7)]V]HBY!\<9<73>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*OX[[F_SCKP1/W\SFHS'Z622>84U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ U^@QO5513\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'\UI^F?75:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.W\WFHSWJG[#DQLS^EBJA(RWJYTKL@K_RPO+LYQ>'_TO^QHAOF\WWJX^?%BSX]J_SRN[KC7&\ULMCJPSSN\W@R?>2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&_T[N@[_IANT*OXKZULMCJ!U^AP[BGILVYY@"GPV7,V[FUXOHDOS^\C_W4,MZSTMVX[AR@J0/W\CDHCWZXGS^K[879V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-V[REI\VFHA]!F_BQ\CDHC&\UH_RINNE]PVI)NW_<%YRM\_FCM@ZUUDV\=#DQZSD]QTHYIM9$^SJOAD^QQHZUB\:h0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$okiPd`vb8584j2_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&imkRjnt`>2:6d<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(komThlzn<3<0f>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*eaoVnjxl2<>2`8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,gcaXlh~j090;0:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.aecZbf|hU}in2>0?63?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+f``WmkmRxjc=32:16<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(komThlzn_wg`8449<91^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%hjjQkauc\r`e;9:4?<6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^ABTZGCL[MNB"mig^fbpdYqmj6:83:?;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/bdd[agsiV|no1?:>528Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,gcaXlh~jS{kl<04=7c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)dnnUomyoPvda?5;5a3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'jllSio{a^tfg949;o1^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%hjjQkauc\r`e;;79m7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_BCS[DBCZNOE#nhh_ecweZpbk5>5?k5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!lff]geqgX~li793=i;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/bdd[agsiV|no1813g9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-`bbYci}kTzhm37?1e?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+f``WmkmRxjc=:=7c=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)dnnUomyoPvda?=;5d3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SNO__@FGVBCI'`IJ\ROKDS>3:6e<]9%BSCAPD/W\MIG(]VM9S^_!U^ABTFRUD&_TOL^PAEFQC@H(aJK[SLJKR=3=7f=R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)nKHZTMIJ]<3<0g>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*oDIYUJHI\33?1`?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+lEFXVKOH_2;>2a8Q5)NWGETH#[PIMC,QZA5WZ[%YRMNPBVQH*SXKHZTMIJ]GDL,mFGWWHNO^1;13b9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYDIYUJHI\HEO-jGDVXIMNY0;0<c:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.k@EUYFLMX7;3=l;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/hABTZGCL[632>m4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ iBCS[DBCZ535?55Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/T]@EUYFLMXLIC!fSBLW858402_;#DQAO^F-QZOKI&_TK?Q\Q/W\GDVD\[F$YRMNP^CG@WABF&cXOCZ31?1;?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RWJK[SLJKRFGM+lUDF]692>64U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.W\GDVXIMNYKH@ iRAMP959;11^<"GPNN]G*PYNDH%^SJ<PSP,V[FGWK]XG#XQLAQ]B@AT@MG%b_N@[<5<0<>S7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*oTKG^793=7;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[FGWWHNO^JKA/hQ@JQ:16:20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@"[PC@R\EABUOLD$e^MAT=5=7==R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTK'\UHM]QNDEPDAK)n[JD_050<8:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN,QZEFXVKOH_IJN.kPGKR;178n7X> I^LL[A(RW@FJ#XQH2^QR*PYDIYI_^A!Z_RAMPZEJXV[946[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B U^VQMB4>3\:$ER@@_E,V[LJF'\UL>R]^.T]@EUESZE%^SY\FG10:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)RW]XBK<<i;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-V[REI\VBHA]Q^2g9V4*OXFFUO"XQFL@-V[B4X[X$^SNO_CUPO+PYPKG^T@NC__P0:?P6(AVDDSI Z_HNB+PY@:VYZ"XQLAQAWVI)PKG^TOH<m;T2,MZHHWM$^SDBN/T]D6ZUV&\UHM]M[RM-TGKRX@JG[>h5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/VAMPZNDEYUHI?j4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.U@JQYOKDZT]?l4U1-J[KIXL'_TEAO U^E1[VW)]VIJ\NZ]L.U@JQYKKDZ9i6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B WBLW[IEJXVIN>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/VAMPZJDEYUZ>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/bdd[agsi5:5>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/bdd[agsi5;5>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/bdd[agsi585>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/bdd[agsi595>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/bdd[agsi5>5>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/bdd[agsi5?5>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/bdd[agsi5<5>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/bdd[agsi5=5>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/bdd[agsi525>i5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/bdd[agsi535>n5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C/hABTZQUWLD9h6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B iUPJCBCUW@D9i6[?/H]MKZB)]VCGM"[PG3]PU+SXKHZHX_B iUPJCBCUWF__?l5Z0.K\JJYC&\UB@L!Z_F0\WT(RWJK[OY\C_H]PVIRXFLU:"XQLDNLF[HUB\:n0Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@RGPSSNW[KCX9'_TO@^]ERGW[HUB\:20Y=!F_OM\@+SXAEK$YRI=_RS-QZEFXJ^Y@RGPSSNW[KCX9'_TB^>PMRGW7==R8&CTBBQK.T]JHD)RWN8T_\ Z_BCSGQTKW@UX^AZPND]2*PYI[8UF_HZ<a:W3+LYIGVN%YRGCA.W\C7YTY'_TOL^LTSN\MZUUD]UEIR?!U^Q@VVRXEZO_>95Z0.K\JJYC&\UB@L!Z_SQW+BYU[]Q;Q#[PRRV10>S7'@UECRJ!U^KOE*SXZZ^$KR\\TZ3^*PYU[]8?7X> I^LL[A(RW@FJ#XQ]SU-D[WUSS;W%YR\\T368Q5)NWGETH#[PIMC,QZTT\&MT^^ZT3\,V[WUS:=1^<"GPNN]G*PYNDH%^S_][/F]QWQ]3U'_T^^Z=4:W3+LYIGVN%YRGCA.W\VVR(OVXXXV;R.T]QWQ433\:$ER@@_E,V[LJF'\UY_Y!H_SQW_3[)]VXXX?:4U1-J[KIXL'_TEAO U^PPP*AXZZ^P;P Z_SQW65=R8&CTBBQK.T]JHD)RW[Y_#EOCT^rvhvc612_;#DQAO^F-QZOKI&_T^^Z PNP14>S7'@UECRJ!U^KOE*SXZZ^$\_KPRDQFP5473\:$ER@@_E,V[LJF'\UY_Y!_RD]QAVCS9;20Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#XQLLDCQ62=R8&CTBBQK.T]JHD)RW[Y_#XQNRL][B@T(]VNDYY<7;T2,MZHHWM$^SDBN/T]QWQ)RWHXFSUHJR.W\@JSS8;20Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#XQKOTV271=R8&CTBBQK.T]JHD)RW[Y_#XQNRL][B@T(]VMNBRJJL@[X5X(RWON886[?/H]MKZB)]VCGM"[PRRV,QZGUEVRMI_!Z_FGM[ACKIPQ9Q#[PFE17?P6(AVDDSI Z_HNB+PYU[]%^SL\B_YDFV*SXOLDTHHBNYZ1^*PYAL:>0Y=!F_OM\@+SXAEK$YR\\T.W\EWKXPOOY#XQHEO]GAIG^S=W%YRHK299V4*OXFFUO"XQFL@-V[WUS'\UJ^@QWFDP,QZTAL[O946[?/H]MKZB)]VCGM"[PRRV,QZGUEVRMI_!Z_UDGV@4d3\:$ER@@_E,V[LJF'\UY_Y!Z_@PN[]@BZ&nbbRbntbjf`73<]9%BSCAPD/W\MIG(]VXXX"[PASO\\CCU'`IG^?64U1-J[KIXL'_TEAO U^PPP*SXI[GTTKK]/hFJJ969:11^<"GPNN]G*PYNDH%^S_][/T]BVHY_NLX$eIGA<0<12>S7'@UECRJ!U^KOE*SXZZ^$YRO]M^ZEAW)nLF__>i5Z0.K\JJYC&\UB@L!Z_SQW+PYFZDUSJH\ iEMVPZbkq5:5>i5Z0.K\JJYC&\UB@L!Z_SQW+PYFZDUSJH\ iEMVPZbkq5;5>i5Z0.K\JJYC&\UB@L!Z_SQW+PYFZDUSJH\ iEMVPZbkq585>i5Z0.K\JJYC&\UB@L!Z_SQW+PYFZDUSJH\ iEMVPZbkq5>5>45Z0.K\JJYC&\UB@L!Z_SQW+PYOIE^TTKK]/T]@H@GU:11^<"GPNN]G*PYNDH%^S_][/T]KEIRXPOOY#XQKOTV1=>S7'@UECRJ!U^KOE*SXZZ^$YRFNLU][B@T(]VNDYY>=9:W3+LYIGVN%YRGCA.W\VVR(]VBJ@YQWFDP,QZBH]];896[?/H]MKZB)]VCGM"[PRRV,QZNFD]USJH\ U^EFJZBBDHSP=P Z_GF01>S7'@UECRJ!U^KOE*SXZZ^$YRFNLU][B@T(]VMNBRJJL@[X6X(RWON956[?/H]MKZB)]VCGM"[PRRV,QZNFD]USJH\ U^PE@WC512_;#DQAO^F-QZOKI&_T^^Z U^JBHQY_NLX$YRZIDSG1`>S7'@UECRJ!U^KOE*SXZZ^$YRFNLU][B@T(l`dT`lzlhdf12>S7'@UECRJ!U^KOE*SXZZ^$YRFNLU][B@T(aJFY>45Z0.K\JJYC&\UB@L!Z_SQW+PYOIE^TTKK]/hFJJ969:01^<"GPNN]G*PYNDH%^S_][/T]KEIRXPOOY#dJFN=3=62=R8&CTBBQK.T]JHD)RW[Y_#XQGAMV\\CCU'`NDYY<j;T2,MZHHWM$^SDBN/T]QWQ)RWAKGXRVIES-j@JSSWmfr0=0=e:W3+LYIGVN%YRGCA.W\VVR(]VBJ@YQWFDP,mAIR\Vngu1<11c9V4*OXFFUO"XQFL@-V[WUS'\U[C_?k;T2,MZHHWM$^SDBN/T]QWQ)RWYXXX=?k;T2,MZHHWM$^SDBN/T]QWQ)RWYXXX<?l;T2,MZHHWM$^SDBN/T]QWQ)RW[Y_<<h4U1-J[KIXL'_TEAO U^PPP*oUMZO_0=0=5:W3+LYIGVN%YRGCA.W\WQGS'HI_^H]JT^rvhvc582_;#DQAO^F-QZOKI&_T_YO[/@AW[ausi}8;7X> I^LL[A(RW@FJ#XQ\T@V,EWKXlz~jx?;4U1-J[KIXL'_TEAO U^QWEQ)DIYUYI^K[_enz54`<]9%BSCAPD/W\MIG(]VY_MY!KISVZ[A66n2_;#DQAO^F-QZOKI&_T_YO[/EKQP\YC9;:0Y=!F_OM\@+SXAEK$YR][AU-GMWR^WZOG>?5Z0.K\JJYC&\UB@L!Z_RVBP*BNZ]STh~znt368Q5)NWGETH#[PIMC,QZUSI]%O_YO[_dl\`i6:=1^<"GPNN]G*PYNDH%^S^ZNT.FPPDRXmgUo`t<=4:W3+LYIGVN%YRGCA.W\WQGS'MY_MYQjn^fo}6463\:$ER@@_E,V[LJF'\UXXLZ DRVBPZjhim827X> I^LL[A(RW@FJ#XQ\T@V,A]RDIYUYILJV_eqweq463\:$ER@@_E,V[LJF'\UXXLZ FTNO[ausi}8m7X> I^LL[A(RW@FJ#XQ\T@V,BZUT\H^P<P F_RVBP+SX[]K_?=5Z0.K\JJYC&\UB@L!Z_RVBP*@X[Z^JXV??]/K\WQGS&\UXXLZ=f:W3+LYIGVN%YRGCA.W\WQGS'OUX_YO[[0_-MZUSI]$^S^ZNT3d8Q5)NWGETH#[PIMC,QZUSI]%MS^][AUY1Y+OX[]K_"XQ\T@V1b>S7'@UECRJ!U^KOE*SX[]K_#KQ\SUCW_6[)AVY_MY Z_RVBP7`<]9%BSCAPD/W\MIG(]VY_MY!I_RQWEQ]3U'CT_YO[.T]PPDR5n2_;#DQAO^F-QZOKI&_T_YO[/G]PWQGSS<W%ER][AU,V[VRF\;l0Y=!F_OM\@+SXAEK$YR][AU-E[VUSI]Q=Q#GPSUCW*PYT\H^9j6[?/H]MKZB)]VCGM"[PSUCW+CYT[]K_W:S!I^QWEQ(RWZ^JX?h4U1-J[KIXL'_TEAO U^QWEQ)AWZY_MYU7]/K\WQGS&\UXXLZ=f:W3+LYIGVN%YRGCA.W\WQGS'OUX_YO[[8_-MZUSI]$^S^ZNT368Q5)NWGETH#[PIMC,QZUSI]%LSC]T0\,V[KUV:=1^<"GPNN]G*PYNDH%^S^ZNT.E\JV]6U'_TB^_=4:W3+LYIGVN%YRGCA.W\WQGS'NUE_V<R.T]MWT433\:$ER@@_E,V[LJF'\UXXLZ G^LP_6[)]VDX]?:4U1-J[KIXL'_TEAO U^QWEQ)@WGYP8P Z_OQR61=R8&CTBBQK.T]JHD)RWZ^JX"IPNRY6Y+SXFZ[986[?/H]MKZB)]VCGM"[PSUCW+BYI[R<V"XQASP07?P6(AVDDSI Z_HNB+PYT\H^$KR@\[6_-QZHTY;>0Y=!F_OM\@+SXAEK$YR][AU-D[KU\0T$^SC]^259V4*OXFFUO"XQFL@-V[VRF\&MTB^U6]/W\JVW512_;#DQAO^F-QZOKI&_T_YO[/Lov|ZBNZ]STh~znt0316>S7'@UECRJ!U^KOE*SX[]K_#C]Pdrvbp969:;1^<"GPNN]G*PYNDH%^S^ZNT.LP[ausi}6:2?<4U1-J[KIXL'_TEAO U^QWEQ)I[Vnxxlz32?01?P6(AVDDSI Z_HNB+PYT\H^$B^Qksucw8685:2_;#DQAO^F-QZOKI&_T_YO[/OQ\`vrf|5>5>?5Z0.K\JJYC&\UB@L!Z_RVBP*HTWmymy2:>308Q5)NWGETH#[PIMC,QZUSI]%E_Rj|t`v?2;453\:$ER@@_E,V[LJF'\UXXLZ NR]gwqgs4>49>6[?/H]MKZB)]VCGM"[PSUCW+KUXlz~jx161239V4*OXFFUO"XQFL@-V[VRF\&DXSi}{au>::4c<]9%BSCAPD/W\MIG(]VY_MY!AS^nlea423\:$ER@@_E,V[LJF'\UXXLZ SUCWAZbt|h~7<3<:;T2,MZHHWM$^SDBN/T]PPDR([]K_IRj|t`v?5;7a3\:$ER@@_E,V[LJF'\UXXLZ TEM\j`~s:=1^<"GPNN]G*PYNDH%^S^ZNT.VQMBABZVnxxlz>c:W3+LYIGVN%YRGCA.W\WQGS'\UJ^@<:;T2,MZHHWM$^SDBN/T]PPDR(]VKYARicud]paq7e3\:$ER@@_E,V[LJF'\UXXLZ U^AQ66=R8&CTBBQK.T]JHD)RWZ^JX"[PDHPW]Z@CKL887X> I^LL[A(RW@FJ#XQ\T@V,QZBNZ]STJI^J239V4*OXFFUO"XQFL@-V[VRF\&_THD\[Y^NGG6g<]9%BSCAPD/W\MIG(]VY_MY!Z_EOV\1)RWJYTAXV I2,V[HS_0&GfyuQ@_21b?P6(AVDDSI Z_HNB+PYT\H^$YRJBUY6,QZETWD_S#D=!U^OV\=)Je|rTCR:>c:W3+LYIGVN%YRGCA.W\WQGS'\UO_A<:;T2,MZHHWM$^SDBN/T]PPDR(]VNX@<!Z_BNFEW433\:$ER@@_E,V[LJF'\UXXLZ U^FPH4)RWME^X?;4U1-J[KIXL'_TEAO U^QWEQ)RWMYG="[PDNWW473<]9%BSCAPD/W\MIG(]VY_MY!Z_EQO5*SXLF__=>?4U1-J[KIXL'_TEAO U^QWEQ)RWMYG="[PGDL\@@JFQR;V"XQID378Q5)NWGETH#[PIMC,QZUSI]%^SI]C1.W\VCBUM;?0Y=!F_OM\@+SXAEK$YR][AU-V[AUK9&_TXKJ]E3;8Q5)NWGETH#[PIMC,QZUSI]%^SI]C1.fjjZjf|jbnh?<4U1-J[KIXL'_TEAO U^QWEQ)RWMYG="gLLS06?P6(AVDDSI Z_HNB+PYT\H^$YRJ\L0-j@LH;878>7X> I^LL[A(RW@FJ#XQ\T@V,QZBTD8%bHD@31?0b?P6(AVDDSI Z_HNB+PYT\H^$YRJ\L0-j@JSSWmfr0=0=a:W3+LYIGVN%YRGCA.W\WQGS'\UO_A? iEMVPZbkq5;5=i5Z0.K\JJYC&\UB@L!Z_RVBP*SXLZF9=i5Z0.K\JJYC&\UB@L!Z_RVBP*SXLZF8=n5Z0.K\JJYC&\UB@L!Z_RVBP*SXLZX:o6[?/H]MKZB)]VCGM"[PSUCW+PYBK[8>7X> I^LL[A(RW@FJ#XQ\T@V,QZCDZVmgyhQ|eu3g?P6(AVDDSI Z_HNB+PYT\H^$YRHZLM05?P6(AVDDSI Z_HNB+PYT\H^$YRHZLM]dhpcX{l~8;6[?/H]MKZB)]VCGM"[PSUCW+PYJ]Q%^SN]PMTZ,M4(RWD_S>"Cbuy]L56><]9%BSCAPD/W\MIG(]VY_MY!Z_LW[+PYD[VG^T"G>.T]NQ]4(EdsSB?>389V4*OXFFUO"XQFL@-V[VRF\&_TAXV U^AP[HS_'@;%YRCZX3-Nip~XG8;;?45Z0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K476;01^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO0317<=R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<?<389V4*OXFFUO"XQFL@-V[VRF\&_TAXV U^AP[HS_'@;%YRCZX3-Nip~XG8;??45Z0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K472;01^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO0357<=R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<?8389V4*OXFFUO"XQFL@-V[VRF\&_TAXV U^AP[HS_'@;%YRCZX3-Nip~XG8;3?45Z0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K47>;11^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO000=>S7'@UECRJ!U^KOE*SX[]K_#XQBUY-V[FUXE\R$E< Z_LW[6*Kj}qUD=?><9:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH9;;8h6[?/H]MKZB)]VCGM"[PSUCW+PYJ]Q%^SN]PMTZ,M4(RWD_S>"Cbuy]L577X[^:856[?/H]MKZB)]VCGM"[PSUCW+PYJ]Q%^SN]PMTZ,M4(RWD_S>"Cbuy]L574412_;#DQAO^F-QZOKI&_T_YO[/T]NQ])RWJYTAXV I0,V[HS_:&GfyuQ@1310<>S7'@UECRJ!U^KOE*SX[]K_#XQBUY-V[FUXE\R$E< Z_LW[6*Kj}qUD=>=7;T2,MZHHWM$^SDBN/T]PPDR(]VG^T"[PCR]NQ])N9'_TAXV=/Lov|ZI6<:20Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N367==R8&CTBBQK.T]JHD)RWZ^JX"[PMTZ,QZETWD_S#D?!U^OV\7)Je|rTC<8<8:W3+LYIGVN%YRGCA.W\WQGS'\UFYU!Z_BQ\IP^(A8$^S@[W2.Onq}YH9>9h7X> I^LL[A(RW@FJ#XQ\T@V,QZKRP&_TO^QBUY-J5+SXE\R9#@czx^M23ZUP8:i0Y=!F_OM\@+SXAEK$YR][AU-V[HS_'\UH_RCZX.K2*PYJ]Q8$A`{w_N34[VQ6;j1^<"GPNN]G*PYNDH%^S^ZNT.W\IP^(]VIXS@[W/H3-QZKRP;%FaxvPO05\WR4402_;#DQAO^F-QZOKI&_T_YO[/T]NQ])RWJYTAXV I0,V[HS_:&GfyuQ@191;?P6(AVDDSI Z_HNB+PYT\H^$YRCZX.W\GVYJ]Q%B=#[PMTZ1+HkrpVE:5<m4U1-J[KIXL'_TEAO U^QWEQ)RWGYG?=5Z0.K\JJYC&\UB@L!Z_RVBP*SXZLYNXRKKGD-J[M4K&\UOCXZ=b:W3+LYIGVN%YRGCA.W\WQGS'\UYI^K[_DFDA*SXLF__<?l4U1-J[KIXL'_TEAO U^QWEQ)RW[OXIYQJDFG,QZBH]];9o6[?/H]MKZB)]VCGM"[PSUCW+PYUMZO_SHJHE.kGKPR;878h7X> I^LL[A(RW@FJ#XQ\T@V,QZTB[L^TIIIJ/hFLQQ:668l0Y=!F_OM\@+SXAEK$YR][AU-V[WOTAGM9<6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^HAI<=;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYMBD^l2b>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@VF44`<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBP@75?2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$OD2>>358Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*EN4;49;6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ CH>0:71<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&IB090=7:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,GL:26;=0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"MF<7<13>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(K@6<2?94U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.AJ8=85?2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$OD26>348Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*B;878=7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!K<0<12>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(L585>;5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/E>0:70<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&N783<9;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-G8085>2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$H181279V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+A:06;<0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"J38?05?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)C4048>6[?/H]MKZB)]VCGM"[PSUCW+PYT\H^TOCZ GZ2^*BhO&\UFYUMV2e9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]7U'_TJI\J2b9V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]7U'_T@XZ=e:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,C^6Z&\USC_MV339V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+B]6U'MeD#[PMTZ@]7b<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP=P Z_GFQA7e<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP=P Z_MWW6`=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'NQ:Q#[PXNP@]64<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&MP>P HnI,V[HS_KP8o7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!H[3_-QZ@CZL8h7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!H[3_-QZJR\;o0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"IT2\,V[]IUKP997X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!H[2_-CkN)]VG^TNW=d:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,C^5Z&\UMH_K=c:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,C^5Z&\UGYY<j;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-D_6[)]VRD^NW<2:W3+LYIGVN%YRGCA.W\WQGS'\UXXLZPCOV,C^2Z&NdC"XQBUYAZ6a=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'NQ?Q#[PFEPF6f=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'NQ?Q#[PLTV1a>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR>V"XQWOSAZ77=R8&CTBBQK.T]JHD)RWZ^JX"[PSUCW[FHS'NQ>Q#IaH/W\IP^DQ;n0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"IT5\,V[CBUM;i0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"IT5\,V[ISS:l1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU:]/W\\JTDQ:80Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"IT6\,DjM(RWD_SOT<k;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-D_3[)]VLO^H<l;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-D_3[)]VF^X?k4U1-J[KIXL'_TEAO U^QWEQ)RWZ^JXRMAT.EX2X(RWQEYOT==;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-D_2[)OgB%YRCZXB[1`>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR=V"XQIDSG1g>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR=V"XQCUU0f?P6(AVDDSI Z_HNB+PYT\H^$YR][AU]@JQ)@S>W%YRV@RB[06>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR(OR2V"J`G.T]NQ]E^:m1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU7]/W\BATB:j1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU7]/W\HPR5m2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV6R.T][KWE^:m1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU6]/W\BATB:j1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#JU6]/W\HPR5m2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$KV7R.T][KWE^:?1^<"GPNN]G*PYNDH%^S^ZNT.W\WQGSWJD_#^2?>348Q5)NWGETH#[PIMC,QZUSI]%^S^ZNT^AMP*U;978=7X> I^LL[A(RW@FJ#XQ\T@V,QZUSI]UHBY!\<3<12>S7'@UECRJ!U^KOE*SX[]K_#XQ\T@V\GKR([595>;5Z0.K\JJYC&\UB@L!Z_RVBP*SX[]K_SN@[/R>7:70<]9%BSCAPD/W\MIG(]VY_MY!Z_RVBPZEI\&Y793<9;T2,MZHHWM$^SDBN/T]PPDR(]VY_MYQLNU-P8385>2_;#DQAO^F-QZOKI&_T_YO[/T]PPDRXKG^$_191279V4*OXFFUO"XQFL@-V[VRF\&_T_YO[_BLW+V:?6;<0Y=!F_OM\@+SXAEK$YR][AU-V[VRF\VIEX"]39?3`?P6(AVDDSI Z_HNB+PYT\H^$YRZKO328Q5)NWGETH#[PIMC,QZUSI]%^SY\FGFGQ6<=R8&CTBBQK.T]JHD)RWZ^JX"[PTSKDC@TXoenS~k{1g9V4*OXFFUO"XQFL@-V[VRF\&cXXLZ30?03?P6(AVDDSI Z_HNB+PYT\H^$e^ZNT=33:4`<]9%BSCAPD/W\MIG(]VY_MY!fSUCW8486n2_;#DQAO^F-QZOKI&_T_YO[/hQWEQ:568l0Y=!F_OM\@+SXAEK$YR][AU-jWQGS4:4:j6[?/H]MKZB)]VCGM"[PSUCW+lUSI]6?2<h4U1-J[KIXL'_TEAO U^QWEQ)n[]K_080>f:W3+LYIGVN%YRGCA.W\WQGS'`Y_MY29>0d8Q5)NWGETH#[PIMC,QZUSI]%b_YO[<6<2b>S7'@UECRJ!U^KOE*SX[]K_#d][AU>;:4`<]9%BSCAPD/W\MIG(]VY_MY!fSUCW8<85:2_;#DQAO^F-QZOKI&_T_YO[/hQWEQEJLVIN>95Z0.K\JJYC&\UB@L!Z_RVBP*oT\H^HAIQLE^l17>S7'@UECRJ!U^KOE*SX[]K_#d][AU]@JQ:76;90Y=!F_OM\@+SXAEK$YR][AU-jWQGSWJD_0<0=3:W3+LYIGVN%YRGCA.W\WQGS'`Y_MYQLNU>1:75<]9%BSCAPD/W\MIG(]VY_MY!fSUCW[FHS4:49?6[?/H]MKZB)]VCGM"[PSUCW+lUSI]UHBY2;>318Q5)NWGETH#[PIMC,QZUSI]%b_YO[_BLW8085;2_;#DQAO^F-QZOKI&_T_YO[/hQWEQYDF]6=2?=4U1-J[KIXL'_TEAO U^QWEQ)n[]K_SN@[<6<17>S7'@UECRJ!U^KOE*SX[]K_#d][AU]@JQ:?6;90Y=!F_OM\@+SXAEK$YR][AU-jWQGSWJD_040=6:W3+LYIGVN%YRGCA.W\PWO@'OUECRZLMB,V[CBU;;1^<"GPNN]G*PYNDH%^SY\FG.W\PF)NWZ^D^LIJ_PWBH+SXKHZTN>:4U1-J[KIXL'_TEAO U^VQMB)RW]I$ER][OSCDAZWRIE$^SNO__ENZ3`=R8&CTBBQK.T]JHD)RW]XBK"[PTB-J[VRHZHMNS\[NL/W\WQIUINOT]XOC/H]PVIRXFLU:"DQAMT]2[QIX<'_TXNB I^LNQZCV9'_TeIAZT.K\]@UK]]<%YR]]LB35A3><]9%BSCAPD/W\MIG(]V^YEJ!Z_UA,MZUSG[KLIR_ZAM,V[VRHZHMNS\[NL.K\WWJSWGOT=#GPNLW\5ZRHW=$^SYMC/H]LQQTBO'_THB[[5d9V4*OXFFUO"XQFL@-V[QTNO&_TXN!F_RVLVDABWX_J@#[PSUMQEBCXY\KG#DQ\RMV\J@Y6&@UEAXQ>_UM\0+SX\JF$eIAZT4c8Q5)NWGETH#[PIMC,QZRUAN%^SYM I^QWKWG@MV[^MA Z_RVLVDABWX_J@"GPSSNW[KCX9'CTB@[P1^VL[1(RW]XBK\:=;T2,MZHHWM$^SDBN/T]WVLA(]V^H#DQ\TNPBC@YV]HF%YR][OSCDAZWRIE%bX_GHGDP4e>S7'@UECRJ!U^KOE*SX\[CL#XQ[C.K\PVCVWGOZ>#[PTB]FUPGSAFD$ER]]LU]MAZ7)AVDFYR?PTN]7*PYSKE%BSCCZ_DS2*PYnLF__#DQVERNVP3(RWZXGO<8J659V4*OXFFUO"XQFL@-V[QTNO&_TXN!F_UQFUZHBY;$^SYMPEPWBPLII'@UX^AZPND]2*LYIE\U:SYAP4/W\PFJ(AVE^X_KH.T]GKPR2i2_;#DQAO^F-QZOKI&_TX_GH/T]WG*OX\ZOZSCK^2/W\PFYBY\K_EB@ I^QQHQYIMV;%ER@BU^3\PJY3&\U_OA!fDNWW13=R8&CTBBQK.T]JHD)RW]XBK"[PTB-J[QUBYVDN]? Z_UA\ATSF\@EE#DQ\RMV\J@Y6&@UEAXQ>_UM\0+SX\[CL]>k4U1-J[KIXL'_TEAO U^VQMB)RW]I$ERZ\EP]MAT4)]V^HSH_ZAUKLJ*oSZ@MLI_<;;T2,MZHHWM$^SDBN/T]WVLA(]V^H#dMNPUWQA7><]9%BSCAPD/W\MIG(]V^YEJ!Z_UA,mF@@WMK_M1>13b9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$ERCL_OM-QZHHWDIT^HI<6:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ DNWW[qkwij1^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^9R:V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S8:V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S8;V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S88V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S89V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S8>V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S8?V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S8<V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S8=V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S82V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fl2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S83V"DQFN^PBJBC)AV_XIRGAPTV\V@AXFL:%YRINNE]GH\7fk2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_6S8W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\:9W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\:8W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\:;W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\::W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\:=W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\:<W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\:?W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\:>W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\:1W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gc3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\:0W%ERGA_SCMC@(NW\YNSD@_UU]QABYIM9$^SJOAD^FO]4gd3\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$KRINNE]GH\7\:T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]48T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]49T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]4:T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]4;T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]4<T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5db<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]4=T$BSD@PR@LDA+OX]ZOTEC^ZT^PFCZHB8'_TKL@K_ENZ5de<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]4]4U'CTECQ]AOEF*LYR[LUBB][[_SGD[KC7&\ULMCJPDM[2ef=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ5^2Z&@UBBR\NNFG-MZSTMVCE\XZPRDE\J@6)]VMJBIQKLX3bg>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[2_0[)AVCES_OAGD,J[PUBW@D[YYQ]EF]MA5(RWNKEHRJCY0c`?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX3X2X(NW@DT^L@HE/K\QVCXAGZ^XR\JG^LF4+SXOHDOSIBV1`a8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY0Y4Y+OXAGUYMCIJ.H]VW@YNFY__S_KH_OG3*PY@IGNTHAW>ab9V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV1Z:^*LYNFVXJBJK!I^WPAZOIX\^T^HIPND2-QZAFFMUO@T?nc:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW>[8_-MZOIW[KEKH F_TQF[LHW]]UYIJQAE1,V[BGILVNGU<77;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T0\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q:<P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]69T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y26X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U>3\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q:8P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]6=T$BSD@PR@LDA+SXOHDOSIBV28;8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y22X(NW@DT^L@HE/W\CDHCWMFR>474U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U>7\,J[LHXZHDLI#[PG@LG[AJ^:030Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q:4P F_HL\VDH@M'_TKL@K_ENZ6<?<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%LSJOAD^FO]7]61T$BSD@PR@LDA+SXOHDOSIBV28:8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)@WNKEHRJCY3Y2Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V<?]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R8:Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^45U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z00Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V<;]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R8>Q#GPIO]QEKAB&\ULMCJPDM[1=<=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^41U'CTECQ]AOEF*PY@IGNTHAW=989V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*AXOHDOSIBV2Z04Y+OXAGUYMCIJ.T]DEKBXLES9545Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.E\CDHCWMFR>V<7]/K\MKYUIGMN"XQHAOF\@I_5101^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R82Q#GPIO]QEKAB&\ULMCJPDM[1===R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&MTKL@K_ENZ6^4Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[22^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W>?R.H]JJZTFFNO%YRINNE]GH\4>12_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S:8V"DQFN^PBJBC)]VMJBIQKLX0:=>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_65Z&@UBBR\NNFG-QZAFFMUO@T<69:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+BY@IGNTHAW=[26^*LYNFVXJBJK!U^EBJAYCDP8256[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/F]DEKBXLES9W>;R.H]JJZTFFNO%YRINNE]GH\4>02_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#JQHAOF\@I_5S:W%ERGA_SCMC@(RWNKEHRJCY3;;?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(OVMJBIQKLX0X0X(NW@DT^L@HE/W\CDHCWMFR>464U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-D[BGILVNGU?U:]/K\MKYUIGMN"XQHAOF\@I_5111^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"IPG@LG[AJ^:R<V"DQFN^PBJBC)]VMJBIQKLX0:<>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'NULMCJPDM[1_2[)AVCES_OAGD,V[BGILVNGU?77;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,CZAFFMUO@T<T8\,J[LHXZHDLI#[PG@LG[AJ^:020Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!H_FCM@ZBKQ;Q2Q#GPIO]QEKAB&\ULMCJPDM[1e5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&_TO^QHAOF\WWJX^?%BSX]J_SRN[KC7&\ULMCJPSSN\W@R0n2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:761:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i648:54=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7=<070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2>2?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=30:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28429091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;9<43<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq86::36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1?8>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><0:=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?5<80n2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:661:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64;:54=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7><070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2=2?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=00:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28729091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;:<43<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq869:36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr=1<8>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><3:=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx3?6<80n2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:561:0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i64::54=5Z0.K\JJYC&\UB@L!Z_UPJC*SX\D%LSCCZ[1_-QZK(]VG^#DQBUU]DEKB_&\Ufmymg/H]@WZAFFMR%YRM\_FCM@]YTZE%BS[8!U^AP[BGILQUX^AQY6.ebjaYcdp;7?<070:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2<2?:3?P6(AVDDSI Z_HNB+PYSZ@M$YRZB/F]MIP]7U'_TA"[PMT-J[HSSWNKEHU Z_lcwgm)NWJYTKL@KX/W\GVY@IGNSS^\C/H]U2+SXKZULMCJW_RPO[S0(ohdoSibv1=10:=6<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28629091^<"GPNN]G*PYNDH%^SY\FG.W\PH)@WGG^W=S!U^O,QZKR'@UFYYQHAOF[*PYji}ic#DQLS^EBJA^)]VIXSJOADY]PVI)NW_<%YRM\_FCM@]YTZEU]:"inne]gh|7;;<4<j6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq8682:h4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles:0908f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu<2:>6d8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw><7<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy0>4:2`<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{28=80n2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}4:>6>l0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i54943<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;6:<36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1?>>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<00=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?568?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:6<72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:5;>25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90<81819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<316<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>2<;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz697>6>l0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i54843<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;69<36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1<>>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<30=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?668?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:5<72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:58>25>4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90?81819V4*OXFFUO"XQFL@-V[QTNO&_TX@!H_OOV_5[)]VG$YRCZ/H]NQQY@IGNS"XQbauak+LYD[VMJBIV!U^AP[BGILQUX^A!F_W4-QZETWNKEHUQ\RM]U2*affmUo`t<326<;4>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>1<;>73\:$ER@@_E,V[LJF'\U_^DI U^VN+BYIE\Q;Q#[PM.W\IP)NWD__SJOADY,V[hgska%BSN]PG@LG\+SXKZULMCJW_RPO+LYQ>'_TO^QHAOF[[VTKW_<$kl`k_enz694>6>l0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i54;43<6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERCZT^EBJA^)]Vgjxnf I^AP[BGILQ$^SN]PG@LG\ZUUD&CTZ; Z_BQ\CDHCPVYY@RX9/fcm`Zbkq;68<36?;T2,MZHHWM$^SDBN/T]WVLA(]V^F#JQAMTY3Y+SXE&_TAX!F_LWW[BGILQ$^S`o{ci-J[FUXOHDOT#[PCR]DEKB_WZXG#DQY6/W\GVY@IGNSS^\C_W4,cdhcWmfr>1=>>928Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<20=<5=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC U^OV+LYJ]]ULMCJW.T]neqeo'@UH_RINNEZ-QZETWNKEHUQ\RM-J[S0)]VIXSJOADY]PVIYQ>&mjbiQklx0?768?82_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:4<72;7X> I^LL[A(RW@FJ#XQ[RHE,QZRJ'NUEAXU?]/W\I*SXE\%BS@[[_FCM@](RWdkoe!F_BQ\CDHCP'_TO^QHAOF[[VTK'@U]:#[PCR]DEKB_WZXGS[8 g`lg[aj~:59>2:h4U1-J[KIXL'_TEAO U^VQMB)RW]G$KR@BUZ2^*PYJ'\UFY"GPMTV\CDHCP'_Talzlh.K\GVY@IGNS"XQLS^EBJA^X[[F$ERX9.T]@WZAFFMRT__BPV7-dekbXles90>08f:W3+LYIGVN%YRGCA.W\PWO@'\U_A"IPNLWX4X(RWD%^S@[ I^OVPZAFFMR%YRcntbj,MZETWNKEHU Z_BQ\CDHCPVYY@"GPV7,V[FUXOHDOTR]]L^T5+bgilVngu?2;>6d8Q5)NWGETH#[PIMC,QZRUAN%^SYC G^LNQ^6Z&\UF#XQBU.K\IPRXOHDOT#[Pm`v`l*OXKZULMCJW.T]@WZAFFMRT__B I^T5*PYD[VMJBIVPSSN\R3)`ignThaw=<4<4b>S7'@UECRJ!U^KOE*SX\[CL#XQ[M.E\JHS\8T$^S@!Z_LW,MZKR\VMJBIV!U^obpfn(AVIXSJOADY,V[FUXOHDOTR]]L.K\R3(RWJYTKL@KX^QQHZP1'nkehRjcy3>5:2`<]9%BSCAPD/W\MIG(]V^YEJ!Z_UO,CZHJ]R:V"XQB/T]NQ*OXE\^TKL@KX/W\idrd`&CTO^QHAOF[*PYD[VMJBIVPSSN,MZP1&\UH_RINNEZ\WWJX^?%lmcjPdm{18280n2_;#DQAO^F-QZOKI&_TX_GH/T]WI*AXFD_P<P Z_L-V[HS(AVG^XRINNEZ-QZkf|jb$ERM\_FCM@](RWJYTKL@KX^QQH*OX^?$^SN]PG@LG\ZUUDV\=#joad^fo}7:?6>l0Y=!F_OM\@+SXAEK$YRZ]IF-V[QK(OVDFYV>R.T]N+PYJ]&CTAXZPG@LG\+SXeh~hd"GPCR]DEKB_&\UH_RINNEZ\WWJ(AV\="XQLS^EBJA^X[[FTZ;!haof\`i5404?:6[?/H]MKZB)]VCGM"[PTSKD+PYSE&MTB@[T0\,V[H)RWD_$ERA]EF,J[\CTWFXNK#[POSGD74=R8&CTBBQK.T]JHD)RW]XBK"[PTL-D[KKRS9W%YRC dnww[qkw:81^<"GPNN]G*PYNDH%^SY\FG.vqmbEhfmCe>?5Z0.K\JJYC&\UB@L!Z_UPJC*ruanIdbiAzt068Q5)NWGETH#[PIMC,mDTJ911^<"GPNN]G*PYNDH%bOL^[USG2=>S7'@UECRJ!U^KOE*oDIYUOCCK=3:W3+LYIGVN%YRGCA.k@EUYI]DUXM@^CER>3:75<]9%BSCAPD/W\MIG(aJK[SC[B_RCNTICT4849?6[?/H]MKZB)]VCGM"gLAQ]MQHYTIDZGI^2=>318Q5)NWGETH#[PIMC,mFGWWG_FS^OBPMGP8685;2_;#DQAO^F-QZOKI&cHM]QAUL]PEHVKMZ6?2?=4U1-J[KIXL'_TEAO iBCS[KSJWZKF\AK\<4<17>S7'@UECRJ!U^KOE*oDIYUEY@Q\ALROAV:16;90Y=!F_OM\@+SXAEK$eNO__OWN[VGJXEOX0:0=3:W3+LYIGVN%YRGCA.k@EUYI]DUXM@^CER>;:75<]9%BSCAPD/W\MIG(aJK[SC[B_RCNTICT404:h6[?/H]MKZB)]VCGM"gLAQ]PPDRB494:h6[?/H]MKZB)]VCGM"gLAQ]PPDRB4849<6[?/H]MKZB)]VCGM"gLAQ]WVLA@M[UDYY?i;T2,MZHHWM$^SDBN/hABTZQUWHNO^1>11g9V4*OXFFUO"XQFL@-jGDVX_[UJHI\31?3e?P6(AVDDSI Z_HNB+lEFXV]YSLJKR=0=5c=R8&CTBBQK.T]JHD)nKHZT[_QNDEP?7;7a3\:$ER@@_E,V[LJF'`IJ\RY]_@FGV9299o1^<"GPNN]G*PYNDH%bOL^PWS]B@AT;=7;m7X> I^LL[A(RW@FJ#dMNP^UQ[DBCZ5<5=k5Z0.K\JJYC&\UB@L!fC@R\SWYFLMX7;3?i;T2,MZHHWM$^SDBN/hABTZQUWHNO^1611g9V4*OXFFUO"XQFL@-jGDVX_[UJHI\39?3b?P6(AVDDSI Z_HNB+lEFXV]YSH@>8:W3+LYIGVN%YRGCA.kGEQG;87;27X> I^LL[A(RW@FJ#dJNT@>24;7>3\:$ER@@_E,V[LJF'`NJXL2>1?3:?P6(AVDDSI Z_HNB+lBF\H6:>3?6;T2,MZHHWM$^SDBN/hFBPD:6;7;27X> I^LL[A(RW@FJ#dJNT@>20;7>3\:$ER@@_E,V[LJF'`NJXL2>5?3:?P6(AVDDSI Z_HNB+lBF\H6::3?6;T2,MZHHWM$^SDBN/hFBPD:6?7;27X> I^LL[A(RW@FJ#dJNT@>2<;7>3\:$ER@@_E,V[LJF'`NJXL2>9?3;?P6(AVDDSI Z_HNB+lBF\H6:2<74U1-J[KIXL'_TEAO iECWE9476830Y=!F_OM\@+SXAEK$eIO[A=02:4?<]9%BSCAPD/W\MIG(aMK_M1<=>0;8Q5)NWGETH#[PIMC,mAGSI5882<74U1-J[KIXL'_TEAO iECWE9436830Y=!F_OM\@+SXAEK$eIO[A=06:4?<]9%BSCAPD/W\MIG(aMK_M1<9>0;8Q5)NWGETH#[PIMC,mAGSI58<2<74U1-J[KIXL'_TEAO iECWE94?6830Y=!F_OM\@+SXAEK$eIO[A=0::4><]9%BSCAPD/W\MIG(aMK_M1<1189V4*OXFFUO"XQFL@-j@DRF4::5=45Z0.K\JJYC&\UB@L!fD@VB8679901^<"GPNN]G*PYNDH%bHLZN<20=5<=R8&CTBBQK.T]JHD)nLH^J0>=1189V4*OXFFUO"XQFL@-j@DRF4:>5=45Z0.K\JJYC&\UB@L!fD@VB8639911^<"GPNN]G*PYNDH%bHLZN<2<2<>S7'@UECRJ!U^KOE*oCI]K783?7;T2,MZHHWM$^SDBN/hFBPD:26820Y=!F_OM\@+SXAEK$eIO[A=4=5==R8&CTBBQK.T]JHD)nLH^J0:0>8:W3+LYIGVN%YRGCA.kGEQG;07;37X> I^LL[A(RW@FJ#dJNT@>::4g<]9%BSCAPD/W\MIG(aMK_MRJ@UU3:?P6(AVDDSI Z_HNB+lTB[L^7<3?6;T2,MZHHWM$^SDBN/hPFW@R;97;27X> I^LL[A(RW@FJ#d\JSDV?6;7>3\:$ER@@_E,V[LJF'`XN_HZ33?3:?P6(AVDDSI Z_HNB+lTB[L^783?6;T2,MZHHWM$^SDBN/hPFW@R;=7;27X> I^LL[A(RW@FJ#d\JSDV?2;7>3\:$ER@@_E,V[LJF'`XN_HZ37?3b?P6(AVDDSI Z_HNB+lUSI]UOCXZ>8:W3+LYIGVN%YRGCA.kWVLA@M[;>7X> I^VR4+AX\^Q;Q#[PTP35?P6(AV^Z<#IPTVY24X(RW][::6[?/H]WU5(@W]]P=<S!U^VR53=R8&CTX\>!G^VT_44Z&\U_]<84U1-J[QW7&NU_[V?<]/W\PT713\:$ERZ^0/E\PR]6<T$^SY_>6:W3+LYSY9$LSYYT14_-QZRV9?1^<"GPTP2-CZRPS8<V"XQ[Q048Q5)NW][;"JQ[WZ34Y+SX\X;=7X> I^VR4+AX\^Q:4P Z_US22>S7'@U_]= H_UUX5<[)]V^Z=85Z0.K\PT6)OV^\W<S!U^VR53=R8&CTX\>!G^VT_76Z&\U_]<84U1-J[QW7&NU_[V<>]/W\PT713\:$ERZ^0/E\PR]5:T$^SY_>6:W3+LYSY9$LSYYT22_-QZRV9?1^<"GPTP2-CZRPS;>V"XQ[Q048Q5)NW][;"JQ[WZ06Y+SX\X;=7X> I^VR4+AX\^Q9:P Z_US22>S7'@U_]= H_UUX62[)]V^Z=;5Z0.K\PT6)OV^\W?6R.T]WU40<]9%BSY_?.F]WS^4>U'_TX\?:;T2,MZRV8'MTXZU=]/W\PT713\:$ERZ^0/E\PR]48T$^SY_>6:W3+LYSY9$LSYYT30_-QZRV9?1^<"GPTP2-CZRPS:8V"XQ[Q048Q5)NW][;"JQ[WZ10Y+SX\X;=7X> I^VR4+AX\^Q88P Z_US22>S7'@U_]= H_UUX70[)]V^Z=85Z0.K\PT6)OV^\W>S!U^VR50=R8&CTX\>!G^VT_1[)]V^Z=85Z0.K\PT6)OV^\W8S!U^VR50=R8&CTX\>!G^VT_3[)]V^Z=85Z0.K\PT6)OV^\W:S!U^VR50=R8&CTX\>!G^VT_=[)]V^Z=85Z0.K\PT6)OV^\W4S!U^VRa>S7'`^YEJQFN=2=b>S7'`^YEJQFN=33:c=R8&c_^DIPIO>25;`<]9%bX_GH_HL?578a3\:$eY\FG^KM8459n2_;#dZ]IF]JJ9736o1^<"g[RHE\MK:6=7l0Y=!fTSKD[LH;9?4m7X> iUPJCZOI48=5j6[?/hVQMBYNF5;32k5Z0.kWVLAXAG6:53k4U1-jPWO@W@D7=3h4U1-jPWO@W@D7>=0i;T2,mQTNOVCE0??1f:W3+lRUANUBB1<=>g9V4*oSZ@MTEC2=3?d8Q5)n\[CLSD@325<e?P6(a]XBKRGA<37=b>S7'`^YEJQFN=05:c=R8&c_^DIPIO>13;`<]9%bX_GH_HL?6=8a3\:$eY\FG^KM87?9m2_;#dZ]IF]JJ949n2_;#dZ]IF]JJ9576o1^<"g[RHE\MK:497l0Y=!fTSKD[LH;;;4m7X> iUPJCZOI4:95j6[?/hVQMBYNF59?2k5Z0.kWVLAXAG6893k4U1-jPWO@W@D7?3k4U1-jPWO@W@D783k4U1-jPWO@W@D793k4U1-jPWO@W@D7:3k4U1-jPWO@W@D7;3k4U1-jPWO@W@D743k4U1-jPWO@W@D753m4URGQ[SOTAKFN46[\E^POKF0<]VG^TL84U^OV\G0<]VG^TN84U^OV\A053\UYM@!F_W4-QZETWKXJARMNSBCGAZP1'@UOI]ZG_MVFUZ55C'_T_O\NM^2,MZD4>BM_<#IPR@OA73]7U'T~lcm37-V[WGJJ:<=7XQ\RMC5?PYTZEH=7XQ\RMA5?PYTZEN87[ML9:TJARYSQYOh7ZO]NHLD[JHKQ?1\IL2?>79TAD:66?1\IL2=>99TAD:4294=7ZKN<2<5?RCE494=7ZKM<0<5?RCE4;437ZKM<283:3=PMK68255XECUF858?3^OI[H2>>99TAGQB4;437ZKMWD>0:==PMK]N0907;VGAS@:2611\IOYJ<7<b?RCE_L6<6=07;VGAS@:06k1\^DZJ_GKQWQe<_[C_IRC@DD]Bg>QUA]OTABJJ_Cf8SWOSMV]BHYFPAe9TVLRBW^COXEQM4:Z3]52<P9S:86V?Y368\5_4<2R;U9:4X1[65a=_AECET VKB!2-5%US]K*;"<.NSBKJ1>^HZJS=7U][LH@4?]USWNDO;6V\T^T@Gg=_WJEYIRGAFN48\adXAml0TifPPsknR`ttafd:<6Vkm^ObnjtQm{ybcc??;Yfn[Hoig{\n~~g`n29[wq5<Qly8h6QP_YNMIZYX8VUTY=!F_OM\@+SXAEK$YR][AU-E[VUSI]Q9Q#GPSUCW*PYT\H^9j6QP_YNMIZYX99UTSX> I^LL[A(RW@FJ#XQ\T@V,QZUSI]IFH?m4_^][HKKXWV;:SRQZ0.K\JJYC&\UB@L!Z_SQW+PYWZZ^;?95P_^ZOJHYXW88TSR[?/H]MKZB)]VCGM"[PSUCW+PYFZDUl`xkPsdv0`>YXWQFEARQP1^]\Q5)NWGETH#[PIMC,QZUSI]%MS^][AUY4Y+OX[]K_"XQ\T@V0a>YXWQFEARQP2^]\Q5)NWGETH#[PIMC,QZUSI]%MS^][AUY24X(NWZ^JX#[PSUCW7a=XWVRGB@QP_2]\[P6(AVDDSI Z_HNB+PYT\H^$JR]\T@VX1X(NWZ^JX#[PSUCW22=XWVRGB@QP_5]\[P6(AVDDSI Z_HNB+PYDIYY_C_!F_BCPA4(NWPOXSYL!U^VQEFCXJ\LMI_!F_LWOPZTH_'_TC_Q]SU]Q@ZTH_V]BHH:n;^]\\IHJWVU>SRQZ0.K\JJYC&\UB@L!Z_RVBP*SXE\R$YRM\_LW[+L7)]VG^T?!Bmtz\K41X[^:9m6QP_YNMIZYX>VUTY=!F_OM\@+SXAEK$YR][AU-V[KUK<?1TSRVCNL]\[2YXW\:$ER@@_E,V[LJF'\UXXLZ U^OV\*SXKZUFYU!F1/W\IP^5'Dg~tRA>1738[ZY_DGGTSR6P_^W3+LYIGVN%YRGCA.W\GDVT\FX$ERMNSD3-MZ_B[V^I"XQ[R@AF[GSANLX$ERCZLU]QKR(RWFXT^IQ]OV]FJ12<WVUS@CCP_^;\[ZS7'@UECRJ!U^KOE*SXO;UX]#[PC@R@PWJ(]VIJ\ROKDSEFJ*SXJ[A;n6o|yoa\ip~X9k1jt`l_lw{[7d<izseoRczx^124>gtqgiTxoasggq[4773hyrbnQ{r`lpb`tX:8:0m~wac^vqekuam{U8h6mgiqq`kucXaek8=6mgiqq`kucXaekTz<Q?5^c/$]okagr+OB\J Fgmawgsg{*:?#=6;bmvjqcuW830ob{atdp\6<=dg|diQ<9:alqkrbzV>m7n}Pbscn[fgtkhnn=?5ls^`qehYdizijhhQy6038gvYezhgTdcld]u24><kzUi~lcPshosh`Yq>Vxjao?7199`wZduidUxe`~ce^t5[wgjj:<j7n}Pcgeoqq2f3jyTokicuu7`?fuXkomgyy8P1b9`wZeaoe:R<n;bq\gcak}}=:n6m|_bmmpwikj|yTt~zxosibvjsil8;0o~QlotlwawYjgmaT=<?4cr]`kphsm{UfcieP2c9`wZaffmUx~a??;bq\cdhcWzxgS{8P1028gvY`ignTbPv7]15==d{VmjbiQ|rm]u2ZtweVynxR?>8:ap[bgilVyy`Rx9_srn[vcsW;;=7n}Pg`lg[vtkW<Tagle^322>etWnkehR}}l^t5[vjnklU9=;5ls^ebjaYtzeU}:R}cibg\740<kzUlmcjPssn\r3Ytd`inS9?9;bq\cdhcWzxgS{8Psmk`aZ36>2ixSjoad^qqhZp1WzfbohQ9c:ap[bgilqUx~ah4cr]dekbWzxgS{88;bq\hpr2?2ixSa{{669`wZkrp;20o~Qbuy11<>etWds:994cr]nq}>?3jyTaxvP199`wZkrpV837n}Pmtz\7==d{Vg~tR:m;bq\v`an{}oy?6jkme9f`bcXll~noya}d:ebjaYdi{xr0=0k;fcm`Zefz{s7=3j4g`lg[fguzp692i5haof\gdtuq595h6inne]`ewt~4=4>7dbn3706?ljf;?&hdd~|cnrf[ljfW;T<8Qn,OMMA)HHFL;9;=5fl`15(fnnxzid|hQfl`]u5Z62Wh&poRvlo^njwq;Dgdzdbh`{_Ocna8oki:<0Bxcmes]LbZRuanmn~R^`ruq>5>KfpVYn}xkacd]Oasck{4;0Y~kPRQOp9qtrm2Oemobj_UpjcbcuWF|xzPPnpw9cgk{l1Xm`~ce^Mm9Wotagm0_lcld]GeqgXLlzd0??259FjddkmVYcohe^Sveioaajkeb`2tswf?AgsiVYjahQNs^Vqmbabz4~yyh5Kauc\TjtsW^coxe3?;UpjcbcuWYeyxRYfduj\58513DkoeQZnhvp[4;63Je~byk}_VkgpmY65Mcxmobjd:ObpfnX\pznS<3mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV;6jlb|e:VqmbabzVZd~yQXievk[7;?3DkoeQZnhvp[7;63Je~byk}_VkgpmY55Mcxmobjd:ObpfnX\pznS?3mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV86jlb|e:VqmbabzVZd~yQXievk[6;?3DkoeQZnhvp[6;63Je~byk}_VkgpmY45Mcxmobjd:ObpfnX\pznS>3mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV96jlb|e:VqmbabzVZd~yQXievk[1;?3DkoeQZnhvp[1;63Je~byk}_VkgpmY35Mcxmobjd:ObpfnX\pznS93mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV>6jlb|e:VqmbabzVZd~yQXievk[0;?3DkoeQZnhvp[0;63Je~byk}_VkgpmY25Mcxmobjd:ObpfnX\pznS83mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV?6jlb|e:VqmbabzVZd~yQXievk[3;?3DkoeQZnhvp[3;63Je~byk}_VkgpmY15Mcxmobjd:ObpfnX\pznS;3mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV<6jlb|e:VqmbabzVZd~yQXievk[2;?3DkoeQZnhvp[2;63Je~byk}_VkgpmY05Mcxmobjd:ObpfnX\pznS:3mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV=6jlb|e:VqmbabzVZd~yQXievk[=;?3DkoeQZnhvp[=;63Je~byk}_VkgpmY?5Mcxmobjd:ObpfnX\pznS53mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV26jlb|e:VqmbabzVZd~yQXievk[<;?3DkoeQZnhvp[<;63Je~byk}_VkgpmY>5Mcxmobjd:ObpfnX\pznS43mark`[ros`Vookh}4EyaoqacXN{efSIo{a^Qwkwg`mV36jlb|e:VqmbabzVZd~yQXievk[46:02GjxnfPUokwwZ77581Hcx`{es]TmaroW8:6Hd}nbmgg?HgskaU_u}kP11?aevodW~cdRkkgdq8A}ek}moTJab_EcweZUsg{kliR??=gcow`=Sz`mliQ_osv\Slbs`V;:155Bauak[Phn|zU:=0?4Cnwmp`tX_`ndR?>=Ekpegjbl2GjxnfPTxrf[47:jhyboRyfti]f`bct3Lrh`xjj_GpliZBf|hUXxb|ngd]258`fdzo0Xghgdp\TjtsW^coxeQ>2<:8Idrd`V_eey}P13?2?Firf}oySZgkti]268Bn{hhgii5Bauak[QwmV;91oo|ib]tmqnXmmmn6KwcmwgaZ@ugdUOmyoPSumqebcX9;7mma}j;UpjcbcuWYeyxRYfduj\56;?3DkoeQZnhvp[45:92Idyczjr^Uj`qnX9:7Oe~omldf8Idrd`V^r|hQ>3<`bwleX`~cShjher9F|fjrllUM~bcPD`vb[VrhzhmnS<=2f`npa>Ruanmn~R^`ru]TmaroW8>646Cntbj\Qkos{V;?1<5LotlwawYPam~cS<:2Dhqbficc3DkoeQ[yqg\51;eizchSzg{h^ggc`u<MqigyikPFsmn[AgsiVYcohe^379cgk{l1_~dihes]SkwrX_`ndR?:=99NeqeoW\dbx~Q>5<38Gjsi|lxT[dj{h^369Aotikfnh6Cntbj\P|vbW8?6nl}fc^ujpmYblnox7Hvlltff[CtheVNjxlQ\tnpbc`Y6=4lj`~k4Tskdc`tXXfxSZgkti]228><Eh~hdR[aiuq\53;63Je~byk}_VkgpmY6>4Nbllcee9NeqeoW]s{iR?9=ccpmfYpa}bTiiijs:G{giscmVLyc`QKauc\WqiuinoT=;3iamqf(fYll|bohhnmhnz9sou|lr= nQlosg\p|vb5;&hS`hh_hf>5)eXeh`d~Rxjrrklj874$jUfeca}_wgqwlii5:&hSo{fle]qasotafd6<!mPcnpf[hgmg{U}i3>,b]`kwcXe`dd~Rxjr<6/gZehzlUfeca}_`nsldYqm{72;!mPr`o\p|vb58&hS~|c17]w}uc::%iTy~kPiot\gim:8%iTy~kPrqo>5)eX}zoTxgh_nww95*dW|ynSlzl_bnhmk;7$jU~hQkauc>4)eX}zoTxgh0<3/gZstmV~yej?20-a\qvcX|{cl>0>#c^wpaZruan96<!mPurg\pwo`<4:'oR{|e^vqmb3:8%iTy~kPtskd286+kVxiRz}if5>4)eX}zoTxgh8<2/gZstmV~yej720-a\qvcX|{cl==3?,b]vw`Ysz`m:=0>#c^wpaZruan;91="l_tqf[qtno896<!mPurg\pwo`9=7; nQzsd]wvla6=4:'oR{|e^vqmbbf|h:6=!mPurg\pwo`lh~j=0>#c^wpaZruannjxl<20-a\qvcX|{clhlzn3<2/gZstmV~yejjnt`6>4)eX}zoTxghd`vb186+kVxiRz}iffbpd0:8%iTy~kPtskd`drf?4:'oR{|e^vqmbbf|h26<!mPurg\pwo`lh~j50>#c^wpaZruannjxl??=1.`[pubW}xbkio{a03>4)eX}zoTxghd`vb57;7$jU~hQ{rhegeqg6;4:'oR{|e^vqmbbf|h;?1="l_tqf[qtnomkm<;20-a\`drfW~coxe3>,b]geqgXllzd0??25.`[pubWnk{1="l_uknavrfeyUu}k20-a\plkb{}kf|Ryfduj>77*dW}cfi~znmq]gauro5<;9 nQzsd]ppjtfolUzylb21-a\pvcvW}s{i0>#c^lviZrtmxUhby3?,b]ww`wXkg~:Szgkti?2(fYs{l{Tocz?_vkgpm;6$jUey`Q{sds\wqgsmz7: nQzsd]wgZkdf}7; nQ{c^o`jqYpam~c1<"l_dzw[fgwW{kiRc`dd?3(fYbp}Uhm}Qio]nkac:8%iTbxcPeyv\gdvXx`dx15"l_dzw[fgwW|ynSkh=0.`[ksjWdkoeQznhvp94*dW}xbk=Qxievk960+kV~yej?Pwhfwl87+kV~yej<Pwhfwl87+kV~yej=Pwhfwl87+kV~yej:Pwhfwl87+kV~yej;Pwhfwl87+kV~yej8Pwhfwl87+kV~yej9Pwhfwl87+kV~yej6Pwhfwl87+kV~yej7Pwhfwl87+kV~yej??_vkgpm;6$jU~di>1^uj`qn:9%iTxgh13]tmaro58&hSy|fg01\slbs`4;'oRz}if37[roc|a7: nQ{rhe21Zqnl}b6=!mPm1]wtlb:8%iTa<Q{phf>5)eXe;U|dj22-a\i6Ysx`n6?!mPm5]wtlb:<%iTa8Q{phf>1)eXe?U|dj26-a\i2Ysx`n6;!mPm9]wtlb:0%iTa4Q{phf>=)eXe8:Tx}gk=02/gZk69V~{ei3>1-a\i44X|yco1<<#c^o27Zrwam7:?!mPm06\puoc58>'oRc>5^vsma;6=%iTa=Q{yqg>5)eXe8Uu}k20-a\i7Ysqyo6<!mPm2]w}uc:8%iTa9Q{yqg>4)eXe<Uu}k20-a\i3Ysqyo6<!mPm6]w}uc:8%iTa5Q{yqg>4)eXe0Uu}k20-a\i46X|pzn1="l_l32[qwm4:'oRc>2^vzt`;7$jUf=>Q{yqg>4)eXe8>Txt~j=1.`[h72W}s{i0>#c^wpaZkdf}:6<!mPurg\ifhs94:'oR{|e^o`jq4:8%iTy~kPmblw786+kVxiRclnu6>4)eX}zoTan`{5<2/gZstmVghby820-a\qvcXejd;0>#c^wpaZkdf}26<!mPurg\ifhs14:'oR{|e^o`jq7759&hSx}j_lamp47:8%iTy~kPmblw57;7$jU~hQbcov2786+kVxiRclnu3795*dW|ynS`mat07>4)eXejd<Ryfduj>5)eXejd=Ryfduj>5)eXejd>Ryfduj>5)eXejd?Ryfduj>5)eXejd8Ryfduj>5)eXejd9Ryfduj>5)eXejd:Ryfduj>5)eXejd;Ryfduj>5)eXejd4Ryfduj>5)eXejd5Ryfduj>5)eXejd==Qxievk94*dWdiex<?Pwhfwl87+kVghby?=_vkgpm;6$jUfocz>3^uj`qn:9%iTan`{15]tmaro58&hS`mat07\slbs`4;'oRm`nrvqelhsW}s{i0kbbdfgaa*dWlrja}bj_egpmbh:nhfxi!s>2:koe60X\@GN_]KL_OAEb>okiVij|Rokdsefj44<aekTol~Pcupo[b4X{xl0eaoPc`r\wqiuino37dbn_bmqa<=ndhUfmymg109jhdYji}icSnabbhlfb>okiVgjxnfPcnoak`=ndhUfmymg_fcm`c=ndhUfmymg_fcm`}c<aekT~h}jt^awvig<aekTyo{ur33?ljfW}xjohQmugdfv`=ndhU~diPm`v`lf=ndhU~diloof24>okiV~yejm`ne]oqqd<aekTxghgdp`?iekWzxgS|2?>b9ogiYtzeUz0<0l;mao[vtkWx692o5buyaz[ii;87h0axvly^nl848e3dsotQco=0=f>krpjsT`b2<>c9nq}e~Wee783m4mtz`}Zubd5:5o6czxb{\w`j;97i0axvly^qfh949k2g~tnwPsdn?7;><fniiydbk139svjauidgjnakPddnb}==tzeUz0<07;rpo[t:5611x~aQ~<2<;?vtkWx6?2pNOp0c16>FGp0:>6K4;:0yPa6<?jl08>=4>3227<c<6j?=nwc6mc;38j=dc2?1/4oo58c68yVdd21hn6><?:01041>a28h=n85\3149=73=83;8?=:7f;3a2g><[ki15?;50;30752?n3;i:om4d826>5<628qXi>47bd8065<6;::?4k4>b7`3?sR4<h0;6<4>:271Vc421hn6><?:01041>a28h=n=5+886975><^1hi6?uz30195>s49=0;7p*<2380g>d>8<0;697526296`2|@1237)=6c;;31>\>>38p?<4<0;'<g?=0m>0(l<59148 `4=19=0(>:9:09'713=0kl0e>6i:18'772=;1o0b><<:198m6>c290/??:539g8j6442810e>6l:18'772=;1o0b><<:398m6>e290/??:539g8j6442:10e>6n:18'772=;1o0b><<:598m6>>290/??:539g8j6442<10e>68:18'772=;1o0b><<:798m6>1290/??:539g8j6442>10e>6::18'772=;1o0b><<:998m6>3290/??:539g8j6442010e>6<:18'772=;1o0b><<:`98m6>5290/??:539g8j6442k10e>6>:18'772=;1o0b><<:b98m6>7290/??:539g8j6442m10e>9i:18'772=;1o0b><<:d98m61b290/??:539g8j6442o10e>9l:18'772=;1o0b><<:028?l50j3:1(><;:2:f?k55;3;:76g<7`83>!55<393i6`<22826>=n;>31<7*<2580<`=i;;91=>54i25;>5<#;;>1?5k4n200>42<3`9<;7>5$207>6>b3g99?7?:;:k033<72-9987=7e:l066<6>21b?:;50;&061<40l1e??=51698m613290/??:539g8j64428207d=83;29 6432:2n7c==3;3:?>o41?0;6)==4;1;a>h4::0:m65f38794?"4:=084h5a33195g=<a:3?6=4+33697=c<f:886<m4;h1:7?6=,:8?6>6j;o117?7c32c85?4?:%110?5?m2d8>>4>e:9j7<7=83.8>94<8d9m775=9o10e>7?:18'772=;1o0b><<:328?l5?03:1(><;:2:f?k55;38:76g<7e83>!55<393i6`<22816>=n;>81<7*<2580<`=i;;91>>54+ec94?"4:=0o56`<2283?>-c03:1(><;:e;8j6442810'i950;&061<c12d8>>4=;:)g2?6=,:8?6i74n200>6=<#m?1<7*<258g=>h4::0?76%k4;29 6432m30b><<:498/a4=83.8>94k9:l066<132!o=7>5$207>a?<f:886:54+e294?"4:=0o56`<228;?>-dn3:1(><;:e;8j6442010'nk50;&061<c12d8>>4n;:)``?6=,:8?6i74n200>g=<#ji1<7*<258g=>h4::0h76%lb;29 6432m30b><<:e98/fg=83.8>94k9:l066<b32!h57>5$207>a?<f:886k54+b594?"4:=0o56`<22824>=,k?0;6)==4;f:?k55;3;:76%l5;29 6432m30b><<:008?.e3290/??:5d89m775=9:10'n=50;&061<c12d8>>4>4:9(g7<72-9987j6;o117?7232!h=7>5$207>a?<f:886<84;*a3>5<#;;>1h45a331952=<#kl1<7*<258g=>h4::0:465$bd83>!55<3n27c==3;3:?>-b93:1(><;:e;8j64428k07&k?:18'772=l01e??=51c98/a`=83.8>94k9:l066<6k21 hh4?:%110?b>3g99?7?k;:)g`?6=,:8?6i74n200>4c<3"nh6=4+3369`<=i;;91=k54+e194?"4:=0o56`<22815>=,k10;6)==4;f:?k55;38976%md;29 6432m30b><<:318?lg32900'il50;&061<c12d8>>4=0:9a<g>=83;1<7>t$2;`>=?43A2i:6F7899l777=831vn5l8:182>5<7s-92o7<:c:J;f3=O0120c<h<:188yg12;3:157>50z&0=f<4<m1C4o84H9:;?!40=390e9?50;9j07<722c??7>5;h67>5<<ah;1<75fa583>>ob<3:17b==8;29?j5513:17pl85983><<729q/?4m535f8L=d13A2346*=7480?l262900e9<50;9j06<722c?87>5;hc2>5<<ah>1<75fe583>>i4:10;66a<2883>>{e?<;1<7<50;2x 6?d2::27E6m6:J;<==#:>?1=>5f24d94?=h;8l1<75rb5d7>5<3290;w)=6c;13f>N?j?1C4564$356><><,:8>65m<;h06b?6=3`8=<7>5;h055?6=3f9:j7>5;|`41<<72=0;6=u+38a95`0<@1h=7E678:&130<53`3<6=44id694?=n;;h1<75`33:94?=zj>??6=4;:183!5>k3;n:6F7b79K<=><,;=>6?5f9683>>ob<3:17d==b;29?j5503:17pl85783>1<729q/?4m51d48L=d13A2346*=7481?l?02900eh:50;9j77d=831d??650;9~f23e290?6=4?{%1:g?7b>2B3n;5G89:8 7122;1b5:4?::kf0?6=3`99n7>5;n11<?6=3th<9?4?:583>5}#;0i1=h84H9`5?M>?02.9;84=;h;4>5<<al>1<75f33`94?=h;;21<75rb67e>5<3290;w)=6c;3f<>N?j?1C4564$356>45<a0=1<75fe583>>o4<;0;66a<2983>>{e?<:1<7:50;2x 6?d28o=7E6m6:J;<==#:>?1>6g67;29?lc32900e><m:188k64?2900qo=k5;293?6=8r.85n4<4c9K<g0<@1237)<85;18m17=831b8?4?::k77?6=3`>?6=44i`694?=nm=0;66a<2983>>{e;m91<7950;2x 6?d2:>i7E6m6:J;<==#:>?1?6g;1;29?l252900e9=50;9j01<722cj87>5;hg7>5<<g:836=44}c1g5?6=?3:1<v*<9b800g=O0k<0D567;%041?5<a=;1<75f4383>>o3;3:17d:;:188md2=831bi94?::m06=<722wi?nh50;594?6|,:3h6>:m;I:a2>N?011/>:;53:k75?6=3`>96=44i5194?=n<=0;66gn4;29?lc32900c><7:188yg5dl3:1;7>50z&0=f<4<k1C4o84H9:;?!40=390e9?50;9j07<722c??7>5;h67>5<<ah>1<75fe583>>i4:10;66sm3b`94?1=83:p(>7l:26a?M>e>2B3455+26797>o393:17d:=:188m15=831b894?::kb0?6=3`o?6=44o20;>5<<uk9h;7>57;294~"41j088o5G8c48L=>?3-8<97=4i5394?=n<;0;66g;3;29?l232900el:50;9ja1<722e8>54?::a7f3=83=1<7>t$2;`>62e3A2i:6F7899'623=;2c?=7>5;h61>5<<a=91<75f4583>>of<3:17dk;:188k64?2900qo=l3;293?6=8r.85n4<4c9K<g0<@1237)<85;18m17=831b8?4?::k77?6=3`>?6=44i`694?=nm=0;66a<2983>>{e;j;1<7950;2x 6?d2:>i7E6m6:J;<==#:>?1?6g;1;29?l252900e9=50;9j01<722cj87>5;hg7>5<<g:836=44}c1ab?6=?3:1<v*<9b800g=O0k<0D567;%041?5<a=;1<75f4383>>o3;3:17d:;:188md2=831bi94?::m06=<722wi?oj50;594?6|,:3h6>:m;I:a2>N?011/>:;53:k75?6=3`>96=44i5194?=n<=0;66gn4;29?lc32900c><7:188yg5ej3:1;7>50z&0=f<4<k1C4o84H9:;?!40=390e9?50;9j07<722c??7>5;h67>5<<ah>1<75fe583>>i4:10;66sm3c;94?1=83:p(>7l:26a?M>e>2B3455+26797>o393:17d:=:188m15=831b894?::kb0?6=3`o?6=44o20;>5<<uk9i;7>57;294~"41j088o5G8c48L=>?3-8<97=4i5394?=n<;0;66g;3;29?l232900el:50;9ja1<722e8>54?::a7g3=83=1<7>t$2;`>62e3A2i:6F7899'623=;2c?=7>5;h61>5<<a=91<75f4583>>of<3:17dk;:188k64?2900qo=m1;293?6=8r.85n4<4c9K<g0<@1237)<85;18m17=831b8?4?::k77?6=3`>?6=44i`694?=nm=0;66a<2983>>{e;hl1<7950;2x 6?d2:>i7E6m6:J;<==#:>?1?6g;1;29?l252900e9=50;9j01<722cj87>5;hg7>5<<g:836=44}c1b`?6=?3:1<v*<9b800g=O0k<0D567;%041?5<a=;1<75f4383>>o3;3:17d:;:188md2=831bi94?::m06=<722wi?ll50;594?6|,:3h6>:m;I:a2>N?011/>:;53:k75?6=3`>96=44i5194?=n<=0;66gn4;29?lc32900c><7:188yg5f13:1;7>50z&0=f<4<k1C4o84H9:;?!40=390e9?50;9j07<722c??7>5;h67>5<<ah>1<75fe583>>i4:10;66sm3`594?1=83:p(>7l:26a?M>e>2B3455+26797>o393:17d:=:188m15=831b894?::kb0?6=3`o?6=44o20;>5<<uk9j97>57;294~"41j088o5G8c48L=>?3-8<97=4i5394?=n<;0;66g;3;29?l232900el:50;9ja1<722e8>54?::a7d5=83=1<7>t$2;`>62e3A2i:6F7899'623=;2c?=7>5;h61>5<<a=91<75f4583>>of<3:17dk;:188k64?2900qo=n1;293?6=8r.85n4<4c9K<g0<@1237)<85;18m17=831b8?4?::k77?6=3`>?6=44i`694?=nm=0;66a<2983>>{e;0l1<7950;2x 6?d2:>i7E6m6:J;<==#:>?1?6g;1;29?l252900e9=50;9j01<722cj87>5;hg7>5<<g:836=44}c1f7?6=?3:1<v*<9b800g=O0k<0D567;%041?5<a=;1<75f4383>>o3;3:17d:;:188md2=831bi94?::m06=<722wi?h?50;594?6|,:3h6>:m;I:a2>N?011/>:;53:k75?6=3`>96=44i5194?=n<=0;66gn4;29?lc32900c><7:188yg5cn3:1;7>50z&0=f<4<k1C4o84H9:;?!40=390e9?50;9j07<722c??7>5;h67>5<<ah>1<75fe583>>i4:10;66sm3ef94?1=83:p(>7l:26a?M>e>2B3455+26797>o393:17d:=:188m15=831b894?::kb0?6=3`o?6=44o20;>5<<uk9on7>57;294~"41j088o5G8c48L=>?3-8<97=4i5394?=n<;0;66g;3;29?l232900el:50;9ja1<722e8>54?::a7a?=83=1<7>t$2;`>62e3A2i:6F7899'623=;2c?=7>5;h61>5<<a=91<75f4583>>of<3:17dk;:188k64?2900qo=k7;293?6=8r.85n4<4c9K<g0<@1237)<85;18m17=831b8?4?::k77?6=3`>?6=44i`694?=nm=0;66a<2983>>{e;j31<7950;2x 6?d2:>i7E6m6:J;<==#:>?1?6g;1;29?l252900e9=50;9j01<722cj87>5;hg7>5<<g:836=44}c1a7?6=?3:1<v*<9b800g=O0k<0D567;%041?5<a=;1<75f4383>>o3;3:17d:;:188md2=831bi94?::m06=<722wi?4j50;594?6|,:3h6>:m;I:a2>N?011/>:;53:k75?6=3`>96=44i5194?=n<=0;66gn4;29?lc32900c><7:188yg5c>3:1?7>50z&0=f<6m91C4o84H9:;?!40=380e4950;9ja1<722e8>54?::a7a2=8391<7>t$2;`>4c73A2i:6F7899'623=:2c2;7>5;hg7>5<<g:836=44}c1g6?6=;3:1<v*<9b82a5=O0k<0D567;%041?4<a0=1<75fe583>>i4:10;66sm3e294?5=83:p(>7l:0g3?M>e>2B3455+26796>o>?3:17dk;:188k64?2900qo=le;297?6=8r.85n4>e19K<g0<@1237)<85;08m<1=831bi94?::m06=<722wi?nm50;194?6|,:3h6<k?;I:a2>N?011/>:;52:k:3?6=3`o?6=44o20;>5<<uk9h47>53;294~"41j0:i=5G8c48L=>?3-8<97<4i8594?=nm=0;66a<2983>>{e;j<1<7=50;2x 6?d28o;7E6m6:J;<==#:>?1>6g67;29?lc32900c><7:188yg5d<3:1?7>50z&0=f<6m91C4o84H9:;?!40=380e4950;9ja1<722e8>54?::a7f4=8391<7>t$2;`>4c73A2i:6F7899'623=:2c2;7>5;hg7>5<<g:836=44}c1`4?6=;3:1<v*<9b82a5=O0k<0D567;%041?4<a0=1<75fe583>>i4:10;66sm3cg94?5=83:p(>7l:0g3?M>e>2B3455+26796>o>?3:17dk;:188k64?2900qo=mc;297?6=8r.85n4>e19K<g0<@1237)<85;08m<1=831bi94?::m06=<722wi?oo50;194?6|,:3h6<k?;I:a2>N?011/>:;52:k:3?6=3`o?6=44o20;>5<<uk9i47>53;294~"41j0:i=5G8c48L=>?3-8<97<4i8594?=nm=0;66a<2983>>{e;k<1<7=50;2x 6?d28o;7E6m6:J;<==#:>?1>6g67;29?lc32900c><7:188yg5e:3:1?7>50z&0=f<6m91C4o84H9:;?!40=380e4950;9ja1<722e8>54?::a7g6=8391<7>t$2;`>4c73A2i:6F7899'623=:2c2;7>5;hg7>5<<g:836=44}c1ba?6=;3:1<v*<9b82a5=O0k<0D567;%041?4<a0=1<75fe583>>i4:10;66sm3`a94?5=83:p(>7l:0g3?M>e>2B3455+26796>o>?3:17dk;:188k64?2900qo=na;297?6=8r.85n4>e19K<g0<@1237)<85;08m<1=831bi94?::m06=<722wi?l650;194?6|,:3h6<k?;I:a2>N?011/>:;52:k:3?6=3`o?6=44o20;>5<<uk9j:7>53;294~"41j0:i=5G8c48L=>?3-8<97<4i8594?=nm=0;66a<2983>>{e;h>1<7=50;2x 6?d28o;7E6m6:J;<==#:>?1>6g67;29?lc32900c><7:188yg5f:3:1?7>50z&0=f<6m91C4o84H9:;?!40=380e4950;9ja1<722e8>54?::a7d6=8391<7>t$2;`>4c73A2i:6F7899'623=:2c2;7>5;hg7>5<<g:836=44}c1f0?6=;3:1<v*<9b82a5=O0k<0D567;%041?4<a0=1<75fe583>>i4:10;66sm3d094?5=83:p(>7l:0g3?M>e>2B3455+26796>o>?3:17dk;:188k64?2900qo=j0;297?6=8r.85n4>e19K<g0<@1237)<85;08m<1=831bi94?::m06=<722wi?ik50;194?6|,:3h6<k?;I:a2>N?011/>:;52:k:3?6=3`o?6=44o20;>5<<uk9oo7>53;294~"41j0:i=5G8c48L=>?3-8<97<4i8594?=nm=0;66a<2983>>{e;mk1<7=50;2x 6?d28o;7E6m6:J;<==#:>?1>6g67;29?lc32900c><7:188yg5c03:1?7>50z&0=f<6m91C4o84H9:;?!40=380e4950;9ja1<722e8>54?::a7fg=8391<7>t$2;`>4c73A2i:6F7899'623=:2c2;7>5;hg7>5<<g:836=44}c1a0?6=;3:1<v*<9b82a5=O0k<0D567;%041?4<a0=1<75fe583>>i4:10;66sm38g94?5=83:p(>7l:0g3?M>e>2B3455+26796>o>?3:17dk;:188k64?2900qo9n9;292g<22>9pD567;%1:g?>b12P2:7?t148~ =>>2:3<7d<:8;29 6432;?<7c==3;28?l42>3:1(><;:374?k55;3;07d<:5;29 6432;?<7c==3;08?l42<3:1(><;:374?k55;3907d<:3;29 6432;?<7c==3;68?l42:3:1(><;:374?k55;3?07d<:1;29 6432;?<7c==3;48?l4283:1(><;:374?k55;3=07d<;f;29 6432;?<7c==3;:8?l43m3:1(><;:374?k55;3307d<;c;29 6432;?<7c==3;c8?l43j3:1(><;:374?k55;3h07d<;a;29 6432;?<7c==3;a8?l4313:1(><;:374?k55;3n07d<;8;29 6432;?<7c==3;g8?l43?3:1(><;:374?k55;3l07d<;6;29 6432;?<7c==3;33?>o5<<0;6)==4;063>h4::0:=65f25694?"4:=099:5a331957=<a;>86=4+3369601<f:886<=4;h075?6=,:8?6?;8;o117?7332c98=4?:%110?42?2d8>>4>5:9j66`=83.8>94=569m775=9?10e?=j:18'772=:<=0b><<:058?l44l3:1(><;:374?k55;3;376g=3b83>!55<38>;6`<2282=>=n::h1<7*<258112=i;;91=l54i31b>5<#;;>1>894n200>4d<3`8857>5$207>7303g99?7?l;:k17=<72-9987<:7:l066<6l21b>>850;&061<5=>1e??=51d98m752290/??:52458j64428l07d<<4;29 6432;?<7c==3;03?>o5;:0;6)==4;063>h4::09=65f22094?"4:=099:5a331967=<a;9:6=4+3369601<f:886?=4;h004?6=,:8?6?;8;o117?4332c9>k4?:%110?42?2d8>>4=5:9j67c=83.8>94=569m775=:?10e?<k:18'772=:<=0b><<:358?l45j3:1(><;:374?k55;38376g=2`83>!55<38>;6`<2281=>=n:;31<7*<258112=i;;91>l54i30;>5<#;;>1>894n200>7d<3`89;7>5$207>7303g99?7<l;:k163<72-9987<:7:l066<5l21b>?;50;&061<5=>1e??=52d98m743290/??:52458j6442;l07d<=3;29 6432;?<7c==3;13?>o5:;0;6)==4;063>h4::08=65f23294?"4:=099:5a331977=<a;;m6=4+3369601<f:886>=4;h02a?6=,:8?6?;8;o117?5332c9=i4?:%110?42?2d8>>4<5:9j64e=83.8>94=569m775=;?10e??m:18'772=:<=0b><<:258?l46i3:1(><;:374?k55;39376g=1883>!55<38>;6`<2280=>=n:821<7*<258112=i;;91?l54i334>5<#;;>1>894n200>6d<3`8:97>5$207>7303g99?7=l;:k151<72-9987<:7:l066<4l21b><=50;&061<5=>1e??=53d98m775290/??:52458j6442:l07d<>1;29 6432;?<7c==3;63?>o5990;6)==4;063>h4::0?=65f21d94?"4:=099:5a331907=<a;:n6=4+3369601<f:8869=4;h03`?6=,:8?6?;8;o117?2332c9<n4?:%110?42?2d8>>4;5:9j65g=83.8>94=569m775=<?10e?>6:18'772=:<=0b><<:558?l4703:1(><;:374?k55;3>376g=0683>!55<38>;6`<2287=>=n:9<1<7*<258112=i;;918l54i326>5<#;;>1>894n200>1d<3`8;87>5$207>7303g99?7:l;:k146<72-9987<:7:l066<3l21b>=<50;&061<5=>1e??=54d98m766290/??:52458j6442=l07d?if;29 6432;?<7c==3;73?>o6nl0;6)==4;063>h4::0>=65f1gf94?"4:=099:5a331917=<a8lh6=4+3369601<f:8868=4;h3ef?6=,:8?6?;8;o117?3332c:jl4?:%110?42?2d8>>4:5:9j5c?=83.8>94=569m775==?10e<h7:18'772=:<=0b><<:458?l7a?3:1(><;:374?k55;3?376g>f783>!55<38>;6`<2286=>=n:<k1<7*<258112=i;;919l54i36g>5<#;;>1>894n200>0d<3`8?>7>5$207>7303g99?7;l;:k172<72-9987<:7:l066<2l21b>?m50;&061<5=>1e??=55d98m746290/??:52458j6442<l07d<>6;29 6432;?<7c==3;43?>o58k0;6)==4;063>h4::0==65f21294?"4:=099:5a331927=<a8l>6=4+3369601<f:886;=4;h`b>5<<a:9j6=44i246>5<<a:<?6=44i245>5<<g:<<6=44o37a>5<<j;lo6=4>c;c960}O0120(>7l:9ga?_?128q9?7s+24f975`<a:?j6=4+336970?<f:886=54i27;>5<#;;>1?874n200>4=<a:?<6=4+336970?<f:886?54i275>5<#;;>1?874n200>6=<a:?>6=4+336970?<f:886954i277>5<#;;>1?874n200>0=<a:?86=4+336970?<f:886;54i271>5<#;;>1?874n200>2=<a:?:6=4+336970?<f:886554i273>5<#;;>1?874n200><=<a:<86=4+336970?<f:886l54i241>5<#;;>1?874n200>g=<a:<:6=4+336970?<f:886n54i243>5<#;;>1?874n200>a=<a:?m6=4+336970?<f:886h54i27f>5<#;;>1?874n200>c=<a:?o6=4+336970?<f:886<>4;h16g?6=,:8?6>;6;o117?7632c89o4?:%110?5212d8>>4>2:9j71`=83.8>94<589m775=9:10eoo50;9j76g=831b=k:50;9j733=831b?;:50;9j730=831d?;950;9l60d=831i4o650;394?6|,:3h657<;I:a2>N?011d???50;9~f=d0290:6=4?{%1:g?42k2B3n;5G89:8k4`42900qo662;29e?6=8r.85n4<4d9K<g0<@1237W79:0y0f?{#;:h14lk4$356>0=ni=0;66gj4;29?lg62900c><7:188k64f2900e9l50;&061<3i2d8>>4?;:k7=?6=,:8?69o4n200>4=<a=21<7*<2587e>h4::0976g;7;29 6432=k0b><<:298m10=83.8>94;a:l066<332wi44?50;c94?6|,:3h6>:j;I:a2>N?011Q5;4>{2`9y!54j32ji6*=7486?lg32900eh:50;9je4<722e8>54?::m06d<722c?n7>5$207>1g<f:886=54i5;94?"4:=0?m6`<2282?>o303:1(><;:5c8j6442;10e9950;&061<3i2d8>>4<;:k72?6=,:8?69o4n200>1=<uk22<7>5a;294~"41j088h5G8c48L=>?3S3=6<u<b;'76d=0ho0(?9::49je1<722cn87>5;hc2>5<<g:836=44o20b>5<<a=h1<7*<2587e>h4::0;76g;9;29 6432=k0b><<:098m1>=83.8>94;a:l066<532c?;7>5$207>1g<f:886>54i5494?"4:=0?m6`<2287?>{e01l1<7o50;2x 6?d2:>n7E6m6:J;<==]1?0:w>l5}%10f?>fm2.9;84:;hc7>5<<al>1<75fa083>>i4:10;66a<2`83>>o3j3:1(><;:5c8j6442910e9750;&061<3i2d8>>4>;:k7<?6=,:8?69o4n200>7=<a==1<7*<2587e>h4::0876g;6;29 6432=k0b><<:598yg>?l3:187>50z&0=f<4991C4o84H9:;?!54j32ji6gn3;29?lc>2900e>:=:188k6622900qo67c;290?6=8r.85n4<119K<g0<@1237)=<b;:ba>of;3:17dk6:188m6252900c>>::188yg>?j3:187>50z&0=f<4991C4o84H9:;?!54j32ji6gn3;29?lc>2900e>:=:188k6622900qo67a;290?6=8r.85n4<119K<g0<@1237)=<b;:ba>of;3:17dk6:188m6252900c>>::188yv52i3:1>vP<5`9><<4=<k1v>;7:181[5202735?4;9:p701=838pR>;8;<::6?2?3ty89;4?:3y]700<51396994}r161?6=:rT89852880903=z{:??6=4={_160>;?180?n6s|34194?4|V:?870661;6:?xu4=;0;6?uQ34089=?62=20q~=:1;296~X4=81644?5469~w6372909wS=:0:?;=4<3>2wx?;=50;0xZ6043422<7:m;|q027<72;qU?;<4=9;3>1?<uz9==7>52z\024=:00:1855rs243>5<5sW9=<63791873>{t;<l1<7<t^27e?8>>83>=7p}<5d83>7}Y;<o0156i:5`8yv52l3:1>vP<5e9><=`=<01v>;l:181[52k2734k4;8:p70d=838pR>;m;<:;b?203ty88k4?:3y]71`<512m6984}r151?6==rT8:8528809e1=:00;1m9528829e1=:01l1m95rs247>5<2sW9=8637938b5>;?180j=637918b5>;?0o0j=6s|37494?4|V:<=70662;g7?xu>:=0;6?u2880977><512o6>:=;|q:5g<72;q644<533c89=?62l>0q~7=3;296~;?1808>55289a9714<uz3:m7>52z?;=4<4:h1644>5e59~w<452909w0660;11<>;?0k088?5rs83:>5<5s422<7==a:?;<c<b<2wx5??50;0x9=>a2:837067a;176>{t;?=1<7<t^244?8>?n399m6s|24`94?4|V;?i7067d;131>{t18o1<7<t=9:g>d5<512h6>>:;|q:5a<72;q645m5a29><=d=;9?0q~7>c;296~;?0k0j?6378`8040=z{8l?6=4={<:a<?5592734l4n3:p740=83?p15l8:0d0?8>?l3o27067c;g:?8>?j3o27067a;g:?x{e:oo1<7?l:8811~N?011/?4m58da8^<0=9r886p*=5e804c=n;<k1<7*<25801<=i;;91<65f34:94?"4:=08945a33195>=n;<=1<7*<25801<=i;;91>65f34494?"4:=08945a33197>=n;<?1<7*<25801<=i;;91865f34694?"4:=08945a33191>=n;<91<7*<25801<=i;;91:65f34094?"4:=08945a33193>=n;<;1<7*<25801<=i;;91465f34294?"4:=08945a3319=>=n;?91<7*<25801<=i;;91m65f37094?"4:=08945a3319f>=n;?;1<7*<25801<=i;;91o65f37294?"4:=08945a3319`>=n;<l1<7*<25801<=i;;91i65f34g94?"4:=08945a3319b>=n;<n1<7*<25801<=i;;91==54i27`>5<#;;>1?874n200>47<3`9>n7>5$207>63>3g99?7?=;:k00c<72-9987=:9:l066<6;21bnl4?::k07d<722c:j94?::k020<722c8:94?::k023<722e8::4?::m11g<722h3n:4?:083>5}#;0i1>8m4H9`5?M>?02e:j>4?::a<=g=83>1<7>t$2;`>6773A2i:6F7899'76d=0hl0el=50;9ja<<722c88?4?::m040<722wi44<50;c94?6|,:3h6>:j;I:a2>N?011Q5;4>{2`9y!54j32jj6*=7486?lg32900eh:50;9je4<722e8>54?::m06d<722c?n7>5$207>1g<f:886=54i5;94?"4:=0?m6`<2282?>o303:1(><;:5c8j6442;10e9950;&061<3i2d8>>4<;:k72?6=,:8?69o4n200>1=<uk22=7>5a;294~"41j088h5G8c48L=>?3S3=6<u<b;'76d=0hl0(?9::49je1<722cn87>5;hc2>5<<g:836=44o20b>5<<a=h1<7*<2587e>h4::0;76g;9;29 6432=k0b><<:098m1>=83.8>94;a:l066<532c?;7>5$207>1g<f:886>54i5494?"4:=0?m6`<2287?>{e00:1<7o50;2x 6?d2:>n7E6m6:J;<==]1?0:w>l5}%10f?>fn2.9;84:;hc7>5<<al>1<75fa083>>i4:10;66a<2`83>>o3j3:1(><;:5c8j6442910e9750;&061<3i2d8>>4>;:k7<?6=,:8?69o4n200>7=<a==1<7*<2587e>h4::0876g;6;29 6432=k0b><<:598yg>?n3:1m7>50z&0=f<4<l1C4o84H9:;?_?128q8n7s+32`9<d`<,;=>685fa583>>ob<3:17do>:188k64?2900c><n:188m1d=83.8>94;a:l066<732c?57>5$207>1g<f:886<54i5:94?"4:=0?m6`<2281?>o3?3:1(><;:5c8j6442:10e9850;&061<3i2d8>>4;;:a<=d=83>1<7>t$2;`>6773A2i:6F7899'76d=0hl0el=50;9ja<<722c88?4?::m040<722wi45j50;694?6|,:3h6>??;I:a2>N?011/?>l58`d8md5=831bi44?::k007<722e8<84?::a<=e=83>1<7>t$2;`>6773A2i:6F7899'76d=0hl0el=50;9ja<<722c88?4?::m040<722wx?8o50;0xZ63f3422>7:m;|q01=<72;qU?864=9;1>1?<uz9>;7>52z\012=:0081855rs275>5<5sW9>:63793873>{t;<?1<7<t^276?8>>:3>=7p}<5583>7}Y;<>0157>:5`8yv52;3:1>vP<529><<7=<01v>;=:181[52:2735<4;8:p707=838pR>;>;<::5?203ty89=4?:3y]706<513:6984}r157?6=:rT8:>5288290g=z{:<96=4={_156>;?190?56s|37394?4|V:<:70660;6;?xu4>90;6?uQ37289=?72==0q~=:f;296~X4=o1644>5479~w63b2909wS=:e:?;<c<3j2wx?8j50;0xZ63c3423j7:6;|q01f<72;qU?8m4=9:e>1><uz9>n7>52z\01g=:01l18:5rs26e>5<5sW9?j6378g872>{t9o>1<7<t^0d7?8>?i3k87p}<6483>0}Y;??0157=:`689=?62h>0157?:`689=>a2h>0q~=94;291~X4>=1644<5a09><<7=i81644>5a09><=`=i81v>89:181[51>2735?4j4:p=4e=838p156n:226?8>?j3k87p}62583>7}:0081??64=9:g>6253ty2=o4?:3y><<4=;;k0157>:d68yv?5;3:1>v3790806==:01i1?9<4}r;2e?6=:r735<4<2`9><<6=m=1v4<=:1818>>839946378c8007=z{0;26=4={<::4?55i2734k4j4:p=77=838p156n:261?8>?n39946s|37594?4|V:<<7067f;11e>{t18n1<7<t=9:a>6623423o7o<;|q11g<72;qU>8l4=9:g>6623ty2=h4?:3y><=b=i:1645m53178yv56>3:19v37b682b6=:01k1i45289`9a<=:01n1i45289a9a<=zuk8mj7>51b8:>73|@1237)=6c;:f`>\>>3;p>>4r$37g>66a3`9>m7>5$207>63>3g99?7>4;h16<?6=,:8?6>;6;o117?7<3`9>;7>5$207>63>3g99?7<4;h162?6=,:8?6>;6;o117?5<3`9>97>5$207>63>3g99?7:4;h160?6=,:8?6>;6;o117?3<3`9>?7>5$207>63>3g99?784;h166?6=,:8?6>;6;o117?1<3`9>=7>5$207>63>3g99?764;h164?6=,:8?6>;6;o117??<3`9=?7>5$207>63>3g99?7o4;h156?6=,:8?6>;6;o117?d<3`9==7>5$207>63>3g99?7m4;h154?6=,:8?6>;6;o117?b<3`9>j7>5$207>63>3g99?7k4;h16a?6=,:8?6>;6;o117?`<3`9>h7>5$207>63>3g99?7??;:k01f<72-9987=:9:l066<6921b?8l50;&061<4=01e??=51398m62a290/??:534;8j64428907dln:188m65f2900e<h;:188m6022900e>8;:188m6012900c>88:188k73e2900n5l8:182>5<7s-92o7<:c:J;f3=O0120c<h<:188yg>?i3:187>50z&0=f<4991C4o84H9:;?!54j32i<6gn3;29?lc>2900e>:=:188k6622900qo662;29e?6=8r.85n4<4d9K<g0<@1237W79:0y0f?{#;:h14o>4$356>0=ni=0;66gj4;29?lg62900c><7:188k64f2900e9l50;&061<3i2d8>>4?;:k7=?6=,:8?69o4n200>4=<a=21<7*<2587e>h4::0976g;7;29 6432=k0b><<:298m10=83.8>94;a:l066<332wi44?50;c94?6|,:3h6>:j;I:a2>N?011Q5;4>{2`9y!54j32i<6*=7486?lg32900eh:50;9je4<722e8>54?::m06d<722c?n7>5$207>1g<f:886=54i5;94?"4:=0?m6`<2282?>o303:1(><;:5c8j6442;10e9950;&061<3i2d8>>4<;:k72?6=,:8?69o4n200>1=<uk22<7>5a;294~"41j088h5G8c48L=>?3S3=6<u<b;'76d=0k:0(?9::49je1<722cn87>5;hc2>5<<g:836=44o20b>5<<a=h1<7*<2587e>h4::0;76g;9;29 6432=k0b><<:098m1>=83.8>94;a:l066<532c?;7>5$207>1g<f:886>54i5494?"4:=0?m6`<2287?>{e01l1<7o50;2x 6?d2:>n7E6m6:J;<==]1?0:w>l5}%10f?>e82.9;84:;hc7>5<<al>1<75fa083>>i4:10;66a<2`83>>o3j3:1(><;:5c8j6442910e9750;&061<3i2d8>>4>;:k7<?6=,:8?69o4n200>7=<a==1<7*<2587e>h4::0876g;6;29 6432=k0b><<:598yg>?j3:187>50z&0=f<4991C4o84H9:;?!54j32i<6gn3;29?lc>2900e>:=:188k6622900qo67d;290?6=8r.85n4<119K<g0<@1237)=<b;:a4>of;3:17dk6:188m6252900c>>::188yg>?k3:187>50z&0=f<4991C4o84H9:;?!54j32i<6gn3;29?lc>2900e>:=:188k6622900q~=:a;296~X4=h1644<54c9~w63?2909wS=:8:?;=7<312wx?8950;0xZ6303422>7:7;|q013<72;qU?884=9;1>11<uz9>97>52z\010=:00818;5rs277>5<5sW9>86379087f>{t;<91<7<t^270?8>>93>27p}<5383>7}Y;<80157>:5:8yv5293:1>vP<509><<7=<>1v>;?:181[5282735<4;6:p735=838pR>8<;<::4?2e3ty8:?4?:3y]734<513;6974}r155?6=:rT8:<5288290==z{:<;6=4={_154>;?190?;6s|34d94?4|V:?m70660;65?xu4=l0;6?uQ34g89=>a2=h0q~=:d;296~X4=m1645h5489~w63d2909wS=:c:?;<c<302wx?8l50;0xZ63e3423j7:8;|q00c<72;qU?9h4=9:e>10<uz;m87>52z\2b1=:01k1m>5rs246>5<2sW9=9637938b0>;?180j8637918b0>;?0o0j86s|37694?3|V:<?70662;c2?8>>93k:70660;c2?8>?n3k:7p}<6783>7}Y;?<0157=:d68yv?6k3:1>v378`8040=:01h1m>5rs807>5<5s422>7==8:?;<a<4<;1v4?m:1818>>:399m637908f0>{t1;91<7<t=9;2>64?3423o7=;2:p=4g=838p157>:20b?8>>83o?7p}62383>7}:00:1??64=9:a>6253ty2=44?:3y><<6=;;k0156i:d68yv?593:1>v378`8007=:01l1??64}r153?6=:rT8::5289d977g<uz3:h7>52z?;<g<48<1645m5a29~w73e2909wS<:b:?;<a<48<1v4?j:1818>?l3k87067c;131>{t;8<1<7;t=9`4>4`43423m7k6;<:;f?c>3423h7k6;<:;g?c>3twi?=>50;3`><<5=rB3455+38a9<`c<R0<1=v<<:|&11a<48o1b?8o50;&061<4=01e??=50:9j70>=83.8>94<589m775=921b?8950;&061<4=01e??=52:9j700=83.8>94<589m775=;21b?8;50;&061<4=01e??=54:9j702=83.8>94<589m775==21b?8=50;&061<4=01e??=56:9j704=83.8>94<589m775=?21b?8?50;&061<4=01e??=58:9j706=83.8>94<589m775=121b?;=50;&061<4=01e??=5a:9j734=83.8>94<589m775=j21b?;?50;&061<4=01e??=5c:9j736=83.8>94<589m775=l21b?8h50;&061<4=01e??=5e:9j70c=83.8>94<589m775=n21b?8j50;&061<4=01e??=51198m63d290/??:534;8j64428;07d=:b;29 6432:?27c==3;31?>o4<o0;6)==4;16=>h4::0:?65fb`83>>o4;h0;66g>f583>>o4><0;66g<6583>>o4>?0;66a<6683>>i5=k0;66l7b683>4<729q/?4m524a8L=d13A2346a>f283>>{e01k1<7:50;2x 6?d2:;;7E6m6:J;<==#;:h14o?4i`194?=nm00;66g<4383>>i48<0;66sm88094?g=83:p(>7l:26f?M>e>2B3455U97826d=u-98n76m1:&130<23`k?6=44id694?=ni80;66a<2983>>i4:h0;66g;b;29 6432=k0b><<:198m1?=83.8>94;a:l066<632c?47>5$207>1g<f:886?54i5594?"4:=0?m6`<2280?>o3>3:1(><;:5c8j6442=10qo661;29e?6=8r.85n4<4d9K<g0<@1237W79:0y0f?{#;:h14o?4$356>0=ni=0;66gj4;29?lg62900c><7:188k64f2900e9l50;&061<3i2d8>>4?;:k7=?6=,:8?69o4n200>4=<a=21<7*<2587e>h4::0976g;7;29 6432=k0b><<:298m10=83.8>94;a:l066<332wi44>50;c94?6|,:3h6>:j;I:a2>N?011Q5;4>{2`9y!54j32i=6*=7486?lg32900eh:50;9je4<722e8>54?::m06d<722c?n7>5$207>1g<f:886=54i5;94?"4:=0?m6`<2282?>o303:1(><;:5c8j6442;10e9950;&061<3i2d8>>4<;:k72?6=,:8?69o4n200>1=<uk23j7>5a;294~"41j088h5G8c48L=>?3S3=6<u<b;'76d=0k;0(?9::49je1<722cn87>5;hc2>5<<g:836=44o20b>5<<a=h1<7*<2587e>h4::0;76g;9;29 6432=k0b><<:098m1>=83.8>94;a:l066<532c?;7>5$207>1g<f:886>54i5494?"4:=0?m6`<2287?>{e01h1<7:50;2x 6?d2:;;7E6m6:J;<==#;:h14o?4i`194?=nm00;66g<4383>>i48<0;66sm89f94?2=83:p(>7l:233?M>e>2B3455+32`9<g7<ah91<75fe883>>o4<;0;66a<0483>>{e01i1<7:50;2x 6?d2:;;7E6m6:J;<==#;:h14o?4i`194?=nm00;66g<4383>>i48<0;66s|34c94?4|V:?j70662;6a?xu4=10;6?uQ34:89=?52=30q~=:7;296~X4=>1644<5499~w6312909wS=:6:?;=7<3?2wx?8;50;0xZ6323422>7:9;|q011<72;qU?8:4=9;2>1d<uz9>?7>52z\016=:00;1845rs271>5<5sW9>>6379087<>{t;<;1<7<t^272?8>>93><7p}<5183>7}Y;<:0157>:548yv51;3:1>vP<629><<6=<k1v>8=:181[51:2735=4;9:p737=838pR>8>;<::4?2?3ty8:=4?:3y]736<513;6994}r16b?6=:rT89k52882903=z{:?n6=4={_16a>;?0o0?n6s|34f94?4|V:?o7067f;6:?xu4=j0;6?uQ34a89=>a2=20q~=:b;296~X4=k1645h5469~w62a2909wS=;f:?;<c<3>2wx=k:50;0xZ4`33423m7o<;|q020<72<qU?;;4=9;1>d2<513:6l:4=9;3>d2<512m6l:4}r150?6==rT8:9528809e4=:00;1m<528829e4=:01l1m<5rs245>5<5sW9=:637938f0>{t18i1<7<t=9:b>6623423n7o<;|q:61<72;q644<533:89=>c2:>97p}61c83>7}:0081??o4=9;2>`2<uz39?7>52z?;=4<4:11645m53508yv?6i3:1>v3790806d=:00:1i95rs801>5<5s422<7==8:?;<g<4<;1v4?6:1818>>8399m6378g8f0>{t1;;1<7<t=9:b>6253423j7==8:p731=838pR>88;<:;b?55i2wx5<j50;0x9=>e2::>7067c;c0?xu5=k0;6?uQ24`89=>c2::>7p}61d83>7}:01n1m>5289a9753<uz9::7>55z?;f2<6n:1645o5e89><=d=m01645j5e89><=e=m01vqo=?1;295f<d2;kpD567;%1:g?>bn2P2:7?t228~ 73c2::m7d=:a;29 6432:?27c==3;28?l5203:1(><;:27:?k55;3;07d=:7;29 6432:?27c==3;08?l52>3:1(><;:27:?k55;3907d=:5;29 6432:?27c==3;68?l52<3:1(><;:27:?k55;3?07d=:3;29 6432:?27c==3;48?l52:3:1(><;:27:?k55;3=07d=:1;29 6432:?27c==3;:8?l5283:1(><;:27:?k55;3307d=93;29 6432:?27c==3;c8?l51:3:1(><;:27:?k55;3h07d=91;29 6432:?27c==3;a8?l5183:1(><;:27:?k55;3n07d=:f;29 6432:?27c==3;g8?l52m3:1(><;:27:?k55;3l07d=:d;29 6432:?27c==3;33?>o4=j0;6)==4;16=>h4::0:=65f34`94?"4:=08945a331957=<a:>m6=4+336970?<f:886<=4;h`b>5<<a:9j6=44i0d7>5<<a:<>6=44i247>5<<a:<=6=44o244>5<<g;?i6=44b9`;>5<6290;w)=6c;::7>N?j?1C4564o202>5<<uk2i;7>51;294~"41j099n5G8c48L=>?3f;m?7>5;|`1bd<72=0;6=u+38a95`><@1h=7E678:&07g<?j:1/>:;5129j=2<722cn87>5;h176?6=3f9947>5;|`;<d<72=0;6=u+38a9746<@1h=7E678:&07g<?j;1bm>4?::kf=?6=3`9?>7>5;n131?6=3th35?4?:`83>5}#;0i1?9k4H9`5?M>?02P2:7?t3c8~ 65e21h97)<85;78md2=831bi94?::kb5?6=3f9947>5;n11e?6=3`>i6=4+33690d=i;;91<65f4883>!55<3>j7c==3;38?l2?290/??:54`9m775=:21b8:4?:%110?2f3g99?7=4;h65>5<#;;>18l5a33190>=zj13:6=4n:183!5>k39?i6F7b79K<=><R0<1=v=m:|&07g<?j;1/>:;55:kb0?6=3`o?6=44i`394?=h;;21<75`33c94?=n<k0;6)==4;6b?k55;3:07d:6:18'772=<h1e??=51:9j0=<72-9987:n;o117?4<3`><6=4+33690d=i;;91?65f4783>!55<3>j7c==3;68?xd?190;6l4?:1y'7<e=;=o0D5l9;I:;<>\>>3;p?o4r$21a>=d53-8<97;4i`694?=nm=0;66gn1;29?j5503:17b==a;29?l2e290/??:54`9m775=821b844?:%110?2f3g99?7?4;h6;>5<#;;>18l5a33196>=n<>0;6)==4;6b?k55;3907d:9:18'772=<h1e??=54:9~f=>a290j6=4?{%1:g?53m2B3n;5G89:8^<0=9r9i6p*<3c8;f7=#:>?196gn4;29?lc32900el?50;9l77>=831d??o50;9j0g<72-9987:n;o117?6<3`>26=4+33690d=i;;91=65f4983>!55<3>j7c==3;08?l20290/??:54`9m775=;21b8;4?:%110?2f3g99?7:4;|`;<g<72=0;6=u+38a9746<@1h=7E678:&07g<?j;1bm>4?::kf=?6=3`9?>7>5;n131?6=3th34i4?:583>5}#;0i1?<>4H9`5?M>?02.8?o47b39je6<722cn57>5;h176?6=3f9;97>5;|`;<f<72=0;6=u+38a9746<@1h=7E678:&07g<?j;1bm>4?::kf=?6=3`9?>7>5;n131?6=3th9jo4?:583>5}#;0i1?<>4H9`5?M>?02.8?o47b29je6<722cn57>5;h176?6=3f9;97>5;|q01d<72;qU?8o4=9;1>1d<uz9>47>52z\01==:0081845rs274>5<5sW9>;6379387<>{t;<<1<7<t^275?8>>:3><7p}<5483>7}Y;<?0157=:548yv52<3:1>vP<559><<7=<k1v>;<:181[52;2735<4;9:p704=838pR>;=;<::5?2?3ty89<4?:3y]707<513:6994}r164?6=:rT89=52883903=z{:<86=4={_157>;?190?n6s|37094?4|V:<970660;6:?xu4>80;6?uQ37389=?72=20q~=90;296~X4>91644>5469~w63a2909wS=:f:?;=5<3>2wx?8k50;0xZ63b3423j7:m;|q01a<72;qU?8j4=9:e>1?<uz9>o7>52z\01f=:01l1855rs27a>5<5sW9>n6378g873>{t;=l1<7<t^26e?8>?n3>=7p}ma;296~Xei279jl467:p76g=838pR>=n;<0ee?53:2wx=k:50;0xZ4`33423m7o<;|q020<72<qU?;;4=9;1>d2<513:6l:4=9;3>d2<512m6l:4}r150?6==rT8:9528809e4=:00;1m<528829e4=:01l1m<5rs245>5<5sW9=:637938f0>{t:<h1<7<t^37a?84ai39946s|90a94?4|512j6>>:;<:;f?g43ty2>94?:3y><<4=;;20156k:261?xu>9k0;6?u2880977g<513:6h:4}r;17?6=:r735<4<299><=e=;=80q~7>a;296~;?1808>l528829a1=z{0896=4={<::4?5502734o4<439~w<7>2909w0660;11e>;?0o0n86s|93394?4|512j6>:=;<:;b?5502wx?;950;0xZ6003423j7==a:p=4b=838p156m:226?8>?k3k87p}61g83>7}:01n1?=;4=3da>d5<uz3:i7>52z?;<a<f;2734n4<049~w<472909w0<ia;g7?84aj39;96s|30794?4|51h36><>;<0ef?53:2wx?<850;4x9=d028l87067a;g:?8>?j3o27067d;g:?8>?k3o270<ib;g:?x{t9ol1<7<t^0de?84al39>m6s|1gg94?4|V8ln70<id;16<>{t9on1<7<t^0dg?84al39>;6s|1ga94?4|V8lh70<id;162>{t9oh1<7<t^0da?84al39>96s|1gc94?4|V8lj70<id;160>{t9o31<7<t^0d:?84al39>?6s|1g:94?4|V8l370<id;166>{t9o=1<7<t^0d4?84al39>=6s|1g494?4|V8l=70<id;164>{t:<k1<7<t^37b?84al39=?6s|25f94?4|V;>o70<id;156>{t:=81<7<t^361?84al39==6s|22594?4|V;9<70<id;154>{t:;i1<7<t^30`?84al39>j6s|23394?4|V;8:70<id;16a>{t:8<1<7<t^335?84al39>h6s|21`94?4|V;:i70<id;16g>{t:9:1<7<t^323?84al39>n6s|1g794?4|V8l>70<id;17b>{t:8?1<7<t^336?84am39>m6s|20694?4|V;;?70<ie;16<>{t:891<7<t^330?84am39>;6s|20094?4|V;;970<ie;162>{t:8;1<7<t^332?84am39>96s|20294?4|V;;;70<ie;160>{t:9l1<7<t^32e?84am39>?6s|21g94?4|V;:n70<ie;166>{t:9n1<7<t^32g?84am39>=6s|21a94?4|V;:h70<ie;164>{t:9k1<7<t^32b?84am39=?6s|21;94?4|V;:270<ie;156>{t:921<7<t^32;?84am39==6s|21594?4|V;:<70<ie;154>{t:9<1<7<t^325?84am39>j6s|21794?4|V;:>70<ie;16a>{t:9>1<7<t^327?84am39>h6s|21194?4|V;:870<ie;16g>{t:981<7<t^321?84am39>n6s|21394?4|V;::70<ie;17b>{t:;h1<7<t^30a?84an39>m6s|23c94?4|V;8j70<if;16<>{t:;31<7<t^30:?84an39>;6s|23:94?4|V;8370<if;162>{t:;=1<7<t^304?84an39>96s|23494?4|V;8=70<if;160>{t:;?1<7<t^306?84an39>?6s|23694?4|V;8?70<if;166>{t:;91<7<t^300?84an39>=6s|23094?4|V;8970<if;164>{t:;:1<7<t^303?84an39=?6s|20d94?4|V;;m70<if;156>{t:8o1<7<t^33f?84an39==6s|20f94?4|V;;o70<if;154>{t:8i1<7<t^33`?84an39>j6s|20`94?4|V;;i70<if;16a>{t:8k1<7<t^33b?84an39>h6s|20;94?4|V;;270<if;16g>{t:821<7<t^33;?84an39>n6s|20594?4|V;;<70<if;17b>{t:=;1<7<t^362?857839>m6s|25294?4|V;>;70=?0;16<>{t::l1<7<t^31e?857839>;6s|22g94?4|V;9n70=?0;162>{t::n1<7<t^31g?857839>96s|22a94?4|V;9h70=?0;160>{t::h1<7<t^31a?857839>?6s|22c94?4|V;9j70=?0;166>{t::31<7<t^31:?857839>=6s|22:94?4|V;9370=?0;164>{t::<1<7<t^315?857839=?6s|22794?4|V;9>70=?0;156>{t::>1<7<t^317?857839==6s|22194?4|V;9870=?0;154>{t::81<7<t^311?857839>j6s|22394?4|V;9:70=?0;16a>{t:::1<7<t^313?857839>h6s|23d94?4|V;8m70=?0;16g>{t:;o1<7<t^30f?857839>n6s|23f94?4|V;8o70=?0;17b>{t:<21<7<t^37;?857939>m6s|24494?4|V;?=70=?1;16<>{t:<?1<7<t^376?857939>;6s|24694?4|V;??70=?1;162>{t:<91<7<t^370?857939>96s|24094?4|V;?970=?1;160>{t:<;1<7<t^372?857939>?6s|24294?4|V;?;70=?1;166>{t:=l1<7<t^36e?857939>=6s|25g94?4|V;>n70=?1;164>{t:=i1<7<t^36`?857939=?6s|25`94?4|V;>i70=?1;156>{t:=k1<7<t^36b?857939==6s|25;94?4|V;>270=?1;154>{t:=21<7<t^36;?857939>j6s|25594?4|V;><70=?1;16a>{t:=<1<7<t^365?857939>h6s|25794?4|V;>>70=?1;16g>{t:=>1<7<t^367?857939>n6s|25194?4|V;>870=?1;17b>{tjh0;6;uQb`9>6cb=jh16>kk5b`9>6c`=jh16?=>5b`9>757=jh1v>=n:185[54i279ji4<3`9>6cc=;:k01?hi:21b?8578398m63<00807d=z{:<>6=49{_151>;5nm08:8522gg9733<5;lm6>8:;<134?51=278<<4<649~w603290=wS=94:?1ba<4>=16>kk5376897`a2:<?70=?0;150>;48808:95rs245>5<5sW9=:63<008023=z{:<<6=4={_153>;5nm08::5rs822>5<5s48mh7<:b:?1b`<6n=1v4<8:18184al39=:63=fd8022=z{0:96=4={<0ea?42j279jk4>f59~w<4?2909w0<ie;152>;5no08::5rs820>5<5s48mj7<:b:?045<6n=1v4<6:18184an39=:63<018022=z{0:?6=4={<134?42j278<<4>f59~w<4f2909w0=?0;152>;48808::5rs37a>5<5sW8>n63<00811g=zuk<i;7>53;294~"41j08<l5G8c48L=>?3-8<97<>;%111?>d92c99k4?::k125<722e8=k4?::a2=?=83?1<7>t$2;`>66d3A2i:6F7899'623=l2.8>847c19j60`=831b>;>50;9j637=831b>;<50;9l74`=831vn;6m:186>5<7s-92o7=?c:J;f3=O0120(?9::d48m73a2900e?8?:188m7062900e?8=:188k67a2900qo87c;291?6=8r.85n4<0b9K<g0<@1237)<85;10?!55=32h<6g=5g83>>o5>90;66g=6083>>o5>;0;66a<1g83>>{e>1n1<7;50;2x 6?d2::h7E6m6:J;<==#:>?1>k5f24d94?=n:?:1<75f27394?=n:?81<75`30d94?=zj?2n6=4::183!5>k39;o6F7b79K<=><,;=>6<jl;%111?>d>2c99k4?::k125<722c9:<4?::k127<722e8=k4?::a2=`=83?1<7>t$2;`>66d3A2i:6F7899'623=j2.8>847c79j60`=831b>;>50;9j637=831b>;<50;9l74`=831vn;7?:186>5<7s-92o7=?c:J;f3=O0120(?9::29'773=0j>0e?;i:188m7072900e?8>:188m7052900c>?i:188yg0>93:197>50z&0=f<48j1C4o84H9:;?!40=3k0(><::9a7?l42n3:17d<90;29?l4193:17d<92;29?j56n3:17pl99383>0<729q/?4m531a8L=d13A2346*=7482a<=#;;?14n;4i37e>5<<a;<;6=44i342>5<<a;<96=44o23e>5<<uk<2?7>55;294~"41j08<n5G8c48L=>?3-8<97?8;h06b?6=3`8=<7>5;h055?6=3`8=>7>5;n12b?6=3th=4l4?:483>5}#;0i1?=m4H9`5?M>?02.9;84i;%111?>d=2c99k4?::k125<722c9:<4?::k127<722e8=k4?::a2``=8381<7>t$2;`>7`>3A2i:6F7899j60c=831d?<h50;9~f3e129086=4?{%1:g?57i2B3n;5G89:8 7122;;0e?;i:188m7072900c>?i:188yg0e>3:1?7>50z&0=f<48h1C4o84H9:;?!40=3997)==5;:`=>o5=o0;66g=6183>>i49o0;66sm6dg94?5=83:p(>7l:22b?M>e>2B3455+26795a3<,:8>65m>;h06b?6=3`8=<7>5;n12b?6=3th=i:4?:483>5}#;0i1?=m4H9`5?M>?02.9;84>2:&060<?k01b>8h50;9j636=831b>;?50;9j634=831d?<h50;9~f3d3290<6=4?{%1:g?57m2B3n;5G89:8 71228no7d<:f;29?l4183:17d<91;29?l41:3:17d<93;29?l41<3:17b=>f;29?xd1j<0;6:4?:1y'7<e=;9o0D5l9;I:;<>"5?<0:hi5f24d94?=n:?:1<75f27394?=n:?81<75f27194?=n:?>1<75`30d94?=zj?o26=4;:183!5>k3;n86F7b79K<=><,;=>6?5f9683>>of93:17dk;:188k64?2900qo8ja;290?6=8r.85n4>e59K<g0<@1237)<85;08m<1=831bm<4?::kf0?6=3f9947>5;|`5a=<72=0;6=u+38a95`0<@1h=7E678:&130<53`3<6=44id694?=n;;h1<75`33:94?=zj?ho6=4::183!5>k3;n?6F7b79K<=><,;=>6?5f9683>>of93:17dlm:188m`2=831d??650;9~f3d?290?6=4?{%1:g?7b>2B3n;5G89:8 7122;1b5:4?::kf0?6=3`99n7>5;n11<?6=3th=nn4?:483>5}#;0i1=h=4H9`5?M>?02.9;84=;h;4>5<<ah;1<75fbc83>>ob<3:17b==8;29?xd1jk0;694?:1y'7<e=9l>0D5l9;I:;<>"5?<097d78:188md7=831bi94?::m06=<722wi;>850;694?6|,:3h6<k;;I:a2>N?011/>:;52:k:3?6=3`k:6=44id694?=h;;21<75rb7`0>5<3290;w)=6c;137>N?j?1C4564$356>7=];>:1=vk::|X2b7<6s:=;6pgmb;29?lc32900e<h<:188k64?2900qo8i0;291?6=8r.85n4>e69K<g0<@1237)<85;08m<1=831bm<4?::kf0?6=3`99n7>5;n11<?6=3th=j<4?:483>5}#;0i1=h94H9`5?M>?02.9;84=;h;4>5<<ah;1<75fe583>>o4:k0;66a<2983>>{e>0>1<7;50;2x 6?d28o<7E6m6:J;<==#:>?1>6g67;29?lg62900eh:50;9j77d=831d??650;9~f3?2290>6=4?{%1:g?7b?2B3n;5G89:8 7122;1b5:4?::kb5?6=3`o?6=44i20a>5<<g:836=44}c4:2?6==3:1<v*<9b82a2=O0k<0D567;%041?4<a0=1<75fa083>>ob<3:17d==b;29?j5503:17pl99683>0<729q/?4m51d58L=d13A2346*=7481?l?02900el?50;9ja1<722c8>o4?::m06=<722wi:4650;794?6|,:3h6<k8;I:a2>N?011/>:;52:k:3?6=3`k:6=44id694?=n;;h1<75`33:94?=zj?326=4::183!5>k3;n;6F7b79K<=><,;=>6?5f9683>>of93:17dk;:188m64e2900c><7:188yg0>i3:197>50z&0=f<6m>1C4o84H9:;?!40=380e4950;9je4<722cn87>5;h11f?6=3f9947>5;|`5=g<72<0;6=u+38a95`1<@1h=7E678:&130<53`3<6=44i`394?=nm=0;66g<2c83>>i4:10;66sm68a94?3=83:p(>7l:0g4?M>e>2B3455+26796>o>?3:17do>:188m`2=831b??l50;9l77>=831vn;7k:186>5<7s-92o7?j7:J;f3=O0120(?9::39j=2<722cj=7>5;hg7>5<<a:8i6=44o20;>5<<uk<i<7>54;294~"41j0:i95G8c48L=>?3-8<97<4i8594?=ni80;66gj4;29?j5503:17pl9c483>1<729q/?4m51d68L=d13A2346*=7481?l?02900el?50;9ja1<722e8>54?::a2f2=83>1<7>t$2;`>4c33A2i:6F7899'623=:2c2;7>5;hc2>5<<al>1<75`33:94?=zj>:36=4<:183!5>k32i96F7b79K<=><ah91<75f31694?=h;8l1<75rb626>5<3290;w)=6c;124>N?j?1C4564i`194?=nm00;66g<4383>>i48<0;66sm71a94?5=83:p(>7l:9`6?M>e>2B3455fa283>>o48=0;66a<1g83>>{e?931<7:50;2x 6?d2:;;7E6m6:J;<==ni:0;66gj9;29?l53:3:17b=?5;29?xd0990;6>4?:1y'7<e=0k?0D5l9;I:;<>of;3:17d=?4;29?j56n3:17pl80e83>1<729q/?4m53028L=d13A2346gn3;29?lc>2900e>:=:188k6622900qo9>4;297?6=8r.85n47b49K<g0<@1237do<:188m6632900c>?i:188yg1693:187>50z&0=f<4991C4o84H9:;?lg42900eh750;9j714=831d?=;50;9~f27?29086=4?{%1:g?>e=2B3n;5G89:8md5=831b?=:50;9l74`=831vn:?::187>5<7s-92o7=>0:J;f3=O0120el=50;9ja<<722c88?4?::m040<722wi;<m50;194?6|,:3h65l:;I:a2>N?011bm>4?::k041<722e8=k4?::a34?=83>1<7>t$2;`>6773A2i:6F7899je6<722cn57>5;h176?6=3f9;97>5;|`465<72:0;6=u+38a9<g3<@1h=7E678:kb7?6=3`9;87>5;n12b?6=3th<=i4?:583>5}#;0i1?<>4H9`5?M>?02cj?7>5;hg:>5<<a:>96=44o226>5<<uk=987>53;294~"41j03n85G8c48L=>?3`k86=44i227>5<<g:;m6=44}c515?6=<3:1<v*<9b8055=O0k<0D567;hc0>5<<al31<75f35094?=h;9?1<75rb60;>5<4290;w)=6c;:a1>N?j?1C4564i`194?=n;9>1<75`30d94?=zj>8>6=4;:183!5>k39:<6F7b79K<=><ah91<75fe883>>o4<;0;66a<0483>>{e?;h1<7=50;2x 6?d21h>7E6m6:J;<==ni:0;66g<0583>>i49o0;66sm71594?4=83:p(>7l:22:?M>e>2B3455+267964=n:<l1<75`30d94?=zj>:i6=4=:183!5>k39;56F7b79K<=><,;=>6??4i37e>5<<g:;m6=44}c53b?6=:3:1<v*<9b804<=O0k<0D567;%041?463`8>j7>5;n12b?6=3th<=>4?:383>5}#;0i1?=74H9`5?M>?02.9;84=1:k11c<722e8=k4?::a341=8381<7>t$2;`>66>3A2i:6F7899'623=:81b>8h50;9l74`=831vn:?m:181>5<7s-92o7=?9:J;f3=O0120(?9::338m73a2900c>?i:188yg16n3:1>7>50z&0=f<4801C4o84H9:;?!40=38:7d<:f;29?j56n3:17pl82283>7<729q/?4m531;8L=d13A2346*=74815>o5=o0;66a<1g83>>{e?;=1<7<50;2x 6?d2::27E6m6:J;<==#:>?1><5f24d94?=h;8l1<75rb60b>5<5290;w)=6c;13=>N?j?1C4564$356>77<a;?m6=44o23e>5<<uk=;:7>55;294~"41j0:i:5G8c48L=>?3-8<97<4i8594?=ni80;66gj4;29?l55j3:17b==8;29?xd08h0;684?:1y'7<e=9l=0D5l9;I:;<>"5?<097d78:188md7=831bi94?::k06g<722e8>54?::a35c=83?1<7>t$2;`>4c03A2i:6F7899'623=:2c2;7>5;hc2>5<<al>1<75f33`94?=h;;21<75rb631>5<2290;w)=6c;3f3>N?j?1C4564$356>7=n1>0;66gn1;29?lc32900e><m:188k64?2900qo9>6;291?6=8r.85n4>e69K<g0<@1237)<85;08m<1=831bm<4?::kf0?6=3`99n7>5;n11<?6=3th<=l4?:483>5}#;0i1=h94H9`5?M>?02.9;84=;h;4>5<<ah;1<75fe583>>o4:k0;66a<2983>>{e?8o1<7;50;2x 6?d28o<7E6m6:J;<==#:>?1>6g67;29?lg62900eh:50;9j77d=831d??650;9~f245290>6=4?{%1:g?7b?2B3n;5G89:8 7122;1b5:4?::kb5?6=3`o?6=44i20a>5<<g:836=44}c512?6==3:1<v*<9b82a2=O0k<0D567;%041?4<a0=1<75fa083>>ob<3:17d==b;29?j5503:17pl82883>0<729q/?4m51d58L=d13A2346*=7481?l?02900el?50;9ja1<722c8>o4?::m06=<722wi::750;194?6|,:3h6>>n;I:a2>N?011/>:;5339j60`=831b>;>50;9l74`=831vn;97:187>5<7s-92o7=?b:J;f3=O0120(?9::0f4?l42n3:17d<90;29?l4193:17b=>f;29?xd1?>0;684?:1y'7<e=;9i0D5l9;I:;<>"5?<0:io5+3379<f4<a;?m6=44i343>5<<a;<:6=44i341>5<<g:;m6=44}c47b?6=<3:1<v*<9b82a==O0k<0D567;%041?743`3<6=44id694?=n;=81<75`33:94?=zj?>n6=4;:183!5>k3;n46F7b79K<=><,;=>6<=4i8594?=nm=0;66g<4383>>i4:10;66sm65f94?2=83:p(>7l:0g;?M>e>2B3455+267956=n1>0;66gj4;29?l53:3:17b==8;29?xd1<j0;694?:1y'7<e=9l20D5l9;I:;<>"5?<0:?6g67;29?lc32900e>:=:188k64?2900qo8;b;290?6=8r.85n4>e99K<g0<@1237)<85;30?l?02900eh:50;9j714=831d??650;9~f32f290?6=4?{%1:g?7b02B3n;5G89:8 7122890e4950;9ja1<722c88?4?::m06=<722wi:9750;694?6|,:3h6<k7;I:a2>N?011/>:;5129j=2<722cn87>5;h176?6=3f9947>5;|`50=<72=0;6=u+38a95`><@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:>96=44o20;>5<<uk<=;7>53;294~"41j08<l5G8c48L=>?3-8<97<>;h06b?6=3`8=<7>5;n12b?6=3th=:n4?:583>5}#;0i1=h:4H9`5?M>?02.9;84=;h;4>5<<ah;1<75fe583>>i4:10;66sm67`94?2=83:p(>7l:0g7?M>e>2B3455+26796>o>?3:17do>:188m`2=831d??650;9~f30c290>6=4?{%1:g?7b;2B3n;5G89:8 7122;1b5:4?::kb5?6=3`hi6=44id694?=h;;21<75rb74;>5<3290;w)=6c;3f2>N?j?1C4564$356>7=n1>0;66gj4;29?l55j3:17b==8;29?xd1>l0;684?:1y'7<e=9l90D5l9;I:;<>"5?<097d78:188md7=831bno4?::kf0?6=3f9947>5;|`511<72:0;6=u+38a975g<@1h=7E678:&130<592c99k4?::k125<722e8=k4?::a20d=83>1<7>t$2;`>4c33A2i:6F7899'623=:2c2;7>5;hc2>5<<al>1<75`33:94?=zj??j6=4;:183!5>k3;n86F7b79K<=><,;=>6?5f9683>>of93:17dk;:188k64?2900qo8:9;290?6=8r.85n4>e59K<g0<@1237)<85;08m<1=831bm<4?::kf0?6=3f9947>5;|`51=<72=0;6=u+38a95`2<@1h=7E678:&130<53`3<6=44i`394?=nm=0;66a<2983>>{e><i1<7;50;2x 6?d28o87E6m6:J;<==#:>?1>6g67;29?lg62900eol50;9ja1<722e8>54?::a203=83>1<7>t$2;`>4c13A2i:6F7899'623=:2c2;7>5;hg7>5<<a:8i6=44o20;>5<<uk<>h7>55;294~"41j0:i>5G8c48L=>?3-8<97<4i8594?=ni80;66gmb;29?lc32900c><7:188yg35j3:1m7>50z&0=f<4<l1C4o84H9:;?_?128q8n7s+26791>of<3:17dk;:188md7=831d??650;9l77g=831b8o4?:%110?2f3g99?7>4;h6:>5<#;;>18l5a33195>=n<10;6)==4;6b?k55;3807d:8:18'772=<h1e??=53:9j03<72-9987:n;o117?2<3th>?94?:`83>5}#;0i1?9k4H9`5?M>?02P2:7?t3c8~ 7122<1bm94?::kf0?6=3`k:6=44o20;>5<<g:8j6=44i5`94?"4:=0?m6`<2283?>o313:1(><;:5c8j6442810e9650;&061<3i2d8>>4=;:k73?6=,:8?69o4n200>6=<a=<1<7*<2587e>h4::0?76sm52194?g=83:p(>7l:26f?M>e>2B3455U97826d=u-8<97;4i`694?=nm=0;66gn1;29?j5503:17b==a;29?l2e290/??:54`9m775=821b844?:%110?2f3g99?7?4;h6;>5<#;;>18l5a33196>=n<>0;6)==4;6b?k55;3907d:9:18'772=<h1e??=54:9~f1`e290j6=4?{%1:g?53m2B3n;5G89:8^<0=9r9i6p*=5e8506=#;:h14lk4$356>0=ni=0;66gj4;29?lg62900c><7:188k64f2900e9l50;&061<3i2d8>>4?;:k7=?6=,:8?69o4n200>4=<a=21<7*<2587e>h4::0976g;7;29 6432=k0b><<:298m10=83.8>94;a:l066<332wi8ko50;c94?6|,:3h6>:j;I:a2>N?011Q5;4>{2`9y!42l3<??6*<3c8;e`=#:>?196gn4;29?lc32900el?50;9l77>=831d??o50;9j0g<72-9987:n;o117?6<3`>26=4+33690d=i;;91=65f4983>!55<3>j7c==3;08?l20290/??:54`9m775=;21b8;4?:%110?2f3g99?7:4;|`7b<<72=0;6=u+38a9747<@1h=7E678:&11a<1<:1/?>l58`g8m73a2900e?8?:188m6252900c>?i:188yg35m3:1m7>50z&0=f<4<l1C4o84H9:;?_?128q8n7s+24f9211<,:9i65oj;%041?3<ah>1<75fe583>>of93:17b==8;29?j55i3:17d:m:18'772=<h1e??=50:9j0<<72-9987:n;o117?7<3`>36=4+33690d=i;;91>65f4683>!55<3>j7c==3;18?l21290/??:54`9m775=<21vn8<k:18b>5<7s-92o7=;e:J;f3=O0120V4851z1a>x"5=m0=8:5+32`9<dc<,;=>685fa583>>ob<3:17do>:188k64?2900c><n:188m1d=83.8>94;a:l066<732c?57>5$207>1g<f:886<54i5:94?"4:=0?m6`<2281?>o3?3:1(><;:5c8j6442:10e9850;&061<3i2d8>>4;;:a17e=83>1<7>t$2;`>6763A2i:6F7899'60b=>==0(>=m:9cf?l42n3:17d<90;29?l53:3:17b=>f;29?xd28;0;6l4?:1y'7<e=;=o0D5l9;I:;<>\>>3;p?o4r$37g>3233-98n76ne:&130<23`k?6=44id694?=ni80;66a<2983>>i4:h0;66g;b;29 6432=k0b><<:198m1?=83.8>94;a:l066<632c?47>5$207>1g<f:886?54i5594?"4:=0?m6`<2280?>o3>3:1(><;:5c8j6442=10qo;?1;29e?6=8r.85n4<4d9K<g0<@1237W79:0y0f?{#:<n1:9:4$21a>=gb3-8<97;4i`694?=nm=0;66gn1;29?j5503:17b==a;29?l2e290/??:54`9m775=821b844?:%110?2f3g99?7?4;h6;>5<#;;>18l5a33196>=n<>0;6)==4;6b?k55;3907d:9:18'772=<h1e??=54:9~f067290?6=4?{%1:g?5692B3n;5G89:8 73c2?>?7)=<b;:ba>o5=o0;66g=6183>>o4<;0;66a<1g83>>{e=8l1<7o50;2x 6?d2:>n7E6m6:J;<==]1?0:w>l5}%06`?03>2.8?o47ad9'623==2cj87>5;hg7>5<<ah;1<75`33:94?=h;;k1<75f4c83>!55<3>j7c==3;28?l2>290/??:54`9m775=921b854?:%110?2f3g99?7<4;h64>5<#;;>18l5a33197>=n<?0;6)==4;6b?k55;3>07pl:1d83>d<729q/?4m535g8L=d13A2346T66;3x7g<z,;?o6;:9;%10f?>fm2.9;84:;hc7>5<<al>1<75fa083>>i4:10;66a<2`83>>o3j3:1(><;:5c8j6442910e9750;&061<3i2d8>>4>;:k7<?6=,:8?69o4n200>7=<a==1<7*<2587e>h4::0876g;6;29 6432=k0b><<:598yg36l3:1m7>50z&0=f<4<l1C4o84H9:;?_?128q8n7s+24f9210<,:9i65oj;%041?3<ah>1<75fe583>>of93:17b==8;29?j55i3:17d:m:18'772=<h1e??=50:9j0<<72-9987:n;o117?7<3`>36=4+33690d=i;;91>65f4683>!55<3>j7c==3;18?l21290/??:54`9m775=<21vn8?l:18b>5<7s-92o7=;e:J;f3=O0120V4851z1a>x"5=m0=8;5+32`9<dc<,;=>685fa583>>ob<3:17do>:188k64?2900c><n:188m1d=83.8>94;a:l066<732c?57>5$207>1g<f:886<54i5:94?"4:=0?m6`<2281?>o3?3:1(><;:5c8j6442:10e9850;&061<3i2d8>>4;;:a14?=83>1<7>t$2;`>6763A2i:6F7899'60b=>=<0(>=m:9cf?l42n3:17d<90;29?l53:3:17b=>f;29?xd29h0;694?:1y'7<e=;8;0D5l9;I:;<>"5=m0=8;5+32`9<dc<a;?m6=44i343>5<<a:>96=44o23e>5<<uk?:n7>54;294~"41j08=?5G8c48L=>?3-8>h78;6:&07g<?il1b>8h50;9j636=831b?9<50;9l74`=831vn8>k:18b>5<7s-92o7=;e:J;f3=O0120V4851z1a>x"5=m0=885+32`9<dc<,;=>685fa583>>ob<3:17do>:188k64?2900c><n:188m1d=83.8>94;a:l066<732c?57>5$207>1g<f:886<54i5:94?"4:=0?m6`<2281?>o3?3:1(><;:5c8j6442:10e9850;&061<3i2d8>>4;;:a15e=83k1<7>t$2;`>62b3A2i:6F7899Y=3<6s:h1q)<:d;471>"4;k03mh5+26791>of<3:17dk;:188md7=831d??650;9l77g=831b8o4?:%110?2f3g99?7>4;h6:>5<#;;>18l5a33195>=n<10;6)==4;6b?k55;3807d:8:18'772=<h1e??=53:9j03<72-9987:n;o117?2<3th><o4?:`83>5}#;0i1?9k4H9`5?M>?02P2:7?t3c8~ 73c2?>>7)=<b;:ba>"5?<0>7do;:188m`2=831bm<4?::m06=<722e8>l4?::k7f?6=,:8?69o4n200>5=<a=31<7*<2587e>h4::0:76g;8;29 6432=k0b><<:398m11=83.8>94;a:l066<432c?:7>5$207>1g<f:886954}c73e?6=i3:1<v*<9b800`=O0k<0D567;[;5>4}4j3w/>8j56578 65e21kn7)<85;78md2=831bi94?::kb5?6=3f9947>5;n11e?6=3`>i6=4+33690d=i;;91<65f4883>!55<3>j7c==3;38?l2?290/??:54`9m775=:21b8:4?:%110?2f3g99?7=4;h65>5<#;;>18l5a33190>=zj<:<6=4;:183!5>k39:=6F7b79K<=><,;?o6;::;%10f?>fm2c99k4?::k125<722c88?4?::m05c<722wi9=650;694?6|,:3h6>?>;I:a2>N?011/>8j56578 65e21kn7d<:f;29?l4183:17d=;2;29?j56n3:17pl:0883>1<729q/?4m53008L=d13A2346*=5e8500=#;:h14lk4i37e>5<<a;<;6=44i261>5<<g:;m6=44}c706?6=13:1<v*<9b800a=O0k<0D567;%041?5<a=;1<75f4383>>o3;3:17d:;:188md7=831bm94?::kf0?6=3f9947>5;n11=?6=3th>>l4?:883>5}#;0i1?9j4H9`5?M>?02.9;84<;h62>5<<a=81<75f4283>>o3<3:17do>:188md2=831bi94?::m06=<722e8>44?::a27g=83>1<7>t$2;`>66e3A2i:6F7899'623=:;1b>8h50;9j636=831b>;?50;9l74`=831vn9h7:187>5<7s-92o7?j6:J;f3=O0120(?;k:760?!54j32jj6*=7481?l?02900eh:50;9j77d=831d??650;9~f07?290?6=4?{%1:g?7b>2B3n;5G89:8 73c2?>=7)=<b;:bb>"5?<097d78:188m`2=831b??l50;9l77>=831vn8>9:187>5<7s-92o7?j6:J;f3=O0120(?;k:766?!54j32jj6*=7481?l?02900eh:50;9j77d=831d??650;9~f34d290?6=4?{%1:g?7b>2B3n;5G89:8 7122;1b5:4?::kf0?6=3`99n7>5;n11<?6=3th=>o4?:583>5}#;0i1=h84H9`5?M>?02.9;84=;h;4>5<<al>1<75f33`94?=h;;21<75rb5d4>5<3290;w)=6c;3f2>N?j?1C4564$356>7=n1>0;66gj4;29?l55j3:17b==8;29?xd3n?0;694?:1y'7<e=9l<0D5l9;I:;<>"5?<097d78:188m`2=831b??l50;9l77>=831vn;<6:186>5<7s-92o7?j7:J;f3=O0120(?9::39j=2<722cj=7>5;hg7>5<<a:8i6=44o20;>5<<uk<9i7>55;294~"41j0:i:5G8c48L=>?3-8<97<4i8594?=ni80;66gj4;29?l55j3:17b==8;29?xd1:m0;684?:1y'7<e=9l=0D5l9;I:;<>"5?<097d78:188md7=831bi94?::k06g<722e8>54?::a1dg=83?1<7>t$2;`>4c03A2i:6F7899'623=:2c2;7>5;hc2>5<<al>1<75f33`94?=h;;21<75rb4c4>5<2290;w)=6c;3f3>N?j?1C4564$356>7=n1>0;66gn1;29?lc32900e><m:188k64?2900qo;n3;291?6=8r.85n4>e69K<g0<@1237)<85;08m<1=831bm<4?::kf0?6=3`99n7>5;n11<?6=3th>5k4?:483>5}#;0i1=h94H9`5?M>?02.9;84=;h;4>5<<ah;1<75fe583>>o4:k0;66a<2983>>{e=0h1<7;50;2x 6?d28o<7E6m6:J;<==#:>?1>6g67;29?lg62900eh:50;9j77d=831d??650;9~f0?0290>6=4?{%1:g?7b?2B3n;5G89:8 7122;1b5:4?::kb5?6=3`o?6=44i20a>5<<g:836=44}c7:7?6==3:1<v*<9b82a2=O0k<0D567;%041?4<a0=1<75fa083>>ob<3:17d==b;29?j5503:17pl:8g83>0<729q/?4m51d58L=d13A2346*=7481?l?02900el?50;9ja1<722c8>o4?::m06=<722wi95l50;794?6|,:3h6<k8;I:a2>N?011/>:;52:k:3?6=3`k:6=44id694?=n;;h1<75`33:94?=zj<2<6=4::183!5>k3;n;6F7b79K<=><,;=>6?5f9683>>of93:17dk;:188m64e2900c><7:188yg3fj3:1>7>50z&0=f<4801C4o84H9:;?!40=38:7d<:f;29?j56n3:17pl:a983>7<729q/?4m531;8L=d13A2346*=74815>o5=o0;66a<1g83>>{e=h>1<7<50;2x 6?d2::27E6m6:J;<==#:>?1><5f24d94?=h;8l1<75rb4c3>5<5290;w)=6c;13=>N?j?1C4564$356>77<a;?m6=44o23e>5<<uk?2o7>52;294~"41j08<45G8c48L=>?3-8<97<>;h06b?6=3f9:j7>5;|`6==<72;0;6=u+38a975?<@1h=7E678:&130<592c99k4?::m05c<722wi94:50;094?6|,:3h6>>6;I:a2>N?011/>:;5209j60`=831d?<h50;9~f0?729096=4?{%1:g?5712B3n;5G89:8 7122;;0e?;i:188k67a2900qo;7c;296?6=8r.85n4<089K<g0<@1237)<85;02?l42n3:17b=>f;29?xd2010;6?4?:1y'7<e=;930D5l9;I:;<>"5?<09=6g=5g83>>i49o0;66sm5`a94?5=83:p(>7l:9`6?M>e>2B3455fa283>>o48=0;66a<1g83>>{e=h<1<7:50;2x 6?d2:;;7E6m6:J;<==ni:0;66gj9;29?l53:3:17b=?5;29?xd2i00;6>4?:1y'7<e=0k?0D5l9;I:;<>of;3:17d=?4;29?j56n3:17pl:a383>1<729q/?4m53028L=d13A2346gn3;29?lc>2900e>:=:188k6622900qo;n5;297?6=8r.85n47b49K<g0<@1237do<:188m6632900c>?i:188yg3>m3:187>50z&0=f<4991C4o84H9:;?lg42900eh750;9j714=831d?=;50;9~f0g629086=4?{%1:g?>e=2B3n;5G89:8md5=831b?=:50;9l74`=831vn87n:187>5<7s-92o7=>0:J;f3=O0120el=50;9ja<<722c88?4?::m040<722wi94j50;194?6|,:3h65l:;I:a2>N?011bm>4?::k041<722e8=k4?::a1<0=83>1<7>t$2;`>6773A2i:6F7899je6<722cn57>5;h176?6=3f9;97>5;|`6=<<72:0;6=u+38a9<g3<@1h=7E678:kb7?6=3`9;87>5;n12b?6=3th>5?4?:583>5}#;0i1?<>4H9`5?M>?02cj?7>5;hg:>5<<a:>96=44o226>5<<uk?297>53;294~"41j03n85G8c48L=>?3`k86=44i227>5<<g:;m6=44}c7;a?6=<3:1<v*<9b8055=O0k<0D567;hc0>5<<al31<75f35094?=h;9?1<75rb4;2>5<4290;w)=6c;:a1>N?j?1C4564i`194?=n;9>1<75`30d94?=zj<2j6=4;:183!5>k39:<6F7b79K<=><ah91<75fe883>>o4<;0;66a<0483>>{e=1n1<7=50;2x 6?d21h>7E6m6:J;<==ni:0;66g<0583>>i49o0;66sm59494?2=83:p(>7l:233?M>e>2B3455fa283>>ob13:17d=;2;29?j57=3:17pl:8883>6<729q/?4m58c78L=d13A2346gn3;29?l57<3:17b=>f;29?xd2ml0;684?:1y'7<e=9l=0D5l9;I:;<>"5?<097d78:188md7=831bi94?::k06g<722e8>54?::a1`d=83?1<7>t$2;`>4c03A2i:6F7899'623=:2c2;7>5;hc2>5<<al>1<75f33`94?=h;;21<75rb4g4>5<2290;w)=6c;3f3>N?j?1C4564$356>7=n1>0;66gn1;29?lc32900e><m:188k64?2900qo;j3;291?6=8r.85n4>e69K<g0<@1237)<85;08m<1=831bm<4?::kf0?6=3`99n7>5;n11<?6=3th>hk4?:483>5}#;0i1=h94H9`5?M>?02.9;84=;h;4>5<<ah;1<75fe583>>o4:k0;66a<2983>>{e=mh1<7;50;2x 6?d28o<7E6m6:J;<==#:>?1>6g67;29?lg62900eh:50;9j77d=831d??650;9~f0b0290>6=4?{%1:g?7b?2B3n;5G89:8 7122;1b5:4?::kb5?6=3`o?6=44i20a>5<<g:836=44}c7g7?6==3:1<v*<9b82a2=O0k<0D567;%041?4<a0=1<75fa083>>ob<3:17d==b;29?j5503:17pl:cg83>0<729q/?4m51d58L=d13A2346*=7481?l?02900el?50;9ja1<722c8>o4?::m06=<722wi9nl50;794?6|,:3h6<k8;I:a2>N?011/>:;52:k:3?6=3`k:6=44id694?=n;;h1<75`33:94?=zj<om6=4=:183!5>k39;56F7b79K<=><,;=>6??4i37e>5<<g:;m6=44}c7fg?6=:3:1<v*<9b804<=O0k<0D567;%041?463`8>j7>5;n12b?6=3th>i54?:383>5}#;0i1?=74H9`5?M>?02.9;84=1:k11c<722e8=k4?::a1`2=8381<7>t$2;`>66>3A2i:6F7899'623=:81b>8h50;9l74`=831vn8k?:181>5<7s-92o7=?9:J;f3=O0120(?9::338m73a2900c>?i:188yg3ck3:1>7>50z&0=f<4801C4o84H9:;?!40=38:7d<:f;29?j56n3:17pl:d983>7<729q/?4m531;8L=d13A2346*=74815>o5=o0;66a<1g83>>{e=m>1<7<50;2x 6?d2::27E6m6:J;<==#:>?1><5f24d94?=h;8l1<75rb4f3>5<5290;w)=6c;13=>N?j?1C4564$356>77<a;?m6=44o23e>5<<uk?ho7>52;294~"41j08<45G8c48L=>?3-8<97<>;h06b?6=3f9:j7>5;|`6b5<72:0;6=u+38a9<g3<@1h=7E678:kb7?6=3`9;87>5;n12b?6=3th>il4?:583>5}#;0i1?<>4H9`5?M>?02cj?7>5;hg:>5<<a:>96=44o226>5<<uk?nh7>53;294~"41j03n85G8c48L=>?3`k86=44i227>5<<g:;m6=44}c7f2?6=<3:1<v*<9b8055=O0k<0D567;hc0>5<<al31<75f35094?=h;9?1<75rb4g:>5<4290;w)=6c;:a1>N?j?1C4564i`194?=n;9>1<75`30d94?=zj<o96=4;:183!5>k39:<6F7b79K<=><ah91<75fe883>>o4<;0;66a<0483>>{e=l?1<7=50;2x 6?d21h>7E6m6:J;<==ni:0;66g<0583>>i49o0;66sm5eg94?2=83:p(>7l:233?M>e>2B3455fa283>>ob13:17d=;2;29?j57=3:17pl:e083>6<729q/?4m58c78L=d13A2346gn3;29?l57<3:17b=>f;29?xd2lh0;694?:1y'7<e=;8:0D5l9;I:;<>of;3:17dk6:188m6252900c>>::188yg3cl3:1?7>50z&0=f<?j<1C4o84H9:;?lg42900e>>;:188k67a2900qo;k6;290?6=8r.85n4<119K<g0<@1237do<:188m`?=831b?9<50;9l753=831vn8j6:180>5<7s-92o76m5:J;f3=O0120el=50;9j752=831d?<h50;9~f0b5290?6=4?{%1:g?5682B3n;5G89:8md5=831bi44?::k007<722e8<84?::a1a3=8391<7>t$2;`>=d23A2i:6F7899je6<722c8<94?::m05c<722wi9nk50;694?6|,:3h6>??;I:a2>N?011bm>4?::kf=?6=3`9?>7>5;n131?6=3th>h<4?:283>5}#;0i14o;4H9`5?M>?02cj?7>5;h130?6=3f9:j7>5;|`6gd<72=0;6=u+38a9746<@1h=7E678:kb7?6=3`o26=44i261>5<<g::>6=44}c7``?6=;3:1<v*<9b8;f0=O0k<0D567;hc0>5<<a::?6=44o23e>5<<uk?<=7>54;294~"41j08<o5G8c48L=>?3-8<9777;h06b?6=3`8=<7>5;h055?6=3f9:j7>5;|`62`<72=0;6=u+38a975d<@1h=7E678:&130<>02c99k4?::k125<722c9:<4?::m05c<722wi9;l50;694?6|,:3h6>>m;I:a2>N?011/>:;5999j60`=831b>;>50;9j637=831d?<h50;9~f00?290?6=4?{%1:g?57j2B3n;5G89:8 7122020e?;i:188m7072900e?8>:188k67a2900qo;95;290?6=8r.85n4<0c9K<g0<@1237)<85;;;?l42n3:17d<90;29?l4193:17b=>f;29?xd2>;0;694?:1y'7<e=;9h0D5l9;I:;<>"5?<0246g=5g83>>o5>90;66g=6083>>i49o0;66sm54d94?2=83:p(>7l:22a?M>e>2B3455+2679===n:<l1<75f27294?=n:?;1<75`30d94?=zj<?h6=4;:183!5>k39;n6F7b79K<=><,;=>6464i37e>5<<a;<;6=44i342>5<<g:;m6=44}c76=?6=<3:1<v*<9b804g=O0k<0D567;%041???3`8>j7>5;h054?6=3`8==7>5;n12b?6=3th>9;4?:583>5}#;0i1?=l4H9`5?M>?02.9;8468:k11c<722c9:=4?::k124<722e8=k4?::a1ce=8391<7>t$2;`>66f3A2i:6F7899'623=;o1/??;58ba8m73a2900e?8?:188k67a2900qo;ib;297?6=8r.85n4<0`9K<g0<@1237)<85;1e?!55=32ho6g=5g83>>o5>90;66a<1g83>>{e=<>1<7650;2x 6?d2:>h7E6m6:J;<==#:>?1?6g;1;29?l252900e9=50;9j01<722cj=7>5;hc7>5<<al>1<75`33:94?=zj<>j6=4;:183!5>k3;n86F7b79K<=><,;=>6?5f9683>>of93:17dk;:188k64?2900qo;;9;290?6=8r.85n4>e59K<g0<@1237)<85;08m<1=831bm<4?::kf0?6=3f9947>5;|`60=<72=0;6=u+38a95`2<@1h=7E678:&130<53`3<6=44i`394?=nm=0;66a<2983>>{e===1<7:50;2x 6?d28o?7E6m6:J;<==#:>?1>6g67;29?lg62900eh:50;9l77>=831vn8:9:187>5<7s-92o7?j4:J;f3=O0120(?9::39j=2<722cj=7>5;hg7>5<<g:836=44}c771?6=<3:1<v*<9b82a1=O0k<0D567;%041?4<a0=1<75fa083>>ob<3:17b==8;29?xd2=:0;694?:1y'7<e=9l>0D5l9;I:;<>"5?<097d78:188md7=831bi94?::m06=<722wi98<50;694?6|,:3h6<k;;I:a2>N?011/>:;52:k:3?6=3`k:6=44id694?=h;;21<75rb472>5<3290;w)=6c;3f0>N?j?1C4564$356>7=n1>0;66gn1;29?lc32900c><7:188yg3283:187>50z&0=f<6m=1C4o84H9:;?!40=380e4950;9je4<722cn87>5;n11<?6=3th>8k4?:583>5}#;0i1=h:4H9`5?M>?02.9;84=;h;4>5<<ah;1<75fe583>>i4:10;66sm55g94?2=83:p(>7l:0g7?M>e>2B3455+26796>o>?3:17do>:188m`2=831d??650;9~f02c290?6=4?{%1:g?7b<2B3n;5G89:8 7122;1b5:4?::kb5?6=3`o?6=44o20;>5<<uk??o7>54;294~"41j0:i95G8c48L=>?3-8<97<4i8594?=ni80;66gj4;29?j5503:17pl:4c83>1<729q/?4m51d68L=d13A2346*=7481?l?02900el?50;9ja1<722e8>54?::a112=83>1<7>t$2;`>4c33A2i:6F7899'623=:2c2;7>5;hc2>5<<al>1<75`33:94?=zj<=;6=4;:183!5>k3;n:6F7b79K<=><,;=>6?5f9683>>ob<3:17d==b;29?j5503:17pl:7383>1<729q/?4m51d48L=d13A2346*=7481?l?02900eh:50;9j77d=831d??650;9~f00c290?6=4?{%1:g?7b>2B3n;5G89:8 7122;1b5:4?::kf0?6=3`99n7>5;n11<?6=3th>:k4?:583>5}#;0i1=h84H9`5?M>?02.9;84=;h;4>5<<al>1<75f33`94?=h;;21<75rb44b>5<3290;w)=6c;3f2>N?j?1C4564$356>7=n1>0;66gj4;29?l55j3:17b==8;29?xd2>j0;694?:1y'7<e=9l<0D5l9;I:;<>"5?<097d78:188m`2=831b??l50;9l77>=831vn888:187>5<7s-92o7?j6:J;f3=O0120(?9::39j=2<722cn87>5;h11f?6=3f9947>5;|`62<<72=0;6=u+38a95`0<@1h=7E678:&130<53`3<6=44id694?=n;;h1<75`33:94?=zj<<?6=4;:183!5>k3;n:6F7b79K<=><,;=>6?5f9683>>ob<3:17d==b;29?j5503:17pl:6783>1<729q/?4m51d48L=d13A2346*=7481?l?02900eh:50;9j77d=831d??650;9~f006290?6=4?{%1:g?7b>2B3n;5G89:8 7122;1b5:4?::kf0?6=3`99n7>5;n11<?6=3th>:>4?:583>5}#;0i1=h84H9`5?M>?02.9;84=;h;4>5<<al>1<75f33`94?=h;;21<75rb47f>5<3290;w)=6c;3f2>N?j?1C4564$356>7=n1>0;66gj4;29?l55j3:17b==8;29?xd2>90;694?:1y'7<e=9l<0D5l9;I:;<>"5?<097d78:188m`2=831b??l50;9l77>=831vn8;m:187>5<7s-92o7?j6:J;f3=O0120(?9::39j=2<722cn87>5;h11f?6=3f9947>5;|`61a<72=0;6=u+38a95`0<@1h=7E678:&130<53`3<6=44id694?=n;;h1<75`33:94?=zj<?36=4;:183!5>k3;n:6F7b79K<=><,;=>6?5f9683>>ob<3:17d==b;29?j5503:17pl:5`83>1<729q/?4m51d48L=d13A2346*=7481?l?02900eh:50;9j77d=831d??650;9~f032290?6=4?{%1:g?7b>2B3n;5G89:8 7122;1b5:4?::kf0?6=3`99n7>5;n11<?6=3th>9:4?:583>5}#;0i1=h84H9`5?M>?02.9;84=;h;4>5<<al>1<75f33`94?=h;;21<75rb4dg>5<69381=?uG89:8 6?d21oj7W79:0y22?{#0131?494i37b>5<#;;>1>874n200>5=<a;>o6=4+336960?<f:886<54i361>5<#;;>1>874n200>7=<a;9<6=4+336960?<f:886>54i30`>5<#;;>1>874n200>1=<a;8:6=4+336960?<f:886854i335>5<#;;>1>874n200>3=<a;:i6=4+336960?<f:886:54i323>5<#;;>1>874n200>==<a8l>6=4+336960?<f:886454icc94?=n;:k1<75f37794?=n;?>1<75f37494?=h;?=1<75`24`94?=e0k21<7?50;2x 6?d21387E6m6:J;<==h;;;1<75rb3d`>5<6k3h1>;uG89:8 6?d21l;7W79:0y17?{#:<n1?=h4i27b>5<#;;>1?874n200>5=<a:?36=4+336970?<f:886<54i274>5<#;;>1?874n200>7=<a:?=6=4+336970?<f:886>54i276>5<#;;>1?874n200>1=<a:??6=4+336970?<f:886854i270>5<#;;>1?874n200>3=<a:?96=4+336970?<f:886:54i272>5<#;;>1?874n200>==<a:?;6=4+336970?<f:886454i240>5<#;;>1?874n200>d=<a:<96=4+336970?<f:886o54i242>5<#;;>1?874n200>f=<a:<;6=4+336970?<f:886i54i27e>5<#;;>1?874n200>`=<a:?n6=4+336970?<f:886k54i27g>5<#;;>1?874n200>46<3`9>o7>5$207>63>3g99?7?>;:k01g<72-9987=:9:l066<6:21b?9h50;&061<4=01e??=51298mgg=831b?>o50;9j5c2=831b?;;50;9j732=831b?;850;9l731=831d>8l50;9a<g>=83;1<7>t$2;`>=?43A2i:6F7899l777=831vn5l8:182>5<7s-92o7<:c:J;f3=O0120c<h<:188yg>>:3:1m7>50z&0=f<4<l1C4o84H9:;?_?128q8n7s+32`9<dc<,;=>685fa583>>ob<3:17do>:188k64?2900c><n:188m1d=83.8>94;a:l066<732c?57>5$207>1g<f:886<54i5:94?"4:=0?m6`<2281?>o3?3:1(><;:5c8j6442:10e9850;&061<3i2d8>>4;;:a<<7=83k1<7>t$2;`>62b3A2i:6F7899Y=3<6s:h1q)=<b;:ba>"5?<0>7do;:188m`2=831bm<4?::m06=<722e8>l4?::k7f?6=,:8?69o4n200>5=<a=31<7*<2587e>h4::0:76g;8;29 6432=k0b><<:398m11=83.8>94;a:l066<432c?:7>5$207>1g<f:886954}c::4?6=i3:1<v*<9b800`=O0k<0D567;[;5>4}4j3w/?>l58`g8 7122<1bm94?::kf0?6=3`k:6=44o20;>5<<g:8j6=44i5`94?"4:=0?m6`<2283?>o313:1(><;:5c8j6442810e9650;&061<3i2d8>>4=;:k73?6=,:8?69o4n200>6=<a=<1<7*<2587e>h4::0?76sm89d94?g=83:p(>7l:26f?M>e>2B3455U97826d=u-98n76ne:&130<23`k?6=44id694?=ni80;66a<2983>>i4:h0;66g;b;29 6432=k0b><<:198m1?=83.8>94;a:l066<632c?47>5$207>1g<f:886?54i5594?"4:=0?m6`<2280?>o3>3:1(><;:5c8j6442=10qo67d;290?6=8r.85n4<119K<g0<@1237)=<b;:ba>of;3:17dk6:188m6252900c>>::188yg>?k3:187>50z&0=f<4991C4o84H9:;?!54j32ji6gn3;29?lc>2900e>:=:188k6622900qo67b;290?6=8r.85n4<119K<g0<@1237)=<b;:ba>of;3:17dk6:188m6252900c>>::188yg>?i3:187>50z&0=f<4991C4o84H9:;?!54j32ji6gn3;29?lc>2900e>:=:188k6622900qo<ib;290?6=8r.85n4<119K<g0<@1237)=<b;:bb>of;3:17dk6:188m6252900c>>::188yv52i3:1>vP<5`9><<4=<k1v>;7:181[5202735?4;9:p701=838pR>;8;<::6?2?3ty89;4?:3y]700<51396994}r161?6=:rT89852880903=z{:??6=4={_160>;?180?n6s|34194?4|V:?870661;6:?xu4=;0;6?uQ34089=?62=20q~=:1;296~X4=81644?5469~w6372909wS=:0:?;=4<3>2wx?;=50;0xZ6043422<7:m;|q027<72;qU?;<4=9;3>1?<uz9==7>52z\024=:00:1855rs243>5<5sW9=<63791873>{t;<l1<7<t^27e?8>>83>=7p}<5d83>7}Y;<o0156i:5`8yv52l3:1>vP<5e9><=`=<01v>;l:181[52k2734k4;8:p70d=838pR>;m;<:;b?203ty88k4?:3y]71`<512m6984}r151?6==rT8:8528809e1=:00;1m9528829e1=:01l1m95rs247>5<2sW9=8637938b5>;?180j=637918b5>;?0o0j=6s|37494?4|V:<=70662;g7?xu>:=0;6?u2880977><512o6>:=;|q:5g<72;q644<533c89=?62l>0q~7=3;296~;?1808>55289a9714<uz3:m7>52z?;=4<4:h1644>5e59~w<452909w0660;11<>;?0k088?5rs83:>5<5s422<7==a:?;<c<b<2wx5??50;0x9=>a2:837067a;176>{t;?=1<7<t^244?8>?n399m6s|90d94?4|512o6>>:;<0ef?g43ty2=h4?:3y><=b=i:1645m53178yv?6l3:1>v378b8b7>;?0k08<85rs83`>5<5s423n7o<;<:;e?57=2wx>8l50;0xZ73e348mn7=?5:p5c2=839p15l7:202?8>?i3k870<ib;176>{t;8<1<78t=9`4>4`43423h7k6;<:;g?c>3423n7k6;<:;e?c>348mn7k6;|p60g=838pR?;n;<0eg?51;2wx>9j50;0xZ72c348mo7=92:p614=838pR?:=;<0eg?5192wx>>950;0xZ750348mo7=90:p67e=838pR?<l;<0eg?52n2wx>??50;0xZ746348mo7=:e:p640=838pR??9;<0eg?52l2wx>=l50;0xZ76e348mo7=:c:p656=838pR?>?;<0eg?52j2wx=k;50;0xZ4`2348mo7=;f:pfd<72;qUnl522ga9fd=z{:9j6=4={_10e>;5nj08?l5rs246>5<5sW9=963=fb8020=z{:<?6=4={_150>;5nj08:95rs245>5<5sW9=:63=fb8023=z{:<<6=4={_153>;5nj08::5rs37a>5<5sW8>n63=fb811g=z{0:;6=4l{<:a<?559279jn4<5`9>6ce=;<201?hl:274?84ak39>:63=fb8010=::oi1?8:4=3d`>634348mo7=:2:?1bf<4=816>km5342897`d28l?7psm5gg94?762;0:>vF7899'7<e=0lk0V4851z35>x"?00085:5f24c94?"4:=09945a33194>=n:=n1<7*<25811<=i;;91=65f25094?"4:=09945a33196>=n::=1<7*<25811<=i;;91?65f23a94?"4:=09945a33190>=n:;;1<7*<25811<=i;;91965f20494?"4:=09945a33192>=n:9h1<7*<25811<=i;;91;65f21294?"4:=09945a3319<>=n9o?1<7*<25811<=i;;91565fb`83>>o4;h0;66g<6483>>o4>=0;66g<6783>>i4>>0;66a=5c83>>d?j10;6<4?:1y'7<e=0090D5l9;I:;<>i4:80;66sm2ga94?7d2k09:vF7899'7<e=0o:0V4851z00>x"5=m08<k5f34c94?"4:=08945a33194>=n;<21<7*<25801<=i;;91=65f34594?"4:=08945a33196>=n;<<1<7*<25801<=i;;91?65f34794?"4:=08945a33190>=n;<>1<7*<25801<=i;;91965f34194?"4:=08945a33192>=n;<81<7*<25801<=i;;91;65f34394?"4:=08945a3319<>=n;<:1<7*<25801<=i;;91565f37194?"4:=08945a3319e>=n;?81<7*<25801<=i;;91n65f37394?"4:=08945a3319g>=n;?:1<7*<25801<=i;;91h65f34d94?"4:=08945a3319a>=n;<o1<7*<25801<=i;;91j65f34f94?"4:=08945a331955=<a:?h6=4+336970?<f:886<?4;h16f?6=,:8?6>;6;o117?7532c88k4?:%110?5212d8>>4>3:9jfd<722c8?l4?::k2b1<722c8:84?::k021<722c8:;4?::m022<722e99o4?::`;f=<7280;6=u+38a9<<5<@1h=7E678:m064<722wi4o950;394?6|,:3h6?;l;I:a2>N?011d=k=50;9~f=?5290j6=4?{%1:g?53m2B3n;5G89:8^<0=9r9i6p*<3c8;e`=#:>?196gn4;29?lc32900el?50;9l77>=831d??o50;9j0g<72-9987:n;o117?6<3`>26=4+33690d=i;;91=65f4983>!55<3>j7c==3;08?l20290/??:54`9m775=;21b8;4?:%110?2f3g99?7:4;|`;=4<72h0;6=u+38a971c<@1h=7E678:X:2?7|;k0v(>=m:9cf?!40=3?0el:50;9ja1<722cj=7>5;n11<?6=3f99m7>5;h6a>5<#;;>18l5a33194>=n<00;6)==4;6b?k55;3;07d:7:18'772=<h1e??=52:9j02<72-9987:n;o117?5<3`>=6=4+33690d=i;;91865rb9;3>5<f290;w)=6c;17a>N?j?1C4564Z8495~5e2t.8?o47ad9'623==2cj87>5;hg7>5<<ah;1<75`33:94?=h;;k1<75f4c83>!55<3>j7c==3;28?l2>290/??:54`9m775=921b854?:%110?2f3g99?7<4;h64>5<#;;>18l5a33197>=n<?0;6)==4;6b?k55;3>07pl78g83>d<729q/?4m535g8L=d13A2346T66;3x7g<z,:9i65oj;%041?3<ah>1<75fe583>>of93:17b==8;29?j55i3:17d:m:18'772=<h1e??=50:9j0<<72-9987:n;o117?7<3`>36=4+33690d=i;;91>65f4683>!55<3>j7c==3;18?l21290/??:54`9m775=<21vn56k:187>5<7s-92o7=>0:J;f3=O0120(>=m:9cf?lg42900eh750;9j714=831d?=;50;9~f=>d290?6=4?{%1:g?5682B3n;5G89:8 65e21kn7do<:188m`?=831b?9<50;9l753=831vn56m:187>5<7s-92o7=>0:J;f3=O0120(>=m:9cf?lg42900eh750;9j714=831d?=;50;9~f=>f290?6=4?{%1:g?5682B3n;5G89:8 65e21kn7do<:188m`?=831b?9<50;9l753=831vn?hm:187>5<7s-92o7=>0:J;f3=O0120(>=m:9ce?lg42900eh750;9j714=831d?=;50;9~w63f2909wS=:a:?;=7<3j2wx?8650;0xZ63?3422>7:6;|q012<72;qU?894=9;1>1><uz9>:7>52z\013=:00818:5rs276>5<5sW9>963793872>{t;<>1<7<t^277?8>>93>i7p}<5283>7}Y;<90157>:5;8yv52:3:1>vP<539><<7=<11v>;>:181[5292735<4;7:p706=838pR>;?;<::5?213ty8:>4?:3y]735<513;69l4}r156?6=:rT8:?5288290<=z{:<:6=4={_155>;?190?46s|37294?4|V:<;70660;64?xu4=o0;6?uQ34d89=?72=<0q~=:e;296~X4=l1645h54c9~w63c2909wS=:d:?;<c<312wx?8m50;0xZ63d3423j7:7;|q01g<72;qU?8l4=9:e>11<uz9?j7>52z\00c=:01l18;5rs246>5<2sW9=9637938b0>;?180j8637918b0>;?0o0j86s|37694?3|V:<?70662;c2?8>>93k:70660;c2?8>?n3k:7p}<6783>7}Y;?<0157=:d68yv?5<3:1>v3793806==:01n1?9<4}r;2f?6=:r735?4<2`9><<7=m=1v4<<:1818>>939946378b8007=z{0;j6=4={<::5?55i2735=4j4:p=74=838p157?:20;?8>?j39?>6s|90;94?4|513;6><n;<:;b?c33ty2><4?:3y><=`=;;20156n:261?xu4>>0;6?uQ37589=>a2:8j7p}61g83>7}:01n1?=;4=3da>d5<uz3:i7>52z?;<a<f;2734n4<049~w<7c2909w067c;c0?8>?j39;96s|90a94?4|512i6l=4=9:b>6623ty99o4?:3y]60d<5;li6>>:;|q2b1<72:q64o6533389=>f2h901?hm:261?xu49?0;6;u28c595c5<512o6h74=9:`>`?<512i6h74=9:b>`?<5;li6h74}|q11d<72;qU>8o4=3d`>6043ty98i4?:3y]61b<5;lh6>8=;|q107<72;qU>9<4=3d`>6063ty9?:4?:3y]661<5;lh6>8?;|q16f<72;qU>?m4=3d`>63a3ty9><4?:3y]677<5;lh6>;j;|q153<72;qU><84=3d`>63c3ty9<o4?:3y]65d<5;lh6>;l;|q145<72;qU>=>4=3d`>63e3ty:j84?:3y]5c3<5;lh6>:i;|qae?6=:rTim63=fb8ae>{t;:k1<7<t^21b?84ak398m6s|37794?4|V:<>70<ic;151>{t;?>1<7<t^247?84ak39=86s|37494?4|V:<=70<ic;152>{t;?=1<7<t^244?84ak39=;6s|24`94?4|V;?i70<ic;06f>{t19:1<7mt=9`;>646348mo7=:a:?1bf<4=116>km5345897`d2:?=70<ic;161>;5nj0899522ga9705<5;lh6>;=;<0eg?529279jn4<519>6ce=9o>0qpl:fg83>47=:3;9wE678:&0=f<?mh1Q5;4>{049y!>?1392;6g=5`83>!55<38>56`<2283?>o5<m0;6)==4;06=>h4::0:76g=4383>!55<38>56`<2281?>o5;>0;6)==4;06=>h4::0876g=2b83>!55<38>56`<2287?>o5:80;6)==4;06=>h4::0>76g=1783>!55<38>56`<2285?>o58k0;6)==4;06=>h4::0<76g=0183>!55<38>56`<228;?>o6n<0;6)==4;06=>h4::0276gma;29?l54i3:17d=95;29?l51<3:17d=96;29?j51?3:17b<:b;29?g>e03:1=7>50z&0=f<?1:1C4o84H9:;?j5593:17pl=fb83>4e=j38=wE678:&0=f<?n91Q5;4>{319y!42l39;j6g<5`83>!55<39>56`<2283?>o4=10;6)==4;16=>h4::0:76g<5683>!55<39>56`<2281?>o4=?0;6)==4;16=>h4::0876g<5483>!55<39>56`<2287?>o4==0;6)==4;16=>h4::0>76g<5283>!55<39>56`<2285?>o4=;0;6)==4;16=>h4::0<76g<5083>!55<39>56`<228;?>o4=90;6)==4;16=>h4::0276g<6283>!55<39>56`<228b?>o4>;0;6)==4;16=>h4::0i76g<6083>!55<39>56`<228`?>o4>90;6)==4;16=>h4::0o76g<5g83>!55<39>56`<228f?>o4=l0;6)==4;16=>h4::0m76g<5e83>!55<39>56`<22824>=n;<i1<7*<25801<=i;;91=<54i27a>5<#;;>1?874n200>44<3`9?j7>5$207>63>3g99?7?<;:kae?6=3`98m7>5;h3e0?6=3`9=97>5;h150?6=3`9=:7>5;n153?6=3f8>n7>5;c:a<?6=93:1<v*<9b8;=6=O0k<0D567;n115?6=3th3n:4?:083>5}#;0i1>8m4H9`5?M>?02e:j>4?::a<<4=83k1<7>t$2;`>62b3A2i:6F7899Y=3<6s:h1q)=<b;:ba>"5?<0>7do;:188m`2=831bm<4?::m06=<722e8>l4?::k7f?6=,:8?69o4n200>5=<a=31<7*<2587e>h4::0:76g;8;29 6432=k0b><<:398m11=83.8>94;a:l066<432c?:7>5$207>1g<f:886954}c::5?6=i3:1<v*<9b800`=O0k<0D567;[;5>4}4j3w/?>l58`g8 7122<1bm94?::kf0?6=3`k:6=44o20;>5<<g:8j6=44i5`94?"4:=0?m6`<2283?>o313:1(><;:5c8j6442810e9650;&061<3i2d8>>4=;:k73?6=,:8?69o4n200>6=<a=<1<7*<2587e>h4::0?76sm88294?g=83:p(>7l:26f?M>e>2B3455U97826d=u-98n76ne:&130<23`k?6=44id694?=ni80;66a<2983>>i4:h0;66g;b;29 6432=k0b><<:198m1?=83.8>94;a:l066<632c?47>5$207>1g<f:886?54i5594?"4:=0?m6`<2280?>o3>3:1(><;:5c8j6442=10qo67f;29e?6=8r.85n4<4d9K<g0<@1237W79:0y0f?{#;:h14lk4$356>0=ni=0;66gj4;29?lg62900c><7:188k64f2900e9l50;&061<3i2d8>>4?;:k7=?6=,:8?69o4n200>4=<a=21<7*<2587e>h4::0976g;7;29 6432=k0b><<:298m10=83.8>94;a:l066<332wi45j50;694?6|,:3h6>??;I:a2>N?011/?>l58`g8md5=831bi44?::k007<722e8<84?::a<=e=83>1<7>t$2;`>6773A2i:6F7899'76d=0ho0el=50;9ja<<722c88?4?::m040<722wi45l50;694?6|,:3h6>??;I:a2>N?011/?>l58`g8md5=831bi44?::k007<722e8<84?::a<=g=83>1<7>t$2;`>6773A2i:6F7899'76d=0ho0el=50;9ja<<722c88?4?::m040<722wi>kl50;694?6|,:3h6>??;I:a2>N?011/?>l58`d8md5=831bi44?::k007<722e8<84?::p70g=838pR>;n;<::6?2e3ty8954?:3y]70><51396974}r163?6=:rT89:5288090==z{:?=6=4={_162>;?1;0?;6s|34794?4|V:?>70662;65?xu4==0;6?uQ34689=?62=h0q~=:3;296~X4=:1644?5489~w6352909wS=:2:?;=4<302wx?8?50;0xZ6363422=7:8;|q015<72;qU?8>4=9;2>10<uz9=?7>52z\026=:00:18o5rs241>5<5sW9=>6379187=>{t;?;1<7<t^242?8>>83>37p}<6183>7}Y;?:0157?:558yv52n3:1>vP<5g9><<6=<?1v>;j:181[52m2734k4;b:p70b=838pR>;k;<:;b?2>3ty89n4?:3y]70e<512m6964}r16f?6=:rT89o5289d902=z{:>m6=4={_17b>;?0o0?:6s|37794?3|V:<>70662;c7?8>>93k?70660;c7?8>?n3k?7p}<6583>0}Y;?>0157=:`389=?62h;0157?:`389=>a2h;0q~=96;296~X4>?1644<5e59~w<432909w0662;11<>;?0m088?5rs83a>5<5s422>7==a:?;=4<b<2wx5?=50;0x9=?62:837067c;176>{t18k1<7<t=9;2>64f3422<7k;;|q:67<72;q644>533:89=>e2:>97p}61883>7}:00:1??o4=9:e>`2<uz39=7>52z?;<c<4:11645o53508yv51?3:1>vP<669><=`=;;k0q~7>f;296~;?0m08<8522g`9e6=z{0;n6=4={<:;`?g43423o7=?5:p=4b=838p156l:`189=>e2::>7p}61b83>7}:01h1m>5289c9753<uz8>n7>52z\11g=::oh1?=;4}r3e0?6=;r73n54<209><=g=i:16>kl53508yv56>3:1:v37b682b6=:01n1i45289a9a<=:01h1i45289c9a<=::oh1i45r}r06e?6=:rT99l522ga9735<uz8?h7>52z\10a=::oi1?;<4}r076?6=:rT98?522ga9737<uz88;7>52z\172=::oi1?;>4}r01g?6=:rT9>n522ga970`<uz89=7>52z\164=::oi1?8k4}r022?6=:rT9=;522ga970b<uz8;n7>52z\14g=::oi1?8m4}r034?6=:rT9<=522ga970d<uz;m97>52z\2b0=::oi1?9h4}r`b>5<5sWhj70<ic;`b?xu4;h0;6?uQ32c897`d2:9j7p}<6483>7}Y;??01?hl:246?xu4>=0;6?uQ376897`d2:<?7p}<6783>7}Y;?<01?hl:245?xu4>>0;6?uQ375897`d2:<<7p}=5c83>7}Y:<h01?hl:37a?xu>890;6nu28c:9777<5;lh6>;n;<0eg?520279jn4<569>6ce=;<<01?hl:276?84ak39>863=fb8016=::oi1?8<4=3d`>636348mo7=:0:?1bf<6n=1vqo:<c;292?6=8r.85n4<0e9K<g0<@1237)<85;32?l42n3:17d<90;29?l4193:17d<92;29?l41;3:17b=>f;29?xd3=o0;6>4?:1y'7<e=;9k0D5l9;I:;<>"5?<0:h85+3379<fd<a;?m6=44i343>5<<g:;m6=44}c63f?6=?3:1<v*<9b804`=O0k<0D567;%041??<a;?m6=44i343>5<<a;<:6=44i341>5<<a;<86=44i347>5<<g:;m6=44}c60f?6=;3:1<v*<9b804d=O0k<0D567;%041?7c=2.8>847c69j60`=831b>;>50;9l74`=831vn9>6:180>5<7s-92o7=?a:J;f3=O0120(?9::0f6?!55=32hn6g=5g83>>o5>90;66a<1g83>>{e<9k1<7=50;2x 6?d2::j7E6m6:J;<==#:>?1=i;4$206>=e03`8>j7>5;h054?6=3f9:j7>5;|`72c<72>0;6=u+38a975c<@1h=7E678:&130<682c99k4?::k125<722c9:<4?::k127<722c9:>4?::k121<722e8=k4?::a026=83=1<7>t$2;`>66b3A2i:6F7899'623=991b>8h50;9j636=831b>;?50;9j634=831b>;=50;9j632=831d?<h50;9~f10b290?6=4?{%1:g?5692B3n;5G89:8m73a2900e?8?:188m6252900c>?i:188yg2093:1;7>50z&0=f<48l1C4o84H9:;?!40=3;;7d<:f;29?l4183:17d<91;29?l41:3:17d<93;29?l41<3:17b=>f;29?xd3?;0;6:4?:1y'7<e=;9o0D5l9;I:;<>"5?<0:<6g=5g83>>o5>90;66g=6083>>o5>;0;66g=6283>>o5>=0;66a<1g83>>{e<>91<7950;2x 6?d2::n7E6m6:J;<==#:>?1==5f24d94?=n:?:1<75f27394?=n:?81<75f27194?=n:?>1<75`30d94?=zj=<36=48:183!5>k39;i6F7b79K<=><,;=>6<>4i37e>5<<a;<;6=44i342>5<<a;<96=44i340>5<<a;<?6=44o23e>5<<uk>=57>54;294~"41j08=<5G8c48L=>?3`8>j7>5;h054?6=3`9?>7>5;n12b?6=3th?:94?:483>5}#;0i1=h94H9`5?M>?02.9;84=;h;4>5<<ah;1<75fe583>>o4:k0;66a<2983>>{e<?91<7;50;2x 6?d28o<7E6m6:J;<==#:>?1>6g67;29?lg62900eh:50;9j77d=831d??650;9~f105290>6=4?{%1:g?7b?2B3n;5G89:8 7122;1b5:4?::kb5?6=3`o?6=44i20a>5<<g:836=44}c655?6==3:1<v*<9b82a2=O0k<0D567;%041?4<a0=1<75fa083>>ob<3:17d==b;29?j5503:17pl;6183>0<729q/?4m51d58L=d13A2346*=7481?l?02900el?50;9ja1<722c8>o4?::m06=<722wi85m50;194?6|,:3h65l:;I:a2>N?011bm>4?::k041<722e8=k4?::a0=?=83>1<7>t$2;`>6773A2i:6F7899je6<722cn57>5;h176?6=3f9;97>5;|`7=6<72:0;6=u+38a9<g3<@1h=7E678:kb7?6=3`9;87>5;n12b?6=3th?5=4?:583>5}#;0i1?<>4H9`5?M>?02cj?7>5;hg:>5<<a:>96=44o226>5<<uk>2;7>53;294~"41j03n85G8c48L=>?3`k86=44i227>5<<g:;m6=44}c6:0?6=<3:1<v*<9b8055=O0k<0D567;hc0>5<<al31<75f35094?=h;9?1<75rb5;a>5<4290;w)=6c;:a1>N?j?1C4564i`194?=n;9>1<75`30d94?=zj=336=4;:183!5>k39:<6F7b79K<=><ah91<75fe883>>o4<;0;66a<0483>>{e<0l1<7=50;2x 6?d21h>7E6m6:J;<==ni:0;66g<0583>>i49o0;66sm48a94?2=83:p(>7l:233?M>e>2B3455fa283>>ob13:17d=;2;29?j57=3:17pl;a283>6<729q/?4m58c78L=d13A2346gn3;29?l57<3:17b=>f;29?xd3i90;694?:1y'7<e=;8:0D5l9;I:;<>of;3:17dk6:188m6252900c>>::188yg2f?3:1?7>50z&0=f<?j<1C4o84H9:;?lg42900e>>;:188k67a2900qo:n4;290?6=8r.85n4<119K<g0<@1237do<:188m`?=831b?9<50;9l753=831vn9om:180>5<7s-92o76m5:J;f3=O0120el=50;9j752=831d?<h50;9~f1g?290?6=4?{%1:g?5682B3n;5G89:8md5=831bi44?::k007<722e8<84?::a0d`=8391<7>t$2;`>=d23A2i:6F7899je6<722c8<94?::m05c<722wi8lm50;694?6|,:3h6>??;I:a2>N?011bm>4?::kf=?6=3`9?>7>5;n131?6=3th?n>4?:283>5}#;0i14o;4H9`5?M>?02cj?7>5;h130?6=3f9:j7>5;|`7f5<72=0;6=u+38a9746<@1h=7E678:kb7?6=3`o26=44i261>5<<g::>6=44}c6;b?6=;3:1<v*<9b8;f0=O0k<0D567;hc0>5<<a::?6=44o23e>5<<uk>3n7>52;294~"41j08<45G8c48L=>?3-8<97<>;h06b?6=3f9:j7>5;|`7=7<72;0;6=u+38a975?<@1h=7E678:&130<592c99k4?::m05c<722wi84850;094?6|,:3h6>>6;I:a2>N?011/>:;5209j60`=831d?<h50;9~f1?f29096=4?{%1:g?5712B3n;5G89:8 7122;;0e?;i:188k67a2900qo:6e;296?6=8r.85n4<089K<g0<@1237)<85;02?l42n3:17b=>f;29?xd3i;0;6?4?:1y'7<e=;930D5l9;I:;<>"5?<09=6g=5g83>>i49o0;66sm4`494?4=83:p(>7l:22:?M>e>2B3455+267964=n:<l1<75`30d94?=zj=kj6=4=:183!5>k39;56F7b79K<=><,;=>6??4i37e>5<<g:;m6=44}c6ba?6=:3:1<v*<9b804<=O0k<0D567;%041?463`8>j7>5;n12b?6=3th?n?4?:383>5}#;0i1?=74H9`5?M>?02.9;84=1:k11c<722e8=k4?::a0=c=8381<7>t$2;`>66>3A2i:6F7899'623=:81b>8h50;9l74`=831vn96n:186>5<7s-92o7?j7:J;f3=O0120(?9::39j=2<722cj=7>5;hg7>5<<a:8i6=44o20;>5<<uk>2=7>55;294~"41j0:i:5G8c48L=>?3-8<97<4i8594?=ni80;66gj4;29?l55j3:17b==8;29?xd31<0;684?:1y'7<e=9l=0D5l9;I:;<>"5?<097d78:188md7=831bi94?::k06g<722e8>54?::a0<?=83?1<7>t$2;`>4c03A2i:6F7899'623=:2c2;7>5;hc2>5<<al>1<75f33`94?=h;;21<75rb5;g>5<2290;w)=6c;3f3>N?j?1C4564$356>7=n1>0;66gn1;29?lc32900e><m:188k64?2900qo:n1;291?6=8r.85n4>e69K<g0<@1237)<85;08m<1=831bm<4?::kf0?6=3`99n7>5;n11<?6=3th?m84?:483>5}#;0i1=h94H9`5?M>?02.9;84=;h;4>5<<ah;1<75fe583>>o4:k0;66a<2983>>{e<h31<7;50;2x 6?d28o<7E6m6:J;<==#:>?1>6g67;29?lg62900eh:50;9j77d=831d??650;9~f1gc290>6=4?{%1:g?7b?2B3n;5G89:8 7122;1b5:4?::kb5?6=3`o?6=44i20a>5<<g:836=44}c6a5?6==3:1<v*<9b82a2=O0k<0D567;%041?4<a0=1<75fa083>>ob<3:17d==b;29?j5503:17pl;8e83>0<729q/?4m51d58L=d13A2346*=7481?l?02900el?50;9ja1<722c8>o4?::m06=<722wi8??50;194?6|,:3h65l:;I:a2>N?011bm>4?::k041<722e8=k4?::a04c=83>1<7>t$2;`>6773A2i:6F7899je6<722cn57>5;h176?6=3f9;97>5;|`760<72:0;6=u+38a9<g3<@1h=7E678:kb7?6=3`9;87>5;n12b?6=3th?>?4?:583>5}#;0i1?<>4H9`5?M>?02cj?7>5;hg:>5<<a:>96=44o226>5<<uk>957>53;294~"41j03n85G8c48L=>?3`k86=44i227>5<<g:;m6=44}c612?6=<3:1<v*<9b8055=O0k<0D567;hc0>5<<al31<75f35094?=h;9?1<75rb50g>5<4290;w)=6c;:a1>N?j?1C4564i`194?=n;9>1<75`30d94?=zj=8j6=4;:183!5>k39:<6F7b79K<=><ah91<75fe883>>o4<;0;66a<0483>>{e<:;1<7=50;2x 6?d21h>7E6m6:J;<==ni:0;66g<0583>>i49o0;66sm43g94?2=83:p(>7l:233?M>e>2B3455fa283>>ob13:17d=;2;29?j57=3:17pl;3583>6<729q/?4m58c78L=d13A2346gn3;29?l57<3:17b=>f;29?xd3:90;6?4?:1y'7<e=;930D5l9;I:;<>"5?<09=6g=5g83>>i49o0;66sm43694?4=83:p(>7l:22:?M>e>2B3455+267964=n:<l1<75`30d94?=zj=836=4=:183!5>k39;56F7b79K<=><,;=>6??4i37e>5<<g:;m6=44}c61g?6=:3:1<v*<9b804<=O0k<0D567;%041?463`8>j7>5;n12b?6=3th??=4?:383>5}#;0i1?=74H9`5?M>?02.9;84=1:k11c<722e8=k4?::a065=8381<7>t$2;`>66>3A2i:6F7899'623=:81b>8h50;9l74`=831vn9?i:186>5<7s-92o7?j7:J;f3=O0120(?9::39j=2<722cj=7>5;hg7>5<<a:8i6=44o20;>5<<uk>9?7>55;294~"41j0:i:5G8c48L=>?3-8<97<4i8594?=ni80;66gj4;29?l55j3:17b==8;29?xd3:>0;684?:1y'7<e=9l=0D5l9;I:;<>"5?<097d78:188md7=831bi94?::k06g<722e8>54?::a07d=83?1<7>t$2;`>4c03A2i:6F7899'623=:2c2;7>5;hc2>5<<al>1<75f33`94?=h;;21<75rb50e>5<2290;w)=6c;3f3>N?j?1C4564$356>7=n1>0;66gn1;29?lc32900e><m:188k64?2900qo:<2;291?6=8r.85n4>e69K<g0<@1237)<85;08m<1=831bm<4?::kf0?6=3`99n7>5;n11<?6=3th?8l4?:283>5}#;0i14o;4H9`5?M>?02cj?7>5;h130?6=3f9:j7>5;|`702<72=0;6=u+38a9746<@1h=7E678:kb7?6=3`o26=44i261>5<<g::>6=44}c67a?6=;3:1<v*<9b8;f0=O0k<0D567;hc0>5<<a::?6=44o23e>5<<uk>?n7>54;294~"41j08==5G8c48L=>?3`k86=44id;94?=n;=81<75`31794?=zj=?96=4<:183!5>k32i96F7b79K<=><ah91<75f31694?=h;8l1<75rb56e>5<3290;w)=6c;124>N?j?1C4564i`194?=nm00;66g<4383>>i48<0;66sm44494?5=83:p(>7l:9`6?M>e>2B3455fa283>>o48=0;66a<1g83>>{e<<91<7:50;2x 6?d2:;;7E6m6:J;<==ni:0;66gj9;29?l53:3:17b=?5;29?xd3=00;6>4?:1y'7<e=0k?0D5l9;I:;<>of;3:17d=?4;29?j56n3:17pl;4883>7<729q/?4m531;8L=d13A2346*=74815>o5=o0;66a<1g83>>{e<=n1<7<50;2x 6?d2::27E6m6:J;<==#:>?1><5f24d94?=h;8l1<75rb572>5<5290;w)=6c;13=>N?j?1C4564$356>77<a;?m6=44o23e>5<<uk>>97>52;294~"41j08<45G8c48L=>?3-8<97<>;h06b?6=3f9:j7>5;|`71=<72;0;6=u+38a975?<@1h=7E678:&130<592c99k4?::m05c<722wi89650;794?6|,:3h6<k8;I:a2>N?011/>:;52:k:3?6=3`k:6=44id694?=n;;h1<75`33:94?=zj=>h6=4::183!5>k3;n;6F7b79K<=><,;=>6?5f9683>>of93:17dk;:188m64e2900c><7:188yg2283:197>50z&0=f<6m>1C4o84H9:;?!40=380e4950;9je4<722cn87>5;h11f?6=3f9947>5;|`711<72<0;6=u+38a95`1<@1h=7E678:&130<53`3<6=44i`394?=nm=0;66g<2c83>>i4:10;66sm44594?3=83:p(>7l:0g4?M>e>2B3455+26796>o>?3:17do>:188m`2=831b??l50;9l77>=831vn;7j:187>5<7s-92o7=?b:J;f3=O0120(?9::0f5?l42n3:17d<90;29?l4193:17b=>f;29?xd3k;0;6:4?:1y'7<e=;9o0D5l9;I:;<>"5?<0:ii5f24d94?=n:?:1<75f27394?=n:?81<75f27194?=n:?>1<75`30d94?=zj?ih6=4<:183!5>k39;m6F7b79K<=><,;=>6??4$206>=ef3`8>j7>5;h054?6=3f9:j7>5;|`5`2<72>0;6=u+38a975c<@1h=7E678:&130<5i2c99k4?::k125<722c9:<4?::k127<722c9:>4?::k121<722e8=k4?::a2ab=8391<7>t$2;`>66f3A2i:6F7899'623=:81/??;58bc8m73a2900e?8?:188k67a2900qo8ke;293?6=8r.85n4<0d9K<g0<@1237)<85;66?l42n3:17d<90;29?l4193:17d<92;29?l41;3:17d<94;29?j56n3:17pl9dg83>2<729q/?4m531g8L=d13A2346*=7482a4=n:<l1<75f27294?=n:?;1<75f27094?=n:?91<75f27694?=h;8l1<75rb7g3>5<0290;w)=6c;13a>N?j?1C4564$356>f=n:<l1<75f27294?=n:?;1<75f27094?=n:?91<75f27694?=h;8l1<75rb7g6>5<0290;w)=6c;13a>N?j?1C4564$356>6c<a;?m6=44i343>5<<a;<:6=44i341>5<<a;<86=44i347>5<<g:;m6=44}c4f2?6=?3:1<v*<9b804`=O0k<0D567;%041?5b3`8>j7>5;h054?6=3`8==7>5;h056?6=3`8=?7>5;h050?6=3f9:j7>5;|`5ga<72>0;6=u+38a975c<@1h=7E678:&130<4m2c99k4?::k125<722c9:<4?::k127<722c9:>4?::k121<722e8=k4?::a2fc=83=1<7>t$2;`>66b3A2i:6F7899'623=;l1b>8h50;9j636=831b>;?50;9j634=831b>;=50;9j632=831d?<h50;9~f3ea290<6=4?{%1:g?57m2B3n;5G89:8 7122:o0e?;i:188m7072900e?8>:188m7052900e?8<:188m7032900c>?i:188yg0c83:197>50z&0=f<48j1C4o84H9:;?!40=39o7d<:f;29?l4183:17d<91;29?l41:3:17b=>f;29?xd1l80;6:4?:1y'7<e=;9o0D5l9;I:;<>"5?<0:ik5f24d94?=n:?:1<75f27394?=n:?81<75f27194?=n:?>1<75`30d94?=zj?n96=48:183!5>k39;i6F7b79K<=><,;=>6<kj;h06b?6=3`8=<7>5;h055?6=3`8=>7>5;h057?6=3`8=87>5;n12b?6=3th=h>4?:683>5}#;0i1?=k4H9`5?M>?02.9;847;h06b?6=3`8=<7>5;h055?6=3`8=>7>5;h057?6=3`8=87>5;n12b?6=3th=h94?:683>5}#;0i1?=k4H9`5?M>?02.9;84>eb9j60`=831b>;>50;9j637=831b>;<50;9j635=831b>;:50;9l74`=831vn;j::184>5<7s-92o7=?e:J;f3=O0120(?9::d9j60`=831b>;>50;9j637=831b>;<50;9j635=831b>;:50;9l74`=831vn;j9:185>5<7s-92o7=?d:J;f3=O0120(?9::0ff?l42n3:17d<90;29?l4193:17d<92;29?l41;3:17b=>f;29?xd1l10;6:4?:1y'7<e=;9o0D5l9;I:;<>"5?<0:il5f24d94?=n:?:1<75f27394?=n:?81<75f27194?=n:?>1<75`30d94?=zj?i<6=4;:183!5>k3;n:6F7b79K<=><,;=>6?5f9683>>ob<3:17d==b;29?j5503:17pl9c883>1<729q/?4m51d48L=d13A2346*=7481?l?02900eh:50;9j77d=831d??650;9~f3ef29086=4?{%1:g?57i2B3n;5G89:8 71228n>7)==5;:`6>o5=o0;66g=6183>>i49o0;66sm72594?2=83:p(>7l:0g5?M>e>2B3455+26796>o>?3:17dk;:188m64e2900c><7:188yg1403:1?7>50z&0=f<48h1C4o84H9:;?!40=3;o96g=5g83>>o5>90;66a<1g83>>{e>ho1<7:50;2x 6?d28o=7E6m6:J;<==#:>?1>6g67;29?lc32900e><m:188k64?2900qo8nf;297?6=8r.85n4<0`9K<g0<@1237)<85;3g1>"4:<03o>5f24d94?=n:?:1<75`30d94?=zj?ni6=48:183!5>k39;i6F7b79K<=><,;=>6>o4i37e>5<<a;<;6=44i342>5<<a;<96=44i340>5<<a;<?6=44o23e>5<<uk<om7>57;294~"41j08<h5G8c48L=>?3-8<97:l;h06b?6=3`8=<7>5;h055?6=3`8=>7>5;h057?6=3`8=87>5;n12b?6=3th=i?4?:583>5}#;0i1?=l4H9`5?M>?02.9;84>4:&060<?k11b>8h50;9j636=831b>;?50;9l74`=831vn;k<:184>5<7s-92o7=?e:J;f3=O0120(?9::5g8m73a2900e?8?:188m7062900e?8=:188m7042900e?8;:188k67a2900qo8kc;293?6=8r.85n4<0d9K<g0<@1237)<85;g4?l42n3:17d<90;29?l4193:17d<92;29?l41;3:17d<94;29?j56n3:17pl8f383>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg>2k3:1?7>50z&0=f<6m91C4o84H9:;?!40=3;87d78:188m`2=831d??650;9~f=3e29086=4?{%1:g?7b82B3n;5G89:8 7122890e4950;9ja1<722e8>54?::a<0g=8391<7>t$2;`>4c73A2i:6F7899'623=9:1b5:4?::kf0?6=3f9947>5;|`;1<<72:0;6=u+38a95`6<@1h=7E678:&130<6;2c2;7>5;hg7>5<<g:836=44}c:6<?6=;3:1<v*<9b82a5=O0k<0D567;%041?743`3<6=44id694?=h;;21<75rb974>5<4290;w)=6c;3f4>N?j?1C4564$356>45<a0=1<75fe583>>i4:10;66sm84794?5=83:p(>7l:0g3?M>e>2B3455+267956=n1>0;66gj4;29?j5503:17pl75583>6<729q/?4m51d28L=d13A2346*=74827>o>?3:17dk;:188k64?2900qo6:3;297?6=8r.85n4>e19K<g0<@1237)<85;30?l?02900eh:50;9l77>=831vn5;=:180>5<7s-92o7?j0:J;f3=O0120(?9::018m<1=831bi94?::m06=<722wi48?50;194?6|,:3h6<k?;I:a2>N?011/>:;5129j=2<722cn87>5;n11<?6=3th39=4?:283>5}#;0i1=h>4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44o20;>5<<uk2?j7>53;294~"41j0:i=5G8c48L=>?3-8<97?<;h;4>5<<al>1<75`33:94?=zj1>n6=4<:183!5>k3;n<6F7b79K<=><,;=>6<=4i8594?=nm=0;66a<2983>>{e0=n1<7=50;2x 6?d28o;7E6m6:J;<==#:>?1=>5f9683>>ob<3:17b==8;29?xd?<j0;6>4?:1y'7<e=9l:0D5l9;I:;<>"5?<0:?6g67;29?lc32900c><7:188yg>3i3:1?7>50z&0=f<6m91C4o84H9:;?!40=3;87d78:188m`2=831d??650;9~f=2>29086=4?{%1:g?7b82B3n;5G89:8 7122890e4950;9ja1<722e8>54?::a<1>=8391<7>t$2;`>4c73A2i:6F7899'623=9:1b5:4?::kf0?6=3f9947>5;|`;02<72:0;6=u+38a95`6<@1h=7E678:&130<6;2c2;7>5;hg7>5<<g:836=44}c:72?6=;3:1<v*<9b82a5=O0k<0D567;%041?743`3<6=44id694?=h;;21<75rb966>5<4290;w)=6c;3f4>N?j?1C4564$356>45<a0=1<75fe583>>i4:10;66sm85694?5=83:p(>7l:0g3?M>e>2B3455+267956=n1>0;66gj4;29?j5503:17pl74283>6<729q/?4m51d28L=d13A2346*=74827>o>?3:17dk;:188k64?2900qo6;2;297?6=8r.85n4>e19K<g0<@1237)<85;30?l?02900eh:50;9l77>=831vn5:>:180>5<7s-92o7?j0:J;f3=O0120(?9::018m<1=831bi94?::m06=<722wi4;=50;194?6|,:3h6<k?;I:a2>N?011/>:;5129j=2<722cn87>5;n11<?6=3th3:?4?:283>5}#;0i1=h>4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44o20;>5<<uk2==7>53;294~"41j0:i=5G8c48L=>?3-8<97?<;h;4>5<<al>1<75`33:94?=zj1<;6=4<:183!5>k3;n<6F7b79K<=><,;=>6<=4i8594?=nm=0;66a<2983>>{e0<l1<7=50;2x 6?d28o;7E6m6:J;<==#:>?1=>5f9683>>ob<3:17b==8;29?xd?=l0;6>4?:1y'7<e=9l:0D5l9;I:;<>"5?<0:?6g67;29?lc32900c><7:188yg>2l3:1?7>50z&0=f<6m91C4o84H9:;?!40=3;87d78:188m`2=831d??650;9~f=3129086=4?{%1:g?7b82B3n;5G89:8 7122890e4950;9ja1<722e8>54?::a<1d=8391<7>t$2;`>4c73A2i:6F7899'623=9:1b5:4?::kf0?6=3f9947>5;|`;05<72:0;6=u+38a95`6<@1h=7E678:&130<6;2c2;7>5;hg7>5<<g:836=44}c5;1?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>3;6=4;:183!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm78`94?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0i;0;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo9n3;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f2g3290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;l;50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`4e3<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk=j;7>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb6c;>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e?1<1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl88683>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1?03:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:66:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::a3=g=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<4o4?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c5;g?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>2o6=4;:183!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm79g94?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd00o0;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo961;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f2?5290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;4=50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`4=1<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk=297>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb6;5>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e?0=1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl89983>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1>13:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:7n:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::a3<e=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<5i4?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c5:a?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>3m6=4;:183!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm7`294?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0i80;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo991;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f20d290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;:950;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`43`<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk=<j7>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb6:3>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e?1;1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl88383>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1?;3:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:6;:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::a334=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<:>4?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c550?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj><>6=4;:183!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm77494?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0>>0;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo998;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f20>290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;;o50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`42g<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk==h7>54;294~"41j0:i85G8c48L=>?3-8<97?<;h;4>5<<al>1<75f33494?=h;;21<75rb64f>5<3290;w)=6c;3f1>N?j?1C4564$356>45<a0=1<75fe583>>o4:?0;66a<2983>>{e??l1<7:50;2x 6?d28o>7E6m6:J;<==#:>?1=>5f9683>>ob<3:17d==6;29?j5503:17pl87183>1<729q/?4m51d78L=d13A2346*=74827>o>?3:17dk;:188m6412900c><7:188yg1093:187>50z&0=f<6m<1C4o84H9:;?!40=3;87d78:188m`2=831b??850;9l77>=831vn:9=:187>5<7s-92o7?j5:J;f3=O0120(?9::018m<1=831bi94?::k063<722e8>54?::a325=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th<;94?:583>5}#;0i1=h;4H9`5?M>?02.9;84>3:k:3?6=3`o?6=44i205>5<<g:836=44}c541?6=<3:1<v*<9b82a0=O0k<0D567;%041?743`3<6=44id694?=n;;<1<75`33:94?=zj>==6=4;:183!5>k3;n96F7b79K<=><,;=>6<=4i8594?=nm=0;66g<2783>>i4:10;66sm76:94?2=83:p(>7l:0g6?M>e>2B3455+267956=n1>0;66gj4;29?l55>3:17b==8;29?xd0?00;694?:1y'7<e=9l?0D5l9;I:;<>"5?<0:?6g67;29?lc32900e><9:188k64?2900qo98a;290?6=8r.85n4>e49K<g0<@1237)<85;30?l?02900eh:50;9j770=831d??650;9~f21e290?6=4?{%1:g?7b=2B3n;5G89:8 7122890e4950;9ja1<722c8>;4?::m06=<722wi;:m50;694?6|,:3h6<k:;I:a2>N?011/>:;5129j=2<722cn87>5;h112?6=3f9947>5;|`43a<72=0;6=u+38a95`3<@1h=7E678:&130<6;2c2;7>5;hg7>5<<a:8=6=44o20;>5<<uk<i57>54;294~"41j0:i?5G8c48L=>?3-8<97<4i8594?=njk0;66gj4;29?j5503:17pl9b`83>1<729q/?4m51d08L=d13A2346*=7481?l?02900eol50;9ja1<722e8>54?::a2g4=83>1<7>t$2;`>4c23A2i:6F7899'623=9:1b5:4?::kf0?6=3`99:7>5;n11<?6=3th=n<4?:583>5}#;0i1=h<4H9`5?M>?02.9;84=;h;4>5<<akh1<75fe583>>i4:10;66sm6df94?2=83:p(>7l:0g1?M>e>2B3455+26796>o>?3:17dlm:188m`2=831d??650;9~f31129086=4?{%1:g?7b82B3n;5G89:8 7122890e4950;9ja1<722e8>54?::a23g=83>1<7>t$2;`>4c53A2i:6F7899'623=:2c2;7>5;h`a>5<<al>1<75`33:94?=zj?<26=4;:183!5>k3;n>6F7b79K<=><,;=>6?5f9683>>oej3:17dk;:188k64?2900qo8:7;290?6=8r.85n4>e39K<g0<@1237)<85;08m<1=831bno4?::kf0?6=3f9947>5;|`513<72=0;6=u+38a95`4<@1h=7E678:&130<53`3<6=44ic`94?=nm=0;66a<2983>>{e>l>1<7:50;2x 6?d2::i7E6m6:J;<==#:>?18i5+3379<f><a;?m6=44i343>5<<a;<:6=44o23e>5<<uk>=97>58183>5}#;0i1??m4H9`5?M>?02P2:7kt25811?7?2831>;4=7;0;>7?=9j0:h7?j:0d905<4>3we=4>50:l2g6<73-8=9794$345>2=#:?=1;6*=6984?!4113=0(?8n:69'63d=?2.9:n48;%042?1<,;=<6:5+26:93>"5?00<7)<8a;58 71e2>1/>:m57:&13a<03-8<i794$35e>2=#:1:1;6*=8084?!4?:3=0(?6<:69'6=2=?2.94848;%0;2?1<,;2<6:5+29:93>"5000<7)<7a;58 7>e2>1/>5m57:&1<a<03-83i794$3:e>2=#:0:1;6*=9084?!4>:3=0(?7<:69'6<2=?2.95848;%0:2?1<,;3<6:5+28:93>"5100<7)<6a;58 7?e2>1/>4m57:&1=a<03-82i794$3;e>2=#:h:1;6*=a084?!4f:3=0(?o<:69'6d2=?2.9m848;%0b2?1<,;k<6:5+2`:93>"5i00<7)<na;58 7ge2>1/>lm57:&1ea<03-8ji794$3ce>2=#:k:1;6*=b084?!4e:3=0(?l<:69'6g2=?2.9n848;%0e2?2<,;l<695+2g:974c<,:9;6>8k;o106??<f:986<<4$263>6533-9?=7=<4:&002<?1<1/?;654:&02<<33-2jm76n9:&;eg<?i01e4lm59:l;ea<6:2.8?<4j8:&001<6lo1bn=4?::ka7?6=3`;o57>5;h3gf?6=3`98:7>5;h103?6=3`9847>5H26:?>o4;00;6E=;9:9j76e=831b?>j50;9j76c=831b?>h50;9j20<72-99878;;o117?6<3`<86=4+336921=i;;91=65f6383>!55<3<?7c==3;08?l06290/??:5659m775=;21b:h4?:%110?033g99?7:4;h4g>5<#;;>1:95a33191>=n>j0;6)==4;47?k55;3<07d8m:18'772=>=1e??=57:9j2d<72-99878;;o117?><3`<26=4+336921=i;;91565f6983>!55<3<?7c==3;c8?l00290/??:5659m775=j21b:;4?:%110?033g99?7m4;h43>5<#;;>1:95a3319`>=n?80;6)==4;53?k55;3:0D>:6;:k5b?6=,:8?6:>4n200>4=O;=307d6::18'772=0=1e??=50:J00<=<a191<7*<258;0>h4::0:7E=;9:9j<g<72-99876n;o117?6<3`226=4+3369<d=i;;91=65f8983>!55<32j7c==3;08?l>0290/??:58`9m775=;21b594?:%110?>f3g99?7:4;h;0>5<#;;>14l5a33191>=n1;0;6)==4;:b?k55;3<07d7>:18'772=0h1e??=57:9j=5<72-99876n;o117?><3`2m6=4+3369<d=i;;91565f8d83>!55<32j7c==3;c8?l>c290/??:58`9m775=j21b4n4?:%110?>f3g99?7m4;h:5>5<#;;>14l5a3319`>=n9881<7*<258254=i;;91<65f10294?"4:=0:=<5a33195>=n99l1<7*<258254=i;;91>65f11g94?"4:=0:=<5a33197>=n99n1<7*<258254=i;;91865f11a94?"4:=0:=<5a33191>=n98h1<7*<258254=i;;91:65f10c94?"4:=0:=<5a33193>=n9831<7*<258254=i;;91465f10:94?"4:=0:=<5a3319=>=n98=1<7*<258254=i;;91m65f10494?"4:=0:=<5a3319f>=n98?1<7*<258254=i;;91o65f10694?"4:=0:=<5a3319`>=n9891<7*<258254=i;;91i65f11`94?"4:=0:=<5a3319b>=n9=>1<7*<258206=i;;91<65f15094?"4:=0:8>5a33195>=n9=;1<7*<258206=i;;91>65f15294?"4:=0:8>5a33197>=n9:l1<7*<258206=i;;91865f12g94?"4:=0:8>5a33191>=n9=n1<7*<258206=i;;91:65f15a94?"4:=0:8>5a33193>=n9=h1<7*<258206=i;;91465f15c94?"4:=0:8>5a3319=>=n9=31<7*<258206=i;;91m65f15:94?"4:=0:8>5a3319f>=n9==1<7*<258206=i;;91o65f15494?"4:=0:8>5a3319`>=n9=?1<7*<258206=i;;91i65f12f94?"4:=0:8>5a3319b>=n9<?1<7*<258211=i;;91<65f14194?"4:=0:995a33195>=n9<n1<7*<25821f=i;;91<65f14`94?"4:=0:9n5a33195>=h91<1<7*<2582<0=i;;91<65`19694?"4:=0:485a33195>=h9191<7*<2582<0=i;;91>65`19094?"4:=0:485a33197>=h91;1<7*<2582<0=i;;91865`19294?"4:=0:485a33191>=h91l1<7*<2582<0=i;;91:65`19g94?"4:=0:485a33193>=h91n1<7*<2582<0=i;;91465`19a94?"4:=0:485a3319=>=h91h1<7*<2582<0=i;;91m65`19c94?"4:=0:485a3319f>=h9131<7*<2582<0=i;;91o65`19:94?"4:=0:485a3319`>=h91=1<7*<2582<0=i;;91i65`16d94?"4:=0:485a3319b>=h9k31<7*<2582f==i;;91<65`1c594?"4:=0:n55a33195>=h9k<1<7*<2582f==i;;91>65`1c794?"4:=0:n55a33197>=h9k>1<7*<2582f==i;;91865`1c194?"4:=0:n55a33191>=h9j81<7*<2582f==i;;91:65`1b394?"4:=0:n55a33193>=h9j:1<7*<2582f==i;;91465`1cd94?"4:=0:n55a3319=>=h9ko1<7*<2582f==i;;91m65`1cf94?"4:=0:n55a3319f>=h9ki1<7*<2582f==i;;91o65`1c`94?"4:=0:n55a3319`>=h9kk1<7*<2582f==i;;91i65`1c094?"4:=0:n55a3319b>=h9jh1<7*<2582gd=i;;91<65`1b;94?"4:=0:ol5a33195>=h9m91<7*<2582`7=i;;91<65`1e394?"4:=0:h?5a33195>=n00k1<7*<258;=<=i;;91<6F<4898m=??290/??:588;8j644281C?974;h::3?6=,:8?6576;o117?4<3`22:7>5$207>=?>3g99?7=4;h:b<?6=,:8?65o8;o117?6<@:>276g7a783>!55<32j;6`<2282?M53121b4l;50;&061<?i>1e??=52:J00<=<a1k?6=4+3369<d1<f:886>5G35;8?l>f;3:1(><;:9c4?k55;3>07d6n2;29 64321k<7c==3;78?l>f93:1(><;:9c4?k55;3<07d6n0;29 64321k<7c==3;58?xd3>m0;6:4?:1y'7<e=;9o0D5l9;I:;<>"5?<0:<6g=5g83>>o5>90;66g=6083>>o5>;0;66g=6283>>o5>=0;66a<1g83>>{e<?h1<7:50;2x 6?d2::i7E6m6:J;<==#:>?1>=5f24d94?=n:?:1<75f27394?=h;8l1<75rb544>5<d03:1<vF7899'7<e=;;n0V485cz3b>4d=;=0847=::2;973<5k38o6?k53681f?{i90:1<6`>c283?!41=3=0(?89:69'631=?2.9:548;%05=?1<,;<j6:5+27`93>"5>j0<7)<9d;58 70b2>1/>;h57:&135<03-8<=794$351>2=#:>91;6*=7584?!40>3=0(?98:69'62>=?2.9;448;%04e?1<,;=i6:5+26a93>"5?m0<7)<8e;58 71a2>1/>5>57:&1<4<03-83>794$3:0>2=#:1>1;6*=8484?!4?>3=0(?68:69'6=>=?2.94448;%0;e?1<,;2i6:5+29a93>"50m0<7)<7e;58 7>a2>1/>4>57:&1=4<03-82>794$3;0>2=#:0>1;6*=9484?!4>>3=0(?78:69'6<>=?2.95448;%0:e?1<,;3i6:5+28a93>"51m0<7)<6e;58 7?a2>1/>l>57:&1e4<03-8j>794$3c0>2=#:h>1;6*=a484?!4f>3=0(?o8:69'6d>=?2.9m448;%0be?1<,;ki6:5+2`a93>"5im0<7)<ne;58 7ga2>1/>o>57:&1f4<03-8i>794$3`0>2=#:k>1;6*=b484?!4e>3=0(?l8:69'6g>=?2.9n448;%0ae?1<,;hi6:5+2ca93>"5jm0<7)<me;58 7da2>1/>n>57:&1g4<03-8h>794$3a0>2=#:j>1;6*=c484?!4d>3=0(?m8:69'6f>=?2.9o448;%0`e?1<,;ii6:5+2ba93>"5km0<7)<le;58 7ea2>1/>i>57:&1`4<03-8o>794$3f0>2=#:m>1;6*=d484?!4c>3=0(?j8:69'6a>=?2.9h448;%0ge?1<,;ni6:5+2ea93>"5lm0<7)<ke;58 7ba2>1/>h>57:&1a4<03-8n>794$3g0>2=#:l>1;6*=e484?!4b>3=0(?k8:69'6`>=?2.9i448;%0fe?1<,;oi6:5+2da93>"5mm0<7)<je;58 7ca2>1/>k>57:&1b4<03-8m>794$3d0>2=#:o>1;6*=f484?!4a>3<0(?h8:79'6c>=;8o0(><j:23f?!55n39:i6`<33826>h4;:0986*<468:1>"4<1088>5+37:92>"4>00=7)6na;:b=>"?ik03m45a8`a957=i0hn1>95fe`83>!55<3;;>6`<2282b>=n9<k1<7*<25821<=i;;91<65fac83>>oe93:17d?k8;29?l75k3:1(><;:017?k55;3=07d?=b;29 643289?7c==3;:8?l75i3:1(><;:017?k55;3307d?=9;29 643289?7c==3;c8?l7503:1(><;:017?k55;3h07d?=6;29 643289?7c==3;a8?l75=3:1(><;:017?k55;3n07d?=4;29 643289?7c==3;g8?l75;3:1(><;:017?k55;3l07d?=2;29 643289?7c==3;33?>o6:80;6)==4;300>h4::0:=65f13294?"4:=0:?95a331957=<a8;m6=4+3369562<f:886<=4;h32a?6=,:8?6<=;;o117?7332c:=i4?:%110?74<2d8>>4>5:9j56e=83.8>94>359m775=9?10e<=m:18'772=9:>0b><<:058?l74i3:1(><;:017?k55;3;376g>3883>!55<3;886`<2282=>=n9:21<7*<258271=i;;91=l54i014>5<#;;>1=>:4n200>4d<3`;8:7>5$207>4533g99?7?l;:k277<72-9987?<4:l066<6l21b=?950;&061<6;=1e??=51d98m47d290/??:51268j64428l07b?94;29 64328==7c==3;33?>i6>:0;6)==4;342>h4::0:=65`17094?"4:=0:;;5a331957=<g8<:6=4+3369520<f:886<=4;n354?6=,:8?6<99;o117?7332e:9k4?:%110?70>2d8>>4>5:9l52c=83.8>94>779m775=9?10c<9k:18'772=9><0b><<:058?j70k3:1(><;:055?k55;3;376a>7c83>!55<3;<:6`<2282=>=h9>k1<7*<258233=i;;91=l54o05:>5<#;;>1=:84n200>4d<3f;<47>5$207>4113g99?7?l;:m231<72-9987?86:l066<6l21d=;750;&061<6??1e??=51d98k43b290/??:51648j64428l07b?l5;29 64328i<7c==3;08?j7d<3:1(><;:0a4?k55;3907d?:8;29 64328?27c==3;38?l72?3:1(><;:07:?k55;3807d?:6;29 64328?27c==3;18?l33290/??:5549m775=921b9>4?:%110?323g99?7<4;h71>5<#;;>1985a33197>=n=80;6)==4;76?k55;3>07d;?:18'772==<1e??=55:9j1c<72-9987;:;o117?0<3`?n6=4+336910=i;;91;65f5e83>!55<3?>7c==3;:8?l3d290/??:5549m775=121b9o4?:%110?323g99?7o4;h7b>5<#;;>1985a3319f>=n?>0;6)==4;5;?k55;3;07d99:18'772=?11e??=52:9j30<72-998797;o117?5<3`=?6=4+33693==i;;91865f7283>!55<3=37c==3;78?l>5290/??:5799m775=>21b4<4?:%110?1?3g99?794;h:3>5<#;;>1;55a3319<>=n?o0;6)==4;5;?k55;3307d9j:18'772=?11e??=5a:9j<<d=83.8>9479d9m775=;21d5k4?::m:a?6=3`9897>5;nc3>5<<a:<i6=44o8f94?=n1h0;66g>d`83>>o>13:17d7l:188m60f2900e4l50;9j761=831b=8<50;&061<6=81e??=50:9j506=83.8>94>509m775=921b=9h50;&061<6=81e??=52:9j51c=83.8>94>509m775=;21b44o50;&061<?101e??=50:9j<<>=83.8>947989m775=921b44950;&061<?101e??=52:9j<<0=83.8>947989m775=;21b=>;50;&061<6;=1e??=50:9j565=83.8>94>359m775=921b=>?50;&061<6;=1e??=52:9j566=83.8>94>359m775=;21b=?h50;&061<6;=1e??=54:9j57c=83.8>94>359m775==21b=?j50;&061<6;=1e??=56:9l521=83.8>94>779m775=821d=:;50;&061<6??1e??=51:9l525=83.8>94>779m775=:21d=:<50;&061<6??1e??=53:9l527=83.8>94>779m775=<21d=:>50;&061<6??1e??=55:9l53`=83.8>94>779m775=>21d=;k50;&061<6??1e??=57:9l53b=83.8>94>779m775=021d=;m50;&061<6??1e??=59:9l53d=83.8>94>779m775=i21d=;o50;&061<6??1e??=5b:9l53>=83.8>94>779m775=k21d=;950;&061<6??1e??=5d:9l530=83.8>94>779m775=m21d=;;50;&061<6??1e??=5f:9l5f>=83.8>94>c69m775=821d=n850;&061<6k>1e??=51:9l5a6=83.8>94>cg9m775=821d=nk50;&061<6ko1e??=51:9l5fb=83.8>94>cg9m775=:21d=nm50;&061<6ko1e??=53:9j13<72-9987;:;o117?6<3`?26=4+336910=i;;91o65f5983>!55<3?>7c==3;f8?l30290/??:5549m775=m21b8k4?:%110?323g99?7h4;n3be?6=,:8?6<o6;o117?6<3f;j47>5$207>4g>3g99?7?4;n3b2?6=,:8?6<o6;o117?4<3f;j97>5$207>4g>3g99?7=4;n3b0?6=,:8?6<o6;o117?2<3f;j?7>5$207>4g>3g99?7;4;n3b6?6=,:8?6<o6;o117?0<3f;j=7>5$207>4g>3g99?794;n3b4?6=,:8?6<o6;o117?><3f;2j7>5$207>4g>3g99?774;n3:a?6=,:8?6<o6;o117?g<3f;2h7>5$207>4g>3g99?7l4;n3:f?6=,:8?6<o6;o117?e<3f;2m7>5$207>4g>3g99?7j4;n3:=?6=,:8?6<o6;o117?c<3f;247>5$207>4g>3g99?7h4;n3:3?6=,:8?6<o6;o117?7732e:5;4?:%110?7f12d8>>4>1:9l5<3=83.8>94>a89m775=9;10c<7;:18'772=9h30b><<:018?j7>;3:1(><;:0c:?k55;3;?76a>9383>!55<3;j56`<22821>=h9k;1<7*<2582e<=i;;91=;54o0`3>5<#;;>1=l74n200>41<3f;jj7>5$207>4g>3g99?7?7;:m2e`<72-9987?n9:l066<6121d=lj50;&061<6i01e??=51`98k4gd290/??:51`;8j64428h07b?nb;29 64328k27c==3;3`?>i6i>0;6)==4;3b=>h4::0:h65`18a94?"4:=0:m45a33195`=<g83:6=4+33695d?<f:886<h4;h5:>5<#;;>1;55a33194>=n?m0;6)==4;5;?k55;3h07d9l:18'772=?11e??=5c:9j3g<72-998797;o117?b<3`=j6=4+33693==i;;91i65f7383>!55<3=37c==3;d8?l>>n3:1(><;:9;f?k55;3:07d66d;29 643213n7c==3;38?l>>k3:1(><;:9;f?k55;3807d??3;29 64328:97c==3;28?l7793:1(><;:021?k55;3;07dhi:18'772=9980b><<:398mcc=83.8>94>039m775=;21bji4?:%110?77:2d8>>4;;:keg?6=,:8?6<>=;o117?3<3`li6=4+3369554<f:886;54igc94?"4:=0:<?5a33193>=nn00;6)==4;336>h4::0376gi8;29 64328:97c==3;;8?l`0290/??:51108j6442h10ek850;&061<68;1e??=5b:9jb1<72-9987??2:l066<d32cm?7>5$207>4653g99?7j4;hd1>5<#;;>1==<4n200>`=<ao;1<7*<258247=i;;91j65ff183>!55<3;;>6`<22824>=nmo0;6)==4;336>h4::0:=65fed83>!55<3;;>6`<22826>=nmm0;6)==4;336>h4::0:?65feb83>!55<3;;>6`<22820>=nmk0;6)==4;336>h4::0:965f11c94?"4:=0:<?5a331953=<a8:26=4+3369554<f:886<94;h33<?6=,:8?6<>=;o117?7?32c:<:4?:%110?77:2d8>>4>9:9j550=83.8>94>039m775=9h10e<>::18'772=9980b><<:0`8?l77<3:1(><;:021?k55;3;h76g>0183>!55<3;;>6`<2282`>=nn<0;6)==4;336>h4::0:i65rb82;>5<7290;w)=6c;15b>N4>l1G?;h54z&0==<6n91/?4751g38 6?f28l:7)=6b;3e5>{z{:2m6=4={_1;b>;?=j0n86s|39f94?4|V:2o706:b;g7?xu40j0;6?uQ39a89=3f2l>0q~=7b;296~X40k164875e59~w6>f2909wS=7a:?;1=<b<2wx?5750;0xZ6>>342>;7k;;|q0<2<72;qU?594=976>`2<uz93:7>52z\0<3=:0<>1i95rs2:6>5<5sW939637528f0>{t;1>1<7<t^2:7?8>2:3o?7p}<8283>7}Y;19015;>:d68yv5?:3:1>vP<839><06=m=1v>6>:181[5?92738k4j4:p7=6=838pR>6?;<:7a?c33ty8;k4?:3y]72`<51>o6h:4}r14a?6=:rT8;h5285a9a1=z{:=h6=4={_14g>;?<h0n86s|36`94?4|V:=i706;9;g7?xu4?h0;6?uQ36c89=2?2l>0q~=89;296~X4?0164995e59~w61?2909wS=88:?;03<b<2wx?:950;0xZ610342?97k;;|q033<72;qU?:84=967>`2<uz9<97>52z\030=:0=91i95rs257>5<5sW9<8637438f0>{t;>91<7<t^250?8>393o?7p}<9783>7}Y;0<0158<:d68yv5>=3:1>vP<949><34=m=1v>7;:181[5><273:<4j4:p7<5=838pR>7<;<:54?c33ty85?4?:3y]7<4<51?m6h:4}r1:5?6=:rT85<5284g9a1=z{:3;6=4={_1:4>;?=m0n86s|39:94?4|V:23706:6;g7?xu4?m0;6?uQ36f89=2e2l>0q~=82;296~X4?;1649>5e59~wag=838pRio4=7f3>7053tyo47>52z\g<>;1l909:<5rse594?4|Vm=01;j?:37e?xuc>3:1>vPk6:?5`5<5>91vi;50;0xZa3<5?im6?8;;|qg0?6=:rTo8639cg8126=z{m81<7<t^e0893ea2;<97p}k1;296~Xc927=ok4=609~wa6=838pRi>4=7ae>73a3tyhj7>52z\`b>;1ko09:=5rsbg94?4|Vjo01;k9:347?xudl3:1>vPld:?5a3<5>:1vnm50;0xZfe<5?o=6?8=;|q`f?6=:rThn639e78124=z{jk1<7<t^bc893c12;?m7p}l9;290g}Yk016;l75376893c12;<;70975;112>;01908>;5278`9770<5>k96><9;<5b7?55>27<m94<279>3d3=;;<01:o9:205?81f?399:638a98063=:?1<1??84=6:4>64134=347==6:?4<<<4:?16;5o5334892>e2:8=7097c;112>;00m08>;5279g9770<5>2m6><9;<5:5?55>27<5?4<279>3<5=;;<01:7;:205?81>=399:638978063=:?0=1??84=6;;>64134=257==6:?4=d<4:?16;4m5334892?c2:8=7096e;112>;01o08>;527`29770<5>k:6><9;<555?55>27<:n4<279>321=;;<01:9j:205?810n399:638818063=:?1;1??84=6:1>64134=3?7==6:?4<1<4:?16;;<5334892042:8=70994;112>;0><08>;527749770<5><<6><9;<55<?55>27<:44<279>33g=;;<01:8m:205?811l399:6386d8063=:??l1??84=653>64134=<=7==6:?437<4:?16;:=5334892132:8=70985;112>;0??08>;5276:9770<5>=26><9;<54e?55>27<;o4<279>32e=;;<01:9k:205?xud?3:1>vPl7:?5a0<5>=1vn850;0xZf0<5?o>6?8<;|q`1?6=:rTh9639e48127=z{j>1<7<t^b6893c22;<:7p}l3;296~Xd;27=i84=5g9~wf4=83;?wSm=;<650?55j27?:>4<2c9>034=;;h0198>:20a?8218399n63;0`811c=:<:h1>;>4=5:g>64e34>i=7==b:?7ea<4:k168l7533`891g22:8i70:n1;11f>;31m08>o5248;977d<5=3>6><m;<6:5?55j27?4l4<2c9>2`3=:?:0q~m>:184[e634<i?7?i3:?52`<f927=:h4j4:?522<5>916:nk5276893d52:8=7p}l0;291~Xd827=9i4n1:?51a<b<27=994=619>2fc=:?90q~li:181[da34<hi7<92:pf`<72;qUnh526bg9637<uzo:6=4=bz\f5>;2:h0j=63:338b5>;28h0j=63:0c8b5>;28j0j=63:0e8b5>;29j0j=63:1e8b5>;29l0j=63:1g8b5>;2880j=63:038b5>;2:m0j=63:2d8b5>;3nh0j=63;fc8b5>;2;:0j=63:358b5>;2:k0j=63:458b5>;2<k0j=63:4b8b5>;2<m0j=63:4d8b5>;2<o0j=63:518b5>;2=80j=63:538b5>;2=:0j=63:448b5>;2<?0j=63:468b5>;2<10j=63:488b5>;2<h0j=63:558b5>;2nk09:=525ga9636<5<lo6>8;;<7ea?51<27>jk4<659>2fc=:<l0q~k?:187[c734=>47o>;<567?g634<hi7<90:p`c<72;qUhk526bf9632<uznn6=4>5z\ga>;3n=09:<524769e4=:<?91m<524709e4=:<?;1m<524729e4=:<:81m<5243d9e4=:<;h1m<524359e4=:<;91m<5240d9e4=:<<=1m<524469e4=:<<:1m<5245a9e4=:<=21m<526bf9635<5=<>6<j6;<653?7c02wxhi4?:6y]`a=:>kn1m<526cf9a1=:>l31i9526dg9636<5?h<6?8?;<4``?41:2wxhn4?:5y]`f=:>lo1>8h4=7ag>70634<oo7<:f:p`6<72;qUh>526bf960`<uzi36=4:{_a;?81203o?709n9;152>;2<=0n8639ce8125=z{kn1<7;m{_`g?81203k?709:3;c7?81f139=9638378:3>;1jm02;639e88:3>;1mh02;639e98:3>;0:002;638278:3>;0:;02;6381d8:3>;09h02;638178:3>;09;02;6380d8:3>;08h02;638078:3>;1>l02;6395e8:3>;2:h0j863:338b0>;28h0j863:0c8b0>;28j0j863:0e8b0>;29j0j863:1e8b0>;29l0j863:1g8b0>;2880j863:038b0>;2:m0j863:2d8b0>;3nh0j863;fc8b0>;2;:0j863:358b0>;2:k0j863:458:3>;2<k02;63:4b8:3>;2<m02;63:4d8:3>;2<o02;63:518:3>;2=802;63:538:3>;2=:02;63:448:3>;2<?02;63:468:3>;2<102;63:488:3>;2<h02;63:558b0>;2nm08:8525gg9733<5<lm6>8:;<650??034>=?778;<656??034>==778;<654??034>3h778;<6a5??034>jh778;<6b=??034>j9778;<6b5??034>2h778;<6:=??034>29778;<6:5??034>3m778;<606??034>9j778;<61f??034>9;778;<617??034>:j778;<663??034>>8778;<664??034>?o778;<67<??034<i>778;<4a5??034>=97l?;<653?ge3tyj87>5137xZd2<5>?;6494=67e><1<5>?96494=67a><1<5>?=6494=677><1<5>?26494=2;f><1<5:h?6494=2ab><1<5:n36494=2fb><1<5:nh6494=2ff><1<5:o;6494=2g1><1<5:o?6494=2c3><1<5:k96494=2c7><1<5:k=6494=2c;><1<5:kj6494=2c`><1<5:kn6494=2`3><1<5:h96494=2`5><1<5:h36494=2`b><1<5:hh6494=2`f><1<5:i;6494=2a1><1<5:i?6494=2a5><1<5:i36494=2a`><1<5:in6494=2f3><1<5:n96494=2f7><1<5:n=6494=2;g>d2<5:h86l:4=2a:>d2<5:n<6l:4=2f:>d2<5:ni6l:4=2fg>d2<5:nm6l:4=2g2>d2<5:o86l:4=2;e>d2<5:k:6l:4=2c0>d2<5:k>6l:4=2c4>d2<5:k26l:4=2ca>d2<5:ko6l:4=2ce>d2<5:h:6l:4=2`6>d2<5:h<6l:4=2`:>d2<5:hi6l:4=2`g>d2<5:hm6l:4=2a2>d2<5:i86l:4=2a6>d2<5:i<6l:4=2aa>d2<5:io6l:4=2ae>d2<5:n:6l:4=2f0>d2<5:n>6l:4=6c:>gg<5?i?6494=7a6><1<5?h;6494=7;g><1<5?3h6494=7;a><1<5?3j6494=7;:><1<5?336494=7;4><1<5?3=6494=7;6><1<5?3?6494=7d2><1<5?l;6494=7`;><1<5?hh6494=7`a><1<5?>36494=76:><1<5?>j6494=76a><1<5?>h6494=76g><1<5?>n6494=76e><1<5?<36494=74g><1<5?<i6494=74`><1<5??>6494=77`><1<5??36494=77:><1<5??j6494=77a><1<5?8o6494=70f><1<5?826494=5d5><1<5=l<6494=70a><1<5?8h6494=425><1<5<;36494=5d;><1<5<?<6494=476><1<5<?j6494=47;><1<5<?o6494=47a><1<5<<;6494=47f><1<5<<86494=442><1<5<<=6494=447><1<5<<26494=444><1<5<<h6494=44b><1<5<<m6494=44g><1<5<=96494=453><1<5<on6494=4ga><1<5<o<6494=4g0><1<5<nm6494=4fa><1<5<n<6494=4f0><1<5<im6494=4aa><1<5<kj6494=4c4><1<5<k86494=4;e><1<5<3i6494=4;4><1<5<386494=4:e><1<5<2i6494=4:4><1<5<lo6oo4=4df>gg<5<lm6oo4=7a4><1<5?i26494=614><1<5?kn6494=6d1><1<51?h6494=97a><1<51?j6494=97:><1<51?36494=974><1<51?>6494=977><1<51?86494=971><1<51?:6494=973><1<51>m6494=96f><1<51>o6494=96`><1<51>j6494=96:><1<51>36494=964><1<51>=6494=966><1<51>?6494=960><1<51>96494=962><1<51<86494=941><1<51<:6494=943><1<51?m6494=97f><1<51?o6494=975><1<51>i6494=963><1<5>2>6494=6;3><1<5>3i6494=6c1><1<5>k86494=6c7><1<5>k>6494=6c5><1<5>k<6494=6c;><1<5>2=6494=6:4><1<5>236494=6::><1<5>2j6494=6:a><1<5>2h6494=6:g><1<5>2n6494=6:e><1<5>3:6494=6;1><1<5>386494=6;7><1<5>3>6494=6;5><1<5>3<6494=6;;><1<5>326494=6;b><1<5>3h6494=6;g><1<5>3n6494=6;e><1<5>k;6494=6c2><1<5><:6494=64`><1<5>=<6494=65f><1<5>=m6494=6:3><1<5>2:6494=6:1><1<5>286494=6:7><1<5><96494=640><1<5><?6494=646><1<5><=6494=644><1<5><36494=64:><1<5><j6494=64a><1<5><o6494=64f><1<5><m6494=653><1<5>=:6494=651><1<5>=86494=657><1<5>=>6494=655><1<5>=36494=65:><1<5>=j6494=65a><1<5>=h6494=65g><1<5?h26494=7`b><1<5?oo6494=755><1<5?<j6494=74:><1<5??<6494=775><1<5=<>6o=4=544>g7<uzni6=4={_fa?82a<39:j6s|30494?13s42i;7?i3:?0=a<3<278n>4;4:?0g<<3<278h:4;4:?0`<<3<278ho4;4:?0`a<3<278hk4;4:?0a4<3<278i>4;4:?0=c<3<278m<4;4:?0e6<3<278m84;4:?0e2<3<278m44;4:?0eg<3<278mi4;4:?0ec<3<278n<4;4:?0f0<3<278n:4;4:?0f<<3<278no4;4:?0fa<3<278nk4;4:?0g4<3<278o>4;4:?0g0<3<278o:4;4:?0gg<3<278oi4;4:?0gc<3<278h<4;4:?0`6<3<278h84;4:?460<b127<><4j9:?45a<b127<=44j9:?450<b127<=<4j9:?44a<b127<<44j9:?440<b127=;:4=5g9>221=:?;019h7:20a?83bi3o270;j6;g:?83b:3o270;ke;g:?83ci3o270;k6;g:?83c:3o270;le;g:?83di3o270;n6;g:?83f:3o270;6e;g:?83>i3o270;66;g:?83>:3o270;7e;g:?83?i3o270;76;g:?82e83o270:nc;g:?82f03o270:n4;g:?82f83o270:6c;g:?82>03o270:64;g:?82>83o270:79;g:?825m3o270:=a;g:?825>3o270:=2;g:?826m3o270::3;g:?823n3o270:;b;g:?823?3o270886;g7?821=3;?863;648207=:<??1=9?4=546>42734>=97?<f:?720<6;l168;;515f8910228>h70:95;36`>;3><035:524779<<0<5=<>6>=l;<651?54l27?:84<3d9>033=;:l01988:07b?821?39=n63;66802d=:<?=144o4=544>=??34>=;7667:?722<?1?168;9512789100289870:97;305>;3>>0:?=52475957`<5=<<6<<j;<653?75l2wx;8o50;0x923>2l>01:;7:20;?xu0=<0;6?u27469a1=:?<91??64}r563?6=:r7<9;4j4:?411<4:11v:;l:181812j3o?709:9;11<>{t?<n1<7=t=671>`2<5>?=6><7;<565?42n2wx;8k50;0x923?2:82709:3;g7?xu0>90;6?u27`;960d<5>l96h:4}r5e7?6=:r7<9k4j4:?4b7<4:11v:h;:180812n399463859875>;0=:0?=6s|7g794?4|5>?;6h:4=67a>64?3ty3>i4?:3y>7a0=;;201988:00`?xu?:j0;6?u23e6977><5=<<6<;7;|q;6g<72;q6?i<533:89100288i7p}72`83>7}:;m:1??64=544>44f3ty3>44?:3y>7fc=;;201988:00:?xu?:10;6?u23ba977><5=<<6<<7;|q;63<72;q6?n6533:89100288=7p}72483>7}:;j<1??64=544>4423ty3>94?:3y>7f2=;;201988:007?xu?::0;6?u23b0977><5=<<6<<<;|q;67<72;q6?n>533:8910228?i7p}72083>7}:;ko1??64=546>42e3ty3>=4?:3y>7ge=;;20198::06b?xu?9o0;6?u23cc977><5=<>6<:6;|q;5`<72;q6?o6533:8910228>37p}71e83>7}:;k<1??64=546>4203ty3=o4?:3y>7g4=;;20198::065?xu?9h0;6?u23c2977><5=<>6<::;|q;5<<72;q6?lk533:89102289o7p}71983>7}:;hi1??64=544>4303ty3=:4?:3y>7dg=;;201988:001?xu?9?0;6?u23`:977><5=<<6<<>;|q;50<72;q6?l8533:89100288;7p}71583>7}:;h>1??64=544>47a3ty3=>4?:3y>7d4=;;201988:03f?xu?9;0;6?u23`2977><5=<<6<?k;|q;71<72;q6?h:533:89100289h7p}73283>7}:;l81??64=544>45e3ty3??4?:3y>7`6=;;201988:075?xu?;80;6?u23eg977><5=<<6<=n;|q;75<72;q6?im533:8910028927p}72g83>7}:;mk1??64=544>45?3ty3>h4?:3y>7a>=;;201988:014?xu?:>0;6?u23bc977><5=<<6<=9;|q;5f<72;q6?o:533:8910028997p}71083>7}:;0o1??64=544>4403ty3?k4?:07x92372:83708=a;06b>;2:h0??63:33877>;28h0?463:0c87<>;28j0?463:0e87<>;29j0?463:1e87<>;29l0?463:1g87<>;2880?463:0387<>;2:m0?463:2d87<>;3nh0?463;fc87<>;2;:0?463:3587<>;2:k0?46s|7g594?73s4=>>7==8:?66d<3<27>??4;4:?64d<3127><o4;9:?64f<3127><i4;9:?65f<3127>=i4;9:?65`<3127>=k4;9:?644<3127><?4;9:?66a<3127>>h4;9:?7bd<3127?jo4;9:?676<3127>?94;9:?66g<312wx4>k50;0x91`32;?m709<6;11<>{t0:h1<7=t=673>64e34<?h7==8:?50`<b<2wx4>o50;6x923e2:8i709:6;11f>;1<j08>55265f9a1=z{1926=4:{<566?55j27<994<2c9>30?=;;h01;:m:20;?803k3o?7p}73983>6}:?<l1?9<4=76b>64?34<?n7k;;|q;72<72:q6:97533:8932f2l>01:h=:205?xu?;?0;65u27`;976g<5?h;6h:4=7g4>70534<?47==8:?50<<b<27=;44=619>361=;;h01;oj:20a?xu?;m0;6>u265d977><5=l<6><m;<41g?55j2wx4>m50;04803m39946394g8f0>;3n?08>o5263`977d<5<:=6><m;<72<?55j27>9:4<2c9>103=;;h018;n:20a?8320399n63:5e806g=:=<h1??l4=443>64e34?>i7==b:?626<4:k169;?533`890012:8i70;94;11f>;2>008>o52575977d<5<<h6><m;<75e?55j27>:k4<2c9>13b=;;h0189=:20a?8308399n63:ed806g=:=lh1??l4=4g4>64e34?n?7==b:?6`c<4:k169il533`890b02:8i70;k3;11f>;2ko08>o525b`977d<5<lo6>=n;<7ea?54i27>jk4<3`9~w2`1290:8v399e806g=:>0i1??l4=7;a>64e34<2m7==b:?5=<<4:k16:46533`893?02:8i70866;11f>;11<08>o52686977d<5?l:6><m;<4e4?55j27=n>4mb:?53<<5=o16:8o533:8933e2l>01;m8:20a?80d1399n639ag8125=:>k;1no5rs92e>5<4s4?<<7==8:?720<?j27?::487:p<5c=839p188k:20;?821=32270:97;55?xu?8m0;6>u257c977><5=<>6564=544>23<uz2;o7>53z?622<4:1168;;5869>031=?=1v5>m:180831<399463;648:0>;3>>0<?6s|81c94?5|5<<:6><7;<651??434>=;76=;|q;4<<72:q698k533:8910220801988:938yv>703:1?v3:5c806==:<??15<524759<5=z{1:<6=4<{<76<?55027?:8460:?722<0n2wx4=850;1x90322:8370:95;:e?821?3=n7p}70583>40|5?l:6h:4=43;>64?34<9m7<91:?66d<3:27>??4;2:?64d<3?27><o4;7:?64f<3?27><i4;7:?65f<3?27>=i4;7:?65`<3?27>=k4;7:?644<3?27><?4;7:?66a<3?27>>h4;7:?7bd<3?27?jo4;7:?676<3?27>?94;7:?66g<3?2wx4==50;3580a83o?70;?6;11<>;1:h09:=5253c904=:=:818<5251c903=:=9h18;5251a903=:=9n18;5250a903=:=8n18;5250g903=:=8l18;52513903=:=9818;5253f903=:=;o18;524gc903=:<oh18;52521903=:=:>18;5253`903=z{1:96=49{<4:`?c334?<=7<:f:?6a`<4:1169hh524d890`b2;?j70;if;06e>{t09;1<78t=7;`>`2<5<<n6?;i;<7ff?55027>in4=5g9>1cc=:=n018hi:36g?xu?890;6;u268`9a1=:=?h1>8h4=4g4>64?34?n47<:f:?6b`<5<;169kh52508yv1an3:1:v399`8f0>;2>1099k525d1977><5<o?6?;i;<7ea?44?27>jk4=369~w2`b290=w0869;g7?831=38>j63:dg806==:=l:1>8h4=4df>74d34?mj7<=c:p3cb=83<p1;77:d6890052;?m70;kb;11<>;2lj099k525gg9677<5<lm6?<>;|q4bf<72?q6:495e59>10`=:<l018j8:20;?83c038>j63:fd8153=:=ol1><84}r5ef?6=>r7=5;4j4:?61f<5=o169i=533:890b32;?m70;ie;03f>;2no09<o5rs6db>5<1s4<297k;;<76=?42n27>ok4<299>1a6=:<l018hj:323?83an38;<6s|7g;94?0|5?3?6h:4=475>73a34?hn7==8:?6gf<5=o169kk51g7890`a28l>7p}71183><}:<o=1??64=546>=g434>=976n2:?720<?i8168;;58`289100213i70:97;::b>;3>>035i524759<<e<uz2;97>53z?56f<4:116;>652728910028;h7p}8f983>6}:>>=1>;>4=5d;>64?34<hm7<90:p<63=838p19h;:343?821139:j6s|89294?5|5:n>6h:4=97`>64?34=<h7k;;|q;3c<72:q6?i=5e59><0d=;;201:9l:d68yv>0m3:1?v3<d08f0>;?=h08>55276`9a1=z{1=o6=4<{<1`b?c3342>57==8:?43d<b<2wx4:m50;1x96ec2l>015;7:20;?81013o?7p}77c83>6}:;jh1i952845977><5>=36h:4}r:4=?6=;r78o:4j4:?;10<4:116;:85e59~w=1?2908w0=l5;g7?8>2<3994638748f0>{t0>=1<7=t=2a0>`2<51?86><7;<540?c33ty3;;4?:2y>7f7=m=1648<533:892142l>0q~685;297~;4jo0n863750806==:?>81i95rs957>5<4s49ih7k;;<:64?55027<;<4j4:p<25=839p1>lm:d689=2a2:8370980;g7?xu??;0;6>u23c;9a1=:0=o1??64=64e>`2<uz2<=7>53z?0f2<b<2738i4<299>33c=m=1v59?:18085e=3o?706;c;11<>;0>m0n86s|87g94?5|5:h:6h:4=96b>64?34==n7k;;|q;2a<72:q6?lh5e59><1?=;;201:8n:d68yv>1k3:1?v3<ae8f0>;?<108>55277;9a1=z{1<i6=4<{<1bf?c3342?;7==8:?42=<b<2wx4;o50;1x96g>2l>015:9:20;?811?3o?7p}76883>6}:;h=1i952857977><5><=6h:4}r:5<?6=;r78m84j4:?;01<4:116;;;5e59~w=002908w0=n3;g7?8>3;3994638658f0>{t0?<1<7=t=2c2>`2<51>96><7;<557?c33ty3:84?:2y>7<`=m=1649?533:892052l>0q~677;297~;4m:0n863762806==:?1>1i95rs9:5>5<4s49n=7k;;<:56?55027<4>4j4:p<=3=839p1>ji:d689=062:8370972;g7?xu?0=0;6>u23ef9a1=:0?:1??64=6:2>`2<uz23?7>53z?0`g<b<2739k4<299>3=6=m=1v56=:18085c13o?706:e;11<>;0?o0n86s|89394?5|5:n<6h:4=97g>64?34=<i7k;;|q;3d<72:q6?n75e59><00=;;201:98:d68yv>1n3:1?v3<b28f0>;?<k08>55277a9a1=z{1<?6=4<{<1:`?c3342?<7==8:?424<b<2wx8=?50;0x96b12l>01>j::20;?xu3890;6?u23e69a1=:;m91??64}r1eb?6=:r78h?4j4:?0`4<4:11v>hj:18185c83o?70=lf;11<>{t;on1<7<t=2af>`2<5:io6><7;|q0bf<72;q6?nm5e59>7fd=;;20q~=ia;296~;4k10n863<c6806==z{:l26=4={<1`2?c3349h97==8:p7c>=838p1>m;:d6896e42:837p}<f683>7}:;j81i9523b3977><uz9m:7>52z?0g5<b<278nk4<299~w6`22909w0=me;g7?85el39946s|3g694?4|5:hh6h:4=2`a>64?3ty8j>4?:3y>7gg=m=16?o7533:8yv5a:3:1>v3<b98f0>;4j>08>55rs2d2>5<5s49i:7k;;<1a1?5502wx?hh50;0x96d52l>01>l>:20;?xu4ml0;6?u23c29a1=:;hl1??64}r1f`?6=:r78mh4j4:?0ea<4:11v>kl:18185fk3o?70=nb;11<>{t;lh1<7<t=2cb>`2<5:k26><7;|q0ad<72;q6?l65e59>7d1=;;20q~=j9;296~;4i?0n863<a4806==z{:o36=4={<1b0?c3349j?7==8:p7`1=838p1>o=:d6896g62:837p}<e783>7}:;h:1i95238d977><uz>;47>52z?0a1<b<278i>4<299~w1602909w0=j2;g7?85b939946s|41494?4|5:o;6h:4=2fe>64?3ty?<84?:3y>7ac=m=16?ij533:8yv27<3:1>v3<db8f0>;4lk08>55rs520>5<5s49om7k;;<1g=?5502wx8=<50;0x96b?2l>01>j8:20;?xu4nk0;6?u23bc9a1=:;j31??64}r1e4?6=:r78n94j4:?0f6<4:11v>k::18185>m3o?70=6d;11<>{t?jo1<7<t=6c:>76734=397==8:p3a?=838p1:o6:335?81>839946s|7d694?4|5>k26?=8;<5:f?5502wx;hl50;0x92g>2;>o709n2;11<>{t?li1<7<t=6c:>4`034=j?7==8:p3`b=838p1:o6:0d:?81f<39946s|7dg94?4|5>k26<hl;<5b1?5502wx;hh50;0x92g>28ln709n6;11<>{t?o:1<7<t=6c:>76534=j;7==8:p3c7=838p1:o6:327?81f039946s|7bd94?4|5>k26?>8;<5;2?5502wx;i>50;0x92g>2;:270977;11<>{t?m;1<7<t=6c:>76c34=347==8:p3a4=838p1:o6:32e?81?139946s|7e194?4|5>k26??=;<5;e?5502wx;i:50;0x92g>2;;?7097b;11<>{t?m?1<7<t=6c:>77?34=3o7==8:p3a0=838p1:o6:33b?81?l39946s|7e594?4|5>k26??k;<5;a?5502wx;i650;0x92g>2;;m7097f;11<>{t?mk1<7<t=6c:>74434=2=7==8:p3ad=838p1:o6:306?81>:39946s|7ea94?4|5>k26?<7;<5:7?5502wx;ij50;0x92g>2;8j70964;11<>{t?mo1<7<t=6c:>74b34=297==8:p3a`=838p1:o6:313?81>>39946s|7d294?4|5>k26?=<;<5:3?5502wx;h?50;0x92g>2;9>70968;11<>{t?l81<7<t=6c:>75>34=257==8:p3`5=838p1:o6:31a?81>i39946s|7d794?4|5>k26?=j;<5:g?5502wx;h850;0x92g>2;>;7096d;11<>{t?l=1<7<t=6c:>72334=2i7==8:p3`>=838p1:o6:365?81>n39946s|7d;94?4|5>k26?:6;<5b4?5502wx;ho50;0x92g>2;>i709n1;11<>{t?hk1<7=t=6c:>4`234=397k;;<555?5502wx;o;50;1x92g>2;:i70960;g7?811k39946s|7b294?5|5>k26?<l;<5:f?c334=<;7==8:p3f1=839p1:o6:361?81f:3o?7098e;11<>{t?j21<7=t=6c:>4`134=j?7k;;<54b?5502wx;n750;1x92g>28l3709n4;g7?81?839946s|7bc94?5|5>k26<hm;<5b1?c334=3=7==8:p3fd=839p1:o6:0dg?81f>3o?70972;11<>{t?ji1<7=t=6c:>76634=j;7k;;<5;7?5502wx;nj50;1x92g>2;:8709n8;g7?81?<39946s|7``94?5|5>k26?>9;<5;2?c334==>7==8:p3de=839p1:o6:32;?81??3o?70993;11<>{t?hn1<7=t=6c:>76d34=347k;;<550?5502wx;lk50;1x92g>2;:n70979;g7?811=39946s|7`d94?5|5>k26??>;<5;e?c334==:7==8:p3g6=839p1:o6:330?81?j3o?70997;11<>{t?k;1<7=t=6c:>77034=3o7k;;<55<?5502wx;o<50;1x92g>2;;27097d;g7?811139946s|7c194?5|5>k26??l;<5;a?c334==m7==8:p3g2=839p1:o6:33f?81?n3o?7099b;11<>{t?k<1<7=t=6c:>74534=2=7k;;<55`?5502wx;o950;1x92g>2;8?70962;g7?811m39946s|7c:94?5|5>k26?<8;<5:7?c334==j7==8:p3g?=839p1:o6:30:?81><3o?70980;11<>{t?kk1<7=t=6c:>74c34=297k;;<545?5502wx;ol50;1x92g>2;8m70966;g7?810:39946s|7ca94?5|5>k26?==;<5:3?c334=<?7==8:p3gb=839p1:o6:317?81>03o?70984;11<>{t?ko1<7=t=6c:>75?34=257k;;<541?5502wx;oh50;1x92g>2;9j7096a;g7?810>39946s|7b394?5|5>k26?=k;<5:g?c334=<47==8:p3f4=839p1:o6:31e?81>l3o?70989;11<>{t?j91<7=t=6c:>72434=2i7k;;<54e?5502wx;n:50;1x92g>2;>>7096f;g7?810j39946s|7b794?5|5>k26?:7;<5b4?c334=<o7==8:p3f0=839p1:o6:36b?81f93o?7098d;11<>{t>k>1<7<t=7`7>67a34<om7<92:p2g3=838p1;l::23e?80ci38=86s|6d`94?5|5?o26><7;<4fe?c334<n47==b:p2`e=838p1;kn:20;?80b03o?7p}9bd83>7}:>kn1??64=7`:>`2<uz<h<7>53z?5f=<b<27=n44<299>2gg=m=1v;m>:18180e0399n639b`806==z{?i96=4={<4ag?55027=no4j4:p2f5=838p1;lm:20;?80e?38>j6s|6cd94?3|5?ho6ol4=7``>gd<5?h<6>?i;<4a=?de34<im7lm;|q47<<72;q6:57530d893ba2;<?7p}83c83>7}:>1h1?<h4=7f4>7043ty<?n4?:3y>2=e=;8l01;ji:342?xu0;m0;6?u269f974`<5?nn6?8=;|q47`<72;q6:5k530d893c72;<87p}83g83>7}:>1l1?<h4=7f4>7033ty<8=4?:3y>2<6=;8l01;jj:347?xu0<80;6?u2683974`<5?nn6?8<;|q407<72;q6:4<530d893ba2;<87p}84283>7}:>091?<h4=7f4>7053ty<?l4?:3y>2=g=;8l01;ji:341?xu0<<0;6ou26dd974`<5>826><m;<512?55j27<>?4<2c9>34c=;;h01:?n:20a?816>399n63813806g=:?9o1??l4=62b>64e34=;:7==b:p2=4=83>p1;7j:23e?80e:3o?708m1;g7?80c038=?6s|69494?5|5?l:6l?4=7d3>d7<5?h=6>?i;|q5ef<72;q6;>85e59>2ae=;8l0q~9;4;296~;1ml08=k526dd960c<uz<<n7>52z?5a=<4:116:hj5bc9~w22d290=w09>e;11<>;09o099k526e59636<5?nn6?8>;<4g6?41:27=i=4=5g9~w22c290<w09=2;11<>;0::099k526e59637<5?no6?8?;<4gb?41827=h?4=5g9>2`6=:?:0q~9;e;292~;0:?08>552735960`<5?n96?8<;<4f6?41827=i94=619>2`5=:?;0q~9;f;292~;0:008>55273c960`<5?n96?8;;<4f7?41827=i94=609>2`4=:<l0q~9;9;2956}:>1k1>;<4=7;0>70534<2>7<92:?5=4<5>;16:4>5270893>a2;<97087e;056>;10m09:?5269a9634<5?2i6?8=;<4;=?41:27<=?4<299>345=:<l01;j;:37e?80c=38>j639d98124=:>m91>;<4=7f5>70534<om7<90:p31g=832p1:?9:20;?816?38>j639cb811c=:>mo1>;>4=7f1>70734<o87<94:?5a5<5>;16:io524d8yv13j3:14v381`806==:?8h1>8h4=7a`>70734<oh7<:f:?5`c<5=o16:i<5273893be2;?m708j0;055>{t?=<1<7?<{<4;e?42n27=5>4=5g9>2<4=:<l01;7>:37e?80>838>j6398g811c=:>1o1>8h4=7:g>73a34<3o7<:f:?5<g<5=o16:57524d892612:83709?7;06b>;1l=09:>526e79636<5?h?6?8<;<4a1?41;27=h>4=609>2a>=:?80q~9;7;2956}:>1k1>;>4=7;0>70734<2>7<90:?5=4<5>916:4>5272893>a2;<;7087e;054>;10m09:=5269a9636<5?2i6?8?;<4;=?41827<<l4<299>35d=:<l01;j;:342?80c=38==639b58121=:>k?1>;:4=7f0>70434<on7<90:p31>=83;8w087a;055>;11:09:<526809637<5?3:6?8>;<4:4?41927=4k4=609>2=c=:?;01;6k:342?80?k38==6398c8124=:>131>;?4=62f>64?34=;j7<:f:?5`1<5>916:i;5270893b42;<?708k6;057>;1l109:=526ec9637<uz<3<7>52z?5=`<5>816:o<533:8yv0?93:1>v39b2806==:>0o1>8h4}r44b?6=:r7=5h4=619>2g7=;;20q~8n9;29f~;11m0j=6399b8b5>;11k0j=6399`8b5>;1100j=639998b5>;11>0j=639978b5>;11<0j=639958b5>;1m>08=k5rs75`>5<5s4<nh7==8:?5`3<5=o1v;68:18180c<38=>639c6806==z{?236=4<{<4g1?41;27=o44<299>2fg=:<l0q~8nd;297~;0;>08>55272:960`<5?n=6?8?;|q53a<72:q6:i;5276893gb2:83708nf;06b>{t>hk1<7<t=7d3>64?34<o47<:f:p2dd=838p1;h>:20;?80c>38==6s|68d94?4|5?3?6><7;<4a1?42n2wx:l>50;0x93?22:83708m5;054>{t>h;1<7<t=7;5>64?34<i97<92:p2d4=838p1;78:20;?80e=38==6s|6`194?4|5?336><7;<4a0?42n2wx:l:50;0x93?>2:83708m4;054>{t>h?1<7<t=7;b>64?34<i87<92:p2d0=838p1;7m:20;?80e<38==6s|6`594?4|5?3h6><7;<4g7?4182wx:l650;0x93?c2:83708k3;06b>{t>>o1<7<t=7`3>64?34<n;7<91:p2=3=83>p1;m::20;?80b?38>j639b7811c=:>j<1>8h4}r4;0?6==r7=o94<299>2f3=m=16:h95272893d12;<;708l6;054>{t>191<7:t=7a7>`2<5?h36><7;<4ag?g634<io7k;;|q5bg<72;q6;=85e59>35>=;8l0q~8i2;297~;0800j?6380b8b7>;08<08<85rs7d`>5<5s4=;m7k;;<53g?56n2wx:k=50;1x926c2h901:??:`18926>2::>7p}9fe83>7}:?9o1i952702974`<uz<m87>53z?454<f;27<=94n3:?44a<48<1v;hj:181816:3o?709>4;12b>{t>o?1<7=t=636>d5<5>;36l=4=632>6623ty=jk4?:3y>340=m=16;<6530d8yv0a>3:1?v38188b7>;09j0j?638148040=z{>:;6=4={<52e?c334=:o7=>f:p2c1=839p1:?k:`1892472h901:?6:226?xu0880;6?u270g9a1=:?;:1?<h4}r4e<?6=;r7<><4n3:?461<f;27<=i4<049~w2652909w09=2;g7?815<39:j6s|6g;94?5|5>8>6l=4=60;>d5<5>8:6>>:;|q446<72;q6;?85e59>37>=;8l0q~8ia;296~;0:k0j?638248040=z{>:?6=4={<51=?c334=9n7=>f:p37e=839p1:>8:23e?817=39?>638098041=z{>8o6=4<{<53f?56n27<<44<439>35e=;9>0q~9=e;297~;08o08=k5271f9714<5>;;6>>;;|q46c<72:q6;<=530d892762:>9709>4;130>{t?::1<7=t=634>67a34=:97=;2:?45=<48=1v:=>:180816j39:j638188007=:?8i1?=:4}r506?6=;r7<=k4<1g9>34b=;=801:<?:227?xu0;:0;6>u2731974`<5>8:6>:=;<510?57<2wx;>:50;1x92402:;m709=5;176>;0:108<95rs616>5<5s4=9m7=>f:?46g<48=1v;9n:18180303o?70889;12b>{t><91<7<t=754>70534<<47=>f:p204=833p1;:7:261?803139?>6394`8007=:>=h1?9<4=76`>62534<?h7=;2:?50`<4<;16:9h5350893102:;m7p}95183>6}:>>21>8h4=74a>64?34<=o7k;;|q514<72;q6::65272893112:837p}97183>0}:>?o1no5267f9fg=:>?=1?<h4=74b>gd<5?<26ol4}r441?6=:r7=:n4<299>231=:<l0q~884;296~;1>m08>55267`9a1=z{?=86=4<{<45<?55027=:i4n1:?52a<b<2wx::<50;0x930?2:8i7089a;11<>{t>>;1<7=t=74;>`2<5?<j6h:4=74:>64?3ty=:k4?:3y>23c=;;201;86:d68yv02n3:19v395e8af>;1=j0in63955805c=:><=1no526449fg=z{?<=6=4={<46f?55027=994=5g9~w3022909w08:9;11<>;1=h0n86s|67694?4|5??36><7;<46=?c33ty=:>4?:3y>20e=;;201;;7:d68yv01:3:1?v3954806==:><i1m<5264a9a1=z{?<:6=4={<461?55j27=9:4<299~w3072908w08:5;g7?802?3o?708:6;11<>{t><o1<7<t=77g>64?34<>:7k;;|q7b`<72;q68k7524d891`e2:837p};fe83>7}:<ok1i9524g`977g<uz>mj7>52z?7b<<5>9168ko533:8yv2ak3:1>v3;f98f0>;3n008=k5rs413>5<5s4?9o7<:f:?66`<4:11v8<i:181835l3o?70;=e;11e>{t=:;1<7<t=40`>70734?9h7==8:p152=838p18>?:37e?837:39946s|51194?4|5<::6h:4=421>64f3ty><84?:3y>156=:?:018>>:20;?xu2:?0;6?u250;960`<5<;m6><7;|q666<72;q69<k5e59>14`=;;k0q~;=7;296~;29009:=5250g977><uz?987>52z?65a<b<27>=h4<2`9~w04?2909w0;>a;06b>;29m08>55rs406>5<5s4?:o7k;;<72`?55i2wx9?750;0x907f2;<;70;>c;11<>{t=;:1<7<t=43a>73a34?:57=>f:p177=838p18?m:343?836i39:j6s|53094?4|5<;36h:4=43a>67a3ty>=94?:3y>151=:<l018>k:20;?xu2980;6?u251a9a1=:=9n1??o4}r721?6=:r7><:4=619>15e=;;20q~;>2;296~;28k0n863:0b806d=z{<;=6=4={<73<?42n27><o4<299~w0742909w0;?a;g7?837j399m6s|50594?4|5<:36?8?;<73e?5502wx9=k50;0x906>2;?m70;?7;12b>{t=9l1<7<t=42:>70734?;47=>f:p146=838p18>9:d68906>2:;m7p}:3483>f}:<o<1i95253c977><5<kj6l?4=4c4>d7<5<k86l?4=4;e>d7<5<3i6l?4=4;4>d7<5<386l?4=4:e>d7<5<2i6l?4=4:4>d7<uz<8n7>52z?66d<4:0169=<5e59~w34a290iw0;<2;11<>;2ml0j=63:ec8b5>;2m>0j=63:e28b5>;2lo0j=63:dc8b5>;2l>0j=63:d28b5>;2ko0j=63:cc8b5>{t>:k1<7<t=40b>`2<5<996><6;|q504<72;q6:?l5e59>27g=;8l0q~8;2;296~;1:k08>55263a9a1=z{?>;6=4={<6e2?55027?j:4j4:p267=838p1;<k:`3890542:837p}93583>7}:>;o1m<52526977><uz<8j7>52z?676<b<27>?94<2`9~w0502909w08=9;c2?835j39946s|62g94?4|5<9?6h:4=40a>64f3ty=?i4?:3y>0cg=;;k018<m:d68yv2a=3:18v392e806g=:>;o1??l4=70:>64e34?;<7=>f:p26e=838p18>>:20b?82aj3o?7p}:3883>g}:=;i1?<h4=4cb>64e34?j;7==b:?6e6<4:k1694h533`890?e2:8i70;67;11f>;21:08>o5259d977d<5<2i6><m;<7;3?55j2wx:>750;0x90552l>018<k:20b?xu1;10;6?u251c977g<5<8n6h:4}r403?6=:r7><i4j4:?65f<4:h1v8=7:18`8051399463:0`87f>;28k0?n63:0b87f>;28m0?n63:1b87f>;29m0?n63:1d87f>;29o0?n63:018007=:=;i1?9<4=40a>1d<uz<897>5cz?56`<4:1169=65350890602:>970;>a;176>;290088?5251390g=:=9818o5253f90g=:=;o18o524gc90g=:<oh18o5252690g=z{?996=4:{<41`?55027><44<439>14d=;=8019h6:261?834;3>i7p}93783>7}:=8l1i9525gd9731<uz<8?7>52z?56`<b<27>jk4=5c9~w3572909w08=d;g7?83am38>n6s|52494?4|5?826h:4=4dg>73e3ty>n;4?:3y>1dd=;8l018ol:227?xu2j<0;6>u25`:974`<5<k=6>:=;<7b=?57<2wx9o:50;1x90g32:;m70;n2;176>;2i<08<95rs4`0>5<4s4?j<7=>f:?6=`<4<;169l?53168yv3e:3:1?v3:9b805c=:=0k1?9<4=4;g>6633ty>n<4?:2y>1<>=;8l01879:261?83>139;86s|5c294?5|5<3?6>?i;<7:6?53:27>584<059~w0ga2908w0;60;12b>;20l088?525839752<uz?ji7>53z?6<f<49o1695o5350890>c2::?7p}:ae83>6}:=121?<h4=4:5>62534?357=?4:p1=3=838p18on:d6890gd2:;m7p}:7c83>7}:=hi1m>525`49753<uz?387>52z?6e2<b<27>m44<1g9~w01f2908w0;n6;c0?83f13k870;n2;131>{t=191<7<t=4c0>`2<5<k>6>?i;|q63<<72:q69l<5a29>1d3=i:1694k53178yv3?:3:1>v3:9g8f0>;2i808=k5rs45;>5<4s4?2i7o<;<7b5?g434?2m7=?5:p1=7=838p187m:d6890?c2:;m7p}:7683>6}:=0k1m>5258f9e6=:=0<1?=;4}r7;4?6=:r7>5:4j4:?6=<<49o1v899:18083>>3k870;69;c0?83>:39;96s|56d94?4|5<386h:4=4;6>67a3ty>;84?:2y>1<4=i:1694;5a29>1=c=;9?0q~;8e;296~;20o0n863:90805c=z{<=?6=4<{<7;a?g434?2=7o<;<7;e?57=2wx9:j50;0x90>e2l>0186k:23e?xu2?:0;6>u259c9e6=:=1n1m>525949753<uz?<o7>52z?6<2<b<27>444<1g9~w0`f2909w0;jf;12b>;2n908<95rs4d:>5<4s4?no7=>f:?6ad<4<;169hj53168yv3a03:1?v3:e9805c=:=l<1?9<4=4g:>6633ty>j:4?:2y>1`2=;8l018k=:261?83b=39;86s|5g494?5|5<o;6>?i;<7ga?53:27>i<4<059~w0`22908w0;kc;12b>;2lh088?525ef9752<uz?m87>53z?6`=<49o169i85350890b>2::?7p}:f283>6}:=m>1?<h4=4f1>62534?o97=?4:p1c4=839p18j?:23e?83dm39?>63:d08041=z{<l:6=4<{<7`g?56n27>ol4<439>1fb=;9>0q~;l9;296~;2ml0n863:f1805c=z{<hm6=4={<7e4?g434?nm7=?5:p1f>=838p18km:d6890cc2:;m7p}:bd83>6}:=lk1m>525df9e6=:=l<1?=;4}r7`3?6=:r7>i:4j4:?6a<<49o1v8lk:18083b>3k870;j9;c0?83b:39;96s|5b494?4|5<o86h:4=4g6>67a3ty>nn4?:2y>1`4=i:169h;5a29>1ac=;9?0q~;l5;296~;2lo0n863:e0805c=z{<hi6=4<{<7ga?g434?n=7o<;<7ge?57=2wx9n:50;0x90be2l>018jk:23e?xu2jh0;6>u25ec9e6=:=mn1m>525e49753<uz?h?7>52z?6`2<b<27>h44<1g9~w0d>2908w0;k6;c0?83c13k870;k2;131>{t=j81<7<t=4f0>`2<5<n>6>?i;|q6f=<72:q69i<5a29>1a3=i:169nk53178yv3d93:1>v3:cg8f0>;2l808=k5rs4`4>5<4s4?hi7o<;<7g5?g434?hm7=?5:p1f6=838p18mm:d6890ec2:;m7p}:4283>7}:=>81i952563974`<uz??>7>52z?62c<b<27>:h4<1g9~w0262909w0;9c;g7?831j39:j6s|55294?4|5<<26h:4=44;>67a3ty>?k4?:3y>130=m=169;;530d8yv34m3:1>v3:628f0>;2>;08=k5rs41g>5<5s4?=<7k;;<76b?56n2wx9>m50;0x903c2l>018;l:23e?xu2;k0;6?u254c9a1=:=<31?<h4}r70e?6=:r7>9:4j4:?613<49o1v;>;:18183ak39:j63:fg8023=z{?:96=4={<7ef?56n27>jh4<679~w3672909w0;:4;11<>;2nm08:;5rs72a>5<5s4??m7==8:?611<b<2wx:=o50;0x902>2:8370;;a;g7?xu1800;6?u255:977><5<>26h:4}r43<?6=:r7>8:4<299>11>=m=1v;>8:181833>399463:468f0>{t>9<1<7<t=466>64?34??:7k;;|q540<72:q698=533:890222l>0189>:342?xu19=0;6>u2540977><5<?86h:4=44f>7063ty==>4?:2y>107=;;2018;=:d68900e2;<:7p}91383>6}:=<:1??64=472>`2<5<<36?8>;|q554<72:q699h533:890372l>0188::342?xu1990;6>u255g977><5<>m6h:4=441>7063ty=<k4?:2y>11b=;;2018:j:d68903a2;<:7p}90d83>6}:==i1??64=46g>`2<5<?h6?8>;|q54a<72:q699l533:8902d2l>018;6:342?xu18j0;6>u2556977><5<>i6h:4=475>7063ty=<>4?:3y>1ce=:<l018hj:244?xu1880;6?u25g`960`<5<lo6>88;|q56=<72=q69:?5272890gf2:8370;nb;06b>;2nm099l5rs704>5<3s4?=i7<90:?6e2<4:1169l6524d890`c2;>o7p}92783>1}:=?h1>;>4=4c0>64?34?j87<:f:?6ba<5<;1v;<::187831038=<63:9g806==:=h:1>8h4=4dg>7503ty=>94?:5y>133=:?:0187m:20;?83>k38>j63:fe816f=z{?886=4;{<756?41827>5:4<299>1<>=:<l018hk:302?xu1:;0;69u254d9636<5<386><7;<7:0?42n27>ji4=179~w346290?w0;:c;054>;20o08>552582960`<5<lo6?>m;|q565<72=q69875272890>e2:8370;7c;06b>;2nm09<=5rs73e>5<3s4?>:7<90:?6<2<4:116956524d890`c28l>7p}91d83>7}:=>81??64=453>`2<uz<:h7>52z?62c<4:1169;j5e59~w37d2909w0;9c;11<>;2>h0n86s|60`94?4|5<<26><7;<753?c33ty==l4?:3y>130=;;20188;:d68yv0613:1>v3:62806==:=?;1i95rs73;>5<5s4?=<7==8:?61`<b<2wx:<950;0x903c2:8370;:b;g7?xu19?0;6?u254c977><5<?36h:4}r421?6=:r7>9:4<299>103=m=1v98i:181821n39:j63;6d8125=z{==;6=4={<644?56n27?:h4=5g9~w10b2909w0:9e;12b>;3>k09:=5rs5a1>5<5s4>h>7=>f:?72g<5>81v98n:181821138=<63;6c805c=z{==:6=4={<645?56n27?:i4=659~w1152909w0:82;12b>;3>m09:>5rs550>5<5s4><?7=>f:?72a<5>81v987:181821039:j63;6e8127=z{=<h6=4={<65=?42n27?:i4<1g9~w15c290=w0::f;12b>;3=>08>o52446977d<5=?;6><m;<67g?55j27?854<2c9~w1762908w0:?b;050>;3;;08>552421960`<uz>:<7>53z?74g<5>:168?h533:891572;?m7p};0g83>6}:<9h1>;<4=50a>64?34>9o7<:f:p05c=839p19>m:342?825?399463;29811c=z{=:o6=4<{<63f?41827?>>4<299>072=:<l0q~:?c;297~;38k099k5240d977><5=8;6?;i;|q757<72>q68>l530d891552:8i70:=f;11f>;3:k08>o52435977d<5=886><m;<62b?55j2wx8k?50;ax916>2:;m70:7d;c2?82e93k:70:nd;c2?82f13k:70:n5;c2?82f93k:70:6d;c2?82>13k:70:65;c2?82>93k:70:7a;c2?xu3kh0;6?u241c974`<5=?m6?8?;|q7fc<721q68;>533:8910a2;?m70:80;06b>;3?8099k52460960`<5==86?;i;<65<?42n27?o?4=609~w1e72903w0:91;11<>;3>o09:=524629636<5==:6?8?;<646?41827?;>4=619>03>=:?:019m=:37e?xu3k80;69u2470977><5=<n6>:=;<6`6?41<27?:i4=619~w1e42908w0:93;11<>;3>m099k5247`960`<uz>h87>52z?721<4:1168;753508yv2a;3:1?v3;088125=:<<l1>8h4=51`>67a3ty?o84?:5y>036=m=168>m524d8912?2:8370:;9;06b>{t<j<1<7:t=542>`2<5=9h6?8?;<67g?55027?8i4=5g9~w1e0290?w0:92;g7?824k38==63;51806==:<<;1>8h4}r6`<?6=<r7?:>4j4:?77f<5>;1688:533:891322;?m7p};c883>1}:<?>1i95242a9635<5=?<6><7;<66<?42n2wx8k<50;6x916f2;<;70:?9;06b>;3;k099k5241`974`<uz>n:7>54z?7<g<5=o1685o533:891022?201988:4c8yv2b03:18v3;93811c=:<0;1??64=546>3?<5=<<68l4}r6f=?6=<r7?5;4=5g9>0<3=;;20198::7c891002<i0q~:ja;290~;31h099k5248;977><5=<>6;l4=544>0b<uz>nn7>54z?7=`<5=o1684j533:891022?i01988:4g8yv2bk3:18v3;a3811c=:<h;1??64=546>3b<5=<<68h4}r6f`?6=<r7?m;4=5g9>0d3=;;20198::7g891002<:0q~:je;290~;3ih099k524`;977><5=<>6;?4=544>07<uz>nj7>54z?7e`<5=o168lj533:891022?801988:408yv2a83:18v3;b3811c=:<k;1??64=546>35<5=<<68=4}r6f3?6=<r7?4h4=5g9>0=b=;;20198::77891002<>0q~:lb;296~;3?809:952475950c<uz>o:7>52z?734<5>8168;9517;8yv2cm3:1>v3;708126=:<?=1=::4}r6gb?6=:r7?;<4=639>031=9>20q~:j0;296~;3?;09:952475952?<uz>n=7>52z?737<5>8168;9516c8yv2b:3:1>v3;738126=:<?=1=:l4}r6f7?6=:r7?;?4=639>031=9>i0q~:j4;296~;3?:09:95247595f2<uz>n97>52z?736<5>8168;9516f8yv2dk3:1>v3;728126=:<?=1=:k4}r6``?6=:r7?;>4=639>031=9<l0q~:le;296~;3>109:9524759536<uz>hj7>52z?72=<5>8168;951738yv2c83:1>v3;698126=:<?=1=;<4}r6g5?6=:r7?:54=639>031=9?90q~:k2;296~;3?909:9524759532<uz>o?7>52z?735<5>8168;951b78yv2c<3:1>v3;718126=:<??1=:h4}r6g1?6=:r7?;=4=639>033=91=0q~:k7;296~;3>o09:95247795=><uz>o47>52z?72c<5>8168;;519;8yv2c13:1>v3;6g8126=:<??1=5o4}r6ge?6=:r7?:k4=639>033=91h0q~:kb;296~;3k;09:?5247795=e<uz>oo7>52z?7g7<5>:168;;519f8yv2cl3:1>v3;c38125=:<??1=n74}r64a?6=:r7?4l4j4:?7<f<49o1v99::18082>83k870:63;c0?82?139;96s|49294?4|5=3:6h:4=5;0>67a3ty?;;4?:2y>0<2=i:168495a29>0<6=;9?0q~:71;296~;31<0n863;96805c=z{==<6=4<{<6:<?g434>2n7o<;<6:0?57=2wx85<50;0x91?>2l>0197m:23e?xu3?10;6>u248a9e6=:<0l1m>5248:9753<uz>3?7>52z?7=a<b<27?5k4<1g9~w11>2908w0:n0;c0?82f;3k870:6c;131>{t<1>1<7<t=5c2>`2<5=k86>?i;|q73d<72:q68l:5a29>0d1=i:168l>53178yv2?=3:1>v3;a48f0>;3i>08=k5rs55a>5<4s4>j47o<;<6bf?g434>j87=?5:p0=0=838p19o6:d6891ge2:;m7p};7b83>6}:<hi1m>524`d9e6=:<h21?=;4}r6;3?6=:r7?mi4j4:?7ec<49o1v99k:18082e83k870:m3;c0?82fk39;96s|49:94?4|5=h:6h:4=5`0>67a3ty?;94?:3y>0=`=i:168o>53178yv20n3:1>v3;8e8f0>;30o08=k5rs5`7>5<4s4>3n7=>f:?7<<<4<;1685m53168yv2e>3:1?v3;93805c=:<0:1?9<4=5;0>6633ty?n:4?:2y>0<0=;8l0197;:261?82>?39;86s|4c:94?5|5=3j6>?i;<6:<?53:27?5o4<059~w1d>2908w0:6e;12b>;31j088?5248d9752<uz>im7>53z?7e7<49o168l>5350891g42::?7p};bc83>6}:<h<1?<h4=5c7>62534>j;7=?4:p0ge=839p19on:23e?82f039?>63;ac8041=z{=ho6=4<{<6ba?56n27?mn4<439>0d`=;9>0q~:me;297~;3j;08=k524c29714<5=h86>>;;|q7f0<72;q685k530d891>a2::?7p};1983>7}:<8l1i952433974`<uz>:?7>53z?767<f;27?>84n3:?75`<48<1v9?6:181825;3o?70:=5;12b>{t<8>1<7=t=505>d5<5=826l=4=501>6623ty?=l4?:3y>071=m=168?7530d8yv26=3:1?v3;2`8b7>;3:m0j?63;278040=z{=;i6=4={<61f?c334>9h7=>f:p040=839p19<j:`1891562h9019<n:226?xu39j0;6?u243d9a1=:<:;1?<h4}r623?6=:r7??94n3:?76`<48<1v9?k:181824:3o?70:<4;12b>{t<:?1<7=t=503>67a34>:i7=;2:?764<48=1v9=9:180825<39:j63;238007=:<;?1?=:4}r603?6=;r7?>54<1g9>070=;=8019<6:227?xu3;10;6>u243a974`<5=8j6>:=;<61`?57<2wx8>750;1x91572:;m70:=e;176>;3;808<95rs51b>5<5s4>8?7=>f:?771<48=1v9:=:18182303o?70:;a;12b>{t<:o1<7=t=56a>d5<5=>n6l=4=564>6623ty?8>4?:3y>01e=m=1689k530d8yv24n3:1?v3;4g8b7>;3=;0j?63;4c8040=z{=>?6=4={<664?c334>>>7=>f:p016=839p19;<:`1891312h9019:i:226?xu3<<0;6?u24469a1=:<<<1?<h4}r675?6=:r7?944n3:?716<48<1v9:9:181822?3o?70::9;12b>{t<<k1<7=t=56:>67a34>?;7=;2:?70d<48=1v9;m:180823l39:j63;4c8007=:<=o1?=:4}r66g?6=;r7?9<4<1g9>01`=;=8019;=:227?xu3=m0;6>u2447974`<5=?86>:=;<662?57<2wx88k50;0x913?2:;m70::9;130>{t>jh1<7<t=7a`>67a34<o;7<:f:p2fe=839p1;j8:23e?80b:38==639e28121=z{?n<6=4={<4g`?56n27=hh4=5g9~w3bc2909w08ke;12b>;1m:09:>5rs7ff>5<5s4<oj7=>f:?5a5<5>=1v;ji:18180b839:j639db8121=z{?o:6=4={<4f1?56n27=h<4=5g9~w3c22909w08j6;12b>;1l809:=5rs7g5>5<5s4<hh7=>f:?5`4<5>81v;mk:18180dm39:j639d08127=z{?in6=4={<4`b?56n27=h<4=629~w3ea2909w08k0;12b>;1l809:95rs7f3>5<4s4<o=7=>f:?5a1<5=o16:h=524d8yv0c93:1>v39d3805c=:>l91>;<4}r4g6?6=:r7=h>4<1g9>2ag=:?90q~8k3;296~;1l=08=k526e`9637<uz<o87>52z?5`0<49o16:il52708yv0c=3:1>v39d7805c=:>m21>;:4}r4g2?6=:r7=h54<1g9>2ad=:?>0q~8k9;296~;1lk08=k526ea9634<uz<h47>511ax93e02l>015l7:202?81203>9709:8;60?81203>?709:3;61?812;3>8709:3;67?85>l3>:70=6d;61?85>l3>870=m3;62?85e;3>970=m3;60?85d13>:70=l9;61?85d13>870=k7;62?85c?3>970=k7;60?85c13>:70=k9;61?85c13>870=kb;62?85cj3>970=kb;60?85cl3>:70=kd;61?85cl3>870=kf;62?85cn3>970=kf;60?85b93>:70=j1;61?85b93>870=j3;62?85b;3>970=j3;60?85>n3>:70=6f;61?85>n3>870=n1;62?85f93>970=n1;60?85f;3>:70=n3;61?85f;3>870=n5;62?85f=3>970=n5;60?85f?3>:70=n7;61?85f?3>870=n9;62?85f13>970=n9;60?85fj3>:70=nb;61?85fj3>870=nd;62?85fl3>970=nd;60?85fn3>:70=nf;61?85fn3>870=m1;62?85e93>970=m1;60?85e=3>:70=m5;61?85e=3>870=m7;62?85e?3>970=m7;60?85e13>:70=m9;61?85e13>870=mb;62?85ej3>970=mb;60?85el3>:70=md;61?85el3>870=mf;62?85en3>970=mf;60?85d93>:70=l1;61?85d93>870=l3;62?85d;3>970=l3;60?85d=3>:70=l5;61?85d=3>870=l7;62?85d?3>970=l7;60?85dj3>:70=lb;61?85dj3>870=ld;62?85dl3>970=ld;60?85dn3>:70=lf;61?85dn3>870=k1;62?85c93>970=k1;60?85c;3>:70=k3;61?85c;3>870=k5;62?85c=3>970=k5;60?81f138>4638a88113=:?h31>8;4=6c:>73334=j57<:3:?4e<<5=;16;l75243892g>2;?;709n9;07b>;0i0098h527`;961e<5>k26?:8;<5b=?43927<m44=3b9>3d?=::<01:o6:312?81f1389n638a88163=:?h31>?>4=6c:>77e34=j57<>5:?4e<<59916;l7521c892g>2;:>709n9;3eb>;0i00:jl527`;960g<5>k26?<>;<4`0?g634<h97o>;<4a4?g634<i?7k;;<502?g634<in7o>;<4f=?g634<nm7o>;<51=?g634=9:7o>;<516?g634=:i7o>;<52e?g634=::7o>;<526?g634=;i7o>;<53e?g634=;:7o>;<531?g434=;47o<;<44<?41927=:o4n1:?52f<f927=954n1:?51<<f927=9l4n1:?51g<f927>994;1:?611<3:27>994;3:?611<3<27>ol4n3:?6ga<f;27>4;4n3:?6<<<f;27?444n3:?7<f<f;27?=h4n3:?764<f;27?8:4n3:?70d<f;27=ii4j4:?720<1?27?:8496:?720<1827?:847e:?720<?l27?:847c:?720<?>27?:84>139>033=98:0198::02e?821=3;;i63;64824a=:<??1==m4=546>47e34>=97?>a:?720<690168;;510:8910228;<70:95;322>;3><0:=8524779542<5=<>6<?<;<651?77j27?:84>549>033=9<90198::0fa?821=398:63;648072=:<?=1il524759763<5=<<64o4=544>4bf34>=;776;<653??d34>=;77m;<653?54?27?::4>539>031=9<:01988:06e?821?3;?i63;66862>;3>>0>563;6686<>;3>>0>;63;6687b>;3>>0<563;6684`>;3>>0<o63;6684f>;3>>0<m63;66846>;3>>0:<>524759557<5=<<6kh4=544>cc<5=<<6kj4=544>ce<5=<<6kl4=544>cg<5=<<6k74=544>c><5=<<6k94=544>c0<5=<<6k:4=544>c5<5=<<6k<4=544>c7<5=<<6k>4=544>``<5=<<6hk4=544>`b<5=<<6hm4=544>`d<5=<<6<>n;<653?77127?::4>099>031=99=01988:025?821?3;;963;668241=:<?=1==>4=544>c3<uz<hm7>52z?5gd<49o16:n75e59~w25?2909w09<8;12b>;0;>0n86s|6`d94?4|5?km6>?i;<4ba?c33ty8=:4?:3y>2ag=;8l01;jm:340?xu4910;6?u26d0974`<5?nh6?8>;|q05<<72;q6:h=530d893bd2;<87p}<1`83>7}:>l>1?<h4=7f`>7073twe=>kl:182M>?02B8=n5U1g096~53:39;>7sG30f8yk74mm0;6<uG89:8L67d3S;m>7<t3509754=uA9:h6sa12gf>5<6sA2346F<1b9Y5c4=:r9?>7=?2;K74b<ug;8ik4?:0yK<=><@:;h7W?i2;0x714=;981qE=>d:m56`7290:wE678:J05f=]9o81>v=;2;136?{O;8n0qc?<f083>4}O0120D>?l;[3e6?4|;=81?=<5}I12`>{i9:l96=4>{I:;<>N49j1Q=k<52z176?57:3wC?<j4}o30b6<728qC4564H23`?_7a:38p?9<53109yM56l2we=>h;:182M>?02B8=n5U1g096~53:39;>7sG30f8yk74n<0;6<uG89:8L67d3S;m>7<t3509754=uA9:h6sa12d5>5<6sA2346F<1b9Y5c4=:r9?>7=?2;K74b<ug;8j:4?:0yK<=><@:;h7W?i2;0x714=;981qE=>d:m56`?290:wE678:J05f=]9o81>v=;2;136?{O;8n0qc?<f883>4}O0120D>?l;[3e6?4|;=81?=<5}I12`>{i9:lj6=4>{I:;<>N49j1Q=k<52z176?57:3wC?<j4}o30bg<728qC4564H23`?_7a:38p?9<53109yM56l2we=>hl:182M>?02B8=n5U1g096~53:39;>7sG30f8yk74nm0;6<uG89:8L67d3S;m>7<t3509754=uA9:h6sa12df>5<6sA2346F<1b9Y5c4=:r9?>7=?2;K74b<ug;8jk4?:0yK<=><@:;h7W?i2;0x714=;981qE=>d:m5167290:wE678:J05f=]9o81>v=;2;136?{O;8n0qc?;0083>4}O0120D>?l;[3e6?4|;=81?=<5}I12`>{i9=:96=4>{I:;<>N49j1Q=k<52z176?57:3wC?<j4}o3746<728qC4564H23`?_7a:38p?9<53109yM56l2we=9>;:182M>?02B8=n5U1g096~53:39;>7sG30f8yk738<0;6<uG89:8L67d3S;m>7<t3509754=uA9:h6sa1525>5<6sA2346F<1b9Y5c4=:r9?>7=?2;K74b<ug;?<:4?:0yK<=><@:;h7W?i2;0x714=;981qE=>d:m516?290:wE678:J05f=]9o81>v=;2;136?{O;8n0qc?;0883>4}O0120D>?l;[3e6?4|;=81?=<5}I12`>{i9=:j6=4>{I:;<>N49j1Q=k<52z176?57:3wC?<j4}o374g<728qC4564H23`?_7a:38p?9<53109yM56l2we=9>l:182M>?02B8=n5U1g096~53:39;>7sG30f8yk738m0;6<uG89:8L67d3S;m>7<t3509754=uA9:h6sa152f>5<6sA2346F<1b9Y5c4=:r9?>7=?2;K74b<ug;?<k4?:0yK<=><@:;h7W?i2;0x714=;981qE=>d:m5177290:wE678:m5176290:wE678:m5175290:wE678:m5174290:wE678:m5173290:wE678:m5172290:wE678:m5171290:wE678:m5170290:wE678:m517?290:wE678:m517>290:wE678:m517f290:wE678:m517e290:wE678:m517d290:wE678:m517c290:wE678:m517b290:wE678:m517a290<wE678:m5147290:wE678:m5146290:wE678:m5145290:wE678:m5144290:wE678:m5143290:wE678:m5142290:wE678:m5141290:wE678:m5140290:wE678:m514?290:wE678:m514>290:wE678:m514f290<wE678:m514e290:wE678:m514d290:wE678:m514c290:wE678:m514b290:wE678:m514a290:wE678:m5157290:wE678:m51562908wE678:m5155290owE678:m5154290=wE678:X034<6s8n?6pT>f3826162twe=9=;:182M>?02we=9=::182M>?02we=9=9:182M>?02we=9=8:182M>?02we=9=7:182M>?02we=9=6:182M>?02we=9=n:182M>?02we=9=m:182M>?02we=9=l:180M>?02we=9=k:182M>?02we=9=j:182M>?02we=9=i:182M>?02we=9:?:182M>?02we=9:>:182M>?02we=9:=:182M>?02we=9:<:182M>?02we=9:;:182M>?02we=9:::182M>?02we=9:9:182M>?02we=9:8:182M>?02we=9:7:182M>?02we=9:6:182M>?02we=9:n:182M>?02we=9:m:182M>?02we=9:l:182M>?02we=9:k:182M>?02we=9:j:182M>?02we=9:i:182M>?02we=9;?:182M>?02we=9;>:182M>?02we=9;=:182M>?02we=9;<:182M>?02we=9;;:182M>?02we=9;::182M>?02we=9;9:182M>?02we=9;8:182M>?02we=9;7:182M>?02we=9;6:182M>?02we=9;n:182M>?02we=9;m:182M>?02we=9;l:182M>?02we=9;k:182M>?02we=9;j:182M>?02we=9;i:182M>?02we=98?:182M>?02we=98>:182M>?02we=98=:182M>?02we=98<:182M>?02we=98;:182M>?02we=98::182M>?02we=989:182M>?02we=988:182M>?02we=987:182M>?02we=986:182M>?02we=98n:182M>?02we=98m:182M>?02we=98l:180M>?02we=98k:182M>?02we=98j:187M>?02we=98i:182M>?02we=99?:182M>?02we=99>:182M>?02we=99=:182M>?02we=99<:182M>?02we=99;:182M>?02we=99::182M>?02we=999:182M>?02we=998:182M>?02we=997:182M>?02we=996:182M>?02we=99n:182M>?02we=99m:182M>?02we=99l:186M>?02we=99k:186M>?02we=99j:186M>?02we=99i:186M>?02we=96?:186M>?02we=96>:186M>?02we=96=:186M>?02we=96<:186M>?02we=96;:186M>?02we=96::186M>?02we=969:182M>?02we=968:182M>?02we=967:182M>?02we=966:182M>?02we=96n:182M>?02we=96m:182M>?02we=96l:182M>?02we=96k:182M>?02we=96j:182M>?02we=96i:182M>?02we=97?:182M>?02we=97>:182M>?02we=97=:182M>?02we=97<:182M>?02we=97;:182M>?02we=97::182M>?02we=979:182M>?02we=978:182M>?02we=977:182M>?02we=976:182M>?02we=97n:182M>?02we=97m:182M>?02we=97l:182M>?02we=97k:182M>?02we=97j:182M>?02we=97i:182M>?02we=9o?:182M>?02we=9o>:182M>?02we=9o=:182M>?02we=9o<:182M>?02we=9o;:182M>?02we=9o::182M>?02we=9o9:182M>?02we=9o8:182M>?02we=9o7:182M>?02we=9o6:182M>?02we=9on:182M>?02we=9om:182M>?02we=9ol:182M>?02we=9ok:182M>?02we=9oj:182M>?02we=9oi:182M>?02we=9l?:182M>?02we=9l>:182M>?02we=9l=:182M>?02we=9l<:182M>?02we=9l;:182M>?02we=9l::182M>?02we=9l9:182M>?02we=9l8:182M>?02we=9l7:182M>?02we=9l6:182M>?02we=9ln:182M>?02we=9lm:182M>?02we=9ll:182M>?02we=9lk:182M>?02we=9lj:182M>?02we=9li:182M>?02we=9m?:182M>?02we=9m>:182M>?02we=9m=:182M>?02we=9m<:182M>?02we=9m;:182M>?02we=9m::182M>?02we=9m9:182M>?02we=9m8:182M>?02we=9m7:182M>?02we=9m6:182M>?02we=9mn:182M>?02we=9mm:182M>?02we=9ml:182M>?02we=9mk:182M>?02we=9mj:182M>?02we=9mi:182M>?02we=9j?:182M>?02we=9j>:182M>?02we=9j=:180M>?02we=9j<:180M>?02we=9j;:180M>?02we=9j::180M>?02we=9j9:180M>?02we=9j8:180M>?02we=9j7:180M>?02we=9j6:180M>?02we=9jn:180M>?02we=9jm:180M>?02we=9jl:180M>?02we=9jk:180M>?02we=9jj:180M>?02we=9ji:180M>?02we=9k?:180M>?02we=9k>:180M>?02we=9k=:180M>?02we=9k<:180M>?02we=9k;:180M>?02we=9k::180M>?02we=9k9:180M>?02we=9k8:180M>?02we=9k7:180M>?02we=9k6:180M>?02we=9kn:180M>?02we=9km:180M>?02we=9kl:180M>?02we=9kk:180M>?02we=9kj:180M>?02we=9ki:180M>?02we=9h?:180M>?02we=9h>:180M>?02we=9h=:180M>?02we=9h<:180M>?02we=9h;:180M>?02we=9h::180M>?02we=9h9:180M>?02we=9h8:180M>?02we=9h7:180M>?02we=9h6:180M>?02we=9hn:180M>?02we=9hm:180M>?02we=9hl:180M>?02we=9hk:180M>?02we=9hj:180M>?02we=9hi:180M>?02we=8>?:180M>?02we=8>>:180M>?02we=8>=:180M>?02we=8><:180M>?02we=8>;:180M>?02we=8>::180M>?02we=8>9:180M>?02we=8>8:180M>?02we=8>7:180M>?02we=8>6:180M>?02we=8>n:180M>?02we=8>m:180M>?02we=8>l:180M>?02we=8>k:180M>?02we=8>j:180M>?02we=8>i:180M>?02we=8??:180M>?02we=8?>:180M>?02we=8?=:180M>?02we=8?<:180M>?02we=8?;:180M>?02we=8?::180M>?02we=8?9:180M>?02we=8?8:180M>?02we=8?7:180M>?02we=8?6:180M>?02we=8?n:182M>?02we=8?m:182M>?02we=8?l:182M>?02we=8?k:182M>?02we=8?j:182M>?02we=8?i:182M>?02we=8<?:182M>?02we=8<>:182M>?02we=8<=:182M>?02we=8<<:182M>?02we=8<;:182M>?02we=8<::182M>?02we=8<9:182M>?02we=8<8:182M>?02we=8<7:182M>?02we=8<6:182M>?02we=8<n:182M>?02we=8<m:182M>?02we=8<l:182M>?02we=8<k:182M>?02we=8<j:182M>?02we=8<i:182M>?02we=8=?:182M>?02we=8=>:182M>?02we=8==:182M>?02we=8=<:182M>?02we=8=;:182M>?02we=8=::182M>?02we=8=9:182M>?02we=8=8:182M>?02we=8=7:182M>?02we=8=6:182M>?02we=8=n:182M>?02we=8=m:182M>?02we=8=l:182M>?02we=8=k:182M>?02we=8=j:182M>?02we=8=i:182M>?02we=8:?:182M>?02we=8:>:182M>?02we=8:=:182M>?02we=8:<:182M>?02we=8:;:182M>?02we=8:::182M>?02we=8:9:182M>?02we=8:8:182M>?02we=8:7:182M>?02we=8:6:182M>?02we=8:n:182M>?02we=8:m:182M>?02we=8:l:182M>?02we=8:k:182M>?02we=8:j:182M>?02we=8:i:182M>?02we=8;?:182M>?02we=8;>:182M>?02we=8;=:182M>?02we=8;<:182M>?02we=8;;:182M>?02we=8;::182M>?02we=8;9:182M>?02we=8;8:182M>?02we=8;7:182M>?02we=8;6:182M>?02we=8;n:182M>?02we=8;m:182M>?02we=8;l:182M>?02we=8;k:182M>?02we=8;j:182M>?02we=8;i:182M>?02we=88?:182M>?02we=88>:182M>?02we=88=:182M>?02we=88<:182M>?02we=88;:182M>?02we=88::182M>?02we=889:182M>?02we=888:182M>?02we=887:182M>?02we=886:182M>?02we=88n:182M>?02we=88m:182M>?02we=88l:182M>?02we=88k:182M>?02we=88j:182M>?02we=88i:182M>?02we=89?:182M>?02we=89>:182M>?02we=89=:182M>?02we=89<:182M>?02we=89;:182M>?02we=89::182M>?02we=899:182M>?02we=898:182M>?02we=897:182M>?02we=896:182M>?02we=89n:182M>?02we=89m:182M>?02we=89l:182M>?02we=89k:182M>?02we=89j:182M>?02we=89i:182M>?02we=86?:182M>?02we=86>:182M>?02we=86=:182M>?02we=86<:182M>?02we=86;:182M>?02we=86::182M>?02we=869:182M>?02we=868:182M>?02we=867:182M>?02we=866:182M>?02we=86n:182M>?02we=86m:182M>?02we=86l:182M>?02we=86k:182M>?02we=86j:182M>?02we=86i:182M>?02we=87?:182M>?02we=87>:182M>?02we=87=:182M>?02we=87<:182M>?02we=87;:182M>?02we=87::182M>?02we=879:182M>?02we=878:182M>?02we=877:182M>?02we=876:182M>?02we=87n:182M>?02we=87m:182M>?02we=87l:182M>?02we=87k:182M>?02we=87j:182M>?02we=87i:182M>?02we=8o?:182M>?02we=8o>:182M>?02we=8o=:182M>?02we=8o<:182M>?02we=8o;:182M>?02we=8o::182M>?02we=8o9:182M>?02we=8o8:182M>?02we=8o7:182M>?02we=8o6:182M>?02we=8on:182M>?02we=8om:182M>?02we=8ol:182M>?02we=8ok:182M>?02we=8oj:182M>?02we=8oi:182M>?02we=8l?:182M>?02we=8l>:182M>?02we=8l=:182M>?02we=8l<:182M>?02we=8l;:182M>?02we=8l::182M>?02we=8l9:182M>?02we=8l8:182M>?02we=8l7:182M>?02we=8l6:182M>?02we=8ln:182M>?02we=8lm:182M>?02we=8ll:182M>?02we=8lk:182M>?02we=8lj:180M>?02we=8li:180M>?02we=8m?:180M>?02we=8m>:180M>?02we=8m=:182M>?02we=8m<:182M>?02we=8m;:182M>?02we=8m::182M>?02we=8m9:182M>?02we=8m8:182M>?02we=8m7:182M>?02we=8m6:182M>?02we=8mn:182M>?02we=8mm:182M>?02we=8ml:182M>?02we=8mk:182M>?02we=8mj:182M>?02we=8mi:182M>?02we=8j?:182M>?02we=8j>:182M>?02we=8j=:182M>?02we=8j<:182M>?02we=8j;:182M>?02we=8j::182M>?02we=8j9:182M>?02we=8j8:182M>?02we=8j7:182M>?02we=8j6:182M>?02we=8jn:182M>?02we=8jm:182M>?02we=8jl:182M>?02we=8jk:182M>?02we=8jj:182M>?02we=8ji:182M>?02we=8k?:182M>?02we=8k>:182M>?02we=8k=:182M>?02we=8k<:182M>?02we=8k;:182M>?02we=8k::182M>?02we=8k9:182M>?02we=8k8:182M>?02we=8k7:182M>?02we=8k6:182M>?02we=8kn:182M>?02we=8km:182M>?02we=8kl:182M>?02we=8kk:182M>?02we=8kj:182M>?02we=8ki:182M>?02we=8h?:182M>?02we=8h>:182M>?02we=8h=:182M>?02we=8h<:182M>?02we=8h;:182M>?02we=8h::182M>?02we=8h9:182M>?02we=8h8:182M>?02we=8h7:182M>?02we=8h6:182M>?02we=8hn:182M>?02we=8hm:182M>?02we=8hl:182M>?02we=8hk:182M>?02we=8hj:182M>?02we=8hi:182M>?02we=;>?:182M>?02we=;>>:182M>?02we=;>=:182M>?02we=;><:182M>?02we=;>;:182M>?02we=;>::182M>?02we=;>9:180M>?02we=;>8:180M>?02we=;>7:180M>?02we=;>6:182M>?02we=;>n:182M>?02we=;>m:182M>?02we=;>l:182M>?02we=;>k:182M>?02we=;>j:182M>?02we=;>i:182M>?02we=;??:182M>?02we=;?>:182M>?02we=;?=:182M>?02we=;?<:182M>?02we=;?;:182M>?02we=;?::182M>?02we=;?9:182M>?02we=;?8:182M>?02we=;?7:182M>?02we=;?6:180M>?02we=;?n:180M>?02we=;?m:180M>?02we=;?l:180M>?02we=;?k:180M>?02we=;?j:180M>?02we=;?i:180M>?02we=;<?:180M>?02we=;<>:180M>?02we=;<=:180M>?02we=;<<:180M>?02we=;<;:180M>?02we=;<::182M>?02we=;<9:182M>?02we=;<8:182M>?02we=;<7:182M>?02we=;<6:182M>?02we=;<n:182M>?02we=;<m:182M>?02we=;<l:182M>?02we=;<k:182M>?02we=;<j:182M>?02we=;<i:182M>?02we=;=?:182M>?02we=;=>:182M>?02we=;==:182M>?02we=;=<:182M>?02we=;=;:182M>?02we=;=::182M>?02we=;=9:182M>?02we=;=8:182M>?02we=;=7:182M>?02we=;=6:182M>?02we=;=n:182M>?02we=;=m:182M>?02we=;=l:182M>?02we=;=k:182M>?02we=;=j:182M>?02we=;=i:182M>?02we=;:?:182M>?02we=;:>:182M>?02we=;:=:182M>?02we=;:<:182M>?02we=;:;:182M>?02we=;:::182M>?02we=;:9:182M>?02we=;:8:182M>?02we=;:7:182M>?02we=;:6:182M>?02we=;:n:182M>?02we=;:m:182M>?02we=;:l:182M>?02we=;:k:182M>?02we=;:j:182M>?02we=;:i:182M>?02we=;;?:182M>?02we=;;>:182M>?02we=;;=:182M>?02we=;;<:182M>?02we=;;;:182M>?02we=;;::182M>?02we=;;9:182M>?02we=;;8:182M>?02we=;;7:182M>?02we=;;6:182M>?02we=;;n:182M>?02we=;;m:182M>?02we=;;l:182M>?02we=;;k:182M>?02we=;;j:182M>?02we=;;i:182M>?02we=;8?:182M>?02we=;8>:182M>?02we=;8=:182M>?02we=;8<:182M>?02we=;8;:182M>?02we=;8::182M>?02we=;89:182M>?02we=;88:182M>?02we=;87:182M>?02we=;86:182M>?02we=;8n:182M>?02we=;8m:182M>?02we=;8l:182M>?02we=;8k:182M>?02we=;8j:182M>?02we=;8i:182M>?02we=;9?:182M>?02we=;9>:182M>?02we=;9=:182M>?02we=;9<:182M>?02we=;9;:182M>?02we=;9::182M>?02we=;99:182M>?02we=;98:182M>?02we=;97:182M>?02we=;96:182M>?02we=;9n:182M>?02we=;9m:182M>?02we=;9l:182M>?02we=;9k:182M>?02we=;9j:182M>?02we=;9i:182M>?02we=;6?:182M>?02we=;6>:182M>?02we=;6=:182M>?02we=;6<:182M>?02we=;6;:182M>?02we=;6::182M>?02we=;69:182M>?02we=;68:182M>?02we=;67:182M>?02we=;66:182M>?02we=;6n:182M>?02we=;6m:182M>?02we=;6l:182M>?02we=;6k:182M>?02we=;6j:182M>?02we=;6i:182M>?02we=;7?:182M>?02we=;7>:182M>?02we=;7=:182M>?02we=;7<:182M>?02we=;7;:182M>?02we=;7::182M>?02we=;79:182M>?02we=;78:182M>?02we=;77:182M>?02we=;76:182M>?02we=;7n:182M>?02we=;7m:182M>?02we=;7l:182M>?02we=;7k:182M>?02we=;7j:182M>?02we=;7i:182M>?02we=;o?:182M>?02we=;o>:182M>?02we=;o=:182M>?02we=;o<:182M>?02we=;o;:182M>?02we=;o::182M>?02we=;o9:182M>?02we=;o8:182M>?02we=;o7:182M>?02we=;o6:182M>?02we=;on:182M>?02we=;om:182M>?02we=;ol:182M>?02we=;ok:182M>?02we=;oj:182M>?02we=;oi:182M>?02we=;l?:182M>?02we=;l>:182M>?02we=;l=:182M>?02we=;l<:182M>?02we=;l;:182M>?02we=;l::182M>?02we=;l9:182M>?02we=;l8:182M>?02we=;l7:182M>?02we=;l6:182M>?02we=;ln:182M>?02we=;lm:182M>?02we=;ll:182M>?02we=;lk:182M>?02we=;lj:182M>?02we=;li:182M>?02we=;m?:182M>?02we=;m>:182M>?02we=;m=:182M>?02we=;m<:182M>?02we=;m;:182M>?02we=;m::182M>?02we=;m9:182M>?02we=;m8:182M>?02we=;m7:180=~N?011vb<8l9;295~N?011vb<8la;295~N?011vb<8lb;295~N?011vb<8lc;295~N?011vb<8ld;295~N?011vb<8le;295~N?011vb<8lf;295~N?011vb8m<:181M>?02we9n:50;1xL=>?3td>o84?:2yK<=><ug?h:7>53zJ;<==zf<i<6=4<{I:;<>{i=j21<7=tH9:;?xh2k00;6>uG89:8yk3di3:1?vF7899~j0ee2908wE678:m77d=83;pD567;|l06f<728qC4564}o11`?6=9rB3455rn20f>5<6sA2346sa33d94?7|@1237p`<3183>4}O0120qc=<1;295~N?011vb>=;:182M>?02we?>;50;3xL=>?3td8?;4?:0yK<=><ug98;7>51zJ;<==zf:936=4>{I:;<>{i;k:1<7?tH9:;?xh4j80;6<uG89:8yk5e:3:1=vF7899~j6d4290:wE678:m7g2=83;pD567;|l0f0<728qC4564}o1a2?6=9rB3455rn2`4>5<6sA2346sa3c;94?7|@1237p`<bc83>4}O0120qc=mc;295~N?011vb9=;:182M>?02we8>;50;3xL=>?3td??;4?:0yK<=><ug>8;7>51zJ;<==zf=936=4>{I:;<>{i<:31<7?tH9:;?xh3;h0;6<uG89:8yk24j3:1=vF7899~j15c290:wE678:m06`=83;pD567;|l705<728qC4564}o6a<?6=9rB3455rn5`:>5<6sA2346sa4cc94?7|@1237p`;bc83>4}O0120qc:mc;295~N?011vb9lk:182M>?02we8ok50;3xL=>?3td?nk4?:0yK<=><ug>h=7>51zJ;<==zf=i86=4>{I:;<>{i<j>1<7?tH9:;?xh2<k0;6<uG89:8yk33k3:1=vF7899~j02c290:wE678:m11c=83;pD567;|l60c<728qC4564}o764?6=9rB3455rn472>5<6sA2346sa54094?7|@1237p`:5583>4}O0120qc;:5;295~N?011vb8;9:182M>?02we98950;3xL=>?3td>954?:0yK<=><ug?>57>51zJ;<==zfj836=4m{I:;<>{ik921<7?tH9:;?xhd800;6<uG89:8yke7i3:1=vF7899~jf6e290:wE678:mg5e=83;pD567;|l`4a<728qC4564}oa3a?6=9rB3455rnb33>5<6sA2346sac0394?7|@1237p`l1383>4}O0120qcm>3;295~N?011vbn?::182M>?02weo<850;3xL=>?3tdhhl4?:cyK<=><ugiim7>51zJ;<==zfjhi6=4>{I:;<>{ikki1<7?tH9:;?xhdjm0;6<uG89:8ykeem3:1=vF7899~jfda290:wE678:mgf6=83;pD567;|l`g7<728qC4564}oa`7?6=9rB3455rnba7>5<6sA2346sacb794?7|@1237p`lc683>4}O0120qcml8;295~N?011vbi6l:18aM>?02weh;m50;3xL=>?3tdo:i4?:0yK<=><ugn=i7>51zJ;<==zfm<m6=4>{I:;<>{il>:1<7?tH9:;?xhc?80;6<uG89:8ykb0:3:1=vF7899~ja13290:wE678:m`23=83;pD567;|lg33<728qC4564}of43?6=9rB3455rne5:>5<6sA2346sad6c94?7|@1237psr}AB@4g5:39i;nj733CDG}7uIJ[wpNO
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/ila36.vhd b/FEE_ADC32board/project/ipcore_dir/ila36.vhd
deleted file mode 100644
index 77f07b8..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila36.vhd
+++ /dev/null
@@ -1,31 +0,0 @@
--------------------------------------------------------------------------------
--- Copyright (c) 2012 Xilinx, Inc.
--- All Rights Reserved
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor     : Xilinx
--- \   \   \/     Version    : 13.3
---  \   \         Application: XILINX CORE Generator
---  /   /         Filename   : ila36.vhd
--- /___/   /\     Timestamp  : Thu Jul 19 13:23:10 W. Europe Daylight Time 2012
--- \   \  /  \
---  \___\/\___\
---
--- Design Name: VHDL Synthesis Wrapper
--------------------------------------------------------------------------------
--- This wrapper is used to integrate with Project Navigator and PlanAhead
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-ENTITY ila36 IS
-  port (
-    CONTROL: inout std_logic_vector(35 downto 0);
-    CLK: in std_logic;
-    TRIG0: in std_logic_vector(35 downto 0));
-END ila36;
-
-ARCHITECTURE ila36_a OF ila36 IS
-BEGIN
-
-END ila36_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/ila36.vho b/FEE_ADC32board/project/ipcore_dir/ila36.vho
deleted file mode 100644
index 6d02486..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila36.vho
+++ /dev/null
@@ -1,40 +0,0 @@
--------------------------------------------------------------------------------
--- Copyright (c) 2012 Xilinx, Inc.
--- All Rights Reserved
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor     : Xilinx
--- \   \   \/     Version    : 13.3
---  \   \         Application: Xilinx CORE Generator
---  /   /         Filename   : ila36.vho
--- /___/   /\     Timestamp  : Thu Jul 19 13:23:10 W. Europe Daylight Time 2012
--- \   \  /  \
---  \___\/\___\
---
--- Design Name: ISE Instantiation template
--- Component Identifier: xilinx.com:ip:chipscope_ila:1.05.a
--------------------------------------------------------------------------------
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component ila36
-  PORT (
-    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    CLK : IN STD_LOGIC;
-    TRIG0 : IN STD_LOGIC_VECTOR(35 DOWNTO 0));
-
-end component;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-
-your_instance_name : ila36
-  port map (
-    CONTROL => CONTROL,
-    CLK => CLK,
-    TRIG0 => TRIG0);
-
--- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/FEE_ADC32board/project/ipcore_dir/ila36.xco b/FEE_ADC32board/project/ipcore_dir/ila36.xco
deleted file mode 100644
index dd04614..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila36.xco
+++ /dev/null
@@ -1,138 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.3
-# Date: Thu Jul 19 11:21:13 2012
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:chipscope_ila:1.05.a
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Structural
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT ILA_(ChipScope_Pro_-_Integrated_Logic_Analyzer) family Xilinx,_Inc. 1.05.a
-# END Select
-# BEGIN Parameters
-CSET check_bramcount=false
-CSET component_name=ila36
-CSET constraint_type=embedded
-CSET counter_width_1=Disabled
-CSET counter_width_10=Disabled
-CSET counter_width_11=Disabled
-CSET counter_width_12=Disabled
-CSET counter_width_13=Disabled
-CSET counter_width_14=Disabled
-CSET counter_width_15=Disabled
-CSET counter_width_16=Disabled
-CSET counter_width_2=Disabled
-CSET counter_width_3=Disabled
-CSET counter_width_4=Disabled
-CSET counter_width_5=Disabled
-CSET counter_width_6=Disabled
-CSET counter_width_7=Disabled
-CSET counter_width_8=Disabled
-CSET counter_width_9=Disabled
-CSET data_port_width=0
-CSET data_same_as_trigger=true
-CSET disable_save_keep=false
-CSET enable_storage_qualification=true
-CSET enable_trigger_output_port=false
-CSET example_design=false
-CSET exclude_from_data_storage_1=false
-CSET exclude_from_data_storage_10=false
-CSET exclude_from_data_storage_11=false
-CSET exclude_from_data_storage_12=false
-CSET exclude_from_data_storage_13=false
-CSET exclude_from_data_storage_14=false
-CSET exclude_from_data_storage_15=false
-CSET exclude_from_data_storage_16=false
-CSET exclude_from_data_storage_2=false
-CSET exclude_from_data_storage_3=false
-CSET exclude_from_data_storage_4=false
-CSET exclude_from_data_storage_5=false
-CSET exclude_from_data_storage_6=false
-CSET exclude_from_data_storage_7=false
-CSET exclude_from_data_storage_8=false
-CSET exclude_from_data_storage_9=false
-CSET match_type_1=basic_with_edges
-CSET match_type_10=basic_with_edges
-CSET match_type_11=basic_with_edges
-CSET match_type_12=basic_with_edges
-CSET match_type_13=basic_with_edges
-CSET match_type_14=basic_with_edges
-CSET match_type_15=basic_with_edges
-CSET match_type_16=basic_with_edges
-CSET match_type_2=basic_with_edges
-CSET match_type_3=basic_with_edges
-CSET match_type_4=basic_with_edges
-CSET match_type_5=basic_with_edges
-CSET match_type_6=basic_with_edges
-CSET match_type_7=basic_with_edges
-CSET match_type_8=basic_with_edges
-CSET match_type_9=basic_with_edges
-CSET match_units_1=1
-CSET match_units_10=1
-CSET match_units_11=1
-CSET match_units_12=1
-CSET match_units_13=1
-CSET match_units_14=1
-CSET match_units_15=1
-CSET match_units_16=1
-CSET match_units_2=1
-CSET match_units_3=1
-CSET match_units_4=1
-CSET match_units_5=1
-CSET match_units_6=1
-CSET match_units_7=1
-CSET match_units_8=1
-CSET match_units_9=1
-CSET max_sequence_levels=1
-CSET number_of_trigger_ports=1
-CSET sample_data_depth=1024
-CSET sample_on=Rising
-CSET trigger_port_width_1=36
-CSET trigger_port_width_10=8
-CSET trigger_port_width_11=8
-CSET trigger_port_width_12=8
-CSET trigger_port_width_13=8
-CSET trigger_port_width_14=8
-CSET trigger_port_width_15=8
-CSET trigger_port_width_16=8
-CSET trigger_port_width_2=8
-CSET trigger_port_width_3=8
-CSET trigger_port_width_4=8
-CSET trigger_port_width_5=8
-CSET trigger_port_width_6=8
-CSET trigger_port_width_7=8
-CSET trigger_port_width_8=8
-CSET trigger_port_width_9=8
-CSET use_rpms=true
-# END Parameters
-GENERATE
-# CRC: d7d162a4
diff --git a/FEE_ADC32board/project/ipcore_dir/ila36.xise b/FEE_ADC32board/project/ipcore_dir/ila36.xise
deleted file mode 100644
index 7a85eae..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila36.xise
+++ /dev/null
@@ -1,72 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="ila36.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="ila36.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ila36|ila36_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="ila36.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ila36" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="ila36" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-19T13:23:19" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BE66BF3D7764410AB7EAAD8952DDFFD8" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/ila36_readme.txt b/FEE_ADC32board/project/ipcore_dir/ila36_readme.txt
deleted file mode 100644
index f39a786..0000000
--- a/FEE_ADC32board/project/ipcore_dir/ila36_readme.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-The following files were generated for 'ila36' in directory
-D:\Xilinx_proj\Panda\test_seradc\ipcore_dir\
-
-XCO file generator:
-   Generate an XCO file for compatibility with legacy flows.
-
-   * ila36.xco
-
-Creates an implementation netlist:
-   Creates an implementation netlist for the IP.
-
-   * ila36.cdc
-   * ila36.ngc
-   * ila36.vhd
-   * ila36.vho
-
-Creates an HDL instantiation template:
-   Creates an HDL instantiation template for the IP.
-
-   * ila36.vho
-
-IP Symbol Generator:
-   Generate an IP symbol based on the current project options'.
-
-   * ila36.asy
-
-SYM file generator:
-   Generate a SYM file for compatibility with legacy flows
-
-   * ila36.sym
-
-Generate ISE metadata:
-   Create a metadata file for use when including this core in ISE designs
-
-   * ila36_xmdf.tcl
-
-Generate ISE subproject:
-   Create an ISE subproject for use when including this core in ISE designs
-
-   * _xmsgs/pn_parser.xmsgs
-   * ila36.gise
-   * ila36.xise
-
-Deliver Readme:
-   Readme file for the IP.
-
-   * ila36_readme.txt
-
-Generate FLIST file:
-   Text file listing all of the output files produced when a customized core was
-   generated in the CORE Generator.
-
-   * ila36_flist.txt
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/FEE_ADC32board/project/ipcore_dir/mgt_usrclk_source_mmcm.vhd b/FEE_ADC32board/project/ipcore_dir/mgt_usrclk_source_mmcm.vhd
deleted file mode 100644
index 112e87f..0000000
--- a/FEE_ADC32board/project/ipcore_dir/mgt_usrclk_source_mmcm.vhd
+++ /dev/null
@@ -1,218 +0,0 @@
-------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   / 
--- /___/  \  /    Vendor: Xilinx 
--- \   \   \/     Version : 1.12
---  \   \         Application : Virtex-6 FPGA GTX Transceiver Wizard 
---  /   /         Filename : mgt_usrclk_source_mmcm.vhd
--- /___/   /\      
--- \   \  /  \ 
---  \___\/\___\ 
---
---
--- Module MGT_USRCLK_SOURCE_MMCM (for use with Virtex-6 GTX Transceivers)
--- Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
--- 
--- 
--- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES. 
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-library UNISIM;
-use UNISIM.VCOMPONENTS.ALL;
-
---***********************************Entity Declaration*******************************
-entity MGT_USRCLK_SOURCE_MMCM is
-generic
-(
-    MULT                : real              := 2.0;
-    DIVIDE              : integer           := 2;    
-    CLK_PERIOD          : real              := 6.4;    
-    OUT0_DIVIDE         : real              := 2.0;
-    OUT1_DIVIDE         : integer           := 2;
-    OUT2_DIVIDE         : integer           := 2;
-    OUT3_DIVIDE         : integer           := 2
-);
-port
-(
-    CLKFBOUT           : out std_logic; 
-    CLK0_OUT           : out std_logic;
-    CLK1_OUT           : out std_logic;
-    CLK2_OUT           : out std_logic;
-    CLK3_OUT           : out std_logic;
-    CLK_IN             : in  std_logic;
-    MMCM_LOCKED_OUT    : out std_logic;
-    MMCM_RESET_IN      : in  std_logic
-);
-
-
-end MGT_USRCLK_SOURCE_MMCM;
-
-architecture RTL of MGT_USRCLK_SOURCE_MMCM is
---*********************************Wire Declarations**********************************
-
-    signal   tied_to_ground_vec_i :   std_logic_vector(15 downto 0);
-    signal   tied_to_ground_i     :   std_logic;
-    signal   tied_to_vcc_i        :   std_logic;
-    signal   clkout0_i            :   std_logic;
-    signal   clkout1_i            :   std_logic;
-    signal   clkout2_i            :   std_logic;
-    signal   clkout3_i            :   std_logic;
-    signal   clkfbout_i           :   std_logic;
-    signal   clkfbout_buf         :   std_logic;
-
-begin
-
---*********************************** Beginning of Code *******************************
-
-    --  Static signal Assigments    
-    tied_to_ground_i         <= '0';
-    tied_to_ground_vec_i     <= (others=>'0');
-    tied_to_vcc_i            <= '1';
-
-    -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
-    -- for improved jitter performance, and to avoid consuming an additional BUFG
-    mmcm_adv_i  : MMCM_ADV
-    generic map
-    (
-         COMPENSATION     =>  "ZHOLD",
-         CLKFBOUT_MULT_F  =>  MULT,
-         DIVCLK_DIVIDE    =>  DIVIDE,
-         CLKFBOUT_PHASE   =>  0.0,
-         CLKIN1_PERIOD    =>  CLK_PERIOD,
-         CLKIN2_PERIOD    =>  10.0,          -- Not used
-         CLKOUT0_DIVIDE_F =>  OUT0_DIVIDE,
-         CLKOUT0_PHASE    =>  0.0,
-         CLKOUT1_DIVIDE   =>  OUT1_DIVIDE,
-         CLKOUT1_PHASE    =>  0.0,
-         CLKOUT2_DIVIDE   =>  OUT2_DIVIDE,
-         CLKOUT2_PHASE    =>  0.0,
-         CLKOUT3_DIVIDE   =>  OUT3_DIVIDE,
-         CLKOUT3_PHASE    =>  0.0,
-         CLOCK_HOLD       =>  TRUE         
-    )
-    port map
-    (
-         CLKIN1          =>  CLK_IN,
-         CLKIN2          =>  tied_to_ground_i,
-         CLKINSEL        =>  tied_to_vcc_i,
-         CLKFBIN         =>  clkfbout_buf,
-         CLKOUT0         =>  clkout0_i,
-         CLKOUT0B        =>  open,
-         CLKOUT1         =>  clkout1_i,
-         CLKOUT1B        =>  open,
-         CLKOUT2         =>  clkout2_i,
-         CLKOUT2B        =>  open,
-         CLKOUT3         =>  clkout3_i,
-         CLKOUT3B        =>  open,
-         CLKOUT4         =>  open,
-         CLKOUT5         =>  open,
-         CLKOUT6         =>  open,
-         CLKFBOUT        =>  clkfbout_i,
-         CLKFBOUTB       =>  open,
-         CLKFBSTOPPED    =>  open,
-         CLKINSTOPPED    =>  open,
-         DO              =>  open,
-         DRDY            =>  open,
-         DADDR           =>  tied_to_ground_vec_i(6 downto 0),
-         DCLK            =>  tied_to_ground_i,
-         DEN             =>  tied_to_ground_i,
-         DI              =>  tied_to_ground_vec_i(15 downto 0),
-         DWE             =>  tied_to_ground_i,
-         LOCKED          =>  MMCM_LOCKED_OUT,
-         PSCLK           =>  tied_to_ground_i,
-         PSEN            =>  tied_to_ground_i,        
-         PSINCDEC        =>  tied_to_ground_i, 
-         PSDONE          =>  open,         
-         PWRDWN          =>  tied_to_ground_i,
-         RST             =>  MMCM_RESET_IN     
-    );
-    
-    clkfb_bufg_i  :  BUFG   
-    port map
-    (
-        O      =>    clkfbout_buf, 
-        I      =>    clkfbout_i
-    ); 
-    CLKFBOUT   <=    clkfbout_buf;
-    
-    clkout0_bufg_i  :  BUFG   
-    port map
-    (
-        O      =>    CLK0_OUT, 
-        I      =>    clkout0_i
-    ); 
-
-
-    clkout1_bufg_i  :  BUFG   
-    port map
-    (
-        O      =>    CLK1_OUT,
-        I      =>    clkout1_i
-    );
-    
-    
-    clkout2_bufg_i  :  BUFG   
-    port map
-    (
-        O      =>    CLK2_OUT, 
-        I      =>    clkout2_i
-    ); 
-
-
-    clkout3_bufg_i  :  BUFG   
-    port map
-    (
-        O      =>    CLK3_OUT,
-        I      =>    clkout3_i
-    );    
-    
-end RTL;
- 
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.asy b/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.asy
deleted file mode 100644
index 115c067..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.asy
+++ /dev/null
@@ -1,37 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 sync_fifo_512x41
-RECTANGLE Normal 32 32 800 4064
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName din[40:0]
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 464 32 464
-PIN 0 464 LEFT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Wide 832 272 800 272
-PIN 832 272 RIGHT 36
-PINATTR PinName dout[40:0]
-PINATTR Polarity OUT
-LINE Normal 832 304 800 304
-PIN 832 304 RIGHT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 832 496 800 496
-PIN 832 496 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.gise b/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.gise
deleted file mode 100644
index 9d5ec34..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.gise
+++ /dev/null
@@ -1,53 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="sync_fifo_512x41.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="sync_fifo_512x41.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="sync_fifo_512x41.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="sync_fifo_512x41.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1411385153" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1411385153">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="517927155140597448" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1475527042133781192" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2025323555865192840" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.ngc b/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.ngc
deleted file mode 100644
index 0208d30..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$5g;44<,[o}e~g`n;"2*73>(-80!<m4/+])[WGIOL*!=6>6;123456789>;7=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<<>4011B755F899;?==?4:2:=57<9830=>4@UURVP?TCIMNYINM31383:4d<9<0BB][[:@FGVDTCIMNYY1?;:1<2f>722@D[YY4NDEPASWGCL[_7=94?>0c853<NFY__6LJKR@PGEABU48?1<3?m;049MKVR\3KOH_O]D@FGVI:6=3:5=l5>6;KMTPR=IMNYNZ\NDEP?50<768h0=;4FNQWW>DBCZK]YMIJ]L=36>586;2;1EC^ZT;PFCFCF490;2<=41;KMTPR=ZLMHIO2?:1<25>7=AGZ^X7\\T@>3>58692;1EC^ZT;PPPG:7294:7??;;209MKVR\3NBMIG33083:42<;;0BB][[:EKA@L:493:5=85<2;MVPUSS2MEJHB2<1;2=50=4:3E^X][[:EMA@J:493:5=>5;1;KMTPR=L@DJ09>50?30?17=AGZ^X7JFNC>74?699;1?=7GAPTV9`lh;<90;2<;4408LQQVR\3NDYYO34183:43<<80DYY^ZT;FLQQD;<90;2<:4408LQQVR\3ndyy2;0;2=51=32@D[YY4KIQCGMU:4294:86:5IORVP?BNXKNB\1=50?33?1<NFY__6ZKN<283:47<<3CE\XZ5WDCO86<768;087GAPTV9S@GR4:0;2<;44;MVPUSS2ME[MIA_<283:43<<3E^X][[:EMSFAIW4:0;2<>45;KMTPR=_LK787>11196>LHW]]0\IO2;:1<2?34<>H>0:LON8:4BEDGFIH;;7;ONA@CBEDGFIHKJMk59vmz275ran=2?!>??;6DEBC@ANOLMJKHIF008<?OIX\^1[HLXE=594;74310BB][[:VGAS@J;?3:5=>57:HLSQQ<PMK]NY1950?34?=<H]]Z^X7KLCQCQMQ_;?3:5=67;;823=44<13CE\XZ5AEFQE9>=87;9744FNQWW>DBCZK636=0>7:;9KPRW]]0YHLJKRDA@8=<76;12M956A@C1?D033HK=M55NA@C5EDG682KJMLONA@4BEDGFIH20MIJ]A=2=<>GCL[K7=364AEFQE94902KOH_O33?:8EABUI5>546OKDSC?1;><IMNYM1818:CG@WG;?7k0MIJ]A=:94;><IMNYM161e:CG@WGULHNO^1>1f:CG@WGULHNO^1??>g9B@ATFZMKOH_2>1?d8EABUI[NJHI\313<e?DBCZHXOMIJ]<01=b>GCL[KYHLJKR=37:47<IMNYM_JNDEP?50<76o1JHI\NRECG@W:6=7o0MIJ]ASFB@AT;97o0MIJ]ASFB@AT;:7o0MIJ]ASFB@AT;;7o0MIJ]ASFB@AT;<7o0MIJ]ASFB@AT;=7o0MIJ]ASFB@AT;>7o0MIJ]ASFB@AT;?7o0MIJ]ASFB@AT;07o0MIJ]ASFB@AT;17l0MIJ]ASFB@ATK494:<6OKDSCQ@DBCZE6:<3??;@FGVDTCIMNY@1?>>028EABUI[NJHI\C<00=55=FLMXJ^IOKDSN?568682KOH_O]D@FGVI:6<7;97LJKR@PGEABUD5;>6=0>0:CG@WGULHNO^A2>5?d8EABUI[NJHI\C<0<e?DBCZHXOMIJ]L=0=b>GCL[KYHLJKRM>0:c=FLMXJ^IOKDSN?0;`<IMNYM_JNDEPO808a3HNO^L\KAEFQH909n2KOH_O]D@FGVI:06o1JHI\NRECG@WJ;07l0MIJ]ASFB@ATK404m7LJKR@PGEABU]5:5==5NDEPBVAGCL[_7==0>0:CG@WGULHNO^X2>1?33?DBCZHXOMIJ]U=31:46<IMNYM_JNDEPV84599;1JHI\NRECG@WS;9=0;2<>4AEFQEWBFLMX^0<:1f:CG@WGULHNO^X2>>g9B@ATFZMKOH_[32?d8EABUI[NJHI\Z<2<e?DBCZHXOMIJ]U=6=b>GCL[KYHLJKRT>6:c=FLMXJ^IOKDSW?2;`<IMNYM_JNDEPV828a3HNO^L\KAEFQQ9>9n2KOH_O]D@FGVP:>611JHI\M<1<;?DBCZK6:255NDEPA878?3HNO^O2<>99B@ATE4=437LJKRC>6:==FLMXI0;07;@FGVG:06h1JHI\M<983:==FLMXI050j;@FGVGQUIMNY0=0i;@FGVGQUIMNY0<>1f:CG@WDPZHNO^1?>>g9B@ATE_[KOH_2>2?d8EABUJ^XJHI\312<e?DBCZK]YMIJ]<06=54=FLMXI[_OKDS>21?69n2KOH_LXR@FGV9726l1JHI\MWSCG@W:66l1JHI\MWSCG@W:56l1JHI\MWSCG@W:46l1JHI\MWSCG@W:36l1JHI\MWSCG@W:26l1JHI\MWSCG@W:16l1JHI\MWSCG@W:06l1JHI\MWSCG@W:?6l1JHI\MWSCG@W:>6o1JHI\MWSCG@WJ;87;;7LJKRCUQEABUD5;;2<>4AEFQFRTFLMXG0<?1119B@ATE_[KOH_B313<24>GCL[H\^LJKRM>27;773HNO^OY]AEFQH9736880MIJ]BVPB@ATK48?1<3??;@FGVGQUIMNY@1?:>g9B@ATE_[KOH_B31?d8EABUJ^XJHI\C<3<e?DBCZK]YMIJ]L=1=b>GCL[H\^LJKRM>7:c=FLMXI[_OKDSN?1;`<IMNYNZ\NDEPO838a3HNO^OY]AEFQH919n2KOH_LXR@FGVI:?6o1JHI\MWSCG@WJ;17l0MIJ]BVPB@ATR494:<6OKDS@TVDBCZ\6:<3??;@FGVGQUIMNYY1?>>028EABUJ^XJHI\Z<00=55=FLMXI[_OKDSW?5686:2KOH_LXR@FGVP:6<3:5==5NDEPASWGCL[_7=90i;@FGVGQUIMNYY1?1f:CG@WDPZHNO^X2=>g9B@ATE_[KOH_[33?d8EABUJ^XJHI\Z<5<e?DBCZK]YMIJ]U=7=b>GCL[H\^LJKRT>5:c=FLMXI[_OKDSW?3;`<IMNYNZ\NDEPV8=8a3HNO^OY]AEFQQ9?9;2KG@45NSXL@[WC@9?1IA@QFNGM\EABUMZYT^L@HE99AQVYNFOE:7No4C@Q@EACNFHk0OL]LAEGJJGd<KHYHMIK@UUCa?FGTKHNNCXZM2:AF57=D@LI@SAGLEOQF[Q_WM;1HE95LLJ25?FJL91:=7NBD2626?FJL:Q20OAE=X0:31>EKC0:?7NBDA49@HNG6?2IGGL?K269@HNG6L==0OAEN1E::?FJLI[NH@Fo4CMIBVAEKCEk0OAENREAOOP2<KEAI96MCKC3:?FJLJ^XH@Fo4CMIASWEKCEk0OAEMWSAOOP3<KEAH=85LLJF21>EKCM\h7NBDDW]GMSOCM<1H@FHW8:AOOC^60990OA\6;BMNILRSMM;?7NA]E^EFJ@TF\@EESD@IO69@V@GSMM;0H:5KBHVFVWb<LLFJUHJPWSKWA7=CA11OELJF<1<:?AOFL@6:<374DHCGM976601OELJF<00==>BNIMC7=>06;EKB@L:6<730HDOKI=36:<=CAHNB0<819:FJEAO;9>427IGNDH>2<;?<L@KOE1?6>99GMDBN48427IGNDH>14;?<L@KOE1<>>89GMDBN4;8556JFAEK?668>3MCJHD2=4?;8@LGCA58>245KI@FJ870912NBMIG326<:?AOFL@694374DHCGM94>611OELJF<3<:?AOFL@68<3l4DHCGM95629427IGNDH>05;><L@KOE1=18:FJEAO;<720HDOKI=7=<>BNIMC7:364DHCGM91902NBMIG38?:8@LGCA53546JFBEK?4;?<L@HOE1??>89GMGBN48;556JFBEK?578>3MCIHD2>3?;8@LDCA5;?245KICFJ843912NBNIG317<:?AOEL@6:;374DH@GM97?601OEOJF<0;=<>BNJMC7=374DH@GM947601OEOJF<33==>BNJMC7>?06;EKA@L:5;730HDLKI=07:<=CAKNB0?;19:FJFAO;:?427IGMDH>13;?<L@HOE1<7>89GMGBN4;3546JFBEK?6;?<L@HOE1=?>c9GMGBN4:;1<374DH@GM956611OEOJF<2<;?AOEL@6?255KICFJ808?3MCIHD29>99GMGBN4>437IGMDH>;:==CAKNB0408;EKME96902NBBL2>0?:8@LHF48;546JFN@>26;><L@DJ0<=18:FJJD:6<720HD@N<07=<>BNFH6::364DHLB841902NBBL2>8?:8@LHF4835;6JFN@>2:==CAGK7>=07;EKME946611OECO323<;?AOII588255KIOC?618?3MCEM1<:>99GMKG;:?437IGAA=04:==CAGK7>507;EKME94>6>1OECO32?:8@LHF4::546JFN@>05;><L@DJ0><18:FJJD:4;720HD@N<26=<>BNFH689364DHLB860902NBBL2<7?:8@LHF4:2546JFN@>0=;1<L@DJ0>0n;EKME92729437IGAA=63:2=CAGK78394DHLB80803MCEM1817:FJJD:06>1OECO38?58@LHF404<7IGAB=2=<>BNFK6:<364DHLA847902NBBO2>2?:8@LHE489546JFNC>20;><L@DI0<;18:FJJG:6>720HD@M<05=<>BNFK6:4364DHLA84?9?2NBBO2>>99GMKD;:9437IGAB=02:==CAGH7>?07;EKMF944611OECL325<;?AOIJ58>255KIO@?638?3MCEN1<8>99GMKD;:1437IGAB=0::2=CAGH7>364DHLA866902NBBO2<1?:8@LHE4:8546JFNC>07;><L@DI0>:18:FJJG:4=720HD@M<24=<>BNFK68;364DHLA86>902NBBO2<9?58@LHE4:4j7IGAB=63>58?3MCEN1:?>69GMKD;<7=0HD@M<4<4?AOIJ5<5;6JFNC>4:2=CAGH74394DHLA8<8f3MC[MIG_<1<b?AOWIMC[0<0n;EKSEAOW4;4h7IG_AEKS86<76h1OE]OKIQ>0:d=CAYHOE]2?>`9GMUDCAY6:2l5KIQ@GMU:56j1OE]LKIQ>0>58f3MC[NIG_<2<;?AIFLF6;245KO@FL846912NDMIA310<:?AIFLF6:>374DNCGK974601OCLJ@<06==>BHIME7=806;EMB@J:6>730HBOKO=34:<=CGHND0<619:FLEAI;90437IANDN>2:<=CGHND0?>19:FLEAI;:8427IANDN>16;?<LFKOC1<<>89GKDBH4;>556J@AEM?608>3MEJHB2=6?;8@JGCG58<245KO@FL87>912NDMIA328<;?AIFLF69245KO@FL8669j2NDMIA33083:<=CGHND0>?18:FLEAI;;720HBOKO=6=<>BHIME79364DNCGK90902NDMIA37?:8@JGCG52546J@AEM?=;1<LFKT^HI7;EMA@J:7601OCOJ@<02==>BHJME7=<06;EMA@J:6:730HBLKO=30:<=CGKND0<:19:FLFAI;9<427IAMDN>22;?<LFHOC1?8>89GKGBH482556J@BEM?5<8?3MEIHB2>>89GKGBH4;:556J@BEM?648>3MEIHB2=2?;8@JDCG588245KOCFL872912NDNIA324<:?AIELF69:374DN@GK940601OCOJ@<3:==>BHJME7>407;EMA@J:5601OCOJ@<22=f>BHJME7?<4?>89GKGBH4:;546J@BEM?7;><LFHOC1:18:FLFAI;=720HBLKO=4=<>BHJME7;364DN@GK9>902NDNIA39?58@JDXZLMj7IA_AEMS858f3ME[MIA_<0<b?AIWIME[0?0l;EMSEAIW4:0;2l5KOQCGKU:46h1OC]LKOQ>3:d=CGYHOC]2>>`9GKUDCGY692n5KOQ@GKU:4294j7IA_BEMS868?3ME^XL2?>89GKPRF48:556J@UUC?548>3ME^XL2>2?;8@JSSI5;8245KOTVB842912NDYYO314<:?AIR\H6::374DNWWE970601OCXZN<0:==>BH]]K7=407;EMVPD:6601OCXZN<32==>BH]]K7><06;EMVPD:5:730HB[[A=00:<=CG\^J0?:19:FLQQG;:<427IAZT@>12;?<LF__M1<8>89GKPRF4;2556J@UUC?6<8?3ME^XL2=>89GKPRF4::556J@UUC?748>3ME^XL2<2?;8@JSSI598245KOTVB862912NDYYO334<:?AIR\H68:374DNWWE950601OCXZN<2:==>BH]]K7?407;EMVPD:46k1OCXZN<5294;?<LF__M1:?>99GKPRF4=437IAZT@>6:==CG\^J0;07;EMVPD:0611OCXZN<9<;?AIR\H62255KOTVA858>3ME^XO2>0?;8@JSSJ5;:245KOTVA844912NDYYL312<:?AIR\K6:8374DNWWF972601OCXZM<04==>BH]]H7=:06;EMVPG:60730HB[[B=3::==CG\^I0<06;EMVPG:58730HB[[B=02:<=CG\^I0?<19:FLQQD;::427IAZTC>10;?<LF__N1<:>89GKPRE4;<556J@UU@?628>3ME^XO2=8?;8@JSSJ582255KOTVA878>3ME^XO2<0?;8@JSSJ59:245KOTVA864912NDYYL332<:?AIR\K688374DNWWF952601OCXZM<24==>BH]]H7?:06;EMVPG:40730HB[[B=1::==CG\^I0>0m;EMVPG:383:556J@UU@?058?3ME^XO2;>99GKPRE4<437IAZTC>5:==CG\^I0:07;EMVPG:?611OCXZM<8<`?@EDXHXBXT2?>b9FGFVFZ@^R0<0l;DA@TDTN\P692n5JCBRBVLR^4:4h7HMLP@PJP\:36j1NON^NRHVZ808d3LIH\L\FTX>5:`=BKJZJ^DZV<683:f=BKJZJ^DZV<6<0?@HF?2OEM_JJN99FJDTCMGF37H@NREGMQ6=BFK=0ICLXRDL;?@HE_[OE@55JNCUQAKSe3LDTINMPRDCGg>CIWLIHSZ\FTD33?C3D<OLH8K;?0GD340=AIEYN>6HK3:DGG1=ALJO87KJ_4:DGT@773OLMJKHIF6DEBC@AN81L?6IAD09J6>O7:2C:>6G=2:K06>O3:2C>46GAIUR\45><AGC_\R>>8:KMMQVX8;20ECG[P^20<>OIA]ZT<964IOKWTZ6202CEEY^P07:8MKOSXV:<46GAIUR\4=><AGC_\R>68:KMMQVX8H20ECG[P^2A<>OIA]ZT<N64IOKWTZ6C02CEEY^P0D:8MKOSXV:M56GAIUQWEQC03@DBXR>?7:KMMQY79>1BBDZP0358MKOSW99<7D@FT^273>OIA]U;9:5FNHV\431<AGC_S=98;HLJPZ6??2CEEYQ?969JJLRX8H=0ECG[_1@4?LHN\V:H;6GAIU]3@2=NF@^T<H94IOKW[5@03@DBXR??7:KMMQY69>1BBDZP1358MKOSW89<7D@FT^373>OIA]U:9:5FNHV\531<AGC_S<98;HLJPZ7??2CEEYQ>969JJLRX9H=0ECG[_0@4?LHN\V;H;6GAIU]2@2=NF@^T=H94IOKW[4@03@DBXR<?7:KMMQY59>1BBDZP2358MKOSW;9<7D@FT^073>OIA]U99:5FNHV\631<AGC_S?98;HLJPZ4??2CEEYQ=969JJLRX:H=0ECG[_3@4?LHN\V8H;6GAIU]1@2=NF@^T>H94IOKW[7@03@DBXR=?7:KMMQY49>1BBDZP3358MKOSW:9<7D@FT^173>OIA]U89:5FNHV\731<AGC_S>98;HLJPZ5??2CEEYQ<969JJLRX;H=0ECG[_2@4?LHN\V9H;6GAIU]0@2=NF@^T?H94IOKW[6@03@DBXR:?7:KMMQY39>1BBDZP4358MKOSW=9<7D@FT^673>OIA]U?9:5FNHV\031<AGC_S998;HLJPZ2??2CEEYQ;969JJLRX<H=0ECG[_5@4?LHN\V>H;6GAIU]7@2=NF@^T8H94IOKW[1@03@DBXR;?7:KMMQY29>1BBDZP5358MKOSW<9<7D@FT^773>OIA]U>9:5FNHV\131<AGC_S898;HLJPZ3??2CEEYQ:969JJLRX=H=0ECG[_4@4?LHN\V?H;6GAIU]6@2=NF@^T9H94IOKW[0@03@DBXR8?7:KMMQY19>1BBDZP6358MKOSW?9<7D@FT^473>OIA]U=9:5FNHV\231<AGC_S;98;HLJPZ0??2CEEYQ9969JJLRX>H=0ECG[_7@4?LHN\V<H;6GAIU]5@2=NF@^T:H94IOKW[3@03@DBXR9?7:KMMQY09>1BBDZP7358MKOSW>9<7D@FT^573>OIA]U<9:5FNHV\331<AGC_S:98;HLJPZ1??2CEEYQ8969JJLRX?H=0ECG[_6@4?LHN\V=H;6GAIU]4@2=NF@^T;H94IOKW[2@13@DBXRO9;HLJPZD>3@DBXRHFLDf8MKLBK]NIEYK]Re9JJOCD\ZHBXH\]3:KMR3=KGHNNH;5COBIF@2=KGNCHMA:4LTV10>JR\:>0@XZ;4:NVP02<D\^=96C\GNL6?HS_KPi0Ald`rWgqwliik2Gbbb|Yesqjkk4<F980B<94NDVTKWM33GEEI<5@169LTQOJASOT\_GBIUKUAVYIOJ;0\n5_.3227466;VF?7]O]T`9SMKYE]ZCOTo5_IO]AQVHFEL30\FQGLTVMI6=WZL<0\^J@ND38U==UIDH8:H?i;SCN[@^SMGYBCCQNf:PBIZC_\LDXEB@PB99QEHYJGMOh7_JNDEPFGF:76m1YHLJKRDA@8469l2XOMIJ]EBA?548a3[NJHI\JCB>26?69l2XOMIJ]EBA?578d3[NJHI\JCB>2:f=ULHNO^HML<3<`?WBFLMXNON2<>b9Q@DBCZLIH090l;SFB@ATBKJ6>2n5]D@FGV@ED4?4h7_JNDEPFGF:06l1YHLJKRDA@8=<76j1YHLJKRDA@8=8d3[NJHI\JCB>::4?<ZMKOH_QLOMNJWLIIWA]HCCHFG`9QADBXN@XXXn5]E@F\SLBS@VKh7_KND^UJ@QNXJ<1YIJMJb:PFCFCF490;245]EFAFE969j2XNKNKNRDE@Af=UMNINM_KHCDN`?WC@KLKYIJMJU79QABEBJk1YIJMJB=294;?<ZLMHIO2?>69QABEBJE=0^HILECWf?WC@KEAJ^I\LLJNf?WC@KEAJ^I\LLJW;?WC@KEAI@55]EFAOOGS>3[Y_M1>50?58VVRF49427_][B=294;1<ZZ^I0=0k;SQWVDKFZZ^YM@k4RRVQEHGU[]XJAAk4RRVQEHGU[]XJAX94RRVQEHD?3[Y_^LCML99QWQTFEK_o7_][RDEBVVRUMNo0^^Z]EFCQWQTBOEo0^^Z]EFCQWQTBO\=0^^Z]EF@;?WUSZLMI@55]SUPFCGS692XXX_KH_QPJKWOSQVK:=6\\TSGD[UTNG[C_URL>;R:8WDPBLH^J;6]MIUGQV6=TLY;:7^F]EF]F\QTFK]UEKNk4SIPFCZKNFVYBVH?<;RKN[FIKD@YBCCQLHDAHe>UNEVNNZDMJ8:QHMUYWAG<0_B[]CD58WWPFDVK<7^\YAM]A2>USI]_X86Z]UD68P\VB>91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(k8%laxv!c`pq}kcs494=<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+tt|z%h="ibuy,`ewt~fl~7=38?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"m>/fov|+efz{seiy2=>728Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b3,chs&jky~t`jt=1=24=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g4)`e|r%k`U?]/en5+k6>81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(k8%laxv!glY2Y+aj{'gx:<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$o<!hmtz-ch]5U'mf#c|609V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$yy} c0-dip~)odQ8Q#ibs/op24=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g4)`e|r%k`U;]/enw+kt=<1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(k8%}=1>1579V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$yy} c0-u59699<?0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j;$z<2>>448Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b3,r4:668?>7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*wus{&i:#{?32?75?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.a2+s7;:7;>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+tt|z%h="x><2<62>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#||tr-`5*p64:4:985Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$o<!y1=6=13=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g4)q95>5=;>4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#n< glw{*fguzpdnx1>1619V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$yy} c3-dip~)khxyuck{<0<54>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#||tr-`6*aj}q$hm|vndv?6;073\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.sqww*e5'ng~t#mnrs{maq:46?;0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j8$k`{w.foX4X(`e8$f=;?4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#n< glw{*bk\9T$la~ bs738Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b0,chs&ngP>P hmr,nw37<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!rrvp+f4(ods"jcT3\,div(j{?;0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j8$k`{w.foX0X(`ez$f8;4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#n< v0>3:00<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!rrvp+f4(~86;2<;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"m=/w3?5;313\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.sqww*e5';7=3?:5:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'xxx~!l2.t28782>2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/pppv)d:&|:0?0>549V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$yy} c3-u5959=?1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(k;%}=1=11478Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b0,r4:36<<0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j8$z<2;>071?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.aliu62:2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/pppv)dgdz::i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$kbgag^gntqXdlk}eciPelrw}ZIUW?Ud:h5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$kbgag^gntqXdlk}eciPelrw}ZIUW?Ud=8l4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#ob_dosp|YajVc>46[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+tt|z%ym`Qjmqvz[l2a3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~lcPre]fjZo6=>1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|k_qlwvZvk}z;7<3Qfnw5g?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"Cnde]dg5(dg|dW5SPGOF\616XgVkohR>POTV\|jt;87;:SD@Y_154?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"Cnde]dg5(dg|dW5SPGOF\616XgVkohR>POTV\|jt;97;:;:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(EhnoSjm?.bmvjq]?UVMEHR<;0^m\eabX8VE^XRv`r=0=54103\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.Ob`aY`k9$hcx`{[9_\CKBX:=:TcRokd^2\KPRXpfx7?3?>769V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$Aljk_fa3*firf}Q3QRIAD^074ZiXimnT<RAZT^zlv92998=<7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*KflmUlo= lotlw_=[XOGNT>9>Po^cg`Z6XG\^Ttb|35?3232=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| M`fg[be7&je~byU7]^EM@Z438VeTmijP0^MVPZ~hz5<5=<97;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&GjhiQhc1,`kphsS1WTKCJP252\kZgclV:TCXZPxnp?2;769>=0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+HgclVmh<#m`uovX<XY@FMU98=Q`_`fg[5YH]]Usc28>0343>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!Baef\cf6)kfexV6R_FLG[727WfUjhiQ?_NWW[}iu414:=8;4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu>3:03<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}6:28;4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu>1:03<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}6828;4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu>7:03<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}6>28;4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu>5:03<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}6<28;4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu>;:3e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}Q3QRIAD^074ZiXimnT<RAZT=3=2f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|R2VSJ@K_363[jYflmU;SB[[<3<5g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsS1WTKCJP252\kZgclV:TCXZ33?4`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkr\0TULBIQ=41]l[dbcW9UDYY2;>7a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjq]?UVMEHR<;0^m\eabX8VE^X1;16b9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmp^>ZWNDOS?:?_n]b`aY7WF__0;09c:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw_=[XOGNT>9>Po^cg`Z6XG\^7;38l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uovX<XY@FMU98=Q`_`fg[5YH]]6328:4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu]311=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|V;>86[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{_377?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkrX;<>0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+be7&je~byQ;559V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmpZ32<2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-dg5(dg|dS;;;;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\302<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}U3955Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{at^f2848202_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-dg5(dg|dSi?32?7;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkrXl8682864U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu]g5929=11^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexRj><4<6<>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsWm;7:3;7;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\`4:06<20Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+be7&je~byQk1=:=12=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|Vn:S<;8;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\`4Y5=>1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexRj>_274?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkrXl8U?9:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{at^f2[0303\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~Th<Q9569V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmpZb6W>?<7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*ad8'idyczPd0];25=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ xsuq,g5)`e|r%ol|}yogw858182_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d8&mfyu laspzj`r;97<;7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i;#jczx/abvwim}692;>4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)z~x#n> glw{*fguzpdnx1=1609V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$|y} c1-dip~)odQ;Q#ib1/o224=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ xsuq,g5)`e|r%k`U>]/enw+kt>81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,twqu(k9%laxv!glY1Y+aj{'gx:<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$o=!hmtz-ch]4U'mf#c|609V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$|y} c1-dip~)odQ?Q#ibs/op10=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ xsuq,g5)q95:59;5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$o=!y1=2=503<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!wrvp+f6(~86:2884U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)z~x#n> v0>2:4323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e7';7>3;9;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m?/w3?6;72=2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d8&|:0>0:6:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l0.t28686=<1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,twqu(k9%}=1:1579V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$|y} c1-u59299?:0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hwrq-svrt'j;$k`{w.bcqv|hb|5:5:=5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$o<!hmtz-gdtuqgo0<090:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l1.enq}(di{xrbhz32?43?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.a2+bkrp'ij~waeu>0:37<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!wrvp+f7(ods"jcT0\,di4(j9?;0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hwrq-svrt'j;$k`{w.foX5X(`ez$f;?4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)z~x#n? glw{*bk\:T$la~ bs738Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%{~z|/b3,chs&ngP?P hmr,nw37<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!wrvp+f7(ods"jcT4\,div(j{<?0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hwrq-svrt'j;$z<2?>448Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%{~z|/b3,r4:768?>7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i:#{?31?75?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.a2+s7;97;>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+qt|z%h="x><3<62>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`5*p64;4:985Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$o<!y1=1=13=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ xsuq,g4)q9595=8;4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)z~x#n? v0>7:00<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!wrvp+f7(~86?2<;=;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m`mq266>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`khv6=h1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,twqu(zhgTjxbc_bmnf0g<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!wrvp+wgjWog`Rhm_h74?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.pbiZ`rdeUb8k5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.pbiZquWldTe<9l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&GjhiQhcb2-cf6)kfexV6R_FLG[736WfUjhiQ?_NWW[}iu484:=:m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'DkohRilc1,dg5(dg|dW5SPGOF\607XgVkohR>POTV\|jt;:7;:;n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(EhnoSjml0/e`4+eh}g~P4PQHNE]114YhWhnoS=Q@UU]{kw:468;<o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)JimnTknm?.fa3*firf}Q3QRIAD^065ZiXimnT<RAZT^zlv92998=h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*KflmUlon>!gb2-gjsi|R2VSJ@K_372[jYflmU;SB[[_ymq80869>i0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!xpovq+HgclVmho= hc1,`kphsS1WTKCJP243\kZgclV:TCXZPxnp?2;76?m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,IdbcWnih<#il0/alqkr\0TULBIQ=50]l[dbcW9UDYYQwos>5:476?j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,IdbcWnih<#il0/alqkr\0TULBIQ=50]l[dbcW9UDYYQwos>4:470k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-NeabXoji;"jm?.bmvjq]?UVMEHR<:1^m\eabX8VE^XRv`r=:=543f3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{<0<6e>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!hcb2-cf6)kfex1<15`9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}6828o4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'nih<#il0/alqkr;<7?j7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw8082i2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dgf6)oj:%ob{at=4=1d=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~by28>4c8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pxg~y#jml0/e`4+eh}g~7439>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsS1WTKCJP243\kZgclV:TCXZ31?52?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dW5SPGOF\607XgVkohR>POTV?6;163\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{[9_\CKBX:<;TcRokd^2\KPR;;7=:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw_=[XOGNT>8?Po^cg`Z6XG\^7839>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsS1WTKCJP243\kZgclV:TCXZ35?52?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dW5SPGOF\607XgVkohR>POTV?2;163\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{[9_\CKBX:<;TcRokd^2\KPR;?7=:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw_=[XOGNT>8?Po^cg`Z6XG\^743;6;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsW8?27X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[73>3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{_27:?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dS9;6;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsW<?27X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[33>3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{_67:?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dS5;k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsWm;7<3;k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsWm;7=3;k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsWm;7>3;k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsWm;7?3;k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsWm;783;k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsWm;793;k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsWm;7:3;k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsWm;7;3;k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsWm;743;l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsWm;T<8m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'nih<#il0/alqkrXl8U:9n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(oji;"jm?.bmvjqYc9V8>o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`kj:%kn>!cnwmpZb6W:?h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7X<<i0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!xpovq+bed8'mh<#m`uov\`4Y2=j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5Z02k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dgf6)oj:%ob{at^f2[23d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{_e3\<05<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%|~R~ats]shpu64943=6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'gna"imm/eaib(`jdmj"cijcb,aib)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+sgkam$hy|;d:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#cjm.vntZtfeVxoSh`;e:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#cjm.vntZtfeVxoSh`>329V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#ob_sf\ak543\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qehYpzVoe985Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae Mlw{[wbXzz~Tm~|jg^EM@Z75WfUFYUQ=_n3210=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(EdsSz|Prrv\evtboVMEHR?=_n]NQ]Y6Wf;:?i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae RRV\BPJKWNOE855Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae gsqw`4(`zz~Tjxbc.sqw[a7302_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%l~~zk1/eqwqYa}ef%~~zPd36;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!}su`oo*au{}n:"j||t^dvhi(u{}Uo?9m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&xxxobd/oetvatt|'myy }d^pppZtbo5:58n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae nfuq`wus&nxxx#|k_sqw[wc`4;4?n6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!agvpgvvr)o{y"jPrrv\v`aX8=h0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*tt|kf`#cixreppp+au{}$yhR||t^pfcZ43k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%ekz|krrv-cwus&~xT~~zPrde?5;2e3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&dl{j}su,dvvr){UyyQ}ef]27a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(zmUyyQnssgd0`=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(zmUyyQnssgd[BHCW88TcRCZX^0\k16<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'{nT~~zParpfcZb6<91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wusjea$~iQ}su]bwwc`Wm88o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!}d^pppZehek9o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"|k_sqw[fijj89o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"y}_sqw[duumn>n7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"y}_sqw[duumnULBIQ>2^m\IP^X9Ve?<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!xr^pppZgtzlmTh<:?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%yylck.uq[wusWhyyijQk22a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+rtXzz~Tobcm3e9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#}{bmi,swYu{}Uhc`l>3g9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#z|Ppovq858Xag|:SD@Y_1a8QVCUW_CXEOBJ3:T@G<=QAL]TXT^J7:TJVQC_>?1\IL2?>79TAD:66?1\IL2=>99TAD:4294=7ZKN<2<;?RCF4=0;2;5XE@>7:2=PMHF7<394WDCO84803^OJ@1<19:UFEI:4294<7ZKNL=1=3>QBI\6;2:5XE@W?5;1<_LK^0?06;VGBQ95=87=0[HOZ<2<5?RCE494=7ZKM<0<5?RCE4;4=7ZKM<2<;?RCE4=0;2;5XEC>7:==PMK]N0=07;VGAS@:6611\IOYJ<3<;?RCE_L68255XECUF818?3^OI[H2:>99TAGQB4?4j7ZKMWD>4>58?3^OI[H28>89TAGQBD5:556YJBVGO848>3^OI[HB32?;8S@DPME68245XECUFH92912]NNZKC<4<:?RCE_LF7:3l4WD@TAI:029427ZKMWDN?3;?<_LH\IX2?>89TAGQB]5;556YJBVGV878>3^OI[H[33?;8S@DPM\6?245XECUFQ93912]NNZKZ<7<a?RCE_L_7;7>19:UFFRCR4>4h7Z\FTD]NKACXIj1\^DZJ_LMGAZDc3^XBXHQXIEVK[Db<_[C_IRYFDUJ\F4b<P@FBBU#WDC"3*4&T\\H+<#?/ARAJM3=_[]FBN:5WSU]DJA1<PZ^TZNMm;Y]@KWCXAGLD:6Vkb^Kgb>^c`VZye`Xjrrklj46<PmgTAld`rWgqwlii991Sh`QBiomqR`ttafd87U}{3:[fw=g<WVUS@CCP_^2\[ZS7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!Baef\cfe7&ni;"naznuY;YZAILV8>=RaPaef\4ZIR\Vrd~1:110:6?ZYXPEDFSRQ>_^]V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$Aljk_fa3*firf}Q3QRIAD^074ZiXimnT<RAZT^zlv929982j7RQPXMLN[ZY5WVU^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,IdbcWnih<#il0/alqkr\0TULBIQ=50]l[dbcW9UDYYQwos>4:47?=2UTSUBAM^]\7ZYX]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/Lcg`Zad8'idyczT8\]DJAY5<9UdSljk_1]LQQYg{6<2<?7a:]\[]JIEVUT8RQPU1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'DkohRilc1,dg5(dg|dW5SPGOF\607XgVkohR>POTV\|jt;:7;:485P_^ZOJHYXW<UTSX> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*KflmUlo= lotlw_=[XOGNT>9>Po^cg`Z6XG\^Ttb|32?321a=XWVRGB@QP_7]\[P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zhgT~iQjn^k226=XWVRGB@QP_6]\[P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!}su`oo*Kj}qU|~R||t^cpv`aXOGNT=?Q`_LW[[4Yh98<87RQPXMLN[ZY?WVU^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wusjea$A`{w_sf\vvrXizxnkRIAD^31[jYJ]QU9Sb?>199ahnYjmdUlicQheogqmfYd{}x::6lck^ofiZabfVzye`Qxievk5g=edbUfi`Qheo]svlkX{k{|h|Pv7d8fimXelgTkh`Ptnr20>dkcVgnaRijn^t4[4Y{};87obd_lgn[lhw}}Ui`bmd159ahnYjmdUdyy~zt^`okfm43jf`;6m`mqcqa6=cld<0hd`30?58`lh;994<7iga<03=3>bnf5;92:5kio>27;1<l`d7=908;ekm8439?2nbb1?9>69gmk:6?7=0hd`319<4?aoi4835:6jfn=3=3>bnf58;2:5kio>15;1<l`d7>?08;ekm8759?2nbb1<;>69gmk:5=7=0hd`327<4?aoi4;=5;6jfn=0;:2=cag695384dhl?6;1<l`d7?=08;ekm8679?2nbb1==>69gmk:4;7=0hd`335<4?aoi4:?5;6jfn=15:2=cag68;394dhl?7=803mce0>716:fjj95912nbb1:?:1<4?aoi4=:5:6jfn=6=2>bnf5?5:6jfn=4=2>bnf5=5:6jfn=:=2>bnf535;6j`uu>3:==cg|~7==07;emvp976611ocxz313<;?air|5;8255kotv?518?3me~x1?:>99gkpr;9?437iazt=34:==cg|~7=507;emvp97>6>1ocxz31?:8`jss4;:546j`uu>15;><lf0?<18:flqq:5;720hb{{<36=<>bh}}699364dnww870902ndyy2=7?:8`jss4;2546j`uu>1=;1<lf0?07;emvp957611ocxz330<;?air|599255kotv?768?3me~x1=;>99gkpr;;<437iazt=15:==cg|~7?:07;emvp95?611ocxz338<4?air|595m6j`uu>74?6902ndyy2;0?58`jss4=4<7iazt=7=3>bh}}6=2:5kotv?3;1<lf0508;emvp9?9=2of|yw>6:djbjY`mgoymya}_scnbl`h9;1mekaPgdlfvdrhzV~d|<=4fhdl[bcim{kcQy9^11b>`nnfUlick}aumq[s?X;%*Seagax!ALV@&@mgoymya} 06-341<n`ldSjkaescwkwYq1V9Tt~z;;gwoh<=nfySobd6:ofijt~02dloo{fle08jjg<g|~{yyQmlj11?wgjdfe{W=S!r`o-v*p1Wgebbdz!r`o,WAV)_@NNS]\FM24-vdke3{nTnd`Pcovq1>tcWld37jPlnejg44<zmUxxlzzs^doebuX{z;:7k|eu]ahnYuidlbjb=4rrv24>u~fjUmekaP500{0477j<1xucmPfhdl[075p=;'jdh`_fgmawgsg{U}5R=#{b]b`aYiojUhcc}{r`kmp86+kVk{|aglaukljZr~xlUjtd}20-a\euvkajkeb`Ptxrf[wgd`4:'oRopmk`eqohfV~r|hQ}dbj>4)eXiyzgeno{inl\p|vbW~khd0>#c^cstiodi}cdbRzvpd]t`fn:8%iTm}~cibcwmjhX|pznSz|lh<2/gZgaVkohQxievk964+kVkseRo}urgq[roc|a7: nQnxh]bspubzV}bhyf21-a\e}oXj|yn~Ryfduj>5)eXiqcThlzn_vkgpm;1<%iTmugPie]tmaro5=&hSlvf_swpawYpam~c1<"l_`zj[qwm4:'oRowi^uvw`tX`nd0?#c^c{mvYslh~jSzgkti?50)eXiqcxSyjjsu]tmaro5=&hSlvfs^vj`Zqnl}b64!mPaykp[qmbmyU|eizg=5.`[d~n{V~xxlPwhfwl82+kVkse~Q{urgq[roc|a7? nQnxhq\p|vb59&hSnabmnl\giidc4;'oRm`uov\p|vb59&hSio{a^alqkrX`nd07#c^ffbdsk|V|j`xk2BmcmoVruagm'oRjfn^uj`qn:<8&hSiga_vkgpmYfp`y6=!mPdhl\slbs`Vxjoe3<2-a\`lhX`ndR|kci?50)eXl`dT{dj{h^ubgm;4:%iThd`PwhfwlZqcka7=8!mPdhl\slbs`V}yoe3=,b]gkprXzz~Tzlb20-a\`jssW~coxe3;1-a\akgedlUy`bm|=1.`[`hfjeoT~~zPsxl`94*dWlxycQfnkg`pliiW}s{i0>#c^gqvjtXag`noyg`n^vzt`Yfp`y6<!mPesplvZoiblieb`Ptxrf[wgd`4:'oRk}rnp\mklbk}cdbRzvpd]q`fn:8%iTi|`r^kmn`esafdTxt~j_vc`l86+kVoy~b|PiohfgqohfV~r|hQxdbj>4)eXm{xd~RgajdawmjhX|pznSz|lh<2/gZ`fe`fr1{g}tdz5(fYa}efTjaohs^pppZpfd4;'oRfns^coijusWlg{xt3?,b]kevYfddexxRhzlm?3(fYoizUjtdQnrtqfv86+kVbjRowi^ctqvcu59&hSeo|_`zj[gstm{7; nQgar]b|lYulVicmc`jl<2/gZnf{VkseR|zsdp>4)eX`hyTmugPws]`ldhime7; nQgar]b|lYp}zoy1="l_icp[d~n{V~omyo20-a\lduXiqcxSyjjsu?3(fYoizUjtd}Pthf>4)eX`hyTmug|_uifau;7$jUcm~Qnxhq\pigt|4:'oRfns^c{mvYszlkou0?#c^jbwZgazUy|m=1.`[mgtWhrbRzzsdp>4)eX`hyTnlmduq?3(fYoizUomyoPcnwmp86+kVbjRjnt`]`kphs{Vkse~3?,b]kevYci}kTob{atr]qefn:8%iTdl}Pd`vb[firf}yT~img=1.`[mgtWmkmRm`uovp[rgd`4:'oRfns^fbpdYdg|dRykci?3(fYoizUomyoPcnwmpvYpzjb6<!mPh`q\mkrXkea6<!mPh`q\idusm{Uhi0>#c^jbwZkbe`dbxRhfld?3(fYoizUdzh|ilnu>4)eX`hyT|ah_gnbcvYfp`y6<!mPh`q\twi`Wofjk~Q}abj>4)eX`hyT|ah_gnbcvYuljb6<!mPh`q\twi`Wofjk~Qxabj>4)eX`hyT|ah_gnbcvYpljb6<!mPh`q\twi`Wofjk~Qxrbj>4)eX`hyT~iQkauc\gjsi|4:'oRfns^pg[wus59&hSeo|_sqw94*dWakxS~bnvd]`a86+kVbjR}}su?3(fYoizU~bik}fmmt95*dWakxS{ocie?3(fYoizU|~Rolk<2/gZnf{V}ySio{a^alqkr:8%iTdl}Pws]qwq;7$jUba}bjmdlweqohfV~r|h3?,b]jiujbeldmyg`n^vzt`Yfp`y6=!mPilroahci|h~bccQ{yqg\vdeo58&hSdcldofjqgsafdTxt~j_sf`l87+kVcf|akbeovbpliiW}s{iRynci?2(fYneyfnah`{aukljZr~xlU|hnf21-a\mhvkmdoexlzfoo]w}ucX{ic1<"l_hljpZquWyd~Rxnl<2/gZoi|lxmmnkPtxrf95*dWdofcwPtxrf94*dWdcmSkgce^lbi`;Edhd`_y|fnf.`[hu`ggU}ma3>,b]ltqojaskeb`Pmnff95*dWf|n~kb`w^nls86+kVzyiaand^nbp`hdq4;'oR~}emmb`Ztboz7; nQrho\bl`hW}s{i0;>2y51(fYwzfmTi`~{y^vkv`uoWhyxizPv`n>6)eXx{elShctx]wlwct`Vkxh|{_wco[d~n{4;;>?"l_qplcZcjx}sTxe|jsi]bwvcu|V|j`R|nci?2474+kVzycjQjmqvz[qnumzbTm~}jru]ueiYuljb6==<=,b]svjaXmdzuRzgrdqk[dutm{~TzlbPw`ak9465:%iT|ah_dosp|Ys`{oxdRo|sdpw[sgkW~nhd0??23.`[uthoVof|ywPtipfwmYf{zoyxRxnl^uqgm;68;8'oR~}of]fiur~W}byi~fPndebp`Yqie78 nQrne\ahvsqV~r|h3?,b]svjaXmdzuRzvpd]b|lu:8%iT|ah_dosp|YsqyoT~lmg=1.`[uthoVof|ywPtxrf[wbd`4:'oR~}of]fiur~W}s{iRynci?3(fYwzfmTi`~{y^vzt`Ypljb6<!mPpsmd[`kw|pUu}kPwsak95*dWyxdkRhzlm]wlwct`Vkxh|{_wco9077$jU{~biPftno[qnumzbTm~}jru]ueiYfp`y6==<<,b]svjaXn|fgSyf}erj\evubz}U}maQ}abj>5544$jU{~biPftno[qnumzbTm~}jru]ueiYuljb6==<<,b]svjaXn|fgSyf}erj\evubz}U}maQxabj>5544$jU{~biPftno[qnumzbTm~}jru]ueiYpljb6==<<,b]svjaXn|fgSyf}erj\evubz}U}maQxrbj>5544$jU{~biPftno[qnumzbTbhintd]uei;280&hS}|`g^dvhiYsqyo6<!mPpsmd[cskdV~r|hQnxhq>4)eXx{elSk{cl^vzt`Yuijb6<!mPpsmd[cskdV~r|hQ}dbj>4)eXx{elSk{cl^vzt`Ypijb6<!mPpsmd[cskdV~r|hQxdbj>4)eXx{elSk{cl^vzt`Ypzjb6<!mPr`ak[qwm4:'oR|k_ecweZeh}g~T{dj{h<;/gZtcWmo{xe3:13.`[wbXn{oz1<"l_sf\tkruW~coxe36,b]q`fnX|pzn1="l_sgd[vjnklUfcikPaykp95*dW{olS~bfcd]nkacXzhic1="l_sgd[vjnklUfcikPreak95*dW{olS~bfcd]nkacXhic1="l_sgd[vjnklUfcikPweak95*dW{olS~bfcd]nkacX{ic1="l_r{mgmthf`pn~R}{afg>6)eX}gnn~kb`w^nls86+kVxiRm`mlmm[jpbzofd{0>#c^wpaZehedeeSx`kesdokr;7$jU~hQkegcvhqYtm}~bbj}20-a\qvcXlfS}{=0.`[pubWlih1="l_tqf[`edWhrb0>#c^wpaZcdkVxjoe3?,b]vw`YbkjUyhnf20-a\qvcXmjiT{lmg=1.`[pubWlihSzjlh<2/gZstmVohoRy}ci?3(fYr{lUnaokkddf\v`a:8%iTy~kPfhdl53Yadhmx1="l_tqf[cqa|VnjxlQlotlw95*dWkgeiQcov?3(fYpijbTxt~j=1.`[rbd`V~r|h3?,b]tvZgdcVfd{0>#c^uq[agsiVidyczPwhfwl8?+kV}ySikti?657*dW~xThh~{h^c{mv;68;>'oRy}_egspmYuijb6=;"l_vp\``vs`Vxooe3>036/gZquWmo{xeQxabj>53*dW~xThh~{h^uggm;68;>'oRy}_egspmYpzjb6=;"l_vp\bwcv58&hSz|Ppovq[roc|a72 nQxr^rmpwYpam~cSlvfs<33(fYpzVzexQxievk[wgd`4>'oRy}_qlwvZqnl}bT~img=02/gZquWyd~Ryfduj\sdeo5=&hSz|Ppovq[roc|aU|hnf211.`[rtXxg~ySzgkti]tvfn:<%iT{Q}errljvcXdh~nbnw21-a\sweoW}s{i0>r269p}keXn`ldS8?=x53/bl`hWnoeio{os]u=Z5+sth0{Qmio]`jqt23~xTic64ws]okbod9;1|~R}{auwp[cjfozUxpNOp60e?EF<l;1J7:51zQga?21=38m?7?<34143?4509:pb98<:09m032=>2.?:<4;5b9~Wae=<??1>k=51216721=:;2:?6]=e187`2<728989>98:30;53=Tlj0?h:4?:01016102;83=55k4d394?7=9rYoi7:95;0e7?74;<9<;7<=8038rQ54k3:1=7?5d3yP``<3><09j>4>327032<5:1;:7):=4;0f6>P3>;09wx<ja;38q7ce291v(?h;:3f8f1c6290>479m:e2xL1453-9?=7:j1:Xa=?4|9k0:i7s+47290a4<,j:18h=4$ef90`4<,:936<5+3259030<a=3o6=4+2g490<e<f;l>6=54i5;b>5<#:o<184m4n3d6>4=<a=326=4+2g490<e<f;l>6?54i5;;>5<#:o<184m4n3d6>6=<a=3<6=4+2g490<e<f;l>6954i5;5>5<#:o<184m4n3d6>0=<a=3>6=4+2g490<e<f;l>6;54i5;7>5<#:o<184m4n3d6>2=<a=386=4+2g490<e<f;l>6554i5;1>5<#:o<184m4n3d6><=<a=3:6=4+2g490<e<f;l>6l54i5:e>5<#:o<184m4n3d6>g=<a=2n6=4+2g490<e<f;l>6n54i5:g>5<#:o<184m4n3d6>a=<a=2h6=4+2g490<e<f;l>6h54i5:a>5<#:o<184m4n3d6>c=<a=2j6=4+2g490<e<f;l>6<>4;h6;=?6=,;l=697l;o0e1?7632c?454?:%0e2?2>k2d9j84>2:9j0=1=83.9j;4;9b9m6c3=9:10e969:18'6c0=<0i0b?h::068?l2?<3:1(?h9:5;`?k4a=3;>76g;8283>!4a>3>2o6`=f4822>=n<181<7*=f787=f=i:o?1=:54i5:2>5<#:o<184m4n3d6>4><3`>3<7>5$3d5>1?d3g8m97?6;:k73c<72-8m:7:6c:l1b0<6i21b8:k50;&1b3<31j1e>k;51c98m11c290/>k8548a8j7`228i07d:8c;29 7`12=3h7c<i5;3g?>o3?k0;6)<i6;6:g>h5n<0:i65f4`194?"5n?0?5n5a2g795c=<a=k96=4+2g490<e<f;l>6?>4;h6b5?6=,;l=697l;o0e1?4632c?m=4?:%0e2?2>k2d9j84=2:9j0<`=83.9j;4;9b9m6c3=::10e97j:18'6c0=<0i0b?h::368?l2>j3:1(?h9:5;`?k4a=38>76g;9183>!4a>3>2o6`=f4812>=n<1?1<7*=f787=f=i:o?1>:54i55b>5<#:o<184m4n3d6>7><3`><;7>5;h6f4?6=3`>n97>5;h6gg?6=3f>h;7>5$3d5>1e13g8m97>4;n6`0?6=,;l=69m9;o0e1?7<3f>h?7>5$3d5>1e13g8m97<4;n6`6?6=,;l=69m9;o0e1?5<3f>h=7>5$3d5>1e13g8m97:4;n6`4?6=,;l=69m9;o0e1?3<3f>ij7>5$3d5>1e13g8m9784;n6aa?6=,;l=69m9;o0e1?1<3f>ih7>5$3d5>1e13g8m9764;n6ag?6=,;l=69m9;o0e1??<3f>in7>5$3d5>1e13g8m97o4;n6a=?6=,;l=69m9;o0e1?d<3f>i47>5$3d5>1e13g8m97m4;n6a3?6=,;l=69m9;o0e1?b<3f>i:7>5$3d5>1e13g8m97k4;n6a1?6=,;l=69m9;o0e1?`<3f>i87>5$3d5>1e13g8m97??;:m7f6<72-8m:7:l6:l1b0<6921d8o<50;&1b3<3k?1e>k;51398k1d6290/>k854b48j7`228907b:m0;29 7`12=i=7c<i5;37?>i3il0;6)<i6;6`2>h5n<0:965`4`f94?"5n?0?o;5a2g7953=<g=kh6=4+2g490f0<f;l>6<94;n6bf?6=,;l=69m9;o0e1?7?32e?ml4?:%0e2?2d>2d9j84>9:9l0d?=83.9j;4;c79m6c3=9h10c9o7:18'6c0=<j<0b?h::0`8?j2f?3:1(?h9:5a5?k4a=3;h76a;a783>!4a>3>h:6`=f482`>=h<h?1<7*=f787g3=i:o?1=h54o5ag>5<#:o<18n84n3d6>4`<3f>ho7>5$3d5>1e13g8m97<?;:m7gg<72-8m:7:l6:l1b0<5921d8no50;&1b3<3k?1e>k;52398k1e>290/>k854b48j7`22;907b:l8;29 7`12=i=7c<i5;07?>i3k<0;6)<i6;6`2>h5n<09965`4cc94?"5n?0?o;5a2g7963=<g=km6=4+2g490f0<f;l>6?94;n6b0?6=,;l=69m9;o0e1?4?32e?h94?::m7g`<722h?9k4?:083>5}#;=;18?=4H57g?M25:2e9j?4?::a00c=83;1<7>t$262>7263A>>h6F;239l616=831vn>8k:187>5<7s-9?=7<<d:J71a=O<;80(?;6:99jfd<722coj7>5;h0e<?6=3f8mm7>5;|`02f<72=0;6=u+353966b<@=?o7E:=2:&11<<?3`hj6=44ied94?=n:o21<75`2gc94?=zj:in6=4;:183!539388h6F;5e9K074<,;?2655fb`83>>ocn3:17d<i8;29?j4ai3:17pl<ce83>1<729q/?9?522f8L13c3A>9>6*=588;?ldf2900eih50;9j6c>=831d>ko50;9~f16e290?6=4?{%175?44j2B?9i5G4308 73>2:1bnl4?::kgf?6=3`nm6=44o3db>5<<uk>:97>54;294~"4<809?i5G44f8L1453Ah<7)<j8;174>oei3:17dji:188m7`?2900c?hn:188yg26j3:187>50z&004<5;m1C88j4H501?Md03-8n47=;0:kae?6=3`nm6=44i3d;>5<<g;lj6=44}c63a?6=<3:1<v*<40817a=O<<n0D9<=;I`4?!4b039?<6*=588;?ldf2900eih50;9j6c>=831d>ko50;9~f17?29086=4?{%175?44i2B?9i5G4308Lg1<,;o36>:?;%06=?5<akk1<75fdg83>>i5nh0;66sm40g94?5=83:p(>:>:31b?M22l2B?>?5Gb69'6`>=;=:0(?;6:29jfd<722coj7>5;n0ee?6=3th?<i4?:583>5}#;=;1>>j4H57g?M25:2Bi;6*=e98005=#:<3146gma;29?lba2900e?h7:188k7`f2900qo:>2;290?6=8r.88<4=3e9K00b<@=897)<:9;:8mgg=831bhk4?::k1b=<722e9jl4?::a047=83>1<7>t$262>75c3A>>h6F;239'60?=02cim7>5;hfe>5<<a;l36=44o3db>5<<uk>:;7>53;294~"4<809?l5G44f8L1453Ah<7)<j8;174>"5=0087dln:188ma`=831d>ko50;9~f173290?6=4?{%175?44l2B?9i5G4308 73>211bnl4?::kgb?6=3`8m47>5;n0ee?6=3th?=i4?:283>5}#;=;1>>o4H57g?M25:2Bi;6*=e98005=#:<31?6gma;29?lba2900c?hn:188yg27k3:187>50z&004<5;m1C88j4H501?Md03-8n47=;0:&11<<?3`hj6=44ied94?=n:o21<75`2gc94?=zj=:?6=4k5;192f}O<;80(>:>:553?_d>2mq:>7??:34970<613;86<?526802?7f28i1=i4<7;'f=<53`99>7>5$3d5>6463g8m97>4;h120?6=,;l=6>?<;o0e1?6<3`>9o7>5$3d5>14e3g8m97>4;h61e?6=,;l=69<m;o0e1?7<3`>947>5$3d5>14e3g8m97<4;h613?6=,;l=69<m;o0e1?5<3`>9:7>5$3d5>14e3g8m97:4;h64>5<#:o<18;5a2g794>=n<<0;6)<i6;65?k4a=3;07d:;:18'6c0=<?1e>k;52:9j06<72-8m:7:9;o0e1?5<3`>96=4+2g4903=i:o?1865f4083>!4a>3>=7c<i5;78?l27290/>k85479m6c3=>21b?k4?:%0e2?213g8m9794;h1f>5<#:o<18;5a2g79<>=n9=21<7*=f78202=i:o?1<65f15794?"5n?0:8:5a2g795>=n9=>1<7*=f78202=i:o?1>65f15194?"5n?0:8:5a2g797>=n9=81<7*=f78202=i:o?1865f15394?"5n?0:8:5a2g791>=n9=:1<7*=f78202=i:o?1:65f12d94?"5n?0:8:5a2g793>=n9:o1<7*=f78202=i:o?1465f12f94?"5n?0:8:5a2g79=>=n9:i1<7*=f78202=i:o?1m65f12c94?"5n?0:8:5a2g79f>=n9:31<7*=f78202=i:o?1o65f12:94?"5n?0:8:5a2g79`>=n9:=1<7*=f78202=i:o?1i65f12494?"5n?0:8:5a2g79b>=n9:?1<7*=f78202=i:o?1==54i017>5<#:o<1=994n3d6>47<3`;8?7>5$3d5>4203g8m97?=;:k277<72-8m:7?;7:l1b0<6;21b=>?50;&1b3<6<>1e>k;51598m44a290/>k851558j7`228?07d?=e;29 7`128><7c<i5;35?>o6:m0;6)<i6;373>h5n<0:;65f13a94?"5n?0:8:5a2g795==<a88i6=4+2g49511<f;l>6<74;h31e?6=,;l=6<:8;o0e1?7f32c:>44?:%0e2?73?2d9j84>b:9j57>=83.9j;4>469m6c3=9j10e<<8:18'6c0=9==0b?h::0f8?l75>3:1(?h9:064?k4a=3;n76g>4d83>!4a>3;?;6`=f482b>=n9=n1<7*=f78202=i:o?1>=54i06`>5<#:o<1=994n3d6>77<3`;?n7>5$3d5>4203g8m97<=;:k20d<72-8m:7?;7:l1b0<5;21b=9750;&1b3<6<>1e>k;52598m421290/>k851558j7`22;?07d?<b;29 7`128><7c<i5;05?>o6;90;6)<i6;373>h5n<09;65f13794?"5n?0:8:5a2g796==<a:8?6=4+2g49775<f;l>6=54i23b>5<#:o<1?<74n3d6>5=<a=9h6=4+2g4906d<f;l>6=54i51b>5<#:o<18>l4n3d6>4=<a=926=4+2g4906d<f;l>6?54i51;>5<#:o<18>l4n3d6>6=<a=9<6=4+2g4906d<f;l>6954i9194?"5n?03>6`=f483?>o?93:1(?h9:908j7`22810e5>50;&1b3<?:2d9j84=;:k4b?6=,;l=65<4n3d6>6=<a>o1<7*=f78;6>h5n<0?76g8d;29 7`12180b?h::498m2e=83.9j;472:l1b0<132c<n7>5$3d5>=4<f;l>6:54i6c94?"5n?03>6`=f48;?>o6?;0;6)<i6;345>h5n<0;76g>6g83>!4a>3;<=6`=f482?>o6>l0;6)<i6;345>h5n<0976g>6e83>!4a>3;<=6`=f480?>o6>j0;6)<i6;345>h5n<0?76g>6c83>!4a>3;<=6`=f486?>o6>h0;6)<i6;345>h5n<0=76g>6883>!4a>3;<=6`=f484?>o6>10;6)<i6;345>h5n<0376g>6683>!4a>3;<=6`=f48:?>o6>?0;6)<i6;345>h5n<0j76g>6583>!4a>3;<=6`=f48a?>o6>:0;6)<i6;345>h5n<0h76g>6383>!4a>3;<=6`=f48g?>o6>80;6)<i6;345>h5n<0n76g>6183>!4a>3;<=6`=f48e?>o6=o0;6)<i6;345>h5n<0:<65f14g94?"5n?0:;<5a2g7954=<a8?o6=4+2g49527<f;l>6<<4;h36g?6=,;l=6<9>;o0e1?7432c:9o4?:%0e2?7092d9j84>4:9j50?=83.9j;4>709m6c3=9<10e<;7:18'6c0=9>;0b?h::048?l72?3:1(?h9:052?k4a=3;<76g>5783>!4a>3;<=6`=f482<>=n9<?1<7*=f78234=i:o?1=454i077>5<#:o<1=:?4n3d6>4g<3`;>?7>5$3d5>4163g8m97?m;:k217<72-8m:7?81:l1b0<6k21b=8?50;&1b3<6?81e>k;51e98m437290/>k851638j7`228o07d?88;29 7`128=:7c<i5;3e?>o6?>0;6)<i6;345>h5n<09<65f16494?"5n?0:;<5a2g7964=<a8=>6=4+2g49527<f;l>6?<4;h340?6=,;l=6<9>;o0e1?4432c:;>4?:%0e2?7092d9j84=4:9j526=83.9j;4>709m6c3=:<10e<8::18'6c0=9>;0b?h::348?l72i3:1(?h9:052?k4a=38<76g>4g83>!4a>3;<=6`=f481<>=nk10;66g=2d83>>oc83:17d<<2;29?l4cm3:17d<kd;29?j7a<3:1(?h9:0d0?k4a=3:07b?i1;29 7`128l87c<i5;38?j7a83:1(?h9:0d0?k4a=3807b?jf;29 7`128l87c<i5;18?j7bm3:1(?h9:0d0?k4a=3>07b?jd;29 7`128l87c<i5;78?j7bk3:1(?h9:0d0?k4a=3<07b?jb;29 7`128l87c<i5;58?j7bi3:1(?h9:0d0?k4a=3207b?j9;29 7`128l87c<i5;;8?j7b03:1(?h9:0d0?k4a=3k07b?j6;29 7`128l87c<i5;`8?j7b=3:1(?h9:0d0?k4a=3i07b?j4;29 7`128l87c<i5;f8?j7b;3:1(?h9:0d0?k4a=3o07b?j2;29 7`128l87c<i5;d8?j7b93:1(?h9:0d0?k4a=3;;76a>e183>!4a>3;m?6`=f4825>=h9ml1<7*=f782b6=i:o?1=?54o0ff>5<#:o<1=k=4n3d6>45<3f;oh7>5$3d5>4`43g8m97?;;:m2`g<72-8m:7?i3:l1b0<6=21d=io50;&1b3<6n:1e>k;51798k4b>290/>k851g18j7`228=07b?k8;29 7`128l87c<i5;3;?>i6l>0;6)<i6;3e7>h5n<0:565`1e494?"5n?0:j>5a2g795d=<g8n>6=4+2g495c5<f;l>6<l4;n3g0?6=,;l=6<h<;o0e1?7d32e:h>4?:%0e2?7a;2d9j84>d:9l5a4=83.9j;4>f29m6c3=9l10c<hn:18'6c0=9o90b?h::0d8?j7a13:1(?h9:0d0?k4a=38;76a>f983>!4a>3;m?6`=f4815>=h9o=1<7*=f782b6=i:o?1>?54o0d5>5<#:o<1=k=4n3d6>75<3f;m97>5$3d5>4`43g8m97<;;:m2b7<72-8m:7?i3:l1b0<5=21d=h950;&1b3<6n:1e>k;52798k4bd290/>k851g18j7`22;=07b?k1;29 7`128l87c<i5;0;?>i59l0;6)<i6;02`>h5n<0;76a=1c83>!4a>38:h6`=f482?>i59h0;6)<i6;02`>h5n<0976a=1883>!4a>38:h6`=f480?>i5910;6)<i6;02`>h5n<0?76a=1683>!4a>38:h6`=f486?>i59?0;6)<i6;02`>h5n<0=76a=1483>!4a>38:h6`=f484?>i59=0;6)<i6;02`>h5n<0376a=1283>!4a>38:h6`=f48:?>i59;0;6)<i6;02`>h5n<0j76a=1183>!4a>38:h6`=f48a?>i58o0;6)<i6;02`>h5n<0h76a=0d83>!4a>38:h6`=f48g?>i58m0;6)<i6;02`>h5n<0n76a=0b83>!4a>38:h6`=f48e?>i58k0;6)<i6;02`>h5n<0:<65`21c94?"5n?09=i5a2g7954=<g;:26=4+2g4964b<f;l>6<<4;n03<?6=,;l=6??k;o0e1?7432e9<:4?:%0e2?46l2d9j84>4:9l653=83.9j;4=1e9m6c3=9<10c?>;:18'6c0=:8n0b?h::048?j47;3:1(?h9:33g?k4a=3;<76a=0383>!4a>38:h6`=f482<>=h:9;1<7*=f7815a=i:o?1=454o323>5<#:o<1><j4n3d6>4g<3f;mj7>5$3d5>77c3g8m97?m;:m2b`<72-8m:7<>d:l1b0<6k21d=kj50;&1b3<59m1e>k;51e98k4`d290/>k8520f8j7`228o07b<=4;29 7`12;;o7c<i5;3e?>i5::0;6)<i6;02`>h5n<09<65`23094?"5n?09=i5a2g7964=<g;8:6=4+2g4964b<f;l>6?<4;n014?6=,;l=6??k;o0e1?4432e9=k4?:%0e2?46l2d9j84=4:9l64e=83.9j;4=1e9m6c3=:<10c??>:18'6c0=:8n0b?h::348?j47>3:1(?h9:33g?k4a=38<76a>fc83>!4a>38:h6`=f481<>=h;9i1<7*=f7804g=i:o?1<65`31c94?"5n?08<o5a2g795>=h;931<7*=f7804g=i:o?1>65`31:94?"5n?08<o5a2g797>=h;9=1<7*=f7804g=i:o?1865`31494?"5n?08<o5a2g791>=h;9?1<7*=f7804g=i:o?1:65`31694?"5n?08<o5a2g793>=h:ol1<7*=f7804g=i:o?1465`32794?=hm90;66l;5g83>4<729q/?9?54318L13c3A>9>6a=f383>>{e<<o1<7?50;2x 6262;>:7E::d:J767=h:=:1<75rb5fb>5<6=80;6=u+35396cd<@=?o7E:=2:Xa=?71sm0j6k4m:b8f><<4:3;m6?>525811?562::1=54>7;0e>40=9<09>7<<:339y!4a93>o46`>a583?k7d>3:0(?=9:31:?!44?38856*=4886?!43i3?0(?:m:49'61e==2.98i4:;%07a?3<,;>m685+24291>"5=80>7)<:2;78 7342<1/>8:55:&110<23-8>:7;4$374>0=#:<2196*=5`86?!42j3?0(?;l:49'60b==2.99h4:;%06b?3<,;<;685+27391>"5>;0>7)<93;78 7032<1/>;;55:&123<23-8=;7;4$34;>0=#:?3196*=6`86?!41j3?0(?8l:49'63b==2.9:h4:;%05b?3<,;=;685+26391>"5?;0>7)<83;78 7132<1/>:;55:&133<23-8<;7;4$35;>0=#:>3196*=7`86?!40j3?0(?9l:49'62b==2.9;h4:;%04b?3<,;2;685+29391>"50;0>7)<73;78 7>32<1/>5;55:&1<3<23-83;7;4$3:;>0=#:13196*=8`86?!4?j3?0(?6l:49'6=b==2.94h4:;%0;b?3<,;3;685+28391>"51;0>7)<63;78 7?32<1/>4;55:&1=3<23-82;7;4$3;;>0=#:03196*=9`86?!4>j3?0(?7l:49'6<b==2.95h4:;%0:b?3<,;k;685+2`391>"5i;0>7)<n3;78 7g32<1/>l;55:&1e3<23-8j;7;4$3c;>0=#:h3196*=a`86?!4fj3?0(?ol:49'6db==2.9mh4:;%0bb?3<,;h;685+2c391>"5j;0>7)<m3;78 7d32<1/>o;55:&1f3<23-8i;7;4$3`;>0=#:k3196*=b`86?!4ej3?0(?ll:49'6gb==2.9nh4:;%0ab?3<,;i;685+2b391>"5k;0>7)<l3;78 7e32<1/>n;55:&1g3<23-8h;7;4$3a;>0=#:j3196*=c`86?!4dj3?0(?ml:49'6fb==2.9oh4:;%0`b?3<,;n;685+2e391>"5l;0>7)<k3;78 7b32<1/>i;55:&1`3<23-8o;7;4$3f;>0=#:m3196*=d`87?!4cj3>0(?jl:3ge?!4ak38nj6*=fe81ac=#:oo1?>84$22f>`7<f:;;6964n232>5=#;:;1?<<4$211>6753-9857l9;%10e?25=2.8?i4;;%10a?2<,=?36>>i;%66=?57n2d?9l4?;o66f?2?3-9887<<9:kaf?6=3`hh6=44ocf94?=hjl0;66gld;29?leb290C?>l4;hae>5<O;:h07dj=:188ma5=83B8?o54ie694?N4;k10ch>50;9j67`=831b>>>50;J07g=<a;9:6=4G32`8?l44;3:17d<<4;29L65e32c9?84?:I10f>=n:mn1<75f2eg94?=n;8?1<75f30494?N4;k10e>?8:18K76d<3`9:47>5;h12f?6=@:9i76g<1b83>M54j21b?<j50;J07g=<a:;n6=4G32`8?l56n3:1D>=m;:k065<72A98n65f33794?=n;;<1<7F<3c98m640290C?>l4;h11<?6=3`9957>5H21a?>o4:h0;6E=<b:9j77d=831b??m50;J07g=<a:8o6=4G32`8?l55m3:17d==f;29L65e32c8?=4?:I10f>=h;:?1<75f4g83>!4a>3>n7c<i5;28?l2c290/>k854d9m6c3=921b8n4?:%0e2?2b3g8m97<4;h6a>5<#:o<18h5a2g797>=n<h0;6)<i6;6f?k4a=3>07d:6:18'6c0=<l1e>k;55:9j1=<72-8m:7:j;o0e1?0<3`?<6=4+2g490`=i:o?1;65f5783>!4a>3>n7c<i5;:8?l32290/>k854d9m6c3=121b994?:%0e2?2b3g8m97o4;h70>5<#:o<18h5a2g79f>=n=;0;6)<i6;6f?k4a=3i07d;>:18'6c0=<l1e>k;5d:9j15<72-8m:7:j;o0e1?c<3`>36=4+2g490`=i:o?1j65f6183>!4a>3?m7c<i5;28L65e32c>i7>5$3d5>0`<f;l>6<5G32`8?l3c290/>k855g9m6c3=:2B8?o54i4a94?"5n?0>j6`=f480?M54j21b9o4?:%0e2?3a3g8m97:4H21a?>o2i3:1(?h9:4d8j7`22<1C?>l4;h4:>5<#:o<19k5a2g792>N4;k10e;650;&1b3<2n2d9j848;I10f>=n>>0;6)<i6;7e?k4a=320D>=m;:k52?6=,;l=68h4n3d6><=O;:h07d8::18'6c0==o1e>k;5a:J07g=<a?>1<7*=f786b>h5n<0i7E=<b:9j26<72-8m:7;i;o0e1?e<@:9i76g92;29 7`12<l0b?h::e9K76d<3`<:6=4+2g491c=i:o?1i6F<3c98m0?=83.9j;4:f:l1b0<a3A98n65f7183>!4a>3<m7c<i5;28L65e32c=i7>5$3d5>3`<f;l>6<5G32`8?l0c290/>k856g9m6c3=:2B8?o54i7a94?"5n?0=j6`=f480?M54j21b:o4?:%0e2?0a3g8m97:4H21a?>o013:1(?h9:7d8j7`22<1C?>l4;h5;>5<#:o<1:k5a2g792>N4;k10e:950;&1b3<1n2d9j848;I10f>=n??0;6)<i6;4e?k4a=320D>=m;:k41?6=,;l=6;h4n3d6><=O;:h07d9;:18'6c0=>o1e>k;5a:J07g=<a>91<7*=f785b>h5n<0i7E=<b:9j37<72-8m:78i;o0e1?e<@:9i76g81;29 7`12?l0b?h::e9K76d<3`<j6=4+2g492c=i:o?1i6F<3c98m=d=83.9j;47a:l1b0<732c357>5$3d5>=g<f;l>6<54i9:94?"5n?03m6`=f481?>o??3:1(?h9:9c8j7`22:10e5850;&1b3<?i2d9j84;;:k;1?6=,;l=65o4n3d6>0=<a0>1<7*=f78;e>h5n<0=76g63;29 7`121k0b?h::698m<4=83.9j;47a:l1b0<?32c2=7>5$3d5>=g<f;l>6454i8294?"5n?03m6`=f48b?>o?n3:1(?h9:9c8j7`22k10e5k50;&1b3<?i2d9j84l;:k;`?6=,;l=65o4n3d6>a=<a1i1<7*=f78;e>h5n<0n76g74;29 7`121k0b?h::g98m<e=83.9j;46b:l1b0<73A98n65f9`83>!4a>33i7c<i5;38L65e32c257>5$3d5><d<f;l>6?5G32`8?l??290/>k859c9m6c3=;2B8?o54i8594?"5n?02n6`=f487?M54j21b5;4?:%0e2??e3g8m97;4H21a?>of=3:1(?h9:8`8j7`22?1C?>l4;hc7>5<#:o<15o5a2g793>N4;k10el=50;&1b3<>j2d9j847;I10f>=ni;0;6)<i6;;a?k4a=330D>=m;:kb5?6=,;l=64l4n3d6>d=O;:h07do?:18'6c0=1k1e>k;5b:J07g=<a0l1<7*=f78:f>h5n<0h7E=<b:9j=`<72-8m:77m;o0e1?b<@:9i76g6d;29 7`120h0b?h::d9K76d<3`3>6=4+2g49=g=i:o?1j6F<3c98mde=83.9j;4nb:l1b0<73A98n65fa`83>!4a>3ki7c<i5;38L65e32cj57>5$3d5>dd<f;l>6?5G32`8?lg?290/>k85ac9m6c3=;2B8?o54i`594?"5n?0jn6`=f487?M54j21bn84?:%0e2?ge3g8m97;4H21a?>oe<3:1(?h9:``8j7`22?1C?>l4;h`0>5<#:o<1mo5a2g793>N4;k10eo<50;&1b3<fj2d9j847;I10f>=nj80;6)<i6;ca?k4a=330D>=m;:ka4?6=,;l=6ll4n3d6>d=O;:h07doi:18'6c0=ik1e>k;5b:J07g=<aho1<7*=f78bf>h5n<0h7E=<b:9jea<72-8m:7om;o0e1?b<@:9i76gn6;29 7`12hh0b?h::d9K76d<3`lh6=4+2g49bg=i:o?1<65ff`83>!4a>3li7c<i5;38?l`?290/>k85fc9m6c3=:21bj:4?:%0e2?`e3g8m97=4;hd5>5<#:o<1jo5a2g790>=nn<0;6)<i6;da?k4a=3?07dh;:18'6c0=nk1e>k;56:9jb6<72-8m:7hm;o0e1?1<3`l96=4+2g49bg=i:o?1465ff083>!4a>3li7c<i5;;8?l`7290/>k85fc9m6c3=i21bik4?:%0e2?`e3g8m97l4;hgg>5<#:o<1jo5a2g79g>=nmj0;6)<i6;da?k4a=3n07dkm:18'6c0=nk1e>k;5e:9jad<72-8m:7hm;o0e1?`<3`o26=4+2g49bg=i:o?1==54id:94?"5n?0mn6`=f4825>=nm>0;6)<i6;da?k4a=3;976gj6;29 7`12oh0b?h::018?lc2290/>k85fc9m6c3=9=10eh:50;&1b3<aj2d9j84>5:9j555=83.9j;4ib:l1b0<6>21b==<50;&1b3<aj2d9j84>7:9j557=83.9j;4ib:l1b0<6021b==>50;&1b3<aj2d9j84>9:9jbc<72-8m:7hm;o0e1?7f32cmi7>5$3d5>cd<f;l>6<l4;hdg>5<#:o<1jo5a2g795f=<ao31<7*=f78ef>h5n<0:h65fed83>!4a>3li7c<i5;3f?>ob;3:1(?h9:g`8j7`228l07d?>d;29 7`128;h7c<i5;28?l76j3:1(?h9:03`?k4a=3;07d?>9;29 7`128;h7c<i5;08?l7603:1(?h9:03`?k4a=3907d?>7;29 7`128;h7c<i5;68?l76>3:1(?h9:03`?k4a=3?07d?>5;29 7`128;h7c<i5;48?l76<3:1(?h9:03`?k4a=3=07d?>3;29 7`128;h7c<i5;:8?l76:3:1(?h9:03`?k4a=3307d?>1;29 7`128;h7c<i5;c8?l7683:1(?h9:03`?k4a=3h07d??e;29 7`128;h7c<i5;a8?l77l3:1(?h9:03`?k4a=3n07d??c;29 7`128;h7c<i5;g8?l77j3:1(?h9:03`?k4a=3l07d??a;29 7`128;h7c<i5;33?>o6800;6)<i6;32g>h5n<0:=65f11:94?"5n?0:=n5a2g7957=<a8:<6=4+2g4954e<f;l>6<=4;h332?6=,;l=6<?l;o0e1?7332c:<84?:%0e2?76k2d9j84>5:9j572=83.9j;4>1b9m6c3=9?10e<<<:18'6c0=98i0b?h::058?l75:3:1(?h9:03`?k4a=3;376g>2083>!4a>3;:o6`=f482=>=n9;:1<7*=f7825f=i:o?1=l54i03e>5<#:o<1=<m4n3d6>4d<3`;:i7>5$3d5>47d3g8m97?l;:k25d<72-8m:7?>c:l1b0<6l21b==h50;&1b3<69j1e>k;51d98m463290/>k8510a8j7`228l07d?8d;29 7`128=h7c<i5;28?l70j3:1(?h9:05`?k4a=3;07d?8a;29 7`128=h7c<i5;08?l7013:1(?h9:05`?k4a=3907d?72;29 7`1282:7c<i5;28?l7?83:1(?h9:0:2?k4a=3;07d?8f;29 7`1282:7c<i5;08?l70m3:1(?h9:0:2?k4a=3907b?6c;29 7`1283i7c<i5;28?j7>i3:1(?h9:0;a?k4a=3;07b?68;29 7`1283i7c<i5;08?j7>?3:1(?h9:0;a?k4a=3907b?66;29 7`1283i7c<i5;68?j7>=3:1(?h9:0;a?k4a=3?07b?64;29 7`1283i7c<i5;48?j7>;3:1(?h9:0;a?k4a=3=07b?62;29 7`1283i7c<i5;:8?j7>93:1(?h9:0;a?k4a=3307b?60;29 7`1283i7c<i5;c8?j7?n3:1(?h9:0;a?k4a=3h07b?7d;29 7`1283i7c<i5;a8?j7?k3:1(?h9:0;a?k4a=3n07b?7b;29 7`1283i7c<i5;g8?j7?i3:1(?h9:0;a?k4a=3l07b?79;29 7`1283i7c<i5;33?>i6010;6)<i6;3:f>h5n<0:=65`19594?"5n?0:5o5a2g7957=<g82=6=4+2g495<d<f;l>6<=4;n3;1?6=,;l=6<7m;o0e1?7332e:494?:%0e2?7>j2d9j84>5:9l5d5=83.9j;4>9c9m6c3=9?10c<o=:18'6c0=90h0b?h::058?j7f93:1(?h9:0;a?k4a=3;376a>a183>!4a>3;2n6`=f482=>=h90l1<7*=f782=g=i:o?1=l54o0;f>5<#:o<1=4l4n3d6>4d<3f;2h7>5$3d5>4?e3g8m97?l;:m2=<<72-8m:7?6b:l1b0<6l21d=5k50;&1b3<61k1e>k;51d98k4>4290/>k8518`8j7`228l07b?me;29 7`128ho7c<i5;28?j7ek3:1(?h9:0`g?k4a=3;07b?ma;29 7`128ho7c<i5;08?j7e13:1(?h9:0`g?k4a=3907b?m8;29 7`128ho7c<i5;68?j7e?3:1(?h9:0`g?k4a=3?07b?m6;29 7`128ho7c<i5;48?j7e=3:1(?h9:0`g?k4a=3=07b?m4;29 7`128ho7c<i5;:8?j7e;3:1(?h9:0`g?k4a=3307b?m2;29 7`128ho7c<i5;c8?j7e93:1(?h9:0`g?k4a=3h07b?nf;29 7`128ho7c<i5;a8?j7fm3:1(?h9:0`g?k4a=3n07b?nd;29 7`128ho7c<i5;g8?j7fk3:1(?h9:0`g?k4a=3l07b?nb;29 7`128ho7c<i5;33?>i6ih0;6)<i6;3a`>h5n<0:=65`1`;94?"5n?0:ni5a2g7957=<g8k36=4+2g495gb<f;l>6<=4;n3b3?6=,;l=6<lk;o0e1?7332e:m;4?:%0e2?7el2d9j84>5:9l5f3=83.9j;4>be9m6c3=9?10c<m;:18'6c0=9kn0b?h::058?j7d;3:1(?h9:0`g?k4a=3;376a>c383>!4a>3;ih6`=f482=>=h9j;1<7*=f782fa=i:o?1=l54o0a3>5<#:o<1=oj4n3d6>4d<3f;ij7>5$3d5>4dc3g8m97?l;:m2fg<72-8m:7?md:l1b0<6l21d=o>50;&1b3<6jm1e>k;51d98k4g2290/>k851cf8j7`228l07b?lb;29 7`128ij7c<i5;28?j7d13:1(?h9:0ab?k4a=3;07b?l8;29 7`128ij7c<i5;08?j7d?3:1(?h9:0ab?k4a=3907b?k0;29 7`128im7c<i5;28?j7dm3:1(?h9:0ae?k4a=3;07b?ld;29 7`128im7c<i5;08?j7dk3:1(?h9:0ae?k4a=3907b<=d;29 7`12;8h7c<i5;28?j45j3:1(?h9:30`?k4a=3;07b<=a;29 7`12;8h7c<i5;08?j4513:1(?h9:30`?k4a=3907b<=8;29 7`12;8h7c<i5;68?j45?3:1(?h9:30`?k4a=3?07b<=6;29 7`12;8h7c<i5;48?j45=3:1(?h9:30`?k4a=3=07b=?3;29 7`12::97c<i5;28L65e32e8<<4?:%0e2?57:2d9j84>;I10f>=h;9:1<7*=f78047=i:o?1>6F<3c98k66c290/>k853108j7`22:1C?>l4;n13g?6=,;l=6>>=;o0e1?2<3f9;m7>5$3d5>6653g8m97;4;n13=?6=,;l=6>>=;o0e1?0<3f9;47>5$3d5>6653g8m9794;n133?6=,;l=6>>=;o0e1?><3f9;:7>5$3d5>6653g8m9774;n131?6=,;l=6>>=;o0e1?g<3f9;87>5$3d5>6653g8m97l4;n0eb?6=,;l=6>>=;o0e1?e<3`>9m7>5$3d5>14>3g8m97>4;h61<?6=,;l=69<6;o0e1?7<3`>9;7>5$3d5>14>3g8m97<4;h612?6=,;l=69<6;o0e1?5<3`>8=7>5$3d5>1573g8m97>4H21a?>o3:o0;6)<i6;604>h5n<0:7E=<b:9j07c=83.9j;4;319m6c3=:2B8?o54i50g>5<#:o<18>>4n3d6>6=O;:h07d:<6;29 7`12=9>7c<i5;28L65e32c??94?:%0e2?24=2d9j84>;I10f>=n<:91<7*=f78770=i:o?1>6F<3c98m155290/>k854278j7`22:1C?>l4;h671?6=,;l=69:;;o0e1?6<3`>??7>5$3d5>1233g8m97?4;h676?6=,;l=69:;;o0e1?4<3`>?=7>5$3d5>1233g8m97=4;h674?6=,;l=69:;;o0e1?2<3`>8j7>5$3d5>1233g8m97;4;h60a?6=,;l=69:;;o0e1?0<3`>8h7>5$3d5>1233g8m9794;h67a?6=,;l=69:k;o0e1?6<@:9i76g;4b83>!4a>3>?h6`=f482?M54j21b89l50;&1b3<3<m1e>k;52:J07g=<a=>j6=4+2g4901b<f;l>6>5G32`8?l2313:1(?h9:56g?k4a=3>0D>=m;:k70=<72-8m:7:;d:l1b0<23A98n65f45594?"5n?0?8i5a2g792>N4;k10e9:9:18'6c0=<=n0b?h::69K76d<3`>>;7>5$3d5>1313g8m97>4H21a?>o3=<0;6)<i6;662>h5n<0:7E=<b:9j002=83.9j;4;579m6c3=:2B8?o54i570>5<#:o<18884n3d6>6=O;:h07d::2;29 7`12=?=7c<i5;68L65e32c?9<4?:%0e2?22>2d9j84:;I10f>=n<<:1<7*=f78713=i:o?1:6F<3c98m12a290/>k854448j7`22>1C?>l4;|q763<720qU8?84=5fb>12234>om7:;3:?7`d<3<;168io5453891bf2=>;70:ka;60b>;3lh0??h524ec906b<uz><6=4={_64?82ci3227p};5;296~X3=27?hl478:p01<72;qU89524ec9<2=z{=91<7<t^51891bf21<0q~:=:181[2534>om76:;|q75?6=:rT?=63;d`8:0>{t<90;6?uQ419>0ag=1:1v>h50;0xZ6`<5=nj64<4}r1f>5<5sW9n70:ka;;2?xu6<10;6?uQ15:891bf28;37p}>4483>7}Y9=?019jn:034?xu6<=0;6?uQ156891bf28;=7p}>4283>7}Y9=9019jn:036?xu6<;0;6?uQ150891bf28;?7p}>4083>7}Y9=;019jn:033?xu6<90;6?uQ152891bf28:n7p}>3g83>7}Y9:l019jn:02g?xu6;l0;6?uQ12g891bf28:h7p}>3e83>7}Y9:n019jn:02a?xu6;j0;6?uQ12a891bf28:<7p}>3`83>7}Y9:k019jn:025?xu6;00;6?uQ12;891bf28:>7p}>3983>7}Y9:2019jn:007?xu6;>0;6?uQ125891bf28887p}>3783>7}Y9:<019jn:03e?xu6;<0;6?uQ127891bf28;n7p}>3583>7}Y9:>019jn:03b?xu6;:0;6?uQ121891bf28:m7p}>3383>7}Y9:8019jn:027?xu6;80;6?uQ123891bf2o=0q~?=f;296~X6:o168io5f79~w44b2909wS?=e:?7`d<a=2wx=?j50;0xZ44c34>om7h;;|q26f<72;qU=?m4=5fb>c5<uz;9n7>52z\26g=:<mk1ik5rs00b>5<5sW;9m63;d`8f`>{t9;31<7<t^00:?82ci3oh7p}>2983>7}Y9;2019jn:d`8yv75?3:1>vP>269>0ag=mh1v<<9:181[75>27?hl4j6:p51c=838pR<:j;<6ge?c23ty:8i4?:3y]51b<5=nj6h:4}r37g?6=:rT:8n524ec9555<uz;?n7>52z\20g=:<mk1==<4}r37e?6=:rT:8l524ec9bc=z{8>26=4={_37=>;3lh0mi6s|15494?4|V8>=70:ka;dg?xu6;k0;6?uQ12`891bf2o30q~?<0;296~X6;9168io5ed9~w4422909wS?=5:?7`d<b;2wx??:50;0xZ64334>om7==5:p<6<72;qU4>524ec90a=z{1;1<7<t^93891bf2=i0q~6?:181[>734>om7:m;|q4b?6=:rT<j63;d`87e>{t?l0;6?uQ7d9>0ag=<01v:j50;0xZ2b<5=nj6864}r5`>5<5sW=h70:ka;74?xu0j3:1>vP8b:?7`d<2>2wx;l4?:3y]3d=:<mk1985rsb:94?4|Vj2019jn:e08yv45m3:1>vP=2d9>0ag=::90q~j?:181[b734>om7mk;|q177<72;qU>><4=5fb>74a3ty9=h4?:3y]64c<5=nj6<l6;|q15g<72;qU><l4=5fb>4d?3ty9=l4?:3y]64g<5=nj6<l8;|q15<<72;qU><74=5fb>4d13ty9=54?:3y]64><5=nj6<l:;|q152<72;qU><94=5fb>4d63ty9=;4?:3y]640<5=nj6<oi;|q150<72;qU><;4=5fb>4gb3ty9=94?:3y]642<5=nj6<ok;|q156<72;qU><=4=5fb>4gd3ty9=?4?:3y]644<5=nj6<o7;|q155<72;qU><>4=5fb>4g03ty9<k4?:3y]65`<5=nj6<o9;|q14`<72;qU>=k4=5fb>4e23ty9<i4?:3y]65b<5=nj6<m;;|q14f<72;qU>=m4=5fb>4e73ty9<o4?:3y]65d<5=nj6<li;|q14d<72;qU>=o4=5fb>4de3ty9<44?:3y]65?<5=nj6<l?;|q14=<72;qU>=64=5fb>4g23ty9<:4?:3y]651<5=nj6<78;|q140<72;qU>=;4=5fb>4?13ty9<94?:3y]652<5=nj6<7:;|q146<72;qU>==4=5fb>4?33ty9<?4?:3y]654<5=nj6<7<;|q144<72;qU>=?4=5fb>4>a3ty9<=4?:3y]656<5=nj6<6k;|q2bc<72;qU=kh4=5fb>4>d3ty:jh4?:3y]5cc<5=nj6<6m;|q2ba<72;qU=kj4=5fb>4>f3ty:jn4?:3y]5ce<5=nj6<69;|q161<72;qU>?:4=5fb>4>23ty9>>4?:3y]675<5=nj6<6;;|q167<72;qU>?<4=5fb>4g43ty9><4?:3y]677<5=nj6<o=;|q165<72;qU>?>4=5fb>4?a3ty9=k4?:3y]64`<5=nj6<7j;|q15f<72;qU><m4=5fb>4?c3ty9=<4?:3y]647<5=nj6<76;|q143<72;qU>=84=5fb>4>b3ty:jo4?:3y]5cd<5=nj6<6<;|q1af<72:q688h52g0891bf2=l019jn:9`8yvc7290=hv3;5d8105=Ym91U?>;4^22`?[57i2T8<45Q31:8Z6603W9;:6P<049]752<V;lm70:ka;0g`>;3lh09hh524ec9743<5=nj6<>?;<6ge?77927?hl4>789>0ag=m>168io5e99>0ag=m0168io516c891bf2o:019jn:g3891bf2o8019jn:05a?82ci3l370:ka;db?82ci3lh70:ka;34`>;3lh0:>=524ec9577<5=nj6<<=;<6ge?70m27?hl4>099>0ag=993019jn:02b?82ci3;<j63;d`8254=:<mk1=<<4=5fb>47434>om7?70:?7`d<690168io510`891bf28;o70:ka;3;6>;3lh0>863;d`867>;3lh0>>63;d`865>;3lh0><63;d`87<>;3lh02<63;d`8;b>;3lh03i63;d`8;`>;3lh03o63;d`8;0>;3lh0?>l524ec907><5=nj69<8;<6ge?25>27?hl4mb:?7`d<ek27?hl4<199>0ag=;;2019jn:20a?82ci399i6P>d09]5ae<V8o<7S?i2:\2b0=Y9o<0R<h8;_3e<>X6n01U=ko4^0f1?[7c;2T:h95Q1e78Z4b13W;o;6P>d99]5a?<V8nj7S?kb:\2`a=Y9mo0R<ji;_3f4>X6m81U=h<4^0g0?[7b<2T:i85Q1d48Z4c?3W;n56P>e`9]5`d<V8oh7S?jd:\2a`=Y9ll0R<h?;_3e5>X6n=1vqo=nb;290?6=8r.88<4=e89K00b<@=897)<i1;6g<>od93:17dk=:188m6542900c?h?:188yg5fi3:187>50z&004<5m01C88j4H501?!4a93>o46gl1;29?lc52900e>=<:188k7`72900qo=n9;290?6=8r.88<4=e89K00b<@=897)<i1;6g<>od93:17dk=:188m6542900c?h?:188yg5f03:187>50z&004<5m01C88j4H501?!4a93>o46gl1;29?lc52900e>=<:188k7`72900qo=nc;290?6=8r.88<4=e89K00b<@=897)<i1;6g<>od93:17dk=:188m6542900c?h?:188yg5em3:187>50z&004<5m01C88j4H501?!4a93>o46gl1;29?lc52900e>=<:188k7`72900qo=md;290?6=8r.88<4=e89K00b<@=897)<i1;6g<>od93:17dk=:188m6542900c?h?:188yg5ek3:187>50z&004<5m01C88j4H501?!4a93>o46gl1;29?lc52900e>=<:188k7`72900qo=mb;290?6=8r.88<4=e89K00b<@=897)<i1;6g<>od93:17dk=:188m6542900c?h?:188yg5en3:187>50z&004<5m01C88j4H501?!4a93>o46gl1;29?lc52900e>=<:188k7`72900qo=;9;290?6=8r.88<4=e89K00b<@=897)<i1;6g<>od93:17dk=:188m6542900c?h?:188yg5303:187>50z&004<5m01C88j4H501?!4a93>o46gl1;29?lc52900e>=<:188k7`72900qo=;7;290?6=8r.88<4=e89K00b<@=897)<i1;6g<>od93:17dk=:188m6542900c?h?:188yg53>3:187>50z&004<5m01C88j4H501?!4a93>o46gl1;29?lc52900e>=<:188k7`72900qo=;a;290?6=8r.88<4=e89K00b<@=897)<i1;6g<>od93:17dk=:188m6542900c?h?:188yg52k3:187>50z&004<5m01C88j4H501?!4a93>o46gl1;29?lc52900e>=<:188k7`72900qo=:b;290?6=8r.88<4=e89K00b<@=897)<i1;6g<>od93:17dk=:188m6542900c?h?:188yg52i3:187>50z&004<5m01C88j4H501?!4a93>o46gl1;29?lc52900e>=<:188k7`72900qo=:9;290?6=8r.88<4=e89K00b<@=897)<i1;6g<>od93:17dk=:188m6542900c?h?:188yg52l3:187>50z&004<5m01C88j4H501?!4a93>o46gl1;29?lc52900e>=<:188k7`72900qo=n3;291?6=8r.88<4=3b9K00b<@=897)<:9;18mgg=831bnk4?::kgf?6=3`nm6=44o3db>5<<uk9j>7>55;294~"4<809?n5G44f8L1453-8>57=4icc94?=njo0;66gkb;29?lba2900c?hn:188yg5f93:197>50z&004<5;j1C88j4H501?!421390eoo50;9jfc<722con7>5;hfe>5<<g;lj6=44}c1b4?6==3:1<v*<40817f=O<<n0D9<=;%06=?5<akk1<75fbg83>>ocj3:17dji:188k7`f2900qo=6f;291?6=8r.88<4=3b9K00b<@=897)<:9;18mgg=831bnk4?::kgf?6=3`nm6=44o3db>5<<uk92i7>55;294~"4<809?n5G44f8L1453-8>57=4icc94?=njo0;66gkb;29?lba2900c?hn:188yg5>l3:197>50z&004<5;j1C88j4H501?!421390eoo50;9jfc<722con7>5;hfe>5<<g;lj6=44}c1:g?6==3:1<v*<40817f=O<<n0D9<=;%06=?5<akk1<75fbg83>>ocj3:17dji:188k7`f2900qo=63;291?6=8r.88<4=3b9K00b<@=897)<:9;18mgg=831bnk4?::kgf?6=3`nm6=44o3db>5<<uk92>7>55;294~"4<809?n5G44f8L1453-8>57=4icc94?=njo0;66gkb;29?lba2900c?hn:188yg5>93:197>50z&004<5;j1C88j4H501?!421390eoo50;9jfc<722con7>5;hfe>5<<g;lj6=44}c1:4?6==3:1<v*<40817f=O<<n0D9<=;%06=?5<akk1<75fbg83>>ocj3:17dji:188k7`f2900qo=7f;291?6=8r.88<4=3b9K00b<@=897)<:9;18mgg=831bnk4?::kgf?6=3`nm6=44o3db>5<<uk93i7>55;294~"4<809?n5G44f8L1453-8>57=4icc94?=njo0;66gkb;29?lba2900c?hn:188yg5?l3:197>50z&004<5;j1C88j4H501?!421390eoo50;9jfc<722con7>5;hfe>5<<g;lj6=44}c1;g?6==3:1<v*<40817f=O<<n0D9<=;%06=?5<akk1<75fbg83>>ocj3:17dji:188k7`f2900qo=7b;291?6=8r.88<4=3d9K00b<@=897)<:9;:8mgg=831bnk4?::kgb?6=3`8m47>5;n0ee?6=3th?<?4?:483>5}#;=;1>>m4H57g?M25:2.9944<;h`b>5<<akl1<75fdc83>>ocn3:17b<ia;29?xd3880;684?:1y'717=::i0D9;k;I616>"5=0087dln:188mg`=831bho4?::kgb?6=3f8mm7>5;|`745<72<0;6=u+353966e<@=?o7E:=2:&11<<43`hj6=44icd94?=nlk0;66gkf;29?j4ai3:17pl<fg83>0<729q/?9?522a8L13c3A>9>6*=5880?ldf2900eoh50;9j`g<722coj7>5;n0ee?6=3th8jh4?:483>5}#;=;1>>m4H57g?M25:2.9944<;h`b>5<<akl1<75fdc83>>ocn3:17b<ia;29?xd4nm0;684?:1y'717=::i0D9;k;I616>"5=0087dln:188mg`=831bho4?::kgb?6=3f8mm7>5;|`0bf<72<0;6=u+353966e<@=?o7E:=2:&11<<43`hj6=44icd94?=nlk0;66gkf;29?j4ai3:17pl<fc83>0<729q/?9?522a8L13c3A>9>6*=5880?ldf2900eoh50;9j`g<722coj7>5;n0ee?6=3th8jl4?:483>5}#;=;1>>m4H57g?M25:2.9944<;h`b>5<<akl1<75fdc83>>ocn3:17b<ia;29?xd4n90;684?:1y'717=::i0D9;k;I616>"5=0087dln:188mg`=831bho4?::kgb?6=3f8mm7>5;|`0ac<72<0;6=u+353966e<@=?o7E:=2:&11<<43`hj6=44icd94?=nlk0;66gkf;29?j4ai3:17pl<ed83>0<729q/?9?522a8L13c3A>9>6*=5880?ldf2900eoh50;9j`g<722coj7>5;n0ee?6=3th8ii4?:483>5}#;=;1>>m4H57g?M25:2.9944<;h`b>5<<akl1<75fdc83>>ocn3:17b<ia;29?xd4mj0;684?:1y'717=::i0D9;k;I616>"5=0087dln:188mg`=831bho4?::kgb?6=3f8mm7>5;|`0ag<72<0;6=u+353966e<@=?o7E:=2:&11<<43`hj6=44icd94?=nlk0;66gkf;29?j4ai3:17pl<e`83>0<729q/?9?522a8L13c3A>9>6*=5880?ldf2900eoh50;9j`g<722coj7>5;n0ee?6=3th8i44?:483>5}#;=;1>>m4H57g?M25:2.9944<;h`b>5<<akl1<75fdc83>>ocn3:17b<ia;29?xd4>l0;6>4?:1y'717=:l90D9;k;I616>"5=00:86*=f6872a=n:=91<75f25694?=h:o:1<75rb2ae>5<4290;w)=;1;0f7>N3=m1C8?<4$37:>42<a;>86=44i367>5<<g;l;6=44}c632?6=<3:1<v*<4081a1=O<<n0D9<=;%06=?da3-8m;7:9d:k106<722c9894?::k100<722e9j=4?::a73d=83=1<7>t$262>7c03A>>h6F;239'60?=::20e?:<:188m7232900e?:::188m7212900e?:8:188m72?2900c?h?:188yg2713:1?7>50z&004<5m:1C88j4H501?!4213;?7)<i7;65b>o5<:0;66g=4583>>i5n90;66sm41c94?5=83:p(>:>:3g0?M22l2B?>?5+24;951=#:o=18;k4i360>5<<a;>?6=44o3d3>5<<uk>:m7>53;294~"4<809i>5G44f8L1453-8>57?;;%0e3?21n2c98>4?::k101<722e9j=4?::a076=8391<7>t$262>7c43A>>h6F;239'60?=9=1/>k9547g8m7242900e?:;:188k7`72900qo=m4;291?6=8r.88<4=e49K00b<@=897)<:9;17?l43;3:17d<;4;29?l43=3:17d<;6;29?j4a83:17pl<b383>0<729q/?9?52d78L13c3A>9>6*=58800>o5<:0;66g=4583>>o5<<0;66g=4783>>i5n90;66sm3c294?3=83:p(>:>:3g6?M22l2B?>?5+24;971=n:=91<75f25694?=n:=?1<75f25494?=h:o:1<75rb2`5>5<4290;w)=;1;0f7>N3=m1C8?<4$37:>65<a;>86=44i367>5<<g;l;6=44}c1`3?6==3:1<v*<4081a0=O<<n0D9<=;%06=?533`8??7>5;h070?6=3`8?97>5;h072?6=3f8m<7>5;|`0g0<72<0;6=u+35396`3<@=?o7E:=2:&11<<4<2c98>4?::k101<722c9884?::k103<722e9j=4?::a7f5=83?1<7>t$262>7c23A>>h6F;239'60?=;=1b>9=50;9j612=831b>9;50;9j610=831d>k>50;9~f6e>29086=4?{%175?4b;2B?9i5G4308 73>2:90e?:<:188m7232900c?h?:188yg52:3:197>50z&004<5m<1C88j4H501?!42139?7d<;3;29?l43<3:17d<;5;29?l43>3:17b<i0;29?xd4=90;684?:1y'717=:l?0D9;k;I616>"5=00886g=4283>>o5<=0;66g=4483>>o5<?0;66a=f183>>{e;=o1<7;50;2x 6262;o>7E::d:J767=#:<31?95f25194?=n:=>1<75f25794?=n:=<1<75`2g294?=zj:??6=4<:183!53938n?6F;5e9K074<,;?26>=4i360>5<<a;>?6=44o3d3>5<<uk9=97>55;294~"4<809i85G44f8L1453-8>57=;;h077?6=3`8?87>5;h071?6=3`8?:7>5;n0e4?6=3th8:>4?:483>5}#;=;1>h;4H57g?M25:2.9944<4:k106<722c9894?::k100<722c98;4?::m1b5<722wi?;?50;794?6|,:>:6?k:;I66`>N3:;1/>875359j615=831b>9:50;9j613=831b>9850;9l6c6=831vn>;i:186>5<7s-9?=7<j5:J71a=O<;80(?;6:268m7242900e?:;:188m7222900e?:9:188k7`72900qo=97;297?6=8r.88<4=e29K00b<@=897)<:9;10?l43;3:17d<;4;29?j4a83:17pl<7583>3<729q/?9?52d48L13c3A>9>6*=5881f>"5n>0?:55f25194?=n:=>1<75f25794?=n:=<1<75f25594?=h:o:1<75rb256>5<0290;w)=;1;0f3>N3=m1C8?<4$37:>7e<a;>86=44i367>5<<a;>>6=44i365>5<<a;><6=44i36;>5<<g;l;6=44}c143?6=?3:1<v*<4081a2=O<<n0D9<=;%06=?4b3`8??7>5;h070?6=3`8?97>5;h072?6=3`8?;7>5;h07<?6=3f8m<7>5;|`036<72<0;6=u+35396`3<@=?o7E:=2:&11<<5i2.9j:4;699j615=831b>9:50;9j613=831b>9850;9l6c6=831vn>99:180>5<7s-9?=7<j3:J71a=O<;80(?;6:218m7242900e?:;:188k7`72900qo=82;290?6=8r.88<4=e59K00b<@=897)<:9;0:?!4a?3>=o6g=4283>>o5<=0;66g=4483>>i5n90;66sm36:94?2=83:p(>:>:3g7?M22l2B?>?5+24;97d=#:o=18;o4i360>5<<a;>?6=44i366>5<<g;l;6=44}c14=?6==3:1<v*<4081a0=O<<n0D9<=;%06=?5e3-8m;7:9a:k106<722c9894?::k100<722c98;4?::m1b5<722wi?:?50;194?6|,:>:6?k<;I66`>N3:;1/>875299'6c1=<?i0e?:<:188m7232900c?h?:188yg5c=3:1?7>50z&004<5m:1C88j4H501?!4213987d<;3;29?l43<3:17b<i0;29?xd4l>0;694?:1y'717=:l>0D9;k;I616>"5=008m6*=f6872<=n:=91<75f25694?=n:=?1<75`2g294?=zj:n36=4::183!53938n96F;5e9K074<,;?26>l4$3d4>10>3`8??7>5;h070?6=3`8?97>5;h072?6=3f8m<7>5;|`0gf<72>0;6=u+35396`1<@=?o7E:=2:&11<<13`8??7>5;h070?6=3`8?97>5;h072?6=3`8?;7>5;h07<?6=3f8m<7>5;|`0e`<72<0;6=u+35396`3<@=?o7E:=2:&11<<03`8??7>5;h070?6=3`8?97>5;h072?6=3f8m<7>5;|`0g4<72<0;6=u+35396`3<@=?o7E:=2:&11<<4<2c98>4?::k101<722c9884?::k103<722e9j=4?::a71e=83?1<7>t$262>7c23A>>h6F;239'60?=?2c98>4?::k101<722c9884?::k103<722e9j=4?::a7a0=83=1<7>t$262>7c03A>>h6F;239'60?=::l0e?:<:188m7232900e?:::188m7212900e?:8:188m72?2900c?h?:188yg5c;3:1:7>50z&004<5m?1C88j4H501?!42139h7)<i7;653>o5<:0;66g=4583>>o5<<0;66g=4783>>o5<>0;66a=f183>>{e;m>1<7950;2x 6262;o<7E::d:J767=#:<31?i5f25194?=n:=>1<75f25794?=n:=<1<75f25594?=n:=21<75`2g294?=zj:n96=4::183!53938n96F;5e9K074<,;?26>74$3d4>1003`8??7>5;h070?6=3`8?97>5;h072?6=3f8m<7>5;|`0`4<72=0;6=u+35396`2<@=?o7E:=2:&11<<402.9j:4;6c9j615=831b>9:50;9j613=831d>k>50;9~f6b729086=4?{%175?4b;2B?9i5G4308 73>2:90(?h8:54a?l43;3:17d<;4;29?j4a83:17pl<7183>7<729q/?9?52ed8L13c3A>9>6g=4383>>i5n90;66sm43394?4=83:p(>:>:3fe?M22l2B?>?5f25094?=h:o:1<75rs5g3>5<0sW>n<63;0b81b==:<9n1>k64=52f>7`?34>:n7<i8:?750<5n1168=l5dc9~w7cd290<w0::f;0e6>;38=08=952416974g<5:k36n?4=2`a>f7<5:>=6n?4=27:>f7<uz8nh7>54`y>00c=:=:019>l:ed891732ml019?>:ed891752ml019>;:201?827<3>8o63;05877d=:<9>18>74=527>15?34>;87:<7:?741<6?;168=:517d8916328<n70:?4;35`>;38=0::n52416953d<5=:?6<8n;<630?71127?<94>699>052=9?=019>;:045?827<3;=863;058226=:<9>1=;<4=527>40634>;87?90:?741<6=o168=:514g8916328?o70:?4;36g>;38=0:9o52416950?<5=:?6<;7;<630?72?27?<94>579>052=9<?019>;:077?827<3;>?63;058217=:<9>1=8?4=527>43734>;87?88:?741<6?>168=:51648916328=>70:?4;340>;38=0:;>524169526<5=:?6<8:;<630?72i27?<94>4g9>052=:mo019>;:3fg?85fk3o970=n8;g1?85f13o970=na;g1?85fj3o970=mf;g1?85ej3o970=mc;g1?85el3o970=me;g1?853i3o970=;6;g1?853?3o970=;8;g1?85313o970=:d;g1?85213o970=:a;g1?852j3o970=:c;g1?xu4kl0;6?uQ4e6896eb2;lj7p};0683>45|5:2i6oh4=2:`>g`<5:2o6oh4=2:f>g`<5:2m6oh4=2;3>g`<5:3:6oh4=2;1>g`<5:386oh4=2;`>g`<5:3o6oh4=2;f>g`<5:3m6oh4=2c3>g`<5:k:6oh4=2c1>g`<5:k86oh4=24f>7`7349ho7<;6:p73e=83>p1>8l:3db?851m38?863;078100=:;?h1>984}r15`?6=:rT?oh5237f96cg<uz>j87>52z\7e1=:<9>1=kl4}r6bb?6=:rT?mk524169650<uz>im7>52z\7fd=:<9>1><?4}r6`1?6=:rT?o852416964e<uz>h47>52z\7g==:<9>1><h4}r6`=?6=:rT?o4524169676<uz>hm7>52z\7gd=:<9>1>??4}r6`f?6=:rT?oo524169674<uz>ho7>52z\7gf=:<9>1>?=4}r6``?6=:rT?oi524169672<uz>j97>52z\7e0=:<9>1=km4}r6b2?6=:rT?m;5241695cb<uz>j;7>52z\7e2=:<9>1=kk4}r6b<?6=:rT?m55241695c`<uz>j57>52z\7e<=:<9>1>=>4}r6be?6=:rT?ml524169657<uz>jn7>52z\7eg=:<9>1>=<4}r6bg?6=:rT?mn524169655<uz>jh7>52z\7ea=:<9>1>=:4}r6ba?6=:rT?mh524169653<uz>i<7>52z\7f5=:<9>1>=94}r6a5?6=:rT?n<52416965><uz>i>7>52z\7f7=:<9>1>=74}r6a7?6=:rT?n>52416965g<uz>i87>52z\7f1=:<9>1>=l4}r6a1?6=:rT?n852416965e<uz>i:7>52z\7f3=:<9>1>=j4}r6a3?6=:rT?n:52416965c<uz>i47>52z\7f==:<9>1>=h4}r6a=?6=:rT?n4524169646<uz>in7>52z\7fg=:<9>1><<4}r6ag?6=:rT?nn524169645<uz>ih7>52z\7fa=:<9>1><:4}r6aa?6=:rT?nh524169643<uz>ij7>52z\7fc=:<9>1><84}r6`4?6=:rT?o=524169641<uz>h=7>52z\7g4=:<9>1><64}r6`6?6=:rT?o?52416964?<uz>h?7>52z\7g6=:<9>1><o4}r6`0?6=:rT?o952416964d<uz>h;7>52z\7g2=:<9>1><k4}r63`?6=<r78oi4=f99>7fc=:o2019>j:ed8916c2;lj7p};0c83>7}:<9h1>ko4=2a`>7233ty?==4?:06x960d2;l370=9d;0e<>;39;09jl5239`96c><5:2h6il4=2:g>ad<5:2n6il4=2:e>ad<5:3;6il4=2;2>ad<5:396il4=2;0>ad<5:3h6il4=2;g>ad<5:3n6il4=2;e>ad<5:k;6il4=2c2>ad<5:k96il4=2c0>ad<uz>:?7>513y>042=:ok01>k6:e`896cf2mh01>km:e`896cd2mh01>kk:e`896cb2mh01>ki:e`896`72mh01>hn:e`896`e2mh01>hl:e`896`c2mh01>hj:e`896`a2mh019>?:e`891662mh019>=:e`8yv2b=3:18vP;e49>7f`=:=901>8m:360?85dk38??6s|4ea94?2|V=nh70=9e;077>;38?098>5237`9612<uz>;97>52z?741<5;;168=852g28yv2703:1=5u2416907e<5=:?69<n;<630?25027?<94;269>052=<;<019>;:30f?85b13hm70=ja;`e?85bj3hm70=jc;`e?85bl3hm70=je;`e?85bn3hm70=i0;`e?85ai3hm70=ib;`e?85ak3hm70=id;`e?85am3hm70=if;`e?82783hm70:?1;`e?827:3hm70=lf;0e4>{t<>=1<7=9{_643>;4>j0im63<6e8ae>;4km0im63<cd8ae>;38j0im63;1e8ae>;39=0im63;0e8ae>;39l0im63;0d8ae>;39k0im63;0c8ae>;39>0im63;108ae>;39;0im63;198ae>;39<0im63;058`<>;38=0o<63<8c8ae>;40j0im63<8e8ae>;40l0im63<8g8ae>;4190im63<908ae>;41;0im63<928ae>;41j0im63<9e8ae>;41l0im63<9g8ae>;4i90im63<a08ae>;4i;0im63<a28ae>;4m00im63<e`8ae>;4mk0im63<eb8ae>;4mm0im63<ed8ae>;4mo0im63<f18ae>;4nh0im63<fc8ae>;4nj0im63<fe8ae>;4nl0im63<fg8ae>;3890im63;008ae>;38;0im6s|38694?3|5=:?6:l4=2;`>7`f349ji7<;3:?00f<5<:16?n?52518yv5>=3:19v3;0584g>;41m09jl523c29613<5:i86?::;<17a?43=2wx?4850;7x91632>n01>7j:3db?85e838??63<c28106=:;=o1>9=4}r1:3?6==r7?<948e:?0=c<5nh16?o<5257896e22;>>70=:0;071>{t;021<7;t=527>2`<5:k;6?hn;<1a6?43;278o84=429>706=:=90q~=69;291~;38=03<63<a081bd=:;k>1>9;4=2a4>722349>>7<;5:p7<g=83?p19>;:93896g52;lj70=m4;077>;4k>098>523409615<uz92n7>55z?741<?;278m>4=f`9>7g0=:=901>m6:360?852<38??6s|41d94?5|5=;:6?hn;<630?55<27?<;4=459~w11f2909wS:8a:?741<6:<1v96::181[2?=27?<94>319~w1?72909wS:60:?741<6;k1v97m:181[2>j27?<94>479~w1?b2909wS:6e:?741<6<01v97i:181[2>n27?<94>4`9~w1g72909wS:n0:?741<6<k1v9o>:181[2f927?<94>4b9~w1g52909wS:n2:?741<6<m1v9o<:181[2f;27?<94>4d9~w11e2909wS:8b:?741<6:?1v99l:181[20k27?<94>269~w11c2909wS:8d:?741<6:11v99j:181[20m27?<94>289~w11a2909wS:8f:?741<6:h1v96?:181[2?827?<94>2c9~w1>62909wS:71:?741<6:j1v96=:181[2?:27?<94>2e9~w1>42909wS:73:?741<6:l1v96;:181[2?<27?<94>2g9~w1>12909wS:76:?741<6;81v968:181[2??27?<94>339~w1>?2909wS:78:?741<6;:1v966:181[2?127?<94>359~w1>f2909wS:7a:?741<6;<1v96m:181[2?j27?<94>379~w1>d2909wS:7c:?741<6;>1v96k:181[2?l27?<94>399~w1>b2909wS:7e:?741<6;01v96i:181[2?n27?<94>3`9~w1?62909wS:61:?741<6;j1v97=:181[2>:27?<94>3e9~w1?42909wS:63:?741<6;l1v97;:181[2><27?<94>3g9~w1?22909wS:65:?741<6<91v979:181[2>>27?<94>409~w1?02909wS:67:?741<6<;1v977:181[2>027?<94>429~w1?>2909wS:69:?741<6<=1v97n:181[2>i27?<94>449~w1?c2909wS:6d:?741<6<11v>h>:18g827<39n70=ia;0ee>;4=o098;523`g9610<5:>h6?:9;<1g7?43?278h94=499>7a4=:=>01>j>:367?85c838?863;208107=:;j;1>984=2f5>72?3ty8j?4?:4y>052=;o16?kl52gc8963a2;>?70=ne;070>;4<j09895rs2d0>5<2s4>;87:?;<1eg?4ai278n=4=479>71c=:=<01>8>:365?xu4n=0;68u2416904=:;on1>ko4=2`3>723349?i7<;4:?024<5<=1v>h::186827<3>970=ie;0ee>;4j;098;523429610<5:<86?:9;|q0b3<72<q68=:5429>7c`=:ok01>l=:367?852838?863<628101=z{:l<6=4:{<630?2334>;<7<ia:?0f1<5<?16?8<5254896022;>=7p}<f983>0}:<9>1885241396cg<5:h?6?:;;<166?43<278:84=459~w6`>290>w0:?4;64?827:38mm63<b78101=:;<>1>9:4=244>7233ty8;l4?:by>7=d=:ok01>;i:366?850<38?863<748101=:;>=1>9;4=250>723349<>7<;4:?034<5<=16?lk52578962d2;>>70=80;076>;4k809885rs25a>5<>s493o7<ia:?0=f<cn2789k4=429>722=:=?01>9::366?850?38?:63<728100=:;>81>9;4=252>7243ty8;n4?:9y>7=b=:ok01>7k:ed896062;>>70=84;072>;4?<098;523659612<5:=86?:9;<146?43;2wx?:j50;5x96>b2;lj70=6e;fe?851938??63<758102=:;>?1>994=254>720349<?7<;3:p72c=83<p1>6i:3db?85>n3nm70=93;071>;4?=098>52367961><5:=<6?:7;|q03c<72<q6?4>52gc896g72ml01>8<:360?850=38??63<768106=z{:2;6=49{<1:5?4ai278m<4kf:?020<5<<16?:852518961>2;>>70=88;070>{t;1;1<7;t=2;1>7`f349j>7ji;<151?43;278;54=429>72?=:=>0q~=72;290~;41:09jl523`19`c=:;?=1>9=4=25:>7243ty?<>4?:3y>7cg=lo168??52g28yv5c13:15v3<e881bd=:;oh1hk523e19613<5:n?6?::;<1g6?43=278h<4=449>7a6=:=901>m>:367?85c>38?;6s|3ec94?>|5:oj6?hn;<1eg?ba349h?7<;6:?0`6<5<?16?i:5254896b52;>=70=k1;077>;4l?098;5rs2fa>5<0s49nn7<ia:?0ba<cn278o>4=459>7a5=:=>01>j;:364?85c:38??63<d78100=z{:nh6=49{<1fg?4ai278jh4kf:?0g0<5<?16?i=5251896b32;>?70=k6;070>{t;mn1<7;t=2gg>7`f349mj7ji;<1`1?43<278h;4=429>7a2=:=90q~=ke;292~;4ml09jl524129`c=:;j=1>984=2f6>724349o47<;5:?0`2<5<=1v>ji:18685bn38mm63;008gb>;4k>0989523e59615<5:n36?:;;|q0a5<72=q6?k>52gc891652ml01>m6:367?85c038??6s|3bf94?2|5:io6?hn;<1`b?43<278:o4=449>7fe=:=?0q~=9a;297~;4>j0oj63<6e8gb>;4>k09j=5rs24:>5<5s49>h7<i0:?02g<5<11v>87:181853i38m<63<6c8102=z{:ih6=4<{<1``?ba349hi7ji;<1`g?4a82wx?nl50;0x96da2;l;70=lc;07<>{t;jk1<7<t=2c`>7`7349ho7<;7:p040=838p19?::ed8916>2;l;7p};1883>6}:<8;1>k64=531>7`?34>:m7<i0:p04e=838p19?m:ed8916f2;l;7p};1g83>7}:<8>1>k64=503>7`73ty?=54?:3y>04>=:ok019?n:367?xu39>0;6>u240:9`c=:<8=1>ko4=52:>7233ty?=84?:5y>041=lo168<;52gc8916>2;>870:>a;077>{t<8o1<7<t=53f>7`f34>9<7<;4:p04b=839p19?j:ed8917c2;lj70:?a;070>{t<8h1<7:t=53g>a`<5=;i6?hn;<63e?43;27?>=4=429~w16b2909w0:?b;fe?827m38mm6s|41a94?4|5=:o6ih4=52`>7`f3ty8m:4?:3y>7de=k816?ll52g28yv5f>3:1>v3<a`81b5=:;hh1o<5rs2c6>5<5s49j57<i0:?0ed<d92wx?l:50;0x96g?2;l;70=n9;a2?xu4j:0;6?u23``9765<5:h?6?h?;|q0f4<72;q6?lo5321896d52;l;7p}<ag83>7}:;h31?>=4=2`3>7`73ty8mi4?:3y>7d>=;:901>oj:3d3?xu4j<0;6?u23`a9765<5:h=6?h?;|q0fd<72;q6?oh5c09>7gc=:o:0q~=m9;296~;4jm09j=523cg9g4=z{:h36=4={<1ag?4a8278ni4l1:p7g1=838p1>lm:3d3?85ek3i:7p}<c783>7}:;ko1?>=4=2a4>7`73ty8o94?:3y>7gb=;:901>m::3d3?xu4k;0;6?u23ca9765<5:i86?h?;|q0g5<72;q6?ol5321896e62;l;7p}<c983>7}:;kl1?>=4=2a:>7`73ty8884?:3y>71g=k816?9752g28yv53<3:1>v3<4981b5=:;=31o<5rs260>5<5s49?;7<i0:?00=<d92wx?9<50;0x96212;l;70=;7;a2?xu4=80;6?u235;9765<5:?96?h?;|q00c<72;q6?965321896372;l;7p}<4e83>7}:;==1?>=4=26f>7`73ty88o4?:3y>710=;:901>:l:3d3?xu4=:0;6?u235c9765<5:??6?h?;|q01=<72;q6?8j5c09>70e=:o:0q~=:7;296~;4=k09j=5234a9g4=z{:?=6=4={<16e?4a82789o4l1:p703=838p1>;6:3d3?852i3i:7p}<6583>7}:;<i1?>=4=246>7`73ty8:?4?:3y>70d=;:901>8<:3d3?xu4>90;6?u234c9765<5:<:6?h?;|q01`<72;q6?8753218963a2;l;7p}<6783>7}:;<n1?>=4=244>7`73ty8;;4?:5y>721=:o:01>99:367?850038?963<788103=z{:286=4={<1;g?ba349<=7<i0:p7=2=838p1>6k:ed896152;l;7p}<8483>7}:;1o1hk5236196c6<uz93:7>52z?0<c<cn278;94=f19~w6>02909w0=60;fe?850=38m<6s|39:94?4|5:3:6ih4=255>7`73ty8444?:3y>7<4=lo16?:652g28yv5?i3:1>v3<928gb>;4?009j=5rs2f6>5<3s49o97<;4:?0`3<5n916?i95257896b?2;>=7p}<e083>7}:;l31hk523e296c6<uz9n>7>52z?0ad<cn278h<4=f19~w6c42909w0=jb;fe?85c:38m<6s|3d694?4|5:oh6ih4=2f0>7`73ty8i84?:3y>7`b=lo16?i:52g28yv5b>3:1>v3<ed8gb>;4l<09j=5rs2g4>5<5s49nj7ji;<1g3?4a82wx?h650;0x96`72ml01>j7:3d3?xu4>o0;6>u241693d=:;1h1hk5236296c6<utd>4i4?:0yK074<ug?3i7>51zJ767=zf<2m6=4>{I616>{i=0:1<7?tH501?xh2180;6<uG4308yk3>:3:1=vF;239~j0?4290:wE:=2:m1<2=838pD9<=;|l6=0<72;qC8?<4}o7:2?6=:rB?>?5rn4;4>5<5sA>9>6sa58:94?4|@=897p`:9883>7}O<;80qc;6a;296~N3:;1vb87m:181M25:2we94m50;0xL1453td>5i4?:3yK074<ug?2i7>52zJ767=zf<3m6=4={I616>{i=h:1<7<tH501?xh2i80;6?uG4308yk3f:3:1>vF;239~j0g42909wE:=2:m1d2=838pD9<=;|l6e0<72;qC8?<4}o7b2?6=:rB?>?5rn4c4>5<5sA>9>6sa5`:94?4|@=897p`:a883>7}O<;80qc;na;296~N3:;1vb8om:181M25:2we9lm50;0xL1453td>mi4?:3yK074<ug?ji7>52zJ767=zf<km6=4={I616>{i=k:1<7<tH501?xh2j80;6?uG4308yk3e:3:1>vF;239~j0d42909wE:=2:m1g2=838pD9<=;|l6f0<72;qC8?<4}o7a2?6=:rB?>?5rn4`4>5<5sA>9>6sa5c:94?4|@=897p`:b883>7}O<;80qc;ma;296~N3:;1vb8lm:181M25:2we9om50;0xL1453td>ni4?:0yK074<ug?ii7>51zJ767=zf<hm6=4>{I616>{i=j:1<7?tH501?xh2k80;6<uG4308yk3d:3:1=vF;239~j0e42909wE:=2:m1f2=839pD9<=;|l6g0<72:qC8?<4}o7`2?6=:rB?>?5rn4a4>5<5sA>9>6sa5b:94?4|@=897p`:c883>7}O<;80qc;la;296~N3:;1vb8mm:181M25:2we9nm50;0xL1453td>oi4?:3yK074<ug?hi7>52zJ767=zf<im6=4={I616>{i=m:1<7<tH501?xh2l80;6?uG4308yk3c:3:1>vF;239~j0b42909wE:=2:m1a2=838pD9<=;|l6`0<72;qC8?<4}o7g2?6=:rB?>?5rn4f4>5<5sA>9>6sa5e:94?4|@=897p`:d883>7}O<;80qc;ka;296~N3:;1vb8jm:181M25:2we9im50;0xL1453td>hi4?:3yK074<ug?oi7>52zJ767=zf<nm6=4={I616>{i=l:1<7<tH501?xh2m80;6?uG4308yk3b:3:1>vF;239~j0c42909wE:=2:m1`2=838pD9<=;|l6a0<72;qC8?<4}o7f2?6=:rB?>?5rn4g4>5<5sA>9>6sa5d:94?4|@=897p`:e883>7}O<;80qc;ja;296~N3:;1vb8km:181M25:2we9hm50;0xL1453td>ii4?:3yK074<ug?ni7>52zJ767=zf<om6=4={I616>{i=o:1<7<tH501?xh2n80;6?uG4308yk3a:3:1>vF;239~j0`42909wE:=2:m1c2=838pD9<=;|l6b0<72;qC8?<4}o7e2?6=:rB?>?5rn4d4>5<5sA>9>6sa5g:94?4|@=897p`:f883>7}O<;80qc;ia;296~N3:;1vb8hm:181M25:2we9km50;0xL1453td>ji4?:3yK074<ug?mi7>52zJ767=zf<lm6=4={I616>{i>9:1<7<tH501?xh1880;6<uG4308yk07:3:1=vF;239~j364290:wE:=2:m252=83;pD9<=;|l540<728qC8?<4}o432?6=9rB?>?5rn724>5<6sA>9>6sa61:94?7|@=897p`90883>4}O<;80qc8?a;295~N3:;1vb;>m:182M25:2we:=m50;3xL1453td=<i4?:0yK074<ug<;i7>51zJ767=zf?:m6=4>{I616>{i>8:1<7?tH501?xh1980;6<uG4308yk06:3:1=vF;239~j374290:wE:=2:m242=83;pD9<=;|l550<728qC8?<4}o422?6=9rB?>?5rn734>5<6sA>9>6sa60:94?7|@=897p`91883>4}O<;80qc8>a;295~N3:;1vb;?m:182M25:2we:<m50;3xL1453td==i4?:0yK074<ug<:i7>51zJ767=zf?;m6=4>{I616>{i>;:1<7?tH501?xh1:80;6<uG4308yk05:3:1=vF;239~j344290:wE:=2:m272=83;pD9<=;|l560<728qC8?<4}o412?6=9rB?>?5rn704>5<6sA>9>6sa63:94?7|@=897p`92883>4}O<;80qc8=a;295~N3:;1vb;<m:182M25:2we:?m50;3xL1453td=>i4?:0yK074<ug<9i7>51zJ767=zf?8m6=4>{I616>{i>::1<7?tH501?xh1;80;6<uG4308yk04:3:1=vF;239~j354290:wE:=2:m262=83;pD9<=;|l570<728qC8?<4}o402?6=9rB?>?5rn714>5<6sA>9>6sa62:94?7|@=897p`93883>4}O<;80qc8<a;295~N3:;1vb;=m:182M25:2we:>m50;3xL1453td=?i4?:0yK074<ug<8i7>51zJ767=zf?9m6=4>{I616>{i>=:1<7?tH501?xh1<80;6<uG4308yk03:3:1=vF;239~j324290:wE:=2:m212=83;pD9<=;|l500<728qC8?<4}o472?6=9rB?>?5rn764>5<6sA>9>6sa65:94?7|@=897p`94883>4}O<;80qc8;a;295~N3:;1vb;:m:182M25:2we:9m50;3xL1453td=8i4?:0yK074<ug<?i7>51zJ767=zf?>m6=4>{I616>{i><:1<7?tH501?xh1=80;6<uG4308yk02:3:1=vF;239~j334290:wE:=2:m202=83;pD9<=;|l510<728qC8?<4}o462?6=9rB?>?5rn774>5<6sA>9>6sa64:94?7|@=897p`95883>4}O<;80qc8:a;295~N3:;1vb;;m:182M25:2we:8m50;0xL1453td88h4?:0yK074<ug9?j7>51zJ767=zutwKLNu82g84e5ge<;>vLMLt0|BCT~{GH
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.vhd b/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.vhd
deleted file mode 100644
index 1ef6411..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.vhd
+++ /dev/null
@@ -1,280 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
--- You must compile the wrapper file sync_fifo_512x41.vhd when simulating
--- the core, sync_fifo_512x41. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-LIBRARY XilinxCoreLib;
--- synthesis translate_on
-ENTITY sync_fifo_512x41 IS
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(40 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(40 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END sync_fifo_512x41;
-
-ARCHITECTURE sync_fifo_512x41_a OF sync_fifo_512x41 IS
--- synthesis translate_off
-COMPONENT wrapped_sync_fifo_512x41
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(40 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(40 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END COMPONENT;
-
--- Configuration specification
-  FOR ALL : wrapped_sync_fifo_512x41 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
-    GENERIC MAP (
-      c_add_ngc_constraint => 0,
-      c_application_type_axis => 0,
-      c_application_type_rach => 0,
-      c_application_type_rdch => 0,
-      c_application_type_wach => 0,
-      c_application_type_wdch => 0,
-      c_application_type_wrch => 0,
-      c_axi_addr_width => 32,
-      c_axi_aruser_width => 1,
-      c_axi_awuser_width => 1,
-      c_axi_buser_width => 1,
-      c_axi_data_width => 64,
-      c_axi_id_width => 4,
-      c_axi_ruser_width => 1,
-      c_axi_type => 0,
-      c_axi_wuser_width => 1,
-      c_axis_tdata_width => 64,
-      c_axis_tdest_width => 4,
-      c_axis_tid_width => 8,
-      c_axis_tkeep_width => 4,
-      c_axis_tstrb_width => 4,
-      c_axis_tuser_width => 4,
-      c_axis_type => 0,
-      c_common_clock => 1,
-      c_count_type => 0,
-      c_data_count_width => 9,
-      c_default_value => "BlankString",
-      c_din_width => 41,
-      c_din_width_axis => 1,
-      c_din_width_rach => 32,
-      c_din_width_rdch => 64,
-      c_din_width_wach => 32,
-      c_din_width_wdch => 64,
-      c_din_width_wrch => 2,
-      c_dout_rst_val => "0",
-      c_dout_width => 41,
-      c_enable_rlocs => 0,
-      c_enable_rst_sync => 1,
-      c_error_injection_type => 0,
-      c_error_injection_type_axis => 0,
-      c_error_injection_type_rach => 0,
-      c_error_injection_type_rdch => 0,
-      c_error_injection_type_wach => 0,
-      c_error_injection_type_wdch => 0,
-      c_error_injection_type_wrch => 0,
-      c_family => "virtex6",
-      c_full_flags_rst_val => 1,
-      c_has_almost_empty => 0,
-      c_has_almost_full => 0,
-      c_has_axi_aruser => 0,
-      c_has_axi_awuser => 0,
-      c_has_axi_buser => 0,
-      c_has_axi_rd_channel => 0,
-      c_has_axi_ruser => 0,
-      c_has_axi_wr_channel => 0,
-      c_has_axi_wuser => 0,
-      c_has_axis_tdata => 0,
-      c_has_axis_tdest => 0,
-      c_has_axis_tid => 0,
-      c_has_axis_tkeep => 0,
-      c_has_axis_tlast => 0,
-      c_has_axis_tready => 1,
-      c_has_axis_tstrb => 0,
-      c_has_axis_tuser => 0,
-      c_has_backup => 0,
-      c_has_data_count => 0,
-      c_has_data_counts_axis => 0,
-      c_has_data_counts_rach => 0,
-      c_has_data_counts_rdch => 0,
-      c_has_data_counts_wach => 0,
-      c_has_data_counts_wdch => 0,
-      c_has_data_counts_wrch => 0,
-      c_has_int_clk => 0,
-      c_has_master_ce => 0,
-      c_has_meminit_file => 0,
-      c_has_overflow => 0,
-      c_has_prog_flags_axis => 0,
-      c_has_prog_flags_rach => 0,
-      c_has_prog_flags_rdch => 0,
-      c_has_prog_flags_wach => 0,
-      c_has_prog_flags_wdch => 0,
-      c_has_prog_flags_wrch => 0,
-      c_has_rd_data_count => 0,
-      c_has_rd_rst => 0,
-      c_has_rst => 1,
-      c_has_slave_ce => 0,
-      c_has_srst => 0,
-      c_has_underflow => 0,
-      c_has_valid => 0,
-      c_has_wr_ack => 0,
-      c_has_wr_data_count => 0,
-      c_has_wr_rst => 0,
-      c_implementation_type => 0,
-      c_implementation_type_axis => 1,
-      c_implementation_type_rach => 1,
-      c_implementation_type_rdch => 1,
-      c_implementation_type_wach => 1,
-      c_implementation_type_wdch => 1,
-      c_implementation_type_wrch => 1,
-      c_init_wr_pntr_val => 0,
-      c_interface_type => 0,
-      c_memory_type => 1,
-      c_mif_file_name => "BlankString",
-      c_msgon_val => 1,
-      c_optimization_mode => 0,
-      c_overflow_low => 0,
-      c_preload_latency => 1,
-      c_preload_regs => 0,
-      c_prim_fifo_type => "512x72",
-      c_prog_empty_thresh_assert_val => 2,
-      c_prog_empty_thresh_assert_val_axis => 1022,
-      c_prog_empty_thresh_assert_val_rach => 1022,
-      c_prog_empty_thresh_assert_val_rdch => 1022,
-      c_prog_empty_thresh_assert_val_wach => 1022,
-      c_prog_empty_thresh_assert_val_wdch => 1022,
-      c_prog_empty_thresh_assert_val_wrch => 1022,
-      c_prog_empty_thresh_negate_val => 3,
-      c_prog_empty_type => 0,
-      c_prog_empty_type_axis => 0,
-      c_prog_empty_type_rach => 0,
-      c_prog_empty_type_rdch => 0,
-      c_prog_empty_type_wach => 0,
-      c_prog_empty_type_wdch => 0,
-      c_prog_empty_type_wrch => 0,
-      c_prog_full_thresh_assert_val => 510,
-      c_prog_full_thresh_assert_val_axis => 1023,
-      c_prog_full_thresh_assert_val_rach => 1023,
-      c_prog_full_thresh_assert_val_rdch => 1023,
-      c_prog_full_thresh_assert_val_wach => 1023,
-      c_prog_full_thresh_assert_val_wdch => 1023,
-      c_prog_full_thresh_assert_val_wrch => 1023,
-      c_prog_full_thresh_negate_val => 509,
-      c_prog_full_type => 0,
-      c_prog_full_type_axis => 0,
-      c_prog_full_type_rach => 0,
-      c_prog_full_type_rdch => 0,
-      c_prog_full_type_wach => 0,
-      c_prog_full_type_wdch => 0,
-      c_prog_full_type_wrch => 0,
-      c_rach_type => 0,
-      c_rd_data_count_width => 9,
-      c_rd_depth => 512,
-      c_rd_freq => 1,
-      c_rd_pntr_width => 9,
-      c_rdch_type => 0,
-      c_reg_slice_mode_axis => 0,
-      c_reg_slice_mode_rach => 0,
-      c_reg_slice_mode_rdch => 0,
-      c_reg_slice_mode_wach => 0,
-      c_reg_slice_mode_wdch => 0,
-      c_reg_slice_mode_wrch => 0,
-      c_synchronizer_stage => 2,
-      c_underflow_low => 0,
-      c_use_common_overflow => 0,
-      c_use_common_underflow => 0,
-      c_use_default_settings => 0,
-      c_use_dout_rst => 1,
-      c_use_ecc => 0,
-      c_use_ecc_axis => 0,
-      c_use_ecc_rach => 0,
-      c_use_ecc_rdch => 0,
-      c_use_ecc_wach => 0,
-      c_use_ecc_wdch => 0,
-      c_use_ecc_wrch => 0,
-      c_use_embedded_reg => 0,
-      c_use_fifo16_flags => 0,
-      c_use_fwft_data_count => 0,
-      c_valid_low => 0,
-      c_wach_type => 0,
-      c_wdch_type => 0,
-      c_wr_ack_low => 0,
-      c_wr_data_count_width => 9,
-      c_wr_depth => 512,
-      c_wr_depth_axis => 1024,
-      c_wr_depth_rach => 16,
-      c_wr_depth_rdch => 1024,
-      c_wr_depth_wach => 16,
-      c_wr_depth_wdch => 1024,
-      c_wr_depth_wrch => 16,
-      c_wr_freq => 1,
-      c_wr_pntr_width => 9,
-      c_wr_pntr_width_axis => 10,
-      c_wr_pntr_width_rach => 4,
-      c_wr_pntr_width_rdch => 10,
-      c_wr_pntr_width_wach => 4,
-      c_wr_pntr_width_wdch => 10,
-      c_wr_pntr_width_wrch => 4,
-      c_wr_response_latency => 1,
-      c_wrch_type => 0
-    );
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_sync_fifo_512x41
-  PORT MAP (
-    clk => clk,
-    rst => rst,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty
-  );
--- synthesis translate_on
-
-END sync_fifo_512x41_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.vho b/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.vho
deleted file mode 100644
index a76e8d0..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.vho
+++ /dev/null
@@ -1,93 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
---    Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3   --
---                                                                            --
---    Rev 1. The FIFO Generator is a parameterizable first-in/first-out       --
---    memory queue generator. Use it to generate resource and performance     --
---    optimized FIFOs with common or independent read/write clock domains,    --
---    and optional fixed or programmable full and empty flags and             --
---    handshaking signals.  Choose from a selection of memory resource        --
---    types for implementation.  Optional Hamming code based error            --
---    detection and correction as well as error injection capability for      --
---    system test help to insure data integrity.  FIFO width and depth are    --
---    parameterizable, and for native interface FIFOs, asymmetric read and    --
---    write port widths are also supported.                                   --
---------------------------------------------------------------------------------
-
--- Interfaces:
---    AXI4Stream_MASTER_M_AXIS
---    AXI4Stream_SLAVE_S_AXIS
---    AXI4_MASTER_M_AXI
---    AXI4_SLAVE_S_AXI
---    AXI4Lite_MASTER_M_AXI
---    AXI4Lite_SLAVE_S_AXI
---    master_aclk
---    slave_aclk
---    slave_aresetn
-
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-COMPONENT sync_fifo_512x41
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(40 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(40 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END COMPONENT;
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : sync_fifo_512x41
-  PORT MAP (
-    clk => clk,
-    rst => rst,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty
-  );
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file sync_fifo_512x41.vhd when simulating
--- the core, sync_fifo_512x41. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.xco b/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.xco
deleted file mode 100644
index 451c055..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.xco
+++ /dev/null
@@ -1,213 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Fri Sep 19 14:11:57 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:fifo_generator:9.3
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=sync_fifo_512x41
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=2
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=3
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=510
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=509
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=41
-CSET input_depth=512
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=41
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=9
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET synchronization_stages=2
-CSET synchronization_stages_axi=2
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=9
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-11-19T12:39:56Z
-# END Extra information
-GENERATE
-# CRC: 2a3474ef
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.xise b/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.xise
deleted file mode 100644
index 03463ae..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_512x41.xise
+++ /dev/null
@@ -1,74 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="sync_fifo_512x41.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="sync_fifo_512x41.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|sync_fifo_512x41|sync_fifo_512x41_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="sync_fifo_512x41.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sync_fifo_512x41" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="sync_fifo_512x41" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-19T16:13:50" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E0A70CCEAC1145F3A8FDDFC1E84B5490" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.asy b/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.asy
deleted file mode 100644
index 9afd578..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.asy
+++ /dev/null
@@ -1,37 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 sync_fifo_FWFT_512x36
-RECTANGLE Normal 32 32 800 4064
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName din[35:0]
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 464 32 464
-PIN 0 464 LEFT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Wide 832 272 800 272
-PIN 832 272 RIGHT 36
-PINATTR PinName dout[35:0]
-PINATTR Polarity OUT
-LINE Normal 832 304 800 304
-PIN 832 304 RIGHT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 832 496 800 496
-PIN 832 496 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.gise b/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.gise
deleted file mode 100644
index 021080a..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.gise
+++ /dev/null
@@ -1,53 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="sync_fifo_FWFT_512x36.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="sync_fifo_FWFT_512x36.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="sync_fifo_FWFT_512x36.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="sync_fifo_FWFT_512x36.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1411385153" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1411385153">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1600854814650439684" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7248263259641125956" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="905516576448332716" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.ngc b/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.ngc
deleted file mode 100644
index 6c0c968..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$50;44<,[o}e~g`n;"2*73>(-80!<m4/+])[WGIOL*!=6>:;123452739:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456788:0<==N311B4557;99;86>6913854g<9=0BB][[:@FGVDTCIMNY0<=50?3b?42=AGZ^X7OKDS@TVDBCZ5;86=0>4:35>LHW]]0OELJF<0794;7338<1EC^ZT;FJFAO;9<0;2<;4178LQQVR\3NDMIA31483:43<9?0DYY^ZT;FLFAI;9<0;2<=41;KMTPR=ZLMHIL2?:1<27>7=AGZ^X7\JGBGA85<768;0=7GAPTV9VVRF490;2<?41;KMTPR=ZZ^I0=4?>0915<=52@D[YY4NDEPBPLCOANB7=7>11891>LHW]]0JHI\MTHGKMBN;93:5=95=:HLSQQ<CAYKOE]2>:1<20>4=AGZ^X7JFPCFJT97=87;>7?4@UURVP?BHXHND\1?50?36?7<H]]Z^X7J@PCFLT97=87;87>85IORVP?BNFH6897>112902?OIX\^1HD@M<2794;753:<1EC^ZT;fjj952294:96=9:NWWTPR=LF__M1=::1<21>512F__\XZ5DNWWF952294:86=9:NWWTPR=lf0>;50?33?1<NFY__6ZKN<283:46<<3CE\XZ5WD@?7?69<2?>=8:454F65>053?K?7;ONA995EDGFIHK:<68NA@CBEDGFIHKJMLh46wn{566sno>38 =>0:5EBC@ANOLMJKHIFG31?=<NFY__6ZKMWD>4>58331O3M<564:;34<75300BB][[:@FGVD:?294:>675IORVP?GCL[H747>1169:>JSSX\^1^IOKDSG@G9>=87805L:49@CB6>G502KJML8NA@33?DGFIHKJM;ONA@CBE==FLMXJ0=07;@FGVD:6611JHI\N<3<;?DBCZH68255NDEPB818?3HNO^L2:>99B@ATF4?437LJKR@>4:d=FLMXJ054?>99B@ATF414n7LJKR@PGEABU494m7LJKR@PGEABU48:5j6OKDSCQ@DBCZ5;:2k5NDEPBVAGCL[6:>3?>;@FGVDTCIMNY0<=50?d8EABUI[NJHI\312<f?DBCZHXOMIJ]<0<f?DBCZHXOMIJ]<3<f?DBCZHXOMIJ]<2<f?DBCZHXOMIJ]<5<f?DBCZHXOMIJ]<4<f?DBCZHXOMIJ]<7<f?DBCZHXOMIJ]<6<f?DBCZHXOMIJ]<9<f?DBCZHXOMIJ]<8<e?DBCZH^BIEGHH=2=54=FLMXJXDKGIFJ?5?69n2KOH_O[IDJJCM:6611JHI\M<1<;?DBCZK6:255NDEPA878?3HNO^O2<>99B@ATE4=437LJKRC>6:==FLMXI0;07;@FGVG:06h1JHI\M<983:==FLMXI050i;@FGVGRNMACLD1>1109B@ATE\@OCEJF31;2=b>GCL[H_EHFFGI>2:`=FLMXI[_OKDS>3:c=FLMXI[_OKDS>24;`<IMNYNZ\NDEP?548a3HNO^OY]AEFQ8449981JHI\MWSCG@W:6;3:5j6OKDS@TVDBCZ5;82h5NDEPASWGCL[6:2h5NDEPASWGCL[692h5NDEPASWGCL[682h5NDEPASWGCL[6?2h5NDEPASWGCL[6>2h5NDEPASWGCL[6=2h5NDEPASWGCL[6<2h5NDEPASWGCL[632h5NDEPASWGCL[622?5NE29BHI?<IZSEOR\JG048FHKXAGLDSLJKRDQP[WGIOL20NX]PIODL5>E53JO:>6MGEBI\HLEBFZOTXT^J2:AJ0>EKC9<0OAE>8148GIM5?9?0OAE=X99@HN4_91:>7NBD9168GIMF=2IGGL?8;BNHE4B5?2IGGL?K469@HNG6L130OAENREAOO1=DDBH>7NBDB0;8GIME_[IGG85LLJA21>EKCM;>7NBDDWa8GIMC^VNBZDJJ5:AOOC^?3JF@JU?7029@HW?<KFGFEYZJD068GJTBWNOEI_O[INL\MK@H?2IYILZJD09G3>BEA]OY^<>4DEF3BA@7L9N;J=H?d:FFHD_BLV]YEYK>0:FEBC@ANOLMJKHIFG08@L><L@KOE1>19:FJEAO;99427IGNDH>25;?<L@KOE1?=>89GMDBN489556JFAEK?518e3MCJHD2>5;2==>BNIMC7=807;EKB@L:6611OELJF<3<;?AOFL@68255KI@FJ818?3MCJHD2:>99GMDBN4?437IGNDH>4:==CAHNB0507;EKB@L:>611OEOJF<1<:?AOEL@6:<374DH@GM976601OEOJF<00==>BNJMC7=>06;EKA@L:6<7h0HDLKI=36>58>3MCIHD2>5?:8@LDCA5;546JFBEK?6;><L@HOE1=18:FJFAO;<720HDLKI=7=<>BNJMC7:364DH@GM91902NBNIG38?:8@LDCA535;6JFN@>3:==CAGK7==07;EKME976611OECO313<;?AOII5;8255KIOC?518?3MCEM1?:>99GMKG;9?437IGAA=34:==CAGK7=507;EKME97>6>1OECO31?:8@LHF4;:546JFN@>15;><L@DJ0?<18:FJJD:5;720HD@N<36=<>BNFH699364DHLB870902NBBL2=7?:8@LHF4;2546JFN@>1=;1<L@DJ0?07;EKME957611OECO330<;?AOII599255KIOC?768?3MCEM1=;>`9GMKG;;<0;255KIOC?70803MCEM1=17:FJJD:36>1OECO35?58@LHF4?4<7IGAA=5=3>BNFH632:5KIOC?=;1<L@DI0=07;EKMF977611OECL310<;?AOIJ5;9255KIO@?568?3MCEN1?;>99GMKD;9<437IGAB=35:==CAGH7=:07;EKMF97?611OECL318<4?AOIJ5;546JFNC>14;><L@DI0??18:FJJG:5:720HD@M<31=<>BNFK698364DHLA873902NBBO2=6?:8@LHE4;=546JFNC>1<;><L@DI0?717:FJJG:5611OECL331<;?AOIJ59:255KIO@?778?3MCEN1=<>99GMKD;;=4j7IGAB=16>58?3MCEN1=:>69GMKD;;7=0HD@M<5<4?AOIJ5?5;6JFNC>5:2=CAGH7;394DHLA8=803MCEN171a:FJTDBNX5:5o6JFP@FJT97=87k0HD^NDHR?5;g<L@ZIHD^30?a8@LVEL@Z7=7>1a:FJTGBNX5;546J@AEM?4;?<LFKOC1??>89GKDBH48;556J@AEM?578>3MEJHB2>3?;8@JGCG5;?2o5KO@FL843=8730HBOKO=36:==CGHND0<07;EMB@J:5611OCLJ@<2<;?AIFLF6?255KO@FL808?3MEJHB29>99GKDBH4>437IANDN>;:==CGHND0408;EMB[WC@02NDNIA30?;8@JDCG5;;245KOCFL847912NDNIA313<:?AIELF6:?374DN@GK9736k1OCOJ@<0794;?<LFHOC1?:>99GKGBH48437IAMDN>1:==CGKND0>07;EMA@J:3611OCOJ@<4<;?AIELF6=255KOCFL828?3MEIHB27>99GKGBH404<7IAM_SGDe>BHXHND\1>1c:FLTDBHX5;1<3o4DNRB@JV;97k0HB^MDNR?4;e<LFZIHB^31;2=e>BHXKND\1?18:FLQQG;8730HB[[A=33:<=CG\^J0<?19:FLQQG;9;427IAZT@>27;?<LF__M1?;>89GKPRF48?556J@UUC?538>3ME^XL2>7?;8@JSSI5;3245KOTVB84?902NDYYO31?;8@JSSI58;245KOTVB877912NDYYO323<:?AIR\H69?374DNWWE943601OCXZN<37==>BH]]K7>;06;EMVPD:5?730HB[[A=0;:<=CG\^J0?718:FLQQG;:730HB[[A=13:<=CG\^J0>?19:FLQQG;;;427IAZT@>07;?<LF__M1=;>c9GKPRF4:?1<374DNWWE952611OCXZN<2<;?AIR\H6?255KOTVB808?3ME^XL29>99GKPRF4>437IAZT@>;:==CG\^J0407;EMVPG:7601OCXZM<02==>BH]]H7=<06;EMVPG:6:730HB[[B=30:<=CG\^I0<:19:FLQQD;9<427IAZTC>22;?<LF__N1?8>89GKPRE482556J@UU@?5<8?3ME^XO2>>89GKPRE4;:556J@UU@?648>3ME^XO2=2?;8@JSSJ588245KOTVA872912NDYYL324<:?AIR\K69:374DNWWF940601OCXZM<3:==>BH]]H7>407;EMVPG:5601OCXZM<22==>BH]]H7?<06;EMVPG:4:730HB[[B=10:<=CG\^I0>:1b:FLQQD;;<0;245KOTVA863902NDYYL33?:8@JSSJ5>546J@UU@?1;><LF__N1818:FLQQD;?720HB[[B=:=<>BH]]H753=4EOC4?@HFZMOE?6KAB69FJGQUMG?0JLB\E39E@6=ALJ>0JIMJ3:DGT1=ALYO?7KJ]E99EBC@5;:9:7J=4GOF2?L4<A980E<<4I308M64<A=80E864IOKWTZ6702CEEY^P00:8MKOSXV:946GAIUR\46><AGC_\R>;8:KMMQVX8<20ECG[P^25<>OIA]ZT<:74IOKWWQGSM>1BBDZP0158MKOSW9;<7D@FT^213>OIA]U;?:5FNHV\411<AGC_S=;8;HLJPZ61?2CEEYQ?769JJLRX81=0ECG[_1;4?LHN\V:J;6GAIU]3F2=NF@^T<N94IOKW[5B03@DBXR>J7:KMMQY7N>1BBDZP1158MKOSW8;<7D@FT^313>OIA]U:?:5FNHV\511<AGC_S<;8;HLJPZ71?2CEEYQ>769JJLRX91=0ECG[_0;4?LHN\V;J;6GAIU]2F2=NF@^T=N94IOKW[4B03@DBXR?J7:KMMQY6N>1BBDZP2158MKOSW;;<7D@FT^013>OIA]U9?:5FNHV\611<AGC_S?;8;HLJPZ41?2CEEYQ=769JJLRX:1=0ECG[_3;4?LHN\V8J;6GAIU]1F2=NF@^T>N94IOKW[7B03@DBXR<J7:KMMQY5N>1BBDZP3158MKOSW:;<7D@FT^113>OIA]U8?:5FNHV\711<AGC_S>;8;HLJPZ51?2CEEYQ<769JJLRX;1=0ECG[_2;4?LHN\V9J;6GAIU]0F2=NF@^T?N94IOKW[6B03@DBXR=J7:KMMQY4N?1BBDZPA79JJLRXJ01BBDZPFHNF`>OIBLI_HOG[ESPg?LHMMJ^XNDZJRS18MKP13EEJHHJ9;MM@O@B03EELENOC4:NVP72<D\^886BZT568HPR2<2F^X;;4MRELJ0=J]QIRo6CnjnpUawunggi0Ad``rWgqwlii:2D;>6@>7:LFPRIUC=1ECCK>;N34?JVSADCQIR^]ILKWMSCTWGMH=6^l;Q,14456889T@95_ASVb?UOIWK_XEIVm;QKM[GSTFHGN56^D_INVPKK43YXN:6^\DNLF5>W63[20^LCM19G2<>TFEVGDHHm4RECG@WCDK5:5o6\KAEFQAFE;97i0^IOKDSG@G949k2XOMIJ]EBA?7;e<ZMKOH_KLC=6=g>TCIMNYINM35?a8VAGCL[OHO181c:PGEABUMJI7;3k4RECG@WCDK521<3m4RECG@WCDK525=45]D@FGVZEHDECXEB@PHVALJCO@i2XNMIQIISQWg>TBIMU\EIZG_@a8V@GCW^COXEQM5:PFCFCe3[OLOHO30;2==>TBOJOJ0=0m;SGDG@GUMNIN:6\JGBGAf>TBOJOI0=4?>89QABEBJ5:5h6\JGBNHEWBUKEA<7_KHCMIA=>TT\H6;6=08;SQWE96912XXXO2?:1<4?WUSJ5:5h6\\TSCNEWUSZHG<7_][R@OA`>TT\[OLM_][RDE4?WUSZLMI=<5]SUPFCZVUAFXBXTQN109QWQTBOVZYEB\FTX]A5>U?3ZK]IIO[A69PFLRBZ[90_I^>1:QKV@AXMQ^YMNZPNFAf?VNUMNUFECQ\I[G27>UNEVID@AG\INL\GMCDCh1XE@QKEWK@A==TC@ZT\D@9;RMVVFC03ZX]MAQN7:QQRDJXJ?1XXLZZS59WVPC33]S[I;<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dv4(un~l#@czx^PBIZTCWLDTJZH[107a?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{;%~kyit.PBIZTBOF__SH@>649V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au9'xm{kz ctpq[cqa|VymykPFRO\BCb6>11^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}1/pescr(k|xySkyit^qweqcXNZGTJKj>-Hl5=>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nx:"hxfu-`qwtXn~lS~zntd]EWHYANm;&Ec?95:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+bt6&{l|jy!lusp\br`sWz~jxhQISL]EBa4112_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j|>.sdtbq)d}{xTjzh{_rvbp`YA[DUMJi<"Io36e>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nx:"hxfu-fiur~Wo}mxRhm589V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au9'xm{kz elrw}Z`pn}Ub;:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eq5+tao~$kbgag^gntqXn~lSaknvhld[`kw|pUm{kzPOS];[j1?3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k?!rguep*ahagmTi`~{y^dtbqYkmh|bbjQjmqvz[cqa|VEYS5Q`14d8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`z8$yjzh{/og{pZ`pn}Uxxlzj<1<54>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#||tr-`5*aj}q$hm|vndv?4;073\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.sqww*e6'ng~t#mnrs{maq:66?:0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j;$k`{w.bcqv|hb|585:=5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$o<!hmtz-gdtuqgo0>091:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'xxx~!l1.enq}(`eR:V"jc>.l355>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#||tr-`5*aj}q$laV?R.fop*hu192_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/pppv)d9&mfyu hmZ0^*bkt&dy==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+tt|z%h="ibuy,di^5Z&ngx"`}91:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'xxx~!l1.enq}(`eR>V"jc|.lq61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#||tr-`5*p6494>:6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+tt|z%h="x><1<210=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g4)q95;59;5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$o<!y1=3=503<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!rrvp+f7(~8692884U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#n? v0>1:4323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.sqww*e6';7?3;9;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"m>/w3?7;72=2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/pppv)d9&|:090:6:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'xxx~!l1.t28186>91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(k;%laxv!c`pq}kcs494=<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+tt|z%h>"ibuy,`ewt~fl~7=38?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"m=/fov|+efz{seiy2=>728Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b0,chs&jky~t`jt=1=24=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g7)`e|r%k`U?]/en5+k6>81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(k;%laxv!glY2Y+aj{'gx:<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$o?!hmtz-ch]5U'mf#c|609V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$yy} c3-dip~)odQ8Q#ibs/op24=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g7)`e|r%k`U;]/enw+kt=<1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(k;%}=1>1579V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$yy} c3-u59699<?0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j8$z<2>>448Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b0,r4:668?>7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*wus{&i9#{?32?75?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.a1+s7;:7;>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+tt|z%h>"x><2<62>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#||tr-`6*p64:4:985Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$o?!y1=6=13=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g7)q95>5=8<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#nabp171?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.aliu71l2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/pppv)`g`dlShctx]oadpnfnUna}zv_NP\2Zi1m2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/pppv)`g`dlShctx]oadpnfnUna}zv_NP\2Zi6=k1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(zhgTi`~{y^da[l303\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~iQnup\tist95:5Sd`y7e9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$Aljk_fa3*firf}Q3QRIAD^010ZiXimnT<RAZT^zlv96998UBB[Q?769V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$Aljk_fa3*firf}Q3QRIAD^010ZiXimnT<RAZT^zlv97998=<7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*KflmUlo= lotlw_=[XOGNT>?:Po^cg`Z6XG\^Ttb|32?3232=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| M`fg[be7&je~byU7]^EM@Z45<VeTmijP0^MVPZ~hz595=<98;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&GjhiQhc1,`kphsS1WTKCJP236\kZgclV:TCXZPxnp?0;76?>1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,IdbcWni;"naznuY;YZAILV898RaPaef\4ZIR\Vrd~1;11054?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"Cnde]dg5(dg|dW5SPGOF\672XgVkohR>POTV\|jt;>7;:;55Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(EhnoSjm?.bmvjq]?UVMEHR<=4^m\eabX8VE^XRv`r=4=5470?2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-NeabXoj:%ob{atZ:^[BHCW;8?SbQnde]3[JSSWqey0:0>1658Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#@okd^e`4+eh}g~P4PQHNE]161YhWhnoS=Q@UU]{kw:?68;>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{<1<61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphs484>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{<3<61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphs4:4>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{<5<61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphs4<4>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{<7<61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphs4>4>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{<9<5g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsS1WTKCJP236\kZgclV:TCXZ31?4`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkr\0TULBIQ=25]l[dbcW9UDYY2=>7a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjq]?UVMEHR<=4^m\eabX8VE^X1=16b9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmp^>ZWNDOS?<;_n]b`aY7WF__0909c:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw_=[XOGNT>?:Po^cg`Z6XG\^7938l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uovX<XY@FMU9>9Q`_`fg[5YH]]6=2;m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznuY;YZAILV898RaPaef\4ZIR\5=5:n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{atZ:^[BHCW;8?SbQnde]3[JSS414>86[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{_177?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkrX9<>0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+be7&je~byQ=559V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmpZ52<2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-dg5(dg|dS9;;;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\102<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}U=995Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{at^560>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsW1?37X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*ad8'idyczPd0>2:0><]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}Uo=1<1599V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmpZb64:4>46[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{_e3?0;3?3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~Th<2:>4:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjqYc95<5955Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{at^f2828202_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-dg5(dg|dSi?38?74?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkrXl8U:9:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{at^f2[7303\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~Th<Q<569V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmpZb6W=?<7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*ad8'idyczPd0]612=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|Vn:S;;8;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\`4Y0=>1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexRj>_943?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.a3+bkrp'ij~waeu>3:36<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!wrvp+f6(ods"no}rxlfp979>91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,twqu(k9%laxv!c`pq}kcs4;4=<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+qt|z%h<"ibuy,`ewt~fl~7?38>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m?/fov|+ajS9W%k`?!m042?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.a3+bkrp'mfW<S!glq-iv063\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e7'ng~t#ib[3_-chu)ez<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i;#jczx/en_6[)ody%a~8>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m?/fov|+ajS=W%k`}!mr76?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.a3+s7;87?=7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i;#{?30?361>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`4*p6484>:6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+qt|z%h<"x><0<210=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ xsuq,g5)q95859;5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$o=!y1=0=503<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!wrvp+f6(~8682884U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)z~x#n> v0>0:4323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e7';783;9;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m?/w3?0;7182_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d9&mfyu laspzj`r;87<;7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i:#jczx/abvwim}6:2;>4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)z~x#n? glw{*fguzpdnx1<1619V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$|y} c0-dip~)khxyuck{<2<55>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`5*aj}q$laV>R.fo2*h7192_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d9&mfyu hmZ3^*bkt&dy==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+qt|z%h="ibuy,di^4Z&ngx"`}91:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l1.enq}(`eR9V"jc|.lq55>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`5*aj}q$laV:R.fop*hu2=2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d9&|:0=0:6:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l1.t28586=<1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,twqu(k8%}=1?1579V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$|y} c0-u59799<?0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hwrq-svrt'j;$z<2=>448Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%{~z|/b3,r4:568?>7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i:#{?33?75?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.a2+s7;;7;>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+qt|z%h="x><5<62>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`5*p64=4:9?5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$obc0408Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%{~z|/bmnt43f3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*tfeVl~`aQlol`6f>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-qehYa}efTobcm14c8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%{~z|/scn[cskdVliSd;8;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"|nm^dvhiYn<o1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"|nm^uq[`hXa8=h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*KflmUlon>!gb2-gjsi|R2VSJ@K_314[jYflmU;SB[[_ymq84869>i0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!xpovq+HgclVmho= hc1,`kphsS1WTKCJP225\kZgclV:TCXZPxnp?6;76?j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,IdbcWnih<#il0/alqkr\0TULBIQ=36]l[dbcW9UDYYQwos>0:470k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-NeabXoji;"jm?.bmvjq]?UVMEHR<<7^m\eabX8VE^XRv`r=6=541d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.Ob`aY`kj:%kn>!cnwmp^>ZWNDOS?=8_n]b`aY7WF__Sua}<4<252e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%||cz}/Lcg`Zadk9$lo= lotlw_=[XOGNT>>9Po^cg`Z6XG\^Ttb|36?323a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| M`fg[bed8'mh<#m`uovX<XY@FMU9?:Q`_`fg[5YH]]Usc29>0323f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| M`fg[bed8'mh<#m`uovX<XY@FMU9?:Q`_`fg[5YH]]Usc28>034g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!Baef\cfe7&ni;"naznuY;YZAILV88;RaPaef\4ZIR\Vrd~161107b?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|d0<0:a:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rvi|{%lon>!gb2-gjsi|5859l5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(oji;"jm?.bmvjq:46<k0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!xpovq+bed8'mh<#m`uov?0;3f3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{<4<6e>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!hcb2-cf6)kfex1815`9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}6<28o4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'nih<#il0/alqkr;07=:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw_=[XOGNT>>9Po^cg`Z6XG\^7=39>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsS1WTKCJP225\kZgclV:TCXZ32?52?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dW5SPGOF\661XgVkohR>POTV?7;163\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{[9_\CKBX::=TcRokd^2\KPR;<7=:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw_=[XOGNT>>9Po^cg`Z6XG\^7939>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsS1WTKCJP225\kZgclV:TCXZ36?52?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dW5SPGOF\661XgVkohR>POTV?3;163\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{[9_\CKBX::=TcRokd^2\KPR;07?27X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[43>3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{_37:?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dS>;6;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsW=?27X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[03>3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{_77:?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dS:;6;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphsW1?o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7;87?o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7;97?o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7;:7?o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7;;7?o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7;<7?o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7;=7?o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7;>7?o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7;?7?o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7;07?h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw[a7X8<i0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!xpovq+bed8'mh<#m`uov\`4Y6=j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5Z42k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dgf6)oj:%ob{at^f2[63d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{_e3\00e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%||cz}/fa`4+ad8'idyczPd0]61f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byQk1^46g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!hcb2-cf6)kfexRj>_67`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dSi?P8418Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pzVzexQltq2858312_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+kbe&ndyyQf<1<7e>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/ofi*bh}}Ub0<>14`9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb bel-gkprXa5;:29o4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ahc dnww[l:6:7>j7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&dof#iazt^k?5683i2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+kbe&ndyyQf<06=0d=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,nah)cg|~Te1?:>5c8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,`jssW`6::3:n;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"`kb/emvpZo;9>4?m6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'gna"j`uu]j84>9<h1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(jmd%ocxzPi=3::1?<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(lfSd2>>5c8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,`jssW`69<3:n;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"`kb/emvpZo;:84?m6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'gna"j`uu]j8749<h1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(jmd%ocxzPi=00:1g<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(lfSd2=4?6b?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.lgn+air|Vc7>80;a:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#cjm.flqqYn4;<58l5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$fi`!kotv\m9406=k0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$hb{{_h>1<;2f3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*hcj'me~xRg328<7=>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/ofi*bh}}Ub0?0;a:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#cjm.flqqYn4::58l5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$fi`!kotv\m9566=k0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$hb{{_h>06;2f3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*hcj'me~xRg332<7e>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/ofi*bh}}Ub0>:14`9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb bel-gkprXa59>2974U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ahc dnww[l:46=30Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$hb{{_h>7:1?<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(lfSd2:>5;8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,`jssW`6=2974U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ahc dnww[l:06=30Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$hb{{_h>;:1?<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(lfSd26>5:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,`jssW`U;855Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$fi`!kotv\mZ7312_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+kbe&ndyyQf_027=>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/ofi*bh}}UbS<?;9:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#cjm.flqqYnW88?56[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'gna"j`uu]j[45312_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+kbe&ndyyQf_067=>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/ofi*bh}}UbS<;;9:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#cjm.flqqYnW8<?56[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'gna"j`uu]j[41312_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+kbe&ndyyQf_0:7=>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/ofi*bh}}UbS<7;8:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#cjm.flqqYnW;>27X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&dof#iazt^k\652>3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*hcj'me~xRgP206:?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.lgn+air|VcT>?:6;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"`kb/emvpZoX::>27X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&dof#iazt^k\612>3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*hcj'me~xRgP246:?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.lgn+air|VcT>;:6;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"`kb/emvpZoX:>>27X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&dof#iazt^k\6=2>3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*hcj'me~xRgP286;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.lgn+air|VcT?974U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ahc dnww[lY48=30Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$hb{{_h]051?<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(lfSdQ<25;8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,`jssW`U8?974U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ahc dnww[lY4<=30Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$hb{{_h]011><]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(lfSdQ;499V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb bel-gkprXaV??46[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'gna"j`uu]j[32?3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*hcj'me~xRgP75:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,`jssW`U3855Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$fi`!kotv\mZ??92_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+kbe&mia#immf,dfhaf&gmnon mmf-djdrn~lhfk#`nthtf[gjlWdofSjka/emvpgYn4943>6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'gna"imm/eaib(`jdmj"cijcb,aib)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+air|kUb0<>1839V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb bel-dfh(`jdm%kocha/ldafe)jdm$kco{iwgaib(ii}c}iRlck^ofiZabf&ndyylPi=32:=4<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(okg%koch.f`ncd(iolih"och/flbplpbjdm%blzfvd]ahnYjmdUlic!kotva[l:6:7297X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&dof#jlb.f`nc+aeenk%bjklc/`nc*aii}c}ioch.ocwmscXjeaTahcPgdl,`jssjVc7=>072:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#cjm.eai+aeen$ln`in.oefgf(een%lblzfvd`nc+hf|`|nSobd_lgn[bci'me~xoQf<06=<7=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,nah)`jd$ln`i!gcode+h`mji%n`i gocwmsceen$emygye^`ooZkbeVmnb"j`uu`\m9726180Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$koc!gcod*bdjoh$ekhml.cod+bhf|`|nn`i!n`vjr`YedbUfi`Qheo-gkpreW`6::36=;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"`kb/f`n*bdjo'miajo!nfg`g+djo&memygyecod*kgsaoTnaePmdo\c`h(lfnRg316<;6>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/ofi*aee'miaj hbleb*kabkj$iaj!hn`vjr`djo'djxdxj_cnh[hcjWnoe#iaztc]j84>90;1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(jmd%ln` hble-cgk`i'dlinm!ble,ckgsaoiaj aaukuaZdkcVgnaRijn.flqqdXa5;225?4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ahc gco-cgk`&nhfkl agda`*gk`'ndjxdxjble-jdrn~lUi`fQbel]dak)cg|~iSd2>>908Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,cgk)okgl"jlbg`,mc`ed&kgl#j`nthtffha)fh~bzhQmlj]nahY`mg%ocxzm_h>14;>53\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*hcj'nhf"jlbg/eaibg)fnoho#lbg.emeqoqmkgl"co{iwg\fimXelgTkh` dnwwfZo;:843>6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'gna"imm/eaib(`jdmj"cijcb,aib)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+air|kUb0?<1839V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb bel-dfh(`jdm%kocha/ldafe)jdm$kco{iwgaib(ii}c}iRlck^ofiZabf&ndyylPi=00:=4<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(okg%koch.f`ncd(iolih"och/flbplpbjdm%blzfvd]ahnYjmdUlic!kotva[l:5<7297X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&dof#jlb.f`nc+aeenk%bjklc/`nc*aii}c}ioch.ocwmscXjeaTahcPgdl,`jssjVc7>8072:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#cjm.eai+aeen$ln`in.oefgf(een%lblzfvd`nc+hf|`|nSobd_lgn[bci'me~xoQf<34=<7=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,nah)`jd$ln`i!gcode+h`mji%n`i gocwmsceen$emygye^`ooZkbeVmnb"j`uu`\m9406180Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$koc!gcod*bdjoh$ekhml.cod+bhf|`|nn`i!n`vjr`YedbUfi`Qheo-gkpreW`69436=;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"`kb/f`n*bdjo'miajo!nfg`g+djo&memygyecod*kgsaoTnaePmdo\c`h(lfnRg328<;5>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/ofi*aee'miaj hbleb*kabkj$iaj!hn`vjr`djo'djxdxj_cnh[hcjWnoe#iaztc]j878?:2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+kbe&mia#immf,dfhaf&gmnon mmf-djdrn~lhfk#`nthtf[gjlWdofSjka/emvpgYn4::54?5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$fi`!hbl,dfha)okglm#`heba-fha(ogke{kmmf,meqoqmVhggRcjm^efj*bh}}hTe1=>>908Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,cgk)okgl"jlbg`,mc`ed&kgl#j`nthtffha)fh~bzhQmlj]nahY`mg%ocxzm_h>06;>53\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*hcj'nhf"jlbg/eaibg)fnoho#lbg.emeqoqmkgl"co{iwg\fimXelgTkh` dnwwfZo;;:43>6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'gna"imm/eaib(`jdmj"cijcb,aib)`fh~bzhlbg/lbplpbWkf`S`kb_fgm+air|kUb0>:1839V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb bel-dfh(`jdm%kocha/ldafe)jdm$kco{iwgaib(ii}c}iRlck^ofiZabf&ndyylPi=16:=7<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(okg%koch.f`ncd(iolih"och/flbplpbjdm%blzfvd]ahnYjmdUlic!kotva[l:461;0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$koc!gcod*bdjoh$ekhml.cod+bhf|`|nn`i!n`vjr`YedbUfi`Qheo-gkpreW`6?25?4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ahc gco-cgk`&nhfkl agda`*gk`'ndjxdxjble-jdrn~lUi`fQbel]dak)cg|~iSd2:>938Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,cgk)okgl"jlbg`,mc`ed&kgl#j`nthtffha)fh~bzhQmlj]nahY`mg%ocxzm_h>5:=7<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(okg%koch.f`ncd(iolih"och/flbplpbjdm%blzfvd]ahnYjmdUlic!kotva[l:061;0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$koc!gcod*bdjoh$ekhml.cod+bhf|`|nn`i!n`vjr`YedbUfi`Qheo-gkpreW`6325?4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ahc gco-cgk`&nhfkl agda`*gk`'ndjxdxjble-jdrn~lUi`fQbel]dak)cg|~iSd26>938Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!mdo,cgk)okgl"jlbg`,mc`ed&kgl#j`nthtffha)fh~bzhQmlj]nahY`mg%}magk.bqwv1b<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(|dzT~lcPre]fj1c<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(|dzT~lcPre]fj4543\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qehYulVoe?:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{kfSkhotv\ak543\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qehYpzVoe985Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae Mlw{[wbXzz~Tm~|jg^EM@Z75WfUFYUQ=_n3210=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(EdsSz|Prrv\evtboVMEHR?=_n]NQ]Y6Wf;:?i5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae RRV\BPJKWNOE855Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae gsqw`4(`zz~Tjxbc.sqw[a7302_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%l~~zk1/eqwqYa}ef%~~zPd36;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!}su`oo*au{}n:"j||t^dvhi(u{}Uo?9m4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&xxxobd/oetvatt|'myy }d^pppZtbo5:58n5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae nfuq`wus&nxxx#|k_sqw[wc`4;4?n6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!agvpgvvr)o{y"jPrrv\v`aX8=h0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*tt|kf`#cixreppp+au{}$yhR||t^pfcZ43k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%ekz|krrv-cwus&~xT~~zPrde?5;2e3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&dl{j}su,dvvr){UyyQ}ef]27a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(zmUyyQnssgd0`=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(zmUyyQnssgd[BHCW88TcRCZX^0\k16<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'{nT~~zParpfcZb6<91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wusjea$~iQ}su]bwwc`Wm88o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!}d^pppZehek9o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"|k_sqw[fijj89o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"y}_sqw[duumn>n7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"y}_sqw[duumnULBIQ>2^m\IP^X9Ve?<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!xr^pppZgtzlmTh<:?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%yylck.uq[wusWhyyijQk22a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+rtXzz~Tobcm3e9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#}{bmi,swYu{}Uhc`l>3g9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#z|Ppovq858Xag|:SD@Y_1a8QVCUW_CXEOBJ3:T@G<=QAL]TXT^J7:TJVQC_>?1\IL2?>79TAD:66?1\IL2=>99TAD:4294=7ZKN<2<5?RCE494=7ZKM<0<5?RCE4;437ZKM<283:3=PMK68255XECUF858?3^OI[H2>>99TAGQB4;437ZKMWD>0:==PMK]N0907;VGAS@:2611\IOYJ<7<b?RCE_L6<6=07;VGAS@:06j1\^DZJ_LMGAZGd3^XBXHQBOEG\Fa=PZ@^NSZGKTI]B`>QUA]OT[DJ[H^@2`>^ND@DS!UJM 1,2$VRRJ):%=-O\CHK5?]USD@H<7U][_FLG3>^T\V\HOo5W_BMQAZOINF<0TilPIed8\anXX{cfZh||inl24>^ceVGjfb|Yesqjkk773QnfS@gaosTfvvohf:1Sy=4Ydq;e>YXWQFEARQP0^]\Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pxg~y#@okd^e`g5(`k9$hcx`{[9_\CKBX::=TcRokd^2\KPRXpfx783?>659\[Z^KFDUTS<>P_^W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$~~zmlj-Nip~XzmUyyQnssgd[BHCW88TcRCZX^0\k47?=2UTSUBAM^]\5ZYX]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/Lcg`Zad8'idyczT8\]DJAY5:=UdSljk_1]LQQYg{6?2<?80:]\[]JIEVUT>RQPU1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dv4(un~l#@czx^PBIZTCWLDTJZH[10:b?ZYXPEDFSRQ<_^]V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$Aljk_fa`4+ad8'idyczT8\]DJAY5;>UdSljk_1]LQQYg{6<2<?75:]\[]JIEVUT8RQPU1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'DkohRil0/alqkr\0TULBIQ=25]l[dbcW9UDYYQwos>4:47112UTSUBAM^]\1ZYX]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~< }fvdw+WGJW[OLCXZPEO343>YXWQFEARQP6^]\Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`z8$yjzh{/bwqvZ`pn}Uxxlzj_GQN[C@c:$Ce=5o4_^][HKKXWV=TSR[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)JimnTknm?.fa3*firf}Q3QRIAD^003ZiXimnT<RAZT^zlv949982>7RQPXMLN[ZY?WVU^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,IdbcWni;"naznuY;YZAILV898RaPaef\4ZIR\Vrd~1<11040?ZYXPEDFSRQ6_^]V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#}{bmi,IhsW~xT~~zParpfcZAILV;9SbQBUY]2[j76911i`fQbel]dakY`mgoyenQlsup22>dkcVgnaRijn^rqmhYpam~c=o5mlj]nahY`mgU{~dcPwscst`tX~?l0naePmdo\c`hX|fz:86lck^ofiZabfV|<S<Qwsu30?gjlWdofSd`uu]ahjel9=1i`fQbel]lqqvr|Vhgcne<;bnh3>eheykyik5lusp\br`sWz~jxh=4deo5?aoi494<7iga<02=3>bnf5;:2:5kio>26;1<l`d7=>08;ekm8429?2nbb1?:>69gmk:6>7=0hd`316<4?aoi4825;6jfn=3::3=cag6:2:5kio>14;1<l`d7><08;ekm8749?2nbb1<<>69gmk:5<7=0hd`324<4?aoi4;<5;6jfn=04:2=cag694394dhl?6<813mce0?08;ekm8669?2nbb1=>>69gmk:4:7=0hd`332<4?aoi4:>556jfn=16>5803mce0>;16:fjj959>2nbb1:16:fjj939>2nbb1816:fjj919>2nbb1616:fjj9?9?2ndyy2?>99gkpr;99437iazt=32:==cg|~7=?07;emvp974611ocxz315<;?air|5;>255kotv?538?3me~x1?8>99gkpr;91437iazt=3::2=cg|~7=364dnww876902ndyy2=1?:8`jss4;8546j`uu>17;><lf0?:18:flqq:5=720hb{{<34=<>bh}}69;364dnww87>902ndyy2=9?58`jss4;437iazt=13:==cg|~7?<07;emvp955611ocxz332<;?air|59?2l5kotv?70<7611ocxz334<4?air|595;6j`uu>7:2=cg|~79394dnww83803me~x1917:flqq:?6>1ocxz39?78ahvsq8<0jdh`_fgmawgsg{Uym`hffn31?coagVmnbh|ntnp\pjv6;2lbjbQheogqeqiuW3T??h4fhdl[bcim{kcQy9^1/$]okagr+OB\J Fgmawgsg{*:8#9>7:djbjY`mgoymya}_w;\7Z~t|=1myab6;hlsqqYedb<0ahc`rx:8jbee}`fo>6``a:mvpussWkf`??5}alnlku]7U'xja#| v7]mklhn|'xja"]KP/UJ@@YWZ@G:4#|nmc9q`ZdnfViex;4re]fj2=ulVl|jy64re]okbod9;1yhR}{auwp[cjfozUx<?4rdqfpZdkcVxjakgio29qwq723zseoRhffn]ESCRX=88s?;??be9p}keXn`ldSKYIT^726}51$ocmcRijndpbpjtX~0U8 vmPaef\jbeXkfdxxofnu?3(fYfxyfbolzfoo]w}ucXiqcx1="l_`rshlef|`eeSywe^pbgm;7$jUj|}bfc`vjkkYsqyoT~img=1.`[dvwd`ijxdaa_u{saZqfka7; nQnpqnjgdrnggUu}kPweak95*dWhz{`dmnthmm[qwmV}yoe3?,b]b|lYflmxT{dj{h<11(fYfp`Uj~x}jr^uj`qn:9%iTmugPavwpawYpam~c1<"l_`zj[gstm{U|eizg=0.`[d~nWmkmRyfduj>21*dWhrbSdjPwhfwl82+kVkseR|zsdp\slbs`4;'oRowi^vzt`;7$jUjtdQxurgq[roc|a7: nQnxhq\pagsiV}bhyf265.`[d~n{V~oi~zPwhfwl82+kVkse~Q{ie]tmaro51&hSlvfs^vha`vX`nd0:#c^c{mvYs{}xiSzgkti?7(fYfp`yTxx}jr^uj`qn:<%iTmug|_u{sa86+kVida`aa_bnlgn;6$jUhcx`{_u{sa86+kVnjxlQlotlw[roc|a7:<!mPdddbqirX~hf~i0LcaoiPpwoio%iThd`Pwhfwl851$jUoecQxievk[d~n{4;'oRjfn^uj`qnXzhic1><#c^fjjZqnl}bT~img=76/gZbnfV}bhyfPw`ak964+kVnbbRyfduj\saeo5?>'oRjfn^uj`qnX{ic1?"l_emvpZtt|V|j`0>#c^flqqYpam~c1>8#c^gmegjbW{fdo~3?,b]fjddkmVxxxR}vnb?2(fYbz{eySd`eebvjkkYsqyo6<!mPesplvZoiblieb`Ptxrf[d~n{4:'oRk}rnp\mklbk}cdbRzvpd]qefn:8%iTi|`r^kmn`esafdTxt~j_sf`l86+kVoy~b|PiohfgqohfV~r|hQxabj>4)eXm{xd~RgajdawmjhX|pznSzjlh<2/gZcuzfxTecdjcukljZr~xlU|~nf20-a\bdkndp7}ezjx7.`[cskdVlgmj}Prrv\rdj:9%iTdl}PamolwqYbey~r1="l_icp[djjgz~Tjxbc=1.`[mgtWhrbSl|zsdp>4)eX`hyTmugPavwpaw;7$jUcm~Qnxh]aqvcu59&hSeo|_`zj[wbXkakebhb20-a\lduXiqcT~x}jr<2/gZnf{VkseRy}_bjbjkck59&hSeo|_`zj[rstm{7; nQgar]b|luX|mkm0>#c^jbwZgazUhh}{=1.`[mgtWhrbRzfd<2/gZnf{Vkse~Q{kdgs95*dWakxSlvfs^voevr:8%iTdl}Paykp[qtbims6=!mPh`q\e}otW}y~o3?,b]kevYfp`yTxx}jr<2/gZnf{Vhjof{=1.`[mgtWmkmRm`uov>4)eX`hyThlzn_bmvjquXiqcx1="l_icp[agsiVidycz|_sc`l86+kVbjRjnt`]`kphs{Vxooe3?,b]kevYci}kTob{atr]tefn:8%iTdl}Pd`vb[firf}yT{img=1.`[mgtWmkmRm`uovp[rtd`4:'oRfns^kmpZekc4:'oRfns^obwqcuWjo6<!mPh`q\i`knf`~Tjdbj=1.`[mgtWf|n~kb`w<2/gZnf{VzycjQil`ep[d~n{4:'oRfns^rqkbYadhmxSolh<2/gZnf{VzycjQil`ep[wbd`4:'oRfns^rqkbYadhmxSzolh<2/gZnf{VzycjQil`ep[rbd`4:'oRfns^rqkbYadhmxSz|lh<2/gZnf{VxoSio{a^alqkr:8%iTdl}Pre]qwq;7$jUcm~Q}su?2(fYoizUx`lxj_bg>4)eX`hyT}{=1.`[mgtW|doihcov?3(fYoizU}magk=1.`[mgtW~xTmne20-a\lduX{UomyoPcnwmp86+kVbjRy}_sqw95*dW`g{`hcjnucwmjhX|pzn1="l_hosh`kbf}keb`Ptxrf[d~n{4;'oRgbpmgnakrf|`eeSywe^pbgm;6$jUba}bjmdlweqohfV~r|hQ}dbj>5)eXadzgi`kat`vjkkYsqyoT{lmg=0.`[lkwdlgnbyo{inl\p|vbW~nhd0?#c^knticjmg~jxdaa_u{saZquka7: nQfnhv\swYwf}xTzlb20-a\mkrbzokhiRzvpd?3(fYjmdeyuRzvpd?2(fYjaoUmeakPn`of9GjffbY~d`h,b]nwbiiWkg1<"l_nrwmho}i}cdbRc`dd?3(fYh~lxm`byPlnu>4)eXx{ogcljPl`vfjf:8%iT|kco`f\v`at58&hS}|fm^djbjYsqyo69<<w37.`[uthoVof|ywPtipfwmYf{zoyxRxnl<6/gZvugnUna}zv_ujqavnXizyn~yQyam]b|lu:9989 nQrne\ahvsqV~c~h}g_`qpawrX~hfT~lmg=0216)eXx{elShctx]wlwct`Vkxh|{_wco[wbd`4;;>?"l_qplcZcjx}sTxe|jsi]bwvcu|V|j`Rynci?2474+kVzycjQjmqvz[qnumzbTm~}jru]ueiYpljb6==<=,b]svjaXmdzuRzgrdqk[dutm{~TzlbPwsak9465:%iT|ah_dosp|Ys`{oxdR`jg`vf[sgk5<&hS}|`g^gntqX|pzn1="l_qplcZcjx}sTxt~j_`zjw86+kVzycjQjmqvz[qwmVxjoe3?,b]svjaXmdzuRzvpd]q`fn:8%iT|ah_dosp|YsqyoT{lmg=1.`[uthoVof|ywPtxrf[rbd`4:'oR~}of]fiur~W}s{iRy}ci?3(fYwzfmTjxbc_ujqavnXizyn~yQyam?654*dWyxdkRhzlm]wlwct`Vkxh|{_wco[d~n{4;;>>"l_qplcZ`rdeUdk|h^cpw`tsWkgSolh<3366*dWyxdkRhzlm]wlwct`Vkxh|{_wco[wbd`4;;>>"l_qplcZ`rdeUdk|h^cpw`tsWkgSzolh<3366*dWyxdkRhzlm]wlwct`Vkxh|{_wco[rbd`4;;>>"l_qplcZ`rdeUdk|h^cpw`tsWkgSz|lh<3366*dWyxdkRhzlm]wlwct`Vdnklzj_wco9077$jU{~biPftno[qwm4:'oR~}of]eqijX|pznSlvfs<2/gZvugnUmyabPtxrf[wgd`4:'oR~}of]eqijX|pznSjlh<2/gZvugnUmyabPtxrf[rgd`4:'oR~}of]eqijX|pznSzjlh<2/gZvugnUmyabPtxrf[rtd`4:'oR|nci]w}uc:8%iT~iQkauc\gjsi|V}bhyf211.`[wbXllzd0;>2-a\vaYazl{6=!mPre]sjqtX`nd07#c^pggmYsqyo6<!mPrde\wiodmVgdhhQnxhq>4)eXzlmTagle^ol``Yuijb6<!mPrde\wiodmVgdhhQ}dbj>4)eXzlmTagle^ol``Ypijb6<!mPrde\wiodmVgdhhQxdbj>4)eXzlmTagle^ol``Ypzjb6<!mPsxl`lwiiasoyS~zngd?1(fYrfmoyjaax_mmt95*dW|ynSnabmnl\kscunee|1="l_tqf[fijefdTycjjrgnls86+kVxiRjjf`wopZub|}cek~3?,b]vw`Ycg|~T~~z21-a\qvcXmji6<!mPurg\afeXiqcx1="l_tqf[`edW{khd0>#c^wpaZcdkVxooe3?,b]vw`YbkjU|mnf20-a\qvcXmjiT{img=1.`[pubWlihSz|lh<2/gZstmVofnhjkee]qab;7$jU~hQiigm22Z`kiny6<!mPurg\br`sWmkmRm`uov>5)eX~hfbhRb`w<2/gZqfkaUu}k20-a\saeoW}s{i0>#c^uq[delWee|1="l_vp\`drfWje~byQxievk946+kV}ySikti?657*dW~xThh~{h^c{mv;68;>'oRy}_egspmYuijb6=;"l_vp\``vs`Vxooe3>036/gZquWmo{xeQxabj>53*dW~xThh~{h^uggm;68;>'oRy}_egspmYpzjb6=;"l_vp\bwcv58&hSz|Ppovq[roc|a72 nQxr^rmpwYpam~cSlvfs<33(fYpzVzexQxievk[wgd`4>'oRy}_qlwvZqnl}bT~img=02/gZquWyd~Ryfduj\sdeo5=&hSz|Ppovq[roc|aU|hnf211.`[rtXxg~ySzgkti]tvfn:<%iT{Q}errljvcXdh~nbnw21-a\sweoW}s{i0>r2b9p}keXn`ldSKYIT^726}51$ocmcRijndpbpjtX~0U8 vsm;vp\flhXkg~y96y}_dl;?rtXdfmbo<<4ws]ppdrr{Vlgmj}PsrCDu10;2JKt9<>:G87>4}T1908mo4>f5827634?>09>l<={o1b=?7<f:kj6;5+3`597d4<uZ2n6>om:0d7>454=:=<6?<n5b9P5`7=<8<1<7?<34143?45i<l0_5k540494?74;<9<;7<=a708`146290:6<u\9180eg<6n=0:?>;<76816d3e3^9>44?:082>c4|[0:1?ll51g695652;>=1>?o:b:&0<<<6m:1]?l652zw2ag<63|;no7>4}%3e1?4>3k>9=7>54d8b2?`6sA93;6*=2d8764=]?:09w<m51g8~ 6g12=;:7)99:500?!>a2=897)<=5;38 7432:kh7d=j0;29 4`02:nm7c?i6;28?l5cm3:1(<h8:2fe?k7a>3;07d=kd;29 4`02:nm7c?i6;08?l5ck3:1(<h8:2fe?k7a>3907d=kb;29 4`02:nm7c?i6;68?l5ci3:1(<h8:2fe?k7a>3?07d=k8;29 4`02:nm7c?i6;48?l5c?3:1(<h8:2fe?k7a>3=07d=k6;29 4`02:nm7c?i6;:8?l5c=3:1(<h8:2fe?k7a>3307d=k4;29 4`02:nm7c?i6;c8?l5c;3:1(<h8:2fe?k7a>3h07d=k2;29 4`02:nm7c?i6;a8?l5c93:1(<h8:2fe?k7a>3n07d=k0;29 4`02:nm7c?i6;g8?l5dn3:1(<h8:2fe?k7a>3l07d=ld;29 4`02:nm7c?i6;33?>o4kj0;6)?i7;1gb>h6n?0:=65f3b`94?"6n>08hk5a1g4957=<a:ij6=4+1g597a`<f8l=6<=4;h1`=?6=,8l<6>ji;o3e2?7332c8o54?:%3e3?5cn2d:j;4>5:9j7f1=83.:j:4<dg9m5c0=9?10e>m9:18'5c1=;ml0b<h9:058?l5d=3:1(<h8:2fe?k7a>3;376g<c583>!7a?39oj6`>f782=>=n;l=1<7*>f680`c=i9o<1=l54i2g5>5<#9o=1?ih4n0d5>4d<3`9n97>5$0d4>6ba3g;m:7?l;:k0a1<72-;m;7=kf:l2b3<6l21b?h=50;&2b2<4lo1e=k851d98m6c5290/=k953ed8j4`128l07d=j1;29 4`02:nm7c?i6;03?>o4l00;6)?i7;1gb>h6n?09=65f3bg94?"6n>08hk5a1g4967=<a:i86=4+1g597a`<f8l=6?=4;h1ab?6=3`>9<7>5;h611?6=3`>:n7>5;n631?6=,8l<69>;;o3e2?6<3f>;?7>5$0d4>1633g;m:7?4;n636?6=,8l<69>;;o3e2?4<3f>;=7>5$0d4>1633g;m:7=4;n634?6=,8l<69>;;o3e2?2<3f9mj7>5$0d4>1633g;m:7;4;n1e`?6=,8l<69>;;o3e2?0<3f9mo7>5$0d4>1633g;m:794;n1ef?6=,8l<69>;;o3e2?><3f9mm7>5$0d4>1633g;m:774;n1e=?6=,8l<69>;;o3e2?g<3f9m47>5$0d4>1633g;m:7l4;n1e3?6=,8l<69>;;o3e2?e<3f9m:7>5$0d4>1633g;m:7j4;n1e1?6=,8l<69>;;o3e2?c<3f9m87>5$0d4>1633g;m:7h4;n1e6?6=,8l<69>;;o3e2?7732e8j<4?:%3e3?27<2d:j;4>1:9l7c6=83.:j:4;059m5c0=9;10c>ki:18'5c1=<9>0b<h9:018?j5bm3:1(<h8:527?k7a>3;?76a<ee83>!7a?3>;86`>f7821>=h;li1<7*>f68741=i9o<1=;54o2ga>5<#9o=18=:4n0d5>41<3f9nm7>5$0d4>1633g;m:7?7;:m0a<<72-;m;7:?4:l2b3<6121d8=m50;&2b2<38=1e=k851`98k16e290/=k954168j4`128h07b:?a;29 4`02=:?7c?i6;3`?>i3800;6)?i7;630>h6n?0:h65`41:94?"6n>0?<95a1g495`=<g=:<6=4+1g59052<f8l=6<h4;n632?6=,8l<69>;;o3e2?4732e8jh4?:%3e3?27<2d:j;4=1:9l7c5=83.:j:4;059m5c0=:;10c>k7:18'5c1=<9>0b<h9:318?j26;3:17b:?d;29?g5f=3:1=7>50z&16`<4011C?l=4H2:4?j7a;3:17pl<a583>4<729q/>?k519c8L6g43A93;6a>8883>>{e:??1<7:50;2x 74b282>7E=n3:J0<2=#90k146g84;29?l?62900e<h6:188k4`e2900qo<l6;290?6=8r.9>h4>849K7d5<@:2<7)?6a;:8m22=831b5<4?::k2b<<722e:jo4?::a6f3=83>1<7>t$30f>4>23A9j?6F<869'5<g=02c<87>5;h;2>5<<a8l26=44o0da>5<<uk9<<7>54;294~"5:l0:4>5G3`18L6>03-;2m7=4i6694?=n0m0;66g61;29?j7aj3:17pl<7`83>1<729q/>?k51978L6g43A93;6F81:&2a<<5:m1b;94?::k:5?6=3`;m57>5;n3ef?6=3th84=4?:583>5}#:;o1=5;4H2c0?M5??2B<=6*>e8816a=n?=0;66g61;29?l7a13:17b?ib;29?xd4?:0;694?:1y'67c=91?0D>o<;I1;3>N092.:i44=2e9'5<g=02c<87>5;h;2>5<<a8l26=44o0da>5<<uk9<h7>53;294~"5:l0:4?5G3`18L6>03A=:7)?j9;01`>"61h087d9;:188m<7=831d=kl50;9~f6>429086=4?{%01a?7?:2B8m>5G3958L27<,8o26?<k;%3:e?5<a>>1<75f9083>>i6nk0;66sm36094?2=83:p(?<j:0:6?M5f;2B84:5G709'5`?=:;n0(<7n:99j31<722c2=7>5;h3e=?6=3f;mn7>5;|`032<72=0;6=u+23g95=3<@:k87E=77:&2=d<?3`=?6=44i8394?=n9o31<75`1g`94?=zj:==6=4;:183!45m3;396F<a29K7=1<,83j655f7583>>o>93:17d?i9;29?j7aj3:17pl<7b83>6<729q/>?k51908L6g43A93;6F81:&2a<<5:m1/=4o53:k40?6=3`3:6=44o0da>5<<uk9<57>54;294~"5:l0:485G3`18L6>03-;2m764i6694?=n180;66g>f883>>i6nk0;66sm39094?5=83:p(?<j:0:1?M5f;2B84:5G709'5`?=:;n0(<7n:29j31<722c2=7>5;n3ef?6=3th8;<4?:583>5}#:;o1=5;4H2c0?M5??2B<=6*>e8816a=#90k146g84;29?l?62900e<h6:188k4`e2900qo=<d;291?6=8r.9>h4>869K7d5<@:2<7)?6a;18m22=831b;84?::k:5?6=3`;mo7>5;n3ef?6=3th8?n4?:483>5}#:;o1=594H2c0?M5??2.:5l4<;h57>5<<a>?1<75f9083>>o6nj0;66a>fc83>>{e;:h1<7;50;2x 74b282<7E=n3:J0<2=#90k1?6g84;29?l122900e4?50;9j5ce=831d=kl50;9~f65f290>6=4?{%01a?7??2B8m>5G3958 4?f2:1b;94?::k41?6=3`3:6=44i0d`>5<<g8li6=44}c10=?6==3:1<v*=2d82<2=O;h90D>68;%3:e?5<a>>1<75f7483>>o>93:17d?ic;29?j7aj3:17pl<3983>0<729q/>?k51958L6g43A93;6*>9`80?l132900e:;50;9j=4<722c:jn4?::m2bg<722wi?>850;794?6|,;8n6<68;I1b7>N40>1/=4o53:k40?6=3`=>6=44i8394?=n9oi1<75`1g`94?=zj:9>6=4::183!45m3;3;6F<a29K7=1<,83j6>5f7583>>o0=3:17d7>:188m4`d2900c<hm:188yg54<3:197>50z&16`<60>1C?l=4H2:4?!7>i390e::50;9j30<722c2=7>5;h3eg?6=3f;mn7>5;|`076<72<0;6=u+23g95=1<@:k87E=77:&2=d<43`=?6=44i6794?=n180;66g>fb83>>i6nk0;66sm32094?3=83:p(?<j:0:4?M5f;2B84:5+18c97>o0<3:17d9::188m<7=831b=km50;9l5cd=831vn>=>:186>5<7s-89i7?77:J0e6=O;1=0(<7n:29j31<722c<97>5;h;2>5<<a8lh6=44o0da>5<<uk98<7>55;294~"5:l0:4:5G3`18L6>03-;2m7=4i6694?=n?<0;66g61;29?l7ak3:17b?ib;29?xd4:o0;684?:1y'67c=91=0D>o<;I1;3>"61h087d9;:188m23=831b5<4?::k2bf<722e:jo4?::a77c=83?1<7>t$30f>4>03A9j?6F<869'5<g=;2c<87>5;h56>5<<a0;1<75f1ga94?=h9oh1<75rb20g>5<2290;w)<=e;3;3>N4i:1C?594$0;b>6=n?=0;66g85;29?l?62900e<hl:188k4`e2900qo==b;291?6=8r.9>h4>869K7d5<@:2<7)?6a;18m22=831b;84?::k:5?6=3`;mo7>5;n3ef?6=3th8>l4?:483>5}#:;o1=594H2c0?M5??2.:5l4<;h57>5<<a>?1<75f9083>>o6nj0;66a>fc83>>{e;;31<7;50;2x 74b282<7E=n3:J0<2=#90k1?6g84;29?l122900e4?50;9j5ce=831d=kl50;9~f64?290>6=4?{%01a?7??2B8m>5G3958 4?f2:1b;94?::k41?6=3`3:6=44i0d`>5<<g8li6=44}c113?6==3:1<v*=2d82<2=O;h90D>68;%3:e?5<a>>1<75f7483>>o>93:17d?ic;29?j7aj3:17pl<2783>0<729q/>?k51958L6g43A93;6*>9`80?l132900e:;50;9j=4<722c:jn4?::m2bg<722wi??;50;794?6|,;8n6<68;I1b7>N40>1/=4o53:k40?6=3`=>6=44i8394?=n9oi1<75`1g`94?=zj:8?6=4::183!45m3;3;6F<a29K7=1<,83j6>5f7583>>o0=3:17d7>:188m4`d2900c<hm:188yg55;3:197>50z&16`<60>1C?l=4H2:4?!7>i390e::50;9j30<722c2=7>5;h3eg?6=3f;mn7>5;|`067<72<0;6=u+23g95=1<@:k87E=77:&2=d<43`=?6=44i6794?=n180;66g>fb83>>i6nk0;66sm35194?3=83:p(?<j:0:4?M5f;2B84:5+18c97>o0<3:17d9::188m<7=831b=km50;9l5cd=831vn>:=:186>5<7s-89i7?77:J0e6=O;1=0(<7n:29j31<722c<97>5;h;2>5<<a8lh6=44o0da>5<<uk9?=7>55;294~"5:l0:4:5G3`18L6>03-;2m7=4i6694?=n?<0;66g61;29?l7ak3:17b?ib;29?xd4<90;684?:1y'67c=91=0D>o<;I1;3>"61h087d9;:188m23=831b5<4?::k2bf<722e:jo4?::a76`=83?1<7>t$30f>4>03A9j?6F<869'5<g=;2c<87>5;h56>5<<a0;1<75f1ga94?=h9oh1<75rb21f>5<2290;w)<=e;3;3>N4i:1C?594$0;b>6=n?=0;66g85;29?l?62900e<hl:188k4`e2900qo=<7;291?6=8r.9>h4>869K7d5<@:2<7)?6a;18m22=831b;84?::k:5?6=3`;mo7>5;n3ef?6=3th8>n4?:483>5}#:;o1=594H2c0?M5??2.:5l4<;h57>5<<a>?1<75f9083>>o6nj0;66a>fc83>>{e;;;1<7;50;2x 74b282<7E=n3:J0<2=#90k1?6g84;29?l122900e4?50;9j5ce=831d=kl50;9~f647290>6=4?{%01a?7??2B8m>5G3958 4?f2:1b;94?::k41?6=3`3:6=44i0d`>5<<g8li6=44}c15<?6=jo096;?tH2:4?!45m39i46T83;fx54<a2;:1>k4>a;31>46=:808<7?m:0f95`<493w/;?4=;h023?6=,8l<6??9;o3e2?6<3`8;j7>5$0d4>76b3g;m:7>4;h1;b?6=,8l<6>6j;o3e2?6<3`93h7>5$0d4>6>b3g;m:7?4;h1;g?6=,8l<6>6j;o3e2?4<3`93n7>5$0d4>6>b3g;m:7=4;h63>5<#9o=1?k5a1g494>=n;l0;6)?i7;1e?k7a>3;07d=k:18'5c1=;o1e=k852:9j7f<72-;m;7=i;o3e2?5<3`9i6=4+1g597c=i9o<1865f3`83>!7a?39m7c?i6;78?l5>290/=k953g9m5c0=>21b?54?:%3e3?5a3g;m:794;h14>5<#9o=1?k5a1g49<>=nl?0;6)?i7;f6?k7a>3:07dj;:18'5c1=l<1e=k851:9j`6<72-;m;7j:;o3e2?4<3`n96=4+1g59`0=i9o<1?65fd083>!7a?3n>7c?i6;68?lb7290/=k95d49m5c0==21boh4?:%3e3?b23g;m:784;hag>5<#9o=1h85a1g493>=nkj0;6)?i7;f6?k7a>3207dmm:18'5c1=l<1e=k859:9jgd<72-;m;7j:;o3e2?g<3`i26=4+1g59`0=i9o<1n65fc983>!7a?3n>7c?i6;a8?le0290/=k95d49m5c0=l21bo;4?:%3e3?b23g;m:7k4;ha6>5<#9o=1h85a1g49b>=nk:0;6)?i7;f6?k7a>3;;76gl2;29 4`02m?0b<h9:038?le6290/=k95d49m5c0=9;10en>50;&2b2<c=2d:j;4>3:9jfc<72-;m;7j:;o3e2?7332cii7>5$0d4>a3<f8l=6<;4;h`g>5<#9o=1h85a1g4953=<aki1<7*>f68g1>h6n?0:;65fbc83>!7a?3n>7c?i6;3;?>oei3:1(<h8:e78j4`128307djk:18'5c1=l<1e=k851`98mae=83.:j:4k5:l2b3<6j21bho4?:%3e3?b23g;m:7?l;:kge?6=,8l<6i;4n0d5>4b<3`n26=4+1g59`0=i9o<1=h54ie:94?"6n>0o96`>f782b>=nl>0;6)?i7;f6?k7a>38;76glf;29 4`02m?0b<h9:338?le3290/=k95d49m5c0=:;10eo750;&2b2<c=2d:j;4=3:9j64?=83.:j:4=199m5c0=821b><=50;&2b2<59;1e=k850:9j7<2=83.:j:4<929m5c0=821b?4<50;&2b2<41:1e=k851:9j7<7=83.:j:4<929m5c0=:21b?4>50;&2b2<41:1e=k853:9j1f<72-;m;7;m;o3e2?6<3`?j6=4+1g591g=i9o<1=65f5883>!7a?3?i7c?i6;08?l3?290/=k955c9m5c0=;21b9:4?:%3e3?3e3g;m:7:4;h75>5<#9o=19o5a1g491>=n=<0;6)?i7;7a?k7a>3<07d;;:18'5c1==k1e=k857:9j16<72-;m;7;m;o3e2?><3`li6=4+1g59bd=i9o<1<65ff883>!7a?3lj7c?i6;38?l`?290/=k95f`9m5c0=:21bj:4?:%3e3?`f3g;m:7=4;hd5>5<#9o=1jl5a1g490>=nn<0;6)?i7;db?k7a>3?07dh<:18'5c1=nh1e=k856:9jb7<72-;m;7hn;o3e2?1<3`l:6=4+1g59bd=i9o<1465ff183>!7a?3lj7c?i6;;8?lca290/=k95f`9m5c0=i21bih4?:%3e3?`f3g;m:7l4;hgg>5<#9o=1jl5a1g49g>=nmj0;6)?i7;db?k7a>3n07dkm:18'5c1=nh1e=k85e:9jad<72-;m;7hn;o3e2?`<3`o36=4+1g59bd=i9o<1==54id594?"6n>0mm6`>f7825>=nm?0;6)?i7;db?k7a>3;976gj5;29 4`02ok0b<h9:018?lc3290/=k95f`9m5c0=9=10eh=50;&2b2<ai2d:j;4>5:9ja7<72-;m;7hn;o3e2?7132cn=7>5$0d4>cg<f8l=6<94;hg3>5<#9o=1jl5a1g495==<aml1<7*>f68ee>h6n?0:565f11094?"6n>0mm6`>f782e>=n99;1<7*>f68ee>h6n?0:n65f11294?"6n>0mm6`>f782g>=nno0;6)?i7;db?k7a>3;o76gie;29 4`02ok0b<h9:0g8?l`c290/=k95f`9m5c0=9o10ekm50;&2b2<ai2d:j;4=0:9jb1<72-;m;7hn;o3e2?4632cn57>5$0d4>cg<f8l=6?<4;hff>5<#9o=1jl5a1g4966=<a>o1<75f16f94?=n0=0;66g>7g83>>o6lo0;66g>dd83>>i6=90;6)?i7;37b>h6n?0;76a>4d83>!7a?3;?j6`>f782?>i6<m0;6)?i7;37b>h6n?0976a>4b83>!7a?3;?j6`>f780?>i6<k0;6)?i7;37b>h6n?0?76a>4`83>!7a?3;?j6`>f786?>i6<10;6)?i7;37b>h6n?0=76a>4683>!7a?3;?j6`>f784?>i6<?0;6)?i7;37b>h6n?0376a>4483>!7a?3;?j6`>f78:?>i6<=0;6)?i7;37b>h6n?0j76a>4283>!7a?3;?j6`>f78a?>i6<;0;6)?i7;37b>h6n?0h76a>4083>!7a?3;?j6`>f78g?>i6<90;6)?i7;37b>h6n?0n76a>3g83>!7a?3;?j6`>f78e?>i6;m0;6)?i7;37b>h6n?0:<65`12a94?"6n>0:8k5a1g4954=<g89i6=4+1g5951`<f8l=6<<4;n30e?6=,8l<6<:i;o3e2?7432e:?44?:%3e3?73n2d:j;4>4:9l56>=83.:j:4>4g9m5c0=9<10c<=8:18'5c1=9=l0b<h9:048?j74>3:1(<h8:06e?k7a>3;<76a>3483>!7a?3;?j6`>f782<>=h9:>1<7*>f6820c=i9o<1=454o074>5<#9o=1=9h4n0d5>4g<3f;>:7>5$0d4>42a3g;m:7?m;:m210<72-;m;7?;f:l2b3<6k21d=8:50;&2b2<6<o1e=k851e98k434290/=k9515d8j4`128o07b?:2;29 4`028>m7c?i6;3e?>i6=80;6)?i7;37b>h6n?09<65`15;94?"6n>0:8k5a1g4964=<g89n6=4+1g5951`<f8l=6?<4;n307?6=,8l<6<:i;o3e2?4432e:;84?:%3e3?70<2d:j;4?;:m236<72-;m;7?84:l2b3<632e:;?4?:%3e3?70<2d:j;4=;:m234<72-;m;7?84:l2b3<432e:;=4?:%3e3?70<2d:j;4;;:m22c<72-;m;7?84:l2b3<232e::i4?:%3e3?70<2d:j;49;:m22f<72-;m;7?84:l2b3<032e::o4?:%3e3?70<2d:j;47;:m22d<72-;m;7?84:l2b3<>32e::44?:%3e3?70<2d:j;4n;:m22=<72-;m;7?84:l2b3<e32e:::4?:%3e3?70<2d:j;4l;:m223<72-;m;7?84:l2b3<c32e::84?:%3e3?70<2d:j;4j;:m221<72-;m;7?84:l2b3<a32e::?4?:%3e3?70<2d:j;4>0:9l537=83.:j:4>759m5c0=9810c<8?:18'5c1=9>>0b<h9:008?j72n3:1(<h8:057?k7a>3;876a>5d83>!7a?3;<86`>f7820>=h9<n1<7*>f68231=i9o<1=854o07`>5<#9o=1=::4n0d5>40<3f;>n7>5$0d4>4133g;m:7?8;:m21d<72-;m;7?84:l2b3<6021d=8750;&2b2<6?=1e=k851898k41d290/=k951668j4`128k07b?8b;29 4`028=?7c?i6;3a?>i6?h0;6)?i7;340>h6n?0:o65`16;94?"6n>0:;95a1g495a=<g8=36=4+1g59522<f8l=6<k4;n343?6=,8l<6<9;;o3e2?7a32e:;;4?:%3e3?70<2d:j;4=0:9l53c=83.:j:4>759m5c0=:810c<8<:18'5c1=9>>0b<h9:308?j7203:1(<h8:057?k7a>38876a=0983>!7a?38;;6`>f783?>i58?0;6)?i7;033>h6n?0:76a=0483>!7a?38;;6`>f781?>i58=0;6)?i7;033>h6n?0876a=0283>!7a?38;;6`>f787?>i58;0;6)?i7;033>h6n?0>76a=0083>!7a?38;;6`>f785?>i5890;6)?i7;033>h6n?0<76a>fg83>!7a?38;;6`>f78;?>i5:;0;66a62;29?g5f<3:1=7>50z&16`<60h1C?l=4H2:4?j7?13:17pl;1883>=6=83:p(?<j:0dg?M5f;2B84:5U728f42=9<026l4>6;34>4>=900i6n4k:d81f?472t.:j?4;169m54g=82d:>n4?;%3:6?3<,838685+18691>"61<0>7)?66;78 4?02<1/=4655:&2=<<23-;2n7;4$0;`>0=#90n196*>9d86?!7>n3?0(<o?:49'5d7==2.:m?4:;%3b7?3<,8k?685+1`791>"6i?0>7)?n7;78 4g?2<1/=l755:&2ed<23-;jn7;4$0c`>0=#9hn196*>ad86?!7fn3?0(<l?:49'5g7==2.:n?4:;%3a7?3<,8h?685+1c791>"6j?0>7)?m7;78 4d?2<1/=o755:&2fd<23-;in7;4$0``>0=#9kn196*>bd86?!7en3?0(<m?:49'5f7==2.:o?4:;%3`7?3<,8i?685+1b791>"6k?0>7)?l7;78 4e?2<1/=n755:&2gd<23-;hn7;4$0a`>0=#9jn196*>cd86?!7dn3?0(<j?:49'5a7==2.:h?4:;%3g7?3<,8n?685+1e791>"6l?0>7)?k7;78 4b?2<1/=i755:&2`d<23-;on7:4$0f`>1=#9mn1=k>4$0df>7443-8;577;;o03f?433g8;o7>4$33f>76c3-8:j7<?d:&163<082.9>:4<8`9'67g=<2.9>o4;;%1:a?47i2.85k4=0`9m7d6=82d8m<4=4:&164<6081b4>4?::k;2?6=3`;<i7>5;h3;4?6=3`8:<7>5;h025?6=3`8:87>5H30;?>o59<0;6E<=8:9j64g=831b><l50;9j64e=831b><j50;9j03<72-;m;7::;o3e2?6<3`>?6=4+1g5900=i9o<1=65f4283>!7a?3>>7c?i6;08?l25290/=k95449m5c0=;21b8k4?:%3e3?223g;m:7:4;h6f>5<#9o=1885a1g491>=n<m0;6)?i7;66?k7a>3<07d:l:18'5c1=<<1e=k857:9j0g<72-;m;7::;o3e2?><3`>j6=4+1g5900=i9o<1565f4883>!7a?3>>7c?i6;c8?l2?290/=k95449m5c0=j21b8:4?:%3e3?223g;m:7m4;h62>5<#9o=1885a1g49`>=n=;0;6)?i7;72?k7a>3:0D?<7;:k64?6=,8l<68?4n0d5>4=O:;207d;i:18'5c1==l1e=k850:J16==<a<n1<7*>f686a>h6n?0:7E<=8:9j20<72-;m;78;;o3e2?6<3`<86=4+1g5921=i9o<1=65f6383>!7a?3<?7c?i6;08?l06290/=k95659m5c0=;21b:h4?:%3e3?033g;m:7:4;h4g>5<#9o=1:95a1g491>=n>j0;6)?i7;47?k7a>3<07d8m:18'5c1=>=1e=k857:9j2d<72-;m;78;;o3e2?><3`<26=4+1g5921=i9o<1565f6983>!7a?3<?7c?i6;c8?l00290/=k95659m5c0=j21b:;4?:%3e3?033g;m:7m4;h43>5<#9o=1:95a1g49`>=n1l0;6)?i7;;g?k7a>3:07d7l:18'5c1=1m1e=k851:9j=g<72-;m;77k;o3e2?4<3`3j6=4+1g59=a=i9o<1?65f9883>!7a?33o7c?i6;68?l??290/=k959e9m5c0==21bm:4?:%3e3??c3g;m:784;hc5>5<#9o=15i5a1g493>=ni<0;6)?i7;;g?k7a>3207do;:18'5c1=1m1e=k859:9je6<72-;m;77k;o3e2?g<3`k96=4+1g59=a=i9o<1n65fa083>!7a?33o7c?i6;a8?lg7290/=k959e9m5c0=l21b5k4?:%3e3??c3g;m:7k4;h;4>5<#9o=15i5a1g49b>=nio0;6)?i7;cf?k7a>3:07dok:18'5c1=il1e=k851:9jef<72-;m;7oj;o3e2?4<3`ki6=4+1g59e`=i9o<1?65fa`83>!7a?3kn7c?i6;68?lg>290/=k95ad9m5c0==21bn54?:%3e3?gb3g;m:784;h`4>5<#9o=1mh5a1g493>=nj?0;6)?i7;cf?k7a>3207dl::18'5c1=il1e=k859:9jf1<72-;m;7oj;o3e2?g<3`h86=4+1g59e`=i9o<1n65fb383>!7a?3kn7c?i6;a8?ld6290/=k95ad9m5c0=l21bn=4?:%3e3?gb3g;m:7k4;hc;>5<#9o=1mh5a1g49b>=n99?1<7*>f68241=i9o<1<65f11194?"6n>0:<95a1g495>=n9921<7*>f68242=i9o<1<65f11494?"6n>0:<:5a1g495>=h98:1<7*>f6824c=i9o<1<65`11g94?"6n>0:<k5a1g495>=h99n1<7*>f6824c=i9o<1>65`11a94?"6n>0:<k5a1g497>=h99h1<7*>f6824c=i9o<1865`11c94?"6n>0:<k5a1g491>=h9831<7*>f6824c=i9o<1:65`10:94?"6n>0:<k5a1g493>=h98=1<7*>f6824c=i9o<1465`10494?"6n>0:<k5a1g49=>=h98?1<7*>f6824c=i9o<1m65`10694?"6n>0:<k5a1g49f>=h9891<7*>f6824c=i9o<1o65`10094?"6n>0:<k5a1g49`>=h98;1<7*>f6824c=i9o<1i65`11;94?"6n>0:<k5a1g49b>=h9;81<7*>f68264=i9o<1<65`13294?"6n>0:><5a1g495>=h98l1<7*>f68264=i9o<1>65`10g94?"6n>0:><5a1g497>=h98n1<7*>f68264=i9o<1865`10a94?"6n>0:><5a1g491>=h9;h1<7*>f68264=i9o<1:65`13c94?"6n>0:><5a1g493>=h9;31<7*>f68264=i9o<1465`13:94?"6n>0:><5a1g49=>=h9;=1<7*>f68264=i9o<1m65`13494?"6n>0:><5a1g49f>=h9;?1<7*>f68264=i9o<1o65`13694?"6n>0:><5a1g49`>=h9;91<7*>f68264=i9o<1i65`10`94?"6n>0:><5a1g49b>=h9;l1<7*>f6826`=i9o<1<65`13f94?"6n>0:>h5a1g495>=h9:81<7*>f68274=i9o<1<65`12294?"6n>0:?<5a1g495>=n;1l1<7*>f680<`=i9o<1<6F=2998m6>c290/=k9539g8j4`1281C>?64;h1;g?6=,8l<6>6j;o3e2?4<3`93n7>5$0d4>6>b3g;m:7=4;h1:`?6=,8l<6>7l;o3e2?6<@;8376g<9c83>!7a?392o6`>f782?M45021b?4o50;&2b2<41j1e=k852:J16==<a:326=4+1g597<e<f8l=6>5G23:8?l5>03:1(<h8:2;`?k7a>3>07d=67;29 4`02:3h7c?i6;78?l5>>3:1(<h8:2;`?k7a>3<07d=65;29 4`02:3h7c?i6;58?xu40k0;68uQ39`8917>2:3370:>9;1:3>;390085;5240;97<3<uz>;6=4={_63?82613<>7p}<e;296~X4m27?=4493:p7a<72;qU?i5240;927=z{:i1<7<t^2a8917>2?;0q~=m:181[5e34>:578j;|q0e?6=:rT8m63;1885`>{t;00;6?uQ389>04?=>j1v>650;0xZ6><5=;26;l4}r14>5<5sW9<70:>9;4b?xuc>3:1>vPk6:?75<<6811vi:50;0xZa2<5=;26lh4}rf0>5<5sWn870:>9;cg?xuc:3:1>vPk2:?75<<fk2wxh<4?:3y]`4=:<831mo5rse294?4|Vm:019?6:`c8yveb2909wSmj;<62=?g>3tyhh7>52z\``>;3900i46s|cb83>7}Ykj168<75b69~wfd=838pRnl4=53:>4613tyhm7>52z\`e>;3900i:6s|c883>7}Yk0168<75b49~wf>=838pRn64=53:>g2<uzi<6=4={_a4?82613h87p}l6;296~Xd>27?=44m2:pg0<72;qUo85240;9f4=z{j91<7<t^b18917>2k:0q~m=:181[e534>:57o7;|q`5?6=:rTh=63;188240=z{j:1<7<t^b28917>20o0q~li:181[da34>:577l;|qaa?6=:rTii63;188:f>{tjm0;6?uQbe9>04?=1h1vom50;0xZge<5=;26474}r`a>5<5sWhi70:>9;;;?xuei3:1>vPma:?75<<f?2wxhi4?:3y]`a=:<831m;5rsea94?4|Vmi019?6:020?xucj3:1>vPkb:?75<<f=2wxhl4?:3y]`d=:<831m95rse;94?4|Vm3019?6:`18yvb?2909wSj7;<62=?g53tyo;7>52z\g3>;3900j=6s|cg83>7}Yko168<75a19~wf2=838pRn:4=53:><`<uzh26=4={_`:?826133<7p}=1883>6}Y:83019?6:33b?826138:n6s|5b83>7}Y=j168<75479~w0g=838pR8o4=53:>12<uz?26=4={_7:?82613>87p}:8;296~X2027?=44;2:p12<72;qU9:5240;90c=z{<<1<7<t^448917>2=o0q~;::181[3234>:57:k;|q60?6=:rT>863;1887g>{t=:0;6?uQ529>04?=<k1v:k50;0xZ2c<5=;26584}r34`?6=:rT:;i5240;95=6<uz2?6=4={_:7?82613287p}>7g83>7}Y9>l019?6:05f?xu6?<0;6?uQ1678917>28997p}>7283>7}Y9>9019?6:001?xu6?;0;6?uQ1608917>288;7p}>7083>7}Y9>;019?6:03e?xu6?90;6?uQ1628917>28;n7p}>6g83>7}Y9?l019?6:03g?xu6>m0;6?uQ17f8917>28;h7p}>6b83>7}Y9?i019?6:00a?xu6>k0;6?uQ17`8917>288j7p}>6`83>7}Y9?k019?6:013?xu6>00;6?uQ17;8917>28827p}>6983>7}Y9?2019?6:00;?xu6>>0;6?uQ1758917>288<7p}>6783>7}Y9?<019?6:005?xu6><0;6?uQ1778917>288>7p}>6583>7}Y9?>019?6:007?xu6>;0;6?uQ1708917>28887p}>6083>7}Y9?;019?6:03a?xu6>90;6?uQ1728917>288m7p}>5g83>7}Y9<l019?6:033?xu6=l0;6?uQ14g8917>28:n7p}>5e83>7}Y9<n019?6:02g?xu6=j0;6?uQ14a8917>28:h7p}>5c83>7}Y9<h019?6:02a?xu6=h0;6?uQ14c8917>28:j7p}>5883>7}Y9<3019?6:03:?xu6?j0;6?uQ16a8917>28;37p}>7c83>7}Y9>h019?6:00g?xu6?h0;6?uQ16c8917>28;<7p}>7883>7}Y9>3019?6:035?xu6?10;6?uQ16:8917>28;>7p}>7683>7}Y9>=019?6:037?xu6??0;6?uQ1648917>28;87p}>6d83>7}Y9?o019?6:031?xu6>:0;6?uQ1718917>28;:7p}>5983>7}Y9<2019?6:02:?xu>:3:18=u23`695=?<V080R?<=;_03<>X58?1U>=;4^327?[47;2T9<?5Q2138Z7673W;mj63;188155=:<8318l5240;90<=:<831855240;902=:<8318<5240;92<=:<831:55240;922=:<831:;5240;925=:<831?5m4=53:>6>e34>:57<>1:?75<<59j168<7520f8Z4543W;8i6P>489]507<V8?97S?:3:\211=Y9<?0R<;9;_363>X6;=1U=>;4^015?[74?2T:?55Q12;8Z45f3W;8n6P>3b9]56b<V89m7S?;0:\204=Y9=80R<:<;_370>X6<<1U=984^064?[7302T:8l5Q15`8Z42d3W;?h6P>4d9]506<uth9m?4?:583>5}#:;o1=ho4H2c0?M5??2.:j?4;169j32<722c2:7>5;h014?6=3f;m=7>5;|`1e4<72=0;6=u+23g95`g<@:k87E=77:&2b7<39>1b;:4?::k:2?6=3`89<7>5;n3e5?6=3th9m=4?:583>5}#:;o1=ho4H2c0?M5??2.:j?4;169j32<722c2:7>5;h014?6=3f;m=7>5;|`1=c<72=0;6=u+23g95`g<@:k87E=77:&2b7<39>1b;:4?::k:2?6=3`89<7>5;n3e5?6=3th9m>4?:583>5}#:;o1=ho4H2c0?M5??2.:j?4;169j32<722c2:7>5;h014?6=3f;m=7>5;|`1f0<72=0;6=u+23g95`g<@:k87E=77:&2b7<39>1b;:4?::k:2?6=3`89<7>5;n3e5?6=3th9n94?:583>5}#:;o1=ho4H2c0?M5??2.:j?4;169j32<722c2:7>5;h014?6=3f;m=7>5;|`1f6<72=0;6=u+23g95`g<@:k87E=77:&2b7<39>1b;:4?::k:2?6=3`89<7>5;n3e5?6=3th9n?4?:583>5}#:;o1=ho4H2c0?M5??2.:j?4;169j32<722c2:7>5;h014?6=3f;m=7>5;|`1f3<72=0;6=u+23g95`g<@:k87E=77:&2b7<39>1b;:4?::k:2?6=3`89<7>5;n3e5?6=3th98?4?:583>5}#:;o1=ho4H2c0?M5??2.:j?4;169j32<722c2:7>5;h014?6=3f;m=7>5;|`104<72=0;6=u+23g95`g<@:k87E=77:&2b7<39>1b;:4?::k:2?6=3`89<7>5;n3e5?6=3th98=4?:583>5}#:;o1=ho4H2c0?M5??2.:j?4;169j32<722c2:7>5;h014?6=3f;m=7>5;|`17c<72=0;6=u+23g95`g<@:k87E=77:&2b7<39>1b;:4?::k:2?6=3`89<7>5;n3e5?6=3th98>4?:583>5}#:;o1=ho4H2c0?M5??2.:j?4;169j32<722c2:7>5;h014?6=3f;m=7>5;|`110<72=0;6=u+23g95`g<@:k87E=77:&2b7<39>1b;:4?::k:2?6=3`89<7>5;n3e5?6=3th9994?:583>5}#:;o1=ho4H2c0?M5??2.:j?4;169j32<722c2:7>5;h014?6=3f;m=7>5;|`116<72=0;6=u+23g95`g<@:k87E=77:&2b7<39>1b;:4?::k:2?6=3`89<7>5;n3e5?6=3th99?4?:583>5}#:;o1=ho4H2c0?M5??2.:j?4;169j32<722c2:7>5;h014?6=3f;m=7>5;|`113<72=0;6=u+23g95`g<@:k87E=77:&2b7<39>1b;:4?::k:2?6=3`89<7>5;n3e5?6=3th95l4?:483>5}#:;o1=5:4H2c0?M5??2.:5l4<;h57>5<<a>?1<75f8e83>>o>93:17b?ib;29?xd5100;684?:1y'67c=91>0D>o<;I1;3>"61h087d9;:188m23=831b4i4?::k:5?6=3f;mn7>5;|`1==<72<0;6=u+23g95=2<@:k87E=77:&2=d<43`=?6=44i6794?=n0m0;66g61;29?j7aj3:17pl=9683>0<729q/>?k51968L6g43A93;6*>9`80?l132900e:;50;9j<a<722c2=7>5;n3ef?6=3th95;4?:483>5}#:;o1=5:4H2c0?M5??2.:5l4<;h57>5<<a>?1<75f8e83>>o>93:17b?ib;29?xd51<0;684?:1y'67c=91>0D>o<;I1;3>"61h087d9;:188m23=831b4i4?::k:5?6=3f;mn7>5;|`1=1<72<0;6=u+23g95=2<@:k87E=77:&2=d<43`=?6=44i6794?=n0m0;66g61;29?j7aj3:17pl=9283>0<729q/>?k51968L6g43A93;6*>9`80?l132900e:;50;9j<a<722c2=7>5;n3ef?6=3th94l4?:483>5}#:;o1=5:4H2c0?M5??2.:5l4<;h57>5<<a>?1<75f8e83>>o>93:17b?ib;29?xd5000;684?:1y'67c=91>0D>o<;I1;3>"61h087d9;:188m23=831b4i4?::k:5?6=3f;mn7>5;|`1<=<72<0;6=u+23g95=2<@:k87E=77:&2=d<43`=?6=44i6794?=n0m0;66g61;29?j7aj3:17pl=8683>0<729q/>?k51968L6g43A93;6*>9`80?l132900e:;50;9j<a<722c2=7>5;n3ef?6=3th94;4?:483>5}#:;o1=5:4H2c0?M5??2.:5l4<;h57>5<<a>?1<75f8e83>>o>93:17b?ib;29?xd50<0;684?:1y'67c=91>0D>o<;I1;3>"61h087d9;:188m23=831b4i4?::k:5?6=3f;mn7>5;|`1<1<72<0;6=u+23g95=2<@:k87E=77:&2=d<43`=?6=44i6794?=n0m0;66g61;29?j7aj3:17pl=8283>0<729q/>?k51968L6g43A93;6*>9`80?l132900e:;50;9j<a<722c2=7>5;n3ef?6=3th94?4?:483>5}#:;o1=584H2c0?M5??2.:5l47;h57>5<<a>?1<75f9083>>o6n00;66a>fc83>>{e::>1<7:50;2x 74b28287E=n3:J0<2=#90k1?6g84;29?l>c2900e4?50;9l5cd=831vn?=>:187>5<7s-89i7?73:J0e6=O;1=0(<7n:29j31<722c3h7>5;h;2>5<<g8li6=44}c003?6=<3:1<v*=2d82<0=O;h90D>68;%3:e?><a>>1<75f9083>>o6n00;66a>fc83>>{e::<1<7:50;2x 74b282>7E=n3:J0<2=#90k146g84;29?l?62900e<h6:188k4`e2900qo<ia;291?6=8r.9>h4>859K7d5<@:2<7)?6a;18m22=831b;84?::k;`?6=3`3:6=44o0da>5<<uk8m57>55;294~"5:l0:495G3`18L6>03-;2m7=4i6694?=n?<0;66g7d;29?l?62900c<hm:188yg4a03:197>50z&16`<60=1C?l=4H2:4?!7>i390e::50;9j30<722c3h7>5;h;2>5<<g8li6=44}c0e3?6==3:1<v*=2d82<1=O;h90D>68;%3:e?5<a>>1<75f7483>>o?l3:17d7>:188k4`e2900qo<i6;291?6=8r.9>h4>859K7d5<@:2<7)?6a;18m22=831b;84?::k;`?6=3`3:6=44o0da>5<<uk8m97>55;294~"5:l0:495G3`18L6>03-;2m7=4i6694?=n?<0;66g7d;29?l?62900c<hm:188yg4a<3:197>50z&16`<60=1C?l=4H2:4?!7>i390e::50;9j30<722c3h7>5;h;2>5<<g8li6=44}c0e7?6==3:1<v*=2d82<1=O;h90D>68;%3:e?5<a>>1<75f7483>>o?l3:17d7>:188k4`e2900qo<i2;291?6=8r.9>h4>859K7d5<@:2<7)?6a;18m22=831b;84?::k;`?6=3`3:6=44o0da>5<<uk8n47>55;294~"5:l0:495G3`18L6>03-;2m7=4i6694?=n?<0;66g7d;29?l?62900c<hm:188yg4b?3:197>50z&16`<60=1C?l=4H2:4?!7>i390e::50;9j30<722c3h7>5;h;2>5<<g8li6=44}c0f2?6==3:1<v*=2d82<1=O;h90D>68;%3:e?5<a>>1<75f7483>>o?l3:17d7>:188k4`e2900qo<j5;291?6=8r.9>h4>859K7d5<@:2<7)?6a;18m22=831b;84?::k;`?6=3`3:6=44o0da>5<<uk8n87>55;294~"5:l0:495G3`18L6>03-;2m7=4i6694?=n?<0;66g7d;29?l?62900c<hm:188yg4b;3:197>50z&16`<60=1C?l=4H2:4?!7>i390e::50;9j30<722c3h7>5;h;2>5<<g8li6=44}c0f6?6==3:1<v*=2d82<1=O;h90D>68;%3:e?5<a>>1<75f7483>>o?l3:17d7>:188k4`e2900qo<j1;291?6=8r.9>h4>859K7d5<@:2<7)?6a;18m22=831b;84?::k;`?6=3`3:6=44o0da>5<<uk8h;7>53;294~"5:l0:i95G3`18L6>03-;2m7?<;h3;g?6=3`;3h7>5;n3e5?6=3th9o94?:683>5}#:;o1=h64H2c0?M5??2.:5l49;h3;g?6=3`;3h7>5;h3;a?6=3`;3j7>5;h3:4?6=3`;2=7>5;n3e5?6=3th9:94?:683>5}#:;o1=h64H2c0?M5??2.:5l463:k2<f<722c:4i4?::k2<`<722c:4k4?::k2=5<722c:5<4?::m2b4<722wi?;k50;194?6|,;8n6<k;;I1b7>N40>1/=4o5129'5c>=;ho0e<6l:188m4>c2900c<h>:188yg51n3:1?7>50z&16`<6m=1C?l=4H2:4?!7>i3;87)?i8;1a3>o60j0;66g>8e83>>i6n80;66sm36d94?5=83:p(?<j:0g7?M5f;2B84:5+18c956=#9o21?lk4i0:`>5<<a82o6=44o0d2>5<<uk9397>53;294~"5:l0:i95G3`18L6>03-;2m7?<;%3e<?5e?2c:4n4?::k2<a<722e:j<4?::a6dd=83?1<7>t$30f>4c13A9j?6F<869'5<g=:l1b=5m50;9j5=b=831b=5k50;9j5=`=831d=k?50;9~f7g>290>6=4?{%01a?7b>2B8m>5G3958 4?f2;o0e<6l:188m4>c2900e<6j:188m4>a2900c<h>:188yg4f?3:197>50z&16`<6m?1C?l=4H2:4?!7>i38n7d?7c;29?l7?l3:17d?7e;29?l7?n3:17b?i1;29?xd5im0;6>4?:1y'67c=9l>0D>o<;I1;3>"61h09h6g>8b83>>o60m0;66a>f083>>{e:ko1<7;50;2x 74b28o=7E=n3:J0<2=#90k1>h5f19a94?=n91n1<75f19g94?=n91l1<75`1g394?=zj;hh6=4::183!45m3;n:6F<a29K7=1<,83j6?k4i0:`>5<<a82o6=44i0:f>5<<a82m6=44o0d2>5<<uk8im7>55;294~"5:l0:i;5G3`18L6>03-;2m7<j;h3;g?6=3`;3h7>5;h3;a?6=3`;3j7>5;n3e5?6=3th9o=4?:283>5}#:;o1=h:4H2c0?M5??2.:5l4=d:k2<f<722c:4i4?::m2b4<722wi>9l50;794?6|,;8n6<k9;I1b7>N40>1/=4o52d9j5=e=831b=5j50;9j5=c=831b=5h50;9l5c7=831vn?:6:186>5<7s-89i7?j6:J0e6=O;1=0(<7n:3g8m4>d2900e<6k:188m4>b2900e<6i:188k4`62900qo<;7;291?6=8r.9>h4>e79K7d5<@:2<7)?6a;0f?l7?k3:17d?7d;29?l7?m3:17d?7f;29?j7a93:17pl=4e83>6<729q/>?k51d68L6g43A93;6*>9`81`>o60j0;66g>8e83>>i6n80;66sm24g94?3=83:p(?<j:0g5?M5f;2B84:5+18c96`=n91i1<75f19f94?=n91o1<75f19d94?=h9o;1<75rb37`>5<2290;w)<=e;3f2>N4i:1C?594$0;b>7c<a82h6=44i0:g>5<<a82n6=44i0:e>5<<g8l:6=44}c06e?6==3:1<v*=2d82a3=O;h90D>68;%3:e?4b3`;3o7>5;h3;`?6=3`;3i7>5;h3;b?6=3f;m=7>5;|`11=<72<0;6=u+23g95`0<@:k87E=77:&2=d<5m2c:4n4?::k2<a<722c:4h4?::k2<c<722e:j<4?::a636=8391<7>t$30f>4c33A9j?6F<869'5<g=:m1b=5m50;9j5=b=831d=k?50;9~f70e290=6=4?{%01a?7b?2B8m>5G3958 4?f2;=0(<h7:2ce?l7?k3:17d?7d;29?l7?m3:17d?7f;29?l7>83:17b?i1;29?xd5>j0;6:4?:1y'67c=9l20D>o<;I1;3>"61h0946g>8b83>>o60m0;66g>8d83>>o60o0;66g>9183>>o6180;66a>f083>>{e:?o1<7950;2x 74b28o37E=n3:J0<2=#90k1>l5f19a94?=n91n1<75f19g94?=n91l1<75f18294?=n90;1<75`1g394?=zj;<j6=4::183!45m3;n:6F<a29K7=1<,83j6?84$0d;>6ga3`;3o7>5;h3;`?6=3`;3i7>5;h3;b?6=3f;m=7>5;|`12a<72:0;6=u+23g95`2<@:k87E=77:&2=d<5l2c:4n4?::k2<a<722e:j<4?::a63?=83>1<7>t$30f>4c23A9j?6F<869'5<g=:<1/=k653c48m4>d2900e<6k:188m4>b2900c<h>:188yg41n3:187>50z&16`<6m<1C?l=4H2:4?!7>i3997)?i8;1a6>o60j0;66g>8e83>>o60l0;66a>f083>>{e:>:1<7;50;2x 74b28o=7E=n3:J0<2=#90k1?>5+1g:97g4<a82h6=44i0:g>5<<a82n6=44i0:e>5<<g8l:6=44}c05<?6=;3:1<v*=2d82a1=O;h90D>68;%3:e?433-;m47=m6:k2<f<722c:4i4?::m2b4<722wi>>>50;694?6|,;8n6<k:;I1b7>N40>1/=4o5359'5c>=;k90e<6l:188m4>c2900e<6j:188k4`62900qo<<9;291?6=8r.9>h4>e79K7d5<@:2<7)?6a;0`?!7a039i?6g>8b83>>o60m0;66g>8d83>>o60o0;66a>f083>>{e:;l1<7;50;2x 74b28o=7E=n3:J0<2=#90k1>?5+1g:97g6<a82h6=44i0:g>5<<a82n6=44i0:e>5<<g8l:6=44}c007?6==3:1<v*=2d82a3=O;h90D>68;%3:e?443-;m47=m0:k2<f<722c:4i4?::k2<`<722c:4k4?::m2b4<722wi>>;50;694?6|,;8n6<k:;I1b7>N40>1/=4o56g9'5c>=;k>0e<6l:188m4>c2900e<6j:188k4`62900qo<ld;297?6=8r.9>h4>e59K7d5<@:2<7)?6a;0g?l7?k3:17d?7d;29?j7a93:17pl=cg83>1<729q/>?k51d78L6g43A93;6*>9`806>"6n108n<5f19a94?=n91n1<75f19g94?=h9o;1<75rb3f3>5<2290;w)<=e;3f2>N4i:1C?594$0;b>65<,8l36>l>;h3;g?6=3`;3h7>5;h3;a?6=3`;3j7>5;n3e5?6=3th9m84?:483>5}#:;o1=h84H2c0?M5??2.:5l48;h3;g?6=3`;3h7>5;h3;a?6=3`;3j7>5;n3e5?6=3th9n54?:483>5}#:;o1=h84H2c0?M5??2.:5l4=e:k2<f<722c:4i4?::k2<`<722c:4k4?::m2b4<722wi>9;50;794?6|,;8n6<k9;I1b7>N40>1/=4o57:k2<f<722c:4i4?::k2<`<722c:4k4?::m2b4<722wi>nk50;594?6|,;8n6<k7;I1b7>N40>1/=4o5949j5=e=831b=5j50;9j5=c=831b=5h50;9j5<6=831b=4?50;9l5c7=831vn>8n:185>5<7s-89i7?j7:J0e6=O;1=0(<7n:0:;?!7a039i86g>8b83>>o60m0;66g>8d83>>o60o0;66g>9183>>i6n80;66sm2b`94?0=83:p(?<j:0g4?M5f;2B84:5+18c970=#9o21?lj4i0:`>5<<a82o6=44i0:f>5<<a82m6=44i0;3>5<<g8l:6=44}c0`g?6=?3:1<v*=2d82a==O;h90D>68;%3:e?513`;3o7>5;h3;`?6=3`;3i7>5;h3;b?6=3`;2<7>5;h3:5?6=3f;m=7>5;|`1gd<72<0;6=u+23g95`0<@:k87E=77:&2=d<4;2.:j54<ae9j5=e=831b=5j50;9j5=c=831b=5h50;9l5c7=831vn?m6:187>5<7s-89i7?j5:J0e6=O;1=0(<7n:208 4`?2:h>7d?7c;29?l7?l3:17d?7e;29?j7a93:17pl=c983>6<729q/>?k51d68L6g43A93;6*>9`81`>"6n108n85f19a94?=n91n1<75`1g394?=zj;<<6=4=:183!45m3;n<6F<a29K7=1<a82i6=44o0d2>5<<uk93:7>52;294~"5:l0:i=5G3`18L6>03`;3n7>5;n3e5?6=3ty?>=4?:6y]076<5:=:6<h6;<146?7a1278;>4>f89>7=6=9o301>9n:0d:?850832o7p}>ee83>2}:;h?1=k=4=24;>76a349=47<>3:?1=c<0?279n?487:?17c<0?2799?487:p5`c=83>?w0=n4;3;=>;4?802=63<788:5>;4??02=63<768:5>;4>109=:5237:97<2<5:<36>7=;<15<?5>9278:54<919>73>=nk16?;65f89>73>=n116?;65f69>73>=n?16?;65f49>73>=n:16?;65f39>73>=n816?;65f19>73>=mo16?;65ed9>73>=mm16?;65eb9>73>=mk16?;65e`9>73>=m116?;65e69>73>=m?16?;65e49>73>=m=16?;65e29>73>=m;16?;65e09>73>=m916?;65dg9>73>=99801>87:022?85103;;<63<698eb>;4>10mi63<698e`>;4>10mo63<698e0>;4>10n563<698ga>;4>10:hk5237:95ac<5;k86484=3;e><0<5;k;6484=3c2><0<5;k96484=3`5><0<5;h96484=3`0><0<5;h?6484=3`6><0<5;>86484=31e><0<5;>;6484=362><0<5;>96484=375><0<5;?96484=370><0<5;??6484=376><0<uz9=h7>516y>73>=;1l01>87:2:g?8510393o63<6980<g=:;?21=:j4=3g2>23<5;o96:;4=3g0>23<5;o?6:;4=3g6>23<5;o=6:;4=3g4>23<5;o36:;4=3d1>23<5;l86:;4=3d7>23<5;l>6:;4=3d5>23<5;l<6:;4=3d;>23<5;l26:;4=3db>23<5;i<6<h>;|q1g3<72;qU8<=4=3a5>4`e3ty9i44?:ey>73>=;>16>k<51g`8973?282m70<n5;3;b>;5<<0:4k522bg95=b<5;ii6<7?;<0`g?7>9279ol4>8e9>6f?=91n01?m7:0:g?85?>3;3n63=b982<c=z{;oj6=4:{<15<?5?348m?7?ib:?11=<60m16>l;519f89722282o7p}=ec83>0}:;?21?4522g695cd<5;k<6<6i;<073?7?n2799l4>8g9~w7cd290>w0=98;1b?84a=3;mn63=a682<a=::==1=5j4=37b>4>c3ty9ii4?:4y>73>=;k16>k851g`897g>282m70<;9;3;b>;5=j0:4k5rs3gf>5<2s49=47=l;<0e3?7aj279m44>8e9>61?=91n01?;l:0:g?xu5mo0;68u237:97a=::o21=kl4=3ca>4>a348?n7?7f:?11`<60o1v?h?:186851039n70<i9;3ef>;5ik0:4i5225`95=b<5;?n6<6k;|q1b4<72<q6?;65419>6cg=9oh01?ok:0:g?843l3;3h63=6182<a=z{:<i6=4>4z?1<7<0=2794>485:?1<1<0=27948485:?1<3<0=2794:485:?1<=<0=27944485:?1<d<0=2795>485:?1=1<0=27958485:?1=3<0=2795:485:?1==<0=27954485:?1=d<0=279o94>8g9>632=91l01?<i:0d2?xu4>j0;6?;t=203>23<5:8:6:;4=20`>23<5:9<6:;4=21f>23<5:9m6:;4=263>23<5:>:6:;4=261>23<5:>86:;4=201>23<5:886:;4=207>23<5:8>6:;4=205>23<5:8<6:;4=20;>23<5:826:;4=20b>23<5:8i6:;4=20g>23<5:8n6:;4=20e>23<5:9;6:;4=212>23<5:996:;4=210>23<5:9?6:;4=216>23<5:9=6:;4=21;>23<5:926:;4=21b>23<5:9i6:;4=21`>23<5:9o6:;4=313>4`63ty9:84?:4y>633=9oh01?<i:0:`?844;3;3o63=6582<`=:;?k1=5j4}r003?6=:rT?<i5222595cd<uz83n7>55z?02=<2<2795>4>fc9>6d3=91i01?:::0:`?84e03;3o6s|29a94?3|5:<368;4=3;7>4`e348j;7?7e:?1fd<60l16>99519g8yv4?l3:19v3<69862>;51<0:jo522`595=e<5;hj6<6l;<073?7?k2wx>5k50;7x960?2<=01?79:0da?84f13;3i63=bb82<`=::=31=5k4}r0;b?6==r78:54:8:?1=2<6nk16>l7519a897dd282h70<;9;3;g>{t:0:1<7;t=24;>0?<5;336<hm;<0bf?7?m279nh4>8d9>61d=91o0q~<61;291~;4>10>m63=9882bg=::hh1=5m4=3`f>4>d348?n7?7c:p6<4=83?p1>87:4a897?f28li70<nd;3;g>;5k90:4n5225f95=e<uz8mo7>52z\0a==:;;:1=kl4}r133?6=:rT8j>5233395cd<uz9:>7>52z\0b`=:;;i1=kl4}r12=?6=:rT?<;5232595cd<uz9:m7>52z\742=:;:o1=kl4}r12f?6=:rT?<55232d95cd<uz9:o7>52z\74<=:;=:1=kl4}r12`?6=:rT?<l5235395cd<uz9:i7>52z\74g=:;=81=kl4}r12b?6=:rT?<n5235195cd<uz8mh7>52z\0a<=:;;81=kl4}r0ea?6=:rT8il5233195cd<uz8mj7>52z\0ag=:;;>1=kl4}r134?6=:rT8in5233795cd<uz9;=7>52z\0aa=:;;<1=kl4}r136?6=:rT8ih5233595cd<uz9;?7>52z\0ac=:;;21=kl4}r130?6=:rT8j=5233;95cd<uz9;97>52z\0b4=:;;k1=kl4}r132?6=:rT8j?5233`95cd<uz9;47>52z\0b1=:;;n1=kl4}r13=?6=:rT8j85233g95cd<uz9;m7>52z\0b3=:;;l1=kl4}r13f?6=:rT8j:5232295cd<uz9;o7>52z\0b==:;:;1=kl4}r13`?6=:rT8j45232095cd<uz9;i7>52z\0bd=:;:91=kl4}r13b?6=:rT8jo5232695cd<uz9:<7>52z\0bf=:;:?1=kl4}r125?6=:rT8ji5232495cd<uz9:?7>52z\0bc=:;:21=kl4}r120?6=:rT?<=5232;95cd<uz9:97>52z\744=:;:k1=kl4}r122?6=:rT?<?5232`95cd<uz9:;7>52z\746=:;:i1=kl4}r12<?6=:rT?<85232f95cd<uz9<>7>54z?1g0<6n016>n851g;8961420;01>9=:0da?xu4?90;6?u236295cd<5;i?6<6k;|q030<728=p1?8::0d:?850?3;mn63=8382b<=::1914i522969<a=::1?14i522949<a=::1=14i5229:9<a=::1314i5229c9<a=::0914i522869<a=::0?14i522849<a=::0=14i5228:9<a=::0314i5228c9<a=:::<1=k74=314>4`>3488=76k;<000?>c3ty8;94?:35x961128li70==0;3eg>;4:80:jn5233a95ce<5:9<6<hl;<10a?7ak278?k4>fb9>716=9oi01>:>:0d`?853:3;mo63<4282bf=:;;81=km4=200>4`d349987?ic:?060<6nj16??851ga8964028lh70==8;3eg>;4:00:jn5233c95ce<5:8i6<hl;<11`?7ak278>h4>fb9>77`=9oi01>=?:0d`?85493;mo63<3382bf=:;:91=km4=217>4`d349897?ic:?073<6nj16?>651ga8965>28lh70=<a;3eg>;4;k0:jn5232a95ce<5:9o6<hl;<15<?461278:l4>919~w61?290:>v3<7882bg=::l;14i522d09<a=::l914i522d69<a=::l?14i522d49<a=::l=14i522d:9<a=::o814i522g19<a=::o>14i522g79<a=::o<14i522g59<a=::o214i522g;9<a=::ok14i5rs506>5<3sW>9963=c682<f=::j>1=5m4=347>4>d3ty?=o4?:6y]04d<5;9;6<6j;<00=?7?n279>k4>8g9>665=91l01?=::0:f?851i3;3o6s|3cd94?3csW9ij63=64840>;5k<0<863=c7840>;4?80<863<83840>;4?00<863<73840>;40:0<863<72840>;4090<863<71840>;4?j0<863<77840>;4?>0<863<7e840>;4?h0<863<21840>;4:80<863<2b840>;4;>0<863<3d840>;4;o0<863<41840>;4<80<863<43840>;4<:0<863<23840>;4::0<863<25840>;4:<0<863<27840>;4:>0<863<29840>;4:00<863<2`840>;4:k0<863<2e840>;4:l0<863<2g840>;4;90<863<30840>;4;;0<863<32840>;4;=0<863<34840>;4;?0<863<39840>;4;00<863<3`840>;4;k0<863<3b840>;4;m0<863<6984a>;4>103863=83840>;50:0<863=85840>;50<0<863=87840>;50>0<863=89840>;5000<863=8`840>;51:0<863=95840>;51<0<863=97840>;51>0<863=99840>;5100<863=9`840>;5;?0<863=36840>;5;80<863=35840>;5m80<863=e3840>;5m:0<863=e5840>;5m<0<863=e7840>;5m>0<863=e9840>;5n;0<863=f2840>;5n=0<863=f4840>;5n?0<863=f6840>;5n10<863=f8840>;5nh0<86s|3b194?4|V:i870=98;`:?xu4kl0;6?uQ3bg8960?2j>0q~=k9;296~X4l016?;65cg9~w6c62909wS=j1:?02=<c?2wx?h<50;0xZ6c5349=47j7;|q0a6<72;qU?h=4=24;>a?<uz9n87>52z\0a1=:;?21hl5rs2g6>5<5sW9n963<698gf>{t;l<1<7<t^2g5?85103nh7p}<e683>7}Y;l=01>87:ef8yv5d<3:1>vP<c59>73>=jh1v>m::181[5d=278:54mb:p7f0=838pR>m9;<15<?dd3ty8o:4?:3y]7f1<5:<36oj4}r1`<?6=:rT8o55237:9f`=z{:i26=4={_1`=>;4>10ij6s|3bc94?4|V:ij70=98;a3?xu4kk0;6?uQ3b`8960?2j;0q~=lc;296~X4kj16?;65c39~w6ec2909wS=ld:?02=<d;2wx?nh50;0xZ6ea349=47m:;|q0`5<72;qU?i>4=24;>f0<uz9o=7>52z\0`4=:;?21o:5rs2f1>5<5sW9o>63<698`<>{t;m91<7<t^2f0?85103i27p}<d583>7}Y;m>01>87:bc8yv5c=3:1>vP<d49>73>=kk1v>j9:181[5c>278:54lc:p7a1=838pR>j8;<15<?ec3ty8h54?:3y]7a><5:<36nk4}r1ge?6=:rT8hl5237:9`5=z{:ni6=4={_1gf>;4>10o=6s|3ea94?4|V:nh70=98;f1?xu4lm0;6?uQ3ef8960?2m90q~=ke;296~X4ll16?;65d59~w6c72909wS=j0:?02=<c>2wx>:?50;ax97>528li70<:8;3;a>;5>k0:4i5227a95=b<5;<n6<6j;<05e?7?l279:44>8e9>63>=91n01?o::0:f?843=3;3i63=6682<g=::k21=5k4}r046?6=1r794>4>fc9>6<5=1816>86519a8970e282n70<9c;3;a>;5>l0:4k5227c95=c<5;<26<6j;<05<?7?k2wx>:=50;:x97>328li70<64;;2?842i3;3i63=6c82<c=::?i1=5h4=34f>4>c348=m7?7f:?12<<60j1v?9;:18484?=3;mn63=948:5>;5=h0:4n5227`95<6<5;<h6<7?;<05a?7>8279:l4>8b9~w712290=w0<76;3ef>;51?02=63=5b82<`=::?h1=5m4=34`>4?6348=i7?61:p620=83?p1?68:0da?84>?33:70<:c;3;g>;5>j0:4n5227g95=e<uz8<;7>56z?1<=<6nk16>465909>60c=91o01?8k:0:`?841n3;3i63=7182<`=z{;=36=4:{<0;=?7aj27954461:?11`<60j16>;h519a89717282m7p}=7883>1}::1k1=kl4=3;b><7<5;<;6<6l;<044?7?k2wx>kl50;0x97`520;01>69:0d2?xu5l80;64u22d395cd<5;l864?4=3af>4>a348hn7?7e:?1gf<60l16>no519g897e>282n70<l8;3;g>;5j10:4i5rs3f1>5<?s48n>7?ib:?1b1<>9279nl4>8g9>6fc=91o01?mm:0:e?84dk3;3j63=c`82<c=::j31=5m4}r0g7?6=?r79i>4>fc9>6c3=1816>oo519f897eb283;70<lb;3;`>;5kj0:5=522bc95=e<uz8o87>56z?1a1<6nk16>k85909>6ge=91l01?mj:0;2?84dj3;3o63=cb82<a=z{;n>6=4:{<0f1?7aj279j:461:?1ff<60m16>nk519a897ed282h7p}=d783>3}::l<1=kl4=3d;><7<5;hn6<6i;<0``?7?k279ok4>8d9>6a6=91o0q~<k7;291~;5m>0:jo522g;9=4=::ko1=5j4=3ae>4>d348o<7?7f:p6a>=83>p1?k7:0da?84ai33:70<l0;3;`>;5l90:4n5rs3a6>5<3s48h97?ib:?1g2<60m16>n:519g89703282o7p}=6283>7}::??15<5227695c7<uz8=>7>52z?113<6n816>;:51838yv4193:1>v3=4282b4=::?>1=4>4}r0`7?6=;r79o8461:?1g3<>9279o94>f09~w7e52909w0<m6;3e5>;5k=0:5<5rs3a2>5<5s48j?7?i1:?1g1<6191v>9m:181850i33:70=9e;3e5>{t;>o1<7=t=255>4`>349<;7?i9:?03c<6n81v>6>:18185?833:70=9f;3e5>{t;1>1<7<t=25:>4`>349397?i1:p72b=838p1>9k:0da?850n3;3h6s|36a94?5|5:=o64?4=25`>4`e349=i7?7d:p72g=83>p1>9l:838961f28li70=9e;3;g>;4?o0:4n5rs2:0>5<5s493?7?ib:?0<0<60m1v>6=:18085?;33:70=72;3ef>;4>o0:4i5rs2:3>5<3s493>77>;<1;4?7aj278:k4>8b9>7=3=91i0q~=83;296~;4?902=63<7282bg=z{:=:6=4={<146??6349<=7?ib:p73?=838p1>87:05e?851i3;m=6s|35694?4|5:8;64?4=24;>43?3ty88k4?:3y>777=1816?;651718yv52i3:1>v3<2b8:5>;4>10::h5rs242>5<5s498;77>;<15<?70>2wx?;<50;0x965b20;01>87:054?xu4>:0;6?u232d9=4=:;?21=:64}r150?6=:r788=461:?02=<6?01v>8::181853933:70=98;34e>{t;?<1<7<t=261><7<5:<36<9m;|q022<72;q6?9=5909>73>=9>i0q~=;5;296~;4:;02=63<69821<=z{:>=6=4={<117??6349=47?:a:p711=838p1><;:838960?28?i7p}<4983>7}:;;?15<5237:950e<uz9?57>52z?063<>9278:54>5e9~w62f2909w0==7;;2?85103;>i6s|35`94?4|5:8364?4=24;>43a3ty88n4?:3y>77?=1816?;651728yv53l3:1>v3<2`8:5>;4>10::<5rs26f>5<5s499n77>;<15<?71:2wx?8>50;0x964c20;01>87:047?xu4=80;6?u233g9=4=:;?21=;;4}r166?6=:r78>k461:?02=<6>?1v>;<:181854833:70=98;353>{t;<>1<7<t=212><7<5:<36<87;|q010<72;q6?><5909>73>=9?30q~=:6;296~;4;:02=63<69822d=z{:?<6=4={<100??6349=47?9b:p70>=838p1>=::838960?28<h7p}<5883>7}:;:<15<5237:953b<uz9>n7>52z?07=<>9278:54>6g9~w63d2909w0=<9;;2?85103;<<6s|34f94?4|5:9j64?4=24;>4163ty89h4?:3y>76d=1816?;651608yv52n3:1>v3<3b8:5>;4>10:;>5rs243>5<5s498h77>;<15<?70=2wx>4k50;0x97g42>=01?o=:0d2?xu51m0;6?u22`395c7<5;k96:94}r0:g?6=:r79m=4>f09>6d7=?>1v?7m:18184>n3;m=63=a1843>{t:hk1<7<t=3c1>747348jn7?i1:p6d>=838p1?o>:303?84f13;m=6s|2`494?4|5;k;6?<?;<0b3?7a92wx>l:50;0x97?a2;8;70<n5;3e5>{t:hi1<7<t=3c0>747348jh7?i1:p6g7=838p1?l9:65897d228l:7p}=b183>7}::k>1=k?4=3`6>21<uz8jj7>52z?1f6<6n816>o:5769~w7gb2909w0<m2;3e5>;5j:0<;6s|2cf94?4|5;h>6?<?;<0aa?7a92wx>ol50;0x97d32;8;70<mc;3e5>{t:k31<7<t=3`0>747348im7?i1:p6g1=838p1?l=:303?84e03;m=6s|2cd94?4|5;h=6?<?;<0`4?7a92wx>>k50;0x97242>=01?:=:0d2?xu5;m0;6?u225395c7<5;>96:94}r00g?6=:r798=4>f09>617=?>1v?=m:181844n3;m=63=41843>{t:=k1<7<t=361>747348?n7?i1:p61>=838p1?:>:303?84313;m=6s|25494?4|5;>;6?<?;<073?7a92wx>9:50;0x975a2;8;70<;5;3e5>{t:=i1<7<t=360>747348?h7?i1:p607=838p1?;9:658973228l:7p}=5183>7}::<>1=k?4=376>21<uz8?j7>52z?116<6n816>8:5769~w72b2909w0<:2;3e5>;5=:0<;6s|24f94?4|5;?>6?<?;<06a?7a92wx>8l50;0x97332;8;70<:c;3e5>{t:<31<7<t=370>747348>m7?i1:p601=838p1?;=:303?84203;m=6s|24d94?4|5;?=6?<?;<054?7a92wx>;j50;6x970b28l:70<9d;3;`>;5>o0:4i5226295=b<uz8<m7>52z?1<6<>9279:54>f09~w71e2909w0<74;;2?84113;m=6s|26a94?4|5;2>64?4=34b>4`63ty9;i4?:3y>6=0=1816>;l51g38yv40m3:1>v3=868:5>;5>j0:j<5rs35e>5<5s483477>;<05`?7a92wx>5>50;0x97>>20;01?8i:0d2?xu5080;6?u229c9=4=::>:1=k?4}r006?6=:r79?<461:?176<6n81v?=7:180844>33:70<<7;;2?84413;m=6s|22c94?4|5;9?64?4=316>4`63ty9?94?:6y>662=9oh01?=?:0:g?84413;3h63=2g82<a=:::91=5k4=316>4>c349=m7?7f:p667=83=p1?=>:0da?84483;3o63=3882<`=::;l1=5k4=310>4>c348897?7c:?02d<60l1v?=9:181844>3;mn63=3882<f=z{;io6=4;{<0``?7?l279ok4>8e9>6a6=91n01?mj:0d2?xu5l00;6?u22d39=4=::j21=k?4}r0ge?6=:r79i?461:?1g<<6n81v?jm:18184b;33:70<la;3e5>{t:mi1<7<t=3g7><7<5;ii6<h>;|q1`a<72;q6>h;5909>6fe=9o;0q~<ke;296~;5m?02=63=ce82b4=z{;nm6=4={<0f3??6348hj7?i1:p6`6=838p1?k7:83897b728l:7p}=6783>6}:;?219>522909=4=::?=1=k?4}|l6=5<728qC?594}o7:5?6=9rB84:5rn4;1>5<6sA93;6sa58194?5|@:2<7p`:9583>4}O;1=0qc;65;296~N40>1vb879:181M5??2we94950;0xL6>03td>554?:3yK7=1<ug?257>52zJ0<2=zf<3j6=4={I1;3>{i=0h1<7<tH2:4?xh21j0;6?uG3958yk3>l3:1>vF<869~j0?b290:wE=77:m1<`=83;pD>68;|l6e5<728qC?594}o7b5?6=9rB84:5rn4c1>5<5sA93;6sa5`194?4|@:2<7p`:a583>7}O;1=0qc;n5;296~N40>1vb8o9:181M5??2we9l950;0xL6>03td>m54?:3yK7=1<ug?j57>52zJ0<2=zf<kj6=4>{I1;3>{i=hh1<7?tH2:4?xh2ij0;6<uG3958yk3fl3:1=vF<869~j0gb290:wE=77:m1d`=83;pD>68;|l6f5<728qC?594}o7a5?6=9rB84:5rn4`1>5<6sA93;6sa5c194?7|@:2<7p`:b583>4}O;1=0qc;m5;295~N40>1vb8l9:182M5??2we9o950;3xL6>03td>n54?:0yK7=1<ug?i57>51zJ0<2=zf<hj6=4>{I1;3>{i=kh1<7?tH2:4?xh2jj0;6<uG3958yk3el3:1=vF<869~j0db290:wE=77:m1g`=83;pD>68;|l6g5<728qC?594}o7`5?6=9rB84:5rn4a1>5<6sA93;6sa5b194?7|@:2<7p`:c583>4}O;1=0qc;l5;295~N40>1vb8m9:182M5??2we9n950;3xL6>03td>o54?:0yK7=1<ug?h57>51zJ0<2=zf<ij6=4>{I1;3>{i=jh1<7?tH2:4?xh2kj0;6<uG3958yk3dl3:1=vF<869~j0eb290:wE=77:m1f`=83;pD>68;|l6`5<728qC?594}o7g5?6=:rB84:5rn4f1>5<6sA93;6sa5e194?7|@:2<7p`:d583>4}O;1=0qc;k5;297~N40>1vb8j9:181M5??2we9i950;0xL6>03td>h54?:3yK7=1<ug?o57>52zJ0<2=zf<nj6=4={I1;3>{i=mh1<7<tH2:4?xh2lj0;6?uG3958yk3cl3:1>vF<869~j0bb2909wE=77:m1a`=838pD>68;|l6a5<72;qC?594}o7f5?6=:rB84:5rn4g1>5<5sA93;6sa5d194?4|@:2<7p`:e583>7}O;1=0qc;j5;296~N40>1vb8k9:181M5??2we9h950;0xL6>03td>i54?:3yK7=1<ug?n57>52zJ0<2=zf<oj6=4={I1;3>{i=lh1<7<tH2:4?xh2mj0;6?uG3958yk3bl3:1>vF<869~j0cb2909wE=77:m1``=838pD>68;|l6b5<72;qC?594}o7e5?6=:rB84:5rn4d1>5<5sA93;6sa5g194?4|@:2<7p`:f583>7}O;1=0qc;i5;296~N40>1vb8h9:181M5??2we9k950;0xL6>03td>j54?:3yK7=1<ug?m57>52zJ0<2=zf<lj6=4>{I1;3>{i=oh1<7?tH2:4?xh2nj0;6<uG3958yk3al3:1=vF<869~j0`b290:wE=77:m1c`=83;pD>68;|l545<728qC?594}o435?6=9rB84:5rn721>5<6sA93;6sa61194?7|@:2<7p`90583>4}O;1=0qc8?5;295~N40>1vb;>9:182M5??2we:=950;3xL6>03td=<54?:0yK7=1<ug<;57>51zJ0<2=zf?:j6=4>{I1;3>{i>9h1<7?tH2:4?xh18j0;6<uG3958yk07l3:1=vF<869~j36b290:wE=77:m25`=83;pD>68;|l555<728qC?594}o425?6=9rB84:5rn731>5<6sA93;6sa60194?7|@:2<7p`91583>4}O;1=0qc8>5;295~N40>1vb;?9:182M5??2we:<950;3xL6>03td==54?:0yK7=1<ug<:57>51zJ0<2=zf?;j6=4>{I1;3>{i>8h1<7?tH2:4?xh19j0;6<uG3958yk06l3:1=vF<869~j37b290:wE=77:m24`=838pD>68;|l565<72;qC?594}o415?6=:rB84:5rn701>5<5sA93;6sa63194?4|@:2<7p`92583>7}O;1=0qc8=5;296~N40>1vb;<9:181M5??2we:?950;0xL6>03td=>54?:3yK7=1<ug<957>52zJ0<2=zf?8j6=4={I1;3>{i>;h1<7<tH2:4?xh1:j0;6?uG3958yk05l3:1>vF<869~j34b2909wE=77:m27`=838pD>68;|l575<72;qC?594}o405?6=:rB84:5rn711>5<5sA93;6sa62194?4|@:2<7p`93583>7}O;1=0qc8<5;296~N40>1vb;=9:181M5??2we:>950;0xL6>03td=?54?:3yK7=1<ug<857>52zJ0<2=zf?9j6=4={I1;3>{i>:h1<7<tH2:4?xh1;j0;6?uG3958yk04l3:1>vF<869~j35b2909wE=77:m26`=838pD>68;|l505<72;qC?594}o475?6=:rB84:5rn761>5<5sA93;6sa65194?4|@:2<7p`94583>4}O;1=0qc8;5;295~N40>1vb;:9:182M5??2we:9950;3xL6>03td=854?:0yK7=1<ug<?57>51zJ0<2=zf?>j6=4>{I1;3>{i>=h1<7?tH2:4?xh1<j0;6<uG3958yk03l3:1=vF<869~j32b290:wE=77:m21`=83;pD>68;|l515<728qC?594}o465?6=9rB84:5rn771>5<6sA93;6sa64194?7|@:2<7p`95583>4}O;1=0qc8:5;295~N40>1vb;;9:182M5??2we:8950;3xL6>03td=954?:0yK7=1<ug<>57>51zJ0<2=zf??j6=4>{I1;3>{i><h1<7?tH2:4?xh1=j0;6<uG3958yk02l3:1=vF<869~j33b290:wE=77:m20`=83;pD>68;|l525<728qC?594}o455?6=9rB84:5rn741>5<6sA93;6sa67194?7|@:2<7p`96583>4}O;1=0qc895;295~N40>1vb;89:182M5??2we:;950;3xL6>03td=:54?:0yK7=1<ug<=57>51zJ0<2=zf?<j6=4>{I1;3>{i>?h1<7?tH2:4?xh1>j0;6<uG3958yk01l3:1=vF<869~j30b290:wE=77:m23`=83;pD>68;|l535<728qC?594}o445?6=9rB84:5rn751>5<6sA93;6sa66194?7|@:2<7p`97583>4}O;1=0qc885;295~N40>1vb;99:182M5??2we::950;3xL6>03td=;54?:0yK7=1<ug<<57>51zJ0<2=zf?=j6=4>{I1;3>{i>>h1<7?tH2:4?xh1?j0;6<uG3958yk00l3:1=vF<869~j31b290:wE=77:m22`=83;pD>68;|l5<5<72;qC?594}o110?6=9rB84:5r}|CDF}0?:0m:98i31c~DED|8tJK\vsO@
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.vhd b/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.vhd
deleted file mode 100644
index dc12793..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.vhd
+++ /dev/null
@@ -1,280 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
--- You must compile the wrapper file sync_fifo_FWFT_512x36.vhd when simulating
--- the core, sync_fifo_FWFT_512x36. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-LIBRARY XilinxCoreLib;
--- synthesis translate_on
-ENTITY sync_fifo_FWFT_512x36 IS
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END sync_fifo_FWFT_512x36;
-
-ARCHITECTURE sync_fifo_FWFT_512x36_a OF sync_fifo_FWFT_512x36 IS
--- synthesis translate_off
-COMPONENT wrapped_sync_fifo_FWFT_512x36
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END COMPONENT;
-
--- Configuration specification
-  FOR ALL : wrapped_sync_fifo_FWFT_512x36 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
-    GENERIC MAP (
-      c_add_ngc_constraint => 0,
-      c_application_type_axis => 0,
-      c_application_type_rach => 0,
-      c_application_type_rdch => 0,
-      c_application_type_wach => 0,
-      c_application_type_wdch => 0,
-      c_application_type_wrch => 0,
-      c_axi_addr_width => 32,
-      c_axi_aruser_width => 1,
-      c_axi_awuser_width => 1,
-      c_axi_buser_width => 1,
-      c_axi_data_width => 64,
-      c_axi_id_width => 4,
-      c_axi_ruser_width => 1,
-      c_axi_type => 0,
-      c_axi_wuser_width => 1,
-      c_axis_tdata_width => 64,
-      c_axis_tdest_width => 4,
-      c_axis_tid_width => 8,
-      c_axis_tkeep_width => 4,
-      c_axis_tstrb_width => 4,
-      c_axis_tuser_width => 4,
-      c_axis_type => 0,
-      c_common_clock => 1,
-      c_count_type => 0,
-      c_data_count_width => 10,
-      c_default_value => "BlankString",
-      c_din_width => 36,
-      c_din_width_axis => 1,
-      c_din_width_rach => 32,
-      c_din_width_rdch => 64,
-      c_din_width_wach => 32,
-      c_din_width_wdch => 64,
-      c_din_width_wrch => 2,
-      c_dout_rst_val => "0",
-      c_dout_width => 36,
-      c_enable_rlocs => 0,
-      c_enable_rst_sync => 1,
-      c_error_injection_type => 0,
-      c_error_injection_type_axis => 0,
-      c_error_injection_type_rach => 0,
-      c_error_injection_type_rdch => 0,
-      c_error_injection_type_wach => 0,
-      c_error_injection_type_wdch => 0,
-      c_error_injection_type_wrch => 0,
-      c_family => "virtex6",
-      c_full_flags_rst_val => 1,
-      c_has_almost_empty => 0,
-      c_has_almost_full => 0,
-      c_has_axi_aruser => 0,
-      c_has_axi_awuser => 0,
-      c_has_axi_buser => 0,
-      c_has_axi_rd_channel => 0,
-      c_has_axi_ruser => 0,
-      c_has_axi_wr_channel => 0,
-      c_has_axi_wuser => 0,
-      c_has_axis_tdata => 0,
-      c_has_axis_tdest => 0,
-      c_has_axis_tid => 0,
-      c_has_axis_tkeep => 0,
-      c_has_axis_tlast => 0,
-      c_has_axis_tready => 1,
-      c_has_axis_tstrb => 0,
-      c_has_axis_tuser => 0,
-      c_has_backup => 0,
-      c_has_data_count => 0,
-      c_has_data_counts_axis => 0,
-      c_has_data_counts_rach => 0,
-      c_has_data_counts_rdch => 0,
-      c_has_data_counts_wach => 0,
-      c_has_data_counts_wdch => 0,
-      c_has_data_counts_wrch => 0,
-      c_has_int_clk => 0,
-      c_has_master_ce => 0,
-      c_has_meminit_file => 0,
-      c_has_overflow => 0,
-      c_has_prog_flags_axis => 0,
-      c_has_prog_flags_rach => 0,
-      c_has_prog_flags_rdch => 0,
-      c_has_prog_flags_wach => 0,
-      c_has_prog_flags_wdch => 0,
-      c_has_prog_flags_wrch => 0,
-      c_has_rd_data_count => 0,
-      c_has_rd_rst => 0,
-      c_has_rst => 1,
-      c_has_slave_ce => 0,
-      c_has_srst => 0,
-      c_has_underflow => 0,
-      c_has_valid => 0,
-      c_has_wr_ack => 0,
-      c_has_wr_data_count => 0,
-      c_has_wr_rst => 0,
-      c_implementation_type => 0,
-      c_implementation_type_axis => 1,
-      c_implementation_type_rach => 1,
-      c_implementation_type_rdch => 1,
-      c_implementation_type_wach => 1,
-      c_implementation_type_wdch => 1,
-      c_implementation_type_wrch => 1,
-      c_init_wr_pntr_val => 0,
-      c_interface_type => 0,
-      c_memory_type => 1,
-      c_mif_file_name => "BlankString",
-      c_msgon_val => 1,
-      c_optimization_mode => 0,
-      c_overflow_low => 0,
-      c_preload_latency => 0,
-      c_preload_regs => 1,
-      c_prim_fifo_type => "512x36",
-      c_prog_empty_thresh_assert_val => 4,
-      c_prog_empty_thresh_assert_val_axis => 1022,
-      c_prog_empty_thresh_assert_val_rach => 1022,
-      c_prog_empty_thresh_assert_val_rdch => 1022,
-      c_prog_empty_thresh_assert_val_wach => 1022,
-      c_prog_empty_thresh_assert_val_wdch => 1022,
-      c_prog_empty_thresh_assert_val_wrch => 1022,
-      c_prog_empty_thresh_negate_val => 5,
-      c_prog_empty_type => 0,
-      c_prog_empty_type_axis => 0,
-      c_prog_empty_type_rach => 0,
-      c_prog_empty_type_rdch => 0,
-      c_prog_empty_type_wach => 0,
-      c_prog_empty_type_wdch => 0,
-      c_prog_empty_type_wrch => 0,
-      c_prog_full_thresh_assert_val => 511,
-      c_prog_full_thresh_assert_val_axis => 1023,
-      c_prog_full_thresh_assert_val_rach => 1023,
-      c_prog_full_thresh_assert_val_rdch => 1023,
-      c_prog_full_thresh_assert_val_wach => 1023,
-      c_prog_full_thresh_assert_val_wdch => 1023,
-      c_prog_full_thresh_assert_val_wrch => 1023,
-      c_prog_full_thresh_negate_val => 510,
-      c_prog_full_type => 0,
-      c_prog_full_type_axis => 0,
-      c_prog_full_type_rach => 0,
-      c_prog_full_type_rdch => 0,
-      c_prog_full_type_wach => 0,
-      c_prog_full_type_wdch => 0,
-      c_prog_full_type_wrch => 0,
-      c_rach_type => 0,
-      c_rd_data_count_width => 10,
-      c_rd_depth => 512,
-      c_rd_freq => 1,
-      c_rd_pntr_width => 9,
-      c_rdch_type => 0,
-      c_reg_slice_mode_axis => 0,
-      c_reg_slice_mode_rach => 0,
-      c_reg_slice_mode_rdch => 0,
-      c_reg_slice_mode_wach => 0,
-      c_reg_slice_mode_wdch => 0,
-      c_reg_slice_mode_wrch => 0,
-      c_synchronizer_stage => 2,
-      c_underflow_low => 0,
-      c_use_common_overflow => 0,
-      c_use_common_underflow => 0,
-      c_use_default_settings => 0,
-      c_use_dout_rst => 1,
-      c_use_ecc => 0,
-      c_use_ecc_axis => 0,
-      c_use_ecc_rach => 0,
-      c_use_ecc_rdch => 0,
-      c_use_ecc_wach => 0,
-      c_use_ecc_wdch => 0,
-      c_use_ecc_wrch => 0,
-      c_use_embedded_reg => 0,
-      c_use_fifo16_flags => 0,
-      c_use_fwft_data_count => 1,
-      c_valid_low => 0,
-      c_wach_type => 0,
-      c_wdch_type => 0,
-      c_wr_ack_low => 0,
-      c_wr_data_count_width => 10,
-      c_wr_depth => 512,
-      c_wr_depth_axis => 1024,
-      c_wr_depth_rach => 16,
-      c_wr_depth_rdch => 1024,
-      c_wr_depth_wach => 16,
-      c_wr_depth_wdch => 1024,
-      c_wr_depth_wrch => 16,
-      c_wr_freq => 1,
-      c_wr_pntr_width => 9,
-      c_wr_pntr_width_axis => 10,
-      c_wr_pntr_width_rach => 4,
-      c_wr_pntr_width_rdch => 10,
-      c_wr_pntr_width_wach => 4,
-      c_wr_pntr_width_wdch => 10,
-      c_wr_pntr_width_wrch => 4,
-      c_wr_response_latency => 1,
-      c_wrch_type => 0
-    );
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_sync_fifo_FWFT_512x36
-  PORT MAP (
-    clk => clk,
-    rst => rst,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty
-  );
--- synthesis translate_on
-
-END sync_fifo_FWFT_512x36_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.vho b/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.vho
deleted file mode 100644
index eb9fec8..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.vho
+++ /dev/null
@@ -1,93 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
---    Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3   --
---                                                                            --
---    Rev 1. The FIFO Generator is a parameterizable first-in/first-out       --
---    memory queue generator. Use it to generate resource and performance     --
---    optimized FIFOs with common or independent read/write clock domains,    --
---    and optional fixed or programmable full and empty flags and             --
---    handshaking signals.  Choose from a selection of memory resource        --
---    types for implementation.  Optional Hamming code based error            --
---    detection and correction as well as error injection capability for      --
---    system test help to insure data integrity.  FIFO width and depth are    --
---    parameterizable, and for native interface FIFOs, asymmetric read and    --
---    write port widths are also supported.                                   --
---------------------------------------------------------------------------------
-
--- Interfaces:
---    AXI4Stream_MASTER_M_AXIS
---    AXI4Stream_SLAVE_S_AXIS
---    AXI4_MASTER_M_AXI
---    AXI4_SLAVE_S_AXI
---    AXI4Lite_MASTER_M_AXI
---    AXI4Lite_SLAVE_S_AXI
---    master_aclk
---    slave_aclk
---    slave_aresetn
-
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-COMPONENT sync_fifo_FWFT_512x36
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC
-  );
-END COMPONENT;
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : sync_fifo_FWFT_512x36
-  PORT MAP (
-    clk => clk,
-    rst => rst,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty
-  );
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file sync_fifo_FWFT_512x36.vhd when simulating
--- the core, sync_fifo_FWFT_512x36. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.xco b/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.xco
deleted file mode 100644
index 66b0110..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.xco
+++ /dev/null
@@ -1,213 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Fri Sep 19 14:17:44 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:fifo_generator:9.3
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=sync_fifo_FWFT_512x36
-CSET data_count=false
-CSET data_count_width=10
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=4
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=5
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=511
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=510
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=36
-CSET input_depth=512
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=36
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=First_Word_Fall_Through
-CSET programmable_empty_type=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
-CSET programmable_full_type=No_Programmable_Full_Threshold
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=10
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET synchronization_stages=2
-CSET synchronization_stages_axi=2
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=true
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=10
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-11-19T12:39:56Z
-# END Extra information
-GENERATE
-# CRC: c1caed69
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.xise b/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.xise
deleted file mode 100644
index 03d6f9b..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_FWFT_512x36.xise
+++ /dev/null
@@ -1,74 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="sync_fifo_FWFT_512x36.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="sync_fifo_FWFT_512x36.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|sync_fifo_FWFT_512x36|sync_fifo_FWFT_512x36_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="sync_fifo_FWFT_512x36.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sync_fifo_FWFT_512x36" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="sync_fifo_FWFT_512x36" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-09-19T16:19:35" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="46168A5A1EB549528AEB437BD4FABD6F" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.asy b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.asy
deleted file mode 100644
index 1789c8a..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.asy
+++ /dev/null
@@ -1,45 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 sync_fifo_progfull364_progempty128_512x36
-RECTANGLE Normal 32 32 800 4064
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName din[35:0]
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 464 32 464
-PIN 0 464 LEFT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Normal 0 528 32 528
-PIN 0 528 LEFT 36
-PINATTR PinName prog_full
-PINATTR Polarity OUT
-LINE Wide 832 272 800 272
-PIN 832 272 RIGHT 36
-PINATTR PinName dout[35:0]
-PINATTR Polarity OUT
-LINE Normal 832 304 800 304
-PIN 832 304 RIGHT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 832 496 800 496
-PIN 832 496 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-LINE Normal 832 560 800 560
-PIN 832 560 RIGHT 36
-PINATTR PinName prog_empty
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.gise b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.gise
deleted file mode 100644
index 67c447c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.gise
+++ /dev/null
@@ -1,53 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="sync_fifo_progfull364_progempty128_512x36.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="sync_fifo_progfull364_progempty128_512x36.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="sync_fifo_progfull364_progempty128_512x36.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="sync_fifo_progfull364_progempty128_512x36.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1413798464" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1413798464">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4882624794146154400" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5129289728832644576" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2610546607946003280" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.ngc b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.ngc
deleted file mode 100644
index 17436be..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$51144<,[o}e~g`n;"2*73>(-80!<m4/+])[WGIOL*!=6>:;123452739:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456788:0<=>?0123<56789:;==5?02C046G78::8<>>7;12A656A8=1;54>>;03b?42=AGZ^X7OKDSCQ@DBCZ5;86=0>a:37>LHW]]0JHI\MWSCG@W:6;3:5=95>6;KMTPR=L@KOE1?::1<20>712@D[YY4KICFJ843=87;>7<85OTVSQQ<CGHND0<;50?36?40=G\^[YY4KOCFL843=87;87<4FNQWW>WC@KLK7<7>11292>LHW]]0YIJMJB=294;76380BB][[:SQWE96=87;:7<4FNQWW>WUSJ5:1<3?420;86?OIX\^1MIJ]AUKFLLAO480;2<742;KMTPR=IMNYNYGJHHEK84<768>0>7GAPTV9@LVFL@Z7=7>11591>LHW]]0OE]LKIQ>2>586=281CXZ_UU8GKUGCGY6:6=0>5:09KPRW]]0OC]LKOQ>2>586;29=6D@_UU8GMKG;;<0;2<=4378JJUSS2MCEN1=::1<26>512@D[YY4kio>01?699<18:7AZTQWW>AIR\H6897>114902?IR\Y__6IAZTC>01?699=18:7AZTQWW>air|59>6=0;;563046<<3CE\XZ5WDC?7?69991?6D@_UU8TAG:4294:7;<46@682DGF02<JMLONA@33?3GFIHKJMLONA@CBEc=1~er:?=zif5:7)6773>LMJKHIFGDEBC@AN88047GAPTV9S@DPM5=1<3?4959:45?6:231EC^ZT;CG@WG;03:5=?56:HLSQQ<FLMXI054?>058=?IR\Y__6_JNDEPFGF:?294974O;;8CBE7=F>=1JM;O7;@CBE3GFI8:0MLONA@CB2DGFIHKJ46OKDSC?4;><IMNYM1?18:CG@WG;:720MIJ]A=1=<>GCL[K78364AEFQE93902KOH_O36?:8EABUI5=5m6OKDSC?<?6902KOH_O38?g8EABUI[NJHI\30?d8EABUI[NJHI\311<e?DBCZHXOMIJ]<03=b>GCL[KYHLJKR=31:47<IMNYM_JNDEP?56<76o1JHI\NRECG@W:6;7o0MIJ]ASFB@AT;97o0MIJ]ASFB@AT;:7o0MIJ]ASFB@AT;;7o0MIJ]ASFB@AT;<7o0MIJ]ASFB@AT;=7o0MIJ]ASFB@AT;>7o0MIJ]ASFB@AT;?7o0MIJ]ASFB@AT;07o0MIJ]ASFB@AT;17l0MIJ]AUKFLLAO494:=6OKDSCWM@NNOA6:6=0i;@FGVDRNMACLD1?18:CG@WD;8720MIJ]B=3=<>GCL[H7>364AEFQF95902KOH_L34?:8EABUJ5?546OKDS@?2;><IMNYN191a:CG@WD;03:546OKDS@?<;`<IMNYNYGJHHEK858692KOH_L[IDJJCM:6294m7LJKRCVJAMO@@5;5i6OKDS@TVDBCZ5:5j6OKDS@TVDBCZ5;;2k5NDEPASWGCL[6:=3h4AEFQFRTFLMX7=?0>1:CG@WDPZHNO^1?<:1<e?DBCZK]YMIJ]<01=a>GCL[H\^LJKR=3=a>GCL[H\^LJKR=0=a>GCL[H\^LJKR=1=a>GCL[H\^LJKR=6=a>GCL[H\^LJKR=7=a>GCL[H\^LJKR=4=a>GCL[H\^LJKR=5=a>GCL[H\^LJKR=:=a>GCL[H\^LJKR=;=7>GKD01J_T@L_SGD53=EEDUBBKAPAEFQAVUXZHDLI55MUR]JJCI63J80OH?=;BJFGNYKAJOE_HQ[YQG1?FO33JF@<;5LLJ3;43=DDB8<<85LLJ0[<>EKC;R:4=;4CMI:41=DDBK>7NBDA058GIMF9M8<7NBDA0F73>EKCH;O445LLJCQ@FJL<2IGGO;4CMIA5<=DDBH\^NBD5:AOOF723JF@H<;4CMIGRf=DDBN]SIGYIEG6?FJLNQ20OAEIX0:37>EKZ01HC@CFTUGG51=DG[OTKH@JR@VJKKYNFOE<7N\JAUGG5>B03MHBXH\]d:FFHD_BLV]YEYK=;EK;?AOFL@6;245KI@FJ846912NBMIG310<:?AOFL@6:>374DHCGM974601OELJF<06=f>BNIMC7=84?>89GMDBN48?546JFAEK?5;><L@KOE1<18:FJEAO;;720HDOKI=6=<>BNIMC79364DHCGM90902NBMIG37?:8@LGCA52546JFAEK?=;><L@HOE1>19:FJFAO;99427IGMDH>25;?<L@HOE1?=>89GMGBN489556JFBEK?518e3MCIHD2>5;2==>BNJMC7=807;EKA@L:6611OEOJF<3<;?AOEL@68255KICFJ818?3MCIHD2:>99GMGBN4?437IGMDH>4:==CAKNB0507;EKA@L:>6>1OECO30?:8@LHF48:546JFN@>25;><L@DJ0<<18:FJJD:6;720HD@N<06=<>BNFH6:9364DHLB840902NBBL2>7?:8@LHF482546JFN@>2=;1<L@DJ0<07;EKME947611OECO320<;?AOII589255KIOC?668?3MCEM1<;>99GMKG;:<437IGAA=05:==CAGK7>:07;EKME94?611OECO328<4?AOII58546JFN@>04;><L@DJ0>?18:FJJD:4:720HD@N<21=<>BNFH6883o4DHLB863=8720HD@N<27=3>BNFH682:5KIOC?0;1<L@DJ0808;EKME909?2NBBL28>69GMKG;07=0HD@N<8<4?AOIJ5:546JFNC>24;><L@DI0<?18:FJJG:6:720HD@M<01=<>BNFK6:8364DHLA843902NBBO2>6?:8@LHE48=546JFNC>2<;><L@DI0<717:FJJG:6611OECL321<;?AOIJ58:255KIO@?678?3MCEN1<<>99GMKD;:=437IGAB=06:==CAGH7>;07;EKMF940611OECL329<;?AOIJ5822:5KIO@?6;><L@DI0>>18:FJJG:49720HD@M<20=<>BNFK68?364DHLA8629i2NBBO2<5;2=<>BNFK689394DHLA86803MCEN1:17:FJJG:26>1OECL36?58@LHE4>4<7IGAB=:=3>BNFK622l5KIQCGMU:76j1OE]OKIQ>2>58f3MC[MIG_<0<b?AOWJMC[0=0l;EKSFAOW480;2l5KIQ@GMU:6611OCLJ@<1<:?AIFLF6:<374DNCGK976601OCLJ@<00==>BHIME7=>06;EMB@J:6<7h0HBOKO=36>58>3MEJHB2>5?:8@JGCG5;546J@AEM?6;><LFKOC1=18:FLEAI;<720HBOKO=7=<>BHIME7:364DNCGK91902NDMIA38?:8@JGCG535;6J@A^PFC==CGKND0=06;EMA@J:68730HBLKO=32:<=CGKND0<<19:FLFAI;9:427IAMDN>20;d<LFHOC1?::1<:?AIELF6:9364DN@GK97902NDNIA32?:8@JDCG59546J@BEM?0;><LFHOC1;18:FLFAI;>720HBLKO=5=<>BHJME74364DN@GK9?9?2NDNR\JG`9GKUGCGY6;2n5KOQCGKU:6294j7IA_AEMS848f3ME[NIA_<1<`?AIWJME[0<4?>`9GKUDCGY6:255KOTVB858>3ME^XL2>0?;8@JSSI5;:245KOTVB844912NDYYO312<:?AIR\H6:8374DNWWE972601OCXZN<04==>BH]]K7=:06;EMVPD:60730HB[[A=3::==CG\^J0<06;EMVPD:58730HB[[A=02:<=CG\^J0?<19:FLQQG;::427IAZT@>10;?<LF__M1<:>89GKPRF4;<556J@UUC?628>3ME^XL2=8?;8@JSSI582255KOTVB878>3ME^XL2<0?;8@JSSI59:245KOTVB864912NDYYO332<:?AIR\H6883l4DNWWE95229427IAZT@>01;><LF__M1=18:FLQQG;<720HB[[A=7=<>BH]]K7:364DNWWE91902NDYYO38?:8@JSSI53546J@UU@?4;?<LF__N1??>89GKPRE48;556J@UU@?578>3ME^XO2>3?;8@JSSJ5;?245KOTVA843912NDYYL317<:?AIR\K6:;374DNWWF97?601OCXZM<0;=<>BH]]H7=374DNWWF947601OCXZM<33==>BH]]H7>?06;EMVPG:5;730HB[[B=07:<=CG\^I0?;19:FLQQD;:?427IAZTC>13;?<LF__N1<7>89GKPRE4;3546J@UU@?6;?<LF__N1=?>89GKPRE4:;556J@UU@?778>3ME^XO2<3?;8@JSSJ59?2o5KOTVA863=8730HB[[B=16:==CG\^I0>07;EMVPG:3611OCXZM<4<;?AIR\K6=255KOTVA828?3ME^XO27>99GKPRE40487H@N7:GMEWBBF:1NBO94EO@TV@H682L>O9HIC5D645@A89?0JLB\E39E@6=ALJ>0JIMJ3:DGT1=ALYO:<6HI01DE45@A89LI<?:4FG560>@ANL;;7KHIFGDEB2@ANOLMJ<>4FGDEBC@ANOLMJKHJ1:E0?BHC92C97D>=;H31?L453@997D:=;H7;?LHN\YU;<55FNHVS[57?3@DBX]Q?299JJLRWW9937D@FTQ]30==NF@^[S=;7;HLJPUY7>11BBDZ__15:?LHN\Z^JXH94IOKW[5603@DBXR>>7:KMMQY7:>1BBDZP0258MKOSW9><7D@FT^263>OIA]U;::5FNHV\421<AGC_S=68;HLJPZ6>?2CEEYQ?A69JJLRX8K=0ECG[_1A4?LHN\V:O;6GAIU]3A2=NF@^T<K94IOKW[4603@DBXR?>7:KMMQY6:>1BBDZP1258MKOSW8><7D@FT^363>OIA]U:::5FNHV\521<AGC_S<68;HLJPZ7>?2CEEYQ>A69JJLRX9K=0ECG[_0A4?LHN\V;O;6GAIU]2A2=NF@^T=K94IOKW[7603@DBXR<>7:KMMQY5:>1BBDZP2258MKOSW;><7D@FT^063>OIA]U9::5FNHV\621<AGC_S?68;HLJPZ4>?2CEEYQ=A69JJLRX:K=0ECG[_3A4?LHN\V8O;6GAIU]1A2=NF@^T>K94IOKW[6603@DBXR=>7:KMMQY4:>1BBDZP3258MKOSW:><7D@FT^163>OIA]U8::5FNHV\721<AGC_S>68;HLJPZ5>?2CEEYQ<A69JJLRX;K=0ECG[_2A4?LHN\V9O;6GAIU]0A2=NF@^T?K84IOKW[D0<AGC_SO74IOKW[COKMm1BBGKLTE@JP@TUl2CEFHM[SCKWAWT43@D]>6BF6:NLEACC>2FDOFKK7:NLCLEFD=1GYY<;;MWW71=K]]>?7A[[559OQQ023DYLCC;4MTZ@]f=JiceyZh||inl`?Hoig{\n~~g`n39M47=I9;1E>?5A639M<2=IM]]D^F:4NNLF5>I6?2E[XDCFZD]SVLKN\@\N_R@HC09Sg>V):9;8==?<_M68TDTSi2ZBBRLZSHF[f>VNFVH^_COBE89SOZNK]]DF?6^]E79SWAIIM81Z46\NMC3;A4><ZHGTABJJc:PGEABUMJI7<3m4RECG@WCDK5;5o6\KAEFQAFE;:7i0^IOKDSG@G959k2XOMIJ]EBA?0;e<ZMKOH_KLC=7=g>TCIMNYINM36?a8VAGCL[OHO191e:PGEABUMJI747>1c:PGEABUMJI743?6;SFB@ATXKFFGE^G@N^JTGJHAANk0^HOK_GKQWQe<ZLKOSZGKTI]Bg>TBIMU\EIZG_C78V@ADMk1YIJMJA=294;?<ZLMHIL2?>c9QABEBI[OLOH84RDE@AGd<ZLMHIO2?:1<:?WC@KLH7<3j4RDE@HNGUL[IGG:5]EFAOOG?<ZZ^J0=4?>69QWQG;8730^^ZM<183:2=U[]H7<3j4RRVQEHGU[]XJA:5]SUPBIGb<ZZ^YIJO]SUPFC2=U[]XNKO?>;SQWV@AXX[CD^DZV_@32?WUSZLMT\_G@RHVZ[G7<[11XM[KKAUC4?VDN\LXY?6]KP038WMTBOVOSX_OLT^LDG`=T@[OLS@GA_RKYA45<[@GTOBBCIRKLJZEOMJAj7^GB_EGUMFC?3ZAB\R^FN79PKPTDM>1X^[OC_@58WWPFDVH=7^ZNTTQ7?QTRM=1_U]K7a:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'m{i#|kpd-NeabX{U{by|Pre]sea]>UVxoS}`{r^kmrZvflR3VSljk_3]LQQYdq5:54l5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(`xl$yh}k M`fg[rtXxg~ySjPp`fX=XYulVzexQfnw]sea]>UVkohR<POTV\g|:661k0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-cuc)zmzn#@okd^uq[uhszVxoS}ok[8_\vaYwf}xTecxPp`fX=XYflmU9SB[[_b{?6;>f3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&GjhiQxr^rmpwYulVzjhV7R_sf\tkruW`d}S}ok[8_\eabX:VE^XRmv<2<;e>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#ie/pgt`)JimnT{Qnup\vaYwimQ2QR|k_qlwvZoi~VzjhV7R_`fg[7YH]]Uhu1:18`9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$l|h }dqg,IdbcW~xT|cz}_sf\tdb\1TUyhR~ats]jjsYwimQ2QRokd^0\KPRXkp6>25o4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)oyo%~i~j/Lcg`ZquWyd~R|k_qcg_<[XzmU{by|Piot\tdb\1TUjhiQ=_NWW[f;>72j7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"Cnde]tvZvi|{UyhR~ndZ;^[wbXxg~ySd`y_qcg_<[XimnT>RAZT^az828?i2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/esa+tcxl%FmijPws]sjqtXzmU{miU6]^pg[uhszVcezR~ndZ;^[dbcW;UDYYQly=:=<g=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ hpd,q`uc(EhnoSz|Ppovq[wbXxhnP5PQ}d^rmpwYnfU{miU6]^cg`Z4XG\^T`xz31?:a?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*KflmU|~R~ats]q`ZvflR3VSjPpovq[lhqWykoW4SPaef\6ZIR\Vf~x1<18c9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$l|h }dqg,IdbcW~xT|cz}_sf\tdb\1TUyhR~ats]jjsYwimQ2QRokd^0\KPRXd|~7?36m;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&nzn"je.Ob`aYpzVzexQ}d^rb`^?ZW{nT|cz}_hlu[ugcS0WTmijP2^MVPZjr|5>54o5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(`xl$yh}k M`fg[rtXxg~ySjPp`fX=XYulVzexQfnw]sea]>UVkohR<POTV\hpr;=72i7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"Cnde]tvZvi|{UyhR~ndZ;^[wbXxg~ySd`y_qcg_<[XimnT>RAZT^nvp9090k1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,dt`(ulyo$Aljk_vp\tkruW{nT|ljT9\]q`Zvi|{Ubb{QaeY:YZgclV8TCXZPltv?3;>e3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&GjhiQxr^rmpwYulVzjhV7R_sf\tkruW`d}S}ok[8_\eabX:VE^XRbzt=:=<g=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ hpd,q`uc(EhnoSz|Ppovq[wbXxhnP5PQ}d^rmpwYnfU{miU6]^cg`Z4XG\^T`xz39?:a?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*KflmU|~R~ats]q`ZvflR3VSjPpovq[lhqWykoW4SPaef\6ZIR\Vrd~1?18c9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$l|h }dqg,IdbcW~xT|cz}_sf\tdb\1TUyhR~ats]jjsYwimQ2QRokd^0\KPRXpfx7>36m;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&nzn"je.Ob`aYpzVzexQ}d^rb`^?ZW{nT|cz}_hlu[ugcS0WTmijP2^MVPZ~hz5954o5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(`xl$yh}k M`fg[rtXxg~ySjPp`fX=XYulVzexQfnw]sea]>UVkohR<POTV\|jt;<72i7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"Cnde]tvZvi|{UyhR~ndZ;^[wbXxg~ySd`y_qcg_<[XimnT>RAZT^zlv9390k1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,dt`(ulyo$Aljk_vp\tkruW{nT|ljT9\]q`Zvi|{Ubb{QaeY:YZgclV8TCXZPxnp?2;>e3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&GjhiQxr^rmpwYulVzjhV7R_sf\tkruW`d}S}ok[8_\eabX:VE^XRv`r=5=<g=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ hpd,q`uc(EhnoSz|Ppovq[wbXxhnP5PQ}d^rmpwYnfU{miU6]^cg`Z4XG\^Ttb|38?:a?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*KflmU|~R~ats]q`ZvflR3VSjPpovq[lhqWykoW4SPaef\6ZIR\Vrd~1715g9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$l|h }dqg,[k67=8Ubb{Q\W142?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*bnnoU{by|Pp`f?5;063\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&nbjkQnup\tdb;:7<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"jffg]sjqtXxhn7?38>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&nzn"je.fjbcYwf}xT|lj34?42?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*bnnoU{by|Pp`f?1;063\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&nbjkQnup\tdb;>7<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"jffg]sjqtXxhn7;38>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&nzn"je.fjbcYwf}xT|lj38?42?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*bnnoU{by|Pp`f?=;073\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&nbjkQnup\tdbX9?:0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-cuc)zmzn#igif^rmpwYwimU9:=5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(`xl$yh}k dhde[uhszVzjhR=90:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'m{i#|kpd-gmc`Xxg~yS}ok_543?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*bnnoU{by|Pp`f\136<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!gqg-vavb'mcmjR~ats]seaY1>91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,dt`(ulyo$hdhi_qlwvZvflV==<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+awm'xo|h!kigd\tkruWykoS58?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&nzn"je.fjbcYwf}xT|ljP94f8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%k}k!rerf+uthoVof|ywPi768Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%k}k!rerf+uthoVof|ywPi^pppuis>11^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,dt`(ulyo$|ah_dosp|YnW{y|bzPSV26g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#ie/pgt`)uidUyhRka_h7`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*tfeV}ySh`Pi708Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%k}k!rerf+rtXxg~ySjPp`f?4;043\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&}yS}`{r^pg[ugc494:4?5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(`xl$yh}k ws]sjqtXzmU{miU6]^pg[uhszVcezR~ndZ;^[dbcW;UDYY2>>908Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%k}k!rerf+rtXxg~ySjPp`fX=XYulVzexQfnw]sea]>UVkohR<POTV?6;>53\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&}yS}`{r^pg[ugcS0WT~iQnup\mkpXxhnP5PQnde]1[JSS4:43>6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+awm'xo|h!xr^rmpwYulVzjhV7R_sf\tkruW`d}S}ok[8_\eabX:VE^X1:1839V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$l|h }dqg,swYwf}xT~iQaeY:YZtcWyd~Rgav^rb`^?ZWhnoS?Q@UU>6:=4<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!gqg-vavb'~xT|cz}_sf\tdb\1TUyhR~ats]jjsYwimQ2QRokd^0\KPR;>7297X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"y}_qlwvZtcWykoW4SPre]sjqtXag|T|ljT9\]b`aY5WF__0:072:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'m{i#|kpd-tvZvi|{UyhR~ndZ;^[wbXxg~ySd`y_qcg_<[XimnT>RAZT=:=<7=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ hpd,q`uc({U{by|Pre]sea]>UVxoS}`{r^kmrZvflR3VSljk_3]LQQ:>6?:0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j;$k`{w.bcqv|hb|5:5:=5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$o<!hmtz-gdtuqgo0<090:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'xxx~!l1.enq}(di{xrbhz32?43?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.a2+bkrp'ij~waeu>0:37<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!rrvp+f7(ods"jcT0\,di4(j9?;0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j;$k`{w.foX5X(`ez$f;?4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#n? glw{*bk\:T$la~ bs738Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b3,chs&ngP?P hmr,nw37<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!rrvp+f7(ods"jcT4\,div(j{<?0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j;$z<2?>448Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b3,r4:768?>7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*wus{&i:#{?31?75?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.a2+s7;97;>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+tt|z%h="x><3<62>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#||tr-`5*p64;4:985Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$o<!y1=1=13=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g4)q9595=8;4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#n? v0>7:00<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!rrvp+f7(~86?2<8?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"m=/fov|+efz{seiy2?>728Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b0,chs&jky~t`jt=3=25=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g7)`e|r%ol|}yogw878182_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/pppv)d:&mfyu laspzj`r;;7<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*wus{&i9#jczx/en_5[)od;%a<8>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"m=/fov|+ajS8W%k`}!mr42?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.a1+bkrp'mfW?S!glq-iv063\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.sqww*e5'ng~t#ib[2_-chu)ez<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*wus{&i9#jczx/en_1[)ody%a~;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"m=/w3?4;313\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.sqww*e5';7<3?:5:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'xxx~!l2.t28482>2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/pppv)d:&|:0<0>549V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$yy} c3-u5949=?1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(k;%}=1<11478Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b0,r4:46<<0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j8$z<2<>076?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.a1+s7;<7?=7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*wus{&i9#{?34?366>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#||tr-`khv7=;1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(kfg{=;j4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#jafnf]fiur~Weojzd`h_dosp|YHZV<Tc;k4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#jafnf]fiur~Weojzd`h_dosp|YHZV<Tc<;m;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"|nm^gntqXnkUb955Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$~lcPelrw}Zo3n2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#ob_sf\akYn9<=0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}d^rmpwYwd|y:0=0Piot4`>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!Baef\cf6)kfexV6R_FLG[743WfUjhiQ?_NWW[}iu494:=RGAV^243>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!Baef\cf6)kfexV6R_FLG[743WfUjhiQ?_NWW[}iu484:=:94U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'DkohRil0/alqkr\0TULBIQ=25]l[dbcW9UDYYQwos>1:470?2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-NeabXoj:%ob{atZ:^[BHCW;8?SbQnde]3[JSSWqey0>0>1658Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#@okd^e`4+eh}g~P4PQHNE]161YhWhnoS=Q@UU]{kw:368;<;6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)JimnTkn>!cnwmp^>ZWNDOS?<;_n]b`aY7WF__Sua}<4<2521<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/Lcg`Zad8'idyczT8\]DJAY5:=UdSljk_1]LQQYg{6=2<?88:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%FmijPgb2-gjsi|R2VSJ@K_307[jYflmU;SB[[_ymq838698=<7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*KflmUlo= lotlw_=[XOGNT>?:Po^cg`Z6XG\^Ttb|37?3232=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| M`fg[be7&je~byU7]^EM@Z45<VeTmijP0^MVPZ~hz525=<;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?4;323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~7=3;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?6;323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~7?3;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?0;323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~793;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?2;323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~7;3;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?<;0d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~P4PQHNE]161YhWhnoS=Q@UU>2:3e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}Q3QRIAD^010ZiXimnT<RAZT=0=2f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|R2VSJ@K_307[jYflmU;SB[[<2<5g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsS1WTKCJP236\kZgclV:TCXZ34?4`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkr\0TULBIQ=25]l[dbcW9UDYY2:>7a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjq]?UVMEHR<=4^m\eabX8VE^X1816b9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmp^>ZWNDOS?<;_n]b`aY7WF__0:09c:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw_=[XOGNT>?:Po^cg`Z6XG\^743;;;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\402<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}U:995Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{at^060>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsW:??7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*ad8'idyczP4468Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjqY2==1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexR8:4:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw[2333\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~T4864U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu]g5979=11^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexRj><3<6<>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsWm;7?3;7;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\`4:36<20Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+be7&je~byQk1=7=1==R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|Vn:0;0:8:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw[a7;?7?37X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*ad8'idyczPd0>;:01<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}Uo=R?:7:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw[a7X:<=0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+be7&je~byQk1^163>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsWm;T8894U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu]g5Z32?2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-dg5(dg|dSi?P6458Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjqYc9V=>;6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{_e3\<<6<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!gqd-swva'DkohRy}_qlwvZvk}z;T|ljT9\]q`Zvi|{U|~Rgav^rb`^?ZWhnoS?Q@UU]`}969191^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$Aljk_vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVPZe~4842<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!Baef\swYwf}xT|a{|1^rb`^?ZW{nT|cz}_vp\mkpXxhnP5PQnde]1[JSSWjs7>37?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&nzm"z|f.Ob`aYpzVzexQltq2[ugcS0WT~iQnup\swYnfU{miU6]^cg`Z4XG\^Tot2<>828Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%k}h!wsre+HgclV}yS}`{r^roqv7XxhnP5PQ}d^rmpwYpzVcezR~ndZ;^[dbcW;UDYYQly=6==5=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^az808>82_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/esb+quxo%FmijPws]sjqtXxex=R~ndZ;^[wbXxg~ySz|Piot\tdb\1TUjhiQ=_NWW[f;>73;7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*bva&~x{j"Cnde]tvZvi|{U{`x}>_qcg_<[XzmU{by|Pws]jjsYwimQ2QRokd^0\KPRXkp6<24>4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)oyl%{~i/Lcg`ZquWyd~R~cur3\tdb\1TUyhR~ats]tvZoi~VzjhV7R_`fg[7YH]]Uhu161909V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$l|k xrqd,IdbcW~xT|cz}_qnvw4YwimQ2QR|k_qlwvZquW`d}S}ok[8_\eabX:VE^XRbzt=3==4=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^nvp949181^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$Aljk_vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVPZjr|5955<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(`xo$|~}h M`fg[rtXxg~yS}bzs0]sea]>UVxoS}`{r^uq[lhqWykoW4SPaef\6ZIR\Vf~x1:1909V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$l|k xrqd,IdbcW~xT|cz}_qnvw4YwimQ2QR|k_qlwvZquW`d}S}ok[8_\eabX:VE^XRbzt=7==4=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^nvp909181^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$Aljk_vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVPZjr|5=55<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(`xo$|~}h M`fg[rtXxg~yS}bzs0]sea]>UVxoS}`{r^uq[lhqWykoW4SPaef\6ZIR\Vf~x161909V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$l|k xrqd,IdbcW~xT|cz}_qnvw4YwimQ2QR|k_qlwvZquW`d}S}ok[8_\eabX:VE^XRbzt=;==4=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^zlv979181^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$Aljk_vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVPZ~hz5855<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(`xo$|~}h M`fg[rtXxg~yS}bzs0]sea]>UVxoS}`{r^uq[lhqWykoW4SPaef\6ZIR\Vrd~1=1909V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$l|k xrqd,IdbcW~xT|cz}_qnvw4YwimQ2QR|k_qlwvZquW`d}S}ok[8_\eabX:VE^XRv`r=6==4=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^zlv939181^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$Aljk_vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVPZ~hz5<55<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(`xo$|~}h M`fg[rtXxg~yS}bzs0]sea]>UVxoS}`{r^uq[lhqWykoW4SPaef\6ZIR\Vrd~191909V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$l|k xrqd,IdbcW~xT|cz}_qnvw4YwimQ2QR|k_qlwvZquW`d}S}ok[8_\eabX:VE^XRv`r=:==4=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^zlv9?9?91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$hdhi_qlwv^>ZWY]YS9>Po^grqdjX?Ve<?6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!kigd\tkruS1WT\Z\P41]l[`wrieU<Sb27>658Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%k}h!wsre+aoanVzexU7]^RTVZ27WfUn}xoc_6]l8=8X[^:==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!kigd\tkruWyko0<091:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'m{j#y}pg-gmc`Xxg~yS}ok<3<55>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#if/uqtc)caolT|cz}_qcg868192_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/esb+quxo%oekhPpovq[ugc4=4==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!kigd\tkruWyko08091:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'m{j#y}pg-gmc`Xxg~yS}ok<7<55>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#if/uqtc)caolT|cz}_qcg828192_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/esb+quxo%oekhPpovq[ugc414==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!kigd\tkruWyko04090:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'m{j#y}pg-gmc`Xxg~yS}ok_043?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"j~i.vpsb*bnnoU{by|Pp`f\636<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!gqd-swva'mcmjR~ats]seaY4>91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$hdhi_qlwvZvflV>=<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!kigd\tkruWykoS88?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&nzm"z|f.fjbcYwf}xT|ljP6728Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%k}h!wsre+aoanVzexQae]425=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(l`lmS}`{r^rb`Z>182_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/esb+quxo%oekhPpovq[ugcW0?h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*bva&~x{j"~}of]eqijXa?90Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hwrq-cu`){zm#}|`g^dvhiYnW{y|bz:c:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'m{j#y}pg-qehYulVoeSd;l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&nzm"z|f.pbiZquWldTe;l4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)oyl%{~i/vp\tkruWyf~<Qae>3:Zkffm;346[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!xr^rmpwYwd|y:S}ok[8_\vaYwf}xT{Qfnw]sea]>UVkohR<POTV?5;>?3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.fre*rtwn&}yS}`{r^roqv7XxhnP5PQ}d^rmpwYpzVcezR~ndZ;^[dbcW;UDYY2=>9:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%k}h!wsre+rtXxg~yS}bzs0]sea]>UVxoS}`{r^uq[lhqWykoW4SPaef\6ZIR\595455Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(`xo$|~}h ws]sjqtXxex=R~ndZ;^[wbXxg~ySz|Piot\tdb\1TUjhiQ=_NWW818?02_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/esb+quxo%|~R~ats]shpu6WykoW4SPre]sjqtX{Ubb{QaeY:YZgclV8TCXZ35?:;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"j~i.vpsb*quWyd~R~cur3\tdb\1TUyhR~ats]tvZoi~VzjhV7R_`fg[7YH]]6=2564U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)oyl%{~i/vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVP919011^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl${Qnup\tist9VzjhV7R_sf\tkruW~xTecxPp`fX=XYflmU9SB[[<9<;<>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#if/uqtc)pzVzexQltq2[ugcS0WT~iQnup\swYnfU{miU6]^cg`Z4XG\^7538?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m?/fov|+efz{seiy2?>728Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%{~z|/b2,chs&jky~t`jt=3=25=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ xsuq,g5)`e|r%ol|}yogw878182_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d8&mfyu laspzj`r;;7<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i;#jczx/en_5[)od;%a<8>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m?/fov|+ajS8W%k`}!mr42?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.a3+bkrp'mfW?S!glq-iv063\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e7'ng~t#ib[2_-chu)ez<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i;#jczx/en_1[)ody%a~;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m?/w3?4;313\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e7';7<3?:5:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l0.t28482>2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d8&|:0<0>549V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$|y} c1-u5949=?1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,twqu(k9%}=1<11478Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%{~z|/b2,r4:46<<0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hwrq-svrt'j:$z<2<>076?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.a3+s7;<7?=7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i;#{?34?354>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`5*aj}q$hm|vndv?4;073\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e6'ng~t#mnrs{maq:66?:0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hwrq-svrt'j;$k`{w.bcqv|hb|585:=5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$o<!hmtz-gdtuqgo0>091:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l1.enq}(`eR:V"jc>.l355>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`5*aj}q$laV?R.fop*hu192_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d9&mfyu hmZ0^*bkt&dy==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+qt|z%h="ibuy,di^5Z&ngx"`}91:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l1.enq}(`eR>V"jc|.lq61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`5*p6494>:6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+qt|z%h="x><1<210=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ xsuq,g4)q95;59;5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$o<!y1=3=503<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!wrvp+f7(~8692884U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)z~x#n? v0>1:4323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e6';7?3;9;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m>/w3?7;72=2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d9&|:090:6:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l1.t28186=;1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,twqu(kfg{<8<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)z~x#nabp07b?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.pbiZ`rdeUhc`l:a:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!}al]eqijXnkUb9:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$~lcPftno[l2a3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$~lcPws]fjZo6?j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,IdbcWnih<#il0/alqkr\0TULBIQ=36]l[dbcW9UDYYQwos>2:470k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-NeabXoji;"jm?.bmvjq]?UVMEHR<<7^m\eabX8VE^XRv`r=0=541d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.Ob`aY`kj:%kn>!cnwmp^>ZWNDOS?=8_n]b`aY7WF__Sua}<2<252e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%||cz}/Lcg`Zadk9$lo= lotlw_=[XOGNT>>9Po^cg`Z6XG\^Ttb|34?323f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| M`fg[bed8'mh<#m`uovX<XY@FMU9?:Q`_`fg[5YH]]Usc2:>034g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!Baef\cfe7&ni;"naznuY;YZAILV88;RaPaef\4ZIR\Vrd~181105g?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"Cnde]dgf6)oj:%ob{atZ:^[BHCW;9<SbQnde]3[JSSWqey0;0>105`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"Cnde]dgf6)oj:%ob{atZ:^[BHCW;9<SbQnde]3[JSSWqey0:0>16a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pxg~y#@okd^e`g5(`k9$hcx`{[9_\CKBX::=TcRokd^2\KPRXpfx743?>5`9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}6:28o4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'nih<#il0/alqkr;:7?j7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw8682i2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dgf6)oj:%ob{at=6=1d=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~by2:>4c8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pxg~y#jml0/e`4+eh}g~7:3;n;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphs4>4>m6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`kj:%kn>!cnwmp9>9?81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznuY;YZAILV88;RaPaef\4ZIR\5;5;<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(oji;"jm?.bmvjq]?UVMEHR<<7^m\eabX8VE^X1<1709V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}Q3QRIAD^003ZiXimnT<RAZT=1=34=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byU7]^EM@Z44?VeTmijP0^MVP929?81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznuY;YZAILV88;RaPaef\4ZIR\5?5;<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(oji;"jm?.bmvjq]?UVMEHR<<7^m\eabX8VE^X181709V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}Q3QRIAD^003ZiXimnT<RAZT=5=34=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byU7]^EM@Z44?VeTmijP0^MVP9>9=01^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]21<=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byQ=589V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}U8945Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(oji;"jm?.bmvjqY3=01^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]61<=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byQ9589V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}U<945Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(oji;"jm?.bmvjqY?=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5969=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5979=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5949=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5959=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5929=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5939=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5909=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5919=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g59>9=j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5Z62k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dgf6)oj:%ob{at^f2[43d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{_e3\60e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%||cz}/fa`4+ad8'idyczPd0]01f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byQk1^66g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!hcb2-cf6)kfexRj>_47`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dSi?P64a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pxg~y#jml0/e`4+eh}g~Th<Q85b9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}Uo=R6:3:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rtXxg~yS}bzs0>3:=7<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(okg%koch.f`ncd(iolih"och/flbplpbjdm%blzfvd]ahnYjmdUlic!yamkg*fusz=n0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$x`~Pr`o\vaYbf=o0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$x`~Pr`o\vaYbf8987X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)uidUyhRka329V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#ob_vp\ak323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&GfyuQ}d^pppZgtzlmTKCJP13]l[HS_W;Ud=<;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%yylck.Onq}YpzVxxxRo|rde\CKBX9;UdS@[W_0]l545c3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&XXXRHZLM]DAK2?3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&myyj>.fpppZ`rde$yyQk15:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+btt|m;%k}{_gwoh+tt|Vn9855Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae gsqw`4(`zz~Tjxbc.sqw[a53k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%ekz|krrv-cwus&{nT~~zPrde?4;2d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&dl{j}su,dvvr)zmUyyQ}ef>1:1d<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'gm|~i||t/eqwq(ulVxxxR|jg^27f>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h rrvahn)io~xo~~z!gsqw*wbXzz~T~hiP25a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+kapzmxxx#i}su,tvZtt|Vxnk1?14c9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#}{bmi,jbqul{y"j||t/uq[wusW{olS<=k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%yylck.pg[wusWhyyij:j;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%yylck.pg[wusWhyyijQHNE]26ZiXE\RT>Ra;0:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$~~zmlj-q`Ztt|Vkx~hiPd063?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!}su`oo*tcW{ySl}}ef]g66e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'{nT~~zPcnoa7a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(zmUyyQlol`27a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim({UyyQnssgd0`=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim({UyyQnssgd[BHCW88TcRCZX^3\k16<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'~xT~~zParpfcZb6<91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wusjea${Q}su]bwwc`Wm88o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!xr^pppZehek9o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"y}_sqw[fijj89m7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)pzVzex2?>^kmr4YNF_U;o6[\ES]UMVOEDL90ZNM6;WKFSZR^XL=0ZD\[EY45?RCF494=7ZKN<0<5?RCF4;437ZKN<283:3=PMH682;5XEC>3:3=PMK6:2;5XEC>1:==PMK686=09;VGA868?3^OI[H2?>99TAGQB48437ZKMWD>1:==PMK]N0>07;VGAS@:3611\IOYJ<4<;?RCE_L6=2l5XECUF82<7611\IOYJ<6<`?RTN\LUFCIKPAb9TVLRBWDEOIRLk;VPJP@YPAM^CSLj4WSKWAZQNL]BTN<j4XHNJJ]+_LK*;"<.\TT@#4+7'IZIBE85WOSAZ2>^T\ECI;6V\T^EM@2=_[]U]ONl4X^ALV@YNFOE=7Ujm_Hfe?]boWYxba[k}shmm55=_ldUFmga}Vdppmjh682RoaRCfnnpUawungg90T~z<;Xgp<d=XWVRGB@QP_1]\[P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"Cnde]dgf6)oj:%ob{atZ:^[BHCW;9<SbQnde]3[JSSWqey090>1978[ZY_DGGTSR?P_^W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%FmijPgb2-gjsi|R2VSJ@K_307[jYflmU;SB[[_ymq818691k0SRQWLOO\[Z4XWV_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-NeabXoji;"jm?.bmvjq]?UVMEHR<<7^m\eabX8VE^XRv`r=5=54>23VUTTA@B_^]0[ZYR8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| M`fg[be7&je~byU7]^EM@Z45<VeTmijP0^MVPZ~hz5=5=<6n;^]\\IHJWVU?SRQZ0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(EhnoSjml0/e`4+eh}g~P4PQHNE]172YhWhnoS=Q@UU]{kw:568;396QP_YNMIZYX=VUTY=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+HgclVmh<#m`uovX<XY@FMU9>9Q`_`fg[5YH]]Usc2=>036`>YXWQFEARQP6^]\Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uidUyhRka_h357>YXWQFEARQP7^]\Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+HkrpV}yS}{_`qqabY@FMU:>RaPMTZ\5Zi69?90SRQWLOO\[Z>XWV_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%FaxvPre]qwqYf{{olSJ@K_00\kZKRPV8Tc<?>8:`ooZkbeVmnbRijndpjgZet|{;=7obd_lgn[bciWyxbaRyfduj2f>dkcVgnaRijn^rqmhYpzhz{iQy6g9ahnYjmdUlicQ{oq37?gjlWdofSjka_w5\5Z~t|890naePmdo\mkvr|Vhgcne>4:`ooZkbeVe~x}{{_cnlgn5<kea<7nabp`pf7>bce?1oec2?>69gmk:687=0hd`310<4?aoi4885;6jfn=30:2=cag6:8394dhl?50803mce0<817:fjj9706>1oec2>8?58`lh;904=7iga<0<4?aoi4;:5;6jfn=02:2=cag69>394dhl?66803mce0?:17:fjj9426>1oec2=6?58`lh;:>4<7iga<3:=3>bnf5822;5kio>1:2=cag68<394dhl?74803mce0><17:fjj9546>1oec2<4?;8`lh;;<0;2:5kio>01;0<l`d7?384dhl?0;0<l`d79384dhl?2;0<l`d7;384dhl?<;0<l`d75394dnww858?3me~x1??>99gkpr;98437iazt=31:==cg|~7=>07;emvp973611ocxz314<;?air|5;=255kotv?528?3me~x1?7>99gkpr;904<7iazt=3=<>bh}}69<364dnww877902ndyy2=2?:8`jss4;9546j`uu>10;><lf0?;18:flqq:5>720hb{{<35=<>bh}}694364dnww87?9?2ndyy2=>99gkpr;;9437iazt=12:==cg|~7??07;emvp954611ocxz335<b?air|59>6=07;emvp9526>1ocxz33?58`jss4=4<7iazt=7=3>bh}}6=2:5kotv?3;1<lf0508;emvp9?9=2of|yw>6:djbjY`mgoymya}_scnbl`h9;1mekaPgdlfvdrhzV~d|<=4fhdl[bcim{kcQy9^11b>`nnfUlick}aumq[s?X;%*Seagax!ALV@&@mgoymya} 06-341<n`ldSjkaescwkwYq1V9Tt~z;;gwoh<=nfySobd6:ofijt~02dloo{fle08jjg<g|~{yyQmljc8twi`Wlg{xt74psmd[cskd:80~lcconrX4X(uid$y#{8Pnnkmmq(uid%XH] XIEG\TWOJ91$ym`l4re]amkYdf}x>7jPeo:8vaYkgnch46|k_qg\wv753{nTyo{ur]ehdatWzy:=6|jsdv\fimXzhgmeka<;sqw6<=tqgiTjdh`_qplccskd:<?S}|`gdosp|750V?:>u=911f1?vikVlbjbQrneeqij4>=U{~bijmqvz57>X=88s?;"iigm\c`hbzh~d~Rx6_2.xgZgclVdloRm`nrvqelhs59&hSl~lhabpliiW}s{iRowir?3(fYfxyfbolzfoo]w}ucXzhic1="l_`rshlef|`eeSywe^pggm;7$jUj|}bfc`vjkkYsqyoT{lmg=1.`[dvwd`ijxdaa_u{saZqcka7; nQnpqnjgdrnggUu}kPwsak95*dWhrbSljkr^uj`qn:;;&hSlvf_`pvw`tX`nd0?#c^c{mZgp}zoySzgkti?2(fYfp`Uiy~k}_vkgpm;6$jUjtdQkauc\slbs`4<? nQnxh]j`Zqnl}b68!mPayk\vpubzV}bhyf21-a\e}oX|pzn1="l_`zj[rstm{U|eizg=0.`[d~n{V~omyoPwhfwl803$jUjtd}PtegppZqnl}b68!mPaykp[qocW~coxe37,b]b|luX|bon|Ryfduj>0)eXiqcxSy}{rc]tmaro5=&hSlvfs^vvw`tX`nd0:#c^c{mvYsqyo6<!mPcnonkkYddfi`1<"l_bmvjqYsqyo6<!mPd`vb[firf}U|eizg=8.`[acai|fS{ocud?Ahdhl[}xbbj"l_ekm[roc|a78:!mPdhl\slbs`Vkse~3>,b]gmkYpam~cSolh<11(fYcagU|eizg_sf`l803$jUoecQxievk[rgd`499 nQkio]tmaroW~nhd08;,b]gmkYpam~cSz|lh<0/gZbh}}UyyQyam?3(fYcg|~T{dj{h<15(fYbfhhgiR|cobq>4)eXmgki`hQ}su]p}ke:9%iTi|`r^kmn`esafdTxt~j=1.`[`tug{Ubbgklthmm[qwmVkse~3?,b]fvwiuW`dainzfoo]w}ucXzhic1="l_dpqkwYnfcohxdaa_u{saZtcka7; nQjrsmq[lhmmj~bccQ{yqg\sdeo59&hSh|}os]jjocd|`eeSywe^uggm;7$jUn~a}_hliafrnggUu}kPwsak95*dWokfeaw2vhpwa}0+kVl~`aQil`ep[wusWkg1<"l_icp[djjgz~Ti`~{y<2/gZnf{Vkgab}{_gwoh86+kVbjRowi^cqqvcu59&hSeo|_`zj[dqr{lx6<!mPh`q\e}oXj|yn~0>#c^jbwZgaVxoSnfnnogo95*dWakxSlvf_swpaw;7$jUcm~Qnxh]tvZeoigdn`0>#c^jbwZgaV}~h|20-a\lduXiqcxSyjnt`?3(fYoizUjtd}Ptegpp86+kVbjRowir]wma;7$jUcm~Qnxhq\pncbx4:'oRfns^c{mvYsdhy1="l_icp[d~n{V~yiljv=0.`[mgtWhrbRz|ts`>4)eX`hyTmug|_uwpaw;7$jUcm~Qmabivt86+kVbjRjnt`]`kphs59&hSeo|_ecweZeh}g~xSlvfs<2/gZnf{VnjxlQlotlwwZtfka7; nQgar]geqgXkfex~Q}dbj>4)eX`hyThlzn_bmvjquXhic1="l_icp[agsiVidycz|_vf`l86+kVbjRjnt`]`kphs{V}yoe3?,b]kevYnf}Uh`f3?,b]kevYjiz~n~Rmj=1.`[mgtWdofecg{_gkoa86+kVbjRayesdokr;7$jUcm~Qrne\big`{Vkse~3?,b]kevYwzfmTjaohs^pbgm;7$jUcm~Qrne\big`{Vxooe3?,b]kevYwzfmTjaohs^ubgm;7$jUcm~Qrne\big`{V}ooe3?,b]kevYwzfmTjaohs^uqgm;7$jUcm~Q}d^fbpdYdg|d1="l_icp[wbXzz~6<!mPh`q\vvr:9%iTdl}PsmcuaZeb59&hSeo|_rppp86+kVbjR{addpehjq:8%iTdl}Pv`nj`86+kVbjRy}_`ah95*dWakxSz|Pd`vb[firf}7; nQgar]tvZtt|4:'oRgbpmgnakrf|`eeSywe<2/gZojxeoficznthmm[qwmVkse~3>,b]jiujbeldmyg`n^vzt`Yuijb6=!mPilroahci|h~bccQ{yqg\vaeo58&hSdcldofjqgsafdTxt~j_vc`l87+kVcf|akbeovbpliiW}s{iRykci?2(fYneyfnah`{aukljZr~xlU|~nf21-a\mkosW~xT|cz}_wco95*dW`dihncd]w}uc:8%iTahc`rx]w}uc:9%iTadhPfhnf[kgjm4Hgmce\tskmc)eXezmdbRxnl<3/gZiw|`gbvlzfoo]nkac:8%iTc{k}fmmt[iip59&hS}|jlncg[igsmgir1<"l_qpfhjgcW{ol0>#c^rqmhYaaoeTxt~j=431|60+kVzycjQjmqvz[qnumzbTm~}jru]uei;6:1&hS}|`g^gntqX|axneQnsrgqpZpfdVkse~3>030/gZvugnUna}zv_ujqavnXizyn~yQyam]qefn:9989 nQrne\ahvsqV~c~h}g_`qpawrX~hfT~img=0216)eXx{elShctx]wlwct`Vkxh|{_wco[rgd`4;;>?"l_qplcZcjx}sTxe|jsi]bwvcu|V|j`Rykci?2474+kVzycjQjmqvz[qnumzbTm~}jru]ueiYpzjb6==<=,b]svjaXmdzuRzgrdqk[kc`i}oTzlb213;/gZvugnUna}zv_u{sa87+kVzycjQjmqvz[qwmVkse~3?,b]svjaXmdzuRzvpd]qefn:8%iT|ah_dosp|YsqyoT~img=1.`[uthoVof|ywPtxrf[rgd`4:'oR~}of]fiur~W}s{iRykci?3(fYwzfmTi`~{y^vzt`Ypzjb6<!mPpsmd[cskdV~c~h}g_`qpawrX~hf6?;:#c^rqkbYa}efTxe|jsi]bwvcu|V|j`Rowir?2475+kVzycjQiumn\pmtb{aUj~k}t^tbhZtfka7:<?=#c^rqkbYa}efTxe|jsi]bwvcu|V|j`R|kci?2475+kVzycjQiumn\pmtb{aUj~k}t^tbhZqfka7:<?=#c^rqkbYa}efTxe|jsi]bwvcu|V|j`Rykci?2475+kVzycjQiumn\pmtb{aUj~k}t^tbhZquka7:<?=#c^rqkbYa}efTxe|jsi]mabgsmV|j`0=93-a\twi`Wog`Rzvpd?2(fYwzfmTjxbc_u{saZgaz7; nQrne\bpjkW}s{iR|nci?3(fYwzfmTjxbc_u{saZtcka7; nQrne\bpjkW}s{iRynci?3(fYwzfmTjxbc_u{saZqcka7; nQrne\bpjkW}s{iRy}ci?3(fYuijbTxt~j=1.`[wbXlh~jSnaznu]tmaro50&hSjPddrwl836:%iT~iQirds>5)eXzmU{by|Pwhfwl8?+kVxooeQ{yqg>4)eXzlmTagle^ol``Yfp`y6<!mPrde\wiodmVgdhhQ}abj>4)eXzlmTagle^ol``Yuljb6<!mPrde\wiodmVgdhhQxabj>4)eXzlmTagle^ol``Ypljb6<!mPrde\wiodmVgdhhQxrbj>4)eX{pdhdaai{gq[vrfol79 nQznegqbiipWee|1="l_tqf[fijefdTc{k}fmmt95*dW|ynSnabmnl\qkbbzofd{0>#c^wpaZbbnhgxR}jtukmcv;7$jU~hQkotv\vvr:9%iTy~kPeba>4)eX}zoTinmPaykp95*dW|ynShml_sc`l86+kVxiRklc^pggm;7$jU~hQjcb]tefn:8%iTy~kPeba\saeo59&hSx}j_da`[rtd`4:'oR{|e^gnf`bcmmUyij3?,b]vw`Yaaoe::Rhcafq>4)eX}zoTjzh{_ecweZeh}g~6<!mPv`nj`Zjh4:'oRynci]w}uc:8%iT{img_u{sa86+kV}ySlmd_mmt95*dW~xThlzn_bmvjqYpam~c14"l_vp\``vs`4?:>!mPws]gauroWhrb0??25.`[rtXllzdR|nci?22)eX{Uoi}zg_sf`l877:=&hSz|PddrwlZqfka7::!mPws]gauroW~nhd0??25.`[rtXllzdRy}ci?22)eX{Um~h21-a\swYwf}xT{dj{h<;/gZquWyd~Ryfduj\e}ot58:'oRy}_qlwvZqnl}bT~lmg=5.`[rtXxg~ySzgkti]q`fn:99&hSz|Ppovq[roc|aU|mnf24-a\swYwf}xT{dj{h^uggm;68%iT{Qnup\slbs`V}yoe3;,b]tvZtb{yeehQcaugmg|;6$jU|~nfPtxrf95{382yrbnQiigm\twi`n|fg?;:Ppsmdahvsq883S8?=x24/bl`hWnoeio{os]u=Z5+sth0{Qmio]`jqt23~xTic64ws]okbod02}yS}hPsr31?rtX{}ky~Qil`ep[vuzHIz3:<5O@y61e?@=<3;p_4>53c795cg=9:9>?im511276~h4j:0:7c=m4;48 6d62:ki7p]7e;1a1?7ai3;8?8=kc;33403<[8o?69?k:1827634lj0:<=;7;R:f>17c290:?>;<db82453f3m>9m7>51;3xW<6=;k?1=ko512167ae=99:>?6x[23g94?7=93;:hv]60;1a1?7ai3;8?8=kc;33405<,:396<k9;W1a6?4|}8on6<5z1dd94>{#9oh1>l5m43c94?372m;1=<mtH2;3?!44;3>9m6T83;0x5`<593w/?o>540:8 20=<;i0(5h543`8 74f281/>?753c48m6c0290/=kj53d48j4`d2910e>k::18'5cb=;l<0b<hl:098m6c3290/=kj53d48j4`d2;10e>k<:18'5cb=;l<0b<hl:298m6c5290/=kj53d48j4`d2=10e>k>:18'5cb=;l<0b<hl:498m6ba290/=kj53d48j4`d2?10e>jj:18'5cb=;l<0b<hl:698m6bc290/=kj53d48j4`d2110e>jl:18'5cb=;l<0b<hl:898m6be290/=kj53d48j4`d2h10e>jn:18'5cb=;l<0b<hl:c98m6b>290/=kj53d48j4`d2j10e>j7:18'5cb=;l<0b<hl:e98m6b0290/=kj53d48j4`d2l10e>j9:18'5cb=;l<0b<hl:g98m6b3290/=kj53d48j4`d28:07d=k3;29 4`c2:o=7c?ic;32?>o4l;0;6)?id;1f2>h6nj0:>65f3e394?"6nm08i;5a1ga956=<a:n;6=4+1gf97`0<f8lh6<:4;h1`b?6=,8lo6>k9;o3eg?7232c8oh4?:%3e`?5b>2d:jn4>6:9j7fb=83.:ji4<e79m5ce=9>10e>ml:18'5cb=;l<0b<hl:0:8?l5dj3:1(<hk:2g5?k7ak3;276g<ed83>!7al39n:6`>fb82e>=n;ln1<7*>fe80a3=i9oi1=o54i2g`>5<#9on1?h84n0d`>4e<3`9nn7>5$0dg>6c13g;mo7?k;:k0ad<72-;mh7=j6:l2bf<6m21b?h750;&2ba<4m?1e=km51g98m6c?290/=kj53d48j4`d2;:07d=j0;29 4`c2:o=7c?ic;02?>o4l<0;6)?id;1f2>h6nj09>65f3bc94?"6nm08i;5a1ga966=<a:i<6=44i50:>5<<a=8n6=44i507>5<<g=:h6=4+1gf905d<f8lh6=54o52b>5<#9on18=l4n0d`>4=<g=:26=4+1gf905d<f8lh6?54o52;>5<#9on18=l4n0d`>6=<g=:<6=4+1gf905d<f8lh6954o525>5<#9on18=l4n0d`>0=<g=:?6=4+1gf905d<f8lh6;54o520>5<#9on18=l4n0d`>2=<g=:96=4+1gf905d<f8lh6554o522>5<#9on18=l4n0d`><=<g=:;6=4+1gf905d<f8lh6l54o2de>5<#9on18=l4n0d`>g=<g:ln6=4+1gf905d<f8lh6n54o2dg>5<#9on18=l4n0d`>a=<g:lh6=4+1gf905d<f8lh6h54o2da>5<#9on18=l4n0d`>c=<g:l26=4+1gf905d<f8lh6<>4;n1e<?6=,8lo69>m;o3eg?7632e8j:4?:%3e`?27j2d:jn4>2:9l7c0=83.:ji4;0c9m5ce=9:10c>h::18'5cb=<9h0b<hl:068?j5a<3:1(<hk:52a?k7ak3;>76a<f283>!7al3>;n6`>fb822>=h;o81<7*>fe874g=i9oi1=:54o2d2>5<#9on18=l4n0d`>4><3f9m<7>5$0dg>16e3g;mo7?6;:m756<72-;mh7:?b:l2bf<6i21d8<<50;&2ba<38k1e=km51c98k176290/=kj541`8j4`d28i07b:>0;29 4`c2=:i7c?ic;3g?>i38o0;6)?id;63f>h6nj0:i65`41g94?"6nm0?<o5a1ga95c=<g=:o6=4+1gf905d<f8lh6?>4;n631?6=,8lo69>m;o3eg?4632e8jl4?:%3e`?27j2d:jn4=2:9l7``=83.:ji4;0c9m5ce=::10c9?n:188k1732900c9<>:188k1472900n>oi:182>5<7s-88?7=61:J0ea=O;0:0c<h6:188yg5fm3:1=7>50z&176<60j1C?lj4H2;3?j7?j3:17pl=9e83>1<729q/>>=51968L6gc3A92<6*>9b8b?l132900e4?50;9j5c`=831d>=?50;9~f7?d290?6=4?{%007?7?<2B8mi5G3828 4?d2h1b;94?::k:5?6=3`;mj7>5;n035?6=3th8?n4?:583>5}#::91=5:4H2cg?M5>82.:5n4n;h57>5<<a0;1<75f1gd94?=h:9;1<75rb21a>5<3290;w)<<3;3;0>N4im1C?4>4$0;`>d=n?=0;66g61;29?l7an3:17b<?1;29?xd4?00;694?:1y'665=9180D>ok;I1:4>"61j087d9;:188m=b=831b5<4?::m144<722wi?5=50;694?6|,;986<6;;I1b`>N4191C;<5+1da9664<a>>1<75f9083>>o6no0;66a=0083>>{e;131<7:50;2x 754282?7E=nd:J0=5=O?81/=hm52208m22=831b5<4?::k2bc<722e9<<4?::a72e=83>1<7>t$310>4>33A9jh6F<919K34=#9li1>><4$0;`>d=n?=0;66g61;29?l7an3:17b<?1;29?xd40?0;6>4?:1y'665=91;0D>ok;I1:4>N092.:in4=339'5<e=;2c<87>5;h;2>5<<g;::6=44}c1;g?6=;3:1<v*=3282<4=O;hn0D>7?;I52?!7bk388>6*>9b80?l132900e4?50;9l657=831vn>9m:187>5<7s-88?7?74:J0ea=O;0:0D:?4$0g`>7553-;2o7o4i6694?=n180;66g>fg83>>i5880;66sm39294?2=83:p(?=<:0:7?M5fl2B85=5+18a9e>o0<3:17d7>:188m4`a2900c?>>:188yg50n3:187>50z&176<60=1C?lj4H2;3?!7>k3k0e::50;9j=4<722c:jk4?::m144<722wi?5;50;194?6|,;986<6>;I1b`>N4191C;<5+1da9664<,83h6>5f7583>>o>93:17b<?1;29?xd40;0;694?:1y'665=91>0D>ok;I1:4>"61j0j7d9;:188m<7=831b=kh50;9l657=831vn>6m:180>5<7s-88?7?71:J0ea=O;0:0D:?4$0g`>7553-;2o7=4i6694?=n180;66a=0083>>{e;>k1<7:50;2x 754282?7E=nd:J0=5=O?81/=hm52208 4?d2h1b;94?::k:5?6=3`;mj7>5;n035?6=3th8;?4?:cd96?06sA92<6*=3280g5=]?:0ow<=510817?4a28i1=94>2;07>66=9m0:j7<?:239y!152;1b><m50;&2ba<59k1e=km50:9j642=83.:ji4=129m5ce=821b?4650;&2ba<41>1e=km50:9j7<0=83.:ji4<969m5ce=921b?4;50;&2ba<41>1e=km52:9j7<2=83.:ji4<969m5ce=;21b8<4?:%3e`?273g;mo7>4;h1e>5<#9on18=5a1ga95>=n;l0;6)?id;63?k7ak3807d=k:18'5cb=<91e=km53:9j7f<72-;mh7:?;o3eg?2<3`9i6=4+1gf905=i9oi1965f3`83>!7al3>;7c?ic;48?l5>290/=kj5419m5ce=?21b?54?:%3e`?273g;mo764;hf7>5<#9on1h>5a1ga94>=nl;0;6)?id;f0?k7ak3;07dj>:18'5cb=l:1e=km52:9j`5<72-;mh7j<;o3eg?5<3`im6=4+1gf9`6=i9oi1865fcd83>!7al3n87c?ic;78?led290/=kj5d29m5ce=>21boo4?:%3e`?b43g;mo794;hab>5<#9on1h>5a1ga9<>=nk00;6)?id;f0?k7ak3307dm7:18'5cb=l:1e=km5a:9jg2<72-;mh7j<;o3eg?d<3`i=6=4+1gf9`6=i9oi1o65fc483>!7al3n87c?ic;f8?le3290/=kj5d29m5ce=m21bo>4?:%3e`?b43g;mo7h4;ha2>5<#9on1h>5a1ga955=<aj:1<7*>fe8g7>h6nj0:=65fbg83>!7al3n87c?ic;31?>oem3:1(<hk:e18j4`d28907dlk:18'5cb=l:1e=km51598mge=83.:ji4k3:l2bf<6=21bno4?:%3e`?b43g;mo7?9;:kae?6=,8lo6i=4n0d`>41<3`h26=4+1gf9`6=i9oi1=554ic:94?"6nm0o?6`>fb82=>=nlk0;6)?id;f0?k7ak3;j76gka;29 4`c2m90b<hl:0`8?lb>290/=kj5d29m5ce=9j10ei650;&2ba<c;2d:jn4>d:9j`2<72-;mh7j<;o3eg?7b32co:7>5$0dg>a5<f8lh6<h4;hf6>5<#9on1h>5a1ga965=<ajn1<7*>fe8g7>h6nj09=65fc383>!7al3n87c?ic;01?>oe?3:1(<hk:e18j4`d2;907d<>e;29 4`c2;;o7c?ic;28?l4603:1(<hk:334?k7ak3:07d=6d;29 4`c2:3h7c?ic;28?l5>j3:1(<hk:2;`?k7ak3;07d=6a;29 4`c2:3h7c?ic;08?l5>13:1(<hk:2;`?k7ak3907d;k:18'5cb==j1e=km50:9j1g<72-;mh7;l;o3eg?7<3`?j6=4+1gf91f=i9oi1>65f5883>!7al3?h7c?ic;18?l3?290/=kj55b9m5ce=<21b9:4?:%3e`?3d3g;mo7;4;h75>5<#9on19n5a1ga92>=n=<0;6)?id;7`?k7ak3=07d;;:18'5cb==j1e=km58:9jb<<72-;mh7h7;o3eg?6<3`l<6=4+1gf9b==i9oi1=65ff783>!7al3l37c?ic;08?l`2290/=kj5f99m5ce=;21bj94?:%3e`?`?3g;mo7:4;hd0>5<#9on1j55a1ga91>=nn80;6)?id;d;?k7ak3<07dh?:18'5cb=n11e=km57:9jac<72-;mh7h7;o3eg?><3`on6=4+1gf9b==i9oi1565fee83>!7al3l37c?ic;c8?lcd290/=kj5f99m5ce=j21bio4?:%3e`?`?3g;mo7m4;hgb>5<#9on1j55a1ga9`>=nm00;6)?id;d;?k7ak3o07dk7:18'5cb=n11e=km5f:9ja3<72-;mh7h7;o3eg?7732cn97>5$0dg>c><f8lh6<?4;hg7>5<#9on1j55a1ga957=<al91<7*>fe8e<>h6nj0:?65fe383>!7al3l37c?ic;37?>ob93:1(<hk:g:8j4`d28?07dk?:18'5cb=n11e=km51798ma`=83.:ji4i8:l2bf<6?21bhh4?:%3e`?`?3g;mo7?7;:kg`?6=,8lo6k64n0d`>4?<3`;;<7>5$0dg>c><f8lh6<o4;hde>5<#9on1j55a1ga95g=<aoo1<7*>fe8e<>h6nj0:o65ffe83>!7al3l37c?ic;3g?>oak3:1(<hk:g:8j4`d28o07dhm:18'5cb=n11e=km51g98mcg=83.:ji4i8:l2bf<5821bj?4?:%3e`?`?3g;mo7<>;:kf3?6=,8lo6k64n0d`>74<3`nh6=4+1gf9b==i9oi1>>54i6g94?=n9>h1<75f8583>>o6?m0;66g>e083>>o6m90;66a>4d83>!7al3;?h6`>fb83?>i6<j0;6)?id;37`>h6nj0:76a>4c83>!7al3;?h6`>fb81?>i6<h0;6)?id;37`>h6nj0876a>4883>!7al3;?h6`>fb87?>i6<10;6)?id;37`>h6nj0>76a>4783>!7al3;?h6`>fb85?>i6<<0;6)?id;37`>h6nj0<76a>4583>!7al3;?h6`>fb8;?>i6<:0;6)?id;37`>h6nj0276a>4383>!7al3;?h6`>fb8b?>i6<80;6)?id;37`>h6nj0i76a>4183>!7al3;?h6`>fb8`?>i6;o0;6)?id;37`>h6nj0o76a>3d83>!7al3;?h6`>fb8f?>i6;m0;6)?id;37`>h6nj0m76a>3c83>!7al3;?h6`>fb824>=h9:k1<7*>fe820a=i9oi1=<54o01:>5<#9on1=9j4n0d`>44<3f;847>5$0dg>42c3g;mo7?<;:m272<72-;mh7?;d:l2bf<6<21d=>850;&2ba<6<m1e=km51498k452290/=kj515f8j4`d28<07b?<4;29 4`c28>o7c?ic;34?>i6;:0;6)?id;37`>h6nj0:465`12094?"6nm0:8i5a1ga95<=<g8?>6=4+1gf951b<f8lh6<o4;n360?6=,8lo6<:k;o3eg?7e32e:9>4?:%3e`?73l2d:jn4>c:9l504=83.:ji4>4e9m5ce=9m10c<;>:18'5cb=9=n0b<hl:0g8?j7283:1(<hk:06g?k7ak3;m76a>4g83>!7al3;?h6`>fb814>=h9==1<7*>fe820a=i9oi1><54o01`>5<#9on1=9j4n0d`>74<3f;8=7>5$0dg>42c3g;mo7<<;:m236<72-;mh7?82:l2bf<732e:;<4?:%3e`?70:2d:jn4>;:m235<72-;mh7?82:l2bf<532e::k4?:%3e`?70:2d:jn4<;:m22`<72-;mh7?82:l2bf<332e::i4?:%3e`?70:2d:jn4:;:m22g<72-;mh7?82:l2bf<132e::l4?:%3e`?70:2d:jn48;:m22<<72-;mh7?82:l2bf<?32e::54?:%3e`?70:2d:jn46;:m222<72-;mh7?82:l2bf<f32e::;4?:%3e`?70:2d:jn4m;:m220<72-;mh7?82:l2bf<d32e::94?:%3e`?70:2d:jn4k;:m226<72-;mh7?82:l2bf<b32e::?4?:%3e`?70:2d:jn4i;:m225<72-;mh7?82:l2bf<6821d=8h50;&2ba<6?;1e=km51098k43b290/=kj51608j4`d28807b?:d;29 4`c28=97c?ic;30?>i6=j0;6)?id;346>h6nj0:865`14`94?"6nm0:;?5a1ga950=<g8?j6=4+1gf9524<f8lh6<84;n36=?6=,8lo6<9=;o3eg?7032e:954?:%3e`?70:2d:jn4>8:9l501=83.:ji4>739m5ce=9010c<9n:18'5cb=9>80b<hl:0c8?j7013:1(<hk:051?k7ak3;i76a>7983>!7al3;<>6`>fb82g>=h9>=1<7*>fe8237=i9oi1=i54o055>5<#9on1=:<4n0d`>4c<3f;<97>5$0dg>4153g;mo7?i;:m231<72-;mh7?82:l2bf<5821d=;m50;&2ba<6?;1e=km52098k406290/=kj51608j4`d2;807b?:6;29 4`c28=97c?ic;00?>i58m0;6)?id;03g>h6nj0;76a=0c83>!7al38;o6`>fb82?>i58h0;6)?id;03g>h6nj0976a=0883>!7al38;o6`>fb80?>i5810;6)?id;03g>h6nj0?76a=0683>!7al38;o6`>fb86?>i58?0;6)?id;03g>h6nj0=76a=0483>!7al38;o6`>fb84?>i58=0;6)?id;03g>h6nj0376a=2683>>i>:3:17o=ne;295?6=8r.9?>4>8b9K7db<@:3;7b?7b;29?xd3:;0;65>50;2x 7542;:97E=nd:J0=5=]?:0nw<85168a>f<603;26<o51c8g>`<a28:1>n4=3;'5c>=<8o0b<?7:19m57g=82.:594:;%3:1?3<,83=685+18591>"6110>7)?69;78 4?f2<1/=4l55:&2=a<23-;2i7;4$0;e>0=#9h:196*>a086?!7f:3?0(<o<:49'5d2==2.:m84:;%3b2?3<,8k<685+1`:91>"6i00>7)?na;78 4ge2<1/=lm55:&2ea<23-;ji7;4$0ce>0=#9k:196*>b086?!7e:3?0(<l<:49'5g2==2.:n84:;%3a2?3<,8h<685+1c:91>"6j00>7)?ma;78 4de2<1/=om55:&2fa<23-;ii7;4$0`e>0=#9j:196*>c086?!7d:3?0(<m<:49'5f2==2.:o84:;%3`2?3<,8i<685+1b:91>"6k00>7)?la;78 4ee2<1/=nm55:&2ga<23-;hi7;4$0ae>0=#9m:196*>d086?!7c:3?0(<j<:49'5a2==2.:h84:;%3g2?3<,8n<685+1e:91>"6l00>7)?ka;78 4be2<1/=im55:&2`a<33-;oi7:4$0fe>4`13-8;?7<=8:&14`<>;2d9==4=4:l154<73-89?7<>2:&161<59;1/>?l5719'67e=;090(?<i:59'666=<2.8m:4=0g9'7d>=:9l0b>o6:19m7dg=:=1/>?851928m=5=831b4;4?::k23f<722c:;h4?::k150<722c9=;4?::k15<<72A89h65f20c94?N5:m10e??i:188m7472900e?<>:188m7452900e9950;&2ba<3>2d:jn4?;:k71?6=,8lo6984n0d`>4=<a=>1<7*>fe872>h6nj0976g;3;29 4`c2=<0b<hl:298m06=83.:ji4;6:l2bf<332c?j7>5$0dg>10<f8lh6854i5g94?"6nm0?:6`>fb85?>o3l3:1(<hk:548j4`d2>10e9m50;&2ba<3>2d:jn47;:k7f?6=,8lo6984n0d`><=<a=k1<7*>fe872>h6nj0j76g;9;29 4`c2=<0b<hl:c98m1>=83.:ji4;6:l2bf<d32c?>7>5$0dg>10<f8lh6i54i4194?"6nm0>>6`>fb83?M45l21b9<4?:%3e`?353g;mo7?4H30g?>o183:1(<hk:4d8j4`d291C>?j4;h7f>5<#9on19k5a1ga95>N5:m10e;850;&2ba<1=2d:jn4?;:k50?6=,8lo6;;4n0d`>4=<a?91<7*>fe851>h6nj0976g92;29 4`c2??0b<hl:298m3`=83.:ji495:l2bf<332c=i7>5$0dg>33<f8lh6854i7f94?"6nm0=96`>fb85?>o1k3:1(<hk:778j4`d2>10e;l50;&2ba<1=2d:jn47;:k5e?6=,8lo6;;4n0d`><=<a?31<7*>fe851>h6nj0j76g98;29 4`c2??0b<hl:c98m31=83.:ji495:l2bf<d32c==7>5$0dg>33<f8lh6i54i8a94?"6nm02n6`>fb83?>o>i3:1(<hk:8`8j4`d2810e4750;&2ba<>j2d:jn4=;:k:<?6=,8lo64l4n0d`>6=<a0=1<7*>fe8:f>h6nj0?76g66;29 4`c20h0b<hl:498md3=83.:ji46b:l2bf<132cj87>5$0dg><d<f8lh6:54i`194?"6nm02n6`>fb8;?>of:3:1(<hk:8`8j4`d2010el?50;&2ba<>j2d:jn4n;:kb4?6=,8lo64l4n0d`>g=<a0l1<7*>fe8:f>h6nj0h76g6e;29 4`c20h0b<hl:e98m<b=83.:ji46b:l2bf<b32c297>5$0dg><d<f8lh6k54i`f94?"6nm0jo6`>fb83?>ofj3:1(<hk:`a8j4`d2810elo50;&2ba<fk2d:jn4=;:kb=?6=,8lo6lm4n0d`>6=<ah21<7*>fe8bg>h6nj0?76gn7;29 4`c2hi0b<hl:498mg0=83.:ji4nc:l2bf<132ci97>5$0dg>de<f8lh6:54ic694?"6nm0jo6`>fb8;?>oe;3:1(<hk:`a8j4`d2010eo<50;&2ba<fk2d:jn4n;:ka5?6=,8lo6lm4n0d`>g=<ak:1<7*>fe8bg>h6nj0h76gnf;29 4`c2hi0b<hl:e98mdc=83.:ji4nc:l2bf<b32cj:7>5$0dg>de<f8lh6k54i020>5<#9on1==<4n0d`>5=<a8::6=4+1gf9554<f8lh6<54i025>5<#9on1==;4n0d`>5=<a8:?6=4+1gf9553<f8lh6<54o02f>5<#9on1==j4n0d`>5=<g8:h6=4+1gf955b<f8lh6<54o02a>5<#9on1==j4n0d`>7=<g8:j6=4+1gf955b<f8lh6>54o02:>5<#9on1==j4n0d`>1=<g8:36=4+1gf955b<f8lh6854o034>5<#9on1==j4n0d`>3=<g8;=6=4+1gf955b<f8lh6:54o036>5<#9on1==j4n0d`>==<g8;?6=4+1gf955b<f8lh6454o030>5<#9on1==j4n0d`>d=<g8;96=4+1gf955b<f8lh6o54o032>5<#9on1==j4n0d`>f=<g8;;6=4+1gf955b<f8lh6i54o02e>5<#9on1==j4n0d`>`=<g8:<6=4+1gf955b<f8lh6k54o003>5<#9on1=<h4n0d`>5=<g8;n6=4+1gf954`<f8lh6<54o03g>5<#9on1=<h4n0d`>7=<g8;h6=4+1gf954`<f8lh6>54o03a>5<#9on1=<h4n0d`>1=<g8;j6=4+1gf954`<f8lh6854o00:>5<#9on1=<h4n0d`>3=<g8836=4+1gf954`<f8lh6:54o004>5<#9on1=<h4n0d`>==<g88=6=4+1gf954`<f8lh6454o006>5<#9on1=<h4n0d`>d=<g88?6=4+1gf954`<f8lh6o54o000>5<#9on1=<h4n0d`>f=<g8896=4+1gf954`<f8lh6i54o002>5<#9on1=<h4n0d`>`=<g8;26=4+1gf954`<f8lh6k54o00g>5<#9on1=?m4n0d`>5=<g88i6=4+1gf957e<f8lh6<54o013>5<#9on1=?h4n0d`>5=<g88n6=4+1gf957`<f8lh6<54i2;;>5<#9on1?494n0d`>5=O:;n07d=66;29 4`c2:3<7c?ic;38L74c32c8584?:%3e`?5>?2d:jn4=;:k0=1<72-;mh7=67:l2bf<432c8m;4?:%3e`?5f=2d:jn4?;I01`>=n;h>1<7*>fe80e0=i9oi1=6F=2e98m6g4290/=kj53`78j4`d2;1C>?j4;h1b6?6=,8lo6>o:;o3eg?5<@;8o76g<a083>!7al39j96`>fb87?>o4i90;6)?id;1b1>h6nj0>76g<9g83>!7al39j96`>fb85?>o41l0;6)?id;1b1>h6nj0<76s|38694?3|V:3?70:=2;1b5>;3:;08m=5243097<`<5=896>7j;|q75?6=:rT?=63;23852>{t;o0;6?uQ3g9>074=>=1v>k50;0xZ6c<5=896;=4}r1g>5<5sW9o70:=2;41?xu4k3:1>vP<c:?767<1n2wx?o4?:3y]7g=:<;81:h5rs2c94?4|V:k019<=:7f8yv5>2909wS=6;<616?0d3ty847>52z\0<>;3:;0=n6s|d583>7}Yl=168?<51148yvb52909wSj=;<616?gc3tyo=7>52z\g5>;3:;0jn6s|d183>7}Yl9168?<5a`9~wf`=838pRnh4=501>d?<uzin6=4={_af?825:3k37p}lc;296~Xdk27?>?4n7:pgg<72;qUoo524309f3=z{jk1<7<t^bc891452k?0q~m6:181[e>34>9>7??4:pg=<72;qUo5524309f1=z{j=1<7<t^b5891452k90q~m9:181[e134>9>7l=;|q`1?6=:rTh963;238a5>{tk=0;6?uQc59>074=j91vn=50;0xZf5<5=896lh4}ra2>5<5sWi:70:=2;cf?xud83:1>vPl0:?767<f>2wxnk4?:3y]fc=:<;81===4}r`f>5<5sWhn70:=2;;`?xuel3:1>vPmd:?767<>i2wxnn4?:3y]ff=:<;81545rsc`94?4|Vkh019<=:8:8yvdf2909wSln;<616??03tyi57>52z\a=>;3:;02:6s|b983>7}Yj1168?<5a49~wad=838pRil4=501>d2<uznj6=4={_fb?825:3;;=6s|d883>7}Yl0168?<5a29~wa>=838pRi64=501>d4<uzn<6=4={_f4?825:3k:7p}k6;296~Xc>27?>?4n0:p`0<72;qUh8524309=c=z{jn1<7<t^bf8914520o0q~m=:181[e534>9>77k;|qa3?6=:rTi;63;238:1>{t:8o1<7=t^33f?825:38:j63;238165=z{<n1<7<t^4f891452==0q~;m:181[3e34>9>7::;|q6e?6=:rT>m63;23870>{t=00;6?uQ589>074=<:1v8650;0xZ0><5=8968>4}r74>5<5sW?<70:=2;6e?xu2>3:1>vP:6:?767<3m2wx984?:3y]10=:<;818i5rs4694?4|V<>019<=:5a8yv1b2909wS9j;<616?>13ty:;o4?:3y]52d<5=896<9j;|q;0?6=:rT3863;238;7>{t9>n1<7<t^05g?825:3;<o6s|16194?4|V8=870:=2;304>{t9>;1<7<t^052?825:3;9<6s|16294?4|V8=;70:=2;32a>{t9?l1<7<t^04e?825:3;:h6s|17g94?4|V8<n70:=2;32g>{t9?n1<7<t^04g?825:3;:n6s|17`94?4|V8<i70:=2;32e>{t9?k1<7<t^04b?825:3;956s|17;94?4|V8<270:=2;31<>{t9?21<7<t^04;?825:3;9i6s|17594?4|V8<<70:=2;313>{t9?<1<7<t^045?825:3;9:6s|17794?4|V8<>70:=2;311>{t9?>1<7<t^047?825:3;986s|17194?4|V8<870:=2;317>{t9?81<7<t^041?825:3;9>6s|17294?4|V8<;70:=2;315>{t9<l1<7<t^07e?825:3;:56s|14g94?4|V8?n70:=2;31`>{t9<n1<7<t^07g?825:3;;i6s|14a94?4|V8?h70:=2;33g>{t9<h1<7<t^07a?825:3;;n6s|14c94?4|V8?j70:=2;33e>{t9<31<7<t^07:?825:3;;56s|14:94?4|V8?370:=2;33<>{t9<=1<7<t^074?825:3;:;6s|16c94?4|V8=j70:=2;322>{t9>31<7<t^05:?825:3;9n6s|16:94?4|V8=370:=2;321>{t9>=1<7<t^054?825:3;:86s|16494?4|V8==70:=2;327>{t9>?1<7<t^056?825:3;:>6s|16694?4|V8=?70:=2;325>{t9?i1<7<t^04`?825:3;:<6s|17394?4|V8<:70:=2;33b>{t9<<1<7<t^075?825:3;;;6s|9383>16|5:kn6<6m;_;1?[45?2T9<i5Q21`8Z76f3W8;56P=099]651<V;:=7S<?5:\141=:<;81><;4=501>1d<5=8969o4=501>1?<5=896964=501>14<5=896;o4=501>3?<5=896;64=501>31<5=896;?4=501>6?234>9>7=64:?767<59?168?<5233891452;897S?<1:\27f=Y9==0R<:i;_364>X6=81U=8<4^070?[72<2T:985Q1208Z4543W;886P>349]560<V89<7S?<8:\27<=Y9:k0R<=m;_30`>X6;l1U=>h4^063?[7392T:8?5Q1518Z4233W;?96P>479]51><V8>27S?;a:\20g=Y9=i0R<:j;|a74?=83>1<7>t$310>4cc3A9jh6F<919'5c>=<8o0e:950;9j=1<722c9>84?::m2b2<722wi?<650;694?6|,;986<kk;I1b`>N4191/=k6540g8m21=831b594?::k160<722e:j:4?::a741=83>1<7>t$310>4cc3A9jh6F<919'5c>=<8o0e:950;9j=1<722c9>84?::m2b2<722wi?<850;694?6|,;986<kk;I1b`>N4191/=k6540g8m21=831b594?::k160<722e:j:4?::a74g=83>1<7>t$310>4cc3A9jh6F<919'5c>=<8o0e:950;9j=1<722c9>84?::m2b2<722wi??m50;694?6|,;986<kk;I1b`>N4191/=k6540g8m21=831b594?::k160<722e:j:4?::a77d=83>1<7>t$310>4cc3A9jh6F<919'5c>=<8o0e:950;9j=1<722c9>84?::m2b2<722wi??o50;694?6|,;986<kk;I1b`>N4191/=k6540g8m21=831b594?::k160<722e:j:4?::a77?=83>1<7>t$310>4cc3A9jh6F<919'5c>=<8o0e:950;9j=1<722c9>84?::m2b2<722wi??j50;694?6|,;986<kk;I1b`>N4191/=k6540g8m21=831b594?::k160<722e:j:4?::a62?=83>1<7>t$310>4cc3A9jh6F<919'5c>=<8o0e:950;9j=1<722c9>84?::m2b2<722wi>:650;694?6|,;986<kk;I1b`>N4191/=k6540g8m21=831b594?::k160<722e:j:4?::a621=83>1<7>t$310>4cc3A9jh6F<919'5c>=<8o0e:950;9j=1<722c9>84?::m2b2<722wi>:850;694?6|,;986<kk;I1b`>N4191/=k6540g8m21=831b594?::k160<722e:j:4?::a62g=83>1<7>t$310>4cc3A9jh6F<919'5c>=<8o0e:950;9j=1<722c9>84?::m2b2<722wi>5m50;694?6|,;986<kk;I1b`>N4191/=k6540g8m21=831b594?::k160<722e:j:4?::a6=d=83>1<7>t$310>4cc3A9jh6F<919'5c>=<8o0e:950;9j=1<722c9>84?::m2b2<722wi>5o50;694?6|,;986<kk;I1b`>N4191/=k6540g8m21=831b594?::k160<722e:j:4?::a6=?=83>1<7>t$310>4cc3A9jh6F<919'5c>=<8o0e:950;9j=1<722c9>84?::m2b2<722wi>5j50;694?6|,;986<kk;I1b`>N4191/=k6540g8m21=831b594?::k160<722e:j:4?::a61c=8391<7>t$310>6gd3A9jh6F<919j32<722c:i>4?::m2b2<722wi>9j50;194?6|,;986>ol;I1b`>N4191b;:4?::k2a6<722e:j:4?::a66e=83>1<7>t$310>4cc3A9jh6F<919j32<722c287>5;h011?6=3f;m;7>5;|`10f<72:0;6=u+22197de<@:ko7E=60:k43?6=3`;n?7>5;n3e3?6=3th9?o4?:583>5}#::91=hj4H2cg?M5>82c<;7>5;h;7>5<<a;8>6=44o0d4>5<<uk8?n7>53;294~"5;:08mn5G3`f8L6?73`=<6=44i0g0>5<<g8l<6=44}c00e?6=<3:1<v*=3282aa=O;hn0D>7?;h54>5<<a0>1<75f23794?=h9o=1<75rb36b>5<4290;w)<<3;1bg>N4im1C?4>4i6594?=n9l91<75`1g594?=zj;926=4;:183!44;3;nh6F<ae9K7<6<a>=1<75f9583>>o5:<0;66a>f683>>{e:=31<7=50;2x 7542:kh7E=nd:J0=5=n?>0;66g>e283>>i6n>0;66sm22:94?2=83:p(?=<:0gg?M5fl2B85=5f7683>>o><3:17d<=5;29?j7a?3:17pl=4983>6<729q/>>=53`a8L6gc3A92<6g87;29?l7b;3:17b?i7;29?xd5;>0;694?:1y'665=9ln0D>ok;I1:4>o0?3:17d7;:188m7422900c<h8:188yg43?3:1?7>50z&176<4ij1C?lj4H2;3?l102900e<k<:188k4`02900qo<<6;290?6=8r.9?>4>ee9K7db<@:3;7d98:188m<2=831b>?;50;9l5c1=831vn?:9:180>5<7s-88?7=nc:J0ea=O;0:0e:950;9j5`5=831d=k950;9~f752290?6=4?{%007?7bl2B8mi5G3828m21=831b594?::k160<722e:j:4?::a66b=8391<7>t$310>4c03A9jh6F<919'5<e=:<1b=5k50;9j5=`=831d=k950;9~f753290?6=4?{%007?7bl2B8mi5G3828m21=831b594?::k160<722e:j:4?::a637=83>1<7>t$310>4>53A9jh6F<919'5<e=;2c<87>5;h:g>5<<a0;1<75`21394?=zj;<;6=4;:183!44;3;3>6F<ae9K7<6<,83h6>5f7583>>o?l3:17d7>:188k7662900qo<:f;290?6=8r.9?>4>839K7db<@:3;7)?6c;18m22=831b4i4?::k:5?6=3f8;=7>5;|`11`<72=0;6=u+22195=4<@:ko7E=60:&2=f<43`=?6=44i9f94?=n180;66a=0083>>{e:<n1<7:50;2x 75428297E=nd:J0=5=#90i1?6g84;29?l>c2900e4?50;9l657=831vn?;l:187>5<7s-88?7?72:J0ea=O;0:0(<7l:29j31<722c3h7>5;h;2>5<<g;::6=44}c06f?6=<3:1<v*=3282<7=O;hn0D>7?;%3:g?5<a>>1<75f8e83>>o>93:17b<?1;29?xd5=h0;694?:1y'665=9180D>ok;I1:4>"61j087d9;:188m=b=831b5<4?::m144<722wi>8750;694?6|,;986<6=;I1b`>N4191/=4m53:k40?6=3`2o6=44i8394?=h:9;1<75rb345>5<3290;w)<<3;3;6>N4im1C?4>4$0;`>6=n?=0;66g7d;29?l?62900c?>>:188yg41=3:187>50z&176<60;1C?lj4H2;3?!7>k390e::50;9j<a<722c2=7>5;n035?6=3th9h>4?:483>5}#::91=5=4H2cg?M5>82.:5n4<;h57>5<<a>?1<75f8e83>>o>93:17b<?1;29?xd5l;0;684?:1y'665=9190D>ok;I1:4>"61j087d9;:188m23=831b4i4?::k:5?6=3f8;=7>5;|`1`4<72<0;6=u+22195=5<@:ko7E=60:&2=f<43`=?6=44i6794?=n0m0;66g61;29?j4793:17pl=d183>0<729q/>>=51918L6gc3A92<6*>9b80?l132900e:;50;9j<a<722c2=7>5;n035?6=3th9ok4?:483>5}#::91=5=4H2cg?M5>82.:5n4<;h57>5<<a>?1<75f8e83>>o>93:17b<?1;29?xd5kl0;684?:1y'665=9190D>ok;I1:4>"61j087d9;:188m23=831b4i4?::k:5?6=3f8;=7>5;|`1ga<72<0;6=u+22195=5<@:ko7E=60:&2=f<43`=?6=44i6794?=n0m0;66g61;29?j4793:17pl=cb83>0<729q/>>=51918L6gc3A92<6*>9b80?l132900e:;50;9j<a<722c2=7>5;n035?6=3th9o>4?:483>5}#::91=5=4H2cg?M5>82.:5n4<;h57>5<<a>?1<75f8e83>>o>93:17b<?1;29?xd5k;0;684?:1y'665=9190D>ok;I1:4>"61j087d9;:188m23=831b4i4?::k:5?6=3f8;=7>5;|`1g4<72<0;6=u+22195=5<@:ko7E=60:&2=f<43`=?6=44i6794?=n0m0;66g61;29?j4793:17pl=c183>0<729q/>>=51918L6gc3A92<6*>9b80?l132900e:;50;9j<a<722c2=7>5;n035?6=3th9nk4?:483>5}#::91=5=4H2cg?M5>82.:5n4<;h57>5<<a>?1<75f8e83>>o>93:17b<?1;29?xd5jl0;684?:1y'665=9190D>ok;I1:4>"61j087d9;:188m23=831b4i4?::k:5?6=3f8;=7>5;|`1fa<72<0;6=u+22195=5<@:ko7E=60:&2=f<43`=?6=44i6794?=n0m0;66g61;29?j4793:17pl=bb83>0<729q/>>=51918L6gc3A92<6*>9b80?l132900e:;50;9j<a<722c2=7>5;n035?6=3th9no4?:483>5}#::91=5;4H2cg?M5>82.:5n4n;h57>5<<a>?1<75f9083>>o6no0;66a=0083>>{e:lo1<7=50;2x 7542:kh7E=nd:J0=5=n?>0;66g>e283>>i6n>0;66sm2df94?5=83:p(?=<:2c`?M5fl2B85=5f7683>>o6m:0;66a>f683>>{e:mi1<7:50;2x 75428oo7E=nd:J0=5=n?>0;66g64;29?l45=3:17b?i7;29?xd5mj0;6>4?:1y'665=;hi0D>ok;I1:4>o0?3:17d?j3;29?j7a?3:17pl=dc83>1<729q/>>=51df8L6gc3A92<6g87;29?l?32900e?<::188k4`02900qo<jb;297?6=8r.9?>4<ab9K7db<@:3;7d98:188m4c42900c<h8:188yg4ci3:187>50z&176<6mm1C?lj4H2;3?l102900e4:50;9j673=831d=k950;9~f7cf29086=4?{%007?5fk2B8mi5G3828m21=831b=h=50;9l5c1=831vn?j6:187>5<7s-88?7?jd:J0ea=O;0:0e:950;9j=1<722c9>84?::m2b2<722wi>h750;194?6|,;986>ol;I1b`>N4191b;:4?::k2a6<722e:j:4?::a6a>=83>1<7>t$310>4cc3A9jh6F<919j32<722c287>5;h011?6=3f;m;7>5;|`1a=<72:0;6=u+22197de<@:ko7E=60:k43?6=3`;n?7>5;n3e3?6=3th9h:4?:583>5}#::91=hj4H2cg?M5>82c<;7>5;h;7>5<<a;8>6=44o0d4>5<<uk8n;7>53;294~"5;:08mn5G3`f8L6?73`=<6=44i0g0>5<<g8l<6=44}c0g2?6=<3:1<v*=3282aa=O;hn0D>7?;h54>5<<a0>1<75f23794?=h9o=1<75rb3g5>5<4290;w)<<3;1bg>N4im1C?4>4i6594?=n9l91<75`1g594?=zj;n>6=4;:183!44;3;nh6F<ae9K7<6<a>=1<75f9583>>o5:<0;66a>f683>>{e:m>1<7:50;2x 75428oo7E=nd:J0=5=n?>0;66g64;29?l45=3:17b?i7;29?xd48:0;694?:1y'665=9180D>ok;I1:4>"61j087d9;:188m=b=831b5<4?::m144<722wi?=<50;694?6|,;986<6=;I1b`>N4191/=4m53:k40?6=3`2o6=44i8394?=h:9;1<75rb222>5<3290;w)<<3;3;6>N4im1C?4>4$0;`>6=n?=0;66g7d;29?l?62900c?>>:188yg5783:187>50z&176<60;1C?lj4H2;3?!7>k390e::50;9j<a<722c2=7>5;n035?6=3th9jk4?:583>5}#::91=5<4H2cg?M5>82.:5n4<;h57>5<<a1n1<75f9083>>i5880;66sm2gg94?2=83:p(?=<:0:1?M5fl2B85=5+18a97>o0<3:17d6k:188m<7=831d>=?50;9~f7`c290?6=4?{%007?7?:2B8mi5G3828 4?d2:1b;94?::k;`?6=3`3:6=44o322>5<<uk8mo7>54;294~"5;:0:4?5G3`f8L6?73-;2o7=4i6694?=n0m0;66g61;29?j4793:17pl=fc83>1<729q/>>=51908L6gc3A92<6*>9b80?l132900e5j50;9j=4<722e9<<4?::a750=83>1<7>t$310>4>53A9jh6F<919'5<e=;2c<87>5;h:g>5<<a0;1<75`21394?=zj::<6=4;:183!44;3;3>6F<ae9K7<6<,83h6>5f7583>>o?l3:17d7>:188k7662900qo=80;291?6=8r.9?>4>829K7db<@:3;7)?6c;18m22=831b;84?::k;`?6=3`3:6=44o322>5<<uk9=j7>55;294~"5;:0:4>5G3`f8L6?73-;2o7=4i6694?=n?<0;66g7d;29?l?62900c?>>:188yg51m3:197>50z&176<60:1C?lj4H2;3?!7>k390e::50;9j30<722c3h7>5;h;2>5<<g;::6=44}c15`?6==3:1<v*=3282<6=O;hn0D>7?;%3:g?5<a>>1<75f7483>>o?l3:17d7>:188k7662900qo=9c;291?6=8r.9?>4>829K7db<@:3;7)?6c;18m22=831b;84?::k;`?6=3`3:6=44o322>5<<uk9=n7>55;294~"5;:0:4>5G3`f8L6?73-;2o7=4i6694?=n?<0;66g7d;29?l?62900c?>>:188yg51i3:197>50z&176<60:1C?lj4H2;3?!7>k390e::50;9j30<722c3h7>5;h;2>5<<g;::6=44}c15=?6==3:1<v*=3282<6=O;hn0D>7?;%3:g?5<a>>1<75f7483>>o?l3:17d7>:188k7662900qo=98;291?6=8r.9?>4>829K7db<@:3;7)?6c;18m22=831b;84?::k;`?6=3`3:6=44o322>5<<uk9>i7>55;294~"5;:0:4>5G3`f8L6?73-;2o7=4i6694?=n?<0;66g7d;29?l?62900c?>>:188yg52l3:197>50z&176<60:1C?lj4H2;3?!7>k390e::50;9j30<722c3h7>5;h;2>5<<g;::6=44}c16g?6==3:1<v*=3282<6=O;hn0D>7?;%3:g?5<a>>1<75f7483>>o?l3:17d7>:188k7662900qo=:b;291?6=8r.9?>4>829K7db<@:3;7)?6c;18m22=831b;84?::k;`?6=3`3:6=44o322>5<<uk9>m7>55;294~"5;:0:4>5G3`f8L6?73-;2o7=4i6694?=n?<0;66g7d;29?l?62900c?>>:188yg5213:197>50z&176<60:1C?lj4H2;3?!7>k390e::50;9j30<722c3h7>5;h;2>5<<g;::6=44}c16<?6==3:1<v*=3282<6=O;hn0D>7?;%3:g?5<a>>1<75f7483>>o?l3:17d7>:188k7662900qo=:7;291?6=8r.9?>4>829K7db<@:3;7)?6c;18m22=831b;84?::k;`?6=3`3:6=44o322>5<<uk82i7>53;294~"5;:0:i:5G3`f8L6?73-;2o7?:;%3ea?5el2c:4h4?::k2<c<722e:j:4?::a76b=8391<7>t$310>4c03A9jh6F<919'5<e=9<1b=5k50;9j5=`=831d=k950;9~f613290?6=4?{%007?7b02B8mi5G3828 4?d2>?0(<hj:2`g?l7?m3:17d?7f;29?l7>83:17b?i7;29?xd51k0;6:4?:1y'665=9lh0D>ok;I1:4>"61j0:;k5f19g94?=n91l1<75f18294?=n90;1<75f18094?=n9091<75`1g594?=zj:=<6=4<:183!44;3;n;6F<ae9K7<6<,83h6<;4$0df>6da3`;3i7>5;h3;b?6=3f;m;7>5;|`03=<72:0;6=u+22195`1<@:ko7E=60:&2=f<6=2.:jh4<bd9j5=c=831b=5h50;9l5c1=831vn>67:180>5<7s-88?7?j7:J0ea=O;0:0(<7l:078 4`b2:hm7d?7e;29?l7?n3:17b?i7;29?xd40l0;6>4?:1y'665=9l=0D>ok;I1:4>"61j0:96*>fd80f`=n91o1<75f19d94?=h9o=1<75rb201>5<2290;w)<<3;3f=>N4im1C?4>4$0;`>7c<a82n6=44i0:e>5<<a83;6=44i0;2>5<<g8l<6=44}c114?6==3:1<v*=3282a<=O;hn0D>7?;%3:g?4b3`;3i7>5;h3;b?6=3`;2<7>5;h3:5?6=3f;m;7>5;|`05`<72<0;6=u+22195`?<@:ko7E=60:&2=f<5m2c:4h4?::k2<c<722c:5=4?::k2=4<722e:j:4?::a772=8391<7>t$310>4c03A9jh6F<919'5<e=:m1b=5k50;9j5=`=831d=k950;9~f652290>6=4?{%007?7b12B8mi5G3828 4?d2;o0e<6j:188m4>a2900e<7?:188m4?62900c<h8:188yg54;3:197>50z&176<6m01C?lj4H2;3?!7>k38n7d?7e;29?l7?n3:17d?60;29?l7>93:17b?i7;29?xd4;80;684?:1y'665=9l30D>ok;I1:4>"61j09i6g>8d83>>o60o0;66g>9183>>o6180;66a>f683>>{e;:=1<7=50;2x 75428o<7E=nd:J0=5=#90i1>i5f19g94?=n91l1<75`1g594?=zj;296=4::183!44;3;n56F<ae9K7<6<,83h6?k4i0:f>5<<a82m6=44i0;3>5<<a83:6=44o0d4>5<<uk83<7>55;294~"5;:0:i45G3`f8L6?73-;2o7<j;h3;a?6=3`;3j7>5;h3:4?6=3`;2=7>5;n3e3?6=3th9;h4?:483>5}#::91=h74H2cg?M5>82.:5n4=e:k2<`<722c:4k4?::k2=5<722c:5<4?::m2b2<722wi>5:50;194?6|,;986<k8;I1b`>N4191/=4m52e9j5=c=831b=5h50;9l5c1=831vn?7::186>5<7s-88?7?j9:J0ea=O;0:0(<7l:3g8m4>b2900e<6i:188m4?72900e<7>:188k4`02900qo<63;291?6=8r.9?>4>e89K7db<@:3;7)?6c;0f?l7?m3:17d?7f;29?l7>83:17d?61;29?j7a?3:17pl=9083>0<729q/>>=51d;8L6gc3A92<6*>9b81a>o60l0;66g>8g83>>o6190;66g>9083>>i6n>0;66sm29d94?3=83:p(?=<:0g:?M5fl2B85=5+18a96`=n91o1<75f19d94?=n90:1<75f18394?=h9o=1<75rb3;4>5<4290;w)<<3;3f3>N4im1C?4>4$0;`>7b<a82n6=44i0:e>5<<g8l<6=44}c0b0?6=>3:1<v*=3282ad=O;hn0D>7?;%3:g?4?3-;mi7=m8:k2<`<722c:4k4?::k2=5<722c:5<4?::k2=7<722e:j:4?::a6d3=83=1<7>t$310>4ce3A9jh6F<919'5<e=:01b=5k50;9j5=`=831b=4>50;9j5<7=831b=4<50;9j5<5=831d=k950;9~f7g0290<6=4?{%007?7bj2B8mi5G3828 4?d2;h0e<6j:188m4>a2900e<7?:188m4?62900e<7=:188m4?42900c<h8:188yg4f;3:197>50z&176<6m01C?lj4H2;3?!7>k38<7)?ie;1a<>o60l0;66g>8g83>>o6190;66g>9083>>i6n>0;66sm2`494?5=83:p(?=<:0g4?M5fl2B85=5+18a96a=n91o1<75f19d94?=h9o=1<75rb3c1>5<3290;w)<<3;3f<>N4im1C?4>4$0;`>70<,8ln6>ll;h3;a?6=3`;3j7>5;h3:4?6=3f;m;7>5;|`1e=<72=0;6=u+22195`><@:ko7E=60:&2=f<4<2.:jh4<b`9j5=c=831b=5h50;9j5<6=831d=k950;9~f7g>290>6=4?{%007?7b12B8mi5G3828 4?d2:?0(<hj:2`b?l7?m3:17d?7f;29?l7>83:17d?61;29?j7a?3:17pl=a083>6<729q/>>=51d58L6gc3A92<6*>9b811>"6nl08nn5f19g94?=n91l1<75`1g594?=zj:>86=4<:183!44;3;n;6F<ae9K7<6<,83h6?j4i0:f>5<<a82m6=44o0d4>5<<uk9?97>54;294~"5;:0:i55G3`f8L6?73-;2o7=;;%3ea?5e12c:4h4?::k2<c<722c:5=4?::m2b2<722wi?9850;794?6|,;986<k6;I1b`>N4191/=4m5349'5cc=;k30e<6j:188m4>a2900e<7?:188m4?62900c<h8:188yg54i3:1;7>50z&176<6mk1C?lj4H2;3?!7>k3=0e<6j:188m4>a2900e<7?:188m4?62900e<7=:188m4?42900c<h8:188yg43n3:1;7>50z&176<6mk1C?lj4H2;3?!7>k3;3m6g>8d83>>o60o0;66g>9183>>o6180;66g>9383>>o61:0;66a>f683>>{e:o;1<7;50;2x 75428o27E=nd:J0=5=#90i1=564i0:f>5<<a82m6=44i0;3>5<<a83:6=44o0d4>5<<uk8m<7>57;294~"5;:0:io5G3`f8L6?73-;2o784i0:f>5<<a82m6=44i0;3>5<<a83:6=44i0;1>5<<a8386=44o0d4>5<<uk8=>7>54;294~"5;:0:495G3`f8L6?73-;2o7o4i6694?=n180;66g>fg83>>i5880;66sm31694?2=83:p(?=<:0:7?M5fl2B85=5+18a9e>o0<3:17d7>:188m4`a2900c?>>:188yg56k3:197>50z&176<6m01C?lj4H2;3?!7>k330e<6j:188m4>a2900e<7?:188m4?62900c<h8:188yg55n3:197>50z&176<6m01C?lj4H2;3?!7>k38n7d?7e;29?l7?n3:17d?60;29?l7>93:17b?i7;29?xd5?j0;684?:1y'665=9l30D>ok;I1:4>"61j027d?7e;29?l7?n3:17d?60;29?l7>93:17b?i7;29?xd48<0;6;4?:1y'665=9lk0D>ok;I1:4>"61j037d?7e;29?l7?n3:17d?60;29?l7>93:17d?62;29?j7a?3:17pl=de83>6<729q/>>=51d58L6gc3A92<6*>9b81`>o60l0;66g>8g83>>i6n>0;66sm22g94?5=83:p(?=<:0g4?M5fl2B85=5+18a96a=n91o1<75f19d94?=h9o=1<75rb3ff>5<4290;w)<<3;3f3>N4im1C?4>4$0;`>7b<a82n6=44i0:e>5<<g8l<6=44}c00b?6=;3:1<v*=3282a2=O;hn0D>7?;%3:g?4c3`;3i7>5;h3;b?6=3f;m;7>5;|`1`c<72:0;6=u+22195`1<@:ko7E=60:&2=f<5l2c:4h4?::k2<c<722e:j:4?::a616=8391<7>t$310>4c03A9jh6F<919'5<e=:m1b=5k50;9j5=`=831d=k950;9~f7c729086=4?{%007?7b?2B8mi5G3828 4?d2;n0e<6j:188m4>a2900c<h8:188yg4103:197>50z&176<6m01C?lj4H2;3?!7>k3;3;6g>8d83>>o60o0;66g>9183>>o6180;66a>f683>>{e;921<7;50;2x 75428o27E=nd:J0=5=#90i1>?5f19g94?=n91l1<75f18294?=n90;1<75`1g594?=zj;<?6=4<:183!44;3;n;6F<ae9K7<6<,83h64?4i0:f>5<<a82m6=44o0d4>5<<uk8=?7>57;294~"5;:0:io5G3`f8L6?73-;2o7?76:k2<`<722c:4k4?::k2=5<722c:5<4?::k2=7<722c:5>4?::m2b2<722wi>9?50;194?6|,;986<k8;I1b`>N4191/=4m52e9j5=c=831b=5h50;9l5c1=831vn?k>:180>5<7s-88?7?j7:J0ea=O;0:0(<7l:3f8m4>b2900e<6i:188k4`02900qo<;2;297?6=8r.9?>4>e69K7db<@:3;7)?6c;0g?l7?m3:17d?7f;29?j7a?3:17pl=e383>6<729q/>>=51d58L6gc3A92<6*>9b81`>o60l0;66g>8g83>>i6n>0;66sm25194?5=83:p(?=<:0g4?M5fl2B85=5+18a96a=n91o1<75f19d94?=h9o=1<75rb3g0>5<4290;w)<<3;3f3>N4im1C?4>4$0;`>7b<a82n6=44i0:e>5<<g8l<6=44}c070?6=;3:1<v*=3282a2=O;hn0D>7?;%3:g?4c3`;3i7>5;h3;b?6=3f;m;7>5;|`1a1<72:0;6=u+22195`1<@:ko7E=60:&2=f<5l2c:4h4?::k2<c<722e:j:4?::a712=83=1<7>t$310>4ce3A9jh6F<919'5<e=9130e<6j:188m4>a2900e<7?:188m4?62900e<7=:188m4?42900c<h8:188yg43=3:1?7>50z&176<6m>1C?lj4H2;3?!7>k38o7d?7e;29?l7?n3:17b?i7;29?xd5m<0;6>4?:1y'665=9l=0D>ok;I1:4>"61j09h6g>8d83>>o60o0;66a>f683>>{e;=;1<7850;2x 75428oj7E=nd:J0=5=#90i1?;5+1gg97g1<a82n6=44i0:e>5<<a83;6=44i0;2>5<<a8396=44o0d4>5<<uk9?>7>57;294~"5;:0:io5G3`f8L6?73-;2o7=8;h3;a?6=3`;3j7>5;h3:4?6=3`;2=7>5;h3:6?6=3`;2?7>5;n3e3?6=3th88=4?:483>5}#::91=h74H2cg?M5>82.:5n4<3:&2b`<4j>1b=5k50;9j5=`=831b=4>50;9j5<7=831d=k950;9~f65a290?6=4?{%007?7b02B8mi5G3828 4?d2:80(<hj:2`a?l7?m3:17d?7f;29?l7>83:17b?i7;29?xd4;l0;6>4?:1y'665=9l=0D>ok;I1:4>"61j09h6*>fd80fg=n91o1<75f19d94?=h9o=1<75rb3c3>5<5290;w)<<3;3f6>N4im1C?4>4i0:g>5<<g8l<6=44}c1;b?6=:3:1<v*=3282a7=O;hn0D>7?;h3;`?6=3f;m;7>5;|q76<<72>qU8?74=25b>4`a349<n7?if:?03f<6no16?5751gd896>428lm70=89;:g?xu6n90;6:u23`d95c?<5:=96??;;<146?460278=;487:?06<<0?279;;487:?1<<<0?2wx=k?50;6;85fm3;3n63<7`8:5>;40;02=63<7g8:5>;40902=63<73815f=:;>81?4j4=251>6?e349<>7=6a:?037<41016?:<5f89>724=n>16?:<5f79>724=n<16?:<5f59>724=n:16?:<5f09>724=n916?:<5eg9>724=ml16?:<5ee9>724=mj16?:<5ec9>724=mh16?:<5e89>724=m116?:<5e79>724=m<16?:<5e59>724=m:16?:<5e39>724=m816?:<5e19>724=lo16?:<5dd9>724=lm16?:<5112896152ol01>9=:gg896152on01>9=:ga896152oh01>9=:gc896152o801>9=:d5896152mi01>9=:0g2?850:3;n<63<1`8:0>;49?02863<168:0>;49102863<188:0>;4:m02863<288:0>;4:h02863<2c8:0>;4:j02863=7`8:0>;5??02863=768:0>;5?102863=788:0>;50m02863=888:0>;50h02863=8c8:0>;50j02863=35843>;5;=09>8522e6932=::m>1>?;4}r130?6=;rT?><523169657<5::>6<7?;|q07f<72;qU8<o4=21`>7663ty8;84?:07x970220;01?lm:67897dd2>?01?lk:67897db2>?01?li:67897e72>?01?m>:67897e52>?01?m<:67897ed2>?01?mk:67897eb2>?01?mi:67897b72>?01?j>:67897b52>?01?j<:678966120;01?7j:0d4?854i3;2=6s|27094?5|V=8;70<92;035>;5>:0:5<5rs3;`>5<1s482o7<?1:?1=`<60o16>;651838966?283:70=84;3:4>;51k0:5<5rs3;g>5<5sW>:863=9e8144=z{:om6=4={_1fb>;4?;0:9;5rs2db>5<5sW9mm63<738224=z{=:>6=4={_631>;4?;0::n5rs52g>5<5sW>;h63<738231=z{=:n6=4={_63a>;4?;0:;85rs52e>5<5sW>;j63<738233=z{=;;6=4={_624>;4?;0:;:5rs532>5<5sW>:=63<73823==z{=;96=4={_626>;4?;0:;45rs530>5<5sW>:?63<73823d=z{:l;6=4={_1e4>;4?;0:9:5rs2d2>5<5sW9m=63<73821==z{:l96=4={_1e6>;4?;0:945rs2d0>5<5sW9m?63<73821d=z{:l?6=4={_1e0>;4?;0:9o5rs2d6>5<5sW9m963<73821f=z{:l=6=4={_1e2>;4?;0:9i5rs2d4>5<5sW9m;63<73821`=z{:l36=4={_1e<>;4?;0:9k5rs2d:>5<5sW9m563<738225=z{:li6=4={_1ef>;4?;0::?5rs2d`>5<5sW9mo63<738226=z{:lo6=4={_1e`>;4?;0::95rs2df>5<5sW9mi63<738220=z{:lm6=4={_1eb>;4?;0::;5rs523>5<5sW>;<63<738222=z{=::6=4={_635>;4?;0::55rs521>5<5sW>;>63<73822<=z{=:86=4={_637>;4?;0::l5rs527>5<5sW>;863<73822g=z{=:=6=4={_632>;4?;0::i5rs524>5<5sW>;;63<73822`=z{=:36=4={_63<>;4?;0::k5rs52:>5<5sW>;563<738235=z{=:j6=4={_63e>;4?;0:;<5rs52`>5<5sW>;o63<738236=z{:=i6=4:{<10f?7an278?n4>fg9>72e=1816?:l52138966328lm7p}<7883>6}:;>31>=?4=21b>4>a349;97?61:p72c=838;w0<6c;3eb>;51m0:jk523929657<5;<>65j4=345>=b<5;?265j4=37b>=b<5;?i65j4=37`>=b<5;?o65j4=37f>=b<5;?m65j4=343>=b<5;<:65j4=3`a>4`a348io76k;<0a`?>c348ii76k;<0ab?>c348h<76k;<0`5?>c348h>76k;<0`7?>c348ho76k;<0``?>c348hi76k;<0`b?>c348o<76k;<0g5?>c348o>76k;<0g7?>c348=>7?if:p7=7=83;ow0=72;035>;48>03h63<078;`>;5nk03h63=fb8;`>;5nm03h63=fd8;`>;5no03h63<018;`>;48803h63<038;`>;48:03h63<568;`>;4=103h63<588;`>;4=h03h63<5c8;`>;4=j03h63<5e8;`>;4=l03h63<698;`>;4>003h63<6`8;`>;4>k03h63<6b8;`>;4>m03h63<6d8;`>;4>o03h63<718;`>{t<;o1<78t^50f?854l3;3i63=6982=5=:;921=5h4=3;a>4>b3498m7?7e:p072=83<pR9<;;<0:a?7?m279:54>8d9>75>=90:01>9;:0:f?84>j3;3j6s|36194?4|5:=96<9k;<140?7a?2wx?:850;3:850:392463<7380=3=:;>81?4;4=251>6?3349<>7?8b:?123<>9278<:461:?012<0=27895485:?01<<0=2789l485:?01g<0=2789n485:?01a<0=2789h485:?02=<0=278:4485:?02d<0=278:o485:?02f<0=278:i485:?02`<0=278:k485:?035<0=278?i4>f69~w6e0290?ivP<c69>6<e=?=16>4j5759>76d=?=16?>m5759>72g=?=16?5l5759>7=4=?=16?:l5759>7=e=?=16?:m5759>7=?=?=16?:75759>7=3=?=16?:h5759>7=6=?=16?585759>7=5=?=16?:<57d9>724=0=16>;;5759>630=?=16>875759>60g=?=16>8l5759>60e=?=16>8j5759>60c=?=16>8h5759>636=?=16>;?5759>6gd=?=16>om5759>6gb=?=16>ok5759>6g`=?=16>n>5759>6f7=?=16>n<5759>6f5=?=16>nm5759>6fb=?=16>nk5759>6f`=?=16>i>5759>6a7=?=16>i<5759>6a5=?=16?=95759>750=?=16>kl5759>6ce=?=16>kj5759>6cc=?=16>kh5759>756=?=16?=?5759>754=?=16?==5759>701=?=16?865759>70?=?=16?8o5759>70d=?=16?8m5759>70b=?=16?8k5759>73>=?=16?;75759>73g=?=16?;l5759>73e=?=16?;j5759>73c=?=16?;h5759>726=?=16>;<5759>752=?=1v?m;:184850:3?>70<lc;035>;49j0:4h5226a95=c<5;9n6<6i;<0ga?7?n278>k4>8d9~w7e2290<w0=82;75?84dl38;=63<1d82=5=:;:;1=4>4=35f>4?73488j7?7f:?1`c<60o1v?m9:184850:3?<70<le;035>;49l0:4h5232395=c<5;=n6<6j;<074?7?n279i=4>8g9~w7e0290<w0=82;7;?84dn38;=63<2182=5=:;:91=4>4=3:3>4?7348?=7?7f:?1a4<60o1v?m7:184850:3?270<k0;035>;4:90:4h5232195=c<5;2;6<6j;<076?7?n279i?4>8g9~w7e>290<w0=82;7b?84c938;=63<2382=5=:;:?1=4>4=3:1>4?7348??7?7f:?1a6<60o1v?mn:184850:3?i70<k2;035>;4:;0:4h5232795=c<5;296<6j;<070?7?n279i94>8g9~w7ee290<w0=82;7g?84c;38;=63<2582<`=:;:=1=5k4=3:7>4>b348?97?7f:?1a0<60o1v>9k:180850n38;=63<73815`=:;>>1=5h4}r1`e?6=:rT8ol523609f2=z{:n>6=4={_1g1>;4?;0h>6s|3d294?4|V:o;70=82;ag?xu4m10;6?uQ3d:896152m?0q~=j9;296~X4m016?:<5d79~w6cf2909wS=ja:?037<c?2wx?hl50;0xZ6ce349<>7j7;|q0af<72;qU?hm4=251>a?<uz9nh7>52z\0aa=:;>81hl5rs2gf>5<5sW9ni63<738gf>{t;jh1<7<t^2aa?850:3h37p}<cb83>7}Y;ji01>9=:c;8yv5dl3:1>vP<ce9>724=jh1v>mj:181[5dm278;?4mb:p7f`=838pR>mi;<146?dd3ty8h=4?:3y]7a6<5:=96oj4}r1g5?6=:rT8h<523609f`=z{:n96=4={_1g6>;4?;0ij6s|3e194?4|V:n870=82;a3?xu4l=0;6?uQ3e6896152j;0q~=k6;296~X4l?16?:<5c29~w6b02909wS=k7:?037<d<2wx?i650;0xZ6b?349<>7m:;|q0`<<72;qU?i74=251>f0<uz9om7>52z\0`d=:;>81o:5rs2fa>5<5sW9on63<738`<>{t;mi1<7<t^2f`?850:3i27p}<de83>7}Y;mn01>9=:bc8yv5cm3:1>vP<dd9>724=kk1v>ji:181[5cn278;?4lc:p7`7=838pR>k>;<146?eb3ty8i?4?:3y]7`4<5:=96nh4}r1f7?6=:rT8i>523609`5=z{:o?6=4={_1f0>;4?;0o=6s|3d794?4|V:o>70=82;f1?xu4m>0;6?uQ3d5896152m>0q~=:f;2955}:;>81?55222f95=c<5;9>64:4=24;>7663483j7?61:?05f<61816>:m5183897bc282n70=;1;3:6>;4<;0:5>5235295=`<5:9m6<6i;<10a?7?n2784k4>8e9>77`=90;01>:;:0;0?xu4>90;6:u236097<=:::<1595237;9657<5;2m6<6i;<12g?7?n279;n4>8g9>66c=91o0q~=91;293~;4?;08m63=368:0>;4>h09<<5230g95<7<5;=n6<7>;<0:5?7>9279?k4>8d9~w605290<w0=82;1a?844033?70=9b;035>;49l0:4k5226g95=`<5;3:6<6i;<074?7?m2wx?;=50;5x96152:i01?=6:868960d2;::70==0;3:5>;5090:5<5228195<7<5;>:6<6j;|q021<72>q6?:<53e9>66g=1=16?;j521389647282m70<70;3;b>;51:0:4k5225095=c<uz9=97>57z?037<4m279?o464:?02`<58816??<5183897>5283:70<65;3:5>;5<:0:4h5rs245>5<0s49<>7=i;<00g??3349=j7<?1:?067<60o16>5<519d897?2282m70<;4;3;a>{t;?=1<78t=251>17<5:=;6?>>;<110?7?n279494>8g9>6<1=91l01?:::0:f?xu5ih0;6hu22c`9657<5;2m6<7?;<0b0?7?n279m84>8g9>6d1=90:01?o<:0:e?84f:3;3j63=a082<c=:;8i1=4>4=35`>4?73488h7?7f:?1`a<60o16>l>519f8964a283;7p}=ac83><}::ki1>=?4=3a`><7<5;2m6<6j;<0b0?7>8279m84>919>6d1=90;01?o<:0;3?84f:3;2<63=a082<`=z{;kh6=47{<0a`?479279oi461:?1=4<61916>l:5183897g2283:70<n7;3;b>;5i:0:5<522`095=c<uz8jh7>57z?1f`<58816>nk5909>6<7=91o01?o;:0;1?84f=3;2>63=a682=7=::h91=5k4}r0ba?6=>r79nk4=009>6f`=1816>4=5182897g3282n70<n5;3:7>;5i>0:5>5rs3ce>5<2s48h<7<?1:?1`5<>92795>4>8d9>6d3=91o01?o8:0:f?xu5j90;6;u22b39657<5;n:64?4=3;6>4?7348j:7?7e:?1e<<61916>l6519d8yv4e93:19v3=c38144=::m815<5228795=c<5;k36<6j;<0b=?7?n2wx>o<50;6x97e42;::70<k3;;2?84>?3;3i63=a882<`=z{:=:6=4<{<0g1??3349=477>;<1;b?7a?2wx?9950;`x97b120>01>;8:322?851133:70<ke;3;a>;4<80:5=5235095<6<5:>;6<7?;<10b?7>8278?h4>8d9>77`=91l01>:;:0;1?xu4<10;6lu22e59=1=:;<21>=?4=24b><7<5:9:6<7>;<0gb?7?m2788<4>909>714=90;01>:?:0;2?854n3;3i63<4582=4=z{:>26=46{<0g<??3349>57<?1:?02g<>9278?<4>8g9>6`6=91o01>:>:0:e?853:3;2>63<4182<`=:;=>1=4>4}r17e?6=0r79h4464:?01d<58816?;m5909>765=90;01?k>:0:f?85393;3i63<4382<c=:;=>1=5h4}r17f?6=?r79hl464:?01g<58816?;j5909>765=91l01?k=:0:f?853<3;3i63<4382<`=z{:>h6=47{<0gf??3349>o7<?1:?02`<>9278?84>909>715=91o01>:9:0;3?84b;3;3i63<4482<c=z{:>o6=48{<0gg??3349>h7<?1:?02c<>9278?84>8g9>713=91o01?k;:0:f?853>3;3j6s|35g94?3|5:?n6?>>;<144??63498;7?7f:?003<60l16>h;519g8yv54j3:1:v3<3c8144=:;:n1=5h4=34;>4>a349;47?7e:?1=g<61916?>o51828yv4>i3:1?v3=9b8:5>;51m02=63=9c82b2=z{;326=4={<0;`?7a?2795o4>929~w7??2909w0<8a;3e3>;51k0:5?5rs21b>5<4s498n77>;<10g??63498m7?i7:p76?=838p1><k:0d4?854i3;2?6s|32:94?4|5:;j6<h8;<10e?7>:2wx?5:50;0x96>420;01>98:0d4?xu40>0;6>u236d95c`<5:2;6<hi;<1;<?7a?2wx?5o50;0x96>>20;01>97:0d4?xu40m0;6?u239095c`<5:2n6<h8;|q0<3<72;q6?585213896>?282m7p}<8483>6}:;1<15<523979657<5:=<6<6i;|q0<6<72=q6?5;5909>7=5=:9;01>98:0:f?85?03;3i6s|39a94?4|5:2h6?>>;<1;a?7?n2wx?5l50;1x96>d20;01>6m:322?85003;3j6s|39;94?2|5:2i64?4=2::>766349<47?7e:?0<`<60l1v>9l:181850133:70=8c;035>{t;>k1<7<t=25a><7<5:=j6?>>;|q050<72;q6?<o5769>74?=9o=0q~=>4;296~;4910:j:5230;932=z{:;86=4={<123?7a?278=5487:p744=838p1>?9:0d4?856?3=<7p}<2083>7}:;831>?;4=201>4`03ty8=k4?:3y>74>=:;?01><?:0d4?xu49m0;6?u23059673<5:;n6<h8;|q05g<72;q6?<852378967d28l<7p}<2283>7}:;8k1>?;4=207>4`03ty8>54?:3y>77b=?>16??m51g58yv55?3:1>v3<2c82b2=:;;i1;:5rs205>5<5s499m7?i7:?06g<0?2wx??;50;0x964>28l<70==a;54?xu4;=0;6?u233a9673<5:9>6<h8;|q077<72;q6??l52378965428l<7p}<3183>7}:;;k1>?;4=212>4`03ty8>h4?:3y>77?=:;?01><i:0d4?xu4;?0;6?u233f9673<5:9<6<h8;|q130<72;q6>:o5769>62?=9o=0q~<84;296~;5?10:j:5226;932=z{;=86=4={<043?7a?279;5487:p624=838p1?99:0d4?840?3=<7p}=8083>7}::>31>?;4=3:1>4`03ty9;k4?:3y>62>=:;?01?6?:0d4?xu5?m0;6?u22659673<5;=n6<h8;|q13g<72;q6>:852378971d28l<7p}=8283>7}::>k1>?;4=3:7>4`03ty9454?:3y>6=b=?>16>5m51g58yv4??3:1>v3=8c82b2=::1i1;:5rs3:5>5<5s483m7?i7:?1<g<0?2wx>5;50;0x97>>28l<70<7a;54?xu51=0;6?u229a9673<5;3>6<h8;|q1=7<72;q6>5l5237897?428l<7p}=9183>7}::1k1>?;4=3;2>4`03ty94h4?:3y>6=?=:;?01?6i:0d4?xu51?0;6?u229f9673<5;3<6<h8;|q100<72;q6>9k51d18972228l<7p}=3b83>7}:::i1=k94=36f>21<uz8?87>53z?17f<5:<16>9j51d18972328l<7p}=3c83>6}:::h1=k94=31`>21<5;>o6:94}r077?6=;r79?o4=249>61e=9l901?:<:0d4?xu5;h0;6>u222c95c1<5;9i6:94=36`>21<uz8?>7>53z?17d<5:<16>9l51d18972528l<7p}=3883>6}:::31=k94=31b>21<5;>i6:94}r075?6=;r79?44=249>61g=9l901?:>:0d4?xu5;10;6>u222:95c1<5;926:94=36b>21<uz8?<7>53z?17=<5:<16>9751d18972728l<7p}=3683>6}:::=1=k94=31;>21<5;>26:94}r00b?6=;r79?:4=249>61>=9l901?=i:0d4?xu5;?0;6>u222495c1<5;9<6:94=36;>21<uz88i7>53z?173<5:<16>9951d18975b28l<7p}=3483>6}:::?1=k94=315>21<5;><6:94}r00`?6=;r79?i4>f69>663=:;?01?:9:0g0?xu5;=0;6>u222695c1<5;9>6:94=365>21<uz8=57>52z?11<<>92798;4>f69~w70f2909w0<:a;;2?843?3;m;6s|27`94?4|5;?i64?4=36;>4`03ty9:n4?:3y>60e=1816>9751g58yv41l3:1>v3=5e8:5>;5<h0:j:5rs34f>5<5s48>i77>;<07f?7a?2wx>;h50;0x973a20;01?:l:0d4?xu5?90;6?u22729=4=::=n1=k94}r045?6=:r79:<461:?10`<6n>1v?88:181844<33?70<98;3e3>{t:<:1<7<t=37:>766348?j7?61:p607=838p1?;n:322?843n3;2?6s|24094?4|5;?i6?>>;<07b?7?n2wx>8=50;0x973d2;::70<93;3:4>{t:<>1<7<t=37g>766348=87?7f:p603=838p1?;j:322?843n3;2<6s|24494?4|5;?m6?>>;<07b?7>:2wx>8950;0x97072;::70<94;3;a>{t:<21<7<t=342>766348?j7?7e:p630=838p1?89:322?841;3;3j6s|27794?4|5;<>6?>>;<057?7?m2wx>l850;6x97g028l<70<n6;3;b>;5i10:5=522`;95<7<uz8i?7>52z?1ff<>9279m<4>f69~w7d32909w0<md;;2?84f:3;m;6s|2c794?4|5;hn64?4=3c0>4`03ty9n;4?:3y>6g`=1816>l:51g58yv4e?3:1>v3=c18:5>;5i<0:j:5rs3`;>5<5s48h=77>;<0b2?7a?2wx>o750;0x97e520;01?o7:0d4?xu5jh0;6?u22b19=4=::h31=k94}r0f1?6=:r79ih4>e29>6`3=9o=0q~<kc;296~;5lj0:j:522dg932=z{;o?6=4<{<0gg?45=279ii4>e29>6`2=9o=0q~<kb;297~;5lk0:j:522ea932=::ln1;:5rs3g0>5<4s48on7<=5:?1af<6m:16>h=51g58yv4ci3:1?v3=d`82b2=::mh1;:522da932=z{;o96=4<{<0ge?45=279io4>e29>6`4=9o=0q~<k9;297~;5l00:j:522ec932=::lh1;:5rs3g2>5<4s48o57<=5:?1ad<6m:16>h?51g58yv4c03:1?v3=d982b2=::m31;:522dc932=z{;o;6=4<{<0g<?45=279i44>e29>6`6=9o=0q~<k7;297~;5l>0:j:522e:932=::l31;:5rs3fe>5<4s48o;7<=5:?1a=<6m:16>ih51g58yv4c>3:1?v3=d782b2=::m=1;:522d:932=z{;nn6=4<{<0g2?45=279i:4>e29>6ac=9o=0q~<k5;297~;5l<0:j:522e4932=::l=1;:5rs3fg>5<4s48o97<=5:?1a3<6m:16>ij51g58yv4c<3:1?v3=d582b2=::m?1;:522d4932=z{::36=4={<0g0??3349;47?i7:p6``=838p1?h?:0d4?857=3;2>6s|31;94?4|5;li64?4=3g5>4`03ty8<l4?:3y>6ce=1816>h951g58yv57j3:1>v3=fe8:5>;5m10:j:5rs22`>5<5s48mi77>;<0f=?7a?2wx?=j50;0x97`a20;01?kn:0d4?xu48l0;6?u23129=4=::lh1=k94}r13b?6=:r78<<461:?1af<6n>1v>??:181857:33:70<jd;3e3>{t;8;1<7<t=220><7<5;on6<h8;|q1b7<72;q6>kl5213897`6283:7p}=f283>7}::oi1>=?4=3d2>4>a3ty9j94?:3y>6cb=:9;01?h?:0;1?xu5n<0;6?u22gg9657<5;l;6<7>;|q1b3<72;q6>kh5213897`6282n7p}=f683>7}:;9:1>=?4=3d3>4>a3ty9j54?:3y>757=:9;01?h?:0:f?xu5n00;6?u23109657<5;l:6<7?;|q1bd<72;q6?==5213897`7283;7p}<0783>7}:;9<1>=?4=226>4>a3ty8<:4?:3y>751=:9;01>>::0:f?xu4<:0;69u235195=`<5:>?6<h8;<171?7>82788;4>909~w62a2909w0=:7;;2?854m3;m;6s|34294?4|5:?364?4=21e>4`03ty89<4?:3y>70?=1816?9>51g58yv52:3:1>v3<5`8:5>;4<80:j:5rs270>5<5s49>n77>;<176?7a?2wx?8:50;0x963d20;01>:<:0d4?xu4=<0;6?u234f9=4=:;=?1=k94}r162?6=:r789h461:?003<6n>1v?7i:180850:3??70<mb;;2?84f83;m;6s|1g094?4|5;>m6<h8;<057?7>;2wx=k=50;0x97`628l<70<i0;3:7>{t:?91<7<t=341><7<5;<86<h8;|q040<72;q6?=:5909>753=9o=0q~?i4;296~;5>=0:j:5227195<4<utd=>54?:0yK7<6<ug<957>51zJ0=5=zf?8j6=4>{I1:4>{i>;h1<7?tH2;3?xh1:j0;6<uG3828yk05l3:1=vF<919~j34b290:wE=60:m27`=83;pD>7?;|l575<728qC?4>4}o405?6=:rB85=5rn711>5<5sA92<6sa62194?4|@:3;7p`93583>7}O;0:0qc8<5;296~N4191vb;=9:181M5>82we:>950;0xL6?73td=?54?:3yK7<6<ug<857>52zJ0=5=zf?9j6=4={I1:4>{i>:h1<7<tH2;3?xh1;j0;6?uG3828yk04l3:1>vF<919~j35b2909wE=60:m26`=838pD>7?;|l505<72;qC?4>4}o475?6=:rB85=5rn761>5<5sA92<6sa65194?4|@:3;7p`94583>7}O;0:0qc8;5;296~N4191vb;:9:181M5>82we:9950;0xL6?73td=854?:3yK7<6<ug<?57>52zJ0=5=zf?>j6=4={I1:4>{i>=h1<7<tH2;3?xh1<j0;6?uG3828yk03l3:1>vF<919~j32b2909wE=60:m21`=838pD>7?;|l515<72;qC?4>4}o465?6=:rB85=5rn771>5<5sA92<6sa64194?4|@:3;7p`95583>7}O;0:0qc8:5;295~N4191vb;;9:182M5>82we:8950;3xL6?73td=954?:0yK7<6<ug<>57>51zJ0=5=zf??j6=4>{I1:4>{i><h1<7<tH2;3?xh1=j0;6>uG3828yk02l3:1?vF<919~j33b2909wE=60:m20`=838pD>7?;|l525<72;qC?4>4}o455?6=:rB85=5rn741>5<5sA92<6sa67194?4|@:3;7p`96583>7}O;0:0qc895;296~N4191vb;89:181M5>82we:;950;0xL6?73td=:54?:3yK7<6<ug<=57>52zJ0=5=zf?<j6=4={I1:4>{i>?h1<7<tH2;3?xh1>j0;6?uG3828yk01l3:1>vF<919~j30b2909wE=60:m23`=838pD>7?;|l535<72;qC?4>4}o445?6=:rB85=5rn751>5<5sA92<6sa66194?4|@:3;7p`97583>7}O;0:0qc885;296~N4191vb;99:181M5>82we::950;0xL6?73td=;54?:3yK7<6<ug<<57>52zJ0=5=zf?=j6=4={I1:4>{i>>h1<7<tH2;3?xh1?j0;6?uG3828yk00l3:1>vF<919~j31b2909wE=60:m22`=838pD>7?;|l5<5<72;qC?4>4}o4;5?6=:rB85=5rn7:1>5<5sA92<6sa69194?4|@:3;7p`98583>7}O;0:0qc875;296~N4191vb;69:181M5>82we:5950;0xL6?73td=454?:3yK7<6<ug<357>52zJ0=5=zf?2j6=4={I1:4>{i>1h1<7<tH2;3?xh10j0;6?uG3828yk0?l3:1>vF<919~j3>b2909wE=60:m2=`=838pD>7?;|l5=5<72;qC?4>4}o4:5?6=:rB85=5rn7;1>5<5sA92<6sa68194?4|@:3;7p`99583>4}O;0:0qc865;295~N4191vb;79:182M5>82we:4950;3xL6?73td=554?:0yK7<6<ug<257>51zJ0=5=zf?3j6=4>{I1:4>{i>0h1<7?tH2;3?xh11j0;6<uG3828yk0>l3:1=vF<919~j3?b290:wE=60:m2<`=83;pD>7?;|l5e5<728qC?4>4}o4b5?6=9rB85=5rn7c1>5<6sA92<6sa6`194?7|@:3;7p`9a583>4}O;0:0qc8n5;295~N4191vb;o9:182M5>82we:l950;3xL6?73td=m54?:0yK7<6<ug<j57>51zJ0=5=zf?kj6=4>{I1:4>{i>hh1<7?tH2;3?xh1ij0;6<uG3828yk0fl3:1=vF<919~j3gb290:wE=60:m2d`=83;pD>7?;|l5f5<728qC?4>4}o4a5?6=9rB85=5rn7`1>5<6sA92<6sa6c194?7|@:3;7p`9b583>4}O;0:0qc8m5;295~N4191vb;l9:182M5>82we:o950;3xL6?73td=n54?:0yK7<6<ug<i57>51zJ0=5=zf?hj6=4>{I1:4>{i>kh1<7?tH2;3?xh1jj0;6<uG3828yk0el3:1=vF<919~j3db290:wE=60:m2g`=83;pD>7?;|l5g5<728qC?4>4}o4`5?6=9rB85=5rn7a1>5<6sA92<6sa6b194?7|@:3;7p`9c583>4}O;0:0qc8l5;295~N4191vb;m9:182M5>82we:n950;3xL6?73td=o54?:0yK7<6<ug<h57>51zJ0=5=zf?ij6=4>{I1:4>{i>jh1<7?tH2;3?xh1kj0;6<uG3828yk0dl3:1=vF<919~j3eb290:wE=60:m2f`=83;pD>7?;|l5`5<728qC?4>4}o4g5?6=9rB85=5rn7f1>5<6sA92<6sa6e194?7|@:3;7p`9d583>4}O;0:0qc8k5;295~N4191vb;j9:182M5>82we:i950;3xL6?73td=h54?:0yK7<6<ug<o57>51zJ0=5=zf?nj6=4>{I1:4>{i>mh1<7?tH2;3?xh1lj0;6<uG3828yk0cl3:1=vF<919~j3bb290:wE=60:m2a`=83;pD>7?;|l5a5<728qC?4>4}o4f5?6=9rB85=5rn7g1>5<6sA92<6sa6d194?7|@:3;7p`9e583>4}O;0:0qc8j5;295~N4191vb;k9:182M5>82we:h950;3xL6?73td=i54?:0yK7<6<ug<n57>51zJ0=5=zf?oj6=4>{I1:4>{i>lh1<7?tH2;3?xh1mj0;6<uG3828yk0bl3:1=vF<919~j3cb290:wE=60:m2``=83;pD>7?;|l5b5<728qC?4>4}o4e5?6=9rB85=5rn7d1>5<6sA92<6sa6g194?7|@:3;7p`9f583>4}O;0:0qc8i5;295~N4191vb;h9:182M5>82we:k950;3xL6?73td=j54?:0yK7<6<ug<m57>51zJ0=5=zf?lj6=4>{I1:4>{i>oh1<7?tH2;3?xh1nj0;6<uG3828yk0al3:1=vF<919~j3`b290:wE=60:m2c`=83;pD>7?;|l445<728qC?4>4}o535?6=9rB85=5rn621>5<6sA92<6sa71194?7|@:3;7p`80583>4}O;0:0qc9?5;295~N4191vb:>9:182M5>82we;=950;3xL6?73td<<54?:0yK7<6<ug=;57>51zJ0=5=zf>:j6=4>{I1:4>{i?9h1<7?tH2;3?xh08j0;6<uG3828yk17l3:1=vF<919~j26b290:wE=60:m35`=83;pD>7?;|l455<728qC?4>4}o525?6=9rB85=5rn631>5<6sA92<6sa70194?7|@:3;7p`81583>4}O;0:0qc9>5;295~N4191vb:?9:182M5>82we;<950;3xL6?73td<=54?:0yK7<6<ug=:57>51zJ0=5=zf>;j6=4>{I1:4>{i?8h1<7?tH2;3?xh09j0;6<uG3828yk16l3:1=vF<919~j27b290:wE=60:m34`=83;pD>7?;|l465<728qC?4>4}o515?6=9rB85=5rn601>5<6sA92<6sa73194?7|@:3;7p`82583>4}O;0:0qc9=5;295~N4191vb:<9:182M5>82we;?950;3xL6?73td<>54?:0yK7<6<ug=957>51zJ0=5=zf>8j6=4>{I1:4>{i?;h1<7?tH2;3?xh0:j0;6<uG3828yk15l3:1=vF<919~j24b290:wE=60:m37`=83;pD>7?;|l475<728qC?4>4}o505?6=9rB85=5rn611>5<6sA92<6sa72194?7|@:3;7p`83583>4}O;0:0qc9<5;295~N4191vb:=9:182M5>82we;>950;3xL6?73td<?54?:0yK7<6<ug=857>51zJ0=5=zf>9j6=4>{I1:4>{i?:h1<7?tH2;3?xh0;j0;6<uG3828yk14l3:1=vF<919~j25b2909wE=60:m36`=83;pD>7?;|l405<728qC?4>4}o575?6=9rB85=5rn661>5<6sA92<6sa75194?7|@:3;7p`=5283>4}O;0:0qpsr@AAx<37=1m8>4:k6}ABA5{GHYqvLM
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.vhd b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.vhd
deleted file mode 100644
index 3e22cf4..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.vhd
+++ /dev/null
@@ -1,286 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
--- You must compile the wrapper file sync_fifo_progfull364_progempty128_512x36.vhd when simulating
--- the core, sync_fifo_progfull364_progempty128_512x36. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-LIBRARY XilinxCoreLib;
--- synthesis translate_on
-ENTITY sync_fifo_progfull364_progempty128_512x36 IS
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC;
-    prog_full : OUT STD_LOGIC;
-    prog_empty : OUT STD_LOGIC
-  );
-END sync_fifo_progfull364_progempty128_512x36;
-
-ARCHITECTURE sync_fifo_progfull364_progempty128_512x36_a OF sync_fifo_progfull364_progempty128_512x36 IS
--- synthesis translate_off
-COMPONENT wrapped_sync_fifo_progfull364_progempty128_512x36
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC;
-    prog_full : OUT STD_LOGIC;
-    prog_empty : OUT STD_LOGIC
-  );
-END COMPONENT;
-
--- Configuration specification
-  FOR ALL : wrapped_sync_fifo_progfull364_progempty128_512x36 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
-    GENERIC MAP (
-      c_add_ngc_constraint => 0,
-      c_application_type_axis => 0,
-      c_application_type_rach => 0,
-      c_application_type_rdch => 0,
-      c_application_type_wach => 0,
-      c_application_type_wdch => 0,
-      c_application_type_wrch => 0,
-      c_axi_addr_width => 32,
-      c_axi_aruser_width => 1,
-      c_axi_awuser_width => 1,
-      c_axi_buser_width => 1,
-      c_axi_data_width => 64,
-      c_axi_id_width => 4,
-      c_axi_ruser_width => 1,
-      c_axi_type => 0,
-      c_axi_wuser_width => 1,
-      c_axis_tdata_width => 64,
-      c_axis_tdest_width => 4,
-      c_axis_tid_width => 8,
-      c_axis_tkeep_width => 4,
-      c_axis_tstrb_width => 4,
-      c_axis_tuser_width => 4,
-      c_axis_type => 0,
-      c_common_clock => 1,
-      c_count_type => 0,
-      c_data_count_width => 9,
-      c_default_value => "BlankString",
-      c_din_width => 36,
-      c_din_width_axis => 1,
-      c_din_width_rach => 32,
-      c_din_width_rdch => 64,
-      c_din_width_wach => 32,
-      c_din_width_wdch => 64,
-      c_din_width_wrch => 2,
-      c_dout_rst_val => "0",
-      c_dout_width => 36,
-      c_enable_rlocs => 0,
-      c_enable_rst_sync => 1,
-      c_error_injection_type => 0,
-      c_error_injection_type_axis => 0,
-      c_error_injection_type_rach => 0,
-      c_error_injection_type_rdch => 0,
-      c_error_injection_type_wach => 0,
-      c_error_injection_type_wdch => 0,
-      c_error_injection_type_wrch => 0,
-      c_family => "virtex6",
-      c_full_flags_rst_val => 1,
-      c_has_almost_empty => 0,
-      c_has_almost_full => 0,
-      c_has_axi_aruser => 0,
-      c_has_axi_awuser => 0,
-      c_has_axi_buser => 0,
-      c_has_axi_rd_channel => 0,
-      c_has_axi_ruser => 0,
-      c_has_axi_wr_channel => 0,
-      c_has_axi_wuser => 0,
-      c_has_axis_tdata => 0,
-      c_has_axis_tdest => 0,
-      c_has_axis_tid => 0,
-      c_has_axis_tkeep => 0,
-      c_has_axis_tlast => 0,
-      c_has_axis_tready => 1,
-      c_has_axis_tstrb => 0,
-      c_has_axis_tuser => 0,
-      c_has_backup => 0,
-      c_has_data_count => 0,
-      c_has_data_counts_axis => 0,
-      c_has_data_counts_rach => 0,
-      c_has_data_counts_rdch => 0,
-      c_has_data_counts_wach => 0,
-      c_has_data_counts_wdch => 0,
-      c_has_data_counts_wrch => 0,
-      c_has_int_clk => 0,
-      c_has_master_ce => 0,
-      c_has_meminit_file => 0,
-      c_has_overflow => 0,
-      c_has_prog_flags_axis => 0,
-      c_has_prog_flags_rach => 0,
-      c_has_prog_flags_rdch => 0,
-      c_has_prog_flags_wach => 0,
-      c_has_prog_flags_wdch => 0,
-      c_has_prog_flags_wrch => 0,
-      c_has_rd_data_count => 0,
-      c_has_rd_rst => 0,
-      c_has_rst => 1,
-      c_has_slave_ce => 0,
-      c_has_srst => 0,
-      c_has_underflow => 0,
-      c_has_valid => 0,
-      c_has_wr_ack => 0,
-      c_has_wr_data_count => 0,
-      c_has_wr_rst => 0,
-      c_implementation_type => 0,
-      c_implementation_type_axis => 1,
-      c_implementation_type_rach => 1,
-      c_implementation_type_rdch => 1,
-      c_implementation_type_wach => 1,
-      c_implementation_type_wdch => 1,
-      c_implementation_type_wrch => 1,
-      c_init_wr_pntr_val => 0,
-      c_interface_type => 0,
-      c_memory_type => 1,
-      c_mif_file_name => "BlankString",
-      c_msgon_val => 1,
-      c_optimization_mode => 0,
-      c_overflow_low => 0,
-      c_preload_latency => 1,
-      c_preload_regs => 0,
-      c_prim_fifo_type => "512x36",
-      c_prog_empty_thresh_assert_val => 128,
-      c_prog_empty_thresh_assert_val_axis => 1022,
-      c_prog_empty_thresh_assert_val_rach => 1022,
-      c_prog_empty_thresh_assert_val_rdch => 1022,
-      c_prog_empty_thresh_assert_val_wach => 1022,
-      c_prog_empty_thresh_assert_val_wdch => 1022,
-      c_prog_empty_thresh_assert_val_wrch => 1022,
-      c_prog_empty_thresh_negate_val => 129,
-      c_prog_empty_type => 1,
-      c_prog_empty_type_axis => 0,
-      c_prog_empty_type_rach => 0,
-      c_prog_empty_type_rdch => 0,
-      c_prog_empty_type_wach => 0,
-      c_prog_empty_type_wdch => 0,
-      c_prog_empty_type_wrch => 0,
-      c_prog_full_thresh_assert_val => 364,
-      c_prog_full_thresh_assert_val_axis => 1023,
-      c_prog_full_thresh_assert_val_rach => 1023,
-      c_prog_full_thresh_assert_val_rdch => 1023,
-      c_prog_full_thresh_assert_val_wach => 1023,
-      c_prog_full_thresh_assert_val_wdch => 1023,
-      c_prog_full_thresh_assert_val_wrch => 1023,
-      c_prog_full_thresh_negate_val => 363,
-      c_prog_full_type => 1,
-      c_prog_full_type_axis => 0,
-      c_prog_full_type_rach => 0,
-      c_prog_full_type_rdch => 0,
-      c_prog_full_type_wach => 0,
-      c_prog_full_type_wdch => 0,
-      c_prog_full_type_wrch => 0,
-      c_rach_type => 0,
-      c_rd_data_count_width => 9,
-      c_rd_depth => 512,
-      c_rd_freq => 1,
-      c_rd_pntr_width => 9,
-      c_rdch_type => 0,
-      c_reg_slice_mode_axis => 0,
-      c_reg_slice_mode_rach => 0,
-      c_reg_slice_mode_rdch => 0,
-      c_reg_slice_mode_wach => 0,
-      c_reg_slice_mode_wdch => 0,
-      c_reg_slice_mode_wrch => 0,
-      c_synchronizer_stage => 2,
-      c_underflow_low => 0,
-      c_use_common_overflow => 0,
-      c_use_common_underflow => 0,
-      c_use_default_settings => 0,
-      c_use_dout_rst => 1,
-      c_use_ecc => 0,
-      c_use_ecc_axis => 0,
-      c_use_ecc_rach => 0,
-      c_use_ecc_rdch => 0,
-      c_use_ecc_wach => 0,
-      c_use_ecc_wdch => 0,
-      c_use_ecc_wrch => 0,
-      c_use_embedded_reg => 0,
-      c_use_fifo16_flags => 0,
-      c_use_fwft_data_count => 0,
-      c_valid_low => 0,
-      c_wach_type => 0,
-      c_wdch_type => 0,
-      c_wr_ack_low => 0,
-      c_wr_data_count_width => 9,
-      c_wr_depth => 512,
-      c_wr_depth_axis => 1024,
-      c_wr_depth_rach => 16,
-      c_wr_depth_rdch => 1024,
-      c_wr_depth_wach => 16,
-      c_wr_depth_wdch => 1024,
-      c_wr_depth_wrch => 16,
-      c_wr_freq => 1,
-      c_wr_pntr_width => 9,
-      c_wr_pntr_width_axis => 10,
-      c_wr_pntr_width_rach => 4,
-      c_wr_pntr_width_rdch => 10,
-      c_wr_pntr_width_wach => 4,
-      c_wr_pntr_width_wdch => 10,
-      c_wr_pntr_width_wrch => 4,
-      c_wr_response_latency => 1,
-      c_wrch_type => 0
-    );
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_sync_fifo_progfull364_progempty128_512x36
-  PORT MAP (
-    clk => clk,
-    rst => rst,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty,
-    prog_full => prog_full,
-    prog_empty => prog_empty
-  );
--- synthesis translate_on
-
-END sync_fifo_progfull364_progempty128_512x36_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.vho b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.vho
deleted file mode 100644
index aea0d36..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.vho
+++ /dev/null
@@ -1,97 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
---    Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3   --
---                                                                            --
---    Rev 1. The FIFO Generator is a parameterizable first-in/first-out       --
---    memory queue generator. Use it to generate resource and performance     --
---    optimized FIFOs with common or independent read/write clock domains,    --
---    and optional fixed or programmable full and empty flags and             --
---    handshaking signals.  Choose from a selection of memory resource        --
---    types for implementation.  Optional Hamming code based error            --
---    detection and correction as well as error injection capability for      --
---    system test help to insure data integrity.  FIFO width and depth are    --
---    parameterizable, and for native interface FIFOs, asymmetric read and    --
---    write port widths are also supported.                                   --
---------------------------------------------------------------------------------
-
--- Interfaces:
---    AXI4Stream_MASTER_M_AXIS
---    AXI4Stream_SLAVE_S_AXIS
---    AXI4_MASTER_M_AXI
---    AXI4_SLAVE_S_AXI
---    AXI4Lite_MASTER_M_AXI
---    AXI4Lite_SLAVE_S_AXI
---    master_aclk
---    slave_aclk
---    slave_aresetn
-
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-COMPONENT sync_fifo_progfull364_progempty128_512x36
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC;
-    prog_full : OUT STD_LOGIC;
-    prog_empty : OUT STD_LOGIC
-  );
-END COMPONENT;
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : sync_fifo_progfull364_progempty128_512x36
-  PORT MAP (
-    clk => clk,
-    rst => rst,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty,
-    prog_full => prog_full,
-    prog_empty => prog_empty
-  );
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file sync_fifo_progfull364_progempty128_512x36.vhd when simulating
--- the core, sync_fifo_progfull364_progempty128_512x36. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.xco b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.xco
deleted file mode 100644
index 1d5568c..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.xco
+++ /dev/null
@@ -1,213 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Mon Oct 20 06:54:50 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:fifo_generator:9.3
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=sync_fifo_progfull364_progempty128_512x36
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=128
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=129
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=364
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=363
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=36
-CSET input_depth=512
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=36
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
-CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=9
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET synchronization_stages=2
-CSET synchronization_stages_axi=2
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=9
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-11-19T12:39:56Z
-# END Extra information
-GENERATE
-# CRC: 5a086950
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.xise b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.xise
deleted file mode 100644
index 25275a6..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull364_progempty128_512x36.xise
+++ /dev/null
@@ -1,74 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="sync_fifo_progfull364_progempty128_512x36.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="sync_fifo_progfull364_progempty128_512x36.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|sync_fifo_progfull364_progempty128_512x36|sync_fifo_progfull364_progempty128_512x36_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="sync_fifo_progfull364_progempty128_512x36.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sync_fifo_progfull364_progempty128_512x36" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="sync_fifo_progfull364_progempty128_512x36" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-10-20T08:56:39" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="AC0F3EA8A81E4C04B9968B3CAC17B115" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.asy b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.asy
deleted file mode 100644
index 10dcc7d..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.asy
+++ /dev/null
@@ -1,45 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 sync_fifo_progfull504_progempty128_512x36
-RECTANGLE Normal 32 32 800 4064
-LINE Normal 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName clk
-PINATTR Polarity IN
-LINE Normal 0 112 32 112
-PIN 0 112 LEFT 36
-PINATTR PinName rst
-PINATTR Polarity IN
-LINE Wide 0 240 32 240
-PIN 0 240 LEFT 36
-PINATTR PinName din[35:0]
-PINATTR Polarity IN
-LINE Normal 0 272 32 272
-PIN 0 272 LEFT 36
-PINATTR PinName wr_en
-PINATTR Polarity IN
-LINE Normal 0 464 32 464
-PIN 0 464 LEFT 36
-PINATTR PinName full
-PINATTR Polarity OUT
-LINE Normal 0 528 32 528
-PIN 0 528 LEFT 36
-PINATTR PinName prog_full
-PINATTR Polarity OUT
-LINE Wide 832 272 800 272
-PIN 832 272 RIGHT 36
-PINATTR PinName dout[35:0]
-PINATTR Polarity OUT
-LINE Normal 832 304 800 304
-PIN 832 304 RIGHT 36
-PINATTR PinName rd_en
-PINATTR Polarity IN
-LINE Normal 832 496 800 496
-PIN 832 496 RIGHT 36
-PINATTR PinName empty
-PINATTR Polarity OUT
-LINE Normal 832 560 800 560
-PIN 832 560 RIGHT 36
-PINATTR PinName prog_empty
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.gise b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.gise
deleted file mode 100644
index 80d56a2..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.gise
+++ /dev/null
@@ -1,53 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="sync_fifo_progfull504_progempty128_512x36.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="sync_fifo_progfull504_progempty128_512x36.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="sync_fifo_progfull504_progempty128_512x36.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="sync_fifo_progfull504_progempty128_512x36.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1413798464" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1413798464">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="4645459345743859736" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="2199697938210370392" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1418036842" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="2373381159543708616" xil_pn:start_ts="1418036842">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.ngc b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.ngc
deleted file mode 100644
index 7b9b610..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$51144<,[o}e~g`n;"2*73>(-80!<m4/+])[WGIOL*!=6>:;123452739:;<=>?0123456789:;<=>?0123456789:;<=>?0123456789:;<=>?0123456788:0<=>?0123<56789:;==5?02C046G78::8<>>7;12A656A8=1;54>>;03b?42=AGZ^X7OKDSCQ@DBCZ5;86=0>a:37>LHW]]0JHI\MWSCG@W:6;3:5=95>6;KMTPR=L@KOE1?::1<20>712@D[YY4KICFJ843=87;>7<85OTVSQQ<CGHND0<;50?36?40=G\^[YY4KOCFL843=87;87<4FNQWW>WC@KLK7<7>11292>LHW]]0YIJMJB=294;76380BB][[:SQWE96=87;:7<4FNQWW>WUSJ5:1<3?420;86?OIX\^1MIJ]AUKFLLAO480;2<742;KMTPR=IMNYNYGJHHEK84<768>0>7GAPTV9@LVFL@Z7=7>11591>LHW]]0OE]LKIQ>2>586=281CXZ_UU8GKUGCGY6:6=0>5:09KPRW]]0OC]LKOQ>2>586;29=6D@_UU8GMKG;;<0;2<=4378JJUSS2MCEN1=::1<26>512@D[YY4kio>01?699<18:7AZTQWW>AIR\H6897>114902?IR\Y__6IAZTC>01?699=18:7AZTQWW>air|59>6=0;;563046<<3CE\XZ5WDC?7?69991?6D@_UU8TAG:4294:7;<46@682DGF02<JMLONA@33?3GFIHKJMLONA@CBEc=1~er:?=zif5:7)6773>LMJKHIFGDEBC@AN88047GAPTV9S@DPM5=1<3?4959:45?6:231EC^ZT;CG@WG;03:5=?56:HLSQQ<FLMXI054?>058=?IR\Y__6_JNDEPFGF:?294974O;;8CBE7=F>=1JM;O7;@CBE3GFI8:0MLONA@CB2DGFIHKJ46OKDSC?4;><IMNYM1?18:CG@WG;:720MIJ]A=1=<>GCL[K78364AEFQE93902KOH_O36?:8EABUI5=5m6OKDSC?<?6902KOH_O38?g8EABUI[NJHI\30?d8EABUI[NJHI\311<e?DBCZHXOMIJ]<03=b>GCL[KYHLJKR=31:47<IMNYM_JNDEP?56<76o1JHI\NRECG@W:6;7o0MIJ]ASFB@AT;97o0MIJ]ASFB@AT;:7o0MIJ]ASFB@AT;;7o0MIJ]ASFB@AT;<7o0MIJ]ASFB@AT;=7o0MIJ]ASFB@AT;>7o0MIJ]ASFB@AT;?7o0MIJ]ASFB@AT;07o0MIJ]ASFB@AT;17l0MIJ]AUKFLLAO494:=6OKDSCWM@NNOA6:6=0i;@FGVDRNMACLD1?18:CG@WD;8720MIJ]B=3=<>GCL[H7>364AEFQF95902KOH_L34?:8EABUJ5?546OKDS@?2;><IMNYN191a:CG@WD;03:546OKDS@?<;`<IMNYNYGJHHEK858692KOH_L[IDJJCM:6294m7LJKRCVJAMO@@5;5i6OKDS@TVDBCZ5:5j6OKDS@TVDBCZ5;;2k5NDEPASWGCL[6:=3h4AEFQFRTFLMX7=?0>1:CG@WDPZHNO^1?<:1<e?DBCZK]YMIJ]<01=a>GCL[H\^LJKR=3=a>GCL[H\^LJKR=0=a>GCL[H\^LJKR=1=a>GCL[H\^LJKR=6=a>GCL[H\^LJKR=7=a>GCL[H\^LJKR=4=a>GCL[H\^LJKR=5=a>GCL[H\^LJKR=:=a>GCL[H\^LJKR=;=7>GKD01J_T@L_SGD53=EEDUBBKAPAEFQAVUXZHDLI55MUR]JJCI63J80OH?=;BJFGNYKAJOE_HQ[YQG1?FO33JF@<;5LLJ3;43=DDB8<<85LLJ0[<>EKC;R:4=;4CMI:41=DDBK>7NBDA058GIMF9M8<7NBDA0F73>EKCH;O445LLJCQ@FJL<2IGGO;4CMIA5<=DDBH\^NBD5:AOOF723JF@H<;4CMIGRf=DDBN]SIGYIEG6?FJLNQ20OAEIX0:37>EKZ01HC@CFTUGG51=DG[OTKH@JR@VJKKYNFOE<7N\JAUGG5>B03MHBXH\]d:FFHD_BLV]YEYK=;EK;?AOFL@6;245KI@FJ846912NBMIG310<:?AOFL@6:>374DHCGM974601OELJF<06=f>BNIMC7=84?>89GMDBN48?546JFAEK?5;><L@KOE1<18:FJEAO;;720HDOKI=6=<>BNIMC79364DHCGM90902NBMIG37?:8@LGCA52546JFAEK?=;><L@HOE1>19:FJFAO;99427IGMDH>25;?<L@HOE1?=>89GMGBN489556JFBEK?518e3MCIHD2>5;2==>BNJMC7=807;EKA@L:6611OEOJF<3<;?AOEL@68255KICFJ818?3MCIHD2:>99GMGBN4?437IGMDH>4:==CAKNB0507;EKA@L:>6>1OECO30?:8@LHF48:546JFN@>25;><L@DJ0<<18:FJJD:6;720HD@N<06=<>BNFH6:9364DHLB840902NBBL2>7?:8@LHF482546JFN@>2=;1<L@DJ0<07;EKME947611OECO320<;?AOII589255KIOC?668?3MCEM1<;>99GMKG;:<437IGAA=05:==CAGK7>:07;EKME94?611OECO328<4?AOII58546JFN@>04;><L@DJ0>?18:FJJD:4:720HD@N<21=<>BNFH6883o4DHLB863=8720HD@N<27=3>BNFH682:5KIOC?0;1<L@DJ0808;EKME909?2NBBL28>69GMKG;07=0HD@N<8<4?AOIJ5:546JFNC>24;><L@DI0<?18:FJJG:6:720HD@M<01=<>BNFK6:8364DHLA843902NBBO2>6?:8@LHE48=546JFNC>2<;><L@DI0<717:FJJG:6611OECL321<;?AOIJ58:255KIO@?678?3MCEN1<<>99GMKD;:=437IGAB=06:==CAGH7>;07;EKMF940611OECL329<;?AOIJ5822:5KIO@?6;><L@DI0>>18:FJJG:49720HD@M<20=<>BNFK68?364DHLA8629i2NBBO2<5;2=<>BNFK689394DHLA86803MCEN1:17:FJJG:26>1OECL36?58@LHE4>4<7IGAB=:=3>BNFK622l5KIQCGMU:76j1OE]OKIQ>2>58f3MC[MIG_<0<b?AOWJMC[0=0l;EKSFAOW480;2l5KIQ@GMU:6611OCLJ@<1<:?AIFLF6:<374DNCGK976601OCLJ@<00==>BHIME7=>06;EMB@J:6<7h0HBOKO=36>58>3MEJHB2>5?:8@JGCG5;546J@AEM?6;><LFKOC1=18:FLEAI;<720HBOKO=7=<>BHIME7:364DNCGK91902NDMIA38?:8@JGCG535;6J@A^PFC==CGKND0=06;EMA@J:68730HBLKO=32:<=CGKND0<<19:FLFAI;9:427IAMDN>20;d<LFHOC1?::1<:?AIELF6:9364DN@GK97902NDNIA32?:8@JDCG59546J@BEM?0;><LFHOC1;18:FLFAI;>720HBLKO=5=<>BHJME74364DN@GK9?9?2NDNR\JG`9GKUGCGY6;2n5KOQCGKU:6294j7IA_AEMS848f3ME[NIA_<1<`?AIWJME[0<4?>`9GKUDCGY6:255KOTVB858>3ME^XL2>0?;8@JSSI5;:245KOTVB844912NDYYO312<:?AIR\H6:8374DNWWE972601OCXZN<04==>BH]]K7=:06;EMVPD:60730HB[[A=3::==CG\^J0<06;EMVPD:58730HB[[A=02:<=CG\^J0?<19:FLQQG;::427IAZT@>10;?<LF__M1<:>89GKPRF4;<556J@UUC?628>3ME^XL2=8?;8@JSSI582255KOTVB878>3ME^XL2<0?;8@JSSI59:245KOTVB864912NDYYO332<:?AIR\H6883l4DNWWE95229427IAZT@>01;><LF__M1=18:FLQQG;<720HB[[A=7=<>BH]]K7:364DNWWE91902NDYYO38?:8@JSSI53546J@UU@?4;?<LF__N1??>89GKPRE48;556J@UU@?578>3ME^XO2>3?;8@JSSJ5;?245KOTVA843912NDYYL317<:?AIR\K6:;374DNWWF97?601OCXZM<0;=<>BH]]H7=374DNWWF947601OCXZM<33==>BH]]H7>?06;EMVPG:5;730HB[[B=07:<=CG\^I0?;19:FLQQD;:?427IAZTC>13;?<LF__N1<7>89GKPRE4;3546J@UU@?6;?<LF__N1=?>89GKPRE4:;556J@UU@?778>3ME^XO2<3?;8@JSSJ59?2o5KOTVA863=8730HB[[B=16:==CG\^I0>07;EMVPG:3611OCXZM<4<;?AIR\K6=255KOTVA828?3ME^XO27>99GKPRE40487H@N7:GMEWBBF:1NBO94EO@TV@H682L>O9HIC5D645@A89?0JLB\E39E@6=ALJ>0JIMJ3:DGT1=ALYO?7KKIF028BC67NO:;JK>?FC210>@A?<;;7KHIFGDEB2@ANOLMJ<>4FGDEBC@ANOLMJKHJ1:E0?BHC92C97D>=;H31?L453@997D:=;H7;?LHN\YU;<55FNHVS[57?3@DBX]Q?299JJLRWW9937D@FTQ]30==NF@^[S=;7;HLJPUY7>11BBDZ__15:?LHN\Z^JXH94IOKW[5603@DBXR>>7:KMMQY7:>1BBDZP0258MKOSW9><7D@FT^263>OIA]U;::5FNHV\421<AGC_S=68;HLJPZ6>?2CEEYQ?A69JJLRX8K=0ECG[_1A4?LHN\V:O;6GAIU]3A2=NF@^T<K94IOKW[4603@DBXR?>7:KMMQY6:>1BBDZP1258MKOSW8><7D@FT^363>OIA]U:::5FNHV\521<AGC_S<68;HLJPZ7>?2CEEYQ>A69JJLRX9K=0ECG[_0A4?LHN\V;O;6GAIU]2A2=NF@^T=K94IOKW[7603@DBXR<>7:KMMQY5:>1BBDZP2258MKOSW;><7D@FT^063>OIA]U9::5FNHV\621<AGC_S?68;HLJPZ4>?2CEEYQ=A69JJLRX:K=0ECG[_3A4?LHN\V8O;6GAIU]1A2=NF@^T>K94IOKW[6603@DBXR=>7:KMMQY4:>1BBDZP3258MKOSW:><7D@FT^163>OIA]U8::5FNHV\721<AGC_S>68;HLJPZ5>?2CEEYQ<A69JJLRX;K=0ECG[_2A4?LHN\V9O;6GAIU]0A2=NF@^T?K84IOKW[D0<AGC_SO74IOKW[COKMm1BBGKLTE@JP@TUl2CEFHM[SCKWAWT43@D]>6BF6:NLEACC>2FDOFKK7:NLCLEFD=1GYY<;;MWW71=K]]>?7A[[559OQQ023DYLCC;4MTZ@]f=JiceyZh||inl`?Hoig{\n~~g`n39M47=I9;1E>?5A639M<2=IM]]D^F:4NNLF5>I6?2E[XDCFZD]SVLKN\@\N_R@HC09Sg>V):9;8==?<_M68TDTSi2ZBBRLZSHF[f>VNFVH^_COBE89SOZNK]]DF?6^]E79SWAIIM81Z46\NMC3;A4><ZHGTABJJc:PGEABUMJI7<3m4RECG@WCDK5;5o6\KAEFQAFE;:7i0^IOKDSG@G959k2XOMIJ]EBA?0;e<ZMKOH_KLC=7=g>TCIMNYINM36?a8VAGCL[OHO191e:PGEABUMJI747>1c:PGEABUMJI743?6;SFB@ATXKFFGE^G@N^JTGJHAANk0^HOK_GKQWQe<ZLKOSZGKTI]Bg>TBIMU\EIZG_C78V@ADMk1YIJMJA=294;?<ZLMHIL2?>c9QABEBI[OLOH84RDE@AGd<ZLMHIO2?:1<:?WC@KLH7<3j4RDE@HNGUL[IGG:5]EFAOOG?<ZZ^J0=4?>69QWQG;8730^^ZM<183:2=U[]H7<3j4RRVQEHGU[]XJA:5]SUPBIGb<ZZ^YIJO]SUPFC2=U[]XNKO?>;SQWV@AXX[CD^DZV_@32?WUSZLMT\_G@RHVZ[G7<[11XM[KKAUC4?VDN\LXY?6]KP038WMTBOVOSX_OLT^LDG`=T@[OLS@GA_RKYA45<[@GTOBBCIRKLJZEOMJAj7^GB_EGUMFC?3ZAB\R^FN79PKPTDM>1X^[OC_@58WWPFDVH=7^ZNTTQ7?QTRM=1_U]K7a:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'m{i#|kpd-NeabX{U{by|Pre]sea]>UVxoS}`{r^kmrZvflR3VSljk_3]LQQYdq5:54l5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(`xl$yh}k M`fg[rtXxg~ySjPp`fX=XYulVzexQfnw]sea]>UVkohR<POTV\g|:661k0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-cuc)zmzn#@okd^uq[uhszVxoS}ok[8_\vaYwf}xTecxPp`fX=XYflmU9SB[[_b{?6;>f3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&GjhiQxr^rmpwYulVzjhV7R_sf\tkruW`d}S}ok[8_\eabX:VE^XRmv<2<;e>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#ie/pgt`)JimnT{Qnup\vaYwimQ2QR|k_qlwvZoi~VzjhV7R_`fg[7YH]]Uhu1:18`9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$l|h }dqg,IdbcW~xT|cz}_sf\tdb\1TUyhR~ats]jjsYwimQ2QRokd^0\KPRXkp6>25o4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)oyo%~i~j/Lcg`ZquWyd~R|k_qcg_<[XzmU{by|Piot\tdb\1TUjhiQ=_NWW[f;>72j7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"Cnde]tvZvi|{UyhR~ndZ;^[wbXxg~ySd`y_qcg_<[XimnT>RAZT^az828?i2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/esa+tcxl%FmijPws]sjqtXzmU{miU6]^pg[uhszVcezR~ndZ;^[dbcW;UDYYQly=:=<g=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ hpd,q`uc(EhnoSz|Ppovq[wbXxhnP5PQ}d^rmpwYnfU{miU6]^cg`Z4XG\^T`xz31?:a?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*KflmU|~R~ats]q`ZvflR3VSjPpovq[lhqWykoW4SPaef\6ZIR\Vf~x1<18c9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$l|h }dqg,IdbcW~xT|cz}_sf\tdb\1TUyhR~ats]jjsYwimQ2QRokd^0\KPRXd|~7?36m;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&nzn"je.Ob`aYpzVzexQ}d^rb`^?ZW{nT|cz}_hlu[ugcS0WTmijP2^MVPZjr|5>54o5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(`xl$yh}k M`fg[rtXxg~ySjPp`fX=XYulVzexQfnw]sea]>UVkohR<POTV\hpr;=72i7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"Cnde]tvZvi|{UyhR~ndZ;^[wbXxg~ySd`y_qcg_<[XimnT>RAZT^nvp9090k1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,dt`(ulyo$Aljk_vp\tkruW{nT|ljT9\]q`Zvi|{Ubb{QaeY:YZgclV8TCXZPltv?3;>e3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&GjhiQxr^rmpwYulVzjhV7R_sf\tkruW`d}S}ok[8_\eabX:VE^XRbzt=:=<g=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ hpd,q`uc(EhnoSz|Ppovq[wbXxhnP5PQ}d^rmpwYnfU{miU6]^cg`Z4XG\^T`xz39?:a?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*KflmU|~R~ats]q`ZvflR3VSjPpovq[lhqWykoW4SPaef\6ZIR\Vrd~1?18c9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$l|h }dqg,IdbcW~xT|cz}_sf\tdb\1TUyhR~ats]jjsYwimQ2QRokd^0\KPRXpfx7>36m;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&nzn"je.Ob`aYpzVzexQ}d^rb`^?ZW{nT|cz}_hlu[ugcS0WTmijP2^MVPZ~hz5954o5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(`xl$yh}k M`fg[rtXxg~ySjPp`fX=XYulVzexQfnw]sea]>UVkohR<POTV\|jt;<72i7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"Cnde]tvZvi|{UyhR~ndZ;^[wbXxg~ySd`y_qcg_<[XimnT>RAZT^zlv9390k1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,dt`(ulyo$Aljk_vp\tkruW{nT|ljT9\]q`Zvi|{Ubb{QaeY:YZgclV8TCXZPxnp?2;>e3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&GjhiQxr^rmpwYulVzjhV7R_sf\tkruW`d}S}ok[8_\eabX:VE^XRv`r=5=<g=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ hpd,q`uc(EhnoSz|Ppovq[wbXxhnP5PQ}d^rmpwYnfU{miU6]^cg`Z4XG\^Ttb|38?:a?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*KflmU|~R~ats]q`ZvflR3VSjPpovq[lhqWykoW4SPaef\6ZIR\Vrd~1715g9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$l|h }dqg,[k67=8Ubb{Q\W142?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*bnnoU{by|Pp`f?5;063\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&nbjkQnup\tdb;:7<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"jffg]sjqtXxhn7?38>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&nzn"je.fjbcYwf}xT|lj34?42?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*bnnoU{by|Pp`f?1;063\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&nbjkQnup\tdb;>7<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"jffg]sjqtXxhn7;38>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&nzn"je.fjbcYwf}xT|lj38?42?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*bnnoU{by|Pp`f?=;073\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&nbjkQnup\tdbX9?:0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-cuc)zmzn#igif^rmpwYwimU9:=5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(`xl$yh}k dhde[uhszVzjhR=90:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'m{i#|kpd-gmc`Xxg~yS}ok_543?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*bnnoU{by|Pp`f\136<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!gqg-vavb'mcmjR~ats]seaY1>91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,dt`(ulyo$hdhi_qlwvZvflV==<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+awm'xo|h!kigd\tkruWykoS58?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&nzn"je.fjbcYwf}xT|ljP94f8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%k}k!rerf+uthoVof|ywPi768Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%k}k!rerf+uthoVof|ywPi^pppuis>11^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,dt`(ulyo$|ah_dosp|YnW{y|bzPSV26g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#ie/pgt`)uidUyhRka_h7`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"j~j.sfsa*tfeV}ySh`Pi708Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%k}k!rerf+rtXxg~ySjPp`f?4;043\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&}yS}`{r^pg[ugc494:4?5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(`xl$yh}k ws]sjqtXzmU{miU6]^pg[uhszVcezR~ndZ;^[dbcW;UDYY2>>908Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%k}k!rerf+rtXxg~ySjPp`fX=XYulVzexQfnw]sea]>UVkohR<POTV?6;>53\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.frf*wbwm&}yS}`{r^pg[ugcS0WT~iQnup\mkpXxhnP5PQnde]1[JSS4:43>6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+awm'xo|h!xr^rmpwYulVzjhV7R_sf\tkruW`d}S}ok[8_\eabX:VE^X1:1839V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$l|h }dqg,swYwf}xT~iQaeY:YZtcWyd~Rgav^rb`^?ZWhnoS?Q@UU>6:=4<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!gqg-vavb'~xT|cz}_sf\tdb\1TUyhR~ats]jjsYwimQ2QRokd^0\KPR;>7297X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*bvb&{n{i"y}_qlwvZtcWykoW4SPre]sjqtXag|T|ljT9\]b`aY5WF__0:072:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'m{i#|kpd-tvZvi|{UyhR~ndZ;^[wbXxg~ySd`y_qcg_<[XimnT>RAZT=:=<7=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ hpd,q`uc({U{by|Pre]sea]>UVxoS}`{r^kmrZvflR3VSljk_3]LQQ:>6?:0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j;$k`{w.bcqv|hb|5:5:=5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$o<!hmtz-gdtuqgo0<090:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'xxx~!l1.enq}(di{xrbhz32?43?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.a2+bkrp'ij~waeu>0:37<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!rrvp+f7(ods"jcT0\,di4(j9?;0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j;$k`{w.foX5X(`ez$f;?4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#n? glw{*bk\:T$la~ bs738Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b3,chs&ngP?P hmr,nw37<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!rrvp+f7(ods"jcT4\,div(j{<?0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j;$z<2?>448Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b3,r4:768?>7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*wus{&i:#{?31?75?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.a2+s7;97;>96[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/fppw+tt|z%h="x><3<62>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#||tr-`5*p64;4:985Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$o<!y1=1=13=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g4)q9595=8;4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#n? v0>7:00<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%l~~}!rrvp+f7(~86?2<8?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"m=/fov|+efz{seiy2?>728Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b0,chs&jky~t`jt=3=25=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&my~ }suq,g7)`e|r%ol|}yogw878182_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/pppv)d:&mfyu laspzj`r;;7<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*wus{&i9#jczx/en_5[)od;%a<8>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"m=/fov|+ajS8W%k`}!mr42?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.a1+bkrp'mfW?S!glq-iv063\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.sqww*e5'ng~t#ib[2_-chu)ez<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*wus{&i9#jczx/en_1[)ody%a~;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"m=/w3?4;313\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$k}|.sqww*e5';7<3?:5:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+btt{'xxx~!l2.t28482>2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#j||s/pppv)d:&|:0<0>549V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*au{z$yy} c3-u5949=?1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(k;%}=1<11478Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)`zzy%~~z|/b0,r4:46<<0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!hrrq-vvrt'j8$z<2<>076?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(o{yx"}{s.a1+s7;<7?=7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j gsqp*wus{&i9#{?34?366>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'nxx#||tr-`khv7=;1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"i}sr,qwqu(kfg{=;j4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#jafnf]fiur~Weojzd`h_dosp|YHZV<Tc;k4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-dvvu)zz~x#jafnf]fiur~Weojzd`h_dosp|YHZV<Tc<;m;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,cwut&{y"|nm^gntqXnkUb955Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.eqwv(u{}y$~lcPelrw}Zo3n2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#ob_sf\akYn9<=0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}d^rmpwYwd|y:0=0Piot4`>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!Baef\cf6)kfexV6R_FLG[743WfUjhiQ?_NWW[}iu494:=RGAV^243>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!Baef\cf6)kfexV6R_FLG[743WfUjhiQ?_NWW[}iu484:=:94U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'DkohRil0/alqkr\0TULBIQ=25]l[dbcW9UDYYQwos>1:470?2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-NeabXoj:%ob{atZ:^[BHCW;8?SbQnde]3[JSSWqey0>0>1658Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#@okd^e`4+eh}g~P4PQHNE]161YhWhnoS=Q@UU]{kw:368;<;6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)JimnTkn>!cnwmp^>ZWNDOS?<;_n]b`aY7WF__Sua}<4<2521<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/Lcg`Zad8'idyczT8\]DJAY5:=UdSljk_1]LQQYg{6=2<?88:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%FmijPgb2-gjsi|R2VSJ@K_307[jYflmU;SB[[_ymq838698=<7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*KflmUlo= lotlw_=[XOGNT>?:Po^cg`Z6XG\^Ttb|37?3232=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| M`fg[be7&je~byU7]^EM@Z45<VeTmijP0^MVPZ~hz525=<;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?4;323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~7=3;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?6;323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~7?3;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?0;323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~793;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?2;323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~7;3;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov?<;0d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~P4PQHNE]161YhWhnoS=Q@UU>2:3e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}Q3QRIAD^010ZiXimnT<RAZT=0=2f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|R2VSJ@K_307[jYflmU;SB[[<2<5g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsS1WTKCJP236\kZgclV:TCXZ34?4`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*wb(zyd~"il0/alqkr\0TULBIQ=25]l[dbcW9UDYY2:>7a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjq]?UVMEHR<=4^m\eabX8VE^X1816b9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,q`*twf}x$kn>!cnwmp^>ZWNDOS?<;_n]b`aY7WF__0:09c:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw_=[XOGNT>?:Po^cg`Z6XG\^743;;;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\402<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}U:995Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= }d.psjqt(oj:%ob{at^060>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsW:??7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*ad8'idyczP4468Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjqY2==1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexR8:4:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw[2333\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&{n$~}`{r.e`4+eh}g~T4864U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu]g5979=11^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$yh"|nup,cf6)kfexRj><3<6<>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsWm;7?3;7;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.sf,vuhsz&mh<#m`uov\`4:36<20Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+be7&je~byQk1=7=1==R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| gb2-gjsi|Vn:0;0:8:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw[a7;?7?37X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"j rqlwv*ad8'idyczPd0>;:01<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6)zm%y|cz}/fa3*firf}Uo=R?:7:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%lo= lotlw[a7X:<=0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+be7&je~byQk1^163>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+tc'{zex!hc1,`kphsWm;T8894U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!re-qtkru'ni;"naznu]g5Z32?2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'xo#~ats-dg5(dg|dSi?P6458Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uxg~y#jm?.bmvjqYc9V=>;6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#|k/srmpw)`k9$hcx`{_e3\<<6<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!gqd-swva'DkohRy}_qlwvZvk}z;T|ljT9\]q`Zvi|{U|~Rgav^rb`^?ZWhnoS?Q@UU]`}969191^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$Aljk_vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVPZe~4842<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!Baef\swYwf}xT|a{|1^rb`^?ZW{nT|cz}_vp\mkpXxhnP5PQnde]1[JSSWjs7>37?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&nzm"z|f.Ob`aYpzVzexQltq2[ugcS0WT~iQnup\swYnfU{miU6]^cg`Z4XG\^Tot2<>828Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%k}h!wsre+HgclV}yS}`{r^roqv7XxhnP5PQ}d^rmpwYpzVcezR~ndZ;^[dbcW;UDYYQly=6==5=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^az808>82_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/esb+quxo%FmijPws]sjqtXxex=R~ndZ;^[wbXxg~ySz|Piot\tdb\1TUjhiQ=_NWW[f;>73;7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*bva&~x{j"Cnde]tvZvi|{U{`x}>_qcg_<[XzmU{by|Pws]jjsYwimQ2QRokd^0\KPRXkp6<24>4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)oyl%{~i/Lcg`ZquWyd~R~cur3\tdb\1TUyhR~ats]tvZoi~VzjhV7R_`fg[7YH]]Uhu161909V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$l|k xrqd,IdbcW~xT|cz}_qnvw4YwimQ2QR|k_qlwvZquW`d}S}ok[8_\eabX:VE^XRbzt=3==4=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^nvp949181^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$Aljk_vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVPZjr|5955<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(`xo$|~}h M`fg[rtXxg~yS}bzs0]sea]>UVxoS}`{r^uq[lhqWykoW4SPaef\6ZIR\Vf~x1:1909V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$l|k xrqd,IdbcW~xT|cz}_qnvw4YwimQ2QR|k_qlwvZquW`d}S}ok[8_\eabX:VE^XRbzt=7==4=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^nvp909181^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$Aljk_vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVPZjr|5=55<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(`xo$|~}h M`fg[rtXxg~yS}bzs0]sea]>UVxoS}`{r^uq[lhqWykoW4SPaef\6ZIR\Vf~x161909V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$l|k xrqd,IdbcW~xT|cz}_qnvw4YwimQ2QR|k_qlwvZquW`d}S}ok[8_\eabX:VE^XRbzt=;==4=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^zlv979181^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$Aljk_vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVPZ~hz5855<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(`xo$|~}h M`fg[rtXxg~yS}bzs0]sea]>UVxoS}`{r^uq[lhqWykoW4SPaef\6ZIR\Vrd~1=1909V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$l|k xrqd,IdbcW~xT|cz}_qnvw4YwimQ2QR|k_qlwvZquW`d}S}ok[8_\eabX:VE^XRv`r=6==4=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^zlv939181^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$Aljk_vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVPZ~hz5<55<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(`xo$|~}h M`fg[rtXxg~yS}bzs0]sea]>UVxoS}`{r^uq[lhqWykoW4SPaef\6ZIR\Vrd~191909V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$l|k xrqd,IdbcW~xT|cz}_qnvw4YwimQ2QR|k_qlwvZquW`d}S}ok[8_\eabX:VE^XRv`r=:==4=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(EhnoSz|Ppovq[ujr{8U{miU6]^pg[uhszV}ySd`y_qcg_<[XimnT>RAZT^zlv9?9?91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$hdhi_qlwv^>ZWY]YS9>Po^grqdjX?Ve<?6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!kigd\tkruS1WT\Z\P41]l[`wrieU<Sb27>658Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%k}h!wsre+aoanVzexU7]^RTVZ27WfUn}xoc_6]l8=8X[^:==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!kigd\tkruWyko0<091:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'m{j#y}pg-gmc`Xxg~yS}ok<3<55>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#if/uqtc)caolT|cz}_qcg868192_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/esb+quxo%oekhPpovq[ugc4=4==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!kigd\tkruWyko08091:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'m{j#y}pg-gmc`Xxg~yS}ok<7<55>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#if/uqtc)caolT|cz}_qcg828192_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/esb+quxo%oekhPpovq[ugc414==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!kigd\tkruWyko04090:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'m{j#y}pg-gmc`Xxg~yS}ok_043?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"j~i.vpsb*bnnoU{by|Pp`f\636<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!gqd-swva'mcmjR~ats]seaY4>91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl$hdhi_qlwvZvflV>=<6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!kigd\tkruWykoS88?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&nzm"z|f.fjbcYwf}xT|ljP6728Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%k}h!wsre+aoanVzexQae]425=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ hpg,tvu`(l`lmS}`{r^rb`Z>182_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/esb+quxo%oekhPpovq[ugcW0?h7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*bva&~x{j"~}of]eqijXa?90Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hwrq-cu`){zm#}|`g^dvhiYnW{y|bz:c:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'m{j#y}pg-qehYulVoeSd;l;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&nzm"z|f.pbiZquWldTe;l4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)oyl%{~i/vp\tkruWyf~<Qae>3:Zkffm;346[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+awn'}y|k!xr^rmpwYwd|y:S}ok[8_\vaYwf}xT{Qfnw]sea]>UVkohR<POTV?5;>?3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.fre*rtwn&}yS}`{r^roqv7XxhnP5PQ}d^rmpwYpzVcezR~ndZ;^[dbcW;UDYY2=>9:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%k}h!wsre+rtXxg~yS}bzs0]sea]>UVxoS}`{r^uq[lhqWykoW4SPaef\6ZIR\595455Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(`xo$|~}h ws]sjqtXxex=R~ndZ;^[wbXxg~ySz|Piot\tdb\1TUjhiQ=_NWW818?02_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/esb+quxo%|~R~ats]shpu6WykoW4SPre]sjqtX{Ubb{QaeY:YZgclV8TCXZ35?:;?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"j~i.vpsb*quWyd~R~cur3\tdb\1TUyhR~ats]tvZoi~VzjhV7R_`fg[7YH]]6=2564U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)oyl%{~i/vp\tkruWyf~<QaeY:YZtcWyd~Ry}_hlu[ugcS0WTmijP2^MVP919011^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,dtc(pzyl${Qnup\tist9VzjhV7R_sf\tkruW~xTecxPp`fX=XYflmU9SB[[<9<;<>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#if/uqtc)pzVzexQltq2[ugcS0WT~iQnup\swYnfU{miU6]^cg`Z4XG\^7538?;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m?/fov|+efz{seiy2?>728Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%{~z|/b2,chs&jky~t`jt=3=25=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ xsuq,g5)`e|r%ol|}yogw878182_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d8&mfyu laspzj`r;;7<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i;#jczx/en_5[)od;%a<8>;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m?/fov|+ajS8W%k`}!mr42?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.a3+bkrp'mfW?S!glq-iv063\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e7'ng~t#ib[2_-chu)ez<:7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i;#jczx/en_1[)ody%a~;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m?/w3?4;313\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e7';7<3?:5:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l0.t28482>2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d8&|:0<0>549V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*ap{z$|y} c1-u5949=?1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,twqu(k9%}=1<11478Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)`zy%{~z|/b2,r4:46<<0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hwrq-svrt'j:$z<2<>076?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.a3+s7;<7?=7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| gvqp*rus{&i;#{?34?354>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`5*aj}q$hm|vndv?4;073\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e6'ng~t#mnrs{maq:66?:0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%{!hwrq-svrt'j;$k`{w.bcqv|hb|585:=5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$o<!hmtz-gdtuqgo0>091:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l1.enq}(`eR:V"jc>.l355>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`5*aj}q$laV?R.fop*hu192_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d9&mfyu hmZ0^*bkt&dy==6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+qt|z%h="ibuy,di^5Z&ngx"`}91:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l1.enq}(`eR>V"jc|.lq61>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'n}x#y|tr-`5*p6494>:6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/fupw+qt|z%h="x><1<210=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&m|~ xsuq,g4)q95;59;5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$o<!y1=3=503<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%l{~}!wrvp+f7(~8692884U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)z~x#n? v0>1:4323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$kz}|.vqww*e6';7?3;9;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,crut&~y"m>/w3?7;72=2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#jy|s/uppv)d9&|:090:6:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!l1.t28186=;1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ixsr,twqu(kfg{<8<4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-dsvu)z~x#nabp07b?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(o~yx"z}{s.pbiZ`rdeUhc`l:a:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+bqt{'}xx~!}al]eqijXnkUb9:5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.etwv(p{}y$~lcPftno[l2a3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x$~lcPws]fjZo6?j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,IdbcWnih<#il0/alqkr\0TULBIQ=36]l[dbcW9UDYYQwos>2:470k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-NeabXoji;"jm?.bmvjq]?UVMEHR<<7^m\eabX8VE^XRv`r=0=541d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.Ob`aY`kj:%kn>!cnwmp^>ZWNDOS?=8_n]b`aY7WF__Sua}<2<252e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%||cz}/Lcg`Zadk9$lo= lotlw_=[XOGNT>>9Po^cg`Z6XG\^Ttb|34?323f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| M`fg[bed8'mh<#m`uovX<XY@FMU9?:Q`_`fg[5YH]]Usc2:>034g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!Baef\cfe7&ni;"naznuY;YZAILV88;RaPaef\4ZIR\Vrd~181105g?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"Cnde]dgf6)oj:%ob{atZ:^[BHCW;9<SbQnde]3[JSSWqey0;0>105`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"Cnde]dgf6)oj:%ob{atZ:^[BHCW;9<SbQnde]3[JSSWqey0:0>16a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pxg~y#@okd^e`g5(`k9$hcx`{[9_\CKBX::=TcRokd^2\KPRXpfx743?>5`9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}6:28o4U1-{wqYaaoeTkh`jr`vlv*adgg|meka!rg-dvc(un&mex{Q`r^qzjfYaaoe%ka>!ws-ttkru'nih<#il0/alqkr;:7?j7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)`f}|TcQ|yoa\bl`h&nf;"z| wqlwv*adk9$lo= lotlw8682i2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dgf6)oj:%ob{at=6=1d=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~by2:>4c8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pxg~y#jml0/e`4+eh}g~7:3;n;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%lbyxPos]p}keXn`ld"jb?.vp,suhsz&mho= hc1,`kphs4>4>m6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(og~}Sb|Psxl`[coag'mg<#y}/vrmpw)`kj:%kn>!cnwmp9>9?81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznuY;YZAILV88;RaPaef\4ZIR\5;5;<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(oji;"jm?.bmvjq]?UVMEHR<<7^m\eabX8VE^X1<1709V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}Q3QRIAD^003ZiXimnT<RAZT=1=34=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byU7]^EM@Z44?VeTmijP0^MVP929?81^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznuY;YZAILV88;RaPaef\4ZIR\5?5;<5Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(oji;"jm?.bmvjq]?UVMEHR<<7^m\eabX8VE^X181709V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}Q3QRIAD^003ZiXimnT<RAZT=5=34=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byU7]^EM@Z44?VeTmijP0^MVP9>9=01^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]21<=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byQ=589V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}U8945Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(oji;"jm?.bmvjqY3=01^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]61<=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byQ9589V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}U<945Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(oji;"jm?.bmvjqY?=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5969=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5979=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5949=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5959=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5929=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5939=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5909=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5919=m1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g59>9=j1^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+bhs~VeyS~wac^djbj(`d9$|~"ynup,cfe7&ni;"naznu]g5Z62k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-dgf6)oj:%ob{at^f2[43d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-djqpXg{UxucmPfhdl*bj7&~x${}`{r.e`g5(`k9$hcx`{_e3\60e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-ci6){%||cz}/fa`4+ad8'idyczPd0]01f=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(pz&}{by| gba3*be7&je~byQk1^66g>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h govu[jtX{pdhSkgio/eo4+qu'~zex!hcb2-cf6)kfexRj>_47`?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"ilc1,dg5(dg|dSi?P64a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-sw)pxg~y#jml0/e`4+eh}g~Th<Q85b9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#j`{v^mq[vikVlbjb hl1,tv*qwf}x$knm?.fa3*firf}Uo=R6:3:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/uq+rtXxg~yS}bzs0>3:=7<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.empsYhzVyrbnQiigm-i`k(okg%koch.f`ncd(iolih"och/flbplpbjdm%blzfvd]ahnYjmdUlic!yamkg*fusz=n0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$x`~Pr`o\vaYbf=o0Y=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)elg$x`~Pr`o\vaYbf8987X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)uidUyhRka329V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#ob_vp\ak323\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&GfyuQ}d^pppZgtzlmTKCJP13]l[HS_W;Ud=<;:;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%yylck.Onq}YpzVxxxRo|rde\CKBX9;UdS@[W_0]l545c3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&XXXRHZLM]DAK2?3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&myyj>.fpppZ`rde$yyQk15:8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+btt|m;%k}{_gwoh+tt|Vn9855Z0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'{ynae gsqw`4(`zz~Tjxbc.sqw[a53k2_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%ekz|krrv-cwus&{nT~~zPrde?4;2d3\:$t~zPfhdl[bcim{kc!hcnlubl`h&{l$kh!rg-qwqdkc&dl{j}su,dvvr)zmUyyQ}ef>1:1d<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'gm|~i||t/eqwq(ulVxxxR|jg^27f>S7'qySkgio^efj`tf|fx$knaavgkek+ta'nxm"h rrvahn)io~xo~~z!gsqw*wbXzz~T~hiP25a8Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+kapzmxxx#i}su,tvZtt|Vxnk1?14c9V4*~t|VlbjbQheogqeqiu'nidb{hffn,qb*aun'xm#}{bmi,jbqul{y"j||t/uq[wusW{olS<=k;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%yylck.pg[wusWhyyij:j;T2,|vrXn`ldSjkaescwkw)`kfd}jdh`.sd,cw`)zo%yylck.pg[wusWhyyijQHNE]26ZiXE\RT>Ra;0:W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$~~zmlj-q`Ztt|Vkx~hiPd063?P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!}su`oo*tcW{ySl}}ef]g66e<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'{nT~~zPcnoa7a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim(zmUyyQlol`27a=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim({UyyQnssgd0`=R8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/sqwfim({UyyQnssgd[BHCW88TcRCZX^3\k16<]9%syQiigm\c`hbzh~d~"ilootemci)zo%l~k }f.pppgjl'~xT~~zParpfcZb6<91^<"v|t^djbjY`mgoymya}/faljs`nnf$yj"i}f/pe+wusjea${Q}su]bwwc`Wm88o6[?/yqw[coagVmnbh|ntnp,cfii~ocmc#|i/fpe*w`(zz~i`f!xr^pppZehek9o7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)u{}hgg"y}_sqw[fijj89m7X> xrv\bl`hWnoeio{os-dgjhqn`ld"h gsd-vc)pzVzex2?>^kmr4YNF_U;o6[\ES]UMVOEDL90ZNM6;WKFSZR^XL=0ZD\[EY45?RCF494=7ZKN<0<5?RCF4;437ZKN<283:3=PMH682;5XEC>3:3=PMK6:2;5XEC>1:==PMK686=09;VGA868?3^OI[H2?>99TAGQB48437ZKMWD>1:==PMK]N0>07;VGAS@:3611\IOYJ<4<;?RCE_L6=2l5XECUF82<7611\IOYJ<6<`?RTN\LUFCIKPAb9TVLRBWDEOIRLk;VPJP@YPAM^CSLj4WSKWAZQNL]BTN<j4XHNJJ]+_LK*;"<.\TT@#4+7'IZIBE85WOSAZ2>^T\ECI;6V\T^EM@2=_[]U]ONl4X^ALV@YNFOE=7Ujm_Hfe?]boWYxba[k}shmm55=_ldUFmga}Vdppmjh682RoaRCfnnpUawungg90T~z<;Xgp<d=XWVRGB@QP_1]\[P6(pz~Tjdh`_fgmawgsg{%lob`yfhdl*w`(o{l%~k!hnut\kwYtqgiTjdh`.fn3*rt(yd~"Cnde]dgf6)oj:%ob{atZ:^[BHCW;9<SbQnde]3[JSSWqey090>1978[ZY_DGGTSR?P_^W3+}usWocmcRijndpbpjt(ojeezkgio/pe+bta&{l$kczy_np\w|hdWocmc#ic0/pg+wvi|{%FmijPgb2-gjsi|R2VSJ@K_307[jYflmU;SB[[_ymq818691k0SRQWLOO\[Z4XWV_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,ckrqWfxTt`l_gkek+ak8'}y#z~ats-NeabXoji;"jm?.bmvjq]?UVMEHR<<7^m\eabX8VE^XRv`r=5=54>23VUTTA@B_^]0[ZYR8&rxxRhffn]dakcui}ey#jm`nwdjbj(un&myj#|i/flwrZiuWzseoRhffn,dh5(ul&x{by| M`fg[be7&je~byU7]^EM@Z45<VeTmijP0^MVPZ~hz5=5=<6n;^]\\IHJWVU?SRQZ0.zppZ`nnfUlick}aumq+behflbjb }f.eqb+ta'ndzRa}_r{mgZ`nnf$l`= xr.usjqt(EhnoSjml0/e`4+eh}g~P4PQHNE]172YhWhnoS=Q@UU]{kw:568;396QP_YNMIZYX=VUTY=!wsu]emciXoldn~lz`r.e`kkpaaoe%~k!hrg,qb*ai|Ud~R}vnb]emci)oe:%~i!}povq+HgclVmh<#m`uovX<XY@FMU9>9Q`_`fg[5YH]]Usc2=>036`>YXWQFEARQP6^]\Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"iatw]lvZu~fjUmeka!gm2-va)uidUyhRka_h357>YXWQFEARQP7^]\Q5){}UmekaPgdlfvdrhz&mhccxiigm-vc)`zo$yj"||tcnh+HkrpV}yS}{_`qqabY@FMU:>RaPMTZ\5Zi69?90SRQWLOO\[Z>XWV_;#u}{_gkekZabflxjxb| gbmmrcoag'xm#j|i.sd,vvredb%FaxvPre]qwqYf{{olSJ@K_00\kZKRPV8Tc<?>8:`ooZkbeVmnbRijndpjgZet|{;=7obd_lgn[bciWyxbaRyfduj2f>dkcVgnaRijn^rqmhYpzhz{iQy6g9ahnYjmdUlicQ{oq37?gjlWdofSjka_w5\5Z~t|890naePmdo\mkvr|Vhgcne>4:`ooZkbeVe~x}{{_cnlgn5<kea<7nabp`pf7>bce?1oec2?>69gmk:687=0hd`310<4?aoi4885;6jfn=30:2=cag6:8394dhl?50803mce0<817:fjj9706>1oec2>8?58`lh;904=7iga<0<4?aoi4;:5;6jfn=02:2=cag69>394dhl?66803mce0?:17:fjj9426>1oec2=6?58`lh;:>4<7iga<3:=3>bnf5822;5kio>1:2=cag68<394dhl?74803mce0><17:fjj9546>1oec2<4?;8`lh;;<0;2:5kio>01;0<l`d7?384dhl?0;0<l`d79384dhl?2;0<l`d7;384dhl?<;0<l`d75394dnww858?3me~x1??>99gkpr;98437iazt=31:==cg|~7=>07;emvp973611ocxz314<;?air|5;=255kotv?528?3me~x1?7>99gkpr;904<7iazt=3=<>bh}}69<364dnww877902ndyy2=2?:8`jss4;9546j`uu>10;><lf0?;18:flqq:5>720hb{{<35=<>bh}}694364dnww87?9?2ndyy2=>99gkpr;;9437iazt=12:==cg|~7??07;emvp954611ocxz335<b?air|59>6=07;emvp9526>1ocxz33?58`jss4=4<7iazt=7=3>bh}}6=2:5kotv?3;1<lf0508;emvp9?9=2of|yw>6:djbjY`mgoymya}_scnbl`h9;1mekaPgdlfvdrhzV~d|<=4fhdl[bcim{kcQy9^11b>`nnfUlick}aumq[s?X;%*Seagax!ALV@&@mgoymya} 06-341<n`ldSjkaescwkwYq1V9Tt~z;;gwoh<=nfySobd6:ofijt~02dloo{fle08jjg<g|~{yyQmljc8twi`Wlg{xt74psmd[cskd:80~lcconrX4X(uid$y#{8Pnnkmmq(uid%XH] XIEG\TWOJ91$ym`l4re]amkYdf}x>7jPeo:8vaYkgnch46|k_qg\wv753{nTyo{ur]ehdatWzy:=6|jsdv\fimXzhgmeka<;sqw6<=tqgiTjdh`_qplccskd<:?S}|`gdosp|750V?:>u=911f1?vikVlbjbQrneeqij28=U{~bijmqvz57>X=88s?;"iigm\c`hbzh~d~Rx6_2.xgZgclVdloRm`nrvqelhs59&hSl~lhabpliiW}s{iRowir?3(fYfxyfbolzfoo]w}ucXzhic1="l_`rshlef|`eeSywe^pggm;7$jUj|}bfc`vjkkYsqyoT{lmg=1.`[dvwd`ijxdaa_u{saZqcka7; nQnpqnjgdrnggUu}kPwsak95*dWhrbSljkr^uj`qn:;;&hSlvf_`pvw`tX`nd0?#c^c{mZgp}zoySzgkti?2(fYfp`Uiy~k}_vkgpm;6$jUjtdQkauc\slbs`4<? nQnxh]j`Zqnl}b68!mPayk\vpubzV}bhyf21-a\e}oX|pzn1="l_`zj[rstm{U|eizg=0.`[d~n{V~omyoPwhfwl803$jUjtd}PtegppZqnl}b68!mPaykp[qocW~coxe37,b]b|luX|bon|Ryfduj>0)eXiqcxSy}{rc]tmaro5=&hSlvfs^vvw`tX`nd0:#c^c{mvYsqyo6<!mPcnonkkYddfi`1<"l_bmvjqYsqyo6<!mPd`vb[firf}U|eizg=8.`[acai|fS{ocud?Ahdhl[}xbbj"l_ekm[roc|a78:!mPdhl\slbs`Vkse~3>,b]gmkYpam~cSolh<11(fYcagU|eizg_sf`l803$jUoecQxievk[rgd`499 nQkio]tmaroW~nhd08;,b]gmkYpam~cSz|lh<0/gZbh}}UyyQyam?3(fYcg|~T{dj{h<15(fYbfhhgiR|cobq>4)eXmgki`hQ}su]p}ke:9%iTi|`r^kmn`esafdTxt~j=1.`[`tug{Ubbgklthmm[qwmVkse~3?,b]fvwiuW`dainzfoo]w}ucXzhic1="l_dpqkwYnfcohxdaa_u{saZtcka7; nQjrsmq[lhmmj~bccQ{yqg\sdeo59&hSh|}os]jjocd|`eeSywe^uggm;7$jUn~a}_hliafrnggUu}kPwsak95*dWokfeaw2vhpwa}0+kVl~`aQil`ep[wusWkg1<"l_icp[djjgz~Ti`~{y<2/gZnf{Vkgab}{_gwoh86+kVbjRowi^cqqvcu59&hSeo|_`zj[dqr{lx6<!mPh`q\e}oXj|yn~0>#c^jbwZgaVxoSnfnnogo95*dWakxSlvf_swpaw;7$jUcm~Qnxh]tvZeoigdn`0>#c^jbwZgaV}~h|20-a\lduXiqcxSyjnt`?3(fYoizUjtd}Ptegpp86+kVbjRowir]wma;7$jUcm~Qnxhq\pncbx4:'oRfns^c{mvYsdhy1="l_icp[d~n{V~yiljv=0.`[mgtWhrbRz|ts`>4)eX`hyTmug|_uwpaw;7$jUcm~Qmabivt86+kVbjRjnt`]`kphs59&hSeo|_ecweZeh}g~xSlvfs<2/gZnf{VnjxlQlotlwwZtfka7; nQgar]geqgXkfex~Q}dbj>4)eX`hyThlzn_bmvjquXhic1="l_icp[agsiVidycz|_vf`l86+kVbjRjnt`]`kphs{V}yoe3?,b]kevYnf}Uh`f3?,b]kevYjiz~n~Rmj=1.`[mgtWdofecg{_gkoa86+kVbjRayesdokr;7$jUcm~Qrne\big`{Vkse~3?,b]kevYwzfmTjaohs^pbgm;7$jUcm~Qrne\big`{Vxooe3?,b]kevYwzfmTjaohs^ubgm;7$jUcm~Qrne\big`{V}ooe3?,b]kevYwzfmTjaohs^uqgm;7$jUcm~Q}d^fbpdYdg|d1="l_icp[wbXzz~6<!mPh`q\vvr:9%iTdl}PsmcuaZeb59&hSeo|_rppp86+kVbjR{addpehjq:8%iTdl}Pv`nj`86+kVbjRy}_`ah95*dWakxSz|Pd`vb[firf}7; nQgar]tvZtt|4:'oRgbpmgnakrf|`eeSywe<2/gZojxeoficznthmm[qwmVkse~3>,b]jiujbeldmyg`n^vzt`Yuijb6=!mPilroahci|h~bccQ{yqg\vaeo58&hSdcldofjqgsafdTxt~j_vc`l87+kVcf|akbeovbpliiW}s{iRykci?2(fYneyfnah`{aukljZr~xlU|~nf21-a\mkosW~xT|cz}_wco95*dW`dihncd]w}uc:8%iTahc`rx]w}uc:9%iTadhPfhnf[kgjm4Hgmce\tskmc)eXezmdbRxnl<3/gZiw|`gbvlzfoo]nkac:8%iTc{k}fmmt[iip59&hS}|jlncg[igsmgir1<"l_qpfhjgcW{ol0>#c^rqmhYaaoeTxt~j=431|60+kVzycjQjmqvz[qnumzbTm~}jru]uei;6:1&hS}|`g^gntqX|axneQnsrgqpZpfdVkse~3>030/gZvugnUna}zv_ujqavnXizyn~yQyam]qefn:9989 nQrne\ahvsqV~c~h}g_`qpawrX~hfT~img=0216)eXx{elShctx]wlwct`Vkxh|{_wco[rgd`4;;>?"l_qplcZcjx}sTxe|jsi]bwvcu|V|j`Rykci?2474+kVzycjQjmqvz[qnumzbTm~}jru]ueiYpzjb6==<=,b]svjaXmdzuRzgrdqk[kc`i}oTzlb213;/gZvugnUna}zv_u{sa87+kVzycjQjmqvz[qwmVkse~3?,b]svjaXmdzuRzvpd]qefn:8%iT|ah_dosp|YsqyoT~img=1.`[uthoVof|ywPtxrf[rgd`4:'oR~}of]fiur~W}s{iRykci?3(fYwzfmTi`~{y^vzt`Ypzjb6<!mPpsmd[cskdV~c~h}g_`qpawrX~hf69=:#c^rqkbYa}efTxe|jsi]bwvcu|V|j`Rowir?2475+kVzycjQiumn\pmtb{aUj~k}t^tbhZtfka7:<?=#c^rqkbYa}efTxe|jsi]bwvcu|V|j`R|kci?2475+kVzycjQiumn\pmtb{aUj~k}t^tbhZqfka7:<?=#c^rqkbYa}efTxe|jsi]bwvcu|V|j`Rykci?2475+kVzycjQiumn\pmtb{aUj~k}t^tbhZquka7:<?=#c^rqkbYa}efTxe|jsi]mabgsmV|j`0;?3-a\twi`Wog`Rzvpd?2(fYwzfmTjxbc_u{saZgaz7; nQrne\bpjkW}s{iR|nci?3(fYwzfmTjxbc_u{saZtcka7; nQrne\bpjkW}s{iRynci?3(fYwzfmTjxbc_u{saZqcka7; nQrne\bpjkW}s{iRy}ci?3(fYuijbTxt~j=1.`[wbXlh~jSnaznu]tmaro50&hSjPddrwl836:%iT~iQirds>5)eXzmU{by|Pwhfwl8?+kVxooeQ{yqg>4)eXzlmTagle^ol``Yfp`y6<!mPrde\wiodmVgdhhQ}abj>4)eXzlmTagle^ol``Yuljb6<!mPrde\wiodmVgdhhQxabj>4)eXzlmTagle^ol``Ypljb6<!mPrde\wiodmVgdhhQxrbj>4)eX{pdhdaai{gq[vrfol79 nQznegqbiipWee|1="l_tqf[fijefdTc{k}fmmt95*dW|ynSnabmnl\qkbbzofd{0>#c^wpaZbbnhgxR}jtukmcv;7$jU~hQkotv\vvr:9%iTy~kPeba>4)eX}zoTinmPaykp95*dW|ynShml_sc`l86+kVxiRklc^pggm;7$jU~hQjcb]tefn:8%iTy~kPeba\saeo59&hSx}j_da`[rtd`4:'oR{|e^gnf`bcmmUyij3?,b]vw`Yaaoe::Rhcafq>4)eX}zoTjzh{_ecweZeh}g~6<!mPv`nj`Zjh4:'oRynci]w}uc:8%iT{img_u{sa86+kV}ySlmd_mmt95*dW~xThlzn_bmvjqYpam~c14"l_vp\``vs`4?:>!mPws]gauroWhrb0??25.`[rtXllzdR|nci?22)eX{Uoi}zg_sf`l877:=&hSz|PddrwlZqfka7::!mPws]gauroW~nhd0??25.`[rtXllzdRy}ci?22)eX{Um~h21-a\swYwf}xT{dj{h<;/gZquWyd~Ryfduj\e}ot58:'oRy}_qlwvZqnl}bT~lmg=5.`[rtXxg~ySzgkti]q`fn:99&hSz|Ppovq[roc|aU|mnf24-a\swYwf}xT{dj{h^uggm;68%iT{Qnup\slbs`V}yoe3;,b]tvZtb{yeehQcaugmg|;6$jU|~nfPtxrf95{382yrbnQiigm\twi`n|fg9=:Ppsmdahvsq883S8?=x24/bl`hWnoeio{os]u=Z5+sth0{Qmio]`jqt23~xTic64ws]okbod02}yS}hPsr31?rtX{}ky~Qil`ep[vuzHIz3:<5O@y61e?@=<3;p_4>53c795cg=9:9>?im5fdfgk5e;3;0b>l;:79'7g7=;hh0q^6j:2`6>4`f28989>jl:gd23>U6m=0?=i4?:01016bd2ol:m6]7e;62`?6=9:9>?im5fg3g?a25i3:1=7?tS8297g3=9ok1=>=:3ea9bc713^9>h4?:082>47csZ3;6>l::0db>454=:nh6kh>6:&0=7<6m?1]?o<52zw2a`<63|;nj7>4}%3ef?4f3k>9m7>5518g5?76krB85=5+221907g<R>91>v?j:339y!5e83>:46*86;61g>"?n3>9n6*=2`82?!45139i:6g<e683>!7al39n:6`>fb83?>o4m<0;6)?id;1f2>h6nj0:76g<e583>!7al39n:6`>fb81?>o4m:0;6)?id;1f2>h6nj0876g<e383>!7al39n:6`>fb87?>o4m80;6)?id;1f2>h6nj0>76g<dg83>!7al39n:6`>fb85?>o4ll0;6)?id;1f2>h6nj0<76g<de83>!7al39n:6`>fb8;?>o4lj0;6)?id;1f2>h6nj0276g<dc83>!7al39n:6`>fb8b?>o4lh0;6)?id;1f2>h6nj0i76g<d883>!7al39n:6`>fb8`?>o4l10;6)?id;1f2>h6nj0o76g<d683>!7al39n:6`>fb8f?>o4l?0;6)?id;1f2>h6nj0m76g<d583>!7al39n:6`>fb824>=n;m91<7*>fe80a3=i9oi1=<54i2f1>5<#9on1?h84n0d`>44<3`9o=7>5$0dg>6c13g;mo7?<;:k0`5<72-;mh7=j6:l2bf<6<21b?nh50;&2ba<4m?1e=km51498m6eb290/=kj53d48j4`d28<07d=ld;29 4`c2:o=7c?ic;34?>o4kj0;6)?id;1f2>h6nj0:465f3b`94?"6nm08i;5a1ga95<=<a:on6=4+1gf97`0<f8lh6<o4;h1f`?6=,8lo6>k9;o3eg?7e32c8in4?:%3e`?5b>2d:jn4>c:9j7`d=83.:ji4<e79m5ce=9m10e>kn:18'5cb=;l<0b<hl:0g8?l5b13:1(<hk:2g5?k7ak3;m76g<e983>!7al39n:6`>fb814>=n;l:1<7*>fe80a3=i9oi1><54i2f6>5<#9on1?h84n0d`>74<3`9hm7>5$0dg>6c13g;mo7<<;:k0g2<722c?>44?::k76`<722c?>94?::m74f<72-;mh7:?b:l2bf<732e?<l4?:%3e`?27j2d:jn4>;:m74<<72-;mh7:?b:l2bf<532e?<54?:%3e`?27j2d:jn4<;:m742<72-;mh7:?b:l2bf<332e?<;4?:%3e`?27j2d:jn4:;:m741<72-;mh7:?b:l2bf<132e?<>4?:%3e`?27j2d:jn48;:m747<72-;mh7:?b:l2bf<?32e?<<4?:%3e`?27j2d:jn46;:m745<72-;mh7:?b:l2bf<f32e8jk4?:%3e`?27j2d:jn4m;:m0b`<72-;mh7:?b:l2bf<d32e8ji4?:%3e`?27j2d:jn4k;:m0bf<72-;mh7:?b:l2bf<b32e8jo4?:%3e`?27j2d:jn4i;:m0b<<72-;mh7:?b:l2bf<6821d?k650;&2ba<38k1e=km51098k6`0290/=kj541`8j4`d28807b=i6;29 4`c2=:i7c?ic;30?>i4n<0;6)?id;63f>h6nj0:865`3g694?"6nm0?<o5a1ga950=<g:l86=4+1gf905d<f8lh6<84;n1e6?6=,8lo69>m;o3eg?7032e8j<4?:%3e`?27j2d:jn4>8:9l7c6=83.:ji4;0c9m5ce=9010c9?<:18'5cb=<9h0b<hl:0c8?j26:3:1(<hk:52a?k7ak3;i76a;1083>!7al3>;n6`>fb82g>=h<8:1<7*>fe874g=i9oi1=i54o52e>5<#9on18=l4n0d`>4c<3f>;i7>5$0dg>16e3g;mo7?i;:m74a<72-;mh7:?b:l2bf<5821d8=;50;&2ba<38k1e=km52098k6`f290/=kj541`8j4`d2;807b=jf;29 4`c2=:i7c?ic;00?>i39h0;66a;1583>>i3:80;66a;2183>>d4io0;6<4?:1y'665=;0;0D>ok;I1:4>i6n00;66sm3`g94?7=83:p(?=<:0:`?M5fl2B85=5`19`94?=zj;3o6=4;:183!44;3;386F<ae9K7<6<,83h6l5f7583>>o>93:17d?if;29?j4793:17pl=9b83>1<729q/>>=51968L6gc3A92<6*>9b8b?l132900e4?50;9j5c`=831d>=?50;9~f65d290?6=4?{%007?7?<2B8mi5G3828 4?d2h1b;94?::k:5?6=3`;mj7>5;n035?6=3th8?o4?:583>5}#::91=5:4H2cg?M5>82.:5n4n;h57>5<<a0;1<75f1gd94?=h:9;1<75rb25:>5<3290;w)<<3;3;6>N4im1C?4>4$0;`>6=n?=0;66g7d;29?l?62900c?>>:188yg5?;3:187>50z&176<60=1C?lj4H2;3?M163-;no7<<2:k40?6=3`3:6=44i0de>5<<g;::6=44}c1;=?6=<3:1<v*=3282<1=O;hn0D>7?;I52?!7bk388>6g84;29?l?62900e<hi:188k7662900qo=8c;290?6=8r.9?>4>859K7db<@:3;7E9>;%3fg?44:2.:5n4n;h57>5<<a0;1<75f1gd94?=h:9;1<75rb2:5>5<4290;w)<<3;3;5>N4im1C?4>4H638 4cd2;997)?6c;18m22=831b5<4?::m144<722wi?5m50;194?6|,;986<6>;I1b`>N4191C;<5+1da9664<,83h6>5f7583>>o>93:17b<?1;29?xd4?k0;694?:1y'665=91>0D>ok;I1:4>N092.:in4=339'5<e=i2c<87>5;h;2>5<<a8lm6=44o322>5<<uk93<7>54;294~"5;:0:495G3`f8L6?73-;2o7o4i6694?=n180;66g>fg83>>i5880;66sm36d94?2=83:p(?=<:0:7?M5fl2B85=5+18a9e>o0<3:17d7>:188m4`a2900c?>>:188yg5?=3:1?7>50z&176<6081C?lj4H2;3?M163-;no7<<2:&2=f<43`=?6=44i8394?=h:9;1<75rb2:1>5<3290;w)<<3;3;0>N4im1C?4>4$0;`>d=n?=0;66g61;29?l7an3:17b<?1;29?xd40k0;6>4?:1y'665=91;0D>ok;I1:4>N092.:in4=339'5<e=;2c<87>5;h;2>5<<g;::6=44}c14e?6=<3:1<v*=3282<1=O;hn0D>7?;I52?!7bk388>6*>9b8b?l132900e4?50;9j5c`=831d>=?50;9~f615290ij7<560yK7<6<,;986>m?;[50>a}6;3;:6?=52g82g?732881>94<0;3g>4`=:908=7s+7381?l46k3:1(<hk:33a?k7ak3:07d<>4;29 4`c2;;87c?ic;28?l5>03:1(<hk:2;4?k7ak3:07d=66;29 4`c2:3<7c?ic;38?l5>=3:1(<hk:2;4?k7ak3807d=64;29 4`c2:3<7c?ic;18?l26290/=kj5419m5ce=821b?k4?:%3e`?273g;mo7?4;h1f>5<#9on18=5a1ga96>=n;m0;6)?id;63?k7ak3907d=l:18'5cb=<91e=km54:9j7g<72-;mh7:?;o3eg?3<3`9j6=4+1gf905=i9oi1:65f3883>!7al3>;7c?ic;58?l5?290/=kj5419m5ce=021bh94?:%3e`?b43g;mo7>4;hf1>5<#9on1h>5a1ga95>=nl80;6)?id;f0?k7ak3807dj?:18'5cb=l:1e=km53:9jgc<72-;mh7j<;o3eg?2<3`in6=4+1gf9`6=i9oi1965fcb83>!7al3n87c?ic;48?lee290/=kj5d29m5ce=?21bol4?:%3e`?b43g;mo764;ha:>5<#9on1h>5a1ga9=>=nk10;6)?id;f0?k7ak3k07dm8:18'5cb=l:1e=km5b:9jg3<72-;mh7j<;o3eg?e<3`i>6=4+1gf9`6=i9oi1h65fc583>!7al3n87c?ic;g8?le4290/=kj5d29m5ce=n21bo<4?:%3e`?b43g;mo7??;:k`4?6=,8lo6i=4n0d`>47<3`hm6=4+1gf9`6=i9oi1=?54icg94?"6nm0o?6`>fb827>=njm0;6)?id;f0?k7ak3;?76gmc;29 4`c2m90b<hl:078?lde290/=kj5d29m5ce=9?10eoo50;&2ba<c;2d:jn4>7:9jf<<72-;mh7j<;o3eg?7?32ci47>5$0dg>a5<f8lh6<74;hfa>5<#9on1h>5a1ga95d=<amk1<7*>fe8g7>h6nj0:n65fd883>!7al3n87c?ic;3`?>oc03:1(<hk:e18j4`d28n07dj8:18'5cb=l:1e=km51d98ma0=83.:ji4k3:l2bf<6n21bh84?:%3e`?b43g;mo7<?;:k``?6=,8lo6i=4n0d`>77<3`i96=4+1gf9`6=i9oi1>?54ic594?"6nm0o?6`>fb817>=n:8o1<7*>fe815a=i9oi1<65f20:94?"6nm09=:5a1ga94>=n;0n1<7*>fe80=f=i9oi1<65f38`94?"6nm085n5a1ga95>=n;0k1<7*>fe80=f=i9oi1>65f38;94?"6nm085n5a1ga97>=n=m0;6)?id;7`?k7ak3:07d;m:18'5cb==j1e=km51:9j1d<72-;mh7;l;o3eg?4<3`?26=4+1gf91f=i9oi1?65f5983>!7al3?h7c?ic;68?l30290/=kj55b9m5ce==21b9;4?:%3e`?3d3g;mo784;h76>5<#9on19n5a1ga93>=n==0;6)?id;7`?k7ak3207dh6:18'5cb=n11e=km50:9jb2<72-;mh7h7;o3eg?7<3`l=6=4+1gf9b==i9oi1>65ff483>!7al3l37c?ic;18?l`3290/=kj5f99m5ce=<21bj>4?:%3e`?`?3g;mo7;4;hd2>5<#9on1j55a1ga92>=nn90;6)?id;d;?k7ak3=07dki:18'5cb=n11e=km58:9ja`<72-;mh7h7;o3eg??<3`oo6=4+1gf9b==i9oi1m65feb83>!7al3l37c?ic;`8?lce290/=kj5f99m5ce=k21bil4?:%3e`?`?3g;mo7j4;hg:>5<#9on1j55a1ga9a>=nm10;6)?id;d;?k7ak3l07dk9:18'5cb=n11e=km51198m`3=83.:ji4i8:l2bf<6921bi94?:%3e`?`?3g;mo7?=;:kf7?6=,8lo6k64n0d`>45<3`o96=4+1gf9b==i9oi1=954id394?"6nm0m46`>fb821>=nm90;6)?id;d;?k7ak3;=76gkf;29 4`c2o20b<hl:058?lbb290/=kj5f99m5ce=9110eij50;&2ba<a02d:jn4>9:9j556=83.:ji4i8:l2bf<6i21bjk4?:%3e`?`?3g;mo7?m;:kea?6=,8lo6k64n0d`>4e<3`lo6=4+1gf9b==i9oi1=i54iga94?"6nm0m46`>fb82a>=nnk0;6)?id;d;?k7ak3;m76gia;29 4`c2o20b<hl:328?l`5290/=kj5f99m5ce=:810eh950;&2ba<a02d:jn4=2:9j`f<72-;mh7h7;o3eg?4432c<i7>5;h34f?6=3`2?6=44i05g>5<<a8o:6=44i0g3>5<<g8>n6=4+1gf951b<f8lh6=54o06`>5<#9on1=9j4n0d`>4=<g8>i6=4+1gf951b<f8lh6?54o06b>5<#9on1=9j4n0d`>6=<g8>26=4+1gf951b<f8lh6954o06;>5<#9on1=9j4n0d`>0=<g8>=6=4+1gf951b<f8lh6;54o066>5<#9on1=9j4n0d`>2=<g8>?6=4+1gf951b<f8lh6554o060>5<#9on1=9j4n0d`><=<g8>96=4+1gf951b<f8lh6l54o062>5<#9on1=9j4n0d`>g=<g8>;6=4+1gf951b<f8lh6n54o01e>5<#9on1=9j4n0d`>a=<g89n6=4+1gf951b<f8lh6h54o01g>5<#9on1=9j4n0d`>c=<g89i6=4+1gf951b<f8lh6<>4;n30e?6=,8lo6<:k;o3eg?7632e:?44?:%3e`?73l2d:jn4>2:9l56>=83.:ji4>4e9m5ce=9:10c<=8:18'5cb=9=n0b<hl:068?j74>3:1(<hk:06g?k7ak3;>76a>3483>!7al3;?h6`>fb822>=h9:>1<7*>fe820a=i9oi1=:54o010>5<#9on1=9j4n0d`>4><3f;8>7>5$0dg>42c3g;mo7?6;:m210<72-;mh7?;d:l2bf<6i21d=8:50;&2ba<6<m1e=km51c98k434290/=kj515f8j4`d28i07b?:2;29 4`c28>o7c?ic;3g?>i6=80;6)?id;37`>h6nj0:i65`14294?"6nm0:8i5a1ga95c=<g8>m6=4+1gf951b<f8lh6?>4;n373?6=,8lo6<:k;o3eg?4632e:?n4?:%3e`?73l2d:jn4=2:9l567=83.:ji4>4e9m5ce=::10c<9<:18'5cb=9>80b<hl:198k416290/=kj51608j4`d2810c<9?:18'5cb=9>80b<hl:398k40a290/=kj51608j4`d2:10c<8j:18'5cb=9>80b<hl:598k40c290/=kj51608j4`d2<10c<8m:18'5cb=9>80b<hl:798k40f290/=kj51608j4`d2>10c<86:18'5cb=9>80b<hl:998k40?290/=kj51608j4`d2010c<88:18'5cb=9>80b<hl:`98k401290/=kj51608j4`d2k10c<8::18'5cb=9>80b<hl:b98k403290/=kj51608j4`d2m10c<8<:18'5cb=9>80b<hl:d98k405290/=kj51608j4`d2o10c<8?:18'5cb=9>80b<hl:028?j72n3:1(<hk:051?k7ak3;:76a>5d83>!7al3;<>6`>fb826>=h9<n1<7*>fe8237=i9oi1=>54o07`>5<#9on1=:<4n0d`>42<3f;>n7>5$0dg>4153g;mo7?:;:m21d<72-;mh7?82:l2bf<6>21d=8750;&2ba<6?;1e=km51698k43?290/=kj51608j4`d28207b?:7;29 4`c28=97c?ic;3:?>i6?h0;6)?id;346>h6nj0:m65`16;94?"6nm0:;?5a1ga95g=<g8=36=4+1gf9524<f8lh6<m4;n343?6=,8lo6<9=;o3eg?7c32e:;;4?:%3e`?70:2d:jn4>e:9l523=83.:ji4>739m5ce=9o10c<9;:18'5cb=9>80b<hl:328?j71k3:1(<hk:051?k7ak38:76a>6083>!7al3;<>6`>fb816>=h9<<1<7*>fe8237=i9oi1>>54o32g>5<#9on1>=m4n0d`>5=<g;:i6=4+1gf965e<f8lh6<54o32b>5<#9on1>=m4n0d`>7=<g;:26=4+1gf965e<f8lh6>54o32;>5<#9on1>=m4n0d`>1=<g;:<6=4+1gf965e<f8lh6854o325>5<#9on1>=m4n0d`>3=<g;:>6=4+1gf965e<f8lh6:54o327>5<#9on1>=m4n0d`>==<g;8<6=44o8094?=e;ho1<7?50;2x 754282h7E=nd:J0=5=h91h1<75rb501>5<?83:1<v*=328147=O;hn0D>7?;[50>`}6>3;<6o4l:0:95<<6i3;i6i4j:g824?4d2;91q)?i8;62a>h6910;7c?=a;28 4?32<1/=4;55:&2=3<23-;2;7;4$0;;>0=#903196*>9`86?!7>j3?0(<7k:49'5<c==2.:5k4:;%3b4?3<,8k:685+1`091>"6i:0>7)?n4;78 4g22<1/=l855:&2e2<23-;j47;4$0c:>0=#9hk196*>ac86?!7fk3?0(<ok:49'5dc==2.:mk4:;%3a4?3<,8h:685+1c091>"6j:0>7)?m4;78 4d22<1/=o855:&2f2<23-;i47;4$0`:>0=#9kk196*>bc86?!7ek3?0(<lk:49'5gc==2.:nk4:;%3`4?3<,8i:685+1b091>"6k:0>7)?l4;78 4e22<1/=n855:&2g2<23-;h47;4$0a:>0=#9jk196*>cc86?!7dk3?0(<mk:49'5fc==2.:ok4:;%3g4?3<,8n:685+1e091>"6l:0>7)?k4;78 4b22<1/=i855:&2`2<23-;o47;4$0f:>0=#9mk196*>dc86?!7ck3?0(<jk:59'5ac=<2.:hk4>f79'655=:;20(?>j:818j7772;>0b??>:19'675=:880(?<;:331?!45j3=;7)<=c;1:7>"5:o0?7)<<0;68 6g02;:m7)=n8;03b>h4i00;7c=na;07?!45>3;3<6g73;29?l>12900e<9l:188m41b2900e??::188m7712900e??6:18K67b<3`8:m7>5H30g?>o59o0;66g=2183>>o5:80;66g=2383>>o3?3:1(<hk:548j4`d2910e9;50;&2ba<3>2d:jn4>;:k70?6=,8lo6984n0d`>7=<a=91<7*>fe872>h6nj0876g:0;29 4`c2=<0b<hl:598m1`=83.:ji4;6:l2bf<232c?i7>5$0dg>10<f8lh6;54i5f94?"6nm0?:6`>fb84?>o3k3:1(<hk:548j4`d2110e9l50;&2ba<3>2d:jn46;:k7e?6=,8lo6984n0d`>d=<a=31<7*>fe872>h6nj0i76g;8;29 4`c2=<0b<hl:b98m14=83.:ji4;6:l2bf<c32c>?7>5$0dg>04<f8lh6=5G23f8?l36290/=kj5539m5ce=92B9>i54i7294?"6nm0>j6`>fb83?M45l21b9h4?:%3e`?3a3g;mo7?4H30g?>o1>3:1(<hk:778j4`d2910e;:50;&2ba<1=2d:jn4>;:k57?6=,8lo6;;4n0d`>7=<a?81<7*>fe851>h6nj0876g9f;29 4`c2??0b<hl:598m3c=83.:ji495:l2bf<232c=h7>5$0dg>33<f8lh6;54i7a94?"6nm0=96`>fb84?>o1j3:1(<hk:778j4`d2110e;o50;&2ba<1=2d:jn46;:k5=?6=,8lo6;;4n0d`>d=<a?21<7*>fe851>h6nj0i76g97;29 4`c2??0b<hl:b98m37=83.:ji495:l2bf<c32c2o7>5$0dg><d<f8lh6=54i8c94?"6nm02n6`>fb82?>o>13:1(<hk:8`8j4`d2;10e4650;&2ba<>j2d:jn4<;:k:3?6=,8lo64l4n0d`>1=<a0<1<7*>fe8:f>h6nj0>76gn5;29 4`c20h0b<hl:798md2=83.:ji46b:l2bf<032cj?7>5$0dg><d<f8lh6554i`094?"6nm02n6`>fb8:?>of93:1(<hk:8`8j4`d2h10el>50;&2ba<>j2d:jn4m;:k:b?6=,8lo64l4n0d`>f=<a0o1<7*>fe8:f>h6nj0o76g6d;29 4`c20h0b<hl:d98m<3=83.:ji46b:l2bf<a32cjh7>5$0dg>de<f8lh6=54i``94?"6nm0jo6`>fb82?>ofi3:1(<hk:`a8j4`d2;10el750;&2ba<fk2d:jn4<;:kb<?6=,8lo6lm4n0d`>1=<ah=1<7*>fe8bg>h6nj0>76gm6;29 4`c2hi0b<hl:798mg3=83.:ji4nc:l2bf<032ci87>5$0dg>de<f8lh6554ic194?"6nm0jo6`>fb8:?>oe:3:1(<hk:`a8j4`d2h10eo?50;&2ba<fk2d:jn4m;:ka4?6=,8lo6lm4n0d`>f=<ahl1<7*>fe8bg>h6nj0o76gne;29 4`c2hi0b<hl:d98md0=83.:ji4nc:l2bf<a32c:<>4?:%3e`?77:2d:jn4?;:k244<72-;mh7??2:l2bf<632c:<;4?:%3e`?77=2d:jn4?;:k241<72-;mh7??5:l2bf<632e:<h4?:%3e`?77l2d:jn4?;:m24f<72-;mh7??d:l2bf<632e:<o4?:%3e`?77l2d:jn4=;:m24d<72-;mh7??d:l2bf<432e:<44?:%3e`?77l2d:jn4;;:m24=<72-;mh7??d:l2bf<232e:=:4?:%3e`?77l2d:jn49;:m253<72-;mh7??d:l2bf<032e:=84?:%3e`?77l2d:jn47;:m251<72-;mh7??d:l2bf<>32e:=>4?:%3e`?77l2d:jn4n;:m257<72-;mh7??d:l2bf<e32e:=<4?:%3e`?77l2d:jn4l;:m255<72-;mh7??d:l2bf<c32e:<k4?:%3e`?77l2d:jn4j;:m242<72-;mh7??d:l2bf<a32e:>=4?:%3e`?76n2d:jn4?;:m25`<72-;mh7?>f:l2bf<632e:=i4?:%3e`?76n2d:jn4=;:m25f<72-;mh7?>f:l2bf<432e:=o4?:%3e`?76n2d:jn4;;:m25d<72-;mh7?>f:l2bf<232e:>44?:%3e`?76n2d:jn49;:m26=<72-;mh7?>f:l2bf<032e:>:4?:%3e`?76n2d:jn47;:m263<72-;mh7?>f:l2bf<>32e:>84?:%3e`?76n2d:jn4n;:m261<72-;mh7?>f:l2bf<e32e:>>4?:%3e`?76n2d:jn4l;:m267<72-;mh7?>f:l2bf<c32e:><4?:%3e`?76n2d:jn4j;:m25<<72-;mh7?>f:l2bf<a32e:>i4?:%3e`?75k2d:jn4?;:m26g<72-;mh7?=c:l2bf<632e:?=4?:%3e`?75n2d:jn4?;:m26`<72-;mh7?=f:l2bf<632c8554?:%3e`?5>?2d:jn4?;I01`>=n;0<1<7*>fe80=2=i9oi1=6F=2e98m6?2290/=kj53858j4`d2;10e>7;:18'5cb=;0=0b<hl:298m6g1290/=kj53`78j4`d291C>?j4;h1b0?6=,8lo6>o:;o3eg?7<@;8o76g<a283>!7al39j96`>fb81?M45l21b?l<50;&2ba<4i<1e=km53:J16a=<a:k:6=4+1gf97d3<f8lh6954i2c3>5<#9on1?l;4n0d`>0=<a:3m6=4+1gf97d3<f8lh6;54i2;f>5<#9on1?l;4n0d`>2=<uz9287>55z\0=1=:<;81?l?4=501>6g734>9>7=6f:?767<41l1v9?50;0xZ17<5=896;84}r1e>5<5sW9m70:=2;47?xu4m3:1>vP<e:?767<1;2wx?i4?:3y]7a=:<;81:?5rs2a94?4|V:i019<=:7d8yv5e2909wS=m;<616?0b3ty8m7>52z\0e>;3:;0=h6s|3883>7}Y;0168?<56b9~w6>=838pR>64=501>3d<uzn?6=4={_f7?825:3;;:6s|d383>7}Yl;168?<5ae9~wa7=838pRi?4=501>dd<uzn;6=4={_f3?825:3kj7p}lf;296~Xdn27?>?4n9:pg`<72;qUoh524309e==z{ji1<7<t^ba891452h=0q~mm:181[ee34>9>7l9;|q`e?6=:rThm63;238a1>{tk00;6?uQc89>074=99>0q~m7:181[e?34>9>7l;;|q`3?6=:rTh;63;238a7>{tk?0;6?uQc79>074=j;1vn;50;0xZf3<5=896o?4}ra7>5<5sWi?70:=2;`3?xud;3:1>vPl3:?767<fn2wxo<4?:3y]g4=:<;81mh5rsb294?4|Vj:019<=:`48yvda2909wSli;<616?77;2wxnh4?:3y]f`=:<;815n5rscf94?4|Vkn019<=:8c8yvdd2909wSll;<616??>3tyin7>52z\af>;3:;0246s|b`83>7}Yjh168?<5969~wg?=838pRo74=501><0<uzh36=4={_`;?825:3k>7p}kb;296~Xcj27?>?4n4:p`d<72;qUhl524309557<uzn26=4={_f:?825:3k87p}k8;296~Xc027?>?4n2:p`2<72;qUh:524309e4=z{m<1<7<t^e4891452h:0q~j::181[b234>9>77i;|q``?6=:rThh63;238:a>{tk;0;6?uQc39>074=1m1vo950;0xZg1<5=8964;4}r02a?6=;rT9=h52430964`<5=896?<?;|q6`?6=:rT>h63;23873>{t=k0;6?uQ5c9>074=<<1v8o50;0xZ0g<5=8969:4}r7:>5<5sW?270:=2;60?xu203:1>vP:8:?767<282wx9:4?:3y]12=:<;818k5rs4494?4|V<<019<=:5g8yv322909wS;:;<616?2c3ty>87>52z\60>;3:;0?o6s|7d83>7}Y?l168?<5879~w41e2909wS?8b:?767<6?l1v5:50;0xZ=2<5=8965=4}r34`?6=:rT:;i52430952e<uz;<?7>52z\236=:<;81=>>4}r345?6=:rT:;<524309576<uz;<<7>52z\235=:<;81=<k4}r35b?6=:rT::k52430954b<uz;=i7>52z\22`=:<;81=<m4}r35`?6=:rT::i52430954d<uz;=n7>52z\22g=:<;81=<o4}r35e?6=:rT::l52430957?<uz;=57>52z\22<=:<;81=?64}r35<?6=:rT::552430957c<uz;=;7>52z\222=:<;81=?94}r352?6=:rT::;524309570<uz;=97>52z\220=:<;81=?;4}r350?6=:rT::9524309572<uz;=?7>52z\226=:<;81=?=4}r356?6=:rT::?524309574<uz;=<7>52z\225=:<;81=??4}r36b?6=:rT:9k52430954?<uz;>i7>52z\21`=:<;81=?j4}r36`?6=:rT:9i52430955c<uz;>o7>52z\21f=:<;81==m4}r36f?6=:rT:9o52430955d<uz;>m7>52z\21d=:<;81==o4}r36=?6=:rT:9452430955?<uz;>47>52z\21==:<;81==64}r363?6=:rT:9:524309541<uz;<m7>52z\23d=:<;81=<84}r34=?6=:rT:;452430957d<uz;<47>52z\23==:<;81=<;4}r343?6=:rT:;:524309542<uz;<:7>52z\233=:<;81=<=4}r341?6=:rT:;8524309544<uz;<87>52z\231=:<;81=<?4}r35g?6=:rT::n524309546<uz;==7>52z\224=:<;81==h4}r362?6=:rT:9;524309551<uz396=4;0z?0e`<60k1U5?5Q2358Z76c3W8;n6P=0`9]65?<V;:37S<?7:\143=Y:9?0R?>;;<616?46=27?>?4;b:?767<3i27?>?4;9:?767<3027?>?4;2:?767<1i27?>?499:?767<1027?>?497:?767<1927?>?4<949>074=;0>019<=:335?825:389=63;238167=Y9:;0R<=l;_373>X6<o1U=8>4^072?[72:2T:9>5Q1468Z4323W;8>6P>329]562<V89>7S?<6:\272=Y9:20R<=6;_30e>X6;k1U=>j4^01f?[74n2T:8=5Q1538Z4253W;??6P>459]513<V8>=7S?;8:\20<=Y9=k0R<:m;_37g>X6<l1vqo=>9;290?6=8r.9?>4>ee9K7db<@:3;7)?i8;62a>o0?3:17d7;:188m7422900c<h8:188yg5603:187>50z&176<6mm1C?lj4H2;3?!7a03>:i6g87;29?l?32900e?<::188k4`02900qo=>7;290?6=8r.9?>4>ee9K7db<@:3;7)?i8;62a>o0?3:17d7;:188m7422900c<h8:188yg56>3:187>50z&176<6mm1C?lj4H2;3?!7a03>:i6g87;29?l?32900e?<::188k4`02900qo=>a;290?6=8r.9?>4>ee9K7db<@:3;7)?i8;62a>o0?3:17d7;:188m7422900c<h8:188yg55k3:187>50z&176<6mm1C?lj4H2;3?!7a03>:i6g87;29?l?32900e?<::188k4`02900qo==b;290?6=8r.9?>4>ee9K7db<@:3;7)?i8;62a>o0?3:17d7;:188m7422900c<h8:188yg55i3:187>50z&176<6mm1C?lj4H2;3?!7a03>:i6g87;29?l?32900e?<::188k4`02900qo==9;290?6=8r.9?>4>ee9K7db<@:3;7)?i8;62a>o0?3:17d7;:188m7422900c<h8:188yg55l3:187>50z&176<6mm1C?lj4H2;3?!7a03>:i6g87;29?l?32900e?<::188k4`02900qo<89;290?6=8r.9?>4>ee9K7db<@:3;7)?i8;62a>o0?3:17d7;:188m7422900c<h8:188yg4003:187>50z&176<6mm1C?lj4H2;3?!7a03>:i6g87;29?l?32900e?<::188k4`02900qo<87;290?6=8r.9?>4>ee9K7db<@:3;7)?i8;62a>o0?3:17d7;:188m7422900c<h8:188yg40>3:187>50z&176<6mm1C?lj4H2;3?!7a03>:i6g87;29?l?32900e?<::188k4`02900qo<8a;290?6=8r.9?>4>ee9K7db<@:3;7)?i8;62a>o0?3:17d7;:188m7422900c<h8:188yg4?k3:187>50z&176<6mm1C?lj4H2;3?!7a03>:i6g87;29?l?32900e?<::188k4`02900qo<7b;290?6=8r.9?>4>ee9K7db<@:3;7)?i8;62a>o0?3:17d7;:188m7422900c<h8:188yg4?i3:187>50z&176<6mm1C?lj4H2;3?!7a03>:i6g87;29?l?32900e?<::188k4`02900qo<79;290?6=8r.9?>4>ee9K7db<@:3;7)?i8;62a>o0?3:17d7;:188m7422900c<h8:188yg4?l3:187>50z&176<6mm1C?lj4H2;3?!7a03>:i6g87;29?l?32900e?<::188k4`02900qo<;e;297?6=8r.9?>4<ab9K7db<@:3;7d98:188m4c42900c<h8:188yg43l3:1?7>50z&176<4ij1C?lj4H2;3?l102900e<k<:188k4`02900qo<<c;290?6=8r.9?>4>ee9K7db<@:3;7d98:188m<2=831b>?;50;9l5c1=831vn?:l:180>5<7s-88?7=nc:J0ea=O;0:0e:950;9j5`5=831d=k950;9~f75e290?6=4?{%007?7bl2B8mi5G3828m21=831b594?::k160<722e:j:4?::a61d=8391<7>t$310>6gd3A9jh6F<919j32<722c:i>4?::m2b2<722wi>>o50;694?6|,;986<kk;I1b`>N4191b;:4?::k:0?6=3`8997>5;n3e3?6=3th98l4?:283>5}#::91?lm4H2cg?M5>82c<;7>5;h3f7?6=3f;m;7>5;|`17<<72=0;6=u+22195`b<@:ko7E=60:k43?6=3`3?6=44i306>5<<g8l<6=44}c07=?6=;3:1<v*=3280ef=O;hn0D>7?;h54>5<<a8o86=44o0d4>5<<uk8847>54;294~"5;:0:ii5G3`f8L6?73`=<6=44i8694?=n:;?1<75`1g594?=zj;>36=4<:183!44;39jo6F<ae9K7<6<a>=1<75f1d194?=h9o=1<75rb314>5<3290;w)<<3;3f`>N4im1C?4>4i6594?=n1=0;66g=2483>>i6n>0;66sm25594?5=83:p(?=<:2c`?M5fl2B85=5f7683>>o6m:0;66a>f683>>{e::<1<7:50;2x 75428oo7E=nd:J0=5=n?>0;66g64;29?l45=3:17b?i7;29?xd5<?0;6>4?:1y'665=;hi0D>ok;I1:4>o0?3:17d?j3;29?j7a?3:17pl=3483>1<729q/>>=51df8L6gc3A92<6g87;29?l?32900e?<::188k4`02900qo<<d;297?6=8r.9?>4>e69K7db<@:3;7)?6c;06?l7?m3:17d?7f;29?j7a?3:17pl=3583>1<729q/>>=51df8L6gc3A92<6g87;29?l?32900e?<::188k4`02900qo<91;290?6=8r.9?>4>839K7db<@:3;7)?6c;18m22=831b4i4?::k:5?6=3f8;=7>5;|`125<72=0;6=u+22195=4<@:ko7E=60:&2=f<43`=?6=44i9f94?=n180;66a=0083>>{e:<l1<7:50;2x 75428297E=nd:J0=5=#90i1?6g84;29?l>c2900e4?50;9l657=831vn?;j:187>5<7s-88?7?72:J0ea=O;0:0(<7l:29j31<722c3h7>5;h;2>5<<g;::6=44}c06`?6=<3:1<v*=3282<7=O;hn0D>7?;%3:g?5<a>>1<75f8e83>>o>93:17b<?1;29?xd5=j0;694?:1y'665=9180D>ok;I1:4>"61j087d9;:188m=b=831b5<4?::m144<722wi>8l50;694?6|,;986<6=;I1b`>N4191/=4m53:k40?6=3`2o6=44i8394?=h:9;1<75rb37b>5<3290;w)<<3;3;6>N4im1C?4>4$0;`>6=n?=0;66g7d;29?l?62900c?>>:188yg4213:187>50z&176<60;1C?lj4H2;3?!7>k390e::50;9j<a<722c2=7>5;n035?6=3th9:;4?:583>5}#::91=5<4H2cg?M5>82.:5n4<;h57>5<<a1n1<75f9083>>i5880;66sm27794?2=83:p(?=<:0:1?M5fl2B85=5+18a97>o0<3:17d6k:188m<7=831d>=?50;9~f7b4290>6=4?{%007?7?;2B8mi5G3828 4?d2:1b;94?::k41?6=3`2o6=44i8394?=h:9;1<75rb3f1>5<2290;w)<<3;3;7>N4im1C?4>4$0;`>6=n?=0;66g85;29?l>c2900e4?50;9l657=831vn?j>:186>5<7s-88?7?73:J0ea=O;0:0(<7l:29j31<722c<97>5;h:g>5<<a0;1<75`21394?=zj;n;6=4::183!44;3;3?6F<ae9K7<6<,83h6>5f7583>>o0=3:17d6k:188m<7=831d>=?50;9~f7ea290>6=4?{%007?7?;2B8mi5G3828 4?d2:1b;94?::k41?6=3`2o6=44i8394?=h:9;1<75rb3af>5<2290;w)<<3;3;7>N4im1C?4>4$0;`>6=n?=0;66g85;29?l>c2900e4?50;9l657=831vn?mk:186>5<7s-88?7?73:J0ea=O;0:0(<7l:29j31<722c<97>5;h:g>5<<a0;1<75`21394?=zj;ih6=4::183!44;3;3?6F<ae9K7<6<,83h6>5f7583>>o0=3:17d6k:188m<7=831d>=?50;9~f7e4290>6=4?{%007?7?;2B8mi5G3828 4?d2:1b;94?::k41?6=3`2o6=44i8394?=h:9;1<75rb3a1>5<2290;w)<<3;3;7>N4im1C?4>4$0;`>6=n?=0;66g85;29?l>c2900e4?50;9l657=831vn?m>:186>5<7s-88?7?73:J0ea=O;0:0(<7l:29j31<722c<97>5;h:g>5<<a0;1<75`21394?=zj;i;6=4::183!44;3;3?6F<ae9K7<6<,83h6>5f7583>>o0=3:17d6k:188m<7=831d>=?50;9~f7da290>6=4?{%007?7?;2B8mi5G3828 4?d2:1b;94?::k41?6=3`2o6=44i8394?=h:9;1<75rb3`f>5<2290;w)<<3;3;7>N4im1C?4>4$0;`>6=n?=0;66g85;29?l>c2900e4?50;9l657=831vn?lk:186>5<7s-88?7?73:J0ea=O;0:0(<7l:29j31<722c<97>5;h:g>5<<a0;1<75`21394?=zj;hh6=4::183!44;3;3?6F<ae9K7<6<,83h6>5f7583>>o0=3:17d6k:188m<7=831d>=?50;9~f7de290>6=4?{%007?7?=2B8mi5G3828 4?d2h1b;94?::k41?6=3`3:6=44i0de>5<<g;::6=44}c0fa?6=;3:1<v*=3280ef=O;hn0D>7?;h54>5<<a8o86=44o0d4>5<<uk8nh7>53;294~"5;:08mn5G3`f8L6?73`=<6=44i0g0>5<<g8l<6=44}c0gg?6=<3:1<v*=3282aa=O;hn0D>7?;h54>5<<a0>1<75f23794?=h9o=1<75rb3g`>5<4290;w)<<3;1bg>N4im1C?4>4i6594?=n9l91<75`1g594?=zj;ni6=4;:183!44;3;nh6F<ae9K7<6<a>=1<75f9583>>o5:<0;66a>f683>>{e:lh1<7=50;2x 7542:kh7E=nd:J0=5=n?>0;66g>e283>>i6n>0;66sm2ec94?2=83:p(?=<:0gg?M5fl2B85=5f7683>>o><3:17d<=5;29?j7a?3:17pl=e`83>6<729q/>>=53`a8L6gc3A92<6g87;29?l7b;3:17b?i7;29?xd5l00;694?:1y'665=9ln0D>ok;I1:4>o0?3:17d7;:188m7422900c<h8:188yg4b13:1?7>50z&176<4ij1C?lj4H2;3?l102900e<k<:188k4`02900qo<k8;290?6=8r.9?>4>ee9K7db<@:3;7d98:188m<2=831b>?;50;9l5c1=831vn?k7:180>5<7s-88?7=nc:J0ea=O;0:0e:950;9j5`5=831d=k950;9~f7b0290?6=4?{%007?7bl2B8mi5G3828m21=831b594?::k160<722e:j:4?::a6`1=8391<7>t$310>6gd3A9jh6F<919j32<722c:i>4?::m2b2<722wi>i850;694?6|,;986<kk;I1b`>N4191b;:4?::k:0?6=3`8997>5;n3e3?6=3th9i;4?:283>5}#::91?lm4H2cg?M5>82c<;7>5;h3f7?6=3f;m;7>5;|`1`0<72=0;6=u+22195`b<@:ko7E=60:k43?6=3`3?6=44i306>5<<g8l<6=44}c0g0?6=<3:1<v*=3282aa=O;hn0D>7?;h54>5<<a0>1<75f23794?=h9o=1<75rb220>5<3290;w)<<3;3;6>N4im1C?4>4$0;`>6=n?=0;66g7d;29?l?62900c?>>:188yg57:3:187>50z&176<60;1C?lj4H2;3?!7>k390e::50;9j<a<722c2=7>5;n035?6=3th8<<4?:583>5}#::91=5<4H2cg?M5>82.:5n4<;h57>5<<a1n1<75f9083>>i5880;66sm31294?2=83:p(?=<:0:1?M5fl2B85=5+18a97>o0<3:17d6k:188m<7=831d>=?50;9~f7`a290?6=4?{%007?7?:2B8mi5G3828 4?d2:1b;94?::k;`?6=3`3:6=44o322>5<<uk8mi7>54;294~"5;:0:4?5G3`f8L6?73-;2o7=4i6694?=n0m0;66g61;29?j4793:17pl=fe83>1<729q/>>=51908L6gc3A92<6*>9b80?l132900e5j50;9j=4<722e9<<4?::a6ce=83>1<7>t$310>4>53A9jh6F<919'5<e=;2c<87>5;h:g>5<<a0;1<75`21394?=zj;li6=4;:183!44;3;3>6F<ae9K7<6<,83h6>5f7583>>o?l3:17d7>:188k7662900qo=?6;290?6=8r.9?>4>839K7db<@:3;7)?6c;18m22=831b4i4?::k:5?6=3f8;=7>5;|`042<72=0;6=u+22195=4<@:ko7E=60:&2=f<43`=?6=44i9f94?=n180;66a=0083>>{e;>:1<7;50;2x 75428287E=nd:J0=5=#90i1?6g84;29?l122900e5j50;9j=4<722e9<<4?::a73`=83?1<7>t$310>4>43A9jh6F<919'5<e=;2c<87>5;h56>5<<a1n1<75f9083>>i5880;66sm37g94?3=83:p(?=<:0:0?M5fl2B85=5+18a97>o0<3:17d9::188m=b=831b5<4?::m144<722wi?;j50;794?6|,;986<6<;I1b`>N4191/=4m53:k40?6=3`=>6=44i9f94?=n180;66a=0083>>{e;?i1<7;50;2x 75428287E=nd:J0=5=#90i1?6g84;29?l122900e5j50;9j=4<722e9<<4?::a73d=83?1<7>t$310>4>43A9jh6F<919'5<e=;2c<87>5;h56>5<<a1n1<75f9083>>i5880;66sm37c94?3=83:p(?=<:0:0?M5fl2B85=5+18a97>o0<3:17d9::188m=b=831b5<4?::m144<722wi?;750;794?6|,;986<6<;I1b`>N4191/=4m53:k40?6=3`=>6=44i9f94?=n180;66a=0083>>{e;?21<7;50;2x 75428287E=nd:J0=5=#90i1?6g84;29?l122900e5j50;9j=4<722e9<<4?::a70c=83?1<7>t$310>4>43A9jh6F<919'5<e=;2c<87>5;h56>5<<a1n1<75f9083>>i5880;66sm34f94?3=83:p(?=<:0:0?M5fl2B85=5+18a97>o0<3:17d9::188m=b=831b5<4?::m144<722wi?8m50;794?6|,;986<6<;I1b`>N4191/=4m53:k40?6=3`=>6=44i9f94?=n180;66a=0083>>{e;<h1<7;50;2x 75428287E=nd:J0=5=#90i1?6g84;29?l122900e5j50;9j=4<722e9<<4?::a70g=83?1<7>t$310>4>43A9jh6F<919'5<e=;2c<87>5;h56>5<<a1n1<75f9083>>i5880;66sm34;94?3=83:p(?=<:0:0?M5fl2B85=5+18a97>o0<3:17d9::188m=b=831b5<4?::m144<722wi?8650;794?6|,;986<6<;I1b`>N4191/=4m53:k40?6=3`=>6=44i9f94?=n180;66a=0083>>{e;<=1<7;50;2x 75428287E=nd:J0=5=#90i1?6g84;29?l122900e5j50;9j=4<722e9<<4?::a6<c=8391<7>t$310>4c03A9jh6F<919'5<e=9<1/=kk53cf8m4>b2900e<6i:188k4`02900qo=<d;297?6=8r.9?>4>e69K7db<@:3;7)?6c;36?l7?m3:17d?7f;29?j7a?3:17pl<7583>1<729q/>>=51d:8L6gc3A92<6*>9b841>"6nl08ni5f19g94?=n91l1<75f18294?=h9o=1<75rb3;a>5<0290;w)<<3;3ff>N4im1C?4>4$0;`>41a3`;3i7>5;h3;b?6=3`;2<7>5;h3:5?6=3`;2>7>5;h3:7?6=3f;m;7>5;|`032<72:0;6=u+22195`1<@:ko7E=60:&2=f<6=2.:jh4<bg9j5=c=831b=5h50;9l5c1=831vn>97:180>5<7s-88?7?j7:J0ea=O;0:0(<7l:078 4`b2:hn7d?7e;29?l7?n3:17b?i7;29?xd4010;6>4?:1y'665=9l=0D>ok;I1:4>"61j0:96*>fd80fc=n91o1<75f19d94?=h9o=1<75rb2:f>5<4290;w)<<3;3f3>N4im1C?4>4$0;`>43<,8ln6>lj;h3;a?6=3`;3j7>5;n3e3?6=3th8>?4?:483>5}#::91=h74H2cg?M5>82.:5n4=e:k2<`<722c:4k4?::k2=5<722c:5<4?::m2b2<722wi??>50;794?6|,;986<k6;I1b`>N4191/=4m52d9j5=c=831b=5h50;9j5<6=831b=4?50;9l5c1=831vn>?j:186>5<7s-88?7?j9:J0ea=O;0:0(<7l:3g8m4>b2900e<6i:188m4?72900e<7>:188k4`02900qo==4;297?6=8r.9?>4>e69K7db<@:3;7)?6c;0g?l7?m3:17d?7f;29?j7a?3:17pl<3483>0<729q/>>=51d;8L6gc3A92<6*>9b81a>o60l0;66g>8g83>>o6190;66g>9083>>i6n>0;66sm32194?3=83:p(?=<:0g:?M5fl2B85=5+18a96`=n91o1<75f19d94?=n90:1<75f18394?=h9o=1<75rb212>5<2290;w)<<3;3f=>N4im1C?4>4$0;`>7c<a82n6=44i0:e>5<<a83;6=44i0;2>5<<g8l<6=44}c103?6=;3:1<v*=3282a2=O;hn0D>7?;%3:g?4c3`;3i7>5;h3;b?6=3f;m;7>5;|`1<7<72<0;6=u+22195`?<@:ko7E=60:&2=f<5m2c:4h4?::k2<c<722c:5=4?::k2=4<722e:j:4?::a6=6=83?1<7>t$310>4c>3A9jh6F<919'5<e=:l1b=5k50;9j5=`=831b=4>50;9j5<7=831d=k950;9~f71b290>6=4?{%007?7b12B8mi5G3828 4?d2;o0e<6j:188m4>a2900e<7?:188m4?62900c<h8:188yg4?<3:1?7>50z&176<6m>1C?lj4H2;3?!7>k38o7d?7e;29?l7?n3:17b?i7;29?xd51<0;684?:1y'665=9l30D>ok;I1:4>"61j09i6g>8d83>>o60o0;66g>9183>>o6180;66a>f683>>{e:091<7;50;2x 75428o27E=nd:J0=5=#90i1>h5f19g94?=n91l1<75f18294?=n90;1<75`1g594?=zj;3:6=4::183!44;3;n56F<ae9K7<6<,83h6?k4i0:f>5<<a82m6=44i0;3>5<<a83:6=44o0d4>5<<uk83j7>55;294~"5;:0:i45G3`f8L6?73-;2o7<j;h3;a?6=3`;3j7>5;h3:4?6=3`;2=7>5;n3e3?6=3th95:4?:283>5}#::91=h94H2cg?M5>82.:5n4=d:k2<`<722c:4k4?::m2b2<722wi>l:50;494?6|,;986<kn;I1b`>N4191/=4m5299'5cc=;k20e<6j:188m4>a2900e<7?:188m4?62900e<7=:188k4`02900qo<n5;293?6=8r.9?>4>ec9K7db<@:3;7)?6c;0:?l7?m3:17d?7f;29?l7>83:17d?61;29?l7>:3:17d?63;29?j7a?3:17pl=a683>2<729q/>>=51d`8L6gc3A92<6*>9b81f>o60l0;66g>8g83>>o6190;66g>9083>>o61;0;66g>9283>>i6n>0;66sm2`194?3=83:p(?=<:0g:?M5fl2B85=5+18a962=#9oo1?o64i0:f>5<<a82m6=44i0;3>5<<a83:6=44o0d4>5<<uk8j:7>53;294~"5;:0:i:5G3`f8L6?73-;2o7<k;h3;a?6=3`;3j7>5;n3e3?6=3th9m?4?:583>5}#::91=h64H2cg?M5>82.:5n4=6:&2b`<4jj1b=5k50;9j5=`=831b=4>50;9l5c1=831vn?o7:187>5<7s-88?7?j8:J0ea=O;0:0(<7l:268 4`b2:hj7d?7e;29?l7?n3:17d?60;29?j7a?3:17pl=a883>0<729q/>>=51d;8L6gc3A92<6*>9b801>"6nl08nl5f19g94?=n91l1<75f18294?=n90;1<75`1g594?=zj;k:6=4<:183!44;3;n;6F<ae9K7<6<,83h6?;4$0df>6dd3`;3i7>5;h3;b?6=3f;m;7>5;|`006<72:0;6=u+22195`1<@:ko7E=60:&2=f<5l2c:4h4?::k2<c<722e:j:4?::a713=83>1<7>t$310>4c?3A9jh6F<919'5<e=;=1/=kk53c;8m4>b2900e<6i:188m4?72900c<h8:188yg53>3:197>50z&176<6m01C?lj4H2;3?!7>k39>7)?ie;1a=>o60l0;66g>8g83>>o6190;66g>9083>>i6n>0;66sm32c94?1=83:p(?=<:0ga?M5fl2B85=5+18a93>o60l0;66g>8g83>>o6190;66g>9083>>o61;0;66g>9283>>i6n>0;66sm25d94?1=83:p(?=<:0ga?M5fl2B85=5+18a95=g<a82n6=44i0:e>5<<a83;6=44i0;2>5<<a8396=44i0;0>5<<g8l<6=44}c0e5?6==3:1<v*=3282a<=O;hn0D>7?;%3:g?7?>2c:4h4?::k2<c<722c:5=4?::k2=4<722e:j:4?::a6c6=83=1<7>t$310>4ce3A9jh6F<919'5<e=>2c:4h4?::k2<c<722c:5=4?::k2=4<722c:5?4?::k2=6<722e:j:4?::a634=83>1<7>t$310>4>33A9jh6F<919'5<e=i2c<87>5;h;2>5<<a8lm6=44o322>5<<uk9;87>54;294~"5;:0:495G3`f8L6?73-;2o7o4i6694?=n180;66g>fg83>>i5880;66sm30a94?3=83:p(?=<:0g:?M5fl2B85=5+18a9=>o60l0;66g>8g83>>o6190;66g>9083>>i6n>0;66sm33d94?3=83:p(?=<:0g:?M5fl2B85=5+18a96`=n91o1<75f19d94?=n90:1<75f18394?=h9o=1<75rb35`>5<2290;w)<<3;3f=>N4im1C?4>4$0;`><=n91o1<75f19d94?=n90:1<75f18394?=h9o=1<75rb226>5<1290;w)<<3;3fe>N4im1C?4>4$0;`>==n91o1<75f19d94?=n90:1<75f18394?=n9081<75`1g594?=zj;no6=4<:183!44;3;n;6F<ae9K7<6<,83h6?j4i0:f>5<<a82m6=44o0d4>5<<uk88i7>53;294~"5;:0:i:5G3`f8L6?73-;2o7<k;h3;a?6=3`;3j7>5;n3e3?6=3th9hh4?:283>5}#::91=h94H2cg?M5>82.:5n4=d:k2<`<722c:4k4?::m2b2<722wi>>h50;194?6|,;986<k8;I1b`>N4191/=4m52e9j5=c=831b=5h50;9l5c1=831vn?ji:180>5<7s-88?7?j7:J0ea=O;0:0(<7l:3f8m4>b2900e<6i:188k4`02900qo<;0;297?6=8r.9?>4>e69K7db<@:3;7)?6c;0g?l7?m3:17d?7f;29?j7a?3:17pl=e183>6<729q/>>=51d58L6gc3A92<6*>9b81`>o60l0;66g>8g83>>i6n>0;66sm27:94?3=83:p(?=<:0g:?M5fl2B85=5+18a95=><a82n6=44i0:e>5<<a83;6=44i0;2>5<<g8l<6=44}c13<?6==3:1<v*=3282a<=O;hn0D>7?;%3:g?453`;3i7>5;h3;b?6=3`;2<7>5;h3:5?6=3f;m;7>5;|`121<72:0;6=u+22195`1<@:ko7E=60:&2=f<>92c:4h4?::k2<c<722e:j:4?::a635=83=1<7>t$310>4ce3A9jh6F<919'5<e=91=0e<6j:188m4>a2900e<7?:188m4?62900e<7=:188m4?42900c<h8:188yg4393:1?7>50z&176<6m>1C?lj4H2;3?!7>k38o7d?7e;29?l7?n3:17b?i7;29?xd5m80;6>4?:1y'665=9l=0D>ok;I1:4>"61j09h6g>8d83>>o60o0;66a>f683>>{e:=81<7=50;2x 75428o<7E=nd:J0=5=#90i1>i5f19g94?=n91l1<75`1g594?=zj;o96=4<:183!44;3;n;6F<ae9K7<6<,83h6?j4i0:f>5<<a82m6=44o0d4>5<<uk8??7>53;294~"5;:0:i:5G3`f8L6?73-;2o7<k;h3;a?6=3`;3j7>5;n3e3?6=3th9i>4?:283>5}#::91=h94H2cg?M5>82.:5n4=d:k2<`<722c:4k4?::m2b2<722wi>9:50;194?6|,;986<k8;I1b`>N4191/=4m52e9j5=c=831b=5h50;9l5c1=831vn?k;:180>5<7s-88?7?j7:J0ea=O;0:0(<7l:3f8m4>b2900e<6i:188k4`02900qo=;4;293?6=8r.9?>4>ec9K7db<@:3;7)?6c;3;=>o60l0;66g>8g83>>o6190;66g>9083>>o61;0;66g>9283>>i6n>0;66sm25794?5=83:p(?=<:0g4?M5fl2B85=5+18a96a=n91o1<75f19d94?=h9o=1<75rb3g6>5<4290;w)<<3;3f3>N4im1C?4>4$0;`>7b<a82n6=44i0:e>5<<g8l<6=44}c175?6=>3:1<v*=3282ad=O;hn0D>7?;%3:g?513-;mi7=m7:k2<`<722c:4k4?::k2=5<722c:5<4?::k2=7<722e:j:4?::a714=83=1<7>t$310>4ce3A9jh6F<919'5<e=;>1b=5k50;9j5=`=831b=4>50;9j5<7=831b=4<50;9j5<5=831d=k950;9~f627290>6=4?{%007?7b12B8mi5G3828 4?d2:90(<hj:2`4?l7?m3:17d?7f;29?l7>83:17d?61;29?j7a?3:17pl<3g83>1<729q/>>=51d:8L6gc3A92<6*>9b806>"6nl08no5f19g94?=n91l1<75f18294?=h9o=1<75rb21f>5<4290;w)<<3;3f3>N4im1C?4>4$0;`>7b<,8ln6>lm;h3;a?6=3`;3j7>5;n3e3?6=3th9m=4?:383>5}#::91=h<4H2cg?M5>82c:4i4?::m2b2<722wi?5h50;094?6|,;986<k=;I1b`>N4191b=5j50;9l5c1=831v9<6:184[251278;l4>fg9>72d=9ol01>9l:0de?85?13;mj63<8282bc=:;>314i5rs0d3>5<0s49jj7?i9:?037<59=16?:<520:896712>=01><6:65897112>=01?66:658yv7a93:185u23`g95=d<5:=j64?4=2:1><7<5:=m64?4=2:3><7<5:=96??l;<146?5>l278;?4<9c9>724=;0k01>9=:2;:?850:3l270=82;d4?850:3l=70=82;d6?850:3l?70=82;d0?850:3l:70=82;d3?850:3om70=82;gf?850:3oo70=82;g`?850:3oi70=82;gb?850:3o270=82;g;?850:3o=70=82;g6?850:3o?70=82;g0?850:3o970=82;g2?850:3o;70=82;fe?850:3nn70=82;fg?850:3;;<63<738eb>;4?;0mi63<738e`>;4?;0mo63<738ef>;4?;0mm63<738e6>;4?;0n;63<738gg>;4?;0:i<5236095`6<5:;j64:4=235><2<5:;<64:4=23;><2<5:;264:4=20g><2<5:8264:4=20b><2<5:8i64:4=20`><2<5;=j64:4=355><2<5;=<64:4=35;><2<5;=264:4=3:g><2<5;2264:4=3:b><2<5;2i64:4=3:`><2<5;9?6:94=317>742348o8798;<0g0?45=2wx?=:50;1xZ146349;87<?1:?040<6191v>=l:181[26i278?n4=009~w612290:9v3=648:5>;5jk0<963=bb841>;5jm0<963=bd841>;5jo0<963=c1841>;5k80<963=c3841>;5k:0<963=cb841>;5km0<963=cd841>;5ko0<963=d1841>;5l80<963=d3841>;5l:0<963<078:5>;51l0:j:5232c95<7<uz8=>7>53z\765=::?81>=?4=340>4?63ty95n4?:7y>6<e=:9;01?7j:0:e?84103;2=63<0982=4=:;>>1=4>4=3;a>4?63ty95i4?:3y]042<5;3o6?>>;|q0ac<72;qU?hh4=251>4313ty8jl4?:3y]7cg<5:=96<8>;|q740<72;qU8=;4=251>40d3ty?<i4?:3y]05b<5:=96<9;;|q74`<72;qU8=k4=251>4123ty?<k4?:3y]05`<5:=96<99;|q755<72;qU8<>4=251>4103ty?=<4?:3y]047<5:=96<97;|q757<72;qU8<<4=251>41>3ty?=>4?:3y]045<5:=96<9n;|q0b5<72;qU?k>4=251>4303ty8j<4?:3y]7c7<5:=96<;7;|q0b7<72;qU?k<4=251>43>3ty8j>4?:3y]7c5<5:=96<;n;|q0b1<72;qU?k:4=251>43e3ty8j84?:3y]7c3<5:=96<;l;|q0b3<72;qU?k84=251>43c3ty8j:4?:3y]7c1<5:=96<;j;|q0b=<72;qU?k64=251>43a3ty8j44?:3y]7c?<5:=96<8?;|q0bg<72;qU?kl4=251>4053ty8jn4?:3y]7ce<5:=96<8<;|q0ba<72;qU?kj4=251>4033ty8jh4?:3y]7cc<5:=96<8:;|q0bc<72;qU?kh4=251>4013ty?<=4?:3y]056<5:=96<88;|q744<72;qU8=?4=251>40?3ty?<?4?:3y]054<5:=96<86;|q746<72;qU8==4=251>40f3ty?<94?:3y]052<5:=96<8m;|q743<72;qU8=84=251>40c3ty?<:4?:3y]051<5:=96<8j;|q74=<72;qU8=64=251>40a3ty?<44?:3y]05?<5:=96<9?;|q74d<72;qU8=o4=251>4163ty?<n4?:3y]05e<5:=96<9<;|q03g<72<q6?>l51gd8965d28lm70=8c;;2?850j38;=63<0582bc=z{:=26=4<{<14=?479278?l4>8g9>753=90;0q~=8e;2965}::0i1=kh4=3;g>4`a3493<7<?1:?120<?l279:;47d:?11<<?l2799l47d:?11g<?l2799n47d:?11a<?l2799h47d:?11c<?l279:=47d:?124<?l279no4>fg9>6ge=0m16>oj58e9>6gc=0m16>oh58e9>6f6=0m16>n?58e9>6f4=0m16>n=58e9>6fe=0m16>nj58e9>6fc=0m16>nh58e9>6a6=0m16>i?58e9>6a4=0m16>i=58e9>634=9ol0q~=71;295a}:;181>=?4=224>=b<5::=65j4=3da>=b<5;lh65j4=3dg>=b<5;ln65j4=3de>=b<5::;65j4=222>=b<5::965j4=220>=b<5:?<65j4=27;>=b<5:?265j4=27b>=b<5:?i65j4=27`>=b<5:?o65j4=27f>=b<5:<365j4=24:>=b<5:<j65j4=24a>=b<5:<h65j4=24g>=b<5:<n65j4=24e>=b<5:=;65j4}r61a?6=>rT?>h5232f95=c<5;<36<7?;<13<?7?n2795o4>8d9>76g=91o0q~:=4;292~X3:=16>4k519g8970?282n70=?8;3:4>;4?=0:4h5228`95=`<uz9<?7>52z?037<6?m16?::51g58yv50>3:1=4u236097<><5:=96>79;<146?5>=278;?4<959>724=9>h01?89:838966020;01>;8:678963?2>?01>;6:678963f2>?01>;m:678963d2>?01>;k:678963b2>?01>87:678960>2>?01>8n:678960e2>?01>8l:678960c2>?01>8j:678960a2>?01>9?:678965c28l<7p}<c683>1c|V:i<70<6c;57?84>l3=?70=<b;57?854k3=?70=8a;57?85?j3=?70=72;57?850j3=?70=7c;57?850k3=?70=79;57?85013=?70=75;57?850n3=?70=70;57?85?>3=?70=73;57?850:3=n70=82;:7?841=3=?70<96;57?84213=?70<:a;57?842j3=?70<:c;57?842l3=?70<:e;57?842n3=?70<90;57?84193=?70<mb;57?84ek3=?70<md;57?84em3=?70<mf;57?84d83=?70<l1;57?84d:3=?70<l3;57?84dk3=?70<ld;57?84dm3=?70<lf;57?84c83=?70<k1;57?84c:3=?70<k3;57?857?3=?70=?6;57?84aj3=?70<ic;57?84al3=?70<ie;57?84an3=?70=?0;57?85793=?70=?2;57?857;3=?70=:7;57?85203=?70=:9;57?852i3=?70=:b;57?852k3=?70=:d;57?852m3=?70=98;57?85113=?70=9a;57?851j3=?70=9c;57?851l3=?70=9e;57?851n3=?70=80;57?841:3=?70=?4;57?xu5k=0;6:u2360910=::ji1>=?4=23`>4>b348<o7?7e:?17`<60o16>ik519d8964a282n7p}=c483>2}:;>819;522bf9657<5:;n6<7?;<105?7>8279;h4>919>66`=91l01?ji:0:e?xu5k?0;6:u2360912=::jo1>=?4=23f>4>b3498=7?7e:?13`<60l16>9>519d897c7282m7p}=c683>2}:;>8195522bd9657<5:8;6<7?;<107?7>82794=4>919>617=91l01?k>:0:e?xu5k10;6:u236091<=::m:1>=?4=203>4>b3498?7?7e:?1<5<60l16>9<519d897c5282m7p}=c883>2}:;>819l522e39657<5:896<7?;<101?7>82794?4>919>615=91l01?k<:0:e?xu5kh0;6:u236091g=::m81>=?4=201>4>b349897?7e:?1<7<60l16>9:519d897c3282m7p}=cc83>2}:;>819i522e19657<5:8?6<6j;<103?7?m279494>8d9>613=91l01?k::0:e?xu4?m0;6>u236d9657<5:=96??j;<140?7?n2wx?no50;0xZ6ef349<>7l8;|q0`0<72;qU?i;4=251>f4<uz9n<7>52z\0a5=:;>81oi5rs2g;>5<5sW9n463<738g1>{t;l31<7<t^2g:?850:3n=7p}<e`83>7}Y;lk01>9=:e58yv5bj3:1>vP<ec9>724=l11v>kl:181[5bk278;?4k9:p7`b=838pR>kk;<146?bf3ty8ih4?:3y]7`c<5:=96il4}r1`f?6=:rT8oo523609f==z{:ih6=4={_1`g>;4?;0i56s|3bf94?4|V:io70=82;`b?xu4kl0;6?uQ3bg896152kh0q~=lf;296~X4ko16?:<5bb9~w6b72909wS=k0:?037<el2wx?i?50;0xZ6b6349<>7lj;|q0`7<72;qU?i<4=251>g`<uz9o?7>52z\0`6=:;>81o=5rs2f7>5<5sW9o863<738`5>{t;m<1<7<t^2f5?850:3i87p}<d683>7}Y;m=01>9=:b68yv5c03:1>vP<d99>724=k<1v>j6:181[5c1278;?4l6:p7ag=838pR>jn;<146?e03ty8ho4?:3y]7ad<5:=96n64}r1gg?6=:rT8hn523609g<=z{:no6=4={_1g`>;4?;0hm6s|3eg94?4|V:nn70=82;aa?xu4lo0;6?uQ3ed896152ji0q~=j1;296~X4m816?:<5cd9~w6c52909wS=j2:?037<dn2wx?h=50;0xZ6c4349<>7j?;|q0a1<72;qU?h:4=251>a7<uz9n97>52z\0a0=:;>81h?5rs2g4>5<5sW9n;63<738g0>{t;<l1<7??{<146?5?3488h7?7e:?170<><278:54=009>6=`=90;01>?l:0;2?840k3;2=63=de82<`=:;=;1=4<4=261>4?4349?<7?7f:?07c<60o16?>k519d896>a282o70==f;3:5>;4<=0:5>5rs243>5<0s49<>7=6;<002??3349=57<?1:?1<c<60o16?<m519d8971d282m70<<e;3;a>{t;?;1<79t=251>6g<5;9<64:4=24b>766349:i7?61:?13`<61816>4?51838975a282n7p}<6383>2}:;>81?o5222:9=1=:;?h1>=?4=23f>4>a348<i7?7f:?1=4<60o16>9>519g8yv51;3:1;v3<7380g>;5;002863<6b8144=:;;:1=4?4=3:3>4?63482?7?61:?104<60l1v>8;:184850:39o70<<a;;7?851l38;=63<2182<c=::1:1=5h4=3;0>4>a348?>7?7e:p733=83=p1>9=:2g8975e20>01>8j:322?855:3;2=63=8382=4=::0?1=4?4=360>4>b3ty8:;4?:6y>724=;o16>>m5959>73`=:9;01><=:0:e?84?:3;3j63=9482<c=::=>1=5k4}r153?6=>r78;?4;1:?035<58816??:519d897>3282m70<67;3;b>;5<<0:4h5rs3cb>5<bs48in7<?1:?1<c<61916>l:519d897g2282m70<n7;3:4>;5i:0:4k522`095=`<5;k:6<6i;<12g?7>8279;n4>919>66b=91l01?jk:0:e?84f83;3h63<2g82=5=z{;ki6=46{<0ag?479279on461:?1<c<60l16>l:5182897g2283;70<n7;3:5>;5i:0:5=522`095<6<5;k:6<6j;|q1ef<721q6>oj5213897ec20;01?7>:0;3?84f<3;2=63=a482=4=::h=1=5h4=3c0>4?6348j>7?7e:p6db=83=p1?lj:322?84dm33:70<61;3;a>;5i=0:5?522`795<4<5;k<6<7=;<0b7?7?m2wx>lk50;4x97da2;::70<lf;;2?84>;3;2<63=a582<`=::h?1=4=4=3c4>4?43ty9mk4?:4y>6f6=:9;01?j?:83897?4282n70<n5;3;a>;5i>0:4h5rs3`3>5<1s48h=7<?1:?1`4<>9279584>919>6d0=91o01?o6:0;3?84f03;3j6s|2c394?3|5;i96?>>;<0g6??6348297?7e:?1e=<60l16>l7519d8yv4e:3:18v3=c28144=::m915<5228595=c<5;k26<6j;|q034<72:q6>i;5959>73>=1816?5h51g58yv53?3:1nv3=d78:0>;4=>09<<5237;9=4=::mo1=5k4=262>4?7349?>7?60:?005<61916?>h51828965b282n70==f;3;b>;4<=0:5?5rs26;>5<fs48o;77;;<16<?479278:l461:?074<61816>ih519g89626283:70=;2;3:5>;4<90:5<5232d95=c<5:>?6<7>;|q00<<720q6>i65959>70?=:9;01>8m:8389656282m70<j0;3;a>;4<80:4k5235095<4<5:>;6<6j;<170?7>82wx?9o50;:x97b>20>01>;n:322?851k33:70=<3;3:5>;5m80:4h5235395=c<5:>96<6i;<170?7?n2wx?9l50;5x97bf20>01>;m:322?851l33:70=<3;3;b>;5m;0:4h5235695=c<5:>96<6j;|q00f<721q6>il5959>70e=:9;01>8j:8389652283:70=;3;3;a>;4<?0:5=522d195=c<5:>>6<6i;|q00a<72>q6>im5959>70b=:9;01>8i:8389652282m70=;5;3;a>;5m=0:4h5235495=`<uz9?i7>55z?01`<58816?:>5909>761=91l01>:9:0:f?84b=3;3i6s|32`94?0|5:9i6?>>;<10`?7?n279:54>8g9>75>=91o01?7m:0;3?854i3;2<6s|28c94?5|5;3h64?4=3;g><7<5;3i6<h8;|q1=<<72;q6>5j51g5897?e28387p}=9983>7}::>k1=k94=3;a>4?53ty8?l4?:2y>76d=1816?>m5909>76g=9o=0q~=<9;296~;4:m0:j:5232c95<5<uz9847>52z?05d<6n>16?>o51808yv5?<3:1>v3<828:5>;4?>0:j:5rs2:4>5<4s49<j7?if:?0<5<6no16?5651g58yv5?i3:1>v3<888:5>;4?10:j:5rs2:g>5<5s493>7?if:?0<`<6n>1v>69:18185?>38;=63<8982<c=z{:2>6=4<{<1;2??6349397<?1:?032<60o1v>6<:18785?=33:70=73;035>;4?>0:4h5239:95=c<uz93o7>52z?0<f<58816?5k519d8yv5?j3:1?v3<8b8:5>;40k09<<5236:95=`<uz9357>54z?0<g<>9278444=009>72>=91o01>6j:0:f?xu4?j0;6?u236;9=4=:;>i1>=?4}r14e?6=:r78;o461:?03d<5881v>?::181856i3=<70=>9;3e3>{t;8>1<7<t=23;>4`0349:5798;|q056<72;q6?<951g58967?2>=0q~=>2;296~;49?0:j:52305932=z{:8:6=4={<12=?45=278>?4>f69~w67a2909w0=>8;011>;4:90:j:5rs23g>5<5s49:;7<=5:?05`<6n>1v>?m:181856>389963<1b82b2=z{:886=4={<12e?45=278>94>f69~w64?2909w0==d;54?855k3;m;6s|33594?4|5:8i6<h8;<11g?103ty8>;4?:3y>77g=9o=01><m:658yv55=3:1>v3<2882b2=:;;k1;:5rs217>5<5s499o7<=5:?070<6n>1v>==:181855j389963<3282b2=z{:9;6=4={<11e?45=278?<4>f69~w64b2909w0==9;011>;4:o0:j:5rs215>5<5s499h7<=5:?072<6n>1v?9::181840i3=<70<89;3e3>{t:>>1<7<t=35;>4`0348<5798;|q136<72;q6>:951g58971?2>=0q~<82;296~;5??0:j:52265932=z{;2:6=4={<04=?45=2794?4>f69~w71a2909w0<88;011>;5090:j:5rs35g>5<5s48<;7<=5:?13`<6n>1v?9m:181840>389963=7b82b2=z{;286=4={<04e?45=279494>f69~w7>?2909w0<7d;54?84?k3;m;6s|29594?4|5;2i6<h8;<0;g?103ty94;4?:3y>6=g=9o=01?6m:658yv4?=3:1>v3=8882b2=::1k1;:5rs3;7>5<5s483o7<=5:?1=0<6n>1v?7=:18184?j389963=9282b2=z{;3;6=4={<0;e?45=2795<4>f69~w7>b2909w0<79;011>;50o0:j:5rs3;5>5<5s483h7<=5:?1=2<6n>1v?:::181843m3;n?63=4482b2=z{;9h6=4={<00g?7a?2798h487:p612=839p1?=l:306?843l3;n?63=4582b2=z{;9i6=4<{<00f?7a?279?n487:?10a<0?2wx>9=50;1x975e2;8>70<;c;3f7>;5<:0:j:5rs31b>5<4s488m7?i7:?17g<0?2798n487:p614=839p1?=n:306?843j3;n?63=4382b2=z{;926=4<{<00=?7a?279?l487:?10g<0?2wx>9?50;1x975>2;8>70<;a;3f7>;5<80:j:5rs31;>5<4s48847?i7:?17<<0?2798l487:p616=839p1?=7:306?84313;n?63=4182b2=z{;9<6=4<{<003?7a?279?5487:?10<<0?2wx>>h50;1x97502;8>70<;8;3f7>;5;o0:j:5rs315>5<4s488:7?i7:?172<0?27985487:p66c=839p1?=9:306?843?3;n?63=3d82b2=z{;9>6=4<{<001?7a?279?;487:?102<0?2wx>>j50;1x975c28l<70<<5;011>;5<?0:i>5rs317>5<4s48887?i7:?170<0?2798;487:p63?=838p1?;6:838972128l<7p}=6`83>7}::<k15<5225595c1<uz8=n7>52z?11g<>9279854>f69~w70d2909w0<:c;;2?84313;m;6s|27f94?4|5;?o64?4=36b>4`03ty9:h4?:3y>60c=1816>9l51g58yv41n3:1>v3=5g8:5>;5<j0:j:5rs353>5<5s48=<77>;<07`?7a?2wx>:?50;0x970620;01?:j:0d4?xu5>>0;6?u22269=1=::?21=k94}r064?6=:r79944=009>61`=90;0q~<:1;296~;5=h09<<5225d95<5<uz8>>7>52z?11g<58816>9h519d8yv42;3:1>v3=5b8144=::?91=4>4}r060?6=:r799i4=009>632=91l0q~<:5;296~;5=l09<<5225d95<6<uz8>:7>52z?11c<58816>9h51808yv42?3:1>v3=618144=::?>1=5k4}r06<?6=:r79:<4=009>61`=91o0q~<96;296~;5>?09<<5227195=`<uz8=97>52z?120<58816>;=519g8yv4f>3:18v3=a682b2=::h<1=5h4=3c;>4?7348j57?61:p6g5=838p1?ll:83897g628l<7p}=b583>7}::kn15<522`095c1<uz8i97>52z?1f`<>9279m>4>f69~w7d12909w0<mf;;2?84f<3;m;6s|2c594?4|5;i;64?4=3c6>4`03ty9n54?:3y>6f7=1816>l851g58yv4e13:1>v3=c38:5>;5i10:j:5rs3`b>5<5s48h?77>;<0b=?7a?2wx>h;50;0x97cb28o870<j5;3e3>{t:mi1<7<t=3f`>4`0348ni798;|q1a1<72:q6>im5237897cc28o870<j4;3e3>{t:mh1<7=t=3fa>4`0348oo798;<0f`?103ty9i>4?:2y>6ad=:;?01?kl:0g0?84b;3;m;6s|2ec94?5|5;nj6<h8;<0gf?10348no798;|q1a7<72:q6>io5237897ce28o870<j2;3e3>{t:m31<7=t=3f:>4`0348om798;<0ff?103ty9i<4?:2y>6a?=:;?01?kn:0g0?84b93;m;6s|2e:94?5|5;n36<h8;<0g=?10348nm798;|q1a5<72:q6>i65237897c>28o870<j0;3e3>{t:m=1<7=t=3f4>4`0348o4798;<0f=?103ty9hk4?:2y>6a1=:;?01?k7:0g0?84cn3;m;6s|2e494?5|5;n=6<h8;<0g3?10348n4798;|q1``<72:q6>i85237897c028o870<ke;3e3>{t:m?1<7=t=3f6>4`0348o:798;<0f3?103ty9hi4?:2y>6a3=:;?01?k9:0g0?84cl3;m;6s|2e694?5|5;n?6<h8;<0g1?10348n:798;|q04=<72;q6>i:5959>75>=9o=0q~<jf;296~;5n90:j:5231795<4<uz9;57>52z?1bg<>9279i;4>f69~w66f2909w0<ic;;2?84b?3;m;6s|31`94?4|5;lo64?4=3g;>4`03ty8<n4?:3y>6cc=1816>h751g58yv57l3:1>v3=fg8:5>;5mh0:j:5rs22f>5<5s49;<77>;<0ff?7a?2wx?=h50;0x966620;01?kl:0d4?xu4990;6?u23109=4=::ln1=k94}r125?6=:r78<>461:?1a`<6n>1v?h=:18184aj38;=63=f082=5=z{;l86=4={<0eg?479279j<4>8g9~w7`32909w0<id;035>;5n80:4h5rs3d6>5<5s48mi7<?1:?1b4<6181v?h9:18184an38;=63=f182=7=z{;l<6=4={<134?479279j=4>909~w7`?2909w0=?1;035>;5n90:5=5rs3d:>5<5s49;>7<?1:?1b5<60o1v?hn:181857;38;=63=f182<`=z{::=6=4={<132?479278<84>8g9~w6602909w0=?7;035>;48<0:4h5rs260>5<3s49??7?7f:?001<6n>16?9;518289621283:7p}<4g83>7}:;<=15<5232g95c1<uz9><7>52z?01=<>9278?k4>f69~w6362909w0=:9;;2?85383;m;6s|34094?4|5:?j64?4=262>4`03ty89>4?:3y>70d=1816?9<51g58yv52<3:1>v3<5b8:5>;4<:0:j:5rs276>5<5s49>h77>;<171?7a?2wx?8850;0x963b20;01>:9:0d4?xu51o0;6>u2360911=::kh15<522`295c1<uz;m>7>52z?10c<6n>16>;=51818yv7a;3:1>v3=f082b2=::o:1=4=4}r057?6=:r79:?461:?126<6n>1v>>::181857<33:70=?5;3e3>{t9o>1<7<t=347>4`0348=?7?62:~j34?290:wE=60:m27?=83;pD>7?;|l56d<728qC?4>4}o41f?6=9rB85=5rn70`>5<6sA92<6sa63f94?7|@:3;7p`92d83>4}O;0:0qc8=f;295~N4191vb;=?:182M5>82we:>?50;0xL6?73td=??4?:3yK7<6<ug<8?7>52zJ0=5=zf?9?6=4={I1:4>{i>:?1<7<tH2;3?xh1;?0;6?uG3828yk04?3:1>vF<919~j35?2909wE=60:m26?=838pD>7?;|l57d<72;qC?4>4}o40f?6=:rB85=5rn71`>5<5sA92<6sa62f94?4|@:3;7p`93d83>7}O;0:0qc8<f;296~N4191vb;:?:181M5>82we:9?50;0xL6?73td=8?4?:3yK7<6<ug<??7>52zJ0=5=zf?>?6=4={I1:4>{i>=?1<7<tH2;3?xh1<?0;6?uG3828yk03?3:1>vF<919~j32?2909wE=60:m21?=838pD>7?;|l50d<72;qC?4>4}o47f?6=:rB85=5rn76`>5<5sA92<6sa65f94?4|@:3;7p`94d83>7}O;0:0qc8;f;296~N4191vb;;?:181M5>82we:8?50;0xL6?73td=9?4?:3yK7<6<ug<>?7>52zJ0=5=zf???6=4={I1:4>{i><?1<7?tH2;3?xh1=?0;6<uG3828yk02?3:1=vF<919~j33?290:wE=60:m20?=83;pD>7?;|l51d<728qC?4>4}o46f?6=:rB85=5rn77`>5<4sA92<6sa64f94?5|@:3;7p`95d83>7}O;0:0qc8:f;296~N4191vb;8?:181M5>82we:;?50;0xL6?73td=:?4?:3yK7<6<ug<=?7>52zJ0=5=zf?<?6=4={I1:4>{i>??1<7<tH2;3?xh1>?0;6?uG3828yk01?3:1>vF<919~j30?2909wE=60:m23?=838pD>7?;|l52d<72;qC?4>4}o45f?6=:rB85=5rn74`>5<5sA92<6sa67f94?4|@:3;7p`96d83>7}O;0:0qc89f;296~N4191vb;9?:181M5>82we::?50;0xL6?73td=;?4?:3yK7<6<ug<<?7>52zJ0=5=zf?=?6=4={I1:4>{i>>?1<7<tH2;3?xh1??0;6?uG3828yk00?3:1>vF<919~j31?2909wE=60:m22?=838pD>7?;|l53d<72;qC?4>4}o44f?6=:rB85=5rn75`>5<5sA92<6sa66f94?4|@:3;7p`97d83>7}O;0:0qc88f;296~N4191vb;6?:181M5>82we:5?50;0xL6?73td=4?4?:3yK7<6<ug<3?7>52zJ0=5=zf?2?6=4={I1:4>{i>1?1<7<tH2;3?xh10?0;6?uG3828yk0??3:1>vF<919~j3>?2909wE=60:m2=?=838pD>7?;|l5<d<72;qC?4>4}o4;f?6=:rB85=5rn7:`>5<5sA92<6sa69f94?4|@:3;7p`98d83>7}O;0:0qc87f;296~N4191vb;7?:181M5>82we:4?50;0xL6?73td=5?4?:3yK7<6<ug<2?7>52zJ0=5=zf?3?6=4>{I1:4>{i>0?1<7?tH2;3?xh11?0;6<uG3828yk0>?3:1=vF<919~j3??290:wE=60:m2<?=83;pD>7?;|l5=d<728qC?4>4}o4:f?6=9rB85=5rn7;`>5<6sA92<6sa68f94?7|@:3;7p`99d83>4}O;0:0qc86f;295~N4191vb;o?:182M5>82we:l?50;3xL6?73td=m?4?:0yK7<6<ug<j?7>51zJ0=5=zf?k?6=4>{I1:4>{i>h?1<7?tH2;3?xh1i?0;6<uG3828yk0f?3:1=vF<919~j3g?290:wE=60:m2d?=83;pD>7?;|l5ed<728qC?4>4}o4bf?6=9rB85=5rn7c`>5<6sA92<6sa6`f94?7|@:3;7p`9ad83>4}O;0:0qc8nf;295~N4191vb;l?:182M5>82we:o?50;3xL6?73td=n?4?:0yK7<6<ug<i?7>51zJ0=5=zf?h?6=4>{I1:4>{i>k?1<7?tH2;3?xh1j?0;6<uG3828yk0e?3:1=vF<919~j3d?290:wE=60:m2g?=83;pD>7?;|l5fd<728qC?4>4}o4af?6=9rB85=5rn7``>5<6sA92<6sa6cf94?7|@:3;7p`9bd83>4}O;0:0qc8mf;295~N4191vb;m?:182M5>82we:n?50;3xL6?73td=o?4?:0yK7<6<ug<h?7>51zJ0=5=zf?i?6=4>{I1:4>{i>j?1<7?tH2;3?xh1k?0;6<uG3828yk0d?3:1=vF<919~j3e?290:wE=60:m2f?=83;pD>7?;|l5gd<728qC?4>4}o4`f?6=9rB85=5rn7a`>5<6sA92<6sa6bf94?7|@:3;7p`9cd83>4}O;0:0qc8lf;295~N4191vb;j?:182M5>82we:i?50;3xL6?73td=h?4?:0yK7<6<ug<o?7>51zJ0=5=zf?n?6=4>{I1:4>{i>m?1<7?tH2;3?xh1l?0;6<uG3828yk0c?3:1=vF<919~j3b?290:wE=60:m2a?=83;pD>7?;|l5`d<728qC?4>4}o4gf?6=9rB85=5rn7f`>5<6sA92<6sa6ef94?7|@:3;7p`9dd83>4}O;0:0qc8kf;295~N4191vb;k?:182M5>82we:h?50;3xL6?73td=i?4?:0yK7<6<ug<n?7>51zJ0=5=zf?o?6=4>{I1:4>{i>l?1<7?tH2;3?xh1m?0;6<uG3828yk0b?3:1=vF<919~j3c?290:wE=60:m2`?=83;pD>7?;|l5ad<728qC?4>4}o4ff?6=9rB85=5rn7g`>5<6sA92<6sa6df94?7|@:3;7p`9ed83>4}O;0:0qc8jf;295~N4191vb;h?:182M5>82we:k?50;3xL6?73td=j?4?:0yK7<6<ug<m?7>51zJ0=5=zf?l?6=4>{I1:4>{i>o?1<7?tH2;3?xh1n?0;6<uG3828yk0a?3:1=vF<919~j3`?290:wE=60:m2c?=83;pD>7?;|l5bd<728qC?4>4}o4ef?6=9rB85=5rn7d`>5<6sA92<6sa6gf94?7|@:3;7p`9fd83>4}O;0:0qc8if;295~N4191vb:>?:182M5>82we;=?50;3xL6?73td<<?4?:0yK7<6<ug=;?7>51zJ0=5=zf>:?6=4>{I1:4>{i?9?1<7?tH2;3?xh08?0;6<uG3828yk17?3:1=vF<919~j26?290:wE=60:m35?=83;pD>7?;|l44d<728qC?4>4}o53f?6=9rB85=5rn62`>5<6sA92<6sa71f94?7|@:3;7p`80d83>4}O;0:0qc9?f;295~N4191vb:??:182M5>82we;<?50;3xL6?73td<=?4?:0yK7<6<ug=:?7>51zJ0=5=zf>;?6=4>{I1:4>{i?8?1<7?tH2;3?xh09?0;6<uG3828yk16?3:1=vF<919~j27?290:wE=60:m34?=83;pD>7?;|l45d<728qC?4>4}o52f?6=9rB85=5rn63`>5<6sA92<6sa70f94?7|@:3;7p`81d83>4}O;0:0qc9>f;295~N4191vb:<?:182M5>82we;??50;3xL6?73td<>?4?:0yK7<6<ug=9?7>51zJ0=5=zf>8?6=4>{I1:4>{i?;?1<7?tH2;3?xh0:?0;6<uG3828yk15?3:1=vF<919~j24?290:wE=60:m37?=83;pD>7?;|l46d<728qC?4>4}o51f?6=9rB85=5rn60`>5<6sA92<6sa73f94?7|@:3;7p`82d83>4}O;0:0qc9=f;295~N4191vb:=?:182M5>82we;>?50;3xL6?73td<??4?:0yK7<6<ug=8?7>51zJ0=5=zf>9?6=4>{I1:4>{i?:?1<7?tH2;3?xh0;?0;6<uG3828yk14?3:1=vF<919~j25?290:wE=60:m36?=83;pD>7?;|l47d<728qC?4>4}o50f?6=9rB85=5rn61`>5<6sA92<6sa72f94?7|@:3;7p`83d83>7}O;0:0qc9<f;295~N4191vb::?:182M5>82we;9?50;3xL6?73td<8?4?:0yK7<6<ug=??7>51zJ0=5=zf;?86=4>{I1:4>{zutJKOv691;0f=db60owKLOu?}ABSxFG
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.vhd b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.vhd
deleted file mode 100644
index fff9732..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.vhd
+++ /dev/null
@@ -1,286 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
--- You must compile the wrapper file sync_fifo_progfull504_progempty128_512x36.vhd when simulating
--- the core, sync_fifo_progfull504_progempty128_512x36. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
--- The synthesis directives "translate_off/translate_on" specified
--- below are supported by Xilinx, Mentor Graphics and Synplicity
--- synthesis tools. Ensure they are correct for your synthesis tool(s).
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
--- synthesis translate_off
-LIBRARY XilinxCoreLib;
--- synthesis translate_on
-ENTITY sync_fifo_progfull504_progempty128_512x36 IS
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC;
-    prog_full : OUT STD_LOGIC;
-    prog_empty : OUT STD_LOGIC
-  );
-END sync_fifo_progfull504_progempty128_512x36;
-
-ARCHITECTURE sync_fifo_progfull504_progempty128_512x36_a OF sync_fifo_progfull504_progempty128_512x36 IS
--- synthesis translate_off
-COMPONENT wrapped_sync_fifo_progfull504_progempty128_512x36
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC;
-    prog_full : OUT STD_LOGIC;
-    prog_empty : OUT STD_LOGIC
-  );
-END COMPONENT;
-
--- Configuration specification
-  FOR ALL : wrapped_sync_fifo_progfull504_progempty128_512x36 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
-    GENERIC MAP (
-      c_add_ngc_constraint => 0,
-      c_application_type_axis => 0,
-      c_application_type_rach => 0,
-      c_application_type_rdch => 0,
-      c_application_type_wach => 0,
-      c_application_type_wdch => 0,
-      c_application_type_wrch => 0,
-      c_axi_addr_width => 32,
-      c_axi_aruser_width => 1,
-      c_axi_awuser_width => 1,
-      c_axi_buser_width => 1,
-      c_axi_data_width => 64,
-      c_axi_id_width => 4,
-      c_axi_ruser_width => 1,
-      c_axi_type => 0,
-      c_axi_wuser_width => 1,
-      c_axis_tdata_width => 64,
-      c_axis_tdest_width => 4,
-      c_axis_tid_width => 8,
-      c_axis_tkeep_width => 4,
-      c_axis_tstrb_width => 4,
-      c_axis_tuser_width => 4,
-      c_axis_type => 0,
-      c_common_clock => 1,
-      c_count_type => 0,
-      c_data_count_width => 9,
-      c_default_value => "BlankString",
-      c_din_width => 36,
-      c_din_width_axis => 1,
-      c_din_width_rach => 32,
-      c_din_width_rdch => 64,
-      c_din_width_wach => 32,
-      c_din_width_wdch => 64,
-      c_din_width_wrch => 2,
-      c_dout_rst_val => "0",
-      c_dout_width => 36,
-      c_enable_rlocs => 0,
-      c_enable_rst_sync => 1,
-      c_error_injection_type => 0,
-      c_error_injection_type_axis => 0,
-      c_error_injection_type_rach => 0,
-      c_error_injection_type_rdch => 0,
-      c_error_injection_type_wach => 0,
-      c_error_injection_type_wdch => 0,
-      c_error_injection_type_wrch => 0,
-      c_family => "virtex6",
-      c_full_flags_rst_val => 1,
-      c_has_almost_empty => 0,
-      c_has_almost_full => 0,
-      c_has_axi_aruser => 0,
-      c_has_axi_awuser => 0,
-      c_has_axi_buser => 0,
-      c_has_axi_rd_channel => 0,
-      c_has_axi_ruser => 0,
-      c_has_axi_wr_channel => 0,
-      c_has_axi_wuser => 0,
-      c_has_axis_tdata => 0,
-      c_has_axis_tdest => 0,
-      c_has_axis_tid => 0,
-      c_has_axis_tkeep => 0,
-      c_has_axis_tlast => 0,
-      c_has_axis_tready => 1,
-      c_has_axis_tstrb => 0,
-      c_has_axis_tuser => 0,
-      c_has_backup => 0,
-      c_has_data_count => 0,
-      c_has_data_counts_axis => 0,
-      c_has_data_counts_rach => 0,
-      c_has_data_counts_rdch => 0,
-      c_has_data_counts_wach => 0,
-      c_has_data_counts_wdch => 0,
-      c_has_data_counts_wrch => 0,
-      c_has_int_clk => 0,
-      c_has_master_ce => 0,
-      c_has_meminit_file => 0,
-      c_has_overflow => 0,
-      c_has_prog_flags_axis => 0,
-      c_has_prog_flags_rach => 0,
-      c_has_prog_flags_rdch => 0,
-      c_has_prog_flags_wach => 0,
-      c_has_prog_flags_wdch => 0,
-      c_has_prog_flags_wrch => 0,
-      c_has_rd_data_count => 0,
-      c_has_rd_rst => 0,
-      c_has_rst => 1,
-      c_has_slave_ce => 0,
-      c_has_srst => 0,
-      c_has_underflow => 0,
-      c_has_valid => 0,
-      c_has_wr_ack => 0,
-      c_has_wr_data_count => 0,
-      c_has_wr_rst => 0,
-      c_implementation_type => 0,
-      c_implementation_type_axis => 1,
-      c_implementation_type_rach => 1,
-      c_implementation_type_rdch => 1,
-      c_implementation_type_wach => 1,
-      c_implementation_type_wdch => 1,
-      c_implementation_type_wrch => 1,
-      c_init_wr_pntr_val => 0,
-      c_interface_type => 0,
-      c_memory_type => 1,
-      c_mif_file_name => "BlankString",
-      c_msgon_val => 1,
-      c_optimization_mode => 0,
-      c_overflow_low => 0,
-      c_preload_latency => 1,
-      c_preload_regs => 0,
-      c_prim_fifo_type => "512x36",
-      c_prog_empty_thresh_assert_val => 128,
-      c_prog_empty_thresh_assert_val_axis => 1022,
-      c_prog_empty_thresh_assert_val_rach => 1022,
-      c_prog_empty_thresh_assert_val_rdch => 1022,
-      c_prog_empty_thresh_assert_val_wach => 1022,
-      c_prog_empty_thresh_assert_val_wdch => 1022,
-      c_prog_empty_thresh_assert_val_wrch => 1022,
-      c_prog_empty_thresh_negate_val => 129,
-      c_prog_empty_type => 1,
-      c_prog_empty_type_axis => 0,
-      c_prog_empty_type_rach => 0,
-      c_prog_empty_type_rdch => 0,
-      c_prog_empty_type_wach => 0,
-      c_prog_empty_type_wdch => 0,
-      c_prog_empty_type_wrch => 0,
-      c_prog_full_thresh_assert_val => 504,
-      c_prog_full_thresh_assert_val_axis => 1023,
-      c_prog_full_thresh_assert_val_rach => 1023,
-      c_prog_full_thresh_assert_val_rdch => 1023,
-      c_prog_full_thresh_assert_val_wach => 1023,
-      c_prog_full_thresh_assert_val_wdch => 1023,
-      c_prog_full_thresh_assert_val_wrch => 1023,
-      c_prog_full_thresh_negate_val => 503,
-      c_prog_full_type => 1,
-      c_prog_full_type_axis => 0,
-      c_prog_full_type_rach => 0,
-      c_prog_full_type_rdch => 0,
-      c_prog_full_type_wach => 0,
-      c_prog_full_type_wdch => 0,
-      c_prog_full_type_wrch => 0,
-      c_rach_type => 0,
-      c_rd_data_count_width => 9,
-      c_rd_depth => 512,
-      c_rd_freq => 1,
-      c_rd_pntr_width => 9,
-      c_rdch_type => 0,
-      c_reg_slice_mode_axis => 0,
-      c_reg_slice_mode_rach => 0,
-      c_reg_slice_mode_rdch => 0,
-      c_reg_slice_mode_wach => 0,
-      c_reg_slice_mode_wdch => 0,
-      c_reg_slice_mode_wrch => 0,
-      c_synchronizer_stage => 2,
-      c_underflow_low => 0,
-      c_use_common_overflow => 0,
-      c_use_common_underflow => 0,
-      c_use_default_settings => 0,
-      c_use_dout_rst => 1,
-      c_use_ecc => 0,
-      c_use_ecc_axis => 0,
-      c_use_ecc_rach => 0,
-      c_use_ecc_rdch => 0,
-      c_use_ecc_wach => 0,
-      c_use_ecc_wdch => 0,
-      c_use_ecc_wrch => 0,
-      c_use_embedded_reg => 0,
-      c_use_fifo16_flags => 0,
-      c_use_fwft_data_count => 0,
-      c_valid_low => 0,
-      c_wach_type => 0,
-      c_wdch_type => 0,
-      c_wr_ack_low => 0,
-      c_wr_data_count_width => 9,
-      c_wr_depth => 512,
-      c_wr_depth_axis => 1024,
-      c_wr_depth_rach => 16,
-      c_wr_depth_rdch => 1024,
-      c_wr_depth_wach => 16,
-      c_wr_depth_wdch => 1024,
-      c_wr_depth_wrch => 16,
-      c_wr_freq => 1,
-      c_wr_pntr_width => 9,
-      c_wr_pntr_width_axis => 10,
-      c_wr_pntr_width_rach => 4,
-      c_wr_pntr_width_rdch => 10,
-      c_wr_pntr_width_wach => 4,
-      c_wr_pntr_width_wdch => 10,
-      c_wr_pntr_width_wrch => 4,
-      c_wr_response_latency => 1,
-      c_wrch_type => 0
-    );
--- synthesis translate_on
-BEGIN
--- synthesis translate_off
-U0 : wrapped_sync_fifo_progfull504_progempty128_512x36
-  PORT MAP (
-    clk => clk,
-    rst => rst,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty,
-    prog_full => prog_full,
-    prog_empty => prog_empty
-  );
--- synthesis translate_on
-
-END sync_fifo_progfull504_progempty128_512x36_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.vho b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.vho
deleted file mode 100644
index 07c5e08..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.vho
+++ /dev/null
@@ -1,97 +0,0 @@
---------------------------------------------------------------------------------
---    This file is owned and controlled by Xilinx and must be used solely     --
---    for design, simulation, implementation and creation of design files     --
---    limited to Xilinx devices or technologies. Use with non-Xilinx          --
---    devices or technologies is expressly prohibited and immediately         --
---    terminates your license.                                                --
---                                                                            --
---    XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY    --
---    FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY    --
---    PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE             --
---    IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS      --
---    MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY      --
---    CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY       --
---    RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY       --
---    DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE   --
---    IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR          --
---    REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF         --
---    INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A   --
---    PARTICULAR PURPOSE.                                                     --
---                                                                            --
---    Xilinx products are not intended for use in life support appliances,    --
---    devices, or systems.  Use in such applications are expressly            --
---    prohibited.                                                             --
---                                                                            --
---    (c) Copyright 1995-2014 Xilinx, Inc.                                    --
---    All rights reserved.                                                    --
---------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------
---    Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3   --
---                                                                            --
---    Rev 1. The FIFO Generator is a parameterizable first-in/first-out       --
---    memory queue generator. Use it to generate resource and performance     --
---    optimized FIFOs with common or independent read/write clock domains,    --
---    and optional fixed or programmable full and empty flags and             --
---    handshaking signals.  Choose from a selection of memory resource        --
---    types for implementation.  Optional Hamming code based error            --
---    detection and correction as well as error injection capability for      --
---    system test help to insure data integrity.  FIFO width and depth are    --
---    parameterizable, and for native interface FIFOs, asymmetric read and    --
---    write port widths are also supported.                                   --
---------------------------------------------------------------------------------
-
--- Interfaces:
---    AXI4Stream_MASTER_M_AXIS
---    AXI4Stream_SLAVE_S_AXIS
---    AXI4_MASTER_M_AXI
---    AXI4_SLAVE_S_AXI
---    AXI4Lite_MASTER_M_AXI
---    AXI4Lite_SLAVE_S_AXI
---    master_aclk
---    slave_aclk
---    slave_aresetn
-
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-COMPONENT sync_fifo_progfull504_progempty128_512x36
-  PORT (
-    clk : IN STD_LOGIC;
-    rst : IN STD_LOGIC;
-    din : IN STD_LOGIC_VECTOR(35 DOWNTO 0);
-    wr_en : IN STD_LOGIC;
-    rd_en : IN STD_LOGIC;
-    dout : OUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    full : OUT STD_LOGIC;
-    empty : OUT STD_LOGIC;
-    prog_full : OUT STD_LOGIC;
-    prog_empty : OUT STD_LOGIC
-  );
-END COMPONENT;
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
-
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-your_instance_name : sync_fifo_progfull504_progempty128_512x36
-  PORT MAP (
-    clk => clk,
-    rst => rst,
-    din => din,
-    wr_en => wr_en,
-    rd_en => rd_en,
-    dout => dout,
-    full => full,
-    empty => empty,
-    prog_full => prog_full,
-    prog_empty => prog_empty
-  );
--- INST_TAG_END ------ End INSTANTIATION Template ------------
-
--- You must compile the wrapper file sync_fifo_progfull504_progempty128_512x36.vhd when simulating
--- the core, sync_fifo_progfull504_progempty128_512x36. When compiling the wrapper file, be sure to
--- reference the XilinxCoreLib VHDL simulation library. For detailed
--- instructions, please refer to the "CORE Generator Help".
-
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.xco b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.xco
deleted file mode 100644
index 03fbb3e..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.xco
+++ /dev/null
@@ -1,213 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.7
-# Date: Mon Oct 20 06:51:31 2014
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:fifo_generator:9.3
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
-# END Select
-# BEGIN Parameters
-CSET add_ngc_constraint_axi=false
-CSET almost_empty_flag=false
-CSET almost_full_flag=false
-CSET aruser_width=1
-CSET awuser_width=1
-CSET axi_address_width=32
-CSET axi_data_width=64
-CSET axi_type=AXI4_Stream
-CSET axis_type=FIFO
-CSET buser_width=1
-CSET clock_enable_type=Slave_Interface_Clock_Enable
-CSET clock_type_axi=Common_Clock
-CSET component_name=sync_fifo_progfull504_progempty128_512x36
-CSET data_count=false
-CSET data_count_width=9
-CSET disable_timing_violations=false
-CSET disable_timing_violations_axi=false
-CSET dout_reset_value=0
-CSET empty_threshold_assert_value=128
-CSET empty_threshold_assert_value_axis=1022
-CSET empty_threshold_assert_value_rach=1022
-CSET empty_threshold_assert_value_rdch=1022
-CSET empty_threshold_assert_value_wach=1022
-CSET empty_threshold_assert_value_wdch=1022
-CSET empty_threshold_assert_value_wrch=1022
-CSET empty_threshold_negate_value=129
-CSET enable_aruser=false
-CSET enable_awuser=false
-CSET enable_buser=false
-CSET enable_common_overflow=false
-CSET enable_common_underflow=false
-CSET enable_data_counts_axis=false
-CSET enable_data_counts_rach=false
-CSET enable_data_counts_rdch=false
-CSET enable_data_counts_wach=false
-CSET enable_data_counts_wdch=false
-CSET enable_data_counts_wrch=false
-CSET enable_ecc=false
-CSET enable_ecc_axis=false
-CSET enable_ecc_rach=false
-CSET enable_ecc_rdch=false
-CSET enable_ecc_wach=false
-CSET enable_ecc_wdch=false
-CSET enable_ecc_wrch=false
-CSET enable_read_channel=false
-CSET enable_read_pointer_increment_by2=false
-CSET enable_reset_synchronization=true
-CSET enable_ruser=false
-CSET enable_tdata=false
-CSET enable_tdest=false
-CSET enable_tid=false
-CSET enable_tkeep=false
-CSET enable_tlast=false
-CSET enable_tready=true
-CSET enable_tstrobe=false
-CSET enable_tuser=false
-CSET enable_write_channel=false
-CSET enable_wuser=false
-CSET fifo_application_type_axis=Data_FIFO
-CSET fifo_application_type_rach=Data_FIFO
-CSET fifo_application_type_rdch=Data_FIFO
-CSET fifo_application_type_wach=Data_FIFO
-CSET fifo_application_type_wdch=Data_FIFO
-CSET fifo_application_type_wrch=Data_FIFO
-CSET fifo_implementation=Common_Clock_Block_RAM
-CSET fifo_implementation_axis=Common_Clock_Block_RAM
-CSET fifo_implementation_rach=Common_Clock_Block_RAM
-CSET fifo_implementation_rdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wach=Common_Clock_Block_RAM
-CSET fifo_implementation_wdch=Common_Clock_Block_RAM
-CSET fifo_implementation_wrch=Common_Clock_Block_RAM
-CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=504
-CSET full_threshold_assert_value_axis=1023
-CSET full_threshold_assert_value_rach=1023
-CSET full_threshold_assert_value_rdch=1023
-CSET full_threshold_assert_value_wach=1023
-CSET full_threshold_assert_value_wdch=1023
-CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=503
-CSET id_width=4
-CSET inject_dbit_error=false
-CSET inject_dbit_error_axis=false
-CSET inject_dbit_error_rach=false
-CSET inject_dbit_error_rdch=false
-CSET inject_dbit_error_wach=false
-CSET inject_dbit_error_wdch=false
-CSET inject_dbit_error_wrch=false
-CSET inject_sbit_error=false
-CSET inject_sbit_error_axis=false
-CSET inject_sbit_error_rach=false
-CSET inject_sbit_error_rdch=false
-CSET inject_sbit_error_wach=false
-CSET inject_sbit_error_wdch=false
-CSET inject_sbit_error_wrch=false
-CSET input_data_width=36
-CSET input_depth=512
-CSET input_depth_axis=1024
-CSET input_depth_rach=16
-CSET input_depth_rdch=1024
-CSET input_depth_wach=16
-CSET input_depth_wdch=1024
-CSET input_depth_wrch=16
-CSET interface_type=Native
-CSET output_data_width=36
-CSET output_depth=512
-CSET overflow_flag=false
-CSET overflow_flag_axi=false
-CSET overflow_sense=Active_High
-CSET overflow_sense_axi=Active_High
-CSET performance_options=Standard_FIFO
-CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant
-CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
-CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
-CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
-CSET programmable_full_type_axis=No_Programmable_Full_Threshold
-CSET programmable_full_type_rach=No_Programmable_Full_Threshold
-CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wach=No_Programmable_Full_Threshold
-CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
-CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
-CSET rach_type=FIFO
-CSET rdch_type=FIFO
-CSET read_clock_frequency=1
-CSET read_data_count=false
-CSET read_data_count_width=9
-CSET register_slice_mode_axis=Fully_Registered
-CSET register_slice_mode_rach=Fully_Registered
-CSET register_slice_mode_rdch=Fully_Registered
-CSET register_slice_mode_wach=Fully_Registered
-CSET register_slice_mode_wdch=Fully_Registered
-CSET register_slice_mode_wrch=Fully_Registered
-CSET reset_pin=true
-CSET reset_type=Asynchronous_Reset
-CSET ruser_width=1
-CSET synchronization_stages=2
-CSET synchronization_stages_axi=2
-CSET tdata_width=64
-CSET tdest_width=4
-CSET tid_width=8
-CSET tkeep_width=4
-CSET tstrb_width=4
-CSET tuser_width=4
-CSET underflow_flag=false
-CSET underflow_flag_axi=false
-CSET underflow_sense=Active_High
-CSET underflow_sense_axi=Active_High
-CSET use_clock_enable=false
-CSET use_dout_reset=true
-CSET use_embedded_registers=false
-CSET use_extra_logic=false
-CSET valid_flag=false
-CSET valid_sense=Active_High
-CSET wach_type=FIFO
-CSET wdch_type=FIFO
-CSET wrch_type=FIFO
-CSET write_acknowledge_flag=false
-CSET write_acknowledge_sense=Active_High
-CSET write_clock_frequency=1
-CSET write_data_count=false
-CSET write_data_count_width=9
-CSET wuser_width=1
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-11-19T12:39:56Z
-# END Extra information
-GENERATE
-# CRC: d742ac77
diff --git a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.xise b/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.xise
deleted file mode 100644
index 49494a7..0000000
--- a/FEE_ADC32board/project/ipcore_dir/sync_fifo_progfull504_progempty128_512x36.xise
+++ /dev/null
@@ -1,74 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="sync_fifo_progfull504_progempty128_512x36.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="sync_fifo_progfull504_progempty128_512x36.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|sync_fifo_progfull504_progempty128_512x36|sync_fifo_progfull504_progempty128_512x36_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="sync_fifo_progfull504_progempty128_512x36.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/sync_fifo_progfull504_progempty128_512x36" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="sync_fifo_progfull504_progempty128_512x36" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-10-20T08:53:22" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="D6BFA174C8A142E88A2B18FFED2A90B4" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/vio36.asy b/FEE_ADC32board/project/ipcore_dir/vio36.asy
deleted file mode 100644
index 57bf4b1..0000000
--- a/FEE_ADC32board/project/ipcore_dir/vio36.asy
+++ /dev/null
@@ -1,13 +0,0 @@
-Version 4
-SymbolType BLOCK
-TEXT 32 32 LEFT 4 vio36
-RECTANGLE Normal 32 32 320 224
-LINE Wide 0 80 32 80
-PIN 0 80 LEFT 36
-PINATTR PinName control[35:0]
-PINATTR Polarity BOTH
-LINE Wide 352 80 320 80
-PIN 352 80 RIGHT 36
-PINATTR PinName async_out[35:0]
-PINATTR Polarity OUT
-
diff --git a/FEE_ADC32board/project/ipcore_dir/vio36.gise b/FEE_ADC32board/project/ipcore_dir/vio36.gise
deleted file mode 100644
index fa94172..0000000
--- a/FEE_ADC32board/project/ipcore_dir/vio36.gise
+++ /dev/null
@@ -1,53 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <!--                                                          -->
-
-  <!--             For tool use only. Do not edit.              -->
-
-  <!--                                                          -->
-
-  <!-- ProjectNavigator created generated project file.         -->
-
-  <!-- For use in tracking generated file and other information -->
-
-  <!-- allowing preservation of process status.                 -->
-
-  <!--                                                          -->
-
-  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
-  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
-
-  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="vio36.xise"/>
-
-  <files xmlns="http://www.xilinx.com/XMLSchema">
-    <file xil_pn:fileType="FILE_ASY" xil_pn:name="vio36.asy" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="vio36.sym" xil_pn:origination="imported"/>
-    <file xil_pn:fileType="FILE_VHO" xil_pn:name="vio36.vho" xil_pn:origination="imported"/>
-  </files>
-
-  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1343053211" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1343053211">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-5742197664057771698" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="353548448524534222" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-    <transform xil_pn:end_ts="1383914820" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6993779039607739646" xil_pn:start_ts="1383914820">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-    </transform>
-  </transforms>
-
-</generated_project>
diff --git a/FEE_ADC32board/project/ipcore_dir/vio36.ngc b/FEE_ADC32board/project/ipcore_dir/vio36.ngc
deleted file mode 100644
index ef881d8..0000000
--- a/FEE_ADC32board/project/ipcore_dir/vio36.ngc
+++ /dev/null
@@ -1,3 +0,0 @@
-XILINX-XDB 0.1 STUB 0.1 ASCII
-XILINX-XDM V1.6e
-$30b40<,[o}e~g`n;"2*731&=$:,)<4-03841=789:?7=>?2593557339<:<<5=4:0245713:<1ECAZT;ALJQTHD59>6=0>9:15>JSSX\^1M^WAC^MVP952294?79>?0g95ri~6;9~mj96;-2683C@A991<JKHIFGDEBC@ANOL37LHNC@1B4f=F[PDHSB[[<1<g?DU^FJUDYY2>0?f8EV_IKVE^X1?>>e9BW\HDWF__0<<1d:CP]KEXG\^7=>0k;@QZJFYH]]6:83j4AR[MGZIR\5;>2i5NSXL@[JSS48<5h6O\YOA\KPR;9>4o7L]VNB]LQQ:607n0M^WAC^MVP97>6j1J_T@L_NWW848c3HYRBNQ@UU>14;b<IZSEORAZT=02:a=F[PDHSB[[<30=`>GTQGITCXZ322<g?DU^FJUDYY2=4?f8EV_IKVE^X1<:>e9BW\HDWF__0?81d:CP]KEXG\^7>:0k;@QZJFYH]]6943j4AR[MGZIR\5822n5NSXL@[JSS4;4o7L]VNB]LQQ:487n0M^WAC^MVP9566m1J_T@L_NWW8649l2KXUCMPOTV?768c3HYRBNQ@UU>00;`<IZSEORAZT=16>58c3HYRBNQ@UU>01;e<IZSEORAZT=1=g>GTQGITCXZ34?a8EV_IKVE^X1;1c:CP]KEXG\^7:3m4AR[MGZIR\5=5o6O\YOA\KPR;07i0M^WAC^MVP9?902H^_RGAFN38G7=DI;1HI<<4CIG@OZJNKLDXIRZVPD08GL2<KEA;:6MCK0:32>EKC;=;96MCK3Z;?FJL:Q;3<85LLJ;31>EKCH;<7NBDA0F13>EKCH;O8:5LLJC2@=3<KEAI=85LLJA21>EKCM;>7NBDDWa8GIMC^VNBZDJJ5:AOOC^?3JF@JU?7089@KHKN\]OOm6M@NUPLH969j2IDBY\@L=33:g=DGG^YCA2>1?`8GJHSZFF7=?0m;BMMPWIK4895n6M@NUPLH9736k1HCCZ]OM>21;d<KFD_^BB317<a?FII\[EG0<91b:ALJQTHD5;32o5LOOVQKI:617k0OB@[RNN?5;d<KFD_^BB321<a?FII\[EG0??1b:ALJQTHD5892o5LOOVQKI:5;7h0OB@[RNN?618e3JEEX_AC<37=f>EHF]XD@1<9>c9@KKRUGE69;3l4CNLWVJJ;:14i7NAATSMO87?9i2IDBY\@L=0=f>EHF]XD@1=?>c9@KKRUGE68=3l4CNLWVJJ;;;4i7NAATSMO8659j2IDBY\@L=17:a=DGG^YCA2<5;2=f>EHF]XD@1=:>`9@KKRUGE682l5LOOVQKI:36h1HCCZ]OM>6:d=DGG^YCA29>`9@KKRUGE6<2l5LOOVQKI:?6h1HCCZ]OM>::42<KFXNSJKAESCWMJHXAGLD;6M]E@VF@4=C<2N8<4<4DH78@ZEKC8:0JI9:B812AF03I18;?6HKE29E@W2<NMXN==5IFGDEBC@ANOLMJKK7;GPLIZHDN81L?6IAD09J6>O7:2C:>6G=2:K06>O3:2C>56GAIUQWEQC43@D]>6BF2:NL2>JHIMOO:6B@CJGG3>JHO@IJ@95CUU37?ISS;=1GYY:;;MWW11=K]]<<7@[WCX]Og>Kfbfx]i}fooa8Ilhhz_oydaa2:L36>H6?2DNXZA]K09L<>I)??roSA?4P59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ6:RP@JHB92[:7_?4S038WMTBOVOSX_OLT^LDG`=T@[OLS@GA_RKYA3=TG\XHI;5\T@VVW2=SFDUEIY:4TXRF57=R8&CTZDA D@VB[AIR\:80Y=!F_WKL+BCIWHYRBNQ@UUY3Y+GTQGITCXZPCDNO+VNNN]UYIJ=>;T2,MZPNG&MNBRO\YOA\KPR\8T$J_T@L_NWW[FCKD&_XI_Q]EF10?P6(AV\BC"IJN^CP]KEXG\^P==S!AR[MGZIR\VIN@A!\HHDW[WC@;;1^<"GPVHM,C@HXIZSEORAZTZ33Y+GTQGITCXZPCDNO+PUBZVXNK>=4U1-J[SOH'NOESL]VNB]LQQ]69T$J_T@L_NWW[FCKD&YCEKZPRDE06>S7'@U]EB!HEO]BW\HDWF__W<?R.@QZJFYH]]UHIAB URGQ[WC@;:1^<"GPVHM,C@HXIZSEORAZTZ31Y+GTQGITCXZPCDNO+VNNN]UYIJ==;T2,MZPNG&MNBRO\YOA\KPR\9;W%M^WAC^MVPZEBDE%^_H\PRDE07>S7'@U]EB!HEO]BW\HDWF__W<=R.@QZJFYH]]UHIAB SIKEPZTBO:80Y=!F_WKL+BCIWHYRBNQ@UUY27X(F[PDHSB[[_BGOH*STM[UYIJ=<;T2,MZPNG&MNBRO\YOA\KPR\9=W%M^WAC^MVPZEBDE%XDDH[_SGD77=R8&CTZDA GDL\EV_IKVE^XV?;]/CP]KEXG\^TOHBC/TQFVZTBO:90Y=!F_WKL+BCIWHYRBNQ@UUY21X(F[PDHSB[[_BGOH*UOAO^T^HI<2:W3+LYQAF%LICQNSXL@[JSSS8?V"L]VNB]LQQYDMEF$Y^K]_SGD76=R8&CTZDA GDL\EV_IKVE^XV?9]/CP]KEXG\^TOHBC/RJJBQYUMN997X> I^TJK*ABFVKXUCMPOTVX53[)IZSEORAZT^AFHI)R[LXT^HI<3:W3+LYQAF%LICQNSXL@[JSSS8=V"L]VNB]LQQYDMEF$_EGIT^PFC64<]9%BS[G@/FGM[DU^FJUDYYU>7\,BW\HDWF__SNKCL.WPAWYUMN987X> I^TJK*ABFVKXUCMPOTVX5=[)IZSEORAZT^AFHI)T@@L_S_KH339V4*OX^@E$KH@PAR[MGZIR\R;3Q#O\YOA\KPRXKLFG#X]JR^PFC65<]9%BS[G@/FGM[DU^FJUDYYU>9\,BW\HDWF__SNKCL.QKMCRXZLM8>6[?/H]UMJ)@MGUJ_T@L_NWW_4?Z&HYRBNQ@UU]@AIJ(]ZOYS_KH339V4*OX^@E$KH@PAR[MGZIR\R;V"L]VNB]LQQYDMEF$_EGIT^PFC67<]9%BS[G@/FGM[DU^FJUDYYU>]/CP]KEXG\^TOHBC/TQFVZTBO:90Y=!F_WKL+BCIWHYRBNQ@UUY14X(F[PDHSB[[_BGOH*UOAO^T^HI<2:W3+LYQAF%LICQNSXL@[JSSS;:V"L]VNB]LQQYDMEF$Y^K]_SGD76=R8&CTZDA GDL\EV_IKVE^XV<>]/CP]KEXG\^TOHBC/RJJBQYUMN997X> I^TJK*ABFVKXUCMPOTVX64[)IZSEORAZT^AFHI)R[LXT^HI<3:W3+LYQAF%LICQNSXL@[JSSS;8V"L]VNB]LQQYDMEF$_EGIT^PFC64<]9%BS[G@/FGM[DU^FJUDYYU=2\,BW\HDWF__SNKCL.WPAWYUMN987X> I^TJK*ABFVKXUCMPOTVX66[)IZSEORAZT^AFHI)T@@L_S_KH339V4*OX^@E$KH@PAR[MGZIR\R88Q#O\YOA\KPRXKLFG#X]JR^PFC65<]9%BS[G@/FGM[DU^FJUDYYU=4\,BW\HDWF__SNKCL.QKMCRXZLM8>6[?/H]UMJ)@MGUJ_T@L_NWW_72Z&HYRBNQ@UU]@AIJ(]ZOYS_KH329V4*OX^@E$KH@PAR[MGZIR\R8>Q#O\YOA\KPRXKLFG#^FFFU]QAB553\:$ERXFO.EFJZGTQGITCXZT24_-EV_IKVE^XRMJLM-VW@TXZLM8?6[?/H]UMJ)@MGUJ_T@L_NWW_70Z&HYRBNQ@UU]@AIJ([ACMXR\JG208Q5)NW_CD#JKA_@QZJFYH]]Q9:P NSXL@[JSSWJOG@"[\ES]QAB543\:$ERXFO.EFJZGTQGITCXZT26_-EV_IKVE^XRMJLM-PLL@SW[OL??5Z0.K\RLI(OLDTM^WAC^MVP^40U'KXUCMPOTV\G@JK'\YN^R\JG218Q5)NW_CD#JKA_@QZJFYH]]Q94P NSXL@[JSSWJOG@"]GIGV\V@A4:2_;#DQYIN-DAKYF[PDHSB[[[3:^*DU^FJUDYYQLEMN,QVCUW[OL?>5Z0.K\RLI(OLDTM^WAC^MVP^4>U'KXUCMPOTV\G@JK'ZBBJYQ]EF11?P6(AV\BC"IJN^CP]KEXG\^P>4S!AR[MGZIR\VIN@A!ZSDP\V@A4:2_;#DQYIN-DAKYF[PDHSB[[[3_-EV_IKVE^XRMJLM-PLL@SW[OL?<5Z0.K\RLI(OLDTM^WAC^MVP^4Z&HYRBNQ@UU]@AIJ(]ZOYS_KH329V4*OX^@E$KH@PAR[MGZIR\R9;Q#O\YOA\KPRXKLFG#^FFFU]QAB553\:$ERXFO.EFJZGTQGITCXZT31_-EV_IKVE^XRMJLM-VW@TXZLM8?6[?/H]UMJ)@MGUJ_T@L_NWW_67Z&HYRBNQ@UU]@AIJ([ACMXR\JG208Q5)NW_CD#JKA_@QZJFYH]]Q8=P NSXL@[JSSWJOG@"[\ES]QAB543\:$ERXFO.EFJZGTQGITCXZT33_-EV_IKVE^XRMJLM-PLL@SW[OL??5Z0.K\RLI(OLDTM^WAC^MVP^55U'KXUCMPOTV\G@JK'\YN^R\JG218Q5)NW_CD#JKA_@QZJFYH]]Q8?P NSXL@[JSSWJOG@"]GIGV\V@A4:2_;#DQYIN-DAKYF[PDHSB[[[21^*DU^FJUDYYQLEMN,QVCUW[OL?>5Z0.K\RLI(OLDTM^WAC^MVP^53U'KXUCMPOTV\G@JK'ZBBJYQ]EF11?P6(AV\BC"IJN^CP]KEXG\^P?9S!AR[MGZIR\VIN@A!ZSDP\V@A4;2_;#DQYIN-DAKYF[PDHSB[[[27^*DU^FJUDYYQLEMN,WMOA\VXNK><4U1-J[SOH'NOESL]VNB]LQQ]4=T$J_T@L_NWW[FCKD&_XI_Q]EF11?P6(AV\BC"IJN^CP]KEXG\^P?P NSXL@[JSSWJOG@"]GIGV\V@A492_;#DQYIN-DAKYF[PDHSB[[[2_-EV_IKVE^XRMJLM-VW@TXZLM8>6[?/H]UMJ)@MGUJ_T@L_NWW_1[)IZSEORAZT^AFHI)T@@L_S_KH309V4*OX^@E$KH@PAR[MGZIR\R>V"L]VNB]LQQYDMEF$Y^K]_SGD77=R8&CTZDA GDL\EV_IKVE^XV;R.@QZJFYH]]UHIAB SIKEPZTBO:;0Y=!F_WKL+BCIWHYRBNQ@UUY6Y+GTQGITCXZPCDNO+PUBZVXNK><4U1-J[SOH'NOESL]VNB]LQQ]1U'KXUCMPOTV\G@JK'ZBBJYQ]EF12?P6(AV\BC"IJN^CP]KEXG\^P:P NSXL@[JSSWJOG@"[\ES]QAB553\:$ERXFO.EFJZGTQGITCXZT7\,BW\HDWF__SNKCL.QKMCRXZLM8=6[?/H]UMJ)@MGUJ_T@L_NWW_2[)IZSEORAZT^AFHI)R[LXT^HI<2:W3+LYQAF%LICQNSXL@[JSSS1W%M^WAC^MVPZEBDE%XDDH[_SGD74=R8&CTZDA GDL\EV_IKVE^XV6R.@QZJFYH]]UHIAB URGQ[WC@;;1^<"GPVHM,C@HXIZSEORAZTZ;^*DU^FJUDYYQLEMN,WMOA\VXNK>?4U1-J[SOH'NOESL]VNB]LQQ]>U'KXUCMPOTV\G@JK'\YN^R\JG2`8Q5)NW_CD#JKA_TRGEQCXG\^P?;S!UQFBP@YDMEF$KH@PNN]@HN(R[LXT^HI<1:W3+LYQAF%LICQZPECWAZIR\R9=Q#[_D@VF[FCKD&YCEKZPRDE0f>S7'@U]EB!HEO]VTAGSMVE^XV=8]/WS@DRBWJOG@"IJN^LL[FJL&\YN^R\JG238Q5)NW_CD#JKA_TRGEQCXG\^P?:S!UQFBP@YDMEF$_EGIT^PFC6d<]9%BS[G@/FGM[PVCI]OTCXZT39_-QUBF\LUHIAB GDL\JJYDDB$^_H\PRDE05>S7'@U]EB!HEO]VTAGSMVE^XV=7]/WS@DRBWJOG@"]GIGV\V@A4j2_;#DQYIN-DAKYRXMK_IRAZTZ1:Y+SWLH^NSNKCL.EFJZHHWJF@"X]JR^PFC67<]9%BS[G@/FGM[PVCI]OTCXZT38_-QUBF\LUHIAB SIKEPZTBO:h0Y=!F_WKL+BCIW\ZOMYKPOTVX05[)]YNJXHQLEMN,C@HXFFUH@F ZSDP\V@A492_;#DQYIN-DAKYRXMK_IRAZTZ63Y+SWLH^NSNKCL.QKMCRXZLM8n6[?/H]UMJ)@MGU^\IO[E^MVP^26U'_[HLZJ_BGOH*ABFVDDSNBD.TQFVZTBO:;0Y=!F_WKL+BCIW\ZOMYKPOTVX04[)]YNJXHQLEMN,WMOA\VXNK>l4U1-J[SOH'NOESX^KAUG\KPR\<;W%Y]JNTD]@AIJ(OLDTBBQLLJ,VW@TXZLM8=6[?/H]UMJ)@MGU^\IO[E^MVP^25U'_[HLZJ_BGOH*UOAO^T^HI<b:W3+LYQAF%LICQZPECWAZIR\R>8Q#[_D@VF[FCKD&MNBR@@_BNH*PUBZVXNK>?4U1-J[SOH'NOESX^KAUG\KPR\<:W%Y]JNTD]@AIJ([ACMXR\JG2`8Q5)NW_CD#JKA_TRGEQCXG\^P89S!UQFBP@YDMEF$KH@PNN]@HN(R[LXT^HI<1:W3+LYQAF%LICQZPECWAZIR\R>?Q#[_D@VF[FCKD&YCEKZPRDE0f>S7'@U]EB!HEO]VTAGSMVE^XV::]/WS@DRBWJOG@"IJN^LL[FJL&\YN^R\JG238Q5)NW_CD#JKA_TRGEQCXG\^P88S!UQFBP@YDMEF$_EGIT^PFC6d<]9%BS[G@/FGM[PVCI]OTCXZT47_-QUBF\LUHIAB GDL\JJYDDB$^_H\PRDE05>S7'@U]EB!HEO]VTAGSMVE^XV:9]/WS@DRBWJOG@"]GIGV\V@A4j2_;#DQYIN-DAKYRXMK_IRAZTZ64Y+SWLH^NSNKCL.EFJZHHWJF@"X]JR^PFC67<]9%BS[G@/FGM[PVCI]OTCXZT46_-QUBF\LUHIAB SIKEPZTBO:h0Y=!F_WKL+BCIW\ZOMYKPOTVX0=[)]YNJXHQLEMN,C@HXFFUH@F ZSDP\V@A492_;#DQYIN-DAKYRXMK_IRAZTZ6;Y+SWLH^NSNKCL.QKMCRXZLM8n6[?/H]UMJ)@MGU^\IO[E^MVP^2>U'_[HLZJ_BGOH*ABFVDDSNBD.TQFVZTBO:;0Y=!F_WKL+BCIW\ZOMYKPOTVX0<[)]YNJXHQLEMN,WMOA\VXNK>l4U1-J[SOH'NOESX^KAUG\KPR\=9W%Y]JNTD]@AIJ(OLDTBBQLLJ,VW@TXZLM8=6[?/H]UMJ)@MGU^\IO[E^MVP^37U'_[HLZJ_BGOH*UOAO^T^HI<b:W3+LYQAF%LICQZPECWAZIR\R?:Q#[_D@VF[FCKD&MNBR@@_BNH*PUBZVXNK>?4U1-J[SOH'NOESX^KAUG\KPR\=8W%Y]JNTD]@AIJ([ACMXR\JG2`8Q5)NW_CD#JKA_TRGEQCXG\^P9?S!UQFBP@YDMEF$KH@PNN]@HN(R[LXT^HI<1:W3+LYQAF%LICQZPECWAZIR\R?9Q#[_D@VF[FCKD&YCEKZPRDE0f>S7'@U]EB!HEO]VTAGSMVE^XV;<]/WS@DRBWJOG@"IJN^LL[FJL&\YN^R\JG238Q5)NW_CD#JKA_TRGEQCXG\^P9>S!UQFBP@YDMEF$_EGIT^PFC6d<]9%BS[G@/FGM[PVCI]OTCXZT55_-QUBF\LUHIAB GDL\JJYDDB$^_H\PRDE05>S7'@U]EB!HEO]VTAGSMVE^XV;;]/WS@DRBWJOG@"]GIGV\V@A4j2_;#DQYIN-DAKYRXMK_IRAZTZ76Y+SWLH^NSNKCL.EFJZHHWJF@"X]JR^PFC67<]9%BS[G@/FGM[PVCI]OTCXZT54_-QUBF\LUHIAB SIKEPZTBO:h0Y=!F_WKL+BCIW\ZOMYKPOTVX13[)]YNJXHQLEMN,C@HXFFUH@F ZSDP\V@A492_;#DQYIN-DAKYRXMK_IRAZTZ75Y+SWLH^NSNKCL.QKMCRXZLM8n6[?/H]UMJ)@MGU^\IO[E^MVP^30U'_[HLZJ_BGOH*ABFVDDSNBD.TQFVZTBO:;0Y=!F_WKL+BCIW\ZOMYKPOTVX12[)]YNJXHQLEMN,WMOA\VXNK>l4U1-J[SOH'NOESX^KAUG\KPR\=1W%Y]JNTD]@AIJ(OLDTBBQLLJ,VW@TXZLM8=6[?/H]UMJ)@MGU^\IO[E^MVP^3?U'_[HLZJ_BGOH*UOAO^T^HI<b:W3+LYQAF%LICQZPECWAZIR\R?2Q#[_D@VF[FCKD&MNBR@@_BNH*PUBZVXNK>?4U1-J[SOH'NOESX^KAUG\KPR\=0W%Y]JNTD]@AIJ([ACMXR\JG2`8Q5)NW_CD#JKA_TRGEQCXG\^P:=S!UQFBP@YDMEF$KH@PNN]@HN(R[LXT^HI<1:W3+LYQAF%LICQZPECWAZIR\R<;Q#[_D@VF[FCKD&YCEKZPRDE0f>S7'@U]EB!HEO]VTAGSMVE^XV8>]/WS@DRBWJOG@"IJN^LL[FJL&\YN^R\JG238Q5)NW_CD#JKA_TRGEQCXG\^P:<S!UQFBP@YDMEF$_EGIT^PFC6d<]9%BS[G@/FGM[PVCI]OTCXZT63_-QUBF\LUHIAB GDL\JJYDDB$^_H\PRDE05>S7'@U]EB!HEO]VTAGSMVE^XV8=]/WS@DRBWJOG@"]GIGV\V@A4j2_;#DQYIN-DAKYRXMK_IRAZTZ40Y+SWLH^NSNKCL.EFJZHHWJF@"X]JR^PFC67<]9%BS[G@/FGM[PVCI]OTCXZT62_-QUBF\LUHIAB SIKEPZTBO:h0Y=!F_WKL+BCIW\ZOMYKPOTVX21[)]YNJXHQLEMN,C@HXFFUH@F ZSDP\V@A492_;#DQYIN-DAKYRXMK_IRAZTZ47Y+SWLH^NSNKCL.QKMCRXZLM8n6[?/H]UMJ)@MGU^\IO[E^MVP^02U'_[HLZJ_BGOH*ABFVDDSNBD.TQFVZTBO:;0Y=!F_WKL+BCIW\ZOMYKPOTVX20[)]YNJXHQLEMN,WMOA\VXNK>l4U1-J[SOH'NOESX^KAUG\KPR\>?W%Y]JNTD]@AIJ(OLDTBBQLLJ,VW@TXZLM8=6[?/H]UMJ)@MGU^\IO[E^MVP^01U'_[HLZJ_BGOH*UOAO^T^HI<b:W3+LYQAF%LICQZPECWAZIR\R<<Q#[_D@VF[FCKD&MNBR@@_BNH*PUBZVXNK>?4U1-J[SOH'NOESX^KAUG\KPR\>>W%Y]JNTD]@AIJ([ACMXR\JG2`8Q5)NW_CD#JKA_TRGEQCXG\^P:5S!UQFBP@YDMEF$KH@PNN]@HN(R[LXT^HI<1:W3+LYQAF%LICQZPECWAZIR\R<3Q#[_D@VF[FCKD&YCEKZPRDE0f>S7'@U]EB!HEO]VTAGSMVE^XV86]/WS@DRBWJOG@"IJN^LL[FJL&\YN^R\JG238Q5)NW_CD#JKA_TRGEQCXG\^P:4S!UQFBP@YDMEF$_EGIT^PFC6d<]9%BS[G@/FGM[PVCI]OTCXZT71_-QUBF\LUHIAB GDL\JJYDDB$^_H\PRDE05>S7'@U]EB!HEO]VTAGSMVE^XV9?]/WS@DRBWJOG@"]GIGV\V@A4j2_;#DQYIN-DAKYRXMK_IRAZTZ52Y+SWLH^NSNKCL.EFJZHHWJF@"X]JR^PFC67<]9%BS[G@/FGM[PVCI]OTCXZT70_-QUBF\LUHIAB SIKEPZTBO::0Y=!F_WKL+BCIW\ZOMYKPOTVX34[)]YNJXHQLEMN,kprX|lg{=45Z0.K\RLI(G\^[YYQ\HHDW8469901^<"GPVHM,KPRW]]UXDDH[<03=5<=R8&CTZDA OTVSQQYT@@L_0<<1189V4*OX^@E$CXZ_UU]PLL@S4895=45Z0.K\RLI(G\^[YYQ\HHDW8429901^<"GPVHM,KPRW]]UXDDH[<07=5<=R8&CTZDA OTVSQQYT@@L_0<81189V4*OX^@E$CXZ_UU]PLL@S48=5=45Z0.K\RLI(G\^[YYQ\HHDW84>9901^<"GPVHM,KPRW]]UXDDH[<0;=5==R8&CTZDA OTVSQQYT@@L_0<0>9:W3+LYQAF%DYY^ZT^QKMCR;:94:56[?/H]UMJ)H]]Z^XR]GIGV?648612_;#DQYIN-LQQVR\VYCEKZ323<2=>S7'@U]EB!@UURVPZUOAO^7>>0>9:W3+LYQAF%DYY^ZT^QKMCR;:=4:56[?/H]UMJ)H]]Z^XR]GIGV?608612_;#DQYIN-LQQVR\VYCEKZ327<2=>S7'@U]EB!@UURVPZUOAO^7>:0>9:W3+LYQAF%DYY^ZT^QKMCR;:14:56[?/H]UMJ)H]]Z^XR]GIGV?6<8602_;#DQYIN-LQQVR\VYCEKZ32?3:?P6(AV\BC"AZTQWW[VNNN]68<3?6;T2,MZPNG&E^X][[_RJJBQ:497;27X> I^TJK*IR\Y__S^FFFU>06;7>3\:$ERXFO.MVPUSSWZBBJY2<3?3:?P6(AV\BC"AZTQWW[VNNN]6883?6;T2,MZPNG&E^X][[_RJJBQ:4=7;27X> I^TJK*IR\Y__S^FFFU>02;7>3\:$ERXFO.MVPUSSWZBBJY2<7?3:?P6(AV\BC"AZTQWW[VNNN]6843?6;T2,MZPNG&E^X][[_RJJBQ:417;37X> I^TJK*IR\Y__S^FFFU>0:4?<]9%BS[G@/NWWTPRX[ACMX1:?>0;8Q5)NW_CD#B[[PTV\WMOA\5>:2<74U1-J[SOH'F__\XZPSIKEP9256830Y=!F_WKL+JSSX\^T_EGIT=60:4?<]9%BS[G@/NWWTPRX[ACMX1:;>0;8Q5)NW_CD#B[[PTV\WMOA\5>>2<74U1-J[SOH'F__\XZPSIKEP9216830Y=!F_WKL+JSSX\^T_EGIT=64:4?<]9%BS[G@/NWWTPRX[ACMX1:7>0;8Q5)NW_CD#B[[PTV\WMOA\5>22<64U1-J[SOH'F__\XZPSIKEP929901^<"GPVHM,KPRW]]UXDDH[<42=5<=R8&CTZDA OTVSQQYT@@L_08?1189V4*OX^@E$CXZ_UU]PLL@S4<85=45Z0.K\RLI(G\^[YYQ\HHDW8059901^<"GPVHM,KPRW]]UXDDH[<46=5<=R8&CTZDA OTVSQQYT@@L_08;1189V4*OX^@E$CXZ_UU]PLL@S4<<5=45Z0.K\RLI(G\^[YYQ\HHDW8019901^<"GPVHM,KPRW]]UXDDH[<4:=5<=R8&CTZDA OTVSQQYT@@L_0871199V4*OX^@E$CXZ_UU]PLL@S4<4:56[?/H]UMJ)H]]Z^XR]GIGV?258612_;#DQYIN-LQQVR\VYCEKZ360<2=>S7'@U]EB!@UURVPZUOAO^7:?0>9:W3+LYQAF%DYY^ZT^QKMCR;>:4:56[?/H]UMJ)H]]Z^XR]GIGV?218612_;#DQYIN-LQQVR\VYCEKZ364<2=>S7'@U]EB!@UURVPZUOAO^7:;0>9:W3+LYQAF%DYY^ZT^QKMCR;>>4:56[?/H]UMJ)H]]Z^XR]GIGV?2=8612_;#DQYIN-LQQVR\VYCEKZ368<2<>S7'@U]EB!@UURVPZUOAO^7:3?6;T2,MZPNG&E^X][[_RJJBQ:087;27X> I^TJK*IR\Y__S^FFFU>45;7?3\:$ERXFO.MVPUSSWZBBJY28>0:8Q5)NW_CD#B[[PTV\WMOA\525=55Z0.K\RLI(G\^[YYQ\HHDW8<86:2_;#DQYIN-PPDRXLF__=?5Z0.K\RLI(]YNJXH2?>018Q5)NW_CD#X^KAUG?5586;2_;#DQYIN-VTAGSM5;:2<=4U1-J[SOH'\ZOMYK313<27>S7'@U]EB!ZPECWA9746890Y=!F_WKL+PVCI]O7=90>3:W3+LYQAF%^\IO[E=36:45<]9%BS[G@/TRGEQC;9?4:?6[?/H]UMJ)RXMK_I1?8>018Q5)NW_CD#X^KAUG?5=86;2_;#DQYIN-VTAGSM5;22<<4U1-J[SOH'\ZOMYK31?30?P6(AV\BC"[_D@VF87699:1^<"GPVHM,QUBF\L69=3?<;T2,MZPNG&_[HLZJ<30=56=R8&CTZDA UQFBP@:5;7;87X> I^TJK*SWLH^N0?:1129V4*OX^@E$Y]JNTD>11;743\:$ERXFO.WS@DRB4;<5=>5Z0.K\RLI(]YNJXH2=7?30?P6(AV\BC"[_D@VF87>99:1^<"GPVHM,QUBF\L6953?=;T2,MZPNG&_[HLZJ<3<27>S7'@U]EB!ZPECWA9576890Y=!F_WKL+PVCI]O7?<0>3:W3+LYQAF%^\IO[E=11:45<]9%BS[G@/TRGEQC;;:4:?6[?/H]UMJ)RXMK_I1=;>018Q5)NW_CD#X^KAUG?7086:2_;#DQYIN-VTAGSM595=?5Z0.K\RLI(]YNJXH2;>008Q5)NW_CD#X^KAUG?1;753\:$ERXFO.WS@DRB4?4:>6[?/H]UMJ)RXMK_I191139V4*OX^@E$Y]JNTD>;:44<]9%BS[G@/TRGEQC;17;87X> I^TJK*SXLH^JSB[[f:W3+LYQAF%^SIAZT0c8Q5)NW_CD#XQ\T@VVW*EAOVINSc<6;T2,MZPNG&_T_YO[UR-E[VRF\R:V"DQ\T@V-QZUSI]827X> I^TJK*SX[]K_Y^!I_RVBP^7Z&@UXXLZ!U^QWEQ4>3\:$ERXFO.W\WQGS]Z%MS^ZNTZ0^*LYT\H^%YR][AU0:?P6(AV\BC"[PSUCWQV)AWZ^JXV=R.H]PPDR)]VY_MY<6;T2,MZPNG&_T_YO[UR-E[VRF\R>V"DQ\T@V-QZUSI]827X> I^TJK*SX[]K_Y^!I_RVBP^3Z&@UXXLZ!U^QWEQ4>3\:$ERXFO.W\WQGS]Z%MS^ZNTZ4^*LYT\H^%YR][AU0:?P6(AV\BC"[PSUCWQV)AWZ^JXV9R.H]PPDR)]VY_MY?n;T2,MZPNG&_T_YO[UR-W@JYimq~:46[?/H]UMJ)RWZ^JXX] U^AF[k533\:$ERXFO.W\WQGS]Z%^S^CZX.W\GVYJ]Q%B8#[PMTZ22*Kj}qUD>>;4U1-J[SOH'\UXXLZZS.W\WHS_'\UH_RCZX.K7*PYJ]Q;=#@czx^M1560<]9%BS[G@/T]PPDRR[&_T_@[W/T]@WZKRP&C?"XQBUY35+HkrpVE9===:;T2,MZPNG&_T_YO[UR-V[VKRP&_TO^QBUY-J0+SXE\R::"Cbuy]L67523\:$ERXFO.W\WQGS]Z%^S^CZX.W\GVYJ]Q%B8#[PMTZ22*Kj}qUD>>=:;T2,MZPNG&_T_YO[UR-V[VKRP&_TO^QBUY-J0+SXE\R::"Cbuy]L61523\:$ERXFO.W\WQGS]Z%^S^CZX.W\GVYJ]Q%B8#[PMTZ22*Kj}qUD>8=:;T2,MZPNG&_T_YO[UR-V[VKRP&_TO^QBUY-J0+SXE\R::"Cbuy]L63523\:$ERXFO.W\WQGS]Z%^S^CZX.W\GVYJ]Q%B8#[PMTZ22*Kj}qUD>:=:;T2,MZPNG&_T_YO[UR-V[VKRP&_TO^QBUY-J0+SXE\R::"Cbuy]L6=523\:$ERXFO.W\WQGS]Z%^S^CZX.W\GVYJ]Q%B8#[PMTZ22*Kj}qUD>4<=;T2,MZPNG&_T_YO[UR-V[VRF\VIEX"MF<0<16>S7'@U]EB!Z_RVBPPU(]VY_MYQLNU-@M949:;1^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(K@682?<4U1-J[SOH'\UXXLZZS.W\WQGSWJD_#NG34?01?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.AJ8085:2_;#DQYIN-V[VRF\\Y$YR][AU]@JQ)DA5<5>?5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$OD28>338Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/E>3:77<]9%BS[G@/T]PPDRR[&_T_YO[_BLW+A:66;;0Y=!F_WKL+PYT\H^^_"[PSUCW[FHS'M692??4U1-J[SOH'\UXXLZZS.W\WQGSWJD_#I2<>338Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/E>7:77<]9%BS[G@/T]PPDRR[&_T_YO[_BLW+A:26;;0Y=!F_WKL+PYT\H^^_"[PSUCW[FHS'M6=2??4U1-J[SOH'\UXXLZZS.W\WQGSWJD_#I28>3f8Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/FY3Y+Ai@'_TAXVLY3:8Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/FY3Y+SXNMXN>:5Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$KV>R.T]OQQ4>3\:$ERXFO.W\WQGS]Z%^S^ZNT^AMP*A\8T$^SUA]CX0g?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.EX5X(@fA$^S@[WCX0;?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.EX5X(RWONYI?94U1-J[SOH'\UXXLZZS.W\WQGSWJD_#JU>]/W\HPR512_;#DQYIN-V[VRF\\Y$YR][AU]@JQ)@S8W%YRV@RB[1`>S7'@U]EB!Z_RVBPPU(]VY_MYQLNU-D_7[)OgB%YRCZXB[1<>S7'@U]EB!Z_RVBPPU(]VY_MYQLNU-D_7[)]VLO^H<8;T2,MZPNG&_T_YO[UR-V[VRF\VIEX"IT2\,V[ISS:01^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(OR8V"XQWOSAZ6a=R8&CTZDA U^QWEQST'\UXXLZPCOV,C^5Z&NdC"XQBUYAZ6==R8&CTZDA U^QWEQST'\UXXLZPCOV,C^5Z&\UMH_K=7:W3+LYQAF%^S^ZNTTQ,QZUSI]UHBY!H[2_-QZJR\;30Y=!F_WKL+PYT\H^^_"[PSUCW[FHS'NQ8Q#[PXNP@]7b<]9%BS[G@/T]PPDRR[&_T_YO[_BLW+B]3U'MeD#[PMTZ@]7><]9%BS[G@/T]PPDRR[&_T_YO[_BLW+B]3U'_TJI\J269V4*OX^@E$YR][AUWP+PYT\H^TOCZ GZ6^*PYK]]827X> I^TJK*SX[]K_Y^!Z_RVBPZEI\&MP8P Z_YMQG\4c3\:$ERXFO.W\WQGS]Z%^S^ZNT^AMP*A\=T$LbE Z_LW[G\4?3\:$ERXFO.W\WQGS]Z%^S^ZNT^AMP*A\=T$^SKJ]E358Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/FY6Y+SXD\^956[?/H]UMJ)RWZ^JXX] U^QWEQYDF]%LW8S!U^ZLVF_5l2_;#DQYIN-V[VRF\\Y$YR][AU]@JQ)@S?W%KcF!U^OV\F_502_;#DQYIN-V[VRF\\Y$YR][AU]@JQ)@S?W%YRHKRD04?P6(AV\BC"[PSUCWQV)RWZ^JXRMAT.EX2X(RWE__>45Z0.K\RLI(]VY_MY[\/T]PPDRXKG^$KV8R.T][KWE^:11^<"GPVHM,QZUSI]_X#XQ\T@V\GKR(OR=V"XQIDSG13>S7'@U]EB!Z_RVBPPU(]VY_MYQLNU-D_2[)]VF^X?74U1-J[SOH'\UXXLZZS.W\WQGSWJD_#JU8]/W\\JTDQ;;0Y=!F_WKL+PYT\H^^_"[PSUCW[FHS'Z6;2??4U1-J[SOH'\UXXLZZS.W\WQGSWJD_#^2>>338Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/R>1:77<]9%BS[G@/T]PPDRR[&_T_YO[_BLW+V:46;;0Y=!F_WKL+PYT\H^^_"[PSUCW[FHS'Z6?2??4U1-J[SOH'\UXXLZZS.W\WQGSWJD_#^2:>338Q5)NW_CD#XQ\T@VVW*SX[]K_SN@[/R>5:77<]9%BS[G@/T]PPDRR[&_T_YO[_BLW+V:068=0Y=!F_WKL+PYT\H^^_"[PTEM2e>S7'@U]EB!Z_RVBPPU(aZ^JX1>11`9V4*OX^@E$YR][AUWP+lUSI]6:2<o4U1-J[SOH'\UXXLZZS.kPPDR;:7;j7X> I^TJK*SX[]K_Y^!fSUCW8686i2_;#DQYIN-V[VRF\\Y$e^ZNT=6=5d=R8&CTZDA U^QWEQST'`Y_MY2:>0c8Q5)NW_CD#XQ\T@VVW*oT\H^7:3?n;T2,MZPNG&_T_YO[UR-jWQGS4>4:i6[?/H]UMJ)RWZ^JXX] iRVBPZEI\5:5=h5Z0.K\RLI(]VY_MY[\/hQWEQYDF]6:2<k4U1-J[SOH'\UXXLZZS.kPPDRXKG^7>3?j;T2,MZPNG&_T_YO[UR-jWQGSWJD_0>0>e:W3+LYQAF%^S^ZNTTQ,mVRF\VIEX1:11d9V4*OX^@E$YR][AUWP+lUSI]UHBY2:>0g8Q5)NW_CD#XQ\T@VVW*oT\H^TOCZ36?3f?P6(AV\BC"[PSUCWQV)n[]K_SN@[<6<16>S7'@U]EB!}ergw[cYblno$ERF=L/W\@JSS9m1^<"GPVHM,v`ub|VlTiiij/T]GKPR79m1^<"GPVHM,v`ub|VlTiiij/T]GKPR69l1^<"GPVHM,v`ub|VlTiiij/hFLQQ:768o0Y=!F_WKL+wctm}UmShjhe.kGKPR;97i0Y^K]_WKPMGJB;2\HO45YIDU\P\VB9m1SEAGAX,ZGF%6)9)Y_YO.?.0"BWFON=2RD^NW9;YQWHLD03QY_SJ@K7:ZPPZPDKk1SSNA]E^KMBJ0<PmhTEih4Xej\Twoj^lxxeb`>0:ZgiZKfbfx]i}foo33?]bjWDcecXjrrklj6=_{}90Uh}6;`qzjfYj}qn0oegsbmsaZpng:;0oegsbmsaZpngV|:S=;Pa-"[mioip)ID^H.Heogqeqiu(89%?:5lotlwaw7e3jyTob`{rnnaqvY{}}d~fo}otlg2>etWds46m|_lw{53b<mmmnSik{ebvlv==iojh~eaj:;wkl73423cd?;"lhhrpgjvbWcdS{?P04]b(KIIM%DDBH<i6:tjk60+kac{nae^tjkZp6W9?Tm!ul_yal[iot|4Ida}aaeov\Jdkb5cd?;5Jn``oaZU~fjbyccazs^KmtprXXfx1kocsd9FjddkmVYrbnf}oomvwZIr|yS]a}t<dbhvc<Mgki`hQNsxl`lwiig|yTEc~zt^Rlvq;aieyn7H`nbmg\Evikaxdbb{|_NwwtprXXfx1y|ze:Qzjfnugge~RGaptv\TjtsW^coxe37;R{mgmthffxSB{{ptv\TjtsW^coxe37;@qzjfnugge~RGaptv\TjtsW^coxe37;@qzjfnugge~RAztqww[Uiu|V]bhyf2379Jjscu|VIgcnePIorvp8`fdzo'oRvkewk`acgjaes6zd|{ey4/gZehzlUu}k29-a\icaXam7: nQbakmq[scu{`ee1<=#c^ojjjtX~lxxeb`23-a\fpoklVxnzd}foo?3(fYdg{oTald`r^tfv87+kVid~hQbiomq[scu5;&hSna}e^ojjjtXiezcmRxjr<;4(fYtze;=Sywe<0/gZstmVcezRmck<2/gZstmVkxucmPio?3(fYr{lUjt`l_nww94*dW|ynS~wac^km95*dW|ynS~wac^mvp86+kVkxucmPio]tmaro51&hSl}vnb]lqqYpam~c1>8#c^qzjfYnfV}bhyf28-a\w|hdWfSzgkti?;(fYdggy~lgat^vzt`;bekoohhj#c^g{ehvkmVnndia=gcow`*zl2|bcRo|yoa\kpr?3cdSna}e048rliXg|~{yyQzpecwaZebdek0zdaPsucwqv{GHy<?o6NOx300>C<328qX;>4=198:e?74;9>2?7<?b96xj771281e><956:&151<58l1v_9m520:9=d<6;::?5>4=0c:4?V>e2;896=4>3227=6<58k2i7^:l:301>5<6;::?5>4=0c;3?a45;3:1=7?tS61964>=1h0:?>>;92814g>23^j97>51;39af}T?:09=546a;30752>;38;n5;4$32g>=b<^;;>6?uz9582?p?2291v(4m5c:`166<72=21ol4jczJ14g=#i109>>5U3481<<f2t.9=>4=1b9'7<<5:=1/;?4=249'e1<63-k86??6;*4b>5<#1l0=56`6d;28?.0?290/5h499:l:`?7<3"<<6=4+9d85=>h>l3807&89:18'=`<112d2h7=4;*46>5<#1l0=56`6d;68?.03290/5h499:l:`?3<3"<96=4+9d85=>h>l3<07&8>:18'=`<112d2h794;*43>5<#1l0=56`6d;:8?.3a290/5h499:l:`??<3"?n6=4+9d85=>h>l3k07&;k:18'=`<112d2h7l4;*7`>5<#1l0=56`6d;a8?.3e290/5h499:l:`?b<3"?j6=4+9d85=>h>l3o07&;6:18'=`<112d2h7h4;*74>5<#1l0=56`6d;33?>-2>3:1(4k5689m=a<6921 984?:%;f>3?<f0n1=?54+4694?">m3<27c7k:018?.34290/5h499:l:`?7332!>>7>5$8g92<=i1m0:965$5083>!?b2?30b4j51798/06=83.2i786;o;g>41<3">m6=4+9d85=>h>l3;376%;e;29 <c=>01e5i4>9:9(34<72-3n6;74n8f95d=<#>:1<7*6e;4:?k?c28h07&8i:18'=`<112d2h7?l;:)5a?6=,0o1:45a9e82`>=,>m0;6)7j:7;8j<b=9l10';m50;&:a?0>3g3o6<h4;*40>5<#1l0=56`6d;02?>-203:1(4k5689m=a<5:21 8i4?:%;f>3?<f0n1>>54o3f94?">m38h7c7k:198k7d=83.2i7<l;o;g>4=<g;k1<7*6e;0`?k?c2;10c?750;&:a?4d3g3o6>54o3:94?">m38h7c7k:598k71=83.2i7<l;o;g>0=<g;?1<7*6e;0`?k?c2?10c?:50;&:a?4d3g3o6:54o3194?">m38h7c7k:998k74=83.2i7<l;o;g><=<g;;1<7*6e;0`?k?c2h10c?>50;&:a?4d3g3o6o54o0d94?">m38h7c7k:b98k4c=83.2i7<l;o;g>a=<g8n1<7*6e;0`?k?c2l10c<m50;&:a?4d3g3o6k54o0c94?">m38h7c7k:028?j7>290/5h4=c:l:`?7632e:47>5$8g96f=i1m0:>65`1683>!?b2;i0b4j51298k40=83.2i7<l;o;g>42<3f;>6=4+9d81g>h>l3;>76a>4;29 <c=:j1e5i4>6:9l56<72-3n6?m4n8f952=<g881<7*6e;0`?k?c28207b?>:18'=`<5k2d2h7?6;:m00?6=,0o1>n5a9e82e>=h;:0;6)7j:3a8j<b=9k10c><50;&:a?4d3g3o6<m4;n12>5<#1l09o6`6d;3g?>i483:1(4k52b9m=a<6m21d>k4?:%;f>7e<f0n1=k54o3g94?">m38h7c7k:328?j41290/5h4=c:l:`?4632e:n7>5$8g96f=i1m09>65`1183>!?b2;i0b4j52298/3d=83.2i786;o;g>76<3k8:>7>51;294~"f038;o6F=119K65d<g0h1<75rb332>5<6290;w)o7:6d8L7773A8;n6a8e;29?xd6i10;694?:1y'e=<?n2B9==5G21`8 =1=;>1b4<4?::k;6?6=3`286=44o8;94?=zj;:<6=4;:183!g?2>30D???;I03f>"??380e>850;9j7=<722c<87>5;nc3>5<<uk8;47>54;294~"f03=27E<>0:J14g=#0>097d=9:188m6>=831b;94?::mb4?6=3th9<;4?:583>5}#i10<m6F=119K65d<,1=1>6g<6;29?l132900el?50;9le5<722wiml4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wimo4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wio=4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wio<4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wih;4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wih:4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wii94?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wii84?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wii;4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wii:4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wii54?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wii44?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wiil4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wiio4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wiin4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wiii4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wiih4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wiik4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wij=4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wij<4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wimn4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wimi4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wimh4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wimk4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722win=4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722win<4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722win?4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722win>4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722win94?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722win84?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722win;4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722win:4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722win54?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722win44?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722winl4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wino4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722winn4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wini4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722winh4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wink4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wio?4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wio>4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wio94?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wio84?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wio;4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wio:4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wio54?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wio44?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wiol4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wioo4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wion4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wioi4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wioh4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wiok4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wih=4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wih<4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wih?4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wih>4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wih94?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wih84?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wih54?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wih44?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wihl4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wiho4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wihn4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wihi4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wihh4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wihk4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wii=4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wii<4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wii?4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wii>4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wij>4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wij?4?:483>5}#i10<n6F=119K65d<,1=1>6g<6;29?l5?2900e::50;9je4<722ej<7>5;|`e1?6=<3:1<v*n8;5:?M4682B9<o5+8681?l512900e>650;9j31<722ej<7>5;|`e0?6==3:1<v*n8;5a?M4682B9<o5+8681?l512900e>650;9j31<722cj=7>5;nc3>5<<ukl<6=4;:183!g?2>30D???;I03f>"??380e>850;9j7=<722c<87>5;nc3>5<<ukl=6=4::183!g?2>h0D???;I03f>"??380e>850;9j7=<722c<87>5;hc2>5<<gh:1<75rbg;94?2=83:p(l65789K646<@;:i7)68:39j73<722c847>5;h57>5<<gh:1<75rbg:94?3=83:p(l657c9K646<@;:i7)68:39j73<722c847>5;h57>5<<ah;1<75`a183>>{enk0;694?:1y'e=<012B9==5G21`8 =1=:2c8:7>5;h1;>5<<a>>1<75`a183>>{enh0;684?:1y'e=<0j2B9==5G21`8 =1=:2c8:7>5;h1;>5<<a>>1<75fa083>>if83:17plid;290?6=8r.j4796;I024>N58k1/4:4=;h15>5<<a:21<75f7583>>if83:17plic;291?6=8r.j479m;I024>N58k1/4:4=;h15>5<<a:21<75f7583>>of93:17bo?:188yg`a290?6=4?{%c;>2?<@;;;7E<?b:&;3?4<a:<1<75f3983>>o0<3:17bo?:188yg`b290>6=4?{%c;>2d<@;;;7E<?b:&;3?4<a:<1<75f3983>>o0<3:17do>:188kd6=831vn<>>:187>5<7s-k36:74H333?M47j2.3;7<4i2494?=n;10;66g84;29?jg72900qo??0;291?6=8r.j479m;I024>N58k1/4:4=;h15>5<<a:21<75f7583>>of93:17bo?:188yg77;3:187>50z&b<?1>3A8:<6F=0c9'<2<53`9=6=44i2:94?=n?=0;66an0;29?xd68;0;684?:1y'e=<0j2B9==5G21`8 =1=:2c8:7>5;h1;>5<<a>>1<75fa083>>if83:17pl>0483>1<729q/m5489:J155=O:9h0(5952:k02?6=3`936=44i6694?=hi90;66sm11694?3=83:p(l657c9K646<@;:i7)68:39j73<722c847>5;h57>5<<ah;1<75`a183>>{e99=1<7:50;2x d>=?01C><>4H32a?!>02;1b?;4?::k0<?6=3`=?6=44o`294?=zj8:=6=4::183!g?2>h0D???;I03f>"??380e>850;9j7=<722c<87>5;hc2>5<<gh:1<75rb02:>5<3290;w)o7:6;8L7773A8;n6*77;08m60=831b?54?::k40?6=3fk;6=44}c33<?6==3:1<v*n8;5a?M4682B9<o5+8681?l512900e>650;9j31<722cj=7>5;nc3>5<<uk;;n7>54;294~"f03=27E<>0:J14g=#0>097d=9:188m6>=831b;94?::mb4?6=3th:<l4?:483>5}#i10<n6F=119K65d<,1=1>6g<6;29?l5?2900e::50;9je4<722ej<7>5;|`24a<72=0;6=u+a984=>N5991C>=l4$9596>o4>3:17d=7:188m22=831dm=4?::a55e=83?1<7>t$`:93g=O:8:0D?>m;%:4>7=n;?0;66g<8;29?l132900el?50;9le5<722wi==h50;694?6|,h21;45G2028L76e3-2<6?5f3783>>o403:17d9;:188kd6=831vn<>j:186>5<7s-k36:l4H333?M47j2.3;7<4i2494?=n;10;66g84;29?lg62900cl>50;9~f476290?6=4?{%c;>2?<@;;;7E<?b:&;3?4<a:<1<75f3983>>o0<3:17bo?:188yg7683:197>50z&b<?1e3A8:<6F=0c9'<2<53`9=6=44i2:94?=n?=0;66gn1;29?jg72900qo?>3;290?6=8r.j4796;I024>N58k1/4:4=;h15>5<<a:21<75f7583>>if83:17pl>1383>0<729q/m548b:J155=O:9h0(5952:k02?6=3`936=44i6694?=ni80;66an0;29?xd69<0;694?:1y'e=<012B9==5G21`8 =1=:2c8:7>5;h1;>5<<a>>1<75`a183>>{e98>1<7;50;2x d>=?k1C><>4H32a?!>02;1b?;4?::k0<?6=3`=?6=44i`394?=hi90;66sm10594?2=83:p(l65789K646<@;:i7)68:39j73<722c847>5;h57>5<<gh:1<75rb035>5<2290;w)o7:6`8L7773A8;n6*77;08m60=831b?54?::k40?6=3`k:6=44o`294?=zj8;26=4;:183!g?2>30D???;I03f>"??380e>850;9j7=<722c<87>5;nc3>5<<uk;:47>55;294~"f03=i7E<>0:J14g=#0>097d=9:188m6>=831b;94?::kb5?6=3fk;6=44}c32f?6=<3:1<v*n8;5:?M4682B9<o5+8681?l512900e>650;9j31<722ej<7>5;|`25d<72<0;6=u+a984f>N5991C>=l4$9596>o4>3:17d=7:188m22=831bm<4?::mb4?6=3th:=i4?:583>5}#i10<56F=119K65d<,1=1>6g<6;29?l5?2900e::50;9le5<722wi=<m50;794?6|,h21;o5G2028L76e3-2<6?5f3783>>o403:17d9;:188md7=831dm=4?::a54`=83>1<7>t$`:93<=O:8:0D?>m;%:4>7=n;?0;66g<8;29?l132900cl>50;9~f47b290>6=4?{%c;>2d<@;;;7E<?b:&;3?4<a:<1<75f3983>>o0<3:17do>:188kd6=831vn<<>:187>5<7s-k36:74H333?M47j2.3;7<4i2494?=n;10;66g84;29?jg72900qo?=0;291?6=8r.j479m;I024>N58k1/4:4=;h15>5<<a:21<75f7583>>of93:17bo?:188yg75;3:187>50z&b<?1>3A8:<6F=0c9'<2<53`9=6=44i2:94?=n?=0;66an0;29?xd6:;0;684?:1y'e=<0j2B9==5G21`8 =1=:2c8:7>5;h1;>5<<a>>1<75fa083>>if83:17pl>2483>1<729q/m5489:J155=O:9h0(5952:k02?6=3`936=44i6694?=hi90;66sm13694?3=83:p(l657c9K646<@;:i7)68:39j73<722c847>5;h57>5<<ah;1<75`a183>>{e9;=1<7:50;2x d>=?01C><>4H32a?!>02;1b?;4?::k0<?6=3`=?6=44o`294?=zj88=6=4::183!g?2>h0D???;I03f>"??380e>850;9j7=<722c<87>5;hc2>5<<gh:1<75rb00:>5<3290;w)o7:6;8L7773A8;n6*77;08m60=831b?54?::k40?6=3fk;6=44}c31<?6==3:1<v*n8;5a?M4682B9<o5+8681?l512900e>650;9j31<722cj=7>5;nc3>5<<uk;9n7>54;294~"f03=27E<>0:J14g=#0>097d=9:188m6>=831b;94?::mb4?6=3th:>l4?:483>5}#i10<n6F=119K65d<,1=1>6g<6;29?l5?2900e::50;9je4<722ej<7>5;|`26a<72=0;6=u+a984=>N5991C>=l4$9596>o4>3:17d=7:188m22=831dm=4?::a57e=83?1<7>t$`:93g=O:8:0D?>m;%:4>7=n;?0;66g<8;29?l132900el?50;9le5<722wi=?h50;694?6|,h21;45G2028L76e3-2<6?5f3783>>o403:17d9;:188kd6=831vn<<j:186>5<7s-k36:l4H333?M47j2.3;7<4i2494?=n;10;66g84;29?lg62900cl>50;9~f456290?6=4?{%c;>2?<@;;;7E<?b:&;3?4<a:<1<75f3983>>o0<3:17bo?:188yg7483:197>50z&b<?1e3A8:<6F=0c9'<2<53`9=6=44i2:94?=n?=0;66gn1;29?jg72900qo?<3;290?6=8r.j4796;I024>N58k1/4:4=;h15>5<<a:21<75f7583>>if83:17pl>3383>0<729q/m548b:J155=O:9h0(5952:k02?6=3`936=44i6694?=ni80;66an0;29?xd6;<0;694?:1y'e=<012B9==5G21`8 =1=:2c8:7>5;h1;>5<<a>>1<75`a183>>{e9:>1<7;50;2x d>=?k1C><>4H32a?!>02;1b?;4?::k0<?6=3`=?6=44i`394?=hi90;66sm12594?2=83:p(l65789K646<@;:i7)68:39j73<722c847>5;h57>5<<gh:1<75rb015>5<2290;w)o7:6`8L7773A8;n6*77;08m60=831b?54?::k40?6=3`k:6=44o`294?=zj8926=4;:183!g?2>30D???;I03f>"??380e>850;9j7=<722c<87>5;nc3>5<<uk;847>55;294~"f03=i7E<>0:J14g=#0>097d=9:188m6>=831b;94?::kb5?6=3fk;6=44}c3b3?6=<3:1<v*n8;5:?M4682B9<o5+8681?l512900e>650;9j31<722ej<7>5;|`2ed<72<0;6=u+a98:4>N5991C>=l4$9591>o?93:17d6=:188m=5=831b494?::m:=?6=3th:mo4?:483>5}#i102<6F=119K65d<,1=1;85f8083>>o?:3:17d6<:188m=2=831d544?::a5de=83?1<7>t$`:9=5=O:8:0D?>m;%:4>==n080;66g72;29?l>42900e5:50;9l=<<722wi=lj50;794?6|,h215=5G2028L76e3-2<6;5f8083>>o?:3:17d6<:188m=2=831d544?::a5dc=83?1<7>t$`:9=5=O:8:0D?>m;%:4>6=n080;66g72;29?l>42900e5:50;9l=<<722wi=lh50;794?6|,h215=5G2028L76e3-2<6o5f8083>>o?:3:17d6<:188m=2=831d544?::a5g6=83?1<7>t$`:9=5=O:8:0D?>m;%:4>1=n080;66g72;29?l>42900e5:50;9l=<<722wi=o?50;794?6|,h215=5G2028L76e3-2<6>5f8083>>o?:3:17d6<:188m=2=831d544?::a5g5=8381<7>t$`:9<==O:8:0D?>m;h:3>5<<g031<75rb0d6>5<3290;w)o7:6;8L7773A8;n6*77;08m60=831b?54?::k40?6=3fk;6=44}c3g5?6=;3:1<v*n8;03b>N5991C>=l4i2c94?=n000;66a69;29?xd6kl0;694?:1y'e=<>;2B9==5G21`8m6g=831b;;4?::kb6?6=3f2j6=44}c3g1?6=;3:1<v*n8;03b>N5991C>=l4i2c94?=n000;66a69;29?xd6l;0;694?:1y'e=<>;2B9==5G21`8m6g=831b;;4?::kb6?6=3f2j6=44}c3g=?6=;3:1<v*n8;03b>N5991C>=l4i2c94?=n000;66a69;29?xd6l?0;694?:1y'e=<>;2B9==5G21`8m6g=831b;;4?::kb6?6=3f2j6=44}c3g`?6=;3:1<v*n8;03b>N5991C>=l4i2c94?=n000;66a69;29?xd6lh0;694?:1y'e=<>;2B9==5G21`8m6g=831b;;4?::kb6?6=3f2j6=44}c3f5?6=;3:1<v*n8;03b>N5991C>=l4i2c94?=n000;66a69;29?xd6ll0;694?:1y'e=<>;2B9==5G21`8m6g=831b;;4?::kb6?6=3f2j6=44}c3f1?6=;3:1<v*n8;03b>N5991C>=l4i2c94?=n000;66a69;29?xd6m;0;694?:1y'e=<>;2B9==5G21`8m6g=831b;;4?::kb6?6=3f2j6=44}c3f=?6=;3:1<v*n8;03b>N5991C>=l4i2c94?=n000;66a69;29?xd6m?0;694?:1y'e=<>;2B9==5G21`8m6g=831b;;4?::kb6?6=3f2j6=44}c3fg?6=;3:1<v*n8;03b>N5991C>=l4i2c94?=n000;66a69;29?xd6l90;6?4?:1y'e=<?m2B9==5G21`8 =1=?2c3=7>5;n;:>5<<uk;o87>52;294~"f032n7E<>0:J14g=#0>0<7d6>:188k<?=831vn<j7:181>5<7s-k365k4H333?M47j2.3;794i9394?=h100;66sm1ea94?4=83:p(l658d9K646<@;:i7)68:69j<4<722e257>5;|`2a5<72;0;6=u+a98;a>N5991C>=l4$9593>o?93:17b76:188yg7b<3:1>7>50z&b<?>b3A8:<6F=0c9'<2<03`2:6=44o8;94?=zj8o36=4=:183!g?21o0D???;I03f>"??3=0e5?50;9l=<<722wi=hl50;094?6|,h214h5G2028L76e3-2<6:5f8083>>i>13:17pl>cg83>0<729q/m548b:J155=O:9h0(5952:k02?6=3`936=44i6694?=ni80;66an0;29?xd6l:0;684?:1y'e=<0j2B9==5G21`8 =1=:2c8:7>5;h1;>5<<a>>1<75fa083>>if83:17pl>d683>0<729q/m548b:J155=O:9h0(5952:k02?6=3`936=44i6694?=ni80;66an0;29?xd6lk0;684?:1y'e=<0j2B9==5G21`8 =1=:2c8:7>5;h1;>5<<a>>1<75fa083>>if83:17pl>dg83>0<729q/m548b:J155=O:9h0(5952:k02?6=3`936=44i6694?=ni80;66an0;29?xd6m:0;684?:1y'e=<0j2B9==5G21`8 =1=:2c8:7>5;h1;>5<<a>>1<75fa083>>if83:17pl>e683>0<729q/m548b:J155=O:9h0(5952:k02?6=3`936=44i6694?=ni80;66an0;29?xd6mh0;684?:1y'e=<0j2B9==5G21`8 =1=:2c8:7>5;h1;>5<<a>>1<75fa083>>if83:17pl>b483>2<729q/m5462:J155=O:9h0(595799j<4<722c3>7>5;h:0>5<<a1>1<75f8483>>o?>3:17b76:188yg7e?3:1;7>50z&b<??53A8:<6F=0c9'<2<002c3=7>5;h:1>5<<a191<75f8583>>o?=3:17d69:188k<?=831vn<l7:184>5<7s-k364<4H333?M47j2.3;7k4i9394?=n0;0;66g73;29?l>32900e5;50;9j<3<722e257>5;|`2f<<72>0;6=u+a98:6>N5991C>=l4$959a>o?93:17d6=:188m=5=831b494?::k;1?6=3`2=6=44o8;94?=zj8hj6=48:183!g?2080D???;I03f>"??3o0e5?50;9j<7<722c3?7>5;h:7>5<<a1?1<75f8783>>i>13:17pl>bc83>2<729q/m5462:J155=O:9h0(595e:k;5?6=3`296=44i9194?=n0=0;66g75;29?l>12900c4750;9~f4dd290<6=4?{%c;><4<@;;;7E<?b:&;3?c<a1;1<75f8383>>o?;3:17d6;:188m=3=831b4;4?::m:=?6=3th:ni4?:483>5}#i102<6F=119K65d<,1=1h6g71;29?l>52900e5=50;9j<1<722e257>5;|`2f`<72>0;6=u+a98:6>N5991C>=l4$9593f=n080;66g72;29?l>42900e5:50;9j<0<722c3:7>5;n;:>5<<uk;i:7>56;294~"f033:7E<>0:J14g=#0>0m7d6>:188m=4=831b4>4?::k;0?6=3`2>6=44o8;94?=z{?k1<7<t^7c894dc21>0q~87:181[0?34;ih76<;|q53?6=:rT=;63>be8;5>{t>?0;6?uQ679>5gb=0;1v;;50;0xZ33<58hh6584}r47>5<5sW<?70?mc;:6?xu1:3:1>vP92:?2ff<?<2wx:<4?:3y]24=:9ki14>5rs7294?4|V?:01<ll:938yv3a2909wS;i;<3ag?>53ty>i7>52z\6a>;6j003:6s|5e83>7}Y=m16=o75849~w0e=838pR8m4=0`:>=2<uz?i6=4={_7a?87e13287p}:a;296~X2i27:n4471:p1<<72;qU94521c;9<7=z{<=1<7<t^45894d?21<0q~;9:181[3134;i476:;|q61?6=:rT>963>b98;0>{t==0;6?uQ559>5g>=0:1v8=50;0xZ05<58h365?4}r71>5<5sW?970?m8;:1?xu293:1>vP:1:?2fg<?>2wx9=4?:3y]15=:9kh1485rs5d94?4|V=l01<lm:968yv2b2909wS:j;<3af?>43ty<=7>52z\45>;6jk03=6s|7183>7}Y?916=ol5839~w3`=83>pR;h4=324>22<58k365=4=0`b>=0<uz<n6=4=6z\5a>;6;108463>3780<>;6;=08463>3380<>;6;908463>2d80<>;6:j08463>2`80<>;6:108463>2780<>;6:=08463>2380<>;6:908463>1d80<>;69j08463>1`80<>;69108463>1780<>;69=08463>1380<>;69908463>0d80<>;68j08463>0`80<>;68108463>0780<>;68=08463>0380<>;68908463ie;1;?8`d2:201ko5399>b=<4027m:7=7;<d7>6><5o81?5521cc9<0=z{?n1<78j{_4g?874139370?<8;c2?874?39370?<6;c2?874=39370?<4;c2?874;39370?<2;c2?874939370?<0;c2?875n39370?=e;c2?875l39370?=c;c2?875j39370?=a;c2?875139370?=8;c2?875?39370?=6;c2?875=39370?=4;c2?875;39370?=2;c2?875939370?=0;c2?876n39370?>e;c2?876l39370?>c;c2?876j39370?>a;c2?876139370?>8;c2?876?39370?>6;c2?876=39370?>4;c2?876;39370?>2;c2?876939370?>0;c2?877n39370??e;c2?877l39370??c;c2?877j39370??a;c2?877139370??8;c2?877?39370??6;c2?877=39370??4;c2?877;39370??2;c2?877939370??0;c2?8`a2:201kk5a09>ba<4027mo7o>;<da>6><5ok1m<52f880<>;a03k:70h8:2:89c0=i816j84<8:?e0?g634l86>64=g09e4=:m;08463j0;1;?8bb2:201im5399>`d<4027o47=7;<f7>6><5m81?552d180<>;dm39370ml:2:89fg=;116o54<8:?`2?5?34i?6>64=b097==:jl08463mc;1;?8df2:201o65399>f3<4027i87=7;<`1>6><5k:1?552ad80<>;fk39370h?:2:89`c=;116in4<8:?fe?5?34o36>64=d497==:m=08463k6;1;?8e72:201lo5399>5gg=0=1v;m50;1xZ3e<58h865>4=0`b>=5<uz<86=4={_40?87ei32:7p}:8;297~X2027jm79;;<3ae?>53ty?h7>59dy]0a=:9h=1?;5212;973=:9:21?;52125973=:9:<1?;52127973=:9:>1?;52121973=:9:81?;52123973=:9::1?;5213d973=:9;o1?;5213f973=:9;i1?;5213`973=:9;k1?;5213;973=:9;21?;52135973=:9;<1?;52137973=:9;>1?;52131973=:9;81?;52133973=:9;:1?;5210d973=:98o1?;5210f973=:98i1?;5210`973=:98k1?;5210;973=:9821?;52105973=:98<1?;52107973=:98>1?;52101973=:9881?;52103973=:98:1?;5211d973=:99o1?;5211f973=:99i1?;5211`973=:99k1?;5211;973=:9921?;52115973=:99<1?;52117973=:99>1?;52111973=:9981?;52113973=:99:1?;52fg802>;am39=70hk:2489ce=;?16jo4<6:?ee?5134l26>84=g:973=:n>08:63i6;15?8`22:<01k:5379>b6<4>27m>7=9;<g1>60<5l91?;52e1802>;b939=70jj:2489a`=;?16hn4<6:?g`?5134nj6>84=e`973=:l108:63k9;15?8b32:<01i;5379>`7<4>27o?7=9;<f3>60<5m;1?;52cd802>;dn39=70ml:2489fb=;?16ol4<6:?`f?5134i36>84=b;973=:k?08:63l7;15?8e32:<01n;5379>g7<4>27h?7=9;<`f>60<5kl1?;52bb802>;el39=70ln:2489gd=;?16n54<6:?a=?5134h=6>84=c5973=:j=08:63m5;15?8d52:<01o=5379>f5<4>27i=7=9;<cf>60<5hl1?;52ab802>;fl39=70h?:2489c7=;?16ih4<6:?fb?5134oh6>84=df973=:mh08:63jb;15?8c?2:<01h75379>a3<4>27n;7=9;<g7>60<5l?1?;52d7802>;c?39=70m?:2489f7=;?16ml4<6:?bf?51348;;7=9;<03<?51348;:7=9;<3e1?5134;nm7=9;<3f3?5134;n?7=9;<3gb?5134;on7=9;<3g3?5134;o?7=9;<3`b?513ty9h7>52z\1`>;b;3k;7p}=b;296~X5j27n=7o?;|q1e?6=:rT9m63kf;c3?xu513:1>vP=9:?g`?g73ty947>52z\1<>;cj3k;7p}=7;296~X5?27o57o?;|q11?6=:rT9963k5;c3?xu5<3:1>vP=4:?g7?g73ty9?7>52z\17>;c93k;7p}=2;296~X5:27hj7o?;|q15?6=:rT9=63ld;c3?xu583:1>vP=0:?`f?g73ty:j7>52z\2b>;d13k;7p}>e;296~X6m27h;7o?;|q2`?6=:rT:h63l5;c3?xu6k3:1>vP>c:?`7?g73ty:m7>52z\2e>;en3k;7p}>9;296~X6127ih7o?;|q2<?6=:rT:463mb;c3?xu6?3:1>vP>7:?a=?g73ty::7>52z\22>;e?3k;7p}>5;296~X6=27i97o?;|q20?6=:rT:863m3;c3?xu6;3:1>vP>3:?a5?g73ty:>7>52z\26>;fn3k;7p}>1;296~X6927jh7o?;|q00?6=:rT8863i1;c3?xu4;3:1>vP<3:?fb?g73ty8>7>52z\06>;bl3k;7p}<1;296~X4927nn7o?;|q04?6=:rT8<63j9;c3?xu5n3:1>vP=f:?f3?g73ty9i7>52z\1a>;b=3k;7p}=6;296~X5>27o;7o?;|q2f?6=:rT:n63l1;c3?xu683:1>vP>0:?bf?g73ty=n7>52z\5f>;6i10256s|9783>c}::8815o521`597==::9=1?55221:97==:9o?1?5521dc97==:9l=1?5521d197==:9ml1?5521e`97==:9m=1?5521e197==:9jl1?5521bg97d=:9m;1?l5rs8594??|5;;:6:k4=0c4>22<58o=6:84=0g1>20<58nn6:84=0fb>20<58n=6:84=0f1>20<58in6:84}r03=?6=;r79<:4n0:?14=<0<279<;4n1:p65g=838p1?>7:`2897612>>0q~?<a;296~;6;00j<63>39840>{ti00;6?u21`59e5=:9h214?5rs074>5<4s4l86::4=d09e5=:m:0<86s|14494?5|5l81;952e18b4>;b93=?7p}>5483>6}:m90<863ke;c3?8ba2>>0q~?:4;297~;cm3=?70jl:`289ab=?=1v<;<:1808bd2>>01io5a19>`g<0<2wx=8<50;1x9ag=?=16h54n0:?g=?133ty:9<4?:2y>`=<0<27o87o?;<f6>22<uz;?j7>53z?g0?1334n96l>4=e1931=z{8>n6=4<{<f1>22<5m:1m=52d0840>{t9=n1<7=t=e2931=:kl0j<63lf;57?xu6<j0;6>u2cd840>;dk3k;70mk:668yv73j3:1?v3lc;57?8ef2h:01nl5759~w42f2908w0mn:6689f>=i916o4484:p51?=839p1n65759>g3<f827h;79;;|q20=<72:q6o;484:?`0?g734i>6::4}r373?6=;r7h879;;<a1>d6<5j91;95rs065>5<4s4i96::4=cg9e5=:jo0<86s|15694?5|5ko1;952bb8b4>;el3=?7p}>4283>6}:jj0<863ma;c3?8de2>>0q~?;2;297~;ei3=?70l7:`289g?=?=1v<:>:1808d?2>>01o85a19>f2<0<2wx=9>50;1x9g0=?=16n94n0:?a1?133ty:?k4?:2y>f1<0<27i>7o?;<`0>22<uz;8i7>53z?a6?1334h;6l>4=c3931=z{89o6=4<{<`3>22<5ho1m=52ag840>{t9:i1<7=t=`g931=:ij0j<63nd;57?xu6;k0;6>u2ab840>;a83k;70h>:668yv7?93:1?v3i0;57?8cb2h:01hh5759~w4>72908w0kj:6689`e=i916ii484:p52`=839p1hm5759>ad<f827nn79;;|q23f<72:q6il484:?f<?g734o26::4}r345?6=;r7n479;;<g5>d6<5l=1;95rs045>5<4s4o=6::4=d69e5=:m<0<86s|14`94?5|5l>1;952d78b4>;c?3=?7p}>5183>6}:l?0<863l0;c3?8e62>>0q~?;5;297~;d83=?70on:`289dd=?=1v<7i:18187403k;70k<:2:8yv70m3:1?v3>38840>;6;>0j<63>37840>{t90o1<7<t=015>d6<5l;1?55rs05g>5<4s4;8;79;;<301?g734;8879;;|q2=a<72;q6=>:5a19>`c<402wx=:l50;1x94522>>01<=<:`2894552>>0q~?6c;296~;6;;0j<63kd;1;?xu6?h0;6>u2121931=:9:;1m=52122931=z{83i6=4={<304?g734ni6>64}r34=?6=;r7:?<484:?26c<f827:>h484:p5<g=838p1<<j:`289a?=;11v<97:180875n3=?70?=d;c3?875k3=?7p}>9983>7}:9;i1m=52d480<>{t9>=1<7=t=00g>22<588i6l>4=00b>22<uz;2;7>52z?26d<f827o?7=7;|q233<72:q6=?l5759>57?=i916=?65759~w4?12909w0?=8;c3?8b62:20q~?85;297~;6:00<863>268b4>;6:?0<86s|18794?4|588=6l>4=bd97==z{8=?6=4<{<313?1334;997o?;<310?133ty:594?:3y>572=i916oi4<8:p525=839p1<<::66894442h:01<<=:668yv7>;3:1>v3>238b4>;dj3937p}>7383>6}:9;91;9521339e5=:9;:1;95rs0;1>5<5s4;9<7o?;<a:>6><uz;<<7>53z?264<0<27:=k4n0:?25`<0<2wx=4?50;0x947b2h:01n95399~w40a2908w0?>f;57?876l3k;70?>c;57?xu6190;6?u210a9e5=:k<0846s|17g94?5|58;o6::4=03a>d6<58;j6::4}r3;b?6=:r7:=l4n0:?`7?5?3ty::i4?:2y>54d=?=16=<75a19>54>=?=1v<6k:18187603k;70li:2:8yv71k3:1?v3>18840>;69>0j<63>17840>{t91i1<7<t=035>d6<5kn1?55rs04a>5<4s4;:;79;;<321?g734;:879;;|q2<g<72;q6=<:5a19>fg<402wx=;o50;1x94722>>01<?<:`2894752>>0q~?7a;296~;69;0j<63m9;1;?xu6>00;6>u2101931=:98;1m=52102931=z{8226=4={<324?g734h<6>64}r35<?6=;r7:=<484:?24c<f827:<h484:p5=>=838p1<>j:`289g3=;11v<88:180877n3=?70??d;c3?877k3=?7p}>8683>7}:99i1m=52b280<>{t9??1<7=t=02g>22<58:i6l>4=02b>22<uz;3:7>52z?24d<f827i=7=7;|q221<72:q6==l5759>55?=i916==65759~w4>22909w0??8;c3?8ga2:20q~?93;297~;6800<863>068b4>;68?0<86s|19694?4|58:=6l>4=`f97==z{8<96=4<{<333?1334;;97o?;<330?133ty:m;4?:3y>552=i916j<4<8:p537=839p1<>::66894642h:01<>=:668yv7f=3:1>v3>038b4>;bn3937p}>6183>6}:9991;9521139e5=:99:1;95rs0c7>5<5s4;;<7o?;<gg>6><uz;>j7>53z?244<0<27mj7o?;<df>22<uz;j?7>52z?ea?g734oi6>64}r36a?6=;r7mj79;;<dg>d6<5oi1;95rs0c1>5<5s4lh6l>4=d;97==z{8?o6=4<{<dg>22<5oh1m=52f`840>{t9h;1<7<t=gc9e5=:m>0846s|14a94?5|5oh1;952f88b4>;a03=?7p}>a183>7}:n10j<63j5;1;?xu6=h0;6>u2f8840>;a?3k;70h9:668yv7>13:1>v3i6;c3?8b02:20q~?:9;297~;a?3=?70h::`289c2=?=1v<6j:1818`32h:01n?5399~w43?2908w0h::6689c5=i916j?484:p5=5=838p1k<5a19>eg<402wx=5<50;0x94g?21;01<h::`28yv7e:3:1>v3>f4840>;6j?0256s|1g494?4|58kj6474=0`4>=0<uz;m;7>52z?2eg<>127:n8476:p5c>=838p1<ol:8;894d02190q~?i9;296~;6im02563>b48;7>{t9ok1<7<t=0cf><?<58h<65;4}r3ef?6=:r7:mk469:?2f0<?=2wx=km50;0x94d720301<l8:968yv7al3:1>v3>b08:=>;6j<0386s|1`;94??|58h86474=0gb>d7<58o<6l?4=0g0>d7<58nm6l?4=0fa>d7<58n<6l?4=0f0>d7<58im6l?4}r036?6=;r7:hk4n0:?2a5<?927:n;472:p655=83>p1<k<:`2894c321;01<l::93894d021;0q~<?4;290~;6m>0j<63>e98;5>;6j<03>63>b68;6>{t:9?1<7=t=0gb>d6<58oi65?4=0`5>=5<uz8;=7>5az?2f4<?<27:n=474:?2ec<?<27:mh474:?2ea<?<27:mn474:?2eg<?<27:ml474:?2`g<f827:hn471:p656=83kp1<l>:91894d721901<oi:91894gb21901<ok:91894gd21901<om:91894gf21901<j8:`2894b?21;0q~?if;29e~;6j803>63>b18;6>;6io03>63>ad8;6>;6im03>63>ab8;6>;6ik03>63>a`8;6>;6l:0j<63>d58;5>{t9oo1<7ot=0`2>=7<58h;65?4=0ce>=7<58kn65?4=0cg>=7<58kh65?4=0ca>=7<58kj65?4=0ae>d6<58n;65?4}r3`2?6=:r7:ok484:?2`4<>12wx=oh50;1x94b52:k01<j::2c894eb21k0q~?l7;296~;6l:0<863>d48:=>{t9j:1<7=t=0f5>6g<58n26>o4=0f1>=g<uz;h47>52z?2`2<0<27:h4469:p5f7=839p1<jn:2c894bc2:k01<j9:9c8yv7d13:1>v3>dc840>;6lm0256s|1b094?5|58nn6>o4=0g2>6g<58nj65o4}r3`e?6=:r7:hk484:?2a4<>12wx=n=50;1x94c52:k01<k::2c894bb21k0q~?lb;296~;6m:0<863>e48:=>{t9j>1<7=t=0g5>6g<58o26>o4=0g1>=g<uz;ho7>52z?2a2<0<27:i4469:p5f3=838p1<kl:2c894c121k0q~?ld;296~;6mh0<863>eb8:=>{t9ln1<7=t=0f3><?<58in6l<4=0f2>=?<uz;ni7>53z?2`1<>127:h?4n2:?2`0<?12wx=hh50;1x94b?20301<j9:`0894b>2130q~?i0;297~;6lj02563>d`8b6>;6lm0356s|1g394?5|58o;6474=0ff>d4<58o:6574}r3e6?6=;r7:i9469:?2a7<f:27:i8479:p5c5=839p1<k7:8;894c12h801<k6:9;8yv7a<3:1>v3>ec8:=>;6mj0356s|1c694?4|58h>6474=0`5>=3<uz;i97>52z?2f2<>127:n;474:p5g1=838p1<l7:8;894db21;0q~?m8;296~;6j002563>bd8;6>{t9k31<7<t=0`b><?<58hn65=4}r3ae?6=:r7:no469:?2f`<?<2wx=ol50;0x94dd20301<lj:978yv7ek3:1>v3>be8:=>;6jl03:6s|1cf94?4|58hn6474=0`5>=7<utd?;94?:0yK65d<ug><97>51zJ14g=zf===6=4>{I03f>{i<>=1<7?tH32a?xh3?10;6<uG21`8yk2013:1=vF=0c9~j11f290:wE<?b:m02d=83;pD?>m;|l73f<728qC>=l4}o64`?6=9rB9<o5rn55f>5<6sA8;n6sa46d94?7|@;:i7p`;8183>4}O:9h0qc:71;295~N58k1vb96=:182M47j2we85=50;3xL76e3td?494?:0yK65d<ug>397>51zJ14g=zf=2=6=4>{I03f>{i<1=1<7?tH32a?xh3010;6<uG21`8yk2?13:1=vF=0c9~j1>f290:wE<?b:m0=d=83;pD?>m;|l7<f<728qC>=l4}o6;`?6=9rB9<o5rn5:f>5<6sA8;n6sa49d94?7|@;:i7p`;9183>4}O:9h0qc:61;295~N58k1vb97=:182M47j2we84=50;3xL76e3td?594?:0yK65d<ug>297>51zJ14g=zf=3=6=4>{I03f>\f?3;p;:4rZ6f95~g02twe84950;3xL76e3td?554?:0yK65d<ug>257>51zJ14g=zf=3j6=4>{I03f>{i<0h1<7?tH32a?xh31j0;6<uG21`8yk2>l3:1=vF=0c9~j1?b290:wE<?b:m0<`=83;pD?>m;|l7e5<728qC>=l4}o6b5?6=9rB9<o5rn5c1>5<6sA8;n6sa4`194?7|@;:i7p`;a583>4}O:9h0qc:n5;295~N58k1vb9o9:182M47j2we8l950;3xL76e3td?m54?:0yK65d<ug>j57>51zJ14g=zf=kj6=4>{I03f>{i<hh1<7?tH32a?xh3ij0;6<uG21`8yk2fl3:1=vF=0c9~j1gb290:wE<?b:m0d`=83;pD?>m;|l7f5<728qC>=l4}o6a5?6=9rB9<o5rn5`1>5<6sA8;n6sa4c194?7|@;:i7p`;b583>4}O:9h0qc:m5;295~N58k1vb9l9:182M47j2we8o950;3xL76e3td?n54?:0yK65d<ug>i57>51zJ14g=zf=hj6=4>{I03f>{i<kh1<7?tH32a?xh3jj0;6<uG21`8yk2el3:1=vF=0c9~j1db290:wE<?b:m0g`=83;pD?>m;|l7g5<728qC>=l4}o6`5?6=9rB9<o5rn5a1>5<6sA8;n6sa4b194?7|@;:i7p`;c583>4}O:9h0qc:l5;295~N58k1vb9m9:182M47j2we8n950;3xL76e3td?o54?:0yK65d<ug>h57>51zJ14g=zf=ij6=4>{I03f>{i<jh1<7?tH32a?xh3kj0;6<uG21`8yk2dl3:1=vF=0c9~j1eb290:wE<?b:m0f`=83;pD?>m;|l7`5<728qC>=l4}o6g5?6=9rB9<o5rn5f1>5<6sA8;n6sa4e194?7|@;:i7p`;d583>4}O:9h0qc:k5;295~N58k1vb9j9:182M47j2we8i950;3xL76e3td?h54?:0yK65d<ug>o57>51zJ14g=zf=nj6=4>{I03f>{i<mh1<7?tH32a?xh3lj0;6<uG21`8yk2cl3:1=vF=0c9~j1bb290:wE<?b:m0a`=83;pD?>m;|l7a5<728qC>=l4}o6f5?6=9rB9<o5rn5g1>5<6sA8;n6sa4d194?7|@;:i7p`;e583>4}O:9h0qc:j5;295~N58k1vb9k9:182M47j2we8h950;3xL76e3td?i54?:0yK65d<ug>n57>51zJ14g=zf=oj6=4>{I03f>{i<lh1<7?tH32a?xh3mj0;6<uG21`8yk2bl3:1=vF=0c9~j1cb290:wE<?b:m0``=83;pD?>m;|l7b5<728qC>=l4}o6e5?6=9rB9<o5rn5d1>5<6sA8;n6sa4g194?7|@;:i7p`;f583>4}O:9h0qc:i5;295~N58k1vb9h9:182M47j2we8k950;3xL76e3td?j54?:0yK65d<ug>m57>51zJ14g=zf=lj6=4>{I03f>{i<oh1<7?tH32a?xh3nj0;6<uG21`8yk2al3:1=vF=0c9~j1`b290:wE<?b:m0c`=83;pD?>m;|l645<728qC>=l4}o735?6=9rB9<o5rn421>5<6sA8;n6sa51194?7|@;:i7p`:0583>4}O:9h0qc;?5;295~N58k1vb8>9:182M47j2we9=950;3xL76e3td><54?:0yK65d<ug?;57>51zJ14g=zf<:j6=4>{I03f>{i=9h1<7?tH32a?xh28j0;6<uG21`8yk37l3:1=vF=0c9~j06b290:wE<?b:m15`=83;pD?>m;|l655<728qC>=l4}o725?6=9rB9<o5rn431>5<6sA8;n6sa50194?7|@;:i7p`:1583>4}O:9h0qc;>5;295~N58k1vb8?9:182M47j2we9<950;3xL76e3td>=54?:0yK65d<ug?:57>51zJ14g=zf<;j6=4>{I03f>{i=8h1<7?tH32a?xh29j0;6<uG21`8yk36l3:1=vF=0c9~j07b290:wE<?b:m14`=83;pD?>m;|l665<728qC>=l4}o715?6=9rB9<o5rn401>5<6sA8;n6sa53194?7|@;:i7p`:2583>4}O:9h0qc;=5;295~N58k1vb8<9:182M47j2we9?950;3xL76e3td>>54?:0yK65d<ug?957>51zJ14g=zf<8j6=4>{I03f>{i=;h1<7?tH32a?xh2:j0;6<uG21`8yk35l3:1=vF=0c9~j04b290:wE<?b:m17`=83;pD?>m;|l675<728qC>=l4}o705?6=9rB9<o5rn411>5<6sA8;n6sa52194?7|@;:i7p`:3583>4}O:9h0qc;<5;295~N58k1vb8=9:182M47j2we9>950;3xL76e3td>?54?:0yK65d<ug?857>51zJ14g=zf<9j6=4>{I03f>{i=:h1<7?tH32a?xh2;j0;6<uG21`8yk34l3:1=vF=0c9~j05b290:wE<?b:m16`=83;pD?>m;|l605<728qC>=l4}o775?6=9rB9<o5rn461>5<6sA8;n6sa55194?7|@;:i7p`:4583>4}O:9h0qc;;5;295~N58k1vb8:9:182M47j2we99950;3xL76e3td>854?:0yK65d<ug??57>51zJ14g=zf<>j6=4>{I03f>{i==h1<7?tH32a?xh2<j0;6<uG21`8yk33l3:1=vF=0c9~j02b290:wE<?b:m11`=83;pD?>m;|l615<728qC>=l4}o765?6=9rB9<o5rn471>5<6sA8;n6sa54194?7|@;:i7p`:5583>4}O:9h0qc;:5;295~N58k1vb8;9:182M47j2we98950;3xL76e3td>954?:0yK65d<ug?>57>51zJ14g=zf<?j6=4>{I03f>{i=<h1<7?tH32a?xh2=j0;6<uG21`8yk32l3:1=vF=0c9~j03b290:wE<?b:m10`=83;pD?>m;|~yEFDs?>h6n:8810e4xFGJr:vLM^t}AB
\ No newline at end of file
diff --git a/FEE_ADC32board/project/ipcore_dir/vio36.vhd b/FEE_ADC32board/project/ipcore_dir/vio36.vhd
deleted file mode 100644
index 1c1e87b..0000000
--- a/FEE_ADC32board/project/ipcore_dir/vio36.vhd
+++ /dev/null
@@ -1,30 +0,0 @@
--------------------------------------------------------------------------------
--- Copyright (c) 2012 Xilinx, Inc.
--- All Rights Reserved
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor     : Xilinx
--- \   \   \/     Version    : 13.3
---  \   \         Application: XILINX CORE Generator
---  /   /         Filename   : vio36.vhd
--- /___/   /\     Timestamp  : Mon Jul 23 15:40:25 W. Europe Daylight Time 2012
--- \   \  /  \
---  \___\/\___\
---
--- Design Name: VHDL Synthesis Wrapper
--------------------------------------------------------------------------------
--- This wrapper is used to integrate with Project Navigator and PlanAhead
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-ENTITY vio36 IS
-  port (
-    CONTROL: inout std_logic_vector(35 downto 0);
-    ASYNC_OUT: out std_logic_vector(35 downto 0));
-END vio36;
-
-ARCHITECTURE vio36_a OF vio36 IS
-BEGIN
-
-END vio36_a;
diff --git a/FEE_ADC32board/project/ipcore_dir/vio36.vho b/FEE_ADC32board/project/ipcore_dir/vio36.vho
deleted file mode 100644
index 8845694..0000000
--- a/FEE_ADC32board/project/ipcore_dir/vio36.vho
+++ /dev/null
@@ -1,38 +0,0 @@
--------------------------------------------------------------------------------
--- Copyright (c) 2012 Xilinx, Inc.
--- All Rights Reserved
--------------------------------------------------------------------------------
---   ____  ____
---  /   /\/   /
--- /___/  \  /    Vendor     : Xilinx
--- \   \   \/     Version    : 13.3
---  \   \         Application: Xilinx CORE Generator
---  /   /         Filename   : vio36.vho
--- /___/   /\     Timestamp  : Mon Jul 23 15:40:25 W. Europe Daylight Time 2012
--- \   \  /  \
---  \___\/\___\
---
--- Design Name: ISE Instantiation template
--- Component Identifier: xilinx.com:ip:chipscope_vio:1.05.a
--------------------------------------------------------------------------------
--- The following code must appear in the VHDL architecture header:
-
-------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
-component vio36
-  PORT (
-    CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
-    ASYNC_OUT : OUT STD_LOGIC_VECTOR(35 DOWNTO 0));
-
-end component;
-
--- COMP_TAG_END ------ End COMPONENT Declaration ------------
--- The following code must appear in the VHDL architecture
--- body. Substitute your own instance name and net names.
-------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
-
-your_instance_name : vio36
-  port map (
-    CONTROL => CONTROL,
-    ASYNC_OUT => ASYNC_OUT);
-
--- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/FEE_ADC32board/project/ipcore_dir/vio36.xco b/FEE_ADC32board/project/ipcore_dir/vio36.xco
deleted file mode 100644
index 04fcaec..0000000
--- a/FEE_ADC32board/project/ipcore_dir/vio36.xco
+++ /dev/null
@@ -1,56 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 13.3
-# Date: Mon Jul 23 13:39:49 2012
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:chipscope_vio:1.05.a
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6vlx130t
-SET devicefamily = virtex6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = ff484
-SET removerpms = false
-SET simulationfiles = Structural
-SET speedgrade = -3
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT VIO_(ChipScope_Pro_-_Virtual_Input/Output) family Xilinx,_Inc. 1.05.a
-# END Select
-# BEGIN Parameters
-CSET asynchronous_input_port_width=8
-CSET asynchronous_output_port_width=36
-CSET component_name=vio36
-CSET constraint_type=embedded
-CSET enable_asynchronous_input_port=false
-CSET enable_asynchronous_output_port=true
-CSET enable_synchronous_input_port=false
-CSET enable_synchronous_output_port=false
-CSET example_design=false
-CSET invert_clock_input=false
-CSET synchronous_input_port_width=8
-CSET synchronous_output_port_width=8
-# END Parameters
-GENERATE
-# CRC: f58807c1
diff --git a/FEE_ADC32board/project/ipcore_dir/vio36.xise b/FEE_ADC32board/project/ipcore_dir/vio36.xise
deleted file mode 100644
index 0cbd773..0000000
--- a/FEE_ADC32board/project/ipcore_dir/vio36.xise
+++ /dev/null
@@ -1,72 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="vio36.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
-    <file xil_pn:name="vio36.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|vio36|vio36_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="vio36.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/vio36" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="ff484" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="vio36" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-07-23T15:40:35" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6A1216FFFD084649B921E416A2F662FE" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FEE_ADC32board/project/ipcore_dir/vio36_readme.txt b/FEE_ADC32board/project/ipcore_dir/vio36_readme.txt
deleted file mode 100644
index e02d82e..0000000
--- a/FEE_ADC32board/project/ipcore_dir/vio36_readme.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-The following files were generated for 'vio36' in directory
-D:\Xilinx_proj\Panda\Xilinx\FrontEndElectronics\FEE_test_ADC32\ipcore_dir\
-
-XCO file generator:
-   Generate an XCO file for compatibility with legacy flows.
-
-   * vio36.xco
-
-Creates an implementation netlist:
-   Creates an implementation netlist for the IP.
-
-   * vio36.cdc
-   * vio36.ngc
-   * vio36.vhd
-   * vio36.vho
-
-Creates an HDL instantiation template:
-   Creates an HDL instantiation template for the IP.
-
-   * vio36.vho
-
-IP Symbol Generator:
-   Generate an IP symbol based on the current project options'.
-
-   * vio36.asy
-
-SYM file generator:
-   Generate a SYM file for compatibility with legacy flows
-
-   * vio36.sym
-
-Generate ISE metadata:
-   Create a metadata file for use when including this core in ISE designs
-
-   * vio36_xmdf.tcl
-
-Generate ISE subproject:
-   Create an ISE subproject for use when including this core in ISE designs
-
-   * _xmsgs/pn_parser.xmsgs
-   * vio36.gise
-   * vio36.xise
-
-Deliver Readme:
-   Readme file for the IP.
-
-   * vio36_readme.txt
-
-Generate FLIST file:
-   Text file listing all of the output files produced when a customized core was
-   generated in the CORE Generator.
-
-   * vio36_flist.txt
-
-Please see the Xilinx CORE Generator online help for further details on
-generated files and how to use them.
-
diff --git a/FEE_ADC32board/project/iseconfig/FEE_ADC32board.projectmgr b/FEE_ADC32board/project/iseconfig/FEE_ADC32board.projectmgr
deleted file mode 100644
index e1a8d03..0000000
--- a/FEE_ADC32board/project/iseconfig/FEE_ADC32board.projectmgr
+++ /dev/null
@@ -1,97 +0,0 @@
-<?xml version='1.0' encoding='utf-8'?>
-<!--This is an ISE project configuration file.-->
-<!--It holds project specific layout data for the projectmgr plugin.-->
-<!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
-<Project version="2" owner="projectmgr" name="FEE_ADC32board" >
-   <!--This is an ISE project configuration file.-->
-   <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
-      <ClosedNodes>
-         <ClosedNodesVersion>2</ClosedNodesVersion>
-         <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel1458_2 - AdcToplevel - AdcToplevel_struct</ClosedNode>
-         <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel1458_3 - AdcToplevel - AdcToplevel_struct</ClosedNode>
-         <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel1458_4 - AdcToplevel - AdcToplevel_struct</ClosedNode>
-         <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_1 - AdcToplevel - AdcToplevel_struct</ClosedNode>
-         <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_2 - AdcToplevel - AdcToplevel_struct</ClosedNode>
-         <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_3 - AdcToplevel - AdcToplevel_struct</ClosedNode>
-         <ClosedNode>/top - Behavioral D:|Project|Panda|GIT|FEE_ADC32board|project|FEE_ADC32board_top.vhd/FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral/AdcToplevel2356_4 - AdcToplevel - AdcToplevel_struct</ClosedNode>
-      </ClosedNodes>
-      <SelectedItems>
-         <SelectedItem>FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral (D:/Project/Panda/GIT/FEE_ADC32board/modules/FEE_ADCinput_module.vhd)</SelectedItem>
-      </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000487000000020000000000000000000000000200000064ffffffff000000810000000300000002000004870000000100000003000000000000000100000003</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
-      <CurrentItem>FEE_ADCinput_module1 - FEE_ADCinput_module - Behavioral (D:/Project/Panda/GIT/FEE_ADC32board/modules/FEE_ADCinput_module.vhd)</CurrentItem>
-   </ItemView>
-   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-         <ClosedNode>Configure Target Device</ClosedNode>
-         <ClosedNode>Design Utilities</ClosedNode>
-         <ClosedNode>Implement Design</ClosedNode>
-         <ClosedNode>Synthesize - XST</ClosedNode>
-         <ClosedNode>User Constraints</ClosedNode>
-      </ClosedNodes>
-      <SelectedItems>
-         <SelectedItem></SelectedItem>
-      </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002ba000000010000000100000000000000000000000064ffffffff000000810000000000000001000002ba0000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem></CurrentItem>
-   </ItemView>
-   <ItemView guiview="File" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-      </ClosedNodes>
-      <SelectedItems/>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000003ce000000040101000100000000000000000000000064ffffffff0000008100000000000000040000022d0000000100000000000000d70000000100000000000000660000000100000000000000640000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem>D:\Project\Panda\GIT\FEE_ADC32board\FEE_modules\blockmem.vhd</CurrentItem>
-   </ItemView>
-   <ItemView guiview="Library" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-         <ClosedNode>work</ClosedNode>
-      </ClosedNodes>
-      <SelectedItems/>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem>work</CurrentItem>
-   </ItemView>
-   <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-         <ClosedNode>Design Utilities</ClosedNode>
-      </ClosedNodes>
-      <SelectedItems>
-         <SelectedItem/>
-      </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002ba000000010000000100000000000000000000000064ffffffff000000810000000000000001000002ba0000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem/>
-   </ItemView>
-   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_PACKAGE_DECL" guiview="Process" >
-      <ClosedNodes>
-         <ClosedNodesVersion>1</ClosedNodesVersion>
-      </ClosedNodes>
-      <SelectedItems>
-         <SelectedItem/>
-      </SelectedItems>
-      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
-      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000002ba000000010000000100000000000000000000000064ffffffff000000810000000000000001000002ba0000000100000000</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem/>
-   </ItemView>
-   <SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
-   <CurrentView>Implementation</CurrentView>
-</Project>
diff --git a/FEE_ADC32board/project/iseconfig/FEE_adc32_module.xreport b/FEE_ADC32board/project/iseconfig/FEE_adc32_module.xreport
deleted file mode 100644
index c126e5c..0000000
--- a/FEE_ADC32board/project/iseconfig/FEE_adc32_module.xreport
+++ /dev/null
@@ -1,215 +0,0 @@
-<?xml version='1.0' encoding='UTF-8'?>
-<report-views version="2.0" >
- <header>
-  <DateModified>2014-12-11T14:19:21</DateModified>
-  <ModuleName>top</ModuleName>
-  <SummaryTimeStamp>Unknown</SummaryTimeStamp>
-  <SavedFilePath>D:/Project/Panda/GIT/FEE_ADC32board/project/iseconfig/FEE_adc32_module.xreport</SavedFilePath>
-  <ImplementationReportsDirectory>D:/Project/Panda/GIT/FEE_ADC32board/project</ImplementationReportsDirectory>
-  <DateInitialized>2014-12-11T14:19:21</DateInitialized>
-  <EnableMessageFiltering>true</EnableMessageFiltering>
- </header>
- <body>
-  <viewgroup label="Design Overview" >
-   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="top_summary.html" label="Summary" >
-    <toc-item title="Design Overview" target="Design Overview" />
-    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
-    <toc-item title="Performance Summary" target="Performance Summary" />
-    <toc-item title="Failing Constraints" target="Failing Constraints" />
-    <toc-item title="Detailed Reports" target="Detailed Reports" />
-   </view>
-   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="top_envsettings.html" label="System Settings" />
-   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="top_map.xrpt" label="IOB Properties" />
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="top_map.xrpt" label="Control Set Information" />
-   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="top_map.xrpt" label="Module Level Utilization" />
-   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="top.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
-   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="top_par.xrpt" label="Pinout Report" />
-   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="top_par.xrpt" label="Clock Report" />
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="top.twx" label="Static Timing" />
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="top_html/fit/report.htm" label="CPLD Fitter Report" />
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="top_html/tim/report.htm" label="CPLD Timing Report" />
-  </viewgroup>
-  <viewgroup label="XPS Errors and Warnings" >
-   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
-   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
-   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
-  </viewgroup>
-  <viewgroup label="XPS Reports" >
-   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
-   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
-   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
-   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="top.log" label="System Log File" />
-  </viewgroup>
-  <viewgroup label="Errors and Warnings" >
-   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
-   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
-   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
-   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
-   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
-   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
-   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
-   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
-   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
-   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
-   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
-  </viewgroup>
-  <viewgroup label="Detailed Reports" >
-   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="top.syr" label="Synthesis Report" >
-    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
-    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
-    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
-    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
-    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
-    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
-    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
-    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
-    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
-    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
-    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
-    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
-    <toc-item title="Partition Report" target="   Partition Report     " />
-    <toc-item title="Final Report" target="   Final Report   " />
-    <toc-item title="Design Summary" target="   Design Summary   " />
-    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
-    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
-    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
-    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
-    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
-    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
-    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
-    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
-    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
-   </view>
-   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="top.srr" label="Synplify Report" />
-   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="top.prec_log" label="Precision Report" />
-   <view inputState="Synthesized" program="ngdbuild" type="Report" file="top.bld" label="Translation Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Command Line" target="Command Line:" />
-    <toc-item title="Partition Status" target="Partition Implementation Status" />
-    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
-   </view>
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="top_map.mrp" label="Map Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
-    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
-    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
-    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
-    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
-    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
-    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
-    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
-    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
-    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
-    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
-    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
-    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="top.par" label="Place and Route Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
-    <toc-item title="Router Information" target="Starting Router" />
-    <toc-item title="Partition Status" target="Partition Implementation Status" />
-    <toc-item title="Clock Report" target="Generating Clock Report" />
-    <toc-item title="Timing Results" target="Timing Score:" />
-    <toc-item title="Final Summary" target="Peak Memory Usage:" />
-   </view>
-   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="top.twr" label="Post-PAR Static Timing Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Timing Report Description" target="Device,package,speed:" />
-    <toc-item title="Informational Messages" target="INFO:" />
-    <toc-item title="Warning Messages" target="WARNING:" />
-    <toc-item title="Timing Constraints" target="Timing constraint:" />
-    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
-    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
-    <toc-item title="Timing Summary" target="Timing summary:" />
-    <toc-item title="Trace Settings" target="Trace Settings:" />
-   </view>
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.rpt" label="CPLD Fitter Report (Text)" >
-    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
-    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
-    <toc-item title="Pin Resources" target="** Pin Resources **" />
-    <toc-item title="Global Resources" target="** Global Control Resources **" />
-   </view>
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.tim" label="CPLD Timing Report (Text)" >
-    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
-    <toc-item title="Performance Summary" target="Performance Summary:" />
-   </view>
-   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="top.pwr" label="Power Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Power summary" target="Power summary" />
-    <toc-item title="Thermal summary" target="Thermal summary" />
-   </view>
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="top.bgn" label="Bitgen Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
-    <toc-item title="Final Summary" target="DRC detected" />
-   </view>
-  </viewgroup>
-  <viewgroup label="Secondary Reports" >
-   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
-   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/top_translate.nlf" label="Post-Translate Simulation Model Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top_map.map" label="Map Log File" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-    <toc-item title="Design Information" target="Design Information" />
-    <toc-item title="Design Summary" target="Design Summary" />
-   </view>
-   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
-   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_preroute.twr" label="Post-Map Static Timing Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Timing Report Description" target="Device,package,speed:" />
-    <toc-item title="Informational Messages" target="INFO:" />
-    <toc-item title="Warning Messages" target="WARNING:" />
-    <toc-item title="Timing Constraints" target="Timing constraint:" />
-    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
-    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
-    <toc-item title="Timing Summary" target="Timing summary:" />
-    <toc-item title="Trace Settings" target="Trace Settings:" />
-   </view>
-   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/top_map.nlf" label="Post-Map Simulation Model Report" />
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_map.psr" label="Physical Synthesis Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="top_pad.txt" label="Pad Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top.unroutes" label="Unroutes Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_preroute.tsi" label="Post-Map Constraints Interaction Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.grf" label="Guide Results Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.dly" label="Asynchronous Delay Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.clk_rgn" label="Clock Region Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.tsi" label="Post-Place and Route Constraints Interaction Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
-   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/top_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_sta.nlf" label="Primetime Netlist Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="top.ibs" label="IBIS Model" >
-    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
-    <toc-item title="Component" target="Component " />
-   </view>
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lck" label="Back-annotate Pin Report" >
-    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
-    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
-   </view>
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lpc" label="Locked Pin Constraints" >
-    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
-    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
-   </view>
-   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/top_timesim.nlf" label="Post-Fit Simulation Model Report" />
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
-  </viewgroup>
- </body>
-</report-views>
diff --git a/FEE_ADC32board/project/iseconfig/top.xreport b/FEE_ADC32board/project/iseconfig/top.xreport
deleted file mode 100644
index e036599..0000000
--- a/FEE_ADC32board/project/iseconfig/top.xreport
+++ /dev/null
@@ -1,215 +0,0 @@
-<?xml version='1.0' encoding='UTF-8'?>
-<report-views version="2.0" >
- <header>
-  <DateModified>2014-12-11T14:50:59</DateModified>
-  <ModuleName>top</ModuleName>
-  <SummaryTimeStamp>Unknown</SummaryTimeStamp>
-  <SavedFilePath>D:/Project/Panda/GIT/FEE_ADC32board/project/iseconfig/top.xreport</SavedFilePath>
-  <ImplementationReportsDirectory>D:/Project/Panda/GIT/FEE_ADC32board/project\</ImplementationReportsDirectory>
-  <DateInitialized>2014-12-11T14:33:13</DateInitialized>
-  <EnableMessageFiltering>true</EnableMessageFiltering>
- </header>
- <body>
-  <viewgroup label="Design Overview" >
-   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="top_summary.html" label="Summary" >
-    <toc-item title="Design Overview" target="Design Overview" />
-    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
-    <toc-item title="Performance Summary" target="Performance Summary" />
-    <toc-item title="Failing Constraints" target="Failing Constraints" />
-    <toc-item title="Detailed Reports" target="Detailed Reports" />
-   </view>
-   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="top_envsettings.html" label="System Settings" />
-   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="top_map.xrpt" label="IOB Properties" />
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="top_map.xrpt" label="Control Set Information" />
-   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="top_map.xrpt" label="Module Level Utilization" />
-   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="top.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
-   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="top_par.xrpt" label="Pinout Report" />
-   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="top_par.xrpt" label="Clock Report" />
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="top.twx" label="Static Timing" />
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="top_html/fit/report.htm" label="CPLD Fitter Report" />
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="top_html/tim/report.htm" label="CPLD Timing Report" />
-  </viewgroup>
-  <viewgroup label="XPS Errors and Warnings" >
-   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
-   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
-   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
-  </viewgroup>
-  <viewgroup label="XPS Reports" >
-   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
-   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
-   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
-   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="top.log" label="System Log File" />
-  </viewgroup>
-  <viewgroup label="Errors and Warnings" >
-   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
-   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
-   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
-   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
-   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
-   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
-   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
-   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
-   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
-   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
-   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
-  </viewgroup>
-  <viewgroup label="Detailed Reports" >
-   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="top.syr" label="Synthesis Report" >
-    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
-    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
-    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
-    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
-    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
-    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
-    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
-    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
-    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
-    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
-    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
-    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
-    <toc-item title="Partition Report" target="   Partition Report     " />
-    <toc-item title="Final Report" target="   Final Report   " />
-    <toc-item title="Design Summary" target="   Design Summary   " />
-    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
-    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
-    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
-    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
-    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
-    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
-    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
-    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
-    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
-   </view>
-   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="top.srr" label="Synplify Report" />
-   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="top.prec_log" label="Precision Report" />
-   <view inputState="Synthesized" program="ngdbuild" type="Report" file="top.bld" label="Translation Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Command Line" target="Command Line:" />
-    <toc-item title="Partition Status" target="Partition Implementation Status" />
-    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
-   </view>
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="top_map.mrp" label="Map Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
-    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
-    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
-    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
-    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
-    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
-    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
-    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
-    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
-    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
-    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
-    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
-    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="top.par" label="Place and Route Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
-    <toc-item title="Router Information" target="Starting Router" />
-    <toc-item title="Partition Status" target="Partition Implementation Status" />
-    <toc-item title="Clock Report" target="Generating Clock Report" />
-    <toc-item title="Timing Results" target="Timing Score:" />
-    <toc-item title="Final Summary" target="Peak Memory Usage:" />
-   </view>
-   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="top.twr" label="Post-PAR Static Timing Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Timing Report Description" target="Device,package,speed:" />
-    <toc-item title="Informational Messages" target="INFO:" />
-    <toc-item title="Warning Messages" target="WARNING:" />
-    <toc-item title="Timing Constraints" target="Timing constraint:" />
-    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
-    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
-    <toc-item title="Timing Summary" target="Timing summary:" />
-    <toc-item title="Trace Settings" target="Trace Settings:" />
-   </view>
-   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.rpt" label="CPLD Fitter Report (Text)" >
-    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
-    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
-    <toc-item title="Pin Resources" target="** Pin Resources **" />
-    <toc-item title="Global Resources" target="** Global Control Resources **" />
-   </view>
-   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="top.tim" label="CPLD Timing Report (Text)" >
-    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
-    <toc-item title="Performance Summary" target="Performance Summary:" />
-   </view>
-   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="top.pwr" label="Power Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Power summary" target="Power summary" />
-    <toc-item title="Thermal summary" target="Thermal summary" />
-   </view>
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="top.bgn" label="Bitgen Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
-    <toc-item title="Final Summary" target="DRC detected" />
-   </view>
-  </viewgroup>
-  <viewgroup label="Secondary Reports" >
-   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
-   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/top_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/top_translate.nlf" label="Post-Translate Simulation Model Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
-   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top_map.map" label="Map Log File" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-    <toc-item title="Design Information" target="Design Information" />
-    <toc-item title="Design Summary" target="Design Summary" />
-   </view>
-   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
-   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_preroute.twr" label="Post-Map Static Timing Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-    <toc-item title="Timing Report Description" target="Device,package,speed:" />
-    <toc-item title="Informational Messages" target="INFO:" />
-    <toc-item title="Warning Messages" target="WARNING:" />
-    <toc-item title="Timing Constraints" target="Timing constraint:" />
-    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
-    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
-    <toc-item title="Timing Summary" target="Timing summary:" />
-    <toc-item title="Trace Settings" target="Trace Settings:" />
-   </view>
-   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/top_map.nlf" label="Post-Map Simulation Model Report" />
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_map.psr" label="Physical Synthesis Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="top_pad.txt" label="Pad Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="top.unroutes" label="Unroutes Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top_preroute.tsi" label="Post-Map Constraints Interaction Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.grf" label="Guide Results Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.dly" label="Asynchronous Delay Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.clk_rgn" label="Clock Region Report" />
-   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.tsi" label="Post-Place and Route Constraints Interaction Report" >
-    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
-   </view>
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
-   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/top_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
-   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="top_sta.nlf" label="Primetime Netlist Report" >
-    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
-   </view>
-   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="top.ibs" label="IBIS Model" >
-    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
-    <toc-item title="Component" target="Component " />
-   </view>
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lck" label="Back-annotate Pin Report" >
-    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
-    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
-   </view>
-   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="top.lpc" label="Locked Pin Constraints" >
-    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
-    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
-   </view>
-   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/top_timesim.nlf" label="Post-Fit Simulation Model Report" />
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
-   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
-  </viewgroup>
- </body>
-</report-views>
diff --git a/FEE_ADC32board/project/top.bit b/FEE_ADC32board/project/top.bit
deleted file mode 100644
index bfb5799..0000000
Binary files a/FEE_ADC32board/project/top.bit and /dev/null differ
diff --git a/SODA_addressmap b/SODA_addressmap
deleted file mode 100644
index 8940039..0000000
--- a/SODA_addressmap
+++ /dev/null
@@ -1,106 +0,0 @@
-SODA_SOURCE (0xF355)
-++++++++++++++++++++
-WRITE_REG:
-
-BE00			soda_cmd_word_S
-BE01			--
-BE02			--
-BE03			CTRL_STATUS_register_i
-
-READ_REG:
-
-BE00			soda_cmd_word_S
-BE01			super_burst_nr_S
-BE02			calib_register_S
-BE03			CTRL_STATUS_register_i
-
-CONTROL(r/w):
-CTRL_STATUS_register_i[31]		:	soda_reset_S
-CTRL_STATUS_register_i[30]		:	soda_enable_S
-CTRL_STATUS_register_i[29]		:	dead_channel_S
-CTRL_STATUS_register_i[28:16]	:	--
-STATUS(read-only):
-CTRL_STATUS_register_i[15]		:	report_error_S
-CTRL_STATUS_register_i[14:2]	:	--
-CTRL_STATUS_register_i[1]		:	downstream_error_S
-CTRL_STATUS_register_i[0]		:	channel_timeout_status_S
-
-
-SODA_CLIENT	(0xF356)
-++++++++++++++++++++
-WRITE_REG:
-
-BE00			LEDregister_i
-
-READ_REG:
-
-BE00			soda_cmd_word_S
-BE01			super_burst_nr_S
-BE02			LEDregister_i
-BE03			Debug_status
-BE04			Debug_RX_count
-BE05			Debug_TX_count
-BE06			Debug_SOS_count
-BE07			Debug_CMD_count
-
-
-Cu_TRB_SODA_HUB	(0xF35B)
-++++++++++++++++++++++++++
-WRITE_REG:
-
-BE00			soda_cmd_word_S
-BE01			CTRL_STATUS_register_S(15 downto 0) channel1
-BE02			CTRL_STATUS_register_S(15 downto 0) channel2
-BE03			CTRL_STATUS_register_S(15 downto 0) channel3
-BE04			CTRL_STATUS_register_S(15 downto 0) channel4
-
-READ_REG:
-
-BE00			'0' & soda_cmd_word_S
-BE01			'0' & superburst_nr_S
-BE04			calib_register_S channel1
-BE05			calib_register_S channel2
-BE06			calib_register_S channel3
-BE07			calib_register_S channel4
-BE08			calib_register_S channel1
-BE09			calib_register_S channel2
-BE10			calib_register_S channel3
-BE11			calib_register_S channel4
-
-CONTROL(r/w):
-CTRL_STATUS_register_i[31]		:	soda_reset_S
-CTRL_STATUS_register_i[30]		:	soda_enable_S
-CTRL_STATUS_register_i[29]		:	dead_channel_S
-CTRL_STATUS_register_i[28:16]	:	--
-STATUS(read-only):
-CTRL_STATUS_register_i[15]		:	report_error_S
-CTRL_STATUS_register_i[14:2]	:	--
-CTRL_STATUS_register_i[1]		:	downstream_error_S
-CTRL_STATUS_register_i[0]		:	channel_timeout_status_S
-
-DEBUG_STATUS(31)		<= send_link_reset_i when rising_edge(SYSCLK);
-DEBUG_STATUS(30)		<= '0';
-DEBUG_STATUS(29)		<= internal_make_link_reset_out when rising_edge(SYSCLK);
-DEBUG_STATUS(28)		<= '0';
-DEBUG_STATUS(27)		<= '0';
-DEBUG_STATUS(26)		<= rx_allow;
-DEBUG_STATUS(25)		<= tx_allow;
-DEBUG_STATUS(24:20)	<= (others => '0');
-DEBUG_STATUS(19:16)	<= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-DEBUG_STATUS(15:3)		<= (others => '0');
-DEBUG_STATUS(2)			<= CLK_EN;
-DEBUG_STATUS(1)			<= CLEAR;
-DEBUG_STATUS(0)			<= RESET;
-
--------------------------------------------------------------------
-constant K_IDLE   : std_logic_vector(7 downto 0) := x"BC";
-constant D_IDLE0  : std_logic_vector(7 downto 0) := x"C5";
-constant D_IDLE1  : std_logic_vector(7 downto 0) := x"50";
-constant K_SOP    : std_logic_vector(7 downto 0) := x"FB";
-constant K_EOP    : std_logic_vector(7 downto 0) := x"FD";
-constant K_BGN    : std_logic_vector(7 downto 0) := x"1C";
-constant K_REQ    : std_logic_vector(7 downto 0) := x"7C";
-constant K_RST    : std_logic_vector(7 downto 0) := x"FE";
-constant K_DLM    : std_logic_vector(7 downto 0) := x"DC";
-
-
diff --git a/SODA_addressmap.odt b/SODA_addressmap.odt
deleted file mode 100644
index c1f671e..0000000
Binary files a/SODA_addressmap.odt and /dev/null differ
diff --git a/SODA_quadsource_addressmap b/SODA_quadsource_addressmap
deleted file mode 100644
index 5a788cb..0000000
--- a/SODA_quadsource_addressmap
+++ /dev/null
@@ -1,70 +0,0 @@
-SODA_QUAD_SOURCE (0xF358)
-+++++++++++++++++++++++++
-WRITE_REG:
-
-BE00			soda_cmd_word_S
-BE01			CTRL_STATUS_register_i[0](15..0)
-BE02			CTRL_STATUS_register_i[1](15..0)
-BE03			CTRL_STATUS_register_i[2](15..0)
-BE04			CTRL_STATUS_register_i[3](15..0)
-
-READ_REG:
-
-BE00			soda_cmd_word_S
-BE01			super_burst_nr_S
-BE04			calib_register_S[0]
-BE05			calib_register_S[1]
-BE06			calib_register_S[2]
-BE07			calib_register_S[3]
-BE08			CTRL_STATUS_register_i[0]
-BE09			CTRL_STATUS_register_i[0]
-BE10			CTRL_STATUS_register_i[0]
-BE11			CTRL_STATUS_register_i[0]
-
-control(read & write):
-CTRL_STATUS_register_i[3..0]	:	LEDs
-CTRL_STATUS_register_i[8]		:	dead_channel
-CTRL_STATUS_register_i[15]		:	reset errors
-status(read-only):
-CTRL_STATUS_register_i[17]		:	timeout-error
-CTRL_STATUS_register_i[18]		:	downstream-error
-CTRL_STATUS_register_i[31]		:	report error
-
-
-SODA_CLIENT	(0xF356)
-++++++++++++++++++++
-WRITE_REG:
-
-BE00			LEDregister_i
-
-READ_REG:
-
-BE00			soda_cmd_word_S
-BE01			super_burst_nr_S
-BE02			LEDregister_i
-BE03			Debug_status
-BE04			Debug_RX_count
-BE05			Debug_TX_count
-BE06			Debug_SOS_count
-BE07			Debug_CMD_count
-
-
-
-
-DEBUG_STATUS(31)		<= send_link_reset_i when rising_edge(SYSCLK);
-DEBUG_STATUS(30)		<= '0';
-DEBUG_STATUS(29)		<= internal_make_link_reset_out when rising_edge(SYSCLK);
-DEBUG_STATUS(28)		<= '0';
-DEBUG_STATUS(27)		<= '0';
-DEBUG_STATUS(26)		<= rx_allow;
-DEBUG_STATUS(25)		<= tx_allow;
-DEBUG_STATUS(24:20)	<= (others => '0');
-DEBUG_STATUS(19:16)	<= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-DEBUG_STATUS(15:3)		<= (others => '0');
-DEBUG_STATUS(2)			<= CLK_EN;
-DEBUG_STATUS(1)			<= CLEAR;
-DEBUG_STATUS(0)			<= RESET;
-
-
-
-
diff --git a/code/Cu_trb3_periph_soda_client.vhd b/code/Cu_trb3_periph_soda_client.vhd
deleted file mode 100644
index b10a703..0000000
--- a/code/Cu_trb3_periph_soda_client.vhd
+++ /dev/null
@@ -1,567 +0,0 @@
----------------
--- TOP LEVEL --
----------------
--- TAB=3 !!
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all; 
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity Cu_trb3_periph_soda_client is
-	generic(
-		SYNC_MODE : integer range 0 to 1 := c_NO;   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
-		USE_125_MHZ : integer := c_NO;
-		CLOCK_FREQUENCY : integer := 100;
-		NUM_INTERFACES : integer := 1
-		);
-	port(
-		--Clocks 
-		CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
-		CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
-		CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-		CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
-		--serdes I/O - connect as you like, no real use
-		CU_SERDES_TX		: out std_logic_vector(3 downto 0);
-		CU_SERDES_RX		: in  std_logic_vector(3 downto 0);
-		SERDES_ADDON_TX	: out std_logic_vector(15 downto 0);
-		SERDES_ADDON_RX	: in  std_logic_vector(15 downto 0);
-		--Inter-FPGA Communication
-		FPGA5_COMM : inout std_logic_vector(11 downto 0);
-																		--Bit 0/1 input, serial link RX active
-																		--Bit 2/3 output, serial link TX active
-																		--others yet undefined
-		--Connection to AddOn
-		LED_LINKOK			: out std_logic_vector(6 downto 1);
-		LED_RX				: out std_logic_vector(6 downto 1); 
-		LED_TX				: out std_logic_vector(6 downto 1);
-		SFP_MOD0				: in  std_logic_vector(6 downto 1);
-		SFP_TXDIS			: out std_logic_vector(6 downto 1); 
-		SFP_LOS				: in  std_logic_vector(6 downto 1);
-		--Flash ROM & Reboot
-		FLASH_CLK			: out   std_logic;
-		FLASH_CS				: out   std_logic;
-		FLASH_DIN			: out   std_logic;
-		FLASH_DOUT			: in    std_logic;
-		PROGRAMN				: out   std_logic;                     --reboot FPGA
-		--Misc
-		TEMPSENS	: inout std_logic;       --Temperature Sensor
-		CODE_LINE			: in    std_logic_vector(1 downto 0);
-		LED_GREEN			: out   std_logic;
-		LED_ORANGE			: out   std_logic;
-		LED_RED				: out   std_logic;
-		LED_YELLOW			: out   std_logic;
-		SUPPL					: in    std_logic;       --terminated diff pair, PCLK, Pads
-		--Test Connectors
-		TEST_LINE			: out std_logic_vector(15 downto 0)
-	);
-end Cu_trb3_periph_soda_client;
-
-architecture Cu_trb3_periph_soda_client_arch of Cu_trb3_periph_soda_client is
-	-- Constants
-	constant REGIO_NUM_STAT_REGS	: integer := 0;
-	constant REGIO_NUM_CTRL_REGS	: integer := 2;
-
-	constant USE_200_MHZ				: integer := 1 - USE_125_MHZ;	-- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
-	--Clock / Reset
-	signal pll_lock						: std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
-	signal clear_i							: std_logic;
-	signal reset_i							: std_logic;
-	signal GSR_N							: std_logic;
-
-	signal clk_100_osc      	   	: std_logic;
-	signal clk_200_osc   	   	   : std_logic;
-	signal time_counter					: unsigned(31 downto 0);
-
-	--Media Interface
-	signal med_stat_op					: std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_ctrl_op					: std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_stat_debug				: std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-	signal med_ctrl_debug				: std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-	signal med_data_out					: std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_packet_num_out			: std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-	signal med_dataready_out			: std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_read_out					: std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_data_in					: std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_packet_num_in			: std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-	signal med_dataready_in				: std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_read_in					: std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
-	--Slow Control channel
-	signal common_stat_reg				: std_logic_vector(std_COMSTATREG*32-1 downto 0);
-	signal common_ctrl_reg				: std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-	signal stat_reg						: std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg						: std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-	signal common_stat_reg_strobe		: std_logic_vector(std_COMSTATREG-1 downto 0);
-	signal common_ctrl_reg_strobe		: std_logic_vector(std_COMCTRLREG-1 downto 0);
-	signal stat_reg_strobe				: std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg_strobe				: std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
-	--RegIO
-	signal my_address						: std_logic_vector (15 downto 0);
-	signal regio_addr_out				: std_logic_vector (15 downto 0);
-	signal regio_read_enable_out		: std_logic;
-	signal regio_write_enable_out		: std_logic;
-	signal regio_data_out				: std_logic_vector (31 downto 0);
-	signal regio_data_in					: std_logic_vector (31 downto 0);
-	signal regio_dataready_in			: std_logic;
-	signal regio_no_more_data_in		: std_logic;
-	signal regio_write_ack_in			: std_logic;
-	signal regio_unknown_addr_in		: std_logic;
-	signal regio_timeout_out			: std_logic;
-
-	--Timer
-	signal global_time					: std_logic_vector(31 downto 0);
-	signal local_time						: std_logic_vector(7 downto 0);
-	signal time_since_last_trg			: std_logic_vector(31 downto 0);
-	signal timer_ticks					: std_logic_vector(1 downto 0);
-
-	--Flash
-	signal spimem_read_en				: std_logic;
-	signal spimem_write_en				: std_logic;
-	signal spimem_data_in				: std_logic_vector(31 downto 0);
-	signal spimem_addr					: std_logic_vector(8 downto 0);
-	signal spimem_data_out				: std_logic_vector(31 downto 0);
-	signal spimem_dataready_out		: std_logic;
-	signal spimem_no_more_data_out	: std_logic;
-	signal spimem_unknown_addr_out	: std_logic;
-	signal spimem_write_ack_out		: std_logic;
-
-	--Cu media interface
-	signal sci1_ack						: std_logic;
-	signal sci1_write						: std_logic;
-	signal sci1_read						: std_logic;
-	signal sci1_data_in					: std_logic_vector(7 downto 0);
-	signal sci1_data_out					: std_logic_vector(7 downto 0);
-	signal sci1_addr						: std_logic_vector(8 downto 0);  
-	signal sfp_txdis_S					: std_logic_vector(6 downto 1)	:= (others => '1'); 
-
-
-	--SODA
-	signal soda_rx_full_clk				: std_logic;
-	signal soda_rx_half_clk				: std_logic;
-	signal soda_tx_full_clk				: std_logic;
-	signal soda_tx_half_clk				: std_logic;
-
-	signal soda_tx_dlm_S					: std_logic;
-	signal soda_tx_dlm_word_S			: std_logic_vector(7 downto 0);
-	signal soda_rx_dlm_S					: std_logic;
-	signal soda_rx_dlm_word_S			: std_logic_vector(7 downto 0);
---	signal make_reset						: std_logic;
-	signal soda_tx_dlm_preview_S		: std_logic;	--PL!
-	signal link_phase_S					: std_logic;	--PL!
---	signal rx_cdr_lol_S					: std_logic;
---	signal link_locked_S					: std_logic;	--PL!
-
-	-- SODA slow controll
-	signal soda_ack						: std_logic;
-	signal soda_write						: std_logic;
-	signal soda_read						: std_logic;
-	signal soda_data_in					: std_logic_vector(31 downto 0);
-	signal soda_data_out					: std_logic_vector(31 downto 0);
-	signal soda_addr						: std_logic_vector(3 downto 0);  
-	signal soda_leds						: std_logic_vector(3 downto 0);  
-
-	signal link_debug_in_S				: std_logic_vector(31 downto 0);
-	signal general_reset_i				: std_logic := '1';
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-
-	LED_RX 		<= (others => '0');		-- otherwise it is floating
-	LED_TX 		<= (others => '0');		-- otherwise it is floating
-	LED_LINKOK	<= (others => '0');		-- otherwise it is floating
-	GSR_N <= pll_lock;
-
-	THE_RESET_HANDLER : trb_net_reset_handler
-		generic map(
-			RESET_DELAY => x"FEEE"
-			)
-		port map(
-			CLEAR_IN      => '0',              -- reset input (high active, async)
-			CLEAR_N_IN    => '1',              -- reset input (low active, async)
-			CLK_IN        => clk_200_osc,	--clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
-			SYSCLK_IN     => clk_100_osc,	--rx_half_clk,  PL 111114,        -- PLL/DLL remastered clock
-			PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
-			RESET_IN      => '0', --general_reset_i, -- '0',              -- general reset signal (SYSCLK) --peter schakel
-			TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
-			CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
-			RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
-			DEBUG_OUT     => open
-		);  
-
--------------------------------------------------------------------------
--- Clock Handling
--------------------------------------------------------------------------
-THE_MAIN_PLL : pll_in200_out100
-	port map(
-		CLK   => CLK_GPLL_RIGHT,
-		CLKOP => clk_100_osc,
-		CLKOK => clk_200_osc,
-		LOCK  => pll_lock
-	);
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
-	TRB_MEDIA_AND_SODA_SYNC_UPLINK : Cu_trb_net16_soda_syncUP_ecp3_sfp
-		port map(
-			OSCCLK						=> clk_200_osc,
-			SYSCLK						=> clk_100_osc,
-			RESET							=> reset_i,
-			CLEAR							=> clear_i,
-			--Internal Connection
-			MED_DATA_IN       	 	=> med_data_out(15 downto 0),
-			MED_PACKET_NUM_IN			=> med_packet_num_out(2 downto 0),
-			MED_DATAREADY_IN			=> med_dataready_out(0),
-			MED_READ_OUT				=> med_read_in(0),
-			MED_DATA_OUT				=> med_data_in(15 downto 0),
-			MED_PACKET_NUM_OUT		=> med_packet_num_in(2 downto 0),
-			MED_DATAREADY_OUT			=> med_dataready_in(0),
-			MED_READ_IN					=> med_read_out(0),
-
-			--Copper SFP Connection
-			CU_RXD_P_IN					=> CU_SERDES_RX(0),
-			CU_RXD_N_IN					=> CU_SERDES_RX(1),
-			CU_TXD_P_OUT				=> CU_SERDES_TX(0),
-			CU_TXD_N_OUT				=> CU_SERDES_TX(1),
-			CU_PRSNT_N_IN				=> FPGA5_COMM(0),
-			CU_LOS_IN					=> FPGA5_COMM(0),
-			CU_TXDIS_OUT				=> FPGA5_COMM(2),
-
-			-- sync clocks
-			SYNC_RX_HALF_CLK_OUT		=> soda_rx_half_clk,
-			SYNC_RX_FULL_CLK_OUT		=> soda_rx_full_clk,
-			SYNC_TX_HALF_CLK_OUT		=> soda_tx_half_clk,
-			SYNC_TX_FULL_CLK_OUT		=> soda_tx_full_clk,
-
-			SYNC_RXD_P_IN				=> SERDES_ADDON_RX(4),
-			SYNC_RXD_N_IN				=> SERDES_ADDON_RX(5),
-			SYNC_TXD_P_OUT				=> SERDES_ADDON_TX(4),
-			SYNC_TXD_N_OUT				=> SERDES_ADDON_TX(5),
-			SYNC_TX_DLM_IN				=> soda_tx_dlm_S,
-			SYNC_TX_DLM_WORD_IN		=> soda_tx_dlm_word_S,
-			SYNC_RX_DLM_OUT			=> soda_rx_dlm_S,
-			SYNC_RX_DLM_WORD_OUT		=> soda_rx_dlm_word_S,
-			SYNC_PRSNT_N_IN			=> SFP_MOD0(3),
-			SYNC_LOS_IN					=> SFP_LOS(3),
-			SYNC_TXDIS_OUT				=> sfp_txdis_S(3),
-
-			SCI_DATA_IN					=> sci1_data_in,
-			SCI_DATA_OUT				=> sci1_data_out,
-			SCI_ADDR						=> sci1_addr,
-			SCI_READ						=> sci1_read,
-			SCI_WRITE					=> sci1_write,
-			SCI_ACK						=> sci1_ack,        
-			-- Status and control port
-			STAT_OP						=> med_stat_op(15 downto 0),
-			CTRL_OP						=> med_ctrl_op(15 downto 0),
-			STAT_DEBUG					=> med_stat_debug(63 downto 0),
-			CTRL_DEBUG					=> (others => '0')
-		);
-
-
--------------------------------------------------------------------------
--- Endpoint
--------------------------------------------------------------------------
-	THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
-		generic map(
-			--USE_CHANNEL               => (c_YES,c_YES,c_NO,c_YES),
-			REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
-			REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
-			ADDRESS_MASK              => x"FFFF",
-			BROADCAST_BITMASK         => x"FF",
-			BROADCAST_SPECIAL_ADDR    => x"45",
-			REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
-			REGIO_HARDWARE_VERSION    => x"9100b000",
-			REGIO_INIT_ADDRESS        => x"f35a",
-			REGIO_USE_VAR_ENDPOINT_ID => c_YES,
-			CLOCK_FREQUENCY           => CLOCK_FREQUENCY,
-			TIMING_TRIGGER_RAW        => c_YES,
-			--Configure data handler
-			DATA_INTERFACE_NUMBER     => 1,
-			DATA_BUFFER_DEPTH         => 9,  --13
-			DATA_BUFFER_WIDTH         => 32,
-			DATA_BUFFER_FULL_THRESH   => 256,
-			TRG_RELEASE_AFTER_DATA    => c_YES,
-			HEADER_BUFFER_DEPTH       => 9,
-			HEADER_BUFFER_FULL_THRESH => 256
-      )
-	port map(
-		CLK                => clk_100_osc,	--rx_half_clk,  PL 111114
-		RESET              => reset_i,
-		CLK_EN             => '1',
-		MED_DATAREADY_OUT  => med_dataready_out(0),
-		MED_DATA_OUT       => med_data_out,
-		MED_PACKET_NUM_OUT => med_packet_num_out,
-		MED_READ_IN        => med_read_in(0),
-		MED_DATAREADY_IN   => med_dataready_in(0),
-		MED_DATA_IN        => med_data_in,
-		MED_PACKET_NUM_IN  => med_packet_num_in,
-		MED_READ_OUT       => med_read_out(0),
-		MED_STAT_OP_IN     => med_stat_op,
-		MED_CTRL_OP_OUT    => med_ctrl_op,
-
-		--Timing trigger in
-		TRG_TIMING_TRG_RECEIVED_IN  => '0',
-		--LVL1 trigger to FEE
-		LVL1_TRG_DATA_VALID_OUT     => open,
-		LVL1_VALID_TIMING_TRG_OUT   => open,
-		LVL1_VALID_NOTIMING_TRG_OUT => open,
-		LVL1_INVALID_TRG_OUT        => open,
-
-		LVL1_TRG_TYPE_OUT        => open,
-		LVL1_TRG_NUMBER_OUT      => open,
-		LVL1_TRG_CODE_OUT        => open,
-		LVL1_TRG_INFORMATION_OUT => open,
-		LVL1_INT_TRG_NUMBER_OUT  => open,
-
-		--Information about trigger handler errors
-		TRG_MULTIPLE_TRG_OUT     => open,
-		TRG_TIMEOUT_DETECTED_OUT => open,
-		TRG_SPURIOUS_TRG_OUT     => open,
-		TRG_MISSING_TMG_TRG_OUT  => open,
-		TRG_SPIKE_DETECTED_OUT   => open,
-
-		--Response from FEE
-		FEE_TRG_RELEASE_IN(0)       => '1',
-		FEE_TRG_STATUSBITS_IN       => (others => '0'),
-		FEE_DATA_IN                 => (others => '0'),
-		FEE_DATA_WRITE_IN(0)        => '0',
-		FEE_DATA_FINISHED_IN(0)     => '1',
-		FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
-		-- Slow Control Data Port
-		REGIO_COMMON_STAT_REG_IN           => (others => '0'),		--common_stat_reg,  --0x00  because it is floating
-		REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
-		REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
-		REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
-		REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
-		REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
-		REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
-		REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
-		REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
-		REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
-		BUS_ADDR_OUT         => regio_addr_out,
-		BUS_READ_ENABLE_OUT  => regio_read_enable_out,
-		BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
-		BUS_DATA_OUT         => regio_data_out,
-		BUS_DATA_IN          => regio_data_in,
-		BUS_DATAREADY_IN     => regio_dataready_in,
-		BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
-		BUS_WRITE_ACK_IN     => regio_write_ack_in,
-		BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
-		BUS_TIMEOUT_OUT      => regio_timeout_out,
-		ONEWIRE_INOUT        => TEMPSENS,
-		ONEWIRE_MONITOR_OUT  => open,
-
-		TIME_GLOBAL_OUT         => global_time,
-		TIME_LOCAL_OUT          => local_time,
-		TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
-		TIME_TICKS_OUT          => timer_ticks,
-
-		STAT_DEBUG_IPU              => open,
-		STAT_DEBUG_1                => open,
-		STAT_DEBUG_2                => open,
-		STAT_DEBUG_DATA_HANDLER_OUT => open,
-		STAT_DEBUG_IPU_HANDLER_OUT  => open,
-		STAT_TRIGGER_OUT            => open,
-		CTRL_MPLEX                  => (others => '0'),
-		IOBUF_CTRL_GEN              => (others => '0'),
-		STAT_ONEWIRE                => open,
-		STAT_ADDR_DEBUG             => open,
-		DEBUG_LVL1_HANDLER_OUT      => open
-	);
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
-  THE_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER    => 3,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"be00", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 4,       others => 0)
-      )
-    port map(
-		CLK   => clk_100_osc,	--rx_half_clk,  PL 111114
-		RESET => reset_i,
-
-		DAT_ADDR_IN					=> regio_addr_out,
-		DAT_DATA_IN					=> regio_data_out,
-		DAT_DATA_OUT				=> regio_data_in,
-		DAT_READ_ENABLE_IN		=> regio_read_enable_out,
-		DAT_WRITE_ENABLE_IN		=> regio_write_enable_out,
-		DAT_TIMEOUT_IN				=> regio_timeout_out,
-		DAT_DATAREADY_OUT			=> regio_dataready_in,
-		DAT_WRITE_ACK_OUT			=> regio_write_ack_in,
-		DAT_NO_MORE_DATA_OUT		=> regio_no_more_data_in,
-		DAT_UNKNOWN_ADDR_OUT		=> regio_unknown_addr_in,
-
-		BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
-		BUS_READ_ENABLE_OUT(1)              => sci1_read,
-		BUS_READ_ENABLE_OUT(2)              => soda_read,
-
-		BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
-		BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
-		BUS_WRITE_ENABLE_OUT(2)             => soda_write,
-
-		BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
-		BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
-		BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
-		BUS_DATA_OUT(2*32+31 downto 2*32)   => soda_data_in,
-
-		BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
-		BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
-		BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
-		BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
-		BUS_ADDR_OUT(2*16+3 downto 2*16)   	=> soda_addr,
-		BUS_ADDR_OUT(2*16+15 downto 2*16+4) => open,
-
-		BUS_TIMEOUT_OUT(0)                  => open,
-		BUS_TIMEOUT_OUT(1)                  => open,
-		BUS_TIMEOUT_OUT(2)                  => open,
-
-		BUS_DATA_IN(0*32+31 downto 0*32)    => spimem_data_out,
-		BUS_DATA_IN(1*32+7 downto 1*32)     => sci1_data_out,
-		BUS_DATA_IN(1*32+31 downto 1*32+8)  => open,
-		BUS_DATA_IN(2*32+31 downto 2*32)    => soda_data_out,
-
-		BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
-		BUS_DATAREADY_IN(1)                 => sci1_ack,
-		BUS_DATAREADY_IN(2)                 => soda_ack,
-
-		BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
-		BUS_WRITE_ACK_IN(1)                 => sci1_ack,
-		BUS_WRITE_ACK_IN(2)                 => soda_ack,
-
-		BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
-		BUS_NO_MORE_DATA_IN(1)              => '0',
-		BUS_NO_MORE_DATA_IN(2)              => '0',
-
-		BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
-		BUS_UNKNOWN_ADDR_IN(1)              => '0',
-		BUS_UNKNOWN_ADDR_IN(2)              => '0',
-
-		STAT_DEBUG => open
-		);
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD :  spi_flash_and_fpga_reload	--.flash_reboot_arch
-  port map(
-    CLK_IN               => clk_100_osc,
-    RESET_IN             => reset_i,
-    
-    BUS_ADDR_IN          => spimem_addr,
-    BUS_READ_IN          => spimem_read_en,
-    BUS_WRITE_IN         => spimem_write_en,
-    BUS_DATAREADY_OUT    => spimem_dataready_out,
-    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
-    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
-    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
-    BUS_DATA_IN          => spimem_data_in,
-    BUS_DATA_OUT         => spimem_data_out,
-    
-    DO_REBOOT_IN         => common_ctrl_reg(15),     
-    PROGRAMN             => PROGRAMN,
-    
-    SPI_CS_OUT           => FLASH_CS,
-    SPI_SCK_OUT          => FLASH_CLK,
-    SPI_SDO_OUT          => FLASH_DIN,
-    SPI_SDI_IN           => FLASH_DOUT
-    );
-
-
---	SFP_TXDIS(1)	<=	sfp_txdis_S(1);
-	SFP_TXDIS		<=	sfp_txdis_S;
-	
-	-----------------------------------------------------------------------
-	-- Since there is nomore trb on this link, link-phase does not need to
-	-- be controlled. To avoid changing code, link-phase is faked here.
-	-----------------------------------------------------------------------
-	DUMMY_LINK_PHASE_PROC : process (soda_rx_full_clk)
-	begin
-		if rising_edge(soda_rx_full_clk) then
-			if (reset_i='1') then
-				link_phase_S	<='0';
-			elsif (link_phase_S='0') then
-				link_phase_S	<='1';
-			else
-				link_phase_S	<='0';
-			end if;
-		end if;
-	end process;
-	
----------------------------------------------------------------------------
--- The Soda Central 
----------------------------------------------------------------------------         
-
-	A_SODA_CLIENT : soda_client
-		port map(
-			SYSCLK					=> soda_rx_half_clk,	--clk_100_osc,
-			SODACLK					=>	soda_rx_full_clk,
-			RESET						=> reset_i,
-			CLEAR						=> clear_i,
-			CLK_EN					=> '1',
-			--Internal Connection
-			RX_DLM_WORD_IN			=> soda_rx_dlm_word_S,
-			RX_DLM_IN				=> soda_rx_dlm_S,
-			TX_DLM_OUT				=> soda_tx_dlm_S, 
-			TX_DLM_WORD_OUT		=> soda_tx_dlm_word_S,
-			TX_DLM_PREVIEW_OUT	=> soda_tx_dlm_preview_S,
-			LINK_PHASE_IN			=> link_phase_S,
-			SODA_DATA_IN			=> soda_data_in,
-			SODA_DATA_OUT			=> soda_data_out,
-			SODA_ADDR_IN			=> soda_addr,
-			SODA_READ_IN			=> soda_read,
-			SODA_WRITE_IN			=> soda_write,
-			SODA_ACK_OUT			=> soda_ack,
-			LEDS_OUT					=>	soda_leds,
-			LINK_DEBUG_IN			=> link_debug_in_S
-		);
-
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
-
-	LED_ORANGE <= time_counter(26);
-	LED_YELLOW <= time_counter(26);
-	LED_GREEN  <= time_counter(26);
-	LED_RED    <= time_counter(26);
----------------------------------------------------------------------------
--- DEBUG
----------------------------------------------------------------------------    
-	link_debug_in_S(31 downto 16)	<= med_stat_op(15 downto 0);
-	link_debug_in_S(15 downto 0)	<= (3 => pll_lock, others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-	blink : process (clk_100_osc)
-	begin
-		if rising_edge(clk_100_osc) then
-			if (time_counter = x"FFFFFFFF") then
-				time_counter <= x"00000000";
-			else
-				time_counter <= time_counter + 1;
-			end if;
-		end if;
-   end process;
-
-end Cu_trb3_periph_soda_client_arch;
\ No newline at end of file
diff --git a/code/Cu_trb3_periph_soda_hub.vhd b/code/Cu_trb3_periph_soda_hub.vhd
deleted file mode 100644
index c0ec61c..0000000
--- a/code/Cu_trb3_periph_soda_hub.vhd
+++ /dev/null
@@ -1,706 +0,0 @@
----------------
--- TOP LEVEL --
----------------
--- TAB=3 !!
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all; 
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity Cu_trb3_periph_soda_hub is
-	generic(
-		SYNC_MODE			: integer range 0 to 1 := c_NO;   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
-		USE_125_MHZ			: integer := c_NO;
-		CLOCK_FREQUENCY	: integer := 100;
-		NUM_INTERFACES		: integer := 6 + 1
-		);
-	port(
-		--Clocks 
-		CLK_GPLL_LEFT		: in std_logic;  --Clock Manager 1/(2468), 125 MHz
-		CLK_GPLL_RIGHT		: in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
-		CLK_PCLK_LEFT		: in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-		CLK_PCLK_RIGHT		: in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-		--serdes I/O - connect as you like, no real use
-		CU_SERDES_TX		: out std_logic_vector(3 downto 0);
-		CU_SERDES_RX		: in  std_logic_vector(3 downto 0);
-		SERDES_ADDON_TX	: out std_logic_vector(15 downto 0);
-		SERDES_ADDON_RX	: in  std_logic_vector(15 downto 0);
-		--Inter-FPGA Communication
-		FPGA5_COMM : inout std_logic_vector(11 downto 0);
-																		--Bit 0/1 input, serial link RX active
-																		--Bit 2/3 output, serial link TX active
-																		--others yet undefined
-		--Connection to AddOn
-		LED_LINKOK			: out std_logic_vector(6 downto 1);
-		LED_RX				: out std_logic_vector(6 downto 1); 
-		LED_TX				: out std_logic_vector(6 downto 1);
-		SFP_MOD0				: in  std_logic_vector(6 downto 1);
-		SFP_TXDIS			: out std_logic_vector(6 downto 1); 
-		SFP_LOS				: in  std_logic_vector(6 downto 1);
-		--Flash ROM & Reboot
-		FLASH_CLK			: out   std_logic;
-		FLASH_CS				: out   std_logic;
-		FLASH_DIN			: out   std_logic;
-		FLASH_DOUT			: in    std_logic;
-		PROGRAMN				: out   std_logic;                     --reboot FPGA
-		--Misc
-		TEMPSENS	: inout std_logic;       --Temperature Sensor
-		CODE_LINE			: in    std_logic_vector(1 downto 0);
-		LED_GREEN			: out   std_logic;
-		LED_ORANGE			: out   std_logic;
-		LED_RED				: out   std_logic;
-		LED_YELLOW			: out   std_logic;
-		SUPPL					: in    std_logic;       --terminated diff pair, PCLK, Pads
-		--Test Connectors
-		TEST_LINE			: out std_logic_vector(15 downto 0)
-	);
-end Cu_trb3_periph_soda_hub;
-
-architecture Cu_trb3_periph_soda_hub_arch of Cu_trb3_periph_soda_hub is
-	-- Constants
-	constant REGIO_NUM_STAT_REGS	: integer := 0;
-	constant REGIO_NUM_CTRL_REGS	: integer := 2;
-
-	constant USE_200_MHZ				: integer := 1 - USE_125_MHZ;	-- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
-	--Clock / Reset
-	signal pll_lock						: std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
-	signal clear_i							: std_logic;
-	signal reset_i							: std_logic;
-	signal downlink_clear				: std_logic;
-	signal downlink_reset				: std_logic;
-	signal GSR_N							: std_logic;
-
-	signal clk_100_osc      	   	: std_logic;
-	signal clk_200_osc   	   	   : std_logic;
-	signal time_counter					: unsigned(31 downto 0);
-
-	--Media Interface
-	signal med_stat_op					: std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_ctrl_op					: std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_stat_debug				: std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-	signal med_ctrl_debug				: std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-	signal med_data_out					: std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_packet_num_out			: std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-	signal med_dataready_out			: std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_read_out					: std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_data_in					: std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_packet_num_in			: std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-	signal med_dataready_in				: std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_read_in					: std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
-	--Slow Control channel
-	signal common_stat_reg				: std_logic_vector(std_COMSTATREG*32-1 downto 0);
-	signal common_ctrl_reg				: std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-	signal stat_reg						: std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg						: std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-	signal common_stat_reg_strobe		: std_logic_vector(std_COMSTATREG-1 downto 0);
-	signal common_ctrl_reg_strobe		: std_logic_vector(std_COMCTRLREG-1 downto 0);
-	signal stat_reg_strobe				: std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg_strobe				: std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
-	--RegIO
-	signal my_address						: std_logic_vector (15 downto 0);
-	signal regio_addr_out				: std_logic_vector (15 downto 0);
-	signal regio_read_enable_out		: std_logic;
-	signal regio_write_enable_out		: std_logic;
-	signal regio_data_out				: std_logic_vector (31 downto 0);
-	signal regio_data_in					: std_logic_vector (31 downto 0);
-	signal regio_dataready_in			: std_logic;
-	signal regio_no_more_data_in		: std_logic;
-	signal regio_write_ack_in			: std_logic;
-	signal regio_unknown_addr_in		: std_logic;
-	signal regio_timeout_out			: std_logic;
-
-	--Timer
-	signal global_time					: std_logic_vector(31 downto 0);
-	signal local_time						: std_logic_vector(7 downto 0);
-	signal time_since_last_trg			: std_logic_vector(31 downto 0);
-	signal timer_ticks					: std_logic_vector(1 downto 0);
-
-	--Flash
-	signal spimem_read_en				: std_logic;
-	signal spimem_write_en				: std_logic;
-	signal spimem_data_in				: std_logic_vector(31 downto 0);
-	signal spimem_addr					: std_logic_vector(8 downto 0);
-	signal spimem_data_out				: std_logic_vector(31 downto 0);
-	signal spimem_dataready_out		: std_logic;
-	signal spimem_no_more_data_out	: std_logic;
-	signal spimem_unknown_addr_out	: std_logic;
-	signal spimem_write_ack_out		: std_logic;
-
-	--Cu media interface
-	signal sci1_ack						: std_logic;
-	signal sci1_write						: std_logic;
-	signal sci1_read						: std_logic;
-	signal sci1_data_in					: std_logic_vector(7 downto 0);
-	signal sci1_data_out					: std_logic_vector(7 downto 0);
-	signal sci1_addr						: std_logic_vector(8 downto 0);  
-	signal sfp_txdis_S					: std_logic_vector(6 downto 1)	:= (others => '1'); 
-
-	signal sci2_ack						: std_logic;
-	signal sci2_nack						: std_logic;
-	signal sci2_write						: std_logic;
-	signal sci2_read						: std_logic;
-	signal sci2_data_in					: std_logic_vector(7 downto 0);
-	signal sci2_data_out					: std_logic_vector(7 downto 0);
-	signal sci2_addr						: std_logic_vector(8 downto 0);  
-
-
-	--SODA
-	signal soda_rxup_full_clk			: std_logic;
-	signal soda_rxup_half_clk			: std_logic;
-	signal soda_txup_full_clk			: std_logic;
-	signal soda_txup_half_clk			: std_logic;
-
-	signal soda_txup_dlm_S					: std_logic;
-	signal soda_txup_dlm_word_S		: std_logic_vector(7 downto 0);
-	signal soda_rxup_dlm_S				: std_logic;
-	signal soda_rxup_dlm_word_S		: std_logic_vector(7 downto 0);
-	signal soda_txup_dlm_preview_S	: std_logic;
-	signal soda_uplink_phase_S			: std_logic;
-
-	--SODA downlink
-	signal soda_rxdn_half_clk			: t_HUB_BIT;
-	signal soda_rxdn_full_clk			: t_HUB_BIT;
-	signal soda_txdn_half_clk			: t_HUB_BIT;
-	signal soda_txdn_full_clk			: t_HUB_BIT;
-
-	signal soda_txdn_dlm_S				: t_HUB_BIT;
-	signal soda_txdn_dlm_word_S		: t_HUB_BYTE;
-	signal soda_rxdn_dlm_S				: t_HUB_BIT;
-	signal soda_rxdn_dlm_word_S		: t_HUB_BYTE;
-	signal soda_txdn_dlm_preview_S	: t_HUB_BIT;
-	signal soda_dnlink_phase_S			: t_HUB_BIT;
-
-	-- SODA slow controll
-	signal soda_ack						: std_logic;
-	signal soda_write						: std_logic;
-	signal soda_read						: std_logic;
-	signal soda_data_in					: std_logic_vector(31 downto 0);
-	signal soda_data_out					: std_logic_vector(31 downto 0);
-	signal soda_addr						: std_logic_vector(3 downto 0);  
-	signal soda_leds						: std_logic_vector(3 downto 0);  
-
-	signal link_debug_in_S				: std_logic_vector(31 downto 0);
-	signal general_reset_i				: std_logic := '1';
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-
-	LED_RX 		<= (others => '0');		-- otherwise it is floating
-	LED_TX 		<= (others => '0');		-- otherwise it is floating
-	LED_LINKOK	<= (others => '0');		-- otherwise it is floating
-	GSR_N <= pll_lock;
-
-	THE_RESET_HANDLER : trb_net_reset_handler
-		generic map(
-			RESET_DELAY => x"FEEE"
-			)
-		port map(
-			CLEAR_IN      => '0',              -- reset input (high active, async)
-			CLEAR_N_IN    => '1',              -- reset input (low active, async)
-			CLK_IN        => clk_200_osc,	--clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
-			SYSCLK_IN     => clk_100_osc,	--rx_half_clk,  PL 111114,        -- PLL/DLL remastered clock
-			PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
-			RESET_IN      => '0', --general_reset_i, -- '0',              -- general reset signal (SYSCLK) --peter schakel
-			TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
-			CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
-			RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
-			DEBUG_OUT     => open
-		);  
-
--------------------------------------------------------------------------
--- Clock Handling
--------------------------------------------------------------------------
-THE_MAIN_PLL : pll_in200_out100
-	port map(
-		CLK   => CLK_GPLL_RIGHT,
-		CLKOP => clk_100_osc,
-		CLKOK => clk_200_osc,
-		LOCK  => pll_lock
-	);
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
-	TRB_MEDIA_AND_SODA_SYNC_UPLINK : Cu_trb_net16_soda_syncUP_ecp3_sfp
-		port map(
-			OSCCLK						=> clk_200_osc,
-			SYSCLK						=> clk_100_osc,
-			RESET							=> reset_i,
-			CLEAR							=> clear_i,
-			--Internal Connection
-			MED_DATA_IN       	 	=> med_data_out(15 downto 0),
-			MED_PACKET_NUM_IN			=> med_packet_num_out(2 downto 0),
-			MED_DATAREADY_IN			=> med_dataready_out(0),
-			MED_READ_OUT				=> med_read_in(0),
-			MED_DATA_OUT				=> med_data_in(15 downto 0),
-			MED_PACKET_NUM_OUT		=> med_packet_num_in(2 downto 0),
-			MED_DATAREADY_OUT			=> med_dataready_in(0),
-			MED_READ_IN					=> med_read_out(0),
-
-			--Copper SFP Connection
-			CU_RXD_P_IN					=> CU_SERDES_RX(0),
-			CU_RXD_N_IN					=> CU_SERDES_RX(1),
-			CU_TXD_P_OUT				=> CU_SERDES_TX(0),
-			CU_TXD_N_OUT				=> CU_SERDES_TX(1),
-			CU_PRSNT_N_IN				=> FPGA5_COMM(0),
-			CU_LOS_IN					=> FPGA5_COMM(0),
-			CU_TXDIS_OUT				=> FPGA5_COMM(2),
-
-			-- sync clocks
-			SYNC_RX_HALF_CLK_OUT		=> soda_rxup_half_clk,
-			SYNC_RX_FULL_CLK_OUT		=> soda_rxup_full_clk,
-			SYNC_TX_HALF_CLK_OUT		=> soda_txup_half_clk,
-			SYNC_TX_FULL_CLK_OUT		=> soda_txup_full_clk,
-
-			SYNC_RXD_P_IN				=> SERDES_ADDON_RX(4),
-			SYNC_RXD_N_IN				=> SERDES_ADDON_RX(5),
-			SYNC_TXD_P_OUT				=> SERDES_ADDON_TX(4),
-			SYNC_TXD_N_OUT				=> SERDES_ADDON_TX(5),
-			SYNC_TX_DLM_IN				=> soda_txup_dlm_S,
-			SYNC_TX_DLM_WORD_IN		=> soda_txup_dlm_word_S,
-			SYNC_RX_DLM_OUT			=> soda_rxup_dlm_S,
-			SYNC_RX_DLM_WORD_OUT		=> soda_rxup_dlm_word_S,
-			SYNC_PRSNT_N_IN			=> SFP_MOD0(3),
-			SYNC_LOS_IN					=> SFP_LOS(3),
-			SYNC_TXDIS_OUT				=> sfp_txdis_S(3),
-
-			SCI_DATA_IN					=> sci1_data_in,
-			SCI_DATA_OUT				=> sci1_data_out,
-			SCI_ADDR						=> sci1_addr,
-			SCI_READ						=> sci1_read,
-			SCI_WRITE					=> sci1_write,
-			SCI_ACK						=> sci1_ack,        
-			-- Status and control port
-			STAT_OP						=> med_stat_op(15 downto 0),
-			CTRL_OP						=> med_ctrl_op(15 downto 0),
-			STAT_DEBUG					=> med_stat_debug(63 downto 0),
-			CTRL_DEBUG					=> (others => '0')
-		);
-
-
--------------------------------------------------------------------------
--- Endpoint
--------------------------------------------------------------------------
-	THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
-		generic map(
-			--USE_CHANNEL               => (c_YES,c_YES,c_NO,c_YES),
-			REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
-			REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
-			ADDRESS_MASK              => x"FFFF",
-			BROADCAST_BITMASK         => x"FF",
-			BROADCAST_SPECIAL_ADDR    => x"45",
-			REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
-			REGIO_HARDWARE_VERSION    => x"9100b000",
-			REGIO_INIT_ADDRESS        => x"f35b",
-			REGIO_USE_VAR_ENDPOINT_ID => c_YES,
-			CLOCK_FREQUENCY           => CLOCK_FREQUENCY,
-			TIMING_TRIGGER_RAW        => c_YES,
-			--Configure data handler
-			DATA_INTERFACE_NUMBER     => 1,
-			DATA_BUFFER_DEPTH         => 9,  --13
-			DATA_BUFFER_WIDTH         => 32,
-			DATA_BUFFER_FULL_THRESH   => 256,
-			TRG_RELEASE_AFTER_DATA    => c_YES,
-			HEADER_BUFFER_DEPTH       => 9,
-			HEADER_BUFFER_FULL_THRESH => 256
-      )
-	port map(
-		CLK                => clk_100_osc,	--rx_half_clk,  PL 111114
-		RESET              => reset_i,
-		CLK_EN             => '1',
-		MED_DATAREADY_OUT  => med_dataready_out(0),
-		MED_DATA_OUT       => med_data_out(15 downto 0),
-		MED_PACKET_NUM_OUT => med_packet_num_out(2 downto 0),
-		MED_READ_IN        => med_read_in(0),
-		MED_DATAREADY_IN   => med_dataready_in(0),
-		MED_DATA_IN        => med_data_in(15 downto 0),
-		MED_PACKET_NUM_IN  => med_packet_num_in(2 downto 0),
-		MED_READ_OUT       => med_read_out(0),
-		MED_STAT_OP_IN     => med_stat_op(15 downto 0),
-		MED_CTRL_OP_OUT    => med_ctrl_op(15 downto 0),
-
-		--Timing trigger in
-		TRG_TIMING_TRG_RECEIVED_IN  => '0',
-		--LVL1 trigger to FEE
-		LVL1_TRG_DATA_VALID_OUT     => open,
-		LVL1_VALID_TIMING_TRG_OUT   => open,
-		LVL1_VALID_NOTIMING_TRG_OUT => open,
-		LVL1_INVALID_TRG_OUT        => open,
-
-		LVL1_TRG_TYPE_OUT        => open,
-		LVL1_TRG_NUMBER_OUT      => open,
-		LVL1_TRG_CODE_OUT        => open,
-		LVL1_TRG_INFORMATION_OUT => open,
-		LVL1_INT_TRG_NUMBER_OUT  => open,
-
-		--Information about trigger handler errors
-		TRG_MULTIPLE_TRG_OUT     => open,
-		TRG_TIMEOUT_DETECTED_OUT => open,
-		TRG_SPURIOUS_TRG_OUT     => open,
-		TRG_MISSING_TMG_TRG_OUT  => open,
-		TRG_SPIKE_DETECTED_OUT   => open,
-
-		--Response from FEE
-		FEE_TRG_RELEASE_IN(0)       => '1',
-		FEE_TRG_STATUSBITS_IN       => (others => '0'),
-		FEE_DATA_IN                 => (others => '0'),
-		FEE_DATA_WRITE_IN(0)        => '0',
-		FEE_DATA_FINISHED_IN(0)     => '1',
-		FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
-		-- Slow Control Data Port
-		REGIO_COMMON_STAT_REG_IN           => (others => '0'),		--common_stat_reg,  --0x00  because it is floating
-		REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
-		REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
-		REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
-		REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
-		REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
-		REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
-		REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
-		REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
-		REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
-		BUS_ADDR_OUT         => regio_addr_out,
-		BUS_READ_ENABLE_OUT  => regio_read_enable_out,
-		BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
-		BUS_DATA_OUT         => regio_data_out,
-		BUS_DATA_IN          => regio_data_in,
-		BUS_DATAREADY_IN     => regio_dataready_in,
-		BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
-		BUS_WRITE_ACK_IN     => regio_write_ack_in,
-		BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
-		BUS_TIMEOUT_OUT      => regio_timeout_out,
-		ONEWIRE_INOUT        => TEMPSENS,
-		ONEWIRE_MONITOR_OUT  => open,
-
-		TIME_GLOBAL_OUT         => global_time,
-		TIME_LOCAL_OUT          => local_time,
-		TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
-		TIME_TICKS_OUT          => timer_ticks,
-
-		STAT_DEBUG_IPU              => open,
-		STAT_DEBUG_1                => open,
-		STAT_DEBUG_2                => open,
-		STAT_DEBUG_DATA_HANDLER_OUT => open,
-		STAT_DEBUG_IPU_HANDLER_OUT  => open,
-		STAT_TRIGGER_OUT            => open,
-		CTRL_MPLEX                  => (others => '0'),
-		IOBUF_CTRL_GEN              => (others => '0'),
-		STAT_ONEWIRE                => open,
-		STAT_ADDR_DEBUG             => open,
-		DEBUG_LVL1_HANDLER_OUT      => open
-	);
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
-  THE_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER    => 3,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"be00", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 4,       others => 0)
-      )
-    port map(
-		CLK   => clk_100_osc,	--rx_half_clk,  PL 111114
-		RESET => reset_i,
-
-		DAT_ADDR_IN					=> regio_addr_out,
-		DAT_DATA_IN					=> regio_data_out,
-		DAT_DATA_OUT				=> regio_data_in,
-		DAT_READ_ENABLE_IN		=> regio_read_enable_out,
-		DAT_WRITE_ENABLE_IN		=> regio_write_enable_out,
-		DAT_TIMEOUT_IN				=> regio_timeout_out,
-		DAT_DATAREADY_OUT			=> regio_dataready_in,
-		DAT_WRITE_ACK_OUT			=> regio_write_ack_in,
-		DAT_NO_MORE_DATA_OUT		=> regio_no_more_data_in,
-		DAT_UNKNOWN_ADDR_OUT		=> regio_unknown_addr_in,
-
-		BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
-		BUS_READ_ENABLE_OUT(1)              => sci1_read,
-		BUS_READ_ENABLE_OUT(2)              => soda_read,
-
-		BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
-		BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
-		BUS_WRITE_ENABLE_OUT(2)             => soda_write,
-
-		BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
-		BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
-		BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
-		BUS_DATA_OUT(2*32+31 downto 2*32)   => soda_data_in,
-
-		BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
-		BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
-		BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
-		BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
-		BUS_ADDR_OUT(2*16+3 downto 2*16)   	=> soda_addr,
-		BUS_ADDR_OUT(2*16+15 downto 2*16+4) => open,
-
-		BUS_TIMEOUT_OUT(0)                  => open,
-		BUS_TIMEOUT_OUT(1)                  => open,
-		BUS_TIMEOUT_OUT(2)                  => open,
-
-		BUS_DATA_IN(0*32+31 downto 0*32)    => spimem_data_out,
-		BUS_DATA_IN(1*32+7 downto 1*32)     => sci1_data_out,
-		BUS_DATA_IN(1*32+31 downto 1*32+8)  => open,
-		BUS_DATA_IN(2*32+31 downto 2*32)    => soda_data_out,
-
-		BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
-		BUS_DATAREADY_IN(1)                 => sci1_ack,
-		BUS_DATAREADY_IN(2)                 => soda_ack,
-
-		BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
-		BUS_WRITE_ACK_IN(1)                 => sci1_ack,
-		BUS_WRITE_ACK_IN(2)                 => soda_ack,
-
-		BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
-		BUS_NO_MORE_DATA_IN(1)              => '0',
-		BUS_NO_MORE_DATA_IN(2)              => '0',
-
-		BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
-		BUS_UNKNOWN_ADDR_IN(1)              => '0',
-		BUS_UNKNOWN_ADDR_IN(2)              => '0',
-
-		STAT_DEBUG => open
-		);
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD :  spi_flash_and_fpga_reload	--.flash_reboot_arch
-  port map(
-    CLK_IN               => clk_100_osc,
-    RESET_IN             => reset_i,
-    
-    BUS_ADDR_IN          => spimem_addr,
-    BUS_READ_IN          => spimem_read_en,
-    BUS_WRITE_IN         => spimem_write_en,
-    BUS_DATAREADY_OUT    => spimem_dataready_out,
-    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
-    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
-    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
-    BUS_DATA_IN          => spimem_data_in,
-    BUS_DATA_OUT         => spimem_data_out,
-    
-    DO_REBOOT_IN         => common_ctrl_reg(15),     
-    PROGRAMN             => PROGRAMN,
-    
-    SPI_CS_OUT           => FLASH_CS,
-    SPI_SCK_OUT          => FLASH_CLK,
-    SPI_SDO_OUT          => FLASH_DIN,
-    SPI_SDI_IN           => FLASH_DOUT
-    );
-
-
---	SFP_TXDIS(1)	<=	sfp_txdis_S(1);
-	SFP_TXDIS		<=	sfp_txdis_S;
-	
-	-----------------------------------------------------------------------
-	-- Since there is nomore trb on this link, link-phase does not need to
-	-- be controlled. To avoid changing code, link-phase is faked here.
-	-----------------------------------------------------------------------
-	DUMMY_LINK_PHASE_PROC : process (soda_rxup_full_clk)
-	begin
-		if rising_edge(soda_rxup_full_clk) then
-			if (reset_i='1') then
-				soda_uplink_phase_S	<='0';
-			elsif (soda_uplink_phase_S='0') then
-				soda_uplink_phase_S	<='1';
-			else
-				soda_uplink_phase_S	<='0';
-			end if;
-		end if;
-	end process;
-	
-
----------------------------------------------------------------------------
--- The Soda Central 
----------------------------------------------------------------------------  
-
-	A_SODA_HUB : soda_hub
-		port map(
-			SYSCLK					=> soda_rxup_half_clk,
-			SODACLK					=>	soda_rxup_full_clk,
-			RESET						=> reset_i,
-			CLEAR						=> clear_i,
-			CLK_EN					=> '1',
-
-	--	SINGLE DUBPLEX UP-LINK TO THE TOP
-			RXUP_DLM_WORD_IN		=> soda_rxup_dlm_word_S,
-			RXUP_DLM_IN				=> soda_rxup_dlm_S,
-			TXUP_DLM_OUT			=> soda_txup_dlm_S, 
-			TXUP_DLM_WORD_OUT		=> soda_txup_dlm_word_S,
-			TXUP_DLM_PREVIEW_OUT	=> soda_txup_dlm_preview_S,
-			UPLINK_PHASE_IN		=> soda_uplink_phase_S,
-	--	MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
-			RXDN_DLM_WORD_IN		=> soda_rxdn_dlm_word_S,
-			RXDN_DLM_IN				=> soda_rxdn_dlm_S,
-			TXDN_DLM_OUT			=> soda_txdn_dlm_S, 
-			TXDN_DLM_WORD_OUT		=> soda_txdn_dlm_word_S,
-			TXDN_DLM_PREVIEW_OUT	=> soda_txdn_dlm_preview_S,
-			DNLINK_PHASE_IN		=> soda_dnlink_phase_S,	
-
-			SODA_DATA_IN			=> soda_data_in,
-			SODA_DATA_OUT			=> soda_data_out,
-			SODA_ADDR_IN			=> soda_addr,
-			SODA_READ_IN			=> soda_read,
-			SODA_WRITE_IN			=> soda_write,
-			SODA_ACK_OUT			=> soda_ack,
-			LEDS_OUT					=>	soda_leds,
-			LINK_DEBUG_IN			=> link_debug_in_S
-		);
-
-
-		downlink_reset	<=	reset_i;	--'1'	when (reset_i = '1' or uplink_ready_S = '0') else '0';
-		downlink_clear	<=	clear_i;	--'1'	when (clear_i = '1' or uplink_ready_S = '0') else '0';
-
-		
-		THE_SODA_HUB_SYNC_DOWNLINK : soda_only_ecp3_sfp_4_sync_down
-			generic map(
-				SERDES_NUM			=> 0, --number of serdes in quad
-				IS_SYNC_SLAVE		=> c_NO
-				)
-			port map(
-				OSC_CLK											=> clk_200_osc,
-				TX_DATACLK										=> soda_rxup_full_clk,
-				SYSCLK											=> clk_100_osc,	-- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
-				RESET												=> downlink_reset,
-				CLEAR												=> downlink_clear,
-				---------------------------------------------------------------------------------------------------------------------------------------------------------
---				LINK_DISABLE_IN								=> sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
-				---------------------------------------------------------------------------------------------------------------------------------------------------------
-				RX_HALF_CLK_OUT(0)							=> soda_rxdn_half_clk(0),
-				RX_HALF_CLK_OUT(1)							=> soda_rxdn_half_clk(1),
-				RX_HALF_CLK_OUT(2)							=> soda_rxdn_half_clk(2),
-				RX_HALF_CLK_OUT(3)							=> soda_rxdn_half_clk(3),
-
-				RX_FULL_CLK_OUT(0)							=> soda_rxdn_full_clk(0),	-- needed for sync replies i.e. calibration
-				RX_FULL_CLK_OUT(1)							=> soda_rxdn_full_clk(1),	-- needed for sync replies i.e. calibration
-				RX_FULL_CLK_OUT(2)							=> soda_rxdn_full_clk(2),	-- needed for sync replies i.e. calibration
-				RX_FULL_CLK_OUT(3)							=> soda_rxdn_full_clk(3),	-- needed for sync replies i.e. calibration
-
-				TX_HALF_CLK_OUT(0)							=> soda_txdn_half_clk(0),
-				TX_HALF_CLK_OUT(1)							=> soda_txdn_half_clk(1),
-				TX_HALF_CLK_OUT(2)							=> soda_txdn_half_clk(2),
-				TX_HALF_CLK_OUT(3)							=> soda_txdn_half_clk(3),
-
-				TX_FULL_CLK_OUT(0)							=> soda_txdn_full_clk(0),
-				TX_FULL_CLK_OUT(1)							=> soda_txdn_full_clk(1),
-				TX_FULL_CLK_OUT(2)							=> soda_txdn_full_clk(2),
-				TX_FULL_CLK_OUT(3)							=> soda_txdn_full_clk(3),
-
-				RX_DLM_OUT(0)									=> soda_rxdn_dlm_S(0),
-				RX_DLM_OUT(1)									=> soda_rxdn_dlm_S(1),
-				RX_DLM_OUT(2)									=> soda_rxdn_dlm_S(2),
-				RX_DLM_OUT(3)									=> soda_rxdn_dlm_S(3),
-				
-				RX_DLM_WORD_OUT(0)							=> soda_rxdn_dlm_word_S(0),
-				RX_DLM_WORD_OUT(1)							=> soda_rxdn_dlm_word_S(1),
-				RX_DLM_WORD_OUT(2)							=> soda_rxdn_dlm_word_S(2),
-				RX_DLM_WORD_OUT(3)							=> soda_rxdn_dlm_word_S(3),
-				
-				TX_DLM_IN(0)									=> soda_txdn_dlm_S(0),
-				TX_DLM_IN(1)									=> soda_txdn_dlm_S(1),
-				TX_DLM_IN(2)									=> soda_txdn_dlm_S(2),
-				TX_DLM_IN(3)									=> soda_txdn_dlm_S(3),
-				
-				TX_DLM_WORD_IN(0)								=> soda_txdn_dlm_word_S(0),
-				TX_DLM_WORD_IN(1)								=> soda_txdn_dlm_word_S(1),
-				TX_DLM_WORD_IN(2)								=> soda_txdn_dlm_word_S(2),
-				TX_DLM_WORD_IN(3)								=> soda_txdn_dlm_word_S(3),
-
-				TX_DLM_PREVIEW_IN(0)							=> soda_txdn_dlm_preview_S(0),			--PL!
-				TX_DLM_PREVIEW_IN(1)							=> soda_txdn_dlm_preview_S(1),			--PL!
-				TX_DLM_PREVIEW_IN(2)							=> soda_txdn_dlm_preview_S(2),			--PL!
-				TX_DLM_PREVIEW_IN(3)							=> soda_txdn_dlm_preview_S(3),			--PL!
-
-				LINK_PHASE_OUT(0)								=>	soda_dnlink_phase_S(0),				--PL!
-				LINK_PHASE_OUT(1)								=>	soda_dnlink_phase_S(1),				--PL!
-				LINK_PHASE_OUT(2)								=>	soda_dnlink_phase_S(2),				--PL!
-				LINK_PHASE_OUT(3)								=>	soda_dnlink_phase_S(3),				--PL!
-
-				--SFP Connection
-				SD_RXD_P_IN(0)									=> SERDES_ADDON_RX(0),			-- B0
-				SD_RXD_P_IN(1)									=> SERDES_ADDON_RX(1),
-				SD_RXD_P_IN(2)									=> SERDES_ADDON_RX(10),			-- B1
-				SD_RXD_P_IN(3)									=> SERDES_ADDON_RX(11),	
-				SD_RXD_N_IN(0)									=> SERDES_ADDON_RX(2),			-- B2
-				SD_RXD_N_IN(1)									=> SERDES_ADDON_RX(3),
-				SD_RXD_N_IN(2)									=> SERDES_ADDON_RX(6),			-- B3
-				SD_RXD_N_IN(3)									=> SERDES_ADDON_RX(7),
-				SD_TXD_P_OUT(0)								=> SERDES_ADDON_TX(0),			-- B0
-				SD_TXD_P_OUT(1)								=> SERDES_ADDON_TX(1),
-				SD_TXD_P_OUT(2)								=> SERDES_ADDON_TX(10),			-- B1
-				SD_TXD_P_OUT(3)								=> SERDES_ADDON_TX(11),
-				SD_TXD_N_OUT(0)								=> SERDES_ADDON_TX(2),			-- B2
-				SD_TXD_N_OUT(1)								=> SERDES_ADDON_TX(3),
-				SD_TXD_N_OUT(2)								=> SERDES_ADDON_TX(6),			-- B3
-				SD_TXD_N_OUT(3)								=> SERDES_ADDON_TX(7),
-				SD_REFCLK_P_IN									=> (others => '0'),
-				SD_REFCLK_N_IN									=> ('0','0','0','0'),
-				SD_PRSNT_N_IN(0)								=> SFP_MOD0(1),
-				SD_PRSNT_N_IN(1)								=> SFP_MOD0(6),
-				SD_PRSNT_N_IN(2)								=> SFP_MOD0(2),
-				SD_PRSNT_N_IN(3)								=> SFP_MOD0(4),
-				SD_LOS_IN(0)									=> SFP_LOS(1),
-				SD_LOS_IN(1)									=> SFP_LOS(6),
-				SD_LOS_IN(2)									=> SFP_LOS(2),
-				SD_LOS_IN(3)									=> SFP_LOS(4),
-				SD_TXDIS_OUT(0)								=> sfp_txdis_S(1),
-				SD_TXDIS_OUT(1)								=> sfp_txdis_S(6),
-				SD_TXDIS_OUT(2)								=> sfp_txdis_S(2),
-				SD_TXDIS_OUT(3)								=> sfp_txdis_S(4),
-
-				SCI_DATA_IN										=> sci2_data_in,
-				SCI_DATA_OUT									=> sci2_data_out,
-				SCI_ADDR											=> sci2_addr,
-				SCI_READ											=> sci2_read,
-				SCI_WRITE										=> sci2_write,
-				SCI_ACK											=> sci2_ack, 
-				SCI_NACK											=> sci2_nack
-		);
-
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
-
-	LED_ORANGE <= time_counter(26);
-	LED_YELLOW <= time_counter(26);
-	LED_GREEN  <= time_counter(26);
-	LED_RED    <= time_counter(26);
----------------------------------------------------------------------------
--- DEBUG
----------------------------------------------------------------------------    
-	link_debug_in_S(31 downto 16)	<= med_stat_op(15 downto 0);
-	link_debug_in_S(15 downto 0)	<= (3 => pll_lock, others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-	blink : process (clk_100_osc)
-	begin
-		if rising_edge(clk_100_osc) then
-			if (time_counter = x"FFFFFFFF") then
-				time_counter <= x"00000000";
-			else
-				time_counter <= time_counter + 1;
-			end if;
-		end if;
-   end process;
-
-end Cu_trb3_periph_soda_hub_arch;
\ No newline at end of file
diff --git a/code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd b/code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd
deleted file mode 100644
index a646ea3..0000000
--- a/code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd
+++ /dev/null
@@ -1,1052 +0,0 @@
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-
-entity Cu_trb_net16_soda_syncUP_ecp3_sfp is
-	port(
-		OSCCLK					: in std_logic; -- 200 MHz reference clock
-		SYSCLK					: in std_logic; -- 100 MHz main clock net, synchronous to RX clock
-		RESET						: in std_logic; -- synchronous reset
-		CLEAR						: in std_logic; -- asynchronous reset
-		--Internal Connection TX
-		MED_DATA_IN				: in std_logic_vector(c_DATA_WIDTH-1 downto 0);
-		MED_PACKET_NUM_IN		: in std_logic_vector(c_NUM_WIDTH-1 downto 0);
-		MED_DATAREADY_IN		: in std_logic;
-		MED_READ_OUT			: out std_logic := '0';
-		--Internal Connection RX
-		MED_DATA_OUT			: out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
-		MED_PACKET_NUM_OUT	: out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
-		MED_DATAREADY_OUT		: out std_logic := '0';
-		MED_READ_IN				: in std_logic;
-
-		--Copper SFP Connection
-		CU_RXD_P_IN				: in std_logic;
-		CU_RXD_N_IN				: in std_logic;
-		CU_TXD_P_OUT			: out std_logic;
-		CU_TXD_N_OUT			: out std_logic;
-		CU_PRSNT_N_IN			: in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		CU_LOS_IN				: in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		CU_TXDIS_OUT			: out std_logic := '0'; -- SFP disable
-		--Fiber/sync SFP Connection
-		SYNC_RX_HALF_CLK_OUT	: out std_logic := '0'; --received 100 MHz
-		SYNC_RX_FULL_CLK_OUT	: out std_logic := '0'; --received 200 MHz
-		SYNC_TX_HALF_CLK_OUT	: out std_logic := '0'; --received 100 MHz
-		SYNC_TX_FULL_CLK_OUT	: out std_logic := '0'; --received 200 MHz
-		SYNC_TX_DLM_IN			: in  std_logic;
-		SYNC_TX_DLM_WORD_IN	: in  std_logic_vector(7 downto 0);
-		SYNC_RX_DLM_OUT		: out  std_logic;
-		SYNC_RX_DLM_WORD_OUT	: out  std_logic_vector(7 downto 0);
-		SYNC_RXD_P_IN			: in std_logic;
-		SYNC_RXD_N_IN			: in std_logic;
-		SYNC_TXD_P_OUT			: out std_logic;
-		SYNC_TXD_N_OUT			: out std_logic;
-		SYNC_PRSNT_N_IN		: in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		SYNC_LOS_IN				: in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		SYNC_TXDIS_OUT			: out std_logic := '0'; -- SFP disable
-		--Control Interface
-		SCI_DATA_IN				: in std_logic_vector(7 downto 0) := (others => '0');
-		SCI_DATA_OUT			: out std_logic_vector(7 downto 0) := (others => '0');
-		SCI_ADDR					: in std_logic_vector(8 downto 0) := (others => '0');
-		SCI_READ					: in std_logic := '0';
-		SCI_WRITE				: in std_logic := '0';
-		SCI_ACK					: out std_logic := '0';
-		SCI_NACK					: out std_logic := '0';
-
-		TX_READY_CH3			: out std_logic;
-		-- Status and control port
-		STAT_OP					: out std_logic_vector (15 downto 0);
-		CTRL_OP					: in std_logic_vector (15 downto 0) := (others => '0');
-		STAT_DEBUG				: out std_logic_vector (63 downto 0);
-		CTRL_DEBUG				: in std_logic_vector (63 downto 0) := (others => '0')
-	);
-end entity;
-
-architecture Cu_trb_net16_soda_syncUP_ecp3_sfp_arch of Cu_trb_net16_soda_syncUP_ecp3_sfp is
-
-
-  -- Placer Directives
-  attribute HGROUP : string;
-  -- for whole architecture
-  attribute HGROUP of  Cu_trb_net16_soda_syncUP_ecp3_sfp_arch : architecture  is "media_interface_group";
-  attribute syn_sharing : string;
-  attribute syn_sharing of  Cu_trb_net16_soda_syncUP_ecp3_sfp_arch : architecture is "off";
-
-	component sfp_2_200_int
-		port
-			(
-			hdinp_ch1, hdinn_ch1    :   in std_logic;
-			hdoutp_ch1, hdoutn_ch1   :   out std_logic;
-			sci_sel_ch1    :   in std_logic;
-			rxiclk_ch1    :   in std_logic;
-			txiclk_ch1    :   in std_logic;
-			rx_full_clk_ch1   :   out std_logic;
-			rx_half_clk_ch1   :   out std_logic;
-			tx_full_clk_ch1   :   out std_logic;
-			tx_half_clk_ch1   :   out std_logic;
-			fpga_rxrefclk_ch1    :   in std_logic;
-			txdata_ch1    :   in std_logic_vector (15 downto 0);
-			tx_k_ch1    :   in std_logic_vector (1 downto 0);
-			tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
-			tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
-			rxdata_ch1   :   out std_logic_vector (15 downto 0);
-			rx_k_ch1   :   out std_logic_vector (1 downto 0);
-			rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
-			rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
-			rx_serdes_rst_ch1_c    :   in std_logic;
-			sb_felb_ch1_c    :   in std_logic;
-			sb_felb_rst_ch1_c    :   in std_logic;
-			tx_pcs_rst_ch1_c    :   in std_logic;
-			tx_pwrup_ch1_c    :   in std_logic;
-			rx_pcs_rst_ch1_c    :   in std_logic;
-			rx_pwrup_ch1_c    :   in std_logic;
-			rx_los_low_ch1_s   :   out std_logic;
-			lsm_status_ch1_s   :   out std_logic;
-			rx_cdr_lol_ch1_s   :   out std_logic;
-			tx_div2_mode_ch1_c   : in std_logic;
-			rx_div2_mode_ch1_c   : in std_logic;
-
-			hdinp_ch3, hdinn_ch3    :   in std_logic;
-			hdoutp_ch3, hdoutn_ch3   :   out std_logic;
-			sci_sel_ch3    :   in std_logic;
-			txiclk_ch3    :   in std_logic;
-			rx_full_clk_ch3   :   out std_logic;
-			rx_half_clk_ch3   :   out std_logic;
-			tx_full_clk_ch3   :   out std_logic;
-			tx_half_clk_ch3   :   out std_logic;
-			fpga_rxrefclk_ch3    :   in std_logic;
-			txdata_ch3    :   in std_logic_vector (7 downto 0);
-			tx_k_ch3    :   in std_logic;
-			tx_force_disp_ch3    :   in std_logic;
-			tx_disp_sel_ch3    :   in std_logic;
-			rxdata_ch3   :   out std_logic_vector (7 downto 0);
-			rx_k_ch3   :   out std_logic;
-			rx_disp_err_ch3   :   out std_logic;
-			rx_cv_err_ch3   :   out std_logic;
-			rx_serdes_rst_ch3_c    :   in std_logic;
-			sb_felb_ch3_c    :   in std_logic;
-			sb_felb_rst_ch3_c    :   in std_logic;
-			tx_pcs_rst_ch3_c    :   in std_logic;
-			tx_pwrup_ch3_c    :   in std_logic;
-			rx_pcs_rst_ch3_c    :   in std_logic;
-			rx_pwrup_ch3_c    :   in std_logic;
-			rx_los_low_ch3_s   :   out std_logic;
-			lsm_status_ch3_s   :   out std_logic;
-			rx_cdr_lol_ch3_s   :   out std_logic;
-			tx_div2_mode_ch3_c   : in std_logic;
-			rx_div2_mode_ch3_c   : in std_logic;
-			---- Miscillaneous ports
-			sci_wrdata    :   in std_logic_vector (7 downto 0);
-			sci_addr    :   in std_logic_vector (5 downto 0);
-			sci_rddata   :   out std_logic_vector (7 downto 0);
-			sci_sel_quad    :   in std_logic;
-			sci_rd    :   in std_logic;
-			sci_wrn    :   in std_logic;
-			fpga_txrefclk  :   in std_logic;
-			tx_serdes_rst_c    :   in std_logic;
-			tx_pll_lol_qd_s   :   out std_logic;
-			tx_sync_qd_c    :   in std_logic;
-			rst_qd_c    :   in std_logic;
-			refclk2fpga   :   out std_logic;
-			serdes_rst_qd_c    :   in std_logic
-		);
-	end component;
-
-	type t_sync_tx_proc_state is (cSEND_IDLE,cSEND_DLM);	--,cFIFO_READ);
-	signal sync_tx_proc_state		: t_sync_tx_proc_state;
-
-
-	signal refck2core             : std_logic;
-	--  signal clock                  : std_logic;
-	--reset signals
-	signal ffc_quad_rst           : std_logic;
-	signal ffc_lane_tx_rst        : std_logic;
-	signal ffc_lane_rx_rst        : std_logic;
-	--serdes connections
-	signal tx_data                : std_logic_vector(15 downto 0);
-	signal tx_k                   : std_logic_vector(1 downto 0);
-	signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals
-	signal rx_k                   : std_logic_vector(1 downto 0);  -- delayed signals
-	signal comb_rx_data           : std_logic_vector(15 downto 0); -- original signals from SFP
-	signal comb_rx_k              : std_logic_vector(1 downto 0);  -- original signals from SFP
-	signal link_ok                : std_logic_vector(0 downto 0);
-	signal link_error             : std_logic_vector(8 downto 0);
-	signal ff_txhalfclk           : std_logic;
-	signal ff_rxhalfclk			      : std_logic;
-	signal ff_rxfullclk           : std_logic;
-	--rx fifo signals
-	signal fifo_rx_rd_en          : std_logic;
-	signal fifo_rx_wr_en          : std_logic;
-	signal fifo_rx_reset          : std_logic;
-	signal fifo_rx_din            : std_logic_vector(17 downto 0);
-	signal fifo_rx_dout           : std_logic_vector(17 downto 0);
-	signal fifo_rx_full           : std_logic;
-	signal fifo_rx_empty          : std_logic;
-	--tx fifo signals
-	signal fifo_tx_rd_en          : std_logic;
-	signal fifo_tx_wr_en          : std_logic;
-	signal fifo_tx_reset          : std_logic;
-	signal fifo_tx_din            : std_logic_vector(17 downto 0);
-	signal fifo_tx_dout           : std_logic_vector(17 downto 0);
-	signal fifo_tx_full           : std_logic;
-	signal fifo_tx_empty          : std_logic;
-	signal fifo_tx_almost_full    : std_logic;
-	--rx path
-	signal rx_counter             : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-	signal buf_med_dataready_out  : std_logic;
-	signal buf_med_data_out       : std_logic_vector(c_DATA_WIDTH-1 downto 0);
-	signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-	signal last_rx                : std_logic_vector(8 downto 0);
-	signal last_fifo_rx_empty     : std_logic;
-	--tx path
-	signal last_fifo_tx_empty     : std_logic;
-	--link status
-	signal rx_k_q                 : std_logic_vector(1 downto 0);
-
-	signal quad_rst               : std_logic;
-	signal lane_rst               : std_logic;
-	signal tx_allow               : std_logic;
-	signal rx_allow               : std_logic;
-	signal tx_allow_qtx           : std_logic;
-
-	signal rx_allow_q             : std_logic; -- clock domain changed signal
-	signal tx_allow_q             : std_logic;
-	signal swap_bytes             : std_logic;
-	signal buf_stat_debug         : std_logic_vector(31 downto 0);
-
-	-- status inputs from SFP
-	signal sfp_prsnt_n            : std_logic; -- synchronized input signals
-	signal sfp_los                : std_logic; -- synchronized input signals
-
-	signal buf_STAT_OP            : std_logic_vector(15 downto 0);
-
-	signal led_counter            : unsigned(16 downto 0);
-	signal rx_led                 : std_logic;
-	signal tx_led                 : std_logic;
-
-
-	signal tx_correct             : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
-	signal first_idle             : std_logic; -- tag the first IDLE2 after data
-
-	signal reset_word_cnt				: unsigned(4 downto 0);
-	signal make_trbnet_reset			: std_logic;
-	signal make_trbnet_reset_q			: std_logic;
-	signal send_reset_words				: std_logic;
-	signal send_reset_words_q			: std_logic;
-	signal send_reset_in					: std_logic;
-	signal send_reset_in_qtx				: std_logic;
-	signal reset_i								: std_logic;
-	signal reset_i_rx							: std_logic;
-	signal pwr_up								: std_logic;
-
-	signal clk_sys								: std_logic;
-	signal clk_tx								: std_logic;
-	signal clk_rx								: std_logic;
-	signal clk_rxref							: std_logic;
-	signal clk_txref							: std_logic;
-  
-	-- Peter Schakel 3-dec-2014
-
-	signal sci_timer							: unsigned(12 downto 0) := (others => '0');
-	signal reset_n								: std_logic;
-	signal trb_rx_serdes_rst				: std_logic;
-	signal trb_rx_cdr_lol					: std_logic;
-	signal trb_rx_los_low					: std_logic;
-	signal trb_rx_pcs_rst					: std_logic;
-	signal trb_tx_pcs_rst					: std_logic;
-	signal rst_qd								: std_logic;
-	signal rst_qd1								: std_logic;
-	signal rst_qd3								: std_logic;
-	signal link_OK_S							: std_logic;
-	signal trb_rx_fsm_state					: std_logic_vector(3 downto 0);
-	signal trb_tx_fsm_state					: std_logic_vector(3 downto 0);
-	signal sync_rx_fsm_state				: std_logic_vector(3 downto 0);
-	signal sync_tx_fsm_state				: std_logic_vector(3 downto 0);
- 	signal clk_200_osc						: std_logic;
-	signal sync_rx_full_clk					: std_logic;
-	signal sync_rx_half_clk					: std_logic;
-	signal sync_tx_full_clk					: std_logic;
-	signal sync_tx_half_clk					: std_logic;
-
-	signal sync_tx_data						: std_logic_vector(7 downto 0);
-	signal sync_tx_k							: std_logic;
-	signal SYNC_TX_DLM_IN_S						: std_logic;
-	signal sync_rx_data						: std_logic_vector(7 downto 0);
-	signal sync_rx_k							: std_logic;
-	signal sync_rx_error						: std_logic;
-	signal sync_rx_serdes_rst				: std_logic;
-	signal sync_tx_pcs_rst					: std_logic;
-	signal sync_rx_pcs_rst					: std_logic;
-	signal sync_rx_los_low					: std_logic;
-	signal sync_lsm_status					: std_logic;
-	signal sync_rx_cdr_lol					: std_logic;
-	signal dlm_fifo_rd_en					: std_logic;
-	signal dlm_fifo_empty					: std_logic;
-	signal dlm_fifo_reading					: std_logic;
-	signal dlm_received_S					: std_logic;
-
-	signal syncfifo_din						: std_logic_vector(17 downto 0);
-	signal syncfifo_dout						: std_logic_vector(17 downto 0);
-
-	type	sci_ctrl	is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-	signal sci_state							: sci_ctrl;
-	
-	signal sci_ch_i							: std_logic_vector(3 downto 0);
-	signal sci_qd_i							: std_logic;
-	signal sci_reg_i							: std_logic;
-	signal sci_addr_i							: std_logic_vector(8 downto 0);
-	signal sci_data_in_i						: std_logic_vector(7 downto 0);
-	signal sci_data_out_i					: std_logic_vector(7 downto 0);
-	signal sci_read_i							: std_logic;
-	signal sci_write_i						: std_logic;
-	signal sci_write_shift_i				: std_logic_vector(2 downto 0);
-	signal sci_read_shift_i					: std_logic_vector(2 downto 0);  
-
-	signal tx_pll_lol_qd_i					: std_logic;
-
-	signal wa_position						: std_logic_vector(15 downto 0) := x"FFFF";
-	signal wa_position_rx					: std_logic_vector(15 downto 0) := x"FFFF";
-	signal sync_wa_position_rx				: std_logic_vector(15 downto 0) := x"FFFF";
-	signal sync_tx_allow						: std_logic;
-	signal sync_rx_allow						: std_logic;
-	signal sync_tx_allow_q					: std_logic;
-	signal sync_rx_allow_q					: std_logic;
-	signal link_phase_S						: std_logic;	--PL!
-	signal request_retr_i					: std_logic;
-	signal start_retr_i						: std_logic;
-	signal request_retr_position_i		: std_logic_vector(7 downto 0);
-	signal start_retr_position_i			: std_logic_vector(7 downto 0);
-	signal send_link_reset_i				: std_logic;
-	signal make_link_reset_i				: std_logic;
-
-	attribute syn_keep									: boolean;
-	attribute syn_preserve								: boolean;
-	attribute syn_keep		of led_counter			: signal is true;
-	attribute syn_keep		of send_reset_in		: signal is true;
-	attribute syn_keep		of reset_i				: signal is true;
-	attribute syn_preserve	of reset_i				: signal is true;
-	attribute syn_preserve	of sci_ch_i				: signal is true;--
-	attribute syn_keep		of sci_ch_i				: signal is true;--
-	attribute syn_preserve	of sci_addr_i			: signal is true;--
-	attribute syn_keep		of sci_addr_i			: signal is true;--
-	attribute syn_preserve	of sci_data_in_i		: signal is true;--
-	attribute syn_keep		of sci_data_in_i		: signal is true;--
-	attribute syn_preserve	of sci_data_out_i		: signal is true;--
-	attribute syn_keep		of sci_data_out_i		: signal is true;--
-	attribute syn_preserve	of sci_read_i			: signal is true;--
-	attribute syn_keep		of sci_read_i			: signal is true;--
-	attribute syn_preserve	of sci_write_i			: signal is true;--
-	attribute syn_keep		of sci_write_i			: signal is true;--
-	attribute syn_preserve	of sci_write_shift_i	: signal is true;--
-	attribute syn_keep		of sci_write_shift_i	: signal is true;--
-	attribute syn_preserve	of	sci_read_shift_i	: signal is true;--
-	attribute syn_keep		of sci_read_shift_i	: signal is true;--
-	attribute syn_preserve	of	wa_position			: signal is true;--
-	attribute syn_keep		of wa_position			: signal is true;--
-	attribute syn_preserve	of	wa_position_rx		: signal is true;--
-	attribute syn_keep		of wa_position_rx		: signal is true;--
-
-begin
-
-clk_200_osc				<= OSCCLK;
-
-SYNC_RX_HALF_CLK_OUT	<= sync_rx_half_clk;
-SYNC_RX_FULL_CLK_OUT	<= sync_rx_full_clk;
-SYNC_TX_HALF_CLK_OUT	<= sync_tx_half_clk;
-SYNC_TX_FULL_CLK_OUT	<= sync_tx_full_clk;
---RX_CDR_LOL_OUT		<= rx_cdr_lol;	
-
-clk_sys					<= SYSCLK;
-clk_tx					<= SYSCLK;
-clk_rx					<= ff_rxhalfclk;
-clk_rxref				<= OSCCLK;
-clk_txref				<= OSCCLK;
-
---sd_los_i			 					<= SD_LOS_IN when rising_edge(SYSCLK);	-- PL!
-
---------------------------------------------------------------------------
--- Internal Lane Resets
---------------------------------------------------------------------------
-  PROC_RESET : process(clk_sys)
-    begin
-      if rising_edge(clk_sys) then
-        reset_i <= RESET;
-        send_reset_in <= ctrl_op(15);
-        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
-      end if;
-    end process;
-
---------------------------------------------------------------------------
--- Synchronizer stages
---------------------------------------------------------------------------
-
--- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
-THE_SFP_STATUS_SYNC: signal_sync
-  generic map(
-    DEPTH => 3,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => sync_prsnt_n_in,
-    D_IN(1)  => sync_los_in,
-    CLK0     => clk_sys,
-    CLK1     => clk_sys,
-    D_OUT(0) => sfp_prsnt_n,
-    D_OUT(1) => sfp_los
-    );
-
-
-THE_RX_K_SYNC: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 4
-    )
-  port map(
-    RESET             => reset_i,
-    D_IN(1 downto 0)  => comb_rx_k,
-    D_IN(2)           => send_reset_words,
-    D_IN(3)           => make_trbnet_reset,
-    CLK0              => clk_rx, -- CHANGED
-    CLK1              => clk_sys,
-    D_OUT(1 downto 0) => rx_k_q,
-    D_OUT(2)          => send_reset_words_q,
-    D_OUT(3)          => make_trbnet_reset_q
-    );
-
-THE_RX_DATA_DELAY: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 16
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN     => comb_rx_data,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT    => rx_data
-    );
-
-THE_RX_K_DELAY: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN     => comb_rx_k,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT    => rx_k
-    );
-
-THE_RX_RESET: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 1
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => reset_i,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT(0) => reset_i_rx
-    );
-
--- Delay for ALLOW signals
-THE_RX_ALLOW_SYNC: signal_sync
-	generic map(
-		DEPTH => 2,
-		WIDTH => 2
-		)
-	port map(
-		RESET    => reset_i,
-		D_IN(0)  => rx_allow,
-		D_IN(1)  => tx_allow,
-		CLK0     => clk_sys,
-		CLK1     => clk_sys,
-		D_OUT(0) => rx_allow_q,
-		D_OUT(1) => tx_allow_q
-	);
-
-THE_TX_SYNC: signal_sync
-	generic map(
-		DEPTH => 1,
-		WIDTH => 2
-		)
-	port map(
-		RESET    => '0',
-		D_IN(0)  => send_reset_in,
-		D_IN(1)  => tx_allow,
-		CLK0     => clk_tx,
-		CLK1     => clk_tx,
-		D_OUT(0) => send_reset_in_qtx,
-		D_OUT(1) => tx_allow_qtx
-	);
-
---THE_DLM_IN_DELAY: signal_sync
---	generic map(
---		DEPTH => 1,
---		WIDTH => 1
---		)
---	port map(
---		RESET    => '0',
---		D_IN(0)  => SYNC_TX_DLM_IN,
---		CLK0     => sync_rx_full_clk,
---		CLK1     => sync_rx_full_clk,
---		D_OUT(0) => SYNC_TX_DLM_IN_S
---	);
---------------------------------------------------------------------------
--- Main control state machine, startup control for SFP
---------------------------------------------------------------------------
-
-THE_SFP_LSM: trb_net16_lsm_sfp
-    generic map (
-      HIGHSPEED_STARTUP => c_YES
-      )
-    port map(
-      SYSCLK            => clk_sys,
-      RESET             => reset_i,
-      CLEAR             => clear,
-      SFP_MISSING_IN    => sfp_prsnt_n,
-      SFP_LOS_IN        => sfp_los,
-      SD_LINK_OK_IN     => link_ok(0),
-      SD_LOS_IN         => link_error(8),
-      SD_TXCLK_BAD_IN   => link_error(5),
-      SD_RXCLK_BAD_IN   => link_error(4),
-      SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
-      SD_ALIGNMENT_IN	=> rx_k_q,
-      SD_CV_IN          => link_error(7 downto 6),
-      FULL_RESET_OUT    => quad_rst,
-      LANE_RESET_OUT    => lane_rst,
-      TX_ALLOW_OUT      => tx_allow,
-      RX_ALLOW_OUT      => rx_allow,
-      SWAP_BYTES_OUT    => swap_bytes,
-      STAT_OP           => buf_stat_op,
-      CTRL_OP           => ctrl_op,
-      STAT_DEBUG        => buf_stat_debug
-      );
-
-SYNC_TXDIS_OUT <= quad_rst or reset_i;
-
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
-ffc_quad_rst         <= quad_rst;
-ffc_lane_tx_rst      <= lane_rst;
-
-
-ffc_lane_rx_rst      <= lane_rst;
-
-
-
--- Instantiation of serdes module
-
-	THE_SERDES: sfp_2_200_int
-		port map(
-		HDINP_CH1           => CU_RXD_P_IN,
-		HDINN_CH1           => CU_RXD_N_IN,
-		HDOUTP_CH1          => CU_TXD_P_OUT,
-		HDOUTN_CH1          => CU_TXD_N_OUT,
-		SCI_SEL_CH1         => sci_ch_i(1),
-		RXICLK_CH1          => clk_rx,
-		TXICLK_CH1          => clk_tx,
-		RX_FULL_CLK_CH1     => ff_rxfullclk,
-		RX_HALF_CLK_CH1     => ff_rxhalfclk,
-		TX_FULL_CLK_CH1     => open,
-		TX_HALF_CLK_CH1     => ff_txhalfclk,
-		FPGA_RXREFCLK_CH1   => clk_rxref,
-		TXDATA_CH1          => tx_data,
-		TX_K_CH1            => tx_k,
-		TX_FORCE_DISP_CH1   => tx_correct,
-		TX_DISP_SEL_CH1     => "00",
-		RXDATA_CH1          => comb_rx_data,
-		RX_K_CH1            => comb_rx_k,
-		RX_DISP_ERR_CH1		=> open,
-		RX_CV_ERR_CH1			=> link_error(7 downto 6),
-		RX_SERDES_RST_CH1_C	=> trb_rx_serdes_rst,
-		SB_FELB_CH1_C			=> '0', --loopback enable
-		SB_FELB_RST_CH1_C		=> '0', --loopback reset
-		TX_PCS_RST_CH1_C		=> trb_tx_pcs_rst,	--'1', --tx power up
-		TX_PWRUP_CH1_C			=> '1', --tx power up
-		RX_PCS_RST_CH1_C		=> trb_rx_pcs_rst,	--'1', --rx power up
-		RX_PWRUP_CH1_C			=> '1', --rx power up
-		RX_LOS_LOW_CH1_S    => trb_rx_los_low,	--link_error(8),
-		LSM_STATUS_CH1_S    => link_ok(0),
-		RX_CDR_LOL_CH1_S    => trb_rx_cdr_lol,	--link_error(4),
-		TX_DIV2_MODE_CH1_C  => '0', --full rate
-		RX_DIV2_MODE_CH1_C  => '0', --full rate
-		
-		HDINP_CH3           => SYNC_RXD_P_IN,
-		HDINN_CH3           => SYNC_RXD_N_IN,
-		HDOUTP_CH3          => SYNC_TXD_P_OUT,
-		HDOUTN_CH3          => SYNC_TXD_N_OUT,
-		SCI_SEL_CH3         => sci_ch_i(3),
-		TXICLK_CH3          => sync_rx_full_clk,
-		RX_FULL_CLK_CH3     => sync_rx_full_clk,
-		RX_HALF_CLK_CH3     => sync_rx_half_clk,
-		TX_FULL_CLK_CH3     => sync_tx_full_clk,
-		TX_HALF_CLK_CH3     => sync_tx_half_clk,
-		FPGA_RXREFCLK_CH3   => clk_200_osc,
-		TXDATA_CH3          => sync_tx_data,
-		TX_K_CH3            => sync_tx_k,
-		TX_FORCE_DISP_CH3   => '0',
-		TX_DISP_SEL_CH3     => '0',
-		RXDATA_CH3          => sync_rx_data,
-		RX_K_CH3            => sync_rx_k,
-		RX_DISP_ERR_CH3     => open,
-		RX_CV_ERR_CH3       => sync_rx_error,
-		RX_SERDES_RST_CH3_C => sync_rx_serdes_rst,
-		SB_FELB_CH3_C       => '0', --loopback enable
-		SB_FELB_RST_CH3_C   => '0', --loopback reset
-		TX_PCS_RST_CH3_C     => sync_tx_pcs_rst,
-		TX_PWRUP_CH3_C       => '1',
-		RX_PCS_RST_CH3_C     => sync_rx_pcs_rst,
-		RX_PWRUP_CH3_C       => '1',
-		RX_LOS_LOW_CH3_S     => sync_rx_los_low,
-		LSM_STATUS_CH3_S     => sync_lsm_status,
-		RX_CDR_LOL_CH3_S     => sync_rx_cdr_lol,
-		TX_DIV2_MODE_CH3_C   => '0',
-		RX_DIV2_MODE_CH3_C   => '0',
-
-		SCI_WRDATA          => sci_data_in_i,
-		SCI_ADDR            => sci_addr_i(5 downto 0),
-		SCI_RDDATA          => sci_data_out_i,
-		SCI_SEL_QUAD        => sci_addr_i(8),
-		SCI_RD              => sci_read_i,
-		SCI_WRN             => sci_write_i,
-		FPGA_TXREFCLK       => clk_txref,
---		FPGA_TXREFCLK       => rx_full_clk,
-		TX_SERDES_RST_C     => CLEAR,
-		TX_PLL_LOL_QD_S     => link_error(5), 
-		TX_SYNC_QD_C			=> '0',
-		RST_QD_C					=> rst_qd,
-		REFCLK2FPGA				=> open,
-		SERDES_RST_QD_C     => ffc_quad_rst
-	);
-  
--------------------------------------------------------------------------
--- RX Fifo & Data output
--------------------------------------------------------------------------
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
-generic map(
-  USE_STATUS_FLAGS => c_NO
-       )
-port map( read_clock_in  => clk_sys,
-      write_clock_in     => clk_rx, -- CHANGED
-      read_enable_in     => fifo_rx_rd_en,
-      write_enable_in    => fifo_rx_wr_en,
-      fifo_gsr_in        => fifo_rx_reset,
-      write_data_in      => fifo_rx_din,
-      read_data_out      => fifo_rx_dout,
-      full_out           => fifo_rx_full,
-      empty_out          => fifo_rx_empty
-    );
-
-fifo_rx_reset <= reset_i or not rx_allow_q;
-fifo_rx_rd_en <= not fifo_rx_empty;
-
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
-THE_BYTE_SWAP_PROC: process
-  begin
-    wait until rising_edge(clk_rx);  --CHANGED
-    last_rx <= rx_k(1) & rx_data(15 downto 8);
-    if( swap_bytes = '0' ) then
-      fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
-      fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
-    else
-      fifo_rx_din   <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
-      fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
-    end if;
-  end process THE_BYTE_SWAP_PROC;
-
-buf_med_data_out          <= fifo_rx_dout(15 downto 0);
-buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
-buf_med_packet_num_out    <= rx_counter;
-med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
-
-
-THE_CNT_RESET_PROC : process
-  begin
-    wait until rising_edge(clk_rx);  --CHANGED
-    if reset_i_rx = '1' then
-      send_reset_words  <= '0';
-      make_trbnet_reset <= '0';
-      reset_word_cnt    <= (others => '0');
-    else
-      send_reset_words   <= '0';
-      make_trbnet_reset  <= '0';
-      if fifo_rx_din = "11" & x"FEFE" then
-        if reset_word_cnt(4) = '0' then
-          reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
-        else
-          send_reset_words <= '1';
-        end if;
-      else
-        reset_word_cnt    <= (others => '0');
-        make_trbnet_reset <= reset_word_cnt(4);
-      end if;
-    end if;
-  end process;
-
-
-THE_SYNC_PROC: process
-  begin
-    wait until rising_edge(clk_sys);
-    med_dataready_out     <= buf_med_dataready_out;
-    med_data_out          <= buf_med_data_out;
-    med_packet_num_out    <= buf_med_packet_num_out;
-    if reset_i = '1' then
-      med_dataready_out <= '0';
-    end if;
-  end process;
-
-
---rx packet counter
----------------------
-THE_RX_PACKETS_PROC: process( clk_sys )
-  begin
-    if( rising_edge(clk_sys) ) then
-      last_fifo_rx_empty <= fifo_rx_empty;
-      if reset_i = '1' or rx_allow_q = '0' then
-        rx_counter <= c_H0;
-      else
-        if( buf_med_dataready_out = '1' ) then
-          if( rx_counter = c_max_word_number ) then
-            rx_counter <= (others => '0');
-          else
-            rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
-          end if;
-        end if;
-      end if;
-    end if;
-  end process;
-
---TX Fifo & Data output to Serdes
----------------------
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
-  generic map(
-    USE_STATUS_FLAGS => c_NO
-        )
-  port map( read_clock_in => clk_tx,
-        write_clock_in    => clk_sys,
-        read_enable_in    => fifo_tx_rd_en,
-        write_enable_in   => fifo_tx_wr_en,
-        fifo_gsr_in       => fifo_tx_reset,
-        write_data_in     => fifo_tx_din,
-        read_data_out     => fifo_tx_dout,
-        full_out          => fifo_tx_full,
-        empty_out         => fifo_tx_empty,
-        almost_full_out   => fifo_tx_almost_full
-      );
-
-fifo_tx_reset <= reset_i or not tx_allow_q;
-fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
-fifo_tx_rd_en <= tx_allow_qtx;
-
-
-THE_SERDES_INPUT_PROC: process( clk_tx )
-  begin
-    if( rising_edge(clk_tx) ) then
-      last_fifo_tx_empty <= fifo_tx_empty;
-      first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
-      if send_reset_in = '1' then
-        tx_data <= x"FEFE";
-        tx_k <= "11";
-      elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
-        tx_data <= x"50bc";
-        tx_k <= "01";
-        tx_correct <= first_idle & '0';
-      else
-        tx_data <= fifo_tx_dout(15 downto 0);
-        tx_k <= "00";
-        tx_correct <= "00";
-      end if;
-    end if;
-  end process THE_SERDES_INPUT_PROC;
-
-  
-sync_rx_proc : process(sync_rx_full_clk)
-begin
-	if rising_edge(sync_rx_full_clk) then
-		SYNC_RX_DLM_OUT <= '0';
-		if dlm_received_S='1' then
-			dlm_received_S			<= '0';
-			SYNC_RX_DLM_OUT		<= '1';
-			SYNC_RX_DLM_WORD_OUT	<= sync_rx_data;
-		elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then
-			dlm_received_S		<= '1';
-		end if;
-	end if;
-end process;  
-
-sync_tx_fsm : process(sync_tx_full_clk)
-begin
-	if rising_edge(sync_tx_full_clk) then
-		case sync_tx_proc_state is
-			when cSEND_IDLE	=>
-				if (SYNC_TX_DLM_IN='0') then
-					sync_tx_proc_state	<= cSEND_IDLE;
---					dlm_fifo_rd_en			<= '0';
-					sync_tx_data			<= x"BC"; -- idle
-					sync_tx_k				<= '1';
-				else
-					sync_tx_proc_state	<= cSEND_DLM;
---					dlm_fifo_rd_en			<= '1';
-					sync_tx_data			<= x"DC"; -- dlm
-					sync_tx_k				<= '1';
-				end if;
---			when cFIFO_READ	=>
---				sync_tx_proc_state		<= cSEND_DLM;
---				dlm_fifo_rd_en				<= '0';
---				sync_tx_data				<= x"DC"; -- dlm
---				sync_tx_k					<= '1';
-			when cSEND_DLM	=>
-				sync_tx_proc_state	<= cSEND_IDLE;
---				dlm_fifo_rd_en			<= '0';
-				sync_tx_data			<= SYNC_TX_DLM_WORD_IN;	--syncfifo_dout(7 downto 0);
-				sync_tx_k				<= '0';
-		when others	=>
-				sync_tx_proc_state	<= cSEND_IDLE;
-				dlm_fifo_rd_en			<= '0';
-				sync_tx_data			<= x"BC"; -- idle
-				sync_tx_k				<= '1';
-		end case;
-	end if;
-end process;
-		
-		
---sync_tx_proc : process(sync_tx_full_clk)
---begin
-	--if rising_edge(sync_tx_full_clk) then
-		--if dlm_fifo_rd_en='1' then
-			--dlm_fifo_rd_en		<= '0';
-			--sync_tx_data		<= syncfifo_dout(7 downto 0);
-			--sync_tx_k			<= '0';
-		--elsif (dlm_fifo_empty='0') and (dlm_fifo_reading='1') then
-			--dlm_fifo_rd_en		<= '1';
-			--sync_tx_data		<= x"DC";
-			--sync_tx_k			<= '1';
-		--elsif dlm_fifo_empty='0' then
-			--dlm_fifo_reading	<= '1';
-			--dlm_fifo_rd_en		<= '0';
-			--sync_tx_data		<= x"BC"; -- idle
-			--sync_tx_k			<= '1';		
-		--else
-			--dlm_fifo_reading	<= '0';
-			--dlm_fifo_rd_en		<= '0';
-			--sync_tx_data		<= x"BC"; -- idle
-			--sync_tx_k			<= '1';
-		--end if;
-	--end if;
---end process;  
-
-link_error(8) <= trb_rx_los_low; -- loss of signal
-link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock 
-link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock
-
-reset_n <= '0' when (RESET='1') or (CLEAR='1')  else '1';
-
--------------------------------------------------      
--- Reset FSM & Link states
-------------------------------------------------- 
-THE_RX_FSM1: rx_reset_fsm
-	port map(
-		RST_N               => reset_n,
-		RX_REFCLK           => OSCCLK,
-		TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
-		RX_SERDES_RST_CH_C  => trb_rx_serdes_rst,
-		RX_CDR_LOL_CH_S     => trb_rx_cdr_lol,
-		RX_LOS_LOW_CH_S     => trb_rx_los_low,
-		RX_PCS_RST_CH_C     => trb_rx_pcs_rst,
-		WA_POSITION         => "0000",
-		STATE_OUT           => trb_rx_fsm_state
-	);
-
-link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';
-
-THE_TX_FSM1: tx_reset_fsm
-	port map(
-		RST_N           => reset_n,
-		TX_REFCLK       => OSCCLK,
-		TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-		RST_QD_C        => rst_qd1,
-		TX_PCS_RST_CH_C => trb_tx_pcs_rst,
-		STATE_OUT       => trb_tx_fsm_state	--open
-	);
-
-THE_RX_FSM3: rx_reset_fsm
-	port map(
-		RST_N               => reset_n,
-		RX_REFCLK           => sync_rx_full_clk,
-		TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
-		RX_SERDES_RST_CH_C  => sync_rx_serdes_rst,
-		RX_CDR_LOL_CH_S     => sync_rx_cdr_lol,
-		RX_LOS_LOW_CH_S     => sync_rx_los_low,
-		RX_PCS_RST_CH_C     => sync_rx_pcs_rst,
-		WA_POSITION         => sync_wa_position_rx(11 downto 8),
-		STATE_OUT           => sync_rx_fsm_state
-	);
-
-SYNC_WA_POSITION : process(sync_rx_full_clk) --??CLK)
-begin
-	if rising_edge(sync_rx_full_clk) then
-		sync_wa_position_rx <= wa_position;
-	end if;
-end process;
-
-THE_TX_FSM3 : tx_reset_fsm
-  port map(
-    RST_N           => reset_n,
-    TX_REFCLK       => OSCCLK,
-    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-    RST_QD_C        => rst_qd3,
-    TX_PCS_RST_CH_C => sync_tx_pcs_rst,
-    STATE_OUT       => sync_tx_fsm_state
-    );
-
---rst_qd			<= '1' when (rst_qd1='1') or (rst_qd3='1') else '0';
-rst_qd			<= RESET;
-
-TX_READY_CH3	<= '1' when (sync_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';  
-
------------------------------------------------------------------------------------------------------
--- SCI --gives access to serdes config port from slow control and reads word alignment every ~ 40 us
------------------------------------------------------------------------------------------------------
-PROC_SCI_CTRL: process(clk_sys)
-	variable cnt : integer range 0 to 4 := 0;
-begin
-	if( rising_edge(clk_sys) ) then
-		SCI_ACK <= '0';
-		case sci_state is
-			when IDLE =>
-				sci_ch_i        <= x"0";
-				sci_qd_i        <= '0';
-				sci_reg_i       <= '0';
-				sci_read_i      <= '0';
-				sci_write_i     <= '0';
-				sci_timer       <= sci_timer + 1;
-				if SCI_READ = '1' or SCI_WRITE = '1' then
-				sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-				sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-				sci_addr_i    <= SCI_ADDR;
-				sci_data_in_i <= SCI_DATA_IN;
-				sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-				sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-				sci_state     <= SCTRL;
-			elsif sci_timer(sci_timer'left) = '1' then
-				sci_timer     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;      
-		when SCTRL =>
-			if sci_reg_i = '1' then
-				--//			SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-				SCI_DATA_OUT  <= (others => '0');
-				SCI_ACK       <= '1';
-				sci_write_i   <= '0';
-				sci_read_i    <= '0';
-				sci_state     <= IDLE;
-			else
-				sci_state     <= SCTRL_WAIT;
-			end if;
-		when SCTRL_WAIT   =>
-			sci_state       <= SCTRL_WAIT2;
-		when SCTRL_WAIT2  =>
-			sci_state       <= SCTRL_FINISH;
-		when SCTRL_FINISH =>
-			SCI_DATA_OUT    <= sci_data_out_i;
-			SCI_ACK         <= '1';
-			sci_write_i     <= '0';
-			sci_read_i      <= '0';
-			sci_state       <= IDLE;
-
-		when GET_WA =>
-			if cnt = 4 then
-				cnt           := 0;
-				sci_state     <= IDLE;
-			else
-				sci_state     <= GET_WA_WAIT;
-				sci_addr_i    <= '0' & x"22";
-				sci_ch_i      <= x"0";
-				sci_ch_i(cnt) <= '1';
-				sci_read_i    <= '1';
-				end if;
-		when GET_WA_WAIT  =>
-			sci_state       <= GET_WA_WAIT2;
-		when GET_WA_WAIT2 =>
-			sci_state       <= GET_WA_FINISH;
-		when GET_WA_FINISH =>
-			wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-			sci_state       <= GET_WA;    
-			cnt             := cnt + 1;
-		end case;
-
-		if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-			SCI_NACK <= '1';
-		else
-			SCI_NACK <= '0';
-		end if;
-	end if;
-end process PROC_SCI_CTRL;
-
-----------------------
---Generate LED signals
-----------------------
-LED_PROC : process( clk_sys )
-	begin
-		if rising_edge(clk_sys) then
-			led_counter <= led_counter + to_unsigned(1,1);
-			if buf_med_dataready_out = '1' then
-				rx_led <= '1';
-			elsif led_counter = 0 then
-			rx_led <= '0';
-			end if;
-			if tx_k(0) = '0' then
-				tx_led <= '1';
-			elsif led_counter = 0 then
-				tx_led <= '0';
-			end if;
-		end if;
-	end process LED_PROC;
-
-
-stat_op(15)           <= send_reset_words_q;
-stat_op(14)           <= buf_stat_op(14);
-stat_op(13)           <= make_trbnet_reset_q;
-stat_op(12)           <= '0';
-stat_op(11)           <= tx_led; --tx led
-stat_op(10)           <= rx_led; --rx led
-stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
-
--- Debug output
-stat_debug(15 downto 0)  <= rx_data;
-stat_debug(17 downto 16) <= rx_k;
-stat_debug(19 downto 18) <= (others => '0');
-stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
-stat_debug(24)           <= fifo_rx_rd_en;
-stat_debug(25)           <= fifo_rx_wr_en;
-stat_debug(26)           <= fifo_rx_reset;
-stat_debug(27)           <= fifo_rx_empty;
-stat_debug(28)           <= fifo_rx_full;
-stat_debug(29)           <= last_rx(8);
-stat_debug(30)           <= rx_allow_q;
-stat_debug(41 downto 31) <= (others => '0');
-stat_debug(42)           <= clk_sys;
-stat_debug(43)           <= clk_sys;
-stat_debug(59 downto 44) <= (others => '0');
-stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
-
-
-end Cu_trb_net16_soda_syncUP_ecp3_sfp_arch;
\ No newline at end of file
diff --git a/code/Cu_trb_net16_soda_sync_ecp3_sfp.vhd b/code/Cu_trb_net16_soda_sync_ecp3_sfp.vhd
deleted file mode 100644
index 7eb154e..0000000
--- a/code/Cu_trb_net16_soda_sync_ecp3_sfp.vhd
+++ /dev/null
@@ -1,1073 +0,0 @@
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-
-entity Cu_trb_net16_soda_sync_ecp3_sfp is
-	port(
-		OSCCLK					: in std_logic; -- 200 MHz reference clock
-		SYSCLK					: in std_logic; -- 100 MHz main clock net, synchronous to RX clock
-		RESET						: in std_logic; -- synchronous reset
-		CLEAR						: in std_logic; -- asynchronous reset
-		--Internal Connection TX
-		MED_DATA_IN				: in std_logic_vector(c_DATA_WIDTH-1 downto 0);
-		MED_PACKET_NUM_IN		: in std_logic_vector(c_NUM_WIDTH-1 downto 0);
-		MED_DATAREADY_IN		: in std_logic;
-		MED_READ_OUT			: out std_logic := '0';
-		--Internal Connection RX
-		MED_DATA_OUT			: out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
-		MED_PACKET_NUM_OUT	: out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
-		MED_DATAREADY_OUT		: out std_logic := '0';
-		MED_READ_IN				: in std_logic;
-
-		--Copper SFP Connection
-		CU_RXD_P_IN				: in std_logic;
-		CU_RXD_N_IN				: in std_logic;
-		CU_TXD_P_OUT			: out std_logic;
-		CU_TXD_N_OUT			: out std_logic;
-		CU_PRSNT_N_IN			: in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		CU_LOS_IN				: in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		CU_TXDIS_OUT			: out std_logic := '0'; -- SFP disable
-		--Fiber/sync SFP Connection
-		SYNC_RX_HALF_CLK_OUT	: out std_logic := '0'; --received 100 MHz
-		SYNC_RX_FULL_CLK_OUT	: out std_logic := '0'; --received 200 MHz
-		SYNC_TX_HALF_CLK_OUT	: out std_logic := '0'; --received 100 MHz
-		SYNC_TX_FULL_CLK_OUT	: out std_logic := '0'; --received 200 MHz
-		SYNC_DLM_IN				: in  std_logic;
-		SYNC_DLM_WORD_IN		: in  std_logic_vector(7 downto 0);
-		SYNC_DLM_OUT			: out  std_logic;
-		SYNC_DLM_WORD_OUT		: out  std_logic_vector(7 downto 0);
-		SYNC_RXD_P_IN			: in std_logic;
-		SYNC_RXD_N_IN			: in std_logic;
-		SYNC_TXD_P_OUT			: out std_logic;
-		SYNC_TXD_N_OUT			: out std_logic;
-		SYNC_PRSNT_N_IN		: in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		SYNC_LOS_IN				: in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		SYNC_TXDIS_OUT			: out std_logic := '0'; -- SFP disable
-		--Control Interface
-		SCI_DATA_IN				: in std_logic_vector(7 downto 0) := (others => '0');
-		SCI_DATA_OUT			: out std_logic_vector(7 downto 0) := (others => '0');
-		SCI_ADDR					: in std_logic_vector(8 downto 0) := (others => '0');
-		SCI_READ					: in std_logic := '0';
-		SCI_WRITE				: in std_logic := '0';
-		SCI_ACK					: out std_logic := '0';
-		SCI_NACK					: out std_logic := '0';
-
-		TX_READY_CH3			: out std_logic;
-		-- Status and control port
-		STAT_OP					: out std_logic_vector (15 downto 0);
-		CTRL_OP					: in std_logic_vector (15 downto 0) := (others => '0');
-		STAT_DEBUG				: out std_logic_vector (63 downto 0);
-		CTRL_DEBUG				: in std_logic_vector (63 downto 0) := (others => '0')
-	);
-end entity;
-
-architecture Cu_trb_net16_soda_sync_ecp3_sfp_arch of Cu_trb_net16_soda_sync_ecp3_sfp is
-
-
-  -- Placer Directives
-  attribute HGROUP : string;
-  -- for whole architecture
-  attribute HGROUP of  Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture  is "media_interface_group";
-  attribute syn_sharing : string;
-  attribute syn_sharing of  Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture is "off";
-
-	component sfp_2_200_int
-		port
-			(
-			hdinp_ch1, hdinn_ch1    :   in std_logic;
-			hdoutp_ch1, hdoutn_ch1   :   out std_logic;
-			sci_sel_ch1    :   in std_logic;
-			rxiclk_ch1    :   in std_logic;
-			txiclk_ch1    :   in std_logic;
-			rx_full_clk_ch1   :   out std_logic;
-			rx_half_clk_ch1   :   out std_logic;
-			tx_full_clk_ch1   :   out std_logic;
-			tx_half_clk_ch1   :   out std_logic;
-			fpga_rxrefclk_ch1    :   in std_logic;
-			txdata_ch1    :   in std_logic_vector (15 downto 0);
-			tx_k_ch1    :   in std_logic_vector (1 downto 0);
-			tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
-			tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
-			rxdata_ch1   :   out std_logic_vector (15 downto 0);
-			rx_k_ch1   :   out std_logic_vector (1 downto 0);
-			rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
-			rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
-			rx_serdes_rst_ch1_c    :   in std_logic;
-			sb_felb_ch1_c    :   in std_logic;
-			sb_felb_rst_ch1_c    :   in std_logic;
-			tx_pcs_rst_ch1_c    :   in std_logic;
-			tx_pwrup_ch1_c    :   in std_logic;
-			rx_pcs_rst_ch1_c    :   in std_logic;
-			rx_pwrup_ch1_c    :   in std_logic;
-			rx_los_low_ch1_s   :   out std_logic;
-			lsm_status_ch1_s   :   out std_logic;
-			rx_cdr_lol_ch1_s   :   out std_logic;
-			tx_div2_mode_ch1_c   : in std_logic;
-			rx_div2_mode_ch1_c   : in std_logic;
-
-			hdinp_ch3, hdinn_ch3    :   in std_logic;
-			hdoutp_ch3, hdoutn_ch3   :   out std_logic;
-			sci_sel_ch3    :   in std_logic;
-			txiclk_ch3    :   in std_logic;
-			rx_full_clk_ch3   :   out std_logic;
-			rx_half_clk_ch3   :   out std_logic;
-			tx_full_clk_ch3   :   out std_logic;
-			tx_half_clk_ch3   :   out std_logic;
-			fpga_rxrefclk_ch3    :   in std_logic;
-			txdata_ch3    :   in std_logic_vector (7 downto 0);
-			tx_k_ch3    :   in std_logic;
-			tx_force_disp_ch3    :   in std_logic;
-			tx_disp_sel_ch3    :   in std_logic;
-			rxdata_ch3   :   out std_logic_vector (7 downto 0);
-			rx_k_ch3   :   out std_logic;
-			rx_disp_err_ch3   :   out std_logic;
-			rx_cv_err_ch3   :   out std_logic;
-			rx_serdes_rst_ch3_c    :   in std_logic;
-			sb_felb_ch3_c    :   in std_logic;
-			sb_felb_rst_ch3_c    :   in std_logic;
-			tx_pcs_rst_ch3_c    :   in std_logic;
-			tx_pwrup_ch3_c    :   in std_logic;
-			rx_pcs_rst_ch3_c    :   in std_logic;
-			rx_pwrup_ch3_c    :   in std_logic;
-			rx_los_low_ch3_s   :   out std_logic;
-			lsm_status_ch3_s   :   out std_logic;
-			rx_cdr_lol_ch3_s   :   out std_logic;
-			tx_div2_mode_ch3_c   : in std_logic;
-			rx_div2_mode_ch3_c   : in std_logic;
-			---- Miscillaneous ports
-			sci_wrdata    :   in std_logic_vector (7 downto 0);
-			sci_addr    :   in std_logic_vector (5 downto 0);
-			sci_rddata   :   out std_logic_vector (7 downto 0);
-			sci_sel_quad    :   in std_logic;
-			sci_rd    :   in std_logic;
-			sci_wrn    :   in std_logic;
-			fpga_txrefclk  :   in std_logic;
-			tx_serdes_rst_c    :   in std_logic;
-			tx_pll_lol_qd_s   :   out std_logic;
-			tx_sync_qd_c    :   in std_logic;
-			rst_qd_c    :   in std_logic;
-			refclk2fpga   :   out std_logic;
-			serdes_rst_qd_c    :   in std_logic
-		);
-	end component;
-
-	type t_sync_tx_proc_state is (cSEND_IDLE,cSEND_DLM,cFIFO_READ);
-	signal sync_tx_proc_state		: t_sync_tx_proc_state;
-
-
-	signal refck2core             : std_logic;
-	--  signal clock                  : std_logic;
-	--reset signals
-	signal ffc_quad_rst           : std_logic;
-	signal ffc_lane_tx_rst        : std_logic;
-	signal ffc_lane_rx_rst        : std_logic;
-	--serdes connections
-	signal tx_data                : std_logic_vector(15 downto 0);
-	signal tx_k                   : std_logic_vector(1 downto 0);
-	signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals
-	signal rx_k                   : std_logic_vector(1 downto 0);  -- delayed signals
-	signal comb_rx_data           : std_logic_vector(15 downto 0); -- original signals from SFP
-	signal comb_rx_k              : std_logic_vector(1 downto 0);  -- original signals from SFP
-	signal link_ok                : std_logic_vector(0 downto 0);
-	signal link_error             : std_logic_vector(8 downto 0);
-	signal ff_txhalfclk           : std_logic;
-	signal ff_rxhalfclk			      : std_logic;
-	signal ff_rxfullclk           : std_logic;
-	--rx fifo signals
-	signal fifo_rx_rd_en          : std_logic;
-	signal fifo_rx_wr_en          : std_logic;
-	signal fifo_rx_reset          : std_logic;
-	signal fifo_rx_din            : std_logic_vector(17 downto 0);
-	signal fifo_rx_dout           : std_logic_vector(17 downto 0);
-	signal fifo_rx_full           : std_logic;
-	signal fifo_rx_empty          : std_logic;
-	--tx fifo signals
-	signal fifo_tx_rd_en          : std_logic;
-	signal fifo_tx_wr_en          : std_logic;
-	signal fifo_tx_reset          : std_logic;
-	signal fifo_tx_din            : std_logic_vector(17 downto 0);
-	signal fifo_tx_dout           : std_logic_vector(17 downto 0);
-	signal fifo_tx_full           : std_logic;
-	signal fifo_tx_empty          : std_logic;
-	signal fifo_tx_almost_full    : std_logic;
-	--rx path
-	signal rx_counter             : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-	signal buf_med_dataready_out  : std_logic;
-	signal buf_med_data_out       : std_logic_vector(c_DATA_WIDTH-1 downto 0);
-	signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-	signal last_rx                : std_logic_vector(8 downto 0);
-	signal last_fifo_rx_empty     : std_logic;
-	--tx path
-	signal last_fifo_tx_empty     : std_logic;
-	--link status
-	signal rx_k_q                 : std_logic_vector(1 downto 0);
-
-	signal quad_rst               : std_logic;
-	signal lane_rst               : std_logic;
-	signal tx_allow               : std_logic;
-	signal rx_allow               : std_logic;
-	signal tx_allow_qtx           : std_logic;
-
-	signal rx_allow_q             : std_logic; -- clock domain changed signal
-	signal tx_allow_q             : std_logic;
-	signal swap_bytes             : std_logic;
-	signal buf_stat_debug         : std_logic_vector(31 downto 0);
-
-	-- status inputs from SFP
-	signal sfp_prsnt_n            : std_logic; -- synchronized input signals
-	signal sfp_los                : std_logic; -- synchronized input signals
-
-	signal buf_STAT_OP            : std_logic_vector(15 downto 0);
-
-	signal led_counter            : unsigned(16 downto 0);
-	signal rx_led                 : std_logic;
-	signal tx_led                 : std_logic;
-
-
-	signal tx_correct             : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
-	signal first_idle             : std_logic; -- tag the first IDLE2 after data
-
-	signal reset_word_cnt				: unsigned(4 downto 0);
-	signal make_trbnet_reset			: std_logic;
-	signal make_trbnet_reset_q			: std_logic;
-	signal send_reset_words				: std_logic;
-	signal send_reset_words_q			: std_logic;
-	signal send_reset_in					: std_logic;
-	signal send_reset_in_qtx				: std_logic;
-	signal reset_i								: std_logic;
-	signal reset_i_rx							: std_logic;
-	signal pwr_up								: std_logic;
-
-	signal clk_sys								: std_logic;
-	signal clk_tx								: std_logic;
-	signal clk_rx								: std_logic;
-	signal clk_rxref							: std_logic;
-	signal clk_txref							: std_logic;
-  
-	-- Peter Schakel 3-dec-2014
-
-	signal sci_timer							: unsigned(12 downto 0) := (others => '0');
-	signal reset_n								: std_logic;
-	signal trb_rx_serdes_rst				: std_logic;
-	signal trb_rx_cdr_lol					: std_logic;
-	signal trb_rx_los_low					: std_logic;
-	signal trb_rx_pcs_rst					: std_logic;
-	signal trb_tx_pcs_rst					: std_logic;
-	signal rst_qd								: std_logic;
-	signal rst_qd1								: std_logic;
-	signal rst_qd3								: std_logic;
-	signal link_OK_S							: std_logic;
-	signal trb_rx_fsm_state					: std_logic_vector(3 downto 0);
-	signal trb_tx_fsm_state					: std_logic_vector(3 downto 0);
-	signal sync_rx_fsm_state				: std_logic_vector(3 downto 0);
-	signal sync_tx_fsm_state				: std_logic_vector(3 downto 0);
- 	signal clk_200_osc						: std_logic;
-	signal sync_rx_full_clk					: std_logic;
-	signal sync_rx_half_clk					: std_logic;
-	signal sync_tx_full_clk					: std_logic;
-	signal sync_tx_half_clk					: std_logic;
-
-	signal sync_tx_data						: std_logic_vector(7 downto 0);
-	signal sync_tx_k							: std_logic;
-	signal sync_dlm_in_S						: std_logic;
-	signal sync_rx_data						: std_logic_vector(7 downto 0);
-	signal sync_rx_k							: std_logic;
-	signal sync_rx_error						: std_logic;
-	signal sync_rx_serdes_rst				: std_logic;
-	signal sync_tx_pcs_rst					: std_logic;
-	signal sync_rx_pcs_rst					: std_logic;
-	signal sync_rx_los_low					: std_logic;
-	signal sync_lsm_status					: std_logic;
-	signal sync_rx_cdr_lol					: std_logic;
-	signal dlm_fifo_rd_en					: std_logic;
-	signal dlm_fifo_empty					: std_logic;
-	signal dlm_fifo_reading					: std_logic;
-	signal dlm_received_S					: std_logic;
-
-	signal syncfifo_din						: std_logic_vector(17 downto 0);
-	signal syncfifo_dout						: std_logic_vector(17 downto 0);
-
-	type	sci_ctrl	is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-	signal sci_state							: sci_ctrl;
-	
-	signal sci_ch_i							: std_logic_vector(3 downto 0);
-	signal sci_qd_i							: std_logic;
-	signal sci_reg_i							: std_logic;
-	signal sci_addr_i							: std_logic_vector(8 downto 0);
-	signal sci_data_in_i						: std_logic_vector(7 downto 0);
-	signal sci_data_out_i					: std_logic_vector(7 downto 0);
-	signal sci_read_i							: std_logic;
-	signal sci_write_i						: std_logic;
-	signal sci_write_shift_i				: std_logic_vector(2 downto 0);
-	signal sci_read_shift_i					: std_logic_vector(2 downto 0);  
-
-	signal tx_pll_lol_qd_i					: std_logic;
-
-	signal wa_position						: std_logic_vector(15 downto 0) := x"FFFF";
-	signal wa_position_rx					: std_logic_vector(15 downto 0) := x"FFFF";
-	signal sync_wa_position_rx				: std_logic_vector(15 downto 0) := x"FFFF";
-	signal sync_tx_allow						: std_logic;
-	signal sync_rx_allow						: std_logic;
-	signal sync_tx_allow_q					: std_logic;
-	signal sync_rx_allow_q					: std_logic;
-	signal link_phase_S						: std_logic;	--PL!
-	signal request_retr_i					: std_logic;
-	signal start_retr_i						: std_logic;
-	signal request_retr_position_i		: std_logic_vector(7 downto 0);
-	signal start_retr_position_i			: std_logic_vector(7 downto 0);
-	signal send_link_reset_i				: std_logic;
-	signal make_link_reset_i				: std_logic;
-
-	attribute syn_keep									: boolean;
-	attribute syn_preserve								: boolean;
-	attribute syn_keep		of led_counter			: signal is true;
-	attribute syn_keep		of send_reset_in		: signal is true;
-	attribute syn_keep		of reset_i				: signal is true;
-	attribute syn_preserve	of reset_i				: signal is true;
-	attribute syn_preserve	of sci_ch_i				: signal is true;--
-	attribute syn_keep		of sci_ch_i				: signal is true;--
-	attribute syn_preserve	of sci_addr_i			: signal is true;--
-	attribute syn_keep		of sci_addr_i			: signal is true;--
-	attribute syn_preserve	of sci_data_in_i		: signal is true;--
-	attribute syn_keep		of sci_data_in_i		: signal is true;--
-	attribute syn_preserve	of sci_data_out_i		: signal is true;--
-	attribute syn_keep		of sci_data_out_i		: signal is true;--
-	attribute syn_preserve	of sci_read_i			: signal is true;--
-	attribute syn_keep		of sci_read_i			: signal is true;--
-	attribute syn_preserve	of sci_write_i			: signal is true;--
-	attribute syn_keep		of sci_write_i			: signal is true;--
-	attribute syn_preserve	of sci_write_shift_i	: signal is true;--
-	attribute syn_keep		of sci_write_shift_i	: signal is true;--
-	attribute syn_preserve	of	sci_read_shift_i	: signal is true;--
-	attribute syn_keep		of sci_read_shift_i	: signal is true;--
-	attribute syn_preserve	of	wa_position			: signal is true;--
-	attribute syn_keep		of wa_position			: signal is true;--
-	attribute syn_preserve	of	wa_position_rx		: signal is true;--
-	attribute syn_keep		of wa_position_rx		: signal is true;--
-
-begin
-
-clk_200_osc				<= OSCCLK;
-
-SYNC_RX_HALF_CLK_OUT	<= sync_rx_half_clk;
-SYNC_RX_FULL_CLK_OUT	<= sync_rx_full_clk;
-SYNC_TX_HALF_CLK_OUT	<= sync_tx_half_clk;
-SYNC_TX_FULL_CLK_OUT	<= sync_tx_full_clk;
---RX_CDR_LOL_OUT		<= rx_cdr_lol;	
-
-clk_sys					<= SYSCLK;
-clk_tx					<= SYSCLK;
-clk_rx					<= ff_rxhalfclk;
-clk_rxref				<= OSCCLK;
-clk_txref				<= OSCCLK;
-
---sd_los_i			 					<= SD_LOS_IN when rising_edge(SYSCLK);	-- PL!
-
---------------------------------------------------------------------------
--- Internal Lane Resets
---------------------------------------------------------------------------
-  PROC_RESET : process(clk_sys)
-    begin
-      if rising_edge(clk_sys) then
-        reset_i <= RESET;
-        send_reset_in <= ctrl_op(15);
-        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
-      end if;
-    end process;
-
---------------------------------------------------------------------------
--- Synchronizer stages
---------------------------------------------------------------------------
-
--- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
-THE_SFP_STATUS_SYNC: signal_sync
-  generic map(
-    DEPTH => 3,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => sync_prsnt_n_in,
-    D_IN(1)  => sync_los_in,
-    CLK0     => clk_sys,
-    CLK1     => clk_sys,
-    D_OUT(0) => sfp_prsnt_n,
-    D_OUT(1) => sfp_los
-    );
-
-
-THE_RX_K_SYNC: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 4
-    )
-  port map(
-    RESET             => reset_i,
-    D_IN(1 downto 0)  => comb_rx_k,
-    D_IN(2)           => send_reset_words,
-    D_IN(3)           => make_trbnet_reset,
-    CLK0              => clk_rx, -- CHANGED
-    CLK1              => clk_sys,
-    D_OUT(1 downto 0) => rx_k_q,
-    D_OUT(2)          => send_reset_words_q,
-    D_OUT(3)          => make_trbnet_reset_q
-    );
-
-THE_RX_DATA_DELAY: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 16
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN     => comb_rx_data,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT    => rx_data
-    );
-
-THE_RX_K_DELAY: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN     => comb_rx_k,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT    => rx_k
-    );
-
-THE_RX_RESET: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 1
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => reset_i,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT(0) => reset_i_rx
-    );
-
--- Delay for ALLOW signals
-THE_RX_ALLOW_SYNC: signal_sync
-	generic map(
-		DEPTH => 2,
-		WIDTH => 2
-		)
-	port map(
-		RESET    => reset_i,
-		D_IN(0)  => rx_allow,
-		D_IN(1)  => tx_allow,
-		CLK0     => clk_sys,
-		CLK1     => clk_sys,
-		D_OUT(0) => rx_allow_q,
-		D_OUT(1) => tx_allow_q
-	);
-
-THE_TX_SYNC: signal_sync
-	generic map(
-		DEPTH => 1,
-		WIDTH => 2
-		)
-	port map(
-		RESET    => '0',
-		D_IN(0)  => send_reset_in,
-		D_IN(1)  => tx_allow,
-		CLK0     => clk_tx,
-		CLK1     => clk_tx,
-		D_OUT(0) => send_reset_in_qtx,
-		D_OUT(1) => tx_allow_qtx
-	);
-
---THE_DLM_IN_DELAY: signal_sync
---	generic map(
---		DEPTH => 1,
---		WIDTH => 1
---		)
---	port map(
---		RESET    => '0',
---		D_IN(0)  => SYNC_DLM_IN,
---		CLK0     => sync_rx_full_clk,
---		CLK1     => sync_rx_full_clk,
---		D_OUT(0) => sync_dlm_in_S
---	);
---------------------------------------------------------------------------
--- Main control state machine, startup control for SFP
---------------------------------------------------------------------------
-
-THE_SFP_LSM: trb_net16_lsm_sfp
-    generic map (
-      HIGHSPEED_STARTUP => c_YES
-      )
-    port map(
-      SYSCLK            => clk_sys,
-      RESET             => reset_i,
-      CLEAR             => clear,
-      SFP_MISSING_IN    => sfp_prsnt_n,
-      SFP_LOS_IN        => sfp_los,
-      SD_LINK_OK_IN     => link_ok(0),
-      SD_LOS_IN         => link_error(8),
-      SD_TXCLK_BAD_IN   => link_error(5),
-      SD_RXCLK_BAD_IN   => link_error(4),
-      SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
-      SD_ALIGNMENT_IN	=> rx_k_q,
-      SD_CV_IN          => link_error(7 downto 6),
-      FULL_RESET_OUT    => quad_rst,
-      LANE_RESET_OUT    => lane_rst,
-      TX_ALLOW_OUT      => tx_allow,
-      RX_ALLOW_OUT      => rx_allow,
-      SWAP_BYTES_OUT    => swap_bytes,
-      STAT_OP           => buf_stat_op,
-      CTRL_OP           => ctrl_op,
-      STAT_DEBUG        => buf_stat_debug
-      );
-
-SYNC_TXDIS_OUT <= quad_rst or reset_i;
-
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
-ffc_quad_rst         <= quad_rst;
-ffc_lane_tx_rst      <= lane_rst;
-
-
-ffc_lane_rx_rst      <= lane_rst;
-
-
-
--- Instantiation of serdes module
-
-	THE_SERDES: sfp_2_200_int
-		port map(
-		HDINP_CH1           => CU_RXD_P_IN,
-		HDINN_CH1           => CU_RXD_N_IN,
-		HDOUTP_CH1          => CU_TXD_P_OUT,
-		HDOUTN_CH1          => CU_TXD_N_OUT,
-		SCI_SEL_CH1         => sci_ch_i(1),
-		RXICLK_CH1          => clk_rx,
-		TXICLK_CH1          => clk_tx,
-		RX_FULL_CLK_CH1     => ff_rxfullclk,
-		RX_HALF_CLK_CH1     => ff_rxhalfclk,
-		TX_FULL_CLK_CH1     => open,
-		TX_HALF_CLK_CH1     => ff_txhalfclk,
-		FPGA_RXREFCLK_CH1   => clk_rxref,
-		TXDATA_CH1          => tx_data,
-		TX_K_CH1            => tx_k,
-		TX_FORCE_DISP_CH1   => tx_correct,
-		TX_DISP_SEL_CH1     => "00",
-		RXDATA_CH1          => comb_rx_data,
-		RX_K_CH1            => comb_rx_k,
-		RX_DISP_ERR_CH1		=> open,
-		RX_CV_ERR_CH1			=> link_error(7 downto 6),
-		RX_SERDES_RST_CH1_C	=> trb_rx_serdes_rst,
-		SB_FELB_CH1_C			=> '0', --loopback enable
-		SB_FELB_RST_CH1_C		=> '0', --loopback reset
-		TX_PCS_RST_CH1_C		=> trb_tx_pcs_rst,	--'1', --tx power up
-		TX_PWRUP_CH1_C			=> '1', --tx power up
-		RX_PCS_RST_CH1_C		=> trb_rx_pcs_rst,	--'1', --rx power up
-		RX_PWRUP_CH1_C			=> '1', --rx power up
-		RX_LOS_LOW_CH1_S    => trb_rx_los_low,	--link_error(8),
-		LSM_STATUS_CH1_S    => link_ok(0),
-		RX_CDR_LOL_CH1_S    => trb_rx_cdr_lol,	--link_error(4),
-		TX_DIV2_MODE_CH1_C  => '0', --full rate
-		RX_DIV2_MODE_CH1_C  => '0', --full rate
-		
-		HDINP_CH3           => SYNC_RXD_P_IN,
-		HDINN_CH3           => SYNC_RXD_N_IN,
-		HDOUTP_CH3          => SYNC_TXD_P_OUT,
-		HDOUTN_CH3          => SYNC_TXD_N_OUT,
-		SCI_SEL_CH3         => sci_ch_i(3),
-		TXICLK_CH3          => sync_rx_full_clk,
-		RX_FULL_CLK_CH3     => sync_rx_full_clk,
-		RX_HALF_CLK_CH3     => sync_rx_half_clk,
-		TX_FULL_CLK_CH3     => sync_tx_full_clk,
-		TX_HALF_CLK_CH3     => sync_tx_half_clk,
-		FPGA_RXREFCLK_CH3   => clk_200_osc,
-		TXDATA_CH3          => sync_tx_data,
-		TX_K_CH3            => sync_tx_k,
-		TX_FORCE_DISP_CH3   => '0',
-		TX_DISP_SEL_CH3     => '0',
-		RXDATA_CH3          => sync_rx_data,
-		RX_K_CH3            => sync_rx_k,
-		RX_DISP_ERR_CH3     => open,
-		RX_CV_ERR_CH3       => sync_rx_error,
-		RX_SERDES_RST_CH3_C => sync_rx_serdes_rst,
-		SB_FELB_CH3_C       => '0', --loopback enable
-		SB_FELB_RST_CH3_C   => '0', --loopback reset
-		TX_PCS_RST_CH3_C     => sync_tx_pcs_rst,
-		TX_PWRUP_CH3_C       => '1',
-		RX_PCS_RST_CH3_C     => sync_rx_pcs_rst,
-		RX_PWRUP_CH3_C       => '1',
-		RX_LOS_LOW_CH3_S     => sync_rx_los_low,
-		LSM_STATUS_CH3_S     => sync_lsm_status,
-		RX_CDR_LOL_CH3_S     => sync_rx_cdr_lol,
-		TX_DIV2_MODE_CH3_C   => '0',
-		RX_DIV2_MODE_CH3_C   => '0',
-
-		SCI_WRDATA          => sci_data_in_i,
-		SCI_ADDR            => sci_addr_i(5 downto 0),
-		SCI_RDDATA          => sci_data_out_i,
-		SCI_SEL_QUAD        => sci_addr_i(8),
-		SCI_RD              => sci_read_i,
-		SCI_WRN             => sci_write_i,
-		FPGA_TXREFCLK       => clk_txref,
---		FPGA_TXREFCLK       => rx_full_clk,
-		TX_SERDES_RST_C     => CLEAR,
-		TX_PLL_LOL_QD_S     => link_error(5), 
-		TX_SYNC_QD_C			=> '0',
-		RST_QD_C					=> rst_qd,
-		REFCLK2FPGA				=> open,
-		SERDES_RST_QD_C     => ffc_quad_rst
-	);
-  
--------------------------------------------------------------------------
--- RX Fifo & Data output
--------------------------------------------------------------------------
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
-generic map(
-  USE_STATUS_FLAGS => c_NO
-       )
-port map( read_clock_in  => clk_sys,
-      write_clock_in     => clk_rx, -- CHANGED
-      read_enable_in     => fifo_rx_rd_en,
-      write_enable_in    => fifo_rx_wr_en,
-      fifo_gsr_in        => fifo_rx_reset,
-      write_data_in      => fifo_rx_din,
-      read_data_out      => fifo_rx_dout,
-      full_out           => fifo_rx_full,
-      empty_out          => fifo_rx_empty
-    );
-
-fifo_rx_reset <= reset_i or not rx_allow_q;
-fifo_rx_rd_en <= not fifo_rx_empty;
-
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
-THE_BYTE_SWAP_PROC: process
-  begin
-    wait until rising_edge(clk_rx);  --CHANGED
-    last_rx <= rx_k(1) & rx_data(15 downto 8);
-    if( swap_bytes = '0' ) then
-      fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
-      fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
-    else
-      fifo_rx_din   <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
-      fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
-    end if;
-  end process THE_BYTE_SWAP_PROC;
-
-buf_med_data_out          <= fifo_rx_dout(15 downto 0);
-buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
-buf_med_packet_num_out    <= rx_counter;
-med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
-
-
-THE_CNT_RESET_PROC : process
-  begin
-    wait until rising_edge(clk_rx);  --CHANGED
-    if reset_i_rx = '1' then
-      send_reset_words  <= '0';
-      make_trbnet_reset <= '0';
-      reset_word_cnt    <= (others => '0');
-    else
-      send_reset_words   <= '0';
-      make_trbnet_reset  <= '0';
-      if fifo_rx_din = "11" & x"FEFE" then
-        if reset_word_cnt(4) = '0' then
-          reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
-        else
-          send_reset_words <= '1';
-        end if;
-      else
-        reset_word_cnt    <= (others => '0');
-        make_trbnet_reset <= reset_word_cnt(4);
-      end if;
-    end if;
-  end process;
-
-
-THE_SYNC_PROC: process
-  begin
-    wait until rising_edge(clk_sys);
-    med_dataready_out     <= buf_med_dataready_out;
-    med_data_out          <= buf_med_data_out;
-    med_packet_num_out    <= buf_med_packet_num_out;
-    if reset_i = '1' then
-      med_dataready_out <= '0';
-    end if;
-  end process;
-
-
---rx packet counter
----------------------
-THE_RX_PACKETS_PROC: process( clk_sys )
-  begin
-    if( rising_edge(clk_sys) ) then
-      last_fifo_rx_empty <= fifo_rx_empty;
-      if reset_i = '1' or rx_allow_q = '0' then
-        rx_counter <= c_H0;
-      else
-        if( buf_med_dataready_out = '1' ) then
-          if( rx_counter = c_max_word_number ) then
-            rx_counter <= (others => '0');
-          else
-            rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
-          end if;
-        end if;
-      end if;
-    end if;
-  end process;
-
---TX Fifo & Data output to Serdes
----------------------
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
-  generic map(
-    USE_STATUS_FLAGS => c_NO
-        )
-  port map( read_clock_in => clk_tx,
-        write_clock_in    => clk_sys,
-        read_enable_in    => fifo_tx_rd_en,
-        write_enable_in   => fifo_tx_wr_en,
-        fifo_gsr_in       => fifo_tx_reset,
-        write_data_in     => fifo_tx_din,
-        read_data_out     => fifo_tx_dout,
-        full_out          => fifo_tx_full,
-        empty_out         => fifo_tx_empty,
-        almost_full_out   => fifo_tx_almost_full
-      );
-
-fifo_tx_reset <= reset_i or not tx_allow_q;
-fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
-fifo_tx_rd_en <= tx_allow_qtx;
-
-
-THE_SERDES_INPUT_PROC: process( clk_tx )
-  begin
-    if( rising_edge(clk_tx) ) then
-      last_fifo_tx_empty <= fifo_tx_empty;
-      first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
-      if send_reset_in = '1' then
-        tx_data <= x"FEFE";
-        tx_k <= "11";
-      elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
-        tx_data <= x"50bc";
-        tx_k <= "01";
-        tx_correct <= first_idle & '0';
-      else
-        tx_data <= fifo_tx_dout(15 downto 0);
-        tx_k <= "00";
-        tx_correct <= "00";
-      end if;
-    end if;
-  end process THE_SERDES_INPUT_PROC;
-
-  
--- map 8-bit dlm on 18-bit fifo
-syncfifo_din(7 downto 0)	<= SYNC_DLM_WORD_IN;
-syncfifo_din(17 downto 8)	<= (others => '0');
---SYNC_DLM_word_S				<= syncfifo_dout(7 downto 0);
-
-SYNC_DLM_tx: trb_net_fifo_16bit_bram_dualport
-	generic map(
-		USE_STATUS_FLAGS => c_NO
-		)
-	port map(
-		read_clock_in		=> sync_tx_full_clk,
-		write_clock_in		=> sync_rx_full_clk, 
-		read_enable_in		=> dlm_fifo_rd_en,
-		write_enable_in	=> SYNC_DLM_IN,	--sync_dlm_in_S,
-		fifo_gsr_in			=> reset,
-		write_data_in		=> syncfifo_din,
-		read_data_out		=> syncfifo_dout,
-		full_out				=> open,
-		empty_out			=> dlm_fifo_empty
-	);
-
-sync_rx_proc : process(sync_rx_full_clk)
-begin
-	if rising_edge(sync_rx_full_clk) then
-		SYNC_DLM_OUT <= '0';
-		if dlm_received_S='1' then
-			dlm_received_S		<= '0';
-			SYNC_DLM_OUT		<= '1';
-			SYNC_DLM_WORD_OUT	<= sync_rx_data;
-		elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then
-			dlm_received_S		<= '1';
-		end if;
-	end if;
-end process;  
-
-sync_tx_fsm : process(sync_tx_full_clk)
-begin
-	if rising_edge(sync_tx_full_clk) then
-		case sync_tx_proc_state is
-			when cSEND_IDLE	=>
-				if (dlm_fifo_empty='1') then
-					sync_tx_proc_state	<= cSEND_IDLE;
-					dlm_fifo_rd_en			<= '0';
-					sync_tx_data			<= x"BC"; -- idle
-					sync_tx_k				<= '1';
-				else
-					sync_tx_proc_state	<= cFIFO_READ;
-					dlm_fifo_rd_en			<= '1';
-					sync_tx_data			<= x"BC"; -- dlm
-					sync_tx_k				<= '1';
-				end if;
-			when cFIFO_READ	=>
-				sync_tx_proc_state		<= cSEND_DLM;
-				dlm_fifo_rd_en				<= '0';
-				sync_tx_data				<= x"DC"; -- dlm
-				sync_tx_k					<= '1';
-			when cSEND_DLM	=>
-				sync_tx_proc_state	<= cSEND_IDLE;
-				dlm_fifo_rd_en			<= '0';
-				sync_tx_data			<= syncfifo_dout(7 downto 0);
-				sync_tx_k				<= '0';
-		when others	=>
-				sync_tx_proc_state	<= cSEND_IDLE;
-				dlm_fifo_rd_en			<= '0';
-				sync_tx_data			<= x"BC"; -- idle
-				sync_tx_k				<= '1';
-		end case;
-	end if;
-end process;
-		
-		
---sync_tx_proc : process(sync_tx_full_clk)
---begin
-	--if rising_edge(sync_tx_full_clk) then
-		--if dlm_fifo_rd_en='1' then
-			--dlm_fifo_rd_en		<= '0';
-			--sync_tx_data		<= syncfifo_dout(7 downto 0);
-			--sync_tx_k			<= '0';
-		--elsif (dlm_fifo_empty='0') and (dlm_fifo_reading='1') then
-			--dlm_fifo_rd_en		<= '1';
-			--sync_tx_data		<= x"DC";
-			--sync_tx_k			<= '1';
-		--elsif dlm_fifo_empty='0' then
-			--dlm_fifo_reading	<= '1';
-			--dlm_fifo_rd_en		<= '0';
-			--sync_tx_data		<= x"BC"; -- idle
-			--sync_tx_k			<= '1';		
-		--else
-			--dlm_fifo_reading	<= '0';
-			--dlm_fifo_rd_en		<= '0';
-			--sync_tx_data		<= x"BC"; -- idle
-			--sync_tx_k			<= '1';
-		--end if;
-	--end if;
---end process;  
-
-link_error(8) <= trb_rx_los_low; -- loss of signal
-link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock 
-link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock
-
-reset_n <= '0' when (RESET='1') or (CLEAR='1')  else '1';
-
--------------------------------------------------      
--- Reset FSM & Link states
-------------------------------------------------- 
-THE_RX_FSM1: rx_reset_fsm
-	port map(
-		RST_N               => reset_n,
-		RX_REFCLK           => OSCCLK,
-		TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
-		RX_SERDES_RST_CH_C  => trb_rx_serdes_rst,
-		RX_CDR_LOL_CH_S     => trb_rx_cdr_lol,
-		RX_LOS_LOW_CH_S     => trb_rx_los_low,
-		RX_PCS_RST_CH_C     => trb_rx_pcs_rst,
-		WA_POSITION         => "0000",
-		STATE_OUT           => trb_rx_fsm_state
-	);
-
-link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';
-
-THE_TX_FSM1: tx_reset_fsm
-	port map(
-		RST_N           => reset_n,
-		TX_REFCLK       => OSCCLK,
-		TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-		RST_QD_C        => rst_qd1,
-		TX_PCS_RST_CH_C => trb_tx_pcs_rst,
-		STATE_OUT       => trb_tx_fsm_state	--open
-	);
-
-THE_RX_FSM3: rx_reset_fsm
-	port map(
-		RST_N               => reset_n,
-		RX_REFCLK           => sync_rx_full_clk,
-		TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
-		RX_SERDES_RST_CH_C  => sync_rx_serdes_rst,
-		RX_CDR_LOL_CH_S     => sync_rx_cdr_lol,
-		RX_LOS_LOW_CH_S     => sync_rx_los_low,
-		RX_PCS_RST_CH_C     => sync_rx_pcs_rst,
-		WA_POSITION         => sync_wa_position_rx(11 downto 8),
-		STATE_OUT           => sync_rx_fsm_state
-	);
-
-SYNC_WA_POSITION : process(sync_rx_full_clk) --??CLK)
-begin
-	if rising_edge(sync_rx_full_clk) then
-		sync_wa_position_rx <= wa_position;
-	end if;
-end process;
-
-THE_TX_FSM3 : tx_reset_fsm
-  port map(
-    RST_N           => reset_n,
-    TX_REFCLK       => OSCCLK,
-    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-    RST_QD_C        => rst_qd3,
-    TX_PCS_RST_CH_C => sync_tx_pcs_rst,
-    STATE_OUT       => sync_tx_fsm_state
-    );
-
---rst_qd			<= '1' when (rst_qd1='1') or (rst_qd3='1') else '0';
-rst_qd			<= RESET;
-
-TX_READY_CH3	<= '1' when (sync_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';  
-
------------------------------------------------------------------------------------------------------
--- SCI --gives access to serdes config port from slow control and reads word alignment every ~ 40 us
------------------------------------------------------------------------------------------------------
-PROC_SCI_CTRL: process(clk_sys)
-	variable cnt : integer range 0 to 4 := 0;
-begin
-	if( rising_edge(clk_sys) ) then
-		SCI_ACK <= '0';
-		case sci_state is
-			when IDLE =>
-				sci_ch_i        <= x"0";
-				sci_qd_i        <= '0';
-				sci_reg_i       <= '0';
-				sci_read_i      <= '0';
-				sci_write_i     <= '0';
-				sci_timer       <= sci_timer + 1;
-				if SCI_READ = '1' or SCI_WRITE = '1' then
-				sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-				sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-				sci_addr_i    <= SCI_ADDR;
-				sci_data_in_i <= SCI_DATA_IN;
-				sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-				sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-				sci_state     <= SCTRL;
-			elsif sci_timer(sci_timer'left) = '1' then
-				sci_timer     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;      
-		when SCTRL =>
-			if sci_reg_i = '1' then
-				--//			SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-				SCI_DATA_OUT  <= (others => '0');
-				SCI_ACK       <= '1';
-				sci_write_i   <= '0';
-				sci_read_i    <= '0';
-				sci_state     <= IDLE;
-			else
-				sci_state     <= SCTRL_WAIT;
-			end if;
-		when SCTRL_WAIT   =>
-			sci_state       <= SCTRL_WAIT2;
-		when SCTRL_WAIT2  =>
-			sci_state       <= SCTRL_FINISH;
-		when SCTRL_FINISH =>
-			SCI_DATA_OUT    <= sci_data_out_i;
-			SCI_ACK         <= '1';
-			sci_write_i     <= '0';
-			sci_read_i      <= '0';
-			sci_state       <= IDLE;
-
-		when GET_WA =>
-			if cnt = 4 then
-				cnt           := 0;
-				sci_state     <= IDLE;
-			else
-				sci_state     <= GET_WA_WAIT;
-				sci_addr_i    <= '0' & x"22";
-				sci_ch_i      <= x"0";
-				sci_ch_i(cnt) <= '1';
-				sci_read_i    <= '1';
-				end if;
-		when GET_WA_WAIT  =>
-			sci_state       <= GET_WA_WAIT2;
-		when GET_WA_WAIT2 =>
-			sci_state       <= GET_WA_FINISH;
-		when GET_WA_FINISH =>
-			wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-			sci_state       <= GET_WA;    
-			cnt             := cnt + 1;
-		end case;
-
-		if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-			SCI_NACK <= '1';
-		else
-			SCI_NACK <= '0';
-		end if;
-	end if;
-end process PROC_SCI_CTRL;
-
-----------------------
---Generate LED signals
-----------------------
-LED_PROC : process( clk_sys )
-	begin
-		if rising_edge(clk_sys) then
-			led_counter <= led_counter + to_unsigned(1,1);
-			if buf_med_dataready_out = '1' then
-				rx_led <= '1';
-			elsif led_counter = 0 then
-			rx_led <= '0';
-			end if;
-			if tx_k(0) = '0' then
-				tx_led <= '1';
-			elsif led_counter = 0 then
-				tx_led <= '0';
-			end if;
-		end if;
-	end process LED_PROC;
-
-
-stat_op(15)           <= send_reset_words_q;
-stat_op(14)           <= buf_stat_op(14);
-stat_op(13)           <= make_trbnet_reset_q;
-stat_op(12)           <= '0';
-stat_op(11)           <= tx_led; --tx led
-stat_op(10)           <= rx_led; --rx led
-stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
-
--- Debug output
-stat_debug(15 downto 0)  <= rx_data;
-stat_debug(17 downto 16) <= rx_k;
-stat_debug(19 downto 18) <= (others => '0');
-stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
-stat_debug(24)           <= fifo_rx_rd_en;
-stat_debug(25)           <= fifo_rx_wr_en;
-stat_debug(26)           <= fifo_rx_reset;
-stat_debug(27)           <= fifo_rx_empty;
-stat_debug(28)           <= fifo_rx_full;
-stat_debug(29)           <= last_rx(8);
-stat_debug(30)           <= rx_allow_q;
-stat_debug(41 downto 31) <= (others => '0');
-stat_debug(42)           <= clk_sys;
-stat_debug(43)           <= clk_sys;
-stat_debug(59 downto 44) <= (others => '0');
-stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
-
-
-end Cu_trb_net16_soda_sync_ecp3_sfp_arch;
\ No newline at end of file
diff --git a/code/TB_soda_chain.vhd b/code/TB_soda_chain.vhd
deleted file mode 100644
index 50b2445..0000000
--- a/code/TB_soda_chain.vhd
+++ /dev/null
@@ -1,217 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
---	use work.trb_net_std.all;
---	use work.trb_net_components.all;
---	use work.trb_net16_hub_func.all;
---	use work.trb3_components.all; 
---	use work.med_sync_define.all;
---	use work.version.all;
-use work.soda_components.all;
-
-
-entity TB_soda_chain is
-end entity;
-
-architecture TestBench of TB_soda_chain is
-
- -- Clock period definitions
- constant sysclk_period: time:= 10ns;
- constant sodaclk_period: time:= 5ns;
-
-
---Inputs
-	signal rst_S							: std_logic;
-	signal sys_clk_S						: std_logic;
-	signal soda_clk_S						: std_logic;
-	signal enable_S						: std_logic := '0';
-	signal SOB_S							: std_logic := '0';
-	signal src_dnstream_dlm_word_S	: std_logic_vector(7 downto 0)	:= (others => '0');
-	signal src_dnstream_dlm_valid_S	: std_logic;
-	signal src_upstream_dlm_word_S	: std_logic_vector(7 downto 0)	:= (others => '0');
-	signal src_upstream_dlm_valid_S	: std_logic;
-
-	signal hub_dnstream_dlm_word_S	: t_HUB_WORD;
-	signal hub_dnstream_dlm_valid_S	: t_HUB_BIT;
-	signal hub_upstream_dlm_word_S	: t_HUB_WORD;
-	signal hub_upstream_dlm_valid_S	: t_HUB_BIT;
-
-	--SODA
-	signal soda_ack						: std_logic;
-	signal soda_write						: std_logic	:= '0';
-	signal soda_read						: std_logic	:= '0';
-	signal soda_data_in					: std_logic_vector(31 downto 0)	:= (others => '0');
-	signal soda_src_data_out			: std_logic_vector(31 downto 0);
-	signal soda_hub_data_out			: std_logic_vector(31 downto 0);
-	signal soda_clt_data_out			: std_logic_vector(31 downto 0);
-	signal soda_addr						: std_logic_vector(3 downto 0)	:= (others => '0');
-	signal soda_leds						: std_logic_vector(3 downto 0);
-begin
-
-	THE_SOB_SOURCE : soda_start_of_burst_faker
-		port map(
-			SYSCLK						=> sys_clk_S,
-			RESET							=> rst_S,
-			SODA_BURST_PULSE_OUT		=> SOB_S
-		);
-
-
-	THE_SODA_SOURCE : soda_source
-		port map(
-			SYSCLK					=> sys_clk_S,
-			SODACLK					=> soda_clk_S,
-			RESET						=> rst_S,
-			CLEAR						=> '0',
-			CLK_EN					=> '1',
-			--Internal Connection
-			SODA_BURST_PULSE_IN	=> SOB_S,
-			RX_DLM_WORD_IN			=> src_upstream_dlm_word_S,
-			RX_DLM_IN				=> src_upstream_dlm_valid_S,
-			TX_DLM_OUT				=> src_dnstream_dlm_valid_S, 
-			TX_DLM_WORD_OUT		=> src_dnstream_dlm_word_S,
-
-			SODA_DATA_IN			=> soda_data_in,
-			SODA_DATA_OUT			=> soda_src_data_out,
-			SODA_ADDR_IN			=> soda_addr,
-			SODA_READ_IN			=> soda_read,
-			SODA_WRITE_IN			=> soda_write,
-			SODA_ACK_OUT			=> soda_ack,
-			LEDS_OUT					=>	soda_leds
-		);
-
-	A_SODA_HUB : soda_hub
-		port map(
-			SYSCLK					=> sys_clk_S,
-			SODACLK					=> soda_clk_S,
-			RESET						=> rst_S,
-			CLEAR						=> '0',
-			CLK_EN					=> '1',
-			--Internal Connection
-			RXTOP_DLM_WORD_IN		=> src_dnstream_dlm_word_S,
-			RXTOP_DLM_IN			=> src_dnstream_dlm_valid_S,
-			TXTOP_DLM_OUT			=> src_upstream_dlm_valid_S,
-			TXTOP_DLM_WORD_OUT	=> src_upstream_dlm_word_S,
-
-			RXBTM_DLM_WORD_IN		=> hub_upstream_dlm_word_S,
-			RXBTM_DLM_IN			=> hub_upstream_dlm_valid_S,
-			TXBTM_DLM_OUT			=> hub_dnstream_dlm_valid_S,
-			TXBTM_DLM_WORD_OUT	=> hub_dnstream_dlm_word_S,
-
-			SODA_DATA_IN			=> soda_data_in,
-			SODA_DATA_OUT			=> soda_hub_data_out,
-			SODA_ADDR_IN			=> soda_addr,
-			SODA_READ_IN			=> soda_read,
-			SODA_WRITE_IN			=> soda_write,
-			SODA_ACK_OUT			=> soda_ack,
-			STAT						=>	open
-		);
-
-	channel :  for i in c_HUB_CHILDREN-1 downto 0 generate
-
-		A_SODA_CLIENT : soda_client
-			port map(
-				SYSCLK					=> sys_clk_S,
-				SODACLK					=> soda_clk_S,
-				RESET						=> rst_S,
-				CLEAR						=> '0',
-				CLK_EN					=> '1',
-				--Internal Connection
-				RX_DLM_WORD_IN			=> hub_dnstream_dlm_word_S(i),
-				RX_DLM_IN				=> hub_dnstream_dlm_valid_S(i),
-				TX_DLM_OUT				=> hub_upstream_dlm_valid_S(i),
-				TX_DLM_WORD_OUT		=> hub_upstream_dlm_word_S(i),
-
-				SODA_DATA_IN			=> soda_data_in,
-				SODA_DATA_OUT			=> soda_clt_data_out,
-				SODA_ADDR_IN			=> soda_addr,
-				SODA_READ_IN			=> soda_read,
-				SODA_WRITE_IN			=> soda_write,
-				SODA_ACK_OUT			=> soda_ack,
-				LEDS_OUT					=>	open,
-				LINK_DEBUG_IN			=>	(others => '0')
-			);
-
-	end generate;
-
-
-------------------------------------------------------------------------------------------------------------
- -- SODA command packet
-------------------------------------------------------------------------------------------------------------
-	cmd_proc	:process
-	begin
-		wait for 2us;
-				soda_addr			<=	"0000";
-				soda_data_in		<= x"08000000";		-- soda_reset
-				soda_write			<= '1';
-		wait for sysclk_period;
-				soda_write			<= '0';
-		wait for sysclk_period;
-				soda_addr			<=	"0000";
-				soda_data_in		<= x"00000000";		-- soda_reset
-				soda_write			<= '1';
-		wait for sysclk_period;
-				soda_write			<= '0';
-------------------------------------------------------------------------------------------------------------
-		wait for 2us;
-				soda_addr			<=	"0100";
-				soda_data_in		<= x"FFFFFFFD";		-- 
-				soda_write			<= '1';
-		wait for sysclk_period;
-				soda_write			<= '0';
-------------------------------------------------------------------------------------------------------------
-		wait for 700us;
-				soda_addr			<=	"0000";
-				soda_data_in		<= x"40000000";		-- time_calibration
-				soda_write			<= '1';
-		wait for sysclk_period;
-				soda_write			<= '0';
-------------------------------------------------------------------------------------------------------------
-		wait for 700us;
-				soda_addr			<=	"0100";
-				soda_data_in		<= x"FFFFFFFE";		-- time_calibration
-				soda_write			<= '1';
-		wait for sysclk_period;
-				soda_write			<= '0';
-------------------------------------------------------------------------------------------------------------
-		wait for 100us;
-				soda_addr			<=	"1001";
-				soda_read			<= '1';
-		wait for sysclk_period;
-				soda_read			<= '0';
-	end process;
-
-------------------------------------------------------------------------------------------------------------
- -- Clock process definitions
-------------------------------------------------------------------------------------------------------------
-	sysclk_proc :process
-		begin
-			sys_clk_S <= '0';
-		wait for sysclk_period/2;
-			sys_clk_S <= '1';
-		wait for sysclk_period/2;
-	end process; 
-
-	sodaclk_proc :process
-		begin
-			soda_clk_S <= '0';
-		wait for sodaclk_period/2;
-			soda_clk_S <= '1';
-		wait for sodaclk_period/2;
-	end process; 
-
-
-------------------------------------------------------------------------------------------------------------
--- reset process
-------------------------------------------------------------------------------------------------------------
-	reset_proc: process
-		begin
-			rst_S <= '1';
-		wait for sysclk_period * 5; 
-			rst_S <= '0';
-		wait;
-	end process;
-
-end TestBench;
-
diff --git a/code/TB_soda_source.vhd b/code/TB_soda_source.vhd
deleted file mode 100644
index 6b7c6dd..0000000
--- a/code/TB_soda_source.vhd
+++ /dev/null
@@ -1,139 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
---	use work.trb_net_std.all;
---	use work.trb_net_components.all;
---	use work.trb_net16_hub_func.all;
---	use work.trb3_components.all; 
---	use work.med_sync_define.all;
---	use work.version.all;
-use work.soda_components.all;
-
-
-entity TB_soda_source_child is
-end entity;
-
-architecture TestBench of TB_soda_source_child is
-
- -- Clock period definitions
- constant clk_period: time:= 4ns;
-
-
---Inputs
-	signal rst_S							: std_logic;
-	signal clk_S							: std_logic;
-	signal enable_S						: std_logic := '0';
-	signal SOB_S							: std_logic := '0';
-	signal src_dnstream_dlm_word_S	: std_logic_vector(7 downto 0)	:= (others => '0');
-	signal src_dnstream_dlm_valid_S	: std_logic;
-	signal src_upstream_dlm_word_S	: std_logic_vector(7 downto 0)	:= (others => '0');
-	signal src_upstream_dlm_valid_S	: std_logic;
-
-	--SODA
-	signal soda_ack						: std_logic;
-	signal soda_write						: std_logic	:= '0';
-	signal soda_read						: std_logic	:= '0';
-	signal soda_data_in					: std_logic_vector(31 downto 0)	:= (others => '0');
-	signal soda_data_out					: std_logic_vector(31 downto 0);
-	signal soda_addr						: std_logic_vector(3 downto 0)	:= (others => '0');
-	signal soda_leds						: std_logic_vector(3 downto 0);
-begin
-
-	THE_SODA_SOURCE : soda_source
-		port map(
-			SYSCLK					=> clk_S,
-			RESET						=> rst_S,
-			CLEAR						=> '0',
-			CLK_EN					=> '1',
-			--Internal Connection
-			SODA_BURST_PULSE_IN	=> SOB_S,
-			RX_DLM_WORD_IN			=> src_upstream_dlm_word_S,
-			RX_DLM_IN				=> src_upstream_dlm_valid_S,
-			TX_DLM_OUT				=> src_dnstream_dlm_valid_S, 
-			TX_DLM_WORD_OUT		=> src_dnstream_dlm_word_S,
-
-			SODA_DATA_IN			=> soda_data_in,
-			SODA_DATA_OUT			=> soda_data_out,
-			SODA_ADDR_IN			=> soda_addr,
-			SODA_READ_IN			=> soda_read,
-			SODA_WRITE_IN			=> soda_write,
-			SODA_ACK_OUT			=> soda_ack,
-			LEDS_OUT					=>	soda_leds,
-			TEST_LINE				=>	open,
-			STAT						=>	open
-		);
-
-
-		A_SODA_CLIENT : soda_client
-			port map(
-				SYSCLK					=> clk_S,
-				RESET						=> rst_S,
-				CLEAR						=> '0',
-				CLK_EN					=> '1',
-				--Internal Connection
-				RX_DLM_WORD_IN			=> src_dnstream_dlm_word_S,
-				RX_DLM_IN				=> src_dnstream_dlm_valid_S,
-				TX_DLM_OUT				=> src_upstream_dlm_valid_S,
-				TX_DLM_WORD_OUT		=> src_upstream_dlm_word_S,
-
-				SODA_DATA_IN			=> soda_data_in,
-				SODA_DATA_OUT			=> soda_data_out,
-				SODA_ADDR_IN			=> soda_addr,
-				SODA_READ_IN			=> soda_read,
-				SODA_WRITE_IN			=> soda_write,
-				SODA_ACK_OUT			=> soda_ack,
-				STAT						=>	open
-			);
-
-------------------------------------------------------------------------------------------------------------
- -- SODA command packet
-------------------------------------------------------------------------------------------------------------
-	cmd_proc	:process
-	begin
-wait for 2us;
-		soda_addr			<=	"0000";
-		soda_data_in		<= x"08000000";		-- soda_reset
-		soda_write			<= '1';
-wait for clk_period;
-		soda_write			<= '0';
-wait for 700us;
-		soda_data_in		<= x"40000000";		-- time_calibration
-		soda_write			<= '1';
-wait for clk_period;
-		soda_write			<= '0';
-
-	end process;
-
-------------------------------------------------------------------------------------------------------------
- -- Clock process definitions
-------------------------------------------------------------------------------------------------------------
-clk_proc :process
-	begin
-		clk_S <= '0';
-		wait for clk_period/2;
-		clk_S <= '1';
-		wait for clk_period/2;
-	end process; 
-
--- reset process
-reset_proc: process
-	begin
-		rst_S <= '1';
-		wait for clk_period * 5; 
-		rst_S <= '0';
-		wait;
-	end process;
-
-burst_proc :process
-	begin
-		SOB_S <= '0';
-		wait for 2.35us;
-		SOB_S <= '1';
-		wait for 50ns;
-	end process; 
-
-
-end TestBench;
-
diff --git a/code/ip/serdes_4_sync_downstream.ipx b/code/ip/serdes_4_sync_downstream.ipx
deleted file mode 100644
index 4665264..0000000
--- a/code/ip/serdes_4_sync_downstream.ipx
+++ /dev/null
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_4_sync_downstream" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 19 11:41:24.218" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-		<File name="serdes_4_sync_downstream.lpc" type="lpc" modified="2015 02 19 11:41:22.000"/>
-		<File name="serdes_4_sync_downstream.pp" type="pp" modified="2015 02 19 11:41:22.000"/>
-		<File name="serdes_4_sync_downstream.sym" type="sym" modified="2015 02 19 11:41:22.000"/>
-		<File name="serdes_4_sync_downstream.tft" type="tft" modified="2015 02 19 11:41:22.000"/>
-		<File name="serdes_4_sync_downstream.txt" type="pcs_module" modified="2015 02 19 11:41:22.000"/>
-		<File name="serdes_4_sync_downstream.vhd" type="top_level_vhdl" modified="2015 02 19 11:41:22.000"/>
-  </Package>
-</DiamondModule>
diff --git a/code/ip/serdes_4_sync_hub_downstream.ipx b/code/ip/serdes_4_sync_hub_downstream.ipx
deleted file mode 100644
index bd45581..0000000
--- a/code/ip/serdes_4_sync_hub_downstream.ipx
+++ /dev/null
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_4_sync_hub_downstream" module="serdes_4_sync_hub_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 08 13:39:53.561" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-		<File name="serdes_4_sync_hub_downstream.lpc" type="lpc" modified="2014 05 08 13:39:51.000"/>
-		<File name="serdes_4_sync_hub_downstream.pp" type="pp" modified="2014 05 08 13:39:51.000"/>
-		<File name="serdes_4_sync_hub_downstream.sym" type="sym" modified="2014 05 08 13:39:51.000"/>
-		<File name="serdes_4_sync_hub_downstream.tft" type="tft" modified="2014 05 08 13:39:51.000"/>
-		<File name="serdes_4_sync_hub_downstream.txt" type="pcs_module" modified="2014 05 08 13:39:51.000"/>
-		<File name="serdes_4_sync_hub_downstream.vhd" type="top_level_vhdl" modified="2014 05 08 13:39:51.000"/>
-  </Package>
-</DiamondModule>
diff --git a/code/ip/serdes_4_sync_hub_downstream.lpc b/code/ip/serdes_4_sync_hub_downstream.lpc
deleted file mode 100644
index 6e2c674..0000000
--- a/code/ip/serdes_4_sync_hub_downstream.lpc
+++ /dev/null
@@ -1,258 +0,0 @@
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_4_sync_hub_downstream
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=05/08/2014
-Time=13:39:51
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=RXTX
-_mode1=RXTX
-_mode2=RXTX
-_mode3=RXTX
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=G8B10B
-_tx_protocol1=G8B10B
-_tx_protocol2=G8B10B
-_tx_protocol3=G8B10B
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=DISABLED
-_tx_fifo1=DISABLED
-_tx_fifo2=DISABLED
-_tx_fifo3=DISABLED
-_tx_ficlk_rate0=200
-_tx_ficlk_rate1=200
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=INTERNAL
-_pll_rxsrc2=INTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2
-_rx_datarange2=2
-_rx_datarange3=2
-_rx_protocol0=G8B10B
-_rx_protocol1=G8B10B
-_rx_protocol2=G8B10B
-_rx_protocol3=G8B10B
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=200
-_rxrefclk_rate1=200
-_rxrefclk_rate2=200
-_rxrefclk_rate3=200
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=DISABLED
-_rx_fifo1=DISABLED
-_rx_fifo2=DISABLED
-_rx_fifo3=DISABLED
-_rx_ficlk_rate0=200
-_rx_ficlk_rate1=200
-_rx_ficlk_rate2=200
-_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=DC
-_rx_dcc2=DC
-_rx_dcc3=DC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=00
-_k01=00
-_k02=00
-_k03=00
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00011100
-_byten02=00011100
-_byten03=00011100
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_4_sync_hub_downstream.pp=pp
-serdes_4_sync_hub_downstream.tft=tft
-serdes_4_sync_hub_downstream.txt=pcs_module
-serdes_4_sync_hub_downstream.sym=sym
diff --git a/code/ip/serdes_4_sync_hub_downstream.vhd b/code/ip/serdes_4_sync_hub_downstream.vhd
deleted file mode 100644
index 256ffcc..0000000
--- a/code/ip/serdes_4_sync_hub_downstream.vhd
+++ /dev/null
@@ -1,2810 +0,0 @@
-
-                                                                                                         
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
---  CONFIG_FILE : String  := "serdes_4_sync_hub_downstream.txt";
---  QUAD_MODE : String := "SINGLE";
---  CH0_CDR_SRC   : String := "REFCLK_CORE";
---  CH1_CDR_SRC   : String := "REFCLK_CORE";
---  CH2_CDR_SRC   : String := "REFCLK_CORE";
---  CH3_CDR_SRC   : String := "REFCLK_CORE";
---  PLL_SRC   : String := "REFCLK_CORE"
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String;
-  CH1_CDR_SRC   : String;
-  CH2_CDR_SRC   : String;
-  CH3_CDR_SRC   : String;
-  PLL_SRC   : String
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
-  CONFIG_FILE => CONFIG_FILE,
-  QUAD_MODE => QUAD_MODE,
-  CH0_CDR_SRC => CH0_CDR_SRC,
-  CH1_CDR_SRC => CH1_CDR_SRC,
-  CH2_CDR_SRC => CH2_CDR_SRC,
-  CH3_CDR_SRC => CH3_CDR_SRC,
-  PLL_SRC => PLL_SRC
-  )
-port map (
-   HDINN0 => HDINN0,
-   HDINN1 => HDINN1,
-   HDINN2 => HDINN2,
-   HDINN3 => HDINN3,
-   HDINP0 => HDINP0,
-   HDINP1 => HDINP1,
-   HDINP2 => HDINP2,
-   HDINP3 => HDINP3,
-   REFCLKN => REFCLKN,
-   REFCLKP => REFCLKP,
-   CIN11 => CIN11,
-   CIN10 => CIN10,
-   CIN9 => CIN9,
-   CIN8 => CIN8,
-   CIN7 => CIN7,
-   CIN6 => CIN6,
-   CIN5 => CIN5,
-   CIN4 => CIN4,
-   CIN3 => CIN3,
-   CIN2 => CIN2,
-   CIN1 => CIN1,
-   CIN0 => CIN0,
-   CYAWSTN => CYAWSTN,
-   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
-   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
-   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
-   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
-   FF_RXI_CLK_3 => FF_RXI_CLK_3,
-   FF_RXI_CLK_2 => FF_RXI_CLK_2,
-   FF_RXI_CLK_1 => FF_RXI_CLK_1,
-   FF_RXI_CLK_0 => FF_RXI_CLK_0,
-   FF_TX_D_0_0 => FF_TX_D_0_0,
-   FF_TX_D_0_1 => FF_TX_D_0_1,
-   FF_TX_D_0_2 => FF_TX_D_0_2,
-   FF_TX_D_0_3 => FF_TX_D_0_3,
-   FF_TX_D_0_4 => FF_TX_D_0_4,
-   FF_TX_D_0_5 => FF_TX_D_0_5,
-   FF_TX_D_0_6 => FF_TX_D_0_6,
-   FF_TX_D_0_7 => FF_TX_D_0_7,
-   FF_TX_D_0_8 => FF_TX_D_0_8,
-   FF_TX_D_0_9 => FF_TX_D_0_9,
-   FF_TX_D_0_10 => FF_TX_D_0_10,
-   FF_TX_D_0_11 => FF_TX_D_0_11,
-   FF_TX_D_0_12 => FF_TX_D_0_12,
-   FF_TX_D_0_13 => FF_TX_D_0_13,
-   FF_TX_D_0_14 => FF_TX_D_0_14,
-   FF_TX_D_0_15 => FF_TX_D_0_15,
-   FF_TX_D_0_16 => FF_TX_D_0_16,
-   FF_TX_D_0_17 => FF_TX_D_0_17,
-   FF_TX_D_0_18 => FF_TX_D_0_18,
-   FF_TX_D_0_19 => FF_TX_D_0_19,
-   FF_TX_D_0_20 => FF_TX_D_0_20,
-   FF_TX_D_0_21 => FF_TX_D_0_21,
-   FF_TX_D_0_22 => FF_TX_D_0_22,
-   FF_TX_D_0_23 => FF_TX_D_0_23,
-   FF_TX_D_1_0 => FF_TX_D_1_0,
-   FF_TX_D_1_1 => FF_TX_D_1_1,
-   FF_TX_D_1_2 => FF_TX_D_1_2,
-   FF_TX_D_1_3 => FF_TX_D_1_3,
-   FF_TX_D_1_4 => FF_TX_D_1_4,
-   FF_TX_D_1_5 => FF_TX_D_1_5,
-   FF_TX_D_1_6 => FF_TX_D_1_6,
-   FF_TX_D_1_7 => FF_TX_D_1_7,
-   FF_TX_D_1_8 => FF_TX_D_1_8,
-   FF_TX_D_1_9 => FF_TX_D_1_9,
-   FF_TX_D_1_10 => FF_TX_D_1_10,
-   FF_TX_D_1_11 => FF_TX_D_1_11,
-   FF_TX_D_1_12 => FF_TX_D_1_12,
-   FF_TX_D_1_13 => FF_TX_D_1_13,
-   FF_TX_D_1_14 => FF_TX_D_1_14,
-   FF_TX_D_1_15 => FF_TX_D_1_15,
-   FF_TX_D_1_16 => FF_TX_D_1_16,
-   FF_TX_D_1_17 => FF_TX_D_1_17,
-   FF_TX_D_1_18 => FF_TX_D_1_18,
-   FF_TX_D_1_19 => FF_TX_D_1_19,
-   FF_TX_D_1_20 => FF_TX_D_1_20,
-   FF_TX_D_1_21 => FF_TX_D_1_21,
-   FF_TX_D_1_22 => FF_TX_D_1_22,
-   FF_TX_D_1_23 => FF_TX_D_1_23,
-   FF_TX_D_2_0 => FF_TX_D_2_0,
-   FF_TX_D_2_1 => FF_TX_D_2_1,
-   FF_TX_D_2_2 => FF_TX_D_2_2,
-   FF_TX_D_2_3 => FF_TX_D_2_3,
-   FF_TX_D_2_4 => FF_TX_D_2_4,
-   FF_TX_D_2_5 => FF_TX_D_2_5,
-   FF_TX_D_2_6 => FF_TX_D_2_6,
-   FF_TX_D_2_7 => FF_TX_D_2_7,
-   FF_TX_D_2_8 => FF_TX_D_2_8,
-   FF_TX_D_2_9 => FF_TX_D_2_9,
-   FF_TX_D_2_10 => FF_TX_D_2_10,
-   FF_TX_D_2_11 => FF_TX_D_2_11,
-   FF_TX_D_2_12 => FF_TX_D_2_12,
-   FF_TX_D_2_13 => FF_TX_D_2_13,
-   FF_TX_D_2_14 => FF_TX_D_2_14,
-   FF_TX_D_2_15 => FF_TX_D_2_15,
-   FF_TX_D_2_16 => FF_TX_D_2_16,
-   FF_TX_D_2_17 => FF_TX_D_2_17,
-   FF_TX_D_2_18 => FF_TX_D_2_18,
-   FF_TX_D_2_19 => FF_TX_D_2_19,
-   FF_TX_D_2_20 => FF_TX_D_2_20,
-   FF_TX_D_2_21 => FF_TX_D_2_21,
-   FF_TX_D_2_22 => FF_TX_D_2_22,
-   FF_TX_D_2_23 => FF_TX_D_2_23,
-   FF_TX_D_3_0 => FF_TX_D_3_0,
-   FF_TX_D_3_1 => FF_TX_D_3_1,
-   FF_TX_D_3_2 => FF_TX_D_3_2,
-   FF_TX_D_3_3 => FF_TX_D_3_3,
-   FF_TX_D_3_4 => FF_TX_D_3_4,
-   FF_TX_D_3_5 => FF_TX_D_3_5,
-   FF_TX_D_3_6 => FF_TX_D_3_6,
-   FF_TX_D_3_7 => FF_TX_D_3_7,
-   FF_TX_D_3_8 => FF_TX_D_3_8,
-   FF_TX_D_3_9 => FF_TX_D_3_9,
-   FF_TX_D_3_10 => FF_TX_D_3_10,
-   FF_TX_D_3_11 => FF_TX_D_3_11,
-   FF_TX_D_3_12 => FF_TX_D_3_12,
-   FF_TX_D_3_13 => FF_TX_D_3_13,
-   FF_TX_D_3_14 => FF_TX_D_3_14,
-   FF_TX_D_3_15 => FF_TX_D_3_15,
-   FF_TX_D_3_16 => FF_TX_D_3_16,
-   FF_TX_D_3_17 => FF_TX_D_3_17,
-   FF_TX_D_3_18 => FF_TX_D_3_18,
-   FF_TX_D_3_19 => FF_TX_D_3_19,
-   FF_TX_D_3_20 => FF_TX_D_3_20,
-   FF_TX_D_3_21 => FF_TX_D_3_21,
-   FF_TX_D_3_22 => FF_TX_D_3_22,
-   FF_TX_D_3_23 => FF_TX_D_3_23,
-   FF_TXI_CLK_0 => FF_TXI_CLK_0,
-   FF_TXI_CLK_1 => FF_TXI_CLK_1,
-   FF_TXI_CLK_2 => FF_TXI_CLK_2,
-   FF_TXI_CLK_3 => FF_TXI_CLK_3,
-   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
-   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
-   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
-   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
-   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
-   FFC_EI_EN_0 => FFC_EI_EN_0,
-   FFC_EI_EN_1 => FFC_EI_EN_1,
-   FFC_EI_EN_2 => FFC_EI_EN_2,
-   FFC_EI_EN_3 => FFC_EI_EN_3,
-   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
-   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
-   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
-   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
-   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
-   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
-   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
-   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
-   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
-   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
-   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
-   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
-   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
-   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
-   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
-   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
-   FFC_MACRO_RST => FFC_MACRO_RST,
-   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
-   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
-   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
-   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
-   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
-   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
-   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
-   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
-   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
-   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
-   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
-   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
-   FFC_QUAD_RST => FFC_QUAD_RST,
-   FFC_RRST_0 => FFC_RRST_0,
-   FFC_RRST_1 => FFC_RRST_1,
-   FFC_RRST_2 => FFC_RRST_2,
-   FFC_RRST_3 => FFC_RRST_3,
-   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
-   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
-   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
-   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
-   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
-   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
-   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
-   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
-   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
-   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
-   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
-   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
-   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
-   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
-   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
-   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
-   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
-   FFC_TRST => FFC_TRST,
-   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
-   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
-   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
-   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
-   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
-   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
-   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
-   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
-   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
-   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
-   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
-   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
-   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
-   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
-   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
-   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
-   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
-   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
-   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
-   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
-   LDR_CORE2TX_0 => LDR_CORE2TX_0,
-   LDR_CORE2TX_1 => LDR_CORE2TX_1,
-   LDR_CORE2TX_2 => LDR_CORE2TX_2,
-   LDR_CORE2TX_3 => LDR_CORE2TX_3,
-   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
-   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
-   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
-   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
-   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
-   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
-   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
-   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
-   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
-   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
-   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
-   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
-   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
-   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
-   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
-   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
-   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
-   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
-   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
-   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
-   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
-   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
-   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
-   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
-   SCIADDR0 => SCIADDR0,
-   SCIADDR1 => SCIADDR1,
-   SCIADDR2 => SCIADDR2,
-   SCIADDR3 => SCIADDR3,
-   SCIADDR4 => SCIADDR4,
-   SCIADDR5 => SCIADDR5,
-   SCIENAUX => SCIENAUX,
-   SCIENCH0 => SCIENCH0,
-   SCIENCH1 => SCIENCH1,
-   SCIENCH2 => SCIENCH2,
-   SCIENCH3 => SCIENCH3,
-   SCIRD => SCIRD,
-   SCISELAUX => SCISELAUX,
-   SCISELCH0 => SCISELCH0,
-   SCISELCH1 => SCISELCH1,
-   SCISELCH2 => SCISELCH2,
-   SCISELCH3 => SCISELCH3,
-   SCIWDATA0 => SCIWDATA0,
-   SCIWDATA1 => SCIWDATA1,
-   SCIWDATA2 => SCIWDATA2,
-   SCIWDATA3 => SCIWDATA3,
-   SCIWDATA4 => SCIWDATA4,
-   SCIWDATA5 => SCIWDATA5,
-   SCIWDATA6 => SCIWDATA6,
-   SCIWDATA7 => SCIWDATA7,
-   SCIWSTN => SCIWSTN,
-   HDOUTN0 => HDOUTN0,
-   HDOUTN1 => HDOUTN1,
-   HDOUTN2 => HDOUTN2,
-   HDOUTN3 => HDOUTN3,
-   HDOUTP0 => HDOUTP0,
-   HDOUTP1 => HDOUTP1,
-   HDOUTP2 => HDOUTP2,
-   HDOUTP3 => HDOUTP3,
-   COUT19 => COUT19,
-   COUT18 => COUT18,
-   COUT17 => COUT17,
-   COUT16 => COUT16,
-   COUT15 => COUT15,
-   COUT14 => COUT14,
-   COUT13 => COUT13,
-   COUT12 => COUT12,
-   COUT11 => COUT11,
-   COUT10 => COUT10,
-   COUT9 => COUT9,
-   COUT8 => COUT8,
-   COUT7 => COUT7,
-   COUT6 => COUT6,
-   COUT5 => COUT5,
-   COUT4 => COUT4,
-   COUT3 => COUT3,
-   COUT2 => COUT2,
-   COUT1 => COUT1,
-   COUT0 => COUT0,
-   FF_RX_D_0_0 => FF_RX_D_0_0,
-   FF_RX_D_0_1 => FF_RX_D_0_1,
-   FF_RX_D_0_2 => FF_RX_D_0_2,
-   FF_RX_D_0_3 => FF_RX_D_0_3,
-   FF_RX_D_0_4 => FF_RX_D_0_4,
-   FF_RX_D_0_5 => FF_RX_D_0_5,
-   FF_RX_D_0_6 => FF_RX_D_0_6,
-   FF_RX_D_0_7 => FF_RX_D_0_7,
-   FF_RX_D_0_8 => FF_RX_D_0_8,
-   FF_RX_D_0_9 => FF_RX_D_0_9,
-   FF_RX_D_0_10 => FF_RX_D_0_10,
-   FF_RX_D_0_11 => FF_RX_D_0_11,
-   FF_RX_D_0_12 => FF_RX_D_0_12,
-   FF_RX_D_0_13 => FF_RX_D_0_13,
-   FF_RX_D_0_14 => FF_RX_D_0_14,
-   FF_RX_D_0_15 => FF_RX_D_0_15,
-   FF_RX_D_0_16 => FF_RX_D_0_16,
-   FF_RX_D_0_17 => FF_RX_D_0_17,
-   FF_RX_D_0_18 => FF_RX_D_0_18,
-   FF_RX_D_0_19 => FF_RX_D_0_19,
-   FF_RX_D_0_20 => FF_RX_D_0_20,
-   FF_RX_D_0_21 => FF_RX_D_0_21,
-   FF_RX_D_0_22 => FF_RX_D_0_22,
-   FF_RX_D_0_23 => FF_RX_D_0_23,
-   FF_RX_D_1_0 => FF_RX_D_1_0,
-   FF_RX_D_1_1 => FF_RX_D_1_1,
-   FF_RX_D_1_2 => FF_RX_D_1_2,
-   FF_RX_D_1_3 => FF_RX_D_1_3,
-   FF_RX_D_1_4 => FF_RX_D_1_4,
-   FF_RX_D_1_5 => FF_RX_D_1_5,
-   FF_RX_D_1_6 => FF_RX_D_1_6,
-   FF_RX_D_1_7 => FF_RX_D_1_7,
-   FF_RX_D_1_8 => FF_RX_D_1_8,
-   FF_RX_D_1_9 => FF_RX_D_1_9,
-   FF_RX_D_1_10 => FF_RX_D_1_10,
-   FF_RX_D_1_11 => FF_RX_D_1_11,
-   FF_RX_D_1_12 => FF_RX_D_1_12,
-   FF_RX_D_1_13 => FF_RX_D_1_13,
-   FF_RX_D_1_14 => FF_RX_D_1_14,
-   FF_RX_D_1_15 => FF_RX_D_1_15,
-   FF_RX_D_1_16 => FF_RX_D_1_16,
-   FF_RX_D_1_17 => FF_RX_D_1_17,
-   FF_RX_D_1_18 => FF_RX_D_1_18,
-   FF_RX_D_1_19 => FF_RX_D_1_19,
-   FF_RX_D_1_20 => FF_RX_D_1_20,
-   FF_RX_D_1_21 => FF_RX_D_1_21,
-   FF_RX_D_1_22 => FF_RX_D_1_22,
-   FF_RX_D_1_23 => FF_RX_D_1_23,
-   FF_RX_D_2_0 => FF_RX_D_2_0,
-   FF_RX_D_2_1 => FF_RX_D_2_1,
-   FF_RX_D_2_2 => FF_RX_D_2_2,
-   FF_RX_D_2_3 => FF_RX_D_2_3,
-   FF_RX_D_2_4 => FF_RX_D_2_4,
-   FF_RX_D_2_5 => FF_RX_D_2_5,
-   FF_RX_D_2_6 => FF_RX_D_2_6,
-   FF_RX_D_2_7 => FF_RX_D_2_7,
-   FF_RX_D_2_8 => FF_RX_D_2_8,
-   FF_RX_D_2_9 => FF_RX_D_2_9,
-   FF_RX_D_2_10 => FF_RX_D_2_10,
-   FF_RX_D_2_11 => FF_RX_D_2_11,
-   FF_RX_D_2_12 => FF_RX_D_2_12,
-   FF_RX_D_2_13 => FF_RX_D_2_13,
-   FF_RX_D_2_14 => FF_RX_D_2_14,
-   FF_RX_D_2_15 => FF_RX_D_2_15,
-   FF_RX_D_2_16 => FF_RX_D_2_16,
-   FF_RX_D_2_17 => FF_RX_D_2_17,
-   FF_RX_D_2_18 => FF_RX_D_2_18,
-   FF_RX_D_2_19 => FF_RX_D_2_19,
-   FF_RX_D_2_20 => FF_RX_D_2_20,
-   FF_RX_D_2_21 => FF_RX_D_2_21,
-   FF_RX_D_2_22 => FF_RX_D_2_22,
-   FF_RX_D_2_23 => FF_RX_D_2_23,
-   FF_RX_D_3_0 => FF_RX_D_3_0,
-   FF_RX_D_3_1 => FF_RX_D_3_1,
-   FF_RX_D_3_2 => FF_RX_D_3_2,
-   FF_RX_D_3_3 => FF_RX_D_3_3,
-   FF_RX_D_3_4 => FF_RX_D_3_4,
-   FF_RX_D_3_5 => FF_RX_D_3_5,
-   FF_RX_D_3_6 => FF_RX_D_3_6,
-   FF_RX_D_3_7 => FF_RX_D_3_7,
-   FF_RX_D_3_8 => FF_RX_D_3_8,
-   FF_RX_D_3_9 => FF_RX_D_3_9,
-   FF_RX_D_3_10 => FF_RX_D_3_10,
-   FF_RX_D_3_11 => FF_RX_D_3_11,
-   FF_RX_D_3_12 => FF_RX_D_3_12,
-   FF_RX_D_3_13 => FF_RX_D_3_13,
-   FF_RX_D_3_14 => FF_RX_D_3_14,
-   FF_RX_D_3_15 => FF_RX_D_3_15,
-   FF_RX_D_3_16 => FF_RX_D_3_16,
-   FF_RX_D_3_17 => FF_RX_D_3_17,
-   FF_RX_D_3_18 => FF_RX_D_3_18,
-   FF_RX_D_3_19 => FF_RX_D_3_19,
-   FF_RX_D_3_20 => FF_RX_D_3_20,
-   FF_RX_D_3_21 => FF_RX_D_3_21,
-   FF_RX_D_3_22 => FF_RX_D_3_22,
-   FF_RX_D_3_23 => FF_RX_D_3_23,
-   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
-   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
-   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
-   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
-   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
-   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
-   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
-   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
-   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
-   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
-   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
-   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
-   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
-   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
-   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
-   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
-   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
-   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
-   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
-   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
-   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
-   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
-   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
-   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
-   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
-   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
-   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
-   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
-   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
-   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
-   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
-   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
-   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
-   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
-   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
-   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
-   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
-   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
-   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
-   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
-   FFS_PLOL => FFS_PLOL,
-   FFS_RLOL_0 => FFS_RLOL_0,
-   FFS_RLOL_1 => FFS_RLOL_1,
-   FFS_RLOL_2 => FFS_RLOL_2,
-   FFS_RLOL_3 => FFS_RLOL_3,
-   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
-   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
-   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
-   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
-   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
-   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
-   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
-   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
-   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
-   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
-   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
-   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
-   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
-   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
-   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
-   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
-   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
-   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
-   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
-   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
-   PCIE_RXVALID_0 => PCIE_RXVALID_0,
-   PCIE_RXVALID_1 => PCIE_RXVALID_1,
-   PCIE_RXVALID_2 => PCIE_RXVALID_2,
-   PCIE_RXVALID_3 => PCIE_RXVALID_3,
-   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
-   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
-   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
-   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
-   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
-   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
-   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
-   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
-   LDR_RX2CORE_0 => LDR_RX2CORE_0,
-   LDR_RX2CORE_1 => LDR_RX2CORE_1,
-   LDR_RX2CORE_2 => LDR_RX2CORE_2,
-   LDR_RX2CORE_3 => LDR_RX2CORE_3,
-   REFCK2CORE => REFCK2CORE,
-   SCIINT => SCIINT,
-   SCIRDATA0 => SCIRDATA0,
-   SCIRDATA1 => SCIRDATA1,
-   SCIRDATA2 => SCIRDATA2,
-   SCIRDATA3 => SCIRDATA3,
-   SCIRDATA4 => SCIRDATA4,
-   SCIRDATA5 => SCIRDATA5,
-   SCIRDATA6 => SCIRDATA6,
-   SCIRDATA7 => SCIRDATA7,
-   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
-   REFCLK_TO_NQ => REFCLK_TO_NQ
-   );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_4_sync_hub_downstream is
-   GENERIC (USER_CONFIG_FILE    :  String := "serdes_4_sync_hub_downstream.txt");
- port (
-------------------
--- CH0 --
-    hdinp_ch0, hdinn_ch0    :   in std_logic;
-    hdoutp_ch0, hdoutn_ch0   :   out std_logic;
-    sci_sel_ch0    :   in std_logic;
-    txiclk_ch0    :   in std_logic;
-    rx_full_clk_ch0   :   out std_logic;
-    rx_half_clk_ch0   :   out std_logic;
-    tx_full_clk_ch0   :   out std_logic;
-    tx_half_clk_ch0   :   out std_logic;
-    fpga_rxrefclk_ch0    :   in std_logic;
-    txdata_ch0    :   in std_logic_vector (7 downto 0);
-    tx_k_ch0    :   in std_logic;
-    tx_force_disp_ch0    :   in std_logic;
-    tx_disp_sel_ch0    :   in std_logic;
-    rxdata_ch0   :   out std_logic_vector (7 downto 0);
-    rx_k_ch0   :   out std_logic;
-    rx_disp_err_ch0   :   out std_logic;
-    rx_cv_err_ch0   :   out std_logic;
-    rx_serdes_rst_ch0_c    :   in std_logic;
-    sb_felb_ch0_c    :   in std_logic;
-    sb_felb_rst_ch0_c    :   in std_logic;
-    tx_pcs_rst_ch0_c    :   in std_logic;
-    tx_pwrup_ch0_c    :   in std_logic;
-    rx_pcs_rst_ch0_c    :   in std_logic;
-    rx_pwrup_ch0_c    :   in std_logic;
-    rx_los_low_ch0_s   :   out std_logic;
-    lsm_status_ch0_s   :   out std_logic;
-    rx_cdr_lol_ch0_s   :   out std_logic;
-    tx_div2_mode_ch0_c   : in std_logic;
-    rx_div2_mode_ch0_c   : in std_logic;
--- CH1 --
-    hdinp_ch1, hdinn_ch1    :   in std_logic;
-    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
-    sci_sel_ch1    :   in std_logic;
-    txiclk_ch1    :   in std_logic;
-    rx_full_clk_ch1   :   out std_logic;
-    rx_half_clk_ch1   :   out std_logic;
-    tx_full_clk_ch1   :   out std_logic;
-    tx_half_clk_ch1   :   out std_logic;
-    fpga_rxrefclk_ch1    :   in std_logic;
-    txdata_ch1    :   in std_logic_vector (7 downto 0);
-    tx_k_ch1    :   in std_logic;
-    tx_force_disp_ch1    :   in std_logic;
-    tx_disp_sel_ch1    :   in std_logic;
-    rxdata_ch1   :   out std_logic_vector (7 downto 0);
-    rx_k_ch1   :   out std_logic;
-    rx_disp_err_ch1   :   out std_logic;
-    rx_cv_err_ch1   :   out std_logic;
-    rx_serdes_rst_ch1_c    :   in std_logic;
-    sb_felb_ch1_c    :   in std_logic;
-    sb_felb_rst_ch1_c    :   in std_logic;
-    tx_pcs_rst_ch1_c    :   in std_logic;
-    tx_pwrup_ch1_c    :   in std_logic;
-    rx_pcs_rst_ch1_c    :   in std_logic;
-    rx_pwrup_ch1_c    :   in std_logic;
-    rx_los_low_ch1_s   :   out std_logic;
-    lsm_status_ch1_s   :   out std_logic;
-    rx_cdr_lol_ch1_s   :   out std_logic;
-    tx_div2_mode_ch1_c   : in std_logic;
-    rx_div2_mode_ch1_c   : in std_logic;
--- CH2 --
-    hdinp_ch2, hdinn_ch2    :   in std_logic;
-    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
-    sci_sel_ch2    :   in std_logic;
-    txiclk_ch2    :   in std_logic;
-    rx_full_clk_ch2   :   out std_logic;
-    rx_half_clk_ch2   :   out std_logic;
-    tx_full_clk_ch2   :   out std_logic;
-    tx_half_clk_ch2   :   out std_logic;
-    fpga_rxrefclk_ch2    :   in std_logic;
-    txdata_ch2    :   in std_logic_vector (7 downto 0);
-    tx_k_ch2    :   in std_logic;
-    tx_force_disp_ch2    :   in std_logic;
-    tx_disp_sel_ch2    :   in std_logic;
-    rxdata_ch2   :   out std_logic_vector (7 downto 0);
-    rx_k_ch2   :   out std_logic;
-    rx_disp_err_ch2   :   out std_logic;
-    rx_cv_err_ch2   :   out std_logic;
-    rx_serdes_rst_ch2_c    :   in std_logic;
-    sb_felb_ch2_c    :   in std_logic;
-    sb_felb_rst_ch2_c    :   in std_logic;
-    tx_pcs_rst_ch2_c    :   in std_logic;
-    tx_pwrup_ch2_c    :   in std_logic;
-    rx_pcs_rst_ch2_c    :   in std_logic;
-    rx_pwrup_ch2_c    :   in std_logic;
-    rx_los_low_ch2_s   :   out std_logic;
-    lsm_status_ch2_s   :   out std_logic;
-    rx_cdr_lol_ch2_s   :   out std_logic;
-    tx_div2_mode_ch2_c   : in std_logic;
-    rx_div2_mode_ch2_c   : in std_logic;
--- CH3 --
-    hdinp_ch3, hdinn_ch3    :   in std_logic;
-    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
-    sci_sel_ch3    :   in std_logic;
-    txiclk_ch3    :   in std_logic;
-    rx_full_clk_ch3   :   out std_logic;
-    rx_half_clk_ch3   :   out std_logic;
-    tx_full_clk_ch3   :   out std_logic;
-    tx_half_clk_ch3   :   out std_logic;
-    fpga_rxrefclk_ch3    :   in std_logic;
-    txdata_ch3    :   in std_logic_vector (7 downto 0);
-    tx_k_ch3    :   in std_logic;
-    tx_force_disp_ch3    :   in std_logic;
-    tx_disp_sel_ch3    :   in std_logic;
-    rxdata_ch3   :   out std_logic_vector (7 downto 0);
-    rx_k_ch3   :   out std_logic;
-    rx_disp_err_ch3   :   out std_logic;
-    rx_cv_err_ch3   :   out std_logic;
-    rx_serdes_rst_ch3_c    :   in std_logic;
-    sb_felb_ch3_c    :   in std_logic;
-    sb_felb_rst_ch3_c    :   in std_logic;
-    tx_pcs_rst_ch3_c    :   in std_logic;
-    tx_pwrup_ch3_c    :   in std_logic;
-    rx_pcs_rst_ch3_c    :   in std_logic;
-    rx_pwrup_ch3_c    :   in std_logic;
-    rx_los_low_ch3_s   :   out std_logic;
-    lsm_status_ch3_s   :   out std_logic;
-    rx_cdr_lol_ch3_s   :   out std_logic;
-    tx_div2_mode_ch3_c   : in std_logic;
-    rx_div2_mode_ch3_c   : in std_logic;
----- Miscillaneous ports
-    sci_wrdata    :   in std_logic_vector (7 downto 0);
-    sci_addr    :   in std_logic_vector (5 downto 0);
-    sci_rddata   :   out std_logic_vector (7 downto 0);
-    sci_sel_quad    :   in std_logic;
-    sci_rd    :   in std_logic;
-    sci_wrn    :   in std_logic;
-    fpga_txrefclk  :   in std_logic;
-    tx_serdes_rst_c    :   in std_logic;
-    tx_pll_lol_qd_s   :   out std_logic;
-    tx_sync_qd_c    :   in std_logic;
-    rst_qd_c    :   in std_logic;
-    refclk2fpga   :   out std_logic;
-    serdes_rst_qd_c    :   in std_logic);
-
-end serdes_4_sync_hub_downstream;
-
-
-architecture serdes_4_sync_hub_downstream_arch of serdes_4_sync_hub_downstream is
-
-component VLO
-port (
-   Z : out std_logic);
-end component;
-
-component VHI
-port (
-   Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
-  );
---synopsys translate_on
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-   attribute CONFIG_FILE: string;
-   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
-   attribute QUAD_MODE: string;
-   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
-   attribute PLL_SRC: string;
-   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH0_CDR_SRC: string;
-   attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH1_CDR_SRC: string;
-   attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH2_CDR_SRC: string;
-   attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH3_CDR_SRC: string;
-   attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_REFCK2CORE: string;
-   attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
-   attribute black_box_pad_pin: string;
-   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal    tx_full_clk_ch0_sig   :   std_logic;
-signal    tx_full_clk_ch1_sig   :   std_logic;
-signal    tx_full_clk_ch2_sig   :   std_logic;
-signal    tx_full_clk_ch3_sig   :   std_logic;
-
-signal    refclk2fpga_sig  :   std_logic;
-signal    tx_pll_lol_qd_sig  :   std_logic;
-signal    rx_los_low_ch0_sig  :   std_logic;
-signal    rx_los_low_ch1_sig  :   std_logic;
-signal    rx_los_low_ch2_sig  :   std_logic;
-signal    rx_los_low_ch3_sig  :   std_logic;
-signal    rx_cdr_lol_ch0_sig  :   std_logic;
-signal    rx_cdr_lol_ch1_sig  :   std_logic;
-signal    rx_cdr_lol_ch2_sig  :   std_logic;
-signal    rx_cdr_lol_ch3_sig  :   std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
-  refclk2fpga <= refclk2fpga_sig;
-    rx_los_low_ch0_s <= rx_los_low_ch0_sig;
-    rx_los_low_ch1_s <= rx_los_low_ch1_sig;
-    rx_los_low_ch2_s <= rx_los_low_ch2_sig;
-    rx_los_low_ch3_s <= rx_los_low_ch3_sig;
-    rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
-    rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
-    rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
-    rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
-  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
-  tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
-  tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
-  tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
-  tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
-  generic map (CONFIG_FILE => USER_CONFIG_FILE,
-               QUAD_MODE => "SINGLE",
-               CH0_CDR_SRC => "REFCLK_CORE",
-               CH1_CDR_SRC => "REFCLK_CORE",
-               CH2_CDR_SRC => "REFCLK_CORE",
-               CH3_CDR_SRC => "REFCLK_CORE",
-               PLL_SRC  => "REFCLK_CORE"
-  )
---synopsys translate_on
-port map  (
-  REFCLKP => fpsc_vlo,
-  REFCLKN => fpsc_vlo,
-
------ CH0 -----
-  HDOUTP0 => hdoutp_ch0,
-  HDOUTN0 => hdoutn_ch0,
-  HDINP0 => hdinp_ch0,
-  HDINN0 => hdinn_ch0,
-  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
-  PCIE_RXPOLARITY_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_1 => fpsc_vlo,
-  PCIE_RXVALID_0 => open,
-  PCIE_PHYSTATUS_0 => open,
-  SCISELCH0 => sci_sel_ch0,
-  SCIENCH0 => fpsc_vhi,
-  FF_RXI_CLK_0 => fpsc_vlo,
-  FF_TXI_CLK_0 => txiclk_ch0,
-  FF_EBRD_CLK_0 => fpsc_vlo,
-  FF_RX_F_CLK_0 => rx_full_clk_ch0,
-  FF_RX_H_CLK_0 => rx_half_clk_ch0,
-  FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
-  FF_TX_H_CLK_0 => tx_half_clk_ch0,
-  FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
-  FF_TX_D_0_0 => txdata_ch0(0),
-  FF_TX_D_0_1 => txdata_ch0(1),
-  FF_TX_D_0_2 => txdata_ch0(2),
-  FF_TX_D_0_3 => txdata_ch0(3),
-  FF_TX_D_0_4 => txdata_ch0(4),
-  FF_TX_D_0_5 => txdata_ch0(5),
-  FF_TX_D_0_6 => txdata_ch0(6),
-  FF_TX_D_0_7 => txdata_ch0(7),
-  FF_TX_D_0_8 => tx_k_ch0,
-  FF_TX_D_0_9 => tx_force_disp_ch0,
-  FF_TX_D_0_10 => tx_disp_sel_ch0,
-  FF_TX_D_0_11 => fpsc_vlo,
-  FF_TX_D_0_12 => fpsc_vlo,
-  FF_TX_D_0_13 => fpsc_vlo,
-  FF_TX_D_0_14 => fpsc_vlo,
-  FF_TX_D_0_15 => fpsc_vlo,
-  FF_TX_D_0_16 => fpsc_vlo,
-  FF_TX_D_0_17 => fpsc_vlo,
-  FF_TX_D_0_18 => fpsc_vlo,
-  FF_TX_D_0_19 => fpsc_vlo,
-  FF_TX_D_0_20 => fpsc_vlo,
-  FF_TX_D_0_21 => fpsc_vlo,
-  FF_TX_D_0_22 => fpsc_vlo,
-  FF_TX_D_0_23 => fpsc_vlo,
-  FF_RX_D_0_0 => rxdata_ch0(0),
-  FF_RX_D_0_1 => rxdata_ch0(1),
-  FF_RX_D_0_2 => rxdata_ch0(2),
-  FF_RX_D_0_3 => rxdata_ch0(3),
-  FF_RX_D_0_4 => rxdata_ch0(4),
-  FF_RX_D_0_5 => rxdata_ch0(5),
-  FF_RX_D_0_6 => rxdata_ch0(6),
-  FF_RX_D_0_7 => rxdata_ch0(7),
-  FF_RX_D_0_8 => rx_k_ch0,
-  FF_RX_D_0_9 => rx_disp_err_ch0,
-  FF_RX_D_0_10 => rx_cv_err_ch0,
-  FF_RX_D_0_11 => open,
-  FF_RX_D_0_12 => open,
-  FF_RX_D_0_13 => open,
-  FF_RX_D_0_14 => open,
-  FF_RX_D_0_15 => open,
-  FF_RX_D_0_16 => open,
-  FF_RX_D_0_17 => open,
-  FF_RX_D_0_18 => open,
-  FF_RX_D_0_19 => open,
-  FF_RX_D_0_20 => open,
-  FF_RX_D_0_21 => open,
-  FF_RX_D_0_22 => open,
-  FF_RX_D_0_23 => open,
-
-  FFC_RRST_0 => rx_serdes_rst_ch0_c,
-  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
-  FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
-  FFC_SB_INV_RX_0 => fpsc_vlo,
-  FFC_PCIE_CT_0 => fpsc_vlo,
-  FFC_PCI_DET_EN_0 => fpsc_vlo,
-  FFC_FB_LOOPBACK_0 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
-  FFC_EI_EN_0 => fpsc_vlo,
-  FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
-  FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
-  FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
-  FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
-  FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
-  FFS_RLOS_HI_0 => open,
-  FFS_PCIE_CON_0 => open,
-  FFS_PCIE_DONE_0 => open,
-  FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
-  FFS_CC_OVERRUN_0 => open,
-  FFS_CC_UNDERRUN_0 => open,
-  FFS_SKP_ADDED_0 => open,
-  FFS_SKP_DELETED_0 => open,
-  FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
-  FFS_RXFBFIFO_ERROR_0 => open,
-  FFS_TXFBFIFO_ERROR_0 => open,
-  LDR_CORE2TX_0 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
-  LDR_RX2CORE_0 => open,
-  FFS_CDR_TRAIN_DONE_0 => open,
-  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
-  FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
-  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
-  FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
-
------ CH1 -----
-  HDOUTP1 => hdoutp_ch1,
-  HDOUTN1 => hdoutn_ch1,
-  HDINP1 => hdinp_ch1,
-  HDINN1 => hdinn_ch1,
-  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
-  PCIE_RXPOLARITY_1 => fpsc_vlo,
-  PCIE_POWERDOWN_1_0 => fpsc_vlo,
-  PCIE_POWERDOWN_1_1 => fpsc_vlo,
-  PCIE_RXVALID_1 => open,
-  PCIE_PHYSTATUS_1 => open,
-  SCISELCH1 => sci_sel_ch1,
-  SCIENCH1 => fpsc_vhi,
-  FF_RXI_CLK_1 => fpsc_vlo,
-  FF_TXI_CLK_1 => txiclk_ch1,
-  FF_EBRD_CLK_1 => fpsc_vlo,
-  FF_RX_F_CLK_1 => rx_full_clk_ch1,
-  FF_RX_H_CLK_1 => rx_half_clk_ch1,
-  FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
-  FF_TX_H_CLK_1 => tx_half_clk_ch1,
-  FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
-  FF_TX_D_1_0 => txdata_ch1(0),
-  FF_TX_D_1_1 => txdata_ch1(1),
-  FF_TX_D_1_2 => txdata_ch1(2),
-  FF_TX_D_1_3 => txdata_ch1(3),
-  FF_TX_D_1_4 => txdata_ch1(4),
-  FF_TX_D_1_5 => txdata_ch1(5),
-  FF_TX_D_1_6 => txdata_ch1(6),
-  FF_TX_D_1_7 => txdata_ch1(7),
-  FF_TX_D_1_8 => tx_k_ch1,
-  FF_TX_D_1_9 => tx_force_disp_ch1,
-  FF_TX_D_1_10 => tx_disp_sel_ch1,
-  FF_TX_D_1_11 => fpsc_vlo,
-  FF_TX_D_1_12 => fpsc_vlo,
-  FF_TX_D_1_13 => fpsc_vlo,
-  FF_TX_D_1_14 => fpsc_vlo,
-  FF_TX_D_1_15 => fpsc_vlo,
-  FF_TX_D_1_16 => fpsc_vlo,
-  FF_TX_D_1_17 => fpsc_vlo,
-  FF_TX_D_1_18 => fpsc_vlo,
-  FF_TX_D_1_19 => fpsc_vlo,
-  FF_TX_D_1_20 => fpsc_vlo,
-  FF_TX_D_1_21 => fpsc_vlo,
-  FF_TX_D_1_22 => fpsc_vlo,
-  FF_TX_D_1_23 => fpsc_vlo,
-  FF_RX_D_1_0 => rxdata_ch1(0),
-  FF_RX_D_1_1 => rxdata_ch1(1),
-  FF_RX_D_1_2 => rxdata_ch1(2),
-  FF_RX_D_1_3 => rxdata_ch1(3),
-  FF_RX_D_1_4 => rxdata_ch1(4),
-  FF_RX_D_1_5 => rxdata_ch1(5),
-  FF_RX_D_1_6 => rxdata_ch1(6),
-  FF_RX_D_1_7 => rxdata_ch1(7),
-  FF_RX_D_1_8 => rx_k_ch1,
-  FF_RX_D_1_9 => rx_disp_err_ch1,
-  FF_RX_D_1_10 => rx_cv_err_ch1,
-  FF_RX_D_1_11 => open,
-  FF_RX_D_1_12 => open,
-  FF_RX_D_1_13 => open,
-  FF_RX_D_1_14 => open,
-  FF_RX_D_1_15 => open,
-  FF_RX_D_1_16 => open,
-  FF_RX_D_1_17 => open,
-  FF_RX_D_1_18 => open,
-  FF_RX_D_1_19 => open,
-  FF_RX_D_1_20 => open,
-  FF_RX_D_1_21 => open,
-  FF_RX_D_1_22 => open,
-  FF_RX_D_1_23 => open,
-
-  FFC_RRST_1 => rx_serdes_rst_ch1_c,
-  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
-  FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
-  FFC_SB_INV_RX_1 => fpsc_vlo,
-  FFC_PCIE_CT_1 => fpsc_vlo,
-  FFC_PCI_DET_EN_1 => fpsc_vlo,
-  FFC_FB_LOOPBACK_1 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
-  FFC_EI_EN_1 => fpsc_vlo,
-  FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
-  FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
-  FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
-  FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
-  FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
-  FFS_RLOS_HI_1 => open,
-  FFS_PCIE_CON_1 => open,
-  FFS_PCIE_DONE_1 => open,
-  FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
-  FFS_CC_OVERRUN_1 => open,
-  FFS_CC_UNDERRUN_1 => open,
-  FFS_SKP_ADDED_1 => open,
-  FFS_SKP_DELETED_1 => open,
-  FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
-  FFS_RXFBFIFO_ERROR_1 => open,
-  FFS_TXFBFIFO_ERROR_1 => open,
-  LDR_CORE2TX_1 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
-  LDR_RX2CORE_1 => open,
-  FFS_CDR_TRAIN_DONE_1 => open,
-  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
-  FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
-  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
-  FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
-
------ CH2 -----
-  HDOUTP2 => hdoutp_ch2,
-  HDOUTN2 => hdoutn_ch2,
-  HDINP2 => hdinp_ch2,
-  HDINN2 => hdinn_ch2,
-  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
-  PCIE_RXPOLARITY_2 => fpsc_vlo,
-  PCIE_POWERDOWN_2_0 => fpsc_vlo,
-  PCIE_POWERDOWN_2_1 => fpsc_vlo,
-  PCIE_RXVALID_2 => open,
-  PCIE_PHYSTATUS_2 => open,
-  SCISELCH2 => sci_sel_ch2,
-  SCIENCH2 => fpsc_vhi,
-  FF_RXI_CLK_2 => fpsc_vlo,
-  FF_TXI_CLK_2 => txiclk_ch2,
-  FF_EBRD_CLK_2 => fpsc_vlo,
-  FF_RX_F_CLK_2 => rx_full_clk_ch2,
-  FF_RX_H_CLK_2 => rx_half_clk_ch2,
-  FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
-  FF_TX_H_CLK_2 => tx_half_clk_ch2,
-  FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
-  FF_TX_D_2_0 => txdata_ch2(0),
-  FF_TX_D_2_1 => txdata_ch2(1),
-  FF_TX_D_2_2 => txdata_ch2(2),
-  FF_TX_D_2_3 => txdata_ch2(3),
-  FF_TX_D_2_4 => txdata_ch2(4),
-  FF_TX_D_2_5 => txdata_ch2(5),
-  FF_TX_D_2_6 => txdata_ch2(6),
-  FF_TX_D_2_7 => txdata_ch2(7),
-  FF_TX_D_2_8 => tx_k_ch2,
-  FF_TX_D_2_9 => tx_force_disp_ch2,
-  FF_TX_D_2_10 => tx_disp_sel_ch2,
-  FF_TX_D_2_11 => fpsc_vlo,
-  FF_TX_D_2_12 => fpsc_vlo,
-  FF_TX_D_2_13 => fpsc_vlo,
-  FF_TX_D_2_14 => fpsc_vlo,
-  FF_TX_D_2_15 => fpsc_vlo,
-  FF_TX_D_2_16 => fpsc_vlo,
-  FF_TX_D_2_17 => fpsc_vlo,
-  FF_TX_D_2_18 => fpsc_vlo,
-  FF_TX_D_2_19 => fpsc_vlo,
-  FF_TX_D_2_20 => fpsc_vlo,
-  FF_TX_D_2_21 => fpsc_vlo,
-  FF_TX_D_2_22 => fpsc_vlo,
-  FF_TX_D_2_23 => fpsc_vlo,
-  FF_RX_D_2_0 => rxdata_ch2(0),
-  FF_RX_D_2_1 => rxdata_ch2(1),
-  FF_RX_D_2_2 => rxdata_ch2(2),
-  FF_RX_D_2_3 => rxdata_ch2(3),
-  FF_RX_D_2_4 => rxdata_ch2(4),
-  FF_RX_D_2_5 => rxdata_ch2(5),
-  FF_RX_D_2_6 => rxdata_ch2(6),
-  FF_RX_D_2_7 => rxdata_ch2(7),
-  FF_RX_D_2_8 => rx_k_ch2,
-  FF_RX_D_2_9 => rx_disp_err_ch2,
-  FF_RX_D_2_10 => rx_cv_err_ch2,
-  FF_RX_D_2_11 => open,
-  FF_RX_D_2_12 => open,
-  FF_RX_D_2_13 => open,
-  FF_RX_D_2_14 => open,
-  FF_RX_D_2_15 => open,
-  FF_RX_D_2_16 => open,
-  FF_RX_D_2_17 => open,
-  FF_RX_D_2_18 => open,
-  FF_RX_D_2_19 => open,
-  FF_RX_D_2_20 => open,
-  FF_RX_D_2_21 => open,
-  FF_RX_D_2_22 => open,
-  FF_RX_D_2_23 => open,
-
-  FFC_RRST_2 => rx_serdes_rst_ch2_c,
-  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c,
-  FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c,
-  FFC_SB_INV_RX_2 => fpsc_vlo,
-  FFC_PCIE_CT_2 => fpsc_vlo,
-  FFC_PCI_DET_EN_2 => fpsc_vlo,
-  FFC_FB_LOOPBACK_2 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
-  FFC_EI_EN_2 => fpsc_vlo,
-  FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c,
-  FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
-  FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
-  FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
-  FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
-  FFS_RLOS_HI_2 => open,
-  FFS_PCIE_CON_2 => open,
-  FFS_PCIE_DONE_2 => open,
-  FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
-  FFS_CC_OVERRUN_2 => open,
-  FFS_CC_UNDERRUN_2 => open,
-  FFS_SKP_ADDED_2 => open,
-  FFS_SKP_DELETED_2 => open,
-  FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
-  FFS_RXFBFIFO_ERROR_2 => open,
-  FFS_TXFBFIFO_ERROR_2 => open,
-  LDR_CORE2TX_2 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
-  LDR_RX2CORE_2 => open,
-  FFS_CDR_TRAIN_DONE_2 => open,
-  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
-  FFC_RATE_MODE_TX_2 => tx_div2_mode_ch2_c,
-  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
-  FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
-
------ CH3 -----
-  HDOUTP3 => hdoutp_ch3,
-  HDOUTN3 => hdoutn_ch3,
-  HDINP3 => hdinp_ch3,
-  HDINN3 => hdinn_ch3,
-  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
-  PCIE_RXPOLARITY_3 => fpsc_vlo,
-  PCIE_POWERDOWN_3_0 => fpsc_vlo,
-  PCIE_POWERDOWN_3_1 => fpsc_vlo,
-  PCIE_RXVALID_3 => open,
-  PCIE_PHYSTATUS_3 => open,
-  SCISELCH3 => sci_sel_ch3,
-  SCIENCH3 => fpsc_vhi,
-  FF_RXI_CLK_3 => fpsc_vlo,
-  FF_TXI_CLK_3 => txiclk_ch3,
-  FF_EBRD_CLK_3 => fpsc_vlo,
-  FF_RX_F_CLK_3 => rx_full_clk_ch3,
-  FF_RX_H_CLK_3 => rx_half_clk_ch3,
-  FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
-  FF_TX_H_CLK_3 => tx_half_clk_ch3,
-  FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
-  FF_TX_D_3_0 => txdata_ch3(0),
-  FF_TX_D_3_1 => txdata_ch3(1),
-  FF_TX_D_3_2 => txdata_ch3(2),
-  FF_TX_D_3_3 => txdata_ch3(3),
-  FF_TX_D_3_4 => txdata_ch3(4),
-  FF_TX_D_3_5 => txdata_ch3(5),
-  FF_TX_D_3_6 => txdata_ch3(6),
-  FF_TX_D_3_7 => txdata_ch3(7),
-  FF_TX_D_3_8 => tx_k_ch3,
-  FF_TX_D_3_9 => tx_force_disp_ch3,
-  FF_TX_D_3_10 => tx_disp_sel_ch3,
-  FF_TX_D_3_11 => fpsc_vlo,
-  FF_TX_D_3_12 => fpsc_vlo,
-  FF_TX_D_3_13 => fpsc_vlo,
-  FF_TX_D_3_14 => fpsc_vlo,
-  FF_TX_D_3_15 => fpsc_vlo,
-  FF_TX_D_3_16 => fpsc_vlo,
-  FF_TX_D_3_17 => fpsc_vlo,
-  FF_TX_D_3_18 => fpsc_vlo,
-  FF_TX_D_3_19 => fpsc_vlo,
-  FF_TX_D_3_20 => fpsc_vlo,
-  FF_TX_D_3_21 => fpsc_vlo,
-  FF_TX_D_3_22 => fpsc_vlo,
-  FF_TX_D_3_23 => fpsc_vlo,
-  FF_RX_D_3_0 => rxdata_ch3(0),
-  FF_RX_D_3_1 => rxdata_ch3(1),
-  FF_RX_D_3_2 => rxdata_ch3(2),
-  FF_RX_D_3_3 => rxdata_ch3(3),
-  FF_RX_D_3_4 => rxdata_ch3(4),
-  FF_RX_D_3_5 => rxdata_ch3(5),
-  FF_RX_D_3_6 => rxdata_ch3(6),
-  FF_RX_D_3_7 => rxdata_ch3(7),
-  FF_RX_D_3_8 => rx_k_ch3,
-  FF_RX_D_3_9 => rx_disp_err_ch3,
-  FF_RX_D_3_10 => rx_cv_err_ch3,
-  FF_RX_D_3_11 => open,
-  FF_RX_D_3_12 => open,
-  FF_RX_D_3_13 => open,
-  FF_RX_D_3_14 => open,
-  FF_RX_D_3_15 => open,
-  FF_RX_D_3_16 => open,
-  FF_RX_D_3_17 => open,
-  FF_RX_D_3_18 => open,
-  FF_RX_D_3_19 => open,
-  FF_RX_D_3_20 => open,
-  FF_RX_D_3_21 => open,
-  FF_RX_D_3_22 => open,
-  FF_RX_D_3_23 => open,
-
-  FFC_RRST_3 => rx_serdes_rst_ch3_c,
-  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
-  FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
-  FFC_SB_INV_RX_3 => fpsc_vlo,
-  FFC_PCIE_CT_3 => fpsc_vlo,
-  FFC_PCI_DET_EN_3 => fpsc_vlo,
-  FFC_FB_LOOPBACK_3 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
-  FFC_EI_EN_3 => fpsc_vlo,
-  FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
-  FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
-  FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
-  FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
-  FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
-  FFS_RLOS_HI_3 => open,
-  FFS_PCIE_CON_3 => open,
-  FFS_PCIE_DONE_3 => open,
-  FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
-  FFS_CC_OVERRUN_3 => open,
-  FFS_CC_UNDERRUN_3 => open,
-  FFS_SKP_ADDED_3 => open,
-  FFS_SKP_DELETED_3 => open,
-  FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
-  FFS_RXFBFIFO_ERROR_3 => open,
-  FFS_TXFBFIFO_ERROR_3 => open,
-  LDR_CORE2TX_3 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
-  LDR_RX2CORE_3 => open,
-  FFS_CDR_TRAIN_DONE_3 => open,
-  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
-  FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
-  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
-  FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
-
------ Auxilliary ----
-  SCIWDATA7 => sci_wrdata(7),
-  SCIWDATA6 => sci_wrdata(6),
-  SCIWDATA5 => sci_wrdata(5),
-  SCIWDATA4 => sci_wrdata(4),
-  SCIWDATA3 => sci_wrdata(3),
-  SCIWDATA2 => sci_wrdata(2),
-  SCIWDATA1 => sci_wrdata(1),
-  SCIWDATA0 => sci_wrdata(0),
-  SCIADDR5 => sci_addr(5),
-  SCIADDR4 => sci_addr(4),
-  SCIADDR3 => sci_addr(3),
-  SCIADDR2 => sci_addr(2),
-  SCIADDR1 => sci_addr(1),
-  SCIADDR0 => sci_addr(0),
-  SCIRDATA7 => sci_rddata(7),
-  SCIRDATA6 => sci_rddata(6),
-  SCIRDATA5 => sci_rddata(5),
-  SCIRDATA4 => sci_rddata(4),
-  SCIRDATA3 => sci_rddata(3),
-  SCIRDATA2 => sci_rddata(2),
-  SCIRDATA1 => sci_rddata(1),
-  SCIRDATA0 => sci_rddata(0),
-  SCIENAUX => fpsc_vhi,
-  SCISELAUX => sci_sel_quad,
-  SCIRD => sci_rd,
-  SCIWSTN => sci_wrn,
-  CYAWSTN => fpsc_vlo,
-  SCIINT => open,
-  FFC_CK_CORE_TX => fpga_txrefclk,
-  FFC_MACRO_RST => serdes_rst_qd_c,
-  FFC_QUAD_RST => rst_qd_c,
-  FFC_TRST => tx_serdes_rst_c,
-  FFS_PLOL => tx_pll_lol_qd_sig,
-  FFC_SYNC_TOGGLE => tx_sync_qd_c,
-  REFCK2CORE => refclk2fpga_sig,
-  CIN0 => fpsc_vlo,
-  CIN1 => fpsc_vlo,
-  CIN2 => fpsc_vlo,
-  CIN3 => fpsc_vlo,
-  CIN4 => fpsc_vlo,
-  CIN5 => fpsc_vlo,
-  CIN6 => fpsc_vlo,
-  CIN7 => fpsc_vlo,
-  CIN8 => fpsc_vlo,
-  CIN9 => fpsc_vlo,
-  CIN10 => fpsc_vlo,
-  CIN11 => fpsc_vlo,
-  COUT0 => open,
-  COUT1 => open,
-  COUT2 => open,
-  COUT3 => open,
-  COUT4 => open,
-  COUT5 => open,
-  COUT6 => open,
-  COUT7 => open,
-  COUT8 => open,
-  COUT9 => open,
-  COUT10 => open,
-  COUT11 => open,
-  COUT12 => open,
-  COUT13 => open,
-  COUT14 => open,
-  COUT15 => open,
-  COUT16 => open,
-  COUT17 => open,
-  COUT18 => open,
-  COUT19 => open,
-  REFCLK_FROM_NQ => refclk_from_nq,
-  REFCLK_TO_NQ => open);
-
-                                                                                              
-                                                                                              
-                                                                                              
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
-   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
-   IF (open_status = name_error) THEN
-      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
-      severity ERROR;
-   END IF;
-   wait;
-END PROCESS;
---synopsys translate_on
-end serdes_4_sync_hub_downstream_arch ;
diff --git a/code/ip/serdes_soda_upstream.ipx b/code/ip/serdes_soda_upstream.ipx
deleted file mode 100644
index ba43a74..0000000
--- a/code/ip/serdes_soda_upstream.ipx
+++ /dev/null
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 08 27 11:44:02.265" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-		<File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 08 27 11:44:00.000"/>
-		<File name="serdes_sync_upstream.pp" type="pp" modified="2014 08 27 11:44:00.000"/>
-		<File name="serdes_sync_upstream.sym" type="sym" modified="2014 08 27 11:44:00.000"/>
-		<File name="serdes_sync_upstream.tft" type="tft" modified="2014 08 27 11:44:00.000"/>
-		<File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 08 27 11:44:00.000"/>
-		<File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 08 27 11:44:00.000"/>
-  </Package>
-</DiamondModule>
diff --git a/code/ip/serdes_soda_upstream.lpc b/code/ip/serdes_soda_upstream.lpc
deleted file mode 100644
index 332fc40..0000000
--- a/code/ip/serdes_soda_upstream.lpc
+++ /dev/null
@@ -1,258 +0,0 @@
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_sync_upstream
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=08/27/2014
-Time=11:44:00
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=DISABLED
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=RXTX
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=DISABLED
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=G8B10B
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=DISABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=DISABLED
-_tx_ficlk_rate0=200
-_tx_ficlk_rate1=200
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=2
-_rx_protocol0=DISABLED
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=G8B10B
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=200
-_rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=200
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=DISABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=DISABLED
-_rx_ficlk_rate0=200
-_rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=DC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=00
-_k02=00
-_k03=01
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00000000
-_byten02=00000000
-_byten03=00011100
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_sync_upstream.pp=pp
-serdes_sync_upstream.tft=tft
-serdes_sync_upstream.txt=pcs_module
-serdes_sync_upstream.sym=sym
diff --git a/code/ip/serdes_soda_upstream.vhd b/code/ip/serdes_soda_upstream.vhd
deleted file mode 100644
index 0f86b70..0000000
--- a/code/ip/serdes_soda_upstream.vhd
+++ /dev/null
@@ -1,2701 +0,0 @@
-
-                                                                                                         
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
---  CONFIG_FILE : String  := "serdes_sync_upstream.txt";
---  QUAD_MODE : String := "SINGLE";
---  CH0_CDR_SRC   : String := "REFCLK_CORE";
---  CH1_CDR_SRC   : String := "REFCLK_EXT";
---  CH2_CDR_SRC   : String := "REFCLK_EXT";
---  CH3_CDR_SRC   : String := "REFCLK_CORE";
---  PLL_SRC   : String := "REFCLK_CORE"
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String;
-  CH1_CDR_SRC   : String;
-  CH2_CDR_SRC   : String;
-  CH3_CDR_SRC   : String;
-  PLL_SRC   : String
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
-  CONFIG_FILE => CONFIG_FILE,
-  QUAD_MODE => QUAD_MODE,
-  CH0_CDR_SRC => CH0_CDR_SRC,
-  CH1_CDR_SRC => CH1_CDR_SRC,
-  CH2_CDR_SRC => CH2_CDR_SRC,
-  CH3_CDR_SRC => CH3_CDR_SRC,
-  PLL_SRC => PLL_SRC
-  )
-port map (
-   HDINN0 => HDINN0,
-   HDINN1 => HDINN1,
-   HDINN2 => HDINN2,
-   HDINN3 => HDINN3,
-   HDINP0 => HDINP0,
-   HDINP1 => HDINP1,
-   HDINP2 => HDINP2,
-   HDINP3 => HDINP3,
-   REFCLKN => REFCLKN,
-   REFCLKP => REFCLKP,
-   CIN11 => CIN11,
-   CIN10 => CIN10,
-   CIN9 => CIN9,
-   CIN8 => CIN8,
-   CIN7 => CIN7,
-   CIN6 => CIN6,
-   CIN5 => CIN5,
-   CIN4 => CIN4,
-   CIN3 => CIN3,
-   CIN2 => CIN2,
-   CIN1 => CIN1,
-   CIN0 => CIN0,
-   CYAWSTN => CYAWSTN,
-   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
-   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
-   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
-   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
-   FF_RXI_CLK_3 => FF_RXI_CLK_3,
-   FF_RXI_CLK_2 => FF_RXI_CLK_2,
-   FF_RXI_CLK_1 => FF_RXI_CLK_1,
-   FF_RXI_CLK_0 => FF_RXI_CLK_0,
-   FF_TX_D_0_0 => FF_TX_D_0_0,
-   FF_TX_D_0_1 => FF_TX_D_0_1,
-   FF_TX_D_0_2 => FF_TX_D_0_2,
-   FF_TX_D_0_3 => FF_TX_D_0_3,
-   FF_TX_D_0_4 => FF_TX_D_0_4,
-   FF_TX_D_0_5 => FF_TX_D_0_5,
-   FF_TX_D_0_6 => FF_TX_D_0_6,
-   FF_TX_D_0_7 => FF_TX_D_0_7,
-   FF_TX_D_0_8 => FF_TX_D_0_8,
-   FF_TX_D_0_9 => FF_TX_D_0_9,
-   FF_TX_D_0_10 => FF_TX_D_0_10,
-   FF_TX_D_0_11 => FF_TX_D_0_11,
-   FF_TX_D_0_12 => FF_TX_D_0_12,
-   FF_TX_D_0_13 => FF_TX_D_0_13,
-   FF_TX_D_0_14 => FF_TX_D_0_14,
-   FF_TX_D_0_15 => FF_TX_D_0_15,
-   FF_TX_D_0_16 => FF_TX_D_0_16,
-   FF_TX_D_0_17 => FF_TX_D_0_17,
-   FF_TX_D_0_18 => FF_TX_D_0_18,
-   FF_TX_D_0_19 => FF_TX_D_0_19,
-   FF_TX_D_0_20 => FF_TX_D_0_20,
-   FF_TX_D_0_21 => FF_TX_D_0_21,
-   FF_TX_D_0_22 => FF_TX_D_0_22,
-   FF_TX_D_0_23 => FF_TX_D_0_23,
-   FF_TX_D_1_0 => FF_TX_D_1_0,
-   FF_TX_D_1_1 => FF_TX_D_1_1,
-   FF_TX_D_1_2 => FF_TX_D_1_2,
-   FF_TX_D_1_3 => FF_TX_D_1_3,
-   FF_TX_D_1_4 => FF_TX_D_1_4,
-   FF_TX_D_1_5 => FF_TX_D_1_5,
-   FF_TX_D_1_6 => FF_TX_D_1_6,
-   FF_TX_D_1_7 => FF_TX_D_1_7,
-   FF_TX_D_1_8 => FF_TX_D_1_8,
-   FF_TX_D_1_9 => FF_TX_D_1_9,
-   FF_TX_D_1_10 => FF_TX_D_1_10,
-   FF_TX_D_1_11 => FF_TX_D_1_11,
-   FF_TX_D_1_12 => FF_TX_D_1_12,
-   FF_TX_D_1_13 => FF_TX_D_1_13,
-   FF_TX_D_1_14 => FF_TX_D_1_14,
-   FF_TX_D_1_15 => FF_TX_D_1_15,
-   FF_TX_D_1_16 => FF_TX_D_1_16,
-   FF_TX_D_1_17 => FF_TX_D_1_17,
-   FF_TX_D_1_18 => FF_TX_D_1_18,
-   FF_TX_D_1_19 => FF_TX_D_1_19,
-   FF_TX_D_1_20 => FF_TX_D_1_20,
-   FF_TX_D_1_21 => FF_TX_D_1_21,
-   FF_TX_D_1_22 => FF_TX_D_1_22,
-   FF_TX_D_1_23 => FF_TX_D_1_23,
-   FF_TX_D_2_0 => FF_TX_D_2_0,
-   FF_TX_D_2_1 => FF_TX_D_2_1,
-   FF_TX_D_2_2 => FF_TX_D_2_2,
-   FF_TX_D_2_3 => FF_TX_D_2_3,
-   FF_TX_D_2_4 => FF_TX_D_2_4,
-   FF_TX_D_2_5 => FF_TX_D_2_5,
-   FF_TX_D_2_6 => FF_TX_D_2_6,
-   FF_TX_D_2_7 => FF_TX_D_2_7,
-   FF_TX_D_2_8 => FF_TX_D_2_8,
-   FF_TX_D_2_9 => FF_TX_D_2_9,
-   FF_TX_D_2_10 => FF_TX_D_2_10,
-   FF_TX_D_2_11 => FF_TX_D_2_11,
-   FF_TX_D_2_12 => FF_TX_D_2_12,
-   FF_TX_D_2_13 => FF_TX_D_2_13,
-   FF_TX_D_2_14 => FF_TX_D_2_14,
-   FF_TX_D_2_15 => FF_TX_D_2_15,
-   FF_TX_D_2_16 => FF_TX_D_2_16,
-   FF_TX_D_2_17 => FF_TX_D_2_17,
-   FF_TX_D_2_18 => FF_TX_D_2_18,
-   FF_TX_D_2_19 => FF_TX_D_2_19,
-   FF_TX_D_2_20 => FF_TX_D_2_20,
-   FF_TX_D_2_21 => FF_TX_D_2_21,
-   FF_TX_D_2_22 => FF_TX_D_2_22,
-   FF_TX_D_2_23 => FF_TX_D_2_23,
-   FF_TX_D_3_0 => FF_TX_D_3_0,
-   FF_TX_D_3_1 => FF_TX_D_3_1,
-   FF_TX_D_3_2 => FF_TX_D_3_2,
-   FF_TX_D_3_3 => FF_TX_D_3_3,
-   FF_TX_D_3_4 => FF_TX_D_3_4,
-   FF_TX_D_3_5 => FF_TX_D_3_5,
-   FF_TX_D_3_6 => FF_TX_D_3_6,
-   FF_TX_D_3_7 => FF_TX_D_3_7,
-   FF_TX_D_3_8 => FF_TX_D_3_8,
-   FF_TX_D_3_9 => FF_TX_D_3_9,
-   FF_TX_D_3_10 => FF_TX_D_3_10,
-   FF_TX_D_3_11 => FF_TX_D_3_11,
-   FF_TX_D_3_12 => FF_TX_D_3_12,
-   FF_TX_D_3_13 => FF_TX_D_3_13,
-   FF_TX_D_3_14 => FF_TX_D_3_14,
-   FF_TX_D_3_15 => FF_TX_D_3_15,
-   FF_TX_D_3_16 => FF_TX_D_3_16,
-   FF_TX_D_3_17 => FF_TX_D_3_17,
-   FF_TX_D_3_18 => FF_TX_D_3_18,
-   FF_TX_D_3_19 => FF_TX_D_3_19,
-   FF_TX_D_3_20 => FF_TX_D_3_20,
-   FF_TX_D_3_21 => FF_TX_D_3_21,
-   FF_TX_D_3_22 => FF_TX_D_3_22,
-   FF_TX_D_3_23 => FF_TX_D_3_23,
-   FF_TXI_CLK_0 => FF_TXI_CLK_0,
-   FF_TXI_CLK_1 => FF_TXI_CLK_1,
-   FF_TXI_CLK_2 => FF_TXI_CLK_2,
-   FF_TXI_CLK_3 => FF_TXI_CLK_3,
-   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
-   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
-   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
-   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
-   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
-   FFC_EI_EN_0 => FFC_EI_EN_0,
-   FFC_EI_EN_1 => FFC_EI_EN_1,
-   FFC_EI_EN_2 => FFC_EI_EN_2,
-   FFC_EI_EN_3 => FFC_EI_EN_3,
-   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
-   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
-   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
-   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
-   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
-   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
-   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
-   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
-   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
-   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
-   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
-   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
-   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
-   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
-   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
-   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
-   FFC_MACRO_RST => FFC_MACRO_RST,
-   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
-   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
-   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
-   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
-   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
-   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
-   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
-   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
-   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
-   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
-   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
-   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
-   FFC_QUAD_RST => FFC_QUAD_RST,
-   FFC_RRST_0 => FFC_RRST_0,
-   FFC_RRST_1 => FFC_RRST_1,
-   FFC_RRST_2 => FFC_RRST_2,
-   FFC_RRST_3 => FFC_RRST_3,
-   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
-   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
-   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
-   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
-   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
-   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
-   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
-   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
-   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
-   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
-   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
-   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
-   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
-   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
-   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
-   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
-   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
-   FFC_TRST => FFC_TRST,
-   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
-   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
-   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
-   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
-   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
-   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
-   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
-   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
-   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
-   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
-   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
-   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
-   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
-   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
-   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
-   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
-   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
-   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
-   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
-   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
-   LDR_CORE2TX_0 => LDR_CORE2TX_0,
-   LDR_CORE2TX_1 => LDR_CORE2TX_1,
-   LDR_CORE2TX_2 => LDR_CORE2TX_2,
-   LDR_CORE2TX_3 => LDR_CORE2TX_3,
-   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
-   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
-   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
-   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
-   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
-   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
-   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
-   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
-   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
-   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
-   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
-   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
-   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
-   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
-   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
-   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
-   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
-   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
-   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
-   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
-   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
-   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
-   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
-   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
-   SCIADDR0 => SCIADDR0,
-   SCIADDR1 => SCIADDR1,
-   SCIADDR2 => SCIADDR2,
-   SCIADDR3 => SCIADDR3,
-   SCIADDR4 => SCIADDR4,
-   SCIADDR5 => SCIADDR5,
-   SCIENAUX => SCIENAUX,
-   SCIENCH0 => SCIENCH0,
-   SCIENCH1 => SCIENCH1,
-   SCIENCH2 => SCIENCH2,
-   SCIENCH3 => SCIENCH3,
-   SCIRD => SCIRD,
-   SCISELAUX => SCISELAUX,
-   SCISELCH0 => SCISELCH0,
-   SCISELCH1 => SCISELCH1,
-   SCISELCH2 => SCISELCH2,
-   SCISELCH3 => SCISELCH3,
-   SCIWDATA0 => SCIWDATA0,
-   SCIWDATA1 => SCIWDATA1,
-   SCIWDATA2 => SCIWDATA2,
-   SCIWDATA3 => SCIWDATA3,
-   SCIWDATA4 => SCIWDATA4,
-   SCIWDATA5 => SCIWDATA5,
-   SCIWDATA6 => SCIWDATA6,
-   SCIWDATA7 => SCIWDATA7,
-   SCIWSTN => SCIWSTN,
-   HDOUTN0 => HDOUTN0,
-   HDOUTN1 => HDOUTN1,
-   HDOUTN2 => HDOUTN2,
-   HDOUTN3 => HDOUTN3,
-   HDOUTP0 => HDOUTP0,
-   HDOUTP1 => HDOUTP1,
-   HDOUTP2 => HDOUTP2,
-   HDOUTP3 => HDOUTP3,
-   COUT19 => COUT19,
-   COUT18 => COUT18,
-   COUT17 => COUT17,
-   COUT16 => COUT16,
-   COUT15 => COUT15,
-   COUT14 => COUT14,
-   COUT13 => COUT13,
-   COUT12 => COUT12,
-   COUT11 => COUT11,
-   COUT10 => COUT10,
-   COUT9 => COUT9,
-   COUT8 => COUT8,
-   COUT7 => COUT7,
-   COUT6 => COUT6,
-   COUT5 => COUT5,
-   COUT4 => COUT4,
-   COUT3 => COUT3,
-   COUT2 => COUT2,
-   COUT1 => COUT1,
-   COUT0 => COUT0,
-   FF_RX_D_0_0 => FF_RX_D_0_0,
-   FF_RX_D_0_1 => FF_RX_D_0_1,
-   FF_RX_D_0_2 => FF_RX_D_0_2,
-   FF_RX_D_0_3 => FF_RX_D_0_3,
-   FF_RX_D_0_4 => FF_RX_D_0_4,
-   FF_RX_D_0_5 => FF_RX_D_0_5,
-   FF_RX_D_0_6 => FF_RX_D_0_6,
-   FF_RX_D_0_7 => FF_RX_D_0_7,
-   FF_RX_D_0_8 => FF_RX_D_0_8,
-   FF_RX_D_0_9 => FF_RX_D_0_9,
-   FF_RX_D_0_10 => FF_RX_D_0_10,
-   FF_RX_D_0_11 => FF_RX_D_0_11,
-   FF_RX_D_0_12 => FF_RX_D_0_12,
-   FF_RX_D_0_13 => FF_RX_D_0_13,
-   FF_RX_D_0_14 => FF_RX_D_0_14,
-   FF_RX_D_0_15 => FF_RX_D_0_15,
-   FF_RX_D_0_16 => FF_RX_D_0_16,
-   FF_RX_D_0_17 => FF_RX_D_0_17,
-   FF_RX_D_0_18 => FF_RX_D_0_18,
-   FF_RX_D_0_19 => FF_RX_D_0_19,
-   FF_RX_D_0_20 => FF_RX_D_0_20,
-   FF_RX_D_0_21 => FF_RX_D_0_21,
-   FF_RX_D_0_22 => FF_RX_D_0_22,
-   FF_RX_D_0_23 => FF_RX_D_0_23,
-   FF_RX_D_1_0 => FF_RX_D_1_0,
-   FF_RX_D_1_1 => FF_RX_D_1_1,
-   FF_RX_D_1_2 => FF_RX_D_1_2,
-   FF_RX_D_1_3 => FF_RX_D_1_3,
-   FF_RX_D_1_4 => FF_RX_D_1_4,
-   FF_RX_D_1_5 => FF_RX_D_1_5,
-   FF_RX_D_1_6 => FF_RX_D_1_6,
-   FF_RX_D_1_7 => FF_RX_D_1_7,
-   FF_RX_D_1_8 => FF_RX_D_1_8,
-   FF_RX_D_1_9 => FF_RX_D_1_9,
-   FF_RX_D_1_10 => FF_RX_D_1_10,
-   FF_RX_D_1_11 => FF_RX_D_1_11,
-   FF_RX_D_1_12 => FF_RX_D_1_12,
-   FF_RX_D_1_13 => FF_RX_D_1_13,
-   FF_RX_D_1_14 => FF_RX_D_1_14,
-   FF_RX_D_1_15 => FF_RX_D_1_15,
-   FF_RX_D_1_16 => FF_RX_D_1_16,
-   FF_RX_D_1_17 => FF_RX_D_1_17,
-   FF_RX_D_1_18 => FF_RX_D_1_18,
-   FF_RX_D_1_19 => FF_RX_D_1_19,
-   FF_RX_D_1_20 => FF_RX_D_1_20,
-   FF_RX_D_1_21 => FF_RX_D_1_21,
-   FF_RX_D_1_22 => FF_RX_D_1_22,
-   FF_RX_D_1_23 => FF_RX_D_1_23,
-   FF_RX_D_2_0 => FF_RX_D_2_0,
-   FF_RX_D_2_1 => FF_RX_D_2_1,
-   FF_RX_D_2_2 => FF_RX_D_2_2,
-   FF_RX_D_2_3 => FF_RX_D_2_3,
-   FF_RX_D_2_4 => FF_RX_D_2_4,
-   FF_RX_D_2_5 => FF_RX_D_2_5,
-   FF_RX_D_2_6 => FF_RX_D_2_6,
-   FF_RX_D_2_7 => FF_RX_D_2_7,
-   FF_RX_D_2_8 => FF_RX_D_2_8,
-   FF_RX_D_2_9 => FF_RX_D_2_9,
-   FF_RX_D_2_10 => FF_RX_D_2_10,
-   FF_RX_D_2_11 => FF_RX_D_2_11,
-   FF_RX_D_2_12 => FF_RX_D_2_12,
-   FF_RX_D_2_13 => FF_RX_D_2_13,
-   FF_RX_D_2_14 => FF_RX_D_2_14,
-   FF_RX_D_2_15 => FF_RX_D_2_15,
-   FF_RX_D_2_16 => FF_RX_D_2_16,
-   FF_RX_D_2_17 => FF_RX_D_2_17,
-   FF_RX_D_2_18 => FF_RX_D_2_18,
-   FF_RX_D_2_19 => FF_RX_D_2_19,
-   FF_RX_D_2_20 => FF_RX_D_2_20,
-   FF_RX_D_2_21 => FF_RX_D_2_21,
-   FF_RX_D_2_22 => FF_RX_D_2_22,
-   FF_RX_D_2_23 => FF_RX_D_2_23,
-   FF_RX_D_3_0 => FF_RX_D_3_0,
-   FF_RX_D_3_1 => FF_RX_D_3_1,
-   FF_RX_D_3_2 => FF_RX_D_3_2,
-   FF_RX_D_3_3 => FF_RX_D_3_3,
-   FF_RX_D_3_4 => FF_RX_D_3_4,
-   FF_RX_D_3_5 => FF_RX_D_3_5,
-   FF_RX_D_3_6 => FF_RX_D_3_6,
-   FF_RX_D_3_7 => FF_RX_D_3_7,
-   FF_RX_D_3_8 => FF_RX_D_3_8,
-   FF_RX_D_3_9 => FF_RX_D_3_9,
-   FF_RX_D_3_10 => FF_RX_D_3_10,
-   FF_RX_D_3_11 => FF_RX_D_3_11,
-   FF_RX_D_3_12 => FF_RX_D_3_12,
-   FF_RX_D_3_13 => FF_RX_D_3_13,
-   FF_RX_D_3_14 => FF_RX_D_3_14,
-   FF_RX_D_3_15 => FF_RX_D_3_15,
-   FF_RX_D_3_16 => FF_RX_D_3_16,
-   FF_RX_D_3_17 => FF_RX_D_3_17,
-   FF_RX_D_3_18 => FF_RX_D_3_18,
-   FF_RX_D_3_19 => FF_RX_D_3_19,
-   FF_RX_D_3_20 => FF_RX_D_3_20,
-   FF_RX_D_3_21 => FF_RX_D_3_21,
-   FF_RX_D_3_22 => FF_RX_D_3_22,
-   FF_RX_D_3_23 => FF_RX_D_3_23,
-   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
-   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
-   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
-   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
-   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
-   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
-   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
-   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
-   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
-   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
-   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
-   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
-   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
-   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
-   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
-   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
-   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
-   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
-   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
-   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
-   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
-   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
-   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
-   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
-   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
-   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
-   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
-   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
-   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
-   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
-   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
-   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
-   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
-   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
-   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
-   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
-   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
-   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
-   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
-   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
-   FFS_PLOL => FFS_PLOL,
-   FFS_RLOL_0 => FFS_RLOL_0,
-   FFS_RLOL_1 => FFS_RLOL_1,
-   FFS_RLOL_2 => FFS_RLOL_2,
-   FFS_RLOL_3 => FFS_RLOL_3,
-   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
-   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
-   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
-   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
-   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
-   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
-   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
-   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
-   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
-   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
-   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
-   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
-   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
-   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
-   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
-   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
-   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
-   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
-   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
-   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
-   PCIE_RXVALID_0 => PCIE_RXVALID_0,
-   PCIE_RXVALID_1 => PCIE_RXVALID_1,
-   PCIE_RXVALID_2 => PCIE_RXVALID_2,
-   PCIE_RXVALID_3 => PCIE_RXVALID_3,
-   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
-   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
-   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
-   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
-   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
-   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
-   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
-   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
-   LDR_RX2CORE_0 => LDR_RX2CORE_0,
-   LDR_RX2CORE_1 => LDR_RX2CORE_1,
-   LDR_RX2CORE_2 => LDR_RX2CORE_2,
-   LDR_RX2CORE_3 => LDR_RX2CORE_3,
-   REFCK2CORE => REFCK2CORE,
-   SCIINT => SCIINT,
-   SCIRDATA0 => SCIRDATA0,
-   SCIRDATA1 => SCIRDATA1,
-   SCIRDATA2 => SCIRDATA2,
-   SCIRDATA3 => SCIRDATA3,
-   SCIRDATA4 => SCIRDATA4,
-   SCIRDATA5 => SCIRDATA5,
-   SCIRDATA6 => SCIRDATA6,
-   SCIRDATA7 => SCIRDATA7,
-   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
-   REFCLK_TO_NQ => REFCLK_TO_NQ
-   );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_sync_upstream is
-   GENERIC (USER_CONFIG_FILE    :  String := "serdes_sync_upstream.txt");
- port (
-------------------
--- CH0 --
--- CH1 --
--- CH2 --
--- CH3 --
-    hdinp_ch3, hdinn_ch3    :   in std_logic;
-    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
-    sci_sel_ch3    :   in std_logic;
-    txiclk_ch3    :   in std_logic;
-    rx_full_clk_ch3   :   out std_logic;
-    rx_half_clk_ch3   :   out std_logic;
-    tx_full_clk_ch3   :   out std_logic;
-    tx_half_clk_ch3   :   out std_logic;
-    fpga_rxrefclk_ch3    :   in std_logic;
-    txdata_ch3    :   in std_logic_vector (7 downto 0);
-    tx_k_ch3    :   in std_logic;
-    tx_force_disp_ch3    :   in std_logic;
-    tx_disp_sel_ch3    :   in std_logic;
-    rxdata_ch3   :   out std_logic_vector (7 downto 0);
-    rx_k_ch3   :   out std_logic;
-    rx_disp_err_ch3   :   out std_logic;
-    rx_cv_err_ch3   :   out std_logic;
-    rx_serdes_rst_ch3_c    :   in std_logic;
-    sb_felb_ch3_c    :   in std_logic;
-    sb_felb_rst_ch3_c    :   in std_logic;
-    tx_pcs_rst_ch3_c    :   in std_logic;
-    tx_pwrup_ch3_c    :   in std_logic;
-    rx_pcs_rst_ch3_c    :   in std_logic;
-    rx_pwrup_ch3_c    :   in std_logic;
-    rx_los_low_ch3_s   :   out std_logic;
-    lsm_status_ch3_s   :   out std_logic;
-    rx_cdr_lol_ch3_s   :   out std_logic;
-    tx_div2_mode_ch3_c   : in std_logic;
-    rx_div2_mode_ch3_c   : in std_logic;
----- Miscillaneous ports
-    sci_wrdata    :   in std_logic_vector (7 downto 0);
-    sci_addr    :   in std_logic_vector (5 downto 0);
-    sci_rddata   :   out std_logic_vector (7 downto 0);
-    sci_sel_quad    :   in std_logic;
-    sci_rd    :   in std_logic;
-    sci_wrn    :   in std_logic;
-    fpga_txrefclk  :   in std_logic;
-    tx_serdes_rst_c    :   in std_logic;
-    tx_pll_lol_qd_s   :   out std_logic;
-    rst_qd_c    :   in std_logic;
-    refclk2fpga   :   out std_logic;
-    serdes_rst_qd_c    :   in std_logic);
-
-end serdes_sync_upstream;
-
-
-architecture serdes_sync_upstream_arch of serdes_sync_upstream is
-
-component VLO
-port (
-   Z : out std_logic);
-end component;
-
-component VHI
-port (
-   Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
-  );
---synopsys translate_on
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-   attribute CONFIG_FILE: string;
-   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
-   attribute QUAD_MODE: string;
-   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
-   attribute PLL_SRC: string;
-   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH3_CDR_SRC: string;
-   attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_REFCK2CORE: string;
-   attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
-   attribute black_box_pad_pin: string;
-   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal    tx_full_clk_ch3_sig   :   std_logic;
-
-signal    refclk2fpga_sig  :   std_logic;
-signal    tx_pll_lol_qd_sig  :   std_logic;
-signal    rx_los_low_ch0_sig  :   std_logic;
-signal    rx_los_low_ch1_sig  :   std_logic;
-signal    rx_los_low_ch2_sig  :   std_logic;
-signal    rx_los_low_ch3_sig  :   std_logic;
-signal    rx_cdr_lol_ch0_sig  :   std_logic;
-signal    rx_cdr_lol_ch1_sig  :   std_logic;
-signal    rx_cdr_lol_ch2_sig  :   std_logic;
-signal    rx_cdr_lol_ch3_sig  :   std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
-  refclk2fpga <= refclk2fpga_sig;
-    rx_los_low_ch3_s <= rx_los_low_ch3_sig;
-    rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
-  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
-  tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
-  generic map (CONFIG_FILE => USER_CONFIG_FILE,
-               QUAD_MODE => "SINGLE",
-               CH3_CDR_SRC => "REFCLK_CORE",
-               PLL_SRC  => "REFCLK_CORE"
-  )
---synopsys translate_on
-port map  (
-  REFCLKP => fpsc_vlo,
-  REFCLKN => fpsc_vlo,
-
------ CH0 -----
-  HDOUTP0 => open,
-  HDOUTN0 => open,
-  HDINP0 => fpsc_vlo,
-  HDINN0 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
-  PCIE_RXPOLARITY_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_1 => fpsc_vlo,
-  PCIE_RXVALID_0 => open,
-  PCIE_PHYSTATUS_0 => open,
-  SCISELCH0 => fpsc_vlo,
-  SCIENCH0 => fpsc_vlo,
-  FF_RXI_CLK_0 => fpsc_vlo,
-  FF_TXI_CLK_0 => fpsc_vlo,
-  FF_EBRD_CLK_0 => fpsc_vlo,
-  FF_RX_F_CLK_0 => open,
-  FF_RX_H_CLK_0 => open,
-  FF_TX_F_CLK_0 => open,
-  FF_TX_H_CLK_0 => open,
-  FFC_CK_CORE_RX_0 => fpsc_vlo,
-  FF_TX_D_0_0 => fpsc_vlo,
-  FF_TX_D_0_1 => fpsc_vlo,
-  FF_TX_D_0_2 => fpsc_vlo,
-  FF_TX_D_0_3 => fpsc_vlo,
-  FF_TX_D_0_4 => fpsc_vlo,
-  FF_TX_D_0_5 => fpsc_vlo,
-  FF_TX_D_0_6 => fpsc_vlo,
-  FF_TX_D_0_7 => fpsc_vlo,
-  FF_TX_D_0_8 => fpsc_vlo,
-  FF_TX_D_0_9 => fpsc_vlo,
-  FF_TX_D_0_10 => fpsc_vlo,
-  FF_TX_D_0_11 => fpsc_vlo,
-  FF_TX_D_0_12 => fpsc_vlo,
-  FF_TX_D_0_13 => fpsc_vlo,
-  FF_TX_D_0_14 => fpsc_vlo,
-  FF_TX_D_0_15 => fpsc_vlo,
-  FF_TX_D_0_16 => fpsc_vlo,
-  FF_TX_D_0_17 => fpsc_vlo,
-  FF_TX_D_0_18 => fpsc_vlo,
-  FF_TX_D_0_19 => fpsc_vlo,
-  FF_TX_D_0_20 => fpsc_vlo,
-  FF_TX_D_0_21 => fpsc_vlo,
-  FF_TX_D_0_22 => fpsc_vlo,
-  FF_TX_D_0_23 => fpsc_vlo,
-  FF_RX_D_0_0 => open,
-  FF_RX_D_0_1 => open,
-  FF_RX_D_0_2 => open,
-  FF_RX_D_0_3 => open,
-  FF_RX_D_0_4 => open,
-  FF_RX_D_0_5 => open,
-  FF_RX_D_0_6 => open,
-  FF_RX_D_0_7 => open,
-  FF_RX_D_0_8 => open,
-  FF_RX_D_0_9 => open,
-  FF_RX_D_0_10 => open,
-  FF_RX_D_0_11 => open,
-  FF_RX_D_0_12 => open,
-  FF_RX_D_0_13 => open,
-  FF_RX_D_0_14 => open,
-  FF_RX_D_0_15 => open,
-  FF_RX_D_0_16 => open,
-  FF_RX_D_0_17 => open,
-  FF_RX_D_0_18 => open,
-  FF_RX_D_0_19 => open,
-  FF_RX_D_0_20 => open,
-  FF_RX_D_0_21 => open,
-  FF_RX_D_0_22 => open,
-  FF_RX_D_0_23 => open,
-
-  FFC_RRST_0 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_0 => fpsc_vlo,
-  FFC_PFIFO_CLR_0 => fpsc_vlo,
-  FFC_SB_INV_RX_0 => fpsc_vlo,
-  FFC_PCIE_CT_0 => fpsc_vlo,
-  FFC_PCI_DET_EN_0 => fpsc_vlo,
-  FFC_FB_LOOPBACK_0 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
-  FFC_EI_EN_0 => fpsc_vlo,
-  FFC_LANE_TX_RST_0 => fpsc_vlo,
-  FFC_TXPWDNB_0 => fpsc_vlo,
-  FFC_LANE_RX_RST_0 => fpsc_vlo,
-  FFC_RXPWDNB_0 => fpsc_vlo,
-  FFS_RLOS_LO_0 => open,
-  FFS_RLOS_HI_0 => open,
-  FFS_PCIE_CON_0 => open,
-  FFS_PCIE_DONE_0 => open,
-  FFS_LS_SYNC_STATUS_0 => open,
-  FFS_CC_OVERRUN_0 => open,
-  FFS_CC_UNDERRUN_0 => open,
-  FFS_SKP_ADDED_0 => open,
-  FFS_SKP_DELETED_0 => open,
-  FFS_RLOL_0 => open,
-  FFS_RXFBFIFO_ERROR_0 => open,
-  FFS_TXFBFIFO_ERROR_0 => open,
-  LDR_CORE2TX_0 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
-  LDR_RX2CORE_0 => open,
-  FFS_CDR_TRAIN_DONE_0 => open,
-  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
-  FFC_RATE_MODE_TX_0 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
-  FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
-  HDOUTP1 => open,
-  HDOUTN1 => open,
-  HDINP1 => fpsc_vlo,
-  HDINN1 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
-  PCIE_RXPOLARITY_1 => fpsc_vlo,
-  PCIE_POWERDOWN_1_0 => fpsc_vlo,
-  PCIE_POWERDOWN_1_1 => fpsc_vlo,
-  PCIE_RXVALID_1 => open,
-  PCIE_PHYSTATUS_1 => open,
-  SCISELCH1 => fpsc_vlo,
-  SCIENCH1 => fpsc_vlo,
-  FF_RXI_CLK_1 => fpsc_vlo,
-  FF_TXI_CLK_1 => fpsc_vlo,
-  FF_EBRD_CLK_1 => fpsc_vlo,
-  FF_RX_F_CLK_1 => open,
-  FF_RX_H_CLK_1 => open,
-  FF_TX_F_CLK_1 => open,
-  FF_TX_H_CLK_1 => open,
-  FFC_CK_CORE_RX_1 => fpsc_vlo,
-  FF_TX_D_1_0 => fpsc_vlo,
-  FF_TX_D_1_1 => fpsc_vlo,
-  FF_TX_D_1_2 => fpsc_vlo,
-  FF_TX_D_1_3 => fpsc_vlo,
-  FF_TX_D_1_4 => fpsc_vlo,
-  FF_TX_D_1_5 => fpsc_vlo,
-  FF_TX_D_1_6 => fpsc_vlo,
-  FF_TX_D_1_7 => fpsc_vlo,
-  FF_TX_D_1_8 => fpsc_vlo,
-  FF_TX_D_1_9 => fpsc_vlo,
-  FF_TX_D_1_10 => fpsc_vlo,
-  FF_TX_D_1_11 => fpsc_vlo,
-  FF_TX_D_1_12 => fpsc_vlo,
-  FF_TX_D_1_13 => fpsc_vlo,
-  FF_TX_D_1_14 => fpsc_vlo,
-  FF_TX_D_1_15 => fpsc_vlo,
-  FF_TX_D_1_16 => fpsc_vlo,
-  FF_TX_D_1_17 => fpsc_vlo,
-  FF_TX_D_1_18 => fpsc_vlo,
-  FF_TX_D_1_19 => fpsc_vlo,
-  FF_TX_D_1_20 => fpsc_vlo,
-  FF_TX_D_1_21 => fpsc_vlo,
-  FF_TX_D_1_22 => fpsc_vlo,
-  FF_TX_D_1_23 => fpsc_vlo,
-  FF_RX_D_1_0 => open,
-  FF_RX_D_1_1 => open,
-  FF_RX_D_1_2 => open,
-  FF_RX_D_1_3 => open,
-  FF_RX_D_1_4 => open,
-  FF_RX_D_1_5 => open,
-  FF_RX_D_1_6 => open,
-  FF_RX_D_1_7 => open,
-  FF_RX_D_1_8 => open,
-  FF_RX_D_1_9 => open,
-  FF_RX_D_1_10 => open,
-  FF_RX_D_1_11 => open,
-  FF_RX_D_1_12 => open,
-  FF_RX_D_1_13 => open,
-  FF_RX_D_1_14 => open,
-  FF_RX_D_1_15 => open,
-  FF_RX_D_1_16 => open,
-  FF_RX_D_1_17 => open,
-  FF_RX_D_1_18 => open,
-  FF_RX_D_1_19 => open,
-  FF_RX_D_1_20 => open,
-  FF_RX_D_1_21 => open,
-  FF_RX_D_1_22 => open,
-  FF_RX_D_1_23 => open,
-
-  FFC_RRST_1 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_1 => fpsc_vlo,
-  FFC_PFIFO_CLR_1 => fpsc_vlo,
-  FFC_SB_INV_RX_1 => fpsc_vlo,
-  FFC_PCIE_CT_1 => fpsc_vlo,
-  FFC_PCI_DET_EN_1 => fpsc_vlo,
-  FFC_FB_LOOPBACK_1 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
-  FFC_EI_EN_1 => fpsc_vlo,
-  FFC_LANE_TX_RST_1 => fpsc_vlo,
-  FFC_TXPWDNB_1 => fpsc_vlo,
-  FFC_LANE_RX_RST_1 => fpsc_vlo,
-  FFC_RXPWDNB_1 => fpsc_vlo,
-  FFS_RLOS_LO_1 => open,
-  FFS_RLOS_HI_1 => open,
-  FFS_PCIE_CON_1 => open,
-  FFS_PCIE_DONE_1 => open,
-  FFS_LS_SYNC_STATUS_1 => open,
-  FFS_CC_OVERRUN_1 => open,
-  FFS_CC_UNDERRUN_1 => open,
-  FFS_SKP_ADDED_1 => open,
-  FFS_SKP_DELETED_1 => open,
-  FFS_RLOL_1 => open,
-  FFS_RXFBFIFO_ERROR_1 => open,
-  FFS_TXFBFIFO_ERROR_1 => open,
-  LDR_CORE2TX_1 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
-  LDR_RX2CORE_1 => open,
-  FFS_CDR_TRAIN_DONE_1 => open,
-  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
-  FFC_RATE_MODE_TX_1 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
-  FFC_RATE_MODE_RX_1 => fpsc_vlo,
-
------ CH2 -----
-  HDOUTP2 => open,
-  HDOUTN2 => open,
-  HDINP2 => fpsc_vlo,
-  HDINN2 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
-  PCIE_RXPOLARITY_2 => fpsc_vlo,
-  PCIE_POWERDOWN_2_0 => fpsc_vlo,
-  PCIE_POWERDOWN_2_1 => fpsc_vlo,
-  PCIE_RXVALID_2 => open,
-  PCIE_PHYSTATUS_2 => open,
-  SCISELCH2 => fpsc_vlo,
-  SCIENCH2 => fpsc_vlo,
-  FF_RXI_CLK_2 => fpsc_vlo,
-  FF_TXI_CLK_2 => fpsc_vlo,
-  FF_EBRD_CLK_2 => fpsc_vlo,
-  FF_RX_F_CLK_2 => open,
-  FF_RX_H_CLK_2 => open,
-  FF_TX_F_CLK_2 => open,
-  FF_TX_H_CLK_2 => open,
-  FFC_CK_CORE_RX_2 => fpsc_vlo,
-  FF_TX_D_2_0 => fpsc_vlo,
-  FF_TX_D_2_1 => fpsc_vlo,
-  FF_TX_D_2_2 => fpsc_vlo,
-  FF_TX_D_2_3 => fpsc_vlo,
-  FF_TX_D_2_4 => fpsc_vlo,
-  FF_TX_D_2_5 => fpsc_vlo,
-  FF_TX_D_2_6 => fpsc_vlo,
-  FF_TX_D_2_7 => fpsc_vlo,
-  FF_TX_D_2_8 => fpsc_vlo,
-  FF_TX_D_2_9 => fpsc_vlo,
-  FF_TX_D_2_10 => fpsc_vlo,
-  FF_TX_D_2_11 => fpsc_vlo,
-  FF_TX_D_2_12 => fpsc_vlo,
-  FF_TX_D_2_13 => fpsc_vlo,
-  FF_TX_D_2_14 => fpsc_vlo,
-  FF_TX_D_2_15 => fpsc_vlo,
-  FF_TX_D_2_16 => fpsc_vlo,
-  FF_TX_D_2_17 => fpsc_vlo,
-  FF_TX_D_2_18 => fpsc_vlo,
-  FF_TX_D_2_19 => fpsc_vlo,
-  FF_TX_D_2_20 => fpsc_vlo,
-  FF_TX_D_2_21 => fpsc_vlo,
-  FF_TX_D_2_22 => fpsc_vlo,
-  FF_TX_D_2_23 => fpsc_vlo,
-  FF_RX_D_2_0 => open,
-  FF_RX_D_2_1 => open,
-  FF_RX_D_2_2 => open,
-  FF_RX_D_2_3 => open,
-  FF_RX_D_2_4 => open,
-  FF_RX_D_2_5 => open,
-  FF_RX_D_2_6 => open,
-  FF_RX_D_2_7 => open,
-  FF_RX_D_2_8 => open,
-  FF_RX_D_2_9 => open,
-  FF_RX_D_2_10 => open,
-  FF_RX_D_2_11 => open,
-  FF_RX_D_2_12 => open,
-  FF_RX_D_2_13 => open,
-  FF_RX_D_2_14 => open,
-  FF_RX_D_2_15 => open,
-  FF_RX_D_2_16 => open,
-  FF_RX_D_2_17 => open,
-  FF_RX_D_2_18 => open,
-  FF_RX_D_2_19 => open,
-  FF_RX_D_2_20 => open,
-  FF_RX_D_2_21 => open,
-  FF_RX_D_2_22 => open,
-  FF_RX_D_2_23 => open,
-
-  FFC_RRST_2 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_2 => fpsc_vlo,
-  FFC_PFIFO_CLR_2 => fpsc_vlo,
-  FFC_SB_INV_RX_2 => fpsc_vlo,
-  FFC_PCIE_CT_2 => fpsc_vlo,
-  FFC_PCI_DET_EN_2 => fpsc_vlo,
-  FFC_FB_LOOPBACK_2 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
-  FFC_EI_EN_2 => fpsc_vlo,
-  FFC_LANE_TX_RST_2 => fpsc_vlo,
-  FFC_TXPWDNB_2 => fpsc_vlo,
-  FFC_LANE_RX_RST_2 => fpsc_vlo,
-  FFC_RXPWDNB_2 => fpsc_vlo,
-  FFS_RLOS_LO_2 => open,
-  FFS_RLOS_HI_2 => open,
-  FFS_PCIE_CON_2 => open,
-  FFS_PCIE_DONE_2 => open,
-  FFS_LS_SYNC_STATUS_2 => open,
-  FFS_CC_OVERRUN_2 => open,
-  FFS_CC_UNDERRUN_2 => open,
-  FFS_SKP_ADDED_2 => open,
-  FFS_SKP_DELETED_2 => open,
-  FFS_RLOL_2 => open,
-  FFS_RXFBFIFO_ERROR_2 => open,
-  FFS_TXFBFIFO_ERROR_2 => open,
-  LDR_CORE2TX_2 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
-  LDR_RX2CORE_2 => open,
-  FFS_CDR_TRAIN_DONE_2 => open,
-  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
-  FFC_RATE_MODE_TX_2 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
-  FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
-  HDOUTP3 => hdoutp_ch3,
-  HDOUTN3 => hdoutn_ch3,
-  HDINP3 => hdinp_ch3,
-  HDINN3 => hdinn_ch3,
-  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
-  PCIE_RXPOLARITY_3 => fpsc_vlo,
-  PCIE_POWERDOWN_3_0 => fpsc_vlo,
-  PCIE_POWERDOWN_3_1 => fpsc_vlo,
-  PCIE_RXVALID_3 => open,
-  PCIE_PHYSTATUS_3 => open,
-  SCISELCH3 => sci_sel_ch3,
-  SCIENCH3 => fpsc_vhi,
-  FF_RXI_CLK_3 => fpsc_vlo,
-  FF_TXI_CLK_3 => txiclk_ch3,
-  FF_EBRD_CLK_3 => fpsc_vlo,
-  FF_RX_F_CLK_3 => rx_full_clk_ch3,
-  FF_RX_H_CLK_3 => rx_half_clk_ch3,
-  FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
-  FF_TX_H_CLK_3 => tx_half_clk_ch3,
-  FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
-  FF_TX_D_3_0 => txdata_ch3(0),
-  FF_TX_D_3_1 => txdata_ch3(1),
-  FF_TX_D_3_2 => txdata_ch3(2),
-  FF_TX_D_3_3 => txdata_ch3(3),
-  FF_TX_D_3_4 => txdata_ch3(4),
-  FF_TX_D_3_5 => txdata_ch3(5),
-  FF_TX_D_3_6 => txdata_ch3(6),
-  FF_TX_D_3_7 => txdata_ch3(7),
-  FF_TX_D_3_8 => tx_k_ch3,
-  FF_TX_D_3_9 => tx_force_disp_ch3,
-  FF_TX_D_3_10 => tx_disp_sel_ch3,
-  FF_TX_D_3_11 => fpsc_vlo,
-  FF_TX_D_3_12 => fpsc_vlo,
-  FF_TX_D_3_13 => fpsc_vlo,
-  FF_TX_D_3_14 => fpsc_vlo,
-  FF_TX_D_3_15 => fpsc_vlo,
-  FF_TX_D_3_16 => fpsc_vlo,
-  FF_TX_D_3_17 => fpsc_vlo,
-  FF_TX_D_3_18 => fpsc_vlo,
-  FF_TX_D_3_19 => fpsc_vlo,
-  FF_TX_D_3_20 => fpsc_vlo,
-  FF_TX_D_3_21 => fpsc_vlo,
-  FF_TX_D_3_22 => fpsc_vlo,
-  FF_TX_D_3_23 => fpsc_vlo,
-  FF_RX_D_3_0 => rxdata_ch3(0),
-  FF_RX_D_3_1 => rxdata_ch3(1),
-  FF_RX_D_3_2 => rxdata_ch3(2),
-  FF_RX_D_3_3 => rxdata_ch3(3),
-  FF_RX_D_3_4 => rxdata_ch3(4),
-  FF_RX_D_3_5 => rxdata_ch3(5),
-  FF_RX_D_3_6 => rxdata_ch3(6),
-  FF_RX_D_3_7 => rxdata_ch3(7),
-  FF_RX_D_3_8 => rx_k_ch3,
-  FF_RX_D_3_9 => rx_disp_err_ch3,
-  FF_RX_D_3_10 => rx_cv_err_ch3,
-  FF_RX_D_3_11 => open,
-  FF_RX_D_3_12 => open,
-  FF_RX_D_3_13 => open,
-  FF_RX_D_3_14 => open,
-  FF_RX_D_3_15 => open,
-  FF_RX_D_3_16 => open,
-  FF_RX_D_3_17 => open,
-  FF_RX_D_3_18 => open,
-  FF_RX_D_3_19 => open,
-  FF_RX_D_3_20 => open,
-  FF_RX_D_3_21 => open,
-  FF_RX_D_3_22 => open,
-  FF_RX_D_3_23 => open,
-
-  FFC_RRST_3 => rx_serdes_rst_ch3_c,
-  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
-  FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
-  FFC_SB_INV_RX_3 => fpsc_vlo,
-  FFC_PCIE_CT_3 => fpsc_vlo,
-  FFC_PCI_DET_EN_3 => fpsc_vlo,
-  FFC_FB_LOOPBACK_3 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
-  FFC_EI_EN_3 => fpsc_vlo,
-  FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
-  FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
-  FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
-  FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
-  FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
-  FFS_RLOS_HI_3 => open,
-  FFS_PCIE_CON_3 => open,
-  FFS_PCIE_DONE_3 => open,
-  FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
-  FFS_CC_OVERRUN_3 => open,
-  FFS_CC_UNDERRUN_3 => open,
-  FFS_SKP_ADDED_3 => open,
-  FFS_SKP_DELETED_3 => open,
-  FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
-  FFS_RXFBFIFO_ERROR_3 => open,
-  FFS_TXFBFIFO_ERROR_3 => open,
-  LDR_CORE2TX_3 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
-  LDR_RX2CORE_3 => open,
-  FFS_CDR_TRAIN_DONE_3 => open,
-  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
-  FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
-  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
-  FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
-
------ Auxilliary ----
-  SCIWDATA7 => sci_wrdata(7),
-  SCIWDATA6 => sci_wrdata(6),
-  SCIWDATA5 => sci_wrdata(5),
-  SCIWDATA4 => sci_wrdata(4),
-  SCIWDATA3 => sci_wrdata(3),
-  SCIWDATA2 => sci_wrdata(2),
-  SCIWDATA1 => sci_wrdata(1),
-  SCIWDATA0 => sci_wrdata(0),
-  SCIADDR5 => sci_addr(5),
-  SCIADDR4 => sci_addr(4),
-  SCIADDR3 => sci_addr(3),
-  SCIADDR2 => sci_addr(2),
-  SCIADDR1 => sci_addr(1),
-  SCIADDR0 => sci_addr(0),
-  SCIRDATA7 => sci_rddata(7),
-  SCIRDATA6 => sci_rddata(6),
-  SCIRDATA5 => sci_rddata(5),
-  SCIRDATA4 => sci_rddata(4),
-  SCIRDATA3 => sci_rddata(3),
-  SCIRDATA2 => sci_rddata(2),
-  SCIRDATA1 => sci_rddata(1),
-  SCIRDATA0 => sci_rddata(0),
-  SCIENAUX => fpsc_vhi,
-  SCISELAUX => sci_sel_quad,
-  SCIRD => sci_rd,
-  SCIWSTN => sci_wrn,
-  CYAWSTN => fpsc_vlo,
-  SCIINT => open,
-  FFC_CK_CORE_TX => fpga_txrefclk,
-  FFC_MACRO_RST => serdes_rst_qd_c,
-  FFC_QUAD_RST => rst_qd_c,
-  FFC_TRST => tx_serdes_rst_c,
-  FFS_PLOL => tx_pll_lol_qd_sig,
-  FFC_SYNC_TOGGLE => fpsc_vlo,
-  REFCK2CORE => refclk2fpga_sig,
-  CIN0 => fpsc_vlo,
-  CIN1 => fpsc_vlo,
-  CIN2 => fpsc_vlo,
-  CIN3 => fpsc_vlo,
-  CIN4 => fpsc_vlo,
-  CIN5 => fpsc_vlo,
-  CIN6 => fpsc_vlo,
-  CIN7 => fpsc_vlo,
-  CIN8 => fpsc_vlo,
-  CIN9 => fpsc_vlo,
-  CIN10 => fpsc_vlo,
-  CIN11 => fpsc_vlo,
-  COUT0 => open,
-  COUT1 => open,
-  COUT2 => open,
-  COUT3 => open,
-  COUT4 => open,
-  COUT5 => open,
-  COUT6 => open,
-  COUT7 => open,
-  COUT8 => open,
-  COUT9 => open,
-  COUT10 => open,
-  COUT11 => open,
-  COUT12 => open,
-  COUT13 => open,
-  COUT14 => open,
-  COUT15 => open,
-  COUT16 => open,
-  COUT17 => open,
-  COUT18 => open,
-  COUT19 => open,
-  REFCLK_FROM_NQ => refclk_from_nq,
-  REFCLK_TO_NQ => open);
-
-                                                                                              
-                                                                                              
-                                                                                              
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
-   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
-   IF (open_status = name_error) THEN
-      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
-      severity ERROR;
-   END IF;
-   wait;
-END PROCESS;
---synopsys translate_on
-end serdes_sync_upstream_arch ;
diff --git a/code/ip/serdes_sync_source_downstream.ipx b/code/ip/serdes_sync_source_downstream.ipx
deleted file mode 100644
index f75e480..0000000
--- a/code/ip/serdes_sync_source_downstream.ipx
+++ /dev/null
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_source_downstream" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 03 02 17:24:32.835" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-		<File name="serdes_sync_source_downstream.lpc" type="lpc" modified="2015 03 02 17:24:29.000"/>
-		<File name="serdes_sync_source_downstream.pp" type="pp" modified="2015 03 02 17:24:29.000"/>
-		<File name="serdes_sync_source_downstream.sym" type="sym" modified="2015 03 02 17:24:30.000"/>
-		<File name="serdes_sync_source_downstream.tft" type="tft" modified="2015 03 02 17:24:29.000"/>
-		<File name="serdes_sync_source_downstream.txt" type="pcs_module" modified="2015 03 02 17:24:29.000"/>
-		<File name="serdes_sync_source_downstream.vhd" type="top_level_vhdl" modified="2015 03 02 17:24:29.000"/>
-  </Package>
-</DiamondModule>
diff --git a/code/ip/serdes_sync_source_downstream.lpc b/code/ip/serdes_sync_source_downstream.lpc
deleted file mode 100644
index fa9375f..0000000
--- a/code/ip/serdes_sync_source_downstream.lpc
+++ /dev/null
@@ -1,258 +0,0 @@
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.2
-ModuleName=serdes_sync_source_downstream
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=03/02/2015
-Time=17:24:29
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=RXTX
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=DISABLED
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=G8B10B
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=DISABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
-_tx_ficlk_rate0=200
-_tx_ficlk_rate1=200
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=2.5
-_rx_protocol0=G8B10B
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=200
-_rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=250.0
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
-_rx_ficlk_rate0=200
-_rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=250.0
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=AC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=00
-_k02=00
-_k03=00
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00000000
-_byten02=00000000
-_byten03=00000000
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_sync_source_downstream.pp=pp
-serdes_sync_source_downstream.tft=tft
-serdes_sync_source_downstream.txt=pcs_module
-serdes_sync_source_downstream.sym=sym
diff --git a/code/ip/serdes_sync_source_downstream.txt b/code/ip/serdes_sync_source_downstream.txt
deleted file mode 100644
index cf095d4..0000000
--- a/code/ip/serdes_sync_source_downstream.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL            "G8B10B"
-CH0_MODE                "RXTX"
-CH1_MODE                "DISABLED"
-CH2_MODE                "DISABLED"
-CH3_MODE                "DISABLED"
-CH0_CDR_SRC       "REFCLK_CORE"
-PLL_SRC                 "REFCLK_CORE"
-TX_DATARATE_RANGE       "MEDHIGH"
-CH0_RX_DATARATE_RANGE   "MEDHIGH"
-REFCK_MULT              "10X"
-#REFCLK_RATE            200
-CH0_RX_DATA_RATE        "FULL"
-CH0_TX_DATA_RATE        "FULL"
-CH0_TX_DATA_WIDTH       "8"
-CH0_RX_DATA_WIDTH        "8"
-CH0_TX_FIFO       "DISABLED"
-CH0_RX_FIFO        "ENABLED"
-CH0_TDRV      "0"
-#CH0_TX_FICLK_RATE      200
-#CH0_RXREFCLK_RATE        "200"
-#CH0_RX_FICLK_RATE      200
-CH0_TX_PRE              "DISABLED"
-CH0_RTERM_TX            "50"
-CH0_RX_EQ               "DISABLED"
-CH0_RTERM_RX            "50"
-CH0_RX_DCC              "DC"
-CH0_LOS_THRESHOLD_LO       "2"
-PLL_TERM                "50"
-PLL_DCC                 "AC"
-PLL_LOL_SET             "0"
-CH0_TX_SB               "DISABLED"
-CH0_RX_SB               "DISABLED"
-CH0_TX_8B10B            "ENABLED"
-CH0_RX_8B10B            "ENABLED"
-CH0_COMMA_A             "1100000101"
-CH0_COMMA_B             "0011111010"
-CH0_COMMA_M             "1111111100"
-CH0_RXWA                "ENABLED"
-CH0_ILSM                "ENABLED"
-CH0_CTC                 "DISABLED"
-CH0_CC_MATCH4           "0100011100"
-CH0_CC_MATCH_MODE       "1"
-CH0_CC_MIN_IPG          "3"
-CCHMARK                 "9"
-CCLMARK                 "7"
-CH0_SSLB                "DISABLED"
-CH0_SPLBPORTS           "DISABLED"
-CH0_PCSLBPORTS          "DISABLED"
-INT_ALL                 "DISABLED"
-QD_REFCK2CORE           "ENABLED"
-
-
diff --git a/code/ip/serdes_sync_source_downstream.vhd b/code/ip/serdes_sync_source_downstream.vhd
deleted file mode 100644
index 0c3024f..0000000
--- a/code/ip/serdes_sync_source_downstream.vhd
+++ /dev/null
@@ -1,2702 +0,0 @@
-
-                                                                                                         
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
---  CONFIG_FILE : String  := "serdes_sync_source_downstream.txt";
---  QUAD_MODE : String := "SINGLE";
---  CH0_CDR_SRC   : String := "REFCLK_CORE";
---  CH1_CDR_SRC   : String := "REFCLK_EXT";
---  CH2_CDR_SRC   : String := "REFCLK_EXT";
---  CH3_CDR_SRC   : String := "REFCLK_EXT";
---  PLL_SRC   : String := "REFCLK_CORE"
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String;
-  CH1_CDR_SRC   : String;
-  CH2_CDR_SRC   : String;
-  CH3_CDR_SRC   : String;
-  PLL_SRC   : String
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
-  CONFIG_FILE => CONFIG_FILE,
-  QUAD_MODE => QUAD_MODE,
-  CH0_CDR_SRC => CH0_CDR_SRC,
-  CH1_CDR_SRC => CH1_CDR_SRC,
-  CH2_CDR_SRC => CH2_CDR_SRC,
-  CH3_CDR_SRC => CH3_CDR_SRC,
-  PLL_SRC => PLL_SRC
-  )
-port map (
-   HDINN0 => HDINN0,
-   HDINN1 => HDINN1,
-   HDINN2 => HDINN2,
-   HDINN3 => HDINN3,
-   HDINP0 => HDINP0,
-   HDINP1 => HDINP1,
-   HDINP2 => HDINP2,
-   HDINP3 => HDINP3,
-   REFCLKN => REFCLKN,
-   REFCLKP => REFCLKP,
-   CIN11 => CIN11,
-   CIN10 => CIN10,
-   CIN9 => CIN9,
-   CIN8 => CIN8,
-   CIN7 => CIN7,
-   CIN6 => CIN6,
-   CIN5 => CIN5,
-   CIN4 => CIN4,
-   CIN3 => CIN3,
-   CIN2 => CIN2,
-   CIN1 => CIN1,
-   CIN0 => CIN0,
-   CYAWSTN => CYAWSTN,
-   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
-   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
-   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
-   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
-   FF_RXI_CLK_3 => FF_RXI_CLK_3,
-   FF_RXI_CLK_2 => FF_RXI_CLK_2,
-   FF_RXI_CLK_1 => FF_RXI_CLK_1,
-   FF_RXI_CLK_0 => FF_RXI_CLK_0,
-   FF_TX_D_0_0 => FF_TX_D_0_0,
-   FF_TX_D_0_1 => FF_TX_D_0_1,
-   FF_TX_D_0_2 => FF_TX_D_0_2,
-   FF_TX_D_0_3 => FF_TX_D_0_3,
-   FF_TX_D_0_4 => FF_TX_D_0_4,
-   FF_TX_D_0_5 => FF_TX_D_0_5,
-   FF_TX_D_0_6 => FF_TX_D_0_6,
-   FF_TX_D_0_7 => FF_TX_D_0_7,
-   FF_TX_D_0_8 => FF_TX_D_0_8,
-   FF_TX_D_0_9 => FF_TX_D_0_9,
-   FF_TX_D_0_10 => FF_TX_D_0_10,
-   FF_TX_D_0_11 => FF_TX_D_0_11,
-   FF_TX_D_0_12 => FF_TX_D_0_12,
-   FF_TX_D_0_13 => FF_TX_D_0_13,
-   FF_TX_D_0_14 => FF_TX_D_0_14,
-   FF_TX_D_0_15 => FF_TX_D_0_15,
-   FF_TX_D_0_16 => FF_TX_D_0_16,
-   FF_TX_D_0_17 => FF_TX_D_0_17,
-   FF_TX_D_0_18 => FF_TX_D_0_18,
-   FF_TX_D_0_19 => FF_TX_D_0_19,
-   FF_TX_D_0_20 => FF_TX_D_0_20,
-   FF_TX_D_0_21 => FF_TX_D_0_21,
-   FF_TX_D_0_22 => FF_TX_D_0_22,
-   FF_TX_D_0_23 => FF_TX_D_0_23,
-   FF_TX_D_1_0 => FF_TX_D_1_0,
-   FF_TX_D_1_1 => FF_TX_D_1_1,
-   FF_TX_D_1_2 => FF_TX_D_1_2,
-   FF_TX_D_1_3 => FF_TX_D_1_3,
-   FF_TX_D_1_4 => FF_TX_D_1_4,
-   FF_TX_D_1_5 => FF_TX_D_1_5,
-   FF_TX_D_1_6 => FF_TX_D_1_6,
-   FF_TX_D_1_7 => FF_TX_D_1_7,
-   FF_TX_D_1_8 => FF_TX_D_1_8,
-   FF_TX_D_1_9 => FF_TX_D_1_9,
-   FF_TX_D_1_10 => FF_TX_D_1_10,
-   FF_TX_D_1_11 => FF_TX_D_1_11,
-   FF_TX_D_1_12 => FF_TX_D_1_12,
-   FF_TX_D_1_13 => FF_TX_D_1_13,
-   FF_TX_D_1_14 => FF_TX_D_1_14,
-   FF_TX_D_1_15 => FF_TX_D_1_15,
-   FF_TX_D_1_16 => FF_TX_D_1_16,
-   FF_TX_D_1_17 => FF_TX_D_1_17,
-   FF_TX_D_1_18 => FF_TX_D_1_18,
-   FF_TX_D_1_19 => FF_TX_D_1_19,
-   FF_TX_D_1_20 => FF_TX_D_1_20,
-   FF_TX_D_1_21 => FF_TX_D_1_21,
-   FF_TX_D_1_22 => FF_TX_D_1_22,
-   FF_TX_D_1_23 => FF_TX_D_1_23,
-   FF_TX_D_2_0 => FF_TX_D_2_0,
-   FF_TX_D_2_1 => FF_TX_D_2_1,
-   FF_TX_D_2_2 => FF_TX_D_2_2,
-   FF_TX_D_2_3 => FF_TX_D_2_3,
-   FF_TX_D_2_4 => FF_TX_D_2_4,
-   FF_TX_D_2_5 => FF_TX_D_2_5,
-   FF_TX_D_2_6 => FF_TX_D_2_6,
-   FF_TX_D_2_7 => FF_TX_D_2_7,
-   FF_TX_D_2_8 => FF_TX_D_2_8,
-   FF_TX_D_2_9 => FF_TX_D_2_9,
-   FF_TX_D_2_10 => FF_TX_D_2_10,
-   FF_TX_D_2_11 => FF_TX_D_2_11,
-   FF_TX_D_2_12 => FF_TX_D_2_12,
-   FF_TX_D_2_13 => FF_TX_D_2_13,
-   FF_TX_D_2_14 => FF_TX_D_2_14,
-   FF_TX_D_2_15 => FF_TX_D_2_15,
-   FF_TX_D_2_16 => FF_TX_D_2_16,
-   FF_TX_D_2_17 => FF_TX_D_2_17,
-   FF_TX_D_2_18 => FF_TX_D_2_18,
-   FF_TX_D_2_19 => FF_TX_D_2_19,
-   FF_TX_D_2_20 => FF_TX_D_2_20,
-   FF_TX_D_2_21 => FF_TX_D_2_21,
-   FF_TX_D_2_22 => FF_TX_D_2_22,
-   FF_TX_D_2_23 => FF_TX_D_2_23,
-   FF_TX_D_3_0 => FF_TX_D_3_0,
-   FF_TX_D_3_1 => FF_TX_D_3_1,
-   FF_TX_D_3_2 => FF_TX_D_3_2,
-   FF_TX_D_3_3 => FF_TX_D_3_3,
-   FF_TX_D_3_4 => FF_TX_D_3_4,
-   FF_TX_D_3_5 => FF_TX_D_3_5,
-   FF_TX_D_3_6 => FF_TX_D_3_6,
-   FF_TX_D_3_7 => FF_TX_D_3_7,
-   FF_TX_D_3_8 => FF_TX_D_3_8,
-   FF_TX_D_3_9 => FF_TX_D_3_9,
-   FF_TX_D_3_10 => FF_TX_D_3_10,
-   FF_TX_D_3_11 => FF_TX_D_3_11,
-   FF_TX_D_3_12 => FF_TX_D_3_12,
-   FF_TX_D_3_13 => FF_TX_D_3_13,
-   FF_TX_D_3_14 => FF_TX_D_3_14,
-   FF_TX_D_3_15 => FF_TX_D_3_15,
-   FF_TX_D_3_16 => FF_TX_D_3_16,
-   FF_TX_D_3_17 => FF_TX_D_3_17,
-   FF_TX_D_3_18 => FF_TX_D_3_18,
-   FF_TX_D_3_19 => FF_TX_D_3_19,
-   FF_TX_D_3_20 => FF_TX_D_3_20,
-   FF_TX_D_3_21 => FF_TX_D_3_21,
-   FF_TX_D_3_22 => FF_TX_D_3_22,
-   FF_TX_D_3_23 => FF_TX_D_3_23,
-   FF_TXI_CLK_0 => FF_TXI_CLK_0,
-   FF_TXI_CLK_1 => FF_TXI_CLK_1,
-   FF_TXI_CLK_2 => FF_TXI_CLK_2,
-   FF_TXI_CLK_3 => FF_TXI_CLK_3,
-   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
-   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
-   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
-   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
-   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
-   FFC_EI_EN_0 => FFC_EI_EN_0,
-   FFC_EI_EN_1 => FFC_EI_EN_1,
-   FFC_EI_EN_2 => FFC_EI_EN_2,
-   FFC_EI_EN_3 => FFC_EI_EN_3,
-   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
-   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
-   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
-   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
-   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
-   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
-   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
-   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
-   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
-   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
-   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
-   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
-   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
-   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
-   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
-   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
-   FFC_MACRO_RST => FFC_MACRO_RST,
-   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
-   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
-   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
-   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
-   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
-   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
-   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
-   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
-   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
-   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
-   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
-   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
-   FFC_QUAD_RST => FFC_QUAD_RST,
-   FFC_RRST_0 => FFC_RRST_0,
-   FFC_RRST_1 => FFC_RRST_1,
-   FFC_RRST_2 => FFC_RRST_2,
-   FFC_RRST_3 => FFC_RRST_3,
-   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
-   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
-   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
-   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
-   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
-   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
-   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
-   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
-   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
-   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
-   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
-   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
-   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
-   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
-   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
-   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
-   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
-   FFC_TRST => FFC_TRST,
-   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
-   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
-   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
-   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
-   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
-   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
-   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
-   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
-   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
-   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
-   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
-   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
-   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
-   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
-   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
-   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
-   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
-   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
-   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
-   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
-   LDR_CORE2TX_0 => LDR_CORE2TX_0,
-   LDR_CORE2TX_1 => LDR_CORE2TX_1,
-   LDR_CORE2TX_2 => LDR_CORE2TX_2,
-   LDR_CORE2TX_3 => LDR_CORE2TX_3,
-   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
-   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
-   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
-   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
-   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
-   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
-   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
-   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
-   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
-   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
-   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
-   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
-   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
-   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
-   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
-   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
-   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
-   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
-   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
-   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
-   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
-   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
-   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
-   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
-   SCIADDR0 => SCIADDR0,
-   SCIADDR1 => SCIADDR1,
-   SCIADDR2 => SCIADDR2,
-   SCIADDR3 => SCIADDR3,
-   SCIADDR4 => SCIADDR4,
-   SCIADDR5 => SCIADDR5,
-   SCIENAUX => SCIENAUX,
-   SCIENCH0 => SCIENCH0,
-   SCIENCH1 => SCIENCH1,
-   SCIENCH2 => SCIENCH2,
-   SCIENCH3 => SCIENCH3,
-   SCIRD => SCIRD,
-   SCISELAUX => SCISELAUX,
-   SCISELCH0 => SCISELCH0,
-   SCISELCH1 => SCISELCH1,
-   SCISELCH2 => SCISELCH2,
-   SCISELCH3 => SCISELCH3,
-   SCIWDATA0 => SCIWDATA0,
-   SCIWDATA1 => SCIWDATA1,
-   SCIWDATA2 => SCIWDATA2,
-   SCIWDATA3 => SCIWDATA3,
-   SCIWDATA4 => SCIWDATA4,
-   SCIWDATA5 => SCIWDATA5,
-   SCIWDATA6 => SCIWDATA6,
-   SCIWDATA7 => SCIWDATA7,
-   SCIWSTN => SCIWSTN,
-   HDOUTN0 => HDOUTN0,
-   HDOUTN1 => HDOUTN1,
-   HDOUTN2 => HDOUTN2,
-   HDOUTN3 => HDOUTN3,
-   HDOUTP0 => HDOUTP0,
-   HDOUTP1 => HDOUTP1,
-   HDOUTP2 => HDOUTP2,
-   HDOUTP3 => HDOUTP3,
-   COUT19 => COUT19,
-   COUT18 => COUT18,
-   COUT17 => COUT17,
-   COUT16 => COUT16,
-   COUT15 => COUT15,
-   COUT14 => COUT14,
-   COUT13 => COUT13,
-   COUT12 => COUT12,
-   COUT11 => COUT11,
-   COUT10 => COUT10,
-   COUT9 => COUT9,
-   COUT8 => COUT8,
-   COUT7 => COUT7,
-   COUT6 => COUT6,
-   COUT5 => COUT5,
-   COUT4 => COUT4,
-   COUT3 => COUT3,
-   COUT2 => COUT2,
-   COUT1 => COUT1,
-   COUT0 => COUT0,
-   FF_RX_D_0_0 => FF_RX_D_0_0,
-   FF_RX_D_0_1 => FF_RX_D_0_1,
-   FF_RX_D_0_2 => FF_RX_D_0_2,
-   FF_RX_D_0_3 => FF_RX_D_0_3,
-   FF_RX_D_0_4 => FF_RX_D_0_4,
-   FF_RX_D_0_5 => FF_RX_D_0_5,
-   FF_RX_D_0_6 => FF_RX_D_0_6,
-   FF_RX_D_0_7 => FF_RX_D_0_7,
-   FF_RX_D_0_8 => FF_RX_D_0_8,
-   FF_RX_D_0_9 => FF_RX_D_0_9,
-   FF_RX_D_0_10 => FF_RX_D_0_10,
-   FF_RX_D_0_11 => FF_RX_D_0_11,
-   FF_RX_D_0_12 => FF_RX_D_0_12,
-   FF_RX_D_0_13 => FF_RX_D_0_13,
-   FF_RX_D_0_14 => FF_RX_D_0_14,
-   FF_RX_D_0_15 => FF_RX_D_0_15,
-   FF_RX_D_0_16 => FF_RX_D_0_16,
-   FF_RX_D_0_17 => FF_RX_D_0_17,
-   FF_RX_D_0_18 => FF_RX_D_0_18,
-   FF_RX_D_0_19 => FF_RX_D_0_19,
-   FF_RX_D_0_20 => FF_RX_D_0_20,
-   FF_RX_D_0_21 => FF_RX_D_0_21,
-   FF_RX_D_0_22 => FF_RX_D_0_22,
-   FF_RX_D_0_23 => FF_RX_D_0_23,
-   FF_RX_D_1_0 => FF_RX_D_1_0,
-   FF_RX_D_1_1 => FF_RX_D_1_1,
-   FF_RX_D_1_2 => FF_RX_D_1_2,
-   FF_RX_D_1_3 => FF_RX_D_1_3,
-   FF_RX_D_1_4 => FF_RX_D_1_4,
-   FF_RX_D_1_5 => FF_RX_D_1_5,
-   FF_RX_D_1_6 => FF_RX_D_1_6,
-   FF_RX_D_1_7 => FF_RX_D_1_7,
-   FF_RX_D_1_8 => FF_RX_D_1_8,
-   FF_RX_D_1_9 => FF_RX_D_1_9,
-   FF_RX_D_1_10 => FF_RX_D_1_10,
-   FF_RX_D_1_11 => FF_RX_D_1_11,
-   FF_RX_D_1_12 => FF_RX_D_1_12,
-   FF_RX_D_1_13 => FF_RX_D_1_13,
-   FF_RX_D_1_14 => FF_RX_D_1_14,
-   FF_RX_D_1_15 => FF_RX_D_1_15,
-   FF_RX_D_1_16 => FF_RX_D_1_16,
-   FF_RX_D_1_17 => FF_RX_D_1_17,
-   FF_RX_D_1_18 => FF_RX_D_1_18,
-   FF_RX_D_1_19 => FF_RX_D_1_19,
-   FF_RX_D_1_20 => FF_RX_D_1_20,
-   FF_RX_D_1_21 => FF_RX_D_1_21,
-   FF_RX_D_1_22 => FF_RX_D_1_22,
-   FF_RX_D_1_23 => FF_RX_D_1_23,
-   FF_RX_D_2_0 => FF_RX_D_2_0,
-   FF_RX_D_2_1 => FF_RX_D_2_1,
-   FF_RX_D_2_2 => FF_RX_D_2_2,
-   FF_RX_D_2_3 => FF_RX_D_2_3,
-   FF_RX_D_2_4 => FF_RX_D_2_4,
-   FF_RX_D_2_5 => FF_RX_D_2_5,
-   FF_RX_D_2_6 => FF_RX_D_2_6,
-   FF_RX_D_2_7 => FF_RX_D_2_7,
-   FF_RX_D_2_8 => FF_RX_D_2_8,
-   FF_RX_D_2_9 => FF_RX_D_2_9,
-   FF_RX_D_2_10 => FF_RX_D_2_10,
-   FF_RX_D_2_11 => FF_RX_D_2_11,
-   FF_RX_D_2_12 => FF_RX_D_2_12,
-   FF_RX_D_2_13 => FF_RX_D_2_13,
-   FF_RX_D_2_14 => FF_RX_D_2_14,
-   FF_RX_D_2_15 => FF_RX_D_2_15,
-   FF_RX_D_2_16 => FF_RX_D_2_16,
-   FF_RX_D_2_17 => FF_RX_D_2_17,
-   FF_RX_D_2_18 => FF_RX_D_2_18,
-   FF_RX_D_2_19 => FF_RX_D_2_19,
-   FF_RX_D_2_20 => FF_RX_D_2_20,
-   FF_RX_D_2_21 => FF_RX_D_2_21,
-   FF_RX_D_2_22 => FF_RX_D_2_22,
-   FF_RX_D_2_23 => FF_RX_D_2_23,
-   FF_RX_D_3_0 => FF_RX_D_3_0,
-   FF_RX_D_3_1 => FF_RX_D_3_1,
-   FF_RX_D_3_2 => FF_RX_D_3_2,
-   FF_RX_D_3_3 => FF_RX_D_3_3,
-   FF_RX_D_3_4 => FF_RX_D_3_4,
-   FF_RX_D_3_5 => FF_RX_D_3_5,
-   FF_RX_D_3_6 => FF_RX_D_3_6,
-   FF_RX_D_3_7 => FF_RX_D_3_7,
-   FF_RX_D_3_8 => FF_RX_D_3_8,
-   FF_RX_D_3_9 => FF_RX_D_3_9,
-   FF_RX_D_3_10 => FF_RX_D_3_10,
-   FF_RX_D_3_11 => FF_RX_D_3_11,
-   FF_RX_D_3_12 => FF_RX_D_3_12,
-   FF_RX_D_3_13 => FF_RX_D_3_13,
-   FF_RX_D_3_14 => FF_RX_D_3_14,
-   FF_RX_D_3_15 => FF_RX_D_3_15,
-   FF_RX_D_3_16 => FF_RX_D_3_16,
-   FF_RX_D_3_17 => FF_RX_D_3_17,
-   FF_RX_D_3_18 => FF_RX_D_3_18,
-   FF_RX_D_3_19 => FF_RX_D_3_19,
-   FF_RX_D_3_20 => FF_RX_D_3_20,
-   FF_RX_D_3_21 => FF_RX_D_3_21,
-   FF_RX_D_3_22 => FF_RX_D_3_22,
-   FF_RX_D_3_23 => FF_RX_D_3_23,
-   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
-   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
-   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
-   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
-   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
-   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
-   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
-   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
-   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
-   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
-   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
-   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
-   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
-   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
-   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
-   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
-   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
-   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
-   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
-   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
-   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
-   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
-   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
-   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
-   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
-   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
-   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
-   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
-   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
-   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
-   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
-   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
-   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
-   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
-   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
-   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
-   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
-   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
-   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
-   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
-   FFS_PLOL => FFS_PLOL,
-   FFS_RLOL_0 => FFS_RLOL_0,
-   FFS_RLOL_1 => FFS_RLOL_1,
-   FFS_RLOL_2 => FFS_RLOL_2,
-   FFS_RLOL_3 => FFS_RLOL_3,
-   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
-   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
-   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
-   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
-   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
-   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
-   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
-   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
-   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
-   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
-   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
-   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
-   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
-   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
-   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
-   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
-   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
-   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
-   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
-   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
-   PCIE_RXVALID_0 => PCIE_RXVALID_0,
-   PCIE_RXVALID_1 => PCIE_RXVALID_1,
-   PCIE_RXVALID_2 => PCIE_RXVALID_2,
-   PCIE_RXVALID_3 => PCIE_RXVALID_3,
-   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
-   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
-   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
-   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
-   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
-   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
-   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
-   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
-   LDR_RX2CORE_0 => LDR_RX2CORE_0,
-   LDR_RX2CORE_1 => LDR_RX2CORE_1,
-   LDR_RX2CORE_2 => LDR_RX2CORE_2,
-   LDR_RX2CORE_3 => LDR_RX2CORE_3,
-   REFCK2CORE => REFCK2CORE,
-   SCIINT => SCIINT,
-   SCIRDATA0 => SCIRDATA0,
-   SCIRDATA1 => SCIRDATA1,
-   SCIRDATA2 => SCIRDATA2,
-   SCIRDATA3 => SCIRDATA3,
-   SCIRDATA4 => SCIRDATA4,
-   SCIRDATA5 => SCIRDATA5,
-   SCIRDATA6 => SCIRDATA6,
-   SCIRDATA7 => SCIRDATA7,
-   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
-   REFCLK_TO_NQ => REFCLK_TO_NQ
-   );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity serdes_sync_source_downstream is
-   GENERIC (USER_CONFIG_FILE    :  String := "serdes_sync_source_downstream.txt");
- port (
-------------------
--- CH0 --
-    hdinp_ch0, hdinn_ch0    :   in std_logic;
-    hdoutp_ch0, hdoutn_ch0   :   out std_logic;
-    sci_sel_ch0    :   in std_logic;
-    rxiclk_ch0    :   in std_logic;
-    txiclk_ch0    :   in std_logic;
-    rx_full_clk_ch0   :   out std_logic;
-    rx_half_clk_ch0   :   out std_logic;
-    tx_full_clk_ch0   :   out std_logic;
-    tx_half_clk_ch0   :   out std_logic;
-    fpga_rxrefclk_ch0    :   in std_logic;
-    txdata_ch0    :   in std_logic_vector (7 downto 0);
-    tx_k_ch0    :   in std_logic;
-    tx_force_disp_ch0    :   in std_logic;
-    tx_disp_sel_ch0    :   in std_logic;
-    rxdata_ch0   :   out std_logic_vector (7 downto 0);
-    rx_k_ch0   :   out std_logic;
-    rx_disp_err_ch0   :   out std_logic;
-    rx_cv_err_ch0   :   out std_logic;
-    rx_serdes_rst_ch0_c    :   in std_logic;
-    sb_felb_ch0_c    :   in std_logic;
-    sb_felb_rst_ch0_c    :   in std_logic;
-    tx_pcs_rst_ch0_c    :   in std_logic;
-    tx_pwrup_ch0_c    :   in std_logic;
-    rx_pcs_rst_ch0_c    :   in std_logic;
-    rx_pwrup_ch0_c    :   in std_logic;
-    rx_los_low_ch0_s   :   out std_logic;
-    lsm_status_ch0_s   :   out std_logic;
-    rx_cdr_lol_ch0_s   :   out std_logic;
-    tx_div2_mode_ch0_c   : in std_logic;
-    rx_div2_mode_ch0_c   : in std_logic;
--- CH1 --
--- CH2 --
--- CH3 --
----- Miscillaneous ports
-    sci_wrdata    :   in std_logic_vector (7 downto 0);
-    sci_addr    :   in std_logic_vector (5 downto 0);
-    sci_rddata   :   out std_logic_vector (7 downto 0);
-    sci_sel_quad    :   in std_logic;
-    sci_rd    :   in std_logic;
-    sci_wrn    :   in std_logic;
-    fpga_txrefclk  :   in std_logic;
-    tx_serdes_rst_c    :   in std_logic;
-    tx_pll_lol_qd_s   :   out std_logic;
-    rst_qd_c    :   in std_logic;
-    refclk2fpga   :   out std_logic;
-    serdes_rst_qd_c    :   in std_logic);
-
-end serdes_sync_source_downstream;
-
-
-architecture serdes_sync_source_downstream_arch of serdes_sync_source_downstream is
-
-component VLO
-port (
-   Z : out std_logic);
-end component;
-
-component VHI
-port (
-   Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
-  );
---synopsys translate_on
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-   attribute CONFIG_FILE: string;
-   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
-   attribute QUAD_MODE: string;
-   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
-   attribute PLL_SRC: string;
-   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH0_CDR_SRC: string;
-   attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_REFCK2CORE: string;
-   attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
-   attribute black_box_pad_pin: string;
-   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal    tx_full_clk_ch0_sig   :   std_logic;
-
-signal    refclk2fpga_sig  :   std_logic;
-signal    tx_pll_lol_qd_sig  :   std_logic;
-signal    rx_los_low_ch0_sig  :   std_logic;
-signal    rx_los_low_ch1_sig  :   std_logic;
-signal    rx_los_low_ch2_sig  :   std_logic;
-signal    rx_los_low_ch3_sig  :   std_logic;
-signal    rx_cdr_lol_ch0_sig  :   std_logic;
-signal    rx_cdr_lol_ch1_sig  :   std_logic;
-signal    rx_cdr_lol_ch2_sig  :   std_logic;
-signal    rx_cdr_lol_ch3_sig  :   std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
-  refclk2fpga <= refclk2fpga_sig;
-    rx_los_low_ch0_s <= rx_los_low_ch0_sig;
-    rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig;
-  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
-  tx_full_clk_ch0 <= tx_full_clk_ch0_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
-  generic map (CONFIG_FILE => USER_CONFIG_FILE,
-               QUAD_MODE => "SINGLE",
-               CH0_CDR_SRC => "REFCLK_CORE",
-               PLL_SRC  => "REFCLK_CORE"
-  )
---synopsys translate_on
-port map  (
-  REFCLKP => fpsc_vlo,
-  REFCLKN => fpsc_vlo,
-
------ CH0 -----
-  HDOUTP0 => hdoutp_ch0,
-  HDOUTN0 => hdoutn_ch0,
-  HDINP0 => hdinp_ch0,
-  HDINN0 => hdinn_ch0,
-  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
-  PCIE_RXPOLARITY_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_1 => fpsc_vlo,
-  PCIE_RXVALID_0 => open,
-  PCIE_PHYSTATUS_0 => open,
-  SCISELCH0 => sci_sel_ch0,
-  SCIENCH0 => fpsc_vhi,
-  FF_RXI_CLK_0 => rxiclk_ch0,
-  FF_TXI_CLK_0 => txiclk_ch0,
-  FF_EBRD_CLK_0 => fpsc_vlo,
-  FF_RX_F_CLK_0 => rx_full_clk_ch0,
-  FF_RX_H_CLK_0 => rx_half_clk_ch0,
-  FF_TX_F_CLK_0 => tx_full_clk_ch0_sig,
-  FF_TX_H_CLK_0 => tx_half_clk_ch0,
-  FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0,
-  FF_TX_D_0_0 => txdata_ch0(0),
-  FF_TX_D_0_1 => txdata_ch0(1),
-  FF_TX_D_0_2 => txdata_ch0(2),
-  FF_TX_D_0_3 => txdata_ch0(3),
-  FF_TX_D_0_4 => txdata_ch0(4),
-  FF_TX_D_0_5 => txdata_ch0(5),
-  FF_TX_D_0_6 => txdata_ch0(6),
-  FF_TX_D_0_7 => txdata_ch0(7),
-  FF_TX_D_0_8 => tx_k_ch0,
-  FF_TX_D_0_9 => tx_force_disp_ch0,
-  FF_TX_D_0_10 => tx_disp_sel_ch0,
-  FF_TX_D_0_11 => fpsc_vlo,
-  FF_TX_D_0_12 => fpsc_vlo,
-  FF_TX_D_0_13 => fpsc_vlo,
-  FF_TX_D_0_14 => fpsc_vlo,
-  FF_TX_D_0_15 => fpsc_vlo,
-  FF_TX_D_0_16 => fpsc_vlo,
-  FF_TX_D_0_17 => fpsc_vlo,
-  FF_TX_D_0_18 => fpsc_vlo,
-  FF_TX_D_0_19 => fpsc_vlo,
-  FF_TX_D_0_20 => fpsc_vlo,
-  FF_TX_D_0_21 => fpsc_vlo,
-  FF_TX_D_0_22 => fpsc_vlo,
-  FF_TX_D_0_23 => fpsc_vlo,
-  FF_RX_D_0_0 => rxdata_ch0(0),
-  FF_RX_D_0_1 => rxdata_ch0(1),
-  FF_RX_D_0_2 => rxdata_ch0(2),
-  FF_RX_D_0_3 => rxdata_ch0(3),
-  FF_RX_D_0_4 => rxdata_ch0(4),
-  FF_RX_D_0_5 => rxdata_ch0(5),
-  FF_RX_D_0_6 => rxdata_ch0(6),
-  FF_RX_D_0_7 => rxdata_ch0(7),
-  FF_RX_D_0_8 => rx_k_ch0,
-  FF_RX_D_0_9 => rx_disp_err_ch0,
-  FF_RX_D_0_10 => rx_cv_err_ch0,
-  FF_RX_D_0_11 => open,
-  FF_RX_D_0_12 => open,
-  FF_RX_D_0_13 => open,
-  FF_RX_D_0_14 => open,
-  FF_RX_D_0_15 => open,
-  FF_RX_D_0_16 => open,
-  FF_RX_D_0_17 => open,
-  FF_RX_D_0_18 => open,
-  FF_RX_D_0_19 => open,
-  FF_RX_D_0_20 => open,
-  FF_RX_D_0_21 => open,
-  FF_RX_D_0_22 => open,
-  FF_RX_D_0_23 => open,
-
-  FFC_RRST_0 => rx_serdes_rst_ch0_c,
-  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c,
-  FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c,
-  FFC_SB_INV_RX_0 => fpsc_vlo,
-  FFC_PCIE_CT_0 => fpsc_vlo,
-  FFC_PCI_DET_EN_0 => fpsc_vlo,
-  FFC_FB_LOOPBACK_0 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
-  FFC_EI_EN_0 => fpsc_vlo,
-  FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c,
-  FFC_TXPWDNB_0 => tx_pwrup_ch0_c,
-  FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c,
-  FFC_RXPWDNB_0 => rx_pwrup_ch0_c,
-  FFS_RLOS_LO_0 => rx_los_low_ch0_sig,
-  FFS_RLOS_HI_0 => open,
-  FFS_PCIE_CON_0 => open,
-  FFS_PCIE_DONE_0 => open,
-  FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s,
-  FFS_CC_OVERRUN_0 => open,
-  FFS_CC_UNDERRUN_0 => open,
-  FFS_SKP_ADDED_0 => open,
-  FFS_SKP_DELETED_0 => open,
-  FFS_RLOL_0 => rx_cdr_lol_ch0_sig,
-  FFS_RXFBFIFO_ERROR_0 => open,
-  FFS_TXFBFIFO_ERROR_0 => open,
-  LDR_CORE2TX_0 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
-  LDR_RX2CORE_0 => open,
-  FFS_CDR_TRAIN_DONE_0 => open,
-  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
-  FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c,
-  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
-  FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c,
-
------ CH1 -----
-  HDOUTP1 => open,
-  HDOUTN1 => open,
-  HDINP1 => fpsc_vlo,
-  HDINN1 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
-  PCIE_RXPOLARITY_1 => fpsc_vlo,
-  PCIE_POWERDOWN_1_0 => fpsc_vlo,
-  PCIE_POWERDOWN_1_1 => fpsc_vlo,
-  PCIE_RXVALID_1 => open,
-  PCIE_PHYSTATUS_1 => open,
-  SCISELCH1 => fpsc_vlo,
-  SCIENCH1 => fpsc_vlo,
-  FF_RXI_CLK_1 => fpsc_vlo,
-  FF_TXI_CLK_1 => fpsc_vlo,
-  FF_EBRD_CLK_1 => fpsc_vlo,
-  FF_RX_F_CLK_1 => open,
-  FF_RX_H_CLK_1 => open,
-  FF_TX_F_CLK_1 => open,
-  FF_TX_H_CLK_1 => open,
-  FFC_CK_CORE_RX_1 => fpsc_vlo,
-  FF_TX_D_1_0 => fpsc_vlo,
-  FF_TX_D_1_1 => fpsc_vlo,
-  FF_TX_D_1_2 => fpsc_vlo,
-  FF_TX_D_1_3 => fpsc_vlo,
-  FF_TX_D_1_4 => fpsc_vlo,
-  FF_TX_D_1_5 => fpsc_vlo,
-  FF_TX_D_1_6 => fpsc_vlo,
-  FF_TX_D_1_7 => fpsc_vlo,
-  FF_TX_D_1_8 => fpsc_vlo,
-  FF_TX_D_1_9 => fpsc_vlo,
-  FF_TX_D_1_10 => fpsc_vlo,
-  FF_TX_D_1_11 => fpsc_vlo,
-  FF_TX_D_1_12 => fpsc_vlo,
-  FF_TX_D_1_13 => fpsc_vlo,
-  FF_TX_D_1_14 => fpsc_vlo,
-  FF_TX_D_1_15 => fpsc_vlo,
-  FF_TX_D_1_16 => fpsc_vlo,
-  FF_TX_D_1_17 => fpsc_vlo,
-  FF_TX_D_1_18 => fpsc_vlo,
-  FF_TX_D_1_19 => fpsc_vlo,
-  FF_TX_D_1_20 => fpsc_vlo,
-  FF_TX_D_1_21 => fpsc_vlo,
-  FF_TX_D_1_22 => fpsc_vlo,
-  FF_TX_D_1_23 => fpsc_vlo,
-  FF_RX_D_1_0 => open,
-  FF_RX_D_1_1 => open,
-  FF_RX_D_1_2 => open,
-  FF_RX_D_1_3 => open,
-  FF_RX_D_1_4 => open,
-  FF_RX_D_1_5 => open,
-  FF_RX_D_1_6 => open,
-  FF_RX_D_1_7 => open,
-  FF_RX_D_1_8 => open,
-  FF_RX_D_1_9 => open,
-  FF_RX_D_1_10 => open,
-  FF_RX_D_1_11 => open,
-  FF_RX_D_1_12 => open,
-  FF_RX_D_1_13 => open,
-  FF_RX_D_1_14 => open,
-  FF_RX_D_1_15 => open,
-  FF_RX_D_1_16 => open,
-  FF_RX_D_1_17 => open,
-  FF_RX_D_1_18 => open,
-  FF_RX_D_1_19 => open,
-  FF_RX_D_1_20 => open,
-  FF_RX_D_1_21 => open,
-  FF_RX_D_1_22 => open,
-  FF_RX_D_1_23 => open,
-
-  FFC_RRST_1 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_1 => fpsc_vlo,
-  FFC_PFIFO_CLR_1 => fpsc_vlo,
-  FFC_SB_INV_RX_1 => fpsc_vlo,
-  FFC_PCIE_CT_1 => fpsc_vlo,
-  FFC_PCI_DET_EN_1 => fpsc_vlo,
-  FFC_FB_LOOPBACK_1 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
-  FFC_EI_EN_1 => fpsc_vlo,
-  FFC_LANE_TX_RST_1 => fpsc_vlo,
-  FFC_TXPWDNB_1 => fpsc_vlo,
-  FFC_LANE_RX_RST_1 => fpsc_vlo,
-  FFC_RXPWDNB_1 => fpsc_vlo,
-  FFS_RLOS_LO_1 => open,
-  FFS_RLOS_HI_1 => open,
-  FFS_PCIE_CON_1 => open,
-  FFS_PCIE_DONE_1 => open,
-  FFS_LS_SYNC_STATUS_1 => open,
-  FFS_CC_OVERRUN_1 => open,
-  FFS_CC_UNDERRUN_1 => open,
-  FFS_SKP_ADDED_1 => open,
-  FFS_SKP_DELETED_1 => open,
-  FFS_RLOL_1 => open,
-  FFS_RXFBFIFO_ERROR_1 => open,
-  FFS_TXFBFIFO_ERROR_1 => open,
-  LDR_CORE2TX_1 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
-  LDR_RX2CORE_1 => open,
-  FFS_CDR_TRAIN_DONE_1 => open,
-  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
-  FFC_RATE_MODE_TX_1 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
-  FFC_RATE_MODE_RX_1 => fpsc_vlo,
-
------ CH2 -----
-  HDOUTP2 => open,
-  HDOUTN2 => open,
-  HDINP2 => fpsc_vlo,
-  HDINN2 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
-  PCIE_RXPOLARITY_2 => fpsc_vlo,
-  PCIE_POWERDOWN_2_0 => fpsc_vlo,
-  PCIE_POWERDOWN_2_1 => fpsc_vlo,
-  PCIE_RXVALID_2 => open,
-  PCIE_PHYSTATUS_2 => open,
-  SCISELCH2 => fpsc_vlo,
-  SCIENCH2 => fpsc_vlo,
-  FF_RXI_CLK_2 => fpsc_vlo,
-  FF_TXI_CLK_2 => fpsc_vlo,
-  FF_EBRD_CLK_2 => fpsc_vlo,
-  FF_RX_F_CLK_2 => open,
-  FF_RX_H_CLK_2 => open,
-  FF_TX_F_CLK_2 => open,
-  FF_TX_H_CLK_2 => open,
-  FFC_CK_CORE_RX_2 => fpsc_vlo,
-  FF_TX_D_2_0 => fpsc_vlo,
-  FF_TX_D_2_1 => fpsc_vlo,
-  FF_TX_D_2_2 => fpsc_vlo,
-  FF_TX_D_2_3 => fpsc_vlo,
-  FF_TX_D_2_4 => fpsc_vlo,
-  FF_TX_D_2_5 => fpsc_vlo,
-  FF_TX_D_2_6 => fpsc_vlo,
-  FF_TX_D_2_7 => fpsc_vlo,
-  FF_TX_D_2_8 => fpsc_vlo,
-  FF_TX_D_2_9 => fpsc_vlo,
-  FF_TX_D_2_10 => fpsc_vlo,
-  FF_TX_D_2_11 => fpsc_vlo,
-  FF_TX_D_2_12 => fpsc_vlo,
-  FF_TX_D_2_13 => fpsc_vlo,
-  FF_TX_D_2_14 => fpsc_vlo,
-  FF_TX_D_2_15 => fpsc_vlo,
-  FF_TX_D_2_16 => fpsc_vlo,
-  FF_TX_D_2_17 => fpsc_vlo,
-  FF_TX_D_2_18 => fpsc_vlo,
-  FF_TX_D_2_19 => fpsc_vlo,
-  FF_TX_D_2_20 => fpsc_vlo,
-  FF_TX_D_2_21 => fpsc_vlo,
-  FF_TX_D_2_22 => fpsc_vlo,
-  FF_TX_D_2_23 => fpsc_vlo,
-  FF_RX_D_2_0 => open,
-  FF_RX_D_2_1 => open,
-  FF_RX_D_2_2 => open,
-  FF_RX_D_2_3 => open,
-  FF_RX_D_2_4 => open,
-  FF_RX_D_2_5 => open,
-  FF_RX_D_2_6 => open,
-  FF_RX_D_2_7 => open,
-  FF_RX_D_2_8 => open,
-  FF_RX_D_2_9 => open,
-  FF_RX_D_2_10 => open,
-  FF_RX_D_2_11 => open,
-  FF_RX_D_2_12 => open,
-  FF_RX_D_2_13 => open,
-  FF_RX_D_2_14 => open,
-  FF_RX_D_2_15 => open,
-  FF_RX_D_2_16 => open,
-  FF_RX_D_2_17 => open,
-  FF_RX_D_2_18 => open,
-  FF_RX_D_2_19 => open,
-  FF_RX_D_2_20 => open,
-  FF_RX_D_2_21 => open,
-  FF_RX_D_2_22 => open,
-  FF_RX_D_2_23 => open,
-
-  FFC_RRST_2 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_2 => fpsc_vlo,
-  FFC_PFIFO_CLR_2 => fpsc_vlo,
-  FFC_SB_INV_RX_2 => fpsc_vlo,
-  FFC_PCIE_CT_2 => fpsc_vlo,
-  FFC_PCI_DET_EN_2 => fpsc_vlo,
-  FFC_FB_LOOPBACK_2 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
-  FFC_EI_EN_2 => fpsc_vlo,
-  FFC_LANE_TX_RST_2 => fpsc_vlo,
-  FFC_TXPWDNB_2 => fpsc_vlo,
-  FFC_LANE_RX_RST_2 => fpsc_vlo,
-  FFC_RXPWDNB_2 => fpsc_vlo,
-  FFS_RLOS_LO_2 => open,
-  FFS_RLOS_HI_2 => open,
-  FFS_PCIE_CON_2 => open,
-  FFS_PCIE_DONE_2 => open,
-  FFS_LS_SYNC_STATUS_2 => open,
-  FFS_CC_OVERRUN_2 => open,
-  FFS_CC_UNDERRUN_2 => open,
-  FFS_SKP_ADDED_2 => open,
-  FFS_SKP_DELETED_2 => open,
-  FFS_RLOL_2 => open,
-  FFS_RXFBFIFO_ERROR_2 => open,
-  FFS_TXFBFIFO_ERROR_2 => open,
-  LDR_CORE2TX_2 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
-  LDR_RX2CORE_2 => open,
-  FFS_CDR_TRAIN_DONE_2 => open,
-  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
-  FFC_RATE_MODE_TX_2 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
-  FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
-  HDOUTP3 => open,
-  HDOUTN3 => open,
-  HDINP3 => fpsc_vlo,
-  HDINN3 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
-  PCIE_RXPOLARITY_3 => fpsc_vlo,
-  PCIE_POWERDOWN_3_0 => fpsc_vlo,
-  PCIE_POWERDOWN_3_1 => fpsc_vlo,
-  PCIE_RXVALID_3 => open,
-  PCIE_PHYSTATUS_3 => open,
-  SCISELCH3 => fpsc_vlo,
-  SCIENCH3 => fpsc_vlo,
-  FF_RXI_CLK_3 => fpsc_vlo,
-  FF_TXI_CLK_3 => fpsc_vlo,
-  FF_EBRD_CLK_3 => fpsc_vlo,
-  FF_RX_F_CLK_3 => open,
-  FF_RX_H_CLK_3 => open,
-  FF_TX_F_CLK_3 => open,
-  FF_TX_H_CLK_3 => open,
-  FFC_CK_CORE_RX_3 => fpsc_vlo,
-  FF_TX_D_3_0 => fpsc_vlo,
-  FF_TX_D_3_1 => fpsc_vlo,
-  FF_TX_D_3_2 => fpsc_vlo,
-  FF_TX_D_3_3 => fpsc_vlo,
-  FF_TX_D_3_4 => fpsc_vlo,
-  FF_TX_D_3_5 => fpsc_vlo,
-  FF_TX_D_3_6 => fpsc_vlo,
-  FF_TX_D_3_7 => fpsc_vlo,
-  FF_TX_D_3_8 => fpsc_vlo,
-  FF_TX_D_3_9 => fpsc_vlo,
-  FF_TX_D_3_10 => fpsc_vlo,
-  FF_TX_D_3_11 => fpsc_vlo,
-  FF_TX_D_3_12 => fpsc_vlo,
-  FF_TX_D_3_13 => fpsc_vlo,
-  FF_TX_D_3_14 => fpsc_vlo,
-  FF_TX_D_3_15 => fpsc_vlo,
-  FF_TX_D_3_16 => fpsc_vlo,
-  FF_TX_D_3_17 => fpsc_vlo,
-  FF_TX_D_3_18 => fpsc_vlo,
-  FF_TX_D_3_19 => fpsc_vlo,
-  FF_TX_D_3_20 => fpsc_vlo,
-  FF_TX_D_3_21 => fpsc_vlo,
-  FF_TX_D_3_22 => fpsc_vlo,
-  FF_TX_D_3_23 => fpsc_vlo,
-  FF_RX_D_3_0 => open,
-  FF_RX_D_3_1 => open,
-  FF_RX_D_3_2 => open,
-  FF_RX_D_3_3 => open,
-  FF_RX_D_3_4 => open,
-  FF_RX_D_3_5 => open,
-  FF_RX_D_3_6 => open,
-  FF_RX_D_3_7 => open,
-  FF_RX_D_3_8 => open,
-  FF_RX_D_3_9 => open,
-  FF_RX_D_3_10 => open,
-  FF_RX_D_3_11 => open,
-  FF_RX_D_3_12 => open,
-  FF_RX_D_3_13 => open,
-  FF_RX_D_3_14 => open,
-  FF_RX_D_3_15 => open,
-  FF_RX_D_3_16 => open,
-  FF_RX_D_3_17 => open,
-  FF_RX_D_3_18 => open,
-  FF_RX_D_3_19 => open,
-  FF_RX_D_3_20 => open,
-  FF_RX_D_3_21 => open,
-  FF_RX_D_3_22 => open,
-  FF_RX_D_3_23 => open,
-
-  FFC_RRST_3 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_3 => fpsc_vlo,
-  FFC_PFIFO_CLR_3 => fpsc_vlo,
-  FFC_SB_INV_RX_3 => fpsc_vlo,
-  FFC_PCIE_CT_3 => fpsc_vlo,
-  FFC_PCI_DET_EN_3 => fpsc_vlo,
-  FFC_FB_LOOPBACK_3 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
-  FFC_EI_EN_3 => fpsc_vlo,
-  FFC_LANE_TX_RST_3 => fpsc_vlo,
-  FFC_TXPWDNB_3 => fpsc_vlo,
-  FFC_LANE_RX_RST_3 => fpsc_vlo,
-  FFC_RXPWDNB_3 => fpsc_vlo,
-  FFS_RLOS_LO_3 => open,
-  FFS_RLOS_HI_3 => open,
-  FFS_PCIE_CON_3 => open,
-  FFS_PCIE_DONE_3 => open,
-  FFS_LS_SYNC_STATUS_3 => open,
-  FFS_CC_OVERRUN_3 => open,
-  FFS_CC_UNDERRUN_3 => open,
-  FFS_SKP_ADDED_3 => open,
-  FFS_SKP_DELETED_3 => open,
-  FFS_RLOL_3 => open,
-  FFS_RXFBFIFO_ERROR_3 => open,
-  FFS_TXFBFIFO_ERROR_3 => open,
-  LDR_CORE2TX_3 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
-  LDR_RX2CORE_3 => open,
-  FFS_CDR_TRAIN_DONE_3 => open,
-  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
-  FFC_RATE_MODE_TX_3 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
-  FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
-  SCIWDATA7 => sci_wrdata(7),
-  SCIWDATA6 => sci_wrdata(6),
-  SCIWDATA5 => sci_wrdata(5),
-  SCIWDATA4 => sci_wrdata(4),
-  SCIWDATA3 => sci_wrdata(3),
-  SCIWDATA2 => sci_wrdata(2),
-  SCIWDATA1 => sci_wrdata(1),
-  SCIWDATA0 => sci_wrdata(0),
-  SCIADDR5 => sci_addr(5),
-  SCIADDR4 => sci_addr(4),
-  SCIADDR3 => sci_addr(3),
-  SCIADDR2 => sci_addr(2),
-  SCIADDR1 => sci_addr(1),
-  SCIADDR0 => sci_addr(0),
-  SCIRDATA7 => sci_rddata(7),
-  SCIRDATA6 => sci_rddata(6),
-  SCIRDATA5 => sci_rddata(5),
-  SCIRDATA4 => sci_rddata(4),
-  SCIRDATA3 => sci_rddata(3),
-  SCIRDATA2 => sci_rddata(2),
-  SCIRDATA1 => sci_rddata(1),
-  SCIRDATA0 => sci_rddata(0),
-  SCIENAUX => fpsc_vhi,
-  SCISELAUX => sci_sel_quad,
-  SCIRD => sci_rd,
-  SCIWSTN => sci_wrn,
-  CYAWSTN => fpsc_vlo,
-  SCIINT => open,
-  FFC_CK_CORE_TX => fpga_txrefclk,
-  FFC_MACRO_RST => serdes_rst_qd_c,
-  FFC_QUAD_RST => rst_qd_c,
-  FFC_TRST => tx_serdes_rst_c,
-  FFS_PLOL => tx_pll_lol_qd_sig,
-  FFC_SYNC_TOGGLE => fpsc_vlo,
-  REFCK2CORE => refclk2fpga_sig,
-  CIN0 => fpsc_vlo,
-  CIN1 => fpsc_vlo,
-  CIN2 => fpsc_vlo,
-  CIN3 => fpsc_vlo,
-  CIN4 => fpsc_vlo,
-  CIN5 => fpsc_vlo,
-  CIN6 => fpsc_vlo,
-  CIN7 => fpsc_vlo,
-  CIN8 => fpsc_vlo,
-  CIN9 => fpsc_vlo,
-  CIN10 => fpsc_vlo,
-  CIN11 => fpsc_vlo,
-  COUT0 => open,
-  COUT1 => open,
-  COUT2 => open,
-  COUT3 => open,
-  COUT4 => open,
-  COUT5 => open,
-  COUT6 => open,
-  COUT7 => open,
-  COUT8 => open,
-  COUT9 => open,
-  COUT10 => open,
-  COUT11 => open,
-  COUT12 => open,
-  COUT13 => open,
-  COUT14 => open,
-  COUT15 => open,
-  COUT16 => open,
-  COUT17 => open,
-  COUT18 => open,
-  COUT19 => open,
-  REFCLK_FROM_NQ => refclk_from_nq,
-  REFCLK_TO_NQ => open);
-
-                                                                                              
-                                                                                              
-                                                                                              
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
-   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
-   IF (open_status = name_error) THEN
-      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
-      severity ERROR;
-   END IF;
-   wait;
-END PROCESS;
---synopsys translate_on
-end serdes_sync_source_downstream_arch ;
diff --git a/code/ip/serdes_sync_upstream.ipx b/code/ip/serdes_sync_upstream.ipx
deleted file mode 100644
index bf676e5..0000000
--- a/code/ip/serdes_sync_upstream.ipx
+++ /dev/null
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 03 04 13:04:52.349" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-		<File name="serdes_sync_upstream.lpc" type="lpc" modified="2015 03 04 13:04:49.000"/>
-		<File name="serdes_sync_upstream.pp" type="pp" modified="2015 03 04 13:04:49.000"/>
-		<File name="serdes_sync_upstream.sym" type="sym" modified="2015 03 04 13:04:49.000"/>
-		<File name="serdes_sync_upstream.tft" type="tft" modified="2015 03 04 13:04:49.000"/>
-		<File name="serdes_sync_upstream.txt" type="pcs_module" modified="2015 03 04 13:04:49.000"/>
-		<File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2015 03 04 13:04:49.000"/>
-  </Package>
-</DiamondModule>
diff --git a/code/ip/serdes_sync_upstream.txt b/code/ip/serdes_sync_upstream.txt
deleted file mode 100644
index 9f2bf0d..0000000
--- a/code/ip/serdes_sync_upstream.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH3_PROTOCOL            "G8B10B"
-CH0_MODE                "DISABLED"
-CH1_MODE                "DISABLED"
-CH2_MODE                "DISABLED"
-CH3_MODE                "RXTX"
-CH3_CDR_SRC       "REFCLK_CORE"
-PLL_SRC                 "REFCLK_CORE"
-TX_DATARATE_RANGE       "MEDHIGH"
-CH3_RX_DATARATE_RANGE   "MEDHIGH"
-REFCK_MULT              "10X"
-#REFCLK_RATE            200
-CH3_RX_DATA_RATE        "FULL"
-CH3_TX_DATA_RATE        "FULL"
-CH3_TX_DATA_WIDTH       "8"
-CH3_RX_DATA_WIDTH        "8"
-CH3_TX_FIFO       "DISABLED"
-CH3_RX_FIFO        "DISABLED"
-CH3_TDRV      "0"
-#CH3_TX_FICLK_RATE      200
-#CH3_RXREFCLK_RATE        "200"
-#CH3_RX_FICLK_RATE      200
-CH3_TX_PRE              "DISABLED"
-CH3_RTERM_TX            "50"
-CH3_RX_EQ               "DISABLED"
-CH3_RTERM_RX            "50"
-CH3_RX_DCC              "DC"
-CH3_LOS_THRESHOLD_LO       "2"
-PLL_TERM                "50"
-PLL_DCC                 "AC"
-PLL_LOL_SET             "0"
-CH3_TX_SB               "DISABLED"
-CH3_RX_SB               "DISABLED"
-CH3_TX_8B10B            "ENABLED"
-CH3_RX_8B10B            "ENABLED"
-CH3_COMMA_A             "1100000101"
-CH3_COMMA_B             "0011111010"
-CH3_COMMA_M             "1111111100"
-CH3_RXWA                "ENABLED"
-CH3_ILSM                "ENABLED"
-CH3_CTC                 "DISABLED"
-CH3_CC_MATCH4           "0000000000"
-CH3_CC_MATCH_MODE       "1"
-CH3_CC_MIN_IPG          "3"
-CCHMARK                 "9"
-CCLMARK                 "7"
-CH3_SSLB                "DISABLED"
-CH3_SPLBPORTS           "DISABLED"
-CH3_PCSLBPORTS          "DISABLED"
-INT_ALL                 "DISABLED"
-QD_REFCK2CORE           "ENABLED"
-
-
diff --git a/code/ip/sfp_1_125_int.ipx b/code/ip/sfp_1_125_int.ipx
deleted file mode 100644
index d9de470..0000000
--- a/code/ip/sfp_1_125_int.ipx
+++ /dev/null
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="sfp_1_125_int" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 11 26 14:19:29.243" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-		<File name="sfp_1_125_int.lpc" type="lpc" modified="2014 11 26 14:19:25.000"/>
-		<File name="sfp_1_125_int.pp" type="pp" modified="2014 11 26 14:19:25.000"/>
-		<File name="sfp_1_125_int.sym" type="sym" modified="2014 11 26 14:19:25.000"/>
-		<File name="sfp_1_125_int.tft" type="tft" modified="2014 11 26 14:19:25.000"/>
-		<File name="sfp_1_125_int.txt" type="pcs_module" modified="2014 11 26 14:19:25.000"/>
-		<File name="sfp_1_125_int.vhd" type="top_level_vhdl" modified="2014 11 26 14:19:25.000"/>
-  </Package>
-</DiamondModule>
diff --git a/code/ip/sfp_1_125_int.lpc b/code/ip/sfp_1_125_int.lpc
deleted file mode 100644
index 0b884d1..0000000
--- a/code/ip/sfp_1_125_int.lpc
+++ /dev/null
@@ -1,258 +0,0 @@
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.2
-ModuleName=sfp_1_125_int
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=11/26/2014
-Time=14:19:25
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=DISABLED
-_mode1=RXTX
-_mode2=DISABLED
-_mode3=DISABLED
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2.5
-_pll_txsrc=INTERNAL
-_refclk_mult=20X
-_refclk_rate=125.0
-_tx_protocol0=DISABLED
-_tx_protocol1=G8B10B
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=16
-_tx_data_width1=16
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
-_tx_ficlk_rate0=125.0
-_tx_ficlk_rate1=125.0
-_tx_ficlk_rate2=250.0
-_tx_ficlk_rate3=250.0
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=INTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=EXTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2.5
-_rx_datarange2=2
-_rx_datarange3=2
-_rx_protocol0=DISABLED
-_rx_protocol1=G8B10B
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=100
-_rxrefclk_rate1=125.0
-_rxrefclk_rate2=100
-_rxrefclk_rate3=100
-_rx_data_width0=16
-_rx_data_width1=16
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=ENABLED
-_rx_ficlk_rate0=100
-_rx_ficlk_rate1=125.0
-_rx_ficlk_rate2=200
-_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=DC
-_rx_dcc2=AC
-_rx_dcc3=AC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=2
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=01
-_k02=00
-_k03=00
-_k10=01
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00011100
-_byten02=00000000
-_byten03=00000000
-_byten10=00011100
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=1
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=ENABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=auto
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-sfp_1_125_int.pp=pp
-sfp_1_125_int.tft=tft
-sfp_1_125_int.txt=pcs_module
-sfp_1_125_int.sym=sym
diff --git a/code/ip/sfp_1_125_int.txt b/code/ip/sfp_1_125_int.txt
deleted file mode 100644
index a684493..0000000
--- a/code/ip/sfp_1_125_int.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH1_PROTOCOL            "G8B10B"
-CH0_MODE                "DISABLED"
-CH1_MODE                "RXTX"
-CH2_MODE                "DISABLED"
-CH3_MODE                "DISABLED"
-CH1_CDR_SRC       "REFCLK_CORE"
-PLL_SRC                 "REFCLK_CORE"
-TX_DATARATE_RANGE       "MEDHIGH"
-CH1_RX_DATARATE_RANGE   "MEDHIGH"
-REFCK_MULT              "20X"
-#REFCLK_RATE            125.0
-CH1_RX_DATA_RATE        "FULL"
-CH1_TX_DATA_RATE        "FULL"
-CH1_TX_DATA_WIDTH       "16"
-CH1_RX_DATA_WIDTH        "16"
-CH1_TX_FIFO       "ENABLED"
-CH1_RX_FIFO        "ENABLED"
-CH1_TDRV      "0"
-#CH1_TX_FICLK_RATE      125.0
-#CH1_RXREFCLK_RATE        "125.0"
-#CH1_RX_FICLK_RATE      125.0
-CH1_TX_PRE              "DISABLED"
-CH1_RTERM_TX            "50"
-CH1_RX_EQ               "DISABLED"
-CH1_RTERM_RX            "50"
-CH1_RX_DCC              "DC"
-CH1_LOS_THRESHOLD_LO       "2"
-PLL_TERM                "50"
-PLL_DCC                 "AC"
-PLL_LOL_SET             "0"
-CH1_TX_SB               "DISABLED"
-CH1_RX_SB               "DISABLED"
-CH1_TX_8B10B            "ENABLED"
-CH1_RX_8B10B            "ENABLED"
-CH1_COMMA_A             "1100000101"
-CH1_COMMA_B             "0011111010"
-CH1_COMMA_M             "1111111100"
-CH1_RXWA                "ENABLED"
-CH1_ILSM                "ENABLED"
-CH1_CTC                 "DISABLED"
-CH1_CC_MATCH4           "0100011100"
-CH1_CC_MATCH_MODE       "1"
-CH1_CC_MIN_IPG          "3"
-CCHMARK                 "9"
-CCLMARK                 "7"
-CH1_SSLB                "DISABLED"
-CH1_SPLBPORTS           "DISABLED"
-CH1_PCSLBPORTS          "DISABLED"
-INT_ALL                 "DISABLED"
-QD_REFCK2CORE           "ENABLED"
-
-
diff --git a/code/ip/sfp_1_125_int.vhd b/code/ip/sfp_1_125_int.vhd
deleted file mode 100644
index df3e4e2..0000000
--- a/code/ip/sfp_1_125_int.vhd
+++ /dev/null
@@ -1,3162 +0,0 @@
-
-                                                                                                         
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
---  CONFIG_FILE : String  := "sfp_1_125_int.txt";
---  QUAD_MODE : String := "SINGLE";
---  CH0_CDR_SRC   : String := "REFCLK_CORE";
---  CH1_CDR_SRC   : String := "REFCLK_CORE";
---  CH2_CDR_SRC   : String := "REFCLK_EXT";
---  CH3_CDR_SRC   : String := "REFCLK_EXT";
---  PLL_SRC   : String := "REFCLK_CORE"
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String;
-  CH1_CDR_SRC   : String;
-  CH2_CDR_SRC   : String;
-  CH3_CDR_SRC   : String;
-  PLL_SRC   : String
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
-  CONFIG_FILE => CONFIG_FILE,
-  QUAD_MODE => QUAD_MODE,
-  CH0_CDR_SRC => CH0_CDR_SRC,
-  CH1_CDR_SRC => CH1_CDR_SRC,
-  CH2_CDR_SRC => CH2_CDR_SRC,
-  CH3_CDR_SRC => CH3_CDR_SRC,
-  PLL_SRC => PLL_SRC
-  )
-port map (
-   HDINN0 => HDINN0,
-   HDINN1 => HDINN1,
-   HDINN2 => HDINN2,
-   HDINN3 => HDINN3,
-   HDINP0 => HDINP0,
-   HDINP1 => HDINP1,
-   HDINP2 => HDINP2,
-   HDINP3 => HDINP3,
-   REFCLKN => REFCLKN,
-   REFCLKP => REFCLKP,
-   CIN11 => CIN11,
-   CIN10 => CIN10,
-   CIN9 => CIN9,
-   CIN8 => CIN8,
-   CIN7 => CIN7,
-   CIN6 => CIN6,
-   CIN5 => CIN5,
-   CIN4 => CIN4,
-   CIN3 => CIN3,
-   CIN2 => CIN2,
-   CIN1 => CIN1,
-   CIN0 => CIN0,
-   CYAWSTN => CYAWSTN,
-   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
-   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
-   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
-   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
-   FF_RXI_CLK_3 => FF_RXI_CLK_3,
-   FF_RXI_CLK_2 => FF_RXI_CLK_2,
-   FF_RXI_CLK_1 => FF_RXI_CLK_1,
-   FF_RXI_CLK_0 => FF_RXI_CLK_0,
-   FF_TX_D_0_0 => FF_TX_D_0_0,
-   FF_TX_D_0_1 => FF_TX_D_0_1,
-   FF_TX_D_0_2 => FF_TX_D_0_2,
-   FF_TX_D_0_3 => FF_TX_D_0_3,
-   FF_TX_D_0_4 => FF_TX_D_0_4,
-   FF_TX_D_0_5 => FF_TX_D_0_5,
-   FF_TX_D_0_6 => FF_TX_D_0_6,
-   FF_TX_D_0_7 => FF_TX_D_0_7,
-   FF_TX_D_0_8 => FF_TX_D_0_8,
-   FF_TX_D_0_9 => FF_TX_D_0_9,
-   FF_TX_D_0_10 => FF_TX_D_0_10,
-   FF_TX_D_0_11 => FF_TX_D_0_11,
-   FF_TX_D_0_12 => FF_TX_D_0_12,
-   FF_TX_D_0_13 => FF_TX_D_0_13,
-   FF_TX_D_0_14 => FF_TX_D_0_14,
-   FF_TX_D_0_15 => FF_TX_D_0_15,
-   FF_TX_D_0_16 => FF_TX_D_0_16,
-   FF_TX_D_0_17 => FF_TX_D_0_17,
-   FF_TX_D_0_18 => FF_TX_D_0_18,
-   FF_TX_D_0_19 => FF_TX_D_0_19,
-   FF_TX_D_0_20 => FF_TX_D_0_20,
-   FF_TX_D_0_21 => FF_TX_D_0_21,
-   FF_TX_D_0_22 => FF_TX_D_0_22,
-   FF_TX_D_0_23 => FF_TX_D_0_23,
-   FF_TX_D_1_0 => FF_TX_D_1_0,
-   FF_TX_D_1_1 => FF_TX_D_1_1,
-   FF_TX_D_1_2 => FF_TX_D_1_2,
-   FF_TX_D_1_3 => FF_TX_D_1_3,
-   FF_TX_D_1_4 => FF_TX_D_1_4,
-   FF_TX_D_1_5 => FF_TX_D_1_5,
-   FF_TX_D_1_6 => FF_TX_D_1_6,
-   FF_TX_D_1_7 => FF_TX_D_1_7,
-   FF_TX_D_1_8 => FF_TX_D_1_8,
-   FF_TX_D_1_9 => FF_TX_D_1_9,
-   FF_TX_D_1_10 => FF_TX_D_1_10,
-   FF_TX_D_1_11 => FF_TX_D_1_11,
-   FF_TX_D_1_12 => FF_TX_D_1_12,
-   FF_TX_D_1_13 => FF_TX_D_1_13,
-   FF_TX_D_1_14 => FF_TX_D_1_14,
-   FF_TX_D_1_15 => FF_TX_D_1_15,
-   FF_TX_D_1_16 => FF_TX_D_1_16,
-   FF_TX_D_1_17 => FF_TX_D_1_17,
-   FF_TX_D_1_18 => FF_TX_D_1_18,
-   FF_TX_D_1_19 => FF_TX_D_1_19,
-   FF_TX_D_1_20 => FF_TX_D_1_20,
-   FF_TX_D_1_21 => FF_TX_D_1_21,
-   FF_TX_D_1_22 => FF_TX_D_1_22,
-   FF_TX_D_1_23 => FF_TX_D_1_23,
-   FF_TX_D_2_0 => FF_TX_D_2_0,
-   FF_TX_D_2_1 => FF_TX_D_2_1,
-   FF_TX_D_2_2 => FF_TX_D_2_2,
-   FF_TX_D_2_3 => FF_TX_D_2_3,
-   FF_TX_D_2_4 => FF_TX_D_2_4,
-   FF_TX_D_2_5 => FF_TX_D_2_5,
-   FF_TX_D_2_6 => FF_TX_D_2_6,
-   FF_TX_D_2_7 => FF_TX_D_2_7,
-   FF_TX_D_2_8 => FF_TX_D_2_8,
-   FF_TX_D_2_9 => FF_TX_D_2_9,
-   FF_TX_D_2_10 => FF_TX_D_2_10,
-   FF_TX_D_2_11 => FF_TX_D_2_11,
-   FF_TX_D_2_12 => FF_TX_D_2_12,
-   FF_TX_D_2_13 => FF_TX_D_2_13,
-   FF_TX_D_2_14 => FF_TX_D_2_14,
-   FF_TX_D_2_15 => FF_TX_D_2_15,
-   FF_TX_D_2_16 => FF_TX_D_2_16,
-   FF_TX_D_2_17 => FF_TX_D_2_17,
-   FF_TX_D_2_18 => FF_TX_D_2_18,
-   FF_TX_D_2_19 => FF_TX_D_2_19,
-   FF_TX_D_2_20 => FF_TX_D_2_20,
-   FF_TX_D_2_21 => FF_TX_D_2_21,
-   FF_TX_D_2_22 => FF_TX_D_2_22,
-   FF_TX_D_2_23 => FF_TX_D_2_23,
-   FF_TX_D_3_0 => FF_TX_D_3_0,
-   FF_TX_D_3_1 => FF_TX_D_3_1,
-   FF_TX_D_3_2 => FF_TX_D_3_2,
-   FF_TX_D_3_3 => FF_TX_D_3_3,
-   FF_TX_D_3_4 => FF_TX_D_3_4,
-   FF_TX_D_3_5 => FF_TX_D_3_5,
-   FF_TX_D_3_6 => FF_TX_D_3_6,
-   FF_TX_D_3_7 => FF_TX_D_3_7,
-   FF_TX_D_3_8 => FF_TX_D_3_8,
-   FF_TX_D_3_9 => FF_TX_D_3_9,
-   FF_TX_D_3_10 => FF_TX_D_3_10,
-   FF_TX_D_3_11 => FF_TX_D_3_11,
-   FF_TX_D_3_12 => FF_TX_D_3_12,
-   FF_TX_D_3_13 => FF_TX_D_3_13,
-   FF_TX_D_3_14 => FF_TX_D_3_14,
-   FF_TX_D_3_15 => FF_TX_D_3_15,
-   FF_TX_D_3_16 => FF_TX_D_3_16,
-   FF_TX_D_3_17 => FF_TX_D_3_17,
-   FF_TX_D_3_18 => FF_TX_D_3_18,
-   FF_TX_D_3_19 => FF_TX_D_3_19,
-   FF_TX_D_3_20 => FF_TX_D_3_20,
-   FF_TX_D_3_21 => FF_TX_D_3_21,
-   FF_TX_D_3_22 => FF_TX_D_3_22,
-   FF_TX_D_3_23 => FF_TX_D_3_23,
-   FF_TXI_CLK_0 => FF_TXI_CLK_0,
-   FF_TXI_CLK_1 => FF_TXI_CLK_1,
-   FF_TXI_CLK_2 => FF_TXI_CLK_2,
-   FF_TXI_CLK_3 => FF_TXI_CLK_3,
-   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
-   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
-   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
-   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
-   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
-   FFC_EI_EN_0 => FFC_EI_EN_0,
-   FFC_EI_EN_1 => FFC_EI_EN_1,
-   FFC_EI_EN_2 => FFC_EI_EN_2,
-   FFC_EI_EN_3 => FFC_EI_EN_3,
-   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
-   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
-   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
-   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
-   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
-   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
-   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
-   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
-   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
-   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
-   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
-   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
-   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
-   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
-   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
-   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
-   FFC_MACRO_RST => FFC_MACRO_RST,
-   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
-   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
-   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
-   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
-   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
-   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
-   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
-   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
-   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
-   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
-   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
-   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
-   FFC_QUAD_RST => FFC_QUAD_RST,
-   FFC_RRST_0 => FFC_RRST_0,
-   FFC_RRST_1 => FFC_RRST_1,
-   FFC_RRST_2 => FFC_RRST_2,
-   FFC_RRST_3 => FFC_RRST_3,
-   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
-   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
-   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
-   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
-   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
-   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
-   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
-   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
-   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
-   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
-   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
-   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
-   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
-   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
-   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
-   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
-   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
-   FFC_TRST => FFC_TRST,
-   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
-   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
-   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
-   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
-   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
-   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
-   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
-   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
-   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
-   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
-   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
-   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
-   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
-   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
-   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
-   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
-   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
-   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
-   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
-   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
-   LDR_CORE2TX_0 => LDR_CORE2TX_0,
-   LDR_CORE2TX_1 => LDR_CORE2TX_1,
-   LDR_CORE2TX_2 => LDR_CORE2TX_2,
-   LDR_CORE2TX_3 => LDR_CORE2TX_3,
-   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
-   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
-   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
-   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
-   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
-   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
-   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
-   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
-   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
-   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
-   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
-   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
-   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
-   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
-   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
-   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
-   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
-   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
-   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
-   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
-   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
-   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
-   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
-   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
-   SCIADDR0 => SCIADDR0,
-   SCIADDR1 => SCIADDR1,
-   SCIADDR2 => SCIADDR2,
-   SCIADDR3 => SCIADDR3,
-   SCIADDR4 => SCIADDR4,
-   SCIADDR5 => SCIADDR5,
-   SCIENAUX => SCIENAUX,
-   SCIENCH0 => SCIENCH0,
-   SCIENCH1 => SCIENCH1,
-   SCIENCH2 => SCIENCH2,
-   SCIENCH3 => SCIENCH3,
-   SCIRD => SCIRD,
-   SCISELAUX => SCISELAUX,
-   SCISELCH0 => SCISELCH0,
-   SCISELCH1 => SCISELCH1,
-   SCISELCH2 => SCISELCH2,
-   SCISELCH3 => SCISELCH3,
-   SCIWDATA0 => SCIWDATA0,
-   SCIWDATA1 => SCIWDATA1,
-   SCIWDATA2 => SCIWDATA2,
-   SCIWDATA3 => SCIWDATA3,
-   SCIWDATA4 => SCIWDATA4,
-   SCIWDATA5 => SCIWDATA5,
-   SCIWDATA6 => SCIWDATA6,
-   SCIWDATA7 => SCIWDATA7,
-   SCIWSTN => SCIWSTN,
-   HDOUTN0 => HDOUTN0,
-   HDOUTN1 => HDOUTN1,
-   HDOUTN2 => HDOUTN2,
-   HDOUTN3 => HDOUTN3,
-   HDOUTP0 => HDOUTP0,
-   HDOUTP1 => HDOUTP1,
-   HDOUTP2 => HDOUTP2,
-   HDOUTP3 => HDOUTP3,
-   COUT19 => COUT19,
-   COUT18 => COUT18,
-   COUT17 => COUT17,
-   COUT16 => COUT16,
-   COUT15 => COUT15,
-   COUT14 => COUT14,
-   COUT13 => COUT13,
-   COUT12 => COUT12,
-   COUT11 => COUT11,
-   COUT10 => COUT10,
-   COUT9 => COUT9,
-   COUT8 => COUT8,
-   COUT7 => COUT7,
-   COUT6 => COUT6,
-   COUT5 => COUT5,
-   COUT4 => COUT4,
-   COUT3 => COUT3,
-   COUT2 => COUT2,
-   COUT1 => COUT1,
-   COUT0 => COUT0,
-   FF_RX_D_0_0 => FF_RX_D_0_0,
-   FF_RX_D_0_1 => FF_RX_D_0_1,
-   FF_RX_D_0_2 => FF_RX_D_0_2,
-   FF_RX_D_0_3 => FF_RX_D_0_3,
-   FF_RX_D_0_4 => FF_RX_D_0_4,
-   FF_RX_D_0_5 => FF_RX_D_0_5,
-   FF_RX_D_0_6 => FF_RX_D_0_6,
-   FF_RX_D_0_7 => FF_RX_D_0_7,
-   FF_RX_D_0_8 => FF_RX_D_0_8,
-   FF_RX_D_0_9 => FF_RX_D_0_9,
-   FF_RX_D_0_10 => FF_RX_D_0_10,
-   FF_RX_D_0_11 => FF_RX_D_0_11,
-   FF_RX_D_0_12 => FF_RX_D_0_12,
-   FF_RX_D_0_13 => FF_RX_D_0_13,
-   FF_RX_D_0_14 => FF_RX_D_0_14,
-   FF_RX_D_0_15 => FF_RX_D_0_15,
-   FF_RX_D_0_16 => FF_RX_D_0_16,
-   FF_RX_D_0_17 => FF_RX_D_0_17,
-   FF_RX_D_0_18 => FF_RX_D_0_18,
-   FF_RX_D_0_19 => FF_RX_D_0_19,
-   FF_RX_D_0_20 => FF_RX_D_0_20,
-   FF_RX_D_0_21 => FF_RX_D_0_21,
-   FF_RX_D_0_22 => FF_RX_D_0_22,
-   FF_RX_D_0_23 => FF_RX_D_0_23,
-   FF_RX_D_1_0 => FF_RX_D_1_0,
-   FF_RX_D_1_1 => FF_RX_D_1_1,
-   FF_RX_D_1_2 => FF_RX_D_1_2,
-   FF_RX_D_1_3 => FF_RX_D_1_3,
-   FF_RX_D_1_4 => FF_RX_D_1_4,
-   FF_RX_D_1_5 => FF_RX_D_1_5,
-   FF_RX_D_1_6 => FF_RX_D_1_6,
-   FF_RX_D_1_7 => FF_RX_D_1_7,
-   FF_RX_D_1_8 => FF_RX_D_1_8,
-   FF_RX_D_1_9 => FF_RX_D_1_9,
-   FF_RX_D_1_10 => FF_RX_D_1_10,
-   FF_RX_D_1_11 => FF_RX_D_1_11,
-   FF_RX_D_1_12 => FF_RX_D_1_12,
-   FF_RX_D_1_13 => FF_RX_D_1_13,
-   FF_RX_D_1_14 => FF_RX_D_1_14,
-   FF_RX_D_1_15 => FF_RX_D_1_15,
-   FF_RX_D_1_16 => FF_RX_D_1_16,
-   FF_RX_D_1_17 => FF_RX_D_1_17,
-   FF_RX_D_1_18 => FF_RX_D_1_18,
-   FF_RX_D_1_19 => FF_RX_D_1_19,
-   FF_RX_D_1_20 => FF_RX_D_1_20,
-   FF_RX_D_1_21 => FF_RX_D_1_21,
-   FF_RX_D_1_22 => FF_RX_D_1_22,
-   FF_RX_D_1_23 => FF_RX_D_1_23,
-   FF_RX_D_2_0 => FF_RX_D_2_0,
-   FF_RX_D_2_1 => FF_RX_D_2_1,
-   FF_RX_D_2_2 => FF_RX_D_2_2,
-   FF_RX_D_2_3 => FF_RX_D_2_3,
-   FF_RX_D_2_4 => FF_RX_D_2_4,
-   FF_RX_D_2_5 => FF_RX_D_2_5,
-   FF_RX_D_2_6 => FF_RX_D_2_6,
-   FF_RX_D_2_7 => FF_RX_D_2_7,
-   FF_RX_D_2_8 => FF_RX_D_2_8,
-   FF_RX_D_2_9 => FF_RX_D_2_9,
-   FF_RX_D_2_10 => FF_RX_D_2_10,
-   FF_RX_D_2_11 => FF_RX_D_2_11,
-   FF_RX_D_2_12 => FF_RX_D_2_12,
-   FF_RX_D_2_13 => FF_RX_D_2_13,
-   FF_RX_D_2_14 => FF_RX_D_2_14,
-   FF_RX_D_2_15 => FF_RX_D_2_15,
-   FF_RX_D_2_16 => FF_RX_D_2_16,
-   FF_RX_D_2_17 => FF_RX_D_2_17,
-   FF_RX_D_2_18 => FF_RX_D_2_18,
-   FF_RX_D_2_19 => FF_RX_D_2_19,
-   FF_RX_D_2_20 => FF_RX_D_2_20,
-   FF_RX_D_2_21 => FF_RX_D_2_21,
-   FF_RX_D_2_22 => FF_RX_D_2_22,
-   FF_RX_D_2_23 => FF_RX_D_2_23,
-   FF_RX_D_3_0 => FF_RX_D_3_0,
-   FF_RX_D_3_1 => FF_RX_D_3_1,
-   FF_RX_D_3_2 => FF_RX_D_3_2,
-   FF_RX_D_3_3 => FF_RX_D_3_3,
-   FF_RX_D_3_4 => FF_RX_D_3_4,
-   FF_RX_D_3_5 => FF_RX_D_3_5,
-   FF_RX_D_3_6 => FF_RX_D_3_6,
-   FF_RX_D_3_7 => FF_RX_D_3_7,
-   FF_RX_D_3_8 => FF_RX_D_3_8,
-   FF_RX_D_3_9 => FF_RX_D_3_9,
-   FF_RX_D_3_10 => FF_RX_D_3_10,
-   FF_RX_D_3_11 => FF_RX_D_3_11,
-   FF_RX_D_3_12 => FF_RX_D_3_12,
-   FF_RX_D_3_13 => FF_RX_D_3_13,
-   FF_RX_D_3_14 => FF_RX_D_3_14,
-   FF_RX_D_3_15 => FF_RX_D_3_15,
-   FF_RX_D_3_16 => FF_RX_D_3_16,
-   FF_RX_D_3_17 => FF_RX_D_3_17,
-   FF_RX_D_3_18 => FF_RX_D_3_18,
-   FF_RX_D_3_19 => FF_RX_D_3_19,
-   FF_RX_D_3_20 => FF_RX_D_3_20,
-   FF_RX_D_3_21 => FF_RX_D_3_21,
-   FF_RX_D_3_22 => FF_RX_D_3_22,
-   FF_RX_D_3_23 => FF_RX_D_3_23,
-   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
-   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
-   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
-   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
-   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
-   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
-   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
-   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
-   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
-   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
-   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
-   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
-   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
-   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
-   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
-   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
-   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
-   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
-   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
-   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
-   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
-   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
-   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
-   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
-   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
-   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
-   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
-   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
-   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
-   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
-   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
-   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
-   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
-   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
-   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
-   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
-   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
-   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
-   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
-   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
-   FFS_PLOL => FFS_PLOL,
-   FFS_RLOL_0 => FFS_RLOL_0,
-   FFS_RLOL_1 => FFS_RLOL_1,
-   FFS_RLOL_2 => FFS_RLOL_2,
-   FFS_RLOL_3 => FFS_RLOL_3,
-   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
-   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
-   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
-   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
-   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
-   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
-   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
-   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
-   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
-   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
-   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
-   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
-   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
-   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
-   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
-   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
-   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
-   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
-   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
-   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
-   PCIE_RXVALID_0 => PCIE_RXVALID_0,
-   PCIE_RXVALID_1 => PCIE_RXVALID_1,
-   PCIE_RXVALID_2 => PCIE_RXVALID_2,
-   PCIE_RXVALID_3 => PCIE_RXVALID_3,
-   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
-   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
-   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
-   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
-   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
-   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
-   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
-   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
-   LDR_RX2CORE_0 => LDR_RX2CORE_0,
-   LDR_RX2CORE_1 => LDR_RX2CORE_1,
-   LDR_RX2CORE_2 => LDR_RX2CORE_2,
-   LDR_RX2CORE_3 => LDR_RX2CORE_3,
-   REFCK2CORE => REFCK2CORE,
-   SCIINT => SCIINT,
-   SCIRDATA0 => SCIRDATA0,
-   SCIRDATA1 => SCIRDATA1,
-   SCIRDATA2 => SCIRDATA2,
-   SCIRDATA3 => SCIRDATA3,
-   SCIRDATA4 => SCIRDATA4,
-   SCIRDATA5 => SCIRDATA5,
-   SCIRDATA6 => SCIRDATA6,
-   SCIRDATA7 => SCIRDATA7,
-   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
-   REFCLK_TO_NQ => REFCLK_TO_NQ
-   );
-
-end PCSD_arch;
-
---synopsys translate_on
-
---THIS MODULE IS INSTANTIATED PER RX CHANNEL
---Reset Sequence Generator
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-                                                                                              
-entity sfp_1_125_intrx_reset_sm is
-generic (count_index: integer :=18);
-port (
-   rst_n       : in std_logic;
-   refclkdiv2        : in std_logic;
-   tx_pll_lol_qd_s   : in std_logic;
-   rx_serdes_rst_ch_c: out std_logic;
-   rx_cdr_lol_ch_s   : in std_logic;
-   rx_los_low_ch_s   : in std_logic;
-   rx_pcs_rst_ch_c   : out std_logic
-);
-end sfp_1_125_intrx_reset_sm ;
-                                                                                              
-architecture rx_reset_sm_arch of sfp_1_125_intrx_reset_sm is
-                                                                                              
-type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
-                                                                                              
-signal   cs:      statetype;  -- current state of lsm
-signal   ns:      statetype;  -- next state of lsm
-attribute syn_encoding : string;
-attribute syn_encoding of cs : signal is "safe";
-attribute syn_encoding of ns : signal is "safe";
-                                                                                              
-signal   tx_pll_lol_qd_s_int: std_logic;
-signal   rx_los_low_int:         std_logic;
-signal   plol_los_int:        std_logic;
-signal   rx_lol_los  :  std_logic;
-signal   rx_lol_los_int:      std_logic;
-signal   rx_lol_los_del:      std_logic;
-signal   rx_pcs_rst_ch_c_int: std_logic;
-signal   rx_serdes_rst_ch_c_int: std_logic;
-                                                                                              
-signal   reset_timer1:  std_logic;
-signal   reset_timer2:  std_logic;
-                                                                                              
-signal   counter1:   std_logic_vector(1 downto 0);
-signal   TIMER1:  std_logic;
-                                                                                              
-signal   counter2: std_logic_vector(18 downto 0);
-signal   TIMER2   : std_logic;
-signal   rstn_m1:       std_logic;                                           
-signal   rstn_m2:       std_logic;                                           
-signal   sync_rst_n:       std_logic;                                                                                                                                      
-begin
-
-process (refclkdiv2, rst_n)
-begin
-   if rst_n = '0' then
-      rstn_m1 <= '0';
-      rstn_m2 <= '0';
-   else if rising_edge(refclkdiv2) then
-      rstn_m1 <= '1';
-      rstn_m2 <= rstn_m1;
-   end if;
-   end if;
-end process;
-
-   sync_rst_n <= rstn_m2;                   
-                                                                                              
-rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
-                                                                                              
-process(refclkdiv2, sync_rst_n)
-begin
-   if  sync_rst_n = '0' then
-         cs <= WAIT_FOR_PLOL;
-         rx_lol_los_int <= '1';
-         rx_lol_los_del <= '1';
-         tx_pll_lol_qd_s_int <= '1';
-         rx_pcs_rst_ch_c <= '1';
-         rx_serdes_rst_ch_c <= '0';
-         rx_los_low_int <= '1';
-      else if rising_edge(refclkdiv2) then
-         cs <= ns;
-         rx_lol_los_del <= rx_lol_los;
-         rx_lol_los_int <= rx_lol_los_del;
-         tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
-         rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
-         rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
-         rx_los_low_int <= rx_los_low_ch_s;
-      end if;
-   end if;
-end process;
-                                                                                              
---TIMER1 = 3NS;
---Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
---A 1 bit counter  counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
-                                                                                              
-process(refclkdiv2, reset_timer1)
-begin
-   if rising_edge(refclkdiv2) then
-      if reset_timer1 = '1' then
-         counter1 <= "00";
-         TIMER1 <= '0';
-      else
-         if counter1(1) = '1' then
-            TIMER1 <='1';
-         else
-            TIMER1 <='0';
-            counter1 <= counter1 + 1 ;
-         end if;
-      end if;
-   end if;
-end process;
-                                                                                              
---TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
---An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-                                                                                              
-process(refclkdiv2, reset_timer2)
-begin
-   if rising_edge(refclkdiv2) then
-      if reset_timer2 = '1' then
-         counter2 <= "0000000000000000000";
-         TIMER2 <= '0';
-      else
-         if counter2(count_index) = '1' then
-            TIMER2 <='1';
-         else
-            TIMER2 <='0';
-            counter2 <= counter2 + 1 ;
-         end if;
-      end if;
-   end if;
-end process;
-                                                                                              
-                                                                                              
-process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
-begin
-      reset_timer1 <= '0';
-      reset_timer2 <= '0';
-                                                                                              
-   case cs is
-      when WAIT_FOR_PLOL =>
-         rx_pcs_rst_ch_c_int <= '1';
-         rx_serdes_rst_ch_c_int <= '0';
-         if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then  --Also make sure A Signal
-            ns <= WAIT_FOR_PLOL;             --is Present prior to moving to the next
-         else
-            ns <= RX_SERDES_RESET;
-            end if;
-                                                                                              
-       when RX_SERDES_RESET =>
-         rx_pcs_rst_ch_c_int <= '1';
-         rx_serdes_rst_ch_c_int <= '1';
-         reset_timer1 <= '1';
-            ns <= WAIT_FOR_TIMER1;
-                                                                                              
-                                                                                              
-      when WAIT_FOR_TIMER1 =>
-         rx_pcs_rst_ch_c_int <= '1';
-         rx_serdes_rst_ch_c_int <= '1';
-         if TIMER1 = '1' then
-            ns <= CHECK_LOL_LOS;
-         else
-            ns <= WAIT_FOR_TIMER1;
-            end if;
-                                                                                              
-      when CHECK_LOL_LOS =>
-         rx_pcs_rst_ch_c_int <= '1';
-         rx_serdes_rst_ch_c_int <= '0';
-         reset_timer2 <= '1';
-            ns <= WAIT_FOR_TIMER2;
-                                                                                              
-      when WAIT_FOR_TIMER2 =>
-         rx_pcs_rst_ch_c_int <= '1';
-         rx_serdes_rst_ch_c_int <= '0';
-         if rx_lol_los_int = rx_lol_los_del then   --NO RISING OR FALLING EDGES
-            if TIMER2 = '1' then
-               if rx_lol_los_int = '1' then
-                  ns <= WAIT_FOR_PLOL;
-               else
-                  ns <= NORMAL;
-               end if;
-            else
-               ns <= WAIT_FOR_TIMER2;
-            end if;
-         else
-               ns <= CHECK_LOL_LOS;    --RESET TIMER2
-         end if;
-                                                                                              
-      when NORMAL =>
-         rx_pcs_rst_ch_c_int <= '0';
-         rx_serdes_rst_ch_c_int <= '0';
-         if rx_lol_los_int = '1' then
-            ns <= WAIT_FOR_PLOL;
-         else
-            ns <= NORMAL;
-         end if;
-                                                                                              
-      when others =>
-         ns <= WAIT_FOR_PLOL;
-                                                                                              
-      end case;
-                                                                                              
-end process;
-                                                                                              
-                                                                                              
-end rx_reset_sm_arch;
-
---THIS MODULE IS INSTANTIATED PER TX  QUAD
---TX Reset Sequence state machine--
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-                                                                                              
-entity sfp_1_125_inttx_reset_sm is
-generic (count_index: integer :=18);
-port (
-   rst_n          : in std_logic;
-   refclkdiv2      : in std_logic;
-   tx_pll_lol_qd_s : in std_logic;
-   rst_qd_c    : out std_logic;
-   tx_pcs_rst_ch_c : out std_logic
-   );
-end sfp_1_125_inttx_reset_sm;
-                                                                                              
-architecture tx_reset_sm_arch of sfp_1_125_inttx_reset_sm is
-                                                                                              
-type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
-                                                                                              
-signal   cs:      statetype;  -- current state of lsm
-signal   ns:      statetype;  -- next state of lsm
-attribute syn_encoding : string;
-attribute syn_encoding of cs : signal is "safe";
-attribute syn_encoding of ns : signal is "safe";
-                                                                                              
-signal   tx_pll_lol_qd_s_int  : std_logic;
-signal   tx_pcs_rst_ch_c_int  : std_logic_vector(3 downto 0);
-signal   rst_qd_c_int      : std_logic;
-                                                                                              
-signal   reset_timer1:  std_logic;
-signal   reset_timer2:  std_logic;
-                                                                                              
-signal   counter1:      std_logic_vector(2 downto 0);
-signal   TIMER1:        std_logic;
-                                                                                              
-signal   counter2:      std_logic_vector(18 downto 0);
-signal   TIMER2:        std_logic;
-
-signal   rstn_m1:       std_logic;                                                                                  
-signal   rstn_m2:       std_logic;                                                                                              
-signal   sync_rst_n:       std_logic;                                                                                              
-begin
-
-process (refclkdiv2, rst_n)
-begin
-   if rst_n = '0' then
-      rstn_m1 <= '0';
-      rstn_m2 <= '0';
-   else if rising_edge(refclkdiv2) then
-      rstn_m1 <= '1';
-      rstn_m2 <= rstn_m1;
-   end if;
-   end if;
-end process;
-   
-   sync_rst_n <= rstn_m2;                                                                                           
-process (refclkdiv2, sync_rst_n)
-begin
-   if sync_rst_n = '0' then
-      cs <= QUAD_RESET;
-      tx_pll_lol_qd_s_int <= '1';
-      tx_pcs_rst_ch_c <= '1';
-      rst_qd_c <= '1';
-   else if rising_edge(refclkdiv2) then
-      cs <= ns;
-      tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
-      tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
-      rst_qd_c <= rst_qd_c_int;
-   end if;
-   end if;
-end process;
---TIMER1 = 20ns;
---Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
--- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
-                                                                                              
-                                                                                              
-process (refclkdiv2, reset_timer1)
-begin
-   if rising_edge(refclkdiv2) then
-      if reset_timer1 = '1' then
-         counter1 <= "000";
-         TIMER1 <= '0';
-      else
-         if counter1(2) = '1' then
-            TIMER1 <= '1';
-         else
-            TIMER1 <='0';
-            counter1 <= counter1 + 1 ;
-         end if;
-      end if;
-   end if;
-end process;
-                                                                                              
-                                                                                              
---TIMER2 = 1,400,000 UI;
---WORST CASE CYCLES is with smallest multipier factor.
--- This would be with X8 clock multiplier in DIV2 mode
--- IN this casse, 1 UI = 2/8 REFCLK  CYCLES = 1/8 REFCLKDIV2 CYCLES
--- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
--- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-                                                                                              
-                                                                                              
-process(refclkdiv2, reset_timer2)
-begin
-   if rising_edge(refclkdiv2) then
-      if reset_timer2 = '1' then
-         counter2 <= "0000000000000000000";
-         TIMER2 <= '0';
-      else
-         if counter2(count_index) = '1' then
-            TIMER2 <='1';
-         else
-            TIMER2 <='0';
-            counter2 <= counter2 + 1 ;
-         end if;
-      end if;
-   end if;
-end process;
-                                                                                              
-process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
-begin
-                                                                                              
-      reset_timer1 <= '0';
-      reset_timer2 <= '0';
-                                                                                              
-   case cs is
-                                                                                              
-      when QUAD_RESET   =>
-      tx_pcs_rst_ch_c_int <= "1111";
-      rst_qd_c_int <= '1';
-      reset_timer1 <= '1';
-         ns <= WAIT_FOR_TIMER1;
-                                                                                              
-      when WAIT_FOR_TIMER1 =>
-      tx_pcs_rst_ch_c_int <= "1111";
-      rst_qd_c_int <= '1';
-      if TIMER1 = '1' then
-         ns <= CHECK_PLOL;
-      else
-         ns <= WAIT_FOR_TIMER1;
-         end if;
-                                                                                              
-      when CHECK_PLOL   =>
-      tx_pcs_rst_ch_c_int <= "1111";
-      rst_qd_c_int <= '0';
-      reset_timer2 <= '1';
-         ns <= WAIT_FOR_TIMER2;
-                                                                                              
-      when WAIT_FOR_TIMER2 =>
-      tx_pcs_rst_ch_c_int <= "1111";
-      rst_qd_c_int <= '0';
-      if TIMER2 = '1' then
-         if tx_pll_lol_qd_s_int = '1' then
-            ns <= QUAD_RESET;
-         else
-            ns <= NORMAL;
-         end if;
-      else
-            ns <= WAIT_FOR_TIMER2;
-            end if;
-                                                                                              
-   when NORMAL =>
-      tx_pcs_rst_ch_c_int <= "0000";
-      rst_qd_c_int <= '0';
-      if tx_pll_lol_qd_s_int = '1' then
-         ns <= QUAD_RESET;
-      else
-         ns <= NORMAL;
-         end if;
-                                                                                              
-   when others =>
-      ns <=    QUAD_RESET;
-                                                                                              
-   end case;
-                                                                                              
-end process;
-                                                                                              
-end tx_reset_sm_arch;
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity sfp_1_125_int is
-   GENERIC (USER_CONFIG_FILE    :  String := "sfp_1_125_int.txt");
- port (
-------------------
--- CH0 --
--- CH1 --
-    hdinp_ch1, hdinn_ch1    :   in std_logic;
-    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
-    sci_sel_ch1    :   in std_logic;
-    rxiclk_ch1    :   in std_logic;
-    txiclk_ch1    :   in std_logic;
-    rx_full_clk_ch1   :   out std_logic;
-    rx_half_clk_ch1   :   out std_logic;
-    tx_full_clk_ch1   :   out std_logic;
-    tx_half_clk_ch1   :   out std_logic;
-    fpga_rxrefclk_ch1    :   in std_logic;
-    txdata_ch1    :   in std_logic_vector (15 downto 0);
-    tx_k_ch1    :   in std_logic_vector (1 downto 0);
-    tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
-    tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
-    rxdata_ch1   :   out std_logic_vector (15 downto 0);
-    rx_k_ch1   :   out std_logic_vector (1 downto 0);
-    rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
-    rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
-    sb_felb_ch1_c    :   in std_logic;
-    sb_felb_rst_ch1_c    :   in std_logic;
-    tx_pwrup_ch1_c    :   in std_logic;
-    rx_pwrup_ch1_c    :   in std_logic;
-    rx_los_low_ch1_s   :   out std_logic;
-    lsm_status_ch1_s   :   out std_logic;
-    rx_cdr_lol_ch1_s   :   out std_logic;
-    tx_div2_mode_ch1_c   : in std_logic;
-    rx_div2_mode_ch1_c   : in std_logic;
--- CH2 --
--- CH3 --
----- Miscillaneous ports
-    sci_wrdata    :   in std_logic_vector (7 downto 0);
-    sci_addr    :   in std_logic_vector (5 downto 0);
-    sci_rddata   :   out std_logic_vector (7 downto 0);
-    sci_sel_quad    :   in std_logic;
-    sci_rd    :   in std_logic;
-    sci_wrn    :   in std_logic;
-    fpga_txrefclk  :   in std_logic;
-    tx_serdes_rst_c    :   in std_logic;
-    tx_pll_lol_qd_s   :   out std_logic;
-    refclk2fpga   :   out std_logic;
-    rst_n      :   in std_logic;
-    serdes_rst_qd_c    :   in std_logic);
-
-end sfp_1_125_int;
-
-
-architecture sfp_1_125_int_arch of sfp_1_125_int is
-
-component VLO
-port (
-   Z : out std_logic);
-end component;
-
-component VHI
-port (
-   Z : out std_logic);
-end component;
-
-component sfp_1_125_intrx_reset_sm
-generic (count_index: integer :=18);
-port (
-   rst_n       : in std_logic;
-   refclkdiv2        : in std_logic;
-   tx_pll_lol_qd_s   : in std_logic;
-   rx_serdes_rst_ch_c: out std_logic;
-   rx_cdr_lol_ch_s   : in std_logic;
-   rx_los_low_ch_s   : in std_logic;
-   rx_pcs_rst_ch_c   : out std_logic
-);
-end component ;
-
-component sfp_1_125_inttx_reset_sm
-generic (count_index: integer :=18);
-port (
-   rst_n          : in std_logic;
-   refclkdiv2      : in std_logic;
-   tx_pll_lol_qd_s : in std_logic;
-   rst_qd_c    : out std_logic;
-   tx_pcs_rst_ch_c : out std_logic
-   );
-end component;
-
-component PCSD
---synopsys translate_off
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
-  );
---synopsys translate_on
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-   attribute CONFIG_FILE: string;
-   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
-   attribute QUAD_MODE: string;
-   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
-   attribute PLL_SRC: string;
-   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH1_CDR_SRC: string;
-   attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_REFCK2CORE: string;
-   attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "125.0";
-   attribute black_box_pad_pin: string;
-   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal    tx_full_clk_ch1_sig   :   std_logic;
-
-signal    refclk2fpga_sig  :   std_logic;
-signal    tx_pll_lol_qd_sig  :   std_logic;
-signal    rx_los_low_ch0_sig  :   std_logic;
-signal    rx_los_low_ch1_sig  :   std_logic;
-signal    rx_los_low_ch2_sig  :   std_logic;
-signal    rx_los_low_ch3_sig  :   std_logic;
-signal    rx_cdr_lol_ch0_sig  :   std_logic;
-signal    rx_cdr_lol_ch1_sig  :   std_logic;
-signal    rx_cdr_lol_ch2_sig  :   std_logic;
-signal    rx_cdr_lol_ch3_sig  :   std_logic;
-
-signal    rx_serdes_rst_ch1_c  : std_logic;
-signal    rx_pcs_rst_ch1_c  : std_logic;
-
--- reset sequence for rx
-signal    refclkdiv2_rx_ch1  :   std_logic;
-
-signal    refclkdiv2_tx_ch  :   std_logic;
-signal    tx_pcs_rst_ch_c   :   std_logic;
-signal    rst_qd_c   :   std_logic;
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
-  refclk2fpga <= refclk2fpga_sig;
-    rx_los_low_ch1_s <= rx_los_low_ch1_sig;
-    rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
-  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
-  tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
-  generic map (CONFIG_FILE => USER_CONFIG_FILE,
-               QUAD_MODE => "SINGLE",
-               CH1_CDR_SRC => "REFCLK_CORE",
-               PLL_SRC  => "REFCLK_CORE"
-  )
---synopsys translate_on
-port map  (
-  REFCLKP => fpsc_vlo,
-  REFCLKN => fpsc_vlo,
-
------ CH0 -----
-  HDOUTP0 => open,
-  HDOUTN0 => open,
-  HDINP0 => fpsc_vlo,
-  HDINN0 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
-  PCIE_RXPOLARITY_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_1 => fpsc_vlo,
-  PCIE_RXVALID_0 => open,
-  PCIE_PHYSTATUS_0 => open,
-  SCISELCH0 => fpsc_vlo,
-  SCIENCH0 => fpsc_vlo,
-  FF_RXI_CLK_0 => fpsc_vlo,
-  FF_TXI_CLK_0 => fpsc_vlo,
-  FF_EBRD_CLK_0 => fpsc_vlo,
-  FF_RX_F_CLK_0 => open,
-  FF_RX_H_CLK_0 => open,
-  FF_TX_F_CLK_0 => open,
-  FF_TX_H_CLK_0 => open,
-  FFC_CK_CORE_RX_0 => fpsc_vlo,
-  FF_TX_D_0_0 => fpsc_vlo,
-  FF_TX_D_0_1 => fpsc_vlo,
-  FF_TX_D_0_2 => fpsc_vlo,
-  FF_TX_D_0_3 => fpsc_vlo,
-  FF_TX_D_0_4 => fpsc_vlo,
-  FF_TX_D_0_5 => fpsc_vlo,
-  FF_TX_D_0_6 => fpsc_vlo,
-  FF_TX_D_0_7 => fpsc_vlo,
-  FF_TX_D_0_8 => fpsc_vlo,
-  FF_TX_D_0_9 => fpsc_vlo,
-  FF_TX_D_0_10 => fpsc_vlo,
-  FF_TX_D_0_11 => fpsc_vlo,
-  FF_TX_D_0_12 => fpsc_vlo,
-  FF_TX_D_0_13 => fpsc_vlo,
-  FF_TX_D_0_14 => fpsc_vlo,
-  FF_TX_D_0_15 => fpsc_vlo,
-  FF_TX_D_0_16 => fpsc_vlo,
-  FF_TX_D_0_17 => fpsc_vlo,
-  FF_TX_D_0_18 => fpsc_vlo,
-  FF_TX_D_0_19 => fpsc_vlo,
-  FF_TX_D_0_20 => fpsc_vlo,
-  FF_TX_D_0_21 => fpsc_vlo,
-  FF_TX_D_0_22 => fpsc_vlo,
-  FF_TX_D_0_23 => fpsc_vlo,
-  FF_RX_D_0_0 => open,
-  FF_RX_D_0_1 => open,
-  FF_RX_D_0_2 => open,
-  FF_RX_D_0_3 => open,
-  FF_RX_D_0_4 => open,
-  FF_RX_D_0_5 => open,
-  FF_RX_D_0_6 => open,
-  FF_RX_D_0_7 => open,
-  FF_RX_D_0_8 => open,
-  FF_RX_D_0_9 => open,
-  FF_RX_D_0_10 => open,
-  FF_RX_D_0_11 => open,
-  FF_RX_D_0_12 => open,
-  FF_RX_D_0_13 => open,
-  FF_RX_D_0_14 => open,
-  FF_RX_D_0_15 => open,
-  FF_RX_D_0_16 => open,
-  FF_RX_D_0_17 => open,
-  FF_RX_D_0_18 => open,
-  FF_RX_D_0_19 => open,
-  FF_RX_D_0_20 => open,
-  FF_RX_D_0_21 => open,
-  FF_RX_D_0_22 => open,
-  FF_RX_D_0_23 => open,
-
-  FFC_RRST_0 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_0 => fpsc_vlo,
-  FFC_PFIFO_CLR_0 => fpsc_vlo,
-  FFC_SB_INV_RX_0 => fpsc_vlo,
-  FFC_PCIE_CT_0 => fpsc_vlo,
-  FFC_PCI_DET_EN_0 => fpsc_vlo,
-  FFC_FB_LOOPBACK_0 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
-  FFC_EI_EN_0 => fpsc_vlo,
-  FFC_LANE_TX_RST_0 => fpsc_vlo,
-  FFC_TXPWDNB_0 => fpsc_vlo,
-  FFC_LANE_RX_RST_0 => fpsc_vlo,
-  FFC_RXPWDNB_0 => fpsc_vlo,
-  FFS_RLOS_LO_0 => open,
-  FFS_RLOS_HI_0 => open,
-  FFS_PCIE_CON_0 => open,
-  FFS_PCIE_DONE_0 => open,
-  FFS_LS_SYNC_STATUS_0 => open,
-  FFS_CC_OVERRUN_0 => open,
-  FFS_CC_UNDERRUN_0 => open,
-  FFS_SKP_ADDED_0 => open,
-  FFS_SKP_DELETED_0 => open,
-  FFS_RLOL_0 => open,
-  FFS_RXFBFIFO_ERROR_0 => open,
-  FFS_TXFBFIFO_ERROR_0 => open,
-  LDR_CORE2TX_0 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
-  LDR_RX2CORE_0 => open,
-  FFS_CDR_TRAIN_DONE_0 => open,
-  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
-  FFC_RATE_MODE_TX_0 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
-  FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
-  HDOUTP1 => hdoutp_ch1,
-  HDOUTN1 => hdoutn_ch1,
-  HDINP1 => hdinp_ch1,
-  HDINN1 => hdinn_ch1,
-  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
-  PCIE_RXPOLARITY_1 => fpsc_vlo,
-  PCIE_POWERDOWN_1_0 => fpsc_vlo,
-  PCIE_POWERDOWN_1_1 => fpsc_vlo,
-  PCIE_RXVALID_1 => open,
-  PCIE_PHYSTATUS_1 => open,
-  SCISELCH1 => sci_sel_ch1,
-  SCIENCH1 => fpsc_vhi,
-  FF_RXI_CLK_1 => rxiclk_ch1,
-  FF_TXI_CLK_1 => txiclk_ch1,
-  FF_EBRD_CLK_1 => fpsc_vlo,
-  FF_RX_F_CLK_1 => rx_full_clk_ch1,
-  FF_RX_H_CLK_1 => rx_half_clk_ch1,
-  FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
-  FF_TX_H_CLK_1 => tx_half_clk_ch1,
-  FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
-  FF_TX_D_1_0 => txdata_ch1(0),
-  FF_TX_D_1_1 => txdata_ch1(1),
-  FF_TX_D_1_2 => txdata_ch1(2),
-  FF_TX_D_1_3 => txdata_ch1(3),
-  FF_TX_D_1_4 => txdata_ch1(4),
-  FF_TX_D_1_5 => txdata_ch1(5),
-  FF_TX_D_1_6 => txdata_ch1(6),
-  FF_TX_D_1_7 => txdata_ch1(7),
-  FF_TX_D_1_8 => tx_k_ch1(0),
-  FF_TX_D_1_9 => tx_force_disp_ch1(0),
-  FF_TX_D_1_10 => tx_disp_sel_ch1(0),
-  FF_TX_D_1_11 => fpsc_vlo,
-  FF_TX_D_1_12 => txdata_ch1(8),
-  FF_TX_D_1_13 => txdata_ch1(9),
-  FF_TX_D_1_14 => txdata_ch1(10),
-  FF_TX_D_1_15 => txdata_ch1(11),
-  FF_TX_D_1_16 => txdata_ch1(12),
-  FF_TX_D_1_17 => txdata_ch1(13),
-  FF_TX_D_1_18 => txdata_ch1(14),
-  FF_TX_D_1_19 => txdata_ch1(15),
-  FF_TX_D_1_20 => tx_k_ch1(1),
-  FF_TX_D_1_21 => tx_force_disp_ch1(1),
-  FF_TX_D_1_22 => tx_disp_sel_ch1(1),
-  FF_TX_D_1_23 => fpsc_vlo,
-  FF_RX_D_1_0 => rxdata_ch1(0),
-  FF_RX_D_1_1 => rxdata_ch1(1),
-  FF_RX_D_1_2 => rxdata_ch1(2),
-  FF_RX_D_1_3 => rxdata_ch1(3),
-  FF_RX_D_1_4 => rxdata_ch1(4),
-  FF_RX_D_1_5 => rxdata_ch1(5),
-  FF_RX_D_1_6 => rxdata_ch1(6),
-  FF_RX_D_1_7 => rxdata_ch1(7),
-  FF_RX_D_1_8 => rx_k_ch1(0),
-  FF_RX_D_1_9 => rx_disp_err_ch1(0),
-  FF_RX_D_1_10 => rx_cv_err_ch1(0),
-  FF_RX_D_1_11 => open,
-  FF_RX_D_1_12 => rxdata_ch1(8),
-  FF_RX_D_1_13 => rxdata_ch1(9),
-  FF_RX_D_1_14 => rxdata_ch1(10),
-  FF_RX_D_1_15 => rxdata_ch1(11),
-  FF_RX_D_1_16 => rxdata_ch1(12),
-  FF_RX_D_1_17 => rxdata_ch1(13),
-  FF_RX_D_1_18 => rxdata_ch1(14),
-  FF_RX_D_1_19 => rxdata_ch1(15),
-  FF_RX_D_1_20 => rx_k_ch1(1),
-  FF_RX_D_1_21 => rx_disp_err_ch1(1),
-  FF_RX_D_1_22 => rx_cv_err_ch1(1),
-  FF_RX_D_1_23 => open,
-
-  FFC_RRST_1 => rx_serdes_rst_ch1_c,
-  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
-  FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
-  FFC_SB_INV_RX_1 => fpsc_vlo,
-  FFC_PCIE_CT_1 => fpsc_vlo,
-  FFC_PCI_DET_EN_1 => fpsc_vlo,
-  FFC_FB_LOOPBACK_1 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
-  FFC_EI_EN_1 => fpsc_vlo,
-  FFC_LANE_TX_RST_1 => tx_pcs_rst_ch_c,
-  FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
-  FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
-  FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
-  FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
-  FFS_RLOS_HI_1 => open,
-  FFS_PCIE_CON_1 => open,
-  FFS_PCIE_DONE_1 => open,
-  FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
-  FFS_CC_OVERRUN_1 => open,
-  FFS_CC_UNDERRUN_1 => open,
-  FFS_SKP_ADDED_1 => open,
-  FFS_SKP_DELETED_1 => open,
-  FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
-  FFS_RXFBFIFO_ERROR_1 => open,
-  FFS_TXFBFIFO_ERROR_1 => open,
-  LDR_CORE2TX_1 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
-  LDR_RX2CORE_1 => open,
-  FFS_CDR_TRAIN_DONE_1 => open,
-  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
-  FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
-  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
-  FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
-
------ CH2 -----
-  HDOUTP2 => open,
-  HDOUTN2 => open,
-  HDINP2 => fpsc_vlo,
-  HDINN2 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
-  PCIE_RXPOLARITY_2 => fpsc_vlo,
-  PCIE_POWERDOWN_2_0 => fpsc_vlo,
-  PCIE_POWERDOWN_2_1 => fpsc_vlo,
-  PCIE_RXVALID_2 => open,
-  PCIE_PHYSTATUS_2 => open,
-  SCISELCH2 => fpsc_vlo,
-  SCIENCH2 => fpsc_vlo,
-  FF_RXI_CLK_2 => fpsc_vlo,
-  FF_TXI_CLK_2 => fpsc_vlo,
-  FF_EBRD_CLK_2 => fpsc_vlo,
-  FF_RX_F_CLK_2 => open,
-  FF_RX_H_CLK_2 => open,
-  FF_TX_F_CLK_2 => open,
-  FF_TX_H_CLK_2 => open,
-  FFC_CK_CORE_RX_2 => fpsc_vlo,
-  FF_TX_D_2_0 => fpsc_vlo,
-  FF_TX_D_2_1 => fpsc_vlo,
-  FF_TX_D_2_2 => fpsc_vlo,
-  FF_TX_D_2_3 => fpsc_vlo,
-  FF_TX_D_2_4 => fpsc_vlo,
-  FF_TX_D_2_5 => fpsc_vlo,
-  FF_TX_D_2_6 => fpsc_vlo,
-  FF_TX_D_2_7 => fpsc_vlo,
-  FF_TX_D_2_8 => fpsc_vlo,
-  FF_TX_D_2_9 => fpsc_vlo,
-  FF_TX_D_2_10 => fpsc_vlo,
-  FF_TX_D_2_11 => fpsc_vlo,
-  FF_TX_D_2_12 => fpsc_vlo,
-  FF_TX_D_2_13 => fpsc_vlo,
-  FF_TX_D_2_14 => fpsc_vlo,
-  FF_TX_D_2_15 => fpsc_vlo,
-  FF_TX_D_2_16 => fpsc_vlo,
-  FF_TX_D_2_17 => fpsc_vlo,
-  FF_TX_D_2_18 => fpsc_vlo,
-  FF_TX_D_2_19 => fpsc_vlo,
-  FF_TX_D_2_20 => fpsc_vlo,
-  FF_TX_D_2_21 => fpsc_vlo,
-  FF_TX_D_2_22 => fpsc_vlo,
-  FF_TX_D_2_23 => fpsc_vlo,
-  FF_RX_D_2_0 => open,
-  FF_RX_D_2_1 => open,
-  FF_RX_D_2_2 => open,
-  FF_RX_D_2_3 => open,
-  FF_RX_D_2_4 => open,
-  FF_RX_D_2_5 => open,
-  FF_RX_D_2_6 => open,
-  FF_RX_D_2_7 => open,
-  FF_RX_D_2_8 => open,
-  FF_RX_D_2_9 => open,
-  FF_RX_D_2_10 => open,
-  FF_RX_D_2_11 => open,
-  FF_RX_D_2_12 => open,
-  FF_RX_D_2_13 => open,
-  FF_RX_D_2_14 => open,
-  FF_RX_D_2_15 => open,
-  FF_RX_D_2_16 => open,
-  FF_RX_D_2_17 => open,
-  FF_RX_D_2_18 => open,
-  FF_RX_D_2_19 => open,
-  FF_RX_D_2_20 => open,
-  FF_RX_D_2_21 => open,
-  FF_RX_D_2_22 => open,
-  FF_RX_D_2_23 => open,
-
-  FFC_RRST_2 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_2 => fpsc_vlo,
-  FFC_PFIFO_CLR_2 => fpsc_vlo,
-  FFC_SB_INV_RX_2 => fpsc_vlo,
-  FFC_PCIE_CT_2 => fpsc_vlo,
-  FFC_PCI_DET_EN_2 => fpsc_vlo,
-  FFC_FB_LOOPBACK_2 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
-  FFC_EI_EN_2 => fpsc_vlo,
-  FFC_LANE_TX_RST_2 => fpsc_vlo,
-  FFC_TXPWDNB_2 => fpsc_vlo,
-  FFC_LANE_RX_RST_2 => fpsc_vlo,
-  FFC_RXPWDNB_2 => fpsc_vlo,
-  FFS_RLOS_LO_2 => open,
-  FFS_RLOS_HI_2 => open,
-  FFS_PCIE_CON_2 => open,
-  FFS_PCIE_DONE_2 => open,
-  FFS_LS_SYNC_STATUS_2 => open,
-  FFS_CC_OVERRUN_2 => open,
-  FFS_CC_UNDERRUN_2 => open,
-  FFS_SKP_ADDED_2 => open,
-  FFS_SKP_DELETED_2 => open,
-  FFS_RLOL_2 => open,
-  FFS_RXFBFIFO_ERROR_2 => open,
-  FFS_TXFBFIFO_ERROR_2 => open,
-  LDR_CORE2TX_2 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
-  LDR_RX2CORE_2 => open,
-  FFS_CDR_TRAIN_DONE_2 => open,
-  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
-  FFC_RATE_MODE_TX_2 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
-  FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
-  HDOUTP3 => open,
-  HDOUTN3 => open,
-  HDINP3 => fpsc_vlo,
-  HDINN3 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
-  PCIE_RXPOLARITY_3 => fpsc_vlo,
-  PCIE_POWERDOWN_3_0 => fpsc_vlo,
-  PCIE_POWERDOWN_3_1 => fpsc_vlo,
-  PCIE_RXVALID_3 => open,
-  PCIE_PHYSTATUS_3 => open,
-  SCISELCH3 => fpsc_vlo,
-  SCIENCH3 => fpsc_vlo,
-  FF_RXI_CLK_3 => fpsc_vlo,
-  FF_TXI_CLK_3 => fpsc_vlo,
-  FF_EBRD_CLK_3 => fpsc_vlo,
-  FF_RX_F_CLK_3 => open,
-  FF_RX_H_CLK_3 => open,
-  FF_TX_F_CLK_3 => open,
-  FF_TX_H_CLK_3 => open,
-  FFC_CK_CORE_RX_3 => fpsc_vlo,
-  FF_TX_D_3_0 => fpsc_vlo,
-  FF_TX_D_3_1 => fpsc_vlo,
-  FF_TX_D_3_2 => fpsc_vlo,
-  FF_TX_D_3_3 => fpsc_vlo,
-  FF_TX_D_3_4 => fpsc_vlo,
-  FF_TX_D_3_5 => fpsc_vlo,
-  FF_TX_D_3_6 => fpsc_vlo,
-  FF_TX_D_3_7 => fpsc_vlo,
-  FF_TX_D_3_8 => fpsc_vlo,
-  FF_TX_D_3_9 => fpsc_vlo,
-  FF_TX_D_3_10 => fpsc_vlo,
-  FF_TX_D_3_11 => fpsc_vlo,
-  FF_TX_D_3_12 => fpsc_vlo,
-  FF_TX_D_3_13 => fpsc_vlo,
-  FF_TX_D_3_14 => fpsc_vlo,
-  FF_TX_D_3_15 => fpsc_vlo,
-  FF_TX_D_3_16 => fpsc_vlo,
-  FF_TX_D_3_17 => fpsc_vlo,
-  FF_TX_D_3_18 => fpsc_vlo,
-  FF_TX_D_3_19 => fpsc_vlo,
-  FF_TX_D_3_20 => fpsc_vlo,
-  FF_TX_D_3_21 => fpsc_vlo,
-  FF_TX_D_3_22 => fpsc_vlo,
-  FF_TX_D_3_23 => fpsc_vlo,
-  FF_RX_D_3_0 => open,
-  FF_RX_D_3_1 => open,
-  FF_RX_D_3_2 => open,
-  FF_RX_D_3_3 => open,
-  FF_RX_D_3_4 => open,
-  FF_RX_D_3_5 => open,
-  FF_RX_D_3_6 => open,
-  FF_RX_D_3_7 => open,
-  FF_RX_D_3_8 => open,
-  FF_RX_D_3_9 => open,
-  FF_RX_D_3_10 => open,
-  FF_RX_D_3_11 => open,
-  FF_RX_D_3_12 => open,
-  FF_RX_D_3_13 => open,
-  FF_RX_D_3_14 => open,
-  FF_RX_D_3_15 => open,
-  FF_RX_D_3_16 => open,
-  FF_RX_D_3_17 => open,
-  FF_RX_D_3_18 => open,
-  FF_RX_D_3_19 => open,
-  FF_RX_D_3_20 => open,
-  FF_RX_D_3_21 => open,
-  FF_RX_D_3_22 => open,
-  FF_RX_D_3_23 => open,
-
-  FFC_RRST_3 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_3 => fpsc_vlo,
-  FFC_PFIFO_CLR_3 => fpsc_vlo,
-  FFC_SB_INV_RX_3 => fpsc_vlo,
-  FFC_PCIE_CT_3 => fpsc_vlo,
-  FFC_PCI_DET_EN_3 => fpsc_vlo,
-  FFC_FB_LOOPBACK_3 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
-  FFC_EI_EN_3 => fpsc_vlo,
-  FFC_LANE_TX_RST_3 => fpsc_vlo,
-  FFC_TXPWDNB_3 => fpsc_vlo,
-  FFC_LANE_RX_RST_3 => fpsc_vlo,
-  FFC_RXPWDNB_3 => fpsc_vlo,
-  FFS_RLOS_LO_3 => open,
-  FFS_RLOS_HI_3 => open,
-  FFS_PCIE_CON_3 => open,
-  FFS_PCIE_DONE_3 => open,
-  FFS_LS_SYNC_STATUS_3 => open,
-  FFS_CC_OVERRUN_3 => open,
-  FFS_CC_UNDERRUN_3 => open,
-  FFS_SKP_ADDED_3 => open,
-  FFS_SKP_DELETED_3 => open,
-  FFS_RLOL_3 => open,
-  FFS_RXFBFIFO_ERROR_3 => open,
-  FFS_TXFBFIFO_ERROR_3 => open,
-  LDR_CORE2TX_3 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
-  LDR_RX2CORE_3 => open,
-  FFS_CDR_TRAIN_DONE_3 => open,
-  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
-  FFC_RATE_MODE_TX_3 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
-  FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
-  SCIWDATA7 => sci_wrdata(7),
-  SCIWDATA6 => sci_wrdata(6),
-  SCIWDATA5 => sci_wrdata(5),
-  SCIWDATA4 => sci_wrdata(4),
-  SCIWDATA3 => sci_wrdata(3),
-  SCIWDATA2 => sci_wrdata(2),
-  SCIWDATA1 => sci_wrdata(1),
-  SCIWDATA0 => sci_wrdata(0),
-  SCIADDR5 => sci_addr(5),
-  SCIADDR4 => sci_addr(4),
-  SCIADDR3 => sci_addr(3),
-  SCIADDR2 => sci_addr(2),
-  SCIADDR1 => sci_addr(1),
-  SCIADDR0 => sci_addr(0),
-  SCIRDATA7 => sci_rddata(7),
-  SCIRDATA6 => sci_rddata(6),
-  SCIRDATA5 => sci_rddata(5),
-  SCIRDATA4 => sci_rddata(4),
-  SCIRDATA3 => sci_rddata(3),
-  SCIRDATA2 => sci_rddata(2),
-  SCIRDATA1 => sci_rddata(1),
-  SCIRDATA0 => sci_rddata(0),
-  SCIENAUX => fpsc_vhi,
-  SCISELAUX => sci_sel_quad,
-  SCIRD => sci_rd,
-  SCIWSTN => sci_wrn,
-  CYAWSTN => fpsc_vlo,
-  SCIINT => open,
-  FFC_CK_CORE_TX => fpga_txrefclk,
-  FFC_MACRO_RST => serdes_rst_qd_c,
-  FFC_QUAD_RST => rst_qd_c,
-  FFC_TRST => tx_serdes_rst_c,
-  FFS_PLOL => tx_pll_lol_qd_sig,
-  FFC_SYNC_TOGGLE => fpsc_vlo,
-  REFCK2CORE => refclk2fpga_sig,
-  CIN0 => fpsc_vlo,
-  CIN1 => fpsc_vlo,
-  CIN2 => fpsc_vlo,
-  CIN3 => fpsc_vlo,
-  CIN4 => fpsc_vlo,
-  CIN5 => fpsc_vlo,
-  CIN6 => fpsc_vlo,
-  CIN7 => fpsc_vlo,
-  CIN8 => fpsc_vlo,
-  CIN9 => fpsc_vlo,
-  CIN10 => fpsc_vlo,
-  CIN11 => fpsc_vlo,
-  COUT0 => open,
-  COUT1 => open,
-  COUT2 => open,
-  COUT3 => open,
-  COUT4 => open,
-  COUT5 => open,
-  COUT6 => open,
-  COUT7 => open,
-  COUT8 => open,
-  COUT9 => open,
-  COUT10 => open,
-  COUT11 => open,
-  COUT12 => open,
-  COUT13 => open,
-  COUT14 => open,
-  COUT15 => open,
-  COUT16 => open,
-  COUT17 => open,
-  COUT18 => open,
-  COUT19 => open,
-  REFCLK_FROM_NQ => refclk_from_nq,
-  REFCLK_TO_NQ => open);
-
--- reset sequence for rx
-                                                                                              
-  P2 : PROCESS(fpga_rxrefclk_ch1, rst_n)
-  BEGIN
-     IF (rst_n = '0') THEN
-         refclkdiv2_rx_ch1 <= '0';
-     ELSIF (fpga_rxrefclk_ch1'event and fpga_rxrefclk_ch1 = '1') THEN
-         refclkdiv2_rx_ch1 <= not refclkdiv2_rx_ch1;
-     END IF;
-  END PROCESS;
-                                                                                              
-rx_reset_sm_ch1 : sfp_1_125_intrx_reset_sm
---synopsys translate_off
-  generic map (count_index => 4)
---synopsys translate_on
-port map  (
-  refclkdiv2 => refclkdiv2_rx_ch1,
-  rst_n => rst_n,
-  rx_cdr_lol_ch_s => rx_cdr_lol_ch1_sig,
-  rx_los_low_ch_s => rx_los_low_ch1_sig,
-  tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
-  rx_pcs_rst_ch_c => rx_pcs_rst_ch1_c,
-  rx_serdes_rst_ch_c => rx_serdes_rst_ch1_c);
-                                                                                              
-                                                                                              
-                                                                                              
-                                                                                              
-  P5 : PROCESS(fpga_txrefclk, rst_n)
-  BEGIN
-     IF (rst_n = '0') THEN
-         refclkdiv2_tx_ch <= '0';
-     ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN
-         refclkdiv2_tx_ch <= not refclkdiv2_tx_ch;
-     END IF;
-  END PROCESS;
-
--- reset sequence for tx
-tx_reset_sm_ch : sfp_1_125_inttx_reset_sm 
---synopsys translate_off
-  generic map (count_index => 4)
---synopsys translate_on
-port map  (
-  rst_n => rst_n,
-  refclkdiv2 => refclkdiv2_tx_ch,
-  tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
-  rst_qd_c => rst_qd_c,
-  tx_pcs_rst_ch_c => tx_pcs_rst_ch_c
-  );
-                                                                                              
-                                                                                              
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
-   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
-   IF (open_status = name_error) THEN
-      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
-      severity ERROR;
-   END IF;
-   wait;
-END PROCESS;
---synopsys translate_on
-end sfp_1_125_int_arch ;
diff --git a/code/ip/sfp_1_200_int.ipx b/code/ip/sfp_1_200_int.ipx
deleted file mode 100644
index 951f7ad..0000000
--- a/code/ip/sfp_1_200_int.ipx
+++ /dev/null
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="sfp_1_200_int" module="sfp_1_200_int" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 11 09:38:27.437" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-		<File name="sfp_1_200_int.lpc" type="lpc" modified="2015 02 11 09:38:25.000"/>
-		<File name="sfp_1_200_int.pp" type="pp" modified="2015 02 11 09:38:25.000"/>
-		<File name="sfp_1_200_int.sym" type="sym" modified="2015 02 11 09:38:25.000"/>
-		<File name="sfp_1_200_int.tft" type="tft" modified="2015 02 11 09:38:25.000"/>
-		<File name="sfp_1_200_int.txt" type="pcs_module" modified="2015 02 11 09:38:25.000"/>
-		<File name="sfp_1_200_int.vhd" type="top_level_vhdl" modified="2015 02 11 09:38:25.000"/>
-  </Package>
-</DiamondModule>
diff --git a/code/ip/sfp_1_200_int.lpc b/code/ip/sfp_1_200_int.lpc
deleted file mode 100644
index 0b4f6ab..0000000
--- a/code/ip/sfp_1_200_int.lpc
+++ /dev/null
@@ -1,258 +0,0 @@
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.2
-ModuleName=sfp_1_200_int
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=02/11/2015
-Time=09:38:25
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=DISABLED
-_mode1=RXTX
-_mode2=DISABLED
-_mode3=DISABLED
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=DISABLED
-_tx_protocol1=G8B10B
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=16
-_tx_data_width1=16
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=DISABLED
-_tx_ficlk_rate0=100
-_tx_ficlk_rate1=100
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=INTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2
-_rx_datarange2=2
-_rx_datarange3=2
-_rx_protocol0=DISABLED
-_rx_protocol1=G8B10B
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=200
-_rxrefclk_rate1=200
-_rxrefclk_rate2=200
-_rxrefclk_rate3=200
-_rx_data_width0=16
-_rx_data_width1=16
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=DISABLED
-_rx_ficlk_rate0=100
-_rx_ficlk_rate1=100
-_rx_ficlk_rate2=200
-_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=DC
-_rx_dcc2=AC
-_rx_dcc3=DC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=2
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=01
-_k02=00
-_k03=00
-_k10=01
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00011100
-_byten02=00000000
-_byten03=00000000
-_byten10=00011100
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=1
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=ENABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-sfp_1_200_int.pp=pp
-sfp_1_200_int.tft=tft
-sfp_1_200_int.txt=pcs_module
-sfp_1_200_int.sym=sym
diff --git a/code/ip/sfp_1_200_int.txt b/code/ip/sfp_1_200_int.txt
deleted file mode 100644
index 8db08f2..0000000
--- a/code/ip/sfp_1_200_int.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH1_PROTOCOL            "G8B10B"
-CH0_MODE                "DISABLED"
-CH1_MODE                "RXTX"
-CH2_MODE                "DISABLED"
-CH3_MODE                "DISABLED"
-CH1_CDR_SRC       "REFCLK_CORE"
-PLL_SRC                 "REFCLK_CORE"
-TX_DATARATE_RANGE       "MEDHIGH"
-CH1_RX_DATARATE_RANGE   "MEDHIGH"
-REFCK_MULT              "10X"
-#REFCLK_RATE            200
-CH1_RX_DATA_RATE        "FULL"
-CH1_TX_DATA_RATE        "FULL"
-CH1_TX_DATA_WIDTH       "16"
-CH1_RX_DATA_WIDTH        "16"
-CH1_TX_FIFO       "ENABLED"
-CH1_RX_FIFO        "ENABLED"
-CH1_TDRV      "0"
-#CH1_TX_FICLK_RATE      100
-#CH1_RXREFCLK_RATE        "200"
-#CH1_RX_FICLK_RATE      100
-CH1_TX_PRE              "DISABLED"
-CH1_RTERM_TX            "50"
-CH1_RX_EQ               "DISABLED"
-CH1_RTERM_RX            "50"
-CH1_RX_DCC              "DC"
-CH1_LOS_THRESHOLD_LO       "2"
-PLL_TERM                "50"
-PLL_DCC                 "AC"
-PLL_LOL_SET             "0"
-CH1_TX_SB               "DISABLED"
-CH1_RX_SB               "DISABLED"
-CH1_TX_8B10B            "ENABLED"
-CH1_RX_8B10B            "ENABLED"
-CH1_COMMA_A             "1100000101"
-CH1_COMMA_B             "0011111010"
-CH1_COMMA_M             "1111111100"
-CH1_RXWA                "ENABLED"
-CH1_ILSM                "ENABLED"
-CH1_CTC                 "DISABLED"
-CH1_CC_MATCH4           "0100011100"
-CH1_CC_MATCH_MODE       "1"
-CH1_CC_MIN_IPG          "3"
-CCHMARK                 "9"
-CCLMARK                 "7"
-CH1_SSLB                "DISABLED"
-CH1_SPLBPORTS           "DISABLED"
-CH1_PCSLBPORTS          "DISABLED"
-INT_ALL                 "DISABLED"
-QD_REFCK2CORE           "ENABLED"
-
-
diff --git a/code/ip/sfp_1_200_int.vhd b/code/ip/sfp_1_200_int.vhd
deleted file mode 100644
index 1dda35d..0000000
--- a/code/ip/sfp_1_200_int.vhd
+++ /dev/null
@@ -1,3162 +0,0 @@
-
-                                                                                                         
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
---  CONFIG_FILE : String  := "sfp_1_200_int.txt";
---  QUAD_MODE : String := "SINGLE";
---  CH0_CDR_SRC   : String := "REFCLK_CORE";
---  CH1_CDR_SRC   : String := "REFCLK_CORE";
---  CH2_CDR_SRC   : String := "REFCLK_EXT";
---  CH3_CDR_SRC   : String := "REFCLK_CORE";
---  PLL_SRC   : String := "REFCLK_CORE"
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String;
-  CH1_CDR_SRC   : String;
-  CH2_CDR_SRC   : String;
-  CH3_CDR_SRC   : String;
-  PLL_SRC   : String
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
-  CONFIG_FILE => CONFIG_FILE,
-  QUAD_MODE => QUAD_MODE,
-  CH0_CDR_SRC => CH0_CDR_SRC,
-  CH1_CDR_SRC => CH1_CDR_SRC,
-  CH2_CDR_SRC => CH2_CDR_SRC,
-  CH3_CDR_SRC => CH3_CDR_SRC,
-  PLL_SRC => PLL_SRC
-  )
-port map (
-   HDINN0 => HDINN0,
-   HDINN1 => HDINN1,
-   HDINN2 => HDINN2,
-   HDINN3 => HDINN3,
-   HDINP0 => HDINP0,
-   HDINP1 => HDINP1,
-   HDINP2 => HDINP2,
-   HDINP3 => HDINP3,
-   REFCLKN => REFCLKN,
-   REFCLKP => REFCLKP,
-   CIN11 => CIN11,
-   CIN10 => CIN10,
-   CIN9 => CIN9,
-   CIN8 => CIN8,
-   CIN7 => CIN7,
-   CIN6 => CIN6,
-   CIN5 => CIN5,
-   CIN4 => CIN4,
-   CIN3 => CIN3,
-   CIN2 => CIN2,
-   CIN1 => CIN1,
-   CIN0 => CIN0,
-   CYAWSTN => CYAWSTN,
-   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
-   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
-   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
-   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
-   FF_RXI_CLK_3 => FF_RXI_CLK_3,
-   FF_RXI_CLK_2 => FF_RXI_CLK_2,
-   FF_RXI_CLK_1 => FF_RXI_CLK_1,
-   FF_RXI_CLK_0 => FF_RXI_CLK_0,
-   FF_TX_D_0_0 => FF_TX_D_0_0,
-   FF_TX_D_0_1 => FF_TX_D_0_1,
-   FF_TX_D_0_2 => FF_TX_D_0_2,
-   FF_TX_D_0_3 => FF_TX_D_0_3,
-   FF_TX_D_0_4 => FF_TX_D_0_4,
-   FF_TX_D_0_5 => FF_TX_D_0_5,
-   FF_TX_D_0_6 => FF_TX_D_0_6,
-   FF_TX_D_0_7 => FF_TX_D_0_7,
-   FF_TX_D_0_8 => FF_TX_D_0_8,
-   FF_TX_D_0_9 => FF_TX_D_0_9,
-   FF_TX_D_0_10 => FF_TX_D_0_10,
-   FF_TX_D_0_11 => FF_TX_D_0_11,
-   FF_TX_D_0_12 => FF_TX_D_0_12,
-   FF_TX_D_0_13 => FF_TX_D_0_13,
-   FF_TX_D_0_14 => FF_TX_D_0_14,
-   FF_TX_D_0_15 => FF_TX_D_0_15,
-   FF_TX_D_0_16 => FF_TX_D_0_16,
-   FF_TX_D_0_17 => FF_TX_D_0_17,
-   FF_TX_D_0_18 => FF_TX_D_0_18,
-   FF_TX_D_0_19 => FF_TX_D_0_19,
-   FF_TX_D_0_20 => FF_TX_D_0_20,
-   FF_TX_D_0_21 => FF_TX_D_0_21,
-   FF_TX_D_0_22 => FF_TX_D_0_22,
-   FF_TX_D_0_23 => FF_TX_D_0_23,
-   FF_TX_D_1_0 => FF_TX_D_1_0,
-   FF_TX_D_1_1 => FF_TX_D_1_1,
-   FF_TX_D_1_2 => FF_TX_D_1_2,
-   FF_TX_D_1_3 => FF_TX_D_1_3,
-   FF_TX_D_1_4 => FF_TX_D_1_4,
-   FF_TX_D_1_5 => FF_TX_D_1_5,
-   FF_TX_D_1_6 => FF_TX_D_1_6,
-   FF_TX_D_1_7 => FF_TX_D_1_7,
-   FF_TX_D_1_8 => FF_TX_D_1_8,
-   FF_TX_D_1_9 => FF_TX_D_1_9,
-   FF_TX_D_1_10 => FF_TX_D_1_10,
-   FF_TX_D_1_11 => FF_TX_D_1_11,
-   FF_TX_D_1_12 => FF_TX_D_1_12,
-   FF_TX_D_1_13 => FF_TX_D_1_13,
-   FF_TX_D_1_14 => FF_TX_D_1_14,
-   FF_TX_D_1_15 => FF_TX_D_1_15,
-   FF_TX_D_1_16 => FF_TX_D_1_16,
-   FF_TX_D_1_17 => FF_TX_D_1_17,
-   FF_TX_D_1_18 => FF_TX_D_1_18,
-   FF_TX_D_1_19 => FF_TX_D_1_19,
-   FF_TX_D_1_20 => FF_TX_D_1_20,
-   FF_TX_D_1_21 => FF_TX_D_1_21,
-   FF_TX_D_1_22 => FF_TX_D_1_22,
-   FF_TX_D_1_23 => FF_TX_D_1_23,
-   FF_TX_D_2_0 => FF_TX_D_2_0,
-   FF_TX_D_2_1 => FF_TX_D_2_1,
-   FF_TX_D_2_2 => FF_TX_D_2_2,
-   FF_TX_D_2_3 => FF_TX_D_2_3,
-   FF_TX_D_2_4 => FF_TX_D_2_4,
-   FF_TX_D_2_5 => FF_TX_D_2_5,
-   FF_TX_D_2_6 => FF_TX_D_2_6,
-   FF_TX_D_2_7 => FF_TX_D_2_7,
-   FF_TX_D_2_8 => FF_TX_D_2_8,
-   FF_TX_D_2_9 => FF_TX_D_2_9,
-   FF_TX_D_2_10 => FF_TX_D_2_10,
-   FF_TX_D_2_11 => FF_TX_D_2_11,
-   FF_TX_D_2_12 => FF_TX_D_2_12,
-   FF_TX_D_2_13 => FF_TX_D_2_13,
-   FF_TX_D_2_14 => FF_TX_D_2_14,
-   FF_TX_D_2_15 => FF_TX_D_2_15,
-   FF_TX_D_2_16 => FF_TX_D_2_16,
-   FF_TX_D_2_17 => FF_TX_D_2_17,
-   FF_TX_D_2_18 => FF_TX_D_2_18,
-   FF_TX_D_2_19 => FF_TX_D_2_19,
-   FF_TX_D_2_20 => FF_TX_D_2_20,
-   FF_TX_D_2_21 => FF_TX_D_2_21,
-   FF_TX_D_2_22 => FF_TX_D_2_22,
-   FF_TX_D_2_23 => FF_TX_D_2_23,
-   FF_TX_D_3_0 => FF_TX_D_3_0,
-   FF_TX_D_3_1 => FF_TX_D_3_1,
-   FF_TX_D_3_2 => FF_TX_D_3_2,
-   FF_TX_D_3_3 => FF_TX_D_3_3,
-   FF_TX_D_3_4 => FF_TX_D_3_4,
-   FF_TX_D_3_5 => FF_TX_D_3_5,
-   FF_TX_D_3_6 => FF_TX_D_3_6,
-   FF_TX_D_3_7 => FF_TX_D_3_7,
-   FF_TX_D_3_8 => FF_TX_D_3_8,
-   FF_TX_D_3_9 => FF_TX_D_3_9,
-   FF_TX_D_3_10 => FF_TX_D_3_10,
-   FF_TX_D_3_11 => FF_TX_D_3_11,
-   FF_TX_D_3_12 => FF_TX_D_3_12,
-   FF_TX_D_3_13 => FF_TX_D_3_13,
-   FF_TX_D_3_14 => FF_TX_D_3_14,
-   FF_TX_D_3_15 => FF_TX_D_3_15,
-   FF_TX_D_3_16 => FF_TX_D_3_16,
-   FF_TX_D_3_17 => FF_TX_D_3_17,
-   FF_TX_D_3_18 => FF_TX_D_3_18,
-   FF_TX_D_3_19 => FF_TX_D_3_19,
-   FF_TX_D_3_20 => FF_TX_D_3_20,
-   FF_TX_D_3_21 => FF_TX_D_3_21,
-   FF_TX_D_3_22 => FF_TX_D_3_22,
-   FF_TX_D_3_23 => FF_TX_D_3_23,
-   FF_TXI_CLK_0 => FF_TXI_CLK_0,
-   FF_TXI_CLK_1 => FF_TXI_CLK_1,
-   FF_TXI_CLK_2 => FF_TXI_CLK_2,
-   FF_TXI_CLK_3 => FF_TXI_CLK_3,
-   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
-   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
-   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
-   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
-   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
-   FFC_EI_EN_0 => FFC_EI_EN_0,
-   FFC_EI_EN_1 => FFC_EI_EN_1,
-   FFC_EI_EN_2 => FFC_EI_EN_2,
-   FFC_EI_EN_3 => FFC_EI_EN_3,
-   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
-   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
-   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
-   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
-   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
-   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
-   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
-   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
-   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
-   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
-   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
-   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
-   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
-   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
-   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
-   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
-   FFC_MACRO_RST => FFC_MACRO_RST,
-   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
-   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
-   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
-   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
-   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
-   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
-   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
-   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
-   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
-   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
-   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
-   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
-   FFC_QUAD_RST => FFC_QUAD_RST,
-   FFC_RRST_0 => FFC_RRST_0,
-   FFC_RRST_1 => FFC_RRST_1,
-   FFC_RRST_2 => FFC_RRST_2,
-   FFC_RRST_3 => FFC_RRST_3,
-   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
-   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
-   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
-   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
-   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
-   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
-   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
-   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
-   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
-   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
-   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
-   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
-   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
-   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
-   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
-   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
-   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
-   FFC_TRST => FFC_TRST,
-   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
-   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
-   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
-   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
-   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
-   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
-   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
-   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
-   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
-   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
-   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
-   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
-   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
-   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
-   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
-   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
-   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
-   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
-   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
-   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
-   LDR_CORE2TX_0 => LDR_CORE2TX_0,
-   LDR_CORE2TX_1 => LDR_CORE2TX_1,
-   LDR_CORE2TX_2 => LDR_CORE2TX_2,
-   LDR_CORE2TX_3 => LDR_CORE2TX_3,
-   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
-   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
-   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
-   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
-   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
-   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
-   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
-   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
-   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
-   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
-   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
-   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
-   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
-   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
-   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
-   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
-   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
-   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
-   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
-   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
-   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
-   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
-   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
-   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
-   SCIADDR0 => SCIADDR0,
-   SCIADDR1 => SCIADDR1,
-   SCIADDR2 => SCIADDR2,
-   SCIADDR3 => SCIADDR3,
-   SCIADDR4 => SCIADDR4,
-   SCIADDR5 => SCIADDR5,
-   SCIENAUX => SCIENAUX,
-   SCIENCH0 => SCIENCH0,
-   SCIENCH1 => SCIENCH1,
-   SCIENCH2 => SCIENCH2,
-   SCIENCH3 => SCIENCH3,
-   SCIRD => SCIRD,
-   SCISELAUX => SCISELAUX,
-   SCISELCH0 => SCISELCH0,
-   SCISELCH1 => SCISELCH1,
-   SCISELCH2 => SCISELCH2,
-   SCISELCH3 => SCISELCH3,
-   SCIWDATA0 => SCIWDATA0,
-   SCIWDATA1 => SCIWDATA1,
-   SCIWDATA2 => SCIWDATA2,
-   SCIWDATA3 => SCIWDATA3,
-   SCIWDATA4 => SCIWDATA4,
-   SCIWDATA5 => SCIWDATA5,
-   SCIWDATA6 => SCIWDATA6,
-   SCIWDATA7 => SCIWDATA7,
-   SCIWSTN => SCIWSTN,
-   HDOUTN0 => HDOUTN0,
-   HDOUTN1 => HDOUTN1,
-   HDOUTN2 => HDOUTN2,
-   HDOUTN3 => HDOUTN3,
-   HDOUTP0 => HDOUTP0,
-   HDOUTP1 => HDOUTP1,
-   HDOUTP2 => HDOUTP2,
-   HDOUTP3 => HDOUTP3,
-   COUT19 => COUT19,
-   COUT18 => COUT18,
-   COUT17 => COUT17,
-   COUT16 => COUT16,
-   COUT15 => COUT15,
-   COUT14 => COUT14,
-   COUT13 => COUT13,
-   COUT12 => COUT12,
-   COUT11 => COUT11,
-   COUT10 => COUT10,
-   COUT9 => COUT9,
-   COUT8 => COUT8,
-   COUT7 => COUT7,
-   COUT6 => COUT6,
-   COUT5 => COUT5,
-   COUT4 => COUT4,
-   COUT3 => COUT3,
-   COUT2 => COUT2,
-   COUT1 => COUT1,
-   COUT0 => COUT0,
-   FF_RX_D_0_0 => FF_RX_D_0_0,
-   FF_RX_D_0_1 => FF_RX_D_0_1,
-   FF_RX_D_0_2 => FF_RX_D_0_2,
-   FF_RX_D_0_3 => FF_RX_D_0_3,
-   FF_RX_D_0_4 => FF_RX_D_0_4,
-   FF_RX_D_0_5 => FF_RX_D_0_5,
-   FF_RX_D_0_6 => FF_RX_D_0_6,
-   FF_RX_D_0_7 => FF_RX_D_0_7,
-   FF_RX_D_0_8 => FF_RX_D_0_8,
-   FF_RX_D_0_9 => FF_RX_D_0_9,
-   FF_RX_D_0_10 => FF_RX_D_0_10,
-   FF_RX_D_0_11 => FF_RX_D_0_11,
-   FF_RX_D_0_12 => FF_RX_D_0_12,
-   FF_RX_D_0_13 => FF_RX_D_0_13,
-   FF_RX_D_0_14 => FF_RX_D_0_14,
-   FF_RX_D_0_15 => FF_RX_D_0_15,
-   FF_RX_D_0_16 => FF_RX_D_0_16,
-   FF_RX_D_0_17 => FF_RX_D_0_17,
-   FF_RX_D_0_18 => FF_RX_D_0_18,
-   FF_RX_D_0_19 => FF_RX_D_0_19,
-   FF_RX_D_0_20 => FF_RX_D_0_20,
-   FF_RX_D_0_21 => FF_RX_D_0_21,
-   FF_RX_D_0_22 => FF_RX_D_0_22,
-   FF_RX_D_0_23 => FF_RX_D_0_23,
-   FF_RX_D_1_0 => FF_RX_D_1_0,
-   FF_RX_D_1_1 => FF_RX_D_1_1,
-   FF_RX_D_1_2 => FF_RX_D_1_2,
-   FF_RX_D_1_3 => FF_RX_D_1_3,
-   FF_RX_D_1_4 => FF_RX_D_1_4,
-   FF_RX_D_1_5 => FF_RX_D_1_5,
-   FF_RX_D_1_6 => FF_RX_D_1_6,
-   FF_RX_D_1_7 => FF_RX_D_1_7,
-   FF_RX_D_1_8 => FF_RX_D_1_8,
-   FF_RX_D_1_9 => FF_RX_D_1_9,
-   FF_RX_D_1_10 => FF_RX_D_1_10,
-   FF_RX_D_1_11 => FF_RX_D_1_11,
-   FF_RX_D_1_12 => FF_RX_D_1_12,
-   FF_RX_D_1_13 => FF_RX_D_1_13,
-   FF_RX_D_1_14 => FF_RX_D_1_14,
-   FF_RX_D_1_15 => FF_RX_D_1_15,
-   FF_RX_D_1_16 => FF_RX_D_1_16,
-   FF_RX_D_1_17 => FF_RX_D_1_17,
-   FF_RX_D_1_18 => FF_RX_D_1_18,
-   FF_RX_D_1_19 => FF_RX_D_1_19,
-   FF_RX_D_1_20 => FF_RX_D_1_20,
-   FF_RX_D_1_21 => FF_RX_D_1_21,
-   FF_RX_D_1_22 => FF_RX_D_1_22,
-   FF_RX_D_1_23 => FF_RX_D_1_23,
-   FF_RX_D_2_0 => FF_RX_D_2_0,
-   FF_RX_D_2_1 => FF_RX_D_2_1,
-   FF_RX_D_2_2 => FF_RX_D_2_2,
-   FF_RX_D_2_3 => FF_RX_D_2_3,
-   FF_RX_D_2_4 => FF_RX_D_2_4,
-   FF_RX_D_2_5 => FF_RX_D_2_5,
-   FF_RX_D_2_6 => FF_RX_D_2_6,
-   FF_RX_D_2_7 => FF_RX_D_2_7,
-   FF_RX_D_2_8 => FF_RX_D_2_8,
-   FF_RX_D_2_9 => FF_RX_D_2_9,
-   FF_RX_D_2_10 => FF_RX_D_2_10,
-   FF_RX_D_2_11 => FF_RX_D_2_11,
-   FF_RX_D_2_12 => FF_RX_D_2_12,
-   FF_RX_D_2_13 => FF_RX_D_2_13,
-   FF_RX_D_2_14 => FF_RX_D_2_14,
-   FF_RX_D_2_15 => FF_RX_D_2_15,
-   FF_RX_D_2_16 => FF_RX_D_2_16,
-   FF_RX_D_2_17 => FF_RX_D_2_17,
-   FF_RX_D_2_18 => FF_RX_D_2_18,
-   FF_RX_D_2_19 => FF_RX_D_2_19,
-   FF_RX_D_2_20 => FF_RX_D_2_20,
-   FF_RX_D_2_21 => FF_RX_D_2_21,
-   FF_RX_D_2_22 => FF_RX_D_2_22,
-   FF_RX_D_2_23 => FF_RX_D_2_23,
-   FF_RX_D_3_0 => FF_RX_D_3_0,
-   FF_RX_D_3_1 => FF_RX_D_3_1,
-   FF_RX_D_3_2 => FF_RX_D_3_2,
-   FF_RX_D_3_3 => FF_RX_D_3_3,
-   FF_RX_D_3_4 => FF_RX_D_3_4,
-   FF_RX_D_3_5 => FF_RX_D_3_5,
-   FF_RX_D_3_6 => FF_RX_D_3_6,
-   FF_RX_D_3_7 => FF_RX_D_3_7,
-   FF_RX_D_3_8 => FF_RX_D_3_8,
-   FF_RX_D_3_9 => FF_RX_D_3_9,
-   FF_RX_D_3_10 => FF_RX_D_3_10,
-   FF_RX_D_3_11 => FF_RX_D_3_11,
-   FF_RX_D_3_12 => FF_RX_D_3_12,
-   FF_RX_D_3_13 => FF_RX_D_3_13,
-   FF_RX_D_3_14 => FF_RX_D_3_14,
-   FF_RX_D_3_15 => FF_RX_D_3_15,
-   FF_RX_D_3_16 => FF_RX_D_3_16,
-   FF_RX_D_3_17 => FF_RX_D_3_17,
-   FF_RX_D_3_18 => FF_RX_D_3_18,
-   FF_RX_D_3_19 => FF_RX_D_3_19,
-   FF_RX_D_3_20 => FF_RX_D_3_20,
-   FF_RX_D_3_21 => FF_RX_D_3_21,
-   FF_RX_D_3_22 => FF_RX_D_3_22,
-   FF_RX_D_3_23 => FF_RX_D_3_23,
-   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
-   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
-   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
-   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
-   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
-   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
-   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
-   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
-   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
-   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
-   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
-   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
-   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
-   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
-   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
-   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
-   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
-   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
-   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
-   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
-   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
-   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
-   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
-   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
-   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
-   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
-   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
-   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
-   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
-   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
-   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
-   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
-   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
-   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
-   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
-   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
-   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
-   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
-   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
-   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
-   FFS_PLOL => FFS_PLOL,
-   FFS_RLOL_0 => FFS_RLOL_0,
-   FFS_RLOL_1 => FFS_RLOL_1,
-   FFS_RLOL_2 => FFS_RLOL_2,
-   FFS_RLOL_3 => FFS_RLOL_3,
-   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
-   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
-   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
-   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
-   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
-   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
-   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
-   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
-   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
-   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
-   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
-   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
-   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
-   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
-   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
-   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
-   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
-   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
-   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
-   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
-   PCIE_RXVALID_0 => PCIE_RXVALID_0,
-   PCIE_RXVALID_1 => PCIE_RXVALID_1,
-   PCIE_RXVALID_2 => PCIE_RXVALID_2,
-   PCIE_RXVALID_3 => PCIE_RXVALID_3,
-   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
-   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
-   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
-   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
-   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
-   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
-   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
-   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
-   LDR_RX2CORE_0 => LDR_RX2CORE_0,
-   LDR_RX2CORE_1 => LDR_RX2CORE_1,
-   LDR_RX2CORE_2 => LDR_RX2CORE_2,
-   LDR_RX2CORE_3 => LDR_RX2CORE_3,
-   REFCK2CORE => REFCK2CORE,
-   SCIINT => SCIINT,
-   SCIRDATA0 => SCIRDATA0,
-   SCIRDATA1 => SCIRDATA1,
-   SCIRDATA2 => SCIRDATA2,
-   SCIRDATA3 => SCIRDATA3,
-   SCIRDATA4 => SCIRDATA4,
-   SCIRDATA5 => SCIRDATA5,
-   SCIRDATA6 => SCIRDATA6,
-   SCIRDATA7 => SCIRDATA7,
-   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
-   REFCLK_TO_NQ => REFCLK_TO_NQ
-   );
-
-end PCSD_arch;
-
---synopsys translate_on
-
---THIS MODULE IS INSTANTIATED PER RX CHANNEL
---Reset Sequence Generator
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-                                                                                              
-entity sfp_1_200_intrx_reset_sm is
-generic (count_index: integer :=18);
-port (
-   rst_n       : in std_logic;
-   refclkdiv2        : in std_logic;
-   tx_pll_lol_qd_s   : in std_logic;
-   rx_serdes_rst_ch_c: out std_logic;
-   rx_cdr_lol_ch_s   : in std_logic;
-   rx_los_low_ch_s   : in std_logic;
-   rx_pcs_rst_ch_c   : out std_logic
-);
-end sfp_1_200_intrx_reset_sm ;
-                                                                                              
-architecture rx_reset_sm_arch of sfp_1_200_intrx_reset_sm is
-                                                                                              
-type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
-                                                                                              
-signal   cs:      statetype;  -- current state of lsm
-signal   ns:      statetype;  -- next state of lsm
-attribute syn_encoding : string;
-attribute syn_encoding of cs : signal is "safe";
-attribute syn_encoding of ns : signal is "safe";
-                                                                                              
-signal   tx_pll_lol_qd_s_int: std_logic;
-signal   rx_los_low_int:         std_logic;
-signal   plol_los_int:        std_logic;
-signal   rx_lol_los  :  std_logic;
-signal   rx_lol_los_int:      std_logic;
-signal   rx_lol_los_del:      std_logic;
-signal   rx_pcs_rst_ch_c_int: std_logic;
-signal   rx_serdes_rst_ch_c_int: std_logic;
-                                                                                              
-signal   reset_timer1:  std_logic;
-signal   reset_timer2:  std_logic;
-                                                                                              
-signal   counter1:   std_logic_vector(1 downto 0);
-signal   TIMER1:  std_logic;
-                                                                                              
-signal   counter2: std_logic_vector(18 downto 0);
-signal   TIMER2   : std_logic;
-signal   rstn_m1:       std_logic;                                           
-signal   rstn_m2:       std_logic;                                           
-signal   sync_rst_n:       std_logic;                                                                                                                                      
-begin
-
-process (refclkdiv2, rst_n)
-begin
-   if rst_n = '0' then
-      rstn_m1 <= '0';
-      rstn_m2 <= '0';
-   else if rising_edge(refclkdiv2) then
-      rstn_m1 <= '1';
-      rstn_m2 <= rstn_m1;
-   end if;
-   end if;
-end process;
-
-   sync_rst_n <= rstn_m2;                   
-                                                                                              
-rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
-                                                                                              
-process(refclkdiv2, sync_rst_n)
-begin
-   if  sync_rst_n = '0' then
-         cs <= WAIT_FOR_PLOL;
-         rx_lol_los_int <= '1';
-         rx_lol_los_del <= '1';
-         tx_pll_lol_qd_s_int <= '1';
-         rx_pcs_rst_ch_c <= '1';
-         rx_serdes_rst_ch_c <= '0';
-         rx_los_low_int <= '1';
-      else if rising_edge(refclkdiv2) then
-         cs <= ns;
-         rx_lol_los_del <= rx_lol_los;
-         rx_lol_los_int <= rx_lol_los_del;
-         tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
-         rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
-         rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
-         rx_los_low_int <= rx_los_low_ch_s;
-      end if;
-   end if;
-end process;
-                                                                                              
---TIMER1 = 3NS;
---Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
---A 1 bit counter  counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
-                                                                                              
-process(refclkdiv2, reset_timer1)
-begin
-   if rising_edge(refclkdiv2) then
-      if reset_timer1 = '1' then
-         counter1 <= "00";
-         TIMER1 <= '0';
-      else
-         if counter1(1) = '1' then
-            TIMER1 <='1';
-         else
-            TIMER1 <='0';
-            counter1 <= counter1 + 1 ;
-         end if;
-      end if;
-   end if;
-end process;
-                                                                                              
---TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
---An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-                                                                                              
-process(refclkdiv2, reset_timer2)
-begin
-   if rising_edge(refclkdiv2) then
-      if reset_timer2 = '1' then
-         counter2 <= "0000000000000000000";
-         TIMER2 <= '0';
-      else
-         if counter2(count_index) = '1' then
-            TIMER2 <='1';
-         else
-            TIMER2 <='0';
-            counter2 <= counter2 + 1 ;
-         end if;
-      end if;
-   end if;
-end process;
-                                                                                              
-                                                                                              
-process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
-begin
-      reset_timer1 <= '0';
-      reset_timer2 <= '0';
-                                                                                              
-   case cs is
-      when WAIT_FOR_PLOL =>
-         rx_pcs_rst_ch_c_int <= '1';
-         rx_serdes_rst_ch_c_int <= '0';
-         if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then  --Also make sure A Signal
-            ns <= WAIT_FOR_PLOL;             --is Present prior to moving to the next
-         else
-            ns <= RX_SERDES_RESET;
-            end if;
-                                                                                              
-       when RX_SERDES_RESET =>
-         rx_pcs_rst_ch_c_int <= '1';
-         rx_serdes_rst_ch_c_int <= '1';
-         reset_timer1 <= '1';
-            ns <= WAIT_FOR_TIMER1;
-                                                                                              
-                                                                                              
-      when WAIT_FOR_TIMER1 =>
-         rx_pcs_rst_ch_c_int <= '1';
-         rx_serdes_rst_ch_c_int <= '1';
-         if TIMER1 = '1' then
-            ns <= CHECK_LOL_LOS;
-         else
-            ns <= WAIT_FOR_TIMER1;
-            end if;
-                                                                                              
-      when CHECK_LOL_LOS =>
-         rx_pcs_rst_ch_c_int <= '1';
-         rx_serdes_rst_ch_c_int <= '0';
-         reset_timer2 <= '1';
-            ns <= WAIT_FOR_TIMER2;
-                                                                                              
-      when WAIT_FOR_TIMER2 =>
-         rx_pcs_rst_ch_c_int <= '1';
-         rx_serdes_rst_ch_c_int <= '0';
-         if rx_lol_los_int = rx_lol_los_del then   --NO RISING OR FALLING EDGES
-            if TIMER2 = '1' then
-               if rx_lol_los_int = '1' then
-                  ns <= WAIT_FOR_PLOL;
-               else
-                  ns <= NORMAL;
-               end if;
-            else
-               ns <= WAIT_FOR_TIMER2;
-            end if;
-         else
-               ns <= CHECK_LOL_LOS;    --RESET TIMER2
-         end if;
-                                                                                              
-      when NORMAL =>
-         rx_pcs_rst_ch_c_int <= '0';
-         rx_serdes_rst_ch_c_int <= '0';
-         if rx_lol_los_int = '1' then
-            ns <= WAIT_FOR_PLOL;
-         else
-            ns <= NORMAL;
-         end if;
-                                                                                              
-      when others =>
-         ns <= WAIT_FOR_PLOL;
-                                                                                              
-      end case;
-                                                                                              
-end process;
-                                                                                              
-                                                                                              
-end rx_reset_sm_arch;
-
---THIS MODULE IS INSTANTIATED PER TX  QUAD
---TX Reset Sequence state machine--
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-                                                                                              
-entity sfp_1_200_inttx_reset_sm is
-generic (count_index: integer :=18);
-port (
-   rst_n          : in std_logic;
-   refclkdiv2      : in std_logic;
-   tx_pll_lol_qd_s : in std_logic;
-   rst_qd_c    : out std_logic;
-   tx_pcs_rst_ch_c : out std_logic
-   );
-end sfp_1_200_inttx_reset_sm;
-                                                                                              
-architecture tx_reset_sm_arch of sfp_1_200_inttx_reset_sm is
-                                                                                              
-type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
-                                                                                              
-signal   cs:      statetype;  -- current state of lsm
-signal   ns:      statetype;  -- next state of lsm
-attribute syn_encoding : string;
-attribute syn_encoding of cs : signal is "safe";
-attribute syn_encoding of ns : signal is "safe";
-                                                                                              
-signal   tx_pll_lol_qd_s_int  : std_logic;
-signal   tx_pcs_rst_ch_c_int  : std_logic_vector(3 downto 0);
-signal   rst_qd_c_int      : std_logic;
-                                                                                              
-signal   reset_timer1:  std_logic;
-signal   reset_timer2:  std_logic;
-                                                                                              
-signal   counter1:      std_logic_vector(2 downto 0);
-signal   TIMER1:        std_logic;
-                                                                                              
-signal   counter2:      std_logic_vector(18 downto 0);
-signal   TIMER2:        std_logic;
-
-signal   rstn_m1:       std_logic;                                                                                  
-signal   rstn_m2:       std_logic;                                                                                              
-signal   sync_rst_n:       std_logic;                                                                                              
-begin
-
-process (refclkdiv2, rst_n)
-begin
-   if rst_n = '0' then
-      rstn_m1 <= '0';
-      rstn_m2 <= '0';
-   else if rising_edge(refclkdiv2) then
-      rstn_m1 <= '1';
-      rstn_m2 <= rstn_m1;
-   end if;
-   end if;
-end process;
-   
-   sync_rst_n <= rstn_m2;                                                                                           
-process (refclkdiv2, sync_rst_n)
-begin
-   if sync_rst_n = '0' then
-      cs <= QUAD_RESET;
-      tx_pll_lol_qd_s_int <= '1';
-      tx_pcs_rst_ch_c <= '1';
-      rst_qd_c <= '1';
-   else if rising_edge(refclkdiv2) then
-      cs <= ns;
-      tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
-      tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0);
-      rst_qd_c <= rst_qd_c_int;
-   end if;
-   end if;
-end process;
---TIMER1 = 20ns;
---Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
--- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
-                                                                                              
-                                                                                              
-process (refclkdiv2, reset_timer1)
-begin
-   if rising_edge(refclkdiv2) then
-      if reset_timer1 = '1' then
-         counter1 <= "000";
-         TIMER1 <= '0';
-      else
-         if counter1(2) = '1' then
-            TIMER1 <= '1';
-         else
-            TIMER1 <='0';
-            counter1 <= counter1 + 1 ;
-         end if;
-      end if;
-   end if;
-end process;
-                                                                                              
-                                                                                              
---TIMER2 = 1,400,000 UI;
---WORST CASE CYCLES is with smallest multipier factor.
--- This would be with X8 clock multiplier in DIV2 mode
--- IN this casse, 1 UI = 2/8 REFCLK  CYCLES = 1/8 REFCLKDIV2 CYCLES
--- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
--- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
-                                                                                              
-                                                                                              
-process(refclkdiv2, reset_timer2)
-begin
-   if rising_edge(refclkdiv2) then
-      if reset_timer2 = '1' then
-         counter2 <= "0000000000000000000";
-         TIMER2 <= '0';
-      else
-         if counter2(count_index) = '1' then
-            TIMER2 <='1';
-         else
-            TIMER2 <='0';
-            counter2 <= counter2 + 1 ;
-         end if;
-      end if;
-   end if;
-end process;
-                                                                                              
-process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
-begin
-                                                                                              
-      reset_timer1 <= '0';
-      reset_timer2 <= '0';
-                                                                                              
-   case cs is
-                                                                                              
-      when QUAD_RESET   =>
-      tx_pcs_rst_ch_c_int <= "1111";
-      rst_qd_c_int <= '1';
-      reset_timer1 <= '1';
-         ns <= WAIT_FOR_TIMER1;
-                                                                                              
-      when WAIT_FOR_TIMER1 =>
-      tx_pcs_rst_ch_c_int <= "1111";
-      rst_qd_c_int <= '1';
-      if TIMER1 = '1' then
-         ns <= CHECK_PLOL;
-      else
-         ns <= WAIT_FOR_TIMER1;
-         end if;
-                                                                                              
-      when CHECK_PLOL   =>
-      tx_pcs_rst_ch_c_int <= "1111";
-      rst_qd_c_int <= '0';
-      reset_timer2 <= '1';
-         ns <= WAIT_FOR_TIMER2;
-                                                                                              
-      when WAIT_FOR_TIMER2 =>
-      tx_pcs_rst_ch_c_int <= "1111";
-      rst_qd_c_int <= '0';
-      if TIMER2 = '1' then
-         if tx_pll_lol_qd_s_int = '1' then
-            ns <= QUAD_RESET;
-         else
-            ns <= NORMAL;
-         end if;
-      else
-            ns <= WAIT_FOR_TIMER2;
-            end if;
-                                                                                              
-   when NORMAL =>
-      tx_pcs_rst_ch_c_int <= "0000";
-      rst_qd_c_int <= '0';
-      if tx_pll_lol_qd_s_int = '1' then
-         ns <= QUAD_RESET;
-      else
-         ns <= NORMAL;
-         end if;
-                                                                                              
-   when others =>
-      ns <=    QUAD_RESET;
-                                                                                              
-   end case;
-                                                                                              
-end process;
-                                                                                              
-end tx_reset_sm_arch;
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity sfp_1_200_int is
-   GENERIC (USER_CONFIG_FILE    :  String := "sfp_1_200_int.txt");
- port (
-------------------
--- CH0 --
--- CH1 --
-    hdinp_ch1, hdinn_ch1    :   in std_logic;
-    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
-    sci_sel_ch1    :   in std_logic;
-    rxiclk_ch1    :   in std_logic;
-    txiclk_ch1    :   in std_logic;
-    rx_full_clk_ch1   :   out std_logic;
-    rx_half_clk_ch1   :   out std_logic;
-    tx_full_clk_ch1   :   out std_logic;
-    tx_half_clk_ch1   :   out std_logic;
-    fpga_rxrefclk_ch1    :   in std_logic;
-    txdata_ch1    :   in std_logic_vector (15 downto 0);
-    tx_k_ch1    :   in std_logic_vector (1 downto 0);
-    tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
-    tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
-    rxdata_ch1   :   out std_logic_vector (15 downto 0);
-    rx_k_ch1   :   out std_logic_vector (1 downto 0);
-    rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
-    rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
-    sb_felb_ch1_c    :   in std_logic;
-    sb_felb_rst_ch1_c    :   in std_logic;
-    tx_pwrup_ch1_c    :   in std_logic;
-    rx_pwrup_ch1_c    :   in std_logic;
-    rx_los_low_ch1_s   :   out std_logic;
-    lsm_status_ch1_s   :   out std_logic;
-    rx_cdr_lol_ch1_s   :   out std_logic;
-    tx_div2_mode_ch1_c   : in std_logic;
-    rx_div2_mode_ch1_c   : in std_logic;
--- CH2 --
--- CH3 --
----- Miscillaneous ports
-    sci_wrdata    :   in std_logic_vector (7 downto 0);
-    sci_addr    :   in std_logic_vector (5 downto 0);
-    sci_rddata   :   out std_logic_vector (7 downto 0);
-    sci_sel_quad    :   in std_logic;
-    sci_rd    :   in std_logic;
-    sci_wrn    :   in std_logic;
-    fpga_txrefclk  :   in std_logic;
-    tx_serdes_rst_c    :   in std_logic;
-    tx_pll_lol_qd_s   :   out std_logic;
-    refclk2fpga   :   out std_logic;
-    rst_n      :   in std_logic;
-    serdes_rst_qd_c    :   in std_logic);
-
-end sfp_1_200_int;
-
-
-architecture sfp_1_200_int_arch of sfp_1_200_int is
-
-component VLO
-port (
-   Z : out std_logic);
-end component;
-
-component VHI
-port (
-   Z : out std_logic);
-end component;
-
-component sfp_1_200_intrx_reset_sm
-generic (count_index: integer :=18);
-port (
-   rst_n       : in std_logic;
-   refclkdiv2        : in std_logic;
-   tx_pll_lol_qd_s   : in std_logic;
-   rx_serdes_rst_ch_c: out std_logic;
-   rx_cdr_lol_ch_s   : in std_logic;
-   rx_los_low_ch_s   : in std_logic;
-   rx_pcs_rst_ch_c   : out std_logic
-);
-end component ;
-
-component sfp_1_200_inttx_reset_sm
-generic (count_index: integer :=18);
-port (
-   rst_n          : in std_logic;
-   refclkdiv2      : in std_logic;
-   tx_pll_lol_qd_s : in std_logic;
-   rst_qd_c    : out std_logic;
-   tx_pcs_rst_ch_c : out std_logic
-   );
-end component;
-
-component PCSD
---synopsys translate_off
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
-  );
---synopsys translate_on
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-   attribute CONFIG_FILE: string;
-   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
-   attribute QUAD_MODE: string;
-   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
-   attribute PLL_SRC: string;
-   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH1_CDR_SRC: string;
-   attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_REFCK2CORE: string;
-   attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
-   attribute black_box_pad_pin: string;
-   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal    tx_full_clk_ch1_sig   :   std_logic;
-
-signal    refclk2fpga_sig  :   std_logic;
-signal    tx_pll_lol_qd_sig  :   std_logic;
-signal    rx_los_low_ch0_sig  :   std_logic;
-signal    rx_los_low_ch1_sig  :   std_logic;
-signal    rx_los_low_ch2_sig  :   std_logic;
-signal    rx_los_low_ch3_sig  :   std_logic;
-signal    rx_cdr_lol_ch0_sig  :   std_logic;
-signal    rx_cdr_lol_ch1_sig  :   std_logic;
-signal    rx_cdr_lol_ch2_sig  :   std_logic;
-signal    rx_cdr_lol_ch3_sig  :   std_logic;
-
-signal    rx_serdes_rst_ch1_c  : std_logic;
-signal    rx_pcs_rst_ch1_c  : std_logic;
-
--- reset sequence for rx
-signal    refclkdiv2_rx_ch1  :   std_logic;
-
-signal    refclkdiv2_tx_ch  :   std_logic;
-signal    tx_pcs_rst_ch_c   :   std_logic;
-signal    rst_qd_c   :   std_logic;
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
-  refclk2fpga <= refclk2fpga_sig;
-    rx_los_low_ch1_s <= rx_los_low_ch1_sig;
-    rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
-  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
-  tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
-  generic map (CONFIG_FILE => USER_CONFIG_FILE,
-               QUAD_MODE => "SINGLE",
-               CH1_CDR_SRC => "REFCLK_CORE",
-               PLL_SRC  => "REFCLK_CORE"
-  )
---synopsys translate_on
-port map  (
-  REFCLKP => fpsc_vlo,
-  REFCLKN => fpsc_vlo,
-
------ CH0 -----
-  HDOUTP0 => open,
-  HDOUTN0 => open,
-  HDINP0 => fpsc_vlo,
-  HDINN0 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
-  PCIE_RXPOLARITY_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_1 => fpsc_vlo,
-  PCIE_RXVALID_0 => open,
-  PCIE_PHYSTATUS_0 => open,
-  SCISELCH0 => fpsc_vlo,
-  SCIENCH0 => fpsc_vlo,
-  FF_RXI_CLK_0 => fpsc_vlo,
-  FF_TXI_CLK_0 => fpsc_vlo,
-  FF_EBRD_CLK_0 => fpsc_vlo,
-  FF_RX_F_CLK_0 => open,
-  FF_RX_H_CLK_0 => open,
-  FF_TX_F_CLK_0 => open,
-  FF_TX_H_CLK_0 => open,
-  FFC_CK_CORE_RX_0 => fpsc_vlo,
-  FF_TX_D_0_0 => fpsc_vlo,
-  FF_TX_D_0_1 => fpsc_vlo,
-  FF_TX_D_0_2 => fpsc_vlo,
-  FF_TX_D_0_3 => fpsc_vlo,
-  FF_TX_D_0_4 => fpsc_vlo,
-  FF_TX_D_0_5 => fpsc_vlo,
-  FF_TX_D_0_6 => fpsc_vlo,
-  FF_TX_D_0_7 => fpsc_vlo,
-  FF_TX_D_0_8 => fpsc_vlo,
-  FF_TX_D_0_9 => fpsc_vlo,
-  FF_TX_D_0_10 => fpsc_vlo,
-  FF_TX_D_0_11 => fpsc_vlo,
-  FF_TX_D_0_12 => fpsc_vlo,
-  FF_TX_D_0_13 => fpsc_vlo,
-  FF_TX_D_0_14 => fpsc_vlo,
-  FF_TX_D_0_15 => fpsc_vlo,
-  FF_TX_D_0_16 => fpsc_vlo,
-  FF_TX_D_0_17 => fpsc_vlo,
-  FF_TX_D_0_18 => fpsc_vlo,
-  FF_TX_D_0_19 => fpsc_vlo,
-  FF_TX_D_0_20 => fpsc_vlo,
-  FF_TX_D_0_21 => fpsc_vlo,
-  FF_TX_D_0_22 => fpsc_vlo,
-  FF_TX_D_0_23 => fpsc_vlo,
-  FF_RX_D_0_0 => open,
-  FF_RX_D_0_1 => open,
-  FF_RX_D_0_2 => open,
-  FF_RX_D_0_3 => open,
-  FF_RX_D_0_4 => open,
-  FF_RX_D_0_5 => open,
-  FF_RX_D_0_6 => open,
-  FF_RX_D_0_7 => open,
-  FF_RX_D_0_8 => open,
-  FF_RX_D_0_9 => open,
-  FF_RX_D_0_10 => open,
-  FF_RX_D_0_11 => open,
-  FF_RX_D_0_12 => open,
-  FF_RX_D_0_13 => open,
-  FF_RX_D_0_14 => open,
-  FF_RX_D_0_15 => open,
-  FF_RX_D_0_16 => open,
-  FF_RX_D_0_17 => open,
-  FF_RX_D_0_18 => open,
-  FF_RX_D_0_19 => open,
-  FF_RX_D_0_20 => open,
-  FF_RX_D_0_21 => open,
-  FF_RX_D_0_22 => open,
-  FF_RX_D_0_23 => open,
-
-  FFC_RRST_0 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_0 => fpsc_vlo,
-  FFC_PFIFO_CLR_0 => fpsc_vlo,
-  FFC_SB_INV_RX_0 => fpsc_vlo,
-  FFC_PCIE_CT_0 => fpsc_vlo,
-  FFC_PCI_DET_EN_0 => fpsc_vlo,
-  FFC_FB_LOOPBACK_0 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
-  FFC_EI_EN_0 => fpsc_vlo,
-  FFC_LANE_TX_RST_0 => fpsc_vlo,
-  FFC_TXPWDNB_0 => fpsc_vlo,
-  FFC_LANE_RX_RST_0 => fpsc_vlo,
-  FFC_RXPWDNB_0 => fpsc_vlo,
-  FFS_RLOS_LO_0 => open,
-  FFS_RLOS_HI_0 => open,
-  FFS_PCIE_CON_0 => open,
-  FFS_PCIE_DONE_0 => open,
-  FFS_LS_SYNC_STATUS_0 => open,
-  FFS_CC_OVERRUN_0 => open,
-  FFS_CC_UNDERRUN_0 => open,
-  FFS_SKP_ADDED_0 => open,
-  FFS_SKP_DELETED_0 => open,
-  FFS_RLOL_0 => open,
-  FFS_RXFBFIFO_ERROR_0 => open,
-  FFS_TXFBFIFO_ERROR_0 => open,
-  LDR_CORE2TX_0 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
-  LDR_RX2CORE_0 => open,
-  FFS_CDR_TRAIN_DONE_0 => open,
-  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
-  FFC_RATE_MODE_TX_0 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
-  FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
-  HDOUTP1 => hdoutp_ch1,
-  HDOUTN1 => hdoutn_ch1,
-  HDINP1 => hdinp_ch1,
-  HDINN1 => hdinn_ch1,
-  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
-  PCIE_RXPOLARITY_1 => fpsc_vlo,
-  PCIE_POWERDOWN_1_0 => fpsc_vlo,
-  PCIE_POWERDOWN_1_1 => fpsc_vlo,
-  PCIE_RXVALID_1 => open,
-  PCIE_PHYSTATUS_1 => open,
-  SCISELCH1 => sci_sel_ch1,
-  SCIENCH1 => fpsc_vhi,
-  FF_RXI_CLK_1 => rxiclk_ch1,
-  FF_TXI_CLK_1 => txiclk_ch1,
-  FF_EBRD_CLK_1 => fpsc_vlo,
-  FF_RX_F_CLK_1 => rx_full_clk_ch1,
-  FF_RX_H_CLK_1 => rx_half_clk_ch1,
-  FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
-  FF_TX_H_CLK_1 => tx_half_clk_ch1,
-  FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
-  FF_TX_D_1_0 => txdata_ch1(0),
-  FF_TX_D_1_1 => txdata_ch1(1),
-  FF_TX_D_1_2 => txdata_ch1(2),
-  FF_TX_D_1_3 => txdata_ch1(3),
-  FF_TX_D_1_4 => txdata_ch1(4),
-  FF_TX_D_1_5 => txdata_ch1(5),
-  FF_TX_D_1_6 => txdata_ch1(6),
-  FF_TX_D_1_7 => txdata_ch1(7),
-  FF_TX_D_1_8 => tx_k_ch1(0),
-  FF_TX_D_1_9 => tx_force_disp_ch1(0),
-  FF_TX_D_1_10 => tx_disp_sel_ch1(0),
-  FF_TX_D_1_11 => fpsc_vlo,
-  FF_TX_D_1_12 => txdata_ch1(8),
-  FF_TX_D_1_13 => txdata_ch1(9),
-  FF_TX_D_1_14 => txdata_ch1(10),
-  FF_TX_D_1_15 => txdata_ch1(11),
-  FF_TX_D_1_16 => txdata_ch1(12),
-  FF_TX_D_1_17 => txdata_ch1(13),
-  FF_TX_D_1_18 => txdata_ch1(14),
-  FF_TX_D_1_19 => txdata_ch1(15),
-  FF_TX_D_1_20 => tx_k_ch1(1),
-  FF_TX_D_1_21 => tx_force_disp_ch1(1),
-  FF_TX_D_1_22 => tx_disp_sel_ch1(1),
-  FF_TX_D_1_23 => fpsc_vlo,
-  FF_RX_D_1_0 => rxdata_ch1(0),
-  FF_RX_D_1_1 => rxdata_ch1(1),
-  FF_RX_D_1_2 => rxdata_ch1(2),
-  FF_RX_D_1_3 => rxdata_ch1(3),
-  FF_RX_D_1_4 => rxdata_ch1(4),
-  FF_RX_D_1_5 => rxdata_ch1(5),
-  FF_RX_D_1_6 => rxdata_ch1(6),
-  FF_RX_D_1_7 => rxdata_ch1(7),
-  FF_RX_D_1_8 => rx_k_ch1(0),
-  FF_RX_D_1_9 => rx_disp_err_ch1(0),
-  FF_RX_D_1_10 => rx_cv_err_ch1(0),
-  FF_RX_D_1_11 => open,
-  FF_RX_D_1_12 => rxdata_ch1(8),
-  FF_RX_D_1_13 => rxdata_ch1(9),
-  FF_RX_D_1_14 => rxdata_ch1(10),
-  FF_RX_D_1_15 => rxdata_ch1(11),
-  FF_RX_D_1_16 => rxdata_ch1(12),
-  FF_RX_D_1_17 => rxdata_ch1(13),
-  FF_RX_D_1_18 => rxdata_ch1(14),
-  FF_RX_D_1_19 => rxdata_ch1(15),
-  FF_RX_D_1_20 => rx_k_ch1(1),
-  FF_RX_D_1_21 => rx_disp_err_ch1(1),
-  FF_RX_D_1_22 => rx_cv_err_ch1(1),
-  FF_RX_D_1_23 => open,
-
-  FFC_RRST_1 => rx_serdes_rst_ch1_c,
-  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
-  FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
-  FFC_SB_INV_RX_1 => fpsc_vlo,
-  FFC_PCIE_CT_1 => fpsc_vlo,
-  FFC_PCI_DET_EN_1 => fpsc_vlo,
-  FFC_FB_LOOPBACK_1 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
-  FFC_EI_EN_1 => fpsc_vlo,
-  FFC_LANE_TX_RST_1 => tx_pcs_rst_ch_c,
-  FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
-  FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
-  FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
-  FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
-  FFS_RLOS_HI_1 => open,
-  FFS_PCIE_CON_1 => open,
-  FFS_PCIE_DONE_1 => open,
-  FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
-  FFS_CC_OVERRUN_1 => open,
-  FFS_CC_UNDERRUN_1 => open,
-  FFS_SKP_ADDED_1 => open,
-  FFS_SKP_DELETED_1 => open,
-  FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
-  FFS_RXFBFIFO_ERROR_1 => open,
-  FFS_TXFBFIFO_ERROR_1 => open,
-  LDR_CORE2TX_1 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
-  LDR_RX2CORE_1 => open,
-  FFS_CDR_TRAIN_DONE_1 => open,
-  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
-  FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
-  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
-  FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
-
------ CH2 -----
-  HDOUTP2 => open,
-  HDOUTN2 => open,
-  HDINP2 => fpsc_vlo,
-  HDINN2 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
-  PCIE_RXPOLARITY_2 => fpsc_vlo,
-  PCIE_POWERDOWN_2_0 => fpsc_vlo,
-  PCIE_POWERDOWN_2_1 => fpsc_vlo,
-  PCIE_RXVALID_2 => open,
-  PCIE_PHYSTATUS_2 => open,
-  SCISELCH2 => fpsc_vlo,
-  SCIENCH2 => fpsc_vlo,
-  FF_RXI_CLK_2 => fpsc_vlo,
-  FF_TXI_CLK_2 => fpsc_vlo,
-  FF_EBRD_CLK_2 => fpsc_vlo,
-  FF_RX_F_CLK_2 => open,
-  FF_RX_H_CLK_2 => open,
-  FF_TX_F_CLK_2 => open,
-  FF_TX_H_CLK_2 => open,
-  FFC_CK_CORE_RX_2 => fpsc_vlo,
-  FF_TX_D_2_0 => fpsc_vlo,
-  FF_TX_D_2_1 => fpsc_vlo,
-  FF_TX_D_2_2 => fpsc_vlo,
-  FF_TX_D_2_3 => fpsc_vlo,
-  FF_TX_D_2_4 => fpsc_vlo,
-  FF_TX_D_2_5 => fpsc_vlo,
-  FF_TX_D_2_6 => fpsc_vlo,
-  FF_TX_D_2_7 => fpsc_vlo,
-  FF_TX_D_2_8 => fpsc_vlo,
-  FF_TX_D_2_9 => fpsc_vlo,
-  FF_TX_D_2_10 => fpsc_vlo,
-  FF_TX_D_2_11 => fpsc_vlo,
-  FF_TX_D_2_12 => fpsc_vlo,
-  FF_TX_D_2_13 => fpsc_vlo,
-  FF_TX_D_2_14 => fpsc_vlo,
-  FF_TX_D_2_15 => fpsc_vlo,
-  FF_TX_D_2_16 => fpsc_vlo,
-  FF_TX_D_2_17 => fpsc_vlo,
-  FF_TX_D_2_18 => fpsc_vlo,
-  FF_TX_D_2_19 => fpsc_vlo,
-  FF_TX_D_2_20 => fpsc_vlo,
-  FF_TX_D_2_21 => fpsc_vlo,
-  FF_TX_D_2_22 => fpsc_vlo,
-  FF_TX_D_2_23 => fpsc_vlo,
-  FF_RX_D_2_0 => open,
-  FF_RX_D_2_1 => open,
-  FF_RX_D_2_2 => open,
-  FF_RX_D_2_3 => open,
-  FF_RX_D_2_4 => open,
-  FF_RX_D_2_5 => open,
-  FF_RX_D_2_6 => open,
-  FF_RX_D_2_7 => open,
-  FF_RX_D_2_8 => open,
-  FF_RX_D_2_9 => open,
-  FF_RX_D_2_10 => open,
-  FF_RX_D_2_11 => open,
-  FF_RX_D_2_12 => open,
-  FF_RX_D_2_13 => open,
-  FF_RX_D_2_14 => open,
-  FF_RX_D_2_15 => open,
-  FF_RX_D_2_16 => open,
-  FF_RX_D_2_17 => open,
-  FF_RX_D_2_18 => open,
-  FF_RX_D_2_19 => open,
-  FF_RX_D_2_20 => open,
-  FF_RX_D_2_21 => open,
-  FF_RX_D_2_22 => open,
-  FF_RX_D_2_23 => open,
-
-  FFC_RRST_2 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_2 => fpsc_vlo,
-  FFC_PFIFO_CLR_2 => fpsc_vlo,
-  FFC_SB_INV_RX_2 => fpsc_vlo,
-  FFC_PCIE_CT_2 => fpsc_vlo,
-  FFC_PCI_DET_EN_2 => fpsc_vlo,
-  FFC_FB_LOOPBACK_2 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
-  FFC_EI_EN_2 => fpsc_vlo,
-  FFC_LANE_TX_RST_2 => fpsc_vlo,
-  FFC_TXPWDNB_2 => fpsc_vlo,
-  FFC_LANE_RX_RST_2 => fpsc_vlo,
-  FFC_RXPWDNB_2 => fpsc_vlo,
-  FFS_RLOS_LO_2 => open,
-  FFS_RLOS_HI_2 => open,
-  FFS_PCIE_CON_2 => open,
-  FFS_PCIE_DONE_2 => open,
-  FFS_LS_SYNC_STATUS_2 => open,
-  FFS_CC_OVERRUN_2 => open,
-  FFS_CC_UNDERRUN_2 => open,
-  FFS_SKP_ADDED_2 => open,
-  FFS_SKP_DELETED_2 => open,
-  FFS_RLOL_2 => open,
-  FFS_RXFBFIFO_ERROR_2 => open,
-  FFS_TXFBFIFO_ERROR_2 => open,
-  LDR_CORE2TX_2 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
-  LDR_RX2CORE_2 => open,
-  FFS_CDR_TRAIN_DONE_2 => open,
-  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
-  FFC_RATE_MODE_TX_2 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
-  FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
-  HDOUTP3 => open,
-  HDOUTN3 => open,
-  HDINP3 => fpsc_vlo,
-  HDINN3 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
-  PCIE_RXPOLARITY_3 => fpsc_vlo,
-  PCIE_POWERDOWN_3_0 => fpsc_vlo,
-  PCIE_POWERDOWN_3_1 => fpsc_vlo,
-  PCIE_RXVALID_3 => open,
-  PCIE_PHYSTATUS_3 => open,
-  SCISELCH3 => fpsc_vlo,
-  SCIENCH3 => fpsc_vlo,
-  FF_RXI_CLK_3 => fpsc_vlo,
-  FF_TXI_CLK_3 => fpsc_vlo,
-  FF_EBRD_CLK_3 => fpsc_vlo,
-  FF_RX_F_CLK_3 => open,
-  FF_RX_H_CLK_3 => open,
-  FF_TX_F_CLK_3 => open,
-  FF_TX_H_CLK_3 => open,
-  FFC_CK_CORE_RX_3 => fpsc_vlo,
-  FF_TX_D_3_0 => fpsc_vlo,
-  FF_TX_D_3_1 => fpsc_vlo,
-  FF_TX_D_3_2 => fpsc_vlo,
-  FF_TX_D_3_3 => fpsc_vlo,
-  FF_TX_D_3_4 => fpsc_vlo,
-  FF_TX_D_3_5 => fpsc_vlo,
-  FF_TX_D_3_6 => fpsc_vlo,
-  FF_TX_D_3_7 => fpsc_vlo,
-  FF_TX_D_3_8 => fpsc_vlo,
-  FF_TX_D_3_9 => fpsc_vlo,
-  FF_TX_D_3_10 => fpsc_vlo,
-  FF_TX_D_3_11 => fpsc_vlo,
-  FF_TX_D_3_12 => fpsc_vlo,
-  FF_TX_D_3_13 => fpsc_vlo,
-  FF_TX_D_3_14 => fpsc_vlo,
-  FF_TX_D_3_15 => fpsc_vlo,
-  FF_TX_D_3_16 => fpsc_vlo,
-  FF_TX_D_3_17 => fpsc_vlo,
-  FF_TX_D_3_18 => fpsc_vlo,
-  FF_TX_D_3_19 => fpsc_vlo,
-  FF_TX_D_3_20 => fpsc_vlo,
-  FF_TX_D_3_21 => fpsc_vlo,
-  FF_TX_D_3_22 => fpsc_vlo,
-  FF_TX_D_3_23 => fpsc_vlo,
-  FF_RX_D_3_0 => open,
-  FF_RX_D_3_1 => open,
-  FF_RX_D_3_2 => open,
-  FF_RX_D_3_3 => open,
-  FF_RX_D_3_4 => open,
-  FF_RX_D_3_5 => open,
-  FF_RX_D_3_6 => open,
-  FF_RX_D_3_7 => open,
-  FF_RX_D_3_8 => open,
-  FF_RX_D_3_9 => open,
-  FF_RX_D_3_10 => open,
-  FF_RX_D_3_11 => open,
-  FF_RX_D_3_12 => open,
-  FF_RX_D_3_13 => open,
-  FF_RX_D_3_14 => open,
-  FF_RX_D_3_15 => open,
-  FF_RX_D_3_16 => open,
-  FF_RX_D_3_17 => open,
-  FF_RX_D_3_18 => open,
-  FF_RX_D_3_19 => open,
-  FF_RX_D_3_20 => open,
-  FF_RX_D_3_21 => open,
-  FF_RX_D_3_22 => open,
-  FF_RX_D_3_23 => open,
-
-  FFC_RRST_3 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_3 => fpsc_vlo,
-  FFC_PFIFO_CLR_3 => fpsc_vlo,
-  FFC_SB_INV_RX_3 => fpsc_vlo,
-  FFC_PCIE_CT_3 => fpsc_vlo,
-  FFC_PCI_DET_EN_3 => fpsc_vlo,
-  FFC_FB_LOOPBACK_3 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
-  FFC_EI_EN_3 => fpsc_vlo,
-  FFC_LANE_TX_RST_3 => fpsc_vlo,
-  FFC_TXPWDNB_3 => fpsc_vlo,
-  FFC_LANE_RX_RST_3 => fpsc_vlo,
-  FFC_RXPWDNB_3 => fpsc_vlo,
-  FFS_RLOS_LO_3 => open,
-  FFS_RLOS_HI_3 => open,
-  FFS_PCIE_CON_3 => open,
-  FFS_PCIE_DONE_3 => open,
-  FFS_LS_SYNC_STATUS_3 => open,
-  FFS_CC_OVERRUN_3 => open,
-  FFS_CC_UNDERRUN_3 => open,
-  FFS_SKP_ADDED_3 => open,
-  FFS_SKP_DELETED_3 => open,
-  FFS_RLOL_3 => open,
-  FFS_RXFBFIFO_ERROR_3 => open,
-  FFS_TXFBFIFO_ERROR_3 => open,
-  LDR_CORE2TX_3 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
-  LDR_RX2CORE_3 => open,
-  FFS_CDR_TRAIN_DONE_3 => open,
-  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
-  FFC_RATE_MODE_TX_3 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
-  FFC_RATE_MODE_RX_3 => fpsc_vlo,
-
------ Auxilliary ----
-  SCIWDATA7 => sci_wrdata(7),
-  SCIWDATA6 => sci_wrdata(6),
-  SCIWDATA5 => sci_wrdata(5),
-  SCIWDATA4 => sci_wrdata(4),
-  SCIWDATA3 => sci_wrdata(3),
-  SCIWDATA2 => sci_wrdata(2),
-  SCIWDATA1 => sci_wrdata(1),
-  SCIWDATA0 => sci_wrdata(0),
-  SCIADDR5 => sci_addr(5),
-  SCIADDR4 => sci_addr(4),
-  SCIADDR3 => sci_addr(3),
-  SCIADDR2 => sci_addr(2),
-  SCIADDR1 => sci_addr(1),
-  SCIADDR0 => sci_addr(0),
-  SCIRDATA7 => sci_rddata(7),
-  SCIRDATA6 => sci_rddata(6),
-  SCIRDATA5 => sci_rddata(5),
-  SCIRDATA4 => sci_rddata(4),
-  SCIRDATA3 => sci_rddata(3),
-  SCIRDATA2 => sci_rddata(2),
-  SCIRDATA1 => sci_rddata(1),
-  SCIRDATA0 => sci_rddata(0),
-  SCIENAUX => fpsc_vhi,
-  SCISELAUX => sci_sel_quad,
-  SCIRD => sci_rd,
-  SCIWSTN => sci_wrn,
-  CYAWSTN => fpsc_vlo,
-  SCIINT => open,
-  FFC_CK_CORE_TX => fpga_txrefclk,
-  FFC_MACRO_RST => serdes_rst_qd_c,
-  FFC_QUAD_RST => rst_qd_c,
-  FFC_TRST => tx_serdes_rst_c,
-  FFS_PLOL => tx_pll_lol_qd_sig,
-  FFC_SYNC_TOGGLE => fpsc_vlo,
-  REFCK2CORE => refclk2fpga_sig,
-  CIN0 => fpsc_vlo,
-  CIN1 => fpsc_vlo,
-  CIN2 => fpsc_vlo,
-  CIN3 => fpsc_vlo,
-  CIN4 => fpsc_vlo,
-  CIN5 => fpsc_vlo,
-  CIN6 => fpsc_vlo,
-  CIN7 => fpsc_vlo,
-  CIN8 => fpsc_vlo,
-  CIN9 => fpsc_vlo,
-  CIN10 => fpsc_vlo,
-  CIN11 => fpsc_vlo,
-  COUT0 => open,
-  COUT1 => open,
-  COUT2 => open,
-  COUT3 => open,
-  COUT4 => open,
-  COUT5 => open,
-  COUT6 => open,
-  COUT7 => open,
-  COUT8 => open,
-  COUT9 => open,
-  COUT10 => open,
-  COUT11 => open,
-  COUT12 => open,
-  COUT13 => open,
-  COUT14 => open,
-  COUT15 => open,
-  COUT16 => open,
-  COUT17 => open,
-  COUT18 => open,
-  COUT19 => open,
-  REFCLK_FROM_NQ => refclk_from_nq,
-  REFCLK_TO_NQ => open);
-
--- reset sequence for rx
-                                                                                              
-  P2 : PROCESS(fpga_rxrefclk_ch1, rst_n)
-  BEGIN
-     IF (rst_n = '0') THEN
-         refclkdiv2_rx_ch1 <= '0';
-     ELSIF (fpga_rxrefclk_ch1'event and fpga_rxrefclk_ch1 = '1') THEN
-         refclkdiv2_rx_ch1 <= not refclkdiv2_rx_ch1;
-     END IF;
-  END PROCESS;
-                                                                                              
-rx_reset_sm_ch1 : sfp_1_200_intrx_reset_sm
---synopsys translate_off
-  generic map (count_index => 4)
---synopsys translate_on
-port map  (
-  refclkdiv2 => refclkdiv2_rx_ch1,
-  rst_n => rst_n,
-  rx_cdr_lol_ch_s => rx_cdr_lol_ch1_sig,
-  rx_los_low_ch_s => rx_los_low_ch1_sig,
-  tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
-  rx_pcs_rst_ch_c => rx_pcs_rst_ch1_c,
-  rx_serdes_rst_ch_c => rx_serdes_rst_ch1_c);
-                                                                                              
-                                                                                              
-                                                                                              
-                                                                                              
-  P5 : PROCESS(fpga_txrefclk, rst_n)
-  BEGIN
-     IF (rst_n = '0') THEN
-         refclkdiv2_tx_ch <= '0';
-     ELSIF (fpga_txrefclk'event and fpga_txrefclk = '1') THEN
-         refclkdiv2_tx_ch <= not refclkdiv2_tx_ch;
-     END IF;
-  END PROCESS;
-
--- reset sequence for tx
-tx_reset_sm_ch : sfp_1_200_inttx_reset_sm 
---synopsys translate_off
-  generic map (count_index => 4)
---synopsys translate_on
-port map  (
-  rst_n => rst_n,
-  refclkdiv2 => refclkdiv2_tx_ch,
-  tx_pll_lol_qd_s => tx_pll_lol_qd_sig,
-  rst_qd_c => rst_qd_c,
-  tx_pcs_rst_ch_c => tx_pcs_rst_ch_c
-  );
-                                                                                              
-                                                                                              
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
-   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
-   IF (open_status = name_error) THEN
-      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
-      severity ERROR;
-   END IF;
-   wait;
-END PROCESS;
---synopsys translate_on
-end sfp_1_200_int_arch ;
diff --git a/code/ip/sfp_2_200_int.ipx b/code/ip/sfp_2_200_int.ipx
deleted file mode 100644
index 9d0d20d..0000000
--- a/code/ip/sfp_2_200_int.ipx
+++ /dev/null
@@ -1,11 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="sfp_2_200_int" module="sfp_2_200_int" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 12 10 11:11:13.056" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
-  <Package>
-		<File name="sfp_2_200_int.lpc" type="lpc" modified="2014 12 10 11:10:10.000"/>
-		<File name="sfp_2_200_int.pp" type="pp" modified="2014 12 10 11:10:10.000"/>
-		<File name="sfp_2_200_int.sym" type="sym" modified="2014 12 10 11:10:10.000"/>
-		<File name="sfp_2_200_int.tft" type="tft" modified="2014 12 10 11:10:10.000"/>
-		<File name="sfp_2_200_int.txt" type="pcs_module" modified="2014 12 10 11:10:10.000"/>
-		<File name="sfp_2_200_int.vhd" type="top_level_vhdl" modified="2014 12 10 11:10:10.000"/>
-  </Package>
-</DiamondModule>
diff --git a/code/ip/sfp_2_200_int.lpc b/code/ip/sfp_2_200_int.lpc
deleted file mode 100644
index 0ef5397..0000000
--- a/code/ip/sfp_2_200_int.lpc
+++ /dev/null
@@ -1,258 +0,0 @@
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.2
-ModuleName=sfp_2_200_int
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=12/10/2014
-Time=11:10:10
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=DISABLED
-_mode1=RXTX
-_mode2=DISABLED
-_mode3=RXTX
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=DISABLED
-_tx_protocol1=G8B10B
-_tx_protocol2=DISABLED
-_tx_protocol3=G8B10B
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=16
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=ENABLED
-_tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=DISABLED
-_tx_ficlk_rate0=200
-_tx_ficlk_rate1=100
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=EXTERNAL
-_pll_rxsrc1=INTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2.5
-_rx_datarange1=2
-_rx_datarange2=2.5
-_rx_datarange3=2
-_rx_protocol0=DISABLED
-_rx_protocol1=G8B10B
-_rx_protocol2=DISABLED
-_rx_protocol3=G8B10B
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=250.0
-_rxrefclk_rate1=200
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=200
-_rx_data_width0=8
-_rx_data_width1=16
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=ENABLED
-_rx_fifo1=ENABLED
-_rx_fifo2=ENABLED
-_rx_fifo3=DISABLED
-_rx_ficlk_rate0=250.0
-_rx_ficlk_rate1=100
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=AC
-_rx_dcc1=DC
-_rx_dcc2=AC
-_rx_dcc3=DC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=00
-_k01=01
-_k02=00
-_k03=00
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00000000
-_byten01=00011100
-_byten02=00000000
-_byten03=00000000
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-sfp_2_200_int.pp=pp
-sfp_2_200_int.tft=tft
-sfp_2_200_int.txt=pcs_module
-sfp_2_200_int.sym=sym
diff --git a/code/ip/sfp_2_200_int.txt b/code/ip/sfp_2_200_int.txt
deleted file mode 100644
index 82c5a8a..0000000
--- a/code/ip/sfp_2_200_int.txt
+++ /dev/null
@@ -1,93 +0,0 @@
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH1_PROTOCOL            "G8B10B"
-CH3_PROTOCOL            "G8B10B"
-CH0_MODE                "DISABLED"
-CH1_MODE                "RXTX"
-CH2_MODE                "DISABLED"
-CH3_MODE                "RXTX"
-CH1_CDR_SRC       "REFCLK_CORE"
-CH3_CDR_SRC       "REFCLK_CORE"
-PLL_SRC                 "REFCLK_CORE"
-TX_DATARATE_RANGE       "MEDHIGH"
-CH1_RX_DATARATE_RANGE   "MEDHIGH"
-CH3_RX_DATARATE_RANGE   "MEDHIGH"
-REFCK_MULT              "10X"
-#REFCLK_RATE            200
-CH1_RX_DATA_RATE        "FULL"
-CH3_RX_DATA_RATE        "FULL"
-CH1_TX_DATA_RATE        "FULL"
-CH3_TX_DATA_RATE        "FULL"
-CH1_TX_DATA_WIDTH       "16"
-CH3_TX_DATA_WIDTH       "8"
-CH1_RX_DATA_WIDTH        "16"
-CH3_RX_DATA_WIDTH        "8"
-CH1_TX_FIFO       "ENABLED"
-CH3_TX_FIFO       "DISABLED"
-CH1_RX_FIFO        "ENABLED"
-CH3_RX_FIFO        "DISABLED"
-CH1_TDRV      "0"
-CH3_TDRV      "0"
-#CH1_TX_FICLK_RATE      100
-#CH3_TX_FICLK_RATE      200
-#CH1_RXREFCLK_RATE        "200"
-#CH3_RXREFCLK_RATE        "200"
-#CH1_RX_FICLK_RATE      100
-#CH3_RX_FICLK_RATE      200
-CH1_TX_PRE              "DISABLED"
-CH3_TX_PRE              "DISABLED"
-CH1_RTERM_TX            "50"
-CH3_RTERM_TX            "50"
-CH1_RX_EQ               "DISABLED"
-CH3_RX_EQ               "DISABLED"
-CH1_RTERM_RX            "50"
-CH3_RTERM_RX            "50"
-CH1_RX_DCC              "DC"
-CH3_RX_DCC              "DC"
-CH1_LOS_THRESHOLD_LO       "2"
-CH3_LOS_THRESHOLD_LO       "2"
-PLL_TERM                "50"
-PLL_DCC                 "AC"
-PLL_LOL_SET             "0"
-CH1_TX_SB               "DISABLED"
-CH3_TX_SB               "DISABLED"
-CH1_RX_SB               "DISABLED"
-CH3_RX_SB               "DISABLED"
-CH1_TX_8B10B            "ENABLED"
-CH3_TX_8B10B            "ENABLED"
-CH1_RX_8B10B            "ENABLED"
-CH3_RX_8B10B            "ENABLED"
-CH1_COMMA_A             "1100000101"
-CH3_COMMA_A             "1100000101"
-CH1_COMMA_B             "0011111010"
-CH3_COMMA_B             "0011111010"
-CH1_COMMA_M             "1111111100"
-CH3_COMMA_M             "1111111100"
-CH1_RXWA                "ENABLED"
-CH3_RXWA                "ENABLED"
-CH1_ILSM                "ENABLED"
-CH3_ILSM                "ENABLED"
-CH1_CTC                 "DISABLED"
-CH3_CTC                 "DISABLED"
-CH1_CC_MATCH4           "0100011100"
-CH3_CC_MATCH4           "0000000000"
-CH1_CC_MATCH_MODE       "1"
-CH3_CC_MATCH_MODE       "1"
-CH1_CC_MIN_IPG          "3"
-CH3_CC_MIN_IPG          "3"
-CCHMARK                 "9"
-CCLMARK                 "7"
-CH1_SSLB                "DISABLED"
-CH3_SSLB                "DISABLED"
-CH1_SPLBPORTS           "DISABLED"
-CH3_SPLBPORTS           "DISABLED"
-CH1_PCSLBPORTS          "DISABLED"
-CH3_PCSLBPORTS          "DISABLED"
-INT_ALL                 "DISABLED"
-QD_REFCK2CORE           "ENABLED"
-
-
diff --git a/code/ip/sfp_2_200_int.vhd b/code/ip/sfp_2_200_int.vhd
deleted file mode 100644
index d655aa6..0000000
--- a/code/ip/sfp_2_200_int.vhd
+++ /dev/null
@@ -1,2739 +0,0 @@
-
-                                                                                                         
-
---synopsys translate_off
-
-library pcsd_work;
-use pcsd_work.all;
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-entity PCSD is
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
---  CONFIG_FILE : String  := "sfp_2_200_int.txt";
---  QUAD_MODE : String := "SINGLE";
---  CH0_CDR_SRC   : String := "REFCLK_EXT";
---  CH1_CDR_SRC   : String := "REFCLK_CORE";
---  CH2_CDR_SRC   : String := "REFCLK_EXT";
---  CH3_CDR_SRC   : String := "REFCLK_CORE";
---  PLL_SRC   : String := "REFCLK_CORE"
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-
-end PCSD;
-
-architecture PCSD_arch of PCSD is
-
-
-component PCSD_sim
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String;
-  CH1_CDR_SRC   : String;
-  CH2_CDR_SRC   : String;
-  CH3_CDR_SRC   : String;
-  PLL_SRC   : String
-  );
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-
-begin
-
-PCSD_sim_inst : PCSD_sim
-generic map (
-  CONFIG_FILE => CONFIG_FILE,
-  QUAD_MODE => QUAD_MODE,
-  CH0_CDR_SRC => CH0_CDR_SRC,
-  CH1_CDR_SRC => CH1_CDR_SRC,
-  CH2_CDR_SRC => CH2_CDR_SRC,
-  CH3_CDR_SRC => CH3_CDR_SRC,
-  PLL_SRC => PLL_SRC
-  )
-port map (
-   HDINN0 => HDINN0,
-   HDINN1 => HDINN1,
-   HDINN2 => HDINN2,
-   HDINN3 => HDINN3,
-   HDINP0 => HDINP0,
-   HDINP1 => HDINP1,
-   HDINP2 => HDINP2,
-   HDINP3 => HDINP3,
-   REFCLKN => REFCLKN,
-   REFCLKP => REFCLKP,
-   CIN11 => CIN11,
-   CIN10 => CIN10,
-   CIN9 => CIN9,
-   CIN8 => CIN8,
-   CIN7 => CIN7,
-   CIN6 => CIN6,
-   CIN5 => CIN5,
-   CIN4 => CIN4,
-   CIN3 => CIN3,
-   CIN2 => CIN2,
-   CIN1 => CIN1,
-   CIN0 => CIN0,
-   CYAWSTN => CYAWSTN,
-   FF_EBRD_CLK_3 => FF_EBRD_CLK_3,
-   FF_EBRD_CLK_2 => FF_EBRD_CLK_2,
-   FF_EBRD_CLK_1 => FF_EBRD_CLK_1,
-   FF_EBRD_CLK_0 => FF_EBRD_CLK_0,
-   FF_RXI_CLK_3 => FF_RXI_CLK_3,
-   FF_RXI_CLK_2 => FF_RXI_CLK_2,
-   FF_RXI_CLK_1 => FF_RXI_CLK_1,
-   FF_RXI_CLK_0 => FF_RXI_CLK_0,
-   FF_TX_D_0_0 => FF_TX_D_0_0,
-   FF_TX_D_0_1 => FF_TX_D_0_1,
-   FF_TX_D_0_2 => FF_TX_D_0_2,
-   FF_TX_D_0_3 => FF_TX_D_0_3,
-   FF_TX_D_0_4 => FF_TX_D_0_4,
-   FF_TX_D_0_5 => FF_TX_D_0_5,
-   FF_TX_D_0_6 => FF_TX_D_0_6,
-   FF_TX_D_0_7 => FF_TX_D_0_7,
-   FF_TX_D_0_8 => FF_TX_D_0_8,
-   FF_TX_D_0_9 => FF_TX_D_0_9,
-   FF_TX_D_0_10 => FF_TX_D_0_10,
-   FF_TX_D_0_11 => FF_TX_D_0_11,
-   FF_TX_D_0_12 => FF_TX_D_0_12,
-   FF_TX_D_0_13 => FF_TX_D_0_13,
-   FF_TX_D_0_14 => FF_TX_D_0_14,
-   FF_TX_D_0_15 => FF_TX_D_0_15,
-   FF_TX_D_0_16 => FF_TX_D_0_16,
-   FF_TX_D_0_17 => FF_TX_D_0_17,
-   FF_TX_D_0_18 => FF_TX_D_0_18,
-   FF_TX_D_0_19 => FF_TX_D_0_19,
-   FF_TX_D_0_20 => FF_TX_D_0_20,
-   FF_TX_D_0_21 => FF_TX_D_0_21,
-   FF_TX_D_0_22 => FF_TX_D_0_22,
-   FF_TX_D_0_23 => FF_TX_D_0_23,
-   FF_TX_D_1_0 => FF_TX_D_1_0,
-   FF_TX_D_1_1 => FF_TX_D_1_1,
-   FF_TX_D_1_2 => FF_TX_D_1_2,
-   FF_TX_D_1_3 => FF_TX_D_1_3,
-   FF_TX_D_1_4 => FF_TX_D_1_4,
-   FF_TX_D_1_5 => FF_TX_D_1_5,
-   FF_TX_D_1_6 => FF_TX_D_1_6,
-   FF_TX_D_1_7 => FF_TX_D_1_7,
-   FF_TX_D_1_8 => FF_TX_D_1_8,
-   FF_TX_D_1_9 => FF_TX_D_1_9,
-   FF_TX_D_1_10 => FF_TX_D_1_10,
-   FF_TX_D_1_11 => FF_TX_D_1_11,
-   FF_TX_D_1_12 => FF_TX_D_1_12,
-   FF_TX_D_1_13 => FF_TX_D_1_13,
-   FF_TX_D_1_14 => FF_TX_D_1_14,
-   FF_TX_D_1_15 => FF_TX_D_1_15,
-   FF_TX_D_1_16 => FF_TX_D_1_16,
-   FF_TX_D_1_17 => FF_TX_D_1_17,
-   FF_TX_D_1_18 => FF_TX_D_1_18,
-   FF_TX_D_1_19 => FF_TX_D_1_19,
-   FF_TX_D_1_20 => FF_TX_D_1_20,
-   FF_TX_D_1_21 => FF_TX_D_1_21,
-   FF_TX_D_1_22 => FF_TX_D_1_22,
-   FF_TX_D_1_23 => FF_TX_D_1_23,
-   FF_TX_D_2_0 => FF_TX_D_2_0,
-   FF_TX_D_2_1 => FF_TX_D_2_1,
-   FF_TX_D_2_2 => FF_TX_D_2_2,
-   FF_TX_D_2_3 => FF_TX_D_2_3,
-   FF_TX_D_2_4 => FF_TX_D_2_4,
-   FF_TX_D_2_5 => FF_TX_D_2_5,
-   FF_TX_D_2_6 => FF_TX_D_2_6,
-   FF_TX_D_2_7 => FF_TX_D_2_7,
-   FF_TX_D_2_8 => FF_TX_D_2_8,
-   FF_TX_D_2_9 => FF_TX_D_2_9,
-   FF_TX_D_2_10 => FF_TX_D_2_10,
-   FF_TX_D_2_11 => FF_TX_D_2_11,
-   FF_TX_D_2_12 => FF_TX_D_2_12,
-   FF_TX_D_2_13 => FF_TX_D_2_13,
-   FF_TX_D_2_14 => FF_TX_D_2_14,
-   FF_TX_D_2_15 => FF_TX_D_2_15,
-   FF_TX_D_2_16 => FF_TX_D_2_16,
-   FF_TX_D_2_17 => FF_TX_D_2_17,
-   FF_TX_D_2_18 => FF_TX_D_2_18,
-   FF_TX_D_2_19 => FF_TX_D_2_19,
-   FF_TX_D_2_20 => FF_TX_D_2_20,
-   FF_TX_D_2_21 => FF_TX_D_2_21,
-   FF_TX_D_2_22 => FF_TX_D_2_22,
-   FF_TX_D_2_23 => FF_TX_D_2_23,
-   FF_TX_D_3_0 => FF_TX_D_3_0,
-   FF_TX_D_3_1 => FF_TX_D_3_1,
-   FF_TX_D_3_2 => FF_TX_D_3_2,
-   FF_TX_D_3_3 => FF_TX_D_3_3,
-   FF_TX_D_3_4 => FF_TX_D_3_4,
-   FF_TX_D_3_5 => FF_TX_D_3_5,
-   FF_TX_D_3_6 => FF_TX_D_3_6,
-   FF_TX_D_3_7 => FF_TX_D_3_7,
-   FF_TX_D_3_8 => FF_TX_D_3_8,
-   FF_TX_D_3_9 => FF_TX_D_3_9,
-   FF_TX_D_3_10 => FF_TX_D_3_10,
-   FF_TX_D_3_11 => FF_TX_D_3_11,
-   FF_TX_D_3_12 => FF_TX_D_3_12,
-   FF_TX_D_3_13 => FF_TX_D_3_13,
-   FF_TX_D_3_14 => FF_TX_D_3_14,
-   FF_TX_D_3_15 => FF_TX_D_3_15,
-   FF_TX_D_3_16 => FF_TX_D_3_16,
-   FF_TX_D_3_17 => FF_TX_D_3_17,
-   FF_TX_D_3_18 => FF_TX_D_3_18,
-   FF_TX_D_3_19 => FF_TX_D_3_19,
-   FF_TX_D_3_20 => FF_TX_D_3_20,
-   FF_TX_D_3_21 => FF_TX_D_3_21,
-   FF_TX_D_3_22 => FF_TX_D_3_22,
-   FF_TX_D_3_23 => FF_TX_D_3_23,
-   FF_TXI_CLK_0 => FF_TXI_CLK_0,
-   FF_TXI_CLK_1 => FF_TXI_CLK_1,
-   FF_TXI_CLK_2 => FF_TXI_CLK_2,
-   FF_TXI_CLK_3 => FF_TXI_CLK_3,
-   FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0,
-   FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1,
-   FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2,
-   FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3,
-   FFC_CK_CORE_TX => FFC_CK_CORE_TX,
-   FFC_EI_EN_0 => FFC_EI_EN_0,
-   FFC_EI_EN_1 => FFC_EI_EN_1,
-   FFC_EI_EN_2 => FFC_EI_EN_2,
-   FFC_EI_EN_3 => FFC_EI_EN_3,
-   FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0,
-   FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1,
-   FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2,
-   FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3,
-   FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0,
-   FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1,
-   FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2,
-   FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3,
-   FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0,
-   FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1,
-   FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2,
-   FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3,
-   FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0,
-   FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1,
-   FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2,
-   FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3,
-   FFC_MACRO_RST => FFC_MACRO_RST,
-   FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0,
-   FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1,
-   FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2,
-   FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3,
-   FFC_PCIE_CT_0 => FFC_PCIE_CT_0,
-   FFC_PCIE_CT_1 => FFC_PCIE_CT_1,
-   FFC_PCIE_CT_2 => FFC_PCIE_CT_2,
-   FFC_PCIE_CT_3 => FFC_PCIE_CT_3,
-   FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0,
-   FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1,
-   FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2,
-   FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3,
-   FFC_QUAD_RST => FFC_QUAD_RST,
-   FFC_RRST_0 => FFC_RRST_0,
-   FFC_RRST_1 => FFC_RRST_1,
-   FFC_RRST_2 => FFC_RRST_2,
-   FFC_RRST_3 => FFC_RRST_3,
-   FFC_RXPWDNB_0 => FFC_RXPWDNB_0,
-   FFC_RXPWDNB_1 => FFC_RXPWDNB_1,
-   FFC_RXPWDNB_2 => FFC_RXPWDNB_2,
-   FFC_RXPWDNB_3 => FFC_RXPWDNB_3,
-   FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0,
-   FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1,
-   FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2,
-   FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3,
-   FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0,
-   FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1,
-   FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2,
-   FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3,
-   FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0,
-   FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1,
-   FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2,
-   FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3,
-   FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE,
-   FFC_TRST => FFC_TRST,
-   FFC_TXPWDNB_0 => FFC_TXPWDNB_0,
-   FFC_TXPWDNB_1 => FFC_TXPWDNB_1,
-   FFC_TXPWDNB_2 => FFC_TXPWDNB_2,
-   FFC_TXPWDNB_3 => FFC_TXPWDNB_3,
-   FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0,
-   FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1,
-   FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2,
-   FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3,
-   FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0,
-   FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1,
-   FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2,
-   FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3,
-   FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0,
-   FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1,
-   FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2,
-   FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3,
-   FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0,
-   FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1,
-   FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2,
-   FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3,
-   LDR_CORE2TX_0 => LDR_CORE2TX_0,
-   LDR_CORE2TX_1 => LDR_CORE2TX_1,
-   LDR_CORE2TX_2 => LDR_CORE2TX_2,
-   LDR_CORE2TX_3 => LDR_CORE2TX_3,
-   FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0,
-   FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1,
-   FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2,
-   FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3,
-   PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0,
-   PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1,
-   PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0,
-   PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1,
-   PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0,
-   PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1,
-   PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0,
-   PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1,
-   PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0,
-   PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1,
-   PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2,
-   PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3,
-   PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0,
-   PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1,
-   PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2,
-   PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3,
-   PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0,
-   PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1,
-   PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2,
-   PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3,
-   SCIADDR0 => SCIADDR0,
-   SCIADDR1 => SCIADDR1,
-   SCIADDR2 => SCIADDR2,
-   SCIADDR3 => SCIADDR3,
-   SCIADDR4 => SCIADDR4,
-   SCIADDR5 => SCIADDR5,
-   SCIENAUX => SCIENAUX,
-   SCIENCH0 => SCIENCH0,
-   SCIENCH1 => SCIENCH1,
-   SCIENCH2 => SCIENCH2,
-   SCIENCH3 => SCIENCH3,
-   SCIRD => SCIRD,
-   SCISELAUX => SCISELAUX,
-   SCISELCH0 => SCISELCH0,
-   SCISELCH1 => SCISELCH1,
-   SCISELCH2 => SCISELCH2,
-   SCISELCH3 => SCISELCH3,
-   SCIWDATA0 => SCIWDATA0,
-   SCIWDATA1 => SCIWDATA1,
-   SCIWDATA2 => SCIWDATA2,
-   SCIWDATA3 => SCIWDATA3,
-   SCIWDATA4 => SCIWDATA4,
-   SCIWDATA5 => SCIWDATA5,
-   SCIWDATA6 => SCIWDATA6,
-   SCIWDATA7 => SCIWDATA7,
-   SCIWSTN => SCIWSTN,
-   HDOUTN0 => HDOUTN0,
-   HDOUTN1 => HDOUTN1,
-   HDOUTN2 => HDOUTN2,
-   HDOUTN3 => HDOUTN3,
-   HDOUTP0 => HDOUTP0,
-   HDOUTP1 => HDOUTP1,
-   HDOUTP2 => HDOUTP2,
-   HDOUTP3 => HDOUTP3,
-   COUT19 => COUT19,
-   COUT18 => COUT18,
-   COUT17 => COUT17,
-   COUT16 => COUT16,
-   COUT15 => COUT15,
-   COUT14 => COUT14,
-   COUT13 => COUT13,
-   COUT12 => COUT12,
-   COUT11 => COUT11,
-   COUT10 => COUT10,
-   COUT9 => COUT9,
-   COUT8 => COUT8,
-   COUT7 => COUT7,
-   COUT6 => COUT6,
-   COUT5 => COUT5,
-   COUT4 => COUT4,
-   COUT3 => COUT3,
-   COUT2 => COUT2,
-   COUT1 => COUT1,
-   COUT0 => COUT0,
-   FF_RX_D_0_0 => FF_RX_D_0_0,
-   FF_RX_D_0_1 => FF_RX_D_0_1,
-   FF_RX_D_0_2 => FF_RX_D_0_2,
-   FF_RX_D_0_3 => FF_RX_D_0_3,
-   FF_RX_D_0_4 => FF_RX_D_0_4,
-   FF_RX_D_0_5 => FF_RX_D_0_5,
-   FF_RX_D_0_6 => FF_RX_D_0_6,
-   FF_RX_D_0_7 => FF_RX_D_0_7,
-   FF_RX_D_0_8 => FF_RX_D_0_8,
-   FF_RX_D_0_9 => FF_RX_D_0_9,
-   FF_RX_D_0_10 => FF_RX_D_0_10,
-   FF_RX_D_0_11 => FF_RX_D_0_11,
-   FF_RX_D_0_12 => FF_RX_D_0_12,
-   FF_RX_D_0_13 => FF_RX_D_0_13,
-   FF_RX_D_0_14 => FF_RX_D_0_14,
-   FF_RX_D_0_15 => FF_RX_D_0_15,
-   FF_RX_D_0_16 => FF_RX_D_0_16,
-   FF_RX_D_0_17 => FF_RX_D_0_17,
-   FF_RX_D_0_18 => FF_RX_D_0_18,
-   FF_RX_D_0_19 => FF_RX_D_0_19,
-   FF_RX_D_0_20 => FF_RX_D_0_20,
-   FF_RX_D_0_21 => FF_RX_D_0_21,
-   FF_RX_D_0_22 => FF_RX_D_0_22,
-   FF_RX_D_0_23 => FF_RX_D_0_23,
-   FF_RX_D_1_0 => FF_RX_D_1_0,
-   FF_RX_D_1_1 => FF_RX_D_1_1,
-   FF_RX_D_1_2 => FF_RX_D_1_2,
-   FF_RX_D_1_3 => FF_RX_D_1_3,
-   FF_RX_D_1_4 => FF_RX_D_1_4,
-   FF_RX_D_1_5 => FF_RX_D_1_5,
-   FF_RX_D_1_6 => FF_RX_D_1_6,
-   FF_RX_D_1_7 => FF_RX_D_1_7,
-   FF_RX_D_1_8 => FF_RX_D_1_8,
-   FF_RX_D_1_9 => FF_RX_D_1_9,
-   FF_RX_D_1_10 => FF_RX_D_1_10,
-   FF_RX_D_1_11 => FF_RX_D_1_11,
-   FF_RX_D_1_12 => FF_RX_D_1_12,
-   FF_RX_D_1_13 => FF_RX_D_1_13,
-   FF_RX_D_1_14 => FF_RX_D_1_14,
-   FF_RX_D_1_15 => FF_RX_D_1_15,
-   FF_RX_D_1_16 => FF_RX_D_1_16,
-   FF_RX_D_1_17 => FF_RX_D_1_17,
-   FF_RX_D_1_18 => FF_RX_D_1_18,
-   FF_RX_D_1_19 => FF_RX_D_1_19,
-   FF_RX_D_1_20 => FF_RX_D_1_20,
-   FF_RX_D_1_21 => FF_RX_D_1_21,
-   FF_RX_D_1_22 => FF_RX_D_1_22,
-   FF_RX_D_1_23 => FF_RX_D_1_23,
-   FF_RX_D_2_0 => FF_RX_D_2_0,
-   FF_RX_D_2_1 => FF_RX_D_2_1,
-   FF_RX_D_2_2 => FF_RX_D_2_2,
-   FF_RX_D_2_3 => FF_RX_D_2_3,
-   FF_RX_D_2_4 => FF_RX_D_2_4,
-   FF_RX_D_2_5 => FF_RX_D_2_5,
-   FF_RX_D_2_6 => FF_RX_D_2_6,
-   FF_RX_D_2_7 => FF_RX_D_2_7,
-   FF_RX_D_2_8 => FF_RX_D_2_8,
-   FF_RX_D_2_9 => FF_RX_D_2_9,
-   FF_RX_D_2_10 => FF_RX_D_2_10,
-   FF_RX_D_2_11 => FF_RX_D_2_11,
-   FF_RX_D_2_12 => FF_RX_D_2_12,
-   FF_RX_D_2_13 => FF_RX_D_2_13,
-   FF_RX_D_2_14 => FF_RX_D_2_14,
-   FF_RX_D_2_15 => FF_RX_D_2_15,
-   FF_RX_D_2_16 => FF_RX_D_2_16,
-   FF_RX_D_2_17 => FF_RX_D_2_17,
-   FF_RX_D_2_18 => FF_RX_D_2_18,
-   FF_RX_D_2_19 => FF_RX_D_2_19,
-   FF_RX_D_2_20 => FF_RX_D_2_20,
-   FF_RX_D_2_21 => FF_RX_D_2_21,
-   FF_RX_D_2_22 => FF_RX_D_2_22,
-   FF_RX_D_2_23 => FF_RX_D_2_23,
-   FF_RX_D_3_0 => FF_RX_D_3_0,
-   FF_RX_D_3_1 => FF_RX_D_3_1,
-   FF_RX_D_3_2 => FF_RX_D_3_2,
-   FF_RX_D_3_3 => FF_RX_D_3_3,
-   FF_RX_D_3_4 => FF_RX_D_3_4,
-   FF_RX_D_3_5 => FF_RX_D_3_5,
-   FF_RX_D_3_6 => FF_RX_D_3_6,
-   FF_RX_D_3_7 => FF_RX_D_3_7,
-   FF_RX_D_3_8 => FF_RX_D_3_8,
-   FF_RX_D_3_9 => FF_RX_D_3_9,
-   FF_RX_D_3_10 => FF_RX_D_3_10,
-   FF_RX_D_3_11 => FF_RX_D_3_11,
-   FF_RX_D_3_12 => FF_RX_D_3_12,
-   FF_RX_D_3_13 => FF_RX_D_3_13,
-   FF_RX_D_3_14 => FF_RX_D_3_14,
-   FF_RX_D_3_15 => FF_RX_D_3_15,
-   FF_RX_D_3_16 => FF_RX_D_3_16,
-   FF_RX_D_3_17 => FF_RX_D_3_17,
-   FF_RX_D_3_18 => FF_RX_D_3_18,
-   FF_RX_D_3_19 => FF_RX_D_3_19,
-   FF_RX_D_3_20 => FF_RX_D_3_20,
-   FF_RX_D_3_21 => FF_RX_D_3_21,
-   FF_RX_D_3_22 => FF_RX_D_3_22,
-   FF_RX_D_3_23 => FF_RX_D_3_23,
-   FF_RX_F_CLK_0 => FF_RX_F_CLK_0,
-   FF_RX_F_CLK_1 => FF_RX_F_CLK_1,
-   FF_RX_F_CLK_2 => FF_RX_F_CLK_2,
-   FF_RX_F_CLK_3 => FF_RX_F_CLK_3,
-   FF_RX_H_CLK_0 => FF_RX_H_CLK_0,
-   FF_RX_H_CLK_1 => FF_RX_H_CLK_1,
-   FF_RX_H_CLK_2 => FF_RX_H_CLK_2,
-   FF_RX_H_CLK_3 => FF_RX_H_CLK_3,
-   FF_TX_F_CLK_0 => FF_TX_F_CLK_0,
-   FF_TX_F_CLK_1 => FF_TX_F_CLK_1,
-   FF_TX_F_CLK_2 => FF_TX_F_CLK_2,
-   FF_TX_F_CLK_3 => FF_TX_F_CLK_3,
-   FF_TX_H_CLK_0 => FF_TX_H_CLK_0,
-   FF_TX_H_CLK_1 => FF_TX_H_CLK_1,
-   FF_TX_H_CLK_2 => FF_TX_H_CLK_2,
-   FF_TX_H_CLK_3 => FF_TX_H_CLK_3,
-   FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0,
-   FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1,
-   FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2,
-   FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3,
-   FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0,
-   FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1,
-   FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2,
-   FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3,
-   FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0,
-   FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1,
-   FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2,
-   FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3,
-   FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0,
-   FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1,
-   FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2,
-   FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3,
-   FFS_PCIE_CON_0 => FFS_PCIE_CON_0,
-   FFS_PCIE_CON_1 => FFS_PCIE_CON_1,
-   FFS_PCIE_CON_2 => FFS_PCIE_CON_2,
-   FFS_PCIE_CON_3 => FFS_PCIE_CON_3,
-   FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0,
-   FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1,
-   FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2,
-   FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3,
-   FFS_PLOL => FFS_PLOL,
-   FFS_RLOL_0 => FFS_RLOL_0,
-   FFS_RLOL_1 => FFS_RLOL_1,
-   FFS_RLOL_2 => FFS_RLOL_2,
-   FFS_RLOL_3 => FFS_RLOL_3,
-   FFS_RLOS_HI_0 => FFS_RLOS_HI_0,
-   FFS_RLOS_HI_1 => FFS_RLOS_HI_1,
-   FFS_RLOS_HI_2 => FFS_RLOS_HI_2,
-   FFS_RLOS_HI_3 => FFS_RLOS_HI_3,
-   FFS_RLOS_LO_0 => FFS_RLOS_LO_0,
-   FFS_RLOS_LO_1 => FFS_RLOS_LO_1,
-   FFS_RLOS_LO_2 => FFS_RLOS_LO_2,
-   FFS_RLOS_LO_3 => FFS_RLOS_LO_3,
-   FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0,
-   FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1,
-   FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2,
-   FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3,
-   FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0,
-   FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1,
-   FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2,
-   FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3,
-   PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0,
-   PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1,
-   PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2,
-   PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3,
-   PCIE_RXVALID_0 => PCIE_RXVALID_0,
-   PCIE_RXVALID_1 => PCIE_RXVALID_1,
-   PCIE_RXVALID_2 => PCIE_RXVALID_2,
-   PCIE_RXVALID_3 => PCIE_RXVALID_3,
-   FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0,
-   FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1,
-   FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2,
-   FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3,
-   FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0,
-   FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1,
-   FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2,
-   FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3,
-   LDR_RX2CORE_0 => LDR_RX2CORE_0,
-   LDR_RX2CORE_1 => LDR_RX2CORE_1,
-   LDR_RX2CORE_2 => LDR_RX2CORE_2,
-   LDR_RX2CORE_3 => LDR_RX2CORE_3,
-   REFCK2CORE => REFCK2CORE,
-   SCIINT => SCIINT,
-   SCIRDATA0 => SCIRDATA0,
-   SCIRDATA1 => SCIRDATA1,
-   SCIRDATA2 => SCIRDATA2,
-   SCIRDATA3 => SCIRDATA3,
-   SCIRDATA4 => SCIRDATA4,
-   SCIRDATA5 => SCIRDATA5,
-   SCIRDATA6 => SCIRDATA6,
-   SCIRDATA7 => SCIRDATA7,
-   REFCLK_FROM_NQ => REFCLK_FROM_NQ,
-   REFCLK_TO_NQ => REFCLK_TO_NQ
-   );
-
-end PCSD_arch;
-
---synopsys translate_on
-
-
-
-
---synopsys translate_off
-library ECP3;
-use ECP3.components.all;
---synopsys translate_on
-
-
-library IEEE, STD;
-use IEEE.std_logic_1164.all;
-use STD.TEXTIO.all;
-
-entity sfp_2_200_int is
-   GENERIC (USER_CONFIG_FILE    :  String := "sfp_2_200_int.txt");
- port (
-------------------
--- CH0 --
--- CH1 --
-    hdinp_ch1, hdinn_ch1    :   in std_logic;
-    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
-    sci_sel_ch1    :   in std_logic;
-    rxiclk_ch1    :   in std_logic;
-    txiclk_ch1    :   in std_logic;
-    rx_full_clk_ch1   :   out std_logic;
-    rx_half_clk_ch1   :   out std_logic;
-    tx_full_clk_ch1   :   out std_logic;
-    tx_half_clk_ch1   :   out std_logic;
-    fpga_rxrefclk_ch1    :   in std_logic;
-    txdata_ch1    :   in std_logic_vector (15 downto 0);
-    tx_k_ch1    :   in std_logic_vector (1 downto 0);
-    tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
-    tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
-    rxdata_ch1   :   out std_logic_vector (15 downto 0);
-    rx_k_ch1   :   out std_logic_vector (1 downto 0);
-    rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
-    rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
-    rx_serdes_rst_ch1_c    :   in std_logic;
-    sb_felb_ch1_c    :   in std_logic;
-    sb_felb_rst_ch1_c    :   in std_logic;
-    tx_pcs_rst_ch1_c    :   in std_logic;
-    tx_pwrup_ch1_c    :   in std_logic;
-    rx_pcs_rst_ch1_c    :   in std_logic;
-    rx_pwrup_ch1_c    :   in std_logic;
-    rx_los_low_ch1_s   :   out std_logic;
-    lsm_status_ch1_s   :   out std_logic;
-    rx_cdr_lol_ch1_s   :   out std_logic;
-    tx_div2_mode_ch1_c   : in std_logic;
-    rx_div2_mode_ch1_c   : in std_logic;
--- CH2 --
--- CH3 --
-    hdinp_ch3, hdinn_ch3    :   in std_logic;
-    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
-    sci_sel_ch3    :   in std_logic;
-    txiclk_ch3    :   in std_logic;
-    rx_full_clk_ch3   :   out std_logic;
-    rx_half_clk_ch3   :   out std_logic;
-    tx_full_clk_ch3   :   out std_logic;
-    tx_half_clk_ch3   :   out std_logic;
-    fpga_rxrefclk_ch3    :   in std_logic;
-    txdata_ch3    :   in std_logic_vector (7 downto 0);
-    tx_k_ch3    :   in std_logic;
-    tx_force_disp_ch3    :   in std_logic;
-    tx_disp_sel_ch3    :   in std_logic;
-    rxdata_ch3   :   out std_logic_vector (7 downto 0);
-    rx_k_ch3   :   out std_logic;
-    rx_disp_err_ch3   :   out std_logic;
-    rx_cv_err_ch3   :   out std_logic;
-    rx_serdes_rst_ch3_c    :   in std_logic;
-    sb_felb_ch3_c    :   in std_logic;
-    sb_felb_rst_ch3_c    :   in std_logic;
-    tx_pcs_rst_ch3_c    :   in std_logic;
-    tx_pwrup_ch3_c    :   in std_logic;
-    rx_pcs_rst_ch3_c    :   in std_logic;
-    rx_pwrup_ch3_c    :   in std_logic;
-    rx_los_low_ch3_s   :   out std_logic;
-    lsm_status_ch3_s   :   out std_logic;
-    rx_cdr_lol_ch3_s   :   out std_logic;
-    tx_div2_mode_ch3_c   : in std_logic;
-    rx_div2_mode_ch3_c   : in std_logic;
----- Miscillaneous ports
-    sci_wrdata    :   in std_logic_vector (7 downto 0);
-    sci_addr    :   in std_logic_vector (5 downto 0);
-    sci_rddata   :   out std_logic_vector (7 downto 0);
-    sci_sel_quad    :   in std_logic;
-    sci_rd    :   in std_logic;
-    sci_wrn    :   in std_logic;
-    fpga_txrefclk  :   in std_logic;
-    tx_serdes_rst_c    :   in std_logic;
-    tx_pll_lol_qd_s   :   out std_logic;
-    tx_sync_qd_c    :   in std_logic;
-    rst_qd_c    :   in std_logic;
-    refclk2fpga   :   out std_logic;
-    serdes_rst_qd_c    :   in std_logic);
-
-end sfp_2_200_int;
-
-
-architecture sfp_2_200_int_arch of sfp_2_200_int is
-
-component VLO
-port (
-   Z : out std_logic);
-end component;
-
-component VHI
-port (
-   Z : out std_logic);
-end component;
-
-
-
-component PCSD
---synopsys translate_off
-GENERIC(
-  CONFIG_FILE : String;
-  QUAD_MODE : String;
-  CH0_CDR_SRC   : String := "REFCLK_EXT";
-  CH1_CDR_SRC   : String := "REFCLK_EXT";
-  CH2_CDR_SRC   : String := "REFCLK_EXT";
-  CH3_CDR_SRC   : String := "REFCLK_EXT";
-  PLL_SRC   : String
-  );
---synopsys translate_on
-port (
-  HDINN0             : in std_logic;
-  HDINN1             : in std_logic;
-  HDINN2             : in std_logic;
-  HDINN3             : in std_logic;
-  HDINP0             : in std_logic;
-  HDINP1             : in std_logic;
-  HDINP2             : in std_logic;
-  HDINP3             : in std_logic;
-  REFCLKN             : in std_logic;
-  REFCLKP             : in std_logic;
-  CIN0             : in std_logic;
-  CIN1             : in std_logic;
-  CIN2             : in std_logic;
-  CIN3             : in std_logic;
-  CIN4             : in std_logic;
-  CIN5             : in std_logic;
-  CIN6             : in std_logic;
-  CIN7             : in std_logic;
-  CIN8             : in std_logic;
-  CIN9             : in std_logic;
-  CIN10             : in std_logic;
-  CIN11             : in std_logic;
-  CYAWSTN             : in std_logic;
-  FF_EBRD_CLK_0             : in std_logic;
-  FF_EBRD_CLK_1             : in std_logic;
-  FF_EBRD_CLK_2             : in std_logic;
-  FF_EBRD_CLK_3             : in std_logic;
-  FF_RXI_CLK_0             : in std_logic;
-  FF_RXI_CLK_1             : in std_logic;
-  FF_RXI_CLK_2             : in std_logic;
-  FF_RXI_CLK_3             : in std_logic;
-  FF_TX_D_0_0             : in std_logic;
-  FF_TX_D_0_1             : in std_logic;
-  FF_TX_D_0_2             : in std_logic;
-  FF_TX_D_0_3             : in std_logic;
-  FF_TX_D_0_4             : in std_logic;
-  FF_TX_D_0_5             : in std_logic;
-  FF_TX_D_0_6             : in std_logic;
-  FF_TX_D_0_7             : in std_logic;
-  FF_TX_D_0_8             : in std_logic;
-  FF_TX_D_0_9             : in std_logic;
-  FF_TX_D_0_10             : in std_logic;
-  FF_TX_D_0_11             : in std_logic;
-  FF_TX_D_0_12             : in std_logic;
-  FF_TX_D_0_13             : in std_logic;
-  FF_TX_D_0_14             : in std_logic;
-  FF_TX_D_0_15             : in std_logic;
-  FF_TX_D_0_16             : in std_logic;
-  FF_TX_D_0_17             : in std_logic;
-  FF_TX_D_0_18             : in std_logic;
-  FF_TX_D_0_19             : in std_logic;
-  FF_TX_D_0_20             : in std_logic;
-  FF_TX_D_0_21             : in std_logic;
-  FF_TX_D_0_22             : in std_logic;
-  FF_TX_D_0_23             : in std_logic;
-  FF_TX_D_1_0             : in std_logic;
-  FF_TX_D_1_1             : in std_logic;
-  FF_TX_D_1_2             : in std_logic;
-  FF_TX_D_1_3             : in std_logic;
-  FF_TX_D_1_4             : in std_logic;
-  FF_TX_D_1_5             : in std_logic;
-  FF_TX_D_1_6             : in std_logic;
-  FF_TX_D_1_7             : in std_logic;
-  FF_TX_D_1_8             : in std_logic;
-  FF_TX_D_1_9             : in std_logic;
-  FF_TX_D_1_10             : in std_logic;
-  FF_TX_D_1_11             : in std_logic;
-  FF_TX_D_1_12             : in std_logic;
-  FF_TX_D_1_13             : in std_logic;
-  FF_TX_D_1_14             : in std_logic;
-  FF_TX_D_1_15             : in std_logic;
-  FF_TX_D_1_16             : in std_logic;
-  FF_TX_D_1_17             : in std_logic;
-  FF_TX_D_1_18             : in std_logic;
-  FF_TX_D_1_19             : in std_logic;
-  FF_TX_D_1_20             : in std_logic;
-  FF_TX_D_1_21             : in std_logic;
-  FF_TX_D_1_22             : in std_logic;
-  FF_TX_D_1_23             : in std_logic;
-  FF_TX_D_2_0             : in std_logic;
-  FF_TX_D_2_1             : in std_logic;
-  FF_TX_D_2_2             : in std_logic;
-  FF_TX_D_2_3             : in std_logic;
-  FF_TX_D_2_4             : in std_logic;
-  FF_TX_D_2_5             : in std_logic;
-  FF_TX_D_2_6             : in std_logic;
-  FF_TX_D_2_7             : in std_logic;
-  FF_TX_D_2_8             : in std_logic;
-  FF_TX_D_2_9             : in std_logic;
-  FF_TX_D_2_10             : in std_logic;
-  FF_TX_D_2_11             : in std_logic;
-  FF_TX_D_2_12             : in std_logic;
-  FF_TX_D_2_13             : in std_logic;
-  FF_TX_D_2_14             : in std_logic;
-  FF_TX_D_2_15             : in std_logic;
-  FF_TX_D_2_16             : in std_logic;
-  FF_TX_D_2_17             : in std_logic;
-  FF_TX_D_2_18             : in std_logic;
-  FF_TX_D_2_19             : in std_logic;
-  FF_TX_D_2_20             : in std_logic;
-  FF_TX_D_2_21             : in std_logic;
-  FF_TX_D_2_22             : in std_logic;
-  FF_TX_D_2_23             : in std_logic;
-  FF_TX_D_3_0             : in std_logic;
-  FF_TX_D_3_1             : in std_logic;
-  FF_TX_D_3_2             : in std_logic;
-  FF_TX_D_3_3             : in std_logic;
-  FF_TX_D_3_4             : in std_logic;
-  FF_TX_D_3_5             : in std_logic;
-  FF_TX_D_3_6             : in std_logic;
-  FF_TX_D_3_7             : in std_logic;
-  FF_TX_D_3_8             : in std_logic;
-  FF_TX_D_3_9             : in std_logic;
-  FF_TX_D_3_10             : in std_logic;
-  FF_TX_D_3_11             : in std_logic;
-  FF_TX_D_3_12             : in std_logic;
-  FF_TX_D_3_13             : in std_logic;
-  FF_TX_D_3_14             : in std_logic;
-  FF_TX_D_3_15             : in std_logic;
-  FF_TX_D_3_16             : in std_logic;
-  FF_TX_D_3_17             : in std_logic;
-  FF_TX_D_3_18             : in std_logic;
-  FF_TX_D_3_19             : in std_logic;
-  FF_TX_D_3_20             : in std_logic;
-  FF_TX_D_3_21             : in std_logic;
-  FF_TX_D_3_22             : in std_logic;
-  FF_TX_D_3_23             : in std_logic;
-  FF_TXI_CLK_0             : in std_logic;
-  FF_TXI_CLK_1             : in std_logic;
-  FF_TXI_CLK_2             : in std_logic;
-  FF_TXI_CLK_3             : in std_logic;
-  FFC_CK_CORE_RX_0         : in std_logic;
-  FFC_CK_CORE_RX_1         : in std_logic;
-  FFC_CK_CORE_RX_2         : in std_logic;
-  FFC_CK_CORE_RX_3         : in std_logic;
-  FFC_CK_CORE_TX           : in std_logic;
-  FFC_EI_EN_0             : in std_logic;
-  FFC_EI_EN_1             : in std_logic;
-  FFC_EI_EN_2             : in std_logic;
-  FFC_EI_EN_3             : in std_logic;
-  FFC_ENABLE_CGALIGN_0             : in std_logic;
-  FFC_ENABLE_CGALIGN_1             : in std_logic;
-  FFC_ENABLE_CGALIGN_2             : in std_logic;
-  FFC_ENABLE_CGALIGN_3             : in std_logic;
-  FFC_FB_LOOPBACK_0             : in std_logic;
-  FFC_FB_LOOPBACK_1             : in std_logic;
-  FFC_FB_LOOPBACK_2             : in std_logic;
-  FFC_FB_LOOPBACK_3             : in std_logic;
-  FFC_LANE_RX_RST_0             : in std_logic;
-  FFC_LANE_RX_RST_1             : in std_logic;
-  FFC_LANE_RX_RST_2             : in std_logic;
-  FFC_LANE_RX_RST_3             : in std_logic;
-  FFC_LANE_TX_RST_0             : in std_logic;
-  FFC_LANE_TX_RST_1             : in std_logic;
-  FFC_LANE_TX_RST_2             : in std_logic;
-  FFC_LANE_TX_RST_3             : in std_logic;
-  FFC_MACRO_RST             : in std_logic;
-  FFC_PCI_DET_EN_0             : in std_logic;
-  FFC_PCI_DET_EN_1             : in std_logic;
-  FFC_PCI_DET_EN_2             : in std_logic;
-  FFC_PCI_DET_EN_3             : in std_logic;
-  FFC_PCIE_CT_0             : in std_logic;
-  FFC_PCIE_CT_1             : in std_logic;
-  FFC_PCIE_CT_2             : in std_logic;
-  FFC_PCIE_CT_3             : in std_logic;
-  FFC_PFIFO_CLR_0             : in std_logic;
-  FFC_PFIFO_CLR_1             : in std_logic;
-  FFC_PFIFO_CLR_2             : in std_logic;
-  FFC_PFIFO_CLR_3             : in std_logic;
-  FFC_QUAD_RST             : in std_logic;
-  FFC_RRST_0             : in std_logic;
-  FFC_RRST_1             : in std_logic;
-  FFC_RRST_2             : in std_logic;
-  FFC_RRST_3             : in std_logic;
-  FFC_RXPWDNB_0             : in std_logic;
-  FFC_RXPWDNB_1             : in std_logic;
-  FFC_RXPWDNB_2             : in std_logic;
-  FFC_RXPWDNB_3             : in std_logic;
-  FFC_SB_INV_RX_0             : in std_logic;
-  FFC_SB_INV_RX_1             : in std_logic;
-  FFC_SB_INV_RX_2             : in std_logic;
-  FFC_SB_INV_RX_3             : in std_logic;
-  FFC_SB_PFIFO_LP_0             : in std_logic;
-  FFC_SB_PFIFO_LP_1             : in std_logic;
-  FFC_SB_PFIFO_LP_2             : in std_logic;
-  FFC_SB_PFIFO_LP_3             : in std_logic;
-  FFC_SIGNAL_DETECT_0             : in std_logic;
-  FFC_SIGNAL_DETECT_1             : in std_logic;
-  FFC_SIGNAL_DETECT_2             : in std_logic;
-  FFC_SIGNAL_DETECT_3             : in std_logic;
-  FFC_SYNC_TOGGLE             : in std_logic;
-  FFC_TRST             : in std_logic;
-  FFC_TXPWDNB_0             : in std_logic;
-  FFC_TXPWDNB_1             : in std_logic;
-  FFC_TXPWDNB_2             : in std_logic;
-  FFC_TXPWDNB_3             : in std_logic;
-  FFC_RATE_MODE_RX_0        : in std_logic;
-  FFC_RATE_MODE_RX_1        : in std_logic;
-  FFC_RATE_MODE_RX_2        : in std_logic;
-  FFC_RATE_MODE_RX_3        : in std_logic;
-  FFC_RATE_MODE_TX_0        : in std_logic;
-  FFC_RATE_MODE_TX_1        : in std_logic;
-  FFC_RATE_MODE_TX_2        : in std_logic;
-  FFC_RATE_MODE_TX_3        : in std_logic;
-  FFC_DIV11_MODE_RX_0       : in std_logic;
-  FFC_DIV11_MODE_RX_1       : in std_logic;
-  FFC_DIV11_MODE_RX_2       : in std_logic;
-  FFC_DIV11_MODE_RX_3       : in std_logic;
-  FFC_DIV11_MODE_TX_0       : in std_logic;
-  FFC_DIV11_MODE_TX_1       : in std_logic;
-  FFC_DIV11_MODE_TX_2       : in std_logic;
-  FFC_DIV11_MODE_TX_3       : in std_logic;
-  LDR_CORE2TX_0             : in std_logic;
-  LDR_CORE2TX_1             : in std_logic;
-  LDR_CORE2TX_2             : in std_logic;
-  LDR_CORE2TX_3             : in std_logic;
-  FFC_LDR_CORE2TX_EN_0      : in std_logic;
-  FFC_LDR_CORE2TX_EN_1      : in std_logic;
-  FFC_LDR_CORE2TX_EN_2      : in std_logic;
-  FFC_LDR_CORE2TX_EN_3      : in std_logic;
-  PCIE_POWERDOWN_0_0      : in std_logic;
-  PCIE_POWERDOWN_0_1      : in std_logic;
-  PCIE_POWERDOWN_1_0      : in std_logic;
-  PCIE_POWERDOWN_1_1      : in std_logic;
-  PCIE_POWERDOWN_2_0      : in std_logic;
-  PCIE_POWERDOWN_2_1      : in std_logic;
-  PCIE_POWERDOWN_3_0      : in std_logic;
-  PCIE_POWERDOWN_3_1      : in std_logic;
-  PCIE_RXPOLARITY_0         : in std_logic;
-  PCIE_RXPOLARITY_1         : in std_logic;
-  PCIE_RXPOLARITY_2         : in std_logic;
-  PCIE_RXPOLARITY_3         : in std_logic;
-  PCIE_TXCOMPLIANCE_0       : in std_logic;
-  PCIE_TXCOMPLIANCE_1       : in std_logic;
-  PCIE_TXCOMPLIANCE_2       : in std_logic;
-  PCIE_TXCOMPLIANCE_3       : in std_logic;
-  PCIE_TXDETRX_PR2TLB_0     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_1     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_2     : in std_logic;
-  PCIE_TXDETRX_PR2TLB_3     : in std_logic;
-  SCIADDR0             : in std_logic;
-  SCIADDR1             : in std_logic;
-  SCIADDR2             : in std_logic;
-  SCIADDR3             : in std_logic;
-  SCIADDR4             : in std_logic;
-  SCIADDR5             : in std_logic;
-  SCIENAUX             : in std_logic;
-  SCIENCH0             : in std_logic;
-  SCIENCH1             : in std_logic;
-  SCIENCH2             : in std_logic;
-  SCIENCH3             : in std_logic;
-  SCIRD                : in std_logic;
-  SCISELAUX             : in std_logic;
-  SCISELCH0             : in std_logic;
-  SCISELCH1             : in std_logic;
-  SCISELCH2             : in std_logic;
-  SCISELCH3             : in std_logic;
-  SCIWDATA0             : in std_logic;
-  SCIWDATA1             : in std_logic;
-  SCIWDATA2             : in std_logic;
-  SCIWDATA3             : in std_logic;
-  SCIWDATA4             : in std_logic;
-  SCIWDATA5             : in std_logic;
-  SCIWDATA6             : in std_logic;
-  SCIWDATA7             : in std_logic;
-  SCIWSTN               : in std_logic;
-  REFCLK_FROM_NQ        : in std_logic;
-  HDOUTN0             : out std_logic;
-  HDOUTN1             : out std_logic;
-  HDOUTN2             : out std_logic;
-  HDOUTN3             : out std_logic;
-  HDOUTP0             : out std_logic;
-  HDOUTP1             : out std_logic;
-  HDOUTP2             : out std_logic;
-  HDOUTP3             : out std_logic;
-  COUT0             : out std_logic;
-  COUT1             : out std_logic;
-  COUT2             : out std_logic;
-  COUT3             : out std_logic;
-  COUT4             : out std_logic;
-  COUT5             : out std_logic;
-  COUT6             : out std_logic;
-  COUT7             : out std_logic;
-  COUT8             : out std_logic;
-  COUT9             : out std_logic;
-  COUT10             : out std_logic;
-  COUT11             : out std_logic;
-  COUT12             : out std_logic;
-  COUT13             : out std_logic;
-  COUT14             : out std_logic;
-  COUT15             : out std_logic;
-  COUT16             : out std_logic;
-  COUT17             : out std_logic;
-  COUT18             : out std_logic;
-  COUT19             : out std_logic;
-  FF_RX_D_0_0             : out std_logic;
-  FF_RX_D_0_1             : out std_logic;
-  FF_RX_D_0_2             : out std_logic;
-  FF_RX_D_0_3             : out std_logic;
-  FF_RX_D_0_4             : out std_logic;
-  FF_RX_D_0_5             : out std_logic;
-  FF_RX_D_0_6             : out std_logic;
-  FF_RX_D_0_7             : out std_logic;
-  FF_RX_D_0_8             : out std_logic;
-  FF_RX_D_0_9             : out std_logic;
-  FF_RX_D_0_10             : out std_logic;
-  FF_RX_D_0_11             : out std_logic;
-  FF_RX_D_0_12             : out std_logic;
-  FF_RX_D_0_13             : out std_logic;
-  FF_RX_D_0_14             : out std_logic;
-  FF_RX_D_0_15             : out std_logic;
-  FF_RX_D_0_16             : out std_logic;
-  FF_RX_D_0_17             : out std_logic;
-  FF_RX_D_0_18             : out std_logic;
-  FF_RX_D_0_19             : out std_logic;
-  FF_RX_D_0_20             : out std_logic;
-  FF_RX_D_0_21             : out std_logic;
-  FF_RX_D_0_22             : out std_logic;
-  FF_RX_D_0_23             : out std_logic;
-  FF_RX_D_1_0             : out std_logic;
-  FF_RX_D_1_1             : out std_logic;
-  FF_RX_D_1_2             : out std_logic;
-  FF_RX_D_1_3             : out std_logic;
-  FF_RX_D_1_4             : out std_logic;
-  FF_RX_D_1_5             : out std_logic;
-  FF_RX_D_1_6             : out std_logic;
-  FF_RX_D_1_7             : out std_logic;
-  FF_RX_D_1_8             : out std_logic;
-  FF_RX_D_1_9             : out std_logic;
-  FF_RX_D_1_10             : out std_logic;
-  FF_RX_D_1_11             : out std_logic;
-  FF_RX_D_1_12             : out std_logic;
-  FF_RX_D_1_13             : out std_logic;
-  FF_RX_D_1_14             : out std_logic;
-  FF_RX_D_1_15             : out std_logic;
-  FF_RX_D_1_16             : out std_logic;
-  FF_RX_D_1_17             : out std_logic;
-  FF_RX_D_1_18             : out std_logic;
-  FF_RX_D_1_19             : out std_logic;
-  FF_RX_D_1_20             : out std_logic;
-  FF_RX_D_1_21             : out std_logic;
-  FF_RX_D_1_22             : out std_logic;
-  FF_RX_D_1_23             : out std_logic;
-  FF_RX_D_2_0             : out std_logic;
-  FF_RX_D_2_1             : out std_logic;
-  FF_RX_D_2_2             : out std_logic;
-  FF_RX_D_2_3             : out std_logic;
-  FF_RX_D_2_4             : out std_logic;
-  FF_RX_D_2_5             : out std_logic;
-  FF_RX_D_2_6             : out std_logic;
-  FF_RX_D_2_7             : out std_logic;
-  FF_RX_D_2_8             : out std_logic;
-  FF_RX_D_2_9             : out std_logic;
-  FF_RX_D_2_10             : out std_logic;
-  FF_RX_D_2_11             : out std_logic;
-  FF_RX_D_2_12             : out std_logic;
-  FF_RX_D_2_13             : out std_logic;
-  FF_RX_D_2_14             : out std_logic;
-  FF_RX_D_2_15             : out std_logic;
-  FF_RX_D_2_16             : out std_logic;
-  FF_RX_D_2_17             : out std_logic;
-  FF_RX_D_2_18             : out std_logic;
-  FF_RX_D_2_19             : out std_logic;
-  FF_RX_D_2_20             : out std_logic;
-  FF_RX_D_2_21             : out std_logic;
-  FF_RX_D_2_22             : out std_logic;
-  FF_RX_D_2_23             : out std_logic;
-  FF_RX_D_3_0             : out std_logic;
-  FF_RX_D_3_1             : out std_logic;
-  FF_RX_D_3_2             : out std_logic;
-  FF_RX_D_3_3             : out std_logic;
-  FF_RX_D_3_4             : out std_logic;
-  FF_RX_D_3_5             : out std_logic;
-  FF_RX_D_3_6             : out std_logic;
-  FF_RX_D_3_7             : out std_logic;
-  FF_RX_D_3_8             : out std_logic;
-  FF_RX_D_3_9             : out std_logic;
-  FF_RX_D_3_10             : out std_logic;
-  FF_RX_D_3_11             : out std_logic;
-  FF_RX_D_3_12             : out std_logic;
-  FF_RX_D_3_13             : out std_logic;
-  FF_RX_D_3_14             : out std_logic;
-  FF_RX_D_3_15             : out std_logic;
-  FF_RX_D_3_16             : out std_logic;
-  FF_RX_D_3_17             : out std_logic;
-  FF_RX_D_3_18             : out std_logic;
-  FF_RX_D_3_19             : out std_logic;
-  FF_RX_D_3_20             : out std_logic;
-  FF_RX_D_3_21             : out std_logic;
-  FF_RX_D_3_22             : out std_logic;
-  FF_RX_D_3_23             : out std_logic;
-  FF_RX_F_CLK_0             : out std_logic;
-  FF_RX_F_CLK_1             : out std_logic;
-  FF_RX_F_CLK_2             : out std_logic;
-  FF_RX_F_CLK_3             : out std_logic;
-  FF_RX_H_CLK_0             : out std_logic;
-  FF_RX_H_CLK_1             : out std_logic;
-  FF_RX_H_CLK_2             : out std_logic;
-  FF_RX_H_CLK_3             : out std_logic;
-  FF_TX_F_CLK_0             : out std_logic;
-  FF_TX_F_CLK_1             : out std_logic;
-  FF_TX_F_CLK_2             : out std_logic;
-  FF_TX_F_CLK_3             : out std_logic;
-  FF_TX_H_CLK_0             : out std_logic;
-  FF_TX_H_CLK_1             : out std_logic;
-  FF_TX_H_CLK_2             : out std_logic;
-  FF_TX_H_CLK_3             : out std_logic;
-  FFS_CC_OVERRUN_0             : out std_logic;
-  FFS_CC_OVERRUN_1             : out std_logic;
-  FFS_CC_OVERRUN_2             : out std_logic;
-  FFS_CC_OVERRUN_3             : out std_logic;
-  FFS_CC_UNDERRUN_0             : out std_logic;
-  FFS_CC_UNDERRUN_1             : out std_logic;
-  FFS_CC_UNDERRUN_2             : out std_logic;
-  FFS_CC_UNDERRUN_3             : out std_logic;
-  FFS_LS_SYNC_STATUS_0             : out std_logic;
-  FFS_LS_SYNC_STATUS_1             : out std_logic;
-  FFS_LS_SYNC_STATUS_2             : out std_logic;
-  FFS_LS_SYNC_STATUS_3             : out std_logic;
-  FFS_CDR_TRAIN_DONE_0             : out std_logic;
-  FFS_CDR_TRAIN_DONE_1             : out std_logic;
-  FFS_CDR_TRAIN_DONE_2             : out std_logic;
-  FFS_CDR_TRAIN_DONE_3             : out std_logic;
-  FFS_PCIE_CON_0             : out std_logic;
-  FFS_PCIE_CON_1             : out std_logic;
-  FFS_PCIE_CON_2             : out std_logic;
-  FFS_PCIE_CON_3             : out std_logic;
-  FFS_PCIE_DONE_0             : out std_logic;
-  FFS_PCIE_DONE_1             : out std_logic;
-  FFS_PCIE_DONE_2             : out std_logic;
-  FFS_PCIE_DONE_3             : out std_logic;
-  FFS_PLOL             : out std_logic;
-  FFS_RLOL_0             : out std_logic;
-  FFS_RLOL_1             : out std_logic;
-  FFS_RLOL_2             : out std_logic;
-  FFS_RLOL_3             : out std_logic;
-  FFS_RLOS_HI_0             : out std_logic;
-  FFS_RLOS_HI_1             : out std_logic;
-  FFS_RLOS_HI_2             : out std_logic;
-  FFS_RLOS_HI_3             : out std_logic;
-  FFS_RLOS_LO_0             : out std_logic;
-  FFS_RLOS_LO_1             : out std_logic;
-  FFS_RLOS_LO_2             : out std_logic;
-  FFS_RLOS_LO_3             : out std_logic;
-  FFS_RXFBFIFO_ERROR_0             : out std_logic;
-  FFS_RXFBFIFO_ERROR_1             : out std_logic;
-  FFS_RXFBFIFO_ERROR_2             : out std_logic;
-  FFS_RXFBFIFO_ERROR_3             : out std_logic;
-  FFS_TXFBFIFO_ERROR_0             : out std_logic;
-  FFS_TXFBFIFO_ERROR_1             : out std_logic;
-  FFS_TXFBFIFO_ERROR_2             : out std_logic;
-  FFS_TXFBFIFO_ERROR_3             : out std_logic;
-  PCIE_PHYSTATUS_0             : out std_logic;
-  PCIE_PHYSTATUS_1             : out std_logic;
-  PCIE_PHYSTATUS_2             : out std_logic;
-  PCIE_PHYSTATUS_3             : out std_logic;
-  PCIE_RXVALID_0               : out std_logic;
-  PCIE_RXVALID_1               : out std_logic;
-  PCIE_RXVALID_2               : out std_logic;
-  PCIE_RXVALID_3               : out std_logic;
-  FFS_SKP_ADDED_0                  : out std_logic;
-  FFS_SKP_ADDED_1                  : out std_logic;
-  FFS_SKP_ADDED_2                  : out std_logic;
-  FFS_SKP_ADDED_3                  : out std_logic;
-  FFS_SKP_DELETED_0                : out std_logic;
-  FFS_SKP_DELETED_1                : out std_logic;
-  FFS_SKP_DELETED_2                : out std_logic;
-  FFS_SKP_DELETED_3                : out std_logic;
-  LDR_RX2CORE_0                    : out std_logic;
-  LDR_RX2CORE_1                    : out std_logic;
-  LDR_RX2CORE_2                    : out std_logic;
-  LDR_RX2CORE_3                    : out std_logic;
-  REFCK2CORE             : out std_logic;
-  SCIINT                : out std_logic;
-  SCIRDATA0             : out std_logic;
-  SCIRDATA1             : out std_logic;
-  SCIRDATA2             : out std_logic;
-  SCIRDATA3             : out std_logic;
-  SCIRDATA4             : out std_logic;
-  SCIRDATA5             : out std_logic;
-  SCIRDATA6             : out std_logic;
-  SCIRDATA7             : out std_logic;
-  REFCLK_TO_NQ          : out std_logic
-);
-end component;
-   attribute CONFIG_FILE: string;
-   attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE;
-   attribute QUAD_MODE: string;
-   attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
-   attribute PLL_SRC: string;
-   attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH1_CDR_SRC: string;
-   attribute CH1_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH3_CDR_SRC: string;
-   attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_REFCK2CORE: string;
-   attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
-   attribute black_box_pad_pin: string;
-   attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
-
-signal refclk_from_nq : std_logic := '0';
-signal fpsc_vlo : std_logic := '0';
-signal fpsc_vhi : std_logic := '1';
-signal cin : std_logic_vector (11 downto 0) := "000000000000";
-signal cout : std_logic_vector (19 downto 0);
-signal    tx_full_clk_ch1_sig   :   std_logic;
-signal    tx_full_clk_ch3_sig   :   std_logic;
-
-signal    refclk2fpga_sig  :   std_logic;
-signal    tx_pll_lol_qd_sig  :   std_logic;
-signal    rx_los_low_ch0_sig  :   std_logic;
-signal    rx_los_low_ch1_sig  :   std_logic;
-signal    rx_los_low_ch2_sig  :   std_logic;
-signal    rx_los_low_ch3_sig  :   std_logic;
-signal    rx_cdr_lol_ch0_sig  :   std_logic;
-signal    rx_cdr_lol_ch1_sig  :   std_logic;
-signal    rx_cdr_lol_ch2_sig  :   std_logic;
-signal    rx_cdr_lol_ch3_sig  :   std_logic;
-
-
-
-
-
-begin
-
-vlo_inst : VLO port map(Z => fpsc_vlo);
-vhi_inst : VHI port map(Z => fpsc_vhi);
-
-  refclk2fpga <= refclk2fpga_sig;
-    rx_los_low_ch1_s <= rx_los_low_ch1_sig;
-    rx_los_low_ch3_s <= rx_los_low_ch3_sig;
-    rx_cdr_lol_ch1_s <= rx_cdr_lol_ch1_sig;
-    rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
-  tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
-  tx_full_clk_ch1 <= tx_full_clk_ch1_sig;
-  tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
-
--- pcs_quad instance
-PCSD_INST : PCSD
---synopsys translate_off
-  generic map (CONFIG_FILE => USER_CONFIG_FILE,
-               QUAD_MODE => "SINGLE",
-               CH1_CDR_SRC => "REFCLK_CORE",
-               CH3_CDR_SRC => "REFCLK_CORE",
-               PLL_SRC  => "REFCLK_CORE"
-  )
---synopsys translate_on
-port map  (
-  REFCLKP => fpsc_vlo,
-  REFCLKN => fpsc_vlo,
-
------ CH0 -----
-  HDOUTP0 => open,
-  HDOUTN0 => open,
-  HDINP0 => fpsc_vlo,
-  HDINN0 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_0 => fpsc_vlo,
-  PCIE_RXPOLARITY_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_0 => fpsc_vlo,
-  PCIE_POWERDOWN_0_1 => fpsc_vlo,
-  PCIE_RXVALID_0 => open,
-  PCIE_PHYSTATUS_0 => open,
-  SCISELCH0 => fpsc_vlo,
-  SCIENCH0 => fpsc_vlo,
-  FF_RXI_CLK_0 => fpsc_vlo,
-  FF_TXI_CLK_0 => fpsc_vlo,
-  FF_EBRD_CLK_0 => fpsc_vlo,
-  FF_RX_F_CLK_0 => open,
-  FF_RX_H_CLK_0 => open,
-  FF_TX_F_CLK_0 => open,
-  FF_TX_H_CLK_0 => open,
-  FFC_CK_CORE_RX_0 => fpsc_vlo,
-  FF_TX_D_0_0 => fpsc_vlo,
-  FF_TX_D_0_1 => fpsc_vlo,
-  FF_TX_D_0_2 => fpsc_vlo,
-  FF_TX_D_0_3 => fpsc_vlo,
-  FF_TX_D_0_4 => fpsc_vlo,
-  FF_TX_D_0_5 => fpsc_vlo,
-  FF_TX_D_0_6 => fpsc_vlo,
-  FF_TX_D_0_7 => fpsc_vlo,
-  FF_TX_D_0_8 => fpsc_vlo,
-  FF_TX_D_0_9 => fpsc_vlo,
-  FF_TX_D_0_10 => fpsc_vlo,
-  FF_TX_D_0_11 => fpsc_vlo,
-  FF_TX_D_0_12 => fpsc_vlo,
-  FF_TX_D_0_13 => fpsc_vlo,
-  FF_TX_D_0_14 => fpsc_vlo,
-  FF_TX_D_0_15 => fpsc_vlo,
-  FF_TX_D_0_16 => fpsc_vlo,
-  FF_TX_D_0_17 => fpsc_vlo,
-  FF_TX_D_0_18 => fpsc_vlo,
-  FF_TX_D_0_19 => fpsc_vlo,
-  FF_TX_D_0_20 => fpsc_vlo,
-  FF_TX_D_0_21 => fpsc_vlo,
-  FF_TX_D_0_22 => fpsc_vlo,
-  FF_TX_D_0_23 => fpsc_vlo,
-  FF_RX_D_0_0 => open,
-  FF_RX_D_0_1 => open,
-  FF_RX_D_0_2 => open,
-  FF_RX_D_0_3 => open,
-  FF_RX_D_0_4 => open,
-  FF_RX_D_0_5 => open,
-  FF_RX_D_0_6 => open,
-  FF_RX_D_0_7 => open,
-  FF_RX_D_0_8 => open,
-  FF_RX_D_0_9 => open,
-  FF_RX_D_0_10 => open,
-  FF_RX_D_0_11 => open,
-  FF_RX_D_0_12 => open,
-  FF_RX_D_0_13 => open,
-  FF_RX_D_0_14 => open,
-  FF_RX_D_0_15 => open,
-  FF_RX_D_0_16 => open,
-  FF_RX_D_0_17 => open,
-  FF_RX_D_0_18 => open,
-  FF_RX_D_0_19 => open,
-  FF_RX_D_0_20 => open,
-  FF_RX_D_0_21 => open,
-  FF_RX_D_0_22 => open,
-  FF_RX_D_0_23 => open,
-
-  FFC_RRST_0 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_0 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_0 => fpsc_vlo,
-  FFC_PFIFO_CLR_0 => fpsc_vlo,
-  FFC_SB_INV_RX_0 => fpsc_vlo,
-  FFC_PCIE_CT_0 => fpsc_vlo,
-  FFC_PCI_DET_EN_0 => fpsc_vlo,
-  FFC_FB_LOOPBACK_0 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_0 => fpsc_vlo,
-  FFC_EI_EN_0 => fpsc_vlo,
-  FFC_LANE_TX_RST_0 => fpsc_vlo,
-  FFC_TXPWDNB_0 => fpsc_vlo,
-  FFC_LANE_RX_RST_0 => fpsc_vlo,
-  FFC_RXPWDNB_0 => fpsc_vlo,
-  FFS_RLOS_LO_0 => open,
-  FFS_RLOS_HI_0 => open,
-  FFS_PCIE_CON_0 => open,
-  FFS_PCIE_DONE_0 => open,
-  FFS_LS_SYNC_STATUS_0 => open,
-  FFS_CC_OVERRUN_0 => open,
-  FFS_CC_UNDERRUN_0 => open,
-  FFS_SKP_ADDED_0 => open,
-  FFS_SKP_DELETED_0 => open,
-  FFS_RLOL_0 => open,
-  FFS_RXFBFIFO_ERROR_0 => open,
-  FFS_TXFBFIFO_ERROR_0 => open,
-  LDR_CORE2TX_0 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_0 => fpsc_vlo,
-  LDR_RX2CORE_0 => open,
-  FFS_CDR_TRAIN_DONE_0 => open,
-  FFC_DIV11_MODE_TX_0 => fpsc_vlo,
-  FFC_RATE_MODE_TX_0 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_0 => fpsc_vlo,
-  FFC_RATE_MODE_RX_0 => fpsc_vlo,
-
------ CH1 -----
-  HDOUTP1 => hdoutp_ch1,
-  HDOUTN1 => hdoutn_ch1,
-  HDINP1 => hdinp_ch1,
-  HDINN1 => hdinn_ch1,
-  PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_1 => fpsc_vlo,
-  PCIE_RXPOLARITY_1 => fpsc_vlo,
-  PCIE_POWERDOWN_1_0 => fpsc_vlo,
-  PCIE_POWERDOWN_1_1 => fpsc_vlo,
-  PCIE_RXVALID_1 => open,
-  PCIE_PHYSTATUS_1 => open,
-  SCISELCH1 => sci_sel_ch1,
-  SCIENCH1 => fpsc_vhi,
-  FF_RXI_CLK_1 => rxiclk_ch1,
-  FF_TXI_CLK_1 => txiclk_ch1,
-  FF_EBRD_CLK_1 => fpsc_vlo,
-  FF_RX_F_CLK_1 => rx_full_clk_ch1,
-  FF_RX_H_CLK_1 => rx_half_clk_ch1,
-  FF_TX_F_CLK_1 => tx_full_clk_ch1_sig,
-  FF_TX_H_CLK_1 => tx_half_clk_ch1,
-  FFC_CK_CORE_RX_1 => fpga_rxrefclk_ch1,
-  FF_TX_D_1_0 => txdata_ch1(0),
-  FF_TX_D_1_1 => txdata_ch1(1),
-  FF_TX_D_1_2 => txdata_ch1(2),
-  FF_TX_D_1_3 => txdata_ch1(3),
-  FF_TX_D_1_4 => txdata_ch1(4),
-  FF_TX_D_1_5 => txdata_ch1(5),
-  FF_TX_D_1_6 => txdata_ch1(6),
-  FF_TX_D_1_7 => txdata_ch1(7),
-  FF_TX_D_1_8 => tx_k_ch1(0),
-  FF_TX_D_1_9 => tx_force_disp_ch1(0),
-  FF_TX_D_1_10 => tx_disp_sel_ch1(0),
-  FF_TX_D_1_11 => fpsc_vlo,
-  FF_TX_D_1_12 => txdata_ch1(8),
-  FF_TX_D_1_13 => txdata_ch1(9),
-  FF_TX_D_1_14 => txdata_ch1(10),
-  FF_TX_D_1_15 => txdata_ch1(11),
-  FF_TX_D_1_16 => txdata_ch1(12),
-  FF_TX_D_1_17 => txdata_ch1(13),
-  FF_TX_D_1_18 => txdata_ch1(14),
-  FF_TX_D_1_19 => txdata_ch1(15),
-  FF_TX_D_1_20 => tx_k_ch1(1),
-  FF_TX_D_1_21 => tx_force_disp_ch1(1),
-  FF_TX_D_1_22 => tx_disp_sel_ch1(1),
-  FF_TX_D_1_23 => fpsc_vlo,
-  FF_RX_D_1_0 => rxdata_ch1(0),
-  FF_RX_D_1_1 => rxdata_ch1(1),
-  FF_RX_D_1_2 => rxdata_ch1(2),
-  FF_RX_D_1_3 => rxdata_ch1(3),
-  FF_RX_D_1_4 => rxdata_ch1(4),
-  FF_RX_D_1_5 => rxdata_ch1(5),
-  FF_RX_D_1_6 => rxdata_ch1(6),
-  FF_RX_D_1_7 => rxdata_ch1(7),
-  FF_RX_D_1_8 => rx_k_ch1(0),
-  FF_RX_D_1_9 => rx_disp_err_ch1(0),
-  FF_RX_D_1_10 => rx_cv_err_ch1(0),
-  FF_RX_D_1_11 => open,
-  FF_RX_D_1_12 => rxdata_ch1(8),
-  FF_RX_D_1_13 => rxdata_ch1(9),
-  FF_RX_D_1_14 => rxdata_ch1(10),
-  FF_RX_D_1_15 => rxdata_ch1(11),
-  FF_RX_D_1_16 => rxdata_ch1(12),
-  FF_RX_D_1_17 => rxdata_ch1(13),
-  FF_RX_D_1_18 => rxdata_ch1(14),
-  FF_RX_D_1_19 => rxdata_ch1(15),
-  FF_RX_D_1_20 => rx_k_ch1(1),
-  FF_RX_D_1_21 => rx_disp_err_ch1(1),
-  FF_RX_D_1_22 => rx_cv_err_ch1(1),
-  FF_RX_D_1_23 => open,
-
-  FFC_RRST_1 => rx_serdes_rst_ch1_c,
-  FFC_SIGNAL_DETECT_1 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_1 => sb_felb_ch1_c,
-  FFC_PFIFO_CLR_1 => sb_felb_rst_ch1_c,
-  FFC_SB_INV_RX_1 => fpsc_vlo,
-  FFC_PCIE_CT_1 => fpsc_vlo,
-  FFC_PCI_DET_EN_1 => fpsc_vlo,
-  FFC_FB_LOOPBACK_1 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_1 => fpsc_vlo,
-  FFC_EI_EN_1 => fpsc_vlo,
-  FFC_LANE_TX_RST_1 => tx_pcs_rst_ch1_c,
-  FFC_TXPWDNB_1 => tx_pwrup_ch1_c,
-  FFC_LANE_RX_RST_1 => rx_pcs_rst_ch1_c,
-  FFC_RXPWDNB_1 => rx_pwrup_ch1_c,
-  FFS_RLOS_LO_1 => rx_los_low_ch1_sig,
-  FFS_RLOS_HI_1 => open,
-  FFS_PCIE_CON_1 => open,
-  FFS_PCIE_DONE_1 => open,
-  FFS_LS_SYNC_STATUS_1 => lsm_status_ch1_s,
-  FFS_CC_OVERRUN_1 => open,
-  FFS_CC_UNDERRUN_1 => open,
-  FFS_SKP_ADDED_1 => open,
-  FFS_SKP_DELETED_1 => open,
-  FFS_RLOL_1 => rx_cdr_lol_ch1_sig,
-  FFS_RXFBFIFO_ERROR_1 => open,
-  FFS_TXFBFIFO_ERROR_1 => open,
-  LDR_CORE2TX_1 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_1 => fpsc_vlo,
-  LDR_RX2CORE_1 => open,
-  FFS_CDR_TRAIN_DONE_1 => open,
-  FFC_DIV11_MODE_TX_1 => fpsc_vlo,
-  FFC_RATE_MODE_TX_1 => tx_div2_mode_ch1_c,
-  FFC_DIV11_MODE_RX_1 => fpsc_vlo,
-  FFC_RATE_MODE_RX_1 => rx_div2_mode_ch1_c,
-
------ CH2 -----
-  HDOUTP2 => open,
-  HDOUTN2 => open,
-  HDINP2 => fpsc_vlo,
-  HDINN2 => fpsc_vlo,
-  PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
-  PCIE_RXPOLARITY_2 => fpsc_vlo,
-  PCIE_POWERDOWN_2_0 => fpsc_vlo,
-  PCIE_POWERDOWN_2_1 => fpsc_vlo,
-  PCIE_RXVALID_2 => open,
-  PCIE_PHYSTATUS_2 => open,
-  SCISELCH2 => fpsc_vlo,
-  SCIENCH2 => fpsc_vlo,
-  FF_RXI_CLK_2 => fpsc_vlo,
-  FF_TXI_CLK_2 => fpsc_vlo,
-  FF_EBRD_CLK_2 => fpsc_vlo,
-  FF_RX_F_CLK_2 => open,
-  FF_RX_H_CLK_2 => open,
-  FF_TX_F_CLK_2 => open,
-  FF_TX_H_CLK_2 => open,
-  FFC_CK_CORE_RX_2 => fpsc_vlo,
-  FF_TX_D_2_0 => fpsc_vlo,
-  FF_TX_D_2_1 => fpsc_vlo,
-  FF_TX_D_2_2 => fpsc_vlo,
-  FF_TX_D_2_3 => fpsc_vlo,
-  FF_TX_D_2_4 => fpsc_vlo,
-  FF_TX_D_2_5 => fpsc_vlo,
-  FF_TX_D_2_6 => fpsc_vlo,
-  FF_TX_D_2_7 => fpsc_vlo,
-  FF_TX_D_2_8 => fpsc_vlo,
-  FF_TX_D_2_9 => fpsc_vlo,
-  FF_TX_D_2_10 => fpsc_vlo,
-  FF_TX_D_2_11 => fpsc_vlo,
-  FF_TX_D_2_12 => fpsc_vlo,
-  FF_TX_D_2_13 => fpsc_vlo,
-  FF_TX_D_2_14 => fpsc_vlo,
-  FF_TX_D_2_15 => fpsc_vlo,
-  FF_TX_D_2_16 => fpsc_vlo,
-  FF_TX_D_2_17 => fpsc_vlo,
-  FF_TX_D_2_18 => fpsc_vlo,
-  FF_TX_D_2_19 => fpsc_vlo,
-  FF_TX_D_2_20 => fpsc_vlo,
-  FF_TX_D_2_21 => fpsc_vlo,
-  FF_TX_D_2_22 => fpsc_vlo,
-  FF_TX_D_2_23 => fpsc_vlo,
-  FF_RX_D_2_0 => open,
-  FF_RX_D_2_1 => open,
-  FF_RX_D_2_2 => open,
-  FF_RX_D_2_3 => open,
-  FF_RX_D_2_4 => open,
-  FF_RX_D_2_5 => open,
-  FF_RX_D_2_6 => open,
-  FF_RX_D_2_7 => open,
-  FF_RX_D_2_8 => open,
-  FF_RX_D_2_9 => open,
-  FF_RX_D_2_10 => open,
-  FF_RX_D_2_11 => open,
-  FF_RX_D_2_12 => open,
-  FF_RX_D_2_13 => open,
-  FF_RX_D_2_14 => open,
-  FF_RX_D_2_15 => open,
-  FF_RX_D_2_16 => open,
-  FF_RX_D_2_17 => open,
-  FF_RX_D_2_18 => open,
-  FF_RX_D_2_19 => open,
-  FF_RX_D_2_20 => open,
-  FF_RX_D_2_21 => open,
-  FF_RX_D_2_22 => open,
-  FF_RX_D_2_23 => open,
-
-  FFC_RRST_2 => fpsc_vlo,
-  FFC_SIGNAL_DETECT_2 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_2 => fpsc_vlo,
-  FFC_PFIFO_CLR_2 => fpsc_vlo,
-  FFC_SB_INV_RX_2 => fpsc_vlo,
-  FFC_PCIE_CT_2 => fpsc_vlo,
-  FFC_PCI_DET_EN_2 => fpsc_vlo,
-  FFC_FB_LOOPBACK_2 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
-  FFC_EI_EN_2 => fpsc_vlo,
-  FFC_LANE_TX_RST_2 => fpsc_vlo,
-  FFC_TXPWDNB_2 => fpsc_vlo,
-  FFC_LANE_RX_RST_2 => fpsc_vlo,
-  FFC_RXPWDNB_2 => fpsc_vlo,
-  FFS_RLOS_LO_2 => open,
-  FFS_RLOS_HI_2 => open,
-  FFS_PCIE_CON_2 => open,
-  FFS_PCIE_DONE_2 => open,
-  FFS_LS_SYNC_STATUS_2 => open,
-  FFS_CC_OVERRUN_2 => open,
-  FFS_CC_UNDERRUN_2 => open,
-  FFS_SKP_ADDED_2 => open,
-  FFS_SKP_DELETED_2 => open,
-  FFS_RLOL_2 => open,
-  FFS_RXFBFIFO_ERROR_2 => open,
-  FFS_TXFBFIFO_ERROR_2 => open,
-  LDR_CORE2TX_2 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_2 => fpsc_vlo,
-  LDR_RX2CORE_2 => open,
-  FFS_CDR_TRAIN_DONE_2 => open,
-  FFC_DIV11_MODE_TX_2 => fpsc_vlo,
-  FFC_RATE_MODE_TX_2 => fpsc_vlo,
-  FFC_DIV11_MODE_RX_2 => fpsc_vlo,
-  FFC_RATE_MODE_RX_2 => fpsc_vlo,
-
------ CH3 -----
-  HDOUTP3 => hdoutp_ch3,
-  HDOUTN3 => hdoutn_ch3,
-  HDINP3 => hdinp_ch3,
-  HDINN3 => hdinn_ch3,
-  PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
-  PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
-  PCIE_RXPOLARITY_3 => fpsc_vlo,
-  PCIE_POWERDOWN_3_0 => fpsc_vlo,
-  PCIE_POWERDOWN_3_1 => fpsc_vlo,
-  PCIE_RXVALID_3 => open,
-  PCIE_PHYSTATUS_3 => open,
-  SCISELCH3 => sci_sel_ch3,
-  SCIENCH3 => fpsc_vhi,
-  FF_RXI_CLK_3 => fpsc_vlo,
-  FF_TXI_CLK_3 => txiclk_ch3,
-  FF_EBRD_CLK_3 => fpsc_vlo,
-  FF_RX_F_CLK_3 => rx_full_clk_ch3,
-  FF_RX_H_CLK_3 => rx_half_clk_ch3,
-  FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
-  FF_TX_H_CLK_3 => tx_half_clk_ch3,
-  FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
-  FF_TX_D_3_0 => txdata_ch3(0),
-  FF_TX_D_3_1 => txdata_ch3(1),
-  FF_TX_D_3_2 => txdata_ch3(2),
-  FF_TX_D_3_3 => txdata_ch3(3),
-  FF_TX_D_3_4 => txdata_ch3(4),
-  FF_TX_D_3_5 => txdata_ch3(5),
-  FF_TX_D_3_6 => txdata_ch3(6),
-  FF_TX_D_3_7 => txdata_ch3(7),
-  FF_TX_D_3_8 => tx_k_ch3,
-  FF_TX_D_3_9 => tx_force_disp_ch3,
-  FF_TX_D_3_10 => tx_disp_sel_ch3,
-  FF_TX_D_3_11 => fpsc_vlo,
-  FF_TX_D_3_12 => fpsc_vlo,
-  FF_TX_D_3_13 => fpsc_vlo,
-  FF_TX_D_3_14 => fpsc_vlo,
-  FF_TX_D_3_15 => fpsc_vlo,
-  FF_TX_D_3_16 => fpsc_vlo,
-  FF_TX_D_3_17 => fpsc_vlo,
-  FF_TX_D_3_18 => fpsc_vlo,
-  FF_TX_D_3_19 => fpsc_vlo,
-  FF_TX_D_3_20 => fpsc_vlo,
-  FF_TX_D_3_21 => fpsc_vlo,
-  FF_TX_D_3_22 => fpsc_vlo,
-  FF_TX_D_3_23 => fpsc_vlo,
-  FF_RX_D_3_0 => rxdata_ch3(0),
-  FF_RX_D_3_1 => rxdata_ch3(1),
-  FF_RX_D_3_2 => rxdata_ch3(2),
-  FF_RX_D_3_3 => rxdata_ch3(3),
-  FF_RX_D_3_4 => rxdata_ch3(4),
-  FF_RX_D_3_5 => rxdata_ch3(5),
-  FF_RX_D_3_6 => rxdata_ch3(6),
-  FF_RX_D_3_7 => rxdata_ch3(7),
-  FF_RX_D_3_8 => rx_k_ch3,
-  FF_RX_D_3_9 => rx_disp_err_ch3,
-  FF_RX_D_3_10 => rx_cv_err_ch3,
-  FF_RX_D_3_11 => open,
-  FF_RX_D_3_12 => open,
-  FF_RX_D_3_13 => open,
-  FF_RX_D_3_14 => open,
-  FF_RX_D_3_15 => open,
-  FF_RX_D_3_16 => open,
-  FF_RX_D_3_17 => open,
-  FF_RX_D_3_18 => open,
-  FF_RX_D_3_19 => open,
-  FF_RX_D_3_20 => open,
-  FF_RX_D_3_21 => open,
-  FF_RX_D_3_22 => open,
-  FF_RX_D_3_23 => open,
-
-  FFC_RRST_3 => rx_serdes_rst_ch3_c,
-  FFC_SIGNAL_DETECT_3 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
-  FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
-  FFC_SB_INV_RX_3 => fpsc_vlo,
-  FFC_PCIE_CT_3 => fpsc_vlo,
-  FFC_PCI_DET_EN_3 => fpsc_vlo,
-  FFC_FB_LOOPBACK_3 => fpsc_vlo,
-  FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
-  FFC_EI_EN_3 => fpsc_vlo,
-  FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
-  FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
-  FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
-  FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
-  FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
-  FFS_RLOS_HI_3 => open,
-  FFS_PCIE_CON_3 => open,
-  FFS_PCIE_DONE_3 => open,
-  FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
-  FFS_CC_OVERRUN_3 => open,
-  FFS_CC_UNDERRUN_3 => open,
-  FFS_SKP_ADDED_3 => open,
-  FFS_SKP_DELETED_3 => open,
-  FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
-  FFS_RXFBFIFO_ERROR_3 => open,
-  FFS_TXFBFIFO_ERROR_3 => open,
-  LDR_CORE2TX_3 => fpsc_vlo,
-  FFC_LDR_CORE2TX_EN_3 => fpsc_vlo,
-  LDR_RX2CORE_3 => open,
-  FFS_CDR_TRAIN_DONE_3 => open,
-  FFC_DIV11_MODE_TX_3 => fpsc_vlo,
-  FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
-  FFC_DIV11_MODE_RX_3 => fpsc_vlo,
-  FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
-
------ Auxilliary ----
-  SCIWDATA7 => sci_wrdata(7),
-  SCIWDATA6 => sci_wrdata(6),
-  SCIWDATA5 => sci_wrdata(5),
-  SCIWDATA4 => sci_wrdata(4),
-  SCIWDATA3 => sci_wrdata(3),
-  SCIWDATA2 => sci_wrdata(2),
-  SCIWDATA1 => sci_wrdata(1),
-  SCIWDATA0 => sci_wrdata(0),
-  SCIADDR5 => sci_addr(5),
-  SCIADDR4 => sci_addr(4),
-  SCIADDR3 => sci_addr(3),
-  SCIADDR2 => sci_addr(2),
-  SCIADDR1 => sci_addr(1),
-  SCIADDR0 => sci_addr(0),
-  SCIRDATA7 => sci_rddata(7),
-  SCIRDATA6 => sci_rddata(6),
-  SCIRDATA5 => sci_rddata(5),
-  SCIRDATA4 => sci_rddata(4),
-  SCIRDATA3 => sci_rddata(3),
-  SCIRDATA2 => sci_rddata(2),
-  SCIRDATA1 => sci_rddata(1),
-  SCIRDATA0 => sci_rddata(0),
-  SCIENAUX => fpsc_vhi,
-  SCISELAUX => sci_sel_quad,
-  SCIRD => sci_rd,
-  SCIWSTN => sci_wrn,
-  CYAWSTN => fpsc_vlo,
-  SCIINT => open,
-  FFC_CK_CORE_TX => fpga_txrefclk,
-  FFC_MACRO_RST => serdes_rst_qd_c,
-  FFC_QUAD_RST => rst_qd_c,
-  FFC_TRST => tx_serdes_rst_c,
-  FFS_PLOL => tx_pll_lol_qd_sig,
-  FFC_SYNC_TOGGLE => tx_sync_qd_c,
-  REFCK2CORE => refclk2fpga_sig,
-  CIN0 => fpsc_vlo,
-  CIN1 => fpsc_vlo,
-  CIN2 => fpsc_vlo,
-  CIN3 => fpsc_vlo,
-  CIN4 => fpsc_vlo,
-  CIN5 => fpsc_vlo,
-  CIN6 => fpsc_vlo,
-  CIN7 => fpsc_vlo,
-  CIN8 => fpsc_vlo,
-  CIN9 => fpsc_vlo,
-  CIN10 => fpsc_vlo,
-  CIN11 => fpsc_vlo,
-  COUT0 => open,
-  COUT1 => open,
-  COUT2 => open,
-  COUT3 => open,
-  COUT4 => open,
-  COUT5 => open,
-  COUT6 => open,
-  COUT7 => open,
-  COUT8 => open,
-  COUT9 => open,
-  COUT10 => open,
-  COUT11 => open,
-  COUT12 => open,
-  COUT13 => open,
-  COUT14 => open,
-  COUT15 => open,
-  COUT16 => open,
-  COUT17 => open,
-  COUT18 => open,
-  COUT19 => open,
-  REFCLK_FROM_NQ => refclk_from_nq,
-  REFCLK_TO_NQ => open);
-
-                                                                                              
-                                                                                              
-                                                                                              
---synopsys translate_off
-file_read : PROCESS
-VARIABLE open_status : file_open_status;
-FILE config : text;
-BEGIN
-   file_open (open_status, config, USER_CONFIG_FILE, read_mode);
-   IF (open_status = name_error) THEN
-      report "Auto configuration file for PCS module not found.  PCS internal configuration registers will not be initialized correctly during simulation!"
-      severity ERROR;
-   END IF;
-   wait;
-END PROCESS;
---synopsys translate_on
-end sfp_2_200_int_arch ;
diff --git a/code/med_ecp3_sfp_4_SODA.vhd b/code/med_ecp3_sfp_4_SODA.vhd
deleted file mode 100644
index cd56fd7..0000000
--- a/code/med_ecp3_sfp_4_SODA.vhd
+++ /dev/null
@@ -1,666 +0,0 @@
---4 channel Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity med_ecp3_sfp_4_soda is
-	generic(	SERDES_NUM : integer range 0 to 3 := 0;
-				IS_SYNC_SLAVE   : integer := c_NO);   -- hub downlink is NO slave
-	port(
-		OSC_CLK					: in  std_logic; -- 200 MHz reference clock
-		TX_DATACLK				: in  std_logic; -- 200 MHz data clock
-		SYSCLK					: in  std_logic; -- 100 MHz main clock net, synchronous to OSC clock
-		RESET						: in  std_logic; -- synchronous reset
-		CLEAR						: in  std_logic; -- asynchronous reset
-		---------------------------------------------------------------------------------------------------------------------------------------------------------
---		LINK_DISABLE_IN		: in  std_logic;	-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
-		---------------------------------------------------------------------------------------------------------------------------------------------------------
-		RX_HALF_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --100 MHz
-		RX_FULL_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --200 MHz
-		TX_HALF_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --100 MHz
-		TX_FULL_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --200 MHz
-
-		--Sync operation
-		RX_DLM_OUT				: out	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');
-		RX_DLM_WORD_OUT		: out	t_HUB_BYTE;	--std_logic_vector(4*8 - 1 downto 0)	:= (others => '0');
-		TX_DLM_IN				: in	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');
-		TX_DLM_WORD_IN			: in	t_HUB_BYTE;	--std_logic_vector(4*8 - 1 downto 0)	:= (others => '0');
-		TX_DLM_PREVIEW_IN		: in	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');	--PL!
-		LINK_PHASE_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');	--PL!
-
-		--SFP Connection 
-		SD_RXD_P_IN				: in	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_RXD_N_IN				: in	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_TXD_P_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_TXD_N_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_REFCLK_P_IN			: in	t_HUB_BIT;	--std_logic;  --not used
-		SD_REFCLK_N_IN			: in	t_HUB_BIT;	--std_logic;  --not used
-		SD_PRSNT_N_IN			: in	t_HUB_BIT;	--std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		SD_LOS_IN				: in	t_HUB_BIT;	--std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		SD_TXDIS_OUT			: out	t_HUB_BIT;	--std_logic := '0'; -- SFP disable
-		--Control Interface
-		SCI_DATA_IN				: in  std_logic_vector(7 downto 0) := (others => '0');
-		SCI_DATA_OUT			: out std_logic_vector(7 downto 0) := (others => '0');
-		SCI_ADDR					: in  std_logic_vector(8 downto 0) := (others => '0');
-		SCI_READ					: in  std_logic := '0';
-		SCI_WRITE				: in  std_logic := '0';
-		SCI_ACK					: out std_logic := '0';
-		SCI_NACK					: out std_logic := '0'
-	);
-end entity;
-
-
-architecture med_ecp3_sfp_4_soda_arch of med_ecp3_sfp_4_soda is
-
-  -- Placer Directives
-  attribute HGROUP : string;
-  -- for whole architecture
-  attribute HGROUP of med_ecp3_sfp_4_soda_arch : architecture  is "media_downlink_group";
-  attribute syn_sharing : string;
-  attribute syn_sharing of med_ecp3_sfp_4_soda_arch : architecture is "off";
-
-
-
-signal clk_200_osc						: std_logic;
-signal clk_200_txdata					: std_logic;
-signal rx_full_clk						: std_logic_vector(3 downto 0);
-signal rx_half_clk						: std_logic_vector(3 downto 0);	
-signal tx_full_clk						: std_logic_vector(3 downto 0);
-signal tx_half_clk						: std_logic_vector(3 downto 0);
-
-type t_tx_state 							is (cRESET,cSEND_IDLE,cSEND_DLM);
-type t_tx_proc_state 					is array(c_HUB_CHILDREN-1 downto 0) of t_tx_state;
-signal tx_proc_state						: t_tx_proc_state;
-
-signal tx_data								: t_HUB_BYTE;	--std_logic_vector(4*8-1 downto 0);
-signal tx_k									: std_logic_vector(3 downto 0);
-signal rx_data								: t_HUB_BYTE;	--std_logic_vector(4*8-1 downto 0);
-signal rx_k									: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_error							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-
-signal rst_n								: t_HUB_BIT;
-signal rst									: t_HUB_BIT;		-- PL!
-signal rx_serdes_rst						: t_HUB_BIT;
-signal tx_serdes_rst						: std_logic; 
-signal tx_pcs_rst							: t_HUB_BIT; 
-signal rx_pcs_rst							: t_HUB_BIT; 
-signal rst_qd								: t_HUB_BIT; 
-signal rst_down_quad						: std_logic; 
-signal serdes_rst_qd						: t_HUB_BIT; 
-signal serdes_rst_down_quad			: std_logic;  	-- combined serdes reset for whole quad
-signal sd_los_i							: t_HUB_BIT; 	--PL!
-
-signal dlm_received_S					: t_HUB_BIT;
-
-
-signal rx_los_low							: t_HUB_BIT; 
-signal lsm_status							: t_HUB_BIT; 
-signal rx_cdr_lol							: t_HUB_BIT; 
-signal tx_pll_lol							: t_HUB_BIT; 
-signal tx_pll_lol_quad					: std_logic; 	-- combined Loss-Of-Lock for whole quad
-
-signal sci_ch_i							: std_logic_vector(3 downto 0);
-signal sci_qd_i							: std_logic;
-signal sci_reg_i							: std_logic;
-signal sci_addr_i							: std_logic_vector(8 downto 0);
-signal sci_data_in_i						: std_logic_vector(7 downto 0);
-signal sci_data_out_i					: std_logic_vector(7 downto 0);
-signal sci_read_i							: std_logic;
-signal sci_write_i						: std_logic;
-signal sci_write_shift_i				: std_logic_vector(2 downto 0);
-signal sci_read_shift_i					: std_logic_vector(2 downto 0);
-
-signal wa_position						: t_HUB_NIBL	:= (others => (others => '1'));	--std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx					: t_HUB_NIBL	:= (others => (others => '1'));	--std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_allow							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal tx_allow_q							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_allow_q							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal link_phase_S						: t_HUB_BIT;	--std_logic_vector(3 downto 0);	--PL!
-signal request_retr_i					: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal start_retr_i						: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal request_retr_position_i		: t_HUB_BYTE;	--std_logic_vector(7 downto 0);
-signal start_retr_position_i			: t_HUB_BYTE;	--std_logic_vector(7 downto 0);
-signal send_link_reset_i				: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal make_link_reset_i				: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal got_link_ready_i					: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal internal_make_link_reset_out	: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-
-signal start_timer						: t_HUB_TIMER19	:= (others => (others => '0'));	--unsigned(18 downto 0)				:= (others => '0');
-
-signal rx_fsm_state						: t_HUB_NIBL;	--std_logic_vector(3 downto 0);
-signal tx_fsm_state						: t_HUB_NIBL;	--std_logic_vector(3 downto 0);
-
-signal stat_rx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal stat_tx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_rx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_tx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_reg							: std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state							: sci_ctrl;
-signal sci_timer							: t_HUB_TIMER13	:= (others => (others => '0'));	--unsigned(12 downto 0)				:= (others => '0');
-
--- fix signal names for constraining
-attribute syn_preserve		: boolean;
-attribute syn_keep			: boolean;
-attribute syn_useioff		: boolean;
-
-attribute syn_useioff	of sd_los_i				: signal is false;		-- do not use an IOFF for this signal
-
-attribute syn_preserve	of sci_ch_i				: signal is true;
-attribute syn_keep		of sci_ch_i				: signal is true;
-attribute syn_preserve	of sci_qd_i				: signal is true;
-attribute syn_keep		of sci_qd_i				: signal is true;
-attribute syn_preserve	of sci_reg_i			: signal is true;
-attribute syn_keep		of sci_reg_i			: signal is true;
-attribute syn_preserve	of sci_addr_i			: signal is true;
-attribute syn_keep		of sci_addr_i			: signal is true;
-attribute syn_preserve	of sci_data_in_i		: signal is true;
-attribute syn_keep		of sci_data_in_i		: signal is true;
-attribute syn_preserve	of sci_data_out_i		: signal is true;
-attribute syn_keep		of sci_data_out_i		: signal is true;
-attribute syn_preserve	of sci_read_i			: signal is true;
-attribute syn_keep		of sci_read_i			: signal is true;
-attribute syn_preserve	of sci_write_i			: signal is true;
-attribute syn_keep		of sci_write_i			: signal is true;
-attribute syn_preserve	of sci_write_shift_i	: signal is true;
-attribute syn_keep		of sci_write_shift_i	: signal is true;
-attribute syn_preserve	of	sci_read_shift_i	: signal is true;
-attribute syn_keep		of sci_read_shift_i	: signal is true;
-
-begin
-
-
---SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
-
-clk_200_osc			<= OSC_CLK;			-- This external clock is oscillator/pll generated !!!
-clk_200_txdata		<= TX_DATACLK;		-- This external clock is the rx_full of the uplink !!!
-
-
-gen_clocks	: for i in 0 to 3 generate
-
-	rst(i)					<=		(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i));
-	rst_n(i)					<=		not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i));
-
-	RX_HALF_CLK_OUT(i)	<= rx_half_clk(i);
-	RX_FULL_CLK_OUT(i)	<= rx_full_clk(i);
-	TX_HALF_CLK_OUT(i)	<= tx_half_clk(i);
-	TX_FULL_CLK_OUT(i)	<= tx_full_clk(i);
-
---	gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate		-- NO WAY IN HELL !! this downlink is a master
---		clk_200_i(i)			<= rx_full_clk(i);
---	end generate;
-
---	gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
---	clk_200_i(i)		<= clk_200_txdata;
---	clk_200_rxdn(i)	<= rx_full_clk(i);	-- These clocks are the rx_full of the DOWNLINKs !!!
---	end generate;
-end generate;
-
--------------------------------------------------  
--- Serdes
-------------------------------------------------- 
-THE_SERDES : entity work.serdes_4_sync_downstream
-	port map(
-	--	CHANNEL0 --	
-		hdinp_ch0				=> SD_RXD_P_IN(0),
-		hdinn_ch0				=> SD_RXD_N_IN(0),
-		hdoutp_ch0				=> SD_TXD_P_OUT(0),
-		hdoutn_ch0				=> SD_TXD_N_OUT(0),
-		rxiclk_ch0				=> clk_200_txdata,
-		sci_sel_ch0				=> sci_ch_i(0),
-		txiclk_ch0				=> clk_200_txdata,
-		rx_full_clk_ch0		=> rx_full_clk(0),
-		rx_half_clk_ch0		=> rx_half_clk(0),
-		tx_full_clk_ch0		=> tx_full_clk(0),
-		tx_half_clk_ch0		=> tx_half_clk(0),
-		fpga_rxrefclk_ch0		=> clk_200_osc,
-		txdata_ch0				=> tx_data(0),
-		tx_k_ch0					=> tx_k(0),
-		tx_force_disp_ch0		=> '0',
-		tx_disp_sel_ch0		=> '0',
-		rxdata_ch0				=> rx_data(0),
-		rx_k_ch0					=> rx_k(0),
-		rx_disp_err_ch0		=> open,
-		rx_cv_err_ch0			=> rx_error(0),
-		rx_serdes_rst_ch0_c  => rx_serdes_rst(0),
-		sb_felb_ch0_c			=> '0',
-		sb_felb_rst_ch0_c		=> '0',
-		tx_pcs_rst_ch0_c		=> tx_pcs_rst(0),
-		tx_pwrup_ch0_c			=> '1',
-		rx_pcs_rst_ch0_c		=> rx_pcs_rst(0),
-		rx_pwrup_ch0_c			=> '1',
-		rx_los_low_ch0_s		=> rx_los_low(0),
-		lsm_status_ch0_s		=> lsm_status(0),
-		rx_cdr_lol_ch0_s		=> rx_cdr_lol(0),
-		tx_div2_mode_ch0_c	=> '0',
-		rx_div2_mode_ch0_c	=> '0',
-	--	CHANNEL1 --	
-		hdinp_ch1				=> SD_RXD_P_IN(1),
-		hdinn_ch1				=> SD_RXD_N_IN(1),
-		hdoutp_ch1				=> SD_TXD_P_OUT(1),
-		hdoutn_ch1				=> SD_TXD_N_OUT(1),
-		rxiclk_ch1				=> clk_200_txdata,
-		sci_sel_ch1				=> sci_ch_i(1),
-		txiclk_ch1				=> clk_200_txdata,
-		rx_full_clk_ch1		=> rx_full_clk(1),
-		rx_half_clk_ch1		=> rx_half_clk(1),
-		tx_full_clk_ch1		=> tx_full_clk(1),
-		tx_half_clk_ch1		=> tx_half_clk(1),
-		fpga_rxrefclk_ch1		=> clk_200_osc,
-		txdata_ch1				=> tx_data(1),
-		tx_k_ch1					=> tx_k(1),
-		tx_force_disp_ch1		=> '0',
-		tx_disp_sel_ch1		=> '0',
-		rxdata_ch1				=> rx_data(1),
-		rx_k_ch1					=> rx_k(1),
-		rx_disp_err_ch1		=> open,
-		rx_cv_err_ch1			=> rx_error(1),
-		rx_serdes_rst_ch1_c  => rx_serdes_rst(1),
-		sb_felb_ch1_c			=> '0',
-		sb_felb_rst_ch1_c		=> '0',
-		tx_pcs_rst_ch1_c		=> tx_pcs_rst(1),
-		tx_pwrup_ch1_c			=> '1',
-		rx_pcs_rst_ch1_c		=> rx_pcs_rst(1),
-		rx_pwrup_ch1_c			=> '1',
-		rx_los_low_ch1_s		=> rx_los_low(1),
-		lsm_status_ch1_s		=> lsm_status(1),
-		rx_cdr_lol_ch1_s		=> rx_cdr_lol(1),
-		tx_div2_mode_ch1_c	=> '0',
-		rx_div2_mode_ch1_c	=> '0',
-	--	CHANNEL2 --	
-		hdinp_ch2				=> SD_RXD_P_IN(2),
-		hdinn_ch2				=> SD_RXD_N_IN(2),
-		hdoutp_ch2				=> SD_TXD_P_OUT(2),
-		hdoutn_ch2				=> SD_TXD_N_OUT(2),
-		rxiclk_ch2				=> clk_200_txdata,
-		sci_sel_ch2				=> sci_ch_i(2),
-		txiclk_ch2				=> clk_200_txdata,
-		rx_full_clk_ch2		=> rx_full_clk(2),
-		rx_half_clk_ch2		=> rx_half_clk(2),
-		tx_full_clk_ch2		=> tx_full_clk(2),
-		tx_half_clk_ch2		=> tx_half_clk(2),
-		fpga_rxrefclk_ch2		=> clk_200_osc,
-		txdata_ch2				=> tx_data(2),
-		tx_k_ch2					=> tx_k(2),
-		tx_force_disp_ch2		=> '0',
-		tx_disp_sel_ch2		=> '0',
-		rxdata_ch2				=> rx_data(2),
-		rx_k_ch2					=> rx_k(2),
-		rx_disp_err_ch2		=> open,
-		rx_cv_err_ch2			=> rx_error(2),
-		rx_serdes_rst_ch2_c  => rx_serdes_rst(2),
-		sb_felb_ch2_c			=> '0',
-		sb_felb_rst_ch2_c		=> '0',
-		tx_pcs_rst_ch2_c		=> tx_pcs_rst(2),
-		tx_pwrup_ch2_c			=> '1',
-		rx_pcs_rst_ch2_c		=> rx_pcs_rst(2),
-		rx_pwrup_ch2_c			=> '1',
-		rx_los_low_ch2_s		=> rx_los_low(2),
-		lsm_status_ch2_s		=> lsm_status(2),
-		rx_cdr_lol_ch2_s		=> rx_cdr_lol(2),
-		tx_div2_mode_ch2_c	=> '0',
-		rx_div2_mode_ch2_c	=> '0',
-	--	CHANNEL3 --	
-		hdinp_ch3				=> SD_RXD_P_IN(3),
-		hdinn_ch3				=> SD_RXD_N_IN(3),
-		hdoutp_ch3				=> SD_TXD_P_OUT(3),
-		hdoutn_ch3				=> SD_TXD_N_OUT(3),
-		rxiclk_ch3				=> clk_200_txdata,
-		sci_sel_ch3				=> sci_ch_i(3),
-		txiclk_ch3				=> clk_200_txdata,
-		rx_full_clk_ch3		=> rx_full_clk(3),
-		rx_half_clk_ch3		=> rx_half_clk(3),
-		tx_full_clk_ch3		=> tx_full_clk(3),
-		tx_half_clk_ch3		=> tx_half_clk(3),
-		fpga_rxrefclk_ch3		=> clk_200_osc,
-		txdata_ch3				=> tx_data(3),
-		tx_k_ch3					=> tx_k(3),
-		tx_force_disp_ch3		=> '0',
-		tx_disp_sel_ch3		=> '0',
-		rxdata_ch3				=> rx_data(3),
-		rx_k_ch3					=> rx_k(3),
-		rx_disp_err_ch3		=> open,
-		rx_cv_err_ch3			=> rx_error(3),
-		rx_serdes_rst_ch3_c  => rx_serdes_rst(3),
-		sb_felb_ch3_c			=> '0',
-		sb_felb_rst_ch3_c		=> '0',
-		tx_pcs_rst_ch3_c		=> tx_pcs_rst(3),
-		tx_pwrup_ch3_c			=> '1',
-		rx_pcs_rst_ch3_c		=> rx_pcs_rst(3),
-		rx_pwrup_ch3_c			=> '1',
-		rx_los_low_ch3_s		=> rx_los_low(3),
-		lsm_status_ch3_s		=> lsm_status(3),
-		rx_cdr_lol_ch3_s		=> rx_cdr_lol(3),
-		tx_div2_mode_ch3_c	=> '0',
-		rx_div2_mode_ch3_c	=> '0',
-	--	COMMON --	
-		sci_wrdata				=> sci_data_in_i,
-		sci_rddata				=> sci_data_out_i,
-		sci_addr					=> sci_addr_i(5 downto 0),
-		sci_sel_quad			=> sci_qd_i,
-		sci_rd					=> sci_read_i,
-		sci_wrn					=> sci_write_i,
-
-		fpga_txrefclk			=> clk_200_txdata,
-		tx_serdes_rst_c		=> '0',	--tx_serdes_rst(0),	-- resets tx_pll	PL 1906
-		tx_pll_lol_qd_s		=> tx_pll_lol_quad,
-		tx_sync_qd_c			=> '0',			-- unused; signal to synchronise channels/serdesses for multi-channel protocols
-		rst_qd_c					=> rst_down_quad,
-		serdes_rst_qd_c		=> serdes_rst_down_quad
-	);
-
--------------------------
--- combined quad reset --
--------------------------
---rst_down_quad				<= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
-rst_down_quad				<= RESET;	-- PL: 18/06/14
---serdes_rst_down_quad		<= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0';
-serdes_rst_down_quad		<= '0';		-- PL: 23/06/14
-
-generated_logic	: for i in 0 to 3 generate
-
---	SD_TXDIS_OUT(i)			<= LINK_DISABLE_IN;	--not (rx_allow_q(i) or not IS_SLAVE);   --slave only switches on when RX is ready
-	SD_TXDIS_OUT(i)			<= '0';	--not rx_allow_q(i);   --slave only switches on when RX is ready
-
-	tx_pll_lol(i)			<= tx_pll_lol_quad;
-	
-	------------------------------------------------- 
-	-- Reset FSM & Link states
-	------------------------------------------------- 
-	THE_RX_FSM : rx_reset_fsm
-	port map(
-		RST_N						=> rst_n(i),
-		RX_REFCLK				=> rx_full_clk(i),	
-		TX_PLL_LOL_QD_S		=> tx_pll_lol(i),
-		RX_SERDES_RST_CH_C	=> rx_serdes_rst(i),
-		RX_CDR_LOL_CH_S		=> rx_cdr_lol(i),
-		RX_LOS_LOW_CH_S		=> rx_los_low(i),
-		RX_PCS_RST_CH_C		=> rx_pcs_rst(i),
-		WA_POSITION				=> wa_position_rx(i),
-		STATE_OUT				=> rx_fsm_state(i)
-	);
-
-	THE_TX_RESET_FSM : tx_reset_fsm
-	port map(
-		RST_N						=> rst_n(i),
-		TX_REFCLK				=> clk_200_txdata,
-		TX_PLL_LOL_QD_S		=> tx_pll_lol(i),
-		RST_QD_C					=> rst_qd(i),
-		TX_PCS_RST_CH_C		=> tx_pcs_rst(i),
-		STATE_OUT				=> tx_fsm_state(i)
-	);
-	
-
-	-- Master does not do bit-locking    
-	wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0";
-
-	
-	PROC_ALLOW : process(clk_200_txdata)	--clk_200_i(i))
-	begin
-		if rising_edge(clk_200_txdata) then	-- clk_200_txdata ??
-			if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
-				rx_allow(i) <= '1';
-				tx_allow(i) <= '1';
-			else
-				rx_allow(i) <= '0';
-				tx_allow(i) <= '1';
-			end if;
-		end if;
-	end process;
-
-	rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK);
-	tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
-
-
-	PROC_START_TIMER : process(clk_200_txdata)	--clk_200_i(i))
-	begin
-		if rising_edge(clk_200_txdata) then
-			if got_link_ready_i(i) = '1' then
-				if start_timer(i)(start_timer'left) = '0' then
-					start_timer(i) <= start_timer(i) + 1;
-				end if;  
-			else
-				start_timer(i) <= (others => '0');
-			end if;
-		end if;
-	end process;
-	------------------------------------------------- 
-	-- TX Data
-	-------------------------------------------------         
-	the_tx_fsm : process(clk_200_txdata)
-	begin
-		if rising_edge(clk_200_txdata) then
-			if (RESET='1') then
-				tx_proc_state(i)	<= cRESET;
-				tx_data(i)			<= x"00"; -- idle
-				tx_k(i)				<= '0';					
-				link_phase_S(i)	<= c_PHASE_L;			
-			else
-				link_phase_S(i)	<= not(link_phase_S(i));			
-				case tx_proc_state(i) is
-					when cSEND_IDLE	=>
-						if (TX_DLM_IN(i)='0') then
-							tx_proc_state(i)	<= cSEND_IDLE;
-							tx_data(i)			<= x"BC"; -- idle
-							tx_k(i)				<= '1';
-						else
-							tx_proc_state(i)	<= cSEND_DLM;
-							tx_data(i)			<= x"DC"; -- dlm
-							tx_k(i)				<= '1';
-						end if;
-					when cSEND_DLM	=>
-						tx_proc_state(i)		<= cSEND_IDLE;
-						tx_data(i)				<= TX_DLM_WORD_IN(i);
-						tx_k(i)					<= '0';
-					when others	=>
-						tx_proc_state(i)		<= cSEND_IDLE;
-						tx_data(i)				<= x"BC"; -- idle
-						tx_k(i)					<= '1';
-				end case;
-			end if;
-		end if;
-	end process;
---	THE_TX : soda_tx_control
---	port map(
---		CLK_200						=> clk_200_txdata,	--tx_full_clk(i),	--clk_200_i(i),
---		CLK_100						=> SYSCLK,
---		RESET_IN						=> rst(i),		--CLEAR, PL!
---
---		TX_DATA_IN					=> (others => '0'),	--	MED_DATA_IN(i),
---		TX_PACKET_NUMBER_IN		=> (others => '0'),	--	MED_PACKET_NUM_IN(i),
---		TX_WRITE_IN					=> '0',					--	MED_DATAREADY_IN(i),
---		TX_READ_OUT					=> open,					--	MED_READ_OUT(i),
---
---		TX_DATA_OUT					=> tx_data(i),
---		TX_K_OUT						=> tx_k(i),
---
---		REQUEST_RETRANSMIT_IN	=> request_retr_i(i),             --TODO
---		REQUEST_POSITION_IN		=> request_retr_position_i(i),    --TODO
---
---		START_RETRANSMIT_IN		=> start_retr_i(i),               --TODO
---		START_POSITION_IN			=> request_retr_position_i(i),    --TODO
---
---		TX_DLM_PREVIEW_IN			=>	TX_DLM_PREVIEW_IN(i),
---		SEND_DLM						=> TX_DLM_IN(i),
---		SEND_DLM_WORD				=> TX_DLM_WORD_IN(i),
---
---		SEND_LINK_RESET_IN		=> '0',	--CTRL_OP(i)(15),
---		TX_ALLOW_IN					=> tx_allow(i),
---		RX_ALLOW_IN					=> rx_allow(i),
---		LINK_PHASE_OUT				=>	link_phase_S(i),		--PL!
---
---		DEBUG_OUT					=> debug_tx_control_i(i),
---		STAT_REG_OUT				=> stat_tx_control_i(i)
---	);
-
-	LINK_PHASE_OUT(i)		<= link_phase_S(i);		--PL!
-	
-
-	-------------------------------------------------      
-	-- RX Data
-	-------------------------------------------------
-	the_rx_proc : process(clk_200_txdata)
-	begin
-		if rising_edge(clk_200_txdata) then
-			RX_DLM_OUT(i)			<= '0';
-			if dlm_received_S(i)='1' then
-				dlm_received_S(i)		<= '0';
-				RX_DLM_OUT(i)			<= '1';
-				RX_DLM_WORD_OUT(i)	<= rx_data(i);
-			elsif (rx_data(i)=x"DC") and (rx_k(i)='1') then
-				dlm_received_S(i)		<= '1';
-			end if;
-		end if;
-	end process;
---	THE_RX_CONTROL : rx_control
---	port map(
---		CLK_200                        => clk_200_txdata,	--clk_200_i(i), --PL!
---		CLK_100                        => SYSCLK,
---		RESET_IN                       => rst(i),		--CLEAR, PL!
---
---		RX_DATA_OUT                    => open,	--	MED_DATA_OUT(i),
---		RX_PACKET_NUMBER_OUT           => open,	--	MED_PACKET_NUM_OUT(i),
---		RX_WRITE_OUT                   => open,	--	MED_DATAREADY_OUT(i),
---		RX_READ_IN                     => '0',		--	MED_READ_IN(i),
---
---		RX_DATA_IN                     => rx_data(i),
---		RX_K_IN                        => rx_k(i),
---
---		REQUEST_RETRANSMIT_OUT         => request_retr_i(i),
---		REQUEST_POSITION_OUT           => request_retr_position_i(i),
---
---		START_RETRANSMIT_OUT           => start_retr_i(i),
---		START_POSITION_OUT             => start_retr_position_i(i),
---
---		--send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
---		RX_DLM                         => RX_DLM_OUT(i),
---		RX_DLM_WORD                    => RX_DLM_WORD_OUT(i),
---
---		SEND_LINK_RESET_OUT            => send_link_reset_i(i),
---		MAKE_RESET_OUT                 => make_link_reset_i(i),
---		RX_ALLOW_IN                    => rx_allow(i),
---		GOT_LINK_READY                 => got_link_ready_i(i),
---
---		DEBUG_OUT                      => debug_rx_control_i(i),
---		STAT_REG_OUT                   => stat_rx_control_i(i)
---	);   
-
-	internal_make_link_reset_out(i)	<= make_link_reset_i(i)	when (IS_SYNC_SLAVE=c_YES) else '0';
-	sd_los_i(i)								<= SD_LOS_IN(i)			when rising_edge(SYSCLK); --PL! 200115
-	
-end generate;    
-    
--------------------------------------------------      
--- SCI
--------------------------------------------------      
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process 
-variable cnt : integer range 0 to 4 := 0;
-begin
-wait until rising_edge(SYSCLK);
-	SCI_ACK <= '0';
-	case sci_state is
-	when IDLE =>
-		sci_ch_i        <= x"0";
-		sci_qd_i        <= '0';
-		sci_reg_i       <= '0';
-		sci_read_i      <= '0';
-		sci_write_i     <= '0';
-		sci_timer(0)    <= sci_timer(0) + 1;
-		sci_timer(1)    <= sci_timer(1) + 1;
-		sci_timer(2)    <= sci_timer(2) + 1;
-		sci_timer(3)    <= sci_timer(3) + 1;
-		if SCI_READ = '1' or SCI_WRITE = '1' then
-			sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_addr_i    <= SCI_ADDR;
-			sci_data_in_i <= SCI_DATA_IN;
-			sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_state     <= SCTRL;
-		else
-			if sci_timer(0)(sci_timer'left) = '1' then
-				sci_timer(0)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(1)(sci_timer'left) = '1' then
-				sci_timer(1)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(2)(sci_timer'left) = '1' then
-				sci_timer(2)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(3)(sci_timer'left) = '1' then
-				sci_timer(3)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-		end if;      
-when SCTRL =>
-	if sci_reg_i = '1' then
-		SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-		SCI_ACK       <= '1';
-		sci_write_i   <= '0';
-		sci_read_i    <= '0';
-		sci_state     <= IDLE;
-	else
-		sci_state     <= SCTRL_WAIT;
-	end if;
-when SCTRL_WAIT   =>
-	sci_state       <= SCTRL_WAIT2;
-when SCTRL_WAIT2  =>
-	sci_state       <= SCTRL_FINISH;
-when SCTRL_FINISH =>
-	SCI_DATA_OUT    <= sci_data_out_i;
-	SCI_ACK         <= '1';
-	sci_write_i     <= '0';
-	sci_read_i      <= '0';
-	sci_state       <= IDLE;
-
-when GET_WA =>
-	if cnt = 4 then
-		cnt           := 0;
-		sci_state     <= IDLE;
-	else
-		sci_state     <= GET_WA_WAIT;
-		sci_addr_i    <= '0' & x"22";
-		sci_ch_i      <= x"0";
-		sci_ch_i(cnt) <= '1';
-		sci_read_i    <= '1';
-	end if;
-when GET_WA_WAIT  =>
-	sci_state       <= GET_WA_WAIT2;
-when GET_WA_WAIT2 =>
-	sci_state       <= GET_WA_FINISH;
-when GET_WA_FINISH =>
---		wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-	wa_position(cnt) <= sci_data_out_i(3 downto 0);
-	sci_state       <= GET_WA;    
-	cnt             := cnt + 1;
-end case;
-
-if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-	SCI_NACK <= '1';
-else
-	SCI_NACK <= '0';
-end if;
-
-end process;
-
-
-
-end med_ecp3_sfp_4_soda_arch;
\ No newline at end of file
diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd
deleted file mode 100644
index 2e6a78d..0000000
--- a/code/med_ecp3_sfp_4_sync_down.vhd
+++ /dev/null
@@ -1,662 +0,0 @@
---4 channel Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity med_ecp3_sfp_4_sync_down is
-	generic(	SERDES_NUM : integer range 0 to 3 := 0;
-				IS_SYNC_SLAVE   : integer := c_NO);   -- hub downlink is NO slave
-	port(
-		OSC_CLK					: in  std_logic; -- 200 MHz reference clock
-		TX_DATACLK				: in  std_logic; -- 200 MHz data clock
-		SYSCLK					: in  std_logic; -- 100 MHz main clock net, synchronous to OSC clock
-		RESET						: in  std_logic; -- synchronous reset
-		CLEAR						: in  std_logic; -- asynchronous reset
-		---------------------------------------------------------------------------------------------------------------------------------------------------------
-		LINK_DISABLE_IN		: in  std_logic;	-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
-		---------------------------------------------------------------------------------------------------------------------------------------------------------
-		--Internal Connection TX
-		MED_DATA_IN				: in  t_HUB_WORD;	-- std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
-		MED_PACKET_NUM_IN		: in	t_HUB_NUM;	--std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
-		MED_DATAREADY_IN		: in  std_logic_vector(3 downto 0);
-		MED_READ_OUT			: out std_logic_vector(3 downto 0) := (others => '0');
-		--Internal Connection RX
-		MED_DATA_OUT			: out  t_HUB_WORD;	-- std_logic_vector(4*c_DATA_WIDTH-1 downto 0)	:= (others => '0');
-		MED_PACKET_NUM_OUT	: out  t_HUB_NUM;	-- std_logic_vector(4*c_NUM_WIDTH-1 downto 0)	:= (others => '0');
-		MED_DATAREADY_OUT		: out std_logic_vector(3 downto 0) 						:= (others => '0');
-		MED_READ_IN				: in  std_logic_vector(3 downto 0);
-		RX_HALF_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --100 MHz
-		RX_FULL_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --200 MHz
-		TX_HALF_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --100 MHz
-		TX_FULL_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --200 MHz
-
-		--Sync operation
-		RX_DLM					: out	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');
-		RX_DLM_WORD				: out	t_HUB_BYTE;	--std_logic_vector(4*8 - 1 downto 0)	:= (others => '0');
-		TX_DLM					: in	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');
-		TX_DLM_WORD				: in	t_HUB_BYTE;	--std_logic_vector(4*8 - 1 downto 0)	:= (others => '0');
-		TX_DLM_PREVIEW_IN		: in	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');	--PL!
-		LINK_PHASE_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');	--PL!
-
-		--SFP Connection 
-		SD_RXD_P_IN				: in	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_RXD_N_IN				: in	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_TXD_P_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_TXD_N_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_REFCLK_P_IN			: in	t_HUB_BIT;	--std_logic;  --not used
-		SD_REFCLK_N_IN			: in	t_HUB_BIT;	--std_logic;  --not used
-		SD_PRSNT_N_IN			: in	t_HUB_BIT;	--std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		SD_LOS_IN				: in	t_HUB_BIT;	--std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		SD_TXDIS_OUT			: out	t_HUB_BIT;	--std_logic := '0'; -- SFP disable
-		--Control Interface
-		SCI_DATA_IN				: in  std_logic_vector(7 downto 0) := (others => '0');
-		SCI_DATA_OUT			: out std_logic_vector(7 downto 0) := (others => '0');
-		SCI_ADDR					: in  std_logic_vector(8 downto 0) := (others => '0');
-		SCI_READ					: in  std_logic := '0';
-		SCI_WRITE				: in  std_logic := '0';
-		SCI_ACK					: out std_logic := '0';
-		SCI_NACK					: out std_logic := '0';
-		-- Status and control port
---		STAT_OP					: out	t_HUB_WORD;	--std_logic_vector (15 downto 0);
---		CTRL_OP					: in	t_HUB_WORD;	--std_logic_vector (15 downto 0) := (others => '0');
-		STAT_OP					: out	std_logic_vector (63 downto 0);
-		CTRL_OP					: in	std_logic_vector (63 downto 0) := (others => '0');
-		STAT_DEBUG				: out std_logic_vector (63 downto 0);
-		CTRL_DEBUG				: in  std_logic_vector (63 downto 0) := (others => '0')
-	);
-end entity;
-
-
-architecture med_ecp3_sfp_4_sync_down_arch of med_ecp3_sfp_4_sync_down is
-
-  -- Placer Directives
-  attribute HGROUP : string;
-  -- for whole architecture
-  attribute HGROUP of med_ecp3_sfp_4_sync_down_arch : architecture  is "media_downlink_group";
-  attribute syn_sharing : string;
-  attribute syn_sharing of med_ecp3_sfp_4_sync_down_arch : architecture is "off";
-  attribute syn_hier     : string;
-  attribute syn_hier of med_ecp3_sfp_4_sync_down_arch : architecture is "hard";
-
-signal clk_200_osc						: std_logic;
-signal clk_200_txdata					: std_logic;
-signal clk_200_rxdn						: std_logic_vector(3 downto 0);
-signal clk_200_i							: std_logic_vector(3 downto 0);
-signal rx_full_clk						: std_logic_vector(3 downto 0);
-signal rx_half_clk						: std_logic_vector(3 downto 0);	
-signal tx_full_clk						: std_logic_vector(3 downto 0);
-signal tx_half_clk						: std_logic_vector(3 downto 0);
-
-signal tx_data								: t_HUB_BYTE;	--std_logic_vector(4*8-1 downto 0);
-signal tx_k									: std_logic_vector(3 downto 0);
-signal rx_data								: t_HUB_BYTE;	--std_logic_vector(4*8-1 downto 0);
-signal rx_k									: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_error							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-
-signal rst_n								: t_HUB_BIT;
-signal rst									: t_HUB_BIT;		-- PL!
-signal rx_serdes_rst						: t_HUB_BIT;
-signal tx_serdes_rst						: std_logic; 
-signal tx_pcs_rst							: t_HUB_BIT; 
-signal rx_pcs_rst							: t_HUB_BIT; 
-signal rst_qd								: t_HUB_BIT; 
-signal rst_down_quad						: std_logic; 
-signal serdes_rst_qd						: t_HUB_BIT; 
-signal serdes_rst_down_quad			: std_logic;  	-- combined serdes reset for whole quad
-signal sd_los_i							: t_HUB_BIT; 	--PL!
-
-signal rx_los_low							: t_HUB_BIT; 
-signal lsm_status							: t_HUB_BIT; 
-signal rx_cdr_lol							: t_HUB_BIT; 
-signal tx_pll_lol							: t_HUB_BIT; 
-signal tx_pll_lol_quad					: std_logic; 	-- combined Loss-Of-Lock for whole quad
-
-signal sci_ch_i							: std_logic_vector(3 downto 0);
-signal sci_qd_i							: std_logic;
-signal sci_reg_i							: std_logic;
-signal sci_addr_i							: std_logic_vector(8 downto 0);
-signal sci_data_in_i						: std_logic_vector(7 downto 0);
-signal sci_data_out_i					: std_logic_vector(7 downto 0);
-signal sci_read_i							: std_logic;
-signal sci_write_i						: std_logic;
-signal sci_write_shift_i				: std_logic_vector(2 downto 0);
-signal sci_read_shift_i					: std_logic_vector(2 downto 0);
-
-signal wa_position						: t_HUB_NIBL	:= (others => (others => '1'));	--std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx					: t_HUB_NIBL	:= (others => (others => '1'));	--std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_allow							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal tx_allow_q							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_allow_q							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal link_phase_S						: t_HUB_BIT;	--std_logic_vector(3 downto 0);	--PL!
-signal request_retr_i					: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal start_retr_i						: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal request_retr_position_i		: t_HUB_BYTE;	--std_logic_vector(7 downto 0);
-signal start_retr_position_i			: t_HUB_BYTE;	--std_logic_vector(7 downto 0);
-signal send_link_reset_i				: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal make_link_reset_i				: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal got_link_ready_i					: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal internal_make_link_reset_out	: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-
-signal start_timer						: t_HUB_TIMER19	:= (others => (others => '0'));	--unsigned(18 downto 0)				:= (others => '0');
-signal watchdog_timer					: t_HUB_TIMER21	:= (others => (others => '0'));	--unsigned(20 downto 0)				:= (others => '0');
-signal watchdog_trigger					: t_HUB_BIT			:= (others => '0');					--std_logic_vector(3 downto 0)	:= (others => '0');
-
-signal rx_fsm_state						: t_HUB_NIBL;	--std_logic_vector(3 downto 0);
-signal tx_fsm_state						: t_HUB_NIBL;	--std_logic_vector(3 downto 0);
-
-signal stat_rx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal stat_tx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_rx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_tx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_reg							: std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state							: sci_ctrl;
-signal sci_timer							: t_HUB_TIMER13	:= (others => (others => '0'));	--unsigned(12 downto 0)				:= (others => '0');
-
--- fix signal names for constraining
-attribute syn_preserve		: boolean;
-attribute syn_keep			: boolean;
-attribute syn_useioff		: boolean;
-
-attribute syn_useioff	of sd_los_i				: signal is false;		-- do not use an IOFF for this signal
-
-attribute syn_preserve	of sci_ch_i				: signal is true;
-attribute syn_keep		of sci_ch_i				: signal is true;
-attribute syn_preserve	of sci_qd_i				: signal is true;
-attribute syn_keep		of sci_qd_i				: signal is true;
-attribute syn_preserve	of sci_reg_i			: signal is true;
-attribute syn_keep		of sci_reg_i			: signal is true;
-attribute syn_preserve	of sci_addr_i			: signal is true;
-attribute syn_keep		of sci_addr_i			: signal is true;
-attribute syn_preserve	of sci_data_in_i		: signal is true;
-attribute syn_keep		of sci_data_in_i		: signal is true;
-attribute syn_preserve	of sci_data_out_i		: signal is true;
-attribute syn_keep		of sci_data_out_i		: signal is true;
-attribute syn_preserve	of sci_read_i			: signal is true;
-attribute syn_keep		of sci_read_i			: signal is true;
-attribute syn_preserve	of sci_write_i			: signal is true;
-attribute syn_keep		of sci_write_i			: signal is true;
-attribute syn_preserve	of sci_write_shift_i	: signal is true;
-attribute syn_keep		of sci_write_shift_i	: signal is true;
-attribute syn_preserve	of	sci_read_shift_i	: signal is true;
-attribute syn_keep		of sci_read_shift_i	: signal is true;
-
-begin
-
-
---SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
-
-clk_200_osc			<= OSC_CLK;			-- This external clock is oscillator/pll generated !!!
-clk_200_txdata		<= TX_DATACLK;		-- This external clock is the rx_full of the uplink !!!
-
-
-gen_clocks	: for i in 0 to 3 generate
-
-	rst(i)					<=		(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
-	rst_n(i)					<=		not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
-
-	RX_HALF_CLK_OUT(i)	<= rx_half_clk(i);
-	RX_FULL_CLK_OUT(i)	<= rx_full_clk(i);
-	TX_HALF_CLK_OUT(i)	<= tx_half_clk(i);
-	TX_FULL_CLK_OUT(i)	<= tx_full_clk(i);
-
---	gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate		-- NO WAY IN HELL !! this downlink is a master
---		clk_200_i(i)			<= rx_full_clk(i);
---	end generate;
-
---	gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
---	clk_200_i(i)		<= clk_200_txdata;
---	clk_200_rxdn(i)	<= rx_full_clk(i);	-- These clocks are the rx_full of the DOWNLINKs !!!
---	end generate;
-end generate;
-
--------------------------------------------------  
--- Serdes
-------------------------------------------------- 
-THE_SERDES : entity work.serdes_4_sync_downstream
-	port map(
-	--	CHANNEL0 --	
-		hdinp_ch0				=> SD_RXD_P_IN(0),
-		hdinn_ch0				=> SD_RXD_N_IN(0),
-		hdoutp_ch0				=> SD_TXD_P_OUT(0),
-		hdoutn_ch0				=> SD_TXD_N_OUT(0),
-		rxiclk_ch0				=> clk_200_txdata,	--clk_200_i(0),
-		sci_sel_ch0				=> sci_ch_i(0),
-		txiclk_ch0				=> clk_200_txdata,
-		rx_full_clk_ch0		=> rx_full_clk(0),
-		rx_half_clk_ch0		=> rx_half_clk(0),
-		tx_full_clk_ch0		=> tx_full_clk(0),
-		tx_half_clk_ch0		=> tx_half_clk(0),
-		fpga_rxrefclk_ch0		=> clk_200_osc,
-		txdata_ch0				=> tx_data(0),
-		tx_k_ch0					=> tx_k(0),
-		tx_force_disp_ch0		=> '0',
-		tx_disp_sel_ch0		=> '0',
-		rxdata_ch0				=> rx_data(0),
-		rx_k_ch0					=> rx_k(0),
-		rx_disp_err_ch0		=> open,
-		rx_cv_err_ch0			=> rx_error(0),
-		rx_serdes_rst_ch0_c  => rx_serdes_rst(0),
-		sb_felb_ch0_c			=> '0',
-		sb_felb_rst_ch0_c		=> '0',
-		tx_pcs_rst_ch0_c		=> tx_pcs_rst(0),
-		tx_pwrup_ch0_c			=> '1',
-		rx_pcs_rst_ch0_c		=> rx_pcs_rst(0),
-		rx_pwrup_ch0_c			=> '1',
-		rx_los_low_ch0_s		=> rx_los_low(0),
-		lsm_status_ch0_s		=> lsm_status(0),
-		rx_cdr_lol_ch0_s		=> rx_cdr_lol(0),
-		tx_div2_mode_ch0_c	=> '0',
-		rx_div2_mode_ch0_c	=> '0',
-	--	CHANNEL1 --	
-		hdinp_ch1				=> SD_RXD_P_IN(1),
-		hdinn_ch1				=> SD_RXD_N_IN(1),
-		hdoutp_ch1				=> SD_TXD_P_OUT(1),
-		hdoutn_ch1				=> SD_TXD_N_OUT(1),
-		rxiclk_ch1				=> clk_200_txdata,	--clk_200_i(1),
-		sci_sel_ch1				=> sci_ch_i(1),
-		txiclk_ch1				=> clk_200_txdata,
-		rx_full_clk_ch1		=> rx_full_clk(1),
-		rx_half_clk_ch1		=> rx_half_clk(1),
-		tx_full_clk_ch1		=> tx_full_clk(1),
-		tx_half_clk_ch1		=> tx_half_clk(1),
-		fpga_rxrefclk_ch1		=> clk_200_osc,
-		txdata_ch1				=> tx_data(1),
-		tx_k_ch1					=> tx_k(1),
-		tx_force_disp_ch1		=> '0',
-		tx_disp_sel_ch1		=> '0',
-		rxdata_ch1				=> rx_data(1),
-		rx_k_ch1					=> rx_k(1),
-		rx_disp_err_ch1		=> open,
-		rx_cv_err_ch1			=> rx_error(1),
-		rx_serdes_rst_ch1_c  => rx_serdes_rst(1),
-		sb_felb_ch1_c			=> '0',
-		sb_felb_rst_ch1_c		=> '0',
-		tx_pcs_rst_ch1_c		=> tx_pcs_rst(1),
-		tx_pwrup_ch1_c			=> '1',
-		rx_pcs_rst_ch1_c		=> rx_pcs_rst(1),
-		rx_pwrup_ch1_c			=> '1',
-		rx_los_low_ch1_s		=> rx_los_low(1),
-		lsm_status_ch1_s		=> lsm_status(1),
-		rx_cdr_lol_ch1_s		=> rx_cdr_lol(1),
-		tx_div2_mode_ch1_c	=> '0',
-		rx_div2_mode_ch1_c	=> '0',
-	--	CHANNEL2 --	
-		hdinp_ch2				=> SD_RXD_P_IN(2),
-		hdinn_ch2				=> SD_RXD_N_IN(2),
-		hdoutp_ch2				=> SD_TXD_P_OUT(2),
-		hdoutn_ch2				=> SD_TXD_N_OUT(2),
-		rxiclk_ch2				=> clk_200_txdata,	--clk_200_i(2),
-		sci_sel_ch2				=> sci_ch_i(2),
-		txiclk_ch2				=> clk_200_txdata,
-		rx_full_clk_ch2		=> rx_full_clk(2),
-		rx_half_clk_ch2		=> rx_half_clk(2),
-		tx_full_clk_ch2		=> tx_full_clk(2),
-		tx_half_clk_ch2		=> tx_half_clk(2),
-		fpga_rxrefclk_ch2		=> clk_200_osc,
-		txdata_ch2				=> tx_data(2),
-		tx_k_ch2					=> tx_k(2),
-		tx_force_disp_ch2		=> '0',
-		tx_disp_sel_ch2		=> '0',
-		rxdata_ch2				=> rx_data(2),
-		rx_k_ch2					=> rx_k(2),
-		rx_disp_err_ch2		=> open,
-		rx_cv_err_ch2			=> rx_error(2),
-		rx_serdes_rst_ch2_c  => rx_serdes_rst(2),
-		sb_felb_ch2_c			=> '0',
-		sb_felb_rst_ch2_c		=> '0',
-		tx_pcs_rst_ch2_c		=> tx_pcs_rst(2),
-		tx_pwrup_ch2_c			=> '1',
-		rx_pcs_rst_ch2_c		=> rx_pcs_rst(2),
-		rx_pwrup_ch2_c			=> '1',
-		rx_los_low_ch2_s		=> rx_los_low(2),
-		lsm_status_ch2_s		=> lsm_status(2),
-		rx_cdr_lol_ch2_s		=> rx_cdr_lol(2),
-		tx_div2_mode_ch2_c	=> '0',
-		rx_div2_mode_ch2_c	=> '0',
-	--	CHANNEL3 --	
-		hdinp_ch3				=> SD_RXD_P_IN(3),
-		hdinn_ch3				=> SD_RXD_N_IN(3),
-		hdoutp_ch3				=> SD_TXD_P_OUT(3),
-		hdoutn_ch3				=> SD_TXD_N_OUT(3),
-		rxiclk_ch3				=> clk_200_txdata,	--clk_200_i(3),
-		sci_sel_ch3				=> sci_ch_i(3),
-		txiclk_ch3				=> clk_200_txdata,
-		rx_full_clk_ch3		=> rx_full_clk(3),
-		rx_half_clk_ch3		=> rx_half_clk(3),
-		tx_full_clk_ch3		=> tx_full_clk(3),
-		tx_half_clk_ch3		=> tx_half_clk(3),
-		fpga_rxrefclk_ch3		=> clk_200_osc,
-		txdata_ch3				=> tx_data(3),
-		tx_k_ch3					=> tx_k(3),
-		tx_force_disp_ch3		=> '0',
-		tx_disp_sel_ch3		=> '0',
-		rxdata_ch3				=> rx_data(3),
-		rx_k_ch3					=> rx_k(3),
-		rx_disp_err_ch3		=> open,
-		rx_cv_err_ch3			=> rx_error(3),
-		rx_serdes_rst_ch3_c  => rx_serdes_rst(3),
-		sb_felb_ch3_c			=> '0',
-		sb_felb_rst_ch3_c		=> '0',
-		tx_pcs_rst_ch3_c		=> tx_pcs_rst(3),
-		tx_pwrup_ch3_c			=> '1',
-		rx_pcs_rst_ch3_c		=> rx_pcs_rst(3),
-		rx_pwrup_ch3_c			=> '1',
-		rx_los_low_ch3_s		=> rx_los_low(3),
-		lsm_status_ch3_s		=> lsm_status(3),
-		rx_cdr_lol_ch3_s		=> rx_cdr_lol(3),
-		tx_div2_mode_ch3_c	=> '0',
-		rx_div2_mode_ch3_c	=> '0',
-	--	COMMON --	
-		sci_wrdata				=> sci_data_in_i,
-		sci_rddata				=> sci_data_out_i,
-		sci_addr					=> sci_addr_i(5 downto 0),
-		sci_sel_quad			=> sci_qd_i,
-		sci_rd					=> sci_read_i,
-		sci_wrn					=> sci_write_i,
-
-		fpga_txrefclk			=> clk_200_txdata,
-		tx_serdes_rst_c		=> '0',	--tx_serdes_rst(0),	-- resets tx_pll	PL 1906
-		tx_pll_lol_qd_s		=> tx_pll_lol_quad,
-		tx_sync_qd_c			=> '0',			-- unused; signal to synchronise channels/serdesses for multi-channel protocols
-		rst_qd_c					=> rst_down_quad,
-		serdes_rst_qd_c		=> serdes_rst_down_quad
-	);
-
--------------------------
--- combined quad reset --
--------------------------
---rst_down_quad				<= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
-rst_down_quad				<= RESET;	-- PL: 18/06/14
---serdes_rst_down_quad		<= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0';
-serdes_rst_down_quad		<= '0';		-- PL: 23/06/14
-
-generated_logic	: for i in 0 to 3 generate
-
-	SD_TXDIS_OUT(i)			<= LINK_DISABLE_IN;	--not (rx_allow_q(i) or not IS_SLAVE);   --slave only switches on when RX is ready
-
-	tx_pll_lol(i)			<= tx_pll_lol_quad;
-	
-	------------------------------------------------- 
-	-- Reset FSM & Link states
-	------------------------------------------------- 
-	THE_RX_FSM : rx_reset_fsm
-	port map(
-		RST_N						=> rst_n(i),
-		RX_REFCLK				=> rx_full_clk(i),	
-		TX_PLL_LOL_QD_S		=> tx_pll_lol(i),
-		RX_SERDES_RST_CH_C	=> rx_serdes_rst(i),
-		RX_CDR_LOL_CH_S		=> rx_cdr_lol(i),
-		RX_LOS_LOW_CH_S		=> rx_los_low(i),
-		RX_PCS_RST_CH_C		=> rx_pcs_rst(i),
-		WA_POSITION				=> wa_position_rx(i),
-		STATE_OUT				=> rx_fsm_state(i)
-	);
-
-	THE_TX_FSM : tx_reset_fsm
-	port map(
-		RST_N						=> rst_n(i),
-		TX_REFCLK				=> clk_200_txdata,
-		TX_PLL_LOL_QD_S		=> tx_pll_lol(i),
-		RST_QD_C					=> rst_qd(i),
-		TX_PCS_RST_CH_C		=> tx_pcs_rst(i),
-		STATE_OUT				=> tx_fsm_state(i)
-	);
-	
-
-	-- Master does not do bit-locking    
-	wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0";
-
-	
-	PROC_ALLOW : process(clk_200_txdata)	--clk_200_i(i))
-	begin
-		if rising_edge(clk_200_txdata) then	-- clk_200_txdata ??
-			if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
-				rx_allow(i) <= '1';
-				tx_allow(i) <= '1';
-			else
-				rx_allow(i) <= '0';
-				tx_allow(i) <= '1';
-			end if;
-		end if;
-	end process;
-
-	rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK);
-	tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
-
-
-	PROC_START_TIMER : process(clk_200_txdata)	--clk_200_i(i))
-	begin
-		if rising_edge(clk_200_txdata) then
-			if got_link_ready_i(i) = '1' then
-				watchdog_timer(i)	<= (others => '0');
-					if start_timer(i)(start_timer'left) = '0' then
-						start_timer(i) <= start_timer(i) + 1;
---						start_timer(i)(start_timer'left downto 0) <= start_timer(i)(start_timer'left downto 0) + 1;
-					end if;  
-			else
-				start_timer(i) <= (others => '0');
-				if ((watchdog_timer(i)(watchdog_timer(i)'left) = '1') and (watchdog_timer(i)(watchdog_timer(i)'left - 1) = '1')) then
-					watchdog_trigger(i)	<= '1';
-				else 
-					watchdog_trigger(i)	<= '0';
-				end if;
-				if watchdog_trigger(i) = '0' then
-					watchdog_timer(i)		<= watchdog_timer(i) + 1;
-				else 
-					watchdog_timer(i)		<= (others => '0');
-				end if;
-			end if;
-		end if;
-	end process;
-	------------------------------------------------- 
-	-- TX Data
-	-------------------------------------------------         
-	THE_TX : soda_tx_control
-	port map(
-		CLK_200						=> clk_200_txdata,	--tx_full_clk(i),	--clk_200_i(i),
-		CLK_100						=> SYSCLK,
-		RESET_IN						=> rst(i),		--CLEAR, PL!
-
-		TX_DATA_IN					=> MED_DATA_IN(i),
-		TX_PACKET_NUMBER_IN		=> MED_PACKET_NUM_IN(i),
-		TX_WRITE_IN					=> MED_DATAREADY_IN(i),
-		TX_READ_OUT					=> MED_READ_OUT(i),
-
-		TX_DATA_OUT					=> tx_data(i),
-		TX_K_OUT						=> tx_k(i),
-
-		REQUEST_RETRANSMIT_IN	=> request_retr_i(i),             --TODO
-		REQUEST_POSITION_IN		=> request_retr_position_i(i),    --TODO
-
-		START_RETRANSMIT_IN		=> start_retr_i(i),               --TODO
-		START_POSITION_IN			=> request_retr_position_i(i),    --TODO
-
-		TX_DLM_PREVIEW_IN			=>	TX_DLM_PREVIEW_IN(i),
-		SEND_DLM						=> TX_DLM(i),
-		SEND_DLM_WORD				=> TX_DLM_WORD(i),
-
-		SEND_LINK_RESET_IN		=> CTRL_OP(i*16 + 15),	--CTRL_OP(i)(15),
-		TX_ALLOW_IN					=> tx_allow(i),
-		RX_ALLOW_IN					=> rx_allow(i),
-		LINK_PHASE_OUT				=>	link_phase_S(i),		--PL!
-
-		DEBUG_OUT					=> debug_tx_control_i(i),
-		STAT_REG_OUT				=> stat_tx_control_i(i)
-	);  
-
-	LINK_PHASE_OUT(i)		<= link_phase_S(i);		--PL!
-	-------------------------------------------------      
-	-- RX Data
-	-------------------------------------------------             
-	THE_RX_CONTROL : rx_control
-	port map(
-		CLK_200                        => clk_200_txdata,	--clk_200_i(i), --PL!
-		CLK_100                        => SYSCLK,
-		RESET_IN                       => rst(i),		--CLEAR, PL!
-
-		RX_DATA_OUT                    => MED_DATA_OUT(i),
-		RX_PACKET_NUMBER_OUT           => MED_PACKET_NUM_OUT(i),
-		RX_WRITE_OUT                   => MED_DATAREADY_OUT(i),
-		RX_READ_IN                     => MED_READ_IN(i),
-
-		RX_DATA_IN                     => rx_data(i),
-		RX_K_IN                        => rx_k(i),
-
-		REQUEST_RETRANSMIT_OUT         => request_retr_i(i),
-		REQUEST_POSITION_OUT           => request_retr_position_i(i),
-
-		START_RETRANSMIT_OUT           => start_retr_i(i),
-		START_POSITION_OUT             => start_retr_position_i(i),
-
-		--send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
-		RX_DLM                         => RX_DLM(i),
-		RX_DLM_WORD                    => RX_DLM_WORD(i),
-
-		SEND_LINK_RESET_OUT            => send_link_reset_i(i),
-		MAKE_RESET_OUT                 => make_link_reset_i(i),
-		RX_ALLOW_IN                    => rx_allow(i),
-		GOT_LINK_READY                 => got_link_ready_i(i),
-
-		DEBUG_OUT                      => debug_rx_control_i(i),
-		STAT_REG_OUT                   => stat_rx_control_i(i)
-	);   
-
-	internal_make_link_reset_out(i)	<= make_link_reset_i(i)	when (IS_SYNC_SLAVE=c_YES) else '0';
-	sd_los_i(i)								<= SD_LOS_IN(i)			when rising_edge(clk_200_txdata);
-
-end generate;    
-    
--------------------------------------------------      
--- SCI
--------------------------------------------------      
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process 
-variable cnt : integer range 0 to 4 := 0;
-begin
-wait until rising_edge(SYSCLK);
-	SCI_ACK <= '0';
-	case sci_state is
-	when IDLE =>
-		sci_ch_i        <= x"0";
-		sci_qd_i        <= '0';
-		sci_reg_i       <= '0';
-		sci_read_i      <= '0';
-		sci_write_i     <= '0';
-		sci_timer(0)    <= sci_timer(0) + 1;
-		sci_timer(1)    <= sci_timer(1) + 1;
-		sci_timer(2)    <= sci_timer(2) + 1;
-		sci_timer(3)    <= sci_timer(3) + 1;
-		if SCI_READ = '1' or SCI_WRITE = '1' then
-			sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_addr_i    <= SCI_ADDR;
-			sci_data_in_i <= SCI_DATA_IN;
-			sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_state     <= SCTRL;
-		else
-			if sci_timer(0)(sci_timer'left) = '1' then
-				sci_timer(0)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(1)(sci_timer'left) = '1' then
-				sci_timer(1)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(2)(sci_timer'left) = '1' then
-				sci_timer(2)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(3)(sci_timer'left) = '1' then
-				sci_timer(3)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-		end if;      
-when SCTRL =>
-	if sci_reg_i = '1' then
-		SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-		SCI_ACK       <= '1';
-		sci_write_i   <= '0';
-		sci_read_i    <= '0';
-		sci_state     <= IDLE;
-	else
-		sci_state     <= SCTRL_WAIT;
-	end if;
-when SCTRL_WAIT   =>
-	sci_state       <= SCTRL_WAIT2;
-when SCTRL_WAIT2  =>
-	sci_state       <= SCTRL_FINISH;
-when SCTRL_FINISH =>
-	SCI_DATA_OUT    <= sci_data_out_i;
-	SCI_ACK         <= '1';
-	sci_write_i     <= '0';
-	sci_read_i      <= '0';
-	sci_state       <= IDLE;
-
-when GET_WA =>
-	if cnt = 4 then
-		cnt           := 0;
-		sci_state     <= IDLE;
-	else
-		sci_state     <= GET_WA_WAIT;
-		sci_addr_i    <= '0' & x"22";
-		sci_ch_i      <= x"0";
-		sci_ch_i(cnt) <= '1';
-		sci_read_i    <= '1';
-	end if;
-when GET_WA_WAIT  =>
-	sci_state       <= GET_WA_WAIT2;
-when GET_WA_WAIT2 =>
-	sci_state       <= GET_WA_FINISH;
-when GET_WA_FINISH =>
---		wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-	wa_position(cnt) <= sci_data_out_i(3 downto 0);
-	sci_state       <= GET_WA;    
-	cnt             := cnt + 1;
-end case;
-
-if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-	SCI_NACK <= '1';
-else
-	SCI_NACK <= '0';
-end if;
-
-end process;
-
-
-
-			
-	STAT_DEBUG <= (others => '0');	--debug_reg;
-
-	generated_status	: for i in 0 to 3 generate
-		STAT_OP(i*16 + 15)		<= send_link_reset_i(i) when rising_edge(SYSCLK);
-		STAT_OP(i*16 + 14)		<= '0';
-		STAT_OP(i*16 + 13)		<= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset
-		STAT_OP(i*16 + 12)		<= '0';
-		STAT_OP(i*16 + 11)		<= '0';
-		STAT_OP(i*16 + 10)		<= rx_allow(i);
-		STAT_OP(i*16 + 9) 		<= tx_allow(i);
-		STAT_OP(i*16 + 8)		<= got_link_ready_i(i)  when rising_edge(rx_half_clk(i));
-		STAT_OP(i*16 + 7)		<= send_link_reset_i(i);
-		STAT_OP(i*16 + 6)		<= make_link_reset_i(i);
-		STAT_OP(i*16 + 5)		<= request_retr_i(i);
-		STAT_OP(i*16 + 4)		<= start_retr_i(i);
-		STAT_OP(i*16 + 3 downto i*16) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";
-	end generate;
-
-end med_ecp3_sfp_4_sync_down_arch;
diff --git a/code/med_ecp3_sfp_4_sync_down_EP.vhd b/code/med_ecp3_sfp_4_sync_down_EP.vhd
deleted file mode 100644
index 68f803d..0000000
--- a/code/med_ecp3_sfp_4_sync_down_EP.vhd
+++ /dev/null
@@ -1,651 +0,0 @@
---4 channel Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity med_ecp3_sfp_4_sync_down_EP is
-	generic(	SERDES_NUM : integer range 0 to 3 := 0;
-				IS_SYNC_SLAVE   : integer := c_NO);   -- hub downlink is NO slave
-	port(
-		OSC_CLK					: in  std_logic; -- 200 MHz reference clock
-		TX_DATACLK				: in  std_logic; -- 200 MHz data clock
-		SYSCLK					: in  std_logic; -- 100 MHz main clock net, synchronous to OSC clock
-		RESET						: in  std_logic; -- synchronous reset
-		CLEAR						: in  std_logic; -- asynchronous reset
-		---------------------------------------------------------------------------------------------------------------------------------------------------------
-		LINK_DISABLE_IN		: in  std_logic;	-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
-		---------------------------------------------------------------------------------------------------------------------------------------------------------
-		RX_HALF_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --100 MHz
-		RX_FULL_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --200 MHz
-		TX_HALF_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --100 MHz
-		TX_FULL_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --200 MHz
-
-		--Sync operation
-		RX_DLM					: out	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');
-		RX_DLM_WORD				: out	t_HUB_BYTE;	--std_logic_vector(4*8 - 1 downto 0)	:= (others => '0');
-		TX_DLM					: in	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');
-		TX_DLM_WORD				: in	t_HUB_BYTE;	--std_logic_vector(4*8 - 1 downto 0)	:= (others => '0');
-		TX_DLM_PREVIEW_IN		: in	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');	--PL!
-		LINK_PHASE_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');	--PL!
-
-		--SFP Connection 
-		SD_RXD_P_IN				: in	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_RXD_N_IN				: in	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_TXD_P_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_TXD_N_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_REFCLK_P_IN			: in	t_HUB_BIT;	--std_logic;  --not used
-		SD_REFCLK_N_IN			: in	t_HUB_BIT;	--std_logic;  --not used
-		SD_PRSNT_N_IN			: in	t_HUB_BIT;	--std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		SD_LOS_IN				: in	t_HUB_BIT;	--std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		SD_TXDIS_OUT			: out	t_HUB_BIT;	--std_logic := '0'; -- SFP disable
-		--Control Interface
-		SCI_DATA_IN				: in  std_logic_vector(7 downto 0) := (others => '0');
-		SCI_DATA_OUT			: out std_logic_vector(7 downto 0) := (others => '0');
-		SCI_ADDR					: in  std_logic_vector(8 downto 0) := (others => '0');
-		SCI_READ					: in  std_logic := '0';
-		SCI_WRITE				: in  std_logic := '0';
-		SCI_ACK					: out std_logic := '0';
-		SCI_NACK					: out std_logic := '0';
-		-- Status and control port
---		STAT_OP					: out	t_HUB_WORD;	--std_logic_vector (15 downto 0);
---		CTRL_OP					: in	t_HUB_WORD;	--std_logic_vector (15 downto 0) := (others => '0');
-		STAT_DEBUG				: out std_logic_vector (63 downto 0);
-		CTRL_DEBUG				: in  std_logic_vector (63 downto 0) := (others => '0')
-	);
-end entity;
-
-
-architecture med_ecp3_sfp_4_sync_down_EP_arch of med_ecp3_sfp_4_sync_down_EP is
-
-  -- Placer Directives
-  attribute HGROUP : string;
-  -- for whole architecture
-  attribute HGROUP of med_ecp3_sfp_4_sync_down_EP_arch : architecture  is "media_downlink_group";
-  attribute syn_sharing : string;
-  attribute syn_sharing of med_ecp3_sfp_4_sync_down_EP_arch : architecture is "off";
-
-
-
-signal clk_200_osc						: std_logic;
-signal clk_200_txdata					: std_logic;
---signal clk_200_rxdn						: std_logic_vector(3 downto 0);
---signal clk_200_i							: std_logic_vector(3 downto 0);
-signal rx_full_clk						: std_logic_vector(3 downto 0);
-signal rx_half_clk						: std_logic_vector(3 downto 0);	
-signal tx_full_clk						: std_logic_vector(3 downto 0);
-signal tx_half_clk						: std_logic_vector(3 downto 0);
-
-signal tx_data								: t_HUB_BYTE;	--std_logic_vector(4*8-1 downto 0);
-signal tx_k									: std_logic_vector(3 downto 0);
-signal rx_data								: t_HUB_BYTE;	--std_logic_vector(4*8-1 downto 0);
-signal rx_k									: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_error							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-
-signal rst_n								: t_HUB_BIT;
-signal rst									: t_HUB_BIT;		-- PL!
-signal rx_serdes_rst						: t_HUB_BIT;
-signal tx_serdes_rst						: std_logic	:= '0'; 
-signal tx_pcs_rst							: t_HUB_BIT; 
-signal rx_pcs_rst							: t_HUB_BIT; 
-signal rst_qd								: t_HUB_BIT; 
-signal rst_down_quad						: std_logic; 
---signal serdes_rst_qd						: t_HUB_BIT; 
-signal serdes_rst_down_quad			: std_logic;  	-- combined serdes reset for whole quad
-signal sd_los_i							: t_HUB_BIT; 	--PL!
-
-signal rx_los_low							: t_HUB_BIT; 
-signal lsm_status							: t_HUB_BIT; 
-signal rx_cdr_lol							: t_HUB_BIT; 
-signal tx_pll_lol							: t_HUB_BIT; 
-signal tx_pll_lol_quad					: std_logic; 	-- combined Loss-Of-Lock for whole quad
-
-signal sci_ch_i							: std_logic_vector(3 downto 0);
-signal sci_qd_i							: std_logic;
-signal sci_reg_i							: std_logic;
-signal sci_addr_i							: std_logic_vector(8 downto 0);
-signal sci_data_in_i						: std_logic_vector(7 downto 0);
-signal sci_data_out_i					: std_logic_vector(7 downto 0);
-signal sci_read_i							: std_logic;
-signal sci_write_i						: std_logic;
---signal sci_write_shift_i				: std_logic_vector(2 downto 0);
---signal sci_read_shift_i					: std_logic_vector(2 downto 0);
-
-signal wa_position						: t_HUB_NIBL	:= (others => (others => '1'));	--std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx					: t_HUB_NIBL	:= (others => (others => '1'));	--std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_allow							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal tx_allow_q							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_allow_q							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal link_phase_S						: t_HUB_BIT;	--std_logic_vector(3 downto 0);	--PL!
-signal request_retr_i					: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal start_retr_i						: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal request_retr_position_i		: t_HUB_BYTE;	--std_logic_vector(7 downto 0);
-signal start_retr_position_i			: t_HUB_BYTE;	--std_logic_vector(7 downto 0);
-signal send_link_reset_i				: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal make_link_reset_i				: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal got_link_ready_i					: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal internal_make_link_reset_out	: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-
-signal start_timer						: t_HUB_TIMER19	:= (others => (others => '0'));	--unsigned(18 downto 0)				:= (others => '0');
-signal watchdog_timer					: t_HUB_TIMER21	:= (others => (others => '0'));	--unsigned(20 downto 0)				:= (others => '0');
-signal watchdog_trigger					: t_HUB_BIT			:= (others => '0');					--std_logic_vector(3 downto 0)	:= (others => '0');
-
-signal rx_fsm_state						: t_HUB_NIBL;	--std_logic_vector(3 downto 0);
-signal tx_fsm_state						: t_HUB_NIBL;	--std_logic_vector(3 downto 0);
-
-signal stat_rx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal stat_tx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_rx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_tx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_reg							: std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state							: sci_ctrl;
-signal sci_timer							: t_HUB_TIMER13	:= (others => (others => '0'));	--unsigned(12 downto 0)				:= (others => '0');
-
-begin
-
-
---SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
-
-clk_200_osc			<= OSC_CLK;			-- This external clock is oscillator/pll generated !!!
-clk_200_txdata		<= TX_DATACLK;		-- This external clock is the rx_full of the uplink !!!
-
-
-gen_clocks	: for i in 0 to 3 generate
-
-	rst(i)					<=		(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
-	rst_n(i)					<=		not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i) or watchdog_trigger(i));
-
-	RX_HALF_CLK_OUT(i)	<= rx_half_clk(i);
-	RX_FULL_CLK_OUT(i)	<= rx_full_clk(i);
-	TX_HALF_CLK_OUT(i)	<= tx_half_clk(i);
-	TX_FULL_CLK_OUT(i)	<= tx_full_clk(i);
-
---	gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate		-- NO WAY IN HELL !! this downlink is a master
---		clk_200_i(i)			<= rx_full_clk(i);
---	end generate;
-
---	gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
---	clk_200_i(i)		<= clk_200_txdata;
---	clk_200_rxdn(i)	<= rx_full_clk(i);	-- These clocks are the rx_full of the DOWNLINKs !!!
---	end generate;
-end generate;
-
--------------------------------------------------  
--- Serdes
-------------------------------------------------- 
-THE_SERDES : entity work.serdes_4_sync_downstream
-	port map(
-	--	CHANNEL0 --	
-		hdinp_ch0				=> SD_RXD_P_IN(0),
-		hdinn_ch0				=> SD_RXD_N_IN(0),
-		hdoutp_ch0				=> SD_TXD_P_OUT(0),
-		hdoutn_ch0				=> SD_TXD_N_OUT(0),
-		rxiclk_ch0				=> clk_200_txdata,	--clk_200_i(0),
-		sci_sel_ch0				=> sci_ch_i(0),
-		txiclk_ch0				=> clk_200_txdata,
-		rx_full_clk_ch0		=> rx_full_clk(0),
-		rx_half_clk_ch0		=> rx_half_clk(0),
-		tx_full_clk_ch0		=> tx_full_clk(0),
-		tx_half_clk_ch0		=> tx_half_clk(0),
-		fpga_rxrefclk_ch0		=> clk_200_osc,
-		txdata_ch0				=> tx_data(0),
-		tx_k_ch0					=> tx_k(0),
-		tx_force_disp_ch0		=> '0',
-		tx_disp_sel_ch0		=> '0',
-		rxdata_ch0				=> rx_data(0),
-		rx_k_ch0					=> rx_k(0),
-		rx_disp_err_ch0		=> open,
-		rx_cv_err_ch0			=> rx_error(0),
-		rx_serdes_rst_ch0_c  => rx_serdes_rst(0),
-		sb_felb_ch0_c			=> '0',
-		sb_felb_rst_ch0_c		=> '0',
-		tx_pcs_rst_ch0_c		=> tx_pcs_rst(0),
-		tx_pwrup_ch0_c			=> '1',
-		rx_pcs_rst_ch0_c		=> rx_pcs_rst(0),
-		rx_pwrup_ch0_c			=> '1',
-		rx_los_low_ch0_s		=> rx_los_low(0),
-		lsm_status_ch0_s		=> lsm_status(0),
-		rx_cdr_lol_ch0_s		=> rx_cdr_lol(0),
-		tx_div2_mode_ch0_c	=> '0',
-		rx_div2_mode_ch0_c	=> '0',
-	--	CHANNEL1 --	
-		hdinp_ch1				=> SD_RXD_P_IN(1),
-		hdinn_ch1				=> SD_RXD_N_IN(1),
-		hdoutp_ch1				=> SD_TXD_P_OUT(1),
-		hdoutn_ch1				=> SD_TXD_N_OUT(1),
-		rxiclk_ch1				=> clk_200_txdata,	--clk_200_i(1),
-		sci_sel_ch1				=> sci_ch_i(1),
-		txiclk_ch1				=> clk_200_txdata,
-		rx_full_clk_ch1		=> rx_full_clk(1),
-		rx_half_clk_ch1		=> rx_half_clk(1),
-		tx_full_clk_ch1		=> tx_full_clk(1),
-		tx_half_clk_ch1		=> tx_half_clk(1),
-		fpga_rxrefclk_ch1		=> clk_200_osc,
-		txdata_ch1				=> tx_data(1),
-		tx_k_ch1					=> tx_k(1),
-		tx_force_disp_ch1		=> '0',
-		tx_disp_sel_ch1		=> '0',
-		rxdata_ch1				=> rx_data(1),
-		rx_k_ch1					=> rx_k(1),
-		rx_disp_err_ch1		=> open,
-		rx_cv_err_ch1			=> rx_error(1),
-		rx_serdes_rst_ch1_c  => rx_serdes_rst(1),
-		sb_felb_ch1_c			=> '0',
-		sb_felb_rst_ch1_c		=> '0',
-		tx_pcs_rst_ch1_c		=> tx_pcs_rst(1),
-		tx_pwrup_ch1_c			=> '1',
-		rx_pcs_rst_ch1_c		=> rx_pcs_rst(1),
-		rx_pwrup_ch1_c			=> '1',
-		rx_los_low_ch1_s		=> rx_los_low(1),
-		lsm_status_ch1_s		=> lsm_status(1),
-		rx_cdr_lol_ch1_s		=> rx_cdr_lol(1),
-		tx_div2_mode_ch1_c	=> '0',
-		rx_div2_mode_ch1_c	=> '0',
-	--	CHANNEL2 --	
-		hdinp_ch2				=> SD_RXD_P_IN(2),
-		hdinn_ch2				=> SD_RXD_N_IN(2),
-		hdoutp_ch2				=> SD_TXD_P_OUT(2),
-		hdoutn_ch2				=> SD_TXD_N_OUT(2),
-		rxiclk_ch2				=> clk_200_txdata,	--clk_200_i(2),
-		sci_sel_ch2				=> sci_ch_i(2),
-		txiclk_ch2				=> clk_200_txdata,
-		rx_full_clk_ch2		=> rx_full_clk(2),
-		rx_half_clk_ch2		=> rx_half_clk(2),
-		tx_full_clk_ch2		=> tx_full_clk(2),
-		tx_half_clk_ch2		=> tx_half_clk(2),
-		fpga_rxrefclk_ch2		=> clk_200_osc,
-		txdata_ch2				=> tx_data(2),
-		tx_k_ch2					=> tx_k(2),
-		tx_force_disp_ch2		=> '0',
-		tx_disp_sel_ch2		=> '0',
-		rxdata_ch2				=> rx_data(2),
-		rx_k_ch2					=> rx_k(2),
-		rx_disp_err_ch2		=> open,
-		rx_cv_err_ch2			=> rx_error(2),
-		rx_serdes_rst_ch2_c  => rx_serdes_rst(2),
-		sb_felb_ch2_c			=> '0',
-		sb_felb_rst_ch2_c		=> '0',
-		tx_pcs_rst_ch2_c		=> tx_pcs_rst(2),
-		tx_pwrup_ch2_c			=> '1',
-		rx_pcs_rst_ch2_c		=> rx_pcs_rst(2),
-		rx_pwrup_ch2_c			=> '1',
-		rx_los_low_ch2_s		=> rx_los_low(2),
-		lsm_status_ch2_s		=> lsm_status(2),
-		rx_cdr_lol_ch2_s		=> rx_cdr_lol(2),
-		tx_div2_mode_ch2_c	=> '0',
-		rx_div2_mode_ch2_c	=> '0',
-	--	CHANNEL3 --	
-		hdinp_ch3				=> SD_RXD_P_IN(3),
-		hdinn_ch3				=> SD_RXD_N_IN(3),
-		hdoutp_ch3				=> SD_TXD_P_OUT(3),
-		hdoutn_ch3				=> SD_TXD_N_OUT(3),
-		rxiclk_ch3				=> clk_200_txdata,	--clk_200_i(3),
-		sci_sel_ch3				=> sci_ch_i(3),
-		txiclk_ch3				=> clk_200_txdata,
-		rx_full_clk_ch3		=> rx_full_clk(3),
-		rx_half_clk_ch3		=> rx_half_clk(3),
-		tx_full_clk_ch3		=> tx_full_clk(3),
-		tx_half_clk_ch3		=> tx_half_clk(3),
-		fpga_rxrefclk_ch3		=> clk_200_osc,
-		txdata_ch3				=> tx_data(3),
-		tx_k_ch3					=> tx_k(3),
-		tx_force_disp_ch3		=> '0',
-		tx_disp_sel_ch3		=> '0',
-		rxdata_ch3				=> rx_data(3),
-		rx_k_ch3					=> rx_k(3),
-		rx_disp_err_ch3		=> open,
-		rx_cv_err_ch3			=> rx_error(3),
-		rx_serdes_rst_ch3_c  => rx_serdes_rst(3),
-		sb_felb_ch3_c			=> '0',
-		sb_felb_rst_ch3_c		=> '0',
-		tx_pcs_rst_ch3_c		=> tx_pcs_rst(3),
-		tx_pwrup_ch3_c			=> '1',
-		rx_pcs_rst_ch3_c		=> rx_pcs_rst(3),
-		rx_pwrup_ch3_c			=> '1',
-		rx_los_low_ch3_s		=> rx_los_low(3),
-		lsm_status_ch3_s		=> lsm_status(3),
-		rx_cdr_lol_ch3_s		=> rx_cdr_lol(3),
-		tx_div2_mode_ch3_c	=> '0',
-		rx_div2_mode_ch3_c	=> '0',
-	--	COMMON --	
-		sci_wrdata				=> sci_data_in_i,
-		sci_rddata				=> sci_data_out_i,
-		sci_addr					=> sci_addr_i(5 downto 0),
-		sci_sel_quad			=> sci_qd_i,
-		sci_rd					=> sci_read_i,
-		sci_wrn					=> sci_write_i,
-
-		fpga_txrefclk			=> clk_200_txdata,	--clk_200_osc,	--clk_200_i(0),
-		tx_serdes_rst_c		=> '0',	--tx_serdes_rst(0),	-- resets tx_pll	PL 1906
-		tx_pll_lol_qd_s		=> tx_pll_lol_quad,
-		tx_sync_qd_c			=> '0',			-- unused; signal to synchronise channels/serdesses for multi-channel protocols
-		rst_qd_c					=> rst_down_quad,				-- jemig wat is Oscar toch gasfjkl[glk
-		serdes_rst_qd_c		=> serdes_rst_down_quad
-	);
-
--------------------------
--- combined quad reset --
--------------------------
---rst_down_quad				<= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
-rst_down_quad				<= RESET;	-- PL: 18/06/14
---serdes_rst_down_quad		<= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0';
-serdes_rst_down_quad		<= '0';		-- PL: 23/06/14
-
-generated_logic	: for i in 0 to 3 generate
-
-	SD_TXDIS_OUT(i)			<= LINK_DISABLE_IN;	--not (rx_allow_q(i) or not IS_SLAVE);   --slave only switches on when RX is ready
-
-	tx_pll_lol(i)			<= tx_pll_lol_quad;
-	
-	------------------------------------------------- 
-	-- Reset FSM & Link states
-	------------------------------------------------- 
-	THE_RX_FSM : rx_reset_fsm
-	port map(
-		RST_N						=> rst_n(i),
-		RX_REFCLK				=> rx_full_clk(i),	--clk_200_osc,	-- want de rx_refclk is clk_200_osc !!! en moet er altijd zijn
-		TX_PLL_LOL_QD_S		=> tx_pll_lol(i),
-		RX_SERDES_RST_CH_C	=> rx_serdes_rst(i),
-		RX_CDR_LOL_CH_S		=> rx_cdr_lol(i),
-		RX_LOS_LOW_CH_S		=> rx_los_low(i),
-		RX_PCS_RST_CH_C		=> rx_pcs_rst(i),
-		WA_POSITION				=> wa_position_rx(i),
-		STATE_OUT				=> rx_fsm_state(i)
-	);
-
-	THE_TX_FSM : tx_reset_fsm
-	port map(
-		RST_N						=> rst_n(i),
-		TX_REFCLK				=> clk_200_txdata,	--clk_200_osc,
-		TX_PLL_LOL_QD_S		=> tx_pll_lol(i),
-		RST_QD_C					=> rst_qd(i),
-		TX_PCS_RST_CH_C		=> tx_pcs_rst(i),
-		STATE_OUT				=> tx_fsm_state(i)
-	);
-	
-
-	-- Master does not do bit-locking    
-	wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0";
-
-	
-	PROC_ALLOW : process(clk_200_txdata)	--clk_200_i(i))
-	begin
-		if rising_edge(clk_200_txdata) then	-- clk_200_txdata ??
-			if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
-				rx_allow(i) <= '1';
-				tx_allow(i) <= '1';
-			else
-				rx_allow(i) <= '0';
-				tx_allow(i) <= '1';
-			end if;
-		end if;
-	end process;
-
-	rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK);
-	tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
-
-
-	PROC_START_TIMER : process(clk_200_txdata)	--clk_200_i(i))
-	begin
-		if rising_edge(clk_200_txdata) then
-			if got_link_ready_i(i) = '1' then
-				watchdog_timer(i)	<= (others => '0');
-					if start_timer(i)(start_timer'left) = '0' then
-						start_timer(i) <= start_timer(i) + 1;
---						start_timer(i)(start_timer'left downto 0) <= start_timer(i)(start_timer'left downto 0) + 1;
-					end if;  
-			else
-				start_timer(i) <= (others => '0');
-				if ((watchdog_timer(i)(watchdog_timer(i)'left) = '1') and (watchdog_timer(i)(watchdog_timer(i)'left - 1) = '1')) then
-					watchdog_trigger(i)	<= '1';
-				else 
-					watchdog_trigger(i)	<= '0';
-				end if;
-				if watchdog_trigger(i) = '0' then
-					watchdog_timer(i)		<= watchdog_timer(i) + 1;
-				else 
-					watchdog_timer(i)		<= (others => '0');
-				end if;
-			end if;
-		end if;
-	end process;
-	------------------------------------------------- 
-	-- TX Data
-	-------------------------------------------------         
-	THE_TX : soda_tx_control
-	port map(
-		CLK_200						=> clk_200_txdata,	--tx_full_clk(i),	--clk_200_i(i),
-		CLK_100						=> SYSCLK,
-		RESET_IN						=> rst(i),		--CLEAR, PL!
-
-		TX_DATA_IN					=> (others => '0'),	--	MED_DATA_IN(i),
-		TX_PACKET_NUMBER_IN		=> (others => '0'),	--	MED_PACKET_NUM_IN(i),
-		TX_WRITE_IN					=> '0',					--	MED_DATAREADY_IN(i),
-		TX_READ_OUT					=> open,					--	MED_READ_OUT(i),
-
-		TX_DATA_OUT					=> tx_data(i),
-		TX_K_OUT						=> tx_k(i),
-
-		REQUEST_RETRANSMIT_IN	=> request_retr_i(i),             --TODO
-		REQUEST_POSITION_IN		=> request_retr_position_i(i),    --TODO
-
-		START_RETRANSMIT_IN		=> start_retr_i(i),               --TODO
-		START_POSITION_IN			=> request_retr_position_i(i),    --TODO
-
-		TX_DLM_PREVIEW_IN			=>	TX_DLM_PREVIEW_IN(i),
-		SEND_DLM						=> TX_DLM(i),
-		SEND_DLM_WORD				=> TX_DLM_WORD(i),
-
-		SEND_LINK_RESET_IN		=> '0',	--CTRL_OP(i)(15),
-		TX_ALLOW_IN					=> tx_allow(i),
-		RX_ALLOW_IN					=> rx_allow(i),
-		LINK_PHASE_OUT				=>	link_phase_S(i),		--PL!
-
-		DEBUG_OUT					=> debug_tx_control_i(i),
-		STAT_REG_OUT				=> stat_tx_control_i(i)
-	);  
-
-	LINK_PHASE_OUT(i)		<= link_phase_S(i);		--PL!
-	-------------------------------------------------      
-	-- RX Data
-	-------------------------------------------------             
-	THE_RX_CONTROL : rx_control
-	port map(
-		CLK_200                        => clk_200_txdata,	--clk_200_i(i), --PL!
-		CLK_100                        => SYSCLK,
-		RESET_IN                       => rst(i),		--CLEAR, PL!
-
-		RX_DATA_OUT                    => open,	--	MED_DATA_OUT(i),
-		RX_PACKET_NUMBER_OUT           => open,	--	MED_PACKET_NUM_OUT(i),
-		RX_WRITE_OUT                   => open,	--	MED_DATAREADY_OUT(i),
-		RX_READ_IN                     => '0',		--	MED_READ_IN(i),
-
-		RX_DATA_IN                     => rx_data(i),
-		RX_K_IN                        => rx_k(i),
-
-		REQUEST_RETRANSMIT_OUT         => request_retr_i(i),
-		REQUEST_POSITION_OUT           => request_retr_position_i(i),
-
-		START_RETRANSMIT_OUT           => start_retr_i(i),
-		START_POSITION_OUT             => start_retr_position_i(i),
-
-		--send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
-		RX_DLM                         => RX_DLM(i),
-		RX_DLM_WORD                    => RX_DLM_WORD(i),
-
-		SEND_LINK_RESET_OUT            => send_link_reset_i(i),
-		MAKE_RESET_OUT                 => make_link_reset_i(i),
-		RX_ALLOW_IN                    => rx_allow(i),
-		GOT_LINK_READY                 => got_link_ready_i(i),
-
-		DEBUG_OUT                      => debug_rx_control_i(i),
-		STAT_REG_OUT                   => stat_rx_control_i(i)
-	);   
-
-	internal_make_link_reset_out(i)	<= make_link_reset_i(i)	when (IS_SYNC_SLAVE=c_YES) else '0';
-	sd_los_i(i)								<= SD_LOS_IN(i)			when rising_edge(SYSCLK);	-- PL!
-
-end generate;    
-    
--------------------------------------------------      
--- SCI
--------------------------------------------------      
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process 
-variable cnt : integer range 0 to 4 := 0;
-begin
-wait until rising_edge(SYSCLK);
-	SCI_ACK <= '0';
-	case sci_state is
-	when IDLE =>
-		sci_ch_i        <= x"0";
-		sci_qd_i        <= '0';
-		sci_reg_i       <= '0';
-		sci_read_i      <= '0';
-		sci_write_i     <= '0';
-		sci_timer(0)    <= sci_timer(0) + 1;
-		sci_timer(1)    <= sci_timer(1) + 1;
-		sci_timer(2)    <= sci_timer(2) + 1;
-		sci_timer(3)    <= sci_timer(3) + 1;
-		if SCI_READ = '1' or SCI_WRITE = '1' then
-			sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_addr_i    <= SCI_ADDR;
-			sci_data_in_i <= SCI_DATA_IN;
-			sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_state     <= SCTRL;
-		else
-			if sci_timer(0)(sci_timer'left) = '1' then
-				sci_timer(0)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(1)(sci_timer'left) = '1' then
-				sci_timer(1)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(2)(sci_timer'left) = '1' then
-				sci_timer(2)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(3)(sci_timer'left) = '1' then
-				sci_timer(3)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-		end if;      
-when SCTRL =>
-	if sci_reg_i = '1' then
-		SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-		SCI_ACK       <= '1';
-		sci_write_i   <= '0';
-		sci_read_i    <= '0';
-		sci_state     <= IDLE;
-	else
-		sci_state     <= SCTRL_WAIT;
-	end if;
-when SCTRL_WAIT   =>
-	sci_state       <= SCTRL_WAIT2;
-when SCTRL_WAIT2  =>
-	sci_state       <= SCTRL_FINISH;
-when SCTRL_FINISH =>
-	SCI_DATA_OUT    <= sci_data_out_i;
-	SCI_ACK         <= '1';
-	sci_write_i     <= '0';
-	sci_read_i      <= '0';
-	sci_state       <= IDLE;
-
-when GET_WA =>
-	if cnt = 4 then
-		cnt           := 0;
-		sci_state     <= IDLE;
-	else
-		sci_state     <= GET_WA_WAIT;
-		sci_addr_i    <= '0' & x"22";
-		sci_ch_i      <= x"0";
-		sci_ch_i(cnt) <= '1';
-		sci_read_i    <= '1';
-	end if;
-when GET_WA_WAIT  =>
-	sci_state       <= GET_WA_WAIT2;
-when GET_WA_WAIT2 =>
-	sci_state       <= GET_WA_FINISH;
-when GET_WA_FINISH =>
---		wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-	wa_position(cnt) <= sci_data_out_i(3 downto 0);
-	sci_state       <= GET_WA;    
-	cnt             := cnt + 1;
-end case;
-
-if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-	SCI_NACK <= '1';
-else
-	SCI_NACK <= '0';
-end if;
-
-end process;
-
-
---	-------------------------------------------------      
---	-- Debug Registers
---	-------------------------------------------------            
---	debug_reg(3 downto 0)   <= rx_fsm_state;
---	debug_reg(4)            <= rx_k;
---	debug_reg(5)            <= rx_error;
---	debug_reg(6)            <= rx_los_low;
---	debug_reg(7)            <= rx_cdr_lol;
---
---	debug_reg(8)            <= tx_k;
---	debug_reg(9)            <= tx_pll_lol;
---	debug_reg(10)           <= lsm_status;
---	debug_reg(11)           <= make_link_reset_i;
---	debug_reg(15 downto 12) <= tx_fsm_state;
---	-- debug_reg(31 downto 24) <= tx_data; 
---
---	debug_reg(16)           <= '0';
---	debug_reg(17)           <= tx_allow;
---	debug_reg(18)        <= RESET;
---	debug_reg(19)  <= CLEAR;
---	debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
---
---	debug_reg(35 downto 32) <= wa_position(3 downto 0);
---	debug_reg(36)   <= debug_tx_control_i(6);
---	debug_reg(39 downto 37) <= "000";
---	debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
-
-			
-	STAT_DEBUG <= (others => '0');	--debug_reg;
-
---	generated_status	: for i in 0 to 3 generate
-	--	internal_make_link_reset_out(i)	<= make_link_reset_i(i)	when (IS_SYNC_SLAVE=c_YES) else '0';
-	--	sd_los_i(i)								<= SD_LOS_IN(i)			when rising_edge(SYSCLK);	-- PL!
-
---		STAT_OP(i)(15)		<= send_link_reset_i(i) when rising_edge(SYSCLK);
---		STAT_OP(i)(14)		<= '0';
---		STAT_OP(i)(13)		<= internal_make_link_reset_out(i) when rising_edge(SYSCLK); --make trbnet reset
---		STAT_OP(i)(12)		<= '0';
---		STAT_OP(i)(11)		<= '0';
---		STAT_OP(i)(10)		<= rx_allow(i);
---		STAT_OP(i)(9) 		<= tx_allow(i);
---		STAT_OP(i)(8)		<= got_link_ready_i(i);
---		STAT_OP(i)(7)		<= send_link_reset_i(i);
---		STAT_OP(i)(6)		<= make_link_reset_i(i);
---		STAT_OP(i)(5)		<= request_retr_i(i);
---		STAT_OP(i)(4)		<= start_retr_i(i);
---		STAT_OP(i)(3 downto 0) <= x"0" when rx_allow_q(i) = '1' and tx_allow_q(i) = '1' else x"7";
---	end generate;
-
-end med_ecp3_sfp_4_sync_down_EP_arch;
\ No newline at end of file
diff --git a/code/med_ecp3_sfp_sync_down.vhd b/code/med_ecp3_sfp_sync_down.vhd
deleted file mode 100644
index 3a496ff..0000000
--- a/code/med_ecp3_sfp_sync_down.vhd
+++ /dev/null
@@ -1,573 +0,0 @@
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity med_ecp3_sfp_sync_down is
-	generic(	SERDES_NUM : integer range 0 to 3 := 0;
-				IS_SYNC_SLAVE   : integer := c_NO);       --select slave mode
-	port(
-		OSCCLK             : in  std_logic; -- _internal_ 200 MHz reference clock
-		SYSCLK             : in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
-		RESET              : in  std_logic; -- synchronous reset
-		CLEAR              : in  std_logic; -- asynchronous reset
-		--Internal Connection TX
-		MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-		MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
-		MED_DATAREADY_IN   : in  std_logic;
-		MED_READ_OUT       : out std_logic := '0';
-		--Internal Connection RX
-		MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
-		MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
-		MED_DATAREADY_OUT  : out std_logic := '0';
-		MED_READ_IN        : in  std_logic;
-		RX_HALF_CLK_OUT    : out std_logic := '0';  --received 100 MHz
-		RX_FULL_CLK_OUT    : out std_logic := '0';  --received 200 MHz
-		TX_HALF_CLK_OUT    : out std_logic := '0';  --pll 100 MHz
-		TX_FULL_CLK_OUT    : out std_logic := '0';  --pll 200 MHz
-
-		--Sync operation
-		RX_DLM             : out std_logic := '0';
-		RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
-		TX_DLM             : in  std_logic := '0';
-		TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
-		TX_DLM_PREVIEW_IN		: in std_logic := '0';	--PL!
-		LINK_PHASE_OUT			: out	std_logic := '0';	--PL!
-
-		--SFP Connection
-		SD_RXD_P_IN        : in  std_logic;
-		SD_RXD_N_IN        : in  std_logic;
-		SD_TXD_P_OUT       : out std_logic;
-		SD_TXD_N_OUT       : out std_logic;
-		SD_REFCLK_P_IN     : in  std_logic;  --not used
-		SD_REFCLK_N_IN     : in  std_logic;  --not used
-		SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
-		--Control Interface
-		SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
-		SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
-		SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
-		SCI_READ           : in  std_logic := '0';
-		SCI_WRITE          : in  std_logic := '0';
-		SCI_ACK            : out std_logic := '0';
-		SCI_NACK           : out std_logic := '0';
-		-- Status and control port
-		STAT_OP            : out std_logic_vector (15 downto 0);
-		CTRL_OP            : in  std_logic_vector (15 downto 0) := (others => '0');
-		STAT_DEBUG         : out std_logic_vector (63 downto 0);
-		CTRL_DEBUG         : in  std_logic_vector (63 downto 0) := (others => '0')
-	);
-end entity;
-
-
-architecture med_ecp3_sfp_sync_down_arch of med_ecp3_sfp_sync_down is
-
-  -- Placer Directives
-  attribute HGROUP : string;
-  -- for whole architecture
-  attribute HGROUP of med_ecp3_sfp_sync_down_arch : architecture  is "media_downlink_group";
-  attribute syn_sharing : string;
-  attribute syn_sharing of med_ecp3_sfp_sync_down_arch : architecture is "off";
-
-
-component DCS
--- synthesis translate_off
-generic
-(
-	DCSMODE	: string :="POS"
-);
--- synthesis translate_on
-port (
-	CLK0 :in std_logic ;
-	CLK1 :in std_logic ;
-	SEL :in std_logic ;
-	DCSOUT :out std_logic) ;
-end component;
-
-
---signal clk_200_i         : std_logic;
---signal clk_200_internal  : std_logic;
-signal clk_200_osc         : std_logic;
-signal clk_100_osc         : std_logic;
-signal rx_full_clk_ch0		: std_logic;
-signal rx_half_clk_ch0		: std_logic;
-signal tx_full_clk_ch0		: std_logic;
-signal tx_half_clk_ch0		: std_logic;
-
-signal tx_data           : std_logic_vector(7 downto 0);
-signal tx_k              : std_logic;
-signal rx_data           : std_logic_vector(7 downto 0);
-signal rx_k              : std_logic;
-signal rx_error          : std_logic;
-signal rx_dlm_S          : std_logic;	--PL!
-
-signal rst_n             : std_logic;
-signal rst						: std_logic;		-- PL!
-signal rx_serdes_rst     : std_logic;
-signal tx_serdes_rst     : std_logic;
-signal tx_pcs_rst        : std_logic;
-signal rx_pcs_rst        : std_logic;
-signal rst_qd            : std_logic;
-signal serdes_rst_qd     : std_logic;
-signal sd_los_i          : std_logic;	--PL!
-
-signal rx_los_low        : std_logic;
-signal lsm_status        : std_logic;
-signal rx_cdr_lol        : std_logic;
-signal tx_pll_lol        : std_logic;
-
-signal sci_ch_i          : std_logic_vector(3 downto 0);
-signal sci_qd_i          : std_logic;
-signal sci_reg_i         : std_logic;
-signal sci_addr_i        : std_logic_vector(8 downto 0);
-signal sci_data_in_i     : std_logic_vector(7 downto 0);
-signal sci_data_out_i    : std_logic_vector(7 downto 0);
-signal sci_read_i        : std_logic;
-signal sci_write_i       : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i  : std_logic_vector(2 downto 0);
-
--- fix signal names for constraining
-attribute syn_preserve : boolean;--
-attribute syn_keep : boolean;--
-attribute syn_preserve	of sci_ch_i				: signal is true;--
-attribute syn_keep		of sci_ch_i				: signal is true;--
-attribute syn_preserve	of sci_qd_i				: signal is true;--
-attribute syn_keep		of sci_qd_i				: signal is true;--
-attribute syn_preserve	of sci_reg_i			: signal is true;--
-attribute syn_keep		of sci_reg_i			: signal is true;--
-attribute syn_preserve	of sci_addr_i			: signal is true;--
-attribute syn_keep		of sci_addr_i			: signal is true;--
-attribute syn_preserve	of sci_data_in_i		: signal is true;--
-attribute syn_keep		of sci_data_in_i		: signal is true;--
-attribute syn_preserve	of sci_data_out_i		: signal is true;--
-attribute syn_keep		of sci_data_out_i		: signal is true;--
-attribute syn_preserve	of sci_read_i			: signal is true;--
-attribute syn_keep		of sci_read_i			: signal is true;--
-attribute syn_preserve	of sci_write_i			: signal is true;--
-attribute syn_keep		of sci_write_i			: signal is true;--
-attribute syn_preserve	of sci_write_shift_i	: signal is true;--
-attribute syn_keep		of sci_write_shift_i	: signal is true;--
-attribute syn_preserve	of	sci_read_shift_i	: signal is true;--
-attribute syn_keep		of sci_read_shift_i	: signal is true;--
-
-signal buf_med_dataready_out : std_logic;
-
-signal wa_position        : std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx     : std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow           : std_logic;
-signal rx_allow           : std_logic;
-signal tx_allow_q         : std_logic;
-signal rx_allow_q         : std_logic;
-signal link_phase_S			: std_logic;	--PL!
-signal request_retr_i     : std_logic;
-signal start_retr_i       : std_logic;
-signal request_retr_position_i  : std_logic_vector(7 downto 0);
-signal start_retr_position_i    : std_logic_vector(7 downto 0);
-signal send_link_reset_i  : std_logic;
-signal make_link_reset_i  : std_logic;
-signal got_link_ready_i   : std_logic;
-signal internal_make_link_reset_out : std_logic;
-
-attribute syn_preserve	of	wa_position			: signal is true;--
-attribute syn_keep		of wa_position			: signal is true;--
-attribute syn_preserve	of	wa_position_rx		: signal is true;--
-attribute syn_keep		of wa_position_rx		: signal is true;--
-
-signal stat_rx_control_i  : std_logic_vector(31 downto 0);
-signal stat_tx_control_i  : std_logic_vector(31 downto 0);
-signal debug_rx_control_i : std_logic_vector(31 downto 0);
-signal debug_tx_control_i : std_logic_vector(31 downto 0);
-signal rx_fsm_state       : std_logic_vector(3 downto 0);
-signal tx_fsm_state       : std_logic_vector(3 downto 0);
-signal debug_reg          : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state         : sci_ctrl;
-signal sci_timer         : unsigned(12 downto 0) := (others => '0');
-signal start_timer       : unsigned(18 downto 0) := (others => '0');
---signal watchdog_timer	: unsigned(20 downto 0) := (others => '0');
---signal watchdog_trigger	: std_logic :='0';
-
-signal led_dlm, last_led_dlm  : std_logic;
-signal led_ok                 : std_logic;
-signal led_tx, last_led_tx    : std_logic;
-signal led_rx, last_led_rx    : std_logic;
-signal timer    : unsigned(20 downto 0);
-
-begin
-
-clk_200_osc		<= OSCCLK;	
-clk_100_osc		<= SYSCLK;	
-	
-RX_HALF_CLK_OUT	<= rx_half_clk_ch0;
-RX_FULL_CLK_OUT	<= rx_full_clk_ch0;
-TX_HALF_CLK_OUT	<= tx_half_clk_ch0;
-TX_FULL_CLK_OUT	<= tx_full_clk_ch0;
-
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
-
-
---rst_n <= not CLEAR;	PL!
---rst_n					<= not(CLEAR or sd_los_i or internal_make_link_reset_out);	-- or watchdog_trigger);
---rst					<=		(CLEAR or sd_los_i or internal_make_link_reset_out);	-- or watchdog_trigger);
-rst_n					<= not(CLEAR or internal_make_link_reset_out);
-rst					<=		(CLEAR or internal_make_link_reset_out);
-
--------------------------------------------------      
--- Serdes
--------------------------------------------------      
-THE_SERDES : entity work.serdes_sync_source_downstream
-  port map(
-    hdinp_ch0            => SD_RXD_P_IN,
-    hdinn_ch0            => SD_RXD_N_IN,
-    hdoutp_ch0           => SD_TXD_P_OUT,
-    hdoutn_ch0           => SD_TXD_N_OUT,
-    rxiclk_ch0           => tx_full_clk_ch0,		-- read fifo is no longer present! PL!
-    txiclk_ch0           => tx_full_clk_ch0,
-    rx_full_clk_ch0      => rx_full_clk_ch0,
-    rx_half_clk_ch0      => rx_half_clk_ch0,
-    tx_full_clk_ch0      => tx_full_clk_ch0,
-    tx_half_clk_ch0      => tx_half_clk_ch0,
-    fpga_rxrefclk_ch0    => clk_200_osc,			-- REF CLK MUST ALWAYS BE PRESENT
-    txdata_ch0           => tx_data,
-    tx_k_ch0             => tx_k,
-    tx_force_disp_ch0    => '0',
-    tx_disp_sel_ch0      => '0',
-    rxdata_ch0           => rx_data,
-    rx_k_ch0             => rx_k,
-    rx_disp_err_ch0      => open,
-    rx_cv_err_ch0        => rx_error,
-    rx_serdes_rst_ch0_c  => rx_serdes_rst,
-    sb_felb_ch0_c        => '0',
-    sb_felb_rst_ch0_c    => '0',
-    tx_pcs_rst_ch0_c     => tx_pcs_rst,
-    tx_pwrup_ch0_c       => '1',
-    rx_pcs_rst_ch0_c     => rx_pcs_rst,
-    rx_pwrup_ch0_c       => '1',
-    rx_los_low_ch0_s     => rx_los_low,
-    lsm_status_ch0_s     => lsm_status,
-    rx_cdr_lol_ch0_s     => rx_cdr_lol,
-    tx_div2_mode_ch0_c   => '0',
-    rx_div2_mode_ch0_c   => '0',
-	 refclk2fpga				=> open,	--refclk2core_S,
-    
-    SCI_WRDATA           => sci_data_in_i,
-    SCI_RDDATA           => sci_data_out_i,
-    SCI_ADDR             => sci_addr_i(5 downto 0),
-    SCI_SEL_QUAD         => sci_qd_i,
-    SCI_SEL_CH0          => sci_ch_i(0),
-    SCI_RD               => sci_read_i,
-    SCI_WRN              => sci_write_i,
-    
-    fpga_txrefclk        => clk_200_osc,			-- REF CLK MUST ALWAYS BE PRESENT
-    tx_serdes_rst_c      => '0',	--tx_serdes_rst,
-    tx_pll_lol_qd_s      => tx_pll_lol,
-    rst_qd_c             => rst_qd,
-    serdes_rst_qd_c      => serdes_rst_qd
-
-    );
-
-    
--------------------------------------------------      
--- Reset FSM & Link states
--------------------------------------------------      
-THE_RX_FSM : rx_reset_fsm
-  port map(
-    RST_N               => rst_n,
-    RX_REFCLK           => clk_200_osc,	--rx_full_clk_ch0,
-    TX_PLL_LOL_QD_S     => tx_pll_lol,
-    RX_SERDES_RST_CH_C  => rx_serdes_rst,
-    RX_CDR_LOL_CH_S     => rx_cdr_lol,
-    RX_LOS_LOW_CH_S     => rx_los_low,
-    RX_PCS_RST_CH_C     => rx_pcs_rst,
-    WA_POSITION         => wa_position_rx(3 downto 0),
-    STATE_OUT           => rx_fsm_state
-    );
-    
-THE_TX_FSM : tx_reset_fsm
-  port map(
-    RST_N           => rst_n,
-    TX_REFCLK       => clk_200_osc,
-    TX_PLL_LOL_QD_S => tx_pll_lol,
-    RST_QD_C        => rst_qd,
-    TX_PCS_RST_CH_C => tx_pcs_rst,
-    STATE_OUT       => tx_fsm_state
-    );
-
--- Master does not do bit-locking    
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
-
-
---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
-PROC_ALLOW : process begin
-  wait until rising_edge(clk_200_osc);	--clk_200_i);
-  if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
-    rx_allow <= '1';
-  else
-    rx_allow <= '0';
-  end if;
-  if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
-    tx_allow <= '1';
-  else
-    tx_allow <= '0';
-  end if;
-end process;
-
-rx_allow_q <= rx_allow when rising_edge(clk_100_osc);
-tx_allow_q <= tx_allow when rising_edge(clk_100_osc);
-
-
--- start_timer begins when the rx-link is ready; i.e.: there is a working link.
--- If you are a SLAVE, you can then start transmitting right away. -- if you are a MASTER, you wait for the start_timer MSB to go high.
--- This gives a slave on the other side time to start-up
--- if the rx-link is NOT ready, the watchdog_timer starts. It should be longer than start_timer and will cause a hanging link to reset
-PROC_START_TIMER : process(clk_200_osc)	--clk_200_i)
-begin
-	if rising_edge(clk_200_osc) then
-		if got_link_ready_i = '1' then
-			if start_timer(start_timer'left) = '0' then
-				start_timer <= start_timer + 1;
-			end if;  
-		else
-			start_timer <= (others => '0');
-		end if;
-	end if;
-end process;
-
--------------------------------------------------      
--- TX Data
--------------------------------------------------         
-THE_TX : soda_tx_control
-	port map(
-		CLK_200						=> clk_200_osc,
-		CLK_100						=> clk_100_osc,
-		RESET_IN						=> rst,		--CLEAR, PL!
-
-		TX_DATA_IN					=> MED_DATA_IN,
-		TX_PACKET_NUMBER_IN		=> MED_PACKET_NUM_IN,
-		TX_WRITE_IN					=> MED_DATAREADY_IN,
-		TX_READ_OUT					=> MED_READ_OUT,
-
-		TX_DATA_OUT					=> tx_data,
-		TX_K_OUT						=> tx_k,
-
-		REQUEST_RETRANSMIT_IN	=> request_retr_i,             --TODO
-		REQUEST_POSITION_IN		=> request_retr_position_i,    --TODO
-
-		START_RETRANSMIT_IN		=> start_retr_i,               --TODO
-		START_POSITION_IN			=> start_retr_position_i,      --TODO
-
-		TX_DLM_PREVIEW_IN			=>	TX_DLM_PREVIEW_IN,
-		SEND_DLM						=> TX_DLM,
-		SEND_DLM_WORD				=> TX_DLM_WORD,
-
-		SEND_LINK_RESET_IN		=> CTRL_OP(15),
-		TX_ALLOW_IN					=> tx_allow,
-		RX_ALLOW_IN					=> rx_allow,
-		LINK_PHASE_OUT				=>	link_phase_S,		--PL!
-
-		DEBUG_OUT					=> debug_tx_control_i,
-		STAT_REG_OUT				=> stat_tx_control_i
-);  
-
-LINK_PHASE_OUT		<= link_phase_S;		--PL!
--------------------------------------------------      
--- RX Data
--------------------------------------------------             
-THE_RX_CONTROL : rx_control
-  port map(
-    CLK_200                        => tx_full_clk_ch0,	--rx_full_clk_ch0, PL! 270814
-    CLK_100                        => clk_100_osc,
-    RESET_IN                       => rst,		--CLEAR, PL!
-
-    RX_DATA_OUT                    => MED_DATA_OUT,
-    RX_PACKET_NUMBER_OUT           => MED_PACKET_NUM_OUT,
-    RX_WRITE_OUT                   => buf_med_dataready_out,
-    RX_READ_IN                     => MED_READ_IN,
-
-    RX_DATA_IN                     => rx_data,
-    RX_K_IN                        => rx_k,
-
-    REQUEST_RETRANSMIT_OUT         => request_retr_i,
-    REQUEST_POSITION_OUT           => request_retr_position_i,
-
-    START_RETRANSMIT_OUT           => start_retr_i,
-    START_POSITION_OUT             => start_retr_position_i,
-
-    --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
-    RX_DLM                         => rx_dlm_S,		--RX_DLM,
-    RX_DLM_WORD                    => RX_DLM_WORD,
-    
-    SEND_LINK_RESET_OUT            => send_link_reset_i,
-    MAKE_RESET_OUT                 => make_link_reset_i,
-    RX_ALLOW_IN                    => rx_allow,
-    GOT_LINK_READY                 => got_link_ready_i,
-
-    DEBUG_OUT                      => debug_rx_control_i,
-    STAT_REG_OUT                   => stat_rx_control_i
-    );   
-    
-RX_DLM				<= rx_dlm_S;		--!PL 16032015
-MED_DATAREADY_OUT <= buf_med_dataready_out;    
-    
--------------------------------------------------      
--- SCI
--------------------------------------------------      
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process 
-  variable cnt : integer range 0 to 4 := 0;
-begin
-  wait until rising_edge(clk_100_osc);
-  SCI_ACK <= '0';
-  case sci_state is
-    when IDLE =>
-      sci_ch_i        <= x"0";
-      sci_qd_i        <= '0';
-      sci_reg_i       <= '0';
-      sci_read_i      <= '0';
-      sci_write_i     <= '0';
-      sci_timer       <= sci_timer + 1;
-      if SCI_READ = '1' or SCI_WRITE = '1' then
-        sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-        sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-        sci_addr_i    <= SCI_ADDR;
-        sci_data_in_i <= SCI_DATA_IN;
-        sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-        sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-        sci_state     <= SCTRL;
-      elsif sci_timer(sci_timer'left) = '1' then
-        sci_timer     <= (others => '0');
-        sci_state     <= GET_WA;
-      end if;      
-    when SCTRL =>
-      if sci_reg_i = '1' then
-        SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-        SCI_ACK       <= '1';
-        sci_write_i   <= '0';
-        sci_read_i    <= '0';
-        sci_state     <= IDLE;
-      else
-        sci_state     <= SCTRL_WAIT;
-      end if;
-    when SCTRL_WAIT   =>
-      sci_state       <= SCTRL_WAIT2;
-    when SCTRL_WAIT2  =>
-      sci_state       <= SCTRL_FINISH;
-    when SCTRL_FINISH =>
-      SCI_DATA_OUT    <= sci_data_out_i;
-      SCI_ACK         <= '1';
-      sci_write_i     <= '0';
-      sci_read_i      <= '0';
-      sci_state       <= IDLE;
-    
-    when GET_WA =>
-      if cnt = 4 then
-        cnt           := 0;
-        sci_state     <= IDLE;
-      else
-        sci_state     <= GET_WA_WAIT;
-        sci_addr_i    <= '0' & x"22";
-        sci_ch_i      <= x"0";
-        sci_ch_i(cnt) <= '1';
-        sci_read_i    <= '1';
-      end if;
-    when GET_WA_WAIT  =>
-      sci_state       <= GET_WA_WAIT2;
-    when GET_WA_WAIT2 =>
-      sci_state       <= GET_WA_FINISH;
-    when GET_WA_FINISH =>
-      wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-      sci_state       <= GET_WA;    
-      cnt             := cnt + 1;
-  end case;
-  
-  if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-    SCI_NACK <= '1';
-  else
-    SCI_NACK <= '0';
-  end if;
-  
-end process;
-
--------------------------------------------------      
--- Generate LED signals
--------------------------------------------------   
-led_ok <= rx_allow and tx_allow when rising_edge(clk_100_osc); 
-led_rx <= (buf_med_dataready_out or led_rx)  and not timer(20) when rising_edge(clk_100_osc);
-led_tx <= (MED_DATAREADY_IN or led_tx or sd_los_i)  and not timer(20) when rising_edge(clk_100_osc);
-led_dlm <= (led_dlm or rx_dlm_S) and not timer(20) when rising_edge(clk_100_osc);
-
-ROC_TIMER : process begin
-  wait until rising_edge(clk_100_osc);
-  timer <= timer + 1 ;
-  if timer(20) = '1' then
-    timer <= (others => '0');
-    last_led_rx <= led_rx ;
-    last_led_tx <= led_tx;
-    last_led_dlm <= led_dlm;
-  end if;
-end process;
-
-
--------------------------------------------------      
--- Debug Registers
--------------------------------------------------            
-debug_reg(3 downto 0)   <= rx_fsm_state;
-debug_reg(4)            <= rx_k;
-debug_reg(5)            <= rx_error;
-debug_reg(6)            <= rx_los_low;
-debug_reg(7)            <= rx_cdr_lol;
-
-debug_reg(8)            <= tx_k;
-debug_reg(9)            <= tx_pll_lol;
-debug_reg(10)           <= lsm_status;
-debug_reg(11)           <= make_link_reset_i;
-debug_reg(15 downto 12) <= tx_fsm_state;
--- debug_reg(31 downto 24) <= tx_data; 
-
-debug_reg(16)           <= '0';
-debug_reg(17)           <= tx_allow;
-debug_reg(18)           <= RESET;
-debug_reg(19)           <= CLEAR;
-debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
-
-debug_reg(35 downto 32) <= wa_position(3 downto 0);
-debug_reg(36)           <= debug_tx_control_i(6);
-debug_reg(39 downto 37) <= "000";
-debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
-
-      
-STAT_DEBUG <= debug_reg;
-
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
-sd_los_i <= SD_LOS_IN when rising_edge(clk_100_osc);	-- PL!
-
-STAT_OP(15)		<= send_link_reset_i when rising_edge(clk_100_osc);
-STAT_OP(14)		<= '0';
-STAT_OP(13)		<= internal_make_link_reset_out when rising_edge(clk_100_osc); --make trbnet reset
-STAT_OP(12) <= led_dlm or last_led_dlm;
-STAT_OP(11) <= led_tx or last_led_tx;
-STAT_OP(10) <= led_rx or last_led_rx;
-STAT_OP(9)  <= led_ok;
---STAT_OP(8 downto 4) <= (others => '0');
-STAT_OP(8)		<= got_link_ready_i;
-STAT_OP(7)		<= send_link_reset_i;
-STAT_OP(6)		<= make_link_reset_i;
-STAT_OP(5)		<= request_retr_i;
-STAT_OP(4)		<= start_retr_i;
-STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-
-end med_ecp3_sfp_sync_down_arch;
diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd
deleted file mode 100644
index 405afb9..0000000
--- a/code/med_ecp3_sfp_sync_up.vhd
+++ /dev/null
@@ -1,558 +0,0 @@
---Media interface for Lattice ECP3 using PCS at 2GHz
--- TAB=3
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity med_ecp3_sfp_sync_up is
-	generic(	SERDES_NUM				: integer range 0 to 3 := 0;
-				IS_SYNC_SLAVE			: integer := c_YES);  --select slave mode
-	port(
-		OSCCLK					: in std_logic; -- 200 MHz reference clock
-		SYSCLK					: in std_logic; -- 100 MHz main clock net, synchronous to RX clock
-		RESET						: in std_logic; -- synchronous reset
-		CLEAR						: in std_logic; -- asynchronous reset
-		--Internal Connection TX
-		MED_DATA_IN				: in std_logic_vector(c_DATA_WIDTH-1 downto 0);
-		MED_PACKET_NUM_IN		: in std_logic_vector(c_NUM_WIDTH-1 downto 0);
-		MED_DATAREADY_IN		: in std_logic;
-		MED_READ_OUT			: out std_logic := '0';
-		--Internal Connection RX
-		MED_DATA_OUT			: out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
-		MED_PACKET_NUM_OUT	: out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
-		MED_DATAREADY_OUT		: out std_logic := '0';
-		MED_READ_IN				: in std_logic;
-		RX_HALF_CLK_OUT		: out std_logic := '0'; --received 100 MHz
-		RX_FULL_CLK_OUT		: out std_logic := '0'; --received 200 MHz
-		TX_HALF_CLK_OUT		: out std_logic := '0'; --received 100 MHz
-		TX_FULL_CLK_OUT		: out std_logic := '0'; --received 200 MHz
-		RX_CDR_LOL_OUT			: out std_logic := '0';	-- CLOCK_DATA RECOVERY LOSS_OF_LOCK 	!PL14082014
-
-		--Sync operation
-		RX_DLM					: out std_logic := '0';
-		RX_DLM_WORD				: out std_logic_vector(7 downto 0) := x"00";
-		TX_DLM					: in std_logic := '0';
-		TX_DLM_WORD				: in std_logic_vector(7 downto 0) := x"00";
-		TX_DLM_PREVIEW_IN		: in std_logic := '0'; --PL!
-		LINK_PHASE_OUT			: out	std_logic := '0';	--PL!
-		LINK_READY_OUT			: out	std_logic := '0';	--PL!
-
-		--SFP Connection
-		SD_RXD_P_IN				: in std_logic;
-		SD_RXD_N_IN				: in std_logic;
-		SD_TXD_P_OUT			: out std_logic;
-		SD_TXD_N_OUT			: out std_logic;
-		SD_REFCLK_P_IN			: in std_logic; --not used
-		SD_REFCLK_N_IN			: in std_logic; --not used
-		SD_PRSNT_N_IN			: in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		SD_LOS_IN				: in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		SD_TXDIS_OUT			: out std_logic := '0'; -- SFP disable
-		--Control Interface
-		SCI_DATA_IN				: in std_logic_vector(7 downto 0) := (others => '0');
-		SCI_DATA_OUT			: out std_logic_vector(7 downto 0) := (others => '0');
-		SCI_ADDR					: in std_logic_vector(8 downto 0) := (others => '0');
-		SCI_READ					: in std_logic := '0';
-		SCI_WRITE				: in std_logic := '0';
-		SCI_ACK					: out std_logic := '0';
-		SCI_NACK					: out std_logic := '0';
-		-- Status and control port
-		STAT_OP					: out std_logic_vector (15 downto 0);
-		CTRL_OP					: in std_logic_vector (15 downto 0) := (others => '0');
-		STAT_DEBUG				: out std_logic_vector (63 downto 0);
-		CTRL_DEBUG				: in std_logic_vector (63 downto 0) := (others => '0')
-	);
-end entity;
-
-
-architecture med_ecp3_sfp_sync_up_arch of med_ecp3_sfp_sync_up is
-
--- Placer Directives
-attribute HGROUP : string;
--- for whole architecture
-attribute HGROUP of med_ecp3_sfp_sync_up_arch : architecture  is "media_uplink_group";
-attribute syn_sharing : string;
-attribute syn_sharing of med_ecp3_sfp_sync_up_arch : architecture is "off";
-
-
-component DCS
--- synthesis translate_off
-generic(
-DSCMODE	: string :="POS"
-);
--- synthesis translate_on
-port (
-CLK0 :in std_logic ;
-CLK1 :in std_logic ;
-SEL :in std_logic ;
-DCSOUT :out std_logic) ;
-end component;
-
-
-signal clk_200_osc      : std_logic;
-signal rx_full_clk		: std_logic;
-signal rx_half_clk		: std_logic;
-signal tx_full_clk		: std_logic;
-signal tx_half_clk		: std_logic;
-
-signal tx_data           : std_logic_vector(7 downto 0);
-signal tx_k              : std_logic;
-signal rx_data           : std_logic_vector(7 downto 0);
-signal rx_k              : std_logic;
-signal rx_error          : std_logic;
-
-signal rst_n             : std_logic;
-signal rst						: std_logic;		-- PL!
-signal rx_serdes_rst     : std_logic;
-signal tx_serdes_rst     : std_logic;
-signal tx_pcs_rst        : std_logic;
-signal rx_pcs_rst        : std_logic;
-signal rst_qd            : std_logic;
-signal serdes_rst_qd     : std_logic;
-signal sd_los_i          : std_logic;	--PL!
-
-signal rx_los_low        : std_logic;
-signal lsm_status        : std_logic;
-signal rx_cdr_lol        : std_logic;
-signal tx_pll_lol        : std_logic;
-
-signal sci_ch_i          : std_logic_vector(3 downto 0);
-signal sci_qd_i          : std_logic;
-signal sci_reg_i         : std_logic;
-signal sci_addr_i        : std_logic_vector(8 downto 0);
-signal sci_data_in_i     : std_logic_vector(7 downto 0);
-signal sci_data_out_i    : std_logic_vector(7 downto 0);
-signal sci_read_i        : std_logic;
-signal sci_write_i       : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i  : std_logic_vector(2 downto 0);
-
--- fix signal names for constraining
-attribute syn_preserve		: boolean;
-attribute syn_keep			: boolean;
-attribute syn_useioff		: boolean;
-
-attribute syn_useioff	of sd_los_i				: signal is false;		-- do not use an IOFF for this signal
-
-attribute syn_preserve	of sci_ch_i				: signal is true;
-attribute syn_keep		of sci_ch_i				: signal is true;
-attribute syn_preserve	of sci_qd_i				: signal is true;
-attribute syn_keep		of sci_qd_i				: signal is true;
-attribute syn_preserve	of sci_reg_i			: signal is true;
-attribute syn_keep		of sci_reg_i			: signal is true;
-attribute syn_preserve	of sci_addr_i			: signal is true;
-attribute syn_keep		of sci_addr_i			: signal is true;
-attribute syn_preserve	of sci_data_in_i		: signal is true;
-attribute syn_keep		of sci_data_in_i		: signal is true;
-attribute syn_preserve	of sci_data_out_i		: signal is true;
-attribute syn_keep		of sci_data_out_i		: signal is true;
-attribute syn_preserve	of sci_read_i			: signal is true;
-attribute syn_keep		of sci_read_i			: signal is true;
-attribute syn_preserve	of sci_write_i			: signal is true;
-attribute syn_keep		of sci_write_i			: signal is true;
-attribute syn_preserve	of sci_write_shift_i	: signal is true;
-attribute syn_keep		of sci_write_shift_i	: signal is true;
-attribute syn_preserve	of	sci_read_shift_i	: signal is true;
-attribute syn_keep		of sci_read_shift_i	: signal is true;
-
-signal wa_position						: std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx					: std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow							: std_logic;
-signal rx_allow							: std_logic;
-signal tx_allow_q							: std_logic;
-signal rx_allow_q							: std_logic;
-signal link_phase_S						: std_logic;	--PL!
-signal request_retr_i					: std_logic;
-signal start_retr_i						: std_logic;
-signal request_retr_position_i		: std_logic_vector(7 downto 0);
-signal start_retr_position_i			: std_logic_vector(7 downto 0);
-signal send_link_reset_i				: std_logic;
-signal make_link_reset_i				: std_logic;
-signal got_link_ready_i					: std_logic;
-signal internal_make_link_reset_out : std_logic;
-
-attribute syn_preserve	of	wa_position			: signal is true;
-attribute syn_keep		of wa_position			: signal is true;
-attribute syn_preserve	of	wa_position_rx		: signal is true;
-attribute syn_keep		of wa_position_rx		: signal is true;
-
-signal stat_rx_control_i  : std_logic_vector(31 downto 0);
-signal stat_tx_control_i  : std_logic_vector(31 downto 0);
-signal debug_rx_control_i : std_logic_vector(31 downto 0);
-signal debug_tx_control_i : std_logic_vector(31 downto 0);
-signal rx_fsm_state       : std_logic_vector(3 downto 0);
-signal tx_fsm_state       : std_logic_vector(3 downto 0);
-signal debug_reg          : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state         : sci_ctrl;
-signal sci_timer         : unsigned(12 downto 0) := (others => '0');
-signal start_timer       : unsigned(18 downto 0) := (others => '0');
-signal watchdog_timer	: unsigned(20 downto 0) := (others => '0');
-signal watchdog_trigger	: std_logic :='0';
-
-begin
-
-clk_200_osc			<= OSCCLK;
-
-RX_HALF_CLK_OUT	<= rx_half_clk;
-RX_FULL_CLK_OUT	<= rx_full_clk;
-TX_HALF_CLK_OUT	<= tx_half_clk;
-TX_FULL_CLK_OUT	<= tx_full_clk;
-RX_CDR_LOL_OUT		<= rx_cdr_lol;		-- !PL14082014
-
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
-
-LINK_READY_OUT		<= got_link_ready_i when rising_edge(rx_half_clk);
-
-
---rst_n <= not CLEAR;	PL!
-rst_n					<= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
-rst					<=		(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
-
-
---gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
---  clk_200_i        <= rx_full_clk;
---end generate;
-
---gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
--- clk_200_i        <= clk_200_internal;
---end generate;
-
-
--------------------------------------------------      
--- Serdes
--------------------------------------------------      
-THE_SERDES : entity work.serdes_sync_upstream
-  port map(
-    hdinp_ch3            => SD_RXD_P_IN,
-    hdinn_ch3            => SD_RXD_N_IN,
-    hdoutp_ch3           => SD_TXD_P_OUT,
-    hdoutn_ch3           => SD_TXD_N_OUT,
-    txiclk_ch3           => rx_full_clk,
-    rx_full_clk_ch3      => rx_full_clk,
-    rx_half_clk_ch3      => rx_half_clk,
-    tx_full_clk_ch3      => tx_full_clk,
-    tx_half_clk_ch3      => tx_half_clk,
-    fpga_rxrefclk_ch3    => clk_200_osc,
-    txdata_ch3           => tx_data,
-    tx_k_ch3             => tx_k,
-    tx_force_disp_ch3    => '0',
-    tx_disp_sel_ch3      => '0',
-    rxdata_ch3           => rx_data,
-    rx_k_ch3             => rx_k,
-    rx_disp_err_ch3      => open,
-    rx_cv_err_ch3        => rx_error,
-    rx_serdes_rst_ch3_c  => rx_serdes_rst,
-    sb_felb_ch3_c        => '0',
-    sb_felb_rst_ch3_c    => '0',
-    tx_pcs_rst_ch3_c     => tx_pcs_rst,
-    tx_pwrup_ch3_c       => '1',
-    rx_pcs_rst_ch3_c     => rx_pcs_rst,
-    rx_pwrup_ch3_c       => '1',
-    rx_los_low_ch3_s     => rx_los_low,
-    lsm_status_ch3_s     => lsm_status,
-    rx_cdr_lol_ch3_s     => rx_cdr_lol,
-    tx_div2_mode_ch3_c   => '0',
-    rx_div2_mode_ch3_c   => '0',
-    
-    SCI_WRDATA           => sci_data_in_i,
-    SCI_RDDATA           => sci_data_out_i,
-    SCI_ADDR             => sci_addr_i(5 downto 0),
-    SCI_SEL_QUAD         => sci_qd_i,
-    SCI_SEL_ch3          => sci_ch_i(3),
-    SCI_RD               => sci_read_i,
-    SCI_WRN              => sci_write_i,
-    
-    fpga_txrefclk        => rx_full_clk, --clk_200_osc,
-    tx_serdes_rst_c      => tx_serdes_rst,
-    tx_pll_lol_qd_s      => tx_pll_lol,
-    rst_qd_c             => rst_qd,
-    serdes_rst_qd_c      => serdes_rst_qd
-
-    );
-
--------------------------------------------------      
--- Reset FSM & Link states
--------------------------------------------------      
-THE_RX_FSM : rx_reset_fsm
-  port map(
-    RST_N               => rst_n,
-    RX_REFCLK           => clk_200_osc,		-- allways running PL!
-    TX_PLL_LOL_QD_S     => tx_pll_lol,
-    RX_SERDES_RST_CH_C  => rx_serdes_rst,
-    RX_CDR_LOL_CH_S     => rx_cdr_lol,
-    RX_LOS_LOW_CH_S     => rx_los_low,
-    RX_PCS_RST_CH_C     => rx_pcs_rst,
-    WA_POSITION         => wa_position_rx(15 downto 12),
-    STATE_OUT           => rx_fsm_state
-    );
-    
-THE_TX_FSM : tx_reset_fsm
-  port map(
-    RST_N           => rst_n,
-    TX_REFCLK       => clk_200_osc,			-- allways running PL! 18-06 was clk_200_i
-    TX_PLL_LOL_QD_S => tx_pll_lol,
-    RST_QD_C        => rst_qd,
-    TX_PCS_RST_CH_C => tx_pcs_rst,
-    STATE_OUT       => tx_fsm_state
-    );
-
--- Master does not do bit-locking    
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
-
-
---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
-PROC_ALLOW : process begin
-  wait until rising_edge(rx_full_clk);	--clk_200_osc);	--clk_200_i);
-  if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
-    rx_allow <= '1';
-  else
-    rx_allow <= '0';
-  end if;
-  if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
-    tx_allow <= '1';
-  else
-    tx_allow <= '0';
-  end if;
-end process;
-
-rx_allow_q <= rx_allow when rising_edge(rx_half_clk);	--SYSCLK);
-tx_allow_q <= tx_allow when rising_edge(rx_half_clk);	--SYSCLK);
-
-
-PROC_START_TIMER : process(rx_full_clk)	--clk_200_osc)	--clk_200_i)
-begin
-	if rising_edge(rx_full_clk)	then --clk_200_osc) then
-		if got_link_ready_i = '1' then
-			watchdog_timer	<= (others => '0');
-			if start_timer(start_timer'left) = '0' then
-				start_timer <= start_timer + 1;
-			end if;  
-		else
-			start_timer <= (others => '0');
-			if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then
-				watchdog_trigger	<= '1';
-			else 
-				watchdog_trigger	<= '0';
-			end if;
-			if watchdog_trigger = '0' then
-				watchdog_timer	<= watchdog_timer + 1;
-			else 
-				watchdog_timer	<= (others => '0');
-			end if;
-		end if;
-	end if;
-end process;
--------------------------------------------------      
--- TX Data
--------------------------------------------------         
-THE_TX : soda_tx_control
-	port map(
-		CLK_200						=> rx_full_clk,	--clk_200_osc,	--clk_200_i,
-		CLK_100						=> rx_half_clk,	--SYSCLK,
-		RESET_IN						=> rst,		--CLEAR, PL!
-
-		TX_DATA_IN					=> MED_DATA_IN,
-		TX_PACKET_NUMBER_IN		=> MED_PACKET_NUM_IN,
-		TX_WRITE_IN					=> MED_DATAREADY_IN,
-		TX_READ_OUT					=> MED_READ_OUT,
-
-		TX_DATA_OUT					=> tx_data,
-		TX_K_OUT						=> tx_k,
-
-		REQUEST_RETRANSMIT_IN	=> request_retr_i,             --TODO
-		REQUEST_POSITION_IN		=> request_retr_position_i,    --TODO
-
-		START_RETRANSMIT_IN		=> start_retr_i,               --TODO
-		START_POSITION_IN			=> request_retr_position_i,    --TODO
-
-		TX_DLM_PREVIEW_IN			=>	TX_DLM_PREVIEW_IN,
-		SEND_DLM						=> TX_DLM,
-		SEND_DLM_WORD				=> TX_DLM_WORD,
-
-		SEND_LINK_RESET_IN		=> CTRL_OP(15),
-		TX_ALLOW_IN					=> tx_allow,
-		RX_ALLOW_IN					=> rx_allow,
-		LINK_PHASE_OUT				=>	link_phase_S,		--PL!
-
-		DEBUG_OUT					=> debug_tx_control_i,
-		STAT_REG_OUT				=> stat_tx_control_i
-);  
-
-LINK_PHASE_OUT		<= link_phase_S;		--PL!
--------------------------------------------------      
--- RX Data
--------------------------------------------------             
-THE_RX_CONTROL : rx_control
-  port map(
-    CLK_200                        => rx_full_clk,
-    CLK_100                        => rx_half_clk,
-    RESET_IN                       => rst,
-
-    RX_DATA_OUT                    => MED_DATA_OUT,
-    RX_PACKET_NUMBER_OUT           => MED_PACKET_NUM_OUT,
-    RX_WRITE_OUT                   => MED_DATAREADY_OUT,
-    RX_READ_IN                     => MED_READ_IN,
-
-    RX_DATA_IN                     => rx_data,
-    RX_K_IN                        => rx_k,
-
-    REQUEST_RETRANSMIT_OUT         => request_retr_i,
-    REQUEST_POSITION_OUT           => request_retr_position_i,
-
-    START_RETRANSMIT_OUT           => start_retr_i,
-    START_POSITION_OUT             => start_retr_position_i,
-
-    --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
-    RX_DLM                         => RX_DLM,
-    RX_DLM_WORD                    => RX_DLM_WORD,
-    
-    SEND_LINK_RESET_OUT            => send_link_reset_i,
-    MAKE_RESET_OUT                 => make_link_reset_i,
-    RX_ALLOW_IN                    => rx_allow,
-    GOT_LINK_READY                 => got_link_ready_i,
-
-    DEBUG_OUT                      => debug_rx_control_i,
-    STAT_REG_OUT                   => stat_rx_control_i
-    );   
-    
-    
-    
--------------------------------------------------      
--- SCI
--------------------------------------------------      
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process 
-  variable cnt : integer range 0 to 4 := 0;
-begin
-  wait until rising_edge(rx_half_clk);	--SYSCLK);
-  SCI_ACK <= '0';
-  case sci_state is
-    when IDLE =>
-      sci_ch_i        <= x"0";
-      sci_qd_i        <= '0';
-      sci_reg_i       <= '0';
-      sci_read_i      <= '0';
-      sci_write_i     <= '0';
-      sci_timer       <= sci_timer + 1;
-      if SCI_READ = '1' or SCI_WRITE = '1' then
-        sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-        sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-        sci_addr_i    <= SCI_ADDR;
-        sci_data_in_i <= SCI_DATA_IN;
-        sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-        sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-        sci_state     <= SCTRL;
-      elsif sci_timer(sci_timer'left) = '1' then
-        sci_timer     <= (others => '0');
-        sci_state     <= GET_WA;
-      end if;      
-    when SCTRL =>
-      if sci_reg_i = '1' then
-        SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-        SCI_ACK       <= '1';
-        sci_write_i   <= '0';
-        sci_read_i    <= '0';
-        sci_state     <= IDLE;
-      else
-        sci_state     <= SCTRL_WAIT;
-      end if;
-    when SCTRL_WAIT   =>
-      sci_state       <= SCTRL_WAIT2;
-    when SCTRL_WAIT2  =>
-      sci_state       <= SCTRL_FINISH;
-    when SCTRL_FINISH =>
-      SCI_DATA_OUT    <= sci_data_out_i;
-      SCI_ACK         <= '1';
-      sci_write_i     <= '0';
-      sci_read_i      <= '0';
-      sci_state       <= IDLE;
-    
-    when GET_WA =>
-      if cnt = 4 then
-        cnt           := 0;
-        sci_state     <= IDLE;
-      else
-        sci_state     <= GET_WA_WAIT;
-        sci_addr_i    <= '0' & x"22";
-        sci_ch_i      <= x"0";
-        sci_ch_i(cnt) <= '1';
-        sci_read_i    <= '1';
-      end if;
-    when GET_WA_WAIT  =>
-      sci_state       <= GET_WA_WAIT2;
-    when GET_WA_WAIT2 =>
-      sci_state       <= GET_WA_FINISH;
-    when GET_WA_FINISH =>
-      wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-      sci_state       <= GET_WA;    
-      cnt             := cnt + 1;
-  end case;
-  
-  if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-    SCI_NACK <= '1';
-  else
-    SCI_NACK <= '0';
-  end if;
-  
-end process;
-
-
--------------------------------------------------      
--- Debug Registers
--------------------------------------------------            
-debug_reg(3 downto 0)   <= rx_fsm_state;
-debug_reg(4)            <= rx_k;
-debug_reg(5)            <= rx_error;
-debug_reg(6)            <= rx_los_low;
-debug_reg(7)            <= rx_cdr_lol;
-
-debug_reg(8)            <= tx_k;
-debug_reg(9)            <= tx_pll_lol;
-debug_reg(10)           <= lsm_status;
-debug_reg(11)           <= make_link_reset_i;
-debug_reg(15 downto 12) <= tx_fsm_state;
--- debug_reg(31 downto 24) <= tx_data; 
-
-debug_reg(16)           <= '0';
-debug_reg(17)           <= tx_allow;
-debug_reg(18)           <= RESET;
-debug_reg(19)           <= CLEAR;
-debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
-
-debug_reg(35 downto 32) <= wa_position(3 downto 0);
-debug_reg(36)           <= debug_tx_control_i(6);
-debug_reg(39 downto 37) <= "000";
-debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
-
-      
-STAT_DEBUG <= debug_reg;
-
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
-sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK);	-- PL!
-
-STAT_OP(15)		<= send_link_reset_i when rising_edge(SYSCLK);
-STAT_OP(14)		<= '0';
-STAT_OP(13)		<= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset
-STAT_OP(12)		<= tx_pll_lol;	 --'0';
-STAT_OP(11)		<= rx_cdr_lol;	--'0';
-STAT_OP(10)		<= rx_allow;
-STAT_OP(9) 		<= tx_allow;
---STAT_OP(8 downto 4) <= (others => '0');
-STAT_OP(8)		<= got_link_ready_i  when rising_edge(rx_half_clk);
-STAT_OP(7)		<= send_link_reset_i;
-STAT_OP(6)		<= make_link_reset_i;
-STAT_OP(5)		<= request_retr_i;
-STAT_OP(4)		<= start_retr_i;
-STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-end med_ecp3_sfp_sync_up_arch;
\ No newline at end of file
diff --git a/code/soda_4source.vhd b/code/soda_4source.vhd
deleted file mode 100644
index e74e3da..0000000
--- a/code/soda_4source.vhd
+++ /dev/null
@@ -1,409 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_unsigned.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; 
-use work.soda_components.all;
-
-entity soda_4source is
-	port(
-		SYSCLK						: in	std_logic; -- fabric clock
-		SODACLK						: in	std_logic;
-		RESET							: in	std_logic; -- synchronous reset
-		CLEAR							: in	std_logic; -- asynchronous reset
-		CLK_EN						: in	std_logic; 
-
-		SODA_BURST_PULSE_IN		: in	std_logic := '0';	-- 
-		SODA_CYCLE_IN				: in	std_logic := '0';	-- 
-	--	MULTIPLE DUPLEX DOWN-LINKS
-		RX_DLM_IN					: in	t_HUB_BIT;
-		RX_DLM_WORD_IN				: in	t_HUB_BYTE;
-		TX_DLM_OUT					: out	t_HUB_BIT;
-		TX_DLM_WORD_OUT			: out	t_HUB_BYTE;
-		TX_DLM_PREVIEW_OUT		: out	t_HUB_BIT;	--PL!
-		LINK_PHASE_IN				: in	t_HUB_BIT;	--PL!
-
-		SODA_DATA_IN				: in	std_logic_vector(31 downto 0)	:= (others => '0');
-		SODA_DATA_OUT				: out	std_logic_vector(31 downto 0)	:= (others => '0');
-		SODA_ADDR_IN				: in	std_logic_vector(3 downto 0)	:= (others => '0');
-		SODA_READ_IN				: in	std_logic := '0';
-		SODA_WRITE_IN				: in	std_logic := '0';
-		SODA_ACK_OUT				: out	std_logic := '0';
-		LEDS_OUT       		   : out  std_logic_vector(3 downto 0);
-		LINK_DEBUG_IN				: in	std_logic_vector(31 downto 0)	:= (others => '0')
-	);
-end soda_4source;
-
-architecture Behavioral of soda_4source is
-
-	--SODA
-	signal trb_cmd_word_S					: std_logic_vector(30 downto 0)	:= (others => '0');
-	signal trb_cmd_strobe_S					: std_logic := '0';	-- for commands sent over trbnet
-	signal trb_cmd_strobe_sodaclk_S		: std_logic := '0';	-- for commands sent over trbnet
-	signal trb_cmd_pending_S				: std_logic := '0';	
-	signal trb_send_cmd_S					: std_logic := '0';	
-	signal soda_cmd_window_S				: std_logic := '0';
-	signal soda_cmd_pending_S				: std_logic	:= '0';
-	signal start_of_superburst_S			: std_logic := '0';
-	signal super_burst_nr_S					: std_logic_vector(30 downto 0)	:= (others => '0');		-- from super-burst-nr-generator
-	signal soda_reset_S						: std_logic;
-	signal soda_enable_S						: std_logic;
---	signal soda_40mhz_cycle_S				: std_logic := '0';
-	
--- Signals
-	type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
-	signal CURRENT_STATE, NEXT_STATE: STATES;
-
-	signal last_packet_sent_S				: t_PACKET_TYPE_SENT;
-	signal expected_reply_S					: t_HUB_BYTE_ARRAY;
-	signal reply_data_valid_S				: t_HUB_BIT_ARRAY		:= (others => '0');
-	signal reply_OK_S							: t_HUB_BIT_ARRAY		:= (others => '0');
-	signal send_start_calibration_S		: t_HUB_BIT_ARRAY		:= (others => '0');
-	signal start_calibration_S				: t_HUB_BIT_ARRAY		:= (others => '0');
-	signal calib_data_valid_S				: t_HUB_BIT_ARRAY		:= (others => '0');
-	signal calibration_time_S				: t_HUB_WORD_ARRAY	:= (others => (others => '0'));
---	signal calib_register_s					: t_HUB_LWORD_ARRAY	:= (others => (others => '0'));
-	signal reply_timeout_error_S			: t_HUB_BIT_ARRAY		:= (others => '0');
-	signal channel_timeout_status_S		: t_HUB_BIT_ARRAY		:= (others => '0');
-	signal downstream_error_S				: t_HUB_BIT_ARRAY		:= (others => '0');
-	signal report_error_S					: t_HUB_BIT_ARRAY;
-
-	--signal common_reply_timeout_error_S	: std_logic;
-	signal common_timeout_status_S		: std_logic;
-	signal common_downstream_error_S		: std_logic;
-	signal common_report_error_S			: std_logic;
-
-	signal dead_channel_S					: t_HUB_BIT_ARRAY		:= (others => '0');
-
-	signal COMMON_CTRL_STATUS_register_S: std_logic_vector(31 downto 0);
-	signal CTRL_STATUS_register_S			: t_HUB_LWORD_ARRAY;	--	:= (others => (others => '0'));
-	
-	signal TXstart_of_superburst_S		: t_HUB_BIT_ARRAY		:= (others => '0');
-	signal TXsuper_burst_nr_S				: t_HUB_LWORD_ARRAY;		-- from super-burst-nr-generator
-	signal TXsoda_cmd_valid_S				: t_HUB_BIT_ARRAY;
-	signal TXsoda_cmd_window_S				: t_HUB_BIT_ARRAY;
-	signal TXsoda_cmd_word_S				: t_HUB_LWORD_ARRAY;
-	
--- slave bus signals
-	signal bus_ack_x				: std_logic;
-	signal bus_ack					: std_logic;
-	signal store_wr_x				: std_logic;
-	signal store_wr				: std_logic;
-	signal store_rd_x				: std_logic;
-	signal store_rd				: std_logic;
-	signal buf_bus_data_out		: std_logic_vector(31 downto 0)	:= (others => '0');
-
---	debug
---	signal debug_status_S		: std_logic_vector(31 downto 0)	:= (others => '0');
---	signal debug_rx_cnt_S		: std_logic_vector(31 downto 0)	:= (others => '0');
---	signal debug_tx_cnt_S		: std_logic_vector(31 downto 0)	:= (others => '0');
---	signal debug_SOS_cnt_S		: std_logic_vector(31 downto 0)	:= (others => '0');
---	signal debug_cmd_cnt_S		: std_logic_vector(31 downto 0)	:= (others => '0');
-
-begin
-	
-	superburst_gen :  soda_superburst_generator
-		generic map(BURST_COUNT		=> 16)
-		port map(
-			SODACLK						=>	SODACLK,		
-			RESET							=>	soda_reset_S,
-			ENABLE						=>	soda_enable_S,
-			SODA_BURST_PULSE_IN		=>	SODA_BURST_PULSE_IN,
-			START_OF_SUPERBURST_OUT	=>	start_of_superburst_S,
-			SUPER_BURST_NR_OUT		=>	super_burst_nr_S,
-			SODA_CMD_WINDOW_OUT		=> soda_cmd_window_S
-		);
-
-	channel :for i in c_HUB_CHILDREN-1 downto 0 generate
-
-		TXsoda_cmd_valid_S(i)			<= trb_cmd_strobe_S;	--trb_cmd_valid_S;
-		TXsoda_cmd_window_S(i)			<= soda_cmd_window_S;
-		TXstart_of_superburst_S(i)		<= start_of_superburst_S;
-		TXsoda_cmd_word_S(i)				<= '0' & trb_cmd_word_S;
-		TXsuper_burst_nr_S(i)			<= '0' & super_burst_nr_S;
-			
-		start_calibration_S(i)			<= send_start_calibration_S(i);
-
-		packet_builder : soda_packet_builder
-			port map(
-				SODACLK						=>	SODACLK,
-				RESET							=>	RESET,
-				--Internal Connection
-				LINK_PHASE_IN			=>	LINK_PHASE_IN(i),		--link_phase_S,	PL!
-				SODA_CYCLE_IN			=> SODA_CYCLE_IN,
-				SODA_CMD_WINDOW_IN	=> TXsoda_cmd_window_S(i),
-				SODA_CMD_STROBE_IN	=> TXsoda_cmd_valid_S(i),
-				START_OF_SUPERBURST	=> TXstart_of_superburst_S(i),
-				SUPER_BURST_NR_IN		=> TXsuper_burst_nr_S(i)(30 downto 0),
-				SODA_CMD_WORD_IN		=> TXsoda_cmd_word_S(i)(30 downto 0),
-				EXPECTED_REPLY_OUT	=> expected_reply_S(i),
-				SEND_TIME_CAL_OUT		=>	send_start_calibration_S(i),
-				TX_DLM_PREVIEW_OUT	=>	TX_DLM_PREVIEW_OUT(i),
-				TX_DLM_OUT				=> TX_DLM_OUT(i),
-				TX_DLM_WORD_OUT		=> TX_DLM_WORD_OUT(i)
-			);
-			
-		hub_reply_handler : soda_reply_handler
-			port map(
-				SODACLK						=>	SODACLK,
-				RESET							=> RESET,
-				CLEAR							=>	'0',
-				CLK_EN						=>	'1',
-				EXPECTED_REPLY_IN			=> expected_reply_S(i),
-				RX_DLM_IN					=> RX_DLM_IN(i),
-				RX_DLM_WORD_IN				=> RX_DLM_WORD_IN(i),
-				REPLY_VALID_OUT			=> reply_data_valid_S(i),
-				REPLY_OK_OUT				=> reply_OK_S(i)
-			);
-
-		hub_calibration_timer : soda_calibration_timer
-			port map(
-				SODACLK						=>	SODACLK,
-				RESET							=> soda_reset_S,	--RESET,
-				CLEAR							=>	'0',
-				CLK_EN						=>	'1',
-				--Internal Connection
-				START_CALIBRATION			=>	start_calibration_S(i),
-				END_CALIBRATION			=>	reply_data_valid_S(i),
-				VALID_OUT					=>	calib_data_valid_S(i),
-				CALIB_TIME_OUT				=>	calibration_time_S(i),
-				TIMEOUT_ERROR				=>	reply_timeout_error_S(i)
-			);
-			
-		sodahub_calib_timeout_proc  : process(SODACLK)
-		begin
-			if rising_edge(SODACLK) then
-				if( RESET = '1' ) then
-					downstream_error_S(i)					<= '0';
-					channel_timeout_status_S(i)			<= '0';
-					report_error_S(i)							<= '0';
-				elsif (soda_reset_S = '1') then	-- check if slowcontrol wants to reset errors
-					channel_timeout_status_S(i) 			<= '0';
-					downstream_error_S(i)					<= '0';			-- set CALIBRATION_TIMEOUT_ERROR status-bit
-					report_error_S(i)							<= '0';			-- reset REPORT_ERROR status-bit
-				elsif (reply_data_valid_S(i) = '1') then							-- the reply was correct
-					channel_timeout_status_S(i) 			<= '0';
-					if (reply_OK_S(i) = '1') then
-						downstream_error_S(i)				<= '0';
-						report_error_S(i)						<= '0';			-- reset REPORT_ERROR status-bit
-					elsif (dead_channel_S(i) = '0') then
-						downstream_error_S(i)				<= '1';
-						report_error_S(i)						<= '1';			-- set REPORT_ERROR status-bit
-					else
-						downstream_error_S(i)				<= '1';
-						report_error_S(i)						<= '0';			-- reset REPORT_ERROR status-bit
-					end if;
-				elsif (reply_timeout_error_S(i) = '1') then --and  (reply_OK_S(i) = '1')) then
-					if (dead_channel_S(i) = '0') then
-						channel_timeout_status_S(i)		<= '1';
-						report_error_S(i)						<= '1';			-- set REPORT_ERROR status-bit
-					else
-						channel_timeout_status_S(i)		<= '1';
-						report_error_S(i)						<= '0';			-- reset REPORT_ERROR status-bit
-					end if;
-				end if;
-			end if;
-		end process;
-
-		---------------------------------------------------------
-		-- Control bits                                        --
-		---------------------------------------------------------
-		dead_channel_S(i)									<=	CTRL_STATUS_register_S(i)(29);		-- slow-control can declare a channel dead
-		---------------------------------------------------------
-		-- Status bits                                         --
-		---------------------------------------------------------
-		CTRL_STATUS_SYNC: signal_sync
-			generic map(
-				DEPTH => 1,
-				WIDTH => 3
-			)
-			port map(
-				RESET             => RESET,
-				D_IN(0)				=> report_error_S(i),
-				D_IN(1)				=> downstream_error_S(i),
-				D_IN(2)				=> channel_timeout_status_S(i),
-				CLK0					=> SYSCLK,
-				CLK1					=> SODACLK,
-				D_OUT(0)				=> CTRL_STATUS_register_S(i)(15),
-				D_OUT(1)				=> CTRL_STATUS_register_S(i)(1),
-				D_OUT(2)				=> CTRL_STATUS_register_S(i)(0)
-			);
-			
-	--CTRL_STATUS_register_S(i)(15)					<= report_error_S(i);
-	CTRL_STATUS_register_S(i)(14 downto 2)		<= (others => '0');
-	--CTRL_STATUS_register_S(i)(1)					<= downstream_error_S(i);
-	--CTRL_STATUS_register_S(i)(0)					<= channel_timeout_status_S(i);
-
-	end generate;
-
-	soda_reset_S											<= (RESET or COMMON_CTRL_STATUS_register_S(31));
-	soda_enable_S											<= COMMON_CTRL_STATUS_register_S(30);
-	common_downstream_error_S			 				<= '1' when ((downstream_error_S(0)='1') or (downstream_error_S(1)='1') or (downstream_error_S(2)='1') or (downstream_error_S(3)='1'))
-																	else '0';
-	common_report_error_S 								<= '1' when ((report_error_S(0)='1') or (report_error_S(1)='1') or (report_error_S(2)='1') or (report_error_S(3)='1'))
-																	else '0';
-	common_timeout_status_S								<= '1' when ((channel_timeout_status_S(0)='1') or (channel_timeout_status_S(1)='1') or (channel_timeout_status_S(2)='1')) or ((channel_timeout_status_S(3)='1'))
-																	else '0';
-	COMMON_CTRL_STATUS_register_S(15)				<= common_report_error_S;
-	COMMON_CTRL_STATUS_register_S(14 downto 2)	<= (others => '0');
-	COMMON_CTRL_STATUS_register_S(1)					<= common_downstream_error_S;
-	COMMON_CTRL_STATUS_register_S(0)					<= common_timeout_status_S;
-
----------------------------------------------------------
--- RegIO Statemachine
----------------------------------------------------------
-	STATE_MEM: process( SYSCLK)
-	begin
-		if( rising_edge(SYSCLK) ) then
-			if( RESET = '1' ) then
-				CURRENT_STATE <= SLEEP;
-				bus_ack       <= '0';
-				store_wr      <= '0';
-				store_rd      <= '0';
-			else
-				CURRENT_STATE <= NEXT_STATE;
-				bus_ack       <= bus_ack_x;
-				store_wr      <= store_wr_x;
-				store_rd      <= store_rd_x;
-			end if;
-		end if;
-	end process STATE_MEM;
-
--- Transition matrix
-	TRANSFORM: process(CURRENT_STATE, SODA_READ_IN, SODA_WRITE_IN )
-	begin
-		NEXT_STATE <= SLEEP;
-		bus_ack_x  <= '0';
-		store_wr_x <= '0';
-		store_rd_x <= '0';
-		case CURRENT_STATE is
-			when SLEEP    =>
-				if   ( (SODA_READ_IN = '1') ) then
-					NEXT_STATE <= RD_RDY;
-					store_rd_x <= '1';
-				elsif( (SODA_WRITE_IN = '1') ) then
-					NEXT_STATE <= WR_RDY;
-					store_wr_x <= '1';
-				else
-					NEXT_STATE <= SLEEP;
-				end if;
-			when RD_RDY    =>
-				NEXT_STATE <= RD_ACK;
-			when WR_RDY    =>
-				NEXT_STATE <= WR_ACK;
-			when RD_ACK    =>
-				if( SODA_READ_IN = '0' ) then
-					NEXT_STATE <= DONE;
-					bus_ack_x  <= '1';
-				else
-					NEXT_STATE <= RD_ACK;
-					bus_ack_x  <= '1';
-				end if;
-			when WR_ACK    =>
-				if( SODA_WRITE_IN = '0' ) then
-					NEXT_STATE <= DONE;
-					bus_ack_x  <= '1';
-				else
-					NEXT_STATE <= WR_ACK;
-					bus_ack_x  <= '1';
-				end if;
-			when DONE    =>
-				NEXT_STATE <= SLEEP;
-			when others    =>
-				NEXT_STATE <= SLEEP;
-	end case;
-end process TRANSFORM;
-
-
-soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse 
-	port map(
-		IN_CLK		=> SYSCLK,
-		OUT_CLK		=> SODACLK,
-		CLK_EN		=> '1',
-		SIGNAL_IN	=> trb_cmd_strobe_S,
-		PULSE_OUT	=> trb_cmd_strobe_sodaclk_S
-	);
-
----------------------------------------------------------
--- data handling                                       --
----------------------------------------------------------
--- For sim purposes the CLIENT gets addresses 11XX
--- register write
-	THE_WRITE_REG_PROC: process( SYSCLK )
-	begin
-		if( rising_edge(SYSCLK) ) then
-			if   ( RESET = '1' ) then
-				trb_cmd_strobe_S										<= '0';
-				trb_cmd_word_S											<= (others => '0');
-				COMMON_CTRL_STATUS_register_S(31 downto 16)	<= (30 => '1', others => '0');			-- enable soda by default
-				CTRL_STATUS_register_S(0)(31 downto 16)		<= (others => '0');
-				CTRL_STATUS_register_S(1)(31 downto 16)		<= (others => '0');
-				CTRL_STATUS_register_S(2)(31 downto 16)		<= (others => '0');
-				CTRL_STATUS_register_S(3)(31 downto 16)		<= (others => '0');
-			elsif( (store_wr = '1') and (SODA_ADDR_IN = "0000") ) then
-				trb_cmd_strobe_S									<= '1';
-				trb_cmd_word_S										<= SODA_DATA_IN(30 downto 0);
-			elsif( (store_wr = '1') and (SODA_ADDR_IN = "0011") ) then
-				trb_cmd_strobe_S										<= '0';
-				COMMON_CTRL_STATUS_register_S(31 downto 16)	<= SODA_DATA_IN(31 downto 16);		-- use only the 16 lower bits for control
-			elsif( (store_wr = '1') and (SODA_ADDR_IN = "0100") ) then
-				trb_cmd_strobe_S										<= '0';
-				CTRL_STATUS_register_S(0)(31 downto 16)		<= SODA_DATA_IN(31 downto 16);		-- use only the 16 lower bits for control
-			elsif( (store_wr = '1') and (SODA_ADDR_IN = "0101") ) then
-				trb_cmd_strobe_S										<= '0';
-				CTRL_STATUS_register_S(1)(31 downto 16)		<= SODA_DATA_IN(31 downto 16);		-- use only the 16 lower bits for control
-			elsif( (store_wr = '1') and (SODA_ADDR_IN = "0110") ) then
-				trb_cmd_strobe_S										<= '0';
-				CTRL_STATUS_register_S(2)(31 downto 16)		<= SODA_DATA_IN(31 downto 16);		-- use only the 16 lower bits for control
-			elsif( (store_wr = '1') and (SODA_ADDR_IN = "0111") ) then
-				trb_cmd_strobe_S										<= '0';
-				CTRL_STATUS_register_S(3)(31 downto 16)		<= SODA_DATA_IN(31 downto 16);		-- use only the 16 lower bits for control
-			else
-				trb_cmd_strobe_S										<= '0';
-			end if;
-		end if;
-	end process THE_WRITE_REG_PROC;
-
-  
--- register read
-	THE_READ_REG_PROC: process( SYSCLK )
-	begin
-		if( rising_edge(SYSCLK) ) then
-			if   ( RESET = '1' ) then
-				buf_bus_data_out	<= (others => '0');
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "0000") ) then
-				buf_bus_data_out	<= '0' & trb_cmd_word_S;
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "0001") ) then
-				buf_bus_data_out	<= '0' & super_burst_nr_S;
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then
-				buf_bus_data_out		<= COMMON_CTRL_STATUS_register_S;
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then
-				buf_bus_data_out		<= CTRL_STATUS_register_S(0);
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "0101") ) then
-				buf_bus_data_out		<= CTRL_STATUS_register_S(1);
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "0110") ) then
-				buf_bus_data_out		<= CTRL_STATUS_register_S(2);
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "0111") ) then
-				buf_bus_data_out		<= CTRL_STATUS_register_S(3);
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "1000") ) then
-				buf_bus_data_out	<= x"0000" & calibration_time_S(0);
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "1001") ) then
-				buf_bus_data_out	<= x"0000" & calibration_time_S(1);
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "1010") ) then
-				buf_bus_data_out	<= x"0000" & calibration_time_S(2);
-			elsif( (store_rd = '1') and (SODA_ADDR_IN = "1011") ) then
-				buf_bus_data_out	<= x"0000" & calibration_time_S(3);
-			end if;
-		end if;
-	end process THE_READ_REG_PROC;
-
-	LEDS_OUT									<= (others => '0');		--LEDregister_i(3 downto 0);
-  
-	SODA_DATA_OUT							<= buf_bus_data_out;
-	SODA_ACK_OUT 							<= bus_ack;
-
-end architecture;
\ No newline at end of file
diff --git a/code/soda_4source_synconstraints.fdc b/code/soda_4source_synconstraints.fdc
deleted file mode 100644
index c61076d..0000000
--- a/code/soda_4source_synconstraints.fdc
+++ /dev/null
@@ -1,67 +0,0 @@
-################################################################################
-####  This file contains constraints from Synplicity SDC files that have been
-####  translated into Synopsys FPGA Design Constraints (FDC).
-####  Translated FDC output file:
-####  /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-####  client SDC files to the translation:
-####  /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-################################################################################
- 
- 
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/code/soda_hub_synconstraints.fdc
-# Written on Tue May 20 15:36:03 2014
-# by Synplify Pro, I-2013.09L  FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
- 
-################################################################################
-####  The following Synplicity constraints from file:
-####  /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-####  are disabled and have not been translated.
-##############################################################################
-# FDC constraints translated from Synplify Legacy Timing & Design Constraints
-##############################################################################
- 
-set_rtl_ff_names {}
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-define_scope_collection  {all_inputs_fdc} {find -port * -filter @direction==input} -disable
-define_scope_collection  {all_outputs_fdc} {find -port * -filter @direction==output} -disable
-define_scope_collection  {all_clocks_fdc} {find -hier  -clock *} -disable
-define_scope_collection  {all_registers_fdc} {find -hier -seq *} -disable
-###==== END Collections
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock  -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} -add
-create_clock  -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} -add
-create_clock  -name {THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add
-create_clock  -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch0} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -add
-create_clock  -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch1} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch1} -period {5.0} -waveform {0 2.5} -add
-create_clock  -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch2} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch2} -period {5.0} -waveform {0 2.5} -add
-create_clock  -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add
-###==== END Clocks
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-###==== END "Compile Points"
-
-
-
-
-
-
-
-
diff --git a/code/soda_SOB_faker.vhd b/code/soda_SOB_faker.vhd
deleted file mode 100644
index 9296601..0000000
--- a/code/soda_SOB_faker.vhd
+++ /dev/null
@@ -1,51 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use ieee.std_logic_unsigned.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; 
-use work.soda_components.all;
-
-entity soda_start_of_burst_faker is
-	generic(
-		CLOCK_PERIOD			: natural range 1 to 20	:= cSODA_CLOCK_PERIOD;	-- clock-period in ns
-		BURST_PERIOD			: natural 					:= cBURST_PERIOD			-- burst-period in ns
-		);
-	port(
-		SYSCLK					: in	std_logic; -- fabric clock
-		RESET						: in	std_logic; -- synchronous reset
-		SODA_BURST_PULSE_OUT	: out	std_logic := '0'
-		);
-end soda_start_of_burst_faker;
-
-architecture Behavioral of soda_start_of_burst_faker is
-
-	constant	cCLOCKS_PER_BURST			: std_logic_vector(15 downto 0)	:= conv_std_logic_vector((BURST_PERIOD / CLOCK_PERIOD) - 1, 16);
-
-	signal	burst_counter_S			: std_logic_vector(15 downto 0)	:= (others => '0');		-- from super-burst-nr-generator
-	
-
-begin
-
-	burst_pulse_edge_proc : process(SYSCLK)
-	begin
-		if rising_edge(SYSCLK) then
-			if (RESET='1') then
-				burst_counter_S		<= cCLOCKS_PER_BURST;
-				SODA_BURST_PULSE_OUT	<= '0';
-			elsif (burst_counter_S=0) then
-				burst_counter_S		<= cCLOCKS_PER_BURST;
-				SODA_BURST_PULSE_OUT	<= '1';
-			else
-				burst_counter_S		<= burst_counter_S - 1;
-				SODA_BURST_PULSE_OUT	<= '0';
-			end if;
-		end if;
-	end process;
-	
-
-end Behavioral;
diff --git a/code/soda_client_synconstraints.fdc b/code/soda_client_synconstraints.fdc
deleted file mode 100644
index e9ff28d..0000000
--- a/code/soda_client_synconstraints.fdc
+++ /dev/null
@@ -1,66 +0,0 @@
-################################################################################
-####  This file contains constraints from Synplicity SDC files that have been
-####  translated into Synopsys FPGA Design Constraints (FDC).
-####  Translated FDC output file:
-####  /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-####  client SDC files to the translation:
-####  /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-################################################################################
- 
- 
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-# Written on Wed Dec 18 11:52:15 2013
-# by Synplify Pro, G-2012.09L-SP1  FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
- 
-################################################################################
-####  The following Synplicity constraints from file:
-####  /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-####  are disabled and have not been translated.
-##############################################################################
-# FDC constraints translated from Synplify Legacy Timing & Design Constraints
-##############################################################################
- 
-set_rtl_ff_names {}
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-define_scope_collection  {all_inputs_fdc} {find -port * -filter @direction==input} -disable
-define_scope_collection  {all_outputs_fdc} {find -port * -filter @direction==output} -disable
-define_scope_collection  {all_clocks_fdc} {find -hier  -clock *} -disable
-define_scope_collection  {all_registers_fdc} {find -hier -seq *} -disable
-###==== END Collections
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock  -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0}
-create_clock  -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5}
-create_clock  -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5}
-create_clock  -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0}
-create_clock  -name {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5}
-
-
-#create_clock  -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} -period {10.0} -waveform {0 5.0}
-#create_clock  -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} -period {5.0} -waveform {0 2.5}
-set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} }
-set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} }
-#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} }
-#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} }
-###==== END Clocks
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-###==== END "Compile Points"
-
diff --git a/code/soda_clockscaler.vhd b/code/soda_clockscaler.vhd
deleted file mode 100644
index c39057a..0000000
--- a/code/soda_clockscaler.vhd
+++ /dev/null
@@ -1,50 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use ieee.std_logic_unsigned.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; 
-use work.soda_components.all;
-
-entity soda_clockscaler is
-	port(
-		CLK						: in	std_logic; -- fabric clock
-		RESET						: in	std_logic; -- synchronous reset
-		CLOCK_ENABLE_OUT		: out	std_logic := '0';
-		CLOCK_OUT				: out	std_logic := '0'
-		);
-end soda_clockscaler;
-
-architecture Behavioral of soda_clockscaler is
-
-	signal	counter_S			: std_logic_vector(24 downto 0)	:= (others => '0');		-- from super-burst-nr-generator
-	signal	clock_out_S			: std_logic	:= '0';
-
-begin
-
-	CLOCK_OUT	<=	clock_out_S;
-
-	pulse_edge_proc : process(CLK)
-	begin
-		if rising_edge(CLK) then
-			if (RESET='1') then
-				counter_S				<= (others => '1');
-				CLOCK_ENABLE_OUT		<= '0';
-				clock_out_S				<= '0';
-			elsif (counter_S=0) then
-				counter_S				<= (others => '1');
-				CLOCK_ENABLE_OUT		<= '1';
-				clock_out_S				<= not(clock_out_S);				
-			else
-				counter_S				<= counter_S - 1;
-				CLOCK_ENABLE_OUT		<= '0';
-			end if;
-		end if;
-	end process;
-	
-
-end Behavioral;
diff --git a/code/soda_cmd_handler.vhd b/code/soda_cmd_handler.vhd
deleted file mode 100644
index 7944824..0000000
--- a/code/soda_cmd_handler.vhd
+++ /dev/null
@@ -1,170 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; 
-use work.soda_components.all;
-
-entity soda_cmd_handler is
-	port(
-		SODACLK							: in	std_logic; -- fabric clock
-		RESET								: in	std_logic; -- synchronous reset
---		CLEAR								: in	std_logic; -- asynchronous reset
---		CLK_EN							: in	std_logic;
-		--Internal Connection
-		START_OF_SUPERBURST_IN		: in std_logic	:= '0';
-		SUPER_BURST_NR_IN				: in std_logic_vector(30 downto 0) := (others => '0');
-		SODA_CMD_VALID_IN				: out std_logic := '0';
-		SODA_CMD_WORD_IN				: out std_logic_vector(30 downto 0) := (others => '0');
---		EXPECTED_REPLY_OUT			: out	std_logic_vector(7 downto 0) := (others => '0');
-		CRC_VALID_OUT					: out std_logic	:= '0';
-		CRC_DATA_OUT					: out std_logic_vector(7 downto 0) := (others => '0');
-		RX_DLM_IN						: in std_logic;
-		RX_DLM_WORD_IN					: in	std_logic_vector(7 downto 0) := (others => '0')
-	);
-end soda_cmd_handler;
-
-architecture Behavioral of soda_cmd_handler is
-
-	signal	soda_pkt_word_S	: std_logic_vector(31 downto 0) := (others => '0');
-	signal	soda_pkt_valid_S	: std_logic := '0';
-	
-	type		packet_state_type is (	c_RST, c_IDLE, c_ERROR,
-												c_SODA_PKT1, c_SODA_PKT2, c_SODA_PKT3, c_SODA_PKT4,
-												c_SODA_PKT5, c_SODA_PKT6, c_SODA_PKT7, c_SODA_PKT8
-											);
-	signal	packet_state_S				:	packet_state_type := c_IDLE;
-
-begin
-
-	packet_fsm_proc : process(SODACLK)
-	begin
-		if rising_edge(SODACLK) then
-			if (RESET='1') then
-				packet_state_S	<=	c_RST;
-			else
-				case packet_state_S is
-					when c_RST	=>
-						if (RX_DLM_IN='1') then						-- received K28.7 #1
-							packet_state_S	<= c_SODA_PKT1;
-						else
-							packet_state_S	<= c_IDLE;
-						end if;
-					when c_IDLE	=>
-						if (RX_DLM_IN='1') then						-- received K28.7 #1
-							packet_state_S	<= c_SODA_PKT1;
-						else
-							packet_state_S	<= c_IDLE;
-						end if;
-					when c_SODA_PKT1	=>
-						if (RX_DLM_IN='0') then						-- possibly received data-byte
-							packet_state_S	<= c_SODA_PKT2;
-						else
-							packet_state_S	<= c_ERROR;
-						end if;
-					when c_SODA_PKT2	=>
-						if (RX_DLM_IN='1') then						-- received K28.7 #2
-							packet_state_S	<= c_SODA_PKT3;
-						else
-							packet_state_S	<= c_ERROR;
-						end if;
-					when c_SODA_PKT3	=>
-						if (RX_DLM_IN='0') then						-- possibly received data-byte
-							packet_state_S	<= c_SODA_PKT4;
-						else
-							packet_state_S	<= c_ERROR;
-						end if;
-					when c_SODA_PKT4	=>
-						if (RX_DLM_IN='1') then						-- received K28.7 #3
-							packet_state_S	<= c_SODA_PKT5;
-						else
-							packet_state_S	<= c_ERROR;
-						end if;
-					when c_SODA_PKT5	=>
-						if (RX_DLM_IN='0') then						-- possibly received data-byte
-							packet_state_S	<= c_SODA_PKT6;
-						else
-							packet_state_S	<= c_ERROR;
-						end if;
-					when c_SODA_PKT6	=>
-						if (RX_DLM_IN='1') then						-- received K28.7 #4
-							packet_state_S	<= c_SODA_PKT7;
-						else
-							packet_state_S	<= c_ERROR;
-						-- else do nothing
-						end if;
-					when c_SODA_PKT7	=>
-						if (RX_DLM_IN='1') then
-							packet_state_S	<= c_ERROR;	-- if there's an unexpected K28.7 there's too much data
-						else
-							packet_state_S	<= c_SODA_PKT8;
-						end if;
-					when c_SODA_PKT8	=>
-						if (RX_DLM_IN='1') then						-- received K28.7 #4+1... must be another packet coming in....
-							packet_state_S	<= c_SODA_PKT1;
-						else
-							packet_state_S	<= c_IDLE;
-						end if;
-					when c_ERROR	=>
-							packet_state_S	<= c_IDLE;				-- TODO: Insert ERROR_HANDLER
-					when others	=>
-							packet_state_S	<= c_IDLE;
-				end case;
-			end if;
-		end if;
-	end process;
-
-	soda_packet_collector_proc : process(SODACLK, packet_state_S)
-	begin
-		if rising_edge(SODACLK) then
-			case packet_state_S is
-					when c_RST	=>
-						START_OF_SUPERBURST_OUT				<= '0';
-						SODA_CMD_VALID_OUT					<= '0';
-						soda_pkt_valid_S						<= '0';
-						soda_pkt_word_S						<= (others=>'0');
-					when c_IDLE	=>
-						START_OF_SUPERBURST_OUT				<= '0';
-						SODA_CMD_VALID_OUT					<= '0';
-						soda_pkt_valid_S						<= '0';
-						soda_pkt_word_S						<= (others=>'0');
-					when c_SODA_PKT1 	=>
-						START_OF_SUPERBURST_OUT				<= '0';
-						SODA_CMD_VALID_OUT					<= '0';
-						soda_pkt_word_S(31 downto 24)		<=	RX_DLM_WORD_IN;
-					when c_SODA_PKT2	=>
-						-- do nothing -- disregard K28.7
-					when c_SODA_PKT3	=>
-						soda_pkt_word_S(23 downto 16)		<=	RX_DLM_WORD_IN;
-					when c_SODA_PKT4	=>
-						-- do nothing -- disregard K28.7
-					when c_SODA_PKT5	=>
-						soda_pkt_word_S(15 downto 8)		<=	RX_DLM_WORD_IN;
-					when c_SODA_PKT6	=>
-						-- do nothing -- disregard K28.7
-					when c_SODA_PKT7	=>
-						soda_pkt_word_S(7 downto 0)		<=	RX_DLM_WORD_IN;	-- get transmitted CRC
-					when c_SODA_PKT8	=>
-						soda_pkt_valid_S						<= '1';
-						if (soda_pkt_word_S(31)= '1') then
-							START_OF_SUPERBURST_OUT			<= '1';
-							SUPER_BURST_NR_OUT				<= soda_pkt_word_S(30 downto 0);
-						else
-							SODA_CMD_VALID_OUT				<= '1';
-							SODA_CMD_WORD_OUT					<= soda_pkt_word_S(30 downto 0);
-						end if;
-					when others	=>
-						START_OF_SUPERBURST_OUT				<= '0';
-						soda_pkt_valid_S						<= '0';
-						soda_pkt_word_S						<= (others=>'0');
-						SODA_CMD_VALID_OUT					<= '0';
-						SODA_CMD_WORD_OUT						<= (others=>'0');
-			end case;
-			
-		end if;
-	end process;
-
-end architecture;
\ No newline at end of file
diff --git a/code/soda_cmd_window_generator.vhd b/code/soda_cmd_window_generator.vhd
deleted file mode 100644
index cb2acc5..0000000
--- a/code/soda_cmd_window_generator.vhd
+++ /dev/null
@@ -1,60 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use ieee.std_logic_unsigned.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; 
-use work.soda_components.all;
-
-entity soda_cmd_window_generator is
-	generic(		CLOCK_PERIOD			: natural range 1 to 20		:= cSODA_CLOCK_PERIOD;				-- clock-period in ns
-					COMMAND_WINDOS_SIZE	: natural range 1 to 65335 := cSODA_COMMAND_WINDOS_SIZE		-- command window size in ns 
-				);
-	port(
-		SODACLK						: in	std_logic; -- fabric clock
-		RESET							: in	std_logic; -- synchronous reset
-		START_OF_SUPERBURST_IN	: in	std_logic := '0';	-- 
-		SODA_CMD_WINDOW_OUT		: out	std_logic := '0'
-		);
-end soda_cmd_window_generator;
-
-architecture Behavioral of soda_cmd_window_generator is
-
-
-	signal	window_delay_counter_S	: std_logic_vector(7 downto 0)	:= (others => '0');		-- 
-	signal	window_size_counter_S	: std_logic_vector(15 downto 0)	:= (others => '0');		-- 
-	
-
-begin
-
-	
-	soda_cmd_window_proc : process(SODACLK)
-	begin
-		if rising_edge(SODACLK) then
-			if (RESET='1') then
-				window_delay_counter_S	<= (others => '0');
-				window_size_counter_S	<= (others => '0');
-				SODA_CMD_WINDOW_OUT		<= '0';
-			elsif (START_OF_SUPERBURST_IN = '1') then
-				window_delay_counter_S	<= cWINDOW_delay;
-			elsif (window_delay_counter_S > 0) then
-				window_delay_counter_S	<= window_delay_counter_S -1;
-			end if;
-			
-			if (window_delay_counter_S = 1) then
-				window_size_counter_S	<= cCLOCKS_PER_WINDOW;
-			elsif	(window_size_counter_S > 0) then
-				SODA_CMD_WINDOW_OUT		<= '1';
-				window_size_counter_S	<= window_size_counter_S - 1;
-			else
-				SODA_CMD_WINDOW_OUT	<= '0';
-			end if;
-
-		end if;
-	end process;
-
-end Behavioral;
diff --git a/code/soda_hub_synconstraints.fdc b/code/soda_hub_synconstraints.fdc
deleted file mode 100644
index c61076d..0000000
--- a/code/soda_hub_synconstraints.fdc
+++ /dev/null
@@ -1,67 +0,0 @@
-################################################################################
-####  This file contains constraints from Synplicity SDC files that have been
-####  translated into Synopsys FPGA Design Constraints (FDC).
-####  Translated FDC output file:
-####  /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-####  client SDC files to the translation:
-####  /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-################################################################################
- 
- 
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/code/soda_hub_synconstraints.fdc
-# Written on Tue May 20 15:36:03 2014
-# by Synplify Pro, I-2013.09L  FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
- 
-################################################################################
-####  The following Synplicity constraints from file:
-####  /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-####  are disabled and have not been translated.
-##############################################################################
-# FDC constraints translated from Synplify Legacy Timing & Design Constraints
-##############################################################################
- 
-set_rtl_ff_names {}
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-define_scope_collection  {all_inputs_fdc} {find -port * -filter @direction==input} -disable
-define_scope_collection  {all_outputs_fdc} {find -port * -filter @direction==output} -disable
-define_scope_collection  {all_clocks_fdc} {find -hier  -clock *} -disable
-define_scope_collection  {all_registers_fdc} {find -hier -seq *} -disable
-###==== END Collections
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock  -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5} -add
-create_clock  -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0} -add
-create_clock  -name {THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add
-create_clock  -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch0} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5} -add
-create_clock  -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch1} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch1} -period {5.0} -waveform {0 2.5} -add
-create_clock  -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch2} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch2} -period {5.0} -waveform {0 2.5} -add
-create_clock  -name {THE_HUB_SYNC_DOWNLINK/THE_SERDES.rx_full_clk_ch3} {n:THE_HUB_SYNC_UPLINK/THE_SERDES.rx_full_clk_ch3} -period {5.0} -waveform {0 2.5} -add
-###==== END Clocks
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-###==== END "Compile Points"
-
-
-
-
-
-
-
-
diff --git a/code/soda_only_ecp3_sfp_4_sync_down.vhd b/code/soda_only_ecp3_sfp_4_sync_down.vhd
deleted file mode 100644
index 9d51221..0000000
--- a/code/soda_only_ecp3_sfp_4_sync_down.vhd
+++ /dev/null
@@ -1,666 +0,0 @@
---4 channel Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-use IEEE.std_logic_1164.ALL;
-use IEEE.numeric_std.all;
-use IEEE.std_logic_unsigned.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity soda_only_ecp3_sfp_4_sync_down is
-	generic(	SERDES_NUM : integer range 0 to 3 := 0;
-				IS_SYNC_SLAVE   : integer := c_NO);   -- hub downlink is NO slave
-	port(
-		OSC_CLK					: in  std_logic; -- 200 MHz reference clock
-		TX_DATACLK				: in  std_logic; -- 200 MHz data clock
-		SYSCLK					: in  std_logic; -- 100 MHz main clock net, synchronous to OSC clock
-		RESET						: in  std_logic; -- synchronous reset
-		CLEAR						: in  std_logic; -- asynchronous reset
-		---------------------------------------------------------------------------------------------------------------------------------------------------------
---		LINK_DISABLE_IN		: in  std_logic;	-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
-		---------------------------------------------------------------------------------------------------------------------------------------------------------
-		RX_HALF_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --100 MHz
-		RX_FULL_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --200 MHz
-		TX_HALF_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --100 MHz
-		TX_FULL_CLK_OUT		: out std_logic_vector(3 downto 0) := (others => '0');  --200 MHz
-
-		--Sync operation
-		RX_DLM_OUT				: out	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');
-		RX_DLM_WORD_OUT		: out	t_HUB_BYTE;	--std_logic_vector(4*8 - 1 downto 0)	:= (others => '0');
-		TX_DLM_IN				: in	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');
-		TX_DLM_WORD_IN			: in	t_HUB_BYTE;	--std_logic_vector(4*8 - 1 downto 0)	:= (others => '0');
-		TX_DLM_PREVIEW_IN		: in	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');	--PL!
-		LINK_PHASE_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0)			:= (others => '0');	--PL!
-
-		--SFP Connection 
-		SD_RXD_P_IN				: in	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_RXD_N_IN				: in	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_TXD_P_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_TXD_N_OUT			: out	t_HUB_BIT;	--std_logic_vector(3 downto 0);
-		SD_REFCLK_P_IN			: in	t_HUB_BIT;	--std_logic;  --not used
-		SD_REFCLK_N_IN			: in	t_HUB_BIT;	--std_logic;  --not used
-		SD_PRSNT_N_IN			: in	t_HUB_BIT;	--std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		SD_LOS_IN				: in	t_HUB_BIT;	--std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		SD_TXDIS_OUT			: out	t_HUB_BIT;	--std_logic := '0'; -- SFP disable
-		--Control Interface
-		SCI_DATA_IN				: in  std_logic_vector(7 downto 0) := (others => '0');
-		SCI_DATA_OUT			: out std_logic_vector(7 downto 0) := (others => '0');
-		SCI_ADDR					: in  std_logic_vector(8 downto 0) := (others => '0');
-		SCI_READ					: in  std_logic := '0';
-		SCI_WRITE				: in  std_logic := '0';
-		SCI_ACK					: out std_logic := '0';
-		SCI_NACK					: out std_logic := '0'
-	);
-end entity;
-
-
-architecture soda_only_ecp3_sfp_4_sync_down_arch of soda_only_ecp3_sfp_4_sync_down is
-
-  -- Placer Directives
-  attribute HGROUP : string;
-  -- for whole architecture
-  attribute HGROUP of soda_only_ecp3_sfp_4_sync_down_arch : architecture  is "media_downlink_group";
-  attribute syn_sharing : string;
-  attribute syn_sharing of soda_only_ecp3_sfp_4_sync_down_arch : architecture is "off";
-
-
-
-signal clk_200_osc						: std_logic;
-signal clk_200_txdata					: std_logic;
-signal rx_full_clk						: std_logic_vector(3 downto 0);
-signal rx_half_clk						: std_logic_vector(3 downto 0);	
-signal tx_full_clk						: std_logic_vector(3 downto 0);
-signal tx_half_clk						: std_logic_vector(3 downto 0);
-
-type t_tx_state 							is (cRESET,cSEND_IDLE,cSEND_DLM);
-type t_tx_proc_state 					is array(c_HUB_CHILDREN-1 downto 0) of t_tx_state;
-signal tx_proc_state						: t_tx_proc_state;
-
-signal tx_data								: t_HUB_BYTE;	--std_logic_vector(4*8-1 downto 0);
-signal tx_k									: std_logic_vector(3 downto 0);
-signal rx_data								: t_HUB_BYTE;	--std_logic_vector(4*8-1 downto 0);
-signal rx_k									: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_error							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-
-signal rst_n								: t_HUB_BIT;
-signal rst									: t_HUB_BIT;		-- PL!
-signal rx_serdes_rst						: t_HUB_BIT;
-signal tx_serdes_rst						: std_logic; 
-signal tx_pcs_rst							: t_HUB_BIT; 
-signal rx_pcs_rst							: t_HUB_BIT; 
-signal rst_qd								: t_HUB_BIT; 
-signal rst_down_quad						: std_logic; 
-signal serdes_rst_qd						: t_HUB_BIT; 
-signal serdes_rst_down_quad			: std_logic;  	-- combined serdes reset for whole quad
-signal sd_los_i							: t_HUB_BIT; 	--PL!
-
-signal dlm_received_S					: t_HUB_BIT;
-
-
-signal rx_los_low							: t_HUB_BIT; 
-signal lsm_status							: t_HUB_BIT; 
-signal rx_cdr_lol							: t_HUB_BIT; 
-signal tx_pll_lol							: t_HUB_BIT; 
-signal tx_pll_lol_quad					: std_logic; 	-- combined Loss-Of-Lock for whole quad
-
-signal sci_ch_i							: std_logic_vector(3 downto 0);
-signal sci_qd_i							: std_logic;
-signal sci_reg_i							: std_logic;
-signal sci_addr_i							: std_logic_vector(8 downto 0);
-signal sci_data_in_i						: std_logic_vector(7 downto 0);
-signal sci_data_out_i					: std_logic_vector(7 downto 0);
-signal sci_read_i							: std_logic;
-signal sci_write_i						: std_logic;
-signal sci_write_shift_i				: std_logic_vector(2 downto 0);
-signal sci_read_shift_i					: std_logic_vector(2 downto 0);
-
-signal wa_position						: t_HUB_NIBL	:= (others => (others => '1'));	--std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx					: t_HUB_NIBL	:= (others => (others => '1'));	--std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_allow							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal tx_allow_q							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal rx_allow_q							: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal link_phase_S						: t_HUB_BIT;	--std_logic_vector(3 downto 0);	--PL!
-signal request_retr_i					: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal start_retr_i						: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal request_retr_position_i		: t_HUB_BYTE;	--std_logic_vector(7 downto 0);
-signal start_retr_position_i			: t_HUB_BYTE;	--std_logic_vector(7 downto 0);
-signal send_link_reset_i				: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal make_link_reset_i				: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal got_link_ready_i					: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-signal internal_make_link_reset_out	: t_HUB_BIT;	--std_logic_vector(3 downto 0);
-
-signal start_timer						: t_HUB_TIMER19	:= (others => (others => '0'));	--unsigned(18 downto 0)				:= (others => '0');
-
-signal rx_fsm_state						: t_HUB_NIBL;	--std_logic_vector(3 downto 0);
-signal tx_fsm_state						: t_HUB_NIBL;	--std_logic_vector(3 downto 0);
-
-signal stat_rx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal stat_tx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_rx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_tx_control_i				: t_HUB_LWORD;	--std_logic_vector(31 downto 0);
-signal debug_reg							: std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state							: sci_ctrl;
-signal sci_timer							: t_HUB_TIMER13	:= (others => (others => '0'));	--unsigned(12 downto 0)				:= (others => '0');
-
--- fix signal names for constraining
-attribute syn_preserve		: boolean;
-attribute syn_keep			: boolean;
-attribute syn_useioff		: boolean;
-
-attribute syn_useioff	of sd_los_i				: signal is false;		-- do not use an IOFF for this signal
-
-attribute syn_preserve	of sci_ch_i				: signal is true;
-attribute syn_keep		of sci_ch_i				: signal is true;
-attribute syn_preserve	of sci_qd_i				: signal is true;
-attribute syn_keep		of sci_qd_i				: signal is true;
-attribute syn_preserve	of sci_reg_i			: signal is true;
-attribute syn_keep		of sci_reg_i			: signal is true;
-attribute syn_preserve	of sci_addr_i			: signal is true;
-attribute syn_keep		of sci_addr_i			: signal is true;
-attribute syn_preserve	of sci_data_in_i		: signal is true;
-attribute syn_keep		of sci_data_in_i		: signal is true;
-attribute syn_preserve	of sci_data_out_i		: signal is true;
-attribute syn_keep		of sci_data_out_i		: signal is true;
-attribute syn_preserve	of sci_read_i			: signal is true;
-attribute syn_keep		of sci_read_i			: signal is true;
-attribute syn_preserve	of sci_write_i			: signal is true;
-attribute syn_keep		of sci_write_i			: signal is true;
-attribute syn_preserve	of sci_write_shift_i	: signal is true;
-attribute syn_keep		of sci_write_shift_i	: signal is true;
-attribute syn_preserve	of	sci_read_shift_i	: signal is true;
-attribute syn_keep		of sci_read_shift_i	: signal is true;
-
-begin
-
-
---SD_TXDIS_OUT <= not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
-
-clk_200_osc			<= OSC_CLK;			-- This external clock is oscillator/pll generated !!!
-clk_200_txdata		<= TX_DATACLK;		-- This external clock is the rx_full of the uplink !!!
-
-
-gen_clocks	: for i in 0 to 3 generate
-
-	rst(i)					<=		(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i));
-	rst_n(i)					<=		not(CLEAR or sd_los_i(i) or internal_make_link_reset_out(i));
-
-	RX_HALF_CLK_OUT(i)	<= rx_half_clk(i);
-	RX_FULL_CLK_OUT(i)	<= rx_full_clk(i);
-	TX_HALF_CLK_OUT(i)	<= tx_half_clk(i);
-	TX_FULL_CLK_OUT(i)	<= tx_full_clk(i);
-
---	gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate		-- NO WAY IN HELL !! this downlink is a master
---		clk_200_i(i)			<= rx_full_clk(i);
---	end generate;
-
---	gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
---	clk_200_i(i)		<= clk_200_txdata;
---	clk_200_rxdn(i)	<= rx_full_clk(i);	-- These clocks are the rx_full of the DOWNLINKs !!!
---	end generate;
-end generate;
-
--------------------------------------------------  
--- Serdes
-------------------------------------------------- 
-THE_SERDES : entity work.serdes_4_sync_downstream
-	port map(
-	--	CHANNEL0 --	
-		hdinp_ch0				=> SD_RXD_P_IN(0),
-		hdinn_ch0				=> SD_RXD_N_IN(0),
-		hdoutp_ch0				=> SD_TXD_P_OUT(0),
-		hdoutn_ch0				=> SD_TXD_N_OUT(0),
-		rxiclk_ch0				=> clk_200_txdata,
-		sci_sel_ch0				=> sci_ch_i(0),
-		txiclk_ch0				=> clk_200_txdata,
-		rx_full_clk_ch0		=> rx_full_clk(0),
-		rx_half_clk_ch0		=> rx_half_clk(0),
-		tx_full_clk_ch0		=> tx_full_clk(0),
-		tx_half_clk_ch0		=> tx_half_clk(0),
-		fpga_rxrefclk_ch0		=> clk_200_osc,
-		txdata_ch0				=> tx_data(0),
-		tx_k_ch0					=> tx_k(0),
-		tx_force_disp_ch0		=> '0',
-		tx_disp_sel_ch0		=> '0',
-		rxdata_ch0				=> rx_data(0),
-		rx_k_ch0					=> rx_k(0),
-		rx_disp_err_ch0		=> open,
-		rx_cv_err_ch0			=> rx_error(0),
-		rx_serdes_rst_ch0_c  => rx_serdes_rst(0),
-		sb_felb_ch0_c			=> '0',
-		sb_felb_rst_ch0_c		=> '0',
-		tx_pcs_rst_ch0_c		=> tx_pcs_rst(0),
-		tx_pwrup_ch0_c			=> '1',
-		rx_pcs_rst_ch0_c		=> rx_pcs_rst(0),
-		rx_pwrup_ch0_c			=> '1',
-		rx_los_low_ch0_s		=> rx_los_low(0),
-		lsm_status_ch0_s		=> lsm_status(0),
-		rx_cdr_lol_ch0_s		=> rx_cdr_lol(0),
-		tx_div2_mode_ch0_c	=> '0',
-		rx_div2_mode_ch0_c	=> '0',
-	--	CHANNEL1 --	
-		hdinp_ch1				=> SD_RXD_P_IN(1),
-		hdinn_ch1				=> SD_RXD_N_IN(1),
-		hdoutp_ch1				=> SD_TXD_P_OUT(1),
-		hdoutn_ch1				=> SD_TXD_N_OUT(1),
-		rxiclk_ch1				=> clk_200_txdata,
-		sci_sel_ch1				=> sci_ch_i(1),
-		txiclk_ch1				=> clk_200_txdata,
-		rx_full_clk_ch1		=> rx_full_clk(1),
-		rx_half_clk_ch1		=> rx_half_clk(1),
-		tx_full_clk_ch1		=> tx_full_clk(1),
-		tx_half_clk_ch1		=> tx_half_clk(1),
-		fpga_rxrefclk_ch1		=> clk_200_osc,
-		txdata_ch1				=> tx_data(1),
-		tx_k_ch1					=> tx_k(1),
-		tx_force_disp_ch1		=> '0',
-		tx_disp_sel_ch1		=> '0',
-		rxdata_ch1				=> rx_data(1),
-		rx_k_ch1					=> rx_k(1),
-		rx_disp_err_ch1		=> open,
-		rx_cv_err_ch1			=> rx_error(1),
-		rx_serdes_rst_ch1_c  => rx_serdes_rst(1),
-		sb_felb_ch1_c			=> '0',
-		sb_felb_rst_ch1_c		=> '0',
-		tx_pcs_rst_ch1_c		=> tx_pcs_rst(1),
-		tx_pwrup_ch1_c			=> '1',
-		rx_pcs_rst_ch1_c		=> rx_pcs_rst(1),
-		rx_pwrup_ch1_c			=> '1',
-		rx_los_low_ch1_s		=> rx_los_low(1),
-		lsm_status_ch1_s		=> lsm_status(1),
-		rx_cdr_lol_ch1_s		=> rx_cdr_lol(1),
-		tx_div2_mode_ch1_c	=> '0',
-		rx_div2_mode_ch1_c	=> '0',
-	--	CHANNEL2 --	
-		hdinp_ch2				=> SD_RXD_P_IN(2),
-		hdinn_ch2				=> SD_RXD_N_IN(2),
-		hdoutp_ch2				=> SD_TXD_P_OUT(2),
-		hdoutn_ch2				=> SD_TXD_N_OUT(2),
-		rxiclk_ch2				=> clk_200_txdata,
-		sci_sel_ch2				=> sci_ch_i(2),
-		txiclk_ch2				=> clk_200_txdata,
-		rx_full_clk_ch2		=> rx_full_clk(2),
-		rx_half_clk_ch2		=> rx_half_clk(2),
-		tx_full_clk_ch2		=> tx_full_clk(2),
-		tx_half_clk_ch2		=> tx_half_clk(2),
-		fpga_rxrefclk_ch2		=> clk_200_osc,
-		txdata_ch2				=> tx_data(2),
-		tx_k_ch2					=> tx_k(2),
-		tx_force_disp_ch2		=> '0',
-		tx_disp_sel_ch2		=> '0',
-		rxdata_ch2				=> rx_data(2),
-		rx_k_ch2					=> rx_k(2),
-		rx_disp_err_ch2		=> open,
-		rx_cv_err_ch2			=> rx_error(2),
-		rx_serdes_rst_ch2_c  => rx_serdes_rst(2),
-		sb_felb_ch2_c			=> '0',
-		sb_felb_rst_ch2_c		=> '0',
-		tx_pcs_rst_ch2_c		=> tx_pcs_rst(2),
-		tx_pwrup_ch2_c			=> '1',
-		rx_pcs_rst_ch2_c		=> rx_pcs_rst(2),
-		rx_pwrup_ch2_c			=> '1',
-		rx_los_low_ch2_s		=> rx_los_low(2),
-		lsm_status_ch2_s		=> lsm_status(2),
-		rx_cdr_lol_ch2_s		=> rx_cdr_lol(2),
-		tx_div2_mode_ch2_c	=> '0',
-		rx_div2_mode_ch2_c	=> '0',
-	--	CHANNEL3 --	
-		hdinp_ch3				=> SD_RXD_P_IN(3),
-		hdinn_ch3				=> SD_RXD_N_IN(3),
-		hdoutp_ch3				=> SD_TXD_P_OUT(3),
-		hdoutn_ch3				=> SD_TXD_N_OUT(3),
-		rxiclk_ch3				=> clk_200_txdata,
-		sci_sel_ch3				=> sci_ch_i(3),
-		txiclk_ch3				=> clk_200_txdata,
-		rx_full_clk_ch3		=> rx_full_clk(3),
-		rx_half_clk_ch3		=> rx_half_clk(3),
-		tx_full_clk_ch3		=> tx_full_clk(3),
-		tx_half_clk_ch3		=> tx_half_clk(3),
-		fpga_rxrefclk_ch3		=> clk_200_osc,
-		txdata_ch3				=> tx_data(3),
-		tx_k_ch3					=> tx_k(3),
-		tx_force_disp_ch3		=> '0',
-		tx_disp_sel_ch3		=> '0',
-		rxdata_ch3				=> rx_data(3),
-		rx_k_ch3					=> rx_k(3),
-		rx_disp_err_ch3		=> open,
-		rx_cv_err_ch3			=> rx_error(3),
-		rx_serdes_rst_ch3_c  => rx_serdes_rst(3),
-		sb_felb_ch3_c			=> '0',
-		sb_felb_rst_ch3_c		=> '0',
-		tx_pcs_rst_ch3_c		=> tx_pcs_rst(3),
-		tx_pwrup_ch3_c			=> '1',
-		rx_pcs_rst_ch3_c		=> rx_pcs_rst(3),
-		rx_pwrup_ch3_c			=> '1',
-		rx_los_low_ch3_s		=> rx_los_low(3),
-		lsm_status_ch3_s		=> lsm_status(3),
-		rx_cdr_lol_ch3_s		=> rx_cdr_lol(3),
-		tx_div2_mode_ch3_c	=> '0',
-		rx_div2_mode_ch3_c	=> '0',
-	--	COMMON --	
-		sci_wrdata				=> sci_data_in_i,
-		sci_rddata				=> sci_data_out_i,
-		sci_addr					=> sci_addr_i(5 downto 0),
-		sci_sel_quad			=> sci_qd_i,
-		sci_rd					=> sci_read_i,
-		sci_wrn					=> sci_write_i,
-
-		fpga_txrefclk			=> clk_200_txdata,
-		tx_serdes_rst_c		=> '0',	--tx_serdes_rst(0),	-- resets tx_pll	PL 1906
-		tx_pll_lol_qd_s		=> tx_pll_lol_quad,
-		tx_sync_qd_c			=> '0',			-- unused; signal to synchronise channels/serdesses for multi-channel protocols
-		rst_qd_c					=> rst_down_quad,
-		serdes_rst_qd_c		=> serdes_rst_down_quad
-	);
-
--------------------------
--- combined quad reset --
--------------------------
---rst_down_quad				<= '1' when (rst_qd(0)='1' or rst_qd(1)='1' or rst_qd(2)='1' or rst_qd(3)='1') else '0';
-rst_down_quad				<= RESET;	-- PL: 18/06/14
---serdes_rst_down_quad		<= '1' when (serdes_rst_qd(0)='1' or serdes_rst_qd(1)='1' or serdes_rst_qd(2)='1' or serdes_rst_qd(3)='1') else '0';
-serdes_rst_down_quad		<= '0';		-- PL: 23/06/14
-
-generated_logic	: for i in 0 to 3 generate
-
---	SD_TXDIS_OUT(i)			<= LINK_DISABLE_IN;	--not (rx_allow_q(i) or not IS_SLAVE);   --slave only switches on when RX is ready
-	SD_TXDIS_OUT(i)			<= '0';	--not rx_allow_q(i);   --slave only switches on when RX is ready
-
-	tx_pll_lol(i)			<= tx_pll_lol_quad;
-	
-	------------------------------------------------- 
-	-- Reset FSM & Link states
-	------------------------------------------------- 
-	THE_RX_FSM : rx_reset_fsm
-	port map(
-		RST_N						=> rst_n(i),
-		RX_REFCLK				=> rx_full_clk(i),	
-		TX_PLL_LOL_QD_S		=> tx_pll_lol(i),
-		RX_SERDES_RST_CH_C	=> rx_serdes_rst(i),
-		RX_CDR_LOL_CH_S		=> rx_cdr_lol(i),
-		RX_LOS_LOW_CH_S		=> rx_los_low(i),
-		RX_PCS_RST_CH_C		=> rx_pcs_rst(i),
-		WA_POSITION				=> wa_position_rx(i),
-		STATE_OUT				=> rx_fsm_state(i)
-	);
-
-	THE_TX_RESET_FSM : tx_reset_fsm
-	port map(
-		RST_N						=> rst_n(i),
-		TX_REFCLK				=> clk_200_txdata,
-		TX_PLL_LOL_QD_S		=> tx_pll_lol(i),
-		RST_QD_C					=> rst_qd(i),
-		TX_PCS_RST_CH_C		=> tx_pcs_rst(i),
-		STATE_OUT				=> tx_fsm_state(i)
-	);
-	
-
-	-- Master does not do bit-locking    
-	wa_position_rx(i) <= wa_position(i) when (IS_SYNC_SLAVE = c_YES) else x"0";
-
-	
-	PROC_ALLOW : process(clk_200_txdata)	--clk_200_i(i))
-	begin
-		if rising_edge(clk_200_txdata) then	-- clk_200_txdata ??
-			if rx_fsm_state(i) = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(i)(start_timer'left) = '1') then
-				rx_allow(i) <= '1';
-				tx_allow(i) <= '1';
-			else
-				rx_allow(i) <= '0';
-				tx_allow(i) <= '1';
-			end if;
-		end if;
-	end process;
-
-	rx_allow_q(i) <= rx_allow(i) when rising_edge(SYSCLK);
-	tx_allow_q(i) <= tx_allow(i) when rising_edge(SYSCLK);
-
-
-	PROC_START_TIMER : process(clk_200_txdata)	--clk_200_i(i))
-	begin
-		if rising_edge(clk_200_txdata) then
-			if got_link_ready_i(i) = '1' then
-				if start_timer(i)(start_timer'left) = '0' then
-					start_timer(i) <= start_timer(i) + 1;
-				end if;  
-			else
-				start_timer(i) <= (others => '0');
-			end if;
-		end if;
-	end process;
-	------------------------------------------------- 
-	-- TX Data
-	-------------------------------------------------         
-	the_tx_fsm : process(clk_200_txdata)
-	begin
-		if rising_edge(clk_200_txdata) then
-			if (RESET='1') then
-				tx_proc_state(i)	<= cRESET;
-				tx_data(i)			<= x"00"; -- idle
-				tx_k(i)				<= '0';					
-				link_phase_S(i)	<= c_PHASE_L;			
-			else
-				link_phase_S(i)	<= not(link_phase_S(i));			
-				case tx_proc_state(i) is
-					when cSEND_IDLE	=>
-						if (TX_DLM_IN(i)='0') then
-							tx_proc_state(i)	<= cSEND_IDLE;
-							tx_data(i)			<= x"BC"; -- idle
-							tx_k(i)				<= '1';
-						else
-							tx_proc_state(i)	<= cSEND_DLM;
-							tx_data(i)			<= x"DC"; -- dlm
-							tx_k(i)				<= '1';
-						end if;
-					when cSEND_DLM	=>
-						tx_proc_state(i)		<= cSEND_IDLE;
-						tx_data(i)				<= TX_DLM_WORD_IN(i);
-						tx_k(i)					<= '0';
-					when others	=>
-						tx_proc_state(i)		<= cSEND_IDLE;
-						tx_data(i)				<= x"BC"; -- idle
-						tx_k(i)					<= '1';
-				end case;
-			end if;
-		end if;
-	end process;
---	THE_TX : soda_tx_control
---	port map(
---		CLK_200						=> clk_200_txdata,	--tx_full_clk(i),	--clk_200_i(i),
---		CLK_100						=> SYSCLK,
---		RESET_IN						=> rst(i),		--CLEAR, PL!
---
---		TX_DATA_IN					=> (others => '0'),	--	MED_DATA_IN(i),
---		TX_PACKET_NUMBER_IN		=> (others => '0'),	--	MED_PACKET_NUM_IN(i),
---		TX_WRITE_IN					=> '0',					--	MED_DATAREADY_IN(i),
---		TX_READ_OUT					=> open,					--	MED_READ_OUT(i),
---
---		TX_DATA_OUT					=> tx_data(i),
---		TX_K_OUT						=> tx_k(i),
---
---		REQUEST_RETRANSMIT_IN	=> request_retr_i(i),             --TODO
---		REQUEST_POSITION_IN		=> request_retr_position_i(i),    --TODO
---
---		START_RETRANSMIT_IN		=> start_retr_i(i),               --TODO
---		START_POSITION_IN			=> request_retr_position_i(i),    --TODO
---
---		TX_DLM_PREVIEW_IN			=>	TX_DLM_PREVIEW_IN(i),
---		SEND_DLM						=> TX_DLM_IN(i),
---		SEND_DLM_WORD				=> TX_DLM_WORD_IN(i),
---
---		SEND_LINK_RESET_IN		=> '0',	--CTRL_OP(i)(15),
---		TX_ALLOW_IN					=> tx_allow(i),
---		RX_ALLOW_IN					=> rx_allow(i),
---		LINK_PHASE_OUT				=>	link_phase_S(i),		--PL!
---
---		DEBUG_OUT					=> debug_tx_control_i(i),
---		STAT_REG_OUT				=> stat_tx_control_i(i)
---	);
-
-	LINK_PHASE_OUT(i)		<= link_phase_S(i);		--PL!
-	
-
-	-------------------------------------------------      
-	-- RX Data
-	-------------------------------------------------
-	the_rx_proc : process(clk_200_txdata)
-	begin
-		if rising_edge(clk_200_txdata) then
-			RX_DLM_OUT(i)			<= '0';
-			if dlm_received_S(i)='1' then
-				dlm_received_S(i)		<= '0';
-				RX_DLM_OUT(i)			<= '1';
-				RX_DLM_WORD_OUT(i)	<= rx_data(i);
-			elsif (rx_data(i)=x"DC") and (rx_k(i)='1') then
-				dlm_received_S(i)		<= '1';
-			end if;
-		end if;
-	end process;
---	THE_RX_CONTROL : rx_control
---	port map(
---		CLK_200                        => clk_200_txdata,	--clk_200_i(i), --PL!
---		CLK_100                        => SYSCLK,
---		RESET_IN                       => rst(i),		--CLEAR, PL!
---
---		RX_DATA_OUT                    => open,	--	MED_DATA_OUT(i),
---		RX_PACKET_NUMBER_OUT           => open,	--	MED_PACKET_NUM_OUT(i),
---		RX_WRITE_OUT                   => open,	--	MED_DATAREADY_OUT(i),
---		RX_READ_IN                     => '0',		--	MED_READ_IN(i),
---
---		RX_DATA_IN                     => rx_data(i),
---		RX_K_IN                        => rx_k(i),
---
---		REQUEST_RETRANSMIT_OUT         => request_retr_i(i),
---		REQUEST_POSITION_OUT           => request_retr_position_i(i),
---
---		START_RETRANSMIT_OUT           => start_retr_i(i),
---		START_POSITION_OUT             => start_retr_position_i(i),
---
---		--send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
---		RX_DLM                         => RX_DLM_OUT(i),
---		RX_DLM_WORD                    => RX_DLM_WORD_OUT(i),
---
---		SEND_LINK_RESET_OUT            => send_link_reset_i(i),
---		MAKE_RESET_OUT                 => make_link_reset_i(i),
---		RX_ALLOW_IN                    => rx_allow(i),
---		GOT_LINK_READY                 => got_link_ready_i(i),
---
---		DEBUG_OUT                      => debug_rx_control_i(i),
---		STAT_REG_OUT                   => stat_rx_control_i(i)
---	);   
-
-	internal_make_link_reset_out(i)	<= make_link_reset_i(i)	when (IS_SYNC_SLAVE=c_YES) else '0';
-	sd_los_i(i)								<= SD_LOS_IN(i)			when rising_edge(SYSCLK); --PL! 200115
-	
-end generate;    
-    
--------------------------------------------------      
--- SCI
--------------------------------------------------      
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process 
-variable cnt : integer range 0 to 4 := 0;
-begin
-wait until rising_edge(SYSCLK);
-	SCI_ACK <= '0';
-	case sci_state is
-	when IDLE =>
-		sci_ch_i        <= x"0";
-		sci_qd_i        <= '0';
-		sci_reg_i       <= '0';
-		sci_read_i      <= '0';
-		sci_write_i     <= '0';
-		sci_timer(0)    <= sci_timer(0) + 1;
-		sci_timer(1)    <= sci_timer(1) + 1;
-		sci_timer(2)    <= sci_timer(2) + 1;
-		sci_timer(3)    <= sci_timer(3) + 1;
-		if SCI_READ = '1' or SCI_WRITE = '1' then
-			sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_addr_i    <= SCI_ADDR;
-			sci_data_in_i <= SCI_DATA_IN;
-			sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_state     <= SCTRL;
-		else
-			if sci_timer(0)(sci_timer'left) = '1' then
-				sci_timer(0)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(1)(sci_timer'left) = '1' then
-				sci_timer(1)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(2)(sci_timer'left) = '1' then
-				sci_timer(2)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-			if sci_timer(3)(sci_timer'left) = '1' then
-				sci_timer(3)     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;
-		end if;      
-when SCTRL =>
-	if sci_reg_i = '1' then
-		SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-		SCI_ACK       <= '1';
-		sci_write_i   <= '0';
-		sci_read_i    <= '0';
-		sci_state     <= IDLE;
-	else
-		sci_state     <= SCTRL_WAIT;
-	end if;
-when SCTRL_WAIT   =>
-	sci_state       <= SCTRL_WAIT2;
-when SCTRL_WAIT2  =>
-	sci_state       <= SCTRL_FINISH;
-when SCTRL_FINISH =>
-	SCI_DATA_OUT    <= sci_data_out_i;
-	SCI_ACK         <= '1';
-	sci_write_i     <= '0';
-	sci_read_i      <= '0';
-	sci_state       <= IDLE;
-
-when GET_WA =>
-	if cnt = 4 then
-		cnt           := 0;
-		sci_state     <= IDLE;
-	else
-		sci_state     <= GET_WA_WAIT;
-		sci_addr_i    <= '0' & x"22";
-		sci_ch_i      <= x"0";
-		sci_ch_i(cnt) <= '1';
-		sci_read_i    <= '1';
-	end if;
-when GET_WA_WAIT  =>
-	sci_state       <= GET_WA_WAIT2;
-when GET_WA_WAIT2 =>
-	sci_state       <= GET_WA_FINISH;
-when GET_WA_FINISH =>
---		wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-	wa_position(cnt) <= sci_data_out_i(3 downto 0);
-	sci_state       <= GET_WA;    
-	cnt             := cnt + 1;
-end case;
-
-if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-	SCI_NACK <= '1';
-else
-	SCI_NACK <= '0';
-end if;
-
-end process;
-
-
-
-end soda_only_ecp3_sfp_4_sync_down_arch;
diff --git a/code/soda_only_ecp3_sfp_sync_up.vhd b/code/soda_only_ecp3_sfp_sync_up.vhd
deleted file mode 100644
index 03ef5be..0000000
--- a/code/soda_only_ecp3_sfp_sync_up.vhd
+++ /dev/null
@@ -1,543 +0,0 @@
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity soda_only_ecp3_sfp_sync_up is
-	generic(	SERDES_NUM				: integer range 0 to 3 := 0;
-				IS_SYNC_SLAVE			: integer := c_YES);       --select slave mode
-	port(
-		OSCCLK					: in  std_logic; -- 200 MHz reference clock
-		SYSCLK					: in  std_logic; -- 100 MHz main clock net, synchronous to RX clock
-		RESET              : in  std_logic; -- synchronous reset
-		CLEAR              : in  std_logic; -- asynchronous reset
-
-		RX_HALF_CLK_OUT    : out std_logic := '0';  --received 100 MHz
-		RX_FULL_CLK_OUT    : out std_logic := '0';  --received 200 MHz
-		TX_HALF_CLK_OUT    : out std_logic := '0';  --received 100 MHz
-		TX_FULL_CLK_OUT    : out std_logic := '0';  --received 200 MHz
-		RX_CDR_LOL_OUT			: out std_logic := '0';	-- CLOCK_DATA RECOVERY LOSS_OF_LOCK 	!PL14082014
-
-		--Sync operation
-		RX_DLM             : out std_logic := '0';
-		RX_DLM_WORD        : out std_logic_vector(7 downto 0) := x"00";
-		TX_DLM             : in  std_logic := '0';
-		TX_DLM_WORD        : in  std_logic_vector(7 downto 0) := x"00";
-		TX_DLM_PREVIEW_IN		: in std_logic := '0'; --PL!
-		LINK_PHASE_OUT			: out	std_logic := '0';	--PL!
-		LINK_READY_OUT			: out	std_logic := '0';	--PL!
-
-		--SFP Connection
-		SD_RXD_P_IN        : in  std_logic;
-		SD_RXD_N_IN        : in  std_logic;
-		SD_TXD_P_OUT       : out std_logic;
-		SD_TXD_N_OUT       : out std_logic;
-		SD_REFCLK_P_IN     : in  std_logic;  --not used
-		SD_REFCLK_N_IN     : in  std_logic;  --not used
-		SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		SD_TXDIS_OUT       : out  std_logic := '0'; -- SFP disable
-		--Control Interface
-		SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
-		SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
-		SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
-		SCI_READ           : in  std_logic := '0';
-		SCI_WRITE          : in  std_logic := '0';
-		SCI_ACK            : out std_logic := '0';
-		SCI_NACK           : out std_logic := '0'
-	);
-end entity;
-
-
-architecture soda_only_ecp3_sfp_sync_up_arch of soda_only_ecp3_sfp_sync_up is
-
--- Placer Directives
-attribute HGROUP : string;
--- for whole architecture
-attribute HGROUP of soda_only_ecp3_sfp_sync_up_arch : architecture  is "media_uplink_group";
-attribute syn_sharing : string;
-attribute syn_sharing of soda_only_ecp3_sfp_sync_up_arch : architecture is "off";
-
-
-component DCS
--- synthesis translate_off
-generic
-(
-	DCSMODE	: string :="POS"
-);
--- synthesis translate_on
-port (
-CLK0 :in std_logic ;
-CLK1 :in std_logic ;
-SEL :in std_logic ;
-DCSOUT :out std_logic) ;
-end component;
-
-
---signal clk_200_i         : std_logic;
---signal clk_200_internal  : std_logic;
-signal clk_200_osc         : std_logic;
-signal rx_full_clk		: std_logic;
-signal rx_half_clk		: std_logic;
-signal tx_full_clk		: std_logic;
-signal tx_half_clk		: std_logic;
-
-signal tx_data           : std_logic_vector(7 downto 0);
-signal tx_k              : std_logic;
-signal rx_data           : std_logic_vector(7 downto 0);
-signal rx_k              : std_logic;
-signal rx_error          : std_logic;
-
-signal rst_n             : std_logic;
-signal rst						: std_logic;		-- PL!
-signal rx_serdes_rst     : std_logic;
-signal tx_serdes_rst     : std_logic;
-signal tx_pcs_rst        : std_logic;
-signal rx_pcs_rst        : std_logic;
-signal rst_qd            : std_logic;
-signal serdes_rst_qd     : std_logic;
-signal sd_los_i          : std_logic;	--PL!
-
-signal rx_los_low        : std_logic;
-signal lsm_status        : std_logic;
-signal rx_cdr_lol        : std_logic;
-signal tx_pll_lol        : std_logic;
-
-signal sci_ch_i          : std_logic_vector(3 downto 0);
-signal sci_qd_i          : std_logic;
-signal sci_reg_i         : std_logic;
-signal sci_addr_i        : std_logic_vector(8 downto 0);
-signal sci_data_in_i     : std_logic_vector(7 downto 0);
-signal sci_data_out_i    : std_logic_vector(7 downto 0);
-signal sci_read_i        : std_logic;
-signal sci_write_i       : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i  : std_logic_vector(2 downto 0);
-
--- fix signal names for constraining
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
-attribute syn_preserve	of sci_ch_i				: signal is true;
-attribute syn_keep		of sci_ch_i				: signal is true;
-attribute syn_preserve	of sci_qd_i				: signal is true;
-attribute syn_keep		of sci_qd_i				: signal is true;
-attribute syn_preserve	of sci_reg_i			: signal is true;
-attribute syn_keep		of sci_reg_i			: signal is true;
-attribute syn_preserve	of sci_addr_i			: signal is true;
-attribute syn_keep		of sci_addr_i			: signal is true;
-attribute syn_preserve	of sci_data_in_i		: signal is true;
-attribute syn_keep		of sci_data_in_i		: signal is true;
-attribute syn_preserve	of sci_data_out_i		: signal is true;
-attribute syn_keep		of sci_data_out_i		: signal is true;
-attribute syn_preserve	of sci_read_i			: signal is true;
-attribute syn_keep		of sci_read_i			: signal is true;
-attribute syn_preserve	of sci_write_i			: signal is true;
-attribute syn_keep		of sci_write_i			: signal is true;
-attribute syn_preserve	of sci_write_shift_i	: signal is true;
-attribute syn_keep		of sci_write_shift_i	: signal is true;
-attribute syn_preserve	of	sci_read_shift_i	: signal is true;
-attribute syn_keep		of sci_read_shift_i	: signal is true;
-
-signal wa_position        : std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx     : std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow           : std_logic;
-signal rx_allow           : std_logic;
-signal tx_allow_q         : std_logic;
-signal rx_allow_q         : std_logic;
-signal link_phase_S			: std_logic;	--PL!
-signal request_retr_i     : std_logic;
-signal start_retr_i       : std_logic;
-signal request_retr_position_i  : std_logic_vector(7 downto 0);
-signal start_retr_position_i    : std_logic_vector(7 downto 0);
-signal send_link_reset_i  : std_logic;
-signal make_link_reset_i  : std_logic;
-signal got_link_ready_i   : std_logic;
-signal internal_make_link_reset_out : std_logic;
-
-attribute syn_preserve	of	wa_position			: signal is true;
-attribute syn_keep		of wa_position			: signal is true;
-attribute syn_preserve	of	wa_position_rx		: signal is true;
-attribute syn_keep		of wa_position_rx		: signal is true;
-
-signal stat_rx_control_i  : std_logic_vector(31 downto 0);
-signal stat_tx_control_i  : std_logic_vector(31 downto 0);
-signal debug_rx_control_i : std_logic_vector(31 downto 0);
-signal debug_tx_control_i : std_logic_vector(31 downto 0);
-signal rx_fsm_state       : std_logic_vector(3 downto 0);
-signal tx_fsm_state       : std_logic_vector(3 downto 0);
-signal debug_reg          : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state         : sci_ctrl;
-signal sci_timer         : unsigned(12 downto 0) := (others => '0');
-signal start_timer       : unsigned(18 downto 0) := (others => '0');
-signal watchdog_timer	: unsigned(20 downto 0) := (others => '0');
-signal watchdog_trigger	: std_logic :='0';
-
-begin
-
-clk_200_osc			<= OSCCLK;
-
-RX_HALF_CLK_OUT	<= rx_half_clk;
-RX_FULL_CLK_OUT	<= rx_full_clk;
-TX_HALF_CLK_OUT	<= tx_half_clk;
-TX_FULL_CLK_OUT	<= tx_full_clk;
-RX_CDR_LOL_OUT		<= rx_cdr_lol;		-- !PL14082014
-
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
-
-LINK_READY_OUT		<= got_link_ready_i;
-
-
---rst_n <= not CLEAR;	PL!
-rst_n					<= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
-rst					<=		(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
-
-
---gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
---  clk_200_i        <= rx_full_clk;
---end generate;
-
---gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
--- clk_200_i        <= clk_200_internal;
---end generate;
-
-
--------------------------------------------------      
--- Serdes
--------------------------------------------------      
-THE_SERDES : sfp_2_200_int
-  port map(
-    hdinp_ch3            => SD_RXD_P_IN,
-    hdinn_ch3            => SD_RXD_N_IN,
-    hdoutp_ch3           => SD_TXD_P_OUT,
-    hdoutn_ch3           => SD_TXD_N_OUT,
-    txiclk_ch3           => rx_full_clk,
-    rx_full_clk_ch3      => rx_full_clk,
-    rx_half_clk_ch3      => rx_half_clk,
-    tx_full_clk_ch3      => tx_full_clk,
-    tx_half_clk_ch3      => tx_half_clk,
-    fpga_rxrefclk_ch3    => clk_200_osc,
-    txdata_ch3           => tx_data,
-    tx_k_ch3             => tx_k,
-    tx_force_disp_ch3    => '0',
-    tx_disp_sel_ch3      => '0',
-    rxdata_ch3           => rx_data,
-    rx_k_ch3             => rx_k,
-    rx_disp_err_ch3      => open,
-    rx_cv_err_ch3        => rx_error,
-    rx_serdes_rst_ch3_c  => rx_serdes_rst,
-    sb_felb_ch3_c        => '0',
-    sb_felb_rst_ch3_c    => '0',
-    tx_pcs_rst_ch3_c     => tx_pcs_rst,
-    tx_pwrup_ch3_c       => '1',
-    rx_pcs_rst_ch3_c     => rx_pcs_rst,
-    rx_pwrup_ch3_c       => '1',
-    rx_los_low_ch3_s     => rx_los_low,
-    lsm_status_ch3_s     => lsm_status,
-    rx_cdr_lol_ch3_s     => rx_cdr_lol,
-    tx_div2_mode_ch3_c   => '0',
-    rx_div2_mode_ch3_c   => '0',
-    
-    SCI_WRDATA           => sci_data_in_i,
-    SCI_RDDATA           => sci_data_out_i,
-    SCI_ADDR             => sci_addr_i(5 downto 0),
-    SCI_SEL_QUAD         => sci_qd_i,
-    SCI_SEL_ch3          => sci_ch_i(0),
-    SCI_RD               => sci_read_i,
-    SCI_WRN              => sci_write_i,
-    
-    fpga_txrefclk        => rx_full_clk,
-    tx_serdes_rst_c      => tx_serdes_rst,
-    tx_pll_lol_qd_s      => tx_pll_lol,
-    rst_qd_c             => rst_qd,
-    serdes_rst_qd_c      => serdes_rst_qd
-
-    );
-
--------------------------------------------------      
--- Reset FSM & Link states
--------------------------------------------------      
-THE_RX_FSM : rx_reset_fsm
-  port map(
-    RST_N               => rst_n,
-    RX_REFCLK           => clk_200_osc,		-- allways running PL!
-    TX_PLL_LOL_QD_S     => tx_pll_lol,
-    RX_SERDES_RST_CH_C  => rx_serdes_rst,
-    RX_CDR_LOL_CH_S     => rx_cdr_lol,
-    RX_LOS_LOW_CH_S     => rx_los_low,
-    RX_PCS_RST_CH_C     => rx_pcs_rst,
-    WA_POSITION         => wa_position_rx(3 downto 0),
-    STATE_OUT           => rx_fsm_state
-    );
-    
-THE_TX_FSM : tx_reset_fsm
-  port map(
-    RST_N           => rst_n,
-    TX_REFCLK       => clk_200_osc,			-- allways running PL! 18-06 was clk_200_i
-    TX_PLL_LOL_QD_S => tx_pll_lol,
-    RST_QD_C        => rst_qd,
-    TX_PCS_RST_CH_C => tx_pcs_rst,
-    STATE_OUT       => tx_fsm_state
-    );
-
--- Master does not do bit-locking    
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
-
-
---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
-PROC_ALLOW : process begin
-  wait until rising_edge(rx_full_clk);	--clk_200_osc);	--clk_200_i);
-  if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
-    rx_allow <= '1';
-  else
-    rx_allow <= '0';
-  end if;
-  if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
-    tx_allow <= '1';
-  else
-    tx_allow <= '0';
-  end if;
-end process;
-
-rx_allow_q <= rx_allow when rising_edge(rx_half_clk);	--SYSCLK);
-tx_allow_q <= tx_allow when rising_edge(rx_half_clk);	--SYSCLK);
-
-
-PROC_START_TIMER : process(rx_full_clk)	--clk_200_osc)	--clk_200_i)
-begin
-	if rising_edge(rx_full_clk)	then --clk_200_osc) then
-		if got_link_ready_i = '1' then
-			watchdog_timer	<= (others => '0');
-			if start_timer(start_timer'left) = '0' then
-				start_timer <= start_timer + 1;
-			end if;  
-		else
-			start_timer <= (others => '0');
-			if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then
-				watchdog_trigger	<= '1';
-			else 
-				watchdog_trigger	<= '0';
-			end if;
-			if watchdog_trigger = '0' then
-				watchdog_timer	<= watchdog_timer + 1;
-			else 
-				watchdog_timer	<= (others => '0');
-			end if;
-		end if;
-	end if;
-end process;
--------------------------------------------------      
--- TX Data
--------------------------------------------------         
-THE_TX : soda_tx_control
-	port map(
-		CLK_200						=> rx_full_clk,	--clk_200_osc,	--clk_200_i,
-		CLK_100						=> rx_half_clk,	--SYSCLK,
-		RESET_IN						=> rst,		--CLEAR, PL!
-
-		TX_DATA_IN					=> (others => '0'),		--MED_DATA_IN,
-		TX_PACKET_NUMBER_IN		=> (others => '0'),		--MED_PACKET_NUM_IN,
-		TX_WRITE_IN					=> '0',						--MED_DATAREADY_IN,
-		TX_READ_OUT					=> open,						--MED_READ_OUT,
-
-		TX_DATA_OUT					=> tx_data,
-		TX_K_OUT						=> tx_k,
-
-		REQUEST_RETRANSMIT_IN	=> request_retr_i,             --TODO
-		REQUEST_POSITION_IN		=> request_retr_position_i,    --TODO
-
-		START_RETRANSMIT_IN		=> start_retr_i,               --TODO
-		START_POSITION_IN			=> request_retr_position_i,    --TODO
-
-		TX_DLM_PREVIEW_IN			=>	TX_DLM_PREVIEW_IN,
-		SEND_DLM						=> TX_DLM,
-		SEND_DLM_WORD				=> TX_DLM_WORD,
-
-		SEND_LINK_RESET_IN		=> '0',							--CTRL_OP(15),
-		TX_ALLOW_IN					=> tx_allow,
-		RX_ALLOW_IN					=> rx_allow,
-		LINK_PHASE_OUT				=>	link_phase_S,		--PL!
-
-		DEBUG_OUT					=> debug_tx_control_i,
-		STAT_REG_OUT				=> stat_tx_control_i
-);  
-
-LINK_PHASE_OUT		<= link_phase_S;		--PL!
--------------------------------------------------      
--- RX Data
--------------------------------------------------             
-THE_RX_CONTROL : rx_control
-  port map(
-    CLK_200                        => rx_full_clk,	--clk_200_i, PL! 
-    CLK_100                        => rx_half_clk,	--SYSCLK,
-    RESET_IN                       => rst,		--CLEAR, PL!
-
-    RX_DATA_OUT                    => open,		--MED_DATA_OUT,
-    RX_PACKET_NUMBER_OUT           => open,		--MED_PACKET_NUM_OUT,
-    RX_WRITE_OUT                   => open,		--MED_DATAREADY_OUT,
-    RX_READ_IN                     => '0',		--MED_READ_IN,
-
-    RX_DATA_IN                     => rx_data,
-    RX_K_IN                        => rx_k,
-
-    REQUEST_RETRANSMIT_OUT         => request_retr_i,
-    REQUEST_POSITION_OUT           => request_retr_position_i,
-
-    START_RETRANSMIT_OUT           => start_retr_i,
-    START_POSITION_OUT             => start_retr_position_i,
-
-    --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
-    RX_DLM                         => RX_DLM,
-    RX_DLM_WORD                    => RX_DLM_WORD,
-    
-    SEND_LINK_RESET_OUT            => send_link_reset_i,
-    MAKE_RESET_OUT                 => make_link_reset_i,
-    RX_ALLOW_IN                    => rx_allow,
-    GOT_LINK_READY                 => got_link_ready_i,
-
-    DEBUG_OUT                      => debug_rx_control_i,
-    STAT_REG_OUT                   => stat_rx_control_i
-    );   
-    
-    
-    
--------------------------------------------------      
--- SCI
--------------------------------------------------      
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process 
-  variable cnt : integer range 0 to 4 := 0;
-begin
-  wait until rising_edge(rx_half_clk);	--SYSCLK);
-  SCI_ACK <= '0';
-  case sci_state is
-    when IDLE =>
-      sci_ch_i        <= x"0";
-      sci_qd_i        <= '0';
-      sci_reg_i       <= '0';
-      sci_read_i      <= '0';
-      sci_write_i     <= '0';
-      sci_timer       <= sci_timer + 1;
-      if SCI_READ = '1' or SCI_WRITE = '1' then
-        sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-        sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-        sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-        sci_addr_i    <= SCI_ADDR;
-        sci_data_in_i <= SCI_DATA_IN;
-        sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-        sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-        sci_state     <= SCTRL;
-      elsif sci_timer(sci_timer'left) = '1' then
-        sci_timer     <= (others => '0');
-        sci_state     <= GET_WA;
-      end if;      
-    when SCTRL =>
-      if sci_reg_i = '1' then
-        SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-        SCI_ACK       <= '1';
-        sci_write_i   <= '0';
-        sci_read_i    <= '0';
-        sci_state     <= IDLE;
-      else
-        sci_state     <= SCTRL_WAIT;
-      end if;
-    when SCTRL_WAIT   =>
-      sci_state       <= SCTRL_WAIT2;
-    when SCTRL_WAIT2  =>
-      sci_state       <= SCTRL_FINISH;
-    when SCTRL_FINISH =>
-      SCI_DATA_OUT    <= sci_data_out_i;
-      SCI_ACK         <= '1';
-      sci_write_i     <= '0';
-      sci_read_i      <= '0';
-      sci_state       <= IDLE;
-    
-    when GET_WA =>
-      if cnt = 4 then
-        cnt           := 0;
-        sci_state     <= IDLE;
-      else
-        sci_state     <= GET_WA_WAIT;
-        sci_addr_i    <= '0' & x"22";
-        sci_ch_i      <= x"0";
-        sci_ch_i(cnt) <= '1';
-        sci_read_i    <= '1';
-      end if;
-    when GET_WA_WAIT  =>
-      sci_state       <= GET_WA_WAIT2;
-    when GET_WA_WAIT2 =>
-      sci_state       <= GET_WA_FINISH;
-    when GET_WA_FINISH =>
-      wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-      sci_state       <= GET_WA;    
-      cnt             := cnt + 1;
-  end case;
-  
-  if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-    SCI_NACK <= '1';
-  else
-    SCI_NACK <= '0';
-  end if;
-  
-end process;
-
-
--------------------------------------------------      
--- Debug Registers
--------------------------------------------------            
-debug_reg(3 downto 0)   <= rx_fsm_state;
-debug_reg(4)            <= rx_k;
-debug_reg(5)            <= rx_error;
-debug_reg(6)            <= rx_los_low;
-debug_reg(7)            <= rx_cdr_lol;
-
-debug_reg(8)            <= tx_k;
-debug_reg(9)            <= tx_pll_lol;
-debug_reg(10)           <= lsm_status;
-debug_reg(11)           <= make_link_reset_i;
-debug_reg(15 downto 12) <= tx_fsm_state;
--- debug_reg(31 downto 24) <= tx_data; 
-
-debug_reg(16)           <= '0';
-debug_reg(17)           <= tx_allow;
-debug_reg(18)           <= RESET;
-debug_reg(19)           <= CLEAR;
-debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
-
-debug_reg(35 downto 32) <= wa_position(3 downto 0);
-debug_reg(36)           <= debug_tx_control_i(6);
-debug_reg(39 downto 37) <= "000";
-debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
-
-      
---STAT_DEBUG <= debug_reg;
-
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
-sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK);	-- PL!
-
-	--STAT_OP(15)		<= send_link_reset_i when rising_edge(SYSCLK);
-	--STAT_OP(14)		<= '0';
-	--STAT_OP(13)		<= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset
-	--STAT_OP(12)		<= tx_pll_lol;	 --'0';
-	--STAT_OP(11)		<= rx_cdr_lol;	--'0';
-	--STAT_OP(10)		<= rx_allow;
-	--STAT_OP(9) 		<= tx_allow;
-	--STAT_OP(8 downto 4) <= (others => '0');
-	--STAT_OP(8)		<= got_link_ready_i;
-	--STAT_OP(7)		<= send_link_reset_i;
-	--STAT_OP(6)		<= make_link_reset_i;
-	--STAT_OP(5)		<= request_retr_i;
-	--STAT_OP(4)		<= start_retr_i;
-	--STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-end soda_only_ecp3_sfp_sync_up_arch;
diff --git a/code/soda_reply_handler.vhd b/code/soda_reply_handler.vhd
deleted file mode 100644
index b4c3094..0000000
--- a/code/soda_reply_handler.vhd
+++ /dev/null
@@ -1,73 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; 
-use work.soda_components.all;
-
-entity soda_reply_handler is
-	port(
-		SODACLK						: in	std_logic; -- fabric clock
-		RESET							: in	std_logic; -- synchronous reset
-		CLEAR							: in	std_logic; -- asynchronous reset
-		CLK_EN						: in	std_logic;
-		--Internal Connection
-		EXPECTED_REPLY_IN			: in	std_logic_vector(7 downto 0) := (others => '0');
-		RX_DLM_IN					: in	std_logic	:= '0';
-		RX_DLM_WORD_IN				: in	std_logic_vector(7 downto 0)	:= (others => '0');
-		REPLY_VALID_OUT			: out std_logic := '0';
-		REPLY_OK_OUT				: out std_logic := '0'
-	);
-end soda_reply_handler;
-
-architecture Behavioral of soda_reply_handler is
-
-	type		packet_state_type is (	c_RST, c_IDLE, c_ERROR,	c_REPLY, c_DONE);
-	signal	reply_recv_state_S				:	packet_state_type := c_IDLE;
-
-begin
-
-	reply_fsm_proc : process(SODACLK)
-	begin
-		if rising_edge(SODACLK) then
-			if (RESET='1') then
-				REPLY_VALID_OUT					<= '0';
-				REPLY_OK_OUT						<= '0';
-				reply_recv_state_S				<= c_IDLE;
-			else
-				REPLY_VALID_OUT					<= '0';
-				case reply_recv_state_S is
-					when c_IDLE	=>
-						if (RX_DLM_IN='1') then
-							reply_recv_state_S	<= c_REPLY;
-							REPLY_VALID_OUT		<= '1';
-							if (EXPECTED_REPLY_IN = RX_DLM_WORD_IN) then
-								REPLY_OK_OUT		<= '1';
-							else
-								REPLY_OK_OUT		<= '0';
-							end if;
-						end if;
-					when c_REPLY =>
-						REPLY_VALID_OUT			<= '0';
-						REPLY_OK_OUT				<= '0';
-						if (RX_DLM_IN='0') then
-							reply_recv_state_S	<= c_IDLE;
-						else
-							reply_recv_state_S	<= c_ERROR;
-						end if;
-					when c_ERROR	=>
-						reply_recv_state_S		<= c_IDLE;
-						REPLY_OK_OUT				<= '0';
-						REPLY_OK_OUT				<= '0';
-					when others =>
-						reply_recv_state_S		<= c_IDLE;
-						REPLY_OK_OUT				<= '0';
-				end case;
-			end if;
-		end if;
-	end process;
-
-end architecture;
\ No newline at end of file
diff --git a/code/soda_source_clock_constraints.sdc b/code/soda_source_clock_constraints.sdc
deleted file mode 100644
index b224237..0000000
--- a/code/soda_source_clock_constraints.sdc
+++ /dev/null
@@ -1,11 +0,0 @@
-#define_clock {p:CLK_PCLK_LEFT}  -freq 200
-
-#define_clock {n:gen_200_PLL.THE_MAIN_PLL.CLKOP} -name {n:gen_200_PLL.THE_MAIN_PLL.CLKOP} -freq 100
-#define_clock {n:gen_200_PLL.THE_MAIN_PLL.CLKOK} -name {n:gen_200_PLL.THE_MAIN_PLL.CLKOK} -freq 200
-
-# Just to stop the nagging:
-define_clock {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -name {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -freq 100
-define_clock {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -name {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -freq 200
-
-#define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200.THE_SERDES.rx_half_clk_ch1} -freq 100
-#define_clock {n:clk_raw_internal} -name {nn:clk_raw_internal} -freq 200
diff --git a/code/soda_source_syn_translated.fdc b/code/soda_source_syn_translated.fdc
deleted file mode 100644
index e9ff28d..0000000
--- a/code/soda_source_syn_translated.fdc
+++ /dev/null
@@ -1,66 +0,0 @@
-################################################################################
-####  This file contains constraints from Synplicity SDC files that have been
-####  translated into Synopsys FPGA Design Constraints (FDC).
-####  Translated FDC output file:
-####  /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-####  client SDC files to the translation:
-####  /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-################################################################################
- 
- 
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/soda_client/FDC_constraints/soda_client/soda_client_syn_translated.fdc
-# Written on Wed Dec 18 11:52:15 2013
-# by Synplify Pro, G-2012.09L-SP1  FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
- 
-################################################################################
-####  The following Synplicity constraints from file:
-####  /local/lemmens/lattice/soda/client/soda_client_clock_constraints.sdc
-####  are disabled and have not been translated.
-##############################################################################
-# FDC constraints translated from Synplify Legacy Timing & Design Constraints
-##############################################################################
- 
-set_rtl_ff_names {}
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-define_scope_collection  {all_inputs_fdc} {find -port * -filter @direction==input} -disable
-define_scope_collection  {all_outputs_fdc} {find -port * -filter @direction==output} -disable
-define_scope_collection  {all_clocks_fdc} {find -hier  -clock *} -disable
-define_scope_collection  {all_registers_fdc} {find -hier -seq *} -disable
-###==== END Collections
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock  -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10.0} -waveform {0 5.0}
-create_clock  -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5.0} -waveform {0 2.5}
-create_clock  -name {clk_raw_internal} {n:clk_raw_internal} -period {5.0} -waveform {0 2.5}
-create_clock  -name {clk_sys_internal} {n:clk_sys_internal} -period {10.0} -waveform {0 5.0}
-create_clock  -name {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} {n:trb3_periph_sodaclient_reveal_coretop_instance.jtck[0]} -period {5.0} -waveform {0 2.5}
-
-
-#create_clock  -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} -period {10.0} -waveform {0 5.0}
-#create_clock  -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} {n:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} -period {5.0} -waveform {0 2.5}
-set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} }
-set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} }
-#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_full_clk_ch0} }
-#set_clock_groups -derive -asynchronous -name {THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0_async_SDC} -group { {c:THE_SYNC_LINK.THE_SERDES.tx_half_clk_ch0} }
-###==== END Clocks
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-###==== END "Compile Points"
-
diff --git a/code/soda_source_synconstraints.fdc b/code/soda_source_synconstraints.fdc
deleted file mode 100644
index d1ccd96..0000000
--- a/code/soda_source_synconstraints.fdc
+++ /dev/null
@@ -1,48 +0,0 @@
-
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/lemmens/lattice/soda/soda_source/soda_source_synconstraints.fdc
-# Written on Tue Dec  3 18:26:37 2013
-# by Synplify Pro, G-2012.09L-1  FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-###==== END Collections
-
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-create_clock  -name {rx_clk_half} {n:THE_SYNC_LINK.THE_SERDES.rx_half_clk_ch0} -period {10}
-create_clock  -name {rx_clk_full} {n:THE_SYNC_LINK.THE_SERDES.rx_full_clk_ch0} -period {5}
-
-#create_clock  -name {clk_sys_internal} {n:gen_200_PLL\.THE_MAIN_PLL.CLKOP} -period {10}
-#create_clock  -name {serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} -period {10}
-#create_clock  -name {serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} -period {5}
-#set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_0} -group { {c:serdes_sync_downstream|rx_half_clk_ch0_inferred_clock} }
-#set_clock_groups -derive -asynchronous -name {Inferred_clkgroup_1} -group { {c:serdes_sync_downstream|rx_full_clk_ch0_inferred_clock} }
-#set_clock_groups -derive -asynchronous -name {raw_internal} -group { {c:clk_raw_internal} }
-#set_clock_groups -derive -asynchronous -name {sys_internal} -group { {c:clk_sys_internal} }
-###==== END Clocks
-
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-###==== END "Compile Points"
-
-
diff --git a/code/soda_tx_control.vhd b/code/soda_tx_control.vhd
deleted file mode 100644
index 4d07b24..0000000
--- a/code/soda_tx_control.vhd
+++ /dev/null
@@ -1,517 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity soda_tx_control is
-  port(
-    CLK_200									: in  std_logic;
-    CLK_100									: in  std_logic;
-    RESET_IN								: in  std_logic;
-
-    TX_DATA_IN								: in  std_logic_vector(15 downto 0);
-    TX_PACKET_NUMBER_IN					: in  std_logic_vector(2 downto 0);
-    TX_WRITE_IN							: in  std_logic;
-    TX_READ_OUT							: out std_logic;
-
-    TX_DATA_OUT							: out std_logic_vector( 7 downto 0);
-    TX_K_OUT								: out std_logic;
-
-    REQUEST_RETRANSMIT_IN				: in  std_logic := '0';
-    REQUEST_POSITION_IN					: in  std_logic_vector( 7 downto 0) := (others => '0');
-
-    START_RETRANSMIT_IN					: in  std_logic := '0';
-    START_POSITION_IN					: in  std_logic_vector( 7 downto 0) := (others => '0');
-    --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
-    TX_DLM_PREVIEW_IN					: in  std_logic := '0';
-    SEND_DLM								: in  std_logic := '0';
-    SEND_DLM_WORD							: in  std_logic_vector( 7 downto 0) := (others => '0');
-    
-    SEND_LINK_RESET_IN					: in  std_logic := '0';
-    TX_ALLOW_IN							: in  std_logic := '0';
-    RX_ALLOW_IN							: in  std_logic := '0';
-	 LINK_PHASE_OUT						: out std_logic := '0';
-
-    DEBUG_OUT								: out std_logic_vector(31 downto 0);
-    STAT_REG_OUT							: out std_logic_vector(31 downto 0)
-    );
-end entity;
-
-
-
-architecture arch of soda_tx_control is
-
-  attribute syn_hier     : string;
-  attribute syn_hier of arch : architecture is "hard";
-
-	type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H,
-							SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H,
-							SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H);  -- gk 05.10.10
-	signal current_state           : state_t;
-	
-  type ram_t is array(0 to 255) of std_logic_vector(17 downto 0);
-  signal ram                     : ram_t;
-
-	signal	link_phase_S	: std_logic	:= '0';
-
-  signal ram_write               : std_logic := '0';
-  signal ram_write_addr          : unsigned(7 downto 0) := (others => '0');
-  signal ram_read                : std_logic := '0';
-  signal ram_read_addr           : unsigned(7 downto 0) := (others => '0');
-  signal ram_dout                : std_logic_vector(17 downto 0);
-  signal next_ram_dout           : std_logic_vector(17 downto 0);
-  signal ram_fill_level          : unsigned(7 downto 0);
-  signal ram_empty               : std_logic;
-  signal ram_afull               : std_logic;
-
-  signal request_position_q      : std_logic_vector( 7 downto 0);
-  signal restart_position_q      : std_logic_vector( 7 downto 0);
-  signal request_position_i      : std_logic_vector( 7 downto 0);
-  signal restart_position_i      : std_logic_vector( 7 downto 0);
-  signal make_request_i          : std_logic;
-  signal make_restart_i          : std_logic;
-  signal load_read_pointer_i     : std_logic;
---  signal SEND_DLM           : std_logic;
-  signal send_dlm_word_S			: std_logic_vector( 7 downto 0);	--PL!
-  signal send_dlm_i              : std_logic;
-  signal start_retransmit_i      : std_logic;
-  signal request_retransmit_i    : std_logic;
-
-  signal buf_tx_read_out         : std_logic;
-  signal tx_data_200             : std_logic_vector(17 downto 0);
-  signal tx_allow_qtx            : std_logic;
-  signal rx_allow_qtx            : std_logic;
-  signal tx_allow_q              : std_logic;
-  signal send_link_reset_qtx     : std_logic;
-  signal ct_fifo_empty           : std_logic;
-  signal ct_fifo_write           : std_logic := '0';
-  signal ct_fifo_read            : std_logic := '0';
-  signal ct_fifo_full            : std_logic;
-  signal ct_fifo_afull           : std_logic;
-  signal ct_fifo_reset           : std_logic;
-  signal last_ct_fifo_empty      : std_logic;
-  signal last_ct_fifo_read       : std_logic;
-  signal debug_sending_dlm       : std_logic;
-
-  -- gk 05.10.10
-  signal save_sop                : std_logic;
-  signal save_eop                : std_logic;
-  signal load_sop                : std_logic;
-  signal load_eop                : std_logic;
-  signal crc_reset               : std_logic;
-  signal crc_q                   : std_logic_vector(7 downto 0);
-  signal crc_en                  : std_logic;
-  signal crc_data                : std_logic_vector(7 downto 0);
-
-begin
-
-----------------------------------------------------------------------
--- Clock Domain Transfer
-----------------------------------------------------------------------
--- gk 05.10.10
-  THE_CT_FIFO : lattice_ecp3_fifo_18x16_dualport_oreg
-    port map(
-      Data(15 downto 0) => TX_DATA_IN,
-      Data(16)          => save_sop,
-      Data(17)          => save_eop,
-      WrClock           => CLK_100,
-      RdClock           => CLK_200,
-      WrEn              => ct_fifo_write,
-      RdEn              => ct_fifo_read,
-      Reset             => ct_fifo_reset,
-      RPReset           => ct_fifo_reset,
-      Q(17 downto 0)    => tx_data_200,
-      Empty             => ct_fifo_empty,
-      Full              => ct_fifo_full,
-      AlmostFull        => ct_fifo_afull
-      );
-
-  THE_RD_PROC : process(CLK_100)
-    begin
-      if rising_edge(CLK_100) then
-        buf_tx_read_out  <= tx_allow_q  and not ct_fifo_afull ;
-      end if;
-    end process;
-
-  ct_fifo_reset <= not tx_allow_qtx;
-  TX_READ_OUT   <= buf_tx_read_out;
-
-  ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN;
-  ct_fifo_read  <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;
-  
-  last_ct_fifo_read   <= ct_fifo_read  when rising_edge(CLK_200);
-  last_ct_fifo_empty  <= ct_fifo_empty when rising_edge(CLK_200);
-  
-  save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0';
-  save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0';
-
-----------------------------------------------------------------------
--- RAM
-----------------------------------------------------------------------
-
-
-  THE_RAM_WR_PROC : process(CLK_200, RESET_IN)
-    begin
-      if RESET_IN = '1' then
-        ram_write <= '0';
-      elsif rising_edge(CLK_200) then
-        ram_write   <= last_ct_fifo_read and not last_ct_fifo_empty;
-      end if;
-    end process;
-
---RAM
-  THE_RAM_PROC : process(CLK_200)
-    begin
-      if rising_edge(CLK_200) then
-        if ram_write = '1' then
-          ram((to_integer(ram_write_addr))) <= tx_data_200;
-        end if;
-        next_ram_dout <= ram(to_integer(ram_read_addr));
-        ram_dout <= next_ram_dout;
-      end if;
-    end process;
-
---RAM read pointer
-  THE_READ_CNT : process(CLK_200, RESET_IN)
-    begin
-      if RESET_IN = '1' then
-        ram_read_addr <= (others => '0');
-      elsif rising_edge(CLK_200) then
-        if tx_allow_qtx = '0' then
-          ram_read_addr <= (others => '0');
-        elsif load_read_pointer_i = '1' then
-          ram_read_addr <= unsigned(restart_position_i);
-        elsif ram_read = '1' then
-          ram_read_addr <= ram_read_addr + to_unsigned(1,1);
-        end if;
-      end if;
-    end process;
-
---RAM write pointer
-  THE_WRITE_CNT : process(CLK_200, RESET_IN)
-    begin
-      if RESET_IN = '1' then
-        ram_write_addr <= (others => '0');
-      elsif rising_edge(CLK_200) then
-        if tx_allow_qtx = '0' then
-          ram_write_addr <= (others => '0');
-        elsif ram_write = '1' then
-          ram_write_addr <= ram_write_addr + to_unsigned(1,1);
-        end if;
-      end if;
-    end process;
-
-
---RAM fill level counter
-  THE_FILL_CNT : process(CLK_200, RESET_IN)
-    begin
-      if RESET_IN = '1' then
-        ram_fill_level <= (others => '0');
-      elsif rising_edge(CLK_200) then
-        if tx_allow_qtx = '0' then
-          ram_fill_level <= (others => '0');
-        else
-          ram_fill_level <= ram_write_addr - ram_read_addr;
-        end if;
-      end if;
-    end process;
-
-
---RAM empty
---   ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN;
-  ram_empty <= '1' when (ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0';
-  ram_afull <= '1' when ram_fill_level >= 4 else '0';
-
-
-
-----------------------------------------------------------------------
--- TX control state machine
-----------------------------------------------------------------------
-
-  THE_DATA_CONTROL_FSM : process(CLK_200, RESET_IN)
-    begin
-      if rising_edge(CLK_200) then
-        TX_K_OUT               <= '0';
-        debug_sending_dlm      <= '0';
-        case current_state is
-          when SEND_IDLE_L =>
-            TX_DATA_OUT        <= K_IDLE;
-            TX_K_OUT           <= '1';
-            current_state      <= SEND_IDLE_H;
-
-          when SEND_IDLE_H =>
-            if rx_allow_qtx = '1' then
-              TX_DATA_OUT        <= D_IDLE1;
-            else
-              TX_DATA_OUT        <= D_IDLE0;
-            end if;
-
-          when SEND_DATA_L =>
-            TX_DATA_OUT        <= ram_dout(7 downto 0);
-            load_sop           <= ram_dout(16);
-            load_eop           <= ram_dout(17);
-            current_state      <= SEND_DATA_H;
-
-          when SEND_DATA_H =>
-            TX_DATA_OUT        <= ram_dout(15 downto 8);
-
-          when SEND_CHKSUM_L =>
-            TX_DATA_OUT        <= K_EOP;
-            TX_K_OUT           <= '1';
-            load_sop           <= '0';
-            load_eop           <= '0';
-            current_state      <= SEND_CHKSUM_H;
-
-          when SEND_CHKSUM_H =>
-            TX_DATA_OUT        <= crc_q;
-
-          when SEND_START_L =>
-            TX_DATA_OUT        <= K_BGN;
-            TX_K_OUT           <= '1';
-            current_state      <= SEND_START_H;
-
-          when SEND_START_H =>
-            TX_DATA_OUT        <= std_logic_vector(ram_read_addr);
-
-          when SEND_REQUEST_L =>
-            TX_DATA_OUT        <= K_REQ;
-            TX_K_OUT           <= '1';
-            current_state      <= SEND_REQUEST_H;
-
-          when SEND_DLM_L =>
-            TX_DATA_OUT        <= K_DLM;
-            TX_K_OUT           <= '1';
-            current_state      <= SEND_DLM_H;
-            debug_sending_dlm  <= '1';
-				send_dlm_word_S	<=	SEND_DLM_WORD;	--PL!
-          
-          when SEND_DLM_H =>
-            TX_DATA_OUT        <= send_dlm_word_S;	--SEND_DLM_WORD;
-            debug_sending_dlm  <= '1';
-            
-          when SEND_REQUEST_H =>
-            TX_DATA_OUT        <= request_position_i;
-
-          when SEND_RESET =>
-            TX_DATA_OUT        <= K_RST;
-            TX_K_OUT           <= '1';
-            if send_link_reset_qtx = '0' then
-              current_state    <= SEND_IDLE_L;
-            end if;
-
-          when others =>
-            current_state      <= SEND_IDLE_L;
-        end case;
-
-		if	current_state = SEND_START_H		or	current_state = SEND_IDLE_H		or
-			current_state = SEND_DATA_H		or	current_state = SEND_DLM_H			or
-			current_state = SEND_REQUEST_H	or	current_state = SEND_CHKSUM_H
-		then
-			link_phase_S	<= c_PHASE_L;			
-			if tx_allow_qtx = '0' then
-				current_state    <= SEND_IDLE_L;
-			elsif send_link_reset_qtx = '1' then
-				current_state    <= SEND_RESET;
-			elsif make_request_i = '1' then
-				current_state    <= SEND_REQUEST_L;
-			elsif make_restart_i = '1' then
-				current_state    <= SEND_START_L;
-				--				elsif send_dlm_i = '1' then
-			elsif (TX_DLM_PREVIEW_IN='1') then	--PL!
-				current_state    <= SEND_DLM_L;
-			elsif ram_empty = '0' then
-				current_state    <= SEND_DATA_L;
-			else
-				current_state    <= SEND_IDLE_L;
-			end if;
-		else
-			link_phase_S	<= c_PHASE_H;
-		end if;
-	end if;
---------------------------
---async because of oreg.--
---------------------------
-	if	(current_state = SEND_START_H or current_state = SEND_IDLE_H  or current_state = SEND_DATA_H  or
-		current_state = SEND_DLM_H or current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H) and
-		ram_empty = '0' and tx_allow_qtx = '1' and send_link_reset_qtx = '0' and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' then
-			ram_read <= '1';
-	else 
-		ram_read <= '0';
-	end if;
-	
-	if RESET_IN = '1' then
-		ram_read <= '0';
-	end if;
-end process;
-
-LINK_PHASE_OUT		<=	link_phase_S;
-----------------------------------------------------------------------
---
-----------------------------------------------------------------------
-
-tx_allow_qtx        <= TX_ALLOW_IN when rising_edge(CLK_200);
-rx_allow_qtx        <= RX_ALLOW_IN when rising_edge(CLK_200);
-
-send_link_reset_qtx <= SEND_LINK_RESET_IN when rising_edge(CLK_200);
-tx_allow_q          <= tx_allow_qtx when rising_edge(CLK_100);
-
-  THE_RETRANSMIT_PULSE_SYNC_1 : pulse_sync
-    port map(
-      CLK_A_IN        => CLK_100,
-      RESET_A_IN      => RESET_IN,
-      PULSE_A_IN      => REQUEST_RETRANSMIT_IN,
-      CLK_B_IN        => CLK_200,
-      RESET_B_IN      => RESET_IN,
-      PULSE_B_OUT     => request_retransmit_i
-    );
-
-  THE_RETRANSMIT_PULSE_SYNC_2 : pulse_sync
-    port map(
-      CLK_A_IN        => CLK_100,
-      RESET_A_IN      => RESET_IN,
-      PULSE_A_IN      => START_RETRANSMIT_IN,
-      CLK_B_IN        => CLK_200,
-      RESET_B_IN      => RESET_IN,
-      PULSE_B_OUT     => start_retransmit_i
-    );
-
---   THE_RETRANSMIT_PULSE_SYNC_3 : pulse_sync
---     port map(
---       CLK_A_IN        => CLK_100,
---       RESET_A_IN      => RESET_IN,
---       PULSE_A_IN      => SEND_DLM,
---       CLK_B_IN        => CLK_200,
---       RESET_B_IN      => RESET_IN,
---       PULSE_B_OUT     => SEND_DLM
---     );    
---  SEND_DLM <= SEND_DLM;
-    
-  THE_POSITION_REG : process(CLK_100)
-    begin
-      if rising_edge(CLK_100) then
-        if REQUEST_RETRANSMIT_IN = '1' then
-          request_position_q <= REQUEST_POSITION_IN;
-        end if;
-        if START_RETRANSMIT_IN = '1' then
-          restart_position_q <= START_POSITION_IN;
-        end if;
-      end if;
-    end process;
-
-
---Store Request Retransmit position
-  THE_STORE_REQUEST_PROC : process(CLK_200, RESET_IN)
-    begin
-      if RESET_IN = '1' then
-        make_request_i <= '0';
-        request_position_i <= (others => '0');
-      elsif rising_edge(CLK_200) then
-        if tx_allow_qtx = '0' then
-          make_request_i     <= '0';
-          request_position_i <= (others => '0');
-        elsif request_retransmit_i = '1' then
-          make_request_i     <= '1';
-          request_position_i <= request_position_q;
-        elsif current_state = SEND_REQUEST_L then
-          make_request_i     <= '0';
-        elsif current_state = SEND_REQUEST_H then
-          request_position_i <= (others => '0');
-        end if;
-      end if;
-    end process;
-
-
---Store Restart position
-  THE_STORE_RESTART_PROC : process(CLK_200, RESET_IN)
-    begin
-      if RESET_IN = '1' then
-        make_restart_i           <= '0';
-        restart_position_i       <= (others => '0');
-      elsif rising_edge(CLK_200) then
-        if tx_allow_qtx = '0' then
-          make_restart_i         <= '0';
-          restart_position_i     <= (others => '0');
-        elsif start_retransmit_i = '1' then
-          make_restart_i         <= '1';
-          restart_position_i     <= restart_position_q;
-        elsif current_state = SEND_START_L then
-          make_restart_i         <= '0';
-        elsif current_state = SEND_START_H then
-          restart_position_i     <= (others => '0');
-        end if;
-      end if;
-    end process;
-
---Store DLM position
-	THE_STORE_DLM_PROC : process(CLK_200, RESET_IN)
-		begin
-			if RESET_IN = '1' then
-				send_dlm_i           <= '0';
-			elsif rising_edge(CLK_200) then
-				if tx_allow_qtx = '0' then
-					send_dlm_i         <= '0';
-				elsif SEND_DLM = '1' then
-					send_dlm_i         <= '1';
---				elsif current_state = SEND_DLM_L then		-- PL!
-				else
-					send_dlm_i         <= '0';
-				end if;
-			end if;
-	end process;    
-    
-  load_read_pointer_i    <= '1' when current_state = SEND_START_L else '0';
-
-  -- gk 05.10.10
-  crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_CHKSUM_H) or (current_state = SEND_START_H)) else '0';
-  crc_en    <= '1' when ((current_state = SEND_DATA_L) or (current_state = SEND_DATA_H)) else '0';
-  crc_data  <= ram_dout(15 downto 8) when (current_state = SEND_DATA_H) else ram_dout(7 downto 0);
-
-  -- gk 05.10.10
-  CRC_CALC : trb_net_CRC8
-    port map(
-      CLK       => CLK_200,
-      RESET     => crc_reset,
-      CLK_EN    => crc_en,
-      DATA_IN   => crc_data,
-      CRC_OUT   => crc_q,
-      CRC_match => open
-      );
-
-
-----------------------------------------------------------------------
--- Debug
-----------------------------------------------------------------------
-  DEBUG_OUT(0) <= ram_read;
-  DEBUG_OUT(1) <= ct_fifo_write;
-  DEBUG_OUT(2) <= ct_fifo_read;
-  DEBUG_OUT(3) <= tx_allow_qtx;
-  DEBUG_OUT(4) <= ram_empty;
-  DEBUG_OUT(5) <= ram_afull;
-  DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200);
-  DEBUG_OUT(31 downto 7) <= (others => '0');
-
-  process(CLK_100)
-    begin
-      if rising_edge(CLK_100) then
-        STAT_REG_OUT(7 downto 0)   <= std_logic_vector(ram_fill_level);
-        STAT_REG_OUT(15 downto 8)  <= std_logic_vector(ram_read_addr);
-        STAT_REG_OUT(16)           <= ram_afull;
-        STAT_REG_OUT(17)           <= ram_empty;
-        STAT_REG_OUT(18)           <= tx_allow_qtx;
-        STAT_REG_OUT(19)           <= TX_ALLOW_IN;
-        STAT_REG_OUT(20)           <= make_restart_i;
-        STAT_REG_OUT(21)           <= make_request_i;
-        STAT_REG_OUT(22)           <= load_eop;
-        STAT_REG_OUT(31 downto 23) <= (others => '0');
-      end if;
-    end process;
-
-
-
-
-end architecture;
\ No newline at end of file
diff --git a/code/trb3_periph_EP_soda4source.vhd b/code/trb3_periph_EP_soda4source.vhd
deleted file mode 100644
index 768e594..0000000
--- a/code/trb3_periph_EP_soda4source.vhd
+++ /dev/null
@@ -1,760 +0,0 @@
----------------
--- TOP LEVEL --
----------------
--- TAB=3 !!
--- 24/11/2014
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use ieee.std_logic_unsigned.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all; 
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_ep_soda4source is 
- generic(
- SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_TRB_INTERFACES : integer := 1
- );
-	port	(
-		--Clocks 
-		CLK_GPLL_LEFT			: in std_logic; --Clock Manager 1/(2468), 125 MHz
-		CLK_GPLL_RIGHT			: in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
-		CLK_PCLK_LEFT			: in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-		CLK_PCLK_RIGHT			: in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- 
-		--serdes I/O - connect as you like, no real use
-		SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
-		SERDES_ADDON_RX      : in  std_logic_vector(15 downto 0);
-
-		--Inter-FPGA Communication
-		FPGA5_COMM				: inout std_logic_vector(11 downto 0);	--Bit 0/1 input, serial link RX active
-																			--Bit 2/3 output, serial link TX active
-																			--others yet undefined
-	  --Connection to AddOn
-	 LED_LINKOK					: out std_logic_vector(6 downto 1);
-	 LED_RX						: out std_logic_vector(6 downto 1); 
-	 LED_TX						: out std_logic_vector(6 downto 1);
-	 SFP_MOD0					: in  std_logic_vector(6 downto 1);
-	 SFP_TXDIS					: out std_logic_vector(6 downto 1); 
-	 SFP_LOS						: in  std_logic_vector(6 downto 1);
-
-		--Flash ROM & Reboot
-		FLASH_CLK				: out	std_logic;
-		FLASH_CS					: out	std_logic;
-		FLASH_DIN				: out	std_logic;
-		FLASH_DOUT				: in	std_logic;
-		PROGRAMN					: out	std_logic; --reboot FPGA
-
-		--Misc
-		TEMPSENS					: inout	std_logic; --Temperature Sensor
-		CODE_LINE				: in	std_logic_vector(1 downto 0);
-		LED_GREEN				: out	std_logic;
-		LED_ORANGE				: out	std_logic;
-		LED_RED					: out	std_logic;
-		LED_YELLOW				: out	std_logic;
-		--Test Connectors
-		TEST_LINE	 			: out std_logic_vector(15 downto 0)			:= (others => '0')
-	);
-	attribute syn_useioff	: boolean;
-	--no IO-FF for LEDs relaxes timing constraints
-	attribute syn_useioff of LED_GREEN		: signal is false;
-	attribute syn_useioff of LED_ORANGE		: signal is false;
-	attribute syn_useioff of LED_RED			: signal is false;
-	attribute syn_useioff of LED_YELLOW		: signal is false;
-	attribute syn_useioff of TEMPSENS		: signal is false;
-	attribute syn_useioff of PROGRAMN		: signal is false;
-	attribute syn_useioff of CODE_LINE		: signal is false;
---	attribute syn_useioff of LED_LINKOK		: signal is false;
---	attribute syn_useioff of LED_TX			: signal is false;
---	attribute syn_useioff of LED_RX			: signal is false;
---	attribute syn_useioff of SFP_MOD0		: signal is false;
---	attribute syn_useioff of SFP_TXDIS		: signal is false;
---	attribute syn_useioff of SFP_LOS			: signal is false;
-	attribute syn_useioff of TEST_LINE		: signal is false;
-	--important signals _with_ IO-FF
-	attribute syn_useioff of FLASH_CLK		: signal is true;
-	attribute syn_useioff of FLASH_CS		: signal is true;
-	attribute syn_useioff of FLASH_DIN		: signal is true;
-	attribute syn_useioff of FLASH_DOUT		: signal is true;
-	attribute syn_useioff of FPGA5_COMM		: signal is true;
-end trb3_periph_EP_soda4source;
-
-architecture trb3_periph_EP_soda4source_arch of trb3_periph_EP_soda4source is
-	--Constants
-	constant REGIO_NUM_STAT_REGS	: integer := 0;
-	constant REGIO_NUM_CTRL_REGS	: integer := 2;
-
-	attribute syn_keep				: boolean;
-	attribute syn_preserve			: boolean;
-
-	constant USE_200_MHZ				: integer := 1 - USE_125_MHZ;	-- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
-	--Clock / Reset
-	signal pll_lock					: std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
-	signal clear_i						: std_logic	:= '1';
-	signal reset_i						: std_logic	:= '1';
-	signal GSR_N						: std_logic	:= '0';
-
-	signal clk_100_osc				: std_logic;
-	signal clk_200_osc				: std_logic;
-	signal time_counter_S			: std_logic_vector(31 downto 0);
-	--Media Interface
-	signal med_stat_op				: std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
-	signal med_ctrl_op				: std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
-	signal med_stat_debug			: std_logic_vector(NUM_TRB_INTERFACES*64-1 downto 0);
---	signal med_ctrl_debug			: std_logic_vector(NUM_TRB_INTERFACES*64-1 downto 0);
-	signal med_data_out				: std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
-	signal med_packet_num_out		: std_logic_vector(NUM_TRB_INTERFACES* 3-1 downto 0);
-	signal med_dataready_out		: std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
-	signal med_read_out				: std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
-	signal med_data_in				: std_logic_vector(NUM_TRB_INTERFACES*16-1 downto 0);
-	signal med_packet_num_in		: std_logic_vector(NUM_TRB_INTERFACES* 3-1 downto 0);
-	signal med_dataready_in			: std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
-	signal med_read_in				: std_logic_vector(NUM_TRB_INTERFACES* 1-1 downto 0);
-
-	--Slow Control channel
---	signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-	signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-	signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-	signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
-	signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
-	signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
-	--RegIO
---	signal my_address             : std_logic_vector(15 downto 0);
-	signal regio_addr_out         : std_logic_vector(15 downto 0);
-	signal regio_read_enable_out  : std_logic;
-	signal regio_write_enable_out : std_logic;
-	signal regio_data_out         : std_logic_vector(31 downto 0);
-	signal regio_data_in          : std_logic_vector(31 downto 0);
-	signal regio_dataready_in     : std_logic;
-	signal regio_no_more_data_in  : std_logic;
-	signal regio_write_ack_in     : std_logic;
-	signal regio_unknown_addr_in  : std_logic;
-	signal regio_timeout_out      : std_logic;
-
-	--Timer
-	signal global_time         : std_logic_vector(31 downto 0);
-	signal local_time          : std_logic_vector(7 downto 0);
-	signal time_since_last_trg : std_logic_vector(31 downto 0);
-	signal timer_ticks         : std_logic_vector(1 downto 0);
-
-	--Flash
-	signal spimem_read_en          : std_logic;
-	signal spimem_write_en         : std_logic;
-	signal spimem_data_in          : std_logic_vector(31 downto 0);
-	signal spimem_addr             : std_logic_vector(8 downto 0);
-	signal spimem_data_out         : std_logic_vector(31 downto 0);
-	signal spimem_dataready_out    : std_logic;
-	signal spimem_no_more_data_out : std_logic;
-	signal spimem_unknown_addr_out : std_logic;
-	signal spimem_write_ack_out    : std_logic;
-
--- SCI for the uplink
-	signal sci1_ack					: std_logic;
-	signal sci1_write					: std_logic;
-	signal sci1_read					: std_logic;
-	signal sci1_data_in				: std_logic_vector(7 downto 0);
-	signal sci1_data_out				: std_logic_vector(7 downto 0);
-	signal sci1_addr					: std_logic_vector(8 downto 0);  
--- SCI for the downlink
-	signal sci2_ack					: std_logic;
-	signal sci2_nack					: std_logic;
-	signal sci2_write					: std_logic;
-	signal sci2_read					: std_logic;
-	signal sci2_data_in				: std_logic_vector(7 downto 0);
-	signal sci2_data_out				: std_logic_vector(7 downto 0);
-	signal sci2_addr					: std_logic_vector(8 downto 0);
-
-	signal sfp_txdis_S				: std_logic_vector(6 downto 1) := (others => '1'); 
-
-	--SODA
-	signal soda_ack				: std_logic;
-	signal soda_nack			: std_logic;
-	signal soda_write			: std_logic;
-	signal soda_read			: std_logic;
-	signal soda_data_in			: std_logic_vector(31 downto 0);
-	signal soda_data_out		: std_logic_vector(31 downto 0);
-	signal soda_addr			: std_logic_vector(3 downto 0);  
-	signal soda_leds			: std_logic_vector(3 downto 0);  
-
-	--SODA downlink
-	signal rx_half_clk			: t_HUB_BIT;
-	signal rx_full_clk			: t_HUB_BIT;
-	signal tx_half_clk			: t_HUB_BIT;
-	signal tx_full_clk			: t_HUB_BIT;
-	  
-	signal tx_dlm_i				: t_HUB_BIT;
-	signal rx_dlm_i				: t_HUB_BIT;
-	signal tx_dlm_word			: t_HUB_BYTE;
-	signal rx_dlm_word			: t_HUB_BYTE;
-	signal tx_dlm_preview_S		: t_HUB_BIT;	--PL!
-	signal link_phase_S			: t_HUB_BIT;	--PL!
-
-	signal link_debug_in_S		: std_logic_vector(31 downto 0);
-	
-	--SODA
-	signal SOB_S							: std_logic := '0';
-	signal soda_40mhz_cycle_S			: std_logic := '0';
-	
-  	-- fix signal names for constraining
-	attribute syn_keep			of GSR_N					: signal is true;
-	attribute syn_preserve		of GSR_N					: signal is true;
-	attribute syn_preserve		of rx_full_clk				: signal is true;
-	attribute syn_keep			of rx_full_clk				: signal is true;
-	attribute syn_preserve		of rx_half_clk				: signal is true;
-	attribute syn_keep			of rx_half_clk				: signal is true;
-	attribute syn_preserve		of tx_full_clk				: signal is true;
-	attribute syn_keep			of tx_full_clk				: signal is true;
-	attribute syn_preserve		of tx_half_clk				: signal is true;
-	attribute syn_keep			of tx_half_clk				: signal is true;
-	attribute syn_preserve		of clk_100_osc				: signal is true;
-	attribute syn_keep			of clk_100_osc				: signal is true;
-	attribute syn_preserve		of clk_200_osc				: signal is true;
-	attribute syn_keep			of clk_200_osc				: signal is true;
-	attribute syn_preserve		of tx_dlm_i					: signal is true;
-	attribute syn_keep			of tx_dlm_i					: signal is true;
-	attribute syn_preserve		of rx_dlm_i					: signal is true;
-	attribute syn_keep			of rx_dlm_i					: signal is true;
-	attribute syn_preserve		of soda_40mhz_cycle_S	: signal is true;
-	attribute syn_keep			of soda_40mhz_cycle_S	: signal is true;
-
-
-begin
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
-	THE_MAIN_PLL : pll_in200_out100
-		port map(
-			CLK	=> CLK_GPLL_RIGHT,
-			CLKOP	=> clk_100_osc,
-			CLKOK	=> clk_200_osc,
-			LOCK	=> pll_lock
-		);
-end generate; 
-
---  GSR_N <= pll_lock;
-
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-	THE_RESET_HANDLER : trb_net_reset_handler
-		generic map(
-						RESET_DELAY => x"FEEE"
-						)
-		port map(
-			CLEAR_IN			=> '0',					-- reset input (high active, async)
-			CLEAR_N_IN		=> '1',					-- reset input (low active, async)
-			CLK_IN			=> clk_200_osc,			-- raw master clock, NOT from PLL/DLL!
-			SYSCLK_IN		=> clk_100_osc,			-- PLL/DLL remastered clock
-			PLL_LOCKED_IN	=> pll_lock,				-- master PLL lock signal (async)
-			RESET_IN			=> '0',					-- general reset signal (SYSCLK)
-			TRB_RESET_IN	=> '0',	--med_stat_op(13),	-- TRBnet reset signal (SYSCLK)
-			CLEAR_OUT		=> clear_i,				-- async reset out, USE WITH CARE!
-			RESET_OUT		=> reset_i,				-- synchronous reset out (SYSCLK)
-			DEBUG_OUT		=> open
-		);
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
-THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
-	generic map(
-		SERDES_NUM	=> 1, --number of serdes in quad
-		EXT_CLOCK	=> c_NO, --use internal clock
-		USE_200_MHZ	=> USE_200_MHZ, --run on 200 MHz clock
-		USE_125_MHZ	=> USE_125_MHZ,
-		USE_CTC		=> c_NO,
-		USE_SLAVE	=> SYNC_MODE
-	)
-	port map(
-		CLK		=> clk_200_osc,
-		SYSCLK					=> clk_100_osc,
-		RESET						=> reset_i,
-		CLEAR						=> clear_i,
-		CLK_EN					=> '1',
-		--Internal Connection
-		MED_DATA_IN				=> med_data_out(15 downto 0),
-		MED_PACKET_NUM_IN		=> med_packet_num_out(2 downto 0),
-		MED_DATAREADY_IN		=> med_dataready_out(0),
-		MED_READ_OUT			=> med_read_in(0),
-		MED_DATA_OUT			=> med_data_in(15 downto 0),
-		MED_PACKET_NUM_OUT	=> med_packet_num_in(2 downto 0),
-		MED_DATAREADY_OUT		=> med_dataready_in(0),
-		MED_READ_IN				=> med_read_out(0),
-		REFCLK2CORE_OUT		=> open,
-		CLK_RX_HALF_OUT		=> open,
-		CLK_RX_FULL_OUT		=> open,
-	 
-		--SFP Connection
-		SD_RXD_P_IN				=> SERDES_ADDON_RX(4),
-		SD_RXD_N_IN				=> SERDES_ADDON_RX(5),
-		SD_TXD_P_OUT			=> SERDES_ADDON_TX(4),
-		SD_TXD_N_OUT			=> SERDES_ADDON_TX(5),
-		SD_REFCLK_P_IN			=> '0',
-		SD_REFCLK_N_IN			=> '0',
-		SD_PRSNT_N_IN			=> FPGA5_COMM(0),
-		SD_LOS_IN				=> FPGA5_COMM(0),
-		SD_TXDIS_OUT			=> FPGA5_COMM(2),
-
-		SCI_DATA_IN				=> sci1_data_in,
-		SCI_DATA_OUT			=> sci1_data_out,
-		SCI_ADDR					=> sci1_addr,
-		SCI_READ					=> sci1_read,
-		SCI_WRITE				=> sci1_write,
-		SCI_ACK					=> sci1_ack, 
-		-- Status and control port
-		STAT_OP					=> med_stat_op(15 downto 0),
-		CTRL_OP					=> med_ctrl_op(15 downto 0),
-		STAT_DEBUG				=> med_stat_debug(63 downto 0),
-		CTRL_DEBUG				=> (others => '0')
-	);
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
---		USE_CHANNEL									=> (c_YES,c_YES,c_NO,c_YES),
-		REGIO_NUM_STAT_REGS						=> REGIO_NUM_STAT_REGS, --4, --16 stat reg
-		REGIO_NUM_CTRL_REGS						=> REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
-		ADDRESS_MASK								=> x"FFFF",
-		BROADCAST_BITMASK							=> x"FF",
-		BROADCAST_SPECIAL_ADDR					=> x"45",
-		REGIO_COMPILE_TIME						=> std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
-		REGIO_HARDWARE_VERSION					=> x"9100b000",
-		REGIO_INIT_ADDRESS						=> x"f358",
-		REGIO_USE_VAR_ENDPOINT_ID				=> c_YES,
-		CLOCK_FREQUENCY							=> CLOCK_FREQUENCY,
-		TIMING_TRIGGER_RAW						=> c_YES,
-		--Configure data handler
-		DATA_INTERFACE_NUMBER					=> 1,
-		DATA_BUFFER_DEPTH							=> 9, --13
-		DATA_BUFFER_WIDTH							=> 32,
-		DATA_BUFFER_FULL_THRESH					=> 256,
-		TRG_RELEASE_AFTER_DATA					=> c_YES,
-		HEADER_BUFFER_DEPTH						=> 9,
-		HEADER_BUFFER_FULL_THRESH				=> 256
- )
- port map(
-		CLK											=> clk_100_osc,
-		RESET											=> reset_i,
-		CLK_EN										=> '1',
-		MED_DATAREADY_OUT							=> med_dataready_out(0),
-		MED_DATA_OUT								=> med_data_out,
-		MED_PACKET_NUM_OUT						=> med_packet_num_out,
-		MED_READ_IN									=> med_read_in(0),
-		MED_DATAREADY_IN							=> med_dataready_in(0),
-		MED_DATA_IN									=> med_data_in,
-		MED_PACKET_NUM_IN							=> med_packet_num_in,
-		MED_READ_OUT								=> med_read_out(0),
-		MED_STAT_OP_IN								=> med_stat_op,
-		MED_CTRL_OP_OUT							=> med_ctrl_op,
-
-		--Timing trigger in
-		TRG_TIMING_TRG_RECEIVED_IN	=> '0',
-		--LVL1 trigger to FEE
-		LVL1_TRG_DATA_VALID_OUT					=> open,
-		LVL1_VALID_TIMING_TRG_OUT				=> open,
-		LVL1_VALID_NOTIMING_TRG_OUT			=> open,
-		LVL1_INVALID_TRG_OUT						=> open,
-
-		LVL1_TRG_TYPE_OUT							=> open,
-		LVL1_TRG_NUMBER_OUT						=> open,
-		LVL1_TRG_CODE_OUT							=> open,
-		LVL1_TRG_INFORMATION_OUT				=> open,
-		LVL1_INT_TRG_NUMBER_OUT					=> open,
-
-		--Information about trigger handler errors
-		TRG_MULTIPLE_TRG_OUT						=> open,
-		TRG_TIMEOUT_DETECTED_OUT				=> open,
-		TRG_SPURIOUS_TRG_OUT						=> open,
-		TRG_MISSING_TMG_TRG_OUT					=> open,
-		TRG_SPIKE_DETECTED_OUT					=> open,
-
-		--Response from FEE
-		FEE_TRG_RELEASE_IN(0)					=> '1',
-		FEE_TRG_STATUSBITS_IN					=> (others => '0'),
-		FEE_DATA_IN									=> (others => '0'),
-		FEE_DATA_WRITE_IN(0)						=> '0',
-		FEE_DATA_FINISHED_IN(0)					=> '1',
-		FEE_DATA_ALMOST_FULL_OUT(0)			=> open,
-
-		-- Slow Control Data Port
-		REGIO_COMMON_STAT_REG_IN				=> (others => '0'),		--common_stat_reg, --0x00 because it is floating
-		REGIO_COMMON_CTRL_REG_OUT				=> common_ctrl_reg, --0x20
-		REGIO_COMMON_STAT_STROBE_OUT			=> common_stat_reg_strobe,
-		REGIO_COMMON_CTRL_STROBE_OUT			=> common_ctrl_reg_strobe,
-		REGIO_STAT_REG_IN							=> stat_reg, --start 0x80
-		REGIO_CTRL_REG_OUT						=> ctrl_reg, --start 0xc0
-		REGIO_STAT_STROBE_OUT					=> stat_reg_strobe,
-		REGIO_CTRL_STROBE_OUT					=> ctrl_reg_strobe,
-		REGIO_VAR_ENDPOINT_ID(1 downto 0)	=> CODE_LINE,
-		REGIO_VAR_ENDPOINT_ID(15 downto 2)	=> (others => '0'),
-
-		BUS_ADDR_OUT								=> regio_addr_out,
-		BUS_READ_ENABLE_OUT						=> regio_read_enable_out,
-		BUS_WRITE_ENABLE_OUT						=> regio_write_enable_out,
-		BUS_DATA_OUT								=> regio_data_out,
-		BUS_DATA_IN									=> regio_data_in,
-		BUS_DATAREADY_IN							=> regio_dataready_in,
-		BUS_NO_MORE_DATA_IN						=> regio_no_more_data_in,
-		BUS_WRITE_ACK_IN							=> regio_write_ack_in,
-		BUS_UNKNOWN_ADDR_IN						=> regio_unknown_addr_in,
-		BUS_TIMEOUT_OUT							=> regio_timeout_out,
-		ONEWIRE_INOUT								=> TEMPSENS,
-		ONEWIRE_MONITOR_OUT						=> open,
-
-		TIME_GLOBAL_OUT							=> global_time,
-		TIME_LOCAL_OUT								=> local_time,
-		TIME_SINCE_LAST_TRG_OUT					=> time_since_last_trg,
-		TIME_TICKS_OUT								=> timer_ticks,
-
-		STAT_DEBUG_IPU								=> open,
-		STAT_DEBUG_1								=> open,
-		STAT_DEBUG_2								=> open,
-		STAT_DEBUG_DATA_HANDLER_OUT			=> open,
-		STAT_DEBUG_IPU_HANDLER_OUT				=> open,
-		STAT_TRIGGER_OUT							=> open,
-		CTRL_MPLEX									=> (others => '0'),
-		IOBUF_CTRL_GEN								=> (others => '0'),
-		STAT_ONEWIRE								=> open,
-		STAT_ADDR_DEBUG							=> open,
-		DEBUG_LVL1_HANDLER_OUT					=> open
-		);
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
- )
- port map(
-		CLK											=> clk_100_osc,
-		RESET											=> reset_i,
-	
-		DAT_ADDR_IN									=> regio_addr_out,
-		DAT_DATA_IN									=> regio_data_out,
-		DAT_DATA_OUT								=> regio_data_in,
-		DAT_READ_ENABLE_IN						=> regio_read_enable_out,
-		DAT_WRITE_ENABLE_IN						=> regio_write_enable_out,
-		DAT_TIMEOUT_IN								=> regio_timeout_out,
-		DAT_DATAREADY_OUT							=> regio_dataready_in,
-		DAT_WRITE_ACK_OUT							=> regio_write_ack_in,
-		DAT_NO_MORE_DATA_OUT						=> regio_no_more_data_in,
-		DAT_UNKNOWN_ADDR_OUT						=> regio_unknown_addr_in,
-
-		BUS_READ_ENABLE_OUT(0)					=> spimem_read_en,
-		BUS_READ_ENABLE_OUT(1)					=> sci1_read,
-		BUS_READ_ENABLE_OUT(2)					=> sci2_read,
-		BUS_READ_ENABLE_OUT(3)					=> soda_read,
-
-		BUS_WRITE_ENABLE_OUT(0)					=> spimem_write_en,
-		BUS_WRITE_ENABLE_OUT(1)					=> sci1_write,
-		BUS_WRITE_ENABLE_OUT(2)					=> sci2_write,
-		BUS_WRITE_ENABLE_OUT(3)					=> soda_write,
-
-		BUS_DATA_OUT(0*32+31 downto 0*32)	=> spimem_data_in,
-		BUS_DATA_OUT(1*32+7 downto 1*32)		=> sci1_data_in,
-		BUS_DATA_OUT(1*32+31 downto 1*32+8)	=> open,
-		BUS_DATA_OUT(2*32+7 downto 2*32)		=> sci2_data_in,
-		BUS_DATA_OUT(2*32+31 downto 2*32+8)	=> open,
-		BUS_DATA_OUT(3*32+31 downto 3*32)	=> soda_data_in,
-
-		BUS_ADDR_OUT(0*16+8 downto 0*16)		=> spimem_addr,
-		BUS_ADDR_OUT(0*16+15 downto 0*16+9)	=> open,
-		BUS_ADDR_OUT(1*16+8 downto 1*16)		=> sci1_addr,
-		BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
-		BUS_ADDR_OUT(2*16+8 downto 2*16) 	=> sci2_addr,
-		BUS_ADDR_OUT(2*16+15 downto 2*16+9)	=> open,
-		BUS_ADDR_OUT(3*16+3 downto 3*16)		=> soda_addr,
-		BUS_ADDR_OUT(3*16+15 downto 3*16+4)	=> open,
-
-		BUS_TIMEOUT_OUT(0)						=> open,
-		BUS_TIMEOUT_OUT(1)						=> open,
-		BUS_TIMEOUT_OUT(2)						=> open,
-		BUS_TIMEOUT_OUT(3)						=> open,
-
-		BUS_DATA_IN(0*32+31 downto 0*32)		=> spimem_data_out,
-		BUS_DATA_IN(1*32+7 downto 1*32)		=> sci1_data_out,
-		BUS_DATA_IN(1*32+31 downto 1*32+8)	=> open,
-		BUS_DATA_IN(2*32+7 downto 2*32)		=> sci2_data_out,
-		BUS_DATA_IN(2*32+31 downto 2*32+8)	=> open,
-		BUS_DATA_IN(3*32+31 downto 3*32)		=> soda_data_out,
-
-		BUS_DATAREADY_IN(0)						=> spimem_dataready_out,
-		BUS_DATAREADY_IN(1)						=> sci1_ack,
-		BUS_DATAREADY_IN(2)						=> sci2_ack,
-		BUS_DATAREADY_IN(3)						=> soda_ack,
-
-		BUS_WRITE_ACK_IN(0)						=> spimem_write_ack_out,
-		BUS_WRITE_ACK_IN(1)						=> sci1_ack,
-		BUS_WRITE_ACK_IN(2)						=> sci2_ack,
-		BUS_WRITE_ACK_IN(3)						=> soda_ack,
-
-		BUS_NO_MORE_DATA_IN(0)					=> spimem_no_more_data_out,
-		BUS_NO_MORE_DATA_IN(1)					=> '0',
-		BUS_NO_MORE_DATA_IN(2)					=> '0',
-		BUS_NO_MORE_DATA_IN(3)					=> '0',
-
-		BUS_UNKNOWN_ADDR_IN(0)					=> spimem_unknown_addr_out,
-		BUS_UNKNOWN_ADDR_IN(1)					=> '0',
-		BUS_UNKNOWN_ADDR_IN(2)					=> '0',
-		BUS_UNKNOWN_ADDR_IN(3)					=> '0',
-
-		STAT_DEBUG									=> open
-		);
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : spi_flash_and_fpga_reload	--.flash_reboot_arch
-	port map(
-		CLK_IN							=> clk_100_osc,
-		RESET_IN							=> reset_i,
-
-		BUS_ADDR_IN						=> spimem_addr,
-		BUS_READ_IN						=> spimem_read_en,
-		BUS_WRITE_IN					=> spimem_write_en,
-		BUS_DATAREADY_OUT				=> spimem_dataready_out,
-		BUS_WRITE_ACK_OUT				=> spimem_write_ack_out,
-		BUS_UNKNOWN_ADDR_OUT			=> spimem_unknown_addr_out,
-		BUS_NO_MORE_DATA_OUT			=> spimem_no_more_data_out,
-		BUS_DATA_IN						=> spimem_data_in,
-		BUS_DATA_OUT					=> spimem_data_out,
-
-		DO_REBOOT_IN					=> common_ctrl_reg(15), 
-		PROGRAMN							=> PROGRAMN,
-
-		SPI_CS_OUT						=> FLASH_CS,
-		SPI_SCK_OUT						=> FLASH_CLK,
-		SPI_SDO_OUT						=> FLASH_DIN,
-		SPI_SDI_IN						=> FLASH_DOUT
-	);
-
----------------------------------------------------------------------------
--- The synchronous quad-downlink interface for Soda
----------------------------------------------------------------------------      
-
-MED_ECP3_SODA_QUAD_SOURCE : med_ecp3_sfp_4_soda
-	generic map(
-		SERDES_NUM										=> 0, --number of serdes (for trb) in quad
-		IS_SYNC_SLAVE									=> c_NO
-		)
-	port map(
-		OSC_CLK											=> clk_200_osc,
-		TX_DATACLK										=> clk_200_osc,
-		SYSCLK											=> clk_100_osc,	-- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
-		RESET												=> reset_i,
-		CLEAR												=> clear_i,
-		---------------------------------------------------------------------------------------------------------------------------------------------------------
---				LINK_DISABLE_IN								=> sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
-		---------------------------------------------------------------------------------------------------------------------------------------------------------
-		RX_HALF_CLK_OUT(0)							=> rx_half_clk(0),
-		RX_HALF_CLK_OUT(1)							=> rx_half_clk(1),
-		RX_HALF_CLK_OUT(2)							=> rx_half_clk(2),
-		RX_HALF_CLK_OUT(3)							=> rx_half_clk(3),
-
-		RX_FULL_CLK_OUT(0)							=> rx_full_clk(0),	-- needed for sync replies i.e. calibration
-		RX_FULL_CLK_OUT(1)							=> rx_full_clk(1),	-- needed for sync replies i.e. calibration
-		RX_FULL_CLK_OUT(2)							=> rx_full_clk(2),	-- needed for sync replies i.e. calibration
-		RX_FULL_CLK_OUT(3)							=> rx_full_clk(3),	-- needed for sync replies i.e. calibration
-
-		TX_HALF_CLK_OUT(0)							=> tx_half_clk(0),
-		TX_HALF_CLK_OUT(1)							=> tx_half_clk(1),
-		TX_HALF_CLK_OUT(2)							=> tx_half_clk(2),
-		TX_HALF_CLK_OUT(3)							=> tx_half_clk(3),
-
-		TX_FULL_CLK_OUT(0)							=> tx_full_clk(0),
-		TX_FULL_CLK_OUT(1)							=> tx_full_clk(1),
-		TX_FULL_CLK_OUT(2)							=> tx_full_clk(2),
-		TX_FULL_CLK_OUT(3)							=> tx_full_clk(3),
-
-		RX_DLM_OUT(0)									=> rx_dlm_i(0),
-		RX_DLM_OUT(1)									=> rx_dlm_i(1),
-		RX_DLM_OUT(2)									=> rx_dlm_i(2),
-		RX_DLM_OUT(3)									=> rx_dlm_i(3),
-		
-		RX_DLM_WORD_OUT(0)							=> rx_dlm_word(0),
-		RX_DLM_WORD_OUT(1)							=> rx_dlm_word(1),
-		RX_DLM_WORD_OUT(2)							=> rx_dlm_word(2),
-		RX_DLM_WORD_OUT(3)							=> rx_dlm_word(3),
-		
-		TX_DLM_IN(0)									=> tx_dlm_i(0),
-		TX_DLM_IN(1)									=> tx_dlm_i(1),
-		TX_DLM_IN(2)									=> tx_dlm_i(2),
-		TX_DLM_IN(3)									=> tx_dlm_i(3),
-		
-		TX_DLM_WORD_IN(0)								=> tx_dlm_word(0),
-		TX_DLM_WORD_IN(1)								=> tx_dlm_word(1),
-		TX_DLM_WORD_IN(2)								=> tx_dlm_word(2),
-		TX_DLM_WORD_IN(3)								=> tx_dlm_word(3),
-
-		TX_DLM_PREVIEW_IN(0)							=> tx_dlm_preview_S(0),			--PL!
-		TX_DLM_PREVIEW_IN(1)							=> tx_dlm_preview_S(1),			--PL!
-		TX_DLM_PREVIEW_IN(2)							=> tx_dlm_preview_S(2),			--PL!
-		TX_DLM_PREVIEW_IN(3)							=> tx_dlm_preview_S(3),			--PL!
-
-		LINK_PHASE_OUT(0)								=>	link_phase_S(0),				--PL!
-		LINK_PHASE_OUT(1)								=>	link_phase_S(1),				--PL!
-		LINK_PHASE_OUT(2)								=>	link_phase_S(2),				--PL!
-		LINK_PHASE_OUT(3)								=>	link_phase_S(3),				--PL!
-
-		--SFP Connection
-		SD_RXD_P_IN(0)									=> SERDES_ADDON_RX(0),			-- B0
-		SD_RXD_P_IN(1)									=> SERDES_ADDON_RX(1),
-		SD_RXD_P_IN(2)									=> SERDES_ADDON_RX(10),			-- B1
-		SD_RXD_P_IN(3)									=> SERDES_ADDON_RX(11),	
-		SD_RXD_N_IN(0)									=> SERDES_ADDON_RX(2),			-- B2
-		SD_RXD_N_IN(1)									=> SERDES_ADDON_RX(3),
-		SD_RXD_N_IN(2)									=> SERDES_ADDON_RX(6),			-- B3
-		SD_RXD_N_IN(3)									=> SERDES_ADDON_RX(7),
-		SD_TXD_P_OUT(0)								=> SERDES_ADDON_TX(0),			-- B0
-		SD_TXD_P_OUT(1)								=> SERDES_ADDON_TX(1),
-		SD_TXD_P_OUT(2)								=> SERDES_ADDON_TX(10),			-- B1
-		SD_TXD_P_OUT(3)								=> SERDES_ADDON_TX(11),
-		SD_TXD_N_OUT(0)								=> SERDES_ADDON_TX(2),			-- B2
-		SD_TXD_N_OUT(1)								=> SERDES_ADDON_TX(3),
-		SD_TXD_N_OUT(2)								=> SERDES_ADDON_TX(6),			-- B3
-		SD_TXD_N_OUT(3)								=> SERDES_ADDON_TX(7),
-		SD_REFCLK_P_IN									=> (others => '0'),
-		SD_REFCLK_N_IN									=> ('0','0','0','0'),
-		SD_PRSNT_N_IN(0)								=> SFP_MOD0(1),
-		SD_PRSNT_N_IN(1)								=> SFP_MOD0(6),
-		SD_PRSNT_N_IN(2)								=> SFP_MOD0(2),
-		SD_PRSNT_N_IN(3)								=> SFP_MOD0(4),
-		SD_LOS_IN(0)									=> SFP_LOS(1),
-		SD_LOS_IN(1)									=> SFP_LOS(6),
-		SD_LOS_IN(2)									=> SFP_LOS(2),
-		SD_LOS_IN(3)									=> SFP_LOS(4),
-		SD_TXDIS_OUT(0)								=> sfp_txdis_S(1),
-		SD_TXDIS_OUT(1)								=> sfp_txdis_S(6),
-		SD_TXDIS_OUT(2)								=> sfp_txdis_S(2),
-		SD_TXDIS_OUT(3)								=> sfp_txdis_S(4),
-
-		SCI_DATA_IN										=> sci2_data_in,
-		SCI_DATA_OUT									=> sci2_data_out,
-		SCI_ADDR											=> sci2_addr,
-		SCI_READ											=> sci2_read,
-		SCI_WRITE										=> sci2_write,
-		SCI_ACK											=> sci2_ack, 
-		SCI_NACK											=> sci2_nack--,
-
-		--Status and control port
---		STAT_OP(0)										=> med_stat_op(15 downto 0),	--med_stat_op(1*16+15 downto 1*16),
---		CTRL_OP(0)										=> med_ctrl_op(15 downto 0),	--med_ctrl_op(0*16+15 downto 0*16),
---		STAT_DEBUG										=> open,
---		CTRL_DEBUG										=> (others => '0')
-	);
- 
-
-
-	SFP_TXDIS		<=	sfp_txdis_S;
---	SFP_TXDIS(1)	<=	sfp_txdis_S(1);
-
----------------------------------------------------------------------------
--- Burst- and 40MHz cycle generator
----------------------------------------------------------------------------         
-
-THE_SOB_SOURCE : soda_start_of_burst_control
-	generic map(
-		CLOCK_PERIOD				=> cSODA_CLOCK_PERIOD,	-- clock-period in ns
-		CYCLE_PERIOD				=> cSODA_CYCLE_PERIOD,	-- cycle-period in ns
-		BURST_PERIOD				=> cBURST_PERIOD			-- burst-period in ns
-		)
-	port map(
-		SODA_CLK						=> clk_200_osc,
-		RESET							=> reset_i,
-		SODA_BURST_PULSE_OUT		=> SOB_S,
-		SODA_40MHZ_CYCLE_OUT		=>	soda_40mhz_cycle_S
-	);
-
----------------------------------------------------------------------------
--- The Soda Central 
----------------------------------------------------------------------------  
-
-	THE_SODA_QUAD_SOURCE : soda_4source
-		port map(
-			SYSCLK						=> clk_100_osc,
-			SODACLK						=> clk_200_osc,
-			RESET							=> reset_i,
-			CLEAR							=> clear_i,
-			CLK_EN						=> '1',
-
-			SODA_BURST_PULSE_IN		=> SOB_S,
-			SODA_CYCLE_IN				=> soda_40mhz_cycle_S,
-	--	MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
-			RX_DLM_IN					=> rx_dlm_i,
-			RX_DLM_WORD_IN				=> rx_dlm_word,
-			TX_DLM_OUT					=> tx_dlm_i, 
-			TX_DLM_WORD_OUT			=> tx_dlm_word,
-			TX_DLM_PREVIEW_OUT		=> tx_dlm_preview_S,
-			LINK_PHASE_IN				=> link_phase_S,
-			SODA_DATA_IN				=> soda_data_in,
-			SODA_DATA_OUT				=> soda_data_out,
-			SODA_ADDR_IN				=> soda_addr,
-			SODA_READ_IN				=> soda_read,
-			SODA_WRITE_IN				=> soda_write,
-			SODA_ACK_OUT				=> soda_ack,
-			LEDS_OUT						=>	soda_leds,
-			LINK_DEBUG_IN				=> link_debug_in_S
-		);
-
-
-	LED_ORANGE	<= time_counter_S(27);
-	LED_YELLOW	<= time_counter_S(26);
-	LED_GREEN	<= time_counter_S(25);
-	LED_RED		<= time_counter_S(24);
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-	blink_L : process (clk_200_osc)
-	begin
-		if rising_edge(clk_200_osc) then
-			if (time_counter_S(15 downto 0) = x"FFFF") then
-				 time_counter_S(15 downto 0)	<= x"0000";
-			else
-				time_counter_S(15 downto 0) <= time_counter_S(15 downto 0) + 1;
-			end if;
-		end if;
-	end process;
-
-	blink_H : process (clk_200_osc, time_counter_S)
-	begin
-		if (rising_edge(clk_200_osc) and (time_counter_S(15 downto 0) = x"FFFF"))then
-			if ((time_counter_S(31 downto 16) = x"FFFF") and (time_counter_S(15 downto 0) = x"FFFF")) then
-				time_counter_S(31 downto 16) <= x"0000";
-			else
-				time_counter_S(31 downto 16) <= time_counter_S(31 downto 16) + 1;
-			end if;
-		end if;
-	end process;
-
-	
-	TEST_LINE(15 downto 3)	<= time_counter_S(31 downto 19);	--(others => '0');		-- otherwise it is floating
-
-	TEST_LINE(2)	<= '1';
-	TEST_LINE(1)	<= '1';
-	TEST_LINE(0)	<= '1';
---	TEST_LINE(7 downto 0)	<= (others => '1');		-- otherwise it is floating
---	TEST_LINE(15 downto 8)	<= (others => '0');		-- otherwise it is floating
-
-end trb3_periph_EP_soda4source_arch;
\ No newline at end of file
diff --git a/code/trb3_periph_EP_sodahub.vhd b/code/trb3_periph_EP_sodahub.vhd
deleted file mode 100644
index 84c3e10..0000000
--- a/code/trb3_periph_EP_sodahub.vhd
+++ /dev/null
@@ -1,804 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all; 
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_EP_hub is
-  generic(
-    SYNC_MODE : integer range 0 to 1 := c_YES;   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
-    USE_125_MHZ : integer := c_NO;
-    CLOCK_FREQUENCY : integer := 100;
-    NUM_TRB_INTERFACES : integer := 1
-    );
-  port(
-    --Clocks 
-		CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
-		CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
-		CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-		CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
-    --serdes I/O - connect as you like, no real use
-		SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
-		SERDES_ADDON_RX      : in  std_logic_vector(15 downto 0);
-
-    --Inter-FPGA Communication
-    FPGA5_COMM : inout std_logic_vector(11 downto 0); --Bit 0/1 input, serial link RX active
-                                                      --Bit 2/3 output, serial link TX active
-                                                      --others yet undefined
-    --Connection to AddOn
-    LED_LINKOK : out std_logic_vector(6 downto 1);
-    LED_RX     : out std_logic_vector(6 downto 1); 
-    LED_TX     : out std_logic_vector(6 downto 1);
-    SFP_MOD0   : in  std_logic_vector(6 downto 1);
-    SFP_TXDIS  : out std_logic_vector(6 downto 1); 
-    SFP_LOS    : in  std_logic_vector(6 downto 1);
-    --SFP_MOD1   : inout std_logic_vector(6 downto 1); 
-    --SFP_MOD2   : inout std_logic_vector(6 downto 1); 
-    --SFP_RATESEL : out std_logic_vector(6 downto 1);
-    --SFP_TXFAULT : in  std_logic_vector(6 downto 1);
-
-    --Flash ROM & Reboot
-    FLASH_CLK  : out   std_logic;
-    FLASH_CS   : out   std_logic;
-    FLASH_DIN  : out   std_logic;
-    FLASH_DOUT : in    std_logic;
-    PROGRAMN   : out   std_logic;                     --reboot FPGA
-
-    --Misc
-    TEMPSENS   : inout std_logic;       --Temperature Sensor
-    CODE_LINE  : in    std_logic_vector(1 downto 0);
-    LED_GREEN  : out   std_logic;
-    LED_ORANGE : out   std_logic;
-    LED_RED    : out   std_logic;
-    LED_YELLOW : out   std_logic;
-    SUPPL      : in    std_logic;       --terminated diff pair, PCLK, Pads
-
-    --Test Connectors
-    TEST_LINE : out std_logic_vector(15 downto 0)
-    );
-
-
-	attribute syn_useioff                  : boolean;
-	--no IO-FF for LEDs relaxes timing constraints
-	attribute syn_useioff of LED_GREEN		: signal is false;
-	attribute syn_useioff of LED_ORANGE		: signal is false;
-	attribute syn_useioff of LED_RED			: signal is false;
-	attribute syn_useioff of LED_YELLOW		: signal is false;
-	attribute syn_useioff of TEMPSENS			: signal is false;
-	attribute syn_useioff of PROGRAMN			: signal is false;
-	attribute syn_useioff of CODE_LINE		: signal is false;
-	attribute syn_useioff of LED_LINKOK		: signal is false;
-	attribute syn_useioff of LED_TX			: signal is false;
-	attribute syn_useioff of LED_RX			: signal is false;
-	attribute syn_useioff of SFP_MOD0			: signal is false;
-	attribute syn_useioff of SFP_TXDIS		: signal is false;
-	attribute syn_useioff of SFP_LOS			: signal is false;
-	attribute syn_useioff of TEST_LINE		: signal is false;
-
-	--important signals _with_ IO-FF
-	attribute syn_useioff of FLASH_CLK		: signal is true;
-	attribute syn_useioff of FLASH_CS			: signal is true;
-	attribute syn_useioff of FLASH_DIN		: signal is true;
-	attribute syn_useioff of FLASH_DOUT		: signal is true;
-	attribute syn_useioff of FPGA5_COMM		: signal is true;
-
-
-end entity;
-
-architecture trb3_periph_EP_hub_arch of trb3_periph_EP_hub is
-	--Constants
-	constant REGIO_NUM_STAT_REGS : integer := 0;
-	constant REGIO_NUM_CTRL_REGS : integer := 2;
-
-	attribute syn_keep     : boolean;
-	attribute syn_preserve : boolean;
-
-	constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
-
-	--Clock / Reset
-	signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
-	signal clear_i                  : std_logic;
-	signal reset_i                  : std_logic;
-	signal downlink_clear				: std_logic;
-	signal downlink_reset				: std_logic;
-	signal GSR_N                    : std_logic;
-	signal clk_100_osc         : std_logic;
-	signal clk_200_osc         : std_logic;
-		signal time_counter			: unsigned(31 downto 0);
-	--Media Interface
-	signal med_stat_op        : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
-	signal med_ctrl_op        : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
-	signal med_stat_debug     : std_logic_vector (NUM_TRB_INTERFACES*64-1 downto 0);
---	signal med_ctrl_debug     : std_logic_vector (NUM_TRB_INTERFACES*64-1 downto 0);
-	signal med_data_out       : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
-	signal med_packet_num_out : std_logic_vector (NUM_TRB_INTERFACES* 3-1 downto 0);
-	signal med_dataready_out  : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
-	signal med_read_out       : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
-	signal med_data_in        : std_logic_vector (NUM_TRB_INTERFACES*16-1 downto 0);
-	signal med_packet_num_in  : std_logic_vector (NUM_TRB_INTERFACES* 3-1 downto 0);
-	signal med_dataready_in   : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
-	signal med_read_in        : std_logic_vector (NUM_TRB_INTERFACES* 1-1 downto 0);
-
-	--Slow Control channel
---	signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-	signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-	signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-	signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
-	signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
-	signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
-	--RegIO
---	signal my_address             : std_logic_vector (15 downto 0);
-	signal regio_addr_out         : std_logic_vector (15 downto 0);
-	signal regio_read_enable_out  : std_logic;
-	signal regio_write_enable_out : std_logic;
-	signal regio_data_out         : std_logic_vector (31 downto 0);
-	signal regio_data_in          : std_logic_vector (31 downto 0);
-	signal regio_dataready_in     : std_logic;
-	signal regio_no_more_data_in  : std_logic;
-	signal regio_write_ack_in     : std_logic;
-	signal regio_unknown_addr_in  : std_logic;
-	signal regio_timeout_out      : std_logic;
-
-	--Timer
-	signal global_time         : std_logic_vector(31 downto 0);
-	signal local_time          : std_logic_vector(7 downto 0);
-	signal time_since_last_trg : std_logic_vector(31 downto 0);
-	signal timer_ticks         : std_logic_vector(1 downto 0);
-
-	--Flash
-	signal spimem_read_en          : std_logic;
-	signal spimem_write_en         : std_logic;
-	signal spimem_data_in          : std_logic_vector(31 downto 0);
-	signal spimem_addr             : std_logic_vector(8 downto 0);
-	signal spimem_data_out         : std_logic_vector(31 downto 0);
-	signal spimem_dataready_out    : std_logic;
-	signal spimem_no_more_data_out : std_logic;
-	signal spimem_unknown_addr_out : std_logic;
-	signal spimem_write_ack_out    : std_logic;
-
--- SCI for the uplink
-	signal sci1_ack      : std_logic;
-	signal sci1_nack		: std_logic;
-	signal sci1_write    : std_logic;
-	signal sci1_read     : std_logic;
-	signal sci1_data_in  : std_logic_vector(7 downto 0);
-	signal sci1_data_out : std_logic_vector(7 downto 0);
-	signal sci1_addr     : std_logic_vector(8 downto 0);  
--- SCI for the downlink
-	signal sci2_ack      : std_logic;
-	signal sci2_nack     : std_logic;
-	signal sci2_write    : std_logic;
-	signal sci2_read     : std_logic;
-	signal sci2_data_in  : std_logic_vector(7 downto 0);
-	signal sci2_data_out : std_logic_vector(7 downto 0);
-	signal sci2_addr     : std_logic_vector(8 downto 0);  
-
-	signal sfp_txdis_S			: std_logic_vector(6 downto 1) := (others => '1'); 
-
-	--SODA
-	signal soda_ack				: std_logic;
-	signal soda_nack			: std_logic;
-	signal soda_write			: std_logic;
-	signal soda_read			: std_logic;
-	signal soda_data_in			: std_logic_vector(31 downto 0);
-	signal soda_data_out		: std_logic_vector(31 downto 0);
-	signal soda_addr			: std_logic_vector(3 downto 0);  
-	signal soda_leds			: std_logic_vector(3 downto 0);  
-
-	--SODA uplink
-	signal rxup_half_clk					: std_logic;
-	signal rxup_full_clk					: std_logic;
-	signal txup_half_clk					: std_logic;
-	signal txup_full_clk					: std_logic;
-
-	signal rx_cdr_lol_S					: std_logic;
-	signal txup_dlm_i						: std_logic;
-	signal rxup_dlm_i						: std_logic;
-	signal txup_dlm_word					: std_logic_vector(7 downto 0);
-	signal rxup_dlm_word					: std_logic_vector(7 downto 0);
-	signal txup_dlm_preview_S			: std_logic;	--PL!
-	signal uplink_phase_S				: std_logic;	--PL!
-	signal uplink_ready_S				: std_logic;	--PL!
-
-	--SODA downlink
-	signal rxdn_half_clk					: t_HUB_BIT;
-	signal rxdn_full_clk					: t_HUB_BIT;
-	signal txdn_half_clk					: t_HUB_BIT;
-	signal txdn_full_clk					: t_HUB_BIT;
-	  
-	signal txdn_dlm_i						: t_HUB_BIT;
-	signal rxdn_dlm_i						: t_HUB_BIT;
-	signal txdn_dlm_word					: t_HUB_BYTE;
-	signal rxdn_dlm_word					: t_HUB_BYTE;
-	signal txdn_dlm_preview_S			: t_HUB_BIT;	--PL!
-	signal dnlink_phase_S				: t_HUB_BIT;	--PL!
-
-	signal link_debug_in_S		: std_logic_vector(31 downto 0);
-	
-	--SODA
-	signal SOB_S							: std_logic := '0';
-  	-- fix signal names for constraining
-	attribute syn_keep			of GSR_N    					: signal is true;
-	attribute syn_preserve		of GSR_N							: signal is true;
-	attribute syn_preserve		of clk_100_osc					: signal is true;
-	attribute syn_keep			of clk_100_osc					: signal is true;
-	attribute syn_preserve		of clk_200_osc					: signal is true;
-	attribute syn_keep			of clk_200_osc					: signal is true;
-
-	attribute syn_preserve		of rxup_full_clk				: signal is true;
-	attribute syn_keep			of rxup_full_clk				: signal is true;
-	attribute syn_preserve		of rxup_half_clk				: signal is true;
-	attribute syn_keep			of rxup_half_clk				: signal is true;
-	attribute syn_preserve		of txup_full_clk				: signal is true;
-	attribute syn_keep			of txup_full_clk				: signal is true;
-	attribute syn_preserve		of txup_half_clk				: signal is true;
-	attribute syn_keep			of txup_half_clk				: signal is true;
-	attribute syn_preserve		of txup_dlm_i					: signal is true;
-	attribute syn_keep			of txup_dlm_i					: signal is true;
-	attribute syn_preserve		of rxup_dlm_i					: signal is true;
-	attribute syn_keep			of rxup_dlm_i					: signal is true;
-
-	attribute syn_preserve		of rxdn_full_clk				: signal is true;
-	attribute syn_keep			of rxdn_full_clk				: signal is true;
-	attribute syn_preserve		of rxdn_half_clk				: signal is true;
-	attribute syn_keep			of rxdn_half_clk				: signal is true;
-	attribute syn_preserve		of txdn_full_clk				: signal is true;
-	attribute syn_keep			of txdn_full_clk				: signal is true;
-	attribute syn_preserve		of txdn_half_clk				: signal is true;
-	attribute syn_keep			of txdn_half_clk				: signal is true;
-	attribute syn_preserve		of txdn_dlm_i					: signal is true;
-	attribute syn_keep			of txdn_dlm_i					: signal is true;
-	attribute syn_preserve		of rxdn_dlm_i					: signal is true;
-	attribute syn_keep			of rxdn_dlm_i					: signal is true;
-
-	
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-  GSR_N <= pll_lock;
-
-  THE_RESET_HANDLER : trb_net_reset_handler
-    generic map(
-      RESET_DELAY => x"FEEE"
-      )
-    port map(
-      CLEAR_IN      => '0',					-- reset input (high active, async)
-      CLEAR_N_IN    => '1',					-- reset input (low active, async)
-      CLK_IN        => clk_200_osc,			-- raw master clock, NOT from PLL/DLL!
-      SYSCLK_IN     => clk_100_osc,			-- PLL/DLL remastered clock
-      PLL_LOCKED_IN => pll_lock,				-- master PLL lock signal (async)
-      RESET_IN      => '0',					-- general reset signal (SYSCLK)
-      TRB_RESET_IN  => med_stat_op(13),	-- TRBnet reset signal (SYSCLK)
-      CLEAR_OUT     => clear_i,				-- async reset out, USE WITH CARE!
-      RESET_OUT     => reset_i,				-- synchronous reset out (SYSCLK)
-      DEBUG_OUT     => open
-      );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
---gen_200_PLL : if USE_125_MHZ = c_NO generate
-	THE_MAIN_PLL : pll_in200_out100
-		port map(
-			CLK   => CLK_GPLL_RIGHT,
-			CLKOP => clk_100_osc,
-			CLKOK => clk_200_osc,
-			LOCK  => pll_lock
-		);
---end generate;      
-
---gen_125 : if USE_125_MHZ = c_YES generate
---  clk_100_osc <= CLK_GPLL_LEFT;
---  clk_200_osc <= CLK_GPLL_LEFT;
---end generate; 
-
-
-
----------------------------------------------------------------------------
--- The synchronous interface for Soda and trb_endpoint
----------------------------------------------------------------------------      
-
-THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
-	generic map(
-		SERDES_NUM			=> 0,  --number of serdes in quad
-		IS_SYNC_SLAVE		=> c_YES
-		)
-	port map(
-		OSCCLK					=> clk_200_osc,
-		SYSCLK					=> clk_100_osc,		-- rx_half_clk is selectively used inside med_ecp3_sfp_sync_down.vhd
-		RESET						=> reset_i,
-		CLEAR						=> clear_i,
-		--Internal Connection for TrbNet data -> not used a.t.m.
-		MED_DATA_IN				=> med_data_out(15 downto 0),
-		MED_PACKET_NUM_IN		=> med_packet_num_out(2 downto 0),
-		MED_DATAREADY_IN		=> med_dataready_out(0),
-		MED_READ_OUT			=> med_read_in(0),
-		MED_DATA_OUT			=> med_data_in(15 downto 0),
-		MED_PACKET_NUM_OUT	=> med_packet_num_in(2 downto 0),
-		MED_DATAREADY_OUT		=> med_dataready_in(0),
-		MED_READ_IN				=> med_read_out(0),
-		RX_HALF_CLK_OUT		=> rxup_half_clk,
-		RX_FULL_CLK_OUT		=> rxup_full_clk,
-		TX_HALF_CLK_OUT		=> txup_half_clk,
-		TX_FULL_CLK_OUT		=> txup_full_clk,
-		RX_CDR_LOL_OUT			=> rx_cdr_lol_S,		-- !PL 14082014     
-
-		RX_DLM					=> rxup_dlm_i,
-		RX_DLM_WORD				=> rxup_dlm_word,
-		TX_DLM					=> txup_dlm_i,
-		TX_DLM_WORD				=> txup_dlm_word,
-		TX_DLM_PREVIEW_IN		=> txup_dlm_preview_S,			--PL!
-		LINK_PHASE_OUT			=>	uplink_phase_S,		--PL!
-		LINK_READY_OUT			=>	uplink_ready_S,		--PL!
-		--SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting
-		SD_RXD_P_IN				=> SERDES_ADDON_RX(4),
-		SD_RXD_N_IN				=> SERDES_ADDON_RX(5),
-		SD_TXD_P_OUT			=> SERDES_ADDON_TX(4),
-		SD_TXD_N_OUT			=> SERDES_ADDON_TX(5),
-		SD_REFCLK_P_IN			=> '0',
-		SD_REFCLK_N_IN			=> '0',
-		SD_PRSNT_N_IN			=> SFP_MOD0(3),	-- = A3, was 1 = B0
-		SD_LOS_IN				=> SFP_LOS(3),
-		SD_TXDIS_OUT			=> sfp_txdis_S(3),	--SFP_TXDIS(3), this signal is now used to release downlinks
-
-		SCI_DATA_IN				=> sci1_data_in,
-		SCI_DATA_OUT			=> sci1_data_out,
-		SCI_ADDR					=> sci1_addr,
-		SCI_READ					=> sci1_read,
-		SCI_WRITE				=> sci1_write,
-		SCI_ACK					=> sci1_ack, 
-		SCI_NACK					=> sci1_nack,
-		-- Status and control port
-		STAT_OP					=> med_stat_op(15 downto 0),
-		CTRL_OP					=> med_ctrl_op(15 downto 0),
-		STAT_DEBUG				=> open,
-		CTRL_DEBUG				=> (others => '0')
-	); 
-
-
-	SFP_TXDIS		<=	sfp_txdis_S;
- 
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
-  THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
-    generic map(
---		USE_CHANNEL               => (c_YES,c_YES,c_NO,c_YES),
-		REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
-		REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
-		ADDRESS_MASK              => x"FFFF",
-		BROADCAST_BITMASK         => x"FF",
-		BROADCAST_SPECIAL_ADDR    => x"45",
-		REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
-		REGIO_HARDWARE_VERSION    => x"9100b000",
-		REGIO_INIT_ADDRESS        => x"f359",
-		REGIO_USE_VAR_ENDPOINT_ID => c_YES,
-		CLOCK_FREQUENCY           => CLOCK_FREQUENCY,
-		TIMING_TRIGGER_RAW        => c_YES,
-		--Configure data handler
-		DATA_INTERFACE_NUMBER     => 1,
-		DATA_BUFFER_DEPTH         => 9,  --13
-		DATA_BUFFER_WIDTH         => 32,
-		DATA_BUFFER_FULL_THRESH   => 256,
-		TRG_RELEASE_AFTER_DATA    => c_YES,
-		HEADER_BUFFER_DEPTH       => 9,
-		HEADER_BUFFER_FULL_THRESH => 256
-      )
-    port map(
-		CLK                => clk_100_osc,
-		RESET              => reset_i,
-		CLK_EN             => '1',
-		MED_DATAREADY_OUT  => med_dataready_out(0),
-		MED_DATA_OUT       => med_data_out,
-		MED_PACKET_NUM_OUT => med_packet_num_out,
-		MED_READ_IN        => med_read_in(0),
-		MED_DATAREADY_IN   => med_dataready_in(0),
-		MED_DATA_IN        => med_data_in,
-		MED_PACKET_NUM_IN  => med_packet_num_in,
-		MED_READ_OUT       => med_read_out(0),
-		MED_STAT_OP_IN     => med_stat_op,
-		MED_CTRL_OP_OUT    => med_ctrl_op,
-
-		--Timing trigger in
-		TRG_TIMING_TRG_RECEIVED_IN  => '0',
-		--LVL1 trigger to FEE
-		LVL1_TRG_DATA_VALID_OUT     => open,
-		LVL1_VALID_TIMING_TRG_OUT   => open,
-		LVL1_VALID_NOTIMING_TRG_OUT => open,
-		LVL1_INVALID_TRG_OUT        => open,
-
-		LVL1_TRG_TYPE_OUT        => open,
-		LVL1_TRG_NUMBER_OUT      => open,
-		LVL1_TRG_CODE_OUT        => open,
-		LVL1_TRG_INFORMATION_OUT => open,
-		LVL1_INT_TRG_NUMBER_OUT  => open,
-
-		--Information about trigger handler errors
-		TRG_MULTIPLE_TRG_OUT     => open,
-		TRG_TIMEOUT_DETECTED_OUT => open,
-		TRG_SPURIOUS_TRG_OUT     => open,
-		TRG_MISSING_TMG_TRG_OUT  => open,
-		TRG_SPIKE_DETECTED_OUT   => open,
-
-		--Response from FEE
-		FEE_TRG_RELEASE_IN(0)       => '1',
-		FEE_TRG_STATUSBITS_IN       => (others => '0'),
-		FEE_DATA_IN                 => (others => '0'),
-		FEE_DATA_WRITE_IN(0)        => '0',
-		FEE_DATA_FINISHED_IN(0)     => '1',
-		FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
-		-- Slow Control Data Port
-		REGIO_COMMON_STAT_REG_IN           => (others => '0'),		--common_stat_reg,  --0x00  because it is floating
-		REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
-		REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
-		REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
-		REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
-		REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
-		REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
-		REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
-		REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
-		REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
-		BUS_ADDR_OUT         => regio_addr_out,
-		BUS_READ_ENABLE_OUT  => regio_read_enable_out,
-		BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
-		BUS_DATA_OUT         => regio_data_out,
-		BUS_DATA_IN          => regio_data_in,
-		BUS_DATAREADY_IN     => regio_dataready_in,
-		BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
-		BUS_WRITE_ACK_IN     => regio_write_ack_in,
-		BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
-		BUS_TIMEOUT_OUT      => regio_timeout_out,
-		ONEWIRE_INOUT        => TEMPSENS,
-		ONEWIRE_MONITOR_OUT  => open,
-
-		TIME_GLOBAL_OUT         => global_time,
-		TIME_LOCAL_OUT          => local_time,
-		TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
-		TIME_TICKS_OUT          => timer_ticks,
-
-		STAT_DEBUG_IPU              => open,
-		STAT_DEBUG_1                => open,
-		STAT_DEBUG_2                => open,
-		STAT_DEBUG_DATA_HANDLER_OUT => open,
-		STAT_DEBUG_IPU_HANDLER_OUT  => open,
-		STAT_TRIGGER_OUT            => open,
-		CTRL_MPLEX                  => (others => '0'),
-		IOBUF_CTRL_GEN              => (others => '0'),
-		STAT_ONEWIRE                => open,
-		STAT_ADDR_DEBUG             => open,
-		DEBUG_LVL1_HANDLER_OUT      => open
-		);
-
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
-  THE_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER    => 4,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 9,       3 => 4,       others => 0)
-      )
-    port map(
-		CLK   => clk_100_osc,
-		RESET => reset_i,
-
-		DAT_ADDR_IN					=> regio_addr_out,
-		DAT_DATA_IN					=> regio_data_out,
-		DAT_DATA_OUT				=> regio_data_in,
-		DAT_READ_ENABLE_IN		=> regio_read_enable_out,
-		DAT_WRITE_ENABLE_IN		=> regio_write_enable_out,
-		DAT_TIMEOUT_IN				=> regio_timeout_out,
-		DAT_DATAREADY_OUT			=> regio_dataready_in,
-		DAT_WRITE_ACK_OUT			=> regio_write_ack_in,
-		DAT_NO_MORE_DATA_OUT		=> regio_no_more_data_in,
-		DAT_UNKNOWN_ADDR_OUT		=> regio_unknown_addr_in,
-
-		BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
-		BUS_READ_ENABLE_OUT(1)              => sci1_read,
-		BUS_READ_ENABLE_OUT(2)              => sci2_read,
-		BUS_READ_ENABLE_OUT(3)              => soda_read,
-
-		BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
-		BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
-		BUS_WRITE_ENABLE_OUT(2)             => sci2_write,
-		BUS_WRITE_ENABLE_OUT(3)             => soda_write,
-
-		BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
-		BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
-		BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
-		BUS_DATA_OUT(2*32+7 downto 2*32)    => sci2_data_in,
-		BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
-		BUS_DATA_OUT(3*32+31 downto 3*32)   => soda_data_in,
-
-		BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
-		BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
-		BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
-		BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
-		BUS_ADDR_OUT(2*16+8 downto 2*16)   	=> sci2_addr,
-		BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
-		BUS_ADDR_OUT(3*16+3 downto 3*16)   	=> soda_addr,
-		BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
-
-		BUS_TIMEOUT_OUT(0)                  => open,
-		BUS_TIMEOUT_OUT(1)                  => open,
-		BUS_TIMEOUT_OUT(2)                  => open,
-		BUS_TIMEOUT_OUT(3)                  => open,
-
-		BUS_DATA_IN(0*32+31 downto 0*32)    => spimem_data_out,
-		BUS_DATA_IN(1*32+7 downto 1*32)     => sci1_data_out,
-		BUS_DATA_IN(1*32+31 downto 1*32+8)  => open,
-		BUS_DATA_IN(2*32+7 downto 2*32)     => sci2_data_out,
-		BUS_DATA_IN(2*32+31 downto 2*32+8)  => open,
-		BUS_DATA_IN(3*32+31 downto 3*32)    => soda_data_out,
-
-		BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
-		BUS_DATAREADY_IN(1)                 => sci1_ack,
-		BUS_DATAREADY_IN(2)                 => sci2_ack,
-		BUS_DATAREADY_IN(3)                 => soda_ack,
-
-		BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
-		BUS_WRITE_ACK_IN(1)                 => sci1_ack,
-		BUS_WRITE_ACK_IN(2)                 => sci2_ack,
-		BUS_WRITE_ACK_IN(3)                 => soda_ack,
-
-		BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
-		BUS_NO_MORE_DATA_IN(1)              => '0',
-		BUS_NO_MORE_DATA_IN(2)              => '0',
-		BUS_NO_MORE_DATA_IN(3)              => '0',
-
-		BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
-		BUS_UNKNOWN_ADDR_IN(1)              => '0',
-		BUS_UNKNOWN_ADDR_IN(2)              => '0',
-		BUS_UNKNOWN_ADDR_IN(3)              => '0',
-
-		STAT_DEBUG => open
-		);
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD :  spi_flash_and_fpga_reload	--.flash_reboot_arch
-  port map(
-	 CLK_IN						=> clk_100_osc,
-    RESET_IN					=> reset_i,
-    
-    BUS_ADDR_IN          => spimem_addr,
-    BUS_READ_IN          => spimem_read_en,
-    BUS_WRITE_IN         => spimem_write_en,
-    BUS_DATAREADY_OUT    => spimem_dataready_out,
-    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
-    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
-    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
-    BUS_DATA_IN          => spimem_data_in,
-    BUS_DATA_OUT         => spimem_data_out,
-    
-    DO_REBOOT_IN         => common_ctrl_reg(15),     
-    PROGRAMN             => PROGRAMN,
-    
-    SPI_CS_OUT           => FLASH_CS,
-    SPI_SCK_OUT          => FLASH_CLK,
-    SPI_SDO_OUT          => FLASH_DIN,
-    SPI_SDI_IN           => FLASH_DOUT
-    );
-
-      
----------------------------------------------------------------------------
--- The synchronous quad-downlink interface for Soda
----------------------------------------------------------------------------      
-
-		THE_HUB_SYNC_DOWNLINK : med_ecp3_sfp_4_sync_down_EP
-			generic map(
-				SERDES_NUM			=> 0, --number of serdes in quad
-				IS_SYNC_SLAVE		=> c_NO
-				)
-			port map(
-				OSC_CLK											=> clk_200_osc,
-				TX_DATACLK										=> rxup_full_clk,
-				SYSCLK											=> clk_100_osc,	-- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
-				RESET												=> downlink_reset,
-				CLEAR												=> downlink_clear,
-				---------------------------------------------------------------------------------------------------------------------------------------------------------
-				LINK_DISABLE_IN								=> sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
-				---------------------------------------------------------------------------------------------------------------------------------------------------------
-				RX_HALF_CLK_OUT(0)							=> rxdn_half_clk(0),
-				RX_HALF_CLK_OUT(1)							=> rxdn_half_clk(1),
-				RX_HALF_CLK_OUT(2)							=> rxdn_half_clk(2),
-				RX_HALF_CLK_OUT(3)							=> rxdn_half_clk(3),
-
-				RX_FULL_CLK_OUT(0)							=> rxdn_full_clk(0),	-- needed for sync replies i.e. calibration
-				RX_FULL_CLK_OUT(1)							=> rxdn_full_clk(1),	-- needed for sync replies i.e. calibration
-				RX_FULL_CLK_OUT(2)							=> rxdn_full_clk(2),	-- needed for sync replies i.e. calibration
-				RX_FULL_CLK_OUT(3)							=> rxdn_full_clk(3),	-- needed for sync replies i.e. calibration
-
-				TX_HALF_CLK_OUT(0)							=> txdn_half_clk(0),
-				TX_HALF_CLK_OUT(1)							=> txdn_half_clk(1),
-				TX_HALF_CLK_OUT(2)							=> txdn_half_clk(2),
-				TX_HALF_CLK_OUT(3)							=> txdn_half_clk(3),
-
-				TX_FULL_CLK_OUT(0)							=> txdn_full_clk(0),
-				TX_FULL_CLK_OUT(1)							=> txdn_full_clk(1),
-				TX_FULL_CLK_OUT(2)							=> txdn_full_clk(2),
-				TX_FULL_CLK_OUT(3)							=> txdn_full_clk(3),
-
-				RX_DLM(0)										=> rxdn_dlm_i(0),
-				RX_DLM(1)										=> rxdn_dlm_i(1),
-				RX_DLM(2)										=> rxdn_dlm_i(2),
-				RX_DLM(3)										=> rxdn_dlm_i(3),
-				
-				RX_DLM_WORD(0)									=> rxdn_dlm_word(0),
-				RX_DLM_WORD(1)									=> rxdn_dlm_word(1),
-				RX_DLM_WORD(2)									=> rxdn_dlm_word(2),
-				RX_DLM_WORD(3)									=> rxdn_dlm_word(3),
-				
-				TX_DLM(0)										=> txdn_dlm_i(0),
-				TX_DLM(1)										=> txdn_dlm_i(1),
-				TX_DLM(2)										=> txdn_dlm_i(2),
-				TX_DLM(3)										=> txdn_dlm_i(3),
-				
-				TX_DLM_WORD(0)									=> txdn_dlm_word(0),
-				TX_DLM_WORD(1)									=> txdn_dlm_word(1),
-				TX_DLM_WORD(2)									=> txdn_dlm_word(2),
-				TX_DLM_WORD(3)									=> txdn_dlm_word(3),
-
-				TX_DLM_PREVIEW_IN(0)							=> txdn_dlm_preview_S(0),			--PL!
-				TX_DLM_PREVIEW_IN(1)							=> txdn_dlm_preview_S(1),			--PL!
-				TX_DLM_PREVIEW_IN(2)							=> txdn_dlm_preview_S(2),			--PL!
-				TX_DLM_PREVIEW_IN(3)							=> txdn_dlm_preview_S(3),			--PL!
-
-				LINK_PHASE_OUT(0)								=>	dnlink_phase_S(0),				--PL!
-				LINK_PHASE_OUT(1)								=>	dnlink_phase_S(1),				--PL!
-				LINK_PHASE_OUT(2)								=>	dnlink_phase_S(2),				--PL!
-				LINK_PHASE_OUT(3)								=>	dnlink_phase_S(3),				--PL!
-
-				--SFP Connection
-				SD_RXD_P_IN(0)									=> SERDES_ADDON_RX(0),			-- B0
-				SD_RXD_P_IN(1)									=> SERDES_ADDON_RX(1),
-				SD_RXD_P_IN(2)									=> SERDES_ADDON_RX(10),			-- B1
-				SD_RXD_P_IN(3)									=> SERDES_ADDON_RX(11),	
-				SD_RXD_N_IN(0)									=> SERDES_ADDON_RX(2),			-- B2
-				SD_RXD_N_IN(1)									=> SERDES_ADDON_RX(3),
-				SD_RXD_N_IN(2)									=> SERDES_ADDON_RX(6),			-- B3
-				SD_RXD_N_IN(3)									=> SERDES_ADDON_RX(7),
-				SD_TXD_P_OUT(0)								=> SERDES_ADDON_TX(0),			-- B0
-				SD_TXD_P_OUT(1)								=> SERDES_ADDON_TX(1),
-				SD_TXD_P_OUT(2)								=> SERDES_ADDON_TX(10),			-- B1
-				SD_TXD_P_OUT(3)								=> SERDES_ADDON_TX(11),
-				SD_TXD_N_OUT(0)								=> SERDES_ADDON_TX(2),			-- B2
-				SD_TXD_N_OUT(1)								=> SERDES_ADDON_TX(3),
-				SD_TXD_N_OUT(2)								=> SERDES_ADDON_TX(6),			-- B3
-				SD_TXD_N_OUT(3)								=> SERDES_ADDON_TX(7),
-				SD_REFCLK_P_IN									=> (others => '0'),
-				SD_REFCLK_N_IN									=> ('0','0','0','0'),
-				SD_PRSNT_N_IN(0)								=> SFP_MOD0(1),
-				SD_PRSNT_N_IN(1)								=> SFP_MOD0(6),
-				SD_PRSNT_N_IN(2)								=> SFP_MOD0(2),
-				SD_PRSNT_N_IN(3)								=> SFP_MOD0(4),
-				SD_LOS_IN(0)									=> SFP_LOS(1),
-				SD_LOS_IN(1)									=> SFP_LOS(6),
-				SD_LOS_IN(2)									=> SFP_LOS(2),
-				SD_LOS_IN(3)									=> SFP_LOS(4),
-				SD_TXDIS_OUT(0)								=> sfp_txdis_S(1),
-				SD_TXDIS_OUT(1)								=> sfp_txdis_S(6),
-				SD_TXDIS_OUT(2)								=> sfp_txdis_S(2),
-				SD_TXDIS_OUT(3)								=> sfp_txdis_S(4),
-
-				SCI_DATA_IN										=> sci2_data_in,
-				SCI_DATA_OUT									=> sci2_data_out,
-				SCI_ADDR											=> sci2_addr,
-				SCI_READ											=> sci2_read,
-				SCI_WRITE										=> sci2_write,
-				SCI_ACK											=> sci2_ack, 
-				SCI_NACK											=> sci2_nack,
-
-				--Status and control port
---				STAT_OP(0)										=> med_stat_op(15 downto 0),	--med_stat_op(1*16+15 downto 1*16),
---				CTRL_OP(0)										=> med_ctrl_op(15 downto 0),	--med_ctrl_op(0*16+15 downto 0*16),
-
-				STAT_DEBUG										=> open,
-				CTRL_DEBUG										=> (others => '0')
-		);
-
-
-
-	SFP_TXDIS		<=	sfp_txdis_S;
---	SFP_TXDIS(1)	<=	sfp_txdis_S(1);
-
----------------------------------------------------------------------------
--- The Soda Central
----------------------------------------------------------------------------         
-
-THE_SOB_SOURCE : soda_start_of_burst_faker
-	generic map(
-		CLOCK_PERIOD				=> cSYS_CLOCK_PERIOD,	-- clock-period in ns
-		BURST_PERIOD				=> cBURST_PERIOD			-- burst-period in ns
-		)
-	port map(
-		SYSCLK						=> clk_100_osc,
-		RESET							=> reset_i,
-		SODA_BURST_PULSE_OUT		=> SOB_S
-	);
-
----------------------------------------------------------------------------
--- The Soda Central 
----------------------------------------------------------------------------  
-
-	A_SODA_HUB : soda_hub
-		port map(
-			SYSCLK					=> rxup_half_clk,
-			SODACLK					=>	rxup_full_clk,
-			RESET						=> reset_i,
-			CLEAR						=> clear_i,
-			CLK_EN					=> '1',
-
-	--	SINGLE DUBPLEX UP-LINK TO THE TOP
-			RXUP_DLM_WORD_IN		=> rxup_dlm_word,
-			RXUP_DLM_IN				=> rxup_dlm_i,
-			TXUP_DLM_OUT			=> txup_dlm_i, 
-			TXUP_DLM_WORD_OUT		=> txup_dlm_word,
-			TXUP_DLM_PREVIEW_OUT	=> txup_dlm_preview_S,
-			UPLINK_PHASE_IN		=> uplink_phase_S,
-	--	MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
-			RXDN_DLM_WORD_IN		=> rxdn_dlm_word,
-			RXDN_DLM_IN				=> rxdn_dlm_i,
-			TXDN_DLM_OUT			=> txdn_dlm_i, 
-			TXDN_DLM_WORD_OUT		=> txdn_dlm_word,
-			TXDN_DLM_PREVIEW_OUT	=> txdn_dlm_preview_S,
-			DNLINK_PHASE_IN		=> dnlink_phase_S,	
-
-			SODA_DATA_IN			=> soda_data_in,
-			SODA_DATA_OUT			=> soda_data_out,
-			SODA_ADDR_IN			=> soda_addr,
-			SODA_READ_IN			=> soda_read,
-			SODA_WRITE_IN			=> soda_write,
-			SODA_ACK_OUT			=> soda_ack,
-			LEDS_OUT					=>	soda_leds,
-			LINK_DEBUG_IN			=> link_debug_in_S
-		);
-
-
-		downlink_reset	<=	'1'	when (reset_i = '1' or uplink_ready_S = '0') else '0';
-		downlink_clear	<=	'1'	when (clear_i = '1' or uplink_ready_S = '0') else '0';
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
-	LED_ORANGE <= SFP_LOS(1);			--med_stat_op(8);
-	LED_YELLOW <= sfp_txdis_S(1);		--med_stat_op(10);
-	LED_GREEN  <= med_stat_op(12);	--tx_pll_lol
-	LED_RED    <= med_stat_op(11);	--rx_cdr_lol
-
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------    
---  TEST_LINE(15 downto 0) <= (others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-  process
-    begin
-      wait until rising_edge(clk_100_osc);
-      time_counter <= time_counter + 1;
-    end process;
-
-
-end trb3_periph_EP_hub_arch;
\ No newline at end of file
diff --git a/code/trb3_periph_sodaclient.vhd b/code/trb3_periph_sodaclient.vhd
deleted file mode 100644
index 86dd712..0000000
--- a/code/trb3_periph_sodaclient.vhd
+++ /dev/null
@@ -1,662 +0,0 @@
----------------
--- TOP LEVEL --
----------------
--- TAB=3 !!
--- 24/11/2014
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all; 
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodaclient is
-  generic(
-    SYNC_MODE : integer range 0 to 1 := c_YES;   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
-    USE_125_MHZ : integer := c_NO;
-    CLOCK_FREQUENCY : integer := 100;
-    NUM_INTERFACES : integer := 1
-    );
-  port(
-    --Clocks 
-    CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
-    CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
-    CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-    CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
-    --Trigger
-    --TRIGGER_LEFT  : in std_logic;       --left side trigger input from fan-out
-    --TRIGGER_RIGHT : in std_logic;       --right side trigger input from fan-out
-    --Serdes Clocks - do not use
-    --CLK_SERDES_INT_LEFT  : in  std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
-    --CLK_SERDES_INT_RIGHT : in  std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
-
-    --serdes I/O - connect as you like, no real use
-    SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
-    SERDES_ADDON_RX      : in  std_logic_vector(15 downto 0);
-
-    --Inter-FPGA Communication
-    FPGA5_COMM : inout std_logic_vector(11 downto 0);
-                                                      --Bit 0/1 input, serial link RX active
-                                                      --Bit 2/3 output, serial link TX active
-                                                      --others yet undefined
-    --Connection to AddOn
-    LED_LINKOK : out std_logic_vector(6 downto 1);
-    LED_RX     : out std_logic_vector(6 downto 1); 
-    LED_TX     : out std_logic_vector(6 downto 1);
-    SFP_MOD0   : in  std_logic_vector(6 downto 1);
-    SFP_TXDIS  : out std_logic_vector(6 downto 1); 
-    SFP_LOS    : in  std_logic_vector(6 downto 1);
-    --SFP_MOD1   : inout std_logic_vector(6 downto 1); 
-    --SFP_MOD2   : inout std_logic_vector(6 downto 1); 
-    --SFP_RATESEL : out std_logic_vector(6 downto 1);
-    --SFP_TXFAULT : in  std_logic_vector(6 downto 1);
-
-    --Flash ROM & Reboot
-    FLASH_CLK  : out   std_logic;
-    FLASH_CS   : out   std_logic;
-    FLASH_DIN  : out   std_logic;
-    FLASH_DOUT : in    std_logic;
-    PROGRAMN   : out   std_logic;                     --reboot FPGA
-
-    --Misc
-    TEMPSENS   : inout std_logic;       --Temperature Sensor
-    CODE_LINE  : in    std_logic_vector(1 downto 0);
-    LED_GREEN  : out   std_logic;
-    LED_ORANGE : out   std_logic;
-    LED_RED    : out   std_logic;
-    LED_YELLOW : out   std_logic;
-    SUPPL      : in    std_logic;       --terminated diff pair, PCLK, Pads
-
-    --Test Connectors
-    TEST_LINE : out std_logic_vector(15 downto 0)
-    );
-
-
-	attribute syn_useioff                  : boolean;
-	--no IO-FF for LEDs relaxes timing constraints
-	attribute syn_useioff of LED_GREEN     : signal is false;
-	attribute syn_useioff of LED_ORANGE    : signal is false;
-	attribute syn_useioff of LED_RED       : signal is false;
-	attribute syn_useioff of LED_YELLOW    : signal is false;
-	attribute syn_useioff of TEMPSENS      : signal is false;
-	attribute syn_useioff of PROGRAMN      : signal is false;
-	attribute syn_useioff of CODE_LINE     : signal is false;
-	attribute syn_useioff of LED_LINKOK    : signal is false;
-	attribute syn_useioff of LED_TX        : signal is false;
-	attribute syn_useioff of LED_RX        : signal is false;
-	attribute syn_useioff of SFP_MOD0      : signal is false;
-	attribute syn_useioff of SFP_TXDIS     : signal is false;
-	attribute syn_useioff of SFP_LOS       : signal is false;
-	attribute syn_useioff of TEST_LINE  : signal is false;
-
-	--important signals _with_ IO-FF
-	attribute syn_useioff of FLASH_CLK  : signal is true;
-	attribute syn_useioff of FLASH_CS   : signal is true;
-	attribute syn_useioff of FLASH_DIN  : signal is true;
-	attribute syn_useioff of FLASH_DOUT : signal is true;
-	attribute syn_useioff of FPGA5_COMM : signal is true;
-
-
-end entity;
-
-architecture trb3_periph_sodaclient_arch of trb3_periph_sodaclient is
-	--Constants
-	constant REGIO_NUM_STAT_REGS : integer := 0;
-	constant REGIO_NUM_CTRL_REGS : integer := 2;
-
-
-	constant USE_200_MHZ : integer := 1 - USE_125_MHZ;	-- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
-	--Clock / Reset
-	signal pll_lock				: std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
-	signal clear_i					: std_logic;
-	signal reset_i					: std_logic;
-	signal GSR						: std_logic;
-	signal GSR_N					: std_logic;
-
-	signal clk_100_osc         : std_logic;
-	signal clk_200_osc         : std_logic;
-	signal rx_full_clk			: std_logic;
-	signal rx_half_clk			: std_logic;
-	signal tx_full_clk			: std_logic;
-	signal tx_half_clk			: std_logic;
-	signal time_counter, time_counter2 : unsigned(31 downto 0);
-	
-	--Media Interface
-	signal med_stat_op        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_ctrl_op        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_stat_debug     : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-	signal med_ctrl_debug     : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-	signal med_data_out       : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-	signal med_dataready_out  : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_read_out       : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_data_in        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_packet_num_in  : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-	signal med_dataready_in   : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_read_in        : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
-	--Slow Control channel
-	signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-	signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-	signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-	signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
-	signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
-	signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
-	--RegIO
-	signal my_address             : std_logic_vector (15 downto 0);
-	signal regio_addr_out         : std_logic_vector (15 downto 0);
-	signal regio_read_enable_out  : std_logic;
-	signal regio_write_enable_out : std_logic;
-	signal regio_data_out         : std_logic_vector (31 downto 0);
-	signal regio_data_in          : std_logic_vector (31 downto 0);
-	signal regio_dataready_in     : std_logic;
-	signal regio_no_more_data_in  : std_logic;
-	signal regio_write_ack_in     : std_logic;
-	signal regio_unknown_addr_in  : std_logic;
-	signal regio_timeout_out      : std_logic;
-
-	--Timer
-	signal global_time         : std_logic_vector(31 downto 0);
-	signal local_time          : std_logic_vector(7 downto 0);
-	signal time_since_last_trg : std_logic_vector(31 downto 0);
-	signal timer_ticks         : std_logic_vector(1 downto 0);
-
-	--Flash
-	signal spimem_read_en          : std_logic;
-	signal spimem_write_en         : std_logic;
-	signal spimem_data_in          : std_logic_vector(31 downto 0);
-	signal spimem_addr             : std_logic_vector(8 downto 0);
-	signal spimem_data_out         : std_logic_vector(31 downto 0);
-	signal spimem_dataready_out    : std_logic;
-	signal spimem_no_more_data_out : std_logic;
-	signal spimem_unknown_addr_out : std_logic;
-	signal spimem_write_ack_out    : std_logic;
-
-	--media interface
-	signal sci1_ack      : std_logic;
-	signal sci1_write    : std_logic;
-	signal sci1_read     : std_logic;
-	signal sci1_data_in  : std_logic_vector(7 downto 0);
-	signal sci1_data_out : std_logic_vector(7 downto 0);
-	signal sci1_addr     : std_logic_vector(8 downto 0);  
-	signal sci1_nack     : std_logic;
-	signal sfp_txdis_S	: std_logic_vector(6 downto 1)	:= (others => '1'); 
-
-
-	--SODA
-	signal tx_dlm_i          : std_logic;
-	signal rx_dlm_i          : std_logic;
-	signal tx_dlm_word       : std_logic_vector(7 downto 0);
-	signal rx_dlm_word       : std_logic_vector(7 downto 0);
-	signal make_reset        : std_logic;
-	signal tx_dlm_preview_S		: std_logic;	--PL!
-	signal link_phase_S			: std_logic;	--PL!
-	signal rx_cdr_lol_S 	      : std_logic;
-	signal link_locked_S			: std_logic;	--PL!
-
-  -- SODA slow controll
-	signal soda_ack			: std_logic;
---	signal soda_nack			: std_logic;
-	signal soda_write			: std_logic;
-	signal soda_read			: std_logic;
-	signal soda_data_in		: std_logic_vector(31 downto 0);
-	signal soda_data_out		: std_logic_vector(31 downto 0);
-	signal soda_addr			: std_logic_vector(3 downto 0);  
-	signal soda_leds			: std_logic_vector(3 downto 0);  
-
-	signal link_debug_in_S	: std_logic_vector(31 downto 0);
-	signal general_reset_i	: std_logic := '1';
-  
-	signal soda_counter_i	: unsigned(3 downto 0);
-  	-- fix signal names for constraining
-	attribute syn_preserve	of rx_full_clk				: signal is true;
-	attribute syn_keep		of rx_full_clk				: signal is true;
-	attribute syn_preserve	of rx_half_clk				: signal is true;
-	attribute syn_keep		of rx_half_clk				: signal is true;
-	attribute syn_preserve	of clk_100_osc				: signal is true;
-	attribute syn_keep		of clk_100_osc				: signal is true;
-	attribute syn_preserve	of clk_200_osc				: signal is true;
-	attribute syn_keep		of clk_200_osc				: signal is true;
-	attribute syn_preserve	of tx_dlm_i					: signal is true;
-	attribute syn_keep		of tx_dlm_i					: signal is true;
-	attribute syn_preserve	of rx_dlm_i					: signal is true;
-	attribute syn_keep		of rx_dlm_i					: signal is true;
-	attribute syn_keep		of GSR						: signal is true;
-	attribute syn_preserve	of GSR						: signal is true;
-	attribute syn_keep		of GSR_N						: signal is true;
-	attribute syn_preserve	of GSR_N						: signal is true;
-	attribute syn_keep		of soda_counter_i			: signal is true;
-	attribute syn_preserve	of soda_counter_i			: signal is true;
-
-	
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-
-	LED_RX 		<= (others => '0');		-- otherwise it is floating
-	LED_TX 		<= (others => '0');		-- otherwise it is floating
-	LED_LINKOK	<= (others => '0');		-- otherwise it is floating
-	
-	GSR_N <= pll_lock;
-	GSR	<= not(pll_lock);
-
-  THE_RESET_HANDLER : trb_net_reset_handler
-    generic map(
-      RESET_DELAY => x"FEEE"
-      )
-    port map(
-      CLEAR_IN      => '0',              -- reset input (high active, async)
-      CLEAR_N_IN    => '1',              -- reset input (low active, async)
-      CLK_IN        => clk_200_osc,			-- raw master clock, NOT from PLL/DLL!
-      SYSCLK_IN     => rx_half_clk,			--clk_100_osc,        -- PLL/DLL remastered clock
-      PLL_LOCKED_IN => pll_lock,				-- master PLL lock signal (async)
-      RESET_IN      => '0',	--general_reset_i,	--'0',					-- general reset signal (SYSCLK) --peter schakel
-      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
-      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
-      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
-      DEBUG_OUT     => open
-      );  
-
-	process(rx_half_clk) 
-	begin
-		if rising_edge(rx_half_clk) then
-			general_reset_i <= not SFP_LOS(1);
-		end if;
-	end process;
-	
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
---gen_200_PLL : if USE_125_MHZ = c_NO generate
-	THE_MAIN_PLL : pll_in200_out100
-		port map(
-		CLK   => CLK_GPLL_RIGHT,
-		RESET => '0',
-		CLKOP => clk_100_osc,
-		CLKOK => clk_200_osc,
-		LOCK  => pll_lock
-	);
---end generate;      
-
---gen_125 : if USE_125_MHZ = c_YES generate
---  clk_100_osc <= CLK_GPLL_LEFT;
---  clk_raw_internal <= CLK_GPLL_LEFT;
---end generate; 
-
---gen_sync_clocks : if SYNC_MODE = c_YES generate
---	clk_sys_i	<= clk_100_osc;
---	clk_soda_i	<= soda_rx_clock_full;
---	clk_200_i	<= soda_rx_clock_full;
---end generate;
-
---gen_local_clocks : if SYNC_MODE = c_NO generate
---	clk_sys_i	<= clk_100_osc;
---	clk_soda_i	<= clk_raw_internal;
---	clk_200_i	<= clk_raw_internal;
---end generate;
-
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
-  THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
-    generic map(
---		USE_CHANNEL               => (c_YES,c_YES,c_NO,c_YES),
-		REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
-		REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
-		ADDRESS_MASK              => x"FFFF",
-		BROADCAST_BITMASK         => x"FF",
-		BROADCAST_SPECIAL_ADDR    => x"45",
-		REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
-		REGIO_HARDWARE_VERSION    => x"9100b000",
-		REGIO_INIT_ADDRESS        => x"f356",
-		REGIO_USE_VAR_ENDPOINT_ID => c_YES,
-		CLOCK_FREQUENCY           => CLOCK_FREQUENCY,
-		TIMING_TRIGGER_RAW        => c_YES,
-		--Configure data handler
-		DATA_INTERFACE_NUMBER     => 1,
-		DATA_BUFFER_DEPTH         => 9,  --13
-		DATA_BUFFER_WIDTH         => 32,
-		DATA_BUFFER_FULL_THRESH   => 256,
-		TRG_RELEASE_AFTER_DATA    => c_YES,
-		HEADER_BUFFER_DEPTH       => 9,
-		HEADER_BUFFER_FULL_THRESH => 256
-      )
-    port map(
-		CLK                => rx_half_clk,	--clk_100_osc,
-		RESET              => reset_i,
-		CLK_EN             => '1',
-		MED_DATAREADY_OUT  => med_dataready_out(0),
-		MED_DATA_OUT       => med_data_out,
-		MED_PACKET_NUM_OUT => med_packet_num_out,
-		MED_READ_IN        => med_read_in(0),
-		MED_DATAREADY_IN   => med_dataready_in(0),
-		MED_DATA_IN        => med_data_in,
-		MED_PACKET_NUM_IN  => med_packet_num_in,
-		MED_READ_OUT       => med_read_out(0),
-		MED_STAT_OP_IN     => med_stat_op,
-		MED_CTRL_OP_OUT    => med_ctrl_op,
-
-		--Timing trigger in
-		TRG_TIMING_TRG_RECEIVED_IN  => '0',
-		--LVL1 trigger to FEE
-		LVL1_TRG_DATA_VALID_OUT     => open,
-		LVL1_VALID_TIMING_TRG_OUT   => open,
-		LVL1_VALID_NOTIMING_TRG_OUT => open,
-		LVL1_INVALID_TRG_OUT        => open,
-
-		LVL1_TRG_TYPE_OUT        => open,
-		LVL1_TRG_NUMBER_OUT      => open,
-		LVL1_TRG_CODE_OUT        => open,
-		LVL1_TRG_INFORMATION_OUT => open,
-		LVL1_INT_TRG_NUMBER_OUT  => open,
-
-		--Information about trigger handler errors
-		TRG_MULTIPLE_TRG_OUT     => open,
-		TRG_TIMEOUT_DETECTED_OUT => open,
-		TRG_SPURIOUS_TRG_OUT     => open,
-		TRG_MISSING_TMG_TRG_OUT  => open,
-		TRG_SPIKE_DETECTED_OUT   => open,
-
-		--Response from FEE
-		FEE_TRG_RELEASE_IN(0)       => '1',
-		FEE_TRG_STATUSBITS_IN       => (others => '0'),
-		FEE_DATA_IN                 => (others => '0'),
-		FEE_DATA_WRITE_IN(0)        => '0',
-		FEE_DATA_FINISHED_IN(0)     => '1',
-		FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
-		-- Slow Control Data Port
-		REGIO_COMMON_STAT_REG_IN           => (others => '0'),		--common_stat_reg,  --0x00  because it is floating
-		REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
-		REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
-		REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
-		REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
-		REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
-		REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
-		REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
-		REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
-		REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
-		BUS_ADDR_OUT         => regio_addr_out,
-		BUS_READ_ENABLE_OUT  => regio_read_enable_out,
-		BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
-		BUS_DATA_OUT         => regio_data_out,
-		BUS_DATA_IN          => regio_data_in,
-		BUS_DATAREADY_IN     => regio_dataready_in,
-		BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
-		BUS_WRITE_ACK_IN     => regio_write_ack_in,
-		BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
-		BUS_TIMEOUT_OUT      => regio_timeout_out,
-		ONEWIRE_INOUT        => TEMPSENS,
-		ONEWIRE_MONITOR_OUT  => open,
-
-		TIME_GLOBAL_OUT         => global_time,
-		TIME_LOCAL_OUT          => local_time,
-		TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
-		TIME_TICKS_OUT          => timer_ticks,
-
-		STAT_DEBUG_IPU              => open,
-		STAT_DEBUG_1                => open,
-		STAT_DEBUG_2                => open,
-		STAT_DEBUG_DATA_HANDLER_OUT => open,
-		STAT_DEBUG_IPU_HANDLER_OUT  => open,
-		STAT_TRIGGER_OUT            => open,
-		CTRL_MPLEX                  => (others => '0'),
-		IOBUF_CTRL_GEN              => (others => '0'),
-		STAT_ONEWIRE                => open,
-		STAT_ADDR_DEBUG             => open,
-		DEBUG_LVL1_HANDLER_OUT      => open
-		);
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
-  THE_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER    => 3,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"be00", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 4,       others => 0)
-      )
-    port map(
-		CLK   => rx_half_clk,	--clk_100_osc,
-		RESET => reset_i,
-
-		DAT_ADDR_IN					=> regio_addr_out,
-		DAT_DATA_IN					=> regio_data_out,
-		DAT_DATA_OUT				=> regio_data_in,
-		DAT_READ_ENABLE_IN		=> regio_read_enable_out,
-		DAT_WRITE_ENABLE_IN		=> regio_write_enable_out,
-		DAT_TIMEOUT_IN				=> regio_timeout_out,
-		DAT_DATAREADY_OUT			=> regio_dataready_in,
-		DAT_WRITE_ACK_OUT			=> regio_write_ack_in,
-		DAT_NO_MORE_DATA_OUT		=> regio_no_more_data_in,
-		DAT_UNKNOWN_ADDR_OUT		=> regio_unknown_addr_in,
-
-		BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
-		BUS_READ_ENABLE_OUT(1)              => sci1_read,
-		BUS_READ_ENABLE_OUT(2)              => soda_read,
-
-		BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
-		BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
-		BUS_WRITE_ENABLE_OUT(2)             => soda_write,
-
-		BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
-		BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
-		BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
-		BUS_DATA_OUT(2*32+31 downto 2*32)   => soda_data_in,
-
-		BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
-		BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
-		BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
-		BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
-		BUS_ADDR_OUT(2*16+3 downto 2*16)   	=> soda_addr,
-		BUS_ADDR_OUT(2*16+15 downto 2*16+4) => open,
-
-		BUS_TIMEOUT_OUT(0)                  => open,
-		BUS_TIMEOUT_OUT(1)                  => open,
-		BUS_TIMEOUT_OUT(2)                  => open,
-
-		BUS_DATA_IN(0*32+31 downto 0*32)    => spimem_data_out,
-		BUS_DATA_IN(1*32+7 downto 1*32)     => sci1_data_out,
-		BUS_DATA_IN(1*32+31 downto 1*32+8)  => open,
-		BUS_DATA_IN(2*32+31 downto 2*32)    => soda_data_out,
-
-		BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
-		BUS_DATAREADY_IN(1)                 => sci1_ack,
-		BUS_DATAREADY_IN(2)                 => soda_ack,
-
-		BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
-		BUS_WRITE_ACK_IN(1)                 => sci1_ack,
-		BUS_WRITE_ACK_IN(2)                 => soda_ack,
-
-		BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
-		BUS_NO_MORE_DATA_IN(1)              => '0',
-		BUS_NO_MORE_DATA_IN(2)              => '0',
-
-		BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
-		BUS_UNKNOWN_ADDR_IN(1)              => '0',
-		BUS_UNKNOWN_ADDR_IN(2)              => '0',
-
-		STAT_DEBUG => open
-		);
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD :  spi_flash_and_fpga_reload	--.flash_reboot_arch
-  port map(
-    CLK_IN               => clk_100_osc,	--rx_half_clk,
-    RESET_IN             => reset_i,
-    
-    BUS_ADDR_IN          => spimem_addr,
-    BUS_READ_IN          => spimem_read_en,
-    BUS_WRITE_IN         => spimem_write_en,
-    BUS_DATAREADY_OUT    => spimem_dataready_out,
-    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
-    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
-    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
-    BUS_DATA_IN          => spimem_data_in,
-    BUS_DATA_OUT         => spimem_data_out,
-    
-    DO_REBOOT_IN         => common_ctrl_reg(15),     
-    PROGRAMN             => PROGRAMN,
-    
-    SPI_CS_OUT           => FLASH_CS,
-    SPI_SCK_OUT          => FLASH_CLK,
-    SPI_SDO_OUT          => FLASH_DIN,
-    SPI_SDI_IN           => FLASH_DOUT
-    );
-
-      
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------      
-
-THE_SYNC_LINK : med_ecp3_sfp_sync_up
-	generic map(
-		SERDES_NUM				=> 1, --number of serdes in quad
-		IS_SYNC_SLAVE			=> c_YES
-		)
-	port map(
-		OSCCLK					=> clk_200_osc,
-		SYSCLK					=> clk_100_osc,
-		RESET						=> reset_i,
-		CLEAR						=> clear_i,
-		--Internal Connection for TrbNet data -> not used a.t.m.
-		MED_DATA_IN				=> med_data_out(15 downto 0),
-		MED_PACKET_NUM_IN		=> med_packet_num_out(2 downto 0),
-		MED_DATAREADY_IN		=> med_dataready_out(0),
-		MED_READ_OUT			=> med_read_in(0),
-		MED_DATA_OUT			=> med_data_in(15 downto 0),
-		MED_PACKET_NUM_OUT	=> med_packet_num_in(2 downto 0),
-		MED_DATAREADY_OUT		=> med_dataready_in(0),
-		MED_READ_IN				=> med_read_out(0),
-		RX_HALF_CLK_OUT		=> rx_half_clk,	--soda_rx_clock_half,
-		RX_FULL_CLK_OUT		=> rx_full_clk,	--soda_rx_clock_full,
-		TX_HALF_CLK_OUT		=> tx_half_clk,
-		TX_FULL_CLK_OUT		=> tx_full_clk,
-		RX_CDR_LOL_OUT			=> rx_cdr_lol_S,
-		
-		RX_DLM					=> rx_dlm_i,
-		RX_DLM_WORD				=> rx_dlm_word,
-		TX_DLM					=> tx_dlm_i,
-		TX_DLM_WORD				=> tx_dlm_word,
-		TX_DLM_PREVIEW_IN		=> tx_dlm_preview_S,			--PL!
-		LINK_PHASE_OUT			=>	link_phase_S,		--PL!
-		--SFP Connection
-		SD_RXD_P_IN				=> SERDES_ADDON_RX(4),	--(0),
-		SD_RXD_N_IN				=> SERDES_ADDON_RX(5),	--(1),
-		SD_TXD_P_OUT			=> SERDES_ADDON_TX(4),	--(0),
-		SD_TXD_N_OUT			=> SERDES_ADDON_TX(5),	--(1),
-		SD_REFCLK_P_IN			=> '0',
-		SD_REFCLK_N_IN			=> '0',
-		SD_PRSNT_N_IN			=> SFP_MOD0(3),	--(1),
-		SD_LOS_IN				=> SFP_LOS(3),	--(1),
-		SD_TXDIS_OUT			=> sfp_txdis_S(3),	--(1),	--SFP_TXDIS(1),
-
-		SCI_DATA_IN				=> sci1_data_in,
-		SCI_DATA_OUT			=> sci1_data_out,
-		SCI_ADDR					=> sci1_addr,
-		SCI_READ					=> sci1_read,
-		SCI_WRITE				=> sci1_write,
-		SCI_ACK					=> sci1_ack, 
-		SCI_NACK					=> sci1_nack,
-		-- Status and control port
-		STAT_OP					=> med_stat_op(15 downto 0),
-		CTRL_OP					=> med_ctrl_op(15 downto 0),
-		STAT_DEBUG				=> open,
-		CTRL_DEBUG				=> (others => '0')
-	);
-
-
---	SFP_TXDIS(1)	<=	sfp_txdis_S(1);
-	SFP_TXDIS		<=	sfp_txdis_S;
-	
----------------------------------------------------------------------------
--- The Soda Central 
----------------------------------------------------------------------------       
-
-	A_SODA_CLIENT : soda_client
-		port map(
-			SYSCLK					=> rx_half_clk,	--clk_100_osc,
-			SODACLK					=>	rx_full_clk,
-			RESET						=> reset_i,
-			CLEAR						=> clear_i,
-			CLK_EN					=> '1',
-			--Internal Connection
-			RX_DLM_WORD_IN			=> rx_dlm_word,
-			RX_DLM_IN				=> rx_dlm_i,
-			TX_DLM_OUT				=> tx_dlm_i, 
-			TX_DLM_WORD_OUT		=> tx_dlm_word,
-			TX_DLM_PREVIEW_OUT	=> tx_dlm_preview_S,
-			LINK_PHASE_IN			=> link_phase_S,
-			SODA_DATA_IN			=> soda_data_in,
-			SODA_DATA_OUT			=> soda_data_out,
-			SODA_ADDR_IN			=> soda_addr,
-			SODA_READ_IN			=> soda_read,
-			SODA_WRITE_IN			=> soda_write,
-			SODA_ACK_OUT			=> soda_ack,
-			LEDS_OUT					=>	soda_leds,
-			LINK_DEBUG_IN			=> link_debug_in_S
-		);
-
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
-	LED_ORANGE <= '0';	--reset_i;			--med_stat_op(8);
-	LED_YELLOW <= '1';	--clear_i;		--med_stat_op(10);
-	LED_GREEN  <= pll_lock;	--tx_pll_lol
-	LED_RED    <= time_counter(26);	--rx_cdr_lol
---	LED_ORANGE <= not reset_i when rising_edge(clk_100_osc);
---	LED_YELLOW <= soda_leds(0);	--'1';
---	LED_GREEN  <= not med_stat_op(9);
---	LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
---	LED_ORANGE <= soda_leds(0);
---	LED_YELLOW <= soda_leds(1);
---	LED_GREEN  <= soda_leds(2);
---	LED_RED    <= soda_leds(3);
-
----------------------------------------------------------------------------
--- DEBUG
----------------------------------------------------------------------------    
-	link_debug_in_S(31 downto 16)	<= med_stat_op(15 downto 0);
-	link_debug_in_S(15 downto 0)	<= (3 => pll_lock, others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-	blink : process (clk_100_osc)
-	begin
-		if rising_edge(clk_100_osc) then
-			if (time_counter = x"FFFFFFFF") then
-				time_counter <= x"00000000";
-			else
-				time_counter <= time_counter + 1;
-			end if;
-		end if;
-   end process;
-
-	process(rx_full_clk)	--soda_rx_clock_full)	--clk_soda_i) 
-	begin
-		if rising_edge(rx_full_clk) then
-			soda_counter_i <= soda_counter_i+1;
-		end if;
-	end process;
-
-	
-end trb3_periph_sodaclient_arch;
diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd
deleted file mode 100644
index e0d7163..0000000
--- a/code/trb3_periph_sodahub.vhd
+++ /dev/null
@@ -1,828 +0,0 @@
----------------
--- TOP LEVEL --
----------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all; 
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodahub is
-  generic(
---     SYNC_MODE : integer range 0 to 1 := c_YES;   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
-    USE_125_MHZ : integer := c_NO;
-    CLOCK_FREQUENCY : integer := 100;
-    NUM_INTERFACES : integer := 6 + 1	-- This is the number of SERDES's in use: 1 copper trb-upstream + 6 to ADDONboard
-    );
-  port(
-    --Clocks 
-    CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
-    CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
-    CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-    CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
-
-    --serdes I/O - connect as you like, no real use
-    SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
-    SERDES_ADDON_RX      : in  std_logic_vector(15 downto 0);
-
-    --Inter-FPGA Communication
-    FPGA5_COMM : inout std_logic_vector(11 downto 0);
-                                                      --Bit 0/1 input, serial link RX active
-                                                      --Bit 2/3 output, serial link TX active
-                                                      --others yet undefined
-    --Connection to AddOn
-    LED_LINKOK : out std_logic_vector(6 downto 1);
-    LED_RX     : out std_logic_vector(6 downto 1);
-    LED_TX     : out std_logic_vector(6 downto 1);
-    SFP_MOD0   : in  std_logic_vector(6 downto 1);
-    SFP_TXDIS  : out std_logic_vector(6 downto 1);
-    SFP_LOS    : in  std_logic_vector(6 downto 1);
-    SFP_MOD1   : inout std_logic_vector(6 downto 1);		--H!
-    SFP_MOD2   : inout std_logic_vector(6 downto 1);		--H!
-    --SFP_RATESEL : out std_logic_vector(6 downto 1);
-    --SFP_TXFAULT : in  std_logic_vector(6 downto 1);
-
-    --Flash ROM & Reboot
-    FLASH_CLK  : out   std_logic;
-    FLASH_CS   : out   std_logic;
-    FLASH_DIN  : out   std_logic;
-    FLASH_DOUT : in    std_logic;
-    PROGRAMN   : out   std_logic;                     --reboot FPGA
-
-    --Misc
-    TEMPSENS   : inout std_logic;       --Temperature Sensor
-    CODE_LINE  : in    std_logic_vector(1 downto 0);
-    LED_GREEN  : out   std_logic;
-    LED_ORANGE : out   std_logic;
-    LED_RED    : out   std_logic;
-    LED_YELLOW : out   std_logic;
-    SUPPL      : in    std_logic;       --terminated diff pair, PCLK, Pads
-
-    --Test Connectors
-    TEST_LINE : out std_logic_vector(15 downto 0)
-    );
-    
-  attribute syn_useioff                  : boolean;
-  --no IO-FF for LEDs relaxes timing constraints
-  attribute syn_useioff of SFP_LOS     : signal is false;
-  attribute syn_useioff of SFP_TXDIS   : signal is false;
-  attribute syn_useioff of SFP_MOD0    : signal is false;
-  attribute syn_useioff of LED_RX      : signal is false;
-  attribute syn_useioff of LED_TX      : signal is false;
-  attribute syn_useioff of LED_LINKOK  : signal is false;
-
-
-  end entity trb3_periph_sodahub;
-
-
-architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is
-	--Constants
-	constant REGIO_NUM_STAT_REGS : integer := 2;	--0; H!
-	constant REGIO_NUM_CTRL_REGS : integer := 2;
-
-
-	constant USE_200_MHZ : integer := 1 - USE_125_MHZ;	-- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
-	--Clock / Reset
-	--  signal clk_sys_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
---	signal clk_soda_i               : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
-	--   signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
-	signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
-	signal clear_i                  : std_logic;
-	signal reset_i                  : std_logic;
-	signal downlink_clear				: std_logic;
-	signal downlink_reset				: std_logic;
-	signal GSR_N                    : std_logic;
-	attribute syn_keep of GSR_N     : signal is true;
-	attribute syn_preserve of GSR_N : signal is true;
-	signal clk_100_osc         : std_logic;
---	signal clk_raw_internal         : std_logic;
-	signal clk_200_osc         : std_logic;
-
-	signal rxup_half_clk					: std_logic;
-	signal rxup_full_clk					: std_logic;
-	signal txup_half_clk					: std_logic;
-	signal txup_full_clk					: std_logic;
-	signal rx_cdr_lol_S					: std_logic;
-
-	signal rxdn_half_clk					: t_HUB_BIT;
-	signal rxdn_full_clk					: t_HUB_BIT;
-	signal txdn_half_clk					: t_HUB_BIT;
-	signal txdn_full_clk					: t_HUB_BIT;
-
-	signal time_counter					: unsigned(31 downto 0);
-	--Media Interface
-	signal med_stat_op					: std_logic_vector (NUM_INTERFACES*16-1 downto 0)	:= (others => '0');
-	signal med_ctrl_op					: std_logic_vector (NUM_INTERFACES*16-1 downto 0)	:= (others => '0');
-	signal med_stat_debug				: std_logic_vector (NUM_INTERFACES*64-1 downto 0)	:= (others => '0');
-	signal med_ctrl_debug				: std_logic_vector (NUM_INTERFACES*64-1 downto 0)	:= (others => '0');
-	signal med_data_out					: std_logic_vector (NUM_INTERFACES*16-1 downto 0)	:= (others => '0');
-	signal med_packet_num_out			: std_logic_vector (NUM_INTERFACES* 3-1 downto 0)	:= (others => '0');
-	signal med_dataready_out			: std_logic_vector (NUM_INTERFACES* 1-1 downto 0)	:= (others => '0');
-	signal med_read_out					: std_logic_vector (NUM_INTERFACES* 1-1 downto 0)	:= (others => '0');
-	signal med_data_in					: std_logic_vector (NUM_INTERFACES*16-1 downto 0)	:= (others => '0');
-	signal med_packet_num_in			: std_logic_vector (NUM_INTERFACES* 3-1 downto 0)	:= (others => '0');
-	signal med_dataready_in				: std_logic_vector (NUM_INTERFACES* 1-1 downto 0)	:= (others => '0');
-	signal med_read_in					: std_logic_vector (NUM_INTERFACES* 1-1 downto 0)	:= (others => '0');
-
-	--Slow Control channel
-	signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-	signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-	signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-	signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
-	signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
-	signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
-	--RegIO
-	signal my_address             : std_logic_vector (15 downto 0);
-	signal regio_addr_out         : std_logic_vector (15 downto 0);
-	signal regio_read_enable_out  : std_logic;
-	signal regio_write_enable_out : std_logic;
-	signal regio_data_out         : std_logic_vector (31 downto 0);
-	signal regio_data_in          : std_logic_vector (31 downto 0);
-	signal regio_dataready_in     : std_logic;
-	signal regio_no_more_data_in  : std_logic;
-	signal regio_write_ack_in     : std_logic;
-	signal regio_unknown_addr_in  : std_logic;
-	signal regio_timeout_out      : std_logic;
-
-	--Timer
-	signal global_time					: std_logic_vector(31 downto 0);
-	signal local_time						: std_logic_vector(7 downto 0);
-	signal time_since_last_trg			: std_logic_vector(31 downto 0);
-	signal timer_ticks					: std_logic_vector(1 downto 0);
-
-	--Flash
-	signal spimem_read_en				: std_logic;
-	signal spimem_write_en				: std_logic;
-	signal spimem_data_in				: std_logic_vector(31 downto 0);
-	signal spimem_addr					: std_logic_vector(8 downto 0);
-	signal spimem_data_out				: std_logic_vector(31 downto 0);
-	signal spimem_dataready_out		: std_logic;
-	signal spimem_no_more_data_out	: std_logic;
-	signal spimem_unknown_addr_out	: std_logic;
-	signal spimem_write_ack_out		: std_logic;
-
-	--media interface
-	signal sci1_ack						: std_logic;
-	signal sci1_write						: std_logic;
-	signal sci1_read						: std_logic;
-	signal sci1_data_in					: std_logic_vector(7 downto 0);
-	signal sci1_data_out					: std_logic_vector(7 downto 0);
-	signal sci1_addr						: std_logic_vector(8 downto 0);  
-	signal sci1_nack						: std_logic;
-	
-	signal sci2_ack						: std_logic;
-	signal sci2_nack						: std_logic;
-	signal sci2_write						: std_logic;
-	signal sci2_read						: std_logic;
-	signal sci2_data_in					: std_logic_vector(7 downto 0);
-	signal sci2_data_out					: std_logic_vector(7 downto 0);
-	signal sci2_addr						: std_logic_vector(8 downto 0);  
-
-	signal sfp_mod0_B						: t_QUAD_BIT	:= (others => '0');
-	signal sfp_los_B						: t_QUAD_BIT	:= (others => '0');
-	signal sfp_txdis_B					: t_QUAD_BIT	:= (others => '0');
-
-
-	--SODA
-	signal make_reset						: std_logic;
-
-	--SODA uplink
-	signal txup_dlm_i						: std_logic;
-	signal rxup_dlm_i						: std_logic;
-	signal txup_dlm_word					: std_logic_vector(7 downto 0);
-	signal rxup_dlm_word					: std_logic_vector(7 downto 0);
-	signal txup_dlm_preview_S			: std_logic;	--PL!
-	signal uplink_phase_S				: std_logic;	--PL!
-	signal uplink_ready_S				: std_logic;	--PL!
-	signal sfp_txdis_S			: std_logic_vector(6 downto 1)	:= (others => '1'); 
-
-	--SODA downlink
-	signal txdn_dlm_i						: t_HUB_BIT;
-	signal rxdn_dlm_i						: t_HUB_BIT;
-	signal txdn_dlm_word					: t_HUB_BYTE;
-	signal rxdn_dlm_word					: t_HUB_BYTE;
-	signal txdn_dlm_preview_S			: t_HUB_BIT;	--PL!
-	signal dnlink_phase_S				: t_HUB_BIT;	--PL!
-
-	-- SODA slow controll
-	signal soda_ack						: std_logic;
---	signal soda_nack						: std_logic;
-	signal soda_write						: std_logic;
-	signal soda_read						: std_logic;
-	signal soda_data_in					: std_logic_vector(31 downto 0);
-	signal soda_data_out					: std_logic_vector(31 downto 0);
-	signal soda_addr						: std_logic_vector(3 downto 0);  
-	signal soda_leds						: std_logic_vector(3 downto 0);  
-
-	signal link_debug_in_S				: std_logic_vector(31 downto 0);
-	signal general_reset_i				: std_logic := '1';
-  
---	signal soda_counter_i				: unsigned(31 downto 0);
-	
-
---	attribute syn_keep of soda_counter_i			: signal is true;
-  	-- fix signal names for constraining
-	attribute syn_preserve	of clk_100_osc		: signal is true;
-	attribute syn_keep		of clk_100_osc		: signal is true;
---	attribute syn_preserve	of clk_raw_internal		: signal is true;
---	attribute syn_keep		of clk_raw_internal		: signal is true;
---	attribute syn_preserve	of clk_soda_i			: signal is true;
---	attribute syn_keep		of clk_soda_i			: signal is true;
-	attribute syn_preserve	of txup_dlm_i			: signal is true;
-	attribute syn_keep		of txup_dlm_i			: signal is true;
-	attribute syn_preserve	of rxup_dlm_i			: signal is true;
-	attribute syn_keep		of rxup_dlm_i			: signal is true;
-	attribute syn_preserve	of txdn_dlm_i			: signal is true;
-	attribute syn_keep		of txdn_dlm_i			: signal is true;
-	attribute syn_preserve	of rxdn_dlm_i			: signal is true;
-	attribute syn_keep		of rxdn_dlm_i			: signal is true;
-
-	
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-
-	TEST_LINE	<= (others => '0');		-- otherwise it is floating
--- 	LED_RX 		<= (others => '0');		-- otherwise it is floating
--- 	LED_TX 		<= (others => '0');		-- otherwise it is floating
--- 	LED_LINKOK	<= (others => '0');		-- otherwise it is floating
-	
-	GSR_N <= pll_lock;
-
-
-  THE_RESET_HANDLER : trb_net_reset_handler
-    generic map(
-      RESET_DELAY => x"FEEE"
-      )
-    port map(
-      CLEAR_IN      => '0',              -- reset input (high active, async)
-      CLEAR_N_IN    => '1',              -- reset input (low active, async)
-      CLK_IN        => clk_200_osc,			-- raw master clock, NOT from PLL/DLL!
-      SYSCLK_IN     => rxup_half_clk,		--clk_100_osc,        -- PLL/DLL remastered clock
-      PLL_LOCKED_IN => GSR_N,		--pll_lock,         -- master PLL lock signal (async)	!PL 14082014
-      RESET_IN      => '0', --general_reset_i, -- '0',              -- general reset signal (SYSCLK) --peter schakel
-      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
-      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
-      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
-      DEBUG_OUT     => open
-      );  
-
---	process(clk_100_osc) 
---	begin
---		if rising_edge(clk_100_osc) then
---			general_reset_i <= not SFP_LOS(1);
---		end if;
---	end process;
-	
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
---gen_200_PLL : if USE_125_MHZ = c_NO generate
-  THE_MAIN_PLL : pll_in200_out100
-    port map(
-      CLK   => CLK_GPLL_RIGHT,
-	  RESET => '0',
-      CLKOP => clk_100_osc,
-      CLKOK => clk_200_osc,
-      LOCK  => pll_lock
-      );
---end generate;      
-
---gen_125 : if USE_125_MHZ = c_YES generate
---  clk_100_osc <= CLK_GPLL_LEFT;
---  clk_raw_internal <= CLK_GPLL_LEFT;
---end generate; 
-
---gen_sync_clocks : if SYNC_MODE = c_YES generate
---	clk_soda_i	<= rxup_full_clk;
---end generate;
-
---gen_local_clocks : if SYNC_MODE = c_NO generate
---	clk_soda_i	<= clk_raw_internal;
---end generate;
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
-  THE_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER    => 4,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 9,       3 => 4,       others => 0)
-      )
-    port map(
-		CLK   => rxup_half_clk,	--clk_100_osc,	--clk_sys_i,
-		RESET => reset_i,
-
-		DAT_ADDR_IN					=> regio_addr_out,
-		DAT_DATA_IN					=> regio_data_out,
-		DAT_DATA_OUT				=> regio_data_in,
-		DAT_READ_ENABLE_IN		=> regio_read_enable_out,
-		DAT_WRITE_ENABLE_IN		=> regio_write_enable_out,
-		DAT_TIMEOUT_IN				=> regio_timeout_out,
-		DAT_DATAREADY_OUT			=> regio_dataready_in,
-		DAT_WRITE_ACK_OUT			=> regio_write_ack_in,
-		DAT_NO_MORE_DATA_OUT		=> regio_no_more_data_in,
-		DAT_UNKNOWN_ADDR_OUT		=> regio_unknown_addr_in,
-
-      BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
-      BUS_READ_ENABLE_OUT(1)              => sci1_read,
-      BUS_READ_ENABLE_OUT(2)              => sci2_read,
-      BUS_READ_ENABLE_OUT(3)              => soda_read,
-
-      BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
-      BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
-      BUS_WRITE_ENABLE_OUT(2)             => sci2_write,
-      BUS_WRITE_ENABLE_OUT(3)             => soda_write,
-
-		BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
-      BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
-      BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
-      BUS_DATA_OUT(2*32+7 downto 2*32)    => sci2_data_in,
-      BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
-      BUS_DATA_OUT(3*32+31 downto 3*32)   => soda_data_in,
- 
-		BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
-      BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
-      BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
-      BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
-      BUS_ADDR_OUT(2*16+8 downto 2*16)    => sci2_addr,
-      BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
-      BUS_ADDR_OUT(3*16+3 downto 3*16)   	=> soda_addr,
-      BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
- 
-		BUS_TIMEOUT_OUT(0)							=> open,
-		BUS_TIMEOUT_OUT(1)							=> open,
-		BUS_TIMEOUT_OUT(2)							=> open,
-		BUS_TIMEOUT_OUT(3)							=> open,
-
-		BUS_DATA_IN(0*32+31	downto 0*32)		=> spimem_data_out,
-      BUS_DATA_IN(1*32+7	downto 1*32)		=> sci1_data_out,
-      BUS_DATA_IN(1*32+31	downto 1*32+8)	=> (others => '0'),
-      BUS_DATA_IN(2*32+7	downto 2*32)		=> sci2_data_out,
-      BUS_DATA_IN(2*32+31	downto 2*32+8)	=> (others => '0'),
-      BUS_DATA_IN(3*32+31	downto 3*32)		=> soda_data_out,
-
-		BUS_DATAREADY_IN(0)						=> spimem_dataready_out,
-      BUS_DATAREADY_IN(1)						=> sci1_ack,
-      BUS_DATAREADY_IN(2)						=> sci2_ack,
-      BUS_DATAREADY_IN(3)						=> soda_ack,
-
-		BUS_WRITE_ACK_IN(0)						=> spimem_write_ack_out,
-      BUS_WRITE_ACK_IN(1)						=> sci1_ack,
-      BUS_WRITE_ACK_IN(2)						=> sci2_ack,
-      BUS_WRITE_ACK_IN(3)						=> soda_ack,
-
-		BUS_NO_MORE_DATA_IN(0)					=> spimem_no_more_data_out,
-      BUS_NO_MORE_DATA_IN(1)					=> '0',
-      BUS_NO_MORE_DATA_IN(2)					=> '0',
-      BUS_NO_MORE_DATA_IN(3)					=> '0',
-      
-		BUS_UNKNOWN_ADDR_IN(0)					=> spimem_unknown_addr_out,
-      BUS_UNKNOWN_ADDR_IN(1)					=> '0',
-      BUS_UNKNOWN_ADDR_IN(2)					=> sci2_nack,
-      BUS_UNKNOWN_ADDR_IN(3)					=> '0',
-
-		STAT_DEBUG => open
-		);
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD :  spi_flash_and_fpga_reload	--.flash_reboot_arch
-  port map(
-    CLK_IN               => rxup_half_clk,	--clk_100_osc,
-    RESET_IN             => reset_i,
-    
-    BUS_ADDR_IN          => spimem_addr,
-    BUS_READ_IN          => spimem_read_en,
-    BUS_WRITE_IN         => spimem_write_en,
-    BUS_DATAREADY_OUT    => spimem_dataready_out,
-    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
-    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
-    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
-    BUS_DATA_IN          => spimem_data_in,
-    BUS_DATA_OUT         => spimem_data_out,
-    
-    DO_REBOOT_IN         => common_ctrl_reg(15),     
-    PROGRAMN             => PROGRAMN,
-    
-    SPI_CS_OUT           => FLASH_CS,
-    SPI_SCK_OUT          => FLASH_CLK,
-    SPI_SDO_OUT          => FLASH_DIN,
-    SPI_SDI_IN           => FLASH_DOUT
-    );
-
-      
-
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------      
-
-THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
-	generic map(
-		SERDES_NUM			=> 0,  --number of serdes in quad
-		IS_SYNC_SLAVE		=> c_YES
-		)
-	port map(
-		OSCCLK					=> clk_200_osc,
-		SYSCLK					=> rxup_half_clk, --clk_100_osc,		-- rx_half_clk is selectively used inside med_ecp3_sfp_sync_down.vhd
-		RESET						=> reset_i,
-		CLEAR						=> clear_i,
-		--Internal Connection for TrbNet data -> not used a.t.m.
-		MED_DATA_IN				=> med_data_out(15 downto 0),
-		MED_PACKET_NUM_IN		=> med_packet_num_out(2 downto 0),
-		MED_DATAREADY_IN		=> med_dataready_out(0),
-		MED_READ_OUT			=> med_read_in(0),
-		MED_DATA_OUT			=> med_data_in(15 downto 0),
-		MED_PACKET_NUM_OUT	=> med_packet_num_in(2 downto 0),
-		MED_DATAREADY_OUT		=> med_dataready_in(0),
-		MED_READ_IN				=> med_read_out(0),
-		RX_HALF_CLK_OUT		=> rxup_half_clk,
-		RX_FULL_CLK_OUT		=> rxup_full_clk,
-		TX_HALF_CLK_OUT		=> txup_half_clk,
-		TX_FULL_CLK_OUT		=> txup_full_clk,
-		RX_CDR_LOL_OUT			=> rx_cdr_lol_S,		-- !PL 14082014     
-
-		RX_DLM					=> rxup_dlm_i,
-		RX_DLM_WORD				=> rxup_dlm_word,
-		TX_DLM					=> txup_dlm_i,
-		TX_DLM_WORD				=> txup_dlm_word,
-		TX_DLM_PREVIEW_IN		=> txup_dlm_preview_S,			--PL!
-		LINK_PHASE_OUT			=>	uplink_phase_S,		--PL!
-		LINK_READY_OUT			=>	uplink_ready_S,		--PL!
-		--SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting
-		SD_RXD_P_IN				=> SERDES_ADDON_RX(4),
-		SD_RXD_N_IN				=> SERDES_ADDON_RX(5),
-		SD_TXD_P_OUT			=> SERDES_ADDON_TX(4),
-		SD_TXD_N_OUT			=> SERDES_ADDON_TX(5),
-		SD_REFCLK_P_IN			=> '0',
-		SD_REFCLK_N_IN			=> '0',
-		SD_PRSNT_N_IN			=> SFP_MOD0(3),	-- = A3, was 1 = B0
-		SD_LOS_IN				=> SFP_LOS(3),
-		SD_TXDIS_OUT			=> sfp_txdis_S(3),	--SFP_TXDIS(3), this signal is now used to release downlinks
-
-		SCI_DATA_IN				=> sci1_data_in,
-		SCI_DATA_OUT			=> sci1_data_out,
-		SCI_ADDR					=> sci1_addr,
-		SCI_READ					=> sci1_read,
-		SCI_WRITE				=> sci1_write,
-		SCI_ACK					=> sci1_ack, 
-		SCI_NACK					=> sci1_nack,
-		-- Status and control port
-		STAT_OP					=> med_stat_op(15 downto 0),
-		CTRL_OP					=> med_ctrl_op(15 downto 0),
-		STAT_DEBUG				=> open,
-		CTRL_DEBUG				=> (others => '0')
-	); 
-
-	SFP_TXDIS		<=	sfp_txdis_S;
-  
----------------------------------------------------------------------------
--- The Soda Central 
----------------------------------------------------------------------------  
-
-	A_SODA_HUB : soda_hub
-		port map(
-			SYSCLK					=> rxup_half_clk,
-			SODACLK					=>	rxup_full_clk,
-			RESET						=> reset_i,
-			CLEAR						=> clear_i,
-			CLK_EN					=> '1',
-
-	--	SINGLE DUBPLEX UP-LINK TO THE TOP
-			RXUP_DLM_WORD_IN		=> rxup_dlm_word,
-			RXUP_DLM_IN				=> rxup_dlm_i,
-			TXUP_DLM_OUT			=> txup_dlm_i, 
-			TXUP_DLM_WORD_OUT		=> txup_dlm_word,
-			TXUP_DLM_PREVIEW_OUT	=> txup_dlm_preview_S,
-			UPLINK_PHASE_IN		=> uplink_phase_S,
-	--	MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
-			RXDN_DLM_WORD_IN		=> rxdn_dlm_word,
-			RXDN_DLM_IN				=> rxdn_dlm_i,
-			TXDN_DLM_OUT			=> txdn_dlm_i, 
-			TXDN_DLM_WORD_OUT		=> txdn_dlm_word,
-			TXDN_DLM_PREVIEW_OUT	=> txdn_dlm_preview_S,
-			DNLINK_PHASE_IN		=> dnlink_phase_S,	
-
-			SODA_DATA_IN			=> soda_data_in,
-			SODA_DATA_OUT			=> soda_data_out,
-			SODA_ADDR_IN			=> soda_addr,
-			SODA_READ_IN			=> soda_read,
-			SODA_WRITE_IN			=> soda_write,
-			SODA_ACK_OUT			=> soda_ack,
-			LEDS_OUT					=>	soda_leds,
-			LINK_DEBUG_IN			=> link_debug_in_S
-		);
-
-
-		downlink_reset	<=	'1'	when (reset_i = '1' or uplink_ready_S = '0') else '0';
-		downlink_clear	<=	'1'	when (clear_i = '1' or uplink_ready_S = '0') else '0';
-
-		
-		THE_HUB_SYNC_DOWNLINK : med_ecp3_sfp_4_sync_down
-			generic map(
-				SERDES_NUM			=> 0, --number of serdes in quad
-				IS_SYNC_SLAVE		=> c_NO
-				)
-			port map(
-				OSC_CLK											=> clk_200_osc,
-				TX_DATACLK										=> rxup_full_clk,
-				SYSCLK											=> rxup_half_clk, --clk_100_osc,	-- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
-				RESET												=> downlink_reset,
-				CLEAR												=> downlink_clear,
-				---------------------------------------------------------------------------------------------------------------------------------------------------------
-				LINK_DISABLE_IN								=> sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
-				---------------------------------------------------------------------------------------------------------------------------------------------------------
---				MED_DATA_IN(0*16+15 downto 0*16)			=> med_data_out(1*16+15 downto 1*16),
-				MED_DATA_IN(0)									=> med_data_out(1*16+15 downto 1*16),
-				MED_DATA_IN(1)									=> med_data_out(6*16+15 downto 6*16),
-				MED_DATA_IN(2)									=> med_data_out(4*16+15 downto 4*16),
-				MED_DATA_IN(3)									=> med_data_out(2*16+15 downto 2*16),
-
---				MED_PACKET_NUM_IN(0*3+2 downto 0*3)		=> med_packet_num_out(1*3+2 downto 1*3),
-				MED_PACKET_NUM_IN(0)							=> med_packet_num_out(1*3+2 downto 1*3),
-				MED_PACKET_NUM_IN(1)							=> med_packet_num_out(6*3+2 downto 6*3),
-				MED_PACKET_NUM_IN(2)							=> med_packet_num_out(2*3+2 downto 2*3),
-				MED_PACKET_NUM_IN(3)							=> med_packet_num_out(4*3+2 downto 4*3),
-
-				MED_DATAREADY_IN(0)							=> med_dataready_out(1),
-				MED_DATAREADY_IN(1)							=> med_dataready_out(6),
-				MED_DATAREADY_IN(2)							=> med_dataready_out(2),
-				MED_DATAREADY_IN(3)							=> med_dataready_out(4),
-
-				MED_READ_OUT(0)								=> med_read_in(1),
-				MED_READ_OUT(1)								=> med_read_in(6),
-				MED_READ_OUT(2)								=> med_read_in(2),
-				MED_READ_OUT(3)								=> med_read_in(4),
-
---				MED_DATA_OUT(0*16+15 downto 0*16)		=> med_data_in(1*16+15 downto 1*16),
-				MED_DATA_OUT(0)								=> med_data_in(1*16+15 downto 1*16),
-				MED_DATA_OUT(1)								=> med_data_in(6*16+15 downto 6*16),
-				MED_DATA_OUT(2)								=> med_data_in(2*16+15 downto 2*16),
-				MED_DATA_OUT(3)								=> med_data_in(4*16+15 downto 4*16),
-
---				MED_PACKET_NUM_OUT(0*3+2 downto 0*3)	=> med_packet_num_in(1*3+2 downto 1*3),
-				MED_PACKET_NUM_OUT(0)						=> med_packet_num_in(1*3+2 downto 1*3),
-				MED_PACKET_NUM_OUT(1)						=> med_packet_num_in(6*3+2 downto 6*3),
-				MED_PACKET_NUM_OUT(2)						=> med_packet_num_in(2*3+2 downto 2*3),
-				MED_PACKET_NUM_OUT(3)						=> med_packet_num_in(4*3+2 downto 4*3),
-
-				MED_DATAREADY_OUT(0)							=> med_dataready_in(1),
-				MED_DATAREADY_OUT(1)							=> med_dataready_in(6),
-				MED_DATAREADY_OUT(2)							=> med_dataready_in(2),
-				MED_DATAREADY_OUT(3)							=> med_dataready_in(4),
-
-				MED_READ_IN(0)									=> med_read_out(1),
-				MED_READ_IN(1)									=> med_read_out(6),
-				MED_READ_IN(2)									=> med_read_out(2),
-				MED_READ_IN(3)									=> med_read_out(4),
-
-				RX_HALF_CLK_OUT(0)							=> rxdn_half_clk(0),
-				RX_HALF_CLK_OUT(1)							=> rxdn_half_clk(1),
-				RX_HALF_CLK_OUT(2)							=> rxdn_half_clk(2),
-				RX_HALF_CLK_OUT(3)							=> rxdn_half_clk(3),
-
-				RX_FULL_CLK_OUT(0)							=> rxdn_full_clk(0),	-- needed for sync replies i.e. calibration
-				RX_FULL_CLK_OUT(1)							=> rxdn_full_clk(1),	-- needed for sync replies i.e. calibration
-				RX_FULL_CLK_OUT(2)							=> rxdn_full_clk(2),	-- needed for sync replies i.e. calibration
-				RX_FULL_CLK_OUT(3)							=> rxdn_full_clk(3),	-- needed for sync replies i.e. calibration
-
-				TX_HALF_CLK_OUT(0)							=> txdn_half_clk(0),
-				TX_HALF_CLK_OUT(1)							=> txdn_half_clk(1),
-				TX_HALF_CLK_OUT(2)							=> txdn_half_clk(2),
-				TX_HALF_CLK_OUT(3)							=> txdn_half_clk(3),
-
-				TX_FULL_CLK_OUT(0)							=> txdn_full_clk(0),
-				TX_FULL_CLK_OUT(1)							=> txdn_full_clk(1),
-				TX_FULL_CLK_OUT(2)							=> txdn_full_clk(2),
-				TX_FULL_CLK_OUT(3)							=> txdn_full_clk(3),
-
-				RX_DLM(0)										=> rxdn_dlm_i(0),
-				RX_DLM(1)										=> rxdn_dlm_i(1),
-				RX_DLM(2)										=> rxdn_dlm_i(2),
-				RX_DLM(3)										=> rxdn_dlm_i(3),
-				
-				RX_DLM_WORD(0)									=> rxdn_dlm_word(0),
-				RX_DLM_WORD(1)									=> rxdn_dlm_word(1),
-				RX_DLM_WORD(2)									=> rxdn_dlm_word(2),
-				RX_DLM_WORD(3)									=> rxdn_dlm_word(3),
-				
-				TX_DLM(0)										=> txdn_dlm_i(0),
-				TX_DLM(1)										=> txdn_dlm_i(1),
-				TX_DLM(2)										=> txdn_dlm_i(2),
-				TX_DLM(3)										=> txdn_dlm_i(3),
-				
-				TX_DLM_WORD(0)									=> txdn_dlm_word(0),
-				TX_DLM_WORD(1)									=> txdn_dlm_word(1),
-				TX_DLM_WORD(2)									=> txdn_dlm_word(2),
-				TX_DLM_WORD(3)									=> txdn_dlm_word(3),
-
-				TX_DLM_PREVIEW_IN(0)							=> txdn_dlm_preview_S(0),			--PL!
-				TX_DLM_PREVIEW_IN(1)							=> txdn_dlm_preview_S(1),			--PL!
-				TX_DLM_PREVIEW_IN(2)							=> txdn_dlm_preview_S(2),			--PL!
-				TX_DLM_PREVIEW_IN(3)							=> txdn_dlm_preview_S(3),			--PL!
-
-				LINK_PHASE_OUT(0)								=>	dnlink_phase_S(0),				--PL!
-				LINK_PHASE_OUT(1)								=>	dnlink_phase_S(1),				--PL!
-				LINK_PHASE_OUT(2)								=>	dnlink_phase_S(2),				--PL!
-				LINK_PHASE_OUT(3)								=>	dnlink_phase_S(3),				--PL!
-
-				--SFP Connection
-				SD_RXD_P_IN(0)									=> SERDES_ADDON_RX(0),			-- B0
-				SD_RXD_P_IN(1)									=> SERDES_ADDON_RX(1),
-				SD_RXD_P_IN(2)									=> SERDES_ADDON_RX(10),			-- B1
-				SD_RXD_P_IN(3)									=> SERDES_ADDON_RX(11),	
-				SD_RXD_N_IN(0)									=> SERDES_ADDON_RX(2),			-- B2
-				SD_RXD_N_IN(1)									=> SERDES_ADDON_RX(3),
-				SD_RXD_N_IN(2)									=> SERDES_ADDON_RX(6),			-- B3
-				SD_RXD_N_IN(3)									=> SERDES_ADDON_RX(7),
-				SD_TXD_P_OUT(0)								=> SERDES_ADDON_TX(0),			-- B0
-				SD_TXD_P_OUT(1)								=> SERDES_ADDON_TX(1),
-				SD_TXD_P_OUT(2)								=> SERDES_ADDON_TX(10),			-- B1
-				SD_TXD_P_OUT(3)								=> SERDES_ADDON_TX(11),
-				SD_TXD_N_OUT(0)								=> SERDES_ADDON_TX(2),			-- B2
-				SD_TXD_N_OUT(1)								=> SERDES_ADDON_TX(3),
-				SD_TXD_N_OUT(2)								=> SERDES_ADDON_TX(6),			-- B3
-				SD_TXD_N_OUT(3)								=> SERDES_ADDON_TX(7),
-				SD_REFCLK_P_IN									=> (others => '0'),
-				SD_REFCLK_N_IN									=> ('0','0','0','0'),
-				SD_PRSNT_N_IN(0)								=> SFP_MOD0(1),
-				SD_PRSNT_N_IN(1)								=> SFP_MOD0(6),
-				SD_PRSNT_N_IN(2)								=> SFP_MOD0(2),
-				SD_PRSNT_N_IN(3)								=> SFP_MOD0(4),
-				SD_LOS_IN(0)									=> SFP_LOS(1),
-				SD_LOS_IN(1)									=> SFP_LOS(6),
-				SD_LOS_IN(2)									=> SFP_LOS(2),
-				SD_LOS_IN(3)									=> SFP_LOS(4),
-				SD_TXDIS_OUT(0)								=> sfp_txdis_S(1),
-				SD_TXDIS_OUT(1)								=> sfp_txdis_S(6),
-				SD_TXDIS_OUT(2)								=> sfp_txdis_S(2),
-				SD_TXDIS_OUT(3)								=> sfp_txdis_S(4),
-
-				SCI_DATA_IN										=> sci2_data_in,
-				SCI_DATA_OUT									=> sci2_data_out,
-				SCI_ADDR											=> sci2_addr,
-				SCI_READ											=> sci2_read,
-				SCI_WRITE										=> sci2_write,
-				SCI_ACK											=> sci2_ack, 
-				SCI_NACK											=> sci2_nack,
-
-				--Status and control port
-				STAT_OP(15 downto 0)							=> med_stat_op(1*16+15 downto 1*16),
-				STAT_OP(31 downto 16)						=> med_stat_op(6*16+15 downto 6*16),
-				STAT_OP(47 downto 32)						=> med_stat_op(2*16+15 downto 2*16),
-				STAT_OP(63 downto 48)						=> med_stat_op(4*16+15 downto 4*16),
-
-				CTRL_OP(15 downto 0)							=> med_ctrl_op(1*16+15 downto 1*16),
-				CTRL_OP(31 downto 16)						=> med_ctrl_op(6*16+15 downto 6*16),
-				CTRL_OP(47 downto 32)						=> med_ctrl_op(2*16+15 downto 2*16),
-				CTRL_OP(63 downto 48)						=> med_ctrl_op(4*16+15 downto 4*16),
-
-				STAT_DEBUG										=> open,
-				CTRL_DEBUG										=> (others => '0')
-		);
-
-
----------------------------------------------------------------------------
--- TRB-Hub
----------------------------------------------------------------------------
-	med_stat_op(3*16+15 downto 3*16) <= x"0007";		--	 !PL telling the hub that this port is inactive	08192014
-	med_stat_op(5*16+15 downto 5*16) <= x"0007";		--	 !PL telling the hub that this port is inactive	08192014
-
-	TRB_HUB : trb_net16_hub_base
-	generic map (
-			HUB_USED_CHANNELS				=> (c_NO,c_NO,c_NO,c_YES),
-			IBUF_SECURE_MODE				=> c_YES,
-			MII_NUMBER						=> 7,
-			MII_IS_UPLINK					=> (0 => 1, others => 0),
-			MII_IS_DOWNLINK				=> (0 => 0, others => 1),
-			MII_IS_UPLINK_ONLY			=> (0 => 1, others => 0),
-			INT_NUMBER						=> 0,
-		--	INT_CHANNELS					=> (0,1,3,3,3,3,3,3),
-			USE_ONEWIRE						=> c_YES,
-			COMPILE_TIME					=> std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
-			HARDWARE_VERSION				=> x"91003200",
-			INIT_ENDPOINT_ID				=> x"0000",
-			INIT_ADDRESS					=> x"F357",
-			USE_VAR_ENDPOINT_ID			=> c_YES,
-			BROADCAST_SPECIAL_ADDR		=> x"45",
-			CLOCK_FREQUENCY				=> CLOCK_FREQUENCY
-		)
-	port map (
-		CLK											=> rxup_half_clk,	--clk_100_osc,
-		RESET											=> reset_i,
-		CLK_EN										=> '1',
-
-		--Media interfacces
-		MED_DATAREADY_OUT(7*1-1 downto 0)	=> med_dataready_out,
-		MED_DATA_OUT(7*16-1 downto 0)			=> med_data_out,
-		MED_PACKET_NUM_OUT(7*3-1 downto 0)	=> med_packet_num_out,
-		MED_READ_IN(7*1-1 downto 0)			=> med_read_in,
-		MED_DATAREADY_IN(7*1-1 downto 0)		=> med_dataready_in,
-		MED_DATA_IN(7*16-1 downto 0)			=> med_data_in,
-		MED_PACKET_NUM_IN(7*3-1 downto 0)	=> med_packet_num_in,
-		MED_READ_OUT(7*1-1 downto 0)			=> med_read_out,
-		MED_STAT_OP(7*16-1 downto 0)			=> med_stat_op,
-		MED_CTRL_OP(7*16-1 downto 0)			=> med_ctrl_op,
-
-		COMMON_STAT_REGS							=> common_stat_reg,
-		COMMON_CTRL_REGS							=> common_ctrl_reg,
-		MY_ADDRESS_OUT								=> my_address,
-		--REGIO INTERFACE
-		REGIO_ADDR_OUT								=> regio_addr_out,
-		REGIO_READ_ENABLE_OUT					=> regio_read_enable_out,
-		REGIO_WRITE_ENABLE_OUT					=> regio_write_enable_out,
-		REGIO_DATA_OUT								=> regio_data_out,
-		REGIO_DATA_IN								=> regio_data_in,
-		REGIO_DATAREADY_IN						=> regio_dataready_in,
-		REGIO_NO_MORE_DATA_IN					=> regio_no_more_data_in,
-		REGIO_WRITE_ACK_IN						=> regio_write_ack_in,
-		REGIO_UNKNOWN_ADDR_IN					=> regio_unknown_addr_in,
-		REGIO_TIMEOUT_OUT							=> regio_timeout_out,
-		REGIO_VAR_ENDPOINT_ID(1 downto 0)	=> CODE_LINE,
-		REGIO_VAR_ENDPOINT_ID(15 downto 2)	=> (others => '0'),
-		ONEWIRE										=> TEMPSENS,
-		ONEWIRE_MONITOR_OUT						=> open,
-		--Status ports (for debugging)
-		MPLEX_CTRL									=> (others => '0'),
-		CTRL_DEBUG									=> (others => '0'),
-		STAT_DEBUG									=> open
-	);
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
---	LED_ORANGE <= SFP_LOS(3);			--med_stat_op(8);
---	LED_YELLOW <= sfp_txdis_S(3);		--med_stat_op(10);
---	LED_GREEN  <= med_stat_op(12);	--tx_pll_lol
---	LED_RED    <= med_stat_op(11);	--rx_cdr_lol
-	LED_ORANGE		<= SFP_LOS(1);	--'1' when (time_counter(26)='0') else '0';
-	LED_YELLOW		<= SFP_LOS(2);	--'1' when (time_counter(26)='0') else '0';
-	LED_GREEN		<= SFP_LOS(3);	--time_counter(26);
-	LED_RED			<= SFP_LOS(4);	--time_counter(26);
-	
----------------------------------------------------------------------------
--- GREEN LED under sfp
----------------------------------------------------------------------------    
-	LED_LINKOK(1)	<= SFP_LOS(1);
-	LED_LINKOK(2)	<=	SFP_LOS(2);
-	LED_LINKOK(3)	<= SFP_LOS(3);
-	LED_LINKOK(4)	<= SFP_LOS(4);
-	LED_LINKOK(5)	<= SFP_LOS(5);
-	LED_LINKOK(6)	<= SFP_LOS(6);
-
-	LED_RX(1) 		<= '1' when (med_stat_op(10)='0') else '0'; 	-- rx_allow
-	LED_RX(2) 		<= '1';
-	LED_RX(3) 		<= '1';
-	LED_RX(4) 		<= '1';
-	LED_RX(5) 		<= '1';
-	LED_RX(6) 		<= '1';
-	
-	LED_TX(1) 		<= '1' when (med_stat_op(9)='0') else '0'; 	-- tx_allow
-	LED_TX(2) 		<= '1';
-	LED_TX(3) 		<= '1';
-	LED_TX(4) 		<= '1';
-	LED_TX(5) 		<= '1';
-	LED_TX(6) 		<= '1';
-
----------------------------------------------------------------------------
--- DEBUG
----------------------------------------------------------------------------    
-	link_debug_in_S(31 downto 16)	<= med_stat_op(15 downto 0);
-	link_debug_in_S(15 downto 0)	<= (3 => pll_lock, others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-
-
-	blink : process (clk_200_osc)
-	begin
-		if rising_edge(clk_200_osc) then
-			if (time_counter = x"FFFFFFFF") then
-				time_counter <= x"00000000";
-			else
-				time_counter <= time_counter + 1;
-			end if;
-		end if;
-   end process;
-
-
-end trb3_periph_sodahub_arch;
\ No newline at end of file
diff --git a/code/trb3_periph_sodasource.vhd b/code/trb3_periph_sodasource.vhd
deleted file mode 100644
index 23653f5..0000000
--- a/code/trb3_periph_sodasource.vhd
+++ /dev/null
@@ -1,719 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all; 
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodasource is
-  generic(
-    SYNC_MODE : integer range 0 to 1 := c_NO;   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
-    USE_125_MHZ : integer := c_NO;
-    CLOCK_FREQUENCY : integer := 100;
-    NUM_INTERFACES : integer := 2
-    );
-  port(
-    --Clocks 
-		CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
-		CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
-		CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-		CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
-    --serdes I/O - connect as you like, no real use
-		SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
-		SERDES_ADDON_RX      : in  std_logic_vector(15 downto 0);
-
-    --Inter-FPGA Communication
-    FPGA5_COMM : inout std_logic_vector(11 downto 0);
-                                                      --Bit 0/1 input, serial link RX active
-                                                      --Bit 2/3 output, serial link TX active
-                                                      --others yet undefined
-    --Connection to AddOn
-    LED_LINKOK : out std_logic_vector(6 downto 1);
-    LED_RX     : out std_logic_vector(6 downto 1); 
-    LED_TX     : out std_logic_vector(6 downto 1);
-    SFP_MOD0   : in  std_logic_vector(6 downto 1);
-    SFP_TXDIS  : out std_logic_vector(6 downto 1); 
-    SFP_LOS    : in  std_logic_vector(6 downto 1);
-    --Flash ROM & Reboot 
-    FLASH_CLK  : out   std_logic;
-    FLASH_CS   : out   std_logic;
-    FLASH_DIN  : out   std_logic;
-    FLASH_DOUT : in    std_logic;
-    PROGRAMN   : out   std_logic;                     --reboot FPGA
-
-    --Misc
-    TEMPSENS   : inout std_logic;       --Temperature Sensor
-    CODE_LINE  : in    std_logic_vector(1 downto 0);
-    LED_GREEN  : out   std_logic;
-    LED_ORANGE : out   std_logic;
-    LED_RED    : out   std_logic;
-    LED_YELLOW : out   std_logic;
-    SUPPL      : in    std_logic;       --terminated diff pair, PCLK, Pads
-
-    --Test Connectors
-    TEST_LINE : out std_logic_vector(15 downto 0)
-    );
-
-
-	attribute syn_useioff                  : boolean;
-	--no IO-FF for LEDs relaxes timing constraints
-	attribute syn_useioff of LED_GREEN		: signal is false;
-	attribute syn_useioff of LED_ORANGE		: signal is false;
-	attribute syn_useioff of LED_RED			: signal is false;
-	attribute syn_useioff of LED_YELLOW		: signal is false;
-	attribute syn_useioff of TEMPSENS			: signal is false;
-	attribute syn_useioff of PROGRAMN			: signal is false;
-	attribute syn_useioff of CODE_LINE		: signal is false;
-	attribute syn_useioff of LED_LINKOK		: signal is false;
-	attribute syn_useioff of LED_TX			: signal is false;
-	attribute syn_useioff of LED_RX			: signal is false;
-	attribute syn_useioff of SFP_MOD0			: signal is false;
-	attribute syn_useioff of SFP_TXDIS		: signal is false;
-	attribute syn_useioff of SFP_LOS			: signal is false;
-	attribute syn_useioff of TEST_LINE		: signal is false;
-
-	--important signals _with_ IO-FF
-	attribute syn_useioff of FLASH_CLK		: signal is true;
-	attribute syn_useioff of FLASH_CS			: signal is true;
-	attribute syn_useioff of FLASH_DIN		: signal is true;
-	attribute syn_useioff of FLASH_DOUT		: signal is true;
-	attribute syn_useioff of FPGA5_COMM		: signal is true;
-
-
-end entity;
-
-architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
-	--Constants
-	constant REGIO_NUM_STAT_REGS : integer := 0;
-	constant REGIO_NUM_CTRL_REGS : integer := 2;
-
-	attribute syn_keep     : boolean;
-	attribute syn_preserve : boolean;
-
-	constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
-
-	--Clock / Reset
-	--  signal clk_sys_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
-	--  signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
-	signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
-	signal clear_i                  : std_logic;
-	signal reset_i                  : std_logic;
-	signal GSR_N                    : std_logic;
-	attribute syn_keep of GSR_N     : signal is true;
-	attribute syn_preserve of GSR_N : signal is true;
-	signal clk_100_osc         : std_logic;
-	signal clk_200_osc         : std_logic;
---	signal rx_clock_half             : std_logic;
---	signal rx_clock_full             : std_logic;
---	signal clk_tdc                  : std_logic;
-	--Media Interface
-	signal med_stat_op        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_ctrl_op        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_stat_debug     : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-	signal med_ctrl_debug     : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-	signal med_data_out       : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-	signal med_dataready_out  : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_read_out       : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_data_in        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-	signal med_packet_num_in  : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-	signal med_dataready_in   : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-	signal med_read_in        : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
-	--Slow Control channel
-	signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-	signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-	signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-	signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
-	signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
-	signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-	signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
-	--RegIO
-	signal my_address             : std_logic_vector (15 downto 0);
-	signal regio_addr_out         : std_logic_vector (15 downto 0);
-	signal regio_read_enable_out  : std_logic;
-	signal regio_write_enable_out : std_logic;
-	signal regio_data_out         : std_logic_vector (31 downto 0);
-	signal regio_data_in          : std_logic_vector (31 downto 0);
-	signal regio_dataready_in     : std_logic;
-	signal regio_no_more_data_in  : std_logic;
-	signal regio_write_ack_in     : std_logic;
-	signal regio_unknown_addr_in  : std_logic;
-	signal regio_timeout_out      : std_logic;
-
-	--Timer
-	signal global_time         : std_logic_vector(31 downto 0);
-	signal local_time          : std_logic_vector(7 downto 0);
-	signal time_since_last_trg : std_logic_vector(31 downto 0);
-	signal timer_ticks         : std_logic_vector(1 downto 0);
-
-	--Flash
-	signal spimem_read_en          : std_logic;
-	signal spimem_write_en         : std_logic;
-	signal spimem_data_in          : std_logic_vector(31 downto 0);
-	signal spimem_addr             : std_logic_vector(8 downto 0);
-	signal spimem_data_out         : std_logic_vector(31 downto 0);
-	signal spimem_dataready_out    : std_logic;
-	signal spimem_no_more_data_out : std_logic;
-	signal spimem_unknown_addr_out : std_logic;
-	signal spimem_write_ack_out    : std_logic;
-
-	signal sci1_ack      : std_logic;
-	signal sci1_write    : std_logic;
-	signal sci1_read     : std_logic;
-	signal sci1_data_in  : std_logic_vector(7 downto 0);
-	signal sci1_data_out : std_logic_vector(7 downto 0);
-	signal sci1_addr     : std_logic_vector(8 downto 0);  
-	signal sci2_ack      : std_logic;
-	signal sci2_nack     : std_logic;
-	signal sci2_write    : std_logic;
-	signal sci2_read     : std_logic;
-	signal sci2_data_in  : std_logic_vector(7 downto 0);
-	signal sci2_data_out : std_logic_vector(7 downto 0);
-	signal sci2_addr     : std_logic_vector(8 downto 0);  
-	signal sfp_txdis_S	: std_logic_vector(6 downto 1) := (others => '1'); 
-
-	--SODA
-	signal soda_ack      : std_logic;
-	signal soda_write    : std_logic;
-	signal soda_read     : std_logic;
-	signal soda_data_in  : std_logic_vector(31 downto 0);
-	signal soda_data_out : std_logic_vector(31 downto 0);
-	signal soda_addr     : std_logic_vector(3 downto 0);  
-	signal soda_leds     : std_logic_vector(3 downto 0);  
-
-
-	--TDC
-	signal hit_in_i : std_logic_vector(63 downto 0);
-	  
-	signal soda_rx_clock_half : std_logic;
-	signal soda_rx_clock_full : std_logic;
-	signal soda_tx_clock_half : std_logic;
-	signal soda_tx_clock_full : std_logic;
-	signal tx_dlm_i          : std_logic;
-	signal rx_dlm_i          : std_logic;
-	signal tx_dlm_word       : std_logic_vector(7 downto 0);
-	signal rx_dlm_word       : std_logic_vector(7 downto 0);
-	signal tx_dlm_preview_S			: std_logic;	--PL!
-	signal link_phase_S			: std_logic;	--PL!
-
-	--SODA
-	signal SOB_S							: std_logic := '0';
-	signal soda_40mhz_cycle_S			: std_logic := '0';
-  	-- fix signal names for constraining
-	attribute syn_preserve		of soda_rx_clock_full	: signal is true;
-	attribute syn_keep			of soda_rx_clock_full	: signal is true;
-	attribute syn_preserve		of soda_rx_clock_half	: signal is true;
-	attribute syn_keep			of soda_rx_clock_half	: signal is true;
-	attribute syn_preserve		of soda_tx_clock_full	: signal is true;
-	attribute syn_keep			of soda_tx_clock_full	: signal is true;
-	attribute syn_preserve		of soda_tx_clock_half	: signal is true;
-	attribute syn_keep			of soda_tx_clock_half	: signal is true;
-	attribute syn_preserve		of clk_100_osc		: signal is true;
-	attribute syn_keep			of clk_100_osc		: signal is true;
-	attribute syn_preserve		of clk_200_osc		: signal is true;
-	attribute syn_keep			of clk_200_osc		: signal is true;
-	attribute syn_preserve		of tx_dlm_i					: signal is true;
-	attribute syn_keep			of tx_dlm_i					: signal is true;
-	attribute syn_preserve		of rx_dlm_i					: signal is true;
-	attribute syn_keep			of rx_dlm_i					: signal is true;
-	attribute syn_preserve		of soda_40mhz_cycle_S	: signal is true;
-	attribute syn_keep			of soda_40mhz_cycle_S	: signal is true;
-
-	
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-  GSR_N <= pll_lock;
-
-  THE_RESET_HANDLER : trb_net_reset_handler
-    generic map(
-      RESET_DELAY => x"FEEE"
-      )
-    port map(
-      CLEAR_IN      => '0',              -- reset input (high active, async)
-      CLEAR_N_IN    => '1',              -- reset input (low active, async)
-      CLK_IN        => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
-      SYSCLK_IN     => clk_100_osc,        -- PLL/DLL remastered clock
-      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
-      RESET_IN      => '0',              -- general reset signal (SYSCLK)
-      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
-      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
-      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
-      DEBUG_OUT     => open
-      );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
-	THE_MAIN_PLL : pll_in200_out100
-		port map(
-			CLK   => CLK_GPLL_RIGHT,
-			RESET => '0',
-			CLKOP => clk_100_osc,
-			CLKOK => clk_200_osc,
-			LOCK  => pll_lock
-		);
-end generate;      
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
-  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
-    generic map(
-      SERDES_NUM  => 1,     --number of serdes in quad
-      EXT_CLOCK   => c_NO,  --use internal clock
-      USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
-      USE_125_MHZ => USE_125_MHZ,
-      USE_CTC     => c_NO,
-      USE_SLAVE   => SYNC_MODE
-      )      
-    port map(
-      CLK                => clk_200_osc,
-      SYSCLK             => clk_100_osc,
-      RESET              => reset_i,
-      CLEAR              => clear_i,
-      CLK_EN             => '1',
-      --Internal Connection
-      MED_DATA_IN        => med_data_out(15 downto 0),
-      MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
-      MED_DATAREADY_IN   => med_dataready_out(0),
-      MED_READ_OUT       => med_read_in(0),
-      MED_DATA_OUT       => med_data_in(15 downto 0),
-      MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
-      MED_DATAREADY_OUT  => med_dataready_in(0),
-      MED_READ_IN        => med_read_out(0),
-      REFCLK2CORE_OUT    => open,
-      CLK_RX_HALF_OUT    => open,	--rx_clock_half,
-      CLK_RX_FULL_OUT    => open,	--rx_clock_full,
-     
-      --SFP Connection
-      SD_RXD_P_IN        => SERDES_ADDON_RX(2),
-      SD_RXD_N_IN        => SERDES_ADDON_RX(3),
-      SD_TXD_P_OUT       => SERDES_ADDON_TX(2),
-      SD_TXD_N_OUT       => SERDES_ADDON_TX(3),
-      SD_REFCLK_P_IN     => '0',
-      SD_REFCLK_N_IN     => '0',
-      SD_PRSNT_N_IN      => FPGA5_COMM(0),
-      SD_LOS_IN          => FPGA5_COMM(0),
-      SD_TXDIS_OUT       => FPGA5_COMM(2),
-      
-      SCI_DATA_IN        => sci1_data_in,
-      SCI_DATA_OUT       => sci1_data_out,
-      SCI_ADDR           => sci1_addr,
-      SCI_READ           => sci1_read,
-      SCI_WRITE          => sci1_write,
-      SCI_ACK            => sci1_ack,        
-      -- Status and control port
-      STAT_OP            => med_stat_op(15 downto 0),
-      CTRL_OP            => med_ctrl_op(15 downto 0),
-      STAT_DEBUG         => open, --med_stat_debug(63 downto 0),
-      CTRL_DEBUG         => (others => '0')
-      );
-
-
----------------------------------------------------------------------------
--- Hub 
----------------------------------------------------------------------------
-
-THE_HUB : trb_net16_hub_base
-  generic map (
-    HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),
-    IBUF_SECURE_MODE  => c_YES,
-    MII_NUMBER        => NUM_INTERFACES,
-    MII_IS_UPLINK     => (0 => 1, others => 0),
-    MII_IS_DOWNLINK   => (0 => 0, others => 1),
-    MII_IS_UPLINK_ONLY=> (0 => 1, others => 0),
-    INT_NUMBER        => 0,
-    USE_ONEWIRE       => c_YES,
-    COMPILE_TIME      => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
---    COMPILE_TIME      => VERSION_NUMBER_TIME, 
-    HARDWARE_VERSION  => x"91003200",
-    INIT_ENDPOINT_ID  => x"0000",
-    INIT_ADDRESS      => x"F355",
-    USE_VAR_ENDPOINT_ID => c_YES,
-    BROADCAST_SPECIAL_ADDR => x"45",
-    CLOCK_FREQUENCY   => CLOCK_FREQUENCY
-    )
-  port map (
-    CLK    => clk_100_osc,	--clk_sys_i,		PL! 30062014
-    RESET  => reset_i,
-    CLK_EN => '1',
-
-    --Media interfacces
-    MED_DATAREADY_OUT(NUM_INTERFACES*1-1 downto 0)   => med_dataready_out,
-    MED_DATA_OUT(NUM_INTERFACES*16-1 downto 0)       => med_data_out,
-    MED_PACKET_NUM_OUT(NUM_INTERFACES*3-1 downto 0)  => med_packet_num_out,
-    MED_READ_IN(NUM_INTERFACES*1-1 downto 0)         => med_read_in,
-    MED_DATAREADY_IN(NUM_INTERFACES*1-1 downto 0)    => med_dataready_in,
-    MED_DATA_IN(NUM_INTERFACES*16-1 downto 0)        => med_data_in,
-    MED_PACKET_NUM_IN(NUM_INTERFACES*3-1 downto 0)   => med_packet_num_in,
-    MED_READ_OUT(NUM_INTERFACES*1-1 downto 0)        => med_read_out,
-    MED_STAT_OP(NUM_INTERFACES*16-1 downto 0)        => med_stat_op,
-    MED_CTRL_OP(NUM_INTERFACES*16-1 downto 0)        => med_ctrl_op,
-
-    COMMON_STAT_REGS                => common_stat_reg,
-    COMMON_CTRL_REGS                => common_ctrl_reg,
-    MY_ADDRESS_OUT                  => open,
-    --REGIO INTERFACE
-    REGIO_ADDR_OUT                  => regio_addr_out,
-    REGIO_READ_ENABLE_OUT           => regio_read_enable_out,
-    REGIO_WRITE_ENABLE_OUT          => regio_write_enable_out,
-    REGIO_DATA_OUT                  => regio_data_out,
-    REGIO_DATA_IN                   => regio_data_in,
-    REGIO_DATAREADY_IN              => regio_dataready_in,
-    REGIO_NO_MORE_DATA_IN           => regio_no_more_data_in,
-    REGIO_WRITE_ACK_IN              => regio_write_ack_in,
-    REGIO_UNKNOWN_ADDR_IN           => regio_unknown_addr_in,
-    REGIO_TIMEOUT_OUT               => regio_timeout_out,
-    REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
-    REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-    ONEWIRE                         => TEMPSENS,
-    ONEWIRE_MONITOR_OUT             => open,
-    --Status ports (for debugging)
-    MPLEX_CTRL            => (others => '0'),
-    CTRL_DEBUG            => (others => '0'),
-    STAT_DEBUG            => open
-    );
-
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
-  THE_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER    => 4,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 9,       3 => 4,       others => 0)
-      )
-    port map(
-		CLK							=> clk_100_osc,
-      RESET							=> reset_i,
-
-      DAT_ADDR_IN					=> regio_addr_out,
-      DAT_DATA_IN					=> regio_data_out,
-      DAT_DATA_OUT				=> regio_data_in,
-      DAT_READ_ENABLE_IN		=> regio_read_enable_out,
-      DAT_WRITE_ENABLE_IN		=> regio_write_enable_out,
-      DAT_TIMEOUT_IN				=> regio_timeout_out,
-      DAT_DATAREADY_OUT			=> regio_dataready_in,
-      DAT_WRITE_ACK_OUT			=> regio_write_ack_in,
-      DAT_NO_MORE_DATA_OUT		=> regio_no_more_data_in,
-      DAT_UNKNOWN_ADDR_OUT		=> regio_unknown_addr_in,
-
-      BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
-      BUS_READ_ENABLE_OUT(1)              => sci1_read,
-      BUS_READ_ENABLE_OUT(2)              => sci2_read,
-      BUS_READ_ENABLE_OUT(3)              => soda_read,
-
-      BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
-      BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
-      BUS_WRITE_ENABLE_OUT(2)             => sci2_write,
-      BUS_WRITE_ENABLE_OUT(3)             => soda_write,
-      
-		BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
-      BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
-      BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
-      BUS_DATA_OUT(2*32+7 downto 2*32)    => sci2_data_in,
-      BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
-      BUS_DATA_OUT(3*32+31 downto 3*32)   => soda_data_in,
-      
-		BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
-      BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
-      BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
-      BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
-      BUS_ADDR_OUT(2*16+8 downto 2*16)    => sci2_addr,
-      BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
-      BUS_ADDR_OUT(3*16+3 downto 3*16)   	=> soda_addr,
-      BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
-      
-		BUS_TIMEOUT_OUT(0)                  => open,
-      BUS_TIMEOUT_OUT(1)                  => open,
-      BUS_TIMEOUT_OUT(2)                  => open,
-      BUS_TIMEOUT_OUT(3)                  => open,
-      
-		BUS_DATA_IN(0*32+31	downto 0*32)	=> spimem_data_out,
-      BUS_DATA_IN(1*32+7	downto 1*32)	=> sci1_data_out,
-      BUS_DATA_IN(1*32+31	downto 1*32+8)	=> (others => '0'),
-      BUS_DATA_IN(2*32+7	downto 2*32)	=> sci2_data_out,
-      BUS_DATA_IN(2*32+31	downto 2*32+8)	=> (others => '0'),
-      BUS_DATA_IN(3*32+31	downto 3*32)	=> soda_data_out,
-      
-		BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
-      BUS_DATAREADY_IN(1)                 => sci1_ack,
-      BUS_DATAREADY_IN(2)                 => sci2_ack,
-      BUS_DATAREADY_IN(3)                 => soda_ack,
-      
-		BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
-      BUS_WRITE_ACK_IN(1)                 => sci1_ack,
-      BUS_WRITE_ACK_IN(2)                 => sci2_ack,
-      BUS_WRITE_ACK_IN(3)                 => soda_ack,
-      
-		BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
-      BUS_NO_MORE_DATA_IN(1)              => '0',
-      BUS_NO_MORE_DATA_IN(2)              => '0',
-      BUS_NO_MORE_DATA_IN(3)              => '0',
-      
-		BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
-      BUS_UNKNOWN_ADDR_IN(1)              => '0',
-      BUS_UNKNOWN_ADDR_IN(2)              => sci2_nack,
-      BUS_UNKNOWN_ADDR_IN(3)              => '0',
-
-		STAT_DEBUG => open
-      );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD :  spi_flash_and_fpga_reload	--.flash_reboot_arch
-  port map(
-	 CLK_IN						=> clk_100_osc,
-    RESET_IN					=> reset_i,
-    
-    BUS_ADDR_IN          => spimem_addr,
-    BUS_READ_IN          => spimem_read_en,
-    BUS_WRITE_IN         => spimem_write_en,
-    BUS_DATAREADY_OUT    => spimem_dataready_out,
-    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
-    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
-    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
-    BUS_DATA_IN          => spimem_data_in,
-    BUS_DATA_OUT         => spimem_data_out,
-    
-    DO_REBOOT_IN         => common_ctrl_reg(15),     
-    PROGRAMN             => PROGRAMN,
-    
-    SPI_CS_OUT           => FLASH_CS,
-    SPI_SCK_OUT          => FLASH_CLK,
-    SPI_SDO_OUT          => FLASH_DIN,
-    SPI_SDI_IN           => FLASH_DOUT
-    );
-
-      
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------      
-
-THE_SYNC_LINK : med_ecp3_sfp_sync_down
-	generic map(
-		SERDES_NUM  => 0,    --number of serdes in quad
-		IS_SYNC_SLAVE => c_NO
-		)
-	port map(
-      OSCCLK					=> clk_200_osc,
-      SYSCLK					=> clk_100_osc,
- 		RESET						=> reset_i,
-		CLEAR						=> clear_i,
-		--Internal Connection for TrbNet data -> not used a.t.m.
-		MED_DATA_IN				=> med_data_out(31 downto 16),
-		MED_PACKET_NUM_IN		=> med_packet_num_out(5 downto 3),
-		MED_DATAREADY_IN		=> med_dataready_out(1),
-		MED_READ_OUT			=> med_read_in(1),
-		MED_DATA_OUT			=> med_data_in(31 downto 16),
-		MED_PACKET_NUM_OUT	=> med_packet_num_in(5 downto 3),
-		MED_DATAREADY_OUT		=> med_dataready_in(1),
-		MED_READ_IN				=> med_read_out(1),
-		RX_HALF_CLK_OUT		=> soda_rx_clock_half,
-		RX_FULL_CLK_OUT		=> soda_rx_clock_full,
-		TX_HALF_CLK_OUT		=> soda_tx_clock_half,
-		TX_FULL_CLK_OUT		=> soda_tx_clock_full,
-
-		RX_DLM					=> rx_dlm_i,
-		RX_DLM_WORD				=> rx_dlm_word,
-		TX_DLM					=> tx_dlm_i,
-		TX_DLM_WORD				=> tx_dlm_word,
-		TX_DLM_PREVIEW_IN		=> tx_dlm_preview_S,			--PL!
-		LINK_PHASE_OUT			=>	link_phase_S,		--PL!
-		--SFP Connection
-		SD_RXD_P_IN				=> SERDES_ADDON_RX(0),
-		SD_RXD_N_IN				=> SERDES_ADDON_RX(1),
-		SD_TXD_P_OUT			=> SERDES_ADDON_TX(0),
-		SD_TXD_N_OUT			=> SERDES_ADDON_TX(1),
-		SD_REFCLK_P_IN			=> '0',
-		SD_REFCLK_N_IN			=> '0',
-		SD_PRSNT_N_IN			=> SFP_MOD0(1),
-		SD_LOS_IN				=> SFP_LOS(1),
-		SD_TXDIS_OUT			=> sfp_txdis_S(1),	--SFP_TXDIS(1),
-
-		SCI_DATA_IN				=> sci2_data_in,
-		SCI_DATA_OUT			=> sci2_data_out,
-		SCI_ADDR					=> sci2_addr,
-		SCI_READ					=> sci2_read,
-		SCI_WRITE				=> sci2_write,
-		SCI_ACK					=> sci2_ack,  
-		SCI_NACK					=> sci2_nack,
-		-- Status and control port
-		STAT_OP					=> med_stat_op(31 downto 16),
-		CTRL_OP					=> med_ctrl_op(31 downto 16),
-		STAT_DEBUG				=> med_stat_debug(63 downto 0),
-		CTRL_DEBUG				=> (others => '0')
-	);      
-
--- THE_SYNC_LINK : med_ecp3_sfp_sync
---    generic map(
---       SERDES_NUM  => 0,    --number of serdes in quad
---       IS_SYNC_SLAVE => c_NO
---       )
---    port map(
---       CLK                  => clk_200_osc,
---       SYSCLK               => clk_100_osc,
---       RESET                => reset_i,
---       CLEAR                => clear_i,
---       --Internal Connection for TrbNet data -> not used a.t.m.
---       MED_DATA_IN          => med_data_out(31 downto 16),
---       MED_PACKET_NUM_IN    => med_packet_num_out(5 downto 3),
---       MED_DATAREADY_IN     => med_dataready_out(1),
---       MED_READ_OUT         => med_read_in(1),
---       MED_DATA_OUT         => med_data_in(31 downto 16),
---       MED_PACKET_NUM_OUT   => med_packet_num_in(5 downto 3),
---       MED_DATAREADY_OUT    => med_dataready_in(1),
---       MED_READ_IN          => med_read_out(1),
---       CLK_RX_HALF_OUT      => soda_rx_clock_half,
---       CLK_RX_FULL_OUT      => soda_rx_clock_full,
--- --       TX_HALF_CLK_OUT      => soda_tx_clock_half,
--- --       TX_FULL_CLK_OUT      => soda_tx_clock_full,
--- 
---       RX_DLM               => rx_dlm_i,
---       RX_DLM_WORD          => rx_dlm_word,
---       TX_DLM               => tx_dlm_i,
---       TX_DLM_WORD          => tx_dlm_word,
--- --       TX_DLM_PREVIEW_IN    => tx_dlm_preview_S,       --PL!
--- --       LINK_PHASE_OUT       => link_phase_S,     --PL!
---       --SFP Connection
---       SD_RXD_P_IN          => SERDES_ADDON_RX(0),
---       SD_RXD_N_IN          => SERDES_ADDON_RX(1),
---       SD_TXD_P_OUT         => SERDES_ADDON_TX(0),
---       SD_TXD_N_OUT         => SERDES_ADDON_TX(1),
---       SD_REFCLK_P_IN       => '0',
---       SD_REFCLK_N_IN       => '0',
---       SD_PRSNT_N_IN        => SFP_MOD0(1),
---       SD_LOS_IN            => SFP_LOS(1),
---       SD_TXDIS_OUT         => sfp_txdis_S(1),   --SFP_TXDIS(1),
--- 
---       SCI_DATA_IN          => sci2_data_in,
---       SCI_DATA_OUT         => sci2_data_out,
---       SCI_ADDR             => sci2_addr,
---       SCI_READ             => sci2_read,
---       SCI_WRITE            => sci2_write,
---       SCI_ACK              => sci2_ack,  
---       SCI_NACK             => sci2_nack,
---       -- Status and control port
---       STAT_OP              => med_stat_op(31 downto 16),
---       CTRL_OP              => med_ctrl_op(31 downto 16),
---       STAT_DEBUG           => med_stat_debug(63 downto 0),
---       CTRL_DEBUG           => (others => '0')
---    );    	
-	
-	SFP_TXDIS(1)	<=	sfp_txdis_S(1);
-
-	
----------------------------------------------------------------------------
--- Burst- and 40MHz cycle generator
----------------------------------------------------------------------------         
-
-THE_SOB_SOURCE : soda_start_of_burst_control
-	generic map(
-		CLOCK_PERIOD				=> cSODA_CLOCK_PERIOD,	-- clock-period in ns
-		CYCLE_PERIOD				=> cSODA_CYCLE_PERIOD,	-- cycle-period in ns
-		BURST_PERIOD				=> cBURST_PERIOD			-- burst-period in ns
-		)
-	port map(
-		SODA_CLK						=> clk_200_osc,
-		RESET							=> reset_i,
-		SODA_BURST_PULSE_OUT		=> SOB_S,
-		SODA_40MHZ_CYCLE_OUT		=>	soda_40mhz_cycle_S
-	);
-
----------------------------------------------------------------------------
--- The Soda Central
----------------------------------------------------------------------------         
-	 
-THE_SODA_SOURCE : soda_source
-	port map(
-		SYSCLK					=> soda_tx_clock_half,	--clk_100_osc,	--clk_sys_i,	PL! 30062014
-		SODACLK					=> soda_tx_clock_full,	--clk_200_osc,	--					PL! 30062014
-		RESET						=> reset_i,
-
-		SODA_BURST_PULSE_IN	=> SOB_S,
-		SODA_CYCLE_IN				=> soda_40mhz_cycle_S,
-
-		RX_DLM_WORD_IN			=> rx_dlm_word,
-		RX_DLM_IN				=> rx_dlm_i,
-		TX_DLM_OUT				=> tx_dlm_i, 
-		TX_DLM_WORD_OUT		=> tx_dlm_word,
-		TX_DLM_PREVIEW_OUT	=> tx_dlm_preview_S,
-		LINK_PHASE_IN			=> link_phase_S,
-		SODA_DATA_IN			=> soda_data_in,
-		SODA_DATA_OUT			=> soda_data_out,
-		SODA_ADDR_IN			=> soda_addr,
-		SODA_READ_IN			=> soda_read,
-		SODA_WRITE_IN			=> soda_write,
-		SODA_ACK_OUT			=> soda_ack,
-		LEDS_OUT					=>	soda_leds
-	);
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
---	LED_ORANGE <= SFP_LOS(3);			--med_stat_op(8);
---	LED_YELLOW <= sfp_txdis_S(3);		--med_stat_op(10);
---	LED_GREEN  <= med_stat_op(12);	--tx_pll_lol
---	LED_RED    <= med_stat_op(11);	--rx_cdr_lol
-	LED_ORANGE		<= '1' when (med_stat_op(26)='0') else '0';
-	LED_YELLOW		<= '1' when (med_stat_op(26)='0') else '0';
-	LED_GREEN		<= med_stat_op(11);
-	LED_RED			<= med_stat_op(10);
-	
-
----------------------------------------------------------------------------
--- GREEN LED under sfp
----------------------------------------------------------------------------    
-	LED_LINKOK(1)	<= not med_stat_op(9);
-	LED_LINKOK(2)	<=	SFP_LOS(2);
-	LED_LINKOK(3)	<= SFP_LOS(3);
-	LED_LINKOK(4)	<= SFP_LOS(4);
-	LED_LINKOK(5)	<= SFP_LOS(5);
-	LED_LINKOK(6)	<= SFP_LOS(6);
-
-	LED_RX(1) 		<= not (med_stat_op(11) or med_stat_op(10));
-	LED_RX(2) 		<= '1';
-	LED_RX(3) 		<= '1';
-	LED_RX(4) 		<= '1';
-	LED_RX(5) 		<= '1';
-	LED_RX(6) 		<= '1';
-	
-	LED_TX(1) 		<= not med_stat_op(12);
-	LED_TX(2) 		<= '1';
-	LED_TX(3) 		<= '1';
-	LED_TX(4) 		<= '1';
-	LED_TX(5) 		<= '1';
-	LED_TX(6) 		<= '1';
-
--- STAT_OP(12) <= led_dlm or last_led_dlm;
--- STAT_OP(11) <= led_tx or last_led_tx;
--- STAT_OP(10) <= led_rx or last_led_rx;
--- STAT_OP(9)  <= led_ok;	
-			
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------    
- TEST_LINE(13 downto 0) <= med_stat_debug(13 downto 0);
- TEST_LINE(14) <= soda_rx_clock_half;
- TEST_LINE(15) <= soda_tx_clock_half;
-
-end trb3_periph_sodasource_arch;
\ No newline at end of file
diff --git a/code/trb_net16_med_1_2sync_3_ecp3_sfp.vhd b/code/trb_net16_med_1_2sync_3_ecp3_sfp.vhd
deleted file mode 100644
index c8b2c04..0000000
--- a/code/trb_net16_med_1_2sync_3_ecp3_sfp.vhd
+++ /dev/null
@@ -1,1151 +0,0 @@
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-
-entity trb_net16_med_1_2sync_3_ecp3_sfp is
-  port(
-    CLK                : in  std_logic; -- SerDes clock
-    SYSCLK             : in  std_logic; -- fabric clock
-    RESET              : in  std_logic; -- synchronous reset
-    CLEAR              : in  std_logic; -- asynchronous reset
-    CLK_EN             : in  std_logic;
-    --Internal Connection
-    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
-    MED_DATAREADY_IN   : in  std_logic;
-    MED_READ_OUT       : out std_logic;
-    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
-    MED_DATAREADY_OUT  : out std_logic;
-    MED_READ_IN        : in  std_logic;
-    REFCLK2CORE_OUT    : out std_logic;
-    CLK_RX_HALF_OUT    : out std_logic;
-    CLK_RX_FULL_OUT    : out std_logic;
-    --SFP Connection
-    SD_RXD_P_IN        : in  std_logic;
-    SD_RXD_N_IN        : in  std_logic;
-    SD_TXD_P_OUT       : out std_logic;
-    SD_TXD_N_OUT       : out std_logic;
-    SD_REFCLK_P_IN     : in  std_logic;
-    SD_REFCLK_N_IN     : in  std_logic;
-    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-    SD_TXDIS_OUT       : out  std_logic; -- SFP disable
-    --Control Interface
-    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
-    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
-    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
-    SCI_READ           : in  std_logic := '0';
-    SCI_WRITE          : in  std_logic := '0';
-    SCI_ACK            : out std_logic := '0';
-    SCI_NACK           : out std_logic := '0';
-	-- SODA serdes channel
-    SODA_RXD_P_IN      : in  std_logic;
-    SODA_RXD_N_IN      : in  std_logic;
-    SODA_TXD_P_OUT     : out std_logic;
-    SODA_TXD_N_OUT     : out std_logic;
-	SODA_DLM_IN        : in  std_logic;
-	SODA_DLM_WORD_IN   : in  std_logic_vector(7 downto 0);
-	SODA_DLM_OUT       : out  std_logic;
-	SODA_DLM_WORD_OUT  : out  std_logic_vector(7 downto 0);
-    SODA_CLOCK_OUT     : out  std_logic; -- 200MHz
-	
-    -- Connection to addon interface        
-    DOUT_TXD_P_OUT     : out  std_logic;
-    DOUT_TXD_N_OUT     : out  std_logic;
-    SFP_MOD0_5         : in  std_logic;
-    SFP_MOD0_3         : in  std_logic;          
-    SFP_LOS_5          : in  std_logic;          
-    SFP_LOS_3          : in  std_logic;
-	TX_READY_CH3       : out std_logic;
-    TX_DATA_CH3        : in std_logic_vector(7 downto 0);
-    TX_K_CH3           : in std_logic;
-    -- Status and control port
-    STAT_OP            : out std_logic_vector (15 downto 0);
-    CTRL_OP            : in  std_logic_vector (15 downto 0);
-    STAT_DEBUG         : out std_logic_vector (63 downto 0);
-    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
-   );
-end entity;
-
-architecture trb_net16_med_1_2sync_3_ecp3_sfp_arch of trb_net16_med_1_2sync_3_ecp3_sfp is
-
-
-  -- Placer Directives
-  attribute HGROUP : string;
-  -- for whole architecture
-  attribute HGROUP of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture  is "media_interface_group";
-  attribute syn_sharing : string;
-  attribute syn_sharing of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture is "off";
-
-  --OJK 29-nov-2013
-	component sfp_1_3_200_int
-	port(
-		hdinp_ch1          : IN std_logic;
-		hdinn_ch1          : IN std_logic;
-		sci_sel_ch1        : IN std_logic;
-		rxiclk_ch1         : IN std_logic;
-		txiclk_ch1         : IN std_logic;
-		fpga_rxrefclk_ch1  : IN std_logic;
-		txdata_ch1         : IN std_logic_vector(15 downto 0);
-		tx_k_ch1           : IN std_logic_vector(1 downto 0);
-		tx_force_disp_ch1  : IN std_logic_vector(1 downto 0);
-		tx_disp_sel_ch1    : IN std_logic_vector(1 downto 0);
-		sb_felb_ch1_c      : IN std_logic;
-		sb_felb_rst_ch1_c  : IN std_logic;
-		tx_pwrup_ch1_c     : IN std_logic;
-		rx_pwrup_ch1_c     : IN std_logic;
-		tx_div2_mode_ch1_c : IN std_logic;
-		rx_div2_mode_ch1_c : IN std_logic;
-		sci_sel_ch3        : IN std_logic;
-		txiclk_ch3         : IN std_logic;
-		fpga_rxrefclk_ch3  : IN std_logic;
-		txdata_ch3         : IN std_logic_vector(7 downto 0);
-		tx_k_ch3           : IN std_logic;
-		tx_force_disp_ch3  : IN std_logic;
-		tx_disp_sel_ch3    : IN std_logic;
-		tx_pwrup_ch3_c     : IN std_logic;
-		tx_div2_mode_ch3_c : IN std_logic;
-		sci_wrdata         : IN std_logic_vector(7 downto 0);
-		sci_addr           : IN std_logic_vector(5 downto 0);
-		sci_sel_quad       : IN std_logic;
-		sci_rd             : IN std_logic;
-		sci_wrn            : IN std_logic;
-		fpga_txrefclk      : IN std_logic;
-		tx_serdes_rst_c    : IN std_logic;
-		tx_sync_qd_c       : IN std_logic;
-		rst_n              : IN std_logic;
-		serdes_rst_qd_c    : IN std_logic;          
-		hdoutp_ch1         : OUT std_logic;
-		hdoutn_ch1         : OUT std_logic;
-		rx_full_clk_ch1    : OUT std_logic;
-		rx_half_clk_ch1    : OUT std_logic;
-		tx_full_clk_ch1    : OUT std_logic;
-		tx_half_clk_ch1    : OUT std_logic;
-		rxdata_ch1         : OUT std_logic_vector(15 downto 0);
-		rx_k_ch1           : OUT std_logic_vector(1 downto 0);
-		rx_disp_err_ch1    : OUT std_logic_vector(1 downto 0);
-		rx_cv_err_ch1      : OUT std_logic_vector(1 downto 0);
-		rx_los_low_ch1_s   : OUT std_logic;
-		lsm_status_ch1_s   : OUT std_logic;
-		rx_cdr_lol_ch1_s   : OUT std_logic;
-		hdoutp_ch3         : OUT std_logic;
-		hdoutn_ch3         : OUT std_logic;
-		tx_full_clk_ch3    : OUT std_logic;
-		tx_half_clk_ch3    : OUT std_logic;
-		sci_rddata         : OUT std_logic_vector(7 downto 0);
-		tx_pll_lol_qd_s    : OUT std_logic;
-		refclk2fpga        : OUT std_logic
-			);
-	end component;
-  
--- Peter Schakel 02-12-14
-component sfp_1_2sync_3_200_int is
- port (
-------------------
--- CH0 --
--- CH1 --
-    hdinp_ch1, hdinn_ch1    :   in std_logic;
-    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
-    sci_sel_ch1    :   in std_logic;
-    rxiclk_ch1    :   in std_logic;
-    txiclk_ch1    :   in std_logic;
-    rx_full_clk_ch1   :   out std_logic;
-    rx_half_clk_ch1   :   out std_logic;
-    tx_full_clk_ch1   :   out std_logic;
-    tx_half_clk_ch1   :   out std_logic;
-    fpga_rxrefclk_ch1    :   in std_logic;
-    txdata_ch1    :   in std_logic_vector (15 downto 0);
-    tx_k_ch1    :   in std_logic_vector (1 downto 0);
-    tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
-    tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
-    rxdata_ch1   :   out std_logic_vector (15 downto 0);
-    rx_k_ch1   :   out std_logic_vector (1 downto 0);
-    rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
-    rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
-    rx_serdes_rst_ch1_c    :   in std_logic;
-    sb_felb_ch1_c    :   in std_logic;
-    sb_felb_rst_ch1_c    :   in std_logic;
-    tx_pcs_rst_ch1_c    :   in std_logic;
-    tx_pwrup_ch1_c    :   in std_logic;
-    rx_pcs_rst_ch1_c    :   in std_logic;
-    rx_pwrup_ch1_c    :   in std_logic;
-    rx_los_low_ch1_s   :   out std_logic;
-    lsm_status_ch1_s   :   out std_logic;
-    rx_cdr_lol_ch1_s   :   out std_logic;
-    tx_div2_mode_ch1_c   : in std_logic;
-    rx_div2_mode_ch1_c   : in std_logic;
--- CH2 --
-    hdinp_ch2, hdinn_ch2    :   in std_logic;
-    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
-    sci_sel_ch2    :   in std_logic;
-    rxiclk_ch2    :   in std_logic;
-    txiclk_ch2    :   in std_logic;
-    rx_full_clk_ch2   :   out std_logic;
-    rx_half_clk_ch2   :   out std_logic;
-    tx_full_clk_ch2   :   out std_logic;
-    tx_half_clk_ch2   :   out std_logic;
-    fpga_rxrefclk_ch2    :   in std_logic;
-    txdata_ch2    :   in std_logic_vector (7 downto 0);
-    tx_k_ch2    :   in std_logic;
-    tx_force_disp_ch2    :   in std_logic;
-    tx_disp_sel_ch2    :   in std_logic;
-    rxdata_ch2   :   out std_logic_vector (7 downto 0);
-    rx_k_ch2   :   out std_logic;
-    rx_disp_err_ch2   :   out std_logic;
-    rx_cv_err_ch2   :   out std_logic;
-    rx_serdes_rst_ch2_c    :   in std_logic;
-    sb_felb_ch2_c    :   in std_logic;
-    sb_felb_rst_ch2_c    :   in std_logic;
-    tx_pcs_rst_ch2_c    :   in std_logic;
-    tx_pwrup_ch2_c    :   in std_logic;
-    rx_pcs_rst_ch2_c    :   in std_logic;
-    rx_pwrup_ch2_c    :   in std_logic;
-    rx_los_low_ch2_s   :   out std_logic;
-    lsm_status_ch2_s   :   out std_logic;
-    rx_cdr_lol_ch2_s   :   out std_logic;
-    tx_div2_mode_ch2_c   : in std_logic;
-    rx_div2_mode_ch2_c   : in std_logic;
--- CH3 --
-    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
-    sci_sel_ch3    :   in std_logic;
-    txiclk_ch3    :   in std_logic;
-    tx_full_clk_ch3   :   out std_logic;
-    tx_half_clk_ch3   :   out std_logic;
-    txdata_ch3    :   in std_logic_vector (7 downto 0);
-    tx_k_ch3    :   in std_logic;
-    tx_force_disp_ch3    :   in std_logic;
-    tx_disp_sel_ch3    :   in std_logic;
-    tx_pcs_rst_ch3_c    :   in std_logic;
-    tx_pwrup_ch3_c    :   in std_logic;
-    tx_div2_mode_ch3_c   : in std_logic;
----- Miscillaneous ports
-    sci_wrdata    :   in std_logic_vector (7 downto 0);
-    sci_addr    :   in std_logic_vector (5 downto 0);
-    sci_rddata   :   out std_logic_vector (7 downto 0);
-    sci_sel_quad    :   in std_logic;
-    sci_rd    :   in std_logic;
-    sci_wrn    :   in std_logic;
-    fpga_txrefclk  :   in std_logic;
-    tx_serdes_rst_c    :   in std_logic;
-    tx_pll_lol_qd_s   :   out std_logic;
-    tx_sync_qd_c    :   in std_logic;
-    rst_qd_c    :   in std_logic;
-    serdes_rst_qd_c    :   in std_logic);
-
-end component;
-
- 
-  
-  signal refck2core             : std_logic;
---  signal clock                  : std_logic;
-  --reset signals
-  signal ffc_quad_rst           : std_logic;
-  signal ffc_lane_tx_rst        : std_logic;
-  signal ffc_lane_rx_rst        : std_logic;
-  --serdes connections
-  signal tx_data                : std_logic_vector(15 downto 0);
-  signal tx_k                   : std_logic_vector(1 downto 0);
-  signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals
-  signal rx_k                   : std_logic_vector(1 downto 0);  -- delayed signals
-  signal comb_rx_data           : std_logic_vector(15 downto 0); -- original signals from SFP
-  signal comb_rx_k              : std_logic_vector(1 downto 0);  -- original signals from SFP
-  signal link_ok                : std_logic_vector(1 downto 0); -- OJK 02-dec-2013: Changed width from 1 bit to 2 bits
-  signal link_error             : std_logic_vector(10 downto 0);-- OJK 02-dec-2013: Changed width from 10 bits to 11 bits
-  signal ff_txhalfclk           : std_logic;
-  signal ff_rxhalfclk			      : std_logic;
-  signal ff_rxfullclk           : std_logic;
-  --rx fifo signals
-  signal fifo_rx_rd_en          : std_logic;
-  signal fifo_rx_wr_en          : std_logic;
-  signal fifo_rx_reset          : std_logic;
-  signal fifo_rx_din            : std_logic_vector(17 downto 0);
-  signal fifo_rx_dout           : std_logic_vector(17 downto 0);
-  signal fifo_rx_full           : std_logic;
-  signal fifo_rx_empty          : std_logic;
-  --tx fifo signals
-  signal fifo_tx_rd_en          : std_logic;
-  signal fifo_tx_wr_en          : std_logic;
-  signal fifo_tx_reset          : std_logic;
-  signal fifo_tx_din            : std_logic_vector(17 downto 0);
-  signal fifo_tx_dout           : std_logic_vector(17 downto 0);
-  signal fifo_tx_full           : std_logic;
-  signal fifo_tx_empty          : std_logic;
-  signal fifo_tx_almost_full    : std_logic;
-  --rx path
-  signal rx_counter             : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-  signal buf_med_dataready_out  : std_logic;
-  signal buf_med_data_out       : std_logic_vector(c_DATA_WIDTH-1 downto 0);
-  signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-  signal last_rx                : std_logic_vector(8 downto 0);
-  signal last_fifo_rx_empty     : std_logic;
-  --tx path
-  signal last_fifo_tx_empty     : std_logic;
-  --link status
-  signal rx_k_q                 : std_logic_vector(1 downto 0);
-
-  signal quad_rst               : std_logic;
-  signal lane_rst               : std_logic;
-  signal tx_allow               : std_logic;
-  signal rx_allow               : std_logic;
-  signal tx_allow_qtx           : std_logic;
-
-  signal rx_allow_q             : std_logic; -- clock domain changed signal
-  signal tx_allow_q             : std_logic;
-  signal swap_bytes             : std_logic;
-  signal buf_stat_debug         : std_logic_vector(31 downto 0);
-
-  -- status inputs from SFP
-  signal sfp_prsnt_n            : std_logic; -- synchronized input signals
-  signal sfp_los                : std_logic; -- synchronized input signals
-
-  signal buf_STAT_OP            : std_logic_vector(15 downto 0);
-
-  signal led_counter            : unsigned(16 downto 0);
-  signal rx_led                 : std_logic;
-  signal tx_led                 : std_logic;
-
-
-  signal tx_correct             : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
-  signal first_idle             : std_logic; -- tag the first IDLE2 after data
-
-  signal reset_word_cnt    : unsigned(4 downto 0);
-  signal make_trbnet_reset : std_logic;
-  signal make_trbnet_reset_q : std_logic;
-  signal send_reset_words  : std_logic;
-  signal send_reset_words_q : std_logic;
-  signal send_reset_in      : std_logic;
-  signal send_reset_in_qtx  : std_logic;
-  signal reset_i                : std_logic;
-  signal reset_i_rx             : std_logic;
-  signal pwr_up                 : std_logic;
-  signal clear_n   : std_logic;
-
-  signal clk_sys : std_logic;
-  signal clk_tx  : std_logic;
-  signal clk_rx  : std_logic;
-  signal clk_rxref : std_logic;
-  signal clk_txref : std_logic;
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state         : sci_ctrl;
-  signal sci_ch_i        : std_logic_vector(3 downto 0);
-  signal sci_qd_i        : std_logic;
-  signal sci_reg_i       : std_logic;
-  signal sci_addr_i      : std_logic_vector(8 downto 0);
-  signal sci_data_in_i   : std_logic_vector(7 downto 0);
-  signal sci_data_out_i  : std_logic_vector(7 downto 0);
-  signal sci_read_i      : std_logic;
-  signal sci_write_i     : std_logic;
---  signal sci_write_shift_i : std_logic_vector(2 downto 0);
---  signal sci_read_shift_i  : std_logic_vector(2 downto 0);  
-  
-  --OJK 13-dec-2013
-  signal cnt             : integer range 0 to 10000;
-  signal tx_pll_lol_qd_i : std_logic;
-  -- Peter Schakel 3-dec-2014
- 	
-  signal sci_timer            : unsigned(12 downto 0) := (others => '0');
-  signal reset_n              : std_logic;
-  signal trb_rx_serdes_rst    : std_logic;
-  signal trb_rx_cdr_lol       : std_logic;
-  signal trb_rx_los_low       : std_logic;
-  signal trb_rx_pcs_rst       : std_logic;
-  signal trb_tx_pcs_rst       : std_logic;
-  signal rst_qd               : std_logic;
-  signal link_OK_S            : std_logic;
-  signal trb_rx_fsm_state     : std_logic_vector(3 downto 0);
-  
-  signal sync_clk_rx_full     : std_logic;
-  signal sync_clk_rx_half     : std_logic;
-  signal sync_clk_tx_full     : std_logic;
-  signal sync_clk_tx_half     : std_logic;
-  signal sync_tx_k            : std_logic;
-  signal sync_tx_data         : std_logic_vector(7 downto 0);
-
-  signal syncfifo_din         : std_logic_vector(17 downto 0);
-  signal syncfifo_dout        : std_logic_vector(17 downto 0);
-	  
-  signal sync_rx_k            : std_logic;
-  signal sync_rx_data         : std_logic_vector(7 downto 0);
-  signal sync_rx_serdes_rst   : std_logic;
-  signal sync_rx_cdr_lol      : std_logic;
-  signal sync_tx_pcs_rst      : std_logic;
-  signal sync_rx_pcs_rst      : std_logic;
-  signal sync_rx_los_low      : std_logic;
-  signal sync_lsm_status      : std_logic;
-  signal SD_tx_pcs_rst        : std_logic;
-  signal DLM_fifo_rd_en       : std_logic;
-  signal DLM_fifo_empty       : std_logic;
-  signal DLM_fifo_reading     : std_logic := '0';  
-  signal SODA_dlm_word_S      : std_logic_vector(7 downto 0);
-  signal DLM_received_S       : std_logic;
-  signal sync_wa_position_rx  : std_logic_vector(15 downto 0) := x"FFFF";
-  signal wa_position          : std_logic_vector(15 downto 0) := x"FFFF";
-  signal sync_rx_fsm_state    : std_logic_vector(3 downto 0);
-  signal sync_tx_fsm_state    : std_logic_vector(3 downto 0);
-  signal CH3_tx_fsm_state     : std_logic_vector(3 downto 0);
-
-  signal CLKdiv100_S          : std_logic;
-  signal sync_clk_rx_fulldiv100_S     : std_logic;
-			
-  attribute syn_keep : boolean;
-  attribute syn_preserve : boolean;
-  attribute syn_keep of led_counter : signal is true;
-  attribute syn_keep of send_reset_in : signal is true;
-  attribute syn_keep of reset_i : signal is true;
-  attribute syn_preserve of reset_i : signal is true;
-
-begin
-
---------------------------------------------------------------------------
--- Select proper clock configuration
---------------------------------------------------------------------------
-  clk_sys <= SYSCLK;
-  clk_tx  <= SYSCLK;
-  clk_rx  <= ff_rxhalfclk;
-  clk_rxref <= CLK;
-  clk_txref <= CLK;
-
-
-
-
---------------------------------------------------------------------------
--- Internal Lane Resets
---------------------------------------------------------------------------
-  clear_n <= not clear;
-
-
-  PROC_RESET : process(clk_sys)
-    begin
-      if rising_edge(clk_sys) then
-        reset_i <= RESET;
-        send_reset_in <= ctrl_op(15);
-        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
-      end if;
-    end process;
-
---------------------------------------------------------------------------
--- Synchronizer stages
---------------------------------------------------------------------------
-
--- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
-THE_SFP_STATUS_SYNC: signal_sync
-  generic map(
-    DEPTH => 3,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => sd_prsnt_n_in,
-    D_IN(1)  => sd_los_in,
-    CLK0     => clk_sys,
-    CLK1     => clk_sys,
-    D_OUT(0) => sfp_prsnt_n,
-    D_OUT(1) => sfp_los
-    );
-
-
-THE_RX_K_SYNC: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 4
-    )
-  port map(
-    RESET             => reset_i,
-    D_IN(1 downto 0)  => comb_rx_k,
-    D_IN(2)           => send_reset_words,
-    D_IN(3)           => make_trbnet_reset,
-    CLK0              => clk_rx, -- CHANGED
-    CLK1              => clk_sys,
-    D_OUT(1 downto 0) => rx_k_q,
-    D_OUT(2)          => send_reset_words_q,
-    D_OUT(3)          => make_trbnet_reset_q
-    );
-
-THE_RX_DATA_DELAY: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 16
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN     => comb_rx_data,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT    => rx_data
-    );
-
-THE_RX_K_DELAY: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN     => comb_rx_k,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT    => rx_k
-    );
-
-THE_RX_RESET: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 1
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => reset_i,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT(0) => reset_i_rx
-    );
-
--- Delay for ALLOW signals
-THE_RX_ALLOW_SYNC: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN(0)  => rx_allow,
-    D_IN(1)  => tx_allow,
-    CLK0     => clk_sys,
-    CLK1     => clk_sys,
-    D_OUT(0) => rx_allow_q,
-    D_OUT(1) => tx_allow_q
-    );
-
-THE_TX_SYNC: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => send_reset_in,
-    D_IN(1)  => tx_allow,
-    CLK0     => clk_tx,
-    CLK1     => clk_tx,
-    D_OUT(0) => send_reset_in_qtx,
-    D_OUT(1) => tx_allow_qtx
-    );
-
-
---------------------------------------------------------------------------
--- Main control state machine, startup control for SFP
---------------------------------------------------------------------------
-
-THE_SFP_LSM: trb_net16_lsm_sfp
-    generic map (
-      HIGHSPEED_STARTUP => c_YES
-      )
-    port map(
-      SYSCLK            => clk_sys,
-      RESET             => reset_i,
-      CLEAR             => clear,
-      SFP_MISSING_IN    => sfp_prsnt_n,
-      SFP_LOS_IN        => sfp_los,
-      SD_LINK_OK_IN     => link_OK_S, --//  ?? link_ok(0),
-      SD_LOS_IN         => link_error(8),
-      SD_TXCLK_BAD_IN   => link_error(5),
-      SD_RXCLK_BAD_IN   => link_error(4),
-      SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
-      SD_ALIGNMENT_IN	=> rx_k_q,
-      SD_CV_IN          => link_error(7 downto 6),
-      FULL_RESET_OUT    => quad_rst,
-      LANE_RESET_OUT    => lane_rst,
-      TX_ALLOW_OUT      => tx_allow,
-      RX_ALLOW_OUT      => rx_allow,
-      SWAP_BYTES_OUT    => swap_bytes,
-      STAT_OP           => buf_stat_op,
-      CTRL_OP           => ctrl_op,
-      STAT_DEBUG        => buf_stat_debug
-      );
-
-sd_txdis_out <= quad_rst or reset_i;
-
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
-ffc_quad_rst         <= quad_rst;
-ffc_lane_tx_rst      <= lane_rst;
-
-
-ffc_lane_rx_rst      <= lane_rst;
-
--- SerDes clock output to FPGA fabric
-REFCLK2CORE_OUT <= ff_rxhalfclk;
-CLK_RX_HALF_OUT <= ff_rxhalfclk;
-CLK_RX_FULL_OUT <= ff_rxfullclk;
-
-THE_SERDES: sfp_1_2sync_3_200_int port map(
-------------------
--- CH0 --
--- CH1 --
-      hdinp_ch1          => sd_rxd_p_in,                
-      hdinn_ch1          => sd_rxd_n_in,                
-      hdoutp_ch1         => sd_txd_p_out,              
-      hdoutn_ch1         => sd_txd_n_out,              
-
-      sci_sel_ch1        => sci_ch_i(1),
-      rxiclk_ch1         => clk_rx,                
-      txiclk_ch1         => clk_tx,                
-      rx_full_clk_ch1    => ff_rxfullclk,          
-      rx_half_clk_ch1    => ff_rxhalfclk,          
-      tx_full_clk_ch1    => open,                  
-      tx_half_clk_ch1    => ff_txhalfclk,          
-      fpga_rxrefclk_ch1  => clk_rxref,             
-      txdata_ch1         => tx_data,               
-      tx_k_ch1           => tx_k,                  
-      tx_force_disp_ch1  => tx_correct,            
-      tx_disp_sel_ch1    => "00",                  
-      rxdata_ch1         => comb_rx_data,          
-      rx_k_ch1           => comb_rx_k,             
-      rx_disp_err_ch1    => open,            
-      rx_cv_err_ch1      => link_error(7 downto 6),
-      rx_serdes_rst_ch1_c => trb_rx_serdes_rst,
-      sb_felb_ch1_c      => '0',                   
-      sb_felb_rst_ch1_c  => '0',                
-      tx_pcs_rst_ch1_c   => trb_tx_pcs_rst,
-      tx_pwrup_ch1_c     => '1',                   
-      rx_pcs_rst_ch1_c   => trb_rx_pcs_rst,
-      rx_pwrup_ch1_c     => '1',                   
-      rx_los_low_ch1_s   => trb_rx_los_low, -- link_error(8),         
-      lsm_status_ch1_s   => link_ok(0),            
-      rx_cdr_lol_ch1_s   => trb_rx_cdr_lol, -- link_error(4),         
-      tx_div2_mode_ch1_c => '0',                   
-      rx_div2_mode_ch1_c => '0',
-
--- CH2 --
-    hdinp_ch2            => SODA_RXD_P_IN,
-    hdinn_ch2            => SODA_RXD_N_IN,
-    hdoutp_ch2           => SODA_TXD_P_OUT,
-    hdoutn_ch2           => SODA_TXD_N_OUT,
-    sci_sel_ch2          => sci_ch_i(2),
-    rxiclk_ch2           => sync_clk_rx_full, -- ?? CLK,
-    txiclk_ch2           => sync_clk_tx_full, -- ??CLK, --????? clk_txref
-    rx_full_clk_ch2      => sync_clk_rx_full,
-    rx_half_clk_ch2      => sync_clk_rx_half,
-    tx_full_clk_ch2      => sync_clk_tx_full,
-    tx_half_clk_ch2      => sync_clk_tx_half,
-    fpga_rxrefclk_ch2    => CLK,
-    txdata_ch2           => sync_tx_data,
-    tx_k_ch2             => sync_tx_k,
-    tx_force_disp_ch2    => '0',
-    tx_disp_sel_ch2      => '0',
-    rxdata_ch2           => sync_rx_data,
-    rx_k_ch2             => sync_rx_k,
-    rx_disp_err_ch2      => open,
-    rx_cv_err_ch2        => open,
-    rx_serdes_rst_ch2_c  => sync_rx_serdes_rst,
-    sb_felb_ch2_c        => '0',
-    sb_felb_rst_ch2_c    => '0',
-    tx_pcs_rst_ch2_c     => sync_tx_pcs_rst,
-    tx_pwrup_ch2_c       => '1',
-    rx_pcs_rst_ch2_c     => sync_rx_pcs_rst,
-    rx_pwrup_ch2_c       => '1',
-    rx_los_low_ch2_s     => sync_rx_los_low,
-    lsm_status_ch2_s     => sync_lsm_status,
-    rx_cdr_lol_ch2_s     => sync_rx_cdr_lol,
-    tx_div2_mode_ch2_c   => '0',
-    rx_div2_mode_ch2_c   => '0',
-		
--- CH3 --
-      hdoutp_ch3         => DOUT_TXD_P_OUT,             
-      hdoutn_ch3         => DOUT_TXD_N_OUT,             
-      sci_sel_ch3        => '0', --disable access to channel 3 registers
-      txiclk_ch3         => clk_tx,             
-      tx_full_clk_ch3    => open,                
-      tx_half_clk_ch3    => open,        
---//????      fpga_rxrefclk_ch3  => clk_rxref,      
-      txdata_ch3         => tx_data_ch3,             
-      tx_k_ch3           => tx_k_ch3,
-      tx_force_disp_ch3  => '0',      
-      tx_disp_sel_ch3    => '0',        
-      tx_pcs_rst_ch3_c   => SD_tx_pcs_rst,
-      tx_pwrup_ch3_c     => '1',         
-      tx_div2_mode_ch3_c => '1', 
-
----- Miscillaneous ports
-      sci_wrdata         => sci_data_in_i,
-      sci_addr           => sci_addr_i(5 downto 0),
-      sci_rddata         => sci_data_out_i,
-      sci_sel_quad       => sci_qd_i,
-      sci_rd             => sci_read_i,
-      sci_wrn            => sci_write_i,
-      fpga_txrefclk      => clk_txref,               
-      tx_serdes_rst_c    => CLEAR,          
-      tx_pll_lol_qd_s    => tx_pll_lol_qd_i,          
-      tx_sync_qd_c       => '0',             -- Multiple channel transmit synchronization is not needed?
---//      refclk2fpga        => open,              -- Not needed?
-      rst_qd_c => rst_qd,
---//??      rst_n              => '1',                   
-      serdes_rst_qd_c    => ffc_quad_rst        
-	);
-
-      syncfifo_din(7 downto 0)  <= SODA_DLM_WORD_IN;
-      syncfifo_din(17 downto 8) <= (others => '0');
-	  SODA_dlm_word_S <= syncfifo_dout(7 downto 0);
-	  
-sync_DLM_tx: trb_net_fifo_16bit_bram_dualport
-generic map(
-  USE_STATUS_FLAGS => c_NO
-       )
-port map( read_clock_in  => sync_clk_tx_full,
-      write_clock_in     => sync_clk_rx_full, 
-      read_enable_in     => DLM_fifo_rd_en,
-      write_enable_in    => SODA_DLM_IN,
-      fifo_gsr_in        => reset,
-      write_data_in      => syncfifo_din,
-      read_data_out      => syncfifo_dout,
-      full_out           => open,
-      empty_out          => DLM_fifo_empty
-    );
-
-process(sync_clk_rx_full)
-begin
-  if rising_edge(sync_clk_rx_full) then
-	SODA_DLM_OUT <= '0';
-	if DLM_received_S='1' then
-		DLM_received_S <= '0';
-		SODA_DLM_OUT <= '1';
-		SODA_DLM_WORD_OUT <= sync_rx_data;
-	elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then
-		DLM_received_S <= '1';
-	end if;
-  end if;
-end process;  
-
-process(sync_clk_tx_full)
-begin
-  if rising_edge(sync_clk_tx_full) then
-	if DLM_fifo_rd_en='1' then
-		DLM_fifo_rd_en <= '0';
-		sync_tx_data <= SODA_dlm_word_S;
-		sync_tx_k <= '0';
-	elsif (DLM_fifo_empty='0') and (DLM_fifo_reading='1') then
-		DLM_fifo_rd_en <= '1';
-		sync_tx_data <= x"DC";
-		sync_tx_k <= '1';
-	elsif DLM_fifo_empty='0' then
-		DLM_fifo_reading <= '1';
-		DLM_fifo_rd_en <= '0';
-		sync_tx_data <= x"BC"; -- idle
-		sync_tx_k <= '1';		
-	else
-		DLM_fifo_reading <= '0';
-		DLM_fifo_rd_en <= '0';
-		sync_tx_data <= x"BC"; -- idle
-		sync_tx_k <= '1';
-	end if;
-  end if;
-end process;  
-SODA_CLOCK_OUT <= sync_clk_rx_full;
-
-
-link_error(8) <= trb_rx_los_low; -- loss of signal
-link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock 
-link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock
-
-reset_n <= '0' when (RESET='1') or (CLEAR='1')  else '1';
-
--------------------------------------------------      
--- Reset FSM & Link states
-------------------------------------------------- 
-THE_RX_FSM1: rx_reset_fsm
-  port map(
-    RST_N               => reset_n,
-    RX_REFCLK           => CLK,
-    TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
-    RX_SERDES_RST_CH_C  => trb_rx_serdes_rst,
-    RX_CDR_LOL_CH_S     => trb_rx_cdr_lol,
-    RX_LOS_LOW_CH_S     => trb_rx_los_low,
-    RX_PCS_RST_CH_C     => trb_rx_pcs_rst,
-    WA_POSITION         => "0000",
-    STATE_OUT           => trb_rx_fsm_state
-    );
-
-link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';
-THE_TX_FSM1: tx_reset_fsm
-  port map(
-    RST_N           => reset_n,
-    TX_REFCLK       => CLK,
-    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-    RST_QD_C        => rst_qd,
-    TX_PCS_RST_CH_C => trb_tx_pcs_rst,
-    STATE_OUT       => open
-    );
-
-THE_RX_FSM2: rx_reset_fsm
-  port map(
-    RST_N               => reset_n,
-    RX_REFCLK           => sync_clk_rx_full, --??CLK,
-    TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
-    RX_SERDES_RST_CH_C  => sync_rx_serdes_rst,
-    RX_CDR_LOL_CH_S     => sync_rx_cdr_lol,
-    RX_LOS_LOW_CH_S     => sync_rx_los_low,
-    RX_PCS_RST_CH_C     => sync_rx_pcs_rst,
-    WA_POSITION         => sync_wa_position_rx(11 downto 8),
-    STATE_OUT           => sync_rx_fsm_state
-    );
-SYNC_WA_POSITION : process(sync_clk_rx_full) --??CLK)
-begin
-  if rising_edge(sync_clk_rx_full) then
-    sync_wa_position_rx <= wa_position;
-  end if;
-end process;
-    
-THE_TX_FSM2: tx_reset_fsm
-  port map(
-    RST_N           => reset_n,
-    TX_REFCLK       => CLK,
-    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-    RST_QD_C        => open, --??
-    TX_PCS_RST_CH_C => sync_tx_pcs_rst,
-    STATE_OUT       => sync_tx_fsm_state
-    );
-	
-THE_TX_FSM3 : tx_reset_fsm
-  port map(
-    RST_N           => reset_n,
-    TX_REFCLK       => CLK,
-    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-    RST_QD_C        => open, --??
-    TX_PCS_RST_CH_C => SD_tx_pcs_rst,
-    STATE_OUT       => CH3_tx_fsm_state
-    );
-TX_READY_CH3 <= '1' when (CH3_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';
-	
-	
--------------------------------------------------------------------------
--- RX Fifo & Data output
--------------------------------------------------------------------------
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
-generic map(
-  USE_STATUS_FLAGS => c_NO
-       )
-port map( read_clock_in  => clk_sys,
-      write_clock_in     => clk_rx, -- CHANGED
-      read_enable_in     => fifo_rx_rd_en,
-      write_enable_in    => fifo_rx_wr_en,
-      fifo_gsr_in        => fifo_rx_reset,
-      write_data_in      => fifo_rx_din,
-      read_data_out      => fifo_rx_dout,
-      full_out           => fifo_rx_full,
-      empty_out          => fifo_rx_empty
-    );
-
-fifo_rx_reset <= reset_i or not rx_allow_q;
-fifo_rx_rd_en <= not fifo_rx_empty;
-
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
-THE_BYTE_SWAP_PROC: process(clk_rx)
-  begin
-    if rising_edge(clk_rx) then
-		last_rx <= rx_k(1) & rx_data(15 downto 8);
-		if( swap_bytes = '0' ) then
-		  fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
-		  fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
-		else
-		  fifo_rx_din   <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
-		  fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
-		end if;
-	end if;
-  end process THE_BYTE_SWAP_PROC;
-
-buf_med_data_out          <= fifo_rx_dout(15 downto 0);
-buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
-buf_med_packet_num_out    <= rx_counter;
-med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
-
-
-THE_CNT_RESET_PROC : process(clk_rx)
-  begin
-    if rising_edge(clk_rx) then
-		if reset_i_rx = '1' then
-		  send_reset_words  <= '0';
-		  make_trbnet_reset <= '0';
-		  reset_word_cnt    <= (others => '0');
-		else
-		  send_reset_words   <= '0';
-		  make_trbnet_reset  <= '0';
-		  if fifo_rx_din = "11" & x"FEFE" then
-			if reset_word_cnt(4) = '0' then
-			  reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
-			else
-			  send_reset_words <= '1';
-			end if;
-		  else
-			reset_word_cnt    <= (others => '0');
-			make_trbnet_reset <= reset_word_cnt(4);
-		  end if;
-		end if;
-	end if;
-  end process;
-
-
-THE_SYNC_PROC: process(clk_rx)
-  begin
-    if rising_edge(clk_rx) then
-		med_dataready_out     <= buf_med_dataready_out;
-		med_data_out          <= buf_med_data_out;
-		med_packet_num_out    <= buf_med_packet_num_out;
-		if reset_i = '1' then
-		  med_dataready_out <= '0';
-		end if;
-	end if;
-  end process;
-
-
---rx packet counter
----------------------
-THE_RX_PACKETS_PROC: process( clk_sys )
-  begin
-    if( rising_edge(clk_sys) ) then
-      last_fifo_rx_empty <= fifo_rx_empty;
-      if reset_i = '1' or rx_allow_q = '0' then
-        rx_counter <= c_H0;
-      else
-        if( buf_med_dataready_out = '1' ) then
-          if( rx_counter = c_max_word_number ) then
-            rx_counter <= (others => '0');
-          else
-            rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
-          end if;
-        end if;
-      end if;
-    end if;
-  end process;
-
---TX Fifo & Data output to Serdes
----------------------
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
-  generic map(
-    USE_STATUS_FLAGS => c_NO
-        )
-  port map( read_clock_in => clk_tx,
-        write_clock_in    => clk_sys,
-        read_enable_in    => fifo_tx_rd_en,
-        write_enable_in   => fifo_tx_wr_en,
-        fifo_gsr_in       => fifo_tx_reset,
-        write_data_in     => fifo_tx_din,
-        read_data_out     => fifo_tx_dout,
-        full_out          => fifo_tx_full,
-        empty_out         => fifo_tx_empty,
-        almost_full_out   => fifo_tx_almost_full
-      );
-
-fifo_tx_reset <= reset_i or not tx_allow_q;
-fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
-fifo_tx_rd_en <= tx_allow_qtx;
-
-
-THE_SERDES_INPUT_PROC: process( clk_tx )
-  begin
-    if( rising_edge(clk_tx) ) then
-      last_fifo_tx_empty <= fifo_tx_empty;
-      first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
-      if send_reset_in = '1' then
-        tx_data <= x"FEFE";
-        tx_k <= "11";
-      elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
-        tx_data <= x"50bc";
-        tx_k <= "01";
-        tx_correct <= first_idle & '0';
-      else
-        tx_data <= fifo_tx_dout(15 downto 0);
-        tx_k <= "00";
-        tx_correct <= "00";
-      end if;
-    end if;
-  end process THE_SERDES_INPUT_PROC;
-
--------------------------------------------------      
--- SCI
--------------------------------------------------      
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process(clk_sys)
-  variable cnt : integer range 0 to 4 := 0;
-begin
-  if( rising_edge(clk_sys) ) then
-	  SCI_ACK <= '0';
-	  case sci_state is
-		when IDLE =>
-		  sci_ch_i        <= x"0";
-		  sci_qd_i        <= '0';
-		  sci_reg_i       <= '0';
-		  sci_read_i      <= '0';
-		  sci_write_i     <= '0';
-		  sci_timer       <= sci_timer + 1;
-		  if SCI_READ = '1' or SCI_WRITE = '1' then
-			sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_addr_i    <= SCI_ADDR;
-			sci_data_in_i <= SCI_DATA_IN;
-			sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_state     <= SCTRL;
-		  elsif sci_timer(sci_timer'left) = '1' then
-			sci_timer     <= (others => '0');
-			sci_state     <= GET_WA;
-		  end if;      
-		when SCTRL =>
-		  if sci_reg_i = '1' then
---//			SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-			SCI_DATA_OUT  <= (others => '0');
-			SCI_ACK       <= '1';
-			sci_write_i   <= '0';
-			sci_read_i    <= '0';
-			sci_state     <= IDLE;
-		  else
-			sci_state     <= SCTRL_WAIT;
-		  end if;
-		when SCTRL_WAIT   =>
-		  sci_state       <= SCTRL_WAIT2;
-		when SCTRL_WAIT2  =>
-		  sci_state       <= SCTRL_FINISH;
-		when SCTRL_FINISH =>
-		  SCI_DATA_OUT    <= sci_data_out_i;
-		  SCI_ACK         <= '1';
-		  sci_write_i     <= '0';
-		  sci_read_i      <= '0';
-		  sci_state       <= IDLE;
-		
-		when GET_WA =>
-		  if cnt = 4 then
-			cnt           := 0;
-			sci_state     <= IDLE;
-		  else
-			sci_state     <= GET_WA_WAIT;
-			sci_addr_i    <= '0' & x"22";
-			sci_ch_i      <= x"0";
-			sci_ch_i(cnt) <= '1';
-			sci_read_i    <= '1';
-		  end if;
-		when GET_WA_WAIT  =>
-		  sci_state       <= GET_WA_WAIT2;
-		when GET_WA_WAIT2 =>
-		  sci_state       <= GET_WA_FINISH;
-		when GET_WA_FINISH =>
-		  wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-		  sci_state       <= GET_WA;    
-		  cnt             := cnt + 1;
-	  end case;
-	  
-	  if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-		SCI_NACK <= '1';
-	  else
-		SCI_NACK <= '0';
-	  end if;
-  end if;
-end process;
-    
-  
-
---Generate LED signals
-----------------------
-process( clk_sys )
-  begin
-    if rising_edge(clk_sys) then
-      led_counter <= led_counter + to_unsigned(1,1);
-
-      if buf_med_dataready_out = '1' then
-        rx_led <= '1';
-      elsif led_counter = 0 then
-        rx_led <= '0';
-      end if;
-
-      if tx_k(0) = '0' then
-        tx_led <= '1';
-      elsif led_counter = 0 then
-        tx_led <= '0';
-      end if;
-
-    end if;
-  end process;
-
-stat_op(15)           <= send_reset_words_q;
-stat_op(14)           <= buf_stat_op(14);
-stat_op(13)           <= make_trbnet_reset_q;
-stat_op(12)           <= '0';
-stat_op(11)           <= tx_led; --tx led
-stat_op(10)           <= rx_led; --rx led
-stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
-
--- Debug output
-stat_debug(15 downto 0)  <= rx_data;
-stat_debug(17 downto 16) <= rx_k;
-stat_debug(19 downto 18) <= (others => '0');
-stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
-stat_debug(24)           <= fifo_rx_rd_en;
-stat_debug(25)           <= fifo_rx_wr_en;
-stat_debug(26)           <= fifo_rx_reset;
-stat_debug(27)           <= fifo_rx_empty;
-stat_debug(28)           <= fifo_rx_full;
-stat_debug(29)           <= last_rx(8);
-stat_debug(30)           <= rx_allow_q;
-stat_debug(41 downto 31) <= (others => '0');
-stat_debug(42)           <= clk_sys;
-stat_debug(43)           <= clk_sys;
-stat_debug(59 downto 44) <= (others => '0');
-stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
-
---stat_debug(3 downto 0)   <= buf_stat_debug(3 downto 0); -- state_bits
---stat_debug(4)            <= buf_stat_debug(4); -- alignme
---stat_debug(5)            <= sfp_prsnt_n;
---stat_debug(6)            <= tx_k(0);
---stat_debug(7)            <= tx_k(1);
---stat_debug(8)            <= rx_k_q(0);
---stat_debug(9)            <= rx_k_q(1);
---stat_debug(18 downto 10) <= link_error;
---stat_debug(19)           <= '0';
---stat_debug(20)           <= link_ok(0);
---stat_debug(38 downto 21) <= fifo_rx_din;
---stat_debug(39)           <= swap_bytes;
---stat_debug(40)           <= buf_stat_debug(7); -- sfp_missing_in
---stat_debug(41)           <= buf_stat_debug(8); -- sfp_los_in
---stat_debug(42)           <= buf_stat_debug(6); -- resync
---stat_debug(59 downto 43) <= (others => '0');
---stat_debug(63 downto 60) <= link_error(3 downto 0);
-
-CLKdiv100_process: process(CLK)
-variable counter_V : integer range 0 to 99 := 0;
-begin
-	if (rising_edge(CLK)) then 
-		if counter_V<49 then -- 99 for 125MHz
-			counter_V := counter_V+1;
-		else
-			counter_V := 0;
-			CLKdiv100_S <= not CLKdiv100_S;
-		end if;
-	end if;
-end process;
-sync_clk_rx_fulldiv100_process: process(sync_clk_rx_full)
-variable counter_V : integer range 0 to 99 := 0;
-begin
-	if (rising_edge(sync_clk_rx_full)) then 
-		if counter_V<49 then -- 99 for 125MHz
-			counter_V := counter_V+1;
-		else
-			counter_V := 0;
-			sync_clk_rx_fulldiv100_S <= not sync_clk_rx_fulldiv100_S;
-		end if;
-	end if;
-end process;
-
-end architecture;
diff --git a/code/trb_net16_soda_sync_ecp3_sfp.vhd b/code/trb_net16_soda_sync_ecp3_sfp.vhd
deleted file mode 100644
index 471762a..0000000
--- a/code/trb_net16_soda_sync_ecp3_sfp.vhd
+++ /dev/null
@@ -1,1021 +0,0 @@
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-
-entity Cu_trb_net16_soda_sync_ecp3_sfp is
-	port(
-		OSCCLK					: in std_logic; -- 200 MHz reference clock
-		SYSCLK					: in std_logic; -- 100 MHz main clock net, synchronous to RX clock
-		RESET						: in std_logic; -- synchronous reset
-		CLEAR						: in std_logic; -- asynchronous reset
-		--Internal Connection TX
-		MED_DATA_IN				: in std_logic_vector(c_DATA_WIDTH-1 downto 0);
-		MED_PACKET_NUM_IN		: in std_logic_vector(c_NUM_WIDTH-1 downto 0);
-		MED_DATAREADY_IN		: in std_logic;
-		MED_READ_OUT			: out std_logic := '0';
-		--Internal Connection RX
-		MED_DATA_OUT			: out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
-		MED_PACKET_NUM_OUT	: out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
-		MED_DATAREADY_OUT		: out std_logic := '0';
-		MED_READ_IN				: in std_logic;
-
-		--Copper SFP Connection
-		CU_RXD_P_IN				: in std_logic;
-		CU_RXD_N_IN				: in std_logic;
-		CU_TXD_P_OUT			: out std_logic;
-		CU_TXD_N_OUT			: out std_logic;
-		CU_PRSNT_N_IN			: in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		CU_LOS_IN				: in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		CU_TXDIS_OUT			: out std_logic := '0'; -- SFP disable
-		--Fiber/sync SFP Connection
-		SYNC_RX_HALF_CLK_OUT	: out std_logic := '0'; --received 100 MHz
-		SYNC_RX_FULL_CLK_OUT	: out std_logic := '0'; --received 200 MHz
-		SYNC_TX_HALF_CLK_OUT	: out std_logic := '0'; --received 100 MHz
-		SYNC_TX_FULL_CLK_OUT	: out std_logic := '0'; --received 200 MHz
-		SYNC_DLM_IN				: in  std_logic;
-		SYNC_DLM_WORD_IN		: in  std_logic_vector(7 downto 0);
-		SYNC_DLM_OUT			: out  std_logic;
-		SYNC_DLM_WORD_OUT		: out  std_logic_vector(7 downto 0);
-		SYNC_RXD_P_IN			: in std_logic;
-		SYNC_RXD_N_IN			: in std_logic;
-		SYNC_TXD_P_OUT			: out std_logic;
-		SYNC_TXD_N_OUT			: out std_logic;
-		SYNC_PRSNT_N_IN		: in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-		SYNC_LOS_IN				: in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-		SYNC_TXDIS_OUT			: out std_logic := '0'; -- SFP disable
-		--Control Interface
-		SCI_DATA_IN				: in std_logic_vector(7 downto 0) := (others => '0');
-		SCI_DATA_OUT			: out std_logic_vector(7 downto 0) := (others => '0');
-		SCI_ADDR					: in std_logic_vector(8 downto 0) := (others => '0');
-		SCI_READ					: in std_logic := '0';
-		SCI_WRITE				: in std_logic := '0';
-		SCI_ACK					: out std_logic := '0';
-		SCI_NACK					: out std_logic := '0';
-
-		TX_READY_CH3			: out std_logic;
-		-- Status and control port
-		STAT_OP					: out std_logic_vector (15 downto 0);
-		CTRL_OP					: in std_logic_vector (15 downto 0) := (others => '0');
-		STAT_DEBUG				: out std_logic_vector (63 downto 0);
-		CTRL_DEBUG				: in std_logic_vector (63 downto 0) := (others => '0')
-	);
-end entity;
-
-architecture Cu_trb_net16_soda_sync_ecp3_sfp_arch of Cu_trb_net16_soda_sync_ecp3_sfp is
-
-
-  -- Placer Directives
-  attribute HGROUP : string;
-  -- for whole architecture
-  attribute HGROUP of  Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture  is "media_interface_group";
-  attribute syn_sharing : string;
-  attribute syn_sharing of  Cu_trb_net16_soda_sync_ecp3_sfp_arch : architecture is "off";
-
-	component sfp_2_200_int
-		port
-			(
-			hdinp_ch1, hdinn_ch1    :   in std_logic;
-			hdoutp_ch1, hdoutn_ch1   :   out std_logic;
-			sci_sel_ch1    :   in std_logic;
-			rxiclk_ch1    :   in std_logic;
-			txiclk_ch1    :   in std_logic;
-			rx_full_clk_ch1   :   out std_logic;
-			rx_half_clk_ch1   :   out std_logic;
-			tx_full_clk_ch1   :   out std_logic;
-			tx_half_clk_ch1   :   out std_logic;
-			fpga_rxrefclk_ch1    :   in std_logic;
-			txdata_ch1    :   in std_logic_vector (15 downto 0);
-			tx_k_ch1    :   in std_logic_vector (1 downto 0);
-			tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
-			tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
-			rxdata_ch1   :   out std_logic_vector (15 downto 0);
-			rx_k_ch1   :   out std_logic_vector (1 downto 0);
-			rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
-			rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
-			rx_serdes_rst_ch1_c    :   in std_logic;
-			sb_felb_ch1_c    :   in std_logic;
-			sb_felb_rst_ch1_c    :   in std_logic;
-			tx_pcs_rst_ch1_c    :   in std_logic;
-			tx_pwrup_ch1_c    :   in std_logic;
-			rx_pcs_rst_ch1_c    :   in std_logic;
-			rx_pwrup_ch1_c    :   in std_logic;
-			rx_los_low_ch1_s   :   out std_logic;
-			lsm_status_ch1_s   :   out std_logic;
-			rx_cdr_lol_ch1_s   :   out std_logic;
-			tx_div2_mode_ch1_c   : in std_logic;
-			rx_div2_mode_ch1_c   : in std_logic;
-
-			hdinp_ch3, hdinn_ch3    :   in std_logic;
-			hdoutp_ch3, hdoutn_ch3   :   out std_logic;
-			sci_sel_ch3    :   in std_logic;
-			txiclk_ch3    :   in std_logic;
-			rx_full_clk_ch3   :   out std_logic;
-			rx_half_clk_ch3   :   out std_logic;
-			tx_full_clk_ch3   :   out std_logic;
-			tx_half_clk_ch3   :   out std_logic;
-			fpga_rxrefclk_ch3    :   in std_logic;
-			txdata_ch3    :   in std_logic_vector (7 downto 0);
-			tx_k_ch3    :   in std_logic;
-			tx_force_disp_ch3    :   in std_logic;
-			tx_disp_sel_ch3    :   in std_logic;
-			rxdata_ch3   :   out std_logic_vector (7 downto 0);
-			rx_k_ch3   :   out std_logic;
-			rx_disp_err_ch3   :   out std_logic;
-			rx_cv_err_ch3   :   out std_logic;
-			rx_serdes_rst_ch3_c    :   in std_logic;
-			sb_felb_ch3_c    :   in std_logic;
-			sb_felb_rst_ch3_c    :   in std_logic;
-			tx_pcs_rst_ch3_c    :   in std_logic;
-			tx_pwrup_ch3_c    :   in std_logic;
-			rx_pcs_rst_ch3_c    :   in std_logic;
-			rx_pwrup_ch3_c    :   in std_logic;
-			rx_los_low_ch3_s   :   out std_logic;
-			lsm_status_ch3_s   :   out std_logic;
-			rx_cdr_lol_ch3_s   :   out std_logic;
-			tx_div2_mode_ch3_c   : in std_logic;
-			rx_div2_mode_ch3_c   : in std_logic;
-			---- Miscillaneous ports
-			sci_wrdata    :   in std_logic_vector (7 downto 0);
-			sci_addr    :   in std_logic_vector (5 downto 0);
-			sci_rddata   :   out std_logic_vector (7 downto 0);
-			sci_sel_quad    :   in std_logic;
-			sci_rd    :   in std_logic;
-			sci_wrn    :   in std_logic;
-			fpga_txrefclk  :   in std_logic;
-			tx_serdes_rst_c    :   in std_logic;
-			tx_pll_lol_qd_s   :   out std_logic;
-			tx_sync_qd_c    :   in std_logic;
-			rst_qd_c    :   in std_logic;
-			refclk2fpga   :   out std_logic;
-			serdes_rst_qd_c    :   in std_logic
-		);
-	end component;
-
-	signal refck2core             : std_logic;
-	--  signal clock                  : std_logic;
-	--reset signals
-	signal ffc_quad_rst           : std_logic;
-	signal ffc_lane_tx_rst        : std_logic;
-	signal ffc_lane_rx_rst        : std_logic;
-	--serdes connections
-	signal tx_data                : std_logic_vector(15 downto 0);
-	signal tx_k                   : std_logic_vector(1 downto 0);
-	signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals
-	signal rx_k                   : std_logic_vector(1 downto 0);  -- delayed signals
-	signal comb_rx_data           : std_logic_vector(15 downto 0); -- original signals from SFP
-	signal comb_rx_k              : std_logic_vector(1 downto 0);  -- original signals from SFP
-	signal link_ok                : std_logic_vector(0 downto 0);
-	signal link_error             : std_logic_vector(8 downto 0);
-	signal ff_txhalfclk           : std_logic;
-	signal ff_rxhalfclk			      : std_logic;
-	signal ff_rxfullclk           : std_logic;
-	--rx fifo signals
-	signal fifo_rx_rd_en          : std_logic;
-	signal fifo_rx_wr_en          : std_logic;
-	signal fifo_rx_reset          : std_logic;
-	signal fifo_rx_din            : std_logic_vector(17 downto 0);
-	signal fifo_rx_dout           : std_logic_vector(17 downto 0);
-	signal fifo_rx_full           : std_logic;
-	signal fifo_rx_empty          : std_logic;
-	--tx fifo signals
-	signal fifo_tx_rd_en          : std_logic;
-	signal fifo_tx_wr_en          : std_logic;
-	signal fifo_tx_reset          : std_logic;
-	signal fifo_tx_din            : std_logic_vector(17 downto 0);
-	signal fifo_tx_dout           : std_logic_vector(17 downto 0);
-	signal fifo_tx_full           : std_logic;
-	signal fifo_tx_empty          : std_logic;
-	signal fifo_tx_almost_full    : std_logic;
-	--rx path
-	signal rx_counter             : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-	signal buf_med_dataready_out  : std_logic;
-	signal buf_med_data_out       : std_logic_vector(c_DATA_WIDTH-1 downto 0);
-	signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-	signal last_rx                : std_logic_vector(8 downto 0);
-	signal last_fifo_rx_empty     : std_logic;
-	--tx path
-	signal last_fifo_tx_empty     : std_logic;
-	--link status
-	signal rx_k_q                 : std_logic_vector(1 downto 0);
-
-	signal quad_rst               : std_logic;
-	signal lane_rst               : std_logic;
-	signal tx_allow               : std_logic;
-	signal rx_allow               : std_logic;
-	signal tx_allow_qtx           : std_logic;
-
-	signal rx_allow_q             : std_logic; -- clock domain changed signal
-	signal tx_allow_q             : std_logic;
-	signal swap_bytes             : std_logic;
-	signal buf_stat_debug         : std_logic_vector(31 downto 0);
-
-	-- status inputs from SFP
-	signal sfp_prsnt_n            : std_logic; -- synchronized input signals
-	signal sfp_los                : std_logic; -- synchronized input signals
-
-	signal buf_STAT_OP            : std_logic_vector(15 downto 0);
-
-	signal led_counter            : unsigned(16 downto 0);
-	signal rx_led                 : std_logic;
-	signal tx_led                 : std_logic;
-
-
-	signal tx_correct             : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
-	signal first_idle             : std_logic; -- tag the first IDLE2 after data
-
-	signal reset_word_cnt				: unsigned(4 downto 0);
-	signal make_trbnet_reset			: std_logic;
-	signal make_trbnet_reset_q			: std_logic;
-	signal send_reset_words				: std_logic;
-	signal send_reset_words_q			: std_logic;
-	signal send_reset_in					: std_logic;
-	signal send_reset_in_qtx				: std_logic;
-	signal reset_i								: std_logic;
-	signal reset_i_rx							: std_logic;
-	signal pwr_up								: std_logic;
-
-	signal clk_sys								: std_logic;
-	signal clk_tx								: std_logic;
-	signal clk_rx								: std_logic;
-	signal clk_rxref							: std_logic;
-	signal clk_txref							: std_logic;
-  
-	-- Peter Schakel 3-dec-2014
-
-	signal sci_timer							: unsigned(12 downto 0) := (others => '0');
-	signal reset_n								: std_logic;
-	signal trb_rx_serdes_rst				: std_logic;
-	signal trb_rx_cdr_lol					: std_logic;
-	signal trb_rx_los_low					: std_logic;
-	signal trb_rx_pcs_rst					: std_logic;
-	signal trb_tx_pcs_rst					: std_logic;
-	signal rst_qd								: std_logic;
-	signal rst_qd1								: std_logic;
-	signal rst_qd3								: std_logic;
-	signal link_OK_S							: std_logic;
-	signal trb_rx_fsm_state					: std_logic_vector(3 downto 0);
-	signal trb_tx_fsm_state					: std_logic_vector(3 downto 0);
-	signal sync_rx_fsm_state				: std_logic_vector(3 downto 0);
-	signal sync_tx_fsm_state				: std_logic_vector(3 downto 0);
- 	signal clk_200_osc						: std_logic;
-	signal sync_rx_full_clk					: std_logic;
-	signal sync_rx_half_clk					: std_logic;
-	signal sync_tx_full_clk					: std_logic;
-	signal sync_tx_half_clk					: std_logic;
-
-	signal sync_tx_data						: std_logic_vector(7 downto 0);
-	signal sync_tx_k							: std_logic;
-	signal sync_rx_data						: std_logic_vector(7 downto 0);
-	signal sync_rx_k							: std_logic;
-	signal sync_rx_error						: std_logic;
-	signal sync_rx_serdes_rst				: std_logic;
-	signal sync_tx_pcs_rst					: std_logic;
-	signal sync_rx_pcs_rst					: std_logic;
-	signal sync_rx_los_low					: std_logic;
-	signal sync_lsm_status					: std_logic;
-	signal sync_rx_cdr_lol					: std_logic;
-	signal dlm_fifo_rd_en					: std_logic;
-	signal dlm_fifo_empty					: std_logic;
-	signal dlm_fifo_reading					: std_logic;
-	signal dlm_received_S					: std_logic;
-
-	signal syncfifo_din						: std_logic_vector(17 downto 0);
-	signal syncfifo_dout						: std_logic_vector(17 downto 0);
-
-	type	sci_ctrl	is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-	signal sci_state							: sci_ctrl;
-	
-	signal sci_ch_i							: std_logic_vector(3 downto 0);
-	signal sci_qd_i							: std_logic;
-	signal sci_reg_i							: std_logic;
-	signal sci_addr_i							: std_logic_vector(8 downto 0);
-	signal sci_data_in_i						: std_logic_vector(7 downto 0);
-	signal sci_data_out_i					: std_logic_vector(7 downto 0);
-	signal sci_read_i							: std_logic;
-	signal sci_write_i						: std_logic;
-	signal sci_write_shift_i				: std_logic_vector(2 downto 0);
-	signal sci_read_shift_i					: std_logic_vector(2 downto 0);  
-
-	signal tx_pll_lol_qd_i					: std_logic;
-
-	signal wa_position						: std_logic_vector(15 downto 0) := x"FFFF";
-	signal wa_position_rx					: std_logic_vector(15 downto 0) := x"FFFF";
-	signal sync_wa_position_rx				: std_logic_vector(15 downto 0) := x"FFFF";
-	signal sync_tx_allow						: std_logic;
-	signal sync_rx_allow						: std_logic;
-	signal sync_tx_allow_q					: std_logic;
-	signal sync_rx_allow_q					: std_logic;
-	signal link_phase_S						: std_logic;	--PL!
-	signal request_retr_i					: std_logic;
-	signal start_retr_i						: std_logic;
-	signal request_retr_position_i		: std_logic_vector(7 downto 0);
-	signal start_retr_position_i			: std_logic_vector(7 downto 0);
-	signal send_link_reset_i				: std_logic;
-	signal make_link_reset_i				: std_logic;
-
-	attribute syn_keep									: boolean;
-	attribute syn_preserve								: boolean;
-	attribute syn_keep		of led_counter			: signal is true;
-	attribute syn_keep		of send_reset_in		: signal is true;
-	attribute syn_keep		of reset_i				: signal is true;
-	attribute syn_preserve	of reset_i				: signal is true;
-	attribute syn_preserve	of sci_ch_i				: signal is true;--
-	attribute syn_keep		of sci_ch_i				: signal is true;--
-	attribute syn_preserve	of sci_addr_i			: signal is true;--
-	attribute syn_keep		of sci_addr_i			: signal is true;--
-	attribute syn_preserve	of sci_data_in_i		: signal is true;--
-	attribute syn_keep		of sci_data_in_i		: signal is true;--
-	attribute syn_preserve	of sci_data_out_i		: signal is true;--
-	attribute syn_keep		of sci_data_out_i		: signal is true;--
-	attribute syn_preserve	of sci_read_i			: signal is true;--
-	attribute syn_keep		of sci_read_i			: signal is true;--
-	attribute syn_preserve	of sci_write_i			: signal is true;--
-	attribute syn_keep		of sci_write_i			: signal is true;--
-	attribute syn_preserve	of sci_write_shift_i	: signal is true;--
-	attribute syn_keep		of sci_write_shift_i	: signal is true;--
-	attribute syn_preserve	of	sci_read_shift_i	: signal is true;--
-	attribute syn_keep		of sci_read_shift_i	: signal is true;--
-	attribute syn_preserve	of	wa_position			: signal is true;--
-	attribute syn_keep		of wa_position			: signal is true;--
-	attribute syn_preserve	of	wa_position_rx		: signal is true;--
-	attribute syn_keep		of wa_position_rx		: signal is true;--
-
-begin
-
-clk_200_osc				<= OSCCLK;
-
-SYNC_RX_HALF_CLK_OUT	<= sync_rx_half_clk;
-SYNC_RX_FULL_CLK_OUT	<= sync_rx_full_clk;
-SYNC_TX_HALF_CLK_OUT	<= sync_tx_half_clk;
-SYNC_TX_FULL_CLK_OUT	<= sync_tx_full_clk;
---RX_CDR_LOL_OUT		<= rx_cdr_lol;	
-
-clk_sys					<= SYSCLK;
-clk_tx					<= SYSCLK;
-clk_rx					<= ff_rxhalfclk;
-clk_rxref				<= OSCCLK;
-clk_txref				<= OSCCLK;
-
---sd_los_i			 					<= SD_LOS_IN when rising_edge(SYSCLK);	-- PL!
-
---------------------------------------------------------------------------
--- Internal Lane Resets
---------------------------------------------------------------------------
-  PROC_RESET : process(clk_sys)
-    begin
-      if rising_edge(clk_sys) then
-        reset_i <= RESET;
-        send_reset_in <= ctrl_op(15);
-        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
-      end if;
-    end process;
-
---------------------------------------------------------------------------
--- Synchronizer stages
---------------------------------------------------------------------------
-
--- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
-THE_SFP_STATUS_SYNC: signal_sync
-  generic map(
-    DEPTH => 3,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => sync_prsnt_n_in,
-    D_IN(1)  => sync_los_in,
-    CLK0     => clk_sys,
-    CLK1     => clk_sys,
-    D_OUT(0) => sfp_prsnt_n,
-    D_OUT(1) => sfp_los
-    );
-
-
-THE_RX_K_SYNC: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 4
-    )
-  port map(
-    RESET             => reset_i,
-    D_IN(1 downto 0)  => comb_rx_k,
-    D_IN(2)           => send_reset_words,
-    D_IN(3)           => make_trbnet_reset,
-    CLK0              => clk_rx, -- CHANGED
-    CLK1              => clk_sys,
-    D_OUT(1 downto 0) => rx_k_q,
-    D_OUT(2)          => send_reset_words_q,
-    D_OUT(3)          => make_trbnet_reset_q
-    );
-
-THE_RX_DATA_DELAY: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 16
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN     => comb_rx_data,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT    => rx_data
-    );
-
-THE_RX_K_DELAY: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN     => comb_rx_k,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT    => rx_k
-    );
-
-THE_RX_RESET: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 1
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => reset_i,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT(0) => reset_i_rx
-    );
-
--- Delay for ALLOW signals
-THE_RX_ALLOW_SYNC: signal_sync
-	generic map(
-		DEPTH => 2,
-		WIDTH => 2
-		)
-	port map(
-		RESET    => reset_i,
-		D_IN(0)  => rx_allow,
-		D_IN(1)  => tx_allow,
-		CLK0     => clk_sys,
-		CLK1     => clk_sys,
-		D_OUT(0) => rx_allow_q,
-		D_OUT(1) => tx_allow_q
-	);
-
-THE_TX_SYNC: signal_sync
-	generic map(
-		DEPTH => 1,
-		WIDTH => 2
-		)
-	port map(
-		RESET    => '0',
-		D_IN(0)  => send_reset_in,
-		D_IN(1)  => tx_allow,
-		CLK0     => clk_tx,
-		CLK1     => clk_tx,
-		D_OUT(0) => send_reset_in_qtx,
-		D_OUT(1) => tx_allow_qtx
-	);
-
-
---------------------------------------------------------------------------
--- Main control state machine, startup control for SFP
---------------------------------------------------------------------------
-
-THE_SFP_LSM: trb_net16_lsm_sfp
-    generic map (
-      HIGHSPEED_STARTUP => c_YES
-      )
-    port map(
-      SYSCLK            => clk_sys,
-      RESET             => reset_i,
-      CLEAR             => clear,
-      SFP_MISSING_IN    => sfp_prsnt_n,
-      SFP_LOS_IN        => sfp_los,
-      SD_LINK_OK_IN     => link_ok(0),
-      SD_LOS_IN         => link_error(8),
-      SD_TXCLK_BAD_IN   => link_error(5),
-      SD_RXCLK_BAD_IN   => link_error(4),
-      SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
-      SD_ALIGNMENT_IN	=> rx_k_q,
-      SD_CV_IN          => link_error(7 downto 6),
-      FULL_RESET_OUT    => quad_rst,
-      LANE_RESET_OUT    => lane_rst,
-      TX_ALLOW_OUT      => tx_allow,
-      RX_ALLOW_OUT      => rx_allow,
-      SWAP_BYTES_OUT    => swap_bytes,
-      STAT_OP           => buf_stat_op,
-      CTRL_OP           => ctrl_op,
-      STAT_DEBUG        => buf_stat_debug
-      );
-
-SYNC_TXDIS_OUT <= quad_rst or reset_i;
-
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
-ffc_quad_rst         <= quad_rst;
-ffc_lane_tx_rst      <= lane_rst;
-
-
-ffc_lane_rx_rst      <= lane_rst;
-
-
-
--- Instantiation of serdes module
-
-	THE_SERDES: sfp_2_200_int
-		port map(
-		HDINP_CH1           => CU_RXD_P_IN,
-		HDINN_CH1           => CU_RXD_N_IN,
-		HDOUTP_CH1          => CU_TXD_P_OUT,
-		HDOUTN_CH1          => CU_TXD_N_OUT,
-		SCI_SEL_CH1         => sci_ch_i(1),
-		RXICLK_CH1          => clk_rx,
-		TXICLK_CH1          => clk_tx,
-		RX_FULL_CLK_CH1     => ff_rxfullclk,
-		RX_HALF_CLK_CH1     => ff_rxhalfclk,
-		TX_FULL_CLK_CH1     => open,
-		TX_HALF_CLK_CH1     => ff_txhalfclk,
-		FPGA_RXREFCLK_CH1   => clk_rxref,
-		TXDATA_CH1          => tx_data,
-		TX_K_CH1            => tx_k,
-		TX_FORCE_DISP_CH1   => tx_correct,
-		TX_DISP_SEL_CH1     => "00",
-		RXDATA_CH1          => comb_rx_data,
-		RX_K_CH1            => comb_rx_k,
-		RX_DISP_ERR_CH1		=> open,
-		RX_CV_ERR_CH1			=> link_error(7 downto 6),
-		RX_SERDES_RST_CH1_C	=> trb_rx_serdes_rst,
-		SB_FELB_CH1_C			=> '0', --loopback enable
-		SB_FELB_RST_CH1_C		=> '0', --loopback reset
-		TX_PCS_RST_CH1_C		=> trb_tx_pcs_rst,	--'1', --tx power up
-		TX_PWRUP_CH1_C			=> '1', --tx power up
-		RX_PCS_RST_CH1_C		=> trb_rx_pcs_rst,	--'1', --rx power up
-		RX_PWRUP_CH1_C			=> '1', --rx power up
-		RX_LOS_LOW_CH1_S    => trb_rx_los_low,	--link_error(8),
-		LSM_STATUS_CH1_S    => link_ok(0),
-		RX_CDR_LOL_CH1_S    => trb_rx_cdr_lol,	--link_error(4),
-		TX_DIV2_MODE_CH1_C  => '0', --full rate
-		RX_DIV2_MODE_CH1_C  => '0', --full rate
-		
-		HDINP_CH3           => SYNC_RXD_P_IN,
-		HDINN_CH3           => SYNC_RXD_N_IN,
-		HDOUTP_CH3          => SYNC_TXD_P_OUT,
-		HDOUTN_CH3          => SYNC_TXD_N_OUT,
-		SCI_SEL_CH3         => sci_ch_i(3),
-		TXICLK_CH3          => sync_rx_full_clk,
-		RX_FULL_CLK_CH3     => sync_rx_full_clk,
-		RX_HALF_CLK_CH3     => sync_rx_half_clk,
-		TX_FULL_CLK_CH3     => sync_tx_full_clk,
-		TX_HALF_CLK_CH3     => sync_tx_half_clk,
-		FPGA_RXREFCLK_CH3   => clk_200_osc,
-		TXDATA_CH3          => sync_tx_data,
-		TX_K_CH3            => sync_tx_k,
-		TX_FORCE_DISP_CH3   => '0',
-		TX_DISP_SEL_CH3     => '0',
-		RXDATA_CH3          => sync_rx_data,
-		RX_K_CH3            => sync_rx_k,
-		RX_DISP_ERR_CH3     => open,
-		RX_CV_ERR_CH3       => sync_rx_error,
-		RX_SERDES_RST_CH3_C => sync_rx_serdes_rst,
-		SB_FELB_CH3_C       => '0', --loopback enable
-		SB_FELB_RST_CH3_C   => '0', --loopback reset
-		TX_PCS_RST_CH3_C     => sync_tx_pcs_rst,
-		TX_PWRUP_CH3_C       => '1',
-		RX_PCS_RST_CH3_C     => sync_rx_pcs_rst,
-		RX_PWRUP_CH3_C       => '1',
-		RX_LOS_LOW_CH3_S     => sync_rx_los_low,
-		LSM_STATUS_CH3_S     => sync_lsm_status,
-		RX_CDR_LOL_CH3_S     => sync_rx_cdr_lol,
-		TX_DIV2_MODE_CH3_C   => '0',
-		RX_DIV2_MODE_CH3_C   => '0',
-
-		SCI_WRDATA          => sci_data_in_i,
-		SCI_ADDR            => sci_addr_i(5 downto 0),
-		SCI_RDDATA          => sci_data_out_i,
-		SCI_SEL_QUAD        => sci_addr_i(8),
-		SCI_RD              => sci_read_i,
-		SCI_WRN             => sci_write_i,
-		FPGA_TXREFCLK       => clk_txref,
---		FPGA_TXREFCLK       => rx_full_clk,
-		TX_SERDES_RST_C     => CLEAR,
-		TX_PLL_LOL_QD_S     => link_error(5), 
-		TX_SYNC_QD_C			=> '0',
-		RST_QD_C					=> rst_qd,
-		REFCLK2FPGA				=> open,
-		SERDES_RST_QD_C     => ffc_quad_rst
-	);
-  
--------------------------------------------------------------------------
--- RX Fifo & Data output
--------------------------------------------------------------------------
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
-generic map(
-  USE_STATUS_FLAGS => c_NO
-       )
-port map( read_clock_in  => clk_sys,
-      write_clock_in     => clk_rx, -- CHANGED
-      read_enable_in     => fifo_rx_rd_en,
-      write_enable_in    => fifo_rx_wr_en,
-      fifo_gsr_in        => fifo_rx_reset,
-      write_data_in      => fifo_rx_din,
-      read_data_out      => fifo_rx_dout,
-      full_out           => fifo_rx_full,
-      empty_out          => fifo_rx_empty
-    );
-
-fifo_rx_reset <= reset_i or not rx_allow_q;
-fifo_rx_rd_en <= not fifo_rx_empty;
-
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
-THE_BYTE_SWAP_PROC: process
-  begin
-    wait until rising_edge(clk_rx);  --CHANGED
-    last_rx <= rx_k(1) & rx_data(15 downto 8);
-    if( swap_bytes = '0' ) then
-      fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
-      fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
-    else
-      fifo_rx_din   <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
-      fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
-    end if;
-  end process THE_BYTE_SWAP_PROC;
-
-buf_med_data_out          <= fifo_rx_dout(15 downto 0);
-buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
-buf_med_packet_num_out    <= rx_counter;
-med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
-
-
-THE_CNT_RESET_PROC : process
-  begin
-    wait until rising_edge(clk_rx);  --CHANGED
-    if reset_i_rx = '1' then
-      send_reset_words  <= '0';
-      make_trbnet_reset <= '0';
-      reset_word_cnt    <= (others => '0');
-    else
-      send_reset_words   <= '0';
-      make_trbnet_reset  <= '0';
-      if fifo_rx_din = "11" & x"FEFE" then
-        if reset_word_cnt(4) = '0' then
-          reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
-        else
-          send_reset_words <= '1';
-        end if;
-      else
-        reset_word_cnt    <= (others => '0');
-        make_trbnet_reset <= reset_word_cnt(4);
-      end if;
-    end if;
-  end process;
-
-
-THE_SYNC_PROC: process
-  begin
-    wait until rising_edge(clk_sys);
-    med_dataready_out     <= buf_med_dataready_out;
-    med_data_out          <= buf_med_data_out;
-    med_packet_num_out    <= buf_med_packet_num_out;
-    if reset_i = '1' then
-      med_dataready_out <= '0';
-    end if;
-  end process;
-
-
---rx packet counter
----------------------
-THE_RX_PACKETS_PROC: process( clk_sys )
-  begin
-    if( rising_edge(clk_sys) ) then
-      last_fifo_rx_empty <= fifo_rx_empty;
-      if reset_i = '1' or rx_allow_q = '0' then
-        rx_counter <= c_H0;
-      else
-        if( buf_med_dataready_out = '1' ) then
-          if( rx_counter = c_max_word_number ) then
-            rx_counter <= (others => '0');
-          else
-            rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
-          end if;
-        end if;
-      end if;
-    end if;
-  end process;
-
---TX Fifo & Data output to Serdes
----------------------
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
-  generic map(
-    USE_STATUS_FLAGS => c_NO
-        )
-  port map( read_clock_in => clk_tx,
-        write_clock_in    => clk_sys,
-        read_enable_in    => fifo_tx_rd_en,
-        write_enable_in   => fifo_tx_wr_en,
-        fifo_gsr_in       => fifo_tx_reset,
-        write_data_in     => fifo_tx_din,
-        read_data_out     => fifo_tx_dout,
-        full_out          => fifo_tx_full,
-        empty_out         => fifo_tx_empty,
-        almost_full_out   => fifo_tx_almost_full
-      );
-
-fifo_tx_reset <= reset_i or not tx_allow_q;
-fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
-fifo_tx_rd_en <= tx_allow_qtx;
-
-
-THE_SERDES_INPUT_PROC: process( clk_tx )
-  begin
-    if( rising_edge(clk_tx) ) then
-      last_fifo_tx_empty <= fifo_tx_empty;
-      first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
-      if send_reset_in = '1' then
-        tx_data <= x"FEFE";
-        tx_k <= "11";
-      elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
-        tx_data <= x"50bc";
-        tx_k <= "01";
-        tx_correct <= first_idle & '0';
-      else
-        tx_data <= fifo_tx_dout(15 downto 0);
-        tx_k <= "00";
-        tx_correct <= "00";
-      end if;
-    end if;
-  end process THE_SERDES_INPUT_PROC;
-
-  
--- map 8-bit dlm on 18-bit fifo
-syncfifo_din(7 downto 0)	<= SYNC_dlm_WORD_IN;
-syncfifo_din(17 downto 8)	<= (others => '0');
---sync_dlm_word_S				<= syncfifo_dout(7 downto 0);
-
-sync_dlm_tx: trb_net_fifo_16bit_bram_dualport
-	generic map(
-		USE_STATUS_FLAGS => c_NO
-		)
-	port map(
-		read_clock_in		=> sync_tx_full_clk,
-		write_clock_in		=> sync_rx_full_clk, 
-		read_enable_in		=> dlm_fifo_rd_en,
-		write_enable_in	=> SYNC_dlm_IN,
-		fifo_gsr_in			=> reset,
-		write_data_in		=> syncfifo_din,
-		read_data_out		=> syncfifo_dout,
-		full_out				=> open,
-		empty_out			=> dlm_fifo_empty
-	);
-
-sync_rx_proc : process(sync_rx_full_clk)
-begin
-	if rising_edge(sync_rx_full_clk) then
-		SYNC_DLM_OUT <= '0';
-		if dlm_received_S='1' then
-			dlm_received_S		<= '0';
-			SYNC_DLM_OUT		<= '1';
-			SYNC_dlm_WORD_OUT	<= sync_rx_data;
-		elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then
-			dlm_received_S		<= '1';
-		end if;
-	end if;
-end process;  
-
-sync_tx_proc : process(sync_tx_full_clk)
-begin
-	if rising_edge(sync_tx_full_clk) then
-		if dlm_fifo_rd_en='1' then
-			dlm_fifo_rd_en		<= '0';
-			sync_tx_data		<= syncfifo_dout(7 downto 0);
-			sync_tx_k			<= '0';
-		elsif (dlm_fifo_empty='0') and (dlm_fifo_reading='1') then
-			dlm_fifo_rd_en		<= '1';
-			sync_tx_data		<= x"DC";
-			sync_tx_k			<= '1';
-		elsif dlm_fifo_empty='0' then
-			dlm_fifo_reading	<= '1';
-			dlm_fifo_rd_en		<= '0';
-			sync_tx_data		<= x"BC"; -- idle
-			sync_tx_k			<= '1';		
-		else
-			dlm_fifo_reading	<= '0';
-			dlm_fifo_rd_en		<= '0';
-			sync_tx_data		<= x"BC"; -- idle
-			sync_tx_k			<= '1';
-		end if;
-	end if;
-end process;  
-
-link_error(8) <= trb_rx_los_low; -- loss of signal
-link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock 
-link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock
-
-reset_n <= '0' when (RESET='1') or (CLEAR='1')  else '1';
-
--------------------------------------------------      
--- Reset FSM & Link states
-------------------------------------------------- 
-THE_RX_FSM1: rx_reset_fsm
-	port map(
-		RST_N               => reset_n,
-		RX_REFCLK           => OSCCLK,
-		TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
-		RX_SERDES_RST_CH_C  => trb_rx_serdes_rst,
-		RX_CDR_LOL_CH_S     => trb_rx_cdr_lol,
-		RX_LOS_LOW_CH_S     => trb_rx_los_low,
-		RX_PCS_RST_CH_C     => trb_rx_pcs_rst,
-		WA_POSITION         => "0000",
-		STATE_OUT           => trb_rx_fsm_state
-	);
-
-link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';
-
-THE_TX_FSM1: tx_reset_fsm
-	port map(
-		RST_N           => reset_n,
-		TX_REFCLK       => OSCCLK,
-		TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-		RST_QD_C        => rst_qd1,
-		TX_PCS_RST_CH_C => trb_tx_pcs_rst,
-		STATE_OUT       => trb_tx_fsm_state	--open
-	);
-
-THE_RX_FSM3: rx_reset_fsm
-	port map(
-		RST_N               => reset_n,
-		RX_REFCLK           => sync_rx_full_clk,
-		TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
-		RX_SERDES_RST_CH_C  => sync_rx_serdes_rst,
-		RX_CDR_LOL_CH_S     => sync_rx_cdr_lol,
-		RX_LOS_LOW_CH_S     => sync_rx_los_low,
-		RX_PCS_RST_CH_C     => sync_rx_pcs_rst,
-		WA_POSITION         => sync_wa_position_rx(11 downto 8),
-		STATE_OUT           => sync_rx_fsm_state
-	);
-
-SYNC_WA_POSITION : process(sync_rx_full_clk) --??CLK)
-begin
-	if rising_edge(sync_rx_full_clk) then
-		sync_wa_position_rx <= wa_position;
-	end if;
-end process;
-
-THE_TX_FSM3 : tx_reset_fsm
-  port map(
-    RST_N           => reset_n,
-    TX_REFCLK       => OSCCLK,
-    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-    RST_QD_C        => rst_qd3,
-    TX_PCS_RST_CH_C => sync_tx_pcs_rst,
-    STATE_OUT       => sync_tx_fsm_state
-    );
-
---rst_qd			<= '1' when (rst_qd1='1') or (rst_qd3='1') else '0';
-rst_qd			<= RESET;
-
-TX_READY_CH3	<= '1' when (sync_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';  
-
------------------------------------------------------------------------------------------------------
--- SCI --gives access to serdes config port from slow control and reads word alignment every ~ 40 us
------------------------------------------------------------------------------------------------------
-PROC_SCI_CTRL: process(clk_sys)
-	variable cnt : integer range 0 to 4 := 0;
-begin
-	if( rising_edge(clk_sys) ) then
-		SCI_ACK <= '0';
-		case sci_state is
-			when IDLE =>
-				sci_ch_i        <= x"0";
-				sci_qd_i        <= '0';
-				sci_reg_i       <= '0';
-				sci_read_i      <= '0';
-				sci_write_i     <= '0';
-				sci_timer       <= sci_timer + 1;
-				if SCI_READ = '1' or SCI_WRITE = '1' then
-				sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-				sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-				sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-				sci_addr_i    <= SCI_ADDR;
-				sci_data_in_i <= SCI_DATA_IN;
-				sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-				sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-				sci_state     <= SCTRL;
-			elsif sci_timer(sci_timer'left) = '1' then
-				sci_timer     <= (others => '0');
-				sci_state     <= GET_WA;
-			end if;      
-		when SCTRL =>
-			if sci_reg_i = '1' then
-				--//			SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-				SCI_DATA_OUT  <= (others => '0');
-				SCI_ACK       <= '1';
-				sci_write_i   <= '0';
-				sci_read_i    <= '0';
-				sci_state     <= IDLE;
-			else
-				sci_state     <= SCTRL_WAIT;
-			end if;
-		when SCTRL_WAIT   =>
-			sci_state       <= SCTRL_WAIT2;
-		when SCTRL_WAIT2  =>
-			sci_state       <= SCTRL_FINISH;
-		when SCTRL_FINISH =>
-			SCI_DATA_OUT    <= sci_data_out_i;
-			SCI_ACK         <= '1';
-			sci_write_i     <= '0';
-			sci_read_i      <= '0';
-			sci_state       <= IDLE;
-
-		when GET_WA =>
-			if cnt = 4 then
-				cnt           := 0;
-				sci_state     <= IDLE;
-			else
-				sci_state     <= GET_WA_WAIT;
-				sci_addr_i    <= '0' & x"22";
-				sci_ch_i      <= x"0";
-				sci_ch_i(cnt) <= '1';
-				sci_read_i    <= '1';
-				end if;
-		when GET_WA_WAIT  =>
-			sci_state       <= GET_WA_WAIT2;
-		when GET_WA_WAIT2 =>
-			sci_state       <= GET_WA_FINISH;
-		when GET_WA_FINISH =>
-			wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-			sci_state       <= GET_WA;    
-			cnt             := cnt + 1;
-		end case;
-
-		if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-			SCI_NACK <= '1';
-		else
-			SCI_NACK <= '0';
-		end if;
-	end if;
-end process PROC_SCI_CTRL;
-
-----------------------
---Generate LED signals
-----------------------
-LED_PROC : process( clk_sys )
-	begin
-		if rising_edge(clk_sys) then
-			led_counter <= led_counter + to_unsigned(1,1);
-			if buf_med_dataready_out = '1' then
-				rx_led <= '1';
-			elsif led_counter = 0 then
-			rx_led <= '0';
-			end if;
-			if tx_k(0) = '0' then
-				tx_led <= '1';
-			elsif led_counter = 0 then
-				tx_led <= '0';
-			end if;
-		end if;
-	end process LED_PROC;
-
-
-stat_op(15)           <= send_reset_words_q;
-stat_op(14)           <= buf_stat_op(14);
-stat_op(13)           <= make_trbnet_reset_q;
-stat_op(12)           <= '0';
-stat_op(11)           <= tx_led; --tx led
-stat_op(10)           <= rx_led; --rx led
-stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
-
--- Debug output
-stat_debug(15 downto 0)  <= rx_data;
-stat_debug(17 downto 16) <= rx_k;
-stat_debug(19 downto 18) <= (others => '0');
-stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
-stat_debug(24)           <= fifo_rx_rd_en;
-stat_debug(25)           <= fifo_rx_wr_en;
-stat_debug(26)           <= fifo_rx_reset;
-stat_debug(27)           <= fifo_rx_empty;
-stat_debug(28)           <= fifo_rx_full;
-stat_debug(29)           <= last_rx(8);
-stat_debug(30)           <= rx_allow_q;
-stat_debug(41 downto 31) <= (others => '0');
-stat_debug(42)           <= clk_sys;
-stat_debug(43)           <= clk_sys;
-stat_debug(59 downto 44) <= (others => '0');
-stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
-
-
-end Cu_trb_net16_soda_sync_ecp3_sfp_arch;
\ No newline at end of file
diff --git a/code/trb_net_CRC.vhd b/code/trb_net_CRC.vhd
deleted file mode 100644
index 7bf2d5c..0000000
--- a/code/trb_net_CRC.vhd
+++ /dev/null
@@ -1,74 +0,0 @@
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-library work;
-use work.trb_net_std.all;
-
-
---this implementation uses IBM-CRC-16, i.e. x16 + x15 + x2 + 1
-
-
-entity trb_net_CRC is
-  port(
-    CLK     : in  std_logic;
-    RESET   : in std_logic;
-    CLK_EN  : in std_logic;
-    DATA_IN : in  std_logic_vector(15 downto 0);
-    CRC_OUT : out std_logic_vector(15 downto 0);
-    CRC_match : out std_logic
-    );
-end entity;
-
-
-architecture trb_net_CRC_arch of trb_net_CRC is
-signal D,C, next_CRC_OUT, CRC : std_logic_vector(15 downto 0) := x"0000";
-
-begin
-    D <= DATA_IN;
-    C <= CRC;
-    CRC_OUT <= CRC;
-    CRC_match <= not or_all(CRC);
-
-    next_CRC_OUT(0) <= D(15) xor D(13) xor D(12) xor D(11) xor D(10) xor D(9) xor
-                 D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor
-                 D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor C(2) xor
-                 C(3) xor C(4) xor C(5) xor C(6) xor C(7) xor C(8) xor
-                 C(9) xor C(10) xor C(11) xor C(12) xor C(13) xor C(15);
-    next_CRC_OUT(1) <= D(14) xor D(13) xor D(12) xor D(11) xor D(10) xor D(9) xor
-                 D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor
-                 D(2) xor D(1) xor C(1) xor C(2) xor C(3) xor C(4) xor
-                 C(5) xor C(6) xor C(7) xor C(8) xor C(9) xor C(10) xor
-                 C(11) xor C(12) xor C(13) xor C(14);
-    next_CRC_OUT(2) <= D(14) xor D(1) xor D(0) xor C(0) xor C(1) xor C(14);
-    next_CRC_OUT(3) <= D(15) xor D(2) xor D(1) xor C(1) xor C(2) xor C(15);
-    next_CRC_OUT(4) <= D(3) xor D(2) xor C(2) xor C(3);
-    next_CRC_OUT(5) <= D(4) xor D(3) xor C(3) xor C(4);
-    next_CRC_OUT(6) <= D(5) xor D(4) xor C(4) xor C(5);
-    next_CRC_OUT(7) <= D(6) xor D(5) xor C(5) xor C(6);
-    next_CRC_OUT(8) <= D(7) xor D(6) xor C(6) xor C(7);
-    next_CRC_OUT(9) <= D(8) xor D(7) xor C(7) xor C(8);
-    next_CRC_OUT(10) <= D(9) xor D(8) xor C(8) xor C(9);
-    next_CRC_OUT(11) <= D(10) xor D(9) xor C(9) xor C(10);
-    next_CRC_OUT(12) <= D(11) xor D(10) xor C(10) xor C(11);
-    next_CRC_OUT(13) <= D(12) xor D(11) xor C(11) xor C(12);
-    next_CRC_OUT(14) <= D(13) xor D(12) xor C(12) xor C(13);
-    next_CRC_OUT(15) <= D(15) xor D(14) xor D(12) xor D(11) xor D(10) xor D(9) xor
-                  D(8) xor D(7) xor D(6) xor D(5) xor D(4) xor D(3) xor
-                  D(2) xor D(1) xor D(0) xor C(0) xor C(1) xor C(2) xor
-                  C(3) xor C(4) xor C(5) xor C(6) xor C(7) xor C(8) xor
-                  C(9) xor C(10) xor C(11) xor C(12) xor C(14) xor C(15);
-
-   process(CLK)
-     begin
-       if rising_edge(CLK) then
-         if RESET = '1' then
-           CRC <= (others => '0');
-         elsif CLK_EN = '1' then
-           CRC <= next_CRC_OUT;
-         end if;
-       end if;
-     end process;
-
-end architecture;
-
diff --git a/code/trb_net_CRC8.vhd b/code/trb_net_CRC8.vhd
deleted file mode 100644
index 3ae8474..0000000
--- a/code/trb_net_CRC8.vhd
+++ /dev/null
@@ -1,61 +0,0 @@
--------------------------------------------------------------------------------
--- Copyright (C) 2009 OutputLogic.com
--- This source file may be used and distributed without restriction
--- provided that this copyright statement is not removed from the file
--- and that any derivative work contains the original copyright notice
--- and the associated disclaimer.
---
--- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
--- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
--- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--------------------------------------------------------------------------------
--- CRC module for data(7:0)
---   lfsr(7:0)=1+x^4+x^5+x^8;
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-
-library work;
-use work.trb_net_std.all;
-
-entity trb_net_CRC8 is
-	port(
-		CLK			: in  std_logic;
-		RESET			: in  std_logic;
-		CLK_EN		: in  std_logic;
-		DATA_IN		: in  std_logic_vector(7 downto 0);
-		CRC_OUT		: out std_logic_vector(7 downto 0);
-		CRC_match	: out std_logic
-	);
-end entity;
-
-architecture imp_crc of trb_net_CRC8 is
-
-	signal lfsr_q: std_logic_vector (7 downto 0);
-	signal lfsr_c: std_logic_vector (7 downto 0);
-
-	begin
-
-	CRC_OUT <= lfsr_q;
-	CRC_match <= not or_all(lfsr_c);
-
-	lfsr_c(0) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(4) xor lfsr_q(6) xor data_in(0) xor data_in(3) xor data_in(4) xor data_in(6);
-	lfsr_c(1) <= lfsr_q(1) xor lfsr_q(4) xor lfsr_q(5) xor lfsr_q(7) xor data_in(1) xor data_in(4) xor data_in(5) xor data_in(7);
-	lfsr_c(2) <= lfsr_q(2) xor lfsr_q(5) xor lfsr_q(6) xor data_in(2) xor data_in(5) xor data_in(6);
-	lfsr_c(3) <= lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(3) xor data_in(6) xor data_in(7);
-	lfsr_c(4) <= lfsr_q(0) xor lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(0) xor data_in(3) xor data_in(6) xor data_in(7);
-	lfsr_c(5) <= lfsr_q(0) xor lfsr_q(1) xor lfsr_q(3) xor lfsr_q(6) xor lfsr_q(7) xor data_in(0) xor data_in(1) xor data_in(3) xor data_in(6) xor data_in(7);
-	lfsr_c(6) <= lfsr_q(1) xor lfsr_q(2) xor lfsr_q(4) xor lfsr_q(7) xor data_in(1) xor data_in(2) xor data_in(4) xor data_in(7);
-	lfsr_c(7) <= lfsr_q(2) xor lfsr_q(3) xor lfsr_q(5) xor data_in(2) xor data_in(3) xor data_in(5);
-
-
-	process (CLK) begin
-		if rising_edge(CLK) then
-			if (RESET = '1') then
-				lfsr_q <= b"00000000";
-			elsif (CLK_EN = '1') then
-				lfsr_q <= lfsr_c;
-			end if;
-		end if;
-	end process;
-end architecture imp_crc;
\ No newline at end of file
diff --git a/cores/README.txt b/cores/README.txt
deleted file mode 100644
index f8ef7dc..0000000
--- a/cores/README.txt
+++ /dev/null
@@ -1 +0,0 @@
-The place for all IP cores used for Soda.
diff --git a/ctsc.ldf b/ctsc.ldf
deleted file mode 100644
index 5c618dd..0000000
--- a/ctsc.ldf
+++ /dev/null
@@ -1,302 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="ctsc" device="LFE3-150EA-8FN672C" default_implementation="ctsc">
-    <Options/>
-    <Implementation title="ctsc" dir="ctsc" description="ctsc" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="Cu_trb3_periph_soda_client" top="Cu_trb3_periph_soda_client"/>
-        <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_client.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_2_200_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_2_200_int.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_2_200_int.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/version.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/Cu_trb3_periph_soda_client.vhd" type="VHDL" type_short="VHDL">
-            <Options top_module="Cu_trb3_periph_soda_client"/>
-        </Source>
-        <Source name="ctsc.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>
-        </Source>
-        <Source name="ctsc.rvl" type="Reveal" type_short="Reveal">
-            <Options/>
-        </Source>
-    </Implementation>
-    <Strategy name="Strategy1" file="ctsc1.sty"/>
-</BaliProject>
diff --git a/ctsc.lpf b/ctsc.lpf
deleted file mode 100644
index abf8239..0000000
--- a/ctsc.lpf
+++ /dev/null
@@ -1,156 +0,0 @@
-rvl_alias "soda_rx_full_clk" "trb_media_and_soda_sync_uplink/sync_rx_full_clk_out";
-BLOCK RESETPATHS;
-BLOCK ASYNCPATHS;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
-LOCATE COMP  "CLK_GPLL_LEFT"        SITE "U25";
-DEFINE PORT GROUP "CLK_group" "CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP  "FPGA5_COMM_0"   SITE "AD4";
-LOCATE COMP  "FPGA5_COMM_1"   SITE "AE3";
-LOCATE COMP  "FPGA5_COMM_2"   SITE "AA7";
-LOCATE COMP  "FPGA5_COMM_3"   SITE "AB7";
-LOCATE COMP  "FPGA5_COMM_4"   SITE "AD3";
-LOCATE COMP  "FPGA5_COMM_5"   SITE "AC4";
-LOCATE COMP  "FPGA5_COMM_6"   SITE "AE2";
-LOCATE COMP  "FPGA5_COMM_7"   SITE "AF3";
-LOCATE COMP  "FPGA5_COMM_8"   SITE "AE4";
-LOCATE COMP  "FPGA5_COMM_9"   SITE "AF4";
-LOCATE COMP  "FPGA5_COMM_10"  SITE "V10";
-LOCATE COMP  "FPGA5_COMM_11"  SITE "W10";
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0   #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1   #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2   #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3   #7
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C  #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6   #17
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8   #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9   #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0   #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1   #27
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5   #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0   #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1   #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2   #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3   #8
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6   #18
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8   #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9   #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0   #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1   #28
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5   #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T  #38
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0   #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1   #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2   #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3   #175
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C  #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6   #185
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0   #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1   #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2   #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3   #176
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C  #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6   #186
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
-#LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
-#LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
-#LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
-#LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF  PORT "SUPPL" IO_TYPE=LVDS25;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-#GSR_NET NET "GSR_N";  
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "TRB_MEDIA_AND_SODA_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI*" 20.000000 ns ;
-MULTICYCLE FROM CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI*" 20.000000 ns ;
-#MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 50 ns;
-
-BLOCK JTAGPATHS ;
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-
-FREQUENCY NET "soda_rx_full_clk" 200.000000 MHz ;
-FREQUENCY NET "soda_rx_half_clk" 100.000000 MHz ;
\ No newline at end of file
diff --git a/ctsh.ldf b/ctsh.ldf
deleted file mode 100644
index 151adf3..0000000
--- a/ctsh.ldf
+++ /dev/null
@@ -1,320 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="ctsh" device="LFE3-150EA-8FN672C" default_implementation="ctsh">
-    <Options/>
-    <Implementation title="ctsh" dir="ctsh" description="ctsh" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="Cu_trb3_periph_soda_hub" top="Cu_trb3_periph_soda_hub"/>
-        <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_hub.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_2_200_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_2_200_int.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_2_200_int.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_4_sync_downstream.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_4_sync_downstream.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_4_sync_downstream.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="code/soda_only_ecp3_sfp_4_sync_down.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/Cu_trb_net16_soda_syncUP_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/version.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/Cu_trb3_periph_soda_hub.vhd" type="VHDL" type_short="VHDL">
-            <Options top_module="Cu_trb3_periph_soda_hub"/>
-        </Source>
-        <Source name="ctsh.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>
-        </Source>
-        <Source name="ctsh.rvl" type="Reveal" type_short="Reveal">
-            <Options/>
-        </Source>
-    </Implementation>
-    <Strategy name="Strategy1" file="ctsh1.sty"/>
-</BaliProject>
diff --git a/ctsh.lpf b/ctsh.lpf
deleted file mode 100644
index d9815bd..0000000
--- a/ctsh.lpf
+++ /dev/null
@@ -1,162 +0,0 @@
-rvl_alias "soda_rxup_full_clk" "trb_media_and_soda_sync_uplink/sync_rx_full_clk_out";
-BLOCK RESETPATHS;
-BLOCK ASYNCPATHS;
-BLOCK RD_DURING_WR_PATHS ;
-BLOCK JTAGPATHS ;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
-LOCATE COMP  "CLK_GPLL_LEFT"        SITE "U25";
-DEFINE PORT GROUP "CLK_group" "CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP  "FPGA5_COMM_0"   SITE "AD4";
-LOCATE COMP  "FPGA5_COMM_1"   SITE "AE3";
-LOCATE COMP  "FPGA5_COMM_2"   SITE "AA7";
-LOCATE COMP  "FPGA5_COMM_3"   SITE "AB7";
-LOCATE COMP  "FPGA5_COMM_4"   SITE "AD3";
-LOCATE COMP  "FPGA5_COMM_5"   SITE "AC4";
-LOCATE COMP  "FPGA5_COMM_6"   SITE "AE2";
-LOCATE COMP  "FPGA5_COMM_7"   SITE "AF3";
-LOCATE COMP  "FPGA5_COMM_8"   SITE "AE4";
-LOCATE COMP  "FPGA5_COMM_9"   SITE "AF4";
-LOCATE COMP  "FPGA5_COMM_10"  SITE "V10";
-LOCATE COMP  "FPGA5_COMM_11"  SITE "W10";
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE_0" SITE "A5" ;
-LOCATE COMP "TEST_LINE_1" SITE "A6" ;
-LOCATE COMP "TEST_LINE_2" SITE "G8" ;
-LOCATE COMP "TEST_LINE_3" SITE "F9" ;
-LOCATE COMP "TEST_LINE_4" SITE "D9" ;
-LOCATE COMP "TEST_LINE_5" SITE "D10" ;
-LOCATE COMP "TEST_LINE_6" SITE "F10" ;
-LOCATE COMP "TEST_LINE_7" SITE "E10" ;
-LOCATE COMP "TEST_LINE_8" SITE "A8" ;
-LOCATE COMP "TEST_LINE_9" SITE "B8" ;
-LOCATE COMP "TEST_LINE_10" SITE "G10" ;
-LOCATE COMP "TEST_LINE_11" SITE "G9" ;
-LOCATE COMP "TEST_LINE_12" SITE "C9" ;
-LOCATE COMP "TEST_LINE_13" SITE "C10" ;
-LOCATE COMP "TEST_LINE_14" SITE "H10" ;
-LOCATE COMP "TEST_LINE_15" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0   #1
-LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1   #3
-LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2   #5
-LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3   #7
-LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C  #15
-LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6   #17
-LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8   #21
-LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9   #23
-LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0   #25
-LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1   #27
-LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5   #35
-LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
-LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0   #2
-LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1   #4
-LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2   #6
-LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3   #8
-LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6   #18
-LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8   #22
-LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9   #24
-LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0   #26
-LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1   #28
-LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5   #36
-LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T  #38
-LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0   #169
-LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1   #171
-LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2   #173
-LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3   #175
-LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C  #183
-LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6   #185
-LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0   #170
-LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1   #172
-LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2   #174
-LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3   #176
-LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C  #184
-LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6   #186
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
-#LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
-#LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
-#LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
-#LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE_1" SITE "AA20" ;
-LOCATE COMP "CODE_LINE_0" SITE "Y21" ;
-IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF  PORT "SUPPL" IO_TYPE=LVDS25;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-#GSR_NET NET "GSR_N";  
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "TRB_MEDIA_AND_SODA_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_SODA_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI*" 20.000000 ns ;
-MULTICYCLE FROM CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI*" 20.000000 ns ;
-#MULTICYCLE TO CELL "TRB_MEDIA_AND_SODA_SYNC_UPLINK/SCI_DATA_OUT*" 50 ns;
-
-BLOCK JTAGPATHS ;
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-
-FREQUENCY NET "soda_rxup_full_clk" 200.000000 MHz ;
-FREQUENCY NET "soda_rxup_half_clk" 100.000000 MHz ;
-FREQUENCY NET "soda_rxdn_full_clk" 200.000000 MHz ;
-FREQUENCY NET "soda_rxdn_half_clk" 100.000000 MHz ;
-#FREQUENCY NET "soda_tx_full_clk" 200.000000 MHz ;
-#FREQUENCY NET "soda_tx_half_clk" 100.000000 MHz ;
\ No newline at end of file
diff --git a/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/DataConcentrator_KC705.xdc b/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/DataConcentrator_KC705.xdc
new file mode 100644
index 0000000..a31cea8
--- /dev/null
+++ b/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/DataConcentrator_KC705.xdc
@@ -0,0 +1,183 @@
+create_clock -period 12.500 -name SGMIICLK_P -waveform {0.000 6.250} [get_ports SGMIICLK_Q0_P]
+#create_clock -period 12.500 -name SGMIICLK_N -waveform {0.000 6.250} [get_ports SGMIICLK_Q0_N]
+create_clock -period 5.000 -name SMA_MGT_REFCLK_P -waveform {0.000 2.500} [get_ports SMA_MGT_REFCLK_P]
+#create_clock -period 5 -name SMA_MGT_REFCLK_N -waveform {0 2.5} [get_ports SMA_MGT_REFCLK_N]
+create_clock -period 4.000 -name Q3_CLK0_MGTREFCLK_P_IPAD -waveform {0.000 2.000} [get_ports Q3_CLK0_MGTREFCLK_P_IPAD]
+#create_clock -period 4.000 -name Q3_CLK0_MGTREFCLK_N_IPAD -waveform {0.000 2.000} [get_ports Q3_CLK0_MGTREFCLK_N_IPAD]
+
+create_clock -period 5.000 -name USER_SMA_CLOCK_P -waveform {0.000 2.500} [get_ports USER_SMA_CLOCK_P]
+set_clock_latency -clock [get_clocks USER_SMA_CLOCK_P] -rise -source -late 1.000 [get_ports SMA_MGT_REFCLK_P]
+
+
+
+
+# GTX_SODAinput
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*TXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
+#create_clock -period 5.000 -name GT0_GTREFCLK0_IN [get_pins -hier -filter name=~*gt0_GTX_SODAinput_i*gtxe2_i*GTREFCLK0]
+
+# GTX_dualSODA
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_dualSODA_i*gtxe2_i*TXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_dualSODA_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_dualSODA_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_dualSODA_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt1_GTX_dualSODA_i*gtxe2_i*TXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt1_GTX_dualSODA_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt1_GTX_dualSODA_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt1_GTX_dualSODA_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#create_clock -period 5.000 -name GT0_GTREFCLK0_IN [get_pins -hier -filter name=~*gt0_GTX_dualSODA_i*gtxe2_i*GTREFCLK0]
+#create_clock -period 5.000 -name GT1_GTREFCLK0_IN [get_pins -hier -filter name=~*gt1_GTX_dualSODA_i*gtxe2_i*GTREFCLK0]
+
+# GTX_trb3_2gb
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_trb3_2gb_i*gtxe2_i*TXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_trb3_2gb_i*gtxe2_i*TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_trb3_2gb_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_trb3_2gb_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_ports SYSCLK_IN]]
+#create_clock -period 8.000 -name GT0_GTREFCLK0_IN [get_pins -hier -filter name=~*gt0_GTX_trb3_2gb_i*gtxe2_i*GTREFCLK0]
+
+
+
+# rename some clocks:
+#create_generated_clock -name clk_200_i [get_pins THE_MAIN_PLL/U0/mmcm_adv_inst/CLKOUT0]
+#create_generated_clock -name clk_100_i [get_pins THE_MAIN_PLL/U0/mmcm_adv_inst/CLKOUT1]
+#create_generated_clock -name clk_80_i [get_pins THE_MAIN_PLL/U0/mmcm_adv_inst/CLKOUT2]
+# or ???????
+#create_generated_clock -name clk_200_i [get_pins THE_MAIN_PLL/U0/clkout1_buf/O]
+#create_generated_clock -name clk_100_i [get_pins THE_MAIN_PLL/U0/clkout2_buf/O]
+#create_generated_clock -name clk_80_i [get_pins THE_MAIN_PLL/U0/clkout3_buf/O]
+create_generated_clock -name clk_200_i [get_pins THE_MAIN_PLL/inst/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clk_100_i [get_pins THE_MAIN_PLL/inst/mmcm_adv_inst/CLKOUT1]
+create_generated_clock -name clk_80_i [get_pins THE_MAIN_PLL/inst/mmcm_adv_inst/CLKOUT2]
+
+
+
+#create_generated_clock -name clk_rx200_0_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_0/clock100to200_1/U0/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clk_rx200_0_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_0/clock100to200_1/inst/mmcm_adv_inst/CLKOUT0]
+#create_generated_clock -name clk_rx200_1_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_1/clock100to200_1/U0/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clk_rx200_1_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_1/clock100to200_1/inst/mmcm_adv_inst/CLKOUT0]
+#//create_generated_clock -name clk_rx200_2_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_2/clock100to200_1/U0/mmcm_adv_inst/CLKOUT0]
+#//create_generated_clock -name clk_rx200_3_i [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/DC_data16to8_3/clock100to200_1/U0/mmcm_adv_inst/CLKOUT0]
+#create_generated_clock -name clk_tx200 [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/clock100to200a/U0/mmcm_adv_inst/CLKOUT0]
+create_generated_clock -name clk_tx200 [get_pins THE_FEE_SERDES/serdesQuadMUXwrapper1/clock100to200a/inst/mmcm_adv_inst/CLKOUT0]
+
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/clk_out]
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/clkout1_buf/O]
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/clkout1_buf/I]
+
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/U0/plle2_adv_inst/CLKOUT0]
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/U0/clkout1_buf/O]
+#//create_generated_clock -name clk_SODA200_i [get_pins THE_JITTERCLEANER/U0/clk_out1]
+
+
+#THE_DATAOUTPUT/GTX_dataoutput_support_i/GTX_dataoutput_init_i/U0/GTX_dataoutput_i/gt0_GTX_dataoutput_i/gtxe2_i/TXUSRCLK2
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_dataoutput_i*gtxe2_i*TXUSRCLK2]] -to [get_clocks -include_generated_clocks clk_80_i]
+
+####################### GT reference clock constraints #########################
+
+# TRBnet fifo clocks asynchronous to system clock:
+create_clock -period 8.000 -name GT0_GTREFCLK0_IN [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*GTREFCLK0]
+create_clock -period 8.000 [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]
+create_clock -period 10.000 [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]
+set_false_path -to [get_cells -hierarchical -filter {NAME =~ *data_sync_reg1}]
+set_false_path -from [get_clocks -include_generated_clocks clk_80_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_80_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]] -to [get_clocks -include_generated_clocks clk_80_i]
+
+set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]] -to [get_clocks -include_generated_clocks clk_100_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]] -to [get_clocks -include_generated_clocks clk_100_i]
+
+# system clocks asynchronous to ease timing:
+set_false_path -from [get_clocks -include_generated_clocks clk_200_i] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_80_i] -to [get_clocks -include_generated_clocks clk_200_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_80_i] -to [get_clocks -include_generated_clocks clk_100_i]
+
+# SODA serdes clocks asynchronous to  system clocks:
+set_false_path -from [get_clocks -include_generated_clocks clk_tx200] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_tx200] -to [get_clocks -include_generated_clocks clk_100_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_80_i] -to [get_clocks -include_generated_clocks clk_tx200]
+set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks clk_tx200]
+
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_0_i] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_1_i] -to [get_clocks -include_generated_clocks clk_80_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_2_i] -to [get_clocks -include_generated_clocks clk_80_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_3_i] -to [get_clocks -include_generated_clocks clk_80_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_0_i] -to [get_clocks -include_generated_clocks clk_100_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_1_i] -to [get_clocks -include_generated_clocks clk_100_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_2_i] -to [get_clocks -include_generated_clocks clk_100_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_3_i] -to [get_clocks -include_generated_clocks clk_100_i]
+
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_2_i] -to [get_clocks -include_generated_clocks clk_SODA200_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_rx200_3_i] -to [get_clocks -include_generated_clocks clk_SODA200_i]
+
+
+
+set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt0_rxresetdone_r3_reg]
+set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt1_rxresetdone_r3_reg]
+#//set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt2_rxresetdone_r3_reg]
+#//set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt3_rxresetdone_r3_reg]
+set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt0_txfsmresetdone_r2_reg]
+set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt1_txfsmresetdone_r2_reg]
+#//set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt2_txfsmresetdone_r2_reg]
+#//set_false_path -from [get_cells THE_FEE_SERDES/serdesQuadMUXwrapper1/gt3_txfsmresetdone_r2_reg]
+
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_r*/CLR}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_r*/CLR}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_r*/D}]
+set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_rxresetdone_r*/D}]
+
+# SODA_input GTX constraints
+#set_false_path -to [get_pins -hierarchical -filter {NAME =~ *reset_on_error_in_r*/D}]
+#set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells GTX_SODAinput_support_i/GTX_SODAinput_init_i/U0/GTX_SODAinput_i/gt0_GTX_SODAinput_i/gtxe2_i]
+#set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*RXOUTCLK}]]
+#set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*gt0_GTX_SODAinput_i*gtxe2_i*RXOUTCLK}]] -to [get_clocks -include_generated_clocks clk_100_i]
+
+
+# no critical timing for external ports:
+set_false_path -to [get_ports {fmc_led[0]}]
+set_false_path -to [get_ports {fmc_led[1]}]
+set_false_path -to [get_ports {fmc_led[2]}]
+set_false_path -to [get_ports {fmc_led[3]}]
+
+set_false_path -from [get_ports {fmc_sfp_los[0]}]
+set_false_path -from [get_ports {fmc_sfp_los[1]}]
+set_false_path -from [get_ports {fmc_sfp_los[2]}]
+set_false_path -from [get_ports {fmc_sfp_los[3]}]
+
+set_false_path -to [get_ports {fmc_sfp_tx_disable[0]}]
+set_false_path -to [get_ports {fmc_sfp_tx_disable[1]}]
+set_false_path -to [get_ports {fmc_sfp_tx_disable[2]}]
+set_false_path -to [get_ports {fmc_sfp_tx_disable[3]}]
+
+set_false_path -to [get_ports XADC_GPIO_0]
+set_false_path -to [get_ports XADC_GPIO_1]
+set_false_path -to [get_ports XADC_GPIO_2]
+set_false_path -to [get_ports XADC_GPIO_3]
+
+
+
+create_generated_clock -name clk_160div3_i [get_pins THE_MAIN_PLL/inst/mmcm_adv_inst/CLKOUT3]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_dataoutput_i*gtxe2_i*TXUSRCLK2]] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_160div3_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*TXOUTCLK]] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_160div3_i] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]]
+set_false_path -from [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter name=~*gt0_GTX_trb3_sync_2gb_i*gtxe2_i*RXOUTCLK]] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_200_i] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_160div3_i] -to [get_clocks -include_generated_clocks clk_200_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_100_i] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_160div3_i] -to [get_clocks -include_generated_clocks clk_100_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_tx200] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_160div3_i] -to [get_clocks -include_generated_clocks clk_tx200]
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_0_i] -to [get_clocks -include_generated_clocks clk_160div3_i]
+set_false_path -from [get_clocks -include_generated_clocks clk_rx200_1_i] -to [get_clocks -include_generated_clocks clk_160div3_i]
+
+set_property BITSTREAM.CONFIG.CONFIGRATE 12 [current_design]
+set_property CONFIG_MODE BPI16 [current_design]
diff --git a/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/DataConcentrator_KC705.xpr b/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/DataConcentrator_KC705.xpr
new file mode 100644
index 0000000..f91ab2f
--- /dev/null
+++ b/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/DataConcentrator_KC705.xpr
@@ -0,0 +1,2260 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2015.3 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="10" Path="P:/soda/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/DataConcentrator_KC705.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="3f163b0412574fb8ba700f5d67591f8b"/>
+    <Option Name="Part" Val="xc7k325tffg900-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="SourceMgmtMode" Val="None"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PPRDIR/DataConcentrator_KC705.ip_user_files"/>
+    <Option Name="IPStaticSourceDir" Val="$PPRDIR/DataConcentrator_KC705.ip_user_files/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../../sources/heap_sorter/sys_config.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_std.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/heap_sorter/sorter_pkg.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/div_pipe_r4_arch2/mypack.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/fifo_sbuf.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/fifo_19x16_obuf.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/heap_sorter/dpram4_synth.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_components.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_sbuf6.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_sbuf5.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_sbuf4.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_sbuf3.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_sbuf2.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_sbuf.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/heap_sorter/sort_dpram.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/heap_sorter/sorter_ctrl.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/div_pipe_r4_arch2/nr_r4_cel.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_sync_block.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_gt.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_cpll_railing.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_LUT_package.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/div_pipe_r4_arch2/cond_add.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_sync_block.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_gt.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_cpll_railing.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/Panda_package.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/cluster/CN_cluster_XY_LUT.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/cluster/blockmemdirectread.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_priority_encoder.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_dummy_fifo.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_CRC.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_sbuf.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/trb_net16_fifo.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/heap_sorter/sorter_sys.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/shift_register.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/basics/ram_16x16_dp.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_tx_startup_fsm.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_rx_startup_fsm.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_multi_gt.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_auto_phase_align.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/div_pipe_r4_arch2/div_r4_pipe.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_time_lookuptable.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_timeshift_lookuptable.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_energy_correction.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/crc8_add_check32.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_tx_startup_fsm.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_rx_startup_fsm.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_multi_gt.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_auto_phase_align.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_hub_func.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_posedge_to_pulse.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/blockmem.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/cluster/CN_precluster_findgap.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/cluster/CN_precluster_build.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/cluster/CN_fiforead2write.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_priority_arbiter.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_pattern_gen.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_term_ibuf.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_term.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_obuf_nodata.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_obuf.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_ibuf.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_dummy_fifo.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_addresses.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/basics/rom_16x8.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/basics/pulse_stretch.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/xilinx/virtex4/lattice_ecp2m_fifo.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_init.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_clock_module.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_clock_module.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/fifo_var_oreg.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_time_energy_LUTs.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_split_data.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_sort_hits.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_fiforead2write.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_CF_MAX_correction.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/crc8_add_check64.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_gt_usrclk_source.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_common_reset.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_init.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_components.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_clock_module.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/basics/signal_sync.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/version.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_addheader64bit.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/cluster/CN_preclustering.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_onewire_listener.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net_onewire.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_trigger.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_term_buf.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_regIO.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_ipudata.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_io_multiplexer.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_iobuf.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_api_base.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/synchronizer_to_other_clock.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/special/handler_lvl1.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/special/handler_ipu.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/special/handler_data.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_gt_usrclk_source.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_common_reset.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_common.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_gt_usrclk_source.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_common_reset.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_wavemux_readfifo.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_wavemux2to1.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_wave2packet64.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_superburst2packet64.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_slowcontrol_to_serial.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_slowcontrol_receive_from_cpu.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_slowcontrol_packetbuilder.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_separate_data.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_mux2to1.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_measure_frequency.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_common.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_support.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_gt_usrclk_source.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/DC_data8to16.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/DC_data16to8.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_d8crc8.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/sync_bit.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/cluster/CN_package.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_data_64bit_cluster.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/trb_net_fifo_16bit_bram_dualport.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_regio_bus_handler.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="simulation"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_endpoint_hades_full.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/special/spi_slim.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/spi_dpram_32_to_8_dummy.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/HUB_8to16_SODA.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/HUB_16to8_SODA.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/special/handler_trigger_and_data.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_support.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_support.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_sorting_wavemux.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_sorting_mux.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_slow_control_TRB3.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_fibermodule_interface.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_extract_wave.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_extract_data.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_data_wave_to_64bit.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_combine_pulses.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_check_timestamp.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_checkwave.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/special/bus_register_handler.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_support.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/DC_rxBitLock.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_reply_pkt_builder.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/serdesDualMUXwrapper.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/gtpBufLayerPackage.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_fifo8to32_SODA.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_fifo32to8_SODA.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_superburst_gen.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_reply_handler.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_packet_builder.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_calibration_timer.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/posedge_to_pulse.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_packet_handler.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_SODA_clockcrossing.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/CN_checkdata.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/special/trb_net_reset_handler.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/trb_net16_med_sync_gtx2_kintex7_sfp.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/trb_net16_endpoint_hades_full_handler.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/special/spi_master.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/special/spi_databus_memory.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/GTX_dataoutputwrapper.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trbnet/special/fpga_reboot.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_module_TRB3.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/dataconversion_for_serdes16.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/jittercleaner_200M.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/DC_SODAserdesWrapper.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_hub.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/serdesQuadBufLayerMUX.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../../trb3/base/trb3_components.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_start_of_burst_control.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../../source/soda_source.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/trb3_kc705_data_concentrator.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_read36bitsfifo.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/DC_wavemux.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_trb3_2gb/GTX_trb3_2gb.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_256x66/async_fifo_256x66.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/fifo_18x512_oreg/fifo_18x512_oreg.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/fifo_36x16k_oreg/fifo_36x16k_oreg.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/fifo_36x32k_oreg/fifo_36x32k_oreg.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/fifo_36x512_oreg/fifo_36x512_oreg.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/pll_in200_out200_160_100_80/pll_in200_out200_160_100_80.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_18x1k/xilinx_fifo_18x1k.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_18x1k_datacount/xilinx_fifo_18x1k_datacount.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_18x16/xilinx_fifo_18x16.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_18x32/xilinx_fifo_18x32.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_18x64/xilinx_fifo_18x64.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_19x16_obuf/xilinx_fifo_19x16_obuf.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_dualport_18x1k/xilinx_fifo_dualport_18x1k.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_sbuf/xilinx_fifo_sbuf.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dataoutput/GTX_dataoutput.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dualSODA/GTX_dualSODA.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_16x8/async_fifo_16x8.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_512x32/async_fifo_512x32.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_512x99/async_fifo_512x99.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_4096x103/async_fifo_nn_4096x103.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_4096x36/async_fifo_nn_4096x36.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_progfull1900_progempty128_2048x36/async_fifo_nn_progfull1900_progempty128_2048x36.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_th_1024x36/async_fifo_nn_th_1024x36.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_thfull_FWFT_2048x36/async_fifo_nn_thfull_FWFT_2048x36.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_thfull_FWFT_512x36/async_fifo_nn_thfull_FWFT_512x36.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/clock100to200/clock100to200.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/pll_in200_out200/pll_in200_out200.upgrade_log"/>
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/sync_fifo_512x41/sync_fifo_512x41.upgrade_log"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="trb3_kc705_data_concentrator"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/DataConcentrator_KC705.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/KC705_Rev1_0_U1.ucf.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/DataConcentrator_KC705_debug.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TargetConstrsFile" Val="$PPRDIR/DataConcentrator_KC705_debug.xdc"/>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="trb3_kc705_data_concentrator"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="GTX_dataoutput" Type="BlockSrcs" RelSrcDir="$PSRCDIR/GTX_dataoutput">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dataoutput/GTX_dataoutput.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="GTX_dataoutput"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="GTX_dualSODA" Type="BlockSrcs" RelSrcDir="$PSRCDIR/GTX_dualSODA">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/GTX_dualSODA/GTX_dualSODA.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="GTX_dualSODA"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_16x8" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_16x8">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_16x8/async_fifo_16x8.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_16x8"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_256x66" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_256x66">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_256x66/async_fifo_256x66.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_256x66"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_512x32" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_512x32">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_512x32/async_fifo_512x32.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_512x32"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_512x99" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_512x99">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_512x99/async_fifo_512x99.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_512x99"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_nn_4096x103" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_nn_4096x103">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_4096x103/async_fifo_nn_4096x103.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_nn_4096x103"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_nn_4096x36" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_nn_4096x36">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_4096x36/async_fifo_nn_4096x36.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_nn_4096x36"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_nn_progfull1900_progempty128_2048x36" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_nn_progfull1900_progempty128_2048x36">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_progfull1900_progempty128_2048x36/async_fifo_nn_progfull1900_progempty128_2048x36.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_nn_progfull1900_progempty128_2048x36"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_nn_th_1024x36" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_nn_th_1024x36">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_th_1024x36/async_fifo_nn_th_1024x36.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_nn_th_1024x36"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_nn_thfull_FWFT_2048x36" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_nn_thfull_FWFT_2048x36">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_thfull_FWFT_2048x36/async_fifo_nn_thfull_FWFT_2048x36.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_nn_thfull_FWFT_2048x36"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_nn_thfull_FWFT_512x36" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_nn_thfull_FWFT_512x36">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_thfull_FWFT_512x36/async_fifo_nn_thfull_FWFT_512x36.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_nn_thfull_FWFT_512x36"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="clock100to200" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clock100to200">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/clock100to200/clock100to200.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="clock100to200"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="fifo_18x512_oreg" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_18x512_oreg">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/fifo_18x512_oreg/fifo_18x512_oreg.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="fifo_18x512_oreg"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="fifo_36x16k_oreg" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_36x16k_oreg">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/fifo_36x16k_oreg/fifo_36x16k_oreg.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="fifo_36x16k_oreg"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="fifo_36x32k_oreg" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_36x32k_oreg">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/fifo_36x32k_oreg/fifo_36x32k_oreg.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="fifo_36x32k_oreg"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="fifo_36x512_oreg" Type="BlockSrcs" RelSrcDir="$PSRCDIR/fifo_36x512_oreg">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/fifo_36x512_oreg/fifo_36x512_oreg.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="fifo_36x512_oreg"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="pll_in200_out200" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pll_in200_out200">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/pll_in200_out200/pll_in200_out200.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="pll_in200_out200"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sync_fifo_512x41" Type="BlockSrcs" RelSrcDir="$PSRCDIR/sync_fifo_512x41">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/sync_fifo_512x41/sync_fifo_512x41.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="sync_fifo_512x41"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="xilinx_fifo_18x16" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xilinx_fifo_18x16">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_18x16/xilinx_fifo_18x16.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="xilinx_fifo_18x16"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="xilinx_fifo_18x1k" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xilinx_fifo_18x1k">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_18x1k/xilinx_fifo_18x1k.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="xilinx_fifo_18x1k"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="xilinx_fifo_18x1k_datacount" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xilinx_fifo_18x1k_datacount">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_18x1k_datacount/xilinx_fifo_18x1k_datacount.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="xilinx_fifo_18x1k_datacount"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="xilinx_fifo_18x32" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xilinx_fifo_18x32">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_18x32/xilinx_fifo_18x32.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="xilinx_fifo_18x32"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="xilinx_fifo_18x64" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xilinx_fifo_18x64">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_18x64/xilinx_fifo_18x64.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="xilinx_fifo_18x64"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="xilinx_fifo_19x16_obuf" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xilinx_fifo_19x16_obuf">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_19x16_obuf/xilinx_fifo_19x16_obuf.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="xilinx_fifo_19x16_obuf"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="xilinx_fifo_dualport_18x1k" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xilinx_fifo_dualport_18x1k">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_dualport_18x1k/xilinx_fifo_dualport_18x1k.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="xilinx_fifo_dualport_18x1k"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="xilinx_fifo_sbuf" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xilinx_fifo_sbuf">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/xilinx_fifo_sbuf/xilinx_fifo_sbuf.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="xilinx_fifo_sbuf"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="pll_in200_out200_160_100_80" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pll_in200_out200_160_100_80">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/pll_in200_out200_160_100_80/pll_in200_out200_160_100_80.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="pll_in200_out200_160_100_80"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="async_fifo_nn_progfull980_progempty768_FWFT_1024x99" Type="BlockSrcs" RelSrcDir="$PSRCDIR/async_fifo_nn_progfull980_progempty768_FWFT_1024x99">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/async_fifo_nn_progfull980_progempty768_FWFT_1024x99/async_fifo_nn_progfull980_progempty768_FWFT_1024x99.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="async_fifo_nn_progfull980_progempty768_FWFT_1024x99"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="syncfifo_1024x66_almostempty256" Type="BlockSrcs" RelSrcDir="$PSRCDIR/syncfifo_1024x66_almostempty256">
+      <File Path="$PPRDIR/../../sources/xilinx/Kintex7/syncfifo_1024x66_almostempty256/syncfifo_1024x66_almostempty256.xci">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="TopModule" Val="syncfifo_1024x66_almostempty256"/>
+        <Option Name="UseBlackboxStub" Val="1"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+    <Simulator Name="ActiveHDL">
+      <Option Name="Description" Val="Active-HDL Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
+        <Step Id="synth_design" PostStepTclHook="$PPRDIR/../post_synthesis.tcl"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="GTX_dataoutput_synth_1" Type="Ft3:Synth" SrcSet="GTX_dataoutput" Part="xc7k325tffg900-2" ConstrsSet="GTX_dataoutput" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/GTX_dataoutput_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="GTX_dualSODA_synth_1" Type="Ft3:Synth" SrcSet="GTX_dualSODA" Part="xc7k325tffg900-2" ConstrsSet="GTX_dualSODA" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/GTX_dualSODA_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_16x8_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_16x8" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_16x8" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_16x8_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_256x66_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_256x66" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_256x66" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_256x66_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_512x32_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_512x32" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_512x32" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_512x32_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_512x99_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_512x99" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_512x99" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_512x99_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_nn_4096x103_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_nn_4096x103" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_4096x103" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_nn_4096x103_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_nn_4096x36_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_nn_4096x36" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_4096x36" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_nn_4096x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_nn_progfull1900_progempty128_2048x36_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_nn_progfull1900_progempty128_2048x36" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_progfull1900_progempty128_2048x36" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_nn_progfull1900_progempty128_2048x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_nn_th_1024x36_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_nn_th_1024x36" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_th_1024x36" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_nn_th_1024x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_nn_thfull_FWFT_2048x36_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_nn_thfull_FWFT_2048x36" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_thfull_FWFT_2048x36" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_nn_thfull_FWFT_2048x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_nn_thfull_FWFT_512x36_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_nn_thfull_FWFT_512x36" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_thfull_FWFT_512x36" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_nn_thfull_FWFT_512x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="clock100to200_synth_1" Type="Ft3:Synth" SrcSet="clock100to200" Part="xc7k325tffg900-2" ConstrsSet="clock100to200" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/clock100to200_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="fifo_18x512_oreg_synth_1" Type="Ft3:Synth" SrcSet="fifo_18x512_oreg" Part="xc7k325tffg900-2" ConstrsSet="fifo_18x512_oreg" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/fifo_18x512_oreg_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="fifo_36x16k_oreg_synth_1" Type="Ft3:Synth" SrcSet="fifo_36x16k_oreg" Part="xc7k325tffg900-2" ConstrsSet="fifo_36x16k_oreg" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/fifo_36x16k_oreg_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="fifo_36x32k_oreg_synth_1" Type="Ft3:Synth" SrcSet="fifo_36x32k_oreg" Part="xc7k325tffg900-2" ConstrsSet="fifo_36x32k_oreg" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/fifo_36x32k_oreg_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="fifo_36x512_oreg_synth_1" Type="Ft3:Synth" SrcSet="fifo_36x512_oreg" Part="xc7k325tffg900-2" ConstrsSet="fifo_36x512_oreg" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/fifo_36x512_oreg_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="pll_in200_out200_synth_1" Type="Ft3:Synth" SrcSet="pll_in200_out200" Part="xc7k325tffg900-2" ConstrsSet="pll_in200_out200" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/pll_in200_out200_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="sync_fifo_512x41_synth_1" Type="Ft3:Synth" SrcSet="sync_fifo_512x41" Part="xc7k325tffg900-2" ConstrsSet="sync_fifo_512x41" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/sync_fifo_512x41_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="xilinx_fifo_18x16_synth_1" Type="Ft3:Synth" SrcSet="xilinx_fifo_18x16" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x16" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/xilinx_fifo_18x16_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="xilinx_fifo_18x1k_synth_1" Type="Ft3:Synth" SrcSet="xilinx_fifo_18x1k" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x1k" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/xilinx_fifo_18x1k_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="xilinx_fifo_18x1k_datacount_synth_1" Type="Ft3:Synth" SrcSet="xilinx_fifo_18x1k_datacount" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x1k_datacount" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/xilinx_fifo_18x1k_datacount_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="xilinx_fifo_18x32_synth_1" Type="Ft3:Synth" SrcSet="xilinx_fifo_18x32" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x32" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/xilinx_fifo_18x32_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="xilinx_fifo_18x64_synth_1" Type="Ft3:Synth" SrcSet="xilinx_fifo_18x64" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x64" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/xilinx_fifo_18x64_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="xilinx_fifo_19x16_obuf_synth_1" Type="Ft3:Synth" SrcSet="xilinx_fifo_19x16_obuf" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_19x16_obuf" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/xilinx_fifo_19x16_obuf_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="xilinx_fifo_dualport_18x1k_synth_1" Type="Ft3:Synth" SrcSet="xilinx_fifo_dualport_18x1k" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_dualport_18x1k" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/xilinx_fifo_dualport_18x1k_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="xilinx_fifo_sbuf_synth_1" Type="Ft3:Synth" SrcSet="xilinx_fifo_sbuf" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_sbuf" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/xilinx_fifo_sbuf_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="pll_in200_out200_160_100_80_synth_1" Type="Ft3:Synth" SrcSet="pll_in200_out200_160_100_80" Part="xc7k325tffg900-2" ConstrsSet="pll_in200_out200_160_100_80" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/pll_in200_out200_160_100_80_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="async_fifo_nn_progfull980_progempty768_FWFT_1024x99_synth_1" Type="Ft3:Synth" SrcSet="async_fifo_nn_progfull980_progempty768_FWFT_1024x99" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_progfull980_progempty768_FWFT_1024x99" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/async_fifo_nn_progfull980_progempty768_FWFT_1024x99_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="syncfifo_1024x66_almostempty256_synth_1" Type="Ft3:Synth" SrcSet="syncfifo_1024x66_almostempty256" Part="xc7k325tffg900-2" ConstrsSet="syncfifo_1024x66_almostempty256" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/syncfifo_1024x66_almostempty256_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2015"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design" EnableStepBool="1"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream" PreStepTclHook="$PPRDIR/../pre_bitstream.tcl">
+          <Option Id="BinFile">1</Option>
+          <Option Id="RawbitFileBool">1</Option>
+        </Step>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+    </Run>
+    <Run Id="GTX_dataoutput_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="GTX_dataoutput" Description="Vivado Implementation Defaults" SynthRun="GTX_dataoutput_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="GTX_dualSODA_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="GTX_dualSODA" Description="Vivado Implementation Defaults" SynthRun="GTX_dualSODA_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_16x8_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_16x8" Description="Vivado Implementation Defaults" SynthRun="async_fifo_16x8_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_256x66_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_256x66" Description="Vivado Implementation Defaults" SynthRun="async_fifo_256x66_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_512x32_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_512x32" Description="Vivado Implementation Defaults" SynthRun="async_fifo_512x32_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_512x99_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_512x99" Description="Vivado Implementation Defaults" SynthRun="async_fifo_512x99_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_nn_4096x103_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_4096x103" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_4096x103_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_nn_4096x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_4096x36" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_4096x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_nn_progfull1900_progempty128_2048x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_progfull1900_progempty128_2048x36" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_progfull1900_progempty128_2048x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_nn_th_1024x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_th_1024x36" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_th_1024x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_nn_thfull_FWFT_2048x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_thfull_FWFT_2048x36" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_thfull_FWFT_2048x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_nn_thfull_FWFT_512x36_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_thfull_FWFT_512x36" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_thfull_FWFT_512x36_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="clock100to200_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="clock100to200" Description="Vivado Implementation Defaults" SynthRun="clock100to200_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="fifo_18x512_oreg_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_18x512_oreg" Description="Vivado Implementation Defaults" SynthRun="fifo_18x512_oreg_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="fifo_36x16k_oreg_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_36x16k_oreg" Description="Vivado Implementation Defaults" SynthRun="fifo_36x16k_oreg_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="fifo_36x32k_oreg_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_36x32k_oreg" Description="Vivado Implementation Defaults" SynthRun="fifo_36x32k_oreg_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="fifo_36x512_oreg_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="fifo_36x512_oreg" Description="Vivado Implementation Defaults" SynthRun="fifo_36x512_oreg_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="pll_in200_out200_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="pll_in200_out200" Description="Vivado Implementation Defaults" SynthRun="pll_in200_out200_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="sync_fifo_512x41_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="sync_fifo_512x41" Description="Vivado Implementation Defaults" SynthRun="sync_fifo_512x41_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="xilinx_fifo_18x16_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x16" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_18x16_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="xilinx_fifo_18x1k_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x1k" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_18x1k_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="xilinx_fifo_18x1k_datacount_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x1k_datacount" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_18x1k_datacount_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="xilinx_fifo_18x32_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x32" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_18x32_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="xilinx_fifo_18x64_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_18x64" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_18x64_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="xilinx_fifo_19x16_obuf_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_19x16_obuf" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_19x16_obuf_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="xilinx_fifo_dualport_18x1k_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_dualport_18x1k" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_dualport_18x1k_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="xilinx_fifo_sbuf_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="xilinx_fifo_sbuf" Description="Vivado Implementation Defaults" SynthRun="xilinx_fifo_sbuf_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="pll_in200_out200_160_100_80_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="pll_in200_out200_160_100_80" Description="Vivado Implementation Defaults" SynthRun="pll_in200_out200_160_100_80_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="async_fifo_nn_progfull980_progempty768_FWFT_1024x99_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="async_fifo_nn_progfull980_progempty768_FWFT_1024x99" Description="Vivado Implementation Defaults" SynthRun="async_fifo_nn_progfull980_progempty768_FWFT_1024x99_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+    <Run Id="syncfifo_1024x66_almostempty256_impl_1" Type="Ft2:EntireDesign" Part="xc7k325tffg900-2" ConstrsSet="syncfifo_1024x66_almostempty256" Description="Vivado Implementation Defaults" SynthRun="syncfifo_1024x66_almostempty256_synth_1" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2015"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+    </Run>
+  </Runs>
+</Project>
diff --git a/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/KC705_Rev1_0_U1.ucf.xdc b/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/KC705_Rev1_0_U1.ucf.xdc
new file mode 100644
index 0000000..1a32d20
--- /dev/null
+++ b/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/KC705_Rev1_0_U1.ucf.xdc
@@ -0,0 +1,1168 @@
+set_property PACKAGE_PIN Y20 [get_ports SFP_TX_DISABLE]
+set_property IOSTANDARD LVCMOS25 [get_ports SFP_TX_DISABLE]
+
+set_property PACKAGE_PIN Y23 [get_ports USER_SMA_GPIO_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_GPIO_P]
+set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_P]
+set_property PACKAGE_PIN Y24 [get_ports USER_SMA_GPIO_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_GPIO_N]
+set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_N]
+
+#set_property PACKAGE_PIN Y21 [get_ports SDIO_SDWP]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_SDWP]
+#set_property PACKAGE_PIN AA21 [get_ports SDIO_SDDET]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_SDDET]
+#set_property PACKAGE_PIN AB22 [get_ports SDIO_CMD_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_CMD_LS]
+#set_property PACKAGE_PIN AB23 [get_ports SDIO_CLK_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_CLK_LS]
+#set_property PACKAGE_PIN AA22 [get_ports SDIO_DAT2_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_DAT2_LS]
+#set_property PACKAGE_PIN AA23 [get_ports SDIO_DAT1_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_DAT1_LS]
+#set_property PACKAGE_PIN AC20 [get_ports SDIO_DAT0_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_DAT0_LS]
+#set_property PACKAGE_PIN AC21 [get_ports SDIO_CD_DAT3_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SDIO_CD_DAT3_LS]
+#set_property PACKAGE_PIN AA20 [get_ports FMC_LPC_LA12_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA12_P]
+#set_property PACKAGE_PIN AB20 [get_ports FMC_LPC_LA12_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA12_N]
+#set_property PACKAGE_PIN AB24 [get_ports FMC_LPC_LA13_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA13_P]
+#set_property PACKAGE_PIN AC25 [get_ports FMC_LPC_LA13_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA13_N]
+#set_property PACKAGE_PIN AC22 [get_ports FMC_LPC_LA16_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA16_P]
+#set_property PACKAGE_PIN AD22 [get_ports FMC_LPC_LA16_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA16_N]
+#set_property PACKAGE_PIN AC24 [get_ports FMC_LPC_LA15_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA15_P]
+#set_property PACKAGE_PIN AD24 [get_ports FMC_LPC_LA15_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA15_N]
+#set_property PACKAGE_PIN AD21 [get_ports FMC_LPC_LA14_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA14_P]
+#set_property PACKAGE_PIN AE21 [get_ports FMC_LPC_LA14_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA14_N]
+#set_property PACKAGE_PIN AE23 [get_ports FMC_LPC_LA01_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA01_CC_P]
+#set_property PACKAGE_PIN AF23 [get_ports FMC_LPC_LA01_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA01_CC_N]
+#set_property PACKAGE_PIN AD23 [get_ports FMC_LPC_LA00_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA00_CC_P]
+#set_property PACKAGE_PIN AE24 [get_ports FMC_LPC_LA00_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA00_CC_N]
+#set_property PACKAGE_PIN AF22 [get_ports FMC_LPC_CLK0_M2C_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK0_M2C_P]
+#set_property PACKAGE_PIN AG23 [get_ports FMC_LPC_CLK0_M2C_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK0_M2C_N]
+#set_property PACKAGE_PIN AG24 [get_ports SI5326_INT_ALM_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SI5326_INT_ALM_LS]
+#set_property PACKAGE_PIN AH24 [get_ports HDMI_INT]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_INT]
+#set_property PACKAGE_PIN AJ24 [get_ports FMC_LPC_LA10_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA10_P]
+#set_property PACKAGE_PIN AK25 [get_ports FMC_LPC_LA10_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA10_N]
+#set_property PACKAGE_PIN AE25 [get_ports FMC_LPC_LA11_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA11_P]
+#set_property PACKAGE_PIN AF25 [get_ports FMC_LPC_LA11_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA11_N]
+#set_property PACKAGE_PIN AK23 [get_ports FMC_LPC_LA09_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA09_P]
+#set_property PACKAGE_PIN AK24 [get_ports FMC_LPC_LA09_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA09_N]
+#set_property PACKAGE_PIN AG25 [get_ports FMC_LPC_LA07_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA07_P]
+#set_property PACKAGE_PIN AH25 [get_ports FMC_LPC_LA07_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA07_N]
+#set_property PACKAGE_PIN AF20 [get_ports FMC_LPC_LA02_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA02_P]
+#set_property PACKAGE_PIN AF21 [get_ports FMC_LPC_LA02_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA02_N]
+#set_property PACKAGE_PIN AG22 [get_ports FMC_LPC_LA05_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA05_P]
+#set_property PACKAGE_PIN AH22 [get_ports FMC_LPC_LA05_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA05_N]
+#set_property PACKAGE_PIN AJ22 [get_ports FMC_LPC_LA08_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA08_P]
+#set_property PACKAGE_PIN AJ23 [get_ports FMC_LPC_LA08_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA08_N]
+#set_property PACKAGE_PIN AG20 [get_ports FMC_LPC_LA03_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA03_P]
+#set_property PACKAGE_PIN AH20 [get_ports FMC_LPC_LA03_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA03_N]
+#set_property PACKAGE_PIN AH21 [get_ports FMC_LPC_LA04_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA04_P]
+#set_property PACKAGE_PIN AJ21 [get_ports FMC_LPC_LA04_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA04_N]
+#set_property PACKAGE_PIN AK20 [get_ports FMC_LPC_LA06_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA06_P]
+#set_property PACKAGE_PIN AK21 [get_ports FMC_LPC_LA06_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA06_N]
+#set_property PACKAGE_PIN AE20 [get_ports SI5326_RST_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports SI5326_RST_LS]
+#set_property PACKAGE_PIN Y25 [get_ports ROTARY_INCB]
+#set_property IOSTANDARD LVCMOS25 [get_ports ROTARY_INCB]
+#set_property PACKAGE_PIN Y26 [get_ports ROTARY_INCA]
+#set_property IOSTANDARD LVCMOS25 [get_ports ROTARY_INCA]
+#set_property PACKAGE_PIN AA26 [get_ports ROTARY_PUSH]
+#set_property IOSTANDARD LVCMOS25 [get_ports ROTARY_PUSH]
+set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_P]
+set_property PACKAGE_PIN W28 [get_ports REC_CLOCK_C_N]
+set_property PACKAGE_PIN W27 [get_ports REC_CLOCK_C_P]
+set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_N]
+#set_property PACKAGE_PIN Y28 [get_ports GPIO_DIP_SW3]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW3]
+#set_property PACKAGE_PIN AA28 [get_ports GPIO_DIP_SW2]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW2]
+#set_property PACKAGE_PIN W29 [get_ports GPIO_DIP_SW1]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW1]
+#set_property PACKAGE_PIN Y29 [get_ports GPIO_DIP_SW0]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_DIP_SW0]
+set_property PACKAGE_PIN AA27 [get_ports XADC_GPIO_3]
+set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_3]
+set_property PACKAGE_PIN AB28 [get_ports XADC_GPIO_2]
+set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2]
+set_property PACKAGE_PIN AA25 [get_ports XADC_GPIO_1]
+set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1]
+set_property PACKAGE_PIN AB25 [get_ports XADC_GPIO_0]
+set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0]
+#set_property PACKAGE_PIN AC29 [get_ports FMC_LPC_LA33_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA33_P]
+#set_property PACKAGE_PIN AC30 [get_ports FMC_LPC_LA33_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA33_N]
+#set_property PACKAGE_PIN Y30 [get_ports FMC_LPC_LA32_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA32_P]
+#set_property PACKAGE_PIN AA30 [get_ports FMC_LPC_LA32_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA32_N]
+#set_property PACKAGE_PIN AD29 [get_ports FMC_LPC_LA31_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA31_P]
+#set_property PACKAGE_PIN AE29 [get_ports FMC_LPC_LA31_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA31_N]
+#set_property PACKAGE_PIN AB29 [get_ports FMC_LPC_LA30_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA30_P]
+#set_property PACKAGE_PIN AB30 [get_ports FMC_LPC_LA30_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA30_N]
+#set_property PACKAGE_PIN AD27 [get_ports FMC_LPC_LA18_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA18_CC_P]
+#set_property PACKAGE_PIN AD28 [get_ports FMC_LPC_LA18_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA18_CC_N]
+#set_property PACKAGE_PIN AB27 [get_ports FMC_LPC_LA17_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA17_CC_P]
+#set_property PACKAGE_PIN AC27 [get_ports FMC_LPC_LA17_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA17_CC_N]
+#set_property PACKAGE_PIN AG29 [get_ports FMC_LPC_CLK1_M2C_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK1_M2C_P]
+#set_property PACKAGE_PIN AH29 [get_ports FMC_LPC_CLK1_M2C_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_CLK1_M2C_N]
+#set_property PACKAGE_PIN AE28 [get_ports FMC_LPC_LA29_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA29_P]
+#set_property PACKAGE_PIN AF28 [get_ports FMC_LPC_LA29_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA29_N]
+#set_property PACKAGE_PIN AK29 [get_ports FMC_LPC_LA26_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA26_P]
+#set_property PACKAGE_PIN AK30 [get_ports FMC_LPC_LA26_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA26_N]
+#set_property PACKAGE_PIN AE30 [get_ports FMC_LPC_LA28_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA28_P]
+#set_property PACKAGE_PIN AF30 [get_ports FMC_LPC_LA28_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA28_N]
+#set_property PACKAGE_PIN AJ28 [get_ports FMC_LPC_LA27_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA27_P]
+#set_property PACKAGE_PIN AJ29 [get_ports FMC_LPC_LA27_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA27_N]
+#set_property PACKAGE_PIN AG30 [get_ports FMC_LPC_LA24_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA24_P]
+#set_property PACKAGE_PIN AH30 [get_ports FMC_LPC_LA24_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA24_N]
+#set_property PACKAGE_PIN AC26 [get_ports FMC_LPC_LA25_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA25_P]
+#set_property PACKAGE_PIN AD26 [get_ports FMC_LPC_LA25_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA25_N]
+#set_property PACKAGE_PIN AJ27 [get_ports FMC_LPC_LA22_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA22_P]
+#set_property PACKAGE_PIN AK28 [get_ports FMC_LPC_LA22_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA22_N]
+#set_property PACKAGE_PIN AG27 [get_ports FMC_LPC_LA21_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA21_P]
+#set_property PACKAGE_PIN AG28 [get_ports FMC_LPC_LA21_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA21_N]
+#set_property PACKAGE_PIN AH26 [get_ports FMC_LPC_LA23_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA23_P]
+#set_property PACKAGE_PIN AH27 [get_ports FMC_LPC_LA23_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA23_N]
+#set_property PACKAGE_PIN AF26 [get_ports FMC_LPC_LA20_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA20_P]
+#set_property PACKAGE_PIN AF27 [get_ports FMC_LPC_LA20_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA20_N]
+#set_property PACKAGE_PIN AJ26 [get_ports FMC_LPC_LA19_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA19_P]
+#set_property PACKAGE_PIN AK26 [get_ports FMC_LPC_LA19_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_LA19_N]
+#set_property PACKAGE_PIN AE26 [get_ports GPIO_LED_4_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_4_LS]
+#set_property PACKAGE_PIN R19 [get_ports PHY_RXD4]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD4]
+#set_property PACKAGE_PIN P24 [get_ports FLASH_D0]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D0]
+#set_property PACKAGE_PIN R25 [get_ports FLASH_D1]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D1]
+#set_property PACKAGE_PIN R20 [get_ports FLASH_D2]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D2]
+#set_property PACKAGE_PIN R21 [get_ports FLASH_D3]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D3]
+#set_property PACKAGE_PIN R23 [get_ports PHY_MDC]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_MDC]
+#set_property PACKAGE_PIN R24 [get_ports FPGA_EMCCLK]
+#set_property IOSTANDARD LVCMOS25 [get_ports FPGA_EMCCLK]
+#set_property PACKAGE_PIN T20 [get_ports FLASH_D4]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D4]
+#set_property PACKAGE_PIN T21 [get_ports FLASH_D5]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D5]
+#set_property PACKAGE_PIN T22 [get_ports FLASH_D6]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D6]
+#set_property PACKAGE_PIN T23 [get_ports FLASH_D7]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D7]
+#set_property PACKAGE_PIN U19 [get_ports FPGA_FCS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FPGA_FCS]
+#set_property PACKAGE_PIN U20 [get_ports FLASH_D8]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D8]
+#set_property PACKAGE_PIN P29 [get_ports FLASH_D9]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D9]
+#set_property PACKAGE_PIN R29 [get_ports FLASH_D10]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D10]
+#set_property PACKAGE_PIN P27 [get_ports FLASH_D11]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D11]
+#set_property PACKAGE_PIN P28 [get_ports FLASH_D12]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D12]
+#set_property PACKAGE_PIN R30 [get_ports PHY_CRS]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_CRS]
+#set_property PACKAGE_PIN T30 [get_ports FLASH_D13]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D13]
+#set_property PACKAGE_PIN P26 [get_ports FLASH_D14]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D14]
+#set_property PACKAGE_PIN R26 [get_ports FLASH_D15]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D15]
+#set_property PACKAGE_PIN R28 [get_ports PHY_RXCTL_RXDV]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXCTL_RXDV]
+#set_property PACKAGE_PIN T28 [get_ports PHY_RXD7]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD7]
+#set_property PACKAGE_PIN T26 [get_ports PHY_RXD6]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD6]
+#set_property PACKAGE_PIN T27 [get_ports PHY_RXD5]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD5]
+#set_property PACKAGE_PIN U27 [get_ports PHY_RXCLK]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXCLK]
+#set_property PACKAGE_PIN U28 [get_ports PHY_RXD3]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD3]
+#set_property PACKAGE_PIN T25 [get_ports PHY_RXD2]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD2]
+#set_property PACKAGE_PIN U25 [get_ports PHY_RXD1]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD1]
+#set_property PACKAGE_PIN U29 [get_ports FLASH_WAIT]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_WAIT]
+#set_property PACKAGE_PIN U30 [get_ports PHY_RXD0]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD0]
+#set_property PACKAGE_PIN V26 [get_ports PHY_RXER]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXER]
+#set_property PACKAGE_PIN V27 [get_ports FLASH_A15]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A15]
+#set_property PACKAGE_PIN V29 [get_ports FLASH_A14]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A14]
+#set_property PACKAGE_PIN V30 [get_ports FLASH_A13]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A13]
+#set_property PACKAGE_PIN V25 [get_ports FLASH_A12]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A12]
+#set_property PACKAGE_PIN W26 [get_ports FLASH_A11]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A11]
+#set_property PACKAGE_PIN V19 [get_ports FLASH_A10]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A10]
+#set_property PACKAGE_PIN V20 [get_ports FLASH_A9]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A9]
+#set_property PACKAGE_PIN W23 [get_ports FLASH_A8]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A8]
+#set_property PACKAGE_PIN W24 [get_ports FLASH_A7]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A7]
+#set_property PACKAGE_PIN U22 [get_ports SM_FAN_TACH]
+#set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_TACH]
+#set_property PACKAGE_PIN U23 [get_ports FLASH_A6]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A6]
+#set_property PACKAGE_PIN V21 [get_ports FLASH_A5]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A5]
+#set_property PACKAGE_PIN V22 [get_ports FLASH_A4]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A4]
+#set_property PACKAGE_PIN U24 [get_ports FLASH_A3]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A3]
+#set_property PACKAGE_PIN V24 [get_ports FLASH_A2]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A2]
+#set_property PACKAGE_PIN W21 [get_ports FLASH_A1]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A1]
+#set_property PACKAGE_PIN W22 [get_ports FLASH_A0]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A0]
+#set_property PACKAGE_PIN W19 [get_ports PHY_COL]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_COL]
+#set_property PACKAGE_PIN M19 [get_ports USB_TX]
+#set_property IOSTANDARD LVCMOS25 [get_ports USB_TX]
+#set_property PACKAGE_PIN J23 [get_ports XADC_VAUX0P_R]
+#set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0P_R]
+#set_property PACKAGE_PIN J24 [get_ports XADC_VAUX0N_R]
+#set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0N_R]
+#set_property PACKAGE_PIN L22 [get_ports XADC_VAUX8P_R]
+#set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8P_R]
+#set_property PACKAGE_PIN L23 [get_ports XADC_VAUX8N_R]
+#set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8N_R]
+#set_property PACKAGE_PIN K23 [get_ports USB_RTS]
+#set_property IOSTANDARD LVCMOS25 [get_ports USB_RTS]
+#set_property PACKAGE_PIN K24 [get_ports USB_RX]
+#set_property IOSTANDARD LVCMOS25 [get_ports USB_RX]
+#set_property PACKAGE_PIN L21 [get_ports IIC_SDA_MAIN]
+#set_property IOSTANDARD LVCMOS25 [get_ports IIC_SDA_MAIN]
+#set_property PACKAGE_PIN K21 [get_ports IIC_SCL_MAIN]
+#set_property IOSTANDARD LVCMOS25 [get_ports IIC_SCL_MAIN]
+#set_property PACKAGE_PIN J21 [get_ports PHY_MDIO]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_MDIO]
+#set_property PACKAGE_PIN J22 [get_ports FMC_LPC_PRSNT_M2C_B_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_LPC_PRSNT_M2C_B_LS]
+#set_property PACKAGE_PIN M20 [get_ports FMC_HPC_PRSNT_M2C_B_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_PRSNT_M2C_B_LS]
+#set_property PACKAGE_PIN L20 [get_ports PHY_RESET]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_RESET]
+#set_property PACKAGE_PIN J29 [get_ports FMC_HPC_PG_M2C_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_PG_M2C_LS]
+#set_property PACKAGE_PIN H29 [get_ports FMC_C2M_PG_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_C2M_PG_LS]
+#set_property PACKAGE_PIN J27 [get_ports FMC_VADJ_ON_B_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_VADJ_ON_B_LS]
+#set_property PACKAGE_PIN J28 [get_ports PHY_TXD7]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD7]
+#set_property PACKAGE_PIN L30 [get_ports PHY_TXD6]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD6]
+#set_property PACKAGE_PIN K30 [get_ports PHY_TXC_GTXCLK]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXC_GTXCLK]
+#set_property PACKAGE_PIN K26 [get_ports PHY_TXD5]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD5]
+#set_property PACKAGE_PIN J26 [get_ports PHY_TXD4]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD4]
+#set_property PACKAGE_PIN L26 [get_ports SM_FAN_PWM]
+#set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_PWM]
+#set_property PACKAGE_PIN L27 [get_ports USB_CTS]
+#set_property IOSTANDARD LVCMOS25 [get_ports USB_CTS]
+set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_P]
+set_property PACKAGE_PIN K25 [get_ports USER_SMA_CLOCK_N]
+set_property PACKAGE_PIN L25 [get_ports USER_SMA_CLOCK_P]
+set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_CLOCK_N]
+#set_property PACKAGE_PIN K28 [get_ports USER_CLOCK_P]
+#set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_P]
+#set_property PACKAGE_PIN K29 [get_ports USER_CLOCK_N]
+#set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_N]
+#set_property PACKAGE_PIN M28 [get_ports PHY_TXCLK]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXCLK]
+#set_property PACKAGE_PIN L28 [get_ports PHY_TXD3]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD3]
+#set_property PACKAGE_PIN M29 [get_ports PHY_TXD2]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD2]
+#set_property PACKAGE_PIN M30 [get_ports FLASH_ADV_B]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_ADV_B]
+#set_property PACKAGE_PIN N27 [get_ports PHY_TXD0]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD0]
+#set_property PACKAGE_PIN M27 [get_ports PHY_TXCTL_TXEN]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXCTL_TXEN]
+#set_property PACKAGE_PIN N29 [get_ports PHY_TXER]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXER]
+#set_property PACKAGE_PIN N30 [get_ports PHY_INT]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_INT]
+#set_property PACKAGE_PIN N25 [get_ports PHY_TXD1]
+#set_property IOSTANDARD LVCMOS25 [get_ports PHY_TXD1]
+#set_property PACKAGE_PIN N26 [get_ports FLASH_A23]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A23]
+#set_property PACKAGE_PIN N19 [get_ports FLASH_A22]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A22]
+#set_property PACKAGE_PIN N20 [get_ports FLASH_A21]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A21]
+#set_property PACKAGE_PIN N21 [get_ports FLASH_A20]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A20]
+#set_property PACKAGE_PIN N22 [get_ports FLASH_A19]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A19]
+#set_property PACKAGE_PIN P23 [get_ports IIC_MUX_RESET_B]
+#set_property IOSTANDARD LVCMOS25 [get_ports IIC_MUX_RESET_B]
+#set_property PACKAGE_PIN N24 [get_ports FLASH_A18]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A18]
+#set_property PACKAGE_PIN P21 [get_ports FLASH_A17]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A17]
+#set_property PACKAGE_PIN P22 [get_ports FLASH_A16]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A16]
+#set_property PACKAGE_PIN M24 [get_ports FLASH_OE_B]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_OE_B]
+#set_property PACKAGE_PIN M25 [get_ports FLASH_FWE_B]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_FWE_B]
+#set_property PACKAGE_PIN M22 [get_ports FLASH_A25]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A25]
+#set_property PACKAGE_PIN M23 [get_ports FLASH_A24]
+#set_property IOSTANDARD LVCMOS25 [get_ports FLASH_A24]
+set_property PACKAGE_PIN P19 [get_ports SFP_LOS_LS]
+set_property IOSTANDARD LVCMOS25 [get_ports SFP_LOS_LS]
+#set_property PACKAGE_PIN F23 [get_ports PCIE_WAKE_B_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports PCIE_WAKE_B_LS]
+#set_property PACKAGE_PIN B23 [get_ports HDMI_R_D0]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D0]
+#set_property PACKAGE_PIN A23 [get_ports HDMI_R_D1]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D1]
+#set_property PACKAGE_PIN E23 [get_ports HDMI_R_D2]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D2]
+#set_property PACKAGE_PIN D23 [get_ports HDMI_R_D3]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D3]
+#set_property PACKAGE_PIN F25 [get_ports HDMI_R_D4]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D4]
+#set_property PACKAGE_PIN E25 [get_ports HDMI_R_D5]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D5]
+#set_property PACKAGE_PIN E24 [get_ports HDMI_R_D6]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D6]
+#set_property PACKAGE_PIN D24 [get_ports HDMI_R_D7]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D7]
+#set_property PACKAGE_PIN F26 [get_ports HDMI_R_D8]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D8]
+#set_property PACKAGE_PIN E26 [get_ports HDMI_R_D9]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D9]
+#set_property PACKAGE_PIN G23 [get_ports HDMI_R_D10]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D10]
+#set_property PACKAGE_PIN G24 [get_ports HDMI_R_D11]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D11]
+#set_property PACKAGE_PIN B27 [get_ports FMC_HPC_LA16_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA16_P]
+#set_property PACKAGE_PIN A27 [get_ports FMC_HPC_LA16_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA16_N]
+#set_property PACKAGE_PIN C24 [get_ports FMC_HPC_LA15_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA15_P]
+#set_property PACKAGE_PIN B24 [get_ports FMC_HPC_LA15_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA15_N]
+#set_property PACKAGE_PIN B28 [get_ports FMC_HPC_LA14_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA14_P]
+#set_property PACKAGE_PIN A28 [get_ports FMC_HPC_LA14_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA14_N]
+#set_property PACKAGE_PIN A25 [get_ports FMC_HPC_LA13_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA13_P]
+#set_property PACKAGE_PIN A26 [get_ports FMC_HPC_LA13_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA13_N]
+#set_property PACKAGE_PIN D26 [get_ports FMC_HPC_LA01_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA01_CC_P]
+#set_property PACKAGE_PIN C26 [get_ports FMC_HPC_LA01_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA01_CC_N]
+#set_property PACKAGE_PIN C25 [get_ports FMC_HPC_LA00_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA00_CC_P]
+#set_property PACKAGE_PIN B25 [get_ports FMC_HPC_LA00_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA00_CC_N]
+#set_property PACKAGE_PIN D27 [get_ports FMC_HPC_CLK0_M2C_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK0_M2C_P]
+#set_property PACKAGE_PIN C27 [get_ports FMC_HPC_CLK0_M2C_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK0_M2C_N]
+#set_property PACKAGE_PIN E28 [get_ports FMC_HPC_LA07_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA07_P]
+#set_property PACKAGE_PIN D28 [get_ports FMC_HPC_LA07_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA07_N]
+#set_property PACKAGE_PIN C29 [get_ports FMC_HPC_LA12_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA12_P]
+#set_property PACKAGE_PIN B29 [get_ports FMC_HPC_LA12_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA12_N]
+#set_property PACKAGE_PIN D29 [get_ports FMC_HPC_LA10_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA10_P]
+#set_property PACKAGE_PIN C30 [get_ports FMC_HPC_LA10_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA10_N]
+#set_property PACKAGE_PIN B30 [get_ports FMC_HPC_LA09_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA09_P]
+#set_property PACKAGE_PIN A30 [get_ports FMC_HPC_LA09_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA09_N]
+#set_property PACKAGE_PIN E29 [get_ports FMC_HPC_LA08_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA08_P]
+#set_property PACKAGE_PIN E30 [get_ports FMC_HPC_LA08_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA08_N]
+#set_property PACKAGE_PIN H24 [get_ports FMC_HPC_LA02_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA02_P]
+#set_property PACKAGE_PIN H25 [get_ports FMC_HPC_LA02_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA02_N]
+#set_property PACKAGE_PIN G28 [get_ports FMC_HPC_LA04_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA04_P]
+#set_property PACKAGE_PIN F28 [get_ports FMC_HPC_LA04_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA04_N]
+#set_property PACKAGE_PIN G27 [get_ports FMC_HPC_LA11_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA11_P]
+#set_property PACKAGE_PIN F27 [get_ports FMC_HPC_LA11_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA11_N]
+#set_property PACKAGE_PIN G29 [get_ports FMC_HPC_LA05_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA05_P]
+#set_property PACKAGE_PIN F30 [get_ports FMC_HPC_LA05_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA05_N]
+#set_property PACKAGE_PIN H26 [get_ports FMC_HPC_LA03_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA03_P]
+#set_property PACKAGE_PIN H27 [get_ports FMC_HPC_LA03_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA03_N]
+#set_property PACKAGE_PIN H30 [get_ports FMC_HPC_LA06_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA06_P]
+#set_property PACKAGE_PIN G30 [get_ports FMC_HPC_LA06_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA06_N]
+#set_property PACKAGE_PIN G25 [get_ports PCIE_PERST_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports PCIE_PERST_LS]
+#set_property PACKAGE_PIN G19 [get_ports GPIO_LED_5_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_5_LS]
+#set_property PACKAGE_PIN K18 [get_ports HDMI_R_CLK]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_CLK]
+#set_property PACKAGE_PIN J18 [get_ports HDMI_R_HSYNC]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_HSYNC]
+#set_property PACKAGE_PIN H20 [get_ports HDMI_R_VSYNC]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_VSYNC]
+#set_property PACKAGE_PIN G20 [get_ports HDMI_SPDIF_OUT_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_SPDIF_OUT_LS]
+#set_property PACKAGE_PIN J17 [get_ports HDMI_R_SPDIF]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_SPDIF]
+#set_property PACKAGE_PIN H17 [get_ports HDMI_R_DE]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_DE]
+#set_property PACKAGE_PIN J19 [get_ports HDMI_R_D12]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D12]
+#set_property PACKAGE_PIN H19 [get_ports HDMI_R_D13]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D13]
+#set_property PACKAGE_PIN L17 [get_ports HDMI_R_D14]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D14]
+#set_property PACKAGE_PIN L18 [get_ports HDMI_R_D15]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D15]
+#set_property PACKAGE_PIN K19 [get_ports HDMI_R_D16]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D16]
+#set_property PACKAGE_PIN K20 [get_ports HDMI_R_D17]
+#set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_D17]
+#set_property PACKAGE_PIN H21 [get_ports FMC_HPC_LA33_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA33_P]
+#set_property PACKAGE_PIN H22 [get_ports FMC_HPC_LA33_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA33_N]
+#set_property PACKAGE_PIN D21 [get_ports FMC_HPC_LA32_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA32_P]
+#set_property PACKAGE_PIN C21 [get_ports FMC_HPC_LA32_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA32_N]
+#set_property PACKAGE_PIN G22 [get_ports FMC_HPC_LA31_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA31_P]
+#set_property PACKAGE_PIN F22 [get_ports FMC_HPC_LA31_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA31_N]
+#set_property PACKAGE_PIN D22 [get_ports FMC_HPC_LA30_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA30_P]
+#set_property PACKAGE_PIN C22 [get_ports FMC_HPC_LA30_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA30_N]
+#set_property PACKAGE_PIN F21 [get_ports FMC_HPC_LA18_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA18_CC_P]
+#set_property PACKAGE_PIN E21 [get_ports FMC_HPC_LA18_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA18_CC_N]
+#set_property PACKAGE_PIN F20 [get_ports FMC_HPC_LA17_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA17_CC_P]
+#set_property PACKAGE_PIN E20 [get_ports FMC_HPC_LA17_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA17_CC_N]
+#set_property PACKAGE_PIN D17 [get_ports FMC_HPC_CLK1_M2C_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK1_M2C_P]
+#set_property PACKAGE_PIN D18 [get_ports FMC_HPC_CLK1_M2C_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_CLK1_M2C_N]
+#set_property PACKAGE_PIN E19 [get_ports FMC_HPC_LA20_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA20_P]
+#set_property PACKAGE_PIN D19 [get_ports FMC_HPC_LA20_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA20_N]
+#set_property PACKAGE_PIN D16 [get_ports FMC_HPC_LA28_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA28_P]
+#set_property PACKAGE_PIN C16 [get_ports FMC_HPC_LA28_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA28_N]
+#set_property PACKAGE_PIN G18 [get_ports FMC_HPC_LA19_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA19_P]
+#set_property PACKAGE_PIN F18 [get_ports FMC_HPC_LA19_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA19_N]
+#set_property PACKAGE_PIN C17 [get_ports FMC_HPC_LA29_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA29_P]
+#set_property PACKAGE_PIN B17 [get_ports FMC_HPC_LA29_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA29_N]
+#set_property PACKAGE_PIN G17 [get_ports FMC_HPC_LA25_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA25_P]
+#set_property PACKAGE_PIN F17 [get_ports FMC_HPC_LA25_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA25_N]
+#set_property PACKAGE_PIN C20 [get_ports FMC_HPC_LA22_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA22_P]
+#set_property PACKAGE_PIN B20 [get_ports FMC_HPC_LA22_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA22_N]
+#set_property PACKAGE_PIN A16 [get_ports FMC_HPC_LA24_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA24_P]
+#set_property PACKAGE_PIN A17 [get_ports FMC_HPC_LA24_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA24_N]
+#set_property PACKAGE_PIN A20 [get_ports FMC_HPC_LA21_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA21_P]
+#set_property PACKAGE_PIN A21 [get_ports FMC_HPC_LA21_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA21_N]
+#set_property PACKAGE_PIN B18 [get_ports FMC_HPC_LA26_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA26_P]
+#set_property PACKAGE_PIN A18 [get_ports FMC_HPC_LA26_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA26_N]
+#set_property PACKAGE_PIN B22 [get_ports FMC_HPC_LA23_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA23_P]
+#set_property PACKAGE_PIN A22 [get_ports FMC_HPC_LA23_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA23_N]
+#set_property PACKAGE_PIN C19 [get_ports FMC_HPC_LA27_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA27_P]
+#set_property PACKAGE_PIN B19 [get_ports FMC_HPC_LA27_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_LA27_N]
+#set_property PACKAGE_PIN E18 [get_ports GPIO_LED_6_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_6_LS]
+set_property PACKAGE_PIN G12 [get_ports GPIO_SW_C]
+set_property IOSTANDARD LVCMOS25 [get_ports GPIO_SW_C]
+#set_property PACKAGE_PIN L16 [get_ports FMC_HPC_HA13_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA13_P]
+#set_property PACKAGE_PIN K16 [get_ports FMC_HPC_HA13_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA13_N]
+#set_property PACKAGE_PIN L15 [get_ports FMC_HPC_HA16_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA16_P]
+#set_property PACKAGE_PIN K15 [get_ports FMC_HPC_HA16_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA16_N]
+#set_property PACKAGE_PIN L12 [get_ports FMC_HPC_HA23_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA23_P]
+#set_property PACKAGE_PIN L13 [get_ports FMC_HPC_HA23_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA23_N]
+#set_property PACKAGE_PIN K13 [get_ports FMC_HPC_HA20_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA20_P]
+#set_property PACKAGE_PIN J13 [get_ports FMC_HPC_HA20_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA20_N]
+#set_property PACKAGE_PIN K14 [get_ports FMC_HPC_HA18_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA18_P]
+#set_property PACKAGE_PIN J14 [get_ports FMC_HPC_HA18_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA18_N]
+#set_property PACKAGE_PIN L11 [get_ports FMC_HPC_HA22_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA22_P]
+#set_property PACKAGE_PIN K11 [get_ports FMC_HPC_HA22_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA22_N]
+#set_property PACKAGE_PIN H15 [get_ports FMC_HPC_HA15_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA15_P]
+#set_property PACKAGE_PIN G15 [get_ports FMC_HPC_HA15_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA15_N]
+#set_property PACKAGE_PIN J11 [get_ports FMC_HPC_HA21_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA21_P]
+#set_property PACKAGE_PIN J12 [get_ports FMC_HPC_HA21_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA21_N]
+#set_property PACKAGE_PIN J16 [get_ports FMC_HPC_HA14_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA14_P]
+#set_property PACKAGE_PIN H16 [get_ports FMC_HPC_HA14_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA14_N]
+#set_property PACKAGE_PIN H11 [get_ports FMC_HPC_HA19_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA19_P]
+#set_property PACKAGE_PIN H12 [get_ports FMC_HPC_HA19_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA19_N]
+#set_property PACKAGE_PIN H14 [get_ports FMC_HPC_HA01_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA01_CC_P]
+#set_property PACKAGE_PIN G14 [get_ports FMC_HPC_HA01_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA01_CC_N]
+#set_property PACKAGE_PIN G13 [get_ports FMC_HPC_HA17_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA17_CC_P]
+#set_property PACKAGE_PIN F13 [get_ports FMC_HPC_HA17_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA17_CC_N]
+#set_property PACKAGE_PIN D12 [get_ports FMC_HPC_HA00_CC_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA00_CC_P]
+#set_property PACKAGE_PIN D13 [get_ports FMC_HPC_HA00_CC_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA00_CC_N]
+#set_property PACKAGE_PIN F12 [get_ports FMC_HPC_HA09_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA09_P]
+#set_property PACKAGE_PIN E13 [get_ports FMC_HPC_HA09_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA09_N]
+#set_property PACKAGE_PIN C12 [get_ports FMC_HPC_HA03_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA03_P]
+#set_property PACKAGE_PIN B12 [get_ports FMC_HPC_HA03_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA03_N]
+#set_property PACKAGE_PIN F11 [get_ports FMC_HPC_HA04_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA04_P]
+#set_property PACKAGE_PIN E11 [get_ports FMC_HPC_HA04_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA04_N]
+#set_property PACKAGE_PIN A11 [get_ports FMC_HPC_HA10_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA10_P]
+#set_property PACKAGE_PIN A12 [get_ports FMC_HPC_HA10_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA10_N]
+#set_property PACKAGE_PIN D11 [get_ports FMC_HPC_HA02_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA02_P]
+#set_property PACKAGE_PIN C11 [get_ports FMC_HPC_HA02_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA02_N]
+#set_property PACKAGE_PIN F15 [get_ports FMC_HPC_HA05_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA05_P]
+#set_property PACKAGE_PIN E16 [get_ports FMC_HPC_HA05_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA05_N]
+#set_property PACKAGE_PIN E14 [get_ports FMC_HPC_HA08_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA08_P]
+#set_property PACKAGE_PIN E15 [get_ports FMC_HPC_HA08_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA08_N]
+#set_property PACKAGE_PIN D14 [get_ports FMC_HPC_HA06_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA06_P]
+#set_property PACKAGE_PIN C14 [get_ports FMC_HPC_HA06_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA06_N]
+#set_property PACKAGE_PIN B13 [get_ports FMC_HPC_HA11_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA11_P]
+#set_property PACKAGE_PIN A13 [get_ports FMC_HPC_HA11_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA11_N]
+#set_property PACKAGE_PIN C15 [get_ports FMC_HPC_HA12_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA12_P]
+#set_property PACKAGE_PIN B15 [get_ports FMC_HPC_HA12_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA12_N]
+#set_property PACKAGE_PIN B14 [get_ports FMC_HPC_HA07_P]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA07_P]
+#set_property PACKAGE_PIN A15 [get_ports FMC_HPC_HA07_N]
+#set_property IOSTANDARD LVCMOS25 [get_ports FMC_HPC_HA07_N]
+#set_property PACKAGE_PIN F16 [get_ports GPIO_LED_7_LS]
+#set_property IOSTANDARD LVCMOS25 [get_ports GPIO_LED_7_LS]
+#set_property PACKAGE_PIN Y14 [get_ports PMBUS_DATA_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_DATA_LS]
+#set_property PACKAGE_PIN AK16 [get_ports DDR3_D24]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D24]
+#set_property PACKAGE_PIN AK15 [get_ports DDR3_D31]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D31]
+#set_property PACKAGE_PIN AG15 [get_ports DDR3_D26]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D26]
+#set_property PACKAGE_PIN AH15 [get_ports DDR3_D30]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D30]
+#set_property PACKAGE_PIN AH16 [get_ports DDR3_DQS3_P]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS3_P]
+#set_property PACKAGE_PIN AJ16 [get_ports DDR3_DQS3_N]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS3_N]
+#set_property PACKAGE_PIN AF15 [get_ports DDR3_D27]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D27]
+#set_property PACKAGE_PIN AG14 [get_ports DDR3_D29]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D29]
+#set_property PACKAGE_PIN AH17 [get_ports DDR3_D28]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D28]
+#set_property PACKAGE_PIN AJ17 [get_ports DDR3_D25]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D25]
+#set_property PACKAGE_PIN AE16 [get_ports DDR3_DM3]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM3]
+#set_property PACKAGE_PIN AF16 [get_ports VTTVREF]
+#set_property PACKAGE_PIN AJ19 [get_ports DDR3_D21]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D21]
+#set_property PACKAGE_PIN AK19 [get_ports DDR3_D17]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D17]
+#set_property PACKAGE_PIN AG19 [get_ports DDR3_D16]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D16]
+#set_property PACKAGE_PIN AH19 [get_ports DDR3_D20]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D20]
+#set_property PACKAGE_PIN AJ18 [get_ports DDR3_DQS2_P]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS2_P]
+#set_property PACKAGE_PIN AK18 [get_ports DDR3_DQS2_N]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS2_N]
+#set_property PACKAGE_PIN AD19 [get_ports DDR3_D23]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D23]
+#set_property PACKAGE_PIN AE19 [get_ports DDR3_D22]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D22]
+#set_property PACKAGE_PIN AF18 [get_ports DDR3_D19]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D19]
+#set_property PACKAGE_PIN AG18 [get_ports DDR3_D18]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D18]
+#set_property PACKAGE_PIN AF17 [get_ports DDR3_DM2]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM2]
+#set_property PACKAGE_PIN AG17 [get_ports PMBUS_CLK_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_CLK_LS]
+#set_property PACKAGE_PIN AD18 [get_ports DDR3_D15]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D15]
+#set_property PACKAGE_PIN AE18 [get_ports DDR3_D14]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D14]
+#set_property PACKAGE_PIN AD17 [get_ports DDR3_D11]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D11]
+#set_property PACKAGE_PIN AD16 [get_ports DDR3_D9]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D9]
+#set_property PACKAGE_PIN Y19 [get_ports DDR3_DQS1_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_P]
+#set_property PACKAGE_PIN Y18 [get_ports DDR3_DQS1_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_N]
+#set_property PACKAGE_PIN AA18 [get_ports DDR3_D12]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D12]
+#set_property PACKAGE_PIN AB18 [get_ports DDR3_D13]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D13]
+#set_property PACKAGE_PIN AB19 [get_ports DDR3_D8]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D8]
+#set_property PACKAGE_PIN AC19 [get_ports DDR3_D10]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D10]
+#set_property PACKAGE_PIN AB17 [get_ports DDR3_DM1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM1]
+#set_property PACKAGE_PIN AC17 [get_ports 7N700]
+#set_property PACKAGE_PIN AE15 [get_ports DDR3_D6]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D6]
+#set_property PACKAGE_PIN AE14 [get_ports VTTVREF]
+#set_property PACKAGE_PIN AA15 [get_ports DDR3_D0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D0]
+#set_property PACKAGE_PIN AB15 [get_ports DDR3_D5]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D5]
+#set_property PACKAGE_PIN AC16 [get_ports DDR3_DQS0_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_P]
+#set_property PACKAGE_PIN AC15 [get_ports DDR3_DQS0_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_N]
+#set_property PACKAGE_PIN AC14 [get_ports DDR3_D2]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D2]
+#set_property PACKAGE_PIN AD14 [get_ports DDR3_D3]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D3]
+#set_property PACKAGE_PIN AA17 [get_ports DDR3_D4]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D4]
+#set_property PACKAGE_PIN AA16 [get_ports DDR3_D1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D1]
+#set_property PACKAGE_PIN Y16 [get_ports DDR3_DM0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM0]
+#set_property PACKAGE_PIN Y15 [get_ports DDR3_D7]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D7]
+#set_property PACKAGE_PIN AB14 [get_ports PMBUS_ALERT_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_ALERT_LS]
+#set_property PACKAGE_PIN Y13 [get_ports VRN_33]
+#set_property IOSTANDARD SSTL15 [get_ports VRN_33]
+set_property PACKAGE_PIN AA12 [get_ports GPIO_SW_N]
+set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_N]
+set_property PACKAGE_PIN AB12 [get_ports GPIO_SW_S]
+set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_S]
+#set_property PACKAGE_PIN AA8 [get_ports GPIO_LED_1_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_1_LS]
+#set_property PACKAGE_PIN AB8 [get_ports GPIO_LED_0_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0_LS]
+#set_property PACKAGE_PIN AB9 [get_ports GPIO_LED_3_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_3_LS]
+#set_property PACKAGE_PIN AC9 [get_ports GPIO_LED_2_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_2_LS]
+#set_property PACKAGE_PIN Y11 [get_ports LCD_RS_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_RS_LS]
+#set_property PACKAGE_PIN Y10 [get_ports LCD_DB7_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB7_LS]
+#set_property PACKAGE_PIN AA11 [get_ports LCD_DB6_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB6_LS]
+#set_property PACKAGE_PIN AA10 [get_ports LCD_DB5_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB5_LS]
+#set_property PACKAGE_PIN AA13 [get_ports LCD_DB4_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_DB4_LS]
+#set_property PACKAGE_PIN AB13 [get_ports LCD_RW_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_RW_LS]
+#set_property PACKAGE_PIN AB10 [get_ports LCD_E_LS]
+#set_property IOSTANDARD LVCMOS15 [get_ports LCD_E_LS]
+#set_property PACKAGE_PIN AC10 [get_ports DDR3_ODT1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
+#set_property PACKAGE_PIN AD8 [get_ports DDR3_ODT0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0]
+#set_property PACKAGE_PIN AE8 [get_ports DDR3_S1_B]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B]
+#set_property PACKAGE_PIN AC12 [get_ports DDR3_S0_B]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B]
+#set_property PACKAGE_PIN AC11 [get_ports DDR3_CAS_B]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B]
+#set_property PACKAGE_PIN AD9 [get_ports DDR3_RAS_B]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B]
+#set_property PACKAGE_PIN AE9 [get_ports DDR3_WE_B]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_WE_B]
+#set_property PACKAGE_PIN AE11 [get_ports DDR3_CLK1_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_P]
+#set_property PACKAGE_PIN AF11 [get_ports DDR3_CLK1_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_N]
+set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
+set_property PACKAGE_PIN AD11 [get_ports SYSCLK_N]
+set_property PACKAGE_PIN AD12 [get_ports SYSCLK_P]
+set_property IOSTANDARD LVDS [get_ports SYSCLK_N]
+#set_property PACKAGE_PIN AG10 [get_ports DDR3_CLK0_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_P]
+#set_property PACKAGE_PIN AH10 [get_ports DDR3_CLK0_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_N]
+#set_property PACKAGE_PIN AE10 [get_ports DDR3_CKE1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1]
+#set_property PACKAGE_PIN AF10 [get_ports DDR3_CKE0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE0]
+#set_property PACKAGE_PIN AJ9 [get_ports DDR3_TEMP_EVENT]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_TEMP_EVENT]
+#set_property PACKAGE_PIN AK9 [get_ports DDR3_BA2]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]
+#set_property PACKAGE_PIN AG9 [get_ports DDR3_BA1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1]
+#set_property PACKAGE_PIN AH9 [get_ports DDR3_BA0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0]
+#set_property PACKAGE_PIN AK11 [get_ports DDR3_A15]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]
+#set_property PACKAGE_PIN AK10 [get_ports DDR3_A14]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A14]
+#set_property PACKAGE_PIN AH11 [get_ports DDR3_A13]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]
+#set_property PACKAGE_PIN AJ11 [get_ports DDR3_A12]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A12]
+#set_property PACKAGE_PIN AE13 [get_ports DDR3_A11]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
+#set_property PACKAGE_PIN AF13 [get_ports DDR3_A10]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
+#set_property PACKAGE_PIN AK14 [get_ports DDR3_A9]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A9]
+#set_property PACKAGE_PIN AK13 [get_ports DDR3_A8]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A8]
+#set_property PACKAGE_PIN AH14 [get_ports DDR3_A7]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A7]
+#set_property PACKAGE_PIN AJ14 [get_ports DDR3_A6]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A6]
+#set_property PACKAGE_PIN AJ13 [get_ports DDR3_A5]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A5]
+#set_property PACKAGE_PIN AJ12 [get_ports DDR3_A4]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A4]
+#set_property PACKAGE_PIN AF12 [get_ports DDR3_A3]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A3]
+#set_property PACKAGE_PIN AG12 [get_ports DDR3_A2]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A2]
+#set_property PACKAGE_PIN AG13 [get_ports DDR3_A1]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A1]
+#set_property PACKAGE_PIN AH12 [get_ports DDR3_A0]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_A0]
+#set_property PACKAGE_PIN AD13 [get_ports VRP_33]
+set_property PACKAGE_PIN AC6 [get_ports GPIO_SW_W]
+set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_W]
+#set_property PACKAGE_PIN AD4 [get_ports DDR3_D63]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
+#set_property PACKAGE_PIN AD3 [get_ports DDR3_D57]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
+#set_property PACKAGE_PIN AC2 [get_ports DDR3_D62]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
+#set_property PACKAGE_PIN AC1 [get_ports DDR3_D56]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
+#set_property PACKAGE_PIN AD2 [get_ports DDR3_DQS7_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]
+#set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS7_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N]
+#set_property PACKAGE_PIN AC5 [get_ports DDR3_D59]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
+#set_property PACKAGE_PIN AC4 [get_ports DDR3_D58]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
+#set_property PACKAGE_PIN AD6 [get_ports DDR3_D61]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
+#set_property PACKAGE_PIN AE6 [get_ports DDR3_D60]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
+#set_property PACKAGE_PIN AC7 [get_ports DDR3_DM7]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
+#set_property PACKAGE_PIN AD7 [get_ports VTTVREF]
+#set_property PACKAGE_PIN AF3 [get_ports DDR3_D52]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D52]
+#set_property PACKAGE_PIN AF2 [get_ports DDR3_D49]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D49]
+#set_property PACKAGE_PIN AE1 [get_ports DDR3_D54]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D54]
+#set_property PACKAGE_PIN AF1 [get_ports DDR3_D48]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D48]
+#set_property PACKAGE_PIN AG4 [get_ports DDR3_DQS6_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_P]
+#set_property PACKAGE_PIN AG3 [get_ports DDR3_DQS6_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_N]
+#set_property PACKAGE_PIN AE4 [get_ports DDR3_D50]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D50]
+#set_property PACKAGE_PIN AE3 [get_ports DDR3_D51]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D51]
+#set_property PACKAGE_PIN AE5 [get_ports DDR3_D55]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D55]
+#set_property PACKAGE_PIN AF5 [get_ports DDR3_D53]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D53]
+#set_property PACKAGE_PIN AF6 [get_ports DDR3_DM6]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM6]
+set_property PACKAGE_PIN AG5 [get_ports GPIO_SW_E]
+set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_E]
+#set_property PACKAGE_PIN AH4 [get_ports DDR3_D44]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D44]
+#set_property PACKAGE_PIN AJ4 [get_ports DDR3_D45]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D45]
+#set_property PACKAGE_PIN AH6 [get_ports DDR3_D41]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D41]
+#set_property PACKAGE_PIN AH5 [get_ports DDR3_D40]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D40]
+#set_property PACKAGE_PIN AG2 [get_ports DDR3_DQS5_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_P]
+#set_property PACKAGE_PIN AH1 [get_ports DDR3_DQS5_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_N]
+#set_property PACKAGE_PIN AH2 [get_ports DDR3_D43]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D43]
+#set_property PACKAGE_PIN AJ2 [get_ports DDR3_D42]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D42]
+#set_property PACKAGE_PIN AJ1 [get_ports DDR3_D47]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D47]
+#set_property PACKAGE_PIN AK1 [get_ports DDR3_D46]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D46]
+#set_property PACKAGE_PIN AJ3 [get_ports DDR3_DM5]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM5]
+#set_property PACKAGE_PIN AK3 [get_ports DDR3_RESET_B]
+#set_property IOSTANDARD LVCMOS15 [get_ports DDR3_RESET_B]
+#set_property PACKAGE_PIN AF8 [get_ports DDR3_D36]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D36]
+#set_property PACKAGE_PIN AG8 [get_ports VTTVREF]
+#set_property PACKAGE_PIN AF7 [get_ports DDR3_D35]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D35]
+#set_property PACKAGE_PIN AG7 [get_ports DDR3_D34]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D34]
+#set_property PACKAGE_PIN AH7 [get_ports DDR3_DQS4_P]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_P]
+#set_property PACKAGE_PIN AJ7 [get_ports DDR3_DQS4_N]
+#set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N]
+#set_property PACKAGE_PIN AJ6 [get_ports DDR3_D39]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D39]
+#set_property PACKAGE_PIN AK6 [get_ports DDR3_D33]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D33]
+#set_property PACKAGE_PIN AJ8 [get_ports DDR3_D38]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D38]
+#set_property PACKAGE_PIN AK8 [get_ports DDR3_D32]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D32]
+#set_property PACKAGE_PIN AK5 [get_ports DDR3_DM4]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_DM4]
+#set_property PACKAGE_PIN AK4 [get_ports DDR3_D37]
+#set_property IOSTANDARD SSTL15 [get_ports DDR3_D37]
+#set_property PACKAGE_PIN AB7 [get_ports CPU_RESET]
+#set_property IOSTANDARD LVCMOS15 [get_ports CPU_RESET]
+#set_property PACKAGE_PIN T2 [get_ports PCIE_TX4_P]
+#set_property PACKAGE_PIN V6 [get_ports PCIE_RX4_P]
+#set_property PACKAGE_PIN T1 [get_ports PCIE_TX4_N]
+#set_property PACKAGE_PIN V5 [get_ports PCIE_RX4_N]
+#set_property PACKAGE_PIN U4 [get_ports PCIE_TX5_P]
+#set_property PACKAGE_PIN W4 [get_ports PCIE_RX5_P]
+#set_property PACKAGE_PIN U3 [get_ports PCIE_TX5_N]
+#set_property PACKAGE_PIN R8 [get_ports 9N302]
+#set_property PACKAGE_PIN W3 [get_ports PCIE_RX5_N]
+#set_property PACKAGE_PIN R7 [get_ports 9N301]
+#set_property PACKAGE_PIN W8 [get_ports 9N173]
+#set_property PACKAGE_PIN U7 [get_ports PCIE_CLK_QO_N]
+#set_property PACKAGE_PIN U8 [get_ports PCIE_CLK_QO_P]
+#set_property PACKAGE_PIN V2 [get_ports PCIE_TX6_P]
+#set_property PACKAGE_PIN Y6 [get_ports PCIE_RX6_P]
+#set_property PACKAGE_PIN V1 [get_ports PCIE_TX6_N]
+#set_property PACKAGE_PIN Y5 [get_ports PCIE_RX6_N]
+#set_property PACKAGE_PIN Y2 [get_ports PCIE_TX7_P]
+#set_property PACKAGE_PIN AA4 [get_ports PCIE_RX7_P]
+#set_property PACKAGE_PIN Y1 [get_ports PCIE_TX7_N]
+#set_property PACKAGE_PIN AA3 [get_ports PCIE_RX7_N]
+#set_property PACKAGE_PIN L4 [get_ports PCIE_TX0_P]
+#set_property PACKAGE_PIN M6 [get_ports PCIE_RX0_P]
+#set_property PACKAGE_PIN L3 [get_ports PCIE_TX0_N]
+#set_property PACKAGE_PIN M5 [get_ports PCIE_RX0_N]
+#set_property PACKAGE_PIN M2 [get_ports PCIE_TX1_P]
+#set_property PACKAGE_PIN P6 [get_ports PCIE_RX1_P]
+#set_property PACKAGE_PIN M1 [get_ports PCIE_TX1_N]
+#set_property PACKAGE_PIN L8 [get_ports SI5326_OUT_C_P]
+#set_property PACKAGE_PIN P5 [get_ports PCIE_RX1_N]
+#set_property PACKAGE_PIN L7 [get_ports SI5326_OUT_C_N]
+#set_property PACKAGE_PIN N7 [get_ports FMC_LPC_GBTCLK0_M2C_C_N]
+#set_property PACKAGE_PIN N8 [get_ports FMC_LPC_GBTCLK0_M2C_C_P]
+#set_property PACKAGE_PIN N4 [get_ports PCIE_TX2_P]
+#set_property PACKAGE_PIN R4 [get_ports PCIE_RX2_P]
+#set_property PACKAGE_PIN N3 [get_ports PCIE_TX2_N]
+#set_property PACKAGE_PIN R3 [get_ports PCIE_RX2_N]
+#set_property PACKAGE_PIN P2 [get_ports PCIE_TX3_P]
+#set_property PACKAGE_PIN T6 [get_ports PCIE_RX3_P]
+#set_property PACKAGE_PIN P1 [get_ports PCIE_TX3_N]
+#set_property PACKAGE_PIN T5 [get_ports PCIE_RX3_N]
+#set_property PACKAGE_PIN F2 [get_ports FMC_LPC_DP0_C2M_P]
+#set_property PACKAGE_PIN F6 [get_ports FMC_LPC_DP0_M2C_P]
+#set_property PACKAGE_PIN F1 [get_ports FMC_LPC_DP0_C2M_N]
+#set_property PACKAGE_PIN F5 [get_ports FMC_LPC_DP0_M2C_N]
+set_property PACKAGE_PIN G3 [get_ports SFP_RX_N]
+set_property PACKAGE_PIN H2 [get_ports SFP_TX_P]
+set_property PACKAGE_PIN H1 [get_ports SFP_TX_N]
+set_property PACKAGE_PIN G4 [get_ports SFP_RX_P]
+#set_property IOSTANDARD LVDS_25 [get_ports SGMIICLK_Q0_P]
+set_property PACKAGE_PIN G7 [get_ports SGMIICLK_Q0_N]
+set_property PACKAGE_PIN G8 [get_ports SGMIICLK_Q0_P]
+set_property PACKAGE_PIN J7 [get_ports SMA_MGT_REFCLK_N]
+set_property PACKAGE_PIN J8 [get_ports SMA_MGT_REFCLK_P]
+#set_property PACKAGE_PIN J4 [get_ports SGMII_TX_P]
+#set_property PACKAGE_PIN H6 [get_ports SGMII_RX_P]
+#set_property PACKAGE_PIN J3 [get_ports SGMII_TX_N]
+#set_property PACKAGE_PIN H5 [get_ports SGMII_RX_N]
+#set_property PACKAGE_PIN K2 [get_ports SMA_MGT_TX_P]
+#set_property PACKAGE_PIN K6 [get_ports SMA_MGT_RX_P]
+#set_property PACKAGE_PIN K1 [get_ports SMA_MGT_TX_N]
+#set_property PACKAGE_PIN K5 [get_ports SMA_MGT_RX_N]
+#set_property PACKAGE_PIN A4 [get_ports FMC_HPC_DP3_C2M_P]
+#set_property PACKAGE_PIN A8 [get_ports FMC_HPC_DP3_M2C_P]
+#set_property PACKAGE_PIN A3 [get_ports FMC_HPC_DP3_C2M_N]
+#set_property PACKAGE_PIN A7 [get_ports FMC_HPC_DP3_M2C_N]
+#set_property PACKAGE_PIN B2 [get_ports FMC_HPC_DP2_C2M_P]
+#set_property PACKAGE_PIN B6 [get_ports FMC_HPC_DP2_M2C_P]
+#set_property PACKAGE_PIN B1 [get_ports FMC_HPC_DP2_C2M_N]
+#set_property PACKAGE_PIN C8 [get_ports FMC_HPC_GBTCLK0_M2C_C_P]
+#set_property PACKAGE_PIN B5 [get_ports FMC_HPC_DP2_M2C_N]
+#set_property PACKAGE_PIN C7 [get_ports FMC_HPC_GBTCLK0_M2C_C_N]
+#set_property PACKAGE_PIN E7 [get_ports FMC_HPC_GBTCLK1_M2C_C_N]
+#set_property PACKAGE_PIN E8 [get_ports FMC_HPC_GBTCLK1_M2C_C_P]
+#set_property PACKAGE_PIN C4 [get_ports FMC_HPC_DP1_C2M_P]
+#set_property PACKAGE_PIN D6 [get_ports FMC_HPC_DP1_M2C_P]
+#set_property PACKAGE_PIN C3 [get_ports FMC_HPC_DP1_C2M_N]
+#set_property PACKAGE_PIN D5 [get_ports FMC_HPC_DP1_M2C_N]
+#set_property PACKAGE_PIN D2 [get_ports FMC_HPC_DP0_C2M_P]
+#set_property PACKAGE_PIN E4 [get_ports FMC_HPC_DP0_M2C_P]
+#set_property PACKAGE_PIN D1 [get_ports FMC_HPC_DP0_C2M_N]
+#set_property PACKAGE_PIN E3 [get_ports FMC_HPC_DP0_M2C_N]
+
+set_property PACKAGE_PIN F20 [get_ports {fmc_sfp_tx_disable[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_disable[0]}]
+set_property PACKAGE_PIN A26 [get_ports {fmc_sfp_tx_disable[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_disable[1]}]
+set_property PACKAGE_PIN D29 [get_ports {fmc_sfp_tx_disable[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_disable[2]}]
+set_property PACKAGE_PIN G30 [get_ports {fmc_sfp_tx_disable[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_disable[3]}]
+
+set_property PACKAGE_PIN F18 [get_ports {fmc_led[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_led[0]}]
+set_property PACKAGE_PIN G18 [get_ports {fmc_led[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_led[1]}]
+set_property PACKAGE_PIN E21 [get_ports {fmc_led[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_led[2]}]
+set_property PACKAGE_PIN F21 [get_ports {fmc_led[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_led[3]}]
+
+set_property PACKAGE_PIN A28 [get_ports {fmc_sfp_los[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_los[0]}]
+set_property PACKAGE_PIN G27 [get_ports {fmc_sfp_los[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_los[1]}]
+set_property PACKAGE_PIN D28 [get_ports {fmc_sfp_los[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_los[2]}]
+set_property PACKAGE_PIN G28 [get_ports {fmc_sfp_los[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_los[3]}]
+
+set_property PACKAGE_PIN E20 [get_ports {fmc_sfp_tx_fault[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_fault[0]}]
+set_property PACKAGE_PIN B28 [get_ports {fmc_sfp_tx_fault[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_fault[1]}]
+set_property PACKAGE_PIN C30 [get_ports {fmc_sfp_tx_fault[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_fault[2]}]
+set_property PACKAGE_PIN E28 [get_ports {fmc_sfp_tx_fault[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_tx_fault[3]}]
+
+set_property PACKAGE_PIN C24 [get_ports {fmc_sfp_rate_sel[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_rate_sel[0]}]
+set_property PACKAGE_PIN F27 [get_ports {fmc_sfp_rate_sel[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_rate_sel[1]}]
+set_property PACKAGE_PIN E29 [get_ports {fmc_sfp_rate_sel[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_rate_sel[2]}]
+set_property PACKAGE_PIN F28 [get_ports {fmc_sfp_rate_sel[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_rate_sel[3]}]
+
+set_property PACKAGE_PIN B24 [get_ports {fmc_sfp_mod_def0[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_mod_def0[0]}]
+set_property PACKAGE_PIN C29 [get_ports {fmc_sfp_mod_def0[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_mod_def0[1]}]
+set_property PACKAGE_PIN E30 [get_ports {fmc_sfp_mod_def0[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_mod_def0[2]}]
+set_property PACKAGE_PIN G29 [get_ports {fmc_sfp_mod_def0[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_sfp_mod_def0[3]}]
+
+set_property PACKAGE_PIN H24 [get_ports {fmc_user_switch[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_user_switch[0]}]
+set_property PACKAGE_PIN H25 [get_ports {fmc_user_switch[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_user_switch[1]}]
+set_property PACKAGE_PIN H26 [get_ports {fmc_user_switch[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_user_switch[2]}]
+set_property PACKAGE_PIN H27 [get_ports {fmc_user_switch[3]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc_user_switch[3]}]
+
+set_property PACKAGE_PIN E4 [get_ports X0Y12_RX_P_IPAD]
+set_property PACKAGE_PIN E3 [get_ports X0Y12_RX_N_IPAD]
+set_property PACKAGE_PIN D1 [get_ports X0Y12_TX_N_OPAD]
+set_property PACKAGE_PIN D2 [get_ports X0Y12_TX_P_OPAD]
+set_property PACKAGE_PIN D5 [get_ports X0Y13_RX_N_IPAD]
+set_property PACKAGE_PIN D6 [get_ports X0Y13_RX_P_IPAD]
+set_property PACKAGE_PIN C3 [get_ports X0Y13_TX_N_OPAD]
+set_property PACKAGE_PIN C4 [get_ports X0Y13_TX_P_OPAD]
+set_property PACKAGE_PIN B5 [get_ports X0Y14_RX_N_IPAD]
+set_property PACKAGE_PIN B6 [get_ports X0Y14_RX_P_IPAD]
+set_property PACKAGE_PIN B1 [get_ports X0Y14_TX_N_OPAD]
+set_property PACKAGE_PIN B2 [get_ports X0Y14_TX_P_OPAD]
+set_property PACKAGE_PIN A4 [get_ports X0Y15_TX_P_OPAD]
+set_property PACKAGE_PIN A7 [get_ports X0Y15_RX_N_IPAD]
+set_property PACKAGE_PIN A8 [get_ports X0Y15_RX_P_IPAD]
+set_property PACKAGE_PIN A3 [get_ports X0Y15_TX_N_OPAD]
+
+set_property PACKAGE_PIN C8 [get_ports Q3_CLK0_MGTREFCLK_P_IPAD]
+set_property PACKAGE_PIN C7 [get_ports Q3_CLK0_MGTREFCLK_N_IPAD]
+#set_property PACKAGE_PIN E7 [get_ports Q3_CLK1_MGTREFCLK_N_IPAD]
+#set_property PACKAGE_PIN E8 [get_ports Q3_CLK1_MGTREFCLK_P_IPAD]
+
+
+
diff --git a/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/trb3_kc705_data_concentrator.vhd b/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/trb3_kc705_data_concentrator.vhd
new file mode 100644
index 0000000..8e4c714
--- /dev/null
+++ b/data_concentrator/Xilinx_KC705/DataConcentrator_KC705/trb3_kc705_data_concentrator.vhd
@@ -0,0 +1,1821 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.soda_components.all;
+use work.version.all;
+use work.panda_package.all; 
+USE work.CN_package.all;
+
+
+entity trb3_kc705_data_concentrator is
+  port(
+    --Clocks
+
+    SYSCLK_P : in std_logic;  --200MHz
+    SYSCLK_N  : in std_logic;  --200MHz
+
+    --Serdes
+    SGMIICLK_Q0_P    : in std_logic; -- reverence clock for onboard sfp
+    SGMIICLK_Q0_N    : in std_logic;
+    SFP_TX_P         : out std_logic;
+    SFP_TX_N         : out std_logic;
+    SFP_RX_P         : in std_logic;
+    SFP_RX_N         : in std_logic;
+    SFP_TX_DISABLE   : out std_logic;
+    SFP_LOS_LS       : in std_logic;
+
+	--Quad SFP on FMC module
+	fmc_led                    : out std_logic_vector(3 downto 0);
+	fmc_user_switch            : inout std_logic_vector(3 downto 0);
+	fmc_sfp_los                : in std_logic_vector(3 downto 0);
+	fmc_sfp_tx_fault           : in std_logic_vector(3 downto 0);
+	fmc_sfp_tx_disable         : out std_logic_vector(3 downto 0);
+	fmc_sfp_rate_sel           : out std_logic_vector(3 downto 0);
+	fmc_sfp_mod_def0           : in std_logic_vector(3 downto 0); -- or out???
+	X0Y12_RX_P_IPAD            : in std_logic;
+	X0Y12_RX_N_IPAD            : in std_logic;
+	X0Y13_RX_P_IPAD            : in std_logic;
+	X0Y13_RX_N_IPAD            : in std_logic;
+	X0Y14_RX_P_IPAD            : in std_logic;
+	X0Y14_RX_N_IPAD            : in std_logic;
+	X0Y15_RX_P_IPAD            : in std_logic;
+	X0Y15_RX_N_IPAD            : in std_logic;
+	Q3_CLK0_MGTREFCLK_P_IPAD   : in std_logic;
+	Q3_CLK0_MGTREFCLK_N_IPAD   : in std_logic;
+--	Q3_CLK1_MGTREFCLK_P_IPAD   : in std_logic;
+--	Q3_CLK1_MGTREFCLK_N_IPAD   : in std_logic;
+	X0Y12_TX_P_OPAD            : out std_logic;
+	X0Y12_TX_N_OPAD            : out std_logic;
+	X0Y13_TX_P_OPAD            : out std_logic;
+	X0Y13_TX_N_OPAD            : out std_logic;
+	X0Y14_TX_P_OPAD            : out std_logic;
+	X0Y14_TX_N_OPAD            : out std_logic;
+	X0Y15_TX_P_OPAD            : out std_logic;
+	X0Y15_TX_N_OPAD            : out std_logic;
+	SMA_MGT_REFCLK_P           : in std_logic; -- sma reference clock input for MGTREFCLK1P_117
+	SMA_MGT_REFCLK_N           : in std_logic; -- sma reference clock input for MGTREFCLK1N_117
+	USER_SMA_CLOCK_P           : out std_logic; -- sma clock output
+	USER_SMA_CLOCK_N           : out std_logic; -- sma clock output
+	REC_CLOCK_C_P              : out std_logic; -- clock output to jitter cleaner
+	REC_CLOCK_C_N              : out std_logic; -- clock output to jitter cleaner
+	USER_SMA_GPIO_P            : out std_logic;
+	USER_SMA_GPIO_N            : out std_logic;
+	
+	GPIO_SW_N                  : in std_logic;
+	GPIO_SW_S                  : in std_logic;
+	GPIO_SW_C                  : in std_logic;
+	GPIO_SW_W                  : in std_logic;
+	GPIO_SW_E                  : in std_logic;
+    XADC_GPIO_0      : out std_logic;  
+    XADC_GPIO_1      : out std_logic;  
+    XADC_GPIO_2      : out std_logic;  
+    XADC_GPIO_3      : out std_logic
+    );
+end entity;
+
+architecture trb3_kc705_data_concentrator of trb3_kc705_data_concentrator is
+
+  constant EXTERNAL_SODA           : boolean := true;
+  
+  
+
+component pll_in200_out200_160_100_80 is
+port
+ (-- Clock in ports
+  clk_in1_p         : in     std_logic;
+  clk_in1_n         : in     std_logic;
+  -- Clock out ports
+  clk_out1          : out    std_logic;
+  clk_out2          : out    std_logic;
+  clk_out3          : out    std_logic;
+  clk_out4          : out    std_logic;
+  -- Status and control signals
+  reset             : in     std_logic;
+  locked            : out    std_logic
+ );
+end component;
+
+component pll_in200_out200 is
+port
+ (-- Clock in ports
+  clk_in1           : in     std_logic;
+  -- Clock out ports
+  clk_out1          : out    std_logic;
+  -- Status and control signals
+  reset             : in     std_logic;
+  locked            : out    std_logic
+ );
+end component;
+
+component jittercleaner_200M is
+port
+ (
+  clk_in           : in     std_logic;
+  clk_out          : out    std_logic;
+  reset            : in     std_logic;
+  locked           : out    std_logic
+ );
+end component;
+
+component trb_net16_med_sync_gtx2_kintex7_sfp is
+  port(
+    CLK                : in  std_logic; -- SerDes clock
+    SYSCLK             : in  std_logic; -- fabric clock
+    SODA_clock         : in  std_logic; --//try
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    CLK_EN             : in  std_logic;
+	disable_GTX_reset  : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic;
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic;
+    MED_READ_IN        : in  std_logic;
+    REFCLK2CORE_OUT    : out std_logic;
+    CLK_RX_HALF_OUT    : out std_logic;
+    CLK_RX_FULL_OUT    : out std_logic;
+    --SFP Connection
+	SODA_RXD_P_IN      : in  std_logic;
+    SODA_RXD_N_IN      : in  std_logic;
+    SODA_TXD_P_OUT     : out std_logic;
+    SODA_TXD_N_OUT     : out std_logic;
+    SODA_REFCLK_P_IN   : in  std_logic;
+    SODA_REFCLK_N_IN   : in  std_logic;
+    SODA_PRSNT_N_IN    : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SODA_LOS_IN        : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SODA_TXDIS_OUT     : out  std_logic; -- SFP disable	
+	SODA_DLM_IN        : in  std_logic;
+	SODA_DLM_WORD_IN   : in  std_logic_vector(7 downto 0);
+	SODA_DLM_OUT       : out  std_logic;
+	SODA_DLM_WORD_OUT  : out  std_logic_vector(7 downto 0);
+    SODA_CLOCK_OUT     : out  std_logic; -- 200MHz
+	SODA_LOCKED_OUT    : out  std_logic;
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0);
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end component;
+
+component GTX_dataoutputwrapper is
+	port ( 
+		sysClk                  : in std_logic;
+		refClk_P                : in std_logic;
+		refClk_N                : in std_logic;
+		clock_out               : out std_logic;
+		clock_rec               : out std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(15 downto 0);
+		kchar_in                : in std_logic_vector(1 downto 0);
+		data_out                : out std_logic_vector(15 downto 0);
+		kchar_out               : out std_logic_vector(1 downto 0);
+		G0_txP                  : out  std_logic;
+		G0_txN                  : out  std_logic;
+		G0_rxP                  : in  std_logic;
+		G0_rxN                  : in  std_logic;
+		G0_LOS                  : in std_logic;
+		tx_locked               : out std_logic;
+		GT0_QPLLOUTCLK_IN       : in std_logic; 
+		GT0_QPLLOUTREFCLK_IN    : in std_logic
+	);
+end component;
+
+component dataconversion_for_serdes16 is
+  port (
+    DATA_CLK        : in  std_logic;
+    CLK             : in  std_logic;
+    RESET           : in  std_logic;
+    TX_READY        : in  std_logic;
+    SFP_MOD0        : in  std_logic;
+    SFP_LOS         : in  std_logic;
+    TX_ALLOWED      : in  std_logic;
+    TX_DATA         : out std_logic_vector(15 downto 0);
+    TX_K            : out std_logic_vector(1 downto 0);
+    DATA_IN_ALLOWED : out std_logic;
+    DATA_IN         : in  std_logic_vector(63 downto 0);
+    DATA_IN_WRITE   : in  std_logic;
+    DATA_IN_FIRST   : in  std_logic;
+    DATA_IN_LAST    : in  std_logic;
+    DATA_IN_ERROR   : in  std_logic);
+end component;
+
+component DC_module_TRB3 is
+	generic (
+		NROFFIBERS              : natural := NROFFIBERS;
+		NROFADCS                : natural := NROFFEEADCS*NROFFEEFPGAS;
+		ADCBITS                 : natural := ADCBITS;
+		ADCCLOCKFREQUENCY       : natural := ADCCLOCKFREQUENCY;
+		MAX_DIVIDERSCALEBITS    : natural := 12;
+		MAX_LUTSIZEBITS         : natural := 9;
+		MAX_LUTSCALEBITS        : natural := 14;
+		MUXINFIFOSIZE           : natural := 10;
+		TRANSFERFIFOSIZE        : natural := 12;
+		CF_FRACTIONBIT          : natural := 11;
+		PANDAPACKETBUFFERBITS   : natural := 13;
+		ADCINDEXSHIFT           : natural := 1;
+		ENERGYSCALINGBITS       : natural := 13;
+		COMBINEPULSESMEMSIZE    : natural := 10;
+		COMBINETIMEDIFFERENCE   : natural := 5000;
+		SYSTEM_ID               : std_logic_vector(15 downto 0) := x"5555";
+		DOPRECLUSTERING         : boolean := DOPRECLUSTERING;  
+		XYPAD_BITSIZE           : natural := 8;
+		CLUSTERBITS             : natural := 8;
+		MAXCLUSTERSBITS         : natural := 5;
+		PARALLELBUILDS          : natural := 2;
+		MINIMUMENERGYBITS       : natural := 8;
+		SKIPSINGLEHITCLUSTERS   : boolean := FALSE
+	);
+	port ( 
+		slowcontrol_clock       : in std_logic;
+		packet_in_clock         : in std_logic;
+		MUX_clock               : in std_logic;
+		packet_out_clock        : in std_logic;
+		SODA_clock              : in std_logic;
+		reset                   : in std_logic;
+
+-- Slave bus
+		BUS_READ_IN             : in   std_logic;
+		BUS_WRITE_IN            : in   std_logic;
+		BUS_BUSY_OUT            : out  std_logic;
+		BUS_ACK_OUT             : out  std_logic;
+		BUS_ADDR_IN             : in   std_logic_vector(1 downto 0);
+		BUS_DATA_IN             : in   std_logic_vector(31 downto 0);
+		BUS_DATA_OUT            : out  std_logic_vector(31 downto 0);
+		
+-- fiber interface signals:
+		fiber_txlocked          : in std_logic_vector(0 to NROFFIBERS-1);
+		fiber_rxlocked          : in std_logic_vector(0 to NROFFIBERS-1);
+		reset_fibers            : out std_logic;
+		fiber_data32write       : out std_logic_vector(0 to NROFFIBERS-1);
+		fiber_data32out         : out array_fiber32bits_type;
+		fiber_data32fifofull    : in std_logic_vector(0 to NROFFIBERS-1);
+		fiber_data32read        : out std_logic_vector(0 to NROFFIBERS-1);
+		fiber_data32present     : in std_logic_vector(0 to NROFFIBERS-1);
+		fiber_data32in          : in array_fiber32bits_type;
+		fiber_rxerror           : in std_logic_vector(0 to NROFFIBERS-1);
+			
+-- SODA signals
+		superburst_number       : in std_logic_vector(30 downto 0);
+		superburst_update       : in std_logic;
+		SODA_enable             : out std_logic;
+		EnableExternalSODA      : out std_logic;
+
+-- 64 bits data output
+		data_out_allowed        : in std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_error          : out std_logic;
+		no_packet_limit         : out std_logic;
+		
+-- testpoints
+		testword0               : out std_logic_vector (35 downto 0) := (others => '0');
+		testword0clock          : out std_logic := '0';
+		testword1               : out std_logic_vector (35 downto 0) := (others => '0');
+		testword2               : out std_logic_vector (35 downto 0) := (others => '0')
+
+		);
+end component;
+
+component serdesQuadBufLayerMUX is 
+	port (
+		refClk                  : in std_logic;
+		refClk_P                : in std_logic := '0';
+		refClk_N                : in std_logic := '1';
+		sysClk                  : in std_logic;
+		reset                   : in std_logic;
+		reset_fibers            : in std_logic;
+		clk_SODA200             : in std_logic;
+		txAsyncClk              : in std_logic;
+		rxAsyncClk              : in std_logic;
+		txpll_clocks            : out std_logic_vector(3 downto 0);
+
+		G0_txAsyncData          : in std_logic_vector (31 downto 0);
+		G0_txAsyncDataWrite     : in std_logic;
+		G0_txAsyncFifoFull      : out std_logic;
+		G0_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G0_rxAsyncDataRead      : in std_logic;
+		G0_rxAsyncDataOverflow  : out std_logic;
+		G0_rxAsyncDataPresent   : out std_logic;
+		G0_txLocked             : out std_logic;
+		G0_rxLocked             : out std_logic;
+		G0_error                : out std_logic;
+		G0_TX_DLM               : in  std_logic;
+		G0_TX_DLM_WORD          : in  std_logic_vector(7 downto 0); 
+		G0_RX_DLM               : out std_logic;
+		G0_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G0_LOS                  : in std_logic;
+		G0_txP                  : out std_logic;
+		G0_txN                  : out std_logic;
+		G0_rxP                  : in std_logic;
+		G0_rxN                  : in std_logic;
+  
+		G1_txAsyncData          : in std_logic_vector (31 downto 0);
+		G1_txAsyncDataWrite     : in std_logic;
+		G1_txAsyncFifoFull      : out std_logic;
+		G1_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G1_rxAsyncDataRead      : in std_logic;
+		G1_rxAsyncDataOverflow  : out std_logic;
+		G1_rxAsyncDataPresent   : out std_logic;
+		G1_txLocked             : out std_logic;
+		G1_rxLocked             : out std_logic;
+		G1_error                : out std_logic;
+		G1_TX_DLM               : in  std_logic;
+		G1_TX_DLM_WORD          : in  std_logic_vector(7 downto 0);   
+		G1_RX_DLM               : out std_logic;
+		G1_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G1_LOS                  : in std_logic;
+		G1_txP                  : out std_logic;
+		G1_txN                  : out std_logic;
+		G1_rxP                  : in std_logic;
+		G1_rxN                  : in std_logic;
+
+		G2_txAsyncData          : in std_logic_vector (31 downto 0);
+		G2_txAsyncDataWrite     : in std_logic;
+		G2_txAsyncFifoFull      : out std_logic;
+		G2_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G2_rxAsyncDataRead      : in std_logic;
+		G2_rxAsyncDataOverflow  : out std_logic;
+		G2_rxAsyncDataPresent   : out std_logic;
+		G2_txLocked             : out std_logic;
+		G2_rxLocked             : out std_logic;
+		G2_error                : out std_logic;
+		G2_TX_DLM               : in  std_logic;
+		G2_TX_DLM_WORD          : in  std_logic_vector(7 downto 0);  
+		G2_RX_DLM               : out std_logic;
+		G2_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G2_LOS                  : in std_logic;
+		G2_txP                  : out std_logic;
+		G2_txN                  : out std_logic;
+		G2_rxP                  : in std_logic;
+		G2_rxN                  : in std_logic;
+
+		G3_txAsyncData          : in std_logic_vector (31 downto 0);
+		G3_txAsyncDataWrite     : in std_logic;
+		G3_txAsyncFifoFull      : out std_logic;
+		G3_rxAsyncData          : out std_logic_vector (31 downto 0);
+		G3_rxAsyncDataRead      : in std_logic;
+		G3_rxAsyncDataOverflow  : out std_logic;
+		G3_rxAsyncDataPresent   : out std_logic;
+		G3_txLocked             : out std_logic;
+		G3_rxLocked             : out std_logic;
+		G3_error                : out std_logic;
+		G3_TX_DLM               : in  std_logic;
+		G3_TX_DLM_WORD          : in  std_logic_vector(7 downto 0);   
+		G3_RX_DLM               : out std_logic;
+		G3_RX_DLM_WORD          : out std_logic_vector(7 downto 0);
+		G3_LOS                  : in std_logic;
+		G3_txP                  : out std_logic;
+		G3_txN                  : out std_logic;
+		G3_rxP                  : in std_logic;
+		G3_rxN                  : in std_logic;
+
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+		GT0_QPLLOUTCLK_IN       : in std_logic := '0';
+		GT0_QPLLOUTREFCLK_IN    : in std_logic := '0';
+
+		testPin                 : out  std_logic_vector(3 downto 0);
+		testword0               : out std_logic_vector (35 downto 0) := (others => '0'); 
+		testword0clock          : out std_logic := '0'
+	);
+end component;
+
+component DC_SODAserdesWrapper is
+	port (
+		refClk                : in  std_logic;	
+		refClk_P              : in  std_logic;	
+		refClk_N              : in  std_logic;	
+		sysClk                : in  std_logic;	
+		asyncclk              : in  std_logic;
+		gtpReset              : in  std_logic;
+		disable_GTX_reset     : in  std_logic;
+		
+		txData                : in  std_logic_vector (7 downto 0);
+		txCharIsK             : in  std_logic;
+		txP                   : out  std_logic;
+		txN                   : out  std_logic;
+		txUsrClk              : out  std_logic;
+		txLocked              : out  std_logic;
+		
+		rxData                : out  std_logic_vector (7 downto 0);
+		rxCharIsK             : out  std_logic;
+		rxNotInTable          : out  std_logic;
+		rxP                   : in  std_logic;
+		rxN                   : in  std_logic;
+		rxUsrClk              : out std_logic;
+		rxUsrClkdiv2          : out std_logic;
+		rxLocked              : out  std_logic;
+		
+		GT0_QPLLOUTCLK_OUT    : out std_logic := '0';
+		GT0_QPLLOUTREFCLK_OUT : out std_logic := '0';
+		resetDone             : out  std_logic
+	);
+end component;
+
+component DC_SODA_clockcrossing is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		DLM_in                  : in std_logic;
+		DLM_WORD_in             : in std_logic_vector(7 downto 0);
+		DLM_out                 : out std_logic;
+		DLM_WORD_out            : out std_logic_vector(7 downto 0);
+		error                   : out std_logic
+	);
+end component;
+
+component sync_bit is
+	port (
+		clock       : in  std_logic;
+		data_in     : in  std_logic;
+		data_out    : out std_logic
+	);
+end component;
+
+component CN_checkdata is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_error           : in std_logic;
+		data_in_write           : in std_logic;
+		dataerror               : out std_logic;
+		timeerror               : out std_logic;
+		waveerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+--Constants
+  constant REGIO_NUM_STAT_REGS : integer := 2;
+  constant REGIO_NUM_CTRL_REGS : integer := 2;
+  
+  attribute keep         : boolean;
+  attribute syn_keep     : boolean;
+  attribute syn_preserve : boolean;
+
+  --Clock / Reset
+  signal clk_100_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+  signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL 
+  signal clk_80_i                 : std_logic;
+  signal clk_160div3_i            : std_logic;
+  signal USER_SMA_CLOCK_S         : std_logic;
+  
+  
+  signal txpll_clocks_S           : std_logic_vector(3 downto 0);
+  
+  signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
+  signal clk_SODA200_i            : std_logic;
+--//  signal clk_SODA200_jitter_i     : std_logic;
+  signal SD_LOS_S                 : std_logic;
+  signal SD_TXDIS_S               : std_logic;
+  
+  
+  
+  signal clear_i                  : std_logic;
+  signal reset_i                  : std_logic;
+  signal GSR_N                    : std_logic;
+  attribute syn_keep of GSR_N     : signal is true;
+  attribute syn_preserve of GSR_N : signal is true;
+
+  --Media Interface
+  signal med_stat_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_ctrl_op        : std_logic_vector (1*16-1 downto 0);
+  signal med_stat_debug     : std_logic_vector (1*64-1 downto 0);
+  signal med_data_out       : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_out  : std_logic;
+  signal med_read_out       : std_logic;
+  signal med_data_in        : std_logic_vector (1*16-1 downto 0);
+  signal med_packet_num_in  : std_logic_vector (1*3-1 downto 0);
+  signal med_dataready_in   : std_logic;
+  signal med_read_in        : std_logic;
+
+  --LVL1 channel
+  signal trg_data_valid_i      : std_logic;
+  signal trg_timing_valid_i    : std_logic;
+  signal trg_notiming_valid_i  : std_logic;
+  signal trg_invalid_i         : std_logic;
+  signal trg_type_i            : std_logic_vector(3 downto 0);
+  signal trg_number_i          : std_logic_vector(15 downto 0);
+  signal trg_code_i            : std_logic_vector(7 downto 0);
+  signal trg_information_i     : std_logic_vector(23 downto 0);
+  signal trg_int_number_i      : std_logic_vector(15 downto 0);
+  signal trg_multiple_trg_i    : std_logic;
+  signal trg_timeout_detected_i: std_logic;
+  signal trg_spurious_trg_i    : std_logic;
+  signal trg_missing_tmg_trg_i : std_logic;
+  signal trg_spike_detected_i  : std_logic;
+  
+  --Data channel
+  signal fee_almost_full_i    : std_logic;
+
+  --Slow Control channel
+  signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+  signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+  signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0) := (others => '0');
+  signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
+  signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
+  signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
+  signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
+  signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
+
+  --RegIO
+  signal my_address             : std_logic_vector (15 downto 0);
+  signal regio_addr_out         : std_logic_vector (15 downto 0);
+  signal regio_read_enable_out  : std_logic;
+  signal regio_write_enable_out : std_logic;
+  signal regio_data_out         : std_logic_vector (31 downto 0);
+  signal regio_data_in          : std_logic_vector (31 downto 0);
+  signal regio_dataready_in     : std_logic;
+  signal regio_no_more_data_in  : std_logic;
+  signal regio_write_ack_in     : std_logic;
+  signal regio_unknown_addr_in  : std_logic;
+  signal regio_timeout_out      : std_logic;
+
+  --Timer
+  signal global_time         : std_logic_vector(31 downto 0);
+  signal local_time          : std_logic_vector(7 downto 0);
+  signal time_since_last_trg : std_logic_vector(31 downto 0);
+  signal timer_ticks         : std_logic_vector(1 downto 0);
+
+  --Flash
+  signal spictrl_read_en  : std_logic;
+  signal spictrl_write_en : std_logic;
+  signal spictrl_data_in  : std_logic_vector(31 downto 0);
+  signal spictrl_addr     : std_logic;
+  signal spictrl_data_out : std_logic_vector(31 downto 0);
+  signal spictrl_ack      : std_logic;
+  signal spictrl_busy     : std_logic;
+  signal spimem_read_en   : std_logic;
+  signal spimem_write_en  : std_logic;
+  signal spimem_data_in   : std_logic_vector(31 downto 0);
+  signal spimem_addr      : std_logic_vector(5 downto 0);
+  signal spimem_data_out  : std_logic_vector(31 downto 0);
+  signal spimem_ack       : std_logic;
+
+  signal spi_bram_addr    : std_logic_vector(7 downto 0);
+  signal spi_bram_wr_d    : std_logic_vector(7 downto 0);
+  signal spi_bram_rd_d    : std_logic_vector(7 downto 0);
+  signal spi_bram_we      : std_logic;
+
+  signal DLM_to_bottom_S        : t_HUB_BIT;
+  signal DLM_WORD_to_bottom_S   : t_HUB_BYTE;
+  signal DLM_from_bottom_S      : t_HUB_BIT;
+  signal DLM_WORD_from_bottom_S : t_HUB_BYTE;
+
+  signal DLM_hub2uplink_S       : std_logic;
+  signal DLM_WORD_hub2uplink_S  : std_logic_vector(7 downto 0) := (others => '0');
+  signal DLM_source2hub_S       : std_logic;
+  signal DLM_WORD_source2hub_S  : std_logic_vector(7 downto 0) := (others => '0');
+
+  signal SODA_burst_pulse_S     : std_logic;
+  signal soda_40mhz_cycle_S     : std_logic;
+  
+  signal EnableExternalSODA_S   : std_logic;
+  signal EnableExternalSODAsync_S : std_logic;
+
+  signal dataout_data_S         : std_logic_vector(15 downto 0);
+  signal dataout_charisK_S      : std_logic_vector(1 downto 0);
+  signal dataout_clock_S        : std_logic;
+  signal dataout_tx_locked_S    : std_logic;
+ 
+  signal dataout_rec_data_S     : std_logic_vector(15 downto 0);
+  signal dataout_rec_charisK_S  : std_logic_vector(1 downto 0);
+  signal dataout_clock_rec_S    : std_logic;
+  signal dataout_allowed_rec_S  : std_logic;
+  signal dataout_allowed_S      : std_logic;
+
+  signal data64b_muxed_allowed  : std_logic := '1';
+  signal data64b_muxed          : std_logic_vector(63 downto 0);
+  signal data64b_muxed_write    : std_logic;
+  signal data64b_muxed_first    : std_logic;
+  signal data64b_muxed_last     : std_logic;
+  signal data64b_muxed_error    : std_logic;
+  signal data64b_muxed_error_S  : std_logic;
+  signal data64b_muxed_allowed0_S: std_logic := '1';
+  signal data64b_muxed_allowed_S: std_logic := '1';
+  signal data64b_muxed_busy_S   : std_logic;
+  signal no_packet_limit_S      : std_logic;
+  
+  signal data64_S               : std_logic_vector(63 downto 0);
+  signal data64_write_S         : std_logic;
+  signal data64_first_S         : std_logic;
+  signal data64_last_S          : std_logic;
+  signal data64_allowed_S       : std_logic;
+  signal data64_error_S         : std_logic;
+ 
+  signal data64b_count          : std_logic_vector(15 downto 0);
+  
+  --FPGA Test
+  signal time_counter : unsigned(31 downto 0);
+
+  --TDC component
+  component TDC
+    generic (
+      CHANNEL_NUMBER : integer range 0 to 64);
+    port (
+      RESET             : in  std_logic;
+      CLK_TDC           : in  std_logic;
+      CLK_READOUT       : in  std_logic;
+      HIT_IN            : in  std_logic_vector(CHANNEL_NUMBER-1 downto 0);
+      TRIGGER_IN        : in  std_logic;
+      TRIGGER_WIN_IN    : in  std_logic_vector(31 downto 0);
+      DATA_OUT          : out std_logic_vector(31 downto 0);
+      TRB_WR_CLK_OUT    : out std_logic;
+      DATA_VALID_OUT    : out std_logic;
+      DATA_FINISHED_OUT : out std_logic;
+      READY_OUT         : out std_logic;
+      TDC_DEBUG_00      : out std_logic_vector(31 downto 0));
+  end component;
+ 
+   -- data_concentrator
+   
+  signal SODA_clock_selected_S : std_logic;
+  signal PACKETIN_clock    : std_logic;
+  signal MUX_clock         : std_logic;
+  signal PACKETOUT_clock   : std_logic;
+  signal dc_read_en        : std_logic := '0';
+  signal dc_write_en       : std_logic := '0';
+  signal dc_busy           : std_logic := '0';
+  signal dc_ack            : std_logic := '0';
+  signal dc_addr           : std_logic_vector(1 downto 0);
+  signal dc_data_in        : std_logic_vector(31 downto 0);
+  signal dc_data_out       : std_logic_vector(31 downto 0);
+
+    -- soda hub
+  signal soda_read_en      : std_logic;
+  signal soda_write_en     : std_logic;
+  signal soda_ack          : std_logic;
+  signal soda_addr         : std_logic_vector(3 downto 0);
+  signal soda_data_in      : std_logic_vector(31 downto 0);
+  signal soda_data_out     : std_logic_vector(31 downto 0);
+		
+    -- soda source
+  signal sodasrc_read_en   : std_logic;
+  signal sodasrc_write_en  : std_logic;
+  signal sodasrc_ack       : std_logic;
+  signal sodasrc_addr      : std_logic_vector(3 downto 0);
+  signal sodasrc_data_in   : std_logic_vector(31 downto 0);
+  signal sodasrc_data_out  : std_logic_vector(31 downto 0);
+
+	-- external SODA
+
+  signal DLM_from_uplink_S        : std_logic;
+  signal DLM_WORD_from_uplink_S   : std_logic_vector(7 downto 0);
+  signal DLM_to_uplink_S          : std_logic;
+  signal DLM_WORD_to_uplink_S     : std_logic_vector(7 downto 0);
+  signal SODA_IN_rxUsrClk_S       : std_logic;
+  signal SODA_IN_rxLocked_S       : std_logic;
+  signal jittercleaner_reset_S    : std_logic;
+  signal jittercleaner_locked_S   : std_logic;
+  signal jittercleaner_clock_in_S  : std_logic;
+  signal jittercleaner_clock_out_S : std_logic;
+  signal jittercleaner_clock_out0_S : std_logic;
+  signal SODA_reset_S             : std_logic;
+	
+	-- fibers	
+  signal q3_clk0_gtrefclk_S       : std_logic;
+  signal q2_clk1_gtrefclk_S       : std_logic;
+    attribute syn_noclockbuf : boolean;
+    attribute syn_noclockbuf of q3_clk0_gtrefclk_S : signal is true;
+    attribute syn_noclockbuf of q2_clk1_gtrefclk_S : signal is true;
+  signal gt0_qplloutclk_S       : std_logic;
+  signal gt0_qplloutrefclk_S       : std_logic;
+  signal reset_SODAclock_S : std_logic;
+  signal reset_fibers_S    : std_logic;
+  signal reset_fee_S    : std_logic;
+  
+  signal fiber_txlocked_S  : std_logic_vector(0 to NROFFIBERS-1);
+  signal fiber_rxlocked_S  : std_logic_vector(0 to NROFFIBERS-1);
+  signal superburst_update_S : std_logic;
+  signal superburst_number_S : std_logic_vector(30 downto 0);
+  signal fiber_data32write_S : std_logic_vector(0 to NROFFIBERS-1);
+  signal fiber_data32out_S : array_fiber32bits_type;
+  signal fiber_data32fifofull_S : std_logic_vector(0 to NROFFIBERS-1);
+  signal fiber_data32read_S : std_logic_vector(0 to NROFFIBERS-1);
+  signal fiber_data32present_S : std_logic_vector(0 to NROFFIBERS-1);
+  signal fiber_data32in_S  : array_fiber32bits_type;
+  signal fiber_rxerror_S   : std_logic_vector(0 to NROFFIBERS-1);
+
+  -- LEDs
+  signal LEDs_link_ok_i    : std_logic_vector(0 to 3);
+  signal LEDs_rx_i         : std_logic_vector(0 to 3);
+  signal LEDs_tx_i         : std_logic_vector(0 to 3);
+
+
+  signal testword0clock_i    : std_logic;
+  attribute syn_keep of testword0clock_i     : signal is true; 
+  attribute syn_preserve of testword0clock_i     : signal is true; 
+
+  attribute syn_keep of clk_100_i : signal is true;
+  attribute syn_keep of clk_200_i : signal is true;
+  
+  attribute syn_keep of clk_80_i : signal is true;
+  attribute syn_keep of clk_SODA200_i : signal is true;
+
+  attribute syn_preserve of clk_100_i : signal is true;
+  attribute syn_preserve of clk_200_i : signal is true;
+  attribute syn_preserve of clk_80_i : signal is true;
+  attribute syn_preserve of clk_SODA200_i : signal is true;
+
+  signal data64b_dataerror        : std_logic;
+  signal data64b_timeerror        : std_logic;
+  signal data64b_waveerror        : std_logic;
+
+  signal dumadr0                  : std_logic_vector(5*16-1 downto 0);
+  type debug_superbursts_type is array(7 downto 0) of std_logic_vector(7 downto 0);
+  signal debug_nextsuperburst_S   : std_logic := '0';
+  signal debug_counter_S          : integer := 0;
+  signal debug_superburst_error_S : std_logic := '0';
+  signal debug_emptypacket_S      : std_logic := '0';
+  signal debug_superburst_S       : std_logic_vector(30 downto 0);
+  signal debug_superbursts_S      : debug_superbursts_type := (others => (others => '0'));
+  signal debug_nrofbytes_S        : std_logic_vector(15 downto 0);
+
+  signal debug_clkdiv2_1          : std_logic;
+  signal debug_clkdiv2_2          : std_logic;
+  signal debug_clkdiv2_3          : std_logic;
+  signal debug_clkdiv2_4          : std_logic;
+
+  signal testword0_S              : std_logic_vector(35 downto 0) := (others => '0');
+
+attribute mark_debug : string;
+-- attribute mark_debug of dataout_data_S : signal is "true";
+-- attribute mark_debug of dataout_charisK_S : signal is "true";
+-- attribute mark_debug of dataout_tx_locked_S : signal is "true";
+-- attribute mark_debug of data64b_muxed_allowed : signal is "true";
+-- attribute mark_debug of data64b_muxed : signal is "true";
+-- attribute mark_debug of data64b_muxed_write : signal is "true";
+-- attribute mark_debug of data64b_muxed_first : signal is "true";
+-- attribute mark_debug of data64b_muxed_last : signal is "true";
+-- attribute mark_debug of data64b_muxed_error : signal is "true";
+-- attribute mark_debug of data64b_dataerror : signal is "true";
+-- attribute mark_debug of data64b_timeerror : signal is "true";
+-- attribute mark_debug of data64b_waveerror : signal is "true";
+-- attribute mark_debug of data64b_count : signal is "true";
+-- attribute mark_debug of dataout_tx_locked_S : signal is "true";
+-- attribute mark_debug of dataout_data_S : signal is "true";
+-- attribute mark_debug of dataout_charisK_S : signal is "true";
+-- attribute mark_debug of dataout_rec_data_S : signal is "true";
+-- attribute mark_debug of dataout_rec_charisK_S : signal is "true";
+
+-- attribute mark_debug of data64b_muxed : signal is "true";
+-- attribute mark_debug of data64b_muxed_write : signal is "true";
+-- attribute mark_debug of data64b_muxed_first : signal is "true";
+-- attribute mark_debug of data64b_muxed_last : signal is "true";
+-- attribute mark_debug of data64b_muxed_busy_S : signal is "true";
+-- attribute mark_debug of data64_S : signal is "true";
+-- attribute mark_debug of data64_write_S : signal is "true";
+-- attribute mark_debug of data64_first_S : signal is "true";
+-- attribute mark_debug of data64_last_S : signal is "true";
+-- attribute mark_debug of data64_allowed_S : signal is "true";
+--attribute mark_debug of data64_error_S : signal is "true";
+
+  
+attribute mark_debug of fiber_data32out_S : signal is "true";
+attribute mark_debug of fiber_data32write_S : signal is "true";
+attribute mark_debug of fiber_data32fifofull_S : signal is "true";
+attribute mark_debug of fiber_data32in_S : signal is "true";
+attribute mark_debug of fiber_data32read_S : signal is "true";
+attribute mark_debug of fiber_data32present_S : signal is "true";
+
+  
+  
+begin
+
+
+---------------------------------------------------------------------------
+-- Reset Generation
+---------------------------------------------------------------------------
+
+GSR_N <= pll_lock;
+SFP_TX_DISABLE <= not SD_TXDIS_S;
+
+
+  THE_RESET_HANDLER : trb_net_reset_handler
+    generic map(
+      RESET_DELAY => x"FEEE"
+      )
+    port map(
+      CLEAR_IN      => '0',              -- reset input (high active, async)
+      CLEAR_N_IN    => '1',              -- reset input (low active, async)
+      CLK_IN        => clk_200_i,        -- raw master clock, NOT from PLL/DLL!
+      SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
+      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
+      RESET_IN      => GPIO_SW_C,              -- general reset signal (SYSCLK)
+      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
+      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
+      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
+      DEBUG_OUT     => open
+      );  
+
+---------------------------------------------------------------------------
+-- Clock Handling
+---------------------------------------------------------------------------
+
+THE_MAIN_PLL : pll_in200_out200_160_100_80 port map(
+	clk_in1_p => SYSCLK_P,
+	clk_in1_n => SYSCLK_N,
+	clk_out1 => clk_200_i,
+	clk_out2 => clk_100_i,
+	clk_out3 => clk_80_i,
+	clk_out4 => clk_160div3_i,
+	reset => '0',
+	locked  => pll_lock);
+
+BUF_sma_clock_inst : OBUFDS
+	generic map(
+		IOSTANDARD => "LVDS_25")
+	port map( 
+		O  => USER_SMA_CLOCK_P,
+		OB => USER_SMA_CLOCK_N,
+		I  => USER_SMA_CLOCK_S);
+		
+BUF_jittercleanerclock_inst : OBUFDS -- reference clock for jitter cleaner
+	generic map(
+		IOSTANDARD => "LVDS_25")
+	port map( 
+		O  => REC_CLOCK_C_P,
+		OB => REC_CLOCK_C_N,
+		I  => clk_200_i);	
+	
+		
+PACKETIN_clock <= clk_160div3_i; -- clk_80_i;
+MUX_clock <= clk_80_i; --clk_100_i;
+PACKETOUT_clock <= clk_80_i;
+
+---------------------------------------------------------------------------
+-- The TrbNet media interface (to other FPGA)
+---------------------------------------------------------------------------
+THE_MEDIA_UPLINK : trb_net16_med_sync_gtx2_kintex7_sfp
+	port map(
+		CLK => clk_200_i,
+		SYSCLK => clk_100_i,
+		SODA_clock => clk_SODA200_i,
+		RESET => reset_i,
+		CLEAR => clear_i,
+		CLK_EN => '1',
+		disable_GTX_reset => '0',
+		--Internal Connection
+		MED_DATA_IN => med_data_out,
+		MED_PACKET_NUM_IN => med_packet_num_out,
+		MED_DATAREADY_IN => med_dataready_out,
+		MED_READ_OUT => med_read_in,
+		MED_DATA_OUT => med_data_in,
+		MED_PACKET_NUM_OUT => med_packet_num_in,
+		MED_DATAREADY_OUT => med_dataready_in,
+		MED_READ_IN => med_read_out,
+		REFCLK2CORE_OUT => open,
+		CLK_RX_HALF_OUT => open,
+		CLK_RX_FULL_OUT => open,
+		--SFP Connection
+		SODA_RXD_P_IN => SFP_RX_P,
+		SODA_RXD_N_IN => SFP_RX_N,
+		SODA_TXD_P_OUT => SFP_TX_P,
+		SODA_TXD_N_OUT => SFP_TX_N,
+		SODA_REFCLK_P_IN => SGMIICLK_Q0_P,
+		SODA_REFCLK_N_IN => SGMIICLK_Q0_N,
+		SODA_PRSNT_N_IN => SD_LOS_S,
+		SODA_LOS_IN => SD_LOS_S,
+		SODA_TXDIS_OUT => SD_TXDIS_S,
+		SODA_DLM_IN => DLM_to_uplink_S,
+		SODA_DLM_WORD_IN => DLM_WORD_to_uplink_S,
+		SODA_DLM_OUT => DLM_from_uplink_S,
+		SODA_DLM_WORD_OUT => DLM_WORD_from_uplink_S,
+		SODA_CLOCK_OUT => SODA_IN_rxUsrClk_S, -- 200MHz
+		SODA_LOCKED_OUT => SODA_IN_rxLocked_S,
+		-- Status and control port
+		STAT_OP => med_stat_op,
+		CTRL_OP => med_ctrl_op,
+		STAT_DEBUG => med_stat_debug,
+		CTRL_DEBUG => (others => '0')
+	);
+process(clk_100_i)
+begin
+	if (rising_edge(clk_100_i)) then 
+		SD_LOS_S <= SFP_LOS_LS;
+	end if;
+end process;
+		
+
+THE_DATAOUTPUT: GTX_dataoutputwrapper port map(
+		sysClk  => clk_100_i,
+		refClk_P => q2_clk1_gtrefclk_S,
+		refClk_N => q3_clk0_gtrefclk_S,
+		clock_out => dataout_clock_S,
+		clock_rec => dataout_clock_rec_S,
+		reset => reset_i,
+		data_in => dataout_data_S,
+		kchar_in => dataout_charisK_S,
+		data_out => dataout_rec_data_S,
+		kchar_out => dataout_rec_charisK_S,
+		G0_txP => X0Y14_TX_P_OPAD,
+		G0_txN => X0Y14_TX_N_OPAD,
+		G0_rxP => X0Y14_RX_P_IPAD,
+		G0_rxN => X0Y14_RX_N_IPAD,
+		G0_LOS => fmc_sfp_los(2),
+		tx_locked => dataout_tx_locked_S,
+ 		GT0_QPLLOUTCLK_IN => gt0_qplloutclk_S,
+		GT0_QPLLOUTREFCLK_IN => gt0_qplloutrefclk_S
+	);
+
+process(dataout_clock_rec_S)
+begin
+	if (rising_edge(dataout_clock_rec_S)) then 
+		if ((dataout_rec_data_S(15 downto 8)=x"3C") and (dataout_rec_charisK_S(1)='1')) or 
+		   ((dataout_rec_data_S(7 downto 0)=x"3C") and (dataout_rec_charisK_S(0)='1')) then
+			dataout_allowed_rec_S <= '0';
+		else
+			dataout_allowed_rec_S <= '1';
+		end if;
+	end if;
+end process;
+sync_dataout_allowed: sync_bit port map(
+		clock => dataout_clock_S,
+		data_in => dataout_allowed_rec_S,
+		data_out => dataout_allowed_S);	
+	
+THE_DATACONVERSION : dataconversion_for_serdes16
+	port map (
+		DATA_CLK         => PACKETOUT_clock,
+		CLK              => dataout_clock_S,
+		RESET            => reset_i,
+		TX_READY         => dataout_tx_locked_S,
+		SFP_MOD0         => '0',
+		SFP_LOS          => '0', --//fmc_sfp_los(2),
+		TX_ALLOWED       => dataout_allowed_S,
+		TX_DATA          => dataout_data_S,
+		TX_K             => dataout_charisK_S,
+		DATA_IN_ALLOWED  => data64_allowed_S, -- data64b_muxed_allowed,
+		DATA_IN          => data64_S, -- data64b_muxed,
+		DATA_IN_WRITE    => data64_write_S, -- data64b_muxed_write,
+		DATA_IN_FIRST    => data64_first_S, -- data64b_muxed_first,
+		DATA_IN_LAST     => data64_last_S, -- data64b_muxed_last,
+		DATA_IN_ERROR    => data64_error_S -- data64b_muxed_error
+	);
+
+data64b_muxed_allowed <= data64_allowed_S;
+data64_S <= data64b_muxed;
+data64_first_S <= data64b_muxed_first;
+data64_last_S <= data64b_muxed_last;
+data64_write_S <= data64b_muxed_write;
+data64_error_S <= data64b_muxed_error;
+
+
+data64b_muxed_allowed_S <= '1' when (data64b_muxed_allowed='1') and (data64b_muxed_allowed0_S='1') else '0';
+
+THE_CHECK : CN_checkdata port map(
+		clock => PACKETOUT_clock,
+		reset => '0',
+		data_in => data64b_muxed,
+		data_in_first => data64b_muxed_first,
+		data_in_last  => data64b_muxed_last,
+		data_in_error => data64b_muxed_error,
+		data_in_write => data64b_muxed_write,
+		dataerror => data64b_dataerror,
+		timeerror => data64b_timeerror,
+		waveerror => data64b_waveerror,
+		testword0 => open);
+
+
+process(PACKETOUT_clock)
+constant MINCLOCKSBETWEENPACKETS : integer := ADCCLOCKFREQUENCY/500000; -- 2048;
+variable counting : boolean := FALSE;
+variable counterpacket : integer range 0 to 65535 := 0;
+variable counterwait : integer range 0 to 65535 := 0;
+begin
+	if (rising_edge(PACKETOUT_clock)) then
+		data64b_muxed_error_S <= '0';
+		if (data64b_muxed_write='1') and (data64b_muxed_last='1') then
+			data64b_muxed_allowed0_S <= '0';
+			counterwait := counterpacket;
+		elsif (counterwait<MINCLOCKSBETWEENPACKETS) and (no_packet_limit_S='0') then
+			data64b_muxed_allowed0_S <= '0';
+			counterwait := counterwait+1;
+		else
+			data64b_muxed_allowed0_S <= data64b_muxed_allowed;
+		end if;
+		if (data64b_muxed_write='1') and (data64b_muxed_first='1') then
+			counting := TRUE;
+			counterpacket := 0;
+		elsif (data64b_muxed_write='1') and (data64b_muxed_last='1') then
+			counting := FALSE;
+		else
+			if (counting) and (counterpacket<65535) then
+				counterpacket := counterpacket+1;
+			end if;
+		end if;
+		if (data64b_muxed_write='1') then
+			if (data64b_muxed_first='1') and (data64b_muxed_last='1') then
+				data64b_muxed_error_S <= '1';
+			elsif data64b_muxed_first='1' then
+				if data64b_muxed_busy_S='1' then
+					data64b_muxed_error_S <= '1';
+				end if;
+				data64b_muxed_busy_S <= '1';
+			elsif data64b_muxed_last='1' then
+				if data64b_muxed_busy_S='0' then
+					data64b_muxed_error_S <= '1';
+				end if;
+				data64b_muxed_busy_S <= '0';
+			else
+			end if;
+		end if;
+	end if;
+end process;
+
+process(PACKETOUT_clock)
+begin
+	if (rising_edge(PACKETOUT_clock)) then
+		debug_nextsuperburst_S <= '0';
+		debug_superburst_error_S <= '0';
+		if data64b_muxed_write='1' then
+			if data64b_muxed_first='1' then
+				debug_counter_S <= 0;
+				if data64b_muxed(47 downto 32) = conv_std_logic_vector(16,16) then
+					debug_emptypacket_S <= '1';
+				else
+					debug_emptypacket_S <= '0';
+				end if;
+				debug_nrofbytes_S <= data64b_muxed(47 downto 32);
+			elsif debug_counter_S=0 then
+				if data64b_muxed(63)='0' then -- pulse data
+					if (debug_superburst_S+1) /= data64b_muxed(30 downto 0) then
+						debug_superburst_error_S <= '1';
+					end if;
+					debug_nextsuperburst_S <= '1';
+					debug_superburst_S <= data64b_muxed(30 downto 0);
+					for i in 1 to 7 loop
+						debug_superbursts_S(i) <= debug_superbursts_S(i-1);
+					end loop;
+					debug_superbursts_S(0) <= data64b_muxed(7 downto 0);
+				end if;
+				if data64b_muxed_last='1' then
+					if debug_nrofbytes_S /= conv_std_logic_vector((debug_counter_S+2)*8,16) then
+						debug_superburst_error_S <= '1';
+					end if;
+				end if;
+				debug_counter_S <= debug_counter_S+1;
+			elsif data64b_muxed_last='1' then
+				if debug_nrofbytes_S /= conv_std_logic_vector((debug_counter_S+2)*8,16) then
+					debug_superburst_error_S <= '1';
+				end if;
+				debug_counter_S <= debug_counter_S+1;
+			else
+				debug_counter_S <= debug_counter_S+1;
+			end if;
+		end if;
+	end if;
+end process;
+
+    
+---------------------------------------------------------------------------
+-- Endpoint
+---------------------------------------------------------------------------
+
+ THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+   generic map(
+     REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
+     REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
+     ADDRESS_MASK              => x"FFFF",
+     BROADCAST_BITMASK         => x"FF",
+     BROADCAST_SPECIAL_ADDR    => x"45",
+     REGIO_COMPILE_TIME        => conv_std_logic_vector(VERSION_NUMBER_TIME, 32),
+     REGIO_HARDWARE_VERSION    => x"91000001",
+     REGIO_USE_1WIRE_INTERFACE => c_NO, --c_YES,c_NO,c_MONITOR
+     REGIO_INIT_ADDRESS        => x"f310",
+     REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+     CLOCK_FREQUENCY           => 100,
+     TIMING_TRIGGER_RAW        => c_YES,
+     --Configure data handler
+     DATA_INTERFACE_NUMBER     => 1,
+     DATA_BUFFER_DEPTH         => 13,         --13
+     DATA_BUFFER_WIDTH         => 32,
+     DATA_BUFFER_FULL_THRESH   => 2**13-800,  --2**13-1024
+     TRG_RELEASE_AFTER_DATA    => c_YES,
+     HEADER_BUFFER_DEPTH       => 9,
+     HEADER_BUFFER_FULL_THRESH => 2**9-16
+     )
+   port map(
+     CLK                => clk_100_i,
+     RESET              => reset_i,
+     CLK_EN             => '1',
+     MED_DATAREADY_OUT  => med_dataready_out,  -- open, --
+     MED_DATA_OUT       => med_data_out,  -- open, --
+     MED_PACKET_NUM_OUT => med_packet_num_out,  -- open, --
+     MED_READ_IN        => med_read_in,
+     MED_DATAREADY_IN   => med_dataready_in,
+     MED_DATA_IN        => med_data_in,
+     MED_PACKET_NUM_IN  => med_packet_num_in,
+     MED_READ_OUT       => med_read_out,  -- open, --
+     MED_STAT_OP_IN     => med_stat_op,
+     MED_CTRL_OP_OUT    => med_ctrl_op,
+
+     --Timing trigger in
+     TRG_TIMING_TRG_RECEIVED_IN  => '0',
+     --LVL1 trigger to FEE
+     LVL1_TRG_DATA_VALID_OUT     => trg_data_valid_i,
+     LVL1_VALID_TIMING_TRG_OUT   => trg_timing_valid_i,
+     LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
+     LVL1_INVALID_TRG_OUT        => trg_invalid_i,
+
+     LVL1_TRG_TYPE_OUT        => trg_type_i,
+     LVL1_TRG_NUMBER_OUT      => trg_number_i,
+     LVL1_TRG_CODE_OUT        => trg_code_i,
+     LVL1_TRG_INFORMATION_OUT => trg_information_i,
+     LVL1_INT_TRG_NUMBER_OUT  => trg_int_number_i,
+
+     --Information about trigger handler errors
+     TRG_MULTIPLE_TRG_OUT         => trg_multiple_trg_i,
+     TRG_TIMEOUT_DETECTED_OUT     => trg_timeout_detected_i,
+     TRG_SPURIOUS_TRG_OUT         => trg_spurious_trg_i,
+     TRG_MISSING_TMG_TRG_OUT      => trg_missing_tmg_trg_i,
+     TRG_SPIKE_DETECTED_OUT       => trg_spike_detected_i,
+     
+     --Response from FEE
+     FEE_TRG_RELEASE_IN(0)       => '0',
+     FEE_TRG_STATUSBITS_IN       => (others => '0'),
+     FEE_DATA_IN                 => (others => '0'),
+     FEE_DATA_WRITE_IN(0)        => '0',
+     FEE_DATA_FINISHED_IN(0)     => '0',
+     FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
+
+     -- Slow Control Data Port
+     REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
+     REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
+     REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
+     REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
+     REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
+     REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
+     REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
+     REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
+     REGIO_VAR_ENDPOINT_ID(1 downto 0)  => (others => '0'), --CODE_LINE,
+     REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
+
+     BUS_ADDR_OUT         => regio_addr_out,
+     BUS_READ_ENABLE_OUT  => regio_read_enable_out,
+     BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
+     BUS_DATA_OUT         => regio_data_out,
+     BUS_DATA_IN          => regio_data_in,
+     BUS_DATAREADY_IN     => regio_dataready_in,
+     BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
+     BUS_WRITE_ACK_IN     => regio_write_ack_in,
+     BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
+     BUS_TIMEOUT_OUT      => regio_timeout_out,
+     ONEWIRE_INOUT        => open, -- TEMPSENS,
+     ONEWIRE_MONITOR_OUT  => open,
+
+     TIME_GLOBAL_OUT         => global_time,
+     TIME_LOCAL_OUT          => local_time,
+     TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
+     TIME_TICKS_OUT          => timer_ticks,
+
+     STAT_DEBUG_IPU              => open,
+     STAT_DEBUG_1                => open,
+     STAT_DEBUG_2                => open,
+     STAT_DEBUG_DATA_HANDLER_OUT => open,
+     STAT_DEBUG_IPU_HANDLER_OUT  => open,
+     STAT_TRIGGER_OUT            => open,
+     CTRL_MPLEX                  => (others => '0'),
+     IOBUF_CTRL_GEN              => (others => '0'),
+     STAT_ONEWIRE                => open,
+     STAT_ADDR_DEBUG             => open,
+     DEBUG_LVL1_HANDLER_OUT      => open
+     );
+
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler
+   generic map(
+     PORT_NUMBER    => 5,
+     PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"e000", 3 => x"e100", 4 => x"e200", others => x"0000"),
+     PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 2, 3 => 4, 4 => 4, others => 0)
+--     PORT_MASK_ENABLE => 0
+     )
+   port map(
+     CLK   => clk_100_i,
+     RESET => reset_i,
+
+     DAT_ADDR_IN          => regio_addr_out,
+     DAT_DATA_IN          => regio_data_out,
+     DAT_DATA_OUT         => regio_data_in,
+     DAT_READ_ENABLE_IN   => regio_read_enable_out,
+     DAT_WRITE_ENABLE_IN  => regio_write_enable_out,
+     DAT_TIMEOUT_IN       => regio_timeout_out,
+     DAT_DATAREADY_OUT    => regio_dataready_in,
+     DAT_WRITE_ACK_OUT    => regio_write_ack_in,
+     DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
+     DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
+		
+     BUS_READ_ENABLE_OUT(0)              => spictrl_read_en,
+     BUS_READ_ENABLE_OUT(1)              => spimem_read_en,
+     BUS_READ_ENABLE_OUT(2)              => dc_read_en,
+     BUS_READ_ENABLE_OUT(3)              => soda_read_en,
+     BUS_READ_ENABLE_OUT(4)              => sodasrc_read_en,
+     BUS_WRITE_ENABLE_OUT(0)             => spictrl_write_en,
+     BUS_WRITE_ENABLE_OUT(1)             => spimem_write_en,
+     BUS_WRITE_ENABLE_OUT(2)             => dc_write_en,
+     BUS_WRITE_ENABLE_OUT(3)             => soda_write_en,
+     BUS_WRITE_ENABLE_OUT(4)             => sodasrc_write_en,
+     BUS_DATA_OUT(0*32+31 downto 0*32)   => spictrl_data_in,
+     BUS_DATA_OUT(1*32+31 downto 1*32)   => spimem_data_in,
+     BUS_DATA_OUT(2*32+31 downto 2*32)   => dc_data_in,
+     BUS_DATA_OUT(3*32+31 downto 3*32)   => soda_data_in,
+     BUS_DATA_OUT(4*32+31 downto 4*32)   => sodasrc_data_in,
+     BUS_ADDR_OUT(0*16)                  => spictrl_addr,
+     BUS_ADDR_OUT(0*16+15 downto 0*16+1) => dumadr0(0*16+15 downto 0*16+1),
+     BUS_ADDR_OUT(1*16+5 downto 1*16)    => spimem_addr,
+     BUS_ADDR_OUT(1*16+15 downto 1*16+6) => dumadr0(1*16+15 downto 1*16+6),
+     BUS_ADDR_OUT(2*16+1 downto 2*16)    => dc_addr,
+     BUS_ADDR_OUT(2*16+15 downto 2*16+2) => dumadr0(2*16+15 downto 2*16+2),
+     BUS_ADDR_OUT(3*16+3 downto 3*16)    => soda_addr,
+     BUS_ADDR_OUT(3*16+15 downto 3*16+4) => dumadr0(3*16+15 downto 3*16+4),
+     BUS_ADDR_OUT(4*16+3 downto 4*16)    => sodasrc_addr,
+     BUS_ADDR_OUT(4*16+15 downto 4*16+4) => dumadr0(4*16+15 downto 4*16+4),
+     BUS_DATA_IN(0*32+31 downto 0*32)    => spictrl_data_out,
+     BUS_DATA_IN(1*32+31 downto 1*32)    => spimem_data_out,
+     BUS_DATA_IN(2*32+31 downto 2*32)    => dc_data_out,
+     BUS_DATA_IN(3*32+31 downto 3*32)    => soda_data_out,
+     BUS_DATA_IN(4*32+31 downto 4*32)    => sodasrc_data_out,
+     BUS_DATAREADY_IN(0)                 => spictrl_ack,
+     BUS_DATAREADY_IN(1)                 => spimem_ack,
+     BUS_DATAREADY_IN(2)                 => dc_ack,
+     BUS_DATAREADY_IN(3)                 => soda_ack,
+     BUS_DATAREADY_IN(4)                 => sodasrc_ack,
+     BUS_WRITE_ACK_IN(0)                 => spictrl_ack,
+     BUS_WRITE_ACK_IN(1)                 => spimem_ack,
+     BUS_WRITE_ACK_IN(2)                 => dc_ack,
+     BUS_WRITE_ACK_IN(3)                 => soda_ack,
+     BUS_WRITE_ACK_IN(4)                 => sodasrc_ack,
+     BUS_NO_MORE_DATA_IN(0)              => spictrl_busy,
+     BUS_NO_MORE_DATA_IN(1)              => '0',
+     BUS_NO_MORE_DATA_IN(2)              => dc_busy,
+     BUS_NO_MORE_DATA_IN(3)              => '0',
+     BUS_NO_MORE_DATA_IN(4)              => '0',
+     BUS_UNKNOWN_ADDR_IN(0)              => '0',
+     BUS_UNKNOWN_ADDR_IN(1)              => '0',
+     BUS_UNKNOWN_ADDR_IN(2)              => '0',
+     BUS_UNKNOWN_ADDR_IN(3)              => '0',
+     BUS_UNKNOWN_ADDR_IN(4)              => '0',
+     BUS_TIMEOUT_OUT                     => open,
+     -- BUS_TIMEOUT_OUT(0)                  => open,
+     -- BUS_TIMEOUT_OUT(1)                  => open,
+     -- BUS_TIMEOUT_OUT(2)                  => open,
+     -- BUS_TIMEOUT_OUT(3)                  => open,
+     -- BUS_TIMEOUT_OUT(4)                  => open,
+
+     --Bus Handler (SPI CTRL)
+     --Bus Handler (SPI Memory)
+     --Bus Handler (test port)
+
+     STAT_DEBUG => open
+     );
+
+---------------------------------------------------------------------------
+-- SPI / Flash
+---------------------------------------------------------------------------
+
+ THE_SPI_MASTER : spi_master
+   port map(
+     CLK_IN         => clk_100_i,
+     RESET_IN       => reset_i,
+     -- Slave bus
+     BUS_READ_IN    => spictrl_read_en,
+     BUS_WRITE_IN   => spictrl_write_en,
+     BUS_BUSY_OUT   => spictrl_busy,
+     BUS_ACK_OUT    => spictrl_ack,
+     BUS_ADDR_IN(0) => spictrl_addr,
+     BUS_DATA_IN    => spictrl_data_in,
+     BUS_DATA_OUT   => spictrl_data_out,
+     -- SPI connections
+     SPI_CS_OUT     => open, -- FLASH_CS,
+     SPI_SDI_IN     => '0', -- FLASH_DOUT,
+     SPI_SDO_OUT    => open, -- FLASH_DIN,
+     SPI_SCK_OUT    => open, -- FLASH_CLK,
+     -- BRAM for read/write data
+     BRAM_A_OUT     => spi_bram_addr,
+     BRAM_WR_D_IN   => spi_bram_wr_d,
+     BRAM_RD_D_OUT  => spi_bram_rd_d,
+     BRAM_WE_OUT    => spi_bram_we,
+     -- Status lines
+     STAT           => open
+     );
+
+-- data memory for SPI accesses
+ THE_SPI_MEMORY : spi_databus_memory
+   port map(
+     CLK_IN        => clk_100_i,
+     RESET_IN      => reset_i,
+     -- Slave bus
+     BUS_ADDR_IN   => spimem_addr,
+     BUS_READ_IN   => spimem_read_en,
+     BUS_WRITE_IN  => spimem_write_en,
+     BUS_ACK_OUT   => spimem_ack,
+     BUS_DATA_IN   => spimem_data_in,
+     BUS_DATA_OUT  => spimem_data_out,
+     -- state machine connections
+     BRAM_ADDR_IN  => spi_bram_addr,
+     BRAM_WR_D_OUT => spi_bram_wr_d,
+     BRAM_RD_D_IN  => spi_bram_rd_d,
+     BRAM_WE_IN    => spi_bram_we,
+     -- Status lines
+     STAT          => open
+     );
+
+
+---------------------------------------------------------------------------
+-- Reboot FPGA
+---------------------------------------------------------------------------
+  THE_FPGA_REBOOT : fpga_reboot
+    port map(
+      CLK       => clk_100_i,
+      RESET     => reset_i,
+      DO_REBOOT => common_ctrl_reg(15),
+      PROGRAMN  => open -- PROGRAMN
+      );
+
+THE_DATACONCENTRATOR: DC_module_TRB3 port map(
+		slowcontrol_clock => clk_100_i,
+		packet_in_clock => PACKETIN_clock,
+		MUX_clock  => MUX_clock,
+		packet_out_clock => PACKETOUT_clock,
+		SODA_clock => clk_SODA200_i,
+		reset => reset_i,
+
+-- Slave bus
+		BUS_READ_IN => dc_read_en,
+		BUS_WRITE_IN => dc_write_en,
+		BUS_BUSY_OUT => dc_busy,
+		BUS_ACK_OUT => dc_ack,
+		BUS_ADDR_IN => dc_addr,
+		BUS_DATA_IN => dc_data_in,
+		BUS_DATA_OUT => dc_data_out,
+
+-- fiber interface signals:
+		fiber_txlocked => fiber_txlocked_S,
+		fiber_rxlocked => fiber_rxlocked_S,
+		reset_fibers => reset_fibers_S,
+		fiber_data32write => fiber_data32write_S,
+		fiber_data32out => fiber_data32out_S,
+		fiber_data32fifofull => fiber_data32fifofull_S,
+		fiber_data32read => fiber_data32read_S,
+		fiber_data32present => fiber_data32present_S,
+		fiber_data32in => fiber_data32in_S,
+		fiber_rxerror => fiber_rxerror_S,
+		
+-- SODA signals
+		superburst_number => superburst_number_S,
+		superburst_update => superburst_update_S,
+		SODA_enable => open,
+		EnableExternalSODA => EnableExternalSODA_S,
+
+-- 64 bits data output
+		data_out_allowed => data64b_muxed_allowed_S, 
+		data_out => data64b_muxed,        
+		data_out_write => data64b_muxed_write, 
+		data_out_first => data64b_muxed_first,
+		data_out_last => data64b_muxed_last, 
+		data_out_error => data64b_muxed_error, 
+		no_packet_limit => no_packet_limit_S,		
+
+-- testpoints
+		testword0 => open,
+		testword0clock => open,
+		testword1 => open,
+		testword2 => open
+		);
+	
+sync_reset_SODA_clock: sync_bit port map(
+		clock => clk_SODA200_i,
+		data_in => reset_i,
+		data_out => reset_SODAclock_S);
+
+soda_packet_handler1 : soda_packet_handler port map(
+		SODACLK => clk_SODA200_i,
+		RESET => reset_SODAclock_S,
+		CLEAR => '0',
+		CLK_EN => '1',
+		--Internal Connection
+		START_OF_SUPERBURST_OUT => superburst_update_S,
+		SUPER_BURST_NR_OUT => superburst_number_S,
+		START_OF_CALIBRATION_OUT => open,
+		SODA_CMD_VALID_OUT => open,
+		SODA_CMD_WORD_OUT => open,
+		RX_DLM_IN => DLM_to_bottom_S(0),
+		RX_DLM_WORD_IN => DLM_WORD_to_bottom_S(0)
+);
+		
+reset_fee_S <= '1' when (reset_i='1') or (SODA_IN_rxLocked_S='0') else '0';
+
+THE_FEE_SERDES: serdesQuadBufLayerMUX port map(
+		refClk => txpll_clocks_S(0), --//clk_SODA200_i,
+		refClk_P => q2_clk1_gtrefclk_S,
+		refClk_N => q3_clk0_gtrefclk_S,
+		sysClk => clk_100_i,
+		reset => reset_fee_S,
+		reset_fibers => reset_fibers_S,
+		clk_SODA200 => clk_SODA200_i,
+		txAsyncClk => clk_100_i, -- slowcontrol_clock
+		rxAsyncClk => PACKETIN_clock,
+		txpll_clocks => txpll_clocks_S,
+
+		G0_txAsyncData => fiber_data32out_S(0),
+		G0_txAsyncDataWrite => fiber_data32write_S(0),
+		G0_txAsyncFifoFull => fiber_data32fifofull_S(0),
+		G0_rxAsyncData => fiber_data32in_S(0),
+		G0_rxAsyncDataRead => fiber_data32read_S(0),
+		G0_rxAsyncDataOverflow => open,
+		G0_rxAsyncDataPresent => fiber_data32present_S(0),
+		G0_txLocked => fiber_txlocked_S(0),
+		G0_rxLocked => fiber_rxlocked_S(0),
+		G0_error => fiber_rxerror_S(0),
+
+		G0_TX_DLM => DLM_to_bottom_S(0),
+		G0_TX_DLM_WORD => DLM_WORD_to_bottom_S(0),
+		G0_RX_DLM => DLM_from_bottom_S(0),
+		G0_RX_DLM_WORD => DLM_WORD_from_bottom_S(0),
+		G0_LOS => fmc_sfp_los(3),
+		G0_txP => X0Y12_TX_P_OPAD, 
+		G0_txN => X0Y12_TX_N_OPAD, 
+		G0_rxP => X0Y12_RX_P_IPAD, 
+		G0_rxN => X0Y12_RX_N_IPAD, 
+  
+		G1_txAsyncData => fiber_data32out_S(1),
+		G1_txAsyncDataWrite => fiber_data32write_S(1),
+		G1_txAsyncFifoFull => fiber_data32fifofull_S(1),
+		G1_rxAsyncData => fiber_data32in_S(1),
+		G1_rxAsyncDataRead => fiber_data32read_S(1),
+		G1_rxAsyncDataOverflow => open,
+		G1_rxAsyncDataPresent => fiber_data32present_S(1),
+		G1_txLocked => fiber_txlocked_S(1),
+		G1_rxLocked => fiber_rxlocked_S(1),
+		G1_error => fiber_rxerror_S(1),
+		G1_TX_DLM => DLM_to_bottom_S(1),
+		G1_TX_DLM_WORD => DLM_WORD_to_bottom_S(1),
+		G1_RX_DLM => DLM_from_bottom_S(1),
+		G1_RX_DLM_WORD => DLM_WORD_from_bottom_S(1),
+		G1_LOS => fmc_sfp_los(2),
+		G1_txP => X0Y13_TX_P_OPAD, 
+		G1_txN => X0Y13_TX_N_OPAD, 
+		G1_rxP => X0Y13_RX_P_IPAD, 
+		G1_rxN => X0Y13_RX_N_IPAD, 
+
+		G2_txAsyncData => fiber_data32out_S(2),
+		G2_txAsyncDataWrite => fiber_data32write_S(2),
+		G2_txAsyncFifoFull => fiber_data32fifofull_S(2),
+		G2_rxAsyncData => fiber_data32in_S(2),
+		G2_rxAsyncDataRead => fiber_data32read_S(2),
+		G2_rxAsyncDataOverflow => open,
+		G2_rxAsyncDataPresent => fiber_data32present_S(2),
+		G2_txLocked => fiber_txlocked_S(2),
+		G2_rxLocked => fiber_rxlocked_S(2),
+		G2_error => fiber_rxerror_S(2),
+		G2_TX_DLM => DLM_to_bottom_S(2),
+		G2_TX_DLM_WORD => DLM_WORD_to_bottom_S(2),
+		G2_RX_DLM => DLM_from_bottom_S(2),
+		G2_RX_DLM_WORD => DLM_WORD_from_bottom_S(2),
+		G2_LOS => fmc_sfp_los(1),
+		G2_txP => open, -- X0Y14_TX_P_OPAD, 
+		G2_txN => open, -- X0Y14_TX_N_OPAD, 
+		G2_rxP => '0', -- X0Y14_RX_P_IPAD, 
+		G2_rxN => '0', -- X0Y14_RX_N_IPAD, 
+
+		G3_txAsyncData => fiber_data32out_S(3),
+		G3_txAsyncDataWrite => fiber_data32write_S(3),
+		G3_txAsyncFifoFull => fiber_data32fifofull_S(3),
+		G3_rxAsyncData => fiber_data32in_S(3),
+		G3_rxAsyncDataRead => fiber_data32read_S(3),
+		G3_rxAsyncDataOverflow => open,
+		G3_rxAsyncDataPresent => fiber_data32present_S(3),
+		G3_txLocked => fiber_txlocked_S(3),
+		G3_rxLocked => fiber_rxlocked_S(3),
+		G3_error => fiber_rxerror_S(3),
+		G3_TX_DLM => DLM_to_bottom_S(3),
+		G3_TX_DLM_WORD => DLM_WORD_to_bottom_S(3),
+		G3_RX_DLM => DLM_from_bottom_S(3),
+		G3_RX_DLM_WORD => DLM_WORD_from_bottom_S(3),
+		G3_LOS => fmc_sfp_los(0),
+		G3_txP => open, -- X0Y15_TX_P_OPAD, 
+		G3_txN => open, -- X0Y15_TX_N_OPAD, 
+		G3_rxP => '0', -- X0Y15_RX_P_IPAD, 
+		G3_rxN => '0', -- X0Y15_RX_N_IPAD, 
+
+		LEDs_link_ok => open,
+		LEDs_rx => open,
+		LEDs_tx => open,
+ 		GT0_QPLLOUTCLK_IN => gt0_qplloutclk_S,
+		GT0_QPLLOUTREFCLK_IN => gt0_qplloutrefclk_S,
+
+		testPin => open,
+		testword0 => open,
+		testword0clock => open
+	);
+
+ibufds_instq2_clk1 : IBUFDS_GTE2 port map(
+	O => q2_clk1_gtrefclk_S,
+	ODIV2 => open,
+	CEB => '0',
+	I => SMA_MGT_REFCLK_P,
+	IB => SMA_MGT_REFCLK_N);
+	
+ibufds_instq3_clk0 : IBUFDS_GTE2 port map(
+	O => q3_clk0_gtrefclk_S,
+	ODIV2 => open,
+	CEB => '0',
+	I => Q3_CLK0_MGTREFCLK_P_IPAD,
+	IB => Q3_CLK0_MGTREFCLK_N_IPAD);
+	
+	
+THE_SODA_INPUT: DC_SODAserdesWrapper port map(
+		refClk => '0',
+		refClk_P => q2_clk1_gtrefclk_S,
+		refClk_N => q3_clk0_gtrefclk_S,
+		sysClk => clk_100_i,
+		asyncclk => clk_100_i,
+		gtpReset => reset_i, -- SODA_reset_S,
+		disable_GTX_reset => '0',
+		
+		txData => (others => '0'),
+		txCharIsK => '0',
+		txP => X0Y15_TX_P_OPAD,
+		txN => X0Y15_TX_N_OPAD,
+		txUsrClk => open,
+		txLocked => open,
+		
+		rxData => open,
+		rxCharIsK => open,
+		rxNotInTable => open,
+		rxP => X0Y15_RX_P_IPAD,
+		rxN => X0Y15_RX_N_IPAD,
+		rxUsrClk => open,
+		rxUsrClkdiv2 => open,
+		rxLocked => open,
+		GT0_QPLLOUTCLK_OUT => gt0_qplloutclk_S,
+		GT0_QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_S,
+		resetDone => open
+	);
+
+
+	
+fmc_led(0) <= fmc_sfp_los(3);
+fmc_led(1) <= fmc_sfp_los(2);
+fmc_led(2) <= fmc_sfp_los(1);
+fmc_led(3) <= fmc_sfp_los(0);
+
+THE_SODA_HUB: soda_hub 
+	port map(
+		SYSCLK => clk_100_i,
+		SODACLK => clk_SODA200_i,
+		RESET => SODA_reset_S,
+		CLEAR => '0',
+		CLK_EN => '1',
+		
+	--	SINGLE DUBPLEX UP-LINK TO THE TOP
+		RXUP_DLM_IN => DLM_hub2uplink_S,
+		RXUP_DLM_WORD_IN => DLM_WORD_hub2uplink_S,
+		TXUP_DLM_OUT => DLM_to_uplink_S, 
+		TXUP_DLM_WORD_OUT => DLM_WORD_to_uplink_S,
+		TXUP_DLM_PREVIEW_OUT => open,
+		UPLINK_PHASE_IN => c_PHASE_H,
+
+	--	MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
+		RXDN_DLM_IN => DLM_from_bottom_S,
+		RXDN_DLM_WORD_IN => DLM_WORD_from_bottom_S,
+		TXDN_DLM_OUT => DLM_to_bottom_S,
+		TXDN_DLM_WORD_OUT => DLM_WORD_to_bottom_S,
+		TXDN_DLM_PREVIEW_OUT => open,
+		DNLINK_PHASE_IN => (others => c_PHASE_H),
+
+		SODA_DATA_IN => soda_data_in,
+		SODA_DATA_OUT => soda_data_out,
+		SODA_ADDR_IN => soda_addr,
+		SODA_READ_IN => soda_read_en,
+		SODA_WRITE_IN => soda_write_en,
+		SODA_ACK_OUT => soda_ack,
+		LEDS_OUT => open,
+		LINK_DEBUG_IN => (others => '0')
+	);
+		
+THE_JITTERCLEANER1: jittercleaner_200M port map(
+	clk_in => jittercleaner_clock_in_S,
+	clk_out => jittercleaner_clock_out0_S,
+	reset => jittercleaner_reset_S,
+	locked => open);
+THE_JITTERCLEANER2: pll_in200_out200 port map(
+	clk_in1 => jittercleaner_clock_out0_S,
+	clk_out1 => jittercleaner_clock_out_S,
+	reset => jittercleaner_reset_S,
+	locked => jittercleaner_locked_S);
+
+-- THE_JITTERCLEANER: jittercleaner_200M port map(
+	-- clk_in => jittercleaner_clock_in_S,
+	-- clk_out => jittercleaner_clock_out_S,
+	-- reset => jittercleaner_reset_S,
+	-- locked => jittercleaner_locked_S);
+-- THE_JITTERCLEANER: BUFG
+  -- port map
+   -- (O   => jittercleaner_clock_out_S,
+    -- I   => jittercleaner_clock_in_S);
+-- jittercleaner_locked_S <= '1';
+	
+gen_externalsoda: if EXTERNAL_SODA=true generate
+	process(clk_SODA200_i)
+		begin
+			if rising_edge(clk_SODA200_i) then 
+				DLM_hub2uplink_S <= '0';
+				if DLM_from_uplink_S='1' then
+					DLM_hub2uplink_S <= '1';
+					DLM_WORD_hub2uplink_S <= DLM_WORD_from_uplink_S;
+				end if;
+			end if;
+		end process;
+	USER_SMA_CLOCK_S <= clk_SODA200_i;
+	clk_SODA200_i <= jittercleaner_clock_out_S;  -- clk_200_i; --//try SODA_IN_rxUsrClk_S; --// jittercleaner_clock_out_S; 
+	jittercleaner_reset_S <= not SODA_IN_rxLocked_S;
+	SODA_reset_S <= not jittercleaner_locked_S;
+	jittercleaner_clock_in_S <= SODA_IN_rxUsrClk_S; -- clk_200_i; --//try ; 
+end generate;
+		
+gen_internalsoda: if EXTERNAL_SODA=false generate
+	DLM_hub2uplink_S <= DLM_source2hub_S;
+	DLM_WORD_hub2uplink_S <= DLM_WORD_source2hub_S;
+	clk_SODA200_i <= txpll_clocks_S(0);
+	USER_SMA_CLOCK_S <= clk_200_i;
+	SODA_reset_S <= reset_i;
+	jittercleaner_reset_S <= reset_i;
+	jittercleaner_clock_in_S <= clk_200_i;
+end generate;
+
+
+SMA_GPIO_output : OBUFDS
+	generic map(
+		IOSTANDARD => "LVDS_25")
+	port map( 
+		O  => USER_SMA_GPIO_P,
+		OB => USER_SMA_GPIO_N,
+		I  => superburst_update_S);
+---------------------------------------------------------------------------
+-- The Soda Central
+---------------------------------------------------------------------------         
+soda_source1: soda_source 
+	port map(
+		SYSCLK => clk_100_i,
+		SODACLK => clk_SODA200_i,
+		RESET => reset_i,
+		--Internal Connection
+		SODA_BURST_PULSE_IN	=> SODA_burst_pulse_S,
+		SODA_CYCLE_IN => soda_40mhz_cycle_S,
+
+		RX_DLM_WORD_IN => DLM_WORD_to_uplink_S,
+		RX_DLM_IN => DLM_to_uplink_S,
+		TX_DLM_OUT => DLM_source2hub_S,
+		TX_DLM_WORD_OUT => DLM_WORD_source2hub_S,
+
+		TX_DLM_PREVIEW_OUT => open,
+		LINK_PHASE_IN => c_PHASE_H,
+
+		SODA_DATA_IN => sodasrc_data_in,
+		SODA_DATA_OUT => sodasrc_data_out,
+		SODA_ADDR_IN => sodasrc_addr,
+		SODA_READ_IN => sodasrc_read_en,
+		SODA_WRITE_IN => sodasrc_write_en,
+		SODA_ACK_OUT => sodasrc_ack,
+
+		LEDS_OUT => open
+	);
+
+---------------------------------------------------------------------------
+-- Burst- and 40MHz cycle generator
+---------------------------------------------------------------------------         
+THE_SOB_SOURCE : soda_start_of_burst_control
+	generic map(
+		CLOCK_PERIOD => cSODA_CLOCK_PERIOD,	-- clock-period in ns
+		CYCLE_PERIOD => cSODA_CYCLE_PERIOD,	-- cycle-period in ns
+		BURST_PERIOD => cBURST_PERIOD			-- burst-period in ns
+		)
+	port map(
+		SODA_CLK => clk_SODA200_i,
+		RESET => reset_i,
+		SODA_BURST_PULSE_OUT => SODA_burst_pulse_S,
+		SODA_40MHZ_CYCLE_OUT =>	soda_40mhz_cycle_S
+	);
+
+XADC_GPIO_0 <= DLM_hub2uplink_S; -- debug_clkdiv2_1;
+XADC_GPIO_1 <= DLM_to_bottom_S(0); --debug_clkdiv2_2;
+XADC_GPIO_2 <= debug_clkdiv2_3;
+XADC_GPIO_3 <= debug_clkdiv2_4;  
+ 
+process(clk_SODA200_i)
+   begin
+       if rising_edge(clk_SODA200_i) then 
+           debug_clkdiv2_1 <= not debug_clkdiv2_1;
+       end if;
+end process;
+process(clk_200_i)
+   begin
+       if rising_edge(clk_200_i) then 
+           debug_clkdiv2_2 <= not debug_clkdiv2_2;
+       end if;
+end process;
+process(USER_SMA_CLOCK_S)
+   begin
+       if rising_edge(USER_SMA_CLOCK_S) then 
+           debug_clkdiv2_3 <= not debug_clkdiv2_3;
+       end if;
+end process;
+process(SODA_IN_rxUsrClk_S)
+   begin
+       if rising_edge(SODA_IN_rxUsrClk_S) then 
+           debug_clkdiv2_4 <= not debug_clkdiv2_4;
+       end if;
+end process;
+
+
+-- LED_LINKOK(1) <= not LEDs_link_ok_i(0);
+-- LED_LINKOK(6) <= not LEDs_link_ok_i(1);
+-- LED_LINKOK(2) <= not LEDs_link_ok_i(2);
+-- LED_LINKOK(4) <= not LEDs_link_ok_i(3);
+-- LED_LINKOK(3) <= '1';
+-- LED_LINKOK(5) <= '1';
+
+-- LED_RX(1) <= not LEDs_rx_i(0);
+-- LED_RX(6) <= not LEDs_rx_i(1);
+-- LED_RX(2) <= not LEDs_rx_i(2);
+-- LED_RX(4) <= not LEDs_rx_i(3);
+-- LED_RX(3) <= '1';
+-- LED_RX(5) <= '1';
+
+-- LED_TX(1) <= not LEDs_tx_i(0);
+-- LED_TX(6) <= not LEDs_tx_i(1);
+-- LED_TX(2) <= not LEDs_tx_i(2);
+-- LED_TX(4) <= not LEDs_tx_i(3);
+-- LED_TX(3) <= '1';
+-- LED_TX(5) <= '1';
+
+
+---------------------------------------------------------------------------
+-- LED
+---------------------------------------------------------------------------
+-- LED_GREEN  <= not med_stat_op(9);
+-- LED_ORANGE <= not med_stat_op(10);
+-- LED_RED    <= not time_counter(26);
+-- LED_YELLOW <= not med_stat_op(11);
+
+
+---------------------------------------------------------------------------
+-- Test Connector
+---------------------------------------------------------------------------    
+  --TEST_LINE(7 downto 0)   <= med_data_in(7 downto 0);
+  --TEST_LINE(8)            <= med_dataready_in;
+  --TEST_LINE(9)            <= med_dataready_out;
+  --TEST_LINE(10)           <= stat_reg_strobe(0);
+  --TEST_LINE(15 downto 11) <= (others => '0');
+
+
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+	fmc_user_switch <= (others => 'Z');
+--	fmc_sfp_tx_fault
+	fmc_sfp_tx_disable <= (others => '0');
+	fmc_sfp_rate_sel <= (others => '0');
+--	fmc_sfp_mod_def0 <= (others => '0');
+--	Q3_CLK0_MGTREFCLK_P_IPAD   : in std_logic;
+--	Q3_CLK0_MGTREFCLK_N_IPAD   : in std_logic;
+
+process(PACKETOUT_clock)
+   begin
+       if rising_edge(PACKETOUT_clock) then 
+			if data64b_muxed_write='1' then
+				if data64b_muxed_first='1' then
+					data64b_count <= (others => '0');
+				else
+					data64b_count <= data64b_count+1;
+				end if;
+			end if;
+       end if;
+end process;
+
+end architecture;
\ No newline at end of file
diff --git a/data_concentrator/sources/cluster/CN_checkcluster.vhd b/data_concentrator/sources/cluster/CN_checkcluster.vhd
new file mode 100644
index 0000000..562e70e
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_checkcluster.vhd
@@ -0,0 +1,251 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   07-03-2016
+-- Module Name:   CN_checkcluster
+-- Description:   Checks cluster packets for errors
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_checkcluster
+-- Checks cluster packets for errors in hitdata, time consistancy
+-- It can check packets with or without the first Panda header word that contains the last packet bit, packet number and packet size, 
+--
+-- The 64 bits packets, according to SODAnet specs:
+-- 64bits word0:  (depending on headerword0)
+--        bit63      = last-packet flag
+--        bit62..48  = packet number
+--        bit47..32  = data size in bytes
+--        bit31..0   = Not used (same as HADES)
+-- 64bits word1:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+--    for cluster data
+-- 64bits word2, clusterresults
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..30  = diameter
+--        bit29..20  = Y position, multiplied by 2
+--        bit19..10  = X position, multiplied by 2
+--        bit9..0    = number of hits in cluster
+-- 64bits word3..word3+nrofhits : pulse data
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+
+--
+-- Library
+--
+-- 
+-- Inputs:
+--     clock : clock for data input
+--     reset : reset
+--     headerword0 : '0' : no Panda header word expected, '1' : Panda header word expected with last packet bit, packet number and packet size
+--     data_in : 64bits data
+--     data_in_first : indicates that 64bits data is first in packet
+--     data_in_last : indicates that 64bits data is last in packet
+--     data_in_error : indicates that 64bits data ontains an error
+--     data_in_write : write signal for 64bits data
+--      
+-- 
+-- Outputs:
+--     dataerror : error in data: wrong header, missing first or last bit, superburst number error or time error
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity CN_checkcluster is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		headerword0             : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_error           : in std_logic;
+		data_in_write           : in std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end CN_checkcluster;
+
+
+architecture behaviour of CN_checkcluster is
+
+signal data_in_busy_S     : std_logic := '0';
+signal dataerror1_S       : std_logic := '0';
+signal dataerror2_S       : std_logic := '0';
+signal wave_S             : std_logic := '0';
+signal prev_time_S        : std_logic_vector(23 downto 0) := (others => '0');
+signal superburst_S       : std_logic_vector(30 downto 0) := (others => '0');
+signal prev_superburst_S  : std_logic_vector(30 downto 0) := (others => '0');
+signal packetsize_S       : integer range 0 to 65535 := 0;
+signal data_in_count_S    : integer range 0 to 65535 := 0;
+signal prev_data_S        : std_logic_vector(63 downto 0) := (others => '0');
+
+signal data_in_second_S   : std_logic := '0';
+signal newcluster_S       : std_logic := '0';
+signal last_received_S    : std_logic := '1';
+signal hits_index_S       : integer range 0 to 1023 := 0;
+signal nrofhits_S         : integer range 0 to 1023 := 0;
+
+begin
+
+dataerror <= '1' when ((dataerror1_S='1') or (dataerror2_S='1')) and (prev_superburst_S>1) else '0';
+
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		dataerror1_S <= '0';
+		if reset='1' then
+			data_in_busy_S <= '0';
+		else
+			if (data_in_write='1') then
+				if (data_in_first='1') and (data_in_last='1') and (headerword0='1') then
+					dataerror1_S <= '1';
+				elsif (data_in_first='1') and (data_in_last='1') and (headerword0='0') then
+					data_in_busy_S <= '0';
+				elsif data_in_first='1' then
+					if data_in_busy_S='1' then
+						dataerror1_S <= '1';
+					end if;
+					data_in_busy_S <= '1';
+				elsif data_in_last='1' then
+					if data_in_busy_S='0' then
+						dataerror1_S <= '1';
+					end if;
+					data_in_busy_S <= '0';
+				else
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0);
+begin
+	if (rising_edge(clock)) then
+		dataerror2_S <= '0';
+		if reset='1' then
+			newcluster_S <= '0';
+			last_received_S <= '1';
+			data_in_second_S <= '0';
+			prev_superburst_S <= (others => '0');
+		else	
+			if (data_in_write='1') then
+				if prev_data_S=data_in then
+					dataerror2_S <= '1';
+				end if;
+				prev_data_S <= data_in;
+				if (data_in_first='1') or (data_in_second_S='1') then
+					if (headerword0='1') and (data_in_second_S='0') then
+						data_in_count_S <= 1;
+						if data_in(63)='0' then
+							dataerror2_S <= '1';
+						end if;
+						packetsize_S <= conv_integer(unsigned(data_in(47 downto 32)));
+						if data_in(31 downto 0)/=x"00000000" then
+							dataerror2_S <= '1';
+						end if;
+						if last_received_S='0' then
+							dataerror2_S <= '1';
+						end if;
+						if data_in_last='1' then 
+							dataerror2_S <= '1';
+							newcluster_S <= '0';
+							last_received_S <= '1';
+							data_in_second_S <= '0';
+						else
+							newcluster_S <= '1';
+							last_received_S <= '0';
+							data_in_second_S <= '1';
+						end if;
+					else
+						if (headerword0='1') then
+							data_in_count_S <= data_in_count_S+1;
+						else
+							data_in_count_S <= 1;
+						end if;
+						data_in_second_S <= '0';
+						if last_received_S='0' then
+							dataerror2_S <= '1';
+						end if;
+						if superburst_S+1/=data_in(30 downto 0) then
+							dataerror2_S <= '1';
+						end if;
+						superburst_S <= data_in(30 downto 0);
+						if data_in_last='1' then -- empty superburst
+							newcluster_S <= '0';
+							last_received_S <= '1';
+							if (headerword0='1') and (packetsize_S/=(data_in_count_S+1)*8) then
+								dataerror2_S <= '1';
+							end if;
+						else
+							newcluster_S <= '1';
+							last_received_S <= '0';
+						end if;
+					end if;
+				else
+					if (data_in_last='1')  then
+						if (headerword0='1') and (packetsize_S/=(data_in_count_S+1)*8) then
+							dataerror2_S <= '1';
+						end if;
+					end if;
+					data_in_count_S <= data_in_count_S+1;
+					if newcluster_S='1' then
+						if last_received_S='1' then
+							dataerror2_S <= '1';
+						end if;
+						newcluster_S <= '0';
+						nrofhits_S <= conv_integer(unsigned(data_in(9 downto 0)));
+						if conv_integer(unsigned(data_in(9 downto 0)))>0 then
+						end if;
+						hits_index_S <= 0;
+						if data_in_last='1' then
+							last_received_S <= '1';
+						end if;
+						if (prev_superburst_S>superburst_S) or ((prev_superburst_S=superburst_S) and (prev_time_S>data_in(63 downto 40))) then
+							dataerror2_S <= '1';
+						end if;
+						prev_superburst_S <= superburst_S;
+						prev_time_S <= data_in(63 downto 40);
+					else
+						if (data_in_last='1') and (hits_index_S+1/=nrofhits_S) then
+							dataerror2_S <= '1';
+						end if;
+						if (last_received_S='1') and (hits_index_S+1/=nrofhits_S) then
+							dataerror2_S <= '1';
+						end if;
+						if hits_index_S>=nrofhits_S-1 then
+							newcluster_S <= '1';
+						end if;
+						hits_index_S <= hits_index_S+1;
+						if data_in_last='1' then
+							last_received_S <= '1';
+						end if;
+					end if;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+
+end behaviour;
+
diff --git a/data_concentrator/sources/cluster/CN_checkdata.vhd b/data_concentrator/sources/cluster/CN_checkdata.vhd
new file mode 100644
index 0000000..4240a29
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_checkdata.vhd
@@ -0,0 +1,247 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   07-03-2016
+-- Module Name:   CN_checkdata
+-- Description:   Checks data packets for errors
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_checkdata
+-- Checks data packets for errors in hitdata, time consistancy or waveforms.
+--
+-- The 64 bits packets, according to SODAnet specs:
+-- 64bits word1:   
+--        bit63      = last-packet flag
+--        bit62..48  = packet number
+--        bit47..32  = data size in bytes
+--        bit31..0   = Not used (same as HADES)
+-- 64bits word2:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+--    for pulse data
+-- 64bits word3 and further, for each pulse:   
+--        bit63..51  = offset in respect to superburst
+--        bit52..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+--    for wave data
+-- 64bits word3:
+--        bit63..56  = status byte
+--        bit55..40  = adc channel
+--        bit39..32  = number of samples in wave
+--        bit15..0  = timestamp in respect to superburst of the first sample in the waveform
+-- 64bits word4 and further : 
+--        bit63..48  = next_adcsample(15:0)
+--        bit47..32  = next_adcsample(15:0)
+--        bit31..16  = next_adcsample(15:0)
+--        bit15..0   = next_adcsample(15:0)
+--
+-- Library
+--
+-- 
+-- Inputs:
+--     clock : clock for data input
+--     reset : reset
+--     data_in : 64bits data
+--     data_in_first : indicates that 64bits data is first in packet
+--     data_in_last : indicates that 64bits data is last in packet
+--     data_in_error : indicates that 64bits data ontains an error
+--     data_in_write : write signal for 64bits data
+--      
+-- 
+-- Outputs:
+--     dataerror : error in data: wrong header, missing first or last bit
+--     timeerror : superburst number error or time error
+--     waveerror : error in waveform 
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity CN_checkdata is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_error           : in std_logic;
+		data_in_write           : in std_logic;
+		dataerror               : out std_logic;
+		timeerror               : out std_logic;
+		waveerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end CN_checkdata;
+
+
+architecture behaviour of CN_checkdata is
+
+signal data_in_busy_S     : std_logic;
+signal dataerror1_S       : std_logic;
+signal dataerror2_S       : std_logic;
+signal timeerror1_S       : std_logic;
+signal timeerror2_S       : std_logic;
+signal timeerror3_S       : std_logic;
+signal waveerror1_S       : std_logic;
+signal superbursterror_S  : std_logic;
+signal wave_S             : std_logic;
+signal data_prev_S        : std_logic_vector(63 downto 0) := (others => '0');
+signal time_S             : std_logic_vector(23 downto 0);
+signal superburst_S       : std_logic_vector(30 downto 0);
+signal prev_superburst_S  : std_logic_vector(30 downto 0);
+signal prev_wavetime_S    : std_logic_vector(15 downto 0);
+signal wavesuperburst_S   : std_logic_vector(30 downto 0);
+signal prev_wavesuperburst_S: std_logic_vector(30 downto 0);
+signal packetsize_S       : integer range 0 to 65535;
+signal data_in_count_S    : integer range 0 to 65535;
+
+begin
+
+dataerror <= '1' when ((dataerror1_S='1') or (dataerror2_S='1')) and (prev_superburst_S>1) else '0';
+timeerror <= '1' when ((timeerror1_S='1') or (timeerror2_S='1') or (timeerror3_S='1')) and (prev_superburst_S>1) else '0';
+waveerror <= waveerror1_S;
+
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		dataerror1_S <= '0';
+		if reset='1' then
+			data_in_busy_S <= '0';
+		else
+			if (data_in_write='1') then
+				if (data_in_first='1') and (data_in_last='1') then
+					dataerror1_S <= '1';
+				elsif data_in_first='1' then
+					if data_in_busy_S='1' then
+						dataerror1_S <= '1';
+					end if;
+					data_in_busy_S <= '1';
+				elsif data_in_last='1' then
+					if data_in_busy_S='0' then
+						dataerror1_S <= '1';
+					end if;
+					data_in_busy_S <= '0';
+				else
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0);
+begin
+	if (rising_edge(clock)) then
+		dataerror2_S <= '0';
+		timeerror1_S <= '0';
+		timeerror2_S <= '0';
+		timeerror3_S <= '0';
+		waveerror1_S <= '0';
+		superbursterror_S <= '0';
+		if reset='1' then
+			prev_superburst_S <= (others => '0');
+			prev_wavesuperburst_S <= (others => '0');
+		else	
+			if (data_in_write='1') then
+				if data_prev_S=data_in then
+					dataerror2_S <= '1';
+				end if;
+				data_prev_S <= data_in;
+				if data_in_first='1' then
+					data_in_count_S<=1;
+					if data_in(63)='0' then
+						dataerror2_S <= '1';
+					end if;
+					packetsize_S <= conv_integer(unsigned(data_in(47 downto 32)));
+					if data_in(31 downto 0)/=x"00000000" then
+						dataerror2_S <= '1';
+					end if;
+				else
+					if data_in_last='1' then
+						if packetsize_S/=(data_in_count_S+1)*8 then
+							dataerror2_S <= '1';
+						end if;
+					end if;
+					if data_in_count_S=1 then
+						if data_in(47 downto 32)/=x"5555" then
+							dataerror2_S <= '1';
+						end if;
+						superburst_S <= data_in(30 downto 0);
+						if data_in(63)='1' then
+							wave_S <= '1';
+							wavesuperburst_S <= data_in(30 downto 0);
+						else
+							wave_S <= '0';
+							prev_superburst_V := prev_superburst_S+1;
+							if data_in(30 downto 0)/=prev_superburst_V then
+								timeerror1_S <= '1';
+							end if;
+							if data_in(30 downto 0)<prev_superburst_S then
+								superbursterror_S <= '1';
+							end if;
+							prev_superburst_S <= data_in(30 downto 0);
+							time_S <= (others => '0');
+						end if;
+					elsif (data_in_count_S=2) and (wave_S='1') then
+						if data_in(39 downto 32)<x"02" then
+							waveerror1_S <= '1';
+						end if;
+						if (wavesuperburst_S<prev_wavesuperburst_S) then
+							timeerror3_S <= '1';
+						elsif (wavesuperburst_S=prev_wavesuperburst_S) then
+							if data_in(15 downto 0)<prev_wavetime_S then
+								timeerror3_S <= '1';
+							end if;
+						end if;
+						data_in_count_S <= 3;
+						prev_wavetime_S <= data_in(15 downto 0);
+						prev_wavesuperburst_S <= wavesuperburst_S;
+					else
+						if wave_S='1' then
+						else
+							if data_in(63 downto 40) < time_S(23 downto 0) then
+								timeerror2_S <= '1';
+							end if;
+							time_S <= data_in(63 downto 40);
+						end if;
+					end if;
+					data_in_count_S <= data_in_count_S+1;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+testword0(63 downto 0) <= data_in;
+testword0(64) <= data_in_first;
+testword0(65) <= data_in_last;
+testword0(66) <= data_in_write;
+testword0(67) <= wave_S;
+testword0(68) <= data_in_busy_S;
+testword0(69) <= dataerror1_S;
+testword0(70) <= dataerror2_S;
+testword0(71) <= timeerror1_S;
+testword0(72) <= timeerror2_S;
+testword0(73) <= timeerror3_S;
+testword0(74) <= waveerror1_S;
+testword0(75) <= '1' when prev_superburst_S>1 else '0';
+
+
+end behaviour;
+
diff --git a/data_concentrator/sources/cluster/CN_cluster_XY_LUT.vhd b/data_concentrator/sources/cluster/CN_cluster_XY_LUT.vhd
new file mode 100644
index 0000000..290036f
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_cluster_XY_LUT.vhd
@@ -0,0 +1,4174 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   31-01-2012
+-- Module Name:   CN_cluster_XY_LUT
+-- Description:   Look Up Table for XY position and on-edge indication
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- CN_cluster_XY_LUT
+--		Look Up Table to translate ADC channel number to X and Y position of the crystal.
+--      Contains also bit that indicates if the crystal is on the edge of the region.
+--
+-- generics
+--		
+-- inputs
+--		clock : clock 
+--		write_enable : write to memory
+--		write_address : address to write to
+--		data_in : data to write into memory
+--		read_address : address to read from
+--			  
+-- outputs
+--		data_out : data from memory
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+entity CN_cluster_XY_LUT is
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(15 downto 0);
+		data_in                 : in std_logic_vector(16 downto 0);
+		read_address            : in std_logic_vector(15 downto 0);
+		data_out                : out std_logic_vector(16 downto 0)
+	);
+end CN_cluster_XY_LUT;
+
+architecture behavioral of CN_cluster_XY_LUT is
+	type mem_type is array (0 to 2**16-1) of std_logic;
+	signal mem_S : mem_type := (others => '1');
+--	type mem_type is array (0 to 2**16-1) of std_logic_vector (16 downto 0);
+--	signal mem_S : mem_type := 
+--('1'&x"0000",'1'&x"0001",'1'&x"0002",'1'&x"0003",'1'&x"0004",'1'&x"0005",'1'&x"0006",'1'&x"0007",'1'&x"0008",'1'&x"0009",'1'&x"000A",'1'&x"000B",'1'&x"000C",'1'&x"000D",'1'&x"000E",'1'&x"000F",
+--'1'&x"0010",'1'&x"0011",'1'&x"0012",'1'&x"0013",'1'&x"0014",'1'&x"0015",'1'&x"0016",'1'&x"0017",'1'&x"0018",'1'&x"0019",'1'&x"001A",'1'&x"001B",'1'&x"001C",'1'&x"001D",'1'&x"001E",'1'&x"001F",
+--'1'&x"0020",'1'&x"0021",'1'&x"0022",'1'&x"0023",'1'&x"0024",'1'&x"0025",'1'&x"0026",'1'&x"0027",'1'&x"0028",'1'&x"0029",'1'&x"002A",'1'&x"002B",'1'&x"002C",'1'&x"002D",'1'&x"002E",'1'&x"002F",
+--'1'&x"0030",'1'&x"0031",'1'&x"0032",'1'&x"0033",'1'&x"0034",'1'&x"0035",'1'&x"0036",'1'&x"0037",'1'&x"0038",'1'&x"0039",'1'&x"003A",'1'&x"003B",'1'&x"003C",'1'&x"003D",'1'&x"003E",'1'&x"003F",
+--'1'&x"0040",'1'&x"0041",'1'&x"0042",'1'&x"0043",'1'&x"0044",'1'&x"0045",'1'&x"0046",'1'&x"0047",'1'&x"0048",'1'&x"0049",'1'&x"004A",'1'&x"004B",'1'&x"004C",'1'&x"004D",'1'&x"004E",'1'&x"004F",
+--'1'&x"0050",'1'&x"0051",'1'&x"0052",'1'&x"0053",'1'&x"0054",'1'&x"0055",'1'&x"0056",'1'&x"0057",'1'&x"0058",'1'&x"0059",'1'&x"005A",'1'&x"005B",'1'&x"005C",'1'&x"005D",'1'&x"005E",'1'&x"005F",
+--'1'&x"0060",'1'&x"0061",'1'&x"0062",'1'&x"0063",'1'&x"0064",'1'&x"0065",'1'&x"0066",'1'&x"0067",'1'&x"0068",'1'&x"0069",'1'&x"006A",'1'&x"006B",'1'&x"006C",'1'&x"006D",'1'&x"006E",'1'&x"006F",
+--'1'&x"0070",'1'&x"0071",'1'&x"0072",'1'&x"0073",'1'&x"0074",'1'&x"0075",'1'&x"0076",'1'&x"0077",'1'&x"0078",'1'&x"0079",'1'&x"007A",'1'&x"007B",'1'&x"007C",'1'&x"007D",'1'&x"007E",'1'&x"007F",
+--'1'&x"0080",'1'&x"0081",'1'&x"0082",'1'&x"0083",'1'&x"0084",'1'&x"0085",'1'&x"0086",'1'&x"0087",'1'&x"0088",'1'&x"0089",'1'&x"008A",'1'&x"008B",'1'&x"008C",'1'&x"008D",'1'&x"008E",'1'&x"008F",
+--'1'&x"0090",'1'&x"0091",'1'&x"0092",'1'&x"0093",'1'&x"0094",'1'&x"0095",'1'&x"0096",'1'&x"0097",'1'&x"0098",'1'&x"0099",'1'&x"009A",'1'&x"009B",'1'&x"009C",'1'&x"009D",'1'&x"009E",'1'&x"009F",
+--'1'&x"00A0",'1'&x"00A1",'1'&x"00A2",'1'&x"00A3",'1'&x"00A4",'1'&x"00A5",'1'&x"00A6",'1'&x"00A7",'1'&x"00A8",'1'&x"00A9",'1'&x"00AA",'1'&x"00AB",'1'&x"00AC",'1'&x"00AD",'1'&x"00AE",'1'&x"00AF",
+--'1'&x"00B0",'1'&x"00B1",'1'&x"00B2",'1'&x"00B3",'1'&x"00B4",'1'&x"00B5",'1'&x"00B6",'1'&x"00B7",'1'&x"00B8",'1'&x"00B9",'1'&x"00BA",'1'&x"00BB",'1'&x"00BC",'1'&x"00BD",'1'&x"00BE",'1'&x"00BF",
+--'1'&x"00C0",'1'&x"00C1",'1'&x"00C2",'1'&x"00C3",'1'&x"00C4",'1'&x"00C5",'1'&x"00C6",'1'&x"00C7",'1'&x"00C8",'1'&x"00C9",'1'&x"00CA",'1'&x"00CB",'1'&x"00CC",'1'&x"00CD",'1'&x"00CE",'1'&x"00CF",
+--'1'&x"00D0",'1'&x"00D1",'1'&x"00D2",'1'&x"00D3",'1'&x"00D4",'1'&x"00D5",'1'&x"00D6",'1'&x"00D7",'1'&x"00D8",'1'&x"00D9",'1'&x"00DA",'1'&x"00DB",'1'&x"00DC",'1'&x"00DD",'1'&x"00DE",'1'&x"00DF",
+--'1'&x"00E0",'1'&x"00E1",'1'&x"00E2",'1'&x"00E3",'1'&x"00E4",'1'&x"00E5",'1'&x"00E6",'1'&x"00E7",'1'&x"00E8",'1'&x"00E9",'1'&x"00EA",'1'&x"00EB",'1'&x"00EC",'1'&x"00ED",'1'&x"00EE",'1'&x"00EF",
+--'1'&x"00F0",'1'&x"00F1",'1'&x"00F2",'1'&x"00F3",'1'&x"00F4",'1'&x"00F5",'1'&x"00F6",'1'&x"00F7",'1'&x"00F8",'1'&x"00F9",'1'&x"00FA",'1'&x"00FB",'1'&x"00FC",'1'&x"00FD",'1'&x"00FE",'1'&x"00FF",
+--'1'&x"0100",'1'&x"0101",'1'&x"0102",'1'&x"0103",'1'&x"0104",'1'&x"0105",'1'&x"0106",'1'&x"0107",'1'&x"0108",'1'&x"0109",'1'&x"010A",'1'&x"010B",'1'&x"010C",'1'&x"010D",'1'&x"010E",'1'&x"010F",
+--'1'&x"0110",'1'&x"0111",'1'&x"0112",'1'&x"0113",'1'&x"0114",'1'&x"0115",'1'&x"0116",'1'&x"0117",'1'&x"0118",'1'&x"0119",'1'&x"011A",'1'&x"011B",'1'&x"011C",'1'&x"011D",'1'&x"011E",'1'&x"011F",
+--'1'&x"0120",'1'&x"0121",'1'&x"0122",'1'&x"0123",'1'&x"0124",'1'&x"0125",'1'&x"0126",'1'&x"0127",'1'&x"0128",'1'&x"0129",'1'&x"012A",'1'&x"012B",'1'&x"012C",'1'&x"012D",'1'&x"012E",'1'&x"012F",
+--'1'&x"0130",'1'&x"0131",'1'&x"0132",'1'&x"0133",'1'&x"0134",'1'&x"0135",'1'&x"0136",'1'&x"0137",'1'&x"0138",'1'&x"0139",'1'&x"013A",'1'&x"013B",'1'&x"013C",'1'&x"013D",'1'&x"013E",'1'&x"013F",
+--'1'&x"0140",'1'&x"0141",'1'&x"0142",'1'&x"0143",'1'&x"0144",'1'&x"0145",'1'&x"0146",'1'&x"0147",'1'&x"0148",'1'&x"0149",'1'&x"014A",'1'&x"014B",'1'&x"014C",'1'&x"014D",'1'&x"014E",'1'&x"014F",
+--'1'&x"0150",'1'&x"0151",'1'&x"0152",'1'&x"0153",'1'&x"0154",'1'&x"0155",'1'&x"0156",'1'&x"0157",'1'&x"0158",'1'&x"0159",'1'&x"015A",'1'&x"015B",'1'&x"015C",'1'&x"015D",'1'&x"015E",'1'&x"015F",
+--'1'&x"0160",'1'&x"0161",'1'&x"0162",'1'&x"0163",'1'&x"0164",'1'&x"0165",'1'&x"0166",'1'&x"0167",'1'&x"0168",'1'&x"0169",'1'&x"016A",'1'&x"016B",'1'&x"016C",'1'&x"016D",'1'&x"016E",'1'&x"016F",
+--'1'&x"0170",'1'&x"0171",'1'&x"0172",'1'&x"0173",'1'&x"0174",'1'&x"0175",'1'&x"0176",'1'&x"0177",'1'&x"0178",'1'&x"0179",'1'&x"017A",'1'&x"017B",'1'&x"017C",'1'&x"017D",'1'&x"017E",'1'&x"017F",
+--'1'&x"0180",'1'&x"0181",'1'&x"0182",'1'&x"0183",'1'&x"0184",'1'&x"0185",'1'&x"0186",'1'&x"0187",'1'&x"0188",'1'&x"0189",'1'&x"018A",'1'&x"018B",'1'&x"018C",'1'&x"018D",'1'&x"018E",'1'&x"018F",
+--'1'&x"0190",'1'&x"0191",'1'&x"0192",'1'&x"0193",'1'&x"0194",'1'&x"0195",'1'&x"0196",'1'&x"0197",'1'&x"0198",'1'&x"0199",'1'&x"019A",'1'&x"019B",'1'&x"019C",'1'&x"019D",'1'&x"019E",'1'&x"019F",
+--'1'&x"01A0",'1'&x"01A1",'1'&x"01A2",'1'&x"01A3",'1'&x"01A4",'1'&x"01A5",'1'&x"01A6",'1'&x"01A7",'1'&x"01A8",'1'&x"01A9",'1'&x"01AA",'1'&x"01AB",'1'&x"01AC",'1'&x"01AD",'1'&x"01AE",'1'&x"01AF",
+--'1'&x"01B0",'1'&x"01B1",'1'&x"01B2",'1'&x"01B3",'1'&x"01B4",'1'&x"01B5",'1'&x"01B6",'1'&x"01B7",'1'&x"01B8",'1'&x"01B9",'1'&x"01BA",'1'&x"01BB",'1'&x"01BC",'1'&x"01BD",'1'&x"01BE",'1'&x"01BF",
+--'1'&x"01C0",'1'&x"01C1",'1'&x"01C2",'1'&x"01C3",'1'&x"01C4",'1'&x"01C5",'1'&x"01C6",'1'&x"01C7",'1'&x"01C8",'1'&x"01C9",'1'&x"01CA",'1'&x"01CB",'1'&x"01CC",'1'&x"01CD",'1'&x"01CE",'1'&x"01CF",
+--'1'&x"01D0",'1'&x"01D1",'1'&x"01D2",'1'&x"01D3",'1'&x"01D4",'1'&x"01D5",'1'&x"01D6",'1'&x"01D7",'1'&x"01D8",'1'&x"01D9",'1'&x"01DA",'1'&x"01DB",'1'&x"01DC",'1'&x"01DD",'1'&x"01DE",'1'&x"01DF",
+--'1'&x"01E0",'1'&x"01E1",'1'&x"01E2",'1'&x"01E3",'1'&x"01E4",'1'&x"01E5",'1'&x"01E6",'1'&x"01E7",'1'&x"01E8",'1'&x"01E9",'1'&x"01EA",'1'&x"01EB",'1'&x"01EC",'1'&x"01ED",'1'&x"01EE",'1'&x"01EF",
+--'1'&x"01F0",'1'&x"01F1",'1'&x"01F2",'1'&x"01F3",'1'&x"01F4",'1'&x"01F5",'1'&x"01F6",'1'&x"01F7",'1'&x"01F8",'1'&x"01F9",'1'&x"01FA",'1'&x"01FB",'1'&x"01FC",'1'&x"01FD",'1'&x"01FE",'1'&x"01FF",
+--'1'&x"0200",'1'&x"0201",'1'&x"0202",'1'&x"0203",'1'&x"0204",'1'&x"0205",'1'&x"0206",'1'&x"0207",'1'&x"0208",'1'&x"0209",'1'&x"020A",'1'&x"020B",'1'&x"020C",'1'&x"020D",'1'&x"020E",'1'&x"020F",
+--'1'&x"0210",'1'&x"0211",'1'&x"0212",'1'&x"0213",'1'&x"0214",'1'&x"0215",'1'&x"0216",'1'&x"0217",'1'&x"0218",'1'&x"0219",'1'&x"021A",'1'&x"021B",'1'&x"021C",'1'&x"021D",'1'&x"021E",'1'&x"021F",
+--'1'&x"0220",'1'&x"0221",'1'&x"0222",'1'&x"0223",'1'&x"0224",'1'&x"0225",'1'&x"0226",'1'&x"0227",'1'&x"0228",'1'&x"0229",'1'&x"022A",'1'&x"022B",'1'&x"022C",'1'&x"022D",'1'&x"022E",'1'&x"022F",
+--'1'&x"0230",'1'&x"0231",'1'&x"0232",'1'&x"0233",'1'&x"0234",'1'&x"0235",'1'&x"0236",'1'&x"0237",'1'&x"0238",'1'&x"0239",'1'&x"023A",'1'&x"023B",'1'&x"023C",'1'&x"023D",'1'&x"023E",'1'&x"023F",
+--'1'&x"0240",'1'&x"0241",'1'&x"0242",'1'&x"0243",'1'&x"0244",'1'&x"0245",'1'&x"0246",'1'&x"0247",'1'&x"0248",'1'&x"0249",'1'&x"024A",'1'&x"024B",'1'&x"024C",'1'&x"024D",'1'&x"024E",'1'&x"024F",
+--'1'&x"0250",'1'&x"0251",'1'&x"0252",'1'&x"0253",'1'&x"0254",'1'&x"0255",'1'&x"0256",'1'&x"0257",'1'&x"0258",'1'&x"0259",'1'&x"025A",'1'&x"025B",'1'&x"025C",'1'&x"025D",'1'&x"025E",'1'&x"025F",
+--'1'&x"0260",'1'&x"0261",'1'&x"0262",'1'&x"0263",'1'&x"0264",'1'&x"0265",'1'&x"0266",'1'&x"0267",'1'&x"0268",'1'&x"0269",'1'&x"026A",'1'&x"026B",'1'&x"026C",'1'&x"026D",'1'&x"026E",'1'&x"026F",
+--'1'&x"0270",'1'&x"0271",'1'&x"0272",'1'&x"0273",'1'&x"0274",'1'&x"0275",'1'&x"0276",'1'&x"0277",'1'&x"0278",'1'&x"0279",'1'&x"027A",'1'&x"027B",'1'&x"027C",'1'&x"027D",'1'&x"027E",'1'&x"027F",
+--'1'&x"0280",'1'&x"0281",'1'&x"0282",'1'&x"0283",'1'&x"0284",'1'&x"0285",'1'&x"0286",'1'&x"0287",'1'&x"0288",'1'&x"0289",'1'&x"028A",'1'&x"028B",'1'&x"028C",'1'&x"028D",'1'&x"028E",'1'&x"028F",
+--'1'&x"0290",'1'&x"0291",'1'&x"0292",'1'&x"0293",'1'&x"0294",'1'&x"0295",'1'&x"0296",'1'&x"0297",'1'&x"0298",'1'&x"0299",'1'&x"029A",'1'&x"029B",'1'&x"029C",'1'&x"029D",'1'&x"029E",'1'&x"029F",
+--'1'&x"02A0",'1'&x"02A1",'1'&x"02A2",'1'&x"02A3",'1'&x"02A4",'1'&x"02A5",'1'&x"02A6",'1'&x"02A7",'1'&x"02A8",'1'&x"02A9",'1'&x"02AA",'1'&x"02AB",'1'&x"02AC",'1'&x"02AD",'1'&x"02AE",'1'&x"02AF",
+--'1'&x"02B0",'1'&x"02B1",'1'&x"02B2",'1'&x"02B3",'1'&x"02B4",'1'&x"02B5",'1'&x"02B6",'1'&x"02B7",'1'&x"02B8",'1'&x"02B9",'1'&x"02BA",'1'&x"02BB",'1'&x"02BC",'1'&x"02BD",'1'&x"02BE",'1'&x"02BF",
+--'1'&x"02C0",'1'&x"02C1",'1'&x"02C2",'1'&x"02C3",'1'&x"02C4",'1'&x"02C5",'1'&x"02C6",'1'&x"02C7",'1'&x"02C8",'1'&x"02C9",'1'&x"02CA",'1'&x"02CB",'1'&x"02CC",'1'&x"02CD",'1'&x"02CE",'1'&x"02CF",
+--'1'&x"02D0",'1'&x"02D1",'1'&x"02D2",'1'&x"02D3",'1'&x"02D4",'1'&x"02D5",'1'&x"02D6",'1'&x"02D7",'1'&x"02D8",'1'&x"02D9",'1'&x"02DA",'1'&x"02DB",'1'&x"02DC",'1'&x"02DD",'1'&x"02DE",'1'&x"02DF",
+--'1'&x"02E0",'1'&x"02E1",'1'&x"02E2",'1'&x"02E3",'1'&x"02E4",'1'&x"02E5",'1'&x"02E6",'1'&x"02E7",'1'&x"02E8",'1'&x"02E9",'1'&x"02EA",'1'&x"02EB",'1'&x"02EC",'1'&x"02ED",'1'&x"02EE",'1'&x"02EF",
+--'1'&x"02F0",'1'&x"02F1",'1'&x"02F2",'1'&x"02F3",'1'&x"02F4",'1'&x"02F5",'1'&x"02F6",'1'&x"02F7",'1'&x"02F8",'1'&x"02F9",'1'&x"02FA",'1'&x"02FB",'1'&x"02FC",'1'&x"02FD",'1'&x"02FE",'1'&x"02FF",
+--'1'&x"0300",'1'&x"0301",'1'&x"0302",'1'&x"0303",'1'&x"0304",'1'&x"0305",'1'&x"0306",'1'&x"0307",'1'&x"0308",'1'&x"0309",'1'&x"030A",'1'&x"030B",'1'&x"030C",'1'&x"030D",'1'&x"030E",'1'&x"030F",
+--'1'&x"0310",'1'&x"0311",'1'&x"0312",'1'&x"0313",'1'&x"0314",'1'&x"0315",'1'&x"0316",'1'&x"0317",'1'&x"0318",'1'&x"0319",'1'&x"031A",'1'&x"031B",'1'&x"031C",'1'&x"031D",'1'&x"031E",'1'&x"031F",
+--'1'&x"0320",'1'&x"0321",'1'&x"0322",'1'&x"0323",'1'&x"0324",'1'&x"0325",'1'&x"0326",'1'&x"0327",'1'&x"0328",'1'&x"0329",'1'&x"032A",'1'&x"032B",'1'&x"032C",'1'&x"032D",'1'&x"032E",'1'&x"032F",
+--'1'&x"0330",'1'&x"0331",'1'&x"0332",'1'&x"0333",'1'&x"0334",'1'&x"0335",'1'&x"0336",'1'&x"0337",'1'&x"0338",'1'&x"0339",'1'&x"033A",'1'&x"033B",'1'&x"033C",'1'&x"033D",'1'&x"033E",'1'&x"033F",
+--'1'&x"0340",'1'&x"0341",'1'&x"0342",'1'&x"0343",'1'&x"0344",'1'&x"0345",'1'&x"0346",'1'&x"0347",'1'&x"0348",'1'&x"0349",'1'&x"034A",'1'&x"034B",'1'&x"034C",'1'&x"034D",'1'&x"034E",'1'&x"034F",
+--'1'&x"0350",'1'&x"0351",'1'&x"0352",'1'&x"0353",'1'&x"0354",'1'&x"0355",'1'&x"0356",'1'&x"0357",'1'&x"0358",'1'&x"0359",'1'&x"035A",'1'&x"035B",'1'&x"035C",'1'&x"035D",'1'&x"035E",'1'&x"035F",
+--'1'&x"0360",'1'&x"0361",'1'&x"0362",'1'&x"0363",'1'&x"0364",'1'&x"0365",'1'&x"0366",'1'&x"0367",'1'&x"0368",'1'&x"0369",'1'&x"036A",'1'&x"036B",'1'&x"036C",'1'&x"036D",'1'&x"036E",'1'&x"036F",
+--'1'&x"0370",'1'&x"0371",'1'&x"0372",'1'&x"0373",'1'&x"0374",'1'&x"0375",'1'&x"0376",'1'&x"0377",'1'&x"0378",'1'&x"0379",'1'&x"037A",'1'&x"037B",'1'&x"037C",'1'&x"037D",'1'&x"037E",'1'&x"037F",
+--'1'&x"0380",'1'&x"0381",'1'&x"0382",'1'&x"0383",'1'&x"0384",'1'&x"0385",'1'&x"0386",'1'&x"0387",'1'&x"0388",'1'&x"0389",'1'&x"038A",'1'&x"038B",'1'&x"038C",'1'&x"038D",'1'&x"038E",'1'&x"038F",
+--'1'&x"0390",'1'&x"0391",'1'&x"0392",'1'&x"0393",'1'&x"0394",'1'&x"0395",'1'&x"0396",'1'&x"0397",'1'&x"0398",'1'&x"0399",'1'&x"039A",'1'&x"039B",'1'&x"039C",'1'&x"039D",'1'&x"039E",'1'&x"039F",
+--'1'&x"03A0",'1'&x"03A1",'1'&x"03A2",'1'&x"03A3",'1'&x"03A4",'1'&x"03A5",'1'&x"03A6",'1'&x"03A7",'1'&x"03A8",'1'&x"03A9",'1'&x"03AA",'1'&x"03AB",'1'&x"03AC",'1'&x"03AD",'1'&x"03AE",'1'&x"03AF",
+--'1'&x"03B0",'1'&x"03B1",'1'&x"03B2",'1'&x"03B3",'1'&x"03B4",'1'&x"03B5",'1'&x"03B6",'1'&x"03B7",'1'&x"03B8",'1'&x"03B9",'1'&x"03BA",'1'&x"03BB",'1'&x"03BC",'1'&x"03BD",'1'&x"03BE",'1'&x"03BF",
+--'1'&x"03C0",'1'&x"03C1",'1'&x"03C2",'1'&x"03C3",'1'&x"03C4",'1'&x"03C5",'1'&x"03C6",'1'&x"03C7",'1'&x"03C8",'1'&x"03C9",'1'&x"03CA",'1'&x"03CB",'1'&x"03CC",'1'&x"03CD",'1'&x"03CE",'1'&x"03CF",
+--'1'&x"03D0",'1'&x"03D1",'1'&x"03D2",'1'&x"03D3",'1'&x"03D4",'1'&x"03D5",'1'&x"03D6",'1'&x"03D7",'1'&x"03D8",'1'&x"03D9",'1'&x"03DA",'1'&x"03DB",'1'&x"03DC",'1'&x"03DD",'1'&x"03DE",'1'&x"03DF",
+--'1'&x"03E0",'1'&x"03E1",'1'&x"03E2",'1'&x"03E3",'1'&x"03E4",'1'&x"03E5",'1'&x"03E6",'1'&x"03E7",'1'&x"03E8",'1'&x"03E9",'1'&x"03EA",'1'&x"03EB",'1'&x"03EC",'1'&x"03ED",'1'&x"03EE",'1'&x"03EF",
+--'1'&x"03F0",'1'&x"03F1",'1'&x"03F2",'1'&x"03F3",'1'&x"03F4",'1'&x"03F5",'1'&x"03F6",'1'&x"03F7",'1'&x"03F8",'1'&x"03F9",'1'&x"03FA",'1'&x"03FB",'1'&x"03FC",'1'&x"03FD",'1'&x"03FE",'1'&x"03FF",
+--'1'&x"0400",'1'&x"0401",'1'&x"0402",'1'&x"0403",'1'&x"0404",'1'&x"0405",'1'&x"0406",'1'&x"0407",'1'&x"0408",'1'&x"0409",'1'&x"040A",'1'&x"040B",'1'&x"040C",'1'&x"040D",'1'&x"040E",'1'&x"040F",
+--'1'&x"0410",'1'&x"0411",'1'&x"0412",'1'&x"0413",'1'&x"0414",'1'&x"0415",'1'&x"0416",'1'&x"0417",'1'&x"0418",'1'&x"0419",'1'&x"041A",'1'&x"041B",'1'&x"041C",'1'&x"041D",'1'&x"041E",'1'&x"041F",
+--'1'&x"0420",'1'&x"0421",'1'&x"0422",'1'&x"0423",'1'&x"0424",'1'&x"0425",'1'&x"0426",'1'&x"0427",'1'&x"0428",'1'&x"0429",'1'&x"042A",'1'&x"042B",'1'&x"042C",'1'&x"042D",'1'&x"042E",'1'&x"042F",
+--'1'&x"0430",'1'&x"0431",'1'&x"0432",'1'&x"0433",'1'&x"0434",'1'&x"0435",'1'&x"0436",'1'&x"0437",'1'&x"0438",'1'&x"0439",'1'&x"043A",'1'&x"043B",'1'&x"043C",'1'&x"043D",'1'&x"043E",'1'&x"043F",
+--'1'&x"0440",'1'&x"0441",'1'&x"0442",'1'&x"0443",'1'&x"0444",'1'&x"0445",'1'&x"0446",'1'&x"0447",'1'&x"0448",'1'&x"0449",'1'&x"044A",'1'&x"044B",'1'&x"044C",'1'&x"044D",'1'&x"044E",'1'&x"044F",
+--'1'&x"0450",'1'&x"0451",'1'&x"0452",'1'&x"0453",'1'&x"0454",'1'&x"0455",'1'&x"0456",'1'&x"0457",'1'&x"0458",'1'&x"0459",'1'&x"045A",'1'&x"045B",'1'&x"045C",'1'&x"045D",'1'&x"045E",'1'&x"045F",
+--'1'&x"0460",'1'&x"0461",'1'&x"0462",'1'&x"0463",'1'&x"0464",'1'&x"0465",'1'&x"0466",'1'&x"0467",'1'&x"0468",'1'&x"0469",'1'&x"046A",'1'&x"046B",'1'&x"046C",'1'&x"046D",'1'&x"046E",'1'&x"046F",
+--'1'&x"0470",'1'&x"0471",'1'&x"0472",'1'&x"0473",'1'&x"0474",'1'&x"0475",'1'&x"0476",'1'&x"0477",'1'&x"0478",'1'&x"0479",'1'&x"047A",'1'&x"047B",'1'&x"047C",'1'&x"047D",'1'&x"047E",'1'&x"047F",
+--'1'&x"0480",'1'&x"0481",'1'&x"0482",'1'&x"0483",'1'&x"0484",'1'&x"0485",'1'&x"0486",'1'&x"0487",'1'&x"0488",'1'&x"0489",'1'&x"048A",'1'&x"048B",'1'&x"048C",'1'&x"048D",'1'&x"048E",'1'&x"048F",
+--'1'&x"0490",'1'&x"0491",'1'&x"0492",'1'&x"0493",'1'&x"0494",'1'&x"0495",'1'&x"0496",'1'&x"0497",'1'&x"0498",'1'&x"0499",'1'&x"049A",'1'&x"049B",'1'&x"049C",'1'&x"049D",'1'&x"049E",'1'&x"049F",
+--'1'&x"04A0",'1'&x"04A1",'1'&x"04A2",'1'&x"04A3",'1'&x"04A4",'1'&x"04A5",'1'&x"04A6",'1'&x"04A7",'1'&x"04A8",'1'&x"04A9",'1'&x"04AA",'1'&x"04AB",'1'&x"04AC",'1'&x"04AD",'1'&x"04AE",'1'&x"04AF",
+--'1'&x"04B0",'1'&x"04B1",'1'&x"04B2",'1'&x"04B3",'1'&x"04B4",'1'&x"04B5",'1'&x"04B6",'1'&x"04B7",'1'&x"04B8",'1'&x"04B9",'1'&x"04BA",'1'&x"04BB",'1'&x"04BC",'1'&x"04BD",'1'&x"04BE",'1'&x"04BF",
+--'1'&x"04C0",'1'&x"04C1",'1'&x"04C2",'1'&x"04C3",'1'&x"04C4",'1'&x"04C5",'1'&x"04C6",'1'&x"04C7",'1'&x"04C8",'1'&x"04C9",'1'&x"04CA",'1'&x"04CB",'1'&x"04CC",'1'&x"04CD",'1'&x"04CE",'1'&x"04CF",
+--'1'&x"04D0",'1'&x"04D1",'1'&x"04D2",'1'&x"04D3",'1'&x"04D4",'1'&x"04D5",'1'&x"04D6",'1'&x"04D7",'1'&x"04D8",'1'&x"04D9",'1'&x"04DA",'1'&x"04DB",'1'&x"04DC",'1'&x"04DD",'1'&x"04DE",'1'&x"04DF",
+--'1'&x"04E0",'1'&x"04E1",'1'&x"04E2",'1'&x"04E3",'1'&x"04E4",'1'&x"04E5",'1'&x"04E6",'1'&x"04E7",'1'&x"04E8",'1'&x"04E9",'1'&x"04EA",'1'&x"04EB",'1'&x"04EC",'1'&x"04ED",'1'&x"04EE",'1'&x"04EF",
+--'1'&x"04F0",'1'&x"04F1",'1'&x"04F2",'1'&x"04F3",'1'&x"04F4",'1'&x"04F5",'1'&x"04F6",'1'&x"04F7",'1'&x"04F8",'1'&x"04F9",'1'&x"04FA",'1'&x"04FB",'1'&x"04FC",'1'&x"04FD",'1'&x"04FE",'1'&x"04FF",
+--'1'&x"0500",'1'&x"0501",'1'&x"0502",'1'&x"0503",'1'&x"0504",'1'&x"0505",'1'&x"0506",'1'&x"0507",'1'&x"0508",'1'&x"0509",'1'&x"050A",'1'&x"050B",'1'&x"050C",'1'&x"050D",'1'&x"050E",'1'&x"050F",
+--'1'&x"0510",'1'&x"0511",'1'&x"0512",'1'&x"0513",'1'&x"0514",'1'&x"0515",'1'&x"0516",'1'&x"0517",'1'&x"0518",'1'&x"0519",'1'&x"051A",'1'&x"051B",'1'&x"051C",'1'&x"051D",'1'&x"051E",'1'&x"051F",
+--'1'&x"0520",'1'&x"0521",'1'&x"0522",'1'&x"0523",'1'&x"0524",'1'&x"0525",'1'&x"0526",'1'&x"0527",'1'&x"0528",'1'&x"0529",'1'&x"052A",'1'&x"052B",'1'&x"052C",'1'&x"052D",'1'&x"052E",'1'&x"052F",
+--'1'&x"0530",'1'&x"0531",'1'&x"0532",'1'&x"0533",'1'&x"0534",'1'&x"0535",'1'&x"0536",'1'&x"0537",'1'&x"0538",'1'&x"0539",'1'&x"053A",'1'&x"053B",'1'&x"053C",'1'&x"053D",'1'&x"053E",'1'&x"053F",
+--'1'&x"0540",'1'&x"0541",'1'&x"0542",'1'&x"0543",'1'&x"0544",'1'&x"0545",'1'&x"0546",'1'&x"0547",'1'&x"0548",'1'&x"0549",'1'&x"054A",'1'&x"054B",'1'&x"054C",'1'&x"054D",'1'&x"054E",'1'&x"054F",
+--'1'&x"0550",'1'&x"0551",'1'&x"0552",'1'&x"0553",'1'&x"0554",'1'&x"0555",'1'&x"0556",'1'&x"0557",'1'&x"0558",'1'&x"0559",'1'&x"055A",'1'&x"055B",'1'&x"055C",'1'&x"055D",'1'&x"055E",'1'&x"055F",
+--'1'&x"0560",'1'&x"0561",'1'&x"0562",'1'&x"0563",'1'&x"0564",'1'&x"0565",'1'&x"0566",'1'&x"0567",'1'&x"0568",'1'&x"0569",'1'&x"056A",'1'&x"056B",'1'&x"056C",'1'&x"056D",'1'&x"056E",'1'&x"056F",
+--'1'&x"0570",'1'&x"0571",'1'&x"0572",'1'&x"0573",'1'&x"0574",'1'&x"0575",'1'&x"0576",'1'&x"0577",'1'&x"0578",'1'&x"0579",'1'&x"057A",'1'&x"057B",'1'&x"057C",'1'&x"057D",'1'&x"057E",'1'&x"057F",
+--'1'&x"0580",'1'&x"0581",'1'&x"0582",'1'&x"0583",'1'&x"0584",'1'&x"0585",'1'&x"0586",'1'&x"0587",'1'&x"0588",'1'&x"0589",'1'&x"058A",'1'&x"058B",'1'&x"058C",'1'&x"058D",'1'&x"058E",'1'&x"058F",
+--'1'&x"0590",'1'&x"0591",'1'&x"0592",'1'&x"0593",'1'&x"0594",'1'&x"0595",'1'&x"0596",'1'&x"0597",'1'&x"0598",'1'&x"0599",'1'&x"059A",'1'&x"059B",'1'&x"059C",'1'&x"059D",'1'&x"059E",'1'&x"059F",
+--'1'&x"05A0",'1'&x"05A1",'1'&x"05A2",'1'&x"05A3",'1'&x"05A4",'1'&x"05A5",'1'&x"05A6",'1'&x"05A7",'1'&x"05A8",'1'&x"05A9",'1'&x"05AA",'1'&x"05AB",'1'&x"05AC",'1'&x"05AD",'1'&x"05AE",'1'&x"05AF",
+--'1'&x"05B0",'1'&x"05B1",'1'&x"05B2",'1'&x"05B3",'1'&x"05B4",'1'&x"05B5",'1'&x"05B6",'1'&x"05B7",'1'&x"05B8",'1'&x"05B9",'1'&x"05BA",'1'&x"05BB",'1'&x"05BC",'1'&x"05BD",'1'&x"05BE",'1'&x"05BF",
+--'1'&x"05C0",'1'&x"05C1",'1'&x"05C2",'1'&x"05C3",'1'&x"05C4",'1'&x"05C5",'1'&x"05C6",'1'&x"05C7",'1'&x"05C8",'1'&x"05C9",'1'&x"05CA",'1'&x"05CB",'1'&x"05CC",'1'&x"05CD",'1'&x"05CE",'1'&x"05CF",
+--'1'&x"05D0",'1'&x"05D1",'1'&x"05D2",'1'&x"05D3",'1'&x"05D4",'1'&x"05D5",'1'&x"05D6",'1'&x"05D7",'1'&x"05D8",'1'&x"05D9",'1'&x"05DA",'1'&x"05DB",'1'&x"05DC",'1'&x"05DD",'1'&x"05DE",'1'&x"05DF",
+--'1'&x"05E0",'1'&x"05E1",'1'&x"05E2",'1'&x"05E3",'1'&x"05E4",'1'&x"05E5",'1'&x"05E6",'1'&x"05E7",'1'&x"05E8",'1'&x"05E9",'1'&x"05EA",'1'&x"05EB",'1'&x"05EC",'1'&x"05ED",'1'&x"05EE",'1'&x"05EF",
+--'1'&x"05F0",'1'&x"05F1",'1'&x"05F2",'1'&x"05F3",'1'&x"05F4",'1'&x"05F5",'1'&x"05F6",'1'&x"05F7",'1'&x"05F8",'1'&x"05F9",'1'&x"05FA",'1'&x"05FB",'1'&x"05FC",'1'&x"05FD",'1'&x"05FE",'1'&x"05FF",
+--'1'&x"0600",'1'&x"0601",'1'&x"0602",'1'&x"0603",'1'&x"0604",'1'&x"0605",'1'&x"0606",'1'&x"0607",'1'&x"0608",'1'&x"0609",'1'&x"060A",'1'&x"060B",'1'&x"060C",'1'&x"060D",'1'&x"060E",'1'&x"060F",
+--'1'&x"0610",'1'&x"0611",'1'&x"0612",'1'&x"0613",'1'&x"0614",'1'&x"0615",'1'&x"0616",'1'&x"0617",'1'&x"0618",'1'&x"0619",'1'&x"061A",'1'&x"061B",'1'&x"061C",'1'&x"061D",'1'&x"061E",'1'&x"061F",
+--'1'&x"0620",'1'&x"0621",'1'&x"0622",'1'&x"0623",'1'&x"0624",'1'&x"0625",'1'&x"0626",'1'&x"0627",'1'&x"0628",'1'&x"0629",'1'&x"062A",'1'&x"062B",'1'&x"062C",'1'&x"062D",'1'&x"062E",'1'&x"062F",
+--'1'&x"0630",'1'&x"0631",'1'&x"0632",'1'&x"0633",'1'&x"0634",'1'&x"0635",'1'&x"0636",'1'&x"0637",'1'&x"0638",'1'&x"0639",'1'&x"063A",'1'&x"063B",'1'&x"063C",'1'&x"063D",'1'&x"063E",'1'&x"063F",
+--'1'&x"0640",'1'&x"0641",'1'&x"0642",'1'&x"0643",'1'&x"0644",'1'&x"0645",'1'&x"0646",'1'&x"0647",'1'&x"0648",'1'&x"0649",'1'&x"064A",'1'&x"064B",'1'&x"064C",'1'&x"064D",'1'&x"064E",'1'&x"064F",
+--'1'&x"0650",'1'&x"0651",'1'&x"0652",'1'&x"0653",'1'&x"0654",'1'&x"0655",'1'&x"0656",'1'&x"0657",'1'&x"0658",'1'&x"0659",'1'&x"065A",'1'&x"065B",'1'&x"065C",'1'&x"065D",'1'&x"065E",'1'&x"065F",
+--'1'&x"0660",'1'&x"0661",'1'&x"0662",'1'&x"0663",'1'&x"0664",'1'&x"0665",'1'&x"0666",'1'&x"0667",'1'&x"0668",'1'&x"0669",'1'&x"066A",'1'&x"066B",'1'&x"066C",'1'&x"066D",'1'&x"066E",'1'&x"066F",
+--'1'&x"0670",'1'&x"0671",'1'&x"0672",'1'&x"0673",'1'&x"0674",'1'&x"0675",'1'&x"0676",'1'&x"0677",'1'&x"0678",'1'&x"0679",'1'&x"067A",'1'&x"067B",'1'&x"067C",'1'&x"067D",'1'&x"067E",'1'&x"067F",
+--'1'&x"0680",'1'&x"0681",'1'&x"0682",'1'&x"0683",'1'&x"0684",'1'&x"0685",'1'&x"0686",'1'&x"0687",'1'&x"0688",'1'&x"0689",'1'&x"068A",'1'&x"068B",'1'&x"068C",'1'&x"068D",'1'&x"068E",'1'&x"068F",
+--'1'&x"0690",'1'&x"0691",'1'&x"0692",'1'&x"0693",'1'&x"0694",'1'&x"0695",'1'&x"0696",'1'&x"0697",'1'&x"0698",'1'&x"0699",'1'&x"069A",'1'&x"069B",'1'&x"069C",'1'&x"069D",'1'&x"069E",'1'&x"069F",
+--'1'&x"06A0",'1'&x"06A1",'1'&x"06A2",'1'&x"06A3",'1'&x"06A4",'1'&x"06A5",'1'&x"06A6",'1'&x"06A7",'1'&x"06A8",'1'&x"06A9",'1'&x"06AA",'1'&x"06AB",'1'&x"06AC",'1'&x"06AD",'1'&x"06AE",'1'&x"06AF",
+--'1'&x"06B0",'1'&x"06B1",'1'&x"06B2",'1'&x"06B3",'1'&x"06B4",'1'&x"06B5",'1'&x"06B6",'1'&x"06B7",'1'&x"06B8",'1'&x"06B9",'1'&x"06BA",'1'&x"06BB",'1'&x"06BC",'1'&x"06BD",'1'&x"06BE",'1'&x"06BF",
+--'1'&x"06C0",'1'&x"06C1",'1'&x"06C2",'1'&x"06C3",'1'&x"06C4",'1'&x"06C5",'1'&x"06C6",'1'&x"06C7",'1'&x"06C8",'1'&x"06C9",'1'&x"06CA",'1'&x"06CB",'1'&x"06CC",'1'&x"06CD",'1'&x"06CE",'1'&x"06CF",
+--'1'&x"06D0",'1'&x"06D1",'1'&x"06D2",'1'&x"06D3",'1'&x"06D4",'1'&x"06D5",'1'&x"06D6",'1'&x"06D7",'1'&x"06D8",'1'&x"06D9",'1'&x"06DA",'1'&x"06DB",'1'&x"06DC",'1'&x"06DD",'1'&x"06DE",'1'&x"06DF",
+--'1'&x"06E0",'1'&x"06E1",'1'&x"06E2",'1'&x"06E3",'1'&x"06E4",'1'&x"06E5",'1'&x"06E6",'1'&x"06E7",'1'&x"06E8",'1'&x"06E9",'1'&x"06EA",'1'&x"06EB",'1'&x"06EC",'1'&x"06ED",'1'&x"06EE",'1'&x"06EF",
+--'1'&x"06F0",'1'&x"06F1",'1'&x"06F2",'1'&x"06F3",'1'&x"06F4",'1'&x"06F5",'1'&x"06F6",'1'&x"06F7",'1'&x"06F8",'1'&x"06F9",'1'&x"06FA",'1'&x"06FB",'1'&x"06FC",'1'&x"06FD",'1'&x"06FE",'1'&x"06FF",
+--'1'&x"0700",'1'&x"0701",'1'&x"0702",'1'&x"0703",'1'&x"0704",'1'&x"0705",'1'&x"0706",'1'&x"0707",'1'&x"0708",'1'&x"0709",'1'&x"070A",'1'&x"070B",'1'&x"070C",'1'&x"070D",'1'&x"070E",'1'&x"070F",
+--'1'&x"0710",'1'&x"0711",'1'&x"0712",'1'&x"0713",'1'&x"0714",'1'&x"0715",'1'&x"0716",'1'&x"0717",'1'&x"0718",'1'&x"0719",'1'&x"071A",'1'&x"071B",'1'&x"071C",'1'&x"071D",'1'&x"071E",'1'&x"071F",
+--'1'&x"0720",'1'&x"0721",'1'&x"0722",'1'&x"0723",'1'&x"0724",'1'&x"0725",'1'&x"0726",'1'&x"0727",'1'&x"0728",'1'&x"0729",'1'&x"072A",'1'&x"072B",'1'&x"072C",'1'&x"072D",'1'&x"072E",'1'&x"072F",
+--'1'&x"0730",'1'&x"0731",'1'&x"0732",'1'&x"0733",'1'&x"0734",'1'&x"0735",'1'&x"0736",'1'&x"0737",'1'&x"0738",'1'&x"0739",'1'&x"073A",'1'&x"073B",'1'&x"073C",'1'&x"073D",'1'&x"073E",'1'&x"073F",
+--'1'&x"0740",'1'&x"0741",'1'&x"0742",'1'&x"0743",'1'&x"0744",'1'&x"0745",'1'&x"0746",'1'&x"0747",'1'&x"0748",'1'&x"0749",'1'&x"074A",'1'&x"074B",'1'&x"074C",'1'&x"074D",'1'&x"074E",'1'&x"074F",
+--'1'&x"0750",'1'&x"0751",'1'&x"0752",'1'&x"0753",'1'&x"0754",'1'&x"0755",'1'&x"0756",'1'&x"0757",'1'&x"0758",'1'&x"0759",'1'&x"075A",'1'&x"075B",'1'&x"075C",'1'&x"075D",'1'&x"075E",'1'&x"075F",
+--'1'&x"0760",'1'&x"0761",'1'&x"0762",'1'&x"0763",'1'&x"0764",'1'&x"0765",'1'&x"0766",'1'&x"0767",'1'&x"0768",'1'&x"0769",'1'&x"076A",'1'&x"076B",'1'&x"076C",'1'&x"076D",'1'&x"076E",'1'&x"076F",
+--'1'&x"0770",'1'&x"0771",'1'&x"0772",'1'&x"0773",'1'&x"0774",'1'&x"0775",'1'&x"0776",'1'&x"0777",'1'&x"0778",'1'&x"0779",'1'&x"077A",'1'&x"077B",'1'&x"077C",'1'&x"077D",'1'&x"077E",'1'&x"077F",
+--'1'&x"0780",'1'&x"0781",'1'&x"0782",'1'&x"0783",'1'&x"0784",'1'&x"0785",'1'&x"0786",'1'&x"0787",'1'&x"0788",'1'&x"0789",'1'&x"078A",'1'&x"078B",'1'&x"078C",'1'&x"078D",'1'&x"078E",'1'&x"078F",
+--'1'&x"0790",'1'&x"0791",'1'&x"0792",'1'&x"0793",'1'&x"0794",'1'&x"0795",'1'&x"0796",'1'&x"0797",'1'&x"0798",'1'&x"0799",'1'&x"079A",'1'&x"079B",'1'&x"079C",'1'&x"079D",'1'&x"079E",'1'&x"079F",
+--'1'&x"07A0",'1'&x"07A1",'1'&x"07A2",'1'&x"07A3",'1'&x"07A4",'1'&x"07A5",'1'&x"07A6",'1'&x"07A7",'1'&x"07A8",'1'&x"07A9",'1'&x"07AA",'1'&x"07AB",'1'&x"07AC",'1'&x"07AD",'1'&x"07AE",'1'&x"07AF",
+--'1'&x"07B0",'1'&x"07B1",'1'&x"07B2",'1'&x"07B3",'1'&x"07B4",'1'&x"07B5",'1'&x"07B6",'1'&x"07B7",'1'&x"07B8",'1'&x"07B9",'1'&x"07BA",'1'&x"07BB",'1'&x"07BC",'1'&x"07BD",'1'&x"07BE",'1'&x"07BF",
+--'1'&x"07C0",'1'&x"07C1",'1'&x"07C2",'1'&x"07C3",'1'&x"07C4",'1'&x"07C5",'1'&x"07C6",'1'&x"07C7",'1'&x"07C8",'1'&x"07C9",'1'&x"07CA",'1'&x"07CB",'1'&x"07CC",'1'&x"07CD",'1'&x"07CE",'1'&x"07CF",
+--'1'&x"07D0",'1'&x"07D1",'1'&x"07D2",'1'&x"07D3",'1'&x"07D4",'1'&x"07D5",'1'&x"07D6",'1'&x"07D7",'1'&x"07D8",'1'&x"07D9",'1'&x"07DA",'1'&x"07DB",'1'&x"07DC",'1'&x"07DD",'1'&x"07DE",'1'&x"07DF",
+--'1'&x"07E0",'1'&x"07E1",'1'&x"07E2",'1'&x"07E3",'1'&x"07E4",'1'&x"07E5",'1'&x"07E6",'1'&x"07E7",'1'&x"07E8",'1'&x"07E9",'1'&x"07EA",'1'&x"07EB",'1'&x"07EC",'1'&x"07ED",'1'&x"07EE",'1'&x"07EF",
+--'1'&x"07F0",'1'&x"07F1",'1'&x"07F2",'1'&x"07F3",'1'&x"07F4",'1'&x"07F5",'1'&x"07F6",'1'&x"07F7",'1'&x"07F8",'1'&x"07F9",'1'&x"07FA",'1'&x"07FB",'1'&x"07FC",'1'&x"07FD",'1'&x"07FE",'1'&x"07FF",
+--'1'&x"0800",'1'&x"0801",'1'&x"0802",'1'&x"0803",'1'&x"0804",'1'&x"0805",'1'&x"0806",'1'&x"0807",'1'&x"0808",'1'&x"0809",'1'&x"080A",'1'&x"080B",'1'&x"080C",'1'&x"080D",'1'&x"080E",'1'&x"080F",
+--'1'&x"0810",'1'&x"0811",'1'&x"0812",'1'&x"0813",'1'&x"0814",'1'&x"0815",'1'&x"0816",'1'&x"0817",'1'&x"0818",'1'&x"0819",'1'&x"081A",'1'&x"081B",'1'&x"081C",'1'&x"081D",'1'&x"081E",'1'&x"081F",
+--'1'&x"0820",'1'&x"0821",'1'&x"0822",'1'&x"0823",'1'&x"0824",'1'&x"0825",'1'&x"0826",'1'&x"0827",'1'&x"0828",'1'&x"0829",'1'&x"082A",'1'&x"082B",'1'&x"082C",'1'&x"082D",'1'&x"082E",'1'&x"082F",
+--'1'&x"0830",'1'&x"0831",'1'&x"0832",'1'&x"0833",'1'&x"0834",'1'&x"0835",'1'&x"0836",'1'&x"0837",'1'&x"0838",'1'&x"0839",'1'&x"083A",'1'&x"083B",'1'&x"083C",'1'&x"083D",'1'&x"083E",'1'&x"083F",
+--'1'&x"0840",'1'&x"0841",'1'&x"0842",'1'&x"0843",'1'&x"0844",'1'&x"0845",'1'&x"0846",'1'&x"0847",'1'&x"0848",'1'&x"0849",'1'&x"084A",'1'&x"084B",'1'&x"084C",'1'&x"084D",'1'&x"084E",'1'&x"084F",
+--'1'&x"0850",'1'&x"0851",'1'&x"0852",'1'&x"0853",'1'&x"0854",'1'&x"0855",'1'&x"0856",'1'&x"0857",'1'&x"0858",'1'&x"0859",'1'&x"085A",'1'&x"085B",'1'&x"085C",'1'&x"085D",'1'&x"085E",'1'&x"085F",
+--'1'&x"0860",'1'&x"0861",'1'&x"0862",'1'&x"0863",'1'&x"0864",'1'&x"0865",'1'&x"0866",'1'&x"0867",'1'&x"0868",'1'&x"0869",'1'&x"086A",'1'&x"086B",'1'&x"086C",'1'&x"086D",'1'&x"086E",'1'&x"086F",
+--'1'&x"0870",'1'&x"0871",'1'&x"0872",'1'&x"0873",'1'&x"0874",'1'&x"0875",'1'&x"0876",'1'&x"0877",'1'&x"0878",'1'&x"0879",'1'&x"087A",'1'&x"087B",'1'&x"087C",'1'&x"087D",'1'&x"087E",'1'&x"087F",
+--'1'&x"0880",'1'&x"0881",'1'&x"0882",'1'&x"0883",'1'&x"0884",'1'&x"0885",'1'&x"0886",'1'&x"0887",'1'&x"0888",'1'&x"0889",'1'&x"088A",'1'&x"088B",'1'&x"088C",'1'&x"088D",'1'&x"088E",'1'&x"088F",
+--'1'&x"0890",'1'&x"0891",'1'&x"0892",'1'&x"0893",'1'&x"0894",'1'&x"0895",'1'&x"0896",'1'&x"0897",'1'&x"0898",'1'&x"0899",'1'&x"089A",'1'&x"089B",'1'&x"089C",'1'&x"089D",'1'&x"089E",'1'&x"089F",
+--'1'&x"08A0",'1'&x"08A1",'1'&x"08A2",'1'&x"08A3",'1'&x"08A4",'1'&x"08A5",'1'&x"08A6",'1'&x"08A7",'1'&x"08A8",'1'&x"08A9",'1'&x"08AA",'1'&x"08AB",'1'&x"08AC",'1'&x"08AD",'1'&x"08AE",'1'&x"08AF",
+--'1'&x"08B0",'1'&x"08B1",'1'&x"08B2",'1'&x"08B3",'1'&x"08B4",'1'&x"08B5",'1'&x"08B6",'1'&x"08B7",'1'&x"08B8",'1'&x"08B9",'1'&x"08BA",'1'&x"08BB",'1'&x"08BC",'1'&x"08BD",'1'&x"08BE",'1'&x"08BF",
+--'1'&x"08C0",'1'&x"08C1",'1'&x"08C2",'1'&x"08C3",'1'&x"08C4",'1'&x"08C5",'1'&x"08C6",'1'&x"08C7",'1'&x"08C8",'1'&x"08C9",'1'&x"08CA",'1'&x"08CB",'1'&x"08CC",'1'&x"08CD",'1'&x"08CE",'1'&x"08CF",
+--'1'&x"08D0",'1'&x"08D1",'1'&x"08D2",'1'&x"08D3",'1'&x"08D4",'1'&x"08D5",'1'&x"08D6",'1'&x"08D7",'1'&x"08D8",'1'&x"08D9",'1'&x"08DA",'1'&x"08DB",'1'&x"08DC",'1'&x"08DD",'1'&x"08DE",'1'&x"08DF",
+--'1'&x"08E0",'1'&x"08E1",'1'&x"08E2",'1'&x"08E3",'1'&x"08E4",'1'&x"08E5",'1'&x"08E6",'1'&x"08E7",'1'&x"08E8",'1'&x"08E9",'1'&x"08EA",'1'&x"08EB",'1'&x"08EC",'1'&x"08ED",'1'&x"08EE",'1'&x"08EF",
+--'1'&x"08F0",'1'&x"08F1",'1'&x"08F2",'1'&x"08F3",'1'&x"08F4",'1'&x"08F5",'1'&x"08F6",'1'&x"08F7",'1'&x"08F8",'1'&x"08F9",'1'&x"08FA",'1'&x"08FB",'1'&x"08FC",'1'&x"08FD",'1'&x"08FE",'1'&x"08FF",
+--'1'&x"0900",'1'&x"0901",'1'&x"0902",'1'&x"0903",'1'&x"0904",'1'&x"0905",'1'&x"0906",'1'&x"0907",'1'&x"0908",'1'&x"0909",'1'&x"090A",'1'&x"090B",'1'&x"090C",'1'&x"090D",'1'&x"090E",'1'&x"090F",
+--'1'&x"0910",'1'&x"0911",'1'&x"0912",'1'&x"0913",'1'&x"0914",'1'&x"0915",'1'&x"0916",'1'&x"0917",'1'&x"0918",'1'&x"0919",'1'&x"091A",'1'&x"091B",'1'&x"091C",'1'&x"091D",'1'&x"091E",'1'&x"091F",
+--'1'&x"0920",'1'&x"0921",'1'&x"0922",'1'&x"0923",'1'&x"0924",'1'&x"0925",'1'&x"0926",'1'&x"0927",'1'&x"0928",'1'&x"0929",'1'&x"092A",'1'&x"092B",'1'&x"092C",'1'&x"092D",'1'&x"092E",'1'&x"092F",
+--'1'&x"0930",'1'&x"0931",'1'&x"0932",'1'&x"0933",'1'&x"0934",'1'&x"0935",'1'&x"0936",'1'&x"0937",'1'&x"0938",'1'&x"0939",'1'&x"093A",'1'&x"093B",'1'&x"093C",'1'&x"093D",'1'&x"093E",'1'&x"093F",
+--'1'&x"0940",'1'&x"0941",'1'&x"0942",'1'&x"0943",'1'&x"0944",'1'&x"0945",'1'&x"0946",'1'&x"0947",'1'&x"0948",'1'&x"0949",'1'&x"094A",'1'&x"094B",'1'&x"094C",'1'&x"094D",'1'&x"094E",'1'&x"094F",
+--'1'&x"0950",'1'&x"0951",'1'&x"0952",'1'&x"0953",'1'&x"0954",'1'&x"0955",'1'&x"0956",'1'&x"0957",'1'&x"0958",'1'&x"0959",'1'&x"095A",'1'&x"095B",'1'&x"095C",'1'&x"095D",'1'&x"095E",'1'&x"095F",
+--'1'&x"0960",'1'&x"0961",'1'&x"0962",'1'&x"0963",'1'&x"0964",'1'&x"0965",'1'&x"0966",'1'&x"0967",'1'&x"0968",'1'&x"0969",'1'&x"096A",'1'&x"096B",'1'&x"096C",'1'&x"096D",'1'&x"096E",'1'&x"096F",
+--'1'&x"0970",'1'&x"0971",'1'&x"0972",'1'&x"0973",'1'&x"0974",'1'&x"0975",'1'&x"0976",'1'&x"0977",'1'&x"0978",'1'&x"0979",'1'&x"097A",'1'&x"097B",'1'&x"097C",'1'&x"097D",'1'&x"097E",'1'&x"097F",
+--'1'&x"0980",'1'&x"0981",'1'&x"0982",'1'&x"0983",'1'&x"0984",'1'&x"0985",'1'&x"0986",'1'&x"0987",'1'&x"0988",'1'&x"0989",'1'&x"098A",'1'&x"098B",'1'&x"098C",'1'&x"098D",'1'&x"098E",'1'&x"098F",
+--'1'&x"0990",'1'&x"0991",'1'&x"0992",'1'&x"0993",'1'&x"0994",'1'&x"0995",'1'&x"0996",'1'&x"0997",'1'&x"0998",'1'&x"0999",'1'&x"099A",'1'&x"099B",'1'&x"099C",'1'&x"099D",'1'&x"099E",'1'&x"099F",
+--'1'&x"09A0",'1'&x"09A1",'1'&x"09A2",'1'&x"09A3",'1'&x"09A4",'1'&x"09A5",'1'&x"09A6",'1'&x"09A7",'1'&x"09A8",'1'&x"09A9",'1'&x"09AA",'1'&x"09AB",'1'&x"09AC",'1'&x"09AD",'1'&x"09AE",'1'&x"09AF",
+--'1'&x"09B0",'1'&x"09B1",'1'&x"09B2",'1'&x"09B3",'1'&x"09B4",'1'&x"09B5",'1'&x"09B6",'1'&x"09B7",'1'&x"09B8",'1'&x"09B9",'1'&x"09BA",'1'&x"09BB",'1'&x"09BC",'1'&x"09BD",'1'&x"09BE",'1'&x"09BF",
+--'1'&x"09C0",'1'&x"09C1",'1'&x"09C2",'1'&x"09C3",'1'&x"09C4",'1'&x"09C5",'1'&x"09C6",'1'&x"09C7",'1'&x"09C8",'1'&x"09C9",'1'&x"09CA",'1'&x"09CB",'1'&x"09CC",'1'&x"09CD",'1'&x"09CE",'1'&x"09CF",
+--'1'&x"09D0",'1'&x"09D1",'1'&x"09D2",'1'&x"09D3",'1'&x"09D4",'1'&x"09D5",'1'&x"09D6",'1'&x"09D7",'1'&x"09D8",'1'&x"09D9",'1'&x"09DA",'1'&x"09DB",'1'&x"09DC",'1'&x"09DD",'1'&x"09DE",'1'&x"09DF",
+--'1'&x"09E0",'1'&x"09E1",'1'&x"09E2",'1'&x"09E3",'1'&x"09E4",'1'&x"09E5",'1'&x"09E6",'1'&x"09E7",'1'&x"09E8",'1'&x"09E9",'1'&x"09EA",'1'&x"09EB",'1'&x"09EC",'1'&x"09ED",'1'&x"09EE",'1'&x"09EF",
+--'1'&x"09F0",'1'&x"09F1",'1'&x"09F2",'1'&x"09F3",'1'&x"09F4",'1'&x"09F5",'1'&x"09F6",'1'&x"09F7",'1'&x"09F8",'1'&x"09F9",'1'&x"09FA",'1'&x"09FB",'1'&x"09FC",'1'&x"09FD",'1'&x"09FE",'1'&x"09FF",
+--'1'&x"0A00",'1'&x"0A01",'1'&x"0A02",'1'&x"0A03",'1'&x"0A04",'1'&x"0A05",'1'&x"0A06",'1'&x"0A07",'1'&x"0A08",'1'&x"0A09",'1'&x"0A0A",'1'&x"0A0B",'1'&x"0A0C",'1'&x"0A0D",'1'&x"0A0E",'1'&x"0A0F",
+--'1'&x"0A10",'1'&x"0A11",'1'&x"0A12",'1'&x"0A13",'1'&x"0A14",'1'&x"0A15",'1'&x"0A16",'1'&x"0A17",'1'&x"0A18",'1'&x"0A19",'1'&x"0A1A",'1'&x"0A1B",'1'&x"0A1C",'1'&x"0A1D",'1'&x"0A1E",'1'&x"0A1F",
+--'1'&x"0A20",'1'&x"0A21",'1'&x"0A22",'1'&x"0A23",'1'&x"0A24",'1'&x"0A25",'1'&x"0A26",'1'&x"0A27",'1'&x"0A28",'1'&x"0A29",'1'&x"0A2A",'1'&x"0A2B",'1'&x"0A2C",'1'&x"0A2D",'1'&x"0A2E",'1'&x"0A2F",
+--'1'&x"0A30",'1'&x"0A31",'1'&x"0A32",'1'&x"0A33",'1'&x"0A34",'1'&x"0A35",'1'&x"0A36",'1'&x"0A37",'1'&x"0A38",'1'&x"0A39",'1'&x"0A3A",'1'&x"0A3B",'1'&x"0A3C",'1'&x"0A3D",'1'&x"0A3E",'1'&x"0A3F",
+--'1'&x"0A40",'1'&x"0A41",'1'&x"0A42",'1'&x"0A43",'1'&x"0A44",'1'&x"0A45",'1'&x"0A46",'1'&x"0A47",'1'&x"0A48",'1'&x"0A49",'1'&x"0A4A",'1'&x"0A4B",'1'&x"0A4C",'1'&x"0A4D",'1'&x"0A4E",'1'&x"0A4F",
+--'1'&x"0A50",'1'&x"0A51",'1'&x"0A52",'1'&x"0A53",'1'&x"0A54",'1'&x"0A55",'1'&x"0A56",'1'&x"0A57",'1'&x"0A58",'1'&x"0A59",'1'&x"0A5A",'1'&x"0A5B",'1'&x"0A5C",'1'&x"0A5D",'1'&x"0A5E",'1'&x"0A5F",
+--'1'&x"0A60",'1'&x"0A61",'1'&x"0A62",'1'&x"0A63",'1'&x"0A64",'1'&x"0A65",'1'&x"0A66",'1'&x"0A67",'1'&x"0A68",'1'&x"0A69",'1'&x"0A6A",'1'&x"0A6B",'1'&x"0A6C",'1'&x"0A6D",'1'&x"0A6E",'1'&x"0A6F",
+--'1'&x"0A70",'1'&x"0A71",'1'&x"0A72",'1'&x"0A73",'1'&x"0A74",'1'&x"0A75",'1'&x"0A76",'1'&x"0A77",'1'&x"0A78",'1'&x"0A79",'1'&x"0A7A",'1'&x"0A7B",'1'&x"0A7C",'1'&x"0A7D",'1'&x"0A7E",'1'&x"0A7F",
+--'1'&x"0A80",'1'&x"0A81",'1'&x"0A82",'1'&x"0A83",'1'&x"0A84",'1'&x"0A85",'1'&x"0A86",'1'&x"0A87",'1'&x"0A88",'1'&x"0A89",'1'&x"0A8A",'1'&x"0A8B",'1'&x"0A8C",'1'&x"0A8D",'1'&x"0A8E",'1'&x"0A8F",
+--'1'&x"0A90",'1'&x"0A91",'1'&x"0A92",'1'&x"0A93",'1'&x"0A94",'1'&x"0A95",'1'&x"0A96",'1'&x"0A97",'1'&x"0A98",'1'&x"0A99",'1'&x"0A9A",'1'&x"0A9B",'1'&x"0A9C",'1'&x"0A9D",'1'&x"0A9E",'1'&x"0A9F",
+--'1'&x"0AA0",'1'&x"0AA1",'1'&x"0AA2",'1'&x"0AA3",'1'&x"0AA4",'1'&x"0AA5",'1'&x"0AA6",'1'&x"0AA7",'1'&x"0AA8",'1'&x"0AA9",'1'&x"0AAA",'1'&x"0AAB",'1'&x"0AAC",'1'&x"0AAD",'1'&x"0AAE",'1'&x"0AAF",
+--'1'&x"0AB0",'1'&x"0AB1",'1'&x"0AB2",'1'&x"0AB3",'1'&x"0AB4",'1'&x"0AB5",'1'&x"0AB6",'1'&x"0AB7",'1'&x"0AB8",'1'&x"0AB9",'1'&x"0ABA",'1'&x"0ABB",'1'&x"0ABC",'1'&x"0ABD",'1'&x"0ABE",'1'&x"0ABF",
+--'1'&x"0AC0",'1'&x"0AC1",'1'&x"0AC2",'1'&x"0AC3",'1'&x"0AC4",'1'&x"0AC5",'1'&x"0AC6",'1'&x"0AC7",'1'&x"0AC8",'1'&x"0AC9",'1'&x"0ACA",'1'&x"0ACB",'1'&x"0ACC",'1'&x"0ACD",'1'&x"0ACE",'1'&x"0ACF",
+--'1'&x"0AD0",'1'&x"0AD1",'1'&x"0AD2",'1'&x"0AD3",'1'&x"0AD4",'1'&x"0AD5",'1'&x"0AD6",'1'&x"0AD7",'1'&x"0AD8",'1'&x"0AD9",'1'&x"0ADA",'1'&x"0ADB",'1'&x"0ADC",'1'&x"0ADD",'1'&x"0ADE",'1'&x"0ADF",
+--'1'&x"0AE0",'1'&x"0AE1",'1'&x"0AE2",'1'&x"0AE3",'1'&x"0AE4",'1'&x"0AE5",'1'&x"0AE6",'1'&x"0AE7",'1'&x"0AE8",'1'&x"0AE9",'1'&x"0AEA",'1'&x"0AEB",'1'&x"0AEC",'1'&x"0AED",'1'&x"0AEE",'1'&x"0AEF",
+--'1'&x"0AF0",'1'&x"0AF1",'1'&x"0AF2",'1'&x"0AF3",'1'&x"0AF4",'1'&x"0AF5",'1'&x"0AF6",'1'&x"0AF7",'1'&x"0AF8",'1'&x"0AF9",'1'&x"0AFA",'1'&x"0AFB",'1'&x"0AFC",'1'&x"0AFD",'1'&x"0AFE",'1'&x"0AFF",
+--'1'&x"0B00",'1'&x"0B01",'1'&x"0B02",'1'&x"0B03",'1'&x"0B04",'1'&x"0B05",'1'&x"0B06",'1'&x"0B07",'1'&x"0B08",'1'&x"0B09",'1'&x"0B0A",'1'&x"0B0B",'1'&x"0B0C",'1'&x"0B0D",'1'&x"0B0E",'1'&x"0B0F",
+--'1'&x"0B10",'1'&x"0B11",'1'&x"0B12",'1'&x"0B13",'1'&x"0B14",'1'&x"0B15",'1'&x"0B16",'1'&x"0B17",'1'&x"0B18",'1'&x"0B19",'1'&x"0B1A",'1'&x"0B1B",'1'&x"0B1C",'1'&x"0B1D",'1'&x"0B1E",'1'&x"0B1F",
+--'1'&x"0B20",'1'&x"0B21",'1'&x"0B22",'1'&x"0B23",'1'&x"0B24",'1'&x"0B25",'1'&x"0B26",'1'&x"0B27",'1'&x"0B28",'1'&x"0B29",'1'&x"0B2A",'1'&x"0B2B",'1'&x"0B2C",'1'&x"0B2D",'1'&x"0B2E",'1'&x"0B2F",
+--'1'&x"0B30",'1'&x"0B31",'1'&x"0B32",'1'&x"0B33",'1'&x"0B34",'1'&x"0B35",'1'&x"0B36",'1'&x"0B37",'1'&x"0B38",'1'&x"0B39",'1'&x"0B3A",'1'&x"0B3B",'1'&x"0B3C",'1'&x"0B3D",'1'&x"0B3E",'1'&x"0B3F",
+--'1'&x"0B40",'1'&x"0B41",'1'&x"0B42",'1'&x"0B43",'1'&x"0B44",'1'&x"0B45",'1'&x"0B46",'1'&x"0B47",'1'&x"0B48",'1'&x"0B49",'1'&x"0B4A",'1'&x"0B4B",'1'&x"0B4C",'1'&x"0B4D",'1'&x"0B4E",'1'&x"0B4F",
+--'1'&x"0B50",'1'&x"0B51",'1'&x"0B52",'1'&x"0B53",'1'&x"0B54",'1'&x"0B55",'1'&x"0B56",'1'&x"0B57",'1'&x"0B58",'1'&x"0B59",'1'&x"0B5A",'1'&x"0B5B",'1'&x"0B5C",'1'&x"0B5D",'1'&x"0B5E",'1'&x"0B5F",
+--'1'&x"0B60",'1'&x"0B61",'1'&x"0B62",'1'&x"0B63",'1'&x"0B64",'1'&x"0B65",'1'&x"0B66",'1'&x"0B67",'1'&x"0B68",'1'&x"0B69",'1'&x"0B6A",'1'&x"0B6B",'1'&x"0B6C",'1'&x"0B6D",'1'&x"0B6E",'1'&x"0B6F",
+--'1'&x"0B70",'1'&x"0B71",'1'&x"0B72",'1'&x"0B73",'1'&x"0B74",'1'&x"0B75",'1'&x"0B76",'1'&x"0B77",'1'&x"0B78",'1'&x"0B79",'1'&x"0B7A",'1'&x"0B7B",'1'&x"0B7C",'1'&x"0B7D",'1'&x"0B7E",'1'&x"0B7F",
+--'1'&x"0B80",'1'&x"0B81",'1'&x"0B82",'1'&x"0B83",'1'&x"0B84",'1'&x"0B85",'1'&x"0B86",'1'&x"0B87",'1'&x"0B88",'1'&x"0B89",'1'&x"0B8A",'1'&x"0B8B",'1'&x"0B8C",'1'&x"0B8D",'1'&x"0B8E",'1'&x"0B8F",
+--'1'&x"0B90",'1'&x"0B91",'1'&x"0B92",'1'&x"0B93",'1'&x"0B94",'1'&x"0B95",'1'&x"0B96",'1'&x"0B97",'1'&x"0B98",'1'&x"0B99",'1'&x"0B9A",'1'&x"0B9B",'1'&x"0B9C",'1'&x"0B9D",'1'&x"0B9E",'1'&x"0B9F",
+--'1'&x"0BA0",'1'&x"0BA1",'1'&x"0BA2",'1'&x"0BA3",'1'&x"0BA4",'1'&x"0BA5",'1'&x"0BA6",'1'&x"0BA7",'1'&x"0BA8",'1'&x"0BA9",'1'&x"0BAA",'1'&x"0BAB",'1'&x"0BAC",'1'&x"0BAD",'1'&x"0BAE",'1'&x"0BAF",
+--'1'&x"0BB0",'1'&x"0BB1",'1'&x"0BB2",'1'&x"0BB3",'1'&x"0BB4",'1'&x"0BB5",'1'&x"0BB6",'1'&x"0BB7",'1'&x"0BB8",'1'&x"0BB9",'1'&x"0BBA",'1'&x"0BBB",'1'&x"0BBC",'1'&x"0BBD",'1'&x"0BBE",'1'&x"0BBF",
+--'1'&x"0BC0",'1'&x"0BC1",'1'&x"0BC2",'1'&x"0BC3",'1'&x"0BC4",'1'&x"0BC5",'1'&x"0BC6",'1'&x"0BC7",'1'&x"0BC8",'1'&x"0BC9",'1'&x"0BCA",'1'&x"0BCB",'1'&x"0BCC",'1'&x"0BCD",'1'&x"0BCE",'1'&x"0BCF",
+--'1'&x"0BD0",'1'&x"0BD1",'1'&x"0BD2",'1'&x"0BD3",'1'&x"0BD4",'1'&x"0BD5",'1'&x"0BD6",'1'&x"0BD7",'1'&x"0BD8",'1'&x"0BD9",'1'&x"0BDA",'1'&x"0BDB",'1'&x"0BDC",'1'&x"0BDD",'1'&x"0BDE",'1'&x"0BDF",
+--'1'&x"0BE0",'1'&x"0BE1",'1'&x"0BE2",'1'&x"0BE3",'1'&x"0BE4",'1'&x"0BE5",'1'&x"0BE6",'1'&x"0BE7",'1'&x"0BE8",'1'&x"0BE9",'1'&x"0BEA",'1'&x"0BEB",'1'&x"0BEC",'1'&x"0BED",'1'&x"0BEE",'1'&x"0BEF",
+--'1'&x"0BF0",'1'&x"0BF1",'1'&x"0BF2",'1'&x"0BF3",'1'&x"0BF4",'1'&x"0BF5",'1'&x"0BF6",'1'&x"0BF7",'1'&x"0BF8",'1'&x"0BF9",'1'&x"0BFA",'1'&x"0BFB",'1'&x"0BFC",'1'&x"0BFD",'1'&x"0BFE",'1'&x"0BFF",
+--'1'&x"0C00",'1'&x"0C01",'1'&x"0C02",'1'&x"0C03",'1'&x"0C04",'1'&x"0C05",'1'&x"0C06",'1'&x"0C07",'1'&x"0C08",'1'&x"0C09",'1'&x"0C0A",'1'&x"0C0B",'1'&x"0C0C",'1'&x"0C0D",'1'&x"0C0E",'1'&x"0C0F",
+--'1'&x"0C10",'1'&x"0C11",'1'&x"0C12",'1'&x"0C13",'1'&x"0C14",'1'&x"0C15",'1'&x"0C16",'1'&x"0C17",'1'&x"0C18",'1'&x"0C19",'1'&x"0C1A",'1'&x"0C1B",'1'&x"0C1C",'1'&x"0C1D",'1'&x"0C1E",'1'&x"0C1F",
+--'1'&x"0C20",'1'&x"0C21",'1'&x"0C22",'1'&x"0C23",'1'&x"0C24",'1'&x"0C25",'1'&x"0C26",'1'&x"0C27",'1'&x"0C28",'1'&x"0C29",'1'&x"0C2A",'1'&x"0C2B",'1'&x"0C2C",'1'&x"0C2D",'1'&x"0C2E",'1'&x"0C2F",
+--'1'&x"0C30",'1'&x"0C31",'1'&x"0C32",'1'&x"0C33",'1'&x"0C34",'1'&x"0C35",'1'&x"0C36",'1'&x"0C37",'1'&x"0C38",'1'&x"0C39",'1'&x"0C3A",'1'&x"0C3B",'1'&x"0C3C",'1'&x"0C3D",'1'&x"0C3E",'1'&x"0C3F",
+--'1'&x"0C40",'1'&x"0C41",'1'&x"0C42",'1'&x"0C43",'1'&x"0C44",'1'&x"0C45",'1'&x"0C46",'1'&x"0C47",'1'&x"0C48",'1'&x"0C49",'1'&x"0C4A",'1'&x"0C4B",'1'&x"0C4C",'1'&x"0C4D",'1'&x"0C4E",'1'&x"0C4F",
+--'1'&x"0C50",'1'&x"0C51",'1'&x"0C52",'1'&x"0C53",'1'&x"0C54",'1'&x"0C55",'1'&x"0C56",'1'&x"0C57",'1'&x"0C58",'1'&x"0C59",'1'&x"0C5A",'1'&x"0C5B",'1'&x"0C5C",'1'&x"0C5D",'1'&x"0C5E",'1'&x"0C5F",
+--'1'&x"0C60",'1'&x"0C61",'1'&x"0C62",'1'&x"0C63",'1'&x"0C64",'1'&x"0C65",'1'&x"0C66",'1'&x"0C67",'1'&x"0C68",'1'&x"0C69",'1'&x"0C6A",'1'&x"0C6B",'1'&x"0C6C",'1'&x"0C6D",'1'&x"0C6E",'1'&x"0C6F",
+--'1'&x"0C70",'1'&x"0C71",'1'&x"0C72",'1'&x"0C73",'1'&x"0C74",'1'&x"0C75",'1'&x"0C76",'1'&x"0C77",'1'&x"0C78",'1'&x"0C79",'1'&x"0C7A",'1'&x"0C7B",'1'&x"0C7C",'1'&x"0C7D",'1'&x"0C7E",'1'&x"0C7F",
+--'1'&x"0C80",'1'&x"0C81",'1'&x"0C82",'1'&x"0C83",'1'&x"0C84",'1'&x"0C85",'1'&x"0C86",'1'&x"0C87",'1'&x"0C88",'1'&x"0C89",'1'&x"0C8A",'1'&x"0C8B",'1'&x"0C8C",'1'&x"0C8D",'1'&x"0C8E",'1'&x"0C8F",
+--'1'&x"0C90",'1'&x"0C91",'1'&x"0C92",'1'&x"0C93",'1'&x"0C94",'1'&x"0C95",'1'&x"0C96",'1'&x"0C97",'1'&x"0C98",'1'&x"0C99",'1'&x"0C9A",'1'&x"0C9B",'1'&x"0C9C",'1'&x"0C9D",'1'&x"0C9E",'1'&x"0C9F",
+--'1'&x"0CA0",'1'&x"0CA1",'1'&x"0CA2",'1'&x"0CA3",'1'&x"0CA4",'1'&x"0CA5",'1'&x"0CA6",'1'&x"0CA7",'1'&x"0CA8",'1'&x"0CA9",'1'&x"0CAA",'1'&x"0CAB",'1'&x"0CAC",'1'&x"0CAD",'1'&x"0CAE",'1'&x"0CAF",
+--'1'&x"0CB0",'1'&x"0CB1",'1'&x"0CB2",'1'&x"0CB3",'1'&x"0CB4",'1'&x"0CB5",'1'&x"0CB6",'1'&x"0CB7",'1'&x"0CB8",'1'&x"0CB9",'1'&x"0CBA",'1'&x"0CBB",'1'&x"0CBC",'1'&x"0CBD",'1'&x"0CBE",'1'&x"0CBF",
+--'1'&x"0CC0",'1'&x"0CC1",'1'&x"0CC2",'1'&x"0CC3",'1'&x"0CC4",'1'&x"0CC5",'1'&x"0CC6",'1'&x"0CC7",'1'&x"0CC8",'1'&x"0CC9",'1'&x"0CCA",'1'&x"0CCB",'1'&x"0CCC",'1'&x"0CCD",'1'&x"0CCE",'1'&x"0CCF",
+--'1'&x"0CD0",'1'&x"0CD1",'1'&x"0CD2",'1'&x"0CD3",'1'&x"0CD4",'1'&x"0CD5",'1'&x"0CD6",'1'&x"0CD7",'1'&x"0CD8",'1'&x"0CD9",'1'&x"0CDA",'1'&x"0CDB",'1'&x"0CDC",'1'&x"0CDD",'1'&x"0CDE",'1'&x"0CDF",
+--'1'&x"0CE0",'1'&x"0CE1",'1'&x"0CE2",'1'&x"0CE3",'1'&x"0CE4",'1'&x"0CE5",'1'&x"0CE6",'1'&x"0CE7",'1'&x"0CE8",'1'&x"0CE9",'1'&x"0CEA",'1'&x"0CEB",'1'&x"0CEC",'1'&x"0CED",'1'&x"0CEE",'1'&x"0CEF",
+--'1'&x"0CF0",'1'&x"0CF1",'1'&x"0CF2",'1'&x"0CF3",'1'&x"0CF4",'1'&x"0CF5",'1'&x"0CF6",'1'&x"0CF7",'1'&x"0CF8",'1'&x"0CF9",'1'&x"0CFA",'1'&x"0CFB",'1'&x"0CFC",'1'&x"0CFD",'1'&x"0CFE",'1'&x"0CFF",
+--'1'&x"0D00",'1'&x"0D01",'1'&x"0D02",'1'&x"0D03",'1'&x"0D04",'1'&x"0D05",'1'&x"0D06",'1'&x"0D07",'1'&x"0D08",'1'&x"0D09",'1'&x"0D0A",'1'&x"0D0B",'1'&x"0D0C",'1'&x"0D0D",'1'&x"0D0E",'1'&x"0D0F",
+--'1'&x"0D10",'1'&x"0D11",'1'&x"0D12",'1'&x"0D13",'1'&x"0D14",'1'&x"0D15",'1'&x"0D16",'1'&x"0D17",'1'&x"0D18",'1'&x"0D19",'1'&x"0D1A",'1'&x"0D1B",'1'&x"0D1C",'1'&x"0D1D",'1'&x"0D1E",'1'&x"0D1F",
+--'1'&x"0D20",'1'&x"0D21",'1'&x"0D22",'1'&x"0D23",'1'&x"0D24",'1'&x"0D25",'1'&x"0D26",'1'&x"0D27",'1'&x"0D28",'1'&x"0D29",'1'&x"0D2A",'1'&x"0D2B",'1'&x"0D2C",'1'&x"0D2D",'1'&x"0D2E",'1'&x"0D2F",
+--'1'&x"0D30",'1'&x"0D31",'1'&x"0D32",'1'&x"0D33",'1'&x"0D34",'1'&x"0D35",'1'&x"0D36",'1'&x"0D37",'1'&x"0D38",'1'&x"0D39",'1'&x"0D3A",'1'&x"0D3B",'1'&x"0D3C",'1'&x"0D3D",'1'&x"0D3E",'1'&x"0D3F",
+--'1'&x"0D40",'1'&x"0D41",'1'&x"0D42",'1'&x"0D43",'1'&x"0D44",'1'&x"0D45",'1'&x"0D46",'1'&x"0D47",'1'&x"0D48",'1'&x"0D49",'1'&x"0D4A",'1'&x"0D4B",'1'&x"0D4C",'1'&x"0D4D",'1'&x"0D4E",'1'&x"0D4F",
+--'1'&x"0D50",'1'&x"0D51",'1'&x"0D52",'1'&x"0D53",'1'&x"0D54",'1'&x"0D55",'1'&x"0D56",'1'&x"0D57",'1'&x"0D58",'1'&x"0D59",'1'&x"0D5A",'1'&x"0D5B",'1'&x"0D5C",'1'&x"0D5D",'1'&x"0D5E",'1'&x"0D5F",
+--'1'&x"0D60",'1'&x"0D61",'1'&x"0D62",'1'&x"0D63",'1'&x"0D64",'1'&x"0D65",'1'&x"0D66",'1'&x"0D67",'1'&x"0D68",'1'&x"0D69",'1'&x"0D6A",'1'&x"0D6B",'1'&x"0D6C",'1'&x"0D6D",'1'&x"0D6E",'1'&x"0D6F",
+--'1'&x"0D70",'1'&x"0D71",'1'&x"0D72",'1'&x"0D73",'1'&x"0D74",'1'&x"0D75",'1'&x"0D76",'1'&x"0D77",'1'&x"0D78",'1'&x"0D79",'1'&x"0D7A",'1'&x"0D7B",'1'&x"0D7C",'1'&x"0D7D",'1'&x"0D7E",'1'&x"0D7F",
+--'1'&x"0D80",'1'&x"0D81",'1'&x"0D82",'1'&x"0D83",'1'&x"0D84",'1'&x"0D85",'1'&x"0D86",'1'&x"0D87",'1'&x"0D88",'1'&x"0D89",'1'&x"0D8A",'1'&x"0D8B",'1'&x"0D8C",'1'&x"0D8D",'1'&x"0D8E",'1'&x"0D8F",
+--'1'&x"0D90",'1'&x"0D91",'1'&x"0D92",'1'&x"0D93",'1'&x"0D94",'1'&x"0D95",'1'&x"0D96",'1'&x"0D97",'1'&x"0D98",'1'&x"0D99",'1'&x"0D9A",'1'&x"0D9B",'1'&x"0D9C",'1'&x"0D9D",'1'&x"0D9E",'1'&x"0D9F",
+--'1'&x"0DA0",'1'&x"0DA1",'1'&x"0DA2",'1'&x"0DA3",'1'&x"0DA4",'1'&x"0DA5",'1'&x"0DA6",'1'&x"0DA7",'1'&x"0DA8",'1'&x"0DA9",'1'&x"0DAA",'1'&x"0DAB",'1'&x"0DAC",'1'&x"0DAD",'1'&x"0DAE",'1'&x"0DAF",
+--'1'&x"0DB0",'1'&x"0DB1",'1'&x"0DB2",'1'&x"0DB3",'1'&x"0DB4",'1'&x"0DB5",'1'&x"0DB6",'1'&x"0DB7",'1'&x"0DB8",'1'&x"0DB9",'1'&x"0DBA",'1'&x"0DBB",'1'&x"0DBC",'1'&x"0DBD",'1'&x"0DBE",'1'&x"0DBF",
+--'1'&x"0DC0",'1'&x"0DC1",'1'&x"0DC2",'1'&x"0DC3",'1'&x"0DC4",'1'&x"0DC5",'1'&x"0DC6",'1'&x"0DC7",'1'&x"0DC8",'1'&x"0DC9",'1'&x"0DCA",'1'&x"0DCB",'1'&x"0DCC",'1'&x"0DCD",'1'&x"0DCE",'1'&x"0DCF",
+--'1'&x"0DD0",'1'&x"0DD1",'1'&x"0DD2",'1'&x"0DD3",'1'&x"0DD4",'1'&x"0DD5",'1'&x"0DD6",'1'&x"0DD7",'1'&x"0DD8",'1'&x"0DD9",'1'&x"0DDA",'1'&x"0DDB",'1'&x"0DDC",'1'&x"0DDD",'1'&x"0DDE",'1'&x"0DDF",
+--'1'&x"0DE0",'1'&x"0DE1",'1'&x"0DE2",'1'&x"0DE3",'1'&x"0DE4",'1'&x"0DE5",'1'&x"0DE6",'1'&x"0DE7",'1'&x"0DE8",'1'&x"0DE9",'1'&x"0DEA",'1'&x"0DEB",'1'&x"0DEC",'1'&x"0DED",'1'&x"0DEE",'1'&x"0DEF",
+--'1'&x"0DF0",'1'&x"0DF1",'1'&x"0DF2",'1'&x"0DF3",'1'&x"0DF4",'1'&x"0DF5",'1'&x"0DF6",'1'&x"0DF7",'1'&x"0DF8",'1'&x"0DF9",'1'&x"0DFA",'1'&x"0DFB",'1'&x"0DFC",'1'&x"0DFD",'1'&x"0DFE",'1'&x"0DFF",
+--'1'&x"0E00",'1'&x"0E01",'1'&x"0E02",'1'&x"0E03",'1'&x"0E04",'1'&x"0E05",'1'&x"0E06",'1'&x"0E07",'1'&x"0E08",'1'&x"0E09",'1'&x"0E0A",'1'&x"0E0B",'1'&x"0E0C",'1'&x"0E0D",'1'&x"0E0E",'1'&x"0E0F",
+--'1'&x"0E10",'1'&x"0E11",'1'&x"0E12",'1'&x"0E13",'1'&x"0E14",'1'&x"0E15",'1'&x"0E16",'1'&x"0E17",'1'&x"0E18",'1'&x"0E19",'1'&x"0E1A",'1'&x"0E1B",'1'&x"0E1C",'1'&x"0E1D",'1'&x"0E1E",'1'&x"0E1F",
+--'1'&x"0E20",'1'&x"0E21",'1'&x"0E22",'1'&x"0E23",'1'&x"0E24",'1'&x"0E25",'1'&x"0E26",'1'&x"0E27",'1'&x"0E28",'1'&x"0E29",'1'&x"0E2A",'1'&x"0E2B",'1'&x"0E2C",'1'&x"0E2D",'1'&x"0E2E",'1'&x"0E2F",
+--'1'&x"0E30",'1'&x"0E31",'1'&x"0E32",'1'&x"0E33",'1'&x"0E34",'1'&x"0E35",'1'&x"0E36",'1'&x"0E37",'1'&x"0E38",'1'&x"0E39",'1'&x"0E3A",'1'&x"0E3B",'1'&x"0E3C",'1'&x"0E3D",'1'&x"0E3E",'1'&x"0E3F",
+--'1'&x"0E40",'1'&x"0E41",'1'&x"0E42",'1'&x"0E43",'1'&x"0E44",'1'&x"0E45",'1'&x"0E46",'1'&x"0E47",'1'&x"0E48",'1'&x"0E49",'1'&x"0E4A",'1'&x"0E4B",'1'&x"0E4C",'1'&x"0E4D",'1'&x"0E4E",'1'&x"0E4F",
+--'1'&x"0E50",'1'&x"0E51",'1'&x"0E52",'1'&x"0E53",'1'&x"0E54",'1'&x"0E55",'1'&x"0E56",'1'&x"0E57",'1'&x"0E58",'1'&x"0E59",'1'&x"0E5A",'1'&x"0E5B",'1'&x"0E5C",'1'&x"0E5D",'1'&x"0E5E",'1'&x"0E5F",
+--'1'&x"0E60",'1'&x"0E61",'1'&x"0E62",'1'&x"0E63",'1'&x"0E64",'1'&x"0E65",'1'&x"0E66",'1'&x"0E67",'1'&x"0E68",'1'&x"0E69",'1'&x"0E6A",'1'&x"0E6B",'1'&x"0E6C",'1'&x"0E6D",'1'&x"0E6E",'1'&x"0E6F",
+--'1'&x"0E70",'1'&x"0E71",'1'&x"0E72",'1'&x"0E73",'1'&x"0E74",'1'&x"0E75",'1'&x"0E76",'1'&x"0E77",'1'&x"0E78",'1'&x"0E79",'1'&x"0E7A",'1'&x"0E7B",'1'&x"0E7C",'1'&x"0E7D",'1'&x"0E7E",'1'&x"0E7F",
+--'1'&x"0E80",'1'&x"0E81",'1'&x"0E82",'1'&x"0E83",'1'&x"0E84",'1'&x"0E85",'1'&x"0E86",'1'&x"0E87",'1'&x"0E88",'1'&x"0E89",'1'&x"0E8A",'1'&x"0E8B",'1'&x"0E8C",'1'&x"0E8D",'1'&x"0E8E",'1'&x"0E8F",
+--'1'&x"0E90",'1'&x"0E91",'1'&x"0E92",'1'&x"0E93",'1'&x"0E94",'1'&x"0E95",'1'&x"0E96",'1'&x"0E97",'1'&x"0E98",'1'&x"0E99",'1'&x"0E9A",'1'&x"0E9B",'1'&x"0E9C",'1'&x"0E9D",'1'&x"0E9E",'1'&x"0E9F",
+--'1'&x"0EA0",'1'&x"0EA1",'1'&x"0EA2",'1'&x"0EA3",'1'&x"0EA4",'1'&x"0EA5",'1'&x"0EA6",'1'&x"0EA7",'1'&x"0EA8",'1'&x"0EA9",'1'&x"0EAA",'1'&x"0EAB",'1'&x"0EAC",'1'&x"0EAD",'1'&x"0EAE",'1'&x"0EAF",
+--'1'&x"0EB0",'1'&x"0EB1",'1'&x"0EB2",'1'&x"0EB3",'1'&x"0EB4",'1'&x"0EB5",'1'&x"0EB6",'1'&x"0EB7",'1'&x"0EB8",'1'&x"0EB9",'1'&x"0EBA",'1'&x"0EBB",'1'&x"0EBC",'1'&x"0EBD",'1'&x"0EBE",'1'&x"0EBF",
+--'1'&x"0EC0",'1'&x"0EC1",'1'&x"0EC2",'1'&x"0EC3",'1'&x"0EC4",'1'&x"0EC5",'1'&x"0EC6",'1'&x"0EC7",'1'&x"0EC8",'1'&x"0EC9",'1'&x"0ECA",'1'&x"0ECB",'1'&x"0ECC",'1'&x"0ECD",'1'&x"0ECE",'1'&x"0ECF",
+--'1'&x"0ED0",'1'&x"0ED1",'1'&x"0ED2",'1'&x"0ED3",'1'&x"0ED4",'1'&x"0ED5",'1'&x"0ED6",'1'&x"0ED7",'1'&x"0ED8",'1'&x"0ED9",'1'&x"0EDA",'1'&x"0EDB",'1'&x"0EDC",'1'&x"0EDD",'1'&x"0EDE",'1'&x"0EDF",
+--'1'&x"0EE0",'1'&x"0EE1",'1'&x"0EE2",'1'&x"0EE3",'1'&x"0EE4",'1'&x"0EE5",'1'&x"0EE6",'1'&x"0EE7",'1'&x"0EE8",'1'&x"0EE9",'1'&x"0EEA",'1'&x"0EEB",'1'&x"0EEC",'1'&x"0EED",'1'&x"0EEE",'1'&x"0EEF",
+--'1'&x"0EF0",'1'&x"0EF1",'1'&x"0EF2",'1'&x"0EF3",'1'&x"0EF4",'1'&x"0EF5",'1'&x"0EF6",'1'&x"0EF7",'1'&x"0EF8",'1'&x"0EF9",'1'&x"0EFA",'1'&x"0EFB",'1'&x"0EFC",'1'&x"0EFD",'1'&x"0EFE",'1'&x"0EFF",
+--'1'&x"0F00",'1'&x"0F01",'1'&x"0F02",'1'&x"0F03",'1'&x"0F04",'1'&x"0F05",'1'&x"0F06",'1'&x"0F07",'1'&x"0F08",'1'&x"0F09",'1'&x"0F0A",'1'&x"0F0B",'1'&x"0F0C",'1'&x"0F0D",'1'&x"0F0E",'1'&x"0F0F",
+--'1'&x"0F10",'1'&x"0F11",'1'&x"0F12",'1'&x"0F13",'1'&x"0F14",'1'&x"0F15",'1'&x"0F16",'1'&x"0F17",'1'&x"0F18",'1'&x"0F19",'1'&x"0F1A",'1'&x"0F1B",'1'&x"0F1C",'1'&x"0F1D",'1'&x"0F1E",'1'&x"0F1F",
+--'1'&x"0F20",'1'&x"0F21",'1'&x"0F22",'1'&x"0F23",'1'&x"0F24",'1'&x"0F25",'1'&x"0F26",'1'&x"0F27",'1'&x"0F28",'1'&x"0F29",'1'&x"0F2A",'1'&x"0F2B",'1'&x"0F2C",'1'&x"0F2D",'1'&x"0F2E",'1'&x"0F2F",
+--'1'&x"0F30",'1'&x"0F31",'1'&x"0F32",'1'&x"0F33",'1'&x"0F34",'1'&x"0F35",'1'&x"0F36",'1'&x"0F37",'1'&x"0F38",'1'&x"0F39",'1'&x"0F3A",'1'&x"0F3B",'1'&x"0F3C",'1'&x"0F3D",'1'&x"0F3E",'1'&x"0F3F",
+--'1'&x"0F40",'1'&x"0F41",'1'&x"0F42",'1'&x"0F43",'1'&x"0F44",'1'&x"0F45",'1'&x"0F46",'1'&x"0F47",'1'&x"0F48",'1'&x"0F49",'1'&x"0F4A",'1'&x"0F4B",'1'&x"0F4C",'1'&x"0F4D",'1'&x"0F4E",'1'&x"0F4F",
+--'1'&x"0F50",'1'&x"0F51",'1'&x"0F52",'1'&x"0F53",'1'&x"0F54",'1'&x"0F55",'1'&x"0F56",'1'&x"0F57",'1'&x"0F58",'1'&x"0F59",'1'&x"0F5A",'1'&x"0F5B",'1'&x"0F5C",'1'&x"0F5D",'1'&x"0F5E",'1'&x"0F5F",
+--'1'&x"0F60",'1'&x"0F61",'1'&x"0F62",'1'&x"0F63",'1'&x"0F64",'1'&x"0F65",'1'&x"0F66",'1'&x"0F67",'1'&x"0F68",'1'&x"0F69",'1'&x"0F6A",'1'&x"0F6B",'1'&x"0F6C",'1'&x"0F6D",'1'&x"0F6E",'1'&x"0F6F",
+--'1'&x"0F70",'1'&x"0F71",'1'&x"0F72",'1'&x"0F73",'1'&x"0F74",'1'&x"0F75",'1'&x"0F76",'1'&x"0F77",'1'&x"0F78",'1'&x"0F79",'1'&x"0F7A",'1'&x"0F7B",'1'&x"0F7C",'1'&x"0F7D",'1'&x"0F7E",'1'&x"0F7F",
+--'1'&x"0F80",'1'&x"0F81",'1'&x"0F82",'1'&x"0F83",'1'&x"0F84",'1'&x"0F85",'1'&x"0F86",'1'&x"0F87",'1'&x"0F88",'1'&x"0F89",'1'&x"0F8A",'1'&x"0F8B",'1'&x"0F8C",'1'&x"0F8D",'1'&x"0F8E",'1'&x"0F8F",
+--'1'&x"0F90",'1'&x"0F91",'1'&x"0F92",'1'&x"0F93",'1'&x"0F94",'1'&x"0F95",'1'&x"0F96",'1'&x"0F97",'1'&x"0F98",'1'&x"0F99",'1'&x"0F9A",'1'&x"0F9B",'1'&x"0F9C",'1'&x"0F9D",'1'&x"0F9E",'1'&x"0F9F",
+--'1'&x"0FA0",'1'&x"0FA1",'1'&x"0FA2",'1'&x"0FA3",'1'&x"0FA4",'1'&x"0FA5",'1'&x"0FA6",'1'&x"0FA7",'1'&x"0FA8",'1'&x"0FA9",'1'&x"0FAA",'1'&x"0FAB",'1'&x"0FAC",'1'&x"0FAD",'1'&x"0FAE",'1'&x"0FAF",
+--'1'&x"0FB0",'1'&x"0FB1",'1'&x"0FB2",'1'&x"0FB3",'1'&x"0FB4",'1'&x"0FB5",'1'&x"0FB6",'1'&x"0FB7",'1'&x"0FB8",'1'&x"0FB9",'1'&x"0FBA",'1'&x"0FBB",'1'&x"0FBC",'1'&x"0FBD",'1'&x"0FBE",'1'&x"0FBF",
+--'1'&x"0FC0",'1'&x"0FC1",'1'&x"0FC2",'1'&x"0FC3",'1'&x"0FC4",'1'&x"0FC5",'1'&x"0FC6",'1'&x"0FC7",'1'&x"0FC8",'1'&x"0FC9",'1'&x"0FCA",'1'&x"0FCB",'1'&x"0FCC",'1'&x"0FCD",'1'&x"0FCE",'1'&x"0FCF",
+--'1'&x"0FD0",'1'&x"0FD1",'1'&x"0FD2",'1'&x"0FD3",'1'&x"0FD4",'1'&x"0FD5",'1'&x"0FD6",'1'&x"0FD7",'1'&x"0FD8",'1'&x"0FD9",'1'&x"0FDA",'1'&x"0FDB",'1'&x"0FDC",'1'&x"0FDD",'1'&x"0FDE",'1'&x"0FDF",
+--'1'&x"0FE0",'1'&x"0FE1",'1'&x"0FE2",'1'&x"0FE3",'1'&x"0FE4",'1'&x"0FE5",'1'&x"0FE6",'1'&x"0FE7",'1'&x"0FE8",'1'&x"0FE9",'1'&x"0FEA",'1'&x"0FEB",'1'&x"0FEC",'1'&x"0FED",'1'&x"0FEE",'1'&x"0FEF",
+--'1'&x"0FF0",'1'&x"0FF1",'1'&x"0FF2",'1'&x"0FF3",'1'&x"0FF4",'1'&x"0FF5",'1'&x"0FF6",'1'&x"0FF7",'1'&x"0FF8",'1'&x"0FF9",'1'&x"0FFA",'1'&x"0FFB",'1'&x"0FFC",'1'&x"0FFD",'1'&x"0FFE",'1'&x"0FFF",
+--'1'&x"1000",'1'&x"1001",'1'&x"1002",'1'&x"1003",'1'&x"1004",'1'&x"1005",'1'&x"1006",'1'&x"1007",'1'&x"1008",'1'&x"1009",'1'&x"100A",'1'&x"100B",'1'&x"100C",'1'&x"100D",'1'&x"100E",'1'&x"100F",
+--'1'&x"1010",'1'&x"1011",'1'&x"1012",'1'&x"1013",'1'&x"1014",'1'&x"1015",'1'&x"1016",'1'&x"1017",'1'&x"1018",'1'&x"1019",'1'&x"101A",'1'&x"101B",'1'&x"101C",'1'&x"101D",'1'&x"101E",'1'&x"101F",
+--'1'&x"1020",'1'&x"1021",'1'&x"1022",'1'&x"1023",'1'&x"1024",'1'&x"1025",'1'&x"1026",'1'&x"1027",'1'&x"1028",'1'&x"1029",'1'&x"102A",'1'&x"102B",'1'&x"102C",'1'&x"102D",'1'&x"102E",'1'&x"102F",
+--'1'&x"1030",'1'&x"1031",'1'&x"1032",'1'&x"1033",'1'&x"1034",'1'&x"1035",'1'&x"1036",'1'&x"1037",'1'&x"1038",'1'&x"1039",'1'&x"103A",'1'&x"103B",'1'&x"103C",'1'&x"103D",'1'&x"103E",'1'&x"103F",
+--'1'&x"1040",'1'&x"1041",'1'&x"1042",'1'&x"1043",'1'&x"1044",'1'&x"1045",'1'&x"1046",'1'&x"1047",'1'&x"1048",'1'&x"1049",'1'&x"104A",'1'&x"104B",'1'&x"104C",'1'&x"104D",'1'&x"104E",'1'&x"104F",
+--'1'&x"1050",'1'&x"1051",'1'&x"1052",'1'&x"1053",'1'&x"1054",'1'&x"1055",'1'&x"1056",'1'&x"1057",'1'&x"1058",'1'&x"1059",'1'&x"105A",'1'&x"105B",'1'&x"105C",'1'&x"105D",'1'&x"105E",'1'&x"105F",
+--'1'&x"1060",'1'&x"1061",'1'&x"1062",'1'&x"1063",'1'&x"1064",'1'&x"1065",'1'&x"1066",'1'&x"1067",'1'&x"1068",'1'&x"1069",'1'&x"106A",'1'&x"106B",'1'&x"106C",'1'&x"106D",'1'&x"106E",'1'&x"106F",
+--'1'&x"1070",'1'&x"1071",'1'&x"1072",'1'&x"1073",'1'&x"1074",'1'&x"1075",'1'&x"1076",'1'&x"1077",'1'&x"1078",'1'&x"1079",'1'&x"107A",'1'&x"107B",'1'&x"107C",'1'&x"107D",'1'&x"107E",'1'&x"107F",
+--'1'&x"1080",'1'&x"1081",'1'&x"1082",'1'&x"1083",'1'&x"1084",'1'&x"1085",'1'&x"1086",'1'&x"1087",'1'&x"1088",'1'&x"1089",'1'&x"108A",'1'&x"108B",'1'&x"108C",'1'&x"108D",'1'&x"108E",'1'&x"108F",
+--'1'&x"1090",'1'&x"1091",'1'&x"1092",'1'&x"1093",'1'&x"1094",'1'&x"1095",'1'&x"1096",'1'&x"1097",'1'&x"1098",'1'&x"1099",'1'&x"109A",'1'&x"109B",'1'&x"109C",'1'&x"109D",'1'&x"109E",'1'&x"109F",
+--'1'&x"10A0",'1'&x"10A1",'1'&x"10A2",'1'&x"10A3",'1'&x"10A4",'1'&x"10A5",'1'&x"10A6",'1'&x"10A7",'1'&x"10A8",'1'&x"10A9",'1'&x"10AA",'1'&x"10AB",'1'&x"10AC",'1'&x"10AD",'1'&x"10AE",'1'&x"10AF",
+--'1'&x"10B0",'1'&x"10B1",'1'&x"10B2",'1'&x"10B3",'1'&x"10B4",'1'&x"10B5",'1'&x"10B6",'1'&x"10B7",'1'&x"10B8",'1'&x"10B9",'1'&x"10BA",'1'&x"10BB",'1'&x"10BC",'1'&x"10BD",'1'&x"10BE",'1'&x"10BF",
+--'1'&x"10C0",'1'&x"10C1",'1'&x"10C2",'1'&x"10C3",'1'&x"10C4",'1'&x"10C5",'1'&x"10C6",'1'&x"10C7",'1'&x"10C8",'1'&x"10C9",'1'&x"10CA",'1'&x"10CB",'1'&x"10CC",'1'&x"10CD",'1'&x"10CE",'1'&x"10CF",
+--'1'&x"10D0",'1'&x"10D1",'1'&x"10D2",'1'&x"10D3",'1'&x"10D4",'1'&x"10D5",'1'&x"10D6",'1'&x"10D7",'1'&x"10D8",'1'&x"10D9",'1'&x"10DA",'1'&x"10DB",'1'&x"10DC",'1'&x"10DD",'1'&x"10DE",'1'&x"10DF",
+--'1'&x"10E0",'1'&x"10E1",'1'&x"10E2",'1'&x"10E3",'1'&x"10E4",'1'&x"10E5",'1'&x"10E6",'1'&x"10E7",'1'&x"10E8",'1'&x"10E9",'1'&x"10EA",'1'&x"10EB",'1'&x"10EC",'1'&x"10ED",'1'&x"10EE",'1'&x"10EF",
+--'1'&x"10F0",'1'&x"10F1",'1'&x"10F2",'1'&x"10F3",'1'&x"10F4",'1'&x"10F5",'1'&x"10F6",'1'&x"10F7",'1'&x"10F8",'1'&x"10F9",'1'&x"10FA",'1'&x"10FB",'1'&x"10FC",'1'&x"10FD",'1'&x"10FE",'1'&x"10FF",
+--'1'&x"1100",'1'&x"1101",'1'&x"1102",'1'&x"1103",'1'&x"1104",'1'&x"1105",'1'&x"1106",'1'&x"1107",'1'&x"1108",'1'&x"1109",'1'&x"110A",'1'&x"110B",'1'&x"110C",'1'&x"110D",'1'&x"110E",'1'&x"110F",
+--'1'&x"1110",'1'&x"1111",'1'&x"1112",'1'&x"1113",'1'&x"1114",'1'&x"1115",'1'&x"1116",'1'&x"1117",'1'&x"1118",'1'&x"1119",'1'&x"111A",'1'&x"111B",'1'&x"111C",'1'&x"111D",'1'&x"111E",'1'&x"111F",
+--'1'&x"1120",'1'&x"1121",'1'&x"1122",'1'&x"1123",'1'&x"1124",'1'&x"1125",'1'&x"1126",'1'&x"1127",'1'&x"1128",'1'&x"1129",'1'&x"112A",'1'&x"112B",'1'&x"112C",'1'&x"112D",'1'&x"112E",'1'&x"112F",
+--'1'&x"1130",'1'&x"1131",'1'&x"1132",'1'&x"1133",'1'&x"1134",'1'&x"1135",'1'&x"1136",'1'&x"1137",'1'&x"1138",'1'&x"1139",'1'&x"113A",'1'&x"113B",'1'&x"113C",'1'&x"113D",'1'&x"113E",'1'&x"113F",
+--'1'&x"1140",'1'&x"1141",'1'&x"1142",'1'&x"1143",'1'&x"1144",'1'&x"1145",'1'&x"1146",'1'&x"1147",'1'&x"1148",'1'&x"1149",'1'&x"114A",'1'&x"114B",'1'&x"114C",'1'&x"114D",'1'&x"114E",'1'&x"114F",
+--'1'&x"1150",'1'&x"1151",'1'&x"1152",'1'&x"1153",'1'&x"1154",'1'&x"1155",'1'&x"1156",'1'&x"1157",'1'&x"1158",'1'&x"1159",'1'&x"115A",'1'&x"115B",'1'&x"115C",'1'&x"115D",'1'&x"115E",'1'&x"115F",
+--'1'&x"1160",'1'&x"1161",'1'&x"1162",'1'&x"1163",'1'&x"1164",'1'&x"1165",'1'&x"1166",'1'&x"1167",'1'&x"1168",'1'&x"1169",'1'&x"116A",'1'&x"116B",'1'&x"116C",'1'&x"116D",'1'&x"116E",'1'&x"116F",
+--'1'&x"1170",'1'&x"1171",'1'&x"1172",'1'&x"1173",'1'&x"1174",'1'&x"1175",'1'&x"1176",'1'&x"1177",'1'&x"1178",'1'&x"1179",'1'&x"117A",'1'&x"117B",'1'&x"117C",'1'&x"117D",'1'&x"117E",'1'&x"117F",
+--'1'&x"1180",'1'&x"1181",'1'&x"1182",'1'&x"1183",'1'&x"1184",'1'&x"1185",'1'&x"1186",'1'&x"1187",'1'&x"1188",'1'&x"1189",'1'&x"118A",'1'&x"118B",'1'&x"118C",'1'&x"118D",'1'&x"118E",'1'&x"118F",
+--'1'&x"1190",'1'&x"1191",'1'&x"1192",'1'&x"1193",'1'&x"1194",'1'&x"1195",'1'&x"1196",'1'&x"1197",'1'&x"1198",'1'&x"1199",'1'&x"119A",'1'&x"119B",'1'&x"119C",'1'&x"119D",'1'&x"119E",'1'&x"119F",
+--'1'&x"11A0",'1'&x"11A1",'1'&x"11A2",'1'&x"11A3",'1'&x"11A4",'1'&x"11A5",'1'&x"11A6",'1'&x"11A7",'1'&x"11A8",'1'&x"11A9",'1'&x"11AA",'1'&x"11AB",'1'&x"11AC",'1'&x"11AD",'1'&x"11AE",'1'&x"11AF",
+--'1'&x"11B0",'1'&x"11B1",'1'&x"11B2",'1'&x"11B3",'1'&x"11B4",'1'&x"11B5",'1'&x"11B6",'1'&x"11B7",'1'&x"11B8",'1'&x"11B9",'1'&x"11BA",'1'&x"11BB",'1'&x"11BC",'1'&x"11BD",'1'&x"11BE",'1'&x"11BF",
+--'1'&x"11C0",'1'&x"11C1",'1'&x"11C2",'1'&x"11C3",'1'&x"11C4",'1'&x"11C5",'1'&x"11C6",'1'&x"11C7",'1'&x"11C8",'1'&x"11C9",'1'&x"11CA",'1'&x"11CB",'1'&x"11CC",'1'&x"11CD",'1'&x"11CE",'1'&x"11CF",
+--'1'&x"11D0",'1'&x"11D1",'1'&x"11D2",'1'&x"11D3",'1'&x"11D4",'1'&x"11D5",'1'&x"11D6",'1'&x"11D7",'1'&x"11D8",'1'&x"11D9",'1'&x"11DA",'1'&x"11DB",'1'&x"11DC",'1'&x"11DD",'1'&x"11DE",'1'&x"11DF",
+--'1'&x"11E0",'1'&x"11E1",'1'&x"11E2",'1'&x"11E3",'1'&x"11E4",'1'&x"11E5",'1'&x"11E6",'1'&x"11E7",'1'&x"11E8",'1'&x"11E9",'1'&x"11EA",'1'&x"11EB",'1'&x"11EC",'1'&x"11ED",'1'&x"11EE",'1'&x"11EF",
+--'1'&x"11F0",'1'&x"11F1",'1'&x"11F2",'1'&x"11F3",'1'&x"11F4",'1'&x"11F5",'1'&x"11F6",'1'&x"11F7",'1'&x"11F8",'1'&x"11F9",'1'&x"11FA",'1'&x"11FB",'1'&x"11FC",'1'&x"11FD",'1'&x"11FE",'1'&x"11FF",
+--'1'&x"1200",'1'&x"1201",'1'&x"1202",'1'&x"1203",'1'&x"1204",'1'&x"1205",'1'&x"1206",'1'&x"1207",'1'&x"1208",'1'&x"1209",'1'&x"120A",'1'&x"120B",'1'&x"120C",'1'&x"120D",'1'&x"120E",'1'&x"120F",
+--'1'&x"1210",'1'&x"1211",'1'&x"1212",'1'&x"1213",'1'&x"1214",'1'&x"1215",'1'&x"1216",'1'&x"1217",'1'&x"1218",'1'&x"1219",'1'&x"121A",'1'&x"121B",'1'&x"121C",'1'&x"121D",'1'&x"121E",'1'&x"121F",
+--'1'&x"1220",'1'&x"1221",'1'&x"1222",'1'&x"1223",'1'&x"1224",'1'&x"1225",'1'&x"1226",'1'&x"1227",'1'&x"1228",'1'&x"1229",'1'&x"122A",'1'&x"122B",'1'&x"122C",'1'&x"122D",'1'&x"122E",'1'&x"122F",
+--'1'&x"1230",'1'&x"1231",'1'&x"1232",'1'&x"1233",'1'&x"1234",'1'&x"1235",'1'&x"1236",'1'&x"1237",'1'&x"1238",'1'&x"1239",'1'&x"123A",'1'&x"123B",'1'&x"123C",'1'&x"123D",'1'&x"123E",'1'&x"123F",
+--'1'&x"1240",'1'&x"1241",'1'&x"1242",'1'&x"1243",'1'&x"1244",'1'&x"1245",'1'&x"1246",'1'&x"1247",'1'&x"1248",'1'&x"1249",'1'&x"124A",'1'&x"124B",'1'&x"124C",'1'&x"124D",'1'&x"124E",'1'&x"124F",
+--'1'&x"1250",'1'&x"1251",'1'&x"1252",'1'&x"1253",'1'&x"1254",'1'&x"1255",'1'&x"1256",'1'&x"1257",'1'&x"1258",'1'&x"1259",'1'&x"125A",'1'&x"125B",'1'&x"125C",'1'&x"125D",'1'&x"125E",'1'&x"125F",
+--'1'&x"1260",'1'&x"1261",'1'&x"1262",'1'&x"1263",'1'&x"1264",'1'&x"1265",'1'&x"1266",'1'&x"1267",'1'&x"1268",'1'&x"1269",'1'&x"126A",'1'&x"126B",'1'&x"126C",'1'&x"126D",'1'&x"126E",'1'&x"126F",
+--'1'&x"1270",'1'&x"1271",'1'&x"1272",'1'&x"1273",'1'&x"1274",'1'&x"1275",'1'&x"1276",'1'&x"1277",'1'&x"1278",'1'&x"1279",'1'&x"127A",'1'&x"127B",'1'&x"127C",'1'&x"127D",'1'&x"127E",'1'&x"127F",
+--'1'&x"1280",'1'&x"1281",'1'&x"1282",'1'&x"1283",'1'&x"1284",'1'&x"1285",'1'&x"1286",'1'&x"1287",'1'&x"1288",'1'&x"1289",'1'&x"128A",'1'&x"128B",'1'&x"128C",'1'&x"128D",'1'&x"128E",'1'&x"128F",
+--'1'&x"1290",'1'&x"1291",'1'&x"1292",'1'&x"1293",'1'&x"1294",'1'&x"1295",'1'&x"1296",'1'&x"1297",'1'&x"1298",'1'&x"1299",'1'&x"129A",'1'&x"129B",'1'&x"129C",'1'&x"129D",'1'&x"129E",'1'&x"129F",
+--'1'&x"12A0",'1'&x"12A1",'1'&x"12A2",'1'&x"12A3",'1'&x"12A4",'1'&x"12A5",'1'&x"12A6",'1'&x"12A7",'1'&x"12A8",'1'&x"12A9",'1'&x"12AA",'1'&x"12AB",'1'&x"12AC",'1'&x"12AD",'1'&x"12AE",'1'&x"12AF",
+--'1'&x"12B0",'1'&x"12B1",'1'&x"12B2",'1'&x"12B3",'1'&x"12B4",'1'&x"12B5",'1'&x"12B6",'1'&x"12B7",'1'&x"12B8",'1'&x"12B9",'1'&x"12BA",'1'&x"12BB",'1'&x"12BC",'1'&x"12BD",'1'&x"12BE",'1'&x"12BF",
+--'1'&x"12C0",'1'&x"12C1",'1'&x"12C2",'1'&x"12C3",'1'&x"12C4",'1'&x"12C5",'1'&x"12C6",'1'&x"12C7",'1'&x"12C8",'1'&x"12C9",'1'&x"12CA",'1'&x"12CB",'1'&x"12CC",'1'&x"12CD",'1'&x"12CE",'1'&x"12CF",
+--'1'&x"12D0",'1'&x"12D1",'1'&x"12D2",'1'&x"12D3",'1'&x"12D4",'1'&x"12D5",'1'&x"12D6",'1'&x"12D7",'1'&x"12D8",'1'&x"12D9",'1'&x"12DA",'1'&x"12DB",'1'&x"12DC",'1'&x"12DD",'1'&x"12DE",'1'&x"12DF",
+--'1'&x"12E0",'1'&x"12E1",'1'&x"12E2",'1'&x"12E3",'1'&x"12E4",'1'&x"12E5",'1'&x"12E6",'1'&x"12E7",'1'&x"12E8",'1'&x"12E9",'1'&x"12EA",'1'&x"12EB",'1'&x"12EC",'1'&x"12ED",'1'&x"12EE",'1'&x"12EF",
+--'1'&x"12F0",'1'&x"12F1",'1'&x"12F2",'1'&x"12F3",'1'&x"12F4",'1'&x"12F5",'1'&x"12F6",'1'&x"12F7",'1'&x"12F8",'1'&x"12F9",'1'&x"12FA",'1'&x"12FB",'1'&x"12FC",'1'&x"12FD",'1'&x"12FE",'1'&x"12FF",
+--'1'&x"1300",'1'&x"1301",'1'&x"1302",'1'&x"1303",'1'&x"1304",'1'&x"1305",'1'&x"1306",'1'&x"1307",'1'&x"1308",'1'&x"1309",'1'&x"130A",'1'&x"130B",'1'&x"130C",'1'&x"130D",'1'&x"130E",'1'&x"130F",
+--'1'&x"1310",'1'&x"1311",'1'&x"1312",'1'&x"1313",'1'&x"1314",'1'&x"1315",'1'&x"1316",'1'&x"1317",'1'&x"1318",'1'&x"1319",'1'&x"131A",'1'&x"131B",'1'&x"131C",'1'&x"131D",'1'&x"131E",'1'&x"131F",
+--'1'&x"1320",'1'&x"1321",'1'&x"1322",'1'&x"1323",'1'&x"1324",'1'&x"1325",'1'&x"1326",'1'&x"1327",'1'&x"1328",'1'&x"1329",'1'&x"132A",'1'&x"132B",'1'&x"132C",'1'&x"132D",'1'&x"132E",'1'&x"132F",
+--'1'&x"1330",'1'&x"1331",'1'&x"1332",'1'&x"1333",'1'&x"1334",'1'&x"1335",'1'&x"1336",'1'&x"1337",'1'&x"1338",'1'&x"1339",'1'&x"133A",'1'&x"133B",'1'&x"133C",'1'&x"133D",'1'&x"133E",'1'&x"133F",
+--'1'&x"1340",'1'&x"1341",'1'&x"1342",'1'&x"1343",'1'&x"1344",'1'&x"1345",'1'&x"1346",'1'&x"1347",'1'&x"1348",'1'&x"1349",'1'&x"134A",'1'&x"134B",'1'&x"134C",'1'&x"134D",'1'&x"134E",'1'&x"134F",
+--'1'&x"1350",'1'&x"1351",'1'&x"1352",'1'&x"1353",'1'&x"1354",'1'&x"1355",'1'&x"1356",'1'&x"1357",'1'&x"1358",'1'&x"1359",'1'&x"135A",'1'&x"135B",'1'&x"135C",'1'&x"135D",'1'&x"135E",'1'&x"135F",
+--'1'&x"1360",'1'&x"1361",'1'&x"1362",'1'&x"1363",'1'&x"1364",'1'&x"1365",'1'&x"1366",'1'&x"1367",'1'&x"1368",'1'&x"1369",'1'&x"136A",'1'&x"136B",'1'&x"136C",'1'&x"136D",'1'&x"136E",'1'&x"136F",
+--'1'&x"1370",'1'&x"1371",'1'&x"1372",'1'&x"1373",'1'&x"1374",'1'&x"1375",'1'&x"1376",'1'&x"1377",'1'&x"1378",'1'&x"1379",'1'&x"137A",'1'&x"137B",'1'&x"137C",'1'&x"137D",'1'&x"137E",'1'&x"137F",
+--'1'&x"1380",'1'&x"1381",'1'&x"1382",'1'&x"1383",'1'&x"1384",'1'&x"1385",'1'&x"1386",'1'&x"1387",'1'&x"1388",'1'&x"1389",'1'&x"138A",'1'&x"138B",'1'&x"138C",'1'&x"138D",'1'&x"138E",'1'&x"138F",
+--'1'&x"1390",'1'&x"1391",'1'&x"1392",'1'&x"1393",'1'&x"1394",'1'&x"1395",'1'&x"1396",'1'&x"1397",'1'&x"1398",'1'&x"1399",'1'&x"139A",'1'&x"139B",'1'&x"139C",'1'&x"139D",'1'&x"139E",'1'&x"139F",
+--'1'&x"13A0",'1'&x"13A1",'1'&x"13A2",'1'&x"13A3",'1'&x"13A4",'1'&x"13A5",'1'&x"13A6",'1'&x"13A7",'1'&x"13A8",'1'&x"13A9",'1'&x"13AA",'1'&x"13AB",'1'&x"13AC",'1'&x"13AD",'1'&x"13AE",'1'&x"13AF",
+--'1'&x"13B0",'1'&x"13B1",'1'&x"13B2",'1'&x"13B3",'1'&x"13B4",'1'&x"13B5",'1'&x"13B6",'1'&x"13B7",'1'&x"13B8",'1'&x"13B9",'1'&x"13BA",'1'&x"13BB",'1'&x"13BC",'1'&x"13BD",'1'&x"13BE",'1'&x"13BF",
+--'1'&x"13C0",'1'&x"13C1",'1'&x"13C2",'1'&x"13C3",'1'&x"13C4",'1'&x"13C5",'1'&x"13C6",'1'&x"13C7",'1'&x"13C8",'1'&x"13C9",'1'&x"13CA",'1'&x"13CB",'1'&x"13CC",'1'&x"13CD",'1'&x"13CE",'1'&x"13CF",
+--'1'&x"13D0",'1'&x"13D1",'1'&x"13D2",'1'&x"13D3",'1'&x"13D4",'1'&x"13D5",'1'&x"13D6",'1'&x"13D7",'1'&x"13D8",'1'&x"13D9",'1'&x"13DA",'1'&x"13DB",'1'&x"13DC",'1'&x"13DD",'1'&x"13DE",'1'&x"13DF",
+--'1'&x"13E0",'1'&x"13E1",'1'&x"13E2",'1'&x"13E3",'1'&x"13E4",'1'&x"13E5",'1'&x"13E6",'1'&x"13E7",'1'&x"13E8",'1'&x"13E9",'1'&x"13EA",'1'&x"13EB",'1'&x"13EC",'1'&x"13ED",'1'&x"13EE",'1'&x"13EF",
+--'1'&x"13F0",'1'&x"13F1",'1'&x"13F2",'1'&x"13F3",'1'&x"13F4",'1'&x"13F5",'1'&x"13F6",'1'&x"13F7",'1'&x"13F8",'1'&x"13F9",'1'&x"13FA",'1'&x"13FB",'1'&x"13FC",'1'&x"13FD",'1'&x"13FE",'1'&x"13FF",
+--'1'&x"1400",'1'&x"1401",'1'&x"1402",'1'&x"1403",'1'&x"1404",'1'&x"1405",'1'&x"1406",'1'&x"1407",'1'&x"1408",'1'&x"1409",'1'&x"140A",'1'&x"140B",'1'&x"140C",'1'&x"140D",'1'&x"140E",'1'&x"140F",
+--'1'&x"1410",'1'&x"1411",'1'&x"1412",'1'&x"1413",'1'&x"1414",'1'&x"1415",'1'&x"1416",'1'&x"1417",'1'&x"1418",'1'&x"1419",'1'&x"141A",'1'&x"141B",'1'&x"141C",'1'&x"141D",'1'&x"141E",'1'&x"141F",
+--'1'&x"1420",'1'&x"1421",'1'&x"1422",'1'&x"1423",'1'&x"1424",'1'&x"1425",'1'&x"1426",'1'&x"1427",'1'&x"1428",'1'&x"1429",'1'&x"142A",'1'&x"142B",'1'&x"142C",'1'&x"142D",'1'&x"142E",'1'&x"142F",
+--'1'&x"1430",'1'&x"1431",'1'&x"1432",'1'&x"1433",'1'&x"1434",'1'&x"1435",'1'&x"1436",'1'&x"1437",'1'&x"1438",'1'&x"1439",'1'&x"143A",'1'&x"143B",'1'&x"143C",'1'&x"143D",'1'&x"143E",'1'&x"143F",
+--'1'&x"1440",'1'&x"1441",'1'&x"1442",'1'&x"1443",'1'&x"1444",'1'&x"1445",'1'&x"1446",'1'&x"1447",'1'&x"1448",'1'&x"1449",'1'&x"144A",'1'&x"144B",'1'&x"144C",'1'&x"144D",'1'&x"144E",'1'&x"144F",
+--'1'&x"1450",'1'&x"1451",'1'&x"1452",'1'&x"1453",'1'&x"1454",'1'&x"1455",'1'&x"1456",'1'&x"1457",'1'&x"1458",'1'&x"1459",'1'&x"145A",'1'&x"145B",'1'&x"145C",'1'&x"145D",'1'&x"145E",'1'&x"145F",
+--'1'&x"1460",'1'&x"1461",'1'&x"1462",'1'&x"1463",'1'&x"1464",'1'&x"1465",'1'&x"1466",'1'&x"1467",'1'&x"1468",'1'&x"1469",'1'&x"146A",'1'&x"146B",'1'&x"146C",'1'&x"146D",'1'&x"146E",'1'&x"146F",
+--'1'&x"1470",'1'&x"1471",'1'&x"1472",'1'&x"1473",'1'&x"1474",'1'&x"1475",'1'&x"1476",'1'&x"1477",'1'&x"1478",'1'&x"1479",'1'&x"147A",'1'&x"147B",'1'&x"147C",'1'&x"147D",'1'&x"147E",'1'&x"147F",
+--'1'&x"1480",'1'&x"1481",'1'&x"1482",'1'&x"1483",'1'&x"1484",'1'&x"1485",'1'&x"1486",'1'&x"1487",'1'&x"1488",'1'&x"1489",'1'&x"148A",'1'&x"148B",'1'&x"148C",'1'&x"148D",'1'&x"148E",'1'&x"148F",
+--'1'&x"1490",'1'&x"1491",'1'&x"1492",'1'&x"1493",'1'&x"1494",'1'&x"1495",'1'&x"1496",'1'&x"1497",'1'&x"1498",'1'&x"1499",'1'&x"149A",'1'&x"149B",'1'&x"149C",'1'&x"149D",'1'&x"149E",'1'&x"149F",
+--'1'&x"14A0",'1'&x"14A1",'1'&x"14A2",'1'&x"14A3",'1'&x"14A4",'1'&x"14A5",'1'&x"14A6",'1'&x"14A7",'1'&x"14A8",'1'&x"14A9",'1'&x"14AA",'1'&x"14AB",'1'&x"14AC",'1'&x"14AD",'1'&x"14AE",'1'&x"14AF",
+--'1'&x"14B0",'1'&x"14B1",'1'&x"14B2",'1'&x"14B3",'1'&x"14B4",'1'&x"14B5",'1'&x"14B6",'1'&x"14B7",'1'&x"14B8",'1'&x"14B9",'1'&x"14BA",'1'&x"14BB",'1'&x"14BC",'1'&x"14BD",'1'&x"14BE",'1'&x"14BF",
+--'1'&x"14C0",'1'&x"14C1",'1'&x"14C2",'1'&x"14C3",'1'&x"14C4",'1'&x"14C5",'1'&x"14C6",'1'&x"14C7",'1'&x"14C8",'1'&x"14C9",'1'&x"14CA",'1'&x"14CB",'1'&x"14CC",'1'&x"14CD",'1'&x"14CE",'1'&x"14CF",
+--'1'&x"14D0",'1'&x"14D1",'1'&x"14D2",'1'&x"14D3",'1'&x"14D4",'1'&x"14D5",'1'&x"14D6",'1'&x"14D7",'1'&x"14D8",'1'&x"14D9",'1'&x"14DA",'1'&x"14DB",'1'&x"14DC",'1'&x"14DD",'1'&x"14DE",'1'&x"14DF",
+--'1'&x"14E0",'1'&x"14E1",'1'&x"14E2",'1'&x"14E3",'1'&x"14E4",'1'&x"14E5",'1'&x"14E6",'1'&x"14E7",'1'&x"14E8",'1'&x"14E9",'1'&x"14EA",'1'&x"14EB",'1'&x"14EC",'1'&x"14ED",'1'&x"14EE",'1'&x"14EF",
+--'1'&x"14F0",'1'&x"14F1",'1'&x"14F2",'1'&x"14F3",'1'&x"14F4",'1'&x"14F5",'1'&x"14F6",'1'&x"14F7",'1'&x"14F8",'1'&x"14F9",'1'&x"14FA",'1'&x"14FB",'1'&x"14FC",'1'&x"14FD",'1'&x"14FE",'1'&x"14FF",
+--'1'&x"1500",'1'&x"1501",'1'&x"1502",'1'&x"1503",'1'&x"1504",'1'&x"1505",'1'&x"1506",'1'&x"1507",'1'&x"1508",'1'&x"1509",'1'&x"150A",'1'&x"150B",'1'&x"150C",'1'&x"150D",'1'&x"150E",'1'&x"150F",
+--'1'&x"1510",'1'&x"1511",'1'&x"1512",'1'&x"1513",'1'&x"1514",'1'&x"1515",'1'&x"1516",'1'&x"1517",'1'&x"1518",'1'&x"1519",'1'&x"151A",'1'&x"151B",'1'&x"151C",'1'&x"151D",'1'&x"151E",'1'&x"151F",
+--'1'&x"1520",'1'&x"1521",'1'&x"1522",'1'&x"1523",'1'&x"1524",'1'&x"1525",'1'&x"1526",'1'&x"1527",'1'&x"1528",'1'&x"1529",'1'&x"152A",'1'&x"152B",'1'&x"152C",'1'&x"152D",'1'&x"152E",'1'&x"152F",
+--'1'&x"1530",'1'&x"1531",'1'&x"1532",'1'&x"1533",'1'&x"1534",'1'&x"1535",'1'&x"1536",'1'&x"1537",'1'&x"1538",'1'&x"1539",'1'&x"153A",'1'&x"153B",'1'&x"153C",'1'&x"153D",'1'&x"153E",'1'&x"153F",
+--'1'&x"1540",'1'&x"1541",'1'&x"1542",'1'&x"1543",'1'&x"1544",'1'&x"1545",'1'&x"1546",'1'&x"1547",'1'&x"1548",'1'&x"1549",'1'&x"154A",'1'&x"154B",'1'&x"154C",'1'&x"154D",'1'&x"154E",'1'&x"154F",
+--'1'&x"1550",'1'&x"1551",'1'&x"1552",'1'&x"1553",'1'&x"1554",'1'&x"1555",'1'&x"1556",'1'&x"1557",'1'&x"1558",'1'&x"1559",'1'&x"155A",'1'&x"155B",'1'&x"155C",'1'&x"155D",'1'&x"155E",'1'&x"155F",
+--'1'&x"1560",'1'&x"1561",'1'&x"1562",'1'&x"1563",'1'&x"1564",'1'&x"1565",'1'&x"1566",'1'&x"1567",'1'&x"1568",'1'&x"1569",'1'&x"156A",'1'&x"156B",'1'&x"156C",'1'&x"156D",'1'&x"156E",'1'&x"156F",
+--'1'&x"1570",'1'&x"1571",'1'&x"1572",'1'&x"1573",'1'&x"1574",'1'&x"1575",'1'&x"1576",'1'&x"1577",'1'&x"1578",'1'&x"1579",'1'&x"157A",'1'&x"157B",'1'&x"157C",'1'&x"157D",'1'&x"157E",'1'&x"157F",
+--'1'&x"1580",'1'&x"1581",'1'&x"1582",'1'&x"1583",'1'&x"1584",'1'&x"1585",'1'&x"1586",'1'&x"1587",'1'&x"1588",'1'&x"1589",'1'&x"158A",'1'&x"158B",'1'&x"158C",'1'&x"158D",'1'&x"158E",'1'&x"158F",
+--'1'&x"1590",'1'&x"1591",'1'&x"1592",'1'&x"1593",'1'&x"1594",'1'&x"1595",'1'&x"1596",'1'&x"1597",'1'&x"1598",'1'&x"1599",'1'&x"159A",'1'&x"159B",'1'&x"159C",'1'&x"159D",'1'&x"159E",'1'&x"159F",
+--'1'&x"15A0",'1'&x"15A1",'1'&x"15A2",'1'&x"15A3",'1'&x"15A4",'1'&x"15A5",'1'&x"15A6",'1'&x"15A7",'1'&x"15A8",'1'&x"15A9",'1'&x"15AA",'1'&x"15AB",'1'&x"15AC",'1'&x"15AD",'1'&x"15AE",'1'&x"15AF",
+--'1'&x"15B0",'1'&x"15B1",'1'&x"15B2",'1'&x"15B3",'1'&x"15B4",'1'&x"15B5",'1'&x"15B6",'1'&x"15B7",'1'&x"15B8",'1'&x"15B9",'1'&x"15BA",'1'&x"15BB",'1'&x"15BC",'1'&x"15BD",'1'&x"15BE",'1'&x"15BF",
+--'1'&x"15C0",'1'&x"15C1",'1'&x"15C2",'1'&x"15C3",'1'&x"15C4",'1'&x"15C5",'1'&x"15C6",'1'&x"15C7",'1'&x"15C8",'1'&x"15C9",'1'&x"15CA",'1'&x"15CB",'1'&x"15CC",'1'&x"15CD",'1'&x"15CE",'1'&x"15CF",
+--'1'&x"15D0",'1'&x"15D1",'1'&x"15D2",'1'&x"15D3",'1'&x"15D4",'1'&x"15D5",'1'&x"15D6",'1'&x"15D7",'1'&x"15D8",'1'&x"15D9",'1'&x"15DA",'1'&x"15DB",'1'&x"15DC",'1'&x"15DD",'1'&x"15DE",'1'&x"15DF",
+--'1'&x"15E0",'1'&x"15E1",'1'&x"15E2",'1'&x"15E3",'1'&x"15E4",'1'&x"15E5",'1'&x"15E6",'1'&x"15E7",'1'&x"15E8",'1'&x"15E9",'1'&x"15EA",'1'&x"15EB",'1'&x"15EC",'1'&x"15ED",'1'&x"15EE",'1'&x"15EF",
+--'1'&x"15F0",'1'&x"15F1",'1'&x"15F2",'1'&x"15F3",'1'&x"15F4",'1'&x"15F5",'1'&x"15F6",'1'&x"15F7",'1'&x"15F8",'1'&x"15F9",'1'&x"15FA",'1'&x"15FB",'1'&x"15FC",'1'&x"15FD",'1'&x"15FE",'1'&x"15FF",
+--'1'&x"1600",'1'&x"1601",'1'&x"1602",'1'&x"1603",'1'&x"1604",'1'&x"1605",'1'&x"1606",'1'&x"1607",'1'&x"1608",'1'&x"1609",'1'&x"160A",'1'&x"160B",'1'&x"160C",'1'&x"160D",'1'&x"160E",'1'&x"160F",
+--'1'&x"1610",'1'&x"1611",'1'&x"1612",'1'&x"1613",'1'&x"1614",'1'&x"1615",'1'&x"1616",'1'&x"1617",'1'&x"1618",'1'&x"1619",'1'&x"161A",'1'&x"161B",'1'&x"161C",'1'&x"161D",'1'&x"161E",'1'&x"161F",
+--'1'&x"1620",'1'&x"1621",'1'&x"1622",'1'&x"1623",'1'&x"1624",'1'&x"1625",'1'&x"1626",'1'&x"1627",'1'&x"1628",'1'&x"1629",'1'&x"162A",'1'&x"162B",'1'&x"162C",'1'&x"162D",'1'&x"162E",'1'&x"162F",
+--'1'&x"1630",'1'&x"1631",'1'&x"1632",'1'&x"1633",'1'&x"1634",'1'&x"1635",'1'&x"1636",'1'&x"1637",'1'&x"1638",'1'&x"1639",'1'&x"163A",'1'&x"163B",'1'&x"163C",'1'&x"163D",'1'&x"163E",'1'&x"163F",
+--'1'&x"1640",'1'&x"1641",'1'&x"1642",'1'&x"1643",'1'&x"1644",'1'&x"1645",'1'&x"1646",'1'&x"1647",'1'&x"1648",'1'&x"1649",'1'&x"164A",'1'&x"164B",'1'&x"164C",'1'&x"164D",'1'&x"164E",'1'&x"164F",
+--'1'&x"1650",'1'&x"1651",'1'&x"1652",'1'&x"1653",'1'&x"1654",'1'&x"1655",'1'&x"1656",'1'&x"1657",'1'&x"1658",'1'&x"1659",'1'&x"165A",'1'&x"165B",'1'&x"165C",'1'&x"165D",'1'&x"165E",'1'&x"165F",
+--'1'&x"1660",'1'&x"1661",'1'&x"1662",'1'&x"1663",'1'&x"1664",'1'&x"1665",'1'&x"1666",'1'&x"1667",'1'&x"1668",'1'&x"1669",'1'&x"166A",'1'&x"166B",'1'&x"166C",'1'&x"166D",'1'&x"166E",'1'&x"166F",
+--'1'&x"1670",'1'&x"1671",'1'&x"1672",'1'&x"1673",'1'&x"1674",'1'&x"1675",'1'&x"1676",'1'&x"1677",'1'&x"1678",'1'&x"1679",'1'&x"167A",'1'&x"167B",'1'&x"167C",'1'&x"167D",'1'&x"167E",'1'&x"167F",
+--'1'&x"1680",'1'&x"1681",'1'&x"1682",'1'&x"1683",'1'&x"1684",'1'&x"1685",'1'&x"1686",'1'&x"1687",'1'&x"1688",'1'&x"1689",'1'&x"168A",'1'&x"168B",'1'&x"168C",'1'&x"168D",'1'&x"168E",'1'&x"168F",
+--'1'&x"1690",'1'&x"1691",'1'&x"1692",'1'&x"1693",'1'&x"1694",'1'&x"1695",'1'&x"1696",'1'&x"1697",'1'&x"1698",'1'&x"1699",'1'&x"169A",'1'&x"169B",'1'&x"169C",'1'&x"169D",'1'&x"169E",'1'&x"169F",
+--'1'&x"16A0",'1'&x"16A1",'1'&x"16A2",'1'&x"16A3",'1'&x"16A4",'1'&x"16A5",'1'&x"16A6",'1'&x"16A7",'1'&x"16A8",'1'&x"16A9",'1'&x"16AA",'1'&x"16AB",'1'&x"16AC",'1'&x"16AD",'1'&x"16AE",'1'&x"16AF",
+--'1'&x"16B0",'1'&x"16B1",'1'&x"16B2",'1'&x"16B3",'1'&x"16B4",'1'&x"16B5",'1'&x"16B6",'1'&x"16B7",'1'&x"16B8",'1'&x"16B9",'1'&x"16BA",'1'&x"16BB",'1'&x"16BC",'1'&x"16BD",'1'&x"16BE",'1'&x"16BF",
+--'1'&x"16C0",'1'&x"16C1",'1'&x"16C2",'1'&x"16C3",'1'&x"16C4",'1'&x"16C5",'1'&x"16C6",'1'&x"16C7",'1'&x"16C8",'1'&x"16C9",'1'&x"16CA",'1'&x"16CB",'1'&x"16CC",'1'&x"16CD",'1'&x"16CE",'1'&x"16CF",
+--'1'&x"16D0",'1'&x"16D1",'1'&x"16D2",'1'&x"16D3",'1'&x"16D4",'1'&x"16D5",'1'&x"16D6",'1'&x"16D7",'1'&x"16D8",'1'&x"16D9",'1'&x"16DA",'1'&x"16DB",'1'&x"16DC",'1'&x"16DD",'1'&x"16DE",'1'&x"16DF",
+--'1'&x"16E0",'1'&x"16E1",'1'&x"16E2",'1'&x"16E3",'1'&x"16E4",'1'&x"16E5",'1'&x"16E6",'1'&x"16E7",'1'&x"16E8",'1'&x"16E9",'1'&x"16EA",'1'&x"16EB",'1'&x"16EC",'1'&x"16ED",'1'&x"16EE",'1'&x"16EF",
+--'1'&x"16F0",'1'&x"16F1",'1'&x"16F2",'1'&x"16F3",'1'&x"16F4",'1'&x"16F5",'1'&x"16F6",'1'&x"16F7",'1'&x"16F8",'1'&x"16F9",'1'&x"16FA",'1'&x"16FB",'1'&x"16FC",'1'&x"16FD",'1'&x"16FE",'1'&x"16FF",
+--'1'&x"1700",'1'&x"1701",'1'&x"1702",'1'&x"1703",'1'&x"1704",'1'&x"1705",'1'&x"1706",'1'&x"1707",'1'&x"1708",'1'&x"1709",'1'&x"170A",'1'&x"170B",'1'&x"170C",'1'&x"170D",'1'&x"170E",'1'&x"170F",
+--'1'&x"1710",'1'&x"1711",'1'&x"1712",'1'&x"1713",'1'&x"1714",'1'&x"1715",'1'&x"1716",'1'&x"1717",'1'&x"1718",'1'&x"1719",'1'&x"171A",'1'&x"171B",'1'&x"171C",'1'&x"171D",'1'&x"171E",'1'&x"171F",
+--'1'&x"1720",'1'&x"1721",'1'&x"1722",'1'&x"1723",'1'&x"1724",'1'&x"1725",'1'&x"1726",'1'&x"1727",'1'&x"1728",'1'&x"1729",'1'&x"172A",'1'&x"172B",'1'&x"172C",'1'&x"172D",'1'&x"172E",'1'&x"172F",
+--'1'&x"1730",'1'&x"1731",'1'&x"1732",'1'&x"1733",'1'&x"1734",'1'&x"1735",'1'&x"1736",'1'&x"1737",'1'&x"1738",'1'&x"1739",'1'&x"173A",'1'&x"173B",'1'&x"173C",'1'&x"173D",'1'&x"173E",'1'&x"173F",
+--'1'&x"1740",'1'&x"1741",'1'&x"1742",'1'&x"1743",'1'&x"1744",'1'&x"1745",'1'&x"1746",'1'&x"1747",'1'&x"1748",'1'&x"1749",'1'&x"174A",'1'&x"174B",'1'&x"174C",'1'&x"174D",'1'&x"174E",'1'&x"174F",
+--'1'&x"1750",'1'&x"1751",'1'&x"1752",'1'&x"1753",'1'&x"1754",'1'&x"1755",'1'&x"1756",'1'&x"1757",'1'&x"1758",'1'&x"1759",'1'&x"175A",'1'&x"175B",'1'&x"175C",'1'&x"175D",'1'&x"175E",'1'&x"175F",
+--'1'&x"1760",'1'&x"1761",'1'&x"1762",'1'&x"1763",'1'&x"1764",'1'&x"1765",'1'&x"1766",'1'&x"1767",'1'&x"1768",'1'&x"1769",'1'&x"176A",'1'&x"176B",'1'&x"176C",'1'&x"176D",'1'&x"176E",'1'&x"176F",
+--'1'&x"1770",'1'&x"1771",'1'&x"1772",'1'&x"1773",'1'&x"1774",'1'&x"1775",'1'&x"1776",'1'&x"1777",'1'&x"1778",'1'&x"1779",'1'&x"177A",'1'&x"177B",'1'&x"177C",'1'&x"177D",'1'&x"177E",'1'&x"177F",
+--'1'&x"1780",'1'&x"1781",'1'&x"1782",'1'&x"1783",'1'&x"1784",'1'&x"1785",'1'&x"1786",'1'&x"1787",'1'&x"1788",'1'&x"1789",'1'&x"178A",'1'&x"178B",'1'&x"178C",'1'&x"178D",'1'&x"178E",'1'&x"178F",
+--'1'&x"1790",'1'&x"1791",'1'&x"1792",'1'&x"1793",'1'&x"1794",'1'&x"1795",'1'&x"1796",'1'&x"1797",'1'&x"1798",'1'&x"1799",'1'&x"179A",'1'&x"179B",'1'&x"179C",'1'&x"179D",'1'&x"179E",'1'&x"179F",
+--'1'&x"17A0",'1'&x"17A1",'1'&x"17A2",'1'&x"17A3",'1'&x"17A4",'1'&x"17A5",'1'&x"17A6",'1'&x"17A7",'1'&x"17A8",'1'&x"17A9",'1'&x"17AA",'1'&x"17AB",'1'&x"17AC",'1'&x"17AD",'1'&x"17AE",'1'&x"17AF",
+--'1'&x"17B0",'1'&x"17B1",'1'&x"17B2",'1'&x"17B3",'1'&x"17B4",'1'&x"17B5",'1'&x"17B6",'1'&x"17B7",'1'&x"17B8",'1'&x"17B9",'1'&x"17BA",'1'&x"17BB",'1'&x"17BC",'1'&x"17BD",'1'&x"17BE",'1'&x"17BF",
+--'1'&x"17C0",'1'&x"17C1",'1'&x"17C2",'1'&x"17C3",'1'&x"17C4",'1'&x"17C5",'1'&x"17C6",'1'&x"17C7",'1'&x"17C8",'1'&x"17C9",'1'&x"17CA",'1'&x"17CB",'1'&x"17CC",'1'&x"17CD",'1'&x"17CE",'1'&x"17CF",
+--'1'&x"17D0",'1'&x"17D1",'1'&x"17D2",'1'&x"17D3",'1'&x"17D4",'1'&x"17D5",'1'&x"17D6",'1'&x"17D7",'1'&x"17D8",'1'&x"17D9",'1'&x"17DA",'1'&x"17DB",'1'&x"17DC",'1'&x"17DD",'1'&x"17DE",'1'&x"17DF",
+--'1'&x"17E0",'1'&x"17E1",'1'&x"17E2",'1'&x"17E3",'1'&x"17E4",'1'&x"17E5",'1'&x"17E6",'1'&x"17E7",'1'&x"17E8",'1'&x"17E9",'1'&x"17EA",'1'&x"17EB",'1'&x"17EC",'1'&x"17ED",'1'&x"17EE",'1'&x"17EF",
+--'1'&x"17F0",'1'&x"17F1",'1'&x"17F2",'1'&x"17F3",'1'&x"17F4",'1'&x"17F5",'1'&x"17F6",'1'&x"17F7",'1'&x"17F8",'1'&x"17F9",'1'&x"17FA",'1'&x"17FB",'1'&x"17FC",'1'&x"17FD",'1'&x"17FE",'1'&x"17FF",
+--'1'&x"1800",'1'&x"1801",'1'&x"1802",'1'&x"1803",'1'&x"1804",'1'&x"1805",'1'&x"1806",'1'&x"1807",'1'&x"1808",'1'&x"1809",'1'&x"180A",'1'&x"180B",'1'&x"180C",'1'&x"180D",'1'&x"180E",'1'&x"180F",
+--'1'&x"1810",'1'&x"1811",'1'&x"1812",'1'&x"1813",'1'&x"1814",'1'&x"1815",'1'&x"1816",'1'&x"1817",'1'&x"1818",'1'&x"1819",'1'&x"181A",'1'&x"181B",'1'&x"181C",'1'&x"181D",'1'&x"181E",'1'&x"181F",
+--'1'&x"1820",'1'&x"1821",'1'&x"1822",'1'&x"1823",'1'&x"1824",'1'&x"1825",'1'&x"1826",'1'&x"1827",'1'&x"1828",'1'&x"1829",'1'&x"182A",'1'&x"182B",'1'&x"182C",'1'&x"182D",'1'&x"182E",'1'&x"182F",
+--'1'&x"1830",'1'&x"1831",'1'&x"1832",'1'&x"1833",'1'&x"1834",'1'&x"1835",'1'&x"1836",'1'&x"1837",'1'&x"1838",'1'&x"1839",'1'&x"183A",'1'&x"183B",'1'&x"183C",'1'&x"183D",'1'&x"183E",'1'&x"183F",
+--'1'&x"1840",'1'&x"1841",'1'&x"1842",'1'&x"1843",'1'&x"1844",'1'&x"1845",'1'&x"1846",'1'&x"1847",'1'&x"1848",'1'&x"1849",'1'&x"184A",'1'&x"184B",'1'&x"184C",'1'&x"184D",'1'&x"184E",'1'&x"184F",
+--'1'&x"1850",'1'&x"1851",'1'&x"1852",'1'&x"1853",'1'&x"1854",'1'&x"1855",'1'&x"1856",'1'&x"1857",'1'&x"1858",'1'&x"1859",'1'&x"185A",'1'&x"185B",'1'&x"185C",'1'&x"185D",'1'&x"185E",'1'&x"185F",
+--'1'&x"1860",'1'&x"1861",'1'&x"1862",'1'&x"1863",'1'&x"1864",'1'&x"1865",'1'&x"1866",'1'&x"1867",'1'&x"1868",'1'&x"1869",'1'&x"186A",'1'&x"186B",'1'&x"186C",'1'&x"186D",'1'&x"186E",'1'&x"186F",
+--'1'&x"1870",'1'&x"1871",'1'&x"1872",'1'&x"1873",'1'&x"1874",'1'&x"1875",'1'&x"1876",'1'&x"1877",'1'&x"1878",'1'&x"1879",'1'&x"187A",'1'&x"187B",'1'&x"187C",'1'&x"187D",'1'&x"187E",'1'&x"187F",
+--'1'&x"1880",'1'&x"1881",'1'&x"1882",'1'&x"1883",'1'&x"1884",'1'&x"1885",'1'&x"1886",'1'&x"1887",'1'&x"1888",'1'&x"1889",'1'&x"188A",'1'&x"188B",'1'&x"188C",'1'&x"188D",'1'&x"188E",'1'&x"188F",
+--'1'&x"1890",'1'&x"1891",'1'&x"1892",'1'&x"1893",'1'&x"1894",'1'&x"1895",'1'&x"1896",'1'&x"1897",'1'&x"1898",'1'&x"1899",'1'&x"189A",'1'&x"189B",'1'&x"189C",'1'&x"189D",'1'&x"189E",'1'&x"189F",
+--'1'&x"18A0",'1'&x"18A1",'1'&x"18A2",'1'&x"18A3",'1'&x"18A4",'1'&x"18A5",'1'&x"18A6",'1'&x"18A7",'1'&x"18A8",'1'&x"18A9",'1'&x"18AA",'1'&x"18AB",'1'&x"18AC",'1'&x"18AD",'1'&x"18AE",'1'&x"18AF",
+--'1'&x"18B0",'1'&x"18B1",'1'&x"18B2",'1'&x"18B3",'1'&x"18B4",'1'&x"18B5",'1'&x"18B6",'1'&x"18B7",'1'&x"18B8",'1'&x"18B9",'1'&x"18BA",'1'&x"18BB",'1'&x"18BC",'1'&x"18BD",'1'&x"18BE",'1'&x"18BF",
+--'1'&x"18C0",'1'&x"18C1",'1'&x"18C2",'1'&x"18C3",'1'&x"18C4",'1'&x"18C5",'1'&x"18C6",'1'&x"18C7",'1'&x"18C8",'1'&x"18C9",'1'&x"18CA",'1'&x"18CB",'1'&x"18CC",'1'&x"18CD",'1'&x"18CE",'1'&x"18CF",
+--'1'&x"18D0",'1'&x"18D1",'1'&x"18D2",'1'&x"18D3",'1'&x"18D4",'1'&x"18D5",'1'&x"18D6",'1'&x"18D7",'1'&x"18D8",'1'&x"18D9",'1'&x"18DA",'1'&x"18DB",'1'&x"18DC",'1'&x"18DD",'1'&x"18DE",'1'&x"18DF",
+--'1'&x"18E0",'1'&x"18E1",'1'&x"18E2",'1'&x"18E3",'1'&x"18E4",'1'&x"18E5",'1'&x"18E6",'1'&x"18E7",'1'&x"18E8",'1'&x"18E9",'1'&x"18EA",'1'&x"18EB",'1'&x"18EC",'1'&x"18ED",'1'&x"18EE",'1'&x"18EF",
+--'1'&x"18F0",'1'&x"18F1",'1'&x"18F2",'1'&x"18F3",'1'&x"18F4",'1'&x"18F5",'1'&x"18F6",'1'&x"18F7",'1'&x"18F8",'1'&x"18F9",'1'&x"18FA",'1'&x"18FB",'1'&x"18FC",'1'&x"18FD",'1'&x"18FE",'1'&x"18FF",
+--'1'&x"1900",'1'&x"1901",'1'&x"1902",'1'&x"1903",'1'&x"1904",'1'&x"1905",'1'&x"1906",'1'&x"1907",'1'&x"1908",'1'&x"1909",'1'&x"190A",'1'&x"190B",'1'&x"190C",'1'&x"190D",'1'&x"190E",'1'&x"190F",
+--'1'&x"1910",'1'&x"1911",'1'&x"1912",'1'&x"1913",'1'&x"1914",'1'&x"1915",'1'&x"1916",'1'&x"1917",'1'&x"1918",'1'&x"1919",'1'&x"191A",'1'&x"191B",'1'&x"191C",'1'&x"191D",'1'&x"191E",'1'&x"191F",
+--'1'&x"1920",'1'&x"1921",'1'&x"1922",'1'&x"1923",'1'&x"1924",'1'&x"1925",'1'&x"1926",'1'&x"1927",'1'&x"1928",'1'&x"1929",'1'&x"192A",'1'&x"192B",'1'&x"192C",'1'&x"192D",'1'&x"192E",'1'&x"192F",
+--'1'&x"1930",'1'&x"1931",'1'&x"1932",'1'&x"1933",'1'&x"1934",'1'&x"1935",'1'&x"1936",'1'&x"1937",'1'&x"1938",'1'&x"1939",'1'&x"193A",'1'&x"193B",'1'&x"193C",'1'&x"193D",'1'&x"193E",'1'&x"193F",
+--'1'&x"1940",'1'&x"1941",'1'&x"1942",'1'&x"1943",'1'&x"1944",'1'&x"1945",'1'&x"1946",'1'&x"1947",'1'&x"1948",'1'&x"1949",'1'&x"194A",'1'&x"194B",'1'&x"194C",'1'&x"194D",'1'&x"194E",'1'&x"194F",
+--'1'&x"1950",'1'&x"1951",'1'&x"1952",'1'&x"1953",'1'&x"1954",'1'&x"1955",'1'&x"1956",'1'&x"1957",'1'&x"1958",'1'&x"1959",'1'&x"195A",'1'&x"195B",'1'&x"195C",'1'&x"195D",'1'&x"195E",'1'&x"195F",
+--'1'&x"1960",'1'&x"1961",'1'&x"1962",'1'&x"1963",'1'&x"1964",'1'&x"1965",'1'&x"1966",'1'&x"1967",'1'&x"1968",'1'&x"1969",'1'&x"196A",'1'&x"196B",'1'&x"196C",'1'&x"196D",'1'&x"196E",'1'&x"196F",
+--'1'&x"1970",'1'&x"1971",'1'&x"1972",'1'&x"1973",'1'&x"1974",'1'&x"1975",'1'&x"1976",'1'&x"1977",'1'&x"1978",'1'&x"1979",'1'&x"197A",'1'&x"197B",'1'&x"197C",'1'&x"197D",'1'&x"197E",'1'&x"197F",
+--'1'&x"1980",'1'&x"1981",'1'&x"1982",'1'&x"1983",'1'&x"1984",'1'&x"1985",'1'&x"1986",'1'&x"1987",'1'&x"1988",'1'&x"1989",'1'&x"198A",'1'&x"198B",'1'&x"198C",'1'&x"198D",'1'&x"198E",'1'&x"198F",
+--'1'&x"1990",'1'&x"1991",'1'&x"1992",'1'&x"1993",'1'&x"1994",'1'&x"1995",'1'&x"1996",'1'&x"1997",'1'&x"1998",'1'&x"1999",'1'&x"199A",'1'&x"199B",'1'&x"199C",'1'&x"199D",'1'&x"199E",'1'&x"199F",
+--'1'&x"19A0",'1'&x"19A1",'1'&x"19A2",'1'&x"19A3",'1'&x"19A4",'1'&x"19A5",'1'&x"19A6",'1'&x"19A7",'1'&x"19A8",'1'&x"19A9",'1'&x"19AA",'1'&x"19AB",'1'&x"19AC",'1'&x"19AD",'1'&x"19AE",'1'&x"19AF",
+--'1'&x"19B0",'1'&x"19B1",'1'&x"19B2",'1'&x"19B3",'1'&x"19B4",'1'&x"19B5",'1'&x"19B6",'1'&x"19B7",'1'&x"19B8",'1'&x"19B9",'1'&x"19BA",'1'&x"19BB",'1'&x"19BC",'1'&x"19BD",'1'&x"19BE",'1'&x"19BF",
+--'1'&x"19C0",'1'&x"19C1",'1'&x"19C2",'1'&x"19C3",'1'&x"19C4",'1'&x"19C5",'1'&x"19C6",'1'&x"19C7",'1'&x"19C8",'1'&x"19C9",'1'&x"19CA",'1'&x"19CB",'1'&x"19CC",'1'&x"19CD",'1'&x"19CE",'1'&x"19CF",
+--'1'&x"19D0",'1'&x"19D1",'1'&x"19D2",'1'&x"19D3",'1'&x"19D4",'1'&x"19D5",'1'&x"19D6",'1'&x"19D7",'1'&x"19D8",'1'&x"19D9",'1'&x"19DA",'1'&x"19DB",'1'&x"19DC",'1'&x"19DD",'1'&x"19DE",'1'&x"19DF",
+--'1'&x"19E0",'1'&x"19E1",'1'&x"19E2",'1'&x"19E3",'1'&x"19E4",'1'&x"19E5",'1'&x"19E6",'1'&x"19E7",'1'&x"19E8",'1'&x"19E9",'1'&x"19EA",'1'&x"19EB",'1'&x"19EC",'1'&x"19ED",'1'&x"19EE",'1'&x"19EF",
+--'1'&x"19F0",'1'&x"19F1",'1'&x"19F2",'1'&x"19F3",'1'&x"19F4",'1'&x"19F5",'1'&x"19F6",'1'&x"19F7",'1'&x"19F8",'1'&x"19F9",'1'&x"19FA",'1'&x"19FB",'1'&x"19FC",'1'&x"19FD",'1'&x"19FE",'1'&x"19FF",
+--'1'&x"1A00",'1'&x"1A01",'1'&x"1A02",'1'&x"1A03",'1'&x"1A04",'1'&x"1A05",'1'&x"1A06",'1'&x"1A07",'1'&x"1A08",'1'&x"1A09",'1'&x"1A0A",'1'&x"1A0B",'1'&x"1A0C",'1'&x"1A0D",'1'&x"1A0E",'1'&x"1A0F",
+--'1'&x"1A10",'1'&x"1A11",'1'&x"1A12",'1'&x"1A13",'1'&x"1A14",'1'&x"1A15",'1'&x"1A16",'1'&x"1A17",'1'&x"1A18",'1'&x"1A19",'1'&x"1A1A",'1'&x"1A1B",'1'&x"1A1C",'1'&x"1A1D",'1'&x"1A1E",'1'&x"1A1F",
+--'1'&x"1A20",'1'&x"1A21",'1'&x"1A22",'1'&x"1A23",'1'&x"1A24",'1'&x"1A25",'1'&x"1A26",'1'&x"1A27",'1'&x"1A28",'1'&x"1A29",'1'&x"1A2A",'1'&x"1A2B",'1'&x"1A2C",'1'&x"1A2D",'1'&x"1A2E",'1'&x"1A2F",
+--'1'&x"1A30",'1'&x"1A31",'1'&x"1A32",'1'&x"1A33",'1'&x"1A34",'1'&x"1A35",'1'&x"1A36",'1'&x"1A37",'1'&x"1A38",'1'&x"1A39",'1'&x"1A3A",'1'&x"1A3B",'1'&x"1A3C",'1'&x"1A3D",'1'&x"1A3E",'1'&x"1A3F",
+--'1'&x"1A40",'1'&x"1A41",'1'&x"1A42",'1'&x"1A43",'1'&x"1A44",'1'&x"1A45",'1'&x"1A46",'1'&x"1A47",'1'&x"1A48",'1'&x"1A49",'1'&x"1A4A",'1'&x"1A4B",'1'&x"1A4C",'1'&x"1A4D",'1'&x"1A4E",'1'&x"1A4F",
+--'1'&x"1A50",'1'&x"1A51",'1'&x"1A52",'1'&x"1A53",'1'&x"1A54",'1'&x"1A55",'1'&x"1A56",'1'&x"1A57",'1'&x"1A58",'1'&x"1A59",'1'&x"1A5A",'1'&x"1A5B",'1'&x"1A5C",'1'&x"1A5D",'1'&x"1A5E",'1'&x"1A5F",
+--'1'&x"1A60",'1'&x"1A61",'1'&x"1A62",'1'&x"1A63",'1'&x"1A64",'1'&x"1A65",'1'&x"1A66",'1'&x"1A67",'1'&x"1A68",'1'&x"1A69",'1'&x"1A6A",'1'&x"1A6B",'1'&x"1A6C",'1'&x"1A6D",'1'&x"1A6E",'1'&x"1A6F",
+--'1'&x"1A70",'1'&x"1A71",'1'&x"1A72",'1'&x"1A73",'1'&x"1A74",'1'&x"1A75",'1'&x"1A76",'1'&x"1A77",'1'&x"1A78",'1'&x"1A79",'1'&x"1A7A",'1'&x"1A7B",'1'&x"1A7C",'1'&x"1A7D",'1'&x"1A7E",'1'&x"1A7F",
+--'1'&x"1A80",'1'&x"1A81",'1'&x"1A82",'1'&x"1A83",'1'&x"1A84",'1'&x"1A85",'1'&x"1A86",'1'&x"1A87",'1'&x"1A88",'1'&x"1A89",'1'&x"1A8A",'1'&x"1A8B",'1'&x"1A8C",'1'&x"1A8D",'1'&x"1A8E",'1'&x"1A8F",
+--'1'&x"1A90",'1'&x"1A91",'1'&x"1A92",'1'&x"1A93",'1'&x"1A94",'1'&x"1A95",'1'&x"1A96",'1'&x"1A97",'1'&x"1A98",'1'&x"1A99",'1'&x"1A9A",'1'&x"1A9B",'1'&x"1A9C",'1'&x"1A9D",'1'&x"1A9E",'1'&x"1A9F",
+--'1'&x"1AA0",'1'&x"1AA1",'1'&x"1AA2",'1'&x"1AA3",'1'&x"1AA4",'1'&x"1AA5",'1'&x"1AA6",'1'&x"1AA7",'1'&x"1AA8",'1'&x"1AA9",'1'&x"1AAA",'1'&x"1AAB",'1'&x"1AAC",'1'&x"1AAD",'1'&x"1AAE",'1'&x"1AAF",
+--'1'&x"1AB0",'1'&x"1AB1",'1'&x"1AB2",'1'&x"1AB3",'1'&x"1AB4",'1'&x"1AB5",'1'&x"1AB6",'1'&x"1AB7",'1'&x"1AB8",'1'&x"1AB9",'1'&x"1ABA",'1'&x"1ABB",'1'&x"1ABC",'1'&x"1ABD",'1'&x"1ABE",'1'&x"1ABF",
+--'1'&x"1AC0",'1'&x"1AC1",'1'&x"1AC2",'1'&x"1AC3",'1'&x"1AC4",'1'&x"1AC5",'1'&x"1AC6",'1'&x"1AC7",'1'&x"1AC8",'1'&x"1AC9",'1'&x"1ACA",'1'&x"1ACB",'1'&x"1ACC",'1'&x"1ACD",'1'&x"1ACE",'1'&x"1ACF",
+--'1'&x"1AD0",'1'&x"1AD1",'1'&x"1AD2",'1'&x"1AD3",'1'&x"1AD4",'1'&x"1AD5",'1'&x"1AD6",'1'&x"1AD7",'1'&x"1AD8",'1'&x"1AD9",'1'&x"1ADA",'1'&x"1ADB",'1'&x"1ADC",'1'&x"1ADD",'1'&x"1ADE",'1'&x"1ADF",
+--'1'&x"1AE0",'1'&x"1AE1",'1'&x"1AE2",'1'&x"1AE3",'1'&x"1AE4",'1'&x"1AE5",'1'&x"1AE6",'1'&x"1AE7",'1'&x"1AE8",'1'&x"1AE9",'1'&x"1AEA",'1'&x"1AEB",'1'&x"1AEC",'1'&x"1AED",'1'&x"1AEE",'1'&x"1AEF",
+--'1'&x"1AF0",'1'&x"1AF1",'1'&x"1AF2",'1'&x"1AF3",'1'&x"1AF4",'1'&x"1AF5",'1'&x"1AF6",'1'&x"1AF7",'1'&x"1AF8",'1'&x"1AF9",'1'&x"1AFA",'1'&x"1AFB",'1'&x"1AFC",'1'&x"1AFD",'1'&x"1AFE",'1'&x"1AFF",
+--'1'&x"1B00",'1'&x"1B01",'1'&x"1B02",'1'&x"1B03",'1'&x"1B04",'1'&x"1B05",'1'&x"1B06",'1'&x"1B07",'1'&x"1B08",'1'&x"1B09",'1'&x"1B0A",'1'&x"1B0B",'1'&x"1B0C",'1'&x"1B0D",'1'&x"1B0E",'1'&x"1B0F",
+--'1'&x"1B10",'1'&x"1B11",'1'&x"1B12",'1'&x"1B13",'1'&x"1B14",'1'&x"1B15",'1'&x"1B16",'1'&x"1B17",'1'&x"1B18",'1'&x"1B19",'1'&x"1B1A",'1'&x"1B1B",'1'&x"1B1C",'1'&x"1B1D",'1'&x"1B1E",'1'&x"1B1F",
+--'1'&x"1B20",'1'&x"1B21",'1'&x"1B22",'1'&x"1B23",'1'&x"1B24",'1'&x"1B25",'1'&x"1B26",'1'&x"1B27",'1'&x"1B28",'1'&x"1B29",'1'&x"1B2A",'1'&x"1B2B",'1'&x"1B2C",'1'&x"1B2D",'1'&x"1B2E",'1'&x"1B2F",
+--'1'&x"1B30",'1'&x"1B31",'1'&x"1B32",'1'&x"1B33",'1'&x"1B34",'1'&x"1B35",'1'&x"1B36",'1'&x"1B37",'1'&x"1B38",'1'&x"1B39",'1'&x"1B3A",'1'&x"1B3B",'1'&x"1B3C",'1'&x"1B3D",'1'&x"1B3E",'1'&x"1B3F",
+--'1'&x"1B40",'1'&x"1B41",'1'&x"1B42",'1'&x"1B43",'1'&x"1B44",'1'&x"1B45",'1'&x"1B46",'1'&x"1B47",'1'&x"1B48",'1'&x"1B49",'1'&x"1B4A",'1'&x"1B4B",'1'&x"1B4C",'1'&x"1B4D",'1'&x"1B4E",'1'&x"1B4F",
+--'1'&x"1B50",'1'&x"1B51",'1'&x"1B52",'1'&x"1B53",'1'&x"1B54",'1'&x"1B55",'1'&x"1B56",'1'&x"1B57",'1'&x"1B58",'1'&x"1B59",'1'&x"1B5A",'1'&x"1B5B",'1'&x"1B5C",'1'&x"1B5D",'1'&x"1B5E",'1'&x"1B5F",
+--'1'&x"1B60",'1'&x"1B61",'1'&x"1B62",'1'&x"1B63",'1'&x"1B64",'1'&x"1B65",'1'&x"1B66",'1'&x"1B67",'1'&x"1B68",'1'&x"1B69",'1'&x"1B6A",'1'&x"1B6B",'1'&x"1B6C",'1'&x"1B6D",'1'&x"1B6E",'1'&x"1B6F",
+--'1'&x"1B70",'1'&x"1B71",'1'&x"1B72",'1'&x"1B73",'1'&x"1B74",'1'&x"1B75",'1'&x"1B76",'1'&x"1B77",'1'&x"1B78",'1'&x"1B79",'1'&x"1B7A",'1'&x"1B7B",'1'&x"1B7C",'1'&x"1B7D",'1'&x"1B7E",'1'&x"1B7F",
+--'1'&x"1B80",'1'&x"1B81",'1'&x"1B82",'1'&x"1B83",'1'&x"1B84",'1'&x"1B85",'1'&x"1B86",'1'&x"1B87",'1'&x"1B88",'1'&x"1B89",'1'&x"1B8A",'1'&x"1B8B",'1'&x"1B8C",'1'&x"1B8D",'1'&x"1B8E",'1'&x"1B8F",
+--'1'&x"1B90",'1'&x"1B91",'1'&x"1B92",'1'&x"1B93",'1'&x"1B94",'1'&x"1B95",'1'&x"1B96",'1'&x"1B97",'1'&x"1B98",'1'&x"1B99",'1'&x"1B9A",'1'&x"1B9B",'1'&x"1B9C",'1'&x"1B9D",'1'&x"1B9E",'1'&x"1B9F",
+--'1'&x"1BA0",'1'&x"1BA1",'1'&x"1BA2",'1'&x"1BA3",'1'&x"1BA4",'1'&x"1BA5",'1'&x"1BA6",'1'&x"1BA7",'1'&x"1BA8",'1'&x"1BA9",'1'&x"1BAA",'1'&x"1BAB",'1'&x"1BAC",'1'&x"1BAD",'1'&x"1BAE",'1'&x"1BAF",
+--'1'&x"1BB0",'1'&x"1BB1",'1'&x"1BB2",'1'&x"1BB3",'1'&x"1BB4",'1'&x"1BB5",'1'&x"1BB6",'1'&x"1BB7",'1'&x"1BB8",'1'&x"1BB9",'1'&x"1BBA",'1'&x"1BBB",'1'&x"1BBC",'1'&x"1BBD",'1'&x"1BBE",'1'&x"1BBF",
+--'1'&x"1BC0",'1'&x"1BC1",'1'&x"1BC2",'1'&x"1BC3",'1'&x"1BC4",'1'&x"1BC5",'1'&x"1BC6",'1'&x"1BC7",'1'&x"1BC8",'1'&x"1BC9",'1'&x"1BCA",'1'&x"1BCB",'1'&x"1BCC",'1'&x"1BCD",'1'&x"1BCE",'1'&x"1BCF",
+--'1'&x"1BD0",'1'&x"1BD1",'1'&x"1BD2",'1'&x"1BD3",'1'&x"1BD4",'1'&x"1BD5",'1'&x"1BD6",'1'&x"1BD7",'1'&x"1BD8",'1'&x"1BD9",'1'&x"1BDA",'1'&x"1BDB",'1'&x"1BDC",'1'&x"1BDD",'1'&x"1BDE",'1'&x"1BDF",
+--'1'&x"1BE0",'1'&x"1BE1",'1'&x"1BE2",'1'&x"1BE3",'1'&x"1BE4",'1'&x"1BE5",'1'&x"1BE6",'1'&x"1BE7",'1'&x"1BE8",'1'&x"1BE9",'1'&x"1BEA",'1'&x"1BEB",'1'&x"1BEC",'1'&x"1BED",'1'&x"1BEE",'1'&x"1BEF",
+--'1'&x"1BF0",'1'&x"1BF1",'1'&x"1BF2",'1'&x"1BF3",'1'&x"1BF4",'1'&x"1BF5",'1'&x"1BF6",'1'&x"1BF7",'1'&x"1BF8",'1'&x"1BF9",'1'&x"1BFA",'1'&x"1BFB",'1'&x"1BFC",'1'&x"1BFD",'1'&x"1BFE",'1'&x"1BFF",
+--'1'&x"1C00",'1'&x"1C01",'1'&x"1C02",'1'&x"1C03",'1'&x"1C04",'1'&x"1C05",'1'&x"1C06",'1'&x"1C07",'1'&x"1C08",'1'&x"1C09",'1'&x"1C0A",'1'&x"1C0B",'1'&x"1C0C",'1'&x"1C0D",'1'&x"1C0E",'1'&x"1C0F",
+--'1'&x"1C10",'1'&x"1C11",'1'&x"1C12",'1'&x"1C13",'1'&x"1C14",'1'&x"1C15",'1'&x"1C16",'1'&x"1C17",'1'&x"1C18",'1'&x"1C19",'1'&x"1C1A",'1'&x"1C1B",'1'&x"1C1C",'1'&x"1C1D",'1'&x"1C1E",'1'&x"1C1F",
+--'1'&x"1C20",'1'&x"1C21",'1'&x"1C22",'1'&x"1C23",'1'&x"1C24",'1'&x"1C25",'1'&x"1C26",'1'&x"1C27",'1'&x"1C28",'1'&x"1C29",'1'&x"1C2A",'1'&x"1C2B",'1'&x"1C2C",'1'&x"1C2D",'1'&x"1C2E",'1'&x"1C2F",
+--'1'&x"1C30",'1'&x"1C31",'1'&x"1C32",'1'&x"1C33",'1'&x"1C34",'1'&x"1C35",'1'&x"1C36",'1'&x"1C37",'1'&x"1C38",'1'&x"1C39",'1'&x"1C3A",'1'&x"1C3B",'1'&x"1C3C",'1'&x"1C3D",'1'&x"1C3E",'1'&x"1C3F",
+--'1'&x"1C40",'1'&x"1C41",'1'&x"1C42",'1'&x"1C43",'1'&x"1C44",'1'&x"1C45",'1'&x"1C46",'1'&x"1C47",'1'&x"1C48",'1'&x"1C49",'1'&x"1C4A",'1'&x"1C4B",'1'&x"1C4C",'1'&x"1C4D",'1'&x"1C4E",'1'&x"1C4F",
+--'1'&x"1C50",'1'&x"1C51",'1'&x"1C52",'1'&x"1C53",'1'&x"1C54",'1'&x"1C55",'1'&x"1C56",'1'&x"1C57",'1'&x"1C58",'1'&x"1C59",'1'&x"1C5A",'1'&x"1C5B",'1'&x"1C5C",'1'&x"1C5D",'1'&x"1C5E",'1'&x"1C5F",
+--'1'&x"1C60",'1'&x"1C61",'1'&x"1C62",'1'&x"1C63",'1'&x"1C64",'1'&x"1C65",'1'&x"1C66",'1'&x"1C67",'1'&x"1C68",'1'&x"1C69",'1'&x"1C6A",'1'&x"1C6B",'1'&x"1C6C",'1'&x"1C6D",'1'&x"1C6E",'1'&x"1C6F",
+--'1'&x"1C70",'1'&x"1C71",'1'&x"1C72",'1'&x"1C73",'1'&x"1C74",'1'&x"1C75",'1'&x"1C76",'1'&x"1C77",'1'&x"1C78",'1'&x"1C79",'1'&x"1C7A",'1'&x"1C7B",'1'&x"1C7C",'1'&x"1C7D",'1'&x"1C7E",'1'&x"1C7F",
+--'1'&x"1C80",'1'&x"1C81",'1'&x"1C82",'1'&x"1C83",'1'&x"1C84",'1'&x"1C85",'1'&x"1C86",'1'&x"1C87",'1'&x"1C88",'1'&x"1C89",'1'&x"1C8A",'1'&x"1C8B",'1'&x"1C8C",'1'&x"1C8D",'1'&x"1C8E",'1'&x"1C8F",
+--'1'&x"1C90",'1'&x"1C91",'1'&x"1C92",'1'&x"1C93",'1'&x"1C94",'1'&x"1C95",'1'&x"1C96",'1'&x"1C97",'1'&x"1C98",'1'&x"1C99",'1'&x"1C9A",'1'&x"1C9B",'1'&x"1C9C",'1'&x"1C9D",'1'&x"1C9E",'1'&x"1C9F",
+--'1'&x"1CA0",'1'&x"1CA1",'1'&x"1CA2",'1'&x"1CA3",'1'&x"1CA4",'1'&x"1CA5",'1'&x"1CA6",'1'&x"1CA7",'1'&x"1CA8",'1'&x"1CA9",'1'&x"1CAA",'1'&x"1CAB",'1'&x"1CAC",'1'&x"1CAD",'1'&x"1CAE",'1'&x"1CAF",
+--'1'&x"1CB0",'1'&x"1CB1",'1'&x"1CB2",'1'&x"1CB3",'1'&x"1CB4",'1'&x"1CB5",'1'&x"1CB6",'1'&x"1CB7",'1'&x"1CB8",'1'&x"1CB9",'1'&x"1CBA",'1'&x"1CBB",'1'&x"1CBC",'1'&x"1CBD",'1'&x"1CBE",'1'&x"1CBF",
+--'1'&x"1CC0",'1'&x"1CC1",'1'&x"1CC2",'1'&x"1CC3",'1'&x"1CC4",'1'&x"1CC5",'1'&x"1CC6",'1'&x"1CC7",'1'&x"1CC8",'1'&x"1CC9",'1'&x"1CCA",'1'&x"1CCB",'1'&x"1CCC",'1'&x"1CCD",'1'&x"1CCE",'1'&x"1CCF",
+--'1'&x"1CD0",'1'&x"1CD1",'1'&x"1CD2",'1'&x"1CD3",'1'&x"1CD4",'1'&x"1CD5",'1'&x"1CD6",'1'&x"1CD7",'1'&x"1CD8",'1'&x"1CD9",'1'&x"1CDA",'1'&x"1CDB",'1'&x"1CDC",'1'&x"1CDD",'1'&x"1CDE",'1'&x"1CDF",
+--'1'&x"1CE0",'1'&x"1CE1",'1'&x"1CE2",'1'&x"1CE3",'1'&x"1CE4",'1'&x"1CE5",'1'&x"1CE6",'1'&x"1CE7",'1'&x"1CE8",'1'&x"1CE9",'1'&x"1CEA",'1'&x"1CEB",'1'&x"1CEC",'1'&x"1CED",'1'&x"1CEE",'1'&x"1CEF",
+--'1'&x"1CF0",'1'&x"1CF1",'1'&x"1CF2",'1'&x"1CF3",'1'&x"1CF4",'1'&x"1CF5",'1'&x"1CF6",'1'&x"1CF7",'1'&x"1CF8",'1'&x"1CF9",'1'&x"1CFA",'1'&x"1CFB",'1'&x"1CFC",'1'&x"1CFD",'1'&x"1CFE",'1'&x"1CFF",
+--'1'&x"1D00",'1'&x"1D01",'1'&x"1D02",'1'&x"1D03",'1'&x"1D04",'1'&x"1D05",'1'&x"1D06",'1'&x"1D07",'1'&x"1D08",'1'&x"1D09",'1'&x"1D0A",'1'&x"1D0B",'1'&x"1D0C",'1'&x"1D0D",'1'&x"1D0E",'1'&x"1D0F",
+--'1'&x"1D10",'1'&x"1D11",'1'&x"1D12",'1'&x"1D13",'1'&x"1D14",'1'&x"1D15",'1'&x"1D16",'1'&x"1D17",'1'&x"1D18",'1'&x"1D19",'1'&x"1D1A",'1'&x"1D1B",'1'&x"1D1C",'1'&x"1D1D",'1'&x"1D1E",'1'&x"1D1F",
+--'1'&x"1D20",'1'&x"1D21",'1'&x"1D22",'1'&x"1D23",'1'&x"1D24",'1'&x"1D25",'1'&x"1D26",'1'&x"1D27",'1'&x"1D28",'1'&x"1D29",'1'&x"1D2A",'1'&x"1D2B",'1'&x"1D2C",'1'&x"1D2D",'1'&x"1D2E",'1'&x"1D2F",
+--'1'&x"1D30",'1'&x"1D31",'1'&x"1D32",'1'&x"1D33",'1'&x"1D34",'1'&x"1D35",'1'&x"1D36",'1'&x"1D37",'1'&x"1D38",'1'&x"1D39",'1'&x"1D3A",'1'&x"1D3B",'1'&x"1D3C",'1'&x"1D3D",'1'&x"1D3E",'1'&x"1D3F",
+--'1'&x"1D40",'1'&x"1D41",'1'&x"1D42",'1'&x"1D43",'1'&x"1D44",'1'&x"1D45",'1'&x"1D46",'1'&x"1D47",'1'&x"1D48",'1'&x"1D49",'1'&x"1D4A",'1'&x"1D4B",'1'&x"1D4C",'1'&x"1D4D",'1'&x"1D4E",'1'&x"1D4F",
+--'1'&x"1D50",'1'&x"1D51",'1'&x"1D52",'1'&x"1D53",'1'&x"1D54",'1'&x"1D55",'1'&x"1D56",'1'&x"1D57",'1'&x"1D58",'1'&x"1D59",'1'&x"1D5A",'1'&x"1D5B",'1'&x"1D5C",'1'&x"1D5D",'1'&x"1D5E",'1'&x"1D5F",
+--'1'&x"1D60",'1'&x"1D61",'1'&x"1D62",'1'&x"1D63",'1'&x"1D64",'1'&x"1D65",'1'&x"1D66",'1'&x"1D67",'1'&x"1D68",'1'&x"1D69",'1'&x"1D6A",'1'&x"1D6B",'1'&x"1D6C",'1'&x"1D6D",'1'&x"1D6E",'1'&x"1D6F",
+--'1'&x"1D70",'1'&x"1D71",'1'&x"1D72",'1'&x"1D73",'1'&x"1D74",'1'&x"1D75",'1'&x"1D76",'1'&x"1D77",'1'&x"1D78",'1'&x"1D79",'1'&x"1D7A",'1'&x"1D7B",'1'&x"1D7C",'1'&x"1D7D",'1'&x"1D7E",'1'&x"1D7F",
+--'1'&x"1D80",'1'&x"1D81",'1'&x"1D82",'1'&x"1D83",'1'&x"1D84",'1'&x"1D85",'1'&x"1D86",'1'&x"1D87",'1'&x"1D88",'1'&x"1D89",'1'&x"1D8A",'1'&x"1D8B",'1'&x"1D8C",'1'&x"1D8D",'1'&x"1D8E",'1'&x"1D8F",
+--'1'&x"1D90",'1'&x"1D91",'1'&x"1D92",'1'&x"1D93",'1'&x"1D94",'1'&x"1D95",'1'&x"1D96",'1'&x"1D97",'1'&x"1D98",'1'&x"1D99",'1'&x"1D9A",'1'&x"1D9B",'1'&x"1D9C",'1'&x"1D9D",'1'&x"1D9E",'1'&x"1D9F",
+--'1'&x"1DA0",'1'&x"1DA1",'1'&x"1DA2",'1'&x"1DA3",'1'&x"1DA4",'1'&x"1DA5",'1'&x"1DA6",'1'&x"1DA7",'1'&x"1DA8",'1'&x"1DA9",'1'&x"1DAA",'1'&x"1DAB",'1'&x"1DAC",'1'&x"1DAD",'1'&x"1DAE",'1'&x"1DAF",
+--'1'&x"1DB0",'1'&x"1DB1",'1'&x"1DB2",'1'&x"1DB3",'1'&x"1DB4",'1'&x"1DB5",'1'&x"1DB6",'1'&x"1DB7",'1'&x"1DB8",'1'&x"1DB9",'1'&x"1DBA",'1'&x"1DBB",'1'&x"1DBC",'1'&x"1DBD",'1'&x"1DBE",'1'&x"1DBF",
+--'1'&x"1DC0",'1'&x"1DC1",'1'&x"1DC2",'1'&x"1DC3",'1'&x"1DC4",'1'&x"1DC5",'1'&x"1DC6",'1'&x"1DC7",'1'&x"1DC8",'1'&x"1DC9",'1'&x"1DCA",'1'&x"1DCB",'1'&x"1DCC",'1'&x"1DCD",'1'&x"1DCE",'1'&x"1DCF",
+--'1'&x"1DD0",'1'&x"1DD1",'1'&x"1DD2",'1'&x"1DD3",'1'&x"1DD4",'1'&x"1DD5",'1'&x"1DD6",'1'&x"1DD7",'1'&x"1DD8",'1'&x"1DD9",'1'&x"1DDA",'1'&x"1DDB",'1'&x"1DDC",'1'&x"1DDD",'1'&x"1DDE",'1'&x"1DDF",
+--'1'&x"1DE0",'1'&x"1DE1",'1'&x"1DE2",'1'&x"1DE3",'1'&x"1DE4",'1'&x"1DE5",'1'&x"1DE6",'1'&x"1DE7",'1'&x"1DE8",'1'&x"1DE9",'1'&x"1DEA",'1'&x"1DEB",'1'&x"1DEC",'1'&x"1DED",'1'&x"1DEE",'1'&x"1DEF",
+--'1'&x"1DF0",'1'&x"1DF1",'1'&x"1DF2",'1'&x"1DF3",'1'&x"1DF4",'1'&x"1DF5",'1'&x"1DF6",'1'&x"1DF7",'1'&x"1DF8",'1'&x"1DF9",'1'&x"1DFA",'1'&x"1DFB",'1'&x"1DFC",'1'&x"1DFD",'1'&x"1DFE",'1'&x"1DFF",
+--'1'&x"1E00",'1'&x"1E01",'1'&x"1E02",'1'&x"1E03",'1'&x"1E04",'1'&x"1E05",'1'&x"1E06",'1'&x"1E07",'1'&x"1E08",'1'&x"1E09",'1'&x"1E0A",'1'&x"1E0B",'1'&x"1E0C",'1'&x"1E0D",'1'&x"1E0E",'1'&x"1E0F",
+--'1'&x"1E10",'1'&x"1E11",'1'&x"1E12",'1'&x"1E13",'1'&x"1E14",'1'&x"1E15",'1'&x"1E16",'1'&x"1E17",'1'&x"1E18",'1'&x"1E19",'1'&x"1E1A",'1'&x"1E1B",'1'&x"1E1C",'1'&x"1E1D",'1'&x"1E1E",'1'&x"1E1F",
+--'1'&x"1E20",'1'&x"1E21",'1'&x"1E22",'1'&x"1E23",'1'&x"1E24",'1'&x"1E25",'1'&x"1E26",'1'&x"1E27",'1'&x"1E28",'1'&x"1E29",'1'&x"1E2A",'1'&x"1E2B",'1'&x"1E2C",'1'&x"1E2D",'1'&x"1E2E",'1'&x"1E2F",
+--'1'&x"1E30",'1'&x"1E31",'1'&x"1E32",'1'&x"1E33",'1'&x"1E34",'1'&x"1E35",'1'&x"1E36",'1'&x"1E37",'1'&x"1E38",'1'&x"1E39",'1'&x"1E3A",'1'&x"1E3B",'1'&x"1E3C",'1'&x"1E3D",'1'&x"1E3E",'1'&x"1E3F",
+--'1'&x"1E40",'1'&x"1E41",'1'&x"1E42",'1'&x"1E43",'1'&x"1E44",'1'&x"1E45",'1'&x"1E46",'1'&x"1E47",'1'&x"1E48",'1'&x"1E49",'1'&x"1E4A",'1'&x"1E4B",'1'&x"1E4C",'1'&x"1E4D",'1'&x"1E4E",'1'&x"1E4F",
+--'1'&x"1E50",'1'&x"1E51",'1'&x"1E52",'1'&x"1E53",'1'&x"1E54",'1'&x"1E55",'1'&x"1E56",'1'&x"1E57",'1'&x"1E58",'1'&x"1E59",'1'&x"1E5A",'1'&x"1E5B",'1'&x"1E5C",'1'&x"1E5D",'1'&x"1E5E",'1'&x"1E5F",
+--'1'&x"1E60",'1'&x"1E61",'1'&x"1E62",'1'&x"1E63",'1'&x"1E64",'1'&x"1E65",'1'&x"1E66",'1'&x"1E67",'1'&x"1E68",'1'&x"1E69",'1'&x"1E6A",'1'&x"1E6B",'1'&x"1E6C",'1'&x"1E6D",'1'&x"1E6E",'1'&x"1E6F",
+--'1'&x"1E70",'1'&x"1E71",'1'&x"1E72",'1'&x"1E73",'1'&x"1E74",'1'&x"1E75",'1'&x"1E76",'1'&x"1E77",'1'&x"1E78",'1'&x"1E79",'1'&x"1E7A",'1'&x"1E7B",'1'&x"1E7C",'1'&x"1E7D",'1'&x"1E7E",'1'&x"1E7F",
+--'1'&x"1E80",'1'&x"1E81",'1'&x"1E82",'1'&x"1E83",'1'&x"1E84",'1'&x"1E85",'1'&x"1E86",'1'&x"1E87",'1'&x"1E88",'1'&x"1E89",'1'&x"1E8A",'1'&x"1E8B",'1'&x"1E8C",'1'&x"1E8D",'1'&x"1E8E",'1'&x"1E8F",
+--'1'&x"1E90",'1'&x"1E91",'1'&x"1E92",'1'&x"1E93",'1'&x"1E94",'1'&x"1E95",'1'&x"1E96",'1'&x"1E97",'1'&x"1E98",'1'&x"1E99",'1'&x"1E9A",'1'&x"1E9B",'1'&x"1E9C",'1'&x"1E9D",'1'&x"1E9E",'1'&x"1E9F",
+--'1'&x"1EA0",'1'&x"1EA1",'1'&x"1EA2",'1'&x"1EA3",'1'&x"1EA4",'1'&x"1EA5",'1'&x"1EA6",'1'&x"1EA7",'1'&x"1EA8",'1'&x"1EA9",'1'&x"1EAA",'1'&x"1EAB",'1'&x"1EAC",'1'&x"1EAD",'1'&x"1EAE",'1'&x"1EAF",
+--'1'&x"1EB0",'1'&x"1EB1",'1'&x"1EB2",'1'&x"1EB3",'1'&x"1EB4",'1'&x"1EB5",'1'&x"1EB6",'1'&x"1EB7",'1'&x"1EB8",'1'&x"1EB9",'1'&x"1EBA",'1'&x"1EBB",'1'&x"1EBC",'1'&x"1EBD",'1'&x"1EBE",'1'&x"1EBF",
+--'1'&x"1EC0",'1'&x"1EC1",'1'&x"1EC2",'1'&x"1EC3",'1'&x"1EC4",'1'&x"1EC5",'1'&x"1EC6",'1'&x"1EC7",'1'&x"1EC8",'1'&x"1EC9",'1'&x"1ECA",'1'&x"1ECB",'1'&x"1ECC",'1'&x"1ECD",'1'&x"1ECE",'1'&x"1ECF",
+--'1'&x"1ED0",'1'&x"1ED1",'1'&x"1ED2",'1'&x"1ED3",'1'&x"1ED4",'1'&x"1ED5",'1'&x"1ED6",'1'&x"1ED7",'1'&x"1ED8",'1'&x"1ED9",'1'&x"1EDA",'1'&x"1EDB",'1'&x"1EDC",'1'&x"1EDD",'1'&x"1EDE",'1'&x"1EDF",
+--'1'&x"1EE0",'1'&x"1EE1",'1'&x"1EE2",'1'&x"1EE3",'1'&x"1EE4",'1'&x"1EE5",'1'&x"1EE6",'1'&x"1EE7",'1'&x"1EE8",'1'&x"1EE9",'1'&x"1EEA",'1'&x"1EEB",'1'&x"1EEC",'1'&x"1EED",'1'&x"1EEE",'1'&x"1EEF",
+--'1'&x"1EF0",'1'&x"1EF1",'1'&x"1EF2",'1'&x"1EF3",'1'&x"1EF4",'1'&x"1EF5",'1'&x"1EF6",'1'&x"1EF7",'1'&x"1EF8",'1'&x"1EF9",'1'&x"1EFA",'1'&x"1EFB",'1'&x"1EFC",'1'&x"1EFD",'1'&x"1EFE",'1'&x"1EFF",
+--'1'&x"1F00",'1'&x"1F01",'1'&x"1F02",'1'&x"1F03",'1'&x"1F04",'1'&x"1F05",'1'&x"1F06",'1'&x"1F07",'1'&x"1F08",'1'&x"1F09",'1'&x"1F0A",'1'&x"1F0B",'1'&x"1F0C",'1'&x"1F0D",'1'&x"1F0E",'1'&x"1F0F",
+--'1'&x"1F10",'1'&x"1F11",'1'&x"1F12",'1'&x"1F13",'1'&x"1F14",'1'&x"1F15",'1'&x"1F16",'1'&x"1F17",'1'&x"1F18",'1'&x"1F19",'1'&x"1F1A",'1'&x"1F1B",'1'&x"1F1C",'1'&x"1F1D",'1'&x"1F1E",'1'&x"1F1F",
+--'1'&x"1F20",'1'&x"1F21",'1'&x"1F22",'1'&x"1F23",'1'&x"1F24",'1'&x"1F25",'1'&x"1F26",'1'&x"1F27",'1'&x"1F28",'1'&x"1F29",'1'&x"1F2A",'1'&x"1F2B",'1'&x"1F2C",'1'&x"1F2D",'1'&x"1F2E",'1'&x"1F2F",
+--'1'&x"1F30",'1'&x"1F31",'1'&x"1F32",'1'&x"1F33",'1'&x"1F34",'1'&x"1F35",'1'&x"1F36",'1'&x"1F37",'1'&x"1F38",'1'&x"1F39",'1'&x"1F3A",'1'&x"1F3B",'1'&x"1F3C",'1'&x"1F3D",'1'&x"1F3E",'1'&x"1F3F",
+--'1'&x"1F40",'1'&x"1F41",'1'&x"1F42",'1'&x"1F43",'1'&x"1F44",'1'&x"1F45",'1'&x"1F46",'1'&x"1F47",'1'&x"1F48",'1'&x"1F49",'1'&x"1F4A",'1'&x"1F4B",'1'&x"1F4C",'1'&x"1F4D",'1'&x"1F4E",'1'&x"1F4F",
+--'1'&x"1F50",'1'&x"1F51",'1'&x"1F52",'1'&x"1F53",'1'&x"1F54",'1'&x"1F55",'1'&x"1F56",'1'&x"1F57",'1'&x"1F58",'1'&x"1F59",'1'&x"1F5A",'1'&x"1F5B",'1'&x"1F5C",'1'&x"1F5D",'1'&x"1F5E",'1'&x"1F5F",
+--'1'&x"1F60",'1'&x"1F61",'1'&x"1F62",'1'&x"1F63",'1'&x"1F64",'1'&x"1F65",'1'&x"1F66",'1'&x"1F67",'1'&x"1F68",'1'&x"1F69",'1'&x"1F6A",'1'&x"1F6B",'1'&x"1F6C",'1'&x"1F6D",'1'&x"1F6E",'1'&x"1F6F",
+--'1'&x"1F70",'1'&x"1F71",'1'&x"1F72",'1'&x"1F73",'1'&x"1F74",'1'&x"1F75",'1'&x"1F76",'1'&x"1F77",'1'&x"1F78",'1'&x"1F79",'1'&x"1F7A",'1'&x"1F7B",'1'&x"1F7C",'1'&x"1F7D",'1'&x"1F7E",'1'&x"1F7F",
+--'1'&x"1F80",'1'&x"1F81",'1'&x"1F82",'1'&x"1F83",'1'&x"1F84",'1'&x"1F85",'1'&x"1F86",'1'&x"1F87",'1'&x"1F88",'1'&x"1F89",'1'&x"1F8A",'1'&x"1F8B",'1'&x"1F8C",'1'&x"1F8D",'1'&x"1F8E",'1'&x"1F8F",
+--'1'&x"1F90",'1'&x"1F91",'1'&x"1F92",'1'&x"1F93",'1'&x"1F94",'1'&x"1F95",'1'&x"1F96",'1'&x"1F97",'1'&x"1F98",'1'&x"1F99",'1'&x"1F9A",'1'&x"1F9B",'1'&x"1F9C",'1'&x"1F9D",'1'&x"1F9E",'1'&x"1F9F",
+--'1'&x"1FA0",'1'&x"1FA1",'1'&x"1FA2",'1'&x"1FA3",'1'&x"1FA4",'1'&x"1FA5",'1'&x"1FA6",'1'&x"1FA7",'1'&x"1FA8",'1'&x"1FA9",'1'&x"1FAA",'1'&x"1FAB",'1'&x"1FAC",'1'&x"1FAD",'1'&x"1FAE",'1'&x"1FAF",
+--'1'&x"1FB0",'1'&x"1FB1",'1'&x"1FB2",'1'&x"1FB3",'1'&x"1FB4",'1'&x"1FB5",'1'&x"1FB6",'1'&x"1FB7",'1'&x"1FB8",'1'&x"1FB9",'1'&x"1FBA",'1'&x"1FBB",'1'&x"1FBC",'1'&x"1FBD",'1'&x"1FBE",'1'&x"1FBF",
+--'1'&x"1FC0",'1'&x"1FC1",'1'&x"1FC2",'1'&x"1FC3",'1'&x"1FC4",'1'&x"1FC5",'1'&x"1FC6",'1'&x"1FC7",'1'&x"1FC8",'1'&x"1FC9",'1'&x"1FCA",'1'&x"1FCB",'1'&x"1FCC",'1'&x"1FCD",'1'&x"1FCE",'1'&x"1FCF",
+--'1'&x"1FD0",'1'&x"1FD1",'1'&x"1FD2",'1'&x"1FD3",'1'&x"1FD4",'1'&x"1FD5",'1'&x"1FD6",'1'&x"1FD7",'1'&x"1FD8",'1'&x"1FD9",'1'&x"1FDA",'1'&x"1FDB",'1'&x"1FDC",'1'&x"1FDD",'1'&x"1FDE",'1'&x"1FDF",
+--'1'&x"1FE0",'1'&x"1FE1",'1'&x"1FE2",'1'&x"1FE3",'1'&x"1FE4",'1'&x"1FE5",'1'&x"1FE6",'1'&x"1FE7",'1'&x"1FE8",'1'&x"1FE9",'1'&x"1FEA",'1'&x"1FEB",'1'&x"1FEC",'1'&x"1FED",'1'&x"1FEE",'1'&x"1FEF",
+--'1'&x"1FF0",'1'&x"1FF1",'1'&x"1FF2",'1'&x"1FF3",'1'&x"1FF4",'1'&x"1FF5",'1'&x"1FF6",'1'&x"1FF7",'1'&x"1FF8",'1'&x"1FF9",'1'&x"1FFA",'1'&x"1FFB",'1'&x"1FFC",'1'&x"1FFD",'1'&x"1FFE",'1'&x"1FFF",
+--'1'&x"2000",'1'&x"2001",'1'&x"2002",'1'&x"2003",'1'&x"2004",'1'&x"2005",'1'&x"2006",'1'&x"2007",'1'&x"2008",'1'&x"2009",'1'&x"200A",'1'&x"200B",'1'&x"200C",'1'&x"200D",'1'&x"200E",'1'&x"200F",
+--'1'&x"2010",'1'&x"2011",'1'&x"2012",'1'&x"2013",'1'&x"2014",'1'&x"2015",'1'&x"2016",'1'&x"2017",'1'&x"2018",'1'&x"2019",'1'&x"201A",'1'&x"201B",'1'&x"201C",'1'&x"201D",'1'&x"201E",'1'&x"201F",
+--'1'&x"2020",'1'&x"2021",'1'&x"2022",'1'&x"2023",'1'&x"2024",'1'&x"2025",'1'&x"2026",'1'&x"2027",'1'&x"2028",'1'&x"2029",'1'&x"202A",'1'&x"202B",'1'&x"202C",'1'&x"202D",'1'&x"202E",'1'&x"202F",
+--'1'&x"2030",'1'&x"2031",'1'&x"2032",'1'&x"2033",'1'&x"2034",'1'&x"2035",'1'&x"2036",'1'&x"2037",'1'&x"2038",'1'&x"2039",'1'&x"203A",'1'&x"203B",'1'&x"203C",'1'&x"203D",'1'&x"203E",'1'&x"203F",
+--'1'&x"2040",'1'&x"2041",'1'&x"2042",'1'&x"2043",'1'&x"2044",'1'&x"2045",'1'&x"2046",'1'&x"2047",'1'&x"2048",'1'&x"2049",'1'&x"204A",'1'&x"204B",'1'&x"204C",'1'&x"204D",'1'&x"204E",'1'&x"204F",
+--'1'&x"2050",'1'&x"2051",'1'&x"2052",'1'&x"2053",'1'&x"2054",'1'&x"2055",'1'&x"2056",'1'&x"2057",'1'&x"2058",'1'&x"2059",'1'&x"205A",'1'&x"205B",'1'&x"205C",'1'&x"205D",'1'&x"205E",'1'&x"205F",
+--'1'&x"2060",'1'&x"2061",'1'&x"2062",'1'&x"2063",'1'&x"2064",'1'&x"2065",'1'&x"2066",'1'&x"2067",'1'&x"2068",'1'&x"2069",'1'&x"206A",'1'&x"206B",'1'&x"206C",'1'&x"206D",'1'&x"206E",'1'&x"206F",
+--'1'&x"2070",'1'&x"2071",'1'&x"2072",'1'&x"2073",'1'&x"2074",'1'&x"2075",'1'&x"2076",'1'&x"2077",'1'&x"2078",'1'&x"2079",'1'&x"207A",'1'&x"207B",'1'&x"207C",'1'&x"207D",'1'&x"207E",'1'&x"207F",
+--'1'&x"2080",'1'&x"2081",'1'&x"2082",'1'&x"2083",'1'&x"2084",'1'&x"2085",'1'&x"2086",'1'&x"2087",'1'&x"2088",'1'&x"2089",'1'&x"208A",'1'&x"208B",'1'&x"208C",'1'&x"208D",'1'&x"208E",'1'&x"208F",
+--'1'&x"2090",'1'&x"2091",'1'&x"2092",'1'&x"2093",'1'&x"2094",'1'&x"2095",'1'&x"2096",'1'&x"2097",'1'&x"2098",'1'&x"2099",'1'&x"209A",'1'&x"209B",'1'&x"209C",'1'&x"209D",'1'&x"209E",'1'&x"209F",
+--'1'&x"20A0",'1'&x"20A1",'1'&x"20A2",'1'&x"20A3",'1'&x"20A4",'1'&x"20A5",'1'&x"20A6",'1'&x"20A7",'1'&x"20A8",'1'&x"20A9",'1'&x"20AA",'1'&x"20AB",'1'&x"20AC",'1'&x"20AD",'1'&x"20AE",'1'&x"20AF",
+--'1'&x"20B0",'1'&x"20B1",'1'&x"20B2",'1'&x"20B3",'1'&x"20B4",'1'&x"20B5",'1'&x"20B6",'1'&x"20B7",'1'&x"20B8",'1'&x"20B9",'1'&x"20BA",'1'&x"20BB",'1'&x"20BC",'1'&x"20BD",'1'&x"20BE",'1'&x"20BF",
+--'1'&x"20C0",'1'&x"20C1",'1'&x"20C2",'1'&x"20C3",'1'&x"20C4",'1'&x"20C5",'1'&x"20C6",'1'&x"20C7",'1'&x"20C8",'1'&x"20C9",'1'&x"20CA",'1'&x"20CB",'1'&x"20CC",'1'&x"20CD",'1'&x"20CE",'1'&x"20CF",
+--'1'&x"20D0",'1'&x"20D1",'1'&x"20D2",'1'&x"20D3",'1'&x"20D4",'1'&x"20D5",'1'&x"20D6",'1'&x"20D7",'1'&x"20D8",'1'&x"20D9",'1'&x"20DA",'1'&x"20DB",'1'&x"20DC",'1'&x"20DD",'1'&x"20DE",'1'&x"20DF",
+--'1'&x"20E0",'1'&x"20E1",'1'&x"20E2",'1'&x"20E3",'1'&x"20E4",'1'&x"20E5",'1'&x"20E6",'1'&x"20E7",'1'&x"20E8",'1'&x"20E9",'1'&x"20EA",'1'&x"20EB",'1'&x"20EC",'1'&x"20ED",'1'&x"20EE",'1'&x"20EF",
+--'1'&x"20F0",'1'&x"20F1",'1'&x"20F2",'1'&x"20F3",'1'&x"20F4",'1'&x"20F5",'1'&x"20F6",'1'&x"20F7",'1'&x"20F8",'1'&x"20F9",'1'&x"20FA",'1'&x"20FB",'1'&x"20FC",'1'&x"20FD",'1'&x"20FE",'1'&x"20FF",
+--'1'&x"2100",'1'&x"2101",'1'&x"2102",'1'&x"2103",'1'&x"2104",'1'&x"2105",'1'&x"2106",'1'&x"2107",'1'&x"2108",'1'&x"2109",'1'&x"210A",'1'&x"210B",'1'&x"210C",'1'&x"210D",'1'&x"210E",'1'&x"210F",
+--'1'&x"2110",'1'&x"2111",'1'&x"2112",'1'&x"2113",'1'&x"2114",'1'&x"2115",'1'&x"2116",'1'&x"2117",'1'&x"2118",'1'&x"2119",'1'&x"211A",'1'&x"211B",'1'&x"211C",'1'&x"211D",'1'&x"211E",'1'&x"211F",
+--'1'&x"2120",'1'&x"2121",'1'&x"2122",'1'&x"2123",'1'&x"2124",'1'&x"2125",'1'&x"2126",'1'&x"2127",'1'&x"2128",'1'&x"2129",'1'&x"212A",'1'&x"212B",'1'&x"212C",'1'&x"212D",'1'&x"212E",'1'&x"212F",
+--'1'&x"2130",'1'&x"2131",'1'&x"2132",'1'&x"2133",'1'&x"2134",'1'&x"2135",'1'&x"2136",'1'&x"2137",'1'&x"2138",'1'&x"2139",'1'&x"213A",'1'&x"213B",'1'&x"213C",'1'&x"213D",'1'&x"213E",'1'&x"213F",
+--'1'&x"2140",'1'&x"2141",'1'&x"2142",'1'&x"2143",'1'&x"2144",'1'&x"2145",'1'&x"2146",'1'&x"2147",'1'&x"2148",'1'&x"2149",'1'&x"214A",'1'&x"214B",'1'&x"214C",'1'&x"214D",'1'&x"214E",'1'&x"214F",
+--'1'&x"2150",'1'&x"2151",'1'&x"2152",'1'&x"2153",'1'&x"2154",'1'&x"2155",'1'&x"2156",'1'&x"2157",'1'&x"2158",'1'&x"2159",'1'&x"215A",'1'&x"215B",'1'&x"215C",'1'&x"215D",'1'&x"215E",'1'&x"215F",
+--'1'&x"2160",'1'&x"2161",'1'&x"2162",'1'&x"2163",'1'&x"2164",'1'&x"2165",'1'&x"2166",'1'&x"2167",'1'&x"2168",'1'&x"2169",'1'&x"216A",'1'&x"216B",'1'&x"216C",'1'&x"216D",'1'&x"216E",'1'&x"216F",
+--'1'&x"2170",'1'&x"2171",'1'&x"2172",'1'&x"2173",'1'&x"2174",'1'&x"2175",'1'&x"2176",'1'&x"2177",'1'&x"2178",'1'&x"2179",'1'&x"217A",'1'&x"217B",'1'&x"217C",'1'&x"217D",'1'&x"217E",'1'&x"217F",
+--'1'&x"2180",'1'&x"2181",'1'&x"2182",'1'&x"2183",'1'&x"2184",'1'&x"2185",'1'&x"2186",'1'&x"2187",'1'&x"2188",'1'&x"2189",'1'&x"218A",'1'&x"218B",'1'&x"218C",'1'&x"218D",'1'&x"218E",'1'&x"218F",
+--'1'&x"2190",'1'&x"2191",'1'&x"2192",'1'&x"2193",'1'&x"2194",'1'&x"2195",'1'&x"2196",'1'&x"2197",'1'&x"2198",'1'&x"2199",'1'&x"219A",'1'&x"219B",'1'&x"219C",'1'&x"219D",'1'&x"219E",'1'&x"219F",
+--'1'&x"21A0",'1'&x"21A1",'1'&x"21A2",'1'&x"21A3",'1'&x"21A4",'1'&x"21A5",'1'&x"21A6",'1'&x"21A7",'1'&x"21A8",'1'&x"21A9",'1'&x"21AA",'1'&x"21AB",'1'&x"21AC",'1'&x"21AD",'1'&x"21AE",'1'&x"21AF",
+--'1'&x"21B0",'1'&x"21B1",'1'&x"21B2",'1'&x"21B3",'1'&x"21B4",'1'&x"21B5",'1'&x"21B6",'1'&x"21B7",'1'&x"21B8",'1'&x"21B9",'1'&x"21BA",'1'&x"21BB",'1'&x"21BC",'1'&x"21BD",'1'&x"21BE",'1'&x"21BF",
+--'1'&x"21C0",'1'&x"21C1",'1'&x"21C2",'1'&x"21C3",'1'&x"21C4",'1'&x"21C5",'1'&x"21C6",'1'&x"21C7",'1'&x"21C8",'1'&x"21C9",'1'&x"21CA",'1'&x"21CB",'1'&x"21CC",'1'&x"21CD",'1'&x"21CE",'1'&x"21CF",
+--'1'&x"21D0",'1'&x"21D1",'1'&x"21D2",'1'&x"21D3",'1'&x"21D4",'1'&x"21D5",'1'&x"21D6",'1'&x"21D7",'1'&x"21D8",'1'&x"21D9",'1'&x"21DA",'1'&x"21DB",'1'&x"21DC",'1'&x"21DD",'1'&x"21DE",'1'&x"21DF",
+--'1'&x"21E0",'1'&x"21E1",'1'&x"21E2",'1'&x"21E3",'1'&x"21E4",'1'&x"21E5",'1'&x"21E6",'1'&x"21E7",'1'&x"21E8",'1'&x"21E9",'1'&x"21EA",'1'&x"21EB",'1'&x"21EC",'1'&x"21ED",'1'&x"21EE",'1'&x"21EF",
+--'1'&x"21F0",'1'&x"21F1",'1'&x"21F2",'1'&x"21F3",'1'&x"21F4",'1'&x"21F5",'1'&x"21F6",'1'&x"21F7",'1'&x"21F8",'1'&x"21F9",'1'&x"21FA",'1'&x"21FB",'1'&x"21FC",'1'&x"21FD",'1'&x"21FE",'1'&x"21FF",
+--'1'&x"2200",'1'&x"2201",'1'&x"2202",'1'&x"2203",'1'&x"2204",'1'&x"2205",'1'&x"2206",'1'&x"2207",'1'&x"2208",'1'&x"2209",'1'&x"220A",'1'&x"220B",'1'&x"220C",'1'&x"220D",'1'&x"220E",'1'&x"220F",
+--'1'&x"2210",'1'&x"2211",'1'&x"2212",'1'&x"2213",'1'&x"2214",'1'&x"2215",'1'&x"2216",'1'&x"2217",'1'&x"2218",'1'&x"2219",'1'&x"221A",'1'&x"221B",'1'&x"221C",'1'&x"221D",'1'&x"221E",'1'&x"221F",
+--'1'&x"2220",'1'&x"2221",'1'&x"2222",'1'&x"2223",'1'&x"2224",'1'&x"2225",'1'&x"2226",'1'&x"2227",'1'&x"2228",'1'&x"2229",'1'&x"222A",'1'&x"222B",'1'&x"222C",'1'&x"222D",'1'&x"222E",'1'&x"222F",
+--'1'&x"2230",'1'&x"2231",'1'&x"2232",'1'&x"2233",'1'&x"2234",'1'&x"2235",'1'&x"2236",'1'&x"2237",'1'&x"2238",'1'&x"2239",'1'&x"223A",'1'&x"223B",'1'&x"223C",'1'&x"223D",'1'&x"223E",'1'&x"223F",
+--'1'&x"2240",'1'&x"2241",'1'&x"2242",'1'&x"2243",'1'&x"2244",'1'&x"2245",'1'&x"2246",'1'&x"2247",'1'&x"2248",'1'&x"2249",'1'&x"224A",'1'&x"224B",'1'&x"224C",'1'&x"224D",'1'&x"224E",'1'&x"224F",
+--'1'&x"2250",'1'&x"2251",'1'&x"2252",'1'&x"2253",'1'&x"2254",'1'&x"2255",'1'&x"2256",'1'&x"2257",'1'&x"2258",'1'&x"2259",'1'&x"225A",'1'&x"225B",'1'&x"225C",'1'&x"225D",'1'&x"225E",'1'&x"225F",
+--'1'&x"2260",'1'&x"2261",'1'&x"2262",'1'&x"2263",'1'&x"2264",'1'&x"2265",'1'&x"2266",'1'&x"2267",'1'&x"2268",'1'&x"2269",'1'&x"226A",'1'&x"226B",'1'&x"226C",'1'&x"226D",'1'&x"226E",'1'&x"226F",
+--'1'&x"2270",'1'&x"2271",'1'&x"2272",'1'&x"2273",'1'&x"2274",'1'&x"2275",'1'&x"2276",'1'&x"2277",'1'&x"2278",'1'&x"2279",'1'&x"227A",'1'&x"227B",'1'&x"227C",'1'&x"227D",'1'&x"227E",'1'&x"227F",
+--'1'&x"2280",'1'&x"2281",'1'&x"2282",'1'&x"2283",'1'&x"2284",'1'&x"2285",'1'&x"2286",'1'&x"2287",'1'&x"2288",'1'&x"2289",'1'&x"228A",'1'&x"228B",'1'&x"228C",'1'&x"228D",'1'&x"228E",'1'&x"228F",
+--'1'&x"2290",'1'&x"2291",'1'&x"2292",'1'&x"2293",'1'&x"2294",'1'&x"2295",'1'&x"2296",'1'&x"2297",'1'&x"2298",'1'&x"2299",'1'&x"229A",'1'&x"229B",'1'&x"229C",'1'&x"229D",'1'&x"229E",'1'&x"229F",
+--'1'&x"22A0",'1'&x"22A1",'1'&x"22A2",'1'&x"22A3",'1'&x"22A4",'1'&x"22A5",'1'&x"22A6",'1'&x"22A7",'1'&x"22A8",'1'&x"22A9",'1'&x"22AA",'1'&x"22AB",'1'&x"22AC",'1'&x"22AD",'1'&x"22AE",'1'&x"22AF",
+--'1'&x"22B0",'1'&x"22B1",'1'&x"22B2",'1'&x"22B3",'1'&x"22B4",'1'&x"22B5",'1'&x"22B6",'1'&x"22B7",'1'&x"22B8",'1'&x"22B9",'1'&x"22BA",'1'&x"22BB",'1'&x"22BC",'1'&x"22BD",'1'&x"22BE",'1'&x"22BF",
+--'1'&x"22C0",'1'&x"22C1",'1'&x"22C2",'1'&x"22C3",'1'&x"22C4",'1'&x"22C5",'1'&x"22C6",'1'&x"22C7",'1'&x"22C8",'1'&x"22C9",'1'&x"22CA",'1'&x"22CB",'1'&x"22CC",'1'&x"22CD",'1'&x"22CE",'1'&x"22CF",
+--'1'&x"22D0",'1'&x"22D1",'1'&x"22D2",'1'&x"22D3",'1'&x"22D4",'1'&x"22D5",'1'&x"22D6",'1'&x"22D7",'1'&x"22D8",'1'&x"22D9",'1'&x"22DA",'1'&x"22DB",'1'&x"22DC",'1'&x"22DD",'1'&x"22DE",'1'&x"22DF",
+--'1'&x"22E0",'1'&x"22E1",'1'&x"22E2",'1'&x"22E3",'1'&x"22E4",'1'&x"22E5",'1'&x"22E6",'1'&x"22E7",'1'&x"22E8",'1'&x"22E9",'1'&x"22EA",'1'&x"22EB",'1'&x"22EC",'1'&x"22ED",'1'&x"22EE",'1'&x"22EF",
+--'1'&x"22F0",'1'&x"22F1",'1'&x"22F2",'1'&x"22F3",'1'&x"22F4",'1'&x"22F5",'1'&x"22F6",'1'&x"22F7",'1'&x"22F8",'1'&x"22F9",'1'&x"22FA",'1'&x"22FB",'1'&x"22FC",'1'&x"22FD",'1'&x"22FE",'1'&x"22FF",
+--'1'&x"2300",'1'&x"2301",'1'&x"2302",'1'&x"2303",'1'&x"2304",'1'&x"2305",'1'&x"2306",'1'&x"2307",'1'&x"2308",'1'&x"2309",'1'&x"230A",'1'&x"230B",'1'&x"230C",'1'&x"230D",'1'&x"230E",'1'&x"230F",
+--'1'&x"2310",'1'&x"2311",'1'&x"2312",'1'&x"2313",'1'&x"2314",'1'&x"2315",'1'&x"2316",'1'&x"2317",'1'&x"2318",'1'&x"2319",'1'&x"231A",'1'&x"231B",'1'&x"231C",'1'&x"231D",'1'&x"231E",'1'&x"231F",
+--'1'&x"2320",'1'&x"2321",'1'&x"2322",'1'&x"2323",'1'&x"2324",'1'&x"2325",'1'&x"2326",'1'&x"2327",'1'&x"2328",'1'&x"2329",'1'&x"232A",'1'&x"232B",'1'&x"232C",'1'&x"232D",'1'&x"232E",'1'&x"232F",
+--'1'&x"2330",'1'&x"2331",'1'&x"2332",'1'&x"2333",'1'&x"2334",'1'&x"2335",'1'&x"2336",'1'&x"2337",'1'&x"2338",'1'&x"2339",'1'&x"233A",'1'&x"233B",'1'&x"233C",'1'&x"233D",'1'&x"233E",'1'&x"233F",
+--'1'&x"2340",'1'&x"2341",'1'&x"2342",'1'&x"2343",'1'&x"2344",'1'&x"2345",'1'&x"2346",'1'&x"2347",'1'&x"2348",'1'&x"2349",'1'&x"234A",'1'&x"234B",'1'&x"234C",'1'&x"234D",'1'&x"234E",'1'&x"234F",
+--'1'&x"2350",'1'&x"2351",'1'&x"2352",'1'&x"2353",'1'&x"2354",'1'&x"2355",'1'&x"2356",'1'&x"2357",'1'&x"2358",'1'&x"2359",'1'&x"235A",'1'&x"235B",'1'&x"235C",'1'&x"235D",'1'&x"235E",'1'&x"235F",
+--'1'&x"2360",'1'&x"2361",'1'&x"2362",'1'&x"2363",'1'&x"2364",'1'&x"2365",'1'&x"2366",'1'&x"2367",'1'&x"2368",'1'&x"2369",'1'&x"236A",'1'&x"236B",'1'&x"236C",'1'&x"236D",'1'&x"236E",'1'&x"236F",
+--'1'&x"2370",'1'&x"2371",'1'&x"2372",'1'&x"2373",'1'&x"2374",'1'&x"2375",'1'&x"2376",'1'&x"2377",'1'&x"2378",'1'&x"2379",'1'&x"237A",'1'&x"237B",'1'&x"237C",'1'&x"237D",'1'&x"237E",'1'&x"237F",
+--'1'&x"2380",'1'&x"2381",'1'&x"2382",'1'&x"2383",'1'&x"2384",'1'&x"2385",'1'&x"2386",'1'&x"2387",'1'&x"2388",'1'&x"2389",'1'&x"238A",'1'&x"238B",'1'&x"238C",'1'&x"238D",'1'&x"238E",'1'&x"238F",
+--'1'&x"2390",'1'&x"2391",'1'&x"2392",'1'&x"2393",'1'&x"2394",'1'&x"2395",'1'&x"2396",'1'&x"2397",'1'&x"2398",'1'&x"2399",'1'&x"239A",'1'&x"239B",'1'&x"239C",'1'&x"239D",'1'&x"239E",'1'&x"239F",
+--'1'&x"23A0",'1'&x"23A1",'1'&x"23A2",'1'&x"23A3",'1'&x"23A4",'1'&x"23A5",'1'&x"23A6",'1'&x"23A7",'1'&x"23A8",'1'&x"23A9",'1'&x"23AA",'1'&x"23AB",'1'&x"23AC",'1'&x"23AD",'1'&x"23AE",'1'&x"23AF",
+--'1'&x"23B0",'1'&x"23B1",'1'&x"23B2",'1'&x"23B3",'1'&x"23B4",'1'&x"23B5",'1'&x"23B6",'1'&x"23B7",'1'&x"23B8",'1'&x"23B9",'1'&x"23BA",'1'&x"23BB",'1'&x"23BC",'1'&x"23BD",'1'&x"23BE",'1'&x"23BF",
+--'1'&x"23C0",'1'&x"23C1",'1'&x"23C2",'1'&x"23C3",'1'&x"23C4",'1'&x"23C5",'1'&x"23C6",'1'&x"23C7",'1'&x"23C8",'1'&x"23C9",'1'&x"23CA",'1'&x"23CB",'1'&x"23CC",'1'&x"23CD",'1'&x"23CE",'1'&x"23CF",
+--'1'&x"23D0",'1'&x"23D1",'1'&x"23D2",'1'&x"23D3",'1'&x"23D4",'1'&x"23D5",'1'&x"23D6",'1'&x"23D7",'1'&x"23D8",'1'&x"23D9",'1'&x"23DA",'1'&x"23DB",'1'&x"23DC",'1'&x"23DD",'1'&x"23DE",'1'&x"23DF",
+--'1'&x"23E0",'1'&x"23E1",'1'&x"23E2",'1'&x"23E3",'1'&x"23E4",'1'&x"23E5",'1'&x"23E6",'1'&x"23E7",'1'&x"23E8",'1'&x"23E9",'1'&x"23EA",'1'&x"23EB",'1'&x"23EC",'1'&x"23ED",'1'&x"23EE",'1'&x"23EF",
+--'1'&x"23F0",'1'&x"23F1",'1'&x"23F2",'1'&x"23F3",'1'&x"23F4",'1'&x"23F5",'1'&x"23F6",'1'&x"23F7",'1'&x"23F8",'1'&x"23F9",'1'&x"23FA",'1'&x"23FB",'1'&x"23FC",'1'&x"23FD",'1'&x"23FE",'1'&x"23FF",
+--'1'&x"2400",'1'&x"2401",'1'&x"2402",'1'&x"2403",'1'&x"2404",'1'&x"2405",'1'&x"2406",'1'&x"2407",'1'&x"2408",'1'&x"2409",'1'&x"240A",'1'&x"240B",'1'&x"240C",'1'&x"240D",'1'&x"240E",'1'&x"240F",
+--'1'&x"2410",'1'&x"2411",'1'&x"2412",'1'&x"2413",'1'&x"2414",'1'&x"2415",'1'&x"2416",'1'&x"2417",'1'&x"2418",'1'&x"2419",'1'&x"241A",'1'&x"241B",'1'&x"241C",'1'&x"241D",'1'&x"241E",'1'&x"241F",
+--'1'&x"2420",'1'&x"2421",'1'&x"2422",'1'&x"2423",'1'&x"2424",'1'&x"2425",'1'&x"2426",'1'&x"2427",'1'&x"2428",'1'&x"2429",'1'&x"242A",'1'&x"242B",'1'&x"242C",'1'&x"242D",'1'&x"242E",'1'&x"242F",
+--'1'&x"2430",'1'&x"2431",'1'&x"2432",'1'&x"2433",'1'&x"2434",'1'&x"2435",'1'&x"2436",'1'&x"2437",'1'&x"2438",'1'&x"2439",'1'&x"243A",'1'&x"243B",'1'&x"243C",'1'&x"243D",'1'&x"243E",'1'&x"243F",
+--'1'&x"2440",'1'&x"2441",'1'&x"2442",'1'&x"2443",'1'&x"2444",'1'&x"2445",'1'&x"2446",'1'&x"2447",'1'&x"2448",'1'&x"2449",'1'&x"244A",'1'&x"244B",'1'&x"244C",'1'&x"244D",'1'&x"244E",'1'&x"244F",
+--'1'&x"2450",'1'&x"2451",'1'&x"2452",'1'&x"2453",'1'&x"2454",'1'&x"2455",'1'&x"2456",'1'&x"2457",'1'&x"2458",'1'&x"2459",'1'&x"245A",'1'&x"245B",'1'&x"245C",'1'&x"245D",'1'&x"245E",'1'&x"245F",
+--'1'&x"2460",'1'&x"2461",'1'&x"2462",'1'&x"2463",'1'&x"2464",'1'&x"2465",'1'&x"2466",'1'&x"2467",'1'&x"2468",'1'&x"2469",'1'&x"246A",'1'&x"246B",'1'&x"246C",'1'&x"246D",'1'&x"246E",'1'&x"246F",
+--'1'&x"2470",'1'&x"2471",'1'&x"2472",'1'&x"2473",'1'&x"2474",'1'&x"2475",'1'&x"2476",'1'&x"2477",'1'&x"2478",'1'&x"2479",'1'&x"247A",'1'&x"247B",'1'&x"247C",'1'&x"247D",'1'&x"247E",'1'&x"247F",
+--'1'&x"2480",'1'&x"2481",'1'&x"2482",'1'&x"2483",'1'&x"2484",'1'&x"2485",'1'&x"2486",'1'&x"2487",'1'&x"2488",'1'&x"2489",'1'&x"248A",'1'&x"248B",'1'&x"248C",'1'&x"248D",'1'&x"248E",'1'&x"248F",
+--'1'&x"2490",'1'&x"2491",'1'&x"2492",'1'&x"2493",'1'&x"2494",'1'&x"2495",'1'&x"2496",'1'&x"2497",'1'&x"2498",'1'&x"2499",'1'&x"249A",'1'&x"249B",'1'&x"249C",'1'&x"249D",'1'&x"249E",'1'&x"249F",
+--'1'&x"24A0",'1'&x"24A1",'1'&x"24A2",'1'&x"24A3",'1'&x"24A4",'1'&x"24A5",'1'&x"24A6",'1'&x"24A7",'1'&x"24A8",'1'&x"24A9",'1'&x"24AA",'1'&x"24AB",'1'&x"24AC",'1'&x"24AD",'1'&x"24AE",'1'&x"24AF",
+--'1'&x"24B0",'1'&x"24B1",'1'&x"24B2",'1'&x"24B3",'1'&x"24B4",'1'&x"24B5",'1'&x"24B6",'1'&x"24B7",'1'&x"24B8",'1'&x"24B9",'1'&x"24BA",'1'&x"24BB",'1'&x"24BC",'1'&x"24BD",'1'&x"24BE",'1'&x"24BF",
+--'1'&x"24C0",'1'&x"24C1",'1'&x"24C2",'1'&x"24C3",'1'&x"24C4",'1'&x"24C5",'1'&x"24C6",'1'&x"24C7",'1'&x"24C8",'1'&x"24C9",'1'&x"24CA",'1'&x"24CB",'1'&x"24CC",'1'&x"24CD",'1'&x"24CE",'1'&x"24CF",
+--'1'&x"24D0",'1'&x"24D1",'1'&x"24D2",'1'&x"24D3",'1'&x"24D4",'1'&x"24D5",'1'&x"24D6",'1'&x"24D7",'1'&x"24D8",'1'&x"24D9",'1'&x"24DA",'1'&x"24DB",'1'&x"24DC",'1'&x"24DD",'1'&x"24DE",'1'&x"24DF",
+--'1'&x"24E0",'1'&x"24E1",'1'&x"24E2",'1'&x"24E3",'1'&x"24E4",'1'&x"24E5",'1'&x"24E6",'1'&x"24E7",'1'&x"24E8",'1'&x"24E9",'1'&x"24EA",'1'&x"24EB",'1'&x"24EC",'1'&x"24ED",'1'&x"24EE",'1'&x"24EF",
+--'1'&x"24F0",'1'&x"24F1",'1'&x"24F2",'1'&x"24F3",'1'&x"24F4",'1'&x"24F5",'1'&x"24F6",'1'&x"24F7",'1'&x"24F8",'1'&x"24F9",'1'&x"24FA",'1'&x"24FB",'1'&x"24FC",'1'&x"24FD",'1'&x"24FE",'1'&x"24FF",
+--'1'&x"2500",'1'&x"2501",'1'&x"2502",'1'&x"2503",'1'&x"2504",'1'&x"2505",'1'&x"2506",'1'&x"2507",'1'&x"2508",'1'&x"2509",'1'&x"250A",'1'&x"250B",'1'&x"250C",'1'&x"250D",'1'&x"250E",'1'&x"250F",
+--'1'&x"2510",'1'&x"2511",'1'&x"2512",'1'&x"2513",'1'&x"2514",'1'&x"2515",'1'&x"2516",'1'&x"2517",'1'&x"2518",'1'&x"2519",'1'&x"251A",'1'&x"251B",'1'&x"251C",'1'&x"251D",'1'&x"251E",'1'&x"251F",
+--'1'&x"2520",'1'&x"2521",'1'&x"2522",'1'&x"2523",'1'&x"2524",'1'&x"2525",'1'&x"2526",'1'&x"2527",'1'&x"2528",'1'&x"2529",'1'&x"252A",'1'&x"252B",'1'&x"252C",'1'&x"252D",'1'&x"252E",'1'&x"252F",
+--'1'&x"2530",'1'&x"2531",'1'&x"2532",'1'&x"2533",'1'&x"2534",'1'&x"2535",'1'&x"2536",'1'&x"2537",'1'&x"2538",'1'&x"2539",'1'&x"253A",'1'&x"253B",'1'&x"253C",'1'&x"253D",'1'&x"253E",'1'&x"253F",
+--'1'&x"2540",'1'&x"2541",'1'&x"2542",'1'&x"2543",'1'&x"2544",'1'&x"2545",'1'&x"2546",'1'&x"2547",'1'&x"2548",'1'&x"2549",'1'&x"254A",'1'&x"254B",'1'&x"254C",'1'&x"254D",'1'&x"254E",'1'&x"254F",
+--'1'&x"2550",'1'&x"2551",'1'&x"2552",'1'&x"2553",'1'&x"2554",'1'&x"2555",'1'&x"2556",'1'&x"2557",'1'&x"2558",'1'&x"2559",'1'&x"255A",'1'&x"255B",'1'&x"255C",'1'&x"255D",'1'&x"255E",'1'&x"255F",
+--'1'&x"2560",'1'&x"2561",'1'&x"2562",'1'&x"2563",'1'&x"2564",'1'&x"2565",'1'&x"2566",'1'&x"2567",'1'&x"2568",'1'&x"2569",'1'&x"256A",'1'&x"256B",'1'&x"256C",'1'&x"256D",'1'&x"256E",'1'&x"256F",
+--'1'&x"2570",'1'&x"2571",'1'&x"2572",'1'&x"2573",'1'&x"2574",'1'&x"2575",'1'&x"2576",'1'&x"2577",'1'&x"2578",'1'&x"2579",'1'&x"257A",'1'&x"257B",'1'&x"257C",'1'&x"257D",'1'&x"257E",'1'&x"257F",
+--'1'&x"2580",'1'&x"2581",'1'&x"2582",'1'&x"2583",'1'&x"2584",'1'&x"2585",'1'&x"2586",'1'&x"2587",'1'&x"2588",'1'&x"2589",'1'&x"258A",'1'&x"258B",'1'&x"258C",'1'&x"258D",'1'&x"258E",'1'&x"258F",
+--'1'&x"2590",'1'&x"2591",'1'&x"2592",'1'&x"2593",'1'&x"2594",'1'&x"2595",'1'&x"2596",'1'&x"2597",'1'&x"2598",'1'&x"2599",'1'&x"259A",'1'&x"259B",'1'&x"259C",'1'&x"259D",'1'&x"259E",'1'&x"259F",
+--'1'&x"25A0",'1'&x"25A1",'1'&x"25A2",'1'&x"25A3",'1'&x"25A4",'1'&x"25A5",'1'&x"25A6",'1'&x"25A7",'1'&x"25A8",'1'&x"25A9",'1'&x"25AA",'1'&x"25AB",'1'&x"25AC",'1'&x"25AD",'1'&x"25AE",'1'&x"25AF",
+--'1'&x"25B0",'1'&x"25B1",'1'&x"25B2",'1'&x"25B3",'1'&x"25B4",'1'&x"25B5",'1'&x"25B6",'1'&x"25B7",'1'&x"25B8",'1'&x"25B9",'1'&x"25BA",'1'&x"25BB",'1'&x"25BC",'1'&x"25BD",'1'&x"25BE",'1'&x"25BF",
+--'1'&x"25C0",'1'&x"25C1",'1'&x"25C2",'1'&x"25C3",'1'&x"25C4",'1'&x"25C5",'1'&x"25C6",'1'&x"25C7",'1'&x"25C8",'1'&x"25C9",'1'&x"25CA",'1'&x"25CB",'1'&x"25CC",'1'&x"25CD",'1'&x"25CE",'1'&x"25CF",
+--'1'&x"25D0",'1'&x"25D1",'1'&x"25D2",'1'&x"25D3",'1'&x"25D4",'1'&x"25D5",'1'&x"25D6",'1'&x"25D7",'1'&x"25D8",'1'&x"25D9",'1'&x"25DA",'1'&x"25DB",'1'&x"25DC",'1'&x"25DD",'1'&x"25DE",'1'&x"25DF",
+--'1'&x"25E0",'1'&x"25E1",'1'&x"25E2",'1'&x"25E3",'1'&x"25E4",'1'&x"25E5",'1'&x"25E6",'1'&x"25E7",'1'&x"25E8",'1'&x"25E9",'1'&x"25EA",'1'&x"25EB",'1'&x"25EC",'1'&x"25ED",'1'&x"25EE",'1'&x"25EF",
+--'1'&x"25F0",'1'&x"25F1",'1'&x"25F2",'1'&x"25F3",'1'&x"25F4",'1'&x"25F5",'1'&x"25F6",'1'&x"25F7",'1'&x"25F8",'1'&x"25F9",'1'&x"25FA",'1'&x"25FB",'1'&x"25FC",'1'&x"25FD",'1'&x"25FE",'1'&x"25FF",
+--'1'&x"2600",'1'&x"2601",'1'&x"2602",'1'&x"2603",'1'&x"2604",'1'&x"2605",'1'&x"2606",'1'&x"2607",'1'&x"2608",'1'&x"2609",'1'&x"260A",'1'&x"260B",'1'&x"260C",'1'&x"260D",'1'&x"260E",'1'&x"260F",
+--'1'&x"2610",'1'&x"2611",'1'&x"2612",'1'&x"2613",'1'&x"2614",'1'&x"2615",'1'&x"2616",'1'&x"2617",'1'&x"2618",'1'&x"2619",'1'&x"261A",'1'&x"261B",'1'&x"261C",'1'&x"261D",'1'&x"261E",'1'&x"261F",
+--'1'&x"2620",'1'&x"2621",'1'&x"2622",'1'&x"2623",'1'&x"2624",'1'&x"2625",'1'&x"2626",'1'&x"2627",'1'&x"2628",'1'&x"2629",'1'&x"262A",'1'&x"262B",'1'&x"262C",'1'&x"262D",'1'&x"262E",'1'&x"262F",
+--'1'&x"2630",'1'&x"2631",'1'&x"2632",'1'&x"2633",'1'&x"2634",'1'&x"2635",'1'&x"2636",'1'&x"2637",'1'&x"2638",'1'&x"2639",'1'&x"263A",'1'&x"263B",'1'&x"263C",'1'&x"263D",'1'&x"263E",'1'&x"263F",
+--'1'&x"2640",'1'&x"2641",'1'&x"2642",'1'&x"2643",'1'&x"2644",'1'&x"2645",'1'&x"2646",'1'&x"2647",'1'&x"2648",'1'&x"2649",'1'&x"264A",'1'&x"264B",'1'&x"264C",'1'&x"264D",'1'&x"264E",'1'&x"264F",
+--'1'&x"2650",'1'&x"2651",'1'&x"2652",'1'&x"2653",'1'&x"2654",'1'&x"2655",'1'&x"2656",'1'&x"2657",'1'&x"2658",'1'&x"2659",'1'&x"265A",'1'&x"265B",'1'&x"265C",'1'&x"265D",'1'&x"265E",'1'&x"265F",
+--'1'&x"2660",'1'&x"2661",'1'&x"2662",'1'&x"2663",'1'&x"2664",'1'&x"2665",'1'&x"2666",'1'&x"2667",'1'&x"2668",'1'&x"2669",'1'&x"266A",'1'&x"266B",'1'&x"266C",'1'&x"266D",'1'&x"266E",'1'&x"266F",
+--'1'&x"2670",'1'&x"2671",'1'&x"2672",'1'&x"2673",'1'&x"2674",'1'&x"2675",'1'&x"2676",'1'&x"2677",'1'&x"2678",'1'&x"2679",'1'&x"267A",'1'&x"267B",'1'&x"267C",'1'&x"267D",'1'&x"267E",'1'&x"267F",
+--'1'&x"2680",'1'&x"2681",'1'&x"2682",'1'&x"2683",'1'&x"2684",'1'&x"2685",'1'&x"2686",'1'&x"2687",'1'&x"2688",'1'&x"2689",'1'&x"268A",'1'&x"268B",'1'&x"268C",'1'&x"268D",'1'&x"268E",'1'&x"268F",
+--'1'&x"2690",'1'&x"2691",'1'&x"2692",'1'&x"2693",'1'&x"2694",'1'&x"2695",'1'&x"2696",'1'&x"2697",'1'&x"2698",'1'&x"2699",'1'&x"269A",'1'&x"269B",'1'&x"269C",'1'&x"269D",'1'&x"269E",'1'&x"269F",
+--'1'&x"26A0",'1'&x"26A1",'1'&x"26A2",'1'&x"26A3",'1'&x"26A4",'1'&x"26A5",'1'&x"26A6",'1'&x"26A7",'1'&x"26A8",'1'&x"26A9",'1'&x"26AA",'1'&x"26AB",'1'&x"26AC",'1'&x"26AD",'1'&x"26AE",'1'&x"26AF",
+--'1'&x"26B0",'1'&x"26B1",'1'&x"26B2",'1'&x"26B3",'1'&x"26B4",'1'&x"26B5",'1'&x"26B6",'1'&x"26B7",'1'&x"26B8",'1'&x"26B9",'1'&x"26BA",'1'&x"26BB",'1'&x"26BC",'1'&x"26BD",'1'&x"26BE",'1'&x"26BF",
+--'1'&x"26C0",'1'&x"26C1",'1'&x"26C2",'1'&x"26C3",'1'&x"26C4",'1'&x"26C5",'1'&x"26C6",'1'&x"26C7",'1'&x"26C8",'1'&x"26C9",'1'&x"26CA",'1'&x"26CB",'1'&x"26CC",'1'&x"26CD",'1'&x"26CE",'1'&x"26CF",
+--'1'&x"26D0",'1'&x"26D1",'1'&x"26D2",'1'&x"26D3",'1'&x"26D4",'1'&x"26D5",'1'&x"26D6",'1'&x"26D7",'1'&x"26D8",'1'&x"26D9",'1'&x"26DA",'1'&x"26DB",'1'&x"26DC",'1'&x"26DD",'1'&x"26DE",'1'&x"26DF",
+--'1'&x"26E0",'1'&x"26E1",'1'&x"26E2",'1'&x"26E3",'1'&x"26E4",'1'&x"26E5",'1'&x"26E6",'1'&x"26E7",'1'&x"26E8",'1'&x"26E9",'1'&x"26EA",'1'&x"26EB",'1'&x"26EC",'1'&x"26ED",'1'&x"26EE",'1'&x"26EF",
+--'1'&x"26F0",'1'&x"26F1",'1'&x"26F2",'1'&x"26F3",'1'&x"26F4",'1'&x"26F5",'1'&x"26F6",'1'&x"26F7",'1'&x"26F8",'1'&x"26F9",'1'&x"26FA",'1'&x"26FB",'1'&x"26FC",'1'&x"26FD",'1'&x"26FE",'1'&x"26FF",
+--'1'&x"2700",'1'&x"2701",'1'&x"2702",'1'&x"2703",'1'&x"2704",'1'&x"2705",'1'&x"2706",'1'&x"2707",'1'&x"2708",'1'&x"2709",'1'&x"270A",'1'&x"270B",'1'&x"270C",'1'&x"270D",'1'&x"270E",'1'&x"270F",
+--'1'&x"2710",'1'&x"2711",'1'&x"2712",'1'&x"2713",'1'&x"2714",'1'&x"2715",'1'&x"2716",'1'&x"2717",'1'&x"2718",'1'&x"2719",'1'&x"271A",'1'&x"271B",'1'&x"271C",'1'&x"271D",'1'&x"271E",'1'&x"271F",
+--'1'&x"2720",'1'&x"2721",'1'&x"2722",'1'&x"2723",'1'&x"2724",'1'&x"2725",'1'&x"2726",'1'&x"2727",'1'&x"2728",'1'&x"2729",'1'&x"272A",'1'&x"272B",'1'&x"272C",'1'&x"272D",'1'&x"272E",'1'&x"272F",
+--'1'&x"2730",'1'&x"2731",'1'&x"2732",'1'&x"2733",'1'&x"2734",'1'&x"2735",'1'&x"2736",'1'&x"2737",'1'&x"2738",'1'&x"2739",'1'&x"273A",'1'&x"273B",'1'&x"273C",'1'&x"273D",'1'&x"273E",'1'&x"273F",
+--'1'&x"2740",'1'&x"2741",'1'&x"2742",'1'&x"2743",'1'&x"2744",'1'&x"2745",'1'&x"2746",'1'&x"2747",'1'&x"2748",'1'&x"2749",'1'&x"274A",'1'&x"274B",'1'&x"274C",'1'&x"274D",'1'&x"274E",'1'&x"274F",
+--'1'&x"2750",'1'&x"2751",'1'&x"2752",'1'&x"2753",'1'&x"2754",'1'&x"2755",'1'&x"2756",'1'&x"2757",'1'&x"2758",'1'&x"2759",'1'&x"275A",'1'&x"275B",'1'&x"275C",'1'&x"275D",'1'&x"275E",'1'&x"275F",
+--'1'&x"2760",'1'&x"2761",'1'&x"2762",'1'&x"2763",'1'&x"2764",'1'&x"2765",'1'&x"2766",'1'&x"2767",'1'&x"2768",'1'&x"2769",'1'&x"276A",'1'&x"276B",'1'&x"276C",'1'&x"276D",'1'&x"276E",'1'&x"276F",
+--'1'&x"2770",'1'&x"2771",'1'&x"2772",'1'&x"2773",'1'&x"2774",'1'&x"2775",'1'&x"2776",'1'&x"2777",'1'&x"2778",'1'&x"2779",'1'&x"277A",'1'&x"277B",'1'&x"277C",'1'&x"277D",'1'&x"277E",'1'&x"277F",
+--'1'&x"2780",'1'&x"2781",'1'&x"2782",'1'&x"2783",'1'&x"2784",'1'&x"2785",'1'&x"2786",'1'&x"2787",'1'&x"2788",'1'&x"2789",'1'&x"278A",'1'&x"278B",'1'&x"278C",'1'&x"278D",'1'&x"278E",'1'&x"278F",
+--'1'&x"2790",'1'&x"2791",'1'&x"2792",'1'&x"2793",'1'&x"2794",'1'&x"2795",'1'&x"2796",'1'&x"2797",'1'&x"2798",'1'&x"2799",'1'&x"279A",'1'&x"279B",'1'&x"279C",'1'&x"279D",'1'&x"279E",'1'&x"279F",
+--'1'&x"27A0",'1'&x"27A1",'1'&x"27A2",'1'&x"27A3",'1'&x"27A4",'1'&x"27A5",'1'&x"27A6",'1'&x"27A7",'1'&x"27A8",'1'&x"27A9",'1'&x"27AA",'1'&x"27AB",'1'&x"27AC",'1'&x"27AD",'1'&x"27AE",'1'&x"27AF",
+--'1'&x"27B0",'1'&x"27B1",'1'&x"27B2",'1'&x"27B3",'1'&x"27B4",'1'&x"27B5",'1'&x"27B6",'1'&x"27B7",'1'&x"27B8",'1'&x"27B9",'1'&x"27BA",'1'&x"27BB",'1'&x"27BC",'1'&x"27BD",'1'&x"27BE",'1'&x"27BF",
+--'1'&x"27C0",'1'&x"27C1",'1'&x"27C2",'1'&x"27C3",'1'&x"27C4",'1'&x"27C5",'1'&x"27C6",'1'&x"27C7",'1'&x"27C8",'1'&x"27C9",'1'&x"27CA",'1'&x"27CB",'1'&x"27CC",'1'&x"27CD",'1'&x"27CE",'1'&x"27CF",
+--'1'&x"27D0",'1'&x"27D1",'1'&x"27D2",'1'&x"27D3",'1'&x"27D4",'1'&x"27D5",'1'&x"27D6",'1'&x"27D7",'1'&x"27D8",'1'&x"27D9",'1'&x"27DA",'1'&x"27DB",'1'&x"27DC",'1'&x"27DD",'1'&x"27DE",'1'&x"27DF",
+--'1'&x"27E0",'1'&x"27E1",'1'&x"27E2",'1'&x"27E3",'1'&x"27E4",'1'&x"27E5",'1'&x"27E6",'1'&x"27E7",'1'&x"27E8",'1'&x"27E9",'1'&x"27EA",'1'&x"27EB",'1'&x"27EC",'1'&x"27ED",'1'&x"27EE",'1'&x"27EF",
+--'1'&x"27F0",'1'&x"27F1",'1'&x"27F2",'1'&x"27F3",'1'&x"27F4",'1'&x"27F5",'1'&x"27F6",'1'&x"27F7",'1'&x"27F8",'1'&x"27F9",'1'&x"27FA",'1'&x"27FB",'1'&x"27FC",'1'&x"27FD",'1'&x"27FE",'1'&x"27FF",
+--'1'&x"2800",'1'&x"2801",'1'&x"2802",'1'&x"2803",'1'&x"2804",'1'&x"2805",'1'&x"2806",'1'&x"2807",'1'&x"2808",'1'&x"2809",'1'&x"280A",'1'&x"280B",'1'&x"280C",'1'&x"280D",'1'&x"280E",'1'&x"280F",
+--'1'&x"2810",'1'&x"2811",'1'&x"2812",'1'&x"2813",'1'&x"2814",'1'&x"2815",'1'&x"2816",'1'&x"2817",'1'&x"2818",'1'&x"2819",'1'&x"281A",'1'&x"281B",'1'&x"281C",'1'&x"281D",'1'&x"281E",'1'&x"281F",
+--'1'&x"2820",'1'&x"2821",'1'&x"2822",'1'&x"2823",'1'&x"2824",'1'&x"2825",'1'&x"2826",'1'&x"2827",'1'&x"2828",'1'&x"2829",'1'&x"282A",'1'&x"282B",'1'&x"282C",'1'&x"282D",'1'&x"282E",'1'&x"282F",
+--'1'&x"2830",'1'&x"2831",'1'&x"2832",'1'&x"2833",'1'&x"2834",'1'&x"2835",'1'&x"2836",'1'&x"2837",'1'&x"2838",'1'&x"2839",'1'&x"283A",'1'&x"283B",'1'&x"283C",'1'&x"283D",'1'&x"283E",'1'&x"283F",
+--'1'&x"2840",'1'&x"2841",'1'&x"2842",'1'&x"2843",'1'&x"2844",'1'&x"2845",'1'&x"2846",'1'&x"2847",'1'&x"2848",'1'&x"2849",'1'&x"284A",'1'&x"284B",'1'&x"284C",'1'&x"284D",'1'&x"284E",'1'&x"284F",
+--'1'&x"2850",'1'&x"2851",'1'&x"2852",'1'&x"2853",'1'&x"2854",'1'&x"2855",'1'&x"2856",'1'&x"2857",'1'&x"2858",'1'&x"2859",'1'&x"285A",'1'&x"285B",'1'&x"285C",'1'&x"285D",'1'&x"285E",'1'&x"285F",
+--'1'&x"2860",'1'&x"2861",'1'&x"2862",'1'&x"2863",'1'&x"2864",'1'&x"2865",'1'&x"2866",'1'&x"2867",'1'&x"2868",'1'&x"2869",'1'&x"286A",'1'&x"286B",'1'&x"286C",'1'&x"286D",'1'&x"286E",'1'&x"286F",
+--'1'&x"2870",'1'&x"2871",'1'&x"2872",'1'&x"2873",'1'&x"2874",'1'&x"2875",'1'&x"2876",'1'&x"2877",'1'&x"2878",'1'&x"2879",'1'&x"287A",'1'&x"287B",'1'&x"287C",'1'&x"287D",'1'&x"287E",'1'&x"287F",
+--'1'&x"2880",'1'&x"2881",'1'&x"2882",'1'&x"2883",'1'&x"2884",'1'&x"2885",'1'&x"2886",'1'&x"2887",'1'&x"2888",'1'&x"2889",'1'&x"288A",'1'&x"288B",'1'&x"288C",'1'&x"288D",'1'&x"288E",'1'&x"288F",
+--'1'&x"2890",'1'&x"2891",'1'&x"2892",'1'&x"2893",'1'&x"2894",'1'&x"2895",'1'&x"2896",'1'&x"2897",'1'&x"2898",'1'&x"2899",'1'&x"289A",'1'&x"289B",'1'&x"289C",'1'&x"289D",'1'&x"289E",'1'&x"289F",
+--'1'&x"28A0",'1'&x"28A1",'1'&x"28A2",'1'&x"28A3",'1'&x"28A4",'1'&x"28A5",'1'&x"28A6",'1'&x"28A7",'1'&x"28A8",'1'&x"28A9",'1'&x"28AA",'1'&x"28AB",'1'&x"28AC",'1'&x"28AD",'1'&x"28AE",'1'&x"28AF",
+--'1'&x"28B0",'1'&x"28B1",'1'&x"28B2",'1'&x"28B3",'1'&x"28B4",'1'&x"28B5",'1'&x"28B6",'1'&x"28B7",'1'&x"28B8",'1'&x"28B9",'1'&x"28BA",'1'&x"28BB",'1'&x"28BC",'1'&x"28BD",'1'&x"28BE",'1'&x"28BF",
+--'1'&x"28C0",'1'&x"28C1",'1'&x"28C2",'1'&x"28C3",'1'&x"28C4",'1'&x"28C5",'1'&x"28C6",'1'&x"28C7",'1'&x"28C8",'1'&x"28C9",'1'&x"28CA",'1'&x"28CB",'1'&x"28CC",'1'&x"28CD",'1'&x"28CE",'1'&x"28CF",
+--'1'&x"28D0",'1'&x"28D1",'1'&x"28D2",'1'&x"28D3",'1'&x"28D4",'1'&x"28D5",'1'&x"28D6",'1'&x"28D7",'1'&x"28D8",'1'&x"28D9",'1'&x"28DA",'1'&x"28DB",'1'&x"28DC",'1'&x"28DD",'1'&x"28DE",'1'&x"28DF",
+--'1'&x"28E0",'1'&x"28E1",'1'&x"28E2",'1'&x"28E3",'1'&x"28E4",'1'&x"28E5",'1'&x"28E6",'1'&x"28E7",'1'&x"28E8",'1'&x"28E9",'1'&x"28EA",'1'&x"28EB",'1'&x"28EC",'1'&x"28ED",'1'&x"28EE",'1'&x"28EF",
+--'1'&x"28F0",'1'&x"28F1",'1'&x"28F2",'1'&x"28F3",'1'&x"28F4",'1'&x"28F5",'1'&x"28F6",'1'&x"28F7",'1'&x"28F8",'1'&x"28F9",'1'&x"28FA",'1'&x"28FB",'1'&x"28FC",'1'&x"28FD",'1'&x"28FE",'1'&x"28FF",
+--'1'&x"2900",'1'&x"2901",'1'&x"2902",'1'&x"2903",'1'&x"2904",'1'&x"2905",'1'&x"2906",'1'&x"2907",'1'&x"2908",'1'&x"2909",'1'&x"290A",'1'&x"290B",'1'&x"290C",'1'&x"290D",'1'&x"290E",'1'&x"290F",
+--'1'&x"2910",'1'&x"2911",'1'&x"2912",'1'&x"2913",'1'&x"2914",'1'&x"2915",'1'&x"2916",'1'&x"2917",'1'&x"2918",'1'&x"2919",'1'&x"291A",'1'&x"291B",'1'&x"291C",'1'&x"291D",'1'&x"291E",'1'&x"291F",
+--'1'&x"2920",'1'&x"2921",'1'&x"2922",'1'&x"2923",'1'&x"2924",'1'&x"2925",'1'&x"2926",'1'&x"2927",'1'&x"2928",'1'&x"2929",'1'&x"292A",'1'&x"292B",'1'&x"292C",'1'&x"292D",'1'&x"292E",'1'&x"292F",
+--'1'&x"2930",'1'&x"2931",'1'&x"2932",'1'&x"2933",'1'&x"2934",'1'&x"2935",'1'&x"2936",'1'&x"2937",'1'&x"2938",'1'&x"2939",'1'&x"293A",'1'&x"293B",'1'&x"293C",'1'&x"293D",'1'&x"293E",'1'&x"293F",
+--'1'&x"2940",'1'&x"2941",'1'&x"2942",'1'&x"2943",'1'&x"2944",'1'&x"2945",'1'&x"2946",'1'&x"2947",'1'&x"2948",'1'&x"2949",'1'&x"294A",'1'&x"294B",'1'&x"294C",'1'&x"294D",'1'&x"294E",'1'&x"294F",
+--'1'&x"2950",'1'&x"2951",'1'&x"2952",'1'&x"2953",'1'&x"2954",'1'&x"2955",'1'&x"2956",'1'&x"2957",'1'&x"2958",'1'&x"2959",'1'&x"295A",'1'&x"295B",'1'&x"295C",'1'&x"295D",'1'&x"295E",'1'&x"295F",
+--'1'&x"2960",'1'&x"2961",'1'&x"2962",'1'&x"2963",'1'&x"2964",'1'&x"2965",'1'&x"2966",'1'&x"2967",'1'&x"2968",'1'&x"2969",'1'&x"296A",'1'&x"296B",'1'&x"296C",'1'&x"296D",'1'&x"296E",'1'&x"296F",
+--'1'&x"2970",'1'&x"2971",'1'&x"2972",'1'&x"2973",'1'&x"2974",'1'&x"2975",'1'&x"2976",'1'&x"2977",'1'&x"2978",'1'&x"2979",'1'&x"297A",'1'&x"297B",'1'&x"297C",'1'&x"297D",'1'&x"297E",'1'&x"297F",
+--'1'&x"2980",'1'&x"2981",'1'&x"2982",'1'&x"2983",'1'&x"2984",'1'&x"2985",'1'&x"2986",'1'&x"2987",'1'&x"2988",'1'&x"2989",'1'&x"298A",'1'&x"298B",'1'&x"298C",'1'&x"298D",'1'&x"298E",'1'&x"298F",
+--'1'&x"2990",'1'&x"2991",'1'&x"2992",'1'&x"2993",'1'&x"2994",'1'&x"2995",'1'&x"2996",'1'&x"2997",'1'&x"2998",'1'&x"2999",'1'&x"299A",'1'&x"299B",'1'&x"299C",'1'&x"299D",'1'&x"299E",'1'&x"299F",
+--'1'&x"29A0",'1'&x"29A1",'1'&x"29A2",'1'&x"29A3",'1'&x"29A4",'1'&x"29A5",'1'&x"29A6",'1'&x"29A7",'1'&x"29A8",'1'&x"29A9",'1'&x"29AA",'1'&x"29AB",'1'&x"29AC",'1'&x"29AD",'1'&x"29AE",'1'&x"29AF",
+--'1'&x"29B0",'1'&x"29B1",'1'&x"29B2",'1'&x"29B3",'1'&x"29B4",'1'&x"29B5",'1'&x"29B6",'1'&x"29B7",'1'&x"29B8",'1'&x"29B9",'1'&x"29BA",'1'&x"29BB",'1'&x"29BC",'1'&x"29BD",'1'&x"29BE",'1'&x"29BF",
+--'1'&x"29C0",'1'&x"29C1",'1'&x"29C2",'1'&x"29C3",'1'&x"29C4",'1'&x"29C5",'1'&x"29C6",'1'&x"29C7",'1'&x"29C8",'1'&x"29C9",'1'&x"29CA",'1'&x"29CB",'1'&x"29CC",'1'&x"29CD",'1'&x"29CE",'1'&x"29CF",
+--'1'&x"29D0",'1'&x"29D1",'1'&x"29D2",'1'&x"29D3",'1'&x"29D4",'1'&x"29D5",'1'&x"29D6",'1'&x"29D7",'1'&x"29D8",'1'&x"29D9",'1'&x"29DA",'1'&x"29DB",'1'&x"29DC",'1'&x"29DD",'1'&x"29DE",'1'&x"29DF",
+--'1'&x"29E0",'1'&x"29E1",'1'&x"29E2",'1'&x"29E3",'1'&x"29E4",'1'&x"29E5",'1'&x"29E6",'1'&x"29E7",'1'&x"29E8",'1'&x"29E9",'1'&x"29EA",'1'&x"29EB",'1'&x"29EC",'1'&x"29ED",'1'&x"29EE",'1'&x"29EF",
+--'1'&x"29F0",'1'&x"29F1",'1'&x"29F2",'1'&x"29F3",'1'&x"29F4",'1'&x"29F5",'1'&x"29F6",'1'&x"29F7",'1'&x"29F8",'1'&x"29F9",'1'&x"29FA",'1'&x"29FB",'1'&x"29FC",'1'&x"29FD",'1'&x"29FE",'1'&x"29FF",
+--'1'&x"2A00",'1'&x"2A01",'1'&x"2A02",'1'&x"2A03",'1'&x"2A04",'1'&x"2A05",'1'&x"2A06",'1'&x"2A07",'1'&x"2A08",'1'&x"2A09",'1'&x"2A0A",'1'&x"2A0B",'1'&x"2A0C",'1'&x"2A0D",'1'&x"2A0E",'1'&x"2A0F",
+--'1'&x"2A10",'1'&x"2A11",'1'&x"2A12",'1'&x"2A13",'1'&x"2A14",'1'&x"2A15",'1'&x"2A16",'1'&x"2A17",'1'&x"2A18",'1'&x"2A19",'1'&x"2A1A",'1'&x"2A1B",'1'&x"2A1C",'1'&x"2A1D",'1'&x"2A1E",'1'&x"2A1F",
+--'1'&x"2A20",'1'&x"2A21",'1'&x"2A22",'1'&x"2A23",'1'&x"2A24",'1'&x"2A25",'1'&x"2A26",'1'&x"2A27",'1'&x"2A28",'1'&x"2A29",'1'&x"2A2A",'1'&x"2A2B",'1'&x"2A2C",'1'&x"2A2D",'1'&x"2A2E",'1'&x"2A2F",
+--'1'&x"2A30",'1'&x"2A31",'1'&x"2A32",'1'&x"2A33",'1'&x"2A34",'1'&x"2A35",'1'&x"2A36",'1'&x"2A37",'1'&x"2A38",'1'&x"2A39",'1'&x"2A3A",'1'&x"2A3B",'1'&x"2A3C",'1'&x"2A3D",'1'&x"2A3E",'1'&x"2A3F",
+--'1'&x"2A40",'1'&x"2A41",'1'&x"2A42",'1'&x"2A43",'1'&x"2A44",'1'&x"2A45",'1'&x"2A46",'1'&x"2A47",'1'&x"2A48",'1'&x"2A49",'1'&x"2A4A",'1'&x"2A4B",'1'&x"2A4C",'1'&x"2A4D",'1'&x"2A4E",'1'&x"2A4F",
+--'1'&x"2A50",'1'&x"2A51",'1'&x"2A52",'1'&x"2A53",'1'&x"2A54",'1'&x"2A55",'1'&x"2A56",'1'&x"2A57",'1'&x"2A58",'1'&x"2A59",'1'&x"2A5A",'1'&x"2A5B",'1'&x"2A5C",'1'&x"2A5D",'1'&x"2A5E",'1'&x"2A5F",
+--'1'&x"2A60",'1'&x"2A61",'1'&x"2A62",'1'&x"2A63",'1'&x"2A64",'1'&x"2A65",'1'&x"2A66",'1'&x"2A67",'1'&x"2A68",'1'&x"2A69",'1'&x"2A6A",'1'&x"2A6B",'1'&x"2A6C",'1'&x"2A6D",'1'&x"2A6E",'1'&x"2A6F",
+--'1'&x"2A70",'1'&x"2A71",'1'&x"2A72",'1'&x"2A73",'1'&x"2A74",'1'&x"2A75",'1'&x"2A76",'1'&x"2A77",'1'&x"2A78",'1'&x"2A79",'1'&x"2A7A",'1'&x"2A7B",'1'&x"2A7C",'1'&x"2A7D",'1'&x"2A7E",'1'&x"2A7F",
+--'1'&x"2A80",'1'&x"2A81",'1'&x"2A82",'1'&x"2A83",'1'&x"2A84",'1'&x"2A85",'1'&x"2A86",'1'&x"2A87",'1'&x"2A88",'1'&x"2A89",'1'&x"2A8A",'1'&x"2A8B",'1'&x"2A8C",'1'&x"2A8D",'1'&x"2A8E",'1'&x"2A8F",
+--'1'&x"2A90",'1'&x"2A91",'1'&x"2A92",'1'&x"2A93",'1'&x"2A94",'1'&x"2A95",'1'&x"2A96",'1'&x"2A97",'1'&x"2A98",'1'&x"2A99",'1'&x"2A9A",'1'&x"2A9B",'1'&x"2A9C",'1'&x"2A9D",'1'&x"2A9E",'1'&x"2A9F",
+--'1'&x"2AA0",'1'&x"2AA1",'1'&x"2AA2",'1'&x"2AA3",'1'&x"2AA4",'1'&x"2AA5",'1'&x"2AA6",'1'&x"2AA7",'1'&x"2AA8",'1'&x"2AA9",'1'&x"2AAA",'1'&x"2AAB",'1'&x"2AAC",'1'&x"2AAD",'1'&x"2AAE",'1'&x"2AAF",
+--'1'&x"2AB0",'1'&x"2AB1",'1'&x"2AB2",'1'&x"2AB3",'1'&x"2AB4",'1'&x"2AB5",'1'&x"2AB6",'1'&x"2AB7",'1'&x"2AB8",'1'&x"2AB9",'1'&x"2ABA",'1'&x"2ABB",'1'&x"2ABC",'1'&x"2ABD",'1'&x"2ABE",'1'&x"2ABF",
+--'1'&x"2AC0",'1'&x"2AC1",'1'&x"2AC2",'1'&x"2AC3",'1'&x"2AC4",'1'&x"2AC5",'1'&x"2AC6",'1'&x"2AC7",'1'&x"2AC8",'1'&x"2AC9",'1'&x"2ACA",'1'&x"2ACB",'1'&x"2ACC",'1'&x"2ACD",'1'&x"2ACE",'1'&x"2ACF",
+--'1'&x"2AD0",'1'&x"2AD1",'1'&x"2AD2",'1'&x"2AD3",'1'&x"2AD4",'1'&x"2AD5",'1'&x"2AD6",'1'&x"2AD7",'1'&x"2AD8",'1'&x"2AD9",'1'&x"2ADA",'1'&x"2ADB",'1'&x"2ADC",'1'&x"2ADD",'1'&x"2ADE",'1'&x"2ADF",
+--'1'&x"2AE0",'1'&x"2AE1",'1'&x"2AE2",'1'&x"2AE3",'1'&x"2AE4",'1'&x"2AE5",'1'&x"2AE6",'1'&x"2AE7",'1'&x"2AE8",'1'&x"2AE9",'1'&x"2AEA",'1'&x"2AEB",'1'&x"2AEC",'1'&x"2AED",'1'&x"2AEE",'1'&x"2AEF",
+--'1'&x"2AF0",'1'&x"2AF1",'1'&x"2AF2",'1'&x"2AF3",'1'&x"2AF4",'1'&x"2AF5",'1'&x"2AF6",'1'&x"2AF7",'1'&x"2AF8",'1'&x"2AF9",'1'&x"2AFA",'1'&x"2AFB",'1'&x"2AFC",'1'&x"2AFD",'1'&x"2AFE",'1'&x"2AFF",
+--'1'&x"2B00",'1'&x"2B01",'1'&x"2B02",'1'&x"2B03",'1'&x"2B04",'1'&x"2B05",'1'&x"2B06",'1'&x"2B07",'1'&x"2B08",'1'&x"2B09",'1'&x"2B0A",'1'&x"2B0B",'1'&x"2B0C",'1'&x"2B0D",'1'&x"2B0E",'1'&x"2B0F",
+--'1'&x"2B10",'1'&x"2B11",'1'&x"2B12",'1'&x"2B13",'1'&x"2B14",'1'&x"2B15",'1'&x"2B16",'1'&x"2B17",'1'&x"2B18",'1'&x"2B19",'1'&x"2B1A",'1'&x"2B1B",'1'&x"2B1C",'1'&x"2B1D",'1'&x"2B1E",'1'&x"2B1F",
+--'1'&x"2B20",'1'&x"2B21",'1'&x"2B22",'1'&x"2B23",'1'&x"2B24",'1'&x"2B25",'1'&x"2B26",'1'&x"2B27",'1'&x"2B28",'1'&x"2B29",'1'&x"2B2A",'1'&x"2B2B",'1'&x"2B2C",'1'&x"2B2D",'1'&x"2B2E",'1'&x"2B2F",
+--'1'&x"2B30",'1'&x"2B31",'1'&x"2B32",'1'&x"2B33",'1'&x"2B34",'1'&x"2B35",'1'&x"2B36",'1'&x"2B37",'1'&x"2B38",'1'&x"2B39",'1'&x"2B3A",'1'&x"2B3B",'1'&x"2B3C",'1'&x"2B3D",'1'&x"2B3E",'1'&x"2B3F",
+--'1'&x"2B40",'1'&x"2B41",'1'&x"2B42",'1'&x"2B43",'1'&x"2B44",'1'&x"2B45",'1'&x"2B46",'1'&x"2B47",'1'&x"2B48",'1'&x"2B49",'1'&x"2B4A",'1'&x"2B4B",'1'&x"2B4C",'1'&x"2B4D",'1'&x"2B4E",'1'&x"2B4F",
+--'1'&x"2B50",'1'&x"2B51",'1'&x"2B52",'1'&x"2B53",'1'&x"2B54",'1'&x"2B55",'1'&x"2B56",'1'&x"2B57",'1'&x"2B58",'1'&x"2B59",'1'&x"2B5A",'1'&x"2B5B",'1'&x"2B5C",'1'&x"2B5D",'1'&x"2B5E",'1'&x"2B5F",
+--'1'&x"2B60",'1'&x"2B61",'1'&x"2B62",'1'&x"2B63",'1'&x"2B64",'1'&x"2B65",'1'&x"2B66",'1'&x"2B67",'1'&x"2B68",'1'&x"2B69",'1'&x"2B6A",'1'&x"2B6B",'1'&x"2B6C",'1'&x"2B6D",'1'&x"2B6E",'1'&x"2B6F",
+--'1'&x"2B70",'1'&x"2B71",'1'&x"2B72",'1'&x"2B73",'1'&x"2B74",'1'&x"2B75",'1'&x"2B76",'1'&x"2B77",'1'&x"2B78",'1'&x"2B79",'1'&x"2B7A",'1'&x"2B7B",'1'&x"2B7C",'1'&x"2B7D",'1'&x"2B7E",'1'&x"2B7F",
+--'1'&x"2B80",'1'&x"2B81",'1'&x"2B82",'1'&x"2B83",'1'&x"2B84",'1'&x"2B85",'1'&x"2B86",'1'&x"2B87",'1'&x"2B88",'1'&x"2B89",'1'&x"2B8A",'1'&x"2B8B",'1'&x"2B8C",'1'&x"2B8D",'1'&x"2B8E",'1'&x"2B8F",
+--'1'&x"2B90",'1'&x"2B91",'1'&x"2B92",'1'&x"2B93",'1'&x"2B94",'1'&x"2B95",'1'&x"2B96",'1'&x"2B97",'1'&x"2B98",'1'&x"2B99",'1'&x"2B9A",'1'&x"2B9B",'1'&x"2B9C",'1'&x"2B9D",'1'&x"2B9E",'1'&x"2B9F",
+--'1'&x"2BA0",'1'&x"2BA1",'1'&x"2BA2",'1'&x"2BA3",'1'&x"2BA4",'1'&x"2BA5",'1'&x"2BA6",'1'&x"2BA7",'1'&x"2BA8",'1'&x"2BA9",'1'&x"2BAA",'1'&x"2BAB",'1'&x"2BAC",'1'&x"2BAD",'1'&x"2BAE",'1'&x"2BAF",
+--'1'&x"2BB0",'1'&x"2BB1",'1'&x"2BB2",'1'&x"2BB3",'1'&x"2BB4",'1'&x"2BB5",'1'&x"2BB6",'1'&x"2BB7",'1'&x"2BB8",'1'&x"2BB9",'1'&x"2BBA",'1'&x"2BBB",'1'&x"2BBC",'1'&x"2BBD",'1'&x"2BBE",'1'&x"2BBF",
+--'1'&x"2BC0",'1'&x"2BC1",'1'&x"2BC2",'1'&x"2BC3",'1'&x"2BC4",'1'&x"2BC5",'1'&x"2BC6",'1'&x"2BC7",'1'&x"2BC8",'1'&x"2BC9",'1'&x"2BCA",'1'&x"2BCB",'1'&x"2BCC",'1'&x"2BCD",'1'&x"2BCE",'1'&x"2BCF",
+--'1'&x"2BD0",'1'&x"2BD1",'1'&x"2BD2",'1'&x"2BD3",'1'&x"2BD4",'1'&x"2BD5",'1'&x"2BD6",'1'&x"2BD7",'1'&x"2BD8",'1'&x"2BD9",'1'&x"2BDA",'1'&x"2BDB",'1'&x"2BDC",'1'&x"2BDD",'1'&x"2BDE",'1'&x"2BDF",
+--'1'&x"2BE0",'1'&x"2BE1",'1'&x"2BE2",'1'&x"2BE3",'1'&x"2BE4",'1'&x"2BE5",'1'&x"2BE6",'1'&x"2BE7",'1'&x"2BE8",'1'&x"2BE9",'1'&x"2BEA",'1'&x"2BEB",'1'&x"2BEC",'1'&x"2BED",'1'&x"2BEE",'1'&x"2BEF",
+--'1'&x"2BF0",'1'&x"2BF1",'1'&x"2BF2",'1'&x"2BF3",'1'&x"2BF4",'1'&x"2BF5",'1'&x"2BF6",'1'&x"2BF7",'1'&x"2BF8",'1'&x"2BF9",'1'&x"2BFA",'1'&x"2BFB",'1'&x"2BFC",'1'&x"2BFD",'1'&x"2BFE",'1'&x"2BFF",
+--'1'&x"2C00",'1'&x"2C01",'1'&x"2C02",'1'&x"2C03",'1'&x"2C04",'1'&x"2C05",'1'&x"2C06",'1'&x"2C07",'1'&x"2C08",'1'&x"2C09",'1'&x"2C0A",'1'&x"2C0B",'1'&x"2C0C",'1'&x"2C0D",'1'&x"2C0E",'1'&x"2C0F",
+--'1'&x"2C10",'1'&x"2C11",'1'&x"2C12",'1'&x"2C13",'1'&x"2C14",'1'&x"2C15",'1'&x"2C16",'1'&x"2C17",'1'&x"2C18",'1'&x"2C19",'1'&x"2C1A",'1'&x"2C1B",'1'&x"2C1C",'1'&x"2C1D",'1'&x"2C1E",'1'&x"2C1F",
+--'1'&x"2C20",'1'&x"2C21",'1'&x"2C22",'1'&x"2C23",'1'&x"2C24",'1'&x"2C25",'1'&x"2C26",'1'&x"2C27",'1'&x"2C28",'1'&x"2C29",'1'&x"2C2A",'1'&x"2C2B",'1'&x"2C2C",'1'&x"2C2D",'1'&x"2C2E",'1'&x"2C2F",
+--'1'&x"2C30",'1'&x"2C31",'1'&x"2C32",'1'&x"2C33",'1'&x"2C34",'1'&x"2C35",'1'&x"2C36",'1'&x"2C37",'1'&x"2C38",'1'&x"2C39",'1'&x"2C3A",'1'&x"2C3B",'1'&x"2C3C",'1'&x"2C3D",'1'&x"2C3E",'1'&x"2C3F",
+--'1'&x"2C40",'1'&x"2C41",'1'&x"2C42",'1'&x"2C43",'1'&x"2C44",'1'&x"2C45",'1'&x"2C46",'1'&x"2C47",'1'&x"2C48",'1'&x"2C49",'1'&x"2C4A",'1'&x"2C4B",'1'&x"2C4C",'1'&x"2C4D",'1'&x"2C4E",'1'&x"2C4F",
+--'1'&x"2C50",'1'&x"2C51",'1'&x"2C52",'1'&x"2C53",'1'&x"2C54",'1'&x"2C55",'1'&x"2C56",'1'&x"2C57",'1'&x"2C58",'1'&x"2C59",'1'&x"2C5A",'1'&x"2C5B",'1'&x"2C5C",'1'&x"2C5D",'1'&x"2C5E",'1'&x"2C5F",
+--'1'&x"2C60",'1'&x"2C61",'1'&x"2C62",'1'&x"2C63",'1'&x"2C64",'1'&x"2C65",'1'&x"2C66",'1'&x"2C67",'1'&x"2C68",'1'&x"2C69",'1'&x"2C6A",'1'&x"2C6B",'1'&x"2C6C",'1'&x"2C6D",'1'&x"2C6E",'1'&x"2C6F",
+--'1'&x"2C70",'1'&x"2C71",'1'&x"2C72",'1'&x"2C73",'1'&x"2C74",'1'&x"2C75",'1'&x"2C76",'1'&x"2C77",'1'&x"2C78",'1'&x"2C79",'1'&x"2C7A",'1'&x"2C7B",'1'&x"2C7C",'1'&x"2C7D",'1'&x"2C7E",'1'&x"2C7F",
+--'1'&x"2C80",'1'&x"2C81",'1'&x"2C82",'1'&x"2C83",'1'&x"2C84",'1'&x"2C85",'1'&x"2C86",'1'&x"2C87",'1'&x"2C88",'1'&x"2C89",'1'&x"2C8A",'1'&x"2C8B",'1'&x"2C8C",'1'&x"2C8D",'1'&x"2C8E",'1'&x"2C8F",
+--'1'&x"2C90",'1'&x"2C91",'1'&x"2C92",'1'&x"2C93",'1'&x"2C94",'1'&x"2C95",'1'&x"2C96",'1'&x"2C97",'1'&x"2C98",'1'&x"2C99",'1'&x"2C9A",'1'&x"2C9B",'1'&x"2C9C",'1'&x"2C9D",'1'&x"2C9E",'1'&x"2C9F",
+--'1'&x"2CA0",'1'&x"2CA1",'1'&x"2CA2",'1'&x"2CA3",'1'&x"2CA4",'1'&x"2CA5",'1'&x"2CA6",'1'&x"2CA7",'1'&x"2CA8",'1'&x"2CA9",'1'&x"2CAA",'1'&x"2CAB",'1'&x"2CAC",'1'&x"2CAD",'1'&x"2CAE",'1'&x"2CAF",
+--'1'&x"2CB0",'1'&x"2CB1",'1'&x"2CB2",'1'&x"2CB3",'1'&x"2CB4",'1'&x"2CB5",'1'&x"2CB6",'1'&x"2CB7",'1'&x"2CB8",'1'&x"2CB9",'1'&x"2CBA",'1'&x"2CBB",'1'&x"2CBC",'1'&x"2CBD",'1'&x"2CBE",'1'&x"2CBF",
+--'1'&x"2CC0",'1'&x"2CC1",'1'&x"2CC2",'1'&x"2CC3",'1'&x"2CC4",'1'&x"2CC5",'1'&x"2CC6",'1'&x"2CC7",'1'&x"2CC8",'1'&x"2CC9",'1'&x"2CCA",'1'&x"2CCB",'1'&x"2CCC",'1'&x"2CCD",'1'&x"2CCE",'1'&x"2CCF",
+--'1'&x"2CD0",'1'&x"2CD1",'1'&x"2CD2",'1'&x"2CD3",'1'&x"2CD4",'1'&x"2CD5",'1'&x"2CD6",'1'&x"2CD7",'1'&x"2CD8",'1'&x"2CD9",'1'&x"2CDA",'1'&x"2CDB",'1'&x"2CDC",'1'&x"2CDD",'1'&x"2CDE",'1'&x"2CDF",
+--'1'&x"2CE0",'1'&x"2CE1",'1'&x"2CE2",'1'&x"2CE3",'1'&x"2CE4",'1'&x"2CE5",'1'&x"2CE6",'1'&x"2CE7",'1'&x"2CE8",'1'&x"2CE9",'1'&x"2CEA",'1'&x"2CEB",'1'&x"2CEC",'1'&x"2CED",'1'&x"2CEE",'1'&x"2CEF",
+--'1'&x"2CF0",'1'&x"2CF1",'1'&x"2CF2",'1'&x"2CF3",'1'&x"2CF4",'1'&x"2CF5",'1'&x"2CF6",'1'&x"2CF7",'1'&x"2CF8",'1'&x"2CF9",'1'&x"2CFA",'1'&x"2CFB",'1'&x"2CFC",'1'&x"2CFD",'1'&x"2CFE",'1'&x"2CFF",
+--'1'&x"2D00",'1'&x"2D01",'1'&x"2D02",'1'&x"2D03",'1'&x"2D04",'1'&x"2D05",'1'&x"2D06",'1'&x"2D07",'1'&x"2D08",'1'&x"2D09",'1'&x"2D0A",'1'&x"2D0B",'1'&x"2D0C",'1'&x"2D0D",'1'&x"2D0E",'1'&x"2D0F",
+--'1'&x"2D10",'1'&x"2D11",'1'&x"2D12",'1'&x"2D13",'1'&x"2D14",'1'&x"2D15",'1'&x"2D16",'1'&x"2D17",'1'&x"2D18",'1'&x"2D19",'1'&x"2D1A",'1'&x"2D1B",'1'&x"2D1C",'1'&x"2D1D",'1'&x"2D1E",'1'&x"2D1F",
+--'1'&x"2D20",'1'&x"2D21",'1'&x"2D22",'1'&x"2D23",'1'&x"2D24",'1'&x"2D25",'1'&x"2D26",'1'&x"2D27",'1'&x"2D28",'1'&x"2D29",'1'&x"2D2A",'1'&x"2D2B",'1'&x"2D2C",'1'&x"2D2D",'1'&x"2D2E",'1'&x"2D2F",
+--'1'&x"2D30",'1'&x"2D31",'1'&x"2D32",'1'&x"2D33",'1'&x"2D34",'1'&x"2D35",'1'&x"2D36",'1'&x"2D37",'1'&x"2D38",'1'&x"2D39",'1'&x"2D3A",'1'&x"2D3B",'1'&x"2D3C",'1'&x"2D3D",'1'&x"2D3E",'1'&x"2D3F",
+--'1'&x"2D40",'1'&x"2D41",'1'&x"2D42",'1'&x"2D43",'1'&x"2D44",'1'&x"2D45",'1'&x"2D46",'1'&x"2D47",'1'&x"2D48",'1'&x"2D49",'1'&x"2D4A",'1'&x"2D4B",'1'&x"2D4C",'1'&x"2D4D",'1'&x"2D4E",'1'&x"2D4F",
+--'1'&x"2D50",'1'&x"2D51",'1'&x"2D52",'1'&x"2D53",'1'&x"2D54",'1'&x"2D55",'1'&x"2D56",'1'&x"2D57",'1'&x"2D58",'1'&x"2D59",'1'&x"2D5A",'1'&x"2D5B",'1'&x"2D5C",'1'&x"2D5D",'1'&x"2D5E",'1'&x"2D5F",
+--'1'&x"2D60",'1'&x"2D61",'1'&x"2D62",'1'&x"2D63",'1'&x"2D64",'1'&x"2D65",'1'&x"2D66",'1'&x"2D67",'1'&x"2D68",'1'&x"2D69",'1'&x"2D6A",'1'&x"2D6B",'1'&x"2D6C",'1'&x"2D6D",'1'&x"2D6E",'1'&x"2D6F",
+--'1'&x"2D70",'1'&x"2D71",'1'&x"2D72",'1'&x"2D73",'1'&x"2D74",'1'&x"2D75",'1'&x"2D76",'1'&x"2D77",'1'&x"2D78",'1'&x"2D79",'1'&x"2D7A",'1'&x"2D7B",'1'&x"2D7C",'1'&x"2D7D",'1'&x"2D7E",'1'&x"2D7F",
+--'1'&x"2D80",'1'&x"2D81",'1'&x"2D82",'1'&x"2D83",'1'&x"2D84",'1'&x"2D85",'1'&x"2D86",'1'&x"2D87",'1'&x"2D88",'1'&x"2D89",'1'&x"2D8A",'1'&x"2D8B",'1'&x"2D8C",'1'&x"2D8D",'1'&x"2D8E",'1'&x"2D8F",
+--'1'&x"2D90",'1'&x"2D91",'1'&x"2D92",'1'&x"2D93",'1'&x"2D94",'1'&x"2D95",'1'&x"2D96",'1'&x"2D97",'1'&x"2D98",'1'&x"2D99",'1'&x"2D9A",'1'&x"2D9B",'1'&x"2D9C",'1'&x"2D9D",'1'&x"2D9E",'1'&x"2D9F",
+--'1'&x"2DA0",'1'&x"2DA1",'1'&x"2DA2",'1'&x"2DA3",'1'&x"2DA4",'1'&x"2DA5",'1'&x"2DA6",'1'&x"2DA7",'1'&x"2DA8",'1'&x"2DA9",'1'&x"2DAA",'1'&x"2DAB",'1'&x"2DAC",'1'&x"2DAD",'1'&x"2DAE",'1'&x"2DAF",
+--'1'&x"2DB0",'1'&x"2DB1",'1'&x"2DB2",'1'&x"2DB3",'1'&x"2DB4",'1'&x"2DB5",'1'&x"2DB6",'1'&x"2DB7",'1'&x"2DB8",'1'&x"2DB9",'1'&x"2DBA",'1'&x"2DBB",'1'&x"2DBC",'1'&x"2DBD",'1'&x"2DBE",'1'&x"2DBF",
+--'1'&x"2DC0",'1'&x"2DC1",'1'&x"2DC2",'1'&x"2DC3",'1'&x"2DC4",'1'&x"2DC5",'1'&x"2DC6",'1'&x"2DC7",'1'&x"2DC8",'1'&x"2DC9",'1'&x"2DCA",'1'&x"2DCB",'1'&x"2DCC",'1'&x"2DCD",'1'&x"2DCE",'1'&x"2DCF",
+--'1'&x"2DD0",'1'&x"2DD1",'1'&x"2DD2",'1'&x"2DD3",'1'&x"2DD4",'1'&x"2DD5",'1'&x"2DD6",'1'&x"2DD7",'1'&x"2DD8",'1'&x"2DD9",'1'&x"2DDA",'1'&x"2DDB",'1'&x"2DDC",'1'&x"2DDD",'1'&x"2DDE",'1'&x"2DDF",
+--'1'&x"2DE0",'1'&x"2DE1",'1'&x"2DE2",'1'&x"2DE3",'1'&x"2DE4",'1'&x"2DE5",'1'&x"2DE6",'1'&x"2DE7",'1'&x"2DE8",'1'&x"2DE9",'1'&x"2DEA",'1'&x"2DEB",'1'&x"2DEC",'1'&x"2DED",'1'&x"2DEE",'1'&x"2DEF",
+--'1'&x"2DF0",'1'&x"2DF1",'1'&x"2DF2",'1'&x"2DF3",'1'&x"2DF4",'1'&x"2DF5",'1'&x"2DF6",'1'&x"2DF7",'1'&x"2DF8",'1'&x"2DF9",'1'&x"2DFA",'1'&x"2DFB",'1'&x"2DFC",'1'&x"2DFD",'1'&x"2DFE",'1'&x"2DFF",
+--'1'&x"2E00",'1'&x"2E01",'1'&x"2E02",'1'&x"2E03",'1'&x"2E04",'1'&x"2E05",'1'&x"2E06",'1'&x"2E07",'1'&x"2E08",'1'&x"2E09",'1'&x"2E0A",'1'&x"2E0B",'1'&x"2E0C",'1'&x"2E0D",'1'&x"2E0E",'1'&x"2E0F",
+--'1'&x"2E10",'1'&x"2E11",'1'&x"2E12",'1'&x"2E13",'1'&x"2E14",'1'&x"2E15",'1'&x"2E16",'1'&x"2E17",'1'&x"2E18",'1'&x"2E19",'1'&x"2E1A",'1'&x"2E1B",'1'&x"2E1C",'1'&x"2E1D",'1'&x"2E1E",'1'&x"2E1F",
+--'1'&x"2E20",'1'&x"2E21",'1'&x"2E22",'1'&x"2E23",'1'&x"2E24",'1'&x"2E25",'1'&x"2E26",'1'&x"2E27",'1'&x"2E28",'1'&x"2E29",'1'&x"2E2A",'1'&x"2E2B",'1'&x"2E2C",'1'&x"2E2D",'1'&x"2E2E",'1'&x"2E2F",
+--'1'&x"2E30",'1'&x"2E31",'1'&x"2E32",'1'&x"2E33",'1'&x"2E34",'1'&x"2E35",'1'&x"2E36",'1'&x"2E37",'1'&x"2E38",'1'&x"2E39",'1'&x"2E3A",'1'&x"2E3B",'1'&x"2E3C",'1'&x"2E3D",'1'&x"2E3E",'1'&x"2E3F",
+--'1'&x"2E40",'1'&x"2E41",'1'&x"2E42",'1'&x"2E43",'1'&x"2E44",'1'&x"2E45",'1'&x"2E46",'1'&x"2E47",'1'&x"2E48",'1'&x"2E49",'1'&x"2E4A",'1'&x"2E4B",'1'&x"2E4C",'1'&x"2E4D",'1'&x"2E4E",'1'&x"2E4F",
+--'1'&x"2E50",'1'&x"2E51",'1'&x"2E52",'1'&x"2E53",'1'&x"2E54",'1'&x"2E55",'1'&x"2E56",'1'&x"2E57",'1'&x"2E58",'1'&x"2E59",'1'&x"2E5A",'1'&x"2E5B",'1'&x"2E5C",'1'&x"2E5D",'1'&x"2E5E",'1'&x"2E5F",
+--'1'&x"2E60",'1'&x"2E61",'1'&x"2E62",'1'&x"2E63",'1'&x"2E64",'1'&x"2E65",'1'&x"2E66",'1'&x"2E67",'1'&x"2E68",'1'&x"2E69",'1'&x"2E6A",'1'&x"2E6B",'1'&x"2E6C",'1'&x"2E6D",'1'&x"2E6E",'1'&x"2E6F",
+--'1'&x"2E70",'1'&x"2E71",'1'&x"2E72",'1'&x"2E73",'1'&x"2E74",'1'&x"2E75",'1'&x"2E76",'1'&x"2E77",'1'&x"2E78",'1'&x"2E79",'1'&x"2E7A",'1'&x"2E7B",'1'&x"2E7C",'1'&x"2E7D",'1'&x"2E7E",'1'&x"2E7F",
+--'1'&x"2E80",'1'&x"2E81",'1'&x"2E82",'1'&x"2E83",'1'&x"2E84",'1'&x"2E85",'1'&x"2E86",'1'&x"2E87",'1'&x"2E88",'1'&x"2E89",'1'&x"2E8A",'1'&x"2E8B",'1'&x"2E8C",'1'&x"2E8D",'1'&x"2E8E",'1'&x"2E8F",
+--'1'&x"2E90",'1'&x"2E91",'1'&x"2E92",'1'&x"2E93",'1'&x"2E94",'1'&x"2E95",'1'&x"2E96",'1'&x"2E97",'1'&x"2E98",'1'&x"2E99",'1'&x"2E9A",'1'&x"2E9B",'1'&x"2E9C",'1'&x"2E9D",'1'&x"2E9E",'1'&x"2E9F",
+--'1'&x"2EA0",'1'&x"2EA1",'1'&x"2EA2",'1'&x"2EA3",'1'&x"2EA4",'1'&x"2EA5",'1'&x"2EA6",'1'&x"2EA7",'1'&x"2EA8",'1'&x"2EA9",'1'&x"2EAA",'1'&x"2EAB",'1'&x"2EAC",'1'&x"2EAD",'1'&x"2EAE",'1'&x"2EAF",
+--'1'&x"2EB0",'1'&x"2EB1",'1'&x"2EB2",'1'&x"2EB3",'1'&x"2EB4",'1'&x"2EB5",'1'&x"2EB6",'1'&x"2EB7",'1'&x"2EB8",'1'&x"2EB9",'1'&x"2EBA",'1'&x"2EBB",'1'&x"2EBC",'1'&x"2EBD",'1'&x"2EBE",'1'&x"2EBF",
+--'1'&x"2EC0",'1'&x"2EC1",'1'&x"2EC2",'1'&x"2EC3",'1'&x"2EC4",'1'&x"2EC5",'1'&x"2EC6",'1'&x"2EC7",'1'&x"2EC8",'1'&x"2EC9",'1'&x"2ECA",'1'&x"2ECB",'1'&x"2ECC",'1'&x"2ECD",'1'&x"2ECE",'1'&x"2ECF",
+--'1'&x"2ED0",'1'&x"2ED1",'1'&x"2ED2",'1'&x"2ED3",'1'&x"2ED4",'1'&x"2ED5",'1'&x"2ED6",'1'&x"2ED7",'1'&x"2ED8",'1'&x"2ED9",'1'&x"2EDA",'1'&x"2EDB",'1'&x"2EDC",'1'&x"2EDD",'1'&x"2EDE",'1'&x"2EDF",
+--'1'&x"2EE0",'1'&x"2EE1",'1'&x"2EE2",'1'&x"2EE3",'1'&x"2EE4",'1'&x"2EE5",'1'&x"2EE6",'1'&x"2EE7",'1'&x"2EE8",'1'&x"2EE9",'1'&x"2EEA",'1'&x"2EEB",'1'&x"2EEC",'1'&x"2EED",'1'&x"2EEE",'1'&x"2EEF",
+--'1'&x"2EF0",'1'&x"2EF1",'1'&x"2EF2",'1'&x"2EF3",'1'&x"2EF4",'1'&x"2EF5",'1'&x"2EF6",'1'&x"2EF7",'1'&x"2EF8",'1'&x"2EF9",'1'&x"2EFA",'1'&x"2EFB",'1'&x"2EFC",'1'&x"2EFD",'1'&x"2EFE",'1'&x"2EFF",
+--'1'&x"2F00",'1'&x"2F01",'1'&x"2F02",'1'&x"2F03",'1'&x"2F04",'1'&x"2F05",'1'&x"2F06",'1'&x"2F07",'1'&x"2F08",'1'&x"2F09",'1'&x"2F0A",'1'&x"2F0B",'1'&x"2F0C",'1'&x"2F0D",'1'&x"2F0E",'1'&x"2F0F",
+--'1'&x"2F10",'1'&x"2F11",'1'&x"2F12",'1'&x"2F13",'1'&x"2F14",'1'&x"2F15",'1'&x"2F16",'1'&x"2F17",'1'&x"2F18",'1'&x"2F19",'1'&x"2F1A",'1'&x"2F1B",'1'&x"2F1C",'1'&x"2F1D",'1'&x"2F1E",'1'&x"2F1F",
+--'1'&x"2F20",'1'&x"2F21",'1'&x"2F22",'1'&x"2F23",'1'&x"2F24",'1'&x"2F25",'1'&x"2F26",'1'&x"2F27",'1'&x"2F28",'1'&x"2F29",'1'&x"2F2A",'1'&x"2F2B",'1'&x"2F2C",'1'&x"2F2D",'1'&x"2F2E",'1'&x"2F2F",
+--'1'&x"2F30",'1'&x"2F31",'1'&x"2F32",'1'&x"2F33",'1'&x"2F34",'1'&x"2F35",'1'&x"2F36",'1'&x"2F37",'1'&x"2F38",'1'&x"2F39",'1'&x"2F3A",'1'&x"2F3B",'1'&x"2F3C",'1'&x"2F3D",'1'&x"2F3E",'1'&x"2F3F",
+--'1'&x"2F40",'1'&x"2F41",'1'&x"2F42",'1'&x"2F43",'1'&x"2F44",'1'&x"2F45",'1'&x"2F46",'1'&x"2F47",'1'&x"2F48",'1'&x"2F49",'1'&x"2F4A",'1'&x"2F4B",'1'&x"2F4C",'1'&x"2F4D",'1'&x"2F4E",'1'&x"2F4F",
+--'1'&x"2F50",'1'&x"2F51",'1'&x"2F52",'1'&x"2F53",'1'&x"2F54",'1'&x"2F55",'1'&x"2F56",'1'&x"2F57",'1'&x"2F58",'1'&x"2F59",'1'&x"2F5A",'1'&x"2F5B",'1'&x"2F5C",'1'&x"2F5D",'1'&x"2F5E",'1'&x"2F5F",
+--'1'&x"2F60",'1'&x"2F61",'1'&x"2F62",'1'&x"2F63",'1'&x"2F64",'1'&x"2F65",'1'&x"2F66",'1'&x"2F67",'1'&x"2F68",'1'&x"2F69",'1'&x"2F6A",'1'&x"2F6B",'1'&x"2F6C",'1'&x"2F6D",'1'&x"2F6E",'1'&x"2F6F",
+--'1'&x"2F70",'1'&x"2F71",'1'&x"2F72",'1'&x"2F73",'1'&x"2F74",'1'&x"2F75",'1'&x"2F76",'1'&x"2F77",'1'&x"2F78",'1'&x"2F79",'1'&x"2F7A",'1'&x"2F7B",'1'&x"2F7C",'1'&x"2F7D",'1'&x"2F7E",'1'&x"2F7F",
+--'1'&x"2F80",'1'&x"2F81",'1'&x"2F82",'1'&x"2F83",'1'&x"2F84",'1'&x"2F85",'1'&x"2F86",'1'&x"2F87",'1'&x"2F88",'1'&x"2F89",'1'&x"2F8A",'1'&x"2F8B",'1'&x"2F8C",'1'&x"2F8D",'1'&x"2F8E",'1'&x"2F8F",
+--'1'&x"2F90",'1'&x"2F91",'1'&x"2F92",'1'&x"2F93",'1'&x"2F94",'1'&x"2F95",'1'&x"2F96",'1'&x"2F97",'1'&x"2F98",'1'&x"2F99",'1'&x"2F9A",'1'&x"2F9B",'1'&x"2F9C",'1'&x"2F9D",'1'&x"2F9E",'1'&x"2F9F",
+--'1'&x"2FA0",'1'&x"2FA1",'1'&x"2FA2",'1'&x"2FA3",'1'&x"2FA4",'1'&x"2FA5",'1'&x"2FA6",'1'&x"2FA7",'1'&x"2FA8",'1'&x"2FA9",'1'&x"2FAA",'1'&x"2FAB",'1'&x"2FAC",'1'&x"2FAD",'1'&x"2FAE",'1'&x"2FAF",
+--'1'&x"2FB0",'1'&x"2FB1",'1'&x"2FB2",'1'&x"2FB3",'1'&x"2FB4",'1'&x"2FB5",'1'&x"2FB6",'1'&x"2FB7",'1'&x"2FB8",'1'&x"2FB9",'1'&x"2FBA",'1'&x"2FBB",'1'&x"2FBC",'1'&x"2FBD",'1'&x"2FBE",'1'&x"2FBF",
+--'1'&x"2FC0",'1'&x"2FC1",'1'&x"2FC2",'1'&x"2FC3",'1'&x"2FC4",'1'&x"2FC5",'1'&x"2FC6",'1'&x"2FC7",'1'&x"2FC8",'1'&x"2FC9",'1'&x"2FCA",'1'&x"2FCB",'1'&x"2FCC",'1'&x"2FCD",'1'&x"2FCE",'1'&x"2FCF",
+--'1'&x"2FD0",'1'&x"2FD1",'1'&x"2FD2",'1'&x"2FD3",'1'&x"2FD4",'1'&x"2FD5",'1'&x"2FD6",'1'&x"2FD7",'1'&x"2FD8",'1'&x"2FD9",'1'&x"2FDA",'1'&x"2FDB",'1'&x"2FDC",'1'&x"2FDD",'1'&x"2FDE",'1'&x"2FDF",
+--'1'&x"2FE0",'1'&x"2FE1",'1'&x"2FE2",'1'&x"2FE3",'1'&x"2FE4",'1'&x"2FE5",'1'&x"2FE6",'1'&x"2FE7",'1'&x"2FE8",'1'&x"2FE9",'1'&x"2FEA",'1'&x"2FEB",'1'&x"2FEC",'1'&x"2FED",'1'&x"2FEE",'1'&x"2FEF",
+--'1'&x"2FF0",'1'&x"2FF1",'1'&x"2FF2",'1'&x"2FF3",'1'&x"2FF4",'1'&x"2FF5",'1'&x"2FF6",'1'&x"2FF7",'1'&x"2FF8",'1'&x"2FF9",'1'&x"2FFA",'1'&x"2FFB",'1'&x"2FFC",'1'&x"2FFD",'1'&x"2FFE",'1'&x"2FFF",
+--'1'&x"3000",'1'&x"3001",'1'&x"3002",'1'&x"3003",'1'&x"3004",'1'&x"3005",'1'&x"3006",'1'&x"3007",'1'&x"3008",'1'&x"3009",'1'&x"300A",'1'&x"300B",'1'&x"300C",'1'&x"300D",'1'&x"300E",'1'&x"300F",
+--'1'&x"3010",'1'&x"3011",'1'&x"3012",'1'&x"3013",'1'&x"3014",'1'&x"3015",'1'&x"3016",'1'&x"3017",'1'&x"3018",'1'&x"3019",'1'&x"301A",'1'&x"301B",'1'&x"301C",'1'&x"301D",'1'&x"301E",'1'&x"301F",
+--'1'&x"3020",'1'&x"3021",'1'&x"3022",'1'&x"3023",'1'&x"3024",'1'&x"3025",'1'&x"3026",'1'&x"3027",'1'&x"3028",'1'&x"3029",'1'&x"302A",'1'&x"302B",'1'&x"302C",'1'&x"302D",'1'&x"302E",'1'&x"302F",
+--'1'&x"3030",'1'&x"3031",'1'&x"3032",'1'&x"3033",'1'&x"3034",'1'&x"3035",'1'&x"3036",'1'&x"3037",'1'&x"3038",'1'&x"3039",'1'&x"303A",'1'&x"303B",'1'&x"303C",'1'&x"303D",'1'&x"303E",'1'&x"303F",
+--'1'&x"3040",'1'&x"3041",'1'&x"3042",'1'&x"3043",'1'&x"3044",'1'&x"3045",'1'&x"3046",'1'&x"3047",'1'&x"3048",'1'&x"3049",'1'&x"304A",'1'&x"304B",'1'&x"304C",'1'&x"304D",'1'&x"304E",'1'&x"304F",
+--'1'&x"3050",'1'&x"3051",'1'&x"3052",'1'&x"3053",'1'&x"3054",'1'&x"3055",'1'&x"3056",'1'&x"3057",'1'&x"3058",'1'&x"3059",'1'&x"305A",'1'&x"305B",'1'&x"305C",'1'&x"305D",'1'&x"305E",'1'&x"305F",
+--'1'&x"3060",'1'&x"3061",'1'&x"3062",'1'&x"3063",'1'&x"3064",'1'&x"3065",'1'&x"3066",'1'&x"3067",'1'&x"3068",'1'&x"3069",'1'&x"306A",'1'&x"306B",'1'&x"306C",'1'&x"306D",'1'&x"306E",'1'&x"306F",
+--'1'&x"3070",'1'&x"3071",'1'&x"3072",'1'&x"3073",'1'&x"3074",'1'&x"3075",'1'&x"3076",'1'&x"3077",'1'&x"3078",'1'&x"3079",'1'&x"307A",'1'&x"307B",'1'&x"307C",'1'&x"307D",'1'&x"307E",'1'&x"307F",
+--'1'&x"3080",'1'&x"3081",'1'&x"3082",'1'&x"3083",'1'&x"3084",'1'&x"3085",'1'&x"3086",'1'&x"3087",'1'&x"3088",'1'&x"3089",'1'&x"308A",'1'&x"308B",'1'&x"308C",'1'&x"308D",'1'&x"308E",'1'&x"308F",
+--'1'&x"3090",'1'&x"3091",'1'&x"3092",'1'&x"3093",'1'&x"3094",'1'&x"3095",'1'&x"3096",'1'&x"3097",'1'&x"3098",'1'&x"3099",'1'&x"309A",'1'&x"309B",'1'&x"309C",'1'&x"309D",'1'&x"309E",'1'&x"309F",
+--'1'&x"30A0",'1'&x"30A1",'1'&x"30A2",'1'&x"30A3",'1'&x"30A4",'1'&x"30A5",'1'&x"30A6",'1'&x"30A7",'1'&x"30A8",'1'&x"30A9",'1'&x"30AA",'1'&x"30AB",'1'&x"30AC",'1'&x"30AD",'1'&x"30AE",'1'&x"30AF",
+--'1'&x"30B0",'1'&x"30B1",'1'&x"30B2",'1'&x"30B3",'1'&x"30B4",'1'&x"30B5",'1'&x"30B6",'1'&x"30B7",'1'&x"30B8",'1'&x"30B9",'1'&x"30BA",'1'&x"30BB",'1'&x"30BC",'1'&x"30BD",'1'&x"30BE",'1'&x"30BF",
+--'1'&x"30C0",'1'&x"30C1",'1'&x"30C2",'1'&x"30C3",'1'&x"30C4",'1'&x"30C5",'1'&x"30C6",'1'&x"30C7",'1'&x"30C8",'1'&x"30C9",'1'&x"30CA",'1'&x"30CB",'1'&x"30CC",'1'&x"30CD",'1'&x"30CE",'1'&x"30CF",
+--'1'&x"30D0",'1'&x"30D1",'1'&x"30D2",'1'&x"30D3",'1'&x"30D4",'1'&x"30D5",'1'&x"30D6",'1'&x"30D7",'1'&x"30D8",'1'&x"30D9",'1'&x"30DA",'1'&x"30DB",'1'&x"30DC",'1'&x"30DD",'1'&x"30DE",'1'&x"30DF",
+--'1'&x"30E0",'1'&x"30E1",'1'&x"30E2",'1'&x"30E3",'1'&x"30E4",'1'&x"30E5",'1'&x"30E6",'1'&x"30E7",'1'&x"30E8",'1'&x"30E9",'1'&x"30EA",'1'&x"30EB",'1'&x"30EC",'1'&x"30ED",'1'&x"30EE",'1'&x"30EF",
+--'1'&x"30F0",'1'&x"30F1",'1'&x"30F2",'1'&x"30F3",'1'&x"30F4",'1'&x"30F5",'1'&x"30F6",'1'&x"30F7",'1'&x"30F8",'1'&x"30F9",'1'&x"30FA",'1'&x"30FB",'1'&x"30FC",'1'&x"30FD",'1'&x"30FE",'1'&x"30FF",
+--'1'&x"3100",'1'&x"3101",'1'&x"3102",'1'&x"3103",'1'&x"3104",'1'&x"3105",'1'&x"3106",'1'&x"3107",'1'&x"3108",'1'&x"3109",'1'&x"310A",'1'&x"310B",'1'&x"310C",'1'&x"310D",'1'&x"310E",'1'&x"310F",
+--'1'&x"3110",'1'&x"3111",'1'&x"3112",'1'&x"3113",'1'&x"3114",'1'&x"3115",'1'&x"3116",'1'&x"3117",'1'&x"3118",'1'&x"3119",'1'&x"311A",'1'&x"311B",'1'&x"311C",'1'&x"311D",'1'&x"311E",'1'&x"311F",
+--'1'&x"3120",'1'&x"3121",'1'&x"3122",'1'&x"3123",'1'&x"3124",'1'&x"3125",'1'&x"3126",'1'&x"3127",'1'&x"3128",'1'&x"3129",'1'&x"312A",'1'&x"312B",'1'&x"312C",'1'&x"312D",'1'&x"312E",'1'&x"312F",
+--'1'&x"3130",'1'&x"3131",'1'&x"3132",'1'&x"3133",'1'&x"3134",'1'&x"3135",'1'&x"3136",'1'&x"3137",'1'&x"3138",'1'&x"3139",'1'&x"313A",'1'&x"313B",'1'&x"313C",'1'&x"313D",'1'&x"313E",'1'&x"313F",
+--'1'&x"3140",'1'&x"3141",'1'&x"3142",'1'&x"3143",'1'&x"3144",'1'&x"3145",'1'&x"3146",'1'&x"3147",'1'&x"3148",'1'&x"3149",'1'&x"314A",'1'&x"314B",'1'&x"314C",'1'&x"314D",'1'&x"314E",'1'&x"314F",
+--'1'&x"3150",'1'&x"3151",'1'&x"3152",'1'&x"3153",'1'&x"3154",'1'&x"3155",'1'&x"3156",'1'&x"3157",'1'&x"3158",'1'&x"3159",'1'&x"315A",'1'&x"315B",'1'&x"315C",'1'&x"315D",'1'&x"315E",'1'&x"315F",
+--'1'&x"3160",'1'&x"3161",'1'&x"3162",'1'&x"3163",'1'&x"3164",'1'&x"3165",'1'&x"3166",'1'&x"3167",'1'&x"3168",'1'&x"3169",'1'&x"316A",'1'&x"316B",'1'&x"316C",'1'&x"316D",'1'&x"316E",'1'&x"316F",
+--'1'&x"3170",'1'&x"3171",'1'&x"3172",'1'&x"3173",'1'&x"3174",'1'&x"3175",'1'&x"3176",'1'&x"3177",'1'&x"3178",'1'&x"3179",'1'&x"317A",'1'&x"317B",'1'&x"317C",'1'&x"317D",'1'&x"317E",'1'&x"317F",
+--'1'&x"3180",'1'&x"3181",'1'&x"3182",'1'&x"3183",'1'&x"3184",'1'&x"3185",'1'&x"3186",'1'&x"3187",'1'&x"3188",'1'&x"3189",'1'&x"318A",'1'&x"318B",'1'&x"318C",'1'&x"318D",'1'&x"318E",'1'&x"318F",
+--'1'&x"3190",'1'&x"3191",'1'&x"3192",'1'&x"3193",'1'&x"3194",'1'&x"3195",'1'&x"3196",'1'&x"3197",'1'&x"3198",'1'&x"3199",'1'&x"319A",'1'&x"319B",'1'&x"319C",'1'&x"319D",'1'&x"319E",'1'&x"319F",
+--'1'&x"31A0",'1'&x"31A1",'1'&x"31A2",'1'&x"31A3",'1'&x"31A4",'1'&x"31A5",'1'&x"31A6",'1'&x"31A7",'1'&x"31A8",'1'&x"31A9",'1'&x"31AA",'1'&x"31AB",'1'&x"31AC",'1'&x"31AD",'1'&x"31AE",'1'&x"31AF",
+--'1'&x"31B0",'1'&x"31B1",'1'&x"31B2",'1'&x"31B3",'1'&x"31B4",'1'&x"31B5",'1'&x"31B6",'1'&x"31B7",'1'&x"31B8",'1'&x"31B9",'1'&x"31BA",'1'&x"31BB",'1'&x"31BC",'1'&x"31BD",'1'&x"31BE",'1'&x"31BF",
+--'1'&x"31C0",'1'&x"31C1",'1'&x"31C2",'1'&x"31C3",'1'&x"31C4",'1'&x"31C5",'1'&x"31C6",'1'&x"31C7",'1'&x"31C8",'1'&x"31C9",'1'&x"31CA",'1'&x"31CB",'1'&x"31CC",'1'&x"31CD",'1'&x"31CE",'1'&x"31CF",
+--'1'&x"31D0",'1'&x"31D1",'1'&x"31D2",'1'&x"31D3",'1'&x"31D4",'1'&x"31D5",'1'&x"31D6",'1'&x"31D7",'1'&x"31D8",'1'&x"31D9",'1'&x"31DA",'1'&x"31DB",'1'&x"31DC",'1'&x"31DD",'1'&x"31DE",'1'&x"31DF",
+--'1'&x"31E0",'1'&x"31E1",'1'&x"31E2",'1'&x"31E3",'1'&x"31E4",'1'&x"31E5",'1'&x"31E6",'1'&x"31E7",'1'&x"31E8",'1'&x"31E9",'1'&x"31EA",'1'&x"31EB",'1'&x"31EC",'1'&x"31ED",'1'&x"31EE",'1'&x"31EF",
+--'1'&x"31F0",'1'&x"31F1",'1'&x"31F2",'1'&x"31F3",'1'&x"31F4",'1'&x"31F5",'1'&x"31F6",'1'&x"31F7",'1'&x"31F8",'1'&x"31F9",'1'&x"31FA",'1'&x"31FB",'1'&x"31FC",'1'&x"31FD",'1'&x"31FE",'1'&x"31FF",
+--'1'&x"3200",'1'&x"3201",'1'&x"3202",'1'&x"3203",'1'&x"3204",'1'&x"3205",'1'&x"3206",'1'&x"3207",'1'&x"3208",'1'&x"3209",'1'&x"320A",'1'&x"320B",'1'&x"320C",'1'&x"320D",'1'&x"320E",'1'&x"320F",
+--'1'&x"3210",'1'&x"3211",'1'&x"3212",'1'&x"3213",'1'&x"3214",'1'&x"3215",'1'&x"3216",'1'&x"3217",'1'&x"3218",'1'&x"3219",'1'&x"321A",'1'&x"321B",'1'&x"321C",'1'&x"321D",'1'&x"321E",'1'&x"321F",
+--'1'&x"3220",'1'&x"3221",'1'&x"3222",'1'&x"3223",'1'&x"3224",'1'&x"3225",'1'&x"3226",'1'&x"3227",'1'&x"3228",'1'&x"3229",'1'&x"322A",'1'&x"322B",'1'&x"322C",'1'&x"322D",'1'&x"322E",'1'&x"322F",
+--'1'&x"3230",'1'&x"3231",'1'&x"3232",'1'&x"3233",'1'&x"3234",'1'&x"3235",'1'&x"3236",'1'&x"3237",'1'&x"3238",'1'&x"3239",'1'&x"323A",'1'&x"323B",'1'&x"323C",'1'&x"323D",'1'&x"323E",'1'&x"323F",
+--'1'&x"3240",'1'&x"3241",'1'&x"3242",'1'&x"3243",'1'&x"3244",'1'&x"3245",'1'&x"3246",'1'&x"3247",'1'&x"3248",'1'&x"3249",'1'&x"324A",'1'&x"324B",'1'&x"324C",'1'&x"324D",'1'&x"324E",'1'&x"324F",
+--'1'&x"3250",'1'&x"3251",'1'&x"3252",'1'&x"3253",'1'&x"3254",'1'&x"3255",'1'&x"3256",'1'&x"3257",'1'&x"3258",'1'&x"3259",'1'&x"325A",'1'&x"325B",'1'&x"325C",'1'&x"325D",'1'&x"325E",'1'&x"325F",
+--'1'&x"3260",'1'&x"3261",'1'&x"3262",'1'&x"3263",'1'&x"3264",'1'&x"3265",'1'&x"3266",'1'&x"3267",'1'&x"3268",'1'&x"3269",'1'&x"326A",'1'&x"326B",'1'&x"326C",'1'&x"326D",'1'&x"326E",'1'&x"326F",
+--'1'&x"3270",'1'&x"3271",'1'&x"3272",'1'&x"3273",'1'&x"3274",'1'&x"3275",'1'&x"3276",'1'&x"3277",'1'&x"3278",'1'&x"3279",'1'&x"327A",'1'&x"327B",'1'&x"327C",'1'&x"327D",'1'&x"327E",'1'&x"327F",
+--'1'&x"3280",'1'&x"3281",'1'&x"3282",'1'&x"3283",'1'&x"3284",'1'&x"3285",'1'&x"3286",'1'&x"3287",'1'&x"3288",'1'&x"3289",'1'&x"328A",'1'&x"328B",'1'&x"328C",'1'&x"328D",'1'&x"328E",'1'&x"328F",
+--'1'&x"3290",'1'&x"3291",'1'&x"3292",'1'&x"3293",'1'&x"3294",'1'&x"3295",'1'&x"3296",'1'&x"3297",'1'&x"3298",'1'&x"3299",'1'&x"329A",'1'&x"329B",'1'&x"329C",'1'&x"329D",'1'&x"329E",'1'&x"329F",
+--'1'&x"32A0",'1'&x"32A1",'1'&x"32A2",'1'&x"32A3",'1'&x"32A4",'1'&x"32A5",'1'&x"32A6",'1'&x"32A7",'1'&x"32A8",'1'&x"32A9",'1'&x"32AA",'1'&x"32AB",'1'&x"32AC",'1'&x"32AD",'1'&x"32AE",'1'&x"32AF",
+--'1'&x"32B0",'1'&x"32B1",'1'&x"32B2",'1'&x"32B3",'1'&x"32B4",'1'&x"32B5",'1'&x"32B6",'1'&x"32B7",'1'&x"32B8",'1'&x"32B9",'1'&x"32BA",'1'&x"32BB",'1'&x"32BC",'1'&x"32BD",'1'&x"32BE",'1'&x"32BF",
+--'1'&x"32C0",'1'&x"32C1",'1'&x"32C2",'1'&x"32C3",'1'&x"32C4",'1'&x"32C5",'1'&x"32C6",'1'&x"32C7",'1'&x"32C8",'1'&x"32C9",'1'&x"32CA",'1'&x"32CB",'1'&x"32CC",'1'&x"32CD",'1'&x"32CE",'1'&x"32CF",
+--'1'&x"32D0",'1'&x"32D1",'1'&x"32D2",'1'&x"32D3",'1'&x"32D4",'1'&x"32D5",'1'&x"32D6",'1'&x"32D7",'1'&x"32D8",'1'&x"32D9",'1'&x"32DA",'1'&x"32DB",'1'&x"32DC",'1'&x"32DD",'1'&x"32DE",'1'&x"32DF",
+--'1'&x"32E0",'1'&x"32E1",'1'&x"32E2",'1'&x"32E3",'1'&x"32E4",'1'&x"32E5",'1'&x"32E6",'1'&x"32E7",'1'&x"32E8",'1'&x"32E9",'1'&x"32EA",'1'&x"32EB",'1'&x"32EC",'1'&x"32ED",'1'&x"32EE",'1'&x"32EF",
+--'1'&x"32F0",'1'&x"32F1",'1'&x"32F2",'1'&x"32F3",'1'&x"32F4",'1'&x"32F5",'1'&x"32F6",'1'&x"32F7",'1'&x"32F8",'1'&x"32F9",'1'&x"32FA",'1'&x"32FB",'1'&x"32FC",'1'&x"32FD",'1'&x"32FE",'1'&x"32FF",
+--'1'&x"3300",'1'&x"3301",'1'&x"3302",'1'&x"3303",'1'&x"3304",'1'&x"3305",'1'&x"3306",'1'&x"3307",'1'&x"3308",'1'&x"3309",'1'&x"330A",'1'&x"330B",'1'&x"330C",'1'&x"330D",'1'&x"330E",'1'&x"330F",
+--'1'&x"3310",'1'&x"3311",'1'&x"3312",'1'&x"3313",'1'&x"3314",'1'&x"3315",'1'&x"3316",'1'&x"3317",'1'&x"3318",'1'&x"3319",'1'&x"331A",'1'&x"331B",'1'&x"331C",'1'&x"331D",'1'&x"331E",'1'&x"331F",
+--'1'&x"3320",'1'&x"3321",'1'&x"3322",'1'&x"3323",'1'&x"3324",'1'&x"3325",'1'&x"3326",'1'&x"3327",'1'&x"3328",'1'&x"3329",'1'&x"332A",'1'&x"332B",'1'&x"332C",'1'&x"332D",'1'&x"332E",'1'&x"332F",
+--'1'&x"3330",'1'&x"3331",'1'&x"3332",'1'&x"3333",'1'&x"3334",'1'&x"3335",'1'&x"3336",'1'&x"3337",'1'&x"3338",'1'&x"3339",'1'&x"333A",'1'&x"333B",'1'&x"333C",'1'&x"333D",'1'&x"333E",'1'&x"333F",
+--'1'&x"3340",'1'&x"3341",'1'&x"3342",'1'&x"3343",'1'&x"3344",'1'&x"3345",'1'&x"3346",'1'&x"3347",'1'&x"3348",'1'&x"3349",'1'&x"334A",'1'&x"334B",'1'&x"334C",'1'&x"334D",'1'&x"334E",'1'&x"334F",
+--'1'&x"3350",'1'&x"3351",'1'&x"3352",'1'&x"3353",'1'&x"3354",'1'&x"3355",'1'&x"3356",'1'&x"3357",'1'&x"3358",'1'&x"3359",'1'&x"335A",'1'&x"335B",'1'&x"335C",'1'&x"335D",'1'&x"335E",'1'&x"335F",
+--'1'&x"3360",'1'&x"3361",'1'&x"3362",'1'&x"3363",'1'&x"3364",'1'&x"3365",'1'&x"3366",'1'&x"3367",'1'&x"3368",'1'&x"3369",'1'&x"336A",'1'&x"336B",'1'&x"336C",'1'&x"336D",'1'&x"336E",'1'&x"336F",
+--'1'&x"3370",'1'&x"3371",'1'&x"3372",'1'&x"3373",'1'&x"3374",'1'&x"3375",'1'&x"3376",'1'&x"3377",'1'&x"3378",'1'&x"3379",'1'&x"337A",'1'&x"337B",'1'&x"337C",'1'&x"337D",'1'&x"337E",'1'&x"337F",
+--'1'&x"3380",'1'&x"3381",'1'&x"3382",'1'&x"3383",'1'&x"3384",'1'&x"3385",'1'&x"3386",'1'&x"3387",'1'&x"3388",'1'&x"3389",'1'&x"338A",'1'&x"338B",'1'&x"338C",'1'&x"338D",'1'&x"338E",'1'&x"338F",
+--'1'&x"3390",'1'&x"3391",'1'&x"3392",'1'&x"3393",'1'&x"3394",'1'&x"3395",'1'&x"3396",'1'&x"3397",'1'&x"3398",'1'&x"3399",'1'&x"339A",'1'&x"339B",'1'&x"339C",'1'&x"339D",'1'&x"339E",'1'&x"339F",
+--'1'&x"33A0",'1'&x"33A1",'1'&x"33A2",'1'&x"33A3",'1'&x"33A4",'1'&x"33A5",'1'&x"33A6",'1'&x"33A7",'1'&x"33A8",'1'&x"33A9",'1'&x"33AA",'1'&x"33AB",'1'&x"33AC",'1'&x"33AD",'1'&x"33AE",'1'&x"33AF",
+--'1'&x"33B0",'1'&x"33B1",'1'&x"33B2",'1'&x"33B3",'1'&x"33B4",'1'&x"33B5",'1'&x"33B6",'1'&x"33B7",'1'&x"33B8",'1'&x"33B9",'1'&x"33BA",'1'&x"33BB",'1'&x"33BC",'1'&x"33BD",'1'&x"33BE",'1'&x"33BF",
+--'1'&x"33C0",'1'&x"33C1",'1'&x"33C2",'1'&x"33C3",'1'&x"33C4",'1'&x"33C5",'1'&x"33C6",'1'&x"33C7",'1'&x"33C8",'1'&x"33C9",'1'&x"33CA",'1'&x"33CB",'1'&x"33CC",'1'&x"33CD",'1'&x"33CE",'1'&x"33CF",
+--'1'&x"33D0",'1'&x"33D1",'1'&x"33D2",'1'&x"33D3",'1'&x"33D4",'1'&x"33D5",'1'&x"33D6",'1'&x"33D7",'1'&x"33D8",'1'&x"33D9",'1'&x"33DA",'1'&x"33DB",'1'&x"33DC",'1'&x"33DD",'1'&x"33DE",'1'&x"33DF",
+--'1'&x"33E0",'1'&x"33E1",'1'&x"33E2",'1'&x"33E3",'1'&x"33E4",'1'&x"33E5",'1'&x"33E6",'1'&x"33E7",'1'&x"33E8",'1'&x"33E9",'1'&x"33EA",'1'&x"33EB",'1'&x"33EC",'1'&x"33ED",'1'&x"33EE",'1'&x"33EF",
+--'1'&x"33F0",'1'&x"33F1",'1'&x"33F2",'1'&x"33F3",'1'&x"33F4",'1'&x"33F5",'1'&x"33F6",'1'&x"33F7",'1'&x"33F8",'1'&x"33F9",'1'&x"33FA",'1'&x"33FB",'1'&x"33FC",'1'&x"33FD",'1'&x"33FE",'1'&x"33FF",
+--'1'&x"3400",'1'&x"3401",'1'&x"3402",'1'&x"3403",'1'&x"3404",'1'&x"3405",'1'&x"3406",'1'&x"3407",'1'&x"3408",'1'&x"3409",'1'&x"340A",'1'&x"340B",'1'&x"340C",'1'&x"340D",'1'&x"340E",'1'&x"340F",
+--'1'&x"3410",'1'&x"3411",'1'&x"3412",'1'&x"3413",'1'&x"3414",'1'&x"3415",'1'&x"3416",'1'&x"3417",'1'&x"3418",'1'&x"3419",'1'&x"341A",'1'&x"341B",'1'&x"341C",'1'&x"341D",'1'&x"341E",'1'&x"341F",
+--'1'&x"3420",'1'&x"3421",'1'&x"3422",'1'&x"3423",'1'&x"3424",'1'&x"3425",'1'&x"3426",'1'&x"3427",'1'&x"3428",'1'&x"3429",'1'&x"342A",'1'&x"342B",'1'&x"342C",'1'&x"342D",'1'&x"342E",'1'&x"342F",
+--'1'&x"3430",'1'&x"3431",'1'&x"3432",'1'&x"3433",'1'&x"3434",'1'&x"3435",'1'&x"3436",'1'&x"3437",'1'&x"3438",'1'&x"3439",'1'&x"343A",'1'&x"343B",'1'&x"343C",'1'&x"343D",'1'&x"343E",'1'&x"343F",
+--'1'&x"3440",'1'&x"3441",'1'&x"3442",'1'&x"3443",'1'&x"3444",'1'&x"3445",'1'&x"3446",'1'&x"3447",'1'&x"3448",'1'&x"3449",'1'&x"344A",'1'&x"344B",'1'&x"344C",'1'&x"344D",'1'&x"344E",'1'&x"344F",
+--'1'&x"3450",'1'&x"3451",'1'&x"3452",'1'&x"3453",'1'&x"3454",'1'&x"3455",'1'&x"3456",'1'&x"3457",'1'&x"3458",'1'&x"3459",'1'&x"345A",'1'&x"345B",'1'&x"345C",'1'&x"345D",'1'&x"345E",'1'&x"345F",
+--'1'&x"3460",'1'&x"3461",'1'&x"3462",'1'&x"3463",'1'&x"3464",'1'&x"3465",'1'&x"3466",'1'&x"3467",'1'&x"3468",'1'&x"3469",'1'&x"346A",'1'&x"346B",'1'&x"346C",'1'&x"346D",'1'&x"346E",'1'&x"346F",
+--'1'&x"3470",'1'&x"3471",'1'&x"3472",'1'&x"3473",'1'&x"3474",'1'&x"3475",'1'&x"3476",'1'&x"3477",'1'&x"3478",'1'&x"3479",'1'&x"347A",'1'&x"347B",'1'&x"347C",'1'&x"347D",'1'&x"347E",'1'&x"347F",
+--'1'&x"3480",'1'&x"3481",'1'&x"3482",'1'&x"3483",'1'&x"3484",'1'&x"3485",'1'&x"3486",'1'&x"3487",'1'&x"3488",'1'&x"3489",'1'&x"348A",'1'&x"348B",'1'&x"348C",'1'&x"348D",'1'&x"348E",'1'&x"348F",
+--'1'&x"3490",'1'&x"3491",'1'&x"3492",'1'&x"3493",'1'&x"3494",'1'&x"3495",'1'&x"3496",'1'&x"3497",'1'&x"3498",'1'&x"3499",'1'&x"349A",'1'&x"349B",'1'&x"349C",'1'&x"349D",'1'&x"349E",'1'&x"349F",
+--'1'&x"34A0",'1'&x"34A1",'1'&x"34A2",'1'&x"34A3",'1'&x"34A4",'1'&x"34A5",'1'&x"34A6",'1'&x"34A7",'1'&x"34A8",'1'&x"34A9",'1'&x"34AA",'1'&x"34AB",'1'&x"34AC",'1'&x"34AD",'1'&x"34AE",'1'&x"34AF",
+--'1'&x"34B0",'1'&x"34B1",'1'&x"34B2",'1'&x"34B3",'1'&x"34B4",'1'&x"34B5",'1'&x"34B6",'1'&x"34B7",'1'&x"34B8",'1'&x"34B9",'1'&x"34BA",'1'&x"34BB",'1'&x"34BC",'1'&x"34BD",'1'&x"34BE",'1'&x"34BF",
+--'1'&x"34C0",'1'&x"34C1",'1'&x"34C2",'1'&x"34C3",'1'&x"34C4",'1'&x"34C5",'1'&x"34C6",'1'&x"34C7",'1'&x"34C8",'1'&x"34C9",'1'&x"34CA",'1'&x"34CB",'1'&x"34CC",'1'&x"34CD",'1'&x"34CE",'1'&x"34CF",
+--'1'&x"34D0",'1'&x"34D1",'1'&x"34D2",'1'&x"34D3",'1'&x"34D4",'1'&x"34D5",'1'&x"34D6",'1'&x"34D7",'1'&x"34D8",'1'&x"34D9",'1'&x"34DA",'1'&x"34DB",'1'&x"34DC",'1'&x"34DD",'1'&x"34DE",'1'&x"34DF",
+--'1'&x"34E0",'1'&x"34E1",'1'&x"34E2",'1'&x"34E3",'1'&x"34E4",'1'&x"34E5",'1'&x"34E6",'1'&x"34E7",'1'&x"34E8",'1'&x"34E9",'1'&x"34EA",'1'&x"34EB",'1'&x"34EC",'1'&x"34ED",'1'&x"34EE",'1'&x"34EF",
+--'1'&x"34F0",'1'&x"34F1",'1'&x"34F2",'1'&x"34F3",'1'&x"34F4",'1'&x"34F5",'1'&x"34F6",'1'&x"34F7",'1'&x"34F8",'1'&x"34F9",'1'&x"34FA",'1'&x"34FB",'1'&x"34FC",'1'&x"34FD",'1'&x"34FE",'1'&x"34FF",
+--'1'&x"3500",'1'&x"3501",'1'&x"3502",'1'&x"3503",'1'&x"3504",'1'&x"3505",'1'&x"3506",'1'&x"3507",'1'&x"3508",'1'&x"3509",'1'&x"350A",'1'&x"350B",'1'&x"350C",'1'&x"350D",'1'&x"350E",'1'&x"350F",
+--'1'&x"3510",'1'&x"3511",'1'&x"3512",'1'&x"3513",'1'&x"3514",'1'&x"3515",'1'&x"3516",'1'&x"3517",'1'&x"3518",'1'&x"3519",'1'&x"351A",'1'&x"351B",'1'&x"351C",'1'&x"351D",'1'&x"351E",'1'&x"351F",
+--'1'&x"3520",'1'&x"3521",'1'&x"3522",'1'&x"3523",'1'&x"3524",'1'&x"3525",'1'&x"3526",'1'&x"3527",'1'&x"3528",'1'&x"3529",'1'&x"352A",'1'&x"352B",'1'&x"352C",'1'&x"352D",'1'&x"352E",'1'&x"352F",
+--'1'&x"3530",'1'&x"3531",'1'&x"3532",'1'&x"3533",'1'&x"3534",'1'&x"3535",'1'&x"3536",'1'&x"3537",'1'&x"3538",'1'&x"3539",'1'&x"353A",'1'&x"353B",'1'&x"353C",'1'&x"353D",'1'&x"353E",'1'&x"353F",
+--'1'&x"3540",'1'&x"3541",'1'&x"3542",'1'&x"3543",'1'&x"3544",'1'&x"3545",'1'&x"3546",'1'&x"3547",'1'&x"3548",'1'&x"3549",'1'&x"354A",'1'&x"354B",'1'&x"354C",'1'&x"354D",'1'&x"354E",'1'&x"354F",
+--'1'&x"3550",'1'&x"3551",'1'&x"3552",'1'&x"3553",'1'&x"3554",'1'&x"3555",'1'&x"3556",'1'&x"3557",'1'&x"3558",'1'&x"3559",'1'&x"355A",'1'&x"355B",'1'&x"355C",'1'&x"355D",'1'&x"355E",'1'&x"355F",
+--'1'&x"3560",'1'&x"3561",'1'&x"3562",'1'&x"3563",'1'&x"3564",'1'&x"3565",'1'&x"3566",'1'&x"3567",'1'&x"3568",'1'&x"3569",'1'&x"356A",'1'&x"356B",'1'&x"356C",'1'&x"356D",'1'&x"356E",'1'&x"356F",
+--'1'&x"3570",'1'&x"3571",'1'&x"3572",'1'&x"3573",'1'&x"3574",'1'&x"3575",'1'&x"3576",'1'&x"3577",'1'&x"3578",'1'&x"3579",'1'&x"357A",'1'&x"357B",'1'&x"357C",'1'&x"357D",'1'&x"357E",'1'&x"357F",
+--'1'&x"3580",'1'&x"3581",'1'&x"3582",'1'&x"3583",'1'&x"3584",'1'&x"3585",'1'&x"3586",'1'&x"3587",'1'&x"3588",'1'&x"3589",'1'&x"358A",'1'&x"358B",'1'&x"358C",'1'&x"358D",'1'&x"358E",'1'&x"358F",
+--'1'&x"3590",'1'&x"3591",'1'&x"3592",'1'&x"3593",'1'&x"3594",'1'&x"3595",'1'&x"3596",'1'&x"3597",'1'&x"3598",'1'&x"3599",'1'&x"359A",'1'&x"359B",'1'&x"359C",'1'&x"359D",'1'&x"359E",'1'&x"359F",
+--'1'&x"35A0",'1'&x"35A1",'1'&x"35A2",'1'&x"35A3",'1'&x"35A4",'1'&x"35A5",'1'&x"35A6",'1'&x"35A7",'1'&x"35A8",'1'&x"35A9",'1'&x"35AA",'1'&x"35AB",'1'&x"35AC",'1'&x"35AD",'1'&x"35AE",'1'&x"35AF",
+--'1'&x"35B0",'1'&x"35B1",'1'&x"35B2",'1'&x"35B3",'1'&x"35B4",'1'&x"35B5",'1'&x"35B6",'1'&x"35B7",'1'&x"35B8",'1'&x"35B9",'1'&x"35BA",'1'&x"35BB",'1'&x"35BC",'1'&x"35BD",'1'&x"35BE",'1'&x"35BF",
+--'1'&x"35C0",'1'&x"35C1",'1'&x"35C2",'1'&x"35C3",'1'&x"35C4",'1'&x"35C5",'1'&x"35C6",'1'&x"35C7",'1'&x"35C8",'1'&x"35C9",'1'&x"35CA",'1'&x"35CB",'1'&x"35CC",'1'&x"35CD",'1'&x"35CE",'1'&x"35CF",
+--'1'&x"35D0",'1'&x"35D1",'1'&x"35D2",'1'&x"35D3",'1'&x"35D4",'1'&x"35D5",'1'&x"35D6",'1'&x"35D7",'1'&x"35D8",'1'&x"35D9",'1'&x"35DA",'1'&x"35DB",'1'&x"35DC",'1'&x"35DD",'1'&x"35DE",'1'&x"35DF",
+--'1'&x"35E0",'1'&x"35E1",'1'&x"35E2",'1'&x"35E3",'1'&x"35E4",'1'&x"35E5",'1'&x"35E6",'1'&x"35E7",'1'&x"35E8",'1'&x"35E9",'1'&x"35EA",'1'&x"35EB",'1'&x"35EC",'1'&x"35ED",'1'&x"35EE",'1'&x"35EF",
+--'1'&x"35F0",'1'&x"35F1",'1'&x"35F2",'1'&x"35F3",'1'&x"35F4",'1'&x"35F5",'1'&x"35F6",'1'&x"35F7",'1'&x"35F8",'1'&x"35F9",'1'&x"35FA",'1'&x"35FB",'1'&x"35FC",'1'&x"35FD",'1'&x"35FE",'1'&x"35FF",
+--'1'&x"3600",'1'&x"3601",'1'&x"3602",'1'&x"3603",'1'&x"3604",'1'&x"3605",'1'&x"3606",'1'&x"3607",'1'&x"3608",'1'&x"3609",'1'&x"360A",'1'&x"360B",'1'&x"360C",'1'&x"360D",'1'&x"360E",'1'&x"360F",
+--'1'&x"3610",'1'&x"3611",'1'&x"3612",'1'&x"3613",'1'&x"3614",'1'&x"3615",'1'&x"3616",'1'&x"3617",'1'&x"3618",'1'&x"3619",'1'&x"361A",'1'&x"361B",'1'&x"361C",'1'&x"361D",'1'&x"361E",'1'&x"361F",
+--'1'&x"3620",'1'&x"3621",'1'&x"3622",'1'&x"3623",'1'&x"3624",'1'&x"3625",'1'&x"3626",'1'&x"3627",'1'&x"3628",'1'&x"3629",'1'&x"362A",'1'&x"362B",'1'&x"362C",'1'&x"362D",'1'&x"362E",'1'&x"362F",
+--'1'&x"3630",'1'&x"3631",'1'&x"3632",'1'&x"3633",'1'&x"3634",'1'&x"3635",'1'&x"3636",'1'&x"3637",'1'&x"3638",'1'&x"3639",'1'&x"363A",'1'&x"363B",'1'&x"363C",'1'&x"363D",'1'&x"363E",'1'&x"363F",
+--'1'&x"3640",'1'&x"3641",'1'&x"3642",'1'&x"3643",'1'&x"3644",'1'&x"3645",'1'&x"3646",'1'&x"3647",'1'&x"3648",'1'&x"3649",'1'&x"364A",'1'&x"364B",'1'&x"364C",'1'&x"364D",'1'&x"364E",'1'&x"364F",
+--'1'&x"3650",'1'&x"3651",'1'&x"3652",'1'&x"3653",'1'&x"3654",'1'&x"3655",'1'&x"3656",'1'&x"3657",'1'&x"3658",'1'&x"3659",'1'&x"365A",'1'&x"365B",'1'&x"365C",'1'&x"365D",'1'&x"365E",'1'&x"365F",
+--'1'&x"3660",'1'&x"3661",'1'&x"3662",'1'&x"3663",'1'&x"3664",'1'&x"3665",'1'&x"3666",'1'&x"3667",'1'&x"3668",'1'&x"3669",'1'&x"366A",'1'&x"366B",'1'&x"366C",'1'&x"366D",'1'&x"366E",'1'&x"366F",
+--'1'&x"3670",'1'&x"3671",'1'&x"3672",'1'&x"3673",'1'&x"3674",'1'&x"3675",'1'&x"3676",'1'&x"3677",'1'&x"3678",'1'&x"3679",'1'&x"367A",'1'&x"367B",'1'&x"367C",'1'&x"367D",'1'&x"367E",'1'&x"367F",
+--'1'&x"3680",'1'&x"3681",'1'&x"3682",'1'&x"3683",'1'&x"3684",'1'&x"3685",'1'&x"3686",'1'&x"3687",'1'&x"3688",'1'&x"3689",'1'&x"368A",'1'&x"368B",'1'&x"368C",'1'&x"368D",'1'&x"368E",'1'&x"368F",
+--'1'&x"3690",'1'&x"3691",'1'&x"3692",'1'&x"3693",'1'&x"3694",'1'&x"3695",'1'&x"3696",'1'&x"3697",'1'&x"3698",'1'&x"3699",'1'&x"369A",'1'&x"369B",'1'&x"369C",'1'&x"369D",'1'&x"369E",'1'&x"369F",
+--'1'&x"36A0",'1'&x"36A1",'1'&x"36A2",'1'&x"36A3",'1'&x"36A4",'1'&x"36A5",'1'&x"36A6",'1'&x"36A7",'1'&x"36A8",'1'&x"36A9",'1'&x"36AA",'1'&x"36AB",'1'&x"36AC",'1'&x"36AD",'1'&x"36AE",'1'&x"36AF",
+--'1'&x"36B0",'1'&x"36B1",'1'&x"36B2",'1'&x"36B3",'1'&x"36B4",'1'&x"36B5",'1'&x"36B6",'1'&x"36B7",'1'&x"36B8",'1'&x"36B9",'1'&x"36BA",'1'&x"36BB",'1'&x"36BC",'1'&x"36BD",'1'&x"36BE",'1'&x"36BF",
+--'1'&x"36C0",'1'&x"36C1",'1'&x"36C2",'1'&x"36C3",'1'&x"36C4",'1'&x"36C5",'1'&x"36C6",'1'&x"36C7",'1'&x"36C8",'1'&x"36C9",'1'&x"36CA",'1'&x"36CB",'1'&x"36CC",'1'&x"36CD",'1'&x"36CE",'1'&x"36CF",
+--'1'&x"36D0",'1'&x"36D1",'1'&x"36D2",'1'&x"36D3",'1'&x"36D4",'1'&x"36D5",'1'&x"36D6",'1'&x"36D7",'1'&x"36D8",'1'&x"36D9",'1'&x"36DA",'1'&x"36DB",'1'&x"36DC",'1'&x"36DD",'1'&x"36DE",'1'&x"36DF",
+--'1'&x"36E0",'1'&x"36E1",'1'&x"36E2",'1'&x"36E3",'1'&x"36E4",'1'&x"36E5",'1'&x"36E6",'1'&x"36E7",'1'&x"36E8",'1'&x"36E9",'1'&x"36EA",'1'&x"36EB",'1'&x"36EC",'1'&x"36ED",'1'&x"36EE",'1'&x"36EF",
+--'1'&x"36F0",'1'&x"36F1",'1'&x"36F2",'1'&x"36F3",'1'&x"36F4",'1'&x"36F5",'1'&x"36F6",'1'&x"36F7",'1'&x"36F8",'1'&x"36F9",'1'&x"36FA",'1'&x"36FB",'1'&x"36FC",'1'&x"36FD",'1'&x"36FE",'1'&x"36FF",
+--'1'&x"3700",'1'&x"3701",'1'&x"3702",'1'&x"3703",'1'&x"3704",'1'&x"3705",'1'&x"3706",'1'&x"3707",'1'&x"3708",'1'&x"3709",'1'&x"370A",'1'&x"370B",'1'&x"370C",'1'&x"370D",'1'&x"370E",'1'&x"370F",
+--'1'&x"3710",'1'&x"3711",'1'&x"3712",'1'&x"3713",'1'&x"3714",'1'&x"3715",'1'&x"3716",'1'&x"3717",'1'&x"3718",'1'&x"3719",'1'&x"371A",'1'&x"371B",'1'&x"371C",'1'&x"371D",'1'&x"371E",'1'&x"371F",
+--'1'&x"3720",'1'&x"3721",'1'&x"3722",'1'&x"3723",'1'&x"3724",'1'&x"3725",'1'&x"3726",'1'&x"3727",'1'&x"3728",'1'&x"3729",'1'&x"372A",'1'&x"372B",'1'&x"372C",'1'&x"372D",'1'&x"372E",'1'&x"372F",
+--'1'&x"3730",'1'&x"3731",'1'&x"3732",'1'&x"3733",'1'&x"3734",'1'&x"3735",'1'&x"3736",'1'&x"3737",'1'&x"3738",'1'&x"3739",'1'&x"373A",'1'&x"373B",'1'&x"373C",'1'&x"373D",'1'&x"373E",'1'&x"373F",
+--'1'&x"3740",'1'&x"3741",'1'&x"3742",'1'&x"3743",'1'&x"3744",'1'&x"3745",'1'&x"3746",'1'&x"3747",'1'&x"3748",'1'&x"3749",'1'&x"374A",'1'&x"374B",'1'&x"374C",'1'&x"374D",'1'&x"374E",'1'&x"374F",
+--'1'&x"3750",'1'&x"3751",'1'&x"3752",'1'&x"3753",'1'&x"3754",'1'&x"3755",'1'&x"3756",'1'&x"3757",'1'&x"3758",'1'&x"3759",'1'&x"375A",'1'&x"375B",'1'&x"375C",'1'&x"375D",'1'&x"375E",'1'&x"375F",
+--'1'&x"3760",'1'&x"3761",'1'&x"3762",'1'&x"3763",'1'&x"3764",'1'&x"3765",'1'&x"3766",'1'&x"3767",'1'&x"3768",'1'&x"3769",'1'&x"376A",'1'&x"376B",'1'&x"376C",'1'&x"376D",'1'&x"376E",'1'&x"376F",
+--'1'&x"3770",'1'&x"3771",'1'&x"3772",'1'&x"3773",'1'&x"3774",'1'&x"3775",'1'&x"3776",'1'&x"3777",'1'&x"3778",'1'&x"3779",'1'&x"377A",'1'&x"377B",'1'&x"377C",'1'&x"377D",'1'&x"377E",'1'&x"377F",
+--'1'&x"3780",'1'&x"3781",'1'&x"3782",'1'&x"3783",'1'&x"3784",'1'&x"3785",'1'&x"3786",'1'&x"3787",'1'&x"3788",'1'&x"3789",'1'&x"378A",'1'&x"378B",'1'&x"378C",'1'&x"378D",'1'&x"378E",'1'&x"378F",
+--'1'&x"3790",'1'&x"3791",'1'&x"3792",'1'&x"3793",'1'&x"3794",'1'&x"3795",'1'&x"3796",'1'&x"3797",'1'&x"3798",'1'&x"3799",'1'&x"379A",'1'&x"379B",'1'&x"379C",'1'&x"379D",'1'&x"379E",'1'&x"379F",
+--'1'&x"37A0",'1'&x"37A1",'1'&x"37A2",'1'&x"37A3",'1'&x"37A4",'1'&x"37A5",'1'&x"37A6",'1'&x"37A7",'1'&x"37A8",'1'&x"37A9",'1'&x"37AA",'1'&x"37AB",'1'&x"37AC",'1'&x"37AD",'1'&x"37AE",'1'&x"37AF",
+--'1'&x"37B0",'1'&x"37B1",'1'&x"37B2",'1'&x"37B3",'1'&x"37B4",'1'&x"37B5",'1'&x"37B6",'1'&x"37B7",'1'&x"37B8",'1'&x"37B9",'1'&x"37BA",'1'&x"37BB",'1'&x"37BC",'1'&x"37BD",'1'&x"37BE",'1'&x"37BF",
+--'1'&x"37C0",'1'&x"37C1",'1'&x"37C2",'1'&x"37C3",'1'&x"37C4",'1'&x"37C5",'1'&x"37C6",'1'&x"37C7",'1'&x"37C8",'1'&x"37C9",'1'&x"37CA",'1'&x"37CB",'1'&x"37CC",'1'&x"37CD",'1'&x"37CE",'1'&x"37CF",
+--'1'&x"37D0",'1'&x"37D1",'1'&x"37D2",'1'&x"37D3",'1'&x"37D4",'1'&x"37D5",'1'&x"37D6",'1'&x"37D7",'1'&x"37D8",'1'&x"37D9",'1'&x"37DA",'1'&x"37DB",'1'&x"37DC",'1'&x"37DD",'1'&x"37DE",'1'&x"37DF",
+--'1'&x"37E0",'1'&x"37E1",'1'&x"37E2",'1'&x"37E3",'1'&x"37E4",'1'&x"37E5",'1'&x"37E6",'1'&x"37E7",'1'&x"37E8",'1'&x"37E9",'1'&x"37EA",'1'&x"37EB",'1'&x"37EC",'1'&x"37ED",'1'&x"37EE",'1'&x"37EF",
+--'1'&x"37F0",'1'&x"37F1",'1'&x"37F2",'1'&x"37F3",'1'&x"37F4",'1'&x"37F5",'1'&x"37F6",'1'&x"37F7",'1'&x"37F8",'1'&x"37F9",'1'&x"37FA",'1'&x"37FB",'1'&x"37FC",'1'&x"37FD",'1'&x"37FE",'1'&x"37FF",
+--'1'&x"3800",'1'&x"3801",'1'&x"3802",'1'&x"3803",'1'&x"3804",'1'&x"3805",'1'&x"3806",'1'&x"3807",'1'&x"3808",'1'&x"3809",'1'&x"380A",'1'&x"380B",'1'&x"380C",'1'&x"380D",'1'&x"380E",'1'&x"380F",
+--'1'&x"3810",'1'&x"3811",'1'&x"3812",'1'&x"3813",'1'&x"3814",'1'&x"3815",'1'&x"3816",'1'&x"3817",'1'&x"3818",'1'&x"3819",'1'&x"381A",'1'&x"381B",'1'&x"381C",'1'&x"381D",'1'&x"381E",'1'&x"381F",
+--'1'&x"3820",'1'&x"3821",'1'&x"3822",'1'&x"3823",'1'&x"3824",'1'&x"3825",'1'&x"3826",'1'&x"3827",'1'&x"3828",'1'&x"3829",'1'&x"382A",'1'&x"382B",'1'&x"382C",'1'&x"382D",'1'&x"382E",'1'&x"382F",
+--'1'&x"3830",'1'&x"3831",'1'&x"3832",'1'&x"3833",'1'&x"3834",'1'&x"3835",'1'&x"3836",'1'&x"3837",'1'&x"3838",'1'&x"3839",'1'&x"383A",'1'&x"383B",'1'&x"383C",'1'&x"383D",'1'&x"383E",'1'&x"383F",
+--'1'&x"3840",'1'&x"3841",'1'&x"3842",'1'&x"3843",'1'&x"3844",'1'&x"3845",'1'&x"3846",'1'&x"3847",'1'&x"3848",'1'&x"3849",'1'&x"384A",'1'&x"384B",'1'&x"384C",'1'&x"384D",'1'&x"384E",'1'&x"384F",
+--'1'&x"3850",'1'&x"3851",'1'&x"3852",'1'&x"3853",'1'&x"3854",'1'&x"3855",'1'&x"3856",'1'&x"3857",'1'&x"3858",'1'&x"3859",'1'&x"385A",'1'&x"385B",'1'&x"385C",'1'&x"385D",'1'&x"385E",'1'&x"385F",
+--'1'&x"3860",'1'&x"3861",'1'&x"3862",'1'&x"3863",'1'&x"3864",'1'&x"3865",'1'&x"3866",'1'&x"3867",'1'&x"3868",'1'&x"3869",'1'&x"386A",'1'&x"386B",'1'&x"386C",'1'&x"386D",'1'&x"386E",'1'&x"386F",
+--'1'&x"3870",'1'&x"3871",'1'&x"3872",'1'&x"3873",'1'&x"3874",'1'&x"3875",'1'&x"3876",'1'&x"3877",'1'&x"3878",'1'&x"3879",'1'&x"387A",'1'&x"387B",'1'&x"387C",'1'&x"387D",'1'&x"387E",'1'&x"387F",
+--'1'&x"3880",'1'&x"3881",'1'&x"3882",'1'&x"3883",'1'&x"3884",'1'&x"3885",'1'&x"3886",'1'&x"3887",'1'&x"3888",'1'&x"3889",'1'&x"388A",'1'&x"388B",'1'&x"388C",'1'&x"388D",'1'&x"388E",'1'&x"388F",
+--'1'&x"3890",'1'&x"3891",'1'&x"3892",'1'&x"3893",'1'&x"3894",'1'&x"3895",'1'&x"3896",'1'&x"3897",'1'&x"3898",'1'&x"3899",'1'&x"389A",'1'&x"389B",'1'&x"389C",'1'&x"389D",'1'&x"389E",'1'&x"389F",
+--'1'&x"38A0",'1'&x"38A1",'1'&x"38A2",'1'&x"38A3",'1'&x"38A4",'1'&x"38A5",'1'&x"38A6",'1'&x"38A7",'1'&x"38A8",'1'&x"38A9",'1'&x"38AA",'1'&x"38AB",'1'&x"38AC",'1'&x"38AD",'1'&x"38AE",'1'&x"38AF",
+--'1'&x"38B0",'1'&x"38B1",'1'&x"38B2",'1'&x"38B3",'1'&x"38B4",'1'&x"38B5",'1'&x"38B6",'1'&x"38B7",'1'&x"38B8",'1'&x"38B9",'1'&x"38BA",'1'&x"38BB",'1'&x"38BC",'1'&x"38BD",'1'&x"38BE",'1'&x"38BF",
+--'1'&x"38C0",'1'&x"38C1",'1'&x"38C2",'1'&x"38C3",'1'&x"38C4",'1'&x"38C5",'1'&x"38C6",'1'&x"38C7",'1'&x"38C8",'1'&x"38C9",'1'&x"38CA",'1'&x"38CB",'1'&x"38CC",'1'&x"38CD",'1'&x"38CE",'1'&x"38CF",
+--'1'&x"38D0",'1'&x"38D1",'1'&x"38D2",'1'&x"38D3",'1'&x"38D4",'1'&x"38D5",'1'&x"38D6",'1'&x"38D7",'1'&x"38D8",'1'&x"38D9",'1'&x"38DA",'1'&x"38DB",'1'&x"38DC",'1'&x"38DD",'1'&x"38DE",'1'&x"38DF",
+--'1'&x"38E0",'1'&x"38E1",'1'&x"38E2",'1'&x"38E3",'1'&x"38E4",'1'&x"38E5",'1'&x"38E6",'1'&x"38E7",'1'&x"38E8",'1'&x"38E9",'1'&x"38EA",'1'&x"38EB",'1'&x"38EC",'1'&x"38ED",'1'&x"38EE",'1'&x"38EF",
+--'1'&x"38F0",'1'&x"38F1",'1'&x"38F2",'1'&x"38F3",'1'&x"38F4",'1'&x"38F5",'1'&x"38F6",'1'&x"38F7",'1'&x"38F8",'1'&x"38F9",'1'&x"38FA",'1'&x"38FB",'1'&x"38FC",'1'&x"38FD",'1'&x"38FE",'1'&x"38FF",
+--'1'&x"3900",'1'&x"3901",'1'&x"3902",'1'&x"3903",'1'&x"3904",'1'&x"3905",'1'&x"3906",'1'&x"3907",'1'&x"3908",'1'&x"3909",'1'&x"390A",'1'&x"390B",'1'&x"390C",'1'&x"390D",'1'&x"390E",'1'&x"390F",
+--'1'&x"3910",'1'&x"3911",'1'&x"3912",'1'&x"3913",'1'&x"3914",'1'&x"3915",'1'&x"3916",'1'&x"3917",'1'&x"3918",'1'&x"3919",'1'&x"391A",'1'&x"391B",'1'&x"391C",'1'&x"391D",'1'&x"391E",'1'&x"391F",
+--'1'&x"3920",'1'&x"3921",'1'&x"3922",'1'&x"3923",'1'&x"3924",'1'&x"3925",'1'&x"3926",'1'&x"3927",'1'&x"3928",'1'&x"3929",'1'&x"392A",'1'&x"392B",'1'&x"392C",'1'&x"392D",'1'&x"392E",'1'&x"392F",
+--'1'&x"3930",'1'&x"3931",'1'&x"3932",'1'&x"3933",'1'&x"3934",'1'&x"3935",'1'&x"3936",'1'&x"3937",'1'&x"3938",'1'&x"3939",'1'&x"393A",'1'&x"393B",'1'&x"393C",'1'&x"393D",'1'&x"393E",'1'&x"393F",
+--'1'&x"3940",'1'&x"3941",'1'&x"3942",'1'&x"3943",'1'&x"3944",'1'&x"3945",'1'&x"3946",'1'&x"3947",'1'&x"3948",'1'&x"3949",'1'&x"394A",'1'&x"394B",'1'&x"394C",'1'&x"394D",'1'&x"394E",'1'&x"394F",
+--'1'&x"3950",'1'&x"3951",'1'&x"3952",'1'&x"3953",'1'&x"3954",'1'&x"3955",'1'&x"3956",'1'&x"3957",'1'&x"3958",'1'&x"3959",'1'&x"395A",'1'&x"395B",'1'&x"395C",'1'&x"395D",'1'&x"395E",'1'&x"395F",
+--'1'&x"3960",'1'&x"3961",'1'&x"3962",'1'&x"3963",'1'&x"3964",'1'&x"3965",'1'&x"3966",'1'&x"3967",'1'&x"3968",'1'&x"3969",'1'&x"396A",'1'&x"396B",'1'&x"396C",'1'&x"396D",'1'&x"396E",'1'&x"396F",
+--'1'&x"3970",'1'&x"3971",'1'&x"3972",'1'&x"3973",'1'&x"3974",'1'&x"3975",'1'&x"3976",'1'&x"3977",'1'&x"3978",'1'&x"3979",'1'&x"397A",'1'&x"397B",'1'&x"397C",'1'&x"397D",'1'&x"397E",'1'&x"397F",
+--'1'&x"3980",'1'&x"3981",'1'&x"3982",'1'&x"3983",'1'&x"3984",'1'&x"3985",'1'&x"3986",'1'&x"3987",'1'&x"3988",'1'&x"3989",'1'&x"398A",'1'&x"398B",'1'&x"398C",'1'&x"398D",'1'&x"398E",'1'&x"398F",
+--'1'&x"3990",'1'&x"3991",'1'&x"3992",'1'&x"3993",'1'&x"3994",'1'&x"3995",'1'&x"3996",'1'&x"3997",'1'&x"3998",'1'&x"3999",'1'&x"399A",'1'&x"399B",'1'&x"399C",'1'&x"399D",'1'&x"399E",'1'&x"399F",
+--'1'&x"39A0",'1'&x"39A1",'1'&x"39A2",'1'&x"39A3",'1'&x"39A4",'1'&x"39A5",'1'&x"39A6",'1'&x"39A7",'1'&x"39A8",'1'&x"39A9",'1'&x"39AA",'1'&x"39AB",'1'&x"39AC",'1'&x"39AD",'1'&x"39AE",'1'&x"39AF",
+--'1'&x"39B0",'1'&x"39B1",'1'&x"39B2",'1'&x"39B3",'1'&x"39B4",'1'&x"39B5",'1'&x"39B6",'1'&x"39B7",'1'&x"39B8",'1'&x"39B9",'1'&x"39BA",'1'&x"39BB",'1'&x"39BC",'1'&x"39BD",'1'&x"39BE",'1'&x"39BF",
+--'1'&x"39C0",'1'&x"39C1",'1'&x"39C2",'1'&x"39C3",'1'&x"39C4",'1'&x"39C5",'1'&x"39C6",'1'&x"39C7",'1'&x"39C8",'1'&x"39C9",'1'&x"39CA",'1'&x"39CB",'1'&x"39CC",'1'&x"39CD",'1'&x"39CE",'1'&x"39CF",
+--'1'&x"39D0",'1'&x"39D1",'1'&x"39D2",'1'&x"39D3",'1'&x"39D4",'1'&x"39D5",'1'&x"39D6",'1'&x"39D7",'1'&x"39D8",'1'&x"39D9",'1'&x"39DA",'1'&x"39DB",'1'&x"39DC",'1'&x"39DD",'1'&x"39DE",'1'&x"39DF",
+--'1'&x"39E0",'1'&x"39E1",'1'&x"39E2",'1'&x"39E3",'1'&x"39E4",'1'&x"39E5",'1'&x"39E6",'1'&x"39E7",'1'&x"39E8",'1'&x"39E9",'1'&x"39EA",'1'&x"39EB",'1'&x"39EC",'1'&x"39ED",'1'&x"39EE",'1'&x"39EF",
+--'1'&x"39F0",'1'&x"39F1",'1'&x"39F2",'1'&x"39F3",'1'&x"39F4",'1'&x"39F5",'1'&x"39F6",'1'&x"39F7",'1'&x"39F8",'1'&x"39F9",'1'&x"39FA",'1'&x"39FB",'1'&x"39FC",'1'&x"39FD",'1'&x"39FE",'1'&x"39FF",
+--'1'&x"3A00",'1'&x"3A01",'1'&x"3A02",'1'&x"3A03",'1'&x"3A04",'1'&x"3A05",'1'&x"3A06",'1'&x"3A07",'1'&x"3A08",'1'&x"3A09",'1'&x"3A0A",'1'&x"3A0B",'1'&x"3A0C",'1'&x"3A0D",'1'&x"3A0E",'1'&x"3A0F",
+--'1'&x"3A10",'1'&x"3A11",'1'&x"3A12",'1'&x"3A13",'1'&x"3A14",'1'&x"3A15",'1'&x"3A16",'1'&x"3A17",'1'&x"3A18",'1'&x"3A19",'1'&x"3A1A",'1'&x"3A1B",'1'&x"3A1C",'1'&x"3A1D",'1'&x"3A1E",'1'&x"3A1F",
+--'1'&x"3A20",'1'&x"3A21",'1'&x"3A22",'1'&x"3A23",'1'&x"3A24",'1'&x"3A25",'1'&x"3A26",'1'&x"3A27",'1'&x"3A28",'1'&x"3A29",'1'&x"3A2A",'1'&x"3A2B",'1'&x"3A2C",'1'&x"3A2D",'1'&x"3A2E",'1'&x"3A2F",
+--'1'&x"3A30",'1'&x"3A31",'1'&x"3A32",'1'&x"3A33",'1'&x"3A34",'1'&x"3A35",'1'&x"3A36",'1'&x"3A37",'1'&x"3A38",'1'&x"3A39",'1'&x"3A3A",'1'&x"3A3B",'1'&x"3A3C",'1'&x"3A3D",'1'&x"3A3E",'1'&x"3A3F",
+--'1'&x"3A40",'1'&x"3A41",'1'&x"3A42",'1'&x"3A43",'1'&x"3A44",'1'&x"3A45",'1'&x"3A46",'1'&x"3A47",'1'&x"3A48",'1'&x"3A49",'1'&x"3A4A",'1'&x"3A4B",'1'&x"3A4C",'1'&x"3A4D",'1'&x"3A4E",'1'&x"3A4F",
+--'1'&x"3A50",'1'&x"3A51",'1'&x"3A52",'1'&x"3A53",'1'&x"3A54",'1'&x"3A55",'1'&x"3A56",'1'&x"3A57",'1'&x"3A58",'1'&x"3A59",'1'&x"3A5A",'1'&x"3A5B",'1'&x"3A5C",'1'&x"3A5D",'1'&x"3A5E",'1'&x"3A5F",
+--'1'&x"3A60",'1'&x"3A61",'1'&x"3A62",'1'&x"3A63",'1'&x"3A64",'1'&x"3A65",'1'&x"3A66",'1'&x"3A67",'1'&x"3A68",'1'&x"3A69",'1'&x"3A6A",'1'&x"3A6B",'1'&x"3A6C",'1'&x"3A6D",'1'&x"3A6E",'1'&x"3A6F",
+--'1'&x"3A70",'1'&x"3A71",'1'&x"3A72",'1'&x"3A73",'1'&x"3A74",'1'&x"3A75",'1'&x"3A76",'1'&x"3A77",'1'&x"3A78",'1'&x"3A79",'1'&x"3A7A",'1'&x"3A7B",'1'&x"3A7C",'1'&x"3A7D",'1'&x"3A7E",'1'&x"3A7F",
+--'1'&x"3A80",'1'&x"3A81",'1'&x"3A82",'1'&x"3A83",'1'&x"3A84",'1'&x"3A85",'1'&x"3A86",'1'&x"3A87",'1'&x"3A88",'1'&x"3A89",'1'&x"3A8A",'1'&x"3A8B",'1'&x"3A8C",'1'&x"3A8D",'1'&x"3A8E",'1'&x"3A8F",
+--'1'&x"3A90",'1'&x"3A91",'1'&x"3A92",'1'&x"3A93",'1'&x"3A94",'1'&x"3A95",'1'&x"3A96",'1'&x"3A97",'1'&x"3A98",'1'&x"3A99",'1'&x"3A9A",'1'&x"3A9B",'1'&x"3A9C",'1'&x"3A9D",'1'&x"3A9E",'1'&x"3A9F",
+--'1'&x"3AA0",'1'&x"3AA1",'1'&x"3AA2",'1'&x"3AA3",'1'&x"3AA4",'1'&x"3AA5",'1'&x"3AA6",'1'&x"3AA7",'1'&x"3AA8",'1'&x"3AA9",'1'&x"3AAA",'1'&x"3AAB",'1'&x"3AAC",'1'&x"3AAD",'1'&x"3AAE",'1'&x"3AAF",
+--'1'&x"3AB0",'1'&x"3AB1",'1'&x"3AB2",'1'&x"3AB3",'1'&x"3AB4",'1'&x"3AB5",'1'&x"3AB6",'1'&x"3AB7",'1'&x"3AB8",'1'&x"3AB9",'1'&x"3ABA",'1'&x"3ABB",'1'&x"3ABC",'1'&x"3ABD",'1'&x"3ABE",'1'&x"3ABF",
+--'1'&x"3AC0",'1'&x"3AC1",'1'&x"3AC2",'1'&x"3AC3",'1'&x"3AC4",'1'&x"3AC5",'1'&x"3AC6",'1'&x"3AC7",'1'&x"3AC8",'1'&x"3AC9",'1'&x"3ACA",'1'&x"3ACB",'1'&x"3ACC",'1'&x"3ACD",'1'&x"3ACE",'1'&x"3ACF",
+--'1'&x"3AD0",'1'&x"3AD1",'1'&x"3AD2",'1'&x"3AD3",'1'&x"3AD4",'1'&x"3AD5",'1'&x"3AD6",'1'&x"3AD7",'1'&x"3AD8",'1'&x"3AD9",'1'&x"3ADA",'1'&x"3ADB",'1'&x"3ADC",'1'&x"3ADD",'1'&x"3ADE",'1'&x"3ADF",
+--'1'&x"3AE0",'1'&x"3AE1",'1'&x"3AE2",'1'&x"3AE3",'1'&x"3AE4",'1'&x"3AE5",'1'&x"3AE6",'1'&x"3AE7",'1'&x"3AE8",'1'&x"3AE9",'1'&x"3AEA",'1'&x"3AEB",'1'&x"3AEC",'1'&x"3AED",'1'&x"3AEE",'1'&x"3AEF",
+--'1'&x"3AF0",'1'&x"3AF1",'1'&x"3AF2",'1'&x"3AF3",'1'&x"3AF4",'1'&x"3AF5",'1'&x"3AF6",'1'&x"3AF7",'1'&x"3AF8",'1'&x"3AF9",'1'&x"3AFA",'1'&x"3AFB",'1'&x"3AFC",'1'&x"3AFD",'1'&x"3AFE",'1'&x"3AFF",
+--'1'&x"3B00",'1'&x"3B01",'1'&x"3B02",'1'&x"3B03",'1'&x"3B04",'1'&x"3B05",'1'&x"3B06",'1'&x"3B07",'1'&x"3B08",'1'&x"3B09",'1'&x"3B0A",'1'&x"3B0B",'1'&x"3B0C",'1'&x"3B0D",'1'&x"3B0E",'1'&x"3B0F",
+--'1'&x"3B10",'1'&x"3B11",'1'&x"3B12",'1'&x"3B13",'1'&x"3B14",'1'&x"3B15",'1'&x"3B16",'1'&x"3B17",'1'&x"3B18",'1'&x"3B19",'1'&x"3B1A",'1'&x"3B1B",'1'&x"3B1C",'1'&x"3B1D",'1'&x"3B1E",'1'&x"3B1F",
+--'1'&x"3B20",'1'&x"3B21",'1'&x"3B22",'1'&x"3B23",'1'&x"3B24",'1'&x"3B25",'1'&x"3B26",'1'&x"3B27",'1'&x"3B28",'1'&x"3B29",'1'&x"3B2A",'1'&x"3B2B",'1'&x"3B2C",'1'&x"3B2D",'1'&x"3B2E",'1'&x"3B2F",
+--'1'&x"3B30",'1'&x"3B31",'1'&x"3B32",'1'&x"3B33",'1'&x"3B34",'1'&x"3B35",'1'&x"3B36",'1'&x"3B37",'1'&x"3B38",'1'&x"3B39",'1'&x"3B3A",'1'&x"3B3B",'1'&x"3B3C",'1'&x"3B3D",'1'&x"3B3E",'1'&x"3B3F",
+--'1'&x"3B40",'1'&x"3B41",'1'&x"3B42",'1'&x"3B43",'1'&x"3B44",'1'&x"3B45",'1'&x"3B46",'1'&x"3B47",'1'&x"3B48",'1'&x"3B49",'1'&x"3B4A",'1'&x"3B4B",'1'&x"3B4C",'1'&x"3B4D",'1'&x"3B4E",'1'&x"3B4F",
+--'1'&x"3B50",'1'&x"3B51",'1'&x"3B52",'1'&x"3B53",'1'&x"3B54",'1'&x"3B55",'1'&x"3B56",'1'&x"3B57",'1'&x"3B58",'1'&x"3B59",'1'&x"3B5A",'1'&x"3B5B",'1'&x"3B5C",'1'&x"3B5D",'1'&x"3B5E",'1'&x"3B5F",
+--'1'&x"3B60",'1'&x"3B61",'1'&x"3B62",'1'&x"3B63",'1'&x"3B64",'1'&x"3B65",'1'&x"3B66",'1'&x"3B67",'1'&x"3B68",'1'&x"3B69",'1'&x"3B6A",'1'&x"3B6B",'1'&x"3B6C",'1'&x"3B6D",'1'&x"3B6E",'1'&x"3B6F",
+--'1'&x"3B70",'1'&x"3B71",'1'&x"3B72",'1'&x"3B73",'1'&x"3B74",'1'&x"3B75",'1'&x"3B76",'1'&x"3B77",'1'&x"3B78",'1'&x"3B79",'1'&x"3B7A",'1'&x"3B7B",'1'&x"3B7C",'1'&x"3B7D",'1'&x"3B7E",'1'&x"3B7F",
+--'1'&x"3B80",'1'&x"3B81",'1'&x"3B82",'1'&x"3B83",'1'&x"3B84",'1'&x"3B85",'1'&x"3B86",'1'&x"3B87",'1'&x"3B88",'1'&x"3B89",'1'&x"3B8A",'1'&x"3B8B",'1'&x"3B8C",'1'&x"3B8D",'1'&x"3B8E",'1'&x"3B8F",
+--'1'&x"3B90",'1'&x"3B91",'1'&x"3B92",'1'&x"3B93",'1'&x"3B94",'1'&x"3B95",'1'&x"3B96",'1'&x"3B97",'1'&x"3B98",'1'&x"3B99",'1'&x"3B9A",'1'&x"3B9B",'1'&x"3B9C",'1'&x"3B9D",'1'&x"3B9E",'1'&x"3B9F",
+--'1'&x"3BA0",'1'&x"3BA1",'1'&x"3BA2",'1'&x"3BA3",'1'&x"3BA4",'1'&x"3BA5",'1'&x"3BA6",'1'&x"3BA7",'1'&x"3BA8",'1'&x"3BA9",'1'&x"3BAA",'1'&x"3BAB",'1'&x"3BAC",'1'&x"3BAD",'1'&x"3BAE",'1'&x"3BAF",
+--'1'&x"3BB0",'1'&x"3BB1",'1'&x"3BB2",'1'&x"3BB3",'1'&x"3BB4",'1'&x"3BB5",'1'&x"3BB6",'1'&x"3BB7",'1'&x"3BB8",'1'&x"3BB9",'1'&x"3BBA",'1'&x"3BBB",'1'&x"3BBC",'1'&x"3BBD",'1'&x"3BBE",'1'&x"3BBF",
+--'1'&x"3BC0",'1'&x"3BC1",'1'&x"3BC2",'1'&x"3BC3",'1'&x"3BC4",'1'&x"3BC5",'1'&x"3BC6",'1'&x"3BC7",'1'&x"3BC8",'1'&x"3BC9",'1'&x"3BCA",'1'&x"3BCB",'1'&x"3BCC",'1'&x"3BCD",'1'&x"3BCE",'1'&x"3BCF",
+--'1'&x"3BD0",'1'&x"3BD1",'1'&x"3BD2",'1'&x"3BD3",'1'&x"3BD4",'1'&x"3BD5",'1'&x"3BD6",'1'&x"3BD7",'1'&x"3BD8",'1'&x"3BD9",'1'&x"3BDA",'1'&x"3BDB",'1'&x"3BDC",'1'&x"3BDD",'1'&x"3BDE",'1'&x"3BDF",
+--'1'&x"3BE0",'1'&x"3BE1",'1'&x"3BE2",'1'&x"3BE3",'1'&x"3BE4",'1'&x"3BE5",'1'&x"3BE6",'1'&x"3BE7",'1'&x"3BE8",'1'&x"3BE9",'1'&x"3BEA",'1'&x"3BEB",'1'&x"3BEC",'1'&x"3BED",'1'&x"3BEE",'1'&x"3BEF",
+--'1'&x"3BF0",'1'&x"3BF1",'1'&x"3BF2",'1'&x"3BF3",'1'&x"3BF4",'1'&x"3BF5",'1'&x"3BF6",'1'&x"3BF7",'1'&x"3BF8",'1'&x"3BF9",'1'&x"3BFA",'1'&x"3BFB",'1'&x"3BFC",'1'&x"3BFD",'1'&x"3BFE",'1'&x"3BFF",
+--'1'&x"3C00",'1'&x"3C01",'1'&x"3C02",'1'&x"3C03",'1'&x"3C04",'1'&x"3C05",'1'&x"3C06",'1'&x"3C07",'1'&x"3C08",'1'&x"3C09",'1'&x"3C0A",'1'&x"3C0B",'1'&x"3C0C",'1'&x"3C0D",'1'&x"3C0E",'1'&x"3C0F",
+--'1'&x"3C10",'1'&x"3C11",'1'&x"3C12",'1'&x"3C13",'1'&x"3C14",'1'&x"3C15",'1'&x"3C16",'1'&x"3C17",'1'&x"3C18",'1'&x"3C19",'1'&x"3C1A",'1'&x"3C1B",'1'&x"3C1C",'1'&x"3C1D",'1'&x"3C1E",'1'&x"3C1F",
+--'1'&x"3C20",'1'&x"3C21",'1'&x"3C22",'1'&x"3C23",'1'&x"3C24",'1'&x"3C25",'1'&x"3C26",'1'&x"3C27",'1'&x"3C28",'1'&x"3C29",'1'&x"3C2A",'1'&x"3C2B",'1'&x"3C2C",'1'&x"3C2D",'1'&x"3C2E",'1'&x"3C2F",
+--'1'&x"3C30",'1'&x"3C31",'1'&x"3C32",'1'&x"3C33",'1'&x"3C34",'1'&x"3C35",'1'&x"3C36",'1'&x"3C37",'1'&x"3C38",'1'&x"3C39",'1'&x"3C3A",'1'&x"3C3B",'1'&x"3C3C",'1'&x"3C3D",'1'&x"3C3E",'1'&x"3C3F",
+--'1'&x"3C40",'1'&x"3C41",'1'&x"3C42",'1'&x"3C43",'1'&x"3C44",'1'&x"3C45",'1'&x"3C46",'1'&x"3C47",'1'&x"3C48",'1'&x"3C49",'1'&x"3C4A",'1'&x"3C4B",'1'&x"3C4C",'1'&x"3C4D",'1'&x"3C4E",'1'&x"3C4F",
+--'1'&x"3C50",'1'&x"3C51",'1'&x"3C52",'1'&x"3C53",'1'&x"3C54",'1'&x"3C55",'1'&x"3C56",'1'&x"3C57",'1'&x"3C58",'1'&x"3C59",'1'&x"3C5A",'1'&x"3C5B",'1'&x"3C5C",'1'&x"3C5D",'1'&x"3C5E",'1'&x"3C5F",
+--'1'&x"3C60",'1'&x"3C61",'1'&x"3C62",'1'&x"3C63",'1'&x"3C64",'1'&x"3C65",'1'&x"3C66",'1'&x"3C67",'1'&x"3C68",'1'&x"3C69",'1'&x"3C6A",'1'&x"3C6B",'1'&x"3C6C",'1'&x"3C6D",'1'&x"3C6E",'1'&x"3C6F",
+--'1'&x"3C70",'1'&x"3C71",'1'&x"3C72",'1'&x"3C73",'1'&x"3C74",'1'&x"3C75",'1'&x"3C76",'1'&x"3C77",'1'&x"3C78",'1'&x"3C79",'1'&x"3C7A",'1'&x"3C7B",'1'&x"3C7C",'1'&x"3C7D",'1'&x"3C7E",'1'&x"3C7F",
+--'1'&x"3C80",'1'&x"3C81",'1'&x"3C82",'1'&x"3C83",'1'&x"3C84",'1'&x"3C85",'1'&x"3C86",'1'&x"3C87",'1'&x"3C88",'1'&x"3C89",'1'&x"3C8A",'1'&x"3C8B",'1'&x"3C8C",'1'&x"3C8D",'1'&x"3C8E",'1'&x"3C8F",
+--'1'&x"3C90",'1'&x"3C91",'1'&x"3C92",'1'&x"3C93",'1'&x"3C94",'1'&x"3C95",'1'&x"3C96",'1'&x"3C97",'1'&x"3C98",'1'&x"3C99",'1'&x"3C9A",'1'&x"3C9B",'1'&x"3C9C",'1'&x"3C9D",'1'&x"3C9E",'1'&x"3C9F",
+--'1'&x"3CA0",'1'&x"3CA1",'1'&x"3CA2",'1'&x"3CA3",'1'&x"3CA4",'1'&x"3CA5",'1'&x"3CA6",'1'&x"3CA7",'1'&x"3CA8",'1'&x"3CA9",'1'&x"3CAA",'1'&x"3CAB",'1'&x"3CAC",'1'&x"3CAD",'1'&x"3CAE",'1'&x"3CAF",
+--'1'&x"3CB0",'1'&x"3CB1",'1'&x"3CB2",'1'&x"3CB3",'1'&x"3CB4",'1'&x"3CB5",'1'&x"3CB6",'1'&x"3CB7",'1'&x"3CB8",'1'&x"3CB9",'1'&x"3CBA",'1'&x"3CBB",'1'&x"3CBC",'1'&x"3CBD",'1'&x"3CBE",'1'&x"3CBF",
+--'1'&x"3CC0",'1'&x"3CC1",'1'&x"3CC2",'1'&x"3CC3",'1'&x"3CC4",'1'&x"3CC5",'1'&x"3CC6",'1'&x"3CC7",'1'&x"3CC8",'1'&x"3CC9",'1'&x"3CCA",'1'&x"3CCB",'1'&x"3CCC",'1'&x"3CCD",'1'&x"3CCE",'1'&x"3CCF",
+--'1'&x"3CD0",'1'&x"3CD1",'1'&x"3CD2",'1'&x"3CD3",'1'&x"3CD4",'1'&x"3CD5",'1'&x"3CD6",'1'&x"3CD7",'1'&x"3CD8",'1'&x"3CD9",'1'&x"3CDA",'1'&x"3CDB",'1'&x"3CDC",'1'&x"3CDD",'1'&x"3CDE",'1'&x"3CDF",
+--'1'&x"3CE0",'1'&x"3CE1",'1'&x"3CE2",'1'&x"3CE3",'1'&x"3CE4",'1'&x"3CE5",'1'&x"3CE6",'1'&x"3CE7",'1'&x"3CE8",'1'&x"3CE9",'1'&x"3CEA",'1'&x"3CEB",'1'&x"3CEC",'1'&x"3CED",'1'&x"3CEE",'1'&x"3CEF",
+--'1'&x"3CF0",'1'&x"3CF1",'1'&x"3CF2",'1'&x"3CF3",'1'&x"3CF4",'1'&x"3CF5",'1'&x"3CF6",'1'&x"3CF7",'1'&x"3CF8",'1'&x"3CF9",'1'&x"3CFA",'1'&x"3CFB",'1'&x"3CFC",'1'&x"3CFD",'1'&x"3CFE",'1'&x"3CFF",
+--'1'&x"3D00",'1'&x"3D01",'1'&x"3D02",'1'&x"3D03",'1'&x"3D04",'1'&x"3D05",'1'&x"3D06",'1'&x"3D07",'1'&x"3D08",'1'&x"3D09",'1'&x"3D0A",'1'&x"3D0B",'1'&x"3D0C",'1'&x"3D0D",'1'&x"3D0E",'1'&x"3D0F",
+--'1'&x"3D10",'1'&x"3D11",'1'&x"3D12",'1'&x"3D13",'1'&x"3D14",'1'&x"3D15",'1'&x"3D16",'1'&x"3D17",'1'&x"3D18",'1'&x"3D19",'1'&x"3D1A",'1'&x"3D1B",'1'&x"3D1C",'1'&x"3D1D",'1'&x"3D1E",'1'&x"3D1F",
+--'1'&x"3D20",'1'&x"3D21",'1'&x"3D22",'1'&x"3D23",'1'&x"3D24",'1'&x"3D25",'1'&x"3D26",'1'&x"3D27",'1'&x"3D28",'1'&x"3D29",'1'&x"3D2A",'1'&x"3D2B",'1'&x"3D2C",'1'&x"3D2D",'1'&x"3D2E",'1'&x"3D2F",
+--'1'&x"3D30",'1'&x"3D31",'1'&x"3D32",'1'&x"3D33",'1'&x"3D34",'1'&x"3D35",'1'&x"3D36",'1'&x"3D37",'1'&x"3D38",'1'&x"3D39",'1'&x"3D3A",'1'&x"3D3B",'1'&x"3D3C",'1'&x"3D3D",'1'&x"3D3E",'1'&x"3D3F",
+--'1'&x"3D40",'1'&x"3D41",'1'&x"3D42",'1'&x"3D43",'1'&x"3D44",'1'&x"3D45",'1'&x"3D46",'1'&x"3D47",'1'&x"3D48",'1'&x"3D49",'1'&x"3D4A",'1'&x"3D4B",'1'&x"3D4C",'1'&x"3D4D",'1'&x"3D4E",'1'&x"3D4F",
+--'1'&x"3D50",'1'&x"3D51",'1'&x"3D52",'1'&x"3D53",'1'&x"3D54",'1'&x"3D55",'1'&x"3D56",'1'&x"3D57",'1'&x"3D58",'1'&x"3D59",'1'&x"3D5A",'1'&x"3D5B",'1'&x"3D5C",'1'&x"3D5D",'1'&x"3D5E",'1'&x"3D5F",
+--'1'&x"3D60",'1'&x"3D61",'1'&x"3D62",'1'&x"3D63",'1'&x"3D64",'1'&x"3D65",'1'&x"3D66",'1'&x"3D67",'1'&x"3D68",'1'&x"3D69",'1'&x"3D6A",'1'&x"3D6B",'1'&x"3D6C",'1'&x"3D6D",'1'&x"3D6E",'1'&x"3D6F",
+--'1'&x"3D70",'1'&x"3D71",'1'&x"3D72",'1'&x"3D73",'1'&x"3D74",'1'&x"3D75",'1'&x"3D76",'1'&x"3D77",'1'&x"3D78",'1'&x"3D79",'1'&x"3D7A",'1'&x"3D7B",'1'&x"3D7C",'1'&x"3D7D",'1'&x"3D7E",'1'&x"3D7F",
+--'1'&x"3D80",'1'&x"3D81",'1'&x"3D82",'1'&x"3D83",'1'&x"3D84",'1'&x"3D85",'1'&x"3D86",'1'&x"3D87",'1'&x"3D88",'1'&x"3D89",'1'&x"3D8A",'1'&x"3D8B",'1'&x"3D8C",'1'&x"3D8D",'1'&x"3D8E",'1'&x"3D8F",
+--'1'&x"3D90",'1'&x"3D91",'1'&x"3D92",'1'&x"3D93",'1'&x"3D94",'1'&x"3D95",'1'&x"3D96",'1'&x"3D97",'1'&x"3D98",'1'&x"3D99",'1'&x"3D9A",'1'&x"3D9B",'1'&x"3D9C",'1'&x"3D9D",'1'&x"3D9E",'1'&x"3D9F",
+--'1'&x"3DA0",'1'&x"3DA1",'1'&x"3DA2",'1'&x"3DA3",'1'&x"3DA4",'1'&x"3DA5",'1'&x"3DA6",'1'&x"3DA7",'1'&x"3DA8",'1'&x"3DA9",'1'&x"3DAA",'1'&x"3DAB",'1'&x"3DAC",'1'&x"3DAD",'1'&x"3DAE",'1'&x"3DAF",
+--'1'&x"3DB0",'1'&x"3DB1",'1'&x"3DB2",'1'&x"3DB3",'1'&x"3DB4",'1'&x"3DB5",'1'&x"3DB6",'1'&x"3DB7",'1'&x"3DB8",'1'&x"3DB9",'1'&x"3DBA",'1'&x"3DBB",'1'&x"3DBC",'1'&x"3DBD",'1'&x"3DBE",'1'&x"3DBF",
+--'1'&x"3DC0",'1'&x"3DC1",'1'&x"3DC2",'1'&x"3DC3",'1'&x"3DC4",'1'&x"3DC5",'1'&x"3DC6",'1'&x"3DC7",'1'&x"3DC8",'1'&x"3DC9",'1'&x"3DCA",'1'&x"3DCB",'1'&x"3DCC",'1'&x"3DCD",'1'&x"3DCE",'1'&x"3DCF",
+--'1'&x"3DD0",'1'&x"3DD1",'1'&x"3DD2",'1'&x"3DD3",'1'&x"3DD4",'1'&x"3DD5",'1'&x"3DD6",'1'&x"3DD7",'1'&x"3DD8",'1'&x"3DD9",'1'&x"3DDA",'1'&x"3DDB",'1'&x"3DDC",'1'&x"3DDD",'1'&x"3DDE",'1'&x"3DDF",
+--'1'&x"3DE0",'1'&x"3DE1",'1'&x"3DE2",'1'&x"3DE3",'1'&x"3DE4",'1'&x"3DE5",'1'&x"3DE6",'1'&x"3DE7",'1'&x"3DE8",'1'&x"3DE9",'1'&x"3DEA",'1'&x"3DEB",'1'&x"3DEC",'1'&x"3DED",'1'&x"3DEE",'1'&x"3DEF",
+--'1'&x"3DF0",'1'&x"3DF1",'1'&x"3DF2",'1'&x"3DF3",'1'&x"3DF4",'1'&x"3DF5",'1'&x"3DF6",'1'&x"3DF7",'1'&x"3DF8",'1'&x"3DF9",'1'&x"3DFA",'1'&x"3DFB",'1'&x"3DFC",'1'&x"3DFD",'1'&x"3DFE",'1'&x"3DFF",
+--'1'&x"3E00",'1'&x"3E01",'1'&x"3E02",'1'&x"3E03",'1'&x"3E04",'1'&x"3E05",'1'&x"3E06",'1'&x"3E07",'1'&x"3E08",'1'&x"3E09",'1'&x"3E0A",'1'&x"3E0B",'1'&x"3E0C",'1'&x"3E0D",'1'&x"3E0E",'1'&x"3E0F",
+--'1'&x"3E10",'1'&x"3E11",'1'&x"3E12",'1'&x"3E13",'1'&x"3E14",'1'&x"3E15",'1'&x"3E16",'1'&x"3E17",'1'&x"3E18",'1'&x"3E19",'1'&x"3E1A",'1'&x"3E1B",'1'&x"3E1C",'1'&x"3E1D",'1'&x"3E1E",'1'&x"3E1F",
+--'1'&x"3E20",'1'&x"3E21",'1'&x"3E22",'1'&x"3E23",'1'&x"3E24",'1'&x"3E25",'1'&x"3E26",'1'&x"3E27",'1'&x"3E28",'1'&x"3E29",'1'&x"3E2A",'1'&x"3E2B",'1'&x"3E2C",'1'&x"3E2D",'1'&x"3E2E",'1'&x"3E2F",
+--'1'&x"3E30",'1'&x"3E31",'1'&x"3E32",'1'&x"3E33",'1'&x"3E34",'1'&x"3E35",'1'&x"3E36",'1'&x"3E37",'1'&x"3E38",'1'&x"3E39",'1'&x"3E3A",'1'&x"3E3B",'1'&x"3E3C",'1'&x"3E3D",'1'&x"3E3E",'1'&x"3E3F",
+--'1'&x"3E40",'1'&x"3E41",'1'&x"3E42",'1'&x"3E43",'1'&x"3E44",'1'&x"3E45",'1'&x"3E46",'1'&x"3E47",'1'&x"3E48",'1'&x"3E49",'1'&x"3E4A",'1'&x"3E4B",'1'&x"3E4C",'1'&x"3E4D",'1'&x"3E4E",'1'&x"3E4F",
+--'1'&x"3E50",'1'&x"3E51",'1'&x"3E52",'1'&x"3E53",'1'&x"3E54",'1'&x"3E55",'1'&x"3E56",'1'&x"3E57",'1'&x"3E58",'1'&x"3E59",'1'&x"3E5A",'1'&x"3E5B",'1'&x"3E5C",'1'&x"3E5D",'1'&x"3E5E",'1'&x"3E5F",
+--'1'&x"3E60",'1'&x"3E61",'1'&x"3E62",'1'&x"3E63",'1'&x"3E64",'1'&x"3E65",'1'&x"3E66",'1'&x"3E67",'1'&x"3E68",'1'&x"3E69",'1'&x"3E6A",'1'&x"3E6B",'1'&x"3E6C",'1'&x"3E6D",'1'&x"3E6E",'1'&x"3E6F",
+--'1'&x"3E70",'1'&x"3E71",'1'&x"3E72",'1'&x"3E73",'1'&x"3E74",'1'&x"3E75",'1'&x"3E76",'1'&x"3E77",'1'&x"3E78",'1'&x"3E79",'1'&x"3E7A",'1'&x"3E7B",'1'&x"3E7C",'1'&x"3E7D",'1'&x"3E7E",'1'&x"3E7F",
+--'1'&x"3E80",'1'&x"3E81",'1'&x"3E82",'1'&x"3E83",'1'&x"3E84",'1'&x"3E85",'1'&x"3E86",'1'&x"3E87",'1'&x"3E88",'1'&x"3E89",'1'&x"3E8A",'1'&x"3E8B",'1'&x"3E8C",'1'&x"3E8D",'1'&x"3E8E",'1'&x"3E8F",
+--'1'&x"3E90",'1'&x"3E91",'1'&x"3E92",'1'&x"3E93",'1'&x"3E94",'1'&x"3E95",'1'&x"3E96",'1'&x"3E97",'1'&x"3E98",'1'&x"3E99",'1'&x"3E9A",'1'&x"3E9B",'1'&x"3E9C",'1'&x"3E9D",'1'&x"3E9E",'1'&x"3E9F",
+--'1'&x"3EA0",'1'&x"3EA1",'1'&x"3EA2",'1'&x"3EA3",'1'&x"3EA4",'1'&x"3EA5",'1'&x"3EA6",'1'&x"3EA7",'1'&x"3EA8",'1'&x"3EA9",'1'&x"3EAA",'1'&x"3EAB",'1'&x"3EAC",'1'&x"3EAD",'1'&x"3EAE",'1'&x"3EAF",
+--'1'&x"3EB0",'1'&x"3EB1",'1'&x"3EB2",'1'&x"3EB3",'1'&x"3EB4",'1'&x"3EB5",'1'&x"3EB6",'1'&x"3EB7",'1'&x"3EB8",'1'&x"3EB9",'1'&x"3EBA",'1'&x"3EBB",'1'&x"3EBC",'1'&x"3EBD",'1'&x"3EBE",'1'&x"3EBF",
+--'1'&x"3EC0",'1'&x"3EC1",'1'&x"3EC2",'1'&x"3EC3",'1'&x"3EC4",'1'&x"3EC5",'1'&x"3EC6",'1'&x"3EC7",'1'&x"3EC8",'1'&x"3EC9",'1'&x"3ECA",'1'&x"3ECB",'1'&x"3ECC",'1'&x"3ECD",'1'&x"3ECE",'1'&x"3ECF",
+--'1'&x"3ED0",'1'&x"3ED1",'1'&x"3ED2",'1'&x"3ED3",'1'&x"3ED4",'1'&x"3ED5",'1'&x"3ED6",'1'&x"3ED7",'1'&x"3ED8",'1'&x"3ED9",'1'&x"3EDA",'1'&x"3EDB",'1'&x"3EDC",'1'&x"3EDD",'1'&x"3EDE",'1'&x"3EDF",
+--'1'&x"3EE0",'1'&x"3EE1",'1'&x"3EE2",'1'&x"3EE3",'1'&x"3EE4",'1'&x"3EE5",'1'&x"3EE6",'1'&x"3EE7",'1'&x"3EE8",'1'&x"3EE9",'1'&x"3EEA",'1'&x"3EEB",'1'&x"3EEC",'1'&x"3EED",'1'&x"3EEE",'1'&x"3EEF",
+--'1'&x"3EF0",'1'&x"3EF1",'1'&x"3EF2",'1'&x"3EF3",'1'&x"3EF4",'1'&x"3EF5",'1'&x"3EF6",'1'&x"3EF7",'1'&x"3EF8",'1'&x"3EF9",'1'&x"3EFA",'1'&x"3EFB",'1'&x"3EFC",'1'&x"3EFD",'1'&x"3EFE",'1'&x"3EFF",
+--'1'&x"3F00",'1'&x"3F01",'1'&x"3F02",'1'&x"3F03",'1'&x"3F04",'1'&x"3F05",'1'&x"3F06",'1'&x"3F07",'1'&x"3F08",'1'&x"3F09",'1'&x"3F0A",'1'&x"3F0B",'1'&x"3F0C",'1'&x"3F0D",'1'&x"3F0E",'1'&x"3F0F",
+--'1'&x"3F10",'1'&x"3F11",'1'&x"3F12",'1'&x"3F13",'1'&x"3F14",'1'&x"3F15",'1'&x"3F16",'1'&x"3F17",'1'&x"3F18",'1'&x"3F19",'1'&x"3F1A",'1'&x"3F1B",'1'&x"3F1C",'1'&x"3F1D",'1'&x"3F1E",'1'&x"3F1F",
+--'1'&x"3F20",'1'&x"3F21",'1'&x"3F22",'1'&x"3F23",'1'&x"3F24",'1'&x"3F25",'1'&x"3F26",'1'&x"3F27",'1'&x"3F28",'1'&x"3F29",'1'&x"3F2A",'1'&x"3F2B",'1'&x"3F2C",'1'&x"3F2D",'1'&x"3F2E",'1'&x"3F2F",
+--'1'&x"3F30",'1'&x"3F31",'1'&x"3F32",'1'&x"3F33",'1'&x"3F34",'1'&x"3F35",'1'&x"3F36",'1'&x"3F37",'1'&x"3F38",'1'&x"3F39",'1'&x"3F3A",'1'&x"3F3B",'1'&x"3F3C",'1'&x"3F3D",'1'&x"3F3E",'1'&x"3F3F",
+--'1'&x"3F40",'1'&x"3F41",'1'&x"3F42",'1'&x"3F43",'1'&x"3F44",'1'&x"3F45",'1'&x"3F46",'1'&x"3F47",'1'&x"3F48",'1'&x"3F49",'1'&x"3F4A",'1'&x"3F4B",'1'&x"3F4C",'1'&x"3F4D",'1'&x"3F4E",'1'&x"3F4F",
+--'1'&x"3F50",'1'&x"3F51",'1'&x"3F52",'1'&x"3F53",'1'&x"3F54",'1'&x"3F55",'1'&x"3F56",'1'&x"3F57",'1'&x"3F58",'1'&x"3F59",'1'&x"3F5A",'1'&x"3F5B",'1'&x"3F5C",'1'&x"3F5D",'1'&x"3F5E",'1'&x"3F5F",
+--'1'&x"3F60",'1'&x"3F61",'1'&x"3F62",'1'&x"3F63",'1'&x"3F64",'1'&x"3F65",'1'&x"3F66",'1'&x"3F67",'1'&x"3F68",'1'&x"3F69",'1'&x"3F6A",'1'&x"3F6B",'1'&x"3F6C",'1'&x"3F6D",'1'&x"3F6E",'1'&x"3F6F",
+--'1'&x"3F70",'1'&x"3F71",'1'&x"3F72",'1'&x"3F73",'1'&x"3F74",'1'&x"3F75",'1'&x"3F76",'1'&x"3F77",'1'&x"3F78",'1'&x"3F79",'1'&x"3F7A",'1'&x"3F7B",'1'&x"3F7C",'1'&x"3F7D",'1'&x"3F7E",'1'&x"3F7F",
+--'1'&x"3F80",'1'&x"3F81",'1'&x"3F82",'1'&x"3F83",'1'&x"3F84",'1'&x"3F85",'1'&x"3F86",'1'&x"3F87",'1'&x"3F88",'1'&x"3F89",'1'&x"3F8A",'1'&x"3F8B",'1'&x"3F8C",'1'&x"3F8D",'1'&x"3F8E",'1'&x"3F8F",
+--'1'&x"3F90",'1'&x"3F91",'1'&x"3F92",'1'&x"3F93",'1'&x"3F94",'1'&x"3F95",'1'&x"3F96",'1'&x"3F97",'1'&x"3F98",'1'&x"3F99",'1'&x"3F9A",'1'&x"3F9B",'1'&x"3F9C",'1'&x"3F9D",'1'&x"3F9E",'1'&x"3F9F",
+--'1'&x"3FA0",'1'&x"3FA1",'1'&x"3FA2",'1'&x"3FA3",'1'&x"3FA4",'1'&x"3FA5",'1'&x"3FA6",'1'&x"3FA7",'1'&x"3FA8",'1'&x"3FA9",'1'&x"3FAA",'1'&x"3FAB",'1'&x"3FAC",'1'&x"3FAD",'1'&x"3FAE",'1'&x"3FAF",
+--'1'&x"3FB0",'1'&x"3FB1",'1'&x"3FB2",'1'&x"3FB3",'1'&x"3FB4",'1'&x"3FB5",'1'&x"3FB6",'1'&x"3FB7",'1'&x"3FB8",'1'&x"3FB9",'1'&x"3FBA",'1'&x"3FBB",'1'&x"3FBC",'1'&x"3FBD",'1'&x"3FBE",'1'&x"3FBF",
+--'1'&x"3FC0",'1'&x"3FC1",'1'&x"3FC2",'1'&x"3FC3",'1'&x"3FC4",'1'&x"3FC5",'1'&x"3FC6",'1'&x"3FC7",'1'&x"3FC8",'1'&x"3FC9",'1'&x"3FCA",'1'&x"3FCB",'1'&x"3FCC",'1'&x"3FCD",'1'&x"3FCE",'1'&x"3FCF",
+--'1'&x"3FD0",'1'&x"3FD1",'1'&x"3FD2",'1'&x"3FD3",'1'&x"3FD4",'1'&x"3FD5",'1'&x"3FD6",'1'&x"3FD7",'1'&x"3FD8",'1'&x"3FD9",'1'&x"3FDA",'1'&x"3FDB",'1'&x"3FDC",'1'&x"3FDD",'1'&x"3FDE",'1'&x"3FDF",
+--'1'&x"3FE0",'1'&x"3FE1",'1'&x"3FE2",'1'&x"3FE3",'1'&x"3FE4",'1'&x"3FE5",'1'&x"3FE6",'1'&x"3FE7",'1'&x"3FE8",'1'&x"3FE9",'1'&x"3FEA",'1'&x"3FEB",'1'&x"3FEC",'1'&x"3FED",'1'&x"3FEE",'1'&x"3FEF",
+--'1'&x"3FF0",'1'&x"3FF1",'1'&x"3FF2",'1'&x"3FF3",'1'&x"3FF4",'1'&x"3FF5",'1'&x"3FF6",'1'&x"3FF7",'1'&x"3FF8",'1'&x"3FF9",'1'&x"3FFA",'1'&x"3FFB",'1'&x"3FFC",'1'&x"3FFD",'1'&x"3FFE",'1'&x"3FFF",
+--'1'&x"4000",'1'&x"4001",'1'&x"4002",'1'&x"4003",'1'&x"4004",'1'&x"4005",'1'&x"4006",'1'&x"4007",'1'&x"4008",'1'&x"4009",'1'&x"400A",'1'&x"400B",'1'&x"400C",'1'&x"400D",'1'&x"400E",'1'&x"400F",
+--'1'&x"4010",'1'&x"4011",'1'&x"4012",'1'&x"4013",'1'&x"4014",'1'&x"4015",'1'&x"4016",'1'&x"4017",'1'&x"4018",'1'&x"4019",'1'&x"401A",'1'&x"401B",'1'&x"401C",'1'&x"401D",'1'&x"401E",'1'&x"401F",
+--'1'&x"4020",'1'&x"4021",'1'&x"4022",'1'&x"4023",'1'&x"4024",'1'&x"4025",'1'&x"4026",'1'&x"4027",'1'&x"4028",'1'&x"4029",'1'&x"402A",'1'&x"402B",'1'&x"402C",'1'&x"402D",'1'&x"402E",'1'&x"402F",
+--'1'&x"4030",'1'&x"4031",'1'&x"4032",'1'&x"4033",'1'&x"4034",'1'&x"4035",'1'&x"4036",'1'&x"4037",'1'&x"4038",'1'&x"4039",'1'&x"403A",'1'&x"403B",'1'&x"403C",'1'&x"403D",'1'&x"403E",'1'&x"403F",
+--'1'&x"4040",'1'&x"4041",'1'&x"4042",'1'&x"4043",'1'&x"4044",'1'&x"4045",'1'&x"4046",'1'&x"4047",'1'&x"4048",'1'&x"4049",'1'&x"404A",'1'&x"404B",'1'&x"404C",'1'&x"404D",'1'&x"404E",'1'&x"404F",
+--'1'&x"4050",'1'&x"4051",'1'&x"4052",'1'&x"4053",'1'&x"4054",'1'&x"4055",'1'&x"4056",'1'&x"4057",'1'&x"4058",'1'&x"4059",'1'&x"405A",'1'&x"405B",'1'&x"405C",'1'&x"405D",'1'&x"405E",'1'&x"405F",
+--'1'&x"4060",'1'&x"4061",'1'&x"4062",'1'&x"4063",'1'&x"4064",'1'&x"4065",'1'&x"4066",'1'&x"4067",'1'&x"4068",'1'&x"4069",'1'&x"406A",'1'&x"406B",'1'&x"406C",'1'&x"406D",'1'&x"406E",'1'&x"406F",
+--'1'&x"4070",'1'&x"4071",'1'&x"4072",'1'&x"4073",'1'&x"4074",'1'&x"4075",'1'&x"4076",'1'&x"4077",'1'&x"4078",'1'&x"4079",'1'&x"407A",'1'&x"407B",'1'&x"407C",'1'&x"407D",'1'&x"407E",'1'&x"407F",
+--'1'&x"4080",'1'&x"4081",'1'&x"4082",'1'&x"4083",'1'&x"4084",'1'&x"4085",'1'&x"4086",'1'&x"4087",'1'&x"4088",'1'&x"4089",'1'&x"408A",'1'&x"408B",'1'&x"408C",'1'&x"408D",'1'&x"408E",'1'&x"408F",
+--'1'&x"4090",'1'&x"4091",'1'&x"4092",'1'&x"4093",'1'&x"4094",'1'&x"4095",'1'&x"4096",'1'&x"4097",'1'&x"4098",'1'&x"4099",'1'&x"409A",'1'&x"409B",'1'&x"409C",'1'&x"409D",'1'&x"409E",'1'&x"409F",
+--'1'&x"40A0",'1'&x"40A1",'1'&x"40A2",'1'&x"40A3",'1'&x"40A4",'1'&x"40A5",'1'&x"40A6",'1'&x"40A7",'1'&x"40A8",'1'&x"40A9",'1'&x"40AA",'1'&x"40AB",'1'&x"40AC",'1'&x"40AD",'1'&x"40AE",'1'&x"40AF",
+--'1'&x"40B0",'1'&x"40B1",'1'&x"40B2",'1'&x"40B3",'1'&x"40B4",'1'&x"40B5",'1'&x"40B6",'1'&x"40B7",'1'&x"40B8",'1'&x"40B9",'1'&x"40BA",'1'&x"40BB",'1'&x"40BC",'1'&x"40BD",'1'&x"40BE",'1'&x"40BF",
+--'1'&x"40C0",'1'&x"40C1",'1'&x"40C2",'1'&x"40C3",'1'&x"40C4",'1'&x"40C5",'1'&x"40C6",'1'&x"40C7",'1'&x"40C8",'1'&x"40C9",'1'&x"40CA",'1'&x"40CB",'1'&x"40CC",'1'&x"40CD",'1'&x"40CE",'1'&x"40CF",
+--'1'&x"40D0",'1'&x"40D1",'1'&x"40D2",'1'&x"40D3",'1'&x"40D4",'1'&x"40D5",'1'&x"40D6",'1'&x"40D7",'1'&x"40D8",'1'&x"40D9",'1'&x"40DA",'1'&x"40DB",'1'&x"40DC",'1'&x"40DD",'1'&x"40DE",'1'&x"40DF",
+--'1'&x"40E0",'1'&x"40E1",'1'&x"40E2",'1'&x"40E3",'1'&x"40E4",'1'&x"40E5",'1'&x"40E6",'1'&x"40E7",'1'&x"40E8",'1'&x"40E9",'1'&x"40EA",'1'&x"40EB",'1'&x"40EC",'1'&x"40ED",'1'&x"40EE",'1'&x"40EF",
+--'1'&x"40F0",'1'&x"40F1",'1'&x"40F2",'1'&x"40F3",'1'&x"40F4",'1'&x"40F5",'1'&x"40F6",'1'&x"40F7",'1'&x"40F8",'1'&x"40F9",'1'&x"40FA",'1'&x"40FB",'1'&x"40FC",'1'&x"40FD",'1'&x"40FE",'1'&x"40FF",
+--'1'&x"4100",'1'&x"4101",'1'&x"4102",'1'&x"4103",'1'&x"4104",'1'&x"4105",'1'&x"4106",'1'&x"4107",'1'&x"4108",'1'&x"4109",'1'&x"410A",'1'&x"410B",'1'&x"410C",'1'&x"410D",'1'&x"410E",'1'&x"410F",
+--'1'&x"4110",'1'&x"4111",'1'&x"4112",'1'&x"4113",'1'&x"4114",'1'&x"4115",'1'&x"4116",'1'&x"4117",'1'&x"4118",'1'&x"4119",'1'&x"411A",'1'&x"411B",'1'&x"411C",'1'&x"411D",'1'&x"411E",'1'&x"411F",
+--'1'&x"4120",'1'&x"4121",'1'&x"4122",'1'&x"4123",'1'&x"4124",'1'&x"4125",'1'&x"4126",'1'&x"4127",'1'&x"4128",'1'&x"4129",'1'&x"412A",'1'&x"412B",'1'&x"412C",'1'&x"412D",'1'&x"412E",'1'&x"412F",
+--'1'&x"4130",'1'&x"4131",'1'&x"4132",'1'&x"4133",'1'&x"4134",'1'&x"4135",'1'&x"4136",'1'&x"4137",'1'&x"4138",'1'&x"4139",'1'&x"413A",'1'&x"413B",'1'&x"413C",'1'&x"413D",'1'&x"413E",'1'&x"413F",
+--'1'&x"4140",'1'&x"4141",'1'&x"4142",'1'&x"4143",'1'&x"4144",'1'&x"4145",'1'&x"4146",'1'&x"4147",'1'&x"4148",'1'&x"4149",'1'&x"414A",'1'&x"414B",'1'&x"414C",'1'&x"414D",'1'&x"414E",'1'&x"414F",
+--'1'&x"4150",'1'&x"4151",'1'&x"4152",'1'&x"4153",'1'&x"4154",'1'&x"4155",'1'&x"4156",'1'&x"4157",'1'&x"4158",'1'&x"4159",'1'&x"415A",'1'&x"415B",'1'&x"415C",'1'&x"415D",'1'&x"415E",'1'&x"415F",
+--'1'&x"4160",'1'&x"4161",'1'&x"4162",'1'&x"4163",'1'&x"4164",'1'&x"4165",'1'&x"4166",'1'&x"4167",'1'&x"4168",'1'&x"4169",'1'&x"416A",'1'&x"416B",'1'&x"416C",'1'&x"416D",'1'&x"416E",'1'&x"416F",
+--'1'&x"4170",'1'&x"4171",'1'&x"4172",'1'&x"4173",'1'&x"4174",'1'&x"4175",'1'&x"4176",'1'&x"4177",'1'&x"4178",'1'&x"4179",'1'&x"417A",'1'&x"417B",'1'&x"417C",'1'&x"417D",'1'&x"417E",'1'&x"417F",
+--'1'&x"4180",'1'&x"4181",'1'&x"4182",'1'&x"4183",'1'&x"4184",'1'&x"4185",'1'&x"4186",'1'&x"4187",'1'&x"4188",'1'&x"4189",'1'&x"418A",'1'&x"418B",'1'&x"418C",'1'&x"418D",'1'&x"418E",'1'&x"418F",
+--'1'&x"4190",'1'&x"4191",'1'&x"4192",'1'&x"4193",'1'&x"4194",'1'&x"4195",'1'&x"4196",'1'&x"4197",'1'&x"4198",'1'&x"4199",'1'&x"419A",'1'&x"419B",'1'&x"419C",'1'&x"419D",'1'&x"419E",'1'&x"419F",
+--'1'&x"41A0",'1'&x"41A1",'1'&x"41A2",'1'&x"41A3",'1'&x"41A4",'1'&x"41A5",'1'&x"41A6",'1'&x"41A7",'1'&x"41A8",'1'&x"41A9",'1'&x"41AA",'1'&x"41AB",'1'&x"41AC",'1'&x"41AD",'1'&x"41AE",'1'&x"41AF",
+--'1'&x"41B0",'1'&x"41B1",'1'&x"41B2",'1'&x"41B3",'1'&x"41B4",'1'&x"41B5",'1'&x"41B6",'1'&x"41B7",'1'&x"41B8",'1'&x"41B9",'1'&x"41BA",'1'&x"41BB",'1'&x"41BC",'1'&x"41BD",'1'&x"41BE",'1'&x"41BF",
+--'1'&x"41C0",'1'&x"41C1",'1'&x"41C2",'1'&x"41C3",'1'&x"41C4",'1'&x"41C5",'1'&x"41C6",'1'&x"41C7",'1'&x"41C8",'1'&x"41C9",'1'&x"41CA",'1'&x"41CB",'1'&x"41CC",'1'&x"41CD",'1'&x"41CE",'1'&x"41CF",
+--'1'&x"41D0",'1'&x"41D1",'1'&x"41D2",'1'&x"41D3",'1'&x"41D4",'1'&x"41D5",'1'&x"41D6",'1'&x"41D7",'1'&x"41D8",'1'&x"41D9",'1'&x"41DA",'1'&x"41DB",'1'&x"41DC",'1'&x"41DD",'1'&x"41DE",'1'&x"41DF",
+--'1'&x"41E0",'1'&x"41E1",'1'&x"41E2",'1'&x"41E3",'1'&x"41E4",'1'&x"41E5",'1'&x"41E6",'1'&x"41E7",'1'&x"41E8",'1'&x"41E9",'1'&x"41EA",'1'&x"41EB",'1'&x"41EC",'1'&x"41ED",'1'&x"41EE",'1'&x"41EF",
+--'1'&x"41F0",'1'&x"41F1",'1'&x"41F2",'1'&x"41F3",'1'&x"41F4",'1'&x"41F5",'1'&x"41F6",'1'&x"41F7",'1'&x"41F8",'1'&x"41F9",'1'&x"41FA",'1'&x"41FB",'1'&x"41FC",'1'&x"41FD",'1'&x"41FE",'1'&x"41FF",
+--'1'&x"4200",'1'&x"4201",'1'&x"4202",'1'&x"4203",'1'&x"4204",'1'&x"4205",'1'&x"4206",'1'&x"4207",'1'&x"4208",'1'&x"4209",'1'&x"420A",'1'&x"420B",'1'&x"420C",'1'&x"420D",'1'&x"420E",'1'&x"420F",
+--'1'&x"4210",'1'&x"4211",'1'&x"4212",'1'&x"4213",'1'&x"4214",'1'&x"4215",'1'&x"4216",'1'&x"4217",'1'&x"4218",'1'&x"4219",'1'&x"421A",'1'&x"421B",'1'&x"421C",'1'&x"421D",'1'&x"421E",'1'&x"421F",
+--'1'&x"4220",'1'&x"4221",'1'&x"4222",'1'&x"4223",'1'&x"4224",'1'&x"4225",'1'&x"4226",'1'&x"4227",'1'&x"4228",'1'&x"4229",'1'&x"422A",'1'&x"422B",'1'&x"422C",'1'&x"422D",'1'&x"422E",'1'&x"422F",
+--'1'&x"4230",'1'&x"4231",'1'&x"4232",'1'&x"4233",'1'&x"4234",'1'&x"4235",'1'&x"4236",'1'&x"4237",'1'&x"4238",'1'&x"4239",'1'&x"423A",'1'&x"423B",'1'&x"423C",'1'&x"423D",'1'&x"423E",'1'&x"423F",
+--'1'&x"4240",'1'&x"4241",'1'&x"4242",'1'&x"4243",'1'&x"4244",'1'&x"4245",'1'&x"4246",'1'&x"4247",'1'&x"4248",'1'&x"4249",'1'&x"424A",'1'&x"424B",'1'&x"424C",'1'&x"424D",'1'&x"424E",'1'&x"424F",
+--'1'&x"4250",'1'&x"4251",'1'&x"4252",'1'&x"4253",'1'&x"4254",'1'&x"4255",'1'&x"4256",'1'&x"4257",'1'&x"4258",'1'&x"4259",'1'&x"425A",'1'&x"425B",'1'&x"425C",'1'&x"425D",'1'&x"425E",'1'&x"425F",
+--'1'&x"4260",'1'&x"4261",'1'&x"4262",'1'&x"4263",'1'&x"4264",'1'&x"4265",'1'&x"4266",'1'&x"4267",'1'&x"4268",'1'&x"4269",'1'&x"426A",'1'&x"426B",'1'&x"426C",'1'&x"426D",'1'&x"426E",'1'&x"426F",
+--'1'&x"4270",'1'&x"4271",'1'&x"4272",'1'&x"4273",'1'&x"4274",'1'&x"4275",'1'&x"4276",'1'&x"4277",'1'&x"4278",'1'&x"4279",'1'&x"427A",'1'&x"427B",'1'&x"427C",'1'&x"427D",'1'&x"427E",'1'&x"427F",
+--'1'&x"4280",'1'&x"4281",'1'&x"4282",'1'&x"4283",'1'&x"4284",'1'&x"4285",'1'&x"4286",'1'&x"4287",'1'&x"4288",'1'&x"4289",'1'&x"428A",'1'&x"428B",'1'&x"428C",'1'&x"428D",'1'&x"428E",'1'&x"428F",
+--'1'&x"4290",'1'&x"4291",'1'&x"4292",'1'&x"4293",'1'&x"4294",'1'&x"4295",'1'&x"4296",'1'&x"4297",'1'&x"4298",'1'&x"4299",'1'&x"429A",'1'&x"429B",'1'&x"429C",'1'&x"429D",'1'&x"429E",'1'&x"429F",
+--'1'&x"42A0",'1'&x"42A1",'1'&x"42A2",'1'&x"42A3",'1'&x"42A4",'1'&x"42A5",'1'&x"42A6",'1'&x"42A7",'1'&x"42A8",'1'&x"42A9",'1'&x"42AA",'1'&x"42AB",'1'&x"42AC",'1'&x"42AD",'1'&x"42AE",'1'&x"42AF",
+--'1'&x"42B0",'1'&x"42B1",'1'&x"42B2",'1'&x"42B3",'1'&x"42B4",'1'&x"42B5",'1'&x"42B6",'1'&x"42B7",'1'&x"42B8",'1'&x"42B9",'1'&x"42BA",'1'&x"42BB",'1'&x"42BC",'1'&x"42BD",'1'&x"42BE",'1'&x"42BF",
+--'1'&x"42C0",'1'&x"42C1",'1'&x"42C2",'1'&x"42C3",'1'&x"42C4",'1'&x"42C5",'1'&x"42C6",'1'&x"42C7",'1'&x"42C8",'1'&x"42C9",'1'&x"42CA",'1'&x"42CB",'1'&x"42CC",'1'&x"42CD",'1'&x"42CE",'1'&x"42CF",
+--'1'&x"42D0",'1'&x"42D1",'1'&x"42D2",'1'&x"42D3",'1'&x"42D4",'1'&x"42D5",'1'&x"42D6",'1'&x"42D7",'1'&x"42D8",'1'&x"42D9",'1'&x"42DA",'1'&x"42DB",'1'&x"42DC",'1'&x"42DD",'1'&x"42DE",'1'&x"42DF",
+--'1'&x"42E0",'1'&x"42E1",'1'&x"42E2",'1'&x"42E3",'1'&x"42E4",'1'&x"42E5",'1'&x"42E6",'1'&x"42E7",'1'&x"42E8",'1'&x"42E9",'1'&x"42EA",'1'&x"42EB",'1'&x"42EC",'1'&x"42ED",'1'&x"42EE",'1'&x"42EF",
+--'1'&x"42F0",'1'&x"42F1",'1'&x"42F2",'1'&x"42F3",'1'&x"42F4",'1'&x"42F5",'1'&x"42F6",'1'&x"42F7",'1'&x"42F8",'1'&x"42F9",'1'&x"42FA",'1'&x"42FB",'1'&x"42FC",'1'&x"42FD",'1'&x"42FE",'1'&x"42FF",
+--'1'&x"4300",'1'&x"4301",'1'&x"4302",'1'&x"4303",'1'&x"4304",'1'&x"4305",'1'&x"4306",'1'&x"4307",'1'&x"4308",'1'&x"4309",'1'&x"430A",'1'&x"430B",'1'&x"430C",'1'&x"430D",'1'&x"430E",'1'&x"430F",
+--'1'&x"4310",'1'&x"4311",'1'&x"4312",'1'&x"4313",'1'&x"4314",'1'&x"4315",'1'&x"4316",'1'&x"4317",'1'&x"4318",'1'&x"4319",'1'&x"431A",'1'&x"431B",'1'&x"431C",'1'&x"431D",'1'&x"431E",'1'&x"431F",
+--'1'&x"4320",'1'&x"4321",'1'&x"4322",'1'&x"4323",'1'&x"4324",'1'&x"4325",'1'&x"4326",'1'&x"4327",'1'&x"4328",'1'&x"4329",'1'&x"432A",'1'&x"432B",'1'&x"432C",'1'&x"432D",'1'&x"432E",'1'&x"432F",
+--'1'&x"4330",'1'&x"4331",'1'&x"4332",'1'&x"4333",'1'&x"4334",'1'&x"4335",'1'&x"4336",'1'&x"4337",'1'&x"4338",'1'&x"4339",'1'&x"433A",'1'&x"433B",'1'&x"433C",'1'&x"433D",'1'&x"433E",'1'&x"433F",
+--'1'&x"4340",'1'&x"4341",'1'&x"4342",'1'&x"4343",'1'&x"4344",'1'&x"4345",'1'&x"4346",'1'&x"4347",'1'&x"4348",'1'&x"4349",'1'&x"434A",'1'&x"434B",'1'&x"434C",'1'&x"434D",'1'&x"434E",'1'&x"434F",
+--'1'&x"4350",'1'&x"4351",'1'&x"4352",'1'&x"4353",'1'&x"4354",'1'&x"4355",'1'&x"4356",'1'&x"4357",'1'&x"4358",'1'&x"4359",'1'&x"435A",'1'&x"435B",'1'&x"435C",'1'&x"435D",'1'&x"435E",'1'&x"435F",
+--'1'&x"4360",'1'&x"4361",'1'&x"4362",'1'&x"4363",'1'&x"4364",'1'&x"4365",'1'&x"4366",'1'&x"4367",'1'&x"4368",'1'&x"4369",'1'&x"436A",'1'&x"436B",'1'&x"436C",'1'&x"436D",'1'&x"436E",'1'&x"436F",
+--'1'&x"4370",'1'&x"4371",'1'&x"4372",'1'&x"4373",'1'&x"4374",'1'&x"4375",'1'&x"4376",'1'&x"4377",'1'&x"4378",'1'&x"4379",'1'&x"437A",'1'&x"437B",'1'&x"437C",'1'&x"437D",'1'&x"437E",'1'&x"437F",
+--'1'&x"4380",'1'&x"4381",'1'&x"4382",'1'&x"4383",'1'&x"4384",'1'&x"4385",'1'&x"4386",'1'&x"4387",'1'&x"4388",'1'&x"4389",'1'&x"438A",'1'&x"438B",'1'&x"438C",'1'&x"438D",'1'&x"438E",'1'&x"438F",
+--'1'&x"4390",'1'&x"4391",'1'&x"4392",'1'&x"4393",'1'&x"4394",'1'&x"4395",'1'&x"4396",'1'&x"4397",'1'&x"4398",'1'&x"4399",'1'&x"439A",'1'&x"439B",'1'&x"439C",'1'&x"439D",'1'&x"439E",'1'&x"439F",
+--'1'&x"43A0",'1'&x"43A1",'1'&x"43A2",'1'&x"43A3",'1'&x"43A4",'1'&x"43A5",'1'&x"43A6",'1'&x"43A7",'1'&x"43A8",'1'&x"43A9",'1'&x"43AA",'1'&x"43AB",'1'&x"43AC",'1'&x"43AD",'1'&x"43AE",'1'&x"43AF",
+--'1'&x"43B0",'1'&x"43B1",'1'&x"43B2",'1'&x"43B3",'1'&x"43B4",'1'&x"43B5",'1'&x"43B6",'1'&x"43B7",'1'&x"43B8",'1'&x"43B9",'1'&x"43BA",'1'&x"43BB",'1'&x"43BC",'1'&x"43BD",'1'&x"43BE",'1'&x"43BF",
+--'1'&x"43C0",'1'&x"43C1",'1'&x"43C2",'1'&x"43C3",'1'&x"43C4",'1'&x"43C5",'1'&x"43C6",'1'&x"43C7",'1'&x"43C8",'1'&x"43C9",'1'&x"43CA",'1'&x"43CB",'1'&x"43CC",'1'&x"43CD",'1'&x"43CE",'1'&x"43CF",
+--'1'&x"43D0",'1'&x"43D1",'1'&x"43D2",'1'&x"43D3",'1'&x"43D4",'1'&x"43D5",'1'&x"43D6",'1'&x"43D7",'1'&x"43D8",'1'&x"43D9",'1'&x"43DA",'1'&x"43DB",'1'&x"43DC",'1'&x"43DD",'1'&x"43DE",'1'&x"43DF",
+--'1'&x"43E0",'1'&x"43E1",'1'&x"43E2",'1'&x"43E3",'1'&x"43E4",'1'&x"43E5",'1'&x"43E6",'1'&x"43E7",'1'&x"43E8",'1'&x"43E9",'1'&x"43EA",'1'&x"43EB",'1'&x"43EC",'1'&x"43ED",'1'&x"43EE",'1'&x"43EF",
+--'1'&x"43F0",'1'&x"43F1",'1'&x"43F2",'1'&x"43F3",'1'&x"43F4",'1'&x"43F5",'1'&x"43F6",'1'&x"43F7",'1'&x"43F8",'1'&x"43F9",'1'&x"43FA",'1'&x"43FB",'1'&x"43FC",'1'&x"43FD",'1'&x"43FE",'1'&x"43FF",
+--'1'&x"4400",'1'&x"4401",'1'&x"4402",'1'&x"4403",'1'&x"4404",'1'&x"4405",'1'&x"4406",'1'&x"4407",'1'&x"4408",'1'&x"4409",'1'&x"440A",'1'&x"440B",'1'&x"440C",'1'&x"440D",'1'&x"440E",'1'&x"440F",
+--'1'&x"4410",'1'&x"4411",'1'&x"4412",'1'&x"4413",'1'&x"4414",'1'&x"4415",'1'&x"4416",'1'&x"4417",'1'&x"4418",'1'&x"4419",'1'&x"441A",'1'&x"441B",'1'&x"441C",'1'&x"441D",'1'&x"441E",'1'&x"441F",
+--'1'&x"4420",'1'&x"4421",'1'&x"4422",'1'&x"4423",'1'&x"4424",'1'&x"4425",'1'&x"4426",'1'&x"4427",'1'&x"4428",'1'&x"4429",'1'&x"442A",'1'&x"442B",'1'&x"442C",'1'&x"442D",'1'&x"442E",'1'&x"442F",
+--'1'&x"4430",'1'&x"4431",'1'&x"4432",'1'&x"4433",'1'&x"4434",'1'&x"4435",'1'&x"4436",'1'&x"4437",'1'&x"4438",'1'&x"4439",'1'&x"443A",'1'&x"443B",'1'&x"443C",'1'&x"443D",'1'&x"443E",'1'&x"443F",
+--'1'&x"4440",'1'&x"4441",'1'&x"4442",'1'&x"4443",'1'&x"4444",'1'&x"4445",'1'&x"4446",'1'&x"4447",'1'&x"4448",'1'&x"4449",'1'&x"444A",'1'&x"444B",'1'&x"444C",'1'&x"444D",'1'&x"444E",'1'&x"444F",
+--'1'&x"4450",'1'&x"4451",'1'&x"4452",'1'&x"4453",'1'&x"4454",'1'&x"4455",'1'&x"4456",'1'&x"4457",'1'&x"4458",'1'&x"4459",'1'&x"445A",'1'&x"445B",'1'&x"445C",'1'&x"445D",'1'&x"445E",'1'&x"445F",
+--'1'&x"4460",'1'&x"4461",'1'&x"4462",'1'&x"4463",'1'&x"4464",'1'&x"4465",'1'&x"4466",'1'&x"4467",'1'&x"4468",'1'&x"4469",'1'&x"446A",'1'&x"446B",'1'&x"446C",'1'&x"446D",'1'&x"446E",'1'&x"446F",
+--'1'&x"4470",'1'&x"4471",'1'&x"4472",'1'&x"4473",'1'&x"4474",'1'&x"4475",'1'&x"4476",'1'&x"4477",'1'&x"4478",'1'&x"4479",'1'&x"447A",'1'&x"447B",'1'&x"447C",'1'&x"447D",'1'&x"447E",'1'&x"447F",
+--'1'&x"4480",'1'&x"4481",'1'&x"4482",'1'&x"4483",'1'&x"4484",'1'&x"4485",'1'&x"4486",'1'&x"4487",'1'&x"4488",'1'&x"4489",'1'&x"448A",'1'&x"448B",'1'&x"448C",'1'&x"448D",'1'&x"448E",'1'&x"448F",
+--'1'&x"4490",'1'&x"4491",'1'&x"4492",'1'&x"4493",'1'&x"4494",'1'&x"4495",'1'&x"4496",'1'&x"4497",'1'&x"4498",'1'&x"4499",'1'&x"449A",'1'&x"449B",'1'&x"449C",'1'&x"449D",'1'&x"449E",'1'&x"449F",
+--'1'&x"44A0",'1'&x"44A1",'1'&x"44A2",'1'&x"44A3",'1'&x"44A4",'1'&x"44A5",'1'&x"44A6",'1'&x"44A7",'1'&x"44A8",'1'&x"44A9",'1'&x"44AA",'1'&x"44AB",'1'&x"44AC",'1'&x"44AD",'1'&x"44AE",'1'&x"44AF",
+--'1'&x"44B0",'1'&x"44B1",'1'&x"44B2",'1'&x"44B3",'1'&x"44B4",'1'&x"44B5",'1'&x"44B6",'1'&x"44B7",'1'&x"44B8",'1'&x"44B9",'1'&x"44BA",'1'&x"44BB",'1'&x"44BC",'1'&x"44BD",'1'&x"44BE",'1'&x"44BF",
+--'1'&x"44C0",'1'&x"44C1",'1'&x"44C2",'1'&x"44C3",'1'&x"44C4",'1'&x"44C5",'1'&x"44C6",'1'&x"44C7",'1'&x"44C8",'1'&x"44C9",'1'&x"44CA",'1'&x"44CB",'1'&x"44CC",'1'&x"44CD",'1'&x"44CE",'1'&x"44CF",
+--'1'&x"44D0",'1'&x"44D1",'1'&x"44D2",'1'&x"44D3",'1'&x"44D4",'1'&x"44D5",'1'&x"44D6",'1'&x"44D7",'1'&x"44D8",'1'&x"44D9",'1'&x"44DA",'1'&x"44DB",'1'&x"44DC",'1'&x"44DD",'1'&x"44DE",'1'&x"44DF",
+--'1'&x"44E0",'1'&x"44E1",'1'&x"44E2",'1'&x"44E3",'1'&x"44E4",'1'&x"44E5",'1'&x"44E6",'1'&x"44E7",'1'&x"44E8",'1'&x"44E9",'1'&x"44EA",'1'&x"44EB",'1'&x"44EC",'1'&x"44ED",'1'&x"44EE",'1'&x"44EF",
+--'1'&x"44F0",'1'&x"44F1",'1'&x"44F2",'1'&x"44F3",'1'&x"44F4",'1'&x"44F5",'1'&x"44F6",'1'&x"44F7",'1'&x"44F8",'1'&x"44F9",'1'&x"44FA",'1'&x"44FB",'1'&x"44FC",'1'&x"44FD",'1'&x"44FE",'1'&x"44FF",
+--'1'&x"4500",'1'&x"4501",'1'&x"4502",'1'&x"4503",'1'&x"4504",'1'&x"4505",'1'&x"4506",'1'&x"4507",'1'&x"4508",'1'&x"4509",'1'&x"450A",'1'&x"450B",'1'&x"450C",'1'&x"450D",'1'&x"450E",'1'&x"450F",
+--'1'&x"4510",'1'&x"4511",'1'&x"4512",'1'&x"4513",'1'&x"4514",'1'&x"4515",'1'&x"4516",'1'&x"4517",'1'&x"4518",'1'&x"4519",'1'&x"451A",'1'&x"451B",'1'&x"451C",'1'&x"451D",'1'&x"451E",'1'&x"451F",
+--'1'&x"4520",'1'&x"4521",'1'&x"4522",'1'&x"4523",'1'&x"4524",'1'&x"4525",'1'&x"4526",'1'&x"4527",'1'&x"4528",'1'&x"4529",'1'&x"452A",'1'&x"452B",'1'&x"452C",'1'&x"452D",'1'&x"452E",'1'&x"452F",
+--'1'&x"4530",'1'&x"4531",'1'&x"4532",'1'&x"4533",'1'&x"4534",'1'&x"4535",'1'&x"4536",'1'&x"4537",'1'&x"4538",'1'&x"4539",'1'&x"453A",'1'&x"453B",'1'&x"453C",'1'&x"453D",'1'&x"453E",'1'&x"453F",
+--'1'&x"4540",'1'&x"4541",'1'&x"4542",'1'&x"4543",'1'&x"4544",'1'&x"4545",'1'&x"4546",'1'&x"4547",'1'&x"4548",'1'&x"4549",'1'&x"454A",'1'&x"454B",'1'&x"454C",'1'&x"454D",'1'&x"454E",'1'&x"454F",
+--'1'&x"4550",'1'&x"4551",'1'&x"4552",'1'&x"4553",'1'&x"4554",'1'&x"4555",'1'&x"4556",'1'&x"4557",'1'&x"4558",'1'&x"4559",'1'&x"455A",'1'&x"455B",'1'&x"455C",'1'&x"455D",'1'&x"455E",'1'&x"455F",
+--'1'&x"4560",'1'&x"4561",'1'&x"4562",'1'&x"4563",'1'&x"4564",'1'&x"4565",'1'&x"4566",'1'&x"4567",'1'&x"4568",'1'&x"4569",'1'&x"456A",'1'&x"456B",'1'&x"456C",'1'&x"456D",'1'&x"456E",'1'&x"456F",
+--'1'&x"4570",'1'&x"4571",'1'&x"4572",'1'&x"4573",'1'&x"4574",'1'&x"4575",'1'&x"4576",'1'&x"4577",'1'&x"4578",'1'&x"4579",'1'&x"457A",'1'&x"457B",'1'&x"457C",'1'&x"457D",'1'&x"457E",'1'&x"457F",
+--'1'&x"4580",'1'&x"4581",'1'&x"4582",'1'&x"4583",'1'&x"4584",'1'&x"4585",'1'&x"4586",'1'&x"4587",'1'&x"4588",'1'&x"4589",'1'&x"458A",'1'&x"458B",'1'&x"458C",'1'&x"458D",'1'&x"458E",'1'&x"458F",
+--'1'&x"4590",'1'&x"4591",'1'&x"4592",'1'&x"4593",'1'&x"4594",'1'&x"4595",'1'&x"4596",'1'&x"4597",'1'&x"4598",'1'&x"4599",'1'&x"459A",'1'&x"459B",'1'&x"459C",'1'&x"459D",'1'&x"459E",'1'&x"459F",
+--'1'&x"45A0",'1'&x"45A1",'1'&x"45A2",'1'&x"45A3",'1'&x"45A4",'1'&x"45A5",'1'&x"45A6",'1'&x"45A7",'1'&x"45A8",'1'&x"45A9",'1'&x"45AA",'1'&x"45AB",'1'&x"45AC",'1'&x"45AD",'1'&x"45AE",'1'&x"45AF",
+--'1'&x"45B0",'1'&x"45B1",'1'&x"45B2",'1'&x"45B3",'1'&x"45B4",'1'&x"45B5",'1'&x"45B6",'1'&x"45B7",'1'&x"45B8",'1'&x"45B9",'1'&x"45BA",'1'&x"45BB",'1'&x"45BC",'1'&x"45BD",'1'&x"45BE",'1'&x"45BF",
+--'1'&x"45C0",'1'&x"45C1",'1'&x"45C2",'1'&x"45C3",'1'&x"45C4",'1'&x"45C5",'1'&x"45C6",'1'&x"45C7",'1'&x"45C8",'1'&x"45C9",'1'&x"45CA",'1'&x"45CB",'1'&x"45CC",'1'&x"45CD",'1'&x"45CE",'1'&x"45CF",
+--'1'&x"45D0",'1'&x"45D1",'1'&x"45D2",'1'&x"45D3",'1'&x"45D4",'1'&x"45D5",'1'&x"45D6",'1'&x"45D7",'1'&x"45D8",'1'&x"45D9",'1'&x"45DA",'1'&x"45DB",'1'&x"45DC",'1'&x"45DD",'1'&x"45DE",'1'&x"45DF",
+--'1'&x"45E0",'1'&x"45E1",'1'&x"45E2",'1'&x"45E3",'1'&x"45E4",'1'&x"45E5",'1'&x"45E6",'1'&x"45E7",'1'&x"45E8",'1'&x"45E9",'1'&x"45EA",'1'&x"45EB",'1'&x"45EC",'1'&x"45ED",'1'&x"45EE",'1'&x"45EF",
+--'1'&x"45F0",'1'&x"45F1",'1'&x"45F2",'1'&x"45F3",'1'&x"45F4",'1'&x"45F5",'1'&x"45F6",'1'&x"45F7",'1'&x"45F8",'1'&x"45F9",'1'&x"45FA",'1'&x"45FB",'1'&x"45FC",'1'&x"45FD",'1'&x"45FE",'1'&x"45FF",
+--'1'&x"4600",'1'&x"4601",'1'&x"4602",'1'&x"4603",'1'&x"4604",'1'&x"4605",'1'&x"4606",'1'&x"4607",'1'&x"4608",'1'&x"4609",'1'&x"460A",'1'&x"460B",'1'&x"460C",'1'&x"460D",'1'&x"460E",'1'&x"460F",
+--'1'&x"4610",'1'&x"4611",'1'&x"4612",'1'&x"4613",'1'&x"4614",'1'&x"4615",'1'&x"4616",'1'&x"4617",'1'&x"4618",'1'&x"4619",'1'&x"461A",'1'&x"461B",'1'&x"461C",'1'&x"461D",'1'&x"461E",'1'&x"461F",
+--'1'&x"4620",'1'&x"4621",'1'&x"4622",'1'&x"4623",'1'&x"4624",'1'&x"4625",'1'&x"4626",'1'&x"4627",'1'&x"4628",'1'&x"4629",'1'&x"462A",'1'&x"462B",'1'&x"462C",'1'&x"462D",'1'&x"462E",'1'&x"462F",
+--'1'&x"4630",'1'&x"4631",'1'&x"4632",'1'&x"4633",'1'&x"4634",'1'&x"4635",'1'&x"4636",'1'&x"4637",'1'&x"4638",'1'&x"4639",'1'&x"463A",'1'&x"463B",'1'&x"463C",'1'&x"463D",'1'&x"463E",'1'&x"463F",
+--'1'&x"4640",'1'&x"4641",'1'&x"4642",'1'&x"4643",'1'&x"4644",'1'&x"4645",'1'&x"4646",'1'&x"4647",'1'&x"4648",'1'&x"4649",'1'&x"464A",'1'&x"464B",'1'&x"464C",'1'&x"464D",'1'&x"464E",'1'&x"464F",
+--'1'&x"4650",'1'&x"4651",'1'&x"4652",'1'&x"4653",'1'&x"4654",'1'&x"4655",'1'&x"4656",'1'&x"4657",'1'&x"4658",'1'&x"4659",'1'&x"465A",'1'&x"465B",'1'&x"465C",'1'&x"465D",'1'&x"465E",'1'&x"465F",
+--'1'&x"4660",'1'&x"4661",'1'&x"4662",'1'&x"4663",'1'&x"4664",'1'&x"4665",'1'&x"4666",'1'&x"4667",'1'&x"4668",'1'&x"4669",'1'&x"466A",'1'&x"466B",'1'&x"466C",'1'&x"466D",'1'&x"466E",'1'&x"466F",
+--'1'&x"4670",'1'&x"4671",'1'&x"4672",'1'&x"4673",'1'&x"4674",'1'&x"4675",'1'&x"4676",'1'&x"4677",'1'&x"4678",'1'&x"4679",'1'&x"467A",'1'&x"467B",'1'&x"467C",'1'&x"467D",'1'&x"467E",'1'&x"467F",
+--'1'&x"4680",'1'&x"4681",'1'&x"4682",'1'&x"4683",'1'&x"4684",'1'&x"4685",'1'&x"4686",'1'&x"4687",'1'&x"4688",'1'&x"4689",'1'&x"468A",'1'&x"468B",'1'&x"468C",'1'&x"468D",'1'&x"468E",'1'&x"468F",
+--'1'&x"4690",'1'&x"4691",'1'&x"4692",'1'&x"4693",'1'&x"4694",'1'&x"4695",'1'&x"4696",'1'&x"4697",'1'&x"4698",'1'&x"4699",'1'&x"469A",'1'&x"469B",'1'&x"469C",'1'&x"469D",'1'&x"469E",'1'&x"469F",
+--'1'&x"46A0",'1'&x"46A1",'1'&x"46A2",'1'&x"46A3",'1'&x"46A4",'1'&x"46A5",'1'&x"46A6",'1'&x"46A7",'1'&x"46A8",'1'&x"46A9",'1'&x"46AA",'1'&x"46AB",'1'&x"46AC",'1'&x"46AD",'1'&x"46AE",'1'&x"46AF",
+--'1'&x"46B0",'1'&x"46B1",'1'&x"46B2",'1'&x"46B3",'1'&x"46B4",'1'&x"46B5",'1'&x"46B6",'1'&x"46B7",'1'&x"46B8",'1'&x"46B9",'1'&x"46BA",'1'&x"46BB",'1'&x"46BC",'1'&x"46BD",'1'&x"46BE",'1'&x"46BF",
+--'1'&x"46C0",'1'&x"46C1",'1'&x"46C2",'1'&x"46C3",'1'&x"46C4",'1'&x"46C5",'1'&x"46C6",'1'&x"46C7",'1'&x"46C8",'1'&x"46C9",'1'&x"46CA",'1'&x"46CB",'1'&x"46CC",'1'&x"46CD",'1'&x"46CE",'1'&x"46CF",
+--'1'&x"46D0",'1'&x"46D1",'1'&x"46D2",'1'&x"46D3",'1'&x"46D4",'1'&x"46D5",'1'&x"46D6",'1'&x"46D7",'1'&x"46D8",'1'&x"46D9",'1'&x"46DA",'1'&x"46DB",'1'&x"46DC",'1'&x"46DD",'1'&x"46DE",'1'&x"46DF",
+--'1'&x"46E0",'1'&x"46E1",'1'&x"46E2",'1'&x"46E3",'1'&x"46E4",'1'&x"46E5",'1'&x"46E6",'1'&x"46E7",'1'&x"46E8",'1'&x"46E9",'1'&x"46EA",'1'&x"46EB",'1'&x"46EC",'1'&x"46ED",'1'&x"46EE",'1'&x"46EF",
+--'1'&x"46F0",'1'&x"46F1",'1'&x"46F2",'1'&x"46F3",'1'&x"46F4",'1'&x"46F5",'1'&x"46F6",'1'&x"46F7",'1'&x"46F8",'1'&x"46F9",'1'&x"46FA",'1'&x"46FB",'1'&x"46FC",'1'&x"46FD",'1'&x"46FE",'1'&x"46FF",
+--'1'&x"4700",'1'&x"4701",'1'&x"4702",'1'&x"4703",'1'&x"4704",'1'&x"4705",'1'&x"4706",'1'&x"4707",'1'&x"4708",'1'&x"4709",'1'&x"470A",'1'&x"470B",'1'&x"470C",'1'&x"470D",'1'&x"470E",'1'&x"470F",
+--'1'&x"4710",'1'&x"4711",'1'&x"4712",'1'&x"4713",'1'&x"4714",'1'&x"4715",'1'&x"4716",'1'&x"4717",'1'&x"4718",'1'&x"4719",'1'&x"471A",'1'&x"471B",'1'&x"471C",'1'&x"471D",'1'&x"471E",'1'&x"471F",
+--'1'&x"4720",'1'&x"4721",'1'&x"4722",'1'&x"4723",'1'&x"4724",'1'&x"4725",'1'&x"4726",'1'&x"4727",'1'&x"4728",'1'&x"4729",'1'&x"472A",'1'&x"472B",'1'&x"472C",'1'&x"472D",'1'&x"472E",'1'&x"472F",
+--'1'&x"4730",'1'&x"4731",'1'&x"4732",'1'&x"4733",'1'&x"4734",'1'&x"4735",'1'&x"4736",'1'&x"4737",'1'&x"4738",'1'&x"4739",'1'&x"473A",'1'&x"473B",'1'&x"473C",'1'&x"473D",'1'&x"473E",'1'&x"473F",
+--'1'&x"4740",'1'&x"4741",'1'&x"4742",'1'&x"4743",'1'&x"4744",'1'&x"4745",'1'&x"4746",'1'&x"4747",'1'&x"4748",'1'&x"4749",'1'&x"474A",'1'&x"474B",'1'&x"474C",'1'&x"474D",'1'&x"474E",'1'&x"474F",
+--'1'&x"4750",'1'&x"4751",'1'&x"4752",'1'&x"4753",'1'&x"4754",'1'&x"4755",'1'&x"4756",'1'&x"4757",'1'&x"4758",'1'&x"4759",'1'&x"475A",'1'&x"475B",'1'&x"475C",'1'&x"475D",'1'&x"475E",'1'&x"475F",
+--'1'&x"4760",'1'&x"4761",'1'&x"4762",'1'&x"4763",'1'&x"4764",'1'&x"4765",'1'&x"4766",'1'&x"4767",'1'&x"4768",'1'&x"4769",'1'&x"476A",'1'&x"476B",'1'&x"476C",'1'&x"476D",'1'&x"476E",'1'&x"476F",
+--'1'&x"4770",'1'&x"4771",'1'&x"4772",'1'&x"4773",'1'&x"4774",'1'&x"4775",'1'&x"4776",'1'&x"4777",'1'&x"4778",'1'&x"4779",'1'&x"477A",'1'&x"477B",'1'&x"477C",'1'&x"477D",'1'&x"477E",'1'&x"477F",
+--'1'&x"4780",'1'&x"4781",'1'&x"4782",'1'&x"4783",'1'&x"4784",'1'&x"4785",'1'&x"4786",'1'&x"4787",'1'&x"4788",'1'&x"4789",'1'&x"478A",'1'&x"478B",'1'&x"478C",'1'&x"478D",'1'&x"478E",'1'&x"478F",
+--'1'&x"4790",'1'&x"4791",'1'&x"4792",'1'&x"4793",'1'&x"4794",'1'&x"4795",'1'&x"4796",'1'&x"4797",'1'&x"4798",'1'&x"4799",'1'&x"479A",'1'&x"479B",'1'&x"479C",'1'&x"479D",'1'&x"479E",'1'&x"479F",
+--'1'&x"47A0",'1'&x"47A1",'1'&x"47A2",'1'&x"47A3",'1'&x"47A4",'1'&x"47A5",'1'&x"47A6",'1'&x"47A7",'1'&x"47A8",'1'&x"47A9",'1'&x"47AA",'1'&x"47AB",'1'&x"47AC",'1'&x"47AD",'1'&x"47AE",'1'&x"47AF",
+--'1'&x"47B0",'1'&x"47B1",'1'&x"47B2",'1'&x"47B3",'1'&x"47B4",'1'&x"47B5",'1'&x"47B6",'1'&x"47B7",'1'&x"47B8",'1'&x"47B9",'1'&x"47BA",'1'&x"47BB",'1'&x"47BC",'1'&x"47BD",'1'&x"47BE",'1'&x"47BF",
+--'1'&x"47C0",'1'&x"47C1",'1'&x"47C2",'1'&x"47C3",'1'&x"47C4",'1'&x"47C5",'1'&x"47C6",'1'&x"47C7",'1'&x"47C8",'1'&x"47C9",'1'&x"47CA",'1'&x"47CB",'1'&x"47CC",'1'&x"47CD",'1'&x"47CE",'1'&x"47CF",
+--'1'&x"47D0",'1'&x"47D1",'1'&x"47D2",'1'&x"47D3",'1'&x"47D4",'1'&x"47D5",'1'&x"47D6",'1'&x"47D7",'1'&x"47D8",'1'&x"47D9",'1'&x"47DA",'1'&x"47DB",'1'&x"47DC",'1'&x"47DD",'1'&x"47DE",'1'&x"47DF",
+--'1'&x"47E0",'1'&x"47E1",'1'&x"47E2",'1'&x"47E3",'1'&x"47E4",'1'&x"47E5",'1'&x"47E6",'1'&x"47E7",'1'&x"47E8",'1'&x"47E9",'1'&x"47EA",'1'&x"47EB",'1'&x"47EC",'1'&x"47ED",'1'&x"47EE",'1'&x"47EF",
+--'1'&x"47F0",'1'&x"47F1",'1'&x"47F2",'1'&x"47F3",'1'&x"47F4",'1'&x"47F5",'1'&x"47F6",'1'&x"47F7",'1'&x"47F8",'1'&x"47F9",'1'&x"47FA",'1'&x"47FB",'1'&x"47FC",'1'&x"47FD",'1'&x"47FE",'1'&x"47FF",
+--'1'&x"4800",'1'&x"4801",'1'&x"4802",'1'&x"4803",'1'&x"4804",'1'&x"4805",'1'&x"4806",'1'&x"4807",'1'&x"4808",'1'&x"4809",'1'&x"480A",'1'&x"480B",'1'&x"480C",'1'&x"480D",'1'&x"480E",'1'&x"480F",
+--'1'&x"4810",'1'&x"4811",'1'&x"4812",'1'&x"4813",'1'&x"4814",'1'&x"4815",'1'&x"4816",'1'&x"4817",'1'&x"4818",'1'&x"4819",'1'&x"481A",'1'&x"481B",'1'&x"481C",'1'&x"481D",'1'&x"481E",'1'&x"481F",
+--'1'&x"4820",'1'&x"4821",'1'&x"4822",'1'&x"4823",'1'&x"4824",'1'&x"4825",'1'&x"4826",'1'&x"4827",'1'&x"4828",'1'&x"4829",'1'&x"482A",'1'&x"482B",'1'&x"482C",'1'&x"482D",'1'&x"482E",'1'&x"482F",
+--'1'&x"4830",'1'&x"4831",'1'&x"4832",'1'&x"4833",'1'&x"4834",'1'&x"4835",'1'&x"4836",'1'&x"4837",'1'&x"4838",'1'&x"4839",'1'&x"483A",'1'&x"483B",'1'&x"483C",'1'&x"483D",'1'&x"483E",'1'&x"483F",
+--'1'&x"4840",'1'&x"4841",'1'&x"4842",'1'&x"4843",'1'&x"4844",'1'&x"4845",'1'&x"4846",'1'&x"4847",'1'&x"4848",'1'&x"4849",'1'&x"484A",'1'&x"484B",'1'&x"484C",'1'&x"484D",'1'&x"484E",'1'&x"484F",
+--'1'&x"4850",'1'&x"4851",'1'&x"4852",'1'&x"4853",'1'&x"4854",'1'&x"4855",'1'&x"4856",'1'&x"4857",'1'&x"4858",'1'&x"4859",'1'&x"485A",'1'&x"485B",'1'&x"485C",'1'&x"485D",'1'&x"485E",'1'&x"485F",
+--'1'&x"4860",'1'&x"4861",'1'&x"4862",'1'&x"4863",'1'&x"4864",'1'&x"4865",'1'&x"4866",'1'&x"4867",'1'&x"4868",'1'&x"4869",'1'&x"486A",'1'&x"486B",'1'&x"486C",'1'&x"486D",'1'&x"486E",'1'&x"486F",
+--'1'&x"4870",'1'&x"4871",'1'&x"4872",'1'&x"4873",'1'&x"4874",'1'&x"4875",'1'&x"4876",'1'&x"4877",'1'&x"4878",'1'&x"4879",'1'&x"487A",'1'&x"487B",'1'&x"487C",'1'&x"487D",'1'&x"487E",'1'&x"487F",
+--'1'&x"4880",'1'&x"4881",'1'&x"4882",'1'&x"4883",'1'&x"4884",'1'&x"4885",'1'&x"4886",'1'&x"4887",'1'&x"4888",'1'&x"4889",'1'&x"488A",'1'&x"488B",'1'&x"488C",'1'&x"488D",'1'&x"488E",'1'&x"488F",
+--'1'&x"4890",'1'&x"4891",'1'&x"4892",'1'&x"4893",'1'&x"4894",'1'&x"4895",'1'&x"4896",'1'&x"4897",'1'&x"4898",'1'&x"4899",'1'&x"489A",'1'&x"489B",'1'&x"489C",'1'&x"489D",'1'&x"489E",'1'&x"489F",
+--'1'&x"48A0",'1'&x"48A1",'1'&x"48A2",'1'&x"48A3",'1'&x"48A4",'1'&x"48A5",'1'&x"48A6",'1'&x"48A7",'1'&x"48A8",'1'&x"48A9",'1'&x"48AA",'1'&x"48AB",'1'&x"48AC",'1'&x"48AD",'1'&x"48AE",'1'&x"48AF",
+--'1'&x"48B0",'1'&x"48B1",'1'&x"48B2",'1'&x"48B3",'1'&x"48B4",'1'&x"48B5",'1'&x"48B6",'1'&x"48B7",'1'&x"48B8",'1'&x"48B9",'1'&x"48BA",'1'&x"48BB",'1'&x"48BC",'1'&x"48BD",'1'&x"48BE",'1'&x"48BF",
+--'1'&x"48C0",'1'&x"48C1",'1'&x"48C2",'1'&x"48C3",'1'&x"48C4",'1'&x"48C5",'1'&x"48C6",'1'&x"48C7",'1'&x"48C8",'1'&x"48C9",'1'&x"48CA",'1'&x"48CB",'1'&x"48CC",'1'&x"48CD",'1'&x"48CE",'1'&x"48CF",
+--'1'&x"48D0",'1'&x"48D1",'1'&x"48D2",'1'&x"48D3",'1'&x"48D4",'1'&x"48D5",'1'&x"48D6",'1'&x"48D7",'1'&x"48D8",'1'&x"48D9",'1'&x"48DA",'1'&x"48DB",'1'&x"48DC",'1'&x"48DD",'1'&x"48DE",'1'&x"48DF",
+--'1'&x"48E0",'1'&x"48E1",'1'&x"48E2",'1'&x"48E3",'1'&x"48E4",'1'&x"48E5",'1'&x"48E6",'1'&x"48E7",'1'&x"48E8",'1'&x"48E9",'1'&x"48EA",'1'&x"48EB",'1'&x"48EC",'1'&x"48ED",'1'&x"48EE",'1'&x"48EF",
+--'1'&x"48F0",'1'&x"48F1",'1'&x"48F2",'1'&x"48F3",'1'&x"48F4",'1'&x"48F5",'1'&x"48F6",'1'&x"48F7",'1'&x"48F8",'1'&x"48F9",'1'&x"48FA",'1'&x"48FB",'1'&x"48FC",'1'&x"48FD",'1'&x"48FE",'1'&x"48FF",
+--'1'&x"4900",'1'&x"4901",'1'&x"4902",'1'&x"4903",'1'&x"4904",'1'&x"4905",'1'&x"4906",'1'&x"4907",'1'&x"4908",'1'&x"4909",'1'&x"490A",'1'&x"490B",'1'&x"490C",'1'&x"490D",'1'&x"490E",'1'&x"490F",
+--'1'&x"4910",'1'&x"4911",'1'&x"4912",'1'&x"4913",'1'&x"4914",'1'&x"4915",'1'&x"4916",'1'&x"4917",'1'&x"4918",'1'&x"4919",'1'&x"491A",'1'&x"491B",'1'&x"491C",'1'&x"491D",'1'&x"491E",'1'&x"491F",
+--'1'&x"4920",'1'&x"4921",'1'&x"4922",'1'&x"4923",'1'&x"4924",'1'&x"4925",'1'&x"4926",'1'&x"4927",'1'&x"4928",'1'&x"4929",'1'&x"492A",'1'&x"492B",'1'&x"492C",'1'&x"492D",'1'&x"492E",'1'&x"492F",
+--'1'&x"4930",'1'&x"4931",'1'&x"4932",'1'&x"4933",'1'&x"4934",'1'&x"4935",'1'&x"4936",'1'&x"4937",'1'&x"4938",'1'&x"4939",'1'&x"493A",'1'&x"493B",'1'&x"493C",'1'&x"493D",'1'&x"493E",'1'&x"493F",
+--'1'&x"4940",'1'&x"4941",'1'&x"4942",'1'&x"4943",'1'&x"4944",'1'&x"4945",'1'&x"4946",'1'&x"4947",'1'&x"4948",'1'&x"4949",'1'&x"494A",'1'&x"494B",'1'&x"494C",'1'&x"494D",'1'&x"494E",'1'&x"494F",
+--'1'&x"4950",'1'&x"4951",'1'&x"4952",'1'&x"4953",'1'&x"4954",'1'&x"4955",'1'&x"4956",'1'&x"4957",'1'&x"4958",'1'&x"4959",'1'&x"495A",'1'&x"495B",'1'&x"495C",'1'&x"495D",'1'&x"495E",'1'&x"495F",
+--'1'&x"4960",'1'&x"4961",'1'&x"4962",'1'&x"4963",'1'&x"4964",'1'&x"4965",'1'&x"4966",'1'&x"4967",'1'&x"4968",'1'&x"4969",'1'&x"496A",'1'&x"496B",'1'&x"496C",'1'&x"496D",'1'&x"496E",'1'&x"496F",
+--'1'&x"4970",'1'&x"4971",'1'&x"4972",'1'&x"4973",'1'&x"4974",'1'&x"4975",'1'&x"4976",'1'&x"4977",'1'&x"4978",'1'&x"4979",'1'&x"497A",'1'&x"497B",'1'&x"497C",'1'&x"497D",'1'&x"497E",'1'&x"497F",
+--'1'&x"4980",'1'&x"4981",'1'&x"4982",'1'&x"4983",'1'&x"4984",'1'&x"4985",'1'&x"4986",'1'&x"4987",'1'&x"4988",'1'&x"4989",'1'&x"498A",'1'&x"498B",'1'&x"498C",'1'&x"498D",'1'&x"498E",'1'&x"498F",
+--'1'&x"4990",'1'&x"4991",'1'&x"4992",'1'&x"4993",'1'&x"4994",'1'&x"4995",'1'&x"4996",'1'&x"4997",'1'&x"4998",'1'&x"4999",'1'&x"499A",'1'&x"499B",'1'&x"499C",'1'&x"499D",'1'&x"499E",'1'&x"499F",
+--'1'&x"49A0",'1'&x"49A1",'1'&x"49A2",'1'&x"49A3",'1'&x"49A4",'1'&x"49A5",'1'&x"49A6",'1'&x"49A7",'1'&x"49A8",'1'&x"49A9",'1'&x"49AA",'1'&x"49AB",'1'&x"49AC",'1'&x"49AD",'1'&x"49AE",'1'&x"49AF",
+--'1'&x"49B0",'1'&x"49B1",'1'&x"49B2",'1'&x"49B3",'1'&x"49B4",'1'&x"49B5",'1'&x"49B6",'1'&x"49B7",'1'&x"49B8",'1'&x"49B9",'1'&x"49BA",'1'&x"49BB",'1'&x"49BC",'1'&x"49BD",'1'&x"49BE",'1'&x"49BF",
+--'1'&x"49C0",'1'&x"49C1",'1'&x"49C2",'1'&x"49C3",'1'&x"49C4",'1'&x"49C5",'1'&x"49C6",'1'&x"49C7",'1'&x"49C8",'1'&x"49C9",'1'&x"49CA",'1'&x"49CB",'1'&x"49CC",'1'&x"49CD",'1'&x"49CE",'1'&x"49CF",
+--'1'&x"49D0",'1'&x"49D1",'1'&x"49D2",'1'&x"49D3",'1'&x"49D4",'1'&x"49D5",'1'&x"49D6",'1'&x"49D7",'1'&x"49D8",'1'&x"49D9",'1'&x"49DA",'1'&x"49DB",'1'&x"49DC",'1'&x"49DD",'1'&x"49DE",'1'&x"49DF",
+--'1'&x"49E0",'1'&x"49E1",'1'&x"49E2",'1'&x"49E3",'1'&x"49E4",'1'&x"49E5",'1'&x"49E6",'1'&x"49E7",'1'&x"49E8",'1'&x"49E9",'1'&x"49EA",'1'&x"49EB",'1'&x"49EC",'1'&x"49ED",'1'&x"49EE",'1'&x"49EF",
+--'1'&x"49F0",'1'&x"49F1",'1'&x"49F2",'1'&x"49F3",'1'&x"49F4",'1'&x"49F5",'1'&x"49F6",'1'&x"49F7",'1'&x"49F8",'1'&x"49F9",'1'&x"49FA",'1'&x"49FB",'1'&x"49FC",'1'&x"49FD",'1'&x"49FE",'1'&x"49FF",
+--'1'&x"4A00",'1'&x"4A01",'1'&x"4A02",'1'&x"4A03",'1'&x"4A04",'1'&x"4A05",'1'&x"4A06",'1'&x"4A07",'1'&x"4A08",'1'&x"4A09",'1'&x"4A0A",'1'&x"4A0B",'1'&x"4A0C",'1'&x"4A0D",'1'&x"4A0E",'1'&x"4A0F",
+--'1'&x"4A10",'1'&x"4A11",'1'&x"4A12",'1'&x"4A13",'1'&x"4A14",'1'&x"4A15",'1'&x"4A16",'1'&x"4A17",'1'&x"4A18",'1'&x"4A19",'1'&x"4A1A",'1'&x"4A1B",'1'&x"4A1C",'1'&x"4A1D",'1'&x"4A1E",'1'&x"4A1F",
+--'1'&x"4A20",'1'&x"4A21",'1'&x"4A22",'1'&x"4A23",'1'&x"4A24",'1'&x"4A25",'1'&x"4A26",'1'&x"4A27",'1'&x"4A28",'1'&x"4A29",'1'&x"4A2A",'1'&x"4A2B",'1'&x"4A2C",'1'&x"4A2D",'1'&x"4A2E",'1'&x"4A2F",
+--'1'&x"4A30",'1'&x"4A31",'1'&x"4A32",'1'&x"4A33",'1'&x"4A34",'1'&x"4A35",'1'&x"4A36",'1'&x"4A37",'1'&x"4A38",'1'&x"4A39",'1'&x"4A3A",'1'&x"4A3B",'1'&x"4A3C",'1'&x"4A3D",'1'&x"4A3E",'1'&x"4A3F",
+--'1'&x"4A40",'1'&x"4A41",'1'&x"4A42",'1'&x"4A43",'1'&x"4A44",'1'&x"4A45",'1'&x"4A46",'1'&x"4A47",'1'&x"4A48",'1'&x"4A49",'1'&x"4A4A",'1'&x"4A4B",'1'&x"4A4C",'1'&x"4A4D",'1'&x"4A4E",'1'&x"4A4F",
+--'1'&x"4A50",'1'&x"4A51",'1'&x"4A52",'1'&x"4A53",'1'&x"4A54",'1'&x"4A55",'1'&x"4A56",'1'&x"4A57",'1'&x"4A58",'1'&x"4A59",'1'&x"4A5A",'1'&x"4A5B",'1'&x"4A5C",'1'&x"4A5D",'1'&x"4A5E",'1'&x"4A5F",
+--'1'&x"4A60",'1'&x"4A61",'1'&x"4A62",'1'&x"4A63",'1'&x"4A64",'1'&x"4A65",'1'&x"4A66",'1'&x"4A67",'1'&x"4A68",'1'&x"4A69",'1'&x"4A6A",'1'&x"4A6B",'1'&x"4A6C",'1'&x"4A6D",'1'&x"4A6E",'1'&x"4A6F",
+--'1'&x"4A70",'1'&x"4A71",'1'&x"4A72",'1'&x"4A73",'1'&x"4A74",'1'&x"4A75",'1'&x"4A76",'1'&x"4A77",'1'&x"4A78",'1'&x"4A79",'1'&x"4A7A",'1'&x"4A7B",'1'&x"4A7C",'1'&x"4A7D",'1'&x"4A7E",'1'&x"4A7F",
+--'1'&x"4A80",'1'&x"4A81",'1'&x"4A82",'1'&x"4A83",'1'&x"4A84",'1'&x"4A85",'1'&x"4A86",'1'&x"4A87",'1'&x"4A88",'1'&x"4A89",'1'&x"4A8A",'1'&x"4A8B",'1'&x"4A8C",'1'&x"4A8D",'1'&x"4A8E",'1'&x"4A8F",
+--'1'&x"4A90",'1'&x"4A91",'1'&x"4A92",'1'&x"4A93",'1'&x"4A94",'1'&x"4A95",'1'&x"4A96",'1'&x"4A97",'1'&x"4A98",'1'&x"4A99",'1'&x"4A9A",'1'&x"4A9B",'1'&x"4A9C",'1'&x"4A9D",'1'&x"4A9E",'1'&x"4A9F",
+--'1'&x"4AA0",'1'&x"4AA1",'1'&x"4AA2",'1'&x"4AA3",'1'&x"4AA4",'1'&x"4AA5",'1'&x"4AA6",'1'&x"4AA7",'1'&x"4AA8",'1'&x"4AA9",'1'&x"4AAA",'1'&x"4AAB",'1'&x"4AAC",'1'&x"4AAD",'1'&x"4AAE",'1'&x"4AAF",
+--'1'&x"4AB0",'1'&x"4AB1",'1'&x"4AB2",'1'&x"4AB3",'1'&x"4AB4",'1'&x"4AB5",'1'&x"4AB6",'1'&x"4AB7",'1'&x"4AB8",'1'&x"4AB9",'1'&x"4ABA",'1'&x"4ABB",'1'&x"4ABC",'1'&x"4ABD",'1'&x"4ABE",'1'&x"4ABF",
+--'1'&x"4AC0",'1'&x"4AC1",'1'&x"4AC2",'1'&x"4AC3",'1'&x"4AC4",'1'&x"4AC5",'1'&x"4AC6",'1'&x"4AC7",'1'&x"4AC8",'1'&x"4AC9",'1'&x"4ACA",'1'&x"4ACB",'1'&x"4ACC",'1'&x"4ACD",'1'&x"4ACE",'1'&x"4ACF",
+--'1'&x"4AD0",'1'&x"4AD1",'1'&x"4AD2",'1'&x"4AD3",'1'&x"4AD4",'1'&x"4AD5",'1'&x"4AD6",'1'&x"4AD7",'1'&x"4AD8",'1'&x"4AD9",'1'&x"4ADA",'1'&x"4ADB",'1'&x"4ADC",'1'&x"4ADD",'1'&x"4ADE",'1'&x"4ADF",
+--'1'&x"4AE0",'1'&x"4AE1",'1'&x"4AE2",'1'&x"4AE3",'1'&x"4AE4",'1'&x"4AE5",'1'&x"4AE6",'1'&x"4AE7",'1'&x"4AE8",'1'&x"4AE9",'1'&x"4AEA",'1'&x"4AEB",'1'&x"4AEC",'1'&x"4AED",'1'&x"4AEE",'1'&x"4AEF",
+--'1'&x"4AF0",'1'&x"4AF1",'1'&x"4AF2",'1'&x"4AF3",'1'&x"4AF4",'1'&x"4AF5",'1'&x"4AF6",'1'&x"4AF7",'1'&x"4AF8",'1'&x"4AF9",'1'&x"4AFA",'1'&x"4AFB",'1'&x"4AFC",'1'&x"4AFD",'1'&x"4AFE",'1'&x"4AFF",
+--'1'&x"4B00",'1'&x"4B01",'1'&x"4B02",'1'&x"4B03",'1'&x"4B04",'1'&x"4B05",'1'&x"4B06",'1'&x"4B07",'1'&x"4B08",'1'&x"4B09",'1'&x"4B0A",'1'&x"4B0B",'1'&x"4B0C",'1'&x"4B0D",'1'&x"4B0E",'1'&x"4B0F",
+--'1'&x"4B10",'1'&x"4B11",'1'&x"4B12",'1'&x"4B13",'1'&x"4B14",'1'&x"4B15",'1'&x"4B16",'1'&x"4B17",'1'&x"4B18",'1'&x"4B19",'1'&x"4B1A",'1'&x"4B1B",'1'&x"4B1C",'1'&x"4B1D",'1'&x"4B1E",'1'&x"4B1F",
+--'1'&x"4B20",'1'&x"4B21",'1'&x"4B22",'1'&x"4B23",'1'&x"4B24",'1'&x"4B25",'1'&x"4B26",'1'&x"4B27",'1'&x"4B28",'1'&x"4B29",'1'&x"4B2A",'1'&x"4B2B",'1'&x"4B2C",'1'&x"4B2D",'1'&x"4B2E",'1'&x"4B2F",
+--'1'&x"4B30",'1'&x"4B31",'1'&x"4B32",'1'&x"4B33",'1'&x"4B34",'1'&x"4B35",'1'&x"4B36",'1'&x"4B37",'1'&x"4B38",'1'&x"4B39",'1'&x"4B3A",'1'&x"4B3B",'1'&x"4B3C",'1'&x"4B3D",'1'&x"4B3E",'1'&x"4B3F",
+--'1'&x"4B40",'1'&x"4B41",'1'&x"4B42",'1'&x"4B43",'1'&x"4B44",'1'&x"4B45",'1'&x"4B46",'1'&x"4B47",'1'&x"4B48",'1'&x"4B49",'1'&x"4B4A",'1'&x"4B4B",'1'&x"4B4C",'1'&x"4B4D",'1'&x"4B4E",'1'&x"4B4F",
+--'1'&x"4B50",'1'&x"4B51",'1'&x"4B52",'1'&x"4B53",'1'&x"4B54",'1'&x"4B55",'1'&x"4B56",'1'&x"4B57",'1'&x"4B58",'1'&x"4B59",'1'&x"4B5A",'1'&x"4B5B",'1'&x"4B5C",'1'&x"4B5D",'1'&x"4B5E",'1'&x"4B5F",
+--'1'&x"4B60",'1'&x"4B61",'1'&x"4B62",'1'&x"4B63",'1'&x"4B64",'1'&x"4B65",'1'&x"4B66",'1'&x"4B67",'1'&x"4B68",'1'&x"4B69",'1'&x"4B6A",'1'&x"4B6B",'1'&x"4B6C",'1'&x"4B6D",'1'&x"4B6E",'1'&x"4B6F",
+--'1'&x"4B70",'1'&x"4B71",'1'&x"4B72",'1'&x"4B73",'1'&x"4B74",'1'&x"4B75",'1'&x"4B76",'1'&x"4B77",'1'&x"4B78",'1'&x"4B79",'1'&x"4B7A",'1'&x"4B7B",'1'&x"4B7C",'1'&x"4B7D",'1'&x"4B7E",'1'&x"4B7F",
+--'1'&x"4B80",'1'&x"4B81",'1'&x"4B82",'1'&x"4B83",'1'&x"4B84",'1'&x"4B85",'1'&x"4B86",'1'&x"4B87",'1'&x"4B88",'1'&x"4B89",'1'&x"4B8A",'1'&x"4B8B",'1'&x"4B8C",'1'&x"4B8D",'1'&x"4B8E",'1'&x"4B8F",
+--'1'&x"4B90",'1'&x"4B91",'1'&x"4B92",'1'&x"4B93",'1'&x"4B94",'1'&x"4B95",'1'&x"4B96",'1'&x"4B97",'1'&x"4B98",'1'&x"4B99",'1'&x"4B9A",'1'&x"4B9B",'1'&x"4B9C",'1'&x"4B9D",'1'&x"4B9E",'1'&x"4B9F",
+--'1'&x"4BA0",'1'&x"4BA1",'1'&x"4BA2",'1'&x"4BA3",'1'&x"4BA4",'1'&x"4BA5",'1'&x"4BA6",'1'&x"4BA7",'1'&x"4BA8",'1'&x"4BA9",'1'&x"4BAA",'1'&x"4BAB",'1'&x"4BAC",'1'&x"4BAD",'1'&x"4BAE",'1'&x"4BAF",
+--'1'&x"4BB0",'1'&x"4BB1",'1'&x"4BB2",'1'&x"4BB3",'1'&x"4BB4",'1'&x"4BB5",'1'&x"4BB6",'1'&x"4BB7",'1'&x"4BB8",'1'&x"4BB9",'1'&x"4BBA",'1'&x"4BBB",'1'&x"4BBC",'1'&x"4BBD",'1'&x"4BBE",'1'&x"4BBF",
+--'1'&x"4BC0",'1'&x"4BC1",'1'&x"4BC2",'1'&x"4BC3",'1'&x"4BC4",'1'&x"4BC5",'1'&x"4BC6",'1'&x"4BC7",'1'&x"4BC8",'1'&x"4BC9",'1'&x"4BCA",'1'&x"4BCB",'1'&x"4BCC",'1'&x"4BCD",'1'&x"4BCE",'1'&x"4BCF",
+--'1'&x"4BD0",'1'&x"4BD1",'1'&x"4BD2",'1'&x"4BD3",'1'&x"4BD4",'1'&x"4BD5",'1'&x"4BD6",'1'&x"4BD7",'1'&x"4BD8",'1'&x"4BD9",'1'&x"4BDA",'1'&x"4BDB",'1'&x"4BDC",'1'&x"4BDD",'1'&x"4BDE",'1'&x"4BDF",
+--'1'&x"4BE0",'1'&x"4BE1",'1'&x"4BE2",'1'&x"4BE3",'1'&x"4BE4",'1'&x"4BE5",'1'&x"4BE6",'1'&x"4BE7",'1'&x"4BE8",'1'&x"4BE9",'1'&x"4BEA",'1'&x"4BEB",'1'&x"4BEC",'1'&x"4BED",'1'&x"4BEE",'1'&x"4BEF",
+--'1'&x"4BF0",'1'&x"4BF1",'1'&x"4BF2",'1'&x"4BF3",'1'&x"4BF4",'1'&x"4BF5",'1'&x"4BF6",'1'&x"4BF7",'1'&x"4BF8",'1'&x"4BF9",'1'&x"4BFA",'1'&x"4BFB",'1'&x"4BFC",'1'&x"4BFD",'1'&x"4BFE",'1'&x"4BFF",
+--'1'&x"4C00",'1'&x"4C01",'1'&x"4C02",'1'&x"4C03",'1'&x"4C04",'1'&x"4C05",'1'&x"4C06",'1'&x"4C07",'1'&x"4C08",'1'&x"4C09",'1'&x"4C0A",'1'&x"4C0B",'1'&x"4C0C",'1'&x"4C0D",'1'&x"4C0E",'1'&x"4C0F",
+--'1'&x"4C10",'1'&x"4C11",'1'&x"4C12",'1'&x"4C13",'1'&x"4C14",'1'&x"4C15",'1'&x"4C16",'1'&x"4C17",'1'&x"4C18",'1'&x"4C19",'1'&x"4C1A",'1'&x"4C1B",'1'&x"4C1C",'1'&x"4C1D",'1'&x"4C1E",'1'&x"4C1F",
+--'1'&x"4C20",'1'&x"4C21",'1'&x"4C22",'1'&x"4C23",'1'&x"4C24",'1'&x"4C25",'1'&x"4C26",'1'&x"4C27",'1'&x"4C28",'1'&x"4C29",'1'&x"4C2A",'1'&x"4C2B",'1'&x"4C2C",'1'&x"4C2D",'1'&x"4C2E",'1'&x"4C2F",
+--'1'&x"4C30",'1'&x"4C31",'1'&x"4C32",'1'&x"4C33",'1'&x"4C34",'1'&x"4C35",'1'&x"4C36",'1'&x"4C37",'1'&x"4C38",'1'&x"4C39",'1'&x"4C3A",'1'&x"4C3B",'1'&x"4C3C",'1'&x"4C3D",'1'&x"4C3E",'1'&x"4C3F",
+--'1'&x"4C40",'1'&x"4C41",'1'&x"4C42",'1'&x"4C43",'1'&x"4C44",'1'&x"4C45",'1'&x"4C46",'1'&x"4C47",'1'&x"4C48",'1'&x"4C49",'1'&x"4C4A",'1'&x"4C4B",'1'&x"4C4C",'1'&x"4C4D",'1'&x"4C4E",'1'&x"4C4F",
+--'1'&x"4C50",'1'&x"4C51",'1'&x"4C52",'1'&x"4C53",'1'&x"4C54",'1'&x"4C55",'1'&x"4C56",'1'&x"4C57",'1'&x"4C58",'1'&x"4C59",'1'&x"4C5A",'1'&x"4C5B",'1'&x"4C5C",'1'&x"4C5D",'1'&x"4C5E",'1'&x"4C5F",
+--'1'&x"4C60",'1'&x"4C61",'1'&x"4C62",'1'&x"4C63",'1'&x"4C64",'1'&x"4C65",'1'&x"4C66",'1'&x"4C67",'1'&x"4C68",'1'&x"4C69",'1'&x"4C6A",'1'&x"4C6B",'1'&x"4C6C",'1'&x"4C6D",'1'&x"4C6E",'1'&x"4C6F",
+--'1'&x"4C70",'1'&x"4C71",'1'&x"4C72",'1'&x"4C73",'1'&x"4C74",'1'&x"4C75",'1'&x"4C76",'1'&x"4C77",'1'&x"4C78",'1'&x"4C79",'1'&x"4C7A",'1'&x"4C7B",'1'&x"4C7C",'1'&x"4C7D",'1'&x"4C7E",'1'&x"4C7F",
+--'1'&x"4C80",'1'&x"4C81",'1'&x"4C82",'1'&x"4C83",'1'&x"4C84",'1'&x"4C85",'1'&x"4C86",'1'&x"4C87",'1'&x"4C88",'1'&x"4C89",'1'&x"4C8A",'1'&x"4C8B",'1'&x"4C8C",'1'&x"4C8D",'1'&x"4C8E",'1'&x"4C8F",
+--'1'&x"4C90",'1'&x"4C91",'1'&x"4C92",'1'&x"4C93",'1'&x"4C94",'1'&x"4C95",'1'&x"4C96",'1'&x"4C97",'1'&x"4C98",'1'&x"4C99",'1'&x"4C9A",'1'&x"4C9B",'1'&x"4C9C",'1'&x"4C9D",'1'&x"4C9E",'1'&x"4C9F",
+--'1'&x"4CA0",'1'&x"4CA1",'1'&x"4CA2",'1'&x"4CA3",'1'&x"4CA4",'1'&x"4CA5",'1'&x"4CA6",'1'&x"4CA7",'1'&x"4CA8",'1'&x"4CA9",'1'&x"4CAA",'1'&x"4CAB",'1'&x"4CAC",'1'&x"4CAD",'1'&x"4CAE",'1'&x"4CAF",
+--'1'&x"4CB0",'1'&x"4CB1",'1'&x"4CB2",'1'&x"4CB3",'1'&x"4CB4",'1'&x"4CB5",'1'&x"4CB6",'1'&x"4CB7",'1'&x"4CB8",'1'&x"4CB9",'1'&x"4CBA",'1'&x"4CBB",'1'&x"4CBC",'1'&x"4CBD",'1'&x"4CBE",'1'&x"4CBF",
+--'1'&x"4CC0",'1'&x"4CC1",'1'&x"4CC2",'1'&x"4CC3",'1'&x"4CC4",'1'&x"4CC5",'1'&x"4CC6",'1'&x"4CC7",'1'&x"4CC8",'1'&x"4CC9",'1'&x"4CCA",'1'&x"4CCB",'1'&x"4CCC",'1'&x"4CCD",'1'&x"4CCE",'1'&x"4CCF",
+--'1'&x"4CD0",'1'&x"4CD1",'1'&x"4CD2",'1'&x"4CD3",'1'&x"4CD4",'1'&x"4CD5",'1'&x"4CD6",'1'&x"4CD7",'1'&x"4CD8",'1'&x"4CD9",'1'&x"4CDA",'1'&x"4CDB",'1'&x"4CDC",'1'&x"4CDD",'1'&x"4CDE",'1'&x"4CDF",
+--'1'&x"4CE0",'1'&x"4CE1",'1'&x"4CE2",'1'&x"4CE3",'1'&x"4CE4",'1'&x"4CE5",'1'&x"4CE6",'1'&x"4CE7",'1'&x"4CE8",'1'&x"4CE9",'1'&x"4CEA",'1'&x"4CEB",'1'&x"4CEC",'1'&x"4CED",'1'&x"4CEE",'1'&x"4CEF",
+--'1'&x"4CF0",'1'&x"4CF1",'1'&x"4CF2",'1'&x"4CF3",'1'&x"4CF4",'1'&x"4CF5",'1'&x"4CF6",'1'&x"4CF7",'1'&x"4CF8",'1'&x"4CF9",'1'&x"4CFA",'1'&x"4CFB",'1'&x"4CFC",'1'&x"4CFD",'1'&x"4CFE",'1'&x"4CFF",
+--'1'&x"4D00",'1'&x"4D01",'1'&x"4D02",'1'&x"4D03",'1'&x"4D04",'1'&x"4D05",'1'&x"4D06",'1'&x"4D07",'1'&x"4D08",'1'&x"4D09",'1'&x"4D0A",'1'&x"4D0B",'1'&x"4D0C",'1'&x"4D0D",'1'&x"4D0E",'1'&x"4D0F",
+--'1'&x"4D10",'1'&x"4D11",'1'&x"4D12",'1'&x"4D13",'1'&x"4D14",'1'&x"4D15",'1'&x"4D16",'1'&x"4D17",'1'&x"4D18",'1'&x"4D19",'1'&x"4D1A",'1'&x"4D1B",'1'&x"4D1C",'1'&x"4D1D",'1'&x"4D1E",'1'&x"4D1F",
+--'1'&x"4D20",'1'&x"4D21",'1'&x"4D22",'1'&x"4D23",'1'&x"4D24",'1'&x"4D25",'1'&x"4D26",'1'&x"4D27",'1'&x"4D28",'1'&x"4D29",'1'&x"4D2A",'1'&x"4D2B",'1'&x"4D2C",'1'&x"4D2D",'1'&x"4D2E",'1'&x"4D2F",
+--'1'&x"4D30",'1'&x"4D31",'1'&x"4D32",'1'&x"4D33",'1'&x"4D34",'1'&x"4D35",'1'&x"4D36",'1'&x"4D37",'1'&x"4D38",'1'&x"4D39",'1'&x"4D3A",'1'&x"4D3B",'1'&x"4D3C",'1'&x"4D3D",'1'&x"4D3E",'1'&x"4D3F",
+--'1'&x"4D40",'1'&x"4D41",'1'&x"4D42",'1'&x"4D43",'1'&x"4D44",'1'&x"4D45",'1'&x"4D46",'1'&x"4D47",'1'&x"4D48",'1'&x"4D49",'1'&x"4D4A",'1'&x"4D4B",'1'&x"4D4C",'1'&x"4D4D",'1'&x"4D4E",'1'&x"4D4F",
+--'1'&x"4D50",'1'&x"4D51",'1'&x"4D52",'1'&x"4D53",'1'&x"4D54",'1'&x"4D55",'1'&x"4D56",'1'&x"4D57",'1'&x"4D58",'1'&x"4D59",'1'&x"4D5A",'1'&x"4D5B",'1'&x"4D5C",'1'&x"4D5D",'1'&x"4D5E",'1'&x"4D5F",
+--'1'&x"4D60",'1'&x"4D61",'1'&x"4D62",'1'&x"4D63",'1'&x"4D64",'1'&x"4D65",'1'&x"4D66",'1'&x"4D67",'1'&x"4D68",'1'&x"4D69",'1'&x"4D6A",'1'&x"4D6B",'1'&x"4D6C",'1'&x"4D6D",'1'&x"4D6E",'1'&x"4D6F",
+--'1'&x"4D70",'1'&x"4D71",'1'&x"4D72",'1'&x"4D73",'1'&x"4D74",'1'&x"4D75",'1'&x"4D76",'1'&x"4D77",'1'&x"4D78",'1'&x"4D79",'1'&x"4D7A",'1'&x"4D7B",'1'&x"4D7C",'1'&x"4D7D",'1'&x"4D7E",'1'&x"4D7F",
+--'1'&x"4D80",'1'&x"4D81",'1'&x"4D82",'1'&x"4D83",'1'&x"4D84",'1'&x"4D85",'1'&x"4D86",'1'&x"4D87",'1'&x"4D88",'1'&x"4D89",'1'&x"4D8A",'1'&x"4D8B",'1'&x"4D8C",'1'&x"4D8D",'1'&x"4D8E",'1'&x"4D8F",
+--'1'&x"4D90",'1'&x"4D91",'1'&x"4D92",'1'&x"4D93",'1'&x"4D94",'1'&x"4D95",'1'&x"4D96",'1'&x"4D97",'1'&x"4D98",'1'&x"4D99",'1'&x"4D9A",'1'&x"4D9B",'1'&x"4D9C",'1'&x"4D9D",'1'&x"4D9E",'1'&x"4D9F",
+--'1'&x"4DA0",'1'&x"4DA1",'1'&x"4DA2",'1'&x"4DA3",'1'&x"4DA4",'1'&x"4DA5",'1'&x"4DA6",'1'&x"4DA7",'1'&x"4DA8",'1'&x"4DA9",'1'&x"4DAA",'1'&x"4DAB",'1'&x"4DAC",'1'&x"4DAD",'1'&x"4DAE",'1'&x"4DAF",
+--'1'&x"4DB0",'1'&x"4DB1",'1'&x"4DB2",'1'&x"4DB3",'1'&x"4DB4",'1'&x"4DB5",'1'&x"4DB6",'1'&x"4DB7",'1'&x"4DB8",'1'&x"4DB9",'1'&x"4DBA",'1'&x"4DBB",'1'&x"4DBC",'1'&x"4DBD",'1'&x"4DBE",'1'&x"4DBF",
+--'1'&x"4DC0",'1'&x"4DC1",'1'&x"4DC2",'1'&x"4DC3",'1'&x"4DC4",'1'&x"4DC5",'1'&x"4DC6",'1'&x"4DC7",'1'&x"4DC8",'1'&x"4DC9",'1'&x"4DCA",'1'&x"4DCB",'1'&x"4DCC",'1'&x"4DCD",'1'&x"4DCE",'1'&x"4DCF",
+--'1'&x"4DD0",'1'&x"4DD1",'1'&x"4DD2",'1'&x"4DD3",'1'&x"4DD4",'1'&x"4DD5",'1'&x"4DD6",'1'&x"4DD7",'1'&x"4DD8",'1'&x"4DD9",'1'&x"4DDA",'1'&x"4DDB",'1'&x"4DDC",'1'&x"4DDD",'1'&x"4DDE",'1'&x"4DDF",
+--'1'&x"4DE0",'1'&x"4DE1",'1'&x"4DE2",'1'&x"4DE3",'1'&x"4DE4",'1'&x"4DE5",'1'&x"4DE6",'1'&x"4DE7",'1'&x"4DE8",'1'&x"4DE9",'1'&x"4DEA",'1'&x"4DEB",'1'&x"4DEC",'1'&x"4DED",'1'&x"4DEE",'1'&x"4DEF",
+--'1'&x"4DF0",'1'&x"4DF1",'1'&x"4DF2",'1'&x"4DF3",'1'&x"4DF4",'1'&x"4DF5",'1'&x"4DF6",'1'&x"4DF7",'1'&x"4DF8",'1'&x"4DF9",'1'&x"4DFA",'1'&x"4DFB",'1'&x"4DFC",'1'&x"4DFD",'1'&x"4DFE",'1'&x"4DFF",
+--'1'&x"4E00",'1'&x"4E01",'1'&x"4E02",'1'&x"4E03",'1'&x"4E04",'1'&x"4E05",'1'&x"4E06",'1'&x"4E07",'1'&x"4E08",'1'&x"4E09",'1'&x"4E0A",'1'&x"4E0B",'1'&x"4E0C",'1'&x"4E0D",'1'&x"4E0E",'1'&x"4E0F",
+--'1'&x"4E10",'1'&x"4E11",'1'&x"4E12",'1'&x"4E13",'1'&x"4E14",'1'&x"4E15",'1'&x"4E16",'1'&x"4E17",'1'&x"4E18",'1'&x"4E19",'1'&x"4E1A",'1'&x"4E1B",'1'&x"4E1C",'1'&x"4E1D",'1'&x"4E1E",'1'&x"4E1F",
+--'1'&x"4E20",'1'&x"4E21",'1'&x"4E22",'1'&x"4E23",'1'&x"4E24",'1'&x"4E25",'1'&x"4E26",'1'&x"4E27",'1'&x"4E28",'1'&x"4E29",'1'&x"4E2A",'1'&x"4E2B",'1'&x"4E2C",'1'&x"4E2D",'1'&x"4E2E",'1'&x"4E2F",
+--'1'&x"4E30",'1'&x"4E31",'1'&x"4E32",'1'&x"4E33",'1'&x"4E34",'1'&x"4E35",'1'&x"4E36",'1'&x"4E37",'1'&x"4E38",'1'&x"4E39",'1'&x"4E3A",'1'&x"4E3B",'1'&x"4E3C",'1'&x"4E3D",'1'&x"4E3E",'1'&x"4E3F",
+--'1'&x"4E40",'1'&x"4E41",'1'&x"4E42",'1'&x"4E43",'1'&x"4E44",'1'&x"4E45",'1'&x"4E46",'1'&x"4E47",'1'&x"4E48",'1'&x"4E49",'1'&x"4E4A",'1'&x"4E4B",'1'&x"4E4C",'1'&x"4E4D",'1'&x"4E4E",'1'&x"4E4F",
+--'1'&x"4E50",'1'&x"4E51",'1'&x"4E52",'1'&x"4E53",'1'&x"4E54",'1'&x"4E55",'1'&x"4E56",'1'&x"4E57",'1'&x"4E58",'1'&x"4E59",'1'&x"4E5A",'1'&x"4E5B",'1'&x"4E5C",'1'&x"4E5D",'1'&x"4E5E",'1'&x"4E5F",
+--'1'&x"4E60",'1'&x"4E61",'1'&x"4E62",'1'&x"4E63",'1'&x"4E64",'1'&x"4E65",'1'&x"4E66",'1'&x"4E67",'1'&x"4E68",'1'&x"4E69",'1'&x"4E6A",'1'&x"4E6B",'1'&x"4E6C",'1'&x"4E6D",'1'&x"4E6E",'1'&x"4E6F",
+--'1'&x"4E70",'1'&x"4E71",'1'&x"4E72",'1'&x"4E73",'1'&x"4E74",'1'&x"4E75",'1'&x"4E76",'1'&x"4E77",'1'&x"4E78",'1'&x"4E79",'1'&x"4E7A",'1'&x"4E7B",'1'&x"4E7C",'1'&x"4E7D",'1'&x"4E7E",'1'&x"4E7F",
+--'1'&x"4E80",'1'&x"4E81",'1'&x"4E82",'1'&x"4E83",'1'&x"4E84",'1'&x"4E85",'1'&x"4E86",'1'&x"4E87",'1'&x"4E88",'1'&x"4E89",'1'&x"4E8A",'1'&x"4E8B",'1'&x"4E8C",'1'&x"4E8D",'1'&x"4E8E",'1'&x"4E8F",
+--'1'&x"4E90",'1'&x"4E91",'1'&x"4E92",'1'&x"4E93",'1'&x"4E94",'1'&x"4E95",'1'&x"4E96",'1'&x"4E97",'1'&x"4E98",'1'&x"4E99",'1'&x"4E9A",'1'&x"4E9B",'1'&x"4E9C",'1'&x"4E9D",'1'&x"4E9E",'1'&x"4E9F",
+--'1'&x"4EA0",'1'&x"4EA1",'1'&x"4EA2",'1'&x"4EA3",'1'&x"4EA4",'1'&x"4EA5",'1'&x"4EA6",'1'&x"4EA7",'1'&x"4EA8",'1'&x"4EA9",'1'&x"4EAA",'1'&x"4EAB",'1'&x"4EAC",'1'&x"4EAD",'1'&x"4EAE",'1'&x"4EAF",
+--'1'&x"4EB0",'1'&x"4EB1",'1'&x"4EB2",'1'&x"4EB3",'1'&x"4EB4",'1'&x"4EB5",'1'&x"4EB6",'1'&x"4EB7",'1'&x"4EB8",'1'&x"4EB9",'1'&x"4EBA",'1'&x"4EBB",'1'&x"4EBC",'1'&x"4EBD",'1'&x"4EBE",'1'&x"4EBF",
+--'1'&x"4EC0",'1'&x"4EC1",'1'&x"4EC2",'1'&x"4EC3",'1'&x"4EC4",'1'&x"4EC5",'1'&x"4EC6",'1'&x"4EC7",'1'&x"4EC8",'1'&x"4EC9",'1'&x"4ECA",'1'&x"4ECB",'1'&x"4ECC",'1'&x"4ECD",'1'&x"4ECE",'1'&x"4ECF",
+--'1'&x"4ED0",'1'&x"4ED1",'1'&x"4ED2",'1'&x"4ED3",'1'&x"4ED4",'1'&x"4ED5",'1'&x"4ED6",'1'&x"4ED7",'1'&x"4ED8",'1'&x"4ED9",'1'&x"4EDA",'1'&x"4EDB",'1'&x"4EDC",'1'&x"4EDD",'1'&x"4EDE",'1'&x"4EDF",
+--'1'&x"4EE0",'1'&x"4EE1",'1'&x"4EE2",'1'&x"4EE3",'1'&x"4EE4",'1'&x"4EE5",'1'&x"4EE6",'1'&x"4EE7",'1'&x"4EE8",'1'&x"4EE9",'1'&x"4EEA",'1'&x"4EEB",'1'&x"4EEC",'1'&x"4EED",'1'&x"4EEE",'1'&x"4EEF",
+--'1'&x"4EF0",'1'&x"4EF1",'1'&x"4EF2",'1'&x"4EF3",'1'&x"4EF4",'1'&x"4EF5",'1'&x"4EF6",'1'&x"4EF7",'1'&x"4EF8",'1'&x"4EF9",'1'&x"4EFA",'1'&x"4EFB",'1'&x"4EFC",'1'&x"4EFD",'1'&x"4EFE",'1'&x"4EFF",
+--'1'&x"4F00",'1'&x"4F01",'1'&x"4F02",'1'&x"4F03",'1'&x"4F04",'1'&x"4F05",'1'&x"4F06",'1'&x"4F07",'1'&x"4F08",'1'&x"4F09",'1'&x"4F0A",'1'&x"4F0B",'1'&x"4F0C",'1'&x"4F0D",'1'&x"4F0E",'1'&x"4F0F",
+--'1'&x"4F10",'1'&x"4F11",'1'&x"4F12",'1'&x"4F13",'1'&x"4F14",'1'&x"4F15",'1'&x"4F16",'1'&x"4F17",'1'&x"4F18",'1'&x"4F19",'1'&x"4F1A",'1'&x"4F1B",'1'&x"4F1C",'1'&x"4F1D",'1'&x"4F1E",'1'&x"4F1F",
+--'1'&x"4F20",'1'&x"4F21",'1'&x"4F22",'1'&x"4F23",'1'&x"4F24",'1'&x"4F25",'1'&x"4F26",'1'&x"4F27",'1'&x"4F28",'1'&x"4F29",'1'&x"4F2A",'1'&x"4F2B",'1'&x"4F2C",'1'&x"4F2D",'1'&x"4F2E",'1'&x"4F2F",
+--'1'&x"4F30",'1'&x"4F31",'1'&x"4F32",'1'&x"4F33",'1'&x"4F34",'1'&x"4F35",'1'&x"4F36",'1'&x"4F37",'1'&x"4F38",'1'&x"4F39",'1'&x"4F3A",'1'&x"4F3B",'1'&x"4F3C",'1'&x"4F3D",'1'&x"4F3E",'1'&x"4F3F",
+--'1'&x"4F40",'1'&x"4F41",'1'&x"4F42",'1'&x"4F43",'1'&x"4F44",'1'&x"4F45",'1'&x"4F46",'1'&x"4F47",'1'&x"4F48",'1'&x"4F49",'1'&x"4F4A",'1'&x"4F4B",'1'&x"4F4C",'1'&x"4F4D",'1'&x"4F4E",'1'&x"4F4F",
+--'1'&x"4F50",'1'&x"4F51",'1'&x"4F52",'1'&x"4F53",'1'&x"4F54",'1'&x"4F55",'1'&x"4F56",'1'&x"4F57",'1'&x"4F58",'1'&x"4F59",'1'&x"4F5A",'1'&x"4F5B",'1'&x"4F5C",'1'&x"4F5D",'1'&x"4F5E",'1'&x"4F5F",
+--'1'&x"4F60",'1'&x"4F61",'1'&x"4F62",'1'&x"4F63",'1'&x"4F64",'1'&x"4F65",'1'&x"4F66",'1'&x"4F67",'1'&x"4F68",'1'&x"4F69",'1'&x"4F6A",'1'&x"4F6B",'1'&x"4F6C",'1'&x"4F6D",'1'&x"4F6E",'1'&x"4F6F",
+--'1'&x"4F70",'1'&x"4F71",'1'&x"4F72",'1'&x"4F73",'1'&x"4F74",'1'&x"4F75",'1'&x"4F76",'1'&x"4F77",'1'&x"4F78",'1'&x"4F79",'1'&x"4F7A",'1'&x"4F7B",'1'&x"4F7C",'1'&x"4F7D",'1'&x"4F7E",'1'&x"4F7F",
+--'1'&x"4F80",'1'&x"4F81",'1'&x"4F82",'1'&x"4F83",'1'&x"4F84",'1'&x"4F85",'1'&x"4F86",'1'&x"4F87",'1'&x"4F88",'1'&x"4F89",'1'&x"4F8A",'1'&x"4F8B",'1'&x"4F8C",'1'&x"4F8D",'1'&x"4F8E",'1'&x"4F8F",
+--'1'&x"4F90",'1'&x"4F91",'1'&x"4F92",'1'&x"4F93",'1'&x"4F94",'1'&x"4F95",'1'&x"4F96",'1'&x"4F97",'1'&x"4F98",'1'&x"4F99",'1'&x"4F9A",'1'&x"4F9B",'1'&x"4F9C",'1'&x"4F9D",'1'&x"4F9E",'1'&x"4F9F",
+--'1'&x"4FA0",'1'&x"4FA1",'1'&x"4FA2",'1'&x"4FA3",'1'&x"4FA4",'1'&x"4FA5",'1'&x"4FA6",'1'&x"4FA7",'1'&x"4FA8",'1'&x"4FA9",'1'&x"4FAA",'1'&x"4FAB",'1'&x"4FAC",'1'&x"4FAD",'1'&x"4FAE",'1'&x"4FAF",
+--'1'&x"4FB0",'1'&x"4FB1",'1'&x"4FB2",'1'&x"4FB3",'1'&x"4FB4",'1'&x"4FB5",'1'&x"4FB6",'1'&x"4FB7",'1'&x"4FB8",'1'&x"4FB9",'1'&x"4FBA",'1'&x"4FBB",'1'&x"4FBC",'1'&x"4FBD",'1'&x"4FBE",'1'&x"4FBF",
+--'1'&x"4FC0",'1'&x"4FC1",'1'&x"4FC2",'1'&x"4FC3",'1'&x"4FC4",'1'&x"4FC5",'1'&x"4FC6",'1'&x"4FC7",'1'&x"4FC8",'1'&x"4FC9",'1'&x"4FCA",'1'&x"4FCB",'1'&x"4FCC",'1'&x"4FCD",'1'&x"4FCE",'1'&x"4FCF",
+--'1'&x"4FD0",'1'&x"4FD1",'1'&x"4FD2",'1'&x"4FD3",'1'&x"4FD4",'1'&x"4FD5",'1'&x"4FD6",'1'&x"4FD7",'1'&x"4FD8",'1'&x"4FD9",'1'&x"4FDA",'1'&x"4FDB",'1'&x"4FDC",'1'&x"4FDD",'1'&x"4FDE",'1'&x"4FDF",
+--'1'&x"4FE0",'1'&x"4FE1",'1'&x"4FE2",'1'&x"4FE3",'1'&x"4FE4",'1'&x"4FE5",'1'&x"4FE6",'1'&x"4FE7",'1'&x"4FE8",'1'&x"4FE9",'1'&x"4FEA",'1'&x"4FEB",'1'&x"4FEC",'1'&x"4FED",'1'&x"4FEE",'1'&x"4FEF",
+--'1'&x"4FF0",'1'&x"4FF1",'1'&x"4FF2",'1'&x"4FF3",'1'&x"4FF4",'1'&x"4FF5",'1'&x"4FF6",'1'&x"4FF7",'1'&x"4FF8",'1'&x"4FF9",'1'&x"4FFA",'1'&x"4FFB",'1'&x"4FFC",'1'&x"4FFD",'1'&x"4FFE",'1'&x"4FFF",
+--'1'&x"5000",'1'&x"5001",'1'&x"5002",'1'&x"5003",'1'&x"5004",'1'&x"5005",'1'&x"5006",'1'&x"5007",'1'&x"5008",'1'&x"5009",'1'&x"500A",'1'&x"500B",'1'&x"500C",'1'&x"500D",'1'&x"500E",'1'&x"500F",
+--'1'&x"5010",'1'&x"5011",'1'&x"5012",'1'&x"5013",'1'&x"5014",'1'&x"5015",'1'&x"5016",'1'&x"5017",'1'&x"5018",'1'&x"5019",'1'&x"501A",'1'&x"501B",'1'&x"501C",'1'&x"501D",'1'&x"501E",'1'&x"501F",
+--'1'&x"5020",'1'&x"5021",'1'&x"5022",'1'&x"5023",'1'&x"5024",'1'&x"5025",'1'&x"5026",'1'&x"5027",'1'&x"5028",'1'&x"5029",'1'&x"502A",'1'&x"502B",'1'&x"502C",'1'&x"502D",'1'&x"502E",'1'&x"502F",
+--'1'&x"5030",'1'&x"5031",'1'&x"5032",'1'&x"5033",'1'&x"5034",'1'&x"5035",'1'&x"5036",'1'&x"5037",'1'&x"5038",'1'&x"5039",'1'&x"503A",'1'&x"503B",'1'&x"503C",'1'&x"503D",'1'&x"503E",'1'&x"503F",
+--'1'&x"5040",'1'&x"5041",'1'&x"5042",'1'&x"5043",'1'&x"5044",'1'&x"5045",'1'&x"5046",'1'&x"5047",'1'&x"5048",'1'&x"5049",'1'&x"504A",'1'&x"504B",'1'&x"504C",'1'&x"504D",'1'&x"504E",'1'&x"504F",
+--'1'&x"5050",'1'&x"5051",'1'&x"5052",'1'&x"5053",'1'&x"5054",'1'&x"5055",'1'&x"5056",'1'&x"5057",'1'&x"5058",'1'&x"5059",'1'&x"505A",'1'&x"505B",'1'&x"505C",'1'&x"505D",'1'&x"505E",'1'&x"505F",
+--'1'&x"5060",'1'&x"5061",'1'&x"5062",'1'&x"5063",'1'&x"5064",'1'&x"5065",'1'&x"5066",'1'&x"5067",'1'&x"5068",'1'&x"5069",'1'&x"506A",'1'&x"506B",'1'&x"506C",'1'&x"506D",'1'&x"506E",'1'&x"506F",
+--'1'&x"5070",'1'&x"5071",'1'&x"5072",'1'&x"5073",'1'&x"5074",'1'&x"5075",'1'&x"5076",'1'&x"5077",'1'&x"5078",'1'&x"5079",'1'&x"507A",'1'&x"507B",'1'&x"507C",'1'&x"507D",'1'&x"507E",'1'&x"507F",
+--'1'&x"5080",'1'&x"5081",'1'&x"5082",'1'&x"5083",'1'&x"5084",'1'&x"5085",'1'&x"5086",'1'&x"5087",'1'&x"5088",'1'&x"5089",'1'&x"508A",'1'&x"508B",'1'&x"508C",'1'&x"508D",'1'&x"508E",'1'&x"508F",
+--'1'&x"5090",'1'&x"5091",'1'&x"5092",'1'&x"5093",'1'&x"5094",'1'&x"5095",'1'&x"5096",'1'&x"5097",'1'&x"5098",'1'&x"5099",'1'&x"509A",'1'&x"509B",'1'&x"509C",'1'&x"509D",'1'&x"509E",'1'&x"509F",
+--'1'&x"50A0",'1'&x"50A1",'1'&x"50A2",'1'&x"50A3",'1'&x"50A4",'1'&x"50A5",'1'&x"50A6",'1'&x"50A7",'1'&x"50A8",'1'&x"50A9",'1'&x"50AA",'1'&x"50AB",'1'&x"50AC",'1'&x"50AD",'1'&x"50AE",'1'&x"50AF",
+--'1'&x"50B0",'1'&x"50B1",'1'&x"50B2",'1'&x"50B3",'1'&x"50B4",'1'&x"50B5",'1'&x"50B6",'1'&x"50B7",'1'&x"50B8",'1'&x"50B9",'1'&x"50BA",'1'&x"50BB",'1'&x"50BC",'1'&x"50BD",'1'&x"50BE",'1'&x"50BF",
+--'1'&x"50C0",'1'&x"50C1",'1'&x"50C2",'1'&x"50C3",'1'&x"50C4",'1'&x"50C5",'1'&x"50C6",'1'&x"50C7",'1'&x"50C8",'1'&x"50C9",'1'&x"50CA",'1'&x"50CB",'1'&x"50CC",'1'&x"50CD",'1'&x"50CE",'1'&x"50CF",
+--'1'&x"50D0",'1'&x"50D1",'1'&x"50D2",'1'&x"50D3",'1'&x"50D4",'1'&x"50D5",'1'&x"50D6",'1'&x"50D7",'1'&x"50D8",'1'&x"50D9",'1'&x"50DA",'1'&x"50DB",'1'&x"50DC",'1'&x"50DD",'1'&x"50DE",'1'&x"50DF",
+--'1'&x"50E0",'1'&x"50E1",'1'&x"50E2",'1'&x"50E3",'1'&x"50E4",'1'&x"50E5",'1'&x"50E6",'1'&x"50E7",'1'&x"50E8",'1'&x"50E9",'1'&x"50EA",'1'&x"50EB",'1'&x"50EC",'1'&x"50ED",'1'&x"50EE",'1'&x"50EF",
+--'1'&x"50F0",'1'&x"50F1",'1'&x"50F2",'1'&x"50F3",'1'&x"50F4",'1'&x"50F5",'1'&x"50F6",'1'&x"50F7",'1'&x"50F8",'1'&x"50F9",'1'&x"50FA",'1'&x"50FB",'1'&x"50FC",'1'&x"50FD",'1'&x"50FE",'1'&x"50FF",
+--'1'&x"5100",'1'&x"5101",'1'&x"5102",'1'&x"5103",'1'&x"5104",'1'&x"5105",'1'&x"5106",'1'&x"5107",'1'&x"5108",'1'&x"5109",'1'&x"510A",'1'&x"510B",'1'&x"510C",'1'&x"510D",'1'&x"510E",'1'&x"510F",
+--'1'&x"5110",'1'&x"5111",'1'&x"5112",'1'&x"5113",'1'&x"5114",'1'&x"5115",'1'&x"5116",'1'&x"5117",'1'&x"5118",'1'&x"5119",'1'&x"511A",'1'&x"511B",'1'&x"511C",'1'&x"511D",'1'&x"511E",'1'&x"511F",
+--'1'&x"5120",'1'&x"5121",'1'&x"5122",'1'&x"5123",'1'&x"5124",'1'&x"5125",'1'&x"5126",'1'&x"5127",'1'&x"5128",'1'&x"5129",'1'&x"512A",'1'&x"512B",'1'&x"512C",'1'&x"512D",'1'&x"512E",'1'&x"512F",
+--'1'&x"5130",'1'&x"5131",'1'&x"5132",'1'&x"5133",'1'&x"5134",'1'&x"5135",'1'&x"5136",'1'&x"5137",'1'&x"5138",'1'&x"5139",'1'&x"513A",'1'&x"513B",'1'&x"513C",'1'&x"513D",'1'&x"513E",'1'&x"513F",
+--'1'&x"5140",'1'&x"5141",'1'&x"5142",'1'&x"5143",'1'&x"5144",'1'&x"5145",'1'&x"5146",'1'&x"5147",'1'&x"5148",'1'&x"5149",'1'&x"514A",'1'&x"514B",'1'&x"514C",'1'&x"514D",'1'&x"514E",'1'&x"514F",
+--'1'&x"5150",'1'&x"5151",'1'&x"5152",'1'&x"5153",'1'&x"5154",'1'&x"5155",'1'&x"5156",'1'&x"5157",'1'&x"5158",'1'&x"5159",'1'&x"515A",'1'&x"515B",'1'&x"515C",'1'&x"515D",'1'&x"515E",'1'&x"515F",
+--'1'&x"5160",'1'&x"5161",'1'&x"5162",'1'&x"5163",'1'&x"5164",'1'&x"5165",'1'&x"5166",'1'&x"5167",'1'&x"5168",'1'&x"5169",'1'&x"516A",'1'&x"516B",'1'&x"516C",'1'&x"516D",'1'&x"516E",'1'&x"516F",
+--'1'&x"5170",'1'&x"5171",'1'&x"5172",'1'&x"5173",'1'&x"5174",'1'&x"5175",'1'&x"5176",'1'&x"5177",'1'&x"5178",'1'&x"5179",'1'&x"517A",'1'&x"517B",'1'&x"517C",'1'&x"517D",'1'&x"517E",'1'&x"517F",
+--'1'&x"5180",'1'&x"5181",'1'&x"5182",'1'&x"5183",'1'&x"5184",'1'&x"5185",'1'&x"5186",'1'&x"5187",'1'&x"5188",'1'&x"5189",'1'&x"518A",'1'&x"518B",'1'&x"518C",'1'&x"518D",'1'&x"518E",'1'&x"518F",
+--'1'&x"5190",'1'&x"5191",'1'&x"5192",'1'&x"5193",'1'&x"5194",'1'&x"5195",'1'&x"5196",'1'&x"5197",'1'&x"5198",'1'&x"5199",'1'&x"519A",'1'&x"519B",'1'&x"519C",'1'&x"519D",'1'&x"519E",'1'&x"519F",
+--'1'&x"51A0",'1'&x"51A1",'1'&x"51A2",'1'&x"51A3",'1'&x"51A4",'1'&x"51A5",'1'&x"51A6",'1'&x"51A7",'1'&x"51A8",'1'&x"51A9",'1'&x"51AA",'1'&x"51AB",'1'&x"51AC",'1'&x"51AD",'1'&x"51AE",'1'&x"51AF",
+--'1'&x"51B0",'1'&x"51B1",'1'&x"51B2",'1'&x"51B3",'1'&x"51B4",'1'&x"51B5",'1'&x"51B6",'1'&x"51B7",'1'&x"51B8",'1'&x"51B9",'1'&x"51BA",'1'&x"51BB",'1'&x"51BC",'1'&x"51BD",'1'&x"51BE",'1'&x"51BF",
+--'1'&x"51C0",'1'&x"51C1",'1'&x"51C2",'1'&x"51C3",'1'&x"51C4",'1'&x"51C5",'1'&x"51C6",'1'&x"51C7",'1'&x"51C8",'1'&x"51C9",'1'&x"51CA",'1'&x"51CB",'1'&x"51CC",'1'&x"51CD",'1'&x"51CE",'1'&x"51CF",
+--'1'&x"51D0",'1'&x"51D1",'1'&x"51D2",'1'&x"51D3",'1'&x"51D4",'1'&x"51D5",'1'&x"51D6",'1'&x"51D7",'1'&x"51D8",'1'&x"51D9",'1'&x"51DA",'1'&x"51DB",'1'&x"51DC",'1'&x"51DD",'1'&x"51DE",'1'&x"51DF",
+--'1'&x"51E0",'1'&x"51E1",'1'&x"51E2",'1'&x"51E3",'1'&x"51E4",'1'&x"51E5",'1'&x"51E6",'1'&x"51E7",'1'&x"51E8",'1'&x"51E9",'1'&x"51EA",'1'&x"51EB",'1'&x"51EC",'1'&x"51ED",'1'&x"51EE",'1'&x"51EF",
+--'1'&x"51F0",'1'&x"51F1",'1'&x"51F2",'1'&x"51F3",'1'&x"51F4",'1'&x"51F5",'1'&x"51F6",'1'&x"51F7",'1'&x"51F8",'1'&x"51F9",'1'&x"51FA",'1'&x"51FB",'1'&x"51FC",'1'&x"51FD",'1'&x"51FE",'1'&x"51FF",
+--'1'&x"5200",'1'&x"5201",'1'&x"5202",'1'&x"5203",'1'&x"5204",'1'&x"5205",'1'&x"5206",'1'&x"5207",'1'&x"5208",'1'&x"5209",'1'&x"520A",'1'&x"520B",'1'&x"520C",'1'&x"520D",'1'&x"520E",'1'&x"520F",
+--'1'&x"5210",'1'&x"5211",'1'&x"5212",'1'&x"5213",'1'&x"5214",'1'&x"5215",'1'&x"5216",'1'&x"5217",'1'&x"5218",'1'&x"5219",'1'&x"521A",'1'&x"521B",'1'&x"521C",'1'&x"521D",'1'&x"521E",'1'&x"521F",
+--'1'&x"5220",'1'&x"5221",'1'&x"5222",'1'&x"5223",'1'&x"5224",'1'&x"5225",'1'&x"5226",'1'&x"5227",'1'&x"5228",'1'&x"5229",'1'&x"522A",'1'&x"522B",'1'&x"522C",'1'&x"522D",'1'&x"522E",'1'&x"522F",
+--'1'&x"5230",'1'&x"5231",'1'&x"5232",'1'&x"5233",'1'&x"5234",'1'&x"5235",'1'&x"5236",'1'&x"5237",'1'&x"5238",'1'&x"5239",'1'&x"523A",'1'&x"523B",'1'&x"523C",'1'&x"523D",'1'&x"523E",'1'&x"523F",
+--'1'&x"5240",'1'&x"5241",'1'&x"5242",'1'&x"5243",'1'&x"5244",'1'&x"5245",'1'&x"5246",'1'&x"5247",'1'&x"5248",'1'&x"5249",'1'&x"524A",'1'&x"524B",'1'&x"524C",'1'&x"524D",'1'&x"524E",'1'&x"524F",
+--'1'&x"5250",'1'&x"5251",'1'&x"5252",'1'&x"5253",'1'&x"5254",'1'&x"5255",'1'&x"5256",'1'&x"5257",'1'&x"5258",'1'&x"5259",'1'&x"525A",'1'&x"525B",'1'&x"525C",'1'&x"525D",'1'&x"525E",'1'&x"525F",
+--'1'&x"5260",'1'&x"5261",'1'&x"5262",'1'&x"5263",'1'&x"5264",'1'&x"5265",'1'&x"5266",'1'&x"5267",'1'&x"5268",'1'&x"5269",'1'&x"526A",'1'&x"526B",'1'&x"526C",'1'&x"526D",'1'&x"526E",'1'&x"526F",
+--'1'&x"5270",'1'&x"5271",'1'&x"5272",'1'&x"5273",'1'&x"5274",'1'&x"5275",'1'&x"5276",'1'&x"5277",'1'&x"5278",'1'&x"5279",'1'&x"527A",'1'&x"527B",'1'&x"527C",'1'&x"527D",'1'&x"527E",'1'&x"527F",
+--'1'&x"5280",'1'&x"5281",'1'&x"5282",'1'&x"5283",'1'&x"5284",'1'&x"5285",'1'&x"5286",'1'&x"5287",'1'&x"5288",'1'&x"5289",'1'&x"528A",'1'&x"528B",'1'&x"528C",'1'&x"528D",'1'&x"528E",'1'&x"528F",
+--'1'&x"5290",'1'&x"5291",'1'&x"5292",'1'&x"5293",'1'&x"5294",'1'&x"5295",'1'&x"5296",'1'&x"5297",'1'&x"5298",'1'&x"5299",'1'&x"529A",'1'&x"529B",'1'&x"529C",'1'&x"529D",'1'&x"529E",'1'&x"529F",
+--'1'&x"52A0",'1'&x"52A1",'1'&x"52A2",'1'&x"52A3",'1'&x"52A4",'1'&x"52A5",'1'&x"52A6",'1'&x"52A7",'1'&x"52A8",'1'&x"52A9",'1'&x"52AA",'1'&x"52AB",'1'&x"52AC",'1'&x"52AD",'1'&x"52AE",'1'&x"52AF",
+--'1'&x"52B0",'1'&x"52B1",'1'&x"52B2",'1'&x"52B3",'1'&x"52B4",'1'&x"52B5",'1'&x"52B6",'1'&x"52B7",'1'&x"52B8",'1'&x"52B9",'1'&x"52BA",'1'&x"52BB",'1'&x"52BC",'1'&x"52BD",'1'&x"52BE",'1'&x"52BF",
+--'1'&x"52C0",'1'&x"52C1",'1'&x"52C2",'1'&x"52C3",'1'&x"52C4",'1'&x"52C5",'1'&x"52C6",'1'&x"52C7",'1'&x"52C8",'1'&x"52C9",'1'&x"52CA",'1'&x"52CB",'1'&x"52CC",'1'&x"52CD",'1'&x"52CE",'1'&x"52CF",
+--'1'&x"52D0",'1'&x"52D1",'1'&x"52D2",'1'&x"52D3",'1'&x"52D4",'1'&x"52D5",'1'&x"52D6",'1'&x"52D7",'1'&x"52D8",'1'&x"52D9",'1'&x"52DA",'1'&x"52DB",'1'&x"52DC",'1'&x"52DD",'1'&x"52DE",'1'&x"52DF",
+--'1'&x"52E0",'1'&x"52E1",'1'&x"52E2",'1'&x"52E3",'1'&x"52E4",'1'&x"52E5",'1'&x"52E6",'1'&x"52E7",'1'&x"52E8",'1'&x"52E9",'1'&x"52EA",'1'&x"52EB",'1'&x"52EC",'1'&x"52ED",'1'&x"52EE",'1'&x"52EF",
+--'1'&x"52F0",'1'&x"52F1",'1'&x"52F2",'1'&x"52F3",'1'&x"52F4",'1'&x"52F5",'1'&x"52F6",'1'&x"52F7",'1'&x"52F8",'1'&x"52F9",'1'&x"52FA",'1'&x"52FB",'1'&x"52FC",'1'&x"52FD",'1'&x"52FE",'1'&x"52FF",
+--'1'&x"5300",'1'&x"5301",'1'&x"5302",'1'&x"5303",'1'&x"5304",'1'&x"5305",'1'&x"5306",'1'&x"5307",'1'&x"5308",'1'&x"5309",'1'&x"530A",'1'&x"530B",'1'&x"530C",'1'&x"530D",'1'&x"530E",'1'&x"530F",
+--'1'&x"5310",'1'&x"5311",'1'&x"5312",'1'&x"5313",'1'&x"5314",'1'&x"5315",'1'&x"5316",'1'&x"5317",'1'&x"5318",'1'&x"5319",'1'&x"531A",'1'&x"531B",'1'&x"531C",'1'&x"531D",'1'&x"531E",'1'&x"531F",
+--'1'&x"5320",'1'&x"5321",'1'&x"5322",'1'&x"5323",'1'&x"5324",'1'&x"5325",'1'&x"5326",'1'&x"5327",'1'&x"5328",'1'&x"5329",'1'&x"532A",'1'&x"532B",'1'&x"532C",'1'&x"532D",'1'&x"532E",'1'&x"532F",
+--'1'&x"5330",'1'&x"5331",'1'&x"5332",'1'&x"5333",'1'&x"5334",'1'&x"5335",'1'&x"5336",'1'&x"5337",'1'&x"5338",'1'&x"5339",'1'&x"533A",'1'&x"533B",'1'&x"533C",'1'&x"533D",'1'&x"533E",'1'&x"533F",
+--'1'&x"5340",'1'&x"5341",'1'&x"5342",'1'&x"5343",'1'&x"5344",'1'&x"5345",'1'&x"5346",'1'&x"5347",'1'&x"5348",'1'&x"5349",'1'&x"534A",'1'&x"534B",'1'&x"534C",'1'&x"534D",'1'&x"534E",'1'&x"534F",
+--'1'&x"5350",'1'&x"5351",'1'&x"5352",'1'&x"5353",'1'&x"5354",'1'&x"5355",'1'&x"5356",'1'&x"5357",'1'&x"5358",'1'&x"5359",'1'&x"535A",'1'&x"535B",'1'&x"535C",'1'&x"535D",'1'&x"535E",'1'&x"535F",
+--'1'&x"5360",'1'&x"5361",'1'&x"5362",'1'&x"5363",'1'&x"5364",'1'&x"5365",'1'&x"5366",'1'&x"5367",'1'&x"5368",'1'&x"5369",'1'&x"536A",'1'&x"536B",'1'&x"536C",'1'&x"536D",'1'&x"536E",'1'&x"536F",
+--'1'&x"5370",'1'&x"5371",'1'&x"5372",'1'&x"5373",'1'&x"5374",'1'&x"5375",'1'&x"5376",'1'&x"5377",'1'&x"5378",'1'&x"5379",'1'&x"537A",'1'&x"537B",'1'&x"537C",'1'&x"537D",'1'&x"537E",'1'&x"537F",
+--'1'&x"5380",'1'&x"5381",'1'&x"5382",'1'&x"5383",'1'&x"5384",'1'&x"5385",'1'&x"5386",'1'&x"5387",'1'&x"5388",'1'&x"5389",'1'&x"538A",'1'&x"538B",'1'&x"538C",'1'&x"538D",'1'&x"538E",'1'&x"538F",
+--'1'&x"5390",'1'&x"5391",'1'&x"5392",'1'&x"5393",'1'&x"5394",'1'&x"5395",'1'&x"5396",'1'&x"5397",'1'&x"5398",'1'&x"5399",'1'&x"539A",'1'&x"539B",'1'&x"539C",'1'&x"539D",'1'&x"539E",'1'&x"539F",
+--'1'&x"53A0",'1'&x"53A1",'1'&x"53A2",'1'&x"53A3",'1'&x"53A4",'1'&x"53A5",'1'&x"53A6",'1'&x"53A7",'1'&x"53A8",'1'&x"53A9",'1'&x"53AA",'1'&x"53AB",'1'&x"53AC",'1'&x"53AD",'1'&x"53AE",'1'&x"53AF",
+--'1'&x"53B0",'1'&x"53B1",'1'&x"53B2",'1'&x"53B3",'1'&x"53B4",'1'&x"53B5",'1'&x"53B6",'1'&x"53B7",'1'&x"53B8",'1'&x"53B9",'1'&x"53BA",'1'&x"53BB",'1'&x"53BC",'1'&x"53BD",'1'&x"53BE",'1'&x"53BF",
+--'1'&x"53C0",'1'&x"53C1",'1'&x"53C2",'1'&x"53C3",'1'&x"53C4",'1'&x"53C5",'1'&x"53C6",'1'&x"53C7",'1'&x"53C8",'1'&x"53C9",'1'&x"53CA",'1'&x"53CB",'1'&x"53CC",'1'&x"53CD",'1'&x"53CE",'1'&x"53CF",
+--'1'&x"53D0",'1'&x"53D1",'1'&x"53D2",'1'&x"53D3",'1'&x"53D4",'1'&x"53D5",'1'&x"53D6",'1'&x"53D7",'1'&x"53D8",'1'&x"53D9",'1'&x"53DA",'1'&x"53DB",'1'&x"53DC",'1'&x"53DD",'1'&x"53DE",'1'&x"53DF",
+--'1'&x"53E0",'1'&x"53E1",'1'&x"53E2",'1'&x"53E3",'1'&x"53E4",'1'&x"53E5",'1'&x"53E6",'1'&x"53E7",'1'&x"53E8",'1'&x"53E9",'1'&x"53EA",'1'&x"53EB",'1'&x"53EC",'1'&x"53ED",'1'&x"53EE",'1'&x"53EF",
+--'1'&x"53F0",'1'&x"53F1",'1'&x"53F2",'1'&x"53F3",'1'&x"53F4",'1'&x"53F5",'1'&x"53F6",'1'&x"53F7",'1'&x"53F8",'1'&x"53F9",'1'&x"53FA",'1'&x"53FB",'1'&x"53FC",'1'&x"53FD",'1'&x"53FE",'1'&x"53FF",
+--'1'&x"5400",'1'&x"5401",'1'&x"5402",'1'&x"5403",'1'&x"5404",'1'&x"5405",'1'&x"5406",'1'&x"5407",'1'&x"5408",'1'&x"5409",'1'&x"540A",'1'&x"540B",'1'&x"540C",'1'&x"540D",'1'&x"540E",'1'&x"540F",
+--'1'&x"5410",'1'&x"5411",'1'&x"5412",'1'&x"5413",'1'&x"5414",'1'&x"5415",'1'&x"5416",'1'&x"5417",'1'&x"5418",'1'&x"5419",'1'&x"541A",'1'&x"541B",'1'&x"541C",'1'&x"541D",'1'&x"541E",'1'&x"541F",
+--'1'&x"5420",'1'&x"5421",'1'&x"5422",'1'&x"5423",'1'&x"5424",'1'&x"5425",'1'&x"5426",'1'&x"5427",'1'&x"5428",'1'&x"5429",'1'&x"542A",'1'&x"542B",'1'&x"542C",'1'&x"542D",'1'&x"542E",'1'&x"542F",
+--'1'&x"5430",'1'&x"5431",'1'&x"5432",'1'&x"5433",'1'&x"5434",'1'&x"5435",'1'&x"5436",'1'&x"5437",'1'&x"5438",'1'&x"5439",'1'&x"543A",'1'&x"543B",'1'&x"543C",'1'&x"543D",'1'&x"543E",'1'&x"543F",
+--'1'&x"5440",'1'&x"5441",'1'&x"5442",'1'&x"5443",'1'&x"5444",'1'&x"5445",'1'&x"5446",'1'&x"5447",'1'&x"5448",'1'&x"5449",'1'&x"544A",'1'&x"544B",'1'&x"544C",'1'&x"544D",'1'&x"544E",'1'&x"544F",
+--'1'&x"5450",'1'&x"5451",'1'&x"5452",'1'&x"5453",'1'&x"5454",'1'&x"5455",'1'&x"5456",'1'&x"5457",'1'&x"5458",'1'&x"5459",'1'&x"545A",'1'&x"545B",'1'&x"545C",'1'&x"545D",'1'&x"545E",'1'&x"545F",
+--'1'&x"5460",'1'&x"5461",'1'&x"5462",'1'&x"5463",'1'&x"5464",'1'&x"5465",'1'&x"5466",'1'&x"5467",'1'&x"5468",'1'&x"5469",'1'&x"546A",'1'&x"546B",'1'&x"546C",'1'&x"546D",'1'&x"546E",'1'&x"546F",
+--'1'&x"5470",'1'&x"5471",'1'&x"5472",'1'&x"5473",'1'&x"5474",'1'&x"5475",'1'&x"5476",'1'&x"5477",'1'&x"5478",'1'&x"5479",'1'&x"547A",'1'&x"547B",'1'&x"547C",'1'&x"547D",'1'&x"547E",'1'&x"547F",
+--'1'&x"5480",'1'&x"5481",'1'&x"5482",'1'&x"5483",'1'&x"5484",'1'&x"5485",'1'&x"5486",'1'&x"5487",'1'&x"5488",'1'&x"5489",'1'&x"548A",'1'&x"548B",'1'&x"548C",'1'&x"548D",'1'&x"548E",'1'&x"548F",
+--'1'&x"5490",'1'&x"5491",'1'&x"5492",'1'&x"5493",'1'&x"5494",'1'&x"5495",'1'&x"5496",'1'&x"5497",'1'&x"5498",'1'&x"5499",'1'&x"549A",'1'&x"549B",'1'&x"549C",'1'&x"549D",'1'&x"549E",'1'&x"549F",
+--'1'&x"54A0",'1'&x"54A1",'1'&x"54A2",'1'&x"54A3",'1'&x"54A4",'1'&x"54A5",'1'&x"54A6",'1'&x"54A7",'1'&x"54A8",'1'&x"54A9",'1'&x"54AA",'1'&x"54AB",'1'&x"54AC",'1'&x"54AD",'1'&x"54AE",'1'&x"54AF",
+--'1'&x"54B0",'1'&x"54B1",'1'&x"54B2",'1'&x"54B3",'1'&x"54B4",'1'&x"54B5",'1'&x"54B6",'1'&x"54B7",'1'&x"54B8",'1'&x"54B9",'1'&x"54BA",'1'&x"54BB",'1'&x"54BC",'1'&x"54BD",'1'&x"54BE",'1'&x"54BF",
+--'1'&x"54C0",'1'&x"54C1",'1'&x"54C2",'1'&x"54C3",'1'&x"54C4",'1'&x"54C5",'1'&x"54C6",'1'&x"54C7",'1'&x"54C8",'1'&x"54C9",'1'&x"54CA",'1'&x"54CB",'1'&x"54CC",'1'&x"54CD",'1'&x"54CE",'1'&x"54CF",
+--'1'&x"54D0",'1'&x"54D1",'1'&x"54D2",'1'&x"54D3",'1'&x"54D4",'1'&x"54D5",'1'&x"54D6",'1'&x"54D7",'1'&x"54D8",'1'&x"54D9",'1'&x"54DA",'1'&x"54DB",'1'&x"54DC",'1'&x"54DD",'1'&x"54DE",'1'&x"54DF",
+--'1'&x"54E0",'1'&x"54E1",'1'&x"54E2",'1'&x"54E3",'1'&x"54E4",'1'&x"54E5",'1'&x"54E6",'1'&x"54E7",'1'&x"54E8",'1'&x"54E9",'1'&x"54EA",'1'&x"54EB",'1'&x"54EC",'1'&x"54ED",'1'&x"54EE",'1'&x"54EF",
+--'1'&x"54F0",'1'&x"54F1",'1'&x"54F2",'1'&x"54F3",'1'&x"54F4",'1'&x"54F5",'1'&x"54F6",'1'&x"54F7",'1'&x"54F8",'1'&x"54F9",'1'&x"54FA",'1'&x"54FB",'1'&x"54FC",'1'&x"54FD",'1'&x"54FE",'1'&x"54FF",
+--'1'&x"5500",'1'&x"5501",'1'&x"5502",'1'&x"5503",'1'&x"5504",'1'&x"5505",'1'&x"5506",'1'&x"5507",'1'&x"5508",'1'&x"5509",'1'&x"550A",'1'&x"550B",'1'&x"550C",'1'&x"550D",'1'&x"550E",'1'&x"550F",
+--'1'&x"5510",'1'&x"5511",'1'&x"5512",'1'&x"5513",'1'&x"5514",'1'&x"5515",'1'&x"5516",'1'&x"5517",'1'&x"5518",'1'&x"5519",'1'&x"551A",'1'&x"551B",'1'&x"551C",'1'&x"551D",'1'&x"551E",'1'&x"551F",
+--'1'&x"5520",'1'&x"5521",'1'&x"5522",'1'&x"5523",'1'&x"5524",'1'&x"5525",'1'&x"5526",'1'&x"5527",'1'&x"5528",'1'&x"5529",'1'&x"552A",'1'&x"552B",'1'&x"552C",'1'&x"552D",'1'&x"552E",'1'&x"552F",
+--'1'&x"5530",'1'&x"5531",'1'&x"5532",'1'&x"5533",'1'&x"5534",'1'&x"5535",'1'&x"5536",'1'&x"5537",'1'&x"5538",'1'&x"5539",'1'&x"553A",'1'&x"553B",'1'&x"553C",'1'&x"553D",'1'&x"553E",'1'&x"553F",
+--'1'&x"5540",'1'&x"5541",'1'&x"5542",'1'&x"5543",'1'&x"5544",'1'&x"5545",'1'&x"5546",'1'&x"5547",'1'&x"5548",'1'&x"5549",'1'&x"554A",'1'&x"554B",'1'&x"554C",'1'&x"554D",'1'&x"554E",'1'&x"554F",
+--'1'&x"5550",'1'&x"5551",'1'&x"5552",'1'&x"5553",'1'&x"5554",'1'&x"5555",'1'&x"5556",'1'&x"5557",'1'&x"5558",'1'&x"5559",'1'&x"555A",'1'&x"555B",'1'&x"555C",'1'&x"555D",'1'&x"555E",'1'&x"555F",
+--'1'&x"5560",'1'&x"5561",'1'&x"5562",'1'&x"5563",'1'&x"5564",'1'&x"5565",'1'&x"5566",'1'&x"5567",'1'&x"5568",'1'&x"5569",'1'&x"556A",'1'&x"556B",'1'&x"556C",'1'&x"556D",'1'&x"556E",'1'&x"556F",
+--'1'&x"5570",'1'&x"5571",'1'&x"5572",'1'&x"5573",'1'&x"5574",'1'&x"5575",'1'&x"5576",'1'&x"5577",'1'&x"5578",'1'&x"5579",'1'&x"557A",'1'&x"557B",'1'&x"557C",'1'&x"557D",'1'&x"557E",'1'&x"557F",
+--'1'&x"5580",'1'&x"5581",'1'&x"5582",'1'&x"5583",'1'&x"5584",'1'&x"5585",'1'&x"5586",'1'&x"5587",'1'&x"5588",'1'&x"5589",'1'&x"558A",'1'&x"558B",'1'&x"558C",'1'&x"558D",'1'&x"558E",'1'&x"558F",
+--'1'&x"5590",'1'&x"5591",'1'&x"5592",'1'&x"5593",'1'&x"5594",'1'&x"5595",'1'&x"5596",'1'&x"5597",'1'&x"5598",'1'&x"5599",'1'&x"559A",'1'&x"559B",'1'&x"559C",'1'&x"559D",'1'&x"559E",'1'&x"559F",
+--'1'&x"55A0",'1'&x"55A1",'1'&x"55A2",'1'&x"55A3",'1'&x"55A4",'1'&x"55A5",'1'&x"55A6",'1'&x"55A7",'1'&x"55A8",'1'&x"55A9",'1'&x"55AA",'1'&x"55AB",'1'&x"55AC",'1'&x"55AD",'1'&x"55AE",'1'&x"55AF",
+--'1'&x"55B0",'1'&x"55B1",'1'&x"55B2",'1'&x"55B3",'1'&x"55B4",'1'&x"55B5",'1'&x"55B6",'1'&x"55B7",'1'&x"55B8",'1'&x"55B9",'1'&x"55BA",'1'&x"55BB",'1'&x"55BC",'1'&x"55BD",'1'&x"55BE",'1'&x"55BF",
+--'1'&x"55C0",'1'&x"55C1",'1'&x"55C2",'1'&x"55C3",'1'&x"55C4",'1'&x"55C5",'1'&x"55C6",'1'&x"55C7",'1'&x"55C8",'1'&x"55C9",'1'&x"55CA",'1'&x"55CB",'1'&x"55CC",'1'&x"55CD",'1'&x"55CE",'1'&x"55CF",
+--'1'&x"55D0",'1'&x"55D1",'1'&x"55D2",'1'&x"55D3",'1'&x"55D4",'1'&x"55D5",'1'&x"55D6",'1'&x"55D7",'1'&x"55D8",'1'&x"55D9",'1'&x"55DA",'1'&x"55DB",'1'&x"55DC",'1'&x"55DD",'1'&x"55DE",'1'&x"55DF",
+--'1'&x"55E0",'1'&x"55E1",'1'&x"55E2",'1'&x"55E3",'1'&x"55E4",'1'&x"55E5",'1'&x"55E6",'1'&x"55E7",'1'&x"55E8",'1'&x"55E9",'1'&x"55EA",'1'&x"55EB",'1'&x"55EC",'1'&x"55ED",'1'&x"55EE",'1'&x"55EF",
+--'1'&x"55F0",'1'&x"55F1",'1'&x"55F2",'1'&x"55F3",'1'&x"55F4",'1'&x"55F5",'1'&x"55F6",'1'&x"55F7",'1'&x"55F8",'1'&x"55F9",'1'&x"55FA",'1'&x"55FB",'1'&x"55FC",'1'&x"55FD",'1'&x"55FE",'1'&x"55FF",
+--'1'&x"5600",'1'&x"5601",'1'&x"5602",'1'&x"5603",'1'&x"5604",'1'&x"5605",'1'&x"5606",'1'&x"5607",'1'&x"5608",'1'&x"5609",'1'&x"560A",'1'&x"560B",'1'&x"560C",'1'&x"560D",'1'&x"560E",'1'&x"560F",
+--'1'&x"5610",'1'&x"5611",'1'&x"5612",'1'&x"5613",'1'&x"5614",'1'&x"5615",'1'&x"5616",'1'&x"5617",'1'&x"5618",'1'&x"5619",'1'&x"561A",'1'&x"561B",'1'&x"561C",'1'&x"561D",'1'&x"561E",'1'&x"561F",
+--'1'&x"5620",'1'&x"5621",'1'&x"5622",'1'&x"5623",'1'&x"5624",'1'&x"5625",'1'&x"5626",'1'&x"5627",'1'&x"5628",'1'&x"5629",'1'&x"562A",'1'&x"562B",'1'&x"562C",'1'&x"562D",'1'&x"562E",'1'&x"562F",
+--'1'&x"5630",'1'&x"5631",'1'&x"5632",'1'&x"5633",'1'&x"5634",'1'&x"5635",'1'&x"5636",'1'&x"5637",'1'&x"5638",'1'&x"5639",'1'&x"563A",'1'&x"563B",'1'&x"563C",'1'&x"563D",'1'&x"563E",'1'&x"563F",
+--'1'&x"5640",'1'&x"5641",'1'&x"5642",'1'&x"5643",'1'&x"5644",'1'&x"5645",'1'&x"5646",'1'&x"5647",'1'&x"5648",'1'&x"5649",'1'&x"564A",'1'&x"564B",'1'&x"564C",'1'&x"564D",'1'&x"564E",'1'&x"564F",
+--'1'&x"5650",'1'&x"5651",'1'&x"5652",'1'&x"5653",'1'&x"5654",'1'&x"5655",'1'&x"5656",'1'&x"5657",'1'&x"5658",'1'&x"5659",'1'&x"565A",'1'&x"565B",'1'&x"565C",'1'&x"565D",'1'&x"565E",'1'&x"565F",
+--'1'&x"5660",'1'&x"5661",'1'&x"5662",'1'&x"5663",'1'&x"5664",'1'&x"5665",'1'&x"5666",'1'&x"5667",'1'&x"5668",'1'&x"5669",'1'&x"566A",'1'&x"566B",'1'&x"566C",'1'&x"566D",'1'&x"566E",'1'&x"566F",
+--'1'&x"5670",'1'&x"5671",'1'&x"5672",'1'&x"5673",'1'&x"5674",'1'&x"5675",'1'&x"5676",'1'&x"5677",'1'&x"5678",'1'&x"5679",'1'&x"567A",'1'&x"567B",'1'&x"567C",'1'&x"567D",'1'&x"567E",'1'&x"567F",
+--'1'&x"5680",'1'&x"5681",'1'&x"5682",'1'&x"5683",'1'&x"5684",'1'&x"5685",'1'&x"5686",'1'&x"5687",'1'&x"5688",'1'&x"5689",'1'&x"568A",'1'&x"568B",'1'&x"568C",'1'&x"568D",'1'&x"568E",'1'&x"568F",
+--'1'&x"5690",'1'&x"5691",'1'&x"5692",'1'&x"5693",'1'&x"5694",'1'&x"5695",'1'&x"5696",'1'&x"5697",'1'&x"5698",'1'&x"5699",'1'&x"569A",'1'&x"569B",'1'&x"569C",'1'&x"569D",'1'&x"569E",'1'&x"569F",
+--'1'&x"56A0",'1'&x"56A1",'1'&x"56A2",'1'&x"56A3",'1'&x"56A4",'1'&x"56A5",'1'&x"56A6",'1'&x"56A7",'1'&x"56A8",'1'&x"56A9",'1'&x"56AA",'1'&x"56AB",'1'&x"56AC",'1'&x"56AD",'1'&x"56AE",'1'&x"56AF",
+--'1'&x"56B0",'1'&x"56B1",'1'&x"56B2",'1'&x"56B3",'1'&x"56B4",'1'&x"56B5",'1'&x"56B6",'1'&x"56B7",'1'&x"56B8",'1'&x"56B9",'1'&x"56BA",'1'&x"56BB",'1'&x"56BC",'1'&x"56BD",'1'&x"56BE",'1'&x"56BF",
+--'1'&x"56C0",'1'&x"56C1",'1'&x"56C2",'1'&x"56C3",'1'&x"56C4",'1'&x"56C5",'1'&x"56C6",'1'&x"56C7",'1'&x"56C8",'1'&x"56C9",'1'&x"56CA",'1'&x"56CB",'1'&x"56CC",'1'&x"56CD",'1'&x"56CE",'1'&x"56CF",
+--'1'&x"56D0",'1'&x"56D1",'1'&x"56D2",'1'&x"56D3",'1'&x"56D4",'1'&x"56D5",'1'&x"56D6",'1'&x"56D7",'1'&x"56D8",'1'&x"56D9",'1'&x"56DA",'1'&x"56DB",'1'&x"56DC",'1'&x"56DD",'1'&x"56DE",'1'&x"56DF",
+--'1'&x"56E0",'1'&x"56E1",'1'&x"56E2",'1'&x"56E3",'1'&x"56E4",'1'&x"56E5",'1'&x"56E6",'1'&x"56E7",'1'&x"56E8",'1'&x"56E9",'1'&x"56EA",'1'&x"56EB",'1'&x"56EC",'1'&x"56ED",'1'&x"56EE",'1'&x"56EF",
+--'1'&x"56F0",'1'&x"56F1",'1'&x"56F2",'1'&x"56F3",'1'&x"56F4",'1'&x"56F5",'1'&x"56F6",'1'&x"56F7",'1'&x"56F8",'1'&x"56F9",'1'&x"56FA",'1'&x"56FB",'1'&x"56FC",'1'&x"56FD",'1'&x"56FE",'1'&x"56FF",
+--'1'&x"5700",'1'&x"5701",'1'&x"5702",'1'&x"5703",'1'&x"5704",'1'&x"5705",'1'&x"5706",'1'&x"5707",'1'&x"5708",'1'&x"5709",'1'&x"570A",'1'&x"570B",'1'&x"570C",'1'&x"570D",'1'&x"570E",'1'&x"570F",
+--'1'&x"5710",'1'&x"5711",'1'&x"5712",'1'&x"5713",'1'&x"5714",'1'&x"5715",'1'&x"5716",'1'&x"5717",'1'&x"5718",'1'&x"5719",'1'&x"571A",'1'&x"571B",'1'&x"571C",'1'&x"571D",'1'&x"571E",'1'&x"571F",
+--'1'&x"5720",'1'&x"5721",'1'&x"5722",'1'&x"5723",'1'&x"5724",'1'&x"5725",'1'&x"5726",'1'&x"5727",'1'&x"5728",'1'&x"5729",'1'&x"572A",'1'&x"572B",'1'&x"572C",'1'&x"572D",'1'&x"572E",'1'&x"572F",
+--'1'&x"5730",'1'&x"5731",'1'&x"5732",'1'&x"5733",'1'&x"5734",'1'&x"5735",'1'&x"5736",'1'&x"5737",'1'&x"5738",'1'&x"5739",'1'&x"573A",'1'&x"573B",'1'&x"573C",'1'&x"573D",'1'&x"573E",'1'&x"573F",
+--'1'&x"5740",'1'&x"5741",'1'&x"5742",'1'&x"5743",'1'&x"5744",'1'&x"5745",'1'&x"5746",'1'&x"5747",'1'&x"5748",'1'&x"5749",'1'&x"574A",'1'&x"574B",'1'&x"574C",'1'&x"574D",'1'&x"574E",'1'&x"574F",
+--'1'&x"5750",'1'&x"5751",'1'&x"5752",'1'&x"5753",'1'&x"5754",'1'&x"5755",'1'&x"5756",'1'&x"5757",'1'&x"5758",'1'&x"5759",'1'&x"575A",'1'&x"575B",'1'&x"575C",'1'&x"575D",'1'&x"575E",'1'&x"575F",
+--'1'&x"5760",'1'&x"5761",'1'&x"5762",'1'&x"5763",'1'&x"5764",'1'&x"5765",'1'&x"5766",'1'&x"5767",'1'&x"5768",'1'&x"5769",'1'&x"576A",'1'&x"576B",'1'&x"576C",'1'&x"576D",'1'&x"576E",'1'&x"576F",
+--'1'&x"5770",'1'&x"5771",'1'&x"5772",'1'&x"5773",'1'&x"5774",'1'&x"5775",'1'&x"5776",'1'&x"5777",'1'&x"5778",'1'&x"5779",'1'&x"577A",'1'&x"577B",'1'&x"577C",'1'&x"577D",'1'&x"577E",'1'&x"577F",
+--'1'&x"5780",'1'&x"5781",'1'&x"5782",'1'&x"5783",'1'&x"5784",'1'&x"5785",'1'&x"5786",'1'&x"5787",'1'&x"5788",'1'&x"5789",'1'&x"578A",'1'&x"578B",'1'&x"578C",'1'&x"578D",'1'&x"578E",'1'&x"578F",
+--'1'&x"5790",'1'&x"5791",'1'&x"5792",'1'&x"5793",'1'&x"5794",'1'&x"5795",'1'&x"5796",'1'&x"5797",'1'&x"5798",'1'&x"5799",'1'&x"579A",'1'&x"579B",'1'&x"579C",'1'&x"579D",'1'&x"579E",'1'&x"579F",
+--'1'&x"57A0",'1'&x"57A1",'1'&x"57A2",'1'&x"57A3",'1'&x"57A4",'1'&x"57A5",'1'&x"57A6",'1'&x"57A7",'1'&x"57A8",'1'&x"57A9",'1'&x"57AA",'1'&x"57AB",'1'&x"57AC",'1'&x"57AD",'1'&x"57AE",'1'&x"57AF",
+--'1'&x"57B0",'1'&x"57B1",'1'&x"57B2",'1'&x"57B3",'1'&x"57B4",'1'&x"57B5",'1'&x"57B6",'1'&x"57B7",'1'&x"57B8",'1'&x"57B9",'1'&x"57BA",'1'&x"57BB",'1'&x"57BC",'1'&x"57BD",'1'&x"57BE",'1'&x"57BF",
+--'1'&x"57C0",'1'&x"57C1",'1'&x"57C2",'1'&x"57C3",'1'&x"57C4",'1'&x"57C5",'1'&x"57C6",'1'&x"57C7",'1'&x"57C8",'1'&x"57C9",'1'&x"57CA",'1'&x"57CB",'1'&x"57CC",'1'&x"57CD",'1'&x"57CE",'1'&x"57CF",
+--'1'&x"57D0",'1'&x"57D1",'1'&x"57D2",'1'&x"57D3",'1'&x"57D4",'1'&x"57D5",'1'&x"57D6",'1'&x"57D7",'1'&x"57D8",'1'&x"57D9",'1'&x"57DA",'1'&x"57DB",'1'&x"57DC",'1'&x"57DD",'1'&x"57DE",'1'&x"57DF",
+--'1'&x"57E0",'1'&x"57E1",'1'&x"57E2",'1'&x"57E3",'1'&x"57E4",'1'&x"57E5",'1'&x"57E6",'1'&x"57E7",'1'&x"57E8",'1'&x"57E9",'1'&x"57EA",'1'&x"57EB",'1'&x"57EC",'1'&x"57ED",'1'&x"57EE",'1'&x"57EF",
+--'1'&x"57F0",'1'&x"57F1",'1'&x"57F2",'1'&x"57F3",'1'&x"57F4",'1'&x"57F5",'1'&x"57F6",'1'&x"57F7",'1'&x"57F8",'1'&x"57F9",'1'&x"57FA",'1'&x"57FB",'1'&x"57FC",'1'&x"57FD",'1'&x"57FE",'1'&x"57FF",
+--'1'&x"5800",'1'&x"5801",'1'&x"5802",'1'&x"5803",'1'&x"5804",'1'&x"5805",'1'&x"5806",'1'&x"5807",'1'&x"5808",'1'&x"5809",'1'&x"580A",'1'&x"580B",'1'&x"580C",'1'&x"580D",'1'&x"580E",'1'&x"580F",
+--'1'&x"5810",'1'&x"5811",'1'&x"5812",'1'&x"5813",'1'&x"5814",'1'&x"5815",'1'&x"5816",'1'&x"5817",'1'&x"5818",'1'&x"5819",'1'&x"581A",'1'&x"581B",'1'&x"581C",'1'&x"581D",'1'&x"581E",'1'&x"581F",
+--'1'&x"5820",'1'&x"5821",'1'&x"5822",'1'&x"5823",'1'&x"5824",'1'&x"5825",'1'&x"5826",'1'&x"5827",'1'&x"5828",'1'&x"5829",'1'&x"582A",'1'&x"582B",'1'&x"582C",'1'&x"582D",'1'&x"582E",'1'&x"582F",
+--'1'&x"5830",'1'&x"5831",'1'&x"5832",'1'&x"5833",'1'&x"5834",'1'&x"5835",'1'&x"5836",'1'&x"5837",'1'&x"5838",'1'&x"5839",'1'&x"583A",'1'&x"583B",'1'&x"583C",'1'&x"583D",'1'&x"583E",'1'&x"583F",
+--'1'&x"5840",'1'&x"5841",'1'&x"5842",'1'&x"5843",'1'&x"5844",'1'&x"5845",'1'&x"5846",'1'&x"5847",'1'&x"5848",'1'&x"5849",'1'&x"584A",'1'&x"584B",'1'&x"584C",'1'&x"584D",'1'&x"584E",'1'&x"584F",
+--'1'&x"5850",'1'&x"5851",'1'&x"5852",'1'&x"5853",'1'&x"5854",'1'&x"5855",'1'&x"5856",'1'&x"5857",'1'&x"5858",'1'&x"5859",'1'&x"585A",'1'&x"585B",'1'&x"585C",'1'&x"585D",'1'&x"585E",'1'&x"585F",
+--'1'&x"5860",'1'&x"5861",'1'&x"5862",'1'&x"5863",'1'&x"5864",'1'&x"5865",'1'&x"5866",'1'&x"5867",'1'&x"5868",'1'&x"5869",'1'&x"586A",'1'&x"586B",'1'&x"586C",'1'&x"586D",'1'&x"586E",'1'&x"586F",
+--'1'&x"5870",'1'&x"5871",'1'&x"5872",'1'&x"5873",'1'&x"5874",'1'&x"5875",'1'&x"5876",'1'&x"5877",'1'&x"5878",'1'&x"5879",'1'&x"587A",'1'&x"587B",'1'&x"587C",'1'&x"587D",'1'&x"587E",'1'&x"587F",
+--'1'&x"5880",'1'&x"5881",'1'&x"5882",'1'&x"5883",'1'&x"5884",'1'&x"5885",'1'&x"5886",'1'&x"5887",'1'&x"5888",'1'&x"5889",'1'&x"588A",'1'&x"588B",'1'&x"588C",'1'&x"588D",'1'&x"588E",'1'&x"588F",
+--'1'&x"5890",'1'&x"5891",'1'&x"5892",'1'&x"5893",'1'&x"5894",'1'&x"5895",'1'&x"5896",'1'&x"5897",'1'&x"5898",'1'&x"5899",'1'&x"589A",'1'&x"589B",'1'&x"589C",'1'&x"589D",'1'&x"589E",'1'&x"589F",
+--'1'&x"58A0",'1'&x"58A1",'1'&x"58A2",'1'&x"58A3",'1'&x"58A4",'1'&x"58A5",'1'&x"58A6",'1'&x"58A7",'1'&x"58A8",'1'&x"58A9",'1'&x"58AA",'1'&x"58AB",'1'&x"58AC",'1'&x"58AD",'1'&x"58AE",'1'&x"58AF",
+--'1'&x"58B0",'1'&x"58B1",'1'&x"58B2",'1'&x"58B3",'1'&x"58B4",'1'&x"58B5",'1'&x"58B6",'1'&x"58B7",'1'&x"58B8",'1'&x"58B9",'1'&x"58BA",'1'&x"58BB",'1'&x"58BC",'1'&x"58BD",'1'&x"58BE",'1'&x"58BF",
+--'1'&x"58C0",'1'&x"58C1",'1'&x"58C2",'1'&x"58C3",'1'&x"58C4",'1'&x"58C5",'1'&x"58C6",'1'&x"58C7",'1'&x"58C8",'1'&x"58C9",'1'&x"58CA",'1'&x"58CB",'1'&x"58CC",'1'&x"58CD",'1'&x"58CE",'1'&x"58CF",
+--'1'&x"58D0",'1'&x"58D1",'1'&x"58D2",'1'&x"58D3",'1'&x"58D4",'1'&x"58D5",'1'&x"58D6",'1'&x"58D7",'1'&x"58D8",'1'&x"58D9",'1'&x"58DA",'1'&x"58DB",'1'&x"58DC",'1'&x"58DD",'1'&x"58DE",'1'&x"58DF",
+--'1'&x"58E0",'1'&x"58E1",'1'&x"58E2",'1'&x"58E3",'1'&x"58E4",'1'&x"58E5",'1'&x"58E6",'1'&x"58E7",'1'&x"58E8",'1'&x"58E9",'1'&x"58EA",'1'&x"58EB",'1'&x"58EC",'1'&x"58ED",'1'&x"58EE",'1'&x"58EF",
+--'1'&x"58F0",'1'&x"58F1",'1'&x"58F2",'1'&x"58F3",'1'&x"58F4",'1'&x"58F5",'1'&x"58F6",'1'&x"58F7",'1'&x"58F8",'1'&x"58F9",'1'&x"58FA",'1'&x"58FB",'1'&x"58FC",'1'&x"58FD",'1'&x"58FE",'1'&x"58FF",
+--'1'&x"5900",'1'&x"5901",'1'&x"5902",'1'&x"5903",'1'&x"5904",'1'&x"5905",'1'&x"5906",'1'&x"5907",'1'&x"5908",'1'&x"5909",'1'&x"590A",'1'&x"590B",'1'&x"590C",'1'&x"590D",'1'&x"590E",'1'&x"590F",
+--'1'&x"5910",'1'&x"5911",'1'&x"5912",'1'&x"5913",'1'&x"5914",'1'&x"5915",'1'&x"5916",'1'&x"5917",'1'&x"5918",'1'&x"5919",'1'&x"591A",'1'&x"591B",'1'&x"591C",'1'&x"591D",'1'&x"591E",'1'&x"591F",
+--'1'&x"5920",'1'&x"5921",'1'&x"5922",'1'&x"5923",'1'&x"5924",'1'&x"5925",'1'&x"5926",'1'&x"5927",'1'&x"5928",'1'&x"5929",'1'&x"592A",'1'&x"592B",'1'&x"592C",'1'&x"592D",'1'&x"592E",'1'&x"592F",
+--'1'&x"5930",'1'&x"5931",'1'&x"5932",'1'&x"5933",'1'&x"5934",'1'&x"5935",'1'&x"5936",'1'&x"5937",'1'&x"5938",'1'&x"5939",'1'&x"593A",'1'&x"593B",'1'&x"593C",'1'&x"593D",'1'&x"593E",'1'&x"593F",
+--'1'&x"5940",'1'&x"5941",'1'&x"5942",'1'&x"5943",'1'&x"5944",'1'&x"5945",'1'&x"5946",'1'&x"5947",'1'&x"5948",'1'&x"5949",'1'&x"594A",'1'&x"594B",'1'&x"594C",'1'&x"594D",'1'&x"594E",'1'&x"594F",
+--'1'&x"5950",'1'&x"5951",'1'&x"5952",'1'&x"5953",'1'&x"5954",'1'&x"5955",'1'&x"5956",'1'&x"5957",'1'&x"5958",'1'&x"5959",'1'&x"595A",'1'&x"595B",'1'&x"595C",'1'&x"595D",'1'&x"595E",'1'&x"595F",
+--'1'&x"5960",'1'&x"5961",'1'&x"5962",'1'&x"5963",'1'&x"5964",'1'&x"5965",'1'&x"5966",'1'&x"5967",'1'&x"5968",'1'&x"5969",'1'&x"596A",'1'&x"596B",'1'&x"596C",'1'&x"596D",'1'&x"596E",'1'&x"596F",
+--'1'&x"5970",'1'&x"5971",'1'&x"5972",'1'&x"5973",'1'&x"5974",'1'&x"5975",'1'&x"5976",'1'&x"5977",'1'&x"5978",'1'&x"5979",'1'&x"597A",'1'&x"597B",'1'&x"597C",'1'&x"597D",'1'&x"597E",'1'&x"597F",
+--'1'&x"5980",'1'&x"5981",'1'&x"5982",'1'&x"5983",'1'&x"5984",'1'&x"5985",'1'&x"5986",'1'&x"5987",'1'&x"5988",'1'&x"5989",'1'&x"598A",'1'&x"598B",'1'&x"598C",'1'&x"598D",'1'&x"598E",'1'&x"598F",
+--'1'&x"5990",'1'&x"5991",'1'&x"5992",'1'&x"5993",'1'&x"5994",'1'&x"5995",'1'&x"5996",'1'&x"5997",'1'&x"5998",'1'&x"5999",'1'&x"599A",'1'&x"599B",'1'&x"599C",'1'&x"599D",'1'&x"599E",'1'&x"599F",
+--'1'&x"59A0",'1'&x"59A1",'1'&x"59A2",'1'&x"59A3",'1'&x"59A4",'1'&x"59A5",'1'&x"59A6",'1'&x"59A7",'1'&x"59A8",'1'&x"59A9",'1'&x"59AA",'1'&x"59AB",'1'&x"59AC",'1'&x"59AD",'1'&x"59AE",'1'&x"59AF",
+--'1'&x"59B0",'1'&x"59B1",'1'&x"59B2",'1'&x"59B3",'1'&x"59B4",'1'&x"59B5",'1'&x"59B6",'1'&x"59B7",'1'&x"59B8",'1'&x"59B9",'1'&x"59BA",'1'&x"59BB",'1'&x"59BC",'1'&x"59BD",'1'&x"59BE",'1'&x"59BF",
+--'1'&x"59C0",'1'&x"59C1",'1'&x"59C2",'1'&x"59C3",'1'&x"59C4",'1'&x"59C5",'1'&x"59C6",'1'&x"59C7",'1'&x"59C8",'1'&x"59C9",'1'&x"59CA",'1'&x"59CB",'1'&x"59CC",'1'&x"59CD",'1'&x"59CE",'1'&x"59CF",
+--'1'&x"59D0",'1'&x"59D1",'1'&x"59D2",'1'&x"59D3",'1'&x"59D4",'1'&x"59D5",'1'&x"59D6",'1'&x"59D7",'1'&x"59D8",'1'&x"59D9",'1'&x"59DA",'1'&x"59DB",'1'&x"59DC",'1'&x"59DD",'1'&x"59DE",'1'&x"59DF",
+--'1'&x"59E0",'1'&x"59E1",'1'&x"59E2",'1'&x"59E3",'1'&x"59E4",'1'&x"59E5",'1'&x"59E6",'1'&x"59E7",'1'&x"59E8",'1'&x"59E9",'1'&x"59EA",'1'&x"59EB",'1'&x"59EC",'1'&x"59ED",'1'&x"59EE",'1'&x"59EF",
+--'1'&x"59F0",'1'&x"59F1",'1'&x"59F2",'1'&x"59F3",'1'&x"59F4",'1'&x"59F5",'1'&x"59F6",'1'&x"59F7",'1'&x"59F8",'1'&x"59F9",'1'&x"59FA",'1'&x"59FB",'1'&x"59FC",'1'&x"59FD",'1'&x"59FE",'1'&x"59FF",
+--'1'&x"5A00",'1'&x"5A01",'1'&x"5A02",'1'&x"5A03",'1'&x"5A04",'1'&x"5A05",'1'&x"5A06",'1'&x"5A07",'1'&x"5A08",'1'&x"5A09",'1'&x"5A0A",'1'&x"5A0B",'1'&x"5A0C",'1'&x"5A0D",'1'&x"5A0E",'1'&x"5A0F",
+--'1'&x"5A10",'1'&x"5A11",'1'&x"5A12",'1'&x"5A13",'1'&x"5A14",'1'&x"5A15",'1'&x"5A16",'1'&x"5A17",'1'&x"5A18",'1'&x"5A19",'1'&x"5A1A",'1'&x"5A1B",'1'&x"5A1C",'1'&x"5A1D",'1'&x"5A1E",'1'&x"5A1F",
+--'1'&x"5A20",'1'&x"5A21",'1'&x"5A22",'1'&x"5A23",'1'&x"5A24",'1'&x"5A25",'1'&x"5A26",'1'&x"5A27",'1'&x"5A28",'1'&x"5A29",'1'&x"5A2A",'1'&x"5A2B",'1'&x"5A2C",'1'&x"5A2D",'1'&x"5A2E",'1'&x"5A2F",
+--'1'&x"5A30",'1'&x"5A31",'1'&x"5A32",'1'&x"5A33",'1'&x"5A34",'1'&x"5A35",'1'&x"5A36",'1'&x"5A37",'1'&x"5A38",'1'&x"5A39",'1'&x"5A3A",'1'&x"5A3B",'1'&x"5A3C",'1'&x"5A3D",'1'&x"5A3E",'1'&x"5A3F",
+--'1'&x"5A40",'1'&x"5A41",'1'&x"5A42",'1'&x"5A43",'1'&x"5A44",'1'&x"5A45",'1'&x"5A46",'1'&x"5A47",'1'&x"5A48",'1'&x"5A49",'1'&x"5A4A",'1'&x"5A4B",'1'&x"5A4C",'1'&x"5A4D",'1'&x"5A4E",'1'&x"5A4F",
+--'1'&x"5A50",'1'&x"5A51",'1'&x"5A52",'1'&x"5A53",'1'&x"5A54",'1'&x"5A55",'1'&x"5A56",'1'&x"5A57",'1'&x"5A58",'1'&x"5A59",'1'&x"5A5A",'1'&x"5A5B",'1'&x"5A5C",'1'&x"5A5D",'1'&x"5A5E",'1'&x"5A5F",
+--'1'&x"5A60",'1'&x"5A61",'1'&x"5A62",'1'&x"5A63",'1'&x"5A64",'1'&x"5A65",'1'&x"5A66",'1'&x"5A67",'1'&x"5A68",'1'&x"5A69",'1'&x"5A6A",'1'&x"5A6B",'1'&x"5A6C",'1'&x"5A6D",'1'&x"5A6E",'1'&x"5A6F",
+--'1'&x"5A70",'1'&x"5A71",'1'&x"5A72",'1'&x"5A73",'1'&x"5A74",'1'&x"5A75",'1'&x"5A76",'1'&x"5A77",'1'&x"5A78",'1'&x"5A79",'1'&x"5A7A",'1'&x"5A7B",'1'&x"5A7C",'1'&x"5A7D",'1'&x"5A7E",'1'&x"5A7F",
+--'1'&x"5A80",'1'&x"5A81",'1'&x"5A82",'1'&x"5A83",'1'&x"5A84",'1'&x"5A85",'1'&x"5A86",'1'&x"5A87",'1'&x"5A88",'1'&x"5A89",'1'&x"5A8A",'1'&x"5A8B",'1'&x"5A8C",'1'&x"5A8D",'1'&x"5A8E",'1'&x"5A8F",
+--'1'&x"5A90",'1'&x"5A91",'1'&x"5A92",'1'&x"5A93",'1'&x"5A94",'1'&x"5A95",'1'&x"5A96",'1'&x"5A97",'1'&x"5A98",'1'&x"5A99",'1'&x"5A9A",'1'&x"5A9B",'1'&x"5A9C",'1'&x"5A9D",'1'&x"5A9E",'1'&x"5A9F",
+--'1'&x"5AA0",'1'&x"5AA1",'1'&x"5AA2",'1'&x"5AA3",'1'&x"5AA4",'1'&x"5AA5",'1'&x"5AA6",'1'&x"5AA7",'1'&x"5AA8",'1'&x"5AA9",'1'&x"5AAA",'1'&x"5AAB",'1'&x"5AAC",'1'&x"5AAD",'1'&x"5AAE",'1'&x"5AAF",
+--'1'&x"5AB0",'1'&x"5AB1",'1'&x"5AB2",'1'&x"5AB3",'1'&x"5AB4",'1'&x"5AB5",'1'&x"5AB6",'1'&x"5AB7",'1'&x"5AB8",'1'&x"5AB9",'1'&x"5ABA",'1'&x"5ABB",'1'&x"5ABC",'1'&x"5ABD",'1'&x"5ABE",'1'&x"5ABF",
+--'1'&x"5AC0",'1'&x"5AC1",'1'&x"5AC2",'1'&x"5AC3",'1'&x"5AC4",'1'&x"5AC5",'1'&x"5AC6",'1'&x"5AC7",'1'&x"5AC8",'1'&x"5AC9",'1'&x"5ACA",'1'&x"5ACB",'1'&x"5ACC",'1'&x"5ACD",'1'&x"5ACE",'1'&x"5ACF",
+--'1'&x"5AD0",'1'&x"5AD1",'1'&x"5AD2",'1'&x"5AD3",'1'&x"5AD4",'1'&x"5AD5",'1'&x"5AD6",'1'&x"5AD7",'1'&x"5AD8",'1'&x"5AD9",'1'&x"5ADA",'1'&x"5ADB",'1'&x"5ADC",'1'&x"5ADD",'1'&x"5ADE",'1'&x"5ADF",
+--'1'&x"5AE0",'1'&x"5AE1",'1'&x"5AE2",'1'&x"5AE3",'1'&x"5AE4",'1'&x"5AE5",'1'&x"5AE6",'1'&x"5AE7",'1'&x"5AE8",'1'&x"5AE9",'1'&x"5AEA",'1'&x"5AEB",'1'&x"5AEC",'1'&x"5AED",'1'&x"5AEE",'1'&x"5AEF",
+--'1'&x"5AF0",'1'&x"5AF1",'1'&x"5AF2",'1'&x"5AF3",'1'&x"5AF4",'1'&x"5AF5",'1'&x"5AF6",'1'&x"5AF7",'1'&x"5AF8",'1'&x"5AF9",'1'&x"5AFA",'1'&x"5AFB",'1'&x"5AFC",'1'&x"5AFD",'1'&x"5AFE",'1'&x"5AFF",
+--'1'&x"5B00",'1'&x"5B01",'1'&x"5B02",'1'&x"5B03",'1'&x"5B04",'1'&x"5B05",'1'&x"5B06",'1'&x"5B07",'1'&x"5B08",'1'&x"5B09",'1'&x"5B0A",'1'&x"5B0B",'1'&x"5B0C",'1'&x"5B0D",'1'&x"5B0E",'1'&x"5B0F",
+--'1'&x"5B10",'1'&x"5B11",'1'&x"5B12",'1'&x"5B13",'1'&x"5B14",'1'&x"5B15",'1'&x"5B16",'1'&x"5B17",'1'&x"5B18",'1'&x"5B19",'1'&x"5B1A",'1'&x"5B1B",'1'&x"5B1C",'1'&x"5B1D",'1'&x"5B1E",'1'&x"5B1F",
+--'1'&x"5B20",'1'&x"5B21",'1'&x"5B22",'1'&x"5B23",'1'&x"5B24",'1'&x"5B25",'1'&x"5B26",'1'&x"5B27",'1'&x"5B28",'1'&x"5B29",'1'&x"5B2A",'1'&x"5B2B",'1'&x"5B2C",'1'&x"5B2D",'1'&x"5B2E",'1'&x"5B2F",
+--'1'&x"5B30",'1'&x"5B31",'1'&x"5B32",'1'&x"5B33",'1'&x"5B34",'1'&x"5B35",'1'&x"5B36",'1'&x"5B37",'1'&x"5B38",'1'&x"5B39",'1'&x"5B3A",'1'&x"5B3B",'1'&x"5B3C",'1'&x"5B3D",'1'&x"5B3E",'1'&x"5B3F",
+--'1'&x"5B40",'1'&x"5B41",'1'&x"5B42",'1'&x"5B43",'1'&x"5B44",'1'&x"5B45",'1'&x"5B46",'1'&x"5B47",'1'&x"5B48",'1'&x"5B49",'1'&x"5B4A",'1'&x"5B4B",'1'&x"5B4C",'1'&x"5B4D",'1'&x"5B4E",'1'&x"5B4F",
+--'1'&x"5B50",'1'&x"5B51",'1'&x"5B52",'1'&x"5B53",'1'&x"5B54",'1'&x"5B55",'1'&x"5B56",'1'&x"5B57",'1'&x"5B58",'1'&x"5B59",'1'&x"5B5A",'1'&x"5B5B",'1'&x"5B5C",'1'&x"5B5D",'1'&x"5B5E",'1'&x"5B5F",
+--'1'&x"5B60",'1'&x"5B61",'1'&x"5B62",'1'&x"5B63",'1'&x"5B64",'1'&x"5B65",'1'&x"5B66",'1'&x"5B67",'1'&x"5B68",'1'&x"5B69",'1'&x"5B6A",'1'&x"5B6B",'1'&x"5B6C",'1'&x"5B6D",'1'&x"5B6E",'1'&x"5B6F",
+--'1'&x"5B70",'1'&x"5B71",'1'&x"5B72",'1'&x"5B73",'1'&x"5B74",'1'&x"5B75",'1'&x"5B76",'1'&x"5B77",'1'&x"5B78",'1'&x"5B79",'1'&x"5B7A",'1'&x"5B7B",'1'&x"5B7C",'1'&x"5B7D",'1'&x"5B7E",'1'&x"5B7F",
+--'1'&x"5B80",'1'&x"5B81",'1'&x"5B82",'1'&x"5B83",'1'&x"5B84",'1'&x"5B85",'1'&x"5B86",'1'&x"5B87",'1'&x"5B88",'1'&x"5B89",'1'&x"5B8A",'1'&x"5B8B",'1'&x"5B8C",'1'&x"5B8D",'1'&x"5B8E",'1'&x"5B8F",
+--'1'&x"5B90",'1'&x"5B91",'1'&x"5B92",'1'&x"5B93",'1'&x"5B94",'1'&x"5B95",'1'&x"5B96",'1'&x"5B97",'1'&x"5B98",'1'&x"5B99",'1'&x"5B9A",'1'&x"5B9B",'1'&x"5B9C",'1'&x"5B9D",'1'&x"5B9E",'1'&x"5B9F",
+--'1'&x"5BA0",'1'&x"5BA1",'1'&x"5BA2",'1'&x"5BA3",'1'&x"5BA4",'1'&x"5BA5",'1'&x"5BA6",'1'&x"5BA7",'1'&x"5BA8",'1'&x"5BA9",'1'&x"5BAA",'1'&x"5BAB",'1'&x"5BAC",'1'&x"5BAD",'1'&x"5BAE",'1'&x"5BAF",
+--'1'&x"5BB0",'1'&x"5BB1",'1'&x"5BB2",'1'&x"5BB3",'1'&x"5BB4",'1'&x"5BB5",'1'&x"5BB6",'1'&x"5BB7",'1'&x"5BB8",'1'&x"5BB9",'1'&x"5BBA",'1'&x"5BBB",'1'&x"5BBC",'1'&x"5BBD",'1'&x"5BBE",'1'&x"5BBF",
+--'1'&x"5BC0",'1'&x"5BC1",'1'&x"5BC2",'1'&x"5BC3",'1'&x"5BC4",'1'&x"5BC5",'1'&x"5BC6",'1'&x"5BC7",'1'&x"5BC8",'1'&x"5BC9",'1'&x"5BCA",'1'&x"5BCB",'1'&x"5BCC",'1'&x"5BCD",'1'&x"5BCE",'1'&x"5BCF",
+--'1'&x"5BD0",'1'&x"5BD1",'1'&x"5BD2",'1'&x"5BD3",'1'&x"5BD4",'1'&x"5BD5",'1'&x"5BD6",'1'&x"5BD7",'1'&x"5BD8",'1'&x"5BD9",'1'&x"5BDA",'1'&x"5BDB",'1'&x"5BDC",'1'&x"5BDD",'1'&x"5BDE",'1'&x"5BDF",
+--'1'&x"5BE0",'1'&x"5BE1",'1'&x"5BE2",'1'&x"5BE3",'1'&x"5BE4",'1'&x"5BE5",'1'&x"5BE6",'1'&x"5BE7",'1'&x"5BE8",'1'&x"5BE9",'1'&x"5BEA",'1'&x"5BEB",'1'&x"5BEC",'1'&x"5BED",'1'&x"5BEE",'1'&x"5BEF",
+--'1'&x"5BF0",'1'&x"5BF1",'1'&x"5BF2",'1'&x"5BF3",'1'&x"5BF4",'1'&x"5BF5",'1'&x"5BF6",'1'&x"5BF7",'1'&x"5BF8",'1'&x"5BF9",'1'&x"5BFA",'1'&x"5BFB",'1'&x"5BFC",'1'&x"5BFD",'1'&x"5BFE",'1'&x"5BFF",
+--'1'&x"5C00",'1'&x"5C01",'1'&x"5C02",'1'&x"5C03",'1'&x"5C04",'1'&x"5C05",'1'&x"5C06",'1'&x"5C07",'1'&x"5C08",'1'&x"5C09",'1'&x"5C0A",'1'&x"5C0B",'1'&x"5C0C",'1'&x"5C0D",'1'&x"5C0E",'1'&x"5C0F",
+--'1'&x"5C10",'1'&x"5C11",'1'&x"5C12",'1'&x"5C13",'1'&x"5C14",'1'&x"5C15",'1'&x"5C16",'1'&x"5C17",'1'&x"5C18",'1'&x"5C19",'1'&x"5C1A",'1'&x"5C1B",'1'&x"5C1C",'1'&x"5C1D",'1'&x"5C1E",'1'&x"5C1F",
+--'1'&x"5C20",'1'&x"5C21",'1'&x"5C22",'1'&x"5C23",'1'&x"5C24",'1'&x"5C25",'1'&x"5C26",'1'&x"5C27",'1'&x"5C28",'1'&x"5C29",'1'&x"5C2A",'1'&x"5C2B",'1'&x"5C2C",'1'&x"5C2D",'1'&x"5C2E",'1'&x"5C2F",
+--'1'&x"5C30",'1'&x"5C31",'1'&x"5C32",'1'&x"5C33",'1'&x"5C34",'1'&x"5C35",'1'&x"5C36",'1'&x"5C37",'1'&x"5C38",'1'&x"5C39",'1'&x"5C3A",'1'&x"5C3B",'1'&x"5C3C",'1'&x"5C3D",'1'&x"5C3E",'1'&x"5C3F",
+--'1'&x"5C40",'1'&x"5C41",'1'&x"5C42",'1'&x"5C43",'1'&x"5C44",'1'&x"5C45",'1'&x"5C46",'1'&x"5C47",'1'&x"5C48",'1'&x"5C49",'1'&x"5C4A",'1'&x"5C4B",'1'&x"5C4C",'1'&x"5C4D",'1'&x"5C4E",'1'&x"5C4F",
+--'1'&x"5C50",'1'&x"5C51",'1'&x"5C52",'1'&x"5C53",'1'&x"5C54",'1'&x"5C55",'1'&x"5C56",'1'&x"5C57",'1'&x"5C58",'1'&x"5C59",'1'&x"5C5A",'1'&x"5C5B",'1'&x"5C5C",'1'&x"5C5D",'1'&x"5C5E",'1'&x"5C5F",
+--'1'&x"5C60",'1'&x"5C61",'1'&x"5C62",'1'&x"5C63",'1'&x"5C64",'1'&x"5C65",'1'&x"5C66",'1'&x"5C67",'1'&x"5C68",'1'&x"5C69",'1'&x"5C6A",'1'&x"5C6B",'1'&x"5C6C",'1'&x"5C6D",'1'&x"5C6E",'1'&x"5C6F",
+--'1'&x"5C70",'1'&x"5C71",'1'&x"5C72",'1'&x"5C73",'1'&x"5C74",'1'&x"5C75",'1'&x"5C76",'1'&x"5C77",'1'&x"5C78",'1'&x"5C79",'1'&x"5C7A",'1'&x"5C7B",'1'&x"5C7C",'1'&x"5C7D",'1'&x"5C7E",'1'&x"5C7F",
+--'1'&x"5C80",'1'&x"5C81",'1'&x"5C82",'1'&x"5C83",'1'&x"5C84",'1'&x"5C85",'1'&x"5C86",'1'&x"5C87",'1'&x"5C88",'1'&x"5C89",'1'&x"5C8A",'1'&x"5C8B",'1'&x"5C8C",'1'&x"5C8D",'1'&x"5C8E",'1'&x"5C8F",
+--'1'&x"5C90",'1'&x"5C91",'1'&x"5C92",'1'&x"5C93",'1'&x"5C94",'1'&x"5C95",'1'&x"5C96",'1'&x"5C97",'1'&x"5C98",'1'&x"5C99",'1'&x"5C9A",'1'&x"5C9B",'1'&x"5C9C",'1'&x"5C9D",'1'&x"5C9E",'1'&x"5C9F",
+--'1'&x"5CA0",'1'&x"5CA1",'1'&x"5CA2",'1'&x"5CA3",'1'&x"5CA4",'1'&x"5CA5",'1'&x"5CA6",'1'&x"5CA7",'1'&x"5CA8",'1'&x"5CA9",'1'&x"5CAA",'1'&x"5CAB",'1'&x"5CAC",'1'&x"5CAD",'1'&x"5CAE",'1'&x"5CAF",
+--'1'&x"5CB0",'1'&x"5CB1",'1'&x"5CB2",'1'&x"5CB3",'1'&x"5CB4",'1'&x"5CB5",'1'&x"5CB6",'1'&x"5CB7",'1'&x"5CB8",'1'&x"5CB9",'1'&x"5CBA",'1'&x"5CBB",'1'&x"5CBC",'1'&x"5CBD",'1'&x"5CBE",'1'&x"5CBF",
+--'1'&x"5CC0",'1'&x"5CC1",'1'&x"5CC2",'1'&x"5CC3",'1'&x"5CC4",'1'&x"5CC5",'1'&x"5CC6",'1'&x"5CC7",'1'&x"5CC8",'1'&x"5CC9",'1'&x"5CCA",'1'&x"5CCB",'1'&x"5CCC",'1'&x"5CCD",'1'&x"5CCE",'1'&x"5CCF",
+--'1'&x"5CD0",'1'&x"5CD1",'1'&x"5CD2",'1'&x"5CD3",'1'&x"5CD4",'1'&x"5CD5",'1'&x"5CD6",'1'&x"5CD7",'1'&x"5CD8",'1'&x"5CD9",'1'&x"5CDA",'1'&x"5CDB",'1'&x"5CDC",'1'&x"5CDD",'1'&x"5CDE",'1'&x"5CDF",
+--'1'&x"5CE0",'1'&x"5CE1",'1'&x"5CE2",'1'&x"5CE3",'1'&x"5CE4",'1'&x"5CE5",'1'&x"5CE6",'1'&x"5CE7",'1'&x"5CE8",'1'&x"5CE9",'1'&x"5CEA",'1'&x"5CEB",'1'&x"5CEC",'1'&x"5CED",'1'&x"5CEE",'1'&x"5CEF",
+--'1'&x"5CF0",'1'&x"5CF1",'1'&x"5CF2",'1'&x"5CF3",'1'&x"5CF4",'1'&x"5CF5",'1'&x"5CF6",'1'&x"5CF7",'1'&x"5CF8",'1'&x"5CF9",'1'&x"5CFA",'1'&x"5CFB",'1'&x"5CFC",'1'&x"5CFD",'1'&x"5CFE",'1'&x"5CFF",
+--'1'&x"5D00",'1'&x"5D01",'1'&x"5D02",'1'&x"5D03",'1'&x"5D04",'1'&x"5D05",'1'&x"5D06",'1'&x"5D07",'1'&x"5D08",'1'&x"5D09",'1'&x"5D0A",'1'&x"5D0B",'1'&x"5D0C",'1'&x"5D0D",'1'&x"5D0E",'1'&x"5D0F",
+--'1'&x"5D10",'1'&x"5D11",'1'&x"5D12",'1'&x"5D13",'1'&x"5D14",'1'&x"5D15",'1'&x"5D16",'1'&x"5D17",'1'&x"5D18",'1'&x"5D19",'1'&x"5D1A",'1'&x"5D1B",'1'&x"5D1C",'1'&x"5D1D",'1'&x"5D1E",'1'&x"5D1F",
+--'1'&x"5D20",'1'&x"5D21",'1'&x"5D22",'1'&x"5D23",'1'&x"5D24",'1'&x"5D25",'1'&x"5D26",'1'&x"5D27",'1'&x"5D28",'1'&x"5D29",'1'&x"5D2A",'1'&x"5D2B",'1'&x"5D2C",'1'&x"5D2D",'1'&x"5D2E",'1'&x"5D2F",
+--'1'&x"5D30",'1'&x"5D31",'1'&x"5D32",'1'&x"5D33",'1'&x"5D34",'1'&x"5D35",'1'&x"5D36",'1'&x"5D37",'1'&x"5D38",'1'&x"5D39",'1'&x"5D3A",'1'&x"5D3B",'1'&x"5D3C",'1'&x"5D3D",'1'&x"5D3E",'1'&x"5D3F",
+--'1'&x"5D40",'1'&x"5D41",'1'&x"5D42",'1'&x"5D43",'1'&x"5D44",'1'&x"5D45",'1'&x"5D46",'1'&x"5D47",'1'&x"5D48",'1'&x"5D49",'1'&x"5D4A",'1'&x"5D4B",'1'&x"5D4C",'1'&x"5D4D",'1'&x"5D4E",'1'&x"5D4F",
+--'1'&x"5D50",'1'&x"5D51",'1'&x"5D52",'1'&x"5D53",'1'&x"5D54",'1'&x"5D55",'1'&x"5D56",'1'&x"5D57",'1'&x"5D58",'1'&x"5D59",'1'&x"5D5A",'1'&x"5D5B",'1'&x"5D5C",'1'&x"5D5D",'1'&x"5D5E",'1'&x"5D5F",
+--'1'&x"5D60",'1'&x"5D61",'1'&x"5D62",'1'&x"5D63",'1'&x"5D64",'1'&x"5D65",'1'&x"5D66",'1'&x"5D67",'1'&x"5D68",'1'&x"5D69",'1'&x"5D6A",'1'&x"5D6B",'1'&x"5D6C",'1'&x"5D6D",'1'&x"5D6E",'1'&x"5D6F",
+--'1'&x"5D70",'1'&x"5D71",'1'&x"5D72",'1'&x"5D73",'1'&x"5D74",'1'&x"5D75",'1'&x"5D76",'1'&x"5D77",'1'&x"5D78",'1'&x"5D79",'1'&x"5D7A",'1'&x"5D7B",'1'&x"5D7C",'1'&x"5D7D",'1'&x"5D7E",'1'&x"5D7F",
+--'1'&x"5D80",'1'&x"5D81",'1'&x"5D82",'1'&x"5D83",'1'&x"5D84",'1'&x"5D85",'1'&x"5D86",'1'&x"5D87",'1'&x"5D88",'1'&x"5D89",'1'&x"5D8A",'1'&x"5D8B",'1'&x"5D8C",'1'&x"5D8D",'1'&x"5D8E",'1'&x"5D8F",
+--'1'&x"5D90",'1'&x"5D91",'1'&x"5D92",'1'&x"5D93",'1'&x"5D94",'1'&x"5D95",'1'&x"5D96",'1'&x"5D97",'1'&x"5D98",'1'&x"5D99",'1'&x"5D9A",'1'&x"5D9B",'1'&x"5D9C",'1'&x"5D9D",'1'&x"5D9E",'1'&x"5D9F",
+--'1'&x"5DA0",'1'&x"5DA1",'1'&x"5DA2",'1'&x"5DA3",'1'&x"5DA4",'1'&x"5DA5",'1'&x"5DA6",'1'&x"5DA7",'1'&x"5DA8",'1'&x"5DA9",'1'&x"5DAA",'1'&x"5DAB",'1'&x"5DAC",'1'&x"5DAD",'1'&x"5DAE",'1'&x"5DAF",
+--'1'&x"5DB0",'1'&x"5DB1",'1'&x"5DB2",'1'&x"5DB3",'1'&x"5DB4",'1'&x"5DB5",'1'&x"5DB6",'1'&x"5DB7",'1'&x"5DB8",'1'&x"5DB9",'1'&x"5DBA",'1'&x"5DBB",'1'&x"5DBC",'1'&x"5DBD",'1'&x"5DBE",'1'&x"5DBF",
+--'1'&x"5DC0",'1'&x"5DC1",'1'&x"5DC2",'1'&x"5DC3",'1'&x"5DC4",'1'&x"5DC5",'1'&x"5DC6",'1'&x"5DC7",'1'&x"5DC8",'1'&x"5DC9",'1'&x"5DCA",'1'&x"5DCB",'1'&x"5DCC",'1'&x"5DCD",'1'&x"5DCE",'1'&x"5DCF",
+--'1'&x"5DD0",'1'&x"5DD1",'1'&x"5DD2",'1'&x"5DD3",'1'&x"5DD4",'1'&x"5DD5",'1'&x"5DD6",'1'&x"5DD7",'1'&x"5DD8",'1'&x"5DD9",'1'&x"5DDA",'1'&x"5DDB",'1'&x"5DDC",'1'&x"5DDD",'1'&x"5DDE",'1'&x"5DDF",
+--'1'&x"5DE0",'1'&x"5DE1",'1'&x"5DE2",'1'&x"5DE3",'1'&x"5DE4",'1'&x"5DE5",'1'&x"5DE6",'1'&x"5DE7",'1'&x"5DE8",'1'&x"5DE9",'1'&x"5DEA",'1'&x"5DEB",'1'&x"5DEC",'1'&x"5DED",'1'&x"5DEE",'1'&x"5DEF",
+--'1'&x"5DF0",'1'&x"5DF1",'1'&x"5DF2",'1'&x"5DF3",'1'&x"5DF4",'1'&x"5DF5",'1'&x"5DF6",'1'&x"5DF7",'1'&x"5DF8",'1'&x"5DF9",'1'&x"5DFA",'1'&x"5DFB",'1'&x"5DFC",'1'&x"5DFD",'1'&x"5DFE",'1'&x"5DFF",
+--'1'&x"5E00",'1'&x"5E01",'1'&x"5E02",'1'&x"5E03",'1'&x"5E04",'1'&x"5E05",'1'&x"5E06",'1'&x"5E07",'1'&x"5E08",'1'&x"5E09",'1'&x"5E0A",'1'&x"5E0B",'1'&x"5E0C",'1'&x"5E0D",'1'&x"5E0E",'1'&x"5E0F",
+--'1'&x"5E10",'1'&x"5E11",'1'&x"5E12",'1'&x"5E13",'1'&x"5E14",'1'&x"5E15",'1'&x"5E16",'1'&x"5E17",'1'&x"5E18",'1'&x"5E19",'1'&x"5E1A",'1'&x"5E1B",'1'&x"5E1C",'1'&x"5E1D",'1'&x"5E1E",'1'&x"5E1F",
+--'1'&x"5E20",'1'&x"5E21",'1'&x"5E22",'1'&x"5E23",'1'&x"5E24",'1'&x"5E25",'1'&x"5E26",'1'&x"5E27",'1'&x"5E28",'1'&x"5E29",'1'&x"5E2A",'1'&x"5E2B",'1'&x"5E2C",'1'&x"5E2D",'1'&x"5E2E",'1'&x"5E2F",
+--'1'&x"5E30",'1'&x"5E31",'1'&x"5E32",'1'&x"5E33",'1'&x"5E34",'1'&x"5E35",'1'&x"5E36",'1'&x"5E37",'1'&x"5E38",'1'&x"5E39",'1'&x"5E3A",'1'&x"5E3B",'1'&x"5E3C",'1'&x"5E3D",'1'&x"5E3E",'1'&x"5E3F",
+--'1'&x"5E40",'1'&x"5E41",'1'&x"5E42",'1'&x"5E43",'1'&x"5E44",'1'&x"5E45",'1'&x"5E46",'1'&x"5E47",'1'&x"5E48",'1'&x"5E49",'1'&x"5E4A",'1'&x"5E4B",'1'&x"5E4C",'1'&x"5E4D",'1'&x"5E4E",'1'&x"5E4F",
+--'1'&x"5E50",'1'&x"5E51",'1'&x"5E52",'1'&x"5E53",'1'&x"5E54",'1'&x"5E55",'1'&x"5E56",'1'&x"5E57",'1'&x"5E58",'1'&x"5E59",'1'&x"5E5A",'1'&x"5E5B",'1'&x"5E5C",'1'&x"5E5D",'1'&x"5E5E",'1'&x"5E5F",
+--'1'&x"5E60",'1'&x"5E61",'1'&x"5E62",'1'&x"5E63",'1'&x"5E64",'1'&x"5E65",'1'&x"5E66",'1'&x"5E67",'1'&x"5E68",'1'&x"5E69",'1'&x"5E6A",'1'&x"5E6B",'1'&x"5E6C",'1'&x"5E6D",'1'&x"5E6E",'1'&x"5E6F",
+--'1'&x"5E70",'1'&x"5E71",'1'&x"5E72",'1'&x"5E73",'1'&x"5E74",'1'&x"5E75",'1'&x"5E76",'1'&x"5E77",'1'&x"5E78",'1'&x"5E79",'1'&x"5E7A",'1'&x"5E7B",'1'&x"5E7C",'1'&x"5E7D",'1'&x"5E7E",'1'&x"5E7F",
+--'1'&x"5E80",'1'&x"5E81",'1'&x"5E82",'1'&x"5E83",'1'&x"5E84",'1'&x"5E85",'1'&x"5E86",'1'&x"5E87",'1'&x"5E88",'1'&x"5E89",'1'&x"5E8A",'1'&x"5E8B",'1'&x"5E8C",'1'&x"5E8D",'1'&x"5E8E",'1'&x"5E8F",
+--'1'&x"5E90",'1'&x"5E91",'1'&x"5E92",'1'&x"5E93",'1'&x"5E94",'1'&x"5E95",'1'&x"5E96",'1'&x"5E97",'1'&x"5E98",'1'&x"5E99",'1'&x"5E9A",'1'&x"5E9B",'1'&x"5E9C",'1'&x"5E9D",'1'&x"5E9E",'1'&x"5E9F",
+--'1'&x"5EA0",'1'&x"5EA1",'1'&x"5EA2",'1'&x"5EA3",'1'&x"5EA4",'1'&x"5EA5",'1'&x"5EA6",'1'&x"5EA7",'1'&x"5EA8",'1'&x"5EA9",'1'&x"5EAA",'1'&x"5EAB",'1'&x"5EAC",'1'&x"5EAD",'1'&x"5EAE",'1'&x"5EAF",
+--'1'&x"5EB0",'1'&x"5EB1",'1'&x"5EB2",'1'&x"5EB3",'1'&x"5EB4",'1'&x"5EB5",'1'&x"5EB6",'1'&x"5EB7",'1'&x"5EB8",'1'&x"5EB9",'1'&x"5EBA",'1'&x"5EBB",'1'&x"5EBC",'1'&x"5EBD",'1'&x"5EBE",'1'&x"5EBF",
+--'1'&x"5EC0",'1'&x"5EC1",'1'&x"5EC2",'1'&x"5EC3",'1'&x"5EC4",'1'&x"5EC5",'1'&x"5EC6",'1'&x"5EC7",'1'&x"5EC8",'1'&x"5EC9",'1'&x"5ECA",'1'&x"5ECB",'1'&x"5ECC",'1'&x"5ECD",'1'&x"5ECE",'1'&x"5ECF",
+--'1'&x"5ED0",'1'&x"5ED1",'1'&x"5ED2",'1'&x"5ED3",'1'&x"5ED4",'1'&x"5ED5",'1'&x"5ED6",'1'&x"5ED7",'1'&x"5ED8",'1'&x"5ED9",'1'&x"5EDA",'1'&x"5EDB",'1'&x"5EDC",'1'&x"5EDD",'1'&x"5EDE",'1'&x"5EDF",
+--'1'&x"5EE0",'1'&x"5EE1",'1'&x"5EE2",'1'&x"5EE3",'1'&x"5EE4",'1'&x"5EE5",'1'&x"5EE6",'1'&x"5EE7",'1'&x"5EE8",'1'&x"5EE9",'1'&x"5EEA",'1'&x"5EEB",'1'&x"5EEC",'1'&x"5EED",'1'&x"5EEE",'1'&x"5EEF",
+--'1'&x"5EF0",'1'&x"5EF1",'1'&x"5EF2",'1'&x"5EF3",'1'&x"5EF4",'1'&x"5EF5",'1'&x"5EF6",'1'&x"5EF7",'1'&x"5EF8",'1'&x"5EF9",'1'&x"5EFA",'1'&x"5EFB",'1'&x"5EFC",'1'&x"5EFD",'1'&x"5EFE",'1'&x"5EFF",
+--'1'&x"5F00",'1'&x"5F01",'1'&x"5F02",'1'&x"5F03",'1'&x"5F04",'1'&x"5F05",'1'&x"5F06",'1'&x"5F07",'1'&x"5F08",'1'&x"5F09",'1'&x"5F0A",'1'&x"5F0B",'1'&x"5F0C",'1'&x"5F0D",'1'&x"5F0E",'1'&x"5F0F",
+--'1'&x"5F10",'1'&x"5F11",'1'&x"5F12",'1'&x"5F13",'1'&x"5F14",'1'&x"5F15",'1'&x"5F16",'1'&x"5F17",'1'&x"5F18",'1'&x"5F19",'1'&x"5F1A",'1'&x"5F1B",'1'&x"5F1C",'1'&x"5F1D",'1'&x"5F1E",'1'&x"5F1F",
+--'1'&x"5F20",'1'&x"5F21",'1'&x"5F22",'1'&x"5F23",'1'&x"5F24",'1'&x"5F25",'1'&x"5F26",'1'&x"5F27",'1'&x"5F28",'1'&x"5F29",'1'&x"5F2A",'1'&x"5F2B",'1'&x"5F2C",'1'&x"5F2D",'1'&x"5F2E",'1'&x"5F2F",
+--'1'&x"5F30",'1'&x"5F31",'1'&x"5F32",'1'&x"5F33",'1'&x"5F34",'1'&x"5F35",'1'&x"5F36",'1'&x"5F37",'1'&x"5F38",'1'&x"5F39",'1'&x"5F3A",'1'&x"5F3B",'1'&x"5F3C",'1'&x"5F3D",'1'&x"5F3E",'1'&x"5F3F",
+--'1'&x"5F40",'1'&x"5F41",'1'&x"5F42",'1'&x"5F43",'1'&x"5F44",'1'&x"5F45",'1'&x"5F46",'1'&x"5F47",'1'&x"5F48",'1'&x"5F49",'1'&x"5F4A",'1'&x"5F4B",'1'&x"5F4C",'1'&x"5F4D",'1'&x"5F4E",'1'&x"5F4F",
+--'1'&x"5F50",'1'&x"5F51",'1'&x"5F52",'1'&x"5F53",'1'&x"5F54",'1'&x"5F55",'1'&x"5F56",'1'&x"5F57",'1'&x"5F58",'1'&x"5F59",'1'&x"5F5A",'1'&x"5F5B",'1'&x"5F5C",'1'&x"5F5D",'1'&x"5F5E",'1'&x"5F5F",
+--'1'&x"5F60",'1'&x"5F61",'1'&x"5F62",'1'&x"5F63",'1'&x"5F64",'1'&x"5F65",'1'&x"5F66",'1'&x"5F67",'1'&x"5F68",'1'&x"5F69",'1'&x"5F6A",'1'&x"5F6B",'1'&x"5F6C",'1'&x"5F6D",'1'&x"5F6E",'1'&x"5F6F",
+--'1'&x"5F70",'1'&x"5F71",'1'&x"5F72",'1'&x"5F73",'1'&x"5F74",'1'&x"5F75",'1'&x"5F76",'1'&x"5F77",'1'&x"5F78",'1'&x"5F79",'1'&x"5F7A",'1'&x"5F7B",'1'&x"5F7C",'1'&x"5F7D",'1'&x"5F7E",'1'&x"5F7F",
+--'1'&x"5F80",'1'&x"5F81",'1'&x"5F82",'1'&x"5F83",'1'&x"5F84",'1'&x"5F85",'1'&x"5F86",'1'&x"5F87",'1'&x"5F88",'1'&x"5F89",'1'&x"5F8A",'1'&x"5F8B",'1'&x"5F8C",'1'&x"5F8D",'1'&x"5F8E",'1'&x"5F8F",
+--'1'&x"5F90",'1'&x"5F91",'1'&x"5F92",'1'&x"5F93",'1'&x"5F94",'1'&x"5F95",'1'&x"5F96",'1'&x"5F97",'1'&x"5F98",'1'&x"5F99",'1'&x"5F9A",'1'&x"5F9B",'1'&x"5F9C",'1'&x"5F9D",'1'&x"5F9E",'1'&x"5F9F",
+--'1'&x"5FA0",'1'&x"5FA1",'1'&x"5FA2",'1'&x"5FA3",'1'&x"5FA4",'1'&x"5FA5",'1'&x"5FA6",'1'&x"5FA7",'1'&x"5FA8",'1'&x"5FA9",'1'&x"5FAA",'1'&x"5FAB",'1'&x"5FAC",'1'&x"5FAD",'1'&x"5FAE",'1'&x"5FAF",
+--'1'&x"5FB0",'1'&x"5FB1",'1'&x"5FB2",'1'&x"5FB3",'1'&x"5FB4",'1'&x"5FB5",'1'&x"5FB6",'1'&x"5FB7",'1'&x"5FB8",'1'&x"5FB9",'1'&x"5FBA",'1'&x"5FBB",'1'&x"5FBC",'1'&x"5FBD",'1'&x"5FBE",'1'&x"5FBF",
+--'1'&x"5FC0",'1'&x"5FC1",'1'&x"5FC2",'1'&x"5FC3",'1'&x"5FC4",'1'&x"5FC5",'1'&x"5FC6",'1'&x"5FC7",'1'&x"5FC8",'1'&x"5FC9",'1'&x"5FCA",'1'&x"5FCB",'1'&x"5FCC",'1'&x"5FCD",'1'&x"5FCE",'1'&x"5FCF",
+--'1'&x"5FD0",'1'&x"5FD1",'1'&x"5FD2",'1'&x"5FD3",'1'&x"5FD4",'1'&x"5FD5",'1'&x"5FD6",'1'&x"5FD7",'1'&x"5FD8",'1'&x"5FD9",'1'&x"5FDA",'1'&x"5FDB",'1'&x"5FDC",'1'&x"5FDD",'1'&x"5FDE",'1'&x"5FDF",
+--'1'&x"5FE0",'1'&x"5FE1",'1'&x"5FE2",'1'&x"5FE3",'1'&x"5FE4",'1'&x"5FE5",'1'&x"5FE6",'1'&x"5FE7",'1'&x"5FE8",'1'&x"5FE9",'1'&x"5FEA",'1'&x"5FEB",'1'&x"5FEC",'1'&x"5FED",'1'&x"5FEE",'1'&x"5FEF",
+--'1'&x"5FF0",'1'&x"5FF1",'1'&x"5FF2",'1'&x"5FF3",'1'&x"5FF4",'1'&x"5FF5",'1'&x"5FF6",'1'&x"5FF7",'1'&x"5FF8",'1'&x"5FF9",'1'&x"5FFA",'1'&x"5FFB",'1'&x"5FFC",'1'&x"5FFD",'1'&x"5FFE",'1'&x"5FFF",
+--'1'&x"6000",'1'&x"6001",'1'&x"6002",'1'&x"6003",'1'&x"6004",'1'&x"6005",'1'&x"6006",'1'&x"6007",'1'&x"6008",'1'&x"6009",'1'&x"600A",'1'&x"600B",'1'&x"600C",'1'&x"600D",'1'&x"600E",'1'&x"600F",
+--'1'&x"6010",'1'&x"6011",'1'&x"6012",'1'&x"6013",'1'&x"6014",'1'&x"6015",'1'&x"6016",'1'&x"6017",'1'&x"6018",'1'&x"6019",'1'&x"601A",'1'&x"601B",'1'&x"601C",'1'&x"601D",'1'&x"601E",'1'&x"601F",
+--'1'&x"6020",'1'&x"6021",'1'&x"6022",'1'&x"6023",'1'&x"6024",'1'&x"6025",'1'&x"6026",'1'&x"6027",'1'&x"6028",'1'&x"6029",'1'&x"602A",'1'&x"602B",'1'&x"602C",'1'&x"602D",'1'&x"602E",'1'&x"602F",
+--'1'&x"6030",'1'&x"6031",'1'&x"6032",'1'&x"6033",'1'&x"6034",'1'&x"6035",'1'&x"6036",'1'&x"6037",'1'&x"6038",'1'&x"6039",'1'&x"603A",'1'&x"603B",'1'&x"603C",'1'&x"603D",'1'&x"603E",'1'&x"603F",
+--'1'&x"6040",'1'&x"6041",'1'&x"6042",'1'&x"6043",'1'&x"6044",'1'&x"6045",'1'&x"6046",'1'&x"6047",'1'&x"6048",'1'&x"6049",'1'&x"604A",'1'&x"604B",'1'&x"604C",'1'&x"604D",'1'&x"604E",'1'&x"604F",
+--'1'&x"6050",'1'&x"6051",'1'&x"6052",'1'&x"6053",'1'&x"6054",'1'&x"6055",'1'&x"6056",'1'&x"6057",'1'&x"6058",'1'&x"6059",'1'&x"605A",'1'&x"605B",'1'&x"605C",'1'&x"605D",'1'&x"605E",'1'&x"605F",
+--'1'&x"6060",'1'&x"6061",'1'&x"6062",'1'&x"6063",'1'&x"6064",'1'&x"6065",'1'&x"6066",'1'&x"6067",'1'&x"6068",'1'&x"6069",'1'&x"606A",'1'&x"606B",'1'&x"606C",'1'&x"606D",'1'&x"606E",'1'&x"606F",
+--'1'&x"6070",'1'&x"6071",'1'&x"6072",'1'&x"6073",'1'&x"6074",'1'&x"6075",'1'&x"6076",'1'&x"6077",'1'&x"6078",'1'&x"6079",'1'&x"607A",'1'&x"607B",'1'&x"607C",'1'&x"607D",'1'&x"607E",'1'&x"607F",
+--'1'&x"6080",'1'&x"6081",'1'&x"6082",'1'&x"6083",'1'&x"6084",'1'&x"6085",'1'&x"6086",'1'&x"6087",'1'&x"6088",'1'&x"6089",'1'&x"608A",'1'&x"608B",'1'&x"608C",'1'&x"608D",'1'&x"608E",'1'&x"608F",
+--'1'&x"6090",'1'&x"6091",'1'&x"6092",'1'&x"6093",'1'&x"6094",'1'&x"6095",'1'&x"6096",'1'&x"6097",'1'&x"6098",'1'&x"6099",'1'&x"609A",'1'&x"609B",'1'&x"609C",'1'&x"609D",'1'&x"609E",'1'&x"609F",
+--'1'&x"60A0",'1'&x"60A1",'1'&x"60A2",'1'&x"60A3",'1'&x"60A4",'1'&x"60A5",'1'&x"60A6",'1'&x"60A7",'1'&x"60A8",'1'&x"60A9",'1'&x"60AA",'1'&x"60AB",'1'&x"60AC",'1'&x"60AD",'1'&x"60AE",'1'&x"60AF",
+--'1'&x"60B0",'1'&x"60B1",'1'&x"60B2",'1'&x"60B3",'1'&x"60B4",'1'&x"60B5",'1'&x"60B6",'1'&x"60B7",'1'&x"60B8",'1'&x"60B9",'1'&x"60BA",'1'&x"60BB",'1'&x"60BC",'1'&x"60BD",'1'&x"60BE",'1'&x"60BF",
+--'1'&x"60C0",'1'&x"60C1",'1'&x"60C2",'1'&x"60C3",'1'&x"60C4",'1'&x"60C5",'1'&x"60C6",'1'&x"60C7",'1'&x"60C8",'1'&x"60C9",'1'&x"60CA",'1'&x"60CB",'1'&x"60CC",'1'&x"60CD",'1'&x"60CE",'1'&x"60CF",
+--'1'&x"60D0",'1'&x"60D1",'1'&x"60D2",'1'&x"60D3",'1'&x"60D4",'1'&x"60D5",'1'&x"60D6",'1'&x"60D7",'1'&x"60D8",'1'&x"60D9",'1'&x"60DA",'1'&x"60DB",'1'&x"60DC",'1'&x"60DD",'1'&x"60DE",'1'&x"60DF",
+--'1'&x"60E0",'1'&x"60E1",'1'&x"60E2",'1'&x"60E3",'1'&x"60E4",'1'&x"60E5",'1'&x"60E6",'1'&x"60E7",'1'&x"60E8",'1'&x"60E9",'1'&x"60EA",'1'&x"60EB",'1'&x"60EC",'1'&x"60ED",'1'&x"60EE",'1'&x"60EF",
+--'1'&x"60F0",'1'&x"60F1",'1'&x"60F2",'1'&x"60F3",'1'&x"60F4",'1'&x"60F5",'1'&x"60F6",'1'&x"60F7",'1'&x"60F8",'1'&x"60F9",'1'&x"60FA",'1'&x"60FB",'1'&x"60FC",'1'&x"60FD",'1'&x"60FE",'1'&x"60FF",
+--'1'&x"6100",'1'&x"6101",'1'&x"6102",'1'&x"6103",'1'&x"6104",'1'&x"6105",'1'&x"6106",'1'&x"6107",'1'&x"6108",'1'&x"6109",'1'&x"610A",'1'&x"610B",'1'&x"610C",'1'&x"610D",'1'&x"610E",'1'&x"610F",
+--'1'&x"6110",'1'&x"6111",'1'&x"6112",'1'&x"6113",'1'&x"6114",'1'&x"6115",'1'&x"6116",'1'&x"6117",'1'&x"6118",'1'&x"6119",'1'&x"611A",'1'&x"611B",'1'&x"611C",'1'&x"611D",'1'&x"611E",'1'&x"611F",
+--'1'&x"6120",'1'&x"6121",'1'&x"6122",'1'&x"6123",'1'&x"6124",'1'&x"6125",'1'&x"6126",'1'&x"6127",'1'&x"6128",'1'&x"6129",'1'&x"612A",'1'&x"612B",'1'&x"612C",'1'&x"612D",'1'&x"612E",'1'&x"612F",
+--'1'&x"6130",'1'&x"6131",'1'&x"6132",'1'&x"6133",'1'&x"6134",'1'&x"6135",'1'&x"6136",'1'&x"6137",'1'&x"6138",'1'&x"6139",'1'&x"613A",'1'&x"613B",'1'&x"613C",'1'&x"613D",'1'&x"613E",'1'&x"613F",
+--'1'&x"6140",'1'&x"6141",'1'&x"6142",'1'&x"6143",'1'&x"6144",'1'&x"6145",'1'&x"6146",'1'&x"6147",'1'&x"6148",'1'&x"6149",'1'&x"614A",'1'&x"614B",'1'&x"614C",'1'&x"614D",'1'&x"614E",'1'&x"614F",
+--'1'&x"6150",'1'&x"6151",'1'&x"6152",'1'&x"6153",'1'&x"6154",'1'&x"6155",'1'&x"6156",'1'&x"6157",'1'&x"6158",'1'&x"6159",'1'&x"615A",'1'&x"615B",'1'&x"615C",'1'&x"615D",'1'&x"615E",'1'&x"615F",
+--'1'&x"6160",'1'&x"6161",'1'&x"6162",'1'&x"6163",'1'&x"6164",'1'&x"6165",'1'&x"6166",'1'&x"6167",'1'&x"6168",'1'&x"6169",'1'&x"616A",'1'&x"616B",'1'&x"616C",'1'&x"616D",'1'&x"616E",'1'&x"616F",
+--'1'&x"6170",'1'&x"6171",'1'&x"6172",'1'&x"6173",'1'&x"6174",'1'&x"6175",'1'&x"6176",'1'&x"6177",'1'&x"6178",'1'&x"6179",'1'&x"617A",'1'&x"617B",'1'&x"617C",'1'&x"617D",'1'&x"617E",'1'&x"617F",
+--'1'&x"6180",'1'&x"6181",'1'&x"6182",'1'&x"6183",'1'&x"6184",'1'&x"6185",'1'&x"6186",'1'&x"6187",'1'&x"6188",'1'&x"6189",'1'&x"618A",'1'&x"618B",'1'&x"618C",'1'&x"618D",'1'&x"618E",'1'&x"618F",
+--'1'&x"6190",'1'&x"6191",'1'&x"6192",'1'&x"6193",'1'&x"6194",'1'&x"6195",'1'&x"6196",'1'&x"6197",'1'&x"6198",'1'&x"6199",'1'&x"619A",'1'&x"619B",'1'&x"619C",'1'&x"619D",'1'&x"619E",'1'&x"619F",
+--'1'&x"61A0",'1'&x"61A1",'1'&x"61A2",'1'&x"61A3",'1'&x"61A4",'1'&x"61A5",'1'&x"61A6",'1'&x"61A7",'1'&x"61A8",'1'&x"61A9",'1'&x"61AA",'1'&x"61AB",'1'&x"61AC",'1'&x"61AD",'1'&x"61AE",'1'&x"61AF",
+--'1'&x"61B0",'1'&x"61B1",'1'&x"61B2",'1'&x"61B3",'1'&x"61B4",'1'&x"61B5",'1'&x"61B6",'1'&x"61B7",'1'&x"61B8",'1'&x"61B9",'1'&x"61BA",'1'&x"61BB",'1'&x"61BC",'1'&x"61BD",'1'&x"61BE",'1'&x"61BF",
+--'1'&x"61C0",'1'&x"61C1",'1'&x"61C2",'1'&x"61C3",'1'&x"61C4",'1'&x"61C5",'1'&x"61C6",'1'&x"61C7",'1'&x"61C8",'1'&x"61C9",'1'&x"61CA",'1'&x"61CB",'1'&x"61CC",'1'&x"61CD",'1'&x"61CE",'1'&x"61CF",
+--'1'&x"61D0",'1'&x"61D1",'1'&x"61D2",'1'&x"61D3",'1'&x"61D4",'1'&x"61D5",'1'&x"61D6",'1'&x"61D7",'1'&x"61D8",'1'&x"61D9",'1'&x"61DA",'1'&x"61DB",'1'&x"61DC",'1'&x"61DD",'1'&x"61DE",'1'&x"61DF",
+--'1'&x"61E0",'1'&x"61E1",'1'&x"61E2",'1'&x"61E3",'1'&x"61E4",'1'&x"61E5",'1'&x"61E6",'1'&x"61E7",'1'&x"61E8",'1'&x"61E9",'1'&x"61EA",'1'&x"61EB",'1'&x"61EC",'1'&x"61ED",'1'&x"61EE",'1'&x"61EF",
+--'1'&x"61F0",'1'&x"61F1",'1'&x"61F2",'1'&x"61F3",'1'&x"61F4",'1'&x"61F5",'1'&x"61F6",'1'&x"61F7",'1'&x"61F8",'1'&x"61F9",'1'&x"61FA",'1'&x"61FB",'1'&x"61FC",'1'&x"61FD",'1'&x"61FE",'1'&x"61FF",
+--'1'&x"6200",'1'&x"6201",'1'&x"6202",'1'&x"6203",'1'&x"6204",'1'&x"6205",'1'&x"6206",'1'&x"6207",'1'&x"6208",'1'&x"6209",'1'&x"620A",'1'&x"620B",'1'&x"620C",'1'&x"620D",'1'&x"620E",'1'&x"620F",
+--'1'&x"6210",'1'&x"6211",'1'&x"6212",'1'&x"6213",'1'&x"6214",'1'&x"6215",'1'&x"6216",'1'&x"6217",'1'&x"6218",'1'&x"6219",'1'&x"621A",'1'&x"621B",'1'&x"621C",'1'&x"621D",'1'&x"621E",'1'&x"621F",
+--'1'&x"6220",'1'&x"6221",'1'&x"6222",'1'&x"6223",'1'&x"6224",'1'&x"6225",'1'&x"6226",'1'&x"6227",'1'&x"6228",'1'&x"6229",'1'&x"622A",'1'&x"622B",'1'&x"622C",'1'&x"622D",'1'&x"622E",'1'&x"622F",
+--'1'&x"6230",'1'&x"6231",'1'&x"6232",'1'&x"6233",'1'&x"6234",'1'&x"6235",'1'&x"6236",'1'&x"6237",'1'&x"6238",'1'&x"6239",'1'&x"623A",'1'&x"623B",'1'&x"623C",'1'&x"623D",'1'&x"623E",'1'&x"623F",
+--'1'&x"6240",'1'&x"6241",'1'&x"6242",'1'&x"6243",'1'&x"6244",'1'&x"6245",'1'&x"6246",'1'&x"6247",'1'&x"6248",'1'&x"6249",'1'&x"624A",'1'&x"624B",'1'&x"624C",'1'&x"624D",'1'&x"624E",'1'&x"624F",
+--'1'&x"6250",'1'&x"6251",'1'&x"6252",'1'&x"6253",'1'&x"6254",'1'&x"6255",'1'&x"6256",'1'&x"6257",'1'&x"6258",'1'&x"6259",'1'&x"625A",'1'&x"625B",'1'&x"625C",'1'&x"625D",'1'&x"625E",'1'&x"625F",
+--'1'&x"6260",'1'&x"6261",'1'&x"6262",'1'&x"6263",'1'&x"6264",'1'&x"6265",'1'&x"6266",'1'&x"6267",'1'&x"6268",'1'&x"6269",'1'&x"626A",'1'&x"626B",'1'&x"626C",'1'&x"626D",'1'&x"626E",'1'&x"626F",
+--'1'&x"6270",'1'&x"6271",'1'&x"6272",'1'&x"6273",'1'&x"6274",'1'&x"6275",'1'&x"6276",'1'&x"6277",'1'&x"6278",'1'&x"6279",'1'&x"627A",'1'&x"627B",'1'&x"627C",'1'&x"627D",'1'&x"627E",'1'&x"627F",
+--'1'&x"6280",'1'&x"6281",'1'&x"6282",'1'&x"6283",'1'&x"6284",'1'&x"6285",'1'&x"6286",'1'&x"6287",'1'&x"6288",'1'&x"6289",'1'&x"628A",'1'&x"628B",'1'&x"628C",'1'&x"628D",'1'&x"628E",'1'&x"628F",
+--'1'&x"6290",'1'&x"6291",'1'&x"6292",'1'&x"6293",'1'&x"6294",'1'&x"6295",'1'&x"6296",'1'&x"6297",'1'&x"6298",'1'&x"6299",'1'&x"629A",'1'&x"629B",'1'&x"629C",'1'&x"629D",'1'&x"629E",'1'&x"629F",
+--'1'&x"62A0",'1'&x"62A1",'1'&x"62A2",'1'&x"62A3",'1'&x"62A4",'1'&x"62A5",'1'&x"62A6",'1'&x"62A7",'1'&x"62A8",'1'&x"62A9",'1'&x"62AA",'1'&x"62AB",'1'&x"62AC",'1'&x"62AD",'1'&x"62AE",'1'&x"62AF",
+--'1'&x"62B0",'1'&x"62B1",'1'&x"62B2",'1'&x"62B3",'1'&x"62B4",'1'&x"62B5",'1'&x"62B6",'1'&x"62B7",'1'&x"62B8",'1'&x"62B9",'1'&x"62BA",'1'&x"62BB",'1'&x"62BC",'1'&x"62BD",'1'&x"62BE",'1'&x"62BF",
+--'1'&x"62C0",'1'&x"62C1",'1'&x"62C2",'1'&x"62C3",'1'&x"62C4",'1'&x"62C5",'1'&x"62C6",'1'&x"62C7",'1'&x"62C8",'1'&x"62C9",'1'&x"62CA",'1'&x"62CB",'1'&x"62CC",'1'&x"62CD",'1'&x"62CE",'1'&x"62CF",
+--'1'&x"62D0",'1'&x"62D1",'1'&x"62D2",'1'&x"62D3",'1'&x"62D4",'1'&x"62D5",'1'&x"62D6",'1'&x"62D7",'1'&x"62D8",'1'&x"62D9",'1'&x"62DA",'1'&x"62DB",'1'&x"62DC",'1'&x"62DD",'1'&x"62DE",'1'&x"62DF",
+--'1'&x"62E0",'1'&x"62E1",'1'&x"62E2",'1'&x"62E3",'1'&x"62E4",'1'&x"62E5",'1'&x"62E6",'1'&x"62E7",'1'&x"62E8",'1'&x"62E9",'1'&x"62EA",'1'&x"62EB",'1'&x"62EC",'1'&x"62ED",'1'&x"62EE",'1'&x"62EF",
+--'1'&x"62F0",'1'&x"62F1",'1'&x"62F2",'1'&x"62F3",'1'&x"62F4",'1'&x"62F5",'1'&x"62F6",'1'&x"62F7",'1'&x"62F8",'1'&x"62F9",'1'&x"62FA",'1'&x"62FB",'1'&x"62FC",'1'&x"62FD",'1'&x"62FE",'1'&x"62FF",
+--'1'&x"6300",'1'&x"6301",'1'&x"6302",'1'&x"6303",'1'&x"6304",'1'&x"6305",'1'&x"6306",'1'&x"6307",'1'&x"6308",'1'&x"6309",'1'&x"630A",'1'&x"630B",'1'&x"630C",'1'&x"630D",'1'&x"630E",'1'&x"630F",
+--'1'&x"6310",'1'&x"6311",'1'&x"6312",'1'&x"6313",'1'&x"6314",'1'&x"6315",'1'&x"6316",'1'&x"6317",'1'&x"6318",'1'&x"6319",'1'&x"631A",'1'&x"631B",'1'&x"631C",'1'&x"631D",'1'&x"631E",'1'&x"631F",
+--'1'&x"6320",'1'&x"6321",'1'&x"6322",'1'&x"6323",'1'&x"6324",'1'&x"6325",'1'&x"6326",'1'&x"6327",'1'&x"6328",'1'&x"6329",'1'&x"632A",'1'&x"632B",'1'&x"632C",'1'&x"632D",'1'&x"632E",'1'&x"632F",
+--'1'&x"6330",'1'&x"6331",'1'&x"6332",'1'&x"6333",'1'&x"6334",'1'&x"6335",'1'&x"6336",'1'&x"6337",'1'&x"6338",'1'&x"6339",'1'&x"633A",'1'&x"633B",'1'&x"633C",'1'&x"633D",'1'&x"633E",'1'&x"633F",
+--'1'&x"6340",'1'&x"6341",'1'&x"6342",'1'&x"6343",'1'&x"6344",'1'&x"6345",'1'&x"6346",'1'&x"6347",'1'&x"6348",'1'&x"6349",'1'&x"634A",'1'&x"634B",'1'&x"634C",'1'&x"634D",'1'&x"634E",'1'&x"634F",
+--'1'&x"6350",'1'&x"6351",'1'&x"6352",'1'&x"6353",'1'&x"6354",'1'&x"6355",'1'&x"6356",'1'&x"6357",'1'&x"6358",'1'&x"6359",'1'&x"635A",'1'&x"635B",'1'&x"635C",'1'&x"635D",'1'&x"635E",'1'&x"635F",
+--'1'&x"6360",'1'&x"6361",'1'&x"6362",'1'&x"6363",'1'&x"6364",'1'&x"6365",'1'&x"6366",'1'&x"6367",'1'&x"6368",'1'&x"6369",'1'&x"636A",'1'&x"636B",'1'&x"636C",'1'&x"636D",'1'&x"636E",'1'&x"636F",
+--'1'&x"6370",'1'&x"6371",'1'&x"6372",'1'&x"6373",'1'&x"6374",'1'&x"6375",'1'&x"6376",'1'&x"6377",'1'&x"6378",'1'&x"6379",'1'&x"637A",'1'&x"637B",'1'&x"637C",'1'&x"637D",'1'&x"637E",'1'&x"637F",
+--'1'&x"6380",'1'&x"6381",'1'&x"6382",'1'&x"6383",'1'&x"6384",'1'&x"6385",'1'&x"6386",'1'&x"6387",'1'&x"6388",'1'&x"6389",'1'&x"638A",'1'&x"638B",'1'&x"638C",'1'&x"638D",'1'&x"638E",'1'&x"638F",
+--'1'&x"6390",'1'&x"6391",'1'&x"6392",'1'&x"6393",'1'&x"6394",'1'&x"6395",'1'&x"6396",'1'&x"6397",'1'&x"6398",'1'&x"6399",'1'&x"639A",'1'&x"639B",'1'&x"639C",'1'&x"639D",'1'&x"639E",'1'&x"639F",
+--'1'&x"63A0",'1'&x"63A1",'1'&x"63A2",'1'&x"63A3",'1'&x"63A4",'1'&x"63A5",'1'&x"63A6",'1'&x"63A7",'1'&x"63A8",'1'&x"63A9",'1'&x"63AA",'1'&x"63AB",'1'&x"63AC",'1'&x"63AD",'1'&x"63AE",'1'&x"63AF",
+--'1'&x"63B0",'1'&x"63B1",'1'&x"63B2",'1'&x"63B3",'1'&x"63B4",'1'&x"63B5",'1'&x"63B6",'1'&x"63B7",'1'&x"63B8",'1'&x"63B9",'1'&x"63BA",'1'&x"63BB",'1'&x"63BC",'1'&x"63BD",'1'&x"63BE",'1'&x"63BF",
+--'1'&x"63C0",'1'&x"63C1",'1'&x"63C2",'1'&x"63C3",'1'&x"63C4",'1'&x"63C5",'1'&x"63C6",'1'&x"63C7",'1'&x"63C8",'1'&x"63C9",'1'&x"63CA",'1'&x"63CB",'1'&x"63CC",'1'&x"63CD",'1'&x"63CE",'1'&x"63CF",
+--'1'&x"63D0",'1'&x"63D1",'1'&x"63D2",'1'&x"63D3",'1'&x"63D4",'1'&x"63D5",'1'&x"63D6",'1'&x"63D7",'1'&x"63D8",'1'&x"63D9",'1'&x"63DA",'1'&x"63DB",'1'&x"63DC",'1'&x"63DD",'1'&x"63DE",'1'&x"63DF",
+--'1'&x"63E0",'1'&x"63E1",'1'&x"63E2",'1'&x"63E3",'1'&x"63E4",'1'&x"63E5",'1'&x"63E6",'1'&x"63E7",'1'&x"63E8",'1'&x"63E9",'1'&x"63EA",'1'&x"63EB",'1'&x"63EC",'1'&x"63ED",'1'&x"63EE",'1'&x"63EF",
+--'1'&x"63F0",'1'&x"63F1",'1'&x"63F2",'1'&x"63F3",'1'&x"63F4",'1'&x"63F5",'1'&x"63F6",'1'&x"63F7",'1'&x"63F8",'1'&x"63F9",'1'&x"63FA",'1'&x"63FB",'1'&x"63FC",'1'&x"63FD",'1'&x"63FE",'1'&x"63FF",
+--'1'&x"6400",'1'&x"6401",'1'&x"6402",'1'&x"6403",'1'&x"6404",'1'&x"6405",'1'&x"6406",'1'&x"6407",'1'&x"6408",'1'&x"6409",'1'&x"640A",'1'&x"640B",'1'&x"640C",'1'&x"640D",'1'&x"640E",'1'&x"640F",
+--'1'&x"6410",'1'&x"6411",'1'&x"6412",'1'&x"6413",'1'&x"6414",'1'&x"6415",'1'&x"6416",'1'&x"6417",'1'&x"6418",'1'&x"6419",'1'&x"641A",'1'&x"641B",'1'&x"641C",'1'&x"641D",'1'&x"641E",'1'&x"641F",
+--'1'&x"6420",'1'&x"6421",'1'&x"6422",'1'&x"6423",'1'&x"6424",'1'&x"6425",'1'&x"6426",'1'&x"6427",'1'&x"6428",'1'&x"6429",'1'&x"642A",'1'&x"642B",'1'&x"642C",'1'&x"642D",'1'&x"642E",'1'&x"642F",
+--'1'&x"6430",'1'&x"6431",'1'&x"6432",'1'&x"6433",'1'&x"6434",'1'&x"6435",'1'&x"6436",'1'&x"6437",'1'&x"6438",'1'&x"6439",'1'&x"643A",'1'&x"643B",'1'&x"643C",'1'&x"643D",'1'&x"643E",'1'&x"643F",
+--'1'&x"6440",'1'&x"6441",'1'&x"6442",'1'&x"6443",'1'&x"6444",'1'&x"6445",'1'&x"6446",'1'&x"6447",'1'&x"6448",'1'&x"6449",'1'&x"644A",'1'&x"644B",'1'&x"644C",'1'&x"644D",'1'&x"644E",'1'&x"644F",
+--'1'&x"6450",'1'&x"6451",'1'&x"6452",'1'&x"6453",'1'&x"6454",'1'&x"6455",'1'&x"6456",'1'&x"6457",'1'&x"6458",'1'&x"6459",'1'&x"645A",'1'&x"645B",'1'&x"645C",'1'&x"645D",'1'&x"645E",'1'&x"645F",
+--'1'&x"6460",'1'&x"6461",'1'&x"6462",'1'&x"6463",'1'&x"6464",'1'&x"6465",'1'&x"6466",'1'&x"6467",'1'&x"6468",'1'&x"6469",'1'&x"646A",'1'&x"646B",'1'&x"646C",'1'&x"646D",'1'&x"646E",'1'&x"646F",
+--'1'&x"6470",'1'&x"6471",'1'&x"6472",'1'&x"6473",'1'&x"6474",'1'&x"6475",'1'&x"6476",'1'&x"6477",'1'&x"6478",'1'&x"6479",'1'&x"647A",'1'&x"647B",'1'&x"647C",'1'&x"647D",'1'&x"647E",'1'&x"647F",
+--'1'&x"6480",'1'&x"6481",'1'&x"6482",'1'&x"6483",'1'&x"6484",'1'&x"6485",'1'&x"6486",'1'&x"6487",'1'&x"6488",'1'&x"6489",'1'&x"648A",'1'&x"648B",'1'&x"648C",'1'&x"648D",'1'&x"648E",'1'&x"648F",
+--'1'&x"6490",'1'&x"6491",'1'&x"6492",'1'&x"6493",'1'&x"6494",'1'&x"6495",'1'&x"6496",'1'&x"6497",'1'&x"6498",'1'&x"6499",'1'&x"649A",'1'&x"649B",'1'&x"649C",'1'&x"649D",'1'&x"649E",'1'&x"649F",
+--'1'&x"64A0",'1'&x"64A1",'1'&x"64A2",'1'&x"64A3",'1'&x"64A4",'1'&x"64A5",'1'&x"64A6",'1'&x"64A7",'1'&x"64A8",'1'&x"64A9",'1'&x"64AA",'1'&x"64AB",'1'&x"64AC",'1'&x"64AD",'1'&x"64AE",'1'&x"64AF",
+--'1'&x"64B0",'1'&x"64B1",'1'&x"64B2",'1'&x"64B3",'1'&x"64B4",'1'&x"64B5",'1'&x"64B6",'1'&x"64B7",'1'&x"64B8",'1'&x"64B9",'1'&x"64BA",'1'&x"64BB",'1'&x"64BC",'1'&x"64BD",'1'&x"64BE",'1'&x"64BF",
+--'1'&x"64C0",'1'&x"64C1",'1'&x"64C2",'1'&x"64C3",'1'&x"64C4",'1'&x"64C5",'1'&x"64C6",'1'&x"64C7",'1'&x"64C8",'1'&x"64C9",'1'&x"64CA",'1'&x"64CB",'1'&x"64CC",'1'&x"64CD",'1'&x"64CE",'1'&x"64CF",
+--'1'&x"64D0",'1'&x"64D1",'1'&x"64D2",'1'&x"64D3",'1'&x"64D4",'1'&x"64D5",'1'&x"64D6",'1'&x"64D7",'1'&x"64D8",'1'&x"64D9",'1'&x"64DA",'1'&x"64DB",'1'&x"64DC",'1'&x"64DD",'1'&x"64DE",'1'&x"64DF",
+--'1'&x"64E0",'1'&x"64E1",'1'&x"64E2",'1'&x"64E3",'1'&x"64E4",'1'&x"64E5",'1'&x"64E6",'1'&x"64E7",'1'&x"64E8",'1'&x"64E9",'1'&x"64EA",'1'&x"64EB",'1'&x"64EC",'1'&x"64ED",'1'&x"64EE",'1'&x"64EF",
+--'1'&x"64F0",'1'&x"64F1",'1'&x"64F2",'1'&x"64F3",'1'&x"64F4",'1'&x"64F5",'1'&x"64F6",'1'&x"64F7",'1'&x"64F8",'1'&x"64F9",'1'&x"64FA",'1'&x"64FB",'1'&x"64FC",'1'&x"64FD",'1'&x"64FE",'1'&x"64FF",
+--'1'&x"6500",'1'&x"6501",'1'&x"6502",'1'&x"6503",'1'&x"6504",'1'&x"6505",'1'&x"6506",'1'&x"6507",'1'&x"6508",'1'&x"6509",'1'&x"650A",'1'&x"650B",'1'&x"650C",'1'&x"650D",'1'&x"650E",'1'&x"650F",
+--'1'&x"6510",'1'&x"6511",'1'&x"6512",'1'&x"6513",'1'&x"6514",'1'&x"6515",'1'&x"6516",'1'&x"6517",'1'&x"6518",'1'&x"6519",'1'&x"651A",'1'&x"651B",'1'&x"651C",'1'&x"651D",'1'&x"651E",'1'&x"651F",
+--'1'&x"6520",'1'&x"6521",'1'&x"6522",'1'&x"6523",'1'&x"6524",'1'&x"6525",'1'&x"6526",'1'&x"6527",'1'&x"6528",'1'&x"6529",'1'&x"652A",'1'&x"652B",'1'&x"652C",'1'&x"652D",'1'&x"652E",'1'&x"652F",
+--'1'&x"6530",'1'&x"6531",'1'&x"6532",'1'&x"6533",'1'&x"6534",'1'&x"6535",'1'&x"6536",'1'&x"6537",'1'&x"6538",'1'&x"6539",'1'&x"653A",'1'&x"653B",'1'&x"653C",'1'&x"653D",'1'&x"653E",'1'&x"653F",
+--'1'&x"6540",'1'&x"6541",'1'&x"6542",'1'&x"6543",'1'&x"6544",'1'&x"6545",'1'&x"6546",'1'&x"6547",'1'&x"6548",'1'&x"6549",'1'&x"654A",'1'&x"654B",'1'&x"654C",'1'&x"654D",'1'&x"654E",'1'&x"654F",
+--'1'&x"6550",'1'&x"6551",'1'&x"6552",'1'&x"6553",'1'&x"6554",'1'&x"6555",'1'&x"6556",'1'&x"6557",'1'&x"6558",'1'&x"6559",'1'&x"655A",'1'&x"655B",'1'&x"655C",'1'&x"655D",'1'&x"655E",'1'&x"655F",
+--'1'&x"6560",'1'&x"6561",'1'&x"6562",'1'&x"6563",'1'&x"6564",'1'&x"6565",'1'&x"6566",'1'&x"6567",'1'&x"6568",'1'&x"6569",'1'&x"656A",'1'&x"656B",'1'&x"656C",'1'&x"656D",'1'&x"656E",'1'&x"656F",
+--'1'&x"6570",'1'&x"6571",'1'&x"6572",'1'&x"6573",'1'&x"6574",'1'&x"6575",'1'&x"6576",'1'&x"6577",'1'&x"6578",'1'&x"6579",'1'&x"657A",'1'&x"657B",'1'&x"657C",'1'&x"657D",'1'&x"657E",'1'&x"657F",
+--'1'&x"6580",'1'&x"6581",'1'&x"6582",'1'&x"6583",'1'&x"6584",'1'&x"6585",'1'&x"6586",'1'&x"6587",'1'&x"6588",'1'&x"6589",'1'&x"658A",'1'&x"658B",'1'&x"658C",'1'&x"658D",'1'&x"658E",'1'&x"658F",
+--'1'&x"6590",'1'&x"6591",'1'&x"6592",'1'&x"6593",'1'&x"6594",'1'&x"6595",'1'&x"6596",'1'&x"6597",'1'&x"6598",'1'&x"6599",'1'&x"659A",'1'&x"659B",'1'&x"659C",'1'&x"659D",'1'&x"659E",'1'&x"659F",
+--'1'&x"65A0",'1'&x"65A1",'1'&x"65A2",'1'&x"65A3",'1'&x"65A4",'1'&x"65A5",'1'&x"65A6",'1'&x"65A7",'1'&x"65A8",'1'&x"65A9",'1'&x"65AA",'1'&x"65AB",'1'&x"65AC",'1'&x"65AD",'1'&x"65AE",'1'&x"65AF",
+--'1'&x"65B0",'1'&x"65B1",'1'&x"65B2",'1'&x"65B3",'1'&x"65B4",'1'&x"65B5",'1'&x"65B6",'1'&x"65B7",'1'&x"65B8",'1'&x"65B9",'1'&x"65BA",'1'&x"65BB",'1'&x"65BC",'1'&x"65BD",'1'&x"65BE",'1'&x"65BF",
+--'1'&x"65C0",'1'&x"65C1",'1'&x"65C2",'1'&x"65C3",'1'&x"65C4",'1'&x"65C5",'1'&x"65C6",'1'&x"65C7",'1'&x"65C8",'1'&x"65C9",'1'&x"65CA",'1'&x"65CB",'1'&x"65CC",'1'&x"65CD",'1'&x"65CE",'1'&x"65CF",
+--'1'&x"65D0",'1'&x"65D1",'1'&x"65D2",'1'&x"65D3",'1'&x"65D4",'1'&x"65D5",'1'&x"65D6",'1'&x"65D7",'1'&x"65D8",'1'&x"65D9",'1'&x"65DA",'1'&x"65DB",'1'&x"65DC",'1'&x"65DD",'1'&x"65DE",'1'&x"65DF",
+--'1'&x"65E0",'1'&x"65E1",'1'&x"65E2",'1'&x"65E3",'1'&x"65E4",'1'&x"65E5",'1'&x"65E6",'1'&x"65E7",'1'&x"65E8",'1'&x"65E9",'1'&x"65EA",'1'&x"65EB",'1'&x"65EC",'1'&x"65ED",'1'&x"65EE",'1'&x"65EF",
+--'1'&x"65F0",'1'&x"65F1",'1'&x"65F2",'1'&x"65F3",'1'&x"65F4",'1'&x"65F5",'1'&x"65F6",'1'&x"65F7",'1'&x"65F8",'1'&x"65F9",'1'&x"65FA",'1'&x"65FB",'1'&x"65FC",'1'&x"65FD",'1'&x"65FE",'1'&x"65FF",
+--'1'&x"6600",'1'&x"6601",'1'&x"6602",'1'&x"6603",'1'&x"6604",'1'&x"6605",'1'&x"6606",'1'&x"6607",'1'&x"6608",'1'&x"6609",'1'&x"660A",'1'&x"660B",'1'&x"660C",'1'&x"660D",'1'&x"660E",'1'&x"660F",
+--'1'&x"6610",'1'&x"6611",'1'&x"6612",'1'&x"6613",'1'&x"6614",'1'&x"6615",'1'&x"6616",'1'&x"6617",'1'&x"6618",'1'&x"6619",'1'&x"661A",'1'&x"661B",'1'&x"661C",'1'&x"661D",'1'&x"661E",'1'&x"661F",
+--'1'&x"6620",'1'&x"6621",'1'&x"6622",'1'&x"6623",'1'&x"6624",'1'&x"6625",'1'&x"6626",'1'&x"6627",'1'&x"6628",'1'&x"6629",'1'&x"662A",'1'&x"662B",'1'&x"662C",'1'&x"662D",'1'&x"662E",'1'&x"662F",
+--'1'&x"6630",'1'&x"6631",'1'&x"6632",'1'&x"6633",'1'&x"6634",'1'&x"6635",'1'&x"6636",'1'&x"6637",'1'&x"6638",'1'&x"6639",'1'&x"663A",'1'&x"663B",'1'&x"663C",'1'&x"663D",'1'&x"663E",'1'&x"663F",
+--'1'&x"6640",'1'&x"6641",'1'&x"6642",'1'&x"6643",'1'&x"6644",'1'&x"6645",'1'&x"6646",'1'&x"6647",'1'&x"6648",'1'&x"6649",'1'&x"664A",'1'&x"664B",'1'&x"664C",'1'&x"664D",'1'&x"664E",'1'&x"664F",
+--'1'&x"6650",'1'&x"6651",'1'&x"6652",'1'&x"6653",'1'&x"6654",'1'&x"6655",'1'&x"6656",'1'&x"6657",'1'&x"6658",'1'&x"6659",'1'&x"665A",'1'&x"665B",'1'&x"665C",'1'&x"665D",'1'&x"665E",'1'&x"665F",
+--'1'&x"6660",'1'&x"6661",'1'&x"6662",'1'&x"6663",'1'&x"6664",'1'&x"6665",'1'&x"6666",'1'&x"6667",'1'&x"6668",'1'&x"6669",'1'&x"666A",'1'&x"666B",'1'&x"666C",'1'&x"666D",'1'&x"666E",'1'&x"666F",
+--'1'&x"6670",'1'&x"6671",'1'&x"6672",'1'&x"6673",'1'&x"6674",'1'&x"6675",'1'&x"6676",'1'&x"6677",'1'&x"6678",'1'&x"6679",'1'&x"667A",'1'&x"667B",'1'&x"667C",'1'&x"667D",'1'&x"667E",'1'&x"667F",
+--'1'&x"6680",'1'&x"6681",'1'&x"6682",'1'&x"6683",'1'&x"6684",'1'&x"6685",'1'&x"6686",'1'&x"6687",'1'&x"6688",'1'&x"6689",'1'&x"668A",'1'&x"668B",'1'&x"668C",'1'&x"668D",'1'&x"668E",'1'&x"668F",
+--'1'&x"6690",'1'&x"6691",'1'&x"6692",'1'&x"6693",'1'&x"6694",'1'&x"6695",'1'&x"6696",'1'&x"6697",'1'&x"6698",'1'&x"6699",'1'&x"669A",'1'&x"669B",'1'&x"669C",'1'&x"669D",'1'&x"669E",'1'&x"669F",
+--'1'&x"66A0",'1'&x"66A1",'1'&x"66A2",'1'&x"66A3",'1'&x"66A4",'1'&x"66A5",'1'&x"66A6",'1'&x"66A7",'1'&x"66A8",'1'&x"66A9",'1'&x"66AA",'1'&x"66AB",'1'&x"66AC",'1'&x"66AD",'1'&x"66AE",'1'&x"66AF",
+--'1'&x"66B0",'1'&x"66B1",'1'&x"66B2",'1'&x"66B3",'1'&x"66B4",'1'&x"66B5",'1'&x"66B6",'1'&x"66B7",'1'&x"66B8",'1'&x"66B9",'1'&x"66BA",'1'&x"66BB",'1'&x"66BC",'1'&x"66BD",'1'&x"66BE",'1'&x"66BF",
+--'1'&x"66C0",'1'&x"66C1",'1'&x"66C2",'1'&x"66C3",'1'&x"66C4",'1'&x"66C5",'1'&x"66C6",'1'&x"66C7",'1'&x"66C8",'1'&x"66C9",'1'&x"66CA",'1'&x"66CB",'1'&x"66CC",'1'&x"66CD",'1'&x"66CE",'1'&x"66CF",
+--'1'&x"66D0",'1'&x"66D1",'1'&x"66D2",'1'&x"66D3",'1'&x"66D4",'1'&x"66D5",'1'&x"66D6",'1'&x"66D7",'1'&x"66D8",'1'&x"66D9",'1'&x"66DA",'1'&x"66DB",'1'&x"66DC",'1'&x"66DD",'1'&x"66DE",'1'&x"66DF",
+--'1'&x"66E0",'1'&x"66E1",'1'&x"66E2",'1'&x"66E3",'1'&x"66E4",'1'&x"66E5",'1'&x"66E6",'1'&x"66E7",'1'&x"66E8",'1'&x"66E9",'1'&x"66EA",'1'&x"66EB",'1'&x"66EC",'1'&x"66ED",'1'&x"66EE",'1'&x"66EF",
+--'1'&x"66F0",'1'&x"66F1",'1'&x"66F2",'1'&x"66F3",'1'&x"66F4",'1'&x"66F5",'1'&x"66F6",'1'&x"66F7",'1'&x"66F8",'1'&x"66F9",'1'&x"66FA",'1'&x"66FB",'1'&x"66FC",'1'&x"66FD",'1'&x"66FE",'1'&x"66FF",
+--'1'&x"6700",'1'&x"6701",'1'&x"6702",'1'&x"6703",'1'&x"6704",'1'&x"6705",'1'&x"6706",'1'&x"6707",'1'&x"6708",'1'&x"6709",'1'&x"670A",'1'&x"670B",'1'&x"670C",'1'&x"670D",'1'&x"670E",'1'&x"670F",
+--'1'&x"6710",'1'&x"6711",'1'&x"6712",'1'&x"6713",'1'&x"6714",'1'&x"6715",'1'&x"6716",'1'&x"6717",'1'&x"6718",'1'&x"6719",'1'&x"671A",'1'&x"671B",'1'&x"671C",'1'&x"671D",'1'&x"671E",'1'&x"671F",
+--'1'&x"6720",'1'&x"6721",'1'&x"6722",'1'&x"6723",'1'&x"6724",'1'&x"6725",'1'&x"6726",'1'&x"6727",'1'&x"6728",'1'&x"6729",'1'&x"672A",'1'&x"672B",'1'&x"672C",'1'&x"672D",'1'&x"672E",'1'&x"672F",
+--'1'&x"6730",'1'&x"6731",'1'&x"6732",'1'&x"6733",'1'&x"6734",'1'&x"6735",'1'&x"6736",'1'&x"6737",'1'&x"6738",'1'&x"6739",'1'&x"673A",'1'&x"673B",'1'&x"673C",'1'&x"673D",'1'&x"673E",'1'&x"673F",
+--'1'&x"6740",'1'&x"6741",'1'&x"6742",'1'&x"6743",'1'&x"6744",'1'&x"6745",'1'&x"6746",'1'&x"6747",'1'&x"6748",'1'&x"6749",'1'&x"674A",'1'&x"674B",'1'&x"674C",'1'&x"674D",'1'&x"674E",'1'&x"674F",
+--'1'&x"6750",'1'&x"6751",'1'&x"6752",'1'&x"6753",'1'&x"6754",'1'&x"6755",'1'&x"6756",'1'&x"6757",'1'&x"6758",'1'&x"6759",'1'&x"675A",'1'&x"675B",'1'&x"675C",'1'&x"675D",'1'&x"675E",'1'&x"675F",
+--'1'&x"6760",'1'&x"6761",'1'&x"6762",'1'&x"6763",'1'&x"6764",'1'&x"6765",'1'&x"6766",'1'&x"6767",'1'&x"6768",'1'&x"6769",'1'&x"676A",'1'&x"676B",'1'&x"676C",'1'&x"676D",'1'&x"676E",'1'&x"676F",
+--'1'&x"6770",'1'&x"6771",'1'&x"6772",'1'&x"6773",'1'&x"6774",'1'&x"6775",'1'&x"6776",'1'&x"6777",'1'&x"6778",'1'&x"6779",'1'&x"677A",'1'&x"677B",'1'&x"677C",'1'&x"677D",'1'&x"677E",'1'&x"677F",
+--'1'&x"6780",'1'&x"6781",'1'&x"6782",'1'&x"6783",'1'&x"6784",'1'&x"6785",'1'&x"6786",'1'&x"6787",'1'&x"6788",'1'&x"6789",'1'&x"678A",'1'&x"678B",'1'&x"678C",'1'&x"678D",'1'&x"678E",'1'&x"678F",
+--'1'&x"6790",'1'&x"6791",'1'&x"6792",'1'&x"6793",'1'&x"6794",'1'&x"6795",'1'&x"6796",'1'&x"6797",'1'&x"6798",'1'&x"6799",'1'&x"679A",'1'&x"679B",'1'&x"679C",'1'&x"679D",'1'&x"679E",'1'&x"679F",
+--'1'&x"67A0",'1'&x"67A1",'1'&x"67A2",'1'&x"67A3",'1'&x"67A4",'1'&x"67A5",'1'&x"67A6",'1'&x"67A7",'1'&x"67A8",'1'&x"67A9",'1'&x"67AA",'1'&x"67AB",'1'&x"67AC",'1'&x"67AD",'1'&x"67AE",'1'&x"67AF",
+--'1'&x"67B0",'1'&x"67B1",'1'&x"67B2",'1'&x"67B3",'1'&x"67B4",'1'&x"67B5",'1'&x"67B6",'1'&x"67B7",'1'&x"67B8",'1'&x"67B9",'1'&x"67BA",'1'&x"67BB",'1'&x"67BC",'1'&x"67BD",'1'&x"67BE",'1'&x"67BF",
+--'1'&x"67C0",'1'&x"67C1",'1'&x"67C2",'1'&x"67C3",'1'&x"67C4",'1'&x"67C5",'1'&x"67C6",'1'&x"67C7",'1'&x"67C8",'1'&x"67C9",'1'&x"67CA",'1'&x"67CB",'1'&x"67CC",'1'&x"67CD",'1'&x"67CE",'1'&x"67CF",
+--'1'&x"67D0",'1'&x"67D1",'1'&x"67D2",'1'&x"67D3",'1'&x"67D4",'1'&x"67D5",'1'&x"67D6",'1'&x"67D7",'1'&x"67D8",'1'&x"67D9",'1'&x"67DA",'1'&x"67DB",'1'&x"67DC",'1'&x"67DD",'1'&x"67DE",'1'&x"67DF",
+--'1'&x"67E0",'1'&x"67E1",'1'&x"67E2",'1'&x"67E3",'1'&x"67E4",'1'&x"67E5",'1'&x"67E6",'1'&x"67E7",'1'&x"67E8",'1'&x"67E9",'1'&x"67EA",'1'&x"67EB",'1'&x"67EC",'1'&x"67ED",'1'&x"67EE",'1'&x"67EF",
+--'1'&x"67F0",'1'&x"67F1",'1'&x"67F2",'1'&x"67F3",'1'&x"67F4",'1'&x"67F5",'1'&x"67F6",'1'&x"67F7",'1'&x"67F8",'1'&x"67F9",'1'&x"67FA",'1'&x"67FB",'1'&x"67FC",'1'&x"67FD",'1'&x"67FE",'1'&x"67FF",
+--'1'&x"6800",'1'&x"6801",'1'&x"6802",'1'&x"6803",'1'&x"6804",'1'&x"6805",'1'&x"6806",'1'&x"6807",'1'&x"6808",'1'&x"6809",'1'&x"680A",'1'&x"680B",'1'&x"680C",'1'&x"680D",'1'&x"680E",'1'&x"680F",
+--'1'&x"6810",'1'&x"6811",'1'&x"6812",'1'&x"6813",'1'&x"6814",'1'&x"6815",'1'&x"6816",'1'&x"6817",'1'&x"6818",'1'&x"6819",'1'&x"681A",'1'&x"681B",'1'&x"681C",'1'&x"681D",'1'&x"681E",'1'&x"681F",
+--'1'&x"6820",'1'&x"6821",'1'&x"6822",'1'&x"6823",'1'&x"6824",'1'&x"6825",'1'&x"6826",'1'&x"6827",'1'&x"6828",'1'&x"6829",'1'&x"682A",'1'&x"682B",'1'&x"682C",'1'&x"682D",'1'&x"682E",'1'&x"682F",
+--'1'&x"6830",'1'&x"6831",'1'&x"6832",'1'&x"6833",'1'&x"6834",'1'&x"6835",'1'&x"6836",'1'&x"6837",'1'&x"6838",'1'&x"6839",'1'&x"683A",'1'&x"683B",'1'&x"683C",'1'&x"683D",'1'&x"683E",'1'&x"683F",
+--'1'&x"6840",'1'&x"6841",'1'&x"6842",'1'&x"6843",'1'&x"6844",'1'&x"6845",'1'&x"6846",'1'&x"6847",'1'&x"6848",'1'&x"6849",'1'&x"684A",'1'&x"684B",'1'&x"684C",'1'&x"684D",'1'&x"684E",'1'&x"684F",
+--'1'&x"6850",'1'&x"6851",'1'&x"6852",'1'&x"6853",'1'&x"6854",'1'&x"6855",'1'&x"6856",'1'&x"6857",'1'&x"6858",'1'&x"6859",'1'&x"685A",'1'&x"685B",'1'&x"685C",'1'&x"685D",'1'&x"685E",'1'&x"685F",
+--'1'&x"6860",'1'&x"6861",'1'&x"6862",'1'&x"6863",'1'&x"6864",'1'&x"6865",'1'&x"6866",'1'&x"6867",'1'&x"6868",'1'&x"6869",'1'&x"686A",'1'&x"686B",'1'&x"686C",'1'&x"686D",'1'&x"686E",'1'&x"686F",
+--'1'&x"6870",'1'&x"6871",'1'&x"6872",'1'&x"6873",'1'&x"6874",'1'&x"6875",'1'&x"6876",'1'&x"6877",'1'&x"6878",'1'&x"6879",'1'&x"687A",'1'&x"687B",'1'&x"687C",'1'&x"687D",'1'&x"687E",'1'&x"687F",
+--'1'&x"6880",'1'&x"6881",'1'&x"6882",'1'&x"6883",'1'&x"6884",'1'&x"6885",'1'&x"6886",'1'&x"6887",'1'&x"6888",'1'&x"6889",'1'&x"688A",'1'&x"688B",'1'&x"688C",'1'&x"688D",'1'&x"688E",'1'&x"688F",
+--'1'&x"6890",'1'&x"6891",'1'&x"6892",'1'&x"6893",'1'&x"6894",'1'&x"6895",'1'&x"6896",'1'&x"6897",'1'&x"6898",'1'&x"6899",'1'&x"689A",'1'&x"689B",'1'&x"689C",'1'&x"689D",'1'&x"689E",'1'&x"689F",
+--'1'&x"68A0",'1'&x"68A1",'1'&x"68A2",'1'&x"68A3",'1'&x"68A4",'1'&x"68A5",'1'&x"68A6",'1'&x"68A7",'1'&x"68A8",'1'&x"68A9",'1'&x"68AA",'1'&x"68AB",'1'&x"68AC",'1'&x"68AD",'1'&x"68AE",'1'&x"68AF",
+--'1'&x"68B0",'1'&x"68B1",'1'&x"68B2",'1'&x"68B3",'1'&x"68B4",'1'&x"68B5",'1'&x"68B6",'1'&x"68B7",'1'&x"68B8",'1'&x"68B9",'1'&x"68BA",'1'&x"68BB",'1'&x"68BC",'1'&x"68BD",'1'&x"68BE",'1'&x"68BF",
+--'1'&x"68C0",'1'&x"68C1",'1'&x"68C2",'1'&x"68C3",'1'&x"68C4",'1'&x"68C5",'1'&x"68C6",'1'&x"68C7",'1'&x"68C8",'1'&x"68C9",'1'&x"68CA",'1'&x"68CB",'1'&x"68CC",'1'&x"68CD",'1'&x"68CE",'1'&x"68CF",
+--'1'&x"68D0",'1'&x"68D1",'1'&x"68D2",'1'&x"68D3",'1'&x"68D4",'1'&x"68D5",'1'&x"68D6",'1'&x"68D7",'1'&x"68D8",'1'&x"68D9",'1'&x"68DA",'1'&x"68DB",'1'&x"68DC",'1'&x"68DD",'1'&x"68DE",'1'&x"68DF",
+--'1'&x"68E0",'1'&x"68E1",'1'&x"68E2",'1'&x"68E3",'1'&x"68E4",'1'&x"68E5",'1'&x"68E6",'1'&x"68E7",'1'&x"68E8",'1'&x"68E9",'1'&x"68EA",'1'&x"68EB",'1'&x"68EC",'1'&x"68ED",'1'&x"68EE",'1'&x"68EF",
+--'1'&x"68F0",'1'&x"68F1",'1'&x"68F2",'1'&x"68F3",'1'&x"68F4",'1'&x"68F5",'1'&x"68F6",'1'&x"68F7",'1'&x"68F8",'1'&x"68F9",'1'&x"68FA",'1'&x"68FB",'1'&x"68FC",'1'&x"68FD",'1'&x"68FE",'1'&x"68FF",
+--'1'&x"6900",'1'&x"6901",'1'&x"6902",'1'&x"6903",'1'&x"6904",'1'&x"6905",'1'&x"6906",'1'&x"6907",'1'&x"6908",'1'&x"6909",'1'&x"690A",'1'&x"690B",'1'&x"690C",'1'&x"690D",'1'&x"690E",'1'&x"690F",
+--'1'&x"6910",'1'&x"6911",'1'&x"6912",'1'&x"6913",'1'&x"6914",'1'&x"6915",'1'&x"6916",'1'&x"6917",'1'&x"6918",'1'&x"6919",'1'&x"691A",'1'&x"691B",'1'&x"691C",'1'&x"691D",'1'&x"691E",'1'&x"691F",
+--'1'&x"6920",'1'&x"6921",'1'&x"6922",'1'&x"6923",'1'&x"6924",'1'&x"6925",'1'&x"6926",'1'&x"6927",'1'&x"6928",'1'&x"6929",'1'&x"692A",'1'&x"692B",'1'&x"692C",'1'&x"692D",'1'&x"692E",'1'&x"692F",
+--'1'&x"6930",'1'&x"6931",'1'&x"6932",'1'&x"6933",'1'&x"6934",'1'&x"6935",'1'&x"6936",'1'&x"6937",'1'&x"6938",'1'&x"6939",'1'&x"693A",'1'&x"693B",'1'&x"693C",'1'&x"693D",'1'&x"693E",'1'&x"693F",
+--'1'&x"6940",'1'&x"6941",'1'&x"6942",'1'&x"6943",'1'&x"6944",'1'&x"6945",'1'&x"6946",'1'&x"6947",'1'&x"6948",'1'&x"6949",'1'&x"694A",'1'&x"694B",'1'&x"694C",'1'&x"694D",'1'&x"694E",'1'&x"694F",
+--'1'&x"6950",'1'&x"6951",'1'&x"6952",'1'&x"6953",'1'&x"6954",'1'&x"6955",'1'&x"6956",'1'&x"6957",'1'&x"6958",'1'&x"6959",'1'&x"695A",'1'&x"695B",'1'&x"695C",'1'&x"695D",'1'&x"695E",'1'&x"695F",
+--'1'&x"6960",'1'&x"6961",'1'&x"6962",'1'&x"6963",'1'&x"6964",'1'&x"6965",'1'&x"6966",'1'&x"6967",'1'&x"6968",'1'&x"6969",'1'&x"696A",'1'&x"696B",'1'&x"696C",'1'&x"696D",'1'&x"696E",'1'&x"696F",
+--'1'&x"6970",'1'&x"6971",'1'&x"6972",'1'&x"6973",'1'&x"6974",'1'&x"6975",'1'&x"6976",'1'&x"6977",'1'&x"6978",'1'&x"6979",'1'&x"697A",'1'&x"697B",'1'&x"697C",'1'&x"697D",'1'&x"697E",'1'&x"697F",
+--'1'&x"6980",'1'&x"6981",'1'&x"6982",'1'&x"6983",'1'&x"6984",'1'&x"6985",'1'&x"6986",'1'&x"6987",'1'&x"6988",'1'&x"6989",'1'&x"698A",'1'&x"698B",'1'&x"698C",'1'&x"698D",'1'&x"698E",'1'&x"698F",
+--'1'&x"6990",'1'&x"6991",'1'&x"6992",'1'&x"6993",'1'&x"6994",'1'&x"6995",'1'&x"6996",'1'&x"6997",'1'&x"6998",'1'&x"6999",'1'&x"699A",'1'&x"699B",'1'&x"699C",'1'&x"699D",'1'&x"699E",'1'&x"699F",
+--'1'&x"69A0",'1'&x"69A1",'1'&x"69A2",'1'&x"69A3",'1'&x"69A4",'1'&x"69A5",'1'&x"69A6",'1'&x"69A7",'1'&x"69A8",'1'&x"69A9",'1'&x"69AA",'1'&x"69AB",'1'&x"69AC",'1'&x"69AD",'1'&x"69AE",'1'&x"69AF",
+--'1'&x"69B0",'1'&x"69B1",'1'&x"69B2",'1'&x"69B3",'1'&x"69B4",'1'&x"69B5",'1'&x"69B6",'1'&x"69B7",'1'&x"69B8",'1'&x"69B9",'1'&x"69BA",'1'&x"69BB",'1'&x"69BC",'1'&x"69BD",'1'&x"69BE",'1'&x"69BF",
+--'1'&x"69C0",'1'&x"69C1",'1'&x"69C2",'1'&x"69C3",'1'&x"69C4",'1'&x"69C5",'1'&x"69C6",'1'&x"69C7",'1'&x"69C8",'1'&x"69C9",'1'&x"69CA",'1'&x"69CB",'1'&x"69CC",'1'&x"69CD",'1'&x"69CE",'1'&x"69CF",
+--'1'&x"69D0",'1'&x"69D1",'1'&x"69D2",'1'&x"69D3",'1'&x"69D4",'1'&x"69D5",'1'&x"69D6",'1'&x"69D7",'1'&x"69D8",'1'&x"69D9",'1'&x"69DA",'1'&x"69DB",'1'&x"69DC",'1'&x"69DD",'1'&x"69DE",'1'&x"69DF",
+--'1'&x"69E0",'1'&x"69E1",'1'&x"69E2",'1'&x"69E3",'1'&x"69E4",'1'&x"69E5",'1'&x"69E6",'1'&x"69E7",'1'&x"69E8",'1'&x"69E9",'1'&x"69EA",'1'&x"69EB",'1'&x"69EC",'1'&x"69ED",'1'&x"69EE",'1'&x"69EF",
+--'1'&x"69F0",'1'&x"69F1",'1'&x"69F2",'1'&x"69F3",'1'&x"69F4",'1'&x"69F5",'1'&x"69F6",'1'&x"69F7",'1'&x"69F8",'1'&x"69F9",'1'&x"69FA",'1'&x"69FB",'1'&x"69FC",'1'&x"69FD",'1'&x"69FE",'1'&x"69FF",
+--'1'&x"6A00",'1'&x"6A01",'1'&x"6A02",'1'&x"6A03",'1'&x"6A04",'1'&x"6A05",'1'&x"6A06",'1'&x"6A07",'1'&x"6A08",'1'&x"6A09",'1'&x"6A0A",'1'&x"6A0B",'1'&x"6A0C",'1'&x"6A0D",'1'&x"6A0E",'1'&x"6A0F",
+--'1'&x"6A10",'1'&x"6A11",'1'&x"6A12",'1'&x"6A13",'1'&x"6A14",'1'&x"6A15",'1'&x"6A16",'1'&x"6A17",'1'&x"6A18",'1'&x"6A19",'1'&x"6A1A",'1'&x"6A1B",'1'&x"6A1C",'1'&x"6A1D",'1'&x"6A1E",'1'&x"6A1F",
+--'1'&x"6A20",'1'&x"6A21",'1'&x"6A22",'1'&x"6A23",'1'&x"6A24",'1'&x"6A25",'1'&x"6A26",'1'&x"6A27",'1'&x"6A28",'1'&x"6A29",'1'&x"6A2A",'1'&x"6A2B",'1'&x"6A2C",'1'&x"6A2D",'1'&x"6A2E",'1'&x"6A2F",
+--'1'&x"6A30",'1'&x"6A31",'1'&x"6A32",'1'&x"6A33",'1'&x"6A34",'1'&x"6A35",'1'&x"6A36",'1'&x"6A37",'1'&x"6A38",'1'&x"6A39",'1'&x"6A3A",'1'&x"6A3B",'1'&x"6A3C",'1'&x"6A3D",'1'&x"6A3E",'1'&x"6A3F",
+--'1'&x"6A40",'1'&x"6A41",'1'&x"6A42",'1'&x"6A43",'1'&x"6A44",'1'&x"6A45",'1'&x"6A46",'1'&x"6A47",'1'&x"6A48",'1'&x"6A49",'1'&x"6A4A",'1'&x"6A4B",'1'&x"6A4C",'1'&x"6A4D",'1'&x"6A4E",'1'&x"6A4F",
+--'1'&x"6A50",'1'&x"6A51",'1'&x"6A52",'1'&x"6A53",'1'&x"6A54",'1'&x"6A55",'1'&x"6A56",'1'&x"6A57",'1'&x"6A58",'1'&x"6A59",'1'&x"6A5A",'1'&x"6A5B",'1'&x"6A5C",'1'&x"6A5D",'1'&x"6A5E",'1'&x"6A5F",
+--'1'&x"6A60",'1'&x"6A61",'1'&x"6A62",'1'&x"6A63",'1'&x"6A64",'1'&x"6A65",'1'&x"6A66",'1'&x"6A67",'1'&x"6A68",'1'&x"6A69",'1'&x"6A6A",'1'&x"6A6B",'1'&x"6A6C",'1'&x"6A6D",'1'&x"6A6E",'1'&x"6A6F",
+--'1'&x"6A70",'1'&x"6A71",'1'&x"6A72",'1'&x"6A73",'1'&x"6A74",'1'&x"6A75",'1'&x"6A76",'1'&x"6A77",'1'&x"6A78",'1'&x"6A79",'1'&x"6A7A",'1'&x"6A7B",'1'&x"6A7C",'1'&x"6A7D",'1'&x"6A7E",'1'&x"6A7F",
+--'1'&x"6A80",'1'&x"6A81",'1'&x"6A82",'1'&x"6A83",'1'&x"6A84",'1'&x"6A85",'1'&x"6A86",'1'&x"6A87",'1'&x"6A88",'1'&x"6A89",'1'&x"6A8A",'1'&x"6A8B",'1'&x"6A8C",'1'&x"6A8D",'1'&x"6A8E",'1'&x"6A8F",
+--'1'&x"6A90",'1'&x"6A91",'1'&x"6A92",'1'&x"6A93",'1'&x"6A94",'1'&x"6A95",'1'&x"6A96",'1'&x"6A97",'1'&x"6A98",'1'&x"6A99",'1'&x"6A9A",'1'&x"6A9B",'1'&x"6A9C",'1'&x"6A9D",'1'&x"6A9E",'1'&x"6A9F",
+--'1'&x"6AA0",'1'&x"6AA1",'1'&x"6AA2",'1'&x"6AA3",'1'&x"6AA4",'1'&x"6AA5",'1'&x"6AA6",'1'&x"6AA7",'1'&x"6AA8",'1'&x"6AA9",'1'&x"6AAA",'1'&x"6AAB",'1'&x"6AAC",'1'&x"6AAD",'1'&x"6AAE",'1'&x"6AAF",
+--'1'&x"6AB0",'1'&x"6AB1",'1'&x"6AB2",'1'&x"6AB3",'1'&x"6AB4",'1'&x"6AB5",'1'&x"6AB6",'1'&x"6AB7",'1'&x"6AB8",'1'&x"6AB9",'1'&x"6ABA",'1'&x"6ABB",'1'&x"6ABC",'1'&x"6ABD",'1'&x"6ABE",'1'&x"6ABF",
+--'1'&x"6AC0",'1'&x"6AC1",'1'&x"6AC2",'1'&x"6AC3",'1'&x"6AC4",'1'&x"6AC5",'1'&x"6AC6",'1'&x"6AC7",'1'&x"6AC8",'1'&x"6AC9",'1'&x"6ACA",'1'&x"6ACB",'1'&x"6ACC",'1'&x"6ACD",'1'&x"6ACE",'1'&x"6ACF",
+--'1'&x"6AD0",'1'&x"6AD1",'1'&x"6AD2",'1'&x"6AD3",'1'&x"6AD4",'1'&x"6AD5",'1'&x"6AD6",'1'&x"6AD7",'1'&x"6AD8",'1'&x"6AD9",'1'&x"6ADA",'1'&x"6ADB",'1'&x"6ADC",'1'&x"6ADD",'1'&x"6ADE",'1'&x"6ADF",
+--'1'&x"6AE0",'1'&x"6AE1",'1'&x"6AE2",'1'&x"6AE3",'1'&x"6AE4",'1'&x"6AE5",'1'&x"6AE6",'1'&x"6AE7",'1'&x"6AE8",'1'&x"6AE9",'1'&x"6AEA",'1'&x"6AEB",'1'&x"6AEC",'1'&x"6AED",'1'&x"6AEE",'1'&x"6AEF",
+--'1'&x"6AF0",'1'&x"6AF1",'1'&x"6AF2",'1'&x"6AF3",'1'&x"6AF4",'1'&x"6AF5",'1'&x"6AF6",'1'&x"6AF7",'1'&x"6AF8",'1'&x"6AF9",'1'&x"6AFA",'1'&x"6AFB",'1'&x"6AFC",'1'&x"6AFD",'1'&x"6AFE",'1'&x"6AFF",
+--'1'&x"6B00",'1'&x"6B01",'1'&x"6B02",'1'&x"6B03",'1'&x"6B04",'1'&x"6B05",'1'&x"6B06",'1'&x"6B07",'1'&x"6B08",'1'&x"6B09",'1'&x"6B0A",'1'&x"6B0B",'1'&x"6B0C",'1'&x"6B0D",'1'&x"6B0E",'1'&x"6B0F",
+--'1'&x"6B10",'1'&x"6B11",'1'&x"6B12",'1'&x"6B13",'1'&x"6B14",'1'&x"6B15",'1'&x"6B16",'1'&x"6B17",'1'&x"6B18",'1'&x"6B19",'1'&x"6B1A",'1'&x"6B1B",'1'&x"6B1C",'1'&x"6B1D",'1'&x"6B1E",'1'&x"6B1F",
+--'1'&x"6B20",'1'&x"6B21",'1'&x"6B22",'1'&x"6B23",'1'&x"6B24",'1'&x"6B25",'1'&x"6B26",'1'&x"6B27",'1'&x"6B28",'1'&x"6B29",'1'&x"6B2A",'1'&x"6B2B",'1'&x"6B2C",'1'&x"6B2D",'1'&x"6B2E",'1'&x"6B2F",
+--'1'&x"6B30",'1'&x"6B31",'1'&x"6B32",'1'&x"6B33",'1'&x"6B34",'1'&x"6B35",'1'&x"6B36",'1'&x"6B37",'1'&x"6B38",'1'&x"6B39",'1'&x"6B3A",'1'&x"6B3B",'1'&x"6B3C",'1'&x"6B3D",'1'&x"6B3E",'1'&x"6B3F",
+--'1'&x"6B40",'1'&x"6B41",'1'&x"6B42",'1'&x"6B43",'1'&x"6B44",'1'&x"6B45",'1'&x"6B46",'1'&x"6B47",'1'&x"6B48",'1'&x"6B49",'1'&x"6B4A",'1'&x"6B4B",'1'&x"6B4C",'1'&x"6B4D",'1'&x"6B4E",'1'&x"6B4F",
+--'1'&x"6B50",'1'&x"6B51",'1'&x"6B52",'1'&x"6B53",'1'&x"6B54",'1'&x"6B55",'1'&x"6B56",'1'&x"6B57",'1'&x"6B58",'1'&x"6B59",'1'&x"6B5A",'1'&x"6B5B",'1'&x"6B5C",'1'&x"6B5D",'1'&x"6B5E",'1'&x"6B5F",
+--'1'&x"6B60",'1'&x"6B61",'1'&x"6B62",'1'&x"6B63",'1'&x"6B64",'1'&x"6B65",'1'&x"6B66",'1'&x"6B67",'1'&x"6B68",'1'&x"6B69",'1'&x"6B6A",'1'&x"6B6B",'1'&x"6B6C",'1'&x"6B6D",'1'&x"6B6E",'1'&x"6B6F",
+--'1'&x"6B70",'1'&x"6B71",'1'&x"6B72",'1'&x"6B73",'1'&x"6B74",'1'&x"6B75",'1'&x"6B76",'1'&x"6B77",'1'&x"6B78",'1'&x"6B79",'1'&x"6B7A",'1'&x"6B7B",'1'&x"6B7C",'1'&x"6B7D",'1'&x"6B7E",'1'&x"6B7F",
+--'1'&x"6B80",'1'&x"6B81",'1'&x"6B82",'1'&x"6B83",'1'&x"6B84",'1'&x"6B85",'1'&x"6B86",'1'&x"6B87",'1'&x"6B88",'1'&x"6B89",'1'&x"6B8A",'1'&x"6B8B",'1'&x"6B8C",'1'&x"6B8D",'1'&x"6B8E",'1'&x"6B8F",
+--'1'&x"6B90",'1'&x"6B91",'1'&x"6B92",'1'&x"6B93",'1'&x"6B94",'1'&x"6B95",'1'&x"6B96",'1'&x"6B97",'1'&x"6B98",'1'&x"6B99",'1'&x"6B9A",'1'&x"6B9B",'1'&x"6B9C",'1'&x"6B9D",'1'&x"6B9E",'1'&x"6B9F",
+--'1'&x"6BA0",'1'&x"6BA1",'1'&x"6BA2",'1'&x"6BA3",'1'&x"6BA4",'1'&x"6BA5",'1'&x"6BA6",'1'&x"6BA7",'1'&x"6BA8",'1'&x"6BA9",'1'&x"6BAA",'1'&x"6BAB",'1'&x"6BAC",'1'&x"6BAD",'1'&x"6BAE",'1'&x"6BAF",
+--'1'&x"6BB0",'1'&x"6BB1",'1'&x"6BB2",'1'&x"6BB3",'1'&x"6BB4",'1'&x"6BB5",'1'&x"6BB6",'1'&x"6BB7",'1'&x"6BB8",'1'&x"6BB9",'1'&x"6BBA",'1'&x"6BBB",'1'&x"6BBC",'1'&x"6BBD",'1'&x"6BBE",'1'&x"6BBF",
+--'1'&x"6BC0",'1'&x"6BC1",'1'&x"6BC2",'1'&x"6BC3",'1'&x"6BC4",'1'&x"6BC5",'1'&x"6BC6",'1'&x"6BC7",'1'&x"6BC8",'1'&x"6BC9",'1'&x"6BCA",'1'&x"6BCB",'1'&x"6BCC",'1'&x"6BCD",'1'&x"6BCE",'1'&x"6BCF",
+--'1'&x"6BD0",'1'&x"6BD1",'1'&x"6BD2",'1'&x"6BD3",'1'&x"6BD4",'1'&x"6BD5",'1'&x"6BD6",'1'&x"6BD7",'1'&x"6BD8",'1'&x"6BD9",'1'&x"6BDA",'1'&x"6BDB",'1'&x"6BDC",'1'&x"6BDD",'1'&x"6BDE",'1'&x"6BDF",
+--'1'&x"6BE0",'1'&x"6BE1",'1'&x"6BE2",'1'&x"6BE3",'1'&x"6BE4",'1'&x"6BE5",'1'&x"6BE6",'1'&x"6BE7",'1'&x"6BE8",'1'&x"6BE9",'1'&x"6BEA",'1'&x"6BEB",'1'&x"6BEC",'1'&x"6BED",'1'&x"6BEE",'1'&x"6BEF",
+--'1'&x"6BF0",'1'&x"6BF1",'1'&x"6BF2",'1'&x"6BF3",'1'&x"6BF4",'1'&x"6BF5",'1'&x"6BF6",'1'&x"6BF7",'1'&x"6BF8",'1'&x"6BF9",'1'&x"6BFA",'1'&x"6BFB",'1'&x"6BFC",'1'&x"6BFD",'1'&x"6BFE",'1'&x"6BFF",
+--'1'&x"6C00",'1'&x"6C01",'1'&x"6C02",'1'&x"6C03",'1'&x"6C04",'1'&x"6C05",'1'&x"6C06",'1'&x"6C07",'1'&x"6C08",'1'&x"6C09",'1'&x"6C0A",'1'&x"6C0B",'1'&x"6C0C",'1'&x"6C0D",'1'&x"6C0E",'1'&x"6C0F",
+--'1'&x"6C10",'1'&x"6C11",'1'&x"6C12",'1'&x"6C13",'1'&x"6C14",'1'&x"6C15",'1'&x"6C16",'1'&x"6C17",'1'&x"6C18",'1'&x"6C19",'1'&x"6C1A",'1'&x"6C1B",'1'&x"6C1C",'1'&x"6C1D",'1'&x"6C1E",'1'&x"6C1F",
+--'1'&x"6C20",'1'&x"6C21",'1'&x"6C22",'1'&x"6C23",'1'&x"6C24",'1'&x"6C25",'1'&x"6C26",'1'&x"6C27",'1'&x"6C28",'1'&x"6C29",'1'&x"6C2A",'1'&x"6C2B",'1'&x"6C2C",'1'&x"6C2D",'1'&x"6C2E",'1'&x"6C2F",
+--'1'&x"6C30",'1'&x"6C31",'1'&x"6C32",'1'&x"6C33",'1'&x"6C34",'1'&x"6C35",'1'&x"6C36",'1'&x"6C37",'1'&x"6C38",'1'&x"6C39",'1'&x"6C3A",'1'&x"6C3B",'1'&x"6C3C",'1'&x"6C3D",'1'&x"6C3E",'1'&x"6C3F",
+--'1'&x"6C40",'1'&x"6C41",'1'&x"6C42",'1'&x"6C43",'1'&x"6C44",'1'&x"6C45",'1'&x"6C46",'1'&x"6C47",'1'&x"6C48",'1'&x"6C49",'1'&x"6C4A",'1'&x"6C4B",'1'&x"6C4C",'1'&x"6C4D",'1'&x"6C4E",'1'&x"6C4F",
+--'1'&x"6C50",'1'&x"6C51",'1'&x"6C52",'1'&x"6C53",'1'&x"6C54",'1'&x"6C55",'1'&x"6C56",'1'&x"6C57",'1'&x"6C58",'1'&x"6C59",'1'&x"6C5A",'1'&x"6C5B",'1'&x"6C5C",'1'&x"6C5D",'1'&x"6C5E",'1'&x"6C5F",
+--'1'&x"6C60",'1'&x"6C61",'1'&x"6C62",'1'&x"6C63",'1'&x"6C64",'1'&x"6C65",'1'&x"6C66",'1'&x"6C67",'1'&x"6C68",'1'&x"6C69",'1'&x"6C6A",'1'&x"6C6B",'1'&x"6C6C",'1'&x"6C6D",'1'&x"6C6E",'1'&x"6C6F",
+--'1'&x"6C70",'1'&x"6C71",'1'&x"6C72",'1'&x"6C73",'1'&x"6C74",'1'&x"6C75",'1'&x"6C76",'1'&x"6C77",'1'&x"6C78",'1'&x"6C79",'1'&x"6C7A",'1'&x"6C7B",'1'&x"6C7C",'1'&x"6C7D",'1'&x"6C7E",'1'&x"6C7F",
+--'1'&x"6C80",'1'&x"6C81",'1'&x"6C82",'1'&x"6C83",'1'&x"6C84",'1'&x"6C85",'1'&x"6C86",'1'&x"6C87",'1'&x"6C88",'1'&x"6C89",'1'&x"6C8A",'1'&x"6C8B",'1'&x"6C8C",'1'&x"6C8D",'1'&x"6C8E",'1'&x"6C8F",
+--'1'&x"6C90",'1'&x"6C91",'1'&x"6C92",'1'&x"6C93",'1'&x"6C94",'1'&x"6C95",'1'&x"6C96",'1'&x"6C97",'1'&x"6C98",'1'&x"6C99",'1'&x"6C9A",'1'&x"6C9B",'1'&x"6C9C",'1'&x"6C9D",'1'&x"6C9E",'1'&x"6C9F",
+--'1'&x"6CA0",'1'&x"6CA1",'1'&x"6CA2",'1'&x"6CA3",'1'&x"6CA4",'1'&x"6CA5",'1'&x"6CA6",'1'&x"6CA7",'1'&x"6CA8",'1'&x"6CA9",'1'&x"6CAA",'1'&x"6CAB",'1'&x"6CAC",'1'&x"6CAD",'1'&x"6CAE",'1'&x"6CAF",
+--'1'&x"6CB0",'1'&x"6CB1",'1'&x"6CB2",'1'&x"6CB3",'1'&x"6CB4",'1'&x"6CB5",'1'&x"6CB6",'1'&x"6CB7",'1'&x"6CB8",'1'&x"6CB9",'1'&x"6CBA",'1'&x"6CBB",'1'&x"6CBC",'1'&x"6CBD",'1'&x"6CBE",'1'&x"6CBF",
+--'1'&x"6CC0",'1'&x"6CC1",'1'&x"6CC2",'1'&x"6CC3",'1'&x"6CC4",'1'&x"6CC5",'1'&x"6CC6",'1'&x"6CC7",'1'&x"6CC8",'1'&x"6CC9",'1'&x"6CCA",'1'&x"6CCB",'1'&x"6CCC",'1'&x"6CCD",'1'&x"6CCE",'1'&x"6CCF",
+--'1'&x"6CD0",'1'&x"6CD1",'1'&x"6CD2",'1'&x"6CD3",'1'&x"6CD4",'1'&x"6CD5",'1'&x"6CD6",'1'&x"6CD7",'1'&x"6CD8",'1'&x"6CD9",'1'&x"6CDA",'1'&x"6CDB",'1'&x"6CDC",'1'&x"6CDD",'1'&x"6CDE",'1'&x"6CDF",
+--'1'&x"6CE0",'1'&x"6CE1",'1'&x"6CE2",'1'&x"6CE3",'1'&x"6CE4",'1'&x"6CE5",'1'&x"6CE6",'1'&x"6CE7",'1'&x"6CE8",'1'&x"6CE9",'1'&x"6CEA",'1'&x"6CEB",'1'&x"6CEC",'1'&x"6CED",'1'&x"6CEE",'1'&x"6CEF",
+--'1'&x"6CF0",'1'&x"6CF1",'1'&x"6CF2",'1'&x"6CF3",'1'&x"6CF4",'1'&x"6CF5",'1'&x"6CF6",'1'&x"6CF7",'1'&x"6CF8",'1'&x"6CF9",'1'&x"6CFA",'1'&x"6CFB",'1'&x"6CFC",'1'&x"6CFD",'1'&x"6CFE",'1'&x"6CFF",
+--'1'&x"6D00",'1'&x"6D01",'1'&x"6D02",'1'&x"6D03",'1'&x"6D04",'1'&x"6D05",'1'&x"6D06",'1'&x"6D07",'1'&x"6D08",'1'&x"6D09",'1'&x"6D0A",'1'&x"6D0B",'1'&x"6D0C",'1'&x"6D0D",'1'&x"6D0E",'1'&x"6D0F",
+--'1'&x"6D10",'1'&x"6D11",'1'&x"6D12",'1'&x"6D13",'1'&x"6D14",'1'&x"6D15",'1'&x"6D16",'1'&x"6D17",'1'&x"6D18",'1'&x"6D19",'1'&x"6D1A",'1'&x"6D1B",'1'&x"6D1C",'1'&x"6D1D",'1'&x"6D1E",'1'&x"6D1F",
+--'1'&x"6D20",'1'&x"6D21",'1'&x"6D22",'1'&x"6D23",'1'&x"6D24",'1'&x"6D25",'1'&x"6D26",'1'&x"6D27",'1'&x"6D28",'1'&x"6D29",'1'&x"6D2A",'1'&x"6D2B",'1'&x"6D2C",'1'&x"6D2D",'1'&x"6D2E",'1'&x"6D2F",
+--'1'&x"6D30",'1'&x"6D31",'1'&x"6D32",'1'&x"6D33",'1'&x"6D34",'1'&x"6D35",'1'&x"6D36",'1'&x"6D37",'1'&x"6D38",'1'&x"6D39",'1'&x"6D3A",'1'&x"6D3B",'1'&x"6D3C",'1'&x"6D3D",'1'&x"6D3E",'1'&x"6D3F",
+--'1'&x"6D40",'1'&x"6D41",'1'&x"6D42",'1'&x"6D43",'1'&x"6D44",'1'&x"6D45",'1'&x"6D46",'1'&x"6D47",'1'&x"6D48",'1'&x"6D49",'1'&x"6D4A",'1'&x"6D4B",'1'&x"6D4C",'1'&x"6D4D",'1'&x"6D4E",'1'&x"6D4F",
+--'1'&x"6D50",'1'&x"6D51",'1'&x"6D52",'1'&x"6D53",'1'&x"6D54",'1'&x"6D55",'1'&x"6D56",'1'&x"6D57",'1'&x"6D58",'1'&x"6D59",'1'&x"6D5A",'1'&x"6D5B",'1'&x"6D5C",'1'&x"6D5D",'1'&x"6D5E",'1'&x"6D5F",
+--'1'&x"6D60",'1'&x"6D61",'1'&x"6D62",'1'&x"6D63",'1'&x"6D64",'1'&x"6D65",'1'&x"6D66",'1'&x"6D67",'1'&x"6D68",'1'&x"6D69",'1'&x"6D6A",'1'&x"6D6B",'1'&x"6D6C",'1'&x"6D6D",'1'&x"6D6E",'1'&x"6D6F",
+--'1'&x"6D70",'1'&x"6D71",'1'&x"6D72",'1'&x"6D73",'1'&x"6D74",'1'&x"6D75",'1'&x"6D76",'1'&x"6D77",'1'&x"6D78",'1'&x"6D79",'1'&x"6D7A",'1'&x"6D7B",'1'&x"6D7C",'1'&x"6D7D",'1'&x"6D7E",'1'&x"6D7F",
+--'1'&x"6D80",'1'&x"6D81",'1'&x"6D82",'1'&x"6D83",'1'&x"6D84",'1'&x"6D85",'1'&x"6D86",'1'&x"6D87",'1'&x"6D88",'1'&x"6D89",'1'&x"6D8A",'1'&x"6D8B",'1'&x"6D8C",'1'&x"6D8D",'1'&x"6D8E",'1'&x"6D8F",
+--'1'&x"6D90",'1'&x"6D91",'1'&x"6D92",'1'&x"6D93",'1'&x"6D94",'1'&x"6D95",'1'&x"6D96",'1'&x"6D97",'1'&x"6D98",'1'&x"6D99",'1'&x"6D9A",'1'&x"6D9B",'1'&x"6D9C",'1'&x"6D9D",'1'&x"6D9E",'1'&x"6D9F",
+--'1'&x"6DA0",'1'&x"6DA1",'1'&x"6DA2",'1'&x"6DA3",'1'&x"6DA4",'1'&x"6DA5",'1'&x"6DA6",'1'&x"6DA7",'1'&x"6DA8",'1'&x"6DA9",'1'&x"6DAA",'1'&x"6DAB",'1'&x"6DAC",'1'&x"6DAD",'1'&x"6DAE",'1'&x"6DAF",
+--'1'&x"6DB0",'1'&x"6DB1",'1'&x"6DB2",'1'&x"6DB3",'1'&x"6DB4",'1'&x"6DB5",'1'&x"6DB6",'1'&x"6DB7",'1'&x"6DB8",'1'&x"6DB9",'1'&x"6DBA",'1'&x"6DBB",'1'&x"6DBC",'1'&x"6DBD",'1'&x"6DBE",'1'&x"6DBF",
+--'1'&x"6DC0",'1'&x"6DC1",'1'&x"6DC2",'1'&x"6DC3",'1'&x"6DC4",'1'&x"6DC5",'1'&x"6DC6",'1'&x"6DC7",'1'&x"6DC8",'1'&x"6DC9",'1'&x"6DCA",'1'&x"6DCB",'1'&x"6DCC",'1'&x"6DCD",'1'&x"6DCE",'1'&x"6DCF",
+--'1'&x"6DD0",'1'&x"6DD1",'1'&x"6DD2",'1'&x"6DD3",'1'&x"6DD4",'1'&x"6DD5",'1'&x"6DD6",'1'&x"6DD7",'1'&x"6DD8",'1'&x"6DD9",'1'&x"6DDA",'1'&x"6DDB",'1'&x"6DDC",'1'&x"6DDD",'1'&x"6DDE",'1'&x"6DDF",
+--'1'&x"6DE0",'1'&x"6DE1",'1'&x"6DE2",'1'&x"6DE3",'1'&x"6DE4",'1'&x"6DE5",'1'&x"6DE6",'1'&x"6DE7",'1'&x"6DE8",'1'&x"6DE9",'1'&x"6DEA",'1'&x"6DEB",'1'&x"6DEC",'1'&x"6DED",'1'&x"6DEE",'1'&x"6DEF",
+--'1'&x"6DF0",'1'&x"6DF1",'1'&x"6DF2",'1'&x"6DF3",'1'&x"6DF4",'1'&x"6DF5",'1'&x"6DF6",'1'&x"6DF7",'1'&x"6DF8",'1'&x"6DF9",'1'&x"6DFA",'1'&x"6DFB",'1'&x"6DFC",'1'&x"6DFD",'1'&x"6DFE",'1'&x"6DFF",
+--'1'&x"6E00",'1'&x"6E01",'1'&x"6E02",'1'&x"6E03",'1'&x"6E04",'1'&x"6E05",'1'&x"6E06",'1'&x"6E07",'1'&x"6E08",'1'&x"6E09",'1'&x"6E0A",'1'&x"6E0B",'1'&x"6E0C",'1'&x"6E0D",'1'&x"6E0E",'1'&x"6E0F",
+--'1'&x"6E10",'1'&x"6E11",'1'&x"6E12",'1'&x"6E13",'1'&x"6E14",'1'&x"6E15",'1'&x"6E16",'1'&x"6E17",'1'&x"6E18",'1'&x"6E19",'1'&x"6E1A",'1'&x"6E1B",'1'&x"6E1C",'1'&x"6E1D",'1'&x"6E1E",'1'&x"6E1F",
+--'1'&x"6E20",'1'&x"6E21",'1'&x"6E22",'1'&x"6E23",'1'&x"6E24",'1'&x"6E25",'1'&x"6E26",'1'&x"6E27",'1'&x"6E28",'1'&x"6E29",'1'&x"6E2A",'1'&x"6E2B",'1'&x"6E2C",'1'&x"6E2D",'1'&x"6E2E",'1'&x"6E2F",
+--'1'&x"6E30",'1'&x"6E31",'1'&x"6E32",'1'&x"6E33",'1'&x"6E34",'1'&x"6E35",'1'&x"6E36",'1'&x"6E37",'1'&x"6E38",'1'&x"6E39",'1'&x"6E3A",'1'&x"6E3B",'1'&x"6E3C",'1'&x"6E3D",'1'&x"6E3E",'1'&x"6E3F",
+--'1'&x"6E40",'1'&x"6E41",'1'&x"6E42",'1'&x"6E43",'1'&x"6E44",'1'&x"6E45",'1'&x"6E46",'1'&x"6E47",'1'&x"6E48",'1'&x"6E49",'1'&x"6E4A",'1'&x"6E4B",'1'&x"6E4C",'1'&x"6E4D",'1'&x"6E4E",'1'&x"6E4F",
+--'1'&x"6E50",'1'&x"6E51",'1'&x"6E52",'1'&x"6E53",'1'&x"6E54",'1'&x"6E55",'1'&x"6E56",'1'&x"6E57",'1'&x"6E58",'1'&x"6E59",'1'&x"6E5A",'1'&x"6E5B",'1'&x"6E5C",'1'&x"6E5D",'1'&x"6E5E",'1'&x"6E5F",
+--'1'&x"6E60",'1'&x"6E61",'1'&x"6E62",'1'&x"6E63",'1'&x"6E64",'1'&x"6E65",'1'&x"6E66",'1'&x"6E67",'1'&x"6E68",'1'&x"6E69",'1'&x"6E6A",'1'&x"6E6B",'1'&x"6E6C",'1'&x"6E6D",'1'&x"6E6E",'1'&x"6E6F",
+--'1'&x"6E70",'1'&x"6E71",'1'&x"6E72",'1'&x"6E73",'1'&x"6E74",'1'&x"6E75",'1'&x"6E76",'1'&x"6E77",'1'&x"6E78",'1'&x"6E79",'1'&x"6E7A",'1'&x"6E7B",'1'&x"6E7C",'1'&x"6E7D",'1'&x"6E7E",'1'&x"6E7F",
+--'1'&x"6E80",'1'&x"6E81",'1'&x"6E82",'1'&x"6E83",'1'&x"6E84",'1'&x"6E85",'1'&x"6E86",'1'&x"6E87",'1'&x"6E88",'1'&x"6E89",'1'&x"6E8A",'1'&x"6E8B",'1'&x"6E8C",'1'&x"6E8D",'1'&x"6E8E",'1'&x"6E8F",
+--'1'&x"6E90",'1'&x"6E91",'1'&x"6E92",'1'&x"6E93",'1'&x"6E94",'1'&x"6E95",'1'&x"6E96",'1'&x"6E97",'1'&x"6E98",'1'&x"6E99",'1'&x"6E9A",'1'&x"6E9B",'1'&x"6E9C",'1'&x"6E9D",'1'&x"6E9E",'1'&x"6E9F",
+--'1'&x"6EA0",'1'&x"6EA1",'1'&x"6EA2",'1'&x"6EA3",'1'&x"6EA4",'1'&x"6EA5",'1'&x"6EA6",'1'&x"6EA7",'1'&x"6EA8",'1'&x"6EA9",'1'&x"6EAA",'1'&x"6EAB",'1'&x"6EAC",'1'&x"6EAD",'1'&x"6EAE",'1'&x"6EAF",
+--'1'&x"6EB0",'1'&x"6EB1",'1'&x"6EB2",'1'&x"6EB3",'1'&x"6EB4",'1'&x"6EB5",'1'&x"6EB6",'1'&x"6EB7",'1'&x"6EB8",'1'&x"6EB9",'1'&x"6EBA",'1'&x"6EBB",'1'&x"6EBC",'1'&x"6EBD",'1'&x"6EBE",'1'&x"6EBF",
+--'1'&x"6EC0",'1'&x"6EC1",'1'&x"6EC2",'1'&x"6EC3",'1'&x"6EC4",'1'&x"6EC5",'1'&x"6EC6",'1'&x"6EC7",'1'&x"6EC8",'1'&x"6EC9",'1'&x"6ECA",'1'&x"6ECB",'1'&x"6ECC",'1'&x"6ECD",'1'&x"6ECE",'1'&x"6ECF",
+--'1'&x"6ED0",'1'&x"6ED1",'1'&x"6ED2",'1'&x"6ED3",'1'&x"6ED4",'1'&x"6ED5",'1'&x"6ED6",'1'&x"6ED7",'1'&x"6ED8",'1'&x"6ED9",'1'&x"6EDA",'1'&x"6EDB",'1'&x"6EDC",'1'&x"6EDD",'1'&x"6EDE",'1'&x"6EDF",
+--'1'&x"6EE0",'1'&x"6EE1",'1'&x"6EE2",'1'&x"6EE3",'1'&x"6EE4",'1'&x"6EE5",'1'&x"6EE6",'1'&x"6EE7",'1'&x"6EE8",'1'&x"6EE9",'1'&x"6EEA",'1'&x"6EEB",'1'&x"6EEC",'1'&x"6EED",'1'&x"6EEE",'1'&x"6EEF",
+--'1'&x"6EF0",'1'&x"6EF1",'1'&x"6EF2",'1'&x"6EF3",'1'&x"6EF4",'1'&x"6EF5",'1'&x"6EF6",'1'&x"6EF7",'1'&x"6EF8",'1'&x"6EF9",'1'&x"6EFA",'1'&x"6EFB",'1'&x"6EFC",'1'&x"6EFD",'1'&x"6EFE",'1'&x"6EFF",
+--'1'&x"6F00",'1'&x"6F01",'1'&x"6F02",'1'&x"6F03",'1'&x"6F04",'1'&x"6F05",'1'&x"6F06",'1'&x"6F07",'1'&x"6F08",'1'&x"6F09",'1'&x"6F0A",'1'&x"6F0B",'1'&x"6F0C",'1'&x"6F0D",'1'&x"6F0E",'1'&x"6F0F",
+--'1'&x"6F10",'1'&x"6F11",'1'&x"6F12",'1'&x"6F13",'1'&x"6F14",'1'&x"6F15",'1'&x"6F16",'1'&x"6F17",'1'&x"6F18",'1'&x"6F19",'1'&x"6F1A",'1'&x"6F1B",'1'&x"6F1C",'1'&x"6F1D",'1'&x"6F1E",'1'&x"6F1F",
+--'1'&x"6F20",'1'&x"6F21",'1'&x"6F22",'1'&x"6F23",'1'&x"6F24",'1'&x"6F25",'1'&x"6F26",'1'&x"6F27",'1'&x"6F28",'1'&x"6F29",'1'&x"6F2A",'1'&x"6F2B",'1'&x"6F2C",'1'&x"6F2D",'1'&x"6F2E",'1'&x"6F2F",
+--'1'&x"6F30",'1'&x"6F31",'1'&x"6F32",'1'&x"6F33",'1'&x"6F34",'1'&x"6F35",'1'&x"6F36",'1'&x"6F37",'1'&x"6F38",'1'&x"6F39",'1'&x"6F3A",'1'&x"6F3B",'1'&x"6F3C",'1'&x"6F3D",'1'&x"6F3E",'1'&x"6F3F",
+--'1'&x"6F40",'1'&x"6F41",'1'&x"6F42",'1'&x"6F43",'1'&x"6F44",'1'&x"6F45",'1'&x"6F46",'1'&x"6F47",'1'&x"6F48",'1'&x"6F49",'1'&x"6F4A",'1'&x"6F4B",'1'&x"6F4C",'1'&x"6F4D",'1'&x"6F4E",'1'&x"6F4F",
+--'1'&x"6F50",'1'&x"6F51",'1'&x"6F52",'1'&x"6F53",'1'&x"6F54",'1'&x"6F55",'1'&x"6F56",'1'&x"6F57",'1'&x"6F58",'1'&x"6F59",'1'&x"6F5A",'1'&x"6F5B",'1'&x"6F5C",'1'&x"6F5D",'1'&x"6F5E",'1'&x"6F5F",
+--'1'&x"6F60",'1'&x"6F61",'1'&x"6F62",'1'&x"6F63",'1'&x"6F64",'1'&x"6F65",'1'&x"6F66",'1'&x"6F67",'1'&x"6F68",'1'&x"6F69",'1'&x"6F6A",'1'&x"6F6B",'1'&x"6F6C",'1'&x"6F6D",'1'&x"6F6E",'1'&x"6F6F",
+--'1'&x"6F70",'1'&x"6F71",'1'&x"6F72",'1'&x"6F73",'1'&x"6F74",'1'&x"6F75",'1'&x"6F76",'1'&x"6F77",'1'&x"6F78",'1'&x"6F79",'1'&x"6F7A",'1'&x"6F7B",'1'&x"6F7C",'1'&x"6F7D",'1'&x"6F7E",'1'&x"6F7F",
+--'1'&x"6F80",'1'&x"6F81",'1'&x"6F82",'1'&x"6F83",'1'&x"6F84",'1'&x"6F85",'1'&x"6F86",'1'&x"6F87",'1'&x"6F88",'1'&x"6F89",'1'&x"6F8A",'1'&x"6F8B",'1'&x"6F8C",'1'&x"6F8D",'1'&x"6F8E",'1'&x"6F8F",
+--'1'&x"6F90",'1'&x"6F91",'1'&x"6F92",'1'&x"6F93",'1'&x"6F94",'1'&x"6F95",'1'&x"6F96",'1'&x"6F97",'1'&x"6F98",'1'&x"6F99",'1'&x"6F9A",'1'&x"6F9B",'1'&x"6F9C",'1'&x"6F9D",'1'&x"6F9E",'1'&x"6F9F",
+--'1'&x"6FA0",'1'&x"6FA1",'1'&x"6FA2",'1'&x"6FA3",'1'&x"6FA4",'1'&x"6FA5",'1'&x"6FA6",'1'&x"6FA7",'1'&x"6FA8",'1'&x"6FA9",'1'&x"6FAA",'1'&x"6FAB",'1'&x"6FAC",'1'&x"6FAD",'1'&x"6FAE",'1'&x"6FAF",
+--'1'&x"6FB0",'1'&x"6FB1",'1'&x"6FB2",'1'&x"6FB3",'1'&x"6FB4",'1'&x"6FB5",'1'&x"6FB6",'1'&x"6FB7",'1'&x"6FB8",'1'&x"6FB9",'1'&x"6FBA",'1'&x"6FBB",'1'&x"6FBC",'1'&x"6FBD",'1'&x"6FBE",'1'&x"6FBF",
+--'1'&x"6FC0",'1'&x"6FC1",'1'&x"6FC2",'1'&x"6FC3",'1'&x"6FC4",'1'&x"6FC5",'1'&x"6FC6",'1'&x"6FC7",'1'&x"6FC8",'1'&x"6FC9",'1'&x"6FCA",'1'&x"6FCB",'1'&x"6FCC",'1'&x"6FCD",'1'&x"6FCE",'1'&x"6FCF",
+--'1'&x"6FD0",'1'&x"6FD1",'1'&x"6FD2",'1'&x"6FD3",'1'&x"6FD4",'1'&x"6FD5",'1'&x"6FD6",'1'&x"6FD7",'1'&x"6FD8",'1'&x"6FD9",'1'&x"6FDA",'1'&x"6FDB",'1'&x"6FDC",'1'&x"6FDD",'1'&x"6FDE",'1'&x"6FDF",
+--'1'&x"6FE0",'1'&x"6FE1",'1'&x"6FE2",'1'&x"6FE3",'1'&x"6FE4",'1'&x"6FE5",'1'&x"6FE6",'1'&x"6FE7",'1'&x"6FE8",'1'&x"6FE9",'1'&x"6FEA",'1'&x"6FEB",'1'&x"6FEC",'1'&x"6FED",'1'&x"6FEE",'1'&x"6FEF",
+--'1'&x"6FF0",'1'&x"6FF1",'1'&x"6FF2",'1'&x"6FF3",'1'&x"6FF4",'1'&x"6FF5",'1'&x"6FF6",'1'&x"6FF7",'1'&x"6FF8",'1'&x"6FF9",'1'&x"6FFA",'1'&x"6FFB",'1'&x"6FFC",'1'&x"6FFD",'1'&x"6FFE",'1'&x"6FFF",
+--'1'&x"7000",'1'&x"7001",'1'&x"7002",'1'&x"7003",'1'&x"7004",'1'&x"7005",'1'&x"7006",'1'&x"7007",'1'&x"7008",'1'&x"7009",'1'&x"700A",'1'&x"700B",'1'&x"700C",'1'&x"700D",'1'&x"700E",'1'&x"700F",
+--'1'&x"7010",'1'&x"7011",'1'&x"7012",'1'&x"7013",'1'&x"7014",'1'&x"7015",'1'&x"7016",'1'&x"7017",'1'&x"7018",'1'&x"7019",'1'&x"701A",'1'&x"701B",'1'&x"701C",'1'&x"701D",'1'&x"701E",'1'&x"701F",
+--'1'&x"7020",'1'&x"7021",'1'&x"7022",'1'&x"7023",'1'&x"7024",'1'&x"7025",'1'&x"7026",'1'&x"7027",'1'&x"7028",'1'&x"7029",'1'&x"702A",'1'&x"702B",'1'&x"702C",'1'&x"702D",'1'&x"702E",'1'&x"702F",
+--'1'&x"7030",'1'&x"7031",'1'&x"7032",'1'&x"7033",'1'&x"7034",'1'&x"7035",'1'&x"7036",'1'&x"7037",'1'&x"7038",'1'&x"7039",'1'&x"703A",'1'&x"703B",'1'&x"703C",'1'&x"703D",'1'&x"703E",'1'&x"703F",
+--'1'&x"7040",'1'&x"7041",'1'&x"7042",'1'&x"7043",'1'&x"7044",'1'&x"7045",'1'&x"7046",'1'&x"7047",'1'&x"7048",'1'&x"7049",'1'&x"704A",'1'&x"704B",'1'&x"704C",'1'&x"704D",'1'&x"704E",'1'&x"704F",
+--'1'&x"7050",'1'&x"7051",'1'&x"7052",'1'&x"7053",'1'&x"7054",'1'&x"7055",'1'&x"7056",'1'&x"7057",'1'&x"7058",'1'&x"7059",'1'&x"705A",'1'&x"705B",'1'&x"705C",'1'&x"705D",'1'&x"705E",'1'&x"705F",
+--'1'&x"7060",'1'&x"7061",'1'&x"7062",'1'&x"7063",'1'&x"7064",'1'&x"7065",'1'&x"7066",'1'&x"7067",'1'&x"7068",'1'&x"7069",'1'&x"706A",'1'&x"706B",'1'&x"706C",'1'&x"706D",'1'&x"706E",'1'&x"706F",
+--'1'&x"7070",'1'&x"7071",'1'&x"7072",'1'&x"7073",'1'&x"7074",'1'&x"7075",'1'&x"7076",'1'&x"7077",'1'&x"7078",'1'&x"7079",'1'&x"707A",'1'&x"707B",'1'&x"707C",'1'&x"707D",'1'&x"707E",'1'&x"707F",
+--'1'&x"7080",'1'&x"7081",'1'&x"7082",'1'&x"7083",'1'&x"7084",'1'&x"7085",'1'&x"7086",'1'&x"7087",'1'&x"7088",'1'&x"7089",'1'&x"708A",'1'&x"708B",'1'&x"708C",'1'&x"708D",'1'&x"708E",'1'&x"708F",
+--'1'&x"7090",'1'&x"7091",'1'&x"7092",'1'&x"7093",'1'&x"7094",'1'&x"7095",'1'&x"7096",'1'&x"7097",'1'&x"7098",'1'&x"7099",'1'&x"709A",'1'&x"709B",'1'&x"709C",'1'&x"709D",'1'&x"709E",'1'&x"709F",
+--'1'&x"70A0",'1'&x"70A1",'1'&x"70A2",'1'&x"70A3",'1'&x"70A4",'1'&x"70A5",'1'&x"70A6",'1'&x"70A7",'1'&x"70A8",'1'&x"70A9",'1'&x"70AA",'1'&x"70AB",'1'&x"70AC",'1'&x"70AD",'1'&x"70AE",'1'&x"70AF",
+--'1'&x"70B0",'1'&x"70B1",'1'&x"70B2",'1'&x"70B3",'1'&x"70B4",'1'&x"70B5",'1'&x"70B6",'1'&x"70B7",'1'&x"70B8",'1'&x"70B9",'1'&x"70BA",'1'&x"70BB",'1'&x"70BC",'1'&x"70BD",'1'&x"70BE",'1'&x"70BF",
+--'1'&x"70C0",'1'&x"70C1",'1'&x"70C2",'1'&x"70C3",'1'&x"70C4",'1'&x"70C5",'1'&x"70C6",'1'&x"70C7",'1'&x"70C8",'1'&x"70C9",'1'&x"70CA",'1'&x"70CB",'1'&x"70CC",'1'&x"70CD",'1'&x"70CE",'1'&x"70CF",
+--'1'&x"70D0",'1'&x"70D1",'1'&x"70D2",'1'&x"70D3",'1'&x"70D4",'1'&x"70D5",'1'&x"70D6",'1'&x"70D7",'1'&x"70D8",'1'&x"70D9",'1'&x"70DA",'1'&x"70DB",'1'&x"70DC",'1'&x"70DD",'1'&x"70DE",'1'&x"70DF",
+--'1'&x"70E0",'1'&x"70E1",'1'&x"70E2",'1'&x"70E3",'1'&x"70E4",'1'&x"70E5",'1'&x"70E6",'1'&x"70E7",'1'&x"70E8",'1'&x"70E9",'1'&x"70EA",'1'&x"70EB",'1'&x"70EC",'1'&x"70ED",'1'&x"70EE",'1'&x"70EF",
+--'1'&x"70F0",'1'&x"70F1",'1'&x"70F2",'1'&x"70F3",'1'&x"70F4",'1'&x"70F5",'1'&x"70F6",'1'&x"70F7",'1'&x"70F8",'1'&x"70F9",'1'&x"70FA",'1'&x"70FB",'1'&x"70FC",'1'&x"70FD",'1'&x"70FE",'1'&x"70FF",
+--'1'&x"7100",'1'&x"7101",'1'&x"7102",'1'&x"7103",'1'&x"7104",'1'&x"7105",'1'&x"7106",'1'&x"7107",'1'&x"7108",'1'&x"7109",'1'&x"710A",'1'&x"710B",'1'&x"710C",'1'&x"710D",'1'&x"710E",'1'&x"710F",
+--'1'&x"7110",'1'&x"7111",'1'&x"7112",'1'&x"7113",'1'&x"7114",'1'&x"7115",'1'&x"7116",'1'&x"7117",'1'&x"7118",'1'&x"7119",'1'&x"711A",'1'&x"711B",'1'&x"711C",'1'&x"711D",'1'&x"711E",'1'&x"711F",
+--'1'&x"7120",'1'&x"7121",'1'&x"7122",'1'&x"7123",'1'&x"7124",'1'&x"7125",'1'&x"7126",'1'&x"7127",'1'&x"7128",'1'&x"7129",'1'&x"712A",'1'&x"712B",'1'&x"712C",'1'&x"712D",'1'&x"712E",'1'&x"712F",
+--'1'&x"7130",'1'&x"7131",'1'&x"7132",'1'&x"7133",'1'&x"7134",'1'&x"7135",'1'&x"7136",'1'&x"7137",'1'&x"7138",'1'&x"7139",'1'&x"713A",'1'&x"713B",'1'&x"713C",'1'&x"713D",'1'&x"713E",'1'&x"713F",
+--'1'&x"7140",'1'&x"7141",'1'&x"7142",'1'&x"7143",'1'&x"7144",'1'&x"7145",'1'&x"7146",'1'&x"7147",'1'&x"7148",'1'&x"7149",'1'&x"714A",'1'&x"714B",'1'&x"714C",'1'&x"714D",'1'&x"714E",'1'&x"714F",
+--'1'&x"7150",'1'&x"7151",'1'&x"7152",'1'&x"7153",'1'&x"7154",'1'&x"7155",'1'&x"7156",'1'&x"7157",'1'&x"7158",'1'&x"7159",'1'&x"715A",'1'&x"715B",'1'&x"715C",'1'&x"715D",'1'&x"715E",'1'&x"715F",
+--'1'&x"7160",'1'&x"7161",'1'&x"7162",'1'&x"7163",'1'&x"7164",'1'&x"7165",'1'&x"7166",'1'&x"7167",'1'&x"7168",'1'&x"7169",'1'&x"716A",'1'&x"716B",'1'&x"716C",'1'&x"716D",'1'&x"716E",'1'&x"716F",
+--'1'&x"7170",'1'&x"7171",'1'&x"7172",'1'&x"7173",'1'&x"7174",'1'&x"7175",'1'&x"7176",'1'&x"7177",'1'&x"7178",'1'&x"7179",'1'&x"717A",'1'&x"717B",'1'&x"717C",'1'&x"717D",'1'&x"717E",'1'&x"717F",
+--'1'&x"7180",'1'&x"7181",'1'&x"7182",'1'&x"7183",'1'&x"7184",'1'&x"7185",'1'&x"7186",'1'&x"7187",'1'&x"7188",'1'&x"7189",'1'&x"718A",'1'&x"718B",'1'&x"718C",'1'&x"718D",'1'&x"718E",'1'&x"718F",
+--'1'&x"7190",'1'&x"7191",'1'&x"7192",'1'&x"7193",'1'&x"7194",'1'&x"7195",'1'&x"7196",'1'&x"7197",'1'&x"7198",'1'&x"7199",'1'&x"719A",'1'&x"719B",'1'&x"719C",'1'&x"719D",'1'&x"719E",'1'&x"719F",
+--'1'&x"71A0",'1'&x"71A1",'1'&x"71A2",'1'&x"71A3",'1'&x"71A4",'1'&x"71A5",'1'&x"71A6",'1'&x"71A7",'1'&x"71A8",'1'&x"71A9",'1'&x"71AA",'1'&x"71AB",'1'&x"71AC",'1'&x"71AD",'1'&x"71AE",'1'&x"71AF",
+--'1'&x"71B0",'1'&x"71B1",'1'&x"71B2",'1'&x"71B3",'1'&x"71B4",'1'&x"71B5",'1'&x"71B6",'1'&x"71B7",'1'&x"71B8",'1'&x"71B9",'1'&x"71BA",'1'&x"71BB",'1'&x"71BC",'1'&x"71BD",'1'&x"71BE",'1'&x"71BF",
+--'1'&x"71C0",'1'&x"71C1",'1'&x"71C2",'1'&x"71C3",'1'&x"71C4",'1'&x"71C5",'1'&x"71C6",'1'&x"71C7",'1'&x"71C8",'1'&x"71C9",'1'&x"71CA",'1'&x"71CB",'1'&x"71CC",'1'&x"71CD",'1'&x"71CE",'1'&x"71CF",
+--'1'&x"71D0",'1'&x"71D1",'1'&x"71D2",'1'&x"71D3",'1'&x"71D4",'1'&x"71D5",'1'&x"71D6",'1'&x"71D7",'1'&x"71D8",'1'&x"71D9",'1'&x"71DA",'1'&x"71DB",'1'&x"71DC",'1'&x"71DD",'1'&x"71DE",'1'&x"71DF",
+--'1'&x"71E0",'1'&x"71E1",'1'&x"71E2",'1'&x"71E3",'1'&x"71E4",'1'&x"71E5",'1'&x"71E6",'1'&x"71E7",'1'&x"71E8",'1'&x"71E9",'1'&x"71EA",'1'&x"71EB",'1'&x"71EC",'1'&x"71ED",'1'&x"71EE",'1'&x"71EF",
+--'1'&x"71F0",'1'&x"71F1",'1'&x"71F2",'1'&x"71F3",'1'&x"71F4",'1'&x"71F5",'1'&x"71F6",'1'&x"71F7",'1'&x"71F8",'1'&x"71F9",'1'&x"71FA",'1'&x"71FB",'1'&x"71FC",'1'&x"71FD",'1'&x"71FE",'1'&x"71FF",
+--'1'&x"7200",'1'&x"7201",'1'&x"7202",'1'&x"7203",'1'&x"7204",'1'&x"7205",'1'&x"7206",'1'&x"7207",'1'&x"7208",'1'&x"7209",'1'&x"720A",'1'&x"720B",'1'&x"720C",'1'&x"720D",'1'&x"720E",'1'&x"720F",
+--'1'&x"7210",'1'&x"7211",'1'&x"7212",'1'&x"7213",'1'&x"7214",'1'&x"7215",'1'&x"7216",'1'&x"7217",'1'&x"7218",'1'&x"7219",'1'&x"721A",'1'&x"721B",'1'&x"721C",'1'&x"721D",'1'&x"721E",'1'&x"721F",
+--'1'&x"7220",'1'&x"7221",'1'&x"7222",'1'&x"7223",'1'&x"7224",'1'&x"7225",'1'&x"7226",'1'&x"7227",'1'&x"7228",'1'&x"7229",'1'&x"722A",'1'&x"722B",'1'&x"722C",'1'&x"722D",'1'&x"722E",'1'&x"722F",
+--'1'&x"7230",'1'&x"7231",'1'&x"7232",'1'&x"7233",'1'&x"7234",'1'&x"7235",'1'&x"7236",'1'&x"7237",'1'&x"7238",'1'&x"7239",'1'&x"723A",'1'&x"723B",'1'&x"723C",'1'&x"723D",'1'&x"723E",'1'&x"723F",
+--'1'&x"7240",'1'&x"7241",'1'&x"7242",'1'&x"7243",'1'&x"7244",'1'&x"7245",'1'&x"7246",'1'&x"7247",'1'&x"7248",'1'&x"7249",'1'&x"724A",'1'&x"724B",'1'&x"724C",'1'&x"724D",'1'&x"724E",'1'&x"724F",
+--'1'&x"7250",'1'&x"7251",'1'&x"7252",'1'&x"7253",'1'&x"7254",'1'&x"7255",'1'&x"7256",'1'&x"7257",'1'&x"7258",'1'&x"7259",'1'&x"725A",'1'&x"725B",'1'&x"725C",'1'&x"725D",'1'&x"725E",'1'&x"725F",
+--'1'&x"7260",'1'&x"7261",'1'&x"7262",'1'&x"7263",'1'&x"7264",'1'&x"7265",'1'&x"7266",'1'&x"7267",'1'&x"7268",'1'&x"7269",'1'&x"726A",'1'&x"726B",'1'&x"726C",'1'&x"726D",'1'&x"726E",'1'&x"726F",
+--'1'&x"7270",'1'&x"7271",'1'&x"7272",'1'&x"7273",'1'&x"7274",'1'&x"7275",'1'&x"7276",'1'&x"7277",'1'&x"7278",'1'&x"7279",'1'&x"727A",'1'&x"727B",'1'&x"727C",'1'&x"727D",'1'&x"727E",'1'&x"727F",
+--'1'&x"7280",'1'&x"7281",'1'&x"7282",'1'&x"7283",'1'&x"7284",'1'&x"7285",'1'&x"7286",'1'&x"7287",'1'&x"7288",'1'&x"7289",'1'&x"728A",'1'&x"728B",'1'&x"728C",'1'&x"728D",'1'&x"728E",'1'&x"728F",
+--'1'&x"7290",'1'&x"7291",'1'&x"7292",'1'&x"7293",'1'&x"7294",'1'&x"7295",'1'&x"7296",'1'&x"7297",'1'&x"7298",'1'&x"7299",'1'&x"729A",'1'&x"729B",'1'&x"729C",'1'&x"729D",'1'&x"729E",'1'&x"729F",
+--'1'&x"72A0",'1'&x"72A1",'1'&x"72A2",'1'&x"72A3",'1'&x"72A4",'1'&x"72A5",'1'&x"72A6",'1'&x"72A7",'1'&x"72A8",'1'&x"72A9",'1'&x"72AA",'1'&x"72AB",'1'&x"72AC",'1'&x"72AD",'1'&x"72AE",'1'&x"72AF",
+--'1'&x"72B0",'1'&x"72B1",'1'&x"72B2",'1'&x"72B3",'1'&x"72B4",'1'&x"72B5",'1'&x"72B6",'1'&x"72B7",'1'&x"72B8",'1'&x"72B9",'1'&x"72BA",'1'&x"72BB",'1'&x"72BC",'1'&x"72BD",'1'&x"72BE",'1'&x"72BF",
+--'1'&x"72C0",'1'&x"72C1",'1'&x"72C2",'1'&x"72C3",'1'&x"72C4",'1'&x"72C5",'1'&x"72C6",'1'&x"72C7",'1'&x"72C8",'1'&x"72C9",'1'&x"72CA",'1'&x"72CB",'1'&x"72CC",'1'&x"72CD",'1'&x"72CE",'1'&x"72CF",
+--'1'&x"72D0",'1'&x"72D1",'1'&x"72D2",'1'&x"72D3",'1'&x"72D4",'1'&x"72D5",'1'&x"72D6",'1'&x"72D7",'1'&x"72D8",'1'&x"72D9",'1'&x"72DA",'1'&x"72DB",'1'&x"72DC",'1'&x"72DD",'1'&x"72DE",'1'&x"72DF",
+--'1'&x"72E0",'1'&x"72E1",'1'&x"72E2",'1'&x"72E3",'1'&x"72E4",'1'&x"72E5",'1'&x"72E6",'1'&x"72E7",'1'&x"72E8",'1'&x"72E9",'1'&x"72EA",'1'&x"72EB",'1'&x"72EC",'1'&x"72ED",'1'&x"72EE",'1'&x"72EF",
+--'1'&x"72F0",'1'&x"72F1",'1'&x"72F2",'1'&x"72F3",'1'&x"72F4",'1'&x"72F5",'1'&x"72F6",'1'&x"72F7",'1'&x"72F8",'1'&x"72F9",'1'&x"72FA",'1'&x"72FB",'1'&x"72FC",'1'&x"72FD",'1'&x"72FE",'1'&x"72FF",
+--'1'&x"7300",'1'&x"7301",'1'&x"7302",'1'&x"7303",'1'&x"7304",'1'&x"7305",'1'&x"7306",'1'&x"7307",'1'&x"7308",'1'&x"7309",'1'&x"730A",'1'&x"730B",'1'&x"730C",'1'&x"730D",'1'&x"730E",'1'&x"730F",
+--'1'&x"7310",'1'&x"7311",'1'&x"7312",'1'&x"7313",'1'&x"7314",'1'&x"7315",'1'&x"7316",'1'&x"7317",'1'&x"7318",'1'&x"7319",'1'&x"731A",'1'&x"731B",'1'&x"731C",'1'&x"731D",'1'&x"731E",'1'&x"731F",
+--'1'&x"7320",'1'&x"7321",'1'&x"7322",'1'&x"7323",'1'&x"7324",'1'&x"7325",'1'&x"7326",'1'&x"7327",'1'&x"7328",'1'&x"7329",'1'&x"732A",'1'&x"732B",'1'&x"732C",'1'&x"732D",'1'&x"732E",'1'&x"732F",
+--'1'&x"7330",'1'&x"7331",'1'&x"7332",'1'&x"7333",'1'&x"7334",'1'&x"7335",'1'&x"7336",'1'&x"7337",'1'&x"7338",'1'&x"7339",'1'&x"733A",'1'&x"733B",'1'&x"733C",'1'&x"733D",'1'&x"733E",'1'&x"733F",
+--'1'&x"7340",'1'&x"7341",'1'&x"7342",'1'&x"7343",'1'&x"7344",'1'&x"7345",'1'&x"7346",'1'&x"7347",'1'&x"7348",'1'&x"7349",'1'&x"734A",'1'&x"734B",'1'&x"734C",'1'&x"734D",'1'&x"734E",'1'&x"734F",
+--'1'&x"7350",'1'&x"7351",'1'&x"7352",'1'&x"7353",'1'&x"7354",'1'&x"7355",'1'&x"7356",'1'&x"7357",'1'&x"7358",'1'&x"7359",'1'&x"735A",'1'&x"735B",'1'&x"735C",'1'&x"735D",'1'&x"735E",'1'&x"735F",
+--'1'&x"7360",'1'&x"7361",'1'&x"7362",'1'&x"7363",'1'&x"7364",'1'&x"7365",'1'&x"7366",'1'&x"7367",'1'&x"7368",'1'&x"7369",'1'&x"736A",'1'&x"736B",'1'&x"736C",'1'&x"736D",'1'&x"736E",'1'&x"736F",
+--'1'&x"7370",'1'&x"7371",'1'&x"7372",'1'&x"7373",'1'&x"7374",'1'&x"7375",'1'&x"7376",'1'&x"7377",'1'&x"7378",'1'&x"7379",'1'&x"737A",'1'&x"737B",'1'&x"737C",'1'&x"737D",'1'&x"737E",'1'&x"737F",
+--'1'&x"7380",'1'&x"7381",'1'&x"7382",'1'&x"7383",'1'&x"7384",'1'&x"7385",'1'&x"7386",'1'&x"7387",'1'&x"7388",'1'&x"7389",'1'&x"738A",'1'&x"738B",'1'&x"738C",'1'&x"738D",'1'&x"738E",'1'&x"738F",
+--'1'&x"7390",'1'&x"7391",'1'&x"7392",'1'&x"7393",'1'&x"7394",'1'&x"7395",'1'&x"7396",'1'&x"7397",'1'&x"7398",'1'&x"7399",'1'&x"739A",'1'&x"739B",'1'&x"739C",'1'&x"739D",'1'&x"739E",'1'&x"739F",
+--'1'&x"73A0",'1'&x"73A1",'1'&x"73A2",'1'&x"73A3",'1'&x"73A4",'1'&x"73A5",'1'&x"73A6",'1'&x"73A7",'1'&x"73A8",'1'&x"73A9",'1'&x"73AA",'1'&x"73AB",'1'&x"73AC",'1'&x"73AD",'1'&x"73AE",'1'&x"73AF",
+--'1'&x"73B0",'1'&x"73B1",'1'&x"73B2",'1'&x"73B3",'1'&x"73B4",'1'&x"73B5",'1'&x"73B6",'1'&x"73B7",'1'&x"73B8",'1'&x"73B9",'1'&x"73BA",'1'&x"73BB",'1'&x"73BC",'1'&x"73BD",'1'&x"73BE",'1'&x"73BF",
+--'1'&x"73C0",'1'&x"73C1",'1'&x"73C2",'1'&x"73C3",'1'&x"73C4",'1'&x"73C5",'1'&x"73C6",'1'&x"73C7",'1'&x"73C8",'1'&x"73C9",'1'&x"73CA",'1'&x"73CB",'1'&x"73CC",'1'&x"73CD",'1'&x"73CE",'1'&x"73CF",
+--'1'&x"73D0",'1'&x"73D1",'1'&x"73D2",'1'&x"73D3",'1'&x"73D4",'1'&x"73D5",'1'&x"73D6",'1'&x"73D7",'1'&x"73D8",'1'&x"73D9",'1'&x"73DA",'1'&x"73DB",'1'&x"73DC",'1'&x"73DD",'1'&x"73DE",'1'&x"73DF",
+--'1'&x"73E0",'1'&x"73E1",'1'&x"73E2",'1'&x"73E3",'1'&x"73E4",'1'&x"73E5",'1'&x"73E6",'1'&x"73E7",'1'&x"73E8",'1'&x"73E9",'1'&x"73EA",'1'&x"73EB",'1'&x"73EC",'1'&x"73ED",'1'&x"73EE",'1'&x"73EF",
+--'1'&x"73F0",'1'&x"73F1",'1'&x"73F2",'1'&x"73F3",'1'&x"73F4",'1'&x"73F5",'1'&x"73F6",'1'&x"73F7",'1'&x"73F8",'1'&x"73F9",'1'&x"73FA",'1'&x"73FB",'1'&x"73FC",'1'&x"73FD",'1'&x"73FE",'1'&x"73FF",
+--'1'&x"7400",'1'&x"7401",'1'&x"7402",'1'&x"7403",'1'&x"7404",'1'&x"7405",'1'&x"7406",'1'&x"7407",'1'&x"7408",'1'&x"7409",'1'&x"740A",'1'&x"740B",'1'&x"740C",'1'&x"740D",'1'&x"740E",'1'&x"740F",
+--'1'&x"7410",'1'&x"7411",'1'&x"7412",'1'&x"7413",'1'&x"7414",'1'&x"7415",'1'&x"7416",'1'&x"7417",'1'&x"7418",'1'&x"7419",'1'&x"741A",'1'&x"741B",'1'&x"741C",'1'&x"741D",'1'&x"741E",'1'&x"741F",
+--'1'&x"7420",'1'&x"7421",'1'&x"7422",'1'&x"7423",'1'&x"7424",'1'&x"7425",'1'&x"7426",'1'&x"7427",'1'&x"7428",'1'&x"7429",'1'&x"742A",'1'&x"742B",'1'&x"742C",'1'&x"742D",'1'&x"742E",'1'&x"742F",
+--'1'&x"7430",'1'&x"7431",'1'&x"7432",'1'&x"7433",'1'&x"7434",'1'&x"7435",'1'&x"7436",'1'&x"7437",'1'&x"7438",'1'&x"7439",'1'&x"743A",'1'&x"743B",'1'&x"743C",'1'&x"743D",'1'&x"743E",'1'&x"743F",
+--'1'&x"7440",'1'&x"7441",'1'&x"7442",'1'&x"7443",'1'&x"7444",'1'&x"7445",'1'&x"7446",'1'&x"7447",'1'&x"7448",'1'&x"7449",'1'&x"744A",'1'&x"744B",'1'&x"744C",'1'&x"744D",'1'&x"744E",'1'&x"744F",
+--'1'&x"7450",'1'&x"7451",'1'&x"7452",'1'&x"7453",'1'&x"7454",'1'&x"7455",'1'&x"7456",'1'&x"7457",'1'&x"7458",'1'&x"7459",'1'&x"745A",'1'&x"745B",'1'&x"745C",'1'&x"745D",'1'&x"745E",'1'&x"745F",
+--'1'&x"7460",'1'&x"7461",'1'&x"7462",'1'&x"7463",'1'&x"7464",'1'&x"7465",'1'&x"7466",'1'&x"7467",'1'&x"7468",'1'&x"7469",'1'&x"746A",'1'&x"746B",'1'&x"746C",'1'&x"746D",'1'&x"746E",'1'&x"746F",
+--'1'&x"7470",'1'&x"7471",'1'&x"7472",'1'&x"7473",'1'&x"7474",'1'&x"7475",'1'&x"7476",'1'&x"7477",'1'&x"7478",'1'&x"7479",'1'&x"747A",'1'&x"747B",'1'&x"747C",'1'&x"747D",'1'&x"747E",'1'&x"747F",
+--'1'&x"7480",'1'&x"7481",'1'&x"7482",'1'&x"7483",'1'&x"7484",'1'&x"7485",'1'&x"7486",'1'&x"7487",'1'&x"7488",'1'&x"7489",'1'&x"748A",'1'&x"748B",'1'&x"748C",'1'&x"748D",'1'&x"748E",'1'&x"748F",
+--'1'&x"7490",'1'&x"7491",'1'&x"7492",'1'&x"7493",'1'&x"7494",'1'&x"7495",'1'&x"7496",'1'&x"7497",'1'&x"7498",'1'&x"7499",'1'&x"749A",'1'&x"749B",'1'&x"749C",'1'&x"749D",'1'&x"749E",'1'&x"749F",
+--'1'&x"74A0",'1'&x"74A1",'1'&x"74A2",'1'&x"74A3",'1'&x"74A4",'1'&x"74A5",'1'&x"74A6",'1'&x"74A7",'1'&x"74A8",'1'&x"74A9",'1'&x"74AA",'1'&x"74AB",'1'&x"74AC",'1'&x"74AD",'1'&x"74AE",'1'&x"74AF",
+--'1'&x"74B0",'1'&x"74B1",'1'&x"74B2",'1'&x"74B3",'1'&x"74B4",'1'&x"74B5",'1'&x"74B6",'1'&x"74B7",'1'&x"74B8",'1'&x"74B9",'1'&x"74BA",'1'&x"74BB",'1'&x"74BC",'1'&x"74BD",'1'&x"74BE",'1'&x"74BF",
+--'1'&x"74C0",'1'&x"74C1",'1'&x"74C2",'1'&x"74C3",'1'&x"74C4",'1'&x"74C5",'1'&x"74C6",'1'&x"74C7",'1'&x"74C8",'1'&x"74C9",'1'&x"74CA",'1'&x"74CB",'1'&x"74CC",'1'&x"74CD",'1'&x"74CE",'1'&x"74CF",
+--'1'&x"74D0",'1'&x"74D1",'1'&x"74D2",'1'&x"74D3",'1'&x"74D4",'1'&x"74D5",'1'&x"74D6",'1'&x"74D7",'1'&x"74D8",'1'&x"74D9",'1'&x"74DA",'1'&x"74DB",'1'&x"74DC",'1'&x"74DD",'1'&x"74DE",'1'&x"74DF",
+--'1'&x"74E0",'1'&x"74E1",'1'&x"74E2",'1'&x"74E3",'1'&x"74E4",'1'&x"74E5",'1'&x"74E6",'1'&x"74E7",'1'&x"74E8",'1'&x"74E9",'1'&x"74EA",'1'&x"74EB",'1'&x"74EC",'1'&x"74ED",'1'&x"74EE",'1'&x"74EF",
+--'1'&x"74F0",'1'&x"74F1",'1'&x"74F2",'1'&x"74F3",'1'&x"74F4",'1'&x"74F5",'1'&x"74F6",'1'&x"74F7",'1'&x"74F8",'1'&x"74F9",'1'&x"74FA",'1'&x"74FB",'1'&x"74FC",'1'&x"74FD",'1'&x"74FE",'1'&x"74FF",
+--'1'&x"7500",'1'&x"7501",'1'&x"7502",'1'&x"7503",'1'&x"7504",'1'&x"7505",'1'&x"7506",'1'&x"7507",'1'&x"7508",'1'&x"7509",'1'&x"750A",'1'&x"750B",'1'&x"750C",'1'&x"750D",'1'&x"750E",'1'&x"750F",
+--'1'&x"7510",'1'&x"7511",'1'&x"7512",'1'&x"7513",'1'&x"7514",'1'&x"7515",'1'&x"7516",'1'&x"7517",'1'&x"7518",'1'&x"7519",'1'&x"751A",'1'&x"751B",'1'&x"751C",'1'&x"751D",'1'&x"751E",'1'&x"751F",
+--'1'&x"7520",'1'&x"7521",'1'&x"7522",'1'&x"7523",'1'&x"7524",'1'&x"7525",'1'&x"7526",'1'&x"7527",'1'&x"7528",'1'&x"7529",'1'&x"752A",'1'&x"752B",'1'&x"752C",'1'&x"752D",'1'&x"752E",'1'&x"752F",
+--'1'&x"7530",'1'&x"7531",'1'&x"7532",'1'&x"7533",'1'&x"7534",'1'&x"7535",'1'&x"7536",'1'&x"7537",'1'&x"7538",'1'&x"7539",'1'&x"753A",'1'&x"753B",'1'&x"753C",'1'&x"753D",'1'&x"753E",'1'&x"753F",
+--'1'&x"7540",'1'&x"7541",'1'&x"7542",'1'&x"7543",'1'&x"7544",'1'&x"7545",'1'&x"7546",'1'&x"7547",'1'&x"7548",'1'&x"7549",'1'&x"754A",'1'&x"754B",'1'&x"754C",'1'&x"754D",'1'&x"754E",'1'&x"754F",
+--'1'&x"7550",'1'&x"7551",'1'&x"7552",'1'&x"7553",'1'&x"7554",'1'&x"7555",'1'&x"7556",'1'&x"7557",'1'&x"7558",'1'&x"7559",'1'&x"755A",'1'&x"755B",'1'&x"755C",'1'&x"755D",'1'&x"755E",'1'&x"755F",
+--'1'&x"7560",'1'&x"7561",'1'&x"7562",'1'&x"7563",'1'&x"7564",'1'&x"7565",'1'&x"7566",'1'&x"7567",'1'&x"7568",'1'&x"7569",'1'&x"756A",'1'&x"756B",'1'&x"756C",'1'&x"756D",'1'&x"756E",'1'&x"756F",
+--'1'&x"7570",'1'&x"7571",'1'&x"7572",'1'&x"7573",'1'&x"7574",'1'&x"7575",'1'&x"7576",'1'&x"7577",'1'&x"7578",'1'&x"7579",'1'&x"757A",'1'&x"757B",'1'&x"757C",'1'&x"757D",'1'&x"757E",'1'&x"757F",
+--'1'&x"7580",'1'&x"7581",'1'&x"7582",'1'&x"7583",'1'&x"7584",'1'&x"7585",'1'&x"7586",'1'&x"7587",'1'&x"7588",'1'&x"7589",'1'&x"758A",'1'&x"758B",'1'&x"758C",'1'&x"758D",'1'&x"758E",'1'&x"758F",
+--'1'&x"7590",'1'&x"7591",'1'&x"7592",'1'&x"7593",'1'&x"7594",'1'&x"7595",'1'&x"7596",'1'&x"7597",'1'&x"7598",'1'&x"7599",'1'&x"759A",'1'&x"759B",'1'&x"759C",'1'&x"759D",'1'&x"759E",'1'&x"759F",
+--'1'&x"75A0",'1'&x"75A1",'1'&x"75A2",'1'&x"75A3",'1'&x"75A4",'1'&x"75A5",'1'&x"75A6",'1'&x"75A7",'1'&x"75A8",'1'&x"75A9",'1'&x"75AA",'1'&x"75AB",'1'&x"75AC",'1'&x"75AD",'1'&x"75AE",'1'&x"75AF",
+--'1'&x"75B0",'1'&x"75B1",'1'&x"75B2",'1'&x"75B3",'1'&x"75B4",'1'&x"75B5",'1'&x"75B6",'1'&x"75B7",'1'&x"75B8",'1'&x"75B9",'1'&x"75BA",'1'&x"75BB",'1'&x"75BC",'1'&x"75BD",'1'&x"75BE",'1'&x"75BF",
+--'1'&x"75C0",'1'&x"75C1",'1'&x"75C2",'1'&x"75C3",'1'&x"75C4",'1'&x"75C5",'1'&x"75C6",'1'&x"75C7",'1'&x"75C8",'1'&x"75C9",'1'&x"75CA",'1'&x"75CB",'1'&x"75CC",'1'&x"75CD",'1'&x"75CE",'1'&x"75CF",
+--'1'&x"75D0",'1'&x"75D1",'1'&x"75D2",'1'&x"75D3",'1'&x"75D4",'1'&x"75D5",'1'&x"75D6",'1'&x"75D7",'1'&x"75D8",'1'&x"75D9",'1'&x"75DA",'1'&x"75DB",'1'&x"75DC",'1'&x"75DD",'1'&x"75DE",'1'&x"75DF",
+--'1'&x"75E0",'1'&x"75E1",'1'&x"75E2",'1'&x"75E3",'1'&x"75E4",'1'&x"75E5",'1'&x"75E6",'1'&x"75E7",'1'&x"75E8",'1'&x"75E9",'1'&x"75EA",'1'&x"75EB",'1'&x"75EC",'1'&x"75ED",'1'&x"75EE",'1'&x"75EF",
+--'1'&x"75F0",'1'&x"75F1",'1'&x"75F2",'1'&x"75F3",'1'&x"75F4",'1'&x"75F5",'1'&x"75F6",'1'&x"75F7",'1'&x"75F8",'1'&x"75F9",'1'&x"75FA",'1'&x"75FB",'1'&x"75FC",'1'&x"75FD",'1'&x"75FE",'1'&x"75FF",
+--'1'&x"7600",'1'&x"7601",'1'&x"7602",'1'&x"7603",'1'&x"7604",'1'&x"7605",'1'&x"7606",'1'&x"7607",'1'&x"7608",'1'&x"7609",'1'&x"760A",'1'&x"760B",'1'&x"760C",'1'&x"760D",'1'&x"760E",'1'&x"760F",
+--'1'&x"7610",'1'&x"7611",'1'&x"7612",'1'&x"7613",'1'&x"7614",'1'&x"7615",'1'&x"7616",'1'&x"7617",'1'&x"7618",'1'&x"7619",'1'&x"761A",'1'&x"761B",'1'&x"761C",'1'&x"761D",'1'&x"761E",'1'&x"761F",
+--'1'&x"7620",'1'&x"7621",'1'&x"7622",'1'&x"7623",'1'&x"7624",'1'&x"7625",'1'&x"7626",'1'&x"7627",'1'&x"7628",'1'&x"7629",'1'&x"762A",'1'&x"762B",'1'&x"762C",'1'&x"762D",'1'&x"762E",'1'&x"762F",
+--'1'&x"7630",'1'&x"7631",'1'&x"7632",'1'&x"7633",'1'&x"7634",'1'&x"7635",'1'&x"7636",'1'&x"7637",'1'&x"7638",'1'&x"7639",'1'&x"763A",'1'&x"763B",'1'&x"763C",'1'&x"763D",'1'&x"763E",'1'&x"763F",
+--'1'&x"7640",'1'&x"7641",'1'&x"7642",'1'&x"7643",'1'&x"7644",'1'&x"7645",'1'&x"7646",'1'&x"7647",'1'&x"7648",'1'&x"7649",'1'&x"764A",'1'&x"764B",'1'&x"764C",'1'&x"764D",'1'&x"764E",'1'&x"764F",
+--'1'&x"7650",'1'&x"7651",'1'&x"7652",'1'&x"7653",'1'&x"7654",'1'&x"7655",'1'&x"7656",'1'&x"7657",'1'&x"7658",'1'&x"7659",'1'&x"765A",'1'&x"765B",'1'&x"765C",'1'&x"765D",'1'&x"765E",'1'&x"765F",
+--'1'&x"7660",'1'&x"7661",'1'&x"7662",'1'&x"7663",'1'&x"7664",'1'&x"7665",'1'&x"7666",'1'&x"7667",'1'&x"7668",'1'&x"7669",'1'&x"766A",'1'&x"766B",'1'&x"766C",'1'&x"766D",'1'&x"766E",'1'&x"766F",
+--'1'&x"7670",'1'&x"7671",'1'&x"7672",'1'&x"7673",'1'&x"7674",'1'&x"7675",'1'&x"7676",'1'&x"7677",'1'&x"7678",'1'&x"7679",'1'&x"767A",'1'&x"767B",'1'&x"767C",'1'&x"767D",'1'&x"767E",'1'&x"767F",
+--'1'&x"7680",'1'&x"7681",'1'&x"7682",'1'&x"7683",'1'&x"7684",'1'&x"7685",'1'&x"7686",'1'&x"7687",'1'&x"7688",'1'&x"7689",'1'&x"768A",'1'&x"768B",'1'&x"768C",'1'&x"768D",'1'&x"768E",'1'&x"768F",
+--'1'&x"7690",'1'&x"7691",'1'&x"7692",'1'&x"7693",'1'&x"7694",'1'&x"7695",'1'&x"7696",'1'&x"7697",'1'&x"7698",'1'&x"7699",'1'&x"769A",'1'&x"769B",'1'&x"769C",'1'&x"769D",'1'&x"769E",'1'&x"769F",
+--'1'&x"76A0",'1'&x"76A1",'1'&x"76A2",'1'&x"76A3",'1'&x"76A4",'1'&x"76A5",'1'&x"76A6",'1'&x"76A7",'1'&x"76A8",'1'&x"76A9",'1'&x"76AA",'1'&x"76AB",'1'&x"76AC",'1'&x"76AD",'1'&x"76AE",'1'&x"76AF",
+--'1'&x"76B0",'1'&x"76B1",'1'&x"76B2",'1'&x"76B3",'1'&x"76B4",'1'&x"76B5",'1'&x"76B6",'1'&x"76B7",'1'&x"76B8",'1'&x"76B9",'1'&x"76BA",'1'&x"76BB",'1'&x"76BC",'1'&x"76BD",'1'&x"76BE",'1'&x"76BF",
+--'1'&x"76C0",'1'&x"76C1",'1'&x"76C2",'1'&x"76C3",'1'&x"76C4",'1'&x"76C5",'1'&x"76C6",'1'&x"76C7",'1'&x"76C8",'1'&x"76C9",'1'&x"76CA",'1'&x"76CB",'1'&x"76CC",'1'&x"76CD",'1'&x"76CE",'1'&x"76CF",
+--'1'&x"76D0",'1'&x"76D1",'1'&x"76D2",'1'&x"76D3",'1'&x"76D4",'1'&x"76D5",'1'&x"76D6",'1'&x"76D7",'1'&x"76D8",'1'&x"76D9",'1'&x"76DA",'1'&x"76DB",'1'&x"76DC",'1'&x"76DD",'1'&x"76DE",'1'&x"76DF",
+--'1'&x"76E0",'1'&x"76E1",'1'&x"76E2",'1'&x"76E3",'1'&x"76E4",'1'&x"76E5",'1'&x"76E6",'1'&x"76E7",'1'&x"76E8",'1'&x"76E9",'1'&x"76EA",'1'&x"76EB",'1'&x"76EC",'1'&x"76ED",'1'&x"76EE",'1'&x"76EF",
+--'1'&x"76F0",'1'&x"76F1",'1'&x"76F2",'1'&x"76F3",'1'&x"76F4",'1'&x"76F5",'1'&x"76F6",'1'&x"76F7",'1'&x"76F8",'1'&x"76F9",'1'&x"76FA",'1'&x"76FB",'1'&x"76FC",'1'&x"76FD",'1'&x"76FE",'1'&x"76FF",
+--'1'&x"7700",'1'&x"7701",'1'&x"7702",'1'&x"7703",'1'&x"7704",'1'&x"7705",'1'&x"7706",'1'&x"7707",'1'&x"7708",'1'&x"7709",'1'&x"770A",'1'&x"770B",'1'&x"770C",'1'&x"770D",'1'&x"770E",'1'&x"770F",
+--'1'&x"7710",'1'&x"7711",'1'&x"7712",'1'&x"7713",'1'&x"7714",'1'&x"7715",'1'&x"7716",'1'&x"7717",'1'&x"7718",'1'&x"7719",'1'&x"771A",'1'&x"771B",'1'&x"771C",'1'&x"771D",'1'&x"771E",'1'&x"771F",
+--'1'&x"7720",'1'&x"7721",'1'&x"7722",'1'&x"7723",'1'&x"7724",'1'&x"7725",'1'&x"7726",'1'&x"7727",'1'&x"7728",'1'&x"7729",'1'&x"772A",'1'&x"772B",'1'&x"772C",'1'&x"772D",'1'&x"772E",'1'&x"772F",
+--'1'&x"7730",'1'&x"7731",'1'&x"7732",'1'&x"7733",'1'&x"7734",'1'&x"7735",'1'&x"7736",'1'&x"7737",'1'&x"7738",'1'&x"7739",'1'&x"773A",'1'&x"773B",'1'&x"773C",'1'&x"773D",'1'&x"773E",'1'&x"773F",
+--'1'&x"7740",'1'&x"7741",'1'&x"7742",'1'&x"7743",'1'&x"7744",'1'&x"7745",'1'&x"7746",'1'&x"7747",'1'&x"7748",'1'&x"7749",'1'&x"774A",'1'&x"774B",'1'&x"774C",'1'&x"774D",'1'&x"774E",'1'&x"774F",
+--'1'&x"7750",'1'&x"7751",'1'&x"7752",'1'&x"7753",'1'&x"7754",'1'&x"7755",'1'&x"7756",'1'&x"7757",'1'&x"7758",'1'&x"7759",'1'&x"775A",'1'&x"775B",'1'&x"775C",'1'&x"775D",'1'&x"775E",'1'&x"775F",
+--'1'&x"7760",'1'&x"7761",'1'&x"7762",'1'&x"7763",'1'&x"7764",'1'&x"7765",'1'&x"7766",'1'&x"7767",'1'&x"7768",'1'&x"7769",'1'&x"776A",'1'&x"776B",'1'&x"776C",'1'&x"776D",'1'&x"776E",'1'&x"776F",
+--'1'&x"7770",'1'&x"7771",'1'&x"7772",'1'&x"7773",'1'&x"7774",'1'&x"7775",'1'&x"7776",'1'&x"7777",'1'&x"7778",'1'&x"7779",'1'&x"777A",'1'&x"777B",'1'&x"777C",'1'&x"777D",'1'&x"777E",'1'&x"777F",
+--'1'&x"7780",'1'&x"7781",'1'&x"7782",'1'&x"7783",'1'&x"7784",'1'&x"7785",'1'&x"7786",'1'&x"7787",'1'&x"7788",'1'&x"7789",'1'&x"778A",'1'&x"778B",'1'&x"778C",'1'&x"778D",'1'&x"778E",'1'&x"778F",
+--'1'&x"7790",'1'&x"7791",'1'&x"7792",'1'&x"7793",'1'&x"7794",'1'&x"7795",'1'&x"7796",'1'&x"7797",'1'&x"7798",'1'&x"7799",'1'&x"779A",'1'&x"779B",'1'&x"779C",'1'&x"779D",'1'&x"779E",'1'&x"779F",
+--'1'&x"77A0",'1'&x"77A1",'1'&x"77A2",'1'&x"77A3",'1'&x"77A4",'1'&x"77A5",'1'&x"77A6",'1'&x"77A7",'1'&x"77A8",'1'&x"77A9",'1'&x"77AA",'1'&x"77AB",'1'&x"77AC",'1'&x"77AD",'1'&x"77AE",'1'&x"77AF",
+--'1'&x"77B0",'1'&x"77B1",'1'&x"77B2",'1'&x"77B3",'1'&x"77B4",'1'&x"77B5",'1'&x"77B6",'1'&x"77B7",'1'&x"77B8",'1'&x"77B9",'1'&x"77BA",'1'&x"77BB",'1'&x"77BC",'1'&x"77BD",'1'&x"77BE",'1'&x"77BF",
+--'1'&x"77C0",'1'&x"77C1",'1'&x"77C2",'1'&x"77C3",'1'&x"77C4",'1'&x"77C5",'1'&x"77C6",'1'&x"77C7",'1'&x"77C8",'1'&x"77C9",'1'&x"77CA",'1'&x"77CB",'1'&x"77CC",'1'&x"77CD",'1'&x"77CE",'1'&x"77CF",
+--'1'&x"77D0",'1'&x"77D1",'1'&x"77D2",'1'&x"77D3",'1'&x"77D4",'1'&x"77D5",'1'&x"77D6",'1'&x"77D7",'1'&x"77D8",'1'&x"77D9",'1'&x"77DA",'1'&x"77DB",'1'&x"77DC",'1'&x"77DD",'1'&x"77DE",'1'&x"77DF",
+--'1'&x"77E0",'1'&x"77E1",'1'&x"77E2",'1'&x"77E3",'1'&x"77E4",'1'&x"77E5",'1'&x"77E6",'1'&x"77E7",'1'&x"77E8",'1'&x"77E9",'1'&x"77EA",'1'&x"77EB",'1'&x"77EC",'1'&x"77ED",'1'&x"77EE",'1'&x"77EF",
+--'1'&x"77F0",'1'&x"77F1",'1'&x"77F2",'1'&x"77F3",'1'&x"77F4",'1'&x"77F5",'1'&x"77F6",'1'&x"77F7",'1'&x"77F8",'1'&x"77F9",'1'&x"77FA",'1'&x"77FB",'1'&x"77FC",'1'&x"77FD",'1'&x"77FE",'1'&x"77FF",
+--'1'&x"7800",'1'&x"7801",'1'&x"7802",'1'&x"7803",'1'&x"7804",'1'&x"7805",'1'&x"7806",'1'&x"7807",'1'&x"7808",'1'&x"7809",'1'&x"780A",'1'&x"780B",'1'&x"780C",'1'&x"780D",'1'&x"780E",'1'&x"780F",
+--'1'&x"7810",'1'&x"7811",'1'&x"7812",'1'&x"7813",'1'&x"7814",'1'&x"7815",'1'&x"7816",'1'&x"7817",'1'&x"7818",'1'&x"7819",'1'&x"781A",'1'&x"781B",'1'&x"781C",'1'&x"781D",'1'&x"781E",'1'&x"781F",
+--'1'&x"7820",'1'&x"7821",'1'&x"7822",'1'&x"7823",'1'&x"7824",'1'&x"7825",'1'&x"7826",'1'&x"7827",'1'&x"7828",'1'&x"7829",'1'&x"782A",'1'&x"782B",'1'&x"782C",'1'&x"782D",'1'&x"782E",'1'&x"782F",
+--'1'&x"7830",'1'&x"7831",'1'&x"7832",'1'&x"7833",'1'&x"7834",'1'&x"7835",'1'&x"7836",'1'&x"7837",'1'&x"7838",'1'&x"7839",'1'&x"783A",'1'&x"783B",'1'&x"783C",'1'&x"783D",'1'&x"783E",'1'&x"783F",
+--'1'&x"7840",'1'&x"7841",'1'&x"7842",'1'&x"7843",'1'&x"7844",'1'&x"7845",'1'&x"7846",'1'&x"7847",'1'&x"7848",'1'&x"7849",'1'&x"784A",'1'&x"784B",'1'&x"784C",'1'&x"784D",'1'&x"784E",'1'&x"784F",
+--'1'&x"7850",'1'&x"7851",'1'&x"7852",'1'&x"7853",'1'&x"7854",'1'&x"7855",'1'&x"7856",'1'&x"7857",'1'&x"7858",'1'&x"7859",'1'&x"785A",'1'&x"785B",'1'&x"785C",'1'&x"785D",'1'&x"785E",'1'&x"785F",
+--'1'&x"7860",'1'&x"7861",'1'&x"7862",'1'&x"7863",'1'&x"7864",'1'&x"7865",'1'&x"7866",'1'&x"7867",'1'&x"7868",'1'&x"7869",'1'&x"786A",'1'&x"786B",'1'&x"786C",'1'&x"786D",'1'&x"786E",'1'&x"786F",
+--'1'&x"7870",'1'&x"7871",'1'&x"7872",'1'&x"7873",'1'&x"7874",'1'&x"7875",'1'&x"7876",'1'&x"7877",'1'&x"7878",'1'&x"7879",'1'&x"787A",'1'&x"787B",'1'&x"787C",'1'&x"787D",'1'&x"787E",'1'&x"787F",
+--'1'&x"7880",'1'&x"7881",'1'&x"7882",'1'&x"7883",'1'&x"7884",'1'&x"7885",'1'&x"7886",'1'&x"7887",'1'&x"7888",'1'&x"7889",'1'&x"788A",'1'&x"788B",'1'&x"788C",'1'&x"788D",'1'&x"788E",'1'&x"788F",
+--'1'&x"7890",'1'&x"7891",'1'&x"7892",'1'&x"7893",'1'&x"7894",'1'&x"7895",'1'&x"7896",'1'&x"7897",'1'&x"7898",'1'&x"7899",'1'&x"789A",'1'&x"789B",'1'&x"789C",'1'&x"789D",'1'&x"789E",'1'&x"789F",
+--'1'&x"78A0",'1'&x"78A1",'1'&x"78A2",'1'&x"78A3",'1'&x"78A4",'1'&x"78A5",'1'&x"78A6",'1'&x"78A7",'1'&x"78A8",'1'&x"78A9",'1'&x"78AA",'1'&x"78AB",'1'&x"78AC",'1'&x"78AD",'1'&x"78AE",'1'&x"78AF",
+--'1'&x"78B0",'1'&x"78B1",'1'&x"78B2",'1'&x"78B3",'1'&x"78B4",'1'&x"78B5",'1'&x"78B6",'1'&x"78B7",'1'&x"78B8",'1'&x"78B9",'1'&x"78BA",'1'&x"78BB",'1'&x"78BC",'1'&x"78BD",'1'&x"78BE",'1'&x"78BF",
+--'1'&x"78C0",'1'&x"78C1",'1'&x"78C2",'1'&x"78C3",'1'&x"78C4",'1'&x"78C5",'1'&x"78C6",'1'&x"78C7",'1'&x"78C8",'1'&x"78C9",'1'&x"78CA",'1'&x"78CB",'1'&x"78CC",'1'&x"78CD",'1'&x"78CE",'1'&x"78CF",
+--'1'&x"78D0",'1'&x"78D1",'1'&x"78D2",'1'&x"78D3",'1'&x"78D4",'1'&x"78D5",'1'&x"78D6",'1'&x"78D7",'1'&x"78D8",'1'&x"78D9",'1'&x"78DA",'1'&x"78DB",'1'&x"78DC",'1'&x"78DD",'1'&x"78DE",'1'&x"78DF",
+--'1'&x"78E0",'1'&x"78E1",'1'&x"78E2",'1'&x"78E3",'1'&x"78E4",'1'&x"78E5",'1'&x"78E6",'1'&x"78E7",'1'&x"78E8",'1'&x"78E9",'1'&x"78EA",'1'&x"78EB",'1'&x"78EC",'1'&x"78ED",'1'&x"78EE",'1'&x"78EF",
+--'1'&x"78F0",'1'&x"78F1",'1'&x"78F2",'1'&x"78F3",'1'&x"78F4",'1'&x"78F5",'1'&x"78F6",'1'&x"78F7",'1'&x"78F8",'1'&x"78F9",'1'&x"78FA",'1'&x"78FB",'1'&x"78FC",'1'&x"78FD",'1'&x"78FE",'1'&x"78FF",
+--'1'&x"7900",'1'&x"7901",'1'&x"7902",'1'&x"7903",'1'&x"7904",'1'&x"7905",'1'&x"7906",'1'&x"7907",'1'&x"7908",'1'&x"7909",'1'&x"790A",'1'&x"790B",'1'&x"790C",'1'&x"790D",'1'&x"790E",'1'&x"790F",
+--'1'&x"7910",'1'&x"7911",'1'&x"7912",'1'&x"7913",'1'&x"7914",'1'&x"7915",'1'&x"7916",'1'&x"7917",'1'&x"7918",'1'&x"7919",'1'&x"791A",'1'&x"791B",'1'&x"791C",'1'&x"791D",'1'&x"791E",'1'&x"791F",
+--'1'&x"7920",'1'&x"7921",'1'&x"7922",'1'&x"7923",'1'&x"7924",'1'&x"7925",'1'&x"7926",'1'&x"7927",'1'&x"7928",'1'&x"7929",'1'&x"792A",'1'&x"792B",'1'&x"792C",'1'&x"792D",'1'&x"792E",'1'&x"792F",
+--'1'&x"7930",'1'&x"7931",'1'&x"7932",'1'&x"7933",'1'&x"7934",'1'&x"7935",'1'&x"7936",'1'&x"7937",'1'&x"7938",'1'&x"7939",'1'&x"793A",'1'&x"793B",'1'&x"793C",'1'&x"793D",'1'&x"793E",'1'&x"793F",
+--'1'&x"7940",'1'&x"7941",'1'&x"7942",'1'&x"7943",'1'&x"7944",'1'&x"7945",'1'&x"7946",'1'&x"7947",'1'&x"7948",'1'&x"7949",'1'&x"794A",'1'&x"794B",'1'&x"794C",'1'&x"794D",'1'&x"794E",'1'&x"794F",
+--'1'&x"7950",'1'&x"7951",'1'&x"7952",'1'&x"7953",'1'&x"7954",'1'&x"7955",'1'&x"7956",'1'&x"7957",'1'&x"7958",'1'&x"7959",'1'&x"795A",'1'&x"795B",'1'&x"795C",'1'&x"795D",'1'&x"795E",'1'&x"795F",
+--'1'&x"7960",'1'&x"7961",'1'&x"7962",'1'&x"7963",'1'&x"7964",'1'&x"7965",'1'&x"7966",'1'&x"7967",'1'&x"7968",'1'&x"7969",'1'&x"796A",'1'&x"796B",'1'&x"796C",'1'&x"796D",'1'&x"796E",'1'&x"796F",
+--'1'&x"7970",'1'&x"7971",'1'&x"7972",'1'&x"7973",'1'&x"7974",'1'&x"7975",'1'&x"7976",'1'&x"7977",'1'&x"7978",'1'&x"7979",'1'&x"797A",'1'&x"797B",'1'&x"797C",'1'&x"797D",'1'&x"797E",'1'&x"797F",
+--'1'&x"7980",'1'&x"7981",'1'&x"7982",'1'&x"7983",'1'&x"7984",'1'&x"7985",'1'&x"7986",'1'&x"7987",'1'&x"7988",'1'&x"7989",'1'&x"798A",'1'&x"798B",'1'&x"798C",'1'&x"798D",'1'&x"798E",'1'&x"798F",
+--'1'&x"7990",'1'&x"7991",'1'&x"7992",'1'&x"7993",'1'&x"7994",'1'&x"7995",'1'&x"7996",'1'&x"7997",'1'&x"7998",'1'&x"7999",'1'&x"799A",'1'&x"799B",'1'&x"799C",'1'&x"799D",'1'&x"799E",'1'&x"799F",
+--'1'&x"79A0",'1'&x"79A1",'1'&x"79A2",'1'&x"79A3",'1'&x"79A4",'1'&x"79A5",'1'&x"79A6",'1'&x"79A7",'1'&x"79A8",'1'&x"79A9",'1'&x"79AA",'1'&x"79AB",'1'&x"79AC",'1'&x"79AD",'1'&x"79AE",'1'&x"79AF",
+--'1'&x"79B0",'1'&x"79B1",'1'&x"79B2",'1'&x"79B3",'1'&x"79B4",'1'&x"79B5",'1'&x"79B6",'1'&x"79B7",'1'&x"79B8",'1'&x"79B9",'1'&x"79BA",'1'&x"79BB",'1'&x"79BC",'1'&x"79BD",'1'&x"79BE",'1'&x"79BF",
+--'1'&x"79C0",'1'&x"79C1",'1'&x"79C2",'1'&x"79C3",'1'&x"79C4",'1'&x"79C5",'1'&x"79C6",'1'&x"79C7",'1'&x"79C8",'1'&x"79C9",'1'&x"79CA",'1'&x"79CB",'1'&x"79CC",'1'&x"79CD",'1'&x"79CE",'1'&x"79CF",
+--'1'&x"79D0",'1'&x"79D1",'1'&x"79D2",'1'&x"79D3",'1'&x"79D4",'1'&x"79D5",'1'&x"79D6",'1'&x"79D7",'1'&x"79D8",'1'&x"79D9",'1'&x"79DA",'1'&x"79DB",'1'&x"79DC",'1'&x"79DD",'1'&x"79DE",'1'&x"79DF",
+--'1'&x"79E0",'1'&x"79E1",'1'&x"79E2",'1'&x"79E3",'1'&x"79E4",'1'&x"79E5",'1'&x"79E6",'1'&x"79E7",'1'&x"79E8",'1'&x"79E9",'1'&x"79EA",'1'&x"79EB",'1'&x"79EC",'1'&x"79ED",'1'&x"79EE",'1'&x"79EF",
+--'1'&x"79F0",'1'&x"79F1",'1'&x"79F2",'1'&x"79F3",'1'&x"79F4",'1'&x"79F5",'1'&x"79F6",'1'&x"79F7",'1'&x"79F8",'1'&x"79F9",'1'&x"79FA",'1'&x"79FB",'1'&x"79FC",'1'&x"79FD",'1'&x"79FE",'1'&x"79FF",
+--'1'&x"7A00",'1'&x"7A01",'1'&x"7A02",'1'&x"7A03",'1'&x"7A04",'1'&x"7A05",'1'&x"7A06",'1'&x"7A07",'1'&x"7A08",'1'&x"7A09",'1'&x"7A0A",'1'&x"7A0B",'1'&x"7A0C",'1'&x"7A0D",'1'&x"7A0E",'1'&x"7A0F",
+--'1'&x"7A10",'1'&x"7A11",'1'&x"7A12",'1'&x"7A13",'1'&x"7A14",'1'&x"7A15",'1'&x"7A16",'1'&x"7A17",'1'&x"7A18",'1'&x"7A19",'1'&x"7A1A",'1'&x"7A1B",'1'&x"7A1C",'1'&x"7A1D",'1'&x"7A1E",'1'&x"7A1F",
+--'1'&x"7A20",'1'&x"7A21",'1'&x"7A22",'1'&x"7A23",'1'&x"7A24",'1'&x"7A25",'1'&x"7A26",'1'&x"7A27",'1'&x"7A28",'1'&x"7A29",'1'&x"7A2A",'1'&x"7A2B",'1'&x"7A2C",'1'&x"7A2D",'1'&x"7A2E",'1'&x"7A2F",
+--'1'&x"7A30",'1'&x"7A31",'1'&x"7A32",'1'&x"7A33",'1'&x"7A34",'1'&x"7A35",'1'&x"7A36",'1'&x"7A37",'1'&x"7A38",'1'&x"7A39",'1'&x"7A3A",'1'&x"7A3B",'1'&x"7A3C",'1'&x"7A3D",'1'&x"7A3E",'1'&x"7A3F",
+--'1'&x"7A40",'1'&x"7A41",'1'&x"7A42",'1'&x"7A43",'1'&x"7A44",'1'&x"7A45",'1'&x"7A46",'1'&x"7A47",'1'&x"7A48",'1'&x"7A49",'1'&x"7A4A",'1'&x"7A4B",'1'&x"7A4C",'1'&x"7A4D",'1'&x"7A4E",'1'&x"7A4F",
+--'1'&x"7A50",'1'&x"7A51",'1'&x"7A52",'1'&x"7A53",'1'&x"7A54",'1'&x"7A55",'1'&x"7A56",'1'&x"7A57",'1'&x"7A58",'1'&x"7A59",'1'&x"7A5A",'1'&x"7A5B",'1'&x"7A5C",'1'&x"7A5D",'1'&x"7A5E",'1'&x"7A5F",
+--'1'&x"7A60",'1'&x"7A61",'1'&x"7A62",'1'&x"7A63",'1'&x"7A64",'1'&x"7A65",'1'&x"7A66",'1'&x"7A67",'1'&x"7A68",'1'&x"7A69",'1'&x"7A6A",'1'&x"7A6B",'1'&x"7A6C",'1'&x"7A6D",'1'&x"7A6E",'1'&x"7A6F",
+--'1'&x"7A70",'1'&x"7A71",'1'&x"7A72",'1'&x"7A73",'1'&x"7A74",'1'&x"7A75",'1'&x"7A76",'1'&x"7A77",'1'&x"7A78",'1'&x"7A79",'1'&x"7A7A",'1'&x"7A7B",'1'&x"7A7C",'1'&x"7A7D",'1'&x"7A7E",'1'&x"7A7F",
+--'1'&x"7A80",'1'&x"7A81",'1'&x"7A82",'1'&x"7A83",'1'&x"7A84",'1'&x"7A85",'1'&x"7A86",'1'&x"7A87",'1'&x"7A88",'1'&x"7A89",'1'&x"7A8A",'1'&x"7A8B",'1'&x"7A8C",'1'&x"7A8D",'1'&x"7A8E",'1'&x"7A8F",
+--'1'&x"7A90",'1'&x"7A91",'1'&x"7A92",'1'&x"7A93",'1'&x"7A94",'1'&x"7A95",'1'&x"7A96",'1'&x"7A97",'1'&x"7A98",'1'&x"7A99",'1'&x"7A9A",'1'&x"7A9B",'1'&x"7A9C",'1'&x"7A9D",'1'&x"7A9E",'1'&x"7A9F",
+--'1'&x"7AA0",'1'&x"7AA1",'1'&x"7AA2",'1'&x"7AA3",'1'&x"7AA4",'1'&x"7AA5",'1'&x"7AA6",'1'&x"7AA7",'1'&x"7AA8",'1'&x"7AA9",'1'&x"7AAA",'1'&x"7AAB",'1'&x"7AAC",'1'&x"7AAD",'1'&x"7AAE",'1'&x"7AAF",
+--'1'&x"7AB0",'1'&x"7AB1",'1'&x"7AB2",'1'&x"7AB3",'1'&x"7AB4",'1'&x"7AB5",'1'&x"7AB6",'1'&x"7AB7",'1'&x"7AB8",'1'&x"7AB9",'1'&x"7ABA",'1'&x"7ABB",'1'&x"7ABC",'1'&x"7ABD",'1'&x"7ABE",'1'&x"7ABF",
+--'1'&x"7AC0",'1'&x"7AC1",'1'&x"7AC2",'1'&x"7AC3",'1'&x"7AC4",'1'&x"7AC5",'1'&x"7AC6",'1'&x"7AC7",'1'&x"7AC8",'1'&x"7AC9",'1'&x"7ACA",'1'&x"7ACB",'1'&x"7ACC",'1'&x"7ACD",'1'&x"7ACE",'1'&x"7ACF",
+--'1'&x"7AD0",'1'&x"7AD1",'1'&x"7AD2",'1'&x"7AD3",'1'&x"7AD4",'1'&x"7AD5",'1'&x"7AD6",'1'&x"7AD7",'1'&x"7AD8",'1'&x"7AD9",'1'&x"7ADA",'1'&x"7ADB",'1'&x"7ADC",'1'&x"7ADD",'1'&x"7ADE",'1'&x"7ADF",
+--'1'&x"7AE0",'1'&x"7AE1",'1'&x"7AE2",'1'&x"7AE3",'1'&x"7AE4",'1'&x"7AE5",'1'&x"7AE6",'1'&x"7AE7",'1'&x"7AE8",'1'&x"7AE9",'1'&x"7AEA",'1'&x"7AEB",'1'&x"7AEC",'1'&x"7AED",'1'&x"7AEE",'1'&x"7AEF",
+--'1'&x"7AF0",'1'&x"7AF1",'1'&x"7AF2",'1'&x"7AF3",'1'&x"7AF4",'1'&x"7AF5",'1'&x"7AF6",'1'&x"7AF7",'1'&x"7AF8",'1'&x"7AF9",'1'&x"7AFA",'1'&x"7AFB",'1'&x"7AFC",'1'&x"7AFD",'1'&x"7AFE",'1'&x"7AFF",
+--'1'&x"7B00",'1'&x"7B01",'1'&x"7B02",'1'&x"7B03",'1'&x"7B04",'1'&x"7B05",'1'&x"7B06",'1'&x"7B07",'1'&x"7B08",'1'&x"7B09",'1'&x"7B0A",'1'&x"7B0B",'1'&x"7B0C",'1'&x"7B0D",'1'&x"7B0E",'1'&x"7B0F",
+--'1'&x"7B10",'1'&x"7B11",'1'&x"7B12",'1'&x"7B13",'1'&x"7B14",'1'&x"7B15",'1'&x"7B16",'1'&x"7B17",'1'&x"7B18",'1'&x"7B19",'1'&x"7B1A",'1'&x"7B1B",'1'&x"7B1C",'1'&x"7B1D",'1'&x"7B1E",'1'&x"7B1F",
+--'1'&x"7B20",'1'&x"7B21",'1'&x"7B22",'1'&x"7B23",'1'&x"7B24",'1'&x"7B25",'1'&x"7B26",'1'&x"7B27",'1'&x"7B28",'1'&x"7B29",'1'&x"7B2A",'1'&x"7B2B",'1'&x"7B2C",'1'&x"7B2D",'1'&x"7B2E",'1'&x"7B2F",
+--'1'&x"7B30",'1'&x"7B31",'1'&x"7B32",'1'&x"7B33",'1'&x"7B34",'1'&x"7B35",'1'&x"7B36",'1'&x"7B37",'1'&x"7B38",'1'&x"7B39",'1'&x"7B3A",'1'&x"7B3B",'1'&x"7B3C",'1'&x"7B3D",'1'&x"7B3E",'1'&x"7B3F",
+--'1'&x"7B40",'1'&x"7B41",'1'&x"7B42",'1'&x"7B43",'1'&x"7B44",'1'&x"7B45",'1'&x"7B46",'1'&x"7B47",'1'&x"7B48",'1'&x"7B49",'1'&x"7B4A",'1'&x"7B4B",'1'&x"7B4C",'1'&x"7B4D",'1'&x"7B4E",'1'&x"7B4F",
+--'1'&x"7B50",'1'&x"7B51",'1'&x"7B52",'1'&x"7B53",'1'&x"7B54",'1'&x"7B55",'1'&x"7B56",'1'&x"7B57",'1'&x"7B58",'1'&x"7B59",'1'&x"7B5A",'1'&x"7B5B",'1'&x"7B5C",'1'&x"7B5D",'1'&x"7B5E",'1'&x"7B5F",
+--'1'&x"7B60",'1'&x"7B61",'1'&x"7B62",'1'&x"7B63",'1'&x"7B64",'1'&x"7B65",'1'&x"7B66",'1'&x"7B67",'1'&x"7B68",'1'&x"7B69",'1'&x"7B6A",'1'&x"7B6B",'1'&x"7B6C",'1'&x"7B6D",'1'&x"7B6E",'1'&x"7B6F",
+--'1'&x"7B70",'1'&x"7B71",'1'&x"7B72",'1'&x"7B73",'1'&x"7B74",'1'&x"7B75",'1'&x"7B76",'1'&x"7B77",'1'&x"7B78",'1'&x"7B79",'1'&x"7B7A",'1'&x"7B7B",'1'&x"7B7C",'1'&x"7B7D",'1'&x"7B7E",'1'&x"7B7F",
+--'1'&x"7B80",'1'&x"7B81",'1'&x"7B82",'1'&x"7B83",'1'&x"7B84",'1'&x"7B85",'1'&x"7B86",'1'&x"7B87",'1'&x"7B88",'1'&x"7B89",'1'&x"7B8A",'1'&x"7B8B",'1'&x"7B8C",'1'&x"7B8D",'1'&x"7B8E",'1'&x"7B8F",
+--'1'&x"7B90",'1'&x"7B91",'1'&x"7B92",'1'&x"7B93",'1'&x"7B94",'1'&x"7B95",'1'&x"7B96",'1'&x"7B97",'1'&x"7B98",'1'&x"7B99",'1'&x"7B9A",'1'&x"7B9B",'1'&x"7B9C",'1'&x"7B9D",'1'&x"7B9E",'1'&x"7B9F",
+--'1'&x"7BA0",'1'&x"7BA1",'1'&x"7BA2",'1'&x"7BA3",'1'&x"7BA4",'1'&x"7BA5",'1'&x"7BA6",'1'&x"7BA7",'1'&x"7BA8",'1'&x"7BA9",'1'&x"7BAA",'1'&x"7BAB",'1'&x"7BAC",'1'&x"7BAD",'1'&x"7BAE",'1'&x"7BAF",
+--'1'&x"7BB0",'1'&x"7BB1",'1'&x"7BB2",'1'&x"7BB3",'1'&x"7BB4",'1'&x"7BB5",'1'&x"7BB6",'1'&x"7BB7",'1'&x"7BB8",'1'&x"7BB9",'1'&x"7BBA",'1'&x"7BBB",'1'&x"7BBC",'1'&x"7BBD",'1'&x"7BBE",'1'&x"7BBF",
+--'1'&x"7BC0",'1'&x"7BC1",'1'&x"7BC2",'1'&x"7BC3",'1'&x"7BC4",'1'&x"7BC5",'1'&x"7BC6",'1'&x"7BC7",'1'&x"7BC8",'1'&x"7BC9",'1'&x"7BCA",'1'&x"7BCB",'1'&x"7BCC",'1'&x"7BCD",'1'&x"7BCE",'1'&x"7BCF",
+--'1'&x"7BD0",'1'&x"7BD1",'1'&x"7BD2",'1'&x"7BD3",'1'&x"7BD4",'1'&x"7BD5",'1'&x"7BD6",'1'&x"7BD7",'1'&x"7BD8",'1'&x"7BD9",'1'&x"7BDA",'1'&x"7BDB",'1'&x"7BDC",'1'&x"7BDD",'1'&x"7BDE",'1'&x"7BDF",
+--'1'&x"7BE0",'1'&x"7BE1",'1'&x"7BE2",'1'&x"7BE3",'1'&x"7BE4",'1'&x"7BE5",'1'&x"7BE6",'1'&x"7BE7",'1'&x"7BE8",'1'&x"7BE9",'1'&x"7BEA",'1'&x"7BEB",'1'&x"7BEC",'1'&x"7BED",'1'&x"7BEE",'1'&x"7BEF",
+--'1'&x"7BF0",'1'&x"7BF1",'1'&x"7BF2",'1'&x"7BF3",'1'&x"7BF4",'1'&x"7BF5",'1'&x"7BF6",'1'&x"7BF7",'1'&x"7BF8",'1'&x"7BF9",'1'&x"7BFA",'1'&x"7BFB",'1'&x"7BFC",'1'&x"7BFD",'1'&x"7BFE",'1'&x"7BFF",
+--'1'&x"7C00",'1'&x"7C01",'1'&x"7C02",'1'&x"7C03",'1'&x"7C04",'1'&x"7C05",'1'&x"7C06",'1'&x"7C07",'1'&x"7C08",'1'&x"7C09",'1'&x"7C0A",'1'&x"7C0B",'1'&x"7C0C",'1'&x"7C0D",'1'&x"7C0E",'1'&x"7C0F",
+--'1'&x"7C10",'1'&x"7C11",'1'&x"7C12",'1'&x"7C13",'1'&x"7C14",'1'&x"7C15",'1'&x"7C16",'1'&x"7C17",'1'&x"7C18",'1'&x"7C19",'1'&x"7C1A",'1'&x"7C1B",'1'&x"7C1C",'1'&x"7C1D",'1'&x"7C1E",'1'&x"7C1F",
+--'1'&x"7C20",'1'&x"7C21",'1'&x"7C22",'1'&x"7C23",'1'&x"7C24",'1'&x"7C25",'1'&x"7C26",'1'&x"7C27",'1'&x"7C28",'1'&x"7C29",'1'&x"7C2A",'1'&x"7C2B",'1'&x"7C2C",'1'&x"7C2D",'1'&x"7C2E",'1'&x"7C2F",
+--'1'&x"7C30",'1'&x"7C31",'1'&x"7C32",'1'&x"7C33",'1'&x"7C34",'1'&x"7C35",'1'&x"7C36",'1'&x"7C37",'1'&x"7C38",'1'&x"7C39",'1'&x"7C3A",'1'&x"7C3B",'1'&x"7C3C",'1'&x"7C3D",'1'&x"7C3E",'1'&x"7C3F",
+--'1'&x"7C40",'1'&x"7C41",'1'&x"7C42",'1'&x"7C43",'1'&x"7C44",'1'&x"7C45",'1'&x"7C46",'1'&x"7C47",'1'&x"7C48",'1'&x"7C49",'1'&x"7C4A",'1'&x"7C4B",'1'&x"7C4C",'1'&x"7C4D",'1'&x"7C4E",'1'&x"7C4F",
+--'1'&x"7C50",'1'&x"7C51",'1'&x"7C52",'1'&x"7C53",'1'&x"7C54",'1'&x"7C55",'1'&x"7C56",'1'&x"7C57",'1'&x"7C58",'1'&x"7C59",'1'&x"7C5A",'1'&x"7C5B",'1'&x"7C5C",'1'&x"7C5D",'1'&x"7C5E",'1'&x"7C5F",
+--'1'&x"7C60",'1'&x"7C61",'1'&x"7C62",'1'&x"7C63",'1'&x"7C64",'1'&x"7C65",'1'&x"7C66",'1'&x"7C67",'1'&x"7C68",'1'&x"7C69",'1'&x"7C6A",'1'&x"7C6B",'1'&x"7C6C",'1'&x"7C6D",'1'&x"7C6E",'1'&x"7C6F",
+--'1'&x"7C70",'1'&x"7C71",'1'&x"7C72",'1'&x"7C73",'1'&x"7C74",'1'&x"7C75",'1'&x"7C76",'1'&x"7C77",'1'&x"7C78",'1'&x"7C79",'1'&x"7C7A",'1'&x"7C7B",'1'&x"7C7C",'1'&x"7C7D",'1'&x"7C7E",'1'&x"7C7F",
+--'1'&x"7C80",'1'&x"7C81",'1'&x"7C82",'1'&x"7C83",'1'&x"7C84",'1'&x"7C85",'1'&x"7C86",'1'&x"7C87",'1'&x"7C88",'1'&x"7C89",'1'&x"7C8A",'1'&x"7C8B",'1'&x"7C8C",'1'&x"7C8D",'1'&x"7C8E",'1'&x"7C8F",
+--'1'&x"7C90",'1'&x"7C91",'1'&x"7C92",'1'&x"7C93",'1'&x"7C94",'1'&x"7C95",'1'&x"7C96",'1'&x"7C97",'1'&x"7C98",'1'&x"7C99",'1'&x"7C9A",'1'&x"7C9B",'1'&x"7C9C",'1'&x"7C9D",'1'&x"7C9E",'1'&x"7C9F",
+--'1'&x"7CA0",'1'&x"7CA1",'1'&x"7CA2",'1'&x"7CA3",'1'&x"7CA4",'1'&x"7CA5",'1'&x"7CA6",'1'&x"7CA7",'1'&x"7CA8",'1'&x"7CA9",'1'&x"7CAA",'1'&x"7CAB",'1'&x"7CAC",'1'&x"7CAD",'1'&x"7CAE",'1'&x"7CAF",
+--'1'&x"7CB0",'1'&x"7CB1",'1'&x"7CB2",'1'&x"7CB3",'1'&x"7CB4",'1'&x"7CB5",'1'&x"7CB6",'1'&x"7CB7",'1'&x"7CB8",'1'&x"7CB9",'1'&x"7CBA",'1'&x"7CBB",'1'&x"7CBC",'1'&x"7CBD",'1'&x"7CBE",'1'&x"7CBF",
+--'1'&x"7CC0",'1'&x"7CC1",'1'&x"7CC2",'1'&x"7CC3",'1'&x"7CC4",'1'&x"7CC5",'1'&x"7CC6",'1'&x"7CC7",'1'&x"7CC8",'1'&x"7CC9",'1'&x"7CCA",'1'&x"7CCB",'1'&x"7CCC",'1'&x"7CCD",'1'&x"7CCE",'1'&x"7CCF",
+--'1'&x"7CD0",'1'&x"7CD1",'1'&x"7CD2",'1'&x"7CD3",'1'&x"7CD4",'1'&x"7CD5",'1'&x"7CD6",'1'&x"7CD7",'1'&x"7CD8",'1'&x"7CD9",'1'&x"7CDA",'1'&x"7CDB",'1'&x"7CDC",'1'&x"7CDD",'1'&x"7CDE",'1'&x"7CDF",
+--'1'&x"7CE0",'1'&x"7CE1",'1'&x"7CE2",'1'&x"7CE3",'1'&x"7CE4",'1'&x"7CE5",'1'&x"7CE6",'1'&x"7CE7",'1'&x"7CE8",'1'&x"7CE9",'1'&x"7CEA",'1'&x"7CEB",'1'&x"7CEC",'1'&x"7CED",'1'&x"7CEE",'1'&x"7CEF",
+--'1'&x"7CF0",'1'&x"7CF1",'1'&x"7CF2",'1'&x"7CF3",'1'&x"7CF4",'1'&x"7CF5",'1'&x"7CF6",'1'&x"7CF7",'1'&x"7CF8",'1'&x"7CF9",'1'&x"7CFA",'1'&x"7CFB",'1'&x"7CFC",'1'&x"7CFD",'1'&x"7CFE",'1'&x"7CFF",
+--'1'&x"7D00",'1'&x"7D01",'1'&x"7D02",'1'&x"7D03",'1'&x"7D04",'1'&x"7D05",'1'&x"7D06",'1'&x"7D07",'1'&x"7D08",'1'&x"7D09",'1'&x"7D0A",'1'&x"7D0B",'1'&x"7D0C",'1'&x"7D0D",'1'&x"7D0E",'1'&x"7D0F",
+--'1'&x"7D10",'1'&x"7D11",'1'&x"7D12",'1'&x"7D13",'1'&x"7D14",'1'&x"7D15",'1'&x"7D16",'1'&x"7D17",'1'&x"7D18",'1'&x"7D19",'1'&x"7D1A",'1'&x"7D1B",'1'&x"7D1C",'1'&x"7D1D",'1'&x"7D1E",'1'&x"7D1F",
+--'1'&x"7D20",'1'&x"7D21",'1'&x"7D22",'1'&x"7D23",'1'&x"7D24",'1'&x"7D25",'1'&x"7D26",'1'&x"7D27",'1'&x"7D28",'1'&x"7D29",'1'&x"7D2A",'1'&x"7D2B",'1'&x"7D2C",'1'&x"7D2D",'1'&x"7D2E",'1'&x"7D2F",
+--'1'&x"7D30",'1'&x"7D31",'1'&x"7D32",'1'&x"7D33",'1'&x"7D34",'1'&x"7D35",'1'&x"7D36",'1'&x"7D37",'1'&x"7D38",'1'&x"7D39",'1'&x"7D3A",'1'&x"7D3B",'1'&x"7D3C",'1'&x"7D3D",'1'&x"7D3E",'1'&x"7D3F",
+--'1'&x"7D40",'1'&x"7D41",'1'&x"7D42",'1'&x"7D43",'1'&x"7D44",'1'&x"7D45",'1'&x"7D46",'1'&x"7D47",'1'&x"7D48",'1'&x"7D49",'1'&x"7D4A",'1'&x"7D4B",'1'&x"7D4C",'1'&x"7D4D",'1'&x"7D4E",'1'&x"7D4F",
+--'1'&x"7D50",'1'&x"7D51",'1'&x"7D52",'1'&x"7D53",'1'&x"7D54",'1'&x"7D55",'1'&x"7D56",'1'&x"7D57",'1'&x"7D58",'1'&x"7D59",'1'&x"7D5A",'1'&x"7D5B",'1'&x"7D5C",'1'&x"7D5D",'1'&x"7D5E",'1'&x"7D5F",
+--'1'&x"7D60",'1'&x"7D61",'1'&x"7D62",'1'&x"7D63",'1'&x"7D64",'1'&x"7D65",'1'&x"7D66",'1'&x"7D67",'1'&x"7D68",'1'&x"7D69",'1'&x"7D6A",'1'&x"7D6B",'1'&x"7D6C",'1'&x"7D6D",'1'&x"7D6E",'1'&x"7D6F",
+--'1'&x"7D70",'1'&x"7D71",'1'&x"7D72",'1'&x"7D73",'1'&x"7D74",'1'&x"7D75",'1'&x"7D76",'1'&x"7D77",'1'&x"7D78",'1'&x"7D79",'1'&x"7D7A",'1'&x"7D7B",'1'&x"7D7C",'1'&x"7D7D",'1'&x"7D7E",'1'&x"7D7F",
+--'1'&x"7D80",'1'&x"7D81",'1'&x"7D82",'1'&x"7D83",'1'&x"7D84",'1'&x"7D85",'1'&x"7D86",'1'&x"7D87",'1'&x"7D88",'1'&x"7D89",'1'&x"7D8A",'1'&x"7D8B",'1'&x"7D8C",'1'&x"7D8D",'1'&x"7D8E",'1'&x"7D8F",
+--'1'&x"7D90",'1'&x"7D91",'1'&x"7D92",'1'&x"7D93",'1'&x"7D94",'1'&x"7D95",'1'&x"7D96",'1'&x"7D97",'1'&x"7D98",'1'&x"7D99",'1'&x"7D9A",'1'&x"7D9B",'1'&x"7D9C",'1'&x"7D9D",'1'&x"7D9E",'1'&x"7D9F",
+--'1'&x"7DA0",'1'&x"7DA1",'1'&x"7DA2",'1'&x"7DA3",'1'&x"7DA4",'1'&x"7DA5",'1'&x"7DA6",'1'&x"7DA7",'1'&x"7DA8",'1'&x"7DA9",'1'&x"7DAA",'1'&x"7DAB",'1'&x"7DAC",'1'&x"7DAD",'1'&x"7DAE",'1'&x"7DAF",
+--'1'&x"7DB0",'1'&x"7DB1",'1'&x"7DB2",'1'&x"7DB3",'1'&x"7DB4",'1'&x"7DB5",'1'&x"7DB6",'1'&x"7DB7",'1'&x"7DB8",'1'&x"7DB9",'1'&x"7DBA",'1'&x"7DBB",'1'&x"7DBC",'1'&x"7DBD",'1'&x"7DBE",'1'&x"7DBF",
+--'1'&x"7DC0",'1'&x"7DC1",'1'&x"7DC2",'1'&x"7DC3",'1'&x"7DC4",'1'&x"7DC5",'1'&x"7DC6",'1'&x"7DC7",'1'&x"7DC8",'1'&x"7DC9",'1'&x"7DCA",'1'&x"7DCB",'1'&x"7DCC",'1'&x"7DCD",'1'&x"7DCE",'1'&x"7DCF",
+--'1'&x"7DD0",'1'&x"7DD1",'1'&x"7DD2",'1'&x"7DD3",'1'&x"7DD4",'1'&x"7DD5",'1'&x"7DD6",'1'&x"7DD7",'1'&x"7DD8",'1'&x"7DD9",'1'&x"7DDA",'1'&x"7DDB",'1'&x"7DDC",'1'&x"7DDD",'1'&x"7DDE",'1'&x"7DDF",
+--'1'&x"7DE0",'1'&x"7DE1",'1'&x"7DE2",'1'&x"7DE3",'1'&x"7DE4",'1'&x"7DE5",'1'&x"7DE6",'1'&x"7DE7",'1'&x"7DE8",'1'&x"7DE9",'1'&x"7DEA",'1'&x"7DEB",'1'&x"7DEC",'1'&x"7DED",'1'&x"7DEE",'1'&x"7DEF",
+--'1'&x"7DF0",'1'&x"7DF1",'1'&x"7DF2",'1'&x"7DF3",'1'&x"7DF4",'1'&x"7DF5",'1'&x"7DF6",'1'&x"7DF7",'1'&x"7DF8",'1'&x"7DF9",'1'&x"7DFA",'1'&x"7DFB",'1'&x"7DFC",'1'&x"7DFD",'1'&x"7DFE",'1'&x"7DFF",
+--'1'&x"7E00",'1'&x"7E01",'1'&x"7E02",'1'&x"7E03",'1'&x"7E04",'1'&x"7E05",'1'&x"7E06",'1'&x"7E07",'1'&x"7E08",'1'&x"7E09",'1'&x"7E0A",'1'&x"7E0B",'1'&x"7E0C",'1'&x"7E0D",'1'&x"7E0E",'1'&x"7E0F",
+--'1'&x"7E10",'1'&x"7E11",'1'&x"7E12",'1'&x"7E13",'1'&x"7E14",'1'&x"7E15",'1'&x"7E16",'1'&x"7E17",'1'&x"7E18",'1'&x"7E19",'1'&x"7E1A",'1'&x"7E1B",'1'&x"7E1C",'1'&x"7E1D",'1'&x"7E1E",'1'&x"7E1F",
+--'1'&x"7E20",'1'&x"7E21",'1'&x"7E22",'1'&x"7E23",'1'&x"7E24",'1'&x"7E25",'1'&x"7E26",'1'&x"7E27",'1'&x"7E28",'1'&x"7E29",'1'&x"7E2A",'1'&x"7E2B",'1'&x"7E2C",'1'&x"7E2D",'1'&x"7E2E",'1'&x"7E2F",
+--'1'&x"7E30",'1'&x"7E31",'1'&x"7E32",'1'&x"7E33",'1'&x"7E34",'1'&x"7E35",'1'&x"7E36",'1'&x"7E37",'1'&x"7E38",'1'&x"7E39",'1'&x"7E3A",'1'&x"7E3B",'1'&x"7E3C",'1'&x"7E3D",'1'&x"7E3E",'1'&x"7E3F",
+--'1'&x"7E40",'1'&x"7E41",'1'&x"7E42",'1'&x"7E43",'1'&x"7E44",'1'&x"7E45",'1'&x"7E46",'1'&x"7E47",'1'&x"7E48",'1'&x"7E49",'1'&x"7E4A",'1'&x"7E4B",'1'&x"7E4C",'1'&x"7E4D",'1'&x"7E4E",'1'&x"7E4F",
+--'1'&x"7E50",'1'&x"7E51",'1'&x"7E52",'1'&x"7E53",'1'&x"7E54",'1'&x"7E55",'1'&x"7E56",'1'&x"7E57",'1'&x"7E58",'1'&x"7E59",'1'&x"7E5A",'1'&x"7E5B",'1'&x"7E5C",'1'&x"7E5D",'1'&x"7E5E",'1'&x"7E5F",
+--'1'&x"7E60",'1'&x"7E61",'1'&x"7E62",'1'&x"7E63",'1'&x"7E64",'1'&x"7E65",'1'&x"7E66",'1'&x"7E67",'1'&x"7E68",'1'&x"7E69",'1'&x"7E6A",'1'&x"7E6B",'1'&x"7E6C",'1'&x"7E6D",'1'&x"7E6E",'1'&x"7E6F",
+--'1'&x"7E70",'1'&x"7E71",'1'&x"7E72",'1'&x"7E73",'1'&x"7E74",'1'&x"7E75",'1'&x"7E76",'1'&x"7E77",'1'&x"7E78",'1'&x"7E79",'1'&x"7E7A",'1'&x"7E7B",'1'&x"7E7C",'1'&x"7E7D",'1'&x"7E7E",'1'&x"7E7F",
+--'1'&x"7E80",'1'&x"7E81",'1'&x"7E82",'1'&x"7E83",'1'&x"7E84",'1'&x"7E85",'1'&x"7E86",'1'&x"7E87",'1'&x"7E88",'1'&x"7E89",'1'&x"7E8A",'1'&x"7E8B",'1'&x"7E8C",'1'&x"7E8D",'1'&x"7E8E",'1'&x"7E8F",
+--'1'&x"7E90",'1'&x"7E91",'1'&x"7E92",'1'&x"7E93",'1'&x"7E94",'1'&x"7E95",'1'&x"7E96",'1'&x"7E97",'1'&x"7E98",'1'&x"7E99",'1'&x"7E9A",'1'&x"7E9B",'1'&x"7E9C",'1'&x"7E9D",'1'&x"7E9E",'1'&x"7E9F",
+--'1'&x"7EA0",'1'&x"7EA1",'1'&x"7EA2",'1'&x"7EA3",'1'&x"7EA4",'1'&x"7EA5",'1'&x"7EA6",'1'&x"7EA7",'1'&x"7EA8",'1'&x"7EA9",'1'&x"7EAA",'1'&x"7EAB",'1'&x"7EAC",'1'&x"7EAD",'1'&x"7EAE",'1'&x"7EAF",
+--'1'&x"7EB0",'1'&x"7EB1",'1'&x"7EB2",'1'&x"7EB3",'1'&x"7EB4",'1'&x"7EB5",'1'&x"7EB6",'1'&x"7EB7",'1'&x"7EB8",'1'&x"7EB9",'1'&x"7EBA",'1'&x"7EBB",'1'&x"7EBC",'1'&x"7EBD",'1'&x"7EBE",'1'&x"7EBF",
+--'1'&x"7EC0",'1'&x"7EC1",'1'&x"7EC2",'1'&x"7EC3",'1'&x"7EC4",'1'&x"7EC5",'1'&x"7EC6",'1'&x"7EC7",'1'&x"7EC8",'1'&x"7EC9",'1'&x"7ECA",'1'&x"7ECB",'1'&x"7ECC",'1'&x"7ECD",'1'&x"7ECE",'1'&x"7ECF",
+--'1'&x"7ED0",'1'&x"7ED1",'1'&x"7ED2",'1'&x"7ED3",'1'&x"7ED4",'1'&x"7ED5",'1'&x"7ED6",'1'&x"7ED7",'1'&x"7ED8",'1'&x"7ED9",'1'&x"7EDA",'1'&x"7EDB",'1'&x"7EDC",'1'&x"7EDD",'1'&x"7EDE",'1'&x"7EDF",
+--'1'&x"7EE0",'1'&x"7EE1",'1'&x"7EE2",'1'&x"7EE3",'1'&x"7EE4",'1'&x"7EE5",'1'&x"7EE6",'1'&x"7EE7",'1'&x"7EE8",'1'&x"7EE9",'1'&x"7EEA",'1'&x"7EEB",'1'&x"7EEC",'1'&x"7EED",'1'&x"7EEE",'1'&x"7EEF",
+--'1'&x"7EF0",'1'&x"7EF1",'1'&x"7EF2",'1'&x"7EF3",'1'&x"7EF4",'1'&x"7EF5",'1'&x"7EF6",'1'&x"7EF7",'1'&x"7EF8",'1'&x"7EF9",'1'&x"7EFA",'1'&x"7EFB",'1'&x"7EFC",'1'&x"7EFD",'1'&x"7EFE",'1'&x"7EFF",
+--'1'&x"7F00",'1'&x"7F01",'1'&x"7F02",'1'&x"7F03",'1'&x"7F04",'1'&x"7F05",'1'&x"7F06",'1'&x"7F07",'1'&x"7F08",'1'&x"7F09",'1'&x"7F0A",'1'&x"7F0B",'1'&x"7F0C",'1'&x"7F0D",'1'&x"7F0E",'1'&x"7F0F",
+--'1'&x"7F10",'1'&x"7F11",'1'&x"7F12",'1'&x"7F13",'1'&x"7F14",'1'&x"7F15",'1'&x"7F16",'1'&x"7F17",'1'&x"7F18",'1'&x"7F19",'1'&x"7F1A",'1'&x"7F1B",'1'&x"7F1C",'1'&x"7F1D",'1'&x"7F1E",'1'&x"7F1F",
+--'1'&x"7F20",'1'&x"7F21",'1'&x"7F22",'1'&x"7F23",'1'&x"7F24",'1'&x"7F25",'1'&x"7F26",'1'&x"7F27",'1'&x"7F28",'1'&x"7F29",'1'&x"7F2A",'1'&x"7F2B",'1'&x"7F2C",'1'&x"7F2D",'1'&x"7F2E",'1'&x"7F2F",
+--'1'&x"7F30",'1'&x"7F31",'1'&x"7F32",'1'&x"7F33",'1'&x"7F34",'1'&x"7F35",'1'&x"7F36",'1'&x"7F37",'1'&x"7F38",'1'&x"7F39",'1'&x"7F3A",'1'&x"7F3B",'1'&x"7F3C",'1'&x"7F3D",'1'&x"7F3E",'1'&x"7F3F",
+--'1'&x"7F40",'1'&x"7F41",'1'&x"7F42",'1'&x"7F43",'1'&x"7F44",'1'&x"7F45",'1'&x"7F46",'1'&x"7F47",'1'&x"7F48",'1'&x"7F49",'1'&x"7F4A",'1'&x"7F4B",'1'&x"7F4C",'1'&x"7F4D",'1'&x"7F4E",'1'&x"7F4F",
+--'1'&x"7F50",'1'&x"7F51",'1'&x"7F52",'1'&x"7F53",'1'&x"7F54",'1'&x"7F55",'1'&x"7F56",'1'&x"7F57",'1'&x"7F58",'1'&x"7F59",'1'&x"7F5A",'1'&x"7F5B",'1'&x"7F5C",'1'&x"7F5D",'1'&x"7F5E",'1'&x"7F5F",
+--'1'&x"7F60",'1'&x"7F61",'1'&x"7F62",'1'&x"7F63",'1'&x"7F64",'1'&x"7F65",'1'&x"7F66",'1'&x"7F67",'1'&x"7F68",'1'&x"7F69",'1'&x"7F6A",'1'&x"7F6B",'1'&x"7F6C",'1'&x"7F6D",'1'&x"7F6E",'1'&x"7F6F",
+--'1'&x"7F70",'1'&x"7F71",'1'&x"7F72",'1'&x"7F73",'1'&x"7F74",'1'&x"7F75",'1'&x"7F76",'1'&x"7F77",'1'&x"7F78",'1'&x"7F79",'1'&x"7F7A",'1'&x"7F7B",'1'&x"7F7C",'1'&x"7F7D",'1'&x"7F7E",'1'&x"7F7F",
+--'1'&x"7F80",'1'&x"7F81",'1'&x"7F82",'1'&x"7F83",'1'&x"7F84",'1'&x"7F85",'1'&x"7F86",'1'&x"7F87",'1'&x"7F88",'1'&x"7F89",'1'&x"7F8A",'1'&x"7F8B",'1'&x"7F8C",'1'&x"7F8D",'1'&x"7F8E",'1'&x"7F8F",
+--'1'&x"7F90",'1'&x"7F91",'1'&x"7F92",'1'&x"7F93",'1'&x"7F94",'1'&x"7F95",'1'&x"7F96",'1'&x"7F97",'1'&x"7F98",'1'&x"7F99",'1'&x"7F9A",'1'&x"7F9B",'1'&x"7F9C",'1'&x"7F9D",'1'&x"7F9E",'1'&x"7F9F",
+--'1'&x"7FA0",'1'&x"7FA1",'1'&x"7FA2",'1'&x"7FA3",'1'&x"7FA4",'1'&x"7FA5",'1'&x"7FA6",'1'&x"7FA7",'1'&x"7FA8",'1'&x"7FA9",'1'&x"7FAA",'1'&x"7FAB",'1'&x"7FAC",'1'&x"7FAD",'1'&x"7FAE",'1'&x"7FAF",
+--'1'&x"7FB0",'1'&x"7FB1",'1'&x"7FB2",'1'&x"7FB3",'1'&x"7FB4",'1'&x"7FB5",'1'&x"7FB6",'1'&x"7FB7",'1'&x"7FB8",'1'&x"7FB9",'1'&x"7FBA",'1'&x"7FBB",'1'&x"7FBC",'1'&x"7FBD",'1'&x"7FBE",'1'&x"7FBF",
+--'1'&x"7FC0",'1'&x"7FC1",'1'&x"7FC2",'1'&x"7FC3",'1'&x"7FC4",'1'&x"7FC5",'1'&x"7FC6",'1'&x"7FC7",'1'&x"7FC8",'1'&x"7FC9",'1'&x"7FCA",'1'&x"7FCB",'1'&x"7FCC",'1'&x"7FCD",'1'&x"7FCE",'1'&x"7FCF",
+--'1'&x"7FD0",'1'&x"7FD1",'1'&x"7FD2",'1'&x"7FD3",'1'&x"7FD4",'1'&x"7FD5",'1'&x"7FD6",'1'&x"7FD7",'1'&x"7FD8",'1'&x"7FD9",'1'&x"7FDA",'1'&x"7FDB",'1'&x"7FDC",'1'&x"7FDD",'1'&x"7FDE",'1'&x"7FDF",
+--'1'&x"7FE0",'1'&x"7FE1",'1'&x"7FE2",'1'&x"7FE3",'1'&x"7FE4",'1'&x"7FE5",'1'&x"7FE6",'1'&x"7FE7",'1'&x"7FE8",'1'&x"7FE9",'1'&x"7FEA",'1'&x"7FEB",'1'&x"7FEC",'1'&x"7FED",'1'&x"7FEE",'1'&x"7FEF",
+--'1'&x"7FF0",'1'&x"7FF1",'1'&x"7FF2",'1'&x"7FF3",'1'&x"7FF4",'1'&x"7FF5",'1'&x"7FF6",'1'&x"7FF7",'1'&x"7FF8",'1'&x"7FF9",'1'&x"7FFA",'1'&x"7FFB",'1'&x"7FFC",'1'&x"7FFD",'1'&x"7FFE",'1'&x"7FFF",
+--'1'&x"8000",'1'&x"8001",'1'&x"8002",'1'&x"8003",'1'&x"8004",'1'&x"8005",'1'&x"8006",'1'&x"8007",'1'&x"8008",'1'&x"8009",'1'&x"800A",'1'&x"800B",'1'&x"800C",'1'&x"800D",'1'&x"800E",'1'&x"800F",
+--'1'&x"8010",'1'&x"8011",'1'&x"8012",'1'&x"8013",'1'&x"8014",'1'&x"8015",'1'&x"8016",'1'&x"8017",'1'&x"8018",'1'&x"8019",'1'&x"801A",'1'&x"801B",'1'&x"801C",'1'&x"801D",'1'&x"801E",'1'&x"801F",
+--'1'&x"8020",'1'&x"8021",'1'&x"8022",'1'&x"8023",'1'&x"8024",'1'&x"8025",'1'&x"8026",'1'&x"8027",'1'&x"8028",'1'&x"8029",'1'&x"802A",'1'&x"802B",'1'&x"802C",'1'&x"802D",'1'&x"802E",'1'&x"802F",
+--'1'&x"8030",'1'&x"8031",'1'&x"8032",'1'&x"8033",'1'&x"8034",'1'&x"8035",'1'&x"8036",'1'&x"8037",'1'&x"8038",'1'&x"8039",'1'&x"803A",'1'&x"803B",'1'&x"803C",'1'&x"803D",'1'&x"803E",'1'&x"803F",
+--'1'&x"8040",'1'&x"8041",'1'&x"8042",'1'&x"8043",'1'&x"8044",'1'&x"8045",'1'&x"8046",'1'&x"8047",'1'&x"8048",'1'&x"8049",'1'&x"804A",'1'&x"804B",'1'&x"804C",'1'&x"804D",'1'&x"804E",'1'&x"804F",
+--'1'&x"8050",'1'&x"8051",'1'&x"8052",'1'&x"8053",'1'&x"8054",'1'&x"8055",'1'&x"8056",'1'&x"8057",'1'&x"8058",'1'&x"8059",'1'&x"805A",'1'&x"805B",'1'&x"805C",'1'&x"805D",'1'&x"805E",'1'&x"805F",
+--'1'&x"8060",'1'&x"8061",'1'&x"8062",'1'&x"8063",'1'&x"8064",'1'&x"8065",'1'&x"8066",'1'&x"8067",'1'&x"8068",'1'&x"8069",'1'&x"806A",'1'&x"806B",'1'&x"806C",'1'&x"806D",'1'&x"806E",'1'&x"806F",
+--'1'&x"8070",'1'&x"8071",'1'&x"8072",'1'&x"8073",'1'&x"8074",'1'&x"8075",'1'&x"8076",'1'&x"8077",'1'&x"8078",'1'&x"8079",'1'&x"807A",'1'&x"807B",'1'&x"807C",'1'&x"807D",'1'&x"807E",'1'&x"807F",
+--'1'&x"8080",'1'&x"8081",'1'&x"8082",'1'&x"8083",'1'&x"8084",'1'&x"8085",'1'&x"8086",'1'&x"8087",'1'&x"8088",'1'&x"8089",'1'&x"808A",'1'&x"808B",'1'&x"808C",'1'&x"808D",'1'&x"808E",'1'&x"808F",
+--'1'&x"8090",'1'&x"8091",'1'&x"8092",'1'&x"8093",'1'&x"8094",'1'&x"8095",'1'&x"8096",'1'&x"8097",'1'&x"8098",'1'&x"8099",'1'&x"809A",'1'&x"809B",'1'&x"809C",'1'&x"809D",'1'&x"809E",'1'&x"809F",
+--'1'&x"80A0",'1'&x"80A1",'1'&x"80A2",'1'&x"80A3",'1'&x"80A4",'1'&x"80A5",'1'&x"80A6",'1'&x"80A7",'1'&x"80A8",'1'&x"80A9",'1'&x"80AA",'1'&x"80AB",'1'&x"80AC",'1'&x"80AD",'1'&x"80AE",'1'&x"80AF",
+--'1'&x"80B0",'1'&x"80B1",'1'&x"80B2",'1'&x"80B3",'1'&x"80B4",'1'&x"80B5",'1'&x"80B6",'1'&x"80B7",'1'&x"80B8",'1'&x"80B9",'1'&x"80BA",'1'&x"80BB",'1'&x"80BC",'1'&x"80BD",'1'&x"80BE",'1'&x"80BF",
+--'1'&x"80C0",'1'&x"80C1",'1'&x"80C2",'1'&x"80C3",'1'&x"80C4",'1'&x"80C5",'1'&x"80C6",'1'&x"80C7",'1'&x"80C8",'1'&x"80C9",'1'&x"80CA",'1'&x"80CB",'1'&x"80CC",'1'&x"80CD",'1'&x"80CE",'1'&x"80CF",
+--'1'&x"80D0",'1'&x"80D1",'1'&x"80D2",'1'&x"80D3",'1'&x"80D4",'1'&x"80D5",'1'&x"80D6",'1'&x"80D7",'1'&x"80D8",'1'&x"80D9",'1'&x"80DA",'1'&x"80DB",'1'&x"80DC",'1'&x"80DD",'1'&x"80DE",'1'&x"80DF",
+--'1'&x"80E0",'1'&x"80E1",'1'&x"80E2",'1'&x"80E3",'1'&x"80E4",'1'&x"80E5",'1'&x"80E6",'1'&x"80E7",'1'&x"80E8",'1'&x"80E9",'1'&x"80EA",'1'&x"80EB",'1'&x"80EC",'1'&x"80ED",'1'&x"80EE",'1'&x"80EF",
+--'1'&x"80F0",'1'&x"80F1",'1'&x"80F2",'1'&x"80F3",'1'&x"80F4",'1'&x"80F5",'1'&x"80F6",'1'&x"80F7",'1'&x"80F8",'1'&x"80F9",'1'&x"80FA",'1'&x"80FB",'1'&x"80FC",'1'&x"80FD",'1'&x"80FE",'1'&x"80FF",
+--'1'&x"8100",'1'&x"8101",'1'&x"8102",'1'&x"8103",'1'&x"8104",'1'&x"8105",'1'&x"8106",'1'&x"8107",'1'&x"8108",'1'&x"8109",'1'&x"810A",'1'&x"810B",'1'&x"810C",'1'&x"810D",'1'&x"810E",'1'&x"810F",
+--'1'&x"8110",'1'&x"8111",'1'&x"8112",'1'&x"8113",'1'&x"8114",'1'&x"8115",'1'&x"8116",'1'&x"8117",'1'&x"8118",'1'&x"8119",'1'&x"811A",'1'&x"811B",'1'&x"811C",'1'&x"811D",'1'&x"811E",'1'&x"811F",
+--'1'&x"8120",'1'&x"8121",'1'&x"8122",'1'&x"8123",'1'&x"8124",'1'&x"8125",'1'&x"8126",'1'&x"8127",'1'&x"8128",'1'&x"8129",'1'&x"812A",'1'&x"812B",'1'&x"812C",'1'&x"812D",'1'&x"812E",'1'&x"812F",
+--'1'&x"8130",'1'&x"8131",'1'&x"8132",'1'&x"8133",'1'&x"8134",'1'&x"8135",'1'&x"8136",'1'&x"8137",'1'&x"8138",'1'&x"8139",'1'&x"813A",'1'&x"813B",'1'&x"813C",'1'&x"813D",'1'&x"813E",'1'&x"813F",
+--'1'&x"8140",'1'&x"8141",'1'&x"8142",'1'&x"8143",'1'&x"8144",'1'&x"8145",'1'&x"8146",'1'&x"8147",'1'&x"8148",'1'&x"8149",'1'&x"814A",'1'&x"814B",'1'&x"814C",'1'&x"814D",'1'&x"814E",'1'&x"814F",
+--'1'&x"8150",'1'&x"8151",'1'&x"8152",'1'&x"8153",'1'&x"8154",'1'&x"8155",'1'&x"8156",'1'&x"8157",'1'&x"8158",'1'&x"8159",'1'&x"815A",'1'&x"815B",'1'&x"815C",'1'&x"815D",'1'&x"815E",'1'&x"815F",
+--'1'&x"8160",'1'&x"8161",'1'&x"8162",'1'&x"8163",'1'&x"8164",'1'&x"8165",'1'&x"8166",'1'&x"8167",'1'&x"8168",'1'&x"8169",'1'&x"816A",'1'&x"816B",'1'&x"816C",'1'&x"816D",'1'&x"816E",'1'&x"816F",
+--'1'&x"8170",'1'&x"8171",'1'&x"8172",'1'&x"8173",'1'&x"8174",'1'&x"8175",'1'&x"8176",'1'&x"8177",'1'&x"8178",'1'&x"8179",'1'&x"817A",'1'&x"817B",'1'&x"817C",'1'&x"817D",'1'&x"817E",'1'&x"817F",
+--'1'&x"8180",'1'&x"8181",'1'&x"8182",'1'&x"8183",'1'&x"8184",'1'&x"8185",'1'&x"8186",'1'&x"8187",'1'&x"8188",'1'&x"8189",'1'&x"818A",'1'&x"818B",'1'&x"818C",'1'&x"818D",'1'&x"818E",'1'&x"818F",
+--'1'&x"8190",'1'&x"8191",'1'&x"8192",'1'&x"8193",'1'&x"8194",'1'&x"8195",'1'&x"8196",'1'&x"8197",'1'&x"8198",'1'&x"8199",'1'&x"819A",'1'&x"819B",'1'&x"819C",'1'&x"819D",'1'&x"819E",'1'&x"819F",
+--'1'&x"81A0",'1'&x"81A1",'1'&x"81A2",'1'&x"81A3",'1'&x"81A4",'1'&x"81A5",'1'&x"81A6",'1'&x"81A7",'1'&x"81A8",'1'&x"81A9",'1'&x"81AA",'1'&x"81AB",'1'&x"81AC",'1'&x"81AD",'1'&x"81AE",'1'&x"81AF",
+--'1'&x"81B0",'1'&x"81B1",'1'&x"81B2",'1'&x"81B3",'1'&x"81B4",'1'&x"81B5",'1'&x"81B6",'1'&x"81B7",'1'&x"81B8",'1'&x"81B9",'1'&x"81BA",'1'&x"81BB",'1'&x"81BC",'1'&x"81BD",'1'&x"81BE",'1'&x"81BF",
+--'1'&x"81C0",'1'&x"81C1",'1'&x"81C2",'1'&x"81C3",'1'&x"81C4",'1'&x"81C5",'1'&x"81C6",'1'&x"81C7",'1'&x"81C8",'1'&x"81C9",'1'&x"81CA",'1'&x"81CB",'1'&x"81CC",'1'&x"81CD",'1'&x"81CE",'1'&x"81CF",
+--'1'&x"81D0",'1'&x"81D1",'1'&x"81D2",'1'&x"81D3",'1'&x"81D4",'1'&x"81D5",'1'&x"81D6",'1'&x"81D7",'1'&x"81D8",'1'&x"81D9",'1'&x"81DA",'1'&x"81DB",'1'&x"81DC",'1'&x"81DD",'1'&x"81DE",'1'&x"81DF",
+--'1'&x"81E0",'1'&x"81E1",'1'&x"81E2",'1'&x"81E3",'1'&x"81E4",'1'&x"81E5",'1'&x"81E6",'1'&x"81E7",'1'&x"81E8",'1'&x"81E9",'1'&x"81EA",'1'&x"81EB",'1'&x"81EC",'1'&x"81ED",'1'&x"81EE",'1'&x"81EF",
+--'1'&x"81F0",'1'&x"81F1",'1'&x"81F2",'1'&x"81F3",'1'&x"81F4",'1'&x"81F5",'1'&x"81F6",'1'&x"81F7",'1'&x"81F8",'1'&x"81F9",'1'&x"81FA",'1'&x"81FB",'1'&x"81FC",'1'&x"81FD",'1'&x"81FE",'1'&x"81FF",
+--'1'&x"8200",'1'&x"8201",'1'&x"8202",'1'&x"8203",'1'&x"8204",'1'&x"8205",'1'&x"8206",'1'&x"8207",'1'&x"8208",'1'&x"8209",'1'&x"820A",'1'&x"820B",'1'&x"820C",'1'&x"820D",'1'&x"820E",'1'&x"820F",
+--'1'&x"8210",'1'&x"8211",'1'&x"8212",'1'&x"8213",'1'&x"8214",'1'&x"8215",'1'&x"8216",'1'&x"8217",'1'&x"8218",'1'&x"8219",'1'&x"821A",'1'&x"821B",'1'&x"821C",'1'&x"821D",'1'&x"821E",'1'&x"821F",
+--'1'&x"8220",'1'&x"8221",'1'&x"8222",'1'&x"8223",'1'&x"8224",'1'&x"8225",'1'&x"8226",'1'&x"8227",'1'&x"8228",'1'&x"8229",'1'&x"822A",'1'&x"822B",'1'&x"822C",'1'&x"822D",'1'&x"822E",'1'&x"822F",
+--'1'&x"8230",'1'&x"8231",'1'&x"8232",'1'&x"8233",'1'&x"8234",'1'&x"8235",'1'&x"8236",'1'&x"8237",'1'&x"8238",'1'&x"8239",'1'&x"823A",'1'&x"823B",'1'&x"823C",'1'&x"823D",'1'&x"823E",'1'&x"823F",
+--'1'&x"8240",'1'&x"8241",'1'&x"8242",'1'&x"8243",'1'&x"8244",'1'&x"8245",'1'&x"8246",'1'&x"8247",'1'&x"8248",'1'&x"8249",'1'&x"824A",'1'&x"824B",'1'&x"824C",'1'&x"824D",'1'&x"824E",'1'&x"824F",
+--'1'&x"8250",'1'&x"8251",'1'&x"8252",'1'&x"8253",'1'&x"8254",'1'&x"8255",'1'&x"8256",'1'&x"8257",'1'&x"8258",'1'&x"8259",'1'&x"825A",'1'&x"825B",'1'&x"825C",'1'&x"825D",'1'&x"825E",'1'&x"825F",
+--'1'&x"8260",'1'&x"8261",'1'&x"8262",'1'&x"8263",'1'&x"8264",'1'&x"8265",'1'&x"8266",'1'&x"8267",'1'&x"8268",'1'&x"8269",'1'&x"826A",'1'&x"826B",'1'&x"826C",'1'&x"826D",'1'&x"826E",'1'&x"826F",
+--'1'&x"8270",'1'&x"8271",'1'&x"8272",'1'&x"8273",'1'&x"8274",'1'&x"8275",'1'&x"8276",'1'&x"8277",'1'&x"8278",'1'&x"8279",'1'&x"827A",'1'&x"827B",'1'&x"827C",'1'&x"827D",'1'&x"827E",'1'&x"827F",
+--'1'&x"8280",'1'&x"8281",'1'&x"8282",'1'&x"8283",'1'&x"8284",'1'&x"8285",'1'&x"8286",'1'&x"8287",'1'&x"8288",'1'&x"8289",'1'&x"828A",'1'&x"828B",'1'&x"828C",'1'&x"828D",'1'&x"828E",'1'&x"828F",
+--'1'&x"8290",'1'&x"8291",'1'&x"8292",'1'&x"8293",'1'&x"8294",'1'&x"8295",'1'&x"8296",'1'&x"8297",'1'&x"8298",'1'&x"8299",'1'&x"829A",'1'&x"829B",'1'&x"829C",'1'&x"829D",'1'&x"829E",'1'&x"829F",
+--'1'&x"82A0",'1'&x"82A1",'1'&x"82A2",'1'&x"82A3",'1'&x"82A4",'1'&x"82A5",'1'&x"82A6",'1'&x"82A7",'1'&x"82A8",'1'&x"82A9",'1'&x"82AA",'1'&x"82AB",'1'&x"82AC",'1'&x"82AD",'1'&x"82AE",'1'&x"82AF",
+--'1'&x"82B0",'1'&x"82B1",'1'&x"82B2",'1'&x"82B3",'1'&x"82B4",'1'&x"82B5",'1'&x"82B6",'1'&x"82B7",'1'&x"82B8",'1'&x"82B9",'1'&x"82BA",'1'&x"82BB",'1'&x"82BC",'1'&x"82BD",'1'&x"82BE",'1'&x"82BF",
+--'1'&x"82C0",'1'&x"82C1",'1'&x"82C2",'1'&x"82C3",'1'&x"82C4",'1'&x"82C5",'1'&x"82C6",'1'&x"82C7",'1'&x"82C8",'1'&x"82C9",'1'&x"82CA",'1'&x"82CB",'1'&x"82CC",'1'&x"82CD",'1'&x"82CE",'1'&x"82CF",
+--'1'&x"82D0",'1'&x"82D1",'1'&x"82D2",'1'&x"82D3",'1'&x"82D4",'1'&x"82D5",'1'&x"82D6",'1'&x"82D7",'1'&x"82D8",'1'&x"82D9",'1'&x"82DA",'1'&x"82DB",'1'&x"82DC",'1'&x"82DD",'1'&x"82DE",'1'&x"82DF",
+--'1'&x"82E0",'1'&x"82E1",'1'&x"82E2",'1'&x"82E3",'1'&x"82E4",'1'&x"82E5",'1'&x"82E6",'1'&x"82E7",'1'&x"82E8",'1'&x"82E9",'1'&x"82EA",'1'&x"82EB",'1'&x"82EC",'1'&x"82ED",'1'&x"82EE",'1'&x"82EF",
+--'1'&x"82F0",'1'&x"82F1",'1'&x"82F2",'1'&x"82F3",'1'&x"82F4",'1'&x"82F5",'1'&x"82F6",'1'&x"82F7",'1'&x"82F8",'1'&x"82F9",'1'&x"82FA",'1'&x"82FB",'1'&x"82FC",'1'&x"82FD",'1'&x"82FE",'1'&x"82FF",
+--'1'&x"8300",'1'&x"8301",'1'&x"8302",'1'&x"8303",'1'&x"8304",'1'&x"8305",'1'&x"8306",'1'&x"8307",'1'&x"8308",'1'&x"8309",'1'&x"830A",'1'&x"830B",'1'&x"830C",'1'&x"830D",'1'&x"830E",'1'&x"830F",
+--'1'&x"8310",'1'&x"8311",'1'&x"8312",'1'&x"8313",'1'&x"8314",'1'&x"8315",'1'&x"8316",'1'&x"8317",'1'&x"8318",'1'&x"8319",'1'&x"831A",'1'&x"831B",'1'&x"831C",'1'&x"831D",'1'&x"831E",'1'&x"831F",
+--'1'&x"8320",'1'&x"8321",'1'&x"8322",'1'&x"8323",'1'&x"8324",'1'&x"8325",'1'&x"8326",'1'&x"8327",'1'&x"8328",'1'&x"8329",'1'&x"832A",'1'&x"832B",'1'&x"832C",'1'&x"832D",'1'&x"832E",'1'&x"832F",
+--'1'&x"8330",'1'&x"8331",'1'&x"8332",'1'&x"8333",'1'&x"8334",'1'&x"8335",'1'&x"8336",'1'&x"8337",'1'&x"8338",'1'&x"8339",'1'&x"833A",'1'&x"833B",'1'&x"833C",'1'&x"833D",'1'&x"833E",'1'&x"833F",
+--'1'&x"8340",'1'&x"8341",'1'&x"8342",'1'&x"8343",'1'&x"8344",'1'&x"8345",'1'&x"8346",'1'&x"8347",'1'&x"8348",'1'&x"8349",'1'&x"834A",'1'&x"834B",'1'&x"834C",'1'&x"834D",'1'&x"834E",'1'&x"834F",
+--'1'&x"8350",'1'&x"8351",'1'&x"8352",'1'&x"8353",'1'&x"8354",'1'&x"8355",'1'&x"8356",'1'&x"8357",'1'&x"8358",'1'&x"8359",'1'&x"835A",'1'&x"835B",'1'&x"835C",'1'&x"835D",'1'&x"835E",'1'&x"835F",
+--'1'&x"8360",'1'&x"8361",'1'&x"8362",'1'&x"8363",'1'&x"8364",'1'&x"8365",'1'&x"8366",'1'&x"8367",'1'&x"8368",'1'&x"8369",'1'&x"836A",'1'&x"836B",'1'&x"836C",'1'&x"836D",'1'&x"836E",'1'&x"836F",
+--'1'&x"8370",'1'&x"8371",'1'&x"8372",'1'&x"8373",'1'&x"8374",'1'&x"8375",'1'&x"8376",'1'&x"8377",'1'&x"8378",'1'&x"8379",'1'&x"837A",'1'&x"837B",'1'&x"837C",'1'&x"837D",'1'&x"837E",'1'&x"837F",
+--'1'&x"8380",'1'&x"8381",'1'&x"8382",'1'&x"8383",'1'&x"8384",'1'&x"8385",'1'&x"8386",'1'&x"8387",'1'&x"8388",'1'&x"8389",'1'&x"838A",'1'&x"838B",'1'&x"838C",'1'&x"838D",'1'&x"838E",'1'&x"838F",
+--'1'&x"8390",'1'&x"8391",'1'&x"8392",'1'&x"8393",'1'&x"8394",'1'&x"8395",'1'&x"8396",'1'&x"8397",'1'&x"8398",'1'&x"8399",'1'&x"839A",'1'&x"839B",'1'&x"839C",'1'&x"839D",'1'&x"839E",'1'&x"839F",
+--'1'&x"83A0",'1'&x"83A1",'1'&x"83A2",'1'&x"83A3",'1'&x"83A4",'1'&x"83A5",'1'&x"83A6",'1'&x"83A7",'1'&x"83A8",'1'&x"83A9",'1'&x"83AA",'1'&x"83AB",'1'&x"83AC",'1'&x"83AD",'1'&x"83AE",'1'&x"83AF",
+--'1'&x"83B0",'1'&x"83B1",'1'&x"83B2",'1'&x"83B3",'1'&x"83B4",'1'&x"83B5",'1'&x"83B6",'1'&x"83B7",'1'&x"83B8",'1'&x"83B9",'1'&x"83BA",'1'&x"83BB",'1'&x"83BC",'1'&x"83BD",'1'&x"83BE",'1'&x"83BF",
+--'1'&x"83C0",'1'&x"83C1",'1'&x"83C2",'1'&x"83C3",'1'&x"83C4",'1'&x"83C5",'1'&x"83C6",'1'&x"83C7",'1'&x"83C8",'1'&x"83C9",'1'&x"83CA",'1'&x"83CB",'1'&x"83CC",'1'&x"83CD",'1'&x"83CE",'1'&x"83CF",
+--'1'&x"83D0",'1'&x"83D1",'1'&x"83D2",'1'&x"83D3",'1'&x"83D4",'1'&x"83D5",'1'&x"83D6",'1'&x"83D7",'1'&x"83D8",'1'&x"83D9",'1'&x"83DA",'1'&x"83DB",'1'&x"83DC",'1'&x"83DD",'1'&x"83DE",'1'&x"83DF",
+--'1'&x"83E0",'1'&x"83E1",'1'&x"83E2",'1'&x"83E3",'1'&x"83E4",'1'&x"83E5",'1'&x"83E6",'1'&x"83E7",'1'&x"83E8",'1'&x"83E9",'1'&x"83EA",'1'&x"83EB",'1'&x"83EC",'1'&x"83ED",'1'&x"83EE",'1'&x"83EF",
+--'1'&x"83F0",'1'&x"83F1",'1'&x"83F2",'1'&x"83F3",'1'&x"83F4",'1'&x"83F5",'1'&x"83F6",'1'&x"83F7",'1'&x"83F8",'1'&x"83F9",'1'&x"83FA",'1'&x"83FB",'1'&x"83FC",'1'&x"83FD",'1'&x"83FE",'1'&x"83FF",
+--'1'&x"8400",'1'&x"8401",'1'&x"8402",'1'&x"8403",'1'&x"8404",'1'&x"8405",'1'&x"8406",'1'&x"8407",'1'&x"8408",'1'&x"8409",'1'&x"840A",'1'&x"840B",'1'&x"840C",'1'&x"840D",'1'&x"840E",'1'&x"840F",
+--'1'&x"8410",'1'&x"8411",'1'&x"8412",'1'&x"8413",'1'&x"8414",'1'&x"8415",'1'&x"8416",'1'&x"8417",'1'&x"8418",'1'&x"8419",'1'&x"841A",'1'&x"841B",'1'&x"841C",'1'&x"841D",'1'&x"841E",'1'&x"841F",
+--'1'&x"8420",'1'&x"8421",'1'&x"8422",'1'&x"8423",'1'&x"8424",'1'&x"8425",'1'&x"8426",'1'&x"8427",'1'&x"8428",'1'&x"8429",'1'&x"842A",'1'&x"842B",'1'&x"842C",'1'&x"842D",'1'&x"842E",'1'&x"842F",
+--'1'&x"8430",'1'&x"8431",'1'&x"8432",'1'&x"8433",'1'&x"8434",'1'&x"8435",'1'&x"8436",'1'&x"8437",'1'&x"8438",'1'&x"8439",'1'&x"843A",'1'&x"843B",'1'&x"843C",'1'&x"843D",'1'&x"843E",'1'&x"843F",
+--'1'&x"8440",'1'&x"8441",'1'&x"8442",'1'&x"8443",'1'&x"8444",'1'&x"8445",'1'&x"8446",'1'&x"8447",'1'&x"8448",'1'&x"8449",'1'&x"844A",'1'&x"844B",'1'&x"844C",'1'&x"844D",'1'&x"844E",'1'&x"844F",
+--'1'&x"8450",'1'&x"8451",'1'&x"8452",'1'&x"8453",'1'&x"8454",'1'&x"8455",'1'&x"8456",'1'&x"8457",'1'&x"8458",'1'&x"8459",'1'&x"845A",'1'&x"845B",'1'&x"845C",'1'&x"845D",'1'&x"845E",'1'&x"845F",
+--'1'&x"8460",'1'&x"8461",'1'&x"8462",'1'&x"8463",'1'&x"8464",'1'&x"8465",'1'&x"8466",'1'&x"8467",'1'&x"8468",'1'&x"8469",'1'&x"846A",'1'&x"846B",'1'&x"846C",'1'&x"846D",'1'&x"846E",'1'&x"846F",
+--'1'&x"8470",'1'&x"8471",'1'&x"8472",'1'&x"8473",'1'&x"8474",'1'&x"8475",'1'&x"8476",'1'&x"8477",'1'&x"8478",'1'&x"8479",'1'&x"847A",'1'&x"847B",'1'&x"847C",'1'&x"847D",'1'&x"847E",'1'&x"847F",
+--'1'&x"8480",'1'&x"8481",'1'&x"8482",'1'&x"8483",'1'&x"8484",'1'&x"8485",'1'&x"8486",'1'&x"8487",'1'&x"8488",'1'&x"8489",'1'&x"848A",'1'&x"848B",'1'&x"848C",'1'&x"848D",'1'&x"848E",'1'&x"848F",
+--'1'&x"8490",'1'&x"8491",'1'&x"8492",'1'&x"8493",'1'&x"8494",'1'&x"8495",'1'&x"8496",'1'&x"8497",'1'&x"8498",'1'&x"8499",'1'&x"849A",'1'&x"849B",'1'&x"849C",'1'&x"849D",'1'&x"849E",'1'&x"849F",
+--'1'&x"84A0",'1'&x"84A1",'1'&x"84A2",'1'&x"84A3",'1'&x"84A4",'1'&x"84A5",'1'&x"84A6",'1'&x"84A7",'1'&x"84A8",'1'&x"84A9",'1'&x"84AA",'1'&x"84AB",'1'&x"84AC",'1'&x"84AD",'1'&x"84AE",'1'&x"84AF",
+--'1'&x"84B0",'1'&x"84B1",'1'&x"84B2",'1'&x"84B3",'1'&x"84B4",'1'&x"84B5",'1'&x"84B6",'1'&x"84B7",'1'&x"84B8",'1'&x"84B9",'1'&x"84BA",'1'&x"84BB",'1'&x"84BC",'1'&x"84BD",'1'&x"84BE",'1'&x"84BF",
+--'1'&x"84C0",'1'&x"84C1",'1'&x"84C2",'1'&x"84C3",'1'&x"84C4",'1'&x"84C5",'1'&x"84C6",'1'&x"84C7",'1'&x"84C8",'1'&x"84C9",'1'&x"84CA",'1'&x"84CB",'1'&x"84CC",'1'&x"84CD",'1'&x"84CE",'1'&x"84CF",
+--'1'&x"84D0",'1'&x"84D1",'1'&x"84D2",'1'&x"84D3",'1'&x"84D4",'1'&x"84D5",'1'&x"84D6",'1'&x"84D7",'1'&x"84D8",'1'&x"84D9",'1'&x"84DA",'1'&x"84DB",'1'&x"84DC",'1'&x"84DD",'1'&x"84DE",'1'&x"84DF",
+--'1'&x"84E0",'1'&x"84E1",'1'&x"84E2",'1'&x"84E3",'1'&x"84E4",'1'&x"84E5",'1'&x"84E6",'1'&x"84E7",'1'&x"84E8",'1'&x"84E9",'1'&x"84EA",'1'&x"84EB",'1'&x"84EC",'1'&x"84ED",'1'&x"84EE",'1'&x"84EF",
+--'1'&x"84F0",'1'&x"84F1",'1'&x"84F2",'1'&x"84F3",'1'&x"84F4",'1'&x"84F5",'1'&x"84F6",'1'&x"84F7",'1'&x"84F8",'1'&x"84F9",'1'&x"84FA",'1'&x"84FB",'1'&x"84FC",'1'&x"84FD",'1'&x"84FE",'1'&x"84FF",
+--'1'&x"8500",'1'&x"8501",'1'&x"8502",'1'&x"8503",'1'&x"8504",'1'&x"8505",'1'&x"8506",'1'&x"8507",'1'&x"8508",'1'&x"8509",'1'&x"850A",'1'&x"850B",'1'&x"850C",'1'&x"850D",'1'&x"850E",'1'&x"850F",
+--'1'&x"8510",'1'&x"8511",'1'&x"8512",'1'&x"8513",'1'&x"8514",'1'&x"8515",'1'&x"8516",'1'&x"8517",'1'&x"8518",'1'&x"8519",'1'&x"851A",'1'&x"851B",'1'&x"851C",'1'&x"851D",'1'&x"851E",'1'&x"851F",
+--'1'&x"8520",'1'&x"8521",'1'&x"8522",'1'&x"8523",'1'&x"8524",'1'&x"8525",'1'&x"8526",'1'&x"8527",'1'&x"8528",'1'&x"8529",'1'&x"852A",'1'&x"852B",'1'&x"852C",'1'&x"852D",'1'&x"852E",'1'&x"852F",
+--'1'&x"8530",'1'&x"8531",'1'&x"8532",'1'&x"8533",'1'&x"8534",'1'&x"8535",'1'&x"8536",'1'&x"8537",'1'&x"8538",'1'&x"8539",'1'&x"853A",'1'&x"853B",'1'&x"853C",'1'&x"853D",'1'&x"853E",'1'&x"853F",
+--'1'&x"8540",'1'&x"8541",'1'&x"8542",'1'&x"8543",'1'&x"8544",'1'&x"8545",'1'&x"8546",'1'&x"8547",'1'&x"8548",'1'&x"8549",'1'&x"854A",'1'&x"854B",'1'&x"854C",'1'&x"854D",'1'&x"854E",'1'&x"854F",
+--'1'&x"8550",'1'&x"8551",'1'&x"8552",'1'&x"8553",'1'&x"8554",'1'&x"8555",'1'&x"8556",'1'&x"8557",'1'&x"8558",'1'&x"8559",'1'&x"855A",'1'&x"855B",'1'&x"855C",'1'&x"855D",'1'&x"855E",'1'&x"855F",
+--'1'&x"8560",'1'&x"8561",'1'&x"8562",'1'&x"8563",'1'&x"8564",'1'&x"8565",'1'&x"8566",'1'&x"8567",'1'&x"8568",'1'&x"8569",'1'&x"856A",'1'&x"856B",'1'&x"856C",'1'&x"856D",'1'&x"856E",'1'&x"856F",
+--'1'&x"8570",'1'&x"8571",'1'&x"8572",'1'&x"8573",'1'&x"8574",'1'&x"8575",'1'&x"8576",'1'&x"8577",'1'&x"8578",'1'&x"8579",'1'&x"857A",'1'&x"857B",'1'&x"857C",'1'&x"857D",'1'&x"857E",'1'&x"857F",
+--'1'&x"8580",'1'&x"8581",'1'&x"8582",'1'&x"8583",'1'&x"8584",'1'&x"8585",'1'&x"8586",'1'&x"8587",'1'&x"8588",'1'&x"8589",'1'&x"858A",'1'&x"858B",'1'&x"858C",'1'&x"858D",'1'&x"858E",'1'&x"858F",
+--'1'&x"8590",'1'&x"8591",'1'&x"8592",'1'&x"8593",'1'&x"8594",'1'&x"8595",'1'&x"8596",'1'&x"8597",'1'&x"8598",'1'&x"8599",'1'&x"859A",'1'&x"859B",'1'&x"859C",'1'&x"859D",'1'&x"859E",'1'&x"859F",
+--'1'&x"85A0",'1'&x"85A1",'1'&x"85A2",'1'&x"85A3",'1'&x"85A4",'1'&x"85A5",'1'&x"85A6",'1'&x"85A7",'1'&x"85A8",'1'&x"85A9",'1'&x"85AA",'1'&x"85AB",'1'&x"85AC",'1'&x"85AD",'1'&x"85AE",'1'&x"85AF",
+--'1'&x"85B0",'1'&x"85B1",'1'&x"85B2",'1'&x"85B3",'1'&x"85B4",'1'&x"85B5",'1'&x"85B6",'1'&x"85B7",'1'&x"85B8",'1'&x"85B9",'1'&x"85BA",'1'&x"85BB",'1'&x"85BC",'1'&x"85BD",'1'&x"85BE",'1'&x"85BF",
+--'1'&x"85C0",'1'&x"85C1",'1'&x"85C2",'1'&x"85C3",'1'&x"85C4",'1'&x"85C5",'1'&x"85C6",'1'&x"85C7",'1'&x"85C8",'1'&x"85C9",'1'&x"85CA",'1'&x"85CB",'1'&x"85CC",'1'&x"85CD",'1'&x"85CE",'1'&x"85CF",
+--'1'&x"85D0",'1'&x"85D1",'1'&x"85D2",'1'&x"85D3",'1'&x"85D4",'1'&x"85D5",'1'&x"85D6",'1'&x"85D7",'1'&x"85D8",'1'&x"85D9",'1'&x"85DA",'1'&x"85DB",'1'&x"85DC",'1'&x"85DD",'1'&x"85DE",'1'&x"85DF",
+--'1'&x"85E0",'1'&x"85E1",'1'&x"85E2",'1'&x"85E3",'1'&x"85E4",'1'&x"85E5",'1'&x"85E6",'1'&x"85E7",'1'&x"85E8",'1'&x"85E9",'1'&x"85EA",'1'&x"85EB",'1'&x"85EC",'1'&x"85ED",'1'&x"85EE",'1'&x"85EF",
+--'1'&x"85F0",'1'&x"85F1",'1'&x"85F2",'1'&x"85F3",'1'&x"85F4",'1'&x"85F5",'1'&x"85F6",'1'&x"85F7",'1'&x"85F8",'1'&x"85F9",'1'&x"85FA",'1'&x"85FB",'1'&x"85FC",'1'&x"85FD",'1'&x"85FE",'1'&x"85FF",
+--'1'&x"8600",'1'&x"8601",'1'&x"8602",'1'&x"8603",'1'&x"8604",'1'&x"8605",'1'&x"8606",'1'&x"8607",'1'&x"8608",'1'&x"8609",'1'&x"860A",'1'&x"860B",'1'&x"860C",'1'&x"860D",'1'&x"860E",'1'&x"860F",
+--'1'&x"8610",'1'&x"8611",'1'&x"8612",'1'&x"8613",'1'&x"8614",'1'&x"8615",'1'&x"8616",'1'&x"8617",'1'&x"8618",'1'&x"8619",'1'&x"861A",'1'&x"861B",'1'&x"861C",'1'&x"861D",'1'&x"861E",'1'&x"861F",
+--'1'&x"8620",'1'&x"8621",'1'&x"8622",'1'&x"8623",'1'&x"8624",'1'&x"8625",'1'&x"8626",'1'&x"8627",'1'&x"8628",'1'&x"8629",'1'&x"862A",'1'&x"862B",'1'&x"862C",'1'&x"862D",'1'&x"862E",'1'&x"862F",
+--'1'&x"8630",'1'&x"8631",'1'&x"8632",'1'&x"8633",'1'&x"8634",'1'&x"8635",'1'&x"8636",'1'&x"8637",'1'&x"8638",'1'&x"8639",'1'&x"863A",'1'&x"863B",'1'&x"863C",'1'&x"863D",'1'&x"863E",'1'&x"863F",
+--'1'&x"8640",'1'&x"8641",'1'&x"8642",'1'&x"8643",'1'&x"8644",'1'&x"8645",'1'&x"8646",'1'&x"8647",'1'&x"8648",'1'&x"8649",'1'&x"864A",'1'&x"864B",'1'&x"864C",'1'&x"864D",'1'&x"864E",'1'&x"864F",
+--'1'&x"8650",'1'&x"8651",'1'&x"8652",'1'&x"8653",'1'&x"8654",'1'&x"8655",'1'&x"8656",'1'&x"8657",'1'&x"8658",'1'&x"8659",'1'&x"865A",'1'&x"865B",'1'&x"865C",'1'&x"865D",'1'&x"865E",'1'&x"865F",
+--'1'&x"8660",'1'&x"8661",'1'&x"8662",'1'&x"8663",'1'&x"8664",'1'&x"8665",'1'&x"8666",'1'&x"8667",'1'&x"8668",'1'&x"8669",'1'&x"866A",'1'&x"866B",'1'&x"866C",'1'&x"866D",'1'&x"866E",'1'&x"866F",
+--'1'&x"8670",'1'&x"8671",'1'&x"8672",'1'&x"8673",'1'&x"8674",'1'&x"8675",'1'&x"8676",'1'&x"8677",'1'&x"8678",'1'&x"8679",'1'&x"867A",'1'&x"867B",'1'&x"867C",'1'&x"867D",'1'&x"867E",'1'&x"867F",
+--'1'&x"8680",'1'&x"8681",'1'&x"8682",'1'&x"8683",'1'&x"8684",'1'&x"8685",'1'&x"8686",'1'&x"8687",'1'&x"8688",'1'&x"8689",'1'&x"868A",'1'&x"868B",'1'&x"868C",'1'&x"868D",'1'&x"868E",'1'&x"868F",
+--'1'&x"8690",'1'&x"8691",'1'&x"8692",'1'&x"8693",'1'&x"8694",'1'&x"8695",'1'&x"8696",'1'&x"8697",'1'&x"8698",'1'&x"8699",'1'&x"869A",'1'&x"869B",'1'&x"869C",'1'&x"869D",'1'&x"869E",'1'&x"869F",
+--'1'&x"86A0",'1'&x"86A1",'1'&x"86A2",'1'&x"86A3",'1'&x"86A4",'1'&x"86A5",'1'&x"86A6",'1'&x"86A7",'1'&x"86A8",'1'&x"86A9",'1'&x"86AA",'1'&x"86AB",'1'&x"86AC",'1'&x"86AD",'1'&x"86AE",'1'&x"86AF",
+--'1'&x"86B0",'1'&x"86B1",'1'&x"86B2",'1'&x"86B3",'1'&x"86B4",'1'&x"86B5",'1'&x"86B6",'1'&x"86B7",'1'&x"86B8",'1'&x"86B9",'1'&x"86BA",'1'&x"86BB",'1'&x"86BC",'1'&x"86BD",'1'&x"86BE",'1'&x"86BF",
+--'1'&x"86C0",'1'&x"86C1",'1'&x"86C2",'1'&x"86C3",'1'&x"86C4",'1'&x"86C5",'1'&x"86C6",'1'&x"86C7",'1'&x"86C8",'1'&x"86C9",'1'&x"86CA",'1'&x"86CB",'1'&x"86CC",'1'&x"86CD",'1'&x"86CE",'1'&x"86CF",
+--'1'&x"86D0",'1'&x"86D1",'1'&x"86D2",'1'&x"86D3",'1'&x"86D4",'1'&x"86D5",'1'&x"86D6",'1'&x"86D7",'1'&x"86D8",'1'&x"86D9",'1'&x"86DA",'1'&x"86DB",'1'&x"86DC",'1'&x"86DD",'1'&x"86DE",'1'&x"86DF",
+--'1'&x"86E0",'1'&x"86E1",'1'&x"86E2",'1'&x"86E3",'1'&x"86E4",'1'&x"86E5",'1'&x"86E6",'1'&x"86E7",'1'&x"86E8",'1'&x"86E9",'1'&x"86EA",'1'&x"86EB",'1'&x"86EC",'1'&x"86ED",'1'&x"86EE",'1'&x"86EF",
+--'1'&x"86F0",'1'&x"86F1",'1'&x"86F2",'1'&x"86F3",'1'&x"86F4",'1'&x"86F5",'1'&x"86F6",'1'&x"86F7",'1'&x"86F8",'1'&x"86F9",'1'&x"86FA",'1'&x"86FB",'1'&x"86FC",'1'&x"86FD",'1'&x"86FE",'1'&x"86FF",
+--'1'&x"8700",'1'&x"8701",'1'&x"8702",'1'&x"8703",'1'&x"8704",'1'&x"8705",'1'&x"8706",'1'&x"8707",'1'&x"8708",'1'&x"8709",'1'&x"870A",'1'&x"870B",'1'&x"870C",'1'&x"870D",'1'&x"870E",'1'&x"870F",
+--'1'&x"8710",'1'&x"8711",'1'&x"8712",'1'&x"8713",'1'&x"8714",'1'&x"8715",'1'&x"8716",'1'&x"8717",'1'&x"8718",'1'&x"8719",'1'&x"871A",'1'&x"871B",'1'&x"871C",'1'&x"871D",'1'&x"871E",'1'&x"871F",
+--'1'&x"8720",'1'&x"8721",'1'&x"8722",'1'&x"8723",'1'&x"8724",'1'&x"8725",'1'&x"8726",'1'&x"8727",'1'&x"8728",'1'&x"8729",'1'&x"872A",'1'&x"872B",'1'&x"872C",'1'&x"872D",'1'&x"872E",'1'&x"872F",
+--'1'&x"8730",'1'&x"8731",'1'&x"8732",'1'&x"8733",'1'&x"8734",'1'&x"8735",'1'&x"8736",'1'&x"8737",'1'&x"8738",'1'&x"8739",'1'&x"873A",'1'&x"873B",'1'&x"873C",'1'&x"873D",'1'&x"873E",'1'&x"873F",
+--'1'&x"8740",'1'&x"8741",'1'&x"8742",'1'&x"8743",'1'&x"8744",'1'&x"8745",'1'&x"8746",'1'&x"8747",'1'&x"8748",'1'&x"8749",'1'&x"874A",'1'&x"874B",'1'&x"874C",'1'&x"874D",'1'&x"874E",'1'&x"874F",
+--'1'&x"8750",'1'&x"8751",'1'&x"8752",'1'&x"8753",'1'&x"8754",'1'&x"8755",'1'&x"8756",'1'&x"8757",'1'&x"8758",'1'&x"8759",'1'&x"875A",'1'&x"875B",'1'&x"875C",'1'&x"875D",'1'&x"875E",'1'&x"875F",
+--'1'&x"8760",'1'&x"8761",'1'&x"8762",'1'&x"8763",'1'&x"8764",'1'&x"8765",'1'&x"8766",'1'&x"8767",'1'&x"8768",'1'&x"8769",'1'&x"876A",'1'&x"876B",'1'&x"876C",'1'&x"876D",'1'&x"876E",'1'&x"876F",
+--'1'&x"8770",'1'&x"8771",'1'&x"8772",'1'&x"8773",'1'&x"8774",'1'&x"8775",'1'&x"8776",'1'&x"8777",'1'&x"8778",'1'&x"8779",'1'&x"877A",'1'&x"877B",'1'&x"877C",'1'&x"877D",'1'&x"877E",'1'&x"877F",
+--'1'&x"8780",'1'&x"8781",'1'&x"8782",'1'&x"8783",'1'&x"8784",'1'&x"8785",'1'&x"8786",'1'&x"8787",'1'&x"8788",'1'&x"8789",'1'&x"878A",'1'&x"878B",'1'&x"878C",'1'&x"878D",'1'&x"878E",'1'&x"878F",
+--'1'&x"8790",'1'&x"8791",'1'&x"8792",'1'&x"8793",'1'&x"8794",'1'&x"8795",'1'&x"8796",'1'&x"8797",'1'&x"8798",'1'&x"8799",'1'&x"879A",'1'&x"879B",'1'&x"879C",'1'&x"879D",'1'&x"879E",'1'&x"879F",
+--'1'&x"87A0",'1'&x"87A1",'1'&x"87A2",'1'&x"87A3",'1'&x"87A4",'1'&x"87A5",'1'&x"87A6",'1'&x"87A7",'1'&x"87A8",'1'&x"87A9",'1'&x"87AA",'1'&x"87AB",'1'&x"87AC",'1'&x"87AD",'1'&x"87AE",'1'&x"87AF",
+--'1'&x"87B0",'1'&x"87B1",'1'&x"87B2",'1'&x"87B3",'1'&x"87B4",'1'&x"87B5",'1'&x"87B6",'1'&x"87B7",'1'&x"87B8",'1'&x"87B9",'1'&x"87BA",'1'&x"87BB",'1'&x"87BC",'1'&x"87BD",'1'&x"87BE",'1'&x"87BF",
+--'1'&x"87C0",'1'&x"87C1",'1'&x"87C2",'1'&x"87C3",'1'&x"87C4",'1'&x"87C5",'1'&x"87C6",'1'&x"87C7",'1'&x"87C8",'1'&x"87C9",'1'&x"87CA",'1'&x"87CB",'1'&x"87CC",'1'&x"87CD",'1'&x"87CE",'1'&x"87CF",
+--'1'&x"87D0",'1'&x"87D1",'1'&x"87D2",'1'&x"87D3",'1'&x"87D4",'1'&x"87D5",'1'&x"87D6",'1'&x"87D7",'1'&x"87D8",'1'&x"87D9",'1'&x"87DA",'1'&x"87DB",'1'&x"87DC",'1'&x"87DD",'1'&x"87DE",'1'&x"87DF",
+--'1'&x"87E0",'1'&x"87E1",'1'&x"87E2",'1'&x"87E3",'1'&x"87E4",'1'&x"87E5",'1'&x"87E6",'1'&x"87E7",'1'&x"87E8",'1'&x"87E9",'1'&x"87EA",'1'&x"87EB",'1'&x"87EC",'1'&x"87ED",'1'&x"87EE",'1'&x"87EF",
+--'1'&x"87F0",'1'&x"87F1",'1'&x"87F2",'1'&x"87F3",'1'&x"87F4",'1'&x"87F5",'1'&x"87F6",'1'&x"87F7",'1'&x"87F8",'1'&x"87F9",'1'&x"87FA",'1'&x"87FB",'1'&x"87FC",'1'&x"87FD",'1'&x"87FE",'1'&x"87FF",
+--'1'&x"8800",'1'&x"8801",'1'&x"8802",'1'&x"8803",'1'&x"8804",'1'&x"8805",'1'&x"8806",'1'&x"8807",'1'&x"8808",'1'&x"8809",'1'&x"880A",'1'&x"880B",'1'&x"880C",'1'&x"880D",'1'&x"880E",'1'&x"880F",
+--'1'&x"8810",'1'&x"8811",'1'&x"8812",'1'&x"8813",'1'&x"8814",'1'&x"8815",'1'&x"8816",'1'&x"8817",'1'&x"8818",'1'&x"8819",'1'&x"881A",'1'&x"881B",'1'&x"881C",'1'&x"881D",'1'&x"881E",'1'&x"881F",
+--'1'&x"8820",'1'&x"8821",'1'&x"8822",'1'&x"8823",'1'&x"8824",'1'&x"8825",'1'&x"8826",'1'&x"8827",'1'&x"8828",'1'&x"8829",'1'&x"882A",'1'&x"882B",'1'&x"882C",'1'&x"882D",'1'&x"882E",'1'&x"882F",
+--'1'&x"8830",'1'&x"8831",'1'&x"8832",'1'&x"8833",'1'&x"8834",'1'&x"8835",'1'&x"8836",'1'&x"8837",'1'&x"8838",'1'&x"8839",'1'&x"883A",'1'&x"883B",'1'&x"883C",'1'&x"883D",'1'&x"883E",'1'&x"883F",
+--'1'&x"8840",'1'&x"8841",'1'&x"8842",'1'&x"8843",'1'&x"8844",'1'&x"8845",'1'&x"8846",'1'&x"8847",'1'&x"8848",'1'&x"8849",'1'&x"884A",'1'&x"884B",'1'&x"884C",'1'&x"884D",'1'&x"884E",'1'&x"884F",
+--'1'&x"8850",'1'&x"8851",'1'&x"8852",'1'&x"8853",'1'&x"8854",'1'&x"8855",'1'&x"8856",'1'&x"8857",'1'&x"8858",'1'&x"8859",'1'&x"885A",'1'&x"885B",'1'&x"885C",'1'&x"885D",'1'&x"885E",'1'&x"885F",
+--'1'&x"8860",'1'&x"8861",'1'&x"8862",'1'&x"8863",'1'&x"8864",'1'&x"8865",'1'&x"8866",'1'&x"8867",'1'&x"8868",'1'&x"8869",'1'&x"886A",'1'&x"886B",'1'&x"886C",'1'&x"886D",'1'&x"886E",'1'&x"886F",
+--'1'&x"8870",'1'&x"8871",'1'&x"8872",'1'&x"8873",'1'&x"8874",'1'&x"8875",'1'&x"8876",'1'&x"8877",'1'&x"8878",'1'&x"8879",'1'&x"887A",'1'&x"887B",'1'&x"887C",'1'&x"887D",'1'&x"887E",'1'&x"887F",
+--'1'&x"8880",'1'&x"8881",'1'&x"8882",'1'&x"8883",'1'&x"8884",'1'&x"8885",'1'&x"8886",'1'&x"8887",'1'&x"8888",'1'&x"8889",'1'&x"888A",'1'&x"888B",'1'&x"888C",'1'&x"888D",'1'&x"888E",'1'&x"888F",
+--'1'&x"8890",'1'&x"8891",'1'&x"8892",'1'&x"8893",'1'&x"8894",'1'&x"8895",'1'&x"8896",'1'&x"8897",'1'&x"8898",'1'&x"8899",'1'&x"889A",'1'&x"889B",'1'&x"889C",'1'&x"889D",'1'&x"889E",'1'&x"889F",
+--'1'&x"88A0",'1'&x"88A1",'1'&x"88A2",'1'&x"88A3",'1'&x"88A4",'1'&x"88A5",'1'&x"88A6",'1'&x"88A7",'1'&x"88A8",'1'&x"88A9",'1'&x"88AA",'1'&x"88AB",'1'&x"88AC",'1'&x"88AD",'1'&x"88AE",'1'&x"88AF",
+--'1'&x"88B0",'1'&x"88B1",'1'&x"88B2",'1'&x"88B3",'1'&x"88B4",'1'&x"88B5",'1'&x"88B6",'1'&x"88B7",'1'&x"88B8",'1'&x"88B9",'1'&x"88BA",'1'&x"88BB",'1'&x"88BC",'1'&x"88BD",'1'&x"88BE",'1'&x"88BF",
+--'1'&x"88C0",'1'&x"88C1",'1'&x"88C2",'1'&x"88C3",'1'&x"88C4",'1'&x"88C5",'1'&x"88C6",'1'&x"88C7",'1'&x"88C8",'1'&x"88C9",'1'&x"88CA",'1'&x"88CB",'1'&x"88CC",'1'&x"88CD",'1'&x"88CE",'1'&x"88CF",
+--'1'&x"88D0",'1'&x"88D1",'1'&x"88D2",'1'&x"88D3",'1'&x"88D4",'1'&x"88D5",'1'&x"88D6",'1'&x"88D7",'1'&x"88D8",'1'&x"88D9",'1'&x"88DA",'1'&x"88DB",'1'&x"88DC",'1'&x"88DD",'1'&x"88DE",'1'&x"88DF",
+--'1'&x"88E0",'1'&x"88E1",'1'&x"88E2",'1'&x"88E3",'1'&x"88E4",'1'&x"88E5",'1'&x"88E6",'1'&x"88E7",'1'&x"88E8",'1'&x"88E9",'1'&x"88EA",'1'&x"88EB",'1'&x"88EC",'1'&x"88ED",'1'&x"88EE",'1'&x"88EF",
+--'1'&x"88F0",'1'&x"88F1",'1'&x"88F2",'1'&x"88F3",'1'&x"88F4",'1'&x"88F5",'1'&x"88F6",'1'&x"88F7",'1'&x"88F8",'1'&x"88F9",'1'&x"88FA",'1'&x"88FB",'1'&x"88FC",'1'&x"88FD",'1'&x"88FE",'1'&x"88FF",
+--'1'&x"8900",'1'&x"8901",'1'&x"8902",'1'&x"8903",'1'&x"8904",'1'&x"8905",'1'&x"8906",'1'&x"8907",'1'&x"8908",'1'&x"8909",'1'&x"890A",'1'&x"890B",'1'&x"890C",'1'&x"890D",'1'&x"890E",'1'&x"890F",
+--'1'&x"8910",'1'&x"8911",'1'&x"8912",'1'&x"8913",'1'&x"8914",'1'&x"8915",'1'&x"8916",'1'&x"8917",'1'&x"8918",'1'&x"8919",'1'&x"891A",'1'&x"891B",'1'&x"891C",'1'&x"891D",'1'&x"891E",'1'&x"891F",
+--'1'&x"8920",'1'&x"8921",'1'&x"8922",'1'&x"8923",'1'&x"8924",'1'&x"8925",'1'&x"8926",'1'&x"8927",'1'&x"8928",'1'&x"8929",'1'&x"892A",'1'&x"892B",'1'&x"892C",'1'&x"892D",'1'&x"892E",'1'&x"892F",
+--'1'&x"8930",'1'&x"8931",'1'&x"8932",'1'&x"8933",'1'&x"8934",'1'&x"8935",'1'&x"8936",'1'&x"8937",'1'&x"8938",'1'&x"8939",'1'&x"893A",'1'&x"893B",'1'&x"893C",'1'&x"893D",'1'&x"893E",'1'&x"893F",
+--'1'&x"8940",'1'&x"8941",'1'&x"8942",'1'&x"8943",'1'&x"8944",'1'&x"8945",'1'&x"8946",'1'&x"8947",'1'&x"8948",'1'&x"8949",'1'&x"894A",'1'&x"894B",'1'&x"894C",'1'&x"894D",'1'&x"894E",'1'&x"894F",
+--'1'&x"8950",'1'&x"8951",'1'&x"8952",'1'&x"8953",'1'&x"8954",'1'&x"8955",'1'&x"8956",'1'&x"8957",'1'&x"8958",'1'&x"8959",'1'&x"895A",'1'&x"895B",'1'&x"895C",'1'&x"895D",'1'&x"895E",'1'&x"895F",
+--'1'&x"8960",'1'&x"8961",'1'&x"8962",'1'&x"8963",'1'&x"8964",'1'&x"8965",'1'&x"8966",'1'&x"8967",'1'&x"8968",'1'&x"8969",'1'&x"896A",'1'&x"896B",'1'&x"896C",'1'&x"896D",'1'&x"896E",'1'&x"896F",
+--'1'&x"8970",'1'&x"8971",'1'&x"8972",'1'&x"8973",'1'&x"8974",'1'&x"8975",'1'&x"8976",'1'&x"8977",'1'&x"8978",'1'&x"8979",'1'&x"897A",'1'&x"897B",'1'&x"897C",'1'&x"897D",'1'&x"897E",'1'&x"897F",
+--'1'&x"8980",'1'&x"8981",'1'&x"8982",'1'&x"8983",'1'&x"8984",'1'&x"8985",'1'&x"8986",'1'&x"8987",'1'&x"8988",'1'&x"8989",'1'&x"898A",'1'&x"898B",'1'&x"898C",'1'&x"898D",'1'&x"898E",'1'&x"898F",
+--'1'&x"8990",'1'&x"8991",'1'&x"8992",'1'&x"8993",'1'&x"8994",'1'&x"8995",'1'&x"8996",'1'&x"8997",'1'&x"8998",'1'&x"8999",'1'&x"899A",'1'&x"899B",'1'&x"899C",'1'&x"899D",'1'&x"899E",'1'&x"899F",
+--'1'&x"89A0",'1'&x"89A1",'1'&x"89A2",'1'&x"89A3",'1'&x"89A4",'1'&x"89A5",'1'&x"89A6",'1'&x"89A7",'1'&x"89A8",'1'&x"89A9",'1'&x"89AA",'1'&x"89AB",'1'&x"89AC",'1'&x"89AD",'1'&x"89AE",'1'&x"89AF",
+--'1'&x"89B0",'1'&x"89B1",'1'&x"89B2",'1'&x"89B3",'1'&x"89B4",'1'&x"89B5",'1'&x"89B6",'1'&x"89B7",'1'&x"89B8",'1'&x"89B9",'1'&x"89BA",'1'&x"89BB",'1'&x"89BC",'1'&x"89BD",'1'&x"89BE",'1'&x"89BF",
+--'1'&x"89C0",'1'&x"89C1",'1'&x"89C2",'1'&x"89C3",'1'&x"89C4",'1'&x"89C5",'1'&x"89C6",'1'&x"89C7",'1'&x"89C8",'1'&x"89C9",'1'&x"89CA",'1'&x"89CB",'1'&x"89CC",'1'&x"89CD",'1'&x"89CE",'1'&x"89CF",
+--'1'&x"89D0",'1'&x"89D1",'1'&x"89D2",'1'&x"89D3",'1'&x"89D4",'1'&x"89D5",'1'&x"89D6",'1'&x"89D7",'1'&x"89D8",'1'&x"89D9",'1'&x"89DA",'1'&x"89DB",'1'&x"89DC",'1'&x"89DD",'1'&x"89DE",'1'&x"89DF",
+--'1'&x"89E0",'1'&x"89E1",'1'&x"89E2",'1'&x"89E3",'1'&x"89E4",'1'&x"89E5",'1'&x"89E6",'1'&x"89E7",'1'&x"89E8",'1'&x"89E9",'1'&x"89EA",'1'&x"89EB",'1'&x"89EC",'1'&x"89ED",'1'&x"89EE",'1'&x"89EF",
+--'1'&x"89F0",'1'&x"89F1",'1'&x"89F2",'1'&x"89F3",'1'&x"89F4",'1'&x"89F5",'1'&x"89F6",'1'&x"89F7",'1'&x"89F8",'1'&x"89F9",'1'&x"89FA",'1'&x"89FB",'1'&x"89FC",'1'&x"89FD",'1'&x"89FE",'1'&x"89FF",
+--'1'&x"8A00",'1'&x"8A01",'1'&x"8A02",'1'&x"8A03",'1'&x"8A04",'1'&x"8A05",'1'&x"8A06",'1'&x"8A07",'1'&x"8A08",'1'&x"8A09",'1'&x"8A0A",'1'&x"8A0B",'1'&x"8A0C",'1'&x"8A0D",'1'&x"8A0E",'1'&x"8A0F",
+--'1'&x"8A10",'1'&x"8A11",'1'&x"8A12",'1'&x"8A13",'1'&x"8A14",'1'&x"8A15",'1'&x"8A16",'1'&x"8A17",'1'&x"8A18",'1'&x"8A19",'1'&x"8A1A",'1'&x"8A1B",'1'&x"8A1C",'1'&x"8A1D",'1'&x"8A1E",'1'&x"8A1F",
+--'1'&x"8A20",'1'&x"8A21",'1'&x"8A22",'1'&x"8A23",'1'&x"8A24",'1'&x"8A25",'1'&x"8A26",'1'&x"8A27",'1'&x"8A28",'1'&x"8A29",'1'&x"8A2A",'1'&x"8A2B",'1'&x"8A2C",'1'&x"8A2D",'1'&x"8A2E",'1'&x"8A2F",
+--'1'&x"8A30",'1'&x"8A31",'1'&x"8A32",'1'&x"8A33",'1'&x"8A34",'1'&x"8A35",'1'&x"8A36",'1'&x"8A37",'1'&x"8A38",'1'&x"8A39",'1'&x"8A3A",'1'&x"8A3B",'1'&x"8A3C",'1'&x"8A3D",'1'&x"8A3E",'1'&x"8A3F",
+--'1'&x"8A40",'1'&x"8A41",'1'&x"8A42",'1'&x"8A43",'1'&x"8A44",'1'&x"8A45",'1'&x"8A46",'1'&x"8A47",'1'&x"8A48",'1'&x"8A49",'1'&x"8A4A",'1'&x"8A4B",'1'&x"8A4C",'1'&x"8A4D",'1'&x"8A4E",'1'&x"8A4F",
+--'1'&x"8A50",'1'&x"8A51",'1'&x"8A52",'1'&x"8A53",'1'&x"8A54",'1'&x"8A55",'1'&x"8A56",'1'&x"8A57",'1'&x"8A58",'1'&x"8A59",'1'&x"8A5A",'1'&x"8A5B",'1'&x"8A5C",'1'&x"8A5D",'1'&x"8A5E",'1'&x"8A5F",
+--'1'&x"8A60",'1'&x"8A61",'1'&x"8A62",'1'&x"8A63",'1'&x"8A64",'1'&x"8A65",'1'&x"8A66",'1'&x"8A67",'1'&x"8A68",'1'&x"8A69",'1'&x"8A6A",'1'&x"8A6B",'1'&x"8A6C",'1'&x"8A6D",'1'&x"8A6E",'1'&x"8A6F",
+--'1'&x"8A70",'1'&x"8A71",'1'&x"8A72",'1'&x"8A73",'1'&x"8A74",'1'&x"8A75",'1'&x"8A76",'1'&x"8A77",'1'&x"8A78",'1'&x"8A79",'1'&x"8A7A",'1'&x"8A7B",'1'&x"8A7C",'1'&x"8A7D",'1'&x"8A7E",'1'&x"8A7F",
+--'1'&x"8A80",'1'&x"8A81",'1'&x"8A82",'1'&x"8A83",'1'&x"8A84",'1'&x"8A85",'1'&x"8A86",'1'&x"8A87",'1'&x"8A88",'1'&x"8A89",'1'&x"8A8A",'1'&x"8A8B",'1'&x"8A8C",'1'&x"8A8D",'1'&x"8A8E",'1'&x"8A8F",
+--'1'&x"8A90",'1'&x"8A91",'1'&x"8A92",'1'&x"8A93",'1'&x"8A94",'1'&x"8A95",'1'&x"8A96",'1'&x"8A97",'1'&x"8A98",'1'&x"8A99",'1'&x"8A9A",'1'&x"8A9B",'1'&x"8A9C",'1'&x"8A9D",'1'&x"8A9E",'1'&x"8A9F",
+--'1'&x"8AA0",'1'&x"8AA1",'1'&x"8AA2",'1'&x"8AA3",'1'&x"8AA4",'1'&x"8AA5",'1'&x"8AA6",'1'&x"8AA7",'1'&x"8AA8",'1'&x"8AA9",'1'&x"8AAA",'1'&x"8AAB",'1'&x"8AAC",'1'&x"8AAD",'1'&x"8AAE",'1'&x"8AAF",
+--'1'&x"8AB0",'1'&x"8AB1",'1'&x"8AB2",'1'&x"8AB3",'1'&x"8AB4",'1'&x"8AB5",'1'&x"8AB6",'1'&x"8AB7",'1'&x"8AB8",'1'&x"8AB9",'1'&x"8ABA",'1'&x"8ABB",'1'&x"8ABC",'1'&x"8ABD",'1'&x"8ABE",'1'&x"8ABF",
+--'1'&x"8AC0",'1'&x"8AC1",'1'&x"8AC2",'1'&x"8AC3",'1'&x"8AC4",'1'&x"8AC5",'1'&x"8AC6",'1'&x"8AC7",'1'&x"8AC8",'1'&x"8AC9",'1'&x"8ACA",'1'&x"8ACB",'1'&x"8ACC",'1'&x"8ACD",'1'&x"8ACE",'1'&x"8ACF",
+--'1'&x"8AD0",'1'&x"8AD1",'1'&x"8AD2",'1'&x"8AD3",'1'&x"8AD4",'1'&x"8AD5",'1'&x"8AD6",'1'&x"8AD7",'1'&x"8AD8",'1'&x"8AD9",'1'&x"8ADA",'1'&x"8ADB",'1'&x"8ADC",'1'&x"8ADD",'1'&x"8ADE",'1'&x"8ADF",
+--'1'&x"8AE0",'1'&x"8AE1",'1'&x"8AE2",'1'&x"8AE3",'1'&x"8AE4",'1'&x"8AE5",'1'&x"8AE6",'1'&x"8AE7",'1'&x"8AE8",'1'&x"8AE9",'1'&x"8AEA",'1'&x"8AEB",'1'&x"8AEC",'1'&x"8AED",'1'&x"8AEE",'1'&x"8AEF",
+--'1'&x"8AF0",'1'&x"8AF1",'1'&x"8AF2",'1'&x"8AF3",'1'&x"8AF4",'1'&x"8AF5",'1'&x"8AF6",'1'&x"8AF7",'1'&x"8AF8",'1'&x"8AF9",'1'&x"8AFA",'1'&x"8AFB",'1'&x"8AFC",'1'&x"8AFD",'1'&x"8AFE",'1'&x"8AFF",
+--'1'&x"8B00",'1'&x"8B01",'1'&x"8B02",'1'&x"8B03",'1'&x"8B04",'1'&x"8B05",'1'&x"8B06",'1'&x"8B07",'1'&x"8B08",'1'&x"8B09",'1'&x"8B0A",'1'&x"8B0B",'1'&x"8B0C",'1'&x"8B0D",'1'&x"8B0E",'1'&x"8B0F",
+--'1'&x"8B10",'1'&x"8B11",'1'&x"8B12",'1'&x"8B13",'1'&x"8B14",'1'&x"8B15",'1'&x"8B16",'1'&x"8B17",'1'&x"8B18",'1'&x"8B19",'1'&x"8B1A",'1'&x"8B1B",'1'&x"8B1C",'1'&x"8B1D",'1'&x"8B1E",'1'&x"8B1F",
+--'1'&x"8B20",'1'&x"8B21",'1'&x"8B22",'1'&x"8B23",'1'&x"8B24",'1'&x"8B25",'1'&x"8B26",'1'&x"8B27",'1'&x"8B28",'1'&x"8B29",'1'&x"8B2A",'1'&x"8B2B",'1'&x"8B2C",'1'&x"8B2D",'1'&x"8B2E",'1'&x"8B2F",
+--'1'&x"8B30",'1'&x"8B31",'1'&x"8B32",'1'&x"8B33",'1'&x"8B34",'1'&x"8B35",'1'&x"8B36",'1'&x"8B37",'1'&x"8B38",'1'&x"8B39",'1'&x"8B3A",'1'&x"8B3B",'1'&x"8B3C",'1'&x"8B3D",'1'&x"8B3E",'1'&x"8B3F",
+--'1'&x"8B40",'1'&x"8B41",'1'&x"8B42",'1'&x"8B43",'1'&x"8B44",'1'&x"8B45",'1'&x"8B46",'1'&x"8B47",'1'&x"8B48",'1'&x"8B49",'1'&x"8B4A",'1'&x"8B4B",'1'&x"8B4C",'1'&x"8B4D",'1'&x"8B4E",'1'&x"8B4F",
+--'1'&x"8B50",'1'&x"8B51",'1'&x"8B52",'1'&x"8B53",'1'&x"8B54",'1'&x"8B55",'1'&x"8B56",'1'&x"8B57",'1'&x"8B58",'1'&x"8B59",'1'&x"8B5A",'1'&x"8B5B",'1'&x"8B5C",'1'&x"8B5D",'1'&x"8B5E",'1'&x"8B5F",
+--'1'&x"8B60",'1'&x"8B61",'1'&x"8B62",'1'&x"8B63",'1'&x"8B64",'1'&x"8B65",'1'&x"8B66",'1'&x"8B67",'1'&x"8B68",'1'&x"8B69",'1'&x"8B6A",'1'&x"8B6B",'1'&x"8B6C",'1'&x"8B6D",'1'&x"8B6E",'1'&x"8B6F",
+--'1'&x"8B70",'1'&x"8B71",'1'&x"8B72",'1'&x"8B73",'1'&x"8B74",'1'&x"8B75",'1'&x"8B76",'1'&x"8B77",'1'&x"8B78",'1'&x"8B79",'1'&x"8B7A",'1'&x"8B7B",'1'&x"8B7C",'1'&x"8B7D",'1'&x"8B7E",'1'&x"8B7F",
+--'1'&x"8B80",'1'&x"8B81",'1'&x"8B82",'1'&x"8B83",'1'&x"8B84",'1'&x"8B85",'1'&x"8B86",'1'&x"8B87",'1'&x"8B88",'1'&x"8B89",'1'&x"8B8A",'1'&x"8B8B",'1'&x"8B8C",'1'&x"8B8D",'1'&x"8B8E",'1'&x"8B8F",
+--'1'&x"8B90",'1'&x"8B91",'1'&x"8B92",'1'&x"8B93",'1'&x"8B94",'1'&x"8B95",'1'&x"8B96",'1'&x"8B97",'1'&x"8B98",'1'&x"8B99",'1'&x"8B9A",'1'&x"8B9B",'1'&x"8B9C",'1'&x"8B9D",'1'&x"8B9E",'1'&x"8B9F",
+--'1'&x"8BA0",'1'&x"8BA1",'1'&x"8BA2",'1'&x"8BA3",'1'&x"8BA4",'1'&x"8BA5",'1'&x"8BA6",'1'&x"8BA7",'1'&x"8BA8",'1'&x"8BA9",'1'&x"8BAA",'1'&x"8BAB",'1'&x"8BAC",'1'&x"8BAD",'1'&x"8BAE",'1'&x"8BAF",
+--'1'&x"8BB0",'1'&x"8BB1",'1'&x"8BB2",'1'&x"8BB3",'1'&x"8BB4",'1'&x"8BB5",'1'&x"8BB6",'1'&x"8BB7",'1'&x"8BB8",'1'&x"8BB9",'1'&x"8BBA",'1'&x"8BBB",'1'&x"8BBC",'1'&x"8BBD",'1'&x"8BBE",'1'&x"8BBF",
+--'1'&x"8BC0",'1'&x"8BC1",'1'&x"8BC2",'1'&x"8BC3",'1'&x"8BC4",'1'&x"8BC5",'1'&x"8BC6",'1'&x"8BC7",'1'&x"8BC8",'1'&x"8BC9",'1'&x"8BCA",'1'&x"8BCB",'1'&x"8BCC",'1'&x"8BCD",'1'&x"8BCE",'1'&x"8BCF",
+--'1'&x"8BD0",'1'&x"8BD1",'1'&x"8BD2",'1'&x"8BD3",'1'&x"8BD4",'1'&x"8BD5",'1'&x"8BD6",'1'&x"8BD7",'1'&x"8BD8",'1'&x"8BD9",'1'&x"8BDA",'1'&x"8BDB",'1'&x"8BDC",'1'&x"8BDD",'1'&x"8BDE",'1'&x"8BDF",
+--'1'&x"8BE0",'1'&x"8BE1",'1'&x"8BE2",'1'&x"8BE3",'1'&x"8BE4",'1'&x"8BE5",'1'&x"8BE6",'1'&x"8BE7",'1'&x"8BE8",'1'&x"8BE9",'1'&x"8BEA",'1'&x"8BEB",'1'&x"8BEC",'1'&x"8BED",'1'&x"8BEE",'1'&x"8BEF",
+--'1'&x"8BF0",'1'&x"8BF1",'1'&x"8BF2",'1'&x"8BF3",'1'&x"8BF4",'1'&x"8BF5",'1'&x"8BF6",'1'&x"8BF7",'1'&x"8BF8",'1'&x"8BF9",'1'&x"8BFA",'1'&x"8BFB",'1'&x"8BFC",'1'&x"8BFD",'1'&x"8BFE",'1'&x"8BFF",
+--'1'&x"8C00",'1'&x"8C01",'1'&x"8C02",'1'&x"8C03",'1'&x"8C04",'1'&x"8C05",'1'&x"8C06",'1'&x"8C07",'1'&x"8C08",'1'&x"8C09",'1'&x"8C0A",'1'&x"8C0B",'1'&x"8C0C",'1'&x"8C0D",'1'&x"8C0E",'1'&x"8C0F",
+--'1'&x"8C10",'1'&x"8C11",'1'&x"8C12",'1'&x"8C13",'1'&x"8C14",'1'&x"8C15",'1'&x"8C16",'1'&x"8C17",'1'&x"8C18",'1'&x"8C19",'1'&x"8C1A",'1'&x"8C1B",'1'&x"8C1C",'1'&x"8C1D",'1'&x"8C1E",'1'&x"8C1F",
+--'1'&x"8C20",'1'&x"8C21",'1'&x"8C22",'1'&x"8C23",'1'&x"8C24",'1'&x"8C25",'1'&x"8C26",'1'&x"8C27",'1'&x"8C28",'1'&x"8C29",'1'&x"8C2A",'1'&x"8C2B",'1'&x"8C2C",'1'&x"8C2D",'1'&x"8C2E",'1'&x"8C2F",
+--'1'&x"8C30",'1'&x"8C31",'1'&x"8C32",'1'&x"8C33",'1'&x"8C34",'1'&x"8C35",'1'&x"8C36",'1'&x"8C37",'1'&x"8C38",'1'&x"8C39",'1'&x"8C3A",'1'&x"8C3B",'1'&x"8C3C",'1'&x"8C3D",'1'&x"8C3E",'1'&x"8C3F",
+--'1'&x"8C40",'1'&x"8C41",'1'&x"8C42",'1'&x"8C43",'1'&x"8C44",'1'&x"8C45",'1'&x"8C46",'1'&x"8C47",'1'&x"8C48",'1'&x"8C49",'1'&x"8C4A",'1'&x"8C4B",'1'&x"8C4C",'1'&x"8C4D",'1'&x"8C4E",'1'&x"8C4F",
+--'1'&x"8C50",'1'&x"8C51",'1'&x"8C52",'1'&x"8C53",'1'&x"8C54",'1'&x"8C55",'1'&x"8C56",'1'&x"8C57",'1'&x"8C58",'1'&x"8C59",'1'&x"8C5A",'1'&x"8C5B",'1'&x"8C5C",'1'&x"8C5D",'1'&x"8C5E",'1'&x"8C5F",
+--'1'&x"8C60",'1'&x"8C61",'1'&x"8C62",'1'&x"8C63",'1'&x"8C64",'1'&x"8C65",'1'&x"8C66",'1'&x"8C67",'1'&x"8C68",'1'&x"8C69",'1'&x"8C6A",'1'&x"8C6B",'1'&x"8C6C",'1'&x"8C6D",'1'&x"8C6E",'1'&x"8C6F",
+--'1'&x"8C70",'1'&x"8C71",'1'&x"8C72",'1'&x"8C73",'1'&x"8C74",'1'&x"8C75",'1'&x"8C76",'1'&x"8C77",'1'&x"8C78",'1'&x"8C79",'1'&x"8C7A",'1'&x"8C7B",'1'&x"8C7C",'1'&x"8C7D",'1'&x"8C7E",'1'&x"8C7F",
+--'1'&x"8C80",'1'&x"8C81",'1'&x"8C82",'1'&x"8C83",'1'&x"8C84",'1'&x"8C85",'1'&x"8C86",'1'&x"8C87",'1'&x"8C88",'1'&x"8C89",'1'&x"8C8A",'1'&x"8C8B",'1'&x"8C8C",'1'&x"8C8D",'1'&x"8C8E",'1'&x"8C8F",
+--'1'&x"8C90",'1'&x"8C91",'1'&x"8C92",'1'&x"8C93",'1'&x"8C94",'1'&x"8C95",'1'&x"8C96",'1'&x"8C97",'1'&x"8C98",'1'&x"8C99",'1'&x"8C9A",'1'&x"8C9B",'1'&x"8C9C",'1'&x"8C9D",'1'&x"8C9E",'1'&x"8C9F",
+--'1'&x"8CA0",'1'&x"8CA1",'1'&x"8CA2",'1'&x"8CA3",'1'&x"8CA4",'1'&x"8CA5",'1'&x"8CA6",'1'&x"8CA7",'1'&x"8CA8",'1'&x"8CA9",'1'&x"8CAA",'1'&x"8CAB",'1'&x"8CAC",'1'&x"8CAD",'1'&x"8CAE",'1'&x"8CAF",
+--'1'&x"8CB0",'1'&x"8CB1",'1'&x"8CB2",'1'&x"8CB3",'1'&x"8CB4",'1'&x"8CB5",'1'&x"8CB6",'1'&x"8CB7",'1'&x"8CB8",'1'&x"8CB9",'1'&x"8CBA",'1'&x"8CBB",'1'&x"8CBC",'1'&x"8CBD",'1'&x"8CBE",'1'&x"8CBF",
+--'1'&x"8CC0",'1'&x"8CC1",'1'&x"8CC2",'1'&x"8CC3",'1'&x"8CC4",'1'&x"8CC5",'1'&x"8CC6",'1'&x"8CC7",'1'&x"8CC8",'1'&x"8CC9",'1'&x"8CCA",'1'&x"8CCB",'1'&x"8CCC",'1'&x"8CCD",'1'&x"8CCE",'1'&x"8CCF",
+--'1'&x"8CD0",'1'&x"8CD1",'1'&x"8CD2",'1'&x"8CD3",'1'&x"8CD4",'1'&x"8CD5",'1'&x"8CD6",'1'&x"8CD7",'1'&x"8CD8",'1'&x"8CD9",'1'&x"8CDA",'1'&x"8CDB",'1'&x"8CDC",'1'&x"8CDD",'1'&x"8CDE",'1'&x"8CDF",
+--'1'&x"8CE0",'1'&x"8CE1",'1'&x"8CE2",'1'&x"8CE3",'1'&x"8CE4",'1'&x"8CE5",'1'&x"8CE6",'1'&x"8CE7",'1'&x"8CE8",'1'&x"8CE9",'1'&x"8CEA",'1'&x"8CEB",'1'&x"8CEC",'1'&x"8CED",'1'&x"8CEE",'1'&x"8CEF",
+--'1'&x"8CF0",'1'&x"8CF1",'1'&x"8CF2",'1'&x"8CF3",'1'&x"8CF4",'1'&x"8CF5",'1'&x"8CF6",'1'&x"8CF7",'1'&x"8CF8",'1'&x"8CF9",'1'&x"8CFA",'1'&x"8CFB",'1'&x"8CFC",'1'&x"8CFD",'1'&x"8CFE",'1'&x"8CFF",
+--'1'&x"8D00",'1'&x"8D01",'1'&x"8D02",'1'&x"8D03",'1'&x"8D04",'1'&x"8D05",'1'&x"8D06",'1'&x"8D07",'1'&x"8D08",'1'&x"8D09",'1'&x"8D0A",'1'&x"8D0B",'1'&x"8D0C",'1'&x"8D0D",'1'&x"8D0E",'1'&x"8D0F",
+--'1'&x"8D10",'1'&x"8D11",'1'&x"8D12",'1'&x"8D13",'1'&x"8D14",'1'&x"8D15",'1'&x"8D16",'1'&x"8D17",'1'&x"8D18",'1'&x"8D19",'1'&x"8D1A",'1'&x"8D1B",'1'&x"8D1C",'1'&x"8D1D",'1'&x"8D1E",'1'&x"8D1F",
+--'1'&x"8D20",'1'&x"8D21",'1'&x"8D22",'1'&x"8D23",'1'&x"8D24",'1'&x"8D25",'1'&x"8D26",'1'&x"8D27",'1'&x"8D28",'1'&x"8D29",'1'&x"8D2A",'1'&x"8D2B",'1'&x"8D2C",'1'&x"8D2D",'1'&x"8D2E",'1'&x"8D2F",
+--'1'&x"8D30",'1'&x"8D31",'1'&x"8D32",'1'&x"8D33",'1'&x"8D34",'1'&x"8D35",'1'&x"8D36",'1'&x"8D37",'1'&x"8D38",'1'&x"8D39",'1'&x"8D3A",'1'&x"8D3B",'1'&x"8D3C",'1'&x"8D3D",'1'&x"8D3E",'1'&x"8D3F",
+--'1'&x"8D40",'1'&x"8D41",'1'&x"8D42",'1'&x"8D43",'1'&x"8D44",'1'&x"8D45",'1'&x"8D46",'1'&x"8D47",'1'&x"8D48",'1'&x"8D49",'1'&x"8D4A",'1'&x"8D4B",'1'&x"8D4C",'1'&x"8D4D",'1'&x"8D4E",'1'&x"8D4F",
+--'1'&x"8D50",'1'&x"8D51",'1'&x"8D52",'1'&x"8D53",'1'&x"8D54",'1'&x"8D55",'1'&x"8D56",'1'&x"8D57",'1'&x"8D58",'1'&x"8D59",'1'&x"8D5A",'1'&x"8D5B",'1'&x"8D5C",'1'&x"8D5D",'1'&x"8D5E",'1'&x"8D5F",
+--'1'&x"8D60",'1'&x"8D61",'1'&x"8D62",'1'&x"8D63",'1'&x"8D64",'1'&x"8D65",'1'&x"8D66",'1'&x"8D67",'1'&x"8D68",'1'&x"8D69",'1'&x"8D6A",'1'&x"8D6B",'1'&x"8D6C",'1'&x"8D6D",'1'&x"8D6E",'1'&x"8D6F",
+--'1'&x"8D70",'1'&x"8D71",'1'&x"8D72",'1'&x"8D73",'1'&x"8D74",'1'&x"8D75",'1'&x"8D76",'1'&x"8D77",'1'&x"8D78",'1'&x"8D79",'1'&x"8D7A",'1'&x"8D7B",'1'&x"8D7C",'1'&x"8D7D",'1'&x"8D7E",'1'&x"8D7F",
+--'1'&x"8D80",'1'&x"8D81",'1'&x"8D82",'1'&x"8D83",'1'&x"8D84",'1'&x"8D85",'1'&x"8D86",'1'&x"8D87",'1'&x"8D88",'1'&x"8D89",'1'&x"8D8A",'1'&x"8D8B",'1'&x"8D8C",'1'&x"8D8D",'1'&x"8D8E",'1'&x"8D8F",
+--'1'&x"8D90",'1'&x"8D91",'1'&x"8D92",'1'&x"8D93",'1'&x"8D94",'1'&x"8D95",'1'&x"8D96",'1'&x"8D97",'1'&x"8D98",'1'&x"8D99",'1'&x"8D9A",'1'&x"8D9B",'1'&x"8D9C",'1'&x"8D9D",'1'&x"8D9E",'1'&x"8D9F",
+--'1'&x"8DA0",'1'&x"8DA1",'1'&x"8DA2",'1'&x"8DA3",'1'&x"8DA4",'1'&x"8DA5",'1'&x"8DA6",'1'&x"8DA7",'1'&x"8DA8",'1'&x"8DA9",'1'&x"8DAA",'1'&x"8DAB",'1'&x"8DAC",'1'&x"8DAD",'1'&x"8DAE",'1'&x"8DAF",
+--'1'&x"8DB0",'1'&x"8DB1",'1'&x"8DB2",'1'&x"8DB3",'1'&x"8DB4",'1'&x"8DB5",'1'&x"8DB6",'1'&x"8DB7",'1'&x"8DB8",'1'&x"8DB9",'1'&x"8DBA",'1'&x"8DBB",'1'&x"8DBC",'1'&x"8DBD",'1'&x"8DBE",'1'&x"8DBF",
+--'1'&x"8DC0",'1'&x"8DC1",'1'&x"8DC2",'1'&x"8DC3",'1'&x"8DC4",'1'&x"8DC5",'1'&x"8DC6",'1'&x"8DC7",'1'&x"8DC8",'1'&x"8DC9",'1'&x"8DCA",'1'&x"8DCB",'1'&x"8DCC",'1'&x"8DCD",'1'&x"8DCE",'1'&x"8DCF",
+--'1'&x"8DD0",'1'&x"8DD1",'1'&x"8DD2",'1'&x"8DD3",'1'&x"8DD4",'1'&x"8DD5",'1'&x"8DD6",'1'&x"8DD7",'1'&x"8DD8",'1'&x"8DD9",'1'&x"8DDA",'1'&x"8DDB",'1'&x"8DDC",'1'&x"8DDD",'1'&x"8DDE",'1'&x"8DDF",
+--'1'&x"8DE0",'1'&x"8DE1",'1'&x"8DE2",'1'&x"8DE3",'1'&x"8DE4",'1'&x"8DE5",'1'&x"8DE6",'1'&x"8DE7",'1'&x"8DE8",'1'&x"8DE9",'1'&x"8DEA",'1'&x"8DEB",'1'&x"8DEC",'1'&x"8DED",'1'&x"8DEE",'1'&x"8DEF",
+--'1'&x"8DF0",'1'&x"8DF1",'1'&x"8DF2",'1'&x"8DF3",'1'&x"8DF4",'1'&x"8DF5",'1'&x"8DF6",'1'&x"8DF7",'1'&x"8DF8",'1'&x"8DF9",'1'&x"8DFA",'1'&x"8DFB",'1'&x"8DFC",'1'&x"8DFD",'1'&x"8DFE",'1'&x"8DFF",
+--'1'&x"8E00",'1'&x"8E01",'1'&x"8E02",'1'&x"8E03",'1'&x"8E04",'1'&x"8E05",'1'&x"8E06",'1'&x"8E07",'1'&x"8E08",'1'&x"8E09",'1'&x"8E0A",'1'&x"8E0B",'1'&x"8E0C",'1'&x"8E0D",'1'&x"8E0E",'1'&x"8E0F",
+--'1'&x"8E10",'1'&x"8E11",'1'&x"8E12",'1'&x"8E13",'1'&x"8E14",'1'&x"8E15",'1'&x"8E16",'1'&x"8E17",'1'&x"8E18",'1'&x"8E19",'1'&x"8E1A",'1'&x"8E1B",'1'&x"8E1C",'1'&x"8E1D",'1'&x"8E1E",'1'&x"8E1F",
+--'1'&x"8E20",'1'&x"8E21",'1'&x"8E22",'1'&x"8E23",'1'&x"8E24",'1'&x"8E25",'1'&x"8E26",'1'&x"8E27",'1'&x"8E28",'1'&x"8E29",'1'&x"8E2A",'1'&x"8E2B",'1'&x"8E2C",'1'&x"8E2D",'1'&x"8E2E",'1'&x"8E2F",
+--'1'&x"8E30",'1'&x"8E31",'1'&x"8E32",'1'&x"8E33",'1'&x"8E34",'1'&x"8E35",'1'&x"8E36",'1'&x"8E37",'1'&x"8E38",'1'&x"8E39",'1'&x"8E3A",'1'&x"8E3B",'1'&x"8E3C",'1'&x"8E3D",'1'&x"8E3E",'1'&x"8E3F",
+--'1'&x"8E40",'1'&x"8E41",'1'&x"8E42",'1'&x"8E43",'1'&x"8E44",'1'&x"8E45",'1'&x"8E46",'1'&x"8E47",'1'&x"8E48",'1'&x"8E49",'1'&x"8E4A",'1'&x"8E4B",'1'&x"8E4C",'1'&x"8E4D",'1'&x"8E4E",'1'&x"8E4F",
+--'1'&x"8E50",'1'&x"8E51",'1'&x"8E52",'1'&x"8E53",'1'&x"8E54",'1'&x"8E55",'1'&x"8E56",'1'&x"8E57",'1'&x"8E58",'1'&x"8E59",'1'&x"8E5A",'1'&x"8E5B",'1'&x"8E5C",'1'&x"8E5D",'1'&x"8E5E",'1'&x"8E5F",
+--'1'&x"8E60",'1'&x"8E61",'1'&x"8E62",'1'&x"8E63",'1'&x"8E64",'1'&x"8E65",'1'&x"8E66",'1'&x"8E67",'1'&x"8E68",'1'&x"8E69",'1'&x"8E6A",'1'&x"8E6B",'1'&x"8E6C",'1'&x"8E6D",'1'&x"8E6E",'1'&x"8E6F",
+--'1'&x"8E70",'1'&x"8E71",'1'&x"8E72",'1'&x"8E73",'1'&x"8E74",'1'&x"8E75",'1'&x"8E76",'1'&x"8E77",'1'&x"8E78",'1'&x"8E79",'1'&x"8E7A",'1'&x"8E7B",'1'&x"8E7C",'1'&x"8E7D",'1'&x"8E7E",'1'&x"8E7F",
+--'1'&x"8E80",'1'&x"8E81",'1'&x"8E82",'1'&x"8E83",'1'&x"8E84",'1'&x"8E85",'1'&x"8E86",'1'&x"8E87",'1'&x"8E88",'1'&x"8E89",'1'&x"8E8A",'1'&x"8E8B",'1'&x"8E8C",'1'&x"8E8D",'1'&x"8E8E",'1'&x"8E8F",
+--'1'&x"8E90",'1'&x"8E91",'1'&x"8E92",'1'&x"8E93",'1'&x"8E94",'1'&x"8E95",'1'&x"8E96",'1'&x"8E97",'1'&x"8E98",'1'&x"8E99",'1'&x"8E9A",'1'&x"8E9B",'1'&x"8E9C",'1'&x"8E9D",'1'&x"8E9E",'1'&x"8E9F",
+--'1'&x"8EA0",'1'&x"8EA1",'1'&x"8EA2",'1'&x"8EA3",'1'&x"8EA4",'1'&x"8EA5",'1'&x"8EA6",'1'&x"8EA7",'1'&x"8EA8",'1'&x"8EA9",'1'&x"8EAA",'1'&x"8EAB",'1'&x"8EAC",'1'&x"8EAD",'1'&x"8EAE",'1'&x"8EAF",
+--'1'&x"8EB0",'1'&x"8EB1",'1'&x"8EB2",'1'&x"8EB3",'1'&x"8EB4",'1'&x"8EB5",'1'&x"8EB6",'1'&x"8EB7",'1'&x"8EB8",'1'&x"8EB9",'1'&x"8EBA",'1'&x"8EBB",'1'&x"8EBC",'1'&x"8EBD",'1'&x"8EBE",'1'&x"8EBF",
+--'1'&x"8EC0",'1'&x"8EC1",'1'&x"8EC2",'1'&x"8EC3",'1'&x"8EC4",'1'&x"8EC5",'1'&x"8EC6",'1'&x"8EC7",'1'&x"8EC8",'1'&x"8EC9",'1'&x"8ECA",'1'&x"8ECB",'1'&x"8ECC",'1'&x"8ECD",'1'&x"8ECE",'1'&x"8ECF",
+--'1'&x"8ED0",'1'&x"8ED1",'1'&x"8ED2",'1'&x"8ED3",'1'&x"8ED4",'1'&x"8ED5",'1'&x"8ED6",'1'&x"8ED7",'1'&x"8ED8",'1'&x"8ED9",'1'&x"8EDA",'1'&x"8EDB",'1'&x"8EDC",'1'&x"8EDD",'1'&x"8EDE",'1'&x"8EDF",
+--'1'&x"8EE0",'1'&x"8EE1",'1'&x"8EE2",'1'&x"8EE3",'1'&x"8EE4",'1'&x"8EE5",'1'&x"8EE6",'1'&x"8EE7",'1'&x"8EE8",'1'&x"8EE9",'1'&x"8EEA",'1'&x"8EEB",'1'&x"8EEC",'1'&x"8EED",'1'&x"8EEE",'1'&x"8EEF",
+--'1'&x"8EF0",'1'&x"8EF1",'1'&x"8EF2",'1'&x"8EF3",'1'&x"8EF4",'1'&x"8EF5",'1'&x"8EF6",'1'&x"8EF7",'1'&x"8EF8",'1'&x"8EF9",'1'&x"8EFA",'1'&x"8EFB",'1'&x"8EFC",'1'&x"8EFD",'1'&x"8EFE",'1'&x"8EFF",
+--'1'&x"8F00",'1'&x"8F01",'1'&x"8F02",'1'&x"8F03",'1'&x"8F04",'1'&x"8F05",'1'&x"8F06",'1'&x"8F07",'1'&x"8F08",'1'&x"8F09",'1'&x"8F0A",'1'&x"8F0B",'1'&x"8F0C",'1'&x"8F0D",'1'&x"8F0E",'1'&x"8F0F",
+--'1'&x"8F10",'1'&x"8F11",'1'&x"8F12",'1'&x"8F13",'1'&x"8F14",'1'&x"8F15",'1'&x"8F16",'1'&x"8F17",'1'&x"8F18",'1'&x"8F19",'1'&x"8F1A",'1'&x"8F1B",'1'&x"8F1C",'1'&x"8F1D",'1'&x"8F1E",'1'&x"8F1F",
+--'1'&x"8F20",'1'&x"8F21",'1'&x"8F22",'1'&x"8F23",'1'&x"8F24",'1'&x"8F25",'1'&x"8F26",'1'&x"8F27",'1'&x"8F28",'1'&x"8F29",'1'&x"8F2A",'1'&x"8F2B",'1'&x"8F2C",'1'&x"8F2D",'1'&x"8F2E",'1'&x"8F2F",
+--'1'&x"8F30",'1'&x"8F31",'1'&x"8F32",'1'&x"8F33",'1'&x"8F34",'1'&x"8F35",'1'&x"8F36",'1'&x"8F37",'1'&x"8F38",'1'&x"8F39",'1'&x"8F3A",'1'&x"8F3B",'1'&x"8F3C",'1'&x"8F3D",'1'&x"8F3E",'1'&x"8F3F",
+--'1'&x"8F40",'1'&x"8F41",'1'&x"8F42",'1'&x"8F43",'1'&x"8F44",'1'&x"8F45",'1'&x"8F46",'1'&x"8F47",'1'&x"8F48",'1'&x"8F49",'1'&x"8F4A",'1'&x"8F4B",'1'&x"8F4C",'1'&x"8F4D",'1'&x"8F4E",'1'&x"8F4F",
+--'1'&x"8F50",'1'&x"8F51",'1'&x"8F52",'1'&x"8F53",'1'&x"8F54",'1'&x"8F55",'1'&x"8F56",'1'&x"8F57",'1'&x"8F58",'1'&x"8F59",'1'&x"8F5A",'1'&x"8F5B",'1'&x"8F5C",'1'&x"8F5D",'1'&x"8F5E",'1'&x"8F5F",
+--'1'&x"8F60",'1'&x"8F61",'1'&x"8F62",'1'&x"8F63",'1'&x"8F64",'1'&x"8F65",'1'&x"8F66",'1'&x"8F67",'1'&x"8F68",'1'&x"8F69",'1'&x"8F6A",'1'&x"8F6B",'1'&x"8F6C",'1'&x"8F6D",'1'&x"8F6E",'1'&x"8F6F",
+--'1'&x"8F70",'1'&x"8F71",'1'&x"8F72",'1'&x"8F73",'1'&x"8F74",'1'&x"8F75",'1'&x"8F76",'1'&x"8F77",'1'&x"8F78",'1'&x"8F79",'1'&x"8F7A",'1'&x"8F7B",'1'&x"8F7C",'1'&x"8F7D",'1'&x"8F7E",'1'&x"8F7F",
+--'1'&x"8F80",'1'&x"8F81",'1'&x"8F82",'1'&x"8F83",'1'&x"8F84",'1'&x"8F85",'1'&x"8F86",'1'&x"8F87",'1'&x"8F88",'1'&x"8F89",'1'&x"8F8A",'1'&x"8F8B",'1'&x"8F8C",'1'&x"8F8D",'1'&x"8F8E",'1'&x"8F8F",
+--'1'&x"8F90",'1'&x"8F91",'1'&x"8F92",'1'&x"8F93",'1'&x"8F94",'1'&x"8F95",'1'&x"8F96",'1'&x"8F97",'1'&x"8F98",'1'&x"8F99",'1'&x"8F9A",'1'&x"8F9B",'1'&x"8F9C",'1'&x"8F9D",'1'&x"8F9E",'1'&x"8F9F",
+--'1'&x"8FA0",'1'&x"8FA1",'1'&x"8FA2",'1'&x"8FA3",'1'&x"8FA4",'1'&x"8FA5",'1'&x"8FA6",'1'&x"8FA7",'1'&x"8FA8",'1'&x"8FA9",'1'&x"8FAA",'1'&x"8FAB",'1'&x"8FAC",'1'&x"8FAD",'1'&x"8FAE",'1'&x"8FAF",
+--'1'&x"8FB0",'1'&x"8FB1",'1'&x"8FB2",'1'&x"8FB3",'1'&x"8FB4",'1'&x"8FB5",'1'&x"8FB6",'1'&x"8FB7",'1'&x"8FB8",'1'&x"8FB9",'1'&x"8FBA",'1'&x"8FBB",'1'&x"8FBC",'1'&x"8FBD",'1'&x"8FBE",'1'&x"8FBF",
+--'1'&x"8FC0",'1'&x"8FC1",'1'&x"8FC2",'1'&x"8FC3",'1'&x"8FC4",'1'&x"8FC5",'1'&x"8FC6",'1'&x"8FC7",'1'&x"8FC8",'1'&x"8FC9",'1'&x"8FCA",'1'&x"8FCB",'1'&x"8FCC",'1'&x"8FCD",'1'&x"8FCE",'1'&x"8FCF",
+--'1'&x"8FD0",'1'&x"8FD1",'1'&x"8FD2",'1'&x"8FD3",'1'&x"8FD4",'1'&x"8FD5",'1'&x"8FD6",'1'&x"8FD7",'1'&x"8FD8",'1'&x"8FD9",'1'&x"8FDA",'1'&x"8FDB",'1'&x"8FDC",'1'&x"8FDD",'1'&x"8FDE",'1'&x"8FDF",
+--'1'&x"8FE0",'1'&x"8FE1",'1'&x"8FE2",'1'&x"8FE3",'1'&x"8FE4",'1'&x"8FE5",'1'&x"8FE6",'1'&x"8FE7",'1'&x"8FE8",'1'&x"8FE9",'1'&x"8FEA",'1'&x"8FEB",'1'&x"8FEC",'1'&x"8FED",'1'&x"8FEE",'1'&x"8FEF",
+--'1'&x"8FF0",'1'&x"8FF1",'1'&x"8FF2",'1'&x"8FF3",'1'&x"8FF4",'1'&x"8FF5",'1'&x"8FF6",'1'&x"8FF7",'1'&x"8FF8",'1'&x"8FF9",'1'&x"8FFA",'1'&x"8FFB",'1'&x"8FFC",'1'&x"8FFD",'1'&x"8FFE",'1'&x"8FFF",
+--'1'&x"9000",'1'&x"9001",'1'&x"9002",'1'&x"9003",'1'&x"9004",'1'&x"9005",'1'&x"9006",'1'&x"9007",'1'&x"9008",'1'&x"9009",'1'&x"900A",'1'&x"900B",'1'&x"900C",'1'&x"900D",'1'&x"900E",'1'&x"900F",
+--'1'&x"9010",'1'&x"9011",'1'&x"9012",'1'&x"9013",'1'&x"9014",'1'&x"9015",'1'&x"9016",'1'&x"9017",'1'&x"9018",'1'&x"9019",'1'&x"901A",'1'&x"901B",'1'&x"901C",'1'&x"901D",'1'&x"901E",'1'&x"901F",
+--'1'&x"9020",'1'&x"9021",'1'&x"9022",'1'&x"9023",'1'&x"9024",'1'&x"9025",'1'&x"9026",'1'&x"9027",'1'&x"9028",'1'&x"9029",'1'&x"902A",'1'&x"902B",'1'&x"902C",'1'&x"902D",'1'&x"902E",'1'&x"902F",
+--'1'&x"9030",'1'&x"9031",'1'&x"9032",'1'&x"9033",'1'&x"9034",'1'&x"9035",'1'&x"9036",'1'&x"9037",'1'&x"9038",'1'&x"9039",'1'&x"903A",'1'&x"903B",'1'&x"903C",'1'&x"903D",'1'&x"903E",'1'&x"903F",
+--'1'&x"9040",'1'&x"9041",'1'&x"9042",'1'&x"9043",'1'&x"9044",'1'&x"9045",'1'&x"9046",'1'&x"9047",'1'&x"9048",'1'&x"9049",'1'&x"904A",'1'&x"904B",'1'&x"904C",'1'&x"904D",'1'&x"904E",'1'&x"904F",
+--'1'&x"9050",'1'&x"9051",'1'&x"9052",'1'&x"9053",'1'&x"9054",'1'&x"9055",'1'&x"9056",'1'&x"9057",'1'&x"9058",'1'&x"9059",'1'&x"905A",'1'&x"905B",'1'&x"905C",'1'&x"905D",'1'&x"905E",'1'&x"905F",
+--'1'&x"9060",'1'&x"9061",'1'&x"9062",'1'&x"9063",'1'&x"9064",'1'&x"9065",'1'&x"9066",'1'&x"9067",'1'&x"9068",'1'&x"9069",'1'&x"906A",'1'&x"906B",'1'&x"906C",'1'&x"906D",'1'&x"906E",'1'&x"906F",
+--'1'&x"9070",'1'&x"9071",'1'&x"9072",'1'&x"9073",'1'&x"9074",'1'&x"9075",'1'&x"9076",'1'&x"9077",'1'&x"9078",'1'&x"9079",'1'&x"907A",'1'&x"907B",'1'&x"907C",'1'&x"907D",'1'&x"907E",'1'&x"907F",
+--'1'&x"9080",'1'&x"9081",'1'&x"9082",'1'&x"9083",'1'&x"9084",'1'&x"9085",'1'&x"9086",'1'&x"9087",'1'&x"9088",'1'&x"9089",'1'&x"908A",'1'&x"908B",'1'&x"908C",'1'&x"908D",'1'&x"908E",'1'&x"908F",
+--'1'&x"9090",'1'&x"9091",'1'&x"9092",'1'&x"9093",'1'&x"9094",'1'&x"9095",'1'&x"9096",'1'&x"9097",'1'&x"9098",'1'&x"9099",'1'&x"909A",'1'&x"909B",'1'&x"909C",'1'&x"909D",'1'&x"909E",'1'&x"909F",
+--'1'&x"90A0",'1'&x"90A1",'1'&x"90A2",'1'&x"90A3",'1'&x"90A4",'1'&x"90A5",'1'&x"90A6",'1'&x"90A7",'1'&x"90A8",'1'&x"90A9",'1'&x"90AA",'1'&x"90AB",'1'&x"90AC",'1'&x"90AD",'1'&x"90AE",'1'&x"90AF",
+--'1'&x"90B0",'1'&x"90B1",'1'&x"90B2",'1'&x"90B3",'1'&x"90B4",'1'&x"90B5",'1'&x"90B6",'1'&x"90B7",'1'&x"90B8",'1'&x"90B9",'1'&x"90BA",'1'&x"90BB",'1'&x"90BC",'1'&x"90BD",'1'&x"90BE",'1'&x"90BF",
+--'1'&x"90C0",'1'&x"90C1",'1'&x"90C2",'1'&x"90C3",'1'&x"90C4",'1'&x"90C5",'1'&x"90C6",'1'&x"90C7",'1'&x"90C8",'1'&x"90C9",'1'&x"90CA",'1'&x"90CB",'1'&x"90CC",'1'&x"90CD",'1'&x"90CE",'1'&x"90CF",
+--'1'&x"90D0",'1'&x"90D1",'1'&x"90D2",'1'&x"90D3",'1'&x"90D4",'1'&x"90D5",'1'&x"90D6",'1'&x"90D7",'1'&x"90D8",'1'&x"90D9",'1'&x"90DA",'1'&x"90DB",'1'&x"90DC",'1'&x"90DD",'1'&x"90DE",'1'&x"90DF",
+--'1'&x"90E0",'1'&x"90E1",'1'&x"90E2",'1'&x"90E3",'1'&x"90E4",'1'&x"90E5",'1'&x"90E6",'1'&x"90E7",'1'&x"90E8",'1'&x"90E9",'1'&x"90EA",'1'&x"90EB",'1'&x"90EC",'1'&x"90ED",'1'&x"90EE",'1'&x"90EF",
+--'1'&x"90F0",'1'&x"90F1",'1'&x"90F2",'1'&x"90F3",'1'&x"90F4",'1'&x"90F5",'1'&x"90F6",'1'&x"90F7",'1'&x"90F8",'1'&x"90F9",'1'&x"90FA",'1'&x"90FB",'1'&x"90FC",'1'&x"90FD",'1'&x"90FE",'1'&x"90FF",
+--'1'&x"9100",'1'&x"9101",'1'&x"9102",'1'&x"9103",'1'&x"9104",'1'&x"9105",'1'&x"9106",'1'&x"9107",'1'&x"9108",'1'&x"9109",'1'&x"910A",'1'&x"910B",'1'&x"910C",'1'&x"910D",'1'&x"910E",'1'&x"910F",
+--'1'&x"9110",'1'&x"9111",'1'&x"9112",'1'&x"9113",'1'&x"9114",'1'&x"9115",'1'&x"9116",'1'&x"9117",'1'&x"9118",'1'&x"9119",'1'&x"911A",'1'&x"911B",'1'&x"911C",'1'&x"911D",'1'&x"911E",'1'&x"911F",
+--'1'&x"9120",'1'&x"9121",'1'&x"9122",'1'&x"9123",'1'&x"9124",'1'&x"9125",'1'&x"9126",'1'&x"9127",'1'&x"9128",'1'&x"9129",'1'&x"912A",'1'&x"912B",'1'&x"912C",'1'&x"912D",'1'&x"912E",'1'&x"912F",
+--'1'&x"9130",'1'&x"9131",'1'&x"9132",'1'&x"9133",'1'&x"9134",'1'&x"9135",'1'&x"9136",'1'&x"9137",'1'&x"9138",'1'&x"9139",'1'&x"913A",'1'&x"913B",'1'&x"913C",'1'&x"913D",'1'&x"913E",'1'&x"913F",
+--'1'&x"9140",'1'&x"9141",'1'&x"9142",'1'&x"9143",'1'&x"9144",'1'&x"9145",'1'&x"9146",'1'&x"9147",'1'&x"9148",'1'&x"9149",'1'&x"914A",'1'&x"914B",'1'&x"914C",'1'&x"914D",'1'&x"914E",'1'&x"914F",
+--'1'&x"9150",'1'&x"9151",'1'&x"9152",'1'&x"9153",'1'&x"9154",'1'&x"9155",'1'&x"9156",'1'&x"9157",'1'&x"9158",'1'&x"9159",'1'&x"915A",'1'&x"915B",'1'&x"915C",'1'&x"915D",'1'&x"915E",'1'&x"915F",
+--'1'&x"9160",'1'&x"9161",'1'&x"9162",'1'&x"9163",'1'&x"9164",'1'&x"9165",'1'&x"9166",'1'&x"9167",'1'&x"9168",'1'&x"9169",'1'&x"916A",'1'&x"916B",'1'&x"916C",'1'&x"916D",'1'&x"916E",'1'&x"916F",
+--'1'&x"9170",'1'&x"9171",'1'&x"9172",'1'&x"9173",'1'&x"9174",'1'&x"9175",'1'&x"9176",'1'&x"9177",'1'&x"9178",'1'&x"9179",'1'&x"917A",'1'&x"917B",'1'&x"917C",'1'&x"917D",'1'&x"917E",'1'&x"917F",
+--'1'&x"9180",'1'&x"9181",'1'&x"9182",'1'&x"9183",'1'&x"9184",'1'&x"9185",'1'&x"9186",'1'&x"9187",'1'&x"9188",'1'&x"9189",'1'&x"918A",'1'&x"918B",'1'&x"918C",'1'&x"918D",'1'&x"918E",'1'&x"918F",
+--'1'&x"9190",'1'&x"9191",'1'&x"9192",'1'&x"9193",'1'&x"9194",'1'&x"9195",'1'&x"9196",'1'&x"9197",'1'&x"9198",'1'&x"9199",'1'&x"919A",'1'&x"919B",'1'&x"919C",'1'&x"919D",'1'&x"919E",'1'&x"919F",
+--'1'&x"91A0",'1'&x"91A1",'1'&x"91A2",'1'&x"91A3",'1'&x"91A4",'1'&x"91A5",'1'&x"91A6",'1'&x"91A7",'1'&x"91A8",'1'&x"91A9",'1'&x"91AA",'1'&x"91AB",'1'&x"91AC",'1'&x"91AD",'1'&x"91AE",'1'&x"91AF",
+--'1'&x"91B0",'1'&x"91B1",'1'&x"91B2",'1'&x"91B3",'1'&x"91B4",'1'&x"91B5",'1'&x"91B6",'1'&x"91B7",'1'&x"91B8",'1'&x"91B9",'1'&x"91BA",'1'&x"91BB",'1'&x"91BC",'1'&x"91BD",'1'&x"91BE",'1'&x"91BF",
+--'1'&x"91C0",'1'&x"91C1",'1'&x"91C2",'1'&x"91C3",'1'&x"91C4",'1'&x"91C5",'1'&x"91C6",'1'&x"91C7",'1'&x"91C8",'1'&x"91C9",'1'&x"91CA",'1'&x"91CB",'1'&x"91CC",'1'&x"91CD",'1'&x"91CE",'1'&x"91CF",
+--'1'&x"91D0",'1'&x"91D1",'1'&x"91D2",'1'&x"91D3",'1'&x"91D4",'1'&x"91D5",'1'&x"91D6",'1'&x"91D7",'1'&x"91D8",'1'&x"91D9",'1'&x"91DA",'1'&x"91DB",'1'&x"91DC",'1'&x"91DD",'1'&x"91DE",'1'&x"91DF",
+--'1'&x"91E0",'1'&x"91E1",'1'&x"91E2",'1'&x"91E3",'1'&x"91E4",'1'&x"91E5",'1'&x"91E6",'1'&x"91E7",'1'&x"91E8",'1'&x"91E9",'1'&x"91EA",'1'&x"91EB",'1'&x"91EC",'1'&x"91ED",'1'&x"91EE",'1'&x"91EF",
+--'1'&x"91F0",'1'&x"91F1",'1'&x"91F2",'1'&x"91F3",'1'&x"91F4",'1'&x"91F5",'1'&x"91F6",'1'&x"91F7",'1'&x"91F8",'1'&x"91F9",'1'&x"91FA",'1'&x"91FB",'1'&x"91FC",'1'&x"91FD",'1'&x"91FE",'1'&x"91FF",
+--'1'&x"9200",'1'&x"9201",'1'&x"9202",'1'&x"9203",'1'&x"9204",'1'&x"9205",'1'&x"9206",'1'&x"9207",'1'&x"9208",'1'&x"9209",'1'&x"920A",'1'&x"920B",'1'&x"920C",'1'&x"920D",'1'&x"920E",'1'&x"920F",
+--'1'&x"9210",'1'&x"9211",'1'&x"9212",'1'&x"9213",'1'&x"9214",'1'&x"9215",'1'&x"9216",'1'&x"9217",'1'&x"9218",'1'&x"9219",'1'&x"921A",'1'&x"921B",'1'&x"921C",'1'&x"921D",'1'&x"921E",'1'&x"921F",
+--'1'&x"9220",'1'&x"9221",'1'&x"9222",'1'&x"9223",'1'&x"9224",'1'&x"9225",'1'&x"9226",'1'&x"9227",'1'&x"9228",'1'&x"9229",'1'&x"922A",'1'&x"922B",'1'&x"922C",'1'&x"922D",'1'&x"922E",'1'&x"922F",
+--'1'&x"9230",'1'&x"9231",'1'&x"9232",'1'&x"9233",'1'&x"9234",'1'&x"9235",'1'&x"9236",'1'&x"9237",'1'&x"9238",'1'&x"9239",'1'&x"923A",'1'&x"923B",'1'&x"923C",'1'&x"923D",'1'&x"923E",'1'&x"923F",
+--'1'&x"9240",'1'&x"9241",'1'&x"9242",'1'&x"9243",'1'&x"9244",'1'&x"9245",'1'&x"9246",'1'&x"9247",'1'&x"9248",'1'&x"9249",'1'&x"924A",'1'&x"924B",'1'&x"924C",'1'&x"924D",'1'&x"924E",'1'&x"924F",
+--'1'&x"9250",'1'&x"9251",'1'&x"9252",'1'&x"9253",'1'&x"9254",'1'&x"9255",'1'&x"9256",'1'&x"9257",'1'&x"9258",'1'&x"9259",'1'&x"925A",'1'&x"925B",'1'&x"925C",'1'&x"925D",'1'&x"925E",'1'&x"925F",
+--'1'&x"9260",'1'&x"9261",'1'&x"9262",'1'&x"9263",'1'&x"9264",'1'&x"9265",'1'&x"9266",'1'&x"9267",'1'&x"9268",'1'&x"9269",'1'&x"926A",'1'&x"926B",'1'&x"926C",'1'&x"926D",'1'&x"926E",'1'&x"926F",
+--'1'&x"9270",'1'&x"9271",'1'&x"9272",'1'&x"9273",'1'&x"9274",'1'&x"9275",'1'&x"9276",'1'&x"9277",'1'&x"9278",'1'&x"9279",'1'&x"927A",'1'&x"927B",'1'&x"927C",'1'&x"927D",'1'&x"927E",'1'&x"927F",
+--'1'&x"9280",'1'&x"9281",'1'&x"9282",'1'&x"9283",'1'&x"9284",'1'&x"9285",'1'&x"9286",'1'&x"9287",'1'&x"9288",'1'&x"9289",'1'&x"928A",'1'&x"928B",'1'&x"928C",'1'&x"928D",'1'&x"928E",'1'&x"928F",
+--'1'&x"9290",'1'&x"9291",'1'&x"9292",'1'&x"9293",'1'&x"9294",'1'&x"9295",'1'&x"9296",'1'&x"9297",'1'&x"9298",'1'&x"9299",'1'&x"929A",'1'&x"929B",'1'&x"929C",'1'&x"929D",'1'&x"929E",'1'&x"929F",
+--'1'&x"92A0",'1'&x"92A1",'1'&x"92A2",'1'&x"92A3",'1'&x"92A4",'1'&x"92A5",'1'&x"92A6",'1'&x"92A7",'1'&x"92A8",'1'&x"92A9",'1'&x"92AA",'1'&x"92AB",'1'&x"92AC",'1'&x"92AD",'1'&x"92AE",'1'&x"92AF",
+--'1'&x"92B0",'1'&x"92B1",'1'&x"92B2",'1'&x"92B3",'1'&x"92B4",'1'&x"92B5",'1'&x"92B6",'1'&x"92B7",'1'&x"92B8",'1'&x"92B9",'1'&x"92BA",'1'&x"92BB",'1'&x"92BC",'1'&x"92BD",'1'&x"92BE",'1'&x"92BF",
+--'1'&x"92C0",'1'&x"92C1",'1'&x"92C2",'1'&x"92C3",'1'&x"92C4",'1'&x"92C5",'1'&x"92C6",'1'&x"92C7",'1'&x"92C8",'1'&x"92C9",'1'&x"92CA",'1'&x"92CB",'1'&x"92CC",'1'&x"92CD",'1'&x"92CE",'1'&x"92CF",
+--'1'&x"92D0",'1'&x"92D1",'1'&x"92D2",'1'&x"92D3",'1'&x"92D4",'1'&x"92D5",'1'&x"92D6",'1'&x"92D7",'1'&x"92D8",'1'&x"92D9",'1'&x"92DA",'1'&x"92DB",'1'&x"92DC",'1'&x"92DD",'1'&x"92DE",'1'&x"92DF",
+--'1'&x"92E0",'1'&x"92E1",'1'&x"92E2",'1'&x"92E3",'1'&x"92E4",'1'&x"92E5",'1'&x"92E6",'1'&x"92E7",'1'&x"92E8",'1'&x"92E9",'1'&x"92EA",'1'&x"92EB",'1'&x"92EC",'1'&x"92ED",'1'&x"92EE",'1'&x"92EF",
+--'1'&x"92F0",'1'&x"92F1",'1'&x"92F2",'1'&x"92F3",'1'&x"92F4",'1'&x"92F5",'1'&x"92F6",'1'&x"92F7",'1'&x"92F8",'1'&x"92F9",'1'&x"92FA",'1'&x"92FB",'1'&x"92FC",'1'&x"92FD",'1'&x"92FE",'1'&x"92FF",
+--'1'&x"9300",'1'&x"9301",'1'&x"9302",'1'&x"9303",'1'&x"9304",'1'&x"9305",'1'&x"9306",'1'&x"9307",'1'&x"9308",'1'&x"9309",'1'&x"930A",'1'&x"930B",'1'&x"930C",'1'&x"930D",'1'&x"930E",'1'&x"930F",
+--'1'&x"9310",'1'&x"9311",'1'&x"9312",'1'&x"9313",'1'&x"9314",'1'&x"9315",'1'&x"9316",'1'&x"9317",'1'&x"9318",'1'&x"9319",'1'&x"931A",'1'&x"931B",'1'&x"931C",'1'&x"931D",'1'&x"931E",'1'&x"931F",
+--'1'&x"9320",'1'&x"9321",'1'&x"9322",'1'&x"9323",'1'&x"9324",'1'&x"9325",'1'&x"9326",'1'&x"9327",'1'&x"9328",'1'&x"9329",'1'&x"932A",'1'&x"932B",'1'&x"932C",'1'&x"932D",'1'&x"932E",'1'&x"932F",
+--'1'&x"9330",'1'&x"9331",'1'&x"9332",'1'&x"9333",'1'&x"9334",'1'&x"9335",'1'&x"9336",'1'&x"9337",'1'&x"9338",'1'&x"9339",'1'&x"933A",'1'&x"933B",'1'&x"933C",'1'&x"933D",'1'&x"933E",'1'&x"933F",
+--'1'&x"9340",'1'&x"9341",'1'&x"9342",'1'&x"9343",'1'&x"9344",'1'&x"9345",'1'&x"9346",'1'&x"9347",'1'&x"9348",'1'&x"9349",'1'&x"934A",'1'&x"934B",'1'&x"934C",'1'&x"934D",'1'&x"934E",'1'&x"934F",
+--'1'&x"9350",'1'&x"9351",'1'&x"9352",'1'&x"9353",'1'&x"9354",'1'&x"9355",'1'&x"9356",'1'&x"9357",'1'&x"9358",'1'&x"9359",'1'&x"935A",'1'&x"935B",'1'&x"935C",'1'&x"935D",'1'&x"935E",'1'&x"935F",
+--'1'&x"9360",'1'&x"9361",'1'&x"9362",'1'&x"9363",'1'&x"9364",'1'&x"9365",'1'&x"9366",'1'&x"9367",'1'&x"9368",'1'&x"9369",'1'&x"936A",'1'&x"936B",'1'&x"936C",'1'&x"936D",'1'&x"936E",'1'&x"936F",
+--'1'&x"9370",'1'&x"9371",'1'&x"9372",'1'&x"9373",'1'&x"9374",'1'&x"9375",'1'&x"9376",'1'&x"9377",'1'&x"9378",'1'&x"9379",'1'&x"937A",'1'&x"937B",'1'&x"937C",'1'&x"937D",'1'&x"937E",'1'&x"937F",
+--'1'&x"9380",'1'&x"9381",'1'&x"9382",'1'&x"9383",'1'&x"9384",'1'&x"9385",'1'&x"9386",'1'&x"9387",'1'&x"9388",'1'&x"9389",'1'&x"938A",'1'&x"938B",'1'&x"938C",'1'&x"938D",'1'&x"938E",'1'&x"938F",
+--'1'&x"9390",'1'&x"9391",'1'&x"9392",'1'&x"9393",'1'&x"9394",'1'&x"9395",'1'&x"9396",'1'&x"9397",'1'&x"9398",'1'&x"9399",'1'&x"939A",'1'&x"939B",'1'&x"939C",'1'&x"939D",'1'&x"939E",'1'&x"939F",
+--'1'&x"93A0",'1'&x"93A1",'1'&x"93A2",'1'&x"93A3",'1'&x"93A4",'1'&x"93A5",'1'&x"93A6",'1'&x"93A7",'1'&x"93A8",'1'&x"93A9",'1'&x"93AA",'1'&x"93AB",'1'&x"93AC",'1'&x"93AD",'1'&x"93AE",'1'&x"93AF",
+--'1'&x"93B0",'1'&x"93B1",'1'&x"93B2",'1'&x"93B3",'1'&x"93B4",'1'&x"93B5",'1'&x"93B6",'1'&x"93B7",'1'&x"93B8",'1'&x"93B9",'1'&x"93BA",'1'&x"93BB",'1'&x"93BC",'1'&x"93BD",'1'&x"93BE",'1'&x"93BF",
+--'1'&x"93C0",'1'&x"93C1",'1'&x"93C2",'1'&x"93C3",'1'&x"93C4",'1'&x"93C5",'1'&x"93C6",'1'&x"93C7",'1'&x"93C8",'1'&x"93C9",'1'&x"93CA",'1'&x"93CB",'1'&x"93CC",'1'&x"93CD",'1'&x"93CE",'1'&x"93CF",
+--'1'&x"93D0",'1'&x"93D1",'1'&x"93D2",'1'&x"93D3",'1'&x"93D4",'1'&x"93D5",'1'&x"93D6",'1'&x"93D7",'1'&x"93D8",'1'&x"93D9",'1'&x"93DA",'1'&x"93DB",'1'&x"93DC",'1'&x"93DD",'1'&x"93DE",'1'&x"93DF",
+--'1'&x"93E0",'1'&x"93E1",'1'&x"93E2",'1'&x"93E3",'1'&x"93E4",'1'&x"93E5",'1'&x"93E6",'1'&x"93E7",'1'&x"93E8",'1'&x"93E9",'1'&x"93EA",'1'&x"93EB",'1'&x"93EC",'1'&x"93ED",'1'&x"93EE",'1'&x"93EF",
+--'1'&x"93F0",'1'&x"93F1",'1'&x"93F2",'1'&x"93F3",'1'&x"93F4",'1'&x"93F5",'1'&x"93F6",'1'&x"93F7",'1'&x"93F8",'1'&x"93F9",'1'&x"93FA",'1'&x"93FB",'1'&x"93FC",'1'&x"93FD",'1'&x"93FE",'1'&x"93FF",
+--'1'&x"9400",'1'&x"9401",'1'&x"9402",'1'&x"9403",'1'&x"9404",'1'&x"9405",'1'&x"9406",'1'&x"9407",'1'&x"9408",'1'&x"9409",'1'&x"940A",'1'&x"940B",'1'&x"940C",'1'&x"940D",'1'&x"940E",'1'&x"940F",
+--'1'&x"9410",'1'&x"9411",'1'&x"9412",'1'&x"9413",'1'&x"9414",'1'&x"9415",'1'&x"9416",'1'&x"9417",'1'&x"9418",'1'&x"9419",'1'&x"941A",'1'&x"941B",'1'&x"941C",'1'&x"941D",'1'&x"941E",'1'&x"941F",
+--'1'&x"9420",'1'&x"9421",'1'&x"9422",'1'&x"9423",'1'&x"9424",'1'&x"9425",'1'&x"9426",'1'&x"9427",'1'&x"9428",'1'&x"9429",'1'&x"942A",'1'&x"942B",'1'&x"942C",'1'&x"942D",'1'&x"942E",'1'&x"942F",
+--'1'&x"9430",'1'&x"9431",'1'&x"9432",'1'&x"9433",'1'&x"9434",'1'&x"9435",'1'&x"9436",'1'&x"9437",'1'&x"9438",'1'&x"9439",'1'&x"943A",'1'&x"943B",'1'&x"943C",'1'&x"943D",'1'&x"943E",'1'&x"943F",
+--'1'&x"9440",'1'&x"9441",'1'&x"9442",'1'&x"9443",'1'&x"9444",'1'&x"9445",'1'&x"9446",'1'&x"9447",'1'&x"9448",'1'&x"9449",'1'&x"944A",'1'&x"944B",'1'&x"944C",'1'&x"944D",'1'&x"944E",'1'&x"944F",
+--'1'&x"9450",'1'&x"9451",'1'&x"9452",'1'&x"9453",'1'&x"9454",'1'&x"9455",'1'&x"9456",'1'&x"9457",'1'&x"9458",'1'&x"9459",'1'&x"945A",'1'&x"945B",'1'&x"945C",'1'&x"945D",'1'&x"945E",'1'&x"945F",
+--'1'&x"9460",'1'&x"9461",'1'&x"9462",'1'&x"9463",'1'&x"9464",'1'&x"9465",'1'&x"9466",'1'&x"9467",'1'&x"9468",'1'&x"9469",'1'&x"946A",'1'&x"946B",'1'&x"946C",'1'&x"946D",'1'&x"946E",'1'&x"946F",
+--'1'&x"9470",'1'&x"9471",'1'&x"9472",'1'&x"9473",'1'&x"9474",'1'&x"9475",'1'&x"9476",'1'&x"9477",'1'&x"9478",'1'&x"9479",'1'&x"947A",'1'&x"947B",'1'&x"947C",'1'&x"947D",'1'&x"947E",'1'&x"947F",
+--'1'&x"9480",'1'&x"9481",'1'&x"9482",'1'&x"9483",'1'&x"9484",'1'&x"9485",'1'&x"9486",'1'&x"9487",'1'&x"9488",'1'&x"9489",'1'&x"948A",'1'&x"948B",'1'&x"948C",'1'&x"948D",'1'&x"948E",'1'&x"948F",
+--'1'&x"9490",'1'&x"9491",'1'&x"9492",'1'&x"9493",'1'&x"9494",'1'&x"9495",'1'&x"9496",'1'&x"9497",'1'&x"9498",'1'&x"9499",'1'&x"949A",'1'&x"949B",'1'&x"949C",'1'&x"949D",'1'&x"949E",'1'&x"949F",
+--'1'&x"94A0",'1'&x"94A1",'1'&x"94A2",'1'&x"94A3",'1'&x"94A4",'1'&x"94A5",'1'&x"94A6",'1'&x"94A7",'1'&x"94A8",'1'&x"94A9",'1'&x"94AA",'1'&x"94AB",'1'&x"94AC",'1'&x"94AD",'1'&x"94AE",'1'&x"94AF",
+--'1'&x"94B0",'1'&x"94B1",'1'&x"94B2",'1'&x"94B3",'1'&x"94B4",'1'&x"94B5",'1'&x"94B6",'1'&x"94B7",'1'&x"94B8",'1'&x"94B9",'1'&x"94BA",'1'&x"94BB",'1'&x"94BC",'1'&x"94BD",'1'&x"94BE",'1'&x"94BF",
+--'1'&x"94C0",'1'&x"94C1",'1'&x"94C2",'1'&x"94C3",'1'&x"94C4",'1'&x"94C5",'1'&x"94C6",'1'&x"94C7",'1'&x"94C8",'1'&x"94C9",'1'&x"94CA",'1'&x"94CB",'1'&x"94CC",'1'&x"94CD",'1'&x"94CE",'1'&x"94CF",
+--'1'&x"94D0",'1'&x"94D1",'1'&x"94D2",'1'&x"94D3",'1'&x"94D4",'1'&x"94D5",'1'&x"94D6",'1'&x"94D7",'1'&x"94D8",'1'&x"94D9",'1'&x"94DA",'1'&x"94DB",'1'&x"94DC",'1'&x"94DD",'1'&x"94DE",'1'&x"94DF",
+--'1'&x"94E0",'1'&x"94E1",'1'&x"94E2",'1'&x"94E3",'1'&x"94E4",'1'&x"94E5",'1'&x"94E6",'1'&x"94E7",'1'&x"94E8",'1'&x"94E9",'1'&x"94EA",'1'&x"94EB",'1'&x"94EC",'1'&x"94ED",'1'&x"94EE",'1'&x"94EF",
+--'1'&x"94F0",'1'&x"94F1",'1'&x"94F2",'1'&x"94F3",'1'&x"94F4",'1'&x"94F5",'1'&x"94F6",'1'&x"94F7",'1'&x"94F8",'1'&x"94F9",'1'&x"94FA",'1'&x"94FB",'1'&x"94FC",'1'&x"94FD",'1'&x"94FE",'1'&x"94FF",
+--'1'&x"9500",'1'&x"9501",'1'&x"9502",'1'&x"9503",'1'&x"9504",'1'&x"9505",'1'&x"9506",'1'&x"9507",'1'&x"9508",'1'&x"9509",'1'&x"950A",'1'&x"950B",'1'&x"950C",'1'&x"950D",'1'&x"950E",'1'&x"950F",
+--'1'&x"9510",'1'&x"9511",'1'&x"9512",'1'&x"9513",'1'&x"9514",'1'&x"9515",'1'&x"9516",'1'&x"9517",'1'&x"9518",'1'&x"9519",'1'&x"951A",'1'&x"951B",'1'&x"951C",'1'&x"951D",'1'&x"951E",'1'&x"951F",
+--'1'&x"9520",'1'&x"9521",'1'&x"9522",'1'&x"9523",'1'&x"9524",'1'&x"9525",'1'&x"9526",'1'&x"9527",'1'&x"9528",'1'&x"9529",'1'&x"952A",'1'&x"952B",'1'&x"952C",'1'&x"952D",'1'&x"952E",'1'&x"952F",
+--'1'&x"9530",'1'&x"9531",'1'&x"9532",'1'&x"9533",'1'&x"9534",'1'&x"9535",'1'&x"9536",'1'&x"9537",'1'&x"9538",'1'&x"9539",'1'&x"953A",'1'&x"953B",'1'&x"953C",'1'&x"953D",'1'&x"953E",'1'&x"953F",
+--'1'&x"9540",'1'&x"9541",'1'&x"9542",'1'&x"9543",'1'&x"9544",'1'&x"9545",'1'&x"9546",'1'&x"9547",'1'&x"9548",'1'&x"9549",'1'&x"954A",'1'&x"954B",'1'&x"954C",'1'&x"954D",'1'&x"954E",'1'&x"954F",
+--'1'&x"9550",'1'&x"9551",'1'&x"9552",'1'&x"9553",'1'&x"9554",'1'&x"9555",'1'&x"9556",'1'&x"9557",'1'&x"9558",'1'&x"9559",'1'&x"955A",'1'&x"955B",'1'&x"955C",'1'&x"955D",'1'&x"955E",'1'&x"955F",
+--'1'&x"9560",'1'&x"9561",'1'&x"9562",'1'&x"9563",'1'&x"9564",'1'&x"9565",'1'&x"9566",'1'&x"9567",'1'&x"9568",'1'&x"9569",'1'&x"956A",'1'&x"956B",'1'&x"956C",'1'&x"956D",'1'&x"956E",'1'&x"956F",
+--'1'&x"9570",'1'&x"9571",'1'&x"9572",'1'&x"9573",'1'&x"9574",'1'&x"9575",'1'&x"9576",'1'&x"9577",'1'&x"9578",'1'&x"9579",'1'&x"957A",'1'&x"957B",'1'&x"957C",'1'&x"957D",'1'&x"957E",'1'&x"957F",
+--'1'&x"9580",'1'&x"9581",'1'&x"9582",'1'&x"9583",'1'&x"9584",'1'&x"9585",'1'&x"9586",'1'&x"9587",'1'&x"9588",'1'&x"9589",'1'&x"958A",'1'&x"958B",'1'&x"958C",'1'&x"958D",'1'&x"958E",'1'&x"958F",
+--'1'&x"9590",'1'&x"9591",'1'&x"9592",'1'&x"9593",'1'&x"9594",'1'&x"9595",'1'&x"9596",'1'&x"9597",'1'&x"9598",'1'&x"9599",'1'&x"959A",'1'&x"959B",'1'&x"959C",'1'&x"959D",'1'&x"959E",'1'&x"959F",
+--'1'&x"95A0",'1'&x"95A1",'1'&x"95A2",'1'&x"95A3",'1'&x"95A4",'1'&x"95A5",'1'&x"95A6",'1'&x"95A7",'1'&x"95A8",'1'&x"95A9",'1'&x"95AA",'1'&x"95AB",'1'&x"95AC",'1'&x"95AD",'1'&x"95AE",'1'&x"95AF",
+--'1'&x"95B0",'1'&x"95B1",'1'&x"95B2",'1'&x"95B3",'1'&x"95B4",'1'&x"95B5",'1'&x"95B6",'1'&x"95B7",'1'&x"95B8",'1'&x"95B9",'1'&x"95BA",'1'&x"95BB",'1'&x"95BC",'1'&x"95BD",'1'&x"95BE",'1'&x"95BF",
+--'1'&x"95C0",'1'&x"95C1",'1'&x"95C2",'1'&x"95C3",'1'&x"95C4",'1'&x"95C5",'1'&x"95C6",'1'&x"95C7",'1'&x"95C8",'1'&x"95C9",'1'&x"95CA",'1'&x"95CB",'1'&x"95CC",'1'&x"95CD",'1'&x"95CE",'1'&x"95CF",
+--'1'&x"95D0",'1'&x"95D1",'1'&x"95D2",'1'&x"95D3",'1'&x"95D4",'1'&x"95D5",'1'&x"95D6",'1'&x"95D7",'1'&x"95D8",'1'&x"95D9",'1'&x"95DA",'1'&x"95DB",'1'&x"95DC",'1'&x"95DD",'1'&x"95DE",'1'&x"95DF",
+--'1'&x"95E0",'1'&x"95E1",'1'&x"95E2",'1'&x"95E3",'1'&x"95E4",'1'&x"95E5",'1'&x"95E6",'1'&x"95E7",'1'&x"95E8",'1'&x"95E9",'1'&x"95EA",'1'&x"95EB",'1'&x"95EC",'1'&x"95ED",'1'&x"95EE",'1'&x"95EF",
+--'1'&x"95F0",'1'&x"95F1",'1'&x"95F2",'1'&x"95F3",'1'&x"95F4",'1'&x"95F5",'1'&x"95F6",'1'&x"95F7",'1'&x"95F8",'1'&x"95F9",'1'&x"95FA",'1'&x"95FB",'1'&x"95FC",'1'&x"95FD",'1'&x"95FE",'1'&x"95FF",
+--'1'&x"9600",'1'&x"9601",'1'&x"9602",'1'&x"9603",'1'&x"9604",'1'&x"9605",'1'&x"9606",'1'&x"9607",'1'&x"9608",'1'&x"9609",'1'&x"960A",'1'&x"960B",'1'&x"960C",'1'&x"960D",'1'&x"960E",'1'&x"960F",
+--'1'&x"9610",'1'&x"9611",'1'&x"9612",'1'&x"9613",'1'&x"9614",'1'&x"9615",'1'&x"9616",'1'&x"9617",'1'&x"9618",'1'&x"9619",'1'&x"961A",'1'&x"961B",'1'&x"961C",'1'&x"961D",'1'&x"961E",'1'&x"961F",
+--'1'&x"9620",'1'&x"9621",'1'&x"9622",'1'&x"9623",'1'&x"9624",'1'&x"9625",'1'&x"9626",'1'&x"9627",'1'&x"9628",'1'&x"9629",'1'&x"962A",'1'&x"962B",'1'&x"962C",'1'&x"962D",'1'&x"962E",'1'&x"962F",
+--'1'&x"9630",'1'&x"9631",'1'&x"9632",'1'&x"9633",'1'&x"9634",'1'&x"9635",'1'&x"9636",'1'&x"9637",'1'&x"9638",'1'&x"9639",'1'&x"963A",'1'&x"963B",'1'&x"963C",'1'&x"963D",'1'&x"963E",'1'&x"963F",
+--'1'&x"9640",'1'&x"9641",'1'&x"9642",'1'&x"9643",'1'&x"9644",'1'&x"9645",'1'&x"9646",'1'&x"9647",'1'&x"9648",'1'&x"9649",'1'&x"964A",'1'&x"964B",'1'&x"964C",'1'&x"964D",'1'&x"964E",'1'&x"964F",
+--'1'&x"9650",'1'&x"9651",'1'&x"9652",'1'&x"9653",'1'&x"9654",'1'&x"9655",'1'&x"9656",'1'&x"9657",'1'&x"9658",'1'&x"9659",'1'&x"965A",'1'&x"965B",'1'&x"965C",'1'&x"965D",'1'&x"965E",'1'&x"965F",
+--'1'&x"9660",'1'&x"9661",'1'&x"9662",'1'&x"9663",'1'&x"9664",'1'&x"9665",'1'&x"9666",'1'&x"9667",'1'&x"9668",'1'&x"9669",'1'&x"966A",'1'&x"966B",'1'&x"966C",'1'&x"966D",'1'&x"966E",'1'&x"966F",
+--'1'&x"9670",'1'&x"9671",'1'&x"9672",'1'&x"9673",'1'&x"9674",'1'&x"9675",'1'&x"9676",'1'&x"9677",'1'&x"9678",'1'&x"9679",'1'&x"967A",'1'&x"967B",'1'&x"967C",'1'&x"967D",'1'&x"967E",'1'&x"967F",
+--'1'&x"9680",'1'&x"9681",'1'&x"9682",'1'&x"9683",'1'&x"9684",'1'&x"9685",'1'&x"9686",'1'&x"9687",'1'&x"9688",'1'&x"9689",'1'&x"968A",'1'&x"968B",'1'&x"968C",'1'&x"968D",'1'&x"968E",'1'&x"968F",
+--'1'&x"9690",'1'&x"9691",'1'&x"9692",'1'&x"9693",'1'&x"9694",'1'&x"9695",'1'&x"9696",'1'&x"9697",'1'&x"9698",'1'&x"9699",'1'&x"969A",'1'&x"969B",'1'&x"969C",'1'&x"969D",'1'&x"969E",'1'&x"969F",
+--'1'&x"96A0",'1'&x"96A1",'1'&x"96A2",'1'&x"96A3",'1'&x"96A4",'1'&x"96A5",'1'&x"96A6",'1'&x"96A7",'1'&x"96A8",'1'&x"96A9",'1'&x"96AA",'1'&x"96AB",'1'&x"96AC",'1'&x"96AD",'1'&x"96AE",'1'&x"96AF",
+--'1'&x"96B0",'1'&x"96B1",'1'&x"96B2",'1'&x"96B3",'1'&x"96B4",'1'&x"96B5",'1'&x"96B6",'1'&x"96B7",'1'&x"96B8",'1'&x"96B9",'1'&x"96BA",'1'&x"96BB",'1'&x"96BC",'1'&x"96BD",'1'&x"96BE",'1'&x"96BF",
+--'1'&x"96C0",'1'&x"96C1",'1'&x"96C2",'1'&x"96C3",'1'&x"96C4",'1'&x"96C5",'1'&x"96C6",'1'&x"96C7",'1'&x"96C8",'1'&x"96C9",'1'&x"96CA",'1'&x"96CB",'1'&x"96CC",'1'&x"96CD",'1'&x"96CE",'1'&x"96CF",
+--'1'&x"96D0",'1'&x"96D1",'1'&x"96D2",'1'&x"96D3",'1'&x"96D4",'1'&x"96D5",'1'&x"96D6",'1'&x"96D7",'1'&x"96D8",'1'&x"96D9",'1'&x"96DA",'1'&x"96DB",'1'&x"96DC",'1'&x"96DD",'1'&x"96DE",'1'&x"96DF",
+--'1'&x"96E0",'1'&x"96E1",'1'&x"96E2",'1'&x"96E3",'1'&x"96E4",'1'&x"96E5",'1'&x"96E6",'1'&x"96E7",'1'&x"96E8",'1'&x"96E9",'1'&x"96EA",'1'&x"96EB",'1'&x"96EC",'1'&x"96ED",'1'&x"96EE",'1'&x"96EF",
+--'1'&x"96F0",'1'&x"96F1",'1'&x"96F2",'1'&x"96F3",'1'&x"96F4",'1'&x"96F5",'1'&x"96F6",'1'&x"96F7",'1'&x"96F8",'1'&x"96F9",'1'&x"96FA",'1'&x"96FB",'1'&x"96FC",'1'&x"96FD",'1'&x"96FE",'1'&x"96FF",
+--'1'&x"9700",'1'&x"9701",'1'&x"9702",'1'&x"9703",'1'&x"9704",'1'&x"9705",'1'&x"9706",'1'&x"9707",'1'&x"9708",'1'&x"9709",'1'&x"970A",'1'&x"970B",'1'&x"970C",'1'&x"970D",'1'&x"970E",'1'&x"970F",
+--'1'&x"9710",'1'&x"9711",'1'&x"9712",'1'&x"9713",'1'&x"9714",'1'&x"9715",'1'&x"9716",'1'&x"9717",'1'&x"9718",'1'&x"9719",'1'&x"971A",'1'&x"971B",'1'&x"971C",'1'&x"971D",'1'&x"971E",'1'&x"971F",
+--'1'&x"9720",'1'&x"9721",'1'&x"9722",'1'&x"9723",'1'&x"9724",'1'&x"9725",'1'&x"9726",'1'&x"9727",'1'&x"9728",'1'&x"9729",'1'&x"972A",'1'&x"972B",'1'&x"972C",'1'&x"972D",'1'&x"972E",'1'&x"972F",
+--'1'&x"9730",'1'&x"9731",'1'&x"9732",'1'&x"9733",'1'&x"9734",'1'&x"9735",'1'&x"9736",'1'&x"9737",'1'&x"9738",'1'&x"9739",'1'&x"973A",'1'&x"973B",'1'&x"973C",'1'&x"973D",'1'&x"973E",'1'&x"973F",
+--'1'&x"9740",'1'&x"9741",'1'&x"9742",'1'&x"9743",'1'&x"9744",'1'&x"9745",'1'&x"9746",'1'&x"9747",'1'&x"9748",'1'&x"9749",'1'&x"974A",'1'&x"974B",'1'&x"974C",'1'&x"974D",'1'&x"974E",'1'&x"974F",
+--'1'&x"9750",'1'&x"9751",'1'&x"9752",'1'&x"9753",'1'&x"9754",'1'&x"9755",'1'&x"9756",'1'&x"9757",'1'&x"9758",'1'&x"9759",'1'&x"975A",'1'&x"975B",'1'&x"975C",'1'&x"975D",'1'&x"975E",'1'&x"975F",
+--'1'&x"9760",'1'&x"9761",'1'&x"9762",'1'&x"9763",'1'&x"9764",'1'&x"9765",'1'&x"9766",'1'&x"9767",'1'&x"9768",'1'&x"9769",'1'&x"976A",'1'&x"976B",'1'&x"976C",'1'&x"976D",'1'&x"976E",'1'&x"976F",
+--'1'&x"9770",'1'&x"9771",'1'&x"9772",'1'&x"9773",'1'&x"9774",'1'&x"9775",'1'&x"9776",'1'&x"9777",'1'&x"9778",'1'&x"9779",'1'&x"977A",'1'&x"977B",'1'&x"977C",'1'&x"977D",'1'&x"977E",'1'&x"977F",
+--'1'&x"9780",'1'&x"9781",'1'&x"9782",'1'&x"9783",'1'&x"9784",'1'&x"9785",'1'&x"9786",'1'&x"9787",'1'&x"9788",'1'&x"9789",'1'&x"978A",'1'&x"978B",'1'&x"978C",'1'&x"978D",'1'&x"978E",'1'&x"978F",
+--'1'&x"9790",'1'&x"9791",'1'&x"9792",'1'&x"9793",'1'&x"9794",'1'&x"9795",'1'&x"9796",'1'&x"9797",'1'&x"9798",'1'&x"9799",'1'&x"979A",'1'&x"979B",'1'&x"979C",'1'&x"979D",'1'&x"979E",'1'&x"979F",
+--'1'&x"97A0",'1'&x"97A1",'1'&x"97A2",'1'&x"97A3",'1'&x"97A4",'1'&x"97A5",'1'&x"97A6",'1'&x"97A7",'1'&x"97A8",'1'&x"97A9",'1'&x"97AA",'1'&x"97AB",'1'&x"97AC",'1'&x"97AD",'1'&x"97AE",'1'&x"97AF",
+--'1'&x"97B0",'1'&x"97B1",'1'&x"97B2",'1'&x"97B3",'1'&x"97B4",'1'&x"97B5",'1'&x"97B6",'1'&x"97B7",'1'&x"97B8",'1'&x"97B9",'1'&x"97BA",'1'&x"97BB",'1'&x"97BC",'1'&x"97BD",'1'&x"97BE",'1'&x"97BF",
+--'1'&x"97C0",'1'&x"97C1",'1'&x"97C2",'1'&x"97C3",'1'&x"97C4",'1'&x"97C5",'1'&x"97C6",'1'&x"97C7",'1'&x"97C8",'1'&x"97C9",'1'&x"97CA",'1'&x"97CB",'1'&x"97CC",'1'&x"97CD",'1'&x"97CE",'1'&x"97CF",
+--'1'&x"97D0",'1'&x"97D1",'1'&x"97D2",'1'&x"97D3",'1'&x"97D4",'1'&x"97D5",'1'&x"97D6",'1'&x"97D7",'1'&x"97D8",'1'&x"97D9",'1'&x"97DA",'1'&x"97DB",'1'&x"97DC",'1'&x"97DD",'1'&x"97DE",'1'&x"97DF",
+--'1'&x"97E0",'1'&x"97E1",'1'&x"97E2",'1'&x"97E3",'1'&x"97E4",'1'&x"97E5",'1'&x"97E6",'1'&x"97E7",'1'&x"97E8",'1'&x"97E9",'1'&x"97EA",'1'&x"97EB",'1'&x"97EC",'1'&x"97ED",'1'&x"97EE",'1'&x"97EF",
+--'1'&x"97F0",'1'&x"97F1",'1'&x"97F2",'1'&x"97F3",'1'&x"97F4",'1'&x"97F5",'1'&x"97F6",'1'&x"97F7",'1'&x"97F8",'1'&x"97F9",'1'&x"97FA",'1'&x"97FB",'1'&x"97FC",'1'&x"97FD",'1'&x"97FE",'1'&x"97FF",
+--'1'&x"9800",'1'&x"9801",'1'&x"9802",'1'&x"9803",'1'&x"9804",'1'&x"9805",'1'&x"9806",'1'&x"9807",'1'&x"9808",'1'&x"9809",'1'&x"980A",'1'&x"980B",'1'&x"980C",'1'&x"980D",'1'&x"980E",'1'&x"980F",
+--'1'&x"9810",'1'&x"9811",'1'&x"9812",'1'&x"9813",'1'&x"9814",'1'&x"9815",'1'&x"9816",'1'&x"9817",'1'&x"9818",'1'&x"9819",'1'&x"981A",'1'&x"981B",'1'&x"981C",'1'&x"981D",'1'&x"981E",'1'&x"981F",
+--'1'&x"9820",'1'&x"9821",'1'&x"9822",'1'&x"9823",'1'&x"9824",'1'&x"9825",'1'&x"9826",'1'&x"9827",'1'&x"9828",'1'&x"9829",'1'&x"982A",'1'&x"982B",'1'&x"982C",'1'&x"982D",'1'&x"982E",'1'&x"982F",
+--'1'&x"9830",'1'&x"9831",'1'&x"9832",'1'&x"9833",'1'&x"9834",'1'&x"9835",'1'&x"9836",'1'&x"9837",'1'&x"9838",'1'&x"9839",'1'&x"983A",'1'&x"983B",'1'&x"983C",'1'&x"983D",'1'&x"983E",'1'&x"983F",
+--'1'&x"9840",'1'&x"9841",'1'&x"9842",'1'&x"9843",'1'&x"9844",'1'&x"9845",'1'&x"9846",'1'&x"9847",'1'&x"9848",'1'&x"9849",'1'&x"984A",'1'&x"984B",'1'&x"984C",'1'&x"984D",'1'&x"984E",'1'&x"984F",
+--'1'&x"9850",'1'&x"9851",'1'&x"9852",'1'&x"9853",'1'&x"9854",'1'&x"9855",'1'&x"9856",'1'&x"9857",'1'&x"9858",'1'&x"9859",'1'&x"985A",'1'&x"985B",'1'&x"985C",'1'&x"985D",'1'&x"985E",'1'&x"985F",
+--'1'&x"9860",'1'&x"9861",'1'&x"9862",'1'&x"9863",'1'&x"9864",'1'&x"9865",'1'&x"9866",'1'&x"9867",'1'&x"9868",'1'&x"9869",'1'&x"986A",'1'&x"986B",'1'&x"986C",'1'&x"986D",'1'&x"986E",'1'&x"986F",
+--'1'&x"9870",'1'&x"9871",'1'&x"9872",'1'&x"9873",'1'&x"9874",'1'&x"9875",'1'&x"9876",'1'&x"9877",'1'&x"9878",'1'&x"9879",'1'&x"987A",'1'&x"987B",'1'&x"987C",'1'&x"987D",'1'&x"987E",'1'&x"987F",
+--'1'&x"9880",'1'&x"9881",'1'&x"9882",'1'&x"9883",'1'&x"9884",'1'&x"9885",'1'&x"9886",'1'&x"9887",'1'&x"9888",'1'&x"9889",'1'&x"988A",'1'&x"988B",'1'&x"988C",'1'&x"988D",'1'&x"988E",'1'&x"988F",
+--'1'&x"9890",'1'&x"9891",'1'&x"9892",'1'&x"9893",'1'&x"9894",'1'&x"9895",'1'&x"9896",'1'&x"9897",'1'&x"9898",'1'&x"9899",'1'&x"989A",'1'&x"989B",'1'&x"989C",'1'&x"989D",'1'&x"989E",'1'&x"989F",
+--'1'&x"98A0",'1'&x"98A1",'1'&x"98A2",'1'&x"98A3",'1'&x"98A4",'1'&x"98A5",'1'&x"98A6",'1'&x"98A7",'1'&x"98A8",'1'&x"98A9",'1'&x"98AA",'1'&x"98AB",'1'&x"98AC",'1'&x"98AD",'1'&x"98AE",'1'&x"98AF",
+--'1'&x"98B0",'1'&x"98B1",'1'&x"98B2",'1'&x"98B3",'1'&x"98B4",'1'&x"98B5",'1'&x"98B6",'1'&x"98B7",'1'&x"98B8",'1'&x"98B9",'1'&x"98BA",'1'&x"98BB",'1'&x"98BC",'1'&x"98BD",'1'&x"98BE",'1'&x"98BF",
+--'1'&x"98C0",'1'&x"98C1",'1'&x"98C2",'1'&x"98C3",'1'&x"98C4",'1'&x"98C5",'1'&x"98C6",'1'&x"98C7",'1'&x"98C8",'1'&x"98C9",'1'&x"98CA",'1'&x"98CB",'1'&x"98CC",'1'&x"98CD",'1'&x"98CE",'1'&x"98CF",
+--'1'&x"98D0",'1'&x"98D1",'1'&x"98D2",'1'&x"98D3",'1'&x"98D4",'1'&x"98D5",'1'&x"98D6",'1'&x"98D7",'1'&x"98D8",'1'&x"98D9",'1'&x"98DA",'1'&x"98DB",'1'&x"98DC",'1'&x"98DD",'1'&x"98DE",'1'&x"98DF",
+--'1'&x"98E0",'1'&x"98E1",'1'&x"98E2",'1'&x"98E3",'1'&x"98E4",'1'&x"98E5",'1'&x"98E6",'1'&x"98E7",'1'&x"98E8",'1'&x"98E9",'1'&x"98EA",'1'&x"98EB",'1'&x"98EC",'1'&x"98ED",'1'&x"98EE",'1'&x"98EF",
+--'1'&x"98F0",'1'&x"98F1",'1'&x"98F2",'1'&x"98F3",'1'&x"98F4",'1'&x"98F5",'1'&x"98F6",'1'&x"98F7",'1'&x"98F8",'1'&x"98F9",'1'&x"98FA",'1'&x"98FB",'1'&x"98FC",'1'&x"98FD",'1'&x"98FE",'1'&x"98FF",
+--'1'&x"9900",'1'&x"9901",'1'&x"9902",'1'&x"9903",'1'&x"9904",'1'&x"9905",'1'&x"9906",'1'&x"9907",'1'&x"9908",'1'&x"9909",'1'&x"990A",'1'&x"990B",'1'&x"990C",'1'&x"990D",'1'&x"990E",'1'&x"990F",
+--'1'&x"9910",'1'&x"9911",'1'&x"9912",'1'&x"9913",'1'&x"9914",'1'&x"9915",'1'&x"9916",'1'&x"9917",'1'&x"9918",'1'&x"9919",'1'&x"991A",'1'&x"991B",'1'&x"991C",'1'&x"991D",'1'&x"991E",'1'&x"991F",
+--'1'&x"9920",'1'&x"9921",'1'&x"9922",'1'&x"9923",'1'&x"9924",'1'&x"9925",'1'&x"9926",'1'&x"9927",'1'&x"9928",'1'&x"9929",'1'&x"992A",'1'&x"992B",'1'&x"992C",'1'&x"992D",'1'&x"992E",'1'&x"992F",
+--'1'&x"9930",'1'&x"9931",'1'&x"9932",'1'&x"9933",'1'&x"9934",'1'&x"9935",'1'&x"9936",'1'&x"9937",'1'&x"9938",'1'&x"9939",'1'&x"993A",'1'&x"993B",'1'&x"993C",'1'&x"993D",'1'&x"993E",'1'&x"993F",
+--'1'&x"9940",'1'&x"9941",'1'&x"9942",'1'&x"9943",'1'&x"9944",'1'&x"9945",'1'&x"9946",'1'&x"9947",'1'&x"9948",'1'&x"9949",'1'&x"994A",'1'&x"994B",'1'&x"994C",'1'&x"994D",'1'&x"994E",'1'&x"994F",
+--'1'&x"9950",'1'&x"9951",'1'&x"9952",'1'&x"9953",'1'&x"9954",'1'&x"9955",'1'&x"9956",'1'&x"9957",'1'&x"9958",'1'&x"9959",'1'&x"995A",'1'&x"995B",'1'&x"995C",'1'&x"995D",'1'&x"995E",'1'&x"995F",
+--'1'&x"9960",'1'&x"9961",'1'&x"9962",'1'&x"9963",'1'&x"9964",'1'&x"9965",'1'&x"9966",'1'&x"9967",'1'&x"9968",'1'&x"9969",'1'&x"996A",'1'&x"996B",'1'&x"996C",'1'&x"996D",'1'&x"996E",'1'&x"996F",
+--'1'&x"9970",'1'&x"9971",'1'&x"9972",'1'&x"9973",'1'&x"9974",'1'&x"9975",'1'&x"9976",'1'&x"9977",'1'&x"9978",'1'&x"9979",'1'&x"997A",'1'&x"997B",'1'&x"997C",'1'&x"997D",'1'&x"997E",'1'&x"997F",
+--'1'&x"9980",'1'&x"9981",'1'&x"9982",'1'&x"9983",'1'&x"9984",'1'&x"9985",'1'&x"9986",'1'&x"9987",'1'&x"9988",'1'&x"9989",'1'&x"998A",'1'&x"998B",'1'&x"998C",'1'&x"998D",'1'&x"998E",'1'&x"998F",
+--'1'&x"9990",'1'&x"9991",'1'&x"9992",'1'&x"9993",'1'&x"9994",'1'&x"9995",'1'&x"9996",'1'&x"9997",'1'&x"9998",'1'&x"9999",'1'&x"999A",'1'&x"999B",'1'&x"999C",'1'&x"999D",'1'&x"999E",'1'&x"999F",
+--'1'&x"99A0",'1'&x"99A1",'1'&x"99A2",'1'&x"99A3",'1'&x"99A4",'1'&x"99A5",'1'&x"99A6",'1'&x"99A7",'1'&x"99A8",'1'&x"99A9",'1'&x"99AA",'1'&x"99AB",'1'&x"99AC",'1'&x"99AD",'1'&x"99AE",'1'&x"99AF",
+--'1'&x"99B0",'1'&x"99B1",'1'&x"99B2",'1'&x"99B3",'1'&x"99B4",'1'&x"99B5",'1'&x"99B6",'1'&x"99B7",'1'&x"99B8",'1'&x"99B9",'1'&x"99BA",'1'&x"99BB",'1'&x"99BC",'1'&x"99BD",'1'&x"99BE",'1'&x"99BF",
+--'1'&x"99C0",'1'&x"99C1",'1'&x"99C2",'1'&x"99C3",'1'&x"99C4",'1'&x"99C5",'1'&x"99C6",'1'&x"99C7",'1'&x"99C8",'1'&x"99C9",'1'&x"99CA",'1'&x"99CB",'1'&x"99CC",'1'&x"99CD",'1'&x"99CE",'1'&x"99CF",
+--'1'&x"99D0",'1'&x"99D1",'1'&x"99D2",'1'&x"99D3",'1'&x"99D4",'1'&x"99D5",'1'&x"99D6",'1'&x"99D7",'1'&x"99D8",'1'&x"99D9",'1'&x"99DA",'1'&x"99DB",'1'&x"99DC",'1'&x"99DD",'1'&x"99DE",'1'&x"99DF",
+--'1'&x"99E0",'1'&x"99E1",'1'&x"99E2",'1'&x"99E3",'1'&x"99E4",'1'&x"99E5",'1'&x"99E6",'1'&x"99E7",'1'&x"99E8",'1'&x"99E9",'1'&x"99EA",'1'&x"99EB",'1'&x"99EC",'1'&x"99ED",'1'&x"99EE",'1'&x"99EF",
+--'1'&x"99F0",'1'&x"99F1",'1'&x"99F2",'1'&x"99F3",'1'&x"99F4",'1'&x"99F5",'1'&x"99F6",'1'&x"99F7",'1'&x"99F8",'1'&x"99F9",'1'&x"99FA",'1'&x"99FB",'1'&x"99FC",'1'&x"99FD",'1'&x"99FE",'1'&x"99FF",
+--'1'&x"9A00",'1'&x"9A01",'1'&x"9A02",'1'&x"9A03",'1'&x"9A04",'1'&x"9A05",'1'&x"9A06",'1'&x"9A07",'1'&x"9A08",'1'&x"9A09",'1'&x"9A0A",'1'&x"9A0B",'1'&x"9A0C",'1'&x"9A0D",'1'&x"9A0E",'1'&x"9A0F",
+--'1'&x"9A10",'1'&x"9A11",'1'&x"9A12",'1'&x"9A13",'1'&x"9A14",'1'&x"9A15",'1'&x"9A16",'1'&x"9A17",'1'&x"9A18",'1'&x"9A19",'1'&x"9A1A",'1'&x"9A1B",'1'&x"9A1C",'1'&x"9A1D",'1'&x"9A1E",'1'&x"9A1F",
+--'1'&x"9A20",'1'&x"9A21",'1'&x"9A22",'1'&x"9A23",'1'&x"9A24",'1'&x"9A25",'1'&x"9A26",'1'&x"9A27",'1'&x"9A28",'1'&x"9A29",'1'&x"9A2A",'1'&x"9A2B",'1'&x"9A2C",'1'&x"9A2D",'1'&x"9A2E",'1'&x"9A2F",
+--'1'&x"9A30",'1'&x"9A31",'1'&x"9A32",'1'&x"9A33",'1'&x"9A34",'1'&x"9A35",'1'&x"9A36",'1'&x"9A37",'1'&x"9A38",'1'&x"9A39",'1'&x"9A3A",'1'&x"9A3B",'1'&x"9A3C",'1'&x"9A3D",'1'&x"9A3E",'1'&x"9A3F",
+--'1'&x"9A40",'1'&x"9A41",'1'&x"9A42",'1'&x"9A43",'1'&x"9A44",'1'&x"9A45",'1'&x"9A46",'1'&x"9A47",'1'&x"9A48",'1'&x"9A49",'1'&x"9A4A",'1'&x"9A4B",'1'&x"9A4C",'1'&x"9A4D",'1'&x"9A4E",'1'&x"9A4F",
+--'1'&x"9A50",'1'&x"9A51",'1'&x"9A52",'1'&x"9A53",'1'&x"9A54",'1'&x"9A55",'1'&x"9A56",'1'&x"9A57",'1'&x"9A58",'1'&x"9A59",'1'&x"9A5A",'1'&x"9A5B",'1'&x"9A5C",'1'&x"9A5D",'1'&x"9A5E",'1'&x"9A5F",
+--'1'&x"9A60",'1'&x"9A61",'1'&x"9A62",'1'&x"9A63",'1'&x"9A64",'1'&x"9A65",'1'&x"9A66",'1'&x"9A67",'1'&x"9A68",'1'&x"9A69",'1'&x"9A6A",'1'&x"9A6B",'1'&x"9A6C",'1'&x"9A6D",'1'&x"9A6E",'1'&x"9A6F",
+--'1'&x"9A70",'1'&x"9A71",'1'&x"9A72",'1'&x"9A73",'1'&x"9A74",'1'&x"9A75",'1'&x"9A76",'1'&x"9A77",'1'&x"9A78",'1'&x"9A79",'1'&x"9A7A",'1'&x"9A7B",'1'&x"9A7C",'1'&x"9A7D",'1'&x"9A7E",'1'&x"9A7F",
+--'1'&x"9A80",'1'&x"9A81",'1'&x"9A82",'1'&x"9A83",'1'&x"9A84",'1'&x"9A85",'1'&x"9A86",'1'&x"9A87",'1'&x"9A88",'1'&x"9A89",'1'&x"9A8A",'1'&x"9A8B",'1'&x"9A8C",'1'&x"9A8D",'1'&x"9A8E",'1'&x"9A8F",
+--'1'&x"9A90",'1'&x"9A91",'1'&x"9A92",'1'&x"9A93",'1'&x"9A94",'1'&x"9A95",'1'&x"9A96",'1'&x"9A97",'1'&x"9A98",'1'&x"9A99",'1'&x"9A9A",'1'&x"9A9B",'1'&x"9A9C",'1'&x"9A9D",'1'&x"9A9E",'1'&x"9A9F",
+--'1'&x"9AA0",'1'&x"9AA1",'1'&x"9AA2",'1'&x"9AA3",'1'&x"9AA4",'1'&x"9AA5",'1'&x"9AA6",'1'&x"9AA7",'1'&x"9AA8",'1'&x"9AA9",'1'&x"9AAA",'1'&x"9AAB",'1'&x"9AAC",'1'&x"9AAD",'1'&x"9AAE",'1'&x"9AAF",
+--'1'&x"9AB0",'1'&x"9AB1",'1'&x"9AB2",'1'&x"9AB3",'1'&x"9AB4",'1'&x"9AB5",'1'&x"9AB6",'1'&x"9AB7",'1'&x"9AB8",'1'&x"9AB9",'1'&x"9ABA",'1'&x"9ABB",'1'&x"9ABC",'1'&x"9ABD",'1'&x"9ABE",'1'&x"9ABF",
+--'1'&x"9AC0",'1'&x"9AC1",'1'&x"9AC2",'1'&x"9AC3",'1'&x"9AC4",'1'&x"9AC5",'1'&x"9AC6",'1'&x"9AC7",'1'&x"9AC8",'1'&x"9AC9",'1'&x"9ACA",'1'&x"9ACB",'1'&x"9ACC",'1'&x"9ACD",'1'&x"9ACE",'1'&x"9ACF",
+--'1'&x"9AD0",'1'&x"9AD1",'1'&x"9AD2",'1'&x"9AD3",'1'&x"9AD4",'1'&x"9AD5",'1'&x"9AD6",'1'&x"9AD7",'1'&x"9AD8",'1'&x"9AD9",'1'&x"9ADA",'1'&x"9ADB",'1'&x"9ADC",'1'&x"9ADD",'1'&x"9ADE",'1'&x"9ADF",
+--'1'&x"9AE0",'1'&x"9AE1",'1'&x"9AE2",'1'&x"9AE3",'1'&x"9AE4",'1'&x"9AE5",'1'&x"9AE6",'1'&x"9AE7",'1'&x"9AE8",'1'&x"9AE9",'1'&x"9AEA",'1'&x"9AEB",'1'&x"9AEC",'1'&x"9AED",'1'&x"9AEE",'1'&x"9AEF",
+--'1'&x"9AF0",'1'&x"9AF1",'1'&x"9AF2",'1'&x"9AF3",'1'&x"9AF4",'1'&x"9AF5",'1'&x"9AF6",'1'&x"9AF7",'1'&x"9AF8",'1'&x"9AF9",'1'&x"9AFA",'1'&x"9AFB",'1'&x"9AFC",'1'&x"9AFD",'1'&x"9AFE",'1'&x"9AFF",
+--'1'&x"9B00",'1'&x"9B01",'1'&x"9B02",'1'&x"9B03",'1'&x"9B04",'1'&x"9B05",'1'&x"9B06",'1'&x"9B07",'1'&x"9B08",'1'&x"9B09",'1'&x"9B0A",'1'&x"9B0B",'1'&x"9B0C",'1'&x"9B0D",'1'&x"9B0E",'1'&x"9B0F",
+--'1'&x"9B10",'1'&x"9B11",'1'&x"9B12",'1'&x"9B13",'1'&x"9B14",'1'&x"9B15",'1'&x"9B16",'1'&x"9B17",'1'&x"9B18",'1'&x"9B19",'1'&x"9B1A",'1'&x"9B1B",'1'&x"9B1C",'1'&x"9B1D",'1'&x"9B1E",'1'&x"9B1F",
+--'1'&x"9B20",'1'&x"9B21",'1'&x"9B22",'1'&x"9B23",'1'&x"9B24",'1'&x"9B25",'1'&x"9B26",'1'&x"9B27",'1'&x"9B28",'1'&x"9B29",'1'&x"9B2A",'1'&x"9B2B",'1'&x"9B2C",'1'&x"9B2D",'1'&x"9B2E",'1'&x"9B2F",
+--'1'&x"9B30",'1'&x"9B31",'1'&x"9B32",'1'&x"9B33",'1'&x"9B34",'1'&x"9B35",'1'&x"9B36",'1'&x"9B37",'1'&x"9B38",'1'&x"9B39",'1'&x"9B3A",'1'&x"9B3B",'1'&x"9B3C",'1'&x"9B3D",'1'&x"9B3E",'1'&x"9B3F",
+--'1'&x"9B40",'1'&x"9B41",'1'&x"9B42",'1'&x"9B43",'1'&x"9B44",'1'&x"9B45",'1'&x"9B46",'1'&x"9B47",'1'&x"9B48",'1'&x"9B49",'1'&x"9B4A",'1'&x"9B4B",'1'&x"9B4C",'1'&x"9B4D",'1'&x"9B4E",'1'&x"9B4F",
+--'1'&x"9B50",'1'&x"9B51",'1'&x"9B52",'1'&x"9B53",'1'&x"9B54",'1'&x"9B55",'1'&x"9B56",'1'&x"9B57",'1'&x"9B58",'1'&x"9B59",'1'&x"9B5A",'1'&x"9B5B",'1'&x"9B5C",'1'&x"9B5D",'1'&x"9B5E",'1'&x"9B5F",
+--'1'&x"9B60",'1'&x"9B61",'1'&x"9B62",'1'&x"9B63",'1'&x"9B64",'1'&x"9B65",'1'&x"9B66",'1'&x"9B67",'1'&x"9B68",'1'&x"9B69",'1'&x"9B6A",'1'&x"9B6B",'1'&x"9B6C",'1'&x"9B6D",'1'&x"9B6E",'1'&x"9B6F",
+--'1'&x"9B70",'1'&x"9B71",'1'&x"9B72",'1'&x"9B73",'1'&x"9B74",'1'&x"9B75",'1'&x"9B76",'1'&x"9B77",'1'&x"9B78",'1'&x"9B79",'1'&x"9B7A",'1'&x"9B7B",'1'&x"9B7C",'1'&x"9B7D",'1'&x"9B7E",'1'&x"9B7F",
+--'1'&x"9B80",'1'&x"9B81",'1'&x"9B82",'1'&x"9B83",'1'&x"9B84",'1'&x"9B85",'1'&x"9B86",'1'&x"9B87",'1'&x"9B88",'1'&x"9B89",'1'&x"9B8A",'1'&x"9B8B",'1'&x"9B8C",'1'&x"9B8D",'1'&x"9B8E",'1'&x"9B8F",
+--'1'&x"9B90",'1'&x"9B91",'1'&x"9B92",'1'&x"9B93",'1'&x"9B94",'1'&x"9B95",'1'&x"9B96",'1'&x"9B97",'1'&x"9B98",'1'&x"9B99",'1'&x"9B9A",'1'&x"9B9B",'1'&x"9B9C",'1'&x"9B9D",'1'&x"9B9E",'1'&x"9B9F",
+--'1'&x"9BA0",'1'&x"9BA1",'1'&x"9BA2",'1'&x"9BA3",'1'&x"9BA4",'1'&x"9BA5",'1'&x"9BA6",'1'&x"9BA7",'1'&x"9BA8",'1'&x"9BA9",'1'&x"9BAA",'1'&x"9BAB",'1'&x"9BAC",'1'&x"9BAD",'1'&x"9BAE",'1'&x"9BAF",
+--'1'&x"9BB0",'1'&x"9BB1",'1'&x"9BB2",'1'&x"9BB3",'1'&x"9BB4",'1'&x"9BB5",'1'&x"9BB6",'1'&x"9BB7",'1'&x"9BB8",'1'&x"9BB9",'1'&x"9BBA",'1'&x"9BBB",'1'&x"9BBC",'1'&x"9BBD",'1'&x"9BBE",'1'&x"9BBF",
+--'1'&x"9BC0",'1'&x"9BC1",'1'&x"9BC2",'1'&x"9BC3",'1'&x"9BC4",'1'&x"9BC5",'1'&x"9BC6",'1'&x"9BC7",'1'&x"9BC8",'1'&x"9BC9",'1'&x"9BCA",'1'&x"9BCB",'1'&x"9BCC",'1'&x"9BCD",'1'&x"9BCE",'1'&x"9BCF",
+--'1'&x"9BD0",'1'&x"9BD1",'1'&x"9BD2",'1'&x"9BD3",'1'&x"9BD4",'1'&x"9BD5",'1'&x"9BD6",'1'&x"9BD7",'1'&x"9BD8",'1'&x"9BD9",'1'&x"9BDA",'1'&x"9BDB",'1'&x"9BDC",'1'&x"9BDD",'1'&x"9BDE",'1'&x"9BDF",
+--'1'&x"9BE0",'1'&x"9BE1",'1'&x"9BE2",'1'&x"9BE3",'1'&x"9BE4",'1'&x"9BE5",'1'&x"9BE6",'1'&x"9BE7",'1'&x"9BE8",'1'&x"9BE9",'1'&x"9BEA",'1'&x"9BEB",'1'&x"9BEC",'1'&x"9BED",'1'&x"9BEE",'1'&x"9BEF",
+--'1'&x"9BF0",'1'&x"9BF1",'1'&x"9BF2",'1'&x"9BF3",'1'&x"9BF4",'1'&x"9BF5",'1'&x"9BF6",'1'&x"9BF7",'1'&x"9BF8",'1'&x"9BF9",'1'&x"9BFA",'1'&x"9BFB",'1'&x"9BFC",'1'&x"9BFD",'1'&x"9BFE",'1'&x"9BFF",
+--'1'&x"9C00",'1'&x"9C01",'1'&x"9C02",'1'&x"9C03",'1'&x"9C04",'1'&x"9C05",'1'&x"9C06",'1'&x"9C07",'1'&x"9C08",'1'&x"9C09",'1'&x"9C0A",'1'&x"9C0B",'1'&x"9C0C",'1'&x"9C0D",'1'&x"9C0E",'1'&x"9C0F",
+--'1'&x"9C10",'1'&x"9C11",'1'&x"9C12",'1'&x"9C13",'1'&x"9C14",'1'&x"9C15",'1'&x"9C16",'1'&x"9C17",'1'&x"9C18",'1'&x"9C19",'1'&x"9C1A",'1'&x"9C1B",'1'&x"9C1C",'1'&x"9C1D",'1'&x"9C1E",'1'&x"9C1F",
+--'1'&x"9C20",'1'&x"9C21",'1'&x"9C22",'1'&x"9C23",'1'&x"9C24",'1'&x"9C25",'1'&x"9C26",'1'&x"9C27",'1'&x"9C28",'1'&x"9C29",'1'&x"9C2A",'1'&x"9C2B",'1'&x"9C2C",'1'&x"9C2D",'1'&x"9C2E",'1'&x"9C2F",
+--'1'&x"9C30",'1'&x"9C31",'1'&x"9C32",'1'&x"9C33",'1'&x"9C34",'1'&x"9C35",'1'&x"9C36",'1'&x"9C37",'1'&x"9C38",'1'&x"9C39",'1'&x"9C3A",'1'&x"9C3B",'1'&x"9C3C",'1'&x"9C3D",'1'&x"9C3E",'1'&x"9C3F",
+--'1'&x"9C40",'1'&x"9C41",'1'&x"9C42",'1'&x"9C43",'1'&x"9C44",'1'&x"9C45",'1'&x"9C46",'1'&x"9C47",'1'&x"9C48",'1'&x"9C49",'1'&x"9C4A",'1'&x"9C4B",'1'&x"9C4C",'1'&x"9C4D",'1'&x"9C4E",'1'&x"9C4F",
+--'1'&x"9C50",'1'&x"9C51",'1'&x"9C52",'1'&x"9C53",'1'&x"9C54",'1'&x"9C55",'1'&x"9C56",'1'&x"9C57",'1'&x"9C58",'1'&x"9C59",'1'&x"9C5A",'1'&x"9C5B",'1'&x"9C5C",'1'&x"9C5D",'1'&x"9C5E",'1'&x"9C5F",
+--'1'&x"9C60",'1'&x"9C61",'1'&x"9C62",'1'&x"9C63",'1'&x"9C64",'1'&x"9C65",'1'&x"9C66",'1'&x"9C67",'1'&x"9C68",'1'&x"9C69",'1'&x"9C6A",'1'&x"9C6B",'1'&x"9C6C",'1'&x"9C6D",'1'&x"9C6E",'1'&x"9C6F",
+--'1'&x"9C70",'1'&x"9C71",'1'&x"9C72",'1'&x"9C73",'1'&x"9C74",'1'&x"9C75",'1'&x"9C76",'1'&x"9C77",'1'&x"9C78",'1'&x"9C79",'1'&x"9C7A",'1'&x"9C7B",'1'&x"9C7C",'1'&x"9C7D",'1'&x"9C7E",'1'&x"9C7F",
+--'1'&x"9C80",'1'&x"9C81",'1'&x"9C82",'1'&x"9C83",'1'&x"9C84",'1'&x"9C85",'1'&x"9C86",'1'&x"9C87",'1'&x"9C88",'1'&x"9C89",'1'&x"9C8A",'1'&x"9C8B",'1'&x"9C8C",'1'&x"9C8D",'1'&x"9C8E",'1'&x"9C8F",
+--'1'&x"9C90",'1'&x"9C91",'1'&x"9C92",'1'&x"9C93",'1'&x"9C94",'1'&x"9C95",'1'&x"9C96",'1'&x"9C97",'1'&x"9C98",'1'&x"9C99",'1'&x"9C9A",'1'&x"9C9B",'1'&x"9C9C",'1'&x"9C9D",'1'&x"9C9E",'1'&x"9C9F",
+--'1'&x"9CA0",'1'&x"9CA1",'1'&x"9CA2",'1'&x"9CA3",'1'&x"9CA4",'1'&x"9CA5",'1'&x"9CA6",'1'&x"9CA7",'1'&x"9CA8",'1'&x"9CA9",'1'&x"9CAA",'1'&x"9CAB",'1'&x"9CAC",'1'&x"9CAD",'1'&x"9CAE",'1'&x"9CAF",
+--'1'&x"9CB0",'1'&x"9CB1",'1'&x"9CB2",'1'&x"9CB3",'1'&x"9CB4",'1'&x"9CB5",'1'&x"9CB6",'1'&x"9CB7",'1'&x"9CB8",'1'&x"9CB9",'1'&x"9CBA",'1'&x"9CBB",'1'&x"9CBC",'1'&x"9CBD",'1'&x"9CBE",'1'&x"9CBF",
+--'1'&x"9CC0",'1'&x"9CC1",'1'&x"9CC2",'1'&x"9CC3",'1'&x"9CC4",'1'&x"9CC5",'1'&x"9CC6",'1'&x"9CC7",'1'&x"9CC8",'1'&x"9CC9",'1'&x"9CCA",'1'&x"9CCB",'1'&x"9CCC",'1'&x"9CCD",'1'&x"9CCE",'1'&x"9CCF",
+--'1'&x"9CD0",'1'&x"9CD1",'1'&x"9CD2",'1'&x"9CD3",'1'&x"9CD4",'1'&x"9CD5",'1'&x"9CD6",'1'&x"9CD7",'1'&x"9CD8",'1'&x"9CD9",'1'&x"9CDA",'1'&x"9CDB",'1'&x"9CDC",'1'&x"9CDD",'1'&x"9CDE",'1'&x"9CDF",
+--'1'&x"9CE0",'1'&x"9CE1",'1'&x"9CE2",'1'&x"9CE3",'1'&x"9CE4",'1'&x"9CE5",'1'&x"9CE6",'1'&x"9CE7",'1'&x"9CE8",'1'&x"9CE9",'1'&x"9CEA",'1'&x"9CEB",'1'&x"9CEC",'1'&x"9CED",'1'&x"9CEE",'1'&x"9CEF",
+--'1'&x"9CF0",'1'&x"9CF1",'1'&x"9CF2",'1'&x"9CF3",'1'&x"9CF4",'1'&x"9CF5",'1'&x"9CF6",'1'&x"9CF7",'1'&x"9CF8",'1'&x"9CF9",'1'&x"9CFA",'1'&x"9CFB",'1'&x"9CFC",'1'&x"9CFD",'1'&x"9CFE",'1'&x"9CFF",
+--'1'&x"9D00",'1'&x"9D01",'1'&x"9D02",'1'&x"9D03",'1'&x"9D04",'1'&x"9D05",'1'&x"9D06",'1'&x"9D07",'1'&x"9D08",'1'&x"9D09",'1'&x"9D0A",'1'&x"9D0B",'1'&x"9D0C",'1'&x"9D0D",'1'&x"9D0E",'1'&x"9D0F",
+--'1'&x"9D10",'1'&x"9D11",'1'&x"9D12",'1'&x"9D13",'1'&x"9D14",'1'&x"9D15",'1'&x"9D16",'1'&x"9D17",'1'&x"9D18",'1'&x"9D19",'1'&x"9D1A",'1'&x"9D1B",'1'&x"9D1C",'1'&x"9D1D",'1'&x"9D1E",'1'&x"9D1F",
+--'1'&x"9D20",'1'&x"9D21",'1'&x"9D22",'1'&x"9D23",'1'&x"9D24",'1'&x"9D25",'1'&x"9D26",'1'&x"9D27",'1'&x"9D28",'1'&x"9D29",'1'&x"9D2A",'1'&x"9D2B",'1'&x"9D2C",'1'&x"9D2D",'1'&x"9D2E",'1'&x"9D2F",
+--'1'&x"9D30",'1'&x"9D31",'1'&x"9D32",'1'&x"9D33",'1'&x"9D34",'1'&x"9D35",'1'&x"9D36",'1'&x"9D37",'1'&x"9D38",'1'&x"9D39",'1'&x"9D3A",'1'&x"9D3B",'1'&x"9D3C",'1'&x"9D3D",'1'&x"9D3E",'1'&x"9D3F",
+--'1'&x"9D40",'1'&x"9D41",'1'&x"9D42",'1'&x"9D43",'1'&x"9D44",'1'&x"9D45",'1'&x"9D46",'1'&x"9D47",'1'&x"9D48",'1'&x"9D49",'1'&x"9D4A",'1'&x"9D4B",'1'&x"9D4C",'1'&x"9D4D",'1'&x"9D4E",'1'&x"9D4F",
+--'1'&x"9D50",'1'&x"9D51",'1'&x"9D52",'1'&x"9D53",'1'&x"9D54",'1'&x"9D55",'1'&x"9D56",'1'&x"9D57",'1'&x"9D58",'1'&x"9D59",'1'&x"9D5A",'1'&x"9D5B",'1'&x"9D5C",'1'&x"9D5D",'1'&x"9D5E",'1'&x"9D5F",
+--'1'&x"9D60",'1'&x"9D61",'1'&x"9D62",'1'&x"9D63",'1'&x"9D64",'1'&x"9D65",'1'&x"9D66",'1'&x"9D67",'1'&x"9D68",'1'&x"9D69",'1'&x"9D6A",'1'&x"9D6B",'1'&x"9D6C",'1'&x"9D6D",'1'&x"9D6E",'1'&x"9D6F",
+--'1'&x"9D70",'1'&x"9D71",'1'&x"9D72",'1'&x"9D73",'1'&x"9D74",'1'&x"9D75",'1'&x"9D76",'1'&x"9D77",'1'&x"9D78",'1'&x"9D79",'1'&x"9D7A",'1'&x"9D7B",'1'&x"9D7C",'1'&x"9D7D",'1'&x"9D7E",'1'&x"9D7F",
+--'1'&x"9D80",'1'&x"9D81",'1'&x"9D82",'1'&x"9D83",'1'&x"9D84",'1'&x"9D85",'1'&x"9D86",'1'&x"9D87",'1'&x"9D88",'1'&x"9D89",'1'&x"9D8A",'1'&x"9D8B",'1'&x"9D8C",'1'&x"9D8D",'1'&x"9D8E",'1'&x"9D8F",
+--'1'&x"9D90",'1'&x"9D91",'1'&x"9D92",'1'&x"9D93",'1'&x"9D94",'1'&x"9D95",'1'&x"9D96",'1'&x"9D97",'1'&x"9D98",'1'&x"9D99",'1'&x"9D9A",'1'&x"9D9B",'1'&x"9D9C",'1'&x"9D9D",'1'&x"9D9E",'1'&x"9D9F",
+--'1'&x"9DA0",'1'&x"9DA1",'1'&x"9DA2",'1'&x"9DA3",'1'&x"9DA4",'1'&x"9DA5",'1'&x"9DA6",'1'&x"9DA7",'1'&x"9DA8",'1'&x"9DA9",'1'&x"9DAA",'1'&x"9DAB",'1'&x"9DAC",'1'&x"9DAD",'1'&x"9DAE",'1'&x"9DAF",
+--'1'&x"9DB0",'1'&x"9DB1",'1'&x"9DB2",'1'&x"9DB3",'1'&x"9DB4",'1'&x"9DB5",'1'&x"9DB6",'1'&x"9DB7",'1'&x"9DB8",'1'&x"9DB9",'1'&x"9DBA",'1'&x"9DBB",'1'&x"9DBC",'1'&x"9DBD",'1'&x"9DBE",'1'&x"9DBF",
+--'1'&x"9DC0",'1'&x"9DC1",'1'&x"9DC2",'1'&x"9DC3",'1'&x"9DC4",'1'&x"9DC5",'1'&x"9DC6",'1'&x"9DC7",'1'&x"9DC8",'1'&x"9DC9",'1'&x"9DCA",'1'&x"9DCB",'1'&x"9DCC",'1'&x"9DCD",'1'&x"9DCE",'1'&x"9DCF",
+--'1'&x"9DD0",'1'&x"9DD1",'1'&x"9DD2",'1'&x"9DD3",'1'&x"9DD4",'1'&x"9DD5",'1'&x"9DD6",'1'&x"9DD7",'1'&x"9DD8",'1'&x"9DD9",'1'&x"9DDA",'1'&x"9DDB",'1'&x"9DDC",'1'&x"9DDD",'1'&x"9DDE",'1'&x"9DDF",
+--'1'&x"9DE0",'1'&x"9DE1",'1'&x"9DE2",'1'&x"9DE3",'1'&x"9DE4",'1'&x"9DE5",'1'&x"9DE6",'1'&x"9DE7",'1'&x"9DE8",'1'&x"9DE9",'1'&x"9DEA",'1'&x"9DEB",'1'&x"9DEC",'1'&x"9DED",'1'&x"9DEE",'1'&x"9DEF",
+--'1'&x"9DF0",'1'&x"9DF1",'1'&x"9DF2",'1'&x"9DF3",'1'&x"9DF4",'1'&x"9DF5",'1'&x"9DF6",'1'&x"9DF7",'1'&x"9DF8",'1'&x"9DF9",'1'&x"9DFA",'1'&x"9DFB",'1'&x"9DFC",'1'&x"9DFD",'1'&x"9DFE",'1'&x"9DFF",
+--'1'&x"9E00",'1'&x"9E01",'1'&x"9E02",'1'&x"9E03",'1'&x"9E04",'1'&x"9E05",'1'&x"9E06",'1'&x"9E07",'1'&x"9E08",'1'&x"9E09",'1'&x"9E0A",'1'&x"9E0B",'1'&x"9E0C",'1'&x"9E0D",'1'&x"9E0E",'1'&x"9E0F",
+--'1'&x"9E10",'1'&x"9E11",'1'&x"9E12",'1'&x"9E13",'1'&x"9E14",'1'&x"9E15",'1'&x"9E16",'1'&x"9E17",'1'&x"9E18",'1'&x"9E19",'1'&x"9E1A",'1'&x"9E1B",'1'&x"9E1C",'1'&x"9E1D",'1'&x"9E1E",'1'&x"9E1F",
+--'1'&x"9E20",'1'&x"9E21",'1'&x"9E22",'1'&x"9E23",'1'&x"9E24",'1'&x"9E25",'1'&x"9E26",'1'&x"9E27",'1'&x"9E28",'1'&x"9E29",'1'&x"9E2A",'1'&x"9E2B",'1'&x"9E2C",'1'&x"9E2D",'1'&x"9E2E",'1'&x"9E2F",
+--'1'&x"9E30",'1'&x"9E31",'1'&x"9E32",'1'&x"9E33",'1'&x"9E34",'1'&x"9E35",'1'&x"9E36",'1'&x"9E37",'1'&x"9E38",'1'&x"9E39",'1'&x"9E3A",'1'&x"9E3B",'1'&x"9E3C",'1'&x"9E3D",'1'&x"9E3E",'1'&x"9E3F",
+--'1'&x"9E40",'1'&x"9E41",'1'&x"9E42",'1'&x"9E43",'1'&x"9E44",'1'&x"9E45",'1'&x"9E46",'1'&x"9E47",'1'&x"9E48",'1'&x"9E49",'1'&x"9E4A",'1'&x"9E4B",'1'&x"9E4C",'1'&x"9E4D",'1'&x"9E4E",'1'&x"9E4F",
+--'1'&x"9E50",'1'&x"9E51",'1'&x"9E52",'1'&x"9E53",'1'&x"9E54",'1'&x"9E55",'1'&x"9E56",'1'&x"9E57",'1'&x"9E58",'1'&x"9E59",'1'&x"9E5A",'1'&x"9E5B",'1'&x"9E5C",'1'&x"9E5D",'1'&x"9E5E",'1'&x"9E5F",
+--'1'&x"9E60",'1'&x"9E61",'1'&x"9E62",'1'&x"9E63",'1'&x"9E64",'1'&x"9E65",'1'&x"9E66",'1'&x"9E67",'1'&x"9E68",'1'&x"9E69",'1'&x"9E6A",'1'&x"9E6B",'1'&x"9E6C",'1'&x"9E6D",'1'&x"9E6E",'1'&x"9E6F",
+--'1'&x"9E70",'1'&x"9E71",'1'&x"9E72",'1'&x"9E73",'1'&x"9E74",'1'&x"9E75",'1'&x"9E76",'1'&x"9E77",'1'&x"9E78",'1'&x"9E79",'1'&x"9E7A",'1'&x"9E7B",'1'&x"9E7C",'1'&x"9E7D",'1'&x"9E7E",'1'&x"9E7F",
+--'1'&x"9E80",'1'&x"9E81",'1'&x"9E82",'1'&x"9E83",'1'&x"9E84",'1'&x"9E85",'1'&x"9E86",'1'&x"9E87",'1'&x"9E88",'1'&x"9E89",'1'&x"9E8A",'1'&x"9E8B",'1'&x"9E8C",'1'&x"9E8D",'1'&x"9E8E",'1'&x"9E8F",
+--'1'&x"9E90",'1'&x"9E91",'1'&x"9E92",'1'&x"9E93",'1'&x"9E94",'1'&x"9E95",'1'&x"9E96",'1'&x"9E97",'1'&x"9E98",'1'&x"9E99",'1'&x"9E9A",'1'&x"9E9B",'1'&x"9E9C",'1'&x"9E9D",'1'&x"9E9E",'1'&x"9E9F",
+--'1'&x"9EA0",'1'&x"9EA1",'1'&x"9EA2",'1'&x"9EA3",'1'&x"9EA4",'1'&x"9EA5",'1'&x"9EA6",'1'&x"9EA7",'1'&x"9EA8",'1'&x"9EA9",'1'&x"9EAA",'1'&x"9EAB",'1'&x"9EAC",'1'&x"9EAD",'1'&x"9EAE",'1'&x"9EAF",
+--'1'&x"9EB0",'1'&x"9EB1",'1'&x"9EB2",'1'&x"9EB3",'1'&x"9EB4",'1'&x"9EB5",'1'&x"9EB6",'1'&x"9EB7",'1'&x"9EB8",'1'&x"9EB9",'1'&x"9EBA",'1'&x"9EBB",'1'&x"9EBC",'1'&x"9EBD",'1'&x"9EBE",'1'&x"9EBF",
+--'1'&x"9EC0",'1'&x"9EC1",'1'&x"9EC2",'1'&x"9EC3",'1'&x"9EC4",'1'&x"9EC5",'1'&x"9EC6",'1'&x"9EC7",'1'&x"9EC8",'1'&x"9EC9",'1'&x"9ECA",'1'&x"9ECB",'1'&x"9ECC",'1'&x"9ECD",'1'&x"9ECE",'1'&x"9ECF",
+--'1'&x"9ED0",'1'&x"9ED1",'1'&x"9ED2",'1'&x"9ED3",'1'&x"9ED4",'1'&x"9ED5",'1'&x"9ED6",'1'&x"9ED7",'1'&x"9ED8",'1'&x"9ED9",'1'&x"9EDA",'1'&x"9EDB",'1'&x"9EDC",'1'&x"9EDD",'1'&x"9EDE",'1'&x"9EDF",
+--'1'&x"9EE0",'1'&x"9EE1",'1'&x"9EE2",'1'&x"9EE3",'1'&x"9EE4",'1'&x"9EE5",'1'&x"9EE6",'1'&x"9EE7",'1'&x"9EE8",'1'&x"9EE9",'1'&x"9EEA",'1'&x"9EEB",'1'&x"9EEC",'1'&x"9EED",'1'&x"9EEE",'1'&x"9EEF",
+--'1'&x"9EF0",'1'&x"9EF1",'1'&x"9EF2",'1'&x"9EF3",'1'&x"9EF4",'1'&x"9EF5",'1'&x"9EF6",'1'&x"9EF7",'1'&x"9EF8",'1'&x"9EF9",'1'&x"9EFA",'1'&x"9EFB",'1'&x"9EFC",'1'&x"9EFD",'1'&x"9EFE",'1'&x"9EFF",
+--'1'&x"9F00",'1'&x"9F01",'1'&x"9F02",'1'&x"9F03",'1'&x"9F04",'1'&x"9F05",'1'&x"9F06",'1'&x"9F07",'1'&x"9F08",'1'&x"9F09",'1'&x"9F0A",'1'&x"9F0B",'1'&x"9F0C",'1'&x"9F0D",'1'&x"9F0E",'1'&x"9F0F",
+--'1'&x"9F10",'1'&x"9F11",'1'&x"9F12",'1'&x"9F13",'1'&x"9F14",'1'&x"9F15",'1'&x"9F16",'1'&x"9F17",'1'&x"9F18",'1'&x"9F19",'1'&x"9F1A",'1'&x"9F1B",'1'&x"9F1C",'1'&x"9F1D",'1'&x"9F1E",'1'&x"9F1F",
+--'1'&x"9F20",'1'&x"9F21",'1'&x"9F22",'1'&x"9F23",'1'&x"9F24",'1'&x"9F25",'1'&x"9F26",'1'&x"9F27",'1'&x"9F28",'1'&x"9F29",'1'&x"9F2A",'1'&x"9F2B",'1'&x"9F2C",'1'&x"9F2D",'1'&x"9F2E",'1'&x"9F2F",
+--'1'&x"9F30",'1'&x"9F31",'1'&x"9F32",'1'&x"9F33",'1'&x"9F34",'1'&x"9F35",'1'&x"9F36",'1'&x"9F37",'1'&x"9F38",'1'&x"9F39",'1'&x"9F3A",'1'&x"9F3B",'1'&x"9F3C",'1'&x"9F3D",'1'&x"9F3E",'1'&x"9F3F",
+--'1'&x"9F40",'1'&x"9F41",'1'&x"9F42",'1'&x"9F43",'1'&x"9F44",'1'&x"9F45",'1'&x"9F46",'1'&x"9F47",'1'&x"9F48",'1'&x"9F49",'1'&x"9F4A",'1'&x"9F4B",'1'&x"9F4C",'1'&x"9F4D",'1'&x"9F4E",'1'&x"9F4F",
+--'1'&x"9F50",'1'&x"9F51",'1'&x"9F52",'1'&x"9F53",'1'&x"9F54",'1'&x"9F55",'1'&x"9F56",'1'&x"9F57",'1'&x"9F58",'1'&x"9F59",'1'&x"9F5A",'1'&x"9F5B",'1'&x"9F5C",'1'&x"9F5D",'1'&x"9F5E",'1'&x"9F5F",
+--'1'&x"9F60",'1'&x"9F61",'1'&x"9F62",'1'&x"9F63",'1'&x"9F64",'1'&x"9F65",'1'&x"9F66",'1'&x"9F67",'1'&x"9F68",'1'&x"9F69",'1'&x"9F6A",'1'&x"9F6B",'1'&x"9F6C",'1'&x"9F6D",'1'&x"9F6E",'1'&x"9F6F",
+--'1'&x"9F70",'1'&x"9F71",'1'&x"9F72",'1'&x"9F73",'1'&x"9F74",'1'&x"9F75",'1'&x"9F76",'1'&x"9F77",'1'&x"9F78",'1'&x"9F79",'1'&x"9F7A",'1'&x"9F7B",'1'&x"9F7C",'1'&x"9F7D",'1'&x"9F7E",'1'&x"9F7F",
+--'1'&x"9F80",'1'&x"9F81",'1'&x"9F82",'1'&x"9F83",'1'&x"9F84",'1'&x"9F85",'1'&x"9F86",'1'&x"9F87",'1'&x"9F88",'1'&x"9F89",'1'&x"9F8A",'1'&x"9F8B",'1'&x"9F8C",'1'&x"9F8D",'1'&x"9F8E",'1'&x"9F8F",
+--'1'&x"9F90",'1'&x"9F91",'1'&x"9F92",'1'&x"9F93",'1'&x"9F94",'1'&x"9F95",'1'&x"9F96",'1'&x"9F97",'1'&x"9F98",'1'&x"9F99",'1'&x"9F9A",'1'&x"9F9B",'1'&x"9F9C",'1'&x"9F9D",'1'&x"9F9E",'1'&x"9F9F",
+--'1'&x"9FA0",'1'&x"9FA1",'1'&x"9FA2",'1'&x"9FA3",'1'&x"9FA4",'1'&x"9FA5",'1'&x"9FA6",'1'&x"9FA7",'1'&x"9FA8",'1'&x"9FA9",'1'&x"9FAA",'1'&x"9FAB",'1'&x"9FAC",'1'&x"9FAD",'1'&x"9FAE",'1'&x"9FAF",
+--'1'&x"9FB0",'1'&x"9FB1",'1'&x"9FB2",'1'&x"9FB3",'1'&x"9FB4",'1'&x"9FB5",'1'&x"9FB6",'1'&x"9FB7",'1'&x"9FB8",'1'&x"9FB9",'1'&x"9FBA",'1'&x"9FBB",'1'&x"9FBC",'1'&x"9FBD",'1'&x"9FBE",'1'&x"9FBF",
+--'1'&x"9FC0",'1'&x"9FC1",'1'&x"9FC2",'1'&x"9FC3",'1'&x"9FC4",'1'&x"9FC5",'1'&x"9FC6",'1'&x"9FC7",'1'&x"9FC8",'1'&x"9FC9",'1'&x"9FCA",'1'&x"9FCB",'1'&x"9FCC",'1'&x"9FCD",'1'&x"9FCE",'1'&x"9FCF",
+--'1'&x"9FD0",'1'&x"9FD1",'1'&x"9FD2",'1'&x"9FD3",'1'&x"9FD4",'1'&x"9FD5",'1'&x"9FD6",'1'&x"9FD7",'1'&x"9FD8",'1'&x"9FD9",'1'&x"9FDA",'1'&x"9FDB",'1'&x"9FDC",'1'&x"9FDD",'1'&x"9FDE",'1'&x"9FDF",
+--'1'&x"9FE0",'1'&x"9FE1",'1'&x"9FE2",'1'&x"9FE3",'1'&x"9FE4",'1'&x"9FE5",'1'&x"9FE6",'1'&x"9FE7",'1'&x"9FE8",'1'&x"9FE9",'1'&x"9FEA",'1'&x"9FEB",'1'&x"9FEC",'1'&x"9FED",'1'&x"9FEE",'1'&x"9FEF",
+--'1'&x"9FF0",'1'&x"9FF1",'1'&x"9FF2",'1'&x"9FF3",'1'&x"9FF4",'1'&x"9FF5",'1'&x"9FF6",'1'&x"9FF7",'1'&x"9FF8",'1'&x"9FF9",'1'&x"9FFA",'1'&x"9FFB",'1'&x"9FFC",'1'&x"9FFD",'1'&x"9FFE",'1'&x"9FFF",
+--'1'&x"A000",'1'&x"A001",'1'&x"A002",'1'&x"A003",'1'&x"A004",'1'&x"A005",'1'&x"A006",'1'&x"A007",'1'&x"A008",'1'&x"A009",'1'&x"A00A",'1'&x"A00B",'1'&x"A00C",'1'&x"A00D",'1'&x"A00E",'1'&x"A00F",
+--'1'&x"A010",'1'&x"A011",'1'&x"A012",'1'&x"A013",'1'&x"A014",'1'&x"A015",'1'&x"A016",'1'&x"A017",'1'&x"A018",'1'&x"A019",'1'&x"A01A",'1'&x"A01B",'1'&x"A01C",'1'&x"A01D",'1'&x"A01E",'1'&x"A01F",
+--'1'&x"A020",'1'&x"A021",'1'&x"A022",'1'&x"A023",'1'&x"A024",'1'&x"A025",'1'&x"A026",'1'&x"A027",'1'&x"A028",'1'&x"A029",'1'&x"A02A",'1'&x"A02B",'1'&x"A02C",'1'&x"A02D",'1'&x"A02E",'1'&x"A02F",
+--'1'&x"A030",'1'&x"A031",'1'&x"A032",'1'&x"A033",'1'&x"A034",'1'&x"A035",'1'&x"A036",'1'&x"A037",'1'&x"A038",'1'&x"A039",'1'&x"A03A",'1'&x"A03B",'1'&x"A03C",'1'&x"A03D",'1'&x"A03E",'1'&x"A03F",
+--'1'&x"A040",'1'&x"A041",'1'&x"A042",'1'&x"A043",'1'&x"A044",'1'&x"A045",'1'&x"A046",'1'&x"A047",'1'&x"A048",'1'&x"A049",'1'&x"A04A",'1'&x"A04B",'1'&x"A04C",'1'&x"A04D",'1'&x"A04E",'1'&x"A04F",
+--'1'&x"A050",'1'&x"A051",'1'&x"A052",'1'&x"A053",'1'&x"A054",'1'&x"A055",'1'&x"A056",'1'&x"A057",'1'&x"A058",'1'&x"A059",'1'&x"A05A",'1'&x"A05B",'1'&x"A05C",'1'&x"A05D",'1'&x"A05E",'1'&x"A05F",
+--'1'&x"A060",'1'&x"A061",'1'&x"A062",'1'&x"A063",'1'&x"A064",'1'&x"A065",'1'&x"A066",'1'&x"A067",'1'&x"A068",'1'&x"A069",'1'&x"A06A",'1'&x"A06B",'1'&x"A06C",'1'&x"A06D",'1'&x"A06E",'1'&x"A06F",
+--'1'&x"A070",'1'&x"A071",'1'&x"A072",'1'&x"A073",'1'&x"A074",'1'&x"A075",'1'&x"A076",'1'&x"A077",'1'&x"A078",'1'&x"A079",'1'&x"A07A",'1'&x"A07B",'1'&x"A07C",'1'&x"A07D",'1'&x"A07E",'1'&x"A07F",
+--'1'&x"A080",'1'&x"A081",'1'&x"A082",'1'&x"A083",'1'&x"A084",'1'&x"A085",'1'&x"A086",'1'&x"A087",'1'&x"A088",'1'&x"A089",'1'&x"A08A",'1'&x"A08B",'1'&x"A08C",'1'&x"A08D",'1'&x"A08E",'1'&x"A08F",
+--'1'&x"A090",'1'&x"A091",'1'&x"A092",'1'&x"A093",'1'&x"A094",'1'&x"A095",'1'&x"A096",'1'&x"A097",'1'&x"A098",'1'&x"A099",'1'&x"A09A",'1'&x"A09B",'1'&x"A09C",'1'&x"A09D",'1'&x"A09E",'1'&x"A09F",
+--'1'&x"A0A0",'1'&x"A0A1",'1'&x"A0A2",'1'&x"A0A3",'1'&x"A0A4",'1'&x"A0A5",'1'&x"A0A6",'1'&x"A0A7",'1'&x"A0A8",'1'&x"A0A9",'1'&x"A0AA",'1'&x"A0AB",'1'&x"A0AC",'1'&x"A0AD",'1'&x"A0AE",'1'&x"A0AF",
+--'1'&x"A0B0",'1'&x"A0B1",'1'&x"A0B2",'1'&x"A0B3",'1'&x"A0B4",'1'&x"A0B5",'1'&x"A0B6",'1'&x"A0B7",'1'&x"A0B8",'1'&x"A0B9",'1'&x"A0BA",'1'&x"A0BB",'1'&x"A0BC",'1'&x"A0BD",'1'&x"A0BE",'1'&x"A0BF",
+--'1'&x"A0C0",'1'&x"A0C1",'1'&x"A0C2",'1'&x"A0C3",'1'&x"A0C4",'1'&x"A0C5",'1'&x"A0C6",'1'&x"A0C7",'1'&x"A0C8",'1'&x"A0C9",'1'&x"A0CA",'1'&x"A0CB",'1'&x"A0CC",'1'&x"A0CD",'1'&x"A0CE",'1'&x"A0CF",
+--'1'&x"A0D0",'1'&x"A0D1",'1'&x"A0D2",'1'&x"A0D3",'1'&x"A0D4",'1'&x"A0D5",'1'&x"A0D6",'1'&x"A0D7",'1'&x"A0D8",'1'&x"A0D9",'1'&x"A0DA",'1'&x"A0DB",'1'&x"A0DC",'1'&x"A0DD",'1'&x"A0DE",'1'&x"A0DF",
+--'1'&x"A0E0",'1'&x"A0E1",'1'&x"A0E2",'1'&x"A0E3",'1'&x"A0E4",'1'&x"A0E5",'1'&x"A0E6",'1'&x"A0E7",'1'&x"A0E8",'1'&x"A0E9",'1'&x"A0EA",'1'&x"A0EB",'1'&x"A0EC",'1'&x"A0ED",'1'&x"A0EE",'1'&x"A0EF",
+--'1'&x"A0F0",'1'&x"A0F1",'1'&x"A0F2",'1'&x"A0F3",'1'&x"A0F4",'1'&x"A0F5",'1'&x"A0F6",'1'&x"A0F7",'1'&x"A0F8",'1'&x"A0F9",'1'&x"A0FA",'1'&x"A0FB",'1'&x"A0FC",'1'&x"A0FD",'1'&x"A0FE",'1'&x"A0FF",
+--'1'&x"A100",'1'&x"A101",'1'&x"A102",'1'&x"A103",'1'&x"A104",'1'&x"A105",'1'&x"A106",'1'&x"A107",'1'&x"A108",'1'&x"A109",'1'&x"A10A",'1'&x"A10B",'1'&x"A10C",'1'&x"A10D",'1'&x"A10E",'1'&x"A10F",
+--'1'&x"A110",'1'&x"A111",'1'&x"A112",'1'&x"A113",'1'&x"A114",'1'&x"A115",'1'&x"A116",'1'&x"A117",'1'&x"A118",'1'&x"A119",'1'&x"A11A",'1'&x"A11B",'1'&x"A11C",'1'&x"A11D",'1'&x"A11E",'1'&x"A11F",
+--'1'&x"A120",'1'&x"A121",'1'&x"A122",'1'&x"A123",'1'&x"A124",'1'&x"A125",'1'&x"A126",'1'&x"A127",'1'&x"A128",'1'&x"A129",'1'&x"A12A",'1'&x"A12B",'1'&x"A12C",'1'&x"A12D",'1'&x"A12E",'1'&x"A12F",
+--'1'&x"A130",'1'&x"A131",'1'&x"A132",'1'&x"A133",'1'&x"A134",'1'&x"A135",'1'&x"A136",'1'&x"A137",'1'&x"A138",'1'&x"A139",'1'&x"A13A",'1'&x"A13B",'1'&x"A13C",'1'&x"A13D",'1'&x"A13E",'1'&x"A13F",
+--'1'&x"A140",'1'&x"A141",'1'&x"A142",'1'&x"A143",'1'&x"A144",'1'&x"A145",'1'&x"A146",'1'&x"A147",'1'&x"A148",'1'&x"A149",'1'&x"A14A",'1'&x"A14B",'1'&x"A14C",'1'&x"A14D",'1'&x"A14E",'1'&x"A14F",
+--'1'&x"A150",'1'&x"A151",'1'&x"A152",'1'&x"A153",'1'&x"A154",'1'&x"A155",'1'&x"A156",'1'&x"A157",'1'&x"A158",'1'&x"A159",'1'&x"A15A",'1'&x"A15B",'1'&x"A15C",'1'&x"A15D",'1'&x"A15E",'1'&x"A15F",
+--'1'&x"A160",'1'&x"A161",'1'&x"A162",'1'&x"A163",'1'&x"A164",'1'&x"A165",'1'&x"A166",'1'&x"A167",'1'&x"A168",'1'&x"A169",'1'&x"A16A",'1'&x"A16B",'1'&x"A16C",'1'&x"A16D",'1'&x"A16E",'1'&x"A16F",
+--'1'&x"A170",'1'&x"A171",'1'&x"A172",'1'&x"A173",'1'&x"A174",'1'&x"A175",'1'&x"A176",'1'&x"A177",'1'&x"A178",'1'&x"A179",'1'&x"A17A",'1'&x"A17B",'1'&x"A17C",'1'&x"A17D",'1'&x"A17E",'1'&x"A17F",
+--'1'&x"A180",'1'&x"A181",'1'&x"A182",'1'&x"A183",'1'&x"A184",'1'&x"A185",'1'&x"A186",'1'&x"A187",'1'&x"A188",'1'&x"A189",'1'&x"A18A",'1'&x"A18B",'1'&x"A18C",'1'&x"A18D",'1'&x"A18E",'1'&x"A18F",
+--'1'&x"A190",'1'&x"A191",'1'&x"A192",'1'&x"A193",'1'&x"A194",'1'&x"A195",'1'&x"A196",'1'&x"A197",'1'&x"A198",'1'&x"A199",'1'&x"A19A",'1'&x"A19B",'1'&x"A19C",'1'&x"A19D",'1'&x"A19E",'1'&x"A19F",
+--'1'&x"A1A0",'1'&x"A1A1",'1'&x"A1A2",'1'&x"A1A3",'1'&x"A1A4",'1'&x"A1A5",'1'&x"A1A6",'1'&x"A1A7",'1'&x"A1A8",'1'&x"A1A9",'1'&x"A1AA",'1'&x"A1AB",'1'&x"A1AC",'1'&x"A1AD",'1'&x"A1AE",'1'&x"A1AF",
+--'1'&x"A1B0",'1'&x"A1B1",'1'&x"A1B2",'1'&x"A1B3",'1'&x"A1B4",'1'&x"A1B5",'1'&x"A1B6",'1'&x"A1B7",'1'&x"A1B8",'1'&x"A1B9",'1'&x"A1BA",'1'&x"A1BB",'1'&x"A1BC",'1'&x"A1BD",'1'&x"A1BE",'1'&x"A1BF",
+--'1'&x"A1C0",'1'&x"A1C1",'1'&x"A1C2",'1'&x"A1C3",'1'&x"A1C4",'1'&x"A1C5",'1'&x"A1C6",'1'&x"A1C7",'1'&x"A1C8",'1'&x"A1C9",'1'&x"A1CA",'1'&x"A1CB",'1'&x"A1CC",'1'&x"A1CD",'1'&x"A1CE",'1'&x"A1CF",
+--'1'&x"A1D0",'1'&x"A1D1",'1'&x"A1D2",'1'&x"A1D3",'1'&x"A1D4",'1'&x"A1D5",'1'&x"A1D6",'1'&x"A1D7",'1'&x"A1D8",'1'&x"A1D9",'1'&x"A1DA",'1'&x"A1DB",'1'&x"A1DC",'1'&x"A1DD",'1'&x"A1DE",'1'&x"A1DF",
+--'1'&x"A1E0",'1'&x"A1E1",'1'&x"A1E2",'1'&x"A1E3",'1'&x"A1E4",'1'&x"A1E5",'1'&x"A1E6",'1'&x"A1E7",'1'&x"A1E8",'1'&x"A1E9",'1'&x"A1EA",'1'&x"A1EB",'1'&x"A1EC",'1'&x"A1ED",'1'&x"A1EE",'1'&x"A1EF",
+--'1'&x"A1F0",'1'&x"A1F1",'1'&x"A1F2",'1'&x"A1F3",'1'&x"A1F4",'1'&x"A1F5",'1'&x"A1F6",'1'&x"A1F7",'1'&x"A1F8",'1'&x"A1F9",'1'&x"A1FA",'1'&x"A1FB",'1'&x"A1FC",'1'&x"A1FD",'1'&x"A1FE",'1'&x"A1FF",
+--'1'&x"A200",'1'&x"A201",'1'&x"A202",'1'&x"A203",'1'&x"A204",'1'&x"A205",'1'&x"A206",'1'&x"A207",'1'&x"A208",'1'&x"A209",'1'&x"A20A",'1'&x"A20B",'1'&x"A20C",'1'&x"A20D",'1'&x"A20E",'1'&x"A20F",
+--'1'&x"A210",'1'&x"A211",'1'&x"A212",'1'&x"A213",'1'&x"A214",'1'&x"A215",'1'&x"A216",'1'&x"A217",'1'&x"A218",'1'&x"A219",'1'&x"A21A",'1'&x"A21B",'1'&x"A21C",'1'&x"A21D",'1'&x"A21E",'1'&x"A21F",
+--'1'&x"A220",'1'&x"A221",'1'&x"A222",'1'&x"A223",'1'&x"A224",'1'&x"A225",'1'&x"A226",'1'&x"A227",'1'&x"A228",'1'&x"A229",'1'&x"A22A",'1'&x"A22B",'1'&x"A22C",'1'&x"A22D",'1'&x"A22E",'1'&x"A22F",
+--'1'&x"A230",'1'&x"A231",'1'&x"A232",'1'&x"A233",'1'&x"A234",'1'&x"A235",'1'&x"A236",'1'&x"A237",'1'&x"A238",'1'&x"A239",'1'&x"A23A",'1'&x"A23B",'1'&x"A23C",'1'&x"A23D",'1'&x"A23E",'1'&x"A23F",
+--'1'&x"A240",'1'&x"A241",'1'&x"A242",'1'&x"A243",'1'&x"A244",'1'&x"A245",'1'&x"A246",'1'&x"A247",'1'&x"A248",'1'&x"A249",'1'&x"A24A",'1'&x"A24B",'1'&x"A24C",'1'&x"A24D",'1'&x"A24E",'1'&x"A24F",
+--'1'&x"A250",'1'&x"A251",'1'&x"A252",'1'&x"A253",'1'&x"A254",'1'&x"A255",'1'&x"A256",'1'&x"A257",'1'&x"A258",'1'&x"A259",'1'&x"A25A",'1'&x"A25B",'1'&x"A25C",'1'&x"A25D",'1'&x"A25E",'1'&x"A25F",
+--'1'&x"A260",'1'&x"A261",'1'&x"A262",'1'&x"A263",'1'&x"A264",'1'&x"A265",'1'&x"A266",'1'&x"A267",'1'&x"A268",'1'&x"A269",'1'&x"A26A",'1'&x"A26B",'1'&x"A26C",'1'&x"A26D",'1'&x"A26E",'1'&x"A26F",
+--'1'&x"A270",'1'&x"A271",'1'&x"A272",'1'&x"A273",'1'&x"A274",'1'&x"A275",'1'&x"A276",'1'&x"A277",'1'&x"A278",'1'&x"A279",'1'&x"A27A",'1'&x"A27B",'1'&x"A27C",'1'&x"A27D",'1'&x"A27E",'1'&x"A27F",
+--'1'&x"A280",'1'&x"A281",'1'&x"A282",'1'&x"A283",'1'&x"A284",'1'&x"A285",'1'&x"A286",'1'&x"A287",'1'&x"A288",'1'&x"A289",'1'&x"A28A",'1'&x"A28B",'1'&x"A28C",'1'&x"A28D",'1'&x"A28E",'1'&x"A28F",
+--'1'&x"A290",'1'&x"A291",'1'&x"A292",'1'&x"A293",'1'&x"A294",'1'&x"A295",'1'&x"A296",'1'&x"A297",'1'&x"A298",'1'&x"A299",'1'&x"A29A",'1'&x"A29B",'1'&x"A29C",'1'&x"A29D",'1'&x"A29E",'1'&x"A29F",
+--'1'&x"A2A0",'1'&x"A2A1",'1'&x"A2A2",'1'&x"A2A3",'1'&x"A2A4",'1'&x"A2A5",'1'&x"A2A6",'1'&x"A2A7",'1'&x"A2A8",'1'&x"A2A9",'1'&x"A2AA",'1'&x"A2AB",'1'&x"A2AC",'1'&x"A2AD",'1'&x"A2AE",'1'&x"A2AF",
+--'1'&x"A2B0",'1'&x"A2B1",'1'&x"A2B2",'1'&x"A2B3",'1'&x"A2B4",'1'&x"A2B5",'1'&x"A2B6",'1'&x"A2B7",'1'&x"A2B8",'1'&x"A2B9",'1'&x"A2BA",'1'&x"A2BB",'1'&x"A2BC",'1'&x"A2BD",'1'&x"A2BE",'1'&x"A2BF",
+--'1'&x"A2C0",'1'&x"A2C1",'1'&x"A2C2",'1'&x"A2C3",'1'&x"A2C4",'1'&x"A2C5",'1'&x"A2C6",'1'&x"A2C7",'1'&x"A2C8",'1'&x"A2C9",'1'&x"A2CA",'1'&x"A2CB",'1'&x"A2CC",'1'&x"A2CD",'1'&x"A2CE",'1'&x"A2CF",
+--'1'&x"A2D0",'1'&x"A2D1",'1'&x"A2D2",'1'&x"A2D3",'1'&x"A2D4",'1'&x"A2D5",'1'&x"A2D6",'1'&x"A2D7",'1'&x"A2D8",'1'&x"A2D9",'1'&x"A2DA",'1'&x"A2DB",'1'&x"A2DC",'1'&x"A2DD",'1'&x"A2DE",'1'&x"A2DF",
+--'1'&x"A2E0",'1'&x"A2E1",'1'&x"A2E2",'1'&x"A2E3",'1'&x"A2E4",'1'&x"A2E5",'1'&x"A2E6",'1'&x"A2E7",'1'&x"A2E8",'1'&x"A2E9",'1'&x"A2EA",'1'&x"A2EB",'1'&x"A2EC",'1'&x"A2ED",'1'&x"A2EE",'1'&x"A2EF",
+--'1'&x"A2F0",'1'&x"A2F1",'1'&x"A2F2",'1'&x"A2F3",'1'&x"A2F4",'1'&x"A2F5",'1'&x"A2F6",'1'&x"A2F7",'1'&x"A2F8",'1'&x"A2F9",'1'&x"A2FA",'1'&x"A2FB",'1'&x"A2FC",'1'&x"A2FD",'1'&x"A2FE",'1'&x"A2FF",
+--'1'&x"A300",'1'&x"A301",'1'&x"A302",'1'&x"A303",'1'&x"A304",'1'&x"A305",'1'&x"A306",'1'&x"A307",'1'&x"A308",'1'&x"A309",'1'&x"A30A",'1'&x"A30B",'1'&x"A30C",'1'&x"A30D",'1'&x"A30E",'1'&x"A30F",
+--'1'&x"A310",'1'&x"A311",'1'&x"A312",'1'&x"A313",'1'&x"A314",'1'&x"A315",'1'&x"A316",'1'&x"A317",'1'&x"A318",'1'&x"A319",'1'&x"A31A",'1'&x"A31B",'1'&x"A31C",'1'&x"A31D",'1'&x"A31E",'1'&x"A31F",
+--'1'&x"A320",'1'&x"A321",'1'&x"A322",'1'&x"A323",'1'&x"A324",'1'&x"A325",'1'&x"A326",'1'&x"A327",'1'&x"A328",'1'&x"A329",'1'&x"A32A",'1'&x"A32B",'1'&x"A32C",'1'&x"A32D",'1'&x"A32E",'1'&x"A32F",
+--'1'&x"A330",'1'&x"A331",'1'&x"A332",'1'&x"A333",'1'&x"A334",'1'&x"A335",'1'&x"A336",'1'&x"A337",'1'&x"A338",'1'&x"A339",'1'&x"A33A",'1'&x"A33B",'1'&x"A33C",'1'&x"A33D",'1'&x"A33E",'1'&x"A33F",
+--'1'&x"A340",'1'&x"A341",'1'&x"A342",'1'&x"A343",'1'&x"A344",'1'&x"A345",'1'&x"A346",'1'&x"A347",'1'&x"A348",'1'&x"A349",'1'&x"A34A",'1'&x"A34B",'1'&x"A34C",'1'&x"A34D",'1'&x"A34E",'1'&x"A34F",
+--'1'&x"A350",'1'&x"A351",'1'&x"A352",'1'&x"A353",'1'&x"A354",'1'&x"A355",'1'&x"A356",'1'&x"A357",'1'&x"A358",'1'&x"A359",'1'&x"A35A",'1'&x"A35B",'1'&x"A35C",'1'&x"A35D",'1'&x"A35E",'1'&x"A35F",
+--'1'&x"A360",'1'&x"A361",'1'&x"A362",'1'&x"A363",'1'&x"A364",'1'&x"A365",'1'&x"A366",'1'&x"A367",'1'&x"A368",'1'&x"A369",'1'&x"A36A",'1'&x"A36B",'1'&x"A36C",'1'&x"A36D",'1'&x"A36E",'1'&x"A36F",
+--'1'&x"A370",'1'&x"A371",'1'&x"A372",'1'&x"A373",'1'&x"A374",'1'&x"A375",'1'&x"A376",'1'&x"A377",'1'&x"A378",'1'&x"A379",'1'&x"A37A",'1'&x"A37B",'1'&x"A37C",'1'&x"A37D",'1'&x"A37E",'1'&x"A37F",
+--'1'&x"A380",'1'&x"A381",'1'&x"A382",'1'&x"A383",'1'&x"A384",'1'&x"A385",'1'&x"A386",'1'&x"A387",'1'&x"A388",'1'&x"A389",'1'&x"A38A",'1'&x"A38B",'1'&x"A38C",'1'&x"A38D",'1'&x"A38E",'1'&x"A38F",
+--'1'&x"A390",'1'&x"A391",'1'&x"A392",'1'&x"A393",'1'&x"A394",'1'&x"A395",'1'&x"A396",'1'&x"A397",'1'&x"A398",'1'&x"A399",'1'&x"A39A",'1'&x"A39B",'1'&x"A39C",'1'&x"A39D",'1'&x"A39E",'1'&x"A39F",
+--'1'&x"A3A0",'1'&x"A3A1",'1'&x"A3A2",'1'&x"A3A3",'1'&x"A3A4",'1'&x"A3A5",'1'&x"A3A6",'1'&x"A3A7",'1'&x"A3A8",'1'&x"A3A9",'1'&x"A3AA",'1'&x"A3AB",'1'&x"A3AC",'1'&x"A3AD",'1'&x"A3AE",'1'&x"A3AF",
+--'1'&x"A3B0",'1'&x"A3B1",'1'&x"A3B2",'1'&x"A3B3",'1'&x"A3B4",'1'&x"A3B5",'1'&x"A3B6",'1'&x"A3B7",'1'&x"A3B8",'1'&x"A3B9",'1'&x"A3BA",'1'&x"A3BB",'1'&x"A3BC",'1'&x"A3BD",'1'&x"A3BE",'1'&x"A3BF",
+--'1'&x"A3C0",'1'&x"A3C1",'1'&x"A3C2",'1'&x"A3C3",'1'&x"A3C4",'1'&x"A3C5",'1'&x"A3C6",'1'&x"A3C7",'1'&x"A3C8",'1'&x"A3C9",'1'&x"A3CA",'1'&x"A3CB",'1'&x"A3CC",'1'&x"A3CD",'1'&x"A3CE",'1'&x"A3CF",
+--'1'&x"A3D0",'1'&x"A3D1",'1'&x"A3D2",'1'&x"A3D3",'1'&x"A3D4",'1'&x"A3D5",'1'&x"A3D6",'1'&x"A3D7",'1'&x"A3D8",'1'&x"A3D9",'1'&x"A3DA",'1'&x"A3DB",'1'&x"A3DC",'1'&x"A3DD",'1'&x"A3DE",'1'&x"A3DF",
+--'1'&x"A3E0",'1'&x"A3E1",'1'&x"A3E2",'1'&x"A3E3",'1'&x"A3E4",'1'&x"A3E5",'1'&x"A3E6",'1'&x"A3E7",'1'&x"A3E8",'1'&x"A3E9",'1'&x"A3EA",'1'&x"A3EB",'1'&x"A3EC",'1'&x"A3ED",'1'&x"A3EE",'1'&x"A3EF",
+--'1'&x"A3F0",'1'&x"A3F1",'1'&x"A3F2",'1'&x"A3F3",'1'&x"A3F4",'1'&x"A3F5",'1'&x"A3F6",'1'&x"A3F7",'1'&x"A3F8",'1'&x"A3F9",'1'&x"A3FA",'1'&x"A3FB",'1'&x"A3FC",'1'&x"A3FD",'1'&x"A3FE",'1'&x"A3FF",
+--'1'&x"A400",'1'&x"A401",'1'&x"A402",'1'&x"A403",'1'&x"A404",'1'&x"A405",'1'&x"A406",'1'&x"A407",'1'&x"A408",'1'&x"A409",'1'&x"A40A",'1'&x"A40B",'1'&x"A40C",'1'&x"A40D",'1'&x"A40E",'1'&x"A40F",
+--'1'&x"A410",'1'&x"A411",'1'&x"A412",'1'&x"A413",'1'&x"A414",'1'&x"A415",'1'&x"A416",'1'&x"A417",'1'&x"A418",'1'&x"A419",'1'&x"A41A",'1'&x"A41B",'1'&x"A41C",'1'&x"A41D",'1'&x"A41E",'1'&x"A41F",
+--'1'&x"A420",'1'&x"A421",'1'&x"A422",'1'&x"A423",'1'&x"A424",'1'&x"A425",'1'&x"A426",'1'&x"A427",'1'&x"A428",'1'&x"A429",'1'&x"A42A",'1'&x"A42B",'1'&x"A42C",'1'&x"A42D",'1'&x"A42E",'1'&x"A42F",
+--'1'&x"A430",'1'&x"A431",'1'&x"A432",'1'&x"A433",'1'&x"A434",'1'&x"A435",'1'&x"A436",'1'&x"A437",'1'&x"A438",'1'&x"A439",'1'&x"A43A",'1'&x"A43B",'1'&x"A43C",'1'&x"A43D",'1'&x"A43E",'1'&x"A43F",
+--'1'&x"A440",'1'&x"A441",'1'&x"A442",'1'&x"A443",'1'&x"A444",'1'&x"A445",'1'&x"A446",'1'&x"A447",'1'&x"A448",'1'&x"A449",'1'&x"A44A",'1'&x"A44B",'1'&x"A44C",'1'&x"A44D",'1'&x"A44E",'1'&x"A44F",
+--'1'&x"A450",'1'&x"A451",'1'&x"A452",'1'&x"A453",'1'&x"A454",'1'&x"A455",'1'&x"A456",'1'&x"A457",'1'&x"A458",'1'&x"A459",'1'&x"A45A",'1'&x"A45B",'1'&x"A45C",'1'&x"A45D",'1'&x"A45E",'1'&x"A45F",
+--'1'&x"A460",'1'&x"A461",'1'&x"A462",'1'&x"A463",'1'&x"A464",'1'&x"A465",'1'&x"A466",'1'&x"A467",'1'&x"A468",'1'&x"A469",'1'&x"A46A",'1'&x"A46B",'1'&x"A46C",'1'&x"A46D",'1'&x"A46E",'1'&x"A46F",
+--'1'&x"A470",'1'&x"A471",'1'&x"A472",'1'&x"A473",'1'&x"A474",'1'&x"A475",'1'&x"A476",'1'&x"A477",'1'&x"A478",'1'&x"A479",'1'&x"A47A",'1'&x"A47B",'1'&x"A47C",'1'&x"A47D",'1'&x"A47E",'1'&x"A47F",
+--'1'&x"A480",'1'&x"A481",'1'&x"A482",'1'&x"A483",'1'&x"A484",'1'&x"A485",'1'&x"A486",'1'&x"A487",'1'&x"A488",'1'&x"A489",'1'&x"A48A",'1'&x"A48B",'1'&x"A48C",'1'&x"A48D",'1'&x"A48E",'1'&x"A48F",
+--'1'&x"A490",'1'&x"A491",'1'&x"A492",'1'&x"A493",'1'&x"A494",'1'&x"A495",'1'&x"A496",'1'&x"A497",'1'&x"A498",'1'&x"A499",'1'&x"A49A",'1'&x"A49B",'1'&x"A49C",'1'&x"A49D",'1'&x"A49E",'1'&x"A49F",
+--'1'&x"A4A0",'1'&x"A4A1",'1'&x"A4A2",'1'&x"A4A3",'1'&x"A4A4",'1'&x"A4A5",'1'&x"A4A6",'1'&x"A4A7",'1'&x"A4A8",'1'&x"A4A9",'1'&x"A4AA",'1'&x"A4AB",'1'&x"A4AC",'1'&x"A4AD",'1'&x"A4AE",'1'&x"A4AF",
+--'1'&x"A4B0",'1'&x"A4B1",'1'&x"A4B2",'1'&x"A4B3",'1'&x"A4B4",'1'&x"A4B5",'1'&x"A4B6",'1'&x"A4B7",'1'&x"A4B8",'1'&x"A4B9",'1'&x"A4BA",'1'&x"A4BB",'1'&x"A4BC",'1'&x"A4BD",'1'&x"A4BE",'1'&x"A4BF",
+--'1'&x"A4C0",'1'&x"A4C1",'1'&x"A4C2",'1'&x"A4C3",'1'&x"A4C4",'1'&x"A4C5",'1'&x"A4C6",'1'&x"A4C7",'1'&x"A4C8",'1'&x"A4C9",'1'&x"A4CA",'1'&x"A4CB",'1'&x"A4CC",'1'&x"A4CD",'1'&x"A4CE",'1'&x"A4CF",
+--'1'&x"A4D0",'1'&x"A4D1",'1'&x"A4D2",'1'&x"A4D3",'1'&x"A4D4",'1'&x"A4D5",'1'&x"A4D6",'1'&x"A4D7",'1'&x"A4D8",'1'&x"A4D9",'1'&x"A4DA",'1'&x"A4DB",'1'&x"A4DC",'1'&x"A4DD",'1'&x"A4DE",'1'&x"A4DF",
+--'1'&x"A4E0",'1'&x"A4E1",'1'&x"A4E2",'1'&x"A4E3",'1'&x"A4E4",'1'&x"A4E5",'1'&x"A4E6",'1'&x"A4E7",'1'&x"A4E8",'1'&x"A4E9",'1'&x"A4EA",'1'&x"A4EB",'1'&x"A4EC",'1'&x"A4ED",'1'&x"A4EE",'1'&x"A4EF",
+--'1'&x"A4F0",'1'&x"A4F1",'1'&x"A4F2",'1'&x"A4F3",'1'&x"A4F4",'1'&x"A4F5",'1'&x"A4F6",'1'&x"A4F7",'1'&x"A4F8",'1'&x"A4F9",'1'&x"A4FA",'1'&x"A4FB",'1'&x"A4FC",'1'&x"A4FD",'1'&x"A4FE",'1'&x"A4FF",
+--'1'&x"A500",'1'&x"A501",'1'&x"A502",'1'&x"A503",'1'&x"A504",'1'&x"A505",'1'&x"A506",'1'&x"A507",'1'&x"A508",'1'&x"A509",'1'&x"A50A",'1'&x"A50B",'1'&x"A50C",'1'&x"A50D",'1'&x"A50E",'1'&x"A50F",
+--'1'&x"A510",'1'&x"A511",'1'&x"A512",'1'&x"A513",'1'&x"A514",'1'&x"A515",'1'&x"A516",'1'&x"A517",'1'&x"A518",'1'&x"A519",'1'&x"A51A",'1'&x"A51B",'1'&x"A51C",'1'&x"A51D",'1'&x"A51E",'1'&x"A51F",
+--'1'&x"A520",'1'&x"A521",'1'&x"A522",'1'&x"A523",'1'&x"A524",'1'&x"A525",'1'&x"A526",'1'&x"A527",'1'&x"A528",'1'&x"A529",'1'&x"A52A",'1'&x"A52B",'1'&x"A52C",'1'&x"A52D",'1'&x"A52E",'1'&x"A52F",
+--'1'&x"A530",'1'&x"A531",'1'&x"A532",'1'&x"A533",'1'&x"A534",'1'&x"A535",'1'&x"A536",'1'&x"A537",'1'&x"A538",'1'&x"A539",'1'&x"A53A",'1'&x"A53B",'1'&x"A53C",'1'&x"A53D",'1'&x"A53E",'1'&x"A53F",
+--'1'&x"A540",'1'&x"A541",'1'&x"A542",'1'&x"A543",'1'&x"A544",'1'&x"A545",'1'&x"A546",'1'&x"A547",'1'&x"A548",'1'&x"A549",'1'&x"A54A",'1'&x"A54B",'1'&x"A54C",'1'&x"A54D",'1'&x"A54E",'1'&x"A54F",
+--'1'&x"A550",'1'&x"A551",'1'&x"A552",'1'&x"A553",'1'&x"A554",'1'&x"A555",'1'&x"A556",'1'&x"A557",'1'&x"A558",'1'&x"A559",'1'&x"A55A",'1'&x"A55B",'1'&x"A55C",'1'&x"A55D",'1'&x"A55E",'1'&x"A55F",
+--'1'&x"A560",'1'&x"A561",'1'&x"A562",'1'&x"A563",'1'&x"A564",'1'&x"A565",'1'&x"A566",'1'&x"A567",'1'&x"A568",'1'&x"A569",'1'&x"A56A",'1'&x"A56B",'1'&x"A56C",'1'&x"A56D",'1'&x"A56E",'1'&x"A56F",
+--'1'&x"A570",'1'&x"A571",'1'&x"A572",'1'&x"A573",'1'&x"A574",'1'&x"A575",'1'&x"A576",'1'&x"A577",'1'&x"A578",'1'&x"A579",'1'&x"A57A",'1'&x"A57B",'1'&x"A57C",'1'&x"A57D",'1'&x"A57E",'1'&x"A57F",
+--'1'&x"A580",'1'&x"A581",'1'&x"A582",'1'&x"A583",'1'&x"A584",'1'&x"A585",'1'&x"A586",'1'&x"A587",'1'&x"A588",'1'&x"A589",'1'&x"A58A",'1'&x"A58B",'1'&x"A58C",'1'&x"A58D",'1'&x"A58E",'1'&x"A58F",
+--'1'&x"A590",'1'&x"A591",'1'&x"A592",'1'&x"A593",'1'&x"A594",'1'&x"A595",'1'&x"A596",'1'&x"A597",'1'&x"A598",'1'&x"A599",'1'&x"A59A",'1'&x"A59B",'1'&x"A59C",'1'&x"A59D",'1'&x"A59E",'1'&x"A59F",
+--'1'&x"A5A0",'1'&x"A5A1",'1'&x"A5A2",'1'&x"A5A3",'1'&x"A5A4",'1'&x"A5A5",'1'&x"A5A6",'1'&x"A5A7",'1'&x"A5A8",'1'&x"A5A9",'1'&x"A5AA",'1'&x"A5AB",'1'&x"A5AC",'1'&x"A5AD",'1'&x"A5AE",'1'&x"A5AF",
+--'1'&x"A5B0",'1'&x"A5B1",'1'&x"A5B2",'1'&x"A5B3",'1'&x"A5B4",'1'&x"A5B5",'1'&x"A5B6",'1'&x"A5B7",'1'&x"A5B8",'1'&x"A5B9",'1'&x"A5BA",'1'&x"A5BB",'1'&x"A5BC",'1'&x"A5BD",'1'&x"A5BE",'1'&x"A5BF",
+--'1'&x"A5C0",'1'&x"A5C1",'1'&x"A5C2",'1'&x"A5C3",'1'&x"A5C4",'1'&x"A5C5",'1'&x"A5C6",'1'&x"A5C7",'1'&x"A5C8",'1'&x"A5C9",'1'&x"A5CA",'1'&x"A5CB",'1'&x"A5CC",'1'&x"A5CD",'1'&x"A5CE",'1'&x"A5CF",
+--'1'&x"A5D0",'1'&x"A5D1",'1'&x"A5D2",'1'&x"A5D3",'1'&x"A5D4",'1'&x"A5D5",'1'&x"A5D6",'1'&x"A5D7",'1'&x"A5D8",'1'&x"A5D9",'1'&x"A5DA",'1'&x"A5DB",'1'&x"A5DC",'1'&x"A5DD",'1'&x"A5DE",'1'&x"A5DF",
+--'1'&x"A5E0",'1'&x"A5E1",'1'&x"A5E2",'1'&x"A5E3",'1'&x"A5E4",'1'&x"A5E5",'1'&x"A5E6",'1'&x"A5E7",'1'&x"A5E8",'1'&x"A5E9",'1'&x"A5EA",'1'&x"A5EB",'1'&x"A5EC",'1'&x"A5ED",'1'&x"A5EE",'1'&x"A5EF",
+--'1'&x"A5F0",'1'&x"A5F1",'1'&x"A5F2",'1'&x"A5F3",'1'&x"A5F4",'1'&x"A5F5",'1'&x"A5F6",'1'&x"A5F7",'1'&x"A5F8",'1'&x"A5F9",'1'&x"A5FA",'1'&x"A5FB",'1'&x"A5FC",'1'&x"A5FD",'1'&x"A5FE",'1'&x"A5FF",
+--'1'&x"A600",'1'&x"A601",'1'&x"A602",'1'&x"A603",'1'&x"A604",'1'&x"A605",'1'&x"A606",'1'&x"A607",'1'&x"A608",'1'&x"A609",'1'&x"A60A",'1'&x"A60B",'1'&x"A60C",'1'&x"A60D",'1'&x"A60E",'1'&x"A60F",
+--'1'&x"A610",'1'&x"A611",'1'&x"A612",'1'&x"A613",'1'&x"A614",'1'&x"A615",'1'&x"A616",'1'&x"A617",'1'&x"A618",'1'&x"A619",'1'&x"A61A",'1'&x"A61B",'1'&x"A61C",'1'&x"A61D",'1'&x"A61E",'1'&x"A61F",
+--'1'&x"A620",'1'&x"A621",'1'&x"A622",'1'&x"A623",'1'&x"A624",'1'&x"A625",'1'&x"A626",'1'&x"A627",'1'&x"A628",'1'&x"A629",'1'&x"A62A",'1'&x"A62B",'1'&x"A62C",'1'&x"A62D",'1'&x"A62E",'1'&x"A62F",
+--'1'&x"A630",'1'&x"A631",'1'&x"A632",'1'&x"A633",'1'&x"A634",'1'&x"A635",'1'&x"A636",'1'&x"A637",'1'&x"A638",'1'&x"A639",'1'&x"A63A",'1'&x"A63B",'1'&x"A63C",'1'&x"A63D",'1'&x"A63E",'1'&x"A63F",
+--'1'&x"A640",'1'&x"A641",'1'&x"A642",'1'&x"A643",'1'&x"A644",'1'&x"A645",'1'&x"A646",'1'&x"A647",'1'&x"A648",'1'&x"A649",'1'&x"A64A",'1'&x"A64B",'1'&x"A64C",'1'&x"A64D",'1'&x"A64E",'1'&x"A64F",
+--'1'&x"A650",'1'&x"A651",'1'&x"A652",'1'&x"A653",'1'&x"A654",'1'&x"A655",'1'&x"A656",'1'&x"A657",'1'&x"A658",'1'&x"A659",'1'&x"A65A",'1'&x"A65B",'1'&x"A65C",'1'&x"A65D",'1'&x"A65E",'1'&x"A65F",
+--'1'&x"A660",'1'&x"A661",'1'&x"A662",'1'&x"A663",'1'&x"A664",'1'&x"A665",'1'&x"A666",'1'&x"A667",'1'&x"A668",'1'&x"A669",'1'&x"A66A",'1'&x"A66B",'1'&x"A66C",'1'&x"A66D",'1'&x"A66E",'1'&x"A66F",
+--'1'&x"A670",'1'&x"A671",'1'&x"A672",'1'&x"A673",'1'&x"A674",'1'&x"A675",'1'&x"A676",'1'&x"A677",'1'&x"A678",'1'&x"A679",'1'&x"A67A",'1'&x"A67B",'1'&x"A67C",'1'&x"A67D",'1'&x"A67E",'1'&x"A67F",
+--'1'&x"A680",'1'&x"A681",'1'&x"A682",'1'&x"A683",'1'&x"A684",'1'&x"A685",'1'&x"A686",'1'&x"A687",'1'&x"A688",'1'&x"A689",'1'&x"A68A",'1'&x"A68B",'1'&x"A68C",'1'&x"A68D",'1'&x"A68E",'1'&x"A68F",
+--'1'&x"A690",'1'&x"A691",'1'&x"A692",'1'&x"A693",'1'&x"A694",'1'&x"A695",'1'&x"A696",'1'&x"A697",'1'&x"A698",'1'&x"A699",'1'&x"A69A",'1'&x"A69B",'1'&x"A69C",'1'&x"A69D",'1'&x"A69E",'1'&x"A69F",
+--'1'&x"A6A0",'1'&x"A6A1",'1'&x"A6A2",'1'&x"A6A3",'1'&x"A6A4",'1'&x"A6A5",'1'&x"A6A6",'1'&x"A6A7",'1'&x"A6A8",'1'&x"A6A9",'1'&x"A6AA",'1'&x"A6AB",'1'&x"A6AC",'1'&x"A6AD",'1'&x"A6AE",'1'&x"A6AF",
+--'1'&x"A6B0",'1'&x"A6B1",'1'&x"A6B2",'1'&x"A6B3",'1'&x"A6B4",'1'&x"A6B5",'1'&x"A6B6",'1'&x"A6B7",'1'&x"A6B8",'1'&x"A6B9",'1'&x"A6BA",'1'&x"A6BB",'1'&x"A6BC",'1'&x"A6BD",'1'&x"A6BE",'1'&x"A6BF",
+--'1'&x"A6C0",'1'&x"A6C1",'1'&x"A6C2",'1'&x"A6C3",'1'&x"A6C4",'1'&x"A6C5",'1'&x"A6C6",'1'&x"A6C7",'1'&x"A6C8",'1'&x"A6C9",'1'&x"A6CA",'1'&x"A6CB",'1'&x"A6CC",'1'&x"A6CD",'1'&x"A6CE",'1'&x"A6CF",
+--'1'&x"A6D0",'1'&x"A6D1",'1'&x"A6D2",'1'&x"A6D3",'1'&x"A6D4",'1'&x"A6D5",'1'&x"A6D6",'1'&x"A6D7",'1'&x"A6D8",'1'&x"A6D9",'1'&x"A6DA",'1'&x"A6DB",'1'&x"A6DC",'1'&x"A6DD",'1'&x"A6DE",'1'&x"A6DF",
+--'1'&x"A6E0",'1'&x"A6E1",'1'&x"A6E2",'1'&x"A6E3",'1'&x"A6E4",'1'&x"A6E5",'1'&x"A6E6",'1'&x"A6E7",'1'&x"A6E8",'1'&x"A6E9",'1'&x"A6EA",'1'&x"A6EB",'1'&x"A6EC",'1'&x"A6ED",'1'&x"A6EE",'1'&x"A6EF",
+--'1'&x"A6F0",'1'&x"A6F1",'1'&x"A6F2",'1'&x"A6F3",'1'&x"A6F4",'1'&x"A6F5",'1'&x"A6F6",'1'&x"A6F7",'1'&x"A6F8",'1'&x"A6F9",'1'&x"A6FA",'1'&x"A6FB",'1'&x"A6FC",'1'&x"A6FD",'1'&x"A6FE",'1'&x"A6FF",
+--'1'&x"A700",'1'&x"A701",'1'&x"A702",'1'&x"A703",'1'&x"A704",'1'&x"A705",'1'&x"A706",'1'&x"A707",'1'&x"A708",'1'&x"A709",'1'&x"A70A",'1'&x"A70B",'1'&x"A70C",'1'&x"A70D",'1'&x"A70E",'1'&x"A70F",
+--'1'&x"A710",'1'&x"A711",'1'&x"A712",'1'&x"A713",'1'&x"A714",'1'&x"A715",'1'&x"A716",'1'&x"A717",'1'&x"A718",'1'&x"A719",'1'&x"A71A",'1'&x"A71B",'1'&x"A71C",'1'&x"A71D",'1'&x"A71E",'1'&x"A71F",
+--'1'&x"A720",'1'&x"A721",'1'&x"A722",'1'&x"A723",'1'&x"A724",'1'&x"A725",'1'&x"A726",'1'&x"A727",'1'&x"A728",'1'&x"A729",'1'&x"A72A",'1'&x"A72B",'1'&x"A72C",'1'&x"A72D",'1'&x"A72E",'1'&x"A72F",
+--'1'&x"A730",'1'&x"A731",'1'&x"A732",'1'&x"A733",'1'&x"A734",'1'&x"A735",'1'&x"A736",'1'&x"A737",'1'&x"A738",'1'&x"A739",'1'&x"A73A",'1'&x"A73B",'1'&x"A73C",'1'&x"A73D",'1'&x"A73E",'1'&x"A73F",
+--'1'&x"A740",'1'&x"A741",'1'&x"A742",'1'&x"A743",'1'&x"A744",'1'&x"A745",'1'&x"A746",'1'&x"A747",'1'&x"A748",'1'&x"A749",'1'&x"A74A",'1'&x"A74B",'1'&x"A74C",'1'&x"A74D",'1'&x"A74E",'1'&x"A74F",
+--'1'&x"A750",'1'&x"A751",'1'&x"A752",'1'&x"A753",'1'&x"A754",'1'&x"A755",'1'&x"A756",'1'&x"A757",'1'&x"A758",'1'&x"A759",'1'&x"A75A",'1'&x"A75B",'1'&x"A75C",'1'&x"A75D",'1'&x"A75E",'1'&x"A75F",
+--'1'&x"A760",'1'&x"A761",'1'&x"A762",'1'&x"A763",'1'&x"A764",'1'&x"A765",'1'&x"A766",'1'&x"A767",'1'&x"A768",'1'&x"A769",'1'&x"A76A",'1'&x"A76B",'1'&x"A76C",'1'&x"A76D",'1'&x"A76E",'1'&x"A76F",
+--'1'&x"A770",'1'&x"A771",'1'&x"A772",'1'&x"A773",'1'&x"A774",'1'&x"A775",'1'&x"A776",'1'&x"A777",'1'&x"A778",'1'&x"A779",'1'&x"A77A",'1'&x"A77B",'1'&x"A77C",'1'&x"A77D",'1'&x"A77E",'1'&x"A77F",
+--'1'&x"A780",'1'&x"A781",'1'&x"A782",'1'&x"A783",'1'&x"A784",'1'&x"A785",'1'&x"A786",'1'&x"A787",'1'&x"A788",'1'&x"A789",'1'&x"A78A",'1'&x"A78B",'1'&x"A78C",'1'&x"A78D",'1'&x"A78E",'1'&x"A78F",
+--'1'&x"A790",'1'&x"A791",'1'&x"A792",'1'&x"A793",'1'&x"A794",'1'&x"A795",'1'&x"A796",'1'&x"A797",'1'&x"A798",'1'&x"A799",'1'&x"A79A",'1'&x"A79B",'1'&x"A79C",'1'&x"A79D",'1'&x"A79E",'1'&x"A79F",
+--'1'&x"A7A0",'1'&x"A7A1",'1'&x"A7A2",'1'&x"A7A3",'1'&x"A7A4",'1'&x"A7A5",'1'&x"A7A6",'1'&x"A7A7",'1'&x"A7A8",'1'&x"A7A9",'1'&x"A7AA",'1'&x"A7AB",'1'&x"A7AC",'1'&x"A7AD",'1'&x"A7AE",'1'&x"A7AF",
+--'1'&x"A7B0",'1'&x"A7B1",'1'&x"A7B2",'1'&x"A7B3",'1'&x"A7B4",'1'&x"A7B5",'1'&x"A7B6",'1'&x"A7B7",'1'&x"A7B8",'1'&x"A7B9",'1'&x"A7BA",'1'&x"A7BB",'1'&x"A7BC",'1'&x"A7BD",'1'&x"A7BE",'1'&x"A7BF",
+--'1'&x"A7C0",'1'&x"A7C1",'1'&x"A7C2",'1'&x"A7C3",'1'&x"A7C4",'1'&x"A7C5",'1'&x"A7C6",'1'&x"A7C7",'1'&x"A7C8",'1'&x"A7C9",'1'&x"A7CA",'1'&x"A7CB",'1'&x"A7CC",'1'&x"A7CD",'1'&x"A7CE",'1'&x"A7CF",
+--'1'&x"A7D0",'1'&x"A7D1",'1'&x"A7D2",'1'&x"A7D3",'1'&x"A7D4",'1'&x"A7D5",'1'&x"A7D6",'1'&x"A7D7",'1'&x"A7D8",'1'&x"A7D9",'1'&x"A7DA",'1'&x"A7DB",'1'&x"A7DC",'1'&x"A7DD",'1'&x"A7DE",'1'&x"A7DF",
+--'1'&x"A7E0",'1'&x"A7E1",'1'&x"A7E2",'1'&x"A7E3",'1'&x"A7E4",'1'&x"A7E5",'1'&x"A7E6",'1'&x"A7E7",'1'&x"A7E8",'1'&x"A7E9",'1'&x"A7EA",'1'&x"A7EB",'1'&x"A7EC",'1'&x"A7ED",'1'&x"A7EE",'1'&x"A7EF",
+--'1'&x"A7F0",'1'&x"A7F1",'1'&x"A7F2",'1'&x"A7F3",'1'&x"A7F4",'1'&x"A7F5",'1'&x"A7F6",'1'&x"A7F7",'1'&x"A7F8",'1'&x"A7F9",'1'&x"A7FA",'1'&x"A7FB",'1'&x"A7FC",'1'&x"A7FD",'1'&x"A7FE",'1'&x"A7FF",
+--'1'&x"A800",'1'&x"A801",'1'&x"A802",'1'&x"A803",'1'&x"A804",'1'&x"A805",'1'&x"A806",'1'&x"A807",'1'&x"A808",'1'&x"A809",'1'&x"A80A",'1'&x"A80B",'1'&x"A80C",'1'&x"A80D",'1'&x"A80E",'1'&x"A80F",
+--'1'&x"A810",'1'&x"A811",'1'&x"A812",'1'&x"A813",'1'&x"A814",'1'&x"A815",'1'&x"A816",'1'&x"A817",'1'&x"A818",'1'&x"A819",'1'&x"A81A",'1'&x"A81B",'1'&x"A81C",'1'&x"A81D",'1'&x"A81E",'1'&x"A81F",
+--'1'&x"A820",'1'&x"A821",'1'&x"A822",'1'&x"A823",'1'&x"A824",'1'&x"A825",'1'&x"A826",'1'&x"A827",'1'&x"A828",'1'&x"A829",'1'&x"A82A",'1'&x"A82B",'1'&x"A82C",'1'&x"A82D",'1'&x"A82E",'1'&x"A82F",
+--'1'&x"A830",'1'&x"A831",'1'&x"A832",'1'&x"A833",'1'&x"A834",'1'&x"A835",'1'&x"A836",'1'&x"A837",'1'&x"A838",'1'&x"A839",'1'&x"A83A",'1'&x"A83B",'1'&x"A83C",'1'&x"A83D",'1'&x"A83E",'1'&x"A83F",
+--'1'&x"A840",'1'&x"A841",'1'&x"A842",'1'&x"A843",'1'&x"A844",'1'&x"A845",'1'&x"A846",'1'&x"A847",'1'&x"A848",'1'&x"A849",'1'&x"A84A",'1'&x"A84B",'1'&x"A84C",'1'&x"A84D",'1'&x"A84E",'1'&x"A84F",
+--'1'&x"A850",'1'&x"A851",'1'&x"A852",'1'&x"A853",'1'&x"A854",'1'&x"A855",'1'&x"A856",'1'&x"A857",'1'&x"A858",'1'&x"A859",'1'&x"A85A",'1'&x"A85B",'1'&x"A85C",'1'&x"A85D",'1'&x"A85E",'1'&x"A85F",
+--'1'&x"A860",'1'&x"A861",'1'&x"A862",'1'&x"A863",'1'&x"A864",'1'&x"A865",'1'&x"A866",'1'&x"A867",'1'&x"A868",'1'&x"A869",'1'&x"A86A",'1'&x"A86B",'1'&x"A86C",'1'&x"A86D",'1'&x"A86E",'1'&x"A86F",
+--'1'&x"A870",'1'&x"A871",'1'&x"A872",'1'&x"A873",'1'&x"A874",'1'&x"A875",'1'&x"A876",'1'&x"A877",'1'&x"A878",'1'&x"A879",'1'&x"A87A",'1'&x"A87B",'1'&x"A87C",'1'&x"A87D",'1'&x"A87E",'1'&x"A87F",
+--'1'&x"A880",'1'&x"A881",'1'&x"A882",'1'&x"A883",'1'&x"A884",'1'&x"A885",'1'&x"A886",'1'&x"A887",'1'&x"A888",'1'&x"A889",'1'&x"A88A",'1'&x"A88B",'1'&x"A88C",'1'&x"A88D",'1'&x"A88E",'1'&x"A88F",
+--'1'&x"A890",'1'&x"A891",'1'&x"A892",'1'&x"A893",'1'&x"A894",'1'&x"A895",'1'&x"A896",'1'&x"A897",'1'&x"A898",'1'&x"A899",'1'&x"A89A",'1'&x"A89B",'1'&x"A89C",'1'&x"A89D",'1'&x"A89E",'1'&x"A89F",
+--'1'&x"A8A0",'1'&x"A8A1",'1'&x"A8A2",'1'&x"A8A3",'1'&x"A8A4",'1'&x"A8A5",'1'&x"A8A6",'1'&x"A8A7",'1'&x"A8A8",'1'&x"A8A9",'1'&x"A8AA",'1'&x"A8AB",'1'&x"A8AC",'1'&x"A8AD",'1'&x"A8AE",'1'&x"A8AF",
+--'1'&x"A8B0",'1'&x"A8B1",'1'&x"A8B2",'1'&x"A8B3",'1'&x"A8B4",'1'&x"A8B5",'1'&x"A8B6",'1'&x"A8B7",'1'&x"A8B8",'1'&x"A8B9",'1'&x"A8BA",'1'&x"A8BB",'1'&x"A8BC",'1'&x"A8BD",'1'&x"A8BE",'1'&x"A8BF",
+--'1'&x"A8C0",'1'&x"A8C1",'1'&x"A8C2",'1'&x"A8C3",'1'&x"A8C4",'1'&x"A8C5",'1'&x"A8C6",'1'&x"A8C7",'1'&x"A8C8",'1'&x"A8C9",'1'&x"A8CA",'1'&x"A8CB",'1'&x"A8CC",'1'&x"A8CD",'1'&x"A8CE",'1'&x"A8CF",
+--'1'&x"A8D0",'1'&x"A8D1",'1'&x"A8D2",'1'&x"A8D3",'1'&x"A8D4",'1'&x"A8D5",'1'&x"A8D6",'1'&x"A8D7",'1'&x"A8D8",'1'&x"A8D9",'1'&x"A8DA",'1'&x"A8DB",'1'&x"A8DC",'1'&x"A8DD",'1'&x"A8DE",'1'&x"A8DF",
+--'1'&x"A8E0",'1'&x"A8E1",'1'&x"A8E2",'1'&x"A8E3",'1'&x"A8E4",'1'&x"A8E5",'1'&x"A8E6",'1'&x"A8E7",'1'&x"A8E8",'1'&x"A8E9",'1'&x"A8EA",'1'&x"A8EB",'1'&x"A8EC",'1'&x"A8ED",'1'&x"A8EE",'1'&x"A8EF",
+--'1'&x"A8F0",'1'&x"A8F1",'1'&x"A8F2",'1'&x"A8F3",'1'&x"A8F4",'1'&x"A8F5",'1'&x"A8F6",'1'&x"A8F7",'1'&x"A8F8",'1'&x"A8F9",'1'&x"A8FA",'1'&x"A8FB",'1'&x"A8FC",'1'&x"A8FD",'1'&x"A8FE",'1'&x"A8FF",
+--'1'&x"A900",'1'&x"A901",'1'&x"A902",'1'&x"A903",'1'&x"A904",'1'&x"A905",'1'&x"A906",'1'&x"A907",'1'&x"A908",'1'&x"A909",'1'&x"A90A",'1'&x"A90B",'1'&x"A90C",'1'&x"A90D",'1'&x"A90E",'1'&x"A90F",
+--'1'&x"A910",'1'&x"A911",'1'&x"A912",'1'&x"A913",'1'&x"A914",'1'&x"A915",'1'&x"A916",'1'&x"A917",'1'&x"A918",'1'&x"A919",'1'&x"A91A",'1'&x"A91B",'1'&x"A91C",'1'&x"A91D",'1'&x"A91E",'1'&x"A91F",
+--'1'&x"A920",'1'&x"A921",'1'&x"A922",'1'&x"A923",'1'&x"A924",'1'&x"A925",'1'&x"A926",'1'&x"A927",'1'&x"A928",'1'&x"A929",'1'&x"A92A",'1'&x"A92B",'1'&x"A92C",'1'&x"A92D",'1'&x"A92E",'1'&x"A92F",
+--'1'&x"A930",'1'&x"A931",'1'&x"A932",'1'&x"A933",'1'&x"A934",'1'&x"A935",'1'&x"A936",'1'&x"A937",'1'&x"A938",'1'&x"A939",'1'&x"A93A",'1'&x"A93B",'1'&x"A93C",'1'&x"A93D",'1'&x"A93E",'1'&x"A93F",
+--'1'&x"A940",'1'&x"A941",'1'&x"A942",'1'&x"A943",'1'&x"A944",'1'&x"A945",'1'&x"A946",'1'&x"A947",'1'&x"A948",'1'&x"A949",'1'&x"A94A",'1'&x"A94B",'1'&x"A94C",'1'&x"A94D",'1'&x"A94E",'1'&x"A94F",
+--'1'&x"A950",'1'&x"A951",'1'&x"A952",'1'&x"A953",'1'&x"A954",'1'&x"A955",'1'&x"A956",'1'&x"A957",'1'&x"A958",'1'&x"A959",'1'&x"A95A",'1'&x"A95B",'1'&x"A95C",'1'&x"A95D",'1'&x"A95E",'1'&x"A95F",
+--'1'&x"A960",'1'&x"A961",'1'&x"A962",'1'&x"A963",'1'&x"A964",'1'&x"A965",'1'&x"A966",'1'&x"A967",'1'&x"A968",'1'&x"A969",'1'&x"A96A",'1'&x"A96B",'1'&x"A96C",'1'&x"A96D",'1'&x"A96E",'1'&x"A96F",
+--'1'&x"A970",'1'&x"A971",'1'&x"A972",'1'&x"A973",'1'&x"A974",'1'&x"A975",'1'&x"A976",'1'&x"A977",'1'&x"A978",'1'&x"A979",'1'&x"A97A",'1'&x"A97B",'1'&x"A97C",'1'&x"A97D",'1'&x"A97E",'1'&x"A97F",
+--'1'&x"A980",'1'&x"A981",'1'&x"A982",'1'&x"A983",'1'&x"A984",'1'&x"A985",'1'&x"A986",'1'&x"A987",'1'&x"A988",'1'&x"A989",'1'&x"A98A",'1'&x"A98B",'1'&x"A98C",'1'&x"A98D",'1'&x"A98E",'1'&x"A98F",
+--'1'&x"A990",'1'&x"A991",'1'&x"A992",'1'&x"A993",'1'&x"A994",'1'&x"A995",'1'&x"A996",'1'&x"A997",'1'&x"A998",'1'&x"A999",'1'&x"A99A",'1'&x"A99B",'1'&x"A99C",'1'&x"A99D",'1'&x"A99E",'1'&x"A99F",
+--'1'&x"A9A0",'1'&x"A9A1",'1'&x"A9A2",'1'&x"A9A3",'1'&x"A9A4",'1'&x"A9A5",'1'&x"A9A6",'1'&x"A9A7",'1'&x"A9A8",'1'&x"A9A9",'1'&x"A9AA",'1'&x"A9AB",'1'&x"A9AC",'1'&x"A9AD",'1'&x"A9AE",'1'&x"A9AF",
+--'1'&x"A9B0",'1'&x"A9B1",'1'&x"A9B2",'1'&x"A9B3",'1'&x"A9B4",'1'&x"A9B5",'1'&x"A9B6",'1'&x"A9B7",'1'&x"A9B8",'1'&x"A9B9",'1'&x"A9BA",'1'&x"A9BB",'1'&x"A9BC",'1'&x"A9BD",'1'&x"A9BE",'1'&x"A9BF",
+--'1'&x"A9C0",'1'&x"A9C1",'1'&x"A9C2",'1'&x"A9C3",'1'&x"A9C4",'1'&x"A9C5",'1'&x"A9C6",'1'&x"A9C7",'1'&x"A9C8",'1'&x"A9C9",'1'&x"A9CA",'1'&x"A9CB",'1'&x"A9CC",'1'&x"A9CD",'1'&x"A9CE",'1'&x"A9CF",
+--'1'&x"A9D0",'1'&x"A9D1",'1'&x"A9D2",'1'&x"A9D3",'1'&x"A9D4",'1'&x"A9D5",'1'&x"A9D6",'1'&x"A9D7",'1'&x"A9D8",'1'&x"A9D9",'1'&x"A9DA",'1'&x"A9DB",'1'&x"A9DC",'1'&x"A9DD",'1'&x"A9DE",'1'&x"A9DF",
+--'1'&x"A9E0",'1'&x"A9E1",'1'&x"A9E2",'1'&x"A9E3",'1'&x"A9E4",'1'&x"A9E5",'1'&x"A9E6",'1'&x"A9E7",'1'&x"A9E8",'1'&x"A9E9",'1'&x"A9EA",'1'&x"A9EB",'1'&x"A9EC",'1'&x"A9ED",'1'&x"A9EE",'1'&x"A9EF",
+--'1'&x"A9F0",'1'&x"A9F1",'1'&x"A9F2",'1'&x"A9F3",'1'&x"A9F4",'1'&x"A9F5",'1'&x"A9F6",'1'&x"A9F7",'1'&x"A9F8",'1'&x"A9F9",'1'&x"A9FA",'1'&x"A9FB",'1'&x"A9FC",'1'&x"A9FD",'1'&x"A9FE",'1'&x"A9FF",
+--'1'&x"AA00",'1'&x"AA01",'1'&x"AA02",'1'&x"AA03",'1'&x"AA04",'1'&x"AA05",'1'&x"AA06",'1'&x"AA07",'1'&x"AA08",'1'&x"AA09",'1'&x"AA0A",'1'&x"AA0B",'1'&x"AA0C",'1'&x"AA0D",'1'&x"AA0E",'1'&x"AA0F",
+--'1'&x"AA10",'1'&x"AA11",'1'&x"AA12",'1'&x"AA13",'1'&x"AA14",'1'&x"AA15",'1'&x"AA16",'1'&x"AA17",'1'&x"AA18",'1'&x"AA19",'1'&x"AA1A",'1'&x"AA1B",'1'&x"AA1C",'1'&x"AA1D",'1'&x"AA1E",'1'&x"AA1F",
+--'1'&x"AA20",'1'&x"AA21",'1'&x"AA22",'1'&x"AA23",'1'&x"AA24",'1'&x"AA25",'1'&x"AA26",'1'&x"AA27",'1'&x"AA28",'1'&x"AA29",'1'&x"AA2A",'1'&x"AA2B",'1'&x"AA2C",'1'&x"AA2D",'1'&x"AA2E",'1'&x"AA2F",
+--'1'&x"AA30",'1'&x"AA31",'1'&x"AA32",'1'&x"AA33",'1'&x"AA34",'1'&x"AA35",'1'&x"AA36",'1'&x"AA37",'1'&x"AA38",'1'&x"AA39",'1'&x"AA3A",'1'&x"AA3B",'1'&x"AA3C",'1'&x"AA3D",'1'&x"AA3E",'1'&x"AA3F",
+--'1'&x"AA40",'1'&x"AA41",'1'&x"AA42",'1'&x"AA43",'1'&x"AA44",'1'&x"AA45",'1'&x"AA46",'1'&x"AA47",'1'&x"AA48",'1'&x"AA49",'1'&x"AA4A",'1'&x"AA4B",'1'&x"AA4C",'1'&x"AA4D",'1'&x"AA4E",'1'&x"AA4F",
+--'1'&x"AA50",'1'&x"AA51",'1'&x"AA52",'1'&x"AA53",'1'&x"AA54",'1'&x"AA55",'1'&x"AA56",'1'&x"AA57",'1'&x"AA58",'1'&x"AA59",'1'&x"AA5A",'1'&x"AA5B",'1'&x"AA5C",'1'&x"AA5D",'1'&x"AA5E",'1'&x"AA5F",
+--'1'&x"AA60",'1'&x"AA61",'1'&x"AA62",'1'&x"AA63",'1'&x"AA64",'1'&x"AA65",'1'&x"AA66",'1'&x"AA67",'1'&x"AA68",'1'&x"AA69",'1'&x"AA6A",'1'&x"AA6B",'1'&x"AA6C",'1'&x"AA6D",'1'&x"AA6E",'1'&x"AA6F",
+--'1'&x"AA70",'1'&x"AA71",'1'&x"AA72",'1'&x"AA73",'1'&x"AA74",'1'&x"AA75",'1'&x"AA76",'1'&x"AA77",'1'&x"AA78",'1'&x"AA79",'1'&x"AA7A",'1'&x"AA7B",'1'&x"AA7C",'1'&x"AA7D",'1'&x"AA7E",'1'&x"AA7F",
+--'1'&x"AA80",'1'&x"AA81",'1'&x"AA82",'1'&x"AA83",'1'&x"AA84",'1'&x"AA85",'1'&x"AA86",'1'&x"AA87",'1'&x"AA88",'1'&x"AA89",'1'&x"AA8A",'1'&x"AA8B",'1'&x"AA8C",'1'&x"AA8D",'1'&x"AA8E",'1'&x"AA8F",
+--'1'&x"AA90",'1'&x"AA91",'1'&x"AA92",'1'&x"AA93",'1'&x"AA94",'1'&x"AA95",'1'&x"AA96",'1'&x"AA97",'1'&x"AA98",'1'&x"AA99",'1'&x"AA9A",'1'&x"AA9B",'1'&x"AA9C",'1'&x"AA9D",'1'&x"AA9E",'1'&x"AA9F",
+--'1'&x"AAA0",'1'&x"AAA1",'1'&x"AAA2",'1'&x"AAA3",'1'&x"AAA4",'1'&x"AAA5",'1'&x"AAA6",'1'&x"AAA7",'1'&x"AAA8",'1'&x"AAA9",'1'&x"AAAA",'1'&x"AAAB",'1'&x"AAAC",'1'&x"AAAD",'1'&x"AAAE",'1'&x"AAAF",
+--'1'&x"AAB0",'1'&x"AAB1",'1'&x"AAB2",'1'&x"AAB3",'1'&x"AAB4",'1'&x"AAB5",'1'&x"AAB6",'1'&x"AAB7",'1'&x"AAB8",'1'&x"AAB9",'1'&x"AABA",'1'&x"AABB",'1'&x"AABC",'1'&x"AABD",'1'&x"AABE",'1'&x"AABF",
+--'1'&x"AAC0",'1'&x"AAC1",'1'&x"AAC2",'1'&x"AAC3",'1'&x"AAC4",'1'&x"AAC5",'1'&x"AAC6",'1'&x"AAC7",'1'&x"AAC8",'1'&x"AAC9",'1'&x"AACA",'1'&x"AACB",'1'&x"AACC",'1'&x"AACD",'1'&x"AACE",'1'&x"AACF",
+--'1'&x"AAD0",'1'&x"AAD1",'1'&x"AAD2",'1'&x"AAD3",'1'&x"AAD4",'1'&x"AAD5",'1'&x"AAD6",'1'&x"AAD7",'1'&x"AAD8",'1'&x"AAD9",'1'&x"AADA",'1'&x"AADB",'1'&x"AADC",'1'&x"AADD",'1'&x"AADE",'1'&x"AADF",
+--'1'&x"AAE0",'1'&x"AAE1",'1'&x"AAE2",'1'&x"AAE3",'1'&x"AAE4",'1'&x"AAE5",'1'&x"AAE6",'1'&x"AAE7",'1'&x"AAE8",'1'&x"AAE9",'1'&x"AAEA",'1'&x"AAEB",'1'&x"AAEC",'1'&x"AAED",'1'&x"AAEE",'1'&x"AAEF",
+--'1'&x"AAF0",'1'&x"AAF1",'1'&x"AAF2",'1'&x"AAF3",'1'&x"AAF4",'1'&x"AAF5",'1'&x"AAF6",'1'&x"AAF7",'1'&x"AAF8",'1'&x"AAF9",'1'&x"AAFA",'1'&x"AAFB",'1'&x"AAFC",'1'&x"AAFD",'1'&x"AAFE",'1'&x"AAFF",
+--'1'&x"AB00",'1'&x"AB01",'1'&x"AB02",'1'&x"AB03",'1'&x"AB04",'1'&x"AB05",'1'&x"AB06",'1'&x"AB07",'1'&x"AB08",'1'&x"AB09",'1'&x"AB0A",'1'&x"AB0B",'1'&x"AB0C",'1'&x"AB0D",'1'&x"AB0E",'1'&x"AB0F",
+--'1'&x"AB10",'1'&x"AB11",'1'&x"AB12",'1'&x"AB13",'1'&x"AB14",'1'&x"AB15",'1'&x"AB16",'1'&x"AB17",'1'&x"AB18",'1'&x"AB19",'1'&x"AB1A",'1'&x"AB1B",'1'&x"AB1C",'1'&x"AB1D",'1'&x"AB1E",'1'&x"AB1F",
+--'1'&x"AB20",'1'&x"AB21",'1'&x"AB22",'1'&x"AB23",'1'&x"AB24",'1'&x"AB25",'1'&x"AB26",'1'&x"AB27",'1'&x"AB28",'1'&x"AB29",'1'&x"AB2A",'1'&x"AB2B",'1'&x"AB2C",'1'&x"AB2D",'1'&x"AB2E",'1'&x"AB2F",
+--'1'&x"AB30",'1'&x"AB31",'1'&x"AB32",'1'&x"AB33",'1'&x"AB34",'1'&x"AB35",'1'&x"AB36",'1'&x"AB37",'1'&x"AB38",'1'&x"AB39",'1'&x"AB3A",'1'&x"AB3B",'1'&x"AB3C",'1'&x"AB3D",'1'&x"AB3E",'1'&x"AB3F",
+--'1'&x"AB40",'1'&x"AB41",'1'&x"AB42",'1'&x"AB43",'1'&x"AB44",'1'&x"AB45",'1'&x"AB46",'1'&x"AB47",'1'&x"AB48",'1'&x"AB49",'1'&x"AB4A",'1'&x"AB4B",'1'&x"AB4C",'1'&x"AB4D",'1'&x"AB4E",'1'&x"AB4F",
+--'1'&x"AB50",'1'&x"AB51",'1'&x"AB52",'1'&x"AB53",'1'&x"AB54",'1'&x"AB55",'1'&x"AB56",'1'&x"AB57",'1'&x"AB58",'1'&x"AB59",'1'&x"AB5A",'1'&x"AB5B",'1'&x"AB5C",'1'&x"AB5D",'1'&x"AB5E",'1'&x"AB5F",
+--'1'&x"AB60",'1'&x"AB61",'1'&x"AB62",'1'&x"AB63",'1'&x"AB64",'1'&x"AB65",'1'&x"AB66",'1'&x"AB67",'1'&x"AB68",'1'&x"AB69",'1'&x"AB6A",'1'&x"AB6B",'1'&x"AB6C",'1'&x"AB6D",'1'&x"AB6E",'1'&x"AB6F",
+--'1'&x"AB70",'1'&x"AB71",'1'&x"AB72",'1'&x"AB73",'1'&x"AB74",'1'&x"AB75",'1'&x"AB76",'1'&x"AB77",'1'&x"AB78",'1'&x"AB79",'1'&x"AB7A",'1'&x"AB7B",'1'&x"AB7C",'1'&x"AB7D",'1'&x"AB7E",'1'&x"AB7F",
+--'1'&x"AB80",'1'&x"AB81",'1'&x"AB82",'1'&x"AB83",'1'&x"AB84",'1'&x"AB85",'1'&x"AB86",'1'&x"AB87",'1'&x"AB88",'1'&x"AB89",'1'&x"AB8A",'1'&x"AB8B",'1'&x"AB8C",'1'&x"AB8D",'1'&x"AB8E",'1'&x"AB8F",
+--'1'&x"AB90",'1'&x"AB91",'1'&x"AB92",'1'&x"AB93",'1'&x"AB94",'1'&x"AB95",'1'&x"AB96",'1'&x"AB97",'1'&x"AB98",'1'&x"AB99",'1'&x"AB9A",'1'&x"AB9B",'1'&x"AB9C",'1'&x"AB9D",'1'&x"AB9E",'1'&x"AB9F",
+--'1'&x"ABA0",'1'&x"ABA1",'1'&x"ABA2",'1'&x"ABA3",'1'&x"ABA4",'1'&x"ABA5",'1'&x"ABA6",'1'&x"ABA7",'1'&x"ABA8",'1'&x"ABA9",'1'&x"ABAA",'1'&x"ABAB",'1'&x"ABAC",'1'&x"ABAD",'1'&x"ABAE",'1'&x"ABAF",
+--'1'&x"ABB0",'1'&x"ABB1",'1'&x"ABB2",'1'&x"ABB3",'1'&x"ABB4",'1'&x"ABB5",'1'&x"ABB6",'1'&x"ABB7",'1'&x"ABB8",'1'&x"ABB9",'1'&x"ABBA",'1'&x"ABBB",'1'&x"ABBC",'1'&x"ABBD",'1'&x"ABBE",'1'&x"ABBF",
+--'1'&x"ABC0",'1'&x"ABC1",'1'&x"ABC2",'1'&x"ABC3",'1'&x"ABC4",'1'&x"ABC5",'1'&x"ABC6",'1'&x"ABC7",'1'&x"ABC8",'1'&x"ABC9",'1'&x"ABCA",'1'&x"ABCB",'1'&x"ABCC",'1'&x"ABCD",'1'&x"ABCE",'1'&x"ABCF",
+--'1'&x"ABD0",'1'&x"ABD1",'1'&x"ABD2",'1'&x"ABD3",'1'&x"ABD4",'1'&x"ABD5",'1'&x"ABD6",'1'&x"ABD7",'1'&x"ABD8",'1'&x"ABD9",'1'&x"ABDA",'1'&x"ABDB",'1'&x"ABDC",'1'&x"ABDD",'1'&x"ABDE",'1'&x"ABDF",
+--'1'&x"ABE0",'1'&x"ABE1",'1'&x"ABE2",'1'&x"ABE3",'1'&x"ABE4",'1'&x"ABE5",'1'&x"ABE6",'1'&x"ABE7",'1'&x"ABE8",'1'&x"ABE9",'1'&x"ABEA",'1'&x"ABEB",'1'&x"ABEC",'1'&x"ABED",'1'&x"ABEE",'1'&x"ABEF",
+--'1'&x"ABF0",'1'&x"ABF1",'1'&x"ABF2",'1'&x"ABF3",'1'&x"ABF4",'1'&x"ABF5",'1'&x"ABF6",'1'&x"ABF7",'1'&x"ABF8",'1'&x"ABF9",'1'&x"ABFA",'1'&x"ABFB",'1'&x"ABFC",'1'&x"ABFD",'1'&x"ABFE",'1'&x"ABFF",
+--'1'&x"AC00",'1'&x"AC01",'1'&x"AC02",'1'&x"AC03",'1'&x"AC04",'1'&x"AC05",'1'&x"AC06",'1'&x"AC07",'1'&x"AC08",'1'&x"AC09",'1'&x"AC0A",'1'&x"AC0B",'1'&x"AC0C",'1'&x"AC0D",'1'&x"AC0E",'1'&x"AC0F",
+--'1'&x"AC10",'1'&x"AC11",'1'&x"AC12",'1'&x"AC13",'1'&x"AC14",'1'&x"AC15",'1'&x"AC16",'1'&x"AC17",'1'&x"AC18",'1'&x"AC19",'1'&x"AC1A",'1'&x"AC1B",'1'&x"AC1C",'1'&x"AC1D",'1'&x"AC1E",'1'&x"AC1F",
+--'1'&x"AC20",'1'&x"AC21",'1'&x"AC22",'1'&x"AC23",'1'&x"AC24",'1'&x"AC25",'1'&x"AC26",'1'&x"AC27",'1'&x"AC28",'1'&x"AC29",'1'&x"AC2A",'1'&x"AC2B",'1'&x"AC2C",'1'&x"AC2D",'1'&x"AC2E",'1'&x"AC2F",
+--'1'&x"AC30",'1'&x"AC31",'1'&x"AC32",'1'&x"AC33",'1'&x"AC34",'1'&x"AC35",'1'&x"AC36",'1'&x"AC37",'1'&x"AC38",'1'&x"AC39",'1'&x"AC3A",'1'&x"AC3B",'1'&x"AC3C",'1'&x"AC3D",'1'&x"AC3E",'1'&x"AC3F",
+--'1'&x"AC40",'1'&x"AC41",'1'&x"AC42",'1'&x"AC43",'1'&x"AC44",'1'&x"AC45",'1'&x"AC46",'1'&x"AC47",'1'&x"AC48",'1'&x"AC49",'1'&x"AC4A",'1'&x"AC4B",'1'&x"AC4C",'1'&x"AC4D",'1'&x"AC4E",'1'&x"AC4F",
+--'1'&x"AC50",'1'&x"AC51",'1'&x"AC52",'1'&x"AC53",'1'&x"AC54",'1'&x"AC55",'1'&x"AC56",'1'&x"AC57",'1'&x"AC58",'1'&x"AC59",'1'&x"AC5A",'1'&x"AC5B",'1'&x"AC5C",'1'&x"AC5D",'1'&x"AC5E",'1'&x"AC5F",
+--'1'&x"AC60",'1'&x"AC61",'1'&x"AC62",'1'&x"AC63",'1'&x"AC64",'1'&x"AC65",'1'&x"AC66",'1'&x"AC67",'1'&x"AC68",'1'&x"AC69",'1'&x"AC6A",'1'&x"AC6B",'1'&x"AC6C",'1'&x"AC6D",'1'&x"AC6E",'1'&x"AC6F",
+--'1'&x"AC70",'1'&x"AC71",'1'&x"AC72",'1'&x"AC73",'1'&x"AC74",'1'&x"AC75",'1'&x"AC76",'1'&x"AC77",'1'&x"AC78",'1'&x"AC79",'1'&x"AC7A",'1'&x"AC7B",'1'&x"AC7C",'1'&x"AC7D",'1'&x"AC7E",'1'&x"AC7F",
+--'1'&x"AC80",'1'&x"AC81",'1'&x"AC82",'1'&x"AC83",'1'&x"AC84",'1'&x"AC85",'1'&x"AC86",'1'&x"AC87",'1'&x"AC88",'1'&x"AC89",'1'&x"AC8A",'1'&x"AC8B",'1'&x"AC8C",'1'&x"AC8D",'1'&x"AC8E",'1'&x"AC8F",
+--'1'&x"AC90",'1'&x"AC91",'1'&x"AC92",'1'&x"AC93",'1'&x"AC94",'1'&x"AC95",'1'&x"AC96",'1'&x"AC97",'1'&x"AC98",'1'&x"AC99",'1'&x"AC9A",'1'&x"AC9B",'1'&x"AC9C",'1'&x"AC9D",'1'&x"AC9E",'1'&x"AC9F",
+--'1'&x"ACA0",'1'&x"ACA1",'1'&x"ACA2",'1'&x"ACA3",'1'&x"ACA4",'1'&x"ACA5",'1'&x"ACA6",'1'&x"ACA7",'1'&x"ACA8",'1'&x"ACA9",'1'&x"ACAA",'1'&x"ACAB",'1'&x"ACAC",'1'&x"ACAD",'1'&x"ACAE",'1'&x"ACAF",
+--'1'&x"ACB0",'1'&x"ACB1",'1'&x"ACB2",'1'&x"ACB3",'1'&x"ACB4",'1'&x"ACB5",'1'&x"ACB6",'1'&x"ACB7",'1'&x"ACB8",'1'&x"ACB9",'1'&x"ACBA",'1'&x"ACBB",'1'&x"ACBC",'1'&x"ACBD",'1'&x"ACBE",'1'&x"ACBF",
+--'1'&x"ACC0",'1'&x"ACC1",'1'&x"ACC2",'1'&x"ACC3",'1'&x"ACC4",'1'&x"ACC5",'1'&x"ACC6",'1'&x"ACC7",'1'&x"ACC8",'1'&x"ACC9",'1'&x"ACCA",'1'&x"ACCB",'1'&x"ACCC",'1'&x"ACCD",'1'&x"ACCE",'1'&x"ACCF",
+--'1'&x"ACD0",'1'&x"ACD1",'1'&x"ACD2",'1'&x"ACD3",'1'&x"ACD4",'1'&x"ACD5",'1'&x"ACD6",'1'&x"ACD7",'1'&x"ACD8",'1'&x"ACD9",'1'&x"ACDA",'1'&x"ACDB",'1'&x"ACDC",'1'&x"ACDD",'1'&x"ACDE",'1'&x"ACDF",
+--'1'&x"ACE0",'1'&x"ACE1",'1'&x"ACE2",'1'&x"ACE3",'1'&x"ACE4",'1'&x"ACE5",'1'&x"ACE6",'1'&x"ACE7",'1'&x"ACE8",'1'&x"ACE9",'1'&x"ACEA",'1'&x"ACEB",'1'&x"ACEC",'1'&x"ACED",'1'&x"ACEE",'1'&x"ACEF",
+--'1'&x"ACF0",'1'&x"ACF1",'1'&x"ACF2",'1'&x"ACF3",'1'&x"ACF4",'1'&x"ACF5",'1'&x"ACF6",'1'&x"ACF7",'1'&x"ACF8",'1'&x"ACF9",'1'&x"ACFA",'1'&x"ACFB",'1'&x"ACFC",'1'&x"ACFD",'1'&x"ACFE",'1'&x"ACFF",
+--'1'&x"AD00",'1'&x"AD01",'1'&x"AD02",'1'&x"AD03",'1'&x"AD04",'1'&x"AD05",'1'&x"AD06",'1'&x"AD07",'1'&x"AD08",'1'&x"AD09",'1'&x"AD0A",'1'&x"AD0B",'1'&x"AD0C",'1'&x"AD0D",'1'&x"AD0E",'1'&x"AD0F",
+--'1'&x"AD10",'1'&x"AD11",'1'&x"AD12",'1'&x"AD13",'1'&x"AD14",'1'&x"AD15",'1'&x"AD16",'1'&x"AD17",'1'&x"AD18",'1'&x"AD19",'1'&x"AD1A",'1'&x"AD1B",'1'&x"AD1C",'1'&x"AD1D",'1'&x"AD1E",'1'&x"AD1F",
+--'1'&x"AD20",'1'&x"AD21",'1'&x"AD22",'1'&x"AD23",'1'&x"AD24",'1'&x"AD25",'1'&x"AD26",'1'&x"AD27",'1'&x"AD28",'1'&x"AD29",'1'&x"AD2A",'1'&x"AD2B",'1'&x"AD2C",'1'&x"AD2D",'1'&x"AD2E",'1'&x"AD2F",
+--'1'&x"AD30",'1'&x"AD31",'1'&x"AD32",'1'&x"AD33",'1'&x"AD34",'1'&x"AD35",'1'&x"AD36",'1'&x"AD37",'1'&x"AD38",'1'&x"AD39",'1'&x"AD3A",'1'&x"AD3B",'1'&x"AD3C",'1'&x"AD3D",'1'&x"AD3E",'1'&x"AD3F",
+--'1'&x"AD40",'1'&x"AD41",'1'&x"AD42",'1'&x"AD43",'1'&x"AD44",'1'&x"AD45",'1'&x"AD46",'1'&x"AD47",'1'&x"AD48",'1'&x"AD49",'1'&x"AD4A",'1'&x"AD4B",'1'&x"AD4C",'1'&x"AD4D",'1'&x"AD4E",'1'&x"AD4F",
+--'1'&x"AD50",'1'&x"AD51",'1'&x"AD52",'1'&x"AD53",'1'&x"AD54",'1'&x"AD55",'1'&x"AD56",'1'&x"AD57",'1'&x"AD58",'1'&x"AD59",'1'&x"AD5A",'1'&x"AD5B",'1'&x"AD5C",'1'&x"AD5D",'1'&x"AD5E",'1'&x"AD5F",
+--'1'&x"AD60",'1'&x"AD61",'1'&x"AD62",'1'&x"AD63",'1'&x"AD64",'1'&x"AD65",'1'&x"AD66",'1'&x"AD67",'1'&x"AD68",'1'&x"AD69",'1'&x"AD6A",'1'&x"AD6B",'1'&x"AD6C",'1'&x"AD6D",'1'&x"AD6E",'1'&x"AD6F",
+--'1'&x"AD70",'1'&x"AD71",'1'&x"AD72",'1'&x"AD73",'1'&x"AD74",'1'&x"AD75",'1'&x"AD76",'1'&x"AD77",'1'&x"AD78",'1'&x"AD79",'1'&x"AD7A",'1'&x"AD7B",'1'&x"AD7C",'1'&x"AD7D",'1'&x"AD7E",'1'&x"AD7F",
+--'1'&x"AD80",'1'&x"AD81",'1'&x"AD82",'1'&x"AD83",'1'&x"AD84",'1'&x"AD85",'1'&x"AD86",'1'&x"AD87",'1'&x"AD88",'1'&x"AD89",'1'&x"AD8A",'1'&x"AD8B",'1'&x"AD8C",'1'&x"AD8D",'1'&x"AD8E",'1'&x"AD8F",
+--'1'&x"AD90",'1'&x"AD91",'1'&x"AD92",'1'&x"AD93",'1'&x"AD94",'1'&x"AD95",'1'&x"AD96",'1'&x"AD97",'1'&x"AD98",'1'&x"AD99",'1'&x"AD9A",'1'&x"AD9B",'1'&x"AD9C",'1'&x"AD9D",'1'&x"AD9E",'1'&x"AD9F",
+--'1'&x"ADA0",'1'&x"ADA1",'1'&x"ADA2",'1'&x"ADA3",'1'&x"ADA4",'1'&x"ADA5",'1'&x"ADA6",'1'&x"ADA7",'1'&x"ADA8",'1'&x"ADA9",'1'&x"ADAA",'1'&x"ADAB",'1'&x"ADAC",'1'&x"ADAD",'1'&x"ADAE",'1'&x"ADAF",
+--'1'&x"ADB0",'1'&x"ADB1",'1'&x"ADB2",'1'&x"ADB3",'1'&x"ADB4",'1'&x"ADB5",'1'&x"ADB6",'1'&x"ADB7",'1'&x"ADB8",'1'&x"ADB9",'1'&x"ADBA",'1'&x"ADBB",'1'&x"ADBC",'1'&x"ADBD",'1'&x"ADBE",'1'&x"ADBF",
+--'1'&x"ADC0",'1'&x"ADC1",'1'&x"ADC2",'1'&x"ADC3",'1'&x"ADC4",'1'&x"ADC5",'1'&x"ADC6",'1'&x"ADC7",'1'&x"ADC8",'1'&x"ADC9",'1'&x"ADCA",'1'&x"ADCB",'1'&x"ADCC",'1'&x"ADCD",'1'&x"ADCE",'1'&x"ADCF",
+--'1'&x"ADD0",'1'&x"ADD1",'1'&x"ADD2",'1'&x"ADD3",'1'&x"ADD4",'1'&x"ADD5",'1'&x"ADD6",'1'&x"ADD7",'1'&x"ADD8",'1'&x"ADD9",'1'&x"ADDA",'1'&x"ADDB",'1'&x"ADDC",'1'&x"ADDD",'1'&x"ADDE",'1'&x"ADDF",
+--'1'&x"ADE0",'1'&x"ADE1",'1'&x"ADE2",'1'&x"ADE3",'1'&x"ADE4",'1'&x"ADE5",'1'&x"ADE6",'1'&x"ADE7",'1'&x"ADE8",'1'&x"ADE9",'1'&x"ADEA",'1'&x"ADEB",'1'&x"ADEC",'1'&x"ADED",'1'&x"ADEE",'1'&x"ADEF",
+--'1'&x"ADF0",'1'&x"ADF1",'1'&x"ADF2",'1'&x"ADF3",'1'&x"ADF4",'1'&x"ADF5",'1'&x"ADF6",'1'&x"ADF7",'1'&x"ADF8",'1'&x"ADF9",'1'&x"ADFA",'1'&x"ADFB",'1'&x"ADFC",'1'&x"ADFD",'1'&x"ADFE",'1'&x"ADFF",
+--'1'&x"AE00",'1'&x"AE01",'1'&x"AE02",'1'&x"AE03",'1'&x"AE04",'1'&x"AE05",'1'&x"AE06",'1'&x"AE07",'1'&x"AE08",'1'&x"AE09",'1'&x"AE0A",'1'&x"AE0B",'1'&x"AE0C",'1'&x"AE0D",'1'&x"AE0E",'1'&x"AE0F",
+--'1'&x"AE10",'1'&x"AE11",'1'&x"AE12",'1'&x"AE13",'1'&x"AE14",'1'&x"AE15",'1'&x"AE16",'1'&x"AE17",'1'&x"AE18",'1'&x"AE19",'1'&x"AE1A",'1'&x"AE1B",'1'&x"AE1C",'1'&x"AE1D",'1'&x"AE1E",'1'&x"AE1F",
+--'1'&x"AE20",'1'&x"AE21",'1'&x"AE22",'1'&x"AE23",'1'&x"AE24",'1'&x"AE25",'1'&x"AE26",'1'&x"AE27",'1'&x"AE28",'1'&x"AE29",'1'&x"AE2A",'1'&x"AE2B",'1'&x"AE2C",'1'&x"AE2D",'1'&x"AE2E",'1'&x"AE2F",
+--'1'&x"AE30",'1'&x"AE31",'1'&x"AE32",'1'&x"AE33",'1'&x"AE34",'1'&x"AE35",'1'&x"AE36",'1'&x"AE37",'1'&x"AE38",'1'&x"AE39",'1'&x"AE3A",'1'&x"AE3B",'1'&x"AE3C",'1'&x"AE3D",'1'&x"AE3E",'1'&x"AE3F",
+--'1'&x"AE40",'1'&x"AE41",'1'&x"AE42",'1'&x"AE43",'1'&x"AE44",'1'&x"AE45",'1'&x"AE46",'1'&x"AE47",'1'&x"AE48",'1'&x"AE49",'1'&x"AE4A",'1'&x"AE4B",'1'&x"AE4C",'1'&x"AE4D",'1'&x"AE4E",'1'&x"AE4F",
+--'1'&x"AE50",'1'&x"AE51",'1'&x"AE52",'1'&x"AE53",'1'&x"AE54",'1'&x"AE55",'1'&x"AE56",'1'&x"AE57",'1'&x"AE58",'1'&x"AE59",'1'&x"AE5A",'1'&x"AE5B",'1'&x"AE5C",'1'&x"AE5D",'1'&x"AE5E",'1'&x"AE5F",
+--'1'&x"AE60",'1'&x"AE61",'1'&x"AE62",'1'&x"AE63",'1'&x"AE64",'1'&x"AE65",'1'&x"AE66",'1'&x"AE67",'1'&x"AE68",'1'&x"AE69",'1'&x"AE6A",'1'&x"AE6B",'1'&x"AE6C",'1'&x"AE6D",'1'&x"AE6E",'1'&x"AE6F",
+--'1'&x"AE70",'1'&x"AE71",'1'&x"AE72",'1'&x"AE73",'1'&x"AE74",'1'&x"AE75",'1'&x"AE76",'1'&x"AE77",'1'&x"AE78",'1'&x"AE79",'1'&x"AE7A",'1'&x"AE7B",'1'&x"AE7C",'1'&x"AE7D",'1'&x"AE7E",'1'&x"AE7F",
+--'1'&x"AE80",'1'&x"AE81",'1'&x"AE82",'1'&x"AE83",'1'&x"AE84",'1'&x"AE85",'1'&x"AE86",'1'&x"AE87",'1'&x"AE88",'1'&x"AE89",'1'&x"AE8A",'1'&x"AE8B",'1'&x"AE8C",'1'&x"AE8D",'1'&x"AE8E",'1'&x"AE8F",
+--'1'&x"AE90",'1'&x"AE91",'1'&x"AE92",'1'&x"AE93",'1'&x"AE94",'1'&x"AE95",'1'&x"AE96",'1'&x"AE97",'1'&x"AE98",'1'&x"AE99",'1'&x"AE9A",'1'&x"AE9B",'1'&x"AE9C",'1'&x"AE9D",'1'&x"AE9E",'1'&x"AE9F",
+--'1'&x"AEA0",'1'&x"AEA1",'1'&x"AEA2",'1'&x"AEA3",'1'&x"AEA4",'1'&x"AEA5",'1'&x"AEA6",'1'&x"AEA7",'1'&x"AEA8",'1'&x"AEA9",'1'&x"AEAA",'1'&x"AEAB",'1'&x"AEAC",'1'&x"AEAD",'1'&x"AEAE",'1'&x"AEAF",
+--'1'&x"AEB0",'1'&x"AEB1",'1'&x"AEB2",'1'&x"AEB3",'1'&x"AEB4",'1'&x"AEB5",'1'&x"AEB6",'1'&x"AEB7",'1'&x"AEB8",'1'&x"AEB9",'1'&x"AEBA",'1'&x"AEBB",'1'&x"AEBC",'1'&x"AEBD",'1'&x"AEBE",'1'&x"AEBF",
+--'1'&x"AEC0",'1'&x"AEC1",'1'&x"AEC2",'1'&x"AEC3",'1'&x"AEC4",'1'&x"AEC5",'1'&x"AEC6",'1'&x"AEC7",'1'&x"AEC8",'1'&x"AEC9",'1'&x"AECA",'1'&x"AECB",'1'&x"AECC",'1'&x"AECD",'1'&x"AECE",'1'&x"AECF",
+--'1'&x"AED0",'1'&x"AED1",'1'&x"AED2",'1'&x"AED3",'1'&x"AED4",'1'&x"AED5",'1'&x"AED6",'1'&x"AED7",'1'&x"AED8",'1'&x"AED9",'1'&x"AEDA",'1'&x"AEDB",'1'&x"AEDC",'1'&x"AEDD",'1'&x"AEDE",'1'&x"AEDF",
+--'1'&x"AEE0",'1'&x"AEE1",'1'&x"AEE2",'1'&x"AEE3",'1'&x"AEE4",'1'&x"AEE5",'1'&x"AEE6",'1'&x"AEE7",'1'&x"AEE8",'1'&x"AEE9",'1'&x"AEEA",'1'&x"AEEB",'1'&x"AEEC",'1'&x"AEED",'1'&x"AEEE",'1'&x"AEEF",
+--'1'&x"AEF0",'1'&x"AEF1",'1'&x"AEF2",'1'&x"AEF3",'1'&x"AEF4",'1'&x"AEF5",'1'&x"AEF6",'1'&x"AEF7",'1'&x"AEF8",'1'&x"AEF9",'1'&x"AEFA",'1'&x"AEFB",'1'&x"AEFC",'1'&x"AEFD",'1'&x"AEFE",'1'&x"AEFF",
+--'1'&x"AF00",'1'&x"AF01",'1'&x"AF02",'1'&x"AF03",'1'&x"AF04",'1'&x"AF05",'1'&x"AF06",'1'&x"AF07",'1'&x"AF08",'1'&x"AF09",'1'&x"AF0A",'1'&x"AF0B",'1'&x"AF0C",'1'&x"AF0D",'1'&x"AF0E",'1'&x"AF0F",
+--'1'&x"AF10",'1'&x"AF11",'1'&x"AF12",'1'&x"AF13",'1'&x"AF14",'1'&x"AF15",'1'&x"AF16",'1'&x"AF17",'1'&x"AF18",'1'&x"AF19",'1'&x"AF1A",'1'&x"AF1B",'1'&x"AF1C",'1'&x"AF1D",'1'&x"AF1E",'1'&x"AF1F",
+--'1'&x"AF20",'1'&x"AF21",'1'&x"AF22",'1'&x"AF23",'1'&x"AF24",'1'&x"AF25",'1'&x"AF26",'1'&x"AF27",'1'&x"AF28",'1'&x"AF29",'1'&x"AF2A",'1'&x"AF2B",'1'&x"AF2C",'1'&x"AF2D",'1'&x"AF2E",'1'&x"AF2F",
+--'1'&x"AF30",'1'&x"AF31",'1'&x"AF32",'1'&x"AF33",'1'&x"AF34",'1'&x"AF35",'1'&x"AF36",'1'&x"AF37",'1'&x"AF38",'1'&x"AF39",'1'&x"AF3A",'1'&x"AF3B",'1'&x"AF3C",'1'&x"AF3D",'1'&x"AF3E",'1'&x"AF3F",
+--'1'&x"AF40",'1'&x"AF41",'1'&x"AF42",'1'&x"AF43",'1'&x"AF44",'1'&x"AF45",'1'&x"AF46",'1'&x"AF47",'1'&x"AF48",'1'&x"AF49",'1'&x"AF4A",'1'&x"AF4B",'1'&x"AF4C",'1'&x"AF4D",'1'&x"AF4E",'1'&x"AF4F",
+--'1'&x"AF50",'1'&x"AF51",'1'&x"AF52",'1'&x"AF53",'1'&x"AF54",'1'&x"AF55",'1'&x"AF56",'1'&x"AF57",'1'&x"AF58",'1'&x"AF59",'1'&x"AF5A",'1'&x"AF5B",'1'&x"AF5C",'1'&x"AF5D",'1'&x"AF5E",'1'&x"AF5F",
+--'1'&x"AF60",'1'&x"AF61",'1'&x"AF62",'1'&x"AF63",'1'&x"AF64",'1'&x"AF65",'1'&x"AF66",'1'&x"AF67",'1'&x"AF68",'1'&x"AF69",'1'&x"AF6A",'1'&x"AF6B",'1'&x"AF6C",'1'&x"AF6D",'1'&x"AF6E",'1'&x"AF6F",
+--'1'&x"AF70",'1'&x"AF71",'1'&x"AF72",'1'&x"AF73",'1'&x"AF74",'1'&x"AF75",'1'&x"AF76",'1'&x"AF77",'1'&x"AF78",'1'&x"AF79",'1'&x"AF7A",'1'&x"AF7B",'1'&x"AF7C",'1'&x"AF7D",'1'&x"AF7E",'1'&x"AF7F",
+--'1'&x"AF80",'1'&x"AF81",'1'&x"AF82",'1'&x"AF83",'1'&x"AF84",'1'&x"AF85",'1'&x"AF86",'1'&x"AF87",'1'&x"AF88",'1'&x"AF89",'1'&x"AF8A",'1'&x"AF8B",'1'&x"AF8C",'1'&x"AF8D",'1'&x"AF8E",'1'&x"AF8F",
+--'1'&x"AF90",'1'&x"AF91",'1'&x"AF92",'1'&x"AF93",'1'&x"AF94",'1'&x"AF95",'1'&x"AF96",'1'&x"AF97",'1'&x"AF98",'1'&x"AF99",'1'&x"AF9A",'1'&x"AF9B",'1'&x"AF9C",'1'&x"AF9D",'1'&x"AF9E",'1'&x"AF9F",
+--'1'&x"AFA0",'1'&x"AFA1",'1'&x"AFA2",'1'&x"AFA3",'1'&x"AFA4",'1'&x"AFA5",'1'&x"AFA6",'1'&x"AFA7",'1'&x"AFA8",'1'&x"AFA9",'1'&x"AFAA",'1'&x"AFAB",'1'&x"AFAC",'1'&x"AFAD",'1'&x"AFAE",'1'&x"AFAF",
+--'1'&x"AFB0",'1'&x"AFB1",'1'&x"AFB2",'1'&x"AFB3",'1'&x"AFB4",'1'&x"AFB5",'1'&x"AFB6",'1'&x"AFB7",'1'&x"AFB8",'1'&x"AFB9",'1'&x"AFBA",'1'&x"AFBB",'1'&x"AFBC",'1'&x"AFBD",'1'&x"AFBE",'1'&x"AFBF",
+--'1'&x"AFC0",'1'&x"AFC1",'1'&x"AFC2",'1'&x"AFC3",'1'&x"AFC4",'1'&x"AFC5",'1'&x"AFC6",'1'&x"AFC7",'1'&x"AFC8",'1'&x"AFC9",'1'&x"AFCA",'1'&x"AFCB",'1'&x"AFCC",'1'&x"AFCD",'1'&x"AFCE",'1'&x"AFCF",
+--'1'&x"AFD0",'1'&x"AFD1",'1'&x"AFD2",'1'&x"AFD3",'1'&x"AFD4",'1'&x"AFD5",'1'&x"AFD6",'1'&x"AFD7",'1'&x"AFD8",'1'&x"AFD9",'1'&x"AFDA",'1'&x"AFDB",'1'&x"AFDC",'1'&x"AFDD",'1'&x"AFDE",'1'&x"AFDF",
+--'1'&x"AFE0",'1'&x"AFE1",'1'&x"AFE2",'1'&x"AFE3",'1'&x"AFE4",'1'&x"AFE5",'1'&x"AFE6",'1'&x"AFE7",'1'&x"AFE8",'1'&x"AFE9",'1'&x"AFEA",'1'&x"AFEB",'1'&x"AFEC",'1'&x"AFED",'1'&x"AFEE",'1'&x"AFEF",
+--'1'&x"AFF0",'1'&x"AFF1",'1'&x"AFF2",'1'&x"AFF3",'1'&x"AFF4",'1'&x"AFF5",'1'&x"AFF6",'1'&x"AFF7",'1'&x"AFF8",'1'&x"AFF9",'1'&x"AFFA",'1'&x"AFFB",'1'&x"AFFC",'1'&x"AFFD",'1'&x"AFFE",'1'&x"AFFF",
+--'1'&x"B000",'1'&x"B001",'1'&x"B002",'1'&x"B003",'1'&x"B004",'1'&x"B005",'1'&x"B006",'1'&x"B007",'1'&x"B008",'1'&x"B009",'1'&x"B00A",'1'&x"B00B",'1'&x"B00C",'1'&x"B00D",'1'&x"B00E",'1'&x"B00F",
+--'1'&x"B010",'1'&x"B011",'1'&x"B012",'1'&x"B013",'1'&x"B014",'1'&x"B015",'1'&x"B016",'1'&x"B017",'1'&x"B018",'1'&x"B019",'1'&x"B01A",'1'&x"B01B",'1'&x"B01C",'1'&x"B01D",'1'&x"B01E",'1'&x"B01F",
+--'1'&x"B020",'1'&x"B021",'1'&x"B022",'1'&x"B023",'1'&x"B024",'1'&x"B025",'1'&x"B026",'1'&x"B027",'1'&x"B028",'1'&x"B029",'1'&x"B02A",'1'&x"B02B",'1'&x"B02C",'1'&x"B02D",'1'&x"B02E",'1'&x"B02F",
+--'1'&x"B030",'1'&x"B031",'1'&x"B032",'1'&x"B033",'1'&x"B034",'1'&x"B035",'1'&x"B036",'1'&x"B037",'1'&x"B038",'1'&x"B039",'1'&x"B03A",'1'&x"B03B",'1'&x"B03C",'1'&x"B03D",'1'&x"B03E",'1'&x"B03F",
+--'1'&x"B040",'1'&x"B041",'1'&x"B042",'1'&x"B043",'1'&x"B044",'1'&x"B045",'1'&x"B046",'1'&x"B047",'1'&x"B048",'1'&x"B049",'1'&x"B04A",'1'&x"B04B",'1'&x"B04C",'1'&x"B04D",'1'&x"B04E",'1'&x"B04F",
+--'1'&x"B050",'1'&x"B051",'1'&x"B052",'1'&x"B053",'1'&x"B054",'1'&x"B055",'1'&x"B056",'1'&x"B057",'1'&x"B058",'1'&x"B059",'1'&x"B05A",'1'&x"B05B",'1'&x"B05C",'1'&x"B05D",'1'&x"B05E",'1'&x"B05F",
+--'1'&x"B060",'1'&x"B061",'1'&x"B062",'1'&x"B063",'1'&x"B064",'1'&x"B065",'1'&x"B066",'1'&x"B067",'1'&x"B068",'1'&x"B069",'1'&x"B06A",'1'&x"B06B",'1'&x"B06C",'1'&x"B06D",'1'&x"B06E",'1'&x"B06F",
+--'1'&x"B070",'1'&x"B071",'1'&x"B072",'1'&x"B073",'1'&x"B074",'1'&x"B075",'1'&x"B076",'1'&x"B077",'1'&x"B078",'1'&x"B079",'1'&x"B07A",'1'&x"B07B",'1'&x"B07C",'1'&x"B07D",'1'&x"B07E",'1'&x"B07F",
+--'1'&x"B080",'1'&x"B081",'1'&x"B082",'1'&x"B083",'1'&x"B084",'1'&x"B085",'1'&x"B086",'1'&x"B087",'1'&x"B088",'1'&x"B089",'1'&x"B08A",'1'&x"B08B",'1'&x"B08C",'1'&x"B08D",'1'&x"B08E",'1'&x"B08F",
+--'1'&x"B090",'1'&x"B091",'1'&x"B092",'1'&x"B093",'1'&x"B094",'1'&x"B095",'1'&x"B096",'1'&x"B097",'1'&x"B098",'1'&x"B099",'1'&x"B09A",'1'&x"B09B",'1'&x"B09C",'1'&x"B09D",'1'&x"B09E",'1'&x"B09F",
+--'1'&x"B0A0",'1'&x"B0A1",'1'&x"B0A2",'1'&x"B0A3",'1'&x"B0A4",'1'&x"B0A5",'1'&x"B0A6",'1'&x"B0A7",'1'&x"B0A8",'1'&x"B0A9",'1'&x"B0AA",'1'&x"B0AB",'1'&x"B0AC",'1'&x"B0AD",'1'&x"B0AE",'1'&x"B0AF",
+--'1'&x"B0B0",'1'&x"B0B1",'1'&x"B0B2",'1'&x"B0B3",'1'&x"B0B4",'1'&x"B0B5",'1'&x"B0B6",'1'&x"B0B7",'1'&x"B0B8",'1'&x"B0B9",'1'&x"B0BA",'1'&x"B0BB",'1'&x"B0BC",'1'&x"B0BD",'1'&x"B0BE",'1'&x"B0BF",
+--'1'&x"B0C0",'1'&x"B0C1",'1'&x"B0C2",'1'&x"B0C3",'1'&x"B0C4",'1'&x"B0C5",'1'&x"B0C6",'1'&x"B0C7",'1'&x"B0C8",'1'&x"B0C9",'1'&x"B0CA",'1'&x"B0CB",'1'&x"B0CC",'1'&x"B0CD",'1'&x"B0CE",'1'&x"B0CF",
+--'1'&x"B0D0",'1'&x"B0D1",'1'&x"B0D2",'1'&x"B0D3",'1'&x"B0D4",'1'&x"B0D5",'1'&x"B0D6",'1'&x"B0D7",'1'&x"B0D8",'1'&x"B0D9",'1'&x"B0DA",'1'&x"B0DB",'1'&x"B0DC",'1'&x"B0DD",'1'&x"B0DE",'1'&x"B0DF",
+--'1'&x"B0E0",'1'&x"B0E1",'1'&x"B0E2",'1'&x"B0E3",'1'&x"B0E4",'1'&x"B0E5",'1'&x"B0E6",'1'&x"B0E7",'1'&x"B0E8",'1'&x"B0E9",'1'&x"B0EA",'1'&x"B0EB",'1'&x"B0EC",'1'&x"B0ED",'1'&x"B0EE",'1'&x"B0EF",
+--'1'&x"B0F0",'1'&x"B0F1",'1'&x"B0F2",'1'&x"B0F3",'1'&x"B0F4",'1'&x"B0F5",'1'&x"B0F6",'1'&x"B0F7",'1'&x"B0F8",'1'&x"B0F9",'1'&x"B0FA",'1'&x"B0FB",'1'&x"B0FC",'1'&x"B0FD",'1'&x"B0FE",'1'&x"B0FF",
+--'1'&x"B100",'1'&x"B101",'1'&x"B102",'1'&x"B103",'1'&x"B104",'1'&x"B105",'1'&x"B106",'1'&x"B107",'1'&x"B108",'1'&x"B109",'1'&x"B10A",'1'&x"B10B",'1'&x"B10C",'1'&x"B10D",'1'&x"B10E",'1'&x"B10F",
+--'1'&x"B110",'1'&x"B111",'1'&x"B112",'1'&x"B113",'1'&x"B114",'1'&x"B115",'1'&x"B116",'1'&x"B117",'1'&x"B118",'1'&x"B119",'1'&x"B11A",'1'&x"B11B",'1'&x"B11C",'1'&x"B11D",'1'&x"B11E",'1'&x"B11F",
+--'1'&x"B120",'1'&x"B121",'1'&x"B122",'1'&x"B123",'1'&x"B124",'1'&x"B125",'1'&x"B126",'1'&x"B127",'1'&x"B128",'1'&x"B129",'1'&x"B12A",'1'&x"B12B",'1'&x"B12C",'1'&x"B12D",'1'&x"B12E",'1'&x"B12F",
+--'1'&x"B130",'1'&x"B131",'1'&x"B132",'1'&x"B133",'1'&x"B134",'1'&x"B135",'1'&x"B136",'1'&x"B137",'1'&x"B138",'1'&x"B139",'1'&x"B13A",'1'&x"B13B",'1'&x"B13C",'1'&x"B13D",'1'&x"B13E",'1'&x"B13F",
+--'1'&x"B140",'1'&x"B141",'1'&x"B142",'1'&x"B143",'1'&x"B144",'1'&x"B145",'1'&x"B146",'1'&x"B147",'1'&x"B148",'1'&x"B149",'1'&x"B14A",'1'&x"B14B",'1'&x"B14C",'1'&x"B14D",'1'&x"B14E",'1'&x"B14F",
+--'1'&x"B150",'1'&x"B151",'1'&x"B152",'1'&x"B153",'1'&x"B154",'1'&x"B155",'1'&x"B156",'1'&x"B157",'1'&x"B158",'1'&x"B159",'1'&x"B15A",'1'&x"B15B",'1'&x"B15C",'1'&x"B15D",'1'&x"B15E",'1'&x"B15F",
+--'1'&x"B160",'1'&x"B161",'1'&x"B162",'1'&x"B163",'1'&x"B164",'1'&x"B165",'1'&x"B166",'1'&x"B167",'1'&x"B168",'1'&x"B169",'1'&x"B16A",'1'&x"B16B",'1'&x"B16C",'1'&x"B16D",'1'&x"B16E",'1'&x"B16F",
+--'1'&x"B170",'1'&x"B171",'1'&x"B172",'1'&x"B173",'1'&x"B174",'1'&x"B175",'1'&x"B176",'1'&x"B177",'1'&x"B178",'1'&x"B179",'1'&x"B17A",'1'&x"B17B",'1'&x"B17C",'1'&x"B17D",'1'&x"B17E",'1'&x"B17F",
+--'1'&x"B180",'1'&x"B181",'1'&x"B182",'1'&x"B183",'1'&x"B184",'1'&x"B185",'1'&x"B186",'1'&x"B187",'1'&x"B188",'1'&x"B189",'1'&x"B18A",'1'&x"B18B",'1'&x"B18C",'1'&x"B18D",'1'&x"B18E",'1'&x"B18F",
+--'1'&x"B190",'1'&x"B191",'1'&x"B192",'1'&x"B193",'1'&x"B194",'1'&x"B195",'1'&x"B196",'1'&x"B197",'1'&x"B198",'1'&x"B199",'1'&x"B19A",'1'&x"B19B",'1'&x"B19C",'1'&x"B19D",'1'&x"B19E",'1'&x"B19F",
+--'1'&x"B1A0",'1'&x"B1A1",'1'&x"B1A2",'1'&x"B1A3",'1'&x"B1A4",'1'&x"B1A5",'1'&x"B1A6",'1'&x"B1A7",'1'&x"B1A8",'1'&x"B1A9",'1'&x"B1AA",'1'&x"B1AB",'1'&x"B1AC",'1'&x"B1AD",'1'&x"B1AE",'1'&x"B1AF",
+--'1'&x"B1B0",'1'&x"B1B1",'1'&x"B1B2",'1'&x"B1B3",'1'&x"B1B4",'1'&x"B1B5",'1'&x"B1B6",'1'&x"B1B7",'1'&x"B1B8",'1'&x"B1B9",'1'&x"B1BA",'1'&x"B1BB",'1'&x"B1BC",'1'&x"B1BD",'1'&x"B1BE",'1'&x"B1BF",
+--'1'&x"B1C0",'1'&x"B1C1",'1'&x"B1C2",'1'&x"B1C3",'1'&x"B1C4",'1'&x"B1C5",'1'&x"B1C6",'1'&x"B1C7",'1'&x"B1C8",'1'&x"B1C9",'1'&x"B1CA",'1'&x"B1CB",'1'&x"B1CC",'1'&x"B1CD",'1'&x"B1CE",'1'&x"B1CF",
+--'1'&x"B1D0",'1'&x"B1D1",'1'&x"B1D2",'1'&x"B1D3",'1'&x"B1D4",'1'&x"B1D5",'1'&x"B1D6",'1'&x"B1D7",'1'&x"B1D8",'1'&x"B1D9",'1'&x"B1DA",'1'&x"B1DB",'1'&x"B1DC",'1'&x"B1DD",'1'&x"B1DE",'1'&x"B1DF",
+--'1'&x"B1E0",'1'&x"B1E1",'1'&x"B1E2",'1'&x"B1E3",'1'&x"B1E4",'1'&x"B1E5",'1'&x"B1E6",'1'&x"B1E7",'1'&x"B1E8",'1'&x"B1E9",'1'&x"B1EA",'1'&x"B1EB",'1'&x"B1EC",'1'&x"B1ED",'1'&x"B1EE",'1'&x"B1EF",
+--'1'&x"B1F0",'1'&x"B1F1",'1'&x"B1F2",'1'&x"B1F3",'1'&x"B1F4",'1'&x"B1F5",'1'&x"B1F6",'1'&x"B1F7",'1'&x"B1F8",'1'&x"B1F9",'1'&x"B1FA",'1'&x"B1FB",'1'&x"B1FC",'1'&x"B1FD",'1'&x"B1FE",'1'&x"B1FF",
+--'1'&x"B200",'1'&x"B201",'1'&x"B202",'1'&x"B203",'1'&x"B204",'1'&x"B205",'1'&x"B206",'1'&x"B207",'1'&x"B208",'1'&x"B209",'1'&x"B20A",'1'&x"B20B",'1'&x"B20C",'1'&x"B20D",'1'&x"B20E",'1'&x"B20F",
+--'1'&x"B210",'1'&x"B211",'1'&x"B212",'1'&x"B213",'1'&x"B214",'1'&x"B215",'1'&x"B216",'1'&x"B217",'1'&x"B218",'1'&x"B219",'1'&x"B21A",'1'&x"B21B",'1'&x"B21C",'1'&x"B21D",'1'&x"B21E",'1'&x"B21F",
+--'1'&x"B220",'1'&x"B221",'1'&x"B222",'1'&x"B223",'1'&x"B224",'1'&x"B225",'1'&x"B226",'1'&x"B227",'1'&x"B228",'1'&x"B229",'1'&x"B22A",'1'&x"B22B",'1'&x"B22C",'1'&x"B22D",'1'&x"B22E",'1'&x"B22F",
+--'1'&x"B230",'1'&x"B231",'1'&x"B232",'1'&x"B233",'1'&x"B234",'1'&x"B235",'1'&x"B236",'1'&x"B237",'1'&x"B238",'1'&x"B239",'1'&x"B23A",'1'&x"B23B",'1'&x"B23C",'1'&x"B23D",'1'&x"B23E",'1'&x"B23F",
+--'1'&x"B240",'1'&x"B241",'1'&x"B242",'1'&x"B243",'1'&x"B244",'1'&x"B245",'1'&x"B246",'1'&x"B247",'1'&x"B248",'1'&x"B249",'1'&x"B24A",'1'&x"B24B",'1'&x"B24C",'1'&x"B24D",'1'&x"B24E",'1'&x"B24F",
+--'1'&x"B250",'1'&x"B251",'1'&x"B252",'1'&x"B253",'1'&x"B254",'1'&x"B255",'1'&x"B256",'1'&x"B257",'1'&x"B258",'1'&x"B259",'1'&x"B25A",'1'&x"B25B",'1'&x"B25C",'1'&x"B25D",'1'&x"B25E",'1'&x"B25F",
+--'1'&x"B260",'1'&x"B261",'1'&x"B262",'1'&x"B263",'1'&x"B264",'1'&x"B265",'1'&x"B266",'1'&x"B267",'1'&x"B268",'1'&x"B269",'1'&x"B26A",'1'&x"B26B",'1'&x"B26C",'1'&x"B26D",'1'&x"B26E",'1'&x"B26F",
+--'1'&x"B270",'1'&x"B271",'1'&x"B272",'1'&x"B273",'1'&x"B274",'1'&x"B275",'1'&x"B276",'1'&x"B277",'1'&x"B278",'1'&x"B279",'1'&x"B27A",'1'&x"B27B",'1'&x"B27C",'1'&x"B27D",'1'&x"B27E",'1'&x"B27F",
+--'1'&x"B280",'1'&x"B281",'1'&x"B282",'1'&x"B283",'1'&x"B284",'1'&x"B285",'1'&x"B286",'1'&x"B287",'1'&x"B288",'1'&x"B289",'1'&x"B28A",'1'&x"B28B",'1'&x"B28C",'1'&x"B28D",'1'&x"B28E",'1'&x"B28F",
+--'1'&x"B290",'1'&x"B291",'1'&x"B292",'1'&x"B293",'1'&x"B294",'1'&x"B295",'1'&x"B296",'1'&x"B297",'1'&x"B298",'1'&x"B299",'1'&x"B29A",'1'&x"B29B",'1'&x"B29C",'1'&x"B29D",'1'&x"B29E",'1'&x"B29F",
+--'1'&x"B2A0",'1'&x"B2A1",'1'&x"B2A2",'1'&x"B2A3",'1'&x"B2A4",'1'&x"B2A5",'1'&x"B2A6",'1'&x"B2A7",'1'&x"B2A8",'1'&x"B2A9",'1'&x"B2AA",'1'&x"B2AB",'1'&x"B2AC",'1'&x"B2AD",'1'&x"B2AE",'1'&x"B2AF",
+--'1'&x"B2B0",'1'&x"B2B1",'1'&x"B2B2",'1'&x"B2B3",'1'&x"B2B4",'1'&x"B2B5",'1'&x"B2B6",'1'&x"B2B7",'1'&x"B2B8",'1'&x"B2B9",'1'&x"B2BA",'1'&x"B2BB",'1'&x"B2BC",'1'&x"B2BD",'1'&x"B2BE",'1'&x"B2BF",
+--'1'&x"B2C0",'1'&x"B2C1",'1'&x"B2C2",'1'&x"B2C3",'1'&x"B2C4",'1'&x"B2C5",'1'&x"B2C6",'1'&x"B2C7",'1'&x"B2C8",'1'&x"B2C9",'1'&x"B2CA",'1'&x"B2CB",'1'&x"B2CC",'1'&x"B2CD",'1'&x"B2CE",'1'&x"B2CF",
+--'1'&x"B2D0",'1'&x"B2D1",'1'&x"B2D2",'1'&x"B2D3",'1'&x"B2D4",'1'&x"B2D5",'1'&x"B2D6",'1'&x"B2D7",'1'&x"B2D8",'1'&x"B2D9",'1'&x"B2DA",'1'&x"B2DB",'1'&x"B2DC",'1'&x"B2DD",'1'&x"B2DE",'1'&x"B2DF",
+--'1'&x"B2E0",'1'&x"B2E1",'1'&x"B2E2",'1'&x"B2E3",'1'&x"B2E4",'1'&x"B2E5",'1'&x"B2E6",'1'&x"B2E7",'1'&x"B2E8",'1'&x"B2E9",'1'&x"B2EA",'1'&x"B2EB",'1'&x"B2EC",'1'&x"B2ED",'1'&x"B2EE",'1'&x"B2EF",
+--'1'&x"B2F0",'1'&x"B2F1",'1'&x"B2F2",'1'&x"B2F3",'1'&x"B2F4",'1'&x"B2F5",'1'&x"B2F6",'1'&x"B2F7",'1'&x"B2F8",'1'&x"B2F9",'1'&x"B2FA",'1'&x"B2FB",'1'&x"B2FC",'1'&x"B2FD",'1'&x"B2FE",'1'&x"B2FF",
+--'1'&x"B300",'1'&x"B301",'1'&x"B302",'1'&x"B303",'1'&x"B304",'1'&x"B305",'1'&x"B306",'1'&x"B307",'1'&x"B308",'1'&x"B309",'1'&x"B30A",'1'&x"B30B",'1'&x"B30C",'1'&x"B30D",'1'&x"B30E",'1'&x"B30F",
+--'1'&x"B310",'1'&x"B311",'1'&x"B312",'1'&x"B313",'1'&x"B314",'1'&x"B315",'1'&x"B316",'1'&x"B317",'1'&x"B318",'1'&x"B319",'1'&x"B31A",'1'&x"B31B",'1'&x"B31C",'1'&x"B31D",'1'&x"B31E",'1'&x"B31F",
+--'1'&x"B320",'1'&x"B321",'1'&x"B322",'1'&x"B323",'1'&x"B324",'1'&x"B325",'1'&x"B326",'1'&x"B327",'1'&x"B328",'1'&x"B329",'1'&x"B32A",'1'&x"B32B",'1'&x"B32C",'1'&x"B32D",'1'&x"B32E",'1'&x"B32F",
+--'1'&x"B330",'1'&x"B331",'1'&x"B332",'1'&x"B333",'1'&x"B334",'1'&x"B335",'1'&x"B336",'1'&x"B337",'1'&x"B338",'1'&x"B339",'1'&x"B33A",'1'&x"B33B",'1'&x"B33C",'1'&x"B33D",'1'&x"B33E",'1'&x"B33F",
+--'1'&x"B340",'1'&x"B341",'1'&x"B342",'1'&x"B343",'1'&x"B344",'1'&x"B345",'1'&x"B346",'1'&x"B347",'1'&x"B348",'1'&x"B349",'1'&x"B34A",'1'&x"B34B",'1'&x"B34C",'1'&x"B34D",'1'&x"B34E",'1'&x"B34F",
+--'1'&x"B350",'1'&x"B351",'1'&x"B352",'1'&x"B353",'1'&x"B354",'1'&x"B355",'1'&x"B356",'1'&x"B357",'1'&x"B358",'1'&x"B359",'1'&x"B35A",'1'&x"B35B",'1'&x"B35C",'1'&x"B35D",'1'&x"B35E",'1'&x"B35F",
+--'1'&x"B360",'1'&x"B361",'1'&x"B362",'1'&x"B363",'1'&x"B364",'1'&x"B365",'1'&x"B366",'1'&x"B367",'1'&x"B368",'1'&x"B369",'1'&x"B36A",'1'&x"B36B",'1'&x"B36C",'1'&x"B36D",'1'&x"B36E",'1'&x"B36F",
+--'1'&x"B370",'1'&x"B371",'1'&x"B372",'1'&x"B373",'1'&x"B374",'1'&x"B375",'1'&x"B376",'1'&x"B377",'1'&x"B378",'1'&x"B379",'1'&x"B37A",'1'&x"B37B",'1'&x"B37C",'1'&x"B37D",'1'&x"B37E",'1'&x"B37F",
+--'1'&x"B380",'1'&x"B381",'1'&x"B382",'1'&x"B383",'1'&x"B384",'1'&x"B385",'1'&x"B386",'1'&x"B387",'1'&x"B388",'1'&x"B389",'1'&x"B38A",'1'&x"B38B",'1'&x"B38C",'1'&x"B38D",'1'&x"B38E",'1'&x"B38F",
+--'1'&x"B390",'1'&x"B391",'1'&x"B392",'1'&x"B393",'1'&x"B394",'1'&x"B395",'1'&x"B396",'1'&x"B397",'1'&x"B398",'1'&x"B399",'1'&x"B39A",'1'&x"B39B",'1'&x"B39C",'1'&x"B39D",'1'&x"B39E",'1'&x"B39F",
+--'1'&x"B3A0",'1'&x"B3A1",'1'&x"B3A2",'1'&x"B3A3",'1'&x"B3A4",'1'&x"B3A5",'1'&x"B3A6",'1'&x"B3A7",'1'&x"B3A8",'1'&x"B3A9",'1'&x"B3AA",'1'&x"B3AB",'1'&x"B3AC",'1'&x"B3AD",'1'&x"B3AE",'1'&x"B3AF",
+--'1'&x"B3B0",'1'&x"B3B1",'1'&x"B3B2",'1'&x"B3B3",'1'&x"B3B4",'1'&x"B3B5",'1'&x"B3B6",'1'&x"B3B7",'1'&x"B3B8",'1'&x"B3B9",'1'&x"B3BA",'1'&x"B3BB",'1'&x"B3BC",'1'&x"B3BD",'1'&x"B3BE",'1'&x"B3BF",
+--'1'&x"B3C0",'1'&x"B3C1",'1'&x"B3C2",'1'&x"B3C3",'1'&x"B3C4",'1'&x"B3C5",'1'&x"B3C6",'1'&x"B3C7",'1'&x"B3C8",'1'&x"B3C9",'1'&x"B3CA",'1'&x"B3CB",'1'&x"B3CC",'1'&x"B3CD",'1'&x"B3CE",'1'&x"B3CF",
+--'1'&x"B3D0",'1'&x"B3D1",'1'&x"B3D2",'1'&x"B3D3",'1'&x"B3D4",'1'&x"B3D5",'1'&x"B3D6",'1'&x"B3D7",'1'&x"B3D8",'1'&x"B3D9",'1'&x"B3DA",'1'&x"B3DB",'1'&x"B3DC",'1'&x"B3DD",'1'&x"B3DE",'1'&x"B3DF",
+--'1'&x"B3E0",'1'&x"B3E1",'1'&x"B3E2",'1'&x"B3E3",'1'&x"B3E4",'1'&x"B3E5",'1'&x"B3E6",'1'&x"B3E7",'1'&x"B3E8",'1'&x"B3E9",'1'&x"B3EA",'1'&x"B3EB",'1'&x"B3EC",'1'&x"B3ED",'1'&x"B3EE",'1'&x"B3EF",
+--'1'&x"B3F0",'1'&x"B3F1",'1'&x"B3F2",'1'&x"B3F3",'1'&x"B3F4",'1'&x"B3F5",'1'&x"B3F6",'1'&x"B3F7",'1'&x"B3F8",'1'&x"B3F9",'1'&x"B3FA",'1'&x"B3FB",'1'&x"B3FC",'1'&x"B3FD",'1'&x"B3FE",'1'&x"B3FF",
+--'1'&x"B400",'1'&x"B401",'1'&x"B402",'1'&x"B403",'1'&x"B404",'1'&x"B405",'1'&x"B406",'1'&x"B407",'1'&x"B408",'1'&x"B409",'1'&x"B40A",'1'&x"B40B",'1'&x"B40C",'1'&x"B40D",'1'&x"B40E",'1'&x"B40F",
+--'1'&x"B410",'1'&x"B411",'1'&x"B412",'1'&x"B413",'1'&x"B414",'1'&x"B415",'1'&x"B416",'1'&x"B417",'1'&x"B418",'1'&x"B419",'1'&x"B41A",'1'&x"B41B",'1'&x"B41C",'1'&x"B41D",'1'&x"B41E",'1'&x"B41F",
+--'1'&x"B420",'1'&x"B421",'1'&x"B422",'1'&x"B423",'1'&x"B424",'1'&x"B425",'1'&x"B426",'1'&x"B427",'1'&x"B428",'1'&x"B429",'1'&x"B42A",'1'&x"B42B",'1'&x"B42C",'1'&x"B42D",'1'&x"B42E",'1'&x"B42F",
+--'1'&x"B430",'1'&x"B431",'1'&x"B432",'1'&x"B433",'1'&x"B434",'1'&x"B435",'1'&x"B436",'1'&x"B437",'1'&x"B438",'1'&x"B439",'1'&x"B43A",'1'&x"B43B",'1'&x"B43C",'1'&x"B43D",'1'&x"B43E",'1'&x"B43F",
+--'1'&x"B440",'1'&x"B441",'1'&x"B442",'1'&x"B443",'1'&x"B444",'1'&x"B445",'1'&x"B446",'1'&x"B447",'1'&x"B448",'1'&x"B449",'1'&x"B44A",'1'&x"B44B",'1'&x"B44C",'1'&x"B44D",'1'&x"B44E",'1'&x"B44F",
+--'1'&x"B450",'1'&x"B451",'1'&x"B452",'1'&x"B453",'1'&x"B454",'1'&x"B455",'1'&x"B456",'1'&x"B457",'1'&x"B458",'1'&x"B459",'1'&x"B45A",'1'&x"B45B",'1'&x"B45C",'1'&x"B45D",'1'&x"B45E",'1'&x"B45F",
+--'1'&x"B460",'1'&x"B461",'1'&x"B462",'1'&x"B463",'1'&x"B464",'1'&x"B465",'1'&x"B466",'1'&x"B467",'1'&x"B468",'1'&x"B469",'1'&x"B46A",'1'&x"B46B",'1'&x"B46C",'1'&x"B46D",'1'&x"B46E",'1'&x"B46F",
+--'1'&x"B470",'1'&x"B471",'1'&x"B472",'1'&x"B473",'1'&x"B474",'1'&x"B475",'1'&x"B476",'1'&x"B477",'1'&x"B478",'1'&x"B479",'1'&x"B47A",'1'&x"B47B",'1'&x"B47C",'1'&x"B47D",'1'&x"B47E",'1'&x"B47F",
+--'1'&x"B480",'1'&x"B481",'1'&x"B482",'1'&x"B483",'1'&x"B484",'1'&x"B485",'1'&x"B486",'1'&x"B487",'1'&x"B488",'1'&x"B489",'1'&x"B48A",'1'&x"B48B",'1'&x"B48C",'1'&x"B48D",'1'&x"B48E",'1'&x"B48F",
+--'1'&x"B490",'1'&x"B491",'1'&x"B492",'1'&x"B493",'1'&x"B494",'1'&x"B495",'1'&x"B496",'1'&x"B497",'1'&x"B498",'1'&x"B499",'1'&x"B49A",'1'&x"B49B",'1'&x"B49C",'1'&x"B49D",'1'&x"B49E",'1'&x"B49F",
+--'1'&x"B4A0",'1'&x"B4A1",'1'&x"B4A2",'1'&x"B4A3",'1'&x"B4A4",'1'&x"B4A5",'1'&x"B4A6",'1'&x"B4A7",'1'&x"B4A8",'1'&x"B4A9",'1'&x"B4AA",'1'&x"B4AB",'1'&x"B4AC",'1'&x"B4AD",'1'&x"B4AE",'1'&x"B4AF",
+--'1'&x"B4B0",'1'&x"B4B1",'1'&x"B4B2",'1'&x"B4B3",'1'&x"B4B4",'1'&x"B4B5",'1'&x"B4B6",'1'&x"B4B7",'1'&x"B4B8",'1'&x"B4B9",'1'&x"B4BA",'1'&x"B4BB",'1'&x"B4BC",'1'&x"B4BD",'1'&x"B4BE",'1'&x"B4BF",
+--'1'&x"B4C0",'1'&x"B4C1",'1'&x"B4C2",'1'&x"B4C3",'1'&x"B4C4",'1'&x"B4C5",'1'&x"B4C6",'1'&x"B4C7",'1'&x"B4C8",'1'&x"B4C9",'1'&x"B4CA",'1'&x"B4CB",'1'&x"B4CC",'1'&x"B4CD",'1'&x"B4CE",'1'&x"B4CF",
+--'1'&x"B4D0",'1'&x"B4D1",'1'&x"B4D2",'1'&x"B4D3",'1'&x"B4D4",'1'&x"B4D5",'1'&x"B4D6",'1'&x"B4D7",'1'&x"B4D8",'1'&x"B4D9",'1'&x"B4DA",'1'&x"B4DB",'1'&x"B4DC",'1'&x"B4DD",'1'&x"B4DE",'1'&x"B4DF",
+--'1'&x"B4E0",'1'&x"B4E1",'1'&x"B4E2",'1'&x"B4E3",'1'&x"B4E4",'1'&x"B4E5",'1'&x"B4E6",'1'&x"B4E7",'1'&x"B4E8",'1'&x"B4E9",'1'&x"B4EA",'1'&x"B4EB",'1'&x"B4EC",'1'&x"B4ED",'1'&x"B4EE",'1'&x"B4EF",
+--'1'&x"B4F0",'1'&x"B4F1",'1'&x"B4F2",'1'&x"B4F3",'1'&x"B4F4",'1'&x"B4F5",'1'&x"B4F6",'1'&x"B4F7",'1'&x"B4F8",'1'&x"B4F9",'1'&x"B4FA",'1'&x"B4FB",'1'&x"B4FC",'1'&x"B4FD",'1'&x"B4FE",'1'&x"B4FF",
+--'1'&x"B500",'1'&x"B501",'1'&x"B502",'1'&x"B503",'1'&x"B504",'1'&x"B505",'1'&x"B506",'1'&x"B507",'1'&x"B508",'1'&x"B509",'1'&x"B50A",'1'&x"B50B",'1'&x"B50C",'1'&x"B50D",'1'&x"B50E",'1'&x"B50F",
+--'1'&x"B510",'1'&x"B511",'1'&x"B512",'1'&x"B513",'1'&x"B514",'1'&x"B515",'1'&x"B516",'1'&x"B517",'1'&x"B518",'1'&x"B519",'1'&x"B51A",'1'&x"B51B",'1'&x"B51C",'1'&x"B51D",'1'&x"B51E",'1'&x"B51F",
+--'1'&x"B520",'1'&x"B521",'1'&x"B522",'1'&x"B523",'1'&x"B524",'1'&x"B525",'1'&x"B526",'1'&x"B527",'1'&x"B528",'1'&x"B529",'1'&x"B52A",'1'&x"B52B",'1'&x"B52C",'1'&x"B52D",'1'&x"B52E",'1'&x"B52F",
+--'1'&x"B530",'1'&x"B531",'1'&x"B532",'1'&x"B533",'1'&x"B534",'1'&x"B535",'1'&x"B536",'1'&x"B537",'1'&x"B538",'1'&x"B539",'1'&x"B53A",'1'&x"B53B",'1'&x"B53C",'1'&x"B53D",'1'&x"B53E",'1'&x"B53F",
+--'1'&x"B540",'1'&x"B541",'1'&x"B542",'1'&x"B543",'1'&x"B544",'1'&x"B545",'1'&x"B546",'1'&x"B547",'1'&x"B548",'1'&x"B549",'1'&x"B54A",'1'&x"B54B",'1'&x"B54C",'1'&x"B54D",'1'&x"B54E",'1'&x"B54F",
+--'1'&x"B550",'1'&x"B551",'1'&x"B552",'1'&x"B553",'1'&x"B554",'1'&x"B555",'1'&x"B556",'1'&x"B557",'1'&x"B558",'1'&x"B559",'1'&x"B55A",'1'&x"B55B",'1'&x"B55C",'1'&x"B55D",'1'&x"B55E",'1'&x"B55F",
+--'1'&x"B560",'1'&x"B561",'1'&x"B562",'1'&x"B563",'1'&x"B564",'1'&x"B565",'1'&x"B566",'1'&x"B567",'1'&x"B568",'1'&x"B569",'1'&x"B56A",'1'&x"B56B",'1'&x"B56C",'1'&x"B56D",'1'&x"B56E",'1'&x"B56F",
+--'1'&x"B570",'1'&x"B571",'1'&x"B572",'1'&x"B573",'1'&x"B574",'1'&x"B575",'1'&x"B576",'1'&x"B577",'1'&x"B578",'1'&x"B579",'1'&x"B57A",'1'&x"B57B",'1'&x"B57C",'1'&x"B57D",'1'&x"B57E",'1'&x"B57F",
+--'1'&x"B580",'1'&x"B581",'1'&x"B582",'1'&x"B583",'1'&x"B584",'1'&x"B585",'1'&x"B586",'1'&x"B587",'1'&x"B588",'1'&x"B589",'1'&x"B58A",'1'&x"B58B",'1'&x"B58C",'1'&x"B58D",'1'&x"B58E",'1'&x"B58F",
+--'1'&x"B590",'1'&x"B591",'1'&x"B592",'1'&x"B593",'1'&x"B594",'1'&x"B595",'1'&x"B596",'1'&x"B597",'1'&x"B598",'1'&x"B599",'1'&x"B59A",'1'&x"B59B",'1'&x"B59C",'1'&x"B59D",'1'&x"B59E",'1'&x"B59F",
+--'1'&x"B5A0",'1'&x"B5A1",'1'&x"B5A2",'1'&x"B5A3",'1'&x"B5A4",'1'&x"B5A5",'1'&x"B5A6",'1'&x"B5A7",'1'&x"B5A8",'1'&x"B5A9",'1'&x"B5AA",'1'&x"B5AB",'1'&x"B5AC",'1'&x"B5AD",'1'&x"B5AE",'1'&x"B5AF",
+--'1'&x"B5B0",'1'&x"B5B1",'1'&x"B5B2",'1'&x"B5B3",'1'&x"B5B4",'1'&x"B5B5",'1'&x"B5B6",'1'&x"B5B7",'1'&x"B5B8",'1'&x"B5B9",'1'&x"B5BA",'1'&x"B5BB",'1'&x"B5BC",'1'&x"B5BD",'1'&x"B5BE",'1'&x"B5BF",
+--'1'&x"B5C0",'1'&x"B5C1",'1'&x"B5C2",'1'&x"B5C3",'1'&x"B5C4",'1'&x"B5C5",'1'&x"B5C6",'1'&x"B5C7",'1'&x"B5C8",'1'&x"B5C9",'1'&x"B5CA",'1'&x"B5CB",'1'&x"B5CC",'1'&x"B5CD",'1'&x"B5CE",'1'&x"B5CF",
+--'1'&x"B5D0",'1'&x"B5D1",'1'&x"B5D2",'1'&x"B5D3",'1'&x"B5D4",'1'&x"B5D5",'1'&x"B5D6",'1'&x"B5D7",'1'&x"B5D8",'1'&x"B5D9",'1'&x"B5DA",'1'&x"B5DB",'1'&x"B5DC",'1'&x"B5DD",'1'&x"B5DE",'1'&x"B5DF",
+--'1'&x"B5E0",'1'&x"B5E1",'1'&x"B5E2",'1'&x"B5E3",'1'&x"B5E4",'1'&x"B5E5",'1'&x"B5E6",'1'&x"B5E7",'1'&x"B5E8",'1'&x"B5E9",'1'&x"B5EA",'1'&x"B5EB",'1'&x"B5EC",'1'&x"B5ED",'1'&x"B5EE",'1'&x"B5EF",
+--'1'&x"B5F0",'1'&x"B5F1",'1'&x"B5F2",'1'&x"B5F3",'1'&x"B5F4",'1'&x"B5F5",'1'&x"B5F6",'1'&x"B5F7",'1'&x"B5F8",'1'&x"B5F9",'1'&x"B5FA",'1'&x"B5FB",'1'&x"B5FC",'1'&x"B5FD",'1'&x"B5FE",'1'&x"B5FF",
+--'1'&x"B600",'1'&x"B601",'1'&x"B602",'1'&x"B603",'1'&x"B604",'1'&x"B605",'1'&x"B606",'1'&x"B607",'1'&x"B608",'1'&x"B609",'1'&x"B60A",'1'&x"B60B",'1'&x"B60C",'1'&x"B60D",'1'&x"B60E",'1'&x"B60F",
+--'1'&x"B610",'1'&x"B611",'1'&x"B612",'1'&x"B613",'1'&x"B614",'1'&x"B615",'1'&x"B616",'1'&x"B617",'1'&x"B618",'1'&x"B619",'1'&x"B61A",'1'&x"B61B",'1'&x"B61C",'1'&x"B61D",'1'&x"B61E",'1'&x"B61F",
+--'1'&x"B620",'1'&x"B621",'1'&x"B622",'1'&x"B623",'1'&x"B624",'1'&x"B625",'1'&x"B626",'1'&x"B627",'1'&x"B628",'1'&x"B629",'1'&x"B62A",'1'&x"B62B",'1'&x"B62C",'1'&x"B62D",'1'&x"B62E",'1'&x"B62F",
+--'1'&x"B630",'1'&x"B631",'1'&x"B632",'1'&x"B633",'1'&x"B634",'1'&x"B635",'1'&x"B636",'1'&x"B637",'1'&x"B638",'1'&x"B639",'1'&x"B63A",'1'&x"B63B",'1'&x"B63C",'1'&x"B63D",'1'&x"B63E",'1'&x"B63F",
+--'1'&x"B640",'1'&x"B641",'1'&x"B642",'1'&x"B643",'1'&x"B644",'1'&x"B645",'1'&x"B646",'1'&x"B647",'1'&x"B648",'1'&x"B649",'1'&x"B64A",'1'&x"B64B",'1'&x"B64C",'1'&x"B64D",'1'&x"B64E",'1'&x"B64F",
+--'1'&x"B650",'1'&x"B651",'1'&x"B652",'1'&x"B653",'1'&x"B654",'1'&x"B655",'1'&x"B656",'1'&x"B657",'1'&x"B658",'1'&x"B659",'1'&x"B65A",'1'&x"B65B",'1'&x"B65C",'1'&x"B65D",'1'&x"B65E",'1'&x"B65F",
+--'1'&x"B660",'1'&x"B661",'1'&x"B662",'1'&x"B663",'1'&x"B664",'1'&x"B665",'1'&x"B666",'1'&x"B667",'1'&x"B668",'1'&x"B669",'1'&x"B66A",'1'&x"B66B",'1'&x"B66C",'1'&x"B66D",'1'&x"B66E",'1'&x"B66F",
+--'1'&x"B670",'1'&x"B671",'1'&x"B672",'1'&x"B673",'1'&x"B674",'1'&x"B675",'1'&x"B676",'1'&x"B677",'1'&x"B678",'1'&x"B679",'1'&x"B67A",'1'&x"B67B",'1'&x"B67C",'1'&x"B67D",'1'&x"B67E",'1'&x"B67F",
+--'1'&x"B680",'1'&x"B681",'1'&x"B682",'1'&x"B683",'1'&x"B684",'1'&x"B685",'1'&x"B686",'1'&x"B687",'1'&x"B688",'1'&x"B689",'1'&x"B68A",'1'&x"B68B",'1'&x"B68C",'1'&x"B68D",'1'&x"B68E",'1'&x"B68F",
+--'1'&x"B690",'1'&x"B691",'1'&x"B692",'1'&x"B693",'1'&x"B694",'1'&x"B695",'1'&x"B696",'1'&x"B697",'1'&x"B698",'1'&x"B699",'1'&x"B69A",'1'&x"B69B",'1'&x"B69C",'1'&x"B69D",'1'&x"B69E",'1'&x"B69F",
+--'1'&x"B6A0",'1'&x"B6A1",'1'&x"B6A2",'1'&x"B6A3",'1'&x"B6A4",'1'&x"B6A5",'1'&x"B6A6",'1'&x"B6A7",'1'&x"B6A8",'1'&x"B6A9",'1'&x"B6AA",'1'&x"B6AB",'1'&x"B6AC",'1'&x"B6AD",'1'&x"B6AE",'1'&x"B6AF",
+--'1'&x"B6B0",'1'&x"B6B1",'1'&x"B6B2",'1'&x"B6B3",'1'&x"B6B4",'1'&x"B6B5",'1'&x"B6B6",'1'&x"B6B7",'1'&x"B6B8",'1'&x"B6B9",'1'&x"B6BA",'1'&x"B6BB",'1'&x"B6BC",'1'&x"B6BD",'1'&x"B6BE",'1'&x"B6BF",
+--'1'&x"B6C0",'1'&x"B6C1",'1'&x"B6C2",'1'&x"B6C3",'1'&x"B6C4",'1'&x"B6C5",'1'&x"B6C6",'1'&x"B6C7",'1'&x"B6C8",'1'&x"B6C9",'1'&x"B6CA",'1'&x"B6CB",'1'&x"B6CC",'1'&x"B6CD",'1'&x"B6CE",'1'&x"B6CF",
+--'1'&x"B6D0",'1'&x"B6D1",'1'&x"B6D2",'1'&x"B6D3",'1'&x"B6D4",'1'&x"B6D5",'1'&x"B6D6",'1'&x"B6D7",'1'&x"B6D8",'1'&x"B6D9",'1'&x"B6DA",'1'&x"B6DB",'1'&x"B6DC",'1'&x"B6DD",'1'&x"B6DE",'1'&x"B6DF",
+--'1'&x"B6E0",'1'&x"B6E1",'1'&x"B6E2",'1'&x"B6E3",'1'&x"B6E4",'1'&x"B6E5",'1'&x"B6E6",'1'&x"B6E7",'1'&x"B6E8",'1'&x"B6E9",'1'&x"B6EA",'1'&x"B6EB",'1'&x"B6EC",'1'&x"B6ED",'1'&x"B6EE",'1'&x"B6EF",
+--'1'&x"B6F0",'1'&x"B6F1",'1'&x"B6F2",'1'&x"B6F3",'1'&x"B6F4",'1'&x"B6F5",'1'&x"B6F6",'1'&x"B6F7",'1'&x"B6F8",'1'&x"B6F9",'1'&x"B6FA",'1'&x"B6FB",'1'&x"B6FC",'1'&x"B6FD",'1'&x"B6FE",'1'&x"B6FF",
+--'1'&x"B700",'1'&x"B701",'1'&x"B702",'1'&x"B703",'1'&x"B704",'1'&x"B705",'1'&x"B706",'1'&x"B707",'1'&x"B708",'1'&x"B709",'1'&x"B70A",'1'&x"B70B",'1'&x"B70C",'1'&x"B70D",'1'&x"B70E",'1'&x"B70F",
+--'1'&x"B710",'1'&x"B711",'1'&x"B712",'1'&x"B713",'1'&x"B714",'1'&x"B715",'1'&x"B716",'1'&x"B717",'1'&x"B718",'1'&x"B719",'1'&x"B71A",'1'&x"B71B",'1'&x"B71C",'1'&x"B71D",'1'&x"B71E",'1'&x"B71F",
+--'1'&x"B720",'1'&x"B721",'1'&x"B722",'1'&x"B723",'1'&x"B724",'1'&x"B725",'1'&x"B726",'1'&x"B727",'1'&x"B728",'1'&x"B729",'1'&x"B72A",'1'&x"B72B",'1'&x"B72C",'1'&x"B72D",'1'&x"B72E",'1'&x"B72F",
+--'1'&x"B730",'1'&x"B731",'1'&x"B732",'1'&x"B733",'1'&x"B734",'1'&x"B735",'1'&x"B736",'1'&x"B737",'1'&x"B738",'1'&x"B739",'1'&x"B73A",'1'&x"B73B",'1'&x"B73C",'1'&x"B73D",'1'&x"B73E",'1'&x"B73F",
+--'1'&x"B740",'1'&x"B741",'1'&x"B742",'1'&x"B743",'1'&x"B744",'1'&x"B745",'1'&x"B746",'1'&x"B747",'1'&x"B748",'1'&x"B749",'1'&x"B74A",'1'&x"B74B",'1'&x"B74C",'1'&x"B74D",'1'&x"B74E",'1'&x"B74F",
+--'1'&x"B750",'1'&x"B751",'1'&x"B752",'1'&x"B753",'1'&x"B754",'1'&x"B755",'1'&x"B756",'1'&x"B757",'1'&x"B758",'1'&x"B759",'1'&x"B75A",'1'&x"B75B",'1'&x"B75C",'1'&x"B75D",'1'&x"B75E",'1'&x"B75F",
+--'1'&x"B760",'1'&x"B761",'1'&x"B762",'1'&x"B763",'1'&x"B764",'1'&x"B765",'1'&x"B766",'1'&x"B767",'1'&x"B768",'1'&x"B769",'1'&x"B76A",'1'&x"B76B",'1'&x"B76C",'1'&x"B76D",'1'&x"B76E",'1'&x"B76F",
+--'1'&x"B770",'1'&x"B771",'1'&x"B772",'1'&x"B773",'1'&x"B774",'1'&x"B775",'1'&x"B776",'1'&x"B777",'1'&x"B778",'1'&x"B779",'1'&x"B77A",'1'&x"B77B",'1'&x"B77C",'1'&x"B77D",'1'&x"B77E",'1'&x"B77F",
+--'1'&x"B780",'1'&x"B781",'1'&x"B782",'1'&x"B783",'1'&x"B784",'1'&x"B785",'1'&x"B786",'1'&x"B787",'1'&x"B788",'1'&x"B789",'1'&x"B78A",'1'&x"B78B",'1'&x"B78C",'1'&x"B78D",'1'&x"B78E",'1'&x"B78F",
+--'1'&x"B790",'1'&x"B791",'1'&x"B792",'1'&x"B793",'1'&x"B794",'1'&x"B795",'1'&x"B796",'1'&x"B797",'1'&x"B798",'1'&x"B799",'1'&x"B79A",'1'&x"B79B",'1'&x"B79C",'1'&x"B79D",'1'&x"B79E",'1'&x"B79F",
+--'1'&x"B7A0",'1'&x"B7A1",'1'&x"B7A2",'1'&x"B7A3",'1'&x"B7A4",'1'&x"B7A5",'1'&x"B7A6",'1'&x"B7A7",'1'&x"B7A8",'1'&x"B7A9",'1'&x"B7AA",'1'&x"B7AB",'1'&x"B7AC",'1'&x"B7AD",'1'&x"B7AE",'1'&x"B7AF",
+--'1'&x"B7B0",'1'&x"B7B1",'1'&x"B7B2",'1'&x"B7B3",'1'&x"B7B4",'1'&x"B7B5",'1'&x"B7B6",'1'&x"B7B7",'1'&x"B7B8",'1'&x"B7B9",'1'&x"B7BA",'1'&x"B7BB",'1'&x"B7BC",'1'&x"B7BD",'1'&x"B7BE",'1'&x"B7BF",
+--'1'&x"B7C0",'1'&x"B7C1",'1'&x"B7C2",'1'&x"B7C3",'1'&x"B7C4",'1'&x"B7C5",'1'&x"B7C6",'1'&x"B7C7",'1'&x"B7C8",'1'&x"B7C9",'1'&x"B7CA",'1'&x"B7CB",'1'&x"B7CC",'1'&x"B7CD",'1'&x"B7CE",'1'&x"B7CF",
+--'1'&x"B7D0",'1'&x"B7D1",'1'&x"B7D2",'1'&x"B7D3",'1'&x"B7D4",'1'&x"B7D5",'1'&x"B7D6",'1'&x"B7D7",'1'&x"B7D8",'1'&x"B7D9",'1'&x"B7DA",'1'&x"B7DB",'1'&x"B7DC",'1'&x"B7DD",'1'&x"B7DE",'1'&x"B7DF",
+--'1'&x"B7E0",'1'&x"B7E1",'1'&x"B7E2",'1'&x"B7E3",'1'&x"B7E4",'1'&x"B7E5",'1'&x"B7E6",'1'&x"B7E7",'1'&x"B7E8",'1'&x"B7E9",'1'&x"B7EA",'1'&x"B7EB",'1'&x"B7EC",'1'&x"B7ED",'1'&x"B7EE",'1'&x"B7EF",
+--'1'&x"B7F0",'1'&x"B7F1",'1'&x"B7F2",'1'&x"B7F3",'1'&x"B7F4",'1'&x"B7F5",'1'&x"B7F6",'1'&x"B7F7",'1'&x"B7F8",'1'&x"B7F9",'1'&x"B7FA",'1'&x"B7FB",'1'&x"B7FC",'1'&x"B7FD",'1'&x"B7FE",'1'&x"B7FF",
+--'1'&x"B800",'1'&x"B801",'1'&x"B802",'1'&x"B803",'1'&x"B804",'1'&x"B805",'1'&x"B806",'1'&x"B807",'1'&x"B808",'1'&x"B809",'1'&x"B80A",'1'&x"B80B",'1'&x"B80C",'1'&x"B80D",'1'&x"B80E",'1'&x"B80F",
+--'1'&x"B810",'1'&x"B811",'1'&x"B812",'1'&x"B813",'1'&x"B814",'1'&x"B815",'1'&x"B816",'1'&x"B817",'1'&x"B818",'1'&x"B819",'1'&x"B81A",'1'&x"B81B",'1'&x"B81C",'1'&x"B81D",'1'&x"B81E",'1'&x"B81F",
+--'1'&x"B820",'1'&x"B821",'1'&x"B822",'1'&x"B823",'1'&x"B824",'1'&x"B825",'1'&x"B826",'1'&x"B827",'1'&x"B828",'1'&x"B829",'1'&x"B82A",'1'&x"B82B",'1'&x"B82C",'1'&x"B82D",'1'&x"B82E",'1'&x"B82F",
+--'1'&x"B830",'1'&x"B831",'1'&x"B832",'1'&x"B833",'1'&x"B834",'1'&x"B835",'1'&x"B836",'1'&x"B837",'1'&x"B838",'1'&x"B839",'1'&x"B83A",'1'&x"B83B",'1'&x"B83C",'1'&x"B83D",'1'&x"B83E",'1'&x"B83F",
+--'1'&x"B840",'1'&x"B841",'1'&x"B842",'1'&x"B843",'1'&x"B844",'1'&x"B845",'1'&x"B846",'1'&x"B847",'1'&x"B848",'1'&x"B849",'1'&x"B84A",'1'&x"B84B",'1'&x"B84C",'1'&x"B84D",'1'&x"B84E",'1'&x"B84F",
+--'1'&x"B850",'1'&x"B851",'1'&x"B852",'1'&x"B853",'1'&x"B854",'1'&x"B855",'1'&x"B856",'1'&x"B857",'1'&x"B858",'1'&x"B859",'1'&x"B85A",'1'&x"B85B",'1'&x"B85C",'1'&x"B85D",'1'&x"B85E",'1'&x"B85F",
+--'1'&x"B860",'1'&x"B861",'1'&x"B862",'1'&x"B863",'1'&x"B864",'1'&x"B865",'1'&x"B866",'1'&x"B867",'1'&x"B868",'1'&x"B869",'1'&x"B86A",'1'&x"B86B",'1'&x"B86C",'1'&x"B86D",'1'&x"B86E",'1'&x"B86F",
+--'1'&x"B870",'1'&x"B871",'1'&x"B872",'1'&x"B873",'1'&x"B874",'1'&x"B875",'1'&x"B876",'1'&x"B877",'1'&x"B878",'1'&x"B879",'1'&x"B87A",'1'&x"B87B",'1'&x"B87C",'1'&x"B87D",'1'&x"B87E",'1'&x"B87F",
+--'1'&x"B880",'1'&x"B881",'1'&x"B882",'1'&x"B883",'1'&x"B884",'1'&x"B885",'1'&x"B886",'1'&x"B887",'1'&x"B888",'1'&x"B889",'1'&x"B88A",'1'&x"B88B",'1'&x"B88C",'1'&x"B88D",'1'&x"B88E",'1'&x"B88F",
+--'1'&x"B890",'1'&x"B891",'1'&x"B892",'1'&x"B893",'1'&x"B894",'1'&x"B895",'1'&x"B896",'1'&x"B897",'1'&x"B898",'1'&x"B899",'1'&x"B89A",'1'&x"B89B",'1'&x"B89C",'1'&x"B89D",'1'&x"B89E",'1'&x"B89F",
+--'1'&x"B8A0",'1'&x"B8A1",'1'&x"B8A2",'1'&x"B8A3",'1'&x"B8A4",'1'&x"B8A5",'1'&x"B8A6",'1'&x"B8A7",'1'&x"B8A8",'1'&x"B8A9",'1'&x"B8AA",'1'&x"B8AB",'1'&x"B8AC",'1'&x"B8AD",'1'&x"B8AE",'1'&x"B8AF",
+--'1'&x"B8B0",'1'&x"B8B1",'1'&x"B8B2",'1'&x"B8B3",'1'&x"B8B4",'1'&x"B8B5",'1'&x"B8B6",'1'&x"B8B7",'1'&x"B8B8",'1'&x"B8B9",'1'&x"B8BA",'1'&x"B8BB",'1'&x"B8BC",'1'&x"B8BD",'1'&x"B8BE",'1'&x"B8BF",
+--'1'&x"B8C0",'1'&x"B8C1",'1'&x"B8C2",'1'&x"B8C3",'1'&x"B8C4",'1'&x"B8C5",'1'&x"B8C6",'1'&x"B8C7",'1'&x"B8C8",'1'&x"B8C9",'1'&x"B8CA",'1'&x"B8CB",'1'&x"B8CC",'1'&x"B8CD",'1'&x"B8CE",'1'&x"B8CF",
+--'1'&x"B8D0",'1'&x"B8D1",'1'&x"B8D2",'1'&x"B8D3",'1'&x"B8D4",'1'&x"B8D5",'1'&x"B8D6",'1'&x"B8D7",'1'&x"B8D8",'1'&x"B8D9",'1'&x"B8DA",'1'&x"B8DB",'1'&x"B8DC",'1'&x"B8DD",'1'&x"B8DE",'1'&x"B8DF",
+--'1'&x"B8E0",'1'&x"B8E1",'1'&x"B8E2",'1'&x"B8E3",'1'&x"B8E4",'1'&x"B8E5",'1'&x"B8E6",'1'&x"B8E7",'1'&x"B8E8",'1'&x"B8E9",'1'&x"B8EA",'1'&x"B8EB",'1'&x"B8EC",'1'&x"B8ED",'1'&x"B8EE",'1'&x"B8EF",
+--'1'&x"B8F0",'1'&x"B8F1",'1'&x"B8F2",'1'&x"B8F3",'1'&x"B8F4",'1'&x"B8F5",'1'&x"B8F6",'1'&x"B8F7",'1'&x"B8F8",'1'&x"B8F9",'1'&x"B8FA",'1'&x"B8FB",'1'&x"B8FC",'1'&x"B8FD",'1'&x"B8FE",'1'&x"B8FF",
+--'1'&x"B900",'1'&x"B901",'1'&x"B902",'1'&x"B903",'1'&x"B904",'1'&x"B905",'1'&x"B906",'1'&x"B907",'1'&x"B908",'1'&x"B909",'1'&x"B90A",'1'&x"B90B",'1'&x"B90C",'1'&x"B90D",'1'&x"B90E",'1'&x"B90F",
+--'1'&x"B910",'1'&x"B911",'1'&x"B912",'1'&x"B913",'1'&x"B914",'1'&x"B915",'1'&x"B916",'1'&x"B917",'1'&x"B918",'1'&x"B919",'1'&x"B91A",'1'&x"B91B",'1'&x"B91C",'1'&x"B91D",'1'&x"B91E",'1'&x"B91F",
+--'1'&x"B920",'1'&x"B921",'1'&x"B922",'1'&x"B923",'1'&x"B924",'1'&x"B925",'1'&x"B926",'1'&x"B927",'1'&x"B928",'1'&x"B929",'1'&x"B92A",'1'&x"B92B",'1'&x"B92C",'1'&x"B92D",'1'&x"B92E",'1'&x"B92F",
+--'1'&x"B930",'1'&x"B931",'1'&x"B932",'1'&x"B933",'1'&x"B934",'1'&x"B935",'1'&x"B936",'1'&x"B937",'1'&x"B938",'1'&x"B939",'1'&x"B93A",'1'&x"B93B",'1'&x"B93C",'1'&x"B93D",'1'&x"B93E",'1'&x"B93F",
+--'1'&x"B940",'1'&x"B941",'1'&x"B942",'1'&x"B943",'1'&x"B944",'1'&x"B945",'1'&x"B946",'1'&x"B947",'1'&x"B948",'1'&x"B949",'1'&x"B94A",'1'&x"B94B",'1'&x"B94C",'1'&x"B94D",'1'&x"B94E",'1'&x"B94F",
+--'1'&x"B950",'1'&x"B951",'1'&x"B952",'1'&x"B953",'1'&x"B954",'1'&x"B955",'1'&x"B956",'1'&x"B957",'1'&x"B958",'1'&x"B959",'1'&x"B95A",'1'&x"B95B",'1'&x"B95C",'1'&x"B95D",'1'&x"B95E",'1'&x"B95F",
+--'1'&x"B960",'1'&x"B961",'1'&x"B962",'1'&x"B963",'1'&x"B964",'1'&x"B965",'1'&x"B966",'1'&x"B967",'1'&x"B968",'1'&x"B969",'1'&x"B96A",'1'&x"B96B",'1'&x"B96C",'1'&x"B96D",'1'&x"B96E",'1'&x"B96F",
+--'1'&x"B970",'1'&x"B971",'1'&x"B972",'1'&x"B973",'1'&x"B974",'1'&x"B975",'1'&x"B976",'1'&x"B977",'1'&x"B978",'1'&x"B979",'1'&x"B97A",'1'&x"B97B",'1'&x"B97C",'1'&x"B97D",'1'&x"B97E",'1'&x"B97F",
+--'1'&x"B980",'1'&x"B981",'1'&x"B982",'1'&x"B983",'1'&x"B984",'1'&x"B985",'1'&x"B986",'1'&x"B987",'1'&x"B988",'1'&x"B989",'1'&x"B98A",'1'&x"B98B",'1'&x"B98C",'1'&x"B98D",'1'&x"B98E",'1'&x"B98F",
+--'1'&x"B990",'1'&x"B991",'1'&x"B992",'1'&x"B993",'1'&x"B994",'1'&x"B995",'1'&x"B996",'1'&x"B997",'1'&x"B998",'1'&x"B999",'1'&x"B99A",'1'&x"B99B",'1'&x"B99C",'1'&x"B99D",'1'&x"B99E",'1'&x"B99F",
+--'1'&x"B9A0",'1'&x"B9A1",'1'&x"B9A2",'1'&x"B9A3",'1'&x"B9A4",'1'&x"B9A5",'1'&x"B9A6",'1'&x"B9A7",'1'&x"B9A8",'1'&x"B9A9",'1'&x"B9AA",'1'&x"B9AB",'1'&x"B9AC",'1'&x"B9AD",'1'&x"B9AE",'1'&x"B9AF",
+--'1'&x"B9B0",'1'&x"B9B1",'1'&x"B9B2",'1'&x"B9B3",'1'&x"B9B4",'1'&x"B9B5",'1'&x"B9B6",'1'&x"B9B7",'1'&x"B9B8",'1'&x"B9B9",'1'&x"B9BA",'1'&x"B9BB",'1'&x"B9BC",'1'&x"B9BD",'1'&x"B9BE",'1'&x"B9BF",
+--'1'&x"B9C0",'1'&x"B9C1",'1'&x"B9C2",'1'&x"B9C3",'1'&x"B9C4",'1'&x"B9C5",'1'&x"B9C6",'1'&x"B9C7",'1'&x"B9C8",'1'&x"B9C9",'1'&x"B9CA",'1'&x"B9CB",'1'&x"B9CC",'1'&x"B9CD",'1'&x"B9CE",'1'&x"B9CF",
+--'1'&x"B9D0",'1'&x"B9D1",'1'&x"B9D2",'1'&x"B9D3",'1'&x"B9D4",'1'&x"B9D5",'1'&x"B9D6",'1'&x"B9D7",'1'&x"B9D8",'1'&x"B9D9",'1'&x"B9DA",'1'&x"B9DB",'1'&x"B9DC",'1'&x"B9DD",'1'&x"B9DE",'1'&x"B9DF",
+--'1'&x"B9E0",'1'&x"B9E1",'1'&x"B9E2",'1'&x"B9E3",'1'&x"B9E4",'1'&x"B9E5",'1'&x"B9E6",'1'&x"B9E7",'1'&x"B9E8",'1'&x"B9E9",'1'&x"B9EA",'1'&x"B9EB",'1'&x"B9EC",'1'&x"B9ED",'1'&x"B9EE",'1'&x"B9EF",
+--'1'&x"B9F0",'1'&x"B9F1",'1'&x"B9F2",'1'&x"B9F3",'1'&x"B9F4",'1'&x"B9F5",'1'&x"B9F6",'1'&x"B9F7",'1'&x"B9F8",'1'&x"B9F9",'1'&x"B9FA",'1'&x"B9FB",'1'&x"B9FC",'1'&x"B9FD",'1'&x"B9FE",'1'&x"B9FF",
+--'1'&x"BA00",'1'&x"BA01",'1'&x"BA02",'1'&x"BA03",'1'&x"BA04",'1'&x"BA05",'1'&x"BA06",'1'&x"BA07",'1'&x"BA08",'1'&x"BA09",'1'&x"BA0A",'1'&x"BA0B",'1'&x"BA0C",'1'&x"BA0D",'1'&x"BA0E",'1'&x"BA0F",
+--'1'&x"BA10",'1'&x"BA11",'1'&x"BA12",'1'&x"BA13",'1'&x"BA14",'1'&x"BA15",'1'&x"BA16",'1'&x"BA17",'1'&x"BA18",'1'&x"BA19",'1'&x"BA1A",'1'&x"BA1B",'1'&x"BA1C",'1'&x"BA1D",'1'&x"BA1E",'1'&x"BA1F",
+--'1'&x"BA20",'1'&x"BA21",'1'&x"BA22",'1'&x"BA23",'1'&x"BA24",'1'&x"BA25",'1'&x"BA26",'1'&x"BA27",'1'&x"BA28",'1'&x"BA29",'1'&x"BA2A",'1'&x"BA2B",'1'&x"BA2C",'1'&x"BA2D",'1'&x"BA2E",'1'&x"BA2F",
+--'1'&x"BA30",'1'&x"BA31",'1'&x"BA32",'1'&x"BA33",'1'&x"BA34",'1'&x"BA35",'1'&x"BA36",'1'&x"BA37",'1'&x"BA38",'1'&x"BA39",'1'&x"BA3A",'1'&x"BA3B",'1'&x"BA3C",'1'&x"BA3D",'1'&x"BA3E",'1'&x"BA3F",
+--'1'&x"BA40",'1'&x"BA41",'1'&x"BA42",'1'&x"BA43",'1'&x"BA44",'1'&x"BA45",'1'&x"BA46",'1'&x"BA47",'1'&x"BA48",'1'&x"BA49",'1'&x"BA4A",'1'&x"BA4B",'1'&x"BA4C",'1'&x"BA4D",'1'&x"BA4E",'1'&x"BA4F",
+--'1'&x"BA50",'1'&x"BA51",'1'&x"BA52",'1'&x"BA53",'1'&x"BA54",'1'&x"BA55",'1'&x"BA56",'1'&x"BA57",'1'&x"BA58",'1'&x"BA59",'1'&x"BA5A",'1'&x"BA5B",'1'&x"BA5C",'1'&x"BA5D",'1'&x"BA5E",'1'&x"BA5F",
+--'1'&x"BA60",'1'&x"BA61",'1'&x"BA62",'1'&x"BA63",'1'&x"BA64",'1'&x"BA65",'1'&x"BA66",'1'&x"BA67",'1'&x"BA68",'1'&x"BA69",'1'&x"BA6A",'1'&x"BA6B",'1'&x"BA6C",'1'&x"BA6D",'1'&x"BA6E",'1'&x"BA6F",
+--'1'&x"BA70",'1'&x"BA71",'1'&x"BA72",'1'&x"BA73",'1'&x"BA74",'1'&x"BA75",'1'&x"BA76",'1'&x"BA77",'1'&x"BA78",'1'&x"BA79",'1'&x"BA7A",'1'&x"BA7B",'1'&x"BA7C",'1'&x"BA7D",'1'&x"BA7E",'1'&x"BA7F",
+--'1'&x"BA80",'1'&x"BA81",'1'&x"BA82",'1'&x"BA83",'1'&x"BA84",'1'&x"BA85",'1'&x"BA86",'1'&x"BA87",'1'&x"BA88",'1'&x"BA89",'1'&x"BA8A",'1'&x"BA8B",'1'&x"BA8C",'1'&x"BA8D",'1'&x"BA8E",'1'&x"BA8F",
+--'1'&x"BA90",'1'&x"BA91",'1'&x"BA92",'1'&x"BA93",'1'&x"BA94",'1'&x"BA95",'1'&x"BA96",'1'&x"BA97",'1'&x"BA98",'1'&x"BA99",'1'&x"BA9A",'1'&x"BA9B",'1'&x"BA9C",'1'&x"BA9D",'1'&x"BA9E",'1'&x"BA9F",
+--'1'&x"BAA0",'1'&x"BAA1",'1'&x"BAA2",'1'&x"BAA3",'1'&x"BAA4",'1'&x"BAA5",'1'&x"BAA6",'1'&x"BAA7",'1'&x"BAA8",'1'&x"BAA9",'1'&x"BAAA",'1'&x"BAAB",'1'&x"BAAC",'1'&x"BAAD",'1'&x"BAAE",'1'&x"BAAF",
+--'1'&x"BAB0",'1'&x"BAB1",'1'&x"BAB2",'1'&x"BAB3",'1'&x"BAB4",'1'&x"BAB5",'1'&x"BAB6",'1'&x"BAB7",'1'&x"BAB8",'1'&x"BAB9",'1'&x"BABA",'1'&x"BABB",'1'&x"BABC",'1'&x"BABD",'1'&x"BABE",'1'&x"BABF",
+--'1'&x"BAC0",'1'&x"BAC1",'1'&x"BAC2",'1'&x"BAC3",'1'&x"BAC4",'1'&x"BAC5",'1'&x"BAC6",'1'&x"BAC7",'1'&x"BAC8",'1'&x"BAC9",'1'&x"BACA",'1'&x"BACB",'1'&x"BACC",'1'&x"BACD",'1'&x"BACE",'1'&x"BACF",
+--'1'&x"BAD0",'1'&x"BAD1",'1'&x"BAD2",'1'&x"BAD3",'1'&x"BAD4",'1'&x"BAD5",'1'&x"BAD6",'1'&x"BAD7",'1'&x"BAD8",'1'&x"BAD9",'1'&x"BADA",'1'&x"BADB",'1'&x"BADC",'1'&x"BADD",'1'&x"BADE",'1'&x"BADF",
+--'1'&x"BAE0",'1'&x"BAE1",'1'&x"BAE2",'1'&x"BAE3",'1'&x"BAE4",'1'&x"BAE5",'1'&x"BAE6",'1'&x"BAE7",'1'&x"BAE8",'1'&x"BAE9",'1'&x"BAEA",'1'&x"BAEB",'1'&x"BAEC",'1'&x"BAED",'1'&x"BAEE",'1'&x"BAEF",
+--'1'&x"BAF0",'1'&x"BAF1",'1'&x"BAF2",'1'&x"BAF3",'1'&x"BAF4",'1'&x"BAF5",'1'&x"BAF6",'1'&x"BAF7",'1'&x"BAF8",'1'&x"BAF9",'1'&x"BAFA",'1'&x"BAFB",'1'&x"BAFC",'1'&x"BAFD",'1'&x"BAFE",'1'&x"BAFF",
+--'1'&x"BB00",'1'&x"BB01",'1'&x"BB02",'1'&x"BB03",'1'&x"BB04",'1'&x"BB05",'1'&x"BB06",'1'&x"BB07",'1'&x"BB08",'1'&x"BB09",'1'&x"BB0A",'1'&x"BB0B",'1'&x"BB0C",'1'&x"BB0D",'1'&x"BB0E",'1'&x"BB0F",
+--'1'&x"BB10",'1'&x"BB11",'1'&x"BB12",'1'&x"BB13",'1'&x"BB14",'1'&x"BB15",'1'&x"BB16",'1'&x"BB17",'1'&x"BB18",'1'&x"BB19",'1'&x"BB1A",'1'&x"BB1B",'1'&x"BB1C",'1'&x"BB1D",'1'&x"BB1E",'1'&x"BB1F",
+--'1'&x"BB20",'1'&x"BB21",'1'&x"BB22",'1'&x"BB23",'1'&x"BB24",'1'&x"BB25",'1'&x"BB26",'1'&x"BB27",'1'&x"BB28",'1'&x"BB29",'1'&x"BB2A",'1'&x"BB2B",'1'&x"BB2C",'1'&x"BB2D",'1'&x"BB2E",'1'&x"BB2F",
+--'1'&x"BB30",'1'&x"BB31",'1'&x"BB32",'1'&x"BB33",'1'&x"BB34",'1'&x"BB35",'1'&x"BB36",'1'&x"BB37",'1'&x"BB38",'1'&x"BB39",'1'&x"BB3A",'1'&x"BB3B",'1'&x"BB3C",'1'&x"BB3D",'1'&x"BB3E",'1'&x"BB3F",
+--'1'&x"BB40",'1'&x"BB41",'1'&x"BB42",'1'&x"BB43",'1'&x"BB44",'1'&x"BB45",'1'&x"BB46",'1'&x"BB47",'1'&x"BB48",'1'&x"BB49",'1'&x"BB4A",'1'&x"BB4B",'1'&x"BB4C",'1'&x"BB4D",'1'&x"BB4E",'1'&x"BB4F",
+--'1'&x"BB50",'1'&x"BB51",'1'&x"BB52",'1'&x"BB53",'1'&x"BB54",'1'&x"BB55",'1'&x"BB56",'1'&x"BB57",'1'&x"BB58",'1'&x"BB59",'1'&x"BB5A",'1'&x"BB5B",'1'&x"BB5C",'1'&x"BB5D",'1'&x"BB5E",'1'&x"BB5F",
+--'1'&x"BB60",'1'&x"BB61",'1'&x"BB62",'1'&x"BB63",'1'&x"BB64",'1'&x"BB65",'1'&x"BB66",'1'&x"BB67",'1'&x"BB68",'1'&x"BB69",'1'&x"BB6A",'1'&x"BB6B",'1'&x"BB6C",'1'&x"BB6D",'1'&x"BB6E",'1'&x"BB6F",
+--'1'&x"BB70",'1'&x"BB71",'1'&x"BB72",'1'&x"BB73",'1'&x"BB74",'1'&x"BB75",'1'&x"BB76",'1'&x"BB77",'1'&x"BB78",'1'&x"BB79",'1'&x"BB7A",'1'&x"BB7B",'1'&x"BB7C",'1'&x"BB7D",'1'&x"BB7E",'1'&x"BB7F",
+--'1'&x"BB80",'1'&x"BB81",'1'&x"BB82",'1'&x"BB83",'1'&x"BB84",'1'&x"BB85",'1'&x"BB86",'1'&x"BB87",'1'&x"BB88",'1'&x"BB89",'1'&x"BB8A",'1'&x"BB8B",'1'&x"BB8C",'1'&x"BB8D",'1'&x"BB8E",'1'&x"BB8F",
+--'1'&x"BB90",'1'&x"BB91",'1'&x"BB92",'1'&x"BB93",'1'&x"BB94",'1'&x"BB95",'1'&x"BB96",'1'&x"BB97",'1'&x"BB98",'1'&x"BB99",'1'&x"BB9A",'1'&x"BB9B",'1'&x"BB9C",'1'&x"BB9D",'1'&x"BB9E",'1'&x"BB9F",
+--'1'&x"BBA0",'1'&x"BBA1",'1'&x"BBA2",'1'&x"BBA3",'1'&x"BBA4",'1'&x"BBA5",'1'&x"BBA6",'1'&x"BBA7",'1'&x"BBA8",'1'&x"BBA9",'1'&x"BBAA",'1'&x"BBAB",'1'&x"BBAC",'1'&x"BBAD",'1'&x"BBAE",'1'&x"BBAF",
+--'1'&x"BBB0",'1'&x"BBB1",'1'&x"BBB2",'1'&x"BBB3",'1'&x"BBB4",'1'&x"BBB5",'1'&x"BBB6",'1'&x"BBB7",'1'&x"BBB8",'1'&x"BBB9",'1'&x"BBBA",'1'&x"BBBB",'1'&x"BBBC",'1'&x"BBBD",'1'&x"BBBE",'1'&x"BBBF",
+--'1'&x"BBC0",'1'&x"BBC1",'1'&x"BBC2",'1'&x"BBC3",'1'&x"BBC4",'1'&x"BBC5",'1'&x"BBC6",'1'&x"BBC7",'1'&x"BBC8",'1'&x"BBC9",'1'&x"BBCA",'1'&x"BBCB",'1'&x"BBCC",'1'&x"BBCD",'1'&x"BBCE",'1'&x"BBCF",
+--'1'&x"BBD0",'1'&x"BBD1",'1'&x"BBD2",'1'&x"BBD3",'1'&x"BBD4",'1'&x"BBD5",'1'&x"BBD6",'1'&x"BBD7",'1'&x"BBD8",'1'&x"BBD9",'1'&x"BBDA",'1'&x"BBDB",'1'&x"BBDC",'1'&x"BBDD",'1'&x"BBDE",'1'&x"BBDF",
+--'1'&x"BBE0",'1'&x"BBE1",'1'&x"BBE2",'1'&x"BBE3",'1'&x"BBE4",'1'&x"BBE5",'1'&x"BBE6",'1'&x"BBE7",'1'&x"BBE8",'1'&x"BBE9",'1'&x"BBEA",'1'&x"BBEB",'1'&x"BBEC",'1'&x"BBED",'1'&x"BBEE",'1'&x"BBEF",
+--'1'&x"BBF0",'1'&x"BBF1",'1'&x"BBF2",'1'&x"BBF3",'1'&x"BBF4",'1'&x"BBF5",'1'&x"BBF6",'1'&x"BBF7",'1'&x"BBF8",'1'&x"BBF9",'1'&x"BBFA",'1'&x"BBFB",'1'&x"BBFC",'1'&x"BBFD",'1'&x"BBFE",'1'&x"BBFF",
+--'1'&x"BC00",'1'&x"BC01",'1'&x"BC02",'1'&x"BC03",'1'&x"BC04",'1'&x"BC05",'1'&x"BC06",'1'&x"BC07",'1'&x"BC08",'1'&x"BC09",'1'&x"BC0A",'1'&x"BC0B",'1'&x"BC0C",'1'&x"BC0D",'1'&x"BC0E",'1'&x"BC0F",
+--'1'&x"BC10",'1'&x"BC11",'1'&x"BC12",'1'&x"BC13",'1'&x"BC14",'1'&x"BC15",'1'&x"BC16",'1'&x"BC17",'1'&x"BC18",'1'&x"BC19",'1'&x"BC1A",'1'&x"BC1B",'1'&x"BC1C",'1'&x"BC1D",'1'&x"BC1E",'1'&x"BC1F",
+--'1'&x"BC20",'1'&x"BC21",'1'&x"BC22",'1'&x"BC23",'1'&x"BC24",'1'&x"BC25",'1'&x"BC26",'1'&x"BC27",'1'&x"BC28",'1'&x"BC29",'1'&x"BC2A",'1'&x"BC2B",'1'&x"BC2C",'1'&x"BC2D",'1'&x"BC2E",'1'&x"BC2F",
+--'1'&x"BC30",'1'&x"BC31",'1'&x"BC32",'1'&x"BC33",'1'&x"BC34",'1'&x"BC35",'1'&x"BC36",'1'&x"BC37",'1'&x"BC38",'1'&x"BC39",'1'&x"BC3A",'1'&x"BC3B",'1'&x"BC3C",'1'&x"BC3D",'1'&x"BC3E",'1'&x"BC3F",
+--'1'&x"BC40",'1'&x"BC41",'1'&x"BC42",'1'&x"BC43",'1'&x"BC44",'1'&x"BC45",'1'&x"BC46",'1'&x"BC47",'1'&x"BC48",'1'&x"BC49",'1'&x"BC4A",'1'&x"BC4B",'1'&x"BC4C",'1'&x"BC4D",'1'&x"BC4E",'1'&x"BC4F",
+--'1'&x"BC50",'1'&x"BC51",'1'&x"BC52",'1'&x"BC53",'1'&x"BC54",'1'&x"BC55",'1'&x"BC56",'1'&x"BC57",'1'&x"BC58",'1'&x"BC59",'1'&x"BC5A",'1'&x"BC5B",'1'&x"BC5C",'1'&x"BC5D",'1'&x"BC5E",'1'&x"BC5F",
+--'1'&x"BC60",'1'&x"BC61",'1'&x"BC62",'1'&x"BC63",'1'&x"BC64",'1'&x"BC65",'1'&x"BC66",'1'&x"BC67",'1'&x"BC68",'1'&x"BC69",'1'&x"BC6A",'1'&x"BC6B",'1'&x"BC6C",'1'&x"BC6D",'1'&x"BC6E",'1'&x"BC6F",
+--'1'&x"BC70",'1'&x"BC71",'1'&x"BC72",'1'&x"BC73",'1'&x"BC74",'1'&x"BC75",'1'&x"BC76",'1'&x"BC77",'1'&x"BC78",'1'&x"BC79",'1'&x"BC7A",'1'&x"BC7B",'1'&x"BC7C",'1'&x"BC7D",'1'&x"BC7E",'1'&x"BC7F",
+--'1'&x"BC80",'1'&x"BC81",'1'&x"BC82",'1'&x"BC83",'1'&x"BC84",'1'&x"BC85",'1'&x"BC86",'1'&x"BC87",'1'&x"BC88",'1'&x"BC89",'1'&x"BC8A",'1'&x"BC8B",'1'&x"BC8C",'1'&x"BC8D",'1'&x"BC8E",'1'&x"BC8F",
+--'1'&x"BC90",'1'&x"BC91",'1'&x"BC92",'1'&x"BC93",'1'&x"BC94",'1'&x"BC95",'1'&x"BC96",'1'&x"BC97",'1'&x"BC98",'1'&x"BC99",'1'&x"BC9A",'1'&x"BC9B",'1'&x"BC9C",'1'&x"BC9D",'1'&x"BC9E",'1'&x"BC9F",
+--'1'&x"BCA0",'1'&x"BCA1",'1'&x"BCA2",'1'&x"BCA3",'1'&x"BCA4",'1'&x"BCA5",'1'&x"BCA6",'1'&x"BCA7",'1'&x"BCA8",'1'&x"BCA9",'1'&x"BCAA",'1'&x"BCAB",'1'&x"BCAC",'1'&x"BCAD",'1'&x"BCAE",'1'&x"BCAF",
+--'1'&x"BCB0",'1'&x"BCB1",'1'&x"BCB2",'1'&x"BCB3",'1'&x"BCB4",'1'&x"BCB5",'1'&x"BCB6",'1'&x"BCB7",'1'&x"BCB8",'1'&x"BCB9",'1'&x"BCBA",'1'&x"BCBB",'1'&x"BCBC",'1'&x"BCBD",'1'&x"BCBE",'1'&x"BCBF",
+--'1'&x"BCC0",'1'&x"BCC1",'1'&x"BCC2",'1'&x"BCC3",'1'&x"BCC4",'1'&x"BCC5",'1'&x"BCC6",'1'&x"BCC7",'1'&x"BCC8",'1'&x"BCC9",'1'&x"BCCA",'1'&x"BCCB",'1'&x"BCCC",'1'&x"BCCD",'1'&x"BCCE",'1'&x"BCCF",
+--'1'&x"BCD0",'1'&x"BCD1",'1'&x"BCD2",'1'&x"BCD3",'1'&x"BCD4",'1'&x"BCD5",'1'&x"BCD6",'1'&x"BCD7",'1'&x"BCD8",'1'&x"BCD9",'1'&x"BCDA",'1'&x"BCDB",'1'&x"BCDC",'1'&x"BCDD",'1'&x"BCDE",'1'&x"BCDF",
+--'1'&x"BCE0",'1'&x"BCE1",'1'&x"BCE2",'1'&x"BCE3",'1'&x"BCE4",'1'&x"BCE5",'1'&x"BCE6",'1'&x"BCE7",'1'&x"BCE8",'1'&x"BCE9",'1'&x"BCEA",'1'&x"BCEB",'1'&x"BCEC",'1'&x"BCED",'1'&x"BCEE",'1'&x"BCEF",
+--'1'&x"BCF0",'1'&x"BCF1",'1'&x"BCF2",'1'&x"BCF3",'1'&x"BCF4",'1'&x"BCF5",'1'&x"BCF6",'1'&x"BCF7",'1'&x"BCF8",'1'&x"BCF9",'1'&x"BCFA",'1'&x"BCFB",'1'&x"BCFC",'1'&x"BCFD",'1'&x"BCFE",'1'&x"BCFF",
+--'1'&x"BD00",'1'&x"BD01",'1'&x"BD02",'1'&x"BD03",'1'&x"BD04",'1'&x"BD05",'1'&x"BD06",'1'&x"BD07",'1'&x"BD08",'1'&x"BD09",'1'&x"BD0A",'1'&x"BD0B",'1'&x"BD0C",'1'&x"BD0D",'1'&x"BD0E",'1'&x"BD0F",
+--'1'&x"BD10",'1'&x"BD11",'1'&x"BD12",'1'&x"BD13",'1'&x"BD14",'1'&x"BD15",'1'&x"BD16",'1'&x"BD17",'1'&x"BD18",'1'&x"BD19",'1'&x"BD1A",'1'&x"BD1B",'1'&x"BD1C",'1'&x"BD1D",'1'&x"BD1E",'1'&x"BD1F",
+--'1'&x"BD20",'1'&x"BD21",'1'&x"BD22",'1'&x"BD23",'1'&x"BD24",'1'&x"BD25",'1'&x"BD26",'1'&x"BD27",'1'&x"BD28",'1'&x"BD29",'1'&x"BD2A",'1'&x"BD2B",'1'&x"BD2C",'1'&x"BD2D",'1'&x"BD2E",'1'&x"BD2F",
+--'1'&x"BD30",'1'&x"BD31",'1'&x"BD32",'1'&x"BD33",'1'&x"BD34",'1'&x"BD35",'1'&x"BD36",'1'&x"BD37",'1'&x"BD38",'1'&x"BD39",'1'&x"BD3A",'1'&x"BD3B",'1'&x"BD3C",'1'&x"BD3D",'1'&x"BD3E",'1'&x"BD3F",
+--'1'&x"BD40",'1'&x"BD41",'1'&x"BD42",'1'&x"BD43",'1'&x"BD44",'1'&x"BD45",'1'&x"BD46",'1'&x"BD47",'1'&x"BD48",'1'&x"BD49",'1'&x"BD4A",'1'&x"BD4B",'1'&x"BD4C",'1'&x"BD4D",'1'&x"BD4E",'1'&x"BD4F",
+--'1'&x"BD50",'1'&x"BD51",'1'&x"BD52",'1'&x"BD53",'1'&x"BD54",'1'&x"BD55",'1'&x"BD56",'1'&x"BD57",'1'&x"BD58",'1'&x"BD59",'1'&x"BD5A",'1'&x"BD5B",'1'&x"BD5C",'1'&x"BD5D",'1'&x"BD5E",'1'&x"BD5F",
+--'1'&x"BD60",'1'&x"BD61",'1'&x"BD62",'1'&x"BD63",'1'&x"BD64",'1'&x"BD65",'1'&x"BD66",'1'&x"BD67",'1'&x"BD68",'1'&x"BD69",'1'&x"BD6A",'1'&x"BD6B",'1'&x"BD6C",'1'&x"BD6D",'1'&x"BD6E",'1'&x"BD6F",
+--'1'&x"BD70",'1'&x"BD71",'1'&x"BD72",'1'&x"BD73",'1'&x"BD74",'1'&x"BD75",'1'&x"BD76",'1'&x"BD77",'1'&x"BD78",'1'&x"BD79",'1'&x"BD7A",'1'&x"BD7B",'1'&x"BD7C",'1'&x"BD7D",'1'&x"BD7E",'1'&x"BD7F",
+--'1'&x"BD80",'1'&x"BD81",'1'&x"BD82",'1'&x"BD83",'1'&x"BD84",'1'&x"BD85",'1'&x"BD86",'1'&x"BD87",'1'&x"BD88",'1'&x"BD89",'1'&x"BD8A",'1'&x"BD8B",'1'&x"BD8C",'1'&x"BD8D",'1'&x"BD8E",'1'&x"BD8F",
+--'1'&x"BD90",'1'&x"BD91",'1'&x"BD92",'1'&x"BD93",'1'&x"BD94",'1'&x"BD95",'1'&x"BD96",'1'&x"BD97",'1'&x"BD98",'1'&x"BD99",'1'&x"BD9A",'1'&x"BD9B",'1'&x"BD9C",'1'&x"BD9D",'1'&x"BD9E",'1'&x"BD9F",
+--'1'&x"BDA0",'1'&x"BDA1",'1'&x"BDA2",'1'&x"BDA3",'1'&x"BDA4",'1'&x"BDA5",'1'&x"BDA6",'1'&x"BDA7",'1'&x"BDA8",'1'&x"BDA9",'1'&x"BDAA",'1'&x"BDAB",'1'&x"BDAC",'1'&x"BDAD",'1'&x"BDAE",'1'&x"BDAF",
+--'1'&x"BDB0",'1'&x"BDB1",'1'&x"BDB2",'1'&x"BDB3",'1'&x"BDB4",'1'&x"BDB5",'1'&x"BDB6",'1'&x"BDB7",'1'&x"BDB8",'1'&x"BDB9",'1'&x"BDBA",'1'&x"BDBB",'1'&x"BDBC",'1'&x"BDBD",'1'&x"BDBE",'1'&x"BDBF",
+--'1'&x"BDC0",'1'&x"BDC1",'1'&x"BDC2",'1'&x"BDC3",'1'&x"BDC4",'1'&x"BDC5",'1'&x"BDC6",'1'&x"BDC7",'1'&x"BDC8",'1'&x"BDC9",'1'&x"BDCA",'1'&x"BDCB",'1'&x"BDCC",'1'&x"BDCD",'1'&x"BDCE",'1'&x"BDCF",
+--'1'&x"BDD0",'1'&x"BDD1",'1'&x"BDD2",'1'&x"BDD3",'1'&x"BDD4",'1'&x"BDD5",'1'&x"BDD6",'1'&x"BDD7",'1'&x"BDD8",'1'&x"BDD9",'1'&x"BDDA",'1'&x"BDDB",'1'&x"BDDC",'1'&x"BDDD",'1'&x"BDDE",'1'&x"BDDF",
+--'1'&x"BDE0",'1'&x"BDE1",'1'&x"BDE2",'1'&x"BDE3",'1'&x"BDE4",'1'&x"BDE5",'1'&x"BDE6",'1'&x"BDE7",'1'&x"BDE8",'1'&x"BDE9",'1'&x"BDEA",'1'&x"BDEB",'1'&x"BDEC",'1'&x"BDED",'1'&x"BDEE",'1'&x"BDEF",
+--'1'&x"BDF0",'1'&x"BDF1",'1'&x"BDF2",'1'&x"BDF3",'1'&x"BDF4",'1'&x"BDF5",'1'&x"BDF6",'1'&x"BDF7",'1'&x"BDF8",'1'&x"BDF9",'1'&x"BDFA",'1'&x"BDFB",'1'&x"BDFC",'1'&x"BDFD",'1'&x"BDFE",'1'&x"BDFF",
+--'1'&x"BE00",'1'&x"BE01",'1'&x"BE02",'1'&x"BE03",'1'&x"BE04",'1'&x"BE05",'1'&x"BE06",'1'&x"BE07",'1'&x"BE08",'1'&x"BE09",'1'&x"BE0A",'1'&x"BE0B",'1'&x"BE0C",'1'&x"BE0D",'1'&x"BE0E",'1'&x"BE0F",
+--'1'&x"BE10",'1'&x"BE11",'1'&x"BE12",'1'&x"BE13",'1'&x"BE14",'1'&x"BE15",'1'&x"BE16",'1'&x"BE17",'1'&x"BE18",'1'&x"BE19",'1'&x"BE1A",'1'&x"BE1B",'1'&x"BE1C",'1'&x"BE1D",'1'&x"BE1E",'1'&x"BE1F",
+--'1'&x"BE20",'1'&x"BE21",'1'&x"BE22",'1'&x"BE23",'1'&x"BE24",'1'&x"BE25",'1'&x"BE26",'1'&x"BE27",'1'&x"BE28",'1'&x"BE29",'1'&x"BE2A",'1'&x"BE2B",'1'&x"BE2C",'1'&x"BE2D",'1'&x"BE2E",'1'&x"BE2F",
+--'1'&x"BE30",'1'&x"BE31",'1'&x"BE32",'1'&x"BE33",'1'&x"BE34",'1'&x"BE35",'1'&x"BE36",'1'&x"BE37",'1'&x"BE38",'1'&x"BE39",'1'&x"BE3A",'1'&x"BE3B",'1'&x"BE3C",'1'&x"BE3D",'1'&x"BE3E",'1'&x"BE3F",
+--'1'&x"BE40",'1'&x"BE41",'1'&x"BE42",'1'&x"BE43",'1'&x"BE44",'1'&x"BE45",'1'&x"BE46",'1'&x"BE47",'1'&x"BE48",'1'&x"BE49",'1'&x"BE4A",'1'&x"BE4B",'1'&x"BE4C",'1'&x"BE4D",'1'&x"BE4E",'1'&x"BE4F",
+--'1'&x"BE50",'1'&x"BE51",'1'&x"BE52",'1'&x"BE53",'1'&x"BE54",'1'&x"BE55",'1'&x"BE56",'1'&x"BE57",'1'&x"BE58",'1'&x"BE59",'1'&x"BE5A",'1'&x"BE5B",'1'&x"BE5C",'1'&x"BE5D",'1'&x"BE5E",'1'&x"BE5F",
+--'1'&x"BE60",'1'&x"BE61",'1'&x"BE62",'1'&x"BE63",'1'&x"BE64",'1'&x"BE65",'1'&x"BE66",'1'&x"BE67",'1'&x"BE68",'1'&x"BE69",'1'&x"BE6A",'1'&x"BE6B",'1'&x"BE6C",'1'&x"BE6D",'1'&x"BE6E",'1'&x"BE6F",
+--'1'&x"BE70",'1'&x"BE71",'1'&x"BE72",'1'&x"BE73",'1'&x"BE74",'1'&x"BE75",'1'&x"BE76",'1'&x"BE77",'1'&x"BE78",'1'&x"BE79",'1'&x"BE7A",'1'&x"BE7B",'1'&x"BE7C",'1'&x"BE7D",'1'&x"BE7E",'1'&x"BE7F",
+--'1'&x"BE80",'1'&x"BE81",'1'&x"BE82",'1'&x"BE83",'1'&x"BE84",'1'&x"BE85",'1'&x"BE86",'1'&x"BE87",'1'&x"BE88",'1'&x"BE89",'1'&x"BE8A",'1'&x"BE8B",'1'&x"BE8C",'1'&x"BE8D",'1'&x"BE8E",'1'&x"BE8F",
+--'1'&x"BE90",'1'&x"BE91",'1'&x"BE92",'1'&x"BE93",'1'&x"BE94",'1'&x"BE95",'1'&x"BE96",'1'&x"BE97",'1'&x"BE98",'1'&x"BE99",'1'&x"BE9A",'1'&x"BE9B",'1'&x"BE9C",'1'&x"BE9D",'1'&x"BE9E",'1'&x"BE9F",
+--'1'&x"BEA0",'1'&x"BEA1",'1'&x"BEA2",'1'&x"BEA3",'1'&x"BEA4",'1'&x"BEA5",'1'&x"BEA6",'1'&x"BEA7",'1'&x"BEA8",'1'&x"BEA9",'1'&x"BEAA",'1'&x"BEAB",'1'&x"BEAC",'1'&x"BEAD",'1'&x"BEAE",'1'&x"BEAF",
+--'1'&x"BEB0",'1'&x"BEB1",'1'&x"BEB2",'1'&x"BEB3",'1'&x"BEB4",'1'&x"BEB5",'1'&x"BEB6",'1'&x"BEB7",'1'&x"BEB8",'1'&x"BEB9",'1'&x"BEBA",'1'&x"BEBB",'1'&x"BEBC",'1'&x"BEBD",'1'&x"BEBE",'1'&x"BEBF",
+--'1'&x"BEC0",'1'&x"BEC1",'1'&x"BEC2",'1'&x"BEC3",'1'&x"BEC4",'1'&x"BEC5",'1'&x"BEC6",'1'&x"BEC7",'1'&x"BEC8",'1'&x"BEC9",'1'&x"BECA",'1'&x"BECB",'1'&x"BECC",'1'&x"BECD",'1'&x"BECE",'1'&x"BECF",
+--'1'&x"BED0",'1'&x"BED1",'1'&x"BED2",'1'&x"BED3",'1'&x"BED4",'1'&x"BED5",'1'&x"BED6",'1'&x"BED7",'1'&x"BED8",'1'&x"BED9",'1'&x"BEDA",'1'&x"BEDB",'1'&x"BEDC",'1'&x"BEDD",'1'&x"BEDE",'1'&x"BEDF",
+--'1'&x"BEE0",'1'&x"BEE1",'1'&x"BEE2",'1'&x"BEE3",'1'&x"BEE4",'1'&x"BEE5",'1'&x"BEE6",'1'&x"BEE7",'1'&x"BEE8",'1'&x"BEE9",'1'&x"BEEA",'1'&x"BEEB",'1'&x"BEEC",'1'&x"BEED",'1'&x"BEEE",'1'&x"BEEF",
+--'1'&x"BEF0",'1'&x"BEF1",'1'&x"BEF2",'1'&x"BEF3",'1'&x"BEF4",'1'&x"BEF5",'1'&x"BEF6",'1'&x"BEF7",'1'&x"BEF8",'1'&x"BEF9",'1'&x"BEFA",'1'&x"BEFB",'1'&x"BEFC",'1'&x"BEFD",'1'&x"BEFE",'1'&x"BEFF",
+--'1'&x"BF00",'1'&x"BF01",'1'&x"BF02",'1'&x"BF03",'1'&x"BF04",'1'&x"BF05",'1'&x"BF06",'1'&x"BF07",'1'&x"BF08",'1'&x"BF09",'1'&x"BF0A",'1'&x"BF0B",'1'&x"BF0C",'1'&x"BF0D",'1'&x"BF0E",'1'&x"BF0F",
+--'1'&x"BF10",'1'&x"BF11",'1'&x"BF12",'1'&x"BF13",'1'&x"BF14",'1'&x"BF15",'1'&x"BF16",'1'&x"BF17",'1'&x"BF18",'1'&x"BF19",'1'&x"BF1A",'1'&x"BF1B",'1'&x"BF1C",'1'&x"BF1D",'1'&x"BF1E",'1'&x"BF1F",
+--'1'&x"BF20",'1'&x"BF21",'1'&x"BF22",'1'&x"BF23",'1'&x"BF24",'1'&x"BF25",'1'&x"BF26",'1'&x"BF27",'1'&x"BF28",'1'&x"BF29",'1'&x"BF2A",'1'&x"BF2B",'1'&x"BF2C",'1'&x"BF2D",'1'&x"BF2E",'1'&x"BF2F",
+--'1'&x"BF30",'1'&x"BF31",'1'&x"BF32",'1'&x"BF33",'1'&x"BF34",'1'&x"BF35",'1'&x"BF36",'1'&x"BF37",'1'&x"BF38",'1'&x"BF39",'1'&x"BF3A",'1'&x"BF3B",'1'&x"BF3C",'1'&x"BF3D",'1'&x"BF3E",'1'&x"BF3F",
+--'1'&x"BF40",'1'&x"BF41",'1'&x"BF42",'1'&x"BF43",'1'&x"BF44",'1'&x"BF45",'1'&x"BF46",'1'&x"BF47",'1'&x"BF48",'1'&x"BF49",'1'&x"BF4A",'1'&x"BF4B",'1'&x"BF4C",'1'&x"BF4D",'1'&x"BF4E",'1'&x"BF4F",
+--'1'&x"BF50",'1'&x"BF51",'1'&x"BF52",'1'&x"BF53",'1'&x"BF54",'1'&x"BF55",'1'&x"BF56",'1'&x"BF57",'1'&x"BF58",'1'&x"BF59",'1'&x"BF5A",'1'&x"BF5B",'1'&x"BF5C",'1'&x"BF5D",'1'&x"BF5E",'1'&x"BF5F",
+--'1'&x"BF60",'1'&x"BF61",'1'&x"BF62",'1'&x"BF63",'1'&x"BF64",'1'&x"BF65",'1'&x"BF66",'1'&x"BF67",'1'&x"BF68",'1'&x"BF69",'1'&x"BF6A",'1'&x"BF6B",'1'&x"BF6C",'1'&x"BF6D",'1'&x"BF6E",'1'&x"BF6F",
+--'1'&x"BF70",'1'&x"BF71",'1'&x"BF72",'1'&x"BF73",'1'&x"BF74",'1'&x"BF75",'1'&x"BF76",'1'&x"BF77",'1'&x"BF78",'1'&x"BF79",'1'&x"BF7A",'1'&x"BF7B",'1'&x"BF7C",'1'&x"BF7D",'1'&x"BF7E",'1'&x"BF7F",
+--'1'&x"BF80",'1'&x"BF81",'1'&x"BF82",'1'&x"BF83",'1'&x"BF84",'1'&x"BF85",'1'&x"BF86",'1'&x"BF87",'1'&x"BF88",'1'&x"BF89",'1'&x"BF8A",'1'&x"BF8B",'1'&x"BF8C",'1'&x"BF8D",'1'&x"BF8E",'1'&x"BF8F",
+--'1'&x"BF90",'1'&x"BF91",'1'&x"BF92",'1'&x"BF93",'1'&x"BF94",'1'&x"BF95",'1'&x"BF96",'1'&x"BF97",'1'&x"BF98",'1'&x"BF99",'1'&x"BF9A",'1'&x"BF9B",'1'&x"BF9C",'1'&x"BF9D",'1'&x"BF9E",'1'&x"BF9F",
+--'1'&x"BFA0",'1'&x"BFA1",'1'&x"BFA2",'1'&x"BFA3",'1'&x"BFA4",'1'&x"BFA5",'1'&x"BFA6",'1'&x"BFA7",'1'&x"BFA8",'1'&x"BFA9",'1'&x"BFAA",'1'&x"BFAB",'1'&x"BFAC",'1'&x"BFAD",'1'&x"BFAE",'1'&x"BFAF",
+--'1'&x"BFB0",'1'&x"BFB1",'1'&x"BFB2",'1'&x"BFB3",'1'&x"BFB4",'1'&x"BFB5",'1'&x"BFB6",'1'&x"BFB7",'1'&x"BFB8",'1'&x"BFB9",'1'&x"BFBA",'1'&x"BFBB",'1'&x"BFBC",'1'&x"BFBD",'1'&x"BFBE",'1'&x"BFBF",
+--'1'&x"BFC0",'1'&x"BFC1",'1'&x"BFC2",'1'&x"BFC3",'1'&x"BFC4",'1'&x"BFC5",'1'&x"BFC6",'1'&x"BFC7",'1'&x"BFC8",'1'&x"BFC9",'1'&x"BFCA",'1'&x"BFCB",'1'&x"BFCC",'1'&x"BFCD",'1'&x"BFCE",'1'&x"BFCF",
+--'1'&x"BFD0",'1'&x"BFD1",'1'&x"BFD2",'1'&x"BFD3",'1'&x"BFD4",'1'&x"BFD5",'1'&x"BFD6",'1'&x"BFD7",'1'&x"BFD8",'1'&x"BFD9",'1'&x"BFDA",'1'&x"BFDB",'1'&x"BFDC",'1'&x"BFDD",'1'&x"BFDE",'1'&x"BFDF",
+--'1'&x"BFE0",'1'&x"BFE1",'1'&x"BFE2",'1'&x"BFE3",'1'&x"BFE4",'1'&x"BFE5",'1'&x"BFE6",'1'&x"BFE7",'1'&x"BFE8",'1'&x"BFE9",'1'&x"BFEA",'1'&x"BFEB",'1'&x"BFEC",'1'&x"BFED",'1'&x"BFEE",'1'&x"BFEF",
+--'1'&x"BFF0",'1'&x"BFF1",'1'&x"BFF2",'1'&x"BFF3",'1'&x"BFF4",'1'&x"BFF5",'1'&x"BFF6",'1'&x"BFF7",'1'&x"BFF8",'1'&x"BFF9",'1'&x"BFFA",'1'&x"BFFB",'1'&x"BFFC",'1'&x"BFFD",'1'&x"BFFE",'1'&x"BFFF",
+--'1'&x"C000",'1'&x"C001",'1'&x"C002",'1'&x"C003",'1'&x"C004",'1'&x"C005",'1'&x"C006",'1'&x"C007",'1'&x"C008",'1'&x"C009",'1'&x"C00A",'1'&x"C00B",'1'&x"C00C",'1'&x"C00D",'1'&x"C00E",'1'&x"C00F",
+--'1'&x"C010",'1'&x"C011",'1'&x"C012",'1'&x"C013",'1'&x"C014",'1'&x"C015",'1'&x"C016",'1'&x"C017",'1'&x"C018",'1'&x"C019",'1'&x"C01A",'1'&x"C01B",'1'&x"C01C",'1'&x"C01D",'1'&x"C01E",'1'&x"C01F",
+--'1'&x"C020",'1'&x"C021",'1'&x"C022",'1'&x"C023",'1'&x"C024",'1'&x"C025",'1'&x"C026",'1'&x"C027",'1'&x"C028",'1'&x"C029",'1'&x"C02A",'1'&x"C02B",'1'&x"C02C",'1'&x"C02D",'1'&x"C02E",'1'&x"C02F",
+--'1'&x"C030",'1'&x"C031",'1'&x"C032",'1'&x"C033",'1'&x"C034",'1'&x"C035",'1'&x"C036",'1'&x"C037",'1'&x"C038",'1'&x"C039",'1'&x"C03A",'1'&x"C03B",'1'&x"C03C",'1'&x"C03D",'1'&x"C03E",'1'&x"C03F",
+--'1'&x"C040",'1'&x"C041",'1'&x"C042",'1'&x"C043",'1'&x"C044",'1'&x"C045",'1'&x"C046",'1'&x"C047",'1'&x"C048",'1'&x"C049",'1'&x"C04A",'1'&x"C04B",'1'&x"C04C",'1'&x"C04D",'1'&x"C04E",'1'&x"C04F",
+--'1'&x"C050",'1'&x"C051",'1'&x"C052",'1'&x"C053",'1'&x"C054",'1'&x"C055",'1'&x"C056",'1'&x"C057",'1'&x"C058",'1'&x"C059",'1'&x"C05A",'1'&x"C05B",'1'&x"C05C",'1'&x"C05D",'1'&x"C05E",'1'&x"C05F",
+--'1'&x"C060",'1'&x"C061",'1'&x"C062",'1'&x"C063",'1'&x"C064",'1'&x"C065",'1'&x"C066",'1'&x"C067",'1'&x"C068",'1'&x"C069",'1'&x"C06A",'1'&x"C06B",'1'&x"C06C",'1'&x"C06D",'1'&x"C06E",'1'&x"C06F",
+--'1'&x"C070",'1'&x"C071",'1'&x"C072",'1'&x"C073",'1'&x"C074",'1'&x"C075",'1'&x"C076",'1'&x"C077",'1'&x"C078",'1'&x"C079",'1'&x"C07A",'1'&x"C07B",'1'&x"C07C",'1'&x"C07D",'1'&x"C07E",'1'&x"C07F",
+--'1'&x"C080",'1'&x"C081",'1'&x"C082",'1'&x"C083",'1'&x"C084",'1'&x"C085",'1'&x"C086",'1'&x"C087",'1'&x"C088",'1'&x"C089",'1'&x"C08A",'1'&x"C08B",'1'&x"C08C",'1'&x"C08D",'1'&x"C08E",'1'&x"C08F",
+--'1'&x"C090",'1'&x"C091",'1'&x"C092",'1'&x"C093",'1'&x"C094",'1'&x"C095",'1'&x"C096",'1'&x"C097",'1'&x"C098",'1'&x"C099",'1'&x"C09A",'1'&x"C09B",'1'&x"C09C",'1'&x"C09D",'1'&x"C09E",'1'&x"C09F",
+--'1'&x"C0A0",'1'&x"C0A1",'1'&x"C0A2",'1'&x"C0A3",'1'&x"C0A4",'1'&x"C0A5",'1'&x"C0A6",'1'&x"C0A7",'1'&x"C0A8",'1'&x"C0A9",'1'&x"C0AA",'1'&x"C0AB",'1'&x"C0AC",'1'&x"C0AD",'1'&x"C0AE",'1'&x"C0AF",
+--'1'&x"C0B0",'1'&x"C0B1",'1'&x"C0B2",'1'&x"C0B3",'1'&x"C0B4",'1'&x"C0B5",'1'&x"C0B6",'1'&x"C0B7",'1'&x"C0B8",'1'&x"C0B9",'1'&x"C0BA",'1'&x"C0BB",'1'&x"C0BC",'1'&x"C0BD",'1'&x"C0BE",'1'&x"C0BF",
+--'1'&x"C0C0",'1'&x"C0C1",'1'&x"C0C2",'1'&x"C0C3",'1'&x"C0C4",'1'&x"C0C5",'1'&x"C0C6",'1'&x"C0C7",'1'&x"C0C8",'1'&x"C0C9",'1'&x"C0CA",'1'&x"C0CB",'1'&x"C0CC",'1'&x"C0CD",'1'&x"C0CE",'1'&x"C0CF",
+--'1'&x"C0D0",'1'&x"C0D1",'1'&x"C0D2",'1'&x"C0D3",'1'&x"C0D4",'1'&x"C0D5",'1'&x"C0D6",'1'&x"C0D7",'1'&x"C0D8",'1'&x"C0D9",'1'&x"C0DA",'1'&x"C0DB",'1'&x"C0DC",'1'&x"C0DD",'1'&x"C0DE",'1'&x"C0DF",
+--'1'&x"C0E0",'1'&x"C0E1",'1'&x"C0E2",'1'&x"C0E3",'1'&x"C0E4",'1'&x"C0E5",'1'&x"C0E6",'1'&x"C0E7",'1'&x"C0E8",'1'&x"C0E9",'1'&x"C0EA",'1'&x"C0EB",'1'&x"C0EC",'1'&x"C0ED",'1'&x"C0EE",'1'&x"C0EF",
+--'1'&x"C0F0",'1'&x"C0F1",'1'&x"C0F2",'1'&x"C0F3",'1'&x"C0F4",'1'&x"C0F5",'1'&x"C0F6",'1'&x"C0F7",'1'&x"C0F8",'1'&x"C0F9",'1'&x"C0FA",'1'&x"C0FB",'1'&x"C0FC",'1'&x"C0FD",'1'&x"C0FE",'1'&x"C0FF",
+--'1'&x"C100",'1'&x"C101",'1'&x"C102",'1'&x"C103",'1'&x"C104",'1'&x"C105",'1'&x"C106",'1'&x"C107",'1'&x"C108",'1'&x"C109",'1'&x"C10A",'1'&x"C10B",'1'&x"C10C",'1'&x"C10D",'1'&x"C10E",'1'&x"C10F",
+--'1'&x"C110",'1'&x"C111",'1'&x"C112",'1'&x"C113",'1'&x"C114",'1'&x"C115",'1'&x"C116",'1'&x"C117",'1'&x"C118",'1'&x"C119",'1'&x"C11A",'1'&x"C11B",'1'&x"C11C",'1'&x"C11D",'1'&x"C11E",'1'&x"C11F",
+--'1'&x"C120",'1'&x"C121",'1'&x"C122",'1'&x"C123",'1'&x"C124",'1'&x"C125",'1'&x"C126",'1'&x"C127",'1'&x"C128",'1'&x"C129",'1'&x"C12A",'1'&x"C12B",'1'&x"C12C",'1'&x"C12D",'1'&x"C12E",'1'&x"C12F",
+--'1'&x"C130",'1'&x"C131",'1'&x"C132",'1'&x"C133",'1'&x"C134",'1'&x"C135",'1'&x"C136",'1'&x"C137",'1'&x"C138",'1'&x"C139",'1'&x"C13A",'1'&x"C13B",'1'&x"C13C",'1'&x"C13D",'1'&x"C13E",'1'&x"C13F",
+--'1'&x"C140",'1'&x"C141",'1'&x"C142",'1'&x"C143",'1'&x"C144",'1'&x"C145",'1'&x"C146",'1'&x"C147",'1'&x"C148",'1'&x"C149",'1'&x"C14A",'1'&x"C14B",'1'&x"C14C",'1'&x"C14D",'1'&x"C14E",'1'&x"C14F",
+--'1'&x"C150",'1'&x"C151",'1'&x"C152",'1'&x"C153",'1'&x"C154",'1'&x"C155",'1'&x"C156",'1'&x"C157",'1'&x"C158",'1'&x"C159",'1'&x"C15A",'1'&x"C15B",'1'&x"C15C",'1'&x"C15D",'1'&x"C15E",'1'&x"C15F",
+--'1'&x"C160",'1'&x"C161",'1'&x"C162",'1'&x"C163",'1'&x"C164",'1'&x"C165",'1'&x"C166",'1'&x"C167",'1'&x"C168",'1'&x"C169",'1'&x"C16A",'1'&x"C16B",'1'&x"C16C",'1'&x"C16D",'1'&x"C16E",'1'&x"C16F",
+--'1'&x"C170",'1'&x"C171",'1'&x"C172",'1'&x"C173",'1'&x"C174",'1'&x"C175",'1'&x"C176",'1'&x"C177",'1'&x"C178",'1'&x"C179",'1'&x"C17A",'1'&x"C17B",'1'&x"C17C",'1'&x"C17D",'1'&x"C17E",'1'&x"C17F",
+--'1'&x"C180",'1'&x"C181",'1'&x"C182",'1'&x"C183",'1'&x"C184",'1'&x"C185",'1'&x"C186",'1'&x"C187",'1'&x"C188",'1'&x"C189",'1'&x"C18A",'1'&x"C18B",'1'&x"C18C",'1'&x"C18D",'1'&x"C18E",'1'&x"C18F",
+--'1'&x"C190",'1'&x"C191",'1'&x"C192",'1'&x"C193",'1'&x"C194",'1'&x"C195",'1'&x"C196",'1'&x"C197",'1'&x"C198",'1'&x"C199",'1'&x"C19A",'1'&x"C19B",'1'&x"C19C",'1'&x"C19D",'1'&x"C19E",'1'&x"C19F",
+--'1'&x"C1A0",'1'&x"C1A1",'1'&x"C1A2",'1'&x"C1A3",'1'&x"C1A4",'1'&x"C1A5",'1'&x"C1A6",'1'&x"C1A7",'1'&x"C1A8",'1'&x"C1A9",'1'&x"C1AA",'1'&x"C1AB",'1'&x"C1AC",'1'&x"C1AD",'1'&x"C1AE",'1'&x"C1AF",
+--'1'&x"C1B0",'1'&x"C1B1",'1'&x"C1B2",'1'&x"C1B3",'1'&x"C1B4",'1'&x"C1B5",'1'&x"C1B6",'1'&x"C1B7",'1'&x"C1B8",'1'&x"C1B9",'1'&x"C1BA",'1'&x"C1BB",'1'&x"C1BC",'1'&x"C1BD",'1'&x"C1BE",'1'&x"C1BF",
+--'1'&x"C1C0",'1'&x"C1C1",'1'&x"C1C2",'1'&x"C1C3",'1'&x"C1C4",'1'&x"C1C5",'1'&x"C1C6",'1'&x"C1C7",'1'&x"C1C8",'1'&x"C1C9",'1'&x"C1CA",'1'&x"C1CB",'1'&x"C1CC",'1'&x"C1CD",'1'&x"C1CE",'1'&x"C1CF",
+--'1'&x"C1D0",'1'&x"C1D1",'1'&x"C1D2",'1'&x"C1D3",'1'&x"C1D4",'1'&x"C1D5",'1'&x"C1D6",'1'&x"C1D7",'1'&x"C1D8",'1'&x"C1D9",'1'&x"C1DA",'1'&x"C1DB",'1'&x"C1DC",'1'&x"C1DD",'1'&x"C1DE",'1'&x"C1DF",
+--'1'&x"C1E0",'1'&x"C1E1",'1'&x"C1E2",'1'&x"C1E3",'1'&x"C1E4",'1'&x"C1E5",'1'&x"C1E6",'1'&x"C1E7",'1'&x"C1E8",'1'&x"C1E9",'1'&x"C1EA",'1'&x"C1EB",'1'&x"C1EC",'1'&x"C1ED",'1'&x"C1EE",'1'&x"C1EF",
+--'1'&x"C1F0",'1'&x"C1F1",'1'&x"C1F2",'1'&x"C1F3",'1'&x"C1F4",'1'&x"C1F5",'1'&x"C1F6",'1'&x"C1F7",'1'&x"C1F8",'1'&x"C1F9",'1'&x"C1FA",'1'&x"C1FB",'1'&x"C1FC",'1'&x"C1FD",'1'&x"C1FE",'1'&x"C1FF",
+--'1'&x"C200",'1'&x"C201",'1'&x"C202",'1'&x"C203",'1'&x"C204",'1'&x"C205",'1'&x"C206",'1'&x"C207",'1'&x"C208",'1'&x"C209",'1'&x"C20A",'1'&x"C20B",'1'&x"C20C",'1'&x"C20D",'1'&x"C20E",'1'&x"C20F",
+--'1'&x"C210",'1'&x"C211",'1'&x"C212",'1'&x"C213",'1'&x"C214",'1'&x"C215",'1'&x"C216",'1'&x"C217",'1'&x"C218",'1'&x"C219",'1'&x"C21A",'1'&x"C21B",'1'&x"C21C",'1'&x"C21D",'1'&x"C21E",'1'&x"C21F",
+--'1'&x"C220",'1'&x"C221",'1'&x"C222",'1'&x"C223",'1'&x"C224",'1'&x"C225",'1'&x"C226",'1'&x"C227",'1'&x"C228",'1'&x"C229",'1'&x"C22A",'1'&x"C22B",'1'&x"C22C",'1'&x"C22D",'1'&x"C22E",'1'&x"C22F",
+--'1'&x"C230",'1'&x"C231",'1'&x"C232",'1'&x"C233",'1'&x"C234",'1'&x"C235",'1'&x"C236",'1'&x"C237",'1'&x"C238",'1'&x"C239",'1'&x"C23A",'1'&x"C23B",'1'&x"C23C",'1'&x"C23D",'1'&x"C23E",'1'&x"C23F",
+--'1'&x"C240",'1'&x"C241",'1'&x"C242",'1'&x"C243",'1'&x"C244",'1'&x"C245",'1'&x"C246",'1'&x"C247",'1'&x"C248",'1'&x"C249",'1'&x"C24A",'1'&x"C24B",'1'&x"C24C",'1'&x"C24D",'1'&x"C24E",'1'&x"C24F",
+--'1'&x"C250",'1'&x"C251",'1'&x"C252",'1'&x"C253",'1'&x"C254",'1'&x"C255",'1'&x"C256",'1'&x"C257",'1'&x"C258",'1'&x"C259",'1'&x"C25A",'1'&x"C25B",'1'&x"C25C",'1'&x"C25D",'1'&x"C25E",'1'&x"C25F",
+--'1'&x"C260",'1'&x"C261",'1'&x"C262",'1'&x"C263",'1'&x"C264",'1'&x"C265",'1'&x"C266",'1'&x"C267",'1'&x"C268",'1'&x"C269",'1'&x"C26A",'1'&x"C26B",'1'&x"C26C",'1'&x"C26D",'1'&x"C26E",'1'&x"C26F",
+--'1'&x"C270",'1'&x"C271",'1'&x"C272",'1'&x"C273",'1'&x"C274",'1'&x"C275",'1'&x"C276",'1'&x"C277",'1'&x"C278",'1'&x"C279",'1'&x"C27A",'1'&x"C27B",'1'&x"C27C",'1'&x"C27D",'1'&x"C27E",'1'&x"C27F",
+--'1'&x"C280",'1'&x"C281",'1'&x"C282",'1'&x"C283",'1'&x"C284",'1'&x"C285",'1'&x"C286",'1'&x"C287",'1'&x"C288",'1'&x"C289",'1'&x"C28A",'1'&x"C28B",'1'&x"C28C",'1'&x"C28D",'1'&x"C28E",'1'&x"C28F",
+--'1'&x"C290",'1'&x"C291",'1'&x"C292",'1'&x"C293",'1'&x"C294",'1'&x"C295",'1'&x"C296",'1'&x"C297",'1'&x"C298",'1'&x"C299",'1'&x"C29A",'1'&x"C29B",'1'&x"C29C",'1'&x"C29D",'1'&x"C29E",'1'&x"C29F",
+--'1'&x"C2A0",'1'&x"C2A1",'1'&x"C2A2",'1'&x"C2A3",'1'&x"C2A4",'1'&x"C2A5",'1'&x"C2A6",'1'&x"C2A7",'1'&x"C2A8",'1'&x"C2A9",'1'&x"C2AA",'1'&x"C2AB",'1'&x"C2AC",'1'&x"C2AD",'1'&x"C2AE",'1'&x"C2AF",
+--'1'&x"C2B0",'1'&x"C2B1",'1'&x"C2B2",'1'&x"C2B3",'1'&x"C2B4",'1'&x"C2B5",'1'&x"C2B6",'1'&x"C2B7",'1'&x"C2B8",'1'&x"C2B9",'1'&x"C2BA",'1'&x"C2BB",'1'&x"C2BC",'1'&x"C2BD",'1'&x"C2BE",'1'&x"C2BF",
+--'1'&x"C2C0",'1'&x"C2C1",'1'&x"C2C2",'1'&x"C2C3",'1'&x"C2C4",'1'&x"C2C5",'1'&x"C2C6",'1'&x"C2C7",'1'&x"C2C8",'1'&x"C2C9",'1'&x"C2CA",'1'&x"C2CB",'1'&x"C2CC",'1'&x"C2CD",'1'&x"C2CE",'1'&x"C2CF",
+--'1'&x"C2D0",'1'&x"C2D1",'1'&x"C2D2",'1'&x"C2D3",'1'&x"C2D4",'1'&x"C2D5",'1'&x"C2D6",'1'&x"C2D7",'1'&x"C2D8",'1'&x"C2D9",'1'&x"C2DA",'1'&x"C2DB",'1'&x"C2DC",'1'&x"C2DD",'1'&x"C2DE",'1'&x"C2DF",
+--'1'&x"C2E0",'1'&x"C2E1",'1'&x"C2E2",'1'&x"C2E3",'1'&x"C2E4",'1'&x"C2E5",'1'&x"C2E6",'1'&x"C2E7",'1'&x"C2E8",'1'&x"C2E9",'1'&x"C2EA",'1'&x"C2EB",'1'&x"C2EC",'1'&x"C2ED",'1'&x"C2EE",'1'&x"C2EF",
+--'1'&x"C2F0",'1'&x"C2F1",'1'&x"C2F2",'1'&x"C2F3",'1'&x"C2F4",'1'&x"C2F5",'1'&x"C2F6",'1'&x"C2F7",'1'&x"C2F8",'1'&x"C2F9",'1'&x"C2FA",'1'&x"C2FB",'1'&x"C2FC",'1'&x"C2FD",'1'&x"C2FE",'1'&x"C2FF",
+--'1'&x"C300",'1'&x"C301",'1'&x"C302",'1'&x"C303",'1'&x"C304",'1'&x"C305",'1'&x"C306",'1'&x"C307",'1'&x"C308",'1'&x"C309",'1'&x"C30A",'1'&x"C30B",'1'&x"C30C",'1'&x"C30D",'1'&x"C30E",'1'&x"C30F",
+--'1'&x"C310",'1'&x"C311",'1'&x"C312",'1'&x"C313",'1'&x"C314",'1'&x"C315",'1'&x"C316",'1'&x"C317",'1'&x"C318",'1'&x"C319",'1'&x"C31A",'1'&x"C31B",'1'&x"C31C",'1'&x"C31D",'1'&x"C31E",'1'&x"C31F",
+--'1'&x"C320",'1'&x"C321",'1'&x"C322",'1'&x"C323",'1'&x"C324",'1'&x"C325",'1'&x"C326",'1'&x"C327",'1'&x"C328",'1'&x"C329",'1'&x"C32A",'1'&x"C32B",'1'&x"C32C",'1'&x"C32D",'1'&x"C32E",'1'&x"C32F",
+--'1'&x"C330",'1'&x"C331",'1'&x"C332",'1'&x"C333",'1'&x"C334",'1'&x"C335",'1'&x"C336",'1'&x"C337",'1'&x"C338",'1'&x"C339",'1'&x"C33A",'1'&x"C33B",'1'&x"C33C",'1'&x"C33D",'1'&x"C33E",'1'&x"C33F",
+--'1'&x"C340",'1'&x"C341",'1'&x"C342",'1'&x"C343",'1'&x"C344",'1'&x"C345",'1'&x"C346",'1'&x"C347",'1'&x"C348",'1'&x"C349",'1'&x"C34A",'1'&x"C34B",'1'&x"C34C",'1'&x"C34D",'1'&x"C34E",'1'&x"C34F",
+--'1'&x"C350",'1'&x"C351",'1'&x"C352",'1'&x"C353",'1'&x"C354",'1'&x"C355",'1'&x"C356",'1'&x"C357",'1'&x"C358",'1'&x"C359",'1'&x"C35A",'1'&x"C35B",'1'&x"C35C",'1'&x"C35D",'1'&x"C35E",'1'&x"C35F",
+--'1'&x"C360",'1'&x"C361",'1'&x"C362",'1'&x"C363",'1'&x"C364",'1'&x"C365",'1'&x"C366",'1'&x"C367",'1'&x"C368",'1'&x"C369",'1'&x"C36A",'1'&x"C36B",'1'&x"C36C",'1'&x"C36D",'1'&x"C36E",'1'&x"C36F",
+--'1'&x"C370",'1'&x"C371",'1'&x"C372",'1'&x"C373",'1'&x"C374",'1'&x"C375",'1'&x"C376",'1'&x"C377",'1'&x"C378",'1'&x"C379",'1'&x"C37A",'1'&x"C37B",'1'&x"C37C",'1'&x"C37D",'1'&x"C37E",'1'&x"C37F",
+--'1'&x"C380",'1'&x"C381",'1'&x"C382",'1'&x"C383",'1'&x"C384",'1'&x"C385",'1'&x"C386",'1'&x"C387",'1'&x"C388",'1'&x"C389",'1'&x"C38A",'1'&x"C38B",'1'&x"C38C",'1'&x"C38D",'1'&x"C38E",'1'&x"C38F",
+--'1'&x"C390",'1'&x"C391",'1'&x"C392",'1'&x"C393",'1'&x"C394",'1'&x"C395",'1'&x"C396",'1'&x"C397",'1'&x"C398",'1'&x"C399",'1'&x"C39A",'1'&x"C39B",'1'&x"C39C",'1'&x"C39D",'1'&x"C39E",'1'&x"C39F",
+--'1'&x"C3A0",'1'&x"C3A1",'1'&x"C3A2",'1'&x"C3A3",'1'&x"C3A4",'1'&x"C3A5",'1'&x"C3A6",'1'&x"C3A7",'1'&x"C3A8",'1'&x"C3A9",'1'&x"C3AA",'1'&x"C3AB",'1'&x"C3AC",'1'&x"C3AD",'1'&x"C3AE",'1'&x"C3AF",
+--'1'&x"C3B0",'1'&x"C3B1",'1'&x"C3B2",'1'&x"C3B3",'1'&x"C3B4",'1'&x"C3B5",'1'&x"C3B6",'1'&x"C3B7",'1'&x"C3B8",'1'&x"C3B9",'1'&x"C3BA",'1'&x"C3BB",'1'&x"C3BC",'1'&x"C3BD",'1'&x"C3BE",'1'&x"C3BF",
+--'1'&x"C3C0",'1'&x"C3C1",'1'&x"C3C2",'1'&x"C3C3",'1'&x"C3C4",'1'&x"C3C5",'1'&x"C3C6",'1'&x"C3C7",'1'&x"C3C8",'1'&x"C3C9",'1'&x"C3CA",'1'&x"C3CB",'1'&x"C3CC",'1'&x"C3CD",'1'&x"C3CE",'1'&x"C3CF",
+--'1'&x"C3D0",'1'&x"C3D1",'1'&x"C3D2",'1'&x"C3D3",'1'&x"C3D4",'1'&x"C3D5",'1'&x"C3D6",'1'&x"C3D7",'1'&x"C3D8",'1'&x"C3D9",'1'&x"C3DA",'1'&x"C3DB",'1'&x"C3DC",'1'&x"C3DD",'1'&x"C3DE",'1'&x"C3DF",
+--'1'&x"C3E0",'1'&x"C3E1",'1'&x"C3E2",'1'&x"C3E3",'1'&x"C3E4",'1'&x"C3E5",'1'&x"C3E6",'1'&x"C3E7",'1'&x"C3E8",'1'&x"C3E9",'1'&x"C3EA",'1'&x"C3EB",'1'&x"C3EC",'1'&x"C3ED",'1'&x"C3EE",'1'&x"C3EF",
+--'1'&x"C3F0",'1'&x"C3F1",'1'&x"C3F2",'1'&x"C3F3",'1'&x"C3F4",'1'&x"C3F5",'1'&x"C3F6",'1'&x"C3F7",'1'&x"C3F8",'1'&x"C3F9",'1'&x"C3FA",'1'&x"C3FB",'1'&x"C3FC",'1'&x"C3FD",'1'&x"C3FE",'1'&x"C3FF",
+--'1'&x"C400",'1'&x"C401",'1'&x"C402",'1'&x"C403",'1'&x"C404",'1'&x"C405",'1'&x"C406",'1'&x"C407",'1'&x"C408",'1'&x"C409",'1'&x"C40A",'1'&x"C40B",'1'&x"C40C",'1'&x"C40D",'1'&x"C40E",'1'&x"C40F",
+--'1'&x"C410",'1'&x"C411",'1'&x"C412",'1'&x"C413",'1'&x"C414",'1'&x"C415",'1'&x"C416",'1'&x"C417",'1'&x"C418",'1'&x"C419",'1'&x"C41A",'1'&x"C41B",'1'&x"C41C",'1'&x"C41D",'1'&x"C41E",'1'&x"C41F",
+--'1'&x"C420",'1'&x"C421",'1'&x"C422",'1'&x"C423",'1'&x"C424",'1'&x"C425",'1'&x"C426",'1'&x"C427",'1'&x"C428",'1'&x"C429",'1'&x"C42A",'1'&x"C42B",'1'&x"C42C",'1'&x"C42D",'1'&x"C42E",'1'&x"C42F",
+--'1'&x"C430",'1'&x"C431",'1'&x"C432",'1'&x"C433",'1'&x"C434",'1'&x"C435",'1'&x"C436",'1'&x"C437",'1'&x"C438",'1'&x"C439",'1'&x"C43A",'1'&x"C43B",'1'&x"C43C",'1'&x"C43D",'1'&x"C43E",'1'&x"C43F",
+--'1'&x"C440",'1'&x"C441",'1'&x"C442",'1'&x"C443",'1'&x"C444",'1'&x"C445",'1'&x"C446",'1'&x"C447",'1'&x"C448",'1'&x"C449",'1'&x"C44A",'1'&x"C44B",'1'&x"C44C",'1'&x"C44D",'1'&x"C44E",'1'&x"C44F",
+--'1'&x"C450",'1'&x"C451",'1'&x"C452",'1'&x"C453",'1'&x"C454",'1'&x"C455",'1'&x"C456",'1'&x"C457",'1'&x"C458",'1'&x"C459",'1'&x"C45A",'1'&x"C45B",'1'&x"C45C",'1'&x"C45D",'1'&x"C45E",'1'&x"C45F",
+--'1'&x"C460",'1'&x"C461",'1'&x"C462",'1'&x"C463",'1'&x"C464",'1'&x"C465",'1'&x"C466",'1'&x"C467",'1'&x"C468",'1'&x"C469",'1'&x"C46A",'1'&x"C46B",'1'&x"C46C",'1'&x"C46D",'1'&x"C46E",'1'&x"C46F",
+--'1'&x"C470",'1'&x"C471",'1'&x"C472",'1'&x"C473",'1'&x"C474",'1'&x"C475",'1'&x"C476",'1'&x"C477",'1'&x"C478",'1'&x"C479",'1'&x"C47A",'1'&x"C47B",'1'&x"C47C",'1'&x"C47D",'1'&x"C47E",'1'&x"C47F",
+--'1'&x"C480",'1'&x"C481",'1'&x"C482",'1'&x"C483",'1'&x"C484",'1'&x"C485",'1'&x"C486",'1'&x"C487",'1'&x"C488",'1'&x"C489",'1'&x"C48A",'1'&x"C48B",'1'&x"C48C",'1'&x"C48D",'1'&x"C48E",'1'&x"C48F",
+--'1'&x"C490",'1'&x"C491",'1'&x"C492",'1'&x"C493",'1'&x"C494",'1'&x"C495",'1'&x"C496",'1'&x"C497",'1'&x"C498",'1'&x"C499",'1'&x"C49A",'1'&x"C49B",'1'&x"C49C",'1'&x"C49D",'1'&x"C49E",'1'&x"C49F",
+--'1'&x"C4A0",'1'&x"C4A1",'1'&x"C4A2",'1'&x"C4A3",'1'&x"C4A4",'1'&x"C4A5",'1'&x"C4A6",'1'&x"C4A7",'1'&x"C4A8",'1'&x"C4A9",'1'&x"C4AA",'1'&x"C4AB",'1'&x"C4AC",'1'&x"C4AD",'1'&x"C4AE",'1'&x"C4AF",
+--'1'&x"C4B0",'1'&x"C4B1",'1'&x"C4B2",'1'&x"C4B3",'1'&x"C4B4",'1'&x"C4B5",'1'&x"C4B6",'1'&x"C4B7",'1'&x"C4B8",'1'&x"C4B9",'1'&x"C4BA",'1'&x"C4BB",'1'&x"C4BC",'1'&x"C4BD",'1'&x"C4BE",'1'&x"C4BF",
+--'1'&x"C4C0",'1'&x"C4C1",'1'&x"C4C2",'1'&x"C4C3",'1'&x"C4C4",'1'&x"C4C5",'1'&x"C4C6",'1'&x"C4C7",'1'&x"C4C8",'1'&x"C4C9",'1'&x"C4CA",'1'&x"C4CB",'1'&x"C4CC",'1'&x"C4CD",'1'&x"C4CE",'1'&x"C4CF",
+--'1'&x"C4D0",'1'&x"C4D1",'1'&x"C4D2",'1'&x"C4D3",'1'&x"C4D4",'1'&x"C4D5",'1'&x"C4D6",'1'&x"C4D7",'1'&x"C4D8",'1'&x"C4D9",'1'&x"C4DA",'1'&x"C4DB",'1'&x"C4DC",'1'&x"C4DD",'1'&x"C4DE",'1'&x"C4DF",
+--'1'&x"C4E0",'1'&x"C4E1",'1'&x"C4E2",'1'&x"C4E3",'1'&x"C4E4",'1'&x"C4E5",'1'&x"C4E6",'1'&x"C4E7",'1'&x"C4E8",'1'&x"C4E9",'1'&x"C4EA",'1'&x"C4EB",'1'&x"C4EC",'1'&x"C4ED",'1'&x"C4EE",'1'&x"C4EF",
+--'1'&x"C4F0",'1'&x"C4F1",'1'&x"C4F2",'1'&x"C4F3",'1'&x"C4F4",'1'&x"C4F5",'1'&x"C4F6",'1'&x"C4F7",'1'&x"C4F8",'1'&x"C4F9",'1'&x"C4FA",'1'&x"C4FB",'1'&x"C4FC",'1'&x"C4FD",'1'&x"C4FE",'1'&x"C4FF",
+--'1'&x"C500",'1'&x"C501",'1'&x"C502",'1'&x"C503",'1'&x"C504",'1'&x"C505",'1'&x"C506",'1'&x"C507",'1'&x"C508",'1'&x"C509",'1'&x"C50A",'1'&x"C50B",'1'&x"C50C",'1'&x"C50D",'1'&x"C50E",'1'&x"C50F",
+--'1'&x"C510",'1'&x"C511",'1'&x"C512",'1'&x"C513",'1'&x"C514",'1'&x"C515",'1'&x"C516",'1'&x"C517",'1'&x"C518",'1'&x"C519",'1'&x"C51A",'1'&x"C51B",'1'&x"C51C",'1'&x"C51D",'1'&x"C51E",'1'&x"C51F",
+--'1'&x"C520",'1'&x"C521",'1'&x"C522",'1'&x"C523",'1'&x"C524",'1'&x"C525",'1'&x"C526",'1'&x"C527",'1'&x"C528",'1'&x"C529",'1'&x"C52A",'1'&x"C52B",'1'&x"C52C",'1'&x"C52D",'1'&x"C52E",'1'&x"C52F",
+--'1'&x"C530",'1'&x"C531",'1'&x"C532",'1'&x"C533",'1'&x"C534",'1'&x"C535",'1'&x"C536",'1'&x"C537",'1'&x"C538",'1'&x"C539",'1'&x"C53A",'1'&x"C53B",'1'&x"C53C",'1'&x"C53D",'1'&x"C53E",'1'&x"C53F",
+--'1'&x"C540",'1'&x"C541",'1'&x"C542",'1'&x"C543",'1'&x"C544",'1'&x"C545",'1'&x"C546",'1'&x"C547",'1'&x"C548",'1'&x"C549",'1'&x"C54A",'1'&x"C54B",'1'&x"C54C",'1'&x"C54D",'1'&x"C54E",'1'&x"C54F",
+--'1'&x"C550",'1'&x"C551",'1'&x"C552",'1'&x"C553",'1'&x"C554",'1'&x"C555",'1'&x"C556",'1'&x"C557",'1'&x"C558",'1'&x"C559",'1'&x"C55A",'1'&x"C55B",'1'&x"C55C",'1'&x"C55D",'1'&x"C55E",'1'&x"C55F",
+--'1'&x"C560",'1'&x"C561",'1'&x"C562",'1'&x"C563",'1'&x"C564",'1'&x"C565",'1'&x"C566",'1'&x"C567",'1'&x"C568",'1'&x"C569",'1'&x"C56A",'1'&x"C56B",'1'&x"C56C",'1'&x"C56D",'1'&x"C56E",'1'&x"C56F",
+--'1'&x"C570",'1'&x"C571",'1'&x"C572",'1'&x"C573",'1'&x"C574",'1'&x"C575",'1'&x"C576",'1'&x"C577",'1'&x"C578",'1'&x"C579",'1'&x"C57A",'1'&x"C57B",'1'&x"C57C",'1'&x"C57D",'1'&x"C57E",'1'&x"C57F",
+--'1'&x"C580",'1'&x"C581",'1'&x"C582",'1'&x"C583",'1'&x"C584",'1'&x"C585",'1'&x"C586",'1'&x"C587",'1'&x"C588",'1'&x"C589",'1'&x"C58A",'1'&x"C58B",'1'&x"C58C",'1'&x"C58D",'1'&x"C58E",'1'&x"C58F",
+--'1'&x"C590",'1'&x"C591",'1'&x"C592",'1'&x"C593",'1'&x"C594",'1'&x"C595",'1'&x"C596",'1'&x"C597",'1'&x"C598",'1'&x"C599",'1'&x"C59A",'1'&x"C59B",'1'&x"C59C",'1'&x"C59D",'1'&x"C59E",'1'&x"C59F",
+--'1'&x"C5A0",'1'&x"C5A1",'1'&x"C5A2",'1'&x"C5A3",'1'&x"C5A4",'1'&x"C5A5",'1'&x"C5A6",'1'&x"C5A7",'1'&x"C5A8",'1'&x"C5A9",'1'&x"C5AA",'1'&x"C5AB",'1'&x"C5AC",'1'&x"C5AD",'1'&x"C5AE",'1'&x"C5AF",
+--'1'&x"C5B0",'1'&x"C5B1",'1'&x"C5B2",'1'&x"C5B3",'1'&x"C5B4",'1'&x"C5B5",'1'&x"C5B6",'1'&x"C5B7",'1'&x"C5B8",'1'&x"C5B9",'1'&x"C5BA",'1'&x"C5BB",'1'&x"C5BC",'1'&x"C5BD",'1'&x"C5BE",'1'&x"C5BF",
+--'1'&x"C5C0",'1'&x"C5C1",'1'&x"C5C2",'1'&x"C5C3",'1'&x"C5C4",'1'&x"C5C5",'1'&x"C5C6",'1'&x"C5C7",'1'&x"C5C8",'1'&x"C5C9",'1'&x"C5CA",'1'&x"C5CB",'1'&x"C5CC",'1'&x"C5CD",'1'&x"C5CE",'1'&x"C5CF",
+--'1'&x"C5D0",'1'&x"C5D1",'1'&x"C5D2",'1'&x"C5D3",'1'&x"C5D4",'1'&x"C5D5",'1'&x"C5D6",'1'&x"C5D7",'1'&x"C5D8",'1'&x"C5D9",'1'&x"C5DA",'1'&x"C5DB",'1'&x"C5DC",'1'&x"C5DD",'1'&x"C5DE",'1'&x"C5DF",
+--'1'&x"C5E0",'1'&x"C5E1",'1'&x"C5E2",'1'&x"C5E3",'1'&x"C5E4",'1'&x"C5E5",'1'&x"C5E6",'1'&x"C5E7",'1'&x"C5E8",'1'&x"C5E9",'1'&x"C5EA",'1'&x"C5EB",'1'&x"C5EC",'1'&x"C5ED",'1'&x"C5EE",'1'&x"C5EF",
+--'1'&x"C5F0",'1'&x"C5F1",'1'&x"C5F2",'1'&x"C5F3",'1'&x"C5F4",'1'&x"C5F5",'1'&x"C5F6",'1'&x"C5F7",'1'&x"C5F8",'1'&x"C5F9",'1'&x"C5FA",'1'&x"C5FB",'1'&x"C5FC",'1'&x"C5FD",'1'&x"C5FE",'1'&x"C5FF",
+--'1'&x"C600",'1'&x"C601",'1'&x"C602",'1'&x"C603",'1'&x"C604",'1'&x"C605",'1'&x"C606",'1'&x"C607",'1'&x"C608",'1'&x"C609",'1'&x"C60A",'1'&x"C60B",'1'&x"C60C",'1'&x"C60D",'1'&x"C60E",'1'&x"C60F",
+--'1'&x"C610",'1'&x"C611",'1'&x"C612",'1'&x"C613",'1'&x"C614",'1'&x"C615",'1'&x"C616",'1'&x"C617",'1'&x"C618",'1'&x"C619",'1'&x"C61A",'1'&x"C61B",'1'&x"C61C",'1'&x"C61D",'1'&x"C61E",'1'&x"C61F",
+--'1'&x"C620",'1'&x"C621",'1'&x"C622",'1'&x"C623",'1'&x"C624",'1'&x"C625",'1'&x"C626",'1'&x"C627",'1'&x"C628",'1'&x"C629",'1'&x"C62A",'1'&x"C62B",'1'&x"C62C",'1'&x"C62D",'1'&x"C62E",'1'&x"C62F",
+--'1'&x"C630",'1'&x"C631",'1'&x"C632",'1'&x"C633",'1'&x"C634",'1'&x"C635",'1'&x"C636",'1'&x"C637",'1'&x"C638",'1'&x"C639",'1'&x"C63A",'1'&x"C63B",'1'&x"C63C",'1'&x"C63D",'1'&x"C63E",'1'&x"C63F",
+--'1'&x"C640",'1'&x"C641",'1'&x"C642",'1'&x"C643",'1'&x"C644",'1'&x"C645",'1'&x"C646",'1'&x"C647",'1'&x"C648",'1'&x"C649",'1'&x"C64A",'1'&x"C64B",'1'&x"C64C",'1'&x"C64D",'1'&x"C64E",'1'&x"C64F",
+--'1'&x"C650",'1'&x"C651",'1'&x"C652",'1'&x"C653",'1'&x"C654",'1'&x"C655",'1'&x"C656",'1'&x"C657",'1'&x"C658",'1'&x"C659",'1'&x"C65A",'1'&x"C65B",'1'&x"C65C",'1'&x"C65D",'1'&x"C65E",'1'&x"C65F",
+--'1'&x"C660",'1'&x"C661",'1'&x"C662",'1'&x"C663",'1'&x"C664",'1'&x"C665",'1'&x"C666",'1'&x"C667",'1'&x"C668",'1'&x"C669",'1'&x"C66A",'1'&x"C66B",'1'&x"C66C",'1'&x"C66D",'1'&x"C66E",'1'&x"C66F",
+--'1'&x"C670",'1'&x"C671",'1'&x"C672",'1'&x"C673",'1'&x"C674",'1'&x"C675",'1'&x"C676",'1'&x"C677",'1'&x"C678",'1'&x"C679",'1'&x"C67A",'1'&x"C67B",'1'&x"C67C",'1'&x"C67D",'1'&x"C67E",'1'&x"C67F",
+--'1'&x"C680",'1'&x"C681",'1'&x"C682",'1'&x"C683",'1'&x"C684",'1'&x"C685",'1'&x"C686",'1'&x"C687",'1'&x"C688",'1'&x"C689",'1'&x"C68A",'1'&x"C68B",'1'&x"C68C",'1'&x"C68D",'1'&x"C68E",'1'&x"C68F",
+--'1'&x"C690",'1'&x"C691",'1'&x"C692",'1'&x"C693",'1'&x"C694",'1'&x"C695",'1'&x"C696",'1'&x"C697",'1'&x"C698",'1'&x"C699",'1'&x"C69A",'1'&x"C69B",'1'&x"C69C",'1'&x"C69D",'1'&x"C69E",'1'&x"C69F",
+--'1'&x"C6A0",'1'&x"C6A1",'1'&x"C6A2",'1'&x"C6A3",'1'&x"C6A4",'1'&x"C6A5",'1'&x"C6A6",'1'&x"C6A7",'1'&x"C6A8",'1'&x"C6A9",'1'&x"C6AA",'1'&x"C6AB",'1'&x"C6AC",'1'&x"C6AD",'1'&x"C6AE",'1'&x"C6AF",
+--'1'&x"C6B0",'1'&x"C6B1",'1'&x"C6B2",'1'&x"C6B3",'1'&x"C6B4",'1'&x"C6B5",'1'&x"C6B6",'1'&x"C6B7",'1'&x"C6B8",'1'&x"C6B9",'1'&x"C6BA",'1'&x"C6BB",'1'&x"C6BC",'1'&x"C6BD",'1'&x"C6BE",'1'&x"C6BF",
+--'1'&x"C6C0",'1'&x"C6C1",'1'&x"C6C2",'1'&x"C6C3",'1'&x"C6C4",'1'&x"C6C5",'1'&x"C6C6",'1'&x"C6C7",'1'&x"C6C8",'1'&x"C6C9",'1'&x"C6CA",'1'&x"C6CB",'1'&x"C6CC",'1'&x"C6CD",'1'&x"C6CE",'1'&x"C6CF",
+--'1'&x"C6D0",'1'&x"C6D1",'1'&x"C6D2",'1'&x"C6D3",'1'&x"C6D4",'1'&x"C6D5",'1'&x"C6D6",'1'&x"C6D7",'1'&x"C6D8",'1'&x"C6D9",'1'&x"C6DA",'1'&x"C6DB",'1'&x"C6DC",'1'&x"C6DD",'1'&x"C6DE",'1'&x"C6DF",
+--'1'&x"C6E0",'1'&x"C6E1",'1'&x"C6E2",'1'&x"C6E3",'1'&x"C6E4",'1'&x"C6E5",'1'&x"C6E6",'1'&x"C6E7",'1'&x"C6E8",'1'&x"C6E9",'1'&x"C6EA",'1'&x"C6EB",'1'&x"C6EC",'1'&x"C6ED",'1'&x"C6EE",'1'&x"C6EF",
+--'1'&x"C6F0",'1'&x"C6F1",'1'&x"C6F2",'1'&x"C6F3",'1'&x"C6F4",'1'&x"C6F5",'1'&x"C6F6",'1'&x"C6F7",'1'&x"C6F8",'1'&x"C6F9",'1'&x"C6FA",'1'&x"C6FB",'1'&x"C6FC",'1'&x"C6FD",'1'&x"C6FE",'1'&x"C6FF",
+--'1'&x"C700",'1'&x"C701",'1'&x"C702",'1'&x"C703",'1'&x"C704",'1'&x"C705",'1'&x"C706",'1'&x"C707",'1'&x"C708",'1'&x"C709",'1'&x"C70A",'1'&x"C70B",'1'&x"C70C",'1'&x"C70D",'1'&x"C70E",'1'&x"C70F",
+--'1'&x"C710",'1'&x"C711",'1'&x"C712",'1'&x"C713",'1'&x"C714",'1'&x"C715",'1'&x"C716",'1'&x"C717",'1'&x"C718",'1'&x"C719",'1'&x"C71A",'1'&x"C71B",'1'&x"C71C",'1'&x"C71D",'1'&x"C71E",'1'&x"C71F",
+--'1'&x"C720",'1'&x"C721",'1'&x"C722",'1'&x"C723",'1'&x"C724",'1'&x"C725",'1'&x"C726",'1'&x"C727",'1'&x"C728",'1'&x"C729",'1'&x"C72A",'1'&x"C72B",'1'&x"C72C",'1'&x"C72D",'1'&x"C72E",'1'&x"C72F",
+--'1'&x"C730",'1'&x"C731",'1'&x"C732",'1'&x"C733",'1'&x"C734",'1'&x"C735",'1'&x"C736",'1'&x"C737",'1'&x"C738",'1'&x"C739",'1'&x"C73A",'1'&x"C73B",'1'&x"C73C",'1'&x"C73D",'1'&x"C73E",'1'&x"C73F",
+--'1'&x"C740",'1'&x"C741",'1'&x"C742",'1'&x"C743",'1'&x"C744",'1'&x"C745",'1'&x"C746",'1'&x"C747",'1'&x"C748",'1'&x"C749",'1'&x"C74A",'1'&x"C74B",'1'&x"C74C",'1'&x"C74D",'1'&x"C74E",'1'&x"C74F",
+--'1'&x"C750",'1'&x"C751",'1'&x"C752",'1'&x"C753",'1'&x"C754",'1'&x"C755",'1'&x"C756",'1'&x"C757",'1'&x"C758",'1'&x"C759",'1'&x"C75A",'1'&x"C75B",'1'&x"C75C",'1'&x"C75D",'1'&x"C75E",'1'&x"C75F",
+--'1'&x"C760",'1'&x"C761",'1'&x"C762",'1'&x"C763",'1'&x"C764",'1'&x"C765",'1'&x"C766",'1'&x"C767",'1'&x"C768",'1'&x"C769",'1'&x"C76A",'1'&x"C76B",'1'&x"C76C",'1'&x"C76D",'1'&x"C76E",'1'&x"C76F",
+--'1'&x"C770",'1'&x"C771",'1'&x"C772",'1'&x"C773",'1'&x"C774",'1'&x"C775",'1'&x"C776",'1'&x"C777",'1'&x"C778",'1'&x"C779",'1'&x"C77A",'1'&x"C77B",'1'&x"C77C",'1'&x"C77D",'1'&x"C77E",'1'&x"C77F",
+--'1'&x"C780",'1'&x"C781",'1'&x"C782",'1'&x"C783",'1'&x"C784",'1'&x"C785",'1'&x"C786",'1'&x"C787",'1'&x"C788",'1'&x"C789",'1'&x"C78A",'1'&x"C78B",'1'&x"C78C",'1'&x"C78D",'1'&x"C78E",'1'&x"C78F",
+--'1'&x"C790",'1'&x"C791",'1'&x"C792",'1'&x"C793",'1'&x"C794",'1'&x"C795",'1'&x"C796",'1'&x"C797",'1'&x"C798",'1'&x"C799",'1'&x"C79A",'1'&x"C79B",'1'&x"C79C",'1'&x"C79D",'1'&x"C79E",'1'&x"C79F",
+--'1'&x"C7A0",'1'&x"C7A1",'1'&x"C7A2",'1'&x"C7A3",'1'&x"C7A4",'1'&x"C7A5",'1'&x"C7A6",'1'&x"C7A7",'1'&x"C7A8",'1'&x"C7A9",'1'&x"C7AA",'1'&x"C7AB",'1'&x"C7AC",'1'&x"C7AD",'1'&x"C7AE",'1'&x"C7AF",
+--'1'&x"C7B0",'1'&x"C7B1",'1'&x"C7B2",'1'&x"C7B3",'1'&x"C7B4",'1'&x"C7B5",'1'&x"C7B6",'1'&x"C7B7",'1'&x"C7B8",'1'&x"C7B9",'1'&x"C7BA",'1'&x"C7BB",'1'&x"C7BC",'1'&x"C7BD",'1'&x"C7BE",'1'&x"C7BF",
+--'1'&x"C7C0",'1'&x"C7C1",'1'&x"C7C2",'1'&x"C7C3",'1'&x"C7C4",'1'&x"C7C5",'1'&x"C7C6",'1'&x"C7C7",'1'&x"C7C8",'1'&x"C7C9",'1'&x"C7CA",'1'&x"C7CB",'1'&x"C7CC",'1'&x"C7CD",'1'&x"C7CE",'1'&x"C7CF",
+--'1'&x"C7D0",'1'&x"C7D1",'1'&x"C7D2",'1'&x"C7D3",'1'&x"C7D4",'1'&x"C7D5",'1'&x"C7D6",'1'&x"C7D7",'1'&x"C7D8",'1'&x"C7D9",'1'&x"C7DA",'1'&x"C7DB",'1'&x"C7DC",'1'&x"C7DD",'1'&x"C7DE",'1'&x"C7DF",
+--'1'&x"C7E0",'1'&x"C7E1",'1'&x"C7E2",'1'&x"C7E3",'1'&x"C7E4",'1'&x"C7E5",'1'&x"C7E6",'1'&x"C7E7",'1'&x"C7E8",'1'&x"C7E9",'1'&x"C7EA",'1'&x"C7EB",'1'&x"C7EC",'1'&x"C7ED",'1'&x"C7EE",'1'&x"C7EF",
+--'1'&x"C7F0",'1'&x"C7F1",'1'&x"C7F2",'1'&x"C7F3",'1'&x"C7F4",'1'&x"C7F5",'1'&x"C7F6",'1'&x"C7F7",'1'&x"C7F8",'1'&x"C7F9",'1'&x"C7FA",'1'&x"C7FB",'1'&x"C7FC",'1'&x"C7FD",'1'&x"C7FE",'1'&x"C7FF",
+--'1'&x"C800",'1'&x"C801",'1'&x"C802",'1'&x"C803",'1'&x"C804",'1'&x"C805",'1'&x"C806",'1'&x"C807",'1'&x"C808",'1'&x"C809",'1'&x"C80A",'1'&x"C80B",'1'&x"C80C",'1'&x"C80D",'1'&x"C80E",'1'&x"C80F",
+--'1'&x"C810",'1'&x"C811",'1'&x"C812",'1'&x"C813",'1'&x"C814",'1'&x"C815",'1'&x"C816",'1'&x"C817",'1'&x"C818",'1'&x"C819",'1'&x"C81A",'1'&x"C81B",'1'&x"C81C",'1'&x"C81D",'1'&x"C81E",'1'&x"C81F",
+--'1'&x"C820",'1'&x"C821",'1'&x"C822",'1'&x"C823",'1'&x"C824",'1'&x"C825",'1'&x"C826",'1'&x"C827",'1'&x"C828",'1'&x"C829",'1'&x"C82A",'1'&x"C82B",'1'&x"C82C",'1'&x"C82D",'1'&x"C82E",'1'&x"C82F",
+--'1'&x"C830",'1'&x"C831",'1'&x"C832",'1'&x"C833",'1'&x"C834",'1'&x"C835",'1'&x"C836",'1'&x"C837",'1'&x"C838",'1'&x"C839",'1'&x"C83A",'1'&x"C83B",'1'&x"C83C",'1'&x"C83D",'1'&x"C83E",'1'&x"C83F",
+--'1'&x"C840",'1'&x"C841",'1'&x"C842",'1'&x"C843",'1'&x"C844",'1'&x"C845",'1'&x"C846",'1'&x"C847",'1'&x"C848",'1'&x"C849",'1'&x"C84A",'1'&x"C84B",'1'&x"C84C",'1'&x"C84D",'1'&x"C84E",'1'&x"C84F",
+--'1'&x"C850",'1'&x"C851",'1'&x"C852",'1'&x"C853",'1'&x"C854",'1'&x"C855",'1'&x"C856",'1'&x"C857",'1'&x"C858",'1'&x"C859",'1'&x"C85A",'1'&x"C85B",'1'&x"C85C",'1'&x"C85D",'1'&x"C85E",'1'&x"C85F",
+--'1'&x"C860",'1'&x"C861",'1'&x"C862",'1'&x"C863",'1'&x"C864",'1'&x"C865",'1'&x"C866",'1'&x"C867",'1'&x"C868",'1'&x"C869",'1'&x"C86A",'1'&x"C86B",'1'&x"C86C",'1'&x"C86D",'1'&x"C86E",'1'&x"C86F",
+--'1'&x"C870",'1'&x"C871",'1'&x"C872",'1'&x"C873",'1'&x"C874",'1'&x"C875",'1'&x"C876",'1'&x"C877",'1'&x"C878",'1'&x"C879",'1'&x"C87A",'1'&x"C87B",'1'&x"C87C",'1'&x"C87D",'1'&x"C87E",'1'&x"C87F",
+--'1'&x"C880",'1'&x"C881",'1'&x"C882",'1'&x"C883",'1'&x"C884",'1'&x"C885",'1'&x"C886",'1'&x"C887",'1'&x"C888",'1'&x"C889",'1'&x"C88A",'1'&x"C88B",'1'&x"C88C",'1'&x"C88D",'1'&x"C88E",'1'&x"C88F",
+--'1'&x"C890",'1'&x"C891",'1'&x"C892",'1'&x"C893",'1'&x"C894",'1'&x"C895",'1'&x"C896",'1'&x"C897",'1'&x"C898",'1'&x"C899",'1'&x"C89A",'1'&x"C89B",'1'&x"C89C",'1'&x"C89D",'1'&x"C89E",'1'&x"C89F",
+--'1'&x"C8A0",'1'&x"C8A1",'1'&x"C8A2",'1'&x"C8A3",'1'&x"C8A4",'1'&x"C8A5",'1'&x"C8A6",'1'&x"C8A7",'1'&x"C8A8",'1'&x"C8A9",'1'&x"C8AA",'1'&x"C8AB",'1'&x"C8AC",'1'&x"C8AD",'1'&x"C8AE",'1'&x"C8AF",
+--'1'&x"C8B0",'1'&x"C8B1",'1'&x"C8B2",'1'&x"C8B3",'1'&x"C8B4",'1'&x"C8B5",'1'&x"C8B6",'1'&x"C8B7",'1'&x"C8B8",'1'&x"C8B9",'1'&x"C8BA",'1'&x"C8BB",'1'&x"C8BC",'1'&x"C8BD",'1'&x"C8BE",'1'&x"C8BF",
+--'1'&x"C8C0",'1'&x"C8C1",'1'&x"C8C2",'1'&x"C8C3",'1'&x"C8C4",'1'&x"C8C5",'1'&x"C8C6",'1'&x"C8C7",'1'&x"C8C8",'1'&x"C8C9",'1'&x"C8CA",'1'&x"C8CB",'1'&x"C8CC",'1'&x"C8CD",'1'&x"C8CE",'1'&x"C8CF",
+--'1'&x"C8D0",'1'&x"C8D1",'1'&x"C8D2",'1'&x"C8D3",'1'&x"C8D4",'1'&x"C8D5",'1'&x"C8D6",'1'&x"C8D7",'1'&x"C8D8",'1'&x"C8D9",'1'&x"C8DA",'1'&x"C8DB",'1'&x"C8DC",'1'&x"C8DD",'1'&x"C8DE",'1'&x"C8DF",
+--'1'&x"C8E0",'1'&x"C8E1",'1'&x"C8E2",'1'&x"C8E3",'1'&x"C8E4",'1'&x"C8E5",'1'&x"C8E6",'1'&x"C8E7",'1'&x"C8E8",'1'&x"C8E9",'1'&x"C8EA",'1'&x"C8EB",'1'&x"C8EC",'1'&x"C8ED",'1'&x"C8EE",'1'&x"C8EF",
+--'1'&x"C8F0",'1'&x"C8F1",'1'&x"C8F2",'1'&x"C8F3",'1'&x"C8F4",'1'&x"C8F5",'1'&x"C8F6",'1'&x"C8F7",'1'&x"C8F8",'1'&x"C8F9",'1'&x"C8FA",'1'&x"C8FB",'1'&x"C8FC",'1'&x"C8FD",'1'&x"C8FE",'1'&x"C8FF",
+--'1'&x"C900",'1'&x"C901",'1'&x"C902",'1'&x"C903",'1'&x"C904",'1'&x"C905",'1'&x"C906",'1'&x"C907",'1'&x"C908",'1'&x"C909",'1'&x"C90A",'1'&x"C90B",'1'&x"C90C",'1'&x"C90D",'1'&x"C90E",'1'&x"C90F",
+--'1'&x"C910",'1'&x"C911",'1'&x"C912",'1'&x"C913",'1'&x"C914",'1'&x"C915",'1'&x"C916",'1'&x"C917",'1'&x"C918",'1'&x"C919",'1'&x"C91A",'1'&x"C91B",'1'&x"C91C",'1'&x"C91D",'1'&x"C91E",'1'&x"C91F",
+--'1'&x"C920",'1'&x"C921",'1'&x"C922",'1'&x"C923",'1'&x"C924",'1'&x"C925",'1'&x"C926",'1'&x"C927",'1'&x"C928",'1'&x"C929",'1'&x"C92A",'1'&x"C92B",'1'&x"C92C",'1'&x"C92D",'1'&x"C92E",'1'&x"C92F",
+--'1'&x"C930",'1'&x"C931",'1'&x"C932",'1'&x"C933",'1'&x"C934",'1'&x"C935",'1'&x"C936",'1'&x"C937",'1'&x"C938",'1'&x"C939",'1'&x"C93A",'1'&x"C93B",'1'&x"C93C",'1'&x"C93D",'1'&x"C93E",'1'&x"C93F",
+--'1'&x"C940",'1'&x"C941",'1'&x"C942",'1'&x"C943",'1'&x"C944",'1'&x"C945",'1'&x"C946",'1'&x"C947",'1'&x"C948",'1'&x"C949",'1'&x"C94A",'1'&x"C94B",'1'&x"C94C",'1'&x"C94D",'1'&x"C94E",'1'&x"C94F",
+--'1'&x"C950",'1'&x"C951",'1'&x"C952",'1'&x"C953",'1'&x"C954",'1'&x"C955",'1'&x"C956",'1'&x"C957",'1'&x"C958",'1'&x"C959",'1'&x"C95A",'1'&x"C95B",'1'&x"C95C",'1'&x"C95D",'1'&x"C95E",'1'&x"C95F",
+--'1'&x"C960",'1'&x"C961",'1'&x"C962",'1'&x"C963",'1'&x"C964",'1'&x"C965",'1'&x"C966",'1'&x"C967",'1'&x"C968",'1'&x"C969",'1'&x"C96A",'1'&x"C96B",'1'&x"C96C",'1'&x"C96D",'1'&x"C96E",'1'&x"C96F",
+--'1'&x"C970",'1'&x"C971",'1'&x"C972",'1'&x"C973",'1'&x"C974",'1'&x"C975",'1'&x"C976",'1'&x"C977",'1'&x"C978",'1'&x"C979",'1'&x"C97A",'1'&x"C97B",'1'&x"C97C",'1'&x"C97D",'1'&x"C97E",'1'&x"C97F",
+--'1'&x"C980",'1'&x"C981",'1'&x"C982",'1'&x"C983",'1'&x"C984",'1'&x"C985",'1'&x"C986",'1'&x"C987",'1'&x"C988",'1'&x"C989",'1'&x"C98A",'1'&x"C98B",'1'&x"C98C",'1'&x"C98D",'1'&x"C98E",'1'&x"C98F",
+--'1'&x"C990",'1'&x"C991",'1'&x"C992",'1'&x"C993",'1'&x"C994",'1'&x"C995",'1'&x"C996",'1'&x"C997",'1'&x"C998",'1'&x"C999",'1'&x"C99A",'1'&x"C99B",'1'&x"C99C",'1'&x"C99D",'1'&x"C99E",'1'&x"C99F",
+--'1'&x"C9A0",'1'&x"C9A1",'1'&x"C9A2",'1'&x"C9A3",'1'&x"C9A4",'1'&x"C9A5",'1'&x"C9A6",'1'&x"C9A7",'1'&x"C9A8",'1'&x"C9A9",'1'&x"C9AA",'1'&x"C9AB",'1'&x"C9AC",'1'&x"C9AD",'1'&x"C9AE",'1'&x"C9AF",
+--'1'&x"C9B0",'1'&x"C9B1",'1'&x"C9B2",'1'&x"C9B3",'1'&x"C9B4",'1'&x"C9B5",'1'&x"C9B6",'1'&x"C9B7",'1'&x"C9B8",'1'&x"C9B9",'1'&x"C9BA",'1'&x"C9BB",'1'&x"C9BC",'1'&x"C9BD",'1'&x"C9BE",'1'&x"C9BF",
+--'1'&x"C9C0",'1'&x"C9C1",'1'&x"C9C2",'1'&x"C9C3",'1'&x"C9C4",'1'&x"C9C5",'1'&x"C9C6",'1'&x"C9C7",'1'&x"C9C8",'1'&x"C9C9",'1'&x"C9CA",'1'&x"C9CB",'1'&x"C9CC",'1'&x"C9CD",'1'&x"C9CE",'1'&x"C9CF",
+--'1'&x"C9D0",'1'&x"C9D1",'1'&x"C9D2",'1'&x"C9D3",'1'&x"C9D4",'1'&x"C9D5",'1'&x"C9D6",'1'&x"C9D7",'1'&x"C9D8",'1'&x"C9D9",'1'&x"C9DA",'1'&x"C9DB",'1'&x"C9DC",'1'&x"C9DD",'1'&x"C9DE",'1'&x"C9DF",
+--'1'&x"C9E0",'1'&x"C9E1",'1'&x"C9E2",'1'&x"C9E3",'1'&x"C9E4",'1'&x"C9E5",'1'&x"C9E6",'1'&x"C9E7",'1'&x"C9E8",'1'&x"C9E9",'1'&x"C9EA",'1'&x"C9EB",'1'&x"C9EC",'1'&x"C9ED",'1'&x"C9EE",'1'&x"C9EF",
+--'1'&x"C9F0",'1'&x"C9F1",'1'&x"C9F2",'1'&x"C9F3",'1'&x"C9F4",'1'&x"C9F5",'1'&x"C9F6",'1'&x"C9F7",'1'&x"C9F8",'1'&x"C9F9",'1'&x"C9FA",'1'&x"C9FB",'1'&x"C9FC",'1'&x"C9FD",'1'&x"C9FE",'1'&x"C9FF",
+--'1'&x"CA00",'1'&x"CA01",'1'&x"CA02",'1'&x"CA03",'1'&x"CA04",'1'&x"CA05",'1'&x"CA06",'1'&x"CA07",'1'&x"CA08",'1'&x"CA09",'1'&x"CA0A",'1'&x"CA0B",'1'&x"CA0C",'1'&x"CA0D",'1'&x"CA0E",'1'&x"CA0F",
+--'1'&x"CA10",'1'&x"CA11",'1'&x"CA12",'1'&x"CA13",'1'&x"CA14",'1'&x"CA15",'1'&x"CA16",'1'&x"CA17",'1'&x"CA18",'1'&x"CA19",'1'&x"CA1A",'1'&x"CA1B",'1'&x"CA1C",'1'&x"CA1D",'1'&x"CA1E",'1'&x"CA1F",
+--'1'&x"CA20",'1'&x"CA21",'1'&x"CA22",'1'&x"CA23",'1'&x"CA24",'1'&x"CA25",'1'&x"CA26",'1'&x"CA27",'1'&x"CA28",'1'&x"CA29",'1'&x"CA2A",'1'&x"CA2B",'1'&x"CA2C",'1'&x"CA2D",'1'&x"CA2E",'1'&x"CA2F",
+--'1'&x"CA30",'1'&x"CA31",'1'&x"CA32",'1'&x"CA33",'1'&x"CA34",'1'&x"CA35",'1'&x"CA36",'1'&x"CA37",'1'&x"CA38",'1'&x"CA39",'1'&x"CA3A",'1'&x"CA3B",'1'&x"CA3C",'1'&x"CA3D",'1'&x"CA3E",'1'&x"CA3F",
+--'1'&x"CA40",'1'&x"CA41",'1'&x"CA42",'1'&x"CA43",'1'&x"CA44",'1'&x"CA45",'1'&x"CA46",'1'&x"CA47",'1'&x"CA48",'1'&x"CA49",'1'&x"CA4A",'1'&x"CA4B",'1'&x"CA4C",'1'&x"CA4D",'1'&x"CA4E",'1'&x"CA4F",
+--'1'&x"CA50",'1'&x"CA51",'1'&x"CA52",'1'&x"CA53",'1'&x"CA54",'1'&x"CA55",'1'&x"CA56",'1'&x"CA57",'1'&x"CA58",'1'&x"CA59",'1'&x"CA5A",'1'&x"CA5B",'1'&x"CA5C",'1'&x"CA5D",'1'&x"CA5E",'1'&x"CA5F",
+--'1'&x"CA60",'1'&x"CA61",'1'&x"CA62",'1'&x"CA63",'1'&x"CA64",'1'&x"CA65",'1'&x"CA66",'1'&x"CA67",'1'&x"CA68",'1'&x"CA69",'1'&x"CA6A",'1'&x"CA6B",'1'&x"CA6C",'1'&x"CA6D",'1'&x"CA6E",'1'&x"CA6F",
+--'1'&x"CA70",'1'&x"CA71",'1'&x"CA72",'1'&x"CA73",'1'&x"CA74",'1'&x"CA75",'1'&x"CA76",'1'&x"CA77",'1'&x"CA78",'1'&x"CA79",'1'&x"CA7A",'1'&x"CA7B",'1'&x"CA7C",'1'&x"CA7D",'1'&x"CA7E",'1'&x"CA7F",
+--'1'&x"CA80",'1'&x"CA81",'1'&x"CA82",'1'&x"CA83",'1'&x"CA84",'1'&x"CA85",'1'&x"CA86",'1'&x"CA87",'1'&x"CA88",'1'&x"CA89",'1'&x"CA8A",'1'&x"CA8B",'1'&x"CA8C",'1'&x"CA8D",'1'&x"CA8E",'1'&x"CA8F",
+--'1'&x"CA90",'1'&x"CA91",'1'&x"CA92",'1'&x"CA93",'1'&x"CA94",'1'&x"CA95",'1'&x"CA96",'1'&x"CA97",'1'&x"CA98",'1'&x"CA99",'1'&x"CA9A",'1'&x"CA9B",'1'&x"CA9C",'1'&x"CA9D",'1'&x"CA9E",'1'&x"CA9F",
+--'1'&x"CAA0",'1'&x"CAA1",'1'&x"CAA2",'1'&x"CAA3",'1'&x"CAA4",'1'&x"CAA5",'1'&x"CAA6",'1'&x"CAA7",'1'&x"CAA8",'1'&x"CAA9",'1'&x"CAAA",'1'&x"CAAB",'1'&x"CAAC",'1'&x"CAAD",'1'&x"CAAE",'1'&x"CAAF",
+--'1'&x"CAB0",'1'&x"CAB1",'1'&x"CAB2",'1'&x"CAB3",'1'&x"CAB4",'1'&x"CAB5",'1'&x"CAB6",'1'&x"CAB7",'1'&x"CAB8",'1'&x"CAB9",'1'&x"CABA",'1'&x"CABB",'1'&x"CABC",'1'&x"CABD",'1'&x"CABE",'1'&x"CABF",
+--'1'&x"CAC0",'1'&x"CAC1",'1'&x"CAC2",'1'&x"CAC3",'1'&x"CAC4",'1'&x"CAC5",'1'&x"CAC6",'1'&x"CAC7",'1'&x"CAC8",'1'&x"CAC9",'1'&x"CACA",'1'&x"CACB",'1'&x"CACC",'1'&x"CACD",'1'&x"CACE",'1'&x"CACF",
+--'1'&x"CAD0",'1'&x"CAD1",'1'&x"CAD2",'1'&x"CAD3",'1'&x"CAD4",'1'&x"CAD5",'1'&x"CAD6",'1'&x"CAD7",'1'&x"CAD8",'1'&x"CAD9",'1'&x"CADA",'1'&x"CADB",'1'&x"CADC",'1'&x"CADD",'1'&x"CADE",'1'&x"CADF",
+--'1'&x"CAE0",'1'&x"CAE1",'1'&x"CAE2",'1'&x"CAE3",'1'&x"CAE4",'1'&x"CAE5",'1'&x"CAE6",'1'&x"CAE7",'1'&x"CAE8",'1'&x"CAE9",'1'&x"CAEA",'1'&x"CAEB",'1'&x"CAEC",'1'&x"CAED",'1'&x"CAEE",'1'&x"CAEF",
+--'1'&x"CAF0",'1'&x"CAF1",'1'&x"CAF2",'1'&x"CAF3",'1'&x"CAF4",'1'&x"CAF5",'1'&x"CAF6",'1'&x"CAF7",'1'&x"CAF8",'1'&x"CAF9",'1'&x"CAFA",'1'&x"CAFB",'1'&x"CAFC",'1'&x"CAFD",'1'&x"CAFE",'1'&x"CAFF",
+--'1'&x"CB00",'1'&x"CB01",'1'&x"CB02",'1'&x"CB03",'1'&x"CB04",'1'&x"CB05",'1'&x"CB06",'1'&x"CB07",'1'&x"CB08",'1'&x"CB09",'1'&x"CB0A",'1'&x"CB0B",'1'&x"CB0C",'1'&x"CB0D",'1'&x"CB0E",'1'&x"CB0F",
+--'1'&x"CB10",'1'&x"CB11",'1'&x"CB12",'1'&x"CB13",'1'&x"CB14",'1'&x"CB15",'1'&x"CB16",'1'&x"CB17",'1'&x"CB18",'1'&x"CB19",'1'&x"CB1A",'1'&x"CB1B",'1'&x"CB1C",'1'&x"CB1D",'1'&x"CB1E",'1'&x"CB1F",
+--'1'&x"CB20",'1'&x"CB21",'1'&x"CB22",'1'&x"CB23",'1'&x"CB24",'1'&x"CB25",'1'&x"CB26",'1'&x"CB27",'1'&x"CB28",'1'&x"CB29",'1'&x"CB2A",'1'&x"CB2B",'1'&x"CB2C",'1'&x"CB2D",'1'&x"CB2E",'1'&x"CB2F",
+--'1'&x"CB30",'1'&x"CB31",'1'&x"CB32",'1'&x"CB33",'1'&x"CB34",'1'&x"CB35",'1'&x"CB36",'1'&x"CB37",'1'&x"CB38",'1'&x"CB39",'1'&x"CB3A",'1'&x"CB3B",'1'&x"CB3C",'1'&x"CB3D",'1'&x"CB3E",'1'&x"CB3F",
+--'1'&x"CB40",'1'&x"CB41",'1'&x"CB42",'1'&x"CB43",'1'&x"CB44",'1'&x"CB45",'1'&x"CB46",'1'&x"CB47",'1'&x"CB48",'1'&x"CB49",'1'&x"CB4A",'1'&x"CB4B",'1'&x"CB4C",'1'&x"CB4D",'1'&x"CB4E",'1'&x"CB4F",
+--'1'&x"CB50",'1'&x"CB51",'1'&x"CB52",'1'&x"CB53",'1'&x"CB54",'1'&x"CB55",'1'&x"CB56",'1'&x"CB57",'1'&x"CB58",'1'&x"CB59",'1'&x"CB5A",'1'&x"CB5B",'1'&x"CB5C",'1'&x"CB5D",'1'&x"CB5E",'1'&x"CB5F",
+--'1'&x"CB60",'1'&x"CB61",'1'&x"CB62",'1'&x"CB63",'1'&x"CB64",'1'&x"CB65",'1'&x"CB66",'1'&x"CB67",'1'&x"CB68",'1'&x"CB69",'1'&x"CB6A",'1'&x"CB6B",'1'&x"CB6C",'1'&x"CB6D",'1'&x"CB6E",'1'&x"CB6F",
+--'1'&x"CB70",'1'&x"CB71",'1'&x"CB72",'1'&x"CB73",'1'&x"CB74",'1'&x"CB75",'1'&x"CB76",'1'&x"CB77",'1'&x"CB78",'1'&x"CB79",'1'&x"CB7A",'1'&x"CB7B",'1'&x"CB7C",'1'&x"CB7D",'1'&x"CB7E",'1'&x"CB7F",
+--'1'&x"CB80",'1'&x"CB81",'1'&x"CB82",'1'&x"CB83",'1'&x"CB84",'1'&x"CB85",'1'&x"CB86",'1'&x"CB87",'1'&x"CB88",'1'&x"CB89",'1'&x"CB8A",'1'&x"CB8B",'1'&x"CB8C",'1'&x"CB8D",'1'&x"CB8E",'1'&x"CB8F",
+--'1'&x"CB90",'1'&x"CB91",'1'&x"CB92",'1'&x"CB93",'1'&x"CB94",'1'&x"CB95",'1'&x"CB96",'1'&x"CB97",'1'&x"CB98",'1'&x"CB99",'1'&x"CB9A",'1'&x"CB9B",'1'&x"CB9C",'1'&x"CB9D",'1'&x"CB9E",'1'&x"CB9F",
+--'1'&x"CBA0",'1'&x"CBA1",'1'&x"CBA2",'1'&x"CBA3",'1'&x"CBA4",'1'&x"CBA5",'1'&x"CBA6",'1'&x"CBA7",'1'&x"CBA8",'1'&x"CBA9",'1'&x"CBAA",'1'&x"CBAB",'1'&x"CBAC",'1'&x"CBAD",'1'&x"CBAE",'1'&x"CBAF",
+--'1'&x"CBB0",'1'&x"CBB1",'1'&x"CBB2",'1'&x"CBB3",'1'&x"CBB4",'1'&x"CBB5",'1'&x"CBB6",'1'&x"CBB7",'1'&x"CBB8",'1'&x"CBB9",'1'&x"CBBA",'1'&x"CBBB",'1'&x"CBBC",'1'&x"CBBD",'1'&x"CBBE",'1'&x"CBBF",
+--'1'&x"CBC0",'1'&x"CBC1",'1'&x"CBC2",'1'&x"CBC3",'1'&x"CBC4",'1'&x"CBC5",'1'&x"CBC6",'1'&x"CBC7",'1'&x"CBC8",'1'&x"CBC9",'1'&x"CBCA",'1'&x"CBCB",'1'&x"CBCC",'1'&x"CBCD",'1'&x"CBCE",'1'&x"CBCF",
+--'1'&x"CBD0",'1'&x"CBD1",'1'&x"CBD2",'1'&x"CBD3",'1'&x"CBD4",'1'&x"CBD5",'1'&x"CBD6",'1'&x"CBD7",'1'&x"CBD8",'1'&x"CBD9",'1'&x"CBDA",'1'&x"CBDB",'1'&x"CBDC",'1'&x"CBDD",'1'&x"CBDE",'1'&x"CBDF",
+--'1'&x"CBE0",'1'&x"CBE1",'1'&x"CBE2",'1'&x"CBE3",'1'&x"CBE4",'1'&x"CBE5",'1'&x"CBE6",'1'&x"CBE7",'1'&x"CBE8",'1'&x"CBE9",'1'&x"CBEA",'1'&x"CBEB",'1'&x"CBEC",'1'&x"CBED",'1'&x"CBEE",'1'&x"CBEF",
+--'1'&x"CBF0",'1'&x"CBF1",'1'&x"CBF2",'1'&x"CBF3",'1'&x"CBF4",'1'&x"CBF5",'1'&x"CBF6",'1'&x"CBF7",'1'&x"CBF8",'1'&x"CBF9",'1'&x"CBFA",'1'&x"CBFB",'1'&x"CBFC",'1'&x"CBFD",'1'&x"CBFE",'1'&x"CBFF",
+--'1'&x"CC00",'1'&x"CC01",'1'&x"CC02",'1'&x"CC03",'1'&x"CC04",'1'&x"CC05",'1'&x"CC06",'1'&x"CC07",'1'&x"CC08",'1'&x"CC09",'1'&x"CC0A",'1'&x"CC0B",'1'&x"CC0C",'1'&x"CC0D",'1'&x"CC0E",'1'&x"CC0F",
+--'1'&x"CC10",'1'&x"CC11",'1'&x"CC12",'1'&x"CC13",'1'&x"CC14",'1'&x"CC15",'1'&x"CC16",'1'&x"CC17",'1'&x"CC18",'1'&x"CC19",'1'&x"CC1A",'1'&x"CC1B",'1'&x"CC1C",'1'&x"CC1D",'1'&x"CC1E",'1'&x"CC1F",
+--'1'&x"CC20",'1'&x"CC21",'1'&x"CC22",'1'&x"CC23",'1'&x"CC24",'1'&x"CC25",'1'&x"CC26",'1'&x"CC27",'1'&x"CC28",'1'&x"CC29",'1'&x"CC2A",'1'&x"CC2B",'1'&x"CC2C",'1'&x"CC2D",'1'&x"CC2E",'1'&x"CC2F",
+--'1'&x"CC30",'1'&x"CC31",'1'&x"CC32",'1'&x"CC33",'1'&x"CC34",'1'&x"CC35",'1'&x"CC36",'1'&x"CC37",'1'&x"CC38",'1'&x"CC39",'1'&x"CC3A",'1'&x"CC3B",'1'&x"CC3C",'1'&x"CC3D",'1'&x"CC3E",'1'&x"CC3F",
+--'1'&x"CC40",'1'&x"CC41",'1'&x"CC42",'1'&x"CC43",'1'&x"CC44",'1'&x"CC45",'1'&x"CC46",'1'&x"CC47",'1'&x"CC48",'1'&x"CC49",'1'&x"CC4A",'1'&x"CC4B",'1'&x"CC4C",'1'&x"CC4D",'1'&x"CC4E",'1'&x"CC4F",
+--'1'&x"CC50",'1'&x"CC51",'1'&x"CC52",'1'&x"CC53",'1'&x"CC54",'1'&x"CC55",'1'&x"CC56",'1'&x"CC57",'1'&x"CC58",'1'&x"CC59",'1'&x"CC5A",'1'&x"CC5B",'1'&x"CC5C",'1'&x"CC5D",'1'&x"CC5E",'1'&x"CC5F",
+--'1'&x"CC60",'1'&x"CC61",'1'&x"CC62",'1'&x"CC63",'1'&x"CC64",'1'&x"CC65",'1'&x"CC66",'1'&x"CC67",'1'&x"CC68",'1'&x"CC69",'1'&x"CC6A",'1'&x"CC6B",'1'&x"CC6C",'1'&x"CC6D",'1'&x"CC6E",'1'&x"CC6F",
+--'1'&x"CC70",'1'&x"CC71",'1'&x"CC72",'1'&x"CC73",'1'&x"CC74",'1'&x"CC75",'1'&x"CC76",'1'&x"CC77",'1'&x"CC78",'1'&x"CC79",'1'&x"CC7A",'1'&x"CC7B",'1'&x"CC7C",'1'&x"CC7D",'1'&x"CC7E",'1'&x"CC7F",
+--'1'&x"CC80",'1'&x"CC81",'1'&x"CC82",'1'&x"CC83",'1'&x"CC84",'1'&x"CC85",'1'&x"CC86",'1'&x"CC87",'1'&x"CC88",'1'&x"CC89",'1'&x"CC8A",'1'&x"CC8B",'1'&x"CC8C",'1'&x"CC8D",'1'&x"CC8E",'1'&x"CC8F",
+--'1'&x"CC90",'1'&x"CC91",'1'&x"CC92",'1'&x"CC93",'1'&x"CC94",'1'&x"CC95",'1'&x"CC96",'1'&x"CC97",'1'&x"CC98",'1'&x"CC99",'1'&x"CC9A",'1'&x"CC9B",'1'&x"CC9C",'1'&x"CC9D",'1'&x"CC9E",'1'&x"CC9F",
+--'1'&x"CCA0",'1'&x"CCA1",'1'&x"CCA2",'1'&x"CCA3",'1'&x"CCA4",'1'&x"CCA5",'1'&x"CCA6",'1'&x"CCA7",'1'&x"CCA8",'1'&x"CCA9",'1'&x"CCAA",'1'&x"CCAB",'1'&x"CCAC",'1'&x"CCAD",'1'&x"CCAE",'1'&x"CCAF",
+--'1'&x"CCB0",'1'&x"CCB1",'1'&x"CCB2",'1'&x"CCB3",'1'&x"CCB4",'1'&x"CCB5",'1'&x"CCB6",'1'&x"CCB7",'1'&x"CCB8",'1'&x"CCB9",'1'&x"CCBA",'1'&x"CCBB",'1'&x"CCBC",'1'&x"CCBD",'1'&x"CCBE",'1'&x"CCBF",
+--'1'&x"CCC0",'1'&x"CCC1",'1'&x"CCC2",'1'&x"CCC3",'1'&x"CCC4",'1'&x"CCC5",'1'&x"CCC6",'1'&x"CCC7",'1'&x"CCC8",'1'&x"CCC9",'1'&x"CCCA",'1'&x"CCCB",'1'&x"CCCC",'1'&x"CCCD",'1'&x"CCCE",'1'&x"CCCF",
+--'1'&x"CCD0",'1'&x"CCD1",'1'&x"CCD2",'1'&x"CCD3",'1'&x"CCD4",'1'&x"CCD5",'1'&x"CCD6",'1'&x"CCD7",'1'&x"CCD8",'1'&x"CCD9",'1'&x"CCDA",'1'&x"CCDB",'1'&x"CCDC",'1'&x"CCDD",'1'&x"CCDE",'1'&x"CCDF",
+--'1'&x"CCE0",'1'&x"CCE1",'1'&x"CCE2",'1'&x"CCE3",'1'&x"CCE4",'1'&x"CCE5",'1'&x"CCE6",'1'&x"CCE7",'1'&x"CCE8",'1'&x"CCE9",'1'&x"CCEA",'1'&x"CCEB",'1'&x"CCEC",'1'&x"CCED",'1'&x"CCEE",'1'&x"CCEF",
+--'1'&x"CCF0",'1'&x"CCF1",'1'&x"CCF2",'1'&x"CCF3",'1'&x"CCF4",'1'&x"CCF5",'1'&x"CCF6",'1'&x"CCF7",'1'&x"CCF8",'1'&x"CCF9",'1'&x"CCFA",'1'&x"CCFB",'1'&x"CCFC",'1'&x"CCFD",'1'&x"CCFE",'1'&x"CCFF",
+--'1'&x"CD00",'1'&x"CD01",'1'&x"CD02",'1'&x"CD03",'1'&x"CD04",'1'&x"CD05",'1'&x"CD06",'1'&x"CD07",'1'&x"CD08",'1'&x"CD09",'1'&x"CD0A",'1'&x"CD0B",'1'&x"CD0C",'1'&x"CD0D",'1'&x"CD0E",'1'&x"CD0F",
+--'1'&x"CD10",'1'&x"CD11",'1'&x"CD12",'1'&x"CD13",'1'&x"CD14",'1'&x"CD15",'1'&x"CD16",'1'&x"CD17",'1'&x"CD18",'1'&x"CD19",'1'&x"CD1A",'1'&x"CD1B",'1'&x"CD1C",'1'&x"CD1D",'1'&x"CD1E",'1'&x"CD1F",
+--'1'&x"CD20",'1'&x"CD21",'1'&x"CD22",'1'&x"CD23",'1'&x"CD24",'1'&x"CD25",'1'&x"CD26",'1'&x"CD27",'1'&x"CD28",'1'&x"CD29",'1'&x"CD2A",'1'&x"CD2B",'1'&x"CD2C",'1'&x"CD2D",'1'&x"CD2E",'1'&x"CD2F",
+--'1'&x"CD30",'1'&x"CD31",'1'&x"CD32",'1'&x"CD33",'1'&x"CD34",'1'&x"CD35",'1'&x"CD36",'1'&x"CD37",'1'&x"CD38",'1'&x"CD39",'1'&x"CD3A",'1'&x"CD3B",'1'&x"CD3C",'1'&x"CD3D",'1'&x"CD3E",'1'&x"CD3F",
+--'1'&x"CD40",'1'&x"CD41",'1'&x"CD42",'1'&x"CD43",'1'&x"CD44",'1'&x"CD45",'1'&x"CD46",'1'&x"CD47",'1'&x"CD48",'1'&x"CD49",'1'&x"CD4A",'1'&x"CD4B",'1'&x"CD4C",'1'&x"CD4D",'1'&x"CD4E",'1'&x"CD4F",
+--'1'&x"CD50",'1'&x"CD51",'1'&x"CD52",'1'&x"CD53",'1'&x"CD54",'1'&x"CD55",'1'&x"CD56",'1'&x"CD57",'1'&x"CD58",'1'&x"CD59",'1'&x"CD5A",'1'&x"CD5B",'1'&x"CD5C",'1'&x"CD5D",'1'&x"CD5E",'1'&x"CD5F",
+--'1'&x"CD60",'1'&x"CD61",'1'&x"CD62",'1'&x"CD63",'1'&x"CD64",'1'&x"CD65",'1'&x"CD66",'1'&x"CD67",'1'&x"CD68",'1'&x"CD69",'1'&x"CD6A",'1'&x"CD6B",'1'&x"CD6C",'1'&x"CD6D",'1'&x"CD6E",'1'&x"CD6F",
+--'1'&x"CD70",'1'&x"CD71",'1'&x"CD72",'1'&x"CD73",'1'&x"CD74",'1'&x"CD75",'1'&x"CD76",'1'&x"CD77",'1'&x"CD78",'1'&x"CD79",'1'&x"CD7A",'1'&x"CD7B",'1'&x"CD7C",'1'&x"CD7D",'1'&x"CD7E",'1'&x"CD7F",
+--'1'&x"CD80",'1'&x"CD81",'1'&x"CD82",'1'&x"CD83",'1'&x"CD84",'1'&x"CD85",'1'&x"CD86",'1'&x"CD87",'1'&x"CD88",'1'&x"CD89",'1'&x"CD8A",'1'&x"CD8B",'1'&x"CD8C",'1'&x"CD8D",'1'&x"CD8E",'1'&x"CD8F",
+--'1'&x"CD90",'1'&x"CD91",'1'&x"CD92",'1'&x"CD93",'1'&x"CD94",'1'&x"CD95",'1'&x"CD96",'1'&x"CD97",'1'&x"CD98",'1'&x"CD99",'1'&x"CD9A",'1'&x"CD9B",'1'&x"CD9C",'1'&x"CD9D",'1'&x"CD9E",'1'&x"CD9F",
+--'1'&x"CDA0",'1'&x"CDA1",'1'&x"CDA2",'1'&x"CDA3",'1'&x"CDA4",'1'&x"CDA5",'1'&x"CDA6",'1'&x"CDA7",'1'&x"CDA8",'1'&x"CDA9",'1'&x"CDAA",'1'&x"CDAB",'1'&x"CDAC",'1'&x"CDAD",'1'&x"CDAE",'1'&x"CDAF",
+--'1'&x"CDB0",'1'&x"CDB1",'1'&x"CDB2",'1'&x"CDB3",'1'&x"CDB4",'1'&x"CDB5",'1'&x"CDB6",'1'&x"CDB7",'1'&x"CDB8",'1'&x"CDB9",'1'&x"CDBA",'1'&x"CDBB",'1'&x"CDBC",'1'&x"CDBD",'1'&x"CDBE",'1'&x"CDBF",
+--'1'&x"CDC0",'1'&x"CDC1",'1'&x"CDC2",'1'&x"CDC3",'1'&x"CDC4",'1'&x"CDC5",'1'&x"CDC6",'1'&x"CDC7",'1'&x"CDC8",'1'&x"CDC9",'1'&x"CDCA",'1'&x"CDCB",'1'&x"CDCC",'1'&x"CDCD",'1'&x"CDCE",'1'&x"CDCF",
+--'1'&x"CDD0",'1'&x"CDD1",'1'&x"CDD2",'1'&x"CDD3",'1'&x"CDD4",'1'&x"CDD5",'1'&x"CDD6",'1'&x"CDD7",'1'&x"CDD8",'1'&x"CDD9",'1'&x"CDDA",'1'&x"CDDB",'1'&x"CDDC",'1'&x"CDDD",'1'&x"CDDE",'1'&x"CDDF",
+--'1'&x"CDE0",'1'&x"CDE1",'1'&x"CDE2",'1'&x"CDE3",'1'&x"CDE4",'1'&x"CDE5",'1'&x"CDE6",'1'&x"CDE7",'1'&x"CDE8",'1'&x"CDE9",'1'&x"CDEA",'1'&x"CDEB",'1'&x"CDEC",'1'&x"CDED",'1'&x"CDEE",'1'&x"CDEF",
+--'1'&x"CDF0",'1'&x"CDF1",'1'&x"CDF2",'1'&x"CDF3",'1'&x"CDF4",'1'&x"CDF5",'1'&x"CDF6",'1'&x"CDF7",'1'&x"CDF8",'1'&x"CDF9",'1'&x"CDFA",'1'&x"CDFB",'1'&x"CDFC",'1'&x"CDFD",'1'&x"CDFE",'1'&x"CDFF",
+--'1'&x"CE00",'1'&x"CE01",'1'&x"CE02",'1'&x"CE03",'1'&x"CE04",'1'&x"CE05",'1'&x"CE06",'1'&x"CE07",'1'&x"CE08",'1'&x"CE09",'1'&x"CE0A",'1'&x"CE0B",'1'&x"CE0C",'1'&x"CE0D",'1'&x"CE0E",'1'&x"CE0F",
+--'1'&x"CE10",'1'&x"CE11",'1'&x"CE12",'1'&x"CE13",'1'&x"CE14",'1'&x"CE15",'1'&x"CE16",'1'&x"CE17",'1'&x"CE18",'1'&x"CE19",'1'&x"CE1A",'1'&x"CE1B",'1'&x"CE1C",'1'&x"CE1D",'1'&x"CE1E",'1'&x"CE1F",
+--'1'&x"CE20",'1'&x"CE21",'1'&x"CE22",'1'&x"CE23",'1'&x"CE24",'1'&x"CE25",'1'&x"CE26",'1'&x"CE27",'1'&x"CE28",'1'&x"CE29",'1'&x"CE2A",'1'&x"CE2B",'1'&x"CE2C",'1'&x"CE2D",'1'&x"CE2E",'1'&x"CE2F",
+--'1'&x"CE30",'1'&x"CE31",'1'&x"CE32",'1'&x"CE33",'1'&x"CE34",'1'&x"CE35",'1'&x"CE36",'1'&x"CE37",'1'&x"CE38",'1'&x"CE39",'1'&x"CE3A",'1'&x"CE3B",'1'&x"CE3C",'1'&x"CE3D",'1'&x"CE3E",'1'&x"CE3F",
+--'1'&x"CE40",'1'&x"CE41",'1'&x"CE42",'1'&x"CE43",'1'&x"CE44",'1'&x"CE45",'1'&x"CE46",'1'&x"CE47",'1'&x"CE48",'1'&x"CE49",'1'&x"CE4A",'1'&x"CE4B",'1'&x"CE4C",'1'&x"CE4D",'1'&x"CE4E",'1'&x"CE4F",
+--'1'&x"CE50",'1'&x"CE51",'1'&x"CE52",'1'&x"CE53",'1'&x"CE54",'1'&x"CE55",'1'&x"CE56",'1'&x"CE57",'1'&x"CE58",'1'&x"CE59",'1'&x"CE5A",'1'&x"CE5B",'1'&x"CE5C",'1'&x"CE5D",'1'&x"CE5E",'1'&x"CE5F",
+--'1'&x"CE60",'1'&x"CE61",'1'&x"CE62",'1'&x"CE63",'1'&x"CE64",'1'&x"CE65",'1'&x"CE66",'1'&x"CE67",'1'&x"CE68",'1'&x"CE69",'1'&x"CE6A",'1'&x"CE6B",'1'&x"CE6C",'1'&x"CE6D",'1'&x"CE6E",'1'&x"CE6F",
+--'1'&x"CE70",'1'&x"CE71",'1'&x"CE72",'1'&x"CE73",'1'&x"CE74",'1'&x"CE75",'1'&x"CE76",'1'&x"CE77",'1'&x"CE78",'1'&x"CE79",'1'&x"CE7A",'1'&x"CE7B",'1'&x"CE7C",'1'&x"CE7D",'1'&x"CE7E",'1'&x"CE7F",
+--'1'&x"CE80",'1'&x"CE81",'1'&x"CE82",'1'&x"CE83",'1'&x"CE84",'1'&x"CE85",'1'&x"CE86",'1'&x"CE87",'1'&x"CE88",'1'&x"CE89",'1'&x"CE8A",'1'&x"CE8B",'1'&x"CE8C",'1'&x"CE8D",'1'&x"CE8E",'1'&x"CE8F",
+--'1'&x"CE90",'1'&x"CE91",'1'&x"CE92",'1'&x"CE93",'1'&x"CE94",'1'&x"CE95",'1'&x"CE96",'1'&x"CE97",'1'&x"CE98",'1'&x"CE99",'1'&x"CE9A",'1'&x"CE9B",'1'&x"CE9C",'1'&x"CE9D",'1'&x"CE9E",'1'&x"CE9F",
+--'1'&x"CEA0",'1'&x"CEA1",'1'&x"CEA2",'1'&x"CEA3",'1'&x"CEA4",'1'&x"CEA5",'1'&x"CEA6",'1'&x"CEA7",'1'&x"CEA8",'1'&x"CEA9",'1'&x"CEAA",'1'&x"CEAB",'1'&x"CEAC",'1'&x"CEAD",'1'&x"CEAE",'1'&x"CEAF",
+--'1'&x"CEB0",'1'&x"CEB1",'1'&x"CEB2",'1'&x"CEB3",'1'&x"CEB4",'1'&x"CEB5",'1'&x"CEB6",'1'&x"CEB7",'1'&x"CEB8",'1'&x"CEB9",'1'&x"CEBA",'1'&x"CEBB",'1'&x"CEBC",'1'&x"CEBD",'1'&x"CEBE",'1'&x"CEBF",
+--'1'&x"CEC0",'1'&x"CEC1",'1'&x"CEC2",'1'&x"CEC3",'1'&x"CEC4",'1'&x"CEC5",'1'&x"CEC6",'1'&x"CEC7",'1'&x"CEC8",'1'&x"CEC9",'1'&x"CECA",'1'&x"CECB",'1'&x"CECC",'1'&x"CECD",'1'&x"CECE",'1'&x"CECF",
+--'1'&x"CED0",'1'&x"CED1",'1'&x"CED2",'1'&x"CED3",'1'&x"CED4",'1'&x"CED5",'1'&x"CED6",'1'&x"CED7",'1'&x"CED8",'1'&x"CED9",'1'&x"CEDA",'1'&x"CEDB",'1'&x"CEDC",'1'&x"CEDD",'1'&x"CEDE",'1'&x"CEDF",
+--'1'&x"CEE0",'1'&x"CEE1",'1'&x"CEE2",'1'&x"CEE3",'1'&x"CEE4",'1'&x"CEE5",'1'&x"CEE6",'1'&x"CEE7",'1'&x"CEE8",'1'&x"CEE9",'1'&x"CEEA",'1'&x"CEEB",'1'&x"CEEC",'1'&x"CEED",'1'&x"CEEE",'1'&x"CEEF",
+--'1'&x"CEF0",'1'&x"CEF1",'1'&x"CEF2",'1'&x"CEF3",'1'&x"CEF4",'1'&x"CEF5",'1'&x"CEF6",'1'&x"CEF7",'1'&x"CEF8",'1'&x"CEF9",'1'&x"CEFA",'1'&x"CEFB",'1'&x"CEFC",'1'&x"CEFD",'1'&x"CEFE",'1'&x"CEFF",
+--'1'&x"CF00",'1'&x"CF01",'1'&x"CF02",'1'&x"CF03",'1'&x"CF04",'1'&x"CF05",'1'&x"CF06",'1'&x"CF07",'1'&x"CF08",'1'&x"CF09",'1'&x"CF0A",'1'&x"CF0B",'1'&x"CF0C",'1'&x"CF0D",'1'&x"CF0E",'1'&x"CF0F",
+--'1'&x"CF10",'1'&x"CF11",'1'&x"CF12",'1'&x"CF13",'1'&x"CF14",'1'&x"CF15",'1'&x"CF16",'1'&x"CF17",'1'&x"CF18",'1'&x"CF19",'1'&x"CF1A",'1'&x"CF1B",'1'&x"CF1C",'1'&x"CF1D",'1'&x"CF1E",'1'&x"CF1F",
+--'1'&x"CF20",'1'&x"CF21",'1'&x"CF22",'1'&x"CF23",'1'&x"CF24",'1'&x"CF25",'1'&x"CF26",'1'&x"CF27",'1'&x"CF28",'1'&x"CF29",'1'&x"CF2A",'1'&x"CF2B",'1'&x"CF2C",'1'&x"CF2D",'1'&x"CF2E",'1'&x"CF2F",
+--'1'&x"CF30",'1'&x"CF31",'1'&x"CF32",'1'&x"CF33",'1'&x"CF34",'1'&x"CF35",'1'&x"CF36",'1'&x"CF37",'1'&x"CF38",'1'&x"CF39",'1'&x"CF3A",'1'&x"CF3B",'1'&x"CF3C",'1'&x"CF3D",'1'&x"CF3E",'1'&x"CF3F",
+--'1'&x"CF40",'1'&x"CF41",'1'&x"CF42",'1'&x"CF43",'1'&x"CF44",'1'&x"CF45",'1'&x"CF46",'1'&x"CF47",'1'&x"CF48",'1'&x"CF49",'1'&x"CF4A",'1'&x"CF4B",'1'&x"CF4C",'1'&x"CF4D",'1'&x"CF4E",'1'&x"CF4F",
+--'1'&x"CF50",'1'&x"CF51",'1'&x"CF52",'1'&x"CF53",'1'&x"CF54",'1'&x"CF55",'1'&x"CF56",'1'&x"CF57",'1'&x"CF58",'1'&x"CF59",'1'&x"CF5A",'1'&x"CF5B",'1'&x"CF5C",'1'&x"CF5D",'1'&x"CF5E",'1'&x"CF5F",
+--'1'&x"CF60",'1'&x"CF61",'1'&x"CF62",'1'&x"CF63",'1'&x"CF64",'1'&x"CF65",'1'&x"CF66",'1'&x"CF67",'1'&x"CF68",'1'&x"CF69",'1'&x"CF6A",'1'&x"CF6B",'1'&x"CF6C",'1'&x"CF6D",'1'&x"CF6E",'1'&x"CF6F",
+--'1'&x"CF70",'1'&x"CF71",'1'&x"CF72",'1'&x"CF73",'1'&x"CF74",'1'&x"CF75",'1'&x"CF76",'1'&x"CF77",'1'&x"CF78",'1'&x"CF79",'1'&x"CF7A",'1'&x"CF7B",'1'&x"CF7C",'1'&x"CF7D",'1'&x"CF7E",'1'&x"CF7F",
+--'1'&x"CF80",'1'&x"CF81",'1'&x"CF82",'1'&x"CF83",'1'&x"CF84",'1'&x"CF85",'1'&x"CF86",'1'&x"CF87",'1'&x"CF88",'1'&x"CF89",'1'&x"CF8A",'1'&x"CF8B",'1'&x"CF8C",'1'&x"CF8D",'1'&x"CF8E",'1'&x"CF8F",
+--'1'&x"CF90",'1'&x"CF91",'1'&x"CF92",'1'&x"CF93",'1'&x"CF94",'1'&x"CF95",'1'&x"CF96",'1'&x"CF97",'1'&x"CF98",'1'&x"CF99",'1'&x"CF9A",'1'&x"CF9B",'1'&x"CF9C",'1'&x"CF9D",'1'&x"CF9E",'1'&x"CF9F",
+--'1'&x"CFA0",'1'&x"CFA1",'1'&x"CFA2",'1'&x"CFA3",'1'&x"CFA4",'1'&x"CFA5",'1'&x"CFA6",'1'&x"CFA7",'1'&x"CFA8",'1'&x"CFA9",'1'&x"CFAA",'1'&x"CFAB",'1'&x"CFAC",'1'&x"CFAD",'1'&x"CFAE",'1'&x"CFAF",
+--'1'&x"CFB0",'1'&x"CFB1",'1'&x"CFB2",'1'&x"CFB3",'1'&x"CFB4",'1'&x"CFB5",'1'&x"CFB6",'1'&x"CFB7",'1'&x"CFB8",'1'&x"CFB9",'1'&x"CFBA",'1'&x"CFBB",'1'&x"CFBC",'1'&x"CFBD",'1'&x"CFBE",'1'&x"CFBF",
+--'1'&x"CFC0",'1'&x"CFC1",'1'&x"CFC2",'1'&x"CFC3",'1'&x"CFC4",'1'&x"CFC5",'1'&x"CFC6",'1'&x"CFC7",'1'&x"CFC8",'1'&x"CFC9",'1'&x"CFCA",'1'&x"CFCB",'1'&x"CFCC",'1'&x"CFCD",'1'&x"CFCE",'1'&x"CFCF",
+--'1'&x"CFD0",'1'&x"CFD1",'1'&x"CFD2",'1'&x"CFD3",'1'&x"CFD4",'1'&x"CFD5",'1'&x"CFD6",'1'&x"CFD7",'1'&x"CFD8",'1'&x"CFD9",'1'&x"CFDA",'1'&x"CFDB",'1'&x"CFDC",'1'&x"CFDD",'1'&x"CFDE",'1'&x"CFDF",
+--'1'&x"CFE0",'1'&x"CFE1",'1'&x"CFE2",'1'&x"CFE3",'1'&x"CFE4",'1'&x"CFE5",'1'&x"CFE6",'1'&x"CFE7",'1'&x"CFE8",'1'&x"CFE9",'1'&x"CFEA",'1'&x"CFEB",'1'&x"CFEC",'1'&x"CFED",'1'&x"CFEE",'1'&x"CFEF",
+--'1'&x"CFF0",'1'&x"CFF1",'1'&x"CFF2",'1'&x"CFF3",'1'&x"CFF4",'1'&x"CFF5",'1'&x"CFF6",'1'&x"CFF7",'1'&x"CFF8",'1'&x"CFF9",'1'&x"CFFA",'1'&x"CFFB",'1'&x"CFFC",'1'&x"CFFD",'1'&x"CFFE",'1'&x"CFFF",
+--'1'&x"D000",'1'&x"D001",'1'&x"D002",'1'&x"D003",'1'&x"D004",'1'&x"D005",'1'&x"D006",'1'&x"D007",'1'&x"D008",'1'&x"D009",'1'&x"D00A",'1'&x"D00B",'1'&x"D00C",'1'&x"D00D",'1'&x"D00E",'1'&x"D00F",
+--'1'&x"D010",'1'&x"D011",'1'&x"D012",'1'&x"D013",'1'&x"D014",'1'&x"D015",'1'&x"D016",'1'&x"D017",'1'&x"D018",'1'&x"D019",'1'&x"D01A",'1'&x"D01B",'1'&x"D01C",'1'&x"D01D",'1'&x"D01E",'1'&x"D01F",
+--'1'&x"D020",'1'&x"D021",'1'&x"D022",'1'&x"D023",'1'&x"D024",'1'&x"D025",'1'&x"D026",'1'&x"D027",'1'&x"D028",'1'&x"D029",'1'&x"D02A",'1'&x"D02B",'1'&x"D02C",'1'&x"D02D",'1'&x"D02E",'1'&x"D02F",
+--'1'&x"D030",'1'&x"D031",'1'&x"D032",'1'&x"D033",'1'&x"D034",'1'&x"D035",'1'&x"D036",'1'&x"D037",'1'&x"D038",'1'&x"D039",'1'&x"D03A",'1'&x"D03B",'1'&x"D03C",'1'&x"D03D",'1'&x"D03E",'1'&x"D03F",
+--'1'&x"D040",'1'&x"D041",'1'&x"D042",'1'&x"D043",'1'&x"D044",'1'&x"D045",'1'&x"D046",'1'&x"D047",'1'&x"D048",'1'&x"D049",'1'&x"D04A",'1'&x"D04B",'1'&x"D04C",'1'&x"D04D",'1'&x"D04E",'1'&x"D04F",
+--'1'&x"D050",'1'&x"D051",'1'&x"D052",'1'&x"D053",'1'&x"D054",'1'&x"D055",'1'&x"D056",'1'&x"D057",'1'&x"D058",'1'&x"D059",'1'&x"D05A",'1'&x"D05B",'1'&x"D05C",'1'&x"D05D",'1'&x"D05E",'1'&x"D05F",
+--'1'&x"D060",'1'&x"D061",'1'&x"D062",'1'&x"D063",'1'&x"D064",'1'&x"D065",'1'&x"D066",'1'&x"D067",'1'&x"D068",'1'&x"D069",'1'&x"D06A",'1'&x"D06B",'1'&x"D06C",'1'&x"D06D",'1'&x"D06E",'1'&x"D06F",
+--'1'&x"D070",'1'&x"D071",'1'&x"D072",'1'&x"D073",'1'&x"D074",'1'&x"D075",'1'&x"D076",'1'&x"D077",'1'&x"D078",'1'&x"D079",'1'&x"D07A",'1'&x"D07B",'1'&x"D07C",'1'&x"D07D",'1'&x"D07E",'1'&x"D07F",
+--'1'&x"D080",'1'&x"D081",'1'&x"D082",'1'&x"D083",'1'&x"D084",'1'&x"D085",'1'&x"D086",'1'&x"D087",'1'&x"D088",'1'&x"D089",'1'&x"D08A",'1'&x"D08B",'1'&x"D08C",'1'&x"D08D",'1'&x"D08E",'1'&x"D08F",
+--'1'&x"D090",'1'&x"D091",'1'&x"D092",'1'&x"D093",'1'&x"D094",'1'&x"D095",'1'&x"D096",'1'&x"D097",'1'&x"D098",'1'&x"D099",'1'&x"D09A",'1'&x"D09B",'1'&x"D09C",'1'&x"D09D",'1'&x"D09E",'1'&x"D09F",
+--'1'&x"D0A0",'1'&x"D0A1",'1'&x"D0A2",'1'&x"D0A3",'1'&x"D0A4",'1'&x"D0A5",'1'&x"D0A6",'1'&x"D0A7",'1'&x"D0A8",'1'&x"D0A9",'1'&x"D0AA",'1'&x"D0AB",'1'&x"D0AC",'1'&x"D0AD",'1'&x"D0AE",'1'&x"D0AF",
+--'1'&x"D0B0",'1'&x"D0B1",'1'&x"D0B2",'1'&x"D0B3",'1'&x"D0B4",'1'&x"D0B5",'1'&x"D0B6",'1'&x"D0B7",'1'&x"D0B8",'1'&x"D0B9",'1'&x"D0BA",'1'&x"D0BB",'1'&x"D0BC",'1'&x"D0BD",'1'&x"D0BE",'1'&x"D0BF",
+--'1'&x"D0C0",'1'&x"D0C1",'1'&x"D0C2",'1'&x"D0C3",'1'&x"D0C4",'1'&x"D0C5",'1'&x"D0C6",'1'&x"D0C7",'1'&x"D0C8",'1'&x"D0C9",'1'&x"D0CA",'1'&x"D0CB",'1'&x"D0CC",'1'&x"D0CD",'1'&x"D0CE",'1'&x"D0CF",
+--'1'&x"D0D0",'1'&x"D0D1",'1'&x"D0D2",'1'&x"D0D3",'1'&x"D0D4",'1'&x"D0D5",'1'&x"D0D6",'1'&x"D0D7",'1'&x"D0D8",'1'&x"D0D9",'1'&x"D0DA",'1'&x"D0DB",'1'&x"D0DC",'1'&x"D0DD",'1'&x"D0DE",'1'&x"D0DF",
+--'1'&x"D0E0",'1'&x"D0E1",'1'&x"D0E2",'1'&x"D0E3",'1'&x"D0E4",'1'&x"D0E5",'1'&x"D0E6",'1'&x"D0E7",'1'&x"D0E8",'1'&x"D0E9",'1'&x"D0EA",'1'&x"D0EB",'1'&x"D0EC",'1'&x"D0ED",'1'&x"D0EE",'1'&x"D0EF",
+--'1'&x"D0F0",'1'&x"D0F1",'1'&x"D0F2",'1'&x"D0F3",'1'&x"D0F4",'1'&x"D0F5",'1'&x"D0F6",'1'&x"D0F7",'1'&x"D0F8",'1'&x"D0F9",'1'&x"D0FA",'1'&x"D0FB",'1'&x"D0FC",'1'&x"D0FD",'1'&x"D0FE",'1'&x"D0FF",
+--'1'&x"D100",'1'&x"D101",'1'&x"D102",'1'&x"D103",'1'&x"D104",'1'&x"D105",'1'&x"D106",'1'&x"D107",'1'&x"D108",'1'&x"D109",'1'&x"D10A",'1'&x"D10B",'1'&x"D10C",'1'&x"D10D",'1'&x"D10E",'1'&x"D10F",
+--'1'&x"D110",'1'&x"D111",'1'&x"D112",'1'&x"D113",'1'&x"D114",'1'&x"D115",'1'&x"D116",'1'&x"D117",'1'&x"D118",'1'&x"D119",'1'&x"D11A",'1'&x"D11B",'1'&x"D11C",'1'&x"D11D",'1'&x"D11E",'1'&x"D11F",
+--'1'&x"D120",'1'&x"D121",'1'&x"D122",'1'&x"D123",'1'&x"D124",'1'&x"D125",'1'&x"D126",'1'&x"D127",'1'&x"D128",'1'&x"D129",'1'&x"D12A",'1'&x"D12B",'1'&x"D12C",'1'&x"D12D",'1'&x"D12E",'1'&x"D12F",
+--'1'&x"D130",'1'&x"D131",'1'&x"D132",'1'&x"D133",'1'&x"D134",'1'&x"D135",'1'&x"D136",'1'&x"D137",'1'&x"D138",'1'&x"D139",'1'&x"D13A",'1'&x"D13B",'1'&x"D13C",'1'&x"D13D",'1'&x"D13E",'1'&x"D13F",
+--'1'&x"D140",'1'&x"D141",'1'&x"D142",'1'&x"D143",'1'&x"D144",'1'&x"D145",'1'&x"D146",'1'&x"D147",'1'&x"D148",'1'&x"D149",'1'&x"D14A",'1'&x"D14B",'1'&x"D14C",'1'&x"D14D",'1'&x"D14E",'1'&x"D14F",
+--'1'&x"D150",'1'&x"D151",'1'&x"D152",'1'&x"D153",'1'&x"D154",'1'&x"D155",'1'&x"D156",'1'&x"D157",'1'&x"D158",'1'&x"D159",'1'&x"D15A",'1'&x"D15B",'1'&x"D15C",'1'&x"D15D",'1'&x"D15E",'1'&x"D15F",
+--'1'&x"D160",'1'&x"D161",'1'&x"D162",'1'&x"D163",'1'&x"D164",'1'&x"D165",'1'&x"D166",'1'&x"D167",'1'&x"D168",'1'&x"D169",'1'&x"D16A",'1'&x"D16B",'1'&x"D16C",'1'&x"D16D",'1'&x"D16E",'1'&x"D16F",
+--'1'&x"D170",'1'&x"D171",'1'&x"D172",'1'&x"D173",'1'&x"D174",'1'&x"D175",'1'&x"D176",'1'&x"D177",'1'&x"D178",'1'&x"D179",'1'&x"D17A",'1'&x"D17B",'1'&x"D17C",'1'&x"D17D",'1'&x"D17E",'1'&x"D17F",
+--'1'&x"D180",'1'&x"D181",'1'&x"D182",'1'&x"D183",'1'&x"D184",'1'&x"D185",'1'&x"D186",'1'&x"D187",'1'&x"D188",'1'&x"D189",'1'&x"D18A",'1'&x"D18B",'1'&x"D18C",'1'&x"D18D",'1'&x"D18E",'1'&x"D18F",
+--'1'&x"D190",'1'&x"D191",'1'&x"D192",'1'&x"D193",'1'&x"D194",'1'&x"D195",'1'&x"D196",'1'&x"D197",'1'&x"D198",'1'&x"D199",'1'&x"D19A",'1'&x"D19B",'1'&x"D19C",'1'&x"D19D",'1'&x"D19E",'1'&x"D19F",
+--'1'&x"D1A0",'1'&x"D1A1",'1'&x"D1A2",'1'&x"D1A3",'1'&x"D1A4",'1'&x"D1A5",'1'&x"D1A6",'1'&x"D1A7",'1'&x"D1A8",'1'&x"D1A9",'1'&x"D1AA",'1'&x"D1AB",'1'&x"D1AC",'1'&x"D1AD",'1'&x"D1AE",'1'&x"D1AF",
+--'1'&x"D1B0",'1'&x"D1B1",'1'&x"D1B2",'1'&x"D1B3",'1'&x"D1B4",'1'&x"D1B5",'1'&x"D1B6",'1'&x"D1B7",'1'&x"D1B8",'1'&x"D1B9",'1'&x"D1BA",'1'&x"D1BB",'1'&x"D1BC",'1'&x"D1BD",'1'&x"D1BE",'1'&x"D1BF",
+--'1'&x"D1C0",'1'&x"D1C1",'1'&x"D1C2",'1'&x"D1C3",'1'&x"D1C4",'1'&x"D1C5",'1'&x"D1C6",'1'&x"D1C7",'1'&x"D1C8",'1'&x"D1C9",'1'&x"D1CA",'1'&x"D1CB",'1'&x"D1CC",'1'&x"D1CD",'1'&x"D1CE",'1'&x"D1CF",
+--'1'&x"D1D0",'1'&x"D1D1",'1'&x"D1D2",'1'&x"D1D3",'1'&x"D1D4",'1'&x"D1D5",'1'&x"D1D6",'1'&x"D1D7",'1'&x"D1D8",'1'&x"D1D9",'1'&x"D1DA",'1'&x"D1DB",'1'&x"D1DC",'1'&x"D1DD",'1'&x"D1DE",'1'&x"D1DF",
+--'1'&x"D1E0",'1'&x"D1E1",'1'&x"D1E2",'1'&x"D1E3",'1'&x"D1E4",'1'&x"D1E5",'1'&x"D1E6",'1'&x"D1E7",'1'&x"D1E8",'1'&x"D1E9",'1'&x"D1EA",'1'&x"D1EB",'1'&x"D1EC",'1'&x"D1ED",'1'&x"D1EE",'1'&x"D1EF",
+--'1'&x"D1F0",'1'&x"D1F1",'1'&x"D1F2",'1'&x"D1F3",'1'&x"D1F4",'1'&x"D1F5",'1'&x"D1F6",'1'&x"D1F7",'1'&x"D1F8",'1'&x"D1F9",'1'&x"D1FA",'1'&x"D1FB",'1'&x"D1FC",'1'&x"D1FD",'1'&x"D1FE",'1'&x"D1FF",
+--'1'&x"D200",'1'&x"D201",'1'&x"D202",'1'&x"D203",'1'&x"D204",'1'&x"D205",'1'&x"D206",'1'&x"D207",'1'&x"D208",'1'&x"D209",'1'&x"D20A",'1'&x"D20B",'1'&x"D20C",'1'&x"D20D",'1'&x"D20E",'1'&x"D20F",
+--'1'&x"D210",'1'&x"D211",'1'&x"D212",'1'&x"D213",'1'&x"D214",'1'&x"D215",'1'&x"D216",'1'&x"D217",'1'&x"D218",'1'&x"D219",'1'&x"D21A",'1'&x"D21B",'1'&x"D21C",'1'&x"D21D",'1'&x"D21E",'1'&x"D21F",
+--'1'&x"D220",'1'&x"D221",'1'&x"D222",'1'&x"D223",'1'&x"D224",'1'&x"D225",'1'&x"D226",'1'&x"D227",'1'&x"D228",'1'&x"D229",'1'&x"D22A",'1'&x"D22B",'1'&x"D22C",'1'&x"D22D",'1'&x"D22E",'1'&x"D22F",
+--'1'&x"D230",'1'&x"D231",'1'&x"D232",'1'&x"D233",'1'&x"D234",'1'&x"D235",'1'&x"D236",'1'&x"D237",'1'&x"D238",'1'&x"D239",'1'&x"D23A",'1'&x"D23B",'1'&x"D23C",'1'&x"D23D",'1'&x"D23E",'1'&x"D23F",
+--'1'&x"D240",'1'&x"D241",'1'&x"D242",'1'&x"D243",'1'&x"D244",'1'&x"D245",'1'&x"D246",'1'&x"D247",'1'&x"D248",'1'&x"D249",'1'&x"D24A",'1'&x"D24B",'1'&x"D24C",'1'&x"D24D",'1'&x"D24E",'1'&x"D24F",
+--'1'&x"D250",'1'&x"D251",'1'&x"D252",'1'&x"D253",'1'&x"D254",'1'&x"D255",'1'&x"D256",'1'&x"D257",'1'&x"D258",'1'&x"D259",'1'&x"D25A",'1'&x"D25B",'1'&x"D25C",'1'&x"D25D",'1'&x"D25E",'1'&x"D25F",
+--'1'&x"D260",'1'&x"D261",'1'&x"D262",'1'&x"D263",'1'&x"D264",'1'&x"D265",'1'&x"D266",'1'&x"D267",'1'&x"D268",'1'&x"D269",'1'&x"D26A",'1'&x"D26B",'1'&x"D26C",'1'&x"D26D",'1'&x"D26E",'1'&x"D26F",
+--'1'&x"D270",'1'&x"D271",'1'&x"D272",'1'&x"D273",'1'&x"D274",'1'&x"D275",'1'&x"D276",'1'&x"D277",'1'&x"D278",'1'&x"D279",'1'&x"D27A",'1'&x"D27B",'1'&x"D27C",'1'&x"D27D",'1'&x"D27E",'1'&x"D27F",
+--'1'&x"D280",'1'&x"D281",'1'&x"D282",'1'&x"D283",'1'&x"D284",'1'&x"D285",'1'&x"D286",'1'&x"D287",'1'&x"D288",'1'&x"D289",'1'&x"D28A",'1'&x"D28B",'1'&x"D28C",'1'&x"D28D",'1'&x"D28E",'1'&x"D28F",
+--'1'&x"D290",'1'&x"D291",'1'&x"D292",'1'&x"D293",'1'&x"D294",'1'&x"D295",'1'&x"D296",'1'&x"D297",'1'&x"D298",'1'&x"D299",'1'&x"D29A",'1'&x"D29B",'1'&x"D29C",'1'&x"D29D",'1'&x"D29E",'1'&x"D29F",
+--'1'&x"D2A0",'1'&x"D2A1",'1'&x"D2A2",'1'&x"D2A3",'1'&x"D2A4",'1'&x"D2A5",'1'&x"D2A6",'1'&x"D2A7",'1'&x"D2A8",'1'&x"D2A9",'1'&x"D2AA",'1'&x"D2AB",'1'&x"D2AC",'1'&x"D2AD",'1'&x"D2AE",'1'&x"D2AF",
+--'1'&x"D2B0",'1'&x"D2B1",'1'&x"D2B2",'1'&x"D2B3",'1'&x"D2B4",'1'&x"D2B5",'1'&x"D2B6",'1'&x"D2B7",'1'&x"D2B8",'1'&x"D2B9",'1'&x"D2BA",'1'&x"D2BB",'1'&x"D2BC",'1'&x"D2BD",'1'&x"D2BE",'1'&x"D2BF",
+--'1'&x"D2C0",'1'&x"D2C1",'1'&x"D2C2",'1'&x"D2C3",'1'&x"D2C4",'1'&x"D2C5",'1'&x"D2C6",'1'&x"D2C7",'1'&x"D2C8",'1'&x"D2C9",'1'&x"D2CA",'1'&x"D2CB",'1'&x"D2CC",'1'&x"D2CD",'1'&x"D2CE",'1'&x"D2CF",
+--'1'&x"D2D0",'1'&x"D2D1",'1'&x"D2D2",'1'&x"D2D3",'1'&x"D2D4",'1'&x"D2D5",'1'&x"D2D6",'1'&x"D2D7",'1'&x"D2D8",'1'&x"D2D9",'1'&x"D2DA",'1'&x"D2DB",'1'&x"D2DC",'1'&x"D2DD",'1'&x"D2DE",'1'&x"D2DF",
+--'1'&x"D2E0",'1'&x"D2E1",'1'&x"D2E2",'1'&x"D2E3",'1'&x"D2E4",'1'&x"D2E5",'1'&x"D2E6",'1'&x"D2E7",'1'&x"D2E8",'1'&x"D2E9",'1'&x"D2EA",'1'&x"D2EB",'1'&x"D2EC",'1'&x"D2ED",'1'&x"D2EE",'1'&x"D2EF",
+--'1'&x"D2F0",'1'&x"D2F1",'1'&x"D2F2",'1'&x"D2F3",'1'&x"D2F4",'1'&x"D2F5",'1'&x"D2F6",'1'&x"D2F7",'1'&x"D2F8",'1'&x"D2F9",'1'&x"D2FA",'1'&x"D2FB",'1'&x"D2FC",'1'&x"D2FD",'1'&x"D2FE",'1'&x"D2FF",
+--'1'&x"D300",'1'&x"D301",'1'&x"D302",'1'&x"D303",'1'&x"D304",'1'&x"D305",'1'&x"D306",'1'&x"D307",'1'&x"D308",'1'&x"D309",'1'&x"D30A",'1'&x"D30B",'1'&x"D30C",'1'&x"D30D",'1'&x"D30E",'1'&x"D30F",
+--'1'&x"D310",'1'&x"D311",'1'&x"D312",'1'&x"D313",'1'&x"D314",'1'&x"D315",'1'&x"D316",'1'&x"D317",'1'&x"D318",'1'&x"D319",'1'&x"D31A",'1'&x"D31B",'1'&x"D31C",'1'&x"D31D",'1'&x"D31E",'1'&x"D31F",
+--'1'&x"D320",'1'&x"D321",'1'&x"D322",'1'&x"D323",'1'&x"D324",'1'&x"D325",'1'&x"D326",'1'&x"D327",'1'&x"D328",'1'&x"D329",'1'&x"D32A",'1'&x"D32B",'1'&x"D32C",'1'&x"D32D",'1'&x"D32E",'1'&x"D32F",
+--'1'&x"D330",'1'&x"D331",'1'&x"D332",'1'&x"D333",'1'&x"D334",'1'&x"D335",'1'&x"D336",'1'&x"D337",'1'&x"D338",'1'&x"D339",'1'&x"D33A",'1'&x"D33B",'1'&x"D33C",'1'&x"D33D",'1'&x"D33E",'1'&x"D33F",
+--'1'&x"D340",'1'&x"D341",'1'&x"D342",'1'&x"D343",'1'&x"D344",'1'&x"D345",'1'&x"D346",'1'&x"D347",'1'&x"D348",'1'&x"D349",'1'&x"D34A",'1'&x"D34B",'1'&x"D34C",'1'&x"D34D",'1'&x"D34E",'1'&x"D34F",
+--'1'&x"D350",'1'&x"D351",'1'&x"D352",'1'&x"D353",'1'&x"D354",'1'&x"D355",'1'&x"D356",'1'&x"D357",'1'&x"D358",'1'&x"D359",'1'&x"D35A",'1'&x"D35B",'1'&x"D35C",'1'&x"D35D",'1'&x"D35E",'1'&x"D35F",
+--'1'&x"D360",'1'&x"D361",'1'&x"D362",'1'&x"D363",'1'&x"D364",'1'&x"D365",'1'&x"D366",'1'&x"D367",'1'&x"D368",'1'&x"D369",'1'&x"D36A",'1'&x"D36B",'1'&x"D36C",'1'&x"D36D",'1'&x"D36E",'1'&x"D36F",
+--'1'&x"D370",'1'&x"D371",'1'&x"D372",'1'&x"D373",'1'&x"D374",'1'&x"D375",'1'&x"D376",'1'&x"D377",'1'&x"D378",'1'&x"D379",'1'&x"D37A",'1'&x"D37B",'1'&x"D37C",'1'&x"D37D",'1'&x"D37E",'1'&x"D37F",
+--'1'&x"D380",'1'&x"D381",'1'&x"D382",'1'&x"D383",'1'&x"D384",'1'&x"D385",'1'&x"D386",'1'&x"D387",'1'&x"D388",'1'&x"D389",'1'&x"D38A",'1'&x"D38B",'1'&x"D38C",'1'&x"D38D",'1'&x"D38E",'1'&x"D38F",
+--'1'&x"D390",'1'&x"D391",'1'&x"D392",'1'&x"D393",'1'&x"D394",'1'&x"D395",'1'&x"D396",'1'&x"D397",'1'&x"D398",'1'&x"D399",'1'&x"D39A",'1'&x"D39B",'1'&x"D39C",'1'&x"D39D",'1'&x"D39E",'1'&x"D39F",
+--'1'&x"D3A0",'1'&x"D3A1",'1'&x"D3A2",'1'&x"D3A3",'1'&x"D3A4",'1'&x"D3A5",'1'&x"D3A6",'1'&x"D3A7",'1'&x"D3A8",'1'&x"D3A9",'1'&x"D3AA",'1'&x"D3AB",'1'&x"D3AC",'1'&x"D3AD",'1'&x"D3AE",'1'&x"D3AF",
+--'1'&x"D3B0",'1'&x"D3B1",'1'&x"D3B2",'1'&x"D3B3",'1'&x"D3B4",'1'&x"D3B5",'1'&x"D3B6",'1'&x"D3B7",'1'&x"D3B8",'1'&x"D3B9",'1'&x"D3BA",'1'&x"D3BB",'1'&x"D3BC",'1'&x"D3BD",'1'&x"D3BE",'1'&x"D3BF",
+--'1'&x"D3C0",'1'&x"D3C1",'1'&x"D3C2",'1'&x"D3C3",'1'&x"D3C4",'1'&x"D3C5",'1'&x"D3C6",'1'&x"D3C7",'1'&x"D3C8",'1'&x"D3C9",'1'&x"D3CA",'1'&x"D3CB",'1'&x"D3CC",'1'&x"D3CD",'1'&x"D3CE",'1'&x"D3CF",
+--'1'&x"D3D0",'1'&x"D3D1",'1'&x"D3D2",'1'&x"D3D3",'1'&x"D3D4",'1'&x"D3D5",'1'&x"D3D6",'1'&x"D3D7",'1'&x"D3D8",'1'&x"D3D9",'1'&x"D3DA",'1'&x"D3DB",'1'&x"D3DC",'1'&x"D3DD",'1'&x"D3DE",'1'&x"D3DF",
+--'1'&x"D3E0",'1'&x"D3E1",'1'&x"D3E2",'1'&x"D3E3",'1'&x"D3E4",'1'&x"D3E5",'1'&x"D3E6",'1'&x"D3E7",'1'&x"D3E8",'1'&x"D3E9",'1'&x"D3EA",'1'&x"D3EB",'1'&x"D3EC",'1'&x"D3ED",'1'&x"D3EE",'1'&x"D3EF",
+--'1'&x"D3F0",'1'&x"D3F1",'1'&x"D3F2",'1'&x"D3F3",'1'&x"D3F4",'1'&x"D3F5",'1'&x"D3F6",'1'&x"D3F7",'1'&x"D3F8",'1'&x"D3F9",'1'&x"D3FA",'1'&x"D3FB",'1'&x"D3FC",'1'&x"D3FD",'1'&x"D3FE",'1'&x"D3FF",
+--'1'&x"D400",'1'&x"D401",'1'&x"D402",'1'&x"D403",'1'&x"D404",'1'&x"D405",'1'&x"D406",'1'&x"D407",'1'&x"D408",'1'&x"D409",'1'&x"D40A",'1'&x"D40B",'1'&x"D40C",'1'&x"D40D",'1'&x"D40E",'1'&x"D40F",
+--'1'&x"D410",'1'&x"D411",'1'&x"D412",'1'&x"D413",'1'&x"D414",'1'&x"D415",'1'&x"D416",'1'&x"D417",'1'&x"D418",'1'&x"D419",'1'&x"D41A",'1'&x"D41B",'1'&x"D41C",'1'&x"D41D",'1'&x"D41E",'1'&x"D41F",
+--'1'&x"D420",'1'&x"D421",'1'&x"D422",'1'&x"D423",'1'&x"D424",'1'&x"D425",'1'&x"D426",'1'&x"D427",'1'&x"D428",'1'&x"D429",'1'&x"D42A",'1'&x"D42B",'1'&x"D42C",'1'&x"D42D",'1'&x"D42E",'1'&x"D42F",
+--'1'&x"D430",'1'&x"D431",'1'&x"D432",'1'&x"D433",'1'&x"D434",'1'&x"D435",'1'&x"D436",'1'&x"D437",'1'&x"D438",'1'&x"D439",'1'&x"D43A",'1'&x"D43B",'1'&x"D43C",'1'&x"D43D",'1'&x"D43E",'1'&x"D43F",
+--'1'&x"D440",'1'&x"D441",'1'&x"D442",'1'&x"D443",'1'&x"D444",'1'&x"D445",'1'&x"D446",'1'&x"D447",'1'&x"D448",'1'&x"D449",'1'&x"D44A",'1'&x"D44B",'1'&x"D44C",'1'&x"D44D",'1'&x"D44E",'1'&x"D44F",
+--'1'&x"D450",'1'&x"D451",'1'&x"D452",'1'&x"D453",'1'&x"D454",'1'&x"D455",'1'&x"D456",'1'&x"D457",'1'&x"D458",'1'&x"D459",'1'&x"D45A",'1'&x"D45B",'1'&x"D45C",'1'&x"D45D",'1'&x"D45E",'1'&x"D45F",
+--'1'&x"D460",'1'&x"D461",'1'&x"D462",'1'&x"D463",'1'&x"D464",'1'&x"D465",'1'&x"D466",'1'&x"D467",'1'&x"D468",'1'&x"D469",'1'&x"D46A",'1'&x"D46B",'1'&x"D46C",'1'&x"D46D",'1'&x"D46E",'1'&x"D46F",
+--'1'&x"D470",'1'&x"D471",'1'&x"D472",'1'&x"D473",'1'&x"D474",'1'&x"D475",'1'&x"D476",'1'&x"D477",'1'&x"D478",'1'&x"D479",'1'&x"D47A",'1'&x"D47B",'1'&x"D47C",'1'&x"D47D",'1'&x"D47E",'1'&x"D47F",
+--'1'&x"D480",'1'&x"D481",'1'&x"D482",'1'&x"D483",'1'&x"D484",'1'&x"D485",'1'&x"D486",'1'&x"D487",'1'&x"D488",'1'&x"D489",'1'&x"D48A",'1'&x"D48B",'1'&x"D48C",'1'&x"D48D",'1'&x"D48E",'1'&x"D48F",
+--'1'&x"D490",'1'&x"D491",'1'&x"D492",'1'&x"D493",'1'&x"D494",'1'&x"D495",'1'&x"D496",'1'&x"D497",'1'&x"D498",'1'&x"D499",'1'&x"D49A",'1'&x"D49B",'1'&x"D49C",'1'&x"D49D",'1'&x"D49E",'1'&x"D49F",
+--'1'&x"D4A0",'1'&x"D4A1",'1'&x"D4A2",'1'&x"D4A3",'1'&x"D4A4",'1'&x"D4A5",'1'&x"D4A6",'1'&x"D4A7",'1'&x"D4A8",'1'&x"D4A9",'1'&x"D4AA",'1'&x"D4AB",'1'&x"D4AC",'1'&x"D4AD",'1'&x"D4AE",'1'&x"D4AF",
+--'1'&x"D4B0",'1'&x"D4B1",'1'&x"D4B2",'1'&x"D4B3",'1'&x"D4B4",'1'&x"D4B5",'1'&x"D4B6",'1'&x"D4B7",'1'&x"D4B8",'1'&x"D4B9",'1'&x"D4BA",'1'&x"D4BB",'1'&x"D4BC",'1'&x"D4BD",'1'&x"D4BE",'1'&x"D4BF",
+--'1'&x"D4C0",'1'&x"D4C1",'1'&x"D4C2",'1'&x"D4C3",'1'&x"D4C4",'1'&x"D4C5",'1'&x"D4C6",'1'&x"D4C7",'1'&x"D4C8",'1'&x"D4C9",'1'&x"D4CA",'1'&x"D4CB",'1'&x"D4CC",'1'&x"D4CD",'1'&x"D4CE",'1'&x"D4CF",
+--'1'&x"D4D0",'1'&x"D4D1",'1'&x"D4D2",'1'&x"D4D3",'1'&x"D4D4",'1'&x"D4D5",'1'&x"D4D6",'1'&x"D4D7",'1'&x"D4D8",'1'&x"D4D9",'1'&x"D4DA",'1'&x"D4DB",'1'&x"D4DC",'1'&x"D4DD",'1'&x"D4DE",'1'&x"D4DF",
+--'1'&x"D4E0",'1'&x"D4E1",'1'&x"D4E2",'1'&x"D4E3",'1'&x"D4E4",'1'&x"D4E5",'1'&x"D4E6",'1'&x"D4E7",'1'&x"D4E8",'1'&x"D4E9",'1'&x"D4EA",'1'&x"D4EB",'1'&x"D4EC",'1'&x"D4ED",'1'&x"D4EE",'1'&x"D4EF",
+--'1'&x"D4F0",'1'&x"D4F1",'1'&x"D4F2",'1'&x"D4F3",'1'&x"D4F4",'1'&x"D4F5",'1'&x"D4F6",'1'&x"D4F7",'1'&x"D4F8",'1'&x"D4F9",'1'&x"D4FA",'1'&x"D4FB",'1'&x"D4FC",'1'&x"D4FD",'1'&x"D4FE",'1'&x"D4FF",
+--'1'&x"D500",'1'&x"D501",'1'&x"D502",'1'&x"D503",'1'&x"D504",'1'&x"D505",'1'&x"D506",'1'&x"D507",'1'&x"D508",'1'&x"D509",'1'&x"D50A",'1'&x"D50B",'1'&x"D50C",'1'&x"D50D",'1'&x"D50E",'1'&x"D50F",
+--'1'&x"D510",'1'&x"D511",'1'&x"D512",'1'&x"D513",'1'&x"D514",'1'&x"D515",'1'&x"D516",'1'&x"D517",'1'&x"D518",'1'&x"D519",'1'&x"D51A",'1'&x"D51B",'1'&x"D51C",'1'&x"D51D",'1'&x"D51E",'1'&x"D51F",
+--'1'&x"D520",'1'&x"D521",'1'&x"D522",'1'&x"D523",'1'&x"D524",'1'&x"D525",'1'&x"D526",'1'&x"D527",'1'&x"D528",'1'&x"D529",'1'&x"D52A",'1'&x"D52B",'1'&x"D52C",'1'&x"D52D",'1'&x"D52E",'1'&x"D52F",
+--'1'&x"D530",'1'&x"D531",'1'&x"D532",'1'&x"D533",'1'&x"D534",'1'&x"D535",'1'&x"D536",'1'&x"D537",'1'&x"D538",'1'&x"D539",'1'&x"D53A",'1'&x"D53B",'1'&x"D53C",'1'&x"D53D",'1'&x"D53E",'1'&x"D53F",
+--'1'&x"D540",'1'&x"D541",'1'&x"D542",'1'&x"D543",'1'&x"D544",'1'&x"D545",'1'&x"D546",'1'&x"D547",'1'&x"D548",'1'&x"D549",'1'&x"D54A",'1'&x"D54B",'1'&x"D54C",'1'&x"D54D",'1'&x"D54E",'1'&x"D54F",
+--'1'&x"D550",'1'&x"D551",'1'&x"D552",'1'&x"D553",'1'&x"D554",'1'&x"D555",'1'&x"D556",'1'&x"D557",'1'&x"D558",'1'&x"D559",'1'&x"D55A",'1'&x"D55B",'1'&x"D55C",'1'&x"D55D",'1'&x"D55E",'1'&x"D55F",
+--'1'&x"D560",'1'&x"D561",'1'&x"D562",'1'&x"D563",'1'&x"D564",'1'&x"D565",'1'&x"D566",'1'&x"D567",'1'&x"D568",'1'&x"D569",'1'&x"D56A",'1'&x"D56B",'1'&x"D56C",'1'&x"D56D",'1'&x"D56E",'1'&x"D56F",
+--'1'&x"D570",'1'&x"D571",'1'&x"D572",'1'&x"D573",'1'&x"D574",'1'&x"D575",'1'&x"D576",'1'&x"D577",'1'&x"D578",'1'&x"D579",'1'&x"D57A",'1'&x"D57B",'1'&x"D57C",'1'&x"D57D",'1'&x"D57E",'1'&x"D57F",
+--'1'&x"D580",'1'&x"D581",'1'&x"D582",'1'&x"D583",'1'&x"D584",'1'&x"D585",'1'&x"D586",'1'&x"D587",'1'&x"D588",'1'&x"D589",'1'&x"D58A",'1'&x"D58B",'1'&x"D58C",'1'&x"D58D",'1'&x"D58E",'1'&x"D58F",
+--'1'&x"D590",'1'&x"D591",'1'&x"D592",'1'&x"D593",'1'&x"D594",'1'&x"D595",'1'&x"D596",'1'&x"D597",'1'&x"D598",'1'&x"D599",'1'&x"D59A",'1'&x"D59B",'1'&x"D59C",'1'&x"D59D",'1'&x"D59E",'1'&x"D59F",
+--'1'&x"D5A0",'1'&x"D5A1",'1'&x"D5A2",'1'&x"D5A3",'1'&x"D5A4",'1'&x"D5A5",'1'&x"D5A6",'1'&x"D5A7",'1'&x"D5A8",'1'&x"D5A9",'1'&x"D5AA",'1'&x"D5AB",'1'&x"D5AC",'1'&x"D5AD",'1'&x"D5AE",'1'&x"D5AF",
+--'1'&x"D5B0",'1'&x"D5B1",'1'&x"D5B2",'1'&x"D5B3",'1'&x"D5B4",'1'&x"D5B5",'1'&x"D5B6",'1'&x"D5B7",'1'&x"D5B8",'1'&x"D5B9",'1'&x"D5BA",'1'&x"D5BB",'1'&x"D5BC",'1'&x"D5BD",'1'&x"D5BE",'1'&x"D5BF",
+--'1'&x"D5C0",'1'&x"D5C1",'1'&x"D5C2",'1'&x"D5C3",'1'&x"D5C4",'1'&x"D5C5",'1'&x"D5C6",'1'&x"D5C7",'1'&x"D5C8",'1'&x"D5C9",'1'&x"D5CA",'1'&x"D5CB",'1'&x"D5CC",'1'&x"D5CD",'1'&x"D5CE",'1'&x"D5CF",
+--'1'&x"D5D0",'1'&x"D5D1",'1'&x"D5D2",'1'&x"D5D3",'1'&x"D5D4",'1'&x"D5D5",'1'&x"D5D6",'1'&x"D5D7",'1'&x"D5D8",'1'&x"D5D9",'1'&x"D5DA",'1'&x"D5DB",'1'&x"D5DC",'1'&x"D5DD",'1'&x"D5DE",'1'&x"D5DF",
+--'1'&x"D5E0",'1'&x"D5E1",'1'&x"D5E2",'1'&x"D5E3",'1'&x"D5E4",'1'&x"D5E5",'1'&x"D5E6",'1'&x"D5E7",'1'&x"D5E8",'1'&x"D5E9",'1'&x"D5EA",'1'&x"D5EB",'1'&x"D5EC",'1'&x"D5ED",'1'&x"D5EE",'1'&x"D5EF",
+--'1'&x"D5F0",'1'&x"D5F1",'1'&x"D5F2",'1'&x"D5F3",'1'&x"D5F4",'1'&x"D5F5",'1'&x"D5F6",'1'&x"D5F7",'1'&x"D5F8",'1'&x"D5F9",'1'&x"D5FA",'1'&x"D5FB",'1'&x"D5FC",'1'&x"D5FD",'1'&x"D5FE",'1'&x"D5FF",
+--'1'&x"D600",'1'&x"D601",'1'&x"D602",'1'&x"D603",'1'&x"D604",'1'&x"D605",'1'&x"D606",'1'&x"D607",'1'&x"D608",'1'&x"D609",'1'&x"D60A",'1'&x"D60B",'1'&x"D60C",'1'&x"D60D",'1'&x"D60E",'1'&x"D60F",
+--'1'&x"D610",'1'&x"D611",'1'&x"D612",'1'&x"D613",'1'&x"D614",'1'&x"D615",'1'&x"D616",'1'&x"D617",'1'&x"D618",'1'&x"D619",'1'&x"D61A",'1'&x"D61B",'1'&x"D61C",'1'&x"D61D",'1'&x"D61E",'1'&x"D61F",
+--'1'&x"D620",'1'&x"D621",'1'&x"D622",'1'&x"D623",'1'&x"D624",'1'&x"D625",'1'&x"D626",'1'&x"D627",'1'&x"D628",'1'&x"D629",'1'&x"D62A",'1'&x"D62B",'1'&x"D62C",'1'&x"D62D",'1'&x"D62E",'1'&x"D62F",
+--'1'&x"D630",'1'&x"D631",'1'&x"D632",'1'&x"D633",'1'&x"D634",'1'&x"D635",'1'&x"D636",'1'&x"D637",'1'&x"D638",'1'&x"D639",'1'&x"D63A",'1'&x"D63B",'1'&x"D63C",'1'&x"D63D",'1'&x"D63E",'1'&x"D63F",
+--'1'&x"D640",'1'&x"D641",'1'&x"D642",'1'&x"D643",'1'&x"D644",'1'&x"D645",'1'&x"D646",'1'&x"D647",'1'&x"D648",'1'&x"D649",'1'&x"D64A",'1'&x"D64B",'1'&x"D64C",'1'&x"D64D",'1'&x"D64E",'1'&x"D64F",
+--'1'&x"D650",'1'&x"D651",'1'&x"D652",'1'&x"D653",'1'&x"D654",'1'&x"D655",'1'&x"D656",'1'&x"D657",'1'&x"D658",'1'&x"D659",'1'&x"D65A",'1'&x"D65B",'1'&x"D65C",'1'&x"D65D",'1'&x"D65E",'1'&x"D65F",
+--'1'&x"D660",'1'&x"D661",'1'&x"D662",'1'&x"D663",'1'&x"D664",'1'&x"D665",'1'&x"D666",'1'&x"D667",'1'&x"D668",'1'&x"D669",'1'&x"D66A",'1'&x"D66B",'1'&x"D66C",'1'&x"D66D",'1'&x"D66E",'1'&x"D66F",
+--'1'&x"D670",'1'&x"D671",'1'&x"D672",'1'&x"D673",'1'&x"D674",'1'&x"D675",'1'&x"D676",'1'&x"D677",'1'&x"D678",'1'&x"D679",'1'&x"D67A",'1'&x"D67B",'1'&x"D67C",'1'&x"D67D",'1'&x"D67E",'1'&x"D67F",
+--'1'&x"D680",'1'&x"D681",'1'&x"D682",'1'&x"D683",'1'&x"D684",'1'&x"D685",'1'&x"D686",'1'&x"D687",'1'&x"D688",'1'&x"D689",'1'&x"D68A",'1'&x"D68B",'1'&x"D68C",'1'&x"D68D",'1'&x"D68E",'1'&x"D68F",
+--'1'&x"D690",'1'&x"D691",'1'&x"D692",'1'&x"D693",'1'&x"D694",'1'&x"D695",'1'&x"D696",'1'&x"D697",'1'&x"D698",'1'&x"D699",'1'&x"D69A",'1'&x"D69B",'1'&x"D69C",'1'&x"D69D",'1'&x"D69E",'1'&x"D69F",
+--'1'&x"D6A0",'1'&x"D6A1",'1'&x"D6A2",'1'&x"D6A3",'1'&x"D6A4",'1'&x"D6A5",'1'&x"D6A6",'1'&x"D6A7",'1'&x"D6A8",'1'&x"D6A9",'1'&x"D6AA",'1'&x"D6AB",'1'&x"D6AC",'1'&x"D6AD",'1'&x"D6AE",'1'&x"D6AF",
+--'1'&x"D6B0",'1'&x"D6B1",'1'&x"D6B2",'1'&x"D6B3",'1'&x"D6B4",'1'&x"D6B5",'1'&x"D6B6",'1'&x"D6B7",'1'&x"D6B8",'1'&x"D6B9",'1'&x"D6BA",'1'&x"D6BB",'1'&x"D6BC",'1'&x"D6BD",'1'&x"D6BE",'1'&x"D6BF",
+--'1'&x"D6C0",'1'&x"D6C1",'1'&x"D6C2",'1'&x"D6C3",'1'&x"D6C4",'1'&x"D6C5",'1'&x"D6C6",'1'&x"D6C7",'1'&x"D6C8",'1'&x"D6C9",'1'&x"D6CA",'1'&x"D6CB",'1'&x"D6CC",'1'&x"D6CD",'1'&x"D6CE",'1'&x"D6CF",
+--'1'&x"D6D0",'1'&x"D6D1",'1'&x"D6D2",'1'&x"D6D3",'1'&x"D6D4",'1'&x"D6D5",'1'&x"D6D6",'1'&x"D6D7",'1'&x"D6D8",'1'&x"D6D9",'1'&x"D6DA",'1'&x"D6DB",'1'&x"D6DC",'1'&x"D6DD",'1'&x"D6DE",'1'&x"D6DF",
+--'1'&x"D6E0",'1'&x"D6E1",'1'&x"D6E2",'1'&x"D6E3",'1'&x"D6E4",'1'&x"D6E5",'1'&x"D6E6",'1'&x"D6E7",'1'&x"D6E8",'1'&x"D6E9",'1'&x"D6EA",'1'&x"D6EB",'1'&x"D6EC",'1'&x"D6ED",'1'&x"D6EE",'1'&x"D6EF",
+--'1'&x"D6F0",'1'&x"D6F1",'1'&x"D6F2",'1'&x"D6F3",'1'&x"D6F4",'1'&x"D6F5",'1'&x"D6F6",'1'&x"D6F7",'1'&x"D6F8",'1'&x"D6F9",'1'&x"D6FA",'1'&x"D6FB",'1'&x"D6FC",'1'&x"D6FD",'1'&x"D6FE",'1'&x"D6FF",
+--'1'&x"D700",'1'&x"D701",'1'&x"D702",'1'&x"D703",'1'&x"D704",'1'&x"D705",'1'&x"D706",'1'&x"D707",'1'&x"D708",'1'&x"D709",'1'&x"D70A",'1'&x"D70B",'1'&x"D70C",'1'&x"D70D",'1'&x"D70E",'1'&x"D70F",
+--'1'&x"D710",'1'&x"D711",'1'&x"D712",'1'&x"D713",'1'&x"D714",'1'&x"D715",'1'&x"D716",'1'&x"D717",'1'&x"D718",'1'&x"D719",'1'&x"D71A",'1'&x"D71B",'1'&x"D71C",'1'&x"D71D",'1'&x"D71E",'1'&x"D71F",
+--'1'&x"D720",'1'&x"D721",'1'&x"D722",'1'&x"D723",'1'&x"D724",'1'&x"D725",'1'&x"D726",'1'&x"D727",'1'&x"D728",'1'&x"D729",'1'&x"D72A",'1'&x"D72B",'1'&x"D72C",'1'&x"D72D",'1'&x"D72E",'1'&x"D72F",
+--'1'&x"D730",'1'&x"D731",'1'&x"D732",'1'&x"D733",'1'&x"D734",'1'&x"D735",'1'&x"D736",'1'&x"D737",'1'&x"D738",'1'&x"D739",'1'&x"D73A",'1'&x"D73B",'1'&x"D73C",'1'&x"D73D",'1'&x"D73E",'1'&x"D73F",
+--'1'&x"D740",'1'&x"D741",'1'&x"D742",'1'&x"D743",'1'&x"D744",'1'&x"D745",'1'&x"D746",'1'&x"D747",'1'&x"D748",'1'&x"D749",'1'&x"D74A",'1'&x"D74B",'1'&x"D74C",'1'&x"D74D",'1'&x"D74E",'1'&x"D74F",
+--'1'&x"D750",'1'&x"D751",'1'&x"D752",'1'&x"D753",'1'&x"D754",'1'&x"D755",'1'&x"D756",'1'&x"D757",'1'&x"D758",'1'&x"D759",'1'&x"D75A",'1'&x"D75B",'1'&x"D75C",'1'&x"D75D",'1'&x"D75E",'1'&x"D75F",
+--'1'&x"D760",'1'&x"D761",'1'&x"D762",'1'&x"D763",'1'&x"D764",'1'&x"D765",'1'&x"D766",'1'&x"D767",'1'&x"D768",'1'&x"D769",'1'&x"D76A",'1'&x"D76B",'1'&x"D76C",'1'&x"D76D",'1'&x"D76E",'1'&x"D76F",
+--'1'&x"D770",'1'&x"D771",'1'&x"D772",'1'&x"D773",'1'&x"D774",'1'&x"D775",'1'&x"D776",'1'&x"D777",'1'&x"D778",'1'&x"D779",'1'&x"D77A",'1'&x"D77B",'1'&x"D77C",'1'&x"D77D",'1'&x"D77E",'1'&x"D77F",
+--'1'&x"D780",'1'&x"D781",'1'&x"D782",'1'&x"D783",'1'&x"D784",'1'&x"D785",'1'&x"D786",'1'&x"D787",'1'&x"D788",'1'&x"D789",'1'&x"D78A",'1'&x"D78B",'1'&x"D78C",'1'&x"D78D",'1'&x"D78E",'1'&x"D78F",
+--'1'&x"D790",'1'&x"D791",'1'&x"D792",'1'&x"D793",'1'&x"D794",'1'&x"D795",'1'&x"D796",'1'&x"D797",'1'&x"D798",'1'&x"D799",'1'&x"D79A",'1'&x"D79B",'1'&x"D79C",'1'&x"D79D",'1'&x"D79E",'1'&x"D79F",
+--'1'&x"D7A0",'1'&x"D7A1",'1'&x"D7A2",'1'&x"D7A3",'1'&x"D7A4",'1'&x"D7A5",'1'&x"D7A6",'1'&x"D7A7",'1'&x"D7A8",'1'&x"D7A9",'1'&x"D7AA",'1'&x"D7AB",'1'&x"D7AC",'1'&x"D7AD",'1'&x"D7AE",'1'&x"D7AF",
+--'1'&x"D7B0",'1'&x"D7B1",'1'&x"D7B2",'1'&x"D7B3",'1'&x"D7B4",'1'&x"D7B5",'1'&x"D7B6",'1'&x"D7B7",'1'&x"D7B8",'1'&x"D7B9",'1'&x"D7BA",'1'&x"D7BB",'1'&x"D7BC",'1'&x"D7BD",'1'&x"D7BE",'1'&x"D7BF",
+--'1'&x"D7C0",'1'&x"D7C1",'1'&x"D7C2",'1'&x"D7C3",'1'&x"D7C4",'1'&x"D7C5",'1'&x"D7C6",'1'&x"D7C7",'1'&x"D7C8",'1'&x"D7C9",'1'&x"D7CA",'1'&x"D7CB",'1'&x"D7CC",'1'&x"D7CD",'1'&x"D7CE",'1'&x"D7CF",
+--'1'&x"D7D0",'1'&x"D7D1",'1'&x"D7D2",'1'&x"D7D3",'1'&x"D7D4",'1'&x"D7D5",'1'&x"D7D6",'1'&x"D7D7",'1'&x"D7D8",'1'&x"D7D9",'1'&x"D7DA",'1'&x"D7DB",'1'&x"D7DC",'1'&x"D7DD",'1'&x"D7DE",'1'&x"D7DF",
+--'1'&x"D7E0",'1'&x"D7E1",'1'&x"D7E2",'1'&x"D7E3",'1'&x"D7E4",'1'&x"D7E5",'1'&x"D7E6",'1'&x"D7E7",'1'&x"D7E8",'1'&x"D7E9",'1'&x"D7EA",'1'&x"D7EB",'1'&x"D7EC",'1'&x"D7ED",'1'&x"D7EE",'1'&x"D7EF",
+--'1'&x"D7F0",'1'&x"D7F1",'1'&x"D7F2",'1'&x"D7F3",'1'&x"D7F4",'1'&x"D7F5",'1'&x"D7F6",'1'&x"D7F7",'1'&x"D7F8",'1'&x"D7F9",'1'&x"D7FA",'1'&x"D7FB",'1'&x"D7FC",'1'&x"D7FD",'1'&x"D7FE",'1'&x"D7FF",
+--'1'&x"D800",'1'&x"D801",'1'&x"D802",'1'&x"D803",'1'&x"D804",'1'&x"D805",'1'&x"D806",'1'&x"D807",'1'&x"D808",'1'&x"D809",'1'&x"D80A",'1'&x"D80B",'1'&x"D80C",'1'&x"D80D",'1'&x"D80E",'1'&x"D80F",
+--'1'&x"D810",'1'&x"D811",'1'&x"D812",'1'&x"D813",'1'&x"D814",'1'&x"D815",'1'&x"D816",'1'&x"D817",'1'&x"D818",'1'&x"D819",'1'&x"D81A",'1'&x"D81B",'1'&x"D81C",'1'&x"D81D",'1'&x"D81E",'1'&x"D81F",
+--'1'&x"D820",'1'&x"D821",'1'&x"D822",'1'&x"D823",'1'&x"D824",'1'&x"D825",'1'&x"D826",'1'&x"D827",'1'&x"D828",'1'&x"D829",'1'&x"D82A",'1'&x"D82B",'1'&x"D82C",'1'&x"D82D",'1'&x"D82E",'1'&x"D82F",
+--'1'&x"D830",'1'&x"D831",'1'&x"D832",'1'&x"D833",'1'&x"D834",'1'&x"D835",'1'&x"D836",'1'&x"D837",'1'&x"D838",'1'&x"D839",'1'&x"D83A",'1'&x"D83B",'1'&x"D83C",'1'&x"D83D",'1'&x"D83E",'1'&x"D83F",
+--'1'&x"D840",'1'&x"D841",'1'&x"D842",'1'&x"D843",'1'&x"D844",'1'&x"D845",'1'&x"D846",'1'&x"D847",'1'&x"D848",'1'&x"D849",'1'&x"D84A",'1'&x"D84B",'1'&x"D84C",'1'&x"D84D",'1'&x"D84E",'1'&x"D84F",
+--'1'&x"D850",'1'&x"D851",'1'&x"D852",'1'&x"D853",'1'&x"D854",'1'&x"D855",'1'&x"D856",'1'&x"D857",'1'&x"D858",'1'&x"D859",'1'&x"D85A",'1'&x"D85B",'1'&x"D85C",'1'&x"D85D",'1'&x"D85E",'1'&x"D85F",
+--'1'&x"D860",'1'&x"D861",'1'&x"D862",'1'&x"D863",'1'&x"D864",'1'&x"D865",'1'&x"D866",'1'&x"D867",'1'&x"D868",'1'&x"D869",'1'&x"D86A",'1'&x"D86B",'1'&x"D86C",'1'&x"D86D",'1'&x"D86E",'1'&x"D86F",
+--'1'&x"D870",'1'&x"D871",'1'&x"D872",'1'&x"D873",'1'&x"D874",'1'&x"D875",'1'&x"D876",'1'&x"D877",'1'&x"D878",'1'&x"D879",'1'&x"D87A",'1'&x"D87B",'1'&x"D87C",'1'&x"D87D",'1'&x"D87E",'1'&x"D87F",
+--'1'&x"D880",'1'&x"D881",'1'&x"D882",'1'&x"D883",'1'&x"D884",'1'&x"D885",'1'&x"D886",'1'&x"D887",'1'&x"D888",'1'&x"D889",'1'&x"D88A",'1'&x"D88B",'1'&x"D88C",'1'&x"D88D",'1'&x"D88E",'1'&x"D88F",
+--'1'&x"D890",'1'&x"D891",'1'&x"D892",'1'&x"D893",'1'&x"D894",'1'&x"D895",'1'&x"D896",'1'&x"D897",'1'&x"D898",'1'&x"D899",'1'&x"D89A",'1'&x"D89B",'1'&x"D89C",'1'&x"D89D",'1'&x"D89E",'1'&x"D89F",
+--'1'&x"D8A0",'1'&x"D8A1",'1'&x"D8A2",'1'&x"D8A3",'1'&x"D8A4",'1'&x"D8A5",'1'&x"D8A6",'1'&x"D8A7",'1'&x"D8A8",'1'&x"D8A9",'1'&x"D8AA",'1'&x"D8AB",'1'&x"D8AC",'1'&x"D8AD",'1'&x"D8AE",'1'&x"D8AF",
+--'1'&x"D8B0",'1'&x"D8B1",'1'&x"D8B2",'1'&x"D8B3",'1'&x"D8B4",'1'&x"D8B5",'1'&x"D8B6",'1'&x"D8B7",'1'&x"D8B8",'1'&x"D8B9",'1'&x"D8BA",'1'&x"D8BB",'1'&x"D8BC",'1'&x"D8BD",'1'&x"D8BE",'1'&x"D8BF",
+--'1'&x"D8C0",'1'&x"D8C1",'1'&x"D8C2",'1'&x"D8C3",'1'&x"D8C4",'1'&x"D8C5",'1'&x"D8C6",'1'&x"D8C7",'1'&x"D8C8",'1'&x"D8C9",'1'&x"D8CA",'1'&x"D8CB",'1'&x"D8CC",'1'&x"D8CD",'1'&x"D8CE",'1'&x"D8CF",
+--'1'&x"D8D0",'1'&x"D8D1",'1'&x"D8D2",'1'&x"D8D3",'1'&x"D8D4",'1'&x"D8D5",'1'&x"D8D6",'1'&x"D8D7",'1'&x"D8D8",'1'&x"D8D9",'1'&x"D8DA",'1'&x"D8DB",'1'&x"D8DC",'1'&x"D8DD",'1'&x"D8DE",'1'&x"D8DF",
+--'1'&x"D8E0",'1'&x"D8E1",'1'&x"D8E2",'1'&x"D8E3",'1'&x"D8E4",'1'&x"D8E5",'1'&x"D8E6",'1'&x"D8E7",'1'&x"D8E8",'1'&x"D8E9",'1'&x"D8EA",'1'&x"D8EB",'1'&x"D8EC",'1'&x"D8ED",'1'&x"D8EE",'1'&x"D8EF",
+--'1'&x"D8F0",'1'&x"D8F1",'1'&x"D8F2",'1'&x"D8F3",'1'&x"D8F4",'1'&x"D8F5",'1'&x"D8F6",'1'&x"D8F7",'1'&x"D8F8",'1'&x"D8F9",'1'&x"D8FA",'1'&x"D8FB",'1'&x"D8FC",'1'&x"D8FD",'1'&x"D8FE",'1'&x"D8FF",
+--'1'&x"D900",'1'&x"D901",'1'&x"D902",'1'&x"D903",'1'&x"D904",'1'&x"D905",'1'&x"D906",'1'&x"D907",'1'&x"D908",'1'&x"D909",'1'&x"D90A",'1'&x"D90B",'1'&x"D90C",'1'&x"D90D",'1'&x"D90E",'1'&x"D90F",
+--'1'&x"D910",'1'&x"D911",'1'&x"D912",'1'&x"D913",'1'&x"D914",'1'&x"D915",'1'&x"D916",'1'&x"D917",'1'&x"D918",'1'&x"D919",'1'&x"D91A",'1'&x"D91B",'1'&x"D91C",'1'&x"D91D",'1'&x"D91E",'1'&x"D91F",
+--'1'&x"D920",'1'&x"D921",'1'&x"D922",'1'&x"D923",'1'&x"D924",'1'&x"D925",'1'&x"D926",'1'&x"D927",'1'&x"D928",'1'&x"D929",'1'&x"D92A",'1'&x"D92B",'1'&x"D92C",'1'&x"D92D",'1'&x"D92E",'1'&x"D92F",
+--'1'&x"D930",'1'&x"D931",'1'&x"D932",'1'&x"D933",'1'&x"D934",'1'&x"D935",'1'&x"D936",'1'&x"D937",'1'&x"D938",'1'&x"D939",'1'&x"D93A",'1'&x"D93B",'1'&x"D93C",'1'&x"D93D",'1'&x"D93E",'1'&x"D93F",
+--'1'&x"D940",'1'&x"D941",'1'&x"D942",'1'&x"D943",'1'&x"D944",'1'&x"D945",'1'&x"D946",'1'&x"D947",'1'&x"D948",'1'&x"D949",'1'&x"D94A",'1'&x"D94B",'1'&x"D94C",'1'&x"D94D",'1'&x"D94E",'1'&x"D94F",
+--'1'&x"D950",'1'&x"D951",'1'&x"D952",'1'&x"D953",'1'&x"D954",'1'&x"D955",'1'&x"D956",'1'&x"D957",'1'&x"D958",'1'&x"D959",'1'&x"D95A",'1'&x"D95B",'1'&x"D95C",'1'&x"D95D",'1'&x"D95E",'1'&x"D95F",
+--'1'&x"D960",'1'&x"D961",'1'&x"D962",'1'&x"D963",'1'&x"D964",'1'&x"D965",'1'&x"D966",'1'&x"D967",'1'&x"D968",'1'&x"D969",'1'&x"D96A",'1'&x"D96B",'1'&x"D96C",'1'&x"D96D",'1'&x"D96E",'1'&x"D96F",
+--'1'&x"D970",'1'&x"D971",'1'&x"D972",'1'&x"D973",'1'&x"D974",'1'&x"D975",'1'&x"D976",'1'&x"D977",'1'&x"D978",'1'&x"D979",'1'&x"D97A",'1'&x"D97B",'1'&x"D97C",'1'&x"D97D",'1'&x"D97E",'1'&x"D97F",
+--'1'&x"D980",'1'&x"D981",'1'&x"D982",'1'&x"D983",'1'&x"D984",'1'&x"D985",'1'&x"D986",'1'&x"D987",'1'&x"D988",'1'&x"D989",'1'&x"D98A",'1'&x"D98B",'1'&x"D98C",'1'&x"D98D",'1'&x"D98E",'1'&x"D98F",
+--'1'&x"D990",'1'&x"D991",'1'&x"D992",'1'&x"D993",'1'&x"D994",'1'&x"D995",'1'&x"D996",'1'&x"D997",'1'&x"D998",'1'&x"D999",'1'&x"D99A",'1'&x"D99B",'1'&x"D99C",'1'&x"D99D",'1'&x"D99E",'1'&x"D99F",
+--'1'&x"D9A0",'1'&x"D9A1",'1'&x"D9A2",'1'&x"D9A3",'1'&x"D9A4",'1'&x"D9A5",'1'&x"D9A6",'1'&x"D9A7",'1'&x"D9A8",'1'&x"D9A9",'1'&x"D9AA",'1'&x"D9AB",'1'&x"D9AC",'1'&x"D9AD",'1'&x"D9AE",'1'&x"D9AF",
+--'1'&x"D9B0",'1'&x"D9B1",'1'&x"D9B2",'1'&x"D9B3",'1'&x"D9B4",'1'&x"D9B5",'1'&x"D9B6",'1'&x"D9B7",'1'&x"D9B8",'1'&x"D9B9",'1'&x"D9BA",'1'&x"D9BB",'1'&x"D9BC",'1'&x"D9BD",'1'&x"D9BE",'1'&x"D9BF",
+--'1'&x"D9C0",'1'&x"D9C1",'1'&x"D9C2",'1'&x"D9C3",'1'&x"D9C4",'1'&x"D9C5",'1'&x"D9C6",'1'&x"D9C7",'1'&x"D9C8",'1'&x"D9C9",'1'&x"D9CA",'1'&x"D9CB",'1'&x"D9CC",'1'&x"D9CD",'1'&x"D9CE",'1'&x"D9CF",
+--'1'&x"D9D0",'1'&x"D9D1",'1'&x"D9D2",'1'&x"D9D3",'1'&x"D9D4",'1'&x"D9D5",'1'&x"D9D6",'1'&x"D9D7",'1'&x"D9D8",'1'&x"D9D9",'1'&x"D9DA",'1'&x"D9DB",'1'&x"D9DC",'1'&x"D9DD",'1'&x"D9DE",'1'&x"D9DF",
+--'1'&x"D9E0",'1'&x"D9E1",'1'&x"D9E2",'1'&x"D9E3",'1'&x"D9E4",'1'&x"D9E5",'1'&x"D9E6",'1'&x"D9E7",'1'&x"D9E8",'1'&x"D9E9",'1'&x"D9EA",'1'&x"D9EB",'1'&x"D9EC",'1'&x"D9ED",'1'&x"D9EE",'1'&x"D9EF",
+--'1'&x"D9F0",'1'&x"D9F1",'1'&x"D9F2",'1'&x"D9F3",'1'&x"D9F4",'1'&x"D9F5",'1'&x"D9F6",'1'&x"D9F7",'1'&x"D9F8",'1'&x"D9F9",'1'&x"D9FA",'1'&x"D9FB",'1'&x"D9FC",'1'&x"D9FD",'1'&x"D9FE",'1'&x"D9FF",
+--'1'&x"DA00",'1'&x"DA01",'1'&x"DA02",'1'&x"DA03",'1'&x"DA04",'1'&x"DA05",'1'&x"DA06",'1'&x"DA07",'1'&x"DA08",'1'&x"DA09",'1'&x"DA0A",'1'&x"DA0B",'1'&x"DA0C",'1'&x"DA0D",'1'&x"DA0E",'1'&x"DA0F",
+--'1'&x"DA10",'1'&x"DA11",'1'&x"DA12",'1'&x"DA13",'1'&x"DA14",'1'&x"DA15",'1'&x"DA16",'1'&x"DA17",'1'&x"DA18",'1'&x"DA19",'1'&x"DA1A",'1'&x"DA1B",'1'&x"DA1C",'1'&x"DA1D",'1'&x"DA1E",'1'&x"DA1F",
+--'1'&x"DA20",'1'&x"DA21",'1'&x"DA22",'1'&x"DA23",'1'&x"DA24",'1'&x"DA25",'1'&x"DA26",'1'&x"DA27",'1'&x"DA28",'1'&x"DA29",'1'&x"DA2A",'1'&x"DA2B",'1'&x"DA2C",'1'&x"DA2D",'1'&x"DA2E",'1'&x"DA2F",
+--'1'&x"DA30",'1'&x"DA31",'1'&x"DA32",'1'&x"DA33",'1'&x"DA34",'1'&x"DA35",'1'&x"DA36",'1'&x"DA37",'1'&x"DA38",'1'&x"DA39",'1'&x"DA3A",'1'&x"DA3B",'1'&x"DA3C",'1'&x"DA3D",'1'&x"DA3E",'1'&x"DA3F",
+--'1'&x"DA40",'1'&x"DA41",'1'&x"DA42",'1'&x"DA43",'1'&x"DA44",'1'&x"DA45",'1'&x"DA46",'1'&x"DA47",'1'&x"DA48",'1'&x"DA49",'1'&x"DA4A",'1'&x"DA4B",'1'&x"DA4C",'1'&x"DA4D",'1'&x"DA4E",'1'&x"DA4F",
+--'1'&x"DA50",'1'&x"DA51",'1'&x"DA52",'1'&x"DA53",'1'&x"DA54",'1'&x"DA55",'1'&x"DA56",'1'&x"DA57",'1'&x"DA58",'1'&x"DA59",'1'&x"DA5A",'1'&x"DA5B",'1'&x"DA5C",'1'&x"DA5D",'1'&x"DA5E",'1'&x"DA5F",
+--'1'&x"DA60",'1'&x"DA61",'1'&x"DA62",'1'&x"DA63",'1'&x"DA64",'1'&x"DA65",'1'&x"DA66",'1'&x"DA67",'1'&x"DA68",'1'&x"DA69",'1'&x"DA6A",'1'&x"DA6B",'1'&x"DA6C",'1'&x"DA6D",'1'&x"DA6E",'1'&x"DA6F",
+--'1'&x"DA70",'1'&x"DA71",'1'&x"DA72",'1'&x"DA73",'1'&x"DA74",'1'&x"DA75",'1'&x"DA76",'1'&x"DA77",'1'&x"DA78",'1'&x"DA79",'1'&x"DA7A",'1'&x"DA7B",'1'&x"DA7C",'1'&x"DA7D",'1'&x"DA7E",'1'&x"DA7F",
+--'1'&x"DA80",'1'&x"DA81",'1'&x"DA82",'1'&x"DA83",'1'&x"DA84",'1'&x"DA85",'1'&x"DA86",'1'&x"DA87",'1'&x"DA88",'1'&x"DA89",'1'&x"DA8A",'1'&x"DA8B",'1'&x"DA8C",'1'&x"DA8D",'1'&x"DA8E",'1'&x"DA8F",
+--'1'&x"DA90",'1'&x"DA91",'1'&x"DA92",'1'&x"DA93",'1'&x"DA94",'1'&x"DA95",'1'&x"DA96",'1'&x"DA97",'1'&x"DA98",'1'&x"DA99",'1'&x"DA9A",'1'&x"DA9B",'1'&x"DA9C",'1'&x"DA9D",'1'&x"DA9E",'1'&x"DA9F",
+--'1'&x"DAA0",'1'&x"DAA1",'1'&x"DAA2",'1'&x"DAA3",'1'&x"DAA4",'1'&x"DAA5",'1'&x"DAA6",'1'&x"DAA7",'1'&x"DAA8",'1'&x"DAA9",'1'&x"DAAA",'1'&x"DAAB",'1'&x"DAAC",'1'&x"DAAD",'1'&x"DAAE",'1'&x"DAAF",
+--'1'&x"DAB0",'1'&x"DAB1",'1'&x"DAB2",'1'&x"DAB3",'1'&x"DAB4",'1'&x"DAB5",'1'&x"DAB6",'1'&x"DAB7",'1'&x"DAB8",'1'&x"DAB9",'1'&x"DABA",'1'&x"DABB",'1'&x"DABC",'1'&x"DABD",'1'&x"DABE",'1'&x"DABF",
+--'1'&x"DAC0",'1'&x"DAC1",'1'&x"DAC2",'1'&x"DAC3",'1'&x"DAC4",'1'&x"DAC5",'1'&x"DAC6",'1'&x"DAC7",'1'&x"DAC8",'1'&x"DAC9",'1'&x"DACA",'1'&x"DACB",'1'&x"DACC",'1'&x"DACD",'1'&x"DACE",'1'&x"DACF",
+--'1'&x"DAD0",'1'&x"DAD1",'1'&x"DAD2",'1'&x"DAD3",'1'&x"DAD4",'1'&x"DAD5",'1'&x"DAD6",'1'&x"DAD7",'1'&x"DAD8",'1'&x"DAD9",'1'&x"DADA",'1'&x"DADB",'1'&x"DADC",'1'&x"DADD",'1'&x"DADE",'1'&x"DADF",
+--'1'&x"DAE0",'1'&x"DAE1",'1'&x"DAE2",'1'&x"DAE3",'1'&x"DAE4",'1'&x"DAE5",'1'&x"DAE6",'1'&x"DAE7",'1'&x"DAE8",'1'&x"DAE9",'1'&x"DAEA",'1'&x"DAEB",'1'&x"DAEC",'1'&x"DAED",'1'&x"DAEE",'1'&x"DAEF",
+--'1'&x"DAF0",'1'&x"DAF1",'1'&x"DAF2",'1'&x"DAF3",'1'&x"DAF4",'1'&x"DAF5",'1'&x"DAF6",'1'&x"DAF7",'1'&x"DAF8",'1'&x"DAF9",'1'&x"DAFA",'1'&x"DAFB",'1'&x"DAFC",'1'&x"DAFD",'1'&x"DAFE",'1'&x"DAFF",
+--'1'&x"DB00",'1'&x"DB01",'1'&x"DB02",'1'&x"DB03",'1'&x"DB04",'1'&x"DB05",'1'&x"DB06",'1'&x"DB07",'1'&x"DB08",'1'&x"DB09",'1'&x"DB0A",'1'&x"DB0B",'1'&x"DB0C",'1'&x"DB0D",'1'&x"DB0E",'1'&x"DB0F",
+--'1'&x"DB10",'1'&x"DB11",'1'&x"DB12",'1'&x"DB13",'1'&x"DB14",'1'&x"DB15",'1'&x"DB16",'1'&x"DB17",'1'&x"DB18",'1'&x"DB19",'1'&x"DB1A",'1'&x"DB1B",'1'&x"DB1C",'1'&x"DB1D",'1'&x"DB1E",'1'&x"DB1F",
+--'1'&x"DB20",'1'&x"DB21",'1'&x"DB22",'1'&x"DB23",'1'&x"DB24",'1'&x"DB25",'1'&x"DB26",'1'&x"DB27",'1'&x"DB28",'1'&x"DB29",'1'&x"DB2A",'1'&x"DB2B",'1'&x"DB2C",'1'&x"DB2D",'1'&x"DB2E",'1'&x"DB2F",
+--'1'&x"DB30",'1'&x"DB31",'1'&x"DB32",'1'&x"DB33",'1'&x"DB34",'1'&x"DB35",'1'&x"DB36",'1'&x"DB37",'1'&x"DB38",'1'&x"DB39",'1'&x"DB3A",'1'&x"DB3B",'1'&x"DB3C",'1'&x"DB3D",'1'&x"DB3E",'1'&x"DB3F",
+--'1'&x"DB40",'1'&x"DB41",'1'&x"DB42",'1'&x"DB43",'1'&x"DB44",'1'&x"DB45",'1'&x"DB46",'1'&x"DB47",'1'&x"DB48",'1'&x"DB49",'1'&x"DB4A",'1'&x"DB4B",'1'&x"DB4C",'1'&x"DB4D",'1'&x"DB4E",'1'&x"DB4F",
+--'1'&x"DB50",'1'&x"DB51",'1'&x"DB52",'1'&x"DB53",'1'&x"DB54",'1'&x"DB55",'1'&x"DB56",'1'&x"DB57",'1'&x"DB58",'1'&x"DB59",'1'&x"DB5A",'1'&x"DB5B",'1'&x"DB5C",'1'&x"DB5D",'1'&x"DB5E",'1'&x"DB5F",
+--'1'&x"DB60",'1'&x"DB61",'1'&x"DB62",'1'&x"DB63",'1'&x"DB64",'1'&x"DB65",'1'&x"DB66",'1'&x"DB67",'1'&x"DB68",'1'&x"DB69",'1'&x"DB6A",'1'&x"DB6B",'1'&x"DB6C",'1'&x"DB6D",'1'&x"DB6E",'1'&x"DB6F",
+--'1'&x"DB70",'1'&x"DB71",'1'&x"DB72",'1'&x"DB73",'1'&x"DB74",'1'&x"DB75",'1'&x"DB76",'1'&x"DB77",'1'&x"DB78",'1'&x"DB79",'1'&x"DB7A",'1'&x"DB7B",'1'&x"DB7C",'1'&x"DB7D",'1'&x"DB7E",'1'&x"DB7F",
+--'1'&x"DB80",'1'&x"DB81",'1'&x"DB82",'1'&x"DB83",'1'&x"DB84",'1'&x"DB85",'1'&x"DB86",'1'&x"DB87",'1'&x"DB88",'1'&x"DB89",'1'&x"DB8A",'1'&x"DB8B",'1'&x"DB8C",'1'&x"DB8D",'1'&x"DB8E",'1'&x"DB8F",
+--'1'&x"DB90",'1'&x"DB91",'1'&x"DB92",'1'&x"DB93",'1'&x"DB94",'1'&x"DB95",'1'&x"DB96",'1'&x"DB97",'1'&x"DB98",'1'&x"DB99",'1'&x"DB9A",'1'&x"DB9B",'1'&x"DB9C",'1'&x"DB9D",'1'&x"DB9E",'1'&x"DB9F",
+--'1'&x"DBA0",'1'&x"DBA1",'1'&x"DBA2",'1'&x"DBA3",'1'&x"DBA4",'1'&x"DBA5",'1'&x"DBA6",'1'&x"DBA7",'1'&x"DBA8",'1'&x"DBA9",'1'&x"DBAA",'1'&x"DBAB",'1'&x"DBAC",'1'&x"DBAD",'1'&x"DBAE",'1'&x"DBAF",
+--'1'&x"DBB0",'1'&x"DBB1",'1'&x"DBB2",'1'&x"DBB3",'1'&x"DBB4",'1'&x"DBB5",'1'&x"DBB6",'1'&x"DBB7",'1'&x"DBB8",'1'&x"DBB9",'1'&x"DBBA",'1'&x"DBBB",'1'&x"DBBC",'1'&x"DBBD",'1'&x"DBBE",'1'&x"DBBF",
+--'1'&x"DBC0",'1'&x"DBC1",'1'&x"DBC2",'1'&x"DBC3",'1'&x"DBC4",'1'&x"DBC5",'1'&x"DBC6",'1'&x"DBC7",'1'&x"DBC8",'1'&x"DBC9",'1'&x"DBCA",'1'&x"DBCB",'1'&x"DBCC",'1'&x"DBCD",'1'&x"DBCE",'1'&x"DBCF",
+--'1'&x"DBD0",'1'&x"DBD1",'1'&x"DBD2",'1'&x"DBD3",'1'&x"DBD4",'1'&x"DBD5",'1'&x"DBD6",'1'&x"DBD7",'1'&x"DBD8",'1'&x"DBD9",'1'&x"DBDA",'1'&x"DBDB",'1'&x"DBDC",'1'&x"DBDD",'1'&x"DBDE",'1'&x"DBDF",
+--'1'&x"DBE0",'1'&x"DBE1",'1'&x"DBE2",'1'&x"DBE3",'1'&x"DBE4",'1'&x"DBE5",'1'&x"DBE6",'1'&x"DBE7",'1'&x"DBE8",'1'&x"DBE9",'1'&x"DBEA",'1'&x"DBEB",'1'&x"DBEC",'1'&x"DBED",'1'&x"DBEE",'1'&x"DBEF",
+--'1'&x"DBF0",'1'&x"DBF1",'1'&x"DBF2",'1'&x"DBF3",'1'&x"DBF4",'1'&x"DBF5",'1'&x"DBF6",'1'&x"DBF7",'1'&x"DBF8",'1'&x"DBF9",'1'&x"DBFA",'1'&x"DBFB",'1'&x"DBFC",'1'&x"DBFD",'1'&x"DBFE",'1'&x"DBFF",
+--'1'&x"DC00",'1'&x"DC01",'1'&x"DC02",'1'&x"DC03",'1'&x"DC04",'1'&x"DC05",'1'&x"DC06",'1'&x"DC07",'1'&x"DC08",'1'&x"DC09",'1'&x"DC0A",'1'&x"DC0B",'1'&x"DC0C",'1'&x"DC0D",'1'&x"DC0E",'1'&x"DC0F",
+--'1'&x"DC10",'1'&x"DC11",'1'&x"DC12",'1'&x"DC13",'1'&x"DC14",'1'&x"DC15",'1'&x"DC16",'1'&x"DC17",'1'&x"DC18",'1'&x"DC19",'1'&x"DC1A",'1'&x"DC1B",'1'&x"DC1C",'1'&x"DC1D",'1'&x"DC1E",'1'&x"DC1F",
+--'1'&x"DC20",'1'&x"DC21",'1'&x"DC22",'1'&x"DC23",'1'&x"DC24",'1'&x"DC25",'1'&x"DC26",'1'&x"DC27",'1'&x"DC28",'1'&x"DC29",'1'&x"DC2A",'1'&x"DC2B",'1'&x"DC2C",'1'&x"DC2D",'1'&x"DC2E",'1'&x"DC2F",
+--'1'&x"DC30",'1'&x"DC31",'1'&x"DC32",'1'&x"DC33",'1'&x"DC34",'1'&x"DC35",'1'&x"DC36",'1'&x"DC37",'1'&x"DC38",'1'&x"DC39",'1'&x"DC3A",'1'&x"DC3B",'1'&x"DC3C",'1'&x"DC3D",'1'&x"DC3E",'1'&x"DC3F",
+--'1'&x"DC40",'1'&x"DC41",'1'&x"DC42",'1'&x"DC43",'1'&x"DC44",'1'&x"DC45",'1'&x"DC46",'1'&x"DC47",'1'&x"DC48",'1'&x"DC49",'1'&x"DC4A",'1'&x"DC4B",'1'&x"DC4C",'1'&x"DC4D",'1'&x"DC4E",'1'&x"DC4F",
+--'1'&x"DC50",'1'&x"DC51",'1'&x"DC52",'1'&x"DC53",'1'&x"DC54",'1'&x"DC55",'1'&x"DC56",'1'&x"DC57",'1'&x"DC58",'1'&x"DC59",'1'&x"DC5A",'1'&x"DC5B",'1'&x"DC5C",'1'&x"DC5D",'1'&x"DC5E",'1'&x"DC5F",
+--'1'&x"DC60",'1'&x"DC61",'1'&x"DC62",'1'&x"DC63",'1'&x"DC64",'1'&x"DC65",'1'&x"DC66",'1'&x"DC67",'1'&x"DC68",'1'&x"DC69",'1'&x"DC6A",'1'&x"DC6B",'1'&x"DC6C",'1'&x"DC6D",'1'&x"DC6E",'1'&x"DC6F",
+--'1'&x"DC70",'1'&x"DC71",'1'&x"DC72",'1'&x"DC73",'1'&x"DC74",'1'&x"DC75",'1'&x"DC76",'1'&x"DC77",'1'&x"DC78",'1'&x"DC79",'1'&x"DC7A",'1'&x"DC7B",'1'&x"DC7C",'1'&x"DC7D",'1'&x"DC7E",'1'&x"DC7F",
+--'1'&x"DC80",'1'&x"DC81",'1'&x"DC82",'1'&x"DC83",'1'&x"DC84",'1'&x"DC85",'1'&x"DC86",'1'&x"DC87",'1'&x"DC88",'1'&x"DC89",'1'&x"DC8A",'1'&x"DC8B",'1'&x"DC8C",'1'&x"DC8D",'1'&x"DC8E",'1'&x"DC8F",
+--'1'&x"DC90",'1'&x"DC91",'1'&x"DC92",'1'&x"DC93",'1'&x"DC94",'1'&x"DC95",'1'&x"DC96",'1'&x"DC97",'1'&x"DC98",'1'&x"DC99",'1'&x"DC9A",'1'&x"DC9B",'1'&x"DC9C",'1'&x"DC9D",'1'&x"DC9E",'1'&x"DC9F",
+--'1'&x"DCA0",'1'&x"DCA1",'1'&x"DCA2",'1'&x"DCA3",'1'&x"DCA4",'1'&x"DCA5",'1'&x"DCA6",'1'&x"DCA7",'1'&x"DCA8",'1'&x"DCA9",'1'&x"DCAA",'1'&x"DCAB",'1'&x"DCAC",'1'&x"DCAD",'1'&x"DCAE",'1'&x"DCAF",
+--'1'&x"DCB0",'1'&x"DCB1",'1'&x"DCB2",'1'&x"DCB3",'1'&x"DCB4",'1'&x"DCB5",'1'&x"DCB6",'1'&x"DCB7",'1'&x"DCB8",'1'&x"DCB9",'1'&x"DCBA",'1'&x"DCBB",'1'&x"DCBC",'1'&x"DCBD",'1'&x"DCBE",'1'&x"DCBF",
+--'1'&x"DCC0",'1'&x"DCC1",'1'&x"DCC2",'1'&x"DCC3",'1'&x"DCC4",'1'&x"DCC5",'1'&x"DCC6",'1'&x"DCC7",'1'&x"DCC8",'1'&x"DCC9",'1'&x"DCCA",'1'&x"DCCB",'1'&x"DCCC",'1'&x"DCCD",'1'&x"DCCE",'1'&x"DCCF",
+--'1'&x"DCD0",'1'&x"DCD1",'1'&x"DCD2",'1'&x"DCD3",'1'&x"DCD4",'1'&x"DCD5",'1'&x"DCD6",'1'&x"DCD7",'1'&x"DCD8",'1'&x"DCD9",'1'&x"DCDA",'1'&x"DCDB",'1'&x"DCDC",'1'&x"DCDD",'1'&x"DCDE",'1'&x"DCDF",
+--'1'&x"DCE0",'1'&x"DCE1",'1'&x"DCE2",'1'&x"DCE3",'1'&x"DCE4",'1'&x"DCE5",'1'&x"DCE6",'1'&x"DCE7",'1'&x"DCE8",'1'&x"DCE9",'1'&x"DCEA",'1'&x"DCEB",'1'&x"DCEC",'1'&x"DCED",'1'&x"DCEE",'1'&x"DCEF",
+--'1'&x"DCF0",'1'&x"DCF1",'1'&x"DCF2",'1'&x"DCF3",'1'&x"DCF4",'1'&x"DCF5",'1'&x"DCF6",'1'&x"DCF7",'1'&x"DCF8",'1'&x"DCF9",'1'&x"DCFA",'1'&x"DCFB",'1'&x"DCFC",'1'&x"DCFD",'1'&x"DCFE",'1'&x"DCFF",
+--'1'&x"DD00",'1'&x"DD01",'1'&x"DD02",'1'&x"DD03",'1'&x"DD04",'1'&x"DD05",'1'&x"DD06",'1'&x"DD07",'1'&x"DD08",'1'&x"DD09",'1'&x"DD0A",'1'&x"DD0B",'1'&x"DD0C",'1'&x"DD0D",'1'&x"DD0E",'1'&x"DD0F",
+--'1'&x"DD10",'1'&x"DD11",'1'&x"DD12",'1'&x"DD13",'1'&x"DD14",'1'&x"DD15",'1'&x"DD16",'1'&x"DD17",'1'&x"DD18",'1'&x"DD19",'1'&x"DD1A",'1'&x"DD1B",'1'&x"DD1C",'1'&x"DD1D",'1'&x"DD1E",'1'&x"DD1F",
+--'1'&x"DD20",'1'&x"DD21",'1'&x"DD22",'1'&x"DD23",'1'&x"DD24",'1'&x"DD25",'1'&x"DD26",'1'&x"DD27",'1'&x"DD28",'1'&x"DD29",'1'&x"DD2A",'1'&x"DD2B",'1'&x"DD2C",'1'&x"DD2D",'1'&x"DD2E",'1'&x"DD2F",
+--'1'&x"DD30",'1'&x"DD31",'1'&x"DD32",'1'&x"DD33",'1'&x"DD34",'1'&x"DD35",'1'&x"DD36",'1'&x"DD37",'1'&x"DD38",'1'&x"DD39",'1'&x"DD3A",'1'&x"DD3B",'1'&x"DD3C",'1'&x"DD3D",'1'&x"DD3E",'1'&x"DD3F",
+--'1'&x"DD40",'1'&x"DD41",'1'&x"DD42",'1'&x"DD43",'1'&x"DD44",'1'&x"DD45",'1'&x"DD46",'1'&x"DD47",'1'&x"DD48",'1'&x"DD49",'1'&x"DD4A",'1'&x"DD4B",'1'&x"DD4C",'1'&x"DD4D",'1'&x"DD4E",'1'&x"DD4F",
+--'1'&x"DD50",'1'&x"DD51",'1'&x"DD52",'1'&x"DD53",'1'&x"DD54",'1'&x"DD55",'1'&x"DD56",'1'&x"DD57",'1'&x"DD58",'1'&x"DD59",'1'&x"DD5A",'1'&x"DD5B",'1'&x"DD5C",'1'&x"DD5D",'1'&x"DD5E",'1'&x"DD5F",
+--'1'&x"DD60",'1'&x"DD61",'1'&x"DD62",'1'&x"DD63",'1'&x"DD64",'1'&x"DD65",'1'&x"DD66",'1'&x"DD67",'1'&x"DD68",'1'&x"DD69",'1'&x"DD6A",'1'&x"DD6B",'1'&x"DD6C",'1'&x"DD6D",'1'&x"DD6E",'1'&x"DD6F",
+--'1'&x"DD70",'1'&x"DD71",'1'&x"DD72",'1'&x"DD73",'1'&x"DD74",'1'&x"DD75",'1'&x"DD76",'1'&x"DD77",'1'&x"DD78",'1'&x"DD79",'1'&x"DD7A",'1'&x"DD7B",'1'&x"DD7C",'1'&x"DD7D",'1'&x"DD7E",'1'&x"DD7F",
+--'1'&x"DD80",'1'&x"DD81",'1'&x"DD82",'1'&x"DD83",'1'&x"DD84",'1'&x"DD85",'1'&x"DD86",'1'&x"DD87",'1'&x"DD88",'1'&x"DD89",'1'&x"DD8A",'1'&x"DD8B",'1'&x"DD8C",'1'&x"DD8D",'1'&x"DD8E",'1'&x"DD8F",
+--'1'&x"DD90",'1'&x"DD91",'1'&x"DD92",'1'&x"DD93",'1'&x"DD94",'1'&x"DD95",'1'&x"DD96",'1'&x"DD97",'1'&x"DD98",'1'&x"DD99",'1'&x"DD9A",'1'&x"DD9B",'1'&x"DD9C",'1'&x"DD9D",'1'&x"DD9E",'1'&x"DD9F",
+--'1'&x"DDA0",'1'&x"DDA1",'1'&x"DDA2",'1'&x"DDA3",'1'&x"DDA4",'1'&x"DDA5",'1'&x"DDA6",'1'&x"DDA7",'1'&x"DDA8",'1'&x"DDA9",'1'&x"DDAA",'1'&x"DDAB",'1'&x"DDAC",'1'&x"DDAD",'1'&x"DDAE",'1'&x"DDAF",
+--'1'&x"DDB0",'1'&x"DDB1",'1'&x"DDB2",'1'&x"DDB3",'1'&x"DDB4",'1'&x"DDB5",'1'&x"DDB6",'1'&x"DDB7",'1'&x"DDB8",'1'&x"DDB9",'1'&x"DDBA",'1'&x"DDBB",'1'&x"DDBC",'1'&x"DDBD",'1'&x"DDBE",'1'&x"DDBF",
+--'1'&x"DDC0",'1'&x"DDC1",'1'&x"DDC2",'1'&x"DDC3",'1'&x"DDC4",'1'&x"DDC5",'1'&x"DDC6",'1'&x"DDC7",'1'&x"DDC8",'1'&x"DDC9",'1'&x"DDCA",'1'&x"DDCB",'1'&x"DDCC",'1'&x"DDCD",'1'&x"DDCE",'1'&x"DDCF",
+--'1'&x"DDD0",'1'&x"DDD1",'1'&x"DDD2",'1'&x"DDD3",'1'&x"DDD4",'1'&x"DDD5",'1'&x"DDD6",'1'&x"DDD7",'1'&x"DDD8",'1'&x"DDD9",'1'&x"DDDA",'1'&x"DDDB",'1'&x"DDDC",'1'&x"DDDD",'1'&x"DDDE",'1'&x"DDDF",
+--'1'&x"DDE0",'1'&x"DDE1",'1'&x"DDE2",'1'&x"DDE3",'1'&x"DDE4",'1'&x"DDE5",'1'&x"DDE6",'1'&x"DDE7",'1'&x"DDE8",'1'&x"DDE9",'1'&x"DDEA",'1'&x"DDEB",'1'&x"DDEC",'1'&x"DDED",'1'&x"DDEE",'1'&x"DDEF",
+--'1'&x"DDF0",'1'&x"DDF1",'1'&x"DDF2",'1'&x"DDF3",'1'&x"DDF4",'1'&x"DDF5",'1'&x"DDF6",'1'&x"DDF7",'1'&x"DDF8",'1'&x"DDF9",'1'&x"DDFA",'1'&x"DDFB",'1'&x"DDFC",'1'&x"DDFD",'1'&x"DDFE",'1'&x"DDFF",
+--'1'&x"DE00",'1'&x"DE01",'1'&x"DE02",'1'&x"DE03",'1'&x"DE04",'1'&x"DE05",'1'&x"DE06",'1'&x"DE07",'1'&x"DE08",'1'&x"DE09",'1'&x"DE0A",'1'&x"DE0B",'1'&x"DE0C",'1'&x"DE0D",'1'&x"DE0E",'1'&x"DE0F",
+--'1'&x"DE10",'1'&x"DE11",'1'&x"DE12",'1'&x"DE13",'1'&x"DE14",'1'&x"DE15",'1'&x"DE16",'1'&x"DE17",'1'&x"DE18",'1'&x"DE19",'1'&x"DE1A",'1'&x"DE1B",'1'&x"DE1C",'1'&x"DE1D",'1'&x"DE1E",'1'&x"DE1F",
+--'1'&x"DE20",'1'&x"DE21",'1'&x"DE22",'1'&x"DE23",'1'&x"DE24",'1'&x"DE25",'1'&x"DE26",'1'&x"DE27",'1'&x"DE28",'1'&x"DE29",'1'&x"DE2A",'1'&x"DE2B",'1'&x"DE2C",'1'&x"DE2D",'1'&x"DE2E",'1'&x"DE2F",
+--'1'&x"DE30",'1'&x"DE31",'1'&x"DE32",'1'&x"DE33",'1'&x"DE34",'1'&x"DE35",'1'&x"DE36",'1'&x"DE37",'1'&x"DE38",'1'&x"DE39",'1'&x"DE3A",'1'&x"DE3B",'1'&x"DE3C",'1'&x"DE3D",'1'&x"DE3E",'1'&x"DE3F",
+--'1'&x"DE40",'1'&x"DE41",'1'&x"DE42",'1'&x"DE43",'1'&x"DE44",'1'&x"DE45",'1'&x"DE46",'1'&x"DE47",'1'&x"DE48",'1'&x"DE49",'1'&x"DE4A",'1'&x"DE4B",'1'&x"DE4C",'1'&x"DE4D",'1'&x"DE4E",'1'&x"DE4F",
+--'1'&x"DE50",'1'&x"DE51",'1'&x"DE52",'1'&x"DE53",'1'&x"DE54",'1'&x"DE55",'1'&x"DE56",'1'&x"DE57",'1'&x"DE58",'1'&x"DE59",'1'&x"DE5A",'1'&x"DE5B",'1'&x"DE5C",'1'&x"DE5D",'1'&x"DE5E",'1'&x"DE5F",
+--'1'&x"DE60",'1'&x"DE61",'1'&x"DE62",'1'&x"DE63",'1'&x"DE64",'1'&x"DE65",'1'&x"DE66",'1'&x"DE67",'1'&x"DE68",'1'&x"DE69",'1'&x"DE6A",'1'&x"DE6B",'1'&x"DE6C",'1'&x"DE6D",'1'&x"DE6E",'1'&x"DE6F",
+--'1'&x"DE70",'1'&x"DE71",'1'&x"DE72",'1'&x"DE73",'1'&x"DE74",'1'&x"DE75",'1'&x"DE76",'1'&x"DE77",'1'&x"DE78",'1'&x"DE79",'1'&x"DE7A",'1'&x"DE7B",'1'&x"DE7C",'1'&x"DE7D",'1'&x"DE7E",'1'&x"DE7F",
+--'1'&x"DE80",'1'&x"DE81",'1'&x"DE82",'1'&x"DE83",'1'&x"DE84",'1'&x"DE85",'1'&x"DE86",'1'&x"DE87",'1'&x"DE88",'1'&x"DE89",'1'&x"DE8A",'1'&x"DE8B",'1'&x"DE8C",'1'&x"DE8D",'1'&x"DE8E",'1'&x"DE8F",
+--'1'&x"DE90",'1'&x"DE91",'1'&x"DE92",'1'&x"DE93",'1'&x"DE94",'1'&x"DE95",'1'&x"DE96",'1'&x"DE97",'1'&x"DE98",'1'&x"DE99",'1'&x"DE9A",'1'&x"DE9B",'1'&x"DE9C",'1'&x"DE9D",'1'&x"DE9E",'1'&x"DE9F",
+--'1'&x"DEA0",'1'&x"DEA1",'1'&x"DEA2",'1'&x"DEA3",'1'&x"DEA4",'1'&x"DEA5",'1'&x"DEA6",'1'&x"DEA7",'1'&x"DEA8",'1'&x"DEA9",'1'&x"DEAA",'1'&x"DEAB",'1'&x"DEAC",'1'&x"DEAD",'1'&x"DEAE",'1'&x"DEAF",
+--'1'&x"DEB0",'1'&x"DEB1",'1'&x"DEB2",'1'&x"DEB3",'1'&x"DEB4",'1'&x"DEB5",'1'&x"DEB6",'1'&x"DEB7",'1'&x"DEB8",'1'&x"DEB9",'1'&x"DEBA",'1'&x"DEBB",'1'&x"DEBC",'1'&x"DEBD",'1'&x"DEBE",'1'&x"DEBF",
+--'1'&x"DEC0",'1'&x"DEC1",'1'&x"DEC2",'1'&x"DEC3",'1'&x"DEC4",'1'&x"DEC5",'1'&x"DEC6",'1'&x"DEC7",'1'&x"DEC8",'1'&x"DEC9",'1'&x"DECA",'1'&x"DECB",'1'&x"DECC",'1'&x"DECD",'1'&x"DECE",'1'&x"DECF",
+--'1'&x"DED0",'1'&x"DED1",'1'&x"DED2",'1'&x"DED3",'1'&x"DED4",'1'&x"DED5",'1'&x"DED6",'1'&x"DED7",'1'&x"DED8",'1'&x"DED9",'1'&x"DEDA",'1'&x"DEDB",'1'&x"DEDC",'1'&x"DEDD",'1'&x"DEDE",'1'&x"DEDF",
+--'1'&x"DEE0",'1'&x"DEE1",'1'&x"DEE2",'1'&x"DEE3",'1'&x"DEE4",'1'&x"DEE5",'1'&x"DEE6",'1'&x"DEE7",'1'&x"DEE8",'1'&x"DEE9",'1'&x"DEEA",'1'&x"DEEB",'1'&x"DEEC",'1'&x"DEED",'1'&x"DEEE",'1'&x"DEEF",
+--'1'&x"DEF0",'1'&x"DEF1",'1'&x"DEF2",'1'&x"DEF3",'1'&x"DEF4",'1'&x"DEF5",'1'&x"DEF6",'1'&x"DEF7",'1'&x"DEF8",'1'&x"DEF9",'1'&x"DEFA",'1'&x"DEFB",'1'&x"DEFC",'1'&x"DEFD",'1'&x"DEFE",'1'&x"DEFF",
+--'1'&x"DF00",'1'&x"DF01",'1'&x"DF02",'1'&x"DF03",'1'&x"DF04",'1'&x"DF05",'1'&x"DF06",'1'&x"DF07",'1'&x"DF08",'1'&x"DF09",'1'&x"DF0A",'1'&x"DF0B",'1'&x"DF0C",'1'&x"DF0D",'1'&x"DF0E",'1'&x"DF0F",
+--'1'&x"DF10",'1'&x"DF11",'1'&x"DF12",'1'&x"DF13",'1'&x"DF14",'1'&x"DF15",'1'&x"DF16",'1'&x"DF17",'1'&x"DF18",'1'&x"DF19",'1'&x"DF1A",'1'&x"DF1B",'1'&x"DF1C",'1'&x"DF1D",'1'&x"DF1E",'1'&x"DF1F",
+--'1'&x"DF20",'1'&x"DF21",'1'&x"DF22",'1'&x"DF23",'1'&x"DF24",'1'&x"DF25",'1'&x"DF26",'1'&x"DF27",'1'&x"DF28",'1'&x"DF29",'1'&x"DF2A",'1'&x"DF2B",'1'&x"DF2C",'1'&x"DF2D",'1'&x"DF2E",'1'&x"DF2F",
+--'1'&x"DF30",'1'&x"DF31",'1'&x"DF32",'1'&x"DF33",'1'&x"DF34",'1'&x"DF35",'1'&x"DF36",'1'&x"DF37",'1'&x"DF38",'1'&x"DF39",'1'&x"DF3A",'1'&x"DF3B",'1'&x"DF3C",'1'&x"DF3D",'1'&x"DF3E",'1'&x"DF3F",
+--'1'&x"DF40",'1'&x"DF41",'1'&x"DF42",'1'&x"DF43",'1'&x"DF44",'1'&x"DF45",'1'&x"DF46",'1'&x"DF47",'1'&x"DF48",'1'&x"DF49",'1'&x"DF4A",'1'&x"DF4B",'1'&x"DF4C",'1'&x"DF4D",'1'&x"DF4E",'1'&x"DF4F",
+--'1'&x"DF50",'1'&x"DF51",'1'&x"DF52",'1'&x"DF53",'1'&x"DF54",'1'&x"DF55",'1'&x"DF56",'1'&x"DF57",'1'&x"DF58",'1'&x"DF59",'1'&x"DF5A",'1'&x"DF5B",'1'&x"DF5C",'1'&x"DF5D",'1'&x"DF5E",'1'&x"DF5F",
+--'1'&x"DF60",'1'&x"DF61",'1'&x"DF62",'1'&x"DF63",'1'&x"DF64",'1'&x"DF65",'1'&x"DF66",'1'&x"DF67",'1'&x"DF68",'1'&x"DF69",'1'&x"DF6A",'1'&x"DF6B",'1'&x"DF6C",'1'&x"DF6D",'1'&x"DF6E",'1'&x"DF6F",
+--'1'&x"DF70",'1'&x"DF71",'1'&x"DF72",'1'&x"DF73",'1'&x"DF74",'1'&x"DF75",'1'&x"DF76",'1'&x"DF77",'1'&x"DF78",'1'&x"DF79",'1'&x"DF7A",'1'&x"DF7B",'1'&x"DF7C",'1'&x"DF7D",'1'&x"DF7E",'1'&x"DF7F",
+--'1'&x"DF80",'1'&x"DF81",'1'&x"DF82",'1'&x"DF83",'1'&x"DF84",'1'&x"DF85",'1'&x"DF86",'1'&x"DF87",'1'&x"DF88",'1'&x"DF89",'1'&x"DF8A",'1'&x"DF8B",'1'&x"DF8C",'1'&x"DF8D",'1'&x"DF8E",'1'&x"DF8F",
+--'1'&x"DF90",'1'&x"DF91",'1'&x"DF92",'1'&x"DF93",'1'&x"DF94",'1'&x"DF95",'1'&x"DF96",'1'&x"DF97",'1'&x"DF98",'1'&x"DF99",'1'&x"DF9A",'1'&x"DF9B",'1'&x"DF9C",'1'&x"DF9D",'1'&x"DF9E",'1'&x"DF9F",
+--'1'&x"DFA0",'1'&x"DFA1",'1'&x"DFA2",'1'&x"DFA3",'1'&x"DFA4",'1'&x"DFA5",'1'&x"DFA6",'1'&x"DFA7",'1'&x"DFA8",'1'&x"DFA9",'1'&x"DFAA",'1'&x"DFAB",'1'&x"DFAC",'1'&x"DFAD",'1'&x"DFAE",'1'&x"DFAF",
+--'1'&x"DFB0",'1'&x"DFB1",'1'&x"DFB2",'1'&x"DFB3",'1'&x"DFB4",'1'&x"DFB5",'1'&x"DFB6",'1'&x"DFB7",'1'&x"DFB8",'1'&x"DFB9",'1'&x"DFBA",'1'&x"DFBB",'1'&x"DFBC",'1'&x"DFBD",'1'&x"DFBE",'1'&x"DFBF",
+--'1'&x"DFC0",'1'&x"DFC1",'1'&x"DFC2",'1'&x"DFC3",'1'&x"DFC4",'1'&x"DFC5",'1'&x"DFC6",'1'&x"DFC7",'1'&x"DFC8",'1'&x"DFC9",'1'&x"DFCA",'1'&x"DFCB",'1'&x"DFCC",'1'&x"DFCD",'1'&x"DFCE",'1'&x"DFCF",
+--'1'&x"DFD0",'1'&x"DFD1",'1'&x"DFD2",'1'&x"DFD3",'1'&x"DFD4",'1'&x"DFD5",'1'&x"DFD6",'1'&x"DFD7",'1'&x"DFD8",'1'&x"DFD9",'1'&x"DFDA",'1'&x"DFDB",'1'&x"DFDC",'1'&x"DFDD",'1'&x"DFDE",'1'&x"DFDF",
+--'1'&x"DFE0",'1'&x"DFE1",'1'&x"DFE2",'1'&x"DFE3",'1'&x"DFE4",'1'&x"DFE5",'1'&x"DFE6",'1'&x"DFE7",'1'&x"DFE8",'1'&x"DFE9",'1'&x"DFEA",'1'&x"DFEB",'1'&x"DFEC",'1'&x"DFED",'1'&x"DFEE",'1'&x"DFEF",
+--'1'&x"DFF0",'1'&x"DFF1",'1'&x"DFF2",'1'&x"DFF3",'1'&x"DFF4",'1'&x"DFF5",'1'&x"DFF6",'1'&x"DFF7",'1'&x"DFF8",'1'&x"DFF9",'1'&x"DFFA",'1'&x"DFFB",'1'&x"DFFC",'1'&x"DFFD",'1'&x"DFFE",'1'&x"DFFF",
+--'1'&x"E000",'1'&x"E001",'1'&x"E002",'1'&x"E003",'1'&x"E004",'1'&x"E005",'1'&x"E006",'1'&x"E007",'1'&x"E008",'1'&x"E009",'1'&x"E00A",'1'&x"E00B",'1'&x"E00C",'1'&x"E00D",'1'&x"E00E",'1'&x"E00F",
+--'1'&x"E010",'1'&x"E011",'1'&x"E012",'1'&x"E013",'1'&x"E014",'1'&x"E015",'1'&x"E016",'1'&x"E017",'1'&x"E018",'1'&x"E019",'1'&x"E01A",'1'&x"E01B",'1'&x"E01C",'1'&x"E01D",'1'&x"E01E",'1'&x"E01F",
+--'1'&x"E020",'1'&x"E021",'1'&x"E022",'1'&x"E023",'1'&x"E024",'1'&x"E025",'1'&x"E026",'1'&x"E027",'1'&x"E028",'1'&x"E029",'1'&x"E02A",'1'&x"E02B",'1'&x"E02C",'1'&x"E02D",'1'&x"E02E",'1'&x"E02F",
+--'1'&x"E030",'1'&x"E031",'1'&x"E032",'1'&x"E033",'1'&x"E034",'1'&x"E035",'1'&x"E036",'1'&x"E037",'1'&x"E038",'1'&x"E039",'1'&x"E03A",'1'&x"E03B",'1'&x"E03C",'1'&x"E03D",'1'&x"E03E",'1'&x"E03F",
+--'1'&x"E040",'1'&x"E041",'1'&x"E042",'1'&x"E043",'1'&x"E044",'1'&x"E045",'1'&x"E046",'1'&x"E047",'1'&x"E048",'1'&x"E049",'1'&x"E04A",'1'&x"E04B",'1'&x"E04C",'1'&x"E04D",'1'&x"E04E",'1'&x"E04F",
+--'1'&x"E050",'1'&x"E051",'1'&x"E052",'1'&x"E053",'1'&x"E054",'1'&x"E055",'1'&x"E056",'1'&x"E057",'1'&x"E058",'1'&x"E059",'1'&x"E05A",'1'&x"E05B",'1'&x"E05C",'1'&x"E05D",'1'&x"E05E",'1'&x"E05F",
+--'1'&x"E060",'1'&x"E061",'1'&x"E062",'1'&x"E063",'1'&x"E064",'1'&x"E065",'1'&x"E066",'1'&x"E067",'1'&x"E068",'1'&x"E069",'1'&x"E06A",'1'&x"E06B",'1'&x"E06C",'1'&x"E06D",'1'&x"E06E",'1'&x"E06F",
+--'1'&x"E070",'1'&x"E071",'1'&x"E072",'1'&x"E073",'1'&x"E074",'1'&x"E075",'1'&x"E076",'1'&x"E077",'1'&x"E078",'1'&x"E079",'1'&x"E07A",'1'&x"E07B",'1'&x"E07C",'1'&x"E07D",'1'&x"E07E",'1'&x"E07F",
+--'1'&x"E080",'1'&x"E081",'1'&x"E082",'1'&x"E083",'1'&x"E084",'1'&x"E085",'1'&x"E086",'1'&x"E087",'1'&x"E088",'1'&x"E089",'1'&x"E08A",'1'&x"E08B",'1'&x"E08C",'1'&x"E08D",'1'&x"E08E",'1'&x"E08F",
+--'1'&x"E090",'1'&x"E091",'1'&x"E092",'1'&x"E093",'1'&x"E094",'1'&x"E095",'1'&x"E096",'1'&x"E097",'1'&x"E098",'1'&x"E099",'1'&x"E09A",'1'&x"E09B",'1'&x"E09C",'1'&x"E09D",'1'&x"E09E",'1'&x"E09F",
+--'1'&x"E0A0",'1'&x"E0A1",'1'&x"E0A2",'1'&x"E0A3",'1'&x"E0A4",'1'&x"E0A5",'1'&x"E0A6",'1'&x"E0A7",'1'&x"E0A8",'1'&x"E0A9",'1'&x"E0AA",'1'&x"E0AB",'1'&x"E0AC",'1'&x"E0AD",'1'&x"E0AE",'1'&x"E0AF",
+--'1'&x"E0B0",'1'&x"E0B1",'1'&x"E0B2",'1'&x"E0B3",'1'&x"E0B4",'1'&x"E0B5",'1'&x"E0B6",'1'&x"E0B7",'1'&x"E0B8",'1'&x"E0B9",'1'&x"E0BA",'1'&x"E0BB",'1'&x"E0BC",'1'&x"E0BD",'1'&x"E0BE",'1'&x"E0BF",
+--'1'&x"E0C0",'1'&x"E0C1",'1'&x"E0C2",'1'&x"E0C3",'1'&x"E0C4",'1'&x"E0C5",'1'&x"E0C6",'1'&x"E0C7",'1'&x"E0C8",'1'&x"E0C9",'1'&x"E0CA",'1'&x"E0CB",'1'&x"E0CC",'1'&x"E0CD",'1'&x"E0CE",'1'&x"E0CF",
+--'1'&x"E0D0",'1'&x"E0D1",'1'&x"E0D2",'1'&x"E0D3",'1'&x"E0D4",'1'&x"E0D5",'1'&x"E0D6",'1'&x"E0D7",'1'&x"E0D8",'1'&x"E0D9",'1'&x"E0DA",'1'&x"E0DB",'1'&x"E0DC",'1'&x"E0DD",'1'&x"E0DE",'1'&x"E0DF",
+--'1'&x"E0E0",'1'&x"E0E1",'1'&x"E0E2",'1'&x"E0E3",'1'&x"E0E4",'1'&x"E0E5",'1'&x"E0E6",'1'&x"E0E7",'1'&x"E0E8",'1'&x"E0E9",'1'&x"E0EA",'1'&x"E0EB",'1'&x"E0EC",'1'&x"E0ED",'1'&x"E0EE",'1'&x"E0EF",
+--'1'&x"E0F0",'1'&x"E0F1",'1'&x"E0F2",'1'&x"E0F3",'1'&x"E0F4",'1'&x"E0F5",'1'&x"E0F6",'1'&x"E0F7",'1'&x"E0F8",'1'&x"E0F9",'1'&x"E0FA",'1'&x"E0FB",'1'&x"E0FC",'1'&x"E0FD",'1'&x"E0FE",'1'&x"E0FF",
+--'1'&x"E100",'1'&x"E101",'1'&x"E102",'1'&x"E103",'1'&x"E104",'1'&x"E105",'1'&x"E106",'1'&x"E107",'1'&x"E108",'1'&x"E109",'1'&x"E10A",'1'&x"E10B",'1'&x"E10C",'1'&x"E10D",'1'&x"E10E",'1'&x"E10F",
+--'1'&x"E110",'1'&x"E111",'1'&x"E112",'1'&x"E113",'1'&x"E114",'1'&x"E115",'1'&x"E116",'1'&x"E117",'1'&x"E118",'1'&x"E119",'1'&x"E11A",'1'&x"E11B",'1'&x"E11C",'1'&x"E11D",'1'&x"E11E",'1'&x"E11F",
+--'1'&x"E120",'1'&x"E121",'1'&x"E122",'1'&x"E123",'1'&x"E124",'1'&x"E125",'1'&x"E126",'1'&x"E127",'1'&x"E128",'1'&x"E129",'1'&x"E12A",'1'&x"E12B",'1'&x"E12C",'1'&x"E12D",'1'&x"E12E",'1'&x"E12F",
+--'1'&x"E130",'1'&x"E131",'1'&x"E132",'1'&x"E133",'1'&x"E134",'1'&x"E135",'1'&x"E136",'1'&x"E137",'1'&x"E138",'1'&x"E139",'1'&x"E13A",'1'&x"E13B",'1'&x"E13C",'1'&x"E13D",'1'&x"E13E",'1'&x"E13F",
+--'1'&x"E140",'1'&x"E141",'1'&x"E142",'1'&x"E143",'1'&x"E144",'1'&x"E145",'1'&x"E146",'1'&x"E147",'1'&x"E148",'1'&x"E149",'1'&x"E14A",'1'&x"E14B",'1'&x"E14C",'1'&x"E14D",'1'&x"E14E",'1'&x"E14F",
+--'1'&x"E150",'1'&x"E151",'1'&x"E152",'1'&x"E153",'1'&x"E154",'1'&x"E155",'1'&x"E156",'1'&x"E157",'1'&x"E158",'1'&x"E159",'1'&x"E15A",'1'&x"E15B",'1'&x"E15C",'1'&x"E15D",'1'&x"E15E",'1'&x"E15F",
+--'1'&x"E160",'1'&x"E161",'1'&x"E162",'1'&x"E163",'1'&x"E164",'1'&x"E165",'1'&x"E166",'1'&x"E167",'1'&x"E168",'1'&x"E169",'1'&x"E16A",'1'&x"E16B",'1'&x"E16C",'1'&x"E16D",'1'&x"E16E",'1'&x"E16F",
+--'1'&x"E170",'1'&x"E171",'1'&x"E172",'1'&x"E173",'1'&x"E174",'1'&x"E175",'1'&x"E176",'1'&x"E177",'1'&x"E178",'1'&x"E179",'1'&x"E17A",'1'&x"E17B",'1'&x"E17C",'1'&x"E17D",'1'&x"E17E",'1'&x"E17F",
+--'1'&x"E180",'1'&x"E181",'1'&x"E182",'1'&x"E183",'1'&x"E184",'1'&x"E185",'1'&x"E186",'1'&x"E187",'1'&x"E188",'1'&x"E189",'1'&x"E18A",'1'&x"E18B",'1'&x"E18C",'1'&x"E18D",'1'&x"E18E",'1'&x"E18F",
+--'1'&x"E190",'1'&x"E191",'1'&x"E192",'1'&x"E193",'1'&x"E194",'1'&x"E195",'1'&x"E196",'1'&x"E197",'1'&x"E198",'1'&x"E199",'1'&x"E19A",'1'&x"E19B",'1'&x"E19C",'1'&x"E19D",'1'&x"E19E",'1'&x"E19F",
+--'1'&x"E1A0",'1'&x"E1A1",'1'&x"E1A2",'1'&x"E1A3",'1'&x"E1A4",'1'&x"E1A5",'1'&x"E1A6",'1'&x"E1A7",'1'&x"E1A8",'1'&x"E1A9",'1'&x"E1AA",'1'&x"E1AB",'1'&x"E1AC",'1'&x"E1AD",'1'&x"E1AE",'1'&x"E1AF",
+--'1'&x"E1B0",'1'&x"E1B1",'1'&x"E1B2",'1'&x"E1B3",'1'&x"E1B4",'1'&x"E1B5",'1'&x"E1B6",'1'&x"E1B7",'1'&x"E1B8",'1'&x"E1B9",'1'&x"E1BA",'1'&x"E1BB",'1'&x"E1BC",'1'&x"E1BD",'1'&x"E1BE",'1'&x"E1BF",
+--'1'&x"E1C0",'1'&x"E1C1",'1'&x"E1C2",'1'&x"E1C3",'1'&x"E1C4",'1'&x"E1C5",'1'&x"E1C6",'1'&x"E1C7",'1'&x"E1C8",'1'&x"E1C9",'1'&x"E1CA",'1'&x"E1CB",'1'&x"E1CC",'1'&x"E1CD",'1'&x"E1CE",'1'&x"E1CF",
+--'1'&x"E1D0",'1'&x"E1D1",'1'&x"E1D2",'1'&x"E1D3",'1'&x"E1D4",'1'&x"E1D5",'1'&x"E1D6",'1'&x"E1D7",'1'&x"E1D8",'1'&x"E1D9",'1'&x"E1DA",'1'&x"E1DB",'1'&x"E1DC",'1'&x"E1DD",'1'&x"E1DE",'1'&x"E1DF",
+--'1'&x"E1E0",'1'&x"E1E1",'1'&x"E1E2",'1'&x"E1E3",'1'&x"E1E4",'1'&x"E1E5",'1'&x"E1E6",'1'&x"E1E7",'1'&x"E1E8",'1'&x"E1E9",'1'&x"E1EA",'1'&x"E1EB",'1'&x"E1EC",'1'&x"E1ED",'1'&x"E1EE",'1'&x"E1EF",
+--'1'&x"E1F0",'1'&x"E1F1",'1'&x"E1F2",'1'&x"E1F3",'1'&x"E1F4",'1'&x"E1F5",'1'&x"E1F6",'1'&x"E1F7",'1'&x"E1F8",'1'&x"E1F9",'1'&x"E1FA",'1'&x"E1FB",'1'&x"E1FC",'1'&x"E1FD",'1'&x"E1FE",'1'&x"E1FF",
+--'1'&x"E200",'1'&x"E201",'1'&x"E202",'1'&x"E203",'1'&x"E204",'1'&x"E205",'1'&x"E206",'1'&x"E207",'1'&x"E208",'1'&x"E209",'1'&x"E20A",'1'&x"E20B",'1'&x"E20C",'1'&x"E20D",'1'&x"E20E",'1'&x"E20F",
+--'1'&x"E210",'1'&x"E211",'1'&x"E212",'1'&x"E213",'1'&x"E214",'1'&x"E215",'1'&x"E216",'1'&x"E217",'1'&x"E218",'1'&x"E219",'1'&x"E21A",'1'&x"E21B",'1'&x"E21C",'1'&x"E21D",'1'&x"E21E",'1'&x"E21F",
+--'1'&x"E220",'1'&x"E221",'1'&x"E222",'1'&x"E223",'1'&x"E224",'1'&x"E225",'1'&x"E226",'1'&x"E227",'1'&x"E228",'1'&x"E229",'1'&x"E22A",'1'&x"E22B",'1'&x"E22C",'1'&x"E22D",'1'&x"E22E",'1'&x"E22F",
+--'1'&x"E230",'1'&x"E231",'1'&x"E232",'1'&x"E233",'1'&x"E234",'1'&x"E235",'1'&x"E236",'1'&x"E237",'1'&x"E238",'1'&x"E239",'1'&x"E23A",'1'&x"E23B",'1'&x"E23C",'1'&x"E23D",'1'&x"E23E",'1'&x"E23F",
+--'1'&x"E240",'1'&x"E241",'1'&x"E242",'1'&x"E243",'1'&x"E244",'1'&x"E245",'1'&x"E246",'1'&x"E247",'1'&x"E248",'1'&x"E249",'1'&x"E24A",'1'&x"E24B",'1'&x"E24C",'1'&x"E24D",'1'&x"E24E",'1'&x"E24F",
+--'1'&x"E250",'1'&x"E251",'1'&x"E252",'1'&x"E253",'1'&x"E254",'1'&x"E255",'1'&x"E256",'1'&x"E257",'1'&x"E258",'1'&x"E259",'1'&x"E25A",'1'&x"E25B",'1'&x"E25C",'1'&x"E25D",'1'&x"E25E",'1'&x"E25F",
+--'1'&x"E260",'1'&x"E261",'1'&x"E262",'1'&x"E263",'1'&x"E264",'1'&x"E265",'1'&x"E266",'1'&x"E267",'1'&x"E268",'1'&x"E269",'1'&x"E26A",'1'&x"E26B",'1'&x"E26C",'1'&x"E26D",'1'&x"E26E",'1'&x"E26F",
+--'1'&x"E270",'1'&x"E271",'1'&x"E272",'1'&x"E273",'1'&x"E274",'1'&x"E275",'1'&x"E276",'1'&x"E277",'1'&x"E278",'1'&x"E279",'1'&x"E27A",'1'&x"E27B",'1'&x"E27C",'1'&x"E27D",'1'&x"E27E",'1'&x"E27F",
+--'1'&x"E280",'1'&x"E281",'1'&x"E282",'1'&x"E283",'1'&x"E284",'1'&x"E285",'1'&x"E286",'1'&x"E287",'1'&x"E288",'1'&x"E289",'1'&x"E28A",'1'&x"E28B",'1'&x"E28C",'1'&x"E28D",'1'&x"E28E",'1'&x"E28F",
+--'1'&x"E290",'1'&x"E291",'1'&x"E292",'1'&x"E293",'1'&x"E294",'1'&x"E295",'1'&x"E296",'1'&x"E297",'1'&x"E298",'1'&x"E299",'1'&x"E29A",'1'&x"E29B",'1'&x"E29C",'1'&x"E29D",'1'&x"E29E",'1'&x"E29F",
+--'1'&x"E2A0",'1'&x"E2A1",'1'&x"E2A2",'1'&x"E2A3",'1'&x"E2A4",'1'&x"E2A5",'1'&x"E2A6",'1'&x"E2A7",'1'&x"E2A8",'1'&x"E2A9",'1'&x"E2AA",'1'&x"E2AB",'1'&x"E2AC",'1'&x"E2AD",'1'&x"E2AE",'1'&x"E2AF",
+--'1'&x"E2B0",'1'&x"E2B1",'1'&x"E2B2",'1'&x"E2B3",'1'&x"E2B4",'1'&x"E2B5",'1'&x"E2B6",'1'&x"E2B7",'1'&x"E2B8",'1'&x"E2B9",'1'&x"E2BA",'1'&x"E2BB",'1'&x"E2BC",'1'&x"E2BD",'1'&x"E2BE",'1'&x"E2BF",
+--'1'&x"E2C0",'1'&x"E2C1",'1'&x"E2C2",'1'&x"E2C3",'1'&x"E2C4",'1'&x"E2C5",'1'&x"E2C6",'1'&x"E2C7",'1'&x"E2C8",'1'&x"E2C9",'1'&x"E2CA",'1'&x"E2CB",'1'&x"E2CC",'1'&x"E2CD",'1'&x"E2CE",'1'&x"E2CF",
+--'1'&x"E2D0",'1'&x"E2D1",'1'&x"E2D2",'1'&x"E2D3",'1'&x"E2D4",'1'&x"E2D5",'1'&x"E2D6",'1'&x"E2D7",'1'&x"E2D8",'1'&x"E2D9",'1'&x"E2DA",'1'&x"E2DB",'1'&x"E2DC",'1'&x"E2DD",'1'&x"E2DE",'1'&x"E2DF",
+--'1'&x"E2E0",'1'&x"E2E1",'1'&x"E2E2",'1'&x"E2E3",'1'&x"E2E4",'1'&x"E2E5",'1'&x"E2E6",'1'&x"E2E7",'1'&x"E2E8",'1'&x"E2E9",'1'&x"E2EA",'1'&x"E2EB",'1'&x"E2EC",'1'&x"E2ED",'1'&x"E2EE",'1'&x"E2EF",
+--'1'&x"E2F0",'1'&x"E2F1",'1'&x"E2F2",'1'&x"E2F3",'1'&x"E2F4",'1'&x"E2F5",'1'&x"E2F6",'1'&x"E2F7",'1'&x"E2F8",'1'&x"E2F9",'1'&x"E2FA",'1'&x"E2FB",'1'&x"E2FC",'1'&x"E2FD",'1'&x"E2FE",'1'&x"E2FF",
+--'1'&x"E300",'1'&x"E301",'1'&x"E302",'1'&x"E303",'1'&x"E304",'1'&x"E305",'1'&x"E306",'1'&x"E307",'1'&x"E308",'1'&x"E309",'1'&x"E30A",'1'&x"E30B",'1'&x"E30C",'1'&x"E30D",'1'&x"E30E",'1'&x"E30F",
+--'1'&x"E310",'1'&x"E311",'1'&x"E312",'1'&x"E313",'1'&x"E314",'1'&x"E315",'1'&x"E316",'1'&x"E317",'1'&x"E318",'1'&x"E319",'1'&x"E31A",'1'&x"E31B",'1'&x"E31C",'1'&x"E31D",'1'&x"E31E",'1'&x"E31F",
+--'1'&x"E320",'1'&x"E321",'1'&x"E322",'1'&x"E323",'1'&x"E324",'1'&x"E325",'1'&x"E326",'1'&x"E327",'1'&x"E328",'1'&x"E329",'1'&x"E32A",'1'&x"E32B",'1'&x"E32C",'1'&x"E32D",'1'&x"E32E",'1'&x"E32F",
+--'1'&x"E330",'1'&x"E331",'1'&x"E332",'1'&x"E333",'1'&x"E334",'1'&x"E335",'1'&x"E336",'1'&x"E337",'1'&x"E338",'1'&x"E339",'1'&x"E33A",'1'&x"E33B",'1'&x"E33C",'1'&x"E33D",'1'&x"E33E",'1'&x"E33F",
+--'1'&x"E340",'1'&x"E341",'1'&x"E342",'1'&x"E343",'1'&x"E344",'1'&x"E345",'1'&x"E346",'1'&x"E347",'1'&x"E348",'1'&x"E349",'1'&x"E34A",'1'&x"E34B",'1'&x"E34C",'1'&x"E34D",'1'&x"E34E",'1'&x"E34F",
+--'1'&x"E350",'1'&x"E351",'1'&x"E352",'1'&x"E353",'1'&x"E354",'1'&x"E355",'1'&x"E356",'1'&x"E357",'1'&x"E358",'1'&x"E359",'1'&x"E35A",'1'&x"E35B",'1'&x"E35C",'1'&x"E35D",'1'&x"E35E",'1'&x"E35F",
+--'1'&x"E360",'1'&x"E361",'1'&x"E362",'1'&x"E363",'1'&x"E364",'1'&x"E365",'1'&x"E366",'1'&x"E367",'1'&x"E368",'1'&x"E369",'1'&x"E36A",'1'&x"E36B",'1'&x"E36C",'1'&x"E36D",'1'&x"E36E",'1'&x"E36F",
+--'1'&x"E370",'1'&x"E371",'1'&x"E372",'1'&x"E373",'1'&x"E374",'1'&x"E375",'1'&x"E376",'1'&x"E377",'1'&x"E378",'1'&x"E379",'1'&x"E37A",'1'&x"E37B",'1'&x"E37C",'1'&x"E37D",'1'&x"E37E",'1'&x"E37F",
+--'1'&x"E380",'1'&x"E381",'1'&x"E382",'1'&x"E383",'1'&x"E384",'1'&x"E385",'1'&x"E386",'1'&x"E387",'1'&x"E388",'1'&x"E389",'1'&x"E38A",'1'&x"E38B",'1'&x"E38C",'1'&x"E38D",'1'&x"E38E",'1'&x"E38F",
+--'1'&x"E390",'1'&x"E391",'1'&x"E392",'1'&x"E393",'1'&x"E394",'1'&x"E395",'1'&x"E396",'1'&x"E397",'1'&x"E398",'1'&x"E399",'1'&x"E39A",'1'&x"E39B",'1'&x"E39C",'1'&x"E39D",'1'&x"E39E",'1'&x"E39F",
+--'1'&x"E3A0",'1'&x"E3A1",'1'&x"E3A2",'1'&x"E3A3",'1'&x"E3A4",'1'&x"E3A5",'1'&x"E3A6",'1'&x"E3A7",'1'&x"E3A8",'1'&x"E3A9",'1'&x"E3AA",'1'&x"E3AB",'1'&x"E3AC",'1'&x"E3AD",'1'&x"E3AE",'1'&x"E3AF",
+--'1'&x"E3B0",'1'&x"E3B1",'1'&x"E3B2",'1'&x"E3B3",'1'&x"E3B4",'1'&x"E3B5",'1'&x"E3B6",'1'&x"E3B7",'1'&x"E3B8",'1'&x"E3B9",'1'&x"E3BA",'1'&x"E3BB",'1'&x"E3BC",'1'&x"E3BD",'1'&x"E3BE",'1'&x"E3BF",
+--'1'&x"E3C0",'1'&x"E3C1",'1'&x"E3C2",'1'&x"E3C3",'1'&x"E3C4",'1'&x"E3C5",'1'&x"E3C6",'1'&x"E3C7",'1'&x"E3C8",'1'&x"E3C9",'1'&x"E3CA",'1'&x"E3CB",'1'&x"E3CC",'1'&x"E3CD",'1'&x"E3CE",'1'&x"E3CF",
+--'1'&x"E3D0",'1'&x"E3D1",'1'&x"E3D2",'1'&x"E3D3",'1'&x"E3D4",'1'&x"E3D5",'1'&x"E3D6",'1'&x"E3D7",'1'&x"E3D8",'1'&x"E3D9",'1'&x"E3DA",'1'&x"E3DB",'1'&x"E3DC",'1'&x"E3DD",'1'&x"E3DE",'1'&x"E3DF",
+--'1'&x"E3E0",'1'&x"E3E1",'1'&x"E3E2",'1'&x"E3E3",'1'&x"E3E4",'1'&x"E3E5",'1'&x"E3E6",'1'&x"E3E7",'1'&x"E3E8",'1'&x"E3E9",'1'&x"E3EA",'1'&x"E3EB",'1'&x"E3EC",'1'&x"E3ED",'1'&x"E3EE",'1'&x"E3EF",
+--'1'&x"E3F0",'1'&x"E3F1",'1'&x"E3F2",'1'&x"E3F3",'1'&x"E3F4",'1'&x"E3F5",'1'&x"E3F6",'1'&x"E3F7",'1'&x"E3F8",'1'&x"E3F9",'1'&x"E3FA",'1'&x"E3FB",'1'&x"E3FC",'1'&x"E3FD",'1'&x"E3FE",'1'&x"E3FF",
+--'1'&x"E400",'1'&x"E401",'1'&x"E402",'1'&x"E403",'1'&x"E404",'1'&x"E405",'1'&x"E406",'1'&x"E407",'1'&x"E408",'1'&x"E409",'1'&x"E40A",'1'&x"E40B",'1'&x"E40C",'1'&x"E40D",'1'&x"E40E",'1'&x"E40F",
+--'1'&x"E410",'1'&x"E411",'1'&x"E412",'1'&x"E413",'1'&x"E414",'1'&x"E415",'1'&x"E416",'1'&x"E417",'1'&x"E418",'1'&x"E419",'1'&x"E41A",'1'&x"E41B",'1'&x"E41C",'1'&x"E41D",'1'&x"E41E",'1'&x"E41F",
+--'1'&x"E420",'1'&x"E421",'1'&x"E422",'1'&x"E423",'1'&x"E424",'1'&x"E425",'1'&x"E426",'1'&x"E427",'1'&x"E428",'1'&x"E429",'1'&x"E42A",'1'&x"E42B",'1'&x"E42C",'1'&x"E42D",'1'&x"E42E",'1'&x"E42F",
+--'1'&x"E430",'1'&x"E431",'1'&x"E432",'1'&x"E433",'1'&x"E434",'1'&x"E435",'1'&x"E436",'1'&x"E437",'1'&x"E438",'1'&x"E439",'1'&x"E43A",'1'&x"E43B",'1'&x"E43C",'1'&x"E43D",'1'&x"E43E",'1'&x"E43F",
+--'1'&x"E440",'1'&x"E441",'1'&x"E442",'1'&x"E443",'1'&x"E444",'1'&x"E445",'1'&x"E446",'1'&x"E447",'1'&x"E448",'1'&x"E449",'1'&x"E44A",'1'&x"E44B",'1'&x"E44C",'1'&x"E44D",'1'&x"E44E",'1'&x"E44F",
+--'1'&x"E450",'1'&x"E451",'1'&x"E452",'1'&x"E453",'1'&x"E454",'1'&x"E455",'1'&x"E456",'1'&x"E457",'1'&x"E458",'1'&x"E459",'1'&x"E45A",'1'&x"E45B",'1'&x"E45C",'1'&x"E45D",'1'&x"E45E",'1'&x"E45F",
+--'1'&x"E460",'1'&x"E461",'1'&x"E462",'1'&x"E463",'1'&x"E464",'1'&x"E465",'1'&x"E466",'1'&x"E467",'1'&x"E468",'1'&x"E469",'1'&x"E46A",'1'&x"E46B",'1'&x"E46C",'1'&x"E46D",'1'&x"E46E",'1'&x"E46F",
+--'1'&x"E470",'1'&x"E471",'1'&x"E472",'1'&x"E473",'1'&x"E474",'1'&x"E475",'1'&x"E476",'1'&x"E477",'1'&x"E478",'1'&x"E479",'1'&x"E47A",'1'&x"E47B",'1'&x"E47C",'1'&x"E47D",'1'&x"E47E",'1'&x"E47F",
+--'1'&x"E480",'1'&x"E481",'1'&x"E482",'1'&x"E483",'1'&x"E484",'1'&x"E485",'1'&x"E486",'1'&x"E487",'1'&x"E488",'1'&x"E489",'1'&x"E48A",'1'&x"E48B",'1'&x"E48C",'1'&x"E48D",'1'&x"E48E",'1'&x"E48F",
+--'1'&x"E490",'1'&x"E491",'1'&x"E492",'1'&x"E493",'1'&x"E494",'1'&x"E495",'1'&x"E496",'1'&x"E497",'1'&x"E498",'1'&x"E499",'1'&x"E49A",'1'&x"E49B",'1'&x"E49C",'1'&x"E49D",'1'&x"E49E",'1'&x"E49F",
+--'1'&x"E4A0",'1'&x"E4A1",'1'&x"E4A2",'1'&x"E4A3",'1'&x"E4A4",'1'&x"E4A5",'1'&x"E4A6",'1'&x"E4A7",'1'&x"E4A8",'1'&x"E4A9",'1'&x"E4AA",'1'&x"E4AB",'1'&x"E4AC",'1'&x"E4AD",'1'&x"E4AE",'1'&x"E4AF",
+--'1'&x"E4B0",'1'&x"E4B1",'1'&x"E4B2",'1'&x"E4B3",'1'&x"E4B4",'1'&x"E4B5",'1'&x"E4B6",'1'&x"E4B7",'1'&x"E4B8",'1'&x"E4B9",'1'&x"E4BA",'1'&x"E4BB",'1'&x"E4BC",'1'&x"E4BD",'1'&x"E4BE",'1'&x"E4BF",
+--'1'&x"E4C0",'1'&x"E4C1",'1'&x"E4C2",'1'&x"E4C3",'1'&x"E4C4",'1'&x"E4C5",'1'&x"E4C6",'1'&x"E4C7",'1'&x"E4C8",'1'&x"E4C9",'1'&x"E4CA",'1'&x"E4CB",'1'&x"E4CC",'1'&x"E4CD",'1'&x"E4CE",'1'&x"E4CF",
+--'1'&x"E4D0",'1'&x"E4D1",'1'&x"E4D2",'1'&x"E4D3",'1'&x"E4D4",'1'&x"E4D5",'1'&x"E4D6",'1'&x"E4D7",'1'&x"E4D8",'1'&x"E4D9",'1'&x"E4DA",'1'&x"E4DB",'1'&x"E4DC",'1'&x"E4DD",'1'&x"E4DE",'1'&x"E4DF",
+--'1'&x"E4E0",'1'&x"E4E1",'1'&x"E4E2",'1'&x"E4E3",'1'&x"E4E4",'1'&x"E4E5",'1'&x"E4E6",'1'&x"E4E7",'1'&x"E4E8",'1'&x"E4E9",'1'&x"E4EA",'1'&x"E4EB",'1'&x"E4EC",'1'&x"E4ED",'1'&x"E4EE",'1'&x"E4EF",
+--'1'&x"E4F0",'1'&x"E4F1",'1'&x"E4F2",'1'&x"E4F3",'1'&x"E4F4",'1'&x"E4F5",'1'&x"E4F6",'1'&x"E4F7",'1'&x"E4F8",'1'&x"E4F9",'1'&x"E4FA",'1'&x"E4FB",'1'&x"E4FC",'1'&x"E4FD",'1'&x"E4FE",'1'&x"E4FF",
+--'1'&x"E500",'1'&x"E501",'1'&x"E502",'1'&x"E503",'1'&x"E504",'1'&x"E505",'1'&x"E506",'1'&x"E507",'1'&x"E508",'1'&x"E509",'1'&x"E50A",'1'&x"E50B",'1'&x"E50C",'1'&x"E50D",'1'&x"E50E",'1'&x"E50F",
+--'1'&x"E510",'1'&x"E511",'1'&x"E512",'1'&x"E513",'1'&x"E514",'1'&x"E515",'1'&x"E516",'1'&x"E517",'1'&x"E518",'1'&x"E519",'1'&x"E51A",'1'&x"E51B",'1'&x"E51C",'1'&x"E51D",'1'&x"E51E",'1'&x"E51F",
+--'1'&x"E520",'1'&x"E521",'1'&x"E522",'1'&x"E523",'1'&x"E524",'1'&x"E525",'1'&x"E526",'1'&x"E527",'1'&x"E528",'1'&x"E529",'1'&x"E52A",'1'&x"E52B",'1'&x"E52C",'1'&x"E52D",'1'&x"E52E",'1'&x"E52F",
+--'1'&x"E530",'1'&x"E531",'1'&x"E532",'1'&x"E533",'1'&x"E534",'1'&x"E535",'1'&x"E536",'1'&x"E537",'1'&x"E538",'1'&x"E539",'1'&x"E53A",'1'&x"E53B",'1'&x"E53C",'1'&x"E53D",'1'&x"E53E",'1'&x"E53F",
+--'1'&x"E540",'1'&x"E541",'1'&x"E542",'1'&x"E543",'1'&x"E544",'1'&x"E545",'1'&x"E546",'1'&x"E547",'1'&x"E548",'1'&x"E549",'1'&x"E54A",'1'&x"E54B",'1'&x"E54C",'1'&x"E54D",'1'&x"E54E",'1'&x"E54F",
+--'1'&x"E550",'1'&x"E551",'1'&x"E552",'1'&x"E553",'1'&x"E554",'1'&x"E555",'1'&x"E556",'1'&x"E557",'1'&x"E558",'1'&x"E559",'1'&x"E55A",'1'&x"E55B",'1'&x"E55C",'1'&x"E55D",'1'&x"E55E",'1'&x"E55F",
+--'1'&x"E560",'1'&x"E561",'1'&x"E562",'1'&x"E563",'1'&x"E564",'1'&x"E565",'1'&x"E566",'1'&x"E567",'1'&x"E568",'1'&x"E569",'1'&x"E56A",'1'&x"E56B",'1'&x"E56C",'1'&x"E56D",'1'&x"E56E",'1'&x"E56F",
+--'1'&x"E570",'1'&x"E571",'1'&x"E572",'1'&x"E573",'1'&x"E574",'1'&x"E575",'1'&x"E576",'1'&x"E577",'1'&x"E578",'1'&x"E579",'1'&x"E57A",'1'&x"E57B",'1'&x"E57C",'1'&x"E57D",'1'&x"E57E",'1'&x"E57F",
+--'1'&x"E580",'1'&x"E581",'1'&x"E582",'1'&x"E583",'1'&x"E584",'1'&x"E585",'1'&x"E586",'1'&x"E587",'1'&x"E588",'1'&x"E589",'1'&x"E58A",'1'&x"E58B",'1'&x"E58C",'1'&x"E58D",'1'&x"E58E",'1'&x"E58F",
+--'1'&x"E590",'1'&x"E591",'1'&x"E592",'1'&x"E593",'1'&x"E594",'1'&x"E595",'1'&x"E596",'1'&x"E597",'1'&x"E598",'1'&x"E599",'1'&x"E59A",'1'&x"E59B",'1'&x"E59C",'1'&x"E59D",'1'&x"E59E",'1'&x"E59F",
+--'1'&x"E5A0",'1'&x"E5A1",'1'&x"E5A2",'1'&x"E5A3",'1'&x"E5A4",'1'&x"E5A5",'1'&x"E5A6",'1'&x"E5A7",'1'&x"E5A8",'1'&x"E5A9",'1'&x"E5AA",'1'&x"E5AB",'1'&x"E5AC",'1'&x"E5AD",'1'&x"E5AE",'1'&x"E5AF",
+--'1'&x"E5B0",'1'&x"E5B1",'1'&x"E5B2",'1'&x"E5B3",'1'&x"E5B4",'1'&x"E5B5",'1'&x"E5B6",'1'&x"E5B7",'1'&x"E5B8",'1'&x"E5B9",'1'&x"E5BA",'1'&x"E5BB",'1'&x"E5BC",'1'&x"E5BD",'1'&x"E5BE",'1'&x"E5BF",
+--'1'&x"E5C0",'1'&x"E5C1",'1'&x"E5C2",'1'&x"E5C3",'1'&x"E5C4",'1'&x"E5C5",'1'&x"E5C6",'1'&x"E5C7",'1'&x"E5C8",'1'&x"E5C9",'1'&x"E5CA",'1'&x"E5CB",'1'&x"E5CC",'1'&x"E5CD",'1'&x"E5CE",'1'&x"E5CF",
+--'1'&x"E5D0",'1'&x"E5D1",'1'&x"E5D2",'1'&x"E5D3",'1'&x"E5D4",'1'&x"E5D5",'1'&x"E5D6",'1'&x"E5D7",'1'&x"E5D8",'1'&x"E5D9",'1'&x"E5DA",'1'&x"E5DB",'1'&x"E5DC",'1'&x"E5DD",'1'&x"E5DE",'1'&x"E5DF",
+--'1'&x"E5E0",'1'&x"E5E1",'1'&x"E5E2",'1'&x"E5E3",'1'&x"E5E4",'1'&x"E5E5",'1'&x"E5E6",'1'&x"E5E7",'1'&x"E5E8",'1'&x"E5E9",'1'&x"E5EA",'1'&x"E5EB",'1'&x"E5EC",'1'&x"E5ED",'1'&x"E5EE",'1'&x"E5EF",
+--'1'&x"E5F0",'1'&x"E5F1",'1'&x"E5F2",'1'&x"E5F3",'1'&x"E5F4",'1'&x"E5F5",'1'&x"E5F6",'1'&x"E5F7",'1'&x"E5F8",'1'&x"E5F9",'1'&x"E5FA",'1'&x"E5FB",'1'&x"E5FC",'1'&x"E5FD",'1'&x"E5FE",'1'&x"E5FF",
+--'1'&x"E600",'1'&x"E601",'1'&x"E602",'1'&x"E603",'1'&x"E604",'1'&x"E605",'1'&x"E606",'1'&x"E607",'1'&x"E608",'1'&x"E609",'1'&x"E60A",'1'&x"E60B",'1'&x"E60C",'1'&x"E60D",'1'&x"E60E",'1'&x"E60F",
+--'1'&x"E610",'1'&x"E611",'1'&x"E612",'1'&x"E613",'1'&x"E614",'1'&x"E615",'1'&x"E616",'1'&x"E617",'1'&x"E618",'1'&x"E619",'1'&x"E61A",'1'&x"E61B",'1'&x"E61C",'1'&x"E61D",'1'&x"E61E",'1'&x"E61F",
+--'1'&x"E620",'1'&x"E621",'1'&x"E622",'1'&x"E623",'1'&x"E624",'1'&x"E625",'1'&x"E626",'1'&x"E627",'1'&x"E628",'1'&x"E629",'1'&x"E62A",'1'&x"E62B",'1'&x"E62C",'1'&x"E62D",'1'&x"E62E",'1'&x"E62F",
+--'1'&x"E630",'1'&x"E631",'1'&x"E632",'1'&x"E633",'1'&x"E634",'1'&x"E635",'1'&x"E636",'1'&x"E637",'1'&x"E638",'1'&x"E639",'1'&x"E63A",'1'&x"E63B",'1'&x"E63C",'1'&x"E63D",'1'&x"E63E",'1'&x"E63F",
+--'1'&x"E640",'1'&x"E641",'1'&x"E642",'1'&x"E643",'1'&x"E644",'1'&x"E645",'1'&x"E646",'1'&x"E647",'1'&x"E648",'1'&x"E649",'1'&x"E64A",'1'&x"E64B",'1'&x"E64C",'1'&x"E64D",'1'&x"E64E",'1'&x"E64F",
+--'1'&x"E650",'1'&x"E651",'1'&x"E652",'1'&x"E653",'1'&x"E654",'1'&x"E655",'1'&x"E656",'1'&x"E657",'1'&x"E658",'1'&x"E659",'1'&x"E65A",'1'&x"E65B",'1'&x"E65C",'1'&x"E65D",'1'&x"E65E",'1'&x"E65F",
+--'1'&x"E660",'1'&x"E661",'1'&x"E662",'1'&x"E663",'1'&x"E664",'1'&x"E665",'1'&x"E666",'1'&x"E667",'1'&x"E668",'1'&x"E669",'1'&x"E66A",'1'&x"E66B",'1'&x"E66C",'1'&x"E66D",'1'&x"E66E",'1'&x"E66F",
+--'1'&x"E670",'1'&x"E671",'1'&x"E672",'1'&x"E673",'1'&x"E674",'1'&x"E675",'1'&x"E676",'1'&x"E677",'1'&x"E678",'1'&x"E679",'1'&x"E67A",'1'&x"E67B",'1'&x"E67C",'1'&x"E67D",'1'&x"E67E",'1'&x"E67F",
+--'1'&x"E680",'1'&x"E681",'1'&x"E682",'1'&x"E683",'1'&x"E684",'1'&x"E685",'1'&x"E686",'1'&x"E687",'1'&x"E688",'1'&x"E689",'1'&x"E68A",'1'&x"E68B",'1'&x"E68C",'1'&x"E68D",'1'&x"E68E",'1'&x"E68F",
+--'1'&x"E690",'1'&x"E691",'1'&x"E692",'1'&x"E693",'1'&x"E694",'1'&x"E695",'1'&x"E696",'1'&x"E697",'1'&x"E698",'1'&x"E699",'1'&x"E69A",'1'&x"E69B",'1'&x"E69C",'1'&x"E69D",'1'&x"E69E",'1'&x"E69F",
+--'1'&x"E6A0",'1'&x"E6A1",'1'&x"E6A2",'1'&x"E6A3",'1'&x"E6A4",'1'&x"E6A5",'1'&x"E6A6",'1'&x"E6A7",'1'&x"E6A8",'1'&x"E6A9",'1'&x"E6AA",'1'&x"E6AB",'1'&x"E6AC",'1'&x"E6AD",'1'&x"E6AE",'1'&x"E6AF",
+--'1'&x"E6B0",'1'&x"E6B1",'1'&x"E6B2",'1'&x"E6B3",'1'&x"E6B4",'1'&x"E6B5",'1'&x"E6B6",'1'&x"E6B7",'1'&x"E6B8",'1'&x"E6B9",'1'&x"E6BA",'1'&x"E6BB",'1'&x"E6BC",'1'&x"E6BD",'1'&x"E6BE",'1'&x"E6BF",
+--'1'&x"E6C0",'1'&x"E6C1",'1'&x"E6C2",'1'&x"E6C3",'1'&x"E6C4",'1'&x"E6C5",'1'&x"E6C6",'1'&x"E6C7",'1'&x"E6C8",'1'&x"E6C9",'1'&x"E6CA",'1'&x"E6CB",'1'&x"E6CC",'1'&x"E6CD",'1'&x"E6CE",'1'&x"E6CF",
+--'1'&x"E6D0",'1'&x"E6D1",'1'&x"E6D2",'1'&x"E6D3",'1'&x"E6D4",'1'&x"E6D5",'1'&x"E6D6",'1'&x"E6D7",'1'&x"E6D8",'1'&x"E6D9",'1'&x"E6DA",'1'&x"E6DB",'1'&x"E6DC",'1'&x"E6DD",'1'&x"E6DE",'1'&x"E6DF",
+--'1'&x"E6E0",'1'&x"E6E1",'1'&x"E6E2",'1'&x"E6E3",'1'&x"E6E4",'1'&x"E6E5",'1'&x"E6E6",'1'&x"E6E7",'1'&x"E6E8",'1'&x"E6E9",'1'&x"E6EA",'1'&x"E6EB",'1'&x"E6EC",'1'&x"E6ED",'1'&x"E6EE",'1'&x"E6EF",
+--'1'&x"E6F0",'1'&x"E6F1",'1'&x"E6F2",'1'&x"E6F3",'1'&x"E6F4",'1'&x"E6F5",'1'&x"E6F6",'1'&x"E6F7",'1'&x"E6F8",'1'&x"E6F9",'1'&x"E6FA",'1'&x"E6FB",'1'&x"E6FC",'1'&x"E6FD",'1'&x"E6FE",'1'&x"E6FF",
+--'1'&x"E700",'1'&x"E701",'1'&x"E702",'1'&x"E703",'1'&x"E704",'1'&x"E705",'1'&x"E706",'1'&x"E707",'1'&x"E708",'1'&x"E709",'1'&x"E70A",'1'&x"E70B",'1'&x"E70C",'1'&x"E70D",'1'&x"E70E",'1'&x"E70F",
+--'1'&x"E710",'1'&x"E711",'1'&x"E712",'1'&x"E713",'1'&x"E714",'1'&x"E715",'1'&x"E716",'1'&x"E717",'1'&x"E718",'1'&x"E719",'1'&x"E71A",'1'&x"E71B",'1'&x"E71C",'1'&x"E71D",'1'&x"E71E",'1'&x"E71F",
+--'1'&x"E720",'1'&x"E721",'1'&x"E722",'1'&x"E723",'1'&x"E724",'1'&x"E725",'1'&x"E726",'1'&x"E727",'1'&x"E728",'1'&x"E729",'1'&x"E72A",'1'&x"E72B",'1'&x"E72C",'1'&x"E72D",'1'&x"E72E",'1'&x"E72F",
+--'1'&x"E730",'1'&x"E731",'1'&x"E732",'1'&x"E733",'1'&x"E734",'1'&x"E735",'1'&x"E736",'1'&x"E737",'1'&x"E738",'1'&x"E739",'1'&x"E73A",'1'&x"E73B",'1'&x"E73C",'1'&x"E73D",'1'&x"E73E",'1'&x"E73F",
+--'1'&x"E740",'1'&x"E741",'1'&x"E742",'1'&x"E743",'1'&x"E744",'1'&x"E745",'1'&x"E746",'1'&x"E747",'1'&x"E748",'1'&x"E749",'1'&x"E74A",'1'&x"E74B",'1'&x"E74C",'1'&x"E74D",'1'&x"E74E",'1'&x"E74F",
+--'1'&x"E750",'1'&x"E751",'1'&x"E752",'1'&x"E753",'1'&x"E754",'1'&x"E755",'1'&x"E756",'1'&x"E757",'1'&x"E758",'1'&x"E759",'1'&x"E75A",'1'&x"E75B",'1'&x"E75C",'1'&x"E75D",'1'&x"E75E",'1'&x"E75F",
+--'1'&x"E760",'1'&x"E761",'1'&x"E762",'1'&x"E763",'1'&x"E764",'1'&x"E765",'1'&x"E766",'1'&x"E767",'1'&x"E768",'1'&x"E769",'1'&x"E76A",'1'&x"E76B",'1'&x"E76C",'1'&x"E76D",'1'&x"E76E",'1'&x"E76F",
+--'1'&x"E770",'1'&x"E771",'1'&x"E772",'1'&x"E773",'1'&x"E774",'1'&x"E775",'1'&x"E776",'1'&x"E777",'1'&x"E778",'1'&x"E779",'1'&x"E77A",'1'&x"E77B",'1'&x"E77C",'1'&x"E77D",'1'&x"E77E",'1'&x"E77F",
+--'1'&x"E780",'1'&x"E781",'1'&x"E782",'1'&x"E783",'1'&x"E784",'1'&x"E785",'1'&x"E786",'1'&x"E787",'1'&x"E788",'1'&x"E789",'1'&x"E78A",'1'&x"E78B",'1'&x"E78C",'1'&x"E78D",'1'&x"E78E",'1'&x"E78F",
+--'1'&x"E790",'1'&x"E791",'1'&x"E792",'1'&x"E793",'1'&x"E794",'1'&x"E795",'1'&x"E796",'1'&x"E797",'1'&x"E798",'1'&x"E799",'1'&x"E79A",'1'&x"E79B",'1'&x"E79C",'1'&x"E79D",'1'&x"E79E",'1'&x"E79F",
+--'1'&x"E7A0",'1'&x"E7A1",'1'&x"E7A2",'1'&x"E7A3",'1'&x"E7A4",'1'&x"E7A5",'1'&x"E7A6",'1'&x"E7A7",'1'&x"E7A8",'1'&x"E7A9",'1'&x"E7AA",'1'&x"E7AB",'1'&x"E7AC",'1'&x"E7AD",'1'&x"E7AE",'1'&x"E7AF",
+--'1'&x"E7B0",'1'&x"E7B1",'1'&x"E7B2",'1'&x"E7B3",'1'&x"E7B4",'1'&x"E7B5",'1'&x"E7B6",'1'&x"E7B7",'1'&x"E7B8",'1'&x"E7B9",'1'&x"E7BA",'1'&x"E7BB",'1'&x"E7BC",'1'&x"E7BD",'1'&x"E7BE",'1'&x"E7BF",
+--'1'&x"E7C0",'1'&x"E7C1",'1'&x"E7C2",'1'&x"E7C3",'1'&x"E7C4",'1'&x"E7C5",'1'&x"E7C6",'1'&x"E7C7",'1'&x"E7C8",'1'&x"E7C9",'1'&x"E7CA",'1'&x"E7CB",'1'&x"E7CC",'1'&x"E7CD",'1'&x"E7CE",'1'&x"E7CF",
+--'1'&x"E7D0",'1'&x"E7D1",'1'&x"E7D2",'1'&x"E7D3",'1'&x"E7D4",'1'&x"E7D5",'1'&x"E7D6",'1'&x"E7D7",'1'&x"E7D8",'1'&x"E7D9",'1'&x"E7DA",'1'&x"E7DB",'1'&x"E7DC",'1'&x"E7DD",'1'&x"E7DE",'1'&x"E7DF",
+--'1'&x"E7E0",'1'&x"E7E1",'1'&x"E7E2",'1'&x"E7E3",'1'&x"E7E4",'1'&x"E7E5",'1'&x"E7E6",'1'&x"E7E7",'1'&x"E7E8",'1'&x"E7E9",'1'&x"E7EA",'1'&x"E7EB",'1'&x"E7EC",'1'&x"E7ED",'1'&x"E7EE",'1'&x"E7EF",
+--'1'&x"E7F0",'1'&x"E7F1",'1'&x"E7F2",'1'&x"E7F3",'1'&x"E7F4",'1'&x"E7F5",'1'&x"E7F6",'1'&x"E7F7",'1'&x"E7F8",'1'&x"E7F9",'1'&x"E7FA",'1'&x"E7FB",'1'&x"E7FC",'1'&x"E7FD",'1'&x"E7FE",'1'&x"E7FF",
+--'1'&x"E800",'1'&x"E801",'1'&x"E802",'1'&x"E803",'1'&x"E804",'1'&x"E805",'1'&x"E806",'1'&x"E807",'1'&x"E808",'1'&x"E809",'1'&x"E80A",'1'&x"E80B",'1'&x"E80C",'1'&x"E80D",'1'&x"E80E",'1'&x"E80F",
+--'1'&x"E810",'1'&x"E811",'1'&x"E812",'1'&x"E813",'1'&x"E814",'1'&x"E815",'1'&x"E816",'1'&x"E817",'1'&x"E818",'1'&x"E819",'1'&x"E81A",'1'&x"E81B",'1'&x"E81C",'1'&x"E81D",'1'&x"E81E",'1'&x"E81F",
+--'1'&x"E820",'1'&x"E821",'1'&x"E822",'1'&x"E823",'1'&x"E824",'1'&x"E825",'1'&x"E826",'1'&x"E827",'1'&x"E828",'1'&x"E829",'1'&x"E82A",'1'&x"E82B",'1'&x"E82C",'1'&x"E82D",'1'&x"E82E",'1'&x"E82F",
+--'1'&x"E830",'1'&x"E831",'1'&x"E832",'1'&x"E833",'1'&x"E834",'1'&x"E835",'1'&x"E836",'1'&x"E837",'1'&x"E838",'1'&x"E839",'1'&x"E83A",'1'&x"E83B",'1'&x"E83C",'1'&x"E83D",'1'&x"E83E",'1'&x"E83F",
+--'1'&x"E840",'1'&x"E841",'1'&x"E842",'1'&x"E843",'1'&x"E844",'1'&x"E845",'1'&x"E846",'1'&x"E847",'1'&x"E848",'1'&x"E849",'1'&x"E84A",'1'&x"E84B",'1'&x"E84C",'1'&x"E84D",'1'&x"E84E",'1'&x"E84F",
+--'1'&x"E850",'1'&x"E851",'1'&x"E852",'1'&x"E853",'1'&x"E854",'1'&x"E855",'1'&x"E856",'1'&x"E857",'1'&x"E858",'1'&x"E859",'1'&x"E85A",'1'&x"E85B",'1'&x"E85C",'1'&x"E85D",'1'&x"E85E",'1'&x"E85F",
+--'1'&x"E860",'1'&x"E861",'1'&x"E862",'1'&x"E863",'1'&x"E864",'1'&x"E865",'1'&x"E866",'1'&x"E867",'1'&x"E868",'1'&x"E869",'1'&x"E86A",'1'&x"E86B",'1'&x"E86C",'1'&x"E86D",'1'&x"E86E",'1'&x"E86F",
+--'1'&x"E870",'1'&x"E871",'1'&x"E872",'1'&x"E873",'1'&x"E874",'1'&x"E875",'1'&x"E876",'1'&x"E877",'1'&x"E878",'1'&x"E879",'1'&x"E87A",'1'&x"E87B",'1'&x"E87C",'1'&x"E87D",'1'&x"E87E",'1'&x"E87F",
+--'1'&x"E880",'1'&x"E881",'1'&x"E882",'1'&x"E883",'1'&x"E884",'1'&x"E885",'1'&x"E886",'1'&x"E887",'1'&x"E888",'1'&x"E889",'1'&x"E88A",'1'&x"E88B",'1'&x"E88C",'1'&x"E88D",'1'&x"E88E",'1'&x"E88F",
+--'1'&x"E890",'1'&x"E891",'1'&x"E892",'1'&x"E893",'1'&x"E894",'1'&x"E895",'1'&x"E896",'1'&x"E897",'1'&x"E898",'1'&x"E899",'1'&x"E89A",'1'&x"E89B",'1'&x"E89C",'1'&x"E89D",'1'&x"E89E",'1'&x"E89F",
+--'1'&x"E8A0",'1'&x"E8A1",'1'&x"E8A2",'1'&x"E8A3",'1'&x"E8A4",'1'&x"E8A5",'1'&x"E8A6",'1'&x"E8A7",'1'&x"E8A8",'1'&x"E8A9",'1'&x"E8AA",'1'&x"E8AB",'1'&x"E8AC",'1'&x"E8AD",'1'&x"E8AE",'1'&x"E8AF",
+--'1'&x"E8B0",'1'&x"E8B1",'1'&x"E8B2",'1'&x"E8B3",'1'&x"E8B4",'1'&x"E8B5",'1'&x"E8B6",'1'&x"E8B7",'1'&x"E8B8",'1'&x"E8B9",'1'&x"E8BA",'1'&x"E8BB",'1'&x"E8BC",'1'&x"E8BD",'1'&x"E8BE",'1'&x"E8BF",
+--'1'&x"E8C0",'1'&x"E8C1",'1'&x"E8C2",'1'&x"E8C3",'1'&x"E8C4",'1'&x"E8C5",'1'&x"E8C6",'1'&x"E8C7",'1'&x"E8C8",'1'&x"E8C9",'1'&x"E8CA",'1'&x"E8CB",'1'&x"E8CC",'1'&x"E8CD",'1'&x"E8CE",'1'&x"E8CF",
+--'1'&x"E8D0",'1'&x"E8D1",'1'&x"E8D2",'1'&x"E8D3",'1'&x"E8D4",'1'&x"E8D5",'1'&x"E8D6",'1'&x"E8D7",'1'&x"E8D8",'1'&x"E8D9",'1'&x"E8DA",'1'&x"E8DB",'1'&x"E8DC",'1'&x"E8DD",'1'&x"E8DE",'1'&x"E8DF",
+--'1'&x"E8E0",'1'&x"E8E1",'1'&x"E8E2",'1'&x"E8E3",'1'&x"E8E4",'1'&x"E8E5",'1'&x"E8E6",'1'&x"E8E7",'1'&x"E8E8",'1'&x"E8E9",'1'&x"E8EA",'1'&x"E8EB",'1'&x"E8EC",'1'&x"E8ED",'1'&x"E8EE",'1'&x"E8EF",
+--'1'&x"E8F0",'1'&x"E8F1",'1'&x"E8F2",'1'&x"E8F3",'1'&x"E8F4",'1'&x"E8F5",'1'&x"E8F6",'1'&x"E8F7",'1'&x"E8F8",'1'&x"E8F9",'1'&x"E8FA",'1'&x"E8FB",'1'&x"E8FC",'1'&x"E8FD",'1'&x"E8FE",'1'&x"E8FF",
+--'1'&x"E900",'1'&x"E901",'1'&x"E902",'1'&x"E903",'1'&x"E904",'1'&x"E905",'1'&x"E906",'1'&x"E907",'1'&x"E908",'1'&x"E909",'1'&x"E90A",'1'&x"E90B",'1'&x"E90C",'1'&x"E90D",'1'&x"E90E",'1'&x"E90F",
+--'1'&x"E910",'1'&x"E911",'1'&x"E912",'1'&x"E913",'1'&x"E914",'1'&x"E915",'1'&x"E916",'1'&x"E917",'1'&x"E918",'1'&x"E919",'1'&x"E91A",'1'&x"E91B",'1'&x"E91C",'1'&x"E91D",'1'&x"E91E",'1'&x"E91F",
+--'1'&x"E920",'1'&x"E921",'1'&x"E922",'1'&x"E923",'1'&x"E924",'1'&x"E925",'1'&x"E926",'1'&x"E927",'1'&x"E928",'1'&x"E929",'1'&x"E92A",'1'&x"E92B",'1'&x"E92C",'1'&x"E92D",'1'&x"E92E",'1'&x"E92F",
+--'1'&x"E930",'1'&x"E931",'1'&x"E932",'1'&x"E933",'1'&x"E934",'1'&x"E935",'1'&x"E936",'1'&x"E937",'1'&x"E938",'1'&x"E939",'1'&x"E93A",'1'&x"E93B",'1'&x"E93C",'1'&x"E93D",'1'&x"E93E",'1'&x"E93F",
+--'1'&x"E940",'1'&x"E941",'1'&x"E942",'1'&x"E943",'1'&x"E944",'1'&x"E945",'1'&x"E946",'1'&x"E947",'1'&x"E948",'1'&x"E949",'1'&x"E94A",'1'&x"E94B",'1'&x"E94C",'1'&x"E94D",'1'&x"E94E",'1'&x"E94F",
+--'1'&x"E950",'1'&x"E951",'1'&x"E952",'1'&x"E953",'1'&x"E954",'1'&x"E955",'1'&x"E956",'1'&x"E957",'1'&x"E958",'1'&x"E959",'1'&x"E95A",'1'&x"E95B",'1'&x"E95C",'1'&x"E95D",'1'&x"E95E",'1'&x"E95F",
+--'1'&x"E960",'1'&x"E961",'1'&x"E962",'1'&x"E963",'1'&x"E964",'1'&x"E965",'1'&x"E966",'1'&x"E967",'1'&x"E968",'1'&x"E969",'1'&x"E96A",'1'&x"E96B",'1'&x"E96C",'1'&x"E96D",'1'&x"E96E",'1'&x"E96F",
+--'1'&x"E970",'1'&x"E971",'1'&x"E972",'1'&x"E973",'1'&x"E974",'1'&x"E975",'1'&x"E976",'1'&x"E977",'1'&x"E978",'1'&x"E979",'1'&x"E97A",'1'&x"E97B",'1'&x"E97C",'1'&x"E97D",'1'&x"E97E",'1'&x"E97F",
+--'1'&x"E980",'1'&x"E981",'1'&x"E982",'1'&x"E983",'1'&x"E984",'1'&x"E985",'1'&x"E986",'1'&x"E987",'1'&x"E988",'1'&x"E989",'1'&x"E98A",'1'&x"E98B",'1'&x"E98C",'1'&x"E98D",'1'&x"E98E",'1'&x"E98F",
+--'1'&x"E990",'1'&x"E991",'1'&x"E992",'1'&x"E993",'1'&x"E994",'1'&x"E995",'1'&x"E996",'1'&x"E997",'1'&x"E998",'1'&x"E999",'1'&x"E99A",'1'&x"E99B",'1'&x"E99C",'1'&x"E99D",'1'&x"E99E",'1'&x"E99F",
+--'1'&x"E9A0",'1'&x"E9A1",'1'&x"E9A2",'1'&x"E9A3",'1'&x"E9A4",'1'&x"E9A5",'1'&x"E9A6",'1'&x"E9A7",'1'&x"E9A8",'1'&x"E9A9",'1'&x"E9AA",'1'&x"E9AB",'1'&x"E9AC",'1'&x"E9AD",'1'&x"E9AE",'1'&x"E9AF",
+--'1'&x"E9B0",'1'&x"E9B1",'1'&x"E9B2",'1'&x"E9B3",'1'&x"E9B4",'1'&x"E9B5",'1'&x"E9B6",'1'&x"E9B7",'1'&x"E9B8",'1'&x"E9B9",'1'&x"E9BA",'1'&x"E9BB",'1'&x"E9BC",'1'&x"E9BD",'1'&x"E9BE",'1'&x"E9BF",
+--'1'&x"E9C0",'1'&x"E9C1",'1'&x"E9C2",'1'&x"E9C3",'1'&x"E9C4",'1'&x"E9C5",'1'&x"E9C6",'1'&x"E9C7",'1'&x"E9C8",'1'&x"E9C9",'1'&x"E9CA",'1'&x"E9CB",'1'&x"E9CC",'1'&x"E9CD",'1'&x"E9CE",'1'&x"E9CF",
+--'1'&x"E9D0",'1'&x"E9D1",'1'&x"E9D2",'1'&x"E9D3",'1'&x"E9D4",'1'&x"E9D5",'1'&x"E9D6",'1'&x"E9D7",'1'&x"E9D8",'1'&x"E9D9",'1'&x"E9DA",'1'&x"E9DB",'1'&x"E9DC",'1'&x"E9DD",'1'&x"E9DE",'1'&x"E9DF",
+--'1'&x"E9E0",'1'&x"E9E1",'1'&x"E9E2",'1'&x"E9E3",'1'&x"E9E4",'1'&x"E9E5",'1'&x"E9E6",'1'&x"E9E7",'1'&x"E9E8",'1'&x"E9E9",'1'&x"E9EA",'1'&x"E9EB",'1'&x"E9EC",'1'&x"E9ED",'1'&x"E9EE",'1'&x"E9EF",
+--'1'&x"E9F0",'1'&x"E9F1",'1'&x"E9F2",'1'&x"E9F3",'1'&x"E9F4",'1'&x"E9F5",'1'&x"E9F6",'1'&x"E9F7",'1'&x"E9F8",'1'&x"E9F9",'1'&x"E9FA",'1'&x"E9FB",'1'&x"E9FC",'1'&x"E9FD",'1'&x"E9FE",'1'&x"E9FF",
+--'1'&x"EA00",'1'&x"EA01",'1'&x"EA02",'1'&x"EA03",'1'&x"EA04",'1'&x"EA05",'1'&x"EA06",'1'&x"EA07",'1'&x"EA08",'1'&x"EA09",'1'&x"EA0A",'1'&x"EA0B",'1'&x"EA0C",'1'&x"EA0D",'1'&x"EA0E",'1'&x"EA0F",
+--'1'&x"EA10",'1'&x"EA11",'1'&x"EA12",'1'&x"EA13",'1'&x"EA14",'1'&x"EA15",'1'&x"EA16",'1'&x"EA17",'1'&x"EA18",'1'&x"EA19",'1'&x"EA1A",'1'&x"EA1B",'1'&x"EA1C",'1'&x"EA1D",'1'&x"EA1E",'1'&x"EA1F",
+--'1'&x"EA20",'1'&x"EA21",'1'&x"EA22",'1'&x"EA23",'1'&x"EA24",'1'&x"EA25",'1'&x"EA26",'1'&x"EA27",'1'&x"EA28",'1'&x"EA29",'1'&x"EA2A",'1'&x"EA2B",'1'&x"EA2C",'1'&x"EA2D",'1'&x"EA2E",'1'&x"EA2F",
+--'1'&x"EA30",'1'&x"EA31",'1'&x"EA32",'1'&x"EA33",'1'&x"EA34",'1'&x"EA35",'1'&x"EA36",'1'&x"EA37",'1'&x"EA38",'1'&x"EA39",'1'&x"EA3A",'1'&x"EA3B",'1'&x"EA3C",'1'&x"EA3D",'1'&x"EA3E",'1'&x"EA3F",
+--'1'&x"EA40",'1'&x"EA41",'1'&x"EA42",'1'&x"EA43",'1'&x"EA44",'1'&x"EA45",'1'&x"EA46",'1'&x"EA47",'1'&x"EA48",'1'&x"EA49",'1'&x"EA4A",'1'&x"EA4B",'1'&x"EA4C",'1'&x"EA4D",'1'&x"EA4E",'1'&x"EA4F",
+--'1'&x"EA50",'1'&x"EA51",'1'&x"EA52",'1'&x"EA53",'1'&x"EA54",'1'&x"EA55",'1'&x"EA56",'1'&x"EA57",'1'&x"EA58",'1'&x"EA59",'1'&x"EA5A",'1'&x"EA5B",'1'&x"EA5C",'1'&x"EA5D",'1'&x"EA5E",'1'&x"EA5F",
+--'1'&x"EA60",'1'&x"EA61",'1'&x"EA62",'1'&x"EA63",'1'&x"EA64",'1'&x"EA65",'1'&x"EA66",'1'&x"EA67",'1'&x"EA68",'1'&x"EA69",'1'&x"EA6A",'1'&x"EA6B",'1'&x"EA6C",'1'&x"EA6D",'1'&x"EA6E",'1'&x"EA6F",
+--'1'&x"EA70",'1'&x"EA71",'1'&x"EA72",'1'&x"EA73",'1'&x"EA74",'1'&x"EA75",'1'&x"EA76",'1'&x"EA77",'1'&x"EA78",'1'&x"EA79",'1'&x"EA7A",'1'&x"EA7B",'1'&x"EA7C",'1'&x"EA7D",'1'&x"EA7E",'1'&x"EA7F",
+--'1'&x"EA80",'1'&x"EA81",'1'&x"EA82",'1'&x"EA83",'1'&x"EA84",'1'&x"EA85",'1'&x"EA86",'1'&x"EA87",'1'&x"EA88",'1'&x"EA89",'1'&x"EA8A",'1'&x"EA8B",'1'&x"EA8C",'1'&x"EA8D",'1'&x"EA8E",'1'&x"EA8F",
+--'1'&x"EA90",'1'&x"EA91",'1'&x"EA92",'1'&x"EA93",'1'&x"EA94",'1'&x"EA95",'1'&x"EA96",'1'&x"EA97",'1'&x"EA98",'1'&x"EA99",'1'&x"EA9A",'1'&x"EA9B",'1'&x"EA9C",'1'&x"EA9D",'1'&x"EA9E",'1'&x"EA9F",
+--'1'&x"EAA0",'1'&x"EAA1",'1'&x"EAA2",'1'&x"EAA3",'1'&x"EAA4",'1'&x"EAA5",'1'&x"EAA6",'1'&x"EAA7",'1'&x"EAA8",'1'&x"EAA9",'1'&x"EAAA",'1'&x"EAAB",'1'&x"EAAC",'1'&x"EAAD",'1'&x"EAAE",'1'&x"EAAF",
+--'1'&x"EAB0",'1'&x"EAB1",'1'&x"EAB2",'1'&x"EAB3",'1'&x"EAB4",'1'&x"EAB5",'1'&x"EAB6",'1'&x"EAB7",'1'&x"EAB8",'1'&x"EAB9",'1'&x"EABA",'1'&x"EABB",'1'&x"EABC",'1'&x"EABD",'1'&x"EABE",'1'&x"EABF",
+--'1'&x"EAC0",'1'&x"EAC1",'1'&x"EAC2",'1'&x"EAC3",'1'&x"EAC4",'1'&x"EAC5",'1'&x"EAC6",'1'&x"EAC7",'1'&x"EAC8",'1'&x"EAC9",'1'&x"EACA",'1'&x"EACB",'1'&x"EACC",'1'&x"EACD",'1'&x"EACE",'1'&x"EACF",
+--'1'&x"EAD0",'1'&x"EAD1",'1'&x"EAD2",'1'&x"EAD3",'1'&x"EAD4",'1'&x"EAD5",'1'&x"EAD6",'1'&x"EAD7",'1'&x"EAD8",'1'&x"EAD9",'1'&x"EADA",'1'&x"EADB",'1'&x"EADC",'1'&x"EADD",'1'&x"EADE",'1'&x"EADF",
+--'1'&x"EAE0",'1'&x"EAE1",'1'&x"EAE2",'1'&x"EAE3",'1'&x"EAE4",'1'&x"EAE5",'1'&x"EAE6",'1'&x"EAE7",'1'&x"EAE8",'1'&x"EAE9",'1'&x"EAEA",'1'&x"EAEB",'1'&x"EAEC",'1'&x"EAED",'1'&x"EAEE",'1'&x"EAEF",
+--'1'&x"EAF0",'1'&x"EAF1",'1'&x"EAF2",'1'&x"EAF3",'1'&x"EAF4",'1'&x"EAF5",'1'&x"EAF6",'1'&x"EAF7",'1'&x"EAF8",'1'&x"EAF9",'1'&x"EAFA",'1'&x"EAFB",'1'&x"EAFC",'1'&x"EAFD",'1'&x"EAFE",'1'&x"EAFF",
+--'1'&x"EB00",'1'&x"EB01",'1'&x"EB02",'1'&x"EB03",'1'&x"EB04",'1'&x"EB05",'1'&x"EB06",'1'&x"EB07",'1'&x"EB08",'1'&x"EB09",'1'&x"EB0A",'1'&x"EB0B",'1'&x"EB0C",'1'&x"EB0D",'1'&x"EB0E",'1'&x"EB0F",
+--'1'&x"EB10",'1'&x"EB11",'1'&x"EB12",'1'&x"EB13",'1'&x"EB14",'1'&x"EB15",'1'&x"EB16",'1'&x"EB17",'1'&x"EB18",'1'&x"EB19",'1'&x"EB1A",'1'&x"EB1B",'1'&x"EB1C",'1'&x"EB1D",'1'&x"EB1E",'1'&x"EB1F",
+--'1'&x"EB20",'1'&x"EB21",'1'&x"EB22",'1'&x"EB23",'1'&x"EB24",'1'&x"EB25",'1'&x"EB26",'1'&x"EB27",'1'&x"EB28",'1'&x"EB29",'1'&x"EB2A",'1'&x"EB2B",'1'&x"EB2C",'1'&x"EB2D",'1'&x"EB2E",'1'&x"EB2F",
+--'1'&x"EB30",'1'&x"EB31",'1'&x"EB32",'1'&x"EB33",'1'&x"EB34",'1'&x"EB35",'1'&x"EB36",'1'&x"EB37",'1'&x"EB38",'1'&x"EB39",'1'&x"EB3A",'1'&x"EB3B",'1'&x"EB3C",'1'&x"EB3D",'1'&x"EB3E",'1'&x"EB3F",
+--'1'&x"EB40",'1'&x"EB41",'1'&x"EB42",'1'&x"EB43",'1'&x"EB44",'1'&x"EB45",'1'&x"EB46",'1'&x"EB47",'1'&x"EB48",'1'&x"EB49",'1'&x"EB4A",'1'&x"EB4B",'1'&x"EB4C",'1'&x"EB4D",'1'&x"EB4E",'1'&x"EB4F",
+--'1'&x"EB50",'1'&x"EB51",'1'&x"EB52",'1'&x"EB53",'1'&x"EB54",'1'&x"EB55",'1'&x"EB56",'1'&x"EB57",'1'&x"EB58",'1'&x"EB59",'1'&x"EB5A",'1'&x"EB5B",'1'&x"EB5C",'1'&x"EB5D",'1'&x"EB5E",'1'&x"EB5F",
+--'1'&x"EB60",'1'&x"EB61",'1'&x"EB62",'1'&x"EB63",'1'&x"EB64",'1'&x"EB65",'1'&x"EB66",'1'&x"EB67",'1'&x"EB68",'1'&x"EB69",'1'&x"EB6A",'1'&x"EB6B",'1'&x"EB6C",'1'&x"EB6D",'1'&x"EB6E",'1'&x"EB6F",
+--'1'&x"EB70",'1'&x"EB71",'1'&x"EB72",'1'&x"EB73",'1'&x"EB74",'1'&x"EB75",'1'&x"EB76",'1'&x"EB77",'1'&x"EB78",'1'&x"EB79",'1'&x"EB7A",'1'&x"EB7B",'1'&x"EB7C",'1'&x"EB7D",'1'&x"EB7E",'1'&x"EB7F",
+--'1'&x"EB80",'1'&x"EB81",'1'&x"EB82",'1'&x"EB83",'1'&x"EB84",'1'&x"EB85",'1'&x"EB86",'1'&x"EB87",'1'&x"EB88",'1'&x"EB89",'1'&x"EB8A",'1'&x"EB8B",'1'&x"EB8C",'1'&x"EB8D",'1'&x"EB8E",'1'&x"EB8F",
+--'1'&x"EB90",'1'&x"EB91",'1'&x"EB92",'1'&x"EB93",'1'&x"EB94",'1'&x"EB95",'1'&x"EB96",'1'&x"EB97",'1'&x"EB98",'1'&x"EB99",'1'&x"EB9A",'1'&x"EB9B",'1'&x"EB9C",'1'&x"EB9D",'1'&x"EB9E",'1'&x"EB9F",
+--'1'&x"EBA0",'1'&x"EBA1",'1'&x"EBA2",'1'&x"EBA3",'1'&x"EBA4",'1'&x"EBA5",'1'&x"EBA6",'1'&x"EBA7",'1'&x"EBA8",'1'&x"EBA9",'1'&x"EBAA",'1'&x"EBAB",'1'&x"EBAC",'1'&x"EBAD",'1'&x"EBAE",'1'&x"EBAF",
+--'1'&x"EBB0",'1'&x"EBB1",'1'&x"EBB2",'1'&x"EBB3",'1'&x"EBB4",'1'&x"EBB5",'1'&x"EBB6",'1'&x"EBB7",'1'&x"EBB8",'1'&x"EBB9",'1'&x"EBBA",'1'&x"EBBB",'1'&x"EBBC",'1'&x"EBBD",'1'&x"EBBE",'1'&x"EBBF",
+--'1'&x"EBC0",'1'&x"EBC1",'1'&x"EBC2",'1'&x"EBC3",'1'&x"EBC4",'1'&x"EBC5",'1'&x"EBC6",'1'&x"EBC7",'1'&x"EBC8",'1'&x"EBC9",'1'&x"EBCA",'1'&x"EBCB",'1'&x"EBCC",'1'&x"EBCD",'1'&x"EBCE",'1'&x"EBCF",
+--'1'&x"EBD0",'1'&x"EBD1",'1'&x"EBD2",'1'&x"EBD3",'1'&x"EBD4",'1'&x"EBD5",'1'&x"EBD6",'1'&x"EBD7",'1'&x"EBD8",'1'&x"EBD9",'1'&x"EBDA",'1'&x"EBDB",'1'&x"EBDC",'1'&x"EBDD",'1'&x"EBDE",'1'&x"EBDF",
+--'1'&x"EBE0",'1'&x"EBE1",'1'&x"EBE2",'1'&x"EBE3",'1'&x"EBE4",'1'&x"EBE5",'1'&x"EBE6",'1'&x"EBE7",'1'&x"EBE8",'1'&x"EBE9",'1'&x"EBEA",'1'&x"EBEB",'1'&x"EBEC",'1'&x"EBED",'1'&x"EBEE",'1'&x"EBEF",
+--'1'&x"EBF0",'1'&x"EBF1",'1'&x"EBF2",'1'&x"EBF3",'1'&x"EBF4",'1'&x"EBF5",'1'&x"EBF6",'1'&x"EBF7",'1'&x"EBF8",'1'&x"EBF9",'1'&x"EBFA",'1'&x"EBFB",'1'&x"EBFC",'1'&x"EBFD",'1'&x"EBFE",'1'&x"EBFF",
+--'1'&x"EC00",'1'&x"EC01",'1'&x"EC02",'1'&x"EC03",'1'&x"EC04",'1'&x"EC05",'1'&x"EC06",'1'&x"EC07",'1'&x"EC08",'1'&x"EC09",'1'&x"EC0A",'1'&x"EC0B",'1'&x"EC0C",'1'&x"EC0D",'1'&x"EC0E",'1'&x"EC0F",
+--'1'&x"EC10",'1'&x"EC11",'1'&x"EC12",'1'&x"EC13",'1'&x"EC14",'1'&x"EC15",'1'&x"EC16",'1'&x"EC17",'1'&x"EC18",'1'&x"EC19",'1'&x"EC1A",'1'&x"EC1B",'1'&x"EC1C",'1'&x"EC1D",'1'&x"EC1E",'1'&x"EC1F",
+--'1'&x"EC20",'1'&x"EC21",'1'&x"EC22",'1'&x"EC23",'1'&x"EC24",'1'&x"EC25",'1'&x"EC26",'1'&x"EC27",'1'&x"EC28",'1'&x"EC29",'1'&x"EC2A",'1'&x"EC2B",'1'&x"EC2C",'1'&x"EC2D",'1'&x"EC2E",'1'&x"EC2F",
+--'1'&x"EC30",'1'&x"EC31",'1'&x"EC32",'1'&x"EC33",'1'&x"EC34",'1'&x"EC35",'1'&x"EC36",'1'&x"EC37",'1'&x"EC38",'1'&x"EC39",'1'&x"EC3A",'1'&x"EC3B",'1'&x"EC3C",'1'&x"EC3D",'1'&x"EC3E",'1'&x"EC3F",
+--'1'&x"EC40",'1'&x"EC41",'1'&x"EC42",'1'&x"EC43",'1'&x"EC44",'1'&x"EC45",'1'&x"EC46",'1'&x"EC47",'1'&x"EC48",'1'&x"EC49",'1'&x"EC4A",'1'&x"EC4B",'1'&x"EC4C",'1'&x"EC4D",'1'&x"EC4E",'1'&x"EC4F",
+--'1'&x"EC50",'1'&x"EC51",'1'&x"EC52",'1'&x"EC53",'1'&x"EC54",'1'&x"EC55",'1'&x"EC56",'1'&x"EC57",'1'&x"EC58",'1'&x"EC59",'1'&x"EC5A",'1'&x"EC5B",'1'&x"EC5C",'1'&x"EC5D",'1'&x"EC5E",'1'&x"EC5F",
+--'1'&x"EC60",'1'&x"EC61",'1'&x"EC62",'1'&x"EC63",'1'&x"EC64",'1'&x"EC65",'1'&x"EC66",'1'&x"EC67",'1'&x"EC68",'1'&x"EC69",'1'&x"EC6A",'1'&x"EC6B",'1'&x"EC6C",'1'&x"EC6D",'1'&x"EC6E",'1'&x"EC6F",
+--'1'&x"EC70",'1'&x"EC71",'1'&x"EC72",'1'&x"EC73",'1'&x"EC74",'1'&x"EC75",'1'&x"EC76",'1'&x"EC77",'1'&x"EC78",'1'&x"EC79",'1'&x"EC7A",'1'&x"EC7B",'1'&x"EC7C",'1'&x"EC7D",'1'&x"EC7E",'1'&x"EC7F",
+--'1'&x"EC80",'1'&x"EC81",'1'&x"EC82",'1'&x"EC83",'1'&x"EC84",'1'&x"EC85",'1'&x"EC86",'1'&x"EC87",'1'&x"EC88",'1'&x"EC89",'1'&x"EC8A",'1'&x"EC8B",'1'&x"EC8C",'1'&x"EC8D",'1'&x"EC8E",'1'&x"EC8F",
+--'1'&x"EC90",'1'&x"EC91",'1'&x"EC92",'1'&x"EC93",'1'&x"EC94",'1'&x"EC95",'1'&x"EC96",'1'&x"EC97",'1'&x"EC98",'1'&x"EC99",'1'&x"EC9A",'1'&x"EC9B",'1'&x"EC9C",'1'&x"EC9D",'1'&x"EC9E",'1'&x"EC9F",
+--'1'&x"ECA0",'1'&x"ECA1",'1'&x"ECA2",'1'&x"ECA3",'1'&x"ECA4",'1'&x"ECA5",'1'&x"ECA6",'1'&x"ECA7",'1'&x"ECA8",'1'&x"ECA9",'1'&x"ECAA",'1'&x"ECAB",'1'&x"ECAC",'1'&x"ECAD",'1'&x"ECAE",'1'&x"ECAF",
+--'1'&x"ECB0",'1'&x"ECB1",'1'&x"ECB2",'1'&x"ECB3",'1'&x"ECB4",'1'&x"ECB5",'1'&x"ECB6",'1'&x"ECB7",'1'&x"ECB8",'1'&x"ECB9",'1'&x"ECBA",'1'&x"ECBB",'1'&x"ECBC",'1'&x"ECBD",'1'&x"ECBE",'1'&x"ECBF",
+--'1'&x"ECC0",'1'&x"ECC1",'1'&x"ECC2",'1'&x"ECC3",'1'&x"ECC4",'1'&x"ECC5",'1'&x"ECC6",'1'&x"ECC7",'1'&x"ECC8",'1'&x"ECC9",'1'&x"ECCA",'1'&x"ECCB",'1'&x"ECCC",'1'&x"ECCD",'1'&x"ECCE",'1'&x"ECCF",
+--'1'&x"ECD0",'1'&x"ECD1",'1'&x"ECD2",'1'&x"ECD3",'1'&x"ECD4",'1'&x"ECD5",'1'&x"ECD6",'1'&x"ECD7",'1'&x"ECD8",'1'&x"ECD9",'1'&x"ECDA",'1'&x"ECDB",'1'&x"ECDC",'1'&x"ECDD",'1'&x"ECDE",'1'&x"ECDF",
+--'1'&x"ECE0",'1'&x"ECE1",'1'&x"ECE2",'1'&x"ECE3",'1'&x"ECE4",'1'&x"ECE5",'1'&x"ECE6",'1'&x"ECE7",'1'&x"ECE8",'1'&x"ECE9",'1'&x"ECEA",'1'&x"ECEB",'1'&x"ECEC",'1'&x"ECED",'1'&x"ECEE",'1'&x"ECEF",
+--'1'&x"ECF0",'1'&x"ECF1",'1'&x"ECF2",'1'&x"ECF3",'1'&x"ECF4",'1'&x"ECF5",'1'&x"ECF6",'1'&x"ECF7",'1'&x"ECF8",'1'&x"ECF9",'1'&x"ECFA",'1'&x"ECFB",'1'&x"ECFC",'1'&x"ECFD",'1'&x"ECFE",'1'&x"ECFF",
+--'1'&x"ED00",'1'&x"ED01",'1'&x"ED02",'1'&x"ED03",'1'&x"ED04",'1'&x"ED05",'1'&x"ED06",'1'&x"ED07",'1'&x"ED08",'1'&x"ED09",'1'&x"ED0A",'1'&x"ED0B",'1'&x"ED0C",'1'&x"ED0D",'1'&x"ED0E",'1'&x"ED0F",
+--'1'&x"ED10",'1'&x"ED11",'1'&x"ED12",'1'&x"ED13",'1'&x"ED14",'1'&x"ED15",'1'&x"ED16",'1'&x"ED17",'1'&x"ED18",'1'&x"ED19",'1'&x"ED1A",'1'&x"ED1B",'1'&x"ED1C",'1'&x"ED1D",'1'&x"ED1E",'1'&x"ED1F",
+--'1'&x"ED20",'1'&x"ED21",'1'&x"ED22",'1'&x"ED23",'1'&x"ED24",'1'&x"ED25",'1'&x"ED26",'1'&x"ED27",'1'&x"ED28",'1'&x"ED29",'1'&x"ED2A",'1'&x"ED2B",'1'&x"ED2C",'1'&x"ED2D",'1'&x"ED2E",'1'&x"ED2F",
+--'1'&x"ED30",'1'&x"ED31",'1'&x"ED32",'1'&x"ED33",'1'&x"ED34",'1'&x"ED35",'1'&x"ED36",'1'&x"ED37",'1'&x"ED38",'1'&x"ED39",'1'&x"ED3A",'1'&x"ED3B",'1'&x"ED3C",'1'&x"ED3D",'1'&x"ED3E",'1'&x"ED3F",
+--'1'&x"ED40",'1'&x"ED41",'1'&x"ED42",'1'&x"ED43",'1'&x"ED44",'1'&x"ED45",'1'&x"ED46",'1'&x"ED47",'1'&x"ED48",'1'&x"ED49",'1'&x"ED4A",'1'&x"ED4B",'1'&x"ED4C",'1'&x"ED4D",'1'&x"ED4E",'1'&x"ED4F",
+--'1'&x"ED50",'1'&x"ED51",'1'&x"ED52",'1'&x"ED53",'1'&x"ED54",'1'&x"ED55",'1'&x"ED56",'1'&x"ED57",'1'&x"ED58",'1'&x"ED59",'1'&x"ED5A",'1'&x"ED5B",'1'&x"ED5C",'1'&x"ED5D",'1'&x"ED5E",'1'&x"ED5F",
+--'1'&x"ED60",'1'&x"ED61",'1'&x"ED62",'1'&x"ED63",'1'&x"ED64",'1'&x"ED65",'1'&x"ED66",'1'&x"ED67",'1'&x"ED68",'1'&x"ED69",'1'&x"ED6A",'1'&x"ED6B",'1'&x"ED6C",'1'&x"ED6D",'1'&x"ED6E",'1'&x"ED6F",
+--'1'&x"ED70",'1'&x"ED71",'1'&x"ED72",'1'&x"ED73",'1'&x"ED74",'1'&x"ED75",'1'&x"ED76",'1'&x"ED77",'1'&x"ED78",'1'&x"ED79",'1'&x"ED7A",'1'&x"ED7B",'1'&x"ED7C",'1'&x"ED7D",'1'&x"ED7E",'1'&x"ED7F",
+--'1'&x"ED80",'1'&x"ED81",'1'&x"ED82",'1'&x"ED83",'1'&x"ED84",'1'&x"ED85",'1'&x"ED86",'1'&x"ED87",'1'&x"ED88",'1'&x"ED89",'1'&x"ED8A",'1'&x"ED8B",'1'&x"ED8C",'1'&x"ED8D",'1'&x"ED8E",'1'&x"ED8F",
+--'1'&x"ED90",'1'&x"ED91",'1'&x"ED92",'1'&x"ED93",'1'&x"ED94",'1'&x"ED95",'1'&x"ED96",'1'&x"ED97",'1'&x"ED98",'1'&x"ED99",'1'&x"ED9A",'1'&x"ED9B",'1'&x"ED9C",'1'&x"ED9D",'1'&x"ED9E",'1'&x"ED9F",
+--'1'&x"EDA0",'1'&x"EDA1",'1'&x"EDA2",'1'&x"EDA3",'1'&x"EDA4",'1'&x"EDA5",'1'&x"EDA6",'1'&x"EDA7",'1'&x"EDA8",'1'&x"EDA9",'1'&x"EDAA",'1'&x"EDAB",'1'&x"EDAC",'1'&x"EDAD",'1'&x"EDAE",'1'&x"EDAF",
+--'1'&x"EDB0",'1'&x"EDB1",'1'&x"EDB2",'1'&x"EDB3",'1'&x"EDB4",'1'&x"EDB5",'1'&x"EDB6",'1'&x"EDB7",'1'&x"EDB8",'1'&x"EDB9",'1'&x"EDBA",'1'&x"EDBB",'1'&x"EDBC",'1'&x"EDBD",'1'&x"EDBE",'1'&x"EDBF",
+--'1'&x"EDC0",'1'&x"EDC1",'1'&x"EDC2",'1'&x"EDC3",'1'&x"EDC4",'1'&x"EDC5",'1'&x"EDC6",'1'&x"EDC7",'1'&x"EDC8",'1'&x"EDC9",'1'&x"EDCA",'1'&x"EDCB",'1'&x"EDCC",'1'&x"EDCD",'1'&x"EDCE",'1'&x"EDCF",
+--'1'&x"EDD0",'1'&x"EDD1",'1'&x"EDD2",'1'&x"EDD3",'1'&x"EDD4",'1'&x"EDD5",'1'&x"EDD6",'1'&x"EDD7",'1'&x"EDD8",'1'&x"EDD9",'1'&x"EDDA",'1'&x"EDDB",'1'&x"EDDC",'1'&x"EDDD",'1'&x"EDDE",'1'&x"EDDF",
+--'1'&x"EDE0",'1'&x"EDE1",'1'&x"EDE2",'1'&x"EDE3",'1'&x"EDE4",'1'&x"EDE5",'1'&x"EDE6",'1'&x"EDE7",'1'&x"EDE8",'1'&x"EDE9",'1'&x"EDEA",'1'&x"EDEB",'1'&x"EDEC",'1'&x"EDED",'1'&x"EDEE",'1'&x"EDEF",
+--'1'&x"EDF0",'1'&x"EDF1",'1'&x"EDF2",'1'&x"EDF3",'1'&x"EDF4",'1'&x"EDF5",'1'&x"EDF6",'1'&x"EDF7",'1'&x"EDF8",'1'&x"EDF9",'1'&x"EDFA",'1'&x"EDFB",'1'&x"EDFC",'1'&x"EDFD",'1'&x"EDFE",'1'&x"EDFF",
+--'1'&x"EE00",'1'&x"EE01",'1'&x"EE02",'1'&x"EE03",'1'&x"EE04",'1'&x"EE05",'1'&x"EE06",'1'&x"EE07",'1'&x"EE08",'1'&x"EE09",'1'&x"EE0A",'1'&x"EE0B",'1'&x"EE0C",'1'&x"EE0D",'1'&x"EE0E",'1'&x"EE0F",
+--'1'&x"EE10",'1'&x"EE11",'1'&x"EE12",'1'&x"EE13",'1'&x"EE14",'1'&x"EE15",'1'&x"EE16",'1'&x"EE17",'1'&x"EE18",'1'&x"EE19",'1'&x"EE1A",'1'&x"EE1B",'1'&x"EE1C",'1'&x"EE1D",'1'&x"EE1E",'1'&x"EE1F",
+--'1'&x"EE20",'1'&x"EE21",'1'&x"EE22",'1'&x"EE23",'1'&x"EE24",'1'&x"EE25",'1'&x"EE26",'1'&x"EE27",'1'&x"EE28",'1'&x"EE29",'1'&x"EE2A",'1'&x"EE2B",'1'&x"EE2C",'1'&x"EE2D",'1'&x"EE2E",'1'&x"EE2F",
+--'1'&x"EE30",'1'&x"EE31",'1'&x"EE32",'1'&x"EE33",'1'&x"EE34",'1'&x"EE35",'1'&x"EE36",'1'&x"EE37",'1'&x"EE38",'1'&x"EE39",'1'&x"EE3A",'1'&x"EE3B",'1'&x"EE3C",'1'&x"EE3D",'1'&x"EE3E",'1'&x"EE3F",
+--'1'&x"EE40",'1'&x"EE41",'1'&x"EE42",'1'&x"EE43",'1'&x"EE44",'1'&x"EE45",'1'&x"EE46",'1'&x"EE47",'1'&x"EE48",'1'&x"EE49",'1'&x"EE4A",'1'&x"EE4B",'1'&x"EE4C",'1'&x"EE4D",'1'&x"EE4E",'1'&x"EE4F",
+--'1'&x"EE50",'1'&x"EE51",'1'&x"EE52",'1'&x"EE53",'1'&x"EE54",'1'&x"EE55",'1'&x"EE56",'1'&x"EE57",'1'&x"EE58",'1'&x"EE59",'1'&x"EE5A",'1'&x"EE5B",'1'&x"EE5C",'1'&x"EE5D",'1'&x"EE5E",'1'&x"EE5F",
+--'1'&x"EE60",'1'&x"EE61",'1'&x"EE62",'1'&x"EE63",'1'&x"EE64",'1'&x"EE65",'1'&x"EE66",'1'&x"EE67",'1'&x"EE68",'1'&x"EE69",'1'&x"EE6A",'1'&x"EE6B",'1'&x"EE6C",'1'&x"EE6D",'1'&x"EE6E",'1'&x"EE6F",
+--'1'&x"EE70",'1'&x"EE71",'1'&x"EE72",'1'&x"EE73",'1'&x"EE74",'1'&x"EE75",'1'&x"EE76",'1'&x"EE77",'1'&x"EE78",'1'&x"EE79",'1'&x"EE7A",'1'&x"EE7B",'1'&x"EE7C",'1'&x"EE7D",'1'&x"EE7E",'1'&x"EE7F",
+--'1'&x"EE80",'1'&x"EE81",'1'&x"EE82",'1'&x"EE83",'1'&x"EE84",'1'&x"EE85",'1'&x"EE86",'1'&x"EE87",'1'&x"EE88",'1'&x"EE89",'1'&x"EE8A",'1'&x"EE8B",'1'&x"EE8C",'1'&x"EE8D",'1'&x"EE8E",'1'&x"EE8F",
+--'1'&x"EE90",'1'&x"EE91",'1'&x"EE92",'1'&x"EE93",'1'&x"EE94",'1'&x"EE95",'1'&x"EE96",'1'&x"EE97",'1'&x"EE98",'1'&x"EE99",'1'&x"EE9A",'1'&x"EE9B",'1'&x"EE9C",'1'&x"EE9D",'1'&x"EE9E",'1'&x"EE9F",
+--'1'&x"EEA0",'1'&x"EEA1",'1'&x"EEA2",'1'&x"EEA3",'1'&x"EEA4",'1'&x"EEA5",'1'&x"EEA6",'1'&x"EEA7",'1'&x"EEA8",'1'&x"EEA9",'1'&x"EEAA",'1'&x"EEAB",'1'&x"EEAC",'1'&x"EEAD",'1'&x"EEAE",'1'&x"EEAF",
+--'1'&x"EEB0",'1'&x"EEB1",'1'&x"EEB2",'1'&x"EEB3",'1'&x"EEB4",'1'&x"EEB5",'1'&x"EEB6",'1'&x"EEB7",'1'&x"EEB8",'1'&x"EEB9",'1'&x"EEBA",'1'&x"EEBB",'1'&x"EEBC",'1'&x"EEBD",'1'&x"EEBE",'1'&x"EEBF",
+--'1'&x"EEC0",'1'&x"EEC1",'1'&x"EEC2",'1'&x"EEC3",'1'&x"EEC4",'1'&x"EEC5",'1'&x"EEC6",'1'&x"EEC7",'1'&x"EEC8",'1'&x"EEC9",'1'&x"EECA",'1'&x"EECB",'1'&x"EECC",'1'&x"EECD",'1'&x"EECE",'1'&x"EECF",
+--'1'&x"EED0",'1'&x"EED1",'1'&x"EED2",'1'&x"EED3",'1'&x"EED4",'1'&x"EED5",'1'&x"EED6",'1'&x"EED7",'1'&x"EED8",'1'&x"EED9",'1'&x"EEDA",'1'&x"EEDB",'1'&x"EEDC",'1'&x"EEDD",'1'&x"EEDE",'1'&x"EEDF",
+--'1'&x"EEE0",'1'&x"EEE1",'1'&x"EEE2",'1'&x"EEE3",'1'&x"EEE4",'1'&x"EEE5",'1'&x"EEE6",'1'&x"EEE7",'1'&x"EEE8",'1'&x"EEE9",'1'&x"EEEA",'1'&x"EEEB",'1'&x"EEEC",'1'&x"EEED",'1'&x"EEEE",'1'&x"EEEF",
+--'1'&x"EEF0",'1'&x"EEF1",'1'&x"EEF2",'1'&x"EEF3",'1'&x"EEF4",'1'&x"EEF5",'1'&x"EEF6",'1'&x"EEF7",'1'&x"EEF8",'1'&x"EEF9",'1'&x"EEFA",'1'&x"EEFB",'1'&x"EEFC",'1'&x"EEFD",'1'&x"EEFE",'1'&x"EEFF",
+--'1'&x"EF00",'1'&x"EF01",'1'&x"EF02",'1'&x"EF03",'1'&x"EF04",'1'&x"EF05",'1'&x"EF06",'1'&x"EF07",'1'&x"EF08",'1'&x"EF09",'1'&x"EF0A",'1'&x"EF0B",'1'&x"EF0C",'1'&x"EF0D",'1'&x"EF0E",'1'&x"EF0F",
+--'1'&x"EF10",'1'&x"EF11",'1'&x"EF12",'1'&x"EF13",'1'&x"EF14",'1'&x"EF15",'1'&x"EF16",'1'&x"EF17",'1'&x"EF18",'1'&x"EF19",'1'&x"EF1A",'1'&x"EF1B",'1'&x"EF1C",'1'&x"EF1D",'1'&x"EF1E",'1'&x"EF1F",
+--'1'&x"EF20",'1'&x"EF21",'1'&x"EF22",'1'&x"EF23",'1'&x"EF24",'1'&x"EF25",'1'&x"EF26",'1'&x"EF27",'1'&x"EF28",'1'&x"EF29",'1'&x"EF2A",'1'&x"EF2B",'1'&x"EF2C",'1'&x"EF2D",'1'&x"EF2E",'1'&x"EF2F",
+--'1'&x"EF30",'1'&x"EF31",'1'&x"EF32",'1'&x"EF33",'1'&x"EF34",'1'&x"EF35",'1'&x"EF36",'1'&x"EF37",'1'&x"EF38",'1'&x"EF39",'1'&x"EF3A",'1'&x"EF3B",'1'&x"EF3C",'1'&x"EF3D",'1'&x"EF3E",'1'&x"EF3F",
+--'1'&x"EF40",'1'&x"EF41",'1'&x"EF42",'1'&x"EF43",'1'&x"EF44",'1'&x"EF45",'1'&x"EF46",'1'&x"EF47",'1'&x"EF48",'1'&x"EF49",'1'&x"EF4A",'1'&x"EF4B",'1'&x"EF4C",'1'&x"EF4D",'1'&x"EF4E",'1'&x"EF4F",
+--'1'&x"EF50",'1'&x"EF51",'1'&x"EF52",'1'&x"EF53",'1'&x"EF54",'1'&x"EF55",'1'&x"EF56",'1'&x"EF57",'1'&x"EF58",'1'&x"EF59",'1'&x"EF5A",'1'&x"EF5B",'1'&x"EF5C",'1'&x"EF5D",'1'&x"EF5E",'1'&x"EF5F",
+--'1'&x"EF60",'1'&x"EF61",'1'&x"EF62",'1'&x"EF63",'1'&x"EF64",'1'&x"EF65",'1'&x"EF66",'1'&x"EF67",'1'&x"EF68",'1'&x"EF69",'1'&x"EF6A",'1'&x"EF6B",'1'&x"EF6C",'1'&x"EF6D",'1'&x"EF6E",'1'&x"EF6F",
+--'1'&x"EF70",'1'&x"EF71",'1'&x"EF72",'1'&x"EF73",'1'&x"EF74",'1'&x"EF75",'1'&x"EF76",'1'&x"EF77",'1'&x"EF78",'1'&x"EF79",'1'&x"EF7A",'1'&x"EF7B",'1'&x"EF7C",'1'&x"EF7D",'1'&x"EF7E",'1'&x"EF7F",
+--'1'&x"EF80",'1'&x"EF81",'1'&x"EF82",'1'&x"EF83",'1'&x"EF84",'1'&x"EF85",'1'&x"EF86",'1'&x"EF87",'1'&x"EF88",'1'&x"EF89",'1'&x"EF8A",'1'&x"EF8B",'1'&x"EF8C",'1'&x"EF8D",'1'&x"EF8E",'1'&x"EF8F",
+--'1'&x"EF90",'1'&x"EF91",'1'&x"EF92",'1'&x"EF93",'1'&x"EF94",'1'&x"EF95",'1'&x"EF96",'1'&x"EF97",'1'&x"EF98",'1'&x"EF99",'1'&x"EF9A",'1'&x"EF9B",'1'&x"EF9C",'1'&x"EF9D",'1'&x"EF9E",'1'&x"EF9F",
+--'1'&x"EFA0",'1'&x"EFA1",'1'&x"EFA2",'1'&x"EFA3",'1'&x"EFA4",'1'&x"EFA5",'1'&x"EFA6",'1'&x"EFA7",'1'&x"EFA8",'1'&x"EFA9",'1'&x"EFAA",'1'&x"EFAB",'1'&x"EFAC",'1'&x"EFAD",'1'&x"EFAE",'1'&x"EFAF",
+--'1'&x"EFB0",'1'&x"EFB1",'1'&x"EFB2",'1'&x"EFB3",'1'&x"EFB4",'1'&x"EFB5",'1'&x"EFB6",'1'&x"EFB7",'1'&x"EFB8",'1'&x"EFB9",'1'&x"EFBA",'1'&x"EFBB",'1'&x"EFBC",'1'&x"EFBD",'1'&x"EFBE",'1'&x"EFBF",
+--'1'&x"EFC0",'1'&x"EFC1",'1'&x"EFC2",'1'&x"EFC3",'1'&x"EFC4",'1'&x"EFC5",'1'&x"EFC6",'1'&x"EFC7",'1'&x"EFC8",'1'&x"EFC9",'1'&x"EFCA",'1'&x"EFCB",'1'&x"EFCC",'1'&x"EFCD",'1'&x"EFCE",'1'&x"EFCF",
+--'1'&x"EFD0",'1'&x"EFD1",'1'&x"EFD2",'1'&x"EFD3",'1'&x"EFD4",'1'&x"EFD5",'1'&x"EFD6",'1'&x"EFD7",'1'&x"EFD8",'1'&x"EFD9",'1'&x"EFDA",'1'&x"EFDB",'1'&x"EFDC",'1'&x"EFDD",'1'&x"EFDE",'1'&x"EFDF",
+--'1'&x"EFE0",'1'&x"EFE1",'1'&x"EFE2",'1'&x"EFE3",'1'&x"EFE4",'1'&x"EFE5",'1'&x"EFE6",'1'&x"EFE7",'1'&x"EFE8",'1'&x"EFE9",'1'&x"EFEA",'1'&x"EFEB",'1'&x"EFEC",'1'&x"EFED",'1'&x"EFEE",'1'&x"EFEF",
+--'1'&x"EFF0",'1'&x"EFF1",'1'&x"EFF2",'1'&x"EFF3",'1'&x"EFF4",'1'&x"EFF5",'1'&x"EFF6",'1'&x"EFF7",'1'&x"EFF8",'1'&x"EFF9",'1'&x"EFFA",'1'&x"EFFB",'1'&x"EFFC",'1'&x"EFFD",'1'&x"EFFE",'1'&x"EFFF",
+--'1'&x"F000",'1'&x"F001",'1'&x"F002",'1'&x"F003",'1'&x"F004",'1'&x"F005",'1'&x"F006",'1'&x"F007",'1'&x"F008",'1'&x"F009",'1'&x"F00A",'1'&x"F00B",'1'&x"F00C",'1'&x"F00D",'1'&x"F00E",'1'&x"F00F",
+--'1'&x"F010",'1'&x"F011",'1'&x"F012",'1'&x"F013",'1'&x"F014",'1'&x"F015",'1'&x"F016",'1'&x"F017",'1'&x"F018",'1'&x"F019",'1'&x"F01A",'1'&x"F01B",'1'&x"F01C",'1'&x"F01D",'1'&x"F01E",'1'&x"F01F",
+--'1'&x"F020",'1'&x"F021",'1'&x"F022",'1'&x"F023",'1'&x"F024",'1'&x"F025",'1'&x"F026",'1'&x"F027",'1'&x"F028",'1'&x"F029",'1'&x"F02A",'1'&x"F02B",'1'&x"F02C",'1'&x"F02D",'1'&x"F02E",'1'&x"F02F",
+--'1'&x"F030",'1'&x"F031",'1'&x"F032",'1'&x"F033",'1'&x"F034",'1'&x"F035",'1'&x"F036",'1'&x"F037",'1'&x"F038",'1'&x"F039",'1'&x"F03A",'1'&x"F03B",'1'&x"F03C",'1'&x"F03D",'1'&x"F03E",'1'&x"F03F",
+--'1'&x"F040",'1'&x"F041",'1'&x"F042",'1'&x"F043",'1'&x"F044",'1'&x"F045",'1'&x"F046",'1'&x"F047",'1'&x"F048",'1'&x"F049",'1'&x"F04A",'1'&x"F04B",'1'&x"F04C",'1'&x"F04D",'1'&x"F04E",'1'&x"F04F",
+--'1'&x"F050",'1'&x"F051",'1'&x"F052",'1'&x"F053",'1'&x"F054",'1'&x"F055",'1'&x"F056",'1'&x"F057",'1'&x"F058",'1'&x"F059",'1'&x"F05A",'1'&x"F05B",'1'&x"F05C",'1'&x"F05D",'1'&x"F05E",'1'&x"F05F",
+--'1'&x"F060",'1'&x"F061",'1'&x"F062",'1'&x"F063",'1'&x"F064",'1'&x"F065",'1'&x"F066",'1'&x"F067",'1'&x"F068",'1'&x"F069",'1'&x"F06A",'1'&x"F06B",'1'&x"F06C",'1'&x"F06D",'1'&x"F06E",'1'&x"F06F",
+--'1'&x"F070",'1'&x"F071",'1'&x"F072",'1'&x"F073",'1'&x"F074",'1'&x"F075",'1'&x"F076",'1'&x"F077",'1'&x"F078",'1'&x"F079",'1'&x"F07A",'1'&x"F07B",'1'&x"F07C",'1'&x"F07D",'1'&x"F07E",'1'&x"F07F",
+--'1'&x"F080",'1'&x"F081",'1'&x"F082",'1'&x"F083",'1'&x"F084",'1'&x"F085",'1'&x"F086",'1'&x"F087",'1'&x"F088",'1'&x"F089",'1'&x"F08A",'1'&x"F08B",'1'&x"F08C",'1'&x"F08D",'1'&x"F08E",'1'&x"F08F",
+--'1'&x"F090",'1'&x"F091",'1'&x"F092",'1'&x"F093",'1'&x"F094",'1'&x"F095",'1'&x"F096",'1'&x"F097",'1'&x"F098",'1'&x"F099",'1'&x"F09A",'1'&x"F09B",'1'&x"F09C",'1'&x"F09D",'1'&x"F09E",'1'&x"F09F",
+--'1'&x"F0A0",'1'&x"F0A1",'1'&x"F0A2",'1'&x"F0A3",'1'&x"F0A4",'1'&x"F0A5",'1'&x"F0A6",'1'&x"F0A7",'1'&x"F0A8",'1'&x"F0A9",'1'&x"F0AA",'1'&x"F0AB",'1'&x"F0AC",'1'&x"F0AD",'1'&x"F0AE",'1'&x"F0AF",
+--'1'&x"F0B0",'1'&x"F0B1",'1'&x"F0B2",'1'&x"F0B3",'1'&x"F0B4",'1'&x"F0B5",'1'&x"F0B6",'1'&x"F0B7",'1'&x"F0B8",'1'&x"F0B9",'1'&x"F0BA",'1'&x"F0BB",'1'&x"F0BC",'1'&x"F0BD",'1'&x"F0BE",'1'&x"F0BF",
+--'1'&x"F0C0",'1'&x"F0C1",'1'&x"F0C2",'1'&x"F0C3",'1'&x"F0C4",'1'&x"F0C5",'1'&x"F0C6",'1'&x"F0C7",'1'&x"F0C8",'1'&x"F0C9",'1'&x"F0CA",'1'&x"F0CB",'1'&x"F0CC",'1'&x"F0CD",'1'&x"F0CE",'1'&x"F0CF",
+--'1'&x"F0D0",'1'&x"F0D1",'1'&x"F0D2",'1'&x"F0D3",'1'&x"F0D4",'1'&x"F0D5",'1'&x"F0D6",'1'&x"F0D7",'1'&x"F0D8",'1'&x"F0D9",'1'&x"F0DA",'1'&x"F0DB",'1'&x"F0DC",'1'&x"F0DD",'1'&x"F0DE",'1'&x"F0DF",
+--'1'&x"F0E0",'1'&x"F0E1",'1'&x"F0E2",'1'&x"F0E3",'1'&x"F0E4",'1'&x"F0E5",'1'&x"F0E6",'1'&x"F0E7",'1'&x"F0E8",'1'&x"F0E9",'1'&x"F0EA",'1'&x"F0EB",'1'&x"F0EC",'1'&x"F0ED",'1'&x"F0EE",'1'&x"F0EF",
+--'1'&x"F0F0",'1'&x"F0F1",'1'&x"F0F2",'1'&x"F0F3",'1'&x"F0F4",'1'&x"F0F5",'1'&x"F0F6",'1'&x"F0F7",'1'&x"F0F8",'1'&x"F0F9",'1'&x"F0FA",'1'&x"F0FB",'1'&x"F0FC",'1'&x"F0FD",'1'&x"F0FE",'1'&x"F0FF",
+--'1'&x"F100",'1'&x"F101",'1'&x"F102",'1'&x"F103",'1'&x"F104",'1'&x"F105",'1'&x"F106",'1'&x"F107",'1'&x"F108",'1'&x"F109",'1'&x"F10A",'1'&x"F10B",'1'&x"F10C",'1'&x"F10D",'1'&x"F10E",'1'&x"F10F",
+--'1'&x"F110",'1'&x"F111",'1'&x"F112",'1'&x"F113",'1'&x"F114",'1'&x"F115",'1'&x"F116",'1'&x"F117",'1'&x"F118",'1'&x"F119",'1'&x"F11A",'1'&x"F11B",'1'&x"F11C",'1'&x"F11D",'1'&x"F11E",'1'&x"F11F",
+--'1'&x"F120",'1'&x"F121",'1'&x"F122",'1'&x"F123",'1'&x"F124",'1'&x"F125",'1'&x"F126",'1'&x"F127",'1'&x"F128",'1'&x"F129",'1'&x"F12A",'1'&x"F12B",'1'&x"F12C",'1'&x"F12D",'1'&x"F12E",'1'&x"F12F",
+--'1'&x"F130",'1'&x"F131",'1'&x"F132",'1'&x"F133",'1'&x"F134",'1'&x"F135",'1'&x"F136",'1'&x"F137",'1'&x"F138",'1'&x"F139",'1'&x"F13A",'1'&x"F13B",'1'&x"F13C",'1'&x"F13D",'1'&x"F13E",'1'&x"F13F",
+--'1'&x"F140",'1'&x"F141",'1'&x"F142",'1'&x"F143",'1'&x"F144",'1'&x"F145",'1'&x"F146",'1'&x"F147",'1'&x"F148",'1'&x"F149",'1'&x"F14A",'1'&x"F14B",'1'&x"F14C",'1'&x"F14D",'1'&x"F14E",'1'&x"F14F",
+--'1'&x"F150",'1'&x"F151",'1'&x"F152",'1'&x"F153",'1'&x"F154",'1'&x"F155",'1'&x"F156",'1'&x"F157",'1'&x"F158",'1'&x"F159",'1'&x"F15A",'1'&x"F15B",'1'&x"F15C",'1'&x"F15D",'1'&x"F15E",'1'&x"F15F",
+--'1'&x"F160",'1'&x"F161",'1'&x"F162",'1'&x"F163",'1'&x"F164",'1'&x"F165",'1'&x"F166",'1'&x"F167",'1'&x"F168",'1'&x"F169",'1'&x"F16A",'1'&x"F16B",'1'&x"F16C",'1'&x"F16D",'1'&x"F16E",'1'&x"F16F",
+--'1'&x"F170",'1'&x"F171",'1'&x"F172",'1'&x"F173",'1'&x"F174",'1'&x"F175",'1'&x"F176",'1'&x"F177",'1'&x"F178",'1'&x"F179",'1'&x"F17A",'1'&x"F17B",'1'&x"F17C",'1'&x"F17D",'1'&x"F17E",'1'&x"F17F",
+--'1'&x"F180",'1'&x"F181",'1'&x"F182",'1'&x"F183",'1'&x"F184",'1'&x"F185",'1'&x"F186",'1'&x"F187",'1'&x"F188",'1'&x"F189",'1'&x"F18A",'1'&x"F18B",'1'&x"F18C",'1'&x"F18D",'1'&x"F18E",'1'&x"F18F",
+--'1'&x"F190",'1'&x"F191",'1'&x"F192",'1'&x"F193",'1'&x"F194",'1'&x"F195",'1'&x"F196",'1'&x"F197",'1'&x"F198",'1'&x"F199",'1'&x"F19A",'1'&x"F19B",'1'&x"F19C",'1'&x"F19D",'1'&x"F19E",'1'&x"F19F",
+--'1'&x"F1A0",'1'&x"F1A1",'1'&x"F1A2",'1'&x"F1A3",'1'&x"F1A4",'1'&x"F1A5",'1'&x"F1A6",'1'&x"F1A7",'1'&x"F1A8",'1'&x"F1A9",'1'&x"F1AA",'1'&x"F1AB",'1'&x"F1AC",'1'&x"F1AD",'1'&x"F1AE",'1'&x"F1AF",
+--'1'&x"F1B0",'1'&x"F1B1",'1'&x"F1B2",'1'&x"F1B3",'1'&x"F1B4",'1'&x"F1B5",'1'&x"F1B6",'1'&x"F1B7",'1'&x"F1B8",'1'&x"F1B9",'1'&x"F1BA",'1'&x"F1BB",'1'&x"F1BC",'1'&x"F1BD",'1'&x"F1BE",'1'&x"F1BF",
+--'1'&x"F1C0",'1'&x"F1C1",'1'&x"F1C2",'1'&x"F1C3",'1'&x"F1C4",'1'&x"F1C5",'1'&x"F1C6",'1'&x"F1C7",'1'&x"F1C8",'1'&x"F1C9",'1'&x"F1CA",'1'&x"F1CB",'1'&x"F1CC",'1'&x"F1CD",'1'&x"F1CE",'1'&x"F1CF",
+--'1'&x"F1D0",'1'&x"F1D1",'1'&x"F1D2",'1'&x"F1D3",'1'&x"F1D4",'1'&x"F1D5",'1'&x"F1D6",'1'&x"F1D7",'1'&x"F1D8",'1'&x"F1D9",'1'&x"F1DA",'1'&x"F1DB",'1'&x"F1DC",'1'&x"F1DD",'1'&x"F1DE",'1'&x"F1DF",
+--'1'&x"F1E0",'1'&x"F1E1",'1'&x"F1E2",'1'&x"F1E3",'1'&x"F1E4",'1'&x"F1E5",'1'&x"F1E6",'1'&x"F1E7",'1'&x"F1E8",'1'&x"F1E9",'1'&x"F1EA",'1'&x"F1EB",'1'&x"F1EC",'1'&x"F1ED",'1'&x"F1EE",'1'&x"F1EF",
+--'1'&x"F1F0",'1'&x"F1F1",'1'&x"F1F2",'1'&x"F1F3",'1'&x"F1F4",'1'&x"F1F5",'1'&x"F1F6",'1'&x"F1F7",'1'&x"F1F8",'1'&x"F1F9",'1'&x"F1FA",'1'&x"F1FB",'1'&x"F1FC",'1'&x"F1FD",'1'&x"F1FE",'1'&x"F1FF",
+--'1'&x"F200",'1'&x"F201",'1'&x"F202",'1'&x"F203",'1'&x"F204",'1'&x"F205",'1'&x"F206",'1'&x"F207",'1'&x"F208",'1'&x"F209",'1'&x"F20A",'1'&x"F20B",'1'&x"F20C",'1'&x"F20D",'1'&x"F20E",'1'&x"F20F",
+--'1'&x"F210",'1'&x"F211",'1'&x"F212",'1'&x"F213",'1'&x"F214",'1'&x"F215",'1'&x"F216",'1'&x"F217",'1'&x"F218",'1'&x"F219",'1'&x"F21A",'1'&x"F21B",'1'&x"F21C",'1'&x"F21D",'1'&x"F21E",'1'&x"F21F",
+--'1'&x"F220",'1'&x"F221",'1'&x"F222",'1'&x"F223",'1'&x"F224",'1'&x"F225",'1'&x"F226",'1'&x"F227",'1'&x"F228",'1'&x"F229",'1'&x"F22A",'1'&x"F22B",'1'&x"F22C",'1'&x"F22D",'1'&x"F22E",'1'&x"F22F",
+--'1'&x"F230",'1'&x"F231",'1'&x"F232",'1'&x"F233",'1'&x"F234",'1'&x"F235",'1'&x"F236",'1'&x"F237",'1'&x"F238",'1'&x"F239",'1'&x"F23A",'1'&x"F23B",'1'&x"F23C",'1'&x"F23D",'1'&x"F23E",'1'&x"F23F",
+--'1'&x"F240",'1'&x"F241",'1'&x"F242",'1'&x"F243",'1'&x"F244",'1'&x"F245",'1'&x"F246",'1'&x"F247",'1'&x"F248",'1'&x"F249",'1'&x"F24A",'1'&x"F24B",'1'&x"F24C",'1'&x"F24D",'1'&x"F24E",'1'&x"F24F",
+--'1'&x"F250",'1'&x"F251",'1'&x"F252",'1'&x"F253",'1'&x"F254",'1'&x"F255",'1'&x"F256",'1'&x"F257",'1'&x"F258",'1'&x"F259",'1'&x"F25A",'1'&x"F25B",'1'&x"F25C",'1'&x"F25D",'1'&x"F25E",'1'&x"F25F",
+--'1'&x"F260",'1'&x"F261",'1'&x"F262",'1'&x"F263",'1'&x"F264",'1'&x"F265",'1'&x"F266",'1'&x"F267",'1'&x"F268",'1'&x"F269",'1'&x"F26A",'1'&x"F26B",'1'&x"F26C",'1'&x"F26D",'1'&x"F26E",'1'&x"F26F",
+--'1'&x"F270",'1'&x"F271",'1'&x"F272",'1'&x"F273",'1'&x"F274",'1'&x"F275",'1'&x"F276",'1'&x"F277",'1'&x"F278",'1'&x"F279",'1'&x"F27A",'1'&x"F27B",'1'&x"F27C",'1'&x"F27D",'1'&x"F27E",'1'&x"F27F",
+--'1'&x"F280",'1'&x"F281",'1'&x"F282",'1'&x"F283",'1'&x"F284",'1'&x"F285",'1'&x"F286",'1'&x"F287",'1'&x"F288",'1'&x"F289",'1'&x"F28A",'1'&x"F28B",'1'&x"F28C",'1'&x"F28D",'1'&x"F28E",'1'&x"F28F",
+--'1'&x"F290",'1'&x"F291",'1'&x"F292",'1'&x"F293",'1'&x"F294",'1'&x"F295",'1'&x"F296",'1'&x"F297",'1'&x"F298",'1'&x"F299",'1'&x"F29A",'1'&x"F29B",'1'&x"F29C",'1'&x"F29D",'1'&x"F29E",'1'&x"F29F",
+--'1'&x"F2A0",'1'&x"F2A1",'1'&x"F2A2",'1'&x"F2A3",'1'&x"F2A4",'1'&x"F2A5",'1'&x"F2A6",'1'&x"F2A7",'1'&x"F2A8",'1'&x"F2A9",'1'&x"F2AA",'1'&x"F2AB",'1'&x"F2AC",'1'&x"F2AD",'1'&x"F2AE",'1'&x"F2AF",
+--'1'&x"F2B0",'1'&x"F2B1",'1'&x"F2B2",'1'&x"F2B3",'1'&x"F2B4",'1'&x"F2B5",'1'&x"F2B6",'1'&x"F2B7",'1'&x"F2B8",'1'&x"F2B9",'1'&x"F2BA",'1'&x"F2BB",'1'&x"F2BC",'1'&x"F2BD",'1'&x"F2BE",'1'&x"F2BF",
+--'1'&x"F2C0",'1'&x"F2C1",'1'&x"F2C2",'1'&x"F2C3",'1'&x"F2C4",'1'&x"F2C5",'1'&x"F2C6",'1'&x"F2C7",'1'&x"F2C8",'1'&x"F2C9",'1'&x"F2CA",'1'&x"F2CB",'1'&x"F2CC",'1'&x"F2CD",'1'&x"F2CE",'1'&x"F2CF",
+--'1'&x"F2D0",'1'&x"F2D1",'1'&x"F2D2",'1'&x"F2D3",'1'&x"F2D4",'1'&x"F2D5",'1'&x"F2D6",'1'&x"F2D7",'1'&x"F2D8",'1'&x"F2D9",'1'&x"F2DA",'1'&x"F2DB",'1'&x"F2DC",'1'&x"F2DD",'1'&x"F2DE",'1'&x"F2DF",
+--'1'&x"F2E0",'1'&x"F2E1",'1'&x"F2E2",'1'&x"F2E3",'1'&x"F2E4",'1'&x"F2E5",'1'&x"F2E6",'1'&x"F2E7",'1'&x"F2E8",'1'&x"F2E9",'1'&x"F2EA",'1'&x"F2EB",'1'&x"F2EC",'1'&x"F2ED",'1'&x"F2EE",'1'&x"F2EF",
+--'1'&x"F2F0",'1'&x"F2F1",'1'&x"F2F2",'1'&x"F2F3",'1'&x"F2F4",'1'&x"F2F5",'1'&x"F2F6",'1'&x"F2F7",'1'&x"F2F8",'1'&x"F2F9",'1'&x"F2FA",'1'&x"F2FB",'1'&x"F2FC",'1'&x"F2FD",'1'&x"F2FE",'1'&x"F2FF",
+--'1'&x"F300",'1'&x"F301",'1'&x"F302",'1'&x"F303",'1'&x"F304",'1'&x"F305",'1'&x"F306",'1'&x"F307",'1'&x"F308",'1'&x"F309",'1'&x"F30A",'1'&x"F30B",'1'&x"F30C",'1'&x"F30D",'1'&x"F30E",'1'&x"F30F",
+--'1'&x"F310",'1'&x"F311",'1'&x"F312",'1'&x"F313",'1'&x"F314",'1'&x"F315",'1'&x"F316",'1'&x"F317",'1'&x"F318",'1'&x"F319",'1'&x"F31A",'1'&x"F31B",'1'&x"F31C",'1'&x"F31D",'1'&x"F31E",'1'&x"F31F",
+--'1'&x"F320",'1'&x"F321",'1'&x"F322",'1'&x"F323",'1'&x"F324",'1'&x"F325",'1'&x"F326",'1'&x"F327",'1'&x"F328",'1'&x"F329",'1'&x"F32A",'1'&x"F32B",'1'&x"F32C",'1'&x"F32D",'1'&x"F32E",'1'&x"F32F",
+--'1'&x"F330",'1'&x"F331",'1'&x"F332",'1'&x"F333",'1'&x"F334",'1'&x"F335",'1'&x"F336",'1'&x"F337",'1'&x"F338",'1'&x"F339",'1'&x"F33A",'1'&x"F33B",'1'&x"F33C",'1'&x"F33D",'1'&x"F33E",'1'&x"F33F",
+--'1'&x"F340",'1'&x"F341",'1'&x"F342",'1'&x"F343",'1'&x"F344",'1'&x"F345",'1'&x"F346",'1'&x"F347",'1'&x"F348",'1'&x"F349",'1'&x"F34A",'1'&x"F34B",'1'&x"F34C",'1'&x"F34D",'1'&x"F34E",'1'&x"F34F",
+--'1'&x"F350",'1'&x"F351",'1'&x"F352",'1'&x"F353",'1'&x"F354",'1'&x"F355",'1'&x"F356",'1'&x"F357",'1'&x"F358",'1'&x"F359",'1'&x"F35A",'1'&x"F35B",'1'&x"F35C",'1'&x"F35D",'1'&x"F35E",'1'&x"F35F",
+--'1'&x"F360",'1'&x"F361",'1'&x"F362",'1'&x"F363",'1'&x"F364",'1'&x"F365",'1'&x"F366",'1'&x"F367",'1'&x"F368",'1'&x"F369",'1'&x"F36A",'1'&x"F36B",'1'&x"F36C",'1'&x"F36D",'1'&x"F36E",'1'&x"F36F",
+--'1'&x"F370",'1'&x"F371",'1'&x"F372",'1'&x"F373",'1'&x"F374",'1'&x"F375",'1'&x"F376",'1'&x"F377",'1'&x"F378",'1'&x"F379",'1'&x"F37A",'1'&x"F37B",'1'&x"F37C",'1'&x"F37D",'1'&x"F37E",'1'&x"F37F",
+--'1'&x"F380",'1'&x"F381",'1'&x"F382",'1'&x"F383",'1'&x"F384",'1'&x"F385",'1'&x"F386",'1'&x"F387",'1'&x"F388",'1'&x"F389",'1'&x"F38A",'1'&x"F38B",'1'&x"F38C",'1'&x"F38D",'1'&x"F38E",'1'&x"F38F",
+--'1'&x"F390",'1'&x"F391",'1'&x"F392",'1'&x"F393",'1'&x"F394",'1'&x"F395",'1'&x"F396",'1'&x"F397",'1'&x"F398",'1'&x"F399",'1'&x"F39A",'1'&x"F39B",'1'&x"F39C",'1'&x"F39D",'1'&x"F39E",'1'&x"F39F",
+--'1'&x"F3A0",'1'&x"F3A1",'1'&x"F3A2",'1'&x"F3A3",'1'&x"F3A4",'1'&x"F3A5",'1'&x"F3A6",'1'&x"F3A7",'1'&x"F3A8",'1'&x"F3A9",'1'&x"F3AA",'1'&x"F3AB",'1'&x"F3AC",'1'&x"F3AD",'1'&x"F3AE",'1'&x"F3AF",
+--'1'&x"F3B0",'1'&x"F3B1",'1'&x"F3B2",'1'&x"F3B3",'1'&x"F3B4",'1'&x"F3B5",'1'&x"F3B6",'1'&x"F3B7",'1'&x"F3B8",'1'&x"F3B9",'1'&x"F3BA",'1'&x"F3BB",'1'&x"F3BC",'1'&x"F3BD",'1'&x"F3BE",'1'&x"F3BF",
+--'1'&x"F3C0",'1'&x"F3C1",'1'&x"F3C2",'1'&x"F3C3",'1'&x"F3C4",'1'&x"F3C5",'1'&x"F3C6",'1'&x"F3C7",'1'&x"F3C8",'1'&x"F3C9",'1'&x"F3CA",'1'&x"F3CB",'1'&x"F3CC",'1'&x"F3CD",'1'&x"F3CE",'1'&x"F3CF",
+--'1'&x"F3D0",'1'&x"F3D1",'1'&x"F3D2",'1'&x"F3D3",'1'&x"F3D4",'1'&x"F3D5",'1'&x"F3D6",'1'&x"F3D7",'1'&x"F3D8",'1'&x"F3D9",'1'&x"F3DA",'1'&x"F3DB",'1'&x"F3DC",'1'&x"F3DD",'1'&x"F3DE",'1'&x"F3DF",
+--'1'&x"F3E0",'1'&x"F3E1",'1'&x"F3E2",'1'&x"F3E3",'1'&x"F3E4",'1'&x"F3E5",'1'&x"F3E6",'1'&x"F3E7",'1'&x"F3E8",'1'&x"F3E9",'1'&x"F3EA",'1'&x"F3EB",'1'&x"F3EC",'1'&x"F3ED",'1'&x"F3EE",'1'&x"F3EF",
+--'1'&x"F3F0",'1'&x"F3F1",'1'&x"F3F2",'1'&x"F3F3",'1'&x"F3F4",'1'&x"F3F5",'1'&x"F3F6",'1'&x"F3F7",'1'&x"F3F8",'1'&x"F3F9",'1'&x"F3FA",'1'&x"F3FB",'1'&x"F3FC",'1'&x"F3FD",'1'&x"F3FE",'1'&x"F3FF",
+--'1'&x"F400",'1'&x"F401",'1'&x"F402",'1'&x"F403",'1'&x"F404",'1'&x"F405",'1'&x"F406",'1'&x"F407",'1'&x"F408",'1'&x"F409",'1'&x"F40A",'1'&x"F40B",'1'&x"F40C",'1'&x"F40D",'1'&x"F40E",'1'&x"F40F",
+--'1'&x"F410",'1'&x"F411",'1'&x"F412",'1'&x"F413",'1'&x"F414",'1'&x"F415",'1'&x"F416",'1'&x"F417",'1'&x"F418",'1'&x"F419",'1'&x"F41A",'1'&x"F41B",'1'&x"F41C",'1'&x"F41D",'1'&x"F41E",'1'&x"F41F",
+--'1'&x"F420",'1'&x"F421",'1'&x"F422",'1'&x"F423",'1'&x"F424",'1'&x"F425",'1'&x"F426",'1'&x"F427",'1'&x"F428",'1'&x"F429",'1'&x"F42A",'1'&x"F42B",'1'&x"F42C",'1'&x"F42D",'1'&x"F42E",'1'&x"F42F",
+--'1'&x"F430",'1'&x"F431",'1'&x"F432",'1'&x"F433",'1'&x"F434",'1'&x"F435",'1'&x"F436",'1'&x"F437",'1'&x"F438",'1'&x"F439",'1'&x"F43A",'1'&x"F43B",'1'&x"F43C",'1'&x"F43D",'1'&x"F43E",'1'&x"F43F",
+--'1'&x"F440",'1'&x"F441",'1'&x"F442",'1'&x"F443",'1'&x"F444",'1'&x"F445",'1'&x"F446",'1'&x"F447",'1'&x"F448",'1'&x"F449",'1'&x"F44A",'1'&x"F44B",'1'&x"F44C",'1'&x"F44D",'1'&x"F44E",'1'&x"F44F",
+--'1'&x"F450",'1'&x"F451",'1'&x"F452",'1'&x"F453",'1'&x"F454",'1'&x"F455",'1'&x"F456",'1'&x"F457",'1'&x"F458",'1'&x"F459",'1'&x"F45A",'1'&x"F45B",'1'&x"F45C",'1'&x"F45D",'1'&x"F45E",'1'&x"F45F",
+--'1'&x"F460",'1'&x"F461",'1'&x"F462",'1'&x"F463",'1'&x"F464",'1'&x"F465",'1'&x"F466",'1'&x"F467",'1'&x"F468",'1'&x"F469",'1'&x"F46A",'1'&x"F46B",'1'&x"F46C",'1'&x"F46D",'1'&x"F46E",'1'&x"F46F",
+--'1'&x"F470",'1'&x"F471",'1'&x"F472",'1'&x"F473",'1'&x"F474",'1'&x"F475",'1'&x"F476",'1'&x"F477",'1'&x"F478",'1'&x"F479",'1'&x"F47A",'1'&x"F47B",'1'&x"F47C",'1'&x"F47D",'1'&x"F47E",'1'&x"F47F",
+--'1'&x"F480",'1'&x"F481",'1'&x"F482",'1'&x"F483",'1'&x"F484",'1'&x"F485",'1'&x"F486",'1'&x"F487",'1'&x"F488",'1'&x"F489",'1'&x"F48A",'1'&x"F48B",'1'&x"F48C",'1'&x"F48D",'1'&x"F48E",'1'&x"F48F",
+--'1'&x"F490",'1'&x"F491",'1'&x"F492",'1'&x"F493",'1'&x"F494",'1'&x"F495",'1'&x"F496",'1'&x"F497",'1'&x"F498",'1'&x"F499",'1'&x"F49A",'1'&x"F49B",'1'&x"F49C",'1'&x"F49D",'1'&x"F49E",'1'&x"F49F",
+--'1'&x"F4A0",'1'&x"F4A1",'1'&x"F4A2",'1'&x"F4A3",'1'&x"F4A4",'1'&x"F4A5",'1'&x"F4A6",'1'&x"F4A7",'1'&x"F4A8",'1'&x"F4A9",'1'&x"F4AA",'1'&x"F4AB",'1'&x"F4AC",'1'&x"F4AD",'1'&x"F4AE",'1'&x"F4AF",
+--'1'&x"F4B0",'1'&x"F4B1",'1'&x"F4B2",'1'&x"F4B3",'1'&x"F4B4",'1'&x"F4B5",'1'&x"F4B6",'1'&x"F4B7",'1'&x"F4B8",'1'&x"F4B9",'1'&x"F4BA",'1'&x"F4BB",'1'&x"F4BC",'1'&x"F4BD",'1'&x"F4BE",'1'&x"F4BF",
+--'1'&x"F4C0",'1'&x"F4C1",'1'&x"F4C2",'1'&x"F4C3",'1'&x"F4C4",'1'&x"F4C5",'1'&x"F4C6",'1'&x"F4C7",'1'&x"F4C8",'1'&x"F4C9",'1'&x"F4CA",'1'&x"F4CB",'1'&x"F4CC",'1'&x"F4CD",'1'&x"F4CE",'1'&x"F4CF",
+--'1'&x"F4D0",'1'&x"F4D1",'1'&x"F4D2",'1'&x"F4D3",'1'&x"F4D4",'1'&x"F4D5",'1'&x"F4D6",'1'&x"F4D7",'1'&x"F4D8",'1'&x"F4D9",'1'&x"F4DA",'1'&x"F4DB",'1'&x"F4DC",'1'&x"F4DD",'1'&x"F4DE",'1'&x"F4DF",
+--'1'&x"F4E0",'1'&x"F4E1",'1'&x"F4E2",'1'&x"F4E3",'1'&x"F4E4",'1'&x"F4E5",'1'&x"F4E6",'1'&x"F4E7",'1'&x"F4E8",'1'&x"F4E9",'1'&x"F4EA",'1'&x"F4EB",'1'&x"F4EC",'1'&x"F4ED",'1'&x"F4EE",'1'&x"F4EF",
+--'1'&x"F4F0",'1'&x"F4F1",'1'&x"F4F2",'1'&x"F4F3",'1'&x"F4F4",'1'&x"F4F5",'1'&x"F4F6",'1'&x"F4F7",'1'&x"F4F8",'1'&x"F4F9",'1'&x"F4FA",'1'&x"F4FB",'1'&x"F4FC",'1'&x"F4FD",'1'&x"F4FE",'1'&x"F4FF",
+--'1'&x"F500",'1'&x"F501",'1'&x"F502",'1'&x"F503",'1'&x"F504",'1'&x"F505",'1'&x"F506",'1'&x"F507",'1'&x"F508",'1'&x"F509",'1'&x"F50A",'1'&x"F50B",'1'&x"F50C",'1'&x"F50D",'1'&x"F50E",'1'&x"F50F",
+--'1'&x"F510",'1'&x"F511",'1'&x"F512",'1'&x"F513",'1'&x"F514",'1'&x"F515",'1'&x"F516",'1'&x"F517",'1'&x"F518",'1'&x"F519",'1'&x"F51A",'1'&x"F51B",'1'&x"F51C",'1'&x"F51D",'1'&x"F51E",'1'&x"F51F",
+--'1'&x"F520",'1'&x"F521",'1'&x"F522",'1'&x"F523",'1'&x"F524",'1'&x"F525",'1'&x"F526",'1'&x"F527",'1'&x"F528",'1'&x"F529",'1'&x"F52A",'1'&x"F52B",'1'&x"F52C",'1'&x"F52D",'1'&x"F52E",'1'&x"F52F",
+--'1'&x"F530",'1'&x"F531",'1'&x"F532",'1'&x"F533",'1'&x"F534",'1'&x"F535",'1'&x"F536",'1'&x"F537",'1'&x"F538",'1'&x"F539",'1'&x"F53A",'1'&x"F53B",'1'&x"F53C",'1'&x"F53D",'1'&x"F53E",'1'&x"F53F",
+--'1'&x"F540",'1'&x"F541",'1'&x"F542",'1'&x"F543",'1'&x"F544",'1'&x"F545",'1'&x"F546",'1'&x"F547",'1'&x"F548",'1'&x"F549",'1'&x"F54A",'1'&x"F54B",'1'&x"F54C",'1'&x"F54D",'1'&x"F54E",'1'&x"F54F",
+--'1'&x"F550",'1'&x"F551",'1'&x"F552",'1'&x"F553",'1'&x"F554",'1'&x"F555",'1'&x"F556",'1'&x"F557",'1'&x"F558",'1'&x"F559",'1'&x"F55A",'1'&x"F55B",'1'&x"F55C",'1'&x"F55D",'1'&x"F55E",'1'&x"F55F",
+--'1'&x"F560",'1'&x"F561",'1'&x"F562",'1'&x"F563",'1'&x"F564",'1'&x"F565",'1'&x"F566",'1'&x"F567",'1'&x"F568",'1'&x"F569",'1'&x"F56A",'1'&x"F56B",'1'&x"F56C",'1'&x"F56D",'1'&x"F56E",'1'&x"F56F",
+--'1'&x"F570",'1'&x"F571",'1'&x"F572",'1'&x"F573",'1'&x"F574",'1'&x"F575",'1'&x"F576",'1'&x"F577",'1'&x"F578",'1'&x"F579",'1'&x"F57A",'1'&x"F57B",'1'&x"F57C",'1'&x"F57D",'1'&x"F57E",'1'&x"F57F",
+--'1'&x"F580",'1'&x"F581",'1'&x"F582",'1'&x"F583",'1'&x"F584",'1'&x"F585",'1'&x"F586",'1'&x"F587",'1'&x"F588",'1'&x"F589",'1'&x"F58A",'1'&x"F58B",'1'&x"F58C",'1'&x"F58D",'1'&x"F58E",'1'&x"F58F",
+--'1'&x"F590",'1'&x"F591",'1'&x"F592",'1'&x"F593",'1'&x"F594",'1'&x"F595",'1'&x"F596",'1'&x"F597",'1'&x"F598",'1'&x"F599",'1'&x"F59A",'1'&x"F59B",'1'&x"F59C",'1'&x"F59D",'1'&x"F59E",'1'&x"F59F",
+--'1'&x"F5A0",'1'&x"F5A1",'1'&x"F5A2",'1'&x"F5A3",'1'&x"F5A4",'1'&x"F5A5",'1'&x"F5A6",'1'&x"F5A7",'1'&x"F5A8",'1'&x"F5A9",'1'&x"F5AA",'1'&x"F5AB",'1'&x"F5AC",'1'&x"F5AD",'1'&x"F5AE",'1'&x"F5AF",
+--'1'&x"F5B0",'1'&x"F5B1",'1'&x"F5B2",'1'&x"F5B3",'1'&x"F5B4",'1'&x"F5B5",'1'&x"F5B6",'1'&x"F5B7",'1'&x"F5B8",'1'&x"F5B9",'1'&x"F5BA",'1'&x"F5BB",'1'&x"F5BC",'1'&x"F5BD",'1'&x"F5BE",'1'&x"F5BF",
+--'1'&x"F5C0",'1'&x"F5C1",'1'&x"F5C2",'1'&x"F5C3",'1'&x"F5C4",'1'&x"F5C5",'1'&x"F5C6",'1'&x"F5C7",'1'&x"F5C8",'1'&x"F5C9",'1'&x"F5CA",'1'&x"F5CB",'1'&x"F5CC",'1'&x"F5CD",'1'&x"F5CE",'1'&x"F5CF",
+--'1'&x"F5D0",'1'&x"F5D1",'1'&x"F5D2",'1'&x"F5D3",'1'&x"F5D4",'1'&x"F5D5",'1'&x"F5D6",'1'&x"F5D7",'1'&x"F5D8",'1'&x"F5D9",'1'&x"F5DA",'1'&x"F5DB",'1'&x"F5DC",'1'&x"F5DD",'1'&x"F5DE",'1'&x"F5DF",
+--'1'&x"F5E0",'1'&x"F5E1",'1'&x"F5E2",'1'&x"F5E3",'1'&x"F5E4",'1'&x"F5E5",'1'&x"F5E6",'1'&x"F5E7",'1'&x"F5E8",'1'&x"F5E9",'1'&x"F5EA",'1'&x"F5EB",'1'&x"F5EC",'1'&x"F5ED",'1'&x"F5EE",'1'&x"F5EF",
+--'1'&x"F5F0",'1'&x"F5F1",'1'&x"F5F2",'1'&x"F5F3",'1'&x"F5F4",'1'&x"F5F5",'1'&x"F5F6",'1'&x"F5F7",'1'&x"F5F8",'1'&x"F5F9",'1'&x"F5FA",'1'&x"F5FB",'1'&x"F5FC",'1'&x"F5FD",'1'&x"F5FE",'1'&x"F5FF",
+--'1'&x"F600",'1'&x"F601",'1'&x"F602",'1'&x"F603",'1'&x"F604",'1'&x"F605",'1'&x"F606",'1'&x"F607",'1'&x"F608",'1'&x"F609",'1'&x"F60A",'1'&x"F60B",'1'&x"F60C",'1'&x"F60D",'1'&x"F60E",'1'&x"F60F",
+--'1'&x"F610",'1'&x"F611",'1'&x"F612",'1'&x"F613",'1'&x"F614",'1'&x"F615",'1'&x"F616",'1'&x"F617",'1'&x"F618",'1'&x"F619",'1'&x"F61A",'1'&x"F61B",'1'&x"F61C",'1'&x"F61D",'1'&x"F61E",'1'&x"F61F",
+--'1'&x"F620",'1'&x"F621",'1'&x"F622",'1'&x"F623",'1'&x"F624",'1'&x"F625",'1'&x"F626",'1'&x"F627",'1'&x"F628",'1'&x"F629",'1'&x"F62A",'1'&x"F62B",'1'&x"F62C",'1'&x"F62D",'1'&x"F62E",'1'&x"F62F",
+--'1'&x"F630",'1'&x"F631",'1'&x"F632",'1'&x"F633",'1'&x"F634",'1'&x"F635",'1'&x"F636",'1'&x"F637",'1'&x"F638",'1'&x"F639",'1'&x"F63A",'1'&x"F63B",'1'&x"F63C",'1'&x"F63D",'1'&x"F63E",'1'&x"F63F",
+--'1'&x"F640",'1'&x"F641",'1'&x"F642",'1'&x"F643",'1'&x"F644",'1'&x"F645",'1'&x"F646",'1'&x"F647",'1'&x"F648",'1'&x"F649",'1'&x"F64A",'1'&x"F64B",'1'&x"F64C",'1'&x"F64D",'1'&x"F64E",'1'&x"F64F",
+--'1'&x"F650",'1'&x"F651",'1'&x"F652",'1'&x"F653",'1'&x"F654",'1'&x"F655",'1'&x"F656",'1'&x"F657",'1'&x"F658",'1'&x"F659",'1'&x"F65A",'1'&x"F65B",'1'&x"F65C",'1'&x"F65D",'1'&x"F65E",'1'&x"F65F",
+--'1'&x"F660",'1'&x"F661",'1'&x"F662",'1'&x"F663",'1'&x"F664",'1'&x"F665",'1'&x"F666",'1'&x"F667",'1'&x"F668",'1'&x"F669",'1'&x"F66A",'1'&x"F66B",'1'&x"F66C",'1'&x"F66D",'1'&x"F66E",'1'&x"F66F",
+--'1'&x"F670",'1'&x"F671",'1'&x"F672",'1'&x"F673",'1'&x"F674",'1'&x"F675",'1'&x"F676",'1'&x"F677",'1'&x"F678",'1'&x"F679",'1'&x"F67A",'1'&x"F67B",'1'&x"F67C",'1'&x"F67D",'1'&x"F67E",'1'&x"F67F",
+--'1'&x"F680",'1'&x"F681",'1'&x"F682",'1'&x"F683",'1'&x"F684",'1'&x"F685",'1'&x"F686",'1'&x"F687",'1'&x"F688",'1'&x"F689",'1'&x"F68A",'1'&x"F68B",'1'&x"F68C",'1'&x"F68D",'1'&x"F68E",'1'&x"F68F",
+--'1'&x"F690",'1'&x"F691",'1'&x"F692",'1'&x"F693",'1'&x"F694",'1'&x"F695",'1'&x"F696",'1'&x"F697",'1'&x"F698",'1'&x"F699",'1'&x"F69A",'1'&x"F69B",'1'&x"F69C",'1'&x"F69D",'1'&x"F69E",'1'&x"F69F",
+--'1'&x"F6A0",'1'&x"F6A1",'1'&x"F6A2",'1'&x"F6A3",'1'&x"F6A4",'1'&x"F6A5",'1'&x"F6A6",'1'&x"F6A7",'1'&x"F6A8",'1'&x"F6A9",'1'&x"F6AA",'1'&x"F6AB",'1'&x"F6AC",'1'&x"F6AD",'1'&x"F6AE",'1'&x"F6AF",
+--'1'&x"F6B0",'1'&x"F6B1",'1'&x"F6B2",'1'&x"F6B3",'1'&x"F6B4",'1'&x"F6B5",'1'&x"F6B6",'1'&x"F6B7",'1'&x"F6B8",'1'&x"F6B9",'1'&x"F6BA",'1'&x"F6BB",'1'&x"F6BC",'1'&x"F6BD",'1'&x"F6BE",'1'&x"F6BF",
+--'1'&x"F6C0",'1'&x"F6C1",'1'&x"F6C2",'1'&x"F6C3",'1'&x"F6C4",'1'&x"F6C5",'1'&x"F6C6",'1'&x"F6C7",'1'&x"F6C8",'1'&x"F6C9",'1'&x"F6CA",'1'&x"F6CB",'1'&x"F6CC",'1'&x"F6CD",'1'&x"F6CE",'1'&x"F6CF",
+--'1'&x"F6D0",'1'&x"F6D1",'1'&x"F6D2",'1'&x"F6D3",'1'&x"F6D4",'1'&x"F6D5",'1'&x"F6D6",'1'&x"F6D7",'1'&x"F6D8",'1'&x"F6D9",'1'&x"F6DA",'1'&x"F6DB",'1'&x"F6DC",'1'&x"F6DD",'1'&x"F6DE",'1'&x"F6DF",
+--'1'&x"F6E0",'1'&x"F6E1",'1'&x"F6E2",'1'&x"F6E3",'1'&x"F6E4",'1'&x"F6E5",'1'&x"F6E6",'1'&x"F6E7",'1'&x"F6E8",'1'&x"F6E9",'1'&x"F6EA",'1'&x"F6EB",'1'&x"F6EC",'1'&x"F6ED",'1'&x"F6EE",'1'&x"F6EF",
+--'1'&x"F6F0",'1'&x"F6F1",'1'&x"F6F2",'1'&x"F6F3",'1'&x"F6F4",'1'&x"F6F5",'1'&x"F6F6",'1'&x"F6F7",'1'&x"F6F8",'1'&x"F6F9",'1'&x"F6FA",'1'&x"F6FB",'1'&x"F6FC",'1'&x"F6FD",'1'&x"F6FE",'1'&x"F6FF",
+--'1'&x"F700",'1'&x"F701",'1'&x"F702",'1'&x"F703",'1'&x"F704",'1'&x"F705",'1'&x"F706",'1'&x"F707",'1'&x"F708",'1'&x"F709",'1'&x"F70A",'1'&x"F70B",'1'&x"F70C",'1'&x"F70D",'1'&x"F70E",'1'&x"F70F",
+--'1'&x"F710",'1'&x"F711",'1'&x"F712",'1'&x"F713",'1'&x"F714",'1'&x"F715",'1'&x"F716",'1'&x"F717",'1'&x"F718",'1'&x"F719",'1'&x"F71A",'1'&x"F71B",'1'&x"F71C",'1'&x"F71D",'1'&x"F71E",'1'&x"F71F",
+--'1'&x"F720",'1'&x"F721",'1'&x"F722",'1'&x"F723",'1'&x"F724",'1'&x"F725",'1'&x"F726",'1'&x"F727",'1'&x"F728",'1'&x"F729",'1'&x"F72A",'1'&x"F72B",'1'&x"F72C",'1'&x"F72D",'1'&x"F72E",'1'&x"F72F",
+--'1'&x"F730",'1'&x"F731",'1'&x"F732",'1'&x"F733",'1'&x"F734",'1'&x"F735",'1'&x"F736",'1'&x"F737",'1'&x"F738",'1'&x"F739",'1'&x"F73A",'1'&x"F73B",'1'&x"F73C",'1'&x"F73D",'1'&x"F73E",'1'&x"F73F",
+--'1'&x"F740",'1'&x"F741",'1'&x"F742",'1'&x"F743",'1'&x"F744",'1'&x"F745",'1'&x"F746",'1'&x"F747",'1'&x"F748",'1'&x"F749",'1'&x"F74A",'1'&x"F74B",'1'&x"F74C",'1'&x"F74D",'1'&x"F74E",'1'&x"F74F",
+--'1'&x"F750",'1'&x"F751",'1'&x"F752",'1'&x"F753",'1'&x"F754",'1'&x"F755",'1'&x"F756",'1'&x"F757",'1'&x"F758",'1'&x"F759",'1'&x"F75A",'1'&x"F75B",'1'&x"F75C",'1'&x"F75D",'1'&x"F75E",'1'&x"F75F",
+--'1'&x"F760",'1'&x"F761",'1'&x"F762",'1'&x"F763",'1'&x"F764",'1'&x"F765",'1'&x"F766",'1'&x"F767",'1'&x"F768",'1'&x"F769",'1'&x"F76A",'1'&x"F76B",'1'&x"F76C",'1'&x"F76D",'1'&x"F76E",'1'&x"F76F",
+--'1'&x"F770",'1'&x"F771",'1'&x"F772",'1'&x"F773",'1'&x"F774",'1'&x"F775",'1'&x"F776",'1'&x"F777",'1'&x"F778",'1'&x"F779",'1'&x"F77A",'1'&x"F77B",'1'&x"F77C",'1'&x"F77D",'1'&x"F77E",'1'&x"F77F",
+--'1'&x"F780",'1'&x"F781",'1'&x"F782",'1'&x"F783",'1'&x"F784",'1'&x"F785",'1'&x"F786",'1'&x"F787",'1'&x"F788",'1'&x"F789",'1'&x"F78A",'1'&x"F78B",'1'&x"F78C",'1'&x"F78D",'1'&x"F78E",'1'&x"F78F",
+--'1'&x"F790",'1'&x"F791",'1'&x"F792",'1'&x"F793",'1'&x"F794",'1'&x"F795",'1'&x"F796",'1'&x"F797",'1'&x"F798",'1'&x"F799",'1'&x"F79A",'1'&x"F79B",'1'&x"F79C",'1'&x"F79D",'1'&x"F79E",'1'&x"F79F",
+--'1'&x"F7A0",'1'&x"F7A1",'1'&x"F7A2",'1'&x"F7A3",'1'&x"F7A4",'1'&x"F7A5",'1'&x"F7A6",'1'&x"F7A7",'1'&x"F7A8",'1'&x"F7A9",'1'&x"F7AA",'1'&x"F7AB",'1'&x"F7AC",'1'&x"F7AD",'1'&x"F7AE",'1'&x"F7AF",
+--'1'&x"F7B0",'1'&x"F7B1",'1'&x"F7B2",'1'&x"F7B3",'1'&x"F7B4",'1'&x"F7B5",'1'&x"F7B6",'1'&x"F7B7",'1'&x"F7B8",'1'&x"F7B9",'1'&x"F7BA",'1'&x"F7BB",'1'&x"F7BC",'1'&x"F7BD",'1'&x"F7BE",'1'&x"F7BF",
+--'1'&x"F7C0",'1'&x"F7C1",'1'&x"F7C2",'1'&x"F7C3",'1'&x"F7C4",'1'&x"F7C5",'1'&x"F7C6",'1'&x"F7C7",'1'&x"F7C8",'1'&x"F7C9",'1'&x"F7CA",'1'&x"F7CB",'1'&x"F7CC",'1'&x"F7CD",'1'&x"F7CE",'1'&x"F7CF",
+--'1'&x"F7D0",'1'&x"F7D1",'1'&x"F7D2",'1'&x"F7D3",'1'&x"F7D4",'1'&x"F7D5",'1'&x"F7D6",'1'&x"F7D7",'1'&x"F7D8",'1'&x"F7D9",'1'&x"F7DA",'1'&x"F7DB",'1'&x"F7DC",'1'&x"F7DD",'1'&x"F7DE",'1'&x"F7DF",
+--'1'&x"F7E0",'1'&x"F7E1",'1'&x"F7E2",'1'&x"F7E3",'1'&x"F7E4",'1'&x"F7E5",'1'&x"F7E6",'1'&x"F7E7",'1'&x"F7E8",'1'&x"F7E9",'1'&x"F7EA",'1'&x"F7EB",'1'&x"F7EC",'1'&x"F7ED",'1'&x"F7EE",'1'&x"F7EF",
+--'1'&x"F7F0",'1'&x"F7F1",'1'&x"F7F2",'1'&x"F7F3",'1'&x"F7F4",'1'&x"F7F5",'1'&x"F7F6",'1'&x"F7F7",'1'&x"F7F8",'1'&x"F7F9",'1'&x"F7FA",'1'&x"F7FB",'1'&x"F7FC",'1'&x"F7FD",'1'&x"F7FE",'1'&x"F7FF",
+--'1'&x"F800",'1'&x"F801",'1'&x"F802",'1'&x"F803",'1'&x"F804",'1'&x"F805",'1'&x"F806",'1'&x"F807",'1'&x"F808",'1'&x"F809",'1'&x"F80A",'1'&x"F80B",'1'&x"F80C",'1'&x"F80D",'1'&x"F80E",'1'&x"F80F",
+--'1'&x"F810",'1'&x"F811",'1'&x"F812",'1'&x"F813",'1'&x"F814",'1'&x"F815",'1'&x"F816",'1'&x"F817",'1'&x"F818",'1'&x"F819",'1'&x"F81A",'1'&x"F81B",'1'&x"F81C",'1'&x"F81D",'1'&x"F81E",'1'&x"F81F",
+--'1'&x"F820",'1'&x"F821",'1'&x"F822",'1'&x"F823",'1'&x"F824",'1'&x"F825",'1'&x"F826",'1'&x"F827",'1'&x"F828",'1'&x"F829",'1'&x"F82A",'1'&x"F82B",'1'&x"F82C",'1'&x"F82D",'1'&x"F82E",'1'&x"F82F",
+--'1'&x"F830",'1'&x"F831",'1'&x"F832",'1'&x"F833",'1'&x"F834",'1'&x"F835",'1'&x"F836",'1'&x"F837",'1'&x"F838",'1'&x"F839",'1'&x"F83A",'1'&x"F83B",'1'&x"F83C",'1'&x"F83D",'1'&x"F83E",'1'&x"F83F",
+--'1'&x"F840",'1'&x"F841",'1'&x"F842",'1'&x"F843",'1'&x"F844",'1'&x"F845",'1'&x"F846",'1'&x"F847",'1'&x"F848",'1'&x"F849",'1'&x"F84A",'1'&x"F84B",'1'&x"F84C",'1'&x"F84D",'1'&x"F84E",'1'&x"F84F",
+--'1'&x"F850",'1'&x"F851",'1'&x"F852",'1'&x"F853",'1'&x"F854",'1'&x"F855",'1'&x"F856",'1'&x"F857",'1'&x"F858",'1'&x"F859",'1'&x"F85A",'1'&x"F85B",'1'&x"F85C",'1'&x"F85D",'1'&x"F85E",'1'&x"F85F",
+--'1'&x"F860",'1'&x"F861",'1'&x"F862",'1'&x"F863",'1'&x"F864",'1'&x"F865",'1'&x"F866",'1'&x"F867",'1'&x"F868",'1'&x"F869",'1'&x"F86A",'1'&x"F86B",'1'&x"F86C",'1'&x"F86D",'1'&x"F86E",'1'&x"F86F",
+--'1'&x"F870",'1'&x"F871",'1'&x"F872",'1'&x"F873",'1'&x"F874",'1'&x"F875",'1'&x"F876",'1'&x"F877",'1'&x"F878",'1'&x"F879",'1'&x"F87A",'1'&x"F87B",'1'&x"F87C",'1'&x"F87D",'1'&x"F87E",'1'&x"F87F",
+--'1'&x"F880",'1'&x"F881",'1'&x"F882",'1'&x"F883",'1'&x"F884",'1'&x"F885",'1'&x"F886",'1'&x"F887",'1'&x"F888",'1'&x"F889",'1'&x"F88A",'1'&x"F88B",'1'&x"F88C",'1'&x"F88D",'1'&x"F88E",'1'&x"F88F",
+--'1'&x"F890",'1'&x"F891",'1'&x"F892",'1'&x"F893",'1'&x"F894",'1'&x"F895",'1'&x"F896",'1'&x"F897",'1'&x"F898",'1'&x"F899",'1'&x"F89A",'1'&x"F89B",'1'&x"F89C",'1'&x"F89D",'1'&x"F89E",'1'&x"F89F",
+--'1'&x"F8A0",'1'&x"F8A1",'1'&x"F8A2",'1'&x"F8A3",'1'&x"F8A4",'1'&x"F8A5",'1'&x"F8A6",'1'&x"F8A7",'1'&x"F8A8",'1'&x"F8A9",'1'&x"F8AA",'1'&x"F8AB",'1'&x"F8AC",'1'&x"F8AD",'1'&x"F8AE",'1'&x"F8AF",
+--'1'&x"F8B0",'1'&x"F8B1",'1'&x"F8B2",'1'&x"F8B3",'1'&x"F8B4",'1'&x"F8B5",'1'&x"F8B6",'1'&x"F8B7",'1'&x"F8B8",'1'&x"F8B9",'1'&x"F8BA",'1'&x"F8BB",'1'&x"F8BC",'1'&x"F8BD",'1'&x"F8BE",'1'&x"F8BF",
+--'1'&x"F8C0",'1'&x"F8C1",'1'&x"F8C2",'1'&x"F8C3",'1'&x"F8C4",'1'&x"F8C5",'1'&x"F8C6",'1'&x"F8C7",'1'&x"F8C8",'1'&x"F8C9",'1'&x"F8CA",'1'&x"F8CB",'1'&x"F8CC",'1'&x"F8CD",'1'&x"F8CE",'1'&x"F8CF",
+--'1'&x"F8D0",'1'&x"F8D1",'1'&x"F8D2",'1'&x"F8D3",'1'&x"F8D4",'1'&x"F8D5",'1'&x"F8D6",'1'&x"F8D7",'1'&x"F8D8",'1'&x"F8D9",'1'&x"F8DA",'1'&x"F8DB",'1'&x"F8DC",'1'&x"F8DD",'1'&x"F8DE",'1'&x"F8DF",
+--'1'&x"F8E0",'1'&x"F8E1",'1'&x"F8E2",'1'&x"F8E3",'1'&x"F8E4",'1'&x"F8E5",'1'&x"F8E6",'1'&x"F8E7",'1'&x"F8E8",'1'&x"F8E9",'1'&x"F8EA",'1'&x"F8EB",'1'&x"F8EC",'1'&x"F8ED",'1'&x"F8EE",'1'&x"F8EF",
+--'1'&x"F8F0",'1'&x"F8F1",'1'&x"F8F2",'1'&x"F8F3",'1'&x"F8F4",'1'&x"F8F5",'1'&x"F8F6",'1'&x"F8F7",'1'&x"F8F8",'1'&x"F8F9",'1'&x"F8FA",'1'&x"F8FB",'1'&x"F8FC",'1'&x"F8FD",'1'&x"F8FE",'1'&x"F8FF",
+--'1'&x"F900",'1'&x"F901",'1'&x"F902",'1'&x"F903",'1'&x"F904",'1'&x"F905",'1'&x"F906",'1'&x"F907",'1'&x"F908",'1'&x"F909",'1'&x"F90A",'1'&x"F90B",'1'&x"F90C",'1'&x"F90D",'1'&x"F90E",'1'&x"F90F",
+--'1'&x"F910",'1'&x"F911",'1'&x"F912",'1'&x"F913",'1'&x"F914",'1'&x"F915",'1'&x"F916",'1'&x"F917",'1'&x"F918",'1'&x"F919",'1'&x"F91A",'1'&x"F91B",'1'&x"F91C",'1'&x"F91D",'1'&x"F91E",'1'&x"F91F",
+--'1'&x"F920",'1'&x"F921",'1'&x"F922",'1'&x"F923",'1'&x"F924",'1'&x"F925",'1'&x"F926",'1'&x"F927",'1'&x"F928",'1'&x"F929",'1'&x"F92A",'1'&x"F92B",'1'&x"F92C",'1'&x"F92D",'1'&x"F92E",'1'&x"F92F",
+--'1'&x"F930",'1'&x"F931",'1'&x"F932",'1'&x"F933",'1'&x"F934",'1'&x"F935",'1'&x"F936",'1'&x"F937",'1'&x"F938",'1'&x"F939",'1'&x"F93A",'1'&x"F93B",'1'&x"F93C",'1'&x"F93D",'1'&x"F93E",'1'&x"F93F",
+--'1'&x"F940",'1'&x"F941",'1'&x"F942",'1'&x"F943",'1'&x"F944",'1'&x"F945",'1'&x"F946",'1'&x"F947",'1'&x"F948",'1'&x"F949",'1'&x"F94A",'1'&x"F94B",'1'&x"F94C",'1'&x"F94D",'1'&x"F94E",'1'&x"F94F",
+--'1'&x"F950",'1'&x"F951",'1'&x"F952",'1'&x"F953",'1'&x"F954",'1'&x"F955",'1'&x"F956",'1'&x"F957",'1'&x"F958",'1'&x"F959",'1'&x"F95A",'1'&x"F95B",'1'&x"F95C",'1'&x"F95D",'1'&x"F95E",'1'&x"F95F",
+--'1'&x"F960",'1'&x"F961",'1'&x"F962",'1'&x"F963",'1'&x"F964",'1'&x"F965",'1'&x"F966",'1'&x"F967",'1'&x"F968",'1'&x"F969",'1'&x"F96A",'1'&x"F96B",'1'&x"F96C",'1'&x"F96D",'1'&x"F96E",'1'&x"F96F",
+--'1'&x"F970",'1'&x"F971",'1'&x"F972",'1'&x"F973",'1'&x"F974",'1'&x"F975",'1'&x"F976",'1'&x"F977",'1'&x"F978",'1'&x"F979",'1'&x"F97A",'1'&x"F97B",'1'&x"F97C",'1'&x"F97D",'1'&x"F97E",'1'&x"F97F",
+--'1'&x"F980",'1'&x"F981",'1'&x"F982",'1'&x"F983",'1'&x"F984",'1'&x"F985",'1'&x"F986",'1'&x"F987",'1'&x"F988",'1'&x"F989",'1'&x"F98A",'1'&x"F98B",'1'&x"F98C",'1'&x"F98D",'1'&x"F98E",'1'&x"F98F",
+--'1'&x"F990",'1'&x"F991",'1'&x"F992",'1'&x"F993",'1'&x"F994",'1'&x"F995",'1'&x"F996",'1'&x"F997",'1'&x"F998",'1'&x"F999",'1'&x"F99A",'1'&x"F99B",'1'&x"F99C",'1'&x"F99D",'1'&x"F99E",'1'&x"F99F",
+--'1'&x"F9A0",'1'&x"F9A1",'1'&x"F9A2",'1'&x"F9A3",'1'&x"F9A4",'1'&x"F9A5",'1'&x"F9A6",'1'&x"F9A7",'1'&x"F9A8",'1'&x"F9A9",'1'&x"F9AA",'1'&x"F9AB",'1'&x"F9AC",'1'&x"F9AD",'1'&x"F9AE",'1'&x"F9AF",
+--'1'&x"F9B0",'1'&x"F9B1",'1'&x"F9B2",'1'&x"F9B3",'1'&x"F9B4",'1'&x"F9B5",'1'&x"F9B6",'1'&x"F9B7",'1'&x"F9B8",'1'&x"F9B9",'1'&x"F9BA",'1'&x"F9BB",'1'&x"F9BC",'1'&x"F9BD",'1'&x"F9BE",'1'&x"F9BF",
+--'1'&x"F9C0",'1'&x"F9C1",'1'&x"F9C2",'1'&x"F9C3",'1'&x"F9C4",'1'&x"F9C5",'1'&x"F9C6",'1'&x"F9C7",'1'&x"F9C8",'1'&x"F9C9",'1'&x"F9CA",'1'&x"F9CB",'1'&x"F9CC",'1'&x"F9CD",'1'&x"F9CE",'1'&x"F9CF",
+--'1'&x"F9D0",'1'&x"F9D1",'1'&x"F9D2",'1'&x"F9D3",'1'&x"F9D4",'1'&x"F9D5",'1'&x"F9D6",'1'&x"F9D7",'1'&x"F9D8",'1'&x"F9D9",'1'&x"F9DA",'1'&x"F9DB",'1'&x"F9DC",'1'&x"F9DD",'1'&x"F9DE",'1'&x"F9DF",
+--'1'&x"F9E0",'1'&x"F9E1",'1'&x"F9E2",'1'&x"F9E3",'1'&x"F9E4",'1'&x"F9E5",'1'&x"F9E6",'1'&x"F9E7",'1'&x"F9E8",'1'&x"F9E9",'1'&x"F9EA",'1'&x"F9EB",'1'&x"F9EC",'1'&x"F9ED",'1'&x"F9EE",'1'&x"F9EF",
+--'1'&x"F9F0",'1'&x"F9F1",'1'&x"F9F2",'1'&x"F9F3",'1'&x"F9F4",'1'&x"F9F5",'1'&x"F9F6",'1'&x"F9F7",'1'&x"F9F8",'1'&x"F9F9",'1'&x"F9FA",'1'&x"F9FB",'1'&x"F9FC",'1'&x"F9FD",'1'&x"F9FE",'1'&x"F9FF",
+--'1'&x"FA00",'1'&x"FA01",'1'&x"FA02",'1'&x"FA03",'1'&x"FA04",'1'&x"FA05",'1'&x"FA06",'1'&x"FA07",'1'&x"FA08",'1'&x"FA09",'1'&x"FA0A",'1'&x"FA0B",'1'&x"FA0C",'1'&x"FA0D",'1'&x"FA0E",'1'&x"FA0F",
+--'1'&x"FA10",'1'&x"FA11",'1'&x"FA12",'1'&x"FA13",'1'&x"FA14",'1'&x"FA15",'1'&x"FA16",'1'&x"FA17",'1'&x"FA18",'1'&x"FA19",'1'&x"FA1A",'1'&x"FA1B",'1'&x"FA1C",'1'&x"FA1D",'1'&x"FA1E",'1'&x"FA1F",
+--'1'&x"FA20",'1'&x"FA21",'1'&x"FA22",'1'&x"FA23",'1'&x"FA24",'1'&x"FA25",'1'&x"FA26",'1'&x"FA27",'1'&x"FA28",'1'&x"FA29",'1'&x"FA2A",'1'&x"FA2B",'1'&x"FA2C",'1'&x"FA2D",'1'&x"FA2E",'1'&x"FA2F",
+--'1'&x"FA30",'1'&x"FA31",'1'&x"FA32",'1'&x"FA33",'1'&x"FA34",'1'&x"FA35",'1'&x"FA36",'1'&x"FA37",'1'&x"FA38",'1'&x"FA39",'1'&x"FA3A",'1'&x"FA3B",'1'&x"FA3C",'1'&x"FA3D",'1'&x"FA3E",'1'&x"FA3F",
+--'1'&x"FA40",'1'&x"FA41",'1'&x"FA42",'1'&x"FA43",'1'&x"FA44",'1'&x"FA45",'1'&x"FA46",'1'&x"FA47",'1'&x"FA48",'1'&x"FA49",'1'&x"FA4A",'1'&x"FA4B",'1'&x"FA4C",'1'&x"FA4D",'1'&x"FA4E",'1'&x"FA4F",
+--'1'&x"FA50",'1'&x"FA51",'1'&x"FA52",'1'&x"FA53",'1'&x"FA54",'1'&x"FA55",'1'&x"FA56",'1'&x"FA57",'1'&x"FA58",'1'&x"FA59",'1'&x"FA5A",'1'&x"FA5B",'1'&x"FA5C",'1'&x"FA5D",'1'&x"FA5E",'1'&x"FA5F",
+--'1'&x"FA60",'1'&x"FA61",'1'&x"FA62",'1'&x"FA63",'1'&x"FA64",'1'&x"FA65",'1'&x"FA66",'1'&x"FA67",'1'&x"FA68",'1'&x"FA69",'1'&x"FA6A",'1'&x"FA6B",'1'&x"FA6C",'1'&x"FA6D",'1'&x"FA6E",'1'&x"FA6F",
+--'1'&x"FA70",'1'&x"FA71",'1'&x"FA72",'1'&x"FA73",'1'&x"FA74",'1'&x"FA75",'1'&x"FA76",'1'&x"FA77",'1'&x"FA78",'1'&x"FA79",'1'&x"FA7A",'1'&x"FA7B",'1'&x"FA7C",'1'&x"FA7D",'1'&x"FA7E",'1'&x"FA7F",
+--'1'&x"FA80",'1'&x"FA81",'1'&x"FA82",'1'&x"FA83",'1'&x"FA84",'1'&x"FA85",'1'&x"FA86",'1'&x"FA87",'1'&x"FA88",'1'&x"FA89",'1'&x"FA8A",'1'&x"FA8B",'1'&x"FA8C",'1'&x"FA8D",'1'&x"FA8E",'1'&x"FA8F",
+--'1'&x"FA90",'1'&x"FA91",'1'&x"FA92",'1'&x"FA93",'1'&x"FA94",'1'&x"FA95",'1'&x"FA96",'1'&x"FA97",'1'&x"FA98",'1'&x"FA99",'1'&x"FA9A",'1'&x"FA9B",'1'&x"FA9C",'1'&x"FA9D",'1'&x"FA9E",'1'&x"FA9F",
+--'1'&x"FAA0",'1'&x"FAA1",'1'&x"FAA2",'1'&x"FAA3",'1'&x"FAA4",'1'&x"FAA5",'1'&x"FAA6",'1'&x"FAA7",'1'&x"FAA8",'1'&x"FAA9",'1'&x"FAAA",'1'&x"FAAB",'1'&x"FAAC",'1'&x"FAAD",'1'&x"FAAE",'1'&x"FAAF",
+--'1'&x"FAB0",'1'&x"FAB1",'1'&x"FAB2",'1'&x"FAB3",'1'&x"FAB4",'1'&x"FAB5",'1'&x"FAB6",'1'&x"FAB7",'1'&x"FAB8",'1'&x"FAB9",'1'&x"FABA",'1'&x"FABB",'1'&x"FABC",'1'&x"FABD",'1'&x"FABE",'1'&x"FABF",
+--'1'&x"FAC0",'1'&x"FAC1",'1'&x"FAC2",'1'&x"FAC3",'1'&x"FAC4",'1'&x"FAC5",'1'&x"FAC6",'1'&x"FAC7",'1'&x"FAC8",'1'&x"FAC9",'1'&x"FACA",'1'&x"FACB",'1'&x"FACC",'1'&x"FACD",'1'&x"FACE",'1'&x"FACF",
+--'1'&x"FAD0",'1'&x"FAD1",'1'&x"FAD2",'1'&x"FAD3",'1'&x"FAD4",'1'&x"FAD5",'1'&x"FAD6",'1'&x"FAD7",'1'&x"FAD8",'1'&x"FAD9",'1'&x"FADA",'1'&x"FADB",'1'&x"FADC",'1'&x"FADD",'1'&x"FADE",'1'&x"FADF",
+--'1'&x"FAE0",'1'&x"FAE1",'1'&x"FAE2",'1'&x"FAE3",'1'&x"FAE4",'1'&x"FAE5",'1'&x"FAE6",'1'&x"FAE7",'1'&x"FAE8",'1'&x"FAE9",'1'&x"FAEA",'1'&x"FAEB",'1'&x"FAEC",'1'&x"FAED",'1'&x"FAEE",'1'&x"FAEF",
+--'1'&x"FAF0",'1'&x"FAF1",'1'&x"FAF2",'1'&x"FAF3",'1'&x"FAF4",'1'&x"FAF5",'1'&x"FAF6",'1'&x"FAF7",'1'&x"FAF8",'1'&x"FAF9",'1'&x"FAFA",'1'&x"FAFB",'1'&x"FAFC",'1'&x"FAFD",'1'&x"FAFE",'1'&x"FAFF",
+--'1'&x"FB00",'1'&x"FB01",'1'&x"FB02",'1'&x"FB03",'1'&x"FB04",'1'&x"FB05",'1'&x"FB06",'1'&x"FB07",'1'&x"FB08",'1'&x"FB09",'1'&x"FB0A",'1'&x"FB0B",'1'&x"FB0C",'1'&x"FB0D",'1'&x"FB0E",'1'&x"FB0F",
+--'1'&x"FB10",'1'&x"FB11",'1'&x"FB12",'1'&x"FB13",'1'&x"FB14",'1'&x"FB15",'1'&x"FB16",'1'&x"FB17",'1'&x"FB18",'1'&x"FB19",'1'&x"FB1A",'1'&x"FB1B",'1'&x"FB1C",'1'&x"FB1D",'1'&x"FB1E",'1'&x"FB1F",
+--'1'&x"FB20",'1'&x"FB21",'1'&x"FB22",'1'&x"FB23",'1'&x"FB24",'1'&x"FB25",'1'&x"FB26",'1'&x"FB27",'1'&x"FB28",'1'&x"FB29",'1'&x"FB2A",'1'&x"FB2B",'1'&x"FB2C",'1'&x"FB2D",'1'&x"FB2E",'1'&x"FB2F",
+--'1'&x"FB30",'1'&x"FB31",'1'&x"FB32",'1'&x"FB33",'1'&x"FB34",'1'&x"FB35",'1'&x"FB36",'1'&x"FB37",'1'&x"FB38",'1'&x"FB39",'1'&x"FB3A",'1'&x"FB3B",'1'&x"FB3C",'1'&x"FB3D",'1'&x"FB3E",'1'&x"FB3F",
+--'1'&x"FB40",'1'&x"FB41",'1'&x"FB42",'1'&x"FB43",'1'&x"FB44",'1'&x"FB45",'1'&x"FB46",'1'&x"FB47",'1'&x"FB48",'1'&x"FB49",'1'&x"FB4A",'1'&x"FB4B",'1'&x"FB4C",'1'&x"FB4D",'1'&x"FB4E",'1'&x"FB4F",
+--'1'&x"FB50",'1'&x"FB51",'1'&x"FB52",'1'&x"FB53",'1'&x"FB54",'1'&x"FB55",'1'&x"FB56",'1'&x"FB57",'1'&x"FB58",'1'&x"FB59",'1'&x"FB5A",'1'&x"FB5B",'1'&x"FB5C",'1'&x"FB5D",'1'&x"FB5E",'1'&x"FB5F",
+--'1'&x"FB60",'1'&x"FB61",'1'&x"FB62",'1'&x"FB63",'1'&x"FB64",'1'&x"FB65",'1'&x"FB66",'1'&x"FB67",'1'&x"FB68",'1'&x"FB69",'1'&x"FB6A",'1'&x"FB6B",'1'&x"FB6C",'1'&x"FB6D",'1'&x"FB6E",'1'&x"FB6F",
+--'1'&x"FB70",'1'&x"FB71",'1'&x"FB72",'1'&x"FB73",'1'&x"FB74",'1'&x"FB75",'1'&x"FB76",'1'&x"FB77",'1'&x"FB78",'1'&x"FB79",'1'&x"FB7A",'1'&x"FB7B",'1'&x"FB7C",'1'&x"FB7D",'1'&x"FB7E",'1'&x"FB7F",
+--'1'&x"FB80",'1'&x"FB81",'1'&x"FB82",'1'&x"FB83",'1'&x"FB84",'1'&x"FB85",'1'&x"FB86",'1'&x"FB87",'1'&x"FB88",'1'&x"FB89",'1'&x"FB8A",'1'&x"FB8B",'1'&x"FB8C",'1'&x"FB8D",'1'&x"FB8E",'1'&x"FB8F",
+--'1'&x"FB90",'1'&x"FB91",'1'&x"FB92",'1'&x"FB93",'1'&x"FB94",'1'&x"FB95",'1'&x"FB96",'1'&x"FB97",'1'&x"FB98",'1'&x"FB99",'1'&x"FB9A",'1'&x"FB9B",'1'&x"FB9C",'1'&x"FB9D",'1'&x"FB9E",'1'&x"FB9F",
+--'1'&x"FBA0",'1'&x"FBA1",'1'&x"FBA2",'1'&x"FBA3",'1'&x"FBA4",'1'&x"FBA5",'1'&x"FBA6",'1'&x"FBA7",'1'&x"FBA8",'1'&x"FBA9",'1'&x"FBAA",'1'&x"FBAB",'1'&x"FBAC",'1'&x"FBAD",'1'&x"FBAE",'1'&x"FBAF",
+--'1'&x"FBB0",'1'&x"FBB1",'1'&x"FBB2",'1'&x"FBB3",'1'&x"FBB4",'1'&x"FBB5",'1'&x"FBB6",'1'&x"FBB7",'1'&x"FBB8",'1'&x"FBB9",'1'&x"FBBA",'1'&x"FBBB",'1'&x"FBBC",'1'&x"FBBD",'1'&x"FBBE",'1'&x"FBBF",
+--'1'&x"FBC0",'1'&x"FBC1",'1'&x"FBC2",'1'&x"FBC3",'1'&x"FBC4",'1'&x"FBC5",'1'&x"FBC6",'1'&x"FBC7",'1'&x"FBC8",'1'&x"FBC9",'1'&x"FBCA",'1'&x"FBCB",'1'&x"FBCC",'1'&x"FBCD",'1'&x"FBCE",'1'&x"FBCF",
+--'1'&x"FBD0",'1'&x"FBD1",'1'&x"FBD2",'1'&x"FBD3",'1'&x"FBD4",'1'&x"FBD5",'1'&x"FBD6",'1'&x"FBD7",'1'&x"FBD8",'1'&x"FBD9",'1'&x"FBDA",'1'&x"FBDB",'1'&x"FBDC",'1'&x"FBDD",'1'&x"FBDE",'1'&x"FBDF",
+--'1'&x"FBE0",'1'&x"FBE1",'1'&x"FBE2",'1'&x"FBE3",'1'&x"FBE4",'1'&x"FBE5",'1'&x"FBE6",'1'&x"FBE7",'1'&x"FBE8",'1'&x"FBE9",'1'&x"FBEA",'1'&x"FBEB",'1'&x"FBEC",'1'&x"FBED",'1'&x"FBEE",'1'&x"FBEF",
+--'1'&x"FBF0",'1'&x"FBF1",'1'&x"FBF2",'1'&x"FBF3",'1'&x"FBF4",'1'&x"FBF5",'1'&x"FBF6",'1'&x"FBF7",'1'&x"FBF8",'1'&x"FBF9",'1'&x"FBFA",'1'&x"FBFB",'1'&x"FBFC",'1'&x"FBFD",'1'&x"FBFE",'1'&x"FBFF",
+--'1'&x"FC00",'1'&x"FC01",'1'&x"FC02",'1'&x"FC03",'1'&x"FC04",'1'&x"FC05",'1'&x"FC06",'1'&x"FC07",'1'&x"FC08",'1'&x"FC09",'1'&x"FC0A",'1'&x"FC0B",'1'&x"FC0C",'1'&x"FC0D",'1'&x"FC0E",'1'&x"FC0F",
+--'1'&x"FC10",'1'&x"FC11",'1'&x"FC12",'1'&x"FC13",'1'&x"FC14",'1'&x"FC15",'1'&x"FC16",'1'&x"FC17",'1'&x"FC18",'1'&x"FC19",'1'&x"FC1A",'1'&x"FC1B",'1'&x"FC1C",'1'&x"FC1D",'1'&x"FC1E",'1'&x"FC1F",
+--'1'&x"FC20",'1'&x"FC21",'1'&x"FC22",'1'&x"FC23",'1'&x"FC24",'1'&x"FC25",'1'&x"FC26",'1'&x"FC27",'1'&x"FC28",'1'&x"FC29",'1'&x"FC2A",'1'&x"FC2B",'1'&x"FC2C",'1'&x"FC2D",'1'&x"FC2E",'1'&x"FC2F",
+--'1'&x"FC30",'1'&x"FC31",'1'&x"FC32",'1'&x"FC33",'1'&x"FC34",'1'&x"FC35",'1'&x"FC36",'1'&x"FC37",'1'&x"FC38",'1'&x"FC39",'1'&x"FC3A",'1'&x"FC3B",'1'&x"FC3C",'1'&x"FC3D",'1'&x"FC3E",'1'&x"FC3F",
+--'1'&x"FC40",'1'&x"FC41",'1'&x"FC42",'1'&x"FC43",'1'&x"FC44",'1'&x"FC45",'1'&x"FC46",'1'&x"FC47",'1'&x"FC48",'1'&x"FC49",'1'&x"FC4A",'1'&x"FC4B",'1'&x"FC4C",'1'&x"FC4D",'1'&x"FC4E",'1'&x"FC4F",
+--'1'&x"FC50",'1'&x"FC51",'1'&x"FC52",'1'&x"FC53",'1'&x"FC54",'1'&x"FC55",'1'&x"FC56",'1'&x"FC57",'1'&x"FC58",'1'&x"FC59",'1'&x"FC5A",'1'&x"FC5B",'1'&x"FC5C",'1'&x"FC5D",'1'&x"FC5E",'1'&x"FC5F",
+--'1'&x"FC60",'1'&x"FC61",'1'&x"FC62",'1'&x"FC63",'1'&x"FC64",'1'&x"FC65",'1'&x"FC66",'1'&x"FC67",'1'&x"FC68",'1'&x"FC69",'1'&x"FC6A",'1'&x"FC6B",'1'&x"FC6C",'1'&x"FC6D",'1'&x"FC6E",'1'&x"FC6F",
+--'1'&x"FC70",'1'&x"FC71",'1'&x"FC72",'1'&x"FC73",'1'&x"FC74",'1'&x"FC75",'1'&x"FC76",'1'&x"FC77",'1'&x"FC78",'1'&x"FC79",'1'&x"FC7A",'1'&x"FC7B",'1'&x"FC7C",'1'&x"FC7D",'1'&x"FC7E",'1'&x"FC7F",
+--'1'&x"FC80",'1'&x"FC81",'1'&x"FC82",'1'&x"FC83",'1'&x"FC84",'1'&x"FC85",'1'&x"FC86",'1'&x"FC87",'1'&x"FC88",'1'&x"FC89",'1'&x"FC8A",'1'&x"FC8B",'1'&x"FC8C",'1'&x"FC8D",'1'&x"FC8E",'1'&x"FC8F",
+--'1'&x"FC90",'1'&x"FC91",'1'&x"FC92",'1'&x"FC93",'1'&x"FC94",'1'&x"FC95",'1'&x"FC96",'1'&x"FC97",'1'&x"FC98",'1'&x"FC99",'1'&x"FC9A",'1'&x"FC9B",'1'&x"FC9C",'1'&x"FC9D",'1'&x"FC9E",'1'&x"FC9F",
+--'1'&x"FCA0",'1'&x"FCA1",'1'&x"FCA2",'1'&x"FCA3",'1'&x"FCA4",'1'&x"FCA5",'1'&x"FCA6",'1'&x"FCA7",'1'&x"FCA8",'1'&x"FCA9",'1'&x"FCAA",'1'&x"FCAB",'1'&x"FCAC",'1'&x"FCAD",'1'&x"FCAE",'1'&x"FCAF",
+--'1'&x"FCB0",'1'&x"FCB1",'1'&x"FCB2",'1'&x"FCB3",'1'&x"FCB4",'1'&x"FCB5",'1'&x"FCB6",'1'&x"FCB7",'1'&x"FCB8",'1'&x"FCB9",'1'&x"FCBA",'1'&x"FCBB",'1'&x"FCBC",'1'&x"FCBD",'1'&x"FCBE",'1'&x"FCBF",
+--'1'&x"FCC0",'1'&x"FCC1",'1'&x"FCC2",'1'&x"FCC3",'1'&x"FCC4",'1'&x"FCC5",'1'&x"FCC6",'1'&x"FCC7",'1'&x"FCC8",'1'&x"FCC9",'1'&x"FCCA",'1'&x"FCCB",'1'&x"FCCC",'1'&x"FCCD",'1'&x"FCCE",'1'&x"FCCF",
+--'1'&x"FCD0",'1'&x"FCD1",'1'&x"FCD2",'1'&x"FCD3",'1'&x"FCD4",'1'&x"FCD5",'1'&x"FCD6",'1'&x"FCD7",'1'&x"FCD8",'1'&x"FCD9",'1'&x"FCDA",'1'&x"FCDB",'1'&x"FCDC",'1'&x"FCDD",'1'&x"FCDE",'1'&x"FCDF",
+--'1'&x"FCE0",'1'&x"FCE1",'1'&x"FCE2",'1'&x"FCE3",'1'&x"FCE4",'1'&x"FCE5",'1'&x"FCE6",'1'&x"FCE7",'1'&x"FCE8",'1'&x"FCE9",'1'&x"FCEA",'1'&x"FCEB",'1'&x"FCEC",'1'&x"FCED",'1'&x"FCEE",'1'&x"FCEF",
+--'1'&x"FCF0",'1'&x"FCF1",'1'&x"FCF2",'1'&x"FCF3",'1'&x"FCF4",'1'&x"FCF5",'1'&x"FCF6",'1'&x"FCF7",'1'&x"FCF8",'1'&x"FCF9",'1'&x"FCFA",'1'&x"FCFB",'1'&x"FCFC",'1'&x"FCFD",'1'&x"FCFE",'1'&x"FCFF",
+--'1'&x"FD00",'1'&x"FD01",'1'&x"FD02",'1'&x"FD03",'1'&x"FD04",'1'&x"FD05",'1'&x"FD06",'1'&x"FD07",'1'&x"FD08",'1'&x"FD09",'1'&x"FD0A",'1'&x"FD0B",'1'&x"FD0C",'1'&x"FD0D",'1'&x"FD0E",'1'&x"FD0F",
+--'1'&x"FD10",'1'&x"FD11",'1'&x"FD12",'1'&x"FD13",'1'&x"FD14",'1'&x"FD15",'1'&x"FD16",'1'&x"FD17",'1'&x"FD18",'1'&x"FD19",'1'&x"FD1A",'1'&x"FD1B",'1'&x"FD1C",'1'&x"FD1D",'1'&x"FD1E",'1'&x"FD1F",
+--'1'&x"FD20",'1'&x"FD21",'1'&x"FD22",'1'&x"FD23",'1'&x"FD24",'1'&x"FD25",'1'&x"FD26",'1'&x"FD27",'1'&x"FD28",'1'&x"FD29",'1'&x"FD2A",'1'&x"FD2B",'1'&x"FD2C",'1'&x"FD2D",'1'&x"FD2E",'1'&x"FD2F",
+--'1'&x"FD30",'1'&x"FD31",'1'&x"FD32",'1'&x"FD33",'1'&x"FD34",'1'&x"FD35",'1'&x"FD36",'1'&x"FD37",'1'&x"FD38",'1'&x"FD39",'1'&x"FD3A",'1'&x"FD3B",'1'&x"FD3C",'1'&x"FD3D",'1'&x"FD3E",'1'&x"FD3F",
+--'1'&x"FD40",'1'&x"FD41",'1'&x"FD42",'1'&x"FD43",'1'&x"FD44",'1'&x"FD45",'1'&x"FD46",'1'&x"FD47",'1'&x"FD48",'1'&x"FD49",'1'&x"FD4A",'1'&x"FD4B",'1'&x"FD4C",'1'&x"FD4D",'1'&x"FD4E",'1'&x"FD4F",
+--'1'&x"FD50",'1'&x"FD51",'1'&x"FD52",'1'&x"FD53",'1'&x"FD54",'1'&x"FD55",'1'&x"FD56",'1'&x"FD57",'1'&x"FD58",'1'&x"FD59",'1'&x"FD5A",'1'&x"FD5B",'1'&x"FD5C",'1'&x"FD5D",'1'&x"FD5E",'1'&x"FD5F",
+--'1'&x"FD60",'1'&x"FD61",'1'&x"FD62",'1'&x"FD63",'1'&x"FD64",'1'&x"FD65",'1'&x"FD66",'1'&x"FD67",'1'&x"FD68",'1'&x"FD69",'1'&x"FD6A",'1'&x"FD6B",'1'&x"FD6C",'1'&x"FD6D",'1'&x"FD6E",'1'&x"FD6F",
+--'1'&x"FD70",'1'&x"FD71",'1'&x"FD72",'1'&x"FD73",'1'&x"FD74",'1'&x"FD75",'1'&x"FD76",'1'&x"FD77",'1'&x"FD78",'1'&x"FD79",'1'&x"FD7A",'1'&x"FD7B",'1'&x"FD7C",'1'&x"FD7D",'1'&x"FD7E",'1'&x"FD7F",
+--'1'&x"FD80",'1'&x"FD81",'1'&x"FD82",'1'&x"FD83",'1'&x"FD84",'1'&x"FD85",'1'&x"FD86",'1'&x"FD87",'1'&x"FD88",'1'&x"FD89",'1'&x"FD8A",'1'&x"FD8B",'1'&x"FD8C",'1'&x"FD8D",'1'&x"FD8E",'1'&x"FD8F",
+--'1'&x"FD90",'1'&x"FD91",'1'&x"FD92",'1'&x"FD93",'1'&x"FD94",'1'&x"FD95",'1'&x"FD96",'1'&x"FD97",'1'&x"FD98",'1'&x"FD99",'1'&x"FD9A",'1'&x"FD9B",'1'&x"FD9C",'1'&x"FD9D",'1'&x"FD9E",'1'&x"FD9F",
+--'1'&x"FDA0",'1'&x"FDA1",'1'&x"FDA2",'1'&x"FDA3",'1'&x"FDA4",'1'&x"FDA5",'1'&x"FDA6",'1'&x"FDA7",'1'&x"FDA8",'1'&x"FDA9",'1'&x"FDAA",'1'&x"FDAB",'1'&x"FDAC",'1'&x"FDAD",'1'&x"FDAE",'1'&x"FDAF",
+--'1'&x"FDB0",'1'&x"FDB1",'1'&x"FDB2",'1'&x"FDB3",'1'&x"FDB4",'1'&x"FDB5",'1'&x"FDB6",'1'&x"FDB7",'1'&x"FDB8",'1'&x"FDB9",'1'&x"FDBA",'1'&x"FDBB",'1'&x"FDBC",'1'&x"FDBD",'1'&x"FDBE",'1'&x"FDBF",
+--'1'&x"FDC0",'1'&x"FDC1",'1'&x"FDC2",'1'&x"FDC3",'1'&x"FDC4",'1'&x"FDC5",'1'&x"FDC6",'1'&x"FDC7",'1'&x"FDC8",'1'&x"FDC9",'1'&x"FDCA",'1'&x"FDCB",'1'&x"FDCC",'1'&x"FDCD",'1'&x"FDCE",'1'&x"FDCF",
+--'1'&x"FDD0",'1'&x"FDD1",'1'&x"FDD2",'1'&x"FDD3",'1'&x"FDD4",'1'&x"FDD5",'1'&x"FDD6",'1'&x"FDD7",'1'&x"FDD8",'1'&x"FDD9",'1'&x"FDDA",'1'&x"FDDB",'1'&x"FDDC",'1'&x"FDDD",'1'&x"FDDE",'1'&x"FDDF",
+--'1'&x"FDE0",'1'&x"FDE1",'1'&x"FDE2",'1'&x"FDE3",'1'&x"FDE4",'1'&x"FDE5",'1'&x"FDE6",'1'&x"FDE7",'1'&x"FDE8",'1'&x"FDE9",'1'&x"FDEA",'1'&x"FDEB",'1'&x"FDEC",'1'&x"FDED",'1'&x"FDEE",'1'&x"FDEF",
+--'1'&x"FDF0",'1'&x"FDF1",'1'&x"FDF2",'1'&x"FDF3",'1'&x"FDF4",'1'&x"FDF5",'1'&x"FDF6",'1'&x"FDF7",'1'&x"FDF8",'1'&x"FDF9",'1'&x"FDFA",'1'&x"FDFB",'1'&x"FDFC",'1'&x"FDFD",'1'&x"FDFE",'1'&x"FDFF",
+--'1'&x"FE00",'1'&x"FE01",'1'&x"FE02",'1'&x"FE03",'1'&x"FE04",'1'&x"FE05",'1'&x"FE06",'1'&x"FE07",'1'&x"FE08",'1'&x"FE09",'1'&x"FE0A",'1'&x"FE0B",'1'&x"FE0C",'1'&x"FE0D",'1'&x"FE0E",'1'&x"FE0F",
+--'1'&x"FE10",'1'&x"FE11",'1'&x"FE12",'1'&x"FE13",'1'&x"FE14",'1'&x"FE15",'1'&x"FE16",'1'&x"FE17",'1'&x"FE18",'1'&x"FE19",'1'&x"FE1A",'1'&x"FE1B",'1'&x"FE1C",'1'&x"FE1D",'1'&x"FE1E",'1'&x"FE1F",
+--'1'&x"FE20",'1'&x"FE21",'1'&x"FE22",'1'&x"FE23",'1'&x"FE24",'1'&x"FE25",'1'&x"FE26",'1'&x"FE27",'1'&x"FE28",'1'&x"FE29",'1'&x"FE2A",'1'&x"FE2B",'1'&x"FE2C",'1'&x"FE2D",'1'&x"FE2E",'1'&x"FE2F",
+--'1'&x"FE30",'1'&x"FE31",'1'&x"FE32",'1'&x"FE33",'1'&x"FE34",'1'&x"FE35",'1'&x"FE36",'1'&x"FE37",'1'&x"FE38",'1'&x"FE39",'1'&x"FE3A",'1'&x"FE3B",'1'&x"FE3C",'1'&x"FE3D",'1'&x"FE3E",'1'&x"FE3F",
+--'1'&x"FE40",'1'&x"FE41",'1'&x"FE42",'1'&x"FE43",'1'&x"FE44",'1'&x"FE45",'1'&x"FE46",'1'&x"FE47",'1'&x"FE48",'1'&x"FE49",'1'&x"FE4A",'1'&x"FE4B",'1'&x"FE4C",'1'&x"FE4D",'1'&x"FE4E",'1'&x"FE4F",
+--'1'&x"FE50",'1'&x"FE51",'1'&x"FE52",'1'&x"FE53",'1'&x"FE54",'1'&x"FE55",'1'&x"FE56",'1'&x"FE57",'1'&x"FE58",'1'&x"FE59",'1'&x"FE5A",'1'&x"FE5B",'1'&x"FE5C",'1'&x"FE5D",'1'&x"FE5E",'1'&x"FE5F",
+--'1'&x"FE60",'1'&x"FE61",'1'&x"FE62",'1'&x"FE63",'1'&x"FE64",'1'&x"FE65",'1'&x"FE66",'1'&x"FE67",'1'&x"FE68",'1'&x"FE69",'1'&x"FE6A",'1'&x"FE6B",'1'&x"FE6C",'1'&x"FE6D",'1'&x"FE6E",'1'&x"FE6F",
+--'1'&x"FE70",'1'&x"FE71",'1'&x"FE72",'1'&x"FE73",'1'&x"FE74",'1'&x"FE75",'1'&x"FE76",'1'&x"FE77",'1'&x"FE78",'1'&x"FE79",'1'&x"FE7A",'1'&x"FE7B",'1'&x"FE7C",'1'&x"FE7D",'1'&x"FE7E",'1'&x"FE7F",
+--'1'&x"FE80",'1'&x"FE81",'1'&x"FE82",'1'&x"FE83",'1'&x"FE84",'1'&x"FE85",'1'&x"FE86",'1'&x"FE87",'1'&x"FE88",'1'&x"FE89",'1'&x"FE8A",'1'&x"FE8B",'1'&x"FE8C",'1'&x"FE8D",'1'&x"FE8E",'1'&x"FE8F",
+--'1'&x"FE90",'1'&x"FE91",'1'&x"FE92",'1'&x"FE93",'1'&x"FE94",'1'&x"FE95",'1'&x"FE96",'1'&x"FE97",'1'&x"FE98",'1'&x"FE99",'1'&x"FE9A",'1'&x"FE9B",'1'&x"FE9C",'1'&x"FE9D",'1'&x"FE9E",'1'&x"FE9F",
+--'1'&x"FEA0",'1'&x"FEA1",'1'&x"FEA2",'1'&x"FEA3",'1'&x"FEA4",'1'&x"FEA5",'1'&x"FEA6",'1'&x"FEA7",'1'&x"FEA8",'1'&x"FEA9",'1'&x"FEAA",'1'&x"FEAB",'1'&x"FEAC",'1'&x"FEAD",'1'&x"FEAE",'1'&x"FEAF",
+--'1'&x"FEB0",'1'&x"FEB1",'1'&x"FEB2",'1'&x"FEB3",'1'&x"FEB4",'1'&x"FEB5",'1'&x"FEB6",'1'&x"FEB7",'1'&x"FEB8",'1'&x"FEB9",'1'&x"FEBA",'1'&x"FEBB",'1'&x"FEBC",'1'&x"FEBD",'1'&x"FEBE",'1'&x"FEBF",
+--'1'&x"FEC0",'1'&x"FEC1",'1'&x"FEC2",'1'&x"FEC3",'1'&x"FEC4",'1'&x"FEC5",'1'&x"FEC6",'1'&x"FEC7",'1'&x"FEC8",'1'&x"FEC9",'1'&x"FECA",'1'&x"FECB",'1'&x"FECC",'1'&x"FECD",'1'&x"FECE",'1'&x"FECF",
+--'1'&x"FED0",'1'&x"FED1",'1'&x"FED2",'1'&x"FED3",'1'&x"FED4",'1'&x"FED5",'1'&x"FED6",'1'&x"FED7",'1'&x"FED8",'1'&x"FED9",'1'&x"FEDA",'1'&x"FEDB",'1'&x"FEDC",'1'&x"FEDD",'1'&x"FEDE",'1'&x"FEDF",
+--'1'&x"FEE0",'1'&x"FEE1",'1'&x"FEE2",'1'&x"FEE3",'1'&x"FEE4",'1'&x"FEE5",'1'&x"FEE6",'1'&x"FEE7",'1'&x"FEE8",'1'&x"FEE9",'1'&x"FEEA",'1'&x"FEEB",'1'&x"FEEC",'1'&x"FEED",'1'&x"FEEE",'1'&x"FEEF",
+--'1'&x"FEF0",'1'&x"FEF1",'1'&x"FEF2",'1'&x"FEF3",'1'&x"FEF4",'1'&x"FEF5",'1'&x"FEF6",'1'&x"FEF7",'1'&x"FEF8",'1'&x"FEF9",'1'&x"FEFA",'1'&x"FEFB",'1'&x"FEFC",'1'&x"FEFD",'1'&x"FEFE",'1'&x"FEFF",
+--'1'&x"FF00",'1'&x"FF01",'1'&x"FF02",'1'&x"FF03",'1'&x"FF04",'1'&x"FF05",'1'&x"FF06",'1'&x"FF07",'1'&x"FF08",'1'&x"FF09",'1'&x"FF0A",'1'&x"FF0B",'1'&x"FF0C",'1'&x"FF0D",'1'&x"FF0E",'1'&x"FF0F",
+--'1'&x"FF10",'1'&x"FF11",'1'&x"FF12",'1'&x"FF13",'1'&x"FF14",'1'&x"FF15",'1'&x"FF16",'1'&x"FF17",'1'&x"FF18",'1'&x"FF19",'1'&x"FF1A",'1'&x"FF1B",'1'&x"FF1C",'1'&x"FF1D",'1'&x"FF1E",'1'&x"FF1F",
+--'1'&x"FF20",'1'&x"FF21",'1'&x"FF22",'1'&x"FF23",'1'&x"FF24",'1'&x"FF25",'1'&x"FF26",'1'&x"FF27",'1'&x"FF28",'1'&x"FF29",'1'&x"FF2A",'1'&x"FF2B",'1'&x"FF2C",'1'&x"FF2D",'1'&x"FF2E",'1'&x"FF2F",
+--'1'&x"FF30",'1'&x"FF31",'1'&x"FF32",'1'&x"FF33",'1'&x"FF34",'1'&x"FF35",'1'&x"FF36",'1'&x"FF37",'1'&x"FF38",'1'&x"FF39",'1'&x"FF3A",'1'&x"FF3B",'1'&x"FF3C",'1'&x"FF3D",'1'&x"FF3E",'1'&x"FF3F",
+--'1'&x"FF40",'1'&x"FF41",'1'&x"FF42",'1'&x"FF43",'1'&x"FF44",'1'&x"FF45",'1'&x"FF46",'1'&x"FF47",'1'&x"FF48",'1'&x"FF49",'1'&x"FF4A",'1'&x"FF4B",'1'&x"FF4C",'1'&x"FF4D",'1'&x"FF4E",'1'&x"FF4F",
+--'1'&x"FF50",'1'&x"FF51",'1'&x"FF52",'1'&x"FF53",'1'&x"FF54",'1'&x"FF55",'1'&x"FF56",'1'&x"FF57",'1'&x"FF58",'1'&x"FF59",'1'&x"FF5A",'1'&x"FF5B",'1'&x"FF5C",'1'&x"FF5D",'1'&x"FF5E",'1'&x"FF5F",
+--'1'&x"FF60",'1'&x"FF61",'1'&x"FF62",'1'&x"FF63",'1'&x"FF64",'1'&x"FF65",'1'&x"FF66",'1'&x"FF67",'1'&x"FF68",'1'&x"FF69",'1'&x"FF6A",'1'&x"FF6B",'1'&x"FF6C",'1'&x"FF6D",'1'&x"FF6E",'1'&x"FF6F",
+--'1'&x"FF70",'1'&x"FF71",'1'&x"FF72",'1'&x"FF73",'1'&x"FF74",'1'&x"FF75",'1'&x"FF76",'1'&x"FF77",'1'&x"FF78",'1'&x"FF79",'1'&x"FF7A",'1'&x"FF7B",'1'&x"FF7C",'1'&x"FF7D",'1'&x"FF7E",'1'&x"FF7F",
+--'1'&x"FF80",'1'&x"FF81",'1'&x"FF82",'1'&x"FF83",'1'&x"FF84",'1'&x"FF85",'1'&x"FF86",'1'&x"FF87",'1'&x"FF88",'1'&x"FF89",'1'&x"FF8A",'1'&x"FF8B",'1'&x"FF8C",'1'&x"FF8D",'1'&x"FF8E",'1'&x"FF8F",
+--'1'&x"FF90",'1'&x"FF91",'1'&x"FF92",'1'&x"FF93",'1'&x"FF94",'1'&x"FF95",'1'&x"FF96",'1'&x"FF97",'1'&x"FF98",'1'&x"FF99",'1'&x"FF9A",'1'&x"FF9B",'1'&x"FF9C",'1'&x"FF9D",'1'&x"FF9E",'1'&x"FF9F",
+--'1'&x"FFA0",'1'&x"FFA1",'1'&x"FFA2",'1'&x"FFA3",'1'&x"FFA4",'1'&x"FFA5",'1'&x"FFA6",'1'&x"FFA7",'1'&x"FFA8",'1'&x"FFA9",'1'&x"FFAA",'1'&x"FFAB",'1'&x"FFAC",'1'&x"FFAD",'1'&x"FFAE",'1'&x"FFAF",
+--'1'&x"FFB0",'1'&x"FFB1",'1'&x"FFB2",'1'&x"FFB3",'1'&x"FFB4",'1'&x"FFB5",'1'&x"FFB6",'1'&x"FFB7",'1'&x"FFB8",'1'&x"FFB9",'1'&x"FFBA",'1'&x"FFBB",'1'&x"FFBC",'1'&x"FFBD",'1'&x"FFBE",'1'&x"FFBF",
+--'1'&x"FFC0",'1'&x"FFC1",'1'&x"FFC2",'1'&x"FFC3",'1'&x"FFC4",'1'&x"FFC5",'1'&x"FFC6",'1'&x"FFC7",'1'&x"FFC8",'1'&x"FFC9",'1'&x"FFCA",'1'&x"FFCB",'1'&x"FFCC",'1'&x"FFCD",'1'&x"FFCE",'1'&x"FFCF",
+--'1'&x"FFD0",'1'&x"FFD1",'1'&x"FFD2",'1'&x"FFD3",'1'&x"FFD4",'1'&x"FFD5",'1'&x"FFD6",'1'&x"FFD7",'1'&x"FFD8",'1'&x"FFD9",'1'&x"FFDA",'1'&x"FFDB",'1'&x"FFDC",'1'&x"FFDD",'1'&x"FFDE",'1'&x"FFDF",
+--'1'&x"FFE0",'1'&x"FFE1",'1'&x"FFE2",'1'&x"FFE3",'1'&x"FFE4",'1'&x"FFE5",'1'&x"FFE6",'1'&x"FFE7",'1'&x"FFE8",'1'&x"FFE9",'1'&x"FFEA",'1'&x"FFEB",'1'&x"FFEC",'1'&x"FFED",'1'&x"FFEE",'1'&x"FFEF",
+--'1'&x"FFF0",'1'&x"FFF1",'1'&x"FFF2",'1'&x"FFF3",'1'&x"FFF4",'1'&x"FFF5",'1'&x"FFF6",'1'&x"FFF7",'1'&x"FFF8",'1'&x"FFF9",'1'&x"FFFA",'1'&x"FFFB",'1'&x"FFFC",'1'&x"FFFD",'1'&x"FFFE",'1'&x"FFFF");
+
+attribute RAM_STYLE : string;
+attribute RAM_STYLE of mem_S: signal is "BLOCK";
+									 
+begin
+
+--	process (clock)
+--	begin
+--		if (clock'event and clock = '1') then
+--			if (write_enable = '1') then
+--				mem_S(conv_integer(write_address)) <= data_in;
+--			end if;
+--			data_out <= mem_S(conv_integer(read_address));			
+--		end if;
+--	end process;
+	process (clock)
+	begin
+		if (clock'event and clock = '1') then
+			if (write_enable = '1') then
+				mem_S(conv_integer(write_address)) <= data_in(16);
+			end if;
+			data_out(16) <= mem_S(conv_integer(read_address));			
+			data_out(14 downto 0) <= read_address(15 downto 1);			
+			data_out(15) <= '0';			
+		end if;
+	end process;	
+
+end architecture behavioral;
\ No newline at end of file
diff --git a/data_concentrator/sources/cluster/CN_cluster_build.vhd b/data_concentrator/sources/cluster/CN_cluster_build.vhd
new file mode 100644
index 0000000..b7c98ec
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_cluster_build.vhd
@@ -0,0 +1,1397 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   26-06-2016
+-- Module Name:   CN_cluster_build
+-- Description:   Construct clusters from a bunch of hits
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+use std.textio.all;
+use IEEE.std_logic_textio.all; -- I/O for logic types
+  
+----------------------------------------------------------------------------------
+-- CN_cluster_build
+-- Construct clusters from a bunch of (pre-)clusters, based on time and XY-position
+-- C-software developed by Marcel Tiemens
+-- Input precluster-data from module that splits up a stream in timebunches.
+-- If a cluster contains only one hit and if this hit is not position on the edge of the region then this cluster is skipped.
+--
+-- Input and output data format is the same:
+--
+-- Cluster packets with 64 bits data words:
+-- 64bits word1, only valid on a new superburst, when the signal data_in_first/data_out_first is active:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+-- for cluster data, for each cluster
+-- 64bits word2, clusterresults
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..30  = diameter
+--        bit29..20  = Y position, multiplied by 2
+--        bit19..10  = X position, multiplied by 2
+--        bit9..0    = number of hits in cluster
+-- 64bits word3..word3+nrofhits : pulse data
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+-- Criteria neighbours:
+--       crystal-positions (X0pos,Y0pos) and (X1pos,Y1pos) are neighbours :
+--				if (((X0pos>=X1pos) and (2*X0pos-2*X1pos <= diameter0+diameter1)) or ((X0pos<X1pos) and (2*X1pos-2*X0pos <= diameter0+diameter1)) and 
+--				  ((Y0pos>=Y1pos) and (2*Y0pos-2*Y1pos <= diameter0+diameter1)) or ((Y0pos<Y1pos) and (2*Y1pos-2*Y0pos <= diameter0+diameter1)) and 
+--				  (((pre0_t>=pre1_t) and (pre0_t-pre1_t <= timedifference)) or ((pre0_t<pre1_t) and (pre1_t-pre0_t <= timedifference))) then
+--                (time1-time0<=timedifference))
+--
+-- Library
+--
+-- 
+-- Generics:
+--     CLUSTERBITS : number of bits for the number of hits in one timebunch
+--     MAXCLUSTERSBITS : number of bits for the maximum clusters in one timebunch
+--     MINIMUMENERGYBITS : number of bits for the miminum energy value
+--     SKIPSINGLEHITCLUSTERS : skip cluster if it contains only one hit and is not positioned on the edge
+-- 
+-- Inputs:
+--     clock : clock
+--     reset : reset
+--     timedifference : maximum difference in time between hits in a cluster, resolutie from Constant Fraction (6.1ps)
+--     minimal_energy : minimum energy for a cluster; clusters with less are skipped if they are not positioned on the edge of a region
+--     data_in : 64-bits input data
+--     data_in_onedge : '1' if the hit is on the edge of the XY-area,
+--     data_in_active : timebunch active
+--     data_in_write : write signal for input data
+--     data_in_first : input data contains new superburst
+--     data_in_last : indicates that the cluster is the last in a superburst
+--     data_out_clusterallowed : allowed to write clusters to output
+--      
+-- 
+-- Outputs:
+--     data_in_allowed : writing of input data allowed 
+--     busy : busy processing timebunch
+--     data_out : 64 bits output data
+--     data_out_write : write signal for 64 bits output data
+--     data_out_first : 64 bits output data contains new superburst
+--     data_out_last : 64 bits output data is the last data of a superburst
+--     nextcluster : signal that indicates the last data of a timebunch
+--     dataerror : error in data
+-- 
+-- Components:
+--     blockmem : synchronous memory block 
+--     blockmemdirectread : synchronous memory block from which the output reacts directly on the written value
+--
+----------------------------------------------------------------------------------
+
+entity CN_cluster_build is
+	generic(
+		CLUSTERBITS             : natural := 8;
+		MAXCLUSTERSBITS         : natural := 5;
+		MINIMUMENERGYBITS       : natural := 8;
+		SKIPSINGLEHITCLUSTERS   : boolean := TRUE
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		timedifference          : in std_logic_vector(23 downto 0);
+		minimal_energy          : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_onedge          : in std_logic;
+		data_in_active          : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_allowed         : out std_logic;
+		busy                    : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_clusterallowed : in std_logic;
+		nextcluster             : out std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end CN_cluster_build;
+
+
+architecture behaviour of CN_cluster_build is
+
+component blockmem is
+	generic (
+		ADDRESS_BITS : natural := 16;
+		DATA_BITS  : natural := 32
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+component blockmemdirectread is
+	generic (
+		ADDRESS_BITS : natural := 16;
+		DATA_BITS  : natural := 32
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+constant ONES                       : std_logic_vector(63 downto 0) := (others => '1');
+constant ZEROS                      : std_logic_vector(63 downto 0) := (others => '0');
+type state_type is (INITIALIZE,COLLECT,PRE_READ0,PRE_READ1,PRIMARY,PRIMARY1,PRIMARY1_0,PRIMARY2,PRIMARY2_0,
+							SECONDAIRY,SECONDAIRY1,ADJUSTSIMULARITIES,SECONDAIRY2,SORTING,
+							WRITESUPERBURST,WRITEONECLUSTER,WRITEONECLUSTERHITS,
+							WRITECLUSTER,WRITEHITS0,WRITEHITS1,WRITEHITS);
+signal state_S                      : state_type := INITIALIZE;
+signal stateprev_S                  : state_type;
+
+signal error_S                      : std_logic := '0';
+signal data_in_write_S              : std_logic;
+signal data_write_address_S         : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_S          : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_prev_S     : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_nextaddress_S      : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_i_s        : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_j_s        : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_onedge_S                : std_logic_vector(0 to 2**CLUSTERBITS);
+signal minimal_energy_S             : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+
+signal data_in_S                    : std_logic_vector(63 downto 0);
+signal precluster0_S                : std_logic_vector(63 downto 0);
+signal data_first_S                 : std_logic := '0';
+signal data_last_S                  : std_logic := '0';
+signal data_in_onedge_S             : std_logic := '0';
+
+signal energy_in_S                  : std_logic_vector(MINIMUMENERGYBITS downto 0);
+signal energy_out_S                 : std_logic_vector(MINIMUMENERGYBITS downto 0);
+signal energy_write_address_S       : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal energy_read_address_S        : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal energy_write_S               : std_logic := '0';
+signal sum_energy_S                 : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+
+signal neighbours_write_S           : std_logic;
+signal neighbours_data_in_S         : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_data_out_S        : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_data_prev_S       : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal nNeighbours_S                : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_write_address_S   : std_logic_vector(CLUSTERBITS+1 downto 0) := (others => '0');
+signal neighbours_read_address_S    : std_logic_vector(CLUSTERBITS+1 downto 0) := (others => '0');
+signal neighbours_size_S            : std_logic_vector(CLUSTERBITS+1 downto 0) := (others => '0');
+
+signal overflow_S                   : std_logic := '0';
+signal passononecluster_S           : std_logic;
+
+signal hitcounter_s                 : integer range 0 to 2**CLUSTERBITS-1 := 0;
+signal nPres_S                      : integer range 0 to 2**CLUSTERBITS-1 := 0;
+signal pre_i_s                      : integer range 0 to 2**CLUSTERBITS-1 := 0;
+signal pre_j_s                      : integer range 0 to 2**CLUSTERBITS-1 := 0;
+signal last_pre_S                   : std_logic := '0';
+
+signal prim_k_S                     : integer range 0 to 2**CLUSTERBITS-1;
+
+signal nClusters1_S                 : integer range 0 to 2**CLUSTERBITS-1;
+signal simLength_S                  : integer range 0 to 2**CLUSTERBITS-1;
+
+signal isAdded_write_S              : std_logic;
+signal isAdded_write_address_S      : std_logic_vector(CLUSTERBITS-1 downto 0) := (others => '0');
+signal isAdded_read_address_S       : std_logic_vector(CLUSTERBITS-1 downto 0) := (others => '0');
+signal isAdded_data_in_S            : std_logic_vector(CLUSTERBITS downto 0);
+signal isAdded_data_out_S           : std_logic_vector(CLUSTERBITS downto 0);
+signal isAdded_k_S                  : std_logic_vector(CLUSTERBITS downto 0);
+
+signal nrofneighbours_s             : integer range 0 to 2**CLUSTERBITS-1;
+signal prim_m_S                     : integer range 0 to 2**CLUSTERBITS-1;
+signal prim_j_s                     : integer range 0 to 2**CLUSTERBITS-1;
+--type similarities_type is array(0 to 2*(2**CLUSTERBITS)-1) of std_logic_vector(CLUSTERBITS-1 downto 0);
+--signal similarities_s               : similarities_type;
+
+signal similarities_write_S         : std_logic;
+signal similarities_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_data_in_S       : std_logic_vector(CLUSTERBITS*2-1 downto 0);
+signal similarities_read_address_S  : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_data_out_S      : std_logic_vector(CLUSTERBITS*2-1 downto 0);
+signal similarities_source_S        : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_destination_S   : std_logic_vector(CLUSTERBITS-1 downto 0);
+
+
+signal sec1_i_S                     : integer range 0 to 2**CLUSTERBITS-1;
+signal sec1_j_S                     : integer range 0 to 2**CLUSTERBITS-1;
+signal sec1_m_S                     : integer range 0 to 2**CLUSTERBITS-1;
+signal sec2_i_S                     : integer range 0 to 2**CLUSTERBITS-1;
+signal sec2_n_S                     : std_logic;
+signal nClusters2_S                 : integer range 0 to 2**MAXCLUSTERSBITS-1;
+
+signal result_diameter_S            : std_logic_vector(9 downto 0);
+signal result_positionX_S           : std_logic_vector(9 downto 0);
+signal result_positionY_S           : std_logic_vector(9 downto 0);
+signal result_time_S                : std_logic_vector(23 downto 0);
+signal result_index_S               : integer range 0 to 2**CLUSTERBITS-1;
+signal result_nrofhits_S            : std_logic_vector(9 downto 0);
+signal result_onedge_S              : std_logic;
+
+signal results_write_address_S      : std_logic_vector(MAXCLUSTERSBITS-1 downto 0);
+signal results_read_address_S       : std_logic_vector(MAXCLUSTERSBITS-1 downto 0);
+signal results_data_in_S            : std_logic_vector(CLUSTERBITS+63 downto 0);
+signal results_data_out_S           : std_logic_vector(CLUSTERBITS+63 downto 0);
+signal results_write_S              : std_logic;
+signal results_index_s              : integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal results_filled_S             : std_logic;
+
+signal hitidx_write_address_S       : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_data_in_S             : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_read_address_S        : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_data_out_S            : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_write_S               : std_logic;
+signal hitidx_index_S               : integer range 0 to 2**CLUSTERBITS-1;
+signal hitidx_endaddress_s          : integer range 0 to 2**CLUSTERBITS-1;
+
+signal hitidx_hitpointer_S          : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_nrofprehits_S         : integer range 0 to 1023 := 0;
+signal hitidx_nrofhits_S            : integer range 0 to 1023 := 0;
+		
+signal nrofclocks_S                 : integer range 0 to 16383;
+signal isAdded_int_in_S             : integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+signal isAdded_int_out_S            : integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+
+signal sort_readkey_s               : std_logic;
+signal sort_ready_S                 : std_logic;
+type clustersortarray_type is array(0 to 2**MAXCLUSTERSBITS-1) of integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal clustersortarray_s           : clustersortarray_type;
+signal sort_i_s                     : integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal sort_j_s                     : integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal sort_j_neg_S                 : std_logic;
+signal sort_key_S                   : std_logic_vector(23 downto 0) := (others => '0');
+
+signal data_out_S                   : std_logic_vector(63 downto 0);
+signal data_out_write_S             : std_logic;
+signal data_out_first_S             : std_logic;
+signal data_out_last_S              : std_logic;
+
+
+--type isAdded_array is array(0 to 2**CLUSTERBITS-1) of integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+--signal debug_isAdded_S              : isAdded_array;
+signal debug_error_S                : std_logic;
+signal debug_minimal_energy_reached_S : std_logic;
+signal debug_sum_energy_S           : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+
+begin
+
+
+dataerror <= error_S;
+data_in_allowed <= '1' when (state_S=INITIALIZE) or (state_S=COLLECT) else '0';
+busy <= '1' when (state_S/=INITIALIZE) else '0';
+data_in_write_S <= '1' when (data_in_write='1') and (data_in_first='0') else '0';
+minimal_energy_S <= minimal_energy;
+
+datamemory: blockmem 
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS,
+		DATA_BITS => 64
+	)
+	port map(
+		clock => clock,
+		write_enable => data_in_write_S,
+		write_address => data_write_address_S,
+		data_in(63 downto 0) => data_in,
+		read_address => data_read_address_S,
+		data_out(63 downto 0) => data_in_S
+	);
+
+energymemory: blockmem 
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS,
+		DATA_BITS => MINIMUMENERGYBITS+1
+	)
+	port map(
+		clock => clock,
+		write_enable => energy_write_S,
+		write_address => energy_write_address_S,
+		data_in => energy_in_S,
+		read_address => energy_read_address_S,
+		data_out => energy_out_S
+	);
+	
+neighbours: blockmemdirectread 
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS+2,
+		DATA_BITS => CLUSTERBITS
+	)
+	port map(
+		clock => clock,
+		write_enable => neighbours_write_S,
+		write_address => neighbours_write_address_S,
+		data_in => neighbours_data_in_S,
+		read_address => neighbours_read_address_S,
+		data_out => neighbours_data_out_S
+	);
+
+isAddedmem: blockmemdirectread 
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS,
+		DATA_BITS => CLUSTERBITS+1
+	)
+	port map(
+		clock => clock,
+		write_enable => isAdded_write_S,
+		write_address => isAdded_write_address_S,
+		data_in => isAdded_data_in_S,
+		read_address => isAdded_read_address_S,
+		data_out => isAdded_data_out_S
+	);
+isAdded_int_in_S <= -1 when isAdded_data_in_S(CLUSTERBITS)='0' else conv_integer(unsigned(isAdded_data_in_S(CLUSTERBITS-1 downto 0)));
+isAdded_int_out_S <= -1 when isAdded_data_out_S(CLUSTERBITS)='0' else conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)));
+	
+similarities: blockmemdirectread 
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS,
+		DATA_BITS => CLUSTERBITS*2
+	)
+	port map(
+		clock => clock,
+		write_enable => similarities_write_S,
+		write_address => similarities_write_address_S,
+		data_in => similarities_data_in_S,
+		read_address => similarities_read_address_S,
+		data_out => similarities_data_out_S
+	);
+
+results: blockmemdirectread
+	generic map (
+		ADDRESS_BITS => MAXCLUSTERSBITS,
+		DATA_BITS => CLUSTERBITS+40+24
+	)
+	port map(
+		clock => clock,
+		write_enable => results_write_S,
+		write_address => results_write_address_S,
+		data_in => results_data_in_S,
+		read_address => results_read_address_S,
+		data_out => results_data_out_S
+	);
+
+hitidices: blockmem
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS,
+		DATA_BITS => CLUSTERBITS
+	)
+	port map(
+		clock => clock,
+		write_enable => hitidx_write_S,
+		write_address => hitidx_write_address_S,
+		data_in => hitidx_data_in_S,
+		read_address => hitidx_read_address_S,
+		data_out => hitidx_data_out_S
+	);
+	
+data_read_address_S <=
+	(others => '0') when (state_S=COLLECT) else
+	conv_std_logic_vector(conv_integer(unsigned(data_read_address_i_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS)
+		when (state_S=PRE_READ0) else
+	data_read_address_i_S when (state_S=PRE_READ1) and (pre_j_S>=nPres_S-1) else
+	conv_std_logic_vector(conv_integer(unsigned(data_read_address_j_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS)
+		when (state_S=PRE_READ1) else
+		
+		
+	(others => '0') when (state_S=SECONDAIRY1) else
+	conv_std_logic_vector(conv_integer(unsigned(hitidx_hitpointer_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS) when (state_S=SECONDAIRY2) and (sec1_m_S<nPres_S-1) else
+	(others => '0') when (state_S=SECONDAIRY2) else
+	(others => '0') when (state_S=WRITESUPERBURST) else
+	hitidx_hitpointer_S when (state_S=WRITEONECLUSTER) else
+	hitidx_hitpointer_S when (state_S=WRITEONECLUSTERHITS) else
+		
+	hitidx_data_out_S when (state_S=WRITECLUSTER) else
+	hitidx_data_out_S when (state_S=WRITEHITS0) else
+	hitidx_hitpointer_S when (state_S=WRITEHITS1) else
+	hitidx_data_out_S when (state_S=WRITEHITS) and (hitidx_nrofprehits_S<=1)  else
+	hitidx_hitpointer_S when (state_S=WRITEHITS) else
+	(others => '0');
+
+energy_read_address_S <= isAdded_read_address_S; --//??
+			
+isAdded_read_address_S <= 
+--	conv_std_logic_vector(nPres_S,CLUSTERBITS) when (state_S=PRIMARY) and (neighbours_read_address_S>=neighbours_size_S) else
+	conv_std_logic_vector(nPres_S,CLUSTERBITS)-1 when (state_S=PRIMARY) and (not ((neighbours_read_address_S<neighbours_size_S) or ((neighbours_size_S=1) and (neighbours_read_address_S=1)))) else
+	conv_std_logic_vector(nPres_S,CLUSTERBITS)-1 when (state_S=PRIMARY) and (neighbours_read_address_S>=neighbours_size_S) else
+	conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY) and (conv_integer(unsigned(neighbours_data_out_S))=0) else
+	conv_std_logic_vector(prim_k_S,CLUSTERBITS) when (state_S=PRIMARY) else
+	
+	neighbours_data_out_S when (state_S=PRIMARY1) else
+	neighbours_data_out_S when (state_S=PRIMARY1_0) and (prim_j_S<nrofneighbours_S-1) else
+	
+	conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY1_0) and (prim_j_S>=nrofneighbours_S-1) else
+	neighbours_data_out_S when (state_S=PRIMARY2) else
+	neighbours_data_out_S when (state_S=PRIMARY2_0) and (prim_j_S<nrofneighbours_S-1) else
+	conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY2_0) and (prim_j_S>=nrofneighbours_S-1) else
+	
+	conv_std_logic_vector(sec1_m_S,CLUSTERBITS) when (state_S=SECONDAIRY) else
+	
+	(others => '0') when ((state_S=SECONDAIRY1) and ((simLength_S=0) or ((sec1_i_S=simLength_S-1) and (sec1_m_S=nPres_S-1)))) else
+	conv_std_logic_vector(sec1_m_S+1,CLUSTERBITS) when (state_S=SECONDAIRY1) and (sec1_m_S<nPres_S-1) and
+		(similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) else
+	(others => '0') when (state_S=SECONDAIRY1) else
+
+	conv_std_logic_vector(sec1_m_S,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) else
+
+	conv_std_logic_vector(sec1_m_S+1,CLUSTERBITS) when (state_S=SECONDAIRY2) and (sec1_m_S<nPres_S-1) else
+	(others => '0') when (state_S=SECONDAIRY2) and (sec1_m_S>=nPres_S) else
+	
+	(others => '0');
+
+similarities_read_address_S <=
+	(others => '0') when (state_S=SECONDAIRY) else
+	conv_std_logic_vector(sec1_i_S,CLUSTERBITS) when (state_S=SECONDAIRY1) and (sec1_m_S<nPres_S-1) and
+		(similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) else
+	conv_std_logic_vector(sec1_i_S+1,CLUSTERBITS) when (state_S=SECONDAIRY1) else
+	conv_std_logic_vector(sec1_i_S,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) and (sec1_j_S=simLength_S-1) else
+	conv_std_logic_vector(sec1_j_S+1,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) else
+	(others => '0');
+				
+results_read_address_S <= 
+	conv_std_logic_vector(1,MAXCLUSTERSBITS) when (state_S=SECONDAIRY1) else
+	conv_std_logic_vector(clustersortarray_S(sort_i_S-1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='1') and (results_filled_S='1') and (sort_i_S<=results_write_address_S) else
+	conv_std_logic_vector(clustersortarray_S(sort_i_S),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='1') else
+	conv_std_logic_vector(clustersortarray_S(sort_j_S-1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='0') and (sort_j_S>0) and (sort_j_neg_S='0') and (results_data_out_S(30+23 downto 30)>sort_key_S) else
+	conv_std_logic_vector(clustersortarray_S(sort_i_S),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_i_S=2**MAXCLUSTERSBITS-1)  else
+	conv_std_logic_vector(clustersortarray_S(sort_i_S+1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING))  else
+	conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITESUPERBURST else
+	conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITECLUSTER else
+	conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITEHITS0 else
+	conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITEHITS1 else
+	conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITEHITS else
+	(others => '0');
+		
+hitidx_read_address_S <=				
+--??	results_data_out_S(2*CLUSTERBITS+30+23 downto CLUSTERBITS+30+24) when (state_S=WRITESUPERBURST) else
+	results_data_out_S(CLUSTERBITS+63 downto 64) when (state_S=WRITECLUSTER) else
+	conv_std_logic_vector(hitidx_index_S,CLUSTERBITS) when (state_S=WRITEHITS0) else
+	conv_std_logic_vector(hitidx_index_S,CLUSTERBITS) when (state_S=WRITEHITS1) else
+	conv_std_logic_vector(hitidx_index_S+1,CLUSTERBITS) when (state_S=WRITEHITS) and (hitidx_nrofprehits_S<=1) else
+	conv_std_logic_vector(hitidx_index_S,CLUSTERBITS) when (state_S=WRITEHITS) else
+	(others => '0');
+
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		case state_S is
+			when INITIALIZE =>
+				for i in 0 to 2**MAXCLUSTERSBITS-1 loop
+					clustersortarray_S(i) <= i;
+				end loop;
+			when COLLECT =>
+			when PRE_READ0 =>
+			when PRE_READ1 =>
+
+			when SECONDAIRY1 =>
+				sort_i_S <= 1;
+				sort_readkey_S <= '1';
+				sort_ready_S <= '0';
+				-- results_read_address_S <= 1;
+			when SECONDAIRY2 | SORTING =>
+				-- for (int i = 1; i < nPreclusters; i++)
+				-- {
+					-- int key = clusters_time[clustersortarray[i]];
+					-- int j = i - 1;
+					-- while (j >= 0 && clusters_time[clustersortarray[j]] > key)
+					-- {
+						-- clustersortarray[j + 1] = clustersortarray[j];
+						-- j = j - 1;
+					-- }
+					-- clustersortarray[j + 1] = i;
+				-- }
+				if sort_readkey_S='1' then
+					if (results_filled_S='1') and (sort_i_S<=results_write_address_S) then
+						sort_key_S <= results_data_out_S(30+23 downto 30);
+						sort_readkey_S <= '0';
+						sort_j_S <= sort_i_S-1;
+						sort_j_neg_S <= '0';
+						-- results_read_address_S <= clustersortarray_S(sort_i_S-1);
+					else
+						-- results_read_address_S <= clustersortarray_S(sort_i_S);
+						if state_S=SORTING then
+							sort_ready_S <= '1';
+						end if;
+					end if;
+				else
+					if (sort_j_neg_S='0') and (results_data_out_S(30+23 downto 30)>sort_key_S) then
+						-- results_read_address_S <= clustersortarray_S(sort_j_S-1);
+						clustersortarray_S(sort_j_S+1) <= clustersortarray_S(sort_j_S);
+						if sort_j_S>0 then
+							sort_j_S <= sort_j_S-1;
+							sort_j_neg_S <= '0';
+						else
+							sort_j_neg_S <= '1';
+						end if;
+					else
+						-- results_read_address_S <= clustersortarray_S(sort_i_S+1);
+						if sort_j_neg_S='1' then
+							clustersortarray_S(0) <= sort_i_S;
+						else
+							clustersortarray_S(sort_j_S+1) <= sort_i_S;
+						end if;
+						if sort_i_S<2**MAXCLUSTERSBITS-1 then
+							sort_i_S <= sort_i_S+1;
+						else 
+							sort_ready_S <= '1';
+						end if;
+						sort_readkey_S <= '1';
+					end if;
+				end if;
+			when others =>
+		end case;
+		stateprev_S <= state_S;
+	end if;
+end process;
+
+
+process(clock)
+file dfile: text;
+variable l : line;
+variable result_startaddress_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+variable result_nrofhits_V : std_logic_vector(9 downto 0);
+variable result_nrofclusters_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+variable result_nrhits_max_V : std_logic_vector(9 downto 0);
+variable result_Xpad_min_V : std_logic_vector(9 downto 0);
+variable result_Ypad_min_V : std_logic_vector(9 downto 0);
+variable result_Xpad_max_V : std_logic_vector(9 downto 0);
+variable result_Ypad_max_V : std_logic_vector(9 downto 0);
+variable result_diameter_V : std_logic_vector(10 downto 0);
+variable result_positionX_V : std_logic_vector(10 downto 0);
+variable result_positionY_V : std_logic_vector(10 downto 0);
+variable result_nrofhits_max_V : std_logic_vector(9 downto 0);
+variable result_time_max_V : std_logic_vector(23 downto 0);
+variable result_onedge_V : std_logic;
+variable sum_energy_V : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+variable minimal_energy_reached_V : std_logic;
+variable nClusters2_V : integer range 0 to 2**MAXCLUSTERSBITS-1 := 0;
+variable hitidx_write_address_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+variable diameter_V : std_logic_vector(9 downto 0);
+variable overflow_V : std_logic;
+variable pre0_x : std_logic_vector(9 downto 0);
+variable pre1_x : std_logic_vector(9 downto 0);
+variable pre0_y : std_logic_vector(9 downto 0);
+variable pre1_y : std_logic_vector(9 downto 0);
+variable pre_d : std_logic_vector(9 downto 0);
+--variable pre_r : std_logic_vector(9 downto 0);
+variable pre0_t : std_logic_vector(23 downto 0);
+variable pre1_t : std_logic_vector(23 downto 0);
+
+begin
+	if (rising_edge(clock)) then
+		error_S <= '0';
+		nextcluster <= '0';
+		energy_write_S <= '0';
+		neighbours_write_S <= '0';
+		isAdded_write_S <= '0';
+		data_out_write_S <= '0';
+		data_out_first_S <= '0';
+		data_out_last_S <= '0';
+		similarities_write_S <= '0';
+		results_write_S <= '0';
+		hitidx_write_S <= '0';
+		case state_S is
+			when INITIALIZE =>
+				data_first_S <= '0';
+				data_last_S <= '0';
+				nPres_S <= 0;
+				hitcounter_S <= 0;
+				nClusters1_S <= 0;
+				nClusters2_S <= 0;
+				simLength_S <= 0;
+				results_index_S <= 0;
+				last_pre_S <= '0';
+				data_in_onedge_S <= '0';
+				passononecluster_S <= '0';
+				sum_energy_S <= (others => '0');
+				neighbours_size_S <= (others => '0');
+				data_write_address_S <= (others => '0');
+				data_read_nextaddress_S <= (others => '0');
+				hitidx_hitpointer_S <= (others => '0');
+				if (data_in_write='1') and (data_in_first='1') then
+					data_out_S <= data_in;
+					data_first_S <= '1';
+				end if;
+				if (data_in_write='1') and (data_in_last='1') then
+					data_last_S <= '1';
+				end if;
+				if data_in_active='1' then
+					state_S <= COLLECT;
+					if data_in_write_S='1' then
+						data_write_address_S(0) <= '1';
+						hitcounter_S <= conv_integer(unsigned(data_in(CLUSTERBITS-1 downto 0)));
+						if conv_integer(unsigned(data_in(CLUSTERBITS-1 downto 0)))=0 then
+							error_S <= '1';
+							isAdded_data_in_S <= (others => '0');
+							isAdded_write_S <= '1';
+							isAdded_write_address_S <= (others => '0');
+							nextcluster <= '1';
+							data_write_address_S <= (others => '0');
+							state_S <= INITIALIZE;
+						end if;
+						nPres_S <= 1;
+					end if;
+				elsif data_in_write='1' then -- empty superburst
+					if (data_in_first='0') or (data_in_last='0') then
+						error_S <= '1';
+					end if;
+					state_S <= WRITESUPERBURST;
+				end if;
+				overflow_S <= '0';
+				isAdded_data_in_S <= (others => '0');
+				if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then 
+					isAdded_write_S <= '1';
+					isAdded_write_address_S <= isAdded_write_address_S+1;
+				end if;
+			when COLLECT =>
+				pre_i_S <= 0;
+				nNeighbours_S <= (others => '0');
+				data_read_address_i_S <= (others => '0');
+				if (data_in_write='1') and (data_in_first='1') then
+					data_first_S <= '1';
+					data_out_S <= data_in;
+				end if;
+				if (data_in_write='1') and (data_in_last='1') then
+					data_last_S <= '1';
+				end if;
+				if data_in_active='0' then
+					if hitcounter_S/=0 then
+						error_S <= '1';
+						if nPres_S>0 then
+							nPres_S <= nPres_S-1;
+						else
+						end if;
+					end if;
+					if (nPres_S=0) then 
+						isAdded_data_in_S <= (others => '0');
+						isAdded_write_S <= '1';
+						isAdded_write_address_S <= (others => '0');
+						data_write_address_S <= (others => '0');
+						state_S <= INITIALIZE;
+					elsif nPres_S=1 then 
+						if (SKIPSINGLEHITCLUSTERS=TRUE) and (sum_energy_S/=ONES(MINIMUMENERGYBITS-1 downto 0)) then
+							nPres_S <= 0;
+						else 
+							passononecluster_S <= '1';
+						end if;
+						state_S <= WRITESUPERBURST;
+					else
+						data_onedge_S(nPres_S-1) <= data_in_onedge_S;
+						energy_write_address_S <= conv_std_logic_vector(nPres_S-1,CLUSTERBITS);
+						energy_in_S <= data_in_onedge_S & sum_energy_S;
+						energy_write_S <= '1';
+						state_S <= PRE_READ0;
+					end if;
+				else
+					if data_in_write_S='1' then
+						if data_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then
+							data_write_address_S <= data_write_address_S+1;
+						else
+							overflow_S <= '1';
+						end if;
+						if hitcounter_S=0 then
+							hitcounter_S <= conv_integer(unsigned(data_in(CLUSTERBITS-1 downto 0)));
+							if nPres_S>0 then
+								data_onedge_S(nPres_S-1) <= data_in_onedge_S; --//
+								energy_write_address_S <= conv_std_logic_vector(nPres_S-1,CLUSTERBITS);
+								energy_in_S <= data_in_onedge_S & sum_energy_S;
+								energy_write_S <= '1';
+								sum_energy_S <= (others => '0');
+							end if;
+							nPres_S <= nPres_S+1;
+						else
+							if conv_integer(unsigned(data_in(15 downto 0)))+conv_integer(unsigned(sum_energy_S))<conv_integer(unsigned(minimal_energy_S)) then
+								sum_energy_S <= conv_std_logic_vector(conv_integer(unsigned(data_in(15 downto 0)))+conv_integer(unsigned(sum_energy_S)),MINIMUMENERGYBITS);
+							else
+								sum_energy_S <= (others => '1');
+							end if;
+							if data_in_onedge='1' then
+								data_in_onedge_S <= '1';
+							end if;
+							hitcounter_S <= hitcounter_S-1;
+						end if;
+					end if;
+				end if;
+				isAdded_data_in_S <= (others => '0');
+				if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then 
+					isAdded_write_S <= '1';
+					isAdded_write_address_S <= isAdded_write_address_S+1;
+				end if;
+			when PRE_READ0 =>
+				prim_k_S <= 0;
+	-- for (int iClus = 0; iClus < nPres - 1; iClus++) {
+		-- int nNeighbours = 0; // #neighbouring preclusters, reset nNeighbours
+		-- neighbours[neighbours_size++] = 0;
+		-- for (int j = iClus + 1; j < nPres; j++) {
+			-- if ((abs(fPreclusterArray[iClus].Xpos - fPreclusterArray[j].Xpos) <= 1+(fPreclusterArray[iClus].diameter + fPreclusterArray[j].diameter + 1) / 2) && (abs(fPreclusterArray[iClus].time - fPreclusterArray[j].time) <= deltaT)) {
+				-- neighbours[neighbours_size++] = j;
+				-- nNeighbours++;
+			-- }
+		-- }
+		-- neighbours[neighbours_size - (nNeighbours + 1)] = nNeighbours; // write nr of neighbours to the appropiate entry in neighbours2[]
+	-- }
+				neighbours_read_address_S <= (others => '0');
+				precluster0_S <= data_in_S;
+				pre_j_S <= pre_i_S+1;
+				isAdded_data_in_S <= (others => '0');
+				neighbours_write_address_S <= conv_std_logic_vector(conv_integer(unsigned(neighbours_size_S))-(conv_integer(unsigned(nNeighbours_S))+1),CLUSTERBITS+2);
+				neighbours_data_in_S <= nNeighbours_S;
+				if stateprev_S/=COLLECT then
+					neighbours_write_S <= '1';
+				end if;
+				nNeighbours_S <= (others => '0');
+				if last_pre_S='1' then
+					if (neighbours_size_S>0) then
+						neighbours_read_address_S(0) <= '1';
+					end if;
+					state_S <= PRIMARY;
+				else
+					neighbours_size_S <= neighbours_size_S+1;
+					state_S <= PRE_READ1;
+				end if;
+				data_read_address_i_S <= conv_std_logic_vector(conv_integer(unsigned(data_read_address_i_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS);
+				data_read_address_j_S <= conv_std_logic_vector(conv_integer(unsigned(data_read_address_i_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS);
+			when PRE_READ1 =>
+				neighbours_read_address_S <= (others => '0');
+				if pre_j_S<nPres_S-1 then
+					pre_j_S <= pre_j_S+1;
+					data_read_address_j_S <= conv_std_logic_vector(conv_integer(unsigned(data_read_address_j_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS);
+				else
+					if pre_i_S+1>=nPres_S-1 then
+						last_pre_S <= '1';
+					end if;
+					pre_i_S <= pre_i_S+1;
+					state_S <= PRE_READ0;
+				end if;
+				pre0_x := precluster0_S(29 downto 20);
+				pre1_x := data_in_S(29 downto 20);
+				pre0_y := precluster0_S(19 downto 10);
+				pre1_y := data_in_S(19 downto 10);
+				pre_d := precluster0_S(39 downto 30) + data_in_S(39 downto 30);
+				pre0_t := precluster0_S(63 downto 40);
+				pre1_t := data_in_S(63 downto 40);
+				if (((pre0_x>=pre1_x) and (pre0_x-pre1_x <= pre_d)) or ((pre0_x<pre1_x) and (pre1_x-pre0_x <= pre_d))) and 
+				  (((pre0_y>=pre1_y) and (pre0_y-pre1_y <= pre_d)) or ((pre0_y<pre1_y) and (pre1_y-pre0_y <= pre_d))) and 
+				  (((pre0_t>=pre1_t) and (pre0_t-pre1_t <= timedifference)) or ((pre0_t<pre1_t) and (pre1_t-pre0_t <= timedifference))) then
+					neighbours_write_address_S <= neighbours_size_S;
+					neighbours_size_S <= neighbours_size_S+1;
+					nNeighbours_S <= nNeighbours_S+1;
+					neighbours_data_in_S <= conv_std_logic_vector(pre_j_S,CLUSTERBITS);
+					neighbours_write_S <= '1';
+				end if;
+			when PRIMARY =>
+				sec1_i_S <= 0;
+				sec1_m_S <= 0;
+				if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+					isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters1_S,CLUSTERBITS);
+					isAdded_write_address_S <= conv_std_logic_vector(prim_k_S,CLUSTERBITS);
+					isAdded_write_S <= '1';
+					nrofneighbours_S <= conv_integer(unsigned(neighbours_data_out_S));
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+					if conv_integer(unsigned(neighbours_data_out_S))>0 then
+						prim_j_S <= 0;
+						state_S <= PRIMARY1;
+					else
+						prim_k_S <= prim_k_S+1;
+						nClusters1_S <= nClusters1_S+1;						
+					end if;
+				else
+					nrofneighbours_S <= conv_integer(unsigned(neighbours_data_out_S));
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+					if conv_integer(unsigned(neighbours_data_out_S))>0 then
+						prim_j_S <= 0;
+						state_S <= PRIMARY2;
+					else
+						--????
+						prim_k_S <= prim_k_S+1;
+					end if;
+				end if;
+				if (neighbours_read_address_S>=neighbours_size_S) then
+					state_S <= SECONDAIRY;
+				end if;
+			when PRIMARY1 =>
+				prim_m_S <= conv_integer(unsigned(neighbours_data_out_S));
+				if (nrofneighbours_S>1) then
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+				end if;
+				neighbours_data_prev_S <= neighbours_data_out_S;
+				state_S <= PRIMARY1_0;
+			when PRIMARY1_0 =>
+				if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+					isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters1_S,CLUSTERBITS);
+					isAdded_write_address_S <= neighbours_data_prev_S; -- conv_std_logic_vector(prim_m_S,CLUSTERBITS);
+					isAdded_write_S <= '1';
+				elsif conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))/=nClusters1_S then 
+					if nClusters1_S>conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0))) then
+						similarities_data_in_S <= conv_std_logic_vector(nClusters1_S,CLUSTERBITS) & isAdded_data_out_S(CLUSTERBITS-1 downto 0);
+					else
+						similarities_data_in_S <= isAdded_data_out_S(CLUSTERBITS-1 downto 0) & conv_std_logic_vector(nClusters1_S,CLUSTERBITS);
+					end if;
+					similarities_write_S <= '1';
+					similarities_write_address_S <= conv_std_logic_vector(simLength_S,CLUSTERBITS);
+					simLength_S <= simLength_S+1;
+				end if;
+				neighbours_data_prev_S <= neighbours_data_out_S;
+				if prim_j_S+2/=nrofneighbours_S then
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+				end if;
+				if (nrofneighbours_S>1) and (prim_j_S<nrofneighbours_S-1) then
+					prim_j_S <= prim_j_S+1;
+				else
+					nClusters1_S <= nClusters1_S+1;
+					prim_k_S <= prim_k_S+1;
+					state_S <= PRIMARY;
+				end if;
+			when PRIMARY2 =>
+				prim_m_S <= conv_integer(unsigned(neighbours_data_out_S));
+				if (nrofneighbours_S>1) then
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+				end if;
+				isAdded_k_S <= isAdded_data_out_S;
+				neighbours_data_prev_S <= neighbours_data_out_S;
+				state_S <= PRIMARY2_0;
+			when PRIMARY2_0 =>
+				if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+					isAdded_data_in_S <= isAdded_k_S;
+					isAdded_write_address_S <= neighbours_data_prev_S; -- conv_std_logic_vector(prim_m_S,CLUSTERBITS);
+					isAdded_write_S <= '1';
+				elsif isAdded_data_out_S/=isAdded_k_S then --hier verder
+					if isAdded_k_S(CLUSTERBITS-1 downto 0)>isAdded_data_out_S(CLUSTERBITS-1 downto 0) then
+						similarities_data_in_S <= isAdded_k_S(CLUSTERBITS-1 downto 0) & isAdded_data_out_S(CLUSTERBITS-1 downto 0);
+					else
+						similarities_data_in_S <= isAdded_data_out_S(CLUSTERBITS-1 downto 0) & isAdded_k_S(CLUSTERBITS-1 downto 0);
+					end if;
+					similarities_write_S <= '1';
+					similarities_write_address_S <= conv_std_logic_vector(simLength_S,CLUSTERBITS);
+					simLength_S <= simLength_S+1;
+				end if;
+				neighbours_data_prev_S <= neighbours_data_out_S;
+				if prim_j_S+2/=nrofneighbours_S then
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+				end if;
+				if (nrofneighbours_S>1) and (prim_j_S<nrofneighbours_S-1) then
+					prim_j_S <= prim_j_S+1;
+				else
+					prim_k_S <= prim_k_S+1;
+					state_S <= PRIMARY;
+				end if;
+			when SECONDAIRY =>
+				sec1_i_S <= 0;
+				sec1_m_S <= 0;
+				if (isAdded_data_out_S(CLUSTERBITS)='0') then
+					isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters1_S,CLUSTERBITS);
+					isAdded_write_address_S <= conv_std_logic_vector(nPres_S-1,CLUSTERBITS);
+					isAdded_write_S <= '1';
+					nClusters1_S <= nClusters1_S+1;
+				end if;
+				state_S <= SECONDAIRY1;
+			when SECONDAIRY1 =>
+				results_filled_S <= '0';
+				results_write_address_S <= (others => '1');
+				hitidx_write_address_S <= (others => '1');
+				hitidx_write_address_V := (others => '1');
+				result_startaddress_V := (others => '0');
+				result_nrofhits_V := (others => '0');
+				result_nrofclusters_V := (others => '0');
+				result_Xpad_min_V := (others => '1');
+				result_Ypad_min_V := (others => '1');
+				result_Xpad_max_V := (others => '0');
+				result_Ypad_max_V := (others => '0');
+				result_nrhits_max_V := (others => '0');
+				result_time_max_V := (others => '0');
+				result_onedge_V := '0';
+				minimal_energy_reached_V := '0';
+				sum_energy_V := (others => '0');
+				sec1_j_S <= sec1_i_S+1;
+				sec2_i_S <= 0;
+				sec2_n_S <= '0';
+				nClusters2_S <= 0;
+				nClusters2_V := 0;
+				hitidx_hitpointer_S <= (others => '0');
+				if (isAdded_data_out_S(CLUSTERBITS-1 downto 0)=similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)) and
+					(similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0))
+				then -- filled bit not set
+					isAdded_data_in_S <= '1' & similarities_data_out_S(CLUSTERBITS-1 downto 0);
+					isAdded_write_address_S <= conv_std_logic_vector(sec1_m_S,CLUSTERBITS);
+					isAdded_write_S <= '1';
+				end if;
+				if (sec1_m_S<nPres_S-1) and (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) then
+					sec1_m_S <= sec1_m_S+1;
+				else
+					sec1_i_S <= sec1_i_S+1;
+					sec1_m_S <= 0;
+				end if;
+				
+				if (simLength_S=0) or ((sec1_i_S=simLength_S-1) and ((sec1_m_S=nPres_S-1) or 
+						(similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)=similarities_data_out_S(CLUSTERBITS-1 downto 0)))) then
+					sec1_m_S <= 0;
+					state_S <= SECONDAIRY2;
+				elsif (sec1_m_S=nPres_S-1) and 
+					(similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) then
+					similarities_source_S <= similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS);
+					similarities_destination_S <= similarities_data_out_S(CLUSTERBITS-1 downto 0);
+					sec1_m_S <= 0;
+					state_S <= ADJUSTSIMULARITIES;
+				end if;
+			when ADJUSTSIMULARITIES =>
+				similarities_data_in_S <= similarities_data_out_S;
+				similarities_write_address_S <= conv_std_logic_vector(sec1_j_S,CLUSTERBITS);
+				if similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)=similarities_source_S then
+					similarities_data_in_S(CLUSTERBITS*2-1 downto CLUSTERBITS) <= similarities_destination_S;
+					similarities_write_S <= '1';
+				end if;
+				if similarities_data_out_S(CLUSTERBITS-1 downto 0)=similarities_source_S then
+					similarities_data_in_S(CLUSTERBITS-1 downto 0) <= similarities_destination_S;
+					similarities_write_S <= '1';
+				end if;
+				if sec1_j_S<simLength_S-1 then
+					sec1_j_S <= sec1_j_S+1;
+				else
+					sec1_j_S <= sec1_i_S+1;
+					state_S <= SECONDAIRY1;
+				end if;				
+			when SECONDAIRY2 =>
+				overflow_V := '0';
+				results_index_S <= 0;
+				if conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S then 
+					sec2_n_S <= '1';
+					isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters2_S,CLUSTERBITS);
+					isAdded_write_address_S <= conv_std_logic_vector(sec1_m_S,CLUSTERBITS);
+					isAdded_write_S <= '1';
+				end if;
+				if (nClusters1_S>0) then
+					if sec1_m_S<nPres_S-1 then
+						sec1_m_S <= sec1_m_S+1;
+						-- data_read_address_S <= hitidx_hitpointer_S+data_in_S(9 downto 0)+1
+						hitidx_hitpointer_S <= conv_std_logic_vector(conv_integer(unsigned(hitidx_hitpointer_S))+conv_integer(unsigned(data_in_S(9 downto 0)))+1,CLUSTERBITS);
+					else
+						-- data_read_address_S <= (others => '0');
+						hitidx_hitpointer_S <= (others => '0');
+						sec1_m_S <= 0;
+						sec2_i_S <= sec2_i_S+1;
+						if (sec2_n_S='1') or (conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S) then
+							if nClusters2_S<2**MAXCLUSTERSBITS-1 then
+								nClusters2_S <= nClusters2_S+1;
+							else
+								error_S <= '1';
+							end if;
+						end if;
+						sec2_n_S <= '0';
+					end if;
+				end if;
+				
+				if conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S then
+					result_nrofhits_V := result_nrofhits_V+data_in_S(9 downto 0);
+					result_nrofclusters_V := result_nrofclusters_V+1;
+					diameter_V := data_in_S(39 downto 30);
+					if data_in_S(29 downto 20)>diameter_V then
+						if data_in_S(29 downto 20)-diameter_V<=result_Xpad_min_V then 
+							result_Xpad_min_V := data_in_S(29 downto 20)-diameter_V;
+						end if;
+					else
+						result_Xpad_min_V := (others => '0');
+					end if;
+					if data_in_S(19 downto 10)>diameter_V then
+						if data_in_S(19 downto 10)-diameter_V<=result_Ypad_min_V then 
+							result_Ypad_min_V := data_in_S(19 downto 10)-diameter_V;
+						end if;
+					else
+						result_Ypad_min_V := (others => '0');
+					end if;
+					if data_in_S(29 downto 20)+diameter_V>result_Xpad_max_V then 
+						result_Xpad_max_V := data_in_S(29 downto 20)+diameter_V;
+					end if;
+					if data_in_S(19 downto 10)+diameter_V>result_Ypad_max_V then 
+						result_Ypad_max_V := data_in_S(19 downto 10)+diameter_V;
+					end if;
+					if data_in_S(9 downto 0)>result_nrhits_max_V then
+						result_nrhits_max_V := data_in_S(9 downto 0);
+						result_time_max_V := data_in_S(63 downto 40);
+					end if;
+					if data_onedge_S(sec1_m_S)='1' then
+						result_onedge_V := '1';
+					end if;
+					if (minimal_energy_reached_V='0') and (conv_integer(unsigned(sum_energy_V))+conv_integer(unsigned(energy_out_S(MINIMUMENERGYBITS-1 downto 0)))<conv_integer(unsigned(minimal_energy_S))) then
+						sum_energy_V := sum_energy_V+energy_out_S(MINIMUMENERGYBITS-1 downto 0);
+					else
+						minimal_energy_reached_V := '1';
+					end if;
+					hitidx_data_in_S <= data_read_address_prev_S;
+					hitidx_write_address_S <= hitidx_write_address_S+1;
+					hitidx_write_address_V := hitidx_write_address_S+1;
+					hitidx_write_S <='1';
+				end if;
+				if (nClusters1_S>0) then
+					if sec1_m_S<nPres_S-1 then
+					else
+						if (sec2_n_S='1') or (conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S) 
+--						or
+--							((sec2_i_S=nClusters1_S-1) and (sec1_m_S=nPres_S-1)) 
+							then
+							if result_Xpad_max_V-result_Xpad_min_V>result_Ypad_max_V-result_Ypad_min_V then
+								result_diameter_V := ('0' & result_Xpad_max_V)-('0' & result_Xpad_min_V);
+							else
+								result_diameter_V := ('0' & result_Ypad_max_V)-('0' & result_Ypad_min_V);
+							end if;
+							result_diameter_S <= result_diameter_V(10 downto 1); 
+							result_time_S <= result_time_max_V;
+							result_positionX_V := ('0'&result_Xpad_min_V)+('0'&result_Xpad_max_V);
+							result_positionX_S <= result_positionX_V(10 downto 1);
+							result_positionY_V := ('0'&result_Ypad_min_V)+('0'&result_Ypad_max_V);
+							result_positionY_S <= result_positionY_V(10 downto 1);
+							result_nrofhits_S <= result_nrofhits_V;
+							result_onedge_S <= result_onedge_V;
+							results_data_in_S <= result_startaddress_V & result_nrofhits_V & result_time_max_V & result_diameter_V(10 downto 1) & result_positionX_V(10 downto 1) & result_positionY_V(10 downto 1);
+							if (result_onedge_V='1') or (SKIPSINGLEHITCLUSTERS=FALSE) or (minimal_energy_reached_V='1') then -- or (result_nrofhits_V>1) 
+								results_write_S <= '1';
+								if (conv_integer(unsigned(results_write_address_S))<(2**MAXCLUSTERSBITS-1)) or (results_filled_S='0') then --// and (sec1_i_S<31) then
+									results_write_address_S <= results_write_address_S+1;
+								else 
+									overflow_V := '1';
+								end if;
+								results_filled_S <= '1';
+								result_startaddress_V := hitidx_write_address_V+1;
+								if nClusters2_V<2**MAXCLUSTERSBITS-1 then
+									nClusters2_V := nClusters2_V+1;
+								end if;
+							else
+if conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))/=sec2_i_S then
+								hitidx_write_address_S <= hitidx_write_address_V-result_nrofclusters_V;
+end if;
+							end if;
+						end if;
+						result_nrofhits_V := (others => '0');
+						result_nrofclusters_V := (others => '0');
+						result_Xpad_min_V := (others => '1');
+						result_Ypad_min_V := (others => '1');
+						result_Xpad_max_V := (others => '0');
+						result_Ypad_max_V := (others => '0');
+						result_nrhits_max_V := (others => '0');
+						result_time_max_V := (others => '0');
+						result_onedge_V := '0';
+						minimal_energy_reached_V := '0';
+						sum_energy_V := (others => '0');
+					end if;
+				end if;
+
+				if ((sec2_i_S=nClusters1_S-1) and (sec1_m_S=nPres_S-1)) or (nClusters1_S=0) then
+					nPres_S <= nClusters2_V;
+					if (nClusters2_V<=1) then
+						hitidx_hitpointer_S <= (others => '0');
+						nClusters2_S <= nClusters2_V;
+						state_S <= WRITESUPERBURST;
+					else
+						nClusters2_S <= nClusters2_V;
+						state_S <= SORTING;
+					end if;
+				elsif overflow_V='1' then
+					nPres_S <= nClusters2_V;
+					error_S <= '1';
+					overflow_S <= '1';
+					state_S <= SORTING;
+				end if;
+			when SORTING =>
+				hitidx_hitpointer_S <= (others => '0');
+				results_index_S <= 0;
+				if sort_ready_S='1' then
+					state_S <= WRITESUPERBURST;
+				end if;
+--				if (((sort_readkey_S='0') and (sort_i_S>=results_write_address_S-1)) and 
+--						((sort_j_neg_S='1') or (results_data_out_S(30+23 downto 30)<=sort_key_S))) or
+--					((sort_readkey_S='1') and (sort_i_S>=results_write_address_S) and (stateprev_S/=SECONDAIRY2)) then
+--					state_S <= WRITESUPERBURST;
+--				end if;
+			when WRITESUPERBURST => 
+				-- results_read_address_S <= clustersortarray_S(0)
+				hitidx_hitpointer_S <= (others => '0');
+				sec1_m_S <= 0;
+				results_index_S <= 0;
+				if (data_out_clusterallowed='1') then
+					data_out_first_S <= data_first_S;
+					data_out_write_S <= data_first_S;
+					if (nPres_S=0) then
+						data_out_last_S <= data_last_S;
+						isAdded_data_in_S <= (others => '0');
+						isAdded_write_S <= '1';
+						isAdded_write_address_S <= (others => '0');
+						nextcluster <= '1';
+						data_write_address_S <= (others => '0');
+						state_S <= INITIALIZE;
+					elsif (passononecluster_S='1') then
+						state_S <= WRITEONECLUSTER;
+						hitidx_hitpointer_S <= hitidx_hitpointer_S+1;
+					else
+						state_S <= WRITECLUSTER;
+					end if;
+				end if;
+			when WRITEONECLUSTER => 
+				-- data_read_address_S <= data_read_address_S+1;
+				data_out_S <= data_in_S(63 downto 0);
+				data_out_write_S <= '1';
+				hitidx_nrofprehits_S <= conv_integer(unsigned(data_in_S(9 downto 0)));
+				hitidx_hitpointer_S <= hitidx_hitpointer_S+1;
+				state_S <= WRITEONECLUSTERHITS;
+			when WRITEONECLUSTERHITS => 
+				-- data_read_address_S <= data_read_address_S+1;
+				data_write_address_S <= (others => '0');
+				data_out_S <= data_in_S(63 downto 0);
+				data_out_write_S <= '1';
+				hitidx_hitpointer_S <= hitidx_hitpointer_S+1;
+				if hitidx_nrofprehits_S>1 then
+					hitidx_nrofprehits_S <= hitidx_nrofprehits_S-1;
+				else
+					if data_last_S='1' then
+						data_out_last_S <= '1';
+					end if;
+					isAdded_data_in_S <= (others => '0');
+					isAdded_write_S <= '1';
+					isAdded_write_address_S <= (others => '0');
+					nextcluster <= '1';
+					data_write_address_S <= (others => '0');
+					state_S <= INITIALIZE;
+				end if;
+			when WRITECLUSTER => -- results_data_out_S available
+				-- data_read_address_S <= hitidx_data_out_S;
+				-- results_read_address_S <= clustersortarray_S(results_index_S)
+				-- hitidx_read_address_S <= results_data_out_S(CLUSTERBITS+63 downto 64);
+				if results_index_S<2**MAXCLUSTERSBITS-1 then
+					results_index_S <= results_index_S+1;
+				end if;
+				data_out_S <= (others => '0');
+				data_out_S(63 downto 40) <= results_data_out_S(53 downto 30); -- time 24 bits
+				data_out_S(39 downto 30) <= results_data_out_S(29 downto 20); -- diameter 10bits
+				data_out_S(29 downto 20) <= results_data_out_S(19 downto 10); -- X 10bits
+				data_out_S(19 downto 10) <= results_data_out_S(9 downto 0); -- Y 10bits
+				data_out_S(9 downto 0) <= results_data_out_S(63 downto 54); -- number of hits 10bits
+				data_out_write_S <= '1';
+				hitidx_nrofhits_S <= conv_integer(unsigned(results_data_out_S(63 downto 54)));
+				hitidx_index_S <= conv_integer(unsigned(results_data_out_S(CLUSTERBITS+63 downto 64)));
+				state_S <= WRITEHITS0;
+			when WRITEHITS0 => -- hitidx_data_out_S available
+				-- data_read_address_S <= hitidx_data_out_S;
+				-- results_read_address_S <= clustersortarray_S(results_index_S)
+				-- hitidx_read_address_S <= hitidx_index_S;
+				hitidx_hitpointer_S <= hitidx_data_out_S+1;
+				hitidx_index_S <= hitidx_index_S+1;
+				state_S <= WRITEHITS1;
+			when WRITEHITS1 => -- clusterdata available
+				-- data_read_address_S <= hitidx_hitpointer_S;
+				-- results_read_address_S <= clustersortarray_S(results_index_S)
+				-- hitidx_read_address_S <= hitidx_index_S;
+				hitidx_hitpointer_S <= hitidx_hitpointer_S+1;
+				if conv_integer(unsigned(data_in_S(9 downto 0)))>0 then
+					hitidx_nrofprehits_S <= conv_integer(unsigned(data_in_S(9 downto 0)));
+				else
+					hitidx_nrofprehits_S <= 1;
+				end if;
+				state_S <= WRITEHITS;
+			when WRITEHITS =>
+				-- data_read_address_S <= hitidx_hitpointer_S;
+				-- results_read_address_S <= clustersortarray_S(results_index_S)
+				-- hitidx_read_address_S <= hitidx_index_S;
+				hitidx_hitpointer_S <= hitidx_hitpointer_S+1;
+				data_out_S <= data_in_S(63 downto 0);
+				data_out_write_S <= '1';
+				if hitidx_nrofprehits_S>1 then
+					hitidx_nrofprehits_S <= hitidx_nrofprehits_S-1;
+				else
+					if hitidx_nrofhits_S>1 then
+						hitidx_hitpointer_S <= hitidx_data_out_S+1;
+						hitidx_index_S <= hitidx_index_S+1;
+						-- data_read_address_S <= hitidx_data_out_S;
+						-- hitidx_read_address_S <= hitidx_index_S+1;
+						state_S <= WRITEHITS1;
+					else -- all hits in output cluster processed
+						if results_index_S<nClusters2_S then
+							state_S <= WRITECLUSTER;
+						else
+							if data_last_S='1' then
+								data_out_last_S <= '1';
+							end if;
+							isAdded_data_in_S <= (others => '0');
+							isAdded_write_S <= '1';
+							isAdded_write_address_S <= (others => '0');
+							nextcluster <= '1';
+							data_write_address_S <= (others => '0');
+							state_S <= INITIALIZE;
+						end if;
+					end if;
+				end if;
+				hitidx_nrofhits_S <= hitidx_nrofhits_S-1;
+			when others =>
+				data_write_address_S <= (others => '0');
+				state_S <= INITIALIZE;
+		end case;
+		if reset='1' then 
+			data_first_S <= '0';
+			data_last_S <= '0';
+			isAdded_data_in_S <= (others => '0');
+			isAdded_write_S <= '1';
+			isAdded_write_address_S <= (others => '0');
+			data_write_address_S <= (others => '0');
+			state_S <= INITIALIZE;
+		end if;
+		data_read_address_prev_S <= data_read_address_S;
+		debug_minimal_energy_reached_S <= minimal_energy_reached_V;
+		debug_sum_energy_S <= sum_energy_V;
+	end if;
+end process;
+
+data_out_write <= data_out_write_S;
+data_out_last <= '1' when (data_out_last_S='1') and (data_out_write_S='1') else '0';
+data_out_first <= '1' when (data_out_first_S='1') and (data_out_write_S='1') else '0';
+data_out <= data_out_S;
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0) := (others => '0');
+variable clusterresult_V : std_logic := '0';
+variable same_superburst_V : std_logic := '0';
+variable nrofhits_V : std_logic_vector(9 downto 0) := (others => '0');
+variable hitscounter_V : std_logic_vector(9 downto 0) := (others => '0');
+variable prev_resulttime_V : std_logic_vector(23 downto 0) := (others => '0');
+variable prev_hittime_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+	if (rising_edge(clock)) then
+		debug_error_S <= '0';
+		if data_out_write_S='1' then
+			if data_out_first_S='1' then
+				if data_out_S(30 downto 0) < prev_superburst_V then
+					debug_error_S <= '1';
+				end if;
+				if data_out_S(30 downto 0)=prev_superburst_V then
+					same_superburst_V := '1';
+				else
+					same_superburst_V := '0';
+				end if;
+				prev_superburst_V := data_out_S(30 downto 0);
+				clusterresult_V := '1';
+			elsif clusterresult_V='1' then
+				if hitscounter_V/=nrofhits_V then
+					debug_error_S <= '1';
+				end if;
+				nrofhits_V := data_out_S(9 downto 0);
+				if (same_superburst_V='1') and (prev_resulttime_V>data_out_S(63 downto 40)) then
+					debug_error_S <= '1';
+				end if;
+				same_superburst_V := '1';
+				prev_resulttime_V := data_out_S(63 downto 40);
+				hitscounter_V := (others => '0');
+				prev_hittime_V := (others => '0');
+				clusterresult_V := '0';
+			else
+				if data_out_last_S='1' then
+					if hitscounter_V/=nrofhits_V-1 then
+						debug_error_S <= '1';
+					end if;
+				end if;
+				if data_out_S(63 downto 40)<prev_hittime_V then
+--					debug_error_S <= '1';
+				end if;
+				prev_hittime_V := data_out_S(63 downto 40);
+				if hitscounter_V=nrofhits_V-1 then
+					clusterresult_V := '1';
+				end if;
+				hitscounter_V := hitscounter_V+1;
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if state_S=INITIALIZE then
+			nrofclocks_S <= 0;
+		else
+			nrofclocks_S <= nrofclocks_S+1;
+		end if;
+	end if;
+end process;
+
+--process(clock)
+--begin
+--	if (rising_edge(clock)) then
+--		if isAdded_write_S='1' then
+--			if isAdded_data_in_S(CLUSTERBITS)='0' then
+--				debug_isAdded_S(conv_integer(unsigned(isAdded_write_address_S))) <= -1;
+--			else
+--				debug_isAdded_S(conv_integer(unsigned(isAdded_write_address_S))) <= conv_integer(unsigned(isAdded_data_in_S(CLUSTERBITS-1 downto 0)));
+--			end if;
+--		end if;
+--	end if;
+--end process;
+--
+--process(clock)
+--begin
+--	if (rising_edge(clock)) then
+--		if similarities_write_S='1' then
+--			similarities_s(conv_integer(unsigned(similarities_write_address_S))*2) <= similarities_data_in_S(CLUSTERBITS*2-1 downto CLUSTERBITS);
+--			similarities_s(conv_integer(unsigned(similarities_write_address_S))*2+1) <= similarities_data_in_S(CLUSTERBITS-1 downto 0);
+--		end if;
+--	end if;
+--end process;
+
+--testword0(4 downto 0) <=
+testword0(115 downto 111) <=
+	"00000" when state_S=INITIALIZE else
+	"00001" when state_S=COLLECT else
+	"00010" when state_S=PRE_READ0 else
+	"00011" when state_S=PRE_READ1 else
+	"00100" when state_S=PRIMARY else
+	"00101" when state_S=PRIMARY1 else
+	"00110" when state_S=PRIMARY1_0 else
+	"00111" when state_S=PRIMARY2 else
+	"01000" when state_S=PRIMARY2_0 else
+	"01001" when state_S=SECONDAIRY else
+	"01010" when state_S=SECONDAIRY1 else
+	"01011" when state_S=ADJUSTSIMULARITIES else
+	"01100" when state_S=SECONDAIRY2 else
+	"01101" when state_S=SORTING else
+	"01110" when state_S=WRITESUPERBURST else
+	"01111" when state_S=WRITEONECLUSTER else
+	"10000" when state_S=WRITEONECLUSTERHITS else
+	"10001" when state_S=WRITECLUSTER else
+	"10010" when state_S=WRITEHITS0 else
+	"10011" when state_S=WRITEHITS1 else
+	"10100" when state_S=WRITEHITS else
+	"11111";
+--testword0(5) <= data_in_write;
+--testword0(6) <= error_S;
+--testword0(7) <= data_out_clusterallowed;
+
+testword0(63 downto 0) <= data_in;
+testword0(64) <= data_in_first;
+testword0(65) <= data_in_last;
+testword0(66) <= data_in_write;
+testword0(67) <= data_in_active;
+testword0(68) <= data_in_onedge;
+testword0(79 downto 70) <= conv_std_logic_vector(sec2_i_S,10);
+testword0(89 downto 80) <= conv_std_logic_vector(nClusters1_S,10);
+testword0(99 downto 90) <= conv_std_logic_vector(sec1_m_S,10);
+testword0(109 downto 100) <= conv_std_logic_vector(nPres_S,10);
+
+testword0(116) <= error_S;
+testword0(MAXCLUSTERSBITS+116 downto 117) <= results_write_address_S;
+
+end behaviour;
+
diff --git a/data_concentrator/sources/cluster/CN_cluster_findgap.vhd b/data_concentrator/sources/cluster/CN_cluster_findgap.vhd
new file mode 100644
index 0000000..71e167f
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_cluster_findgap.vhd
@@ -0,0 +1,419 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   19-08-2016
+-- Module Name:   CN_cluster_findgap
+-- Description:   Breaks stream of (pre-)clusters into timebunches
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_cluster_findgap
+-- Breaks stream of (pre-)clusters into timebunches.
+-- If the time between two clusters is larger than the specified gap time, or if a new superburst starts,
+-- then an output signal indicates that the next timebuch is starting.
+-- An on-edge signal is added to the data to indicate if the crystal is on the edge of the region that this module is processing.
+-- The module can be configured to process either SODAnet packets, or superburst packets without any preceding header.
+--
+-- The 64 bits packets, according to SODAnet specs:
+-- 64bits word0: (only if HEADERWORD0 is set to TRUE)
+--        bit63      = last-packet flag
+--        bit62..48  = packet number
+--        bit47..32  = data size in bytes
+--        bit31..0   = Not used (same as HADES)
+-- 64bits word1:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+-- for cluster data, for each cluster
+-- 64bits word2, clusterresults
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..30  = diameter
+--        bit29..20  = Y position, multiplied by 2
+--        bit19..10  = X position, multiplied by 2
+--        bit9..0    = number of hits in cluster
+-- 64bits word3..word3+nrofhits : pulse data
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+-- Library
+--
+-- generics:
+--      HEADERWORD0 : true : process SODAnet packet, false process packet with first word containing superburstnumber
+-- 
+-- Inputs:
+--      clock : clock
+--      reset : reset
+--      gap_time : maximum gap time between clusters, resolutie from Constant Fraction (6.1ps)
+--      onedgeLUT_write : write signal for on-edge Look Up Table
+--      onedgeLUT_load : when '1' the LUT can be loaded with values, on '0' the writing address is set back to zero
+--      onedgeLUT_data : loading data for the LUT: 'on edge'
+--      data_in : 64bits data
+--      data_in_first : indicates that 64bits data is first in a packet
+--      data_in_last : indicates that 64bits data is last in packet
+--      data_in_write : write signal for 64bits data
+--      data_out_allowed : allowed to write output data
+-- 
+-- Outputs:
+--      data_in_allowed : allow input data to be written
+--      data_out : 64 bits output data
+--      data_out_onedge : the hit in the output data is positioned on the edge of the Data Concentrator region
+--      data_out_active : timebunch active
+--      data_out_nexttimebunch : actual and further output data belongs to new timebunch
+--      data_out_write : write signal for 64 bits / XY and on-edge output data
+--      data_out_first : 64 bits output data contains new superburst
+--      data_out_last : 64 bits output data is the last data of a superburst
+--      superburst_rewind : new superburstnumber is lower than previous
+--      dataerror : error in data
+-- 
+-- Components:
+--      CN_cluster_onedge_LUT :  memory block for on-edge Look Up Table
+--
+----------------------------------------------------------------------------------
+
+entity CN_cluster_findgap is
+	generic(
+		HEADERWORD0             : boolean := TRUE   
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		gap_time                : in std_logic_vector(23 downto 0);
+		onedgeLUT_write         : in std_logic;
+		onedgeLUT_load          : in std_logic;
+		onedgeLUT_data          : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_onedge         : out std_logic;
+		data_out_active         : out std_logic;
+		data_out_nexttimebunch  : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_allowed        : in std_logic;
+		superburst_rewind       : out std_logic;
+		dataerror               : out std_logic
+	); 
+end CN_cluster_findgap;
+
+
+architecture behaviour of CN_cluster_findgap is
+
+component CN_cluster_onedge_LUT is
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(15 downto 0);
+		data_in                 : in std_logic;
+		read_address            : in std_logic_vector(15 downto 0);
+		data_out                : out std_logic
+	);
+end component;
+
+signal timeoutcount_S           : std_logic_vector(11 downto 0);
+signal data_in_write_S          : std_logic;
+signal data_in_allowed_S        : std_logic;
+
+signal dataerror1_S             : std_logic := '0';
+signal wave_S                   : std_logic := '0';
+signal new_superburst_S         : std_logic := '0';
+signal time_S                   : std_logic_vector(23 downto 0);
+signal prev_suberburst_S        : std_logic_vector(30 downto 0) := (others => '0');
+signal packetsize_S             : integer range 0 to 65535;
+signal data_in_count_S          : integer range 0 to 65535;
+signal waitforfirst_S           : std_logic := '1';
+
+signal expectfirst_S            : std_logic := '1';
+signal expect_resultword_S      : std_logic := '1';
+signal nrofhits_S               : std_logic_vector(9 downto 0);
+signal hitscounter_S            : std_logic_vector(9 downto 0);
+
+signal data_out_nextbunch_S     : std_logic;
+signal data_out_nextbunch0_S    : std_logic := '0';
+
+signal data_out_allowed_S       : std_logic := '0';
+signal data_out_active_S        : std_logic := '0';
+signal data_out_write_S         : std_logic := '0';
+signal data_out_first_S         : std_logic := '0';
+signal data_out_last_S          : std_logic := '0';
+signal data_out_write0_S        : std_logic := '0';
+
+signal onedgeLUT_loadaddress_S  : std_logic_vector(15 downto 0) := (others => '0');
+signal onedgeLUT_data_S         : std_logic;
+signal onedgeLUT_data0_S        : std_logic;
+
+begin
+
+dataerror <= '1' when (dataerror1_S='1') else '0';
+data_in_allowed_S <= '1' when (data_out_allowed='1') else '0';
+data_in_allowed <= data_in_allowed_S;
+data_out_write <= '1' when (data_out_write_S='1') and (data_out_allowed='1') else '0';
+data_out_first <= '1' when (data_out_first_S='1') and (data_out_allowed='1') else '0';
+data_out_last <= '1' when (data_out_last_S='1') and (data_out_allowed='1') else '0';
+data_in_write_S <= '1' when (data_in_write='1') and (data_in_allowed_S='1') else '0';
+
+data_out_active <= data_out_active_S;
+data_out_nexttimebunch <= data_out_nextbunch_S;
+
+-- Look Up Table for position of hits near edge of region
+LUT1: CN_cluster_onedge_LUT port map(
+		clock => clock,
+		write_enable => onedgeLUT_write,
+		write_address => onedgeLUT_loadaddress_S,
+		data_in => onedgeLUT_data,
+		read_address => data_in(31 downto 16),
+		data_out => onedgeLUT_data_S);
+data_out_onedge <= onedgeLUT_data0_S when (data_out_allowed_S='0') and (data_out_allowed='1') else onedgeLUT_data_S;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if onedgeLUT_load='1' then
+			if onedgeLUT_write='1' then 
+				onedgeLUT_loadaddress_S <= onedgeLUT_loadaddress_S+1;
+			end if;
+		else
+			onedgeLUT_loadaddress_S <= (others => '0');
+		end if;
+		if data_out_write0_S='1' then
+			onedgeLUT_data0_S <= onedgeLUT_data_S;
+		end if;
+		data_out_allowed_S <= data_out_allowed;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		data_out_allowed_S <= data_out_allowed;
+	end if;
+end process;
+		
+		
+-- input data handling process
+process(clock)
+variable prev_suberburst_V : std_logic_vector(30 downto 0);
+begin
+	if (rising_edge(clock)) then
+		dataerror1_S <= '0';
+		superburst_rewind <= '0';
+		data_out_nextbunch_S <= '0';
+		data_out_write_S <= '0';
+		data_out_write0_S <= '0';
+		data_out_first_S <= '0';
+		data_out_last_S <= '0';
+		if reset='1' then
+			waitforfirst_S <= '1';
+			data_out_nextbunch0_S <='0';
+			new_superburst_S <= '0';
+			data_out_active_S <= '0';
+			data_out_last_S <= '0'; 
+			data_out_first_S <= '0'; 
+			expectfirst_S <= '1';
+			expect_resultword_S <= '0'; 
+			prev_suberburst_S <= (others => '0');
+		else
+			if (data_out_write_S='1') and (data_out_allowed='1') and (data_out_last_S='1') then
+				data_out_active_S <= '0';
+			end if;
+			if (data_out_nextbunch_S='1') and (data_out_allowed='0') then
+	--//			data_out_nextbunch_S <= '1'; -- retry
+			end if;		
+			if (data_out_write_S='1') and (data_out_allowed='0') then
+				data_out_write_S <= '1'; -- retry;
+				data_out_last_S <= data_out_last_S;
+				data_out_first_S <= data_out_first_S;
+			else
+				if data_out_nextbunch0_S='1' then
+					data_out_nextbunch_S <= '1';
+					data_out_nextbunch0_S <='0';
+				end if;
+			end if;
+			if (data_in_write_S='1') then
+				timeoutcount_S <= (others => '0');
+				if (data_in_first='1') then
+					waitforfirst_S <= '0';
+					data_in_count_S <= 1;
+					data_out_active_S <= '0';
+					time_S <= (others => '0');
+					if expectfirst_S='0' then
+						dataerror1_S <= '1';
+					end if;
+					if new_superburst_S='0' then
+						data_out_nextbunch_S <= '1';
+					end if;
+					new_superburst_S <= '1';
+					if (HEADERWORD0=TRUE) then
+						if data_in(63)='0' then
+							dataerror1_S <= '1';
+						end if;
+						packetsize_S <= conv_integer(unsigned(data_in(47 downto 32)));
+						if data_in(31 downto 0)/=x"00000000" then
+							dataerror1_S <= '1';
+						end if;
+					else
+						prev_suberburst_V := prev_suberburst_S+1;
+						if (data_in(30 downto 0)/=prev_suberburst_V) and (conv_integer(unsigned(prev_suberburst_S))/=0) then
+							dataerror1_S <= '1';
+						end if;
+						if prev_suberburst_S>data_in(30 downto 0) then
+							superburst_rewind <= '1';
+						end if;
+						prev_suberburst_S <= data_in(30 downto 0);
+						data_out <= data_in;
+						data_out_write_S <= '1';
+						data_out_first_S <= '1';
+						if (data_in_last='1') then -- empty superburst
+							data_out_last_S <= '1';
+							data_out_nextbunch0_S <= '1';
+							expect_resultword_S <= '0';
+							expectfirst_S <= '1';
+						else
+							data_out_active_S <= '1';
+							expect_resultword_S <= '1';
+							expectfirst_S <= '0';
+						end if;
+					end if;
+				elsif (HEADERWORD0=TRUE) and (data_in_count_S=1) and (waitforfirst_S='0') then
+					data_out_active_S <= '0';
+					prev_suberburst_V := prev_suberburst_S+1;
+					if (data_in(30 downto 0)/=prev_suberburst_V) and (conv_integer(unsigned(prev_suberburst_S))/=0) then
+						dataerror1_S <= '1';
+					end if;
+					if prev_suberburst_S>data_in(30 downto 0) then
+						superburst_rewind <= '1';
+					end if;
+					prev_suberburst_S <= data_in(30 downto 0);
+					data_out <= data_in;
+					data_out_first_S <= '1';
+					time_S <= (others => '0');
+					if (data_in_last='1') then -- empty superburst
+						data_out_last_S <= '1';
+						data_out_write_S <= '1';
+						data_out_nextbunch0_S <= '1';
+						expect_resultword_S <= '0';
+						expectfirst_S <= '1';
+					else
+						data_out_active_S <= '1';
+						expect_resultword_S <= '1';
+						expectfirst_S <= '0';
+					end if;
+					if data_in_last='1' then
+						if packetsize_S/=(data_in_count_S+1)*8 then
+							dataerror1_S <= '1';
+						end if;
+					end if;
+					data_in_count_S <= data_in_count_S+1;
+				elsif (expect_resultword_S='1') and (waitforfirst_S='0') then
+					data_out_active_S <= '1';
+					if data_in(63 downto 40) < time_S(23 downto 0) then
+						dataerror1_S <= '1';
+					end if;
+					time_S <= data_in(63 downto 40);
+					nrofhits_S <= data_in(9 downto 0);
+					hitscounter_S <= (others => '0');
+					if conv_integer(unsigned(data_in(9 downto 0)))=0 then
+						dataerror1_S <= '1';
+						if data_in_last='1' then
+							expectfirst_S <= '1';
+							expect_resultword_S <= '0';
+						else
+							expectfirst_S <= '0';
+							expect_resultword_S <= '1';
+						end if;
+					else
+						if data_in_last='1' then
+							dataerror1_S <= '1';
+							expectfirst_S <= '1';
+							expect_resultword_S <= '0';
+						else
+							expectfirst_S <= '0';
+							expect_resultword_S <= '0';
+						end if;
+					end if;
+					if (new_superburst_S='1') or ('0' & data_in(63 downto 40))>('0' & time_S) + ('0' & gap_time) then
+						if (new_superburst_S='0') then
+							data_out_nextbunch_S <= '1';
+						end if;
+						new_superburst_S <= '0';
+						data_out <= data_in;
+						data_out_last_S <= data_in_last;
+						data_out_write_S <= '1';
+						data_out_write0_S <= '1';
+					else
+						data_out <= data_in;
+						data_out_last_S <= data_in_last;
+						data_out_write_S <= '1';
+						data_out_write0_S <= '1';
+					end if;
+					data_in_count_S <= data_in_count_S+1;
+				elsif waitforfirst_S='0' then
+					if hitscounter_S>=nrofhits_S-1 then
+						if data_in_last='1' then
+							expectfirst_S <= '1';
+							expect_resultword_S <= '0';
+						else
+							expectfirst_S <= '0';
+							expect_resultword_S <= '1';
+						end if;
+					else
+						if data_in_last='1' then
+							dataerror1_S <= '1';
+							expectfirst_S <= '1';
+							expect_resultword_S <= '0';
+						else
+							expectfirst_S <= '0';
+							expect_resultword_S <= '0';
+						end if;
+					end if;
+					data_out <= data_in;
+					data_out_last_S <= data_in_last;
+					data_out_write_S <= '1';
+					data_out_write0_S <= '1';
+					if (HEADERWORD0=TRUE) and (data_in_last='1') then
+						if packetsize_S/=(data_in_count_S+1)*8 then
+							dataerror1_S <= '1';
+						end if;
+					end if;
+					hitscounter_S <= hitscounter_S+1;
+					data_in_count_S <= data_in_count_S+1;
+				end if;
+			else
+				if (data_out_active_S='1') then
+					if (timeoutcount_S(timeoutcount_S'left)='0')  then
+						if data_out_allowed='1' then
+							timeoutcount_S <= timeoutcount_S+1;
+						end if;
+					else
+						data_out_nextbunch_S <= '1';
+						data_out_active_S <= '0';
+		--					superburst_rewind <= '1';
+						timeoutcount_S <= (others => '0');
+					end if;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+			
+
+
+
+end behaviour;
+
diff --git a/data_concentrator/sources/cluster/CN_cluster_onedge_LUT.vhd b/data_concentrator/sources/cluster/CN_cluster_onedge_LUT.vhd
new file mode 100644
index 0000000..f7e1d94
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_cluster_onedge_LUT.vhd
@@ -0,0 +1,68 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   31-01-2012
+-- Module Name:   CN_cluster_onedge_LUT
+-- Description:   Look Up Table for on-edge indication
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- CN_cluster_onedge_LUT
+--		Look Up Table for bit that indicates if the crystal is on the edge of the region.
+--
+--
+-- generics
+--    ADDRESS_BITS : Number of bits for the address
+--    DATA_BITS : number of bits for data
+--		
+-- inputs
+--		clock : clock 
+--		write_enable : write to memory
+--		write_address : address to write to
+--		data_in : data to write into memory
+--		read_address : address to read from
+--			  
+-- outputs
+--		data_out : data from memory
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+entity CN_cluster_onedge_LUT is
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(15 downto 0);
+		data_in                 : in std_logic;
+		read_address            : in std_logic_vector(15 downto 0);
+		data_out                : out std_logic
+	);
+end CN_cluster_onedge_LUT;
+
+architecture behavioral of CN_cluster_onedge_LUT is
+type mem_type is array (0 to 2**16-1) of std_logic;
+signal mem_S : mem_type := (others => '1');
+
+attribute RAM_STYLE : string;
+attribute RAM_STYLE of mem_S: signal is "BLOCK";
+ 						 
+begin
+
+	process (clock)
+	begin
+		if (clock'event and clock = '1') then
+			if (write_enable = '1') then
+				mem_S(conv_integer(write_address)) <= data_in;
+			end if;
+			data_out <= mem_S(conv_integer(read_address));			
+		end if;
+	end process;
+	
+
+end architecture behavioral;
\ No newline at end of file
diff --git a/data_concentrator/sources/cluster/CN_clustering.vhd b/data_concentrator/sources/cluster/CN_clustering.vhd
new file mode 100644
index 0000000..7ba7a69
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_clustering.vhd
@@ -0,0 +1,578 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   01-07-2016
+-- Module Name:   CN_clustering
+-- Description:   Clustering part of the PANDA cluster finding
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_clustering
+-- Clustering algorithm, developed by Marcel Tiemens (KVI-cart) for the PANDA Detector at GSI.
+-- This clustering stage searches for time-gaps in the pre-clusters and calculates if pre-clusters are part of the same cluster.
+-- Pre-clusters are considered to belong to the same cluster if the time and distance between the hits are small (next to each other, also diagonally).
+-- The timegap searching divides the input stream into time-bunches in module CN_cluster_findgap.
+-- The time-bunch is processed by module CN_cluster_build to split the data into clusters.
+-- To increase the throughput several mudules are put in parallel.
+-- If a cluster contains only one hit and if this hit is not position on the edge of the region then this cluster is skipped.
+--
+-- The input data consist of a data package from the Panda Data concentrator. Waveforms packages are ignored.
+-- This module can be configured to process data that does not contain the first header word (generic HEADERWORD0).
+-- The output data has the same structure, but only without the header word 0
+--
+-- The 64 bits packets, according to SODAnet specs:
+-- 64bits word0: (only if HEADERWORD0 is set to TRUE)  
+--        bit63      = last-packet flag
+--        bit62..48  = packet number
+--        bit47..32  = data size in bytes
+--        bit31..0   = Not used (same as HADES)
+-- 64bits word1:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+--    for pulse data
+-- 64bits word2 and further, for each pulse:   
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+--    for wave data (ignored)
+-- 64bits word2:
+--        bit63..56  = status byte
+--        bit55..40  = adc channel
+--        bit39..32  = number of samples in wave
+--        bit15..0  = timestamp in respect to superburst of the first sample in the waveform
+-- 64bits word3 and further : 
+--        bit63..48  = next_adcsample(15:0)
+--        bit47..32  = next_adcsample(15:0)
+--        bit31..16  = next_adcsample(15:0)
+--        bit15..0   = next_adcsample(15:0)
+--
+--    for cluster data
+-- 64bits word2, clusterresults
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..30  = diameter
+--        bit29..20  = Y position, multiplied by 2
+--        bit19..10  = X position, multiplied by 2
+--        bit9..0    = number of hits in cluster
+-- 64bits word3..word3+nrofhits : pulse data
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+-- Library
+--
+-- Generics:
+--       CLUSTERBITS : number of bits for the number of hits in one timebunch
+--       MAXCLUSTERSBITS : number of bits for the maximum clusters in one timebunch
+--       PARALLELBUILDS : number of CN_precluster_build modules to work in parallel
+--       HEADERWORD0 : true : process SODAnet packet, false process packet with first word containing superburstnumber
+--       MINIMUMENERGYBITS : number of bits for the miminum energy value
+--       SKIPSINGLEHITCLUSTERS : skip precluster if it contains only one hit and is not positioned on the edge
+-- 
+-- Inputs:
+--      clock : clock
+--      reset : reset
+--      gap_time : maximum gap time between hits, resolutie from Constant Fraction (6.1ps)
+--      timedifference : maximum difference in time between hits in a cluster, resolutie from Constant Fraction (6.1ps)
+--      minimal_energy : minimum energy for a cluster; clusters with less are skipped if they are not positioned on the edge of a region
+--      onedgeLUT_write : write signal for on-edge Look Up Table
+--      onedgeLUT_load : when '1' the LUT can be loaded with values, on '0' the writing address is set back to zero
+--      onedgeLUT_data : loading data for the LUT: 'on edge'
+--      data_in : 64bits data
+--      data_in_first : indicates that 64bits data is first in a packet
+--      data_in_last : indicates that 64bits data is last in packet
+--      data_in_write : write signal for 64bits data
+--      data_out_allowed : allowed to write output data
+-- 
+-- Outputs:
+--      data_in_allowed : writing of input data allowed 
+--      data_out : 64 bits output data
+--      data_out_write : write signal for 64 bits output data
+--      data_out_first : 64 bits output data contains the new superburst number
+--      data_out_last : 64 bits output data is the last of a superburst (not necessarily the same as timebunch)
+--      dataerror : error in data
+-- 
+-- Components:
+--      CN_cluster_findgap : Breaks stream of hits into timebunches
+--      CN_cluster_build : Construct clusters from a bunch of hits
+--      syncfifo_1024x66_almostempty256 : synchronous fifo to buffer output data
+--      CN_fiforead2write : Converts reading from fifo to write
+--
+----------------------------------------------------------------------------------
+
+entity CN_clustering is
+	generic(
+		CLUSTERBITS             : natural := 8;
+		MAXCLUSTERSBITS         : natural := 5;
+		PARALLELBUILDS          : natural := 4;
+		HEADERWORD0             : boolean := TRUE;
+		MINIMUMENERGYBITS       : natural := 8;
+		SKIPSINGLEHITCLUSTERS   : boolean := FALSE
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		gap_time                : in std_logic_vector(23 downto 0);
+		timedifference          : in std_logic_vector(23 downto 0);
+		minimal_energy          : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+		onedgeLUT_write         : in std_logic;
+		onedgeLUT_load          : in std_logic;
+		onedgeLUT_data          : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_allowed        : in std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end CN_clustering;
+
+
+architecture behaviour of CN_clustering is
+
+component CN_cluster_findgap is
+	generic(
+		HEADERWORD0             : boolean := HEADERWORD0   
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		gap_time                : in std_logic_vector(23 downto 0);
+		onedgeLUT_write         : in std_logic;
+		onedgeLUT_load          : in std_logic;
+		onedgeLUT_data          : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_onedge         : out std_logic;
+		data_out_active         : out std_logic;
+		data_out_nexttimebunch  : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_allowed        : in std_logic;
+		superburst_rewind       : out std_logic;
+		dataerror               : out std_logic
+	); 
+end component;
+
+
+component CN_cluster_build is
+	generic(
+		CLUSTERBITS             : natural := CLUSTERBITS;
+		MAXCLUSTERSBITS         : natural := MAXCLUSTERSBITS;
+		MINIMUMENERGYBITS       : natural := MINIMUMENERGYBITS;
+		SKIPSINGLEHITCLUSTERS   : boolean := SKIPSINGLEHITCLUSTERS
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		timedifference          : in std_logic_vector(23 downto 0);
+		minimal_energy          : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_onedge          : in std_logic;
+		data_in_active          : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_allowed         : out std_logic;
+		busy                    : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_clusterallowed : in std_logic;
+		nextcluster             : out std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component syncfifo_1024x66_almostempty256 is
+	port(
+    clk                        : in std_logic;
+    srst                       : in std_logic;
+    din                        : in std_logic_vector(65 DOWNTO 0);
+    wr_en                      : in std_logic;
+    rd_en                      : in std_logic;
+    dout                       : out std_logic_vector(65 DOWNTO 0);
+    full                       : out std_logic;
+    empty                      : out std_logic;
+    prog_empty                 : out std_logic
+	); 
+end component;
+
+component syncfifo_4096x66_almostempty3524 is
+	port(
+    clk                        : in std_logic;
+    srst                       : in std_logic;
+    din                        : in std_logic_vector(65 DOWNTO 0);
+    wr_en                      : in std_logic;
+    rd_en                      : in std_logic;
+    dout                       : out std_logic_vector(65 DOWNTO 0);
+    full                       : out std_logic;
+    empty                      : out std_logic;
+    prog_empty                 : out std_logic
+	); 
+end component;
+
+component CN_fiforead2write is
+	generic(
+		BITS                    : integer := 66
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic; 
+		data_in                 : in std_logic_vector(BITS-1 downto 0);
+		data_in_empty           : in std_logic;
+		data_in_read            : out std_logic;
+		data_out                : out std_logic_vector(BITS-1 downto 0);
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic
+	); 
+end component;
+
+signal build_reset_S           : std_logic;
+signal superburst_rewind_S     : std_logic := '0';
+signal gapdata_S               : std_logic_vector(63 downto 0);
+signal gapdata_onedge_S        : std_logic := '1';
+signal gapdataerror_S          : std_logic;
+signal gapdata_active_S        : std_logic;
+signal gapdata_write_S         : std_logic;
+signal gapdata_first_s         : std_logic;
+signal gapdata_last_S          : std_logic;
+signal gapdata_allowed_S       : std_logic;
+signal gapdata_nexttimebunch_S : std_logic;
+signal build_actual0_S         : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_next_S            : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_actual_S          : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_read_S            : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_active_S          : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_allowed_S         : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_write_S           : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_write_S        : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_firsts_S       : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_last_S         : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_allowed_S      : std_logic_vector(0 to PARALLELBUILDS-1);
+signal busy_S                  : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_nextcluster_S     : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_error_S           : std_logic_vector(0 to PARALLELBUILDS-1);
+
+signal fifoout_datain_S        : std_logic_vector(65 downto 0);
+signal fifoout_dataout_S       : std_logic_vector(65 downto 0);
+signal fifoout_write_S         : std_logic;
+signal fifoout_read_S          : std_logic;
+signal fifoout_full_S          : std_logic;
+signal fifoout_empty_S         : std_logic;
+signal fifoout_prog_empty_S    : std_logic;
+
+
+	
+
+type data_out_type is array(0 to PARALLELBUILDS-1) of std_logic_vector(63 downto 0);
+signal data_out_S              : data_out_type;
+
+type testword_type is array(0 to PARALLELBUILDS-1) of std_logic_vector(127 downto 0);
+signal testword0_S             : testword_type;
+
+signal debug_error_S           : std_logic;
+
+begin
+dataerror <= '1' when (gapdataerror_S='1') or (conv_integer(unsigned(build_error_S))/=0) or (fifoout_full_S='1') else '0';
+CN_cluster_findgap1: CN_cluster_findgap port map(
+		clock => clock,
+		reset => reset,
+		gap_time => gap_time,
+		onedgeLUT_write => onedgeLUT_write,
+		onedgeLUT_load => onedgeLUT_load,
+		onedgeLUT_data => onedgeLUT_data,
+		data_in => data_in,
+		data_in_first => data_in_first,
+		data_in_last => data_in_last,
+		data_in_write => data_in_write,
+		data_in_allowed => data_in_allowed,
+		data_out => gapdata_S,
+		data_out_onedge => gapdata_onedge_S,
+		data_out_active => gapdata_active_S,
+		data_out_nexttimebunch => gapdata_nexttimebunch_S,
+		data_out_write => gapdata_write_S,
+		data_out_first => gapdata_first_S,
+		data_out_last => gapdata_last_S,
+		data_out_allowed => gapdata_allowed_S,
+		superburst_rewind => superburst_rewind_S,
+		dataerror => gapdataerror_S);
+
+gapdata_allowed_S <= build_allowed_S(build_actual_S);
+
+build_actual_S <= build_next_S when (gapdata_nexttimebunch_S='1') else build_actual0_S;
+build_next_S <= 0 when build_actual0_S>=PARALLELBUILDS-1 else build_actual0_S+1;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if (gapdata_nexttimebunch_S='1') then
+			if build_actual0_S<PARALLELBUILDS-1 then
+				build_actual0_S <= build_actual0_S+1;
+			else
+				build_actual0_S <= 0;
+			end if;
+		end if;
+	end if;
+end process;
+
+-- gapdata_allowed_S <= '1' when 
+	-- ((build_allowed_S(build_actual0_S)='1') and (gapdata_nexttimebunch_S='0')) or 
+	-- ((build_allowed_S(build_next_S)='1') and (gapdata_nexttimebunch_S='1'))
+	-- else '0';
+
+-- build_actual_S <= build_next_S when (gapdata_nexttimebunch_S='1') and (build_allowed_S(build_next_S)='1') else build_actual0_S;
+-- build_next_S <= 0 when build_actual0_S>=PARALLELBUILDS-1 else build_actual0_S+1;
+
+-- process(clock)
+-- begin
+	-- if (rising_edge(clock)) then
+		-- if (gapdata_nexttimebunch_S='1') and (gapdata_allowed_S='1') then
+			-- if build_actual0_S<PARALLELBUILDS-1 then
+				-- build_actual0_S <= build_actual0_S+1;
+			-- else
+				-- build_actual0_S <= 0;
+			-- end if;
+		-- end if;
+	-- end if;
+-- end process;
+build_reset_S <= '1' when (superburst_rewind_S='1') or (reset='1') else '0';
+CN_cluster_builds: for idx in 0 to PARALLELBUILDS-1 generate
+	
+	build_write_S(idx) <= gapdata_write_S when idx=build_actual_S else '0';
+	build_active_S(idx) <= gapdata_active_S when idx=build_actual_S else '0';
+	
+	CN_cluster_build0: CN_cluster_build port map(
+			clock => clock,
+			reset => build_reset_S,
+			timedifference => timedifference,
+			minimal_energy => minimal_energy,
+			data_in => gapdata_S,
+			data_in_onedge => gapdata_onedge_S,
+			data_in_active => build_active_S(idx),
+			data_in_write => build_write_S(idx),
+			data_in_first => gapdata_first_S,
+			data_in_last => gapdata_last_S,
+			data_in_allowed => build_allowed_S(idx),
+			busy => busy_S(idx),
+			data_out => data_out_S(idx),
+			data_out_write => data_out_write_S(idx),
+			data_out_first => data_out_firsts_S(idx),
+			data_out_last => data_out_last_S(idx),
+			data_out_clusterallowed => data_out_allowed_S(idx),
+			nextcluster => build_nextcluster_S(idx),
+			dataerror => build_error_S(idx),
+			testword0 => testword0_S(idx)
+	);
+data_out_allowed_S(idx) <= fifoout_prog_empty_S when build_read_S=idx else '0';
+
+end generate;
+
+fifoout_datain_S(63 downto 0) <= data_out_S(build_read_S);
+fifoout_write_S <= data_out_write_S(build_read_S);
+fifoout_datain_S(65) <= data_out_firsts_S(build_read_S);
+fifoout_datain_S(64) <= data_out_last_S(build_read_S);
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if build_actual_S/=build_read_S then
+			if busy_S(build_read_S)='0' then
+				if build_read_S<PARALLELBUILDS-1 then
+					build_read_S <= build_read_S+1;
+				else
+					build_read_S <= 0;
+				end if;
+			end if;
+		else
+			if (build_nextcluster_S(build_read_S)='1') then
+				if build_read_S<PARALLELBUILDS-1 then
+					build_read_S <= build_read_S+1;
+				else
+					build_read_S <= 0;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+outfifo: syncfifo_1024x66_almostempty256 port map(
+--outfifo: syncfifo_4096x66_almostempty3524 port map(
+    clk => clock,
+    srst => build_reset_S,
+    din => fifoout_datain_S,
+    wr_en => fifoout_write_S,
+    rd_en => fifoout_read_S,
+    dout => fifoout_dataout_S,
+    full => fifoout_full_S,
+    empty => fifoout_empty_S,
+    prog_empty => fifoout_prog_empty_S); 
+
+
+read2write: CN_fiforead2write port map(
+	clock => clock,
+	reset => build_reset_S,
+	data_in => fifoout_dataout_S,
+	data_in_empty => fifoout_empty_S,
+	data_in_read => fifoout_read_S,
+	data_out(65) => data_out_first,
+	data_out(64) => data_out_last,
+	data_out(63 downto 0) => data_out,
+	data_out_write => data_out_write,
+	data_out_allowed => data_out_allowed);
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0) := (others => '0');
+variable clusterresult_V : std_logic := '0';
+variable same_superburst_V : std_logic := '0';
+variable nextissuperburst_V : std_logic := '1';
+variable nrofhits_V : std_logic_vector(9 downto 0) := (others => '0');
+variable hitscounter_V : std_logic_vector(9 downto 0) := (others => '0');
+variable prev_resulttime_V : std_logic_vector(23 downto 0) := (others => '0');
+variable prev_hittime_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+	if (rising_edge(clock)) then
+		debug_error_S <= '0';
+		if reset='1' then
+			prev_superburst_V := (others => '0');
+			clusterresult_V := '0';
+			same_superburst_V := '0';
+			nextissuperburst_V := '1';
+			nrofhits_V := (others => '0');
+			hitscounter_V := (others => '0');
+			prev_resulttime_V := (others => '0');
+			prev_hittime_V := (others => '0');
+		elsif fifoout_write_S='1' then
+			if fifoout_datain_S(65)='1' then -- first
+				if nextissuperburst_V='0' then
+				end if;
+				if (fifoout_datain_S(30 downto 0)/=prev_superburst_V+1) and (conv_integer(unsigned(prev_superburst_V))/=0) then
+					debug_error_S <= '1';
+				end if;
+				same_superburst_V := '0';
+				prev_superburst_V := fifoout_datain_S(30 downto 0);
+				clusterresult_V := '1';
+				if fifoout_datain_S(64)='1' then -- last
+					nextissuperburst_V := '1';
+				else
+					nextissuperburst_V := '0';
+				end if;
+			elsif clusterresult_V='1' then
+				if fifoout_datain_S(64)='1' then -- last
+					nextissuperburst_V := '1';
+					debug_error_S <= '1';
+				else
+					nextissuperburst_V := '0';
+				end if;
+				if hitscounter_V/=nrofhits_V then
+					debug_error_S <= '1';
+				end if;
+				nrofhits_V := fifoout_datain_S(9 downto 0);
+				if (same_superburst_V='1') and (prev_resulttime_V>fifoout_datain_S(63 downto 40)) then
+					debug_error_S <= '1';
+				end if;
+				same_superburst_V := '1';
+				prev_resulttime_V := fifoout_datain_S(63 downto 40);
+				hitscounter_V := (others => '0');
+				prev_hittime_V := (others => '0');
+				clusterresult_V := '0';
+			else
+				if fifoout_datain_S(64)='1' then -- last
+					if hitscounter_V/=nrofhits_V-1 then
+						debug_error_S <= '1';
+					end if;
+					nextissuperburst_V := '1';
+				else
+					nextissuperburst_V := '0';
+				end if;
+				if fifoout_datain_S(63 downto 40)<prev_hittime_V then
+--						debug_error_S <= '1'; -- hits not sequential
+				end if;
+				prev_hittime_V := fifoout_datain_S(63 downto 40);
+				if hitscounter_V=nrofhits_V-1 then
+					clusterresult_V := '1';
+				end if;
+				hitscounter_V := hitscounter_V+1;
+			end if;
+		end if;
+	end if;
+end process;
+
+-- testword0(63 downto 0) <= gapdata_S;
+-- testword0(64) <= gapdata_first_s;
+-- testword0(65) <= gapdata_last_S;
+-- testword0(66) <= gapdata_write_S;
+-- testword0(67) <= gapdata_allowed_S;
+-- testword0(68) <= gapdata_active_S;
+-- testword0(69) <= gapdataerror_S;
+-- testword0(70) <= gapdata_nexttimebunch_S;
+-- testword0(71) <= '0' when build_actual0_S=0 else '1';
+-- testword0(72) <= '0' when build_next_S=0 else '1';
+-- testword0(73) <= '0' when build_actual_S=0 else '1';
+-- testword0(74) <= '0' when build_read_S=0 else '1';
+-- testword0(75) <= build_active_S(0);
+-- testword0(76) <= build_active_S(1);
+-- testword0(77) <= build_allowed_S(0);
+-- testword0(78) <= build_allowed_S(1);
+-- testword0(79) <= build_write_S(0);
+-- testword0(80) <= build_write_S(1);
+-- testword0(81) <= data_out_write_S(0);
+-- testword0(82) <= data_out_write_S(1);
+-- testword0(83) <= data_out_firsts_S(0);
+-- testword0(84) <= data_out_firsts_S(1);
+-- testword0(85) <= data_out_last_S(0);
+-- testword0(86) <= data_out_last_S(1);
+-- testword0(87) <= data_out_allowed_S(0);
+-- testword0(88) <= data_out_allowed_S(1);
+-- testword0(89) <= busy_S(0);
+-- testword0(90) <= busy_S(1);
+-- testword0(91) <= build_nextcluster_S(0);
+-- testword0(92) <= build_nextcluster_S(1);
+-- testword0(93) <= build_error_S(0);
+-- testword0(94) <= build_error_S(1);
+-- testword0(95) <= fifoout_write_S;
+-- testword0(96) <= fifoout_full_S;
+-- testword0(97) <= fifoout_prog_empty_S;
+-- testword0(98) <= fifoout_empty_S;
+-- testword0(99) <= fifoout_read_S;
+-- testword0(100) <= gapdata_first_s;
+-- testword0(101) <= build_reset_S;
+-- testword0(102) <= superburst_rewind_S;
+
+
+-- testword0(119 downto 112) <= testword0_S(0)(7 downto 0);
+-- testword0(127 downto 120) <= testword0_S(1)(7 downto 0);
+
+testword0 <=  testword0_S(1);
+
+end behaviour;
+
diff --git a/data_concentrator/sources/cluster/CN_combine2clusters.vhd b/data_concentrator/sources/cluster/CN_combine2clusters.vhd
new file mode 100644
index 0000000..7a2601d
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_combine2clusters.vhd
@@ -0,0 +1,584 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI-cart/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   01-07-2016
+-- Module Name:   CN_combine2clusters
+-- Description:   Combines two streams of cluster data to one
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_combine2clusters
+-- Combines two streams of cluster data to one, based on superburst number and time within superburst.
+-- Depending on if an input is connected and functioning an input can be enabled/disabled with the data_in_exists input.
+-- Data packets are compared, the oldest are passed on until both superburst numbers are identical.
+-- Then the cluster-time of the clusters of both inputs are compared and the oldest is passed on.
+-- There is a timeout if no data is available of one of the inputs. This should only happen if there is an error in the system.
+-- The input and output data structure is the same:
+--
+-- The 64 bits data:
+-- 64bits word1:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+-- 64bits word2, clusterresults
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..30  = diameter
+--        bit29..20  = Y position, multiplied by 2
+--        bit19..10  = X position, multiplied by 2
+--        bit9..0    = number of hits in cluster
+-- 64bits word3..word4+nrofhits : pulse data
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+-- Library
+--
+-- 
+-- Inputs:
+--      clock : clock
+--      reset : reset
+--      data1_in : 64bits data
+--      data1_in_first : indicates that 64bits data is first in a packet
+--      data1_in_last : indicates that 64bits data is last in packet
+--      data1_in_write : write signal for 64bits data
+--      data1_in_exists_S : input is being used
+--      data2_in : 64bits data
+--      data2_in_first : indicates that 64bits data is first in a packet
+--      data2_in_last : indicates that 64bits data is last in packet
+--      data2_in_write : write signal for 64bits data
+--      data2_in_exists_S : input is being used
+--      data_out_allowed : allowed to write output data
+-- 
+-- Outputs:
+--      data1_in_allowed : allowed to write data to input data1
+--      data2_in_allowed : allowed to write data to input data2
+--      data_in_allowed : writing of input data allowed 
+--      data_out : 64 bits output data
+--      data_out_write : write signal for 64 bits output data
+--      data_out_first : 64 bits output data contains the new superburst number
+--      data_out_last : 64 bits output data is the last of a superburst
+--      data_out_exists : output is being used
+--      dataerror : error in data
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity CN_combine2clusters is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data1_in                : in std_logic_vector(63 downto 0);
+		data1_in_first          : in std_logic;
+		data1_in_last           : in std_logic;
+		data1_in_write          : in std_logic;
+		data1_in_exists         : in std_logic;
+		data1_in_allowed        : out std_logic;
+		data2_in                : in std_logic_vector(63 downto 0);
+		data2_in_first          : in std_logic;
+		data2_in_last           : in std_logic;
+		data2_in_write          : in std_logic;
+		data2_in_exists         : in std_logic;
+		data2_in_allowed        : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_exists         : out std_logic;
+		data_out_allowed        : in std_logic;
+		dataerror               : out std_logic
+	); 
+end CN_combine2clusters;
+
+
+architecture behaviour of CN_combine2clusters is
+constant TIMEOUTBITS             : integer := 12;
+signal timeout_counter_S         : std_logic_vector(TIMEOUTBITS-1 downto 0) := (others => '0');
+type state_type is (INITIALIZE,CLUSTER1,CLUSTER2,WAITSUPERBURST,CLUSTERRESULT);
+signal state_S                      : state_type := INITIALIZE;
+
+signal error_S                   : std_logic := '0';
+signal data1_in_exists_S         : std_logic := '0';
+signal data2_in_exists_S         : std_logic := '0';
+signal data1_in_alive_S          : std_logic := '1';
+signal data2_in_alive_S          : std_logic := '1';
+signal data1_in_allowed_S        : std_logic := '0';
+signal data2_in_allowed_S        : std_logic := '0';
+signal data1_in_write_S          : std_logic := '0';
+signal data2_in_write_S          : std_logic := '0';
+signal data_out_trywrite_S       : std_logic := '0';
+signal data_out_write_S          : std_logic := '0';
+signal data_out_S                : std_logic_vector(63 downto 0) := (others => '0');
+signal data1_timestamp_valid_S   : std_logic := '0';
+signal data2_timestamp_valid_S   : std_logic := '0';
+
+signal data1_packetfinished_S    : std_logic := '1';
+signal data2_packetfinished_S    : std_logic := '1';
+signal data1_passon_S            : std_logic := '0';
+signal data2_passon_S            : std_logic := '0';
+signal superburst_same_S         : std_logic := '0';
+signal data_out_first_S          : std_logic := '0';
+signal data_out_last_S           : std_logic := '0';
+signal count_S                   : std_logic_vector(9 downto 0) := (others => '0');
+signal superburst1_valid_S       : std_logic := '0';
+signal superburst2_valid_S       : std_logic := '0';
+
+
+signal debug_hits1_S             : std_logic_vector(9 downto 0) := (others => '0');
+signal debug_hits2_S             : std_logic_vector(9 downto 0) := (others => '0');
+signal debug_data1_results_S     : std_logic_vector(63 downto 0) := (others => '0');
+signal debug_data2_results_S     : std_logic_vector(63 downto 0) := (others => '0');
+signal debug_data1_sb_S          : std_logic_vector(63 downto 0) := (others => '0');
+signal debug_data2_sb_S          : std_logic_vector(63 downto 0) := (others => '0');
+
+						
+begin
+
+data1_in_exists_S <= '1' when (data1_in_exists='1') and (data1_in_alive_S='1') else '0';
+data2_in_exists_S <= '1' when (data2_in_exists='1') and (data2_in_alive_S='1') else '0';
+data_out_exists <= '1' when (data1_in_exists_S='1') or (data2_in_exists_S='1') else '0';
+		
+dataerror <= error_S when (data1_in_exists_S='1') and (data2_in_exists_S='1') else '0';
+
+data_out <=
+	data_out_S when (data1_in_exists_S='1') and (data2_in_exists_S='1') else 
+	data1_in when (data1_in_exists_S='1') and (data2_in_exists_S='0') else 
+	data2_in when (data1_in_exists_S='0') and (data2_in_exists_S='1') else 
+	(others => '0');
+data_out_write <= 
+	data_out_write_S when (data1_in_exists_S='1') and (data2_in_exists_S='1') else 
+	data1_in_write when (data1_in_exists_S='1') and (data2_in_exists_S='0') else 
+	data2_in_write when (data1_in_exists_S='0') and (data2_in_exists_S='1') else 
+	'0';
+data_out_write_S <= '1' when ((data_out_trywrite_S='1') and (data_out_allowed='1')) else '0';
+data_out_first <= 
+	'1' when ((data_out_first_S='1') and (data_out_allowed='1')) and ((data1_in_exists_S='1') and (data2_in_exists_S='1')) else
+	data1_in_first when (data1_in_exists_S='1') and (data2_in_exists_S='0') else 
+	data2_in_first when (data1_in_exists_S='0') and (data2_in_exists_S='1') else 
+	'0';
+data_out_last <= 
+	'1' when ((data_out_last_S='1') and (data_out_allowed='1')) and ((data1_in_exists_S='1') and (data2_in_exists_S='1')) else
+	data1_in_last when (data1_in_exists_S='1') and (data2_in_exists_S='0') else 
+	data2_in_last when (data1_in_exists_S='0') and (data2_in_exists_S='1') else 
+	'0';
+data1_in_allowed <= 
+	data1_in_allowed_S when ((data1_in_exists_S='1') and (data2_in_exists_S='1')) else
+	data_out_allowed;	
+data1_in_allowed_S <= '1' when (data_out_allowed='1') and (data2_passon_S='0')
+	and (
+		(data1_passon_S='1') or
+		((state_S=CLUSTER1) and (data1_packetfinished_S='0')) or 
+		((state_S=WAITSUPERBURST) and (superburst1_valid_S='0')) or
+		((state_S=CLUSTERRESULT) and (data1_timestamp_valid_S='0') and (data1_packetfinished_S='0'))
+		)
+	else '0';
+
+data2_in_allowed <= 
+	data2_in_allowed_S when ((data1_in_exists_S='1') and (data2_in_exists_S='1')) else
+	data_out_allowed;	
+data2_in_allowed_S <= '1' when (data_out_allowed='1') and (data1_passon_S='0')
+	and (
+		(data2_passon_S='1') or
+		((state_S=CLUSTER2) and (data2_packetfinished_S='0')) or 
+		((state_S=WAITSUPERBURST) and (superburst2_valid_S='0')) or
+		((state_S=CLUSTERRESULT) and (data2_timestamp_valid_S='0') and (data2_packetfinished_S='0'))
+		)
+	else '0';
+
+data1_in_write_S <= '1' when (data1_in_write='1') and (data1_in_allowed_S='1') else '0';
+data2_in_write_S <= '1' when (data2_in_write='1') and (data2_in_allowed_S='1') else '0';
+
+readprocess: process(clock)
+variable data1_results_V         : std_logic_vector(63 downto 0) := (others => '0');
+variable data2_results_V         : std_logic_vector(63 downto 0) := (others => '0');
+variable superburst1_word_V      : std_logic_vector(63 downto 0) := (others => '0');
+variable superburst2_word_V      : std_logic_vector(63 downto 0) := (others => '0');
+variable superburst1_last_V      : std_logic := '0';
+variable superburst2_last_V      : std_logic := '0';
+variable superburst1_valid_V     : std_logic := '0';
+variable superburst2_valid_V     : std_logic := '0';
+variable data1_timestamp_valid_V : std_logic := '0';
+variable data2_timestamp_valid_V : std_logic := '0';
+
+begin
+	if rising_edge(clock) then
+		error_S <= '0';
+		data_out_trywrite_S <= '0';
+		data_out_first_S <= '0';
+		data_out_last_S <= '0';
+		if reset='1' then
+			data1_in_alive_S <= '1';
+			data2_in_alive_S <= '1';
+			timeout_counter_S <= (others => '0');
+			data1_results_V := (others => '0');
+			data2_results_V := (others => '0');
+			superburst1_word_V := (others => '0');
+			superburst2_word_V := (others => '0');
+			superburst1_last_V := '0';
+			superburst2_last_V := '0';
+			superburst1_valid_V := '0';
+			superburst2_valid_V := '0';
+			data1_timestamp_valid_V := '0';
+			data2_timestamp_valid_V := '0';
+			state_S <= INITIALIZE;
+		elsif (data_out_trywrite_S='1') and (data_out_write_S='0') then -- unsuccesful write
+			data_out_first_S <= data_out_first_S;
+			data_out_last_S <= data_out_last_S;
+			data_out_trywrite_S <= '1'; -- try again
+			timeout_counter_S <= (others => '0');
+		else
+			case state_S is
+				when INITIALIZE =>
+					data1_in_alive_S <= '1';
+					data2_in_alive_S <= '1';
+					superburst1_last_V := '0';
+					superburst2_last_V := '0';
+					superburst1_valid_V := '0';
+					superburst2_valid_V := '0';
+					data1_timestamp_valid_V := '0';
+					data2_timestamp_valid_V := '0';
+					state_S <= WAITSUPERBURST;
+				when CLUSTER1 =>
+					data1_timestamp_valid_V := '0';
+					if data1_in_write_S='1' then
+						timeout_counter_S <= (others => '0');
+						if (data1_in_first='1') then
+							error_S <= '1';
+							state_S <= WAITSUPERBURST;
+							data1_timestamp_valid_V := '0';
+							data2_timestamp_valid_V := '0';
+							superburst1_valid_V := '1';
+							superburst1_word_V := data1_in;
+							superburst1_last_V := data1_in_last;
+						elsif (data1_in_last='1') then
+							if count_S/=data1_results_V(9 downto 0)-1 then
+								error_S <= '1';
+							end if;
+							data_out_S <= data1_in;
+							data_out_trywrite_S <= '1';
+							data1_packetfinished_S <= '1';
+							if (data2_packetfinished_S='1') or (data1_passon_S='1') then
+								data_out_last_S <= '1';
+								state_S <= WAITSUPERBURST;
+							else
+								state_S <= CLUSTERRESULT;
+							end if;
+						elsif (count_S>=data1_results_V(9 downto 0)-1) then -- last data
+							data_out_S <= data1_in;
+							data_out_trywrite_S <= '1';
+							state_S <= CLUSTERRESULT;
+						else
+							data_out_S <= data1_in;
+							data_out_first_S <= '0';
+							data_out_trywrite_S <= '1';
+							count_S <= count_S+1;
+						end if;
+					else
+						if timeout_counter_S(TIMEOUTBITS-1)='1' then
+							data1_in_alive_S <= '0';
+							error_S <= '1';
+							state_S <= WAITSUPERBURST;
+							superburst1_valid_V := '0';
+							data1_timestamp_valid_V := '0';
+							data2_timestamp_valid_V := '0';
+							timeout_counter_S <= (others => '0');
+						else
+							if data_out_allowed='1' then
+								if data_out_write_S='1' then
+									timeout_counter_S <= (others => '0');
+								else
+									timeout_counter_S <= timeout_counter_S+1;
+								end if;
+							end if;
+						end if;
+					end if;
+					if (data1_packetfinished_S='1') then
+						error_S <= '1';
+						if (data2_packetfinished_S='1') then
+							state_S <= WAITSUPERBURST;
+						else
+							state_S <= CLUSTERRESULT;
+						end if;
+					end if;
+				when CLUSTER2 =>
+					data2_timestamp_valid_V := '0';
+					if data2_in_write_S='1' then
+						timeout_counter_S <= (others => '0');
+						if (data2_in_first='1') then
+							error_S <= '1';
+							state_S <= WAITSUPERBURST;
+							data1_timestamp_valid_V := '0';
+							data2_timestamp_valid_V := '0';
+							superburst2_valid_V := '1';
+							superburst2_word_V := data2_in;
+							superburst2_last_V := data2_in_last;
+						elsif (data2_in_last='1') then
+							if count_S/=data2_results_V(9 downto 0)-1 then
+								error_S <= '1';
+							end if;
+							data_out_S <= data2_in;
+							data_out_trywrite_S <= '1';
+							data2_packetfinished_S <= '1';
+							if (data1_packetfinished_S='1') or (data2_passon_S='1') then
+								data_out_last_S <= '1';
+								state_S <= WAITSUPERBURST;
+							else
+								state_S <= CLUSTERRESULT;
+							end if;
+						elsif (count_S>=data2_results_V(9 downto 0)-1) then -- last data
+							data_out_S <= data2_in;
+							data_out_trywrite_S <= '1';
+							state_S <= CLUSTERRESULT;
+						else
+							data_out_S <= data2_in;
+							data_out_first_S <= '0';
+							data_out_trywrite_S <= '1';
+							count_S <= count_S+1;
+						end if;
+					else
+						if timeout_counter_S(TIMEOUTBITS-1)='1' then
+							data2_in_alive_S <= '0';
+							error_S <= '1';
+							state_S <= WAITSUPERBURST;
+							superburst2_valid_V := '0';
+							data1_timestamp_valid_V := '0';
+							data2_timestamp_valid_V := '0';
+							timeout_counter_S <= (others => '0');
+						else
+							if data_out_allowed='1' then
+								if data_out_write_S='1' then
+									timeout_counter_S <= (others => '0');
+								else
+									timeout_counter_S <= timeout_counter_S+1;
+								end if;
+							end if;
+						end if;
+					end if;
+					if (data2_packetfinished_S='1') then
+						error_S <= '1';
+						if (data1_packetfinished_S='1') then
+							state_S <= WAITSUPERBURST;
+						else
+							state_S <= CLUSTERRESULT;
+						end if;
+					end if;
+				when WAITSUPERBURST =>
+					data1_packetfinished_S <= '0';
+					data2_packetfinished_S <= '0';
+					superburst_same_S <= '0';
+					data1_passon_S <= '0';
+					data2_passon_S <= '0';
+					data1_timestamp_valid_V := '0';
+					data2_timestamp_valid_V := '0';
+					count_S <= (others => '0');
+					if (data1_in_write_S='1') and (data1_in_first='1') then
+						superburst1_valid_V := '1';
+						superburst1_word_V := data1_in;
+						superburst1_last_V := data1_in_last;
+					end if;
+					if (data2_in_write_S='1') and (data2_in_first='1') then
+						superburst2_valid_V := '1';
+						superburst2_word_V := data2_in;
+						superburst2_last_V := data2_in_last;
+					end if;
+					if (superburst1_valid_V='1') and (superburst2_valid_V='1') then
+						if superburst1_word_V(30 downto 0)=superburst2_word_V(30 downto 0) then
+							if (superburst1_last_V='1') and (superburst2_last_V='1') then
+								data_out_trywrite_S <= '1';						
+								data_out_first_S <= '1';
+								data_out_last_S <= '1';
+								data_out_S <= superburst1_word_V;
+								state_S <= WAITSUPERBURST;
+								superburst1_valid_V := '0';
+								superburst2_valid_V := '0';
+							elsif (superburst1_last_V='1') and (superburst2_last_V='0') then
+								data_out_trywrite_S <= '1';						
+								data_out_first_S <= '1';
+								data_out_last_S <= '0';
+								data2_passon_S <= '1';
+								data_out_S <= superburst2_word_V;
+								state_S <= CLUSTERRESULT;
+								superburst1_valid_V := '0';
+								superburst2_valid_V := '0';
+							elsif (superburst1_last_V='0') and (superburst2_last_V='1') then
+								data_out_trywrite_S <= '1';						
+								data_out_first_S <= '1';
+								data_out_last_S <= '0';
+								data1_passon_S <= '1';
+								data_out_S <= superburst1_word_V;
+								state_S <= CLUSTERRESULT;
+								superburst1_valid_V := '0';
+								superburst2_valid_V := '0';
+							else
+								data_out_trywrite_S <= '1';						
+								data_out_first_S <= '1';
+								data_out_last_S <= '0';
+								superburst_same_S <= '1';
+								data_out_S <= superburst1_word_V;
+								state_S <= CLUSTERRESULT;
+								superburst1_valid_V := '0';
+								superburst2_valid_V := '0';
+							end if;						
+						elsif superburst2_word_V(30 downto 0)>superburst1_word_V(30 downto 0) then
+							if (superburst1_last_V='1') then
+								data_out_trywrite_S <= '1';						
+								data_out_first_S <= '1';
+								data_out_S <= superburst1_word_V;
+								state_S <= WAITSUPERBURST;
+								superburst1_valid_V := '0';
+							else
+								data_out_trywrite_S <= '1';						
+								data_out_first_S <= '1';
+								data_out_last_S <= '0';
+								data1_passon_S <= '1';
+								data_out_S <= superburst1_word_V;
+								state_S <= CLUSTERRESULT;
+								superburst1_valid_V := '0';
+							end if;						
+						else
+							if (superburst2_last_V='1') then
+								data_out_trywrite_S <= '1';						
+								data_out_first_S <= '1';
+								data_out_S <= superburst2_word_V;
+								state_S <= WAITSUPERBURST;
+								superburst2_valid_V := '0';
+							else
+								data_out_trywrite_S <= '1';						
+								data_out_first_S <= '1';
+								data_out_last_S <= '0';
+								data2_passon_S <= '1';
+								data_out_S <= superburst2_word_V;
+								state_S <= CLUSTERRESULT;
+								superburst2_valid_V := '0';
+							end if;						
+						end if;
+					else
+						-- timeout
+					end if;
+				when CLUSTERRESULT =>
+					count_S <= (others => '0');
+					if data1_in_write_S='1' then
+						data1_results_V := data1_in;
+						debug_hits1_S <= data1_in(9 downto 0);
+						if conv_integer(unsigned(data1_in(9 downto 0)))/=0 then
+							data1_timestamp_valid_V := '1';
+						else
+							data1_timestamp_valid_V := '0';
+							error_S <= '1';
+						end if;
+						if (data1_in_first='1') or (data1_in_last='1') then
+							error_S <= '1';
+						end if;
+					elsif (data1_packetfinished_S='1') then
+						data1_timestamp_valid_V := '0';
+					end if;
+					if data2_in_write_S='1' then
+						data2_results_V := data2_in;
+						debug_hits2_S <= data2_in(9 downto 0);
+						if conv_integer(unsigned(data2_in(9 downto 0)))/=0 then
+							data2_timestamp_valid_V := '1';
+						else
+							data2_timestamp_valid_V := '0';
+							error_S <= '1';
+						end if;
+						if (data2_in_first='1') or (data2_in_last='1') then
+							error_S <= '1';
+						end if;
+					elsif (data2_packetfinished_S='1') then
+						data2_timestamp_valid_V := '0';
+					end if;
+					if (data1_packetfinished_S='1') and (data2_packetfinished_S='1') then
+						error_S <= '1';
+						state_S <= WAITSUPERBURST;
+					elsif ((data1_passon_S='1') or (data2_packetfinished_S='1')) and (data1_timestamp_valid_V='1') then
+						timeout_counter_S <= (others => '0');
+						data1_timestamp_valid_V := '0';
+						data_out_trywrite_S <= '1';						
+						data_out_S <= data1_results_V;
+						state_S <= CLUSTER1;
+					elsif ((data2_passon_S='1') or (data1_packetfinished_S='1')) and (data2_timestamp_valid_V='1') then
+						timeout_counter_S <= (others => '0');
+						data2_timestamp_valid_V := '0';
+						data_out_trywrite_S <= '1';						
+						data_out_S <= data2_results_V;
+						state_S <= CLUSTER2;
+					else
+						if (data1_timestamp_valid_V='1') and (data2_timestamp_valid_V='1') then
+							timeout_counter_S <= (others => '0');
+							if (data1_results_V(63 downto 40)<data2_results_V(63 downto 40)) then -- select 1
+								data1_timestamp_valid_V := '0';
+								data_out_trywrite_S <= '1';						
+								data_out_S <= data1_results_V;
+								state_S <= CLUSTER1;
+							else -- select 2
+								data2_timestamp_valid_V := '0';
+								data_out_trywrite_S <= '1';						
+								data_out_S <= data2_results_V;
+								state_S <= CLUSTER2;
+							end if;
+						elsif (data1_timestamp_valid_V='1') and (data2_timestamp_valid_V='0') then -- wait
+							if timeout_counter_S(TIMEOUTBITS-1)='1' then
+								data2_in_alive_S <= '0';
+								error_S <= '1';
+								data1_timestamp_valid_V := '0';
+								data_out_trywrite_S <= '1';						
+								data_out_S <= data1_results_V;
+								timeout_counter_S <= (others => '0');
+								state_S <= CLUSTER1;
+							else
+								if data_out_allowed='1' then
+									timeout_counter_S <= timeout_counter_S+1;
+								end if;
+							end if;
+						elsif (data1_timestamp_valid_V='0') and (data2_timestamp_valid_V='1') then -- wait
+							if timeout_counter_S(TIMEOUTBITS-1)='1' then
+								data1_in_alive_S <= '0';
+								error_S <= '1';
+								data2_timestamp_valid_V := '0';
+								data_out_trywrite_S <= '1';						
+								data_out_S <= data2_results_V;
+								timeout_counter_S <= (others => '0');
+								state_S <= CLUSTER2;
+							else
+								if data_out_allowed='1' then
+									timeout_counter_S <= timeout_counter_S+1;
+								end if;
+							end if;
+						else -- no valid timestamps
+						end if;
+					end if;
+				when OTHERS =>
+					state_S <= INITIALIZE;
+			end case;
+		end if;
+		superburst1_valid_S <= superburst1_valid_V;
+		superburst2_valid_S <= superburst2_valid_V;
+		data1_timestamp_valid_S <= data1_timestamp_valid_V;
+		data2_timestamp_valid_S <= data2_timestamp_valid_V;
+		debug_data1_results_S <= data1_results_V;
+		debug_data2_results_S <= data2_results_V;
+		debug_data1_sb_S <= superburst1_word_V;
+		debug_data2_sb_S <= superburst2_word_V;
+		if (data1_in_write='1') then
+			data1_in_alive_S <= '1';
+		end if;
+		if (data2_in_write='1') then
+			data2_in_alive_S <= '1';
+		end if;
+	end if;
+end process;
+
+end behaviour;
+
diff --git a/data_concentrator/sources/cluster/CN_combineclusters.vhd b/data_concentrator/sources/cluster/CN_combineclusters.vhd
new file mode 100644
index 0000000..27fe464
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_combineclusters.vhd
@@ -0,0 +1,263 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   01-09-2016
+-- Module Name:   CN_combineclusters
+-- Description:   Combines multiple streams of cluster data to one
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library work;
+USE work.CN_package.all;
+----------------------------------------------------------------------------------
+-- CN_combineclusters
+-- Combines multiple streams of cluster data to one, based on superburst number and time within superburst.
+-- The inputs are compared and combined in a tree structure with two inputs and one output.
+-- If the number of inputs is not a power of 2 then the missing inputs are filled up with empty data.
+-- Also, depending on if an input is connected and functioning an input can be enabled/disabled with the data_in_exists input.
+-- The input and output data structure is the same:
+--
+-- The 64 bits data:
+-- 64bits word1:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+-- 64bits word2, clusterresults
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..30  = diameter
+--        bit29..20  = Y position, multiplied by 2
+--        bit19..10  = X position, multiplied by 2
+--        bit9..0    = number of hits in cluster
+-- 64bits word3..word4+nrofhits : pulse data
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+-- Library
+--
+-- 
+-- Inputs:
+--      clock : clock for data input
+--      reset : reset
+--      data_in : array of 64bits data
+--      data_in_first : array of bits that indicates that corresponding 64bits data is first in packet
+--      data_in_last : array of bits that indicates that corresponding 64bits data is last in packet
+--      data_in_write : array of write signals for corresponding 64bits data
+--      data_in_exists : input is being used
+--      data_out_allowed : allowed to write output data
+--      
+-- 
+-- Outputs:
+--      data_in_allowed : array of signals to allow writing to corresponding input
+--      data_out : 64 bits output data
+--      data_out_write : write signal for 64 bits output data
+--      data_out_first : 64 bits output data contains the new superburst number
+--      data_out_last : 64 bits output data is the last of a superburst
+--      dataerror : error in data
+-- 
+-- Components:
+--      CN_combine2clusters : Combines two streams of cluster data to one
+--
+----------------------------------------------------------------------------------
+
+entity CN_combineclusters is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in CN_inputs64bits_type;
+		data_in_first           : in std_logic_vector(0 to NROFCNINPUTS-1);
+		data_in_last            : in std_logic_vector(0 to NROFCNINPUTS-1);
+		data_in_write           : in std_logic_vector(0 to NROFCNINPUTS-1);
+		data_in_exists          : in std_logic_vector(0 to NROFCNINPUTS-1);
+		data_in_allowed         : out std_logic_vector(0 to NROFCNINPUTS-1);
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_allowed        : in std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end CN_combineclusters;
+
+
+architecture behaviour of CN_combineclusters is
+constant TIMEOUTBITS            : integer := 12;
+constant mux2to1_gen_max        : integer := twologarray(NROFCNINPUTS); 
+constant NROFCNINPUTSPOW2       : integer := 2**mux2to1_gen_max;
+
+component CN_combine2clusters is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data1_in                : in std_logic_vector(63 downto 0);
+		data1_in_first          : in std_logic;
+		data1_in_last           : in std_logic;
+		data1_in_write          : in std_logic;
+		data1_in_exists         : in std_logic;
+		data1_in_allowed        : out std_logic;
+		data2_in                : in std_logic_vector(63 downto 0);
+		data2_in_first          : in std_logic;
+		data2_in_last           : in std_logic;
+		data2_in_write          : in std_logic;
+		data2_in_exists         : in std_logic;
+		data2_in_allowed        : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_exists         : out std_logic;
+		data_out_allowed        : in std_logic;
+		dataerror               : out std_logic
+	); 
+end component;
+
+
+type data_element_type is array(0 to NROFCNINPUTSPOW2-1) of std_logic_vector(63 downto 0);
+type data_type is array(0 to mux2to1_gen_max) of data_element_type;
+type singlebit_type is array(0 to mux2to1_gen_max) of std_logic_vector(0 to NROFCNINPUTSPOW2-1);
+
+signal data_S                    : data_type;
+signal data_first_S              : singlebit_type;
+signal data_last_S               : singlebit_type;
+signal data_write_S              : singlebit_type;
+signal data_exists_S             : singlebit_type;
+signal data_allowed_S            : singlebit_type;
+signal dataerror_S               : singlebit_type;
+
+begin
+
+gen_inputs: for i in 0 to NROFCNINPUTSPOW2-1 generate
+	
+	data_S(0)(i) <= data_in(i) when i<NROFCNINPUTS else (others => '0');
+	data_first_S(0)(i) <= data_in_first(i) when i<NROFCNINPUTS else '0';
+	data_last_S(0)(i) <= data_in_last(i) when i<NROFCNINPUTS else '0';
+	data_write_S(0)(i) <= data_in_write(i) when i<NROFCNINPUTS else '0';
+	data_exists_S(0)(i) <= data_in_exists(i) when i<NROFCNINPUTS else '0';
+	gen_aollowed: if i<NROFCNINPUTS generate
+		data_in_allowed(i) <= data_allowed_S(0)(i);
+	end generate;
+	
+end generate;
+
+
+MUX_multiplex2to1_all: for i1 in 0 to mux2to1_gen_max-1 generate 
+
+	MUX_multiplex2to1_i: for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 generate 
+		CN_combine2clusters_all: CN_combine2clusters port map(
+				clock => clock,
+				reset => reset,
+				data1_in => data_S(i1)(i2*2),
+				data1_in_first => data_first_S(i1)(i2*2),
+				data1_in_last => data_last_S(i1)(i2*2),
+				data1_in_write => data_write_S(i1)(i2*2),
+				data1_in_exists => data_exists_S(i1)(i2*2),
+				data1_in_allowed => data_allowed_S(i1)(i2*2),
+				data2_in => data_S(i1)(i2*2+1),
+				data2_in_first => data_first_S(i1)(i2*2+1),
+				data2_in_last => data_last_S(i1)(i2*2+1),
+				data2_in_write => data_write_S(i1)(i2*2+1),
+				data2_in_exists => data_exists_S(i1)(i2*2+1),
+				data2_in_allowed => data_allowed_S(i1)(i2*2+1),
+				data_out => data_S(i1+1)(i2),
+				data_out_write => data_write_S(i1+1)(i2),
+				data_out_first => data_first_S(i1+1)(i2),
+				data_out_last => data_last_S(i1+1)(i2),
+				data_out_exists => data_exists_S(i1+1)(i2),
+				data_out_allowed => data_allowed_S(i1+1)(i2),
+				dataerror => dataerror_S(i1+1)(i2)
+			); 
+	end generate;
+end generate;
+
+data_out <= data_S(mux2to1_gen_max)(0);
+data_out_write <= data_write_S(mux2to1_gen_max)(0);
+data_out_first <= data_first_S(mux2to1_gen_max)(0);
+data_out_last <= data_last_S(mux2to1_gen_max)(0);
+data_allowed_S(mux2to1_gen_max)(0) <= data_out_allowed;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then 
+		dataerror <= '0';
+		for i1 in 0 to mux2to1_gen_max-1 loop 
+			for i2 in 0 to (2**(mux2to1_gen_max-i1-1))-1 loop 
+				if dataerror_S(i1)(i2)='1' then
+					dataerror <= '1';
+				end if;
+			end loop;
+		end loop;
+	end if;
+end process;
+
+
+testword0(7 downto 0) <= data_in(0)(7 downto 0);
+testword0(8) <= data_in_write(0);
+testword0(9) <= data_in_first(0);
+testword0(10) <= data_in_last(0);
+testword0(11) <= data_allowed_S(0)(0);
+testword0(19 downto 12) <= data_in(1)(7 downto 0);
+testword0(20) <= data_in_write(1);
+testword0(21) <= data_in_first(1);
+testword0(22) <= data_in_last(1);
+testword0(23) <= data_allowed_S(0)(1);
+testword0(31 downto 24) <= data_in(2)(7 downto 0);
+testword0(32) <= data_in_write(2);
+testword0(33) <= data_in_first(2);
+testword0(34) <= data_in_last(2);
+testword0(35) <= data_allowed_S(0)(2);
+testword0(43 downto 36) <= data_in(3)(7 downto 0);
+testword0(44) <= data_in_write(3);
+testword0(45) <= data_in_first(3);
+testword0(46) <= data_in_last(3);
+testword0(47) <= data_allowed_S(0)(3);
+
+
+testword0(55 downto 48) <= data_S(1)(0)(7 downto 0);
+testword0(56) <= data_write_S(1)(0);
+testword0(57) <= data_first_S(1)(0);
+testword0(58) <= data_last_S(1)(0);
+testword0(59) <= data_allowed_S(1)(0);
+testword0(60) <= dataerror_S(1)(0);
+
+testword0(68 downto 61) <= data_S(1)(1)(7 downto 0);
+testword0(69) <= data_write_S(1)(1);
+testword0(70) <= data_first_S(1)(1);
+testword0(71) <= data_last_S(1)(1);
+testword0(72) <= data_allowed_S(1)(1);
+testword0(73) <= dataerror_S(1)(1);
+
+testword0(81 downto 74) <= data_S(2)(0)(7 downto 0);
+testword0(82) <= data_write_S(2)(0);
+testword0(83) <= data_first_S(2)(0);
+testword0(84) <= data_last_S(2)(0);
+testword0(85) <= data_allowed_S(2)(0);
+testword0(86) <= dataerror_S(2)(0);
+
+testword0(87) <= data_in_exists(0);
+testword0(88) <= data_in_exists(1);
+testword0(89) <= data_in_exists(2);
+testword0(90) <= data_in_exists(3);
+
+testword0(91) <= data_exists_S(1)(0);
+testword0(92) <= data_exists_S(1)(1);
+testword0(93) <= data_exists_S(2)(0);
+
+
+
+
+
+
+end behaviour;
+
diff --git a/data_concentrator/sources/cluster/CN_fiforead2write.vhd b/data_concentrator/sources/cluster/CN_fiforead2write.vhd
new file mode 100644
index 0000000..25cad7b
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_fiforead2write.vhd
@@ -0,0 +1,144 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   14-03-2016
+-- Module Name:   CN_fiforead2write
+-- Description:   Converts reading from fifo to write
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+----------------------------------------------------------------------------------
+-- CN_fiforead2write
+-- Converts reading from fifo to write
+--
+--
+--
+-- Library
+--
+-- 
+-- Generics
+--     BITS : number of bits at input and output
+--
+-- Inputs:
+--     clock : clock input for 64 bits data
+--     data_in : input data
+--     data_in_empty : empty from connected fifo
+--     data_out_allowed : writing of input data is allowed
+-- 
+-- Outputs:
+--     data_in_read : read data from fifo
+--     data_out : output data
+--     data_out_write : write signal for output data
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity CN_fiforead2write is
+	generic(
+		BITS                    : integer := 32
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic; 
+		data_in                 : in std_logic_vector(BITS-1 downto 0);
+		data_in_empty           : in std_logic;
+		data_in_read            : out std_logic;
+		data_out                : out std_logic_vector(BITS-1 downto 0);
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic
+	); 
+end CN_fiforead2write;
+
+
+
+architecture behaviour of CN_fiforead2write is
+
+signal data_in_read_S          : std_logic;
+signal data_in_read_aftr1clk_S : std_logic := '0';
+signal data_out_filled_S       : std_logic := '0';
+signal data_out_trywrite_S     : std_logic := '0';
+signal data_out_buf_S          : std_logic_vector(BITS-1 downto 0);
+signal data_out_S              : std_logic_vector(BITS-1 downto 0);
+
+
+begin
+
+data_in_read <= data_in_read_S;
+data_in_read_S <= '1' when (data_in_empty='0') and (data_out_allowed='1') and (data_out_filled_S='0')  and (reset='0') else '0';
+out_process: process(clock)
+begin
+	if rising_edge(clock) then
+		data_out_trywrite_S <= '0';
+		if reset='1' then
+			data_in_read_aftr1clk_S <= '0';
+			data_out_filled_S <= '0';
+		else
+			data_in_read_aftr1clk_S <= data_in_read_S;
+			if data_in_read_aftr1clk_S='1' then 
+				if data_out_allowed='1' then
+					if (data_out_trywrite_S='1') then
+						if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+							data_out_S <= data_out_buf_S;
+							data_out_buf_S <= data_in;
+							data_out_trywrite_S <= '1'; -- write previous data
+							data_out_filled_S <= '1';
+						else -- write new data
+							data_out_S <= data_in;
+							data_out_trywrite_S <= '1';
+							data_out_filled_S <= '0';
+						end if;
+					else -- data_out_trywrite_S='0'
+						if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+							data_out_S <= data_out_buf_S;
+							data_out_buf_S <= data_in;
+							data_out_trywrite_S <= '1'; -- write previous data
+							data_out_filled_S <= '1';
+						else -- -- data_out_filled_S='0',  write new data
+							data_out_S <= data_in;
+							data_out_trywrite_S <= '1';
+							data_out_filled_S <= '0';
+						end if;
+					end if;
+				else -- data_out_allowed='0'
+					if data_out_trywrite_S='1' then -- try again, save new data
+						data_out_buf_S <= data_in;
+						data_out_trywrite_S <= '1';
+						data_out_filled_S <= '1';
+						if data_out_filled_S='1' then
+							--error
+						end if;
+					else -- data_out_trywrite_S='0'
+						if (data_out_filled_S='1') then -- now previous saved data is writing, save new data
+							data_out_S <= data_out_buf_S;
+							data_out_buf_S <= data_in;
+							data_out_trywrite_S <= '1'; -- write previous data
+							data_out_filled_S <= '1';
+						else -- data_out_filled_S='0'
+							data_out_S <= data_in;
+							data_out_trywrite_S <= '1';
+							data_out_filled_S <= '0';
+						end if;
+					end if;
+				end if;
+			elsif (data_out_allowed='0') and (data_out_trywrite_S='1') then -- try again
+				data_out_trywrite_S <= '1';
+			elsif data_out_filled_S='1' then
+				if data_out_allowed='1' then
+					data_out_S <= data_out_buf_S;
+					data_out_trywrite_S <= '1';
+					data_out_filled_S <= '0';
+				end if;
+			else
+			end if;
+		end if;
+	end if;
+end process;
+data_out_write <= '1' when (data_out_trywrite_S='1') and (data_out_allowed='1') else '0';
+data_out <= data_out_S;
+
+end behaviour;
+
diff --git a/data_concentrator/sources/cluster/CN_package.vhd b/data_concentrator/sources/cluster/CN_package.vhd
new file mode 100644
index 0000000..29a81af
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_package.vhd
@@ -0,0 +1,468 @@
+----------------------------------------------------------------------------------
+-- Company:     KVI-cart/RUG/Groningen University
+-- Engineer:    Peter Schakel
+-- Create Date: 20-04-2016
+-- Module Name: CN_package
+-- Description: Package with constants and functions for Compute Node
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+package CN_package is
+
+	constant NROFCNINPUTS : natural := 4; -- 147;
+	constant XYPAD_BITSIZE : natural := 8;  
+--	constant ADCCLOCKFREQUENCY : natural := 80000000; -- 80000000; -- 62500000;
+	
+-- fiber constants
+constant KCHAR280        : std_logic_vector(7 downto 0) := "00011100"; -- 1C
+constant KCHAR281        : std_logic_vector(7 downto 0) := "00111100"; -- 3C
+constant KCHAR285        : std_logic_vector(7 downto 0) := "10111100"; -- BC
+-- constant KCHAR277        : std_logic_vector(7 downto 0) := "11111011"; -- FB
+constant KCHAR286        : std_logic_vector(7 downto 0) := x"DC";
+	
+	type CN_inputs8bits_type is array(0 to NROFCNINPUTS-1) of std_logic_vector(7 downto 0);
+	type CN_inputs32bits_type is array(0 to NROFCNINPUTS-1) of std_logic_vector(31 downto 0);
+	type CN_inputs64bits_type is array(0 to NROFCNINPUTS-1) of std_logic_vector(63 downto 0);
+	
+	type twologarray_type is array(0 to 256) of natural;
+	constant twologarray : twologarray_type :=
+(0,0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
+7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
+8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8);
+-- (0,0,1,1,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
+-- 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,7);
+
+component CN_posedge_to_pulse is
+	port (
+		clock_in     : in  std_logic;
+		clock_out     : in  std_logic;
+		en_clk    : in  std_logic;
+		signal_in : in  std_logic;
+		pulse     : out std_logic
+	);
+end component;
+
+component CN_handledata is
+	port(
+		clock_rx                : in std_logic_vector(0 to NROFCNINPUTS-1); 
+		clock_tx                : in std_logic_vector(0 to NROFCNINPUTS-1);  
+		clock                   : in std_logic; 
+		clock_UDP               : in std_logic; 
+		reset                   : in std_logic;
+		filter_enable           : in std_logic;
+		filter_bothgain         : in std_logic;
+		filter_adcnr            : in std_logic_vector(15 downto 0);
+		dc_locked               : in std_logic_vector(0 to NROFCNINPUTS-1);
+		rxdata                  : in CN_inputs8bits_type;
+		rx_k                    : in std_logic_vector(0 to NROFCNINPUTS-1);
+		txdata                  : out CN_inputs8bits_type;
+		tx_k                    : out std_logic_vector(0 to NROFCNINPUTS-1);
+		ll_data                 : out std_logic_vector(31 downto 0);
+		ll_sof_n                : out std_logic;
+		ll_eof_n                : out std_logic;
+		ll_src_ready_n          : out std_logic;
+		ll_dst_ready_n          : in std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0');
+		testword1               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_handleclusters is
+	port(
+		clock_rx                : in std_logic_vector(0 to NROFCNINPUTS-1); 
+		clock_tx                : in std_logic_vector(0 to NROFCNINPUTS-1);  
+		clock                   : in std_logic; 
+		clock_UDP               : in std_logic; 
+		reset                   : in std_logic;
+		XYLUT_write             : in std_logic_vector(0 to NROFCNINPUTS-1);
+		XYLUT_load              : in std_logic_vector(0 to NROFCNINPUTS-1);
+		XYLUT_data              : in std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+		data_in_exists          : in std_logic_vector(0 to NROFCNINPUTS-1);
+		dc_locked               : in std_logic_vector(0 to NROFCNINPUTS-1);
+		rxdata                  : in CN_inputs8bits_type;
+		rx_k                    : in std_logic_vector(0 to NROFCNINPUTS-1);
+		txdata                  : out CN_inputs8bits_type;
+		tx_k                    : out std_logic_vector(0 to NROFCNINPUTS-1);
+		ll_data                 : out std_logic_vector(31 downto 0);
+		ll_sof_n                : out std_logic;
+		ll_eof_n                : out std_logic;
+		ll_src_ready_n          : out std_logic;
+		ll_dst_ready_n          : in std_logic;
+		error                   : out std_logic;
+		autoreset               : out std_logic;
+		select_out              : in std_logic_vector(3 downto 0) := (others => '0');
+		select_UDP_speed        : in std_logic_vector(2 downto 0) := (others => '0');
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0');
+		testword1               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_fiberdatato64bits is
+	port(
+		clock_rx                : in std_logic; 
+		clock_tx                : in std_logic; 
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		rxdata                  : in std_logic_vector(7 downto 0);
+		rx_k                    : in std_logic;
+		txdata                  : out std_logic_vector(7 downto 0);
+		tx_k                    : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic;
+		data_out_error          : out std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_separatewaves is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_connected       : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_in_error           : in std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic;
+		data_out_error          : out std_logic;
+		wave_out                : out std_logic_vector(63 downto 0);
+		wave_out_first          : out std_logic;
+		wave_out_last           : out std_logic;
+		wave_out_write          : out std_logic;
+		wave_out_allowed        : in std_logic;
+		wave_out_error          : out std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_bufferdata is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_in_error           : in std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_bufferfull     : out std_logic;
+		data_out_allowed        : in std_logic;
+		data_out_error          : out std_logic
+	); 
+end component;
+
+component CN_combine2packets is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data0_in                : in std_logic_vector(63 downto 0);
+		data0_in_first          : in std_logic;
+		data0_in_last           : in std_logic;
+		data0_in_write          : in std_logic;
+		data0_in_connected      : in std_logic;
+		data0_in_allowed        : out std_logic;
+		data0_in_error          : in std_logic;
+		data1_in                : in std_logic_vector(63 downto 0);
+		data1_in_first          : in std_logic;
+		data1_in_last           : in std_logic;
+		data1_in_write          : in std_logic;
+		data1_in_connected      : in std_logic;
+		data1_in_allowed        : out std_logic;
+		data1_in_error          : in std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic;
+		data_out_error          : out std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_sortwavepackets is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data0_in                : in std_logic_vector(63 downto 0);
+		data0_in_first          : in std_logic;
+		data0_in_last           : in std_logic;
+		data0_in_write          : in std_logic;
+		data0_in_connected      : in std_logic;
+		data0_bufferfull        : in std_logic;
+		data0_in_allowed        : out std_logic;
+		data0_in_error          : in std_logic;
+		data1_in                : in std_logic_vector(63 downto 0);
+		data1_in_first          : in std_logic;
+		data1_in_last           : in std_logic;
+		data1_in_write          : in std_logic;
+		data1_in_connected      : in std_logic;
+		data1_bufferfull        : in std_logic;
+		data1_in_allowed        : out std_logic;
+		data1_in_error          : in std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic;
+		data_out_error          : out std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_process_DCdata is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(31 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_read           : in std_logic;
+		data_out_available      : out std_logic;
+		error                   : out std_logic
+	); 
+end component;
+
+component CN_combine2streams is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data0_in                : in std_logic_vector(63 downto 0);
+		data0_in_first          : in std_logic;
+		data0_in_last           : in std_logic;
+		data0_in_write          : in std_logic;
+		data0_in_allowed        : out std_logic;
+		data0_in_error          : in std_logic;
+		data1_in                : in std_logic_vector(63 downto 0);
+		data1_in_first          : in std_logic;
+		data1_in_last           : in std_logic;
+		data1_in_write          : in std_logic;
+		data1_in_allowed        : out std_logic;
+		data1_in_error          : in std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic;
+		data_out_error          : out std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_filter is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		filter_enable           : in std_logic;
+		filter_bothgain         : in std_logic;
+		filter_adcnr            : in std_logic_vector(15 downto 0);
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_error           : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_error          : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_data64to32bits is
+	port(
+		clock                   : in std_logic; 
+		clock_UDP               : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_error           : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		ll_data                 : out std_logic_vector(31 downto 0);
+		ll_sof_n                : out std_logic;
+		ll_eof_n                : out std_logic;
+		ll_src_ready_n          : out std_logic;
+		ll_dst_ready_n          : in std_logic;
+		error                   : out std_logic;
+		testword0               : out std_logic_vector(35 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_fiforead2write is
+	generic(
+		BITS                    : integer := 32
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic; 
+		data_in                 : in std_logic_vector(BITS-1 downto 0);
+		data_in_empty           : in std_logic;
+		data_in_read            : out std_logic;
+		data_out                : out std_logic_vector(BITS-1 downto 0);
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic
+	); 
+end component;
+
+component CN_checkdata is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_error           : in std_logic;
+		data_in_write           : in std_logic;
+		dataerror               : out std_logic;
+		timeerror               : out std_logic;
+		waveerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_checkcluster is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		headerword0             : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_error           : in std_logic;
+		data_in_write           : in std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component sync_bit is
+	port (
+		clock       : in  std_logic;
+		data_in     : in  std_logic;
+		data_out    : out std_logic
+	);
+end component;
+
+component CN_preclustering is
+	generic(
+		XYPAD_BITSIZE           : natural := 8;
+		CLUSTERBITS             : natural := 8;
+		MAXCLUSTERSBITS         : natural := 5;
+		PARALLELBUILDS          : natural := 4;
+		MINIMUMENERGYBITS       : natural := 8;
+		SKIPSINGLEHITCLUSTERS   : boolean := FALSE;
+		HEADERWORD0             : boolean := TRUE   
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		gap_time                : in std_logic_vector(23 downto 0);
+		timedifference          : in std_logic_vector(23 downto 0);
+		minimal_energy          : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+		XYLUT_write             : in std_logic;
+		XYLUT_load              : in std_logic;
+		XYLUT_data              : in std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_allowed        : in std_logic;
+		superburst_rewind       : out std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0)
+	); 
+end component;
+
+component CN_combineclusters is
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		data_in                 : in CN_inputs64bits_type;
+		data_in_first           : in std_logic_vector(0 to NROFCNINPUTS-1);
+		data_in_last            : in std_logic_vector(0 to NROFCNINPUTS-1);
+		data_in_write           : in std_logic_vector(0 to NROFCNINPUTS-1);
+		data_in_exists          : in std_logic_vector(0 to NROFCNINPUTS-1);
+		data_in_allowed         : out std_logic_vector(0 to NROFCNINPUTS-1);
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_allowed        : in std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+
+component CN_clustering is
+	generic(
+		CLUSTERBITS             : natural := 9;
+		MAXCLUSTERSBITS         : natural := 5;
+		PARALLELBUILDS          : natural := 4;
+		HEADERWORD0             : boolean := FALSE;
+		MINIMUMENERGYBITS       : natural := 8;
+		SKIPSINGLEHITCLUSTERS   : boolean := FALSE
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		gap_time                : in std_logic_vector(23 downto 0);
+		timedifference          : in std_logic_vector(23 downto 0);
+		minimal_energy          : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+		onedgeLUT_write         : in std_logic;
+		onedgeLUT_load          : in std_logic;
+		onedgeLUT_data          : in std_logic;
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_allowed        : in std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end component;
+		
+end CN_package;
diff --git a/data_concentrator/sources/cluster/CN_precluster_build.vhd b/data_concentrator/sources/cluster/CN_precluster_build.vhd
new file mode 100644
index 0000000..7d93030
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_precluster_build.vhd
@@ -0,0 +1,1305 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   26-06-2016
+-- Module Name:   CN_precluster_build
+-- Description:   Construct clusters from a bunch of hits
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+use std.textio.all;
+use IEEE.std_logic_textio.all; -- I/O for logic types
+  
+----------------------------------------------------------------------------------
+-- CN_precluster_build
+-- Construct clusters from a bunch of hits, based on time and XY-position
+-- C-software developed by Marcel Tiemens
+-- Input hit-data from module that splits up a stream in timebunches:
+-- If a cluster contains only one hit and if this hit is not position on the edge of the region then this cluster is skipped.
+--
+-- Input data from CN_precluster_findgap module:
+-- 64bits word1:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+-- 64bits word2 and further, for each hit:   
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+--
+-- Output packets with 64 bits data words:
+-- 64bits word1:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+--    for cluster data
+-- 64bits word2, clusterresults
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..30  = diameter
+--        bit29..20  = Y position, multiplied by 2
+--        bit19..10  = X position, multiplied by 2
+--        bit9..0    = number of hits in cluster
+-- 64bits word3..word3+nrofhits : pulse data
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+-- Criteria neighbours:
+--       crystal-positions (X0pos,Y0pos) and (X1pos,Y1pos) are neighbours :
+--       if (((X0pos+1==X1pos) or (X0pos==X1pos+1) or (X0pos==X1pos)) and
+--            (Y0pos+1==Y1pos) or (Y0pos==Y1pos+1) or (Y0pos==Y1pos)) and
+--            (time1-time0<=timedifference))
+--
+--
+--
+-- Library
+--
+-- 
+-- Generics:
+--      XYPAD_BITSIZE : number of bits for the X and Y position 
+--      CLUSTERBITS : number of bits for the number of hits in one timebunch
+--      MAXCLUSTERSBITS : number of bits for the maximum clusters in one timebunch
+--      MINIMUMENERGYBITS : number of bits for the miminum energy value
+--      SKIPSINGLEHITCLUSTERS : skip precluster if it contains only one hit and is not positioned on the edge
+-- 
+-- Inputs:
+--      clock : clock
+--      reset : reset
+--      timedifference : maximum difference in time between hits in a cluster, resolutie from Constant Fraction (6.1ps)
+--      minimal_energy : minimum energy for a cluster; clusters with less are skipped if they are not positioned on the edge of a region
+--      data_in : 64-bits input data
+--      data_in_Xpad : X-position of the crystal of the hit
+--      data_in_Ypad : Y-position of the crystal of the hit
+--      data_in_onedge : '1' if the hit is on the edge of the XY-area, not yet used
+--      data_in_active : timebunch active
+--      data_in_write : write signal for hitdata
+--      data_in_first : indicates that the data contains new superburst number
+--      data_in_last : indicates that the hit is the last one in a superburst
+--      data_out_clusterallowed : allowed to write clusters to output
+--      
+-- Outputs:
+--      data_in_allowed : writing of input data allowed 
+--      busy : busy processing timebunch
+--      data_out : 64 bits output data
+--      data_out_write : write signal for 64 bits output data
+--      data_out_first : 64 bits output data contains the new superburst number
+--      data_out_last : 64 bits output data is the last of a superburst (not necessarily the same as timebunch)
+--      nextcluster : signal that indicates the last data of a timebunch
+--      dataerror : error in data
+-- 
+-- Components:
+--      blockmem : synchronous memory block 
+--      blockmemdirectread : synchronous memory block from which the output reacts directly on the written value
+--
+----------------------------------------------------------------------------------
+
+entity CN_precluster_build is
+	generic(
+		XYPAD_BITSIZE           : natural := 8;
+		CLUSTERBITS             : natural := 8;
+		MAXCLUSTERSBITS         : natural := 5;
+		MINIMUMENERGYBITS       : natural := 8;
+		SKIPSINGLEHITCLUSTERS   : boolean := FALSE
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		timedifference          : in std_logic_vector(23 downto 0);
+		minimal_energy          : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_Xpad            : in std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+		data_in_Ypad            : in std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+		data_in_onedge          : in std_logic;
+		data_in_active          : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_allowed         : out std_logic;
+		busy                    : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_clusterallowed : in std_logic;
+		nextcluster             : out std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(36 downto 0) := (others => '0')
+	); 
+end CN_precluster_build;
+
+
+architecture behaviour of CN_precluster_build is
+
+component blockmem is
+	generic (
+		ADDRESS_BITS : natural := 16;
+		DATA_BITS  : natural := 32
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+component blockmemdirectread is
+	generic (
+		ADDRESS_BITS : natural := 16;
+		DATA_BITS  : natural := 32
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end component;
+
+constant ONES                       : std_logic_vector(63 downto 0) := (others => '1');
+constant ZEROS                      : std_logic_vector(63 downto 0) := (others => '0');
+type state_type is (INITIALIZE,COLLECT,PRE_READ0,PRE_READ1,PRIMARY,PRIMARY1,PRIMARY1_0,PRIMARY2,PRIMARY2_0,
+							SECONDAIRY,SECONDAIRY1,ADJUSTSIMULARITIES,SECONDAIRY2,SORTING,
+							WRITESUPERBURST,WRITECLUSTER,WRITEHITS0,WRITEHITS);
+signal state_S                      : state_type := INITIALIZE;
+signal nextstate_S                  : state_type;
+signal stateprev_S                  : state_type;
+
+signal error_S                      : std_logic := '0';
+signal data_in_write_S              : std_logic;
+signal data_write_address_S         : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_S          : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_f_S        : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_address_prev_S     : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal data_read_nextaddress_S      : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal minimal_energy_S             : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+
+
+signal datamem_in_S                 : std_logic_vector(16+8+16+24+2*XYPAD_BITSIZE downto 0);
+signal datamem_out_S                : std_logic_vector(16+8+16+24+2*XYPAD_BITSIZE downto 0);
+signal data_in_channel_S            : std_logic_vector(15 downto 0);
+signal data_in_statusbyte_S         : std_logic_vector(7 downto 0);
+signal data_in_energy_S             : std_logic_vector(15 downto 0);
+signal data_in_time_S               : std_logic_vector(23 downto 0);
+signal data_in_Xpad_S               : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data_in_Ypad_S               : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data_in_onedge_S             : std_logic;
+signal data0_channel_S              : std_logic_vector(15 downto 0);
+signal data0_statusbyte_S           : std_logic_vector(7 downto 0);
+signal data0_energy_S               : std_logic_vector(15 downto 0);
+signal data0_time_S                 : std_logic_vector(23 downto 0);
+signal data0_Xpad_S                 : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data0_Ypad_S                 : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data0_onedge_S               : std_logic;
+signal data_first_S                 : std_logic := '0';
+signal data_last_S                  : std_logic := '0';
+
+
+signal neighbours_write_S           : std_logic;
+signal neighbours_data_in_S         : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_data_out_S        : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_data_prev_S       : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal nNeighbours_S                : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal neighbours_write_address_S   : std_logic_vector(CLUSTERBITS+1 downto 0) := (others => '0');
+signal neighbours_read_address_S    : std_logic_vector(CLUSTERBITS+1 downto 0) := (others => '0');
+signal neighbours_index_S           : std_logic_vector(CLUSTERBITS+1 downto 0);
+signal neighbours_count_index_S     : std_logic_vector(CLUSTERBITS+1 downto 0);
+
+signal nDigis_S                     : integer range 0 to 2**CLUSTERBITS-1 := 0;
+signal only_one_hit_S               : std_logic;
+signal overflow_S                   : std_logic := '0';
+signal data_read_first_S            : std_logic;
+signal data_read_last_S             : std_logic;
+
+signal prim_k_S                     : integer range 0 to 2**CLUSTERBITS-1;
+
+signal nClusters_S                  : integer range 0 to 2**CLUSTERBITS-1;
+signal simLength_S                  : integer range 0 to 2**CLUSTERBITS-1;
+
+signal isAdded_write_S              : std_logic;
+signal isAdded_write_address_S      : std_logic_vector(CLUSTERBITS-1 downto 0) := (others => '0');
+signal isAdded_read_address_S       : std_logic_vector(CLUSTERBITS-1 downto 0) := (others => '0');
+signal isAdded_read_address_f_S     : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal isadded_read_address_aftr1clk_s : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal isAdded_data_in_S            : std_logic_vector(CLUSTERBITS downto 0);
+signal isAdded_data_out_S           : std_logic_vector(CLUSTERBITS downto 0);
+signal isAdded_k_S                  : std_logic_vector(CLUSTERBITS downto 0);
+
+signal nrofneighbours_s             : integer range 0 to 2**CLUSTERBITS-1;
+signal prim_m_S                     : integer range 0 to 2**CLUSTERBITS-1;
+signal prim_j_s                     : integer range 0 to 2**CLUSTERBITS-1;
+--type similarities_type is array(0 to 2*(2**CLUSTERBITS)-1) of std_logic_vector(CLUSTERBITS-1 downto 0);
+--signal similarities_s               : similarities_type;
+
+signal similarities_write_S         : std_logic;
+signal similarities_write_address_S : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_data_in_S       : std_logic_vector(CLUSTERBITS*2-1 downto 0);
+signal similarities_read_address_S  : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_data_out_S      : std_logic_vector(CLUSTERBITS*2-1 downto 0);
+signal similarities_source_S        : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal similarities_destination_S   : std_logic_vector(CLUSTERBITS-1 downto 0);
+
+
+signal sec1_i_S                     : integer range 0 to 2**CLUSTERBITS-1;
+signal sec1_j_S                     : integer range 0 to 2**CLUSTERBITS-1;
+signal sec1_m_S                     : integer range 0 to 2**CLUSTERBITS-1;
+signal sec2_i_S                     : integer range 0 to 2**CLUSTERBITS-1;
+signal sec2_n_S                     : std_logic;
+signal nPreclusters_S               : integer range 0 to 2**CLUSTERBITS-1;
+
+signal result_diameter_S            : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal result_positionX_S           : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal result_positionY_S           : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal result_time_S                : std_logic_vector(23 downto 0);
+signal result_index_S               : integer range 0 to 2**CLUSTERBITS-1;
+signal result_nrofhits_S            : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal result_onedge_S              : std_logic;
+
+signal results_write_address_S      : std_logic_vector(MAXCLUSTERSBITS-1 downto 0);
+signal results_read_address_S       : std_logic_vector(MAXCLUSTERSBITS-1 downto 0);
+signal results_data_in_S            : std_logic_vector(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+24-1 downto 0);
+signal results_data_out_S           : std_logic_vector(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+24-1 downto 0);
+signal results_write_S              : std_logic;
+signal results_index_s              : integer range 0 to 2**CLUSTERBITS-1;
+signal results_filled_S             : std_logic;
+
+signal hitidx_write_address_S       : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_data_in_S             : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_read_address_S        : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_data_out_S            : std_logic_vector(CLUSTERBITS-1 downto 0);
+signal hitidx_write_S               : std_logic;
+signal hitidx_index_S               : integer range 0 to 2**CLUSTERBITS-1;
+signal hitidx_endaddress_s          : integer range 0 to 2**CLUSTERBITS-1;
+		
+signal nrofclocks_S                 : integer range 0 to 16383;
+signal isAdded_int_in_S             : integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+signal isAdded_int_out_S            : integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+
+signal sort_readkey_s               : std_logic;
+type clustersortarray_type is array(0 to 2**MAXCLUSTERSBITS-1) of integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal clustersortarray_s           : clustersortarray_type;
+signal sort_i_s                     : integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal sort_j_s                     : integer range 0 to 2**MAXCLUSTERSBITS-1;
+signal sort_j_neg_S                 : std_logic;
+signal sort_key_S                   : std_logic_vector(23 downto 0) := (others => '0');
+
+signal data_out_S                   : std_logic_vector(63 downto 0);
+signal data_out_write_S             : std_logic;
+signal data_out_first_S             : std_logic;
+signal data_out_last_S              : std_logic;
+signal nextcluster_S                : std_logic;
+
+
+
+--type isAdded_array is array(0 to 2**CLUSTERBITS-1) of integer range -2**CLUSTERBITS to 2**CLUSTERBITS-1;
+--signal debug_isAdded_S              : isAdded_array;
+signal debug_error_S                : std_logic;
+signal debug_minimal_energy_reached_S : std_logic;
+
+attribute mark_debug : string;
+attribute mark_debug of debug_error_S : signal is "true";
+
+begin
+
+dataerror <= error_S;
+data_in_allowed <= '1' when (state_S=INITIALIZE) or (state_S=COLLECT) else '0';
+busy <= '1' when (state_S/=INITIALIZE) else '0';
+data_in_write_S <= '1' when (data_in_write='1') and (data_in_first='0') else '0';
+minimal_energy_S <= minimal_energy;
+
+datamemory: blockmem 
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS,
+		DATA_BITS => 16+8+16+24+2*XYPAD_BITSIZE+1
+	)
+	port map(
+		clock => clock,
+		write_enable => data_in_write_S,
+		write_address => data_write_address_S,
+		data_in => datamem_in_S,
+		read_address => data_read_address_f_S,
+		data_out => datamem_out_S
+	);
+
+datamem_in_S(15 downto 0) <= data_in(31 downto 16); -- channel
+datamem_in_S(23 downto 16) <= data_in(39 downto 32); -- statusbyte
+datamem_in_S(39 downto 24) <= data_in(15 downto 0); -- energy
+datamem_in_S(63 downto 40) <= data_in(63 downto 40); -- time
+datamem_in_S(63+XYPAD_BITSIZE downto 64) <= data_in_Xpad;
+datamem_in_S(63+2*XYPAD_BITSIZE downto 64+XYPAD_BITSIZE) <= data_in_Ypad;
+datamem_in_S(64+2*XYPAD_BITSIZE) <= data_in_onedge;
+data_in_channel_S <= datamem_out_S(15 downto 0);
+data_in_statusbyte_S <= datamem_out_S(23 downto 16);
+data_in_energy_S <= datamem_out_S(39 downto 24);
+data_in_time_S <= datamem_out_S(63 downto 40);
+data_in_Xpad_S <= datamem_out_S(63+XYPAD_BITSIZE downto 64);
+data_in_Ypad_S <= datamem_out_S(63+2*XYPAD_BITSIZE downto 64+XYPAD_BITSIZE);
+data_in_onedge_S <= datamem_out_S(64+2*XYPAD_BITSIZE);
+
+
+	
+neighbours: blockmemdirectread 
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS+2,
+		DATA_BITS => CLUSTERBITS
+	)
+	port map(
+		clock => clock,
+		write_enable => neighbours_write_S,
+		write_address => neighbours_write_address_S,
+		data_in => neighbours_data_in_S,
+		read_address => neighbours_read_address_S,
+		data_out => neighbours_data_out_S
+	);
+
+
+isAddedmem: blockmemdirectread 
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS,
+		DATA_BITS => CLUSTERBITS+1
+	)
+	port map(
+		clock => clock,
+		write_enable => isAdded_write_S,
+		write_address => isAdded_write_address_S,
+		data_in => isAdded_data_in_S,
+		read_address => isAdded_read_address_f_S,
+		data_out => isAdded_data_out_S
+	);
+isAdded_int_in_S <= -1 when isAdded_data_in_S(CLUSTERBITS)='0' else conv_integer(unsigned(isAdded_data_in_S(CLUSTERBITS-1 downto 0)));
+isAdded_int_out_S <= -1 when isAdded_data_out_S(CLUSTERBITS)='0' else conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)));
+	
+similarities: blockmemdirectread 
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS,
+		DATA_BITS => CLUSTERBITS*2
+	)
+	port map(
+		clock => clock,
+		write_enable => similarities_write_S,
+		write_address => similarities_write_address_S,
+		data_in => similarities_data_in_S,
+		read_address => similarities_read_address_S,
+		data_out => similarities_data_out_S
+	);
+
+results: blockmemdirectread
+	generic map (
+		ADDRESS_BITS => MAXCLUSTERSBITS,
+		DATA_BITS => 2*CLUSTERBITS+XYPAD_BITSIZE*3+2+24
+	)
+	port map(
+		clock => clock,
+		write_enable => results_write_S,
+		write_address => results_write_address_S,
+		data_in => results_data_in_S,
+		read_address => results_read_address_S,
+		data_out => results_data_out_S
+	);
+
+hitidices: blockmem
+	generic map (
+		ADDRESS_BITS => CLUSTERBITS,
+		DATA_BITS => CLUSTERBITS
+	)
+	port map(
+		clock => clock,
+		write_enable => hitidx_write_S,
+		write_address => hitidx_write_address_S,
+		data_in => hitidx_data_in_S,
+		read_address => hitidx_read_address_S,
+		data_out => hitidx_data_out_S
+	);
+	
+data_read_address_f_S <=
+	hitidx_data_out_S when (state_S=WRITECLUSTER) else
+	hitidx_data_out_S when (state_S=WRITEHITS0) else
+	hitidx_data_out_S when (state_S=WRITEHITS) else
+	data_read_address_S;
+
+isAdded_read_address_f_S <= 
+--	data_write_address_S-1 when (state_S=PRIMARY) and (neighbours_read_address_S>=neighbours_count_index_S) else
+	data_write_address_S-1 when (state_S=PRIMARY) and (not ((neighbours_read_address_S<neighbours_count_index_S) or ((neighbours_count_index_S=1) and (neighbours_read_address_S=1)))) else
+	data_write_address_S-1 when (state_S=PRIMARY) and (neighbours_read_address_S>=neighbours_count_index_S) else
+	conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY) and (conv_integer(unsigned(neighbours_data_out_S))=0) else
+	conv_std_logic_vector(prim_k_S,CLUSTERBITS) when (state_S=PRIMARY) else
+	
+	neighbours_data_out_S when (state_S=PRIMARY1) else
+	neighbours_data_out_S when (state_S=PRIMARY1_0) and (prim_j_S<nrofneighbours_S-1) else
+	
+	conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY1_0) and (prim_j_S>=nrofneighbours_S-1) else
+	neighbours_data_out_S when (state_S=PRIMARY2) else
+	neighbours_data_out_S when (state_S=PRIMARY2_0) and (prim_j_S<nrofneighbours_S-1) else
+	conv_std_logic_vector(prim_k_S+1,CLUSTERBITS) when (state_S=PRIMARY2_0) and (prim_j_S>=nrofneighbours_S-1) else
+	
+	conv_std_logic_vector(sec1_m_S,CLUSTERBITS) when (state_S=SECONDAIRY) else
+	
+	(others => '0') when ((state_S=SECONDAIRY1) and ((simLength_S=0) or ((sec1_i_S=simLength_S-1) and (sec1_m_S=conv_integer(unsigned(data_write_address_S))-1)))) else
+	conv_std_logic_vector(sec1_m_S+1,CLUSTERBITS) when (state_S=SECONDAIRY1) and (sec1_m_S<conv_integer(unsigned(data_write_address_S))-1) and
+		(similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) else
+	(others => '0') when (state_S=SECONDAIRY1) else
+
+	conv_std_logic_vector(sec1_m_S,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) else
+
+	conv_std_logic_vector(sec1_m_S+1,CLUSTERBITS) when (state_S=SECONDAIRY2) and (sec1_m_S<conv_integer(unsigned(data_write_address_S))-1) else
+	(others => '0') when (state_S=SECONDAIRY2) and (sec1_m_S>=conv_integer(unsigned(data_write_address_S))) else
+	
+	isAdded_read_address_S;
+	
+similarities_read_address_S <=
+	(others => '0') when (state_S=SECONDAIRY) else
+	conv_std_logic_vector(sec1_i_S,CLUSTERBITS) when (state_S=SECONDAIRY1) and (sec1_m_S<conv_integer(unsigned(data_write_address_S))-1) and
+		(similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) else
+	conv_std_logic_vector(sec1_i_S+1,CLUSTERBITS) when (state_S=SECONDAIRY1) else
+	conv_std_logic_vector(sec1_i_S,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) and (sec1_j_S=simLength_S-1) else
+	conv_std_logic_vector(sec1_j_S+1,CLUSTERBITS) when (state_S=ADJUSTSIMULARITIES) else
+	(others => '0');
+				
+results_read_address_S <= 
+	conv_std_logic_vector(1,MAXCLUSTERSBITS) when (state_S=SECONDAIRY1) else
+	conv_std_logic_vector(clustersortarray_S(sort_i_S-1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='1') and (results_filled_S='1') and (sort_i_S<=results_write_address_S) else
+	conv_std_logic_vector(clustersortarray_S(sort_i_S),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='1') else
+	conv_std_logic_vector(clustersortarray_S(sort_j_S-1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING)) and (sort_readkey_S='0') and (sort_j_S>0) and (sort_j_neg_S='0') and (results_data_out_S(XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2)>sort_key_S) else
+	conv_std_logic_vector(clustersortarray_S(sort_i_S+1),MAXCLUSTERSBITS) when ((state_S=SECONDAIRY2) or (state_S=SORTING))  else
+	conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITESUPERBURST else
+	conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITECLUSTER else
+	conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITEHITS else
+	conv_std_logic_vector(clustersortarray_S(results_index_S),MAXCLUSTERSBITS) when state_S=WRITEHITS0 else
+	(others => '0');
+		
+hitidx_read_address_S <=				
+	results_data_out_S(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto CLUSTERBITS+XYPAD_BITSIZE*3+2+24) when (state_S=WRITESUPERBURST) else
+	results_data_out_S(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto CLUSTERBITS+XYPAD_BITSIZE*3+2+24) when (state_S=WRITECLUSTER) else
+	conv_std_logic_vector(hitidx_index_S+1,CLUSTERBITS) when (state_S=WRITEHITS0) else
+	conv_std_logic_vector(hitidx_index_S+1,CLUSTERBITS) when (state_S=WRITEHITS) and (hitidx_index_S<hitidx_endaddress_S-1) else
+	conv_std_logic_vector(hitidx_index_S,CLUSTERBITS) when (state_S=WRITEHITS) else
+	(others => '0');
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		neighbours_write_S <= '0';
+		case state_S is
+			when INITIALIZE =>
+				for i in 0 to 2**MAXCLUSTERSBITS-1 loop
+					clustersortarray_S(i) <= i;
+				end loop;
+			when COLLECT =>
+				neighbours_index_S <= (others => '0');
+				neighbours_index_S(0) <= '1';
+				neighbours_count_index_S <= (others => '0');
+				nNeighbours_S <= (others => '0');
+				data_read_first_S <= '1';
+			when PRE_READ0 =>
+				neighbours_write_address_S <= neighbours_count_index_S;
+				neighbours_data_in_S <= nNeighbours_S;
+				neighbours_write_S <= '1';
+				if (data_read_first_S='0') then -- and (data_read_last_S='0') then
+					neighbours_count_index_S <= neighbours_index_S;
+					neighbours_index_S <= neighbours_index_S+1;
+				else
+					data_read_first_S <= '0';
+				end if;
+				nNeighbours_S <= (others => '0');
+			when PRE_READ1 =>
+				if ((conv_integer(unsigned(data0_Xpad_S))+1=conv_integer(unsigned(data_in_Xpad_S))) or 
+					(conv_integer(unsigned(data0_Xpad_S))=conv_integer(unsigned(data_in_Xpad_S))+1) or 
+					(conv_integer(unsigned(data0_Xpad_S))=conv_integer(unsigned(data_in_Xpad_S)))) and 
+					((conv_integer(unsigned(data0_Ypad_S))+1=conv_integer(unsigned(data_in_Ypad_S))) or 
+					(conv_integer(unsigned(data0_Ypad_S))=conv_integer(unsigned(data_in_Ypad_S))+1) or 
+					(conv_integer(unsigned(data0_Ypad_S))=conv_integer(unsigned(data_in_Ypad_S)))) and
+					(data_in_time_S-data0_time_S<=timedifference) then
+					neighbours_write_address_S <= neighbours_index_S;
+					neighbours_data_in_S <= data_read_address_prev_S;
+					neighbours_write_S <= '1';
+					neighbours_index_S <= neighbours_index_S+1;
+					nNeighbours_S <= nNeighbours_S+1;
+				else
+				end if;
+			when SECONDAIRY1 =>
+				sort_i_S <= 1;
+				sort_readkey_S <= '1';
+				-- results_read_address_S <= 1;
+			when SECONDAIRY2 | SORTING =>
+				-- for (int i = 1; i < nPreclusters; i++)
+				-- {
+					-- int key = clusters_time[clustersortarray[i]];
+					-- int j = i - 1;
+					-- while (j >= 0 && clusters_time[clustersortarray[j]] > key)
+					-- {
+						-- clustersortarray[j + 1] = clustersortarray[j];
+						-- j = j - 1;
+					-- }
+					-- clustersortarray[j + 1] = i;
+				-- }
+				if sort_readkey_S='1' then
+					if (results_filled_S='1') and (sort_i_S<=results_write_address_S) then
+						sort_key_S <= results_data_out_S(XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2);
+						sort_readkey_S <= '0';
+						sort_j_S <= sort_i_S-1;
+						sort_j_neg_S <= '0';
+						-- results_read_address_S <= clustersortarray_S(sort_i_S-1);
+					else
+						-- results_read_address_S <= clustersortarray_S(sort_i_S);
+					end if;
+				else
+					if (sort_j_neg_S='0') and (results_data_out_S(XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2)>sort_key_S) then
+						-- results_read_address_S <= clustersortarray_S(sort_j_S-1);
+						clustersortarray_S(sort_j_S+1) <= clustersortarray_S(sort_j_S);
+						if sort_j_S>0 then
+							sort_j_S <= sort_j_S-1;
+							sort_j_neg_S <= '0';
+						else
+							sort_j_neg_S <= '1';
+						end if;
+					else
+						-- results_read_address_S <= clustersortarray_S(sort_i_S+1);
+						if sort_j_neg_S='1' then
+							clustersortarray_S(0) <= sort_i_S;
+						else
+							clustersortarray_S(sort_j_S+1) <= sort_i_S;
+						end if;
+						sort_i_S <= sort_i_S+1;
+						sort_readkey_S <= '1';
+					end if;
+				end if;
+			when others =>
+		end case;
+		stateprev_S <= state_S;
+	end if;
+end process;
+
+
+process(clock)
+file dfile: text;
+variable l : line;
+variable result_startaddress_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+variable result_nrofhits_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+variable result_Xpad_min_V : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+variable result_Ypad_min_V : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+variable result_Xpad_max_V : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+variable result_Ypad_max_V : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+variable result_diameter_V : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+variable result_positionX_V : std_logic_vector(XYPAD_BITSIZE downto 0);
+variable result_positionY_V : std_logic_vector(XYPAD_BITSIZE downto 0);
+variable result_energy_max_V : std_logic_vector(15 downto 0);
+variable result_time_max_V : std_logic_vector(23 downto 0);
+variable result_onedge_V : std_logic;
+variable sum_energy_V : std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+variable minimal_energy_reached_V : std_logic;
+variable nPreclusters_V : integer range 0 to 2**CLUSTERBITS-1 := 0;
+variable hitidx_write_address_V : std_logic_vector(CLUSTERBITS-1 downto 0);
+begin
+	if (rising_edge(clock)) then
+		error_S <= '0';
+		isAdded_read_address_aftr1clk_S <= isAdded_read_address_f_S;
+		only_one_hit_S <= '0';
+		nextcluster_S <= '0';
+		isAdded_write_S <= '0';
+		data_out_write_S <= '0';
+		data_out_first_S <= '0';
+		data_out_last_S <= '0';
+		similarities_write_S <= '0';
+		results_write_S <= '0';
+		hitidx_write_S <= '0';
+		case state_S is
+			when INITIALIZE =>
+				nDigis_S <= 0;
+				nClusters_S <= 0;
+				nPreclusters_S <= 0;
+				results_index_S <= 0;
+				result_onedge_V := '0';
+				data_write_address_S <= (others => '0');
+				data_read_address_S <= (others => '0');
+				data_read_nextaddress_S <= (others => '0');
+				hitidx_data_in_S <= (others => '0');
+				hitidx_write_address_S <= (others => '0');
+				hitidx_write_S <='1';
+				minimal_energy_reached_V := '0';
+				if (data_in_write='1') and (data_in_last='1') then
+					data_last_S <= '1';
+				end if;
+				if (data_in_write='1') and (data_in_first='1') then
+					data_first_S <= '1';
+					data_out_S <= data_in;
+				end if;
+				if (data_in_write_S='1') and (data_in_active='1') then
+					result_onedge_V := data_in_onedge;
+					if conv_integer(unsigned(data_in(15 downto 0)))>=conv_integer(unsigned(minimal_energy_S)) then
+						minimal_energy_reached_V := '1';
+					end if;
+				end if;
+				if data_in_active='1' then
+					if data_in_write_S='1' then
+						data_write_address_S(0) <= '1';
+						nDigis_S <= 1;
+					end if;
+					state_S <= COLLECT;
+				elsif data_in_write='1' then -- empty superburst
+					data_out_S <= data_in;
+					if (data_in_first='0') or (data_in_last='0') then
+						error_S <= '1';
+					end if;
+					state_S <= WRITESUPERBURST;
+				end if;
+				overflow_S <= '0';
+				isAdded_data_in_S <= (others => '0');
+				if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then 
+					isAdded_write_S <= '1';
+					isAdded_write_address_S <= isAdded_write_address_S+1;
+				end if;
+			when COLLECT =>
+				if (data_in_write='1') and (data_in_last='1') then
+					data_last_S <= '1';
+				end if;
+				if (data_in_write='1') and (data_in_first='1') then
+					data_first_S <= '1';
+					data_out_S <= data_in;
+				end if;
+				if (data_in_write_S='1') then
+					result_onedge_V := data_in_onedge;
+					if conv_integer(unsigned(data_in(15 downto 0)))>=conv_integer(unsigned(minimal_energy_S)) then
+						minimal_energy_reached_V := '1';
+					end if;
+				end if;
+				neighbours_read_address_S <= (others => '0');
+				data_read_last_S <= '0';
+				data_read_address_S <= (others => '0');
+				data_read_nextaddress_S <= (others => '0');
+				if data_in_active='0' then
+					if nDigis_S=0 then 
+						data_first_S <= '0';
+						data_last_S <= '0';
+						isAdded_data_in_S <= (others => '0');
+						isAdded_write_S <= '1';
+						isAdded_write_address_S <= (others => '0');
+						nextcluster_S <= '1';
+						data_write_address_S <= (others => '0');
+						state_S <= INITIALIZE;
+					elsif nDigis_S=1 then 
+						if (SKIPSINGLEHITCLUSTERS=FALSE) or (result_onedge_V='1') or (minimal_energy_reached_V='1') then 
+							-- or (((data_last_S='1') or ((data_in_write='1') and (data_in_last='1'))) and (data_first_S='0')) then
+							only_one_hit_S <= '1';
+							data_write_address_S <= (others => '0');
+							data_write_address_S(0) <= '1';
+							state_S <= WRITESUPERBURST;
+						else -- skip this hit
+							state_S <= WRITESUPERBURST;
+						end if;
+					else
+						state_S <= PRE_READ0;
+						data_read_address_S(0) <= '1';
+					end if;
+				else
+					if data_in_write_S='1' then
+						if data_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then
+							data_write_address_S <= data_write_address_S+1;
+							nDigis_S <= nDigis_S+1;
+						else
+							overflow_S <= '1';
+						end if;
+					end if;
+				end if;
+				isAdded_data_in_S <= (others => '0');
+				if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then 
+					isAdded_write_S <= '1';
+					isAdded_write_address_S <= isAdded_write_address_S+1;
+				end if;
+			when PRE_READ0 =>
+				neighbours_read_address_S <= (others => '0');
+				isAdded_data_in_S <= (others => '0');
+				if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then 
+					isAdded_write_S <= '1';
+					isAdded_write_address_S <= isAdded_write_address_S+1;
+				end if;
+				isAdded_read_address_S <= (others => '0');
+				data0_channel_S <= data_in_channel_S;
+				data0_statusbyte_S <= data_in_statusbyte_S;
+				data0_energy_S <= data_in_energy_S;
+				data0_time_S <= data_in_time_S;
+				data0_Xpad_S <= data_in_Xpad_S;
+				data0_Ypad_S <= data_in_Ypad_S;
+				data0_onedge_S <= data_in_onedge_S;
+				if data_read_last_S='1' then
+					if (neighbours_index_S>1) then
+						neighbours_read_address_S(0) <= '1';
+					end if;
+					prim_k_S <= 0;
+					nClusters_S <= 0;
+					simLength_S <= 0;
+					state_S <= PRIMARY;
+				elsif data_read_address_S<data_write_address_S-1 then
+					data_read_address_S <= data_read_address_S+1;
+					data_read_nextaddress_S <= data_read_nextaddress_S+1;
+					state_S <= PRE_READ1;
+					nextstate_S <= PRE_READ1;
+				else
+					state_S <= PRE_READ1;
+					nextstate_S <= PRE_READ0;
+					data_read_last_S <= '1';
+				end if;
+			when PRE_READ1 =>
+				isAdded_data_in_S <= (others => '0');
+				if isAdded_write_address_S/=ONES(CLUSTERBITS-1 downto 0) then 
+					isAdded_write_S <= '1';
+					isAdded_write_address_S <= isAdded_write_address_S+1;
+				end if;
+				neighbours_read_address_S <= (others => '0');
+				if data_read_address_S<data_write_address_S-1 then
+					data_read_address_S <= data_read_address_S+1;
+				else
+					data_read_address_S <= data_read_nextaddress_S;
+					nextstate_S <= PRE_READ0;
+				end if;
+				state_S <= nextstate_S;
+			when PRIMARY =>
+				sec1_i_S <= 0;
+				sec1_m_S <= 0;
+				if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+					isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters_S,CLUSTERBITS);
+					isAdded_write_address_S <= conv_std_logic_vector(prim_k_S,CLUSTERBITS);
+					isAdded_write_S <= '1';
+					nrofneighbours_S <= conv_integer(unsigned(neighbours_data_out_S));
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+					if conv_integer(unsigned(neighbours_data_out_S))>0 then
+						prim_j_S <= 0;
+						state_S <= PRIMARY1;
+					else
+						--????
+						prim_k_S <= prim_k_S+1;
+						nClusters_S <= nClusters_S+1;						
+--						neighbours_read_address_S <= neighbours_read_address_S+1;
+					end if;
+				else
+					nrofneighbours_S <= conv_integer(unsigned(neighbours_data_out_S));
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+					if conv_integer(unsigned(neighbours_data_out_S))>0 then
+						prim_j_S <= 0;
+						state_S <= PRIMARY2;
+					else
+						--????
+						prim_k_S <= prim_k_S+1;
+--						neighbours_read_address_S <= neighbours_read_address_S+1;
+					end if;
+				end if;
+--				if (neighbours_read_address_S<neighbours_count_index_S) or ((neighbours_count_index_S=1) and (neighbours_read_address_S=1))  then -- neighbours_count_index_S contains size of neighbour array
+--					else
+				if (neighbours_read_address_S>=neighbours_count_index_S) then -- neighbours_count_index_S contains size of neighbour array
+					state_S <= SECONDAIRY;
+				end if;
+			when PRIMARY1 =>
+				prim_m_S <= conv_integer(unsigned(neighbours_data_out_S));
+				if (nrofneighbours_S>1) then
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+				end if;
+				neighbours_data_prev_S <= neighbours_data_out_S;
+				state_S <= PRIMARY1_0;
+			when PRIMARY1_0 =>
+				if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+					isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters_S,CLUSTERBITS);
+					isAdded_write_address_S <= neighbours_data_prev_S; -- conv_std_logic_vector(prim_m_S,CLUSTERBITS);
+					isAdded_write_S <= '1';
+				elsif conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))/=nClusters_S then 
+					if nClusters_S>conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0))) then
+						similarities_data_in_S <= conv_std_logic_vector(nClusters_S,CLUSTERBITS) & isAdded_data_out_S(CLUSTERBITS-1 downto 0);
+					else
+						similarities_data_in_S <= isAdded_data_out_S(CLUSTERBITS-1 downto 0) & conv_std_logic_vector(nClusters_S,CLUSTERBITS);
+					end if;
+					similarities_write_S <= '1';
+					similarities_write_address_S <= conv_std_logic_vector(simLength_S,CLUSTERBITS);
+					simLength_S <= simLength_S+1;
+				end if;
+				neighbours_data_prev_S <= neighbours_data_out_S;
+				if prim_j_S+2/=nrofneighbours_S then
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+				end if;
+				if (nrofneighbours_S>1) and (prim_j_S<nrofneighbours_S-1) then
+					prim_j_S <= prim_j_S+1;
+				else
+					nClusters_S <= nClusters_S+1;
+					prim_k_S <= prim_k_S+1;
+					state_S <= PRIMARY;
+				end if;
+			when PRIMARY2 =>
+				prim_m_S <= conv_integer(unsigned(neighbours_data_out_S));
+				if (nrofneighbours_S>1) then
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+				end if;
+				isAdded_k_S <= isAdded_data_out_S;
+				neighbours_data_prev_S <= neighbours_data_out_S;
+				state_S <= PRIMARY2_0;
+			when PRIMARY2_0 =>
+				if isAdded_data_out_S(CLUSTERBITS)='0' then -- filled bit not set
+					isAdded_data_in_S <= isAdded_k_S;
+					isAdded_write_address_S <= neighbours_data_prev_S; -- conv_std_logic_vector(prim_m_S,CLUSTERBITS);
+					isAdded_write_S <= '1';
+				elsif isAdded_data_out_S/=isAdded_k_S then --hier verder
+					if isAdded_k_S(CLUSTERBITS-1 downto 0)>isAdded_data_out_S(CLUSTERBITS-1 downto 0) then
+						similarities_data_in_S <= isAdded_k_S(CLUSTERBITS-1 downto 0) & isAdded_data_out_S(CLUSTERBITS-1 downto 0);
+					else
+						similarities_data_in_S <= isAdded_data_out_S(CLUSTERBITS-1 downto 0) & isAdded_k_S(CLUSTERBITS-1 downto 0);
+					end if;
+					similarities_write_S <= '1';
+					similarities_write_address_S <= conv_std_logic_vector(simLength_S,CLUSTERBITS);
+					simLength_S <= simLength_S+1;
+				end if;
+				neighbours_data_prev_S <= neighbours_data_out_S;
+				if prim_j_S+2/=nrofneighbours_S then
+					neighbours_read_address_S <= neighbours_read_address_S+1;
+				end if;
+				if (nrofneighbours_S>1) and (prim_j_S<nrofneighbours_S-1) then
+					prim_j_S <= prim_j_S+1;
+				else
+					prim_k_S <= prim_k_S+1;
+					state_S <= PRIMARY;
+				end if;
+			when SECONDAIRY =>
+				data_read_address_S <= (others => '0');
+				sec1_i_S <= 0;
+				sec1_m_S <= 0;
+				if (isAdded_data_out_S(CLUSTERBITS)='0') then
+					isAdded_data_in_S <= '1' & conv_std_logic_vector(nClusters_S,CLUSTERBITS);
+					isAdded_write_address_S <= data_write_address_S-1;
+					isAdded_write_S <= '1';
+					nClusters_S <= nClusters_S+1;
+				end if;
+				state_S <= SECONDAIRY1;
+			when SECONDAIRY1 =>
+				results_filled_S <= '0';
+				data_read_address_S <= (others => '0');
+				results_write_address_S <= (others => '1');
+				hitidx_write_address_S <= (others => '1');
+				hitidx_write_address_V := (others => '1');
+				result_startaddress_V := (others => '0');
+				result_nrofhits_V := (others => '0');
+				result_Xpad_min_V := (others => '1');
+				result_Ypad_min_V := (others => '1');
+				result_Xpad_max_V := (others => '0');
+				result_Ypad_max_V := (others => '0');
+				result_energy_max_V := (others => '0');
+				result_time_max_V := (others => '0');
+				result_onedge_V := '0';
+				minimal_energy_reached_V := '0';
+				sum_energy_V := (others => '0');
+				sec1_j_S <= sec1_i_S+1;
+				sec2_i_S <= 0;
+				sec2_n_S <= '0';
+				nPreclusters_S <= 0;
+				nPreclusters_V := 0;
+				if (isAdded_data_out_S(CLUSTERBITS-1 downto 0)=similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)) and
+					(similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0))
+				then -- filled bit not set
+					isAdded_data_in_S <= '1' & similarities_data_out_S(CLUSTERBITS-1 downto 0);
+					isAdded_write_address_S <= conv_std_logic_vector(sec1_m_S,CLUSTERBITS);
+					isAdded_write_S <= '1';
+				end if;
+				if (sec1_m_S<conv_integer(unsigned(data_write_address_S))-1) and (similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) then
+					sec1_m_S <= sec1_m_S+1;
+				else
+					sec1_i_S <= sec1_i_S+1;
+					sec1_m_S <= 0;
+				end if;
+				
+				if (simLength_S=0) or ((sec1_i_S=simLength_S-1) and ((sec1_m_S=conv_integer(unsigned(data_write_address_S))-1) or 
+						(similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)=similarities_data_out_S(CLUSTERBITS-1 downto 0)))) then
+					data_read_address_S <= data_read_address_S+1;
+					sec1_m_S <= 0;
+					state_S <= SECONDAIRY2;
+				elsif (sec1_m_S=conv_integer(unsigned(data_write_address_S))-1) and 
+					(similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)/=similarities_data_out_S(CLUSTERBITS-1 downto 0)) then
+					similarities_source_S <= similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS);
+					similarities_destination_S <= similarities_data_out_S(CLUSTERBITS-1 downto 0);
+					sec1_m_S <= 0;
+					state_S <= ADJUSTSIMULARITIES;
+				end if;
+			when ADJUSTSIMULARITIES =>
+				similarities_data_in_S <= similarities_data_out_S;
+				similarities_write_address_S <= conv_std_logic_vector(sec1_j_S,CLUSTERBITS);
+				if similarities_data_out_S(CLUSTERBITS*2-1 downto CLUSTERBITS)=similarities_source_S then
+					similarities_data_in_S(CLUSTERBITS*2-1 downto CLUSTERBITS) <= similarities_destination_S;
+					similarities_write_S <= '1';
+				end if;
+				if similarities_data_out_S(CLUSTERBITS-1 downto 0)=similarities_source_S then
+					similarities_data_in_S(CLUSTERBITS-1 downto 0) <= similarities_destination_S;
+					similarities_write_S <= '1';
+				end if;
+				if sec1_j_S<simLength_S-1 then
+					sec1_j_S <= sec1_j_S+1;
+				else
+					sec1_j_S <= sec1_i_S+1;
+					state_S <= SECONDAIRY1;
+				end if;				
+			when SECONDAIRY2 =>
+				results_index_S <= 0;
+				if conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S then 
+					sec2_n_S <= '1';
+					isAdded_data_in_S <= '1' & conv_std_logic_vector(nPreclusters_S,CLUSTERBITS);
+					isAdded_write_address_S <= conv_std_logic_vector(sec1_m_S,CLUSTERBITS);
+					isAdded_write_S <= '1';
+				end if;
+				if (nClusters_S>0) then
+					if sec1_m_S<conv_integer(unsigned(data_write_address_S))-1 then
+						sec1_m_S <= sec1_m_S+1;
+					else
+						sec1_m_S <= 0;
+						sec2_i_S <= sec2_i_S+1;
+						if (sec2_n_S='1') or (conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S) then
+							if nPreclusters_S<2**MAXCLUSTERSBITS-1 then
+								nPreclusters_S <= nPreclusters_S+1;
+--//								nPreclusters_V := nPreclusters_S+1;
+							else
+								error_S <= '1';
+							end if;
+						end if;
+						sec2_n_S <= '0';
+					end if;
+				end if;
+				
+				if conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S then
+					result_nrofhits_V := result_nrofhits_V+1;
+					if data_in_Xpad_S<=result_Xpad_min_V then 
+						result_Xpad_min_V := data_in_Xpad_S;
+					end if;
+					if data_in_Ypad_S<=result_Ypad_min_V then 
+						result_Ypad_min_V := data_in_Ypad_S;
+					end if;
+					if data_in_Xpad_S>=result_Xpad_max_V then 
+						result_Xpad_max_V := data_in_Xpad_S;
+					end if;
+					if data_in_Ypad_S>=result_Ypad_max_V then 
+						result_Ypad_max_V := data_in_Ypad_S;
+					end if;
+					if data_in_energy_S>result_energy_max_V then
+						result_energy_max_V := data_in_energy_S;
+						result_time_max_V := data_in_time_S;
+					end if;
+					if (minimal_energy_reached_V='0') and (conv_integer(unsigned(sum_energy_V))+conv_integer(unsigned(data_in_energy_S))<conv_integer(unsigned(minimal_energy_S))) then
+						sum_energy_V := sum_energy_V+data_in_energy_S(MINIMUMENERGYBITS-1 downto 0);
+					else
+						minimal_energy_reached_V := '1';
+					end if;
+					if data_in_onedge_S='1' then
+						result_onedge_V := '1';
+					end if;
+					hitidx_data_in_S <= isAdded_read_address_aftr1clk_S;
+					hitidx_write_address_V := hitidx_write_address_V+1;
+					hitidx_write_address_S <= hitidx_write_address_V;
+					hitidx_write_S <='1';
+				end if;
+				if (nClusters_S>0) then
+					if sec1_m_S<conv_integer(unsigned(data_write_address_S))-1 then
+						if sec1_m_S+1<conv_integer(unsigned(data_write_address_S))-1 then
+							data_read_address_S <= data_read_address_S+1;
+						else
+							data_read_address_S <= (others => '0');
+						end if;
+					else
+						data_read_address_S <= data_read_address_S+1;
+						if (sec2_n_S='1') or (conv_integer(unsigned(isAdded_data_out_S(CLUSTERBITS-1 downto 0)))=sec2_i_S) 
+--						or
+--							((sec2_i_S=nClusters_S-1) and (sec1_m_S=conv_integer(unsigned(data_write_address_S))-1)) 
+							then
+							if result_Xpad_max_V-result_Xpad_min_V>result_Ypad_max_V-result_Ypad_min_V then
+								result_diameter_V := (1+result_Xpad_max_V)-result_Xpad_min_V;
+							else
+								result_diameter_V := (1+result_Ypad_max_V)-result_Ypad_min_V;
+							end if;
+							result_diameter_S <= result_diameter_V;
+							result_time_S <= result_time_max_V;
+							result_positionX_V := ('0'&result_Xpad_min_V)+('0'&result_Xpad_max_V);
+							result_positionX_S <= result_positionX_V(XYPAD_BITSIZE downto 1);
+							result_positionY_V := ('0'&result_Ypad_min_V)+('0'&result_Ypad_max_V);
+							result_positionY_S <= result_positionY_V(XYPAD_BITSIZE downto 1);
+							results_data_in_S <= result_startaddress_V & result_nrofhits_V & result_time_max_V & result_diameter_V & result_positionX_V & result_positionY_V;
+							result_nrofhits_S <= result_nrofhits_V;
+							result_onedge_S <= result_onedge_V;
+							if (result_onedge_V='1') or (SKIPSINGLEHITCLUSTERS=FALSE) or (minimal_energy_reached_V='1') then -- or (result_nrofhits_V>1) 
+								results_write_S <= '1';
+								results_write_address_S <= results_write_address_S+1;
+								results_filled_S <= '1';
+								result_startaddress_V := hitidx_write_address_V+1;
+								nPreclusters_V := nPreclusters_V+1;
+							else
+								hitidx_write_address_V := hitidx_write_address_V-result_nrofhits_V;
+							end if;
+						end if;
+						result_nrofhits_V := (others => '0');
+						result_Xpad_min_V := (others => '1');
+						result_Ypad_min_V := (others => '1');
+						result_Xpad_max_V := (others => '0');
+						result_Ypad_max_V := (others => '0');
+						result_energy_max_V := (others => '0');
+						result_time_max_V := (others => '0');
+						result_onedge_V := '0';
+						minimal_energy_reached_V := '0';
+						sum_energy_V := (others => '0');
+					end if;
+				end if;
+
+				if ((sec2_i_S=nClusters_S-1) and (sec1_m_S=conv_integer(unsigned(data_write_address_S))-1)) or (nClusters_S=0) then
+					if (nPreclusters_V<=1) then
+						nPreclusters_S <= nPreclusters_V;
+						state_S <= WRITESUPERBURST;
+					else
+						nPreclusters_S <= nPreclusters_V;
+						state_S <= SORTING;
+					end if;
+				end if;
+			when SORTING =>
+				results_index_S <= 0;
+				if (((sort_readkey_S='0') and (sort_i_S>=results_write_address_S-1)) and 
+						((sort_j_neg_S='1') or (results_data_out_S(XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2)<=sort_key_S))) or
+					((sort_readkey_S='1') and (sort_i_S>=results_write_address_S) and (stateprev_S/=SECONDAIRY2)) then
+					state_S <= WRITESUPERBURST;
+				end if;
+			when WRITESUPERBURST => 
+				-- results_read_address_S <= clustersortarray_S(0)
+				-- data_read_address_S <= hitidx_data_out_S;
+				-- hitidx_read_address_S <= results_data_out_S(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto CLUSTERBITS+XYPAD_BITSIZE*3+2+24);
+				if only_one_hit_S='1' then
+					nPreclusters_S <= 1;
+					results_write_address_S <= (others => '0');
+					results_data_in_S <= ZEROS(CLUSTERBITS-1 downto 0) & ZEROS(CLUSTERBITS-1 downto 1)&'1' & 
+							data_in_time_S & conv_std_logic_vector(1,XYPAD_BITSIZE) & data_in_Xpad_S & '0' & data_in_Ypad_S & '0';
+					results_write_S <= '1';
+				end if;
+				sec1_m_S <= 0;
+				results_index_S <= 0;
+				if (data_out_clusterallowed='1') then
+					data_out_first_S <= data_first_S;
+					data_out_write_S <= data_first_S;
+					if (nPreclusters_S=0) and (only_one_hit_S='0') then
+						if data_last_S='1' then
+							data_out_last_S <= '1';
+						end if;
+						data_first_S <= '0';
+						data_last_S <= '0';
+						isAdded_data_in_S <= (others => '0');
+						isAdded_write_S <= '1';
+						isAdded_write_address_S <= (others => '0');
+						nextcluster_S <= '1';
+						data_write_address_S <= (others => '0');
+						state_S <= INITIALIZE;
+					else
+						state_S <= WRITECLUSTER; 
+					end if;
+				end if;
+			when WRITECLUSTER =>
+				-- data_read_address_S <= hitidx_data_out_S;
+				-- results_read_address_S <= clustersortarray_S(results_index_S)
+				results_index_S <= results_index_S+1;
+				data_out_S <= (others => '0');
+				data_out_S(63 downto 40) <= results_data_out_S(XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2); -- time 24 bits
+				data_out_S(XYPAD_BITSIZE+29 downto 30) <= results_data_out_S(XYPAD_BITSIZE*3+2-1 downto XYPAD_BITSIZE*2+2); -- diameter 10bits
+				data_out_S(XYPAD_BITSIZE+20 downto 20) <= results_data_out_S(XYPAD_BITSIZE*2+1 downto XYPAD_BITSIZE+1); -- X *2 10bits
+				data_out_S(XYPAD_BITSIZE+10 downto 10) <= results_data_out_S(XYPAD_BITSIZE downto 0); -- Y *2 10bits
+				data_out_S(CLUSTERBITS-1 downto 0) <= results_data_out_S(CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2+24); -- number of hits 10bits
+				data_out_write_S <= '1';
+				hitidx_index_S <= conv_integer(unsigned(results_data_out_S(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto CLUSTERBITS+XYPAD_BITSIZE*3+2+24)));
+				hitidx_endaddress_S <= conv_integer(unsigned(results_data_out_S(2*CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto CLUSTERBITS+XYPAD_BITSIZE*3+2+24)))+
+							conv_integer(unsigned(results_data_out_S(CLUSTERBITS+XYPAD_BITSIZE*3+2+23 downto XYPAD_BITSIZE*3+2+24)));
+				state_S <= WRITEHITS0;
+			when WRITEHITS0 =>
+				hitidx_index_S <= hitidx_index_S+1;
+				state_S <= WRITEHITS;
+			when WRITEHITS =>
+				-- results_read_address_S <= clustersortarray_S(results_index_S)
+				-- data_read_address_S <= hitidx_data_out_S;
+				data_out_S <= data_in_time_S & data_in_statusbyte_S & data_in_channel_S & data_in_energy_S;
+				data_out_write_S <= '1';
+				if hitidx_index_S<hitidx_endaddress_S then
+					hitidx_index_S <= hitidx_index_S+1;
+					-- hitidx_read_address_S <= hitidx_index_S+1;
+				else
+					if results_index_S<nPreclusters_S then
+						state_S <= WRITECLUSTER;
+					else
+						if data_last_S='1' then
+							data_out_last_S <= '1';
+						end if;
+						data_first_S <= '0';
+						data_last_S <= '0';
+						isAdded_data_in_S <= (others => '0');
+						isAdded_write_S <= '1';
+						isAdded_write_address_S <= (others => '0');
+						nextcluster_S <= '1';
+						data_write_address_S <= (others => '0');
+						state_S <= INITIALIZE;
+					end if;
+				end if;
+			when others =>
+				data_write_address_S <= (others => '0');
+				state_S <= INITIALIZE;
+		end case;
+		data_read_address_prev_S <= data_read_address_S;
+		if reset='1' then 
+			data_first_S <= '0';
+			data_last_S <= '0';
+			isAdded_data_in_S <= (others => '0');
+			isAdded_write_S <= '1';
+			isAdded_write_address_S <= (others => '0');
+			data_write_address_S <= (others => '0');
+			data_out_write_S <= '0';
+			data_out_first_S <= '0';
+			data_out_last_S <= '0';
+			nextcluster_S <= '0';
+			state_S <= INITIALIZE;
+		end if;
+		debug_minimal_energy_reached_S <= minimal_energy_reached_V;
+	end if;
+end process;
+
+data_out_write <= data_out_write_S;
+data_out_last <= '1' when (data_out_last_S='1') and (data_out_write_S='1') else '0';
+data_out_first <= '1' when (data_out_first_S='1') and (data_out_write_S='1') else '0';
+data_out <= data_out_S;
+nextcluster <= nextcluster_S;
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0) := (others => '0');
+variable clusterresult_V : std_logic := '0';
+variable same_superburst_V : std_logic := '0';
+variable nrofhits_V : std_logic_vector(9 downto 0) := (others => '0');
+variable hitscounter_V : std_logic_vector(9 downto 0) := (others => '0');
+variable prev_resulttime_V : std_logic_vector(23 downto 0) := (others => '0');
+variable prev_hittime_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+	if (rising_edge(clock)) then
+		debug_error_S <= '0';
+		if data_out_write_S='1' then
+			if data_out_first_S='1' then
+				if data_out_S(30 downto 0) < prev_superburst_V then
+					debug_error_S <= '1';
+				end if;
+				if data_out_S(30 downto 0)=prev_superburst_V then
+					same_superburst_V := '1';
+				else
+					same_superburst_V := '0';
+				end if;
+				prev_superburst_V := data_out_S(30 downto 0);
+				clusterresult_V := '1';
+			elsif clusterresult_V='1' then
+				if hitscounter_V/=nrofhits_V then
+					debug_error_S <= '1';
+				end if;
+				nrofhits_V := data_out_S(9 downto 0);
+				if (same_superburst_V='1') and (prev_resulttime_V>data_out_S(63 downto 40)) then
+					debug_error_S <= '1';
+				end if;
+				same_superburst_V := '1';
+				prev_resulttime_V := data_out_S(63 downto 40);
+				hitscounter_V := (others => '0');
+				prev_hittime_V := (others => '0');
+				clusterresult_V := '0';
+			else
+				if data_out_last_S='1' then
+					if hitscounter_V/=nrofhits_V-1 then
+						debug_error_S <= '1';
+					end if;
+				end if;
+				if data_out_S(63 downto 40)<prev_hittime_V then
+					debug_error_S <= '1';
+				end if;
+				prev_hittime_V := data_out_S(63 downto 40);
+				if hitscounter_V=nrofhits_V-1 then
+					clusterresult_V := '1';
+				end if;
+				hitscounter_V := hitscounter_V+1;
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if state_S=INITIALIZE then
+			nrofclocks_S <= 0;
+		else
+			nrofclocks_S <= nrofclocks_S+1;
+		end if;
+	end if;
+end process;
+
+--process(clock)
+--begin
+--	if (rising_edge(clock)) then
+--		if isAdded_write_S='1' then
+--			if isAdded_data_in_S(CLUSTERBITS)='0' then
+--				debug_isAdded_S(conv_integer(unsigned(isAdded_write_address_S))) <= -1;
+--			else
+--				debug_isAdded_S(conv_integer(unsigned(isAdded_write_address_S))) <= conv_integer(unsigned(isAdded_data_in_S(CLUSTERBITS-1 downto 0)));
+--			end if;
+--		end if;
+--	end if;
+--end process;
+
+--process(clock)
+--begin
+--	if (rising_edge(clock)) then
+--		if similarities_write_S='1' then
+--			similarities_s(conv_integer(unsigned(similarities_write_address_S))*2) <= similarities_data_in_S(CLUSTERBITS*2-1 downto CLUSTERBITS);
+--			similarities_s(conv_integer(unsigned(similarities_write_address_S))*2+1) <= similarities_data_in_S(CLUSTERBITS-1 downto 0);
+--		end if;
+--	end if;
+--end process;
+
+
+testword0(0) <= data_in_active;
+testword0(1) <= data_in_write;
+testword0(2) <= data_in_first;
+testword0(3) <= data_in_last;
+testword0(7 downto 4) <= 
+	x"0" when state_S=INITIALIZE else
+	x"1" when state_S=COLLECT else
+	x"2" when state_S=PRE_READ0 else
+	x"3" when state_S=PRE_READ1 else
+	x"4" when state_S=PRIMARY else
+	x"5" when state_S=PRIMARY1 or state_S=PRIMARY1_0 else
+	x"6" when state_S=PRIMARY2 or state_S=PRIMARY2_0 else
+	x"7" when state_S=SECONDAIRY or state_S=SECONDAIRY1 else
+	x"8" when state_S=ADJUSTSIMULARITIES else
+	x"9" when state_S=SECONDAIRY2 else
+	x"a" when state_S=SORTING else
+	x"b" when state_S=WRITESUPERBURST else
+	x"c" when state_S=WRITECLUSTER else
+	x"d" when state_S=WRITEHITS0 else
+	x"e" when state_S=WRITEHITS else
+	x"f";
+testword0(8) <= data_first_S;
+testword0(9) <= data_last_S;
+testword0(10) <= data_out_write_S;
+testword0(11) <= data_out_first_S;
+testword0(12) <= data_out_last_S;
+testword0(13) <= data_out_clusterallowed;
+testword0(14) <= overflow_S;
+testword0(15) <= debug_error_S;
+testword0(16) <= error_S;
+testword0(17) <= nextcluster_S;
+
+end behaviour;
+
diff --git a/data_concentrator/sources/cluster/CN_precluster_findgap.vhd b/data_concentrator/sources/cluster/CN_precluster_findgap.vhd
new file mode 100644
index 0000000..837dae0
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_precluster_findgap.vhd
@@ -0,0 +1,395 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   26-06-2016
+-- Module Name:   CN_precluster_findgap
+-- Description:   Breaks stream of hits into timebunches
+-- Modifications:
+--   04-01-2017   HEADERWORD0 added
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_precluster_findgap
+-- Breaks stream of hits into timebunches.
+-- If the time between two hits is larger than the specified gap time, or if a new superburst starts,
+-- then an output signal indicates that the next timebuch is starting.
+-- The following parameters are added to the data : X-position of the crystal, Y-position of the crystal,
+-- on edge signal that indicates if the crystal is on the edge of a Data Concentrator region.
+--
+-- The 64 bits input packets, according to SODAnet specs, (wave data is ignored):
+-- 64bits word1: only if HEADERWORD0=true
+--        bit63      = last-packet flag
+--        bit62..48  = packet number
+--        bit47..32  = data size in bytes
+--        bit31..0   = Not used (same as HADES)
+-- 64bits word2:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+--    for pulse data
+-- 64bits word3 and further, for each pulse:   
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+--    for wave data
+-- 64bits word3:
+--        bit63..56  = status byte
+--        bit55..40  = adc channel
+--        bit39..32  = number of samples in wave
+--        bit15..0  = timestamp in respect to superburst of the first sample in the waveform
+-- 64bits word4 and further : 
+--        bit63..48  = next_adcsample(15:0)
+--        bit47..32  = next_adcsample(15:0)
+--        bit31..16  = next_adcsample(15:0)
+--        bit15..0   = next_adcsample(15:0)
+--
+-- Output data:
+-- 64bits word1, only valid on a new superburst, when the signal data_out_first is active:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+-- 64bits word2 and further, for each pulse:   
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+--
+-- Library
+--
+-- Generics:
+--      XYPAD_BITSIZE : number of bits for the X and Y position
+--      HEADERWORD0 : Panda header word in data
+-- 
+-- Inputs:
+--     clock : clock
+--     reset : reset
+--     gap_time : maximum gap time between hits, resolutie from Constant Fraction (6.1ps)
+--     XYLUT_write : write signal for XY position and on-edge Look Up Table
+--     XYLUT_load : when '1' the LUT can be loaded with values, on '0' the writing address is set back to zero
+--     XYLUT_data : loading data for the LUT: 'on edge', X-value, Y-value
+--     data_in : 64bits data
+--     data_in_first : indicates that 64bits data is first in a packet
+--     data_in_last : indicates that 64bits data is last in packet
+--     data_in_write : write signal for 64bits data
+--     data_out_allowed : allowed to write output data
+--      
+-- 
+-- Outputs:
+--     data_in_allowed : writing of input data allowed
+--     data_out : 64 bits output data
+--     data_out_Xpad : X-position of the hit in the output data
+--     data_out_Ypad : Y-position of the hit in the output data
+--     data_out_onedge : the hit in the output data is positioned on the edge of the Data Concentrator region
+--     data_out_active : timebunch active
+--     data_out_nexttimebunch : actual and further output data belongs to new timebunch
+--     data_out_write : write signal for 64 bits / XY and on-edge output data
+--     data_out_first : 64 bits output data contains new superburst
+--     data_out_last : 64 bits output data is the last data of a superburst
+--     superburst_rewind : new superburstnumber is lower than previous
+--     dataerror : error in data
+-- 
+-- Components:
+--     CN_cluster_XY_LUT :  memory block for X,Y position and on-edge Look Up Table
+--
+----------------------------------------------------------------------------------
+
+entity CN_precluster_findgap is
+	generic(
+		XYPAD_BITSIZE           : natural := 7;
+		HEADERWORD0             : boolean := TRUE   
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		gap_time                : in std_logic_vector(23 downto 0);
+		XYLUT_write             : in std_logic;
+		XYLUT_load              : in std_logic;
+		XYLUT_data              : in std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_Xpad           : out std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+		data_out_Ypad           : out std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+		data_out_onedge         : out std_logic;
+		data_out_active         : out std_logic;
+		data_out_nexttimebunch  : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_allowed        : in std_logic;
+		superburst_rewind       : out std_logic;
+		dataerror               : out std_logic
+	); 
+end CN_precluster_findgap;
+
+
+architecture behaviour of CN_precluster_findgap is
+
+component CN_cluster_XY_LUT is
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(15 downto 0);
+		data_in                 : in std_logic_vector(16 downto 0);
+		read_address            : in std_logic_vector(15 downto 0);
+		data_out                : out std_logic_vector(16 downto 0)
+	);
+end component;
+
+
+signal timeoutcount_S           : std_logic_vector(17 downto 0);
+signal data_in_write_S          : std_logic;
+signal data_in_allowed_S        : std_logic;
+
+signal dataerror1_S             : std_logic := '0';
+signal wave_S                   : std_logic := '0';
+signal new_superburst_S         : std_logic := '0';
+signal time_S                   : std_logic_vector(23 downto 0);
+signal prev_suberburst_S        : std_logic_vector(30 downto 0) := (others => '0');
+signal packetsize_S             : integer range 0 to 65535;
+signal data_in_count_S          : integer range 0 to 65535;
+signal waitforfirst_S           : std_logic := '1';
+
+signal data_out_nextbunch_S     : std_logic;
+signal data_out_nextbunch0_S    : std_logic := '0';
+
+signal XYLUT_loadaddress_S      : std_logic_vector(15 downto 0) := (others => '0');
+signal XYLUT_data_in_S          : std_logic_vector(16 downto 0);
+signal XYlut_data_S             : std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+signal XYlut_data0_S            : std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+signal data_out_allowed_S       : std_logic := '0';
+signal data_out_write0_S        : std_logic := '0';
+signal data_out_active_S        : std_logic := '0';
+signal data_out_write_S         : std_logic := '0';
+signal data_out_last_S          : std_logic := '0';
+signal data_out_first_S         : std_logic := '0';
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of data_in : signal is "true";
+-- attribute mark_debug of data_in_write : signal is "true";
+-- attribute mark_debug of data_in_first : signal is "true";
+-- attribute mark_debug of data_in_last : signal is "true";
+-- attribute mark_debug of data_in_allowed : signal is "true";
+-- attribute mark_debug of data_out : signal is "true";
+-- attribute mark_debug of data_out_write : signal is "true";
+-- attribute mark_debug of data_out_first : signal is "true";
+-- attribute mark_debug of data_out_last : signal is "true";
+-- attribute mark_debug of data_out_allowed : signal is "true";
+-- attribute mark_debug of waitforfirst_S : signal is "true";
+-- attribute mark_debug of data_out_nextbunch_S : signal is "true";
+-- attribute mark_debug of data_out_allowed_S : signal is "true";
+-- attribute mark_debug of data_out_write0_S : signal is "true";
+-- attribute mark_debug of data_out_active_S : signal is "true";
+
+-- attribute mark_debug of timeoutcount_S : signal is "true";
+-- attribute mark_debug of dataerror1_S : signal is "true";
+	
+begin
+
+dataerror <= '1' when (dataerror1_S='1') else '0';
+data_in_allowed_S <= '1' when (data_out_allowed='1') and (XYLUT_load='0') 
+and (data_out_last_S='0') --//
+else '0';
+data_in_allowed <= data_in_allowed_S;
+data_out_write <= '1' when (data_out_write_S='1') and (data_out_allowed='1') else '0';
+data_out_last <= data_out_last_S;
+data_in_write_S <= '1' when (data_in_write='1') and (data_in_allowed_S='1') else '0';
+data_out_first <= data_out_first_S;
+
+data_out_active <= data_out_active_S;
+data_out_nexttimebunch <= data_out_nextbunch_S;
+
+
+-- Look Up Table to translate ADC channel number to XY pad position
+XYLUT_data_in_S(XYPAD_BITSIZE-1 downto 0) <= XYLUT_data(XYPAD_BITSIZE-1 downto 0);
+XYLUT_data_in_S(XYPAD_BITSIZE+7 downto 8) <= XYLUT_data(XYPAD_BITSIZE*2-1 downto XYPAD_BITSIZE);
+XYLUT_data_in_S(16) <= XYLUT_data(2*XYPAD_BITSIZE);
+LUT1: CN_cluster_XY_LUT port map(
+		clock => clock,
+		write_enable => XYLUT_write,
+		write_address => XYLUT_loadaddress_S,
+		data_in => XYLUT_data_in_S,
+		read_address => data_in(31 downto 16),
+		data_out => XYlut_data_S);
+
+data_out_Xpad <= XYlut_data0_S(XYPAD_BITSIZE+7 downto 8) when (data_out_allowed_S='0') else XYlut_data_S(XYPAD_BITSIZE+7 downto 8);
+data_out_Ypad <= XYlut_data0_S(XYPAD_BITSIZE-1 downto 0) when (data_out_allowed_S='0') and (data_out_allowed='1') else XYlut_data_S(XYPAD_BITSIZE-1 downto 0);
+data_out_onedge <= XYlut_data0_S(16) when (data_out_allowed_S='0') and (data_out_allowed='1') else XYlut_data_S(XYPAD_BITSIZE*2);
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if XYLUT_load='1' then
+			if XYLUT_write='1' then 
+				XYLUT_loadaddress_S <= XYLUT_loadaddress_S+1;
+			end if;
+		else
+			XYLUT_loadaddress_S <= (others => '0');
+		end if;
+		if data_out_write0_S='1' then
+			XYlut_data0_S <= XYlut_data_S;
+		end if;
+		data_out_allowed_S <= data_out_allowed;
+	end if;
+end process;
+		
+		
+-- input data handling process
+process(clock)
+variable prev_suberburst_V : std_logic_vector(30 downto 0);
+begin
+	if (rising_edge(clock)) then
+		dataerror1_S <= '0';
+		superburst_rewind <= '0';
+		data_out_nextbunch_S <= '0';
+		data_out_write0_S <= '0';
+		data_out_write_S <= '0';
+		data_out_last_S <= '0';
+		data_out_first_S <= '0';
+		if reset='1' then
+			waitforfirst_S <= '1';
+			data_out_nextbunch0_S <='0';
+			new_superburst_S <= '0';
+			data_out_active_S <= '0';
+			prev_suberburst_S <= (others => '0');
+			data_in_count_S <= 0;
+		else
+			if (data_out_nextbunch_S='1') and (data_out_allowed='0') then
+	--//			data_out_nextbunch_S <= '1'; -- retry
+			end if;		
+			if (data_out_write_S='1') and (data_out_allowed='0') then
+				data_out_write_S <= '1'; -- retry;
+				data_out_last_S <= data_out_last_S;
+				data_out_first_S <= data_out_first_S;
+			else
+				if data_out_last_S='1' then
+					data_out_active_S <= '0';
+				end if;
+				if data_out_nextbunch0_S='1' then
+					data_out_nextbunch_S <= '1';
+					data_out_nextbunch0_S <='0';
+				end if;
+			end if;
+			if (data_in_write_S='1') then
+				timeoutcount_S <= (others => '0');
+				if (data_in_first='1') and (HEADERWORD0=true) then
+					waitforfirst_S <= '0';
+					data_in_count_S <= 1;
+					if data_in(63)='0' then
+						dataerror1_S <= '1';
+					end if;
+					packetsize_S <= conv_integer(unsigned(data_in(47 downto 32)));
+					if data_in(31 downto 0)/=x"00000000" then
+						dataerror1_S <= '1';
+					end if;
+					data_out_active_S <= '0';
+					if new_superburst_S='0' then
+						data_out_nextbunch_S <= '1';
+					end if;
+					new_superburst_S <= '1';
+				elsif (waitforfirst_S='0') or (HEADERWORD0=false) then
+					if (data_in_last='1') and (HEADERWORD0=true) then
+						if packetsize_S/=(data_in_count_S+1)*8 then
+							dataerror1_S <= '1';
+						end if;
+					end if;
+					if (data_in_first='1') and (HEADERWORD0=false) then
+						if new_superburst_S='0' then
+							data_out_nextbunch_S <= '1';
+						end if;
+						new_superburst_S <= '1';
+					end if;
+					if ((data_in_count_S=1) and (HEADERWORD0=true)) or ((data_in_first='1') and (HEADERWORD0=false)) then
+						if data_in(63)='1' then
+							wave_S <= '1';
+						else
+							wave_S <= '0';
+							data_out <= data_in;
+							prev_suberburst_V := prev_suberburst_S+1;
+							if (data_in(30 downto 0)/=prev_suberburst_V) and (conv_integer(unsigned(prev_suberburst_S))/=0) then
+								dataerror1_S <= '1';
+							end if;
+							if prev_suberburst_S>data_in(30 downto 0) then
+								superburst_rewind <= '1';
+							end if;
+							prev_suberburst_S <= data_in(30 downto 0);
+							time_S <= (others => '0');
+							data_out_first_S <= '1';
+							data_out_write_S <= '1';
+							if data_in_last='1' then -- empty superburst
+								data_out_active_S <= '0';
+								data_out_last_S <= '1';
+								data_out_nextbunch0_S <= '1';
+							else
+								data_out_active_S <= '1';
+							end if;
+						end if;
+					elsif (wave_S='0') then
+						if data_in(63 downto 40) < time_S(23 downto 0) then
+							dataerror1_S <= '1';
+						end if;
+						time_S <= data_in(63 downto 40);
+						if (new_superburst_S='1') or ('0' & data_in(63 downto 40))>('0' & time_S) + ('0' & gap_time) then
+							if (new_superburst_S='0') then
+								data_out_nextbunch_S <= '1';
+							end if;
+							new_superburst_S <= '0';
+							data_out_active_S <= '1';
+							data_out <= data_in;
+							data_out_last_S <= data_in_last;
+							data_out_write_S <= '1';
+							data_out_write0_S <= '1';
+						else
+							data_out_active_S <= '1';
+							data_out <= data_in;
+							data_out_last_S <= data_in_last;
+							data_out_write_S <= '1';
+							data_out_write0_S <= '1';
+						end if;
+					end if;
+					data_in_count_S <= data_in_count_S+1;
+				end if;
+			else
+				if (data_out_active_S='1') then
+					if (timeoutcount_S(timeoutcount_S'left)='0')  then
+						if data_out_allowed='1' then
+							timeoutcount_S <= timeoutcount_S+1;
+						end if;
+					else
+						data_out_nextbunch_S <= '1';
+						data_out_active_S <= '0';
+		--					superburst_rewind <= '1';
+						timeoutcount_S <= (others => '0');
+					end if;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+
+end behaviour;
+
diff --git a/data_concentrator/sources/cluster/CN_preclustering.vhd b/data_concentrator/sources/cluster/CN_preclustering.vhd
new file mode 100644
index 0000000..455e644
--- /dev/null
+++ b/data_concentrator/sources/cluster/CN_preclustering.vhd
@@ -0,0 +1,668 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI-cart/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   01-07-2016
+-- Module Name:   CN_preclustering
+-- Description:   Pre-clustering part of the PANDA cluster finding
+-- Modifications:
+--   04-01-2017   HEADERWORD0 added
+----------------------------------------------------------------------------------
+LIBRARY ieee ;
+USE ieee.std_logic_1164.all ;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+----------------------------------------------------------------------------------
+-- CN_preclustering
+-- First stage of the clustering algorithm, developed by Marcel Tiemens (KVI-cart) for the PANDA Detector at GSI.
+-- This stage searches for time-gaps in the measured hits (digis) and calculates which hits are part of the same cluster.
+-- Hits are considered to belong to the same cluster if the time and distance between the hits are small (next to each other, also diagonally).
+-- The timegap searching divides the input hit stream into time-bunches in module CN_precluster_findgap.
+-- The time-bunch is processed by module CN_precluster_build to split the data into preclusters.
+-- To increase the throughput several mudules are put in parallel.
+-- If a cluster contains only one hit and if this hit is not position on the edge of the region then this cluster is skipped.
+--
+-- The input data consist of a data package from the Panda Data concentrator. Waveforms packages are ignored.
+--
+-- The 64 bits packets, according to SODAnet specs:
+-- 64bits word1:   
+--        bit63      = last-packet flag
+--        bit62..48  = packet number
+--        bit47..32  = data size in bytes
+--        bit31..0   = Not used (same as HADES)
+-- 64bits word2:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+--
+--    for pulse data
+-- 64bits word3 and further, for each pulse:   
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+--    for wave data
+-- 64bits word3:
+--        bit63..56  = status byte
+--        bit55..40  = adc channel
+--        bit39..32  = number of samples in wave
+--        bit15..0  = timestamp in respect to superburst of the first sample in the waveform
+-- 64bits word4 and further : 
+--        bit63..48  = next_adcsample(15:0)
+--        bit47..32  = next_adcsample(15:0)
+--        bit31..16  = next_adcsample(15:0)
+--        bit15..0   = next_adcsample(15:0)
+--
+-- The output data contains clusters, with in each cluster the original hit-data. There is no header with the size of the packet.
+-- Only a header for the superburst number.
+--
+-- 64bits word1:   
+--        bi63..48   = Status
+--           bit48=internal data-error
+--           bit49=internal error
+--           bit50=error in pulse-data/superburst number
+--           bit63=0:pulse data packet, 1:waveform packet
+--        bit47..32  = System ID
+--        bit31      = 0
+--        bit30..0   = Super-burst number
+-- 64bits word2, clusterresults
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..30  = diameter
+--        bit29..20  = Y position, multiplied by 2
+--        bit19..10  = X position, multiplied by 2
+--        bit9..0    = number of hits in cluster
+-- 64bits word3..word4+nrofhits : pulse data
+--        bit63..51  = offset in respect to superburst
+--        bit50..40  = Time fraction (11 bits used)
+--        bit39..32  = status byte
+--        bit31..16  = adc channel
+--        bit15..0   = Energy (pulse height)
+--
+--
+-- Library
+--
+-- Generics:
+--      XYPAD_BITSIZE : number of bits for the X and Y position 
+--      CLUSTERBITS : number of bits for the number of hits in one timebunch
+--      MAXCLUSTERSBITS : number of bits for the maximum clusters in one timebunch
+--      PARALLELBUILDS : number of CN_precluster_build modules to work in parallel
+--      MINIMUMENERGYBITS : number of bits for the miminum energy value
+--      SKIPSINGLEHITCLUSTERS : skip precluster if it contains only one hit and is not positioned on the edge
+--      HEADERWORD0 : Panda header word in data
+-- 
+-- Inputs:
+--      clock : clock
+--      reset : reset
+--      gap_time : maximum gap time between hits, resolutie from Constant Fraction (6.1ps)
+--      timedifference : maximum difference in time between hits in a cluster, resolutie from Constant Fraction (6.1ps)
+--      minimal_energy : minimum energy for a cluster; clusters with less are skipped if they are not positioned on the edge of a region
+--      XYLUT_write : write signal for XY position and on-edge Look Up Table
+--      XYLUT_load : when '1' the LUT can be loaded with values, on '0' the writing address is set back to zero
+--      XYLUT_data : loading data for the LUT: 'on edge', X-value, Y-value
+--      data_in : 64bits data
+--      data_in_first : indicates that 64bits data is first in a packet
+--      data_in_last : indicates that 64bits data is last in packet
+--      data_in_write : write signal for 64bits data
+--      data_out_allowed : allowed to write output data
+-- 
+-- Outputs:
+--      data_in_allowed : writing of input data allowed 
+--      data_out : 64 bits output data
+--      data_out_write : write signal for 64 bits output data
+--      data_out_first : 64 bits output data contains the new superburst number
+--      data_out_last : 64 bits output data is the last of a superburst (not necessarily the same as timebunch)
+--      superburst_rewind : new superburstnumber is lower than previous
+--      dataerror : error in data
+-- 
+-- Components:
+--      CN_precluster_findgap : Breaks stream of hits into timebunches
+--      CN_precluster_build : Construct clusters from a bunch of hits
+--      syncfifo_4096x66_almostempty3524 : synchronous fifo to buffer output data
+--      CN_fiforead2write : Converts reading from fifo to write
+--
+----------------------------------------------------------------------------------
+
+entity CN_preclustering is
+	generic(
+		XYPAD_BITSIZE           : natural := 8;
+		CLUSTERBITS             : natural := 8;
+		MAXCLUSTERSBITS         : natural := 5;
+		PARALLELBUILDS          : natural := 4;
+		MINIMUMENERGYBITS       : natural := 8;
+		SKIPSINGLEHITCLUSTERS   : boolean := FALSE;
+		HEADERWORD0             : boolean := TRUE   
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		gap_time                : in std_logic_vector(23 downto 0);
+		timedifference          : in std_logic_vector(23 downto 0);
+		minimal_energy          : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+		XYLUT_write             : in std_logic;
+		XYLUT_load              : in std_logic;
+		XYLUT_data              : in std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_allowed        : in std_logic;
+		superburst_rewind       : out std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(127 downto 0) := (others => '0')
+	); 
+end CN_preclustering;
+
+
+architecture behaviour of CN_preclustering is
+
+component CN_precluster_findgap is
+	generic(
+		XYPAD_BITSIZE           : natural := XYPAD_BITSIZE;
+		HEADERWORD0             : boolean := HEADERWORD0   
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		gap_time                : in std_logic_vector(23 downto 0);
+		XYLUT_write             : in std_logic;
+		XYLUT_load              : in std_logic;
+		XYLUT_data              : in std_logic_vector(XYPAD_BITSIZE*2 downto 0);
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_allowed         : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_Xpad           : out std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+		data_out_Ypad           : out std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+		data_out_onedge         : out std_logic;
+		data_out_active         : out std_logic;
+		data_out_nexttimebunch  : out std_logic;
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_allowed        : in std_logic;
+		superburst_rewind       : out std_logic;
+		dataerror               : out std_logic
+	); 
+end component;
+
+component CN_precluster_build is
+	generic(
+		XYPAD_BITSIZE           : natural := XYPAD_BITSIZE;
+		CLUSTERBITS             : natural := CLUSTERBITS;
+		MAXCLUSTERSBITS         : natural := MAXCLUSTERSBITS;
+		MINIMUMENERGYBITS       : natural := MINIMUMENERGYBITS;
+		SKIPSINGLEHITCLUSTERS   : boolean := SKIPSINGLEHITCLUSTERS
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic;
+		timedifference          : in std_logic_vector(23 downto 0);
+		minimal_energy          : in std_logic_vector(MINIMUMENERGYBITS-1 downto 0);
+		data_in                 : in std_logic_vector(63 downto 0);
+		data_in_Xpad            : in std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+		data_in_Ypad            : in std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+		data_in_onedge          : in std_logic;
+		data_in_active          : in std_logic;
+		data_in_write           : in std_logic;
+		data_in_first           : in std_logic;
+		data_in_last            : in std_logic;
+		data_in_allowed         : out std_logic;
+		busy                    : out std_logic;
+		data_out                : out std_logic_vector(63 downto 0);
+		data_out_write          : out std_logic;
+		data_out_first          : out std_logic;
+		data_out_last           : out std_logic;
+		data_out_clusterallowed : in std_logic;
+		nextcluster             : out std_logic;
+		dataerror               : out std_logic;
+		testword0               : out std_logic_vector(36 downto 0) := (others => '0')
+	); 
+end component;
+
+component syncfifo_1024x66_almostempty256 is
+	port(
+    clk                        : in std_logic;
+    srst                       : in std_logic;
+    din                        : in std_logic_vector(65 DOWNTO 0);
+    wr_en                      : in std_logic;
+    rd_en                      : in std_logic;
+    dout                       : out std_logic_vector(65 DOWNTO 0);
+    full                       : out std_logic;
+    empty                      : out std_logic;
+    prog_empty                 : out std_logic
+	); 
+end component;
+
+component syncfifo_4096x66_almostempty3524 is
+	port(
+    clk                        : in std_logic;
+    srst                       : in std_logic;
+    din                        : in std_logic_vector(65 DOWNTO 0);
+    wr_en                      : in std_logic;
+    rd_en                      : in std_logic;
+    dout                       : out std_logic_vector(65 DOWNTO 0);
+    full                       : out std_logic;
+    empty                      : out std_logic;
+    prog_empty                 : out std_logic
+	); 
+end component;
+
+component CN_fiforead2write is
+	generic(
+		BITS                    : integer := 66
+	);
+	port(
+		clock                   : in std_logic; 
+		reset                   : in std_logic; 
+		data_in                 : in std_logic_vector(BITS-1 downto 0);
+		data_in_empty           : in std_logic;
+		data_in_read            : out std_logic;
+		data_out                : out std_logic_vector(BITS-1 downto 0);
+		data_out_write          : out std_logic;
+		data_out_allowed        : in std_logic
+	); 
+end component;
+
+signal data_S                  : std_logic_vector(63 downto 0);
+signal data_Xpad_S             : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data_Ypad_S             : std_logic_vector(XYPAD_BITSIZE-1 downto 0);
+signal data_onedge_S           : std_logic;
+signal data_active_S           : std_logic;
+signal data_write_S            : std_logic;
+signal data_last_S             : std_logic;
+signal data_first_S            : std_logic;
+signal data_allowed_S          : std_logic;
+signal data_out_nexttimebunch_S: std_logic;
+signal superburst_rewind_S     : std_logic;
+
+signal build_reset_S           : std_logic;
+signal build_actual0_S         : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_next_S            : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_actual_S          : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_read_S            : integer range 0 to PARALLELBUILDS-1 := 0;
+signal build_active_S          : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_allowed_S         : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_write_S           : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_write_S        : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_firsts_S       : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_last_S         : std_logic_vector(0 to PARALLELBUILDS-1);
+signal data_out_allowed_S      : std_logic_vector(0 to PARALLELBUILDS-1);
+signal busy_S                  : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_nextcluster_S     : std_logic_vector(0 to PARALLELBUILDS-1);
+signal build_error_S           : std_logic_vector(0 to PARALLELBUILDS-1);
+
+signal fifoout0_datain_S       : std_logic_vector(65 downto 0);
+signal fifoout_datain_S        : std_logic_vector(65 downto 0);
+signal fifoout_dataout_S       : std_logic_vector(65 downto 0);
+signal fifoout_reset_S         : std_logic;
+signal fifoout_write_S         : std_logic;
+signal fifoout_read_S          : std_logic;
+signal fifoout_full_S          : std_logic;
+signal fifoout_empty_S         : std_logic;
+signal fifoout_prog_empty_S    : std_logic;
+
+
+	
+signal dataerror0_S            : std_logic;
+
+type data_out_type is array(0 to PARALLELBUILDS-1) of std_logic_vector(63 downto 0);
+signal data_out_S              : data_out_type;
+
+signal debug_data_in_error_S   : std_logic;
+signal debug_error_S           : std_logic;
+type testwords36_type is array(0 to PARALLELBUILDS-1) of std_logic_vector(36 downto 0);
+signal testwords36_S           : testwords36_type;
+
+-- attribute mark_debug : string;
+-- attribute mark_debug of debug_data_in_error_S : signal is "true";
+-- attribute mark_debug of debug_error_S : signal is "true";
+-- attribute mark_debug of dataerror0_S : signal is "true";
+-- attribute mark_debug of build_error_S : signal is "true";
+
+-- attribute mark_debug of fifoout_datain_S : signal is "true";
+-- attribute mark_debug of fifoout_write_S : signal is "true";
+-- attribute mark_debug of fifoout_full_S : signal is "true";
+-- attribute mark_debug of fifoout_empty_S : signal is "true";
+
+
+begin
+
+dataerror <= '1' when (dataerror0_S='1') or (conv_integer(unsigned(build_error_S))/=0) or (fifoout_full_S='1') else '0';
+superburst_rewind <= superburst_rewind_S;
+
+CN_precluster_findgap1: CN_precluster_findgap port map(
+		clock => clock,
+		reset => reset,
+		gap_time => gap_time,
+		XYLUT_write => XYLUT_write,
+		XYLUT_load => XYLUT_load,
+		XYLUT_data => XYLUT_data,
+		data_in => data_in,
+		data_in_first => data_in_first,
+		data_in_last => data_in_last,
+		data_in_write => data_in_write,
+		data_in_allowed => data_in_allowed,
+		data_out => data_S,
+		data_out_Xpad => data_Xpad_S,
+		data_out_Ypad => data_Ypad_S,
+		data_out_onedge => data_onedge_S,
+		data_out_active => data_active_S,
+		data_out_nexttimebunch => data_out_nexttimebunch_S,
+		data_out_write => data_write_S,
+		data_out_last => data_last_S,
+		data_out_first => data_first_S,
+		data_out_allowed => data_allowed_S,
+		superburst_rewind => superburst_rewind_S,
+		dataerror => dataerror0_S);
+
+data_allowed_S <= build_allowed_S(build_actual_S);
+
+build_actual_S <= build_next_S when (data_out_nexttimebunch_S='1') else build_actual0_S;
+build_next_S <= 0 when build_actual0_S>=PARALLELBUILDS-1 else build_actual0_S+1;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if reset='1' then
+			build_actual0_S <= 0;
+		else
+			if (data_out_nexttimebunch_S='1') then
+				if build_actual0_S<PARALLELBUILDS-1 then
+					build_actual0_S <= build_actual0_S+1;
+				else
+					build_actual0_S <= 0;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+----------
+-- data_allowed_S <= '1' when 
+	-- ((build_allowed_S(build_actual0_S)='1') and (data_out_nexttimebunch_S='0')) or 
+	-- ((build_allowed_S(build_next_S)='1') and (data_out_nexttimebunch_S='1'))
+	-- else '0';
+
+-- build_actual_S <= build_next_S when (data_out_nexttimebunch_S='1') and (build_allowed_S(build_next_S)='1') else build_actual0_S;
+-- build_next_S <= 0 when build_actual0_S>=PARALLELBUILDS-1 else build_actual0_S+1;
+
+-- process(clock)
+-- begin
+	-- if (rising_edge(clock)) then
+		-- if (data_out_nexttimebunch_S='1') and (data_allowed_S='1') then
+			-- if build_actual0_S<PARALLELBUILDS-1 then
+				-- build_actual0_S <= build_actual0_S+1;
+			-- else
+				-- build_actual0_S <= 0;
+			-- end if;
+		-- end if;
+	-- end if;
+-- end process;
+
+CN_cluster_builds: for idx in 0 to PARALLELBUILDS-1 generate
+	
+	build_write_S(idx) <= data_write_S when idx=build_actual_S else '0';
+	build_active_S(idx) <= data_active_S when idx=build_actual_S else '0';
+	build_reset_S <= '1' when (superburst_rewind_S='1') or (reset='1') else '0';
+	
+	CN_precluster_build0: CN_precluster_build port map(
+			clock => clock,
+			reset => build_reset_S,
+			timedifference => timedifference,
+			minimal_energy => minimal_energy,
+			data_in => data_S,
+			data_in_Xpad => data_Xpad_S,
+			data_in_Ypad => data_Ypad_S,
+			data_in_onedge => data_onedge_S,
+			data_in_active => build_active_S(idx),
+			data_in_write => build_write_S(idx),
+			data_in_first => data_first_S,
+			data_in_last => data_last_S,
+			data_in_allowed => build_allowed_S(idx),
+			busy => busy_S(idx),
+			data_out => data_out_S(idx),
+			data_out_write => data_out_write_S(idx),
+			data_out_first => data_out_firsts_S(idx),
+			data_out_last => data_out_last_S(idx),
+			data_out_clusterallowed => data_out_allowed_S(idx),
+			nextcluster => build_nextcluster_S(idx),
+			dataerror => build_error_S(idx),
+			testword0 => testwords36_S(idx));
+data_out_allowed_S(idx) <= fifoout_prog_empty_S when build_read_S=idx else '0';
+
+end generate;
+
+-- fifoout_datain_S(63 downto 0) <= data_out_S(build_read_S);
+-- fifoout_write_S <= data_out_write_S(build_read_S);
+-- fifoout_datain_S(65) <= data_out_firsts_S(build_read_S);
+-- fifoout_datain_S(64) <= data_out_last_S(build_read_S);
+process(clock)
+variable regfilled_V : std_logic := '0';
+begin
+	if (rising_edge(clock)) then
+		fifoout_write_S <= '0';
+		if reset='1' then
+			regfilled_V := '0';
+		else
+			if data_out_write_S(build_read_S)='1' then
+				fifoout0_datain_S(63 downto 0) <= data_out_S(build_read_S);
+				fifoout0_datain_S(65) <= data_out_firsts_S(build_read_S);
+				fifoout0_datain_S(64) <= data_out_last_S(build_read_S);
+				if regfilled_V='1' then
+					fifoout_datain_S <= fifoout0_datain_S;
+					if data_out_firsts_S(build_read_S)='1' then
+						fifoout_datain_S(64) <= '1'; -- force last
+					end if;
+					fifoout_write_S <= '1';
+					regfilled_V := '1';
+				else
+					if data_out_last_S(build_read_S)='1' then
+						fifoout_datain_S(63 downto 0) <= data_out_S(build_read_S);
+						fifoout_datain_S(65) <= data_out_firsts_S(build_read_S);
+						fifoout_datain_S(64) <= '1';
+						fifoout_write_S <= '1';
+						regfilled_V := '0';
+					else
+						regfilled_V := '1';
+					end if;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		if reset='1' then
+			build_read_S <= 0;
+		else
+			if build_actual_S/=build_read_S then
+				if busy_S(build_read_S)='0' then
+					if build_read_S<PARALLELBUILDS-1 then
+						build_read_S <= build_read_S+1;
+					else
+						build_read_S <= 0;
+					end if;
+				end if;
+			else
+				if (build_nextcluster_S(build_read_S)='1') then
+					if build_read_S<PARALLELBUILDS-1 then
+						build_read_S <= build_read_S+1;
+					else
+						build_read_S <= 0;
+					end if;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+fifoout_reset_S <= '1' when (superburst_rewind_S='1') or (reset='1') else '0';
+outfifo: syncfifo_1024x66_almostempty256 port map(
+--outfifo: syncfifo_4096x66_almostempty3524 port map(
+    clk => clock,
+    srst => fifoout_reset_S,
+    din => fifoout_datain_S,
+    wr_en => fifoout_write_S,
+    rd_en => fifoout_read_S,
+    dout => fifoout_dataout_S,
+    full => fifoout_full_S,
+    empty => fifoout_empty_S,
+    prog_empty => fifoout_prog_empty_S); 
+
+
+read2write: CN_fiforead2write port map(
+	clock => clock,
+	reset => fifoout_reset_S,
+	data_in => fifoout_dataout_S,
+	data_in_empty => fifoout_empty_S,
+	data_in_read => fifoout_read_S,
+	data_out(65) => data_out_first,
+	data_out(64) => data_out_last,
+	data_out(63 downto 0) => data_out,
+	data_out_write => data_out_write,
+	data_out_allowed => data_out_allowed);
+
+process(clock)
+variable prev_superburst_V : std_logic_vector(30 downto 0) := (others => '0');
+variable clusterresult_V : std_logic := '0';
+variable same_superburst_V : std_logic := '0';
+variable nextissuperburst_V : std_logic := '1';
+variable nrofhits_V : std_logic_vector(9 downto 0) := (others => '0');
+variable hitscounter_V : std_logic_vector(9 downto 0) := (others => '0');
+variable prev_resulttime_V : std_logic_vector(23 downto 0) := (others => '0');
+variable prev_hittime_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+	if (rising_edge(clock)) then
+		debug_error_S <= '0';
+		if reset='1' then
+			prev_superburst_V := (others => '0');
+			clusterresult_V := '0';
+			same_superburst_V := '0';
+			nextissuperburst_V := '1';
+			nrofhits_V := (others => '0');
+			hitscounter_V := (others => '0');
+			prev_resulttime_V := (others => '0');
+			prev_hittime_V := (others => '0');
+		else
+			if fifoout_write_S='1' then
+				if fifoout_datain_S(65)='1' then -- first
+					if nextissuperburst_V='0' then
+					end if;
+					if (fifoout_datain_S(30 downto 0)/=prev_superburst_V+1) and (conv_integer(unsigned(prev_superburst_V))/=0) then
+						debug_error_S <= '1';
+					end if;
+					same_superburst_V := '0';
+					prev_superburst_V := fifoout_datain_S(30 downto 0);
+					clusterresult_V := '1';
+					if fifoout_datain_S(64)='1' then -- last
+						nextissuperburst_V := '1';
+					else
+						nextissuperburst_V := '0';
+					end if;
+				elsif clusterresult_V='1' then
+					if fifoout_datain_S(64)='1' then -- last
+						nextissuperburst_V := '1';
+						debug_error_S <= '1';
+					else
+						nextissuperburst_V := '0';
+					end if;
+					if hitscounter_V/=nrofhits_V then
+						debug_error_S <= '1';
+					end if;
+					nrofhits_V := fifoout_datain_S(9 downto 0);
+					if (same_superburst_V='1') and (prev_resulttime_V>fifoout_datain_S(63 downto 40)) then
+						debug_error_S <= '1';
+					end if;
+					same_superburst_V := '1';
+					prev_resulttime_V := fifoout_datain_S(63 downto 40);
+					hitscounter_V := (others => '0');
+					prev_hittime_V := (others => '0');
+					clusterresult_V := '0';
+				else
+					if fifoout_datain_S(64)='1' then -- last
+						if hitscounter_V/=nrofhits_V-1 then
+							debug_error_S <= '1';
+						end if;
+						nextissuperburst_V := '1';
+					else
+						nextissuperburst_V := '0';
+					end if;
+					if fifoout_datain_S(63 downto 40)<prev_hittime_V then
+						debug_error_S <= '1';
+					end if;
+					prev_hittime_V := fifoout_datain_S(63 downto 40);
+					if hitscounter_V=nrofhits_V-1 then
+						clusterresult_V := '1';
+					end if;
+					hitscounter_V := hitscounter_V+1;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+
+process(clock)
+variable SB_V : std_logic_vector(30 downto 0);
+begin
+	if (rising_edge(clock)) then
+		debug_data_in_error_S <= '0';
+		if data_in_write='1' then
+			if data_in_first='1' then
+				if SB_V /= data_in(30 downto 0) then
+					debug_data_in_error_S <= '1';
+				end if;
+				SB_V := data_in(30 downto 0)+1;
+			end if;
+		end if;
+	end if;
+end process;	
+		
+		
+testword0(63 downto 0) <= fifoout_datain_S(63 downto 0);
+testword0(64) <= fifoout_datain_S(64);
+testword0(65) <= fifoout_datain_S(65);
+testword0(66) <= fifoout_write_S;
+testword0(67) <= fifoout_full_S;
+testword0(68) <= fifoout_prog_empty_S;
+testword0(70 downto 69) <= conv_std_logic_vector(build_read_S,2);
+testword0(71) <= superburst_rewind_S;
+testword0(72) <= dataerror0_S;
+testword0(73) <= debug_error_S;
+
+
+testword0(74) <= data_write_S;
+testword0(75) <= data_in_write;
+testword0(76) <= data_in_first;
+testword0(77) <= data_in_last;
+testword0(78) <= data_active_S;
+testword0(79) <= data_first_S;
+testword0(80) <= data_last_S;
+testword0(81) <= data_allowed_S;
+testword0(82) <= data_out_nexttimebunch_S;
+testword0(83) <= superburst_rewind_S;
+testword0(84) <= build_reset_S;
+testword0(85) <= build_allowed_S(0);
+testword0(86) <= build_allowed_S(1);
+
+testword0(105 downto 88) <= testwords36_S(0)(17 downto 0);
+testword0(123 downto 106) <= testwords36_S(1)(17 downto 0);
+
+
+end behaviour;
diff --git a/data_concentrator/sources/cluster/blockmemdirectread.vhd b/data_concentrator/sources/cluster/blockmemdirectread.vhd
new file mode 100644
index 0000000..025199e
--- /dev/null
+++ b/data_concentrator/sources/cluster/blockmemdirectread.vhd
@@ -0,0 +1,95 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   18-07-2016
+-- Module Name:   blockmemdirectread
+-- Description:   Generic memory block
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+------------------------------------------------------------------------------------------------------
+-- blockmemdirectread
+--		Generic memory block with separated addresses for reading and writing
+--      Data is immidiately available on output when read from written address
+--
+--
+-- generics
+--    ADDRESS_BITS : Number of bits for the address
+--    DATA_BITS : number of bits for data
+--		
+-- inputs
+--		clock : clock 
+--		write_enable : write to memory
+--		write_address : address to write to
+--		data_in : data to write into memory
+--		read_address : address to read from
+--			  
+-- outputs
+--		data_out : data from memory
+--
+-- components
+--
+------------------------------------------------------------------------------------------------------
+
+entity blockmemdirectread is
+	generic (
+		ADDRESS_BITS : natural := 8;
+		DATA_BITS  : natural := 18
+		);
+	port (
+		clock                   : in  std_logic; 
+		write_enable            : in std_logic;
+		write_address           : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_in                 : in std_logic_vector(DATA_BITS-1 downto 0);
+		read_address            : in std_logic_vector(ADDRESS_BITS-1 downto 0);
+		data_out                : out std_logic_vector(DATA_BITS-1 downto 0)
+	);
+end blockmemdirectread;
+
+architecture behavioral of blockmemdirectread is
+type mem_type is array (2**ADDRESS_BITS-1 downto 0) of std_logic_vector (DATA_BITS-1 downto 0);
+signal mem_S                : mem_type := (others => (others => '0'));
+attribute RAM_STYLE : string;
+attribute RAM_STYLE of mem_S: signal is "BLOCK";
+		
+signal data_out_S           : std_logic_vector(DATA_BITS-1 downto 0);
+signal data_in_prev_S       : std_logic_vector(DATA_BITS-1 downto 0);
+signal read_address_prev_S  : std_logic_vector(ADDRESS_BITS-1 downto 0);
+signal correction0_S        : std_logic;
+signal correction1_S        : std_logic;
+signal correctionp_S        : std_logic;
+
+begin
+
+	process (clock)
+	begin
+		if (clock'event and clock = '1') then
+			if (write_enable = '1') then
+				mem_S(conv_integer(write_address)) <= data_in;
+			end if;
+			data_out_S <= mem_S(conv_integer(read_address));			
+		end if;
+	end process;
+
+data_out <= 
+	data_in when correctionp_S='1' else
+	data_in_prev_S when correction1_S='1' else 
+	data_out_S;
+
+correctionp_S <= '1' when (write_address=read_address_prev_S) and (write_enable='1') else '0';
+correction0_S <= '1' when (write_address=read_address) and (write_enable='1') else '0';
+process(clock)
+begin
+	if (rising_edge(clock)) then
+		correction1_S <= correction0_S;
+		data_in_prev_S <= data_in;
+		read_address_prev_S <= read_address;
+	end if;
+end process;
+	
+
+end architecture behavioral;
\ No newline at end of file
diff --git a/data_concentrator/sources/div_pipe_r4_arch2/cond_add.vhd b/data_concentrator/sources/div_pipe_r4_arch2/cond_add.vhd
new file mode 100644
index 0000000..9b33ef6
--- /dev/null
+++ b/data_concentrator/sources/div_pipe_r4_arch2/cond_add.vhd
@@ -0,0 +1,37 @@
+----------------------------------------
+--  Conditional adder
+--  op_a + op_b or only op_a depending on sel
+--  
+----------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity cond_adder is
+	generic (
+		XBITS : natural := 32;
+		YBITS : natural := 32
+	);
+    port (
+        op_a: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+        op_b: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+        sel: in STD_LOGIC;
+        outp: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+     );
+end cond_adder;
+
+architecture simple_arch of cond_adder is
+
+begin
+  anAdder: process (sel,op_a,op_b)
+  begin
+     if sel = '1' then
+        outp <= op_a + op_b;
+     else
+        outp <= op_a;
+     end if; 
+  end process;
+end simple_arch;
+
diff --git a/data_concentrator/sources/div_pipe_r4_arch2/div_r4_pipe.vhd b/data_concentrator/sources/div_pipe_r4_arch2/div_r4_pipe.vhd
new file mode 100644
index 0000000..34eb546
--- /dev/null
+++ b/data_concentrator/sources/div_pipe_r4_arch2/div_r4_pipe.vhd
@@ -0,0 +1,149 @@
+-----------------------------------------------------------------------
+---- Pipelined radix 4 Divisor based on Arch2 (half arch)
+---- A, and B naturals (non negative integers) with XBITS and YBITS width
+---- there is no restriction XBITS >= YBITS. 
+---- Return quotient Q of XBITS and remainder R of NBITS
+---- GRAIN defines the amount of bits computed at each cycle. 
+----
+---- The circuit captures operands at each cycle 
+---- The algorithm needs XBITS/GRAIN/DEPTH + 1 cylcles to calculate the quotient 
+---- and remainder (Latency). Its posible to obtain the result one cycle before.
+---- GRAIN = 2 for that radix 4 divider
+---- DEPTH (logic depth) every how many basic cell we register.
+---- DEPTH = 1 maximun pipeline
+----------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+entity div_r4_pipe is
+	generic (
+		XBITS : natural := 32;
+		YBITS : natural := 32;
+		GRAIN : natural := 2;
+		DEPTH : natural := 8
+	);
+	port (
+		A: in STD_LOGIC_VECTOR (XBITS-1 downto 0);
+		B: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+		clk: in STD_LOGIC;
+		Q: out STD_LOGIC_VECTOR (XBITS-1 downto 0);
+		R: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+	);
+end div_r4_pipe;
+
+architecture simple_arch of div_r4_pipe is
+
+  component cond_adder is
+	generic (
+		XBITS : natural := XBITS;
+		YBITS : natural := YBITS
+	);
+      port (
+        op_a: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+        op_b: in STD_LOGIC_VECTOR (YBITS-1 downto 0);
+        sel: in STD_LOGIC;
+        outp: out STD_LOGIC_VECTOR (YBITS-1 downto 0)
+       );
+  end component;
+
+  component nr_r4_half_cell is
+	generic (
+		XBITS : natural := XBITS;
+		YBITS : natural := YBITS
+	);
+    port (
+        op_r: in STD_LOGIC_VECTOR (YBITS downto 0);
+        op_y: in STD_LOGIC_VECTOR (YBITS downto 0);
+        op_3y: in STD_LOGIC_VECTOR (YBITS+1 downto 0);
+        x_1: in STD_LOGIC;
+        x_0: in STD_LOGIC;
+        n_qneg: out STD_LOGIC_VECTOR (1 downto 0);
+        new_r: out STD_LOGIC_VECTOR (YBITS downto 0)
+        );
+  end component;
+
+
+ type connectionmatrix is array (0 to GRAIN) of STD_LOGIC_VECTOR (YBITS downto 0);
+  Signal  iR, reg_Y_rem: STD_LOGIC_VECTOR (YBITS-1 downto 0);
+  Signal  iQ: STD_LOGIC_VECTOR (XBITS-1 downto 0);
+
+  type matrix_rem is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS downto 0);
+  signal rem_in, rem_out: matrix_rem := (others => (others => '0'));
+  type matrix_Y is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS downto 0);
+  signal reg_Y: matrix_Y := (others => (others => '0'));
+  type matrix_3Y is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (YBITS+1 downto 0);
+  signal reg_3Y: matrix_3Y := (others => (others => '0'));
+  type matrix_X is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (XBITS-1 downto 0);
+  signal reg_X: matrix_X := (others => (others => '0'));
+  type matrix_Q is array (0 to XBITS/GRAIN-1) of STD_LOGIC_VECTOR (XBITS-1 downto 0);
+  signal reg_Q: matrix_Q := (others => (others => '0'));
+
+signal rem_no_adj: STD_LOGIC_VECTOR (YBITS downto 0);
+
+--attribute keep_hierarchy: string;
+--attribute keep_hierarchy of low_level_arch: architecture is "yes";
+--attribute IOB: string;
+--attribute IOB of low_level_arch: architecture is "FALSE";
+
+begin
+
+  FF_0: process (clk)
+  begin
+  if CLK'event and CLK='1' then  --CLK rising edge 
+    reg_Y(0) <= ('0' & B);
+    reg_3Y(0) <= ('0' & B) + ('0' & B & '0');
+    reg_X(0) <= A; 
+    --Q <= not reg_Q(XBITS/GRAIN-1); --ito obtain the result a cycle before
+    Q <= iQ; iQ <= not reg_Q(XBITS/GRAIN-1);
+    rem_no_adj <= rem_out(XBITS/GRAIN-1);
+    reg_Y_rem <= reg_Y(XBITS/GRAIN-1)(YBITS-1 downto 0);
+    R <= iR;
+  end if;
+  end process;
+
+
+  rem_in(0) <= (others => '0');
+  
+  g1: for i in 0 to XBITS/GRAIN -1 generate
+  cell: nr_r4_half_cell port map( op_r => rem_in(i),
+        op_y => reg_Y(i), op_3y => reg_3Y(i),
+        x_1 => reg_X(i)(XBITS-1-i*2), x_0 => reg_X(i)(XBITS-2-i*2),
+        n_qneg => reg_Q(i)(XBITS-1-i*2 downto XBITS-2-i*2),  new_r => rem_out(i) );
+  end generate;
+ 
+  g2: for i in 0 to XBITS/GRAIN-2 generate
+    g2c: if (i+1) mod DEPTH /= 0 generate
+      rem_in(i+1) <= rem_out(i);
+      reg_Y(i+1) <= reg_Y(i); reg_3Y(i+1) <= reg_3Y(i);
+      reg_X(i+1) <= reg_X(i); 
+      reg_Q(i+1)(XBITS-1 downto XBITS-2-i*2) <= reg_Q(i)(XBITS-1 downto XBITS-2-i*2); 
+    end generate;
+    g2FF: if (i+1) mod DEPTH = 0 generate
+      FFs: process(clk)
+      begin
+        if CLK'event and CLK='1' then  --CLK rising edge 
+          rem_in(i+1) <= rem_out(i);
+          reg_Y(i+1) <= reg_Y(i); reg_3Y(i+1) <= reg_3Y(i);
+          reg_X(i+1) <= reg_X(i); 
+          reg_Q(i+1)(XBITS-1 downto XBITS-2-i*2) <= reg_Q(i)(XBITS-1 downto XBITS-2-i*2); 
+        end if;
+      end process;
+    end generate;
+  end generate;
+
+ 
+-- use this code to obtain the remainder a cycle before
+-- final_rem_Adjust: cond_adder port map (op_a => rem_out(XBITS/GRAIN-1)(YBITS-1 downto 0),
+--          op_b => reg_Y(XBITS/GRAIN-1)(YBITS-1 downto 0),
+--          sel => rem_out(XBITS/GRAIN-1)(YBITS), outp => iR);
+
+  
+ final_rem_Adjust: cond_adder port map (op_a => rem_no_adj(YBITS-1 downto 0),
+          op_b => reg_Y_rem(YBITS-1 downto 0),
+          sel => rem_no_adj(YBITS), outp => iR);
+
+
+end simple_arch;
diff --git a/data_concentrator/sources/div_pipe_r4_arch2/implement_32by32.pdf b/data_concentrator/sources/div_pipe_r4_arch2/implement_32by32.pdf
new file mode 100644
index 0000000..9c418f2
Binary files /dev/null and b/data_concentrator/sources/div_pipe_r4_arch2/implement_32by32.pdf differ
diff --git a/data_concentrator/sources/div_pipe_r4_arch2/mypack.vhd b/data_concentrator/sources/div_pipe_r4_arch2/mypack.vhd
new file mode 100644
index 0000000..8d69abd
--- /dev/null
+++ b/data_concentrator/sources/div_pipe_r4_arch2/mypack.vhd
@@ -0,0 +1,10 @@
+-------------------------------------
+-- Defines the dataPath width
+--
+-------------------------------------
+package mypackage is
+   constant XBITS :INTEGER := 32; 
+   constant YBITS :INTEGER := 32;
+   constant GRAIN :INTEGER := 2; --Allways in 2!!!!
+   constant DEPTH :INTEGER := 1; --Every how much steps register
+end mypackage;
diff --git a/data_concentrator/sources/div_pipe_r4_arch2/nr_r4_cel.vhd b/data_concentrator/sources/div_pipe_r4_arch2/nr_r4_cel.vhd
new file mode 100644
index 0000000..f2fdf98
--- /dev/null
+++ b/data_concentrator/sources/div_pipe_r4_arch2/nr_r4_cel.vhd
@@ -0,0 +1,61 @@
+--------------------------------------------------------
+-- 
+-- Basic cell radix 4 arch 2. divider
+--------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+use work.mypackage.all;
+
+entity nr_r4_half_cell is
+	generic (
+		XBITS : natural := 32;
+		YBITS : natural := 32
+	);
+    --generic(pos_x: integer:= 0; pos_y: integer := 0; agroup: string:= "cell_r4"); 
+    port (
+        op_r: in STD_LOGIC_VECTOR (YBITS downto 0);
+        op_y: in STD_LOGIC_VECTOR (YBITS downto 0);
+        op_3y: in STD_LOGIC_VECTOR (YBITS+1 downto 0);
+        x_1: in STD_LOGIC;
+        x_0: in STD_LOGIC;
+        n_qneg: out STD_LOGIC_VECTOR (1 downto 0);
+        new_r: out STD_LOGIC_VECTOR (YBITS downto 0)
+        );
+end nr_r4_half_cell;
+
+architecture half of nr_r4_half_cell is
+  signal op_4r: STD_LOGIC_VECTOR (YBITS+1 downto 0);
+  signal a2_pm_b, a4_pm_b, a4_pm_3b: STD_LOGIC_VECTOR (YBITS+1 downto 0);
+  signal sr: STD_LOGIC;
+begin
+  sr <= op_r(YBITS);
+  op_4r <= op_r(YBITS-1 downto 0) & x_1 & x_0; 
+  
+  a2_pm_b  <= (op_r & x_1) + (op_y) when sr = '1' else (sr & op_y) + not (op_r & x_1);
+  a4_pm_3b <= (op_4r + op_3y) when sr = '1' else (op_4r) - (op_3y);
+  a4_pm_b  <= (op_4r + op_y) when sr = '1' else (op_4r) - (sr & op_y);
+
+  mux_outps: process (a2_pm_b, a4_pm_b, a4_pm_3b)
+  begin
+  if a2_pm_b(YBITS)= '1' then 
+    new_r <= a4_pm_3b(YBITS downto 0);
+    n_qneg(0) <= a4_pm_3b(YBITS);
+  else 
+    new_r <= a4_pm_b(YBITS downto 0);
+    n_qneg(0) <= a4_pm_b(YBITS);
+  end if;    
+  end process;
+
+  mux_nqb: process (sr,a2_pm_b, a4_pm_b, a4_pm_3b)
+  begin
+    if sr = '1' then --11      
+       n_qneg(1) <= a2_pm_b(YBITS);
+    else
+       n_qneg(1) <= not a2_pm_b(YBITS);
+    end if; 
+
+  end process;
+  
+end half;
diff --git a/data_concentrator/sources/div_pipe_r4_arch2/test_tb.vhd b/data_concentrator/sources/div_pipe_r4_arch2/test_tb.vhd
new file mode 100644
index 0000000..1e5d7c1
--- /dev/null
+++ b/data_concentrator/sources/div_pipe_r4_arch2/test_tb.vhd
@@ -0,0 +1,165 @@
+--------------------------------------------------------------------
+-- VHDL Test Bench for sequential divider
+--
+-- Notes: 
+-- Exhaustive testbench. 
+-- Only for small values of XBITS and YBITS
+--------------------------------------------------------------------
+
+LIBRARY  IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_unsigned.all;
+
+LIBRARY ieee;
+USE IEEE.STD_LOGIC_TEXTIO.ALL;
+USE STD.TEXTIO.ALL;
+
+ENTITY testb_tb_pipe IS
+END testb_tb_pipe;
+
+ARCHITECTURE pruebas OF testb_tb_pipe IS 
+FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
+   constant XBITS :INTEGER := 28; 
+   constant YBITS :INTEGER := 16;
+   constant GRAIN :INTEGER := 2; --Allways in 2!!!!
+   constant DEPTH :INTEGER := 1; --Every how much steps register
+	
+	
+   COMPONENT div_r4_pipe
+	generic (
+		XBITS : natural := XBITS;
+		YBITS : natural := YBITS;
+		GRAIN : natural := GRAIN;
+		DEPTH : natural := DEPTH
+	);
+   PORT(
+      a : IN std_logic_vector(XBITS-1 downto 0);
+      b : IN std_logic_vector(YBITS-1 downto 0);
+      clk : IN std_logic;          
+      q : OUT std_logic_vector(XBITS-1 downto 0);
+      r : OUT std_logic_vector(YBITS-1 downto 0)
+      );
+   END COMPONENT;
+
+   SIGNAL x :  std_logic_vector(XBITS-1 downto 0);
+   SIGNAL y :  std_logic_vector(YBITS-1 downto 0);
+   SIGNAL clk :  std_logic;
+   SIGNAL q :  std_logic_vector(XBITS-1 downto 0);
+   SIGNAL r :  std_logic_vector(YBITS-1 downto 0);
+   constant PERIOD: time := 10 ns;   
+
+BEGIN
+
+   uut: div_r4_pipe PORT MAP(
+      a => x, 
+		b => y,
+      clk => clk,
+      q => q, 
+		r => r
+   );
+
+   PROCESS -- clock process (drives clk),
+   BEGIN
+      clk <= '0';
+      WAIT FOR PERIOD/2;
+      clk <= '1';
+      WAIT FOR PERIOD/2;
+   END PROCESS;
+
+
+tb_gen : PROCESS --generate values
+   VARIABLE TX_LOC : LINE;
+   VARIABLE TX_STR : String(1 to 4096);
+   BEGIN
+			x <= CONV_STD_LOGIC_VECTOR (200, XBITS);
+			y <= CONV_STD_LOGIC_VECTOR (10, YBITS);
+			WAIT FOR PERIOD*(YBITS+4);
+			x <= CONV_STD_LOGIC_VECTOR (4364537, XBITS);
+			y <= CONV_STD_LOGIC_VECTOR (4325, YBITS);
+			WAIT FOR PERIOD*(YBITS+4);
+
+			x <= CONV_STD_LOGIC_VECTOR (83456342, XBITS);
+			y <= CONV_STD_LOGIC_VECTOR (6545, YBITS);
+			WAIT FOR PERIOD*(YBITS+4);
+			for i in 0 to 20 loop
+				x <= CONV_STD_LOGIC_VECTOR (100+i*2000, XBITS);
+				y <= CONV_STD_LOGIC_VECTOR (2000, YBITS);
+				WAIT FOR PERIOD;
+			end loop;
+			
+   END PROCESS;
+	
+--   tb_gen : PROCESS --generate values
+--   VARIABLE TX_LOC : LINE;
+--   VARIABLE TX_STR : String(1 to 4096);
+--   BEGIN
+--      for I in 0  to 2**XBITS -1 loop
+--         for J in 1 to 2**YBITS -1 loop
+--            x <= CONV_STD_LOGIC_VECTOR (I, XBITS);
+--            y <= CONV_STD_LOGIC_VECTOR (J, YBITS);
+--            WAIT FOR PERIOD;
+--         end loop;
+--      end loop;
+--
+--      WAIT FOR 3 * PERIOD;
+--
+--   END PROCESS;
+--
+--   tb_test : PROCESS --test the correctness of data
+--   VARIABLE TX_LOC : LINE;
+--   VARIABLE TX_STR : String(1 to 4096);
+--   BEGIN
+--      WAIT FOR (XBITS/GRAIN/DEPTH)*PERIOD;
+--      
+--      Wait for PERIOD; --Only if you produce the result one cycle later
+--      
+--      for I in 0 to 2**XBITS -1 loop
+--         for J in 1 to 2**YBITS -1 loop
+--            WAIT FOR PERIOD;
+--            IF ( I /= (J * CONV_INTEGER(Q)) + CONV_INTEGER(R)) THEN 
+--               write(TX_LOC,string'("ERROR!!! X=")); write(TX_LOC, X);
+--               write(TX_LOC,string'(" Y=")); write(TX_LOC, Y);
+--               write(TX_LOC,string'(" Q=")); write(TX_LOC, Q);
+--               write(TX_LOC,string'(" R=")); write(TX_LOC, R);
+--               write(TX_LOC, string'(" "));
+--               write(TX_LOC,string'(" (i=")); write(TX_LOC, i);
+--               write(TX_LOC,string'(" j=")); write(TX_LOC, j); 
+--               write(TX_LOC, string'(")"));
+--               TX_STR(TX_LOC.all'range) := TX_LOC.all;
+--               writeline(results, TX_LOC);
+--               Deallocate(TX_LOC);
+--               ASSERT (FALSE) REPORT TX_STR SEVERITY FAILURE;
+--            ELSIF (J < CONV_INTEGER(R)) THEN 
+--                  write(TX_LOC,string'("--> Error Resto Mayor que Y =")); write(TX_LOC, 0.0);
+--                  write(TX_LOC,string'("ns X=")); write(TX_LOC, X);
+--                  write(TX_LOC,string'(" Y=")); write(TX_LOC, Y);
+--                  write(TX_LOC,string'(" Q=")); write(TX_LOC, Q);
+--                  write(TX_LOC,string'(" R=")); write(TX_LOC, R);
+--                  write(TX_LOC, string'(" "));
+--                  TX_STR(TX_LOC.all'range) := TX_LOC.all;		
+--                  writeline(results, TX_LOC);
+--                  Deallocate(TX_LOC);
+--                  ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
+----            ELSE -- print if everything is ok
+----              write(TX_LOC,string'("OK -> X=")); write(TX_LOC, X);
+----              write(TX_LOC,string'(" Y=")); write(TX_LOC, Y);
+----              write(TX_LOC,string'(" Q=")); write(TX_LOC, Q);
+----              write(TX_LOC,string'(" R=")); write(TX_LOC, R);
+----              write(TX_LOC, string'(" "));
+----              TX_STR(TX_LOC.all'range) := TX_LOC.all;
+----              writeline(results, TX_LOC);
+----              Deallocate(TX_LOC);
+----              ASSERT (FALSE) REPORT TX_STR SEVERITY WARNING;
+--
+--            END IF;
+--
+--         end loop;
+--      end loop;
+--      ASSERT (FALSE) REPORT
+--      "Simulation successful (not a failure).  No problems detected. "
+--      SEVERITY FAILURE;
+--      --wait; -- will wait forever
+--   END PROCESS;
+
+END;
diff --git a/data_concentrator/sources/heap_sorter/Heap sorter for FPGA __ Overview __ OpenCores.pdf b/data_concentrator/sources/heap_sorter/Heap sorter for FPGA __ Overview __ OpenCores.pdf
new file mode 100644
index 0000000..e77e0a3
Binary files /dev/null and b/data_concentrator/sources/heap_sorter/Heap sorter for FPGA __ Overview __ OpenCores.pdf differ
diff --git a/data_concentrator/sources/heap_sorter/dpram4_synth.vhd b/data_concentrator/sources/heap_sorter/dpram4_synth.vhd
new file mode 100644
index 0000000..06e0670
--- /dev/null
+++ b/data_concentrator/sources/heap_sorter/dpram4_synth.vhd
@@ -0,0 +1,65 @@
+-- Dual port, single clock memory, inferrable in Xilinx and Altera FPGA
+
+library ieee;
+use ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+entity dp_ram_scl is
+   
+  generic
+    (
+      DATA_WIDTH : natural := 8;
+      ADDR_WIDTH : natural := 6
+      );
+
+  port
+    (
+      clk    : in  std_logic;
+      addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
+      addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
+      data_a : in  std_logic_vector((DATA_WIDTH-1) downto 0);
+      data_b : in  std_logic_vector((DATA_WIDTH-1) downto 0);
+      we_a   : in  std_logic := '1';
+      we_b   : in  std_logic := '1';
+      q_a    : out std_logic_vector((DATA_WIDTH -1) downto 0);
+      q_b    : out std_logic_vector((DATA_WIDTH -1) downto 0)
+      );
+
+end dp_ram_scl;
+
+
+architecture rtl of dp_ram_scl is
+
+  -- Create a type for data word
+  subtype data_word is std_logic_vector((DATA_WIDTH-1) downto 0);
+  type ram_memory is array((2**ADDR_WIDTH-1) downto 0) of data_word;
+
+  -- Declare the RAM variable.    
+  shared variable ram : ram_memory;
+
+begin
+
+  process(clk)
+  begin
+    if(rising_edge(clk)) then
+      -- Port B 
+      if(we_b = '1') then
+        ram(conv_integer(unsigned(addr_b))) := data_b;
+      end if;
+      q_b <= ram(conv_integer(unsigned(addr_b)));
+    end if;
+  end process;
+
+  process(clk)
+  begin
+    if(rising_edge(clk)) then
+      -- Port A
+      if(we_a = '1') then
+        ram(conv_integer(unsigned(addr_a))) := data_a;
+      end if;
+      q_a <= ram(conv_integer(unsigned(addr_a)));
+    end if;
+  end process;
+
+end rtl;
diff --git a/data_concentrator/sources/heap_sorter/sort_dpram.vhd b/data_concentrator/sources/heap_sorter/sort_dpram.vhd
new file mode 100644
index 0000000..e77035d
--- /dev/null
+++ b/data_concentrator/sources/heap_sorter/sort_dpram.vhd
@@ -0,0 +1,157 @@
+-------------------------------------------------------------------------------
+-- Title      : Parametrized DP RAM for heap-sorter
+-- Project    : heap-sorter
+-------------------------------------------------------------------------------
+-- File       : sort_dpram.vhd
+-- Author     : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
+-- Company    : 
+-- Created    : 2010-05-14
+-- Last update: 2011-07-06
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 Wojciech M. Zabolotny
+-- This file is published under the BSD license, so you can freely adapt
+-- it for your own purposes.
+-- Additionally this design has been described in my article:
+--    Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
+--    for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
+-- I'd be glad if you cite this article when you publish something based
+-- on my design.
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2010-05-14  1.0      wzab    Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+library work;
+use work.sorter_pkg.all;
+use work.sys_config.all;
+
+entity sort_dp_ram is
+
+  generic
+    (
+      ADDR_WIDTH : natural;
+      NLEVELS    : natural;
+      NAME       : string := "X"
+      );
+
+  port
+    (
+      clk    : in  std_logic;
+      addr_a : in  std_logic_vector(NLEVELS-1 downto 0);
+      addr_b : in  std_logic_vector(NLEVELS-1 downto 0);
+      data_a : in  T_DATA_REC;
+      data_b : in  T_DATA_REC;
+      we_a   : in  std_logic;
+      we_b   : in  std_logic;
+      q_a    : out T_DATA_REC;
+      q_b    : out T_DATA_REC
+      );
+
+end sort_dp_ram;
+
+architecture rtl of sort_dp_ram is
+
+  signal vq_a, vq_b, tdata_a, tdata_b : std_logic_vector(DATA_REC_WIDTH-1 downto 0);
+  signal reg                          : T_DATA_REC := DATA_REC_INIT_DATA;
+
+  component dp_ram_scl
+    generic (
+      DATA_WIDTH : natural;
+      ADDR_WIDTH : natural);
+    port (
+      clk    : in  std_logic;
+      addr_a : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
+      addr_b : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
+      data_a : in  std_logic_vector((DATA_WIDTH-1) downto 0);
+      data_b : in  std_logic_vector((DATA_WIDTH-1) downto 0);
+      we_a   : in  std_logic := '1';
+      we_b   : in  std_logic := '1';
+      q_a    : out std_logic_vector((DATA_WIDTH -1) downto 0);
+      q_b    : out std_logic_vector((DATA_WIDTH -1) downto 0));
+  end component;
+  
+begin
+
+  -- Convert our data records int std_logic_vector, so that
+  -- standard DP RAM may handle it
+  tdata_a <= tdrec2stlv(data_a);
+  tdata_b <= tdrec2stlv(data_b);
+
+  
+  i1 : if ADDR_WIDTH > 0 generate
+    -- When ADDR_WIDTH is above 0 embed the real DP RAM
+    -- (even though synthesis tool may still replace it with
+    -- registers during optimization for low ADDR_WIDTH)
+    
+    q_a <= stlv2tdrec(vq_a);
+    q_b <= stlv2tdrec(vq_b);
+
+    dp_ram_1 : dp_ram_scl
+      generic map (
+        DATA_WIDTH => DATA_REC_WIDTH,
+        ADDR_WIDTH => ADDR_WIDTH)
+      port map (
+        clk    => clk,
+        addr_a => addr_a(ADDR_WIDTH-1 downto 0),
+        addr_b => addr_b(ADDR_WIDTH-1 downto 0),
+        data_a => tdata_a,
+        data_b => tdata_b,
+        we_a   => we_a,
+        we_b   => we_b,
+        q_a    => vq_a,
+        q_b    => vq_b);
+
+  end generate i1;
+
+  i2 : if ADDR_WIDTH = 0 generate
+    -- When ADDR_WIDTH is 0, DP RAM should be simply replaced
+    -- with a register implemented below
+
+    p1 : process (clk)
+    begin  -- process p1
+      if clk'event and clk = '1' then   -- rising clock edge
+        if we_a = '1' then
+          reg <= data_a;
+          q_a <= data_a;
+          q_b <= data_a;
+        elsif we_b = '1' then
+          reg <= data_b;
+          q_a <= data_b;
+          q_b <= data_b;
+        else
+          q_a <= reg;
+          q_b <= reg;
+        end if;
+      end if;
+    end process p1;
+    
+  end generate i2;
+
+  dbg1 : if SORT_DEBUG generate
+
+    -- Process monitoring read/write accesses to the memory (only for debugging)
+    p3 : process (clk)
+      variable rline : line;
+    begin  -- process p1
+      if clk'event and clk = '1' then   -- rising clock edge
+        if(we_a = '1' and we_b = '1') then
+          write(rline, NAME);
+          write(rline, ADDR_WIDTH);
+          write(rline, string'(" Possible write collision!"));
+          writeline(reports, rline);
+        end if;
+
+      end if;
+    end process p3;
+  end generate dbg1;
+end rtl;
diff --git a/data_concentrator/sources/heap_sorter/sorter_ctrl.vhd b/data_concentrator/sources/heap_sorter/sorter_ctrl.vhd
new file mode 100644
index 0000000..09ed705
--- /dev/null
+++ b/data_concentrator/sources/heap_sorter/sorter_ctrl.vhd
@@ -0,0 +1,288 @@
+-------------------------------------------------------------------------------
+-- Title      : Sorting node controller for heap-sorter
+-- Project    : heap-sorter
+-------------------------------------------------------------------------------
+-- File       : sorter_ctrl.vhd
+-- Author     : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
+-- Company    : 
+-- Created    : 2010-05-14
+-- Last update: 2013-07-04
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 Wojciech M. Zabolotny
+-- This file is published under the BSD license, so you can freely adapt
+-- it for your own purposes.
+-- Additionally this design has been described in my article:
+--    Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
+--    for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
+-- I'd be glad if you cite this article when you publish something based
+-- on my design.
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2010-05-14  1.0      wzab    Created
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- The sorter controller is connected with three dual port memories.
+-- The first dual port memory tm_... provides the "upstream data"
+-- The second dual port memory lm_... provides the "left branch of downstream data"
+-- The third dual port memory rm_... provides the "right branch of downstream data"
+-- The controller is notified about availability of the new data by the
+-- "update" signal.
+-- However in this architecture we need to service two upstream memories!
+-- That's because we want to save one cycle, and to be able to issue
+--
+-- Important feature of each controller is the ability to clear the memory
+-- after reset.
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+library work;
+use work.sorter_pkg.all;
+use work.sys_config.all;
+
+entity sorter_ctrl is
+  
+  generic (
+    NLEVELS   : integer;                -- number of levels (max number of
+                                        -- address bits
+    NADDRBITS : integer                 -- number of used address bits
+    );
+
+  port (
+    -- Top memory connections
+    tm_din       : in  T_DATA_REC;
+    tm_dout      : out T_DATA_REC;
+    tm_addr      : out std_logic_vector(NLEVELS-1 downto 0);
+    tm_we        : out std_logic;
+    -- Left memory connections
+    lm_din       : in  T_DATA_REC;
+    lm_dout      : out T_DATA_REC;
+    lm_addr      : out std_logic_vector(NLEVELS-1 downto 0);
+    lm_we        : out std_logic;
+    -- Right memory connections
+    rm_din       : in  T_DATA_REC;
+    rm_dout      : out T_DATA_REC;
+    rm_addr      : out std_logic_vector(NLEVELS-1 downto 0);
+    rm_we        : out std_logic;
+    -- Upper level controller connections
+    up_in        : in  std_logic;
+    up_in_val    : in  T_DATA_REC;
+    up_in_addr   : in  std_logic_vector(NLEVELS-1 downto 0);
+    -- Upper level update notifier
+    up_out       : out std_logic;
+    up_out_val   : out T_DATA_REC;
+    up_out_addr  : out std_logic_vector(NLEVELS-1 downto 0);
+    -- Lower level controller connections
+    low_out      : out std_logic;
+    low_out_val  : out T_DATA_REC;
+    low_out_addr : out std_logic_vector(NLEVELS-1 downto 0);
+    low_in       : in  std_logic;
+    low_in_val   : in  T_DATA_REC;
+    low_in_addr  : in  std_logic_vector(NLEVELS-1 downto 0);
+    -- Lower level update notifier
+    -- System connections
+    clk          : in  std_logic;
+    clk_en       : in  std_logic;
+    ready_in     : in  std_logic;
+    ready_out    : out std_logic;       -- signals, when memory is cleared
+                                        -- after reset
+    rst_n        : in  std_logic);
+end sorter_ctrl;
+
+architecture sorter_ctrl_arch1 of sorter_ctrl is
+
+  type T_CTRL_STATE is (CTRL_RESET, CTRL_CLEAR, CTRL_IDLE, CTRL_S1, CTRL_S0);
+  signal ctrl_state, ctrl_state_next    : T_CTRL_STATE := CTRL_IDLE;
+  signal addr, addr_i                   : std_logic_vector(NLEVELS-1 downto 0);
+  signal s_low_in_addr, s_low_in_addr_i : std_logic_vector(NLEVELS-1 downto 0);
+  signal s_up_in_addr, s_up_in_addr_i   : std_logic_vector(NLEVELS-1 downto 0);
+  signal s_ready_out, s_ready_out_i     : std_logic;
+  signal s_low_in, s_low_in_i           : std_logic;
+  signal s_addr_out                     : std_logic_vector(NLEVELS-1 downto 0);
+  signal s_tm_dout                      : T_DATA_REC;
+  signal s_up_in_val_i, s_up_in_val     : T_DATA_REC   := DATA_REC_INIT_DATA;
+  signal s_low_in_val_i, s_low_in_val   : T_DATA_REC   := DATA_REC_INIT_DATA;
+
+
+  constant ADDR_MAX : std_logic_vector(NLEVELS-1 downto 0) := std_logic_vector(to_unsigned(2**NADDRBITS-1, NLEVELS));
+
+begin
+
+  tm_dout <= s_tm_dout;
+-- We have the two-process state machine.
+  p1 : process (addr, ctrl_state, lm_din, low_in, low_in_addr, low_in_val,
+                ready_in, rm_din, s_addr_out, s_low_in, s_low_in_addr,
+                s_low_in_val, s_ready_out, s_up_in_val, up_in, up_in_addr,
+                up_in_val)
+    variable l_val : T_DATA_REC;
+    variable r_val : T_DATA_REC;
+    
+  begin  -- process p1
+    -- defaults
+    ctrl_state_next <= ctrl_state;
+    tm_we           <= '0';
+    rm_we           <= '0';
+    lm_we           <= '0';
+    lm_addr         <= (others => '0');
+    rm_addr         <= (others => '0');
+    tm_addr         <= (others => '0');
+    s_ready_out_i   <= s_ready_out;
+    addr_i          <= addr;
+    up_out_val      <= DATA_REC_INIT_DATA;  -- to avoid latches
+    low_out_val     <= DATA_REC_INIT_DATA;  -- to avoid latches
+    s_low_in_addr_i <= s_low_in_addr;
+    s_low_in_i      <= low_in;
+    low_out         <= '0';
+    up_out          <= '0';
+    up_out_addr     <= (others => '0');
+    s_up_in_val_i   <= s_up_in_val;
+    s_low_in_val_i  <= s_low_in_val;
+    lm_dout         <= DATA_REC_INIT_DATA;
+    rm_dout         <= DATA_REC_INIT_DATA;
+    s_tm_dout       <= DATA_REC_INIT_DATA;
+    s_addr_out      <= (others => '0');
+    case ctrl_state is
+      when CTRL_RESET =>
+        addr_i          <= (others => '0');
+        s_ready_out_i   <= '0';
+        ctrl_state_next <= CTRL_CLEAR;
+      when CTRL_CLEAR =>
+        lm_addr <= addr;
+        rm_addr <= addr;
+        lm_dout <= DATA_REC_INIT_DATA;
+        rm_dout <= DATA_REC_INIT_DATA;
+        lm_we   <= '1';
+        rm_we   <= '1';
+        if addr = ADDR_MAX then
+          if ready_in = '1' then
+            s_ready_out_i   <= '1';
+            ctrl_state_next <= CTRL_IDLE;
+          end if;
+        else
+          addr_i <= std_logic_vector(unsigned(addr)+1);
+        end if;
+      when CTRL_IDLE =>
+        -- We read "down" memories ("upper" value is provided by the ``bypass channel'')
+        if up_in = '1' then
+          ctrl_state_next <= CTRL_S1;
+          tm_addr         <= up_in_addr;
+          lm_addr         <= up_in_addr;
+          rm_addr         <= up_in_addr;
+          addr_i          <= up_in_addr;
+          s_up_in_val_i   <= up_in_val;
+          if low_in = '1' then
+            s_low_in_val_i  <= low_in_val;
+            s_low_in_addr_i <= low_in_addr;
+          end if;
+        end if;
+      when CTRL_S1 =>
+        -- In this cycle we can compare data
+        l_val := lm_din;
+        r_val := rm_din;
+        -- Check, if we need to take value from lower ``bypass channel''
+        if s_low_in = '1' then
+          if (addr(NADDRBITS-1 downto 0) = s_low_in_addr(NADDRBITS-1 downto 0)) then
+            -- We are reading a value which was just updated, so we need to get it
+            -- from ``bypass channel'' instead of memory
+            if s_low_in_addr(NADDRBITS) = '1' then
+              l_val := s_low_in_val;
+            else
+              r_val := s_low_in_val;
+            end if;
+          end if;
+        end if;
+        if sort_cmp_lt(l_val, s_up_in_val) and sort_cmp_lt(l_val, r_val) then
+          -- The L-ram value is the smallest
+          -- Output the value from the L-ram and put the new value into the L-ram
+          s_tm_dout <= l_val;
+          tm_addr   <= addr;
+          tm_we     <= '1';
+
+          up_out_val  <= l_val;
+          up_out      <= '1';
+          up_out_addr <= addr;
+
+          lm_addr <= addr;
+          lm_dout <= s_up_in_val;
+          lm_we   <= '1';
+
+          low_out               <= '1';
+          low_out_val           <= s_up_in_val;
+          s_addr_out(NADDRBITS) <= '1';
+
+          if NADDRBITS > 0 then
+            s_addr_out(NADDRBITS-1 downto 0) <= addr(NADDRBITS-1 downto 0);
+          end if;
+          ctrl_state_next <= CTRL_IDLE;
+        elsif sort_cmp_lt(r_val, s_up_in_val) then
+          -- The R-ram value is the smallest
+          -- Output the value from the R-ram and put the new value into the R-ram
+          s_tm_dout <= r_val;
+          tm_addr   <= addr;
+          tm_we     <= '1';
+
+          up_out_val  <= r_val;
+          up_out      <= '1';
+          up_out_addr <= addr;
+
+          rm_addr <= addr;
+          rm_dout <= s_up_in_val;
+          rm_we   <= '1';
+
+          low_out     <= '1';
+          low_out_val <= s_up_in_val;
+
+          s_addr_out(NADDRBITS) <= '0';
+          if NADDRBITS > 0 then
+            s_addr_out(NADDRBITS-1 downto 0) <= addr(NADDRBITS-1 downto 0);
+          end if;
+          ctrl_state_next <= CTRL_IDLE;
+        else
+          -- The new value is the smallest
+          -- Nothing to do, no update downstream
+          s_tm_dout <= s_up_in_val;
+          tm_we     <= '1';
+          tm_addr   <= addr;
+
+          up_out_val  <= s_up_in_val;
+          up_out      <= '1';
+          up_out_addr <= addr;
+
+          ctrl_state_next <= CTRL_IDLE;
+        end if;
+      when others => null;
+    end case;
+  end process p1;
+
+  p2 : process (clk, rst_n) is
+  begin  -- process p2
+    if rst_n = '0' then                 -- asynchronous reset (active low)
+      ctrl_state    <= CTRL_RESET;
+      s_ready_out   <= '0';
+      addr          <= (others => '0');
+      s_low_in_addr <= (others => '0');
+      s_low_in      <= '0';
+      s_low_in_val  <= DATA_REC_INIT_DATA;
+      s_up_in_val   <= DATA_REC_INIT_DATA;
+      --update_out  <= '0';
+      --addr_out    <= (others => '0');
+    elsif clk'event and clk = '1' then  -- rising clock edge
+      s_ready_out   <= s_ready_out_i;
+      ctrl_state    <= ctrl_state_next;
+      addr          <= addr_i;
+      s_low_in_addr <= s_low_in_addr_i;
+      s_low_in_val  <= s_low_in_val_i;
+      s_up_in_val   <= s_up_in_val_i;
+      s_low_in      <= s_low_in_i;
+    end if;
+  end process p2;
+  ready_out    <= s_ready_out;
+  low_out_addr <= s_addr_out;
+end sorter_ctrl_arch1;
diff --git a/data_concentrator/sources/heap_sorter/sorter_pkg.vhd b/data_concentrator/sources/heap_sorter/sorter_pkg.vhd
new file mode 100644
index 0000000..7afe0e7
--- /dev/null
+++ b/data_concentrator/sources/heap_sorter/sorter_pkg.vhd
@@ -0,0 +1,192 @@
+-------------------------------------------------------------------------------
+-- Title      : Definitions for heap-sorter
+-- Project    : heap-sorter
+-------------------------------------------------------------------------------
+-- File       : sorter_pkg.vhd
+-- Author     : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
+-- Company    : 
+-- Created    : 2010-05-14
+-- Last update: 2011-07-11
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 Wojciech M. Zabolotny
+-- This file is published under the BSD license, so you can freely adapt
+-- it for your own purposes.
+-- Additionally this design has been described in my article:
+--    Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
+--    for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
+-- I'd be glad if you cite this article when you publish something based
+-- on my design.
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2010-05-14  1.0      wzab    Created
+-------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+library work;
+use work.sys_config.all;
+
+package sorter_pkg is
+  constant DATA_REC_WIDTH : integer := DATA_REC_SORT_KEY_WIDTH +
+                                       DATA_REC_PAYLOAD_WIDTH + 2;
+  
+
+  subtype T_SORT_KEY is unsigned (DATA_REC_SORT_KEY_WIDTH - 1 downto 0);
+  subtype T_PAYLOAD is std_logic_vector(DATA_REC_PAYLOAD_WIDTH - 1 downto 0);
+
+  --alias T_SORT_KEY is unsigned (12 downto 0);
+  type T_DATA_REC is record
+    d_key     : T_SORT_KEY;
+    init      : std_logic;
+    valid     : std_logic;
+    d_payload : T_PAYLOAD;
+  end record;
+
+  -- Special constant used to initially fill the sorter
+  -- Must be sorted so, that is smaller, than any other data
+  constant DATA_REC_INIT_DATA : T_DATA_REC := (
+    d_key     => to_unsigned(0, DATA_REC_SORT_KEY_WIDTH),
+    init      => '1',
+    valid     => '0',
+    d_payload => (others => '0')
+    );
+
+  -- Special constant used to ``flush'' the sorter at the end
+  constant DATA_REC_END_DATA : T_DATA_REC := (
+    d_key     => to_unsigned(0, DATA_REC_SORT_KEY_WIDTH),
+    init      => '1',
+    valid     => '1',
+    d_payload => (others => '0')
+    );
+
+  
+  function sort_cmp_lt (
+    constant v1 : T_DATA_REC;
+    constant v2 : T_DATA_REC)
+    return boolean;
+
+  function tdrec2stlv (
+    constant drec : T_DATA_REC)
+    return std_logic_vector;
+
+  function stlv2tdrec (
+    constant dstlv : std_logic_vector)
+    return T_DATA_REC;
+
+   file reports : text open write_mode is "STD_OUTPUT";
+
+end sorter_pkg;
+
+package body sorter_pkg is
+
+  function stlv2tdrec (
+    constant dstlv : std_logic_vector)
+    return T_DATA_REC is
+    variable result : T_DATA_REC;
+    variable j      : integer := 0;
+  begin  -- stlv2drec
+    j                := 0;
+    result.d_key     := unsigned(dstlv(j-1+DATA_REC_SORT_KEY_WIDTH downto j));
+    j                := j+DATA_REC_SORT_KEY_WIDTH;
+    result.valid     := dstlv(j);
+    j                := j+1;
+    result.init      := dstlv(j);
+    j                := j+1;
+    result.d_payload := dstlv(j-1+DATA_REC_PAYLOAD_WIDTH downto j);
+    j                := j+DATA_REC_PAYLOAD_WIDTH;
+    return result;
+  end stlv2tdrec;
+
+  function tdrec2stlv (
+    constant drec : T_DATA_REC)
+    return std_logic_vector is
+    variable result : std_logic_vector(DATA_REC_WIDTH-1 downto 0);
+    variable j      : integer := 0;
+  begin  -- tdrec2stlv
+    j                                            := 0;
+    result(j-1+DATA_REC_SORT_KEY_WIDTH downto j) := std_logic_vector(drec.d_key);
+    j                                            := j+DATA_REC_SORT_KEY_WIDTH;
+    result(j)                                    := drec.valid;
+    j                                            := j+1;
+    result(j)                                    := drec.init;
+    j                                            := j+1;
+    result(j-1+DATA_REC_PAYLOAD_WIDTH downto j)  := std_logic_vector(drec.d_payload);
+    j                                            := j+DATA_REC_PAYLOAD_WIDTH;
+    return result;
+  end tdrec2stlv;
+
+
+  -- Function sort_cmp_lt returns TRUE when the first opperand is ``less'' than
+  -- the second one
+  function sort_cmp_lt (
+    constant v1 : T_DATA_REC;
+    constant v2 : T_DATA_REC)
+    return boolean is
+    variable rline : line;
+    variable dcomp  : unsigned(DATA_REC_SORT_KEY_WIDTH-1 downto 0) := (others => '0');
+  begin  -- sort_cmp_lt
+    -- Check the special cases
+    if (v1.init = '1') and (v2.init = '0') then
+      -- v1 is the special record, v2 is the standard one
+      if v1.valid = '0' then
+        -- initialization record - ``smaller'' than all standard records
+        return true;
+      else
+        -- end record - ``bigger'' than all standard records
+        return false;
+      end if;
+    elsif (v1.init = '0') and (v2.init = '1') then
+      -- v2 is the special record, v1 is the standard one      
+      if (v2.valid = '0') then
+        -- v2 is the initialization record - it is ``smaller'' than standard record v1
+        return false;
+      else
+        -- v2 is the end record - it is ``bigger'' than standard record v1
+        return true;
+      end if;
+    elsif (v1.init = '1') and (v2.init = '1') then
+      -- both v1 and v2 are special records
+      if (v1.valid = '0') and (v2.valid = '1') then
+        -- v1 - initial record, v2 - end record
+        return true;
+      else
+        -- v1 is end record, so it is ``bigger'' or ``equal'' to other records
+        return false;
+      end if;
+    elsif (v1.init = '0') and (v2.init = '0') then
+      -- We compare standard words
+      -- We must consider the fact, that in longer sequences of data records
+      -- the sort keys may wrap around
+      -- therefore we perform subtraction modulo
+      -- 2**DATA_REC_SORT_KEY_WIDTH and check the MSB
+      dcomp := v1.d_key-v2.d_key;
+      if dcomp(DATA_REC_SORT_KEY_WIDTH-1) = '1' then
+      --if signed(v1.d_key - v2.d_key)<0 then -- old implementation
+        return true;
+      elsif v2.d_key = v1.d_key then
+        if v2.valid = '1' then
+          return true;
+        else
+          -- Empty data records should wait
+          return false;
+        end if;
+      else
+        return false;
+      end if;
+    else
+      assert false report "Wrong records in sort_cmp_lt" severity error;
+      return false;
+    end if;
+    return false;                       -- should never happen
+  end sort_cmp_lt;
+
+
+end sorter_pkg;
+
diff --git a/data_concentrator/sources/heap_sorter/sorter_sys.vhd b/data_concentrator/sources/heap_sorter/sorter_sys.vhd
new file mode 100644
index 0000000..b3903da
--- /dev/null
+++ b/data_concentrator/sources/heap_sorter/sorter_sys.vhd
@@ -0,0 +1,290 @@
+-------------------------------------------------------------------------------
+-- Title      : Top entity of heap-sorter
+-- Project    : heap-sorter
+-------------------------------------------------------------------------------
+-- File       : sorter_sys.vhd
+-- Author     : Wojciech M. Zabolotny <wzab@ise.pw.edu.pl>
+-- Company    : 
+-- Created    : 2010-05-14
+-- Last update: 2011-07-11
+-- Platform   : 
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: 
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 Wojciech M. Zabolotny
+-- This file is published under the BSD license, so you can freely adapt
+-- it for your own purposes.
+-- Additionally this design has been described in my article
+-- Additionally this design has been described in my article:
+--    Wojciech M. Zabolotny, "Dual port memory based Heapsort implementation
+--    for FPGA", Proc. SPIE 8008, 80080E (2011); doi:10.1117/12.905281
+-- I'd be glad if you cite this article when you publish something based
+-- on my design.
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2010-05-14  1.0      wzab    Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+library work;
+use work.sorter_pkg.all;
+use work.sys_config.all;
+
+entity sorter_sys is
+  generic (
+    NLEVELS : integer := SYS_NLEVELS     -- number of levels in the sorter heap
+    );
+
+  port (
+    din   : in  T_DATA_REC;
+    we    : in  std_logic;
+    dout  : out T_DATA_REC;
+    dav   : out std_logic;
+    clk   : in  std_logic;
+    rst_n : in  std_logic;
+    ready : out std_logic);
+end sorter_sys;
+
+architecture sorter_sys_arch1 of sorter_sys is
+
+  component sort_dp_ram
+    generic (
+      ADDR_WIDTH : natural;
+      NLEVELS    : natural;
+      NAME       : string);
+    port (
+      clk    : in  std_logic;
+      addr_a : in  std_logic_vector(NLEVELS-1 downto 0);
+      addr_b : in  std_logic_vector(NLEVELS-1 downto 0);
+      data_a : in  T_DATA_REC;
+      data_b : in  T_DATA_REC;
+      we_a   : in  std_logic;
+      we_b   : in  std_logic;
+      q_a    : out T_DATA_REC;
+      q_b    : out T_DATA_REC);
+  end component;
+
+  component sorter_ctrl
+    generic (
+      NLEVELS   : integer;
+      NADDRBITS : integer);
+    port (
+      tm_din       : in  T_DATA_REC;
+      tm_dout      : out T_DATA_REC;
+      tm_addr      : out std_logic_vector(NLEVELS-1 downto 0);
+      tm_we        : out std_logic;
+      lm_din       : in  T_DATA_REC;
+      lm_dout      : out T_DATA_REC;
+      lm_addr      : out std_logic_vector(NLEVELS-1 downto 0);
+      lm_we        : out std_logic;
+      rm_din       : in  T_DATA_REC;
+      rm_dout      : out T_DATA_REC;
+      rm_addr      : out std_logic_vector(NLEVELS-1 downto 0);
+      rm_we        : out std_logic;
+      up_in        : in  std_logic;
+      up_in_val    : in  T_DATA_REC;
+      up_in_addr   : in  std_logic_vector(NLEVELS-1 downto 0);
+      up_out       : out std_logic;
+      up_out_val   : out T_DATA_REC;
+      up_out_addr  : out std_logic_vector(NLEVELS-1 downto 0);
+      low_out      : out std_logic;
+      low_out_val  : out T_DATA_REC;
+      low_out_addr : out std_logic_vector(NLEVELS-1 downto 0);
+      low_in       : in  std_logic;
+      low_in_val   : in  T_DATA_REC;
+      low_in_addr  : in  std_logic_vector(NLEVELS-1 downto 0);
+      clk          : in  std_logic;
+      clk_en       : in  std_logic;
+      ready_in     : in  std_logic;
+      ready_out    : out std_logic;
+      rst_n        : in  std_logic);
+  end component;
+
+  -- Create signals for address buses
+  -- Some of them will remain unused.
+  subtype T_SORT_BUS_ADDR is std_logic_vector(NLEVELS-1 downto 0);
+  type T_SORT_ADDR_BUSES is array (NLEVELS downto 0) of T_SORT_BUS_ADDR;
+  signal low_addr, up_addr, addr_dr, addr_dl, addr_u                       : T_SORT_ADDR_BUSES                  := (others => (others => '0'));
+  type T_SORT_DATA_BUSES is array (NLEVELS downto 0) of T_DATA_REC;
+  signal up_update_path, low_update_path, data_d, data_dl, data_dr, data_u : T_SORT_DATA_BUSES                  := (others => DATA_REC_INIT_DATA);
+  signal q_dr, q_dl, q_u, q_ul, q_ur                                       : T_SORT_DATA_BUSES                  := (others => DATA_REC_INIT_DATA);
+  signal we_ul, we_ur, we_u, we_dl, we_dr, low_update, up_update, s_ready  : std_logic_vector(NLEVELS downto 0) := (others => '0');
+  signal addr_switch, addr_switch_del                                      : std_logic_vector(NLEVELS downto 0);
+  signal l0_reg                                                            : T_DATA_REC;
+  signal clk_en                                                            : std_logic                          := '1';
+  
+begin  -- sorter_sys_arch1
+
+-- Build the sorting tree
+  
+  g1 : for i in 0 to NLEVELS-1 generate
+
+    -- Two RAMs from the upper level are seen as a single RAM
+    -- We use the most significant bit (i-th bit) to distinguish RAM
+    -- In all RAMs the A-ports are used for upstream connections
+    -- and the B-ports are used for downstream connections
+
+    -- Below are processes used to combine two upstream RAMs in a single one
+    i0a : if i >= 1 generate
+      addr_switch(i) <= addr_u(i)(i-1);
+    end generate i0a;
+    i0b : if i = 0 generate
+      addr_switch(i) <= '0';
+    end generate i0b;
+
+    -- There is a problem with reading of data provided by two upstream RAMs
+    -- we need to multiplex the data...
+    -- Delay for read data multiplexer
+    s1 : process (clk, rst_n)
+    begin  -- process s1
+      if rst_n = '0' then                 -- asynchronous reset (active low)
+        addr_switch_del(i) <= '0';
+      elsif clk'event and clk = '1' then  -- rising clock edge
+        addr_switch_del(i) <= addr_switch(i);
+      end if;
+    end process s1;
+
+    -- Upper RAM signals' multiplexer
+    c1 : process (addr_switch, addr_switch_del, q_ul, q_ur, we_u)
+    begin  -- process c1
+      we_ul(i) <= '0';
+      we_ur(i) <= '0';
+      if addr_switch(i) = '1' then
+        we_ul(i) <= we_u(i);
+      else
+        we_ur(i) <= we_u(i);
+      end if;
+      if addr_switch_del(i) = '1' then
+        q_u(i) <= q_ul(i);
+      else
+        q_u(i) <= q_ur(i);
+      end if;
+    end process c1;
+
+    dp_ram_l : sort_dp_ram
+      generic map (
+        NLEVELS    => NLEVELS,
+        ADDR_WIDTH => i,
+        NAME       => "L")
+      port map (
+        clk    => clk,
+        addr_a => addr_dl(i),
+        addr_b => addr_u(i+1),
+        data_a => data_dl(i),
+        data_b => data_u(i+1),
+        we_a   => we_dl(i),
+        we_b   => we_ul(i+1),
+        q_a    => q_dl(i),
+        q_b    => q_ul(i+1));
+
+    dp_ram_r : sort_dp_ram
+      generic map (
+        NLEVELS    => NLEVELS,
+        ADDR_WIDTH => i,
+        NAME       => "R")
+      port map (
+        clk    => clk,
+        addr_a => addr_dr(i),
+        addr_b => addr_u(i+1),
+        data_a => data_dr(i),
+        data_b => data_u(i+1),
+        we_a   => we_dr(i),
+        we_b   => we_ur(i+1),
+        q_a    => q_dr(i),
+        q_b    => q_ur(i+1));
+
+    sorter_ctrl_1 : sorter_ctrl
+      generic map (
+        NLEVELS   => NLEVELS,
+        NADDRBITS => i)
+      port map (
+        tm_din       => q_u(i),
+        tm_dout      => data_u(i),
+        tm_addr      => addr_u(i),
+        tm_we        => we_u(i),
+        lm_din       => q_dl(i),
+        lm_dout      => data_dl(i),
+        lm_addr      => addr_dl(i),
+        lm_we        => we_dl(i),
+        rm_din       => q_dr(i),
+        rm_dout      => data_dr(i),
+        rm_addr      => addr_dr(i),
+        rm_we        => we_dr(i),
+        up_in        => up_update(i),
+        up_in_val    => up_update_path(i),
+        up_in_addr   => up_addr(i),
+        up_out       => low_update(i),
+        up_out_val   => low_update_path(i),
+        up_out_addr  => low_addr(i),
+        low_in       => low_update(i+1),
+        low_in_val   => low_update_path(i+1),
+        low_in_addr  => low_addr(i+1),
+        low_out      => up_update(i+1),  -- connections to the next level
+        low_out_val  => up_update_path(i+1),
+        low_out_addr => up_addr(i+1),
+        clk          => clk,
+        clk_en       => clk_en,
+        ready_in     => s_ready(i+1),
+        ready_out    => s_ready(i),
+        rst_n        => rst_n);
+
+  end generate g1;
+  -- top level
+
+  -- On the top level we have only a single register
+  process (clk, rst_n)
+    variable rline : line;
+  begin  -- process
+    if rst_n = '0' then                 -- asynchronous reset (active low)
+      l0_reg <= DATA_REC_INIT_DATA;
+    elsif clk'event and clk = '1' then  -- rising clock edge
+      dav <= '0';
+      if we_u(0) = '1' then
+        l0_reg <= data_u(0);
+        dout   <= data_u(0);
+        dav    <= '1';
+        if SORT_DEBUG then
+          write(rline, string'("OUT: "));
+          write(rline, tdrec2stlv(data_u(0)));
+          writeline(reports, rline);
+        end if;
+      elsif we = '1' then
+        if SORT_DEBUG then
+          write(rline, string'("IN: "));
+          write(rline, tdrec2stlv(din));
+          writeline(reports, rline);
+        end if;
+        l0_reg <= din;
+        dout   <= din;
+      else
+        dout <= l0_reg;
+      end if;
+    end if;
+  end process;
+  ready             <= s_ready(0);
+  q_ur(0)           <= l0_reg;
+  q_ul(0)           <= l0_reg;
+  up_update(0)      <= we;
+  up_update_path(0) <= din;
+  up_addr(0)        <= (others => '0');
+
+  -- signals for the last level
+
+  s_ready(NLEVELS) <= '1';
+  --addr(NLEVELS)    <= (others => '0');
+  data_dr(NLEVELS) <= DATA_REC_INIT_DATA;
+  data_dl(NLEVELS) <= DATA_REC_INIT_DATA;
+  we_dl(NLEVELS)   <= '0';
+  we_dr(NLEVELS)   <= '0';
+
+  low_update(NLEVELS)      <= '0';
+  low_update_path(NLEVELS) <= DATA_REC_INIT_DATA;
+  low_addr(0)              <= (others => '0');
+  
+end sorter_sys_arch1;
diff --git a/data_concentrator/sources/heap_sorter/sys_config.vhd b/data_concentrator/sources/heap_sorter/sys_config.vhd
new file mode 100644
index 0000000..e0948c6
--- /dev/null
+++ b/data_concentrator/sources/heap_sorter/sys_config.vhd
@@ -0,0 +1,9 @@
+library ieee;
+use ieee.std_logic_1164.all;
+library work;
+package sys_config is
+  constant SORT_DEBUG              : boolean :=false;
+  constant SYS_NLEVELS             : integer :=5;
+  constant DATA_REC_SORT_KEY_WIDTH : integer :=31+16+12; -- superburst+timestamp+constantfraction
+  constant DATA_REC_PAYLOAD_WIDTH  : integer :=16+16+8;  -- adcnumber+energy+status
+end sys_config;
diff --git a/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try1.vhd b/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try1.vhd
deleted file mode 100644
index c5b1f83..0000000
--- a/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try1.vhd
+++ /dev/null
@@ -1,181 +0,0 @@
------------------------------------------------------------------------------------
--- Wrapper for asynchronous FIFO : width 32, 8 deep
------------------------------------------------------------------------------------
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY async_fifo_nn_thfull_FWFT_512x36 IS
-	PORT
-	(
-		rst                     : in std_logic;
-		wr_clk                  : in std_logic;
-		rd_clk                  : in std_logic;
-		din                     : in std_logic_vector(35 downto 0);
-		wr_en                   : in std_logic;
-		rd_en                   : in std_logic;
-		dout                    : out std_logic_vector(35 downto 0);
-		full                    : out std_logic;
-		empty                   : out std_logic;
-		rd_data_count           : out std_logic_vector(8 downto 0);
-		prog_full               : out std_logic
-	);
-END async_fifo_nn_thfull_FWFT_512x36;
-
-
-ARCHITECTURE Behavioral OF async_fifo_nn_thfull_FWFT_512x36 IS
-component async_fifo_nn_thfull_512x36_ecp3
-    port (
-        Data: in  std_logic_vector(35 downto 0); 
-        WrClock: in  std_logic; 
-        RdClock: in  std_logic; 
-        WrEn: in  std_logic; 
-        RdEn: in  std_logic; 
-        Reset: in  std_logic; 
-        RPReset: in  std_logic; 
-        Q: out  std_logic_vector(35 downto 0); 
-        RCNT: out  std_logic_vector(9 downto 0); 
-        Empty: out  std_logic; 
-        Full: out  std_logic; 
-        AlmostFull: out  std_logic);
-end component;
-
-signal ff_data_out : std_logic_vector (35 DOWNTO 0) := (others => '0');
-signal ff_read_request : std_logic := '0';
-signal ff_read_request_i : std_logic := '0';
-signal ff_read_request_final : std_logic := '0';
-signal ff_empty : std_logic := '0';
-signal data_available_i : std_logic := '0';
-signal rd_data_count_i : std_logic_vector (9 DOWNTO 0) := (others => '0');
-
-BEGIN
--- data_available <= data_available_i;
-process (rd_clk)
-begin
-	if rising_edge(rd_clk) then
-		ff_read_request <= '0';
-		if rst='1' then
-			data_available_i <= '0';
-		else
-			if (ff_empty='0') and (data_available_i='0') and (rd_en='0') then
-				if ff_read_request_i='1' then
-					ff_read_request <= '0';
-					dout <= ff_data_out;
-					data_available_i <= '1';
-					empty <= '0';
-				else 
-					if ff_read_request='0' then
-						ff_read_request <= '1';
-					end if;
-					data_available_i <= '0';
---					empty <= '0';
-				end if;
-			elsif (ff_empty='0') and (data_available_i='0') and (rd_en='1') then  -- ignore
-				if ff_read_request_i='1' then
-					ff_read_request <= '0';
-					dout <= ff_data_out;
-					data_available_i <= '1';
-					empty <= '0';
-				else 
-					ff_read_request <= '1';
-					data_available_i <= '0';
---					empty <= '0';
-				end if;
-				
-			elsif (ff_empty='0') and (data_available_i='1') and (rd_en='0') then  
-				if ff_read_request_i='1' then -- should not occur
-					ff_read_request <= '0';
-					dout <= ff_data_out;
-					data_available_i <= '1';
-					empty <= '0';
-				else 
-					ff_read_request <= '0';
-					data_available_i <= '1';
-					empty <= '0';
-				end if;
-			elsif (ff_empty='0') and (data_available_i='1') and (rd_en='1') then  
-				if ff_read_request_i='1' then
-					ff_read_request <= '1';
-					dout <= ff_data_out;
-					data_available_i <= '1';
-					empty <= '0';
-				else 
-					ff_read_request <= '1';
-					data_available_i <= '0';
-					empty <= '0';
-				end if;
-
-			elsif (ff_empty='1') and (data_available_i='0') and (rd_en='0') then  
-				if ff_read_request_i='1' then
-					ff_read_request <= '0';
-					dout <= ff_data_out;
-					data_available_i <= '1';
-					empty <= '0';
-				else 
-					ff_read_request <= '0';
-					data_available_i <= '0';
-					empty <= '1';
-				end if;
-			elsif (ff_empty='1') and (data_available_i='0') and (rd_en='1') then -- ignore rd
-				if ff_read_request_i='1' then
-					ff_read_request <= '0';
-					dout <= ff_data_out;
-					data_available_i <= '1';
-					empty <= '0';
-				else 
-					ff_read_request <= '0';
-					data_available_i <= '0';
-					empty <= '1';
-				end if;
-
-			elsif (ff_empty='1') and (data_available_i='1') and (rd_en='0') then  
-				if ff_read_request_i='1' then
-					ff_read_request <= '0';
-					dout <= ff_data_out;
-					data_available_i <= '1';
-					empty <= '0';
-				else 
-					ff_read_request <= '0';
-					data_available_i <= '1';
-					empty <= '0';
-				end if;
-			elsif (ff_empty='1') and (data_available_i='1') and (rd_en='1') then  
-				if ff_read_request_i='1' then
-					ff_read_request <= '0';
-					dout <= ff_data_out;
-					data_available_i <= '1';
-					empty <= '0';
-				else 
-					ff_read_request <= '0';
-					data_available_i <= '0';
-					empty <= '1';
-				end if;
-			end if;
-		end if;
-		ff_read_request_i <= ff_read_request_final;
-	end if;
-end process;
-
-async_fifo_nn_thfull_512x36_ecp3_1: async_fifo_nn_thfull_512x36_ecp3 port map(
-		Data => din,
-		WrClock => wr_clk,
-		RdClock => rd_clk,
-		WrEn => wr_en,
-		RdEn => ff_read_request_final,
-		Reset => rst,
-        RPReset => rst,
-		Q => ff_data_out,
-        RCNT => rd_data_count_i, 
-		Empty => ff_empty,
-		Full => full,
-        AlmostFull => prog_full);
-rd_data_count <= (others => '1') when rd_data_count_i(9)='1' else rd_data_count_i(8 downto 0);
-
-ff_read_request_final <= '1' when
-	((rd_en='1') and (ff_empty='0') and (data_available_i='1')) or
-	((rd_en='0') and (ff_empty='0') and (data_available_i='0') and (ff_read_request_i='0'))
-	else '0';
-
-
-
-END Behavioral;
diff --git a/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try2.vhd b/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try2.vhd
deleted file mode 100644
index 70597b1..0000000
--- a/data_concentrator/sources/lattice/async_fifo_nn_thfull_FWFT_512x36_try2.vhd
+++ /dev/null
@@ -1,117 +0,0 @@
------------------------------------------------------------------------------------
--- Wrapper for asynchronous FIFO : width 32, 8 deep
------------------------------------------------------------------------------------
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY async_fifo_nn_thfull_FWFT_512x36 IS
-	PORT
-	(
-		rst                     : in std_logic;
-		wr_clk                  : in std_logic;
-		rd_clk                  : in std_logic;
-		din                     : in std_logic_vector(35 downto 0);
-		wr_en                   : in std_logic;
-		rd_en                   : in std_logic;
-		dout                    : out std_logic_vector(35 downto 0);
-		full                    : out std_logic;
-		empty                   : out std_logic;
-		rd_data_count           : out std_logic_vector(8 downto 0);
-		prog_full               : out std_logic
-	);
-END async_fifo_nn_thfull_FWFT_512x36;
-
-
-ARCHITECTURE Behavioral OF async_fifo_nn_thfull_FWFT_512x36 IS
-component async_fifo_nn_thfull_512x36_ecp3
-    port (
-        Data: in  std_logic_vector(35 downto 0); 
-        WrClock: in  std_logic; 
-        RdClock: in  std_logic; 
-        WrEn: in  std_logic; 
-        RdEn: in  std_logic; 
-        Reset: in  std_logic; 
-        RPReset: in  std_logic; 
-        Q: out  std_logic_vector(35 downto 0); 
-        RCNT: out  std_logic_vector(9 downto 0); 
-        Empty: out  std_logic; 
-        Full: out  std_logic; 
-        AlmostFull: out  std_logic);
-end component;
-
-
-signal fifo_dout                      : std_logic_vector (35 downto 0) := (others => '0');
-signal middle_dout                    : std_logic_vector (35 downto 0) := (others => '0');
-signal rd_data_count_i                : std_logic_vector (9 downto 0) := (others => '0');
-signal fifo_empty                     : std_logic := '0';
-signal will_update_middle             : std_logic := '0';
-signal will_update_dout               : std_logic := '0';
-signal middle_valid                   : std_logic := '0';
-signal fifo_valid                     : std_logic := '0';
-signal dout_valid                     : std_logic := '0';
-signal fifo_rd_en                     : std_logic := '0';
-
-
-BEGIN
-	   
-async_fifo_nn_thfull_512x36_ecp3_1: async_fifo_nn_thfull_512x36_ecp3 port map(
-		Data => din,
-		WrClock => wr_clk,
-		RdClock => rd_clk,
-		WrEn => wr_en,
-		RdEn => fifo_rd_en,
-		Reset => rst,
-        RPReset => rst,
-		Q => fifo_dout,
-        RCNT => rd_data_count_i, 
-		Empty => fifo_empty,
-		Full => full,
-        AlmostFull => prog_full);
-rd_data_count <= (others => '1') when rd_data_count_i(9)='1' else rd_data_count_i(8 downto 0);
-   
-will_update_middle <= '1' when (fifo_valid='1') and  (middle_valid=will_update_dout) else '0';
-will_update_dout <= '1' when ((middle_valid='1') or  (fifo_valid='1')) and ((rd_en='1') and (dout_valid='0')) else '0';
-fifo_rd_en <= '1' when (fifo_empty='0') and (not (((middle_valid='1') and (dout_valid='1') and (fifo_valid='1')))) else '0';
-empty <= not dout_valid;
-
-process (rd_clk)
-begin
-	if rising_edge(rd_clk) then
-		if rst='1' then
-			fifo_valid <= '0';
-			middle_valid <= '0';
-			dout_valid <= '0';
-			dout <= (others => '0');
-			middle_dout <= (others => '0');
-		else
-            if (will_update_middle='1') then
-               middle_dout <= fifo_dout;
-            end if;
-            if (will_update_dout='1') then
-				if middle_valid='1' then
-					dout <= middle_dout;
-				else
-					dout <= fifo_dout;
-				end if;
-            end if;
-            if (fifo_rd_en='1') then
-               fifo_valid <= '1';
-            elsif ((will_update_middle='1') or (will_update_dout='1')) then
-               fifo_valid <= '0';
-            end if;
-            if (will_update_middle='1') then
-               middle_valid <= '1';
-            elsif (will_update_dout='1') then
-               middle_valid <= '0';
-            end if;
-            if (will_update_dout='1') then
-               dout_valid <= '1';
-            elsif (rd_en='1') then
-               dout_valid <= '0';
-			end if;
-		end if;
-	end if;
-end process;
-
-END Behavioral;
diff --git a/data_concentrator/sources/lattice/trb_net16_med_1_2sync_3_ecp3_sfp_old.vhd b/data_concentrator/sources/lattice/trb_net16_med_1_2sync_3_ecp3_sfp_old.vhd
deleted file mode 100644
index 15f7d37..0000000
--- a/data_concentrator/sources/lattice/trb_net16_med_1_2sync_3_ecp3_sfp_old.vhd
+++ /dev/null
@@ -1,1151 +0,0 @@
---Media interface for Lattice ECP3 using PCS at 2GHz
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-
-entity trb_net16_med_1_2sync_3_ecp3_sfp is
-  port(
-    CLK                : in  std_logic; -- SerDes clock
-    SYSCLK             : in  std_logic; -- fabric clock
-    RESET              : in  std_logic; -- synchronous reset
-    CLEAR              : in  std_logic; -- asynchronous reset
-    CLK_EN             : in  std_logic;
-    --Internal Connection
-    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
-    MED_DATAREADY_IN   : in  std_logic;
-    MED_READ_OUT       : out std_logic;
-    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
-    MED_DATAREADY_OUT  : out std_logic;
-    MED_READ_IN        : in  std_logic;
-    REFCLK2CORE_OUT    : out std_logic;
-    CLK_RX_HALF_OUT    : out std_logic;
-    CLK_RX_FULL_OUT    : out std_logic;
-    --SFP Connection
-    SD_RXD_P_IN        : in  std_logic;
-    SD_RXD_N_IN        : in  std_logic;
-    SD_TXD_P_OUT       : out std_logic;
-    SD_TXD_N_OUT       : out std_logic;
-    SD_REFCLK_P_IN     : in  std_logic;
-    SD_REFCLK_N_IN     : in  std_logic;
-    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
-    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
-    SD_TXDIS_OUT       : out  std_logic; -- SFP disable
-    --Control Interface
-    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
-    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
-    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
-    SCI_READ           : in  std_logic := '0';
-    SCI_WRITE          : in  std_logic := '0';
-    SCI_ACK            : out std_logic := '0';
-    SCI_NACK           : out std_logic := '0';
-	-- SODA serdes channel
-    SODA_RXD_P_IN      : in  std_logic;
-    SODA_RXD_N_IN      : in  std_logic;
-    SODA_TXD_P_OUT     : out std_logic;
-    SODA_TXD_N_OUT     : out std_logic;
-	SODA_DLM_IN        : in  std_logic;
-	SODA_DLM_WORD_IN   : in  std_logic_vector(7 downto 0);
-	SODA_DLM_OUT       : out  std_logic;
-	SODA_DLM_WORD_OUT  : out  std_logic_vector(7 downto 0);
-    SODA_CLOCK_OUT     : out  std_logic; -- 200MHz
-	
-    -- Connection to addon interface        
-    DOUT_TXD_P_OUT     : out  std_logic;
-    DOUT_TXD_N_OUT     : out  std_logic;
-    SFP_MOD0_5         : in  std_logic;
-    SFP_MOD0_3         : in  std_logic;          
-    SFP_LOS_5          : in  std_logic;          
-    SFP_LOS_3          : in  std_logic;
-	TX_READY_CH3       : out std_logic;
-    TX_DATA_CH3        : in std_logic_vector(7 downto 0);
-    TX_K_CH3           : in std_logic;
-    -- Status and control port
-    STAT_OP            : out std_logic_vector (15 downto 0);
-    CTRL_OP            : in  std_logic_vector (15 downto 0);
-    STAT_DEBUG         : out std_logic_vector (63 downto 0);
-    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
-   );
-end entity;
-
-architecture trb_net16_med_1_2sync_3_ecp3_sfp_arch of trb_net16_med_1_2sync_3_ecp3_sfp is
-
-
-  -- Placer Directives
-  attribute HGROUP : string;
-  -- for whole architecture
-  attribute HGROUP of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture  is "media_interface_group";
-  attribute syn_sharing : string;
-  attribute syn_sharing of trb_net16_med_1_2sync_3_ecp3_sfp_arch : architecture is "off";
-
-  --OJK 29-nov-2013
-	component sfp_1_3_200_int
-	port(
-		hdinp_ch1          : IN std_logic;
-		hdinn_ch1          : IN std_logic;
-		sci_sel_ch1        : IN std_logic;
-		rxiclk_ch1         : IN std_logic;
-		txiclk_ch1         : IN std_logic;
-		fpga_rxrefclk_ch1  : IN std_logic;
-		txdata_ch1         : IN std_logic_vector(15 downto 0);
-		tx_k_ch1           : IN std_logic_vector(1 downto 0);
-		tx_force_disp_ch1  : IN std_logic_vector(1 downto 0);
-		tx_disp_sel_ch1    : IN std_logic_vector(1 downto 0);
-		sb_felb_ch1_c      : IN std_logic;
-		sb_felb_rst_ch1_c  : IN std_logic;
-		tx_pwrup_ch1_c     : IN std_logic;
-		rx_pwrup_ch1_c     : IN std_logic;
-		tx_div2_mode_ch1_c : IN std_logic;
-		rx_div2_mode_ch1_c : IN std_logic;
-		sci_sel_ch3        : IN std_logic;
-		txiclk_ch3         : IN std_logic;
-		fpga_rxrefclk_ch3  : IN std_logic;
-		txdata_ch3         : IN std_logic_vector(7 downto 0);
-		tx_k_ch3           : IN std_logic;
-		tx_force_disp_ch3  : IN std_logic;
-		tx_disp_sel_ch3    : IN std_logic;
-		tx_pwrup_ch3_c     : IN std_logic;
-		tx_div2_mode_ch3_c : IN std_logic;
-		sci_wrdata         : IN std_logic_vector(7 downto 0);
-		sci_addr           : IN std_logic_vector(5 downto 0);
-		sci_sel_quad       : IN std_logic;
-		sci_rd             : IN std_logic;
-		sci_wrn            : IN std_logic;
-		fpga_txrefclk      : IN std_logic;
-		tx_serdes_rst_c    : IN std_logic;
-		tx_sync_qd_c       : IN std_logic;
-		rst_n              : IN std_logic;
-		serdes_rst_qd_c    : IN std_logic;          
-		hdoutp_ch1         : OUT std_logic;
-		hdoutn_ch1         : OUT std_logic;
-		rx_full_clk_ch1    : OUT std_logic;
-		rx_half_clk_ch1    : OUT std_logic;
-		tx_full_clk_ch1    : OUT std_logic;
-		tx_half_clk_ch1    : OUT std_logic;
-		rxdata_ch1         : OUT std_logic_vector(15 downto 0);
-		rx_k_ch1           : OUT std_logic_vector(1 downto 0);
-		rx_disp_err_ch1    : OUT std_logic_vector(1 downto 0);
-		rx_cv_err_ch1      : OUT std_logic_vector(1 downto 0);
-		rx_los_low_ch1_s   : OUT std_logic;
-		lsm_status_ch1_s   : OUT std_logic;
-		rx_cdr_lol_ch1_s   : OUT std_logic;
-		hdoutp_ch3         : OUT std_logic;
-		hdoutn_ch3         : OUT std_logic;
-		tx_full_clk_ch3    : OUT std_logic;
-		tx_half_clk_ch3    : OUT std_logic;
-		sci_rddata         : OUT std_logic_vector(7 downto 0);
-		tx_pll_lol_qd_s    : OUT std_logic;
-		refclk2fpga        : OUT std_logic
-			);
-	end component;
-  
--- Peter Schakel 02-12-14
-component sfp_1_2sync_3_200_int is
- port (
-------------------
--- CH0 --
--- CH1 --
-    hdinp_ch1, hdinn_ch1    :   in std_logic;
-    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
-    sci_sel_ch1    :   in std_logic;
-    rxiclk_ch1    :   in std_logic;
-    txiclk_ch1    :   in std_logic;
-    rx_full_clk_ch1   :   out std_logic;
-    rx_half_clk_ch1   :   out std_logic;
-    tx_full_clk_ch1   :   out std_logic;
-    tx_half_clk_ch1   :   out std_logic;
-    fpga_rxrefclk_ch1    :   in std_logic;
-    txdata_ch1    :   in std_logic_vector (15 downto 0);
-    tx_k_ch1    :   in std_logic_vector (1 downto 0);
-    tx_force_disp_ch1    :   in std_logic_vector (1 downto 0);
-    tx_disp_sel_ch1    :   in std_logic_vector (1 downto 0);
-    rxdata_ch1   :   out std_logic_vector (15 downto 0);
-    rx_k_ch1   :   out std_logic_vector (1 downto 0);
-    rx_disp_err_ch1   :   out std_logic_vector (1 downto 0);
-    rx_cv_err_ch1   :   out std_logic_vector (1 downto 0);
-    rx_serdes_rst_ch1_c    :   in std_logic;
-    sb_felb_ch1_c    :   in std_logic;
-    sb_felb_rst_ch1_c    :   in std_logic;
-    tx_pcs_rst_ch1_c    :   in std_logic;
-    tx_pwrup_ch1_c    :   in std_logic;
-    rx_pcs_rst_ch1_c    :   in std_logic;
-    rx_pwrup_ch1_c    :   in std_logic;
-    rx_los_low_ch1_s   :   out std_logic;
-    lsm_status_ch1_s   :   out std_logic;
-    rx_cdr_lol_ch1_s   :   out std_logic;
-    tx_div2_mode_ch1_c   : in std_logic;
-    rx_div2_mode_ch1_c   : in std_logic;
--- CH2 --
-    hdinp_ch2, hdinn_ch2    :   in std_logic;
-    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
-    sci_sel_ch2    :   in std_logic;
-    rxiclk_ch2    :   in std_logic;
-    txiclk_ch2    :   in std_logic;
-    rx_full_clk_ch2   :   out std_logic;
-    rx_half_clk_ch2   :   out std_logic;
-    tx_full_clk_ch2   :   out std_logic;
-    tx_half_clk_ch2   :   out std_logic;
-    fpga_rxrefclk_ch2    :   in std_logic;
-    txdata_ch2    :   in std_logic_vector (7 downto 0);
-    tx_k_ch2    :   in std_logic;
-    tx_force_disp_ch2    :   in std_logic;
-    tx_disp_sel_ch2    :   in std_logic;
-    rxdata_ch2   :   out std_logic_vector (7 downto 0);
-    rx_k_ch2   :   out std_logic;
-    rx_disp_err_ch2   :   out std_logic;
-    rx_cv_err_ch2   :   out std_logic;
-    rx_serdes_rst_ch2_c    :   in std_logic;
-    sb_felb_ch2_c    :   in std_logic;
-    sb_felb_rst_ch2_c    :   in std_logic;
-    tx_pcs_rst_ch2_c    :   in std_logic;
-    tx_pwrup_ch2_c    :   in std_logic;
-    rx_pcs_rst_ch2_c    :   in std_logic;
-    rx_pwrup_ch2_c    :   in std_logic;
-    rx_los_low_ch2_s   :   out std_logic;
-    lsm_status_ch2_s   :   out std_logic;
-    rx_cdr_lol_ch2_s   :   out std_logic;
-    tx_div2_mode_ch2_c   : in std_logic;
-    rx_div2_mode_ch2_c   : in std_logic;
--- CH3 --
-    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
-    sci_sel_ch3    :   in std_logic;
-    txiclk_ch3    :   in std_logic;
-    tx_full_clk_ch3   :   out std_logic;
-    tx_half_clk_ch3   :   out std_logic;
-    txdata_ch3    :   in std_logic_vector (7 downto 0);
-    tx_k_ch3    :   in std_logic;
-    tx_force_disp_ch3    :   in std_logic;
-    tx_disp_sel_ch3    :   in std_logic;
-    tx_pcs_rst_ch3_c    :   in std_logic;
-    tx_pwrup_ch3_c    :   in std_logic;
-    tx_div2_mode_ch3_c   : in std_logic;
----- Miscillaneous ports
-    sci_wrdata    :   in std_logic_vector (7 downto 0);
-    sci_addr    :   in std_logic_vector (5 downto 0);
-    sci_rddata   :   out std_logic_vector (7 downto 0);
-    sci_sel_quad    :   in std_logic;
-    sci_rd    :   in std_logic;
-    sci_wrn    :   in std_logic;
-    fpga_txrefclk  :   in std_logic;
-    tx_serdes_rst_c    :   in std_logic;
-    tx_pll_lol_qd_s   :   out std_logic;
-    tx_sync_qd_c    :   in std_logic;
-    rst_qd_c    :   in std_logic;
-    serdes_rst_qd_c    :   in std_logic);
-
-end component;
-
- 
-  
-  signal refck2core             : std_logic;
---  signal clock                  : std_logic;
-  --reset signals
-  signal ffc_quad_rst           : std_logic;
-  signal ffc_lane_tx_rst        : std_logic;
-  signal ffc_lane_rx_rst        : std_logic;
-  --serdes connections
-  signal tx_data                : std_logic_vector(15 downto 0);
-  signal tx_k                   : std_logic_vector(1 downto 0);
-  signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals
-  signal rx_k                   : std_logic_vector(1 downto 0);  -- delayed signals
-  signal comb_rx_data           : std_logic_vector(15 downto 0); -- original signals from SFP
-  signal comb_rx_k              : std_logic_vector(1 downto 0);  -- original signals from SFP
-  signal link_ok                : std_logic_vector(1 downto 0); -- OJK 02-dec-2013: Changed width from 1 bit to 2 bits
-  signal link_error             : std_logic_vector(10 downto 0);-- OJK 02-dec-2013: Changed width from 10 bits to 11 bits
-  signal ff_txhalfclk           : std_logic;
-  signal ff_rxhalfclk			      : std_logic;
-  signal ff_rxfullclk           : std_logic;
-  --rx fifo signals
-  signal fifo_rx_rd_en          : std_logic;
-  signal fifo_rx_wr_en          : std_logic;
-  signal fifo_rx_reset          : std_logic;
-  signal fifo_rx_din            : std_logic_vector(17 downto 0);
-  signal fifo_rx_dout           : std_logic_vector(17 downto 0);
-  signal fifo_rx_full           : std_logic;
-  signal fifo_rx_empty          : std_logic;
-  --tx fifo signals
-  signal fifo_tx_rd_en          : std_logic;
-  signal fifo_tx_wr_en          : std_logic;
-  signal fifo_tx_reset          : std_logic;
-  signal fifo_tx_din            : std_logic_vector(17 downto 0);
-  signal fifo_tx_dout           : std_logic_vector(17 downto 0);
-  signal fifo_tx_full           : std_logic;
-  signal fifo_tx_empty          : std_logic;
-  signal fifo_tx_almost_full    : std_logic;
-  --rx path
-  signal rx_counter             : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-  signal buf_med_dataready_out  : std_logic;
-  signal buf_med_data_out       : std_logic_vector(c_DATA_WIDTH-1 downto 0);
-  signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
-  signal last_rx                : std_logic_vector(8 downto 0);
-  signal last_fifo_rx_empty     : std_logic;
-  --tx path
-  signal last_fifo_tx_empty     : std_logic;
-  --link status
-  signal rx_k_q                 : std_logic_vector(1 downto 0);
-
-  signal quad_rst               : std_logic;
-  signal lane_rst               : std_logic;
-  signal tx_allow               : std_logic;
-  signal rx_allow               : std_logic;
-  signal tx_allow_qtx           : std_logic;
-
-  signal rx_allow_q             : std_logic; -- clock domain changed signal
-  signal tx_allow_q             : std_logic;
-  signal swap_bytes             : std_logic;
-  signal buf_stat_debug         : std_logic_vector(31 downto 0);
-
-  -- status inputs from SFP
-  signal sfp_prsnt_n            : std_logic; -- synchronized input signals
-  signal sfp_los                : std_logic; -- synchronized input signals
-
-  signal buf_STAT_OP            : std_logic_vector(15 downto 0);
-
-  signal led_counter            : unsigned(16 downto 0);
-  signal rx_led                 : std_logic;
-  signal tx_led                 : std_logic;
-
-
-  signal tx_correct             : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
-  signal first_idle             : std_logic; -- tag the first IDLE2 after data
-
-  signal reset_word_cnt    : unsigned(4 downto 0);
-  signal make_trbnet_reset : std_logic;
-  signal make_trbnet_reset_q : std_logic;
-  signal send_reset_words  : std_logic;
-  signal send_reset_words_q : std_logic;
-  signal send_reset_in      : std_logic;
-  signal send_reset_in_qtx  : std_logic;
-  signal reset_i                : std_logic;
-  signal reset_i_rx             : std_logic;
-  signal pwr_up                 : std_logic;
-  signal clear_n   : std_logic;
-
-  signal clk_sys : std_logic;
-  signal clk_tx  : std_logic;
-  signal clk_rx  : std_logic;
-  signal clk_rxref : std_logic;
-  signal clk_txref : std_logic;
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state         : sci_ctrl;
-  signal sci_ch_i        : std_logic_vector(3 downto 0);
-  signal sci_qd_i        : std_logic;
-  signal sci_reg_i       : std_logic;
-  signal sci_addr_i      : std_logic_vector(8 downto 0);
-  signal sci_data_in_i   : std_logic_vector(7 downto 0);
-  signal sci_data_out_i  : std_logic_vector(7 downto 0);
-  signal sci_read_i      : std_logic;
-  signal sci_write_i     : std_logic;
---  signal sci_write_shift_i : std_logic_vector(2 downto 0);
---  signal sci_read_shift_i  : std_logic_vector(2 downto 0);  
-  
-  --OJK 13-dec-2013
-  signal cnt             : integer range 0 to 10000;
-  signal tx_pll_lol_qd_i : std_logic;
-  -- Peter Schakel 3-dec-2014
- 	
-  signal sci_timer            : unsigned(12 downto 0) := (others => '0');
-  signal reset_n              : std_logic;
-  signal trb_rx_serdes_rst    : std_logic;
-  signal trb_rx_cdr_lol       : std_logic;
-  signal trb_rx_los_low       : std_logic;
-  signal trb_rx_pcs_rst       : std_logic;
-  signal trb_tx_pcs_rst       : std_logic;
-  signal rst_qd               : std_logic;
-  signal link_OK_S            : std_logic;
-  signal trb_tx_fsm_state     : std_logic_vector(3 downto 0);
-  signal trb_rx_fsm_state     : std_logic_vector(3 downto 0);
-  
-  signal sync_clk_rx_full     : std_logic;
-  signal sync_clk_rx_half     : std_logic;
-  signal sync_clk_tx_full     : std_logic;
-  signal sync_clk_tx_half     : std_logic;
-  signal sync_tx_k            : std_logic;
-  signal sync_tx_data         : std_logic_vector(7 downto 0);
-
-  signal syncfifo_din         : std_logic_vector(17 downto 0);
-  signal syncfifo_dout        : std_logic_vector(17 downto 0);
-	  
-  signal sync_rx_k            : std_logic;
-  signal sync_rx_data         : std_logic_vector(7 downto 0);
-  signal sync_rx_serdes_rst   : std_logic;
-  signal sync_rx_cdr_lol      : std_logic;
-  signal sync_tx_pcs_rst      : std_logic;
-  signal sync_rx_pcs_rst      : std_logic;
-  signal sync_rx_los_low      : std_logic;
-  signal sync_lsm_status      : std_logic;
-  signal SD_tx_pcs_rst        : std_logic;
-  signal DLM_fifo_rd_en       : std_logic;
-  signal DLM_fifo_empty       : std_logic;
-  signal DLM_fifo_reading     : std_logic := '0';  
-  signal SODA_dlm_word_S      : std_logic_vector(7 downto 0);
-  signal DLM_received_S       : std_logic;
-  signal sync_wa_position_rx  : std_logic_vector(15 downto 0) := x"FFFF";
-  signal wa_position          : std_logic_vector(15 downto 0) := x"FFFF";
-  signal sync_rx_fsm_state    : std_logic_vector(3 downto 0);
-  signal sync_tx_fsm_state    : std_logic_vector(3 downto 0);
-  signal CH3_tx_fsm_state     : std_logic_vector(3 downto 0);
-
-  signal CLKdiv100_S          : std_logic;
-  signal sync_clk_rx_fulldiv100_S     : std_logic;
-			
-  attribute syn_keep : boolean;
-  attribute syn_preserve : boolean;
-  attribute syn_keep of led_counter : signal is true;
-  attribute syn_keep of send_reset_in : signal is true;
-  attribute syn_keep of reset_i : signal is true;
-  attribute syn_preserve of reset_i : signal is true;
-
-begin
-
---------------------------------------------------------------------------
--- Select proper clock configuration
---------------------------------------------------------------------------
-  clk_sys <= SYSCLK;
-  clk_tx  <= SYSCLK;
-  clk_rx  <= ff_rxhalfclk;
-  clk_rxref <= CLK;
-  clk_txref <= CLK;
-
-
-
-
---------------------------------------------------------------------------
--- Internal Lane Resets
---------------------------------------------------------------------------
-  clear_n <= not clear;
-
-
-  PROC_RESET : process(clk_sys)
-    begin
-      if rising_edge(clk_sys) then
-        reset_i <= RESET;
-        send_reset_in <= ctrl_op(15);
-        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
-      end if;
-    end process;
-
---------------------------------------------------------------------------
--- Synchronizer stages
---------------------------------------------------------------------------
-
--- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
-THE_SFP_STATUS_SYNC: signal_sync
-  generic map(
-    DEPTH => 3,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => sd_prsnt_n_in,
-    D_IN(1)  => sd_los_in,
-    CLK0     => clk_sys,
-    CLK1     => clk_sys,
-    D_OUT(0) => sfp_prsnt_n,
-    D_OUT(1) => sfp_los
-    );
-
-
-THE_RX_K_SYNC: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 4
-    )
-  port map(
-    RESET             => reset_i,
-    D_IN(1 downto 0)  => comb_rx_k,
-    D_IN(2)           => send_reset_words,
-    D_IN(3)           => make_trbnet_reset,
-    CLK0              => clk_rx, -- CHANGED
-    CLK1              => clk_sys,
-    D_OUT(1 downto 0) => rx_k_q,
-    D_OUT(2)          => send_reset_words_q,
-    D_OUT(3)          => make_trbnet_reset_q
-    );
-
-THE_RX_DATA_DELAY: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 16
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN     => comb_rx_data,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT    => rx_data
-    );
-
-THE_RX_K_DELAY: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN     => comb_rx_k,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT    => rx_k
-    );
-
-THE_RX_RESET: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 1
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => reset_i,
-    CLK0     => clk_rx,
-    CLK1     => clk_rx,
-    D_OUT(0) => reset_i_rx
-    );
-
--- Delay for ALLOW signals
-THE_RX_ALLOW_SYNC: signal_sync
-  generic map(
-    DEPTH => 2,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => reset_i,
-    D_IN(0)  => rx_allow,
-    D_IN(1)  => tx_allow,
-    CLK0     => clk_sys,
-    CLK1     => clk_sys,
-    D_OUT(0) => rx_allow_q,
-    D_OUT(1) => tx_allow_q
-    );
-
-THE_TX_SYNC: signal_sync
-  generic map(
-    DEPTH => 1,
-    WIDTH => 2
-    )
-  port map(
-    RESET    => '0',
-    D_IN(0)  => send_reset_in,
-    D_IN(1)  => tx_allow,
-    CLK0     => clk_tx,
-    CLK1     => clk_tx,
-    D_OUT(0) => send_reset_in_qtx,
-    D_OUT(1) => tx_allow_qtx
-    );
-
-
---------------------------------------------------------------------------
--- Main control state machine, startup control for SFP
---------------------------------------------------------------------------
-
-THE_SFP_LSM: trb_net16_lsm_sfp
-    generic map (
-      HIGHSPEED_STARTUP => c_YES
-      )
-    port map(
-      SYSCLK            => clk_sys,
-      RESET             => reset_i,
-      CLEAR             => clear,
-      SFP_MISSING_IN    => sfp_prsnt_n,
-      SFP_LOS_IN        => sfp_los,
-      SD_LINK_OK_IN     => link_OK_S, --//  ?? link_ok(0),
-      SD_LOS_IN         => link_error(8),
-      SD_TXCLK_BAD_IN   => link_error(5),
-      SD_RXCLK_BAD_IN   => link_error(4),
-      SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
-      SD_ALIGNMENT_IN	=> rx_k_q,
-      SD_CV_IN          => link_error(7 downto 6),
-      FULL_RESET_OUT    => quad_rst,
-      LANE_RESET_OUT    => lane_rst,
-      TX_ALLOW_OUT      => tx_allow,
-      RX_ALLOW_OUT      => rx_allow,
-      SWAP_BYTES_OUT    => swap_bytes,
-      STAT_OP           => buf_stat_op,
-      CTRL_OP           => ctrl_op,
-      STAT_DEBUG        => buf_stat_debug
-      );
-
-sd_txdis_out <= quad_rst or reset_i;
-
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-
-ffc_quad_rst         <= quad_rst;
-ffc_lane_tx_rst      <= lane_rst;
-
-
-ffc_lane_rx_rst      <= lane_rst;
-
--- SerDes clock output to FPGA fabric
-REFCLK2CORE_OUT <= ff_rxhalfclk;
-CLK_RX_HALF_OUT <= ff_rxhalfclk;
-CLK_RX_FULL_OUT <= ff_rxfullclk;
-
-THE_SERDES: sfp_1_2sync_3_200_int port map(
-------------------
--- CH0 --
--- CH1 --
-      hdinp_ch1          => sd_rxd_p_in,                
-      hdinn_ch1          => sd_rxd_n_in,                
-      hdoutp_ch1         => sd_txd_p_out,              
-      hdoutn_ch1         => sd_txd_n_out,              
-
-      sci_sel_ch1        => sci_ch_i(1),
-      rxiclk_ch1         => clk_rx,                
-      txiclk_ch1         => clk_tx,                
-      rx_full_clk_ch1    => ff_rxfullclk,          
-      rx_half_clk_ch1    => ff_rxhalfclk,          
-      tx_full_clk_ch1    => open,                  
-      tx_half_clk_ch1    => ff_txhalfclk,          
-      fpga_rxrefclk_ch1  => clk_rxref,             
-      txdata_ch1         => tx_data,               
-      tx_k_ch1           => tx_k,                  
-      tx_force_disp_ch1  => tx_correct,            
-      tx_disp_sel_ch1    => "00",                  
-      rxdata_ch1         => comb_rx_data,          
-      rx_k_ch1           => comb_rx_k,             
-      rx_disp_err_ch1    => open,            
-      rx_cv_err_ch1      => link_error(7 downto 6),
-      rx_serdes_rst_ch1_c => trb_rx_serdes_rst,
-      sb_felb_ch1_c      => '0',                   
-      sb_felb_rst_ch1_c  => '0',                
-      tx_pcs_rst_ch1_c   => trb_tx_pcs_rst,
-      tx_pwrup_ch1_c     => '1',                   
-      rx_pcs_rst_ch1_c   => trb_rx_pcs_rst,
-      rx_pwrup_ch1_c     => '1',                   
-      rx_los_low_ch1_s   => trb_rx_los_low, -- link_error(8),         
-      lsm_status_ch1_s   => link_ok(0),            
-      rx_cdr_lol_ch1_s   => trb_rx_cdr_lol, -- link_error(4),         
-      tx_div2_mode_ch1_c => '0',                   
-      rx_div2_mode_ch1_c => '0',
-
--- CH2 --
-    hdinp_ch2            => SODA_RXD_P_IN,
-    hdinn_ch2            => SODA_RXD_N_IN,
-    hdoutp_ch2           => SODA_TXD_P_OUT,
-    hdoutn_ch2           => SODA_TXD_N_OUT,
-    sci_sel_ch2          => sci_ch_i(2),
-    rxiclk_ch2           => sync_clk_rx_full, -- ?? CLK,
-    txiclk_ch2           => sync_clk_tx_full, -- ??CLK, --????? clk_txref
-    rx_full_clk_ch2      => sync_clk_rx_full,
-    rx_half_clk_ch2      => sync_clk_rx_half,
-    tx_full_clk_ch2      => sync_clk_tx_full,
-    tx_half_clk_ch2      => sync_clk_tx_half,
-    fpga_rxrefclk_ch2    => CLK,
-    txdata_ch2           => sync_tx_data,
-    tx_k_ch2             => sync_tx_k,
-    tx_force_disp_ch2    => '0',
-    tx_disp_sel_ch2      => '0',
-    rxdata_ch2           => sync_rx_data,
-    rx_k_ch2             => sync_rx_k,
-    rx_disp_err_ch2      => open,
-    rx_cv_err_ch2        => open,
-    rx_serdes_rst_ch2_c  => sync_rx_serdes_rst,
-    sb_felb_ch2_c        => '0',
-    sb_felb_rst_ch2_c    => '0',
-    tx_pcs_rst_ch2_c     => sync_tx_pcs_rst,
-    tx_pwrup_ch2_c       => '1',
-    rx_pcs_rst_ch2_c     => sync_rx_pcs_rst,
-    rx_pwrup_ch2_c       => '1',
-    rx_los_low_ch2_s     => sync_rx_los_low,
-    lsm_status_ch2_s     => sync_lsm_status,
-    rx_cdr_lol_ch2_s     => sync_rx_cdr_lol,
-    tx_div2_mode_ch2_c   => '0',
-    rx_div2_mode_ch2_c   => '0',
-		
--- CH3 --
-      hdoutp_ch3         => DOUT_TXD_P_OUT,             
-      hdoutn_ch3         => DOUT_TXD_N_OUT,             
-      sci_sel_ch3        => '0', --disable access to channel 3 registers
-      txiclk_ch3         => clk_tx,             
-      tx_full_clk_ch3    => open,                
-      tx_half_clk_ch3    => open,        
---//????      fpga_rxrefclk_ch3  => clk_rxref,      
-      txdata_ch3         => tx_data_ch3,             
-      tx_k_ch3           => tx_k_ch3,
-      tx_force_disp_ch3  => '0',      
-      tx_disp_sel_ch3    => '0',        
-      tx_pcs_rst_ch3_c   => SD_tx_pcs_rst,
-      tx_pwrup_ch3_c     => '1',         
-      tx_div2_mode_ch3_c => '1', 
-
----- Miscillaneous ports
-      sci_wrdata         => sci_data_in_i,
-      sci_addr           => sci_addr_i(5 downto 0),
-      sci_rddata         => sci_data_out_i,
-      sci_sel_quad       => sci_qd_i,
-      sci_rd             => sci_read_i,
-      sci_wrn            => sci_write_i,
-      fpga_txrefclk      => clk_txref,               
-      tx_serdes_rst_c    => CLEAR,          
-      tx_pll_lol_qd_s    => tx_pll_lol_qd_i,          
-      tx_sync_qd_c       => '0',             -- Multiple channel transmit synchronization is not needed?
---//      refclk2fpga        => open,              -- Not needed?
-      rst_qd_c => rst_qd,
---//??      rst_n              => '1',                   
-      serdes_rst_qd_c    => ffc_quad_rst        
-	);
-
-      syncfifo_din(7 downto 0)  <= SODA_DLM_WORD_IN;
-      syncfifo_din(17 downto 8) <= (others => '0');
-	  SODA_dlm_word_S <= syncfifo_dout(7 downto 0);
-sync_DLM_tx: trb_net_fifo_16bit_bram_dualport
-generic map(
-  USE_STATUS_FLAGS => c_NO
-       )
-port map( read_clock_in  => sync_clk_tx_full,
-      write_clock_in     => sync_clk_rx_full, 
-      read_enable_in     => DLM_fifo_rd_en,
-      write_enable_in    => SODA_DLM_IN,
-      fifo_gsr_in        => reset,
-      write_data_in      => syncfifo_din,
-      read_data_out      => syncfifo_dout,
-      full_out           => open,
-      empty_out          => DLM_fifo_empty
-    );
-
-process(sync_clk_rx_full)
-begin
-  if rising_edge(sync_clk_rx_full) then
-	SODA_DLM_OUT <= '0';
-	if DLM_received_S='1' then
-		DLM_received_S <= '0';
-		SODA_DLM_OUT <= '1';
-		SODA_DLM_WORD_OUT <= sync_rx_data;
-	elsif (sync_rx_data=x"DC") and (sync_rx_k='1') then
-		DLM_received_S <= '1';
-	end if;
-  end if;
-end process;  
-
-process(sync_clk_tx_full)
-begin
-  if rising_edge(sync_clk_tx_full) then
-	if DLM_fifo_rd_en='1' then
-		DLM_fifo_rd_en <= '0';
-		sync_tx_data <= SODA_dlm_word_S;
-		sync_tx_k <= '0';
-	elsif (DLM_fifo_empty='0') and (DLM_fifo_reading='1') then
-		DLM_fifo_rd_en <= '1';
-		sync_tx_data <= x"DC";
-		sync_tx_k <= '1';
-	elsif DLM_fifo_empty='0' then
-		DLM_fifo_reading <= '1';
-		DLM_fifo_rd_en <= '0';
-		sync_tx_data <= x"BC"; -- idle
-		sync_tx_k <= '1';		
-	else
-		DLM_fifo_reading <= '0';
-		DLM_fifo_rd_en <= '0';
-		sync_tx_data <= x"BC"; -- idle
-		sync_tx_k <= '1';
-	end if;
-  end if;
-end process;  
-SODA_CLOCK_OUT <= sync_clk_rx_full;
-
-
-link_error(8) <= trb_rx_los_low; -- loss of signal
-link_error(4) <= '1' when (trb_rx_cdr_lol='1') or (link_OK_S='0') else '0'; -- loss of lock 
-link_error(5) <= tx_pll_lol_qd_i; -- transmit loss of lock
-
-reset_n <= '0' when (RESET='1') or (CLEAR='1')  else '1';
-
--------------------------------------------------      
--- Reset FSM & Link states
-------------------------------------------------- 
-THE_RX_FSM1: rx_reset_fsm
-  port map(
-    RST_N               => reset_n,
-    RX_REFCLK           => CLK,
-    TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
-    RX_SERDES_RST_CH_C  => trb_rx_serdes_rst,
-    RX_CDR_LOL_CH_S     => trb_rx_cdr_lol,
-    RX_LOS_LOW_CH_S     => trb_rx_los_low,
-    RX_PCS_RST_CH_C     => trb_rx_pcs_rst,
-    WA_POSITION         => "0000",
-    STATE_OUT           => trb_rx_fsm_state
-    );
-
-link_OK_S <= '1' when (link_ok(0)='1') and (trb_rx_fsm_state = x"6") else '0';
-THE_TX_FSM1: tx_reset_fsm
-  port map(
-    RST_N           => reset_n,
-    TX_REFCLK       => CLK,
-    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-    RST_QD_C        => rst_qd,
-    TX_PCS_RST_CH_C => trb_tx_pcs_rst,
-    STATE_OUT       => trb_tx_fsm_state
-    );
-
-THE_RX_FSM2: rx_reset_fsm
-  port map(
-    RST_N               => reset_n,
-    RX_REFCLK           => sync_clk_rx_full, --??CLK,
-    TX_PLL_LOL_QD_S     => tx_pll_lol_qd_i,
-    RX_SERDES_RST_CH_C  => sync_rx_serdes_rst,
-    RX_CDR_LOL_CH_S     => sync_rx_cdr_lol,
-    RX_LOS_LOW_CH_S     => sync_rx_los_low,
-    RX_PCS_RST_CH_C     => sync_rx_pcs_rst,
-    WA_POSITION         => sync_wa_position_rx(11 downto 8),
-    STATE_OUT           => sync_rx_fsm_state
-    );
-SYNC_WA_POSITION : process(sync_clk_rx_full) --??CLK)
-begin
-  if rising_edge(sync_clk_rx_full) then
-    sync_wa_position_rx <= wa_position;
-  end if;
-end process;
-    
-THE_TX_FSM2: tx_reset_fsm
-  port map(
-    RST_N           => reset_n,
-    TX_REFCLK       => CLK,
-    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-    RST_QD_C        => open, --??
-    TX_PCS_RST_CH_C => sync_tx_pcs_rst,
-    STATE_OUT       => sync_tx_fsm_state
-    );
-	
-THE_TX_FSM3 : tx_reset_fsm
-  port map(
-    RST_N           => reset_n,
-    TX_REFCLK       => CLK,
-    TX_PLL_LOL_QD_S => tx_pll_lol_qd_i,
-    RST_QD_C        => open, --??
-    TX_PCS_RST_CH_C => SD_tx_pcs_rst,
-    STATE_OUT       => CH3_tx_fsm_state
-    );
-TX_READY_CH3 <= '1' when (CH3_tx_fsm_state=x"5") and (tx_pll_lol_qd_i='0') else '0';
-	
-	
--------------------------------------------------------------------------
--- RX Fifo & Data output
--------------------------------------------------------------------------
-THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
-generic map(
-  USE_STATUS_FLAGS => c_NO
-       )
-port map( read_clock_in  => clk_sys,
-      write_clock_in     => clk_rx, -- CHANGED
-      read_enable_in     => fifo_rx_rd_en,
-      write_enable_in    => fifo_rx_wr_en,
-      fifo_gsr_in        => fifo_rx_reset,
-      write_data_in      => fifo_rx_din,
-      read_data_out      => fifo_rx_dout,
-      full_out           => fifo_rx_full,
-      empty_out          => fifo_rx_empty
-    );
-
-fifo_rx_reset <= reset_i or not rx_allow_q;
-fifo_rx_rd_en <= not fifo_rx_empty;
-
--- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
-THE_BYTE_SWAP_PROC: process(clk_rx)
-  begin
-    if rising_edge(clk_rx) then
-		last_rx <= rx_k(1) & rx_data(15 downto 8);
-		if( swap_bytes = '0' ) then
-		  fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
-		  fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok(0);
-		else
-		  fifo_rx_din   <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
-		  fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok(0);
-		end if;
-	end if;
-  end process THE_BYTE_SWAP_PROC;
-
-buf_med_data_out          <= fifo_rx_dout(15 downto 0);
-buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
-buf_med_packet_num_out    <= rx_counter;
-med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
-
-
-THE_CNT_RESET_PROC : process(clk_rx)
-  begin
-    if rising_edge(clk_rx) then
-		if reset_i_rx = '1' then
-		  send_reset_words  <= '0';
-		  make_trbnet_reset <= '0';
-		  reset_word_cnt    <= (others => '0');
-		else
-		  send_reset_words   <= '0';
-		  make_trbnet_reset  <= '0';
-		  if fifo_rx_din = "11" & x"FEFE" then
-			if reset_word_cnt(4) = '0' then
-			  reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
-			else
-			  send_reset_words <= '1';
-			end if;
-		  else
-			reset_word_cnt    <= (others => '0');
-			make_trbnet_reset <= reset_word_cnt(4);
-		  end if;
-		end if;
-	end if;
-  end process;
-
-
-THE_SYNC_PROC: process(clk_rx)
-  begin
-    if rising_edge(clk_rx) then
-		med_dataready_out     <= buf_med_dataready_out;
-		med_data_out          <= buf_med_data_out;
-		med_packet_num_out    <= buf_med_packet_num_out;
-		if reset_i = '1' then
-		  med_dataready_out <= '0';
-		end if;
-	end if;
-  end process;
-
-
---rx packet counter
----------------------
-THE_RX_PACKETS_PROC: process( clk_sys )
-  begin
-    if( rising_edge(clk_sys) ) then
-      last_fifo_rx_empty <= fifo_rx_empty;
-      if reset_i = '1' or rx_allow_q = '0' then
-        rx_counter <= c_H0;
-      else
-        if( buf_med_dataready_out = '1' ) then
-          if( rx_counter = c_max_word_number ) then
-            rx_counter <= (others => '0');
-          else
-            rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
-          end if;
-        end if;
-      end if;
-    end if;
-  end process;
-
---TX Fifo & Data output to Serdes
----------------------
-THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
-  generic map(
-    USE_STATUS_FLAGS => c_NO
-        )
-  port map( read_clock_in => clk_tx,
-        write_clock_in    => clk_sys,
-        read_enable_in    => fifo_tx_rd_en,
-        write_enable_in   => fifo_tx_wr_en,
-        fifo_gsr_in       => fifo_tx_reset,
-        write_data_in     => fifo_tx_din,
-        read_data_out     => fifo_tx_dout,
-        full_out          => fifo_tx_full,
-        empty_out         => fifo_tx_empty,
-        almost_full_out   => fifo_tx_almost_full
-      );
-
-fifo_tx_reset <= reset_i or not tx_allow_q;
-fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
-fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
-fifo_tx_rd_en <= tx_allow_qtx;
-
-
-THE_SERDES_INPUT_PROC: process( clk_tx )
-  begin
-    if( rising_edge(clk_tx) ) then
-      last_fifo_tx_empty <= fifo_tx_empty;
-      first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
-      if send_reset_in = '1' then
-        tx_data <= x"FEFE";
-        tx_k <= "11";
-      elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
-        tx_data <= x"50bc";
-        tx_k <= "01";
-        tx_correct <= first_idle & '0';
-      else
-        tx_data <= fifo_tx_dout(15 downto 0);
-        tx_k <= "00";
-        tx_correct <= "00";
-      end if;
-    end if;
-  end process THE_SERDES_INPUT_PROC;
-
--------------------------------------------------      
--- SCI
--------------------------------------------------      
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process(clk_sys)
-  variable cnt : integer range 0 to 4 := 0;
-begin
-  if( rising_edge(clk_sys) ) then
-	  SCI_ACK <= '0';
-	  case sci_state is
-		when IDLE =>
-		  sci_ch_i        <= x"0";
-		  sci_qd_i        <= '0';
-		  sci_reg_i       <= '0';
-		  sci_read_i      <= '0';
-		  sci_write_i     <= '0';
-		  sci_timer       <= sci_timer + 1;
-		  if SCI_READ = '1' or SCI_WRITE = '1' then
-			sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
-			sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
-			sci_addr_i    <= SCI_ADDR;
-			sci_data_in_i <= SCI_DATA_IN;
-			sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
-			sci_state     <= SCTRL;
-		  elsif sci_timer(sci_timer'left) = '1' then
-			sci_timer     <= (others => '0');
-			sci_state     <= GET_WA;
-		  end if;      
-		when SCTRL =>
-		  if sci_reg_i = '1' then
---//			SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
-			SCI_DATA_OUT  <= (others => '0');
-			SCI_ACK       <= '1';
-			sci_write_i   <= '0';
-			sci_read_i    <= '0';
-			sci_state     <= IDLE;
-		  else
-			sci_state     <= SCTRL_WAIT;
-		  end if;
-		when SCTRL_WAIT   =>
-		  sci_state       <= SCTRL_WAIT2;
-		when SCTRL_WAIT2  =>
-		  sci_state       <= SCTRL_FINISH;
-		when SCTRL_FINISH =>
-		  SCI_DATA_OUT    <= sci_data_out_i;
-		  SCI_ACK         <= '1';
-		  sci_write_i     <= '0';
-		  sci_read_i      <= '0';
-		  sci_state       <= IDLE;
-		
-		when GET_WA =>
-		  if cnt = 4 then
-			cnt           := 0;
-			sci_state     <= IDLE;
-		  else
-			sci_state     <= GET_WA_WAIT;
-			sci_addr_i    <= '0' & x"22";
-			sci_ch_i      <= x"0";
-			sci_ch_i(cnt) <= '1';
-			sci_read_i    <= '1';
-		  end if;
-		when GET_WA_WAIT  =>
-		  sci_state       <= GET_WA_WAIT2;
-		when GET_WA_WAIT2 =>
-		  sci_state       <= GET_WA_FINISH;
-		when GET_WA_FINISH =>
-		  wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
-		  sci_state       <= GET_WA;    
-		  cnt             := cnt + 1;
-	  end case;
-	  
-	  if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
-		SCI_NACK <= '1';
-	  else
-		SCI_NACK <= '0';
-	  end if;
-  end if;
-end process;
-    
-  
-
---Generate LED signals
-----------------------
-process( clk_sys )
-  begin
-    if rising_edge(clk_sys) then
-      led_counter <= led_counter + to_unsigned(1,1);
-
-      if buf_med_dataready_out = '1' then
-        rx_led <= '1';
-      elsif led_counter = 0 then
-        rx_led <= '0';
-      end if;
-
-      if tx_k(0) = '0' then
-        tx_led <= '1';
-      elsif led_counter = 0 then
-        tx_led <= '0';
-      end if;
-
-    end if;
-  end process;
-
-stat_op(15)           <= send_reset_words_q;
-stat_op(14)           <= buf_stat_op(14);
-stat_op(13)           <= make_trbnet_reset_q;
-stat_op(12)           <= '0';
-stat_op(11)           <= tx_led; --tx led
-stat_op(10)           <= rx_led; --rx led
-stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
-
--- Debug output
-stat_debug(15 downto 0)  <= rx_data;
-stat_debug(17 downto 16) <= rx_k;
-stat_debug(19 downto 18) <= (others => '0');
-stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
-stat_debug(24)           <= fifo_rx_rd_en;
-stat_debug(25)           <= fifo_rx_wr_en;
-stat_debug(26)           <= fifo_rx_reset;
-stat_debug(27)           <= fifo_rx_empty;
-stat_debug(28)           <= fifo_rx_full;
-stat_debug(29)           <= last_rx(8);
-stat_debug(30)           <= rx_allow_q;
-stat_debug(41 downto 31) <= (others => '0');
-stat_debug(42)           <= clk_sys;
-stat_debug(43)           <= clk_sys;
-stat_debug(59 downto 44) <= (others => '0');
-stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
-
---stat_debug(3 downto 0)   <= buf_stat_debug(3 downto 0); -- state_bits
---stat_debug(4)            <= buf_stat_debug(4); -- alignme
---stat_debug(5)            <= sfp_prsnt_n;
---stat_debug(6)            <= tx_k(0);
---stat_debug(7)            <= tx_k(1);
---stat_debug(8)            <= rx_k_q(0);
---stat_debug(9)            <= rx_k_q(1);
---stat_debug(18 downto 10) <= link_error;
---stat_debug(19)           <= '0';
---stat_debug(20)           <= link_ok(0);
---stat_debug(38 downto 21) <= fifo_rx_din;
---stat_debug(39)           <= swap_bytes;
---stat_debug(40)           <= buf_stat_debug(7); -- sfp_missing_in
---stat_debug(41)           <= buf_stat_debug(8); -- sfp_los_in
---stat_debug(42)           <= buf_stat_debug(6); -- resync
---stat_debug(59 downto 43) <= (others => '0');
---stat_debug(63 downto 60) <= link_error(3 downto 0);
-
-CLKdiv100_process: process(CLK)
-variable counter_V : integer range 0 to 99 := 0;
-begin
-	if (rising_edge(CLK)) then 
-		if counter_V<49 then -- 99 for 125MHz
-			counter_V := counter_V+1;
-		else
-			counter_V := 0;
-			CLKdiv100_S <= not CLKdiv100_S;
-		end if;
-	end if;
-end process;
-sync_clk_rx_fulldiv100_process: process(sync_clk_rx_full)
-variable counter_V : integer range 0 to 99 := 0;
-begin
-	if (rising_edge(sync_clk_rx_full)) then 
-		if counter_V<49 then -- 99 for 125MHz
-			counter_V := counter_V+1;
-		else
-			counter_V := 0;
-			sync_clk_rx_fulldiv100_S <= not sync_clk_rx_fulldiv100_S;
-		end if;
-	end if;
-end process;
-
-end architecture;
\ No newline at end of file
diff --git a/data_concentrator/sources/xilinx/DC_SODAserdesWrapper.vhd b/data_concentrator/sources/xilinx/DC_SODAserdesWrapper.vhd
new file mode 100644
index 0000000..781717c
--- /dev/null
+++ b/data_concentrator/sources/xilinx/DC_SODAserdesWrapper.vhd
@@ -0,0 +1,612 @@
+----------------------------------------------------------------------------------
+-- Company: KVI/RUG/Groningen University
+-- Engineer: Peter Schakel
+-- Create Date:   05-02-2015
+-- Module Name:   DC_SODAserdesWrapper
+-- Description: GTP/GTX tranceiver for PANDA Front End Electronics on Kintex7 with clock synchronization
+-- Modifications:
+--   05-02-2015   Originally FEE_gtxWrapper_Virtex6
+--   05-02-2015   Originally FEE_gtxWrapper_Kintex7
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+library work;
+use work.panda_package.all;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- DC_SODAserdesWrapper
+-- GTP/GTX tranceiver for PANDA Front End Electronics and Multiplexer with clock synchronization on a Virtex5.
+--
+-- Receiver makes recovered synchronous clock on incomming serial data (SODA). 
+-- Data is 16-bits, synchronous to recovered clock.
+-- Transmitter sends 16-bits data.
+--
+-- Only one channel of the dual GTP or GTX is used.
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     refClk : Reference clock for GTP/GTX, frequency must match expected SODA frequency 
+--     refClk_P : Reference clock for GTP/GTX in case of differential input pins, frequency must match expected SODA frequency 
+--     refClk_N : Reference clock for GTP/GTX in case of differential input pins, frequency must match expected SODA frequency 
+--     sysClk : stable clock (80MHz)
+--     asyncclk : clock for synchronous resetting
+--     gtpReset : reset GTP/GTX
+--     disable_GTX_reset : disable ressetting temporarely
+--     txData : 16-bits input data to transmit
+--     txCharIsK : data to transmit are K-characters
+--     rxP,rxN : differential transmit inputs from the GTP/GTX
+-- 
+-- Outputs:
+--     txP,txN : differential transmit outputs of the GTP/GTX
+--     txUsrClk : clock for transmit data
+--     txLocked :  transmitter locked
+--     rxData : 16-bits received data
+--     rxCharIsK : received 16-bits data (2 bytes) are K-characters
+--     rxNotInTable : receiver data not valid
+--     rxUsrClk : Recovered synchronous clock
+--     rxLocked : receiver locked to incoming data
+--     GT0_QPLLOUTCLK_OUT : QPLL reference clock, needed for Xilinx
+--     GT0_QPLLOUTREFCLK_OUT : QPLL reference clock, needed for Xilinx
+--     resetDone : resetting ready
+-- 
+-- Components:
+--     GTXVIRTEX5FEE : Xilinx module for GTP or GTX, generated with the IP core generator with a few adjustments
+--     FEE_rxBitLock : Module for checking and resetting the GTP/GTX to lock the receiver clock at the right phase
+--     Clock_62M5_doubler : Clock doubler with PLL
+--
+----------------------------------------------------------------------------------
+
+entity DC_SODAserdesWrapper is
+	port (
+		refClk                : in  std_logic;	
+		refClk_P              : in  std_logic;	
+		refClk_N              : in  std_logic;	
+		sysClk                : in  std_logic;	
+		asyncclk              : in  std_logic;
+		gtpReset              : in  std_logic;
+		disable_GTX_reset     : in  std_logic;
+		
+		txData                : in  std_logic_vector (7 downto 0);
+		txCharIsK             : in  std_logic;
+		txP                   : out  std_logic;
+		txN                   : out  std_logic;
+		txUsrClk              : out  std_logic;
+		txLocked              : out  std_logic;
+		
+		rxData                : out  std_logic_vector (7 downto 0);
+		rxCharIsK             : out  std_logic;
+		rxNotInTable          : out  std_logic;
+		rxP                   : in  std_logic;
+		rxN                   : in  std_logic;
+		rxUsrClk              : out std_logic;
+		rxUsrClkdiv2          : out std_logic;
+		rxLocked              : out  std_logic;
+		
+		GT0_QPLLOUTCLK_OUT    : out std_logic := '0';
+		GT0_QPLLOUTREFCLK_OUT : out std_logic := '0';
+		resetDone             : out  std_logic
+	);
+end DC_SODAserdesWrapper;
+
+architecture Behavioral of DC_SODAserdesWrapper is
+
+component GTX_SODAinput_support
+generic
+(
+    -- Simulation attributes
+    EXAMPLE_SIM_GTRESET_SPEEDUP    : string    := "FALSE";    -- Set to TRUE to speed up sim reset
+    STABLE_CLOCK_PERIOD            : integer   := 10 
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q3_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_OUT                    : out  std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_TXUSRCLKX2_OUT                      : out  std_logic; --// Modified
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+        --GT0  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+   
+
+    --____________________________COMMON PORTS________________________________
+		GT0_QPLLOUTCLK_OUT    : out std_logic := '0';
+		GT0_QPLLOUTREFCLK_OUT : out std_logic := '0';
+        sysclk_in : in std_logic;
+	   q2_clk1_gtrefclk : in std_logic;  --//modification
+	   q3_clk0_gtrefclk : in std_logic  --//modification
+);
+end component;
+
+
+component clock100to200 is
+	port
+	(
+		clk_in1                 : in std_logic;
+		clk_out1                : out std_logic;
+		clk_out2                : out std_logic;
+		reset                   : in std_logic;
+		locked                  : out std_logic
+	);
+end component;
+
+component DC_rxBitLock is
+	port (
+		clk                     : in  std_logic;
+		reset                   : in  std_logic;
+		resetDone               : in  std_logic;
+		lossOfSync              : in  std_logic;
+		rxPllLocked             : in  std_logic; 
+		rxReset                 : out  std_logic;
+		fsmStatus               : out  std_logic_vector (1 downto 0)
+	);
+end component;
+
+component DC_data8to16 is
+	port ( 
+		clock_in                : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		kchar_in                : in std_logic;
+		clock_out               : in std_logic;
+		data_out                : out std_logic_vector(15 downto 0);
+		kchar_out               : out std_logic_vector(1 downto 0)
+	);
+end component;
+
+component DC_data16to8 is
+	port ( 
+		clock_in                : in std_logic;
+        data_in                 : in std_logic_vector(15 downto 0);
+        kchar_in                : in std_logic_vector(1 downto 0);
+        notintable_in           : in std_logic_vector(1 downto 0);
+        clock_out               : out std_logic;
+        data_out                : out std_logic_vector(7 downto 0);
+        kchar_out               : out std_logic;
+        notintable_out          : out std_logic
+	);
+end component;
+
+component DC_posedge_to_pulse is
+	port (
+		clock_in                : in  std_logic;
+		clock_out               : in  std_logic;
+		en_clk                  : in  std_logic;
+		signal_in               : in  std_logic;
+		pulse                   : out std_logic
+	);
+end component;
+
+component sync_bit is
+	port (
+		clock       : in  std_logic;
+		data_in     : in  std_logic;
+		data_out    : out std_logic
+	);
+end component;
+
+signal gtpReset_S          : std_logic;
+signal txReset_S           : std_logic;
+signal txResetdone_S       : std_logic;
+signal txUsrClkx2_S        : std_logic; -- tx clock at double tx speed
+
+signal gtx0_txresetdone_r  : std_logic;
+signal gtx0_txresetdone_r2 : std_logic;
+signal txLocked_S          : std_logic;
+signal txOutClk_S          : std_logic :='0';
+signal txUsrClk_buf_S      : std_logic :='0';
+signal txData16_S          : std_logic_vector(15 downto 0);
+signal txCharIsK16_S       : std_logic_vector(1 downto 0);
+signal txmmcm_lock_S       : std_logic;
+signal txmmcm_reset_S      : std_logic;
+
+
+signal rxRecClk_S          : std_logic :='0';
+signal rxReset_S           : std_logic :='0';
+signal rxData_S            : std_logic_vector(7 downto 0);
+signal rxCharIsK_S         : std_logic;
+signal rxNotInTable_S      : std_logic;
+signal rxData16_S          : std_logic_vector(15 downto 0);
+signal rxCharIsK16_S       : std_logic_vector(1 downto 0);
+signal rxNotInTable16_S    : std_logic_vector(1 downto 0);
+signal rxDispError16_S     : std_logic_vector(1 downto 0);
+signal rxLocked0_S         : std_logic;
+signal rxLocked1_S         : std_logic;
+signal rxLocked2_S         : std_logic;
+signal rxResetBitLock_S    : std_logic :='0';
+signal sync_rxResetBitLock_S : std_logic :='0';
+signal prev_rxResetBitLock_S : std_logic :='0';
+signal rxLossOfSync1_S     : std_logic;
+signal fsmStatus_S         : std_logic_vector(1 downto 0);
+signal rxPLLwrapper_reset_S : std_logic :='0';
+signal rxResetBitLock_pulse_S : std_logic :='0';
+
+signal rxphmonitor_S       : std_logic_vector(4 downto 0);
+signal rxphslipmonitor_S   : std_logic_vector(4 downto 0);
+
+signal pllLkDet_S          : std_logic :='0';
+signal resetDone_S         : std_logic :='0';
+
+signal eyescandataerror_S  : std_logic :='0';
+signal rxCDRlock_S         : std_logic :='0';
+signal CDR_reset_S         : std_logic :='0';
+
+signal drpaddr_in_S        : std_logic_vector(8 downto 0);
+signal drpdi_in_S          : std_logic_vector(15 downto 0);
+signal drpdo_out_S         : std_logic_vector(15 downto 0);
+signal drpen_in_S          : std_logic;
+signal drprdy_out_S        : std_logic;
+signal drpwe_in_S          : std_logic;
+
+signal comma_align_latency_S        : std_logic_vector(6 downto 0);
+signal comma_align_latency0_valid_S : std_logic;
+signal comma_align_latency_valid_S  : std_logic;
+
+
+type drp_state_type is (initting, running, reading);
+signal drp_state_S : drp_state_type := initting;	
+
+
+
+begin
+	resetDone <= resetDone_S;
+	rxLocked <= rxLocked2_S;
+	txLocked <= txLocked_S;	
+	rxUsrClkdiv2 <= rxRecClk_S;
+	txUsrClk <= txUsrClkx2_S;
+
+	
+process(txUsrClk_buf_S,txResetdone_S)
+    begin
+        if(txResetdone_S = '0') then
+            gtx0_txresetdone_r  <= '0';
+            gtx0_txresetdone_r2 <= '0';
+        elsif(txUsrClk_buf_S'event and txUsrClk_buf_S = '1') then
+            gtx0_txresetdone_r  <= txResetdone_S;
+            gtx0_txresetdone_r2 <= gtx0_txresetdone_r;
+        end if;
+    end process;
+txReset_S <= '0'; 
+txLocked_S <= '1' when (gtx0_txresetdone_r2='1') else '0';			
+	
+
+DC_data8to16_1: DC_data8to16
+	port map( 
+		clock_in => txUsrClkx2_S,
+		data_in => txData,
+		kchar_in => txCharIsK,
+		clock_out => txUsrClk_buf_S,
+		data_out => txData16_S,
+		kchar_out => txCharIsK16_S
+	);
+
+DC_data16to8_1: DC_data16to8 
+	port map(
+		clock_in => rxRecClk_S,
+		data_in => rxData16_S,
+		kchar_in => rxCharIsK16_S,
+		notintable_in => rxNotInTable16_S,
+		clock_out => rxUsrClk,
+		data_out => rxData_S,
+		kchar_out => rxCharIsK_S,
+		notintable_out => rxNotInTable_S
+	);
+rxData <= rxData_S;
+rxCharIsK <= rxCharIsK_S;
+rxNotInTable <= rxNotInTable_S;
+
+
+-- clock100to200a: clock100to200 port map(
+		-- clk_in1 => txoutclk_S,
+		-- clk_out1 => txUsrClk_buf_S,
+		-- clk_out2 => txUsrClkx2_S,
+		-- reset => gtpReset_S,
+		-- locked => open);
+
+
+--buf_rxclk: BUFG port map(I => rxRecClk_S, O => rxRecClk_buf_S);
+
+
+ 	
+gtx_i : GTX_SODAinput_support 
+	port map(
+		SOFT_RESET_TX_IN => gtpReset_S,
+		SOFT_RESET_RX_IN => gtpReset_S,
+		DONT_RESET_ON_DATA_ERROR_IN => '1',
+    Q3_CLK0_GTREFCLK_PAD_N_IN => '0', --// Modified
+    Q3_CLK0_GTREFCLK_PAD_P_IN => '0', --// Modified
+        GT0_TX_MMCM_LOCK_OUT => open,
+		GT0_TX_FSM_RESET_DONE_OUT => open, --// txResetdone_S,
+		GT0_RX_FSM_RESET_DONE_OUT => open, --// resetDone_S,
+    GT0_DATA_VALID_IN => '1',
+    GT0_TXUSRCLK_OUT => open,
+    GT0_TXUSRCLK2_OUT => txoutclk_S,
+    GT0_TXUSRCLKX2_OUT => txUsrClkx2_S,
+    GT0_RXUSRCLK_OUT => open,
+    GT0_RXUSRCLK2_OUT => rxRecClk_S,
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y15)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out => open,
+        gt0_cplllock_out => pllLkDet_S,
+        gt0_cpllreset_in => '0',
+        ---------------------------- Channel - DRP Ports  --------------------------
+		gt0_drpaddr_in => drpaddr_in_S,
+		gt0_drpdi_in => drpdi_in_S,
+		gt0_drpdo_out => drpdo_out_S,
+		gt0_drpen_in => drpen_in_S,
+		gt0_drprdy_out => drprdy_out_S,
+		gt0_drpwe_in => drpwe_in_S,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out => open,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in => '0',
+		gt0_rxuserrdy_in => '0',
+        -------------------------- RX Margin Analysis Ports ------------------------
+ 		gt0_eyescandataerror_out => eyescandataerror_S,
+        gt0_eyescantrigger_in => '0',
+        -------------------------- RX CDR Reset Ports ------------------------ // modified
+ 		GT0_RXCDRRESET_IN => CDR_reset_S,
+		GT0_RXCDRLOCK_OUT => rxCDRlock_S,
+       ------------------ Receive Ports - FPGA RX interface Ports -----------------
+		gt0_rxdata_out => rxData16_S,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+		gt0_rxdisperr_out => rxDispError16_S,
+		gt0_rxnotintable_out => rxNotInTable16_S,
+        --------------------------- Receive Ports - RX AFE -------------------------
+		gt0_gtxrxp_in => rxP,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+ 		gt0_gtxrxn_in => rxN,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+		gt0_rxphmonitor_out => rxphmonitor_S,
+		gt0_rxphslipmonitor_out => rxphslipmonitor_S,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in => '0',
+        gt0_rxmonitorout_out => open,
+        gt0_rxmonitorsel_in => "00",
+	
+		------------- Receive Ports - RX Initialization and Reset Ports ------------
+		gt0_gtrxreset_in => rxReset_S, --// => '0',
+		gt0_rxpmareset_in => rxReset_S, --// => '0',
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+		gt0_rxcharisk_out => rxCharIsK16_S,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+		gt0_rxresetdone_out => resetDone_S,
+		--------------------- TX Initialization and Reset Ports --------------------
+		gt0_gttxreset_in => txReset_S,
+		gt0_txuserrdy_in => '0',
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+		gt0_txdata_in => txData16_S,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+		gt0_gtxtxn_out => txN,
+		gt0_gtxtxp_out => txP,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+		gt0_txoutclkfabric_out => open,
+		gt0_txoutclkpcs_out => open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+		gt0_txcharisk_in => txCharIsK16_S,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+		gt0_txresetdone_out => txResetdone_S,
+		GT0_QPLLOUTCLK_OUT  => GT0_QPLLOUTCLK_OUT,
+		GT0_QPLLOUTREFCLK_OUT => GT0_QPLLOUTREFCLK_OUT,
+		sysclk_in => sysClk,
+		q2_clk1_gtrefclk => refClk_P,  --//modification
+		q3_clk0_gtrefclk => refClk_N  --//modification
+	);
+
+rxLossOfSync1_S <= '0' when (rxNotInTable16_S="00") or (disable_GTX_reset='1') else '1';
+DC_rxBitLock1 : DC_rxBitLock port map (
+		clk => rxRecClk_S,
+		reset => gtpReset_S,
+		resetDone => resetDone_S,
+		lossOfSync => rxLossOfSync1_S,
+		rxPllLocked => PllLkDet_S,
+		rxReset => rxResetBitLock_S,
+		fsmStatus => fsmStatus_S
+	);
+	
+process(sysClk,gtpReset)
+variable counter_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+	if gtpReset='1' then
+		gtpReset_S	<= '1';
+		counter_V := (others => '0');
+	elsif rising_edge(sysClk) then
+		gtpReset_S	<= '0';
+		if counter_V(counter_V'left)='1' then
+			if resetDone_S='0' then
+				counter_V := (others => '0');
+				gtpReset_S	<= '1';
+			end if;
+		else
+			counter_V := counter_V+1;
+		end if;
+	end if;
+end process;
+
+---- rxReset_S <= gtpReset;
+rxReset_S <= '1' when ((rxPLLwrapper_reset_S='1') or (gtpReset_S='1') or (rxResetBitLock_pulse_S='1')) and (disable_GTX_reset='0') else '0';
+--//rxLocked_S	<= '1' when (fsmStatus_S = "10")  else '0';
+-- peter: gepulste reset (op refclk) voor zowel GTP als PLL
+-- lengte van de reset-pulse varieert om te voorkomen dat de reset synchroon is met de GTP			
+----rxPLLwrapper_reset_S <= '1' when (notPllLkDet_S='1') or (rxResetBitLock_pulse_S='1') else '0';
+
+
+--//rxPLLwrapper_reset_S <= '0'; --// '1' when (rxResetBitLock_pulse_S='1') else '0';
+
+rxLocked0_S <= '1' when (resetDone_S='1') and (fsmStatus_S = "10") else '0';
+sync_rx_locked: sync_bit port map(
+	clock => sysClk,
+	data_in => rxLocked0_S,
+	data_out => rxLocked1_S);
+
+process(asyncclk) 
+variable resetcounter_V : integer range 0 to 63 := 0;
+variable lastresetcounter_V : integer range 0 to 63 := 10;
+begin
+	if rising_edge(asyncclk) then
+		if (sync_rxResetBitLock_S='1') and (prev_rxResetBitLock_S='0') then
+			rxResetBitLock_pulse_S <= '1';
+			resetcounter_V := 0;
+			if lastresetcounter_V<63 then
+				lastresetcounter_V := lastresetcounter_V+1;
+			else
+				lastresetcounter_V := 10;
+			end if;
+		elsif resetcounter_V<lastresetcounter_V then
+			rxResetBitLock_pulse_S <= '1';
+			resetcounter_V := resetcounter_V+1;
+		else
+			rxResetBitLock_pulse_S <= '0';
+		end if;
+		sync_rxResetBitLock_S <= rxResetBitLock_S;
+		prev_rxResetBitLock_S <= sync_rxResetBitLock_S;
+	end if;
+end process;
+process(sysClk) 
+variable counter_V : std_logic_vector(5 downto 0) := (others => '0');
+variable timoutcounter_V : std_logic_vector(11 downto 0) := (others => '0');
+begin
+	if rising_edge(sysClk) then
+		rxPLLwrapper_reset_S <= '0';
+		CDR_reset_S <= '0';
+		comma_align_latency0_valid_S <= '0';
+		drpen_in_S <= '0';
+		drpwe_in_S <= '0';
+		drpdi_in_S <= (others => '0');
+		case drp_state_S is
+			when initting =>
+				rxLocked2_S	<= '0';
+				counter_V := (others => '0');
+				if resetDone_S='1' then
+					drp_state_S <= running;
+				end if;
+			when running =>
+				if rxLocked1_S='0' then
+					drp_state_S <= initting;
+				else
+					if counter_V(counter_V'left) = '1' then
+						counter_V := (others => '0');
+						timoutcounter_V := (others => '0');
+						drpen_in_S <= '1';
+						drpaddr_in_S <= "101001110"; -- x"14E";
+						drp_state_S <= reading;
+					else
+						counter_V := counter_V+1;
+					end if;
+				end if;
+			when reading =>
+				if drprdy_out_S='1' then
+					comma_align_latency_S <= drpdo_out_S(6 downto 0); --		COMMA_ALIGN_LATENCY
+					comma_align_latency0_valid_S <= '1';
+					if drpdo_out_S(6 downto 0)/="0000000" then
+						CDR_reset_S <= '1'; --// rxPLLwrapper_reset_S <= '1';
+						rxLocked2_S	<= '0';
+					else 
+						rxLocked2_S	<= '1';
+					end if;
+					drp_state_S <= running;
+				elsif timoutcounter_V(timoutcounter_V'left)='1' then
+					CDR_reset_S <= '1';
+					rxPLLwrapper_reset_S <= '1';
+					drp_state_S <= initting;
+				else
+					timoutcounter_V := timoutcounter_V+1;
+				end if;
+			when others =>
+				drp_state_S <= initting;
+		end case;
+	end if;
+end process;
+
+
+pulse_comma_align_latency: DC_posedge_to_pulse port map(
+		clock_in => sysClk,
+		clock_out => rxRecClk_S,
+		en_clk => '1',
+		signal_in => comma_align_latency0_valid_S,
+		pulse => comma_align_latency_valid_S);
+
+
+end Behavioral;
diff --git a/data_concentrator/sources/xilinx/DC_data16to8.vhd b/data_concentrator/sources/xilinx/DC_data16to8.vhd
new file mode 100644
index 0000000..f9364d6
--- /dev/null
+++ b/data_concentrator/sources/xilinx/DC_data16to8.vhd
@@ -0,0 +1,114 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   04-02-2015
+-- Module Name:   DC_data16to8
+-- Description:   Converts 16 bits data at 100MHz to 8 bits data at 200MHz
+-- Modifications:
+--   04-05-2015   version Data Concentrator instead of Front End Electronics
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- DC_data16to8
+-- Converts 16 bits data at 100MHz to 8 bits data at 200MHz
+--
+-- Library
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock_in : input clock at single 
+--     data_in : 16 bits input data
+--     kchar_in : corresponding k-character (one for each input byte)
+--     notintable_in : error, signal not in 10/8 decoder table
+-- 
+-- Outputs:
+--     clock_out : output clock at double speed
+--     data_out : 8 bits output data at double speed
+--     kchar_out : corresponding k-character
+--     notintable_out : error, signal not in 10/8 decoder table
+-- 
+-- Components:
+--     clock100to200 : clock doubler : 100MHz -> 200MHz
+--
+----------------------------------------------------------------------------------
+
+entity DC_data16to8 is
+	port ( 
+		clock_in                : in std_logic;
+		data_in                 : in std_logic_vector(15 downto 0);
+		kchar_in                : in std_logic_vector(1 downto 0);
+		notintable_in           : in std_logic_vector(1 downto 0);
+		clock_out               : out std_logic;
+		data_out                : out std_logic_vector(7 downto 0);
+		kchar_out               : out std_logic;
+		notintable_out          : out std_logic
+	);
+end DC_data16to8;
+
+architecture Behavioral of DC_data16to8 is
+
+component clock100to200 is
+	port
+	(
+		clk_in1                 : in std_logic;
+		clk_out1                : out std_logic;
+		reset                   : in std_logic;
+		locked                  : out std_logic
+	);
+end component;
+
+signal clock_out_S              : std_logic;
+signal phase_S                  : std_logic;
+signal kchar_in_S               : std_logic_vector(1 downto 0);
+
+begin
+
+clock100to200_1: clock100to200 port map(
+		clk_in1 => clock_in,
+		clk_out1 => clock_out_S,
+		reset => '0',
+		locked => open);
+clock_out <= clock_out_S;
+
+process(clock_out_S)
+begin
+	if (rising_edge(clock_out_S)) then
+		kchar_in_S <= kchar_in;
+	end if;
+end process;
+	
+process(clock_out_S)
+begin
+	if (rising_edge(clock_out_S)) then
+		if kchar_in_S/=kchar_in then
+			phase_S <= '0';
+		else
+			phase_S <= not phase_S;
+		end if;
+	end if;
+end process;
+
+process(clock_out_S)
+begin
+	if (rising_edge(clock_out_S)) then
+		if phase_S='1' then
+			data_out <= data_in(7 downto 0);
+			kchar_out <= kchar_in(0);
+			notintable_out <= notintable_in(0);
+		else
+			data_out <= data_in(15 downto 8);
+			kchar_out <= kchar_in(1);
+			notintable_out <= notintable_in(1);
+		end if;
+	end if;
+end process;
+
+end Behavioral;
diff --git a/data_concentrator/sources/xilinx/DC_data8to16.vhd b/data_concentrator/sources/xilinx/DC_data8to16.vhd
new file mode 100644
index 0000000..1742f1c
--- /dev/null
+++ b/data_concentrator/sources/xilinx/DC_data8to16.vhd
@@ -0,0 +1,86 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   06-02-2015
+-- Module Name:   DC_data8to16
+-- Description:   Converts 8 bits data at 200MHz to 16 bits data at 100MHz
+-- Modifications:
+--   04-05-2015   version Data Concentrator instead of Front End Electronics
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+library UNISIM;
+use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- DC_data8to16
+-- Converts 8 bits data at 200MHz to 16 bits data at 100MHz
+--
+-- Library
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock_in : input clock
+--     data_in : 8 bits input data
+--     kchar_in : corresponding k-character
+-- 
+-- Outputs:
+--     clock_out : output clock at half speed
+--     data_out : 16 bits output data at half speed
+--     kchar_out : corresponding k-character (one for each byte)
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+entity DC_data8to16 is
+	port ( 
+		clock_in                : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		kchar_in                : in std_logic;
+		clock_out               : in std_logic;
+		data_out                : out std_logic_vector(15 downto 0);
+		kchar_out               : out std_logic_vector(1 downto 0)
+	);
+end DC_data8to16;
+
+architecture Behavioral of DC_data8to16 is
+
+signal clock_in_S               : std_logic;
+signal data_in0_S               : std_logic_vector(7 downto 0);
+signal kchar_in0_S              : std_logic;
+signal data_in1_S               : std_logic_vector(7 downto 0);
+signal kchar_in1_S              : std_logic;
+signal data_out_S               : std_logic_vector(15 downto 0);
+signal kchar_out_S              : std_logic_vector(1 downto 0);
+
+begin
+
+clock_in_S <= clock_in;
+
+	
+process(clock_in_S)
+begin
+	if (rising_edge(clock_in_S)) then
+		data_in0_S <= data_in;
+		kchar_in0_S <= kchar_in;
+		data_in1_S <= data_in0_S;
+		kchar_in1_S <= kchar_in0_S;
+	end if;
+end process;
+
+process(clock_out)
+begin
+	if (rising_edge(clock_out)) then
+		data_out_S <= data_in0_S & data_in1_S;
+		kchar_out_S <= kchar_in0_S & kchar_in1_S;
+		data_out <= data_out_S;
+		kchar_out <= kchar_out_S;
+	end if;
+end process;
+
+end Behavioral;
diff --git a/data_concentrator/sources/xilinx/DC_rxBitLock.vhd b/data_concentrator/sources/xilinx/DC_rxBitLock.vhd
new file mode 100644
index 0000000..cc622f3
--- /dev/null
+++ b/data_concentrator/sources/xilinx/DC_rxBitLock.vhd
@@ -0,0 +1,175 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Michel Hevinga / Peter Schakel
+-- Create Date:   2010
+-- Module Name:   DC_rxBitLock
+-- Description:   Module to lock receiving clock of GTP/GTX at the right phase
+-- Modifications:
+--   18-11-2014   8 bits data instead of 16 bits
+--   19-11-2014   name changed from rxBitLock to FEE_rxBitLock
+--   26-05-2015   name changed from FEE_rxBitLock to DC_rxBitLock
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+--use IEEE.NUMERIC_STD.ALL;
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+----------------------------------------------------------------------------------
+-- DC_rxBitLock
+-- Module to lock receiving clock of GTP/GTX at the right phase.
+-- First is checked if the resetDone input is high, (resetting is done)
+-- then if lossOfSync is low ('0'), (GTP/GTX loss of sync signal)
+-- If all these checks are allright the fmstatus will show that the GTP/GTX is locked on th incomming data.
+-- If one of these checks are not reached within a certain time (TIME_OUT_SYNC_MAX constant)
+-- the rxReset output is activated and checking is started again.
+-- Also, the lossOfSync is always checked during operation.
+--
+-- Library
+--
+-- Generics:
+-- 
+-- Inputs:
+--     clk : recovered clock from the GTP/GTX
+--     reset : reset
+--     resetDone : Reset is done, ready to check lock & synchronisation
+--     lossOfSync : Loss of Sync: "00" means synchronised
+--     rxPllLocked : Receiver PLL locked, not used at the moment
+-- 
+-- Outputs:
+--     rxReset : Reset GTP/GTX to try another lock
+--     fsmStatus : Status of the state machine:
+--        00 : WAIT_RESET_DONE : waiting until ResetDone
+--        01 : WAIT_TIME_OUT_SYNC : waiting for word aligned
+--        10 : CHECK_LOSS_SYNC : running state : keep on checking for Loss of sync and bytes swapped
+--        11 : RX_RESET : resetting for a new lock attempt
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+entity DC_rxBitLock is
+	port (
+		clk                     : in std_logic;
+		reset                   : in std_logic;
+		resetDone               : in std_logic;
+		lossOfSync              : in std_logic;
+		rxPllLocked             : in std_logic;
+		rxReset                 : out std_logic;
+		fsmStatus               : out std_logic_vector (1 downto 0));
+end DC_rxBitLock;
+
+architecture Behavioral of DC_rxBitLock is
+
+constant TIME_OUT_SYNC_MAX	: integer range 0 to 500 := 500;
+
+signal rxReset_S              : std_logic :='0';
+signal fsmStatus_S            : std_logic_vector (1 downto 0) :="00";
+signal timeOutSynFlag_S       : std_logic :='0';
+signal timeOutSyncCounter_I   : integer range 0 to TIME_OUT_SYNC_MAX :=0;
+
+signal resettimeFlag_S        : std_logic :='0'; -- counter & flag for reset extender
+signal resettimeCounter_I     : integer range 0 to 15 :=0; -- counter & flag for reset extender
+
+
+type state_T is (WAIT_RESET_DONE, WAIT_TIME_OUT_SYNC, CHECK_LOSS_SYNC, RX_RESET);
+signal currentState_S,nextState_S : state_T := WAIT_RESET_DONE;	
+
+begin
+
+rxReset <= rxReset_S;
+fsmStatus <= fsmStatus_S;
+
+fsmClk: process(clk, reset)
+begin
+	if (reset = '1')then
+		currentState_S <= RX_RESET;
+	else
+		if rising_edge(clk) then
+			currentState_S <= nextState_S;
+		end if;
+	end if;
+end process;
+
+fsmInput: process (currentState_S,resetDone, timeOutSynFlag_S, 
+			lossOfSync, rxPllLocked, timeOutSynFlag_S, resettimeFlag_S)
+begin
+	case currentState_S is
+		when WAIT_RESET_DONE 	=> if(resetDone = '1') then
+												nextState_S <= WAIT_TIME_OUT_SYNC;
+											else
+												nextState_S <= WAIT_RESET_DONE;
+											end if;
+		when WAIT_TIME_OUT_SYNC	=> if (timeOutSynFlag_S = '1') then
+												nextState_S <= RX_RESET;
+											else
+												if (lossOfSync = '0') then
+													nextState_S <= CHECK_LOSS_SYNC;
+												else
+													nextState_S <= WAIT_TIME_OUT_SYNC;
+												end if;
+											end if;
+		when CHECK_LOSS_SYNC		=> if (lossOfSync /= '0') then
+												nextState_S <= RX_RESET;
+											else
+												nextState_S <= CHECK_LOSS_SYNC;
+											end if;
+		when RX_RESET				=>	if (resettimeFlag_S = '1') then  -- reset long to prevent that resetDone signal is missed
+												nextState_S <= WAIT_RESET_DONE;
+											else
+												nextState_S <= RX_RESET;
+											end if;
+		when others					=> nextState_S <= RX_RESET;
+	end case;
+end process;
+
+fsmOutput: process (clk)
+begin
+if rising_edge(clk) then
+	case currentState_S is
+		when WAIT_RESET_DONE 	=> fsmStatus_S <= "00";
+											rxReset_S <= '0';
+											timeOutSyncCounter_I <= 0;
+											timeOutSynFlag_S <= '0';
+											resettimeFlag_S <= '0';
+											resettimeCounter_I <= 0;
+		when WAIT_TIME_OUT_SYNC	=> fsmStatus_S <= "01";
+											rxReset_S <= '0';
+											resettimeFlag_S <= '0';
+											resettimeCounter_I <= 0;
+											if (timeOutSyncCounter_I < TIME_OUT_SYNC_MAX) then
+												timeOutSyncCounter_I <= timeOutSyncCounter_I+1;
+												timeOutSynFlag_S <= '0';
+											else
+												timeOutSyncCounter_I <= 0;
+												timeOutSynFlag_S <= '1';
+											end if;		
+		when CHECK_LOSS_SYNC		=> fsmStatus_S <= "10";
+											rxReset_S <= '0';
+											timeOutSyncCounter_I <= 0;
+											timeOutSynFlag_S <= '0';
+											resettimeFlag_S <= '0';
+											resettimeCounter_I <= 0;
+		
+		when RX_RESET				=>	fsmStatus_S <= "11";
+											rxReset_S <= '1';
+											timeOutSyncCounter_I <= 0;
+											timeOutSynFlag_S <= '0';
+											if resettimeCounter_I<8 then  -- peter : reset langer gemaakt om te voorkomen dat resetDone signaal wordt gemist
+												resettimeCounter_I <= resettimeCounter_I+1;
+												resettimeFlag_S <= '0';
+											else
+												resettimeCounter_I <= 0;
+												resettimeFlag_S <= '1';
+											end if;
+		
+		when others					=> 
+	end case;
+end if;	
+end process;
+
+
+end Behavioral;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX/GTX_trb3_2gb_wrapper.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX/GTX_trb3_2gb_wrapper.vhd
new file mode 100644
index 0000000..6eda3f1
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX/GTX_trb3_2gb_wrapper.vhd
@@ -0,0 +1,627 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_trb3_2gb_support.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_trb3_2gb_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_trb3_2gb_wrapper is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 10  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT  : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT : out std_logic;
+       sysclk_in        : in std_logic
+
+);
+
+end GTX_trb3_2gb_wrapper;
+    
+architecture RTL of GTX_trb3_2gb_wrapper is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_trb3_2gb
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_trb3_2gb_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component GTX_trb3_2gb_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE" ;       -- Set to "TRUE" to speed up sim reset
+    SIM_QPLLREFCLK_SEL              :bit_vector  := "001"
+ 
+);
+port
+(
+    QPLLREFCLKSEL_IN   : in std_logic_vector(2 downto 0);
+    GTREFCLK0_IN : in std_logic;
+    GTREFCLK1_IN      : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_trb3_2gb_GT_USRCLK_SOURCE 
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    Q2_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_OUT                    : out  std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y10)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt0_rxdlyen_i                   : std_logic;
+    signal  gt0_rxdlysreset_i               : std_logic;
+    signal  gt0_rxdlysresetdone_i           : std_logic;
+    signal  gt0_rxphalign_i                 : std_logic;
+    signal  gt0_rxphaligndone_i             : std_logic;
+    signal  gt0_rxphalignen_i               : std_logic;
+    signal  gt0_rxphdlyreset_i              : std_logic;
+    signal  gt0_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt0_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    ----------------------------- Reference Clocks ----------------------------
+    
+signal    q2_clk0_refclk_i                : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+     gt0_qplloutclk_out <= gt0_qplloutclk_i;
+     gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+    
+  
+    gt_usrclk_source : GTX_trb3_2gb_GT_USRCLK_SOURCE
+    port map
+   (
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+        GT0_RXOUTCLK_IN                 =>      gt0_rxoutclk_i,
+        Q2_CLK0_GTREFCLK_PAD_N_IN       =>      Q2_CLK0_GTREFCLK_PAD_N_IN,
+        Q2_CLK0_GTREFCLK_PAD_P_IN       =>      Q2_CLK0_GTREFCLK_PAD_P_IN,
+        Q2_CLK0_GTREFCLK_OUT            =>      q2_clk0_refclk_i
+
+    );
+
+sysclk_in_i <= sysclk_in;
+
+    common0_i:GTX_trb3_2gb_common 
+  generic map
+  (
+   WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+   SIM_QPLLREFCLK_SEL => "001"
+  )
+ port map
+   (
+    QPLLREFCLKSEL_IN    => "001",
+    GTREFCLK0_IN      => q2_clk0_refclk_i,
+    GTREFCLK1_IN      => tied_to_ground_i,
+    QPLLLOCK_OUT => gt0_qplllock_i,
+    QPLLLOCKDETCLK_IN => sysclk_in_i,
+    QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+    common_reset_i:GTX_trb3_2gb_common_reset 
+   generic map 
+   (
+      STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   )
+   port map
+   (    
+      STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET => soft_reset_tx_in,               --User Reset, can be pulled any time
+      COMMON_RESET => commonreset_i              --Reset QPLL
+   );
+
+
+    GTX_trb3_2gb_init_i : GTX_trb3_2gb
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_tx_in                =>      SOFT_RESET_TX_IN,
+        soft_reset_rx_in                =>      SOFT_RESET_RX_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y10)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      q2_clk0_refclk_i,
+        gt0_gtrefclk1_in                =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX/GTX_trb3_2gb_wrapper_ver3.4.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX/GTX_trb3_2gb_wrapper_ver3.4.vhd
new file mode 100644
index 0000000..7741d5e
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX/GTX_trb3_2gb_wrapper_ver3.4.vhd
@@ -0,0 +1,621 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.4
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_trb3_2gb_support.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_trb3_2gb_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_trb3_2gb_wrapper is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 10  
+
+);
+port
+(
+    SOFT_RESET_IN                           : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT  : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT : out std_logic;
+     SYSCLK_IN                             : in   std_logic
+
+);
+
+end GTX_trb3_2gb_wrapper;
+    
+architecture RTL of GTX_trb3_2gb_wrapper is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_trb3_2gb
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_IN                           : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+     ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_trb3_2gb_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component GTX_trb3_2gb_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE"        -- Set to "TRUE" to speed up sim reset 
+);
+port
+(
+    GTREFCLK0_IN : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_trb3_2gb_GT_USRCLK_SOURCE 
+port
+(
+    Q2_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_OUT                    : out  std_logic;
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    DRPCLK_IN_P                        : in  std_logic;
+    DRPCLK_IN_N                        : in  std_logic;
+    DRPCLK_OUT                         : out std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y10)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt0_rxdlyen_i                   : std_logic;
+    signal  gt0_rxdlysreset_i               : std_logic;
+    signal  gt0_rxdlysresetdone_i           : std_logic;
+    signal  gt0_rxphalign_i                 : std_logic;
+    signal  gt0_rxphaligndone_i             : std_logic;
+    signal  gt0_rxphalignen_i               : std_logic;
+    signal  gt0_rxphdlyreset_i              : std_logic;
+    signal  gt0_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt0_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    ----------------------------- Reference Clocks ----------------------------
+    
+signal    q2_clk0_refclk_i                : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+sysclk_in_i <= SYSCLK_IN;
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+     gt0_qplloutclk_out <= gt0_qplloutclk_i;
+     gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+    
+  
+    gt_usrclk_source : GTX_trb3_2gb_GT_USRCLK_SOURCE
+    port map
+   (
+        Q2_CLK0_GTREFCLK_PAD_N_IN       =>      Q2_CLK0_GTREFCLK_PAD_N_IN,
+        Q2_CLK0_GTREFCLK_PAD_P_IN       =>      Q2_CLK0_GTREFCLK_PAD_P_IN,
+        Q2_CLK0_GTREFCLK_OUT            =>      q2_clk0_refclk_i,
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+        GT0_RXOUTCLK_IN                 =>      gt0_rxoutclk_i,
+        DRPCLK_IN_P                     =>      '0',
+        DRPCLK_IN_N                     =>      '1',
+        DRPCLK_OUT                      =>      open
+
+    );
+
+
+    common0_i:GTX_trb3_2gb_common 
+  generic map
+  (
+   WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP
+  )
+ port map
+   (
+    GTREFCLK0_IN => q2_clk0_refclk_i,
+    QPLLLOCK_OUT => gt0_qplllock_i,
+    QPLLLOCKDETCLK_IN => sysclk_in_i,
+    QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+    common_reset_i:GTX_trb3_2gb_common_reset 
+   generic map 
+   (
+      STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   )
+   port map
+   (    
+      STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET => soft_reset_in,               --User Reset, can be pulled any time
+      COMMON_RESET => commonreset_i              --Reset QPLL
+   );
+
+
+    GTX_trb3_2gb_init_i : GTX_trb3_2gb
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_in                   =>      SOFT_RESET_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y10)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      q2_clk0_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX/gtx_trb3_2gb_common.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX/gtx_trb3_2gb_common.vhd
new file mode 100644
index 0000000..d8aaa8d
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX/gtx_trb3_2gb_common.vhd
@@ -0,0 +1,247 @@
+---------------------------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_trb3_2gb_common.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_trb3_2gb_common 
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_trb3_2gb_common is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "TRUE";        -- Set to "true" to speed up sim reset 
+    SIM_QPLLREFCLK_SEL              : bit_vector :=  "001"
+);
+port
+(
+    QPLLREFCLKSEL_IN  : in std_logic_vector(2 downto 0);
+    GTREFCLK1_IN      : in std_logic;
+    GTREFCLK0_IN : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+);
+
+end GTX_trb3_2gb_common;
+    
+architecture RTL of GTX_trb3_2gb_common is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_trb3_2gb_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+    impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return "0000100000";
+       elsif (qpllfbdiv_top = 20) then
+         return "0000110000" ;
+       elsif (qpllfbdiv_top = 32) then
+         return "0001100000" ;
+       elsif (qpllfbdiv_top = 40) then
+         return "0010000000" ;
+       elsif (qpllfbdiv_top = 64) then
+         return "0011100000" ;
+       elsif (qpllfbdiv_top = 66) then
+         return "0101000000" ;
+       elsif (qpllfbdiv_top = 80) then
+         return "0100100000" ;
+       elsif (qpllfbdiv_top = 100) then
+         return "0101110000" ;
+       else 
+         return "0000000000" ;
+       end if;
+    end function;
+
+    impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return '1';
+       elsif (qpllfbdiv_top = 20) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 32) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 40) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 64) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 66) then
+         return '0' ;
+       elsif (qpllfbdiv_top = 80) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 100) then
+         return '1' ;
+       else 
+         return '1' ;
+       end if;
+    end function;
+
+    constant   QPLL_FBDIV_TOP   : integer  := 16;
+    constant   QPLL_FBDIV_IN    :   bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+    constant   QPLL_FBDIV_RATIO :   bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal  tied_to_vcc_vec_i               :   std_logic_vector(63 downto 0);
+
+begin
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    tied_to_vcc_vec_i(63 downto 0)      <= (others => '1');
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTXE2_COMMON____________________________________
+
+    gtxe2_common_i : GTXE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_QPLLREFCLK_SEL   => (SIM_QPLLREFCLK_SEL),
+            SIM_VERSION          => "4.0",
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000040000001000"),
+        COMMON_CFG                              =>     (x"00000000"),
+        QPLL_CFG                                =>     (x"06801C1"),
+        QPLL_CLKOUT_CFG                         =>     ("0000"),
+        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
+        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
+        QPLL_CP                                 =>     ("0000011111"),
+        QPLL_CP_MONITOR_EN                      =>     ('0'),
+        QPLL_DMONITOR_SEL                       =>     ('0'),
+        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
+        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
+        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
+        QPLL_INIT_CFG                           =>     (x"000006"),
+        QPLL_LOCK_CFG                           =>     (x"21E8"),
+        QPLL_LPF                                =>     ("1111"),
+        QPLL_REFCLK_DIV                         =>     (1)
+
+        
+    )
+    port map
+    (
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      GTREFCLK1_IN,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ------------------------- Common Block -  QPLL Ports -----------------------
+        QPLLDMONITOR                    =>      open,
+        ----------------------- Common Block - Clocking Ports ----------------------
+        QPLLOUTCLK                      =>      QPLLOUTCLK_OUT,
+        QPLLOUTREFCLK                   =>      QPLLOUTREFCLK_OUT,
+        REFCLKOUTMONITOR                =>      open,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        QPLLFBCLKLOST                   =>      open,
+        QPLLLOCK                        =>      QPLLLOCK_OUT,
+        QPLLLOCKDETCLK                  =>      QPLLLOCKDETCLK_IN,
+        QPLLLOCKEN                      =>      tied_to_vcc_i,
+        QPLLOUTRESET                    =>      tied_to_ground_i,
+        QPLLPD                          =>      tied_to_vcc_i,
+        QPLLREFCLKLOST                  =>      QPLLREFCLKLOST_OUT,
+        QPLLREFCLKSEL                   =>      QPLLREFCLKSEL_IN,
+        QPLLRESET                       =>      QPLLRESET_IN,
+        QPLLRSVD1                       =>      "0000000000000000",
+        QPLLRSVD2                       =>      "11111",
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "11111",
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX/gtx_trb3_2gb_common_reset.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX/gtx_trb3_2gb_common_reset.vhd
new file mode 100644
index 0000000..b3fffb5
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX/gtx_trb3_2gb_common_reset.vhd
@@ -0,0 +1,154 @@
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_trb3_2gb_common_reset.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module GTX_trb3_2gb_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_trb3_2gb_common_reset is 
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic:= '0'  --Reset QPLL
+   );
+end GTX_trb3_2gb_common_reset;
+
+architecture RTL of GTX_trb3_2gb_common_reset is
+
+
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+
+
+  signal init_wait_count  : std_logic_vector(7 downto 0) :=(others => '0');
+  signal init_wait_done   : std_logic :='0';
+  signal common_reset_asserted   : std_logic :='0';
+  signal common_reset_i   : std_logic ;
+
+  type rst_type is(
+    INIT, ASSERT_COMMON_RESET);
+    
+  signal state : rst_type := INIT;
+
+begin
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1') then
+        state                <= INIT;
+        common_reset_asserted   <= '0';
+        COMMON_RESET   <= '0';
+      else
+        
+        case state is
+          when INIT => 
+            if init_wait_done = '1' then
+              state        <= ASSERT_COMMON_RESET;
+            end if;
+            
+          when ASSERT_COMMON_RESET =>
+             if common_reset_asserted = '0' then
+                COMMON_RESET          <= '1';
+                common_reset_asserted  <= '1';
+              else
+                COMMON_RESET          <= '0';
+              end if;
+           when OTHERS =>
+            state   <= INIT;
+         end case;
+       end if;
+    end if;
+  end process;
+ 
+
+end RTL; 
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX/gtx_trb3_2gb_gt_usrclk_source.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX/gtx_trb3_2gb_gt_usrclk_source.vhd
new file mode 100644
index 0000000..8bfd81c
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX/gtx_trb3_2gb_gt_usrclk_source.vhd
@@ -0,0 +1,183 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_trb3_2gb_gt_usrclk_source.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+-- Module GTX_trb3_2gb_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_trb3_2gb_GT_USRCLK_SOURCE is
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    Q2_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_OUT                    : out  std_logic
+);
+
+
+end GTX_trb3_2gb_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_trb3_2gb_GT_USRCLK_SOURCE is
+
+component GTX_TRB3_2GB_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+    signal   tied_to_ground_i     :   std_logic;
+    signal   tied_to_vcc_i        :   std_logic;
+ 
+    signal   gt0_txoutclk_i :   std_logic;
+    signal   gt0_rxoutclk_i :   std_logic;
+
+    attribute syn_noclockbuf : boolean;
+    signal   q2_clk0_gtrefclk :   std_logic;
+    attribute syn_noclockbuf of q2_clk0_gtrefclk : signal is true;
+
+    signal  gt0_txusrclk_i                  : std_logic;
+    signal  gt0_rxusrclk_i                  : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+    --  Static signal Assigments    
+    tied_to_ground_i         <= '0';
+    tied_to_vcc_i            <= '1';
+    gt0_txoutclk_i                               <= GT0_TXOUTCLK_IN;
+    gt0_rxoutclk_i                               <= GT0_RXOUTCLK_IN;
+
+    Q2_CLK0_GTREFCLK_OUT                         <= q2_clk0_gtrefclk;
+
+    --IBUFDS_GTE2
+    ibufds_instq2_clk0 : IBUFDS_GTE2  
+    port map
+    (
+        O               => 	q2_clk0_gtrefclk,
+        ODIV2           =>    open,
+        CEB             => 	tied_to_ground_i,
+        I               => 	Q2_CLK0_GTREFCLK_PAD_P_IN,
+        IB              => 	Q2_CLK0_GTREFCLK_PAD_N_IN
+    );
+
+
+    
+    -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+    -- for improved jitter performance, and to avoid consuming an additional BUFG
+    txoutclk_bufg0_i : BUFG
+    port map
+    (
+        I                               =>      gt0_txoutclk_i,
+        O                               =>      gt0_txusrclk_i
+    );
+
+
+    rxoutclk_bufg1_i : BUFG
+    port map
+    (
+        I                               =>      gt0_rxoutclk_i,
+        O                               =>      gt0_rxusrclk_i
+    );
+
+
+
+ 
+GT0_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT0_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/GTX_quadSODA_wrapper_old.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/GTX_quadSODA_wrapper_old.vhd
new file mode 100644
index 0000000..c5fc3de
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/GTX_quadSODA_wrapper_old.vhd
@@ -0,0 +1,1793 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_quadsoda_support.vhd, renamed to GTX_quadSODA_wrapper
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_quadSODA_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_quadSODA_wrapper is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 10  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q3_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q3_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_OUT                    : out  std_logic;
+    GT0_RX_MMCM_LOCK_OUT                    : out  std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_MMCM_LOCK_OUT                    : out  std_logic;
+    GT1_RX_MMCM_LOCK_OUT                    : out  std_logic;
+    GT2_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_DATA_VALID_IN                       : in   std_logic;
+    GT2_TX_MMCM_LOCK_OUT                    : out  std_logic;
+    GT2_RX_MMCM_LOCK_OUT                    : out  std_logic;
+    GT3_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_DATA_VALID_IN                       : in   std_logic;
+    GT3_TX_MMCM_LOCK_OUT                    : out  std_logic;
+    GT3_RX_MMCM_LOCK_OUT                    : out  std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT1_TXUSRCLK_OUT                        : out  std_logic;
+    GT1_TXUSRCLK2_OUT                       : out  std_logic;
+    GT1_RXUSRCLK_OUT                        : out  std_logic;
+    GT1_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT2_TXUSRCLK_OUT                        : out  std_logic;
+    GT2_TXUSRCLK2_OUT                       : out  std_logic;
+    GT2_RXUSRCLK_OUT                        : out  std_logic;
+    GT2_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT3_TXUSRCLK_OUT                        : out  std_logic;
+    GT3_TXUSRCLK2_OUT                       : out  std_logic;
+    GT3_RXUSRCLK_OUT                        : out  std_logic;
+    GT3_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtgrefclk_in                        : in   std_logic;
+    gt0_gtnorthrefclk0_in                   : in   std_logic;
+    gt0_gtnorthrefclk1_in                   : in   std_logic;
+    gt0_gtsouthrefclk0_in                   : in   std_logic;
+    gt0_gtsouthrefclk1_in                   : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt1_gtgrefclk_in                        : in   std_logic;
+    gt1_gtnorthrefclk0_in                   : in   std_logic;
+    gt1_gtnorthrefclk1_in                   : in   std_logic;
+    gt1_gtsouthrefclk0_in                   : in   std_logic;
+    gt1_gtsouthrefclk1_in                   : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+
+    --GT2  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt2_cpllfbclklost_out                   : out  std_logic;
+    gt2_cplllock_out                        : out  std_logic;
+    gt2_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt2_gtgrefclk_in                        : in   std_logic;
+    gt2_gtnorthrefclk0_in                   : in   std_logic;
+    gt2_gtnorthrefclk1_in                   : in   std_logic;
+    gt2_gtsouthrefclk0_in                   : in   std_logic;
+    gt2_gtsouthrefclk1_in                   : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt2_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt2_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt2_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt2_drpen_in                            : in   std_logic;
+    gt2_drprdy_out                          : out  std_logic;
+    gt2_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt2_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt2_eyescanreset_in                     : in   std_logic;
+    gt2_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt2_eyescandataerror_out                : out  std_logic;
+    gt2_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt2_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt2_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt2_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt2_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt2_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt2_rxdfelpmreset_in                    : in   std_logic;
+    gt2_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt2_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt2_gtrxreset_in                        : in   std_logic;
+    gt2_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt2_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt2_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt2_gttxreset_in                        : in   std_logic;
+    gt2_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt2_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt2_gtxtxn_out                          : out  std_logic;
+    gt2_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt2_txoutclkfabric_out                  : out  std_logic;
+    gt2_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt2_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt2_txresetdone_out                     : out  std_logic;
+
+    --GT3  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt3_cpllfbclklost_out                   : out  std_logic;
+    gt3_cplllock_out                        : out  std_logic;
+    gt3_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt3_gtgrefclk_in                        : in   std_logic;
+    gt3_gtnorthrefclk0_in                   : in   std_logic;
+    gt3_gtnorthrefclk1_in                   : in   std_logic;
+    gt3_gtsouthrefclk0_in                   : in   std_logic;
+    gt3_gtsouthrefclk1_in                   : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt3_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt3_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt3_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt3_drpen_in                            : in   std_logic;
+    gt3_drprdy_out                          : out  std_logic;
+    gt3_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt3_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt3_eyescanreset_in                     : in   std_logic;
+    gt3_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt3_eyescandataerror_out                : out  std_logic;
+    gt3_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt3_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt3_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt3_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt3_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt3_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt3_rxdfelpmreset_in                    : in   std_logic;
+    gt3_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt3_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt3_gtrxreset_in                        : in   std_logic;
+    gt3_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt3_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt3_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt3_gttxreset_in                        : in   std_logic;
+    gt3_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt3_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt3_gtxtxn_out                          : out  std_logic;
+    gt3_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt3_txoutclkfabric_out                  : out  std_logic;
+    gt3_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt3_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt3_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT  : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT : out std_logic;
+       sysclk_in        : in std_logic
+
+);
+
+end GTX_quadSODA_wrapper;
+    
+architecture RTL of GTX_quadSODA_wrapper is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_quadSODA
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+    GT0_RX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_RX_MMCM_RESET_OUT                   : out  std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT1_TX_MMCM_RESET_OUT                   : out  std_logic;
+    GT1_RX_MMCM_LOCK_IN                     : in   std_logic;
+    GT1_RX_MMCM_RESET_OUT                   : out  std_logic;
+    GT2_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_DATA_VALID_IN                       : in   std_logic;
+    GT2_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT2_TX_MMCM_RESET_OUT                   : out  std_logic;
+    GT2_RX_MMCM_LOCK_IN                     : in   std_logic;
+    GT2_RX_MMCM_RESET_OUT                   : out  std_logic;
+    GT3_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_DATA_VALID_IN                       : in   std_logic;
+    GT3_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT3_TX_MMCM_RESET_OUT                   : out  std_logic;
+    GT3_RX_MMCM_LOCK_IN                     : in   std_logic;
+    GT3_RX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtgrefclk_in                        : in   std_logic;
+    gt0_gtnorthrefclk0_in                   : in   std_logic;
+    gt0_gtnorthrefclk1_in                   : in   std_logic;
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    gt0_gtsouthrefclk0_in                   : in   std_logic;
+    gt0_gtsouthrefclk1_in                   : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cplllockdetclk_in                   : in   std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt1_gtgrefclk_in                        : in   std_logic;
+    gt1_gtnorthrefclk0_in                   : in   std_logic;
+    gt1_gtnorthrefclk1_in                   : in   std_logic;
+    gt1_gtrefclk0_in                        : in   std_logic;
+    gt1_gtrefclk1_in                        : in   std_logic;
+    gt1_gtsouthrefclk0_in                   : in   std_logic;
+    gt1_gtsouthrefclk1_in                   : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpclk_in                           : in   std_logic;
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt1_rxusrclk_in                         : in   std_logic;
+    gt1_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt1_txusrclk_in                         : in   std_logic;
+    gt1_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclk_out                        : out  std_logic;
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+
+    --GT2  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt2_cpllfbclklost_out                   : out  std_logic;
+    gt2_cplllock_out                        : out  std_logic;
+    gt2_cplllockdetclk_in                   : in   std_logic;
+    gt2_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt2_gtgrefclk_in                        : in   std_logic;
+    gt2_gtnorthrefclk0_in                   : in   std_logic;
+    gt2_gtnorthrefclk1_in                   : in   std_logic;
+    gt2_gtrefclk0_in                        : in   std_logic;
+    gt2_gtrefclk1_in                        : in   std_logic;
+    gt2_gtsouthrefclk0_in                   : in   std_logic;
+    gt2_gtsouthrefclk1_in                   : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt2_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt2_drpclk_in                           : in   std_logic;
+    gt2_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt2_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt2_drpen_in                            : in   std_logic;
+    gt2_drprdy_out                          : out  std_logic;
+    gt2_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt2_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt2_eyescanreset_in                     : in   std_logic;
+    gt2_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt2_eyescandataerror_out                : out  std_logic;
+    gt2_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt2_rxusrclk_in                         : in   std_logic;
+    gt2_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt2_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt2_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt2_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt2_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt2_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt2_rxdfelpmreset_in                    : in   std_logic;
+    gt2_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt2_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt2_gtrxreset_in                        : in   std_logic;
+    gt2_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt2_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt2_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt2_gttxreset_in                        : in   std_logic;
+    gt2_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt2_txusrclk_in                         : in   std_logic;
+    gt2_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt2_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt2_gtxtxn_out                          : out  std_logic;
+    gt2_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt2_txoutclk_out                        : out  std_logic;
+    gt2_txoutclkfabric_out                  : out  std_logic;
+    gt2_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt2_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt2_txresetdone_out                     : out  std_logic;
+
+    --GT3  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt3_cpllfbclklost_out                   : out  std_logic;
+    gt3_cplllock_out                        : out  std_logic;
+    gt3_cplllockdetclk_in                   : in   std_logic;
+    gt3_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt3_gtgrefclk_in                        : in   std_logic;
+    gt3_gtnorthrefclk0_in                   : in   std_logic;
+    gt3_gtnorthrefclk1_in                   : in   std_logic;
+    gt3_gtrefclk0_in                        : in   std_logic;
+    gt3_gtrefclk1_in                        : in   std_logic;
+    gt3_gtsouthrefclk0_in                   : in   std_logic;
+    gt3_gtsouthrefclk1_in                   : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt3_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt3_drpclk_in                           : in   std_logic;
+    gt3_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt3_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt3_drpen_in                            : in   std_logic;
+    gt3_drprdy_out                          : out  std_logic;
+    gt3_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt3_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt3_eyescanreset_in                     : in   std_logic;
+    gt3_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt3_eyescandataerror_out                : out  std_logic;
+    gt3_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt3_rxusrclk_in                         : in   std_logic;
+    gt3_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt3_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt3_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt3_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt3_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt3_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt3_rxdfelpmreset_in                    : in   std_logic;
+    gt3_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt3_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt3_gtrxreset_in                        : in   std_logic;
+    gt3_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt3_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt3_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt3_gttxreset_in                        : in   std_logic;
+    gt3_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt3_txusrclk_in                         : in   std_logic;
+    gt3_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt3_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt3_gtxtxn_out                          : out  std_logic;
+    gt3_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt3_txoutclk_out                        : out  std_logic;
+    gt3_txoutclkfabric_out                  : out  std_logic;
+    gt3_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt3_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt3_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_quadSODA_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component GTX_quadSODA_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE" ;       -- Set to "TRUE" to speed up sim reset
+    SIM_QPLLREFCLK_SEL              :bit_vector  := "001"
+ 
+);
+port
+(
+    GTGREFCLK_IN      : in std_logic;
+    GTNORTHREFCLK0_IN : in std_logic;
+    GTNORTHREFCLK1_IN : in std_logic;
+    GTSOUTHREFCLK0_IN : in std_logic;
+    GTSOUTHREFCLK1_IN : in std_logic;
+    QPLLREFCLKSEL_IN   : in std_logic_vector(2 downto 0);
+    GTREFCLK0_IN : in std_logic;
+    GTREFCLK1_IN      : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_quadSODA_GT_USRCLK_SOURCE 
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_TXCLK_LOCK_OUT           : out std_logic;
+    GT0_TX_MMCM_RESET_IN         : in std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXCLK_LOCK_OUT           : out std_logic;
+    GT0_RX_MMCM_RESET_IN         : in std_logic;
+ 
+    GT1_TXUSRCLK_OUT             : out std_logic;
+    GT1_TXUSRCLK2_OUT            : out std_logic;
+    GT1_TXOUTCLK_IN              : in  std_logic;
+    GT1_TXCLK_LOCK_OUT           : out std_logic;
+    GT1_TX_MMCM_RESET_IN         : in std_logic;
+    GT1_RXUSRCLK_OUT             : out std_logic;
+    GT1_RXUSRCLK2_OUT            : out std_logic;
+    GT1_RXCLK_LOCK_OUT           : out std_logic;
+    GT1_RX_MMCM_RESET_IN         : in std_logic;
+ 
+    GT2_TXUSRCLK_OUT             : out std_logic;
+    GT2_TXUSRCLK2_OUT            : out std_logic;
+    GT2_TXOUTCLK_IN              : in  std_logic;
+    GT2_TXCLK_LOCK_OUT           : out std_logic;
+    GT2_TX_MMCM_RESET_IN         : in std_logic;
+    GT2_RXUSRCLK_OUT             : out std_logic;
+    GT2_RXUSRCLK2_OUT            : out std_logic;
+    GT2_RXCLK_LOCK_OUT           : out std_logic;
+    GT2_RX_MMCM_RESET_IN         : in std_logic;
+ 
+    GT3_TXUSRCLK_OUT             : out std_logic;
+    GT3_TXUSRCLK2_OUT            : out std_logic;
+    GT3_TXOUTCLK_IN              : in  std_logic;
+    GT3_TXCLK_LOCK_OUT           : out std_logic;
+    GT3_TX_MMCM_RESET_IN         : in std_logic;
+    GT3_RXUSRCLK_OUT             : out std_logic;
+    GT3_RXUSRCLK2_OUT            : out std_logic;
+    GT3_RXCLK_LOCK_OUT           : out std_logic;
+    GT3_RX_MMCM_RESET_IN         : in std_logic;
+    Q3_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q3_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q3_CLK1_GTREFCLK_OUT                    : out  std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+    signal   gt1_txfsmresetdone_i            : std_logic;
+signal   gt1_rxfsmresetdone_i            : std_logic;
+    signal   gt1_txfsmresetdone_r            : std_logic;
+    signal   gt1_txfsmresetdone_r2           : std_logic;
+signal   gt1_rxresetdone_r               : std_logic;
+signal   gt1_rxresetdone_r2              : std_logic;
+signal   gt1_rxresetdone_r3              : std_logic;
+
+
+    signal   gt2_txfsmresetdone_i            : std_logic;
+signal   gt2_rxfsmresetdone_i            : std_logic;
+    signal   gt2_txfsmresetdone_r            : std_logic;
+    signal   gt2_txfsmresetdone_r2           : std_logic;
+signal   gt2_rxresetdone_r               : std_logic;
+signal   gt2_rxresetdone_r2              : std_logic;
+signal   gt2_rxresetdone_r3              : std_logic;
+
+
+    signal   gt3_txfsmresetdone_i            : std_logic;
+signal   gt3_rxfsmresetdone_i            : std_logic;
+    signal   gt3_txfsmresetdone_r            : std_logic;
+    signal   gt3_txfsmresetdone_r2           : std_logic;
+signal   gt3_rxresetdone_r               : std_logic;
+signal   gt3_rxresetdone_r2              : std_logic;
+signal   gt3_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y12)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    signal  gt0_gtgrefclk_i                 : std_logic;
+    signal  gt0_gtnorthrefclk0_i            : std_logic;
+    signal  gt0_gtnorthrefclk1_i            : std_logic;
+    signal  gt0_gtsouthrefclk0_i            : std_logic;
+    signal  gt0_gtsouthrefclk1_i            : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt0_txdlyen_i                   : std_logic;
+    signal  gt0_txdlysreset_i               : std_logic;
+    signal  gt0_txdlysresetdone_i           : std_logic;
+    signal  gt0_txphalign_i                 : std_logic;
+    signal  gt0_txphaligndone_i             : std_logic;
+    signal  gt0_txphalignen_i               : std_logic;
+    signal  gt0_txphdlyreset_i              : std_logic;
+    signal  gt0_txphinit_i                  : std_logic;
+    signal  gt0_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT1  (X1Y13)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt1_cpllfbclklost_i             : std_logic;
+    signal  gt1_cplllock_i                  : std_logic;
+    signal  gt1_cpllrefclklost_i            : std_logic;
+    signal  gt1_cpllreset_i                 : std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    signal  gt1_gtgrefclk_i                 : std_logic;
+    signal  gt1_gtnorthrefclk0_i            : std_logic;
+    signal  gt1_gtnorthrefclk1_i            : std_logic;
+    signal  gt1_gtsouthrefclk0_i            : std_logic;
+    signal  gt1_gtsouthrefclk1_i            : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt1_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt1_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt1_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt1_drpen_i                     : std_logic;
+    signal  gt1_drprdy_i                    : std_logic;
+    signal  gt1_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt1_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt1_eyescanreset_i              : std_logic;
+    signal  gt1_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt1_eyescandataerror_i          : std_logic;
+    signal  gt1_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt1_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt1_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt1_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt1_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt1_gtxrxn_i                    : std_logic;
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt1_rxlpmhfhold_i               : std_logic;
+    signal  gt1_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt1_rxdfelpmreset_i             : std_logic;
+    signal  gt1_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt1_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt1_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt1_gtrxreset_i                 : std_logic;
+    signal  gt1_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt1_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt1_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt1_gttxreset_i                 : std_logic;
+    signal  gt1_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt1_txdlyen_i                   : std_logic;
+    signal  gt1_txdlysreset_i               : std_logic;
+    signal  gt1_txdlysresetdone_i           : std_logic;
+    signal  gt1_txphalign_i                 : std_logic;
+    signal  gt1_txphaligndone_i             : std_logic;
+    signal  gt1_txphalignen_i               : std_logic;
+    signal  gt1_txphdlyreset_i              : std_logic;
+    signal  gt1_txphinit_i                  : std_logic;
+    signal  gt1_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt1_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt1_gtxtxn_i                    : std_logic;
+    signal  gt1_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt1_txoutclk_i                  : std_logic;
+    signal  gt1_txoutclkfabric_i            : std_logic;
+    signal  gt1_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt1_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt1_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT2  (X1Y14)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt2_cpllfbclklost_i             : std_logic;
+    signal  gt2_cplllock_i                  : std_logic;
+    signal  gt2_cpllrefclklost_i            : std_logic;
+    signal  gt2_cpllreset_i                 : std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    signal  gt2_gtgrefclk_i                 : std_logic;
+    signal  gt2_gtnorthrefclk0_i            : std_logic;
+    signal  gt2_gtnorthrefclk1_i            : std_logic;
+    signal  gt2_gtsouthrefclk0_i            : std_logic;
+    signal  gt2_gtsouthrefclk1_i            : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt2_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt2_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt2_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt2_drpen_i                     : std_logic;
+    signal  gt2_drprdy_i                    : std_logic;
+    signal  gt2_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt2_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt2_eyescanreset_i              : std_logic;
+    signal  gt2_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt2_eyescandataerror_i          : std_logic;
+    signal  gt2_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt2_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt2_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt2_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt2_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt2_gtxrxn_i                    : std_logic;
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt2_rxlpmhfhold_i               : std_logic;
+    signal  gt2_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt2_rxdfelpmreset_i             : std_logic;
+    signal  gt2_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt2_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt2_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt2_gtrxreset_i                 : std_logic;
+    signal  gt2_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt2_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt2_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt2_gttxreset_i                 : std_logic;
+    signal  gt2_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt2_txdlyen_i                   : std_logic;
+    signal  gt2_txdlysreset_i               : std_logic;
+    signal  gt2_txdlysresetdone_i           : std_logic;
+    signal  gt2_txphalign_i                 : std_logic;
+    signal  gt2_txphaligndone_i             : std_logic;
+    signal  gt2_txphalignen_i               : std_logic;
+    signal  gt2_txphdlyreset_i              : std_logic;
+    signal  gt2_txphinit_i                  : std_logic;
+    signal  gt2_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt2_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt2_gtxtxn_i                    : std_logic;
+    signal  gt2_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt2_txoutclk_i                  : std_logic;
+    signal  gt2_txoutclkfabric_i            : std_logic;
+    signal  gt2_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt2_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt2_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT3  (X1Y15)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt3_cpllfbclklost_i             : std_logic;
+    signal  gt3_cplllock_i                  : std_logic;
+    signal  gt3_cpllrefclklost_i            : std_logic;
+    signal  gt3_cpllreset_i                 : std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    signal  gt3_gtgrefclk_i                 : std_logic;
+    signal  gt3_gtnorthrefclk0_i            : std_logic;
+    signal  gt3_gtnorthrefclk1_i            : std_logic;
+    signal  gt3_gtsouthrefclk0_i            : std_logic;
+    signal  gt3_gtsouthrefclk1_i            : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt3_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt3_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt3_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt3_drpen_i                     : std_logic;
+    signal  gt3_drprdy_i                    : std_logic;
+    signal  gt3_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt3_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt3_eyescanreset_i              : std_logic;
+    signal  gt3_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt3_eyescandataerror_i          : std_logic;
+    signal  gt3_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt3_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt3_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt3_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt3_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt3_gtxrxn_i                    : std_logic;
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt3_rxlpmhfhold_i               : std_logic;
+    signal  gt3_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt3_rxdfelpmreset_i             : std_logic;
+    signal  gt3_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt3_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt3_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt3_gtrxreset_i                 : std_logic;
+    signal  gt3_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt3_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt3_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt3_gttxreset_i                 : std_logic;
+    signal  gt3_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt3_txdlyen_i                   : std_logic;
+    signal  gt3_txdlysreset_i               : std_logic;
+    signal  gt3_txdlysresetdone_i           : std_logic;
+    signal  gt3_txphalign_i                 : std_logic;
+    signal  gt3_txphaligndone_i             : std_logic;
+    signal  gt3_txphalignen_i               : std_logic;
+    signal  gt3_txphdlyreset_i              : std_logic;
+    signal  gt3_txphinit_i                  : std_logic;
+    signal  gt3_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt3_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt3_gtxtxn_i                    : std_logic;
+    signal  gt3_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt3_txoutclk_i                  : std_logic;
+    signal  gt3_txoutclkfabric_i            : std_logic;
+    signal  gt3_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt3_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt3_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  gt1_tx_system_reset_c           : std_logic;
+    signal  gt1_rx_system_reset_c           : std_logic;
+    signal  gt2_tx_system_reset_c           : std_logic;
+    signal  gt2_rx_system_reset_c           : std_logic;
+    signal  gt3_tx_system_reset_c           : std_logic;
+    signal  gt3_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt1_txusrclk_i                  : std_logic; 
+    signal    gt1_txusrclk2_i                 : std_logic; 
+    signal    gt1_rxusrclk_i                  : std_logic; 
+    signal    gt1_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt2_txusrclk_i                  : std_logic; 
+    signal    gt2_txusrclk2_i                 : std_logic; 
+    signal    gt2_rxusrclk_i                  : std_logic; 
+    signal    gt2_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt3_txusrclk_i                  : std_logic; 
+    signal    gt3_txusrclk2_i                 : std_logic; 
+    signal    gt3_rxusrclk_i                  : std_logic; 
+    signal    gt3_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt0_txmmcm_lock_i               : std_logic;
+    signal    gt0_txmmcm_reset_i              : std_logic;
+    signal    gt0_rxmmcm_lock_i               : std_logic; 
+    signal    gt0_rxmmcm_reset_i              : std_logic;
+    signal    gt1_txmmcm_lock_i               : std_logic;
+    signal    gt1_txmmcm_reset_i              : std_logic;
+    signal    gt1_rxmmcm_lock_i               : std_logic; 
+    signal    gt1_rxmmcm_reset_i              : std_logic;
+    signal    gt2_txmmcm_lock_i               : std_logic;
+    signal    gt2_txmmcm_reset_i              : std_logic;
+    signal    gt2_rxmmcm_lock_i               : std_logic; 
+    signal    gt2_rxmmcm_reset_i              : std_logic;
+    signal    gt3_txmmcm_lock_i               : std_logic;
+    signal    gt3_txmmcm_reset_i              : std_logic;
+    signal    gt3_rxmmcm_lock_i               : std_logic; 
+    signal    gt3_rxmmcm_reset_i              : std_logic;
+    ----------------------------- Reference Clocks ----------------------------
+    
+signal    q3_clk1_refclk_i                : std_logic;
+    signal gt0_gtgrefclk_common_i : std_logic;
+    signal gt0_gtnorthrefclk0_common_i : std_logic;
+    signal gt0_gtnorthrefclk1_common_i : std_logic;
+    signal gt0_gtrefclk1_common_i : std_logic;
+    signal gt0_gtsouthrefclk0_common_i : std_logic;
+    signal gt0_gtsouthrefclk1_common_i : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+     GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i;
+    GT0_RX_MMCM_LOCK_OUT <= gt0_rxmmcm_lock_i;
+     GT1_TX_MMCM_LOCK_OUT <= gt1_txmmcm_lock_i;
+    GT1_RX_MMCM_LOCK_OUT <= gt1_rxmmcm_lock_i;
+     GT2_TX_MMCM_LOCK_OUT <= gt2_txmmcm_lock_i;
+    GT2_RX_MMCM_LOCK_OUT <= gt2_rxmmcm_lock_i;
+     GT3_TX_MMCM_LOCK_OUT <= gt3_txmmcm_lock_i;
+    GT3_RX_MMCM_LOCK_OUT <= gt3_rxmmcm_lock_i;
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+     gt0_qplloutclk_out <= gt0_qplloutclk_i;
+     gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+ 
+      GT1_TXUSRCLK_OUT <= gt1_txusrclk_i; 
+      GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
+      GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
+      GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
+ 
+      GT2_TXUSRCLK_OUT <= gt2_txusrclk_i; 
+      GT2_TXUSRCLK2_OUT <= gt2_txusrclk2_i;
+      GT2_RXUSRCLK_OUT <= gt2_rxusrclk_i;
+      GT2_RXUSRCLK2_OUT <= gt2_rxusrclk2_i;
+ 
+      GT3_TXUSRCLK_OUT <= gt3_txusrclk_i; 
+      GT3_TXUSRCLK2_OUT <= gt3_txusrclk2_i;
+      GT3_RXUSRCLK_OUT <= gt3_rxusrclk_i;
+      GT3_RXUSRCLK2_OUT <= gt3_rxusrclk2_i;
+
+
+    
+  
+    
+  
+    
+  
+    
+  
+    gt_usrclk_source : GTX_quadSODA_GT_USRCLK_SOURCE
+    port map
+   (
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_TXCLK_LOCK_OUT              =>      gt0_txmmcm_lock_i,
+        GT0_TX_MMCM_RESET_IN            =>      gt0_txmmcm_reset_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+        GT0_RXCLK_LOCK_OUT              =>      gt0_rxmmcm_lock_i,
+        GT0_RX_MMCM_RESET_IN            =>      gt0_rxmmcm_reset_i,
+ 
+        GT1_TXUSRCLK_OUT                =>      gt1_txusrclk_i,
+        GT1_TXUSRCLK2_OUT               =>      gt1_txusrclk2_i,
+        GT1_TXOUTCLK_IN                 =>      gt1_txoutclk_i,
+        GT1_TXCLK_LOCK_OUT              =>      gt1_txmmcm_lock_i,
+        GT1_TX_MMCM_RESET_IN            =>      gt1_txmmcm_reset_i,
+        GT1_RXUSRCLK_OUT                =>      gt1_rxusrclk_i,
+        GT1_RXUSRCLK2_OUT               =>      gt1_rxusrclk2_i,
+        GT1_RXCLK_LOCK_OUT              =>      gt1_rxmmcm_lock_i,
+        GT1_RX_MMCM_RESET_IN            =>      gt1_rxmmcm_reset_i,
+ 
+        GT2_TXUSRCLK_OUT                =>      gt2_txusrclk_i,
+        GT2_TXUSRCLK2_OUT               =>      gt2_txusrclk2_i,
+        GT2_TXOUTCLK_IN                 =>      gt2_txoutclk_i,
+        GT2_TXCLK_LOCK_OUT              =>      gt2_txmmcm_lock_i,
+        GT2_TX_MMCM_RESET_IN            =>      gt2_txmmcm_reset_i,
+        GT2_RXUSRCLK_OUT                =>      gt2_rxusrclk_i,
+        GT2_RXUSRCLK2_OUT               =>      gt2_rxusrclk2_i,
+        GT2_RXCLK_LOCK_OUT              =>      gt2_rxmmcm_lock_i,
+        GT2_RX_MMCM_RESET_IN            =>      gt2_rxmmcm_reset_i,
+ 
+        GT3_TXUSRCLK_OUT                =>      gt3_txusrclk_i,
+        GT3_TXUSRCLK2_OUT               =>      gt3_txusrclk2_i,
+        GT3_TXOUTCLK_IN                 =>      gt3_txoutclk_i,
+        GT3_TXCLK_LOCK_OUT              =>      gt3_txmmcm_lock_i,
+        GT3_TX_MMCM_RESET_IN            =>      gt3_txmmcm_reset_i,
+        GT3_RXUSRCLK_OUT                =>      gt3_rxusrclk_i,
+        GT3_RXUSRCLK2_OUT               =>      gt3_rxusrclk2_i,
+        GT3_RXCLK_LOCK_OUT              =>      gt3_rxmmcm_lock_i,
+        GT3_RX_MMCM_RESET_IN            =>      gt3_rxmmcm_reset_i,
+        Q3_CLK1_GTREFCLK_PAD_N_IN       =>      Q3_CLK1_GTREFCLK_PAD_N_IN,
+        Q3_CLK1_GTREFCLK_PAD_P_IN       =>      Q3_CLK1_GTREFCLK_PAD_P_IN,
+        Q3_CLK1_GTREFCLK_OUT            =>      q3_clk1_refclk_i
+
+    );
+
+sysclk_in_i <= sysclk_in;
+
+    common0_i:GTX_quadSODA_common 
+  generic map
+  (
+   WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+   SIM_QPLLREFCLK_SEL => "001"
+  )
+ port map
+   (
+    GTGREFCLK_IN      => gt0_gtgrefclk_common_i,
+    GTNORTHREFCLK0_IN => gt0_gtnorthrefclk0_common_i,
+    GTNORTHREFCLK1_IN => gt0_gtnorthrefclk1_common_i,
+    GTSOUTHREFCLK0_IN => gt0_gtsouthrefclk0_common_i,
+    GTSOUTHREFCLK1_IN => gt0_gtsouthrefclk1_common_i,
+    QPLLREFCLKSEL_IN    => "001",
+    GTREFCLK0_IN      => tied_to_ground_i,
+    GTREFCLK1_IN      => q3_clk1_refclk_i,
+    QPLLLOCK_OUT => gt0_qplllock_i,
+    QPLLLOCKDETCLK_IN => sysclk_in_i,
+    QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+    common_reset_i:GTX_quadSODA_common_reset 
+   generic map 
+   (
+      STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   )
+   port map
+   (    
+      STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET => soft_reset_tx_in,               --User Reset, can be pulled any time
+      COMMON_RESET => commonreset_i              --Reset QPLL
+   );
+
+
+    GTX_quadSODA_init_i : GTX_quadSODA
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_tx_in                =>      SOFT_RESET_TX_IN,
+        soft_reset_rx_in                =>      SOFT_RESET_RX_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_mmcm_lock_in             =>      gt0_txmmcm_lock_i,
+        gt0_tx_mmcm_reset_out           =>      gt0_txmmcm_reset_i,
+        gt0_rx_mmcm_lock_in             =>      gt0_rxmmcm_lock_i,
+        gt0_rx_mmcm_reset_out           =>      gt0_rxmmcm_reset_i,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+        gt1_tx_mmcm_lock_in             =>      gt1_txmmcm_lock_i,
+        gt1_tx_mmcm_reset_out           =>      gt1_txmmcm_reset_i,
+        gt1_rx_mmcm_lock_in             =>      gt1_rxmmcm_lock_i,
+        gt1_rx_mmcm_reset_out           =>      gt1_rxmmcm_reset_i,
+        gt1_tx_fsm_reset_done_out       =>      gt1_tx_fsm_reset_done_out,
+        gt1_rx_fsm_reset_done_out       =>      gt1_rx_fsm_reset_done_out,
+        gt1_data_valid_in               =>      gt1_data_valid_in,
+        gt2_tx_mmcm_lock_in             =>      gt2_txmmcm_lock_i,
+        gt2_tx_mmcm_reset_out           =>      gt2_txmmcm_reset_i,
+        gt2_rx_mmcm_lock_in             =>      gt2_rxmmcm_lock_i,
+        gt2_rx_mmcm_reset_out           =>      gt2_rxmmcm_reset_i,
+        gt2_tx_fsm_reset_done_out       =>      gt2_tx_fsm_reset_done_out,
+        gt2_rx_fsm_reset_done_out       =>      gt2_rx_fsm_reset_done_out,
+        gt2_data_valid_in               =>      gt2_data_valid_in,
+        gt3_tx_mmcm_lock_in             =>      gt3_txmmcm_lock_i,
+        gt3_tx_mmcm_reset_out           =>      gt3_txmmcm_reset_i,
+        gt3_rx_mmcm_lock_in             =>      gt3_rxmmcm_lock_i,
+        gt3_rx_mmcm_reset_out           =>      gt3_rxmmcm_reset_i,
+        gt3_tx_fsm_reset_done_out       =>      gt3_tx_fsm_reset_done_out,
+        gt3_rx_fsm_reset_done_out       =>      gt3_rx_fsm_reset_done_out,
+        gt3_data_valid_in               =>      gt3_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y12)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtgrefclk_in                =>      gt0_gtgrefclk_in,
+        gt0_gtnorthrefclk0_in           =>      gt0_gtnorthrefclk0_in,
+        gt0_gtnorthrefclk1_in           =>      gt0_gtnorthrefclk1_in,
+        gt0_gtrefclk0_in                =>      tied_to_ground_i,
+        gt0_gtrefclk1_in                =>      q3_clk1_refclk_i,
+        gt0_gtsouthrefclk0_in           =>      gt0_gtsouthrefclk0_in,
+        gt0_gtsouthrefclk1_in           =>      gt0_gtsouthrefclk1_in,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT1  (X1Y13)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt1_cpllfbclklost_out           =>      gt1_cpllfbclklost_out,
+        gt1_cplllock_out                =>      gt1_cplllock_out,
+        gt1_cplllockdetclk_in           =>      sysclk_in_i,
+        gt1_cpllreset_in                =>      gt1_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt1_gtgrefclk_in                =>      gt1_gtgrefclk_in,
+        gt1_gtnorthrefclk0_in           =>      gt1_gtnorthrefclk0_in,
+        gt1_gtnorthrefclk1_in           =>      gt1_gtnorthrefclk1_in,
+        gt1_gtrefclk0_in                =>      tied_to_ground_i,
+        gt1_gtrefclk1_in                =>      q3_clk1_refclk_i,
+        gt1_gtsouthrefclk0_in           =>      gt1_gtsouthrefclk0_in,
+        gt1_gtsouthrefclk1_in           =>      gt1_gtsouthrefclk1_in,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt1_drpaddr_in                  =>      gt1_drpaddr_in,
+        gt1_drpclk_in                   =>      sysclk_in_i,
+        gt1_drpdi_in                    =>      gt1_drpdi_in,
+        gt1_drpdo_out                   =>      gt1_drpdo_out,
+        gt1_drpen_in                    =>      gt1_drpen_in,
+        gt1_drprdy_out                  =>      gt1_drprdy_out,
+        gt1_drpwe_in                    =>      gt1_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt1_dmonitorout_out             =>      gt1_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt1_eyescanreset_in             =>      gt1_eyescanreset_in,
+        gt1_rxuserrdy_in                =>      gt1_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt1_eyescandataerror_out        =>      gt1_eyescandataerror_out,
+        gt1_eyescantrigger_in           =>      gt1_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt1_rxusrclk_in                 =>      gt1_rxusrclk_i,
+        gt1_rxusrclk2_in                =>      gt1_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt1_rxdata_out                  =>      gt1_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt1_rxdisperr_out               =>      gt1_rxdisperr_out,
+        gt1_rxnotintable_out            =>      gt1_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt1_gtxrxp_in                   =>      gt1_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt1_gtxrxn_in                   =>      gt1_gtxrxn_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt1_rxdfelpmreset_in            =>      gt1_rxdfelpmreset_in,
+        gt1_rxmonitorout_out            =>      gt1_rxmonitorout_out,
+        gt1_rxmonitorsel_in             =>      gt1_rxmonitorsel_in,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt1_gtrxreset_in                =>      gt1_gtrxreset_in,
+        gt1_rxpmareset_in               =>      gt1_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt1_rxcharisk_out               =>      gt1_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt1_rxresetdone_out             =>      gt1_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt1_gttxreset_in                =>      gt1_gttxreset_in,
+        gt1_txuserrdy_in                =>      gt1_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt1_txusrclk_in                 =>      gt1_txusrclk_i,
+        gt1_txusrclk2_in                =>      gt1_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt1_txdata_in                   =>      gt1_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt1_gtxtxn_out                  =>      gt1_gtxtxn_out,
+        gt1_gtxtxp_out                  =>      gt1_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt1_txoutclk_out                =>      gt1_txoutclk_i,
+        gt1_txoutclkfabric_out          =>      gt1_txoutclkfabric_out,
+        gt1_txoutclkpcs_out             =>      gt1_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt1_txcharisk_in                =>      gt1_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt1_txresetdone_out             =>      gt1_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT2  (X1Y14)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt2_cpllfbclklost_out           =>      gt2_cpllfbclklost_out,
+        gt2_cplllock_out                =>      gt2_cplllock_out,
+        gt2_cplllockdetclk_in           =>      sysclk_in_i,
+        gt2_cpllreset_in                =>      gt2_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt2_gtgrefclk_in                =>      gt2_gtgrefclk_in,
+        gt2_gtnorthrefclk0_in           =>      gt2_gtnorthrefclk0_in,
+        gt2_gtnorthrefclk1_in           =>      gt2_gtnorthrefclk1_in,
+        gt2_gtrefclk0_in                =>      tied_to_ground_i,
+        gt2_gtrefclk1_in                =>      q3_clk1_refclk_i,
+        gt2_gtsouthrefclk0_in           =>      gt2_gtsouthrefclk0_in,
+        gt2_gtsouthrefclk1_in           =>      gt2_gtsouthrefclk1_in,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt2_drpaddr_in                  =>      gt2_drpaddr_in,
+        gt2_drpclk_in                   =>      sysclk_in_i,
+        gt2_drpdi_in                    =>      gt2_drpdi_in,
+        gt2_drpdo_out                   =>      gt2_drpdo_out,
+        gt2_drpen_in                    =>      gt2_drpen_in,
+        gt2_drprdy_out                  =>      gt2_drprdy_out,
+        gt2_drpwe_in                    =>      gt2_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt2_dmonitorout_out             =>      gt2_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt2_eyescanreset_in             =>      gt2_eyescanreset_in,
+        gt2_rxuserrdy_in                =>      gt2_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt2_eyescandataerror_out        =>      gt2_eyescandataerror_out,
+        gt2_eyescantrigger_in           =>      gt2_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt2_rxusrclk_in                 =>      gt2_rxusrclk_i,
+        gt2_rxusrclk2_in                =>      gt2_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt2_rxdata_out                  =>      gt2_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt2_rxdisperr_out               =>      gt2_rxdisperr_out,
+        gt2_rxnotintable_out            =>      gt2_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt2_gtxrxp_in                   =>      gt2_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt2_gtxrxn_in                   =>      gt2_gtxrxn_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt2_rxdfelpmreset_in            =>      gt2_rxdfelpmreset_in,
+        gt2_rxmonitorout_out            =>      gt2_rxmonitorout_out,
+        gt2_rxmonitorsel_in             =>      gt2_rxmonitorsel_in,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt2_gtrxreset_in                =>      gt2_gtrxreset_in,
+        gt2_rxpmareset_in               =>      gt2_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt2_rxcharisk_out               =>      gt2_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt2_rxresetdone_out             =>      gt2_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt2_gttxreset_in                =>      gt2_gttxreset_in,
+        gt2_txuserrdy_in                =>      gt2_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt2_txusrclk_in                 =>      gt2_txusrclk_i,
+        gt2_txusrclk2_in                =>      gt2_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt2_txdata_in                   =>      gt2_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt2_gtxtxn_out                  =>      gt2_gtxtxn_out,
+        gt2_gtxtxp_out                  =>      gt2_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt2_txoutclk_out                =>      gt2_txoutclk_i,
+        gt2_txoutclkfabric_out          =>      gt2_txoutclkfabric_out,
+        gt2_txoutclkpcs_out             =>      gt2_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt2_txcharisk_in                =>      gt2_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt2_txresetdone_out             =>      gt2_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT3  (X1Y15)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt3_cpllfbclklost_out           =>      gt3_cpllfbclklost_out,
+        gt3_cplllock_out                =>      gt3_cplllock_out,
+        gt3_cplllockdetclk_in           =>      sysclk_in_i,
+        gt3_cpllreset_in                =>      gt3_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt3_gtgrefclk_in                =>      gt3_gtgrefclk_in,
+        gt3_gtnorthrefclk0_in           =>      gt3_gtnorthrefclk0_in,
+        gt3_gtnorthrefclk1_in           =>      gt3_gtnorthrefclk1_in,
+        gt3_gtrefclk0_in                =>      tied_to_ground_i,
+        gt3_gtrefclk1_in                =>      q3_clk1_refclk_i,
+        gt3_gtsouthrefclk0_in           =>      gt3_gtsouthrefclk0_in,
+        gt3_gtsouthrefclk1_in           =>      gt3_gtsouthrefclk1_in,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt3_drpaddr_in                  =>      gt3_drpaddr_in,
+        gt3_drpclk_in                   =>      sysclk_in_i,
+        gt3_drpdi_in                    =>      gt3_drpdi_in,
+        gt3_drpdo_out                   =>      gt3_drpdo_out,
+        gt3_drpen_in                    =>      gt3_drpen_in,
+        gt3_drprdy_out                  =>      gt3_drprdy_out,
+        gt3_drpwe_in                    =>      gt3_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt3_dmonitorout_out             =>      gt3_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt3_eyescanreset_in             =>      gt3_eyescanreset_in,
+        gt3_rxuserrdy_in                =>      gt3_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt3_eyescandataerror_out        =>      gt3_eyescandataerror_out,
+        gt3_eyescantrigger_in           =>      gt3_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt3_rxusrclk_in                 =>      gt3_rxusrclk_i,
+        gt3_rxusrclk2_in                =>      gt3_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt3_rxdata_out                  =>      gt3_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt3_rxdisperr_out               =>      gt3_rxdisperr_out,
+        gt3_rxnotintable_out            =>      gt3_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt3_gtxrxp_in                   =>      gt3_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt3_gtxrxn_in                   =>      gt3_gtxrxn_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt3_rxdfelpmreset_in            =>      gt3_rxdfelpmreset_in,
+        gt3_rxmonitorout_out            =>      gt3_rxmonitorout_out,
+        gt3_rxmonitorsel_in             =>      gt3_rxmonitorsel_in,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt3_gtrxreset_in                =>      gt3_gtrxreset_in,
+        gt3_rxpmareset_in               =>      gt3_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt3_rxcharisk_out               =>      gt3_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt3_rxresetdone_out             =>      gt3_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt3_gttxreset_in                =>      gt3_gttxreset_in,
+        gt3_txuserrdy_in                =>      gt3_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt3_txusrclk_in                 =>      gt3_txusrclk_i,
+        gt3_txusrclk2_in                =>      gt3_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt3_txdata_in                   =>      gt3_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt3_gtxtxn_out                  =>      gt3_gtxtxn_out,
+        gt3_gtxtxp_out                  =>      gt3_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt3_txoutclk_out                =>      gt3_txoutclk_i,
+        gt3_txoutclkfabric_out          =>      gt3_txoutclkfabric_out,
+        gt3_txoutclkpcs_out             =>      gt3_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt3_txcharisk_in                =>      gt3_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt3_txresetdone_out             =>      gt3_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/GTX_quadSODA_wrapper_old2.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/GTX_quadSODA_wrapper_old2.vhd
new file mode 100644
index 0000000..5814ab1
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/GTX_quadSODA_wrapper_old2.vhd
@@ -0,0 +1,1593 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_quadsoda_support.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_quadSODA_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_quadSODA_wrapper is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 10  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+    GT2_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_DATA_VALID_IN                       : in   std_logic;
+    GT3_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_DATA_VALID_IN                       : in   std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT1_TXUSRCLK_OUT                        : out  std_logic;
+    GT1_TXUSRCLK2_OUT                       : out  std_logic;
+    GT1_RXUSRCLK_OUT                        : out  std_logic;
+    GT1_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT2_TXUSRCLK_OUT                        : out  std_logic;
+    GT2_TXUSRCLK2_OUT                       : out  std_logic;
+    GT2_RXUSRCLK_OUT                        : out  std_logic;
+    GT2_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT3_TXUSRCLK_OUT                        : out  std_logic;
+    GT3_TXUSRCLK2_OUT                       : out  std_logic;
+    GT3_RXUSRCLK_OUT                        : out  std_logic;
+    GT3_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+
+    --GT2  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt2_cpllfbclklost_out                   : out  std_logic;
+    gt2_cplllock_out                        : out  std_logic;
+    gt2_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt2_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt2_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt2_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt2_drpen_in                            : in   std_logic;
+    gt2_drprdy_out                          : out  std_logic;
+    gt2_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt2_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt2_eyescanreset_in                     : in   std_logic;
+    gt2_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt2_eyescandataerror_out                : out  std_logic;
+    gt2_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt2_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt2_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt2_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt2_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt2_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt2_rxdfelpmreset_in                    : in   std_logic;
+    gt2_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt2_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt2_gtrxreset_in                        : in   std_logic;
+    gt2_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt2_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt2_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt2_gttxreset_in                        : in   std_logic;
+    gt2_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt2_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt2_gtxtxn_out                          : out  std_logic;
+    gt2_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt2_txoutclkfabric_out                  : out  std_logic;
+    gt2_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt2_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt2_txresetdone_out                     : out  std_logic;
+
+    --GT3  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt3_cpllfbclklost_out                   : out  std_logic;
+    gt3_cplllock_out                        : out  std_logic;
+    gt3_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt3_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt3_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt3_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt3_drpen_in                            : in   std_logic;
+    gt3_drprdy_out                          : out  std_logic;
+    gt3_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt3_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt3_eyescanreset_in                     : in   std_logic;
+    gt3_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt3_eyescandataerror_out                : out  std_logic;
+    gt3_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt3_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt3_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt3_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt3_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt3_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt3_rxdfelpmreset_in                    : in   std_logic;
+    gt3_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt3_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt3_gtrxreset_in                        : in   std_logic;
+    gt3_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt3_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt3_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt3_gttxreset_in                        : in   std_logic;
+    gt3_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt3_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt3_gtxtxn_out                          : out  std_logic;
+    gt3_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt3_txoutclkfabric_out                  : out  std_logic;
+    gt3_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt3_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt3_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT  : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT : out std_logic;
+       sysclk_in        : in std_logic
+
+);
+
+end GTX_quadSODA_wrapper;
+    
+architecture RTL of GTX_quadSODA_wrapper is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_quadSODA
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+    GT2_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_DATA_VALID_IN                       : in   std_logic;
+    GT3_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_DATA_VALID_IN                       : in   std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cplllockdetclk_in                   : in   std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt1_gtrefclk0_in                        : in   std_logic;
+    gt1_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpclk_in                           : in   std_logic;
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt1_rxusrclk_in                         : in   std_logic;
+    gt1_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt1_txusrclk_in                         : in   std_logic;
+    gt1_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclk_out                        : out  std_logic;
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+
+    --GT2  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt2_cpllfbclklost_out                   : out  std_logic;
+    gt2_cplllock_out                        : out  std_logic;
+    gt2_cplllockdetclk_in                   : in   std_logic;
+    gt2_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt2_gtrefclk0_in                        : in   std_logic;
+    gt2_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt2_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt2_drpclk_in                           : in   std_logic;
+    gt2_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt2_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt2_drpen_in                            : in   std_logic;
+    gt2_drprdy_out                          : out  std_logic;
+    gt2_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt2_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt2_eyescanreset_in                     : in   std_logic;
+    gt2_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt2_eyescandataerror_out                : out  std_logic;
+    gt2_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt2_rxusrclk_in                         : in   std_logic;
+    gt2_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt2_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt2_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt2_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt2_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt2_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt2_rxdfelpmreset_in                    : in   std_logic;
+    gt2_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt2_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt2_gtrxreset_in                        : in   std_logic;
+    gt2_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt2_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt2_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt2_gttxreset_in                        : in   std_logic;
+    gt2_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt2_txusrclk_in                         : in   std_logic;
+    gt2_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt2_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt2_gtxtxn_out                          : out  std_logic;
+    gt2_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt2_txoutclk_out                        : out  std_logic;
+    gt2_txoutclkfabric_out                  : out  std_logic;
+    gt2_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt2_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt2_txresetdone_out                     : out  std_logic;
+
+    --GT3  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt3_cpllfbclklost_out                   : out  std_logic;
+    gt3_cplllock_out                        : out  std_logic;
+    gt3_cplllockdetclk_in                   : in   std_logic;
+    gt3_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt3_gtrefclk0_in                        : in   std_logic;
+    gt3_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt3_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt3_drpclk_in                           : in   std_logic;
+    gt3_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt3_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt3_drpen_in                            : in   std_logic;
+    gt3_drprdy_out                          : out  std_logic;
+    gt3_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt3_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt3_eyescanreset_in                     : in   std_logic;
+    gt3_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt3_eyescandataerror_out                : out  std_logic;
+    gt3_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt3_rxusrclk_in                         : in   std_logic;
+    gt3_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt3_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt3_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt3_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt3_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt3_gtxrxn_in                           : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt3_rxdfelpmreset_in                    : in   std_logic;
+    gt3_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt3_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt3_gtrxreset_in                        : in   std_logic;
+    gt3_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt3_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt3_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt3_gttxreset_in                        : in   std_logic;
+    gt3_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt3_txusrclk_in                         : in   std_logic;
+    gt3_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt3_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt3_gtxtxn_out                          : out  std_logic;
+    gt3_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt3_txoutclk_out                        : out  std_logic;
+    gt3_txoutclkfabric_out                  : out  std_logic;
+    gt3_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt3_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt3_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_quadSODA_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component GTX_quadSODA_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE" ;       -- Set to "TRUE" to speed up sim reset
+    SIM_QPLLREFCLK_SEL              :bit_vector  := "001"
+ 
+);
+port
+(
+    QPLLREFCLKSEL_IN   : in std_logic_vector(2 downto 0);
+    GTREFCLK0_IN : in std_logic;
+    GTREFCLK1_IN      : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_quadSODA_GT_USRCLK_SOURCE 
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+ 
+    GT1_TXUSRCLK_OUT             : out std_logic;
+    GT1_TXUSRCLK2_OUT            : out std_logic;
+    GT1_TXOUTCLK_IN              : in  std_logic;
+    GT1_RXUSRCLK_OUT             : out std_logic;
+    GT1_RXUSRCLK2_OUT            : out std_logic;
+ 
+    GT2_TXUSRCLK_OUT             : out std_logic;
+    GT2_TXUSRCLK2_OUT            : out std_logic;
+    GT2_TXOUTCLK_IN              : in  std_logic;
+    GT2_RXUSRCLK_OUT             : out std_logic;
+    GT2_RXUSRCLK2_OUT            : out std_logic;
+ 
+    GT3_TXUSRCLK_OUT             : out std_logic;
+    GT3_TXUSRCLK2_OUT            : out std_logic;
+    GT3_TXOUTCLK_IN              : in  std_logic;
+    GT3_RXUSRCLK_OUT             : out std_logic;
+    GT3_RXUSRCLK2_OUT            : out std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_OUT                    : out  std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+    signal   gt1_txfsmresetdone_i            : std_logic;
+signal   gt1_rxfsmresetdone_i            : std_logic;
+    signal   gt1_txfsmresetdone_r            : std_logic;
+    signal   gt1_txfsmresetdone_r2           : std_logic;
+signal   gt1_rxresetdone_r               : std_logic;
+signal   gt1_rxresetdone_r2              : std_logic;
+signal   gt1_rxresetdone_r3              : std_logic;
+
+
+    signal   gt2_txfsmresetdone_i            : std_logic;
+signal   gt2_rxfsmresetdone_i            : std_logic;
+    signal   gt2_txfsmresetdone_r            : std_logic;
+    signal   gt2_txfsmresetdone_r2           : std_logic;
+signal   gt2_rxresetdone_r               : std_logic;
+signal   gt2_rxresetdone_r2              : std_logic;
+signal   gt2_rxresetdone_r3              : std_logic;
+
+
+    signal   gt3_txfsmresetdone_i            : std_logic;
+signal   gt3_rxfsmresetdone_i            : std_logic;
+    signal   gt3_txfsmresetdone_r            : std_logic;
+    signal   gt3_txfsmresetdone_r2           : std_logic;
+signal   gt3_rxresetdone_r               : std_logic;
+signal   gt3_rxresetdone_r2              : std_logic;
+signal   gt3_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y12)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt0_txdlyen_i                   : std_logic;
+    signal  gt0_txdlysreset_i               : std_logic;
+    signal  gt0_txdlysresetdone_i           : std_logic;
+    signal  gt0_txphalign_i                 : std_logic;
+    signal  gt0_txphaligndone_i             : std_logic;
+    signal  gt0_txphalignen_i               : std_logic;
+    signal  gt0_txphdlyreset_i              : std_logic;
+    signal  gt0_txphinit_i                  : std_logic;
+    signal  gt0_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT1  (X1Y13)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt1_cpllfbclklost_i             : std_logic;
+    signal  gt1_cplllock_i                  : std_logic;
+    signal  gt1_cpllrefclklost_i            : std_logic;
+    signal  gt1_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt1_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt1_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt1_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt1_drpen_i                     : std_logic;
+    signal  gt1_drprdy_i                    : std_logic;
+    signal  gt1_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt1_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt1_eyescanreset_i              : std_logic;
+    signal  gt1_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt1_eyescandataerror_i          : std_logic;
+    signal  gt1_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt1_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt1_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt1_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt1_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt1_gtxrxn_i                    : std_logic;
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt1_rxlpmhfhold_i               : std_logic;
+    signal  gt1_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt1_rxdfelpmreset_i             : std_logic;
+    signal  gt1_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt1_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt1_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt1_gtrxreset_i                 : std_logic;
+    signal  gt1_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt1_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt1_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt1_gttxreset_i                 : std_logic;
+    signal  gt1_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt1_txdlyen_i                   : std_logic;
+    signal  gt1_txdlysreset_i               : std_logic;
+    signal  gt1_txdlysresetdone_i           : std_logic;
+    signal  gt1_txphalign_i                 : std_logic;
+    signal  gt1_txphaligndone_i             : std_logic;
+    signal  gt1_txphalignen_i               : std_logic;
+    signal  gt1_txphdlyreset_i              : std_logic;
+    signal  gt1_txphinit_i                  : std_logic;
+    signal  gt1_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt1_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt1_gtxtxn_i                    : std_logic;
+    signal  gt1_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt1_txoutclk_i                  : std_logic;
+    signal  gt1_txoutclkfabric_i            : std_logic;
+    signal  gt1_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt1_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt1_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT2  (X1Y14)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt2_cpllfbclklost_i             : std_logic;
+    signal  gt2_cplllock_i                  : std_logic;
+    signal  gt2_cpllrefclklost_i            : std_logic;
+    signal  gt2_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt2_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt2_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt2_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt2_drpen_i                     : std_logic;
+    signal  gt2_drprdy_i                    : std_logic;
+    signal  gt2_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt2_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt2_eyescanreset_i              : std_logic;
+    signal  gt2_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt2_eyescandataerror_i          : std_logic;
+    signal  gt2_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt2_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt2_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt2_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt2_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt2_gtxrxn_i                    : std_logic;
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt2_rxlpmhfhold_i               : std_logic;
+    signal  gt2_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt2_rxdfelpmreset_i             : std_logic;
+    signal  gt2_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt2_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt2_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt2_gtrxreset_i                 : std_logic;
+    signal  gt2_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt2_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt2_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt2_gttxreset_i                 : std_logic;
+    signal  gt2_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt2_txdlyen_i                   : std_logic;
+    signal  gt2_txdlysreset_i               : std_logic;
+    signal  gt2_txdlysresetdone_i           : std_logic;
+    signal  gt2_txphalign_i                 : std_logic;
+    signal  gt2_txphaligndone_i             : std_logic;
+    signal  gt2_txphalignen_i               : std_logic;
+    signal  gt2_txphdlyreset_i              : std_logic;
+    signal  gt2_txphinit_i                  : std_logic;
+    signal  gt2_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt2_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt2_gtxtxn_i                    : std_logic;
+    signal  gt2_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt2_txoutclk_i                  : std_logic;
+    signal  gt2_txoutclkfabric_i            : std_logic;
+    signal  gt2_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt2_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt2_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT3  (X1Y15)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt3_cpllfbclklost_i             : std_logic;
+    signal  gt3_cplllock_i                  : std_logic;
+    signal  gt3_cpllrefclklost_i            : std_logic;
+    signal  gt3_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt3_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt3_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt3_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt3_drpen_i                     : std_logic;
+    signal  gt3_drprdy_i                    : std_logic;
+    signal  gt3_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt3_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt3_eyescanreset_i              : std_logic;
+    signal  gt3_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt3_eyescandataerror_i          : std_logic;
+    signal  gt3_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt3_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt3_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt3_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt3_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt3_gtxrxn_i                    : std_logic;
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt3_rxlpmhfhold_i               : std_logic;
+    signal  gt3_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt3_rxdfelpmreset_i             : std_logic;
+    signal  gt3_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt3_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt3_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt3_gtrxreset_i                 : std_logic;
+    signal  gt3_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt3_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt3_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt3_gttxreset_i                 : std_logic;
+    signal  gt3_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt3_txdlyen_i                   : std_logic;
+    signal  gt3_txdlysreset_i               : std_logic;
+    signal  gt3_txdlysresetdone_i           : std_logic;
+    signal  gt3_txphalign_i                 : std_logic;
+    signal  gt3_txphaligndone_i             : std_logic;
+    signal  gt3_txphalignen_i               : std_logic;
+    signal  gt3_txphdlyreset_i              : std_logic;
+    signal  gt3_txphinit_i                  : std_logic;
+    signal  gt3_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt3_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt3_gtxtxn_i                    : std_logic;
+    signal  gt3_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt3_txoutclk_i                  : std_logic;
+    signal  gt3_txoutclkfabric_i            : std_logic;
+    signal  gt3_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt3_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt3_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  gt1_tx_system_reset_c           : std_logic;
+    signal  gt1_rx_system_reset_c           : std_logic;
+    signal  gt2_tx_system_reset_c           : std_logic;
+    signal  gt2_rx_system_reset_c           : std_logic;
+    signal  gt3_tx_system_reset_c           : std_logic;
+    signal  gt3_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt1_txusrclk_i                  : std_logic; 
+    signal    gt1_txusrclk2_i                 : std_logic; 
+    signal    gt1_rxusrclk_i                  : std_logic; 
+    signal    gt1_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt2_txusrclk_i                  : std_logic; 
+    signal    gt2_txusrclk2_i                 : std_logic; 
+    signal    gt2_rxusrclk_i                  : std_logic; 
+    signal    gt2_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt3_txusrclk_i                  : std_logic; 
+    signal    gt3_txusrclk2_i                 : std_logic; 
+    signal    gt3_rxusrclk_i                  : std_logic; 
+    signal    gt3_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    ----------------------------- Reference Clocks ----------------------------
+    
+signal    q2_clk1_refclk_i                : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+     gt0_qplloutclk_out <= gt0_qplloutclk_i;
+     gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+ 
+      GT1_TXUSRCLK_OUT <= gt1_txusrclk_i; 
+      GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
+      GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
+      GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
+ 
+      GT2_TXUSRCLK_OUT <= gt2_txusrclk_i; 
+      GT2_TXUSRCLK2_OUT <= gt2_txusrclk2_i;
+      GT2_RXUSRCLK_OUT <= gt2_rxusrclk_i;
+      GT2_RXUSRCLK2_OUT <= gt2_rxusrclk2_i;
+ 
+      GT3_TXUSRCLK_OUT <= gt3_txusrclk_i; 
+      GT3_TXUSRCLK2_OUT <= gt3_txusrclk2_i;
+      GT3_RXUSRCLK_OUT <= gt3_rxusrclk_i;
+      GT3_RXUSRCLK2_OUT <= gt3_rxusrclk2_i;
+
+
+    
+  
+    
+  
+    
+  
+    
+  
+    gt_usrclk_source : GTX_quadSODA_GT_USRCLK_SOURCE
+    port map
+   (
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+ 
+        GT1_TXUSRCLK_OUT                =>      gt1_txusrclk_i,
+        GT1_TXUSRCLK2_OUT               =>      gt1_txusrclk2_i,
+        GT1_TXOUTCLK_IN                 =>      gt1_txoutclk_i,
+        GT1_RXUSRCLK_OUT                =>      gt1_rxusrclk_i,
+        GT1_RXUSRCLK2_OUT               =>      gt1_rxusrclk2_i,
+ 
+        GT2_TXUSRCLK_OUT                =>      gt2_txusrclk_i,
+        GT2_TXUSRCLK2_OUT               =>      gt2_txusrclk2_i,
+        GT2_TXOUTCLK_IN                 =>      gt2_txoutclk_i,
+        GT2_RXUSRCLK_OUT                =>      gt2_rxusrclk_i,
+        GT2_RXUSRCLK2_OUT               =>      gt2_rxusrclk2_i,
+ 
+        GT3_TXUSRCLK_OUT                =>      gt3_txusrclk_i,
+        GT3_TXUSRCLK2_OUT               =>      gt3_txusrclk2_i,
+        GT3_TXOUTCLK_IN                 =>      gt3_txoutclk_i,
+        GT3_RXUSRCLK_OUT                =>      gt3_rxusrclk_i,
+        GT3_RXUSRCLK2_OUT               =>      gt3_rxusrclk2_i,
+        Q2_CLK1_GTREFCLK_PAD_N_IN       =>      Q2_CLK1_GTREFCLK_PAD_N_IN,
+        Q2_CLK1_GTREFCLK_PAD_P_IN       =>      Q2_CLK1_GTREFCLK_PAD_P_IN,
+        Q2_CLK1_GTREFCLK_OUT            =>      q2_clk1_refclk_i
+
+    );
+
+sysclk_in_i <= sysclk_in;
+
+    common0_i:GTX_quadSODA_common 
+  generic map
+  (
+   WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+   SIM_QPLLREFCLK_SEL => "001"
+  )
+ port map
+   (
+    QPLLREFCLKSEL_IN    => "001",
+    GTREFCLK0_IN      => tied_to_ground_i,
+    GTREFCLK1_IN      => q2_clk1_refclk_i,
+    QPLLLOCK_OUT => gt0_qplllock_i,
+    QPLLLOCKDETCLK_IN => sysclk_in_i,
+    QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+    common_reset_i:GTX_quadSODA_common_reset 
+   generic map 
+   (
+      STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   )
+   port map
+   (    
+      STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET => soft_reset_tx_in,               --User Reset, can be pulled any time
+      COMMON_RESET => commonreset_i              --Reset QPLL
+   );
+
+
+    GTX_quadSODA_init_i : GTX_quadSODA
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_tx_in                =>      SOFT_RESET_TX_IN,
+        soft_reset_rx_in                =>      SOFT_RESET_RX_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+        gt1_tx_fsm_reset_done_out       =>      gt1_tx_fsm_reset_done_out,
+        gt1_rx_fsm_reset_done_out       =>      gt1_rx_fsm_reset_done_out,
+        gt1_data_valid_in               =>      gt1_data_valid_in,
+        gt2_tx_fsm_reset_done_out       =>      gt2_tx_fsm_reset_done_out,
+        gt2_rx_fsm_reset_done_out       =>      gt2_rx_fsm_reset_done_out,
+        gt2_data_valid_in               =>      gt2_data_valid_in,
+        gt3_tx_fsm_reset_done_out       =>      gt3_tx_fsm_reset_done_out,
+        gt3_rx_fsm_reset_done_out       =>      gt3_rx_fsm_reset_done_out,
+        gt3_data_valid_in               =>      gt3_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y12)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      tied_to_ground_i,
+        gt0_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT1  (X1Y13)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt1_cpllfbclklost_out           =>      gt1_cpllfbclklost_out,
+        gt1_cplllock_out                =>      gt1_cplllock_out,
+        gt1_cplllockdetclk_in           =>      sysclk_in_i,
+        gt1_cpllreset_in                =>      gt1_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt1_gtrefclk0_in                =>      tied_to_ground_i,
+        gt1_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt1_drpaddr_in                  =>      gt1_drpaddr_in,
+        gt1_drpclk_in                   =>      sysclk_in_i,
+        gt1_drpdi_in                    =>      gt1_drpdi_in,
+        gt1_drpdo_out                   =>      gt1_drpdo_out,
+        gt1_drpen_in                    =>      gt1_drpen_in,
+        gt1_drprdy_out                  =>      gt1_drprdy_out,
+        gt1_drpwe_in                    =>      gt1_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt1_dmonitorout_out             =>      gt1_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt1_eyescanreset_in             =>      gt1_eyescanreset_in,
+        gt1_rxuserrdy_in                =>      gt1_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt1_eyescandataerror_out        =>      gt1_eyescandataerror_out,
+        gt1_eyescantrigger_in           =>      gt1_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt1_rxusrclk_in                 =>      gt1_rxusrclk_i,
+        gt1_rxusrclk2_in                =>      gt1_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt1_rxdata_out                  =>      gt1_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt1_rxdisperr_out               =>      gt1_rxdisperr_out,
+        gt1_rxnotintable_out            =>      gt1_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt1_gtxrxp_in                   =>      gt1_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt1_gtxrxn_in                   =>      gt1_gtxrxn_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt1_rxdfelpmreset_in            =>      gt1_rxdfelpmreset_in,
+        gt1_rxmonitorout_out            =>      gt1_rxmonitorout_out,
+        gt1_rxmonitorsel_in             =>      gt1_rxmonitorsel_in,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt1_gtrxreset_in                =>      gt1_gtrxreset_in,
+        gt1_rxpmareset_in               =>      gt1_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt1_rxcharisk_out               =>      gt1_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt1_rxresetdone_out             =>      gt1_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt1_gttxreset_in                =>      gt1_gttxreset_in,
+        gt1_txuserrdy_in                =>      gt1_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt1_txusrclk_in                 =>      gt1_txusrclk_i,
+        gt1_txusrclk2_in                =>      gt1_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt1_txdata_in                   =>      gt1_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt1_gtxtxn_out                  =>      gt1_gtxtxn_out,
+        gt1_gtxtxp_out                  =>      gt1_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt1_txoutclk_out                =>      gt1_txoutclk_i,
+        gt1_txoutclkfabric_out          =>      gt1_txoutclkfabric_out,
+        gt1_txoutclkpcs_out             =>      gt1_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt1_txcharisk_in                =>      gt1_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt1_txresetdone_out             =>      gt1_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT2  (X1Y14)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt2_cpllfbclklost_out           =>      gt2_cpllfbclklost_out,
+        gt2_cplllock_out                =>      gt2_cplllock_out,
+        gt2_cplllockdetclk_in           =>      sysclk_in_i,
+        gt2_cpllreset_in                =>      gt2_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt2_gtrefclk0_in                =>      tied_to_ground_i,
+        gt2_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt2_drpaddr_in                  =>      gt2_drpaddr_in,
+        gt2_drpclk_in                   =>      sysclk_in_i,
+        gt2_drpdi_in                    =>      gt2_drpdi_in,
+        gt2_drpdo_out                   =>      gt2_drpdo_out,
+        gt2_drpen_in                    =>      gt2_drpen_in,
+        gt2_drprdy_out                  =>      gt2_drprdy_out,
+        gt2_drpwe_in                    =>      gt2_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt2_dmonitorout_out             =>      gt2_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt2_eyescanreset_in             =>      gt2_eyescanreset_in,
+        gt2_rxuserrdy_in                =>      gt2_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt2_eyescandataerror_out        =>      gt2_eyescandataerror_out,
+        gt2_eyescantrigger_in           =>      gt2_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt2_rxusrclk_in                 =>      gt2_rxusrclk_i,
+        gt2_rxusrclk2_in                =>      gt2_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt2_rxdata_out                  =>      gt2_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt2_rxdisperr_out               =>      gt2_rxdisperr_out,
+        gt2_rxnotintable_out            =>      gt2_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt2_gtxrxp_in                   =>      gt2_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt2_gtxrxn_in                   =>      gt2_gtxrxn_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt2_rxdfelpmreset_in            =>      gt2_rxdfelpmreset_in,
+        gt2_rxmonitorout_out            =>      gt2_rxmonitorout_out,
+        gt2_rxmonitorsel_in             =>      gt2_rxmonitorsel_in,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt2_gtrxreset_in                =>      gt2_gtrxreset_in,
+        gt2_rxpmareset_in               =>      gt2_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt2_rxcharisk_out               =>      gt2_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt2_rxresetdone_out             =>      gt2_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt2_gttxreset_in                =>      gt2_gttxreset_in,
+        gt2_txuserrdy_in                =>      gt2_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt2_txusrclk_in                 =>      gt2_txusrclk_i,
+        gt2_txusrclk2_in                =>      gt2_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt2_txdata_in                   =>      gt2_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt2_gtxtxn_out                  =>      gt2_gtxtxn_out,
+        gt2_gtxtxp_out                  =>      gt2_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt2_txoutclk_out                =>      gt2_txoutclk_i,
+        gt2_txoutclkfabric_out          =>      gt2_txoutclkfabric_out,
+        gt2_txoutclkpcs_out             =>      gt2_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt2_txcharisk_in                =>      gt2_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt2_txresetdone_out             =>      gt2_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT3  (X1Y15)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt3_cpllfbclklost_out           =>      gt3_cpllfbclklost_out,
+        gt3_cplllock_out                =>      gt3_cplllock_out,
+        gt3_cplllockdetclk_in           =>      sysclk_in_i,
+        gt3_cpllreset_in                =>      gt3_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt3_gtrefclk0_in                =>      tied_to_ground_i,
+        gt3_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt3_drpaddr_in                  =>      gt3_drpaddr_in,
+        gt3_drpclk_in                   =>      sysclk_in_i,
+        gt3_drpdi_in                    =>      gt3_drpdi_in,
+        gt3_drpdo_out                   =>      gt3_drpdo_out,
+        gt3_drpen_in                    =>      gt3_drpen_in,
+        gt3_drprdy_out                  =>      gt3_drprdy_out,
+        gt3_drpwe_in                    =>      gt3_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt3_dmonitorout_out             =>      gt3_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt3_eyescanreset_in             =>      gt3_eyescanreset_in,
+        gt3_rxuserrdy_in                =>      gt3_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt3_eyescandataerror_out        =>      gt3_eyescandataerror_out,
+        gt3_eyescantrigger_in           =>      gt3_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt3_rxusrclk_in                 =>      gt3_rxusrclk_i,
+        gt3_rxusrclk2_in                =>      gt3_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt3_rxdata_out                  =>      gt3_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt3_rxdisperr_out               =>      gt3_rxdisperr_out,
+        gt3_rxnotintable_out            =>      gt3_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt3_gtxrxp_in                   =>      gt3_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt3_gtxrxn_in                   =>      gt3_gtxrxn_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt3_rxdfelpmreset_in            =>      gt3_rxdfelpmreset_in,
+        gt3_rxmonitorout_out            =>      gt3_rxmonitorout_out,
+        gt3_rxmonitorsel_in             =>      gt3_rxmonitorsel_in,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt3_gtrxreset_in                =>      gt3_gtrxreset_in,
+        gt3_rxpmareset_in               =>      gt3_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt3_rxcharisk_out               =>      gt3_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt3_rxresetdone_out             =>      gt3_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt3_gttxreset_in                =>      gt3_gttxreset_in,
+        gt3_txuserrdy_in                =>      gt3_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt3_txusrclk_in                 =>      gt3_txusrclk_i,
+        gt3_txusrclk2_in                =>      gt3_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt3_txdata_in                   =>      gt3_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt3_gtxtxn_out                  =>      gt3_gtxtxn_out,
+        gt3_gtxtxp_out                  =>      gt3_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt3_txoutclk_out                =>      gt3_txoutclk_i,
+        gt3_txoutclkfabric_out          =>      gt3_txoutclkfabric_out,
+        gt3_txoutclkpcs_out             =>      gt3_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt3_txcharisk_in                =>      gt3_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt3_txresetdone_out             =>      gt3_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/GTX_quadSODA_wrapper_old3.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/GTX_quadSODA_wrapper_old3.vhd
new file mode 100644
index 0000000..e1e9c61
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/GTX_quadSODA_wrapper_old3.vhd
@@ -0,0 +1,1693 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_quadsoda_support.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_quadSODA_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_quadSODA_wrapper is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 10  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+    GT2_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_DATA_VALID_IN                       : in   std_logic;
+    GT3_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_DATA_VALID_IN                       : in   std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT1_TXUSRCLK_OUT                        : out  std_logic;
+    GT1_TXUSRCLK2_OUT                       : out  std_logic;
+    GT1_RXUSRCLK_OUT                        : out  std_logic;
+    GT1_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT2_TXUSRCLK_OUT                        : out  std_logic;
+    GT2_TXUSRCLK2_OUT                       : out  std_logic;
+    GT2_RXUSRCLK_OUT                        : out  std_logic;
+    GT2_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT3_TXUSRCLK_OUT                        : out  std_logic;
+    GT3_TXUSRCLK2_OUT                       : out  std_logic;
+    GT3_RXUSRCLK_OUT                        : out  std_logic;
+    GT3_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt1_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt1_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+
+    --GT2  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt2_cpllfbclklost_out                   : out  std_logic;
+    gt2_cplllock_out                        : out  std_logic;
+    gt2_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt2_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt2_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt2_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt2_drpen_in                            : in   std_logic;
+    gt2_drprdy_out                          : out  std_logic;
+    gt2_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt2_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt2_eyescanreset_in                     : in   std_logic;
+    gt2_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt2_eyescandataerror_out                : out  std_logic;
+    gt2_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt2_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt2_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt2_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt2_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt2_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt2_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt2_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt2_rxdfelpmreset_in                    : in   std_logic;
+    gt2_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt2_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt2_gtrxreset_in                        : in   std_logic;
+    gt2_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt2_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt2_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt2_gttxreset_in                        : in   std_logic;
+    gt2_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt2_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt2_gtxtxn_out                          : out  std_logic;
+    gt2_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt2_txoutclkfabric_out                  : out  std_logic;
+    gt2_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt2_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt2_txresetdone_out                     : out  std_logic;
+
+    --GT3  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt3_cpllfbclklost_out                   : out  std_logic;
+    gt3_cplllock_out                        : out  std_logic;
+    gt3_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt3_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt3_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt3_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt3_drpen_in                            : in   std_logic;
+    gt3_drprdy_out                          : out  std_logic;
+    gt3_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt3_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt3_eyescanreset_in                     : in   std_logic;
+    gt3_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt3_eyescandataerror_out                : out  std_logic;
+    gt3_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt3_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt3_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt3_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt3_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt3_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt3_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt3_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt3_rxdfelpmreset_in                    : in   std_logic;
+    gt3_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt3_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt3_gtrxreset_in                        : in   std_logic;
+    gt3_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt3_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt3_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt3_gttxreset_in                        : in   std_logic;
+    gt3_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt3_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt3_gtxtxn_out                          : out  std_logic;
+    gt3_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt3_txoutclkfabric_out                  : out  std_logic;
+    gt3_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt3_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt3_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT  : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT : out std_logic;
+       sysclk_in        : in std_logic
+
+);
+
+end GTX_quadSODA_wrapper;
+    
+architecture RTL of GTX_quadSODA_wrapper is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_quadSODA
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+    GT2_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_DATA_VALID_IN                       : in   std_logic;
+    GT3_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_DATA_VALID_IN                       : in   std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cplllockdetclk_in                   : in   std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt1_gtrefclk0_in                        : in   std_logic;
+    gt1_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpclk_in                           : in   std_logic;
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt1_rxusrclk_in                         : in   std_logic;
+    gt1_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt1_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt1_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt1_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt1_txusrclk_in                         : in   std_logic;
+    gt1_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclk_out                        : out  std_logic;
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+
+    --GT2  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt2_cpllfbclklost_out                   : out  std_logic;
+    gt2_cplllock_out                        : out  std_logic;
+    gt2_cplllockdetclk_in                   : in   std_logic;
+    gt2_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt2_gtrefclk0_in                        : in   std_logic;
+    gt2_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt2_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt2_drpclk_in                           : in   std_logic;
+    gt2_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt2_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt2_drpen_in                            : in   std_logic;
+    gt2_drprdy_out                          : out  std_logic;
+    gt2_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt2_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt2_eyescanreset_in                     : in   std_logic;
+    gt2_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt2_eyescandataerror_out                : out  std_logic;
+    gt2_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt2_rxusrclk_in                         : in   std_logic;
+    gt2_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt2_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt2_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt2_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt2_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt2_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt2_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt2_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt2_rxdfelpmreset_in                    : in   std_logic;
+    gt2_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt2_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt2_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt2_gtrxreset_in                        : in   std_logic;
+    gt2_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt2_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt2_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt2_gttxreset_in                        : in   std_logic;
+    gt2_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt2_txusrclk_in                         : in   std_logic;
+    gt2_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt2_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt2_gtxtxn_out                          : out  std_logic;
+    gt2_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt2_txoutclk_out                        : out  std_logic;
+    gt2_txoutclkfabric_out                  : out  std_logic;
+    gt2_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt2_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt2_txresetdone_out                     : out  std_logic;
+
+    --GT3  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt3_cpllfbclklost_out                   : out  std_logic;
+    gt3_cplllock_out                        : out  std_logic;
+    gt3_cplllockdetclk_in                   : in   std_logic;
+    gt3_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt3_gtrefclk0_in                        : in   std_logic;
+    gt3_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt3_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt3_drpclk_in                           : in   std_logic;
+    gt3_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt3_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt3_drpen_in                            : in   std_logic;
+    gt3_drprdy_out                          : out  std_logic;
+    gt3_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt3_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt3_eyescanreset_in                     : in   std_logic;
+    gt3_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt3_eyescandataerror_out                : out  std_logic;
+    gt3_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt3_rxusrclk_in                         : in   std_logic;
+    gt3_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt3_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt3_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt3_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt3_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt3_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt3_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt3_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt3_rxdfelpmreset_in                    : in   std_logic;
+    gt3_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt3_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt3_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt3_gtrxreset_in                        : in   std_logic;
+    gt3_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt3_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt3_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt3_gttxreset_in                        : in   std_logic;
+    gt3_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt3_txusrclk_in                         : in   std_logic;
+    gt3_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt3_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt3_gtxtxn_out                          : out  std_logic;
+    gt3_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt3_txoutclk_out                        : out  std_logic;
+    gt3_txoutclkfabric_out                  : out  std_logic;
+    gt3_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt3_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt3_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_quadSODA_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component GTX_quadSODA_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE" ;       -- Set to "TRUE" to speed up sim reset
+    SIM_QPLLREFCLK_SEL              :bit_vector  := "001"
+ 
+);
+port
+(
+    QPLLREFCLKSEL_IN   : in std_logic_vector(2 downto 0);
+    GTREFCLK0_IN : in std_logic;
+    GTREFCLK1_IN      : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_quadSODA_GT_USRCLK_SOURCE 
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT1_TXUSRCLK_OUT             : out std_logic;
+    GT1_TXUSRCLK2_OUT            : out std_logic;
+    GT1_TXOUTCLK_IN              : in  std_logic;
+    GT1_RXUSRCLK_OUT             : out std_logic;
+    GT1_RXUSRCLK2_OUT            : out std_logic;
+    GT1_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT2_TXUSRCLK_OUT             : out std_logic;
+    GT2_TXUSRCLK2_OUT            : out std_logic;
+    GT2_TXOUTCLK_IN              : in  std_logic;
+    GT2_RXUSRCLK_OUT             : out std_logic;
+    GT2_RXUSRCLK2_OUT            : out std_logic;
+    GT2_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT3_TXUSRCLK_OUT             : out std_logic;
+    GT3_TXUSRCLK2_OUT            : out std_logic;
+    GT3_TXOUTCLK_IN              : in  std_logic;
+    GT3_RXUSRCLK_OUT             : out std_logic;
+    GT3_RXUSRCLK2_OUT            : out std_logic;
+    GT3_RXOUTCLK_IN              : in  std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_OUT                    : out  std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+    signal   gt1_txfsmresetdone_i            : std_logic;
+signal   gt1_rxfsmresetdone_i            : std_logic;
+    signal   gt1_txfsmresetdone_r            : std_logic;
+    signal   gt1_txfsmresetdone_r2           : std_logic;
+signal   gt1_rxresetdone_r               : std_logic;
+signal   gt1_rxresetdone_r2              : std_logic;
+signal   gt1_rxresetdone_r3              : std_logic;
+
+
+    signal   gt2_txfsmresetdone_i            : std_logic;
+signal   gt2_rxfsmresetdone_i            : std_logic;
+    signal   gt2_txfsmresetdone_r            : std_logic;
+    signal   gt2_txfsmresetdone_r2           : std_logic;
+signal   gt2_rxresetdone_r               : std_logic;
+signal   gt2_rxresetdone_r2              : std_logic;
+signal   gt2_rxresetdone_r3              : std_logic;
+
+
+    signal   gt3_txfsmresetdone_i            : std_logic;
+signal   gt3_rxfsmresetdone_i            : std_logic;
+    signal   gt3_txfsmresetdone_r            : std_logic;
+    signal   gt3_txfsmresetdone_r2           : std_logic;
+signal   gt3_rxresetdone_r               : std_logic;
+signal   gt3_rxresetdone_r2              : std_logic;
+signal   gt3_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y12)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt0_rxdlyen_i                   : std_logic;
+    signal  gt0_rxdlysreset_i               : std_logic;
+    signal  gt0_rxdlysresetdone_i           : std_logic;
+    signal  gt0_rxphalign_i                 : std_logic;
+    signal  gt0_rxphaligndone_i             : std_logic;
+    signal  gt0_rxphalignen_i               : std_logic;
+    signal  gt0_rxphdlyreset_i              : std_logic;
+    signal  gt0_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt0_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt0_txdlyen_i                   : std_logic;
+    signal  gt0_txdlysreset_i               : std_logic;
+    signal  gt0_txdlysresetdone_i           : std_logic;
+    signal  gt0_txphalign_i                 : std_logic;
+    signal  gt0_txphaligndone_i             : std_logic;
+    signal  gt0_txphalignen_i               : std_logic;
+    signal  gt0_txphdlyreset_i              : std_logic;
+    signal  gt0_txphinit_i                  : std_logic;
+    signal  gt0_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT1  (X1Y13)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt1_cpllfbclklost_i             : std_logic;
+    signal  gt1_cplllock_i                  : std_logic;
+    signal  gt1_cpllrefclklost_i            : std_logic;
+    signal  gt1_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt1_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt1_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt1_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt1_drpen_i                     : std_logic;
+    signal  gt1_drprdy_i                    : std_logic;
+    signal  gt1_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt1_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt1_eyescanreset_i              : std_logic;
+    signal  gt1_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt1_eyescandataerror_i          : std_logic;
+    signal  gt1_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt1_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt1_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt1_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt1_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt1_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt1_rxdlyen_i                   : std_logic;
+    signal  gt1_rxdlysreset_i               : std_logic;
+    signal  gt1_rxdlysresetdone_i           : std_logic;
+    signal  gt1_rxphalign_i                 : std_logic;
+    signal  gt1_rxphaligndone_i             : std_logic;
+    signal  gt1_rxphalignen_i               : std_logic;
+    signal  gt1_rxphdlyreset_i              : std_logic;
+    signal  gt1_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt1_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt1_rxlpmhfhold_i               : std_logic;
+    signal  gt1_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt1_rxdfelpmreset_i             : std_logic;
+    signal  gt1_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt1_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt1_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt1_gtrxreset_i                 : std_logic;
+    signal  gt1_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt1_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt1_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt1_gttxreset_i                 : std_logic;
+    signal  gt1_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt1_txdlyen_i                   : std_logic;
+    signal  gt1_txdlysreset_i               : std_logic;
+    signal  gt1_txdlysresetdone_i           : std_logic;
+    signal  gt1_txphalign_i                 : std_logic;
+    signal  gt1_txphaligndone_i             : std_logic;
+    signal  gt1_txphalignen_i               : std_logic;
+    signal  gt1_txphdlyreset_i              : std_logic;
+    signal  gt1_txphinit_i                  : std_logic;
+    signal  gt1_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt1_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt1_gtxtxn_i                    : std_logic;
+    signal  gt1_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt1_txoutclk_i                  : std_logic;
+    signal  gt1_txoutclkfabric_i            : std_logic;
+    signal  gt1_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt1_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt1_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT2  (X1Y14)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt2_cpllfbclklost_i             : std_logic;
+    signal  gt2_cplllock_i                  : std_logic;
+    signal  gt2_cpllrefclklost_i            : std_logic;
+    signal  gt2_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt2_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt2_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt2_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt2_drpen_i                     : std_logic;
+    signal  gt2_drprdy_i                    : std_logic;
+    signal  gt2_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt2_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt2_eyescanreset_i              : std_logic;
+    signal  gt2_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt2_eyescandataerror_i          : std_logic;
+    signal  gt2_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt2_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt2_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt2_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt2_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt2_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt2_rxdlyen_i                   : std_logic;
+    signal  gt2_rxdlysreset_i               : std_logic;
+    signal  gt2_rxdlysresetdone_i           : std_logic;
+    signal  gt2_rxphalign_i                 : std_logic;
+    signal  gt2_rxphaligndone_i             : std_logic;
+    signal  gt2_rxphalignen_i               : std_logic;
+    signal  gt2_rxphdlyreset_i              : std_logic;
+    signal  gt2_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt2_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt2_rxlpmhfhold_i               : std_logic;
+    signal  gt2_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt2_rxdfelpmreset_i             : std_logic;
+    signal  gt2_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt2_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt2_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt2_gtrxreset_i                 : std_logic;
+    signal  gt2_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt2_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt2_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt2_gttxreset_i                 : std_logic;
+    signal  gt2_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt2_txdlyen_i                   : std_logic;
+    signal  gt2_txdlysreset_i               : std_logic;
+    signal  gt2_txdlysresetdone_i           : std_logic;
+    signal  gt2_txphalign_i                 : std_logic;
+    signal  gt2_txphaligndone_i             : std_logic;
+    signal  gt2_txphalignen_i               : std_logic;
+    signal  gt2_txphdlyreset_i              : std_logic;
+    signal  gt2_txphinit_i                  : std_logic;
+    signal  gt2_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt2_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt2_gtxtxn_i                    : std_logic;
+    signal  gt2_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt2_txoutclk_i                  : std_logic;
+    signal  gt2_txoutclkfabric_i            : std_logic;
+    signal  gt2_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt2_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt2_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT3  (X1Y15)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt3_cpllfbclklost_i             : std_logic;
+    signal  gt3_cplllock_i                  : std_logic;
+    signal  gt3_cpllrefclklost_i            : std_logic;
+    signal  gt3_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt3_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt3_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt3_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt3_drpen_i                     : std_logic;
+    signal  gt3_drprdy_i                    : std_logic;
+    signal  gt3_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt3_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt3_eyescanreset_i              : std_logic;
+    signal  gt3_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt3_eyescandataerror_i          : std_logic;
+    signal  gt3_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt3_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt3_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt3_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt3_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt3_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt3_rxdlyen_i                   : std_logic;
+    signal  gt3_rxdlysreset_i               : std_logic;
+    signal  gt3_rxdlysresetdone_i           : std_logic;
+    signal  gt3_rxphalign_i                 : std_logic;
+    signal  gt3_rxphaligndone_i             : std_logic;
+    signal  gt3_rxphalignen_i               : std_logic;
+    signal  gt3_rxphdlyreset_i              : std_logic;
+    signal  gt3_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt3_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt3_rxlpmhfhold_i               : std_logic;
+    signal  gt3_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt3_rxdfelpmreset_i             : std_logic;
+    signal  gt3_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt3_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt3_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt3_gtrxreset_i                 : std_logic;
+    signal  gt3_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt3_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt3_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt3_gttxreset_i                 : std_logic;
+    signal  gt3_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt3_txdlyen_i                   : std_logic;
+    signal  gt3_txdlysreset_i               : std_logic;
+    signal  gt3_txdlysresetdone_i           : std_logic;
+    signal  gt3_txphalign_i                 : std_logic;
+    signal  gt3_txphaligndone_i             : std_logic;
+    signal  gt3_txphalignen_i               : std_logic;
+    signal  gt3_txphdlyreset_i              : std_logic;
+    signal  gt3_txphinit_i                  : std_logic;
+    signal  gt3_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt3_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt3_gtxtxn_i                    : std_logic;
+    signal  gt3_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt3_txoutclk_i                  : std_logic;
+    signal  gt3_txoutclkfabric_i            : std_logic;
+    signal  gt3_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt3_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt3_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  gt1_tx_system_reset_c           : std_logic;
+    signal  gt1_rx_system_reset_c           : std_logic;
+    signal  gt2_tx_system_reset_c           : std_logic;
+    signal  gt2_rx_system_reset_c           : std_logic;
+    signal  gt3_tx_system_reset_c           : std_logic;
+    signal  gt3_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt1_txusrclk_i                  : std_logic; 
+    signal    gt1_txusrclk2_i                 : std_logic; 
+    signal    gt1_rxusrclk_i                  : std_logic; 
+    signal    gt1_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt2_txusrclk_i                  : std_logic; 
+    signal    gt2_txusrclk2_i                 : std_logic; 
+    signal    gt2_rxusrclk_i                  : std_logic; 
+    signal    gt2_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt3_txusrclk_i                  : std_logic; 
+    signal    gt3_txusrclk2_i                 : std_logic; 
+    signal    gt3_rxusrclk_i                  : std_logic; 
+    signal    gt3_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    ----------------------------- Reference Clocks ----------------------------
+    
+signal    q2_clk1_refclk_i                : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+     gt0_qplloutclk_out <= gt0_qplloutclk_i;
+     gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+ 
+      GT1_TXUSRCLK_OUT <= gt1_txusrclk_i; 
+      GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
+      GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
+      GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
+ 
+      GT2_TXUSRCLK_OUT <= gt2_txusrclk_i; 
+      GT2_TXUSRCLK2_OUT <= gt2_txusrclk2_i;
+      GT2_RXUSRCLK_OUT <= gt2_rxusrclk_i;
+      GT2_RXUSRCLK2_OUT <= gt2_rxusrclk2_i;
+ 
+      GT3_TXUSRCLK_OUT <= gt3_txusrclk_i; 
+      GT3_TXUSRCLK2_OUT <= gt3_txusrclk2_i;
+      GT3_RXUSRCLK_OUT <= gt3_rxusrclk_i;
+      GT3_RXUSRCLK2_OUT <= gt3_rxusrclk2_i;
+
+
+    
+  
+    
+  
+    
+  
+    
+  
+    gt_usrclk_source : GTX_quadSODA_GT_USRCLK_SOURCE
+    port map
+   (
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+        GT0_RXOUTCLK_IN                 =>      gt0_rxoutclk_i,
+ 
+        GT1_TXUSRCLK_OUT                =>      gt1_txusrclk_i,
+        GT1_TXUSRCLK2_OUT               =>      gt1_txusrclk2_i,
+        GT1_TXOUTCLK_IN                 =>      gt1_txoutclk_i,
+        GT1_RXUSRCLK_OUT                =>      gt1_rxusrclk_i,
+        GT1_RXUSRCLK2_OUT               =>      gt1_rxusrclk2_i,
+        GT1_RXOUTCLK_IN                 =>      gt1_rxoutclk_i,
+ 
+        GT2_TXUSRCLK_OUT                =>      gt2_txusrclk_i,
+        GT2_TXUSRCLK2_OUT               =>      gt2_txusrclk2_i,
+        GT2_TXOUTCLK_IN                 =>      gt2_txoutclk_i,
+        GT2_RXUSRCLK_OUT                =>      gt2_rxusrclk_i,
+        GT2_RXUSRCLK2_OUT               =>      gt2_rxusrclk2_i,
+        GT2_RXOUTCLK_IN                 =>      gt2_rxoutclk_i,
+ 
+        GT3_TXUSRCLK_OUT                =>      gt3_txusrclk_i,
+        GT3_TXUSRCLK2_OUT               =>      gt3_txusrclk2_i,
+        GT3_TXOUTCLK_IN                 =>      gt3_txoutclk_i,
+        GT3_RXUSRCLK_OUT                =>      gt3_rxusrclk_i,
+        GT3_RXUSRCLK2_OUT               =>      gt3_rxusrclk2_i,
+        GT3_RXOUTCLK_IN                 =>      gt3_rxoutclk_i,
+        Q2_CLK1_GTREFCLK_PAD_N_IN       =>      Q2_CLK1_GTREFCLK_PAD_N_IN,
+        Q2_CLK1_GTREFCLK_PAD_P_IN       =>      Q2_CLK1_GTREFCLK_PAD_P_IN,
+        Q2_CLK1_GTREFCLK_OUT            =>      q2_clk1_refclk_i
+
+    );
+
+sysclk_in_i <= sysclk_in;
+
+    common0_i:GTX_quadSODA_common 
+  generic map
+  (
+   WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+   SIM_QPLLREFCLK_SEL => "001"
+  )
+ port map
+   (
+    QPLLREFCLKSEL_IN    => "001",
+    GTREFCLK0_IN      => tied_to_ground_i,
+    GTREFCLK1_IN      => q2_clk1_refclk_i,
+    QPLLLOCK_OUT => gt0_qplllock_i,
+    QPLLLOCKDETCLK_IN => sysclk_in_i,
+    QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+    common_reset_i:GTX_quadSODA_common_reset 
+   generic map 
+   (
+      STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   )
+   port map
+   (    
+      STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET => soft_reset_tx_in,               --User Reset, can be pulled any time
+      COMMON_RESET => commonreset_i              --Reset QPLL
+   );
+
+
+    GTX_quadSODA_init_i : GTX_quadSODA
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_tx_in                =>      SOFT_RESET_TX_IN,
+        soft_reset_rx_in                =>      SOFT_RESET_RX_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+        gt1_tx_fsm_reset_done_out       =>      gt1_tx_fsm_reset_done_out,
+        gt1_rx_fsm_reset_done_out       =>      gt1_rx_fsm_reset_done_out,
+        gt1_data_valid_in               =>      gt1_data_valid_in,
+        gt2_tx_fsm_reset_done_out       =>      gt2_tx_fsm_reset_done_out,
+        gt2_rx_fsm_reset_done_out       =>      gt2_rx_fsm_reset_done_out,
+        gt2_data_valid_in               =>      gt2_data_valid_in,
+        gt3_tx_fsm_reset_done_out       =>      gt3_tx_fsm_reset_done_out,
+        gt3_rx_fsm_reset_done_out       =>      gt3_rx_fsm_reset_done_out,
+        gt3_data_valid_in               =>      gt3_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y12)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      tied_to_ground_i,
+        gt0_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT1  (X1Y13)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt1_cpllfbclklost_out           =>      gt1_cpllfbclklost_out,
+        gt1_cplllock_out                =>      gt1_cplllock_out,
+        gt1_cplllockdetclk_in           =>      sysclk_in_i,
+        gt1_cpllreset_in                =>      gt1_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt1_gtrefclk0_in                =>      tied_to_ground_i,
+        gt1_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt1_drpaddr_in                  =>      gt1_drpaddr_in,
+        gt1_drpclk_in                   =>      sysclk_in_i,
+        gt1_drpdi_in                    =>      gt1_drpdi_in,
+        gt1_drpdo_out                   =>      gt1_drpdo_out,
+        gt1_drpen_in                    =>      gt1_drpen_in,
+        gt1_drprdy_out                  =>      gt1_drprdy_out,
+        gt1_drpwe_in                    =>      gt1_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt1_dmonitorout_out             =>      gt1_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt1_eyescanreset_in             =>      gt1_eyescanreset_in,
+        gt1_rxuserrdy_in                =>      gt1_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt1_eyescandataerror_out        =>      gt1_eyescandataerror_out,
+        gt1_eyescantrigger_in           =>      gt1_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt1_rxusrclk_in                 =>      gt1_rxusrclk_i,
+        gt1_rxusrclk2_in                =>      gt1_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt1_rxdata_out                  =>      gt1_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt1_rxdisperr_out               =>      gt1_rxdisperr_out,
+        gt1_rxnotintable_out            =>      gt1_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt1_gtxrxp_in                   =>      gt1_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt1_gtxrxn_in                   =>      gt1_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt1_rxphmonitor_out             =>      gt1_rxphmonitor_out,
+        gt1_rxphslipmonitor_out         =>      gt1_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt1_rxdfelpmreset_in            =>      gt1_rxdfelpmreset_in,
+        gt1_rxmonitorout_out            =>      gt1_rxmonitorout_out,
+        gt1_rxmonitorsel_in             =>      gt1_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt1_rxoutclk_out                =>      gt1_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt1_gtrxreset_in                =>      gt1_gtrxreset_in,
+        gt1_rxpmareset_in               =>      gt1_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt1_rxcharisk_out               =>      gt1_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt1_rxresetdone_out             =>      gt1_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt1_gttxreset_in                =>      gt1_gttxreset_in,
+        gt1_txuserrdy_in                =>      gt1_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt1_txusrclk_in                 =>      gt1_txusrclk_i,
+        gt1_txusrclk2_in                =>      gt1_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt1_txdata_in                   =>      gt1_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt1_gtxtxn_out                  =>      gt1_gtxtxn_out,
+        gt1_gtxtxp_out                  =>      gt1_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt1_txoutclk_out                =>      gt1_txoutclk_i,
+        gt1_txoutclkfabric_out          =>      gt1_txoutclkfabric_out,
+        gt1_txoutclkpcs_out             =>      gt1_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt1_txcharisk_in                =>      gt1_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt1_txresetdone_out             =>      gt1_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT2  (X1Y14)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt2_cpllfbclklost_out           =>      gt2_cpllfbclklost_out,
+        gt2_cplllock_out                =>      gt2_cplllock_out,
+        gt2_cplllockdetclk_in           =>      sysclk_in_i,
+        gt2_cpllreset_in                =>      gt2_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt2_gtrefclk0_in                =>      tied_to_ground_i,
+        gt2_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt2_drpaddr_in                  =>      gt2_drpaddr_in,
+        gt2_drpclk_in                   =>      sysclk_in_i,
+        gt2_drpdi_in                    =>      gt2_drpdi_in,
+        gt2_drpdo_out                   =>      gt2_drpdo_out,
+        gt2_drpen_in                    =>      gt2_drpen_in,
+        gt2_drprdy_out                  =>      gt2_drprdy_out,
+        gt2_drpwe_in                    =>      gt2_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt2_dmonitorout_out             =>      gt2_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt2_eyescanreset_in             =>      gt2_eyescanreset_in,
+        gt2_rxuserrdy_in                =>      gt2_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt2_eyescandataerror_out        =>      gt2_eyescandataerror_out,
+        gt2_eyescantrigger_in           =>      gt2_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt2_rxusrclk_in                 =>      gt2_rxusrclk_i,
+        gt2_rxusrclk2_in                =>      gt2_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt2_rxdata_out                  =>      gt2_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt2_rxdisperr_out               =>      gt2_rxdisperr_out,
+        gt2_rxnotintable_out            =>      gt2_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt2_gtxrxp_in                   =>      gt2_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt2_gtxrxn_in                   =>      gt2_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt2_rxphmonitor_out             =>      gt2_rxphmonitor_out,
+        gt2_rxphslipmonitor_out         =>      gt2_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt2_rxdfelpmreset_in            =>      gt2_rxdfelpmreset_in,
+        gt2_rxmonitorout_out            =>      gt2_rxmonitorout_out,
+        gt2_rxmonitorsel_in             =>      gt2_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt2_rxoutclk_out                =>      gt2_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt2_gtrxreset_in                =>      gt2_gtrxreset_in,
+        gt2_rxpmareset_in               =>      gt2_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt2_rxcharisk_out               =>      gt2_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt2_rxresetdone_out             =>      gt2_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt2_gttxreset_in                =>      gt2_gttxreset_in,
+        gt2_txuserrdy_in                =>      gt2_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt2_txusrclk_in                 =>      gt2_txusrclk_i,
+        gt2_txusrclk2_in                =>      gt2_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt2_txdata_in                   =>      gt2_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt2_gtxtxn_out                  =>      gt2_gtxtxn_out,
+        gt2_gtxtxp_out                  =>      gt2_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt2_txoutclk_out                =>      gt2_txoutclk_i,
+        gt2_txoutclkfabric_out          =>      gt2_txoutclkfabric_out,
+        gt2_txoutclkpcs_out             =>      gt2_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt2_txcharisk_in                =>      gt2_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt2_txresetdone_out             =>      gt2_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT3  (X1Y15)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt3_cpllfbclklost_out           =>      gt3_cpllfbclklost_out,
+        gt3_cplllock_out                =>      gt3_cplllock_out,
+        gt3_cplllockdetclk_in           =>      sysclk_in_i,
+        gt3_cpllreset_in                =>      gt3_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt3_gtrefclk0_in                =>      tied_to_ground_i,
+        gt3_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt3_drpaddr_in                  =>      gt3_drpaddr_in,
+        gt3_drpclk_in                   =>      sysclk_in_i,
+        gt3_drpdi_in                    =>      gt3_drpdi_in,
+        gt3_drpdo_out                   =>      gt3_drpdo_out,
+        gt3_drpen_in                    =>      gt3_drpen_in,
+        gt3_drprdy_out                  =>      gt3_drprdy_out,
+        gt3_drpwe_in                    =>      gt3_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt3_dmonitorout_out             =>      gt3_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt3_eyescanreset_in             =>      gt3_eyescanreset_in,
+        gt3_rxuserrdy_in                =>      gt3_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt3_eyescandataerror_out        =>      gt3_eyescandataerror_out,
+        gt3_eyescantrigger_in           =>      gt3_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt3_rxusrclk_in                 =>      gt3_rxusrclk_i,
+        gt3_rxusrclk2_in                =>      gt3_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt3_rxdata_out                  =>      gt3_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt3_rxdisperr_out               =>      gt3_rxdisperr_out,
+        gt3_rxnotintable_out            =>      gt3_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt3_gtxrxp_in                   =>      gt3_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt3_gtxrxn_in                   =>      gt3_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt3_rxphmonitor_out             =>      gt3_rxphmonitor_out,
+        gt3_rxphslipmonitor_out         =>      gt3_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt3_rxdfelpmreset_in            =>      gt3_rxdfelpmreset_in,
+        gt3_rxmonitorout_out            =>      gt3_rxmonitorout_out,
+        gt3_rxmonitorsel_in             =>      gt3_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt3_rxoutclk_out                =>      gt3_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt3_gtrxreset_in                =>      gt3_gtrxreset_in,
+        gt3_rxpmareset_in               =>      gt3_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt3_rxcharisk_out               =>      gt3_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt3_rxresetdone_out             =>      gt3_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt3_gttxreset_in                =>      gt3_gttxreset_in,
+        gt3_txuserrdy_in                =>      gt3_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt3_txusrclk_in                 =>      gt3_txusrclk_i,
+        gt3_txusrclk2_in                =>      gt3_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt3_txdata_in                   =>      gt3_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt3_gtxtxn_out                  =>      gt3_gtxtxn_out,
+        gt3_gtxtxp_out                  =>      gt3_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt3_txoutclk_out                =>      gt3_txoutclk_i,
+        gt3_txoutclkfabric_out          =>      gt3_txoutclkfabric_out,
+        gt3_txoutclkpcs_out             =>      gt3_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt3_txcharisk_in                =>      gt3_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt3_txresetdone_out             =>      gt3_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_common.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_common.vhd
new file mode 100644
index 0000000..293a589
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_common.vhd
@@ -0,0 +1,247 @@
+---------------------------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_quadsoda_common.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_quadSODA_common 
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_quadSODA_common is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "TRUE";        -- Set to "true" to speed up sim reset 
+    SIM_QPLLREFCLK_SEL              : bit_vector :=  "001"
+);
+port
+(
+    QPLLREFCLKSEL_IN  : in std_logic_vector(2 downto 0);
+    GTREFCLK1_IN      : in std_logic;
+    GTREFCLK0_IN : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+);
+
+end GTX_quadSODA_common;
+    
+architecture RTL of GTX_quadSODA_common is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_quadSODA_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+    impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return "0000100000";
+       elsif (qpllfbdiv_top = 20) then
+         return "0000110000" ;
+       elsif (qpllfbdiv_top = 32) then
+         return "0001100000" ;
+       elsif (qpllfbdiv_top = 40) then
+         return "0010000000" ;
+       elsif (qpllfbdiv_top = 64) then
+         return "0011100000" ;
+       elsif (qpllfbdiv_top = 66) then
+         return "0101000000" ;
+       elsif (qpllfbdiv_top = 80) then
+         return "0100100000" ;
+       elsif (qpllfbdiv_top = 100) then
+         return "0101110000" ;
+       else 
+         return "0000000000" ;
+       end if;
+    end function;
+
+    impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return '1';
+       elsif (qpllfbdiv_top = 20) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 32) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 40) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 64) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 66) then
+         return '0' ;
+       elsif (qpllfbdiv_top = 80) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 100) then
+         return '1' ;
+       else 
+         return '1' ;
+       end if;
+    end function;
+
+    constant   QPLL_FBDIV_TOP   : integer  := 80;
+    constant   QPLL_FBDIV_IN    :   bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+    constant   QPLL_FBDIV_RATIO :   bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal  tied_to_vcc_vec_i               :   std_logic_vector(63 downto 0);
+
+begin
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    tied_to_vcc_vec_i(63 downto 0)      <= (others => '1');
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTXE2_COMMON____________________________________
+
+    gtxe2_common_i : GTXE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_QPLLREFCLK_SEL   => (SIM_QPLLREFCLK_SEL),
+            SIM_VERSION          => "4.0",
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000040000001000"),
+        COMMON_CFG                              =>     (x"00000000"),
+        QPLL_CFG                                =>     (x"06801C1"),
+        QPLL_CLKOUT_CFG                         =>     ("0000"),
+        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
+        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
+        QPLL_CP                                 =>     ("0000011111"),
+        QPLL_CP_MONITOR_EN                      =>     ('0'),
+        QPLL_DMONITOR_SEL                       =>     ('0'),
+        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
+        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
+        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
+        QPLL_INIT_CFG                           =>     (x"000006"),
+        QPLL_LOCK_CFG                           =>     (x"21E8"),
+        QPLL_LPF                                =>     ("1111"),
+        QPLL_REFCLK_DIV                         =>     (3)
+
+        
+    )
+    port map
+    (
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      GTREFCLK1_IN,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ------------------------- Common Block -  QPLL Ports -----------------------
+        QPLLDMONITOR                    =>      open,
+        ----------------------- Common Block - Clocking Ports ----------------------
+        QPLLOUTCLK                      =>      QPLLOUTCLK_OUT,
+        QPLLOUTREFCLK                   =>      QPLLOUTREFCLK_OUT,
+        REFCLKOUTMONITOR                =>      open,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        QPLLFBCLKLOST                   =>      open,
+        QPLLLOCK                        =>      QPLLLOCK_OUT,
+        QPLLLOCKDETCLK                  =>      QPLLLOCKDETCLK_IN,
+        QPLLLOCKEN                      =>      tied_to_vcc_i,
+        QPLLOUTRESET                    =>      tied_to_ground_i,
+        QPLLPD                          =>      tied_to_vcc_i,
+        QPLLREFCLKLOST                  =>      QPLLREFCLKLOST_OUT,
+        QPLLREFCLKSEL                   =>      QPLLREFCLKSEL_IN,
+        QPLLRESET                       =>      QPLLRESET_IN,
+        QPLLRSVD1                       =>      "0000000000000000",
+        QPLLRSVD2                       =>      "11111",
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "11111",
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_common_reset.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_common_reset.vhd
new file mode 100644
index 0000000..9117ff4
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_common_reset.vhd
@@ -0,0 +1,154 @@
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_quadsoda_common_reset.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module GTX_quadSODA_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_quadSODA_common_reset is 
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic:= '0'  --Reset QPLL
+   );
+end GTX_quadSODA_common_reset;
+
+architecture RTL of GTX_quadSODA_common_reset is
+
+
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+
+
+  signal init_wait_count  : std_logic_vector(7 downto 0) :=(others => '0');
+  signal init_wait_done   : std_logic :='0';
+  signal common_reset_asserted   : std_logic :='0';
+  signal common_reset_i   : std_logic ;
+
+  type rst_type is(
+    INIT, ASSERT_COMMON_RESET);
+    
+  signal state : rst_type := INIT;
+
+begin
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1') then
+        state                <= INIT;
+        common_reset_asserted   <= '0';
+        COMMON_RESET   <= '0';
+      else
+        
+        case state is
+          when INIT => 
+            if init_wait_done = '1' then
+              state        <= ASSERT_COMMON_RESET;
+            end if;
+            
+          when ASSERT_COMMON_RESET =>
+             if common_reset_asserted = '0' then
+                COMMON_RESET          <= '1';
+                common_reset_asserted  <= '1';
+              else
+                COMMON_RESET          <= '0';
+              end if;
+           when OTHERS =>
+            state   <= INIT;
+         end case;
+       end if;
+    end if;
+  end process;
+ 
+
+end RTL; 
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_gt_usrclk_source.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_gt_usrclk_source.vhd
new file mode 100644
index 0000000..49b665d
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_gt_usrclk_source.vhd
@@ -0,0 +1,234 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_quadsoda_gt_usrclk_source.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+-- Module GTX_quadSODA_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_quadSODA_GT_USRCLK_SOURCE is
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT1_TXUSRCLK_OUT             : out std_logic;
+    GT1_TXUSRCLK2_OUT            : out std_logic;
+    GT1_TXOUTCLK_IN              : in  std_logic;
+    GT1_RXUSRCLK_OUT             : out std_logic;
+    GT1_RXUSRCLK2_OUT            : out std_logic;
+    GT1_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT2_TXUSRCLK_OUT             : out std_logic;
+    GT2_TXUSRCLK2_OUT            : out std_logic;
+    GT2_TXOUTCLK_IN              : in  std_logic;
+    GT2_RXUSRCLK_OUT             : out std_logic;
+    GT2_RXUSRCLK2_OUT            : out std_logic;
+    GT2_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT3_TXUSRCLK_OUT             : out std_logic;
+    GT3_TXUSRCLK2_OUT            : out std_logic;
+    GT3_TXOUTCLK_IN              : in  std_logic;
+    GT3_RXUSRCLK_OUT             : out std_logic;
+    GT3_RXUSRCLK2_OUT            : out std_logic;
+    GT3_RXOUTCLK_IN              : in  std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_OUT                    : out  std_logic
+);
+
+
+end GTX_quadSODA_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_quadSODA_GT_USRCLK_SOURCE is
+
+component GTX_QUADSODA_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+    signal   tied_to_ground_i     :   std_logic;
+    signal   tied_to_vcc_i        :   std_logic;
+ 
+    signal   gt0_txoutclk_i :   std_logic;
+    signal   gt0_rxoutclk_i :   std_logic;
+ 
+    signal   gt1_txoutclk_i :   std_logic;
+    signal   gt1_rxoutclk_i :   std_logic;
+ 
+    signal   gt2_txoutclk_i :   std_logic;
+    signal   gt2_rxoutclk_i :   std_logic;
+ 
+    signal   gt3_txoutclk_i :   std_logic;
+    signal   gt3_rxoutclk_i :   std_logic;
+
+    attribute syn_noclockbuf : boolean;
+    signal   q2_clk1_gtrefclk :   std_logic;
+    attribute syn_noclockbuf of q2_clk1_gtrefclk : signal is true;
+
+    signal  gt0_txusrclk_i                  : std_logic;
+    signal  gt0_rxusrclk_i                  : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+    --  Static signal Assigments    
+    tied_to_ground_i         <= '0';
+    tied_to_vcc_i            <= '1';
+    gt0_txoutclk_i                               <= GT0_TXOUTCLK_IN;
+    gt0_rxoutclk_i                               <= GT0_RXOUTCLK_IN;
+    gt1_txoutclk_i                               <= GT1_TXOUTCLK_IN;
+    gt1_rxoutclk_i                               <= GT1_RXOUTCLK_IN;
+    gt2_txoutclk_i                               <= GT2_TXOUTCLK_IN;
+    gt2_rxoutclk_i                               <= GT2_RXOUTCLK_IN;
+    gt3_txoutclk_i                               <= GT3_TXOUTCLK_IN;
+    gt3_rxoutclk_i                               <= GT3_RXOUTCLK_IN;
+
+    Q2_CLK1_GTREFCLK_OUT                         <= q2_clk1_gtrefclk;
+
+    --IBUFDS_GTE2
+    ibufds_instq2_clk1 : IBUFDS_GTE2  
+    port map
+    (
+        O               => 	q2_clk1_gtrefclk,
+        ODIV2           =>    open,
+        CEB             => 	tied_to_ground_i,
+        I               => 	Q2_CLK1_GTREFCLK_PAD_P_IN,
+        IB              => 	Q2_CLK1_GTREFCLK_PAD_N_IN
+    );
+
+
+    
+    -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+    -- for improved jitter performance, and to avoid consuming an additional BUFG
+    txoutclk_bufg0_i : BUFG
+    port map
+    (
+        I                               =>      gt0_txoutclk_i,
+        O                               =>      gt0_txusrclk_i
+    );
+
+
+    rxoutclk_bufg1_i : BUFG
+    port map
+    (
+        I                               =>      gt0_rxoutclk_i,
+        O                               =>      gt0_rxusrclk_i
+    );
+
+
+
+ 
+GT0_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT0_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+ 
+GT1_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT1_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT1_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT1_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+ 
+GT2_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT2_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT2_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT2_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+ 
+GT3_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT3_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT3_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT3_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_support.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_support.vhd
new file mode 100644
index 0000000..3b3c6e3
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODA/gtx_quadsoda_support.vhd
@@ -0,0 +1,1693 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_quadsoda_support.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_quadSODA_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_quadSODA_support is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 10  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+    GT2_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_DATA_VALID_IN                       : in   std_logic;
+    GT3_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_DATA_VALID_IN                       : in   std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT1_TXUSRCLK_OUT                        : out  std_logic;
+    GT1_TXUSRCLK2_OUT                       : out  std_logic;
+    GT1_RXUSRCLK_OUT                        : out  std_logic;
+    GT1_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT2_TXUSRCLK_OUT                        : out  std_logic;
+    GT2_TXUSRCLK2_OUT                       : out  std_logic;
+    GT2_RXUSRCLK_OUT                        : out  std_logic;
+    GT2_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT3_TXUSRCLK_OUT                        : out  std_logic;
+    GT3_TXUSRCLK2_OUT                       : out  std_logic;
+    GT3_RXUSRCLK_OUT                        : out  std_logic;
+    GT3_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt1_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt1_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+
+    --GT2  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt2_cpllfbclklost_out                   : out  std_logic;
+    gt2_cplllock_out                        : out  std_logic;
+    gt2_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt2_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt2_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt2_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt2_drpen_in                            : in   std_logic;
+    gt2_drprdy_out                          : out  std_logic;
+    gt2_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt2_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt2_eyescanreset_in                     : in   std_logic;
+    gt2_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt2_eyescandataerror_out                : out  std_logic;
+    gt2_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt2_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt2_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt2_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt2_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt2_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt2_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt2_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt2_rxdfelpmreset_in                    : in   std_logic;
+    gt2_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt2_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt2_gtrxreset_in                        : in   std_logic;
+    gt2_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt2_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt2_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt2_gttxreset_in                        : in   std_logic;
+    gt2_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt2_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt2_gtxtxn_out                          : out  std_logic;
+    gt2_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt2_txoutclkfabric_out                  : out  std_logic;
+    gt2_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt2_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt2_txresetdone_out                     : out  std_logic;
+
+    --GT3  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt3_cpllfbclklost_out                   : out  std_logic;
+    gt3_cplllock_out                        : out  std_logic;
+    gt3_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt3_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt3_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt3_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt3_drpen_in                            : in   std_logic;
+    gt3_drprdy_out                          : out  std_logic;
+    gt3_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt3_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt3_eyescanreset_in                     : in   std_logic;
+    gt3_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt3_eyescandataerror_out                : out  std_logic;
+    gt3_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt3_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt3_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt3_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt3_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt3_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt3_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt3_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt3_rxdfelpmreset_in                    : in   std_logic;
+    gt3_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt3_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt3_gtrxreset_in                        : in   std_logic;
+    gt3_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt3_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt3_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt3_gttxreset_in                        : in   std_logic;
+    gt3_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt3_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt3_gtxtxn_out                          : out  std_logic;
+    gt3_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt3_txoutclkfabric_out                  : out  std_logic;
+    gt3_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt3_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt3_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT  : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT : out std_logic;
+       sysclk_in        : in std_logic
+
+);
+
+end GTX_quadSODA_support;
+    
+architecture RTL of GTX_quadSODA_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_quadSODA
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+    GT2_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_DATA_VALID_IN                       : in   std_logic;
+    GT3_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_DATA_VALID_IN                       : in   std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cplllockdetclk_in                   : in   std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt1_gtrefclk0_in                        : in   std_logic;
+    gt1_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpclk_in                           : in   std_logic;
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt1_rxusrclk_in                         : in   std_logic;
+    gt1_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt1_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt1_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt1_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt1_txusrclk_in                         : in   std_logic;
+    gt1_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclk_out                        : out  std_logic;
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+
+    --GT2  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt2_cpllfbclklost_out                   : out  std_logic;
+    gt2_cplllock_out                        : out  std_logic;
+    gt2_cplllockdetclk_in                   : in   std_logic;
+    gt2_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt2_gtrefclk0_in                        : in   std_logic;
+    gt2_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt2_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt2_drpclk_in                           : in   std_logic;
+    gt2_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt2_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt2_drpen_in                            : in   std_logic;
+    gt2_drprdy_out                          : out  std_logic;
+    gt2_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt2_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt2_eyescanreset_in                     : in   std_logic;
+    gt2_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt2_eyescandataerror_out                : out  std_logic;
+    gt2_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt2_rxusrclk_in                         : in   std_logic;
+    gt2_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt2_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt2_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt2_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt2_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt2_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt2_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt2_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt2_rxdfelpmreset_in                    : in   std_logic;
+    gt2_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt2_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt2_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt2_gtrxreset_in                        : in   std_logic;
+    gt2_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt2_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt2_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt2_gttxreset_in                        : in   std_logic;
+    gt2_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt2_txusrclk_in                         : in   std_logic;
+    gt2_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt2_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt2_gtxtxn_out                          : out  std_logic;
+    gt2_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt2_txoutclk_out                        : out  std_logic;
+    gt2_txoutclkfabric_out                  : out  std_logic;
+    gt2_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt2_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt2_txresetdone_out                     : out  std_logic;
+
+    --GT3  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt3_cpllfbclklost_out                   : out  std_logic;
+    gt3_cplllock_out                        : out  std_logic;
+    gt3_cplllockdetclk_in                   : in   std_logic;
+    gt3_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt3_gtrefclk0_in                        : in   std_logic;
+    gt3_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt3_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt3_drpclk_in                           : in   std_logic;
+    gt3_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt3_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt3_drpen_in                            : in   std_logic;
+    gt3_drprdy_out                          : out  std_logic;
+    gt3_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt3_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt3_eyescanreset_in                     : in   std_logic;
+    gt3_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt3_eyescandataerror_out                : out  std_logic;
+    gt3_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt3_rxusrclk_in                         : in   std_logic;
+    gt3_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt3_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt3_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt3_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt3_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt3_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt3_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt3_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt3_rxdfelpmreset_in                    : in   std_logic;
+    gt3_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt3_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt3_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt3_gtrxreset_in                        : in   std_logic;
+    gt3_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt3_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt3_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt3_gttxreset_in                        : in   std_logic;
+    gt3_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt3_txusrclk_in                         : in   std_logic;
+    gt3_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt3_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt3_gtxtxn_out                          : out  std_logic;
+    gt3_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt3_txoutclk_out                        : out  std_logic;
+    gt3_txoutclkfabric_out                  : out  std_logic;
+    gt3_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt3_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt3_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_quadSODA_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component GTX_quadSODA_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE" ;       -- Set to "TRUE" to speed up sim reset
+    SIM_QPLLREFCLK_SEL              :bit_vector  := "001"
+ 
+);
+port
+(
+    QPLLREFCLKSEL_IN   : in std_logic_vector(2 downto 0);
+    GTREFCLK0_IN : in std_logic;
+    GTREFCLK1_IN      : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_quadSODA_GT_USRCLK_SOURCE 
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT1_TXUSRCLK_OUT             : out std_logic;
+    GT1_TXUSRCLK2_OUT            : out std_logic;
+    GT1_TXOUTCLK_IN              : in  std_logic;
+    GT1_RXUSRCLK_OUT             : out std_logic;
+    GT1_RXUSRCLK2_OUT            : out std_logic;
+    GT1_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT2_TXUSRCLK_OUT             : out std_logic;
+    GT2_TXUSRCLK2_OUT            : out std_logic;
+    GT2_TXOUTCLK_IN              : in  std_logic;
+    GT2_RXUSRCLK_OUT             : out std_logic;
+    GT2_RXUSRCLK2_OUT            : out std_logic;
+    GT2_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT3_TXUSRCLK_OUT             : out std_logic;
+    GT3_TXUSRCLK2_OUT            : out std_logic;
+    GT3_TXOUTCLK_IN              : in  std_logic;
+    GT3_RXUSRCLK_OUT             : out std_logic;
+    GT3_RXUSRCLK2_OUT            : out std_logic;
+    GT3_RXOUTCLK_IN              : in  std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_OUT                    : out  std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+    signal   gt1_txfsmresetdone_i            : std_logic;
+signal   gt1_rxfsmresetdone_i            : std_logic;
+    signal   gt1_txfsmresetdone_r            : std_logic;
+    signal   gt1_txfsmresetdone_r2           : std_logic;
+signal   gt1_rxresetdone_r               : std_logic;
+signal   gt1_rxresetdone_r2              : std_logic;
+signal   gt1_rxresetdone_r3              : std_logic;
+
+
+    signal   gt2_txfsmresetdone_i            : std_logic;
+signal   gt2_rxfsmresetdone_i            : std_logic;
+    signal   gt2_txfsmresetdone_r            : std_logic;
+    signal   gt2_txfsmresetdone_r2           : std_logic;
+signal   gt2_rxresetdone_r               : std_logic;
+signal   gt2_rxresetdone_r2              : std_logic;
+signal   gt2_rxresetdone_r3              : std_logic;
+
+
+    signal   gt3_txfsmresetdone_i            : std_logic;
+signal   gt3_rxfsmresetdone_i            : std_logic;
+    signal   gt3_txfsmresetdone_r            : std_logic;
+    signal   gt3_txfsmresetdone_r2           : std_logic;
+signal   gt3_rxresetdone_r               : std_logic;
+signal   gt3_rxresetdone_r2              : std_logic;
+signal   gt3_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y12)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt0_rxdlyen_i                   : std_logic;
+    signal  gt0_rxdlysreset_i               : std_logic;
+    signal  gt0_rxdlysresetdone_i           : std_logic;
+    signal  gt0_rxphalign_i                 : std_logic;
+    signal  gt0_rxphaligndone_i             : std_logic;
+    signal  gt0_rxphalignen_i               : std_logic;
+    signal  gt0_rxphdlyreset_i              : std_logic;
+    signal  gt0_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt0_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt0_txdlyen_i                   : std_logic;
+    signal  gt0_txdlysreset_i               : std_logic;
+    signal  gt0_txdlysresetdone_i           : std_logic;
+    signal  gt0_txphalign_i                 : std_logic;
+    signal  gt0_txphaligndone_i             : std_logic;
+    signal  gt0_txphalignen_i               : std_logic;
+    signal  gt0_txphdlyreset_i              : std_logic;
+    signal  gt0_txphinit_i                  : std_logic;
+    signal  gt0_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT1  (X1Y13)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt1_cpllfbclklost_i             : std_logic;
+    signal  gt1_cplllock_i                  : std_logic;
+    signal  gt1_cpllrefclklost_i            : std_logic;
+    signal  gt1_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt1_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt1_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt1_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt1_drpen_i                     : std_logic;
+    signal  gt1_drprdy_i                    : std_logic;
+    signal  gt1_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt1_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt1_eyescanreset_i              : std_logic;
+    signal  gt1_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt1_eyescandataerror_i          : std_logic;
+    signal  gt1_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt1_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt1_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt1_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt1_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt1_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt1_rxdlyen_i                   : std_logic;
+    signal  gt1_rxdlysreset_i               : std_logic;
+    signal  gt1_rxdlysresetdone_i           : std_logic;
+    signal  gt1_rxphalign_i                 : std_logic;
+    signal  gt1_rxphaligndone_i             : std_logic;
+    signal  gt1_rxphalignen_i               : std_logic;
+    signal  gt1_rxphdlyreset_i              : std_logic;
+    signal  gt1_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt1_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt1_rxlpmhfhold_i               : std_logic;
+    signal  gt1_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt1_rxdfelpmreset_i             : std_logic;
+    signal  gt1_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt1_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt1_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt1_gtrxreset_i                 : std_logic;
+    signal  gt1_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt1_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt1_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt1_gttxreset_i                 : std_logic;
+    signal  gt1_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt1_txdlyen_i                   : std_logic;
+    signal  gt1_txdlysreset_i               : std_logic;
+    signal  gt1_txdlysresetdone_i           : std_logic;
+    signal  gt1_txphalign_i                 : std_logic;
+    signal  gt1_txphaligndone_i             : std_logic;
+    signal  gt1_txphalignen_i               : std_logic;
+    signal  gt1_txphdlyreset_i              : std_logic;
+    signal  gt1_txphinit_i                  : std_logic;
+    signal  gt1_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt1_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt1_gtxtxn_i                    : std_logic;
+    signal  gt1_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt1_txoutclk_i                  : std_logic;
+    signal  gt1_txoutclkfabric_i            : std_logic;
+    signal  gt1_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt1_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt1_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT2  (X1Y14)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt2_cpllfbclklost_i             : std_logic;
+    signal  gt2_cplllock_i                  : std_logic;
+    signal  gt2_cpllrefclklost_i            : std_logic;
+    signal  gt2_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt2_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt2_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt2_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt2_drpen_i                     : std_logic;
+    signal  gt2_drprdy_i                    : std_logic;
+    signal  gt2_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt2_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt2_eyescanreset_i              : std_logic;
+    signal  gt2_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt2_eyescandataerror_i          : std_logic;
+    signal  gt2_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt2_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt2_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt2_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt2_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt2_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt2_rxdlyen_i                   : std_logic;
+    signal  gt2_rxdlysreset_i               : std_logic;
+    signal  gt2_rxdlysresetdone_i           : std_logic;
+    signal  gt2_rxphalign_i                 : std_logic;
+    signal  gt2_rxphaligndone_i             : std_logic;
+    signal  gt2_rxphalignen_i               : std_logic;
+    signal  gt2_rxphdlyreset_i              : std_logic;
+    signal  gt2_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt2_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt2_rxlpmhfhold_i               : std_logic;
+    signal  gt2_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt2_rxdfelpmreset_i             : std_logic;
+    signal  gt2_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt2_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt2_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt2_gtrxreset_i                 : std_logic;
+    signal  gt2_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt2_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt2_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt2_gttxreset_i                 : std_logic;
+    signal  gt2_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt2_txdlyen_i                   : std_logic;
+    signal  gt2_txdlysreset_i               : std_logic;
+    signal  gt2_txdlysresetdone_i           : std_logic;
+    signal  gt2_txphalign_i                 : std_logic;
+    signal  gt2_txphaligndone_i             : std_logic;
+    signal  gt2_txphalignen_i               : std_logic;
+    signal  gt2_txphdlyreset_i              : std_logic;
+    signal  gt2_txphinit_i                  : std_logic;
+    signal  gt2_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt2_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt2_gtxtxn_i                    : std_logic;
+    signal  gt2_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt2_txoutclk_i                  : std_logic;
+    signal  gt2_txoutclkfabric_i            : std_logic;
+    signal  gt2_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt2_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt2_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT3  (X1Y15)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt3_cpllfbclklost_i             : std_logic;
+    signal  gt3_cplllock_i                  : std_logic;
+    signal  gt3_cpllrefclklost_i            : std_logic;
+    signal  gt3_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt3_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt3_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt3_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt3_drpen_i                     : std_logic;
+    signal  gt3_drprdy_i                    : std_logic;
+    signal  gt3_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt3_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt3_eyescanreset_i              : std_logic;
+    signal  gt3_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt3_eyescandataerror_i          : std_logic;
+    signal  gt3_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt3_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt3_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt3_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt3_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt3_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt3_rxdlyen_i                   : std_logic;
+    signal  gt3_rxdlysreset_i               : std_logic;
+    signal  gt3_rxdlysresetdone_i           : std_logic;
+    signal  gt3_rxphalign_i                 : std_logic;
+    signal  gt3_rxphaligndone_i             : std_logic;
+    signal  gt3_rxphalignen_i               : std_logic;
+    signal  gt3_rxphdlyreset_i              : std_logic;
+    signal  gt3_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt3_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt3_rxlpmhfhold_i               : std_logic;
+    signal  gt3_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt3_rxdfelpmreset_i             : std_logic;
+    signal  gt3_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt3_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt3_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt3_gtrxreset_i                 : std_logic;
+    signal  gt3_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt3_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt3_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt3_gttxreset_i                 : std_logic;
+    signal  gt3_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt3_txdlyen_i                   : std_logic;
+    signal  gt3_txdlysreset_i               : std_logic;
+    signal  gt3_txdlysresetdone_i           : std_logic;
+    signal  gt3_txphalign_i                 : std_logic;
+    signal  gt3_txphaligndone_i             : std_logic;
+    signal  gt3_txphalignen_i               : std_logic;
+    signal  gt3_txphdlyreset_i              : std_logic;
+    signal  gt3_txphinit_i                  : std_logic;
+    signal  gt3_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt3_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt3_gtxtxn_i                    : std_logic;
+    signal  gt3_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt3_txoutclk_i                  : std_logic;
+    signal  gt3_txoutclkfabric_i            : std_logic;
+    signal  gt3_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt3_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt3_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  gt1_tx_system_reset_c           : std_logic;
+    signal  gt1_rx_system_reset_c           : std_logic;
+    signal  gt2_tx_system_reset_c           : std_logic;
+    signal  gt2_rx_system_reset_c           : std_logic;
+    signal  gt3_tx_system_reset_c           : std_logic;
+    signal  gt3_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt1_txusrclk_i                  : std_logic; 
+    signal    gt1_txusrclk2_i                 : std_logic; 
+    signal    gt1_rxusrclk_i                  : std_logic; 
+    signal    gt1_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt2_txusrclk_i                  : std_logic; 
+    signal    gt2_txusrclk2_i                 : std_logic; 
+    signal    gt2_rxusrclk_i                  : std_logic; 
+    signal    gt2_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt3_txusrclk_i                  : std_logic; 
+    signal    gt3_txusrclk2_i                 : std_logic; 
+    signal    gt3_rxusrclk_i                  : std_logic; 
+    signal    gt3_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    ----------------------------- Reference Clocks ----------------------------
+    
+signal    q2_clk1_refclk_i                : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+     gt0_qplloutclk_out <= gt0_qplloutclk_i;
+     gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+ 
+      GT1_TXUSRCLK_OUT <= gt1_txusrclk_i; 
+      GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
+      GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
+      GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
+ 
+      GT2_TXUSRCLK_OUT <= gt2_txusrclk_i; 
+      GT2_TXUSRCLK2_OUT <= gt2_txusrclk2_i;
+      GT2_RXUSRCLK_OUT <= gt2_rxusrclk_i;
+      GT2_RXUSRCLK2_OUT <= gt2_rxusrclk2_i;
+ 
+      GT3_TXUSRCLK_OUT <= gt3_txusrclk_i; 
+      GT3_TXUSRCLK2_OUT <= gt3_txusrclk2_i;
+      GT3_RXUSRCLK_OUT <= gt3_rxusrclk_i;
+      GT3_RXUSRCLK2_OUT <= gt3_rxusrclk2_i;
+
+
+    
+  
+    
+  
+    
+  
+    
+  
+    gt_usrclk_source : GTX_quadSODA_GT_USRCLK_SOURCE
+    port map
+   (
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+        GT0_RXOUTCLK_IN                 =>      gt0_rxoutclk_i,
+ 
+        GT1_TXUSRCLK_OUT                =>      gt1_txusrclk_i,
+        GT1_TXUSRCLK2_OUT               =>      gt1_txusrclk2_i,
+        GT1_TXOUTCLK_IN                 =>      gt1_txoutclk_i,
+        GT1_RXUSRCLK_OUT                =>      gt1_rxusrclk_i,
+        GT1_RXUSRCLK2_OUT               =>      gt1_rxusrclk2_i,
+        GT1_RXOUTCLK_IN                 =>      gt1_rxoutclk_i,
+ 
+        GT2_TXUSRCLK_OUT                =>      gt2_txusrclk_i,
+        GT2_TXUSRCLK2_OUT               =>      gt2_txusrclk2_i,
+        GT2_TXOUTCLK_IN                 =>      gt2_txoutclk_i,
+        GT2_RXUSRCLK_OUT                =>      gt2_rxusrclk_i,
+        GT2_RXUSRCLK2_OUT               =>      gt2_rxusrclk2_i,
+        GT2_RXOUTCLK_IN                 =>      gt2_rxoutclk_i,
+ 
+        GT3_TXUSRCLK_OUT                =>      gt3_txusrclk_i,
+        GT3_TXUSRCLK2_OUT               =>      gt3_txusrclk2_i,
+        GT3_TXOUTCLK_IN                 =>      gt3_txoutclk_i,
+        GT3_RXUSRCLK_OUT                =>      gt3_rxusrclk_i,
+        GT3_RXUSRCLK2_OUT               =>      gt3_rxusrclk2_i,
+        GT3_RXOUTCLK_IN                 =>      gt3_rxoutclk_i,
+        Q2_CLK1_GTREFCLK_PAD_N_IN       =>      Q2_CLK1_GTREFCLK_PAD_N_IN,
+        Q2_CLK1_GTREFCLK_PAD_P_IN       =>      Q2_CLK1_GTREFCLK_PAD_P_IN,
+        Q2_CLK1_GTREFCLK_OUT            =>      q2_clk1_refclk_i
+
+    );
+
+sysclk_in_i <= sysclk_in;
+
+    common0_i:GTX_quadSODA_common 
+  generic map
+  (
+   WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+   SIM_QPLLREFCLK_SEL => "001"
+  )
+ port map
+   (
+    QPLLREFCLKSEL_IN    => "001",
+    GTREFCLK0_IN      => tied_to_ground_i,
+    GTREFCLK1_IN      => q2_clk1_refclk_i,
+    QPLLLOCK_OUT => gt0_qplllock_i,
+    QPLLLOCKDETCLK_IN => sysclk_in_i,
+    QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+    common_reset_i:GTX_quadSODA_common_reset 
+   generic map 
+   (
+      STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   )
+   port map
+   (    
+      STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET => soft_reset_tx_in,               --User Reset, can be pulled any time
+      COMMON_RESET => commonreset_i              --Reset QPLL
+   );
+
+
+    GTX_quadSODA_init_i : GTX_quadSODA
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_tx_in                =>      SOFT_RESET_TX_IN,
+        soft_reset_rx_in                =>      SOFT_RESET_RX_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+        gt1_tx_fsm_reset_done_out       =>      gt1_tx_fsm_reset_done_out,
+        gt1_rx_fsm_reset_done_out       =>      gt1_rx_fsm_reset_done_out,
+        gt1_data_valid_in               =>      gt1_data_valid_in,
+        gt2_tx_fsm_reset_done_out       =>      gt2_tx_fsm_reset_done_out,
+        gt2_rx_fsm_reset_done_out       =>      gt2_rx_fsm_reset_done_out,
+        gt2_data_valid_in               =>      gt2_data_valid_in,
+        gt3_tx_fsm_reset_done_out       =>      gt3_tx_fsm_reset_done_out,
+        gt3_rx_fsm_reset_done_out       =>      gt3_rx_fsm_reset_done_out,
+        gt3_data_valid_in               =>      gt3_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y12)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      tied_to_ground_i,
+        gt0_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT1  (X1Y13)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt1_cpllfbclklost_out           =>      gt1_cpllfbclklost_out,
+        gt1_cplllock_out                =>      gt1_cplllock_out,
+        gt1_cplllockdetclk_in           =>      sysclk_in_i,
+        gt1_cpllreset_in                =>      gt1_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt1_gtrefclk0_in                =>      tied_to_ground_i,
+        gt1_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt1_drpaddr_in                  =>      gt1_drpaddr_in,
+        gt1_drpclk_in                   =>      sysclk_in_i,
+        gt1_drpdi_in                    =>      gt1_drpdi_in,
+        gt1_drpdo_out                   =>      gt1_drpdo_out,
+        gt1_drpen_in                    =>      gt1_drpen_in,
+        gt1_drprdy_out                  =>      gt1_drprdy_out,
+        gt1_drpwe_in                    =>      gt1_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt1_dmonitorout_out             =>      gt1_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt1_eyescanreset_in             =>      gt1_eyescanreset_in,
+        gt1_rxuserrdy_in                =>      gt1_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt1_eyescandataerror_out        =>      gt1_eyescandataerror_out,
+        gt1_eyescantrigger_in           =>      gt1_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt1_rxusrclk_in                 =>      gt1_rxusrclk_i,
+        gt1_rxusrclk2_in                =>      gt1_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt1_rxdata_out                  =>      gt1_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt1_rxdisperr_out               =>      gt1_rxdisperr_out,
+        gt1_rxnotintable_out            =>      gt1_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt1_gtxrxp_in                   =>      gt1_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt1_gtxrxn_in                   =>      gt1_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt1_rxphmonitor_out             =>      gt1_rxphmonitor_out,
+        gt1_rxphslipmonitor_out         =>      gt1_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt1_rxdfelpmreset_in            =>      gt1_rxdfelpmreset_in,
+        gt1_rxmonitorout_out            =>      gt1_rxmonitorout_out,
+        gt1_rxmonitorsel_in             =>      gt1_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt1_rxoutclk_out                =>      gt1_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt1_gtrxreset_in                =>      gt1_gtrxreset_in,
+        gt1_rxpmareset_in               =>      gt1_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt1_rxcharisk_out               =>      gt1_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt1_rxresetdone_out             =>      gt1_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt1_gttxreset_in                =>      gt1_gttxreset_in,
+        gt1_txuserrdy_in                =>      gt1_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt1_txusrclk_in                 =>      gt1_txusrclk_i,
+        gt1_txusrclk2_in                =>      gt1_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt1_txdata_in                   =>      gt1_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt1_gtxtxn_out                  =>      gt1_gtxtxn_out,
+        gt1_gtxtxp_out                  =>      gt1_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt1_txoutclk_out                =>      gt1_txoutclk_i,
+        gt1_txoutclkfabric_out          =>      gt1_txoutclkfabric_out,
+        gt1_txoutclkpcs_out             =>      gt1_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt1_txcharisk_in                =>      gt1_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt1_txresetdone_out             =>      gt1_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT2  (X1Y14)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt2_cpllfbclklost_out           =>      gt2_cpllfbclklost_out,
+        gt2_cplllock_out                =>      gt2_cplllock_out,
+        gt2_cplllockdetclk_in           =>      sysclk_in_i,
+        gt2_cpllreset_in                =>      gt2_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt2_gtrefclk0_in                =>      tied_to_ground_i,
+        gt2_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt2_drpaddr_in                  =>      gt2_drpaddr_in,
+        gt2_drpclk_in                   =>      sysclk_in_i,
+        gt2_drpdi_in                    =>      gt2_drpdi_in,
+        gt2_drpdo_out                   =>      gt2_drpdo_out,
+        gt2_drpen_in                    =>      gt2_drpen_in,
+        gt2_drprdy_out                  =>      gt2_drprdy_out,
+        gt2_drpwe_in                    =>      gt2_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt2_dmonitorout_out             =>      gt2_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt2_eyescanreset_in             =>      gt2_eyescanreset_in,
+        gt2_rxuserrdy_in                =>      gt2_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt2_eyescandataerror_out        =>      gt2_eyescandataerror_out,
+        gt2_eyescantrigger_in           =>      gt2_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt2_rxusrclk_in                 =>      gt2_rxusrclk_i,
+        gt2_rxusrclk2_in                =>      gt2_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt2_rxdata_out                  =>      gt2_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt2_rxdisperr_out               =>      gt2_rxdisperr_out,
+        gt2_rxnotintable_out            =>      gt2_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt2_gtxrxp_in                   =>      gt2_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt2_gtxrxn_in                   =>      gt2_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt2_rxphmonitor_out             =>      gt2_rxphmonitor_out,
+        gt2_rxphslipmonitor_out         =>      gt2_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt2_rxdfelpmreset_in            =>      gt2_rxdfelpmreset_in,
+        gt2_rxmonitorout_out            =>      gt2_rxmonitorout_out,
+        gt2_rxmonitorsel_in             =>      gt2_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt2_rxoutclk_out                =>      gt2_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt2_gtrxreset_in                =>      gt2_gtrxreset_in,
+        gt2_rxpmareset_in               =>      gt2_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt2_rxcharisk_out               =>      gt2_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt2_rxresetdone_out             =>      gt2_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt2_gttxreset_in                =>      gt2_gttxreset_in,
+        gt2_txuserrdy_in                =>      gt2_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt2_txusrclk_in                 =>      gt2_txusrclk_i,
+        gt2_txusrclk2_in                =>      gt2_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt2_txdata_in                   =>      gt2_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt2_gtxtxn_out                  =>      gt2_gtxtxn_out,
+        gt2_gtxtxp_out                  =>      gt2_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt2_txoutclk_out                =>      gt2_txoutclk_i,
+        gt2_txoutclkfabric_out          =>      gt2_txoutclkfabric_out,
+        gt2_txoutclkpcs_out             =>      gt2_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt2_txcharisk_in                =>      gt2_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt2_txresetdone_out             =>      gt2_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT3  (X1Y15)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt3_cpllfbclklost_out           =>      gt3_cpllfbclklost_out,
+        gt3_cplllock_out                =>      gt3_cplllock_out,
+        gt3_cplllockdetclk_in           =>      sysclk_in_i,
+        gt3_cpllreset_in                =>      gt3_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt3_gtrefclk0_in                =>      tied_to_ground_i,
+        gt3_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt3_drpaddr_in                  =>      gt3_drpaddr_in,
+        gt3_drpclk_in                   =>      sysclk_in_i,
+        gt3_drpdi_in                    =>      gt3_drpdi_in,
+        gt3_drpdo_out                   =>      gt3_drpdo_out,
+        gt3_drpen_in                    =>      gt3_drpen_in,
+        gt3_drprdy_out                  =>      gt3_drprdy_out,
+        gt3_drpwe_in                    =>      gt3_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt3_dmonitorout_out             =>      gt3_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt3_eyescanreset_in             =>      gt3_eyescanreset_in,
+        gt3_rxuserrdy_in                =>      gt3_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt3_eyescandataerror_out        =>      gt3_eyescandataerror_out,
+        gt3_eyescantrigger_in           =>      gt3_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt3_rxusrclk_in                 =>      gt3_rxusrclk_i,
+        gt3_rxusrclk2_in                =>      gt3_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt3_rxdata_out                  =>      gt3_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt3_rxdisperr_out               =>      gt3_rxdisperr_out,
+        gt3_rxnotintable_out            =>      gt3_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt3_gtxrxp_in                   =>      gt3_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt3_gtxrxn_in                   =>      gt3_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt3_rxphmonitor_out             =>      gt3_rxphmonitor_out,
+        gt3_rxphslipmonitor_out         =>      gt3_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt3_rxdfelpmreset_in            =>      gt3_rxdfelpmreset_in,
+        gt3_rxmonitorout_out            =>      gt3_rxmonitorout_out,
+        gt3_rxmonitorsel_in             =>      gt3_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt3_rxoutclk_out                =>      gt3_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt3_gtrxreset_in                =>      gt3_gtrxreset_in,
+        gt3_rxpmareset_in               =>      gt3_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt3_rxcharisk_out               =>      gt3_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt3_rxresetdone_out             =>      gt3_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt3_gttxreset_in                =>      gt3_gttxreset_in,
+        gt3_txuserrdy_in                =>      gt3_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt3_txusrclk_in                 =>      gt3_txusrclk_i,
+        gt3_txusrclk2_in                =>      gt3_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt3_txdata_in                   =>      gt3_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt3_gtxtxn_out                  =>      gt3_gtxtxn_out,
+        gt3_gtxtxp_out                  =>      gt3_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt3_txoutclk_out                =>      gt3_txoutclk_i,
+        gt3_txoutclkfabric_out          =>      gt3_txoutclkfabric_out,
+        gt3_txoutclkpcs_out             =>      gt3_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt3_txcharisk_in                =>      gt3_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt3_txresetdone_out             =>      gt3_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput/GTX_SODAinput.xci b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput/GTX_SODAinput.xci
new file mode 100644
index 0000000..2bb4ad0
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput/GTX_SODAinput.xci
@@ -0,0 +1,1242 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>GTX_SODAinput</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gtwizard" spirit:version="3.5"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">GTX_SODAinput</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">GTX_SODAinput</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_tx_pll" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_rx_pll" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt15_val" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt15_val_tx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt15_val_rx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_encoding" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_decoding" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_drp_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txbuf_en" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txoutclk_source" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxbuf_en" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxusrclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_comma_preset" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_align_comma_word" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxslide" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_dfe_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxslide_mode" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput.vhd
new file mode 100644
index 0000000..1af7506
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput.vhd
@@ -0,0 +1,403 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_sodainput.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_SODAinput (a Core Top)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_SODAinput is
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end GTX_SODAinput;
+
+architecture RTL of GTX_SODAinput is
+    attribute DowngradeIPIdentifiedWarnings: string;
+    attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+    attribute X_CORE_INFO : string;
+    attribute X_CORE_INFO of RTL : architecture is "GTX_SODAinput,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_SODAinput,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+--**************************Component Declarations*****************************
+
+component GTX_SODAinput_init 
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    EXAMPLE_SIMULATION                      : integer   := 0;          -- Set to 1 for simulation
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+ 
+    STABLE_CLOCK_PERIOD                     : integer   := 10;  
+        -- Set to 1 for simulation
+    EXAMPLE_USE_CHIPSCOPE                   : integer   := 1       --// Modified       -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end component;
+ 
+--**************************** Main Body of Code *******************************
+begin
+    U0 : GTX_SODAinput_init
+    generic map
+(
+        EXAMPLE_SIM_GTRESET_SPEEDUP   => "TRUE",
+        EXAMPLE_SIMULATION            => 0,
+ 
+        USE_BUFG           => 0,
+ 
+        STABLE_CLOCK_PERIOD           => 10,
+        EXAMPLE_USE_CHIPSCOPE         => 1 --// Modified
+)
+port map
+(
+        SYSCLK_IN                       =>      SYSCLK_IN,
+        SOFT_RESET_TX_IN                =>      SOFT_RESET_TX_IN,
+        SOFT_RESET_RX_IN                =>      SOFT_RESET_RX_IN,
+        DONT_RESET_ON_DATA_ERROR_IN     =>      DONT_RESET_ON_DATA_ERROR_IN,
+    GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
+    GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT,
+    GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
+    GT0_TX_MMCM_LOCK_IN => GT0_TX_MMCM_LOCK_IN,
+    GT0_TX_MMCM_RESET_OUT => GT0_TX_MMCM_RESET_OUT,
+
+    --_________________________________________________________________________
+    --GT0  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      gt0_cplllockdetclk_in,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+    -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      gt0_gtrefclk0_in,
+        gt0_gtrefclk1_in                =>      gt0_gtrefclk1_in,
+    ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      gt0_drpclk_in,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+    --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+    --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+    -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+	------------------------- Receive Ports - CDR Ports ------------------------
+		GT0_RXCDRRESET_IN               => GT0_RXCDRRESET_IN, --// Modified
+		GT0_RXCDRLOCK_OUT               => GT0_RXCDRLOCK_OUT, --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_in,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_in,
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+    --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_out,
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+    --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_in,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_in,
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_out,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  => GT0_QPLLOUTCLK_IN,
+     GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN 
+
+);
+ 
+end RTL;    
+ 
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_auto_phase_align.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_auto_phase_align.vhd
new file mode 100644
index 0000000..4609431
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_auto_phase_align.vhd
@@ -0,0 +1,198 @@
+--//////////////////////////////////////////////////////////////////////////////
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_sodainput_auto_phase_align.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description : The logic below implements the procedure to do automatic phase-alignment 
+--                on the 7-series GTX as described in ug476pdf, version 1.3,
+--                Chapters "Using the TX Phase Alignment to Bypass the TX Buffer"
+--                and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer"
+--                Should the logic below differ from what is described in a later version  
+--                of the user-guide, you are using an auto-alignment block, which is 
+--                out of date and needs to be updated for safe operation.
+--                     
+--
+--
+-- Module GTX_SODAinput_AUTO_PHASE_ALIGN
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity GTX_SODAinput_AUTO_PHASE_ALIGN is     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RUN_PHALIGNMENT          : in  STD_LOGIC;              --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Auto phase-alignment performed sucessfully
+           PHALIGNDONE              : in  STD_LOGIC;              --\ Phase-alignment signals from and to the
+           DLYSRESET                : out STD_LOGIC;              -- |transceiver.
+           DLYSRESETDONE            : in  STD_LOGIC;              --/
+           RECCLKSTABLE             : in  STD_LOGIC               --/on the RX-side.
+           
+           );
+end GTX_SODAinput_AUTO_PHASE_ALIGN;
+
+architecture RTL of GTX_SODAinput_AUTO_PHASE_ALIGN is
+
+  component GTX_SODAinput_sync_block
+   generic (
+     INITIALISE : bit_vector(5 downto 0) := "000000"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+  type phase_align_auto_fsm is(
+    INIT, WAIT_PHRST_DONE, COUNT_PHALIGN_DONE, PHALIGN_DONE
+    );
+    
+  signal phalign_state       : phase_align_auto_fsm := INIT;
+  signal phaligndone_prev     : std_logic := '0';
+  signal phaligndone_ris_edge : std_logic;
+
+  signal count_phalign_edges   : integer range 0 to 3:= 0;
+  signal phaligndone_sync      : std_logic := '0';
+  signal dlysresetdone_sync    : std_logic := '0';
+
+begin
+
+ sync_PHALIGNDONE : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  PHALIGNDONE,
+            data_out        =>  phaligndone_sync 
+         );
+
+  sync_DLYSRESETDONE : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  DLYSRESETDONE,
+            data_out        =>  dlysresetdone_sync 
+         );
+
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      phaligndone_prev <= phaligndone_sync; 
+    end if;
+  end process;
+  phaligndone_ris_edge <= '1' when (phaligndone_prev = '0') and (phaligndone_sync = '1') else '0';
+  
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if RUN_PHALIGNMENT = '0' or RECCLKSTABLE = '0' then
+        DLYSRESET           <= '0';
+        count_phalign_edges   <= 0;
+        PHASE_ALIGNMENT_DONE  <= '0';
+        phalign_state      <= INIT;
+      else
+        if phaligndone_ris_edge = '1' then
+          if count_phalign_edges < 3 then
+            count_phalign_edges <= count_phalign_edges + 1;
+          end if;
+        end if;
+        
+        DLYSRESET         <= '0';
+                  
+        case phalign_state is
+          when INIT => 
+            PHASE_ALIGNMENT_DONE <= '0';
+            if RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1' then
+              --DLYSRESET is toggled to '1'
+              DLYSRESET  <= '1';
+              phalign_state <= WAIT_PHRST_DONE;
+            end if;           
+            
+          when WAIT_PHRST_DONE =>
+            if dlysresetdone_sync = '1' then
+              phalign_state <= COUNT_PHALIGN_DONE;
+            end if;
+            --No timeout-check here as that is done in the main FSM
+            
+          when COUNT_PHALIGN_DONE =>
+            if (count_phalign_edges = 2) then
+
+              --For GTX: Only on the second edge of the PHALIGNDONE-signal the 
+              --         phase-alignment is completed
+              --For GTH, GTP: TXSYNCDONE indicates the completion of Phase Alignment
+
+              phalign_state <= PHALIGN_DONE;
+            end if;
+          
+          when PHALIGN_DONE =>
+            PHASE_ALIGNMENT_DONE <= '1';
+
+          when OTHERS =>
+            phalign_state      <= INIT;
+
+        end case;        
+      end if;      
+    end if;    
+  end process;
+
+end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_cpll_railing.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_cpll_railing.vhd
new file mode 100644
index 0000000..2f7620e
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_cpll_railing.vhd
@@ -0,0 +1,144 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_sodainput_cpll_railing.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_SODAinput_cpll_railing
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity GTX_SODAinput_cpll_railing is
+generic( USE_BUFG       : integer := 0
+       );
+   port  (
+         cpll_reset_out : out std_logic;
+         cpll_pd_out : out std_logic;
+         refclk_out : out std_logic;
+        
+         refclk_in : in std_logic
+          );
+   end GTX_SODAinput_cpll_railing;
+
+
+architecture RTL of GTX_SODAinput_cpll_railing is
+
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+attribute equivalent_register_removal: string; 
+signal cpllpd_wait    :   std_logic_vector(95 downto 0)  := x"FFFFFFFFFFFFFFFFFFFFFFFF";
+signal cpllreset_wait :   std_logic_vector(127 downto 0) := x"000000000000000000000000000000FF";
+attribute equivalent_register_removal of cpllpd_wait : signal is "no";
+attribute equivalent_register_removal of cpllreset_wait : signal is "no";
+signal    gtrefclk0_i      :std_logic ;
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+  use_bufg_cpll:if(USE_BUFG = 1) generate
+  refclk_buf : BUFG
+  port map
+   (O   => gtrefclk0_i,
+    I   => refclk_in);
+
+  end generate;
+
+  use_bufr_cpll:if(USE_BUFG = 0) generate
+  refclk_buf : BUFR
+  port map
+   (O   => gtrefclk0_i,
+    CE  => tied_to_vcc_i,
+    CLR => tied_to_ground_i,
+    I   => refclk_in);
+
+  end generate;
+
+    process( gtrefclk0_i )
+    begin
+        if(gtrefclk0_i'event and gtrefclk0_i = '1') then 
+           cpllpd_wait <= cpllpd_wait(94 downto 0) & '0';
+           cpllreset_wait <= cpllreset_wait(126 downto 0) & '0';
+         end if;
+    end process;
+
+cpll_pd_out <= cpllpd_wait(95);
+cpll_reset_out <= cpllreset_wait(127);
+refclk_out <= gtrefclk0_i;
+
+
+ end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_gt.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_gt.vhd
new file mode 100644
index 0000000..f26f9e4
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_gt.vhd
@@ -0,0 +1,834 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_sodainput_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_SODAinput_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity GTX_SODAinput_GT is
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP    : string     :=  "FALSE";        -- Set to "TRUE" to speed up sim reset
+    RX_DFE_KL_CFG2_IN         : bit_vector :=   X"301148AC";
+    SIM_CPLLREFCLK_SEL        : bit_vector :=   "001";
+    PMA_RSV_IN                : bit_vector :=  x"00018480";
+    PCS_RSVD_ATTR_IN          : bit_vector :=   X"000000000000"
+);
+port 
+(
+     cpllpd_in : in std_logic;
+     cpllrefclksel_in : in std_logic_vector(2 downto 0);
+    --------------------------------- CPLL Ports -------------------------------
+    cpllfbclklost_out                       : out  std_logic;
+    cplllock_out                            : out  std_logic;
+    cplllockdetclk_in                       : in   std_logic;
+    cpllrefclklost_out                      : out  std_logic;
+    cpllreset_in                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gtrefclk0_in                            : in   std_logic;
+    gtrefclk1_in                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    drpaddr_in                              : in   std_logic_vector(8 downto 0);
+    drpclk_in                               : in   std_logic;
+    drpdi_in                                : in   std_logic_vector(15 downto 0);
+    drpdo_out                               : out  std_logic_vector(15 downto 0);
+    drpen_in                                : in   std_logic;
+    drprdy_out                              : out  std_logic;
+    drpwe_in                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    qpllclk_in                              : in   std_logic;
+    qpllrefclk_in                           : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    dmonitorout_out                         : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    eyescanreset_in                         : in   std_logic;
+    rxuserrdy_in                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    eyescandataerror_out                    : out  std_logic;
+    eyescantrigger_in                       : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	RXCDRRESET_IN                           : in  std_logic; --// Modified
+    RXCDRLOCK_OUT                           : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    rxusrclk_in                             : in   std_logic;
+    rxusrclk2_in                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    rxdata_out                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    rxdisperr_out                           : out  std_logic_vector(1 downto 0);
+    rxnotintable_out                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gtxrxp_in                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gtxrxn_in                               : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    rxdlyen_in                              : in   std_logic;
+    rxdlysreset_in                          : in   std_logic;
+    rxdlysresetdone_out                     : out  std_logic;
+    rxphalign_in                            : in   std_logic;
+    rxphaligndone_out                       : out  std_logic;
+    rxphalignen_in                          : in   std_logic;
+    rxphdlyreset_in                         : in   std_logic;
+    rxphmonitor_out                         : out  std_logic_vector(4 downto 0);
+    rxphslipmonitor_out                     : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    rxlpmhfhold_in                          : in   std_logic;
+    rxlpmlfhold_in                          : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    rxdfelpmreset_in                        : in   std_logic;
+    rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
+    rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    rxoutclk_out                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gtrxreset_in                            : in   std_logic;
+    rxpmareset_in                           : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    rxcharisk_out                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    rxresetdone_out                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gttxreset_in                            : in   std_logic;
+    txuserrdy_in                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    txusrclk_in                             : in   std_logic;
+    txusrclk2_in                            : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    txdlyen_in                              : in   std_logic;
+    txdlysreset_in                          : in   std_logic;
+    txdlysresetdone_out                     : out  std_logic;
+    txphalign_in                            : in   std_logic;
+    txphaligndone_out                       : out  std_logic;
+    txphalignen_in                          : in   std_logic;
+    txphdlyreset_in                         : in   std_logic;
+    txphinit_in                             : in   std_logic;
+    txphinitdone_out                        : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    txdata_in                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gtxtxn_out                              : out  std_logic;
+    gtxtxp_out                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    txoutclk_out                            : out  std_logic;
+    txoutclkfabric_out                      : out  std_logic;
+    txoutclkpcs_out                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    txcharisk_in                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    txresetdone_out                         : out  std_logic
+
+
+);
+
+
+end GTX_SODAinput_GT;
+
+architecture RTL of GTX_SODAinput_GT is
+   
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+
+
+    -- RX Datapath signals
+    signal rxdata_i                         :   std_logic_vector(63 downto 0);      
+    signal rxchariscomma_float_i            :   std_logic_vector(5 downto 0);
+    signal rxcharisk_float_i                :   std_logic_vector(5 downto 0);
+    signal rxdisperr_float_i                :   std_logic_vector(5 downto 0);
+    signal rxnotintable_float_i             :   std_logic_vector(5 downto 0);
+    signal rxrundisp_float_i                :   std_logic_vector(5 downto 0);
+
+
+    -- TX Datapath signals
+    signal txdata_i                         :   std_logic_vector(63 downto 0);
+    signal txkerr_float_i                   :   std_logic_vector(5 downto 0);
+    signal txrundisp_float_i                :   std_logic_vector(5 downto 0);
+    signal rxstartofseq_float_i             :   std_logic;
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+    -------------------  GT Datapath byte mapping  -----------------
+    RXDATA_OUT    <=   rxdata_i(15 downto 0);
+
+    txdata_i    <=   (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
+
+
+
+    ----------------------------- GTXE2 Instance  --------------------------   
+
+    gtxe2_i :GTXE2_CHANNEL
+    generic map
+    (
+
+        --_______________________ Simulation-Only Attributes ___________________
+
+        SIM_RECEIVER_DETECT_PASS   =>      ("TRUE"),
+        SIM_RESET_SPEEDUP          =>      (GT_SIM_GTRESET_SPEEDUP),
+        SIM_TX_EIDLE_DRIVE_LEVEL   =>      ("X"),
+        SIM_CPLLREFCLK_SEL         =>      (SIM_CPLLREFCLK_SEL),
+        SIM_VERSION                =>      ("4.0"), 
+        
+
+       ------------------RX Byte and Word Alignment Attributes---------------
+        ALIGN_COMMA_DOUBLE                      =>     ("FALSE"),
+        ALIGN_COMMA_ENABLE                      =>     ("1111111111"),
+        ALIGN_COMMA_WORD                        =>     (1),
+        ALIGN_MCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_MCOMMA_VALUE                      =>     ("1010000011"),
+        ALIGN_PCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_PCOMMA_VALUE                      =>     ("0101111100"),
+        SHOW_REALIGN_COMMA                      =>     ("FALSE"), --//("TRUE"), Modified
+        RXSLIDE_AUTO_WAIT                       =>     (7),
+        RXSLIDE_MODE                            =>     ("AUTO"), --// ("PCS"), Modified
+        RX_SIG_VALID_DLY                        =>     (10),
+
+       ------------------RX 8B/10B Decoder Attributes---------------
+        RX_DISPERR_SEQ_MATCH                    =>     ("TRUE"),
+        DEC_MCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_PCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_VALID_COMMA_ONLY                    =>     ("FALSE"),
+
+       ------------------------RX Clock Correction Attributes----------------------
+        CBCC_DATA_SOURCE_SEL                    =>     ("DECODED"),
+        CLK_COR_SEQ_2_USE                       =>     ("FALSE"),
+        CLK_COR_KEEP_IDLE                       =>     ("FALSE"),
+        CLK_COR_MAX_LAT                         =>     (9),
+        CLK_COR_MIN_LAT                         =>     (7),
+        CLK_COR_PRECEDENCE                      =>     ("TRUE"),
+        CLK_COR_REPEAT_WAIT                     =>     (0),
+        CLK_COR_SEQ_LEN                         =>     (1),
+        CLK_COR_SEQ_1_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_1_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_1_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_4                         =>     ("0000000000"),
+        CLK_CORRECT_USE                         =>     ("FALSE"),
+        CLK_COR_SEQ_2_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_2_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_2_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_4                         =>     ("0000000000"),
+
+       ------------------------RX Channel Bonding Attributes----------------------
+        CHAN_BOND_KEEP_ALIGN                    =>     ("FALSE"),
+        CHAN_BOND_MAX_SKEW                      =>     (1),
+        CHAN_BOND_SEQ_LEN                       =>     (1),
+        CHAN_BOND_SEQ_1_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_USE                     =>     ("FALSE"),
+        FTS_DESKEW_SEQ_ENABLE                   =>     ("1111"),
+        FTS_LANE_DESKEW_CFG                     =>     ("1111"),
+        FTS_LANE_DESKEW_EN                      =>     ("FALSE"),
+
+       ---------------------------RX Margin Analysis Attributes----------------------------
+        ES_CONTROL                              =>     ("000000"),
+        ES_ERRDET_EN                            =>     ("FALSE"),
+        ES_EYE_SCAN_EN                          =>     ("TRUE"),
+        ES_HORZ_OFFSET                          =>     (x"000"),
+        ES_PMA_CFG                              =>     ("0000000000"),
+        ES_PRESCALE                             =>     ("00000"),
+        ES_QUALIFIER                            =>     (x"00000000000000000000"),
+        ES_QUAL_MASK                            =>     (x"00000000000000000000"),
+        ES_SDATA_MASK                           =>     (x"00000000000000000000"),
+        ES_VERT_OFFSET                          =>     ("000000000"),
+
+       -------------------------FPGA RX Interface Attributes-------------------------
+        RX_DATA_WIDTH                           =>     (20),
+
+       ---------------------------PMA Attributes----------------------------
+        OUTREFCLK_SEL_INV                       =>     ("11"),
+        PMA_RSV                                 =>     (PMA_RSV_IN),
+        PMA_RSV2                                =>     (x"2050"),
+        PMA_RSV3                                =>     ("00"),
+        PMA_RSV4                                =>     (x"00000000"),
+        RX_BIAS_CFG                             =>     ("000000000100"),
+        DMONITOR_CFG                            =>     (x"000A00"),
+        RX_CM_SEL                               =>     ("00"),
+        RX_CM_TRIM                              =>     ("010"),
+        RX_DEBUG_CFG                            =>     ("000000000000"),
+        RX_OS_CFG                               =>     ("0000010000000"),
+        TERM_RCAL_CFG                           =>     ("10000"),
+        TERM_RCAL_OVRD                          =>     ('0'),
+        TST_RSV                                 =>     (x"00000000"),
+        RX_CLK25_DIV                            =>     (10),
+        TX_CLK25_DIV                            =>     (10),
+        UCODEER_CLR                             =>     ('0'),
+
+       ---------------------------PCI Express Attributes----------------------------
+        PCS_PCIE_EN                             =>     ("FALSE"),
+
+       ---------------------------PCS Attributes----------------------------
+        PCS_RSVD_ATTR                           =>     (PCS_RSVD_ATTR_IN),
+
+       -------------RX Buffer Attributes------------
+        RXBUF_ADDR_MODE                         =>     ("FAST"),
+        RXBUF_EIDLE_HI_CNT                      =>     ("1000"),
+        RXBUF_EIDLE_LO_CNT                      =>     ("0000"),
+        RXBUF_EN                                =>     ("FALSE"),
+        RX_BUFFER_CFG                           =>     ("000000"),
+        RXBUF_RESET_ON_CB_CHANGE                =>     ("TRUE"),
+        RXBUF_RESET_ON_COMMAALIGN               =>     ("FALSE"),
+        RXBUF_RESET_ON_EIDLE                    =>     ("FALSE"),
+        RXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        RXBUFRESET_TIME                         =>     ("00001"),
+        RXBUF_THRESH_OVFLW                      =>     (61),
+        RXBUF_THRESH_OVRD                       =>     ("FALSE"),
+        RXBUF_THRESH_UNDFLW                     =>     (4),
+        RXDLY_CFG                               =>     (x"001F"),
+        RXDLY_LCFG                              =>     (x"030"),
+        RXDLY_TAP_CFG                           =>     (x"0000"),
+        RXPH_CFG                                =>     (x"000000"),
+        RXPHDLY_CFG                             =>     (x"084020"),
+        RXPH_MONITOR_SEL                        =>     ("00000"),
+        RX_XCLK_SEL                             =>     ("RXUSR"),
+        RX_DDI_SEL                              =>     ("000000"),
+        RX_DEFER_RESET_BUF_EN                   =>     ("TRUE"),
+
+       -----------------------CDR Attributes-------------------------
+
+       --For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
+
+       --For Display Port, HBR2 -   set RXCDR_CFG=72'h038c008bff20200010
+
+       --For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
+
+       --For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
+
+       --For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
+
+       --For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
+
+       --For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
+
+       --For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
+        RXCDR_CFG                               =>     (x"03000023ff10200020"),
+        RXCDR_FR_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_HOLD_DURING_EIDLE                 =>     ('0'),
+        RXCDR_PH_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_LOCK_CFG                          =>     ("010101"),
+
+       -------------------RX Initialization and Reset Attributes-------------------
+        RXCDRFREQRESET_TIME                     =>     ("00001"),
+        RXCDRPHRESET_TIME                       =>     ("00001"),
+        RXISCANRESET_TIME                       =>     ("00001"),
+        RXPCSRESET_TIME                         =>     ("00001"),
+        RXPMARESET_TIME                         =>     ("00011"),
+
+       -------------------RX OOB Signaling Attributes-------------------
+        RXOOB_CFG                               =>     ("0000110"),
+
+       -------------------------RX Gearbox Attributes---------------------------
+        RXGEARBOX_EN                            =>     ("FALSE"),
+        GEARBOX_MODE                            =>     ("000"),
+
+       -------------------------PRBS Detection Attribute-----------------------
+        RXPRBS_ERR_LOOPBACK                     =>     ('0'),
+
+       -------------Power-Down Attributes----------
+        PD_TRANS_TIME_FROM_P2                   =>     (x"03c"),
+        PD_TRANS_TIME_NONE_P2                   =>     (x"3c"),
+        PD_TRANS_TIME_TO_P2                     =>     (x"64"),
+
+       -------------RX OOB Signaling Attributes----------
+        SAS_MAX_COM                             =>     (64),
+        SAS_MIN_COM                             =>     (36),
+        SATA_BURST_SEQ_LEN                      =>     ("0101"),
+        SATA_BURST_VAL                          =>     ("100"),
+        SATA_EIDLE_VAL                          =>     ("100"),
+        SATA_MAX_BURST                          =>     (8),
+        SATA_MAX_INIT                           =>     (21),
+        SATA_MAX_WAKE                           =>     (7),
+        SATA_MIN_BURST                          =>     (4),
+        SATA_MIN_INIT                           =>     (12),
+        SATA_MIN_WAKE                           =>     (4),
+
+       -------------RX Fabric Clock Output Control Attributes----------
+        TRANS_TIME_RATE                         =>     (x"0E"),
+
+       --------------TX Buffer Attributes----------------
+        TXBUF_EN                                =>     ("FALSE"),
+        TXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        TXDLY_CFG                               =>     (x"001F"),
+        TXDLY_LCFG                              =>     (x"030"),
+        TXDLY_TAP_CFG                           =>     (x"0000"),
+        TXPH_CFG                                =>     (x"0780"),
+        TXPHDLY_CFG                             =>     (x"084020"),
+        TXPH_MONITOR_SEL                        =>     ("00000"),
+        TX_XCLK_SEL                             =>     ("TXUSR"),
+
+       -------------------------FPGA TX Interface Attributes-------------------------
+        TX_DATA_WIDTH                           =>     (20),
+
+       -------------------------TX Configurable Driver Attributes-------------------------
+        TX_DEEMPH0                              =>     ("00000"),
+        TX_DEEMPH1                              =>     ("00000"),
+        TX_EIDLE_ASSERT_DELAY                   =>     ("110"),
+        TX_EIDLE_DEASSERT_DELAY                 =>     ("100"),
+        TX_LOOPBACK_DRIVE_HIZ                   =>     ("FALSE"),
+        TX_MAINCURSOR_SEL                       =>     ('0'),
+        TX_DRIVE_MODE                           =>     ("DIRECT"),
+        TX_MARGIN_FULL_0                        =>     ("1001110"),
+        TX_MARGIN_FULL_1                        =>     ("1001001"),
+        TX_MARGIN_FULL_2                        =>     ("1000101"),
+        TX_MARGIN_FULL_3                        =>     ("1000010"),
+        TX_MARGIN_FULL_4                        =>     ("1000000"),
+        TX_MARGIN_LOW_0                         =>     ("1000110"),
+        TX_MARGIN_LOW_1                         =>     ("1000100"),
+        TX_MARGIN_LOW_2                         =>     ("1000010"),
+        TX_MARGIN_LOW_3                         =>     ("1000000"),
+        TX_MARGIN_LOW_4                         =>     ("1000000"),
+
+       -------------------------TX Gearbox Attributes--------------------------
+        TXGEARBOX_EN                            =>     ("FALSE"),
+
+       -------------------------TX Initialization and Reset Attributes--------------------------
+        TXPCSRESET_TIME                         =>     ("00001"),
+        TXPMARESET_TIME                         =>     ("00001"),
+
+       -------------------------TX Receiver Detection Attributes--------------------------
+        TX_RXDETECT_CFG                         =>     (x"1832"),
+        TX_RXDETECT_REF                         =>     ("100"),
+
+       ----------------------------CPLL Attributes----------------------------
+        CPLL_CFG                                =>     (x"BC07DC"),
+        CPLL_FBDIV                              =>     (2),
+        CPLL_FBDIV_45                           =>     (4),
+        CPLL_INIT_CFG                           =>     (x"00001E"),
+        CPLL_LOCK_CFG                           =>     (x"01E8"),
+        CPLL_REFCLK_DIV                         =>     (1),
+        RXOUT_DIV                               =>     (2),
+        TXOUT_DIV                               =>     (2),
+        SATA_CPLL_CFG                           =>     ("VCO_3000MHZ"),
+
+       --------------RX Initialization and Reset Attributes-------------
+        RXDFELPMRESET_TIME                      =>     ("0001111"),
+
+       --------------RX Equalizer Attributes-------------
+        RXLPM_HF_CFG                            =>     ("00000011110000"),
+        RXLPM_LF_CFG                            =>     ("00000011110000"),
+        RX_DFE_GAIN_CFG                         =>     (x"020FEA"),
+        RX_DFE_H2_CFG                           =>     ("000000000000"),
+        RX_DFE_H3_CFG                           =>     ("000001000000"),
+        RX_DFE_H4_CFG                           =>     ("00011110000"),
+        RX_DFE_H5_CFG                           =>     ("00011100000"),
+        RX_DFE_KL_CFG                           =>     ("0000011111110"),
+        RX_DFE_LPM_CFG                          =>     (x"0904"),
+        RX_DFE_LPM_HOLD_DURING_EIDLE            =>     ('0'),
+        RX_DFE_UT_CFG                           =>     ("10001111000000000"),
+        RX_DFE_VP_CFG                           =>     ("00011111100000011"),
+
+       -------------------------Power-Down Attributes-------------------------
+        RX_CLKMUX_PD                            =>     ('1'),
+        TX_CLKMUX_PD                            =>     ('1'),
+
+       -------------------------FPGA RX Interface Attribute-------------------------
+        RX_INT_DATAWIDTH                        =>     (0),
+
+       -------------------------FPGA TX Interface Attribute-------------------------
+        TX_INT_DATAWIDTH                        =>     (0),
+
+       ------------------TX Configurable Driver Attributes---------------
+        TX_QPI_STATUS_EN                        =>     ('0'),
+
+       -------------------------RX Equalizer Attributes--------------------------
+        RX_DFE_KL_CFG2                          =>     (RX_DFE_KL_CFG2_IN),
+        RX_DFE_XYD_CFG                          =>     ("0000000000000"),
+
+       -------------------------TX Configurable Driver Attributes--------------------------
+        TX_PREDRIVER_MODE                       =>     ('0')
+
+
+    )
+    port map
+    (
+        --------------------------------- CPLL Ports -------------------------------
+        CPLLFBCLKLOST                   =>      cpllfbclklost_out,
+        CPLLLOCK                        =>      cplllock_out,
+        CPLLLOCKDETCLK                  =>      cplllockdetclk_in,
+        CPLLLOCKEN                      =>      tied_to_vcc_i,
+        CPLLPD                          =>      cpllpd_in,
+        CPLLREFCLKLOST                  =>      cpllrefclklost_out,
+        CPLLREFCLKSEL                   =>      cpllrefclksel_in,
+        CPLLRESET                       =>      cpllreset_in,
+        GTRSVD                          =>      "0000000000000000",
+        PCSRSVDIN                       =>      "0000000000000000",
+        PCSRSVDIN2                      =>      "00000",
+        PMARSVDIN                       =>      "00000",
+        PMARSVDIN2                      =>      "00000",
+        TSTIN                           =>      "11111111111111111111",
+        TSTOUT                          =>      open,
+        ---------------------------------- Channel ---------------------------------
+        CLKRSVD                         =>      tied_to_ground_vec_i(3 downto 0),
+        -------------------------- Channel - Clocking Ports ------------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      gtrefclk0_in,
+        GTREFCLK1                       =>      gtrefclk1_in,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR                         =>      drpaddr_in,
+        DRPCLK                          =>      drpclk_in,
+        DRPDI                           =>      drpdi_in,
+        DRPDO                           =>      drpdo_out,
+        DRPEN                           =>      drpen_in,
+        DRPRDY                          =>      drprdy_out,
+        DRPWE                           =>      drpwe_in,
+        ------------------------------- Clocking Ports -----------------------------
+        GTREFCLKMONITOR                 =>      open,
+        QPLLCLK                         =>      qpllclk_in,
+        QPLLREFCLK                      =>      qpllrefclk_in,
+        RXSYSCLKSEL                     =>      "00",
+        TXSYSCLKSEL                     =>      "00",
+        --------------------------- Digital Monitor Ports --------------------------
+        DMONITOROUT                     =>      dmonitorout_out,
+        ----------------- FPGA TX Interface Datapath Configuration  ----------------
+        TX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------------------- Loopback Ports -----------------------------
+        LOOPBACK                        =>      tied_to_ground_vec_i(2 downto 0),
+        ----------------------------- PCI Express Ports ----------------------------
+        PHYSTATUS                       =>      open,
+        RXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        RXVALID                         =>      open,
+        ------------------------------ Power-Down Ports ----------------------------
+        RXPD                            =>      "00",
+        TXPD                            =>      "00",
+        -------------------------- RX 8B/10B Decoder Ports -------------------------
+        SETERRSTATUS                    =>      tied_to_ground_i,
+        --------------------- RX Initialization and Reset Ports --------------------
+        EYESCANRESET                    =>      eyescanreset_in,
+        RXUSERRDY                       =>      rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR                =>      eyescandataerror_out,
+        EYESCANMODE                     =>      tied_to_ground_i,
+        EYESCANTRIGGER                  =>      eyescantrigger_in,
+        ------------------------- Receive Ports - CDR Ports ------------------------
+        RXCDRFREQRESET                  =>      tied_to_ground_i,
+        RXCDRHOLD                       =>      tied_to_ground_i,
+        RXCDRLOCK                       =>      RXCDRLOCK_OUT, --// Modified
+        RXCDROVRDEN                     =>      tied_to_ground_i,
+        RXCDRRESET                      =>      RXCDRRESET_IN, --// Modified
+        RXCDRRESETRSV                   =>      tied_to_ground_i,
+        ------------------- Receive Ports - Clock Correction Ports -----------------
+        RXCLKCORCNT                     =>      open,
+        ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+        RX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXUSRCLK                        =>      rxusrclk_in,
+        RXUSRCLK2                       =>      rxusrclk2_in,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        RXDATA                          =>      rxdata_i,
+        ------------------- Receive Ports - Pattern Checker Ports ------------------
+        RXPRBSERR                       =>      open,
+        RXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ------------------- Receive Ports - Pattern Checker ports ------------------
+        RXPRBSCNTRESET                  =>      tied_to_ground_i,
+        -------------------- Receive Ports - RX  Equalizer Ports -------------------
+        RXDFEXYDEN                      =>      tied_to_vcc_i,
+        RXDFEXYDHOLD                    =>      tied_to_ground_i,
+        RXDFEXYDOVRDEN                  =>      tied_to_ground_i,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXDISPERR(7 downto 2)           =>      rxdisperr_float_i,
+        RXDISPERR(1 downto 0)           =>      rxdisperr_out,
+        RXNOTINTABLE(7 downto 2)        =>      rxnotintable_float_i,
+        RXNOTINTABLE(1 downto 0)        =>      rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        GTXRXP                          =>      gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTXRXN                          =>      gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        RXBUFRESET                      =>      tied_to_ground_i,
+        RXBUFSTATUS                     =>      open,
+        RXDDIEN                         =>      tied_to_vcc_i,
+        RXDLYBYPASS                     =>      tied_to_ground_i,
+        RXDLYEN                         =>      rxdlyen_in,
+        RXDLYOVRDEN                     =>      tied_to_ground_i,
+        RXDLYSRESET                     =>      rxdlysreset_in,
+        RXDLYSRESETDONE                 =>      rxdlysresetdone_out,
+        RXPHALIGN                       =>      rxphalign_in,
+        RXPHALIGNDONE                   =>      rxphaligndone_out,
+        RXPHALIGNEN                     =>      rxphalignen_in,
+        RXPHDLYPD                       =>      tied_to_ground_i,
+        RXPHDLYRESET                    =>      rxphdlyreset_in,
+        RXPHMONITOR                     =>      rxphmonitor_out,
+        RXPHOVRDEN                      =>      tied_to_ground_i,
+        RXPHSLIPMONITOR                 =>      rxphslipmonitor_out,
+        RXSTATUS                        =>      open,
+        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+        RXBYTEISALIGNED                 =>      open,
+        RXBYTEREALIGN                   =>      open,
+        RXCOMMADET                      =>      open,
+        RXCOMMADETEN                    =>      tied_to_vcc_i,
+        RXMCOMMAALIGNEN                 =>      tied_to_vcc_i,
+        RXPCOMMAALIGNEN                 =>      tied_to_vcc_i,
+        ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+        RXCHANBONDSEQ                   =>      open,
+        RXCHBONDEN                      =>      tied_to_ground_i,
+        RXCHBONDLEVEL                   =>      tied_to_ground_vec_i(2 downto 0),
+        RXCHBONDMASTER                  =>      tied_to_ground_i,
+        RXCHBONDO                       =>      open,
+        RXCHBONDSLAVE                   =>      tied_to_ground_i,
+        ----------------- Receive Ports - RX Channel Bonding Ports  ----------------
+        RXCHANISALIGNED                 =>      open,
+        RXCHANREALIGN                   =>      open,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        RXLPMHFHOLD                     =>      rxlpmhfhold_in,
+        RXLPMHFOVRDEN                   =>      tied_to_ground_i,
+        RXLPMLFHOLD                     =>      rxlpmlfhold_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        RXDFEAGCHOLD                    =>      tied_to_ground_i,
+        RXDFEAGCOVRDEN                  =>      tied_to_ground_i,
+        RXDFECM1EN                      =>      tied_to_ground_i,
+        RXDFELFHOLD                     =>      tied_to_ground_i,
+        RXDFELFOVRDEN                   =>      tied_to_ground_i,
+        RXDFELPMRESET                   =>      rxdfelpmreset_in,
+        RXDFETAP2HOLD                   =>      tied_to_ground_i,
+        RXDFETAP2OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP3HOLD                   =>      tied_to_ground_i,
+        RXDFETAP3OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP4HOLD                   =>      tied_to_ground_i,
+        RXDFETAP4OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP5HOLD                   =>      tied_to_ground_i,
+        RXDFETAP5OVRDEN                 =>      tied_to_ground_i,
+        RXDFEUTHOLD                     =>      tied_to_ground_i,
+        RXDFEUTOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVPHOLD                     =>      tied_to_ground_i,
+        RXDFEVPOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVSEN                       =>      tied_to_ground_i,
+        RXLPMLFKLOVRDEN                 =>      tied_to_ground_i,
+        RXMONITOROUT                    =>      rxmonitorout_out,
+        RXMONITORSEL                    =>      rxmonitorsel_in,
+        RXOSHOLD                        =>      tied_to_ground_i,
+        RXOSOVRDEN                      =>      tied_to_ground_i,
+        ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+        RXRATEDONE                      =>      open,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK                        =>      rxoutclk_out,
+        RXOUTCLKFABRIC                  =>      open,
+        RXOUTCLKPCS                     =>      open,
+        RXOUTCLKSEL                     =>      "010",
+        ---------------------- Receive Ports - RX Gearbox Ports --------------------
+        RXDATAVALID                     =>      open,
+        RXHEADER                        =>      open,
+        RXHEADERVALID                   =>      open,
+        RXSTARTOFSEQ                    =>      open,
+        --------------------- Receive Ports - RX Gearbox Ports  --------------------
+        RXGEARBOXSLIP                   =>      tied_to_ground_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET                       =>      gtrxreset_in,
+        RXOOBRESET                      =>      tied_to_ground_i,
+        RXPCSRESET                      =>      tied_to_ground_i,
+        RXPMARESET                      =>      rxpmareset_in,
+        ------------------ Receive Ports - RX Margin Analysis ports ----------------
+        RXLPMEN                         =>      tied_to_vcc_i,
+        ------------------- Receive Ports - RX OOB Signaling ports -----------------
+        RXCOMSASDET                     =>      open,
+        RXCOMWAKEDET                    =>      open,
+        ------------------ Receive Ports - RX OOB Signaling ports  -----------------
+        RXCOMINITDET                    =>      open,
+        ------------------ Receive Ports - RX OOB signalling Ports -----------------
+        RXELECIDLE                      =>      open,
+        RXELECIDLEMODE                  =>      "11",
+        ----------------- Receive Ports - RX Polarity Control Ports ----------------
+        RXPOLARITY                      =>      tied_to_ground_i,
+        ---------------------- Receive Ports - RX gearbox ports --------------------
+        RXSLIDE                         =>      tied_to_ground_i,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        RXCHARISCOMMA                   =>      open,
+        RXCHARISK(7 downto 2)           =>      rxcharisk_float_i,
+        RXCHARISK(1 downto 0)           =>      rxcharisk_out,
+        ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
+        RXCHBONDI                       =>      "00000",
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE                     =>      rxresetdone_out,
+        -------------------------------- Rx AFE Ports ------------------------------
+        RXQPIEN                         =>      tied_to_ground_i,
+        RXQPISENN                       =>      open,
+        RXQPISENP                       =>      open,
+        --------------------------- TX Buffer Bypass Ports -------------------------
+        TXPHDLYTSTCLK                   =>      tied_to_ground_i,
+        ------------------------ TX Configurable Driver Ports ----------------------
+        TXPOSTCURSOR                    =>      "00000",
+        TXPOSTCURSORINV                 =>      tied_to_ground_i,
+        TXPRECURSOR                     =>      tied_to_ground_vec_i(4 downto 0),
+        TXPRECURSORINV                  =>      tied_to_ground_i,
+        TXQPIBIASEN                     =>      tied_to_ground_i,
+        TXQPISTRONGPDOWN                =>      tied_to_ground_i,
+        TXQPIWEAKPUP                    =>      tied_to_ground_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        CFGRESET                        =>      tied_to_ground_i,
+        GTTXRESET                       =>      gttxreset_in,
+        PCSRSVDOUT                      =>      open,
+        TXUSERRDY                       =>      txuserrdy_in,
+        ---------------------- Transceiver Reset Mode Operation --------------------
+        GTRESETSEL                      =>      tied_to_ground_i,
+        RESETOVRD                       =>      tied_to_ground_i,
+        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+        TXCHARDISPMODE                  =>      tied_to_ground_vec_i(7 downto 0),
+        TXCHARDISPVAL                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXUSRCLK                        =>      txusrclk_in,
+        TXUSRCLK2                       =>      txusrclk2_in,
+        --------------------- Transmit Ports - PCI Express Ports -------------------
+        TXELECIDLE                      =>      tied_to_ground_i,
+        TXMARGIN                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        TXSWING                         =>      tied_to_ground_i,
+        ------------------ Transmit Ports - Pattern Generator Ports ----------------
+        TXPRBSFORCEERR                  =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        TXDLYBYPASS                     =>      tied_to_ground_i,
+        TXDLYEN                         =>      txdlyen_in,
+        TXDLYHOLD                       =>      tied_to_ground_i,
+        TXDLYOVRDEN                     =>      tied_to_ground_i,
+        TXDLYSRESET                     =>      txdlysreset_in,
+        TXDLYSRESETDONE                 =>      txdlysresetdone_out,
+        TXDLYUPDOWN                     =>      tied_to_ground_i,
+        TXPHALIGN                       =>      txphalign_in,
+        TXPHALIGNDONE                   =>      txphaligndone_out,
+        TXPHALIGNEN                     =>      txphalignen_in,
+        TXPHDLYPD                       =>      tied_to_ground_i,
+        TXPHDLYRESET                    =>      txphdlyreset_in,
+        TXPHINIT                        =>      txphinit_in,
+        TXPHINITDONE                    =>      txphinitdone_out,
+        TXPHOVRDEN                      =>      tied_to_ground_i,
+        ---------------------- Transmit Ports - TX Buffer Ports --------------------
+        TXBUFSTATUS                     =>      open,
+        --------------- Transmit Ports - TX Configurable Driver Ports --------------
+        TXBUFDIFFCTRL                   =>      "100",
+        TXDEEMPH                        =>      tied_to_ground_i,
+        TXDIFFCTRL                      =>      "1000",
+        TXDIFFPD                        =>      tied_to_ground_i,
+        TXINHIBIT                       =>      tied_to_ground_i,
+        TXMAINCURSOR                    =>      "0000000",
+        TXPISOPD                        =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        TXDATA                          =>      txdata_i,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        GTXTXN                          =>      gtxtxn_out,
+        GTXTXP                          =>      gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK                        =>      txoutclk_out,
+        TXOUTCLKFABRIC                  =>      txoutclkfabric_out,
+        TXOUTCLKPCS                     =>      txoutclkpcs_out,
+        TXOUTCLKSEL                     =>      "011",
+        TXRATEDONE                      =>      open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        TXCHARISK(7 downto 2)           =>      tied_to_ground_vec_i(5 downto 0),
+        TXCHARISK(1 downto 0)           =>      txcharisk_in,
+        TXGEARBOXREADY                  =>      open,
+        TXHEADER                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXSEQUENCE                      =>      tied_to_ground_vec_i(6 downto 0),
+        TXSTARTSEQ                      =>      tied_to_ground_i,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXPCSRESET                      =>      tied_to_ground_i,
+        TXPMARESET                      =>      tied_to_ground_i,
+        TXRESETDONE                     =>      txresetdone_out,
+        ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+        TXCOMFINISH                     =>      open,
+        TXCOMINIT                       =>      tied_to_ground_i,
+        TXCOMSAS                        =>      tied_to_ground_i,
+        TXCOMWAKE                       =>      tied_to_ground_i,
+        TXPDELECIDLEMODE                =>      tied_to_ground_i,
+        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+        TXPOLARITY                      =>      tied_to_ground_i,
+        --------------- Transmit Ports - TX Receiver Detection Ports  --------------
+        TXDETECTRX                      =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
+        TX8B10BBYPASS                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+        TXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ----------------------- Tx Configurable Driver  Ports ----------------------
+        TXQPISENN                       =>      open,
+        TXQPISENP                       =>      open
+
+     );
+
+
+ end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_init.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_init.vhd
new file mode 100644
index 0000000..f1aa3c9
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_init.vhd
@@ -0,0 +1,882 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_sodainput_init.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_SODAinput_init
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity GTX_SODAinput_init is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    EXAMPLE_SIMULATION                      : integer   := 0;          -- Set to 1 for simulation
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+ 
+    STABLE_CLOCK_PERIOD                     : integer   := 10;  
+        -- Set to 1 for simulation
+    EXAMPLE_USE_CHIPSCOPE                   : integer   := 1   --// Modified         -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+    --_________________________________________________________________________
+    --GT0  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end GTX_SODAinput_init;
+    
+architecture RTL of GTX_SODAinput_init is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+
+component GTX_SODAinput_multi_gt 
+generic
+(
+    -- Simulation attributes
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+    WRAPPER_SIM_GTRESET_SPEEDUP    : string    := "FALSE" -- Set to "TRUE" to speed up sim reset
+
+);
+port
+(
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllrefclklost_out                  : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxdlyen_in                          : in   std_logic;
+    gt0_rxdlysreset_in                      : in   std_logic;
+    gt0_rxdlysresetdone_out                 : out  std_logic;
+    gt0_rxphalign_in                        : in   std_logic;
+    gt0_rxphaligndone_out                   : out  std_logic;
+    gt0_rxphalignen_in                      : in   std_logic;
+    gt0_rxphdlyreset_in                     : in   std_logic;
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    gt0_rxlpmhfhold_in                      : in   std_logic;
+    gt0_rxlpmlfhold_in                      : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    gt0_txdlyen_in                          : in   std_logic;
+    gt0_txdlysreset_in                      : in   std_logic;
+    gt0_txdlysresetdone_out                 : out  std_logic;
+    gt0_txphalign_in                        : in   std_logic;
+    gt0_txphaligndone_out                   : out  std_logic;
+    gt0_txphalignen_in                      : in   std_logic;
+    gt0_txphdlyreset_in                     : in   std_logic;
+    gt0_txphinit_in                         : in   std_logic;
+    gt0_txphinitdone_out                    : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+   
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN : in  std_logic;
+     GT0_QPLLOUTREFCLK_IN : in  std_logic 
+
+);
+end component;
+
+component GTX_SODAinput_TX_STARTUP_FSM
+  Generic(
+           EXAMPLE_SIMULATION       : integer := 0;
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient              
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           TXUSERCLK                : in  STD_LOGIC;              --TXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;              --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;              --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;              --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the CPLL of the GT
+           TXRESETDONE              : in  STD_LOGIC;      
+           MMCM_LOCK                : in  STD_LOGIC;      
+           GTTXRESET                : out STD_LOGIC:='0';      
+           MMCM_RESET               : out STD_LOGIC:='0';      
+           QPLL_RESET               : out STD_LOGIC:='0';        --Reset QPLL
+           CPLL_RESET               : out STD_LOGIC:='0';        --Reset CPLL
+           TX_FSM_RESET_DONE        : out STD_LOGIC:='0';        --Reset-sequence has sucessfully been finished.
+           TXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC:='0';
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';
+           PHALIGNMENT_DONE         : in  STD_LOGIC;
+           
+           RETRY_COUNTER            : out  STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end component;
+
+component GTX_SODAinput_RX_STARTUP_FSM
+  Generic(
+           EXAMPLE_SIMULATION       : integer := 0;
+           EQ_MODE                  : string := "DFE";
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient                         
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;        --Stable Clock, either a stable clock from the PCB
+                                                            --or reference-clock present at startup.
+           RXUSERCLK                : in  STD_LOGIC;        --RXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;        --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;        --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;        --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the CPLL of the GT
+           RXRESETDONE              : in  STD_LOGIC;
+           MMCM_LOCK                : in  STD_LOGIC;
+           RECCLK_STABLE            : in  STD_LOGIC;
+           RECCLK_MONITOR_RESTART   : in  STD_LOGIC;
+           DATA_VALID               : in  STD_LOGIC;
+           TXUSERRDY                : in  STD_LOGIC;       --TXUSERRDY from GT 
+           DONT_RESET_ON_DATA_ERROR : in  STD_LOGIC;
+           GTRXRESET                : out STD_LOGIC:='0';
+           MMCM_RESET               : out STD_LOGIC:='0';
+           QPLL_RESET               : out STD_LOGIC:='0';  --Reset QPLL (only if RX uses QPLL)
+           CPLL_RESET               : out STD_LOGIC:='0';  --Reset CPLL (only if RX uses CPLL)
+           RX_FSM_RESET_DONE        : out STD_LOGIC:='0';  --Reset-sequence has sucessfully been finished.
+           RXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC;
+           PHALIGNMENT_DONE         : in  STD_LOGIC; 
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';           
+           RXDFEAGCHOLD             : out STD_LOGIC;
+           RXDFELFHOLD              : out STD_LOGIC;
+           RXLPMLFHOLD              : out STD_LOGIC;
+           RXLPMHFHOLD              : out STD_LOGIC;
+           RETRY_COUNTER            : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end component;
+
+
+
+
+component GTX_SODAinput_AUTO_PHASE_ALIGN     
+    port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RUN_PHALIGNMENT          : in  STD_LOGIC;              --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC;              -- Auto phase-alignment performed sucessfully
+           PHALIGNDONE              : in  STD_LOGIC;              --\ Phase-alignment signals from and to the
+           DLYSRESET                : out STD_LOGIC;              -- |transceiver.
+           DLYSRESETDONE            : in  STD_LOGIC;              --/
+           RECCLKSTABLE             : in  STD_LOGIC               --/on the RX-side.
+           
+           );
+end component;
+
+
+component GTX_SODAinput_TX_MANUAL_PHASE_ALIGN 
+  Generic( NUMBER_OF_LANES          : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
+           MASTER_LANE_ID           : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RESET_PHALIGNMENT        : in  STD_LOGIC;
+           RUN_PHALIGNMENT          : in  STD_LOGIC;
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Manual phase-alignment performed sucessfully  
+           TXDLYSRESET              : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXDLYSRESETDONE          : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXPHINIT                 : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXPHINITDONE             : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXPHALIGN                : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXPHALIGNDONE            : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXDLYEN                  : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+           );
+end component;
+
+component GTX_SODAinput_RX_MANUAL_PHASE_ALIGN 
+  Generic( NUMBER_OF_LANES          : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
+           MASTER_LANE_ID           : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RESET_PHALIGNMENT        : in  STD_LOGIC;
+           RUN_PHALIGNMENT          : in  STD_LOGIC;
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Manual phase-alignment performed sucessfully    
+           RXDLYSRESET              : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           RXDLYSRESETDONE          : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           RXPHALIGN                : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           RXPHALIGNDONE            : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           RXDLYEN                  : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+           );
+end component;
+
+  function get_cdrlock_time(is_sim : in integer) return integer is
+    variable lock_time: integer;
+  begin
+    if (is_sim = 1) then
+      lock_time := 1000;
+    else
+      lock_time := 50000 / integer(2); --Typical CDR lock time is 50,000UI as per DS183
+    end if;
+    return lock_time;
+  end function;
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+    constant RX_CDRLOCK_TIME      : integer := get_cdrlock_time(EXAMPLE_SIMULATION);       -- 200us
+    constant WAIT_TIME_CDRLOCK    : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD;      -- 200 us time-out
+
+
+
+    -------------------------- GT Wrapper Wires ------------------------------
+    signal   gt0_txpmaresetdone_i            : std_logic;
+    signal   gt0_rxpmaresetdone_i            : std_logic;
+    signal   gt0_cpllreset_i                 : std_logic;
+    signal   gt0_cpllreset_t                 : std_logic;
+    signal   gt0_cpllrefclklost_i            : std_logic;
+    signal   gt0_cplllock_i                  : std_logic;
+    signal   gt0_txresetdone_i               : std_logic;
+    signal   gt0_rxresetdone_i               : std_logic;
+    signal   gt0_gttxreset_i                 : std_logic;
+    signal   gt0_gttxreset_t                 : std_logic;
+    signal   gt0_gtrxreset_i                 : std_logic;
+    signal   gt0_gtrxreset_t                 : std_logic;
+    signal   gt0_rxdfelpmreset_i             : std_logic;
+    signal   gt0_txuserrdy_i                 : std_logic;
+    signal   gt0_txuserrdy_t                 : std_logic;
+    signal   gt0_rxuserrdy_i                 : std_logic;
+    signal   gt0_rxuserrdy_t                 : std_logic;
+
+    signal   gt0_rxdfeagchold_i              : std_logic;
+    signal   gt0_rxdfelfhold_i               : std_logic;
+    signal   gt0_rxlpmlfhold_i               : std_logic;
+    signal   gt0_rxlpmhfhold_i               : std_logic;
+
+
+
+    signal   gt0_qpllreset_i                 : std_logic;
+    signal   gt0_qpllreset_t                 : std_logic;
+    signal   gt0_qpllrefclklost_i            : std_logic;
+    signal   gt0_qplllock_i                  : std_logic;
+
+
+    ------------------------------- Global Signals -----------------------------
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_vcc_i                   : std_logic;
+    signal   gt0_txphaligndone_i             : std_logic;
+    signal   gt0_txdlysreset_i               : std_logic;
+    signal   gt0_txdlysresetdone_i           : std_logic;
+    signal   gt0_txphdlyreset_i              : std_logic;
+    signal   gt0_txphalignen_i               : std_logic;
+    signal   gt0_txdlyen_i                   : std_logic;
+    signal   gt0_txphalign_i                 : std_logic;
+    signal   gt0_txphinit_i                  : std_logic;
+    signal   gt0_txphinitdone_i              : std_logic;
+    signal   gt0_run_tx_phalignment_i        : std_logic;
+    signal   gt0_rst_tx_phalignment_i        : std_logic;
+    signal   gt0_tx_phalignment_done_i       : std_logic;
+
+    signal   gt0_txoutclk_i                  : std_logic;
+    signal   gt0_rxoutclk_i                  : std_logic;
+    signal   gt0_rxoutclk_i2                 : std_logic;
+    signal   gt0_txoutclk_i2                 : std_logic;
+    signal   gt0_recclk_stable_i             : std_logic;
+    signal   gt0_rx_cdrlocked                : std_logic;
+    signal   gt0_rx_cdrlock_counter  :   integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
+    signal   gt0_rxphaligndone_i             : std_logic;
+    signal   gt0_rxdlysreset_i               : std_logic;
+    signal   gt0_rxdlysresetdone_i           : std_logic;
+    signal   gt0_rxphdlyreset_i              : std_logic;
+    signal   gt0_rxphalignen_i               : std_logic;
+    signal   gt0_rxdlyen_i                   : std_logic;
+    signal   gt0_rxphalign_i                 : std_logic;
+    signal   gt0_run_rx_phalignment_i        : std_logic;
+    signal   gt0_rst_rx_phalignment_i        : std_logic;
+    signal   gt0_rx_phalignment_done_i       : std_logic;
+
+
+
+    --------------------------- TX Buffer Bypass Signals --------------------
+    signal  mstr0_txsyncallin_i  :   std_logic;
+    signal  U0_TXDLYEN           :   std_logic_vector(0 downto 0);
+    signal  U0_TXDLYSRESET       :   std_logic_vector(0 downto 0);
+    signal  U0_TXDLYSRESETDONE   :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHINIT          :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHINITDONE      :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHALIGN         :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHALIGNDONE     :   std_logic_vector(0 downto 0);
+    signal  U0_run_tx_phalignment_i :   std_logic;
+    signal  U0_rst_tx_phalignment_i :   std_logic;
+
+
+    --------------------------- RX Buffer Bypass Signals --------------------
+    signal   rxmstr0_rxsyncallin_i :   std_logic;
+    signal  U0_RXDLYEN           :   std_logic_vector(0 downto 0);
+    signal  U0_RXDLYSRESET       :   std_logic_vector(0 downto 0);
+    signal  U0_RXDLYSRESETDONE   :   std_logic_vector(0 downto 0);
+    signal  U0_RXPHALIGN         :   std_logic_vector(0 downto 0);
+    signal  U0_RXPHALIGNDONE     :   std_logic_vector(0 downto 0);
+    signal  U0_run_rx_phalignment_i :   std_logic;
+    signal  U0_rst_rx_phalignment_i :   std_logic;
+
+
+
+    signal      rx_cdrlocked                    : std_logic;
+
+
+ 
+
+
+--**************************** Main Body of Code *******************************
+begin
+    --  Static signal Assigments
+    tied_to_ground_i                             <= '0';
+    tied_to_vcc_i                                <= '1';
+
+    ----------------------------- The GT Wrapper -----------------------------
+    
+    -- Use the instantiation template in the example directory to add the GT wrapper to your design.
+    -- In this example, the wrapper is wired up for basic operation with a frame generator and frame 
+    -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is 
+    -- enabled, bonding should occur after alignment.
+
+
+    GTX_SODAinput_i : GTX_SODAinput_multi_gt
+    generic map
+    (
+        USE_BUFG                        =>      USE_BUFG,
+        WRAPPER_SIM_GTRESET_SPEEDUP     =>      EXAMPLE_SIM_GTRESET_SPEEDUP
+    )
+    port map
+    (
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y15)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_i,
+        gt0_cplllockdetclk_in           =>      gt0_cplllockdetclk_in,
+        gt0_cpllrefclklost_out          =>      gt0_cpllrefclklost_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_i,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      gt0_gtrefclk0_in,
+        gt0_gtrefclk1_in                =>      gt0_gtrefclk1_in,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      gt0_drpclk_in,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_i,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+		------------------------- Receive Ports - CDR Ports ------------------------
+		GT0_RXCDRRESET_IN               =>      GT0_RXCDRRESET_IN, --// Modified
+		GT0_RXCDRLOCK_OUT               =>      GT0_RXCDRLOCK_OUT, --// Modified
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_in,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_in,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxdlyen_in                  =>      gt0_rxdlyen_i,
+        gt0_rxdlysreset_in              =>      gt0_rxdlysreset_i,
+        gt0_rxdlysresetdone_out         =>      gt0_rxdlysresetdone_i,
+        gt0_rxphalign_in                =>      gt0_rxphalign_i,
+        gt0_rxphaligndone_out           =>      gt0_rxphaligndone_i,
+        gt0_rxphalignen_in              =>      gt0_rxphalignen_i,
+        gt0_rxphdlyreset_in             =>      gt0_rxphdlyreset_i,
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        gt0_rxlpmhfhold_in              =>      gt0_rxlpmhfhold_i,
+        gt0_rxlpmlfhold_in              =>      gt0_rxlpmlfhold_i,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_i,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_i,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_i,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_in,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_in,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        gt0_txdlyen_in                  =>      gt0_txdlyen_i,
+        gt0_txdlysreset_in              =>      gt0_txdlysreset_i,
+        gt0_txdlysresetdone_out         =>      gt0_txdlysresetdone_i,
+        gt0_txphalign_in                =>      gt0_txphalign_i,
+        gt0_txphaligndone_out           =>      gt0_txphaligndone_i,
+        gt0_txphalignen_in              =>      gt0_txphalignen_i,
+        gt0_txphdlyreset_in             =>      gt0_txphdlyreset_i,
+        gt0_txphinit_in                 =>      gt0_txphinit_i,
+        gt0_txphinitdone_out            =>      gt0_txphinitdone_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_i,
+
+
+
+
+    --____________________________COMMON PORTS________________________________
+        gt0_qplloutclk_in               =>      gt0_qplloutclk_in,
+        gt0_qplloutrefclk_in            =>      gt0_qplloutrefclk_in
+    );
+
+
+gt0_rxdfelpmreset_i                          <= tied_to_ground_i;
+
+
+GT0_CPLLLOCK_OUT                             <= gt0_cplllock_i;
+GT0_TXRESETDONE_OUT                          <= gt0_txresetdone_i;
+GT0_RXRESETDONE_OUT                          <= gt0_rxresetdone_i;
+GT0_RXOUTCLK_OUT                             <= gt0_rxoutclk_i;
+GT0_TXOUTCLK_OUT                             <= gt0_txoutclk_i;
+
+chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
+gt0_cpllreset_i                              <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
+    gt0_gttxreset_i                              <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
+    gt0_gtrxreset_i                              <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
+    gt0_txuserrdy_i                              <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
+    gt0_rxuserrdy_i                              <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
+end generate chipscope;
+
+no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
+gt0_cpllreset_i                              <= gt0_cpllreset_t;
+gt0_gttxreset_i                              <= gt0_gttxreset_t;
+gt0_gtrxreset_i                              <= gt0_gtrxreset_t;
+gt0_txuserrdy_i                              <= gt0_txuserrdy_t;
+gt0_rxuserrdy_i                              <= gt0_rxuserrdy_t;
+end generate no_chipscope;
+
+
+gt0_txresetfsm_i:  GTX_SODAinput_TX_STARTUP_FSM 
+
+  generic map(
+           EXAMPLE_SIMULATION       => EXAMPLE_SIMULATION,
+           STABLE_CLOCK_PERIOD      => STABLE_CLOCK_PERIOD,           -- Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   => 8, 
+           TX_QPLL_USED             => FALSE ,                       -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             => FALSE,                        -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   => TRUE                 -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                     -- is enough. For single-lane applications the automatic alignment is 
+                                                                     -- sufficient              
+             )     
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        TXUSERCLK                       =>      GT0_TXUSRCLK_IN,
+        SOFT_RESET                      =>      SOFT_RESET_TX_IN,
+        QPLLREFCLKLOST                  =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      gt0_cpllrefclklost_i,
+        QPLLLOCK                        =>      tied_to_vcc_i,
+        CPLLLOCK                        =>      gt0_cplllock_i,
+        TXRESETDONE                     =>      gt0_txresetdone_i,
+        MMCM_LOCK                       =>      GT0_TX_MMCM_LOCK_IN,
+        GTTXRESET                       =>      gt0_gttxreset_t,
+        MMCM_RESET                      =>      GT0_TX_MMCM_RESET_OUT,
+        QPLL_RESET                      =>      open,
+        CPLL_RESET                      =>      gt0_cpllreset_t,
+        TX_FSM_RESET_DONE               =>      GT0_TX_FSM_RESET_DONE_OUT,
+        TXUSERRDY                       =>      gt0_txuserrdy_t,
+        RUN_PHALIGNMENT                 =>      gt0_run_tx_phalignment_i,
+        RESET_PHALIGNMENT               =>      gt0_rst_tx_phalignment_i,
+        PHALIGNMENT_DONE                =>      gt0_tx_phalignment_done_i,
+        RETRY_COUNTER                   =>      open
+           );
+
+
+
+
+
+
+
+
+gt0_rxresetfsm_i:  GTX_SODAinput_RX_STARTUP_FSM 
+
+  generic map(
+           EXAMPLE_SIMULATION       => EXAMPLE_SIMULATION,
+           EQ_MODE                  => "LPM",                 --Rx Equalization Mode - Set to DFE or LPM
+           STABLE_CLOCK_PERIOD      => STABLE_CLOCK_PERIOD,           --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   => 8, 
+           TX_QPLL_USED             => FALSE ,                       -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             => FALSE,                        -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   =>  FALSE                        -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                     -- is enough. For single-lane applications the automatic alignment is 
+                                                                     -- sufficient              
+             )     
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        RXUSERCLK                       =>      GT0_RXUSRCLK_IN,
+        SOFT_RESET                      =>      SOFT_RESET_RX_IN,
+        DONT_RESET_ON_DATA_ERROR        =>      DONT_RESET_ON_DATA_ERROR_IN,
+        QPLLREFCLKLOST                  =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      gt0_cpllrefclklost_i,
+        QPLLLOCK                        =>      tied_to_vcc_i,
+        CPLLLOCK                        =>      gt0_cplllock_i,
+        RXRESETDONE                     =>      gt0_rxresetdone_i,
+        MMCM_LOCK                       =>      tied_to_vcc_i,
+        RECCLK_STABLE                   =>      gt0_recclk_stable_i,
+        RECCLK_MONITOR_RESTART          =>      tied_to_ground_i,
+        DATA_VALID                      =>      GT0_DATA_VALID_IN,
+        TXUSERRDY                       =>      tied_to_vcc_i,
+        GTRXRESET                       =>      gt0_gtrxreset_t,
+        MMCM_RESET                      =>      open,
+        QPLL_RESET                      =>      open,
+        CPLL_RESET                      =>      open,
+        RX_FSM_RESET_DONE               =>      GT0_RX_FSM_RESET_DONE_OUT,
+        RXUSERRDY                       =>      gt0_rxuserrdy_t,
+        RUN_PHALIGNMENT                 =>      gt0_run_rx_phalignment_i,
+        RESET_PHALIGNMENT               =>      gt0_rst_rx_phalignment_i,
+        PHALIGNMENT_DONE                =>      gt0_rx_phalignment_done_i,
+        RXDFEAGCHOLD                    =>      gt0_rxdfeagchold_i,
+        RXDFELFHOLD                     =>      gt0_rxdfelfhold_i,
+        RXLPMLFHOLD                     =>      gt0_rxlpmlfhold_i,
+        RXLPMHFHOLD                     =>      gt0_rxlpmhfhold_i,
+        RETRY_COUNTER                   =>      open
+           );
+
+
+
+  gt0_cdrlock_timeout:process(SYSCLK_IN)
+  begin
+    if rising_edge(SYSCLK_IN) then
+        if(gt0_gtrxreset_i = '1') then
+          gt0_rx_cdrlocked       <= '0';
+          gt0_rx_cdrlock_counter <=  0                        after DLY;
+        elsif (gt0_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
+          gt0_rx_cdrlocked       <= '1';
+          gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter        after DLY;
+        else
+          gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter + 1    after DLY;
+        end if;
+    end if;
+  end process;
+
+gt0_recclk_stable_i                          <= gt0_rx_cdrlocked;
+
+
+
+    --------------------------- TX Buffer Bypass Logic --------------------
+    -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer.
+    -- Include the TX SYNC module in your own design if TX Buffer is bypassed.
+
+
+--Auto
+gt0_txphdlyreset_i                           <= tied_to_ground_i;
+gt0_txphalignen_i                            <= tied_to_ground_i;
+gt0_txdlyen_i                                <= tied_to_ground_i;
+gt0_txphalign_i                              <= tied_to_ground_i;
+gt0_txphinit_i                               <= tied_to_ground_i;
+
+gt0_tx_auto_phase_align_i : GTX_SODAinput_AUTO_PHASE_ALIGN    
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        RUN_PHALIGNMENT                 =>      gt0_run_tx_phalignment_i,
+        PHASE_ALIGNMENT_DONE            =>      gt0_tx_phalignment_done_i,
+        PHALIGNDONE                     =>      gt0_txphaligndone_i,
+        DLYSRESET                       =>      gt0_txdlysreset_i,
+        DLYSRESETDONE                   =>      gt0_txdlysresetdone_i,
+        RECCLKSTABLE                    =>      tied_to_vcc_i
+           );
+
+
+
+
+   --------------------------- RX Buffer Bypass Logic --------------------
+--   The RX SYNC Module drives the ports needed to Bypass the RX Buffer.
+--   Include the RX SYNC module in your own design if RX Buffer is bypassed.
+
+
+--Auto
+gt0_rxphdlyreset_i                           <= '1'; --// Modified???????  tied_to_ground_i;
+gt0_rxphalignen_i                            <= '1'; --// Modified???????  tied_to_ground_i;
+gt0_rxdlyen_i                                <= tied_to_ground_i;
+gt0_rxphalign_i                              <= tied_to_ground_i;
+
+gt0_rx_phalignment_done_i <= '1'; --// Modified
+gt0_rxdlysreset_i <= '1'; --// Modified
+-- gt0_rx_auto_phase_align_i : GTX_SODAinput_AUTO_PHASE_ALIGN    
+  -- port map ( 
+        -- STABLE_CLOCK                    =>      SYSCLK_IN,
+        -- RUN_PHALIGNMENT                 =>      gt0_run_rx_phalignment_i,
+        -- PHASE_ALIGNMENT_DONE            =>      gt0_rx_phalignment_done_i,
+        -- PHALIGNDONE                     =>      gt0_rxphaligndone_i,
+        -- DLYSRESET                       =>      gt0_rxdlysreset_i,
+        -- DLYSRESETDONE                   =>      gt0_rxdlysresetdone_i,
+        -- RECCLKSTABLE                    =>      gt0_recclk_stable_i
+     -- );
+
+end RTL;
+
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_multi_gt.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_multi_gt.vhd
new file mode 100644
index 0000000..e8c6b31
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_multi_gt.vhd
@@ -0,0 +1,509 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_sodainput_multi_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_SODAinput_multi_gt (a Multi GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+
+entity GTX_SODAinput_multi_gt is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE";        -- Set to "TRUE" to speed up sim reset
+    RX_DFE_KL_CFG2_IN               : bit_vector :=  X"301148AC";
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+ 
+    PMA_RSV_IN                      : bit_vector :=  x"00018480"
+);
+port
+(
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X0Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllrefclklost_out                  : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxdlyen_in                          : in   std_logic;
+    gt0_rxdlysreset_in                      : in   std_logic;
+    gt0_rxdlysresetdone_out                 : out  std_logic;
+    gt0_rxphalign_in                        : in   std_logic;
+    gt0_rxphaligndone_out                   : out  std_logic;
+    gt0_rxphalignen_in                      : in   std_logic;
+    gt0_rxphdlyreset_in                     : in   std_logic;
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    gt0_rxlpmhfhold_in                      : in   std_logic;
+    gt0_rxlpmlfhold_in                      : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    gt0_txdlyen_in                          : in   std_logic;
+    gt0_txdlysreset_in                      : in   std_logic;
+    gt0_txdlysresetdone_out                 : out  std_logic;
+    gt0_txphalign_in                        : in   std_logic;
+    gt0_txphaligndone_out                   : out  std_logic;
+    gt0_txphalignen_in                      : in   std_logic;
+    gt0_txphdlyreset_in                     : in   std_logic;
+    gt0_txphinit_in                         : in   std_logic;
+    gt0_txphinitdone_out                    : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+
+end GTX_SODAinput_multi_gt;
+    
+architecture RTL of GTX_SODAinput_multi_gt is
+    attribute DowngradeIPIdentifiedWarnings: string;
+    attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_SODAinput_multi_gt,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--***************************** Signal Declarations *****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal   gt0_qplloutclk_i         :   std_logic;
+    signal   gt0_qplloutrefclk_i      :   std_logic;
+
+    signal  gt0_mgtrefclktx_i           :   std_logic_vector(1 downto 0);
+    signal  gt0_mgtrefclkrx_i           :   std_logic_vector(1 downto 0);
+ 
+    signal   gt0_qpllclk_i            :   std_logic;
+    signal   gt0_qpllrefclk_i         :   std_logic;
+    signal   gt0_cpllreset_i            :   std_logic;
+    signal   gt0_cpllpd_i         :   std_logic;
+    signal   cpll_reset0_i            :   std_logic;
+    signal   cpll_pd0_i         :   std_logic;
+
+--*************************** Component Declarations **************************
+component GTX_SODAinput_GT
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP       : string   := "FALSE";
+    RX_DFE_KL_CFG2_IN            : bit_vector :=   X"3010D90C";
+    PMA_RSV_IN                   : bit_vector :=   X"00000000";
+    SIM_CPLLREFCLK_SEL           : bit_vector :=   "001";
+    PCS_RSVD_ATTR_IN             : bit_vector :=   X"000000000000"
+);
+port 
+(   
+     cpllpd_in : in std_logic;
+     cpllrefclksel_in : in std_logic_vector (2 downto 0);
+    --------------------------------- CPLL Ports -------------------------------
+    cpllfbclklost_out                       : out  std_logic;
+    cplllock_out                            : out  std_logic;
+    cplllockdetclk_in                       : in   std_logic;
+    cpllrefclklost_out                      : out  std_logic;
+    cpllreset_in                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gtrefclk0_in                            : in   std_logic;
+    gtrefclk1_in                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    drpaddr_in                              : in   std_logic_vector(8 downto 0);
+    drpclk_in                               : in   std_logic;
+    drpdi_in                                : in   std_logic_vector(15 downto 0);
+    drpdo_out                               : out  std_logic_vector(15 downto 0);
+    drpen_in                                : in   std_logic;
+    drprdy_out                              : out  std_logic;
+    drpwe_in                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    qpllclk_in                              : in   std_logic;
+    qpllrefclk_in                           : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    dmonitorout_out                         : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    eyescanreset_in                         : in   std_logic;
+    rxuserrdy_in                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    eyescandataerror_out                    : out  std_logic;
+    eyescantrigger_in                       : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	RXCDRRESET_IN                           : in  std_logic; --// Modified
+    RXCDRLOCK_OUT                           : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    rxusrclk_in                             : in   std_logic;
+    rxusrclk2_in                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    rxdata_out                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    rxdisperr_out                           : out  std_logic_vector(1 downto 0);
+    rxnotintable_out                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gtxrxp_in                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gtxrxn_in                               : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    rxdlyen_in                              : in   std_logic;
+    rxdlysreset_in                          : in   std_logic;
+    rxdlysresetdone_out                     : out  std_logic;
+    rxphalign_in                            : in   std_logic;
+    rxphaligndone_out                       : out  std_logic;
+    rxphalignen_in                          : in   std_logic;
+    rxphdlyreset_in                         : in   std_logic;
+    rxphmonitor_out                         : out  std_logic_vector(4 downto 0);
+    rxphslipmonitor_out                     : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    rxlpmhfhold_in                          : in   std_logic;
+    rxlpmlfhold_in                          : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    rxdfelpmreset_in                        : in   std_logic;
+    rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
+    rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    rxoutclk_out                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gtrxreset_in                            : in   std_logic;
+    rxpmareset_in                           : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    rxcharisk_out                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    rxresetdone_out                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gttxreset_in                            : in   std_logic;
+    txuserrdy_in                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    txusrclk_in                             : in   std_logic;
+    txusrclk2_in                            : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    txdlyen_in                              : in   std_logic;
+    txdlysreset_in                          : in   std_logic;
+    txdlysresetdone_out                     : out  std_logic;
+    txphalign_in                            : in   std_logic;
+    txphaligndone_out                       : out  std_logic;
+    txphalignen_in                          : in   std_logic;
+    txphdlyreset_in                         : in   std_logic;
+    txphinit_in                             : in   std_logic;
+    txphinitdone_out                        : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    txdata_in                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gtxtxn_out                              : out  std_logic;
+    gtxtxp_out                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    txoutclk_out                            : out  std_logic;
+    txoutclkfabric_out                      : out  std_logic;
+    txoutclkpcs_out                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    txcharisk_in                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    txresetdone_out                         : out  std_logic
+
+
+);
+end component;
+component GTX_SODAinput_cpll_railing
+  Generic(
+           USE_BUFG       : integer := 0
+);
+port 
+(   
+        cpll_reset_out : out std_logic;
+         cpll_pd_out : out std_logic;
+         refclk_out : out std_logic;
+        
+         refclk_in : in std_logic
+
+);
+end component;
+
+
+
+--********************************* Main Body of Code**************************
+
+begin                       
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    gt0_qpllclk_i    <= GT0_QPLLOUTCLK_IN;  
+    gt0_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN; 
+
+
+ 
+    --------------------------- GT Instances  -------------------------------   
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X0Y15)
+
+gt0_GTX_SODAinput_i : GTX_SODAinput_GT 
+    generic map
+    (
+        -- Simulation attributes
+        GT_SIM_GTRESET_SPEEDUP        =>  WRAPPER_SIM_GTRESET_SPEEDUP,
+        RX_DFE_KL_CFG2_IN             =>  RX_DFE_KL_CFG2_IN,
+        SIM_CPLLREFCLK_SEL            =>  "001",
+        PMA_RSV_IN                    =>  PMA_RSV_IN,
+        PCS_RSVD_ATTR_IN              =>  X"000000000000"
+    )
+    port map
+    (
+        cpllpd_in => gt0_cpllpd_i,
+        cpllrefclksel_in => "001",
+        --------------------------------- CPLL Ports -------------------------------
+        cpllfbclklost_out               =>      gt0_cpllfbclklost_out,
+        cplllock_out                    =>      gt0_cplllock_out,
+        cplllockdetclk_in               =>      gt0_cplllockdetclk_in,
+        cpllrefclklost_out              =>      gt0_cpllrefclklost_out,
+        cpllreset_in                    =>      gt0_cpllreset_i,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gtrefclk0_in                    =>      gt0_gtrefclk0_in,
+        gtrefclk1_in                    =>      gt0_gtrefclk1_in,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        drpaddr_in                      =>      gt0_drpaddr_in,
+        drpclk_in                       =>      gt0_drpclk_in,
+        drpdi_in                        =>      gt0_drpdi_in,
+        drpdo_out                       =>      gt0_drpdo_out,
+        drpen_in                        =>      gt0_drpen_in,
+        drprdy_out                      =>      gt0_drprdy_out,
+        drpwe_in                        =>      gt0_drpwe_in,
+        ------------------------------- Clocking Ports -----------------------------
+        qpllclk_in                      =>      gt0_qpllclk_i,
+        qpllrefclk_in                   =>      gt0_qpllrefclk_i,
+        --------------------------- Digital Monitor Ports --------------------------
+        dmonitorout_out                 =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        eyescanreset_in                 =>      gt0_eyescanreset_in,
+        rxuserrdy_in                    =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        eyescandataerror_out            =>      gt0_eyescandataerror_out,
+        eyescantrigger_in               =>      gt0_eyescantrigger_in,
+		------------------------- Receive Ports - CDR Ports ------------------------
+		RXCDRRESET_IN                   =>      GT0_RXCDRRESET_IN, --// Modified
+		RXCDRLOCK_OUT                   =>      GT0_RXCDRLOCK_OUT, --// Modified
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        rxusrclk_in                     =>      gt0_rxusrclk_in,
+        rxusrclk2_in                    =>      gt0_rxusrclk2_in,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        rxdata_out                      =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        rxdisperr_out                   =>      gt0_rxdisperr_out,
+        rxnotintable_out                =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gtxrxp_in                       =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gtxrxn_in                       =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        rxdlyen_in                      =>      gt0_rxdlyen_in,
+        rxdlysreset_in                  =>      gt0_rxdlysreset_in,
+        rxdlysresetdone_out             =>      gt0_rxdlysresetdone_out,
+        rxphalign_in                    =>      gt0_rxphalign_in,
+        rxphaligndone_out               =>      gt0_rxphaligndone_out,
+        rxphalignen_in                  =>      gt0_rxphalignen_in,
+        rxphdlyreset_in                 =>      gt0_rxphdlyreset_in,
+        rxphmonitor_out                 =>      gt0_rxphmonitor_out,
+        rxphslipmonitor_out             =>      gt0_rxphslipmonitor_out,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        rxlpmhfhold_in                  =>      gt0_rxlpmhfhold_in,
+        rxlpmlfhold_in                  =>      gt0_rxlpmlfhold_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        rxdfelpmreset_in                =>      gt0_rxdfelpmreset_in,
+        rxmonitorout_out                =>      gt0_rxmonitorout_out,
+        rxmonitorsel_in                 =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        rxoutclk_out                    =>      gt0_rxoutclk_out,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gtrxreset_in                    =>      gt0_gtrxreset_in,
+        rxpmareset_in                   =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        rxcharisk_out                   =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        rxresetdone_out                 =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gttxreset_in                    =>      gt0_gttxreset_in,
+        txuserrdy_in                    =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        txusrclk_in                     =>      gt0_txusrclk_in,
+        txusrclk2_in                    =>      gt0_txusrclk2_in,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        txdlyen_in                      =>      gt0_txdlyen_in,
+        txdlysreset_in                  =>      gt0_txdlysreset_in,
+        txdlysresetdone_out             =>      gt0_txdlysresetdone_out,
+        txphalign_in                    =>      gt0_txphalign_in,
+        txphaligndone_out               =>      gt0_txphaligndone_out,
+        txphalignen_in                  =>      gt0_txphalignen_in,
+        txphdlyreset_in                 =>      gt0_txphdlyreset_in,
+        txphinit_in                     =>      gt0_txphinit_in,
+        txphinitdone_out                =>      gt0_txphinitdone_out,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        txdata_in                       =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gtxtxn_out                      =>      gt0_gtxtxn_out,
+        gtxtxp_out                      =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        txoutclk_out                    =>      gt0_txoutclk_out,
+        txoutclkfabric_out              =>      gt0_txoutclkfabric_out,
+        txoutclkpcs_out                 =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        txcharisk_in                    =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        txresetdone_out                 =>      gt0_txresetdone_out
+
+    );
+
+
+   cpll_railing0_i : GTX_SODAinput_cpll_railing
+  generic map(
+           USE_BUFG       => USE_BUFG
+   ) 
+   port map
+   (
+        cpll_reset_out => cpll_reset0_i,
+        cpll_pd_out => cpll_pd0_i,
+        refclk_out => open,
+        refclk_in => gt0_gtrefclk0_in
+);
+
+
+gt0_cpllreset_i <= cpll_reset0_i or gt0_cpllreset_in; 
+gt0_cpllpd_i <= cpll_pd0_i ; 
+end RTL;     
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_rx_startup_fsm.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_rx_startup_fsm.vhd
new file mode 100644
index 0000000..d71f1ca
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_rx_startup_fsm.vhd
@@ -0,0 +1,788 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 3.5
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename : gtx_sodainput_rx_startup_fsm.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--  Description :     This module performs RX reset and initialization.
+--                     
+--
+--
+-- Module GTX_SODAinput_rx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_SODAinput_RX_STARTUP_FSM is
+  Generic( EXAMPLE_SIMULATION       : integer := 0;
+           EQ_MODE                  : string  := "DFE";           --RX Equalisation Mode; set to DFE or LPM
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient                         
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;        --Stable Clock, either a stable clock from the PCB
+                                                            --or reference-clock present at startup.
+           RXUSERCLK                : in  STD_LOGIC;        --RXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;        --User Reset, can be pulled any time
+
+           QPLLREFCLKLOST           : in  STD_LOGIC;        --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;        --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the CPLL of the GT
+           RXRESETDONE              : in  STD_LOGIC;
+           MMCM_LOCK                : in  STD_LOGIC;
+           RECCLK_STABLE            : in  STD_LOGIC;
+           RECCLK_MONITOR_RESTART   : in  STD_LOGIC:='0';
+           DATA_VALID               : in  STD_LOGIC;
+           TXUSERRDY                : in  STD_LOGIC;       --TXUSERRDY from GT 
+           DONT_RESET_ON_DATA_ERROR : in  STD_LOGIC;       --Used to control the Auto-Reset of FSM when Data Error is detected
+           GTRXRESET                : out STD_LOGIC;
+           MMCM_RESET               : out STD_LOGIC;
+           QPLL_RESET               : out STD_LOGIC:='0';  --Reset QPLL (only if RX uses QPLL)
+           CPLL_RESET               : out STD_LOGIC:='0';  --Reset CPLL (only if RX uses CPLL)
+           RX_FSM_RESET_DONE        : out STD_LOGIC;       --Reset-sequence has sucessfully been finished.
+           RXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC;
+           PHALIGNMENT_DONE         : in  STD_LOGIC; 
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';           
+           RXDFEAGCHOLD             : out STD_LOGIC;
+           RXDFELFHOLD              : out STD_LOGIC;
+           RXLPMLFHOLD              : out STD_LOGIC;
+           RXLPMHFHOLD              : out STD_LOGIC;
+           RETRY_COUNTER            : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end GTX_SODAinput_RX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+--   are calculated at design-time based on the Generics
+--   
+-- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
+--   => signal which PLL has been reset
+-- * 
+
+
+
+architecture RTL of GTX_SODAinput_RX_STARTUP_FSM is
+
+  component GTX_SODAinput_sync_block
+   generic (
+     INITIALISE : bit_vector(5 downto 0) := "000000"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+  type rx_rst_fsm_type is(
+    INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
+    RELEASE_MMCM_RESET, WAIT_FOR_RXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+    MONITOR_DATA_VALID, FSM_DONE);
+    
+  signal rx_state : rx_rst_fsm_type := INIT;
+
+  constant MMCM_LOCK_CNT_MAX    : integer := 256;
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+  constant WAIT_TIMEOUT_2ms     : integer := 2000000 / STABLE_CLOCK_PERIOD;--  2 ms time-out
+  constant WAIT_TLOCK_MAX       : integer :=  100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_TIMEOUT_500us   : integer :=  500000 / STABLE_CLOCK_PERIOD;--500 us time-out
+  constant WAIT_TIMEOUT_1us     : integer :=  1000 / STABLE_CLOCK_PERIOD;  --1 us time-out
+  constant WAIT_TIMEOUT_100us    : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
+  constant WAIT_TIME_ADAPT      : integer := (37000000 /integer(2))/STABLE_CLOCK_PERIOD;
+  constant WAIT_TIME_MAX    : integer := 100 ; --10 us time-out
+    
+  signal init_wait_count        : integer range 0 to WAIT_MAX:=0;
+  signal init_wait_done         : std_logic := '0';
+  signal pll_reset_asserted     : std_logic := '0';
+  signal rx_fsm_reset_done_int  : std_logic := '0';
+  signal rx_fsm_reset_done_int_s2  : std_logic := '0';
+  signal rx_fsm_reset_done_int_s3  : std_logic := '0';
+   
+  signal rxresetdone_s2         : std_logic := '0'; 
+  signal rxresetdone_s3         : std_logic := '0'; 
+
+  constant MAX_RETRIES          : integer := 2**RETRY_COUNTER_BITWIDTH-1; 
+  signal retry_counter_int      : integer range 0 to MAX_RETRIES := 0;  
+  signal time_out_counter       : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+  signal recclk_mon_restart_count : integer range 0 to 3:= 0;
+  signal recclk_mon_count_reset   : std_logic := '0';
+  
+  signal reset_time_out         : std_logic := '0';
+  signal time_out_2ms           : std_logic := '0';--\Flags that the various time-out points 
+  signal time_tlock_max         : std_logic := '0';--|have been reached.
+  signal time_out_500us         : std_logic := '0';--|
+  signal time_out_1us           : std_logic := '0';--/
+  signal time_out_100us         : std_logic := '0';--/
+  signal check_tlock_max        : std_logic := '0';
+    
+  signal mmcm_lock_count        : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+  signal mmcm_lock_int          : std_logic := '0';
+  signal mmcm_lock_i            : std_logic := '0';
+  signal mmcm_lock_reclocked    : std_logic := '0';
+  signal gtrxreset_i    : std_logic := '0';
+  signal mmcm_reset_i    : std_logic := '1';
+  signal rxpmaresetdone_i    : std_logic := '0';
+  signal txpmaresetdone_i    : std_logic := '0';
+  signal rxpmaresetdone_ss    : std_logic := '0';
+  signal rxpmaresetdone_sync    : std_logic ;
+  signal txpmaresetdone_sync    : std_logic ;
+  signal rxpmaresetdone_s    : std_logic ;
+  signal rxpmaresetdone_rx_s    : std_logic ;
+  signal pmaresetdone_fallingedge_detect    : std_logic ;
+  signal pmaresetdone_fallingedge_detect_s    : std_logic ;
+    
+  signal run_phase_alignment_int: std_logic := '0';
+  signal run_phase_alignment_int_s2 : std_logic := '0';
+  signal run_phase_alignment_int_s3 : std_logic := '0';
+
+  constant MAX_WAIT_BYPASS        : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
+  signal wait_bypass_count        : integer range 0 to MAX_WAIT_BYPASS-1;
+  signal time_out_wait_bypass     : std_logic := '0';
+  signal time_out_wait_bypass_s2   : std_logic := '0';
+  signal time_out_wait_bypass_s3   : std_logic := '0';
+
+  signal refclk_lost              : std_logic;
+
+  signal time_out_adapt           : std_logic := '0';   
+  signal adapt_count_reset        : std_logic := '0';   
+  signal adapt_count              : integer range 0 to WAIT_TIME_ADAPT-1;
+  signal      data_valid_sync: std_logic := '0';
+  signal      cplllock_sync: std_logic := '0';
+  signal      qplllock_sync: std_logic := '0';
+  signal      cplllock_prev: std_logic := '0';
+  signal      qplllock_prev: std_logic := '0';
+  signal      cplllock_ris_edge: std_logic := '0';
+  signal      qplllock_ris_edge: std_logic := '0';
+  signal      wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+  signal      wait_time_done : std_logic;
+
+
+  attribute shreg_extract                   : string;
+  attribute ASYNC_REG                       : string;
+
+  signal      reset_sync_reg1_tx : std_logic;
+  signal      reset_sync_reg1 : std_logic;
+  signal      gtrxreset_s : std_logic;
+  signal      gtrxreset_tx_s : std_logic;
+  signal      txpmaresetdone_s : std_logic;
+begin
+  --Alias section, signals used within this module mapped to output ports:
+  RETRY_COUNTER     <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+  RUN_PHALIGNMENT   <= run_phase_alignment_int;
+  RX_FSM_RESET_DONE <= rx_fsm_reset_done_int;
+  GTRXRESET <= gtrxreset_i; 
+  MMCM_RESET <= mmcm_reset_i; 
+  process(STABLE_CLOCK,SOFT_RESET)
+  begin
+    if (SOFT_RESET = '1') then
+        init_wait_done <= '0';
+        init_wait_count <= 0 ;
+    elsif rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+
+  adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate
+      time_out_adapt <= '1';
+  end generate;
+
+  adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(adapt_count_reset = '1') then
+        adapt_count    <= 0;
+        time_out_adapt <= '0';
+     elsif(adapt_count = WAIT_TIME_ADAPT -1) then
+        time_out_adapt <= '1';
+     else 
+        adapt_count    <= adapt_count + 1;  
+     end if;
+    end if;
+  end process;
+  end generate;
+
+  retries_recclk_monitor:process(STABLE_CLOCK)
+  begin
+    --This counter monitors, how many retries the RECCLK monitor
+    --runs. If during startup too many retries are necessary, the whole 
+    --initialisation-process of the transceivers gets restarted.
+    if rising_edge(STABLE_CLOCK) then  
+      if recclk_mon_count_reset = '1' then
+        recclk_mon_restart_count <= 0;
+      elsif RECCLK_MONITOR_RESTART = '1' then
+        if recclk_mon_restart_count = 3 then
+          recclk_mon_restart_count <= 0;
+        else 
+          recclk_mon_restart_count <= recclk_mon_restart_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  timeouts:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- One common large counter for generating three time-out signals.
+      -- Intermediate time-outs are derived from calculated values, based
+      -- on the period of the provided clock.
+      if reset_time_out = '1' then
+        time_out_counter  <= 0;
+        time_out_2ms      <= '0';
+        time_tlock_max    <= '0';
+        time_out_500us    <= '0';
+        time_out_1us      <= '0';
+        time_out_100us    <= '0';
+      else
+        if time_out_counter = WAIT_TIMEOUT_2ms then
+          time_out_2ms <= '1';
+        else
+          time_out_counter <= time_out_counter + 1;
+        end if;
+        
+        if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
+          time_tlock_max <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_500us then
+          time_out_500us <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_1us then
+          time_out_1us <= '1';
+        end if;
+
+        if time_out_counter = WAIT_TIMEOUT_100us then
+          time_out_100us <= '1';
+        end if;
+
+      end if;
+    end if;
+  end process;
+
+
+
+  mmcm_lock_wait:process(STABLE_CLOCK)
+  begin
+    --The lock-signal from the MMCM is not immediately used but 
+    --enabling a counter. Only when the counter hits its maximum,
+    --the MMCM is considered as "really" locked. 
+    --The counter avoids that the FSM already starts on only a 
+    --coarse lock of the MMCM (=toggling of the LOCK-signal).
+    if rising_edge(STABLE_CLOCK) then
+      if mmcm_lock_i = '0' then
+        mmcm_lock_count <= 0;
+        mmcm_lock_reclocked   <= '0';
+      else       
+        if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+          mmcm_lock_count <= mmcm_lock_count + 1;
+        else
+          mmcm_lock_reclocked <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+  -- Clock Domain Crossing
+
+  sync_run_phase_alignment_int : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  RXUSERCLK,
+            data_in         =>  run_phase_alignment_int,
+            data_out        =>  run_phase_alignment_int_s2 
+         );
+
+  sync_rx_fsm_reset_done_int : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  RXUSERCLK,
+            data_in         =>  rx_fsm_reset_done_int,
+            data_out        =>  rx_fsm_reset_done_int_s2 
+         );
+
+  process(RXUSERCLK)
+  begin
+    if rising_edge(RXUSERCLK) then
+      run_phase_alignment_int_s3   <=  run_phase_alignment_int_s2;
+
+      rx_fsm_reset_done_int_s3     <=  rx_fsm_reset_done_int_s2;
+    end if;
+  end process;
+
+ sync_RXRESETDONE : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  RXRESETDONE,
+            data_out        =>  rxresetdone_s2 
+         );
+
+  sync_time_out_wait_bypass : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  time_out_wait_bypass,
+            data_out        =>  time_out_wait_bypass_s2 
+         );
+
+  sync_mmcm_lock_reclocked : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  MMCM_LOCK,
+            data_out        =>  mmcm_lock_i 
+         );
+
+  sync_data_valid : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  DATA_VALID,
+            data_out        =>  data_valid_sync
+         );
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+       rxresetdone_s3     <= rxresetdone_s2;
+
+       time_out_wait_bypass_s3 <=  time_out_wait_bypass_s2;
+
+       cplllock_prev           <=  cplllock_sync;
+       qplllock_prev           <=  qplllock_sync;
+    end if;
+  end process;
+
+ sync_CPLLLOCK : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  CPLLLOCK,
+            data_out        =>  cplllock_sync
+         );
+
+ sync_QPLLLOCK : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  QPLLLOCK,
+            data_out        =>  qplllock_sync
+         );
+
+
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       cplllock_ris_edge <= '0';
+     elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+       cplllock_ris_edge <= '1';
+     elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+       cplllock_ris_edge <= cplllock_ris_edge;
+     else 
+       cplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       qplllock_ris_edge <= '0';
+     elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+       qplllock_ris_edge <= '1';
+     elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+       qplllock_ris_edge <= qplllock_ris_edge;
+     else 
+       qplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+
+  timeout_buffer_bypass:process(RXUSERCLK)
+  begin
+    if rising_edge(RXUSERCLK) then
+      if run_phase_alignment_int_s3 = '0' then
+        wait_bypass_count     <= 0;
+        time_out_wait_bypass  <= '0';
+      elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
+        if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+          time_out_wait_bypass <= '1';
+        else
+          wait_bypass_count <= wait_bypass_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+   refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+
+  timeout_max:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+        if((rx_state = ASSERT_ALL_RESETS) or
+          (rx_state = RELEASE_MMCM_RESET)) then
+            wait_time_cnt <= WAIT_TIME_MAX;
+        elsif (wait_time_cnt > 0 ) then
+            wait_time_cnt <= wait_time_cnt - 1;
+          end if;
+       end if;
+   end process;
+
+  wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+ 
+  --FSM for resetting the GTX/GTH/GTP in the 7-series. 
+  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  --
+  -- Following steps are performed:
+  -- 1) After configuration wait for approximately 500 ns as specified in 
+  --    answer-record 43482
+  -- 2) Assert all resets on the GT and on an MMCM potentially connected. 
+  --    After that wait until a reference-clock has been detected.
+  -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+  -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+  --    Also get info from the TX-side which PLL has been reset.
+  -- 5) Wait for the RESET_DONE-signal from the GT.
+  -- 6) Signal to start the phase-alignment procedure and wait for it to 
+  --    finish.
+  -- 7) Reset-sequence has successfully run through. Signal this to the 
+  --    rest of the design by asserting RX_FSM_RESET_DONE.
+  
+  reset_fsm:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if (SOFT_RESET = '1' ) then
+      --if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+        rx_state                <= INIT;
+        RXUSERRDY               <= '0';
+        gtrxreset_i               <= '0';
+        mmcm_reset_i              <= '0';
+        rx_fsm_reset_done_int   <= '0';
+        QPLL_RESET              <= '0';
+        CPLL_RESET              <= '0';
+        pll_reset_asserted      <= '0';
+        reset_time_out          <= '1';
+        retry_counter_int       <=  0;
+        run_phase_alignment_int <= '0';
+        check_tlock_max         <= '0';
+        RESET_PHALIGNMENT       <= '1';
+        recclk_mon_count_reset  <= '1';
+        adapt_count_reset       <= '1';
+        RXDFEAGCHOLD            <= '0';
+        RXDFELFHOLD             <= '0';
+        RXLPMLFHOLD             <= '0';
+        RXLPMHFHOLD             <= '0';
+
+      else
+        
+        case rx_state is
+          when INIT => 
+            --Initial state after configuration. This state will be left after
+            --approx. 500 ns and not be re-entered. 
+            if init_wait_done = '1' then
+              rx_state  <= ASSERT_ALL_RESETS;
+            end if;
+            
+          when ASSERT_ALL_RESETS => 
+            --This is the state into which the FSM will always jump back if any
+            --time-outs will occur. 
+            --The number of retries is reported on the output RETRY_COUNTER. In 
+            --case the transceiver never comes up for some reason, this machine 
+            --will still continue its best and rerun until the FPGA is turned off
+            --or the transceivers come up correctly.
+             if RX_QPLL_USED and not TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                QPLL_RESET          <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                QPLL_RESET          <= '0';
+              end if;
+            elsif not RX_QPLL_USED and TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                CPLL_RESET <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                CPLL_RESET          <= '0';
+              end if;  
+            end if;
+
+            RXUSERRDY               <= '0';
+            gtrxreset_i               <= '1';
+            mmcm_reset_i              <= '1';
+            run_phase_alignment_int <= '0';    
+            RESET_PHALIGNMENT       <= '1';
+            check_tlock_max         <= '0';
+            recclk_mon_count_reset  <= '1';
+            adapt_count_reset       <= '1';
+            
+            if (RX_QPLL_USED     and not TX_QPLL_USED  and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+               (not RX_QPLL_USED and TX_QPLL_USED  and (cplllock_sync = '0') and pll_reset_asserted = '1') or
+               (not RX_QPLL_USED and not TX_QPLL_USED  ) or
+               (RX_QPLL_USED and  TX_QPLL_USED  ) then
+              rx_state  <= WAIT_FOR_PLL_LOCK;
+              reset_time_out          <= '1';
+            end if;           
+           
+          when  WAIT_FOR_PLL_LOCK =>
+              if(wait_time_done = '1') then
+                 rx_state        <=  RELEASE_PLL_RESET;  
+            end if;
+ 
+          when RELEASE_PLL_RESET => 
+            --PLL-Reset of the GTX gets released and the time-out counter
+            --starts running.
+            pll_reset_asserted  <= '0';
+            reset_time_out  <= '0';
+            
+            if (RX_QPLL_USED     and not TX_QPLL_USED and (qplllock_sync = '1')) or
+               (not RX_QPLL_USED and TX_QPLL_USED     and (cplllock_sync = '1')) then
+              rx_state                <= VERIFY_RECCLK_STABLE;
+              reset_time_out          <= '1';
+              recclk_mon_count_reset  <= '0';
+              adapt_count_reset       <= '0';
+            elsif (RX_QPLL_USED and (qplllock_sync = '1')) or
+                  (not RX_QPLL_USED and (cplllock_sync = '1')) then
+              rx_state                <= VERIFY_RECCLK_STABLE;
+              reset_time_out          <= '1';
+              recclk_mon_count_reset  <= '0';
+              adapt_count_reset       <= '0';
+            end if;
+            
+            if time_out_2ms = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+
+          when VERIFY_RECCLK_STABLE =>
+            --reset_time_out  <= '0';
+            --Time-out counter is not released in this state as here the FSM
+            --does not wait for a certain period of time but checks on the number
+            --of retries in the RECCLK monitor 
+            gtrxreset_i <= '0';
+            if RECCLK_STABLE = '1' then
+              rx_state        <= RELEASE_MMCM_RESET;
+              reset_time_out  <= '1';
+              
+            end if;          
+
+            if recclk_mon_restart_count = 2 then
+              --If two retries are performed in the RECCLK monitor
+              --the whole initialisation-sequence gets restarted.
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+          
+          when RELEASE_MMCM_RESET => 
+            --Release of the MMCM-reset. Waiting for the MMCM to lock.
+            check_tlock_max <= '1';
+            
+            mmcm_reset_i <= '0';
+            reset_time_out  <= '0';
+         
+            if mmcm_lock_reclocked = '1' then
+              rx_state <= WAIT_FOR_RXUSRCLK;
+              reset_time_out  <= '1';
+            end if;          
+            
+            if (time_tlock_max = '1' and reset_time_out = '0' )then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+ 
+           when WAIT_FOR_RXUSRCLK =>
+              if wait_time_done = '1' then
+               rx_state <=  WAIT_RESET_DONE;  
+            end if;
+           
+          when WAIT_RESET_DONE => 
+            --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
+            --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
+            if TXUSERRDY = '1' then
+               RXUSERRDY <= '1';
+            end if;
+            reset_time_out  <= '0';
+            if rxresetdone_s3 = '1' then
+              rx_state        <= DO_PHASE_ALIGNMENT; 
+              reset_time_out  <= '1';
+            end if;          
+
+            if time_out_2ms = '1' and reset_time_out = '0' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+          
+          when DO_PHASE_ALIGNMENT => 
+            --The direct handling of the signals for the Phase Alignment is done outside
+            --this state-machine. 
+            RESET_PHALIGNMENT       <= '0';
+            run_phase_alignment_int <= '1';
+            reset_time_out          <= '0';
+            
+            if PHALIGNMENT_DONE = '1' then
+              rx_state        <= MONITOR_DATA_VALID;
+              reset_time_out  <= '1';
+            end if;
+            
+            if time_out_wait_bypass_s3 = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <=  retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+          
+          when MONITOR_DATA_VALID => 
+              reset_time_out  <= '0';
+
+              if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0')  then
+                 rx_state              <= ASSERT_ALL_RESETS; 
+                 rx_fsm_reset_done_int <= '0';
+              elsif (data_valid_sync = '1') then
+                 rx_state              <= FSM_DONE; 
+                 rx_fsm_reset_done_int <= '0';
+                 reset_time_out        <= '1';
+              end if;
+ 
+         when FSM_DONE =>
+            reset_time_out  <= '0';
+            if data_valid_sync = '0' then
+               rx_fsm_reset_done_int <= '0';
+               reset_time_out        <= '1';
+               rx_state              <= MONITOR_DATA_VALID;
+ 
+            elsif(time_out_1us = '1' and reset_time_out = '0')  then
+               rx_fsm_reset_done_int <= '1';
+            end if;
+
+            if(time_out_adapt = '1') then
+               if(EQ_MODE = "DFE") then
+                  RXDFEAGCHOLD  <=  '1';
+                  RXDFELFHOLD   <=  '1';
+                  RXLPMHFHOLD   <=  '0';
+                  RXLPMLFHOLD   <=  '0';
+               else 
+                  RXDFEAGCHOLD  <=  '0';
+                  RXDFELFHOLD   <=  '0';
+                  RXLPMHFHOLD   <=  '0';
+                  RXLPMLFHOLD   <=  '0';
+               end if;
+            end if;
+           when OTHERS => 
+              rx_state                <= INIT;
+        end case;
+      end if;
+    end if;
+  end process;
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_sync_block.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_sync_block.vhd
new file mode 100644
index 0000000..c2564a1
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_sync_block.vhd
@@ -0,0 +1,194 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 3.5
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename : gtx_sodainput_sync_block.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--
+-- Description: Used on signals crossing from one clock domain to
+--              another, this is a flip-flop pair, with both flops
+--              placed together with RLOCs into the same slice.  Thus
+--              the routing delay between the two is minimum to safe-
+--              guard against metastability issues.
+--                     
+--
+-- Module GTX_SODAinput_sync_block
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_SODAinput_sync_block is
+  generic (
+    INITIALISE : bit_vector(5 downto 0) := "000000"
+  );
+  port (
+    clk         : in  std_logic;          -- clock to be sync'ed to
+    data_in     : in  std_logic;          -- Data to be 'synced'
+    data_out    : out std_logic           -- synced data
+    );
+
+-- attribute dont_touch : string;
+-- attribute dont_touch    of   GTX_SODAinput_sync_block : entity is "yes";
+
+end GTX_SODAinput_sync_block;
+
+
+architecture structural of GTX_SODAinput_sync_block is
+
+
+  -- Internal Signals
+  signal data_sync1 : std_logic;
+  signal data_sync2 : std_logic;
+  signal data_sync3 : std_logic;
+  signal data_sync4 : std_logic;
+  signal data_sync5 : std_logic;
+
+  -- These attributes will stop timing errors being reported in back annotated
+  -- SDF simulation.
+  attribute ASYNC_REG                       : string;
+  attribute ASYNC_REG of data_sync_reg1    : label is "true";
+  attribute ASYNC_REG of data_sync_reg2    : label is "true";
+  attribute ASYNC_REG of data_sync_reg3    : label is "true";
+  attribute ASYNC_REG of data_sync_reg4    : label is "true";
+  attribute ASYNC_REG of data_sync_reg5    : label is "true";
+  attribute ASYNC_REG of data_sync_reg6    : label is "true";
+
+  -- These attributes will stop XST translating the desired flip-flops into an
+  -- SRL based shift register.
+  attribute shreg_extract                   : string;
+  attribute shreg_extract of data_sync_reg1 : label is "no";
+  attribute shreg_extract of data_sync_reg2 : label is "no";
+  attribute shreg_extract of data_sync_reg3 : label is "no";
+  attribute shreg_extract of data_sync_reg4 : label is "no";
+  attribute shreg_extract of data_sync_reg5 : label is "no";
+  attribute shreg_extract of data_sync_reg6 : label is "no";
+
+  
+begin
+
+  data_sync_reg1 : FD
+  generic map (
+    INIT => INITIALISE(0)
+  )
+  port map (
+    C    => clk,
+    D    => data_in,
+    Q    => data_sync1
+  );
+
+ data_sync_reg2 : FD
+  generic map (
+    INIT => INITIALISE(1)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync1,
+    Q    => data_sync2
+  );
+
+ data_sync_reg3 : FD
+  generic map (
+    INIT => INITIALISE(2)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync2,
+    Q    => data_sync3
+  );
+
+ data_sync_reg4 : FD
+  generic map (
+    INIT => INITIALISE(3)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync3,
+    Q    => data_sync4
+  );
+
+ data_sync_reg5 : FD
+  generic map (
+    INIT => INITIALISE(4)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync4,
+    Q    => data_sync5
+  );  
+
+  data_sync_reg6 : FD
+  generic map (
+    INIT => INITIALISE(5)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync5,
+    Q    => data_out
+  );
+
+
+
+end structural;
+
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_tx_startup_fsm.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_tx_startup_fsm.vhd
new file mode 100644
index 0000000..0714163
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/IPsources/gtx_sodainput_tx_startup_fsm.vhd
@@ -0,0 +1,609 @@
+--//////////////////////////////////////////////////////////////////////////////
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename :gtx_sodainput_tx_startup_fsm.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module GTX_SODAinput_tx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity GTX_SODAinput_TX_STARTUP_FSM is
+  Generic(
+           EXAMPLE_SIMULATION       : integer := 0; 
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient              
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           TXUSERCLK                : in  STD_LOGIC;              --TXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;              --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;              --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;              --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the CPLL of the GT
+           TXRESETDONE              : in  STD_LOGIC;      
+           MMCM_LOCK                : in  STD_LOGIC;      
+           GTTXRESET                : out STD_LOGIC;      
+           MMCM_RESET               : out STD_LOGIC:='1';      
+           QPLL_RESET               : out STD_LOGIC:='0';        --Reset QPLL
+           CPLL_RESET               : out STD_LOGIC:='0';        --Reset CPLL
+           TX_FSM_RESET_DONE        : out STD_LOGIC;             --Reset-sequence has sucessfully been finished.
+           TXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC:='0';
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';
+           PHALIGNMENT_DONE         : in  STD_LOGIC;
+           
+           RETRY_COUNTER            : out  STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end GTX_SODAinput_TX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+--   are calculated at design-time based on the Generics
+--   
+-- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX
+--   => signal which PLL has been reset
+-- * 
+
+
+
+architecture RTL of GTX_SODAinput_TX_STARTUP_FSM is
+
+  component GTX_SODAinput_sync_block
+   generic (
+     INITIALISE : bit_vector(5 downto 0) := "000000"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+  type tx_rst_fsm_type is(
+    INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET,
+    WAIT_FOR_TXOUTCLK, RELEASE_MMCM_RESET, WAIT_FOR_TXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+    RESET_FSM_DONE);
+    
+  signal tx_state : tx_rst_fsm_type := INIT;
+
+  constant MMCM_LOCK_CNT_MAX    : integer := 256;
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+    
+  constant WAIT_TIMEOUT_2ms     : integer := 2000000 / STABLE_CLOCK_PERIOD;--  2 ms time-out
+  constant WAIT_TLOCK_MAX       : integer :=  100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_TIMEOUT_500us   : integer :=  500000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_1us_cycles      : integer :=  1000 / STABLE_CLOCK_PERIOD;--1 us time-out
+  constant WAIT_1us             : integer := WAIT_1us_cycles+ 10;                    -- 1us plus some additional margin
+    
+  signal init_wait_count        : integer range 0 to WAIT_MAX:=0;
+  signal init_wait_done         : std_logic := '0';
+  signal pll_reset_asserted     : std_logic := '0';
+
+  signal tx_fsm_reset_done_int     : std_logic := '0';
+  signal tx_fsm_reset_done_int_s2  : std_logic := '0';
+  signal tx_fsm_reset_done_int_s3  : std_logic := '0';
+   
+  signal txresetdone_s2         : std_logic := '0'; 
+  signal txresetdone_s3         : std_logic := '0'; 
+
+  constant MAX_RETRIES          : integer := 2**RETRY_COUNTER_BITWIDTH-1; 
+  signal retry_counter_int      : integer range 0 to MAX_RETRIES;  
+  signal time_out_counter       : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+    
+  signal reset_time_out         : std_logic := '0';
+  signal time_out_2ms           : std_logic := '0';--\Flags that the various time-out points 
+  signal time_tlock_max         : std_logic := '0';--|have been reached.
+  signal time_out_500us         : std_logic := '0';--/
+    
+  signal mmcm_lock_count        : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+  signal mmcm_lock_int          : std_logic := '0';
+  signal mmcm_lock_i            : std_logic := '0';
+  signal mmcm_lock_reclocked    : std_logic := '0';
+    
+  signal run_phase_alignment_int    : std_logic := '0';
+  signal run_phase_alignment_int_s2 : std_logic := '0';
+  signal run_phase_alignment_int_s3 : std_logic := '0';
+  constant MAX_WAIT_BYPASS      : integer := 45824; --110000 TXUSRCLK cycles is the max time for Multi lane designs
+ 
+  constant WAIT_TIME_MAX    : integer := 100 ; --10 us time-out
+
+  signal wait_bypass_count      : integer range 0 to MAX_WAIT_BYPASS-1;
+  signal time_out_wait_bypass   : std_logic := '0';
+  signal time_out_wait_bypass_s2   : std_logic := '0';
+  signal time_out_wait_bypass_s3   : std_logic := '0';
+  signal txuserrdy_i   : std_logic := '0';
+  signal refclk_lost            : std_logic;
+  signal gttxreset_i            : std_logic := '0';
+  signal txpmaresetdone_i            : std_logic := '0';
+  signal txpmaresetdone_sync            : std_logic ;
+
+  signal      cplllock_sync: std_logic := '0';
+  signal      qplllock_sync: std_logic := '0';
+  signal      cplllock_prev: std_logic := '0';
+  signal      qplllock_prev: std_logic := '0';
+  signal      cplllock_ris_edge: std_logic := '0';
+  signal      qplllock_ris_edge: std_logic := '0';
+ signal      wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+  signal      wait_time_done :std_logic;
+ 
+begin
+  --Alias section, signals used within this module mapped to output ports:
+  RETRY_COUNTER     <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+  RUN_PHALIGNMENT   <= run_phase_alignment_int;
+  TX_FSM_RESET_DONE <= tx_fsm_reset_done_int;    
+  GTTXRESET <= gttxreset_i;
+
+  process(STABLE_CLOCK,SOFT_RESET)
+  begin
+    if (SOFT_RESET = '1') then
+        init_wait_done <= '0';
+        init_wait_count <= 0 ;
+    elsif rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+  timeouts:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- One common large counter for generating three time-out signals.
+      -- Intermediate time-outs are derived from calculated values, based
+      -- on the period of the provided clock.
+      if reset_time_out = '1' then
+        time_out_counter  <= 0;
+        time_out_2ms      <= '0';
+        time_tlock_max    <= '0';
+        time_out_500us    <= '0';
+      else
+        if time_out_counter = WAIT_TIMEOUT_2ms then
+          time_out_2ms <= '1';
+        else
+          time_out_counter <= time_out_counter + 1;
+        end if;
+        
+        if time_out_counter = WAIT_TLOCK_MAX then
+          time_tlock_max <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_500us then
+          time_out_500us <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  mmcm_lock_wait:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if mmcm_lock_i = '0' then
+        mmcm_lock_count <= 0;
+        mmcm_lock_reclocked   <= '0';
+      else 
+        if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+          mmcm_lock_count <= mmcm_lock_count + 1;
+        else
+          mmcm_lock_reclocked <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+ 
+ 
+
+  -- Clock Domain Crossing
+
+  sync_run_phase_alignment_int : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  TXUSERCLK,
+            data_in         =>  run_phase_alignment_int,
+            data_out        =>  run_phase_alignment_int_s2 
+         );
+
+  sync_tx_fsm_reset_done_int : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  TXUSERCLK,
+            data_in         =>  tx_fsm_reset_done_int,
+            data_out        =>  tx_fsm_reset_done_int_s2 
+         );
+
+  process(TXUSERCLK)
+  begin
+    if rising_edge(TXUSERCLK) then
+      run_phase_alignment_int_s3   <=  run_phase_alignment_int_s2;
+
+      tx_fsm_reset_done_int_s3     <=  tx_fsm_reset_done_int_s2;
+    end if;
+  end process;
+
+ sync_TXRESETDONE : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  TXRESETDONE,
+            data_out        =>  txresetdone_s2 
+         );
+
+  sync_time_out_wait_bypass : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  time_out_wait_bypass,
+            data_out        =>  time_out_wait_bypass_s2 
+         );
+
+  sync_mmcm_lock_reclocked : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  MMCM_LOCK,
+            data_out        =>  mmcm_lock_i 
+         );
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+       txresetdone_s3     <= txresetdone_s2;
+
+       time_out_wait_bypass_s3 <=  time_out_wait_bypass_s2;
+
+       cplllock_prev           <=  cplllock_sync;
+       qplllock_prev           <=  qplllock_sync;
+    end if;
+  end process;
+
+ sync_CPLLLOCK : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  CPLLLOCK,
+            data_out        =>  cplllock_sync
+         );
+
+ sync_QPLLLOCK : GTX_SODAinput_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  QPLLLOCK,
+            data_out        =>  qplllock_sync
+         );
+
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       cplllock_ris_edge <= '0';
+     elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+       cplllock_ris_edge <= '1';
+     elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+       cplllock_ris_edge <= cplllock_ris_edge;
+     else 
+       cplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       qplllock_ris_edge <= '0';
+     elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+       qplllock_ris_edge <= '1';
+     elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+       qplllock_ris_edge <= qplllock_ris_edge;
+     else 
+       qplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+
+
+  timeout_buffer_bypass:process(TXUSERCLK)
+  begin
+    if rising_edge(TXUSERCLK) then
+      if run_phase_alignment_int_s3 = '0' then
+        wait_bypass_count     <= 0;
+        time_out_wait_bypass  <= '0';
+      elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0')  then
+        if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+          time_out_wait_bypass <= '1';
+        else
+          wait_bypass_count <= wait_bypass_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+   refclk_lost <= '1' when ((TX_QPLL_USED and QPLLREFCLKLOST='1') or (not TX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+  timeout_max:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+        if((tx_state = ASSERT_ALL_RESETS) or
+          (tx_state = RELEASE_PLL_RESET) or 
+          (tx_state = RELEASE_MMCM_RESET)) then
+            wait_time_cnt <= WAIT_TIME_MAX;
+        elsif (wait_time_cnt > 0 ) then
+            wait_time_cnt <= wait_time_cnt - 1;
+          end if;
+       end if;
+   end process;
+
+  wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+
+  --FSM for resetting the GTX/GTH/GTP in the 7-series. 
+  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  --
+  -- Following steps are performed:
+  -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in 
+  --    answer-record 43482
+  -- 2) Assert all resets on the GT and on an MMCM potentially connected. 
+  --    After that wait until a reference-clock has been detected.
+  -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+  -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+  --    Also signal to the RX-side which PLL has been reset.
+  -- 5) Wait for the RESET_DONE-signal from the GT.
+  -- 6) Signal to start the phase-alignment procedure and wait for it to 
+  --    finish.
+  -- 7) Reset-sequence has successfully run through. Signal this to the 
+  --    rest of the design by asserting TX_FSM_RESET_DONE.
+  
+  reset_fsm:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1') then
+      --if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+        tx_state                <= INIT;
+        TXUSERRDY               <= '0';
+        gttxreset_i               <= '0';
+        MMCM_RESET              <= '0';
+        tx_fsm_reset_done_int   <= '0';
+        QPLL_RESET              <= '0';
+        CPLL_RESET              <= '0';
+        pll_reset_asserted      <= '0';
+        reset_time_out          <= '0';
+        retry_counter_int       <=  0;
+        run_phase_alignment_int <= '0';
+        RESET_PHALIGNMENT       <= '1';
+      else
+        
+        case tx_state is
+          when INIT => 
+            --Initial state after configuration. This state will be left after
+            --approx. 500 ns and not be re-entered. 
+            if init_wait_done = '1' then
+              tx_state        <= ASSERT_ALL_RESETS;
+              reset_time_out  <= '1';
+            end if;
+            
+          when ASSERT_ALL_RESETS => 
+            --This is the state into which the FSM will always jump back if any
+            --time-outs will occur. 
+            --The number of retries is reported on the output RETRY_COUNTER. In 
+            --case the transceiver never comes up for some reason, this machine 
+            --will still continue its best and rerun until the FPGA is turned off
+            --or the transceivers come up correctly.
+            if TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                QPLL_RESET          <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                QPLL_RESET          <= '0';
+              end if;
+            else
+              if pll_reset_asserted = '0' then
+                CPLL_RESET <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                CPLL_RESET          <= '0';
+              end if;  
+            end if;
+            TXUSERRDY               <= '0';
+            gttxreset_i               <= '1';
+            MMCM_RESET              <= '1';
+            reset_time_out          <= '1';
+            run_phase_alignment_int <= '0';     
+            RESET_PHALIGNMENT       <= '1';
+
+            if (TX_QPLL_USED  and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+               (not TX_QPLL_USED  and (cplllock_sync = '0') and pll_reset_asserted = '1') then
+              tx_state  <= WAIT_FOR_PLL_LOCK;
+           end if;    
+       
+           when WAIT_FOR_PLL_LOCK =>
+              if(wait_time_done = '1') then
+                 tx_state        <=  RELEASE_PLL_RESET;  
+           end if;    
+         
+          when RELEASE_PLL_RESET => 
+            --PLL-Reset of the GTX gets released and the time-out counter
+            --starts running.
+            pll_reset_asserted  <= '0';
+
+            if (TX_QPLL_USED and (qplllock_sync = '1')) or
+               (not TX_QPLL_USED and (cplllock_sync = '1')) then
+              tx_state  <= WAIT_FOR_TXOUTCLK;
+              reset_time_out  <= '1';
+            end if;
+            
+            if time_out_2ms = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+
+           when WAIT_FOR_TXOUTCLK =>
+            gttxreset_i <= '0';
+              if(wait_time_done = '1') then
+               tx_state <=  RELEASE_MMCM_RESET;  
+           end if;    
+
+          when RELEASE_MMCM_RESET => 
+            --Release of the MMCM-reset. Waiting for the MMCM to lock.
+            MMCM_RESET <= '0';
+            reset_time_out  <= '0';
+            if mmcm_lock_reclocked = '1' then
+              tx_state <= WAIT_FOR_TXUSRCLK;
+              reset_time_out  <= '1';
+            end if;          
+            
+            if (time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0') then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+
+           when WAIT_FOR_TXUSRCLK =>
+              if(wait_time_done = '1') then
+               tx_state <=  WAIT_RESET_DONE; 
+           end if;    
+ 
+          when WAIT_RESET_DONE => 
+            TXUSERRDY <= '1';
+            reset_time_out  <= '0';
+            if txresetdone_s3 = '1' then              
+              tx_state      <= DO_PHASE_ALIGNMENT;               
+              reset_time_out  <= '1';
+            end if;          
+
+            if (time_out_500us = '1' and reset_time_out = '0') then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;                    
+          
+          when DO_PHASE_ALIGNMENT => 
+            --The direct handling of the signals for the Phase Alignment is done outside
+            --this state-machine. 
+            RESET_PHALIGNMENT       <= '0';
+            run_phase_alignment_int <= '1';
+            reset_time_out          <= '0';
+            
+            if PHALIGNMENT_DONE = '1' then
+              tx_state        <= RESET_FSM_DONE;
+            end if;
+            
+            if time_out_wait_bypass_s3 = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <=  retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+          
+          when RESET_FSM_DONE => 
+            reset_time_out        <= '1';
+            tx_fsm_reset_done_int <= '1';
+
+          when OTHERS =>
+            tx_state              <= INIT;
+          
+        end case;
+      end if;
+    end if;
+  end process; 
+
+end RTL;
diff --git a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_clock_module.vhd
similarity index 65%
rename from FEE_ADC32board/project/ipcore_dir/clockmodule40switch.vhd
rename to data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_clock_module.vhd
index 32c471f..8fcb64b 100644
--- a/FEE_ADC32board/project/ipcore_dir/clockmodule40switch.vhd
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_clock_module.vhd
@@ -1,223 +1,245 @@
--- file: clockmodule40switch.vhd
--- 
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- None
---
-------------------------------------------------------------------------------
--- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
--- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
-------------------------------------------------------------------------------
--- CLK_OUT1____40.000______0.000______50.0______247.096____196.976
--- CLK_OUT2____80.000______0.000______50.0______200.412____196.976
---
-------------------------------------------------------------------------------
--- "Input Clock   Freq (MHz)    Input Jitter (UI)"
-------------------------------------------------------------------------------
--- __primary______________40____________0.010
--- _secondary____________40____________0.010
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-use ieee.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity clockmodule40switch is
-port
- (-- Clock in ports
-  CLK_IN1           : in     std_logic;
-  CLK_IN2           : in     std_logic;
-  CLK_IN_SEL           : in     std_logic;
-  -- Clock out ports
-  CLK_OUT1          : out    std_logic;
-  CLK_OUT2          : out    std_logic;
-  -- Status and control signals
-  RESET             : in     std_logic;
-  LOCKED            : out    std_logic
- );
-end clockmodule40switch;
-
-architecture xilinx of clockmodule40switch is
-  attribute CORE_GENERATION_INFO : string;
-  attribute CORE_GENERATION_INFO of xilinx : architecture is "clockmodule40switch,clk_wiz_v3_6,{component_name=clockmodule40switch,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=true,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=25.000,clkin2_period=25.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-  -- Input clock buffering / unused connectors
-  signal clkin1      : std_logic;
-  signal clkin2      : std_logic;
-  -- Output clock buffering / unused connectors
-  signal clkfbout         : std_logic;
-  signal clkfbout_buf     : std_logic;
-  signal clkfboutb_unused : std_logic;
-  signal clkout0          : std_logic;
-  signal clkout0b_unused  : std_logic;
-  signal clkout1          : std_logic;
-  signal clkout1b_unused  : std_logic;
-  signal clkout2_unused   : std_logic;
-  signal clkout2b_unused  : std_logic;
-  signal clkout3_unused   : std_logic;
-  signal clkout3b_unused  : std_logic;
-  signal clkout4_unused   : std_logic;
-  signal clkout5_unused   : std_logic;
-  signal clkout6_unused   : std_logic;
-  -- Dynamic programming unused signals
-  signal do_unused        : std_logic_vector(15 downto 0);
-  signal drdy_unused      : std_logic;
-  -- Dynamic phase shift unused signals
-  signal psdone_unused    : std_logic;
-  -- Unused status signals
-  signal clkfbstopped_unused : std_logic;
-  signal clkinstopped_unused : std_logic;
-begin
-
-
-  -- Input buffering
-  --------------------------------------
-  clkin1_buf : BUFG
-  port map
-   (O => clkin1,
-    I => CLK_IN1);
-
-  clkin2_buf : BUFG
-  port map
-   (O => clkin2,
-    I => CLK_IN2);
-
-  -- Clocking primitive
-  --------------------------------------
-  -- Instantiation of the MMCM primitive
-  --    * Unused inputs are tied off
-  --    * Unused outputs are labeled unused
-  mmcm_adv_inst : MMCM_ADV
-  generic map
-   (BANDWIDTH            => "OPTIMIZED",
-    CLKOUT4_CASCADE      => FALSE,
-    CLOCK_HOLD           => FALSE,
-    COMPENSATION         => "ZHOLD",
-    STARTUP_WAIT         => FALSE,
-    DIVCLK_DIVIDE        => 1,
-    CLKFBOUT_MULT_F      => 24.000,
-    CLKFBOUT_PHASE       => 0.000,
-    CLKFBOUT_USE_FINE_PS => FALSE,
-    CLKOUT0_DIVIDE_F     => 24.000,
-    CLKOUT0_PHASE        => 0.000,
-    CLKOUT0_DUTY_CYCLE   => 0.500,
-    CLKOUT0_USE_FINE_PS  => FALSE,
-    CLKOUT1_DIVIDE       => 12,
-    CLKOUT1_PHASE        => 0.000,
-    CLKOUT1_DUTY_CYCLE   => 0.500,
-    CLKOUT1_USE_FINE_PS  => FALSE,
-    CLKIN1_PERIOD        => 25.000,
-    REF_JITTER1          => 0.010,
-    CLKIN2_PERIOD        => 25.000,
-    REF_JITTER2          => 0.010)
-  port map
-    -- Output clocks
-   (CLKFBOUT            => clkfbout,
-    CLKFBOUTB           => clkfboutb_unused,
-    CLKOUT0             => clkout0,
-    CLKOUT0B            => clkout0b_unused,
-    CLKOUT1             => clkout1,
-    CLKOUT1B            => clkout1b_unused,
-    CLKOUT2             => clkout2_unused,
-    CLKOUT2B            => clkout2b_unused,
-    CLKOUT3             => clkout3_unused,
-    CLKOUT3B            => clkout3b_unused,
-    CLKOUT4             => clkout4_unused,
-    CLKOUT5             => clkout5_unused,
-    CLKOUT6             => clkout6_unused,
-    -- Input clock control
-    CLKFBIN             => clkfbout_buf,
-    CLKIN1              => clkin1,
-    CLKIN2              => clkin2,
-    CLKINSEL            => CLK_IN_SEL,
-    -- Ports for dynamic reconfiguration
-    DADDR               => (others => '0'),
-    DCLK                => '0',
-    DEN                 => '0',
-    DI                  => (others => '0'),
-    DO                  => do_unused,
-    DRDY                => drdy_unused,
-    DWE                 => '0',
-    -- Ports for dynamic phase shift
-    PSCLK               => '0',
-    PSEN                => '0',
-    PSINCDEC            => '0',
-    PSDONE              => psdone_unused,
-    -- Other control and status signals
-    LOCKED              => LOCKED,
-    CLKINSTOPPED        => clkinstopped_unused,
-    CLKFBSTOPPED        => clkfbstopped_unused,
-    PWRDWN              => '0',
-    RST                 => RESET);
-
-  -- Output buffering
-  -------------------------------------
-  clkf_buf : BUFG
-  port map
-   (O => clkfbout_buf,
-    I => clkfbout);
-
-
-  clkout1_buf : BUFG
-  port map
-   (O   => CLK_OUT1,
-    I   => clkout0);
-
-
-
-  clkout2_buf : BUFG
-  port map
-   (O   => CLK_OUT2,
-    I   => clkout1);
-
-end xilinx;
+-- file: clk_wiz_v2_1.vhd
+-- 
+-- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+-- Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1   100.000      0.000    50.000      130.958     98.575
+-- CLK_OUT2   200.000      0.000    50.000      114.829     98.575
+--
+------------------------------------------------------------------------------
+-- Input Clock   Input Freq (MHz)   Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary         100.000            0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_SODAinput_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end GTX_SODAinput_CLOCK_MODULE;
+
+architecture xilinx of GTX_SODAinput_CLOCK_MODULE is
+  attribute X_CORE_INFO : string;
+  attribute X_CORE_INFO of xilinx : architecture is "GTX_SODAinput,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfbout_buf     : std_logic;
+  signal clkfboutb_unused : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout0b_unused  : std_logic;
+  signal clkout1          : std_logic;
+  signal clkout1b_unused  : std_logic;
+  signal clkout2          : std_logic;
+  signal clkout2b_unused  : std_logic;
+  signal clkout3          : std_logic;
+  signal clkout3b_unused  : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  signal clkout6_unused   : std_logic;
+  -- Dynamic programming unused signals
+  signal do_unused        : std_logic_vector(15 downto 0);
+  signal drdy_unused      : std_logic;
+  -- Dynamic phase shift unused signals
+  signal psdone_unused    : std_logic;
+  -- Unused status signals
+  signal clkfbstopped_unused : std_logic;
+  signal clkinstopped_unused : std_logic;
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : BUFG
+  port map
+   (O => clkin1,
+    I => CLK_IN);
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the MMCM primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+
+  mmcm_adv_inst : MMCME2_ADV
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLKOUT4_CASCADE      => FALSE,
+    COMPENSATION         => "ZHOLD",
+    STARTUP_WAIT         => FALSE,
+    DIVCLK_DIVIDE        => DIVIDE,
+    CLKFBOUT_MULT_F      => MULT,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKFBOUT_USE_FINE_PS => FALSE,
+    CLKOUT0_DIVIDE_F     => OUT0_DIVIDE,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT0_USE_FINE_PS  => FALSE,
+    CLKIN1_PERIOD        => CLK_PERIOD,
+    CLKOUT1_DIVIDE       => OUT1_DIVIDE,
+    CLKOUT1_PHASE        => 0.000,
+    CLKOUT1_DUTY_CYCLE   => 0.500,
+    CLKOUT1_USE_FINE_PS  => FALSE,
+    CLKOUT2_DIVIDE       => OUT2_DIVIDE,
+    CLKOUT2_PHASE        => 0.000,
+    CLKOUT2_DUTY_CYCLE   => 0.500,
+    CLKOUT2_USE_FINE_PS  => FALSE,
+    CLKOUT3_DIVIDE       => OUT3_DIVIDE,
+    CLKOUT3_PHASE        => 0.000,
+    CLKOUT3_DUTY_CYCLE   => 0.500,
+    CLKOUT3_USE_FINE_PS  => FALSE,
+    REF_JITTER1          => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKFBOUTB           => clkfboutb_unused,
+    CLKOUT0             => clkout0,
+    CLKOUT0B            => clkout0b_unused,
+    CLKOUT1             => clkout1,
+    CLKOUT1B            => clkout1b_unused,
+    CLKOUT2             => clkout2,
+    CLKOUT2B            => clkout2b_unused,
+    CLKOUT3             => clkout3,
+    CLKOUT3B            => clkout3b_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    CLKOUT6             => clkout6_unused,
+    -- Input clock control
+    CLKFBIN             => clkfbout,
+    CLKIN1              => clkin1,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => do_unused,
+    DRDY                => drdy_unused,
+    DWE                 => '0',
+    -- Ports for dynamic phase shift
+    PSCLK               => '0',
+    PSEN                => '0',
+    PSINCDEC            => '0',
+    PSDONE              => psdone_unused,
+    -- Other control and status signals
+    LOCKED              => MMCM_LOCKED_OUT,
+    CLKINSTOPPED        => clkinstopped_unused,
+    CLKFBSTOPPED        => clkfbstopped_unused,
+    PWRDWN              => '0',
+    RST                 => MMCM_RESET_IN);
+
+  -- Output buffering
+  -------------------------------------
+  --clkf_buf : BUFG
+  --port map
+  -- (O => clkfbout_buf,
+  --  I => clkfbout);
+
+
+  clkout0_buf : BUFG
+  port map
+   (O   => CLK0_OUT,
+    I   => clkout0);
+
+  clkout1_buf : BUFG
+  port map
+   (O   => CLK1_OUT,
+    I   => clkout1);
+
+--  clkout2_buf : BUFG
+--  port map
+--   (O   => CLK2_OUT,
+--    I   => clkout2);
+--
+--  clkout3_buf : BUFG
+--  port map
+--   (O   => CLK3_OUT,
+--    I   => clkout3);
+
+CLK2_OUT <= '0';
+CLK3_OUT <= '0';
+end xilinx;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_common.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_common.vhd
new file mode 100644
index 0000000..bce8870
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_common.vhd
@@ -0,0 +1,247 @@
+---------------------------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_sodainput_common.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_SODAinput_common 
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_SODAinput_common is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "TRUE";        -- Set to "true" to speed up sim reset 
+    SIM_QPLLREFCLK_SEL              : bit_vector :=  "001"
+);
+port
+(
+    QPLLREFCLKSEL_IN  : in std_logic_vector(2 downto 0);
+    GTREFCLK1_IN      : in std_logic;
+    GTREFCLK0_IN : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+);
+
+end GTX_SODAinput_common;
+    
+architecture RTL of GTX_SODAinput_common is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_SODAinput_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+    impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return "0000100000";
+       elsif (qpllfbdiv_top = 20) then
+         return "0000110000" ;
+       elsif (qpllfbdiv_top = 32) then
+         return "0001100000" ;
+       elsif (qpllfbdiv_top = 40) then
+         return "0010000000" ;
+       elsif (qpllfbdiv_top = 64) then
+         return "0011100000" ;
+       elsif (qpllfbdiv_top = 66) then
+         return "0101000000" ;
+       elsif (qpllfbdiv_top = 80) then
+         return "0100100000" ;
+       elsif (qpllfbdiv_top = 100) then
+         return "0101110000" ;
+       else 
+         return "0000000000" ;
+       end if;
+    end function;
+
+    impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return '1';
+       elsif (qpllfbdiv_top = 20) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 32) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 40) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 64) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 66) then
+         return '0' ;
+       elsif (qpllfbdiv_top = 80) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 100) then
+         return '1' ;
+       else 
+         return '1' ;
+       end if;
+    end function;
+
+    constant   QPLL_FBDIV_TOP   : integer  := 16;
+    constant   QPLL_FBDIV_IN    :   bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+    constant   QPLL_FBDIV_RATIO :   bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal  tied_to_vcc_vec_i               :   std_logic_vector(63 downto 0);
+
+begin
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    tied_to_vcc_vec_i(63 downto 0)      <= (others => '1');
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTXE2_COMMON____________________________________
+
+    gtxe2_common_i : GTXE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_QPLLREFCLK_SEL   => (SIM_QPLLREFCLK_SEL),
+            SIM_VERSION          => "4.0",
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000040000001000"),
+        COMMON_CFG                              =>     (x"00000000"),
+        QPLL_CFG                                =>     (x"06801C1"),
+        QPLL_CLKOUT_CFG                         =>     ("0000"),
+        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
+        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
+        QPLL_CP                                 =>     ("0000011111"),
+        QPLL_CP_MONITOR_EN                      =>     ('0'),
+        QPLL_DMONITOR_SEL                       =>     ('0'),
+        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
+        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
+        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
+        QPLL_INIT_CFG                           =>     (x"000006"),
+        QPLL_LOCK_CFG                           =>     (x"21E8"),
+        QPLL_LPF                                =>     ("1111"),
+        QPLL_REFCLK_DIV                         =>     (1)
+
+        
+    )
+    port map
+    (
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      GTREFCLK1_IN,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ------------------------- Common Block -  QPLL Ports -----------------------
+        QPLLDMONITOR                    =>      open,
+        ----------------------- Common Block - Clocking Ports ----------------------
+        QPLLOUTCLK                      =>      QPLLOUTCLK_OUT,
+        QPLLOUTREFCLK                   =>      QPLLOUTREFCLK_OUT,
+        REFCLKOUTMONITOR                =>      open,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        QPLLFBCLKLOST                   =>      open,
+        QPLLLOCK                        =>      QPLLLOCK_OUT,
+        QPLLLOCKDETCLK                  =>      QPLLLOCKDETCLK_IN,
+        QPLLLOCKEN                      =>      tied_to_vcc_i,
+        QPLLOUTRESET                    =>      tied_to_ground_i,
+        QPLLPD                          =>      tied_to_vcc_i,
+        QPLLREFCLKLOST                  =>      QPLLREFCLKLOST_OUT,
+        QPLLREFCLKSEL                   =>      QPLLREFCLKSEL_IN,
+        QPLLRESET                       =>      QPLLRESET_IN,
+        QPLLRSVD1                       =>      "0000000000000000",
+        QPLLRSVD2                       =>      "11111",
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "11111",
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_common_reset.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_common_reset.vhd
new file mode 100644
index 0000000..10667f9
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_common_reset.vhd
@@ -0,0 +1,154 @@
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_sodainput_common_reset.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module GTX_SODAinput_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_SODAinput_common_reset is 
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic:= '0'  --Reset QPLL
+   );
+end GTX_SODAinput_common_reset;
+
+architecture RTL of GTX_SODAinput_common_reset is
+
+
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+
+
+  signal init_wait_count  : std_logic_vector(7 downto 0) :=(others => '0');
+  signal init_wait_done   : std_logic :='0';
+  signal common_reset_asserted   : std_logic :='0';
+  signal common_reset_i   : std_logic ;
+
+  type rst_type is(
+    INIT, ASSERT_COMMON_RESET);
+    
+  signal state : rst_type := INIT;
+
+begin
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1') then
+        state                <= INIT;
+        common_reset_asserted   <= '0';
+        COMMON_RESET   <= '0';
+      else
+        
+        case state is
+          when INIT => 
+            if init_wait_done = '1' then
+              state        <= ASSERT_COMMON_RESET;
+            end if;
+            
+          when ASSERT_COMMON_RESET =>
+             if common_reset_asserted = '0' then
+                COMMON_RESET          <= '1';
+                common_reset_asserted  <= '1';
+              else
+                COMMON_RESET          <= '0';
+              end if;
+           when OTHERS =>
+            state   <= INIT;
+         end case;
+       end if;
+    end if;
+  end process;
+ 
+
+end RTL; 
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_gt_usrclk_source.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_gt_usrclk_source.vhd
new file mode 100644
index 0000000..08c7bb7
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_gt_usrclk_source.vhd
@@ -0,0 +1,208 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_sodainput_gt_usrclk_source.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+-- Module GTX_SODAinput_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_SODAinput_GT_USRCLK_SOURCE is
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXUSRCLKX2_OUT           : out std_logic; --// Modified
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_TXCLK_LOCK_OUT           : out std_logic;
+    GT0_TX_MMCM_RESET_IN         : in std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    Q3_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_OUT                    : out  std_logic
+);
+
+
+end GTX_SODAinput_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_SODAinput_GT_USRCLK_SOURCE is
+
+component GTX_SODAINPUT_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+    signal   tied_to_ground_i     :   std_logic;
+    signal   tied_to_vcc_i        :   std_logic;
+ 
+    signal   gt0_txoutclk_i :   std_logic;
+    signal   gt0_rxoutclk_i :   std_logic;
+
+--// Modified    attribute syn_noclockbuf : boolean;
+    signal   q3_clk0_gtrefclk :   std_logic;
+ --// Modified   attribute syn_noclockbuf of q3_clk0_gtrefclk : signal is true;
+
+    signal  gt0_txusrclk_i                  : std_logic;
+	
+    signal  gt0_rxusrclk_i                  : std_logic;
+    signal  txoutclk_mmcm0_locked_i         : std_logic;
+    signal  txoutclk_mmcm0_reset_i          : std_logic;
+    signal  gt0_txoutclk_to_mmcm_i          : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+    --  Static signal Assigments    
+    tied_to_ground_i         <= '0';
+    tied_to_vcc_i            <= '1';
+    gt0_txoutclk_i                               <= GT0_TXOUTCLK_IN;
+    gt0_rxoutclk_i                               <= GT0_RXOUTCLK_IN;
+
+    Q3_CLK0_GTREFCLK_OUT                         <= q3_clk0_gtrefclk;
+
+	--// Modified
+    -- --IBUFDS_GTE2
+    -- ibufds_instq3_clk0 : IBUFDS_GTE2  
+    -- port map
+    -- (
+        -- O               => 	q3_clk0_gtrefclk,
+        -- ODIV2           =>    open,
+        -- CEB             => 	tied_to_ground_i,
+        -- I               => 	Q3_CLK0_GTREFCLK_PAD_P_IN,
+        -- IB              => 	Q3_CLK0_GTREFCLK_PAD_N_IN
+    -- );
+
+
+    
+    -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+    -- for improved jitter performance, and to avoid consuming an additional BUFG
+    txoutclk_mmcm0_reset_i                       <= GT0_TX_MMCM_RESET_IN;
+    txoutclk_mmcm0_i : GTX_SODAinput_CLOCK_MODULE
+    generic map
+    (
+        MULT                            =>      16.0, --// 14.0 Modified 
+        DIVIDE                          =>      5,
+        CLK_PERIOD                      =>      4.0,
+        OUT0_DIVIDE                     =>      8.0, --// 7.0 Modified 
+        OUT1_DIVIDE                     =>      4, --// 1.0 Modified 
+        OUT2_DIVIDE                     =>      1,
+        OUT3_DIVIDE                     =>      1
+    )
+    port map
+    (
+        CLK0_OUT                        =>      gt0_txusrclk_i,
+        CLK1_OUT                        =>      GT0_TXUSRCLKX2_OUT, --// Modified
+        CLK2_OUT                        =>      open,
+        CLK3_OUT                        =>      open,
+        CLK_IN                          =>      gt0_txoutclk_i,
+        MMCM_LOCKED_OUT                 =>      txoutclk_mmcm0_locked_i,
+        MMCM_RESET_IN                   =>      txoutclk_mmcm0_reset_i
+    );
+
+
+    rxoutclk_bufg1_i : BUFG
+    port map
+    (
+        I                               =>      gt0_rxoutclk_i,
+        O                               =>      gt0_rxusrclk_i
+    );
+
+
+
+ 
+GT0_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT0_TXCLK_LOCK_OUT                           <= txoutclk_mmcm0_locked_i;
+GT0_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_support.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_support.vhd
new file mode 100644
index 0000000..17fc736
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_SODAinput_support/gtx_sodainput_support.vhd
@@ -0,0 +1,665 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_sodainput_support.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_SODAinput_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_SODAinput_support is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 10  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q3_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_OUT                    : out  std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_TXUSRCLKX2_OUT                      : out  std_logic; --// Modified
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT  : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT : out std_logic;
+        sysclk_in : in std_logic;
+	   q2_clk1_gtrefclk : in std_logic;  --//modification
+	   q3_clk0_gtrefclk : in std_logic  --//modification
+
+);
+
+end GTX_SODAinput_support;
+    
+architecture RTL of GTX_SODAinput_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_SODAinput
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+);
+
+end component;
+
+component GTX_SODAinput_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component GTX_SODAinput_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE" ;       -- Set to "TRUE" to speed up sim reset
+    SIM_QPLLREFCLK_SEL              :bit_vector  := "001"
+ 
+);
+port
+(
+    QPLLREFCLKSEL_IN   : in std_logic_vector(2 downto 0);
+    GTREFCLK0_IN : in std_logic;
+    GTREFCLK1_IN      : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_SODAinput_GT_USRCLK_SOURCE 
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXUSRCLKX2_OUT           : out std_logic; --// Modified
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_TXCLK_LOCK_OUT           : out std_logic;
+    GT0_TX_MMCM_RESET_IN         : in std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    Q3_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_OUT                    : out  std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y15)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt0_rxdlyen_i                   : std_logic;
+    signal  gt0_rxdlysreset_i               : std_logic;
+    signal  gt0_rxdlysresetdone_i           : std_logic;
+    signal  gt0_rxphalign_i                 : std_logic;
+    signal  gt0_rxphaligndone_i             : std_logic;
+    signal  gt0_rxphalignen_i               : std_logic;
+    signal  gt0_rxphdlyreset_i              : std_logic;
+    signal  gt0_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt0_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt0_txdlyen_i                   : std_logic;
+    signal  gt0_txdlysreset_i               : std_logic;
+    signal  gt0_txdlysresetdone_i           : std_logic;
+    signal  gt0_txphalign_i                 : std_logic;
+    signal  gt0_txphaligndone_i             : std_logic;
+    signal  gt0_txphalignen_i               : std_logic;
+    signal  gt0_txphdlyreset_i              : std_logic;
+    signal  gt0_txphinit_i                  : std_logic;
+    signal  gt0_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt0_txmmcm_lock_i               : std_logic;
+    signal    gt0_txmmcm_reset_i              : std_logic;
+    ----------------------------- Reference Clocks ----------------------------
+    
+signal    q3_clk0_refclk_i                : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+     GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i;
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+     gt0_qplloutclk_out <= gt0_qplloutclk_i;
+     gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+    
+  
+    gt_usrclk_source : GTX_SODAinput_GT_USRCLK_SOURCE
+    port map
+   (
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+		GT0_TXUSRCLKX2_OUT              =>      GT0_TXUSRCLKX2_OUT,  --// Modified
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_TXCLK_LOCK_OUT              =>      gt0_txmmcm_lock_i,
+        GT0_TX_MMCM_RESET_IN            =>      gt0_txmmcm_reset_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+        GT0_RXOUTCLK_IN                 =>      gt0_rxoutclk_i,
+        Q3_CLK0_GTREFCLK_PAD_N_IN       =>      Q3_CLK0_GTREFCLK_PAD_N_IN,
+        Q3_CLK0_GTREFCLK_PAD_P_IN       =>      Q3_CLK0_GTREFCLK_PAD_P_IN,
+        Q3_CLK0_GTREFCLK_OUT            =>      open  --// Modified q3_clk0_refclk_i
+
+    );
+q3_clk0_refclk_i <= q3_clk0_gtrefclk; --// Modified
+--//gt0_qplloutclk_i <= GT0_QPLLOUTCLK_IN; --// Modified
+--//gt0_qplloutrefclk_i <= GT0_QPLLOUTREFCLK_IN; --// Modified
+
+sysclk_in_i <= sysclk_in;
+
+    common0_i:GTX_SODAinput_common 
+  generic map
+  (
+   WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+   SIM_QPLLREFCLK_SEL => "001"
+  )
+ port map
+   (
+    QPLLREFCLKSEL_IN    => "001",
+    GTREFCLK0_IN      => q3_clk0_refclk_i,
+    GTREFCLK1_IN      => tied_to_ground_i,
+    QPLLLOCK_OUT => gt0_qplllock_i,
+    QPLLLOCKDETCLK_IN => sysclk_in_i,
+    QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+    -- common_reset_i:GTX_SODAinput_common_reset 
+   -- generic map 
+   -- (
+      -- STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   -- )
+   -- port map
+   -- (    
+      -- STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      -- SOFT_RESET => soft_reset_tx_in,               --User Reset, can be pulled any time
+      -- COMMON_RESET => commonreset_i              --Reset QPLL
+   -- );
+
+
+    GTX_SODAinput_init_i : GTX_SODAinput
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_tx_in                =>      SOFT_RESET_TX_IN,
+        soft_reset_rx_in                =>      SOFT_RESET_RX_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_mmcm_lock_in             =>      gt0_txmmcm_lock_i,
+        gt0_tx_mmcm_reset_out           =>      gt0_txmmcm_reset_i,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y15)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      q3_clk0_refclk_i,
+        gt0_gtrefclk1_in                =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+		------------------------- Receive Ports - CDR Ports ------------------------
+		GT0_RXCDRRESET_IN               =>      GT0_RXCDRRESET_IN, --// Modified
+		GT0_RXCDRLOCK_OUT               =>      GT0_RXCDRLOCK_OUT, --// Modified
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput/GTX_dataoutput.xci b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput/GTX_dataoutput.xci
new file mode 100644
index 0000000..cd1bb57
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput/GTX_dataoutput.xci
@@ -0,0 +1,1249 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>GTX_dataoutput</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gtwizard" spirit:version="3.6"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">GTX_dataoutput</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.example_chipscope">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">Programmable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_extended_timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tdlock_time">1000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">GTX_dataoutput</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.example_chipscope">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">Programmable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK0_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_extended_timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_line_rate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_line_rate">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">250.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tdlock_time">1000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_align_comma_word" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_comma_preset" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_decoding" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_dfe_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_drp_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_encoding" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxslide" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxbuf_en" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxslide_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxusrclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txbuf_en" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txoutclk_source" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val_rx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val_tx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_rx_pll" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_tx_pll" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_reference_clock" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_clock_module.vhd
similarity index 65%
rename from FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vhd
rename to data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_clock_module.vhd
index 251b107..8299046 100644
--- a/FEE_ADC32board/project/ipcore_dir/FEE_clockbuf80MHz.vhd
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_clock_module.vhd
@@ -1,209 +1,245 @@
--- file: FEE_clockbuf80MHz.vhd
--- 
--- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--- 
--- This file contains confidential and proprietary information
--- of Xilinx, Inc. and is protected under U.S. and
--- international copyright and other intellectual property
--- laws.
--- 
--- DISCLAIMER
--- This disclaimer is not a license and does not grant any
--- rights to the materials distributed herewith. Except as
--- otherwise provided in a valid license issued to you by
--- Xilinx, and to the maximum extent permitted by applicable
--- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
--- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
--- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
--- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
--- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
--- (2) Xilinx shall not be liable (whether in contract or tort,
--- including negligence, or under any other theory of
--- liability) for any loss or damage of any kind or nature
--- related to, arising under or in connection with these
--- materials, including for any direct, or any indirect,
--- special, incidental, or consequential loss or damage
--- (including loss of data, profits, goodwill, or any type of
--- loss or damage suffered as a result of any action brought
--- by a third party) even if such damage or loss was
--- reasonably foreseeable or Xilinx had been advised of the
--- possibility of the same.
--- 
--- CRITICAL APPLICATIONS
--- Xilinx products are not designed or intended to be fail-
--- safe, or for use in any application requiring fail-safe
--- performance, such as life-support or safety devices or
--- systems, Class III medical devices, nuclear facilities,
--- applications related to the deployment of airbags, or any
--- other applications that could lead to death, personal
--- injury, or severe property or environmental damage
--- (individually and collectively, "Critical
--- Applications"). Customer assumes the sole risk and
--- liability of any use of Xilinx products in Critical
--- Applications, subject only to applicable laws and
--- regulations governing limitations on product liability.
--- 
--- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
--- PART OF THIS FILE AT ALL TIMES.
--- 
-------------------------------------------------------------------------------
--- User entered comments
-------------------------------------------------------------------------------
--- None
---
-------------------------------------------------------------------------------
--- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
--- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
-------------------------------------------------------------------------------
--- CLK_OUT1____80.000______0.000______50.0______147.966____103.963
--- CLK_OUT2____80.000____180.000______50.0______147.966____103.963
---
-------------------------------------------------------------------------------
--- "Input Clock   Freq (MHz)    Input Jitter (UI)"
-------------------------------------------------------------------------------
--- __primary______________80____________0.010
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_arith.all;
-use ieee.numeric_std.all;
-
-library unisim;
-use unisim.vcomponents.all;
-
-entity FEE_clockbuf80MHz is
-port
- (-- Clock in ports
-  CLK_IN1           : in     std_logic;
-  -- Clock out ports
-  CLK_OUT1          : out    std_logic;
-  CLK_OUT2          : out    std_logic
- );
-end FEE_clockbuf80MHz;
-
-architecture xilinx of FEE_clockbuf80MHz is
-  attribute CORE_GENERATION_INFO : string;
-  attribute CORE_GENERATION_INFO of xilinx : architecture is "FEE_clockbuf80MHz,clk_wiz_v3_6,{component_name=FEE_clockbuf80MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=12.500,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-  -- Input clock buffering / unused connectors
-  signal clkin1      : std_logic;
-  -- Output clock buffering / unused connectors
-  signal clkfbout         : std_logic;
-  signal clkfbout_buf     : std_logic;
-  signal clkfboutb_unused : std_logic;
-  signal clkout0          : std_logic;
-  signal clkout0b_unused  : std_logic;
-  signal clkout1          : std_logic;
-  signal clkout1b_unused  : std_logic;
-  signal clkout2_unused   : std_logic;
-  signal clkout2b_unused  : std_logic;
-  signal clkout3_unused   : std_logic;
-  signal clkout3b_unused  : std_logic;
-  signal clkout4_unused   : std_logic;
-  signal clkout5_unused   : std_logic;
-  signal clkout6_unused   : std_logic;
-  -- Dynamic programming unused signals
-  signal do_unused        : std_logic_vector(15 downto 0);
-  signal drdy_unused      : std_logic;
-  -- Dynamic phase shift unused signals
-  signal psdone_unused    : std_logic;
-  -- Unused status signals
-  signal locked_unused    : std_logic;
-  signal clkfbstopped_unused : std_logic;
-  signal clkinstopped_unused : std_logic;
-begin
-
-
-  -- Input buffering
-  --------------------------------------
-  clkin1 <= CLK_IN1;
-
-
-  -- Clocking primitive
-  --------------------------------------
-  -- Instantiation of the MMCM primitive
-  --    * Unused inputs are tied off
-  --    * Unused outputs are labeled unused
-  mmcm_adv_inst : MMCM_ADV
-  generic map
-   (BANDWIDTH            => "OPTIMIZED",
-    CLKOUT4_CASCADE      => FALSE,
-    CLOCK_HOLD           => FALSE,
-    COMPENSATION         => "ZHOLD",
-    STARTUP_WAIT         => FALSE,
-    DIVCLK_DIVIDE        => 1,
-    CLKFBOUT_MULT_F      => 12.000,
-    CLKFBOUT_PHASE       => 0.000,
-    CLKFBOUT_USE_FINE_PS => FALSE,
-    CLKOUT0_DIVIDE_F     => 12.000,
-    CLKOUT0_PHASE        => 0.000,
-    CLKOUT0_DUTY_CYCLE   => 0.500,
-    CLKOUT0_USE_FINE_PS  => FALSE,
-    CLKOUT1_DIVIDE       => 12,
-    CLKOUT1_PHASE        => 180.000,
-    CLKOUT1_DUTY_CYCLE   => 0.500,
-    CLKOUT1_USE_FINE_PS  => FALSE,
-    CLKIN1_PERIOD        => 12.500,
-    REF_JITTER1          => 0.010)
-  port map
-    -- Output clocks
-   (CLKFBOUT            => clkfbout,
-    CLKFBOUTB           => clkfboutb_unused,
-    CLKOUT0             => clkout0,
-    CLKOUT0B            => clkout0b_unused,
-    CLKOUT1             => clkout1,
-    CLKOUT1B            => clkout1b_unused,
-    CLKOUT2             => clkout2_unused,
-    CLKOUT2B            => clkout2b_unused,
-    CLKOUT3             => clkout3_unused,
-    CLKOUT3B            => clkout3b_unused,
-    CLKOUT4             => clkout4_unused,
-    CLKOUT5             => clkout5_unused,
-    CLKOUT6             => clkout6_unused,
-    -- Input clock control
-    CLKFBIN             => clkfbout_buf,
-    CLKIN1              => clkin1,
-    CLKIN2              => '0',
-    -- Tied to always select the primary input clock
-    CLKINSEL            => '1',
-    -- Ports for dynamic reconfiguration
-    DADDR               => (others => '0'),
-    DCLK                => '0',
-    DEN                 => '0',
-    DI                  => (others => '0'),
-    DO                  => do_unused,
-    DRDY                => drdy_unused,
-    DWE                 => '0',
-    -- Ports for dynamic phase shift
-    PSCLK               => '0',
-    PSEN                => '0',
-    PSINCDEC            => '0',
-    PSDONE              => psdone_unused,
-    -- Other control and status signals
-    LOCKED              => locked_unused,
-    CLKINSTOPPED        => clkinstopped_unused,
-    CLKFBSTOPPED        => clkfbstopped_unused,
-    PWRDWN              => '0',
-    RST                 => '0');
-
-  -- Output buffering
-  -------------------------------------
-  clkf_buf : BUFG
-  port map
-   (O => clkfbout_buf,
-    I => clkfbout);
-
-
-  clkout1_buf : BUFG
-  port map
-   (O   => CLK_OUT1,
-    I   => clkout0);
-
-
-
-  clkout2_buf : BUFG
-  port map
-   (O   => CLK_OUT2,
-    I   => clkout1);
-
-end xilinx;
+-- file: clk_wiz_v2_1.vhd
+-- 
+-- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+-- Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1   100.000      0.000    50.000      130.958     98.575
+-- CLK_OUT2   200.000      0.000    50.000      114.829     98.575
+--
+------------------------------------------------------------------------------
+-- Input Clock   Input Freq (MHz)   Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary         100.000            0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_dataoutput_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end GTX_dataoutput_CLOCK_MODULE;
+
+architecture xilinx of GTX_dataoutput_CLOCK_MODULE is
+  attribute X_CORE_INFO : string;
+  attribute X_CORE_INFO of xilinx : architecture is "GTX_dataoutput,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfbout_buf     : std_logic;
+  signal clkfboutb_unused : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout0b_unused  : std_logic;
+  signal clkout1          : std_logic;
+  signal clkout1b_unused  : std_logic;
+  signal clkout2          : std_logic;
+  signal clkout2b_unused  : std_logic;
+  signal clkout3          : std_logic;
+  signal clkout3b_unused  : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  signal clkout6_unused   : std_logic;
+  -- Dynamic programming unused signals
+  signal do_unused        : std_logic_vector(15 downto 0);
+  signal drdy_unused      : std_logic;
+  -- Dynamic phase shift unused signals
+  signal psdone_unused    : std_logic;
+  -- Unused status signals
+  signal clkfbstopped_unused : std_logic;
+  signal clkinstopped_unused : std_logic;
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : BUFG
+  port map
+   (O => clkin1,
+    I => CLK_IN);
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the MMCM primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+
+  mmcm_adv_inst : MMCME2_ADV
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLKOUT4_CASCADE      => FALSE,
+    COMPENSATION         => "ZHOLD",
+    STARTUP_WAIT         => FALSE,
+    DIVCLK_DIVIDE        => DIVIDE,
+    CLKFBOUT_MULT_F      => MULT,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKFBOUT_USE_FINE_PS => FALSE,
+    CLKOUT0_DIVIDE_F     => OUT0_DIVIDE,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT0_USE_FINE_PS  => FALSE,
+    CLKIN1_PERIOD        => CLK_PERIOD,
+    CLKOUT1_DIVIDE       => OUT1_DIVIDE,
+    CLKOUT1_PHASE        => 0.000,
+    CLKOUT1_DUTY_CYCLE   => 0.500,
+    CLKOUT1_USE_FINE_PS  => FALSE,
+    CLKOUT2_DIVIDE       => OUT2_DIVIDE,
+    CLKOUT2_PHASE        => 0.000,
+    CLKOUT2_DUTY_CYCLE   => 0.500,
+    CLKOUT2_USE_FINE_PS  => FALSE,
+    CLKOUT3_DIVIDE       => OUT3_DIVIDE,
+    CLKOUT3_PHASE        => 0.000,
+    CLKOUT3_DUTY_CYCLE   => 0.500,
+    CLKOUT3_USE_FINE_PS  => FALSE,
+    REF_JITTER1          => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKFBOUTB           => clkfboutb_unused,
+    CLKOUT0             => clkout0,
+    CLKOUT0B            => clkout0b_unused,
+    CLKOUT1             => clkout1,
+    CLKOUT1B            => clkout1b_unused,
+    CLKOUT2             => clkout2,
+    CLKOUT2B            => clkout2b_unused,
+    CLKOUT3             => clkout3,
+    CLKOUT3B            => clkout3b_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    CLKOUT6             => clkout6_unused,
+    -- Input clock control
+    CLKFBIN             => clkfbout,
+    CLKIN1              => clkin1,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => do_unused,
+    DRDY                => drdy_unused,
+    DWE                 => '0',
+    -- Ports for dynamic phase shift
+    PSCLK               => '0',
+    PSEN                => '0',
+    PSINCDEC            => '0',
+    PSDONE              => psdone_unused,
+    -- Other control and status signals
+    LOCKED              => MMCM_LOCKED_OUT,
+    CLKINSTOPPED        => clkinstopped_unused,
+    CLKFBSTOPPED        => clkfbstopped_unused,
+    PWRDWN              => '0',
+    RST                 => MMCM_RESET_IN);
+
+  -- Output buffering
+  -------------------------------------
+  --clkf_buf : BUFG
+  --port map
+  -- (O => clkfbout_buf,
+  --  I => clkfbout);
+
+
+  clkout0_buf : BUFG
+  port map
+   (O   => CLK0_OUT,
+    I   => clkout0);
+
+  clkout1_buf : BUFG
+  port map
+   (O   => CLK1_OUT,
+    I   => clkout1);
+
+--  clkout2_buf : BUFG
+--  port map
+--   (O   => CLK2_OUT,
+--    I   => clkout2);
+--
+--  clkout3_buf : BUFG
+--  port map
+--   (O   => CLK3_OUT,
+--    I   => clkout3);
+
+CLK2_OUT <= '0';
+CLK3_OUT <= '0';
+end xilinx;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_common.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_common.vhd
new file mode 100644
index 0000000..e166383
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_common.vhd
@@ -0,0 +1,247 @@
+---------------------------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_dataoutput_common.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_dataoutput_common 
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_dataoutput_common is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "TRUE";        -- Set to "true" to speed up sim reset 
+    SIM_QPLLREFCLK_SEL              : bit_vector :=  "001"
+);
+port
+(
+    QPLLREFCLKSEL_IN  : in std_logic_vector(2 downto 0);
+    GTREFCLK1_IN      : in std_logic;
+    GTREFCLK0_IN : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+);
+
+end GTX_dataoutput_common;
+    
+architecture RTL of GTX_dataoutput_common is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_dataoutput_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+    impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return "0000100000";
+       elsif (qpllfbdiv_top = 20) then
+         return "0000110000" ;
+       elsif (qpllfbdiv_top = 32) then
+         return "0001100000" ;
+       elsif (qpllfbdiv_top = 40) then
+         return "0010000000" ;
+       elsif (qpllfbdiv_top = 64) then
+         return "0011100000" ;
+       elsif (qpllfbdiv_top = 66) then
+         return "0101000000" ;
+       elsif (qpllfbdiv_top = 80) then
+         return "0100100000" ;
+       elsif (qpllfbdiv_top = 100) then
+         return "0101110000" ;
+       else 
+         return "0000000000" ;
+       end if;
+    end function;
+
+    impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return '1';
+       elsif (qpllfbdiv_top = 20) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 32) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 40) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 64) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 66) then
+         return '0' ;
+       elsif (qpllfbdiv_top = 80) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 100) then
+         return '1' ;
+       else 
+         return '1' ;
+       end if;
+    end function;
+
+    constant   QPLL_FBDIV_TOP   : integer  := 16;
+    constant   QPLL_FBDIV_IN    :   bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+    constant   QPLL_FBDIV_RATIO :   bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal  tied_to_vcc_vec_i               :   std_logic_vector(63 downto 0);
+
+begin
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    tied_to_vcc_vec_i(63 downto 0)      <= (others => '1');
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTXE2_COMMON____________________________________
+
+    gtxe2_common_i : GTXE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_QPLLREFCLK_SEL   => (SIM_QPLLREFCLK_SEL),
+            SIM_VERSION          => "4.0",
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000040000001000"),
+        COMMON_CFG                              =>     (x"00000000"),
+        QPLL_CFG                                =>     (x"06801C1"),
+        QPLL_CLKOUT_CFG                         =>     ("0000"),
+        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
+        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
+        QPLL_CP                                 =>     ("0000011111"),
+        QPLL_CP_MONITOR_EN                      =>     ('0'),
+        QPLL_DMONITOR_SEL                       =>     ('0'),
+        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
+        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
+        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
+        QPLL_INIT_CFG                           =>     (x"000006"),
+        QPLL_LOCK_CFG                           =>     (x"21E8"),
+        QPLL_LPF                                =>     ("1111"),
+        QPLL_REFCLK_DIV                         =>     (1)
+
+        
+    )
+    port map
+    (
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      GTREFCLK1_IN,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ------------------------- Common Block -  QPLL Ports -----------------------
+        QPLLDMONITOR                    =>      open,
+        ----------------------- Common Block - Clocking Ports ----------------------
+        QPLLOUTCLK                      =>      QPLLOUTCLK_OUT,
+        QPLLOUTREFCLK                   =>      QPLLOUTREFCLK_OUT,
+        REFCLKOUTMONITOR                =>      open,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        QPLLFBCLKLOST                   =>      open,
+        QPLLLOCK                        =>      QPLLLOCK_OUT,
+        QPLLLOCKDETCLK                  =>      QPLLLOCKDETCLK_IN,
+        QPLLLOCKEN                      =>      tied_to_vcc_i,
+        QPLLOUTRESET                    =>      tied_to_ground_i,
+        QPLLPD                          =>      tied_to_vcc_i,
+        QPLLREFCLKLOST                  =>      QPLLREFCLKLOST_OUT,
+        QPLLREFCLKSEL                   =>      QPLLREFCLKSEL_IN,
+        QPLLRESET                       =>      QPLLRESET_IN,
+        QPLLRSVD1                       =>      "0000000000000000",
+        QPLLRSVD2                       =>      "11111",
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "11111",
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_common_reset.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_common_reset.vhd
new file mode 100644
index 0000000..2f2f902
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_common_reset.vhd
@@ -0,0 +1,154 @@
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_dataoutput_common_reset.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module GTX_dataoutput_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_dataoutput_common_reset is 
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic:= '0'  --Reset QPLL
+   );
+end GTX_dataoutput_common_reset;
+
+architecture RTL of GTX_dataoutput_common_reset is
+
+
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+
+
+  signal init_wait_count  : std_logic_vector(7 downto 0) :=(others => '0');
+  signal init_wait_done   : std_logic :='0';
+  signal common_reset_asserted   : std_logic :='0';
+  signal common_reset_i   : std_logic ;
+
+  type rst_type is(
+    INIT, ASSERT_COMMON_RESET);
+    
+  signal state : rst_type := INIT;
+
+begin
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1') then
+        state                <= INIT;
+        common_reset_asserted   <= '0';
+        COMMON_RESET   <= '0';
+      else
+        
+        case state is
+          when INIT => 
+            if init_wait_done = '1' then
+              state        <= ASSERT_COMMON_RESET;
+            end if;
+            
+          when ASSERT_COMMON_RESET =>
+             if common_reset_asserted = '0' then
+                COMMON_RESET          <= '1';
+                common_reset_asserted  <= '1';
+              else
+                COMMON_RESET          <= '0';
+              end if;
+           when OTHERS =>
+            state   <= INIT;
+         end case;
+       end if;
+    end if;
+  end process;
+ 
+
+end RTL; 
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_gt_usrclk_source.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_gt_usrclk_source.vhd
new file mode 100644
index 0000000..e8839ff
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_gt_usrclk_source.vhd
@@ -0,0 +1,205 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_dataoutput_gt_usrclk_source.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+-- Module GTX_dataoutput_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_dataoutput_GT_USRCLK_SOURCE is
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_TXCLK_LOCK_OUT           : out std_logic;
+    GT0_TX_MMCM_RESET_IN         : in std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    Q3_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_OUT                    : out  std_logic
+);
+
+
+end GTX_dataoutput_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_dataoutput_GT_USRCLK_SOURCE is
+
+component GTX_DATAOUTPUT_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+    signal   tied_to_ground_i     :   std_logic;
+    signal   tied_to_vcc_i        :   std_logic;
+ 
+    signal   gt0_txoutclk_i :   std_logic;
+    signal   gt0_rxoutclk_i :   std_logic;
+
+    attribute syn_noclockbuf : boolean;
+    signal   q3_clk0_gtrefclk :   std_logic;
+    attribute syn_noclockbuf of q3_clk0_gtrefclk : signal is true;
+
+    signal  gt0_txusrclk_i                  : std_logic;
+    signal  gt0_rxusrclk_i                  : std_logic;
+    signal  txoutclk_mmcm0_locked_i         : std_logic;
+    signal  txoutclk_mmcm0_reset_i          : std_logic;
+    signal  gt0_txoutclk_to_mmcm_i          : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+    --  Static signal Assigments    
+    tied_to_ground_i         <= '0';
+    tied_to_vcc_i            <= '1';
+    gt0_txoutclk_i                               <= GT0_TXOUTCLK_IN;
+    gt0_rxoutclk_i                               <= GT0_RXOUTCLK_IN;
+
+    Q3_CLK0_GTREFCLK_OUT                         <= q3_clk0_gtrefclk;
+
+    --IBUFDS_GTE2
+    ibufds_instq3_clk0 : IBUFDS_GTE2  
+    port map
+    (
+        O               => 	q3_clk0_gtrefclk,
+        ODIV2           =>    open,
+        CEB             => 	tied_to_ground_i,
+        I               => 	Q3_CLK0_GTREFCLK_PAD_P_IN,
+        IB              => 	Q3_CLK0_GTREFCLK_PAD_N_IN
+    );
+
+
+    
+    -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+    -- for improved jitter performance, and to avoid consuming an additional BUFG
+    txoutclk_mmcm0_reset_i                       <= GT0_TX_MMCM_RESET_IN;
+    txoutclk_mmcm0_i : GTX_dataoutput_CLOCK_MODULE
+    generic map
+    (
+        MULT                            =>      13.0,
+        DIVIDE                          =>      5,
+        CLK_PERIOD                      =>      4.0,
+        OUT0_DIVIDE                     =>      13.0,
+        OUT1_DIVIDE                     =>      1,
+        OUT2_DIVIDE                     =>      1,
+        OUT3_DIVIDE                     =>      1
+    )
+    port map
+    (
+        CLK0_OUT                        =>      gt0_txusrclk_i,
+        CLK1_OUT                        =>      open,
+        CLK2_OUT                        =>      open,
+        CLK3_OUT                        =>      open,
+        CLK_IN                          =>      gt0_txoutclk_i,
+        MMCM_LOCKED_OUT                 =>      txoutclk_mmcm0_locked_i,
+        MMCM_RESET_IN                   =>      txoutclk_mmcm0_reset_i
+    );
+
+
+    rxoutclk_bufg1_i : BUFG
+    port map
+    (
+        I                               =>      gt0_rxoutclk_i,
+        O                               =>      gt0_rxusrclk_i
+    );
+
+
+
+ 
+GT0_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT0_TXCLK_LOCK_OUT                           <= txoutclk_mmcm0_locked_i;
+GT0_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_support.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_support.vhd
new file mode 100644
index 0000000..fbe9933
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dataoutput_support/gtx_dataoutput_support.vhd
@@ -0,0 +1,656 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_dataoutput_support.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_dataoutput_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_dataoutput_support is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 10  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q3_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_OUT                    : out  std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;  --//modification
+     GT0_QPLLOUTREFCLK_IN : in std_logic;  --//modification
+       sysclk_in        : in std_logic;
+	q2_clk1_gtrefclk : in std_logic;  --//modification
+	q3_clk0_gtrefclk : in std_logic  --//modification
+
+);
+
+end GTX_dataoutput_support;
+    
+architecture RTL of GTX_dataoutput_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_dataoutput
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_dataoutput_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component GTX_dataoutput_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE" ;       -- Set to "TRUE" to speed up sim reset
+    SIM_QPLLREFCLK_SEL              :bit_vector  := "001"
+ 
+);
+port
+(
+    QPLLREFCLKSEL_IN   : in std_logic_vector(2 downto 0);
+    GTREFCLK0_IN : in std_logic;
+    GTREFCLK1_IN      : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_dataoutput_GT_USRCLK_SOURCE 
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_TXCLK_LOCK_OUT           : out std_logic;
+    GT0_TX_MMCM_RESET_IN         : in std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    Q3_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q3_CLK0_GTREFCLK_OUT                    : out  std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y14)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt0_rxdlyen_i                   : std_logic;
+    signal  gt0_rxdlysreset_i               : std_logic;
+    signal  gt0_rxdlysresetdone_i           : std_logic;
+    signal  gt0_rxphalign_i                 : std_logic;
+    signal  gt0_rxphaligndone_i             : std_logic;
+    signal  gt0_rxphalignen_i               : std_logic;
+    signal  gt0_rxphdlyreset_i              : std_logic;
+    signal  gt0_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt0_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt0_txdlyen_i                   : std_logic;
+    signal  gt0_txdlysreset_i               : std_logic;
+    signal  gt0_txdlysresetdone_i           : std_logic;
+    signal  gt0_txphalign_i                 : std_logic;
+    signal  gt0_txphaligndone_i             : std_logic;
+    signal  gt0_txphalignen_i               : std_logic;
+    signal  gt0_txphdlyreset_i              : std_logic;
+    signal  gt0_txphinit_i                  : std_logic;
+    signal  gt0_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt0_txmmcm_lock_i               : std_logic;
+    signal    gt0_txmmcm_reset_i              : std_logic;
+    ----------------------------- Reference Clocks ----------------------------
+    
+signal    q3_clk0_refclk_i                : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+     GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i;
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+--// Modified     gt0_qplloutclk_out <= gt0_qplloutclk_i;
+--// Modified     gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+    
+  
+    gt_usrclk_source : GTX_dataoutput_GT_USRCLK_SOURCE
+    port map
+   (
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_TXCLK_LOCK_OUT              =>      gt0_txmmcm_lock_i,
+        GT0_TX_MMCM_RESET_IN            =>      gt0_txmmcm_reset_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+        GT0_RXOUTCLK_IN                 =>      gt0_rxoutclk_i,
+        Q3_CLK0_GTREFCLK_PAD_N_IN       =>      Q3_CLK0_GTREFCLK_PAD_N_IN,
+        Q3_CLK0_GTREFCLK_PAD_P_IN       =>      Q3_CLK0_GTREFCLK_PAD_P_IN,
+        Q3_CLK0_GTREFCLK_OUT            =>      open --//modification q3_clk0_refclk_i
+
+    );
+q3_clk0_refclk_i <= q3_clk0_gtrefclk;  --//modification
+
+sysclk_in_i <= sysclk_in;
+
+gt0_qplloutclk_i <= GT0_QPLLOUTCLK_IN; --// Modified
+gt0_qplloutrefclk_i <= GT0_QPLLOUTREFCLK_IN; --// Modified
+
+--// Modified
+    -- common0_i:GTX_dataoutput_common 
+  -- generic map
+  -- (
+   -- WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+   -- SIM_QPLLREFCLK_SEL => "001"
+  -- )
+ -- port map
+   -- (
+    -- QPLLREFCLKSEL_IN    => "001",
+    -- GTREFCLK0_IN      => q3_clk0_refclk_i,
+    -- GTREFCLK1_IN      => tied_to_ground_i,
+    -- QPLLLOCK_OUT => gt0_qplllock_i,
+    -- QPLLLOCKDETCLK_IN => sysclk_in_i,
+    -- QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    -- QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    -- QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    -- QPLLRESET_IN => gt0_qpllreset_t
+
+-- );
+
+    common_reset_i:GTX_dataoutput_common_reset 
+   generic map 
+   (
+      STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   )
+   port map
+   (    
+      STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET => soft_reset_tx_in,               --User Reset, can be pulled any time
+      COMMON_RESET => commonreset_i              --Reset QPLL
+   );
+
+
+    GTX_dataoutput_init_i : GTX_dataoutput
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_tx_in                =>      SOFT_RESET_TX_IN,
+        soft_reset_rx_in                =>      SOFT_RESET_RX_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_mmcm_lock_in             =>      gt0_txmmcm_lock_i,
+        gt0_tx_mmcm_reset_out           =>      gt0_txmmcm_reset_i,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y14)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      q3_clk0_refclk_i,
+        gt0_gtrefclk1_in                =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA/GTX_dualSODA.xci b/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA/GTX_dualSODA.xci
new file mode 100644
index 0000000..ef7d78e
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA/GTX_dualSODA.xci
@@ -0,0 +1,1249 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>GTX_dualSODA</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gtwizard" spirit:version="3.6"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">GTX_dualSODA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.example_chipscope">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">Programmable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_extended_timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.tdlock_time">1000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">GTX_dualSODA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.example_chipscope">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">Programmable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_extended_timeout">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.tdlock_time">1000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_align_comma_word" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_comma_preset" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_decoding" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_dfe_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_drp_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_encoding" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxslide" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxbuf_en" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxslide_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxusrclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txbuf_en" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txoutclk_source" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt12_val" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt12_val_rx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt12_val_tx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt13_val" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt13_val_rx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt13_val_tx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_rx_pll" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_tx_pll" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_reference_clock" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_common.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_common.vhd
new file mode 100644
index 0000000..72345c7
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_common.vhd
@@ -0,0 +1,247 @@
+---------------------------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_dualsoda_common.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_dualSODA_common 
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_dualSODA_common is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "TRUE";        -- Set to "true" to speed up sim reset 
+    SIM_QPLLREFCLK_SEL              : bit_vector :=  "001"
+);
+port
+(
+    QPLLREFCLKSEL_IN  : in std_logic_vector(2 downto 0);
+    GTREFCLK1_IN      : in std_logic;
+    GTREFCLK0_IN : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+);
+
+end GTX_dualSODA_common;
+    
+architecture RTL of GTX_dualSODA_common is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_dualSODA_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+    impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return "0000100000";
+       elsif (qpllfbdiv_top = 20) then
+         return "0000110000" ;
+       elsif (qpllfbdiv_top = 32) then
+         return "0001100000" ;
+       elsif (qpllfbdiv_top = 40) then
+         return "0010000000" ;
+       elsif (qpllfbdiv_top = 64) then
+         return "0011100000" ;
+       elsif (qpllfbdiv_top = 66) then
+         return "0101000000" ;
+       elsif (qpllfbdiv_top = 80) then
+         return "0100100000" ;
+       elsif (qpllfbdiv_top = 100) then
+         return "0101110000" ;
+       else 
+         return "0000000000" ;
+       end if;
+    end function;
+
+    impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return '1';
+       elsif (qpllfbdiv_top = 20) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 32) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 40) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 64) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 66) then
+         return '0' ;
+       elsif (qpllfbdiv_top = 80) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 100) then
+         return '1' ;
+       else 
+         return '1' ;
+       end if;
+    end function;
+
+    constant   QPLL_FBDIV_TOP   : integer  := 16;
+    constant   QPLL_FBDIV_IN    :   bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+    constant   QPLL_FBDIV_RATIO :   bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal  tied_to_vcc_vec_i               :   std_logic_vector(63 downto 0);
+
+begin
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    tied_to_vcc_vec_i(63 downto 0)      <= (others => '1');
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTXE2_COMMON____________________________________
+
+    gtxe2_common_i : GTXE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_QPLLREFCLK_SEL   => (SIM_QPLLREFCLK_SEL),
+            SIM_VERSION          => "4.0",
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000040000001000"),
+        COMMON_CFG                              =>     (x"00000000"),
+        QPLL_CFG                                =>     (x"06801C1"),
+        QPLL_CLKOUT_CFG                         =>     ("0000"),
+        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
+        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
+        QPLL_CP                                 =>     ("0000011111"),
+        QPLL_CP_MONITOR_EN                      =>     ('0'),
+        QPLL_DMONITOR_SEL                       =>     ('0'),
+        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
+        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
+        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
+        QPLL_INIT_CFG                           =>     (x"000006"),
+        QPLL_LOCK_CFG                           =>     (x"21E8"),
+        QPLL_LPF                                =>     ("1111"),
+        QPLL_REFCLK_DIV                         =>     (1)
+
+        
+    )
+    port map
+    (
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      GTREFCLK1_IN,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ------------------------- Common Block -  QPLL Ports -----------------------
+        QPLLDMONITOR                    =>      open,
+        ----------------------- Common Block - Clocking Ports ----------------------
+        QPLLOUTCLK                      =>      QPLLOUTCLK_OUT,
+        QPLLOUTREFCLK                   =>      QPLLOUTREFCLK_OUT,
+        REFCLKOUTMONITOR                =>      open,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        QPLLFBCLKLOST                   =>      open,
+        QPLLLOCK                        =>      QPLLLOCK_OUT,
+        QPLLLOCKDETCLK                  =>      QPLLLOCKDETCLK_IN,
+        QPLLLOCKEN                      =>      tied_to_vcc_i,
+        QPLLOUTRESET                    =>      tied_to_ground_i,
+        QPLLPD                          =>      tied_to_vcc_i,
+        QPLLREFCLKLOST                  =>      QPLLREFCLKLOST_OUT,
+        QPLLREFCLKSEL                   =>      QPLLREFCLKSEL_IN,
+        QPLLRESET                       =>      QPLLRESET_IN,
+        QPLLRSVD1                       =>      "0000000000000000",
+        QPLLRSVD2                       =>      "11111",
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "11111",
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_common_reset.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_common_reset.vhd
new file mode 100644
index 0000000..dc79771
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_common_reset.vhd
@@ -0,0 +1,154 @@
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_dualsoda_common_reset.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module GTX_dualSODA_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_dualSODA_common_reset is 
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic:= '0'  --Reset QPLL
+   );
+end GTX_dualSODA_common_reset;
+
+architecture RTL of GTX_dualSODA_common_reset is
+
+
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+
+
+  signal init_wait_count  : std_logic_vector(7 downto 0) :=(others => '0');
+  signal init_wait_done   : std_logic :='0';
+  signal common_reset_asserted   : std_logic :='0';
+  signal common_reset_i   : std_logic ;
+
+  type rst_type is(
+    INIT, ASSERT_COMMON_RESET);
+    
+  signal state : rst_type := INIT;
+
+begin
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1') then
+        state                <= INIT;
+        common_reset_asserted   <= '0';
+        COMMON_RESET   <= '0';
+      else
+        
+        case state is
+          when INIT => 
+            if init_wait_done = '1' then
+              state        <= ASSERT_COMMON_RESET;
+            end if;
+            
+          when ASSERT_COMMON_RESET =>
+             if common_reset_asserted = '0' then
+                COMMON_RESET          <= '1';
+                common_reset_asserted  <= '1';
+              else
+                COMMON_RESET          <= '0';
+              end if;
+           when OTHERS =>
+            state   <= INIT;
+         end case;
+       end if;
+    end if;
+  end process;
+ 
+
+end RTL; 
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_gt_usrclk_source.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_gt_usrclk_source.vhd
new file mode 100644
index 0000000..1a4e88b
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_gt_usrclk_source.vhd
@@ -0,0 +1,201 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_dualsoda_gt_usrclk_source.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+-- Module GTX_dualSODA_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_dualSODA_GT_USRCLK_SOURCE is
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT1_TXUSRCLK_OUT             : out std_logic;
+    GT1_TXUSRCLK2_OUT            : out std_logic;
+    GT1_TXOUTCLK_IN              : in  std_logic;
+    GT1_RXUSRCLK_OUT             : out std_logic;
+    GT1_RXUSRCLK2_OUT            : out std_logic;
+    GT1_RXOUTCLK_IN              : in  std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_OUT                    : out  std_logic
+);
+
+
+end GTX_dualSODA_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_dualSODA_GT_USRCLK_SOURCE is
+
+component GTX_DUALSODA_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+    signal   tied_to_ground_i     :   std_logic;
+    signal   tied_to_vcc_i        :   std_logic;
+ 
+    signal   gt0_txoutclk_i :   std_logic;
+    signal   gt0_rxoutclk_i :   std_logic;
+ 
+    signal   gt1_txoutclk_i :   std_logic;
+    signal   gt1_rxoutclk_i :   std_logic;
+
+--// Modified    attribute syn_noclockbuf : boolean;
+    signal   q2_clk1_gtrefclk :   std_logic;
+--// Modified    attribute syn_noclockbuf of q2_clk1_gtrefclk : signal is true;
+
+    signal  gt0_txusrclk_i                  : std_logic;
+    signal  gt0_rxusrclk_i                  : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+    --  Static signal Assigments    
+    tied_to_ground_i         <= '0';
+    tied_to_vcc_i            <= '1';
+    gt0_txoutclk_i                               <= GT0_TXOUTCLK_IN;
+    gt0_rxoutclk_i                               <= GT0_RXOUTCLK_IN;
+    gt1_txoutclk_i                               <= GT1_TXOUTCLK_IN;
+    gt1_rxoutclk_i                               <= GT1_RXOUTCLK_IN;
+
+    Q2_CLK1_GTREFCLK_OUT                         <= q2_clk1_gtrefclk;
+
+	--// Modified
+    --IBUFDS_GTE2
+    -- ibufds_instq2_clk1 : IBUFDS_GTE2  
+    -- port map
+    -- (
+        -- O               => 	q2_clk1_gtrefclk,
+        -- ODIV2           =>    open,
+        -- CEB             => 	tied_to_ground_i,
+        -- I               => 	Q2_CLK1_GTREFCLK_PAD_P_IN,
+        -- IB              => 	Q2_CLK1_GTREFCLK_PAD_N_IN
+    -- );
+
+
+    
+    -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+    -- for improved jitter performance, and to avoid consuming an additional BUFG
+    txoutclk_bufg0_i : BUFG
+    port map
+    (
+        I                               =>      gt0_txoutclk_i,
+        O                               =>      gt0_txusrclk_i
+    );
+
+
+    rxoutclk_bufg1_i : BUFG
+    port map
+    (
+        I                               =>      gt0_rxoutclk_i,
+        O                               =>      gt0_rxusrclk_i
+    );
+
+
+
+ 
+GT0_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT0_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+ 
+GT1_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT1_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT1_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT1_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_support.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_support.vhd
new file mode 100644
index 0000000..9e9f5fc
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_dualSODA_support/gtx_dualsoda_support.vhd
@@ -0,0 +1,1017 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_dualsoda_support.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_dualSODA_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_dualSODA_support is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 10  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT1_TXUSRCLK_OUT                        : out  std_logic;
+    GT1_TXUSRCLK2_OUT                       : out  std_logic;
+    GT1_RXUSRCLK_OUT                        : out  std_logic;
+    GT1_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt1_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt1_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;  --//modification
+     GT0_QPLLOUTREFCLK_IN : in std_logic;  --//modification
+		sysclk_in        : in std_logic;
+		q2_clk1_gtrefclk : in std_logic;  --//modification
+		q3_clk0_gtrefclk : in std_logic  --//modification
+);
+
+end GTX_dualSODA_support;
+    
+architecture RTL of GTX_dualSODA_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_dualSODA
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cplllockdetclk_in                   : in   std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt1_gtrefclk0_in                        : in   std_logic;
+    gt1_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpclk_in                           : in   std_logic;
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt1_rxusrclk_in                         : in   std_logic;
+    gt1_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt1_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt1_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt1_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt1_txusrclk_in                         : in   std_logic;
+    gt1_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclk_out                        : out  std_logic;
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_dualSODA_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component GTX_dualSODA_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE" ;       -- Set to "TRUE" to speed up sim reset
+    SIM_QPLLREFCLK_SEL              :bit_vector  := "001"
+ 
+);
+port
+(
+    QPLLREFCLKSEL_IN   : in std_logic_vector(2 downto 0);
+    GTREFCLK0_IN : in std_logic;
+    GTREFCLK1_IN      : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_dualSODA_GT_USRCLK_SOURCE 
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+ 
+    GT1_TXUSRCLK_OUT             : out std_logic;
+    GT1_TXUSRCLK2_OUT            : out std_logic;
+    GT1_TXOUTCLK_IN              : in  std_logic;
+    GT1_RXUSRCLK_OUT             : out std_logic;
+    GT1_RXUSRCLK2_OUT            : out std_logic;
+    GT1_RXOUTCLK_IN              : in  std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_OUT                    : out  std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+    signal   gt1_txfsmresetdone_i            : std_logic;
+signal   gt1_rxfsmresetdone_i            : std_logic;
+    signal   gt1_txfsmresetdone_r            : std_logic;
+    signal   gt1_txfsmresetdone_r2           : std_logic;
+signal   gt1_rxresetdone_r               : std_logic;
+signal   gt1_rxresetdone_r2              : std_logic;
+signal   gt1_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y12)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt0_rxdlyen_i                   : std_logic;
+    signal  gt0_rxdlysreset_i               : std_logic;
+    signal  gt0_rxdlysresetdone_i           : std_logic;
+    signal  gt0_rxphalign_i                 : std_logic;
+    signal  gt0_rxphaligndone_i             : std_logic;
+    signal  gt0_rxphalignen_i               : std_logic;
+    signal  gt0_rxphdlyreset_i              : std_logic;
+    signal  gt0_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt0_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt0_txdlyen_i                   : std_logic;
+    signal  gt0_txdlysreset_i               : std_logic;
+    signal  gt0_txdlysresetdone_i           : std_logic;
+    signal  gt0_txphalign_i                 : std_logic;
+    signal  gt0_txphaligndone_i             : std_logic;
+    signal  gt0_txphalignen_i               : std_logic;
+    signal  gt0_txphdlyreset_i              : std_logic;
+    signal  gt0_txphinit_i                  : std_logic;
+    signal  gt0_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT1  (X1Y13)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt1_cpllfbclklost_i             : std_logic;
+    signal  gt1_cplllock_i                  : std_logic;
+    signal  gt1_cpllrefclklost_i            : std_logic;
+    signal  gt1_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt1_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt1_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt1_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt1_drpen_i                     : std_logic;
+    signal  gt1_drprdy_i                    : std_logic;
+    signal  gt1_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt1_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt1_eyescanreset_i              : std_logic;
+    signal  gt1_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt1_eyescandataerror_i          : std_logic;
+    signal  gt1_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt1_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt1_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt1_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt1_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt1_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt1_rxdlyen_i                   : std_logic;
+    signal  gt1_rxdlysreset_i               : std_logic;
+    signal  gt1_rxdlysresetdone_i           : std_logic;
+    signal  gt1_rxphalign_i                 : std_logic;
+    signal  gt1_rxphaligndone_i             : std_logic;
+    signal  gt1_rxphalignen_i               : std_logic;
+    signal  gt1_rxphdlyreset_i              : std_logic;
+    signal  gt1_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt1_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt1_rxlpmhfhold_i               : std_logic;
+    signal  gt1_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt1_rxdfelpmreset_i             : std_logic;
+    signal  gt1_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt1_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt1_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt1_gtrxreset_i                 : std_logic;
+    signal  gt1_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt1_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt1_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt1_gttxreset_i                 : std_logic;
+    signal  gt1_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt1_txdlyen_i                   : std_logic;
+    signal  gt1_txdlysreset_i               : std_logic;
+    signal  gt1_txdlysresetdone_i           : std_logic;
+    signal  gt1_txphalign_i                 : std_logic;
+    signal  gt1_txphaligndone_i             : std_logic;
+    signal  gt1_txphalignen_i               : std_logic;
+    signal  gt1_txphdlyreset_i              : std_logic;
+    signal  gt1_txphinit_i                  : std_logic;
+    signal  gt1_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt1_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt1_gtxtxn_i                    : std_logic;
+    signal  gt1_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt1_txoutclk_i                  : std_logic;
+    signal  gt1_txoutclkfabric_i            : std_logic;
+    signal  gt1_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt1_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt1_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  gt1_tx_system_reset_c           : std_logic;
+    signal  gt1_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt1_txusrclk_i                  : std_logic; 
+    signal    gt1_txusrclk2_i                 : std_logic; 
+    signal    gt1_rxusrclk_i                  : std_logic; 
+    signal    gt1_rxusrclk2_i                 : std_logic; 
+
+signal    q2_clk1_refclk_i                : std_logic;
+
+signal commonreset_i : std_logic;
+
+attribute mark_debug : string;
+
+
+
+-- attribute mark_debug of SOFT_RESET_TX_IN : signal is "true";
+-- attribute mark_debug of DONT_RESET_ON_DATA_ERROR_IN : signal is "true";
+-- attribute mark_debug of gt0_tx_fsm_reset_done_out : signal is "true";
+-- attribute mark_debug of gt0_rx_fsm_reset_done_out : signal is "true";
+-- attribute mark_debug of gt0_data_valid_in : signal is "true";
+-- attribute mark_debug of gt0_cpllfbclklost_out : signal is "true";
+-- attribute mark_debug of gt0_cplllock_out : signal is "true";
+-- attribute mark_debug of gt0_cpllreset_in : signal is "true";
+-- attribute mark_debug of gt0_rxuserrdy_in : signal is "true";
+-- attribute mark_debug of gt0_rxdata_out : signal is "true";
+-- attribute mark_debug of gt0_rxcharisk_out : signal is "true";
+-- attribute mark_debug of gt0_rxdisperr_out : signal is "true";
+-- attribute mark_debug of gt0_rxnotintable_out : signal is "true";
+-- attribute mark_debug of gt0_gtrxreset_in : signal is "true";
+-- attribute mark_debug of gt0_rxpmareset_in : signal is "true";
+-- attribute mark_debug of gt0_rxresetdone_out : signal is "true";
+-- attribute mark_debug of gt0_gttxreset_in : signal is "true";
+-- attribute mark_debug of gt0_txuserrdy_in : signal is "true";
+-- attribute mark_debug of gt0_txdata_in : signal is "true";
+-- attribute mark_debug of gt0_txcharisk_in : signal is "true";
+-- attribute mark_debug of gt0_txresetdone_out : signal is "true";
+
+
+
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+--// Modified     gt0_qplloutclk_out <= gt0_qplloutclk_i;
+--// Modified     gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+ 
+      GT1_TXUSRCLK_OUT <= gt1_txusrclk_i; 
+      GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
+      GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
+      GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
+
+
+    
+  
+    
+  
+    gt_usrclk_source : GTX_dualSODA_GT_USRCLK_SOURCE
+    port map
+   (
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+        GT0_RXOUTCLK_IN                 =>      gt0_rxoutclk_i,
+ 
+        GT1_TXUSRCLK_OUT                =>      gt1_txusrclk_i,
+        GT1_TXUSRCLK2_OUT               =>      gt1_txusrclk2_i,
+        GT1_TXOUTCLK_IN                 =>      gt1_txoutclk_i,
+        GT1_RXUSRCLK_OUT                =>      gt1_rxusrclk_i,
+        GT1_RXUSRCLK2_OUT               =>      gt1_rxusrclk2_i,
+        GT1_RXOUTCLK_IN                 =>      gt1_rxoutclk_i,
+        Q2_CLK1_GTREFCLK_PAD_N_IN       =>      Q2_CLK1_GTREFCLK_PAD_N_IN,
+        Q2_CLK1_GTREFCLK_PAD_P_IN       =>      Q2_CLK1_GTREFCLK_PAD_P_IN,
+        Q2_CLK1_GTREFCLK_OUT            =>      open  --// Modified q2_clk1_refclk_i
+
+    );
+q2_clk1_refclk_i <= q2_clk1_gtrefclk; --// Modified
+
+sysclk_in_i <= sysclk_in;
+
+gt0_qplloutclk_i <= GT0_QPLLOUTCLK_IN; --// Modified
+gt0_qplloutrefclk_i <= GT0_QPLLOUTREFCLK_IN; --// Modified
+
+--// Modified
+    -- common0_i:GTX_dualSODA_common 
+  -- generic map
+  -- (
+   -- WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+   -- SIM_QPLLREFCLK_SEL => "001"
+  -- )
+ -- port map
+   -- (
+    -- QPLLREFCLKSEL_IN    => "001",
+    -- GTREFCLK0_IN      => q3_clk0_gtrefclk, --// Modified tied_to_ground_i,
+    -- GTREFCLK1_IN      => q2_clk1_refclk_i,
+    -- QPLLLOCK_OUT => gt0_qplllock_i,
+    -- QPLLLOCKDETCLK_IN => sysclk_in_i,
+    -- QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    -- QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    -- QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    -- QPLLRESET_IN => gt0_qpllreset_t
+
+-- );
+
+    common_reset_i:GTX_dualSODA_common_reset 
+   generic map 
+   (
+      STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   )
+   port map
+   (    
+      STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET => soft_reset_tx_in,               --User Reset, can be pulled any time
+      COMMON_RESET => commonreset_i              --Reset QPLL
+   );
+
+
+    GTX_dualSODA_init_i : GTX_dualSODA
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_tx_in                =>      SOFT_RESET_TX_IN,
+        soft_reset_rx_in                =>      SOFT_RESET_RX_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+        gt1_tx_fsm_reset_done_out       =>      gt1_tx_fsm_reset_done_out,
+        gt1_rx_fsm_reset_done_out       =>      gt1_rx_fsm_reset_done_out,
+        gt1_data_valid_in               =>      gt1_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y12)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      tied_to_ground_i,
+        gt0_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT1  (X1Y13)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt1_cpllfbclklost_out           =>      gt1_cpllfbclklost_out,
+        gt1_cplllock_out                =>      gt1_cplllock_out,
+        gt1_cplllockdetclk_in           =>      sysclk_in_i,
+        gt1_cpllreset_in                =>      gt1_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt1_gtrefclk0_in                =>      tied_to_ground_i,
+        gt1_gtrefclk1_in                =>      q2_clk1_refclk_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt1_drpaddr_in                  =>      gt1_drpaddr_in,
+        gt1_drpclk_in                   =>      sysclk_in_i,
+        gt1_drpdi_in                    =>      gt1_drpdi_in,
+        gt1_drpdo_out                   =>      gt1_drpdo_out,
+        gt1_drpen_in                    =>      gt1_drpen_in,
+        gt1_drprdy_out                  =>      gt1_drprdy_out,
+        gt1_drpwe_in                    =>      gt1_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt1_dmonitorout_out             =>      gt1_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt1_eyescanreset_in             =>      gt1_eyescanreset_in,
+        gt1_rxuserrdy_in                =>      gt1_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt1_eyescandataerror_out        =>      gt1_eyescandataerror_out,
+        gt1_eyescantrigger_in           =>      gt1_eyescantrigger_in,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt1_rxusrclk_in                 =>      gt1_rxusrclk_i,
+        gt1_rxusrclk2_in                =>      gt1_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt1_rxdata_out                  =>      gt1_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt1_rxdisperr_out               =>      gt1_rxdisperr_out,
+        gt1_rxnotintable_out            =>      gt1_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt1_gtxrxp_in                   =>      gt1_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt1_gtxrxn_in                   =>      gt1_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt1_rxphmonitor_out             =>      gt1_rxphmonitor_out,
+        gt1_rxphslipmonitor_out         =>      gt1_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt1_rxdfelpmreset_in            =>      gt1_rxdfelpmreset_in,
+        gt1_rxmonitorout_out            =>      gt1_rxmonitorout_out,
+        gt1_rxmonitorsel_in             =>      gt1_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt1_rxoutclk_out                =>      gt1_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt1_gtrxreset_in                =>      gt1_gtrxreset_in,
+        gt1_rxpmareset_in               =>      gt1_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt1_rxcharisk_out               =>      gt1_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt1_rxresetdone_out             =>      gt1_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt1_gttxreset_in                =>      gt1_gttxreset_in,
+        gt1_txuserrdy_in                =>      gt1_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt1_txusrclk_in                 =>      gt1_txusrclk_i,
+        gt1_txusrclk2_in                =>      gt1_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt1_txdata_in                   =>      gt1_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt1_gtxtxn_out                  =>      gt1_gtxtxn_out,
+        gt1_gtxtxp_out                  =>      gt1_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt1_txoutclk_out                =>      gt1_txoutclk_i,
+        gt1_txoutclkfabric_out          =>      gt1_txoutclkfabric_out,
+        gt1_txoutclkpcs_out             =>      gt1_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt1_txcharisk_in                =>      gt1_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt1_txresetdone_out             =>      gt1_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/GTX_quadSODA.xci b/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/GTX_quadSODA.xci
new file mode 100644
index 0000000..ac4a104
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/GTX_quadSODA.xci
@@ -0,0 +1,1250 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com"
+		xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
+		xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+	<spirit:vendor>xilinx.com</spirit:vendor>
+	<spirit:library>xci</spirit:library>
+	<spirit:name>unknown</spirit:name>
+	<spirit:version>1.0</spirit:version>
+	<spirit:componentInstances>
+		<spirit:componentInstance>
+			<spirit:instanceName>GTX_quadSODA</spirit:instanceName>
+			<spirit:componentRef spirit:vendor="xilinx.com"
+					spirit:library="ip"
+					spirit:name="gtwizard"
+					spirit:version="3.5"/>
+			<spirit:configurableElementValues>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">GTX_quadSODA</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">3</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">80</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">GTX_quadSODA</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">200.000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">80</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">3</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">200.000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k325t</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Manual</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N1">5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N2">8</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_L">0.5</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+				<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.1</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+				<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+				<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+			</spirit:configurableElementValues>
+			<spirit:vendorExtensions>
+				<xilinx:componentInstanceExtensions>
+					<xilinx:configElementInfos>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt12_val_tx_refclk"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt12_val_rx_refclk"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt13_val_tx_refclk"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt13_val_rx_refclk"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val_tx_refclk"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val_rx_refclk"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt15_val_tx_refclk"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt15_val_rx_refclk"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.advanced_clocking"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_reference_clock"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_reference_clock"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_line_rate"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_data_width"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_line_rate"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_data_width"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxbuf_en"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxusrclk"
+								xilinx:valueSource="user"/>
+						<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_uselabtools"
+								xilinx:valueSource="user"/>
+					</xilinx:configElementInfos>
+				</xilinx:componentInstanceExtensions>
+			</spirit:vendorExtensions>
+		</spirit:componentInstance>
+	</spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/xci/ila_0.xci b/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/xci/ila_0.xci
new file mode 100644
index 0000000..1586f34
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/xci/ila_0.xci
@@ -0,0 +1,2102 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>ila_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ila" spirit:version="5.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1023_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1022_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1021_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1020_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1019_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1018_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1017_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1016_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1015_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1014_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1013_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1012_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1011_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1010_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1009_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1008_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1007_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1006_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1005_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1004_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1003_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1002_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1001_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1000_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE999_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE998_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE997_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE996_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE995_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE994_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE993_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE992_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE991_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE990_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE989_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE988_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE987_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE986_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE985_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE984_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE983_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE982_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE981_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE980_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE979_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE978_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE977_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE976_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE975_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE974_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE973_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE972_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE971_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE970_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE969_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE968_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE967_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE966_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE965_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE964_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE963_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE962_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE961_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE960_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE959_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE958_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE957_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE956_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE955_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE954_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE953_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE952_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE951_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE950_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE949_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE948_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE947_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE946_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE945_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE944_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE943_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE942_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE941_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE940_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE939_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE938_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE937_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE936_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE935_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE934_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE933_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE932_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE931_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE930_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE929_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE928_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE927_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE926_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE925_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE924_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE923_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE922_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE921_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE920_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE919_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE918_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE917_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE916_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE915_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE914_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE913_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE912_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE911_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE910_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE909_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE908_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE907_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE906_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE905_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE904_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE903_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE902_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE901_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE900_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE899_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE898_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE897_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE896_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE895_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE894_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE893_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE892_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE891_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE890_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE889_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE888_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE887_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE886_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE885_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE884_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE883_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE882_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE881_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE880_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE879_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE878_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE877_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE876_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE875_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE874_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE873_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE872_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE871_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE870_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE869_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE868_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE867_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE866_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE865_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE864_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE863_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE862_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE861_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE860_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE859_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE858_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE857_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE856_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE855_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE854_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE853_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE852_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE851_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE850_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE849_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE848_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE847_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE846_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE845_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE844_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE843_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE842_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE841_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE840_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE839_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE838_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE837_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE836_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE835_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE834_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE833_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE832_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE831_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE830_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE829_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE828_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE827_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE826_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE825_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE824_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE823_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE822_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE821_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE820_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE819_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE818_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE817_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE816_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE815_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE814_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE813_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE812_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE811_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE810_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE809_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE808_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE807_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE806_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE805_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE804_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE803_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE802_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE801_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE800_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE799_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE798_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE797_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE796_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE795_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE794_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE793_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE792_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE791_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE790_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE789_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE788_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE787_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE786_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE785_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE784_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE783_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE782_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE781_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE780_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE779_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE778_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE777_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE776_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE775_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE774_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE773_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE772_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE771_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE770_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE769_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE768_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE767_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE766_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE765_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE764_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE763_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE762_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE761_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE760_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE759_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE758_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE757_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE756_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE755_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE754_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE753_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE752_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE751_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE750_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE749_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE748_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE747_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE746_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE745_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE744_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE743_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE742_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE741_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE740_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE739_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE738_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE737_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE736_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE735_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE734_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE733_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE732_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE731_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE730_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE729_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE728_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE727_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE726_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE725_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE724_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE723_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE722_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE721_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE720_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE719_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE718_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE717_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE716_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE715_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE714_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE713_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE712_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE711_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE710_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE709_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE708_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE707_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE706_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE705_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE704_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE703_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE702_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE701_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE700_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE699_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE698_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE697_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE696_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE695_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE694_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE693_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE692_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE691_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE690_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE689_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE688_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE687_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE686_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE685_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE684_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE683_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE682_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE681_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE680_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE679_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE678_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE677_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE676_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE675_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE674_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE673_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE672_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE671_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE670_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE669_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE668_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE667_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE666_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE665_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE664_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE663_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE662_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE661_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE660_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE659_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE658_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE657_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE656_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE655_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE654_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE653_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE652_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE651_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE650_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE649_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE648_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE647_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE646_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE645_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE644_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE643_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE642_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE641_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE640_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE639_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE638_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE637_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE636_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE635_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE634_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE633_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE632_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE631_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE630_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE629_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE628_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE627_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE626_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE625_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE624_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE623_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE622_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE621_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE620_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE619_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE618_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE617_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE616_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE615_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE614_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE613_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE612_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE611_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE610_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE609_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE608_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE607_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE606_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE605_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE604_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE603_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE602_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE601_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE600_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE599_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE598_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE597_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE596_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE595_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE594_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE593_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE592_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE591_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE590_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE589_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE588_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE587_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE586_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE585_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE584_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE583_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE582_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE581_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE580_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE579_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE578_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE577_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE576_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE575_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE574_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE573_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE572_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE571_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE570_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE569_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE568_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE567_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE566_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE565_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE564_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE563_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE562_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE561_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE560_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE559_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE558_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE557_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE556_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE555_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE554_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE553_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE552_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE551_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE550_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE549_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE548_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE547_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE546_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE545_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE544_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE543_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE542_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE541_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE540_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE539_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE538_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE537_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE536_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE535_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE534_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE533_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE532_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE531_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE530_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE529_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE528_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE527_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE526_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE525_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE524_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE523_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE522_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE521_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE520_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE519_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE518_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE517_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE516_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE515_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE514_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE513_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE512_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE511_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE510_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE509_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE508_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE507_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE506_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE505_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE504_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE503_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE502_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE501_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE500_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE499_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE498_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE497_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE496_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE495_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE494_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE493_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE492_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE491_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE490_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE489_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE488_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE487_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE486_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE485_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE484_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE483_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE482_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE481_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE480_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE479_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE478_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE477_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE476_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE475_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE474_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE473_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE472_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE471_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE470_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE469_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE468_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE467_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE466_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE465_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE464_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE463_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE462_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE461_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE460_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE459_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE458_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE457_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE456_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE455_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE454_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE453_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE452_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE451_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE450_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE449_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE448_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE447_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE446_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE445_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE444_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE443_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE442_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE441_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE440_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE439_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE438_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE437_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE436_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE435_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE434_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE433_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE432_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE431_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE430_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE429_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE428_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE427_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE426_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE425_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE424_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE423_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE422_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE421_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE420_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE419_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE418_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE417_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE416_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE415_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE414_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE413_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE412_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE411_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE410_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE409_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE408_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE407_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE406_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE405_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE404_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE403_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE402_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE401_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE400_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE399_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE398_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE397_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE396_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE395_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE394_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE393_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE392_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE391_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE390_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE389_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE388_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE387_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE386_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE385_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE384_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE383_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE382_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE381_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE380_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE379_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE378_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE377_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE376_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE375_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE374_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE373_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE372_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE371_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE370_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE369_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE368_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE367_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE366_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE365_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE364_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE363_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE362_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE361_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE360_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE359_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE358_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE357_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE356_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE355_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE354_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE353_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE352_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE351_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE350_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE349_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE348_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE347_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE346_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE345_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE344_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE343_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE342_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE341_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE340_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE339_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE338_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE337_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE336_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE335_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE334_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE333_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE332_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE331_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE330_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE329_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE328_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE327_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE326_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE325_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE324_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE323_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE322_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE321_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE320_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE319_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE318_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE317_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE316_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE315_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE314_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE313_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE312_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE311_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE310_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE309_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE308_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE307_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE306_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE305_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE304_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE303_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE302_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE301_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE300_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE299_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE298_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE297_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE296_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE295_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE294_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE293_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE292_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE291_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE290_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE289_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE288_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE287_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE286_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE285_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE284_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE283_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE282_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE281_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE280_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE279_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE278_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE277_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE276_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE275_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE274_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE273_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE272_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE271_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE270_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE269_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE268_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE267_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE266_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE265_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE264_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE263_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE262_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE261_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE260_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE259_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE258_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE257_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE256_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE255_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE254_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE253_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE252_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE251_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE250_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE249_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE248_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE247_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE246_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE245_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE244_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE243_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE242_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE241_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE240_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE239_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE238_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE237_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE236_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE235_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE234_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE233_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE232_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE231_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE230_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE229_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE228_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE227_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE226_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE225_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE224_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE223_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE222_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE221_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE220_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE219_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE218_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE217_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE216_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE215_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE214_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE213_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE212_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE211_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE210_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE209_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE208_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE207_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE206_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE205_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE204_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE203_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE202_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE201_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE200_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE199_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE198_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE197_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE196_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE195_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE194_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE193_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE192_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE191_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE190_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE189_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE188_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE187_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE186_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE185_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE184_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE183_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE182_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE181_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE180_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE179_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE178_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE177_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE176_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE175_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE174_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE173_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE172_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE171_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE170_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE169_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE168_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE167_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE166_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE165_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE164_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE163_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE162_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE161_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE160_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE159_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE158_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE157_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE156_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE155_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE154_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE153_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE152_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE151_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE150_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE149_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE148_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE147_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE146_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE145_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE144_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE143_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE142_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE141_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE140_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE139_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE138_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE137_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE136_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE135_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE134_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE133_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE132_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE131_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE130_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE129_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE128_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE127_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE126_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE125_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE124_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE123_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE122_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE121_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE120_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE119_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE118_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE117_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE116_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE115_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE114_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE113_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE112_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE111_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE110_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE109_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE108_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE107_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE106_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE105_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE104_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE103_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE102_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE101_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE100_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE99_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE98_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE97_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE96_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE95_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE94_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE93_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE92_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE91_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE90_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE89_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE88_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE87_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE86_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE85_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE84_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE83_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE82_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE81_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE80_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE79_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE78_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE77_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE76_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE75_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE74_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE73_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE72_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE71_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE69_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE68_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE67_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE66_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE65_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE64_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE63_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE62_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE61_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE60_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE59_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE58_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE57_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE56_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE55_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE54_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE53_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE52_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE51_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE50_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE49_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE48_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE47_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE46_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE45_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE44_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE43_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE42_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE41_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE40_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE39_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE38_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE37_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE36_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE35_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE34_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE33_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE32_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE31_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE30_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE29_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE28_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE27_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE26_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE25_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE24_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE23_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE22_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE21_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE20_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE19_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE18_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE17_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE16_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE15_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE14_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE13_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE12_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE11_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE10_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE9_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE8_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE7_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE6_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE5_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE4_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE3_WIDTH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE2_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE0_WIDTH">80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DATA_DEPTH">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_OF_PROBES">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XLNX_HW_PROBE_INFO">DEFAULT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ila_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE70_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRIGOUT_EN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_STRG_QUAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INPUT_PIPE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ADV_TRIGGER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1023_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1022_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1021_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1020_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1019_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1018_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1017_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1016_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1015_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1014_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1013_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1012_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1011_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1010_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1009_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1008_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1007_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1006_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1005_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1004_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1003_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1002_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1001_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1000_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE999_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE998_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE997_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE996_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE995_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE994_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE993_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE992_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE991_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE990_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE989_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE988_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE987_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE986_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE985_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE984_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE983_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE982_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE981_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE980_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE979_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE978_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE977_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE976_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE975_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE974_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE973_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE972_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE971_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE970_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE969_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE968_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE967_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE966_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE965_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE964_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE963_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE962_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE961_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE960_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE959_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE958_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE957_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE956_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE955_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE954_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE953_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE952_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE951_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE950_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE949_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE948_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE947_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE946_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE945_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE944_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE943_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE942_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE941_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE940_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE939_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE938_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE937_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE936_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE935_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE934_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE933_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE932_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE931_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE930_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE929_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE928_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE927_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE926_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE925_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE924_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE923_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE922_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE921_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE920_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE919_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE918_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE917_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE916_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE915_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE914_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE913_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE912_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE911_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE910_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE909_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE908_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE907_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE906_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE905_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE904_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE903_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE902_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE901_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE900_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE899_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE898_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE897_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE896_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE895_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE894_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE893_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE892_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE891_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE890_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE889_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE888_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE887_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE886_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE885_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE884_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE883_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE882_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE881_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE880_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE879_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE878_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE877_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE876_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE875_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE874_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE873_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE872_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE871_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE870_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE869_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE868_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE867_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE866_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE865_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE864_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE863_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE862_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE861_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE860_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE859_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE858_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE857_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE856_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE855_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE854_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE853_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE852_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE851_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE850_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE849_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE848_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE847_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE846_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE845_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE844_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE843_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE842_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE841_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE840_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE839_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE838_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE837_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE836_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE835_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE834_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE833_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE832_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE831_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE830_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE829_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE828_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE827_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE826_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE825_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE824_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE823_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE822_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE821_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE820_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE819_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE818_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE817_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE816_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE815_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE814_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE813_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE812_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE811_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE810_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE809_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE808_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE807_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE806_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE805_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE804_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE803_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE802_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE801_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE800_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE799_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE798_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE797_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE796_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE795_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE794_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE793_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE792_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE791_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE790_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE789_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE788_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE787_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE786_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE785_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE784_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE783_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE782_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE781_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE780_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE779_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE778_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE777_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE776_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE775_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE774_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE773_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE772_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE771_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE770_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE769_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE768_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE767_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE766_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE765_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE764_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE763_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE762_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE761_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE760_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE759_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE758_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE757_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE756_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE755_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE754_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE753_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE752_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE751_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE750_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE749_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE748_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE747_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE746_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE745_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE744_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE743_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE742_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE741_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE740_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE739_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE738_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE737_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE736_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE735_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE734_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE733_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE732_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE731_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE730_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE729_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE728_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE727_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE726_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE725_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE724_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE723_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE722_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE721_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE720_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE719_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE718_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE717_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE716_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE715_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE714_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE713_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE712_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE711_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE710_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE709_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE708_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE707_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE706_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE705_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE704_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE703_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE702_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE701_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE700_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE699_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE698_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE697_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE696_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE695_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE694_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE693_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE692_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE691_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE690_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE689_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE688_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE687_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE686_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE685_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE684_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE683_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE682_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE681_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE680_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE679_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE678_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE677_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE676_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE675_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE674_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE673_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE672_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE671_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE670_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE669_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE668_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE667_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE666_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE665_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE664_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE663_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE662_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE661_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE660_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE659_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE658_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE657_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE656_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE655_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE654_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE653_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE652_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE651_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE650_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE649_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE648_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE647_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE646_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE645_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE644_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE643_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE642_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE641_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE640_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE639_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE638_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE637_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE636_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE635_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE634_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE633_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE632_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE631_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE630_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE629_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE628_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE627_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE626_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE625_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE624_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE623_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE622_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE621_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE620_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE619_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE618_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE617_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE616_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE615_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE614_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE613_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE612_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE611_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE610_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE609_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE608_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE607_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE606_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE605_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE604_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE603_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE602_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE601_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE600_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE599_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE598_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE597_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE596_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE595_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE594_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE593_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE592_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE591_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE590_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE589_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE588_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE587_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE586_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE585_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE584_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE583_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE582_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE581_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE580_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE579_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE578_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE577_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE576_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE575_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE574_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE573_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE572_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE571_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE570_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE569_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE568_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE567_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE566_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE565_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE564_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE563_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE562_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE561_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE560_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE559_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE558_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE557_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE556_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE555_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE554_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE553_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE552_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE551_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE550_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE549_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE548_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE547_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE546_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE545_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE544_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE543_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE542_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE541_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE540_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE539_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE538_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE537_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE536_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE535_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE534_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE533_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE532_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE531_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE530_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE529_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE528_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE527_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE526_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE525_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE524_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE523_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE522_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE521_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE520_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE519_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE518_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE517_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE516_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE515_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE514_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE513_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE512_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE511_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE510_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE509_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE508_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE507_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE506_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE505_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE504_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE503_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE502_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE501_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE500_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE499_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE498_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE497_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE496_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE495_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE494_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE493_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE492_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE491_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE490_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE489_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE488_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE487_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE486_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE485_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE484_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE483_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE482_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE481_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE480_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE479_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE478_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE477_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE476_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE475_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE474_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE473_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE472_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE471_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE470_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE469_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE468_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE467_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE466_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE465_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE464_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE463_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE462_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE461_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE460_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE459_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE458_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE457_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE456_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE455_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE454_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE453_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE452_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE451_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE450_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE449_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE448_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE447_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE446_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE445_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE444_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE443_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE442_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE441_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE440_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE439_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE438_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE437_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE436_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE435_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE434_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE433_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE432_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE431_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE430_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE429_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE428_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE427_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE426_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE425_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE424_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE423_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE422_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE421_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE420_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE419_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE418_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE417_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE416_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE415_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE414_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE413_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE412_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE411_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE410_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE409_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE408_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE407_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE406_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE405_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE404_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE403_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE402_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE401_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE400_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE399_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE398_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE397_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE396_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE395_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE394_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE393_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE392_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE391_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE390_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE389_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE388_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE387_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE386_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE385_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE384_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE383_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE382_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE381_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE380_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE379_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE378_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE377_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE376_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE375_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE374_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE373_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE372_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE371_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE370_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE369_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE368_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE367_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE366_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE365_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE364_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE363_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE362_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE361_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE360_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE359_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE358_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE357_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE356_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE355_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE354_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE353_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE352_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE351_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE350_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE349_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE348_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE347_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE346_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE345_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE344_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE343_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE342_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE341_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE340_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE339_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE338_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE337_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE336_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE335_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE334_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE333_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE332_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE331_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE330_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE329_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE328_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE327_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE326_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE325_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE324_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE323_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE322_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE321_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE320_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE319_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE318_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE317_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE316_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE315_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE314_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE313_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE312_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE311_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE310_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE309_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE308_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE307_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE306_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE305_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE304_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE303_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE302_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE301_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE300_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE299_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE298_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE297_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE296_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE295_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE294_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE293_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE292_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE291_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE290_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE289_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE288_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE287_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE286_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE285_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE284_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE283_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE282_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE281_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE280_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE279_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE278_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE277_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE276_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE275_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE274_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE273_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE272_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE271_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE270_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE269_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE268_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE267_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE266_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE265_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE264_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE263_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE262_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE261_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE260_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE259_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE258_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE257_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE256_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE255_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE254_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE253_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE252_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE251_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE250_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE249_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE248_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE247_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE246_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE245_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE244_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE243_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE242_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE241_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE240_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE239_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE238_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE237_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE236_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE235_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE234_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE233_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE232_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE231_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE230_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE229_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE228_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE227_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE226_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE225_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE224_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE223_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE222_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE221_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE220_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE219_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE218_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE217_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE216_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE215_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE214_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE213_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE212_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE211_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE210_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE209_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE208_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE207_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE206_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE205_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE204_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE203_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE202_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE201_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE200_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE199_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE198_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE197_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE196_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE195_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE194_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE193_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE192_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE191_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE190_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE189_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE188_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE187_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE186_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE185_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE184_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE183_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE182_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE181_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE180_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE179_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE178_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE177_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE176_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE175_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE174_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE173_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE172_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE171_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE170_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE169_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE168_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE167_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE166_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE165_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE164_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE163_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE162_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE161_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE160_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE159_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE158_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE157_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE156_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE155_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE154_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE153_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE152_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE151_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE150_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE149_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE148_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE147_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE146_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE145_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE144_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE143_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE142_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE141_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE140_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE139_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE138_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE137_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE136_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE135_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE134_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE133_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE132_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE131_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE130_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE129_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE128_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE127_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE126_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE125_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE124_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE123_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE122_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE121_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE120_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE119_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE118_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE117_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE116_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE115_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE114_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE113_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE112_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE111_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE110_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE109_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE108_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE107_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE106_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE105_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE104_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE103_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE102_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE101_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE100_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE99_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE98_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE97_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE96_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE95_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE94_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE93_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE92_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE91_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE90_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE89_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE88_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE87_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE86_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE85_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE84_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE83_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE82_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE81_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE80_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE79_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE78_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE77_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE76_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE75_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE74_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE73_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE72_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE71_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE70_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE69_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE68_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE67_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE66_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE65_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE64_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE63_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE62_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE61_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE60_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE59_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE58_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE57_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE56_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE55_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE54_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE53_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE52_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE51_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE50_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE49_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE48_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE47_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE46_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE45_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE44_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE43_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE42_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE41_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE40_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE39_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE38_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE37_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE36_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE35_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE34_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE33_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE32_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE31_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE30_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE29_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE28_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE27_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE26_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE25_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE24_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE23_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE22_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE21_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE20_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE19_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE18_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE17_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE16_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE15_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE14_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE13_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE12_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE11_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE10_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE9_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE8_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE7_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE6_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE5_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE4_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE3_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE2_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE0_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRIGIN_EN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALL_PROBE_SAME_MU">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALL_PROBE_SAME_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XLNX_HW_PROBE_INFO">NUM_OF_PROBES=7,DATA_DEPTH=2048,PROBE0_WIDTH=80,PROBE0_MU_CNT=1,PROBE1_WIDTH=8,PROBE1_MU_CNT=1,PROBE2_WIDTH=1,PROBE2_MU_CNT=1,PROBE3_WIDTH=2,PROBE3_MU_CNT=1,PROBE4_WIDTH=8,PROBE4_MU_CNT=1,PROBE5_WIDTH=1,PROBE5_MU_CNT=1,PROBE6_WIDTH=1,PROBE6_MU_CNT=1,PROBE7_WIDTH=1,PROBE7_MU_CNT=1,PROBE8_WIDTH=1,PROBE8_MU_CNT=1,PROBE9_WIDTH=1,PROBE9_MU_CNT=1,PROBE10_WIDTH=1,PROBE10_MU_CNT=1,PROBE11_WIDTH=1,PROBE11_MU_CNT=1,PROBE12_WIDTH=1,PROBE12_MU_CNT=1,PROBE13_WIDTH=1,PROBE13_MU_CNT=1,PROBE14_WIDTH=1,PROBE14_MU_CNT=1,PROBE15_WIDTH=1,PROBE15_MU_CNT=1,PROBE16_WIDTH=1,PROBE16_MU_CNT=1,PROBE17_WIDTH=1,PROBE17_MU_CNT=1,PROBE18_WIDTH=1,PROBE18_MU_CNT=1,PROBE19_WIDTH=1,PROBE19_MU_CNT=1,PROBE20_WIDTH=1,PROBE20_MU_CNT=1,PROBE21_WIDTH=1,PROBE21_MU_CNT=1,PROBE22_WIDTH=1,PROBE22_MU_CNT=1,PROBE23_WIDTH=1,PROBE23_MU_CNT=1,PROBE24_WIDTH=1,PROBE24_MU_CNT=1,PROBE25_WIDTH=1,PROBE25_MU_CNT=1,PROBE26_WIDTH=1,PROBE26_MU_CNT=1,PROBE27_WIDTH=1,PROBE27_MU_CNT=1,PROBE28_WIDTH=1,PROBE28_MU_CNT=1,PROBE29_WIDTH=1,PROBE29_MU_CNT=1,PROBE30_WIDTH=1,PROBE30_MU_CNT=1,PROBE31_WIDTH=1,PROBE31_MU_CNT=1,PROBE32_WIDTH=1,PROBE32_MU_CNT=1,PROBE33_WIDTH=1,PROBE33_MU_CNT=1,PROBE34_WIDTH=1,PROBE34_MU_CNT=1,PROBE35_WIDTH=1,PROBE35_MU_CNT=1,PROBE36_WIDTH=1,PROBE36_MU_CNT=1,PROBE37_WIDTH=1,PROBE37_MU_CNT=1,PROBE38_WIDTH=1,PROBE38_MU_CNT=1,PROBE39_WIDTH=1,PROBE39_MU_CNT=1,PROBE40_WIDTH=1,PROBE40_MU_CNT=1,PROBE41_WIDTH=1,PROBE41_MU_CNT=1,PROBE42_WIDTH=1,PROBE42_MU_CNT=1,PROBE43_WIDTH=1,PROBE43_MU_CNT=1,PROBE44_WIDTH=1,PROBE44_MU_CNT=1,PROBE45_WIDTH=1,PROBE45_MU_CNT=1,PROBE46_WIDTH=1,PROBE46_MU_CNT=1,PROBE47_WIDTH=1,PROBE47_MU_CNT=1,PROBE48_WIDTH=1,PROBE48_MU_CNT=1,PROBE49_WIDTH=1,PROBE49_MU_CNT=1,PROBE50_WIDTH=1,PROBE50_MU_CNT=1,PROBE51_WIDTH=1,PROBE51_MU_CNT=1,PROBE52_WIDTH=1,PROBE52_MU_CNT=1,PROBE53_WIDTH=1,PROBE53_MU_CNT=1,PROBE54_WIDTH=1,PROBE54_MU_CNT=1,PROBE55_WIDTH=1,PROBE55_MU_CNT=1,PROBE56_WIDTH=1,PROBE56_MU_CNT=1,PROBE57_WIDTH=1,PROBE57_MU_CNT=1,PROBE58_WIDTH=1,PROBE58_MU_CNT=1,PROBE59_WIDTH=1,PROBE59_MU_CNT=1,PROBE60_WIDTH=1,PROBE60_MU_CNT=1,PROBE61_WIDTH=1,PROBE61_MU_CNT=1,PROBE62_WIDTH=1,PROBE62_MU_CNT=1,PROBE63_WIDTH=1,PROBE63_MU_CNT=1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OF_PROBES">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_DEPTH">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MAJOR_VERSION">2013</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MINOR_VERSION">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIGOUT_EN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIGIN_EN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADV_TRIGGER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_PIPE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_STRG_QUAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USER_REPO_PATHS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2014.3.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/xci/ila_1.xci b/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/xci/ila_1.xci
new file mode 100644
index 0000000..6ab26c7
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/xci/ila_1.xci
@@ -0,0 +1,2102 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>ila_1</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="ila" spirit:version="5.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1023_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1022_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1021_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1020_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1019_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1018_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1017_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1016_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1015_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1014_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1013_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1012_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1011_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1010_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1009_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1008_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1007_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1006_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1005_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1004_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1003_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1002_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1001_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1000_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE999_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE998_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE997_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE996_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE995_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE994_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE993_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE992_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE991_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE990_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE989_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE988_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE987_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE986_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE985_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE984_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE983_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE982_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE981_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE980_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE979_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE978_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE977_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE976_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE975_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE974_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE973_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE972_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE971_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE970_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE969_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE968_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE967_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE966_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE965_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE964_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE963_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE962_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE961_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE960_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE959_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE958_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE957_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE956_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE955_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE954_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE953_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE952_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE951_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE950_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE949_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE948_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE947_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE946_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE945_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE944_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE943_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE942_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE941_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE940_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE939_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE938_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE937_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE936_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE935_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE934_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE933_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE932_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE931_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE930_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE929_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE928_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE927_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE926_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE925_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE924_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE923_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE922_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE921_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE920_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE919_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE918_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE917_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE916_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE915_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE914_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE913_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE912_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE911_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE910_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE909_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE908_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE907_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE906_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE905_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE904_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE903_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE902_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE901_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE900_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE899_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE898_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE897_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE896_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE895_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE894_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE893_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE892_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE891_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE890_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE889_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE888_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE887_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE886_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE885_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE884_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE883_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE882_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE881_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE880_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE879_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE878_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE877_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE876_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE875_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE874_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE873_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE872_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE871_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE870_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE869_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE868_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE867_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE866_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE865_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE864_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE863_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE862_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE861_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE860_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE859_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE858_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE857_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE856_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE855_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE854_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE853_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE852_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE851_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE850_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE849_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE848_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE847_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE846_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE845_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE844_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE843_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE842_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE841_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE840_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE839_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE838_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE837_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE836_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE835_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE834_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE833_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE832_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE831_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE830_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE829_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE828_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE827_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE826_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE825_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE824_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE823_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE822_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE821_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE820_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE819_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE818_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE817_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE816_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE815_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE814_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE813_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE812_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE811_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE810_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE809_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE808_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE807_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE806_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE805_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE804_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE803_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE802_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE801_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE800_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE799_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE798_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE797_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE796_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE795_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE794_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE793_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE792_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE791_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE790_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE789_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE788_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE787_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE786_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE785_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE784_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE783_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE782_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE781_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE780_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE779_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE778_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE777_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE776_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE775_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE774_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE773_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE772_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE771_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE770_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE769_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE768_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE767_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE766_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE765_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE764_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE763_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE762_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE761_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE760_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE759_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE758_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE757_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE756_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE755_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE754_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE753_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE752_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE751_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE750_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE749_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE748_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE747_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE746_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE745_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE744_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE743_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE742_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE741_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE740_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE739_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE738_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE737_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE736_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE735_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE734_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE733_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE732_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE731_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE730_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE729_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE728_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE727_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE726_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE725_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE724_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE723_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE722_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE721_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE720_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE719_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE718_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE717_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE716_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE715_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE714_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE713_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE712_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE711_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE710_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE709_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE708_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE707_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE706_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE705_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE704_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE703_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE702_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE701_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE700_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE699_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE698_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE697_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE696_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE695_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE694_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE693_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE692_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE691_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE690_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE689_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE688_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE687_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE686_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE685_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE684_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE683_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE682_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE681_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE680_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE679_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE678_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE677_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE676_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE675_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE674_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE673_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE672_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE671_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE670_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE669_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE668_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE667_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE666_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE665_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE664_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE663_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE662_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE661_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE660_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE659_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE658_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE657_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE656_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE655_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE654_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE653_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE652_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE651_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE650_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE649_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE648_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE647_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE646_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE645_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE644_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE643_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE642_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE641_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE640_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE639_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE638_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE637_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE636_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE635_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE634_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE633_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE632_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE631_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE630_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE629_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE628_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE627_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE626_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE625_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE624_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE623_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE622_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE621_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE620_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE619_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE618_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE617_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE616_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE615_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE614_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE613_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE612_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE611_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE610_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE609_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE608_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE607_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE606_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE605_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE604_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE603_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE602_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE601_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE600_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE599_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE598_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE597_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE596_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE595_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE594_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE593_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE592_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE591_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE590_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE589_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE588_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE587_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE586_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE585_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE584_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE583_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE582_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE581_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE580_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE579_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE578_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE577_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE576_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE575_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE574_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE573_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE572_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE571_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE570_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE569_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE568_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE567_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE566_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE565_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE564_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE563_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE562_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE561_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE560_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE559_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE558_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE557_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE556_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE555_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE554_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE553_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE552_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE551_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE550_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE549_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE548_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE547_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE546_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE545_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE544_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE543_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE542_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE541_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE540_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE539_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE538_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE537_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE536_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE535_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE534_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE533_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE532_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE531_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE530_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE529_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE528_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE527_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE526_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE525_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE524_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE523_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE522_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE521_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE520_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE519_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE518_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE517_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE516_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE515_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE514_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE513_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE512_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE511_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE510_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE509_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE508_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE507_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE506_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE505_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE504_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE503_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE502_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE501_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE500_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE499_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE498_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE497_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE496_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE495_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE494_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE493_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE492_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE491_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE490_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE489_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE488_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE487_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE486_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE485_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE484_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE483_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE482_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE481_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE480_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE479_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE478_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE477_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE476_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE475_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE474_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE473_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE472_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE471_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE470_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE469_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE468_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE467_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE466_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE465_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE464_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE463_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE462_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE461_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE460_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE459_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE458_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE457_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE456_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE455_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE454_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE453_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE452_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE451_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE450_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE449_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE448_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE447_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE446_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE445_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE444_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE443_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE442_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE441_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE440_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE439_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE438_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE437_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE436_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE435_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE434_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE433_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE432_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE431_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE430_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE429_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE428_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE427_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE426_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE425_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE424_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE423_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE422_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE421_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE420_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE419_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE418_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE417_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE416_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE415_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE414_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE413_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE412_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE411_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE410_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE409_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE408_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE407_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE406_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE405_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE404_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE403_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE402_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE401_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE400_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE399_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE398_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE397_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE396_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE395_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE394_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE393_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE392_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE391_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE390_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE389_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE388_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE387_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE386_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE385_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE384_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE383_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE382_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE381_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE380_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE379_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE378_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE377_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE376_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE375_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE374_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE373_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE372_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE371_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE370_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE369_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE368_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE367_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE366_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE365_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE364_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE363_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE362_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE361_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE360_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE359_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE358_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE357_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE356_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE355_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE354_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE353_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE352_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE351_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE350_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE349_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE348_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE347_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE346_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE345_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE344_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE343_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE342_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE341_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE340_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE339_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE338_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE337_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE336_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE335_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE334_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE333_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE332_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE331_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE330_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE329_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE328_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE327_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE326_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE325_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE324_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE323_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE322_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE321_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE320_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE319_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE318_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE317_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE316_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE315_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE314_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE313_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE312_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE311_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE310_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE309_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE308_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE307_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE306_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE305_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE304_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE303_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE302_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE301_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE300_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE299_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE298_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE297_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE296_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE295_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE294_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE293_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE292_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE291_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE290_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE289_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE288_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE287_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE286_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE285_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE284_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE283_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE282_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE281_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE280_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE279_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE278_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE277_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE276_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE275_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE274_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE273_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE272_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE271_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE270_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE269_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE268_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE267_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE266_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE265_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE264_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE263_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE262_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE261_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE260_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE259_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE258_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE257_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE256_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE255_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE254_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE253_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE252_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE251_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE250_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE249_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE248_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE247_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE246_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE245_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE244_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE243_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE242_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE241_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE240_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE239_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE238_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE237_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE236_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE235_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE234_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE233_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE232_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE231_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE230_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE229_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE228_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE227_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE226_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE225_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE224_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE223_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE222_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE221_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE220_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE219_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE218_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE217_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE216_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE215_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE214_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE213_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE212_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE211_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE210_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE209_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE208_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE207_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE206_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE205_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE204_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE203_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE202_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE201_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE200_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE199_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE198_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE197_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE196_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE195_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE194_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE193_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE192_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE191_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE190_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE189_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE188_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE187_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE186_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE185_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE184_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE183_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE182_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE181_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE180_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE179_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE178_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE177_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE176_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE175_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE174_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE173_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE172_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE171_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE170_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE169_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE168_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE167_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE166_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE165_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE164_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE163_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE162_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE161_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE160_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE159_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE158_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE157_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE156_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE155_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE154_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE153_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE152_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE151_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE150_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE149_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE148_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE147_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE146_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE145_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE144_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE143_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE142_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE141_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE140_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE139_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE138_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE137_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE136_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE135_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE134_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE133_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE132_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE131_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE130_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE129_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE128_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE127_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE126_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE125_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE124_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE123_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE122_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE121_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE120_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE119_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE118_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE117_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE116_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE115_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE114_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE113_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE112_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE111_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE110_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE109_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE108_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE107_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE106_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE105_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE104_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE103_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE102_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE101_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE100_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE99_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE98_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE97_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE96_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE95_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE94_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE93_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE92_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE91_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE90_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE89_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE88_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE87_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE86_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE85_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE84_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE83_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE82_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE81_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE80_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE79_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE78_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE77_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE76_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE75_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE74_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE73_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE72_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE71_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE69_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE68_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE67_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE66_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE65_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE64_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE63_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE62_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE61_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE60_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE59_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE58_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE57_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE56_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE55_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE54_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE53_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE52_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE51_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE50_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE49_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE48_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE47_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE46_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE45_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE44_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE43_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE42_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE41_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE40_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE39_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE38_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE37_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE36_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE35_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE34_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE33_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE32_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE31_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE30_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE29_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE28_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE27_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE26_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE25_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE24_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE23_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE22_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE21_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE20_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE19_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE18_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE17_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE16_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE15_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE14_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE13_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE12_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE11_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE10_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE9_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE8_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE7_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE6_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE5_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE4_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE3_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE2_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE0_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_DATA_DEPTH">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_OF_PROBES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_XLNX_HW_PROBE_INFO">DEFAULT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">ila_1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE70_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRIGOUT_EN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_STRG_QUAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_INPUT_PIPE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_ADV_TRIGGER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1023_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1022_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1021_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1020_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1019_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1018_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1017_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1016_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1015_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1014_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1013_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1012_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1011_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1010_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1009_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1008_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1007_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1006_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1005_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1004_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1003_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1002_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1001_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1000_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE999_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE998_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE997_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE996_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE995_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE994_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE993_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE992_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE991_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE990_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE989_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE988_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE987_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE986_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE985_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE984_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE983_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE982_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE981_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE980_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE979_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE978_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE977_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE976_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE975_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE974_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE973_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE972_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE971_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE970_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE969_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE968_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE967_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE966_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE965_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE964_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE963_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE962_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE961_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE960_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE959_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE958_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE957_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE956_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE955_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE954_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE953_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE952_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE951_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE950_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE949_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE948_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE947_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE946_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE945_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE944_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE943_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE942_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE941_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE940_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE939_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE938_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE937_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE936_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE935_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE934_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE933_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE932_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE931_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE930_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE929_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE928_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE927_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE926_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE925_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE924_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE923_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE922_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE921_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE920_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE919_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE918_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE917_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE916_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE915_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE914_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE913_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE912_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE911_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE910_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE909_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE908_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE907_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE906_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE905_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE904_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE903_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE902_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE901_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE900_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE899_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE898_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE897_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE896_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE895_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE894_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE893_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE892_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE891_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE890_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE889_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE888_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE887_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE886_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE885_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE884_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE883_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE882_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE881_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE880_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE879_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE878_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE877_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE876_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE875_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE874_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE873_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE872_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE871_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE870_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE869_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE868_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE867_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE866_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE865_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE864_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE863_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE862_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE861_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE860_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE859_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE858_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE857_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE856_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE855_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE854_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE853_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE852_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE851_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE850_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE849_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE848_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE847_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE846_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE845_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE844_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE843_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE842_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE841_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE840_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE839_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE838_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE837_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE836_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE835_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE834_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE833_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE832_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE831_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE830_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE829_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE828_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE827_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE826_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE825_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE824_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE823_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE822_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE821_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE820_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE819_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE818_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE817_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE816_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE815_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE814_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE813_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE812_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE811_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE810_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE809_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE808_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE807_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE806_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE805_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE804_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE803_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE802_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE801_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE800_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE799_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE798_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE797_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE796_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE795_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE794_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE793_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE792_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE791_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE790_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE789_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE788_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE787_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE786_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE785_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE784_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE783_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE782_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE781_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE780_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE779_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE778_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE777_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE776_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE775_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE774_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE773_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE772_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE771_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE770_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE769_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE768_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE767_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE766_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE765_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE764_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE763_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE762_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE761_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE760_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE759_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE758_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE757_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE756_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE755_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE754_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE753_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE752_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE751_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE750_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE749_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE748_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE747_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE746_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE745_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE744_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE743_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE742_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE741_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE740_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE739_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE738_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE737_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE736_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE735_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE734_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE733_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE732_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE731_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE730_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE729_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE728_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE727_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE726_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE725_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE724_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE723_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE722_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE721_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE720_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE719_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE718_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE717_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE716_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE715_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE714_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE713_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE712_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE711_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE710_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE709_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE708_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE707_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE706_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE705_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE704_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE703_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE702_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE701_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE700_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE699_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE698_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE697_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE696_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE695_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE694_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE693_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE692_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE691_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE690_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE689_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE688_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE687_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE686_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE685_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE684_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE683_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE682_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE681_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE680_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE679_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE678_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE677_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE676_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE675_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE674_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE673_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE672_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE671_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE670_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE669_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE668_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE667_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE666_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE665_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE664_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE663_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE662_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE661_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE660_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE659_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE658_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE657_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE656_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE655_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE654_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE653_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE652_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE651_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE650_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE649_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE648_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE647_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE646_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE645_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE644_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE643_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE642_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE641_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE640_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE639_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE638_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE637_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE636_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE635_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE634_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE633_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE632_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE631_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE630_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE629_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE628_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE627_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE626_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE625_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE624_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE623_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE622_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE621_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE620_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE619_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE618_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE617_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE616_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE615_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE614_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE613_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE612_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE611_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE610_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE609_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE608_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE607_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE606_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE605_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE604_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE603_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE602_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE601_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE600_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE599_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE598_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE597_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE596_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE595_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE594_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE593_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE592_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE591_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE590_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE589_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE588_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE587_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE586_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE585_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE584_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE583_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE582_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE581_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE580_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE579_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE578_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE577_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE576_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE575_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE574_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE573_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE572_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE571_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE570_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE569_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE568_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE567_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE566_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE565_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE564_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE563_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE562_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE561_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE560_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE559_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE558_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE557_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE556_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE555_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE554_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE553_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE552_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE551_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE550_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE549_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE548_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE547_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE546_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE545_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE544_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE543_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE542_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE541_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE540_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE539_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE538_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE537_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE536_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE535_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE534_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE533_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE532_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE531_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE530_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE529_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE528_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE527_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE526_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE525_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE524_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE523_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE522_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE521_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE520_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE519_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE518_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE517_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE516_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE515_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE514_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE513_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE512_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE511_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE510_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE509_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE508_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE507_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE506_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE505_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE504_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE503_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE502_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE501_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE500_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE499_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE498_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE497_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE496_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE495_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE494_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE493_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE492_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE491_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE490_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE489_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE488_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE487_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE486_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE485_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE484_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE483_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE482_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE481_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE480_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE479_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE478_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE477_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE476_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE475_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE474_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE473_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE472_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE471_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE470_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE469_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE468_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE467_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE466_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE465_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE464_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE463_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE462_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE461_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE460_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE459_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE458_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE457_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE456_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE455_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE454_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE453_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE452_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE451_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE450_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE449_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE448_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE447_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE446_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE445_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE444_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE443_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE442_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE441_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE440_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE439_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE438_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE437_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE436_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE435_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE434_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE433_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE432_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE431_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE430_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE429_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE428_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE427_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE426_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE425_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE424_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE423_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE422_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE421_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE420_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE419_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE418_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE417_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE416_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE415_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE414_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE413_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE412_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE411_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE410_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE409_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE408_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE407_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE406_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE405_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE404_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE403_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE402_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE401_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE400_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE399_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE398_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE397_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE396_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE395_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE394_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE393_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE392_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE391_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE390_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE389_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE388_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE387_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE386_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE385_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE384_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE383_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE382_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE381_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE380_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE379_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE378_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE377_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE376_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE375_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE374_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE373_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE372_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE371_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE370_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE369_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE368_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE367_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE366_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE365_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE364_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE363_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE362_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE361_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE360_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE359_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE358_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE357_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE356_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE355_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE354_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE353_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE352_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE351_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE350_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE349_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE348_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE347_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE346_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE345_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE344_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE343_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE342_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE341_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE340_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE339_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE338_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE337_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE336_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE335_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE334_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE333_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE332_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE331_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE330_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE329_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE328_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE327_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE326_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE325_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE324_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE323_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE322_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE321_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE320_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE319_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE318_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE317_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE316_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE315_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE314_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE313_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE312_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE311_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE310_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE309_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE308_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE307_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE306_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE305_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE304_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE303_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE302_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE301_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE300_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE299_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE298_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE297_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE296_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE295_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE294_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE293_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE292_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE291_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE290_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE289_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE288_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE287_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE286_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE285_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE284_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE283_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE282_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE281_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE280_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE279_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE278_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE277_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE276_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE275_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE274_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE273_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE272_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE271_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE270_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE269_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE268_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE267_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE266_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE265_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE264_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE263_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE262_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE261_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE260_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE259_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE258_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE257_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE256_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE255_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE254_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE253_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE252_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE251_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE250_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE249_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE248_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE247_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE246_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE245_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE244_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE243_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE242_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE241_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE240_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE239_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE238_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE237_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE236_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE235_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE234_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE233_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE232_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE231_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE230_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE229_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE228_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE227_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE226_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE225_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE224_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE223_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE222_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE221_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE220_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE219_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE218_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE217_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE216_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE215_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE214_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE213_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE212_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE211_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE210_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE209_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE208_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE207_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE206_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE205_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE204_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE203_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE202_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE201_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE200_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE199_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE198_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE197_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE196_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE195_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE194_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE193_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE192_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE191_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE190_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE189_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE188_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE187_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE186_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE185_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE184_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE183_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE182_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE181_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE180_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE179_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE178_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE177_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE176_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE175_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE174_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE173_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE172_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE171_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE170_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE169_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE168_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE167_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE166_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE165_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE164_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE163_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE162_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE161_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE160_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE159_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE158_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE157_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE156_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE155_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE154_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE153_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE152_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE151_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE150_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE149_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE148_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE147_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE146_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE145_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE144_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE143_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE142_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE141_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE140_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE139_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE138_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE137_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE136_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE135_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE134_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE133_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE132_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE131_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE130_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE129_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE128_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE127_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE126_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE125_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE124_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE123_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE122_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE121_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE120_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE119_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE118_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE117_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE116_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE115_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE114_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE113_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE112_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE111_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE110_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE109_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE108_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE107_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE106_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE105_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE104_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE103_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE102_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE101_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE100_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE99_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE98_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE97_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE96_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE95_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE94_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE93_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE92_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE91_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE90_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE89_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE88_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE87_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE86_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE85_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE84_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE83_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE82_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE81_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE80_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE79_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE78_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE77_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE76_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE75_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE74_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE73_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE72_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE71_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE70_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE69_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE68_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE67_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE66_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE65_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE64_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE63_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE62_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE61_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE60_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE59_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE58_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE57_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE56_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE55_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE54_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE53_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE52_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE51_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE50_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE49_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE48_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE47_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE46_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE45_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE44_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE43_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE42_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE41_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE40_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE39_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE38_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE37_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE36_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE35_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE34_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE33_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE32_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE31_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE30_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE29_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE28_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE27_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE26_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE25_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE24_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE23_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE22_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE21_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE20_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE19_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE18_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE17_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE16_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE15_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE14_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE13_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE12_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE11_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE10_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE9_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE8_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE7_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE6_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE5_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE4_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE3_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE2_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE1_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE0_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_TRIGIN_EN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALL_PROBE_SAME_MU">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALL_PROBE_SAME_MU_CNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XLNX_HW_PROBE_INFO">NUM_OF_PROBES=2,DATA_DEPTH=2048,PROBE0_WIDTH=1,PROBE0_MU_CNT=1,PROBE1_WIDTH=1,PROBE1_MU_CNT=1,PROBE2_WIDTH=1,PROBE2_MU_CNT=1,PROBE3_WIDTH=1,PROBE3_MU_CNT=1,PROBE4_WIDTH=1,PROBE4_MU_CNT=1,PROBE5_WIDTH=1,PROBE5_MU_CNT=1,PROBE6_WIDTH=1,PROBE6_MU_CNT=1,PROBE7_WIDTH=1,PROBE7_MU_CNT=1,PROBE8_WIDTH=1,PROBE8_MU_CNT=1,PROBE9_WIDTH=1,PROBE9_MU_CNT=1,PROBE10_WIDTH=1,PROBE10_MU_CNT=1,PROBE11_WIDTH=1,PROBE11_MU_CNT=1,PROBE12_WIDTH=1,PROBE12_MU_CNT=1,PROBE13_WIDTH=1,PROBE13_MU_CNT=1,PROBE14_WIDTH=1,PROBE14_MU_CNT=1,PROBE15_WIDTH=1,PROBE15_MU_CNT=1,PROBE16_WIDTH=1,PROBE16_MU_CNT=1,PROBE17_WIDTH=1,PROBE17_MU_CNT=1,PROBE18_WIDTH=1,PROBE18_MU_CNT=1,PROBE19_WIDTH=1,PROBE19_MU_CNT=1,PROBE20_WIDTH=1,PROBE20_MU_CNT=1,PROBE21_WIDTH=1,PROBE21_MU_CNT=1,PROBE22_WIDTH=1,PROBE22_MU_CNT=1,PROBE23_WIDTH=1,PROBE23_MU_CNT=1,PROBE24_WIDTH=1,PROBE24_MU_CNT=1,PROBE25_WIDTH=1,PROBE25_MU_CNT=1,PROBE26_WIDTH=1,PROBE26_MU_CNT=1,PROBE27_WIDTH=1,PROBE27_MU_CNT=1,PROBE28_WIDTH=1,PROBE28_MU_CNT=1,PROBE29_WIDTH=1,PROBE29_MU_CNT=1,PROBE30_WIDTH=1,PROBE30_MU_CNT=1,PROBE31_WIDTH=1,PROBE31_MU_CNT=1,PROBE32_WIDTH=1,PROBE32_MU_CNT=1,PROBE33_WIDTH=1,PROBE33_MU_CNT=1,PROBE34_WIDTH=1,PROBE34_MU_CNT=1,PROBE35_WIDTH=1,PROBE35_MU_CNT=1,PROBE36_WIDTH=1,PROBE36_MU_CNT=1,PROBE37_WIDTH=1,PROBE37_MU_CNT=1,PROBE38_WIDTH=1,PROBE38_MU_CNT=1,PROBE39_WIDTH=1,PROBE39_MU_CNT=1,PROBE40_WIDTH=1,PROBE40_MU_CNT=1,PROBE41_WIDTH=1,PROBE41_MU_CNT=1,PROBE42_WIDTH=1,PROBE42_MU_CNT=1,PROBE43_WIDTH=1,PROBE43_MU_CNT=1,PROBE44_WIDTH=1,PROBE44_MU_CNT=1,PROBE45_WIDTH=1,PROBE45_MU_CNT=1,PROBE46_WIDTH=1,PROBE46_MU_CNT=1,PROBE47_WIDTH=1,PROBE47_MU_CNT=1,PROBE48_WIDTH=1,PROBE48_MU_CNT=1,PROBE49_WIDTH=1,PROBE49_MU_CNT=1,PROBE50_WIDTH=1,PROBE50_MU_CNT=1,PROBE51_WIDTH=1,PROBE51_MU_CNT=1,PROBE52_WIDTH=1,PROBE52_MU_CNT=1,PROBE53_WIDTH=1,PROBE53_MU_CNT=1,PROBE54_WIDTH=1,PROBE54_MU_CNT=1,PROBE55_WIDTH=1,PROBE55_MU_CNT=1,PROBE56_WIDTH=1,PROBE56_MU_CNT=1,PROBE57_WIDTH=1,PROBE57_MU_CNT=1,PROBE58_WIDTH=1,PROBE58_MU_CNT=1,PROBE59_WIDTH=1,PROBE59_MU_CNT=1,PROBE60_WIDTH=1,PROBE60_MU_CNT=1,PROBE61_WIDTH=1,PROBE61_MU_CNT=1,PROBE62_WIDTH=1,PROBE62_MU_CNT=1,PROBE63_WIDTH=1,PROBE63_MU_CNT=1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OF_PROBES">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_DEPTH">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MAJOR_VERSION">2013</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MINOR_VERSION">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIGOUT_EN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TRIGIN_EN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADV_TRIGGER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_PIPE_STAGES">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_STRG_QUAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USER_REPO_PATHS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2014.3.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/xci/vio_0.xci b/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/xci/vio_0.xci
new file mode 100644
index 0000000..81cb173
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_quadSODA/xci/vio_0.xci
@@ -0,0 +1,826 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>vio_0</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="vio" spirit:version="3.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT255_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT254_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT253_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT252_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT251_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT250_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT249_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT248_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT247_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT246_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT245_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT244_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT243_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT242_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT241_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT240_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT239_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT238_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT237_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT236_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT235_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT234_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT233_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT232_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT231_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT230_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT229_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT228_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT227_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT226_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT225_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT224_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT223_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT222_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT221_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT220_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT219_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT218_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT217_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT216_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT215_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT214_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT213_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT212_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT211_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT210_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT209_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT208_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT207_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT206_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT205_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT204_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT203_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT202_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT201_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT200_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT199_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT198_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT197_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT196_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT195_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT194_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT193_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT192_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT191_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT190_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT189_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT188_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT187_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT186_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT185_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT184_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT183_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT182_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT181_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT180_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT179_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT178_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT177_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT176_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT175_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT174_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT173_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT172_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT171_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT170_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT169_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT168_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT167_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT166_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT165_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT164_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT163_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT162_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT161_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT160_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT159_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT158_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT157_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT156_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT155_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT154_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT153_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT152_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT151_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT150_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT149_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT148_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT147_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT146_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT145_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT144_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT143_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT142_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT141_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT140_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT139_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT138_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT137_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT136_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT135_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT134_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT133_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT132_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT131_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT130_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT129_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT128_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT127_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT126_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT125_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT124_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT123_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT122_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT121_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT120_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT119_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT118_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT117_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT116_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT115_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT114_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT113_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT112_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT111_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT110_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT109_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT108_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT107_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT106_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT105_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT104_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT103_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT102_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT101_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT100_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT96_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT94_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT93_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT92_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT91_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT90_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT89_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT88_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT87_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT86_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT85_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT84_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT83_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT82_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT81_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT80_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT79_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT78_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT77_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT76_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT75_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT74_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT73_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT72_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT71_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT70_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT69_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT68_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT67_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT66_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT65_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT64_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT63_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT62_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT61_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT60_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT59_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT58_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT57_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT56_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT55_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT54_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT53_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT52_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT51_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT50_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT49_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT48_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT47_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT46_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT45_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT44_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT43_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT42_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT41_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT40_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT39_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT38_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT37_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT36_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT35_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT34_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT33_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT32_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT31_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT30_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT29_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT28_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT27_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT26_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT25_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT24_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT23_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT22_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT21_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT20_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT19_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT18_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT17_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT16_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT15_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT14_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT13_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT12_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT11_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT10_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT8_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT7_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT6_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT5_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT4_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT3_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT2_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT1_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT0_INIT_VAL">0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT255_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT254_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT253_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT252_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT251_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT250_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT249_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT248_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT247_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT246_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT245_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT244_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT243_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT242_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT241_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT240_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT239_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT238_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT237_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT236_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT235_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT234_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT233_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT232_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT231_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT230_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT229_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT228_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT227_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT226_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT225_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT224_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT223_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT222_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT221_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT220_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT219_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT218_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT217_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT216_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT215_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT214_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT213_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT212_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT211_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT210_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT209_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT208_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT207_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT206_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT205_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT204_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT203_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT202_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT201_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT200_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT199_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT198_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT197_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT196_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT195_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT194_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT193_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT192_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT191_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT190_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT189_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT188_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT187_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT186_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT185_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT184_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT183_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT182_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT181_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT180_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT179_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT178_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT177_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT176_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT175_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT174_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT173_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT172_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT171_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT170_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT169_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT168_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT167_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT166_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT165_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT164_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT163_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT162_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT161_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT160_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT159_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT158_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT157_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT156_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT155_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT154_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT153_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT152_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT151_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT150_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT149_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT148_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT147_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT146_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT145_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT144_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT143_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT142_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT141_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT140_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT139_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT138_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT137_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT136_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT135_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT134_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT133_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT132_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT131_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT130_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT129_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT128_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT127_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT126_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT125_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT124_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT123_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT122_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT121_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT120_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT119_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT118_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT117_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT116_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT115_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT114_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT113_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT112_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT111_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT110_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT109_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT108_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT107_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT106_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT105_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT104_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT103_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT102_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT101_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT100_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT99_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT98_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT97_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT96_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT95_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT94_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT93_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT92_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT91_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT90_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT89_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT88_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT87_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT86_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT85_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT84_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT83_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT82_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT81_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT80_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT79_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT78_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT77_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT76_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT75_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT74_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT73_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT72_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT71_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT70_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT69_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT68_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT67_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT66_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT65_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT64_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT63_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT62_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT61_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT60_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT59_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT58_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT57_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT56_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT55_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT54_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT53_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT52_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT51_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT50_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT49_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT48_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT47_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT46_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT45_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT44_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT43_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT42_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT41_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT40_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT39_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT38_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT37_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT36_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT35_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT34_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT33_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT32_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT31_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT30_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT29_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT28_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT27_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT26_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT25_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT24_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT23_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT22_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT21_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT20_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT19_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT18_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT17_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT16_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT15_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT14_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT13_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT12_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT11_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT10_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT9_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT8_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT7_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT6_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT5_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT4_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT3_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT2_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT1_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_OUT0_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN255_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN254_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN253_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN252_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN251_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN250_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN249_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN248_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN247_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN246_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN245_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN244_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN243_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN242_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN241_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN240_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN239_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN238_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN237_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN236_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN235_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN234_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN233_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN232_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN231_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN230_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN229_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN228_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN227_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN226_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN225_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN224_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN223_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN222_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN221_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN220_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN219_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN218_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN217_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN216_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN215_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN214_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN213_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN212_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN211_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN210_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN209_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN208_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN207_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN206_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN205_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN204_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN203_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN202_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN201_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN200_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN199_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN198_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN197_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN196_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN195_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN194_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN193_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN192_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN191_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN190_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN189_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN188_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN187_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN186_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN185_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN184_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN183_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN182_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN181_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN180_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN179_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN178_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN177_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN176_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN175_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN174_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN173_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN172_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN171_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN170_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN169_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN168_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN167_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN166_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN165_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN164_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN163_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN162_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN161_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN160_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN159_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN158_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN157_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN156_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN155_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN154_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN153_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN152_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN151_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN150_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN149_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN148_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN147_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN146_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN145_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN144_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN143_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN142_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN141_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN140_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN139_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN138_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN137_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN136_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN135_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN134_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN133_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN132_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN131_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN130_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN129_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN128_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN127_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN126_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN125_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN124_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN123_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN122_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN121_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN120_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN119_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN118_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN117_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN116_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN115_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN114_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN113_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN112_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN111_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN110_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN109_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN108_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN107_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN106_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN105_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN104_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN103_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN102_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN101_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN100_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN99_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN98_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN97_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN96_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN95_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN94_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN93_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN92_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN91_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN90_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN89_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN88_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN87_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN86_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN85_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN84_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN83_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN82_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN81_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN80_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN79_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN78_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN77_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN76_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN75_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN74_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN73_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN72_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN71_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN70_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN69_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN68_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN67_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN66_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN65_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN64_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN63_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN62_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN61_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN60_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN59_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN58_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN57_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN56_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN55_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN54_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN53_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN52_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN51_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN50_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN49_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN48_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN47_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN46_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN45_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN44_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN43_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN42_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN41_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN40_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN39_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN38_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN37_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN36_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN35_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN34_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN33_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN32_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN31_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN30_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN29_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN28_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN27_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN26_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN25_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN24_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN23_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN22_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN21_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN20_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN19_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN18_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN17_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN16_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN15_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN14_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN13_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN12_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN11_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN10_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN9_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN8_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN7_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN6_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN5_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN4_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN3_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN2_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN1_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_PROBE_IN0_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_SYNCHRONIZATION">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_NUM_PROBE_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">vio_0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XLNX_HW_PROBE_INFO">NUM_PROBE_IN=1,NUM_PROBE_OUT=1,PROBE_IN0_WIDTH=1,PROBE_IN1_WIDTH=1,PROBE_IN2_WIDTH=1,PROBE_IN3_WIDTH=1,PROBE_IN4_WIDTH=1,PROBE_IN5_WIDTH=1,PROBE_IN6_WIDTH=1,PROBE_IN7_WIDTH=1,PROBE_IN8_WIDTH=1,PROBE_IN9_WIDTH=1,PROBE_IN10_WIDTH=1,PROBE_IN11_WIDTH=1,PROBE_IN12_WIDTH=1,PROBE_IN13_WIDTH=1,PROBE_IN14_WIDTH=1,PROBE_IN15_WIDTH=1,PROBE_IN16_WIDTH=1,PROBE_IN17_WIDTH=1,PROBE_IN18_WIDTH=1,PROBE_IN19_WIDTH=1,PROBE_IN20_WIDTH=1,PROBE_IN21_WIDTH=1,PROBE_IN22_WIDTH=1,PROBE_IN23_WIDTH=1,PROBE_IN24_WIDTH=1,PROBE_IN25_WIDTH=1,PROBE_IN26_WIDTH=1,PROBE_IN27_WIDTH=1,PROBE_IN28_WIDTH=1,PROBE_IN29_WIDTH=1,PROBE_IN30_WIDTH=1,PROBE_IN31_WIDTH=1,PROBE_IN32_WIDTH=1,PROBE_IN33_WIDTH=1,PROBE_IN34_WIDTH=1,PROBE_IN35_WIDTH=1,PROBE_IN36_WIDTH=1,PROBE_IN37_WIDTH=1,PROBE_IN38_WIDTH=1,PROBE_IN39_WIDTH=1,PROBE_IN40_WIDTH=1,PROBE_IN41_WIDTH=1,PROBE_IN42_WIDTH=1,PROBE_IN43_WIDTH=1,PROBE_IN44_WIDTH=1,PROBE_IN45_WIDTH=1,PROBE_IN46_WIDTH=1,PROBE_IN47_WIDTH=1,PROBE_IN48_WIDTH=1,PROBE_IN49_WIDTH=1,PROBE_IN50_WIDTH=1,PROBE_IN51_WIDTH=1,PROBE_IN52_WIDTH=1,PROBE_IN53_WIDTH=1,PROBE_IN54_WIDTH=1,PROBE_IN55_WIDTH=1,PROBE_IN56_WIDTH=1,PROBE_IN57_WIDTH=1,PROBE_IN58_WIDTH=1,PROBE_IN59_WIDTH=1,PROBE_IN60_WIDTH=1,PROBE_IN61_WIDTH=1,PROBE_IN62_WIDTH=1,PROBE_IN63_WIDTH=1,PROBE_OUT0_WIDTH=1,PROBE_OUT1_WIDTH=1,PROBE_OUT2_WIDTH=1,PROBE_OUT3_WIDTH=1,PROBE_OUT4_WIDTH=1,PROBE_OUT5_WIDTH=1,PROBE_OUT6_WIDTH=1,PROBE_OUT7_WIDTH=1,PROBE_OUT8_WIDTH=1,PROBE_OUT9_WIDTH=1,PROBE_OUT10_WIDTH=1,PROBE_OUT11_WIDTH=1,PROBE_OUT12_WIDTH=1,PROBE_OUT13_WIDTH=1,PROBE_OUT14_WIDTH=1,PROBE_OUT15_WIDTH=1,PROBE_OUT16_WIDTH=1,PROBE_OUT17_WIDTH=1,PROBE_OUT18_WIDTH=1,PROBE_OUT19_WIDTH=1,PROBE_OUT20_WIDTH=1,PROBE_OUT21_WIDTH=1,PROBE_OUT22_WIDTH=1,PROBE_OUT23_WIDTH=1,PROBE_OUT24_WIDTH=1,PROBE_OUT25_WIDTH=1,PROBE_OUT26_WIDTH=1,PROBE_OUT27_WIDTH=1,PROBE_OUT28_WIDTH=1,PROBE_OUT29_WIDTH=1,PROBE_OUT30_WIDTH=1,PROBE_OUT31_WIDTH=1,PROBE_OUT32_WIDTH=1,PROBE_OUT33_WIDTH=1,PROBE_OUT34_WIDTH=1,PROBE_OUT35_WIDTH=1,PROBE_OUT36_WIDTH=1,PROBE_OUT37_WIDTH=1,PROBE_OUT38_WIDTH=1,PROBE_OUT39_WIDTH=1,PROBE_OUT40_WIDTH=1,PROBE_OUT41_WIDTH=1,PROBE_OUT42_WIDTH=1,PROBE_OUT43_WIDTH=1,PROBE_OUT44_WIDTH=1,PROBE_OUT45_WIDTH=1,PROBE_OUT46_WIDTH=1,PROBE_OUT47_WIDTH=1,PROBE_OUT48_WIDTH=1,PROBE_OUT49_WIDTH=1,PROBE_OUT50_WIDTH=1,PROBE_OUT51_WIDTH=1,PROBE_OUT52_WIDTH=1,PROBE_OUT53_WIDTH=1,PROBE_OUT54_WIDTH=1,PROBE_OUT55_WIDTH=1,PROBE_OUT56_WIDTH=1,PROBE_OUT57_WIDTH=1,PROBE_OUT58_WIDTH=1,PROBE_OUT59_WIDTH=1,PROBE_OUT60_WIDTH=1,PROBE_OUT61_WIDTH=1,PROBE_OUT62_WIDTH=1,PROBE_OUT63_WIDTH=1,PROBE_OUT0_INIT_VAL=0x0,PROBE_OUT1_INIT_VAL=0x0,PROBE_OUT2_INIT_VAL=0x0,PROBE_OUT3_INIT_VAL=0x0,PROBE_OUT4_INIT_VAL=0x0,PROBE_OUT5_INIT_VAL=0x0,PROBE_OUT6_INIT_VAL=0x0,PROBE_OUT7_INIT_VAL=0x0,PROBE_OUT8_INIT_VAL=0x0,PROBE_OUT9_INIT_VAL=0x0,PROBE_OUT10_INIT_VAL=0x0,PROBE_OUT11_INIT_VAL=0x0,PROBE_OUT12_INIT_VAL=0x0,PROBE_OUT13_INIT_VAL=0x0,PROBE_OUT14_INIT_VAL=0x0,PROBE_OUT15_INIT_VAL=0x0,PROBE_OUT16_INIT_VAL=0x0,PROBE_OUT17_INIT_VAL=0x0,PROBE_OUT18_INIT_VAL=0x0,PROBE_OUT19_INIT_VAL=0x0,PROBE_OUT20_INIT_VAL=0x0,PROBE_OUT21_INIT_VAL=0x0,PROBE_OUT22_INIT_VAL=0x0,PROBE_OUT23_INIT_VAL=0x0,PROBE_OUT24_INIT_VAL=0x0,PROBE_OUT25_INIT_VAL=0x0,PROBE_OUT26_INIT_VAL=0x0,PROBE_OUT27_INIT_VAL=0x0,PROBE_OUT28_INIT_VAL=0x0,PROBE_OUT29_INIT_VAL=0x0,PROBE_OUT30_INIT_VAL=0x0,PROBE_OUT31_INIT_VAL=0x0,PROBE_OUT32_INIT_VAL=0x0,PROBE_OUT33_INIT_VAL=0x0,PROBE_OUT34_INIT_VAL=0x0,PROBE_OUT35_INIT_VAL=0x0,PROBE_OUT36_INIT_VAL=0x0,PROBE_OUT37_INIT_VAL=0x0,PROBE_OUT38_INIT_VAL=0x0,PROBE_OUT39_INIT_VAL=0x0,PROBE_OUT40_INIT_VAL=0x0,PROBE_OUT41_INIT_VAL=0x0,PROBE_OUT42_INIT_VAL=0x0,PROBE_OUT43_INIT_VAL=0x0,PROBE_OUT44_INIT_VAL=0x0,PROBE_OUT45_INIT_VAL=0x0,PROBE_OUT46_INIT_VAL=0x0,PROBE_OUT47_INIT_VAL=0x0,PROBE_OUT48_INIT_VAL=0x0,PROBE_OUT49_INIT_VAL=0x0,PROBE_OUT50_INIT_VAL=0x0,PROBE_OUT51_INIT_VAL=0x0,PROBE_OUT52_INIT_VAL=0x0,PROBE_OUT53_INIT_VAL=0x0,PROBE_OUT54_INIT_VAL=0x0,PROBE_OUT55_INIT_VAL=0x0,PROBE_OUT56_INIT_VAL=0x0,PROBE_OUT57_INIT_VAL=0x0,PROBE_OUT58_INIT_VAL=0x0,PROBE_OUT59_INIT_VAL=0x0,PROBE_OUT60_INIT_VAL=0x0,PROBE_OUT61_INIT_VAL=0x0,PROBE_OUT62_INIT_VAL=0x0,PROBE_OUT63_INIT_VAL=0x0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE_INFO1">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE_INFO2">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MAJOR_VERSION">2013</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MINOR_VERSION">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BUILD_REVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE_MAJOR_VER">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE_MINOR_VER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CORE_MINOR_ALPHA_VER">97</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XSDB_SLAVE_TYPE">33</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NEXT_SLAVE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CSE_DRV_VER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_TEST_REG">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PIPE_IFACE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BUS_ADDR_WIDTH">17</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BUS_DATA_WIDTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_IN">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_PROBE_IN_ACTIVITY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_PROBE_OUT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USER_REPO_PATHS"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2014.1.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_2gb/GTX_trb3_2gb.xci b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_2gb/GTX_trb3_2gb.xci
new file mode 100644
index 0000000..ac3e4e8
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_2gb/GTX_trb3_2gb.xci
@@ -0,0 +1,1191 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>GTX_trb3_2gb</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gtwizard" spirit:version="3.5"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">GTX_trb3_2gb</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">GTX_trb3_2gb</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb/GTX_trb3_sync_2gb.xci b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb/GTX_trb3_sync_2gb.xci
new file mode 100644
index 0000000..e07b69a
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb/GTX_trb3_sync_2gb.xci
@@ -0,0 +1,1245 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>GTX_trb3_sync_2gb</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="gtwizard" spirit:version="3.5"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">GTX_trb3_sync_2gb</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_tx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt10_val_rx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.identical_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_data_width">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txoutclk_source">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxoutclk_source">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz_selection">GTZ0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_multi_channel_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk0_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txoutclk1_source">TXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk0_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk1_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk2_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxoutclk3_source">RXOUTCLK_LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txoutclk_source">TX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxoutclk_source">RX_FIFO_CLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz1_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz2_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz3_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz4_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz5_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz6_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz7_val_encoding">100GBASER_MODE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.component_name">GTX_trb3_sync_2gb</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_type">GTX</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_column">right_column</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.identical_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_drp_clock">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_qpll">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_tx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_tx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_tx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_tx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_tx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_tx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_tx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_tx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_tx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_tx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt1_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt2_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt3_val_rx_refclk">REFCLK1_Q0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt4_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt5_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt6_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt7_val_rx_refclk">REFCLK1_Q1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt8_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt9_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt10_val_rx_refclk">REFCLK0_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt11_val_rx_refclk">REFCLK1_Q2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt12_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt13_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt14_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt15_val_rx_refclk">REFCLK1_Q3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt16_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt17_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt18_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt19_val_rx_refclk">REFCLK1_Q4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt20_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt21_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt22_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt23_val_rx_refclk">REFCLK1_Q5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt24_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt25_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt26_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt27_val_rx_refclk">REFCLK1_Q6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt28_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt29_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt30_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt31_val_rx_refclk">REFCLK1_Q7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt32_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt33_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt34_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt35_val_rx_refclk">REFCLK1_Q8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.advanced_clocking">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.prbs_gen_check">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_encoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_fbdiv">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_fbdiv">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_qpll_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_txout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_line_rate">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_data_width">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_decoding">8B/10B</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_int_datawidth">20</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_reference_clock">125.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cpll_rxout_div">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_drp_clock">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10bbypass">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispmode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txchardispval">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxchariscomma">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcharisk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrundisp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txusrclk">TXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxbuf_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxusrclk">RXOUTCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcsreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbufreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxoutclk">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxrate">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxcomma_deten">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_det">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_mcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_pcomma_detect">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dec_valid_comma_only">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_comma_preset">K28.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_pcomma_value">0101111100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_mcomma_value">1010000011</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_enable">1111111111</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_double">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_align_comma_word">Any_Byte_Boundary</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxmcommaalignen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxslide">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyteisaligned">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxbyterealign">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcommadet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiff_emph_mode">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txdiffctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txpostcursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_dfe_mode">LPM-Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_agc_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_termination_voltage">AVTT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_cm_trim">800</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txinhibit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpibiasen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpistrongpdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txqpiweakpup">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpien">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenn">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxqpisenp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfereset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxdfeagcovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmhfovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmlfklovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pcs_pcie_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_rx_burst_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_sata_e_idle_val">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_to_p2">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_from_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_pd_trans_time_non_p2">60</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_sigvalidclk">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_clkrsvd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_tx8b10ben">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmovrden">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmstepsize">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpippmsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxvalid">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cominitdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comsasdet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_comwakedet">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcominit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomsas">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomwake">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txcomfinish">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txdetectrx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txelecidle">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_phystatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxelecidle">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_prbs_detector">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbssel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txprbsforceerr">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxprbs_err_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cb">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_max_skew">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_use">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_len">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_ppm_offset">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_cc_seq_periodicity">5000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_chan_bond_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_1_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_1_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_2_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_3_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4">00000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_k">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_disp">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_clk_cor_seq_2_4_mask">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxslide_mode">OFF</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_max_cb_level">7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txoutclk_source">USE_TXPLLREFCLK</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rxoutclk_source">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_gt_in_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.num_active_unit">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xspeedgrade">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_xdevice">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_row">bottom_row</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.silicon_version">no_silicon_version_loaded</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_tx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt_val_rx_pll">CPLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_tx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_tx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_tx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt36_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt37_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt38_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt39_val_rx_refclk">REFCLK1_Q9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt40_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt41_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt42_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt43_val_rx_refclk">REFCLK1_Q10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt44_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt45_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt46_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt47_val_rx_refclk">REFCLK1_Q11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_uselabtools">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_usesharedlogic">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll0_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_fbdiv_45">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_refclk_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_txout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_pll1_rxout_div">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_sync_mode">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_en">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_lpm_dfe">DFE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.pcie_cb_mode">One_Hop</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll0pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_pll1pd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_cpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_qpllpd">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxstartofseq">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_tx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_buffer_bypass_mode">Auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpmareset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpmareset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxsysclksel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxcdrhold">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txprecursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_txmaincursor">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_rx_equalizer">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxlpmen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_txpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_port_rxpowerdown">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gt0_val_oob">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal1_val">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_config">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_multi_channel_mode">0000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_master_slave">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz0">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz1">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz2">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz3">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz4">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz5">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz6">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.use_gtz7">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_protocol_file">Start_from_scratch</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_tx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_line_rate">25.78125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_no_rx">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_identical_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk0">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_refclk1">322.266</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk0_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk1_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk2_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxoutclk3_source">LANE0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_drpclk_source">DRPCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_refclk_source">REFCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txoutclk_source">TXOUTCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxoutclk_source">RXRECCLKPMA_DIV4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk0_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk1_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk2_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk3_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk4_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk5_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk6_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_txusrclk7_source">OCTAL0_TXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk0_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk1_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk2_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk3_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk4_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk5_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk6_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.octal0_val_rxusrclk7_source">OCTAL0_RXOUTCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_txusrclk_source">TXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rxusrclk_source">RXUSRCLK0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_data_width">160</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_encoding">GB_100GBASE_R4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txoutputen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqpostctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txeqprectrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txslewctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txattnctrl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfibreset">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxfifostatus">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxratesel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxpolarity">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxsignalok">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxbitslip">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_refsel">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_corecntl">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_pllrecalen">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_loopback">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_txprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_port_rxprbs">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz0_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz1_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz2_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz3_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz4_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz5_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz6_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_rx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N1">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_N2">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.gtz7_val_tx_div_L">0.5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_tx_pll" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt_val_rx_pll" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt10_val" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt10_val_tx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt10_val_rx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val_tx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt14_val_rx_refclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_tx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.identical_val_rx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_encoding" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_int_datawidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_line_rate" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_data_width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_decoding" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_int_datawidth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_reference_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv_45" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_cpll_fbdiv" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_drp_clock" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxcharisk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txbuf_en" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_tx_buffer_bypass_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_txoutclk_source" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxbuf_en" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_buffer_bypass_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxusrclk" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_comma_preset" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_align_comma_word" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_port_rxslide" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_dfe_mode" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_termination_voltage" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rx_cm_trim" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_1_4" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_3" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_clk_cor_seq_2_4" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.gt0_val_rxslide_mode" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb.vhd
new file mode 100644
index 0000000..3cd15db
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb.vhd
@@ -0,0 +1,403 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_trb3_sync_2gb.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_trb3_sync_2gb (a Core Top)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_trb3_sync_2gb is
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end GTX_trb3_sync_2gb;
+
+architecture RTL of GTX_trb3_sync_2gb is
+    attribute DowngradeIPIdentifiedWarnings: string;
+    attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+    attribute X_CORE_INFO : string;
+    attribute X_CORE_INFO of RTL : architecture is "GTX_trb3_sync_2gb,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_trb3_sync_2gb,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+--**************************Component Declarations*****************************
+
+component GTX_trb3_sync_2gb_init 
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    EXAMPLE_SIMULATION                      : integer   := 0;          -- Set to 1 for simulation
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+ 
+    STABLE_CLOCK_PERIOD                     : integer   := 10;  
+        -- Set to 1 for simulation
+    EXAMPLE_USE_CHIPSCOPE                   : integer   := 1       --// Modified       -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+end component;
+ 
+--**************************** Main Body of Code *******************************
+begin
+    U0 : GTX_trb3_sync_2gb_init
+    generic map
+(
+        EXAMPLE_SIM_GTRESET_SPEEDUP   => "TRUE",
+        EXAMPLE_SIMULATION            => 0,
+ 
+        USE_BUFG           => 0,
+ 
+        STABLE_CLOCK_PERIOD           => 10,
+        EXAMPLE_USE_CHIPSCOPE         => 1 --// Modified
+)
+port map
+(
+        SYSCLK_IN                       =>      SYSCLK_IN,
+        SOFT_RESET_TX_IN                =>      SOFT_RESET_TX_IN,
+        SOFT_RESET_RX_IN                =>      SOFT_RESET_RX_IN,
+        DONT_RESET_ON_DATA_ERROR_IN     =>      DONT_RESET_ON_DATA_ERROR_IN,
+    GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
+    GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT,
+    GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
+    GT0_TX_MMCM_LOCK_IN => GT0_TX_MMCM_LOCK_IN,
+    GT0_TX_MMCM_RESET_OUT => GT0_TX_MMCM_RESET_OUT,
+
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      gt0_cplllockdetclk_in,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+    -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      gt0_gtrefclk0_in,
+        gt0_gtrefclk1_in                =>      gt0_gtrefclk1_in,
+    ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      gt0_drpclk_in,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+    --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+    --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+    -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+	------------------------- Receive Ports - CDR Ports ------------------------
+		GT0_RXCDRRESET_IN               => GT0_RXCDRRESET_IN, --// Modified
+		GT0_RXCDRLOCK_OUT               => GT0_RXCDRLOCK_OUT, --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_in,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_in,
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+    --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_out,
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+    --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_in,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_in,
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_out,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  => GT0_QPLLOUTCLK_IN,
+     GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN 
+
+);
+ 
+end RTL;    
+ 
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_auto_phase_align.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_auto_phase_align.vhd
new file mode 100644
index 0000000..1952e54
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_auto_phase_align.vhd
@@ -0,0 +1,198 @@
+--//////////////////////////////////////////////////////////////////////////////
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_trb3_sync_2gb_auto_phase_align.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description : The logic below implements the procedure to do automatic phase-alignment 
+--                on the 7-series GTX as described in ug476pdf, version 1.3,
+--                Chapters "Using the TX Phase Alignment to Bypass the TX Buffer"
+--                and "Using the RX Phase Alignment to Bypass the RX Elastic Buffer"
+--                Should the logic below differ from what is described in a later version  
+--                of the user-guide, you are using an auto-alignment block, which is 
+--                out of date and needs to be updated for safe operation.
+--                     
+--
+--
+-- Module GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN is     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RUN_PHALIGNMENT          : in  STD_LOGIC;              --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Auto phase-alignment performed sucessfully
+           PHALIGNDONE              : in  STD_LOGIC;              --\ Phase-alignment signals from and to the
+           DLYSRESET                : out STD_LOGIC;              -- |transceiver.
+           DLYSRESETDONE            : in  STD_LOGIC;              --/
+           RECCLKSTABLE             : in  STD_LOGIC               --/on the RX-side.
+           
+           );
+end GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN;
+
+architecture RTL of GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN is
+
+  component GTX_trb3_sync_2gb_sync_block
+   generic (
+     INITIALISE : bit_vector(5 downto 0) := "000000"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+  type phase_align_auto_fsm is(
+    INIT, WAIT_PHRST_DONE, COUNT_PHALIGN_DONE, PHALIGN_DONE
+    );
+    
+  signal phalign_state       : phase_align_auto_fsm := INIT;
+  signal phaligndone_prev     : std_logic := '0';
+  signal phaligndone_ris_edge : std_logic;
+
+  signal count_phalign_edges   : integer range 0 to 3:= 0;
+  signal phaligndone_sync      : std_logic := '0';
+  signal dlysresetdone_sync    : std_logic := '0';
+
+begin
+
+ sync_PHALIGNDONE : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  PHALIGNDONE,
+            data_out        =>  phaligndone_sync 
+         );
+
+  sync_DLYSRESETDONE : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  DLYSRESETDONE,
+            data_out        =>  dlysresetdone_sync 
+         );
+
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      phaligndone_prev <= phaligndone_sync; 
+    end if;
+  end process;
+  phaligndone_ris_edge <= '1' when (phaligndone_prev = '0') and (phaligndone_sync = '1') else '0';
+  
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if RUN_PHALIGNMENT = '0' or RECCLKSTABLE = '0' then
+        DLYSRESET           <= '0';
+        count_phalign_edges   <= 0;
+        PHASE_ALIGNMENT_DONE  <= '0';
+        phalign_state      <= INIT;
+      else
+        if phaligndone_ris_edge = '1' then
+          if count_phalign_edges < 3 then
+            count_phalign_edges <= count_phalign_edges + 1;
+          end if;
+        end if;
+        
+        DLYSRESET         <= '0';
+                  
+        case phalign_state is
+          when INIT => 
+            PHASE_ALIGNMENT_DONE <= '0';
+            if RUN_PHALIGNMENT = '1' and RECCLKSTABLE = '1' then
+              --DLYSRESET is toggled to '1'
+              DLYSRESET  <= '1';
+              phalign_state <= WAIT_PHRST_DONE;
+            end if;           
+            
+          when WAIT_PHRST_DONE =>
+            if dlysresetdone_sync = '1' then
+              phalign_state <= COUNT_PHALIGN_DONE;
+            end if;
+            --No timeout-check here as that is done in the main FSM
+            
+          when COUNT_PHALIGN_DONE =>
+            if (count_phalign_edges = 2) then
+
+              --For GTX: Only on the second edge of the PHALIGNDONE-signal the 
+              --         phase-alignment is completed
+              --For GTH, GTP: TXSYNCDONE indicates the completion of Phase Alignment
+
+              phalign_state <= PHALIGN_DONE;
+            end if;
+          
+          when PHALIGN_DONE =>
+            PHASE_ALIGNMENT_DONE <= '1';
+
+          when OTHERS =>
+            phalign_state      <= INIT;
+
+        end case;        
+      end if;      
+    end if;    
+  end process;
+
+end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_cpll_railing.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_cpll_railing.vhd
new file mode 100644
index 0000000..811fc58
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_cpll_railing.vhd
@@ -0,0 +1,144 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_trb3_sync_2gb_cpll_railing.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_trb3_sync_2gb_cpll_railing
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity GTX_trb3_sync_2gb_cpll_railing is
+generic( USE_BUFG       : integer := 0
+       );
+   port  (
+         cpll_reset_out : out std_logic;
+         cpll_pd_out : out std_logic;
+         refclk_out : out std_logic;
+        
+         refclk_in : in std_logic
+          );
+   end GTX_trb3_sync_2gb_cpll_railing;
+
+
+architecture RTL of GTX_trb3_sync_2gb_cpll_railing is
+
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+attribute equivalent_register_removal: string; 
+signal cpllpd_wait    :   std_logic_vector(95 downto 0)  := x"FFFFFFFFFFFFFFFFFFFFFFFF";
+signal cpllreset_wait :   std_logic_vector(127 downto 0) := x"000000000000000000000000000000FF";
+attribute equivalent_register_removal of cpllpd_wait : signal is "no";
+attribute equivalent_register_removal of cpllreset_wait : signal is "no";
+signal    gtrefclk0_i      :std_logic ;
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+  use_bufg_cpll:if(USE_BUFG = 1) generate
+  refclk_buf : BUFG
+  port map
+   (O   => gtrefclk0_i,
+    I   => refclk_in);
+
+  end generate;
+
+  use_bufr_cpll:if(USE_BUFG = 0) generate
+  refclk_buf : BUFR
+  port map
+   (O   => gtrefclk0_i,
+    CE  => tied_to_vcc_i,
+    CLR => tied_to_ground_i,
+    I   => refclk_in);
+
+  end generate;
+
+    process( gtrefclk0_i )
+    begin
+        if(gtrefclk0_i'event and gtrefclk0_i = '1') then 
+           cpllpd_wait <= cpllpd_wait(94 downto 0) & '0';
+           cpllreset_wait <= cpllreset_wait(126 downto 0) & '0';
+         end if;
+    end process;
+
+cpll_pd_out <= cpllpd_wait(95);
+cpll_reset_out <= cpllreset_wait(127);
+refclk_out <= gtrefclk0_i;
+
+
+ end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_gt.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_gt.vhd
new file mode 100644
index 0000000..51dc62a
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_gt.vhd
@@ -0,0 +1,834 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_trb3_sync_2gb_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_trb3_sync_2gb_GT (a GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***************************** Entity Declaration ****************************
+
+entity GTX_trb3_sync_2gb_GT is
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP    : string     :=  "FALSE";        -- Set to "TRUE" to speed up sim reset
+    RX_DFE_KL_CFG2_IN         : bit_vector :=   X"301148AC";
+    SIM_CPLLREFCLK_SEL        : bit_vector :=   "001";
+    PMA_RSV_IN                : bit_vector :=  x"00018480";
+    PCS_RSVD_ATTR_IN          : bit_vector :=   X"000000000000"
+);
+port 
+(
+     cpllpd_in : in std_logic;
+     cpllrefclksel_in : in std_logic_vector(2 downto 0);
+    --------------------------------- CPLL Ports -------------------------------
+    cpllfbclklost_out                       : out  std_logic;
+    cplllock_out                            : out  std_logic;
+    cplllockdetclk_in                       : in   std_logic;
+    cpllrefclklost_out                      : out  std_logic;
+    cpllreset_in                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gtrefclk0_in                            : in   std_logic;
+    gtrefclk1_in                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    drpaddr_in                              : in   std_logic_vector(8 downto 0);
+    drpclk_in                               : in   std_logic;
+    drpdi_in                                : in   std_logic_vector(15 downto 0);
+    drpdo_out                               : out  std_logic_vector(15 downto 0);
+    drpen_in                                : in   std_logic;
+    drprdy_out                              : out  std_logic;
+    drpwe_in                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    qpllclk_in                              : in   std_logic;
+    qpllrefclk_in                           : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    dmonitorout_out                         : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    eyescanreset_in                         : in   std_logic;
+    rxuserrdy_in                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    eyescandataerror_out                    : out  std_logic;
+    eyescantrigger_in                       : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	RXCDRRESET_IN                           : in  std_logic; --// Modified
+    RXCDRLOCK_OUT                           : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    rxusrclk_in                             : in   std_logic;
+    rxusrclk2_in                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    rxdata_out                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    rxdisperr_out                           : out  std_logic_vector(1 downto 0);
+    rxnotintable_out                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gtxrxp_in                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gtxrxn_in                               : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    rxdlyen_in                              : in   std_logic;
+    rxdlysreset_in                          : in   std_logic;
+    rxdlysresetdone_out                     : out  std_logic;
+    rxphalign_in                            : in   std_logic;
+    rxphaligndone_out                       : out  std_logic;
+    rxphalignen_in                          : in   std_logic;
+    rxphdlyreset_in                         : in   std_logic;
+    rxphmonitor_out                         : out  std_logic_vector(4 downto 0);
+    rxphslipmonitor_out                     : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    rxlpmhfhold_in                          : in   std_logic;
+    rxlpmlfhold_in                          : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    rxdfelpmreset_in                        : in   std_logic;
+    rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
+    rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    rxoutclk_out                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gtrxreset_in                            : in   std_logic;
+    rxpmareset_in                           : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    rxcharisk_out                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    rxresetdone_out                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gttxreset_in                            : in   std_logic;
+    txuserrdy_in                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    txusrclk_in                             : in   std_logic;
+    txusrclk2_in                            : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    txdlyen_in                              : in   std_logic;
+    txdlysreset_in                          : in   std_logic;
+    txdlysresetdone_out                     : out  std_logic;
+    txphalign_in                            : in   std_logic;
+    txphaligndone_out                       : out  std_logic;
+    txphalignen_in                          : in   std_logic;
+    txphdlyreset_in                         : in   std_logic;
+    txphinit_in                             : in   std_logic;
+    txphinitdone_out                        : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    txdata_in                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gtxtxn_out                              : out  std_logic;
+    gtxtxp_out                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    txoutclk_out                            : out  std_logic;
+    txoutclkfabric_out                      : out  std_logic;
+    txoutclkpcs_out                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    txcharisk_in                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    txresetdone_out                         : out  std_logic
+
+
+);
+
+
+end GTX_trb3_sync_2gb_GT;
+
+architecture RTL of GTX_trb3_sync_2gb_GT is
+   
+--**************************** Signal Declarations ****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+
+
+
+    -- RX Datapath signals
+    signal rxdata_i                         :   std_logic_vector(63 downto 0);      
+    signal rxchariscomma_float_i            :   std_logic_vector(5 downto 0);
+    signal rxcharisk_float_i                :   std_logic_vector(5 downto 0);
+    signal rxdisperr_float_i                :   std_logic_vector(5 downto 0);
+    signal rxnotintable_float_i             :   std_logic_vector(5 downto 0);
+    signal rxrundisp_float_i                :   std_logic_vector(5 downto 0);
+
+
+    -- TX Datapath signals
+    signal txdata_i                         :   std_logic_vector(63 downto 0);
+    signal txkerr_float_i                   :   std_logic_vector(5 downto 0);
+    signal txrundisp_float_i                :   std_logic_vector(5 downto 0);
+    signal rxstartofseq_float_i             :   std_logic;
+--******************************** Main Body of Code***************************
+                       
+begin                      
+
+    ---------------------------  Static signal Assignments ---------------------   
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+
+    -------------------  GT Datapath byte mapping  -----------------
+    RXDATA_OUT    <=   rxdata_i(15 downto 0);
+
+    txdata_i    <=   (tied_to_ground_vec_i(47 downto 0) & TXDATA_IN);
+
+
+
+    ----------------------------- GTXE2 Instance  --------------------------   
+
+    gtxe2_i :GTXE2_CHANNEL
+    generic map
+    (
+
+        --_______________________ Simulation-Only Attributes ___________________
+
+        SIM_RECEIVER_DETECT_PASS   =>      ("TRUE"),
+        SIM_RESET_SPEEDUP          =>      (GT_SIM_GTRESET_SPEEDUP),
+        SIM_TX_EIDLE_DRIVE_LEVEL   =>      ("X"),
+        SIM_CPLLREFCLK_SEL         =>      (SIM_CPLLREFCLK_SEL),
+        SIM_VERSION                =>      ("4.0"), 
+        
+
+       ------------------RX Byte and Word Alignment Attributes---------------
+        ALIGN_COMMA_DOUBLE                      =>     ("FALSE"),
+        ALIGN_COMMA_ENABLE                      =>     ("1111111111"),
+        ALIGN_COMMA_WORD                        =>     (1),
+        ALIGN_MCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_MCOMMA_VALUE                      =>     ("1010000011"),
+        ALIGN_PCOMMA_DET                        =>     ("TRUE"),
+        ALIGN_PCOMMA_VALUE                      =>     ("0101111100"),
+        SHOW_REALIGN_COMMA                      =>     ("FALSE"), --//("TRUE"), Modified
+        RXSLIDE_AUTO_WAIT                       =>     (7),
+        RXSLIDE_MODE                            =>     ("AUTO"), --// ("PCS"), Modified
+        RX_SIG_VALID_DLY                        =>     (10),
+
+       ------------------RX 8B/10B Decoder Attributes---------------
+        RX_DISPERR_SEQ_MATCH                    =>     ("TRUE"),
+        DEC_MCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_PCOMMA_DETECT                       =>     ("TRUE"),
+        DEC_VALID_COMMA_ONLY                    =>     ("FALSE"),
+
+       ------------------------RX Clock Correction Attributes----------------------
+        CBCC_DATA_SOURCE_SEL                    =>     ("DECODED"),
+        CLK_COR_SEQ_2_USE                       =>     ("FALSE"),
+        CLK_COR_KEEP_IDLE                       =>     ("FALSE"),
+        CLK_COR_MAX_LAT                         =>     (9),
+        CLK_COR_MIN_LAT                         =>     (7),
+        CLK_COR_PRECEDENCE                      =>     ("TRUE"),
+        CLK_COR_REPEAT_WAIT                     =>     (0),
+        CLK_COR_SEQ_LEN                         =>     (1),
+        CLK_COR_SEQ_1_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_1_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_1_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_1_4                         =>     ("0000000000"),
+        CLK_CORRECT_USE                         =>     ("FALSE"),
+        CLK_COR_SEQ_2_ENABLE                    =>     ("1111"),
+        CLK_COR_SEQ_2_1                         =>     ("0100000000"),
+        CLK_COR_SEQ_2_2                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_3                         =>     ("0000000000"),
+        CLK_COR_SEQ_2_4                         =>     ("0000000000"),
+
+       ------------------------RX Channel Bonding Attributes----------------------
+        CHAN_BOND_KEEP_ALIGN                    =>     ("FALSE"),
+        CHAN_BOND_MAX_SKEW                      =>     (1),
+        CHAN_BOND_SEQ_LEN                       =>     (1),
+        CHAN_BOND_SEQ_1_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_1_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_1                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_2                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_3                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_4                       =>     ("0000000000"),
+        CHAN_BOND_SEQ_2_ENABLE                  =>     ("1111"),
+        CHAN_BOND_SEQ_2_USE                     =>     ("FALSE"),
+        FTS_DESKEW_SEQ_ENABLE                   =>     ("1111"),
+        FTS_LANE_DESKEW_CFG                     =>     ("1111"),
+        FTS_LANE_DESKEW_EN                      =>     ("FALSE"),
+
+       ---------------------------RX Margin Analysis Attributes----------------------------
+        ES_CONTROL                              =>     ("000000"),
+        ES_ERRDET_EN                            =>     ("FALSE"),
+        ES_EYE_SCAN_EN                          =>     ("TRUE"),
+        ES_HORZ_OFFSET                          =>     (x"000"),
+        ES_PMA_CFG                              =>     ("0000000000"),
+        ES_PRESCALE                             =>     ("00000"),
+        ES_QUALIFIER                            =>     (x"00000000000000000000"),
+        ES_QUAL_MASK                            =>     (x"00000000000000000000"),
+        ES_SDATA_MASK                           =>     (x"00000000000000000000"),
+        ES_VERT_OFFSET                          =>     ("000000000"),
+
+       -------------------------FPGA RX Interface Attributes-------------------------
+        RX_DATA_WIDTH                           =>     (20),
+
+       ---------------------------PMA Attributes----------------------------
+        OUTREFCLK_SEL_INV                       =>     ("11"),
+        PMA_RSV                                 =>     (PMA_RSV_IN),
+        PMA_RSV2                                =>     (x"2050"),
+        PMA_RSV3                                =>     ("00"),
+        PMA_RSV4                                =>     (x"00000000"),
+        RX_BIAS_CFG                             =>     ("000000000100"),
+        DMONITOR_CFG                            =>     (x"000A00"),
+        RX_CM_SEL                               =>     ("00"),
+        RX_CM_TRIM                              =>     ("010"),
+        RX_DEBUG_CFG                            =>     ("000000000000"),
+        RX_OS_CFG                               =>     ("0000010000000"),
+        TERM_RCAL_CFG                           =>     ("10000"),
+        TERM_RCAL_OVRD                          =>     ('0'),
+        TST_RSV                                 =>     (x"00000000"),
+        RX_CLK25_DIV                            =>     (5),
+        TX_CLK25_DIV                            =>     (5),
+        UCODEER_CLR                             =>     ('0'),
+
+       ---------------------------PCI Express Attributes----------------------------
+        PCS_PCIE_EN                             =>     ("FALSE"),
+
+       ---------------------------PCS Attributes----------------------------
+        PCS_RSVD_ATTR                           =>     (PCS_RSVD_ATTR_IN),
+
+       -------------RX Buffer Attributes------------
+        RXBUF_ADDR_MODE                         =>     ("FAST"),
+        RXBUF_EIDLE_HI_CNT                      =>     ("1000"),
+        RXBUF_EIDLE_LO_CNT                      =>     ("0000"),
+        RXBUF_EN                                =>     ("FALSE"),
+        RX_BUFFER_CFG                           =>     ("000000"),
+        RXBUF_RESET_ON_CB_CHANGE                =>     ("TRUE"),
+        RXBUF_RESET_ON_COMMAALIGN               =>     ("FALSE"),
+        RXBUF_RESET_ON_EIDLE                    =>     ("FALSE"),
+        RXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        RXBUFRESET_TIME                         =>     ("00001"),
+        RXBUF_THRESH_OVFLW                      =>     (61),
+        RXBUF_THRESH_OVRD                       =>     ("FALSE"),
+        RXBUF_THRESH_UNDFLW                     =>     (4),
+        RXDLY_CFG                               =>     (x"001F"),
+        RXDLY_LCFG                              =>     (x"030"),
+        RXDLY_TAP_CFG                           =>     (x"0000"),
+        RXPH_CFG                                =>     (x"000000"),
+        RXPHDLY_CFG                             =>     (x"084020"),
+        RXPH_MONITOR_SEL                        =>     ("00000"),
+        RX_XCLK_SEL                             =>     ("RXUSR"),
+        RX_DDI_SEL                              =>     ("000000"),
+        RX_DEFER_RESET_BUF_EN                   =>     ("TRUE"),
+
+       -----------------------CDR Attributes-------------------------
+
+       --For Display Port, HBR/RBR- set RXCDR_CFG=72'h0380008bff40200008
+
+       --For Display Port, HBR2 -   set RXCDR_CFG=72'h038c008bff20200010
+
+       --For SATA Gen1 GTX- set RXCDR_CFG=72'h03_8000_8BFF_4010_0008
+
+       --For SATA Gen2 GTX- set RXCDR_CFG=72'h03_8800_8BFF_4020_0008
+
+       --For SATA Gen3 GTX- set RXCDR_CFG=72'h03_8000_8BFF_1020_0010
+
+       --For SATA Gen3 GTP- set RXCDR_CFG=83'h0_0000_87FE_2060_2444_1010
+
+       --For SATA Gen2 GTP- set RXCDR_CFG=83'h0_0000_47FE_2060_2448_1010
+
+       --For SATA Gen1 GTP- set RXCDR_CFG=83'h0_0000_47FE_1060_2448_1010
+        RXCDR_CFG                               =>     (x"03000023ff10200020"),
+        RXCDR_FR_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_HOLD_DURING_EIDLE                 =>     ('0'),
+        RXCDR_PH_RESET_ON_EIDLE                 =>     ('0'),
+        RXCDR_LOCK_CFG                          =>     ("010101"),
+
+       -------------------RX Initialization and Reset Attributes-------------------
+        RXCDRFREQRESET_TIME                     =>     ("00001"),
+        RXCDRPHRESET_TIME                       =>     ("00001"),
+        RXISCANRESET_TIME                       =>     ("00001"),
+        RXPCSRESET_TIME                         =>     ("00001"),
+        RXPMARESET_TIME                         =>     ("00011"),
+
+       -------------------RX OOB Signaling Attributes-------------------
+        RXOOB_CFG                               =>     ("0000110"),
+
+       -------------------------RX Gearbox Attributes---------------------------
+        RXGEARBOX_EN                            =>     ("FALSE"),
+        GEARBOX_MODE                            =>     ("000"),
+
+       -------------------------PRBS Detection Attribute-----------------------
+        RXPRBS_ERR_LOOPBACK                     =>     ('0'),
+
+       -------------Power-Down Attributes----------
+        PD_TRANS_TIME_FROM_P2                   =>     (x"03c"),
+        PD_TRANS_TIME_NONE_P2                   =>     (x"3c"),
+        PD_TRANS_TIME_TO_P2                     =>     (x"64"),
+
+       -------------RX OOB Signaling Attributes----------
+        SAS_MAX_COM                             =>     (64),
+        SAS_MIN_COM                             =>     (36),
+        SATA_BURST_SEQ_LEN                      =>     ("0101"),
+        SATA_BURST_VAL                          =>     ("100"),
+        SATA_EIDLE_VAL                          =>     ("100"),
+        SATA_MAX_BURST                          =>     (8),
+        SATA_MAX_INIT                           =>     (21),
+        SATA_MAX_WAKE                           =>     (7),
+        SATA_MIN_BURST                          =>     (4),
+        SATA_MIN_INIT                           =>     (12),
+        SATA_MIN_WAKE                           =>     (4),
+
+       -------------RX Fabric Clock Output Control Attributes----------
+        TRANS_TIME_RATE                         =>     (x"0E"),
+
+       --------------TX Buffer Attributes----------------
+        TXBUF_EN                                =>     ("FALSE"),
+        TXBUF_RESET_ON_RATE_CHANGE              =>     ("TRUE"),
+        TXDLY_CFG                               =>     (x"001F"),
+        TXDLY_LCFG                              =>     (x"030"),
+        TXDLY_TAP_CFG                           =>     (x"0000"),
+        TXPH_CFG                                =>     (x"0780"),
+        TXPHDLY_CFG                             =>     (x"084020"),
+        TXPH_MONITOR_SEL                        =>     ("00000"),
+        TX_XCLK_SEL                             =>     ("TXUSR"),
+
+       -------------------------FPGA TX Interface Attributes-------------------------
+        TX_DATA_WIDTH                           =>     (20),
+
+       -------------------------TX Configurable Driver Attributes-------------------------
+        TX_DEEMPH0                              =>     ("00000"),
+        TX_DEEMPH1                              =>     ("00000"),
+        TX_EIDLE_ASSERT_DELAY                   =>     ("110"),
+        TX_EIDLE_DEASSERT_DELAY                 =>     ("100"),
+        TX_LOOPBACK_DRIVE_HIZ                   =>     ("FALSE"),
+        TX_MAINCURSOR_SEL                       =>     ('0'),
+        TX_DRIVE_MODE                           =>     ("DIRECT"),
+        TX_MARGIN_FULL_0                        =>     ("1001110"),
+        TX_MARGIN_FULL_1                        =>     ("1001001"),
+        TX_MARGIN_FULL_2                        =>     ("1000101"),
+        TX_MARGIN_FULL_3                        =>     ("1000010"),
+        TX_MARGIN_FULL_4                        =>     ("1000000"),
+        TX_MARGIN_LOW_0                         =>     ("1000110"),
+        TX_MARGIN_LOW_1                         =>     ("1000100"),
+        TX_MARGIN_LOW_2                         =>     ("1000010"),
+        TX_MARGIN_LOW_3                         =>     ("1000000"),
+        TX_MARGIN_LOW_4                         =>     ("1000000"),
+
+       -------------------------TX Gearbox Attributes--------------------------
+        TXGEARBOX_EN                            =>     ("FALSE"),
+
+       -------------------------TX Initialization and Reset Attributes--------------------------
+        TXPCSRESET_TIME                         =>     ("00001"),
+        TXPMARESET_TIME                         =>     ("00001"),
+
+       -------------------------TX Receiver Detection Attributes--------------------------
+        TX_RXDETECT_CFG                         =>     (x"1832"),
+        TX_RXDETECT_REF                         =>     ("100"),
+
+       ----------------------------CPLL Attributes----------------------------
+        CPLL_CFG                                =>     (x"BC07DC"),
+        CPLL_FBDIV                              =>     (4),
+        CPLL_FBDIV_45                           =>     (4),
+        CPLL_INIT_CFG                           =>     (x"00001E"),
+        CPLL_LOCK_CFG                           =>     (x"01E8"),
+        CPLL_REFCLK_DIV                         =>     (1),
+        RXOUT_DIV                               =>     (2),
+        TXOUT_DIV                               =>     (2),
+        SATA_CPLL_CFG                           =>     ("VCO_3000MHZ"),
+
+       --------------RX Initialization and Reset Attributes-------------
+        RXDFELPMRESET_TIME                      =>     ("0001111"),
+
+       --------------RX Equalizer Attributes-------------
+        RXLPM_HF_CFG                            =>     ("00000011110000"),
+        RXLPM_LF_CFG                            =>     ("00000011110000"),
+        RX_DFE_GAIN_CFG                         =>     (x"020FEA"),
+        RX_DFE_H2_CFG                           =>     ("000000000000"),
+        RX_DFE_H3_CFG                           =>     ("000001000000"),
+        RX_DFE_H4_CFG                           =>     ("00011110000"),
+        RX_DFE_H5_CFG                           =>     ("00011100000"),
+        RX_DFE_KL_CFG                           =>     ("0000011111110"),
+        RX_DFE_LPM_CFG                          =>     (x"0904"),
+        RX_DFE_LPM_HOLD_DURING_EIDLE            =>     ('0'),
+        RX_DFE_UT_CFG                           =>     ("10001111000000000"),
+        RX_DFE_VP_CFG                           =>     ("00011111100000011"),
+
+       -------------------------Power-Down Attributes-------------------------
+        RX_CLKMUX_PD                            =>     ('1'),
+        TX_CLKMUX_PD                            =>     ('1'),
+
+       -------------------------FPGA RX Interface Attribute-------------------------
+        RX_INT_DATAWIDTH                        =>     (0),
+
+       -------------------------FPGA TX Interface Attribute-------------------------
+        TX_INT_DATAWIDTH                        =>     (0),
+
+       ------------------TX Configurable Driver Attributes---------------
+        TX_QPI_STATUS_EN                        =>     ('0'),
+
+       -------------------------RX Equalizer Attributes--------------------------
+        RX_DFE_KL_CFG2                          =>     (RX_DFE_KL_CFG2_IN),
+        RX_DFE_XYD_CFG                          =>     ("0000000000000"),
+
+       -------------------------TX Configurable Driver Attributes--------------------------
+        TX_PREDRIVER_MODE                       =>     ('0')
+
+
+    )
+    port map
+    (
+        --------------------------------- CPLL Ports -------------------------------
+        CPLLFBCLKLOST                   =>      cpllfbclklost_out,
+        CPLLLOCK                        =>      cplllock_out,
+        CPLLLOCKDETCLK                  =>      cplllockdetclk_in,
+        CPLLLOCKEN                      =>      tied_to_vcc_i,
+        CPLLPD                          =>      cpllpd_in,
+        CPLLREFCLKLOST                  =>      cpllrefclklost_out,
+        CPLLREFCLKSEL                   =>      cpllrefclksel_in,
+        CPLLRESET                       =>      cpllreset_in,
+        GTRSVD                          =>      "0000000000000000",
+        PCSRSVDIN                       =>      "0000000000000000",
+        PCSRSVDIN2                      =>      "00000",
+        PMARSVDIN                       =>      "00000",
+        PMARSVDIN2                      =>      "00000",
+        TSTIN                           =>      "11111111111111111111",
+        TSTOUT                          =>      open,
+        ---------------------------------- Channel ---------------------------------
+        CLKRSVD                         =>      tied_to_ground_vec_i(3 downto 0),
+        -------------------------- Channel - Clocking Ports ------------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      gtrefclk0_in,
+        GTREFCLK1                       =>      gtrefclk1_in,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        DRPADDR                         =>      drpaddr_in,
+        DRPCLK                          =>      drpclk_in,
+        DRPDI                           =>      drpdi_in,
+        DRPDO                           =>      drpdo_out,
+        DRPEN                           =>      drpen_in,
+        DRPRDY                          =>      drprdy_out,
+        DRPWE                           =>      drpwe_in,
+        ------------------------------- Clocking Ports -----------------------------
+        GTREFCLKMONITOR                 =>      open,
+        QPLLCLK                         =>      qpllclk_in,
+        QPLLREFCLK                      =>      qpllrefclk_in,
+        RXSYSCLKSEL                     =>      "00",
+        TXSYSCLKSEL                     =>      "00",
+        --------------------------- Digital Monitor Ports --------------------------
+        DMONITOROUT                     =>      dmonitorout_out,
+        ----------------- FPGA TX Interface Datapath Configuration  ----------------
+        TX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------------------- Loopback Ports -----------------------------
+        LOOPBACK                        =>      tied_to_ground_vec_i(2 downto 0),
+        ----------------------------- PCI Express Ports ----------------------------
+        PHYSTATUS                       =>      open,
+        RXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        RXVALID                         =>      open,
+        ------------------------------ Power-Down Ports ----------------------------
+        RXPD                            =>      "00",
+        TXPD                            =>      "00",
+        -------------------------- RX 8B/10B Decoder Ports -------------------------
+        SETERRSTATUS                    =>      tied_to_ground_i,
+        --------------------- RX Initialization and Reset Ports --------------------
+        EYESCANRESET                    =>      eyescanreset_in,
+        RXUSERRDY                       =>      rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        EYESCANDATAERROR                =>      eyescandataerror_out,
+        EYESCANMODE                     =>      tied_to_ground_i,
+        EYESCANTRIGGER                  =>      eyescantrigger_in,
+        ------------------------- Receive Ports - CDR Ports ------------------------
+        RXCDRFREQRESET                  =>      tied_to_ground_i,
+        RXCDRHOLD                       =>      tied_to_ground_i,
+        RXCDRLOCK                       =>      RXCDRLOCK_OUT, --// Modified
+        RXCDROVRDEN                     =>      tied_to_ground_i,
+        RXCDRRESET                      =>      RXCDRRESET_IN, --// Modified
+        RXCDRRESETRSV                   =>      tied_to_ground_i,
+        ------------------- Receive Ports - Clock Correction Ports -----------------
+        RXCLKCORCNT                     =>      open,
+        ---------- Receive Ports - FPGA RX Interface Datapath Configuration --------
+        RX8B10BEN                       =>      tied_to_vcc_i,
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        RXUSRCLK                        =>      rxusrclk_in,
+        RXUSRCLK2                       =>      rxusrclk2_in,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        RXDATA                          =>      rxdata_i,
+        ------------------- Receive Ports - Pattern Checker Ports ------------------
+        RXPRBSERR                       =>      open,
+        RXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ------------------- Receive Ports - Pattern Checker ports ------------------
+        RXPRBSCNTRESET                  =>      tied_to_ground_i,
+        -------------------- Receive Ports - RX  Equalizer Ports -------------------
+        RXDFEXYDEN                      =>      tied_to_vcc_i,
+        RXDFEXYDHOLD                    =>      tied_to_ground_i,
+        RXDFEXYDOVRDEN                  =>      tied_to_ground_i,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        RXDISPERR(7 downto 2)           =>      rxdisperr_float_i,
+        RXDISPERR(1 downto 0)           =>      rxdisperr_out,
+        RXNOTINTABLE(7 downto 2)        =>      rxnotintable_float_i,
+        RXNOTINTABLE(1 downto 0)        =>      rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        GTXRXP                          =>      gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        GTXRXN                          =>      gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        RXBUFRESET                      =>      tied_to_ground_i,
+        RXBUFSTATUS                     =>      open,
+        RXDDIEN                         =>      tied_to_vcc_i,
+        RXDLYBYPASS                     =>      tied_to_ground_i,
+        RXDLYEN                         =>      rxdlyen_in,
+        RXDLYOVRDEN                     =>      tied_to_ground_i,
+        RXDLYSRESET                     =>      rxdlysreset_in,
+        RXDLYSRESETDONE                 =>      rxdlysresetdone_out,
+        RXPHALIGN                       =>      rxphalign_in,
+        RXPHALIGNDONE                   =>      rxphaligndone_out,
+        RXPHALIGNEN                     =>      rxphalignen_in,
+        RXPHDLYPD                       =>      tied_to_ground_i,
+        RXPHDLYRESET                    =>      rxphdlyreset_in,
+        RXPHMONITOR                     =>      rxphmonitor_out,
+        RXPHOVRDEN                      =>      tied_to_ground_i,
+        RXPHSLIPMONITOR                 =>      rxphslipmonitor_out,
+        RXSTATUS                        =>      open,
+        -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
+        RXBYTEISALIGNED                 =>      open,
+        RXBYTEREALIGN                   =>      open,
+        RXCOMMADET                      =>      open,
+        RXCOMMADETEN                    =>      tied_to_vcc_i,
+        RXMCOMMAALIGNEN                 =>      tied_to_vcc_i,
+        RXPCOMMAALIGNEN                 =>      tied_to_vcc_i,
+        ------------------ Receive Ports - RX Channel Bonding Ports ----------------
+        RXCHANBONDSEQ                   =>      open,
+        RXCHBONDEN                      =>      tied_to_ground_i,
+        RXCHBONDLEVEL                   =>      tied_to_ground_vec_i(2 downto 0),
+        RXCHBONDMASTER                  =>      tied_to_ground_i,
+        RXCHBONDO                       =>      open,
+        RXCHBONDSLAVE                   =>      tied_to_ground_i,
+        ----------------- Receive Ports - RX Channel Bonding Ports  ----------------
+        RXCHANISALIGNED                 =>      open,
+        RXCHANREALIGN                   =>      open,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        RXLPMHFHOLD                     =>      rxlpmhfhold_in,
+        RXLPMHFOVRDEN                   =>      tied_to_ground_i,
+        RXLPMLFHOLD                     =>      rxlpmlfhold_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        RXDFEAGCHOLD                    =>      tied_to_ground_i,
+        RXDFEAGCOVRDEN                  =>      tied_to_ground_i,
+        RXDFECM1EN                      =>      tied_to_ground_i,
+        RXDFELFHOLD                     =>      tied_to_ground_i,
+        RXDFELFOVRDEN                   =>      tied_to_ground_i,
+        RXDFELPMRESET                   =>      rxdfelpmreset_in,
+        RXDFETAP2HOLD                   =>      tied_to_ground_i,
+        RXDFETAP2OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP3HOLD                   =>      tied_to_ground_i,
+        RXDFETAP3OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP4HOLD                   =>      tied_to_ground_i,
+        RXDFETAP4OVRDEN                 =>      tied_to_ground_i,
+        RXDFETAP5HOLD                   =>      tied_to_ground_i,
+        RXDFETAP5OVRDEN                 =>      tied_to_ground_i,
+        RXDFEUTHOLD                     =>      tied_to_ground_i,
+        RXDFEUTOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVPHOLD                     =>      tied_to_ground_i,
+        RXDFEVPOVRDEN                   =>      tied_to_ground_i,
+        RXDFEVSEN                       =>      tied_to_ground_i,
+        RXLPMLFKLOVRDEN                 =>      tied_to_ground_i,
+        RXMONITOROUT                    =>      rxmonitorout_out,
+        RXMONITORSEL                    =>      rxmonitorsel_in,
+        RXOSHOLD                        =>      tied_to_ground_i,
+        RXOSOVRDEN                      =>      tied_to_ground_i,
+        ------------ Receive Ports - RX Fabric ClocK Output Control Ports ----------
+        RXRATEDONE                      =>      open,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        RXOUTCLK                        =>      rxoutclk_out,
+        RXOUTCLKFABRIC                  =>      open,
+        RXOUTCLKPCS                     =>      open,
+        RXOUTCLKSEL                     =>      "010",
+        ---------------------- Receive Ports - RX Gearbox Ports --------------------
+        RXDATAVALID                     =>      open,
+        RXHEADER                        =>      open,
+        RXHEADERVALID                   =>      open,
+        RXSTARTOFSEQ                    =>      open,
+        --------------------- Receive Ports - RX Gearbox Ports  --------------------
+        RXGEARBOXSLIP                   =>      tied_to_ground_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        GTRXRESET                       =>      gtrxreset_in,
+        RXOOBRESET                      =>      tied_to_ground_i,
+        RXPCSRESET                      =>      tied_to_ground_i,
+        RXPMARESET                      =>      rxpmareset_in,
+        ------------------ Receive Ports - RX Margin Analysis ports ----------------
+        RXLPMEN                         =>      tied_to_vcc_i,
+        ------------------- Receive Ports - RX OOB Signaling ports -----------------
+        RXCOMSASDET                     =>      open,
+        RXCOMWAKEDET                    =>      open,
+        ------------------ Receive Ports - RX OOB Signaling ports  -----------------
+        RXCOMINITDET                    =>      open,
+        ------------------ Receive Ports - RX OOB signalling Ports -----------------
+        RXELECIDLE                      =>      open,
+        RXELECIDLEMODE                  =>      "11",
+        ----------------- Receive Ports - RX Polarity Control Ports ----------------
+        RXPOLARITY                      =>      tied_to_ground_i,
+        ---------------------- Receive Ports - RX gearbox ports --------------------
+        RXSLIDE                         =>      tied_to_ground_i,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        RXCHARISCOMMA                   =>      open,
+        RXCHARISK(7 downto 2)           =>      rxcharisk_float_i,
+        RXCHARISK(1 downto 0)           =>      rxcharisk_out,
+        ------------------ Receive Ports - Rx Channel Bonding Ports ----------------
+        RXCHBONDI                       =>      "00000",
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        RXRESETDONE                     =>      rxresetdone_out,
+        -------------------------------- Rx AFE Ports ------------------------------
+        RXQPIEN                         =>      tied_to_ground_i,
+        RXQPISENN                       =>      open,
+        RXQPISENP                       =>      open,
+        --------------------------- TX Buffer Bypass Ports -------------------------
+        TXPHDLYTSTCLK                   =>      tied_to_ground_i,
+        ------------------------ TX Configurable Driver Ports ----------------------
+        TXPOSTCURSOR                    =>      "00000",
+        TXPOSTCURSORINV                 =>      tied_to_ground_i,
+        TXPRECURSOR                     =>      tied_to_ground_vec_i(4 downto 0),
+        TXPRECURSORINV                  =>      tied_to_ground_i,
+        TXQPIBIASEN                     =>      tied_to_ground_i,
+        TXQPISTRONGPDOWN                =>      tied_to_ground_i,
+        TXQPIWEAKPUP                    =>      tied_to_ground_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        CFGRESET                        =>      tied_to_ground_i,
+        GTTXRESET                       =>      gttxreset_in,
+        PCSRSVDOUT                      =>      open,
+        TXUSERRDY                       =>      txuserrdy_in,
+        ---------------------- Transceiver Reset Mode Operation --------------------
+        GTRESETSEL                      =>      tied_to_ground_i,
+        RESETOVRD                       =>      tied_to_ground_i,
+        ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
+        TXCHARDISPMODE                  =>      tied_to_ground_vec_i(7 downto 0),
+        TXCHARDISPVAL                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        TXUSRCLK                        =>      txusrclk_in,
+        TXUSRCLK2                       =>      txusrclk2_in,
+        --------------------- Transmit Ports - PCI Express Ports -------------------
+        TXELECIDLE                      =>      tied_to_ground_i,
+        TXMARGIN                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXRATE                          =>      tied_to_ground_vec_i(2 downto 0),
+        TXSWING                         =>      tied_to_ground_i,
+        ------------------ Transmit Ports - Pattern Generator Ports ----------------
+        TXPRBSFORCEERR                  =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        TXDLYBYPASS                     =>      tied_to_ground_i,
+        TXDLYEN                         =>      txdlyen_in,
+        TXDLYHOLD                       =>      tied_to_ground_i,
+        TXDLYOVRDEN                     =>      tied_to_ground_i,
+        TXDLYSRESET                     =>      txdlysreset_in,
+        TXDLYSRESETDONE                 =>      txdlysresetdone_out,
+        TXDLYUPDOWN                     =>      tied_to_ground_i,
+        TXPHALIGN                       =>      txphalign_in,
+        TXPHALIGNDONE                   =>      txphaligndone_out,
+        TXPHALIGNEN                     =>      txphalignen_in,
+        TXPHDLYPD                       =>      tied_to_ground_i,
+        TXPHDLYRESET                    =>      txphdlyreset_in,
+        TXPHINIT                        =>      txphinit_in,
+        TXPHINITDONE                    =>      txphinitdone_out,
+        TXPHOVRDEN                      =>      tied_to_ground_i,
+        ---------------------- Transmit Ports - TX Buffer Ports --------------------
+        TXBUFSTATUS                     =>      open,
+        --------------- Transmit Ports - TX Configurable Driver Ports --------------
+        TXBUFDIFFCTRL                   =>      "100",
+        TXDEEMPH                        =>      tied_to_ground_i,
+        TXDIFFCTRL                      =>      "1000",
+        TXDIFFPD                        =>      tied_to_ground_i,
+        TXINHIBIT                       =>      tied_to_ground_i,
+        TXMAINCURSOR                    =>      "0000000",
+        TXPISOPD                        =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        TXDATA                          =>      txdata_i,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        GTXTXN                          =>      gtxtxn_out,
+        GTXTXP                          =>      gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        TXOUTCLK                        =>      txoutclk_out,
+        TXOUTCLKFABRIC                  =>      txoutclkfabric_out,
+        TXOUTCLKPCS                     =>      txoutclkpcs_out,
+        TXOUTCLKSEL                     =>      "011",
+        TXRATEDONE                      =>      open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        TXCHARISK(7 downto 2)           =>      tied_to_ground_vec_i(5 downto 0),
+        TXCHARISK(1 downto 0)           =>      txcharisk_in,
+        TXGEARBOXREADY                  =>      open,
+        TXHEADER                        =>      tied_to_ground_vec_i(2 downto 0),
+        TXSEQUENCE                      =>      tied_to_ground_vec_i(6 downto 0),
+        TXSTARTSEQ                      =>      tied_to_ground_i,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        TXPCSRESET                      =>      tied_to_ground_i,
+        TXPMARESET                      =>      tied_to_ground_i,
+        TXRESETDONE                     =>      txresetdone_out,
+        ------------------ Transmit Ports - TX OOB signalling Ports ----------------
+        TXCOMFINISH                     =>      open,
+        TXCOMINIT                       =>      tied_to_ground_i,
+        TXCOMSAS                        =>      tied_to_ground_i,
+        TXCOMWAKE                       =>      tied_to_ground_i,
+        TXPDELECIDLEMODE                =>      tied_to_ground_i,
+        ----------------- Transmit Ports - TX Polarity Control Ports ---------------
+        TXPOLARITY                      =>      tied_to_ground_i,
+        --------------- Transmit Ports - TX Receiver Detection Ports  --------------
+        TXDETECTRX                      =>      tied_to_ground_i,
+        ------------------ Transmit Ports - TX8b/10b Encoder Ports -----------------
+        TX8B10BBYPASS                   =>      tied_to_ground_vec_i(7 downto 0),
+        ------------------ Transmit Ports - pattern Generator Ports ----------------
+        TXPRBSSEL                       =>      tied_to_ground_vec_i(2 downto 0),
+        ----------------------- Tx Configurable Driver  Ports ----------------------
+        TXQPISENN                       =>      open,
+        TXQPISENP                       =>      open
+
+     );
+
+
+ end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_init.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_init.vhd
new file mode 100644
index 0000000..35ec4b5
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_init.vhd
@@ -0,0 +1,885 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_trb3_sync_2gb_init.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_trb3_sync_2gb_init
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration************************
+
+entity GTX_trb3_sync_2gb_init is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    EXAMPLE_SIMULATION                      : integer   := 0;          -- Set to 1 for simulation
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+ 
+    STABLE_CLOCK_PERIOD                     : integer   := 10;  
+        -- Set to 1 for simulation
+    EXAMPLE_USE_CHIPSCOPE                   : integer   := 1   --// Modified         -- Set to 1 to use Chipscope to drive resets
+
+);
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end GTX_trb3_sync_2gb_init;
+    
+architecture RTL of GTX_trb3_sync_2gb_init is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+
+component GTX_trb3_sync_2gb_multi_gt 
+generic
+(
+    -- Simulation attributes
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+    WRAPPER_SIM_GTRESET_SPEEDUP    : string    := "FALSE" -- Set to "TRUE" to speed up sim reset
+
+);
+port
+(
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllrefclklost_out                  : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxdlyen_in                          : in   std_logic;
+    gt0_rxdlysreset_in                      : in   std_logic;
+    gt0_rxdlysresetdone_out                 : out  std_logic;
+    gt0_rxphalign_in                        : in   std_logic;
+    gt0_rxphaligndone_out                   : out  std_logic;
+    gt0_rxphalignen_in                      : in   std_logic;
+    gt0_rxphdlyreset_in                     : in   std_logic;
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    gt0_rxlpmhfhold_in                      : in   std_logic;
+    gt0_rxlpmlfhold_in                      : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    gt0_txdlyen_in                          : in   std_logic;
+    gt0_txdlysreset_in                      : in   std_logic;
+    gt0_txdlysresetdone_out                 : out  std_logic;
+    gt0_txphalign_in                        : in   std_logic;
+    gt0_txphaligndone_out                   : out  std_logic;
+    gt0_txphalignen_in                      : in   std_logic;
+    gt0_txphdlyreset_in                     : in   std_logic;
+    gt0_txphinit_in                         : in   std_logic;
+    gt0_txphinitdone_out                    : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+   
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN : in  std_logic;
+     GT0_QPLLOUTREFCLK_IN : in  std_logic 
+
+);
+end component;
+
+component GTX_trb3_sync_2gb_TX_STARTUP_FSM
+  Generic(
+           EXAMPLE_SIMULATION       : integer := 0;
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient              
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           TXUSERCLK                : in  STD_LOGIC;              --TXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;              --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;              --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;              --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the CPLL of the GT
+           TXRESETDONE              : in  STD_LOGIC;      
+           MMCM_LOCK                : in  STD_LOGIC;      
+           GTTXRESET                : out STD_LOGIC:='0';      
+           MMCM_RESET               : out STD_LOGIC:='0';      
+           QPLL_RESET               : out STD_LOGIC:='0';        --Reset QPLL
+           CPLL_RESET               : out STD_LOGIC:='0';        --Reset CPLL
+           TX_FSM_RESET_DONE        : out STD_LOGIC:='0';        --Reset-sequence has sucessfully been finished.
+           TXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC:='0';
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';
+           PHALIGNMENT_DONE         : in  STD_LOGIC;
+           
+           RETRY_COUNTER            : out  STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end component;
+
+component GTX_trb3_sync_2gb_RX_STARTUP_FSM
+  Generic(
+           EXAMPLE_SIMULATION       : integer := 0;
+           EQ_MODE                  : string := "DFE";
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient                         
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;        --Stable Clock, either a stable clock from the PCB
+                                                            --or reference-clock present at startup.
+           RXUSERCLK                : in  STD_LOGIC;        --RXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;        --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;        --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;        --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the CPLL of the GT
+           RXRESETDONE              : in  STD_LOGIC;
+           MMCM_LOCK                : in  STD_LOGIC;
+           RECCLK_STABLE            : in  STD_LOGIC;
+           RECCLK_MONITOR_RESTART   : in  STD_LOGIC;
+           DATA_VALID               : in  STD_LOGIC;
+           TXUSERRDY                : in  STD_LOGIC;       --TXUSERRDY from GT 
+           DONT_RESET_ON_DATA_ERROR : in  STD_LOGIC;
+           GTRXRESET                : out STD_LOGIC:='0';
+           MMCM_RESET               : out STD_LOGIC:='0';
+           QPLL_RESET               : out STD_LOGIC:='0';  --Reset QPLL (only if RX uses QPLL)
+           CPLL_RESET               : out STD_LOGIC:='0';  --Reset CPLL (only if RX uses CPLL)
+           RX_FSM_RESET_DONE        : out STD_LOGIC:='0';  --Reset-sequence has sucessfully been finished.
+           RXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC;
+           PHALIGNMENT_DONE         : in  STD_LOGIC; 
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';           
+           RXDFEAGCHOLD             : out STD_LOGIC;
+           RXDFELFHOLD              : out STD_LOGIC;
+           RXLPMLFHOLD              : out STD_LOGIC;
+           RXLPMHFHOLD              : out STD_LOGIC;
+           RETRY_COUNTER            : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end component;
+
+
+
+
+component GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN     
+    port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RUN_PHALIGNMENT          : in  STD_LOGIC;              --Signal from the main Reset-FSM to run the auto phase-alignment procedure
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC;              -- Auto phase-alignment performed sucessfully
+           PHALIGNDONE              : in  STD_LOGIC;              --\ Phase-alignment signals from and to the
+           DLYSRESET                : out STD_LOGIC;              -- |transceiver.
+           DLYSRESETDONE            : in  STD_LOGIC;              --/
+           RECCLKSTABLE             : in  STD_LOGIC               --/on the RX-side.
+           
+           );
+end component;
+
+
+component GTX_trb3_sync_2gb_TX_MANUAL_PHASE_ALIGN 
+  Generic( NUMBER_OF_LANES          : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
+           MASTER_LANE_ID           : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RESET_PHALIGNMENT        : in  STD_LOGIC;
+           RUN_PHALIGNMENT          : in  STD_LOGIC;
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Manual phase-alignment performed sucessfully  
+           TXDLYSRESET              : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXDLYSRESETDONE          : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXPHINIT                 : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXPHINITDONE             : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXPHALIGN                : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           TXPHALIGNDONE            : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           TXDLYEN                  : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+           );
+end component;
+
+component GTX_trb3_sync_2gb_RX_MANUAL_PHASE_ALIGN 
+  Generic( NUMBER_OF_LANES          : integer range 1 to 32:= 4;  -- Number of lanes that are controlled using this FSM.
+           MASTER_LANE_ID           : integer range 0 to 31:= 0   -- Number of the lane which is considered the master in manual phase-alignment
+         );     
+
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           RESET_PHALIGNMENT        : in  STD_LOGIC;
+           RUN_PHALIGNMENT          : in  STD_LOGIC;
+           PHASE_ALIGNMENT_DONE     : out STD_LOGIC := '0';       -- Manual phase-alignment performed sucessfully    
+           RXDLYSRESET              : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           RXDLYSRESETDONE          : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           RXPHALIGN                : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0');
+           RXPHALIGNDONE            : in  STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0);
+           RXDLYEN                  : out STD_LOGIC_VECTOR(NUMBER_OF_LANES-1 downto 0) := (others=> '0')
+           );
+end component;
+
+  function get_cdrlock_time(is_sim : in integer) return integer is
+    variable lock_time: integer;
+  begin
+    if (is_sim = 1) then
+      lock_time := 1000;
+    else
+      lock_time := 50000 / integer(2); --Typical CDR lock time is 50,000UI as per DS183
+    end if;
+    return lock_time;
+  end function;
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+    constant RX_CDRLOCK_TIME      : integer := get_cdrlock_time(EXAMPLE_SIMULATION);       -- 200us
+    constant WAIT_TIME_CDRLOCK    : integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD;      -- 200 us time-out
+
+
+
+    -------------------------- GT Wrapper Wires ------------------------------
+    signal   gt0_txpmaresetdone_i            : std_logic;
+    signal   gt0_rxpmaresetdone_i            : std_logic;
+    signal   gt0_cpllreset_i                 : std_logic;
+    signal   gt0_cpllreset_t                 : std_logic;
+    signal   gt0_cpllrefclklost_i            : std_logic;
+    signal   gt0_cplllock_i                  : std_logic;
+    signal   gt0_txresetdone_i               : std_logic;
+    signal   gt0_rxresetdone_i               : std_logic;
+    signal   gt0_gttxreset_i                 : std_logic;
+    signal   gt0_gttxreset_t                 : std_logic;
+    signal   gt0_gtrxreset_i                 : std_logic;
+    signal   gt0_gtrxreset_t                 : std_logic;
+    signal   gt0_rxdfelpmreset_i             : std_logic;
+    signal   gt0_txuserrdy_i                 : std_logic;
+    signal   gt0_txuserrdy_t                 : std_logic;
+    signal   gt0_rxuserrdy_i                 : std_logic;
+    signal   gt0_rxuserrdy_t                 : std_logic;
+
+    signal   gt0_rxdfeagchold_i              : std_logic;
+    signal   gt0_rxdfelfhold_i               : std_logic;
+    signal   gt0_rxlpmlfhold_i               : std_logic;
+    signal   gt0_rxlpmhfhold_i               : std_logic;
+
+
+
+    signal   gt0_qpllreset_i                 : std_logic;
+    signal   gt0_qpllreset_t                 : std_logic;
+    signal   gt0_qpllrefclklost_i            : std_logic;
+    signal   gt0_qplllock_i                  : std_logic;
+
+
+    ------------------------------- Global Signals -----------------------------
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_vcc_i                   : std_logic;
+    signal   gt0_txphaligndone_i             : std_logic;
+    signal   gt0_txdlysreset_i               : std_logic;
+    signal   gt0_txdlysresetdone_i           : std_logic;
+    signal   gt0_txphdlyreset_i              : std_logic;
+    signal   gt0_txphalignen_i               : std_logic;
+    signal   gt0_txdlyen_i                   : std_logic;
+    signal   gt0_txphalign_i                 : std_logic;
+    signal   gt0_txphinit_i                  : std_logic;
+    signal   gt0_txphinitdone_i              : std_logic;
+    signal   gt0_run_tx_phalignment_i        : std_logic;
+    signal   gt0_rst_tx_phalignment_i        : std_logic;
+    signal   gt0_tx_phalignment_done_i       : std_logic;
+
+    signal   gt0_txoutclk_i                  : std_logic;
+    signal   gt0_rxoutclk_i                  : std_logic;
+    signal   gt0_rxoutclk_i2                 : std_logic;
+    signal   gt0_txoutclk_i2                 : std_logic;
+    signal   gt0_recclk_stable_i             : std_logic;
+    signal   gt0_rx_cdrlocked                : std_logic;
+    signal   gt0_rx_cdrlock_counter  :   integer range 0 to WAIT_TIME_CDRLOCK:= 0 ;
+    signal   gt0_rxphaligndone_i             : std_logic;
+    signal   gt0_rxdlysreset_i               : std_logic;
+    signal   gt0_rxdlysresetdone_i           : std_logic;
+    signal   gt0_rxphdlyreset_i              : std_logic;
+    signal   gt0_rxphalignen_i               : std_logic;
+    signal   gt0_rxdlyen_i                   : std_logic;
+    signal   gt0_rxphalign_i                 : std_logic;
+    signal   gt0_run_rx_phalignment_i        : std_logic;
+    signal   gt0_rst_rx_phalignment_i        : std_logic;
+    signal   gt0_rx_phalignment_done_i       : std_logic;
+
+
+
+    --------------------------- TX Buffer Bypass Signals --------------------
+    signal  mstr0_txsyncallin_i  :   std_logic;
+    signal  U0_TXDLYEN           :   std_logic_vector(0 downto 0);
+    signal  U0_TXDLYSRESET       :   std_logic_vector(0 downto 0);
+    signal  U0_TXDLYSRESETDONE   :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHINIT          :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHINITDONE      :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHALIGN         :   std_logic_vector(0 downto 0);
+    signal  U0_TXPHALIGNDONE     :   std_logic_vector(0 downto 0);
+    signal  U0_run_tx_phalignment_i :   std_logic;
+    signal  U0_rst_tx_phalignment_i :   std_logic;
+
+
+    --------------------------- RX Buffer Bypass Signals --------------------
+    signal   rxmstr0_rxsyncallin_i :   std_logic;
+    signal  U0_RXDLYEN           :   std_logic_vector(0 downto 0);
+    signal  U0_RXDLYSRESET       :   std_logic_vector(0 downto 0);
+    signal  U0_RXDLYSRESETDONE   :   std_logic_vector(0 downto 0);
+    signal  U0_RXPHALIGN         :   std_logic_vector(0 downto 0);
+    signal  U0_RXPHALIGNDONE     :   std_logic_vector(0 downto 0);
+    signal  U0_run_rx_phalignment_i :   std_logic;
+    signal  U0_rst_rx_phalignment_i :   std_logic;
+
+
+
+    signal      rx_cdrlocked                    : std_logic;
+
+
+ 
+
+
+--**************************** Main Body of Code *******************************
+begin
+    --  Static signal Assigments
+    tied_to_ground_i                             <= '0';
+    tied_to_vcc_i                                <= '1';
+
+    ----------------------------- The GT Wrapper -----------------------------
+    
+    -- Use the instantiation template in the example directory to add the GT wrapper to your design.
+    -- In this example, the wrapper is wired up for basic operation with a frame generator and frame 
+    -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is 
+    -- enabled, bonding should occur after alignment.
+
+
+    GTX_trb3_sync_2gb_i : GTX_trb3_sync_2gb_multi_gt
+    generic map
+    (
+        USE_BUFG                        =>      USE_BUFG,
+        WRAPPER_SIM_GTRESET_SPEEDUP     =>      EXAMPLE_SIM_GTRESET_SPEEDUP
+    )
+    port map
+    (
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y10)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_i,
+        gt0_cplllockdetclk_in           =>      gt0_cplllockdetclk_in,
+        gt0_cpllrefclklost_out          =>      gt0_cpllrefclklost_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_i,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      gt0_gtrefclk0_in,
+        gt0_gtrefclk1_in                =>      gt0_gtrefclk1_in,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      gt0_drpclk_in,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_i,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+		------------------------- Receive Ports - CDR Ports ------------------------
+		GT0_RXCDRRESET_IN               =>      GT0_RXCDRRESET_IN, --// Modified
+		GT0_RXCDRLOCK_OUT               =>      GT0_RXCDRLOCK_OUT, --// Modified
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_in,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_in,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxdlyen_in                  =>      gt0_rxdlyen_i,
+        gt0_rxdlysreset_in              =>      gt0_rxdlysreset_i,
+        gt0_rxdlysresetdone_out         =>      gt0_rxdlysresetdone_i,
+        gt0_rxphalign_in                =>      gt0_rxphalign_i,
+        gt0_rxphaligndone_out           =>      gt0_rxphaligndone_i,
+        gt0_rxphalignen_in              =>      gt0_rxphalignen_i,
+        gt0_rxphdlyreset_in             =>      gt0_rxphdlyreset_i,
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        gt0_rxlpmhfhold_in              =>      gt0_rxlpmhfhold_i,
+        gt0_rxlpmlfhold_in              =>      gt0_rxlpmlfhold_i,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_i,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_i,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_i,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_i,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_in,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_in,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        gt0_txdlyen_in                  =>      gt0_txdlyen_i,
+        gt0_txdlysreset_in              =>      gt0_txdlysreset_i,
+        gt0_txdlysresetdone_out         =>      gt0_txdlysresetdone_i,
+        gt0_txphalign_in                =>      gt0_txphalign_i,
+        gt0_txphaligndone_out           =>      gt0_txphaligndone_i,
+        gt0_txphalignen_in              =>      gt0_txphalignen_i,
+        gt0_txphdlyreset_in             =>      gt0_txphdlyreset_i,
+        gt0_txphinit_in                 =>      gt0_txphinit_i,
+        gt0_txphinitdone_out            =>      gt0_txphinitdone_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_i,
+
+
+
+
+    --____________________________COMMON PORTS________________________________
+        gt0_qplloutclk_in               =>      gt0_qplloutclk_in,
+        gt0_qplloutrefclk_in            =>      gt0_qplloutrefclk_in
+    );
+
+
+gt0_rxdfelpmreset_i                          <= tied_to_ground_i;
+
+
+GT0_CPLLLOCK_OUT                             <= gt0_cplllock_i;
+GT0_TXRESETDONE_OUT                          <= gt0_txresetdone_i;
+GT0_RXRESETDONE_OUT                          <= gt0_rxresetdone_i;
+GT0_RXOUTCLK_OUT                             <= gt0_rxoutclk_i;
+GT0_TXOUTCLK_OUT                             <= gt0_txoutclk_i;
+
+chipscope : if EXAMPLE_USE_CHIPSCOPE = 1 generate
+gt0_cpllreset_i                              <= GT0_CPLLRESET_IN or gt0_cpllreset_t;
+    gt0_gttxreset_i                              <= GT0_GTTXRESET_IN or gt0_gttxreset_t;
+    gt0_gtrxreset_i                              <= GT0_GTRXRESET_IN or gt0_gtrxreset_t;
+    gt0_txuserrdy_i                              <= GT0_TXUSERRDY_IN or gt0_txuserrdy_t;
+    gt0_rxuserrdy_i                              <= GT0_RXUSERRDY_IN or gt0_rxuserrdy_t;
+end generate chipscope;
+
+no_chipscope : if EXAMPLE_USE_CHIPSCOPE = 0 generate
+gt0_cpllreset_i                              <= gt0_cpllreset_t;
+gt0_gttxreset_i                              <= gt0_gttxreset_t;
+gt0_gtrxreset_i                              <= gt0_gtrxreset_t;
+gt0_txuserrdy_i                              <= gt0_txuserrdy_t;
+gt0_rxuserrdy_i                              <= gt0_rxuserrdy_t;
+end generate no_chipscope;
+
+
+gt0_txresetfsm_i:  GTX_trb3_sync_2gb_TX_STARTUP_FSM 
+
+  generic map(
+           EXAMPLE_SIMULATION       => EXAMPLE_SIMULATION,
+           STABLE_CLOCK_PERIOD      => STABLE_CLOCK_PERIOD,           -- Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   => 8, 
+           TX_QPLL_USED             => FALSE ,                       -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             => FALSE,                        -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   => TRUE                 -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                     -- is enough. For single-lane applications the automatic alignment is 
+                                                                     -- sufficient              
+             )     
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        TXUSERCLK                       =>      GT0_TXUSRCLK_IN,
+        SOFT_RESET                      =>      SOFT_RESET_TX_IN,
+        QPLLREFCLKLOST                  =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      gt0_cpllrefclklost_i,
+        QPLLLOCK                        =>      tied_to_vcc_i,
+        CPLLLOCK                        =>      gt0_cplllock_i,
+        TXRESETDONE                     =>      gt0_txresetdone_i,
+        MMCM_LOCK                       =>      GT0_TX_MMCM_LOCK_IN,
+        GTTXRESET                       =>      gt0_gttxreset_t,
+        MMCM_RESET                      =>      GT0_TX_MMCM_RESET_OUT,
+        QPLL_RESET                      =>      open,
+        CPLL_RESET                      =>      gt0_cpllreset_t,
+        TX_FSM_RESET_DONE               =>      GT0_TX_FSM_RESET_DONE_OUT,
+        TXUSERRDY                       =>      gt0_txuserrdy_t,
+        RUN_PHALIGNMENT                 =>      gt0_run_tx_phalignment_i,
+        RESET_PHALIGNMENT               =>      gt0_rst_tx_phalignment_i,
+        PHALIGNMENT_DONE                =>      gt0_tx_phalignment_done_i,
+        RETRY_COUNTER                   =>      open
+           );
+
+
+
+
+
+
+
+
+gt0_rxresetfsm_i:  GTX_trb3_sync_2gb_RX_STARTUP_FSM 
+
+  generic map(
+           EXAMPLE_SIMULATION       => EXAMPLE_SIMULATION,
+           EQ_MODE                  => "LPM",                 --Rx Equalization Mode - Set to DFE or LPM
+           STABLE_CLOCK_PERIOD      => STABLE_CLOCK_PERIOD,           --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   => 8, 
+           TX_QPLL_USED             => FALSE ,                       -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             => FALSE,                        -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   =>  FALSE                        -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                     -- is enough. For single-lane applications the automatic alignment is 
+                                                                     -- sufficient              
+             )     
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        RXUSERCLK                       =>      GT0_RXUSRCLK_IN,
+        SOFT_RESET                      =>      SOFT_RESET_RX_IN,
+        DONT_RESET_ON_DATA_ERROR        =>      DONT_RESET_ON_DATA_ERROR_IN,
+        QPLLREFCLKLOST                  =>      tied_to_ground_i,
+        CPLLREFCLKLOST                  =>      gt0_cpllrefclklost_i,
+        QPLLLOCK                        =>      tied_to_vcc_i,
+        CPLLLOCK                        =>      gt0_cplllock_i,
+        RXRESETDONE                     =>      gt0_rxresetdone_i,
+        MMCM_LOCK                       =>      tied_to_vcc_i,
+        RECCLK_STABLE                   =>      gt0_recclk_stable_i,
+        RECCLK_MONITOR_RESTART          =>      tied_to_ground_i,
+        DATA_VALID                      =>      GT0_DATA_VALID_IN,
+        TXUSERRDY                       =>      tied_to_vcc_i,
+        GTRXRESET                       =>      gt0_gtrxreset_t,
+        MMCM_RESET                      =>      open,
+        QPLL_RESET                      =>      open,
+        CPLL_RESET                      =>      open,
+        RX_FSM_RESET_DONE               =>      GT0_RX_FSM_RESET_DONE_OUT,
+        RXUSERRDY                       =>      gt0_rxuserrdy_t,
+        RUN_PHALIGNMENT                 =>      gt0_run_rx_phalignment_i,
+        RESET_PHALIGNMENT               =>      gt0_rst_rx_phalignment_i,
+        PHALIGNMENT_DONE                =>      gt0_rx_phalignment_done_i,
+        RXDFEAGCHOLD                    =>      gt0_rxdfeagchold_i,
+        RXDFELFHOLD                     =>      gt0_rxdfelfhold_i,
+        RXLPMLFHOLD                     =>      gt0_rxlpmlfhold_i,
+        RXLPMHFHOLD                     =>      gt0_rxlpmhfhold_i,
+        RETRY_COUNTER                   =>      open
+           );
+
+
+
+  gt0_cdrlock_timeout:process(SYSCLK_IN)
+  begin
+    if rising_edge(SYSCLK_IN) then
+        if(gt0_gtrxreset_i = '1') then
+          gt0_rx_cdrlocked       <= '0';
+          gt0_rx_cdrlock_counter <=  0                        after DLY;
+        elsif (gt0_rx_cdrlock_counter = WAIT_TIME_CDRLOCK) then
+          gt0_rx_cdrlocked       <= '1';
+          gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter        after DLY;
+        else
+          gt0_rx_cdrlock_counter <= gt0_rx_cdrlock_counter + 1    after DLY;
+        end if;
+    end if;
+  end process;
+
+gt0_recclk_stable_i                          <= gt0_rx_cdrlocked;
+
+
+
+    --------------------------- TX Buffer Bypass Logic --------------------
+    -- The TX SYNC Module drives the ports needed to Bypass the TX Buffer.
+    -- Include the TX SYNC module in your own design if TX Buffer is bypassed.
+
+
+--Auto
+gt0_txphdlyreset_i                           <= tied_to_ground_i;
+gt0_txphalignen_i                            <= tied_to_ground_i;
+gt0_txdlyen_i                                <= tied_to_ground_i;
+gt0_txphalign_i                              <= tied_to_ground_i;
+gt0_txphinit_i                               <= tied_to_ground_i;
+
+gt0_tx_auto_phase_align_i : GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN    
+    port map ( 
+        STABLE_CLOCK                    =>      SYSCLK_IN,
+        RUN_PHALIGNMENT                 =>      gt0_run_tx_phalignment_i,
+        PHASE_ALIGNMENT_DONE            =>      gt0_tx_phalignment_done_i,
+        PHALIGNDONE                     =>      gt0_txphaligndone_i,
+        DLYSRESET                       =>      gt0_txdlysreset_i,
+        DLYSRESETDONE                   =>      gt0_txdlysresetdone_i,
+        RECCLKSTABLE                    =>      tied_to_vcc_i
+           );
+
+
+
+
+   --------------------------- RX Buffer Bypass Logic --------------------
+--   The RX SYNC Module drives the ports needed to Bypass the RX Buffer.
+--   Include the RX SYNC module in your own design if RX Buffer is bypassed.
+
+
+--Auto
+--Auto
+gt0_rxphdlyreset_i                           <= '1'; --// Modified???????  tied_to_ground_i;
+gt0_rxphalignen_i                            <= '1'; --// Modified???????  tied_to_ground_i;
+gt0_rxdlyen_i                                <= tied_to_ground_i;
+gt0_rxphalign_i                              <= tied_to_ground_i;
+
+gt0_rx_phalignment_done_i <= '1'; --// Modified
+gt0_rxdlysreset_i <= '1'; --// Modified
+-- gt0_rx_auto_phase_align_i : GTX_trb3_sync_2gb_AUTO_PHASE_ALIGN    
+  -- port map ( 
+        -- STABLE_CLOCK                    =>      SYSCLK_IN,
+        -- RUN_PHALIGNMENT                 =>      gt0_run_rx_phalignment_i,
+        -- PHASE_ALIGNMENT_DONE            =>      gt0_rx_phalignment_done_i,
+        -- PHALIGNDONE                     =>      gt0_rxphaligndone_i,
+        -- DLYSRESET                       =>      gt0_rxdlysreset_i,
+        -- DLYSRESETDONE                   =>      gt0_rxdlysresetdone_i,
+        -- RECCLKSTABLE                    =>      gt0_recclk_stable_i
+     -- );
+
+
+
+end RTL;
+
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_multi_gt.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_multi_gt.vhd
new file mode 100644
index 0000000..9b4a7b6
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_multi_gt.vhd
@@ -0,0 +1,509 @@
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_trb3_sync_2gb_multi_gt.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_trb3_sync_2gb_multi_gt (a Multi GT Wrapper)
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+
+entity GTX_trb3_sync_2gb_multi_gt is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE";        -- Set to "TRUE" to speed up sim reset
+    RX_DFE_KL_CFG2_IN               : bit_vector :=  X"301148AC";
+    USE_BUFG                        : integer   := 0;          -- Set to 1 for bufg usage for cpll railing logic
+ 
+    PMA_RSV_IN                      : bit_vector :=  x"00018480"
+);
+port
+(
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X0Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllrefclklost_out                  : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxdlyen_in                          : in   std_logic;
+    gt0_rxdlysreset_in                      : in   std_logic;
+    gt0_rxdlysresetdone_out                 : out  std_logic;
+    gt0_rxphalign_in                        : in   std_logic;
+    gt0_rxphaligndone_out                   : out  std_logic;
+    gt0_rxphalignen_in                      : in   std_logic;
+    gt0_rxphdlyreset_in                     : in   std_logic;
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    gt0_rxlpmhfhold_in                      : in   std_logic;
+    gt0_rxlpmlfhold_in                      : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    gt0_txdlyen_in                          : in   std_logic;
+    gt0_txdlysreset_in                      : in   std_logic;
+    gt0_txdlysresetdone_out                 : out  std_logic;
+    gt0_txphalign_in                        : in   std_logic;
+    gt0_txphaligndone_out                   : out  std_logic;
+    gt0_txphalignen_in                      : in   std_logic;
+    gt0_txphdlyreset_in                     : in   std_logic;
+    gt0_txphinit_in                         : in   std_logic;
+    gt0_txphinitdone_out                    : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+
+end GTX_trb3_sync_2gb_multi_gt;
+    
+architecture RTL of GTX_trb3_sync_2gb_multi_gt is
+    attribute DowngradeIPIdentifiedWarnings: string;
+    attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_trb3_sync_2gb_multi_gt,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--***************************** Signal Declarations *****************************
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal   gt0_qplloutclk_i         :   std_logic;
+    signal   gt0_qplloutrefclk_i      :   std_logic;
+
+    signal  gt0_mgtrefclktx_i           :   std_logic_vector(1 downto 0);
+    signal  gt0_mgtrefclkrx_i           :   std_logic_vector(1 downto 0);
+ 
+    signal   gt0_qpllclk_i            :   std_logic;
+    signal   gt0_qpllrefclk_i         :   std_logic;
+    signal   gt0_cpllreset_i            :   std_logic;
+    signal   gt0_cpllpd_i         :   std_logic;
+    signal   cpll_reset0_i            :   std_logic;
+    signal   cpll_pd0_i         :   std_logic;
+
+--*************************** Component Declarations **************************
+component GTX_trb3_sync_2gb_GT
+generic
+(
+    -- Simulation attributes
+    GT_SIM_GTRESET_SPEEDUP       : string   := "FALSE";
+    RX_DFE_KL_CFG2_IN            : bit_vector :=   X"3010D90C";
+    PMA_RSV_IN                   : bit_vector :=   X"00000000";
+    SIM_CPLLREFCLK_SEL           : bit_vector :=   "001";
+    PCS_RSVD_ATTR_IN             : bit_vector :=   X"000000000000"
+);
+port 
+(   
+     cpllpd_in : in std_logic;
+     cpllrefclksel_in : in std_logic_vector (2 downto 0);
+    --------------------------------- CPLL Ports -------------------------------
+    cpllfbclklost_out                       : out  std_logic;
+    cplllock_out                            : out  std_logic;
+    cplllockdetclk_in                       : in   std_logic;
+    cpllrefclklost_out                      : out  std_logic;
+    cpllreset_in                            : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gtrefclk0_in                            : in   std_logic;
+    gtrefclk1_in                            : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    drpaddr_in                              : in   std_logic_vector(8 downto 0);
+    drpclk_in                               : in   std_logic;
+    drpdi_in                                : in   std_logic_vector(15 downto 0);
+    drpdo_out                               : out  std_logic_vector(15 downto 0);
+    drpen_in                                : in   std_logic;
+    drprdy_out                              : out  std_logic;
+    drpwe_in                                : in   std_logic;
+    ------------------------------- Clocking Ports -----------------------------
+    qpllclk_in                              : in   std_logic;
+    qpllrefclk_in                           : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    dmonitorout_out                         : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    eyescanreset_in                         : in   std_logic;
+    rxuserrdy_in                            : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    eyescandataerror_out                    : out  std_logic;
+    eyescantrigger_in                       : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	RXCDRRESET_IN                           : in  std_logic; --// Modified
+    RXCDRLOCK_OUT                           : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    rxusrclk_in                             : in   std_logic;
+    rxusrclk2_in                            : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    rxdata_out                              : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    rxdisperr_out                           : out  std_logic_vector(1 downto 0);
+    rxnotintable_out                        : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gtxrxp_in                               : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gtxrxn_in                               : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    rxdlyen_in                              : in   std_logic;
+    rxdlysreset_in                          : in   std_logic;
+    rxdlysresetdone_out                     : out  std_logic;
+    rxphalign_in                            : in   std_logic;
+    rxphaligndone_out                       : out  std_logic;
+    rxphalignen_in                          : in   std_logic;
+    rxphdlyreset_in                         : in   std_logic;
+    rxphmonitor_out                         : out  std_logic_vector(4 downto 0);
+    rxphslipmonitor_out                     : out  std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    rxlpmhfhold_in                          : in   std_logic;
+    rxlpmlfhold_in                          : in   std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    rxdfelpmreset_in                        : in   std_logic;
+    rxmonitorout_out                        : out  std_logic_vector(6 downto 0);
+    rxmonitorsel_in                         : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    rxoutclk_out                            : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gtrxreset_in                            : in   std_logic;
+    rxpmareset_in                           : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    rxcharisk_out                           : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    rxresetdone_out                         : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gttxreset_in                            : in   std_logic;
+    txuserrdy_in                            : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    txusrclk_in                             : in   std_logic;
+    txusrclk2_in                            : in   std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    txdlyen_in                              : in   std_logic;
+    txdlysreset_in                          : in   std_logic;
+    txdlysresetdone_out                     : out  std_logic;
+    txphalign_in                            : in   std_logic;
+    txphaligndone_out                       : out  std_logic;
+    txphalignen_in                          : in   std_logic;
+    txphdlyreset_in                         : in   std_logic;
+    txphinit_in                             : in   std_logic;
+    txphinitdone_out                        : out  std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    txdata_in                               : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gtxtxn_out                              : out  std_logic;
+    gtxtxp_out                              : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    txoutclk_out                            : out  std_logic;
+    txoutclkfabric_out                      : out  std_logic;
+    txoutclkpcs_out                         : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    txcharisk_in                            : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    txresetdone_out                         : out  std_logic
+
+
+);
+end component;
+component GTX_trb3_sync_2gb_cpll_railing
+  Generic(
+           USE_BUFG       : integer := 0
+);
+port 
+(   
+        cpll_reset_out : out std_logic;
+         cpll_pd_out : out std_logic;
+         refclk_out : out std_logic;
+        
+         refclk_in : in std_logic
+
+);
+end component;
+
+
+
+--********************************* Main Body of Code**************************
+
+begin                       
+
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    gt0_qpllclk_i    <= GT0_QPLLOUTCLK_IN;  
+    gt0_qpllrefclk_i <= GT0_QPLLOUTREFCLK_IN; 
+
+
+ 
+    --------------------------- GT Instances  -------------------------------   
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --GT0  (X0Y10)
+
+gt0_GTX_trb3_sync_2gb_i : GTX_trb3_sync_2gb_GT 
+    generic map
+    (
+        -- Simulation attributes
+        GT_SIM_GTRESET_SPEEDUP        =>  WRAPPER_SIM_GTRESET_SPEEDUP,
+        RX_DFE_KL_CFG2_IN             =>  RX_DFE_KL_CFG2_IN,
+        SIM_CPLLREFCLK_SEL            =>  "001",
+        PMA_RSV_IN                    =>  PMA_RSV_IN,
+        PCS_RSVD_ATTR_IN              =>  X"000000000000"
+    )
+    port map
+    (
+        cpllpd_in => gt0_cpllpd_i,
+        cpllrefclksel_in => "001",
+        --------------------------------- CPLL Ports -------------------------------
+        cpllfbclklost_out               =>      gt0_cpllfbclklost_out,
+        cplllock_out                    =>      gt0_cplllock_out,
+        cplllockdetclk_in               =>      gt0_cplllockdetclk_in,
+        cpllrefclklost_out              =>      gt0_cpllrefclklost_out,
+        cpllreset_in                    =>      gt0_cpllreset_i,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gtrefclk0_in                    =>      gt0_gtrefclk0_in,
+        gtrefclk1_in                    =>      gt0_gtrefclk1_in,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        drpaddr_in                      =>      gt0_drpaddr_in,
+        drpclk_in                       =>      gt0_drpclk_in,
+        drpdi_in                        =>      gt0_drpdi_in,
+        drpdo_out                       =>      gt0_drpdo_out,
+        drpen_in                        =>      gt0_drpen_in,
+        drprdy_out                      =>      gt0_drprdy_out,
+        drpwe_in                        =>      gt0_drpwe_in,
+        ------------------------------- Clocking Ports -----------------------------
+        qpllclk_in                      =>      gt0_qpllclk_i,
+        qpllrefclk_in                   =>      gt0_qpllrefclk_i,
+        --------------------------- Digital Monitor Ports --------------------------
+        dmonitorout_out                 =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        eyescanreset_in                 =>      gt0_eyescanreset_in,
+        rxuserrdy_in                    =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        eyescandataerror_out            =>      gt0_eyescandataerror_out,
+        eyescantrigger_in               =>      gt0_eyescantrigger_in,
+		------------------------- Receive Ports - CDR Ports ------------------------
+		RXCDRRESET_IN                   =>      GT0_RXCDRRESET_IN, --// Modified
+		RXCDRLOCK_OUT                   =>      GT0_RXCDRLOCK_OUT, --// Modified
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        rxusrclk_in                     =>      gt0_rxusrclk_in,
+        rxusrclk2_in                    =>      gt0_rxusrclk2_in,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        rxdata_out                      =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        rxdisperr_out                   =>      gt0_rxdisperr_out,
+        rxnotintable_out                =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gtxrxp_in                       =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gtxrxn_in                       =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        rxdlyen_in                      =>      gt0_rxdlyen_in,
+        rxdlysreset_in                  =>      gt0_rxdlysreset_in,
+        rxdlysresetdone_out             =>      gt0_rxdlysresetdone_out,
+        rxphalign_in                    =>      gt0_rxphalign_in,
+        rxphaligndone_out               =>      gt0_rxphaligndone_out,
+        rxphalignen_in                  =>      gt0_rxphalignen_in,
+        rxphdlyreset_in                 =>      gt0_rxphdlyreset_in,
+        rxphmonitor_out                 =>      gt0_rxphmonitor_out,
+        rxphslipmonitor_out             =>      gt0_rxphslipmonitor_out,
+        -------------------- Receive Ports - RX Equailizer Ports -------------------
+        rxlpmhfhold_in                  =>      gt0_rxlpmhfhold_in,
+        rxlpmlfhold_in                  =>      gt0_rxlpmlfhold_in,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        rxdfelpmreset_in                =>      gt0_rxdfelpmreset_in,
+        rxmonitorout_out                =>      gt0_rxmonitorout_out,
+        rxmonitorsel_in                 =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        rxoutclk_out                    =>      gt0_rxoutclk_out,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gtrxreset_in                    =>      gt0_gtrxreset_in,
+        rxpmareset_in                   =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        rxcharisk_out                   =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        rxresetdone_out                 =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gttxreset_in                    =>      gt0_gttxreset_in,
+        txuserrdy_in                    =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        txusrclk_in                     =>      gt0_txusrclk_in,
+        txusrclk2_in                    =>      gt0_txusrclk2_in,
+        ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+        txdlyen_in                      =>      gt0_txdlyen_in,
+        txdlysreset_in                  =>      gt0_txdlysreset_in,
+        txdlysresetdone_out             =>      gt0_txdlysresetdone_out,
+        txphalign_in                    =>      gt0_txphalign_in,
+        txphaligndone_out               =>      gt0_txphaligndone_out,
+        txphalignen_in                  =>      gt0_txphalignen_in,
+        txphdlyreset_in                 =>      gt0_txphdlyreset_in,
+        txphinit_in                     =>      gt0_txphinit_in,
+        txphinitdone_out                =>      gt0_txphinitdone_out,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        txdata_in                       =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gtxtxn_out                      =>      gt0_gtxtxn_out,
+        gtxtxp_out                      =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        txoutclk_out                    =>      gt0_txoutclk_out,
+        txoutclkfabric_out              =>      gt0_txoutclkfabric_out,
+        txoutclkpcs_out                 =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        txcharisk_in                    =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        txresetdone_out                 =>      gt0_txresetdone_out
+
+    );
+
+
+   cpll_railing0_i : GTX_trb3_sync_2gb_cpll_railing
+  generic map(
+           USE_BUFG       => USE_BUFG
+   ) 
+   port map
+   (
+        cpll_reset_out => cpll_reset0_i,
+        cpll_pd_out => cpll_pd0_i,
+        refclk_out => open,
+        refclk_in => gt0_gtrefclk0_in
+);
+
+
+gt0_cpllreset_i <= cpll_reset0_i or gt0_cpllreset_in; 
+gt0_cpllpd_i <= cpll_pd0_i ; 
+end RTL;     
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_rx_startup_fsm.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_rx_startup_fsm.vhd
new file mode 100644
index 0000000..9bb7fe7
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_rx_startup_fsm.vhd
@@ -0,0 +1,788 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 3.5
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename : gtx_trb3_sync_2gb_rx_startup_fsm.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--  Description :     This module performs RX reset and initialization.
+--                     
+--
+--
+-- Module GTX_trb3_sync_2gb_rx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_trb3_sync_2gb_RX_STARTUP_FSM is
+  Generic( EXAMPLE_SIMULATION       : integer := 0;
+           EQ_MODE                  : string  := "DFE";           --RX Equalisation Mode; set to DFE or LPM
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient                         
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;        --Stable Clock, either a stable clock from the PCB
+                                                            --or reference-clock present at startup.
+           RXUSERCLK                : in  STD_LOGIC;        --RXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;        --User Reset, can be pulled any time
+
+           QPLLREFCLKLOST           : in  STD_LOGIC;        --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;        --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;        --Lock Detect from the CPLL of the GT
+           RXRESETDONE              : in  STD_LOGIC;
+           MMCM_LOCK                : in  STD_LOGIC;
+           RECCLK_STABLE            : in  STD_LOGIC;
+           RECCLK_MONITOR_RESTART   : in  STD_LOGIC:='0';
+           DATA_VALID               : in  STD_LOGIC;
+           TXUSERRDY                : in  STD_LOGIC;       --TXUSERRDY from GT 
+           DONT_RESET_ON_DATA_ERROR : in  STD_LOGIC;       --Used to control the Auto-Reset of FSM when Data Error is detected
+           GTRXRESET                : out STD_LOGIC;
+           MMCM_RESET               : out STD_LOGIC;
+           QPLL_RESET               : out STD_LOGIC:='0';  --Reset QPLL (only if RX uses QPLL)
+           CPLL_RESET               : out STD_LOGIC:='0';  --Reset CPLL (only if RX uses CPLL)
+           RX_FSM_RESET_DONE        : out STD_LOGIC;       --Reset-sequence has sucessfully been finished.
+           RXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC;
+           PHALIGNMENT_DONE         : in  STD_LOGIC; 
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';           
+           RXDFEAGCHOLD             : out STD_LOGIC;
+           RXDFELFHOLD              : out STD_LOGIC;
+           RXLPMLFHOLD              : out STD_LOGIC;
+           RXLPMHFHOLD              : out STD_LOGIC;
+           RETRY_COUNTER            : out STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end GTX_trb3_sync_2gb_RX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+--   are calculated at design-time based on the Generics
+--   
+-- * if either of the PLLs is reset during TX-startup, it does not need to be reset again by RX
+--   => signal which PLL has been reset
+-- * 
+
+
+
+architecture RTL of GTX_trb3_sync_2gb_RX_STARTUP_FSM is
+
+  component GTX_trb3_sync_2gb_sync_block
+   generic (
+     INITIALISE : bit_vector(5 downto 0) := "000000"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+  type rx_rst_fsm_type is(
+    INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET, VERIFY_RECCLK_STABLE,
+    RELEASE_MMCM_RESET, WAIT_FOR_RXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+    MONITOR_DATA_VALID, FSM_DONE);
+    
+  signal rx_state : rx_rst_fsm_type := INIT;
+
+  constant MMCM_LOCK_CNT_MAX    : integer := 256;
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+  constant WAIT_TIMEOUT_2ms     : integer := 2000000 / STABLE_CLOCK_PERIOD;--  2 ms time-out
+  constant WAIT_TLOCK_MAX       : integer :=  100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_TIMEOUT_500us   : integer :=  500000 / STABLE_CLOCK_PERIOD;--500 us time-out
+  constant WAIT_TIMEOUT_1us     : integer :=  1000 / STABLE_CLOCK_PERIOD;  --1 us time-out
+  constant WAIT_TIMEOUT_100us    : integer := 100000 / STABLE_CLOCK_PERIOD; --100 us time-out
+  constant WAIT_TIME_ADAPT      : integer := (37000000 /integer(2))/STABLE_CLOCK_PERIOD;
+  constant WAIT_TIME_MAX    : integer := 100 ; --10 us time-out
+    
+  signal init_wait_count        : integer range 0 to WAIT_MAX:=0;
+  signal init_wait_done         : std_logic := '0';
+  signal pll_reset_asserted     : std_logic := '0';
+  signal rx_fsm_reset_done_int  : std_logic := '0';
+  signal rx_fsm_reset_done_int_s2  : std_logic := '0';
+  signal rx_fsm_reset_done_int_s3  : std_logic := '0';
+   
+  signal rxresetdone_s2         : std_logic := '0'; 
+  signal rxresetdone_s3         : std_logic := '0'; 
+
+  constant MAX_RETRIES          : integer := 2**RETRY_COUNTER_BITWIDTH-1; 
+  signal retry_counter_int      : integer range 0 to MAX_RETRIES := 0;  
+  signal time_out_counter       : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+  signal recclk_mon_restart_count : integer range 0 to 3:= 0;
+  signal recclk_mon_count_reset   : std_logic := '0';
+  
+  signal reset_time_out         : std_logic := '0';
+  signal time_out_2ms           : std_logic := '0';--\Flags that the various time-out points 
+  signal time_tlock_max         : std_logic := '0';--|have been reached.
+  signal time_out_500us         : std_logic := '0';--|
+  signal time_out_1us           : std_logic := '0';--/
+  signal time_out_100us         : std_logic := '0';--/
+  signal check_tlock_max        : std_logic := '0';
+    
+  signal mmcm_lock_count        : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+  signal mmcm_lock_int          : std_logic := '0';
+  signal mmcm_lock_i            : std_logic := '0';
+  signal mmcm_lock_reclocked    : std_logic := '0';
+  signal gtrxreset_i    : std_logic := '0';
+  signal mmcm_reset_i    : std_logic := '1';
+  signal rxpmaresetdone_i    : std_logic := '0';
+  signal txpmaresetdone_i    : std_logic := '0';
+  signal rxpmaresetdone_ss    : std_logic := '0';
+  signal rxpmaresetdone_sync    : std_logic ;
+  signal txpmaresetdone_sync    : std_logic ;
+  signal rxpmaresetdone_s    : std_logic ;
+  signal rxpmaresetdone_rx_s    : std_logic ;
+  signal pmaresetdone_fallingedge_detect    : std_logic ;
+  signal pmaresetdone_fallingedge_detect_s    : std_logic ;
+    
+  signal run_phase_alignment_int: std_logic := '0';
+  signal run_phase_alignment_int_s2 : std_logic := '0';
+  signal run_phase_alignment_int_s3 : std_logic := '0';
+
+  constant MAX_WAIT_BYPASS        : integer := 5000;--5000 RXUSRCLK cycles is the max time for Multi lanes designs
+  signal wait_bypass_count        : integer range 0 to MAX_WAIT_BYPASS-1;
+  signal time_out_wait_bypass     : std_logic := '0';
+  signal time_out_wait_bypass_s2   : std_logic := '0';
+  signal time_out_wait_bypass_s3   : std_logic := '0';
+
+  signal refclk_lost              : std_logic;
+
+  signal time_out_adapt           : std_logic := '0';   
+  signal adapt_count_reset        : std_logic := '0';   
+  signal adapt_count              : integer range 0 to WAIT_TIME_ADAPT-1;
+  signal      data_valid_sync: std_logic := '0';
+  signal      cplllock_sync: std_logic := '0';
+  signal      qplllock_sync: std_logic := '0';
+  signal      cplllock_prev: std_logic := '0';
+  signal      qplllock_prev: std_logic := '0';
+  signal      cplllock_ris_edge: std_logic := '0';
+  signal      qplllock_ris_edge: std_logic := '0';
+  signal      wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+  signal      wait_time_done : std_logic;
+
+
+  attribute shreg_extract                   : string;
+  attribute ASYNC_REG                       : string;
+
+  signal      reset_sync_reg1_tx : std_logic;
+  signal      reset_sync_reg1 : std_logic;
+  signal      gtrxreset_s : std_logic;
+  signal      gtrxreset_tx_s : std_logic;
+  signal      txpmaresetdone_s : std_logic;
+begin
+  --Alias section, signals used within this module mapped to output ports:
+  RETRY_COUNTER     <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+  RUN_PHALIGNMENT   <= run_phase_alignment_int;
+  RX_FSM_RESET_DONE <= rx_fsm_reset_done_int;
+  GTRXRESET <= gtrxreset_i; 
+  MMCM_RESET <= mmcm_reset_i; 
+  process(STABLE_CLOCK,SOFT_RESET)
+  begin
+    if (SOFT_RESET = '1') then
+        init_wait_done <= '0';
+        init_wait_count <= 0 ;
+    elsif rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+
+  adapt_wait_sim:if(EXAMPLE_SIMULATION = 1) generate
+      time_out_adapt <= '1';
+  end generate;
+
+  adapt_wait_hw:if(EXAMPLE_SIMULATION = 0) generate
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(adapt_count_reset = '1') then
+        adapt_count    <= 0;
+        time_out_adapt <= '0';
+     elsif(adapt_count = WAIT_TIME_ADAPT -1) then
+        time_out_adapt <= '1';
+     else 
+        adapt_count    <= adapt_count + 1;  
+     end if;
+    end if;
+  end process;
+  end generate;
+
+  retries_recclk_monitor:process(STABLE_CLOCK)
+  begin
+    --This counter monitors, how many retries the RECCLK monitor
+    --runs. If during startup too many retries are necessary, the whole 
+    --initialisation-process of the transceivers gets restarted.
+    if rising_edge(STABLE_CLOCK) then  
+      if recclk_mon_count_reset = '1' then
+        recclk_mon_restart_count <= 0;
+      elsif RECCLK_MONITOR_RESTART = '1' then
+        if recclk_mon_restart_count = 3 then
+          recclk_mon_restart_count <= 0;
+        else 
+          recclk_mon_restart_count <= recclk_mon_restart_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  timeouts:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- One common large counter for generating three time-out signals.
+      -- Intermediate time-outs are derived from calculated values, based
+      -- on the period of the provided clock.
+      if reset_time_out = '1' then
+        time_out_counter  <= 0;
+        time_out_2ms      <= '0';
+        time_tlock_max    <= '0';
+        time_out_500us    <= '0';
+        time_out_1us      <= '0';
+        time_out_100us    <= '0';
+      else
+        if time_out_counter = WAIT_TIMEOUT_2ms then
+          time_out_2ms <= '1';
+        else
+          time_out_counter <= time_out_counter + 1;
+        end if;
+        
+        if (time_out_counter > WAIT_TLOCK_MAX) and (check_tlock_max='1') then
+          time_tlock_max <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_500us then
+          time_out_500us <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_1us then
+          time_out_1us <= '1';
+        end if;
+
+        if time_out_counter = WAIT_TIMEOUT_100us then
+          time_out_100us <= '1';
+        end if;
+
+      end if;
+    end if;
+  end process;
+
+
+
+  mmcm_lock_wait:process(STABLE_CLOCK)
+  begin
+    --The lock-signal from the MMCM is not immediately used but 
+    --enabling a counter. Only when the counter hits its maximum,
+    --the MMCM is considered as "really" locked. 
+    --The counter avoids that the FSM already starts on only a 
+    --coarse lock of the MMCM (=toggling of the LOCK-signal).
+    if rising_edge(STABLE_CLOCK) then
+      if mmcm_lock_i = '0' then
+        mmcm_lock_count <= 0;
+        mmcm_lock_reclocked   <= '0';
+      else       
+        if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+          mmcm_lock_count <= mmcm_lock_count + 1;
+        else
+          mmcm_lock_reclocked <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+  
+
+  -- Clock Domain Crossing
+
+  sync_run_phase_alignment_int : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  RXUSERCLK,
+            data_in         =>  run_phase_alignment_int,
+            data_out        =>  run_phase_alignment_int_s2 
+         );
+
+  sync_rx_fsm_reset_done_int : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  RXUSERCLK,
+            data_in         =>  rx_fsm_reset_done_int,
+            data_out        =>  rx_fsm_reset_done_int_s2 
+         );
+
+  process(RXUSERCLK)
+  begin
+    if rising_edge(RXUSERCLK) then
+      run_phase_alignment_int_s3   <=  run_phase_alignment_int_s2;
+
+      rx_fsm_reset_done_int_s3     <=  rx_fsm_reset_done_int_s2;
+    end if;
+  end process;
+
+ sync_RXRESETDONE : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  RXRESETDONE,
+            data_out        =>  rxresetdone_s2 
+         );
+
+  sync_time_out_wait_bypass : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  time_out_wait_bypass,
+            data_out        =>  time_out_wait_bypass_s2 
+         );
+
+  sync_mmcm_lock_reclocked : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  MMCM_LOCK,
+            data_out        =>  mmcm_lock_i 
+         );
+
+  sync_data_valid : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  DATA_VALID,
+            data_out        =>  data_valid_sync
+         );
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+       rxresetdone_s3     <= rxresetdone_s2;
+
+       time_out_wait_bypass_s3 <=  time_out_wait_bypass_s2;
+
+       cplllock_prev           <=  cplllock_sync;
+       qplllock_prev           <=  qplllock_sync;
+    end if;
+  end process;
+
+ sync_CPLLLOCK : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  CPLLLOCK,
+            data_out        =>  cplllock_sync
+         );
+
+ sync_QPLLLOCK : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  QPLLLOCK,
+            data_out        =>  qplllock_sync
+         );
+
+
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       cplllock_ris_edge <= '0';
+     elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+       cplllock_ris_edge <= '1';
+     elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+       cplllock_ris_edge <= cplllock_ris_edge;
+     else 
+       cplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       qplllock_ris_edge <= '0';
+     elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+       qplllock_ris_edge <= '1';
+     elsif(rx_state = ASSERT_ALL_RESETS or rx_state = RELEASE_PLL_RESET) then
+       qplllock_ris_edge <= qplllock_ris_edge;
+     else 
+       qplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+
+  timeout_buffer_bypass:process(RXUSERCLK)
+  begin
+    if rising_edge(RXUSERCLK) then
+      if run_phase_alignment_int_s3 = '0' then
+        wait_bypass_count     <= 0;
+        time_out_wait_bypass  <= '0';
+      elsif (run_phase_alignment_int_s3 = '1') and (rx_fsm_reset_done_int_s3 = '0') then
+        if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+          time_out_wait_bypass <= '1';
+        else
+          wait_bypass_count <= wait_bypass_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+   refclk_lost <= '1' when ((RX_QPLL_USED and QPLLREFCLKLOST='1') or (not RX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+
+  timeout_max:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+        if((rx_state = ASSERT_ALL_RESETS) or
+          (rx_state = RELEASE_MMCM_RESET)) then
+            wait_time_cnt <= WAIT_TIME_MAX;
+        elsif (wait_time_cnt > 0 ) then
+            wait_time_cnt <= wait_time_cnt - 1;
+          end if;
+       end if;
+   end process;
+
+  wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+ 
+  --FSM for resetting the GTX/GTH/GTP in the 7-series. 
+  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  --
+  -- Following steps are performed:
+  -- 1) After configuration wait for approximately 500 ns as specified in 
+  --    answer-record 43482
+  -- 2) Assert all resets on the GT and on an MMCM potentially connected. 
+  --    After that wait until a reference-clock has been detected.
+  -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+  -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+  --    Also get info from the TX-side which PLL has been reset.
+  -- 5) Wait for the RESET_DONE-signal from the GT.
+  -- 6) Signal to start the phase-alignment procedure and wait for it to 
+  --    finish.
+  -- 7) Reset-sequence has successfully run through. Signal this to the 
+  --    rest of the design by asserting RX_FSM_RESET_DONE.
+  
+  reset_fsm:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if (SOFT_RESET = '1' ) then
+      --if (SOFT_RESET = '1' or (not(rx_state = INIT) and not(rx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+        rx_state                <= INIT;
+        RXUSERRDY               <= '0';
+        gtrxreset_i               <= '0';
+        mmcm_reset_i              <= '0';
+        rx_fsm_reset_done_int   <= '0';
+        QPLL_RESET              <= '0';
+        CPLL_RESET              <= '0';
+        pll_reset_asserted      <= '0';
+        reset_time_out          <= '1';
+        retry_counter_int       <=  0;
+        run_phase_alignment_int <= '0';
+        check_tlock_max         <= '0';
+        RESET_PHALIGNMENT       <= '1';
+        recclk_mon_count_reset  <= '1';
+        adapt_count_reset       <= '1';
+        RXDFEAGCHOLD            <= '0';
+        RXDFELFHOLD             <= '0';
+        RXLPMLFHOLD             <= '0';
+        RXLPMHFHOLD             <= '0';
+
+      else
+        
+        case rx_state is
+          when INIT => 
+            --Initial state after configuration. This state will be left after
+            --approx. 500 ns and not be re-entered. 
+            if init_wait_done = '1' then
+              rx_state  <= ASSERT_ALL_RESETS;
+            end if;
+            
+          when ASSERT_ALL_RESETS => 
+            --This is the state into which the FSM will always jump back if any
+            --time-outs will occur. 
+            --The number of retries is reported on the output RETRY_COUNTER. In 
+            --case the transceiver never comes up for some reason, this machine 
+            --will still continue its best and rerun until the FPGA is turned off
+            --or the transceivers come up correctly.
+             if RX_QPLL_USED and not TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                QPLL_RESET          <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                QPLL_RESET          <= '0';
+              end if;
+            elsif not RX_QPLL_USED and TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                CPLL_RESET <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                CPLL_RESET          <= '0';
+              end if;  
+            end if;
+
+            RXUSERRDY               <= '0';
+            gtrxreset_i               <= '1';
+            mmcm_reset_i              <= '1';
+            run_phase_alignment_int <= '0';    
+            RESET_PHALIGNMENT       <= '1';
+            check_tlock_max         <= '0';
+            recclk_mon_count_reset  <= '1';
+            adapt_count_reset       <= '1';
+            
+            if (RX_QPLL_USED     and not TX_QPLL_USED  and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+               (not RX_QPLL_USED and TX_QPLL_USED  and (cplllock_sync = '0') and pll_reset_asserted = '1') or
+               (not RX_QPLL_USED and not TX_QPLL_USED  ) or
+               (RX_QPLL_USED and  TX_QPLL_USED  ) then
+              rx_state  <= WAIT_FOR_PLL_LOCK;
+              reset_time_out          <= '1';
+            end if;           
+           
+          when  WAIT_FOR_PLL_LOCK =>
+              if(wait_time_done = '1') then
+                 rx_state        <=  RELEASE_PLL_RESET;  
+            end if;
+ 
+          when RELEASE_PLL_RESET => 
+            --PLL-Reset of the GTX gets released and the time-out counter
+            --starts running.
+            pll_reset_asserted  <= '0';
+            reset_time_out  <= '0';
+            
+            if (RX_QPLL_USED     and not TX_QPLL_USED and (qplllock_sync = '1')) or
+               (not RX_QPLL_USED and TX_QPLL_USED     and (cplllock_sync = '1')) then
+              rx_state                <= VERIFY_RECCLK_STABLE;
+              reset_time_out          <= '1';
+              recclk_mon_count_reset  <= '0';
+              adapt_count_reset       <= '0';
+            elsif (RX_QPLL_USED and (qplllock_sync = '1')) or
+                  (not RX_QPLL_USED and (cplllock_sync = '1')) then
+              rx_state                <= VERIFY_RECCLK_STABLE;
+              reset_time_out          <= '1';
+              recclk_mon_count_reset  <= '0';
+              adapt_count_reset       <= '0';
+            end if;
+            
+            if time_out_2ms = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+
+          when VERIFY_RECCLK_STABLE =>
+            --reset_time_out  <= '0';
+            --Time-out counter is not released in this state as here the FSM
+            --does not wait for a certain period of time but checks on the number
+            --of retries in the RECCLK monitor 
+            gtrxreset_i <= '0';
+            if RECCLK_STABLE = '1' then
+              rx_state        <= RELEASE_MMCM_RESET;
+              reset_time_out  <= '1';
+              
+            end if;          
+
+            if recclk_mon_restart_count = 2 then
+              --If two retries are performed in the RECCLK monitor
+              --the whole initialisation-sequence gets restarted.
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+          
+          when RELEASE_MMCM_RESET => 
+            --Release of the MMCM-reset. Waiting for the MMCM to lock.
+            check_tlock_max <= '1';
+            
+            mmcm_reset_i <= '0';
+            reset_time_out  <= '0';
+         
+            if mmcm_lock_reclocked = '1' then
+              rx_state <= WAIT_FOR_RXUSRCLK;
+              reset_time_out  <= '1';
+            end if;          
+            
+            if (time_tlock_max = '1' and reset_time_out = '0' )then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+ 
+           when WAIT_FOR_RXUSRCLK =>
+              if wait_time_done = '1' then
+               rx_state <=  WAIT_RESET_DONE;  
+            end if;
+           
+          when WAIT_RESET_DONE => 
+            --When TXOUTCLK is the source for RXUSRCLK, RXUSERRDY depends on TXUSERRDY
+            --If RXOUTCLK is the source for RXUSRCLK, TXUSERRDY can be tied to '1'
+            if TXUSERRDY = '1' then
+               RXUSERRDY <= '1';
+            end if;
+            reset_time_out  <= '0';
+            if rxresetdone_s3 = '1' then
+              rx_state        <= DO_PHASE_ALIGNMENT; 
+              reset_time_out  <= '1';
+            end if;          
+
+            if time_out_2ms = '1' and reset_time_out = '0' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+          
+          when DO_PHASE_ALIGNMENT => 
+            --The direct handling of the signals for the Phase Alignment is done outside
+            --this state-machine. 
+            RESET_PHALIGNMENT       <= '0';
+            run_phase_alignment_int <= '1';
+            reset_time_out          <= '0';
+            
+            if PHALIGNMENT_DONE = '1' then
+              rx_state        <= MONITOR_DATA_VALID;
+              reset_time_out  <= '1';
+            end if;
+            
+            if time_out_wait_bypass_s3 = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <=  retry_counter_int + 1;
+              end if;
+              rx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+          
+          when MONITOR_DATA_VALID => 
+              reset_time_out  <= '0';
+
+              if(time_out_100us = '1' and data_valid_sync ='0' and DONT_RESET_ON_DATA_ERROR = '0' and reset_time_out = '0')  then
+                 rx_state              <= ASSERT_ALL_RESETS; 
+                 rx_fsm_reset_done_int <= '0';
+              elsif (data_valid_sync = '1') then
+                 rx_state              <= FSM_DONE; 
+                 rx_fsm_reset_done_int <= '0';
+                 reset_time_out        <= '1';
+              end if;
+ 
+         when FSM_DONE =>
+            reset_time_out  <= '0';
+            if data_valid_sync = '0' then
+               rx_fsm_reset_done_int <= '0';
+               reset_time_out        <= '1';
+               rx_state              <= MONITOR_DATA_VALID;
+ 
+            elsif(time_out_1us = '1' and reset_time_out = '0')  then
+               rx_fsm_reset_done_int <= '1';
+            end if;
+
+            if(time_out_adapt = '1') then
+               if(EQ_MODE = "DFE") then
+                  RXDFEAGCHOLD  <=  '1';
+                  RXDFELFHOLD   <=  '1';
+                  RXLPMHFHOLD   <=  '0';
+                  RXLPMLFHOLD   <=  '0';
+               else 
+                  RXDFEAGCHOLD  <=  '0';
+                  RXDFELFHOLD   <=  '0';
+                  RXLPMHFHOLD   <=  '0';
+                  RXLPMLFHOLD   <=  '0';
+               end if;
+            end if;
+           when OTHERS => 
+              rx_state                <= INIT;
+        end case;
+      end if;
+    end if;
+  end process;
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_sync_block.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_sync_block.vhd
new file mode 100644
index 0000000..59309a8
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_sync_block.vhd
@@ -0,0 +1,194 @@
+--////////////////////////////////////////////////////////////////////////////////
+--//   ____  ____ 
+--//  /   /\/   / 
+--// /___/  \  /    Vendor: Xilinx 
+--// \   \   \/     Version : 3.5
+--//  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--//  /   /         Filename : gtx_trb3_sync_2gb_sync_block.vhd
+--// /___/   /\     
+--// \   \  /  \ 
+--//  \___\/\___\ 
+--//
+--//
+--
+-- Description: Used on signals crossing from one clock domain to
+--              another, this is a flip-flop pair, with both flops
+--              placed together with RLOCs into the same slice.  Thus
+--              the routing delay between the two is minimum to safe-
+--              guard against metastability issues.
+--                     
+--
+-- Module GTX_trb3_sync_2gb_sync_block
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_trb3_sync_2gb_sync_block is
+  generic (
+    INITIALISE : bit_vector(5 downto 0) := "000000"
+  );
+  port (
+    clk         : in  std_logic;          -- clock to be sync'ed to
+    data_in     : in  std_logic;          -- Data to be 'synced'
+    data_out    : out std_logic           -- synced data
+    );
+
+-- attribute dont_touch : string;
+-- attribute dont_touch    of   GTX_trb3_sync_2gb_sync_block : entity is "yes";
+
+end GTX_trb3_sync_2gb_sync_block;
+
+
+architecture structural of GTX_trb3_sync_2gb_sync_block is
+
+
+  -- Internal Signals
+  signal data_sync1 : std_logic;
+  signal data_sync2 : std_logic;
+  signal data_sync3 : std_logic;
+  signal data_sync4 : std_logic;
+  signal data_sync5 : std_logic;
+
+  -- These attributes will stop timing errors being reported in back annotated
+  -- SDF simulation.
+  attribute ASYNC_REG                       : string;
+  attribute ASYNC_REG of data_sync_reg1    : label is "true";
+  attribute ASYNC_REG of data_sync_reg2    : label is "true";
+  attribute ASYNC_REG of data_sync_reg3    : label is "true";
+  attribute ASYNC_REG of data_sync_reg4    : label is "true";
+  attribute ASYNC_REG of data_sync_reg5    : label is "true";
+  attribute ASYNC_REG of data_sync_reg6    : label is "true";
+
+  -- These attributes will stop XST translating the desired flip-flops into an
+  -- SRL based shift register.
+  attribute shreg_extract                   : string;
+  attribute shreg_extract of data_sync_reg1 : label is "no";
+  attribute shreg_extract of data_sync_reg2 : label is "no";
+  attribute shreg_extract of data_sync_reg3 : label is "no";
+  attribute shreg_extract of data_sync_reg4 : label is "no";
+  attribute shreg_extract of data_sync_reg5 : label is "no";
+  attribute shreg_extract of data_sync_reg6 : label is "no";
+
+  
+begin
+
+  data_sync_reg1 : FD
+  generic map (
+    INIT => INITIALISE(0)
+  )
+  port map (
+    C    => clk,
+    D    => data_in,
+    Q    => data_sync1
+  );
+
+ data_sync_reg2 : FD
+  generic map (
+    INIT => INITIALISE(1)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync1,
+    Q    => data_sync2
+  );
+
+ data_sync_reg3 : FD
+  generic map (
+    INIT => INITIALISE(2)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync2,
+    Q    => data_sync3
+  );
+
+ data_sync_reg4 : FD
+  generic map (
+    INIT => INITIALISE(3)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync3,
+    Q    => data_sync4
+  );
+
+ data_sync_reg5 : FD
+  generic map (
+    INIT => INITIALISE(4)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync4,
+    Q    => data_sync5
+  );  
+
+  data_sync_reg6 : FD
+  generic map (
+    INIT => INITIALISE(5)
+  )
+  port map (
+    C    => clk,
+    D    => data_sync5,
+    Q    => data_out
+  );
+
+
+
+end structural;
+
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_tx_startup_fsm.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_tx_startup_fsm.vhd
new file mode 100644
index 0000000..8aab9f6
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/IPsources/gtx_trb3_sync_2gb_tx_startup_fsm.vhd
@@ -0,0 +1,609 @@
+--//////////////////////////////////////////////////////////////////////////////
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename :gtx_trb3_sync_2gb_tx_startup_fsm.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module GTX_trb3_sync_2gb_tx_startup_fsm
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity GTX_trb3_sync_2gb_TX_STARTUP_FSM is
+  Generic(
+           EXAMPLE_SIMULATION       : integer := 0; 
+           STABLE_CLOCK_PERIOD      : integer range 4 to 250 := 8; --Period of the stable clock driving this state-machine, unit is [ns]
+           RETRY_COUNTER_BITWIDTH   : integer range 2 to 8  := 8; 
+           TX_QPLL_USED             : boolean := False;           -- the TX and RX Reset FSMs must
+           RX_QPLL_USED             : boolean := False;           -- share these two generic values
+           PHASE_ALIGNMENT_MANUAL   : boolean := True             -- Decision if a manual phase-alignment is necessary or the automatic 
+                                                                  -- is enough. For single-lane applications the automatic alignment is 
+                                                                  -- sufficient              
+         );     
+    Port ( STABLE_CLOCK             : in  STD_LOGIC;              --Stable Clock, either a stable clock from the PCB
+                                                                  --or reference-clock present at startup.
+           TXUSERCLK                : in  STD_LOGIC;              --TXUSERCLK as used in the design
+           SOFT_RESET               : in  STD_LOGIC;              --User Reset, can be pulled any time
+           QPLLREFCLKLOST           : in  STD_LOGIC;              --QPLL Reference-clock for the GT is lost
+           CPLLREFCLKLOST           : in  STD_LOGIC;              --CPLL Reference-clock for the GT is lost
+           QPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the QPLL of the GT
+           CPLLLOCK                 : in  STD_LOGIC;              --Lock Detect from the CPLL of the GT
+           TXRESETDONE              : in  STD_LOGIC;      
+           MMCM_LOCK                : in  STD_LOGIC;      
+           GTTXRESET                : out STD_LOGIC;      
+           MMCM_RESET               : out STD_LOGIC:='1';      
+           QPLL_RESET               : out STD_LOGIC:='0';        --Reset QPLL
+           CPLL_RESET               : out STD_LOGIC:='0';        --Reset CPLL
+           TX_FSM_RESET_DONE        : out STD_LOGIC;             --Reset-sequence has sucessfully been finished.
+           TXUSERRDY                : out STD_LOGIC:='0';
+           RUN_PHALIGNMENT          : out STD_LOGIC:='0';
+           RESET_PHALIGNMENT        : out STD_LOGIC:='0';
+           PHALIGNMENT_DONE         : in  STD_LOGIC;
+           
+           RETRY_COUNTER            : out  STD_LOGIC_VECTOR (RETRY_COUNTER_BITWIDTH-1 downto 0):=(others=>'0')-- Number of 
+                                                            -- Retries it took to get the transceiver up and running
+           );
+end GTX_trb3_sync_2gb_TX_STARTUP_FSM;
+
+--Interdependencies:
+-- * Timing depends on the frequency of the stable clock. Hence counters-sizes
+--   are calculated at design-time based on the Generics
+--   
+-- * if either of PLLs is reset during TX-startup, it does not need to be reset again by RX
+--   => signal which PLL has been reset
+-- * 
+
+
+
+architecture RTL of GTX_trb3_sync_2gb_TX_STARTUP_FSM is
+
+  component GTX_trb3_sync_2gb_sync_block
+   generic (
+     INITIALISE : bit_vector(5 downto 0) := "000000"
+   );
+   port  (
+             clk           : in  std_logic;
+             data_in       : in  std_logic;
+             data_out      : out std_logic
+          );
+   end component;
+
+  type tx_rst_fsm_type is(
+    INIT, ASSERT_ALL_RESETS, WAIT_FOR_PLL_LOCK, RELEASE_PLL_RESET,
+    WAIT_FOR_TXOUTCLK, RELEASE_MMCM_RESET, WAIT_FOR_TXUSRCLK, WAIT_RESET_DONE, DO_PHASE_ALIGNMENT,
+    RESET_FSM_DONE);
+    
+  signal tx_state : tx_rst_fsm_type := INIT;
+
+  constant MMCM_LOCK_CNT_MAX    : integer := 256;
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+    
+  constant WAIT_TIMEOUT_2ms     : integer := 2000000 / STABLE_CLOCK_PERIOD;--  2 ms time-out
+  constant WAIT_TLOCK_MAX       : integer :=  100000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_TIMEOUT_500us   : integer :=  500000 / STABLE_CLOCK_PERIOD;--100 us time-out
+  constant WAIT_1us_cycles      : integer :=  1000 / STABLE_CLOCK_PERIOD;--1 us time-out
+  constant WAIT_1us             : integer := WAIT_1us_cycles+ 10;                    -- 1us plus some additional margin
+    
+  signal init_wait_count        : integer range 0 to WAIT_MAX:=0;
+  signal init_wait_done         : std_logic := '0';
+  signal pll_reset_asserted     : std_logic := '0';
+
+  signal tx_fsm_reset_done_int     : std_logic := '0';
+  signal tx_fsm_reset_done_int_s2  : std_logic := '0';
+  signal tx_fsm_reset_done_int_s3  : std_logic := '0';
+   
+  signal txresetdone_s2         : std_logic := '0'; 
+  signal txresetdone_s3         : std_logic := '0'; 
+
+  constant MAX_RETRIES          : integer := 2**RETRY_COUNTER_BITWIDTH-1; 
+  signal retry_counter_int      : integer range 0 to MAX_RETRIES;  
+  signal time_out_counter       : integer range 0 to WAIT_TIMEOUT_2ms := 0;
+    
+  signal reset_time_out         : std_logic := '0';
+  signal time_out_2ms           : std_logic := '0';--\Flags that the various time-out points 
+  signal time_tlock_max         : std_logic := '0';--|have been reached.
+  signal time_out_500us         : std_logic := '0';--/
+    
+  signal mmcm_lock_count        : integer range 0 to MMCM_LOCK_CNT_MAX-1:=0;
+  signal mmcm_lock_int          : std_logic := '0';
+  signal mmcm_lock_i            : std_logic := '0';
+  signal mmcm_lock_reclocked    : std_logic := '0';
+    
+  signal run_phase_alignment_int    : std_logic := '0';
+  signal run_phase_alignment_int_s2 : std_logic := '0';
+  signal run_phase_alignment_int_s3 : std_logic := '0';
+  constant MAX_WAIT_BYPASS      : integer := 45824; --110000 TXUSRCLK cycles is the max time for Multi lane designs
+ 
+  constant WAIT_TIME_MAX    : integer := 100 ; --10 us time-out
+
+  signal wait_bypass_count      : integer range 0 to MAX_WAIT_BYPASS-1;
+  signal time_out_wait_bypass   : std_logic := '0';
+  signal time_out_wait_bypass_s2   : std_logic := '0';
+  signal time_out_wait_bypass_s3   : std_logic := '0';
+  signal txuserrdy_i   : std_logic := '0';
+  signal refclk_lost            : std_logic;
+  signal gttxreset_i            : std_logic := '0';
+  signal txpmaresetdone_i            : std_logic := '0';
+  signal txpmaresetdone_sync            : std_logic ;
+
+  signal      cplllock_sync: std_logic := '0';
+  signal      qplllock_sync: std_logic := '0';
+  signal      cplllock_prev: std_logic := '0';
+  signal      qplllock_prev: std_logic := '0';
+  signal      cplllock_ris_edge: std_logic := '0';
+  signal      qplllock_ris_edge: std_logic := '0';
+ signal      wait_time_cnt : integer range 0 to WAIT_TIME_MAX;
+  signal      wait_time_done :std_logic;
+ 
+begin
+  --Alias section, signals used within this module mapped to output ports:
+  RETRY_COUNTER     <= STD_LOGIC_VECTOR(TO_UNSIGNED(retry_counter_int,RETRY_COUNTER_BITWIDTH));
+  RUN_PHALIGNMENT   <= run_phase_alignment_int;
+  TX_FSM_RESET_DONE <= tx_fsm_reset_done_int;    
+  GTTXRESET <= gttxreset_i;
+
+  process(STABLE_CLOCK,SOFT_RESET)
+  begin
+    if (SOFT_RESET = '1') then
+        init_wait_done <= '0';
+        init_wait_count <= 0 ;
+    elsif rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+  timeouts:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- One common large counter for generating three time-out signals.
+      -- Intermediate time-outs are derived from calculated values, based
+      -- on the period of the provided clock.
+      if reset_time_out = '1' then
+        time_out_counter  <= 0;
+        time_out_2ms      <= '0';
+        time_tlock_max    <= '0';
+        time_out_500us    <= '0';
+      else
+        if time_out_counter = WAIT_TIMEOUT_2ms then
+          time_out_2ms <= '1';
+        else
+          time_out_counter <= time_out_counter + 1;
+        end if;
+        
+        if time_out_counter = WAIT_TLOCK_MAX then
+          time_tlock_max <= '1';
+        end if;
+      
+        if time_out_counter = WAIT_TIMEOUT_500us then
+          time_out_500us <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  mmcm_lock_wait:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if mmcm_lock_i = '0' then
+        mmcm_lock_count <= 0;
+        mmcm_lock_reclocked   <= '0';
+      else 
+        if mmcm_lock_count < MMCM_LOCK_CNT_MAX - 1 then
+          mmcm_lock_count <= mmcm_lock_count + 1;
+        else
+          mmcm_lock_reclocked <= '1';
+        end if;
+      end if;
+    end if;
+  end process;
+ 
+ 
+
+  -- Clock Domain Crossing
+
+  sync_run_phase_alignment_int : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  TXUSERCLK,
+            data_in         =>  run_phase_alignment_int,
+            data_out        =>  run_phase_alignment_int_s2 
+         );
+
+  sync_tx_fsm_reset_done_int : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  TXUSERCLK,
+            data_in         =>  tx_fsm_reset_done_int,
+            data_out        =>  tx_fsm_reset_done_int_s2 
+         );
+
+  process(TXUSERCLK)
+  begin
+    if rising_edge(TXUSERCLK) then
+      run_phase_alignment_int_s3   <=  run_phase_alignment_int_s2;
+
+      tx_fsm_reset_done_int_s3     <=  tx_fsm_reset_done_int_s2;
+    end if;
+  end process;
+
+ sync_TXRESETDONE : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  TXRESETDONE,
+            data_out        =>  txresetdone_s2 
+         );
+
+  sync_time_out_wait_bypass : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  time_out_wait_bypass,
+            data_out        =>  time_out_wait_bypass_s2 
+         );
+
+  sync_mmcm_lock_reclocked : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  MMCM_LOCK,
+            data_out        =>  mmcm_lock_i 
+         );
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+       txresetdone_s3     <= txresetdone_s2;
+
+       time_out_wait_bypass_s3 <=  time_out_wait_bypass_s2;
+
+       cplllock_prev           <=  cplllock_sync;
+       qplllock_prev           <=  qplllock_sync;
+    end if;
+  end process;
+
+ sync_CPLLLOCK : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  CPLLLOCK,
+            data_out        =>  cplllock_sync
+         );
+
+ sync_QPLLLOCK : GTX_trb3_sync_2gb_sync_block
+  port map
+         (
+            clk             =>  STABLE_CLOCK,
+            data_in         =>  QPLLLOCK,
+            data_out        =>  qplllock_sync
+         );
+
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       cplllock_ris_edge <= '0';
+     elsif((cplllock_prev = '0') and (cplllock_sync = '1')) then
+       cplllock_ris_edge <= '1';
+     elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+       cplllock_ris_edge <= cplllock_ris_edge;
+     else 
+       cplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+  process (STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+     if(SOFT_RESET = '1' ) then
+       qplllock_ris_edge <= '0';
+     elsif((qplllock_prev = '0') and (qplllock_sync = '1')) then
+       qplllock_ris_edge <= '1';
+     elsif(tx_state = ASSERT_ALL_RESETS or tx_state = RELEASE_PLL_RESET) then
+       qplllock_ris_edge <= qplllock_ris_edge;
+     else 
+       qplllock_ris_edge <= '0';
+     end if;
+    end if;
+  end process;
+
+
+
+  timeout_buffer_bypass:process(TXUSERCLK)
+  begin
+    if rising_edge(TXUSERCLK) then
+      if run_phase_alignment_int_s3 = '0' then
+        wait_bypass_count     <= 0;
+        time_out_wait_bypass  <= '0';
+      elsif (run_phase_alignment_int_s3 = '1') and (tx_fsm_reset_done_int_s3 = '0')  then
+        if wait_bypass_count = MAX_WAIT_BYPASS - 1 then
+          time_out_wait_bypass <= '1';
+        else
+          wait_bypass_count <= wait_bypass_count + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+   refclk_lost <= '1' when ((TX_QPLL_USED and QPLLREFCLKLOST='1') or (not TX_QPLL_USED and CPLLREFCLKLOST='1')) else '0';
+
+
+  timeout_max:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+        if((tx_state = ASSERT_ALL_RESETS) or
+          (tx_state = RELEASE_PLL_RESET) or 
+          (tx_state = RELEASE_MMCM_RESET)) then
+            wait_time_cnt <= WAIT_TIME_MAX;
+        elsif (wait_time_cnt > 0 ) then
+            wait_time_cnt <= wait_time_cnt - 1;
+          end if;
+       end if;
+   end process;
+
+  wait_time_done <= '1' when (wait_time_cnt = 0) else '0';
+
+  --FSM for resetting the GTX/GTH/GTP in the 7-series. 
+  --~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  --
+  -- Following steps are performed:
+  -- 1) Only for GTX - After configuration wait for approximately 500 ns as specified in 
+  --    answer-record 43482
+  -- 2) Assert all resets on the GT and on an MMCM potentially connected. 
+  --    After that wait until a reference-clock has been detected.
+  -- 3) Release the reset to the GT and wait until the GT-PLL has locked.
+  -- 4) Release the MMCM-reset and wait until the MMCM has signalled lock.
+  --    Also signal to the RX-side which PLL has been reset.
+  -- 5) Wait for the RESET_DONE-signal from the GT.
+  -- 6) Signal to start the phase-alignment procedure and wait for it to 
+  --    finish.
+  -- 7) Reset-sequence has successfully run through. Signal this to the 
+  --    rest of the design by asserting TX_FSM_RESET_DONE.
+  
+  reset_fsm:process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1') then
+      --if(SOFT_RESET = '1' or (not(tx_state = INIT) and not(tx_state = ASSERT_ALL_RESETS) and refclk_lost = '1')) then
+        tx_state                <= INIT;
+        TXUSERRDY               <= '0';
+        gttxreset_i               <= '0';
+        MMCM_RESET              <= '0';
+        tx_fsm_reset_done_int   <= '0';
+        QPLL_RESET              <= '0';
+        CPLL_RESET              <= '0';
+        pll_reset_asserted      <= '0';
+        reset_time_out          <= '0';
+        retry_counter_int       <=  0;
+        run_phase_alignment_int <= '0';
+        RESET_PHALIGNMENT       <= '1';
+      else
+        
+        case tx_state is
+          when INIT => 
+            --Initial state after configuration. This state will be left after
+            --approx. 500 ns and not be re-entered. 
+            if init_wait_done = '1' then
+              tx_state        <= ASSERT_ALL_RESETS;
+              reset_time_out  <= '1';
+            end if;
+            
+          when ASSERT_ALL_RESETS => 
+            --This is the state into which the FSM will always jump back if any
+            --time-outs will occur. 
+            --The number of retries is reported on the output RETRY_COUNTER. In 
+            --case the transceiver never comes up for some reason, this machine 
+            --will still continue its best and rerun until the FPGA is turned off
+            --or the transceivers come up correctly.
+            if TX_QPLL_USED then
+              if pll_reset_asserted = '0' then
+                QPLL_RESET          <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                QPLL_RESET          <= '0';
+              end if;
+            else
+              if pll_reset_asserted = '0' then
+                CPLL_RESET <= '1';
+                pll_reset_asserted  <= '1';
+              else
+                CPLL_RESET          <= '0';
+              end if;  
+            end if;
+            TXUSERRDY               <= '0';
+            gttxreset_i               <= '1';
+            MMCM_RESET              <= '1';
+            reset_time_out          <= '1';
+            run_phase_alignment_int <= '0';     
+            RESET_PHALIGNMENT       <= '1';
+
+            if (TX_QPLL_USED  and (qplllock_sync = '0') and pll_reset_asserted = '1') or
+               (not TX_QPLL_USED  and (cplllock_sync = '0') and pll_reset_asserted = '1') then
+              tx_state  <= WAIT_FOR_PLL_LOCK;
+           end if;    
+       
+           when WAIT_FOR_PLL_LOCK =>
+              if(wait_time_done = '1') then
+                 tx_state        <=  RELEASE_PLL_RESET;  
+           end if;    
+         
+          when RELEASE_PLL_RESET => 
+            --PLL-Reset of the GTX gets released and the time-out counter
+            --starts running.
+            pll_reset_asserted  <= '0';
+
+            if (TX_QPLL_USED and (qplllock_sync = '1')) or
+               (not TX_QPLL_USED and (cplllock_sync = '1')) then
+              tx_state  <= WAIT_FOR_TXOUTCLK;
+              reset_time_out  <= '1';
+            end if;
+            
+            if time_out_2ms = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+
+           when WAIT_FOR_TXOUTCLK =>
+            gttxreset_i <= '0';
+              if(wait_time_done = '1') then
+               tx_state <=  RELEASE_MMCM_RESET;  
+           end if;    
+
+          when RELEASE_MMCM_RESET => 
+            --Release of the MMCM-reset. Waiting for the MMCM to lock.
+            MMCM_RESET <= '0';
+            reset_time_out  <= '0';
+            if mmcm_lock_reclocked = '1' then
+              tx_state <= WAIT_FOR_TXUSRCLK;
+              reset_time_out  <= '1';
+            end if;          
+            
+            if (time_tlock_max = '1' and mmcm_lock_reclocked = '0' and reset_time_out = '0') then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;            
+
+           when WAIT_FOR_TXUSRCLK =>
+              if(wait_time_done = '1') then
+               tx_state <=  WAIT_RESET_DONE; 
+           end if;    
+ 
+          when WAIT_RESET_DONE => 
+            TXUSERRDY <= '1';
+            reset_time_out  <= '0';
+            if txresetdone_s3 = '1' then              
+              tx_state      <= DO_PHASE_ALIGNMENT;               
+              reset_time_out  <= '1';
+            end if;          
+
+            if (time_out_500us = '1' and reset_time_out = '0') then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <= retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;                    
+          
+          when DO_PHASE_ALIGNMENT => 
+            --The direct handling of the signals for the Phase Alignment is done outside
+            --this state-machine. 
+            RESET_PHALIGNMENT       <= '0';
+            run_phase_alignment_int <= '1';
+            reset_time_out          <= '0';
+            
+            if PHALIGNMENT_DONE = '1' then
+              tx_state        <= RESET_FSM_DONE;
+            end if;
+            
+            if time_out_wait_bypass_s3 = '1' then
+              if retry_counter_int = MAX_RETRIES then
+                -- If too many retries are performed compared to what is specified in 
+                -- the generic, the counter simply wraps around.
+                retry_counter_int <= 0;
+              else
+                retry_counter_int <=  retry_counter_int + 1;
+              end if;
+              tx_state            <= ASSERT_ALL_RESETS; 
+            end if;           
+          
+          when RESET_FSM_DONE => 
+            reset_time_out        <= '1';
+            tx_fsm_reset_done_int <= '1';
+
+          when OTHERS =>
+            tx_state              <= INIT;
+          
+        end case;
+      end if;
+    end if;
+  end process; 
+
+end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_clock_module.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_clock_module.vhd
new file mode 100644
index 0000000..14c09fb
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_clock_module.vhd
@@ -0,0 +1,245 @@
+-- file: clk_wiz_v2_1.vhd
+-- 
+-- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+-- Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1   100.000      0.000    50.000      130.958     98.575
+-- CLK_OUT2   200.000      0.000    50.000      114.829     98.575
+--
+------------------------------------------------------------------------------
+-- Input Clock   Input Freq (MHz)   Input Jitter (UI)
+------------------------------------------------------------------------------
+-- primary         100.000            0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity GTX_trb3_sync_2gb_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end GTX_trb3_sync_2gb_CLOCK_MODULE;
+
+architecture xilinx of GTX_trb3_sync_2gb_CLOCK_MODULE is
+  attribute X_CORE_INFO : string;
+  attribute X_CORE_INFO of xilinx : architecture is "GTX_trb3_sync_2gb,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_wiz_v2_1,clk_wiz_v2_1,{component_name=clk_wiz_v2_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfbout_buf     : std_logic;
+  signal clkfboutb_unused : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout0b_unused  : std_logic;
+  signal clkout1          : std_logic;
+  signal clkout1b_unused  : std_logic;
+  signal clkout2          : std_logic;
+  signal clkout2b_unused  : std_logic;
+  signal clkout3          : std_logic;
+  signal clkout3b_unused  : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  signal clkout6_unused   : std_logic;
+  -- Dynamic programming unused signals
+  signal do_unused        : std_logic_vector(15 downto 0);
+  signal drdy_unused      : std_logic;
+  -- Dynamic phase shift unused signals
+  signal psdone_unused    : std_logic;
+  -- Unused status signals
+  signal clkfbstopped_unused : std_logic;
+  signal clkinstopped_unused : std_logic;
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : BUFG
+  port map
+   (O => clkin1,
+    I => CLK_IN);
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the MMCM primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+
+  mmcm_adv_inst : MMCME2_ADV
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLKOUT4_CASCADE      => FALSE,
+    COMPENSATION         => "ZHOLD",
+    STARTUP_WAIT         => FALSE,
+    DIVCLK_DIVIDE        => DIVIDE,
+    CLKFBOUT_MULT_F      => MULT,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKFBOUT_USE_FINE_PS => FALSE,
+    CLKOUT0_DIVIDE_F     => OUT0_DIVIDE,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT0_USE_FINE_PS  => FALSE,
+    CLKIN1_PERIOD        => CLK_PERIOD,
+    CLKOUT1_DIVIDE       => OUT1_DIVIDE,
+    CLKOUT1_PHASE        => 0.000,
+    CLKOUT1_DUTY_CYCLE   => 0.500,
+    CLKOUT1_USE_FINE_PS  => FALSE,
+    CLKOUT2_DIVIDE       => OUT2_DIVIDE,
+    CLKOUT2_PHASE        => 0.000,
+    CLKOUT2_DUTY_CYCLE   => 0.500,
+    CLKOUT2_USE_FINE_PS  => FALSE,
+    CLKOUT3_DIVIDE       => OUT3_DIVIDE,
+    CLKOUT3_PHASE        => 0.000,
+    CLKOUT3_DUTY_CYCLE   => 0.500,
+    CLKOUT3_USE_FINE_PS  => FALSE,
+    REF_JITTER1          => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKFBOUTB           => clkfboutb_unused,
+    CLKOUT0             => clkout0,
+    CLKOUT0B            => clkout0b_unused,
+    CLKOUT1             => clkout1,
+    CLKOUT1B            => clkout1b_unused,
+    CLKOUT2             => clkout2,
+    CLKOUT2B            => clkout2b_unused,
+    CLKOUT3             => clkout3,
+    CLKOUT3B            => clkout3b_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    CLKOUT6             => clkout6_unused,
+    -- Input clock control
+    CLKFBIN             => clkfbout,
+    CLKIN1              => clkin1,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => do_unused,
+    DRDY                => drdy_unused,
+    DWE                 => '0',
+    -- Ports for dynamic phase shift
+    PSCLK               => '0',
+    PSEN                => '0',
+    PSINCDEC            => '0',
+    PSDONE              => psdone_unused,
+    -- Other control and status signals
+    LOCKED              => MMCM_LOCKED_OUT,
+    CLKINSTOPPED        => clkinstopped_unused,
+    CLKFBSTOPPED        => clkfbstopped_unused,
+    PWRDWN              => '0',
+    RST                 => MMCM_RESET_IN);
+
+  -- Output buffering
+  -------------------------------------
+  --clkf_buf : BUFG
+  --port map
+  -- (O => clkfbout_buf,
+  --  I => clkfbout);
+
+
+  clkout0_buf : BUFG
+  port map
+   (O   => CLK0_OUT,
+    I   => clkout0);
+
+  clkout1_buf : BUFG
+  port map
+   (O   => CLK1_OUT,
+    I   => clkout1);
+
+--  clkout2_buf : BUFG
+--  port map
+--   (O   => CLK2_OUT,
+--    I   => clkout2);
+--
+--  clkout3_buf : BUFG
+--  port map
+--   (O   => CLK3_OUT,
+--    I   => clkout3);
+
+CLK2_OUT <= '0';
+CLK3_OUT <= '0';
+end xilinx;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_common.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_common.vhd
new file mode 100644
index 0000000..0580693
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_common.vhd
@@ -0,0 +1,247 @@
+---------------------------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard
+--  /   /         Filename : gtx_trb3_sync_2gb_common.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--
+-- Module GTX_trb3_sync_2gb_common 
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+
+--***************************** Entity Declaration ****************************
+entity GTX_trb3_sync_2gb_common is
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "TRUE";        -- Set to "true" to speed up sim reset 
+    SIM_QPLLREFCLK_SEL              : bit_vector :=  "001"
+);
+port
+(
+    QPLLREFCLKSEL_IN  : in std_logic_vector(2 downto 0);
+    GTREFCLK1_IN      : in std_logic;
+    GTREFCLK0_IN : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+);
+
+end GTX_trb3_sync_2gb_common;
+    
+architecture RTL of GTX_trb3_sync_2gb_common is
+
+    attribute CORE_GENERATION_INFO : string;
+    attribute CORE_GENERATION_INFO of RTL : architecture is "GTX_trb3_sync_2gb_common,gtwizard_v3_5,{protocol_file=Start_from_scratch}";
+
+
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--*************************Logic to set Attribute QPLL_FB_DIV*****************************
+    impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return "0000100000";
+       elsif (qpllfbdiv_top = 20) then
+         return "0000110000" ;
+       elsif (qpllfbdiv_top = 32) then
+         return "0001100000" ;
+       elsif (qpllfbdiv_top = 40) then
+         return "0010000000" ;
+       elsif (qpllfbdiv_top = 64) then
+         return "0011100000" ;
+       elsif (qpllfbdiv_top = 66) then
+         return "0101000000" ;
+       elsif (qpllfbdiv_top = 80) then
+         return "0100100000" ;
+       elsif (qpllfbdiv_top = 100) then
+         return "0101110000" ;
+       else 
+         return "0000000000" ;
+       end if;
+    end function;
+
+    impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
+    begin
+       if (qpllfbdiv_top = 16) then
+         return '1';
+       elsif (qpllfbdiv_top = 20) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 32) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 40) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 64) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 66) then
+         return '0' ;
+       elsif (qpllfbdiv_top = 80) then
+         return '1' ;
+       elsif (qpllfbdiv_top = 100) then
+         return '1' ;
+       else 
+         return '1' ;
+       end if;
+    end function;
+
+    constant   QPLL_FBDIV_TOP   : integer  := 16;
+    constant   QPLL_FBDIV_IN    :   bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
+    constant   QPLL_FBDIV_RATIO :   bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
+
+    -- ground and tied_to_vcc_i signals
+    signal  tied_to_ground_i                :   std_logic;
+    signal  tied_to_ground_vec_i            :   std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   :   std_logic;
+    signal  tied_to_vcc_vec_i               :   std_logic_vector(63 downto 0);
+
+begin
+    tied_to_ground_i                    <= '0';
+    tied_to_ground_vec_i(63 downto 0)   <= (others => '0');
+    tied_to_vcc_i                       <= '1';
+    tied_to_vcc_vec_i(63 downto 0)      <= (others => '1');
+
+    --_________________________________________________________________________
+    --_________________________________________________________________________
+    --_________________________GTXE2_COMMON____________________________________
+
+    gtxe2_common_i : GTXE2_COMMON
+    generic map
+    (
+            -- Simulation attributes
+            SIM_RESET_SPEEDUP    => WRAPPER_SIM_GTRESET_SPEEDUP,
+            SIM_QPLLREFCLK_SEL   => (SIM_QPLLREFCLK_SEL),
+            SIM_VERSION          => "4.0",
+
+
+       ------------------COMMON BLOCK Attributes---------------
+        BIAS_CFG                                =>     (x"0000040000001000"),
+        COMMON_CFG                              =>     (x"00000000"),
+        QPLL_CFG                                =>     (x"06801C1"),
+        QPLL_CLKOUT_CFG                         =>     ("0000"),
+        QPLL_COARSE_FREQ_OVRD                   =>     ("010000"),
+        QPLL_COARSE_FREQ_OVRD_EN                =>     ('0'),
+        QPLL_CP                                 =>     ("0000011111"),
+        QPLL_CP_MONITOR_EN                      =>     ('0'),
+        QPLL_DMONITOR_SEL                       =>     ('0'),
+        QPLL_FBDIV                              =>     (QPLL_FBDIV_IN),
+        QPLL_FBDIV_MONITOR_EN                   =>     ('0'),
+        QPLL_FBDIV_RATIO                        =>     (QPLL_FBDIV_RATIO),
+        QPLL_INIT_CFG                           =>     (x"000006"),
+        QPLL_LOCK_CFG                           =>     (x"21E8"),
+        QPLL_LPF                                =>     ("1111"),
+        QPLL_REFCLK_DIV                         =>     (1)
+
+        
+    )
+    port map
+    (
+        ------------- Common Block  - Dynamic Reconfiguration Port (DRP) -----------
+        DRPADDR                         =>      tied_to_ground_vec_i(7 downto 0),
+        DRPCLK                          =>      tied_to_ground_i,
+        DRPDI                           =>      tied_to_ground_vec_i(15 downto 0),
+        DRPDO                           =>      open,
+        DRPEN                           =>      tied_to_ground_i,
+        DRPRDY                          =>      open,
+        DRPWE                           =>      tied_to_ground_i,
+        ---------------------- Common Block  - Ref Clock Ports ---------------------
+        GTGREFCLK                       =>      tied_to_ground_i,
+        GTNORTHREFCLK0                  =>      tied_to_ground_i,
+        GTNORTHREFCLK1                  =>      tied_to_ground_i,
+        GTREFCLK0                       =>      GTREFCLK0_IN,
+        GTREFCLK1                       =>      GTREFCLK1_IN,
+        GTSOUTHREFCLK0                  =>      tied_to_ground_i,
+        GTSOUTHREFCLK1                  =>      tied_to_ground_i,
+        ------------------------- Common Block -  QPLL Ports -----------------------
+        QPLLDMONITOR                    =>      open,
+        ----------------------- Common Block - Clocking Ports ----------------------
+        QPLLOUTCLK                      =>      QPLLOUTCLK_OUT,
+        QPLLOUTREFCLK                   =>      QPLLOUTREFCLK_OUT,
+        REFCLKOUTMONITOR                =>      open,
+        ------------------------- Common Block - QPLL Ports ------------------------
+        QPLLFBCLKLOST                   =>      open,
+        QPLLLOCK                        =>      QPLLLOCK_OUT,
+        QPLLLOCKDETCLK                  =>      QPLLLOCKDETCLK_IN,
+        QPLLLOCKEN                      =>      tied_to_vcc_i,
+        QPLLOUTRESET                    =>      tied_to_ground_i,
+        QPLLPD                          =>      tied_to_vcc_i,
+        QPLLREFCLKLOST                  =>      QPLLREFCLKLOST_OUT,
+        QPLLREFCLKSEL                   =>      QPLLREFCLKSEL_IN,
+        QPLLRESET                       =>      QPLLRESET_IN,
+        QPLLRSVD1                       =>      "0000000000000000",
+        QPLLRSVD2                       =>      "11111",
+        --------------------------------- QPLL Ports -------------------------------
+        BGBYPASSB                       =>      tied_to_vcc_i,
+        BGMONITORENB                    =>      tied_to_vcc_i,
+        BGPDB                           =>      tied_to_vcc_i,
+        BGRCALOVRD                      =>      "11111",
+        PMARSVD                         =>      "00000000",
+        RCALENB                         =>      tied_to_vcc_i
+
+    );
+
+end RTL;
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_common_reset.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_common_reset.vhd
new file mode 100644
index 0000000..3a6ab7b
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_common_reset.vhd
@@ -0,0 +1,154 @@
+--------------------------------------------------------------------------------
+--   ____  ____ 
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_trb3_sync_2gb_common_reset.vhd
+-- /___/   /\     
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+--  Description :     This module performs TX reset and initialization.
+--                     
+--
+--
+-- Module GTX_trb3_sync_2gb_common_reset
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+--*****************************************************************************
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+entity GTX_trb3_sync_2gb_common_reset is 
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic:= '0'  --Reset QPLL
+   );
+end GTX_trb3_sync_2gb_common_reset;
+
+architecture RTL of GTX_trb3_sync_2gb_common_reset is
+
+
+  constant STARTUP_DELAY        : integer := 500;--AR43482: Transceiver needs to wait for 500 ns after configuration
+  constant WAIT_CYCLES          : integer := STARTUP_DELAY / STABLE_CLOCK_PERIOD; -- Number of Clock-Cycles to wait after configuration
+  constant WAIT_MAX             : integer := WAIT_CYCLES + 10;                    -- 500 ns plus some additional margin
+
+
+  signal init_wait_count  : std_logic_vector(7 downto 0) :=(others => '0');
+  signal init_wait_done   : std_logic :='0';
+  signal common_reset_asserted   : std_logic :='0';
+  signal common_reset_i   : std_logic ;
+
+  type rst_type is(
+    INIT, ASSERT_COMMON_RESET);
+    
+  signal state : rst_type := INIT;
+
+begin
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      -- The counter starts running when configuration has finished and 
+      -- the clock is stable. When its maximum count-value has been reached,
+      -- the 500 ns from Answer Record 43482 have been passed.
+      if init_wait_count = WAIT_MAX then
+        init_wait_done <= '1';
+      else
+        init_wait_count <= init_wait_count + 1;
+      end if;
+    end if;
+  end process;
+
+  process(STABLE_CLOCK)
+  begin
+    if rising_edge(STABLE_CLOCK) then
+      if(SOFT_RESET = '1') then
+        state                <= INIT;
+        common_reset_asserted   <= '0';
+        COMMON_RESET   <= '0';
+      else
+        
+        case state is
+          when INIT => 
+            if init_wait_done = '1' then
+              state        <= ASSERT_COMMON_RESET;
+            end if;
+            
+          when ASSERT_COMMON_RESET =>
+             if common_reset_asserted = '0' then
+                COMMON_RESET          <= '1';
+                common_reset_asserted  <= '1';
+              else
+                COMMON_RESET          <= '0';
+              end if;
+           when OTHERS =>
+            state   <= INIT;
+         end case;
+       end if;
+    end if;
+  end process;
+ 
+
+end RTL; 
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_gt_usrclk_source.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_gt_usrclk_source.vhd
new file mode 100644
index 0000000..afb33f4
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_gt_usrclk_source.vhd
@@ -0,0 +1,206 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   / 
+-- /___/  \  /    Vendor: Xilinx 
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_trb3_sync_2gb_gt_usrclk_source.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\ 
+--
+--
+-- Module GTX_trb3_sync_2gb_GT_USRCLK_SOURCE (for use with GTs)
+-- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+
+--***********************************Entity Declaration*******************************
+entity GTX_trb3_sync_2gb_GT_USRCLK_SOURCE is
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXUSRCLKX2_OUT           : out std_logic; --// Modified
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_TXCLK_LOCK_OUT           : out std_logic;
+    GT0_TX_MMCM_RESET_IN         : in std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    Q2_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_OUT                    : out  std_logic
+);
+
+
+end GTX_trb3_sync_2gb_GT_USRCLK_SOURCE;
+
+architecture RTL of GTX_trb3_sync_2gb_GT_USRCLK_SOURCE is
+
+component GTX_TRB3_SYNC_2GB_CLOCK_MODULE is
+generic
+(
+    MULT                : real              := 2.0;
+    DIVIDE              : integer           := 2;    
+    CLK_PERIOD          : real              := 6.4;    
+    OUT0_DIVIDE         : real              := 2.0;
+    OUT1_DIVIDE         : integer           := 2;
+    OUT2_DIVIDE         : integer           := 2;
+    OUT3_DIVIDE         : integer           := 2
+);
+port
+ (-- Clock in ports
+  CLK_IN           : in     std_logic;
+  -- Clock out ports
+  CLK0_OUT          : out    std_logic;
+  CLK1_OUT          : out    std_logic;
+  CLK2_OUT          : out    std_logic;
+  CLK3_OUT          : out    std_logic;
+  -- Status and control signals
+  MMCM_RESET_IN     : in     std_logic;
+  MMCM_LOCKED_OUT   : out    std_logic
+ );
+end component;
+
+--*********************************Wire Declarations**********************************
+
+    signal   tied_to_ground_i     :   std_logic;
+    signal   tied_to_vcc_i        :   std_logic;
+ 
+    signal   gt0_txoutclk_i :   std_logic;
+    signal   gt0_rxoutclk_i :   std_logic;
+
+    attribute syn_noclockbuf : boolean;
+    signal   q2_clk0_gtrefclk :   std_logic;
+    attribute syn_noclockbuf of q2_clk0_gtrefclk : signal is true;
+
+    signal  gt0_txusrclk_i                  : std_logic;
+    signal  gt0_rxusrclk_i                  : std_logic;
+    signal  txoutclk_mmcm0_locked_i         : std_logic;
+    signal  txoutclk_mmcm0_reset_i          : std_logic;
+    signal  gt0_txoutclk_to_mmcm_i          : std_logic;
+
+
+begin
+
+--*********************************** Beginning of Code *******************************
+
+    --  Static signal Assigments    
+    tied_to_ground_i         <= '0';
+    tied_to_vcc_i            <= '1';
+    gt0_txoutclk_i                               <= GT0_TXOUTCLK_IN;
+    gt0_rxoutclk_i                               <= GT0_RXOUTCLK_IN;
+
+    Q2_CLK0_GTREFCLK_OUT                         <= q2_clk0_gtrefclk;
+
+    --IBUFDS_GTE2
+    ibufds_instq2_clk0 : IBUFDS_GTE2  
+    port map
+    (
+        O               => 	q2_clk0_gtrefclk,
+        ODIV2           =>    open,
+        CEB             => 	tied_to_ground_i,
+        I               => 	Q2_CLK0_GTREFCLK_PAD_P_IN,
+        IB              => 	Q2_CLK0_GTREFCLK_PAD_N_IN
+    );
+
+
+    
+    -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
+    -- for improved jitter performance, and to avoid consuming an additional BUFG
+    txoutclk_mmcm0_reset_i                       <= GT0_TX_MMCM_RESET_IN;
+    txoutclk_mmcm0_i : GTX_trb3_sync_2gb_CLOCK_MODULE
+    generic map
+    (
+        MULT                            =>      32.0, --// 28.0 Modified 
+        DIVIDE                          =>      5,
+        CLK_PERIOD                      =>      8.0,
+        OUT0_DIVIDE                     =>      8.0,  --// 7.0 Modified 
+        OUT1_DIVIDE                     =>      4,    --// 1 Modified 
+        OUT2_DIVIDE                     =>      1,
+        OUT3_DIVIDE                     =>      1
+    )
+    port map
+    (
+        CLK0_OUT                        =>      gt0_txusrclk_i,
+        CLK1_OUT                        =>      GT0_TXUSRCLKX2_OUT, --// Modified
+        CLK2_OUT                        =>      open,
+        CLK3_OUT                        =>      open,
+        CLK_IN                          =>      gt0_txoutclk_i,
+        MMCM_LOCKED_OUT                 =>      txoutclk_mmcm0_locked_i,
+        MMCM_RESET_IN                   =>      txoutclk_mmcm0_reset_i
+    );
+
+
+    rxoutclk_bufg1_i : BUFG
+    port map
+    (
+        I                               =>      gt0_rxoutclk_i,
+        O                               =>      gt0_rxusrclk_i
+    );
+
+
+
+ 
+GT0_TXUSRCLK_OUT                             <= gt0_txusrclk_i;
+GT0_TXUSRCLK2_OUT                            <= gt0_txusrclk_i;
+GT0_TXCLK_LOCK_OUT                           <= txoutclk_mmcm0_locked_i;
+GT0_RXUSRCLK_OUT                             <= gt0_rxusrclk_i;
+GT0_RXUSRCLK2_OUT                            <= gt0_rxusrclk_i;
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_support.vhd b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_support.vhd
new file mode 100644
index 0000000..0adacfd
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/GTX_trb3_sync_2gb_support/gtx_trb3_sync_2gb_support.vhd
@@ -0,0 +1,661 @@
+------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor: Xilinx
+-- \   \   \/     Version : 3.5
+--  \   \         Application : 7 Series FPGAs Transceivers Wizard 
+--  /   /         Filename : gtx_trb3_sync_2gb_support.vhd
+-- /___/   /\      
+-- \   \  /  \ 
+--  \___\/\___\
+--
+--  Description : This module instantiates the modules required for
+--                reset and initialisation of the Transceiver
+--
+-- Module GTX_trb3_sync_2gb_support
+-- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
+-- 
+-- 
+-- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES. 
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+--***********************************Entity Declaration************************
+
+entity GTX_trb3_sync_2gb_support is
+generic
+(
+    EXAMPLE_SIM_GTRESET_SPEEDUP             : string    := "TRUE";     -- simulation setting for GT SecureIP model
+    STABLE_CLOCK_PERIOD                     : integer   := 10  
+
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_OUT                    : out  std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_TXUSRCLKX2_OUT                      : out  std_logic; --// Modified
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT  : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT : out std_logic;
+       sysclk_in        : in std_logic
+
+);
+
+end GTX_trb3_sync_2gb_support;
+    
+architecture RTL of GTX_trb3_sync_2gb_support is
+attribute DowngradeIPIdentifiedWarnings: string;
+attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
+
+--**************************Component Declarations*****************************
+
+component GTX_trb3_sync_2gb
+ 
+port
+(
+    SYSCLK_IN                               : in   std_logic;
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_IN                     : in   std_logic;
+    GT0_TX_MMCM_RESET_OUT                   : out  std_logic;
+
+    --_________________________________________________________________________
+    --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cplllockdetclk_in                   : in   std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    -------------------------- Channel - Clocking Ports ------------------------
+    gt0_gtrefclk0_in                        : in   std_logic;
+    gt0_gtrefclk1_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpclk_in                           : in   std_logic;
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+    gt0_rxusrclk_in                         : in   std_logic;
+    gt0_rxusrclk2_in                        : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    gt0_rxoutclk_out                        : out  std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+    gt0_txusrclk_in                         : in   std_logic;
+    gt0_txusrclk2_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclk_out                        : out  std_logic;
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic
+
+);
+
+end component;
+
+component GTX_trb3_sync_2gb_common_reset  
+generic
+(
+      STABLE_CLOCK_PERIOD      : integer := 8        -- Period of the stable clock driving this state-machine, unit is [ns]
+   );
+port
+   (    
+      STABLE_CLOCK             : in std_logic;             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET               : in std_logic;               --User Reset, can be pulled any time
+      COMMON_RESET             : out std_logic  --Reset QPLL
+   );
+end component;
+
+component GTX_trb3_sync_2gb_common 
+generic
+(
+    -- Simulation attributes
+    WRAPPER_SIM_GTRESET_SPEEDUP     : string     :=  "FALSE" ;       -- Set to "TRUE" to speed up sim reset
+    SIM_QPLLREFCLK_SEL              :bit_vector  := "001"
+ 
+);
+port
+(
+    QPLLREFCLKSEL_IN   : in std_logic_vector(2 downto 0);
+    GTREFCLK0_IN : in std_logic;
+    GTREFCLK1_IN      : in std_logic;
+    QPLLLOCK_OUT : out std_logic;
+    QPLLLOCKDETCLK_IN : in std_logic;
+    QPLLOUTCLK_OUT : out std_logic;
+    QPLLOUTREFCLK_OUT : out std_logic;
+    QPLLREFCLKLOST_OUT : out std_logic;    
+    QPLLRESET_IN : in std_logic
+
+);
+
+end component;
+component GTX_trb3_sync_2gb_GT_USRCLK_SOURCE 
+port
+(
+ 
+    GT0_TXUSRCLK_OUT             : out std_logic;
+    GT0_TXUSRCLK2_OUT            : out std_logic;
+    GT0_TXUSRCLKX2_OUT           : out std_logic; --// Modified
+    GT0_TXOUTCLK_IN              : in  std_logic;
+    GT0_TXCLK_LOCK_OUT           : out std_logic;
+    GT0_TX_MMCM_RESET_IN         : in std_logic;
+    GT0_RXUSRCLK_OUT             : out std_logic;
+    GT0_RXUSRCLK2_OUT            : out std_logic;
+    GT0_RXOUTCLK_IN              : in  std_logic;
+    Q2_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_OUT                    : out  std_logic
+);
+end component;
+
+--***********************************Parameter Declarations********************
+
+    constant DLY : time := 1 ns;
+
+--************************** Register Declarations ****************************
+
+    signal   gt0_txfsmresetdone_i            : std_logic;
+signal   gt0_rxfsmresetdone_i            : std_logic;
+    signal   gt0_txfsmresetdone_r            : std_logic;
+    signal   gt0_txfsmresetdone_r2           : std_logic;
+signal   gt0_rxresetdone_r               : std_logic;
+signal   gt0_rxresetdone_r2              : std_logic;
+signal   gt0_rxresetdone_r3              : std_logic;
+
+
+signal   reset_pulse                     : std_logic_vector(3 downto 0);
+    signal   reset_counter  :   unsigned(5 downto 0) := "000000";
+
+
+--**************************** Wire Declarations ******************************
+    -------------------------- GT Wrapper Wires ------------------------------
+    --________________________________________________________________________
+    --________________________________________________________________________
+    --GT0  (X1Y10)
+
+    --------------------------------- CPLL Ports -------------------------------
+    signal  gt0_cpllfbclklost_i             : std_logic;
+    signal  gt0_cplllock_i                  : std_logic;
+    signal  gt0_cpllrefclklost_i            : std_logic;
+    signal  gt0_cpllreset_i                 : std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    signal  gt0_drpaddr_i                   : std_logic_vector(8 downto 0);
+    signal  gt0_drpdi_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpdo_i                     : std_logic_vector(15 downto 0);
+    signal  gt0_drpen_i                     : std_logic;
+    signal  gt0_drprdy_i                    : std_logic;
+    signal  gt0_drpwe_i                     : std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    signal  gt0_dmonitorout_i               : std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    signal  gt0_eyescanreset_i              : std_logic;
+    signal  gt0_rxuserrdy_i                 : std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    signal  gt0_eyescandataerror_i          : std_logic;
+    signal  gt0_eyescantrigger_i            : std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    signal  gt0_rxdata_i                    : std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    signal  gt0_rxdisperr_i                 : std_logic_vector(1 downto 0);
+    signal  gt0_rxnotintable_i              : std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    signal  gt0_gtxrxp_i                    : std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    signal  gt0_gtxrxn_i                    : std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    signal  gt0_rxdlyen_i                   : std_logic;
+    signal  gt0_rxdlysreset_i               : std_logic;
+    signal  gt0_rxdlysresetdone_i           : std_logic;
+    signal  gt0_rxphalign_i                 : std_logic;
+    signal  gt0_rxphaligndone_i             : std_logic;
+    signal  gt0_rxphalignen_i               : std_logic;
+    signal  gt0_rxphdlyreset_i              : std_logic;
+    signal  gt0_rxphmonitor_i               : std_logic_vector(4 downto 0);
+    signal  gt0_rxphslipmonitor_i           : std_logic_vector(4 downto 0);
+    -------------------- Receive Ports - RX Equailizer Ports -------------------
+    signal  gt0_rxlpmhfhold_i               : std_logic;
+    signal  gt0_rxlpmlfhold_i               : std_logic;
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    signal  gt0_rxdfelpmreset_i             : std_logic;
+    signal  gt0_rxmonitorout_i              : std_logic_vector(6 downto 0);
+    signal  gt0_rxmonitorsel_i              : std_logic_vector(1 downto 0);
+    --------------- Receive Ports - RX Fabric Output Control Ports -------------
+    signal  gt0_rxoutclk_i                  : std_logic;
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    signal  gt0_gtrxreset_i                 : std_logic;
+    signal  gt0_rxpmareset_i                : std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    signal  gt0_rxcharisk_i                 : std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    signal  gt0_rxresetdone_i               : std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    signal  gt0_gttxreset_i                 : std_logic;
+    signal  gt0_txuserrdy_i                 : std_logic;
+    ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
+    signal  gt0_txdlyen_i                   : std_logic;
+    signal  gt0_txdlysreset_i               : std_logic;
+    signal  gt0_txdlysresetdone_i           : std_logic;
+    signal  gt0_txphalign_i                 : std_logic;
+    signal  gt0_txphaligndone_i             : std_logic;
+    signal  gt0_txphalignen_i               : std_logic;
+    signal  gt0_txphdlyreset_i              : std_logic;
+    signal  gt0_txphinit_i                  : std_logic;
+    signal  gt0_txphinitdone_i              : std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    signal  gt0_txdata_i                    : std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    signal  gt0_gtxtxn_i                    : std_logic;
+    signal  gt0_gtxtxp_i                    : std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    signal  gt0_txoutclk_i                  : std_logic;
+    signal  gt0_txoutclkfabric_i            : std_logic;
+    signal  gt0_txoutclkpcs_i               : std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    signal  gt0_txcharisk_i                 : std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    signal  gt0_txresetdone_i               : std_logic;
+
+    --____________________________COMMON PORTS________________________________
+    signal gt0_qplllock_i : std_logic;
+    signal gt0_qpllrefclklost_i  : std_logic;
+    signal gt0_qpllreset_i  : std_logic;
+    signal gt0_qpllreset_t  : std_logic;
+     signal gt0_qplloutclk_i  : std_logic;
+     signal gt0_qplloutrefclk_i : std_logic;
+
+    ------------------------------- Global Signals -----------------------------
+    signal  gt0_tx_system_reset_c           : std_logic;
+    signal  gt0_rx_system_reset_c           : std_logic;
+    signal  tied_to_ground_i                : std_logic;
+    signal  tied_to_ground_vec_i            : std_logic_vector(63 downto 0);
+    signal  tied_to_vcc_i                   : std_logic;
+    signal  tied_to_vcc_vec_i               : std_logic_vector(7 downto 0);
+    signal  drpclk_in_i                     : std_logic;
+    signal  sysclk_in_i                     : std_logic;
+    signal  GTTXRESET_IN                    : std_logic;
+    signal  GTRXRESET_IN                    : std_logic;
+    signal  CPLLRESET_IN                    : std_logic;
+    signal  QPLLRESET_IN                    : std_logic;
+
+    attribute keep: string;
+   ------------------------------- User Clocks ---------------------------------
+    signal    gt0_txusrclk_i                  : std_logic; 
+    signal    gt0_txusrclk2_i                 : std_logic; 
+    signal    gt0_rxusrclk_i                  : std_logic; 
+    signal    gt0_rxusrclk2_i                 : std_logic; 
+    
+    
+    
+    
+    signal    gt0_txmmcm_lock_i               : std_logic;
+    signal    gt0_txmmcm_reset_i              : std_logic;
+    ----------------------------- Reference Clocks ----------------------------
+    
+signal    q2_clk0_refclk_i                : std_logic;
+
+signal commonreset_i : std_logic;
+--**************************** Main Body of Code *******************************
+begin
+
+    --  Static signal Assigments
+tied_to_ground_i                             <= '0';
+tied_to_ground_vec_i                         <= x"0000000000000000";
+tied_to_vcc_i                                <= '1';
+tied_to_vcc_vec_i                            <= "11111111";
+
+     GT0_TX_MMCM_LOCK_OUT <= gt0_txmmcm_lock_i;
+ 
+     gt0_qpllreset_t <= tied_to_vcc_i;
+     gt0_qplloutclk_out <= gt0_qplloutclk_i;
+     gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
+
+
+ 
+      GT0_TXUSRCLK_OUT <= gt0_txusrclk_i; 
+      GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
+      GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
+      GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
+
+
+    
+  
+    gt_usrclk_source : GTX_trb3_sync_2gb_GT_USRCLK_SOURCE
+    port map
+   (
+ 
+        GT0_TXUSRCLK_OUT                =>      gt0_txusrclk_i,
+        GT0_TXUSRCLK2_OUT               =>      gt0_txusrclk2_i,
+		GT0_TXUSRCLKX2_OUT              =>      GT0_TXUSRCLKX2_OUT,  --// Modified
+        GT0_TXOUTCLK_IN                 =>      gt0_txoutclk_i,
+        GT0_TXCLK_LOCK_OUT              =>      gt0_txmmcm_lock_i,
+        GT0_TX_MMCM_RESET_IN            =>      gt0_txmmcm_reset_i,
+        GT0_RXUSRCLK_OUT                =>      gt0_rxusrclk_i,
+        GT0_RXUSRCLK2_OUT               =>      gt0_rxusrclk2_i,
+        GT0_RXOUTCLK_IN                 =>      gt0_rxoutclk_i,
+        Q2_CLK0_GTREFCLK_PAD_N_IN       =>      Q2_CLK0_GTREFCLK_PAD_N_IN,
+        Q2_CLK0_GTREFCLK_PAD_P_IN       =>      Q2_CLK0_GTREFCLK_PAD_P_IN,
+        Q2_CLK0_GTREFCLK_OUT            =>      q2_clk0_refclk_i
+
+    );
+
+sysclk_in_i <= sysclk_in;
+
+    common0_i:GTX_trb3_sync_2gb_common 
+  generic map
+  (
+   WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
+   SIM_QPLLREFCLK_SEL => "001"
+  )
+ port map
+   (
+    QPLLREFCLKSEL_IN    => "001",
+    GTREFCLK0_IN      => q2_clk0_refclk_i,
+    GTREFCLK1_IN      => tied_to_ground_i,
+    QPLLLOCK_OUT => gt0_qplllock_i,
+    QPLLLOCKDETCLK_IN => sysclk_in_i,
+    QPLLOUTCLK_OUT => gt0_qplloutclk_i,
+    QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
+    QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,    
+    QPLLRESET_IN => gt0_qpllreset_t
+
+);
+
+    common_reset_i:GTX_trb3_sync_2gb_common_reset 
+   generic map 
+   (
+      STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD        -- Period of the stable clock driving this state-machine, unit is [ns]
+   )
+   port map
+   (    
+      STABLE_CLOCK => sysclk_in_i,             --Stable Clock, either a stable clock from the PCB
+      SOFT_RESET => soft_reset_tx_in,               --User Reset, can be pulled any time
+      COMMON_RESET => commonreset_i              --Reset QPLL
+   );
+
+
+    GTX_trb3_sync_2gb_init_i : GTX_trb3_sync_2gb
+    port map
+    (
+        sysclk_in                       =>      sysclk_in_i,
+        soft_reset_tx_in                =>      SOFT_RESET_TX_IN,
+        soft_reset_rx_in                =>      SOFT_RESET_RX_IN,
+        dont_reset_on_data_error_in     =>      DONT_RESET_ON_DATA_ERROR_IN,
+        gt0_tx_mmcm_lock_in             =>      gt0_txmmcm_lock_i,
+        gt0_tx_mmcm_reset_out           =>      gt0_txmmcm_reset_i,
+        gt0_tx_fsm_reset_done_out       =>      gt0_tx_fsm_reset_done_out,
+        gt0_rx_fsm_reset_done_out       =>      gt0_rx_fsm_reset_done_out,
+        gt0_data_valid_in               =>      gt0_data_valid_in,
+
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y10)
+
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out           =>      gt0_cpllfbclklost_out,
+        gt0_cplllock_out                =>      gt0_cplllock_out,
+        gt0_cplllockdetclk_in           =>      sysclk_in_i,
+        gt0_cpllreset_in                =>      gt0_cpllreset_in,
+        -------------------------- Channel - Clocking Ports ------------------------
+        gt0_gtrefclk0_in                =>      q2_clk0_refclk_i,
+        gt0_gtrefclk1_in                =>      tied_to_ground_i,
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in                  =>      gt0_drpaddr_in,
+        gt0_drpclk_in                   =>      sysclk_in_i,
+        gt0_drpdi_in                    =>      gt0_drpdi_in,
+        gt0_drpdo_out                   =>      gt0_drpdo_out,
+        gt0_drpen_in                    =>      gt0_drpen_in,
+        gt0_drprdy_out                  =>      gt0_drprdy_out,
+        gt0_drpwe_in                    =>      gt0_drpwe_in,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out             =>      gt0_dmonitorout_out,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in             =>      gt0_eyescanreset_in,
+        gt0_rxuserrdy_in                =>      gt0_rxuserrdy_in,
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out        =>      gt0_eyescandataerror_out,
+        gt0_eyescantrigger_in           =>      gt0_eyescantrigger_in,
+		------------------------- Receive Ports - CDR Ports ------------------------
+		GT0_RXCDRRESET_IN               =>      GT0_RXCDRRESET_IN, --// Modified
+		GT0_RXCDRLOCK_OUT               =>      GT0_RXCDRLOCK_OUT, --// Modified
+        ------------------ Receive Ports - FPGA RX Interface Ports -----------------
+        gt0_rxusrclk_in                 =>      gt0_rxusrclk_i,
+        gt0_rxusrclk2_in                =>      gt0_rxusrclk2_i,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out                  =>      gt0_rxdata_out,
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out               =>      gt0_rxdisperr_out,
+        gt0_rxnotintable_out            =>      gt0_rxnotintable_out,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in                   =>      gt0_gtxrxp_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in                   =>      gt0_gtxrxn_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out             =>      gt0_rxphmonitor_out,
+        gt0_rxphslipmonitor_out         =>      gt0_rxphslipmonitor_out,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in            =>      gt0_rxdfelpmreset_in,
+        gt0_rxmonitorout_out            =>      gt0_rxmonitorout_out,
+        gt0_rxmonitorsel_in             =>      gt0_rxmonitorsel_in,
+        --------------- Receive Ports - RX Fabric Output Control Ports -------------
+        gt0_rxoutclk_out                =>      gt0_rxoutclk_i,
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in                =>      gt0_gtrxreset_in,
+        gt0_rxpmareset_in               =>      gt0_rxpmareset_in,
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out               =>      gt0_rxcharisk_out,
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out             =>      gt0_rxresetdone_out,
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in                =>      gt0_gttxreset_in,
+        gt0_txuserrdy_in                =>      gt0_txuserrdy_in,
+        ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
+        gt0_txusrclk_in                 =>      gt0_txusrclk_i,
+        gt0_txusrclk2_in                =>      gt0_txusrclk2_i,
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in                   =>      gt0_txdata_in,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out                  =>      gt0_gtxtxn_out,
+        gt0_gtxtxp_out                  =>      gt0_gtxtxp_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclk_out                =>      gt0_txoutclk_i,
+        gt0_txoutclkfabric_out          =>      gt0_txoutclkfabric_out,
+        gt0_txoutclkpcs_out             =>      gt0_txoutclkpcs_out,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in                =>      gt0_txcharisk_in,
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out             =>      gt0_txresetdone_out,
+
+
+
+    gt0_qplloutclk_in => gt0_qplloutclk_i,
+    gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
+    );
+
+
+
+end RTL;
+
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_16x8/async_fifo_16x8.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_16x8/async_fifo_16x8.xci
new file mode 100644
index 0000000..de97fd7
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_16x8/async_fifo_16x8.xci
@@ -0,0 +1,423 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_16x8</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_16x8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_256x66/async_fifo_256x66.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_256x66/async_fifo_256x66.xci
new file mode 100644
index 0000000..dd989c8
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_256x66/async_fifo_256x66.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_256x66</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">66</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">66</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">253</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">252</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_256x66</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">253</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">252</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">66</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">66</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_512x32/async_fifo_512x32.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_512x32/async_fifo_512x32.xci
new file mode 100644
index 0000000..bee83ca
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_512x32/async_fifo_512x32.xci
@@ -0,0 +1,423 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_512x32</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">508</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_512x32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">508</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_512x99/async_fifo_512x99.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_512x99/async_fifo_512x99.xci
new file mode 100644
index 0000000..107e2d8
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_512x99/async_fifo_512x99.xci
@@ -0,0 +1,423 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_512x99</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">508</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_512x99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">508</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_4096x103/async_fifo_nn_4096x103.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_4096x103/async_fifo_nn_4096x103.xci
new file mode 100644
index 0000000..834804e
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_4096x103/async_fifo_nn_4096x103.xci
@@ -0,0 +1,424 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_nn_4096x103</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">103</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">103</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">4093</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">4092</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_nn_4096x103</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">4093</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">4092</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">103</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">103</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_4096x36/async_fifo_nn_4096x36.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_4096x36/async_fifo_nn_4096x36.xci
new file mode 100644
index 0000000..401533c
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_4096x36/async_fifo_nn_4096x36.xci
@@ -0,0 +1,424 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_nn_4096x36</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">4093</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">4092</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_nn_4096x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">4093</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">4092</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">4096</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">12</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_progfull1900_progempty128_2048x36/async_fifo_nn_progfull1900_progempty128_2048x36.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_progfull1900_progempty128_2048x36/async_fifo_nn_progfull1900_progempty128_2048x36.xci
new file mode 100644
index 0000000..723267c
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_progfull1900_progempty128_2048x36/async_fifo_nn_progfull1900_progempty128_2048x36.xci
@@ -0,0 +1,430 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_nn_progfull1900_progempty128_2048x36</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">2kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">129</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1899</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_nn_progfull1900_progempty128_2048x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">129</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1899</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">Single_Programmable_Empty_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Dout_Reset" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_progfull980_progempty768_FWFT_1024x99/async_fifo_nn_progfull980_progempty768_FWFT_1024x99.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_progfull980_progempty768_FWFT_1024x99/async_fifo_nn_progfull980_progempty768_FWFT_1024x99.xci
new file mode 100644
index 0000000..eefb69f
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_progfull980_progempty768_FWFT_1024x99/async_fifo_nn_progfull980_progempty768_FWFT_1024x99.xci
@@ -0,0 +1,426 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_nn_progfull980_progempty768_FWFT_1024x99</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_nn_progfull980_progempty768_FWFT_1024x99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">99</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">Single_Programmable_Empty_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Flags_Reset_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_th_1024x36/async_fifo_nn_th_1024x36.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_th_1024x36/async_fifo_nn_th_1024x36.xci
new file mode 100644
index 0000000..8e9ca06
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_th_1024x36/async_fifo_nn_th_1024x36.xci
@@ -0,0 +1,422 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_nn_th_1024x36</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">129</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1021</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1020</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_nn_th_1024x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">128</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">129</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1021</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1020</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">Single_Programmable_Empty_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_thfull_FWFT_2048x36/async_fifo_nn_thfull_FWFT_2048x36.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_thfull_FWFT_2048x36/async_fifo_nn_thfull_FWFT_2048x36.xci
new file mode 100644
index 0000000..2b011dd
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_thfull_FWFT_2048x36/async_fifo_nn_thfull_FWFT_2048x36.xci
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_nn_thfull_FWFT_2048x36</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">2kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1914</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1913</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_nn_thfull_FWFT_2048x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1914</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1913</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">2048</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_thfull_FWFT_512x36/async_fifo_nn_thfull_FWFT_512x36.xci b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_thfull_FWFT_512x36/async_fifo_nn_thfull_FWFT_512x36.xci
new file mode 100644
index 0000000..997fbae
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/async_fifo_nn_thfull_FWFT_512x36/async_fifo_nn_thfull_FWFT_512x36.xci
@@ -0,0 +1,428 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>async_fifo_nn_thfull_FWFT_512x36</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">511</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">async_fifo_nn_thfull_FWFT_512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">511</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">First_Word_Fall_Through</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fifo_Implementation" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Performance_Options" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Full_Type" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/clock100to200/clock100to200.xci b/data_concentrator/sources/xilinx/Kintex7/clock100to200/clock100to200.xci
new file mode 100644
index 0000000..b2f718c
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/clock100to200/clock100to200.xci
@@ -0,0 +1,522 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>clock100to200</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock   Freq (MHz)    Input Jitter (UI)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">Min_O_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">14.250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">7.125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___200.000______0.000______50.0_______89.238_____78.520</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no_CLK_OUT2_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clock100to200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">89.238</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">78.520</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">90.666</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">79.592</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clock100to200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">Min_O_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">14.250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">7.125</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_USED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.JITTER_SEL" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/fifo_18x512_oreg/fifo_18x512_oreg.xci b/data_concentrator/sources/xilinx/Kintex7/fifo_18x512_oreg/fifo_18x512_oreg.xci
new file mode 100644
index 0000000..cad98c0
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/fifo_18x512_oreg/fifo_18x512_oreg.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>fifo_18x512_oreg</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_18x512_oreg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Input_Port</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/fifo_36x16k_oreg/fifo_36x16k_oreg.xci b/data_concentrator/sources/xilinx/Kintex7/fifo_36x16k_oreg/fifo_36x16k_oreg.xci
new file mode 100644
index 0000000..44000d2
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/fifo_36x16k_oreg/fifo_36x16k_oreg.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>fifo_36x16k_oreg</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">16382</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">16381</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">16384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">16384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_36x16k_oreg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">16382</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">16381</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">16384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">16384</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Input_Port</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/fifo_36x32k_oreg/fifo_36x32k_oreg.xci b/data_concentrator/sources/xilinx/Kintex7/fifo_36x32k_oreg/fifo_36x32k_oreg.xci
new file mode 100644
index 0000000..0a59b23
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/fifo_36x32k_oreg/fifo_36x32k_oreg.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>fifo_36x32k_oreg</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">4kx9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">32766</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">32765</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">32768</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">32768</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_36x32k_oreg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">32766</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">32765</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">32768</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">32768</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Input_Port</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/fifo_36x512_oreg/fifo_36x512_oreg.xci b/data_concentrator/sources/xilinx/Kintex7/fifo_36x512_oreg/fifo_36x512_oreg.xci
new file mode 100644
index 0000000..1c05e19
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/fifo_36x512_oreg/fifo_36x512_oreg.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>fifo_36x512_oreg</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">fifo_36x512_oreg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Input_Port</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/pll_in200_out200/pll_in200_out200.xci b/data_concentrator/sources/xilinx/Kintex7/pll_in200_out200/pll_in200_out200.xci
new file mode 100644
index 0000000..e600685
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/pll_in200_out200/pll_in200_out200.xci
@@ -0,0 +1,539 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>pll_in200_out200</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">500.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock   Freq (MHz)    Input Jitter (UI)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________200.000___________500.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">Min_O_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">8.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">5.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">8.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">BUF_IN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___200.000______0.000______50.0______119.192_____71.149</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no_CLK_OUT2_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">PLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">pll_in200_out200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">500.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">500.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">112.745</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">65.553</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFGCE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">pll_in200_out200</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">PS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">Min_O_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">5.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">BUF_IN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT5_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.FEEDBACK_SOURCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.JITTER_OPTIONS" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.JITTER_SEL" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_BANDWIDTH" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_REF_JITTER1" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_REF_JITTER2" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.OVERRIDE_MMCM" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIMITIVE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_IN_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.PRIM_SOURCE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_MIN_POWER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/pll_in200_out200_160_100_80/pll_in200_out200_160_100_80.xci b/data_concentrator/sources/xilinx/Kintex7/pll_in200_out200_160_100_80/pll_in200_out200_160_100_80.xci
new file mode 100644
index 0000000..1b0e4eb
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/pll_in200_out200_160_100_80/pll_in200_out200_160_100_80.xci
@@ -0,0 +1,519 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>pll_in200_out200_160_100_80</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="5.2"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">53.333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">53.33333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock   Freq (MHz)    Input Jitter (UI)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________200.000____________0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">4.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">5.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B">  Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">CLK_OUT1___200.000______0.000______50.0______100.010_____97.786</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">CLK_OUT2___100.000______0.000______50.0______114.523_____97.786</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">CLK_OUT3____80.000______0.000______50.0______119.805_____97.786</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">CLK_OUT4____53.333______0.000______50.0______130.134_____97.786</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Differential_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">pll_in200_out200_160_100_80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">50.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">100.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">97.786</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">114.523</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">97.786</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">119.805</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">97.786</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">80.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">130.134</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">97.786</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">53.33333</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">pll_in200_out200_160_100_80</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">4.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">5.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">4.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">15</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">200.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Differential_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_JITTER" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_USED" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.NUM_OUT_CLKS" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/sync_fifo_512x41/sync_fifo_512x41.xci b/data_concentrator/sources/xilinx/Kintex7/sync_fifo_512x41/sync_fifo_512x41.xci
new file mode 100644
index 0000000..75ae95d
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/sync_fifo_512x41/sync_fifo_512x41.xci
@@ -0,0 +1,422 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>sync_fifo_512x41</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">41</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">41</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x72</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">sync_fifo_512x41</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">510</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">509</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">41</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">41</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">512</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">9</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Depth" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Data_Count_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Data_Count_Width" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/syncfifo_1024x66_almostempty256/syncfifo_1024x66_almostempty256.xci b/data_concentrator/sources/xilinx/Kintex7/syncfifo_1024x66_almostempty256/syncfifo_1024x66_almostempty256.xci
new file mode 100644
index 0000000..c9f97f4
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/syncfifo_1024x66_almostempty256/syncfifo_1024x66_almostempty256.xci
@@ -0,0 +1,418 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>syncfifo_1024x66_almostempty256</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">66</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">66</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">257</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1021</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">syncfifo_1024x66_almostempty256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">256</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">257</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1021</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">66</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">66</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">Single_Programmable_Empty_Threshold_Constant</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Synchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+      <spirit:vendorExtensions>
+        <xilinx:componentInstanceExtensions>
+          <xilinx:configElementInfos>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Input_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Output_Data_Width" xilinx:valueSource="user"/>
+            <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Programmable_Empty_Type" xilinx:valueSource="user"/>
+          </xilinx:configElementInfos>
+        </xilinx:componentInstanceExtensions>
+      </spirit:vendorExtensions>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x16/xilinx_fifo_18x16.xci b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x16/xilinx_fifo_18x16.xci
new file mode 100644
index 0000000..8ec6a02
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x16/xilinx_fifo_18x16.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xilinx_fifo_18x16</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xilinx_fifo_18x16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x1k/xilinx_fifo_18x1k.xci b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x1k/xilinx_fifo_18x1k.xci
new file mode 100644
index 0000000..0c1357b
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x1k/xilinx_fifo_18x1k.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xilinx_fifo_18x1k</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1021</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xilinx_fifo_18x1k</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1021</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x1k_datacount/xilinx_fifo_18x1k_datacount.xci b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x1k_datacount/xilinx_fifo_18x1k_datacount.xci
new file mode 100644
index 0000000..394b69e
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x1k_datacount/xilinx_fifo_18x1k_datacount.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xilinx_fifo_18x1k_datacount</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1021</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xilinx_fifo_18x1k_datacount</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1021</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x32/xilinx_fifo_18x32.xci b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x32/xilinx_fifo_18x32.xci
new file mode 100644
index 0000000..f49368a
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x32/xilinx_fifo_18x32.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xilinx_fifo_18x32</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">30</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xilinx_fifo_18x32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">30</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">29</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">5</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x64/xilinx_fifo_18x64.xci b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x64/xilinx_fifo_18x64.xci
new file mode 100644
index 0000000..410235e
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_18x64/xilinx_fifo_18x64.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xilinx_fifo_18x64</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">62</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">61</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xilinx_fifo_18x64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">62</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">61</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">6</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_19x16_obuf/xilinx_fifo_19x16_obuf.xci b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_19x16_obuf/xilinx_fifo_19x16_obuf.xci
new file mode 100644
index 0000000..5ee7fa0
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_19x16_obuf/xilinx_fifo_19x16_obuf.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xilinx_fifo_19x16_obuf</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xilinx_fifo_19x16_obuf</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">Single_Programmable_Full_Threshold_Input_Port</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_dualport_18x1k/xilinx_fifo_dualport_18x1k.xci b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_dualport_18x1k/xilinx_fifo_dualport_18x1k.xci
new file mode 100644
index 0000000..a7b5563
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_dualport_18x1k/xilinx_fifo_dualport_18x1k.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xilinx_fifo_dualport_18x1k</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">1021</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">1020</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xilinx_fifo_dualport_18x1k</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Independent_Clocks_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">1021</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">1020</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_sbuf/xilinx_fifo_sbuf.xci b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_sbuf/xilinx_fifo_sbuf.xci
new file mode 100644
index 0000000..02c1fb5
--- /dev/null
+++ b/data_concentrator/sources/xilinx/Kintex7/xilinx_fifo_sbuf/xilinx_fifo_sbuf.xci
@@ -0,0 +1,407 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>xilinx.com</spirit:vendor>
+  <spirit:library>xci</spirit:library>
+  <spirit:name>unknown</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:componentInstances>
+    <spirit:componentInstance>
+      <spirit:instanceName>xilinx_fifo_sbuf</spirit:instanceName>
+      <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="fifo_generator" spirit:version="13.0"/>
+      <spirit:configurableElementValues>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CORE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.MASTER_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.READ_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.SLAVE_ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.WRITE_CLK.FREQ_HZ">100000000</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADD_NGC_CONSTRAINT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_APPLICATION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDATA_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TDEST_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXIS_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ADDR_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ARUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_AWUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_BUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LEN_WIDTH">8</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_LOCK_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_RUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_WUSER_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLOCK">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_VALUE">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_RDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WACH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WDCH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_WIDTH_WRCH">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_RST_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_WIDTH">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RLOCS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_RST_SYNC">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ERROR_INJECTION_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FULL_FLAGS_RST_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_EMPTY">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ALMOST_FULL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDATA">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TDEST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TKEEP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TLAST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TREADY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TSTRB">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXIS_TUSER">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ARUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_AWUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_BUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RD_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_RUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WR_CHANNEL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_WUSER">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_BACKUP">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DATA_COUNTS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INT_CLK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MASTER_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEMINIT_FILE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_PROG_FLAGS_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RD_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SLAVE_CE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SRST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_VALID">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_ACK">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_WR_RST">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_AXIS">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_RDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WACH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WDCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IMPLEMENTATION_TYPE_WRCH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_WR_PNTR_VAL">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEMORY_TYPE">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MIF_FILE_NAME">BlankString</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MSGON_VAL">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OPTIMIZATION_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_SAVING_MODE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRELOAD_REGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_AXIS">1kx18</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_RDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WACH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WDCH">1kx36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_FIFO_TYPE_WRCH">512x36</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_THRESH_NEGATE_VAL">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_EMPTY_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WACH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_THRESH_NEGATE_VAL">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PROG_FULL_TYPE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_DEPTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RD_PNTR_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REG_SLICE_MODE_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SYNCHRONIZER_STAGE">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_UNDERFLOW_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_OVERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_COMMON_UNDERFLOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_SETTINGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DOUT_RST">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_AXIS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_RDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WACH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WDCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC_WRCH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_EMBEDDED_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FIFO16_FLAGS">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FWFT_DATA_COUNT">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PIPELINE_REG">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VALID_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WACH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WDCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRCH_TYPE">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_ACK_LOW">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DATA_COUNT_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_AXIS">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_RDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WACH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WDCH">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_DEPTH_WRCH">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_FREQ">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_AXIS">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_RDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WACH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WDCH">10</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_PNTR_WIDTH_WRCH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WR_RESPONSE_LATENCY">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDRESS_WIDTH">32</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AWUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Add_NGC_Constraint_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Empty_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Almost_Full_Flag">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Enable_Type">Slave_Interface_Clock_Enable</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Clock_Type_AXI">Common_Clock</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">xilinx_fifo_sbuf</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DATA_WIDTH">64</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Timing_Violations_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Dout_Reset_Value">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_axis">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_rdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wach">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wdch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Assert_Value_wrch">1022</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Empty_Threshold_Negate_Value">3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Overflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Common_Underflow">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Data_Counts_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_Type">Hard_ECC</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_ECC_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Reset_Synchronization">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_Safety_Circuit">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TLAST">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_TREADY">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_axis">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_rdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wach">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wdch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Application_Type_wrch">Data_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_axis">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_rdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wach">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wdch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FIFO_Implementation_wrch">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fifo_Implementation">Common_Clock_Block_RAM</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Flags_Reset_Value">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value">14</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_axis">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_rdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wach">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wdch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Assert_Value_wrch">1023</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Full_Threshold_Negate_Value">13</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_ACLKEN">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TKEEP">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.HAS_TSTRB">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Dbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_rdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wach">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wdch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Inject_Sbit_Error_wrch">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Data_Width">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_axis">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_rdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wach">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wdch">1024</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Input_Depth_wrch">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Master_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Data_Width">19</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Depth">16</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Register_Type">Embedded_Reg</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Overflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PROTOCOL">AXI4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Performance_Options">Standard_FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_axis">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_rdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wach">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wdch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Empty_Type_wrch">No_Programmable_Empty_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_axis">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_rdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wach">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wdch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Programmable_Full_Type_wrch">No_Programmable_Full_Threshold</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_axis">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_rdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wach">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wdch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_Slice_Mode_wrch">Fully_Registered</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Pin">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">Asynchronous_Reset</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Slave_interface_Clock_enable_memory_mapped">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDATA_NUM_BYTES">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TDEST_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TID_WIDTH">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TKEEP_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TSTRB_WIDTH">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.TUSER_WIDTH">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Flag_AXI">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Underflow_Sense_AXI">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Dout_Reset">true</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Embedded_Registers_axis">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Extra_Logic">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Valid_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WUSER_Width">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Flag">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Acknowledge_Sense">Active_High</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Clock_Frequency">1</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Data_Count_Width">4</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.asymmetric_port_width">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.axis_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dynamic_power_saving">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecc_pipeline_reg">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_low_latency">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.enable_read_pointer_increment_by2">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.rdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.synchronization_stages_axi">2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_dout_register">false</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wach_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wdch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.wrch_type">FIFO</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">kintex7</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7k325t</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">ffg900</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE">C</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">0</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2015.3</spirit:configurableElementValue>
+        <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
+      </spirit:configurableElementValues>
+    </spirit:componentInstance>
+  </spirit:componentInstances>
+</spirit:design>
diff --git a/data_concentrator/sources/xilinx/fifo_19x16_obuf.vhd b/data_concentrator/sources/xilinx/fifo_19x16_obuf.vhd
new file mode 100644
index 0000000..1230adf
--- /dev/null
+++ b/data_concentrator/sources/xilinx/fifo_19x16_obuf.vhd
@@ -0,0 +1,66 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+
+entity fifo_19x16_obuf is
+port(
+	Data          : in  std_logic_vector(18 downto 0);
+	Clock         : in  std_logic;
+	WrEn          : in  std_logic;
+	RdEn          : in  std_logic;
+	Reset         : in  std_logic;
+	AmFullThresh  : in  std_logic_vector(3 downto 0);
+	Q             : out std_logic_vector(18 downto 0);
+	WCNT          : out std_logic_vector(4 downto 0);
+	Empty         : out std_logic;
+	Full          : out std_logic;
+	AlmostFull    : out std_logic
+);
+end entity;
+
+
+
+
+
+architecture fifo_19x16_obuf_arch of fifo_19x16_obuf is
+
+
+
+component xilinx_fifo_19x16_obuf IS
+port (
+	clk: IN std_logic;
+	din: IN std_logic_VECTOR(18 downto 0);
+	prog_full_thresh: IN std_logic_VECTOR(3 downto 0);
+	rd_en: IN std_logic;
+	rst: IN std_logic;
+	wr_en: IN std_logic;
+	data_count: OUT std_logic_VECTOR(3 downto 0);
+	dout: OUT std_logic_VECTOR(18 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic;
+	prog_full: OUT std_logic
+);
+end component;
+
+
+
+begin
+
+WCNT(4) <= '0';
+
+the_xilinx_fifo_19x16_obuf: xilinx_fifo_19x16_obuf
+port map(
+	clk              => Clock,
+	din              => Data,
+	prog_full_thresh => AmFullThresh,
+	rd_en            => RdEn,
+	rst              => Reset,
+	wr_en            => WrEn,
+	data_count       => WCNT(3 downto 0),
+	dout             => Q,
+	empty            => Empty,
+	full             => Full,
+	prog_full        => AlmostFull
+);
+
+end architecture;
diff --git a/data_concentrator/sources/xilinx/fifo_sbuf.vhd b/data_concentrator/sources/xilinx/fifo_sbuf.vhd
new file mode 100644
index 0000000..26d31e5
--- /dev/null
+++ b/data_concentrator/sources/xilinx/fifo_sbuf.vhd
@@ -0,0 +1,59 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+
+entity fifo_sbuf is
+port(
+	Data: in  std_logic_vector(18 downto 0); 
+	Clock: in  std_logic; 
+	WrEn: in  std_logic; 
+	RdEn: in  std_logic; 
+	Reset: in  std_logic; 
+	Q: out  std_logic_vector(18 downto 0); 
+	Empty: out  std_logic; 
+	Full: out  std_logic; 
+	AlmostFull: out  std_logic
+);
+end entity;
+
+
+
+
+
+architecture fifo_sbuf_arch of fifo_sbuf is
+
+
+
+component xilinx_fifo_sbuf IS
+port (
+	din: IN std_logic_VECTOR(18 downto 0);
+	clk: IN std_logic;
+	wr_en: IN std_logic;
+	rd_en: IN std_logic;
+	rst: IN std_logic;
+	dout: OUT std_logic_VECTOR(18 downto 0);
+	empty: OUT std_logic;
+	full: OUT std_logic;
+	almost_full: OUT std_logic
+);
+end component;
+
+
+
+begin
+
+
+the_xilinx_fifo_sbuf: xilinx_fifo_sbuf
+port map(
+	din              => Data,
+	clk              => Clock,
+	wr_en            => WrEn,
+	rd_en            => RdEn,
+	rst              => Reset,
+	dout             => Q,
+	empty            => Empty,
+	full             => Full,
+	almost_full	     => AlmostFull
+);
+
+end architecture;
diff --git a/data_concentrator/sources/xilinx/fifo_var_oreg.vhd b/data_concentrator/sources/xilinx/fifo_var_oreg.vhd
new file mode 100644
index 0000000..f24da79
--- /dev/null
+++ b/data_concentrator/sources/xilinx/fifo_var_oreg.vhd
@@ -0,0 +1,176 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+entity fifo_var_oreg is
+  generic(
+    FIFO_WIDTH                   : integer range 1 to 64 := 36;
+    FIFO_DEPTH                   : integer range 1 to 16 := 8
+    );
+  port(
+    Data                         : in  std_logic_vector(FIFO_WIDTH-1 downto 0);
+    Clock                        : in  std_logic;
+    WrEn                         : in  std_logic;
+    RdEn                         : in  std_logic;
+    Reset                        : in  std_logic;
+    AmFullThresh                 : in  std_logic_vector(FIFO_DEPTH-1 downto 0);
+    Q                            : out std_logic_vector(FIFO_WIDTH-1 downto 0);
+    WCNT                         : out std_logic_vector(FIFO_DEPTH downto 0);
+    Empty                        : out std_logic;
+    Full                         : out std_logic;
+    AlmostFull                   : out std_logic
+    );
+end entity;
+
+architecture fifo_var_oreg_arch of fifo_var_oreg is
+
+component fifo_18x512_oreg
+  port (
+    clk               : in std_logic;
+    din               : in std_logic_vector(17 downto 0);
+    prog_full_thresh  : in std_logic_vector(8 downto 0);
+    rd_en             : in std_logic;
+    rst               : in std_logic;
+    wr_en             : in std_logic;
+    data_count        : out std_logic_vector(8 downto 0);
+    dout              : out std_logic_vector(17 downto 0);
+    empty             : out std_logic;
+    full              : out std_logic;
+    prog_full         : out std_logic
+    );
+end component;
+
+component fifo_36x512_oreg
+  port (
+    clk               : in std_logic;
+    din               : in std_logic_vector(35 downto 0);
+    prog_full_thresh  : in std_logic_vector(8 downto 0);
+    rd_en             : in std_logic;
+    rst               : in std_logic;
+    wr_en             : in std_logic;
+    data_count        : out std_logic_vector(8 downto 0);
+    dout              : out std_logic_vector(35 downto 0);
+    empty             : out std_logic;
+    full              : out std_logic;
+    prog_full         : out std_logic
+    );
+end component;
+
+
+component fifo_36x16k_oreg
+  port (
+    clk               : in std_logic;
+    din               : in std_logic_vector(35 downto 0);
+    prog_full_thresh  : in std_logic_vector(13 downto 0);
+    rd_en             : in std_logic;
+    rst               : in std_logic;
+    wr_en             : in std_logic;
+    data_count        : out std_logic_vector(13 downto 0);
+    dout              : out std_logic_vector(35 downto 0);
+    empty             : out std_logic;
+    full              : out std_logic;
+    prog_full         : out std_logic
+    );
+end component;
+
+component fifo_36x32k_oreg
+  port (
+    clk               : in std_logic;
+    din               : in std_logic_vector(35 downto 0);
+    prog_full_thresh  : in std_logic_vector(14 downto 0);
+    rd_en             : in std_logic;
+    rst               : in std_logic;
+    wr_en             : in std_logic;
+    data_count        : out std_logic_vector(14 downto 0);
+    dout              : out std_logic_vector(35 downto 0);
+    empty             : out std_logic;
+    full              : out std_logic;
+    prog_full         : out std_logic
+    );
+end component;
+
+begin
+
+assert    (FIFO_DEPTH >= 13 and FIFO_DEPTH <= 14 and FIFO_WIDTH = 36)
+       or (FIFO_DEPTH >= 9 and FIFO_DEPTH <= 9 and FIFO_WIDTH = 18)
+       or (FIFO_DEPTH >= 9 and FIFO_DEPTH <= 9 and FIFO_WIDTH = 36)
+          report "Selected data buffer size not implemented: depth - "&integer'image(FIFO_DEPTH)& ", width + 4 : " &integer'image(FIFO_WIDTH) severity error;
+
+
+
+  gen_36_16k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 14  generate
+    THE_FIFO :  fifo_36x16k_oreg
+      port map(
+        din                    =>  Data,
+        clk                    =>  Clock,
+        wr_en                  =>  WrEn,
+        rd_en                  =>  RdEn,
+        rst                    =>  Reset,
+        prog_full_thresh       =>  AmFullThresh,
+        dout                   =>  Q,
+        data_count             =>  WCNT(13 downto 0),
+        empty                  =>  Empty,
+        full                   =>  Full,
+        prog_full              =>  AlmostFull
+        );
+  end generate;
+
+
+  gen_36_32k : if FIFO_WIDTH = 36 and FIFO_DEPTH = 15  generate
+    THE_FIFO :  fifo_36x32k_oreg
+      port map(
+        din                    =>  Data,
+        clk                    =>  Clock,
+        wr_en                  =>  WrEn,
+        rd_en                  =>  RdEn,
+        rst                    =>  Reset,
+        prog_full_thresh       =>  AmFullThresh,
+        dout                   =>  Q,
+        data_count             =>  WCNT(14 downto 0),
+        empty                  =>  Empty,
+        full                   =>  Full,
+        prog_full              =>  AlmostFull
+        );
+  end generate;
+
+  gen_36_512 : if FIFO_WIDTH = 36 and FIFO_DEPTH = 9  generate
+    THE_FIFO :  fifo_36x512_oreg
+      port map(
+        din                    =>  Data,
+        clk                    =>  Clock,
+        wr_en                  =>  WrEn,
+        rd_en                  =>  RdEn,
+        rst                    =>  Reset,
+        prog_full_thresh       =>  AmFullThresh,
+        dout                   =>  Q,
+        data_count             =>  WCNT(8 downto 0),
+        empty                  =>  Empty,
+        full                   =>  Full,
+        prog_full              =>  AlmostFull
+        );
+  end generate;
+
+  gen_18_512 : if FIFO_WIDTH = 18 and FIFO_DEPTH = 9  generate
+    THE_FIFO :  fifo_18x512_oreg
+      port map(
+        din                    =>  Data,
+        clk                    =>  Clock,
+        wr_en                  =>  WrEn,
+        rd_en                  =>  RdEn,
+        rst                    =>  Reset,
+        prog_full_thresh       =>  AmFullThresh,
+        dout                   =>  Q,
+        data_count             =>  WCNT(8 downto 0),
+        empty                  =>  Empty,
+        full                   =>  Full,
+        prog_full              =>  AlmostFull
+        );
+  end generate;
+
+
+
+end architecture;
diff --git a/data_concentrator/sources/xilinx/jittercleaner_200M.vhd b/data_concentrator/sources/xilinx/jittercleaner_200M.vhd
new file mode 100644
index 0000000..528ec85
--- /dev/null
+++ b/data_concentrator/sources/xilinx/jittercleaner_200M.vhd
@@ -0,0 +1,179 @@
+-- file: pll_in200_out200_clk_wiz.vhd
+-- 
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+--  Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
+--   Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
+------------------------------------------------------------------------------
+-- CLK_OUT1___200.000______0.000______50.0______112.745_____65.553
+--
+------------------------------------------------------------------------------
+-- Input Clock   Freq (MHz)    Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________200.000___________500.000
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity jittercleaner_200M is
+port
+ (
+  clk_in           : in     std_logic;
+  clk_out          : out    std_logic;
+  reset            : in     std_logic;
+  locked           : out    std_logic
+ );
+end jittercleaner_200M;
+
+architecture behavior of jittercleaner_200M is
+  -- Output clock buffering / unused connectors
+  signal clkfbout_pll_in200_out200         : std_logic;
+  signal clkfbout_buf_pll_in200_out200     : std_logic;
+  signal clkfboutb_unused : std_logic;
+  signal clk_out1_pll_in200_out200          : std_logic;
+  signal clkout0b_unused         : std_logic;
+  signal clkout1_unused   : std_logic;
+  signal clkout1b_unused         : std_logic;
+  signal clkout2_unused   : std_logic;
+  signal clkout2b_unused         : std_logic;
+  signal clkout3_unused   : std_logic;
+  signal clkout3b_unused  : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  signal clkout6_unused   : std_logic;
+  -- Dynamic programming unused signals
+  signal do_unused        : std_logic_vector(15 downto 0);
+  signal drdy_unused      : std_logic;
+  -- Dynamic phase shift unused signals
+  signal psdone_unused    : std_logic;
+  signal locked_int : std_logic;
+  -- Unused status signals
+  signal clkfbstopped_unused : std_logic;
+  signal clkinstopped_unused : std_logic;
+  signal reset_high   : std_logic;
+
+begin
+
+
+  -- Clocking PRIMITIVE
+  --------------------------------------
+  -- Instantiation of the MMCM PRIMITIVE
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+  plle2 : PLLE2_ADV
+  generic map
+   (BANDWIDTH            => "HIGH",
+    COMPENSATION         => "ZHOLD",
+    DIVCLK_DIVIDE        => 1,
+    CLKFBOUT_MULT        => 9,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKOUT0_DIVIDE       => 9,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKIN1_PERIOD        => 5.0)
+  port map
+    -- Output clocks
+   (
+    CLKFBOUT            => clkfbout_pll_in200_out200,
+    CLKOUT0             => clk_out1_pll_in200_out200,
+    CLKOUT1             => clkout1_unused,
+    CLKOUT2             => clkout2_unused,
+    CLKOUT3             => clkout3_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    -- Input clock control
+    CLKFBIN             => clkfbout_buf_pll_in200_out200,
+    CLKIN1              => clk_in,
+    CLKIN2              => '0',
+    -- Tied to always select the primary input clock
+    CLKINSEL            => '1',
+    -- Ports for dynamic reconfiguration
+    DADDR               => (others => '0'),
+    DCLK                => '0',
+    DEN                 => '0',
+    DI                  => (others => '0'),
+    DO                  => do_unused,
+    DRDY                => drdy_unused,
+    DWE                 => '0',
+    -- Other control and status signals
+    LOCKED              => locked_int,
+    PWRDWN              => '0',
+    RST                 => reset_high);
+
+  reset_high <= reset; 
+  locked <= locked_int;
+
+  -- Output buffering
+  -------------------------------------
+
+  clkf_buf : BUFG
+  port map
+   (O => clkfbout_buf_pll_in200_out200,
+    I => clkfbout_pll_in200_out200);
+
+
+
+  clkout1_buf : BUFG
+  port map
+   (O   => clk_out,
+    I   => clk_out1_pll_in200_out200);
+
+
+
+end behavior;
diff --git a/data_concentrator/sources/xilinx/lattice_ecp2m_fifo.vhd b/data_concentrator/sources/xilinx/lattice_ecp2m_fifo.vhd
new file mode 100644
index 0000000..1b5b553
--- /dev/null
+++ b/data_concentrator/sources/xilinx/lattice_ecp2m_fifo.vhd
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+package lattice_ecp2m_fifo is
+
+  component fifo_var_oreg is
+    generic(
+      FIFO_WIDTH                   : integer range 1 to 64 := 36;
+      FIFO_DEPTH                   : integer range 1 to 16 := 8
+      );
+    port(
+      Data                         : in  std_logic_vector(FIFO_WIDTH-1 downto 0);
+      Clock                        : in  std_logic;
+      WrEn                         : in  std_logic;
+      RdEn                         : in  std_logic;
+      Reset                        : in  std_logic;
+      AmFullThresh                 : in  std_logic_vector(FIFO_DEPTH-1 downto 0);
+      Q                            : out std_logic_vector(FIFO_WIDTH-1 downto 0);
+      WCNT                         : out std_logic_vector(FIFO_DEPTH downto 0);
+      Empty                        : out std_logic;
+      Full                         : out std_logic;
+      AlmostFull                   : out std_logic
+      );
+  end component;
+
+end package;
diff --git a/data_concentrator/sources/xilinx/serdesDualMUXwrapper.vhd b/data_concentrator/sources/xilinx/serdesDualMUXwrapper.vhd
new file mode 100644
index 0000000..1b92205
--- /dev/null
+++ b/data_concentrator/sources/xilinx/serdesDualMUXwrapper.vhd
@@ -0,0 +1,783 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   18-07-2013
+-- Module Name:   serdesQuadMUXwrapper
+-- Description:   Module with a quad serdes/GTX with synchronized transmit frequency and 16 bits bus
+-- Modifications:
+--   29-08-2014   ADCCLOCKFREQUENCY added: SODA clock at 80MHz 
+--   27-01-2015   SCI interface removed
+--   29-02-2015   txUsrClkDiv2 removed
+--   04-05-2015   version for Kintex7
+--   26-05-2015   version with only two fibers
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+----------------------------------------------------------------------------------
+-- serdesQuadMUXwrapper
+-- Quad serdes/GTX tranceiver for PANDA Front End Electronics and Multiplexer with synchronised transmitted data.
+--
+--
+--
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     refClk : Reference clock for the serdes, synchronous with transmitted data
+--     refClk_P : differential input pad for Reference clock for GTP/GTX, if internal clock cannot be used (Xilinx), now used for one of the reference clocks
+--     refClk_N : differential input pad for Reference clock for GTP/GTX, if internal clock cannot be used (Xilinx), now used for one of the reference clocks
+--     sysClk : Local bus system clock for serdes control interface and LEDs
+--     gtpReset : reset serdes
+--     refClkIn : reference clock from other part of QUAD, for common GTX module
+--     txUsrClk : clock for the synchronous data to be transmitted, SODA clock
+--   For channel0 in quad serdes :
+--     G0_txData : transmit data, clocked with refClk that is synchrouous with SODA
+--     G0_rxP,G0_rxN :  differential input to the serdes
+--     G0_LOS : no fiber signal detected
+--     G0_txCharIsK0 : data is K-character
+--   For channel1 in quad serdes :
+--     G1_txData : transmit data, clocked with refClk that is synchrouous with SODA
+--     G1_rxP,G0_rxN :  differential input to the serdes
+--     G1_LOS : no fiber signal detected
+--     G1_txCharIsK0 : data is K-character
+--   For channel2 in quad serdes :
+--     G2_txData : transmit data, clocked with refClk that is synchrouous with SODA
+--     G2_rxP,G0_rxN :  differential input to the serdes
+--     G2_LOS : no fiber signal detected
+--     G2_txCharIsK0 : data is K-character
+--   For channel3 in quad serdes :
+--     G3_txData : transmit data, clocked with refClk that is synchrouous with SODA
+--     G3_rxP,G0_rxN :  differential input to the serdes
+--     G3_LOS : no fiber signal detected
+--     G3_txCharIsK0 : data is K-character
+--   GT0_QPLLOUTCLK_IN : QPLL reference clock, needed for Xilinx
+--   GT0_QPLLOUTREFCLK_IN : QPLL reference clock, needed for Xilinx
+-- 
+-- Outputs:
+--     refClkOut : reference clock output
+--     refClk_OK : indicates if refClkOut is stable (PLL locked) (always 1 for Lattice serdes)
+--     txpll_clocks : clock used at GTX transmitter
+--   For channel0 in quad serdes  :
+--     G0_rxData : Data received, clocked with G0_rxUsrClk
+--     G0_txP,G0_txN : differential transmit outputs of the serdes
+--     G0_rxUsrClk : clock for received data
+--     G0_rxLocked : Receiver is locked to incomming data
+--     G0_rxNotInTable : Error in received data
+--     G0_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G0_rxCharIsK0 : received data is K-character
+--   For channel1 in quad serdes :
+--     G1_rxData : Data received, clocked with G1_rxUsrClk
+--     G1_txP,G0_txN : differential transmit outputs of the serdes
+--     G1_rxUsrClk : clock for received data
+--     G1_rxLocked : Receiver is locked to incomming data
+--     G1_rxNotInTable : Error in received data
+--     G1_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G1_rxCharIsK0 : received data is K-character
+--   For channel2 in quad serdes :
+--     G2_rxData : Data received, clocked with G2_rxUsrClk
+--     G2_txP,G0_txN : differential transmit outputs of the serdes
+--     G2_rxUsrClk : clock for received data
+--     G2_rxLocked : Receiver is locked to incomming data
+--     G2_rxNotInTable : Error in received data
+--     G2_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G2_rxCharIsK0 : received data is K-character
+--   For channel3 in quad serdes :
+--     G3_rxData : Data received, clocked with G3_rxUsrClk
+--     G3_txP,G0_txN : differential transmit outputs of the serdes
+--     G3_rxUsrClk : clock for received data
+--     G3_rxLocked : Receiver is locked to incomming data
+--     G3_rxNotInTable : Error in received data
+--     G3_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G3_rxCharIsK0 : received data is K-character
+--     LEDs_link_ok : serdes status for LED on extension board : link ok
+--     LEDs_rx : serdes status for LED on extension board : receive
+--     LEDs_tx : serdes status for LED on extension board : transmit
+-- 
+-- 
+-- Components:
+--     GTX_quadSODA_support : wrapper module for GTX, produced by IP core generator
+--     DC_data8to16 : data from 8 bits to 16 bits on half clock speed
+--     DC_data16to8 : data from 16 bits to 8 bits on double clock speed
+--     clock100to200 : clock doubler : 100MHz to 200MHz
+--     sync_bit : Synchronization for 1 bit cross clock signal
+--
+----------------------------------------------------------------------------------
+
+entity serdesQuadMUXwrapper is 
+	port ( 	
+		refClk                  : in  std_logic;
+		refClk_P                : in  std_logic := '0';
+		refClk_N                : in  std_logic := '1';
+		sysClk                  : in  std_logic;
+		gtpReset                : in  std_logic;
+		
+		refClk_OK               : out std_logic;
+		txpll_clocks            : out std_logic_vector(3 downto 0);
+		
+		G0_txData               : in  std_logic_vector (7 downto 0);
+		G0_rxData               : out  std_logic_vector (7 downto 0);
+		G0_txP                  : out  std_logic;
+		G0_txN                  : out  std_logic;
+		G0_rxP                  : in  std_logic;
+		G0_rxN                  : in  std_logic;
+		G0_LOS                  : in std_logic;
+		G0_rxUsrClk             : out  std_logic; -- 200MHz
+		G0_rxLocked             : out  std_logic;
+		G0_rxNotInTable         : out  std_logic;
+		G0_txLocked             : out  std_logic;
+		G0_txCharIsK0           : in  std_logic;
+		G0_rxCharIsK0           : out  std_logic;
+
+		G1_txData               : in  std_logic_vector (7 downto 0);
+		G1_rxData               : out  std_logic_vector (7 downto 0);
+		G1_txP                  : out  std_logic;
+		G1_txN                  : out  std_logic;
+		G1_rxP                  : in  std_logic;
+		G1_rxN                  : in  std_logic;
+		G1_LOS                  : in std_logic;
+		G1_rxUsrClk             : out  std_logic; -- 200MHz
+		G1_rxLocked             : out  std_logic;
+		G1_rxNotInTable         : out  std_logic;
+		G1_txLocked             : out  std_logic;
+		G1_txCharIsK0           : in  std_logic;
+		G1_rxCharIsK0           : out  std_logic;
+		
+		G2_txData               : in  std_logic_vector (7 downto 0);
+		G2_rxData               : out  std_logic_vector (7 downto 0);
+		G2_txP                  : out  std_logic;
+		G2_txN                  : out  std_logic;
+		G2_rxP                  : in  std_logic;
+		G2_rxN                  : in  std_logic;
+		G2_LOS                  : in std_logic;
+		G2_rxUsrClk             : out  std_logic; -- 200MHz
+		G2_rxLocked             : out  std_logic;
+		G2_rxNotInTable         : out  std_logic;
+		G2_txLocked             : out  std_logic;
+		G2_txCharIsK0           : in  std_logic;
+		G2_rxCharIsK0           : out  std_logic;		
+		
+		G3_txData               : in  std_logic_vector (7 downto 0);
+		G3_rxData               : out  std_logic_vector (7 downto 0);
+		G3_txP                  : out  std_logic;
+		G3_txN                  : out  std_logic;
+		G3_rxP                  : in  std_logic;
+		G3_rxN                  : in  std_logic;
+		G3_LOS                  : in std_logic;
+		G3_rxUsrClk             : out  std_logic; -- 200MHz
+		G3_rxLocked             : out  std_logic;
+		G3_rxNotInTable         : out  std_logic;
+		G3_txLocked             : out  std_logic;
+		G3_txCharIsK0           : in  std_logic;
+		G3_rxCharIsK0           : out  std_logic;
+		
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+
+		GT0_QPLLOUTCLK_IN       : in std_logic := '0';
+		GT0_QPLLOUTREFCLK_IN    : in std_logic := '0';
+		testword0               : out std_logic_vector (35 downto 0) := (others => '0'); 
+		testword0clock          : out std_logic := '0'
+		);
+end serdesQuadMUXwrapper;
+
+architecture Behavioral of serdesQuadMUXwrapper is
+		
+component GTX_dualSODA_support
+generic
+(
+    -- Simulation attributes
+    EXAMPLE_SIM_GTRESET_SPEEDUP    : string    := "FALSE";    -- Set to TRUE to speed up sim reset
+    STABLE_CLOCK_PERIOD            : integer   := 16 
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT1_TXUSRCLK_OUT                        : out  std_logic;
+    GT1_TXUSRCLK2_OUT                       : out  std_logic;
+    GT1_RXUSRCLK_OUT                        : out  std_logic;
+    GT1_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+        --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+   
+    --_________________________________________________________________________
+        --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt1_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt1_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+   
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_IN  : in std_logic;
+     GT0_QPLLOUTREFCLK_IN : in std_logic;
+		sysclk_in        : in std_logic;
+		q2_clk1_gtrefclk : in std_logic;  --//modification
+		q3_clk0_gtrefclk : in std_logic   --//modification
+);
+end component;
+
+component DC_data8to16 is
+	port ( 
+		clock_in                : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		kchar_in                : in std_logic;
+		clock_out               : in std_logic;
+		data_out                : out std_logic_vector(15 downto 0);
+		kchar_out               : out std_logic_vector(1 downto 0)
+	);
+end component;
+
+component DC_data16to8 is
+	port ( 
+		clock_in                : in std_logic;
+        data_in                 : in std_logic_vector(15 downto 0);
+        kchar_in                : in std_logic_vector(1 downto 0);
+        notintable_in           : in std_logic_vector(1 downto 0);
+        clock_out               : out std_logic;
+        data_out                : out std_logic_vector(7 downto 0);
+        kchar_out               : out std_logic;
+        notintable_out          : out std_logic
+	);
+end component;
+
+component clock100to200 is
+	port
+	(
+		clk_in1                 : in std_logic;
+		clk_out1                : out std_logic;
+		reset                   : in std_logic;
+		locked                  : out std_logic
+	);
+end component;
+
+component sync_bit is
+	port (
+		clock       : in  std_logic;
+		data_in     : in  std_logic;
+		data_out    : out std_logic
+	);
+end component;
+
+    constant DLY : time := 1 ns;
+signal      gt0_txusrclkX2_i                        : std_logic;
+
+signal      gt0_txusrclk2_i                         : std_logic;
+signal      gt1_txusrclk2_i                         : std_logic;
+signal      gt2_txusrclk2_i                         : std_logic;
+signal      gt3_txusrclk2_i                         : std_logic;
+signal      gt0_rxusrclk2_i                         : std_logic;
+signal      gt1_rxusrclk2_i                         : std_logic;
+signal      gt2_rxusrclk2_i                         : std_logic;
+signal      gt3_rxusrclk2_i                         : std_logic;
+
+signal      gt0_txdata_i                            : std_logic_vector(15 downto 0);
+signal      gt1_txdata_i                            : std_logic_vector(15 downto 0);
+signal      gt2_txdata_i                            : std_logic_vector(15 downto 0);
+signal      gt3_txdata_i                            : std_logic_vector(15 downto 0);
+signal      gt0_txcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt1_txcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt2_txcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt3_txcharisk_i                         : std_logic_vector(1 downto 0);
+
+signal      gt0_rxdata_i                            : std_logic_vector(15 downto 0);
+signal      gt1_rxdata_i                            : std_logic_vector(15 downto 0);
+signal      gt2_rxdata_i                            : std_logic_vector(15 downto 0);
+signal      gt3_rxdata_i                            : std_logic_vector(15 downto 0);
+signal      gt0_rxnotintable_i                      : std_logic_vector(1 downto 0);
+signal      gt1_rxnotintable_i                      : std_logic_vector(1 downto 0);
+signal      gt2_rxnotintable_i                      : std_logic_vector(1 downto 0);
+signal      gt3_rxnotintable_i                      : std_logic_vector(1 downto 0);
+signal      gt0_rxcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt1_rxcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt2_rxcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt3_rxcharisk_i                         : std_logic_vector(1 downto 0);
+
+signal      gt0_gtrxreset_i                         : std_logic;
+signal      gt1_gtrxreset_i                         : std_logic;
+signal      gt2_gtrxreset_i                         : std_logic;
+signal      gt3_gtrxreset_i                         : std_logic;
+signal      gt0_gttxreset_i                         : std_logic;
+signal      gt1_gttxreset_i                         : std_logic;
+signal      gt2_gttxreset_i                         : std_logic;
+signal      gt3_gttxreset_i                         : std_logic;
+signal      gt0_txresetdone_i                       : std_logic;
+signal      gt1_txresetdone_i                       : std_logic;
+signal      gt2_txresetdone_i                       : std_logic;
+signal      gt3_txresetdone_i                       : std_logic;
+	
+signal      gt0_rxresetdone_i                       : std_logic;
+signal      gt1_rxresetdone_i                       : std_logic;
+signal      gt2_rxresetdone_i                       : std_logic;
+signal      gt3_rxresetdone_i                       : std_logic;
+
+	
+--************************** Register Declarations ****************************
+attribute   ASYNC_REG                               : string;
+signal      gt_txfsmresetdone_i                     : std_logic;
+signal      gt_txfsmresetdone_r                     : std_logic;
+signal      gt_txfsmresetdone_r2                    : std_logic;
+attribute   ASYNC_REG of gt_txfsmresetdone_r        : signal is "TRUE";
+attribute   ASYNC_REG of gt_txfsmresetdone_r2       : signal is "TRUE";
+signal      gt0_txfsmresetdone_i                    : std_logic;
+signal      gt0_txfsmresetdone_r                    : std_logic;
+signal      gt0_txfsmresetdone_r2                   : std_logic;
+attribute   ASYNC_REG of gt0_txfsmresetdone_r       : signal is "TRUE";
+attribute   ASYNC_REG of gt0_txfsmresetdone_r2      : signal is "TRUE";
+signal      gt0_rxresetdone_r                       : std_logic;
+signal      gt0_rxresetdone_r2                      : std_logic;
+signal      gt0_rxresetdone_r3                      : std_logic;
+attribute   ASYNC_REG of gt0_rxresetdone_r          : signal is "TRUE";
+attribute   ASYNC_REG of gt0_rxresetdone_r2         : signal is "TRUE";
+attribute   ASYNC_REG of gt0_rxresetdone_r3         : signal is "TRUE";
+signal      gt1_txfsmresetdone_i                    : std_logic;
+signal      gt1_txfsmresetdone_r                    : std_logic;
+signal      gt1_txfsmresetdone_r2                   : std_logic;
+attribute   ASYNC_REG of gt1_txfsmresetdone_r       : signal is "TRUE";
+attribute   ASYNC_REG of gt1_txfsmresetdone_r2      : signal is "TRUE";
+signal      gt1_rxresetdone_r                       : std_logic;
+signal      gt1_rxresetdone_r2                      : std_logic;
+signal      gt1_rxresetdone_r3                      : std_logic;
+attribute   ASYNC_REG of gt1_rxresetdone_r          : signal is "TRUE";
+attribute   ASYNC_REG of gt1_rxresetdone_r2         : signal is "TRUE";
+attribute   ASYNC_REG of gt1_rxresetdone_r3         : signal is "TRUE";
+
+
+       begin
+G2_rxData <= (others => '0');
+G2_txP <= '0';
+G2_txN <= '0';
+G2_rxUsrClk <= '0';
+G2_rxLocked <= '0';
+G2_rxNotInTable <= '0';
+G2_txLocked <= '0';
+G2_rxCharIsK0 <= '0';
+
+
+G3_rxData <= (others => '0');
+G3_txP <= '0';
+G3_txN <= '0';
+G3_rxUsrClk <= '0';
+G3_rxLocked <= '0';
+G3_rxNotInTable <= '0';
+G3_txLocked <= '0';
+G3_rxCharIsK0 <= '0';
+
+		
+txpll_clocks(0) <= gt0_txusrclkX2_i;
+txpll_clocks(1) <= gt0_txusrclkX2_i;
+txpll_clocks(2) <= gt0_txusrclkX2_i;
+txpll_clocks(3) <= gt0_txusrclkX2_i;
+
+clock100to200a: clock100to200 port map(
+		clk_in1 => gt0_txusrclk2_i,
+		clk_out1 => gt0_txusrclkX2_i,
+		reset => '0',
+		locked => open);
+
+
+DC_data8to16_0: DC_data8to16 port map(
+		clock_in => gt0_txusrclkX2_i,
+		data_in => G0_txData,
+		kchar_in => G0_txCharIsK0,
+		clock_out => gt0_txusrclk2_i,
+		data_out => gt0_txdata_i,
+		kchar_out => gt0_txcharisk_i);
+DC_data8to16_1: DC_data8to16 port map(
+		clock_in => gt0_txusrclkX2_i,
+		data_in => G1_txData,
+		kchar_in => G1_txCharIsK0,
+		clock_out => gt0_txusrclk2_i,
+		data_out => gt1_txdata_i,
+		kchar_out => gt1_txcharisk_i);
+
+		
+DC_data16to8_0: DC_data16to8 port map(
+		clock_in => gt0_rxusrclk2_i,
+		data_in => gt0_rxdata_i,
+		kchar_in => gt0_rxcharisk_i,
+		notintable_in => gt0_rxnotintable_i,
+		clock_out => G0_rxUsrClk,
+		data_out => G0_rxData,
+		kchar_out => G0_rxCharIsK0,
+		notintable_out => G0_rxNotInTable);
+DC_data16to8_1: DC_data16to8 port map(
+		clock_in => gt1_rxusrclk2_i,
+		data_in => gt1_rxdata_i,
+		kchar_in => gt1_rxcharisk_i,
+		notintable_in => gt1_rxnotintable_i,
+		clock_out => G1_rxUsrClk,
+		data_out => G1_rxData,
+		kchar_out => G1_rxCharIsK0,
+		notintable_out => G1_rxNotInTable);
+
+GTX_dualSODA_support1: GTX_dualSODA_support port map(
+	SOFT_RESET_TX_IN => gtpReset,
+	SOFT_RESET_RX_IN => gtpReset,
+	DONT_RESET_ON_DATA_ERROR_IN => '0',
+	Q2_CLK1_GTREFCLK_PAD_N_IN => '0', -- not used, IBUFDS_GTE2 buffer is at top level
+	Q2_CLK1_GTREFCLK_PAD_P_IN => '0', -- not used, IBUFDS_GTE2 buffer is at top level
+	
+	GT0_TX_FSM_RESET_DONE_OUT => gt0_txfsmresetdone_i,
+	GT0_RX_FSM_RESET_DONE_OUT => open,
+	GT0_DATA_VALID_IN => '1',
+	GT1_TX_FSM_RESET_DONE_OUT => gt1_txfsmresetdone_i,
+	GT1_RX_FSM_RESET_DONE_OUT => open,
+	GT1_DATA_VALID_IN => '1',
+ 
+    GT0_TXUSRCLK_OUT => open,
+    GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+    GT0_RXUSRCLK_OUT => open,
+    GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ 
+    GT1_TXUSRCLK_OUT => open,
+    GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
+    GT1_RXUSRCLK_OUT => open,
+    GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
+ 
+	--_____________________________________________________________________
+	--_____________________________________________________________________
+	--GT0  (X1Y12)
+
+	--------------------------------- CPLL Ports -------------------------------
+	gt0_cpllfbclklost_out => open,
+	gt0_cplllock_out => refClk_OK,
+	gt0_cpllreset_in => '0',
+	---------------------------- Channel - DRP Ports  --------------------------
+	gt0_drpaddr_in => (others => '0'),
+	gt0_drpdi_in => (others => '0'),
+	gt0_drpdo_out => open,
+	gt0_drpen_in => '0',
+	gt0_drprdy_out => open,
+	gt0_drpwe_in => '0',
+	--------------------------- Digital Monitor Ports --------------------------
+	gt0_dmonitorout_out => open,
+	--------------------- RX Initialization and Reset Ports --------------------
+	gt0_eyescanreset_in => '0',
+	gt0_rxuserrdy_in => '0',
+	-------------------------- RX Margin Analysis Ports ------------------------
+	gt0_eyescandataerror_out => open,
+	gt0_eyescantrigger_in => '0',
+	------------------ Receive Ports - FPGA RX interface Ports -----------------
+	gt0_rxdata_out => gt0_rxdata_i,
+	------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+	gt0_rxdisperr_out => open,
+	gt0_rxnotintable_out => gt0_rxnotintable_i,
+	--------------------------- Receive Ports - RX AFE -------------------------
+	gt0_gtxrxp_in => G0_rxP,
+	------------------------ Receive Ports - RX AFE Ports ----------------------
+	gt0_gtxrxn_in => G0_rxN,
+	------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+	gt0_rxphmonitor_out => open,
+	gt0_rxphslipmonitor_out => open,
+	--------------------- Receive Ports - RX Equalizer Ports -------------------
+	gt0_rxdfelpmreset_in => '0',
+	gt0_rxmonitorout_out => open,
+	gt0_rxmonitorsel_in => "00",
+	------------- Receive Ports - RX Initialization and Reset Ports ------------
+	gt0_gtrxreset_in => gt0_gtrxreset_i,
+	gt0_rxpmareset_in => '0',
+	------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+	gt0_rxcharisk_out => gt0_rxcharisk_i,
+	-------------- Receive Ports -RX Initialization and Reset Ports ------------
+	gt0_rxresetdone_out => gt0_rxresetdone_i,
+	--------------------- TX Initialization and Reset Ports --------------------
+	gt0_gttxreset_in => gt0_gttxreset_i,
+	gt0_txuserrdy_in => '0',
+	------------------ Transmit Ports - TX Data Path interface -----------------
+	gt0_txdata_in => gt0_txdata_i,
+	---------------- Transmit Ports - TX Driver and OOB signaling --------------
+	gt0_gtxtxn_out => G0_txN,
+	gt0_gtxtxp_out => G0_txP,
+	----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+	gt0_txoutclkfabric_out => testword0(35),
+	gt0_txoutclkpcs_out => testword0(34),
+	--------------------- Transmit Ports - TX Gearbox Ports --------------------
+	gt0_txcharisk_in => gt0_txcharisk_i,
+	------------- Transmit Ports - TX Initialization and Reset Ports -----------
+	gt0_txresetdone_out => gt0_txresetdone_i,
+	
+	--_____________________________________________________________________
+	--_____________________________________________________________________
+	--GT1  (X1Y13)
+
+	--------------------------------- CPLL Ports -------------------------------
+	gt1_cpllfbclklost_out => open,
+	gt1_cplllock_out => open,
+	gt1_cpllreset_in => '0',
+	---------------------------- Channel - DRP Ports  --------------------------
+	gt1_drpaddr_in => (others => '0'),
+	gt1_drpdi_in => (others => '0'),
+	gt1_drpdo_out => open,
+	gt1_drpen_in => '0',
+	gt1_drprdy_out => open,
+	gt1_drpwe_in => '0',
+	--------------------------- Digital Monitor Ports --------------------------
+	gt1_dmonitorout_out => open,
+	--------------------- RX Initialization and Reset Ports --------------------
+	gt1_eyescanreset_in => '0',
+	gt1_rxuserrdy_in => '0',
+	-------------------------- RX Margin Analysis Ports ------------------------
+	gt1_eyescandataerror_out => open,
+	gt1_eyescantrigger_in => '0',
+	------------------ Receive Ports - FPGA RX interface Ports -----------------
+	gt1_rxdata_out => gt1_rxdata_i,
+	------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+	gt1_rxdisperr_out => open,
+	gt1_rxnotintable_out => gt1_rxnotintable_i,
+	--------------------------- Receive Ports - RX AFE -------------------------
+	gt1_gtxrxp_in => G1_rxP,
+	------------------------ Receive Ports - RX AFE Ports ----------------------
+	gt1_gtxrxn_in => G1_rxN,
+	------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+	gt1_rxphmonitor_out => open,
+	gt1_rxphslipmonitor_out => open,
+	--------------------- Receive Ports - RX Equalizer Ports -------------------
+	gt1_rxdfelpmreset_in => '0',
+	gt1_rxmonitorout_out => open,
+	gt1_rxmonitorsel_in => "00",
+	------------- Receive Ports - RX Initialization and Reset Ports ------------
+	gt1_gtrxreset_in => gt1_gtrxreset_i,
+	gt1_rxpmareset_in => '0',
+	------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+	gt1_rxcharisk_out => gt1_rxcharisk_i,
+	-------------- Receive Ports -RX Initialization and Reset Ports ------------
+	gt1_rxresetdone_out => gt1_rxresetdone_i,
+	--------------------- TX Initialization and Reset Ports --------------------
+	gt1_gttxreset_in => gt1_gttxreset_i,
+	gt1_txuserrdy_in => '0',
+	------------------ Transmit Ports - TX Data Path interface -----------------
+	gt1_txdata_in => gt1_txdata_i,
+	---------------- Transmit Ports - TX Driver and OOB signaling --------------
+	gt1_gtxtxn_out => G1_txN,
+	gt1_gtxtxp_out => G1_txP,
+	----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+	gt1_txoutclkfabric_out => open,
+	gt1_txoutclkpcs_out => open,
+	--------------------- Transmit Ports - TX Gearbox Ports --------------------
+	gt1_txcharisk_in => gt1_txcharisk_i,
+	------------- Transmit Ports - TX Initialization and Reset Ports -----------
+	gt1_txresetdone_out => gt1_txresetdone_i,
+    --____________________________COMMON PORTS________________________________
+	GT0_QPLLOUTCLK_IN  => GT0_QPLLOUTCLK_IN,
+	GT0_QPLLOUTREFCLK_IN => GT0_QPLLOUTREFCLK_IN,
+	sysclk_in => sysClk,
+	q2_clk1_gtrefclk => refClk_P,  --//modification
+	q3_clk0_gtrefclk => refClk_N  --//modification
+    );
+
+    -------------------------- User Module Resets -----------------------------
+    -- All the User Modules are held in reset till the RESETDONE goes high. 
+    -- The RESETDONE is registered a couple of times on USRCLK2 and connected 
+    -- to the reset of the modules
+    
+process(gt0_rxusrclk2_i,gt0_rxresetdone_i,G0_LOS)
+    begin
+        if(gt0_rxresetdone_i = '0') or (G0_LOS='1') then
+            gt0_rxresetdone_r  <= '0'   after DLY;
+            gt0_rxresetdone_r2 <= '0'   after DLY;
+            gt0_rxresetdone_r3 <= '0'   after DLY;
+elsif (gt0_rxusrclk2_i'event and gt0_rxusrclk2_i = '1') then
+            gt0_rxresetdone_r  <= gt0_rxresetdone_i   after DLY;
+            gt0_rxresetdone_r2 <= gt0_rxresetdone_r   after DLY;
+            gt0_rxresetdone_r3  <= gt0_rxresetdone_r2   after DLY;
+        end if;
+    end process;
+process(gt0_txusrclk2_i,gt0_txfsmresetdone_i,gt0_txresetdone_i)
+    begin
+        if(gt0_txfsmresetdone_i = '0') or (gt0_txresetdone_i='0')  then
+            gt0_txfsmresetdone_r  <= '0'   after DLY;
+            gt0_txfsmresetdone_r2 <= '0'   after DLY;
+elsif (gt0_txusrclk2_i'event and gt0_txusrclk2_i = '1') then
+            gt0_txfsmresetdone_r  <= gt0_txfsmresetdone_i   after DLY;
+            gt0_txfsmresetdone_r2 <= gt0_txfsmresetdone_r   after DLY;
+        end if;
+    end process;
+	
+process(gt1_rxusrclk2_i,gt1_rxresetdone_i,G1_LOS)
+    begin
+        if(gt1_rxresetdone_i = '0') or (G1_LOS='1') then
+            gt1_rxresetdone_r  <= '0'   after DLY;
+            gt1_rxresetdone_r2 <= '0'   after DLY;
+            gt1_rxresetdone_r3 <= '0'   after DLY;
+elsif (gt1_rxusrclk2_i'event and gt1_rxusrclk2_i = '1') then
+            gt1_rxresetdone_r  <= gt1_rxresetdone_i   after DLY;
+            gt1_rxresetdone_r2 <= gt1_rxresetdone_r   after DLY;
+            gt1_rxresetdone_r3  <= gt1_rxresetdone_r2   after DLY;
+        end if;
+    end process;
+process(gt1_txusrclk2_i,gt1_txfsmresetdone_i,gt1_txresetdone_i)
+    begin
+        if(gt1_txfsmresetdone_i = '0') or (gt1_txresetdone_i='0')  then
+            gt1_txfsmresetdone_r  <= '0'   after DLY;
+            gt1_txfsmresetdone_r2 <= '0'   after DLY;
+elsif (gt1_txusrclk2_i'event and gt1_txusrclk2_i = '1') then
+            gt1_txfsmresetdone_r  <= gt1_txfsmresetdone_i   after DLY;
+            gt1_txfsmresetdone_r2 <= gt1_txfsmresetdone_r   after DLY;
+        end if;
+    end process;
+	
+
+G0_rxLocked <= gt0_rxresetdone_r3;
+G1_rxLocked <= gt1_rxresetdone_r3;
+
+G0_rxLocked <= gt0_rxresetdone_r3;
+G0_txLocked <= gt0_txfsmresetdone_r2;
+G1_txLocked <= gt1_txfsmresetdone_r2;
+
+
+gt0_gtrxreset_i <= '1' when (G0_LOS='1') or (gtpReset='1') else '0';
+gt1_gtrxreset_i <= '1' when (G1_LOS='1') or (gtpReset='1') else '0';
+
+gt0_gttxreset_i <= '1' when (G0_LOS='1') or (gtpReset='1') else '0';
+gt1_gttxreset_i <= '1' when (G1_LOS='1') or (gtpReset='1') else '0';
+
+
+LEDs_link_ok(0)  <= '1' when (gt0_rxresetdone_r3='1') and (gt0_txfsmresetdone_r2='1') else '0';
+LEDs_link_ok(1)  <= '1' when (gt0_rxresetdone_r3='1') and (gt1_txfsmresetdone_r2='1') else '0';
+LEDs_link_ok(2)  <= '0';
+LEDs_link_ok(3)  <= '0';
+
+LEDs_rx <= (others => '0');
+LEDs_tx <= (others => '0');
+
+			
+end Behavioral;
+
+
+
diff --git a/data_concentrator/sources/xilinx/serdesQuadMUXwrapper.vhd b/data_concentrator/sources/xilinx/serdesQuadMUXwrapper.vhd
new file mode 100644
index 0000000..09451ce
--- /dev/null
+++ b/data_concentrator/sources/xilinx/serdesQuadMUXwrapper.vhd
@@ -0,0 +1,1146 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   18-07-2013
+-- Module Name:   serdesQuadMUXwrapper
+-- Description:   Module with a quad serdes/GTX with synchronized transmit frequency and 16 bits bus
+-- Modifications:
+--   29-08-2014   ADCCLOCKFREQUENCY added: SODA clock at 80MHz 
+--   27-01-2015   SCI interface removed
+--   29-02-2015   txUsrClkDiv2 removed
+--   04-05-2015   version for Kintex7
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+----------------------------------------------------------------------------------
+-- serdesQuadMUXwrapper
+-- Quad serdes/GTX tranceiver for PANDA Front End Electronics and Multiplexer with synchronised transmitted data.
+--
+--
+--
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     gtpClk : Reference clock for the serdes, synchronous with transmitted data
+--     gtpClk_P : differential input pad for Reference clock for GTP/GTX, if internal clock cannot be used (Xilinx)
+--     gtpClk_N : differential input pad for Reference clock for GTP/GTX, if internal clock cannot be used (Xilinx)
+--     sysClk : Local bus system clock for serdes control interface and LEDs
+--     gtpReset : reset serdes
+--     txUsrClk : clock for the synchronous data to be transmitted, SODA clock
+--   For channel0 in quad serdes :
+--     G0_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+--     G0_rxP,G0_rxN :  differential input to the serdes
+--     G0_LOS : no fiber signal detected
+--     G0_txCharIsK0 : data is K-character
+--   For channel1 in quad serdes :
+--     G1_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+--     G1_rxP,G0_rxN :  differential input to the serdes
+--     G1_LOS : no fiber signal detected
+--     G1_txCharIsK0 : data is K-character
+--   For channel2 in quad serdes :
+--     G2_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+--     G2_rxP,G0_rxN :  differential input to the serdes
+--     G2_LOS : no fiber signal detected
+--     G2_txCharIsK0 : data is K-character
+--   For channel3 in quad serdes :
+--     G3_txData : transmit data, clocked with gtpClk that is synchrouous with SODA
+--     G3_rxP,G0_rxN :  differential input to the serdes
+--     G3_LOS : no fiber signal detected
+--     G3_txCharIsK0 : data is K-character
+-- 
+-- Outputs:
+--     refClkOut : reference clock output
+--     refClk_OK : indicates if refClkOut is stable (PLL locked) (always 1 for Lattice serdes)
+--     txpll_clocks : clock used at GTX transmitter
+--   For channel0 in quad serdes  :
+--     G0_rxData : Data received, clocked with G0_rxUsrClk
+--     G0_txP,G0_txN : differential transmit outputs of the serdes
+--     G0_rxUsrClk : clock for received data
+--     G0_rxLocked : Receiver is locked to incomming data
+--     G0_rxNotInTable : Error in received data
+--     G0_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G0_rxCharIsK0 : received data is K-character
+--   For channel1 in quad serdes :
+--     G1_rxData : Data received, clocked with G1_rxUsrClk
+--     G1_txP,G0_txN : differential transmit outputs of the serdes
+--     G1_rxUsrClk : clock for received data
+--     G1_rxLocked : Receiver is locked to incomming data
+--     G1_rxNotInTable : Error in received data
+--     G1_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G1_rxCharIsK0 : received data is K-character
+--   For channel2 in quad serdes :
+--     G2_rxData : Data received, clocked with G2_rxUsrClk
+--     G2_txP,G0_txN : differential transmit outputs of the serdes
+--     G2_rxUsrClk : clock for received data
+--     G2_rxLocked : Receiver is locked to incomming data
+--     G2_rxNotInTable : Error in received data
+--     G2_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G2_rxCharIsK0 : received data is K-character
+--   For channel3 in quad serdes :
+--     G3_rxData : Data received, clocked with G3_rxUsrClk
+--     G3_txP,G0_txN : differential transmit outputs of the serdes
+--     G3_rxUsrClk : clock for received data
+--     G3_rxLocked : Receiver is locked to incomming data
+--     G3_rxNotInTable : Error in received data
+--     G3_txLocked : Transmitter is locked to reference clock (synchronous with SODA)
+--     G3_rxCharIsK0 : received data is K-character
+--     LEDs_link_ok : serdes status for LED on extension board : link ok
+--     LEDs_rx : serdes status for LED on extension board : receive
+--     LEDs_tx : serdes status for LED on extension board : transmit
+-- 
+-- 
+-- Components:
+--     GTX_quadSODA_support : wrapper module for GTX, produced by IP core generator
+--     DC_data8to16 : data from 8 bits to 16 bits on half clock speed
+--     DC_data16to8 : data from 16 bits to 8 bits on double clock speed
+--     clock100to200 : clock doubler : 100MHz to 200MHz
+--     sync_bit : Synchronization for 1 bit cross clock signal
+--
+----------------------------------------------------------------------------------
+
+entity serdesQuadMUXwrapper is 
+	port ( 	
+		gtpClk                  : in  std_logic;
+		gtpClk_P                : in  std_logic := '0';
+		gtpClk_N                : in  std_logic := '1';
+		sysClk                  : in  std_logic;
+		gtpReset                : in  std_logic;
+		
+		refClkOut               : out std_logic;
+		refClk_OK               : out std_logic;
+		txpll_clocks            : out std_logic_vector(3 downto 0);
+		
+		G0_txData               : in  std_logic_vector (7 downto 0);
+		G0_rxData               : out  std_logic_vector (7 downto 0);
+		G0_txP                  : out  std_logic;
+		G0_txN                  : out  std_logic;
+		G0_rxP                  : in  std_logic;
+		G0_rxN                  : in  std_logic;
+		G0_LOS                  : in std_logic;
+		G0_rxUsrClk             : out  std_logic; -- 200MHz
+		G0_rxLocked             : out  std_logic;
+		G0_rxNotInTable         : out  std_logic;
+		G0_txLocked             : out  std_logic;
+		G0_txCharIsK0           : in  std_logic;
+		G0_rxCharIsK0           : out  std_logic;
+
+		G1_txData               : in  std_logic_vector (7 downto 0);
+		G1_rxData               : out  std_logic_vector (7 downto 0);
+		G1_txP                  : out  std_logic;
+		G1_txN                  : out  std_logic;
+		G1_rxP                  : in  std_logic;
+		G1_rxN                  : in  std_logic;
+		G1_LOS                  : in std_logic;
+		G1_rxUsrClk             : out  std_logic; -- 200MHz
+		G1_rxLocked             : out  std_logic;
+		G1_rxNotInTable         : out  std_logic;
+		G1_txLocked             : out  std_logic;
+		G1_txCharIsK0           : in  std_logic;
+		G1_rxCharIsK0           : out  std_logic;
+		
+		G2_txData               : in  std_logic_vector (7 downto 0);
+		G2_rxData               : out  std_logic_vector (7 downto 0);
+		G2_txP                  : out  std_logic;
+		G2_txN                  : out  std_logic;
+		G2_rxP                  : in  std_logic;
+		G2_rxN                  : in  std_logic;
+		G2_LOS                  : in std_logic;
+		G2_rxUsrClk             : out  std_logic; -- 200MHz
+		G2_rxLocked             : out  std_logic;
+		G2_rxNotInTable         : out  std_logic;
+		G2_txLocked             : out  std_logic;
+		G2_txCharIsK0           : in  std_logic;
+		G2_rxCharIsK0           : out  std_logic;		
+		
+		G3_txData               : in  std_logic_vector (7 downto 0);
+		G3_rxData               : out  std_logic_vector (7 downto 0);
+		G3_txP                  : out  std_logic;
+		G3_txN                  : out  std_logic;
+		G3_rxP                  : in  std_logic;
+		G3_rxN                  : in  std_logic;
+		G3_LOS                  : in std_logic;
+		G3_rxUsrClk             : out  std_logic; -- 200MHz
+		G3_rxLocked             : out  std_logic;
+		G3_rxNotInTable         : out  std_logic;
+		G3_txLocked             : out  std_logic;
+		G3_txCharIsK0           : in  std_logic;
+		G3_rxCharIsK0           : out  std_logic;
+		
+		LEDs_link_ok            : out std_logic_vector(0 to 3);
+		LEDs_rx                 : out std_logic_vector(0 to 3); 
+		LEDs_tx                 : out std_logic_vector(0 to 3);
+
+		testword0               : out std_logic_vector (35 downto 0) := (others => '0'); 
+		testword0clock          : out std_logic := '0'
+		);
+end serdesQuadMUXwrapper;
+
+architecture Behavioral of serdesQuadMUXwrapper is
+		
+component GTX_quadSODA_support
+generic
+(
+    -- Simulation attributes
+    EXAMPLE_SIM_GTRESET_SPEEDUP    : string    := "FALSE";    -- Set to TRUE to speed up sim reset
+    STABLE_CLOCK_PERIOD            : integer   := 10 
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK1_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT1_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT1_DATA_VALID_IN                       : in   std_logic;
+    GT2_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT2_DATA_VALID_IN                       : in   std_logic;
+    GT3_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT3_DATA_VALID_IN                       : in   std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT1_TXUSRCLK_OUT                        : out  std_logic;
+    GT1_TXUSRCLK2_OUT                       : out  std_logic;
+    GT1_RXUSRCLK_OUT                        : out  std_logic;
+    GT1_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT2_TXUSRCLK_OUT                        : out  std_logic;
+    GT2_TXUSRCLK2_OUT                       : out  std_logic;
+    GT2_RXUSRCLK_OUT                        : out  std_logic;
+    GT2_RXUSRCLK2_OUT                       : out  std_logic;
+ 
+    GT3_TXUSRCLK_OUT                        : out  std_logic;
+    GT3_TXUSRCLK2_OUT                       : out  std_logic;
+    GT3_RXUSRCLK_OUT                        : out  std_logic;
+    GT3_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+        --GT0  (X1Y12)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+   
+    --_________________________________________________________________________
+        --GT1  (X1Y13)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt1_cpllfbclklost_out                   : out  std_logic;
+    gt1_cplllock_out                        : out  std_logic;
+    gt1_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt1_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt1_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt1_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt1_drpen_in                            : in   std_logic;
+    gt1_drprdy_out                          : out  std_logic;
+    gt1_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt1_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt1_eyescanreset_in                     : in   std_logic;
+    gt1_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt1_eyescandataerror_out                : out  std_logic;
+    gt1_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt1_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt1_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt1_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt1_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt1_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt1_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt1_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt1_rxdfelpmreset_in                    : in   std_logic;
+    gt1_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt1_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt1_gtrxreset_in                        : in   std_logic;
+    gt1_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt1_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt1_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt1_gttxreset_in                        : in   std_logic;
+    gt1_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt1_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt1_gtxtxn_out                          : out  std_logic;
+    gt1_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt1_txoutclkfabric_out                  : out  std_logic;
+    gt1_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt1_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt1_txresetdone_out                     : out  std_logic;
+   
+    --_________________________________________________________________________
+        --GT2  (X1Y14)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt2_cpllfbclklost_out                   : out  std_logic;
+    gt2_cplllock_out                        : out  std_logic;
+    gt2_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt2_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt2_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt2_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt2_drpen_in                            : in   std_logic;
+    gt2_drprdy_out                          : out  std_logic;
+    gt2_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt2_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt2_eyescanreset_in                     : in   std_logic;
+    gt2_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt2_eyescandataerror_out                : out  std_logic;
+    gt2_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt2_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt2_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt2_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt2_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt2_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt2_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt2_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt2_rxdfelpmreset_in                    : in   std_logic;
+    gt2_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt2_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt2_gtrxreset_in                        : in   std_logic;
+    gt2_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt2_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt2_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt2_gttxreset_in                        : in   std_logic;
+    gt2_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt2_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt2_gtxtxn_out                          : out  std_logic;
+    gt2_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt2_txoutclkfabric_out                  : out  std_logic;
+    gt2_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt2_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt2_txresetdone_out                     : out  std_logic;
+   
+    --_________________________________________________________________________
+        --GT3  (X1Y15)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt3_cpllfbclklost_out                   : out  std_logic;
+    gt3_cplllock_out                        : out  std_logic;
+    gt3_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt3_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt3_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt3_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt3_drpen_in                            : in   std_logic;
+    gt3_drprdy_out                          : out  std_logic;
+    gt3_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt3_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt3_eyescanreset_in                     : in   std_logic;
+    gt3_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt3_eyescandataerror_out                : out  std_logic;
+    gt3_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt3_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt3_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt3_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt3_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt3_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt3_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt3_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt3_rxdfelpmreset_in                    : in   std_logic;
+    gt3_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt3_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt3_gtrxreset_in                        : in   std_logic;
+    gt3_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt3_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt3_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt3_gttxreset_in                        : in   std_logic;
+    gt3_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt3_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt3_gtxtxn_out                          : out  std_logic;
+    gt3_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt3_txoutclkfabric_out                  : out  std_logic;
+    gt3_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt3_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt3_txresetdone_out                     : out  std_logic;
+   
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT  : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT : out std_logic;
+        sysclk_in : in std_logic
+);
+end component;
+
+component DC_data8to16 is
+	port ( 
+		clock_in                : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		kchar_in                : in std_logic;
+		clock_out               : in std_logic;
+		data_out                : out std_logic_vector(15 downto 0);
+		kchar_out               : out std_logic_vector(1 downto 0)
+	);
+end component;
+
+component DC_data16to8 is
+	port ( 
+		clock_in                : in std_logic;
+        data_in                 : in std_logic_vector(15 downto 0);
+        kchar_in                : in std_logic_vector(1 downto 0);
+        notintable_in           : in std_logic_vector(1 downto 0);
+        clock_out               : out std_logic;
+        data_out                : out std_logic_vector(7 downto 0);
+        kchar_out               : out std_logic;
+        notintable_out          : out std_logic
+	);
+end component;
+
+component clock100to200 is
+	port
+	(
+		clk_in1                 : in std_logic;
+		clk_out1                : out std_logic;
+		clk_out2                : out std_logic;
+		reset                   : in std_logic;
+		locked                  : out std_logic
+	);
+end component;
+
+component sync_bit is
+	port (
+		clock       : in  std_logic;
+		data_in     : in  std_logic;
+		data_out    : out std_logic
+	);
+end component;
+
+    constant DLY : time := 1 ns;
+signal      gt0_txusrclkX2_i                        : std_logic;
+
+signal      gt0_txusrclk2_i                         : std_logic;
+signal      gt1_txusrclk2_i                         : std_logic;
+signal      gt2_txusrclk2_i                         : std_logic;
+signal      gt3_txusrclk2_i                         : std_logic;
+signal      gt0_rxusrclk2_i                         : std_logic;
+signal      gt1_rxusrclk2_i                         : std_logic;
+signal      gt2_rxusrclk2_i                         : std_logic;
+signal      gt3_rxusrclk2_i                         : std_logic;
+
+signal      gt0_txdata_i                            : std_logic_vector(15 downto 0);
+signal      gt1_txdata_i                            : std_logic_vector(15 downto 0);
+signal      gt2_txdata_i                            : std_logic_vector(15 downto 0);
+signal      gt3_txdata_i                            : std_logic_vector(15 downto 0);
+signal      gt0_txcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt1_txcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt2_txcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt3_txcharisk_i                         : std_logic_vector(1 downto 0);
+
+signal      gt0_rxdata_i                            : std_logic_vector(15 downto 0);
+signal      gt1_rxdata_i                            : std_logic_vector(15 downto 0);
+signal      gt2_rxdata_i                            : std_logic_vector(15 downto 0);
+signal      gt3_rxdata_i                            : std_logic_vector(15 downto 0);
+signal      gt0_rxnotintable_i                      : std_logic_vector(1 downto 0);
+signal      gt1_rxnotintable_i                      : std_logic_vector(1 downto 0);
+signal      gt2_rxnotintable_i                      : std_logic_vector(1 downto 0);
+signal      gt3_rxnotintable_i                      : std_logic_vector(1 downto 0);
+signal      gt0_rxcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt1_rxcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt2_rxcharisk_i                         : std_logic_vector(1 downto 0);
+signal      gt3_rxcharisk_i                         : std_logic_vector(1 downto 0);
+
+signal      gt0_gtrxreset_i                         : std_logic;
+signal      gt1_gtrxreset_i                         : std_logic;
+signal      gt2_gtrxreset_i                         : std_logic;
+signal      gt3_gtrxreset_i                         : std_logic;
+signal      gt0_txresetdone_i                       : std_logic;
+signal      gt1_txresetdone_i                       : std_logic;
+signal      gt2_txresetdone_i                       : std_logic;
+signal      gt3_txresetdone_i                       : std_logic;
+	
+signal      gt0_rxresetdone_i                       : std_logic;
+signal      gt1_rxresetdone_i                       : std_logic;
+signal      gt2_rxresetdone_i                       : std_logic;
+signal      gt3_rxresetdone_i                       : std_logic;
+
+	
+--************************** Register Declarations ****************************
+attribute   ASYNC_REG                               : string;
+signal      gt_txfsmresetdone_i                     : std_logic;
+signal      gt_txfsmresetdone_r                     : std_logic;
+signal      gt_txfsmresetdone_r2                    : std_logic;
+attribute   ASYNC_REG of gt_txfsmresetdone_r        : signal is "TRUE";
+attribute   ASYNC_REG of gt_txfsmresetdone_r2       : signal is "TRUE";
+signal      gt0_txfsmresetdone_i                    : std_logic;
+signal      gt0_txfsmresetdone_r                    : std_logic;
+signal      gt0_txfsmresetdone_r2                   : std_logic;
+attribute   ASYNC_REG of gt0_txfsmresetdone_r       : signal is "TRUE";
+attribute   ASYNC_REG of gt0_txfsmresetdone_r2      : signal is "TRUE";
+signal      gt0_rxresetdone_r                       : std_logic;
+signal      gt0_rxresetdone_r2                      : std_logic;
+signal      gt0_rxresetdone_r3                      : std_logic;
+attribute   ASYNC_REG of gt0_rxresetdone_r          : signal is "TRUE";
+attribute   ASYNC_REG of gt0_rxresetdone_r2         : signal is "TRUE";
+attribute   ASYNC_REG of gt0_rxresetdone_r3         : signal is "TRUE";
+signal      gt1_txfsmresetdone_i                    : std_logic;
+signal      gt1_txfsmresetdone_r                    : std_logic;
+signal      gt1_txfsmresetdone_r2                   : std_logic;
+attribute   ASYNC_REG of gt1_txfsmresetdone_r       : signal is "TRUE";
+attribute   ASYNC_REG of gt1_txfsmresetdone_r2      : signal is "TRUE";
+signal      gt1_rxresetdone_r                       : std_logic;
+signal      gt1_rxresetdone_r2                      : std_logic;
+signal      gt1_rxresetdone_r3                      : std_logic;
+attribute   ASYNC_REG of gt1_rxresetdone_r          : signal is "TRUE";
+attribute   ASYNC_REG of gt1_rxresetdone_r2         : signal is "TRUE";
+attribute   ASYNC_REG of gt1_rxresetdone_r3         : signal is "TRUE";
+signal      gt2_txfsmresetdone_i                    : std_logic;
+signal      gt2_txfsmresetdone_r                    : std_logic;
+signal      gt2_txfsmresetdone_r2                   : std_logic;
+attribute   ASYNC_REG of gt2_txfsmresetdone_r       : signal is "TRUE";
+attribute   ASYNC_REG of gt2_txfsmresetdone_r2      : signal is "TRUE";
+signal      gt2_rxresetdone_r                       : std_logic;
+signal      gt2_rxresetdone_r2                      : std_logic;
+signal      gt2_rxresetdone_r3                      : std_logic;
+attribute   ASYNC_REG of gt2_rxresetdone_r          : signal is "TRUE";
+attribute   ASYNC_REG of gt2_rxresetdone_r2         : signal is "TRUE";
+attribute   ASYNC_REG of gt2_rxresetdone_r3         : signal is "TRUE";
+signal      gt3_txfsmresetdone_i                    : std_logic;
+signal      gt3_txfsmresetdone_r                    : std_logic;
+signal      gt3_txfsmresetdone_r2                   : std_logic;
+attribute   ASYNC_REG of gt3_txfsmresetdone_r       : signal is "TRUE";
+attribute   ASYNC_REG of gt3_txfsmresetdone_r2      : signal is "TRUE";
+signal      gt3_rxresetdone_r                       : std_logic;
+signal      gt3_rxresetdone_r2                      : std_logic;
+signal      gt3_rxresetdone_r3                      : std_logic;
+attribute   ASYNC_REG of gt3_rxresetdone_r          : signal is "TRUE";
+attribute   ASYNC_REG of gt3_rxresetdone_r2         : signal is "TRUE";
+attribute   ASYNC_REG of gt3_rxresetdone_r3         : signal is "TRUE";
+
+
+       begin
+
+refClkOut <= gtpClk;
+refClk_OK <= '1';
+
+txpll_clocks(0) <= gt0_txusrclkX2_i;
+txpll_clocks(1) <= gt0_txusrclkX2_i;
+txpll_clocks(2) <= gt0_txusrclkX2_i;
+txpll_clocks(3) <= gt0_txusrclkX2_i;
+
+clock100to200a: clock100to200 port map(
+		clk_in1 => gt0_txusrclk2_i,
+		clk_out1 => open,
+		clk_out2 => gt0_txusrclkX2_i,
+		reset => '0',
+		locked => open);
+
+
+DC_data8to16_0: DC_data8to16 port map(
+		clock_in => gt0_txusrclkX2_i,
+		data_in => G0_txData,
+		kchar_in => G0_txCharIsK0,
+		clock_out => gt0_txusrclk2_i,
+		data_out => gt0_txdata_i,
+		kchar_out => gt0_txcharisk_i);
+DC_data8to16_1: DC_data8to16 port map(
+		clock_in => gt0_txusrclkX2_i,
+		data_in => G1_txData,
+		kchar_in => G1_txCharIsK0,
+		clock_out => gt0_txusrclk2_i,
+		data_out => gt1_txdata_i,
+		kchar_out => gt1_txcharisk_i);
+DC_data8to16_2: DC_data8to16 port map(
+		clock_in => gt0_txusrclkX2_i,
+		data_in => G2_txData,
+		kchar_in => G2_txCharIsK0,
+		clock_out => gt0_txusrclk2_i,
+		data_out => gt2_txdata_i,
+		kchar_out => gt2_txcharisk_i);
+DC_data8to16_3: DC_data8to16 port map(
+		clock_in => gt0_txusrclkX2_i,
+		data_in => G3_txData,
+		kchar_in => G3_txCharIsK0,
+		clock_out => gt0_txusrclk2_i,
+		data_out => gt3_txdata_i,
+		kchar_out => gt3_txcharisk_i);
+		
+DC_data16to8_0: DC_data16to8 port map(
+		clock_in => gt0_rxusrclk2_i,
+		data_in => gt0_rxdata_i,
+		kchar_in => gt0_rxcharisk_i,
+		notintable_in => gt0_rxnotintable_i,
+		clock_out => G0_rxUsrClk,
+		data_out => G0_rxData,
+		kchar_out => G0_rxCharIsK0,
+		notintable_out => G0_rxNotInTable);
+DC_data16to8_1: DC_data16to8 port map(
+		clock_in => gt1_rxusrclk2_i,
+		data_in => gt1_rxdata_i,
+		kchar_in => gt1_rxcharisk_i,
+		notintable_in => gt1_rxnotintable_i,
+		clock_out => G1_rxUsrClk,
+		data_out => G1_rxData,
+		kchar_out => G1_rxCharIsK0,
+		notintable_out => G1_rxNotInTable);
+DC_data16to8_2: DC_data16to8 port map(
+		clock_in => gt2_rxusrclk2_i,
+		data_in => gt2_rxdata_i,
+		kchar_in => gt2_rxcharisk_i,
+		notintable_in => gt2_rxnotintable_i,
+		clock_out => G2_rxUsrClk,
+		data_out => G2_rxData,
+		kchar_out => G2_rxCharIsK0,
+		notintable_out => G2_rxNotInTable);
+DC_data16to8_3: DC_data16to8 port map(
+		clock_in => gt3_rxusrclk2_i,
+		data_in => gt3_rxdata_i,
+		kchar_in => gt3_rxcharisk_i,
+		notintable_in => gt3_rxnotintable_i,
+		clock_out => G3_rxUsrClk,
+		data_out => G3_rxData,
+		kchar_out => G3_rxCharIsK0,
+		notintable_out => G3_rxNotInTable);
+		
+GTX_quadSODA_support1: GTX_quadSODA_support port map(
+	SOFT_RESET_TX_IN => gtpReset,
+	SOFT_RESET_RX_IN => gtpReset,
+	DONT_RESET_ON_DATA_ERROR_IN => '0',
+	Q2_CLK1_GTREFCLK_PAD_N_IN => gtpClk_N,
+	Q2_CLK1_GTREFCLK_PAD_P_IN => gtpClk_P,
+	
+	GT0_TX_FSM_RESET_DONE_OUT => gt0_txfsmresetdone_i,
+	GT0_RX_FSM_RESET_DONE_OUT => open,
+	GT0_DATA_VALID_IN => '1',
+	GT1_TX_FSM_RESET_DONE_OUT => gt1_txfsmresetdone_i,
+	GT1_RX_FSM_RESET_DONE_OUT => open,
+	GT1_DATA_VALID_IN => '1',
+	GT2_TX_FSM_RESET_DONE_OUT => gt2_txfsmresetdone_i,
+	GT2_RX_FSM_RESET_DONE_OUT => open,
+	GT2_DATA_VALID_IN => '1',
+	GT3_TX_FSM_RESET_DONE_OUT => gt3_txfsmresetdone_i,
+	GT3_RX_FSM_RESET_DONE_OUT => open,
+	GT3_DATA_VALID_IN => '1',
+ 
+    GT0_TXUSRCLK_OUT => open,
+    GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
+    GT0_RXUSRCLK_OUT => open,
+    GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
+ 
+    GT1_TXUSRCLK_OUT => open,
+    GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
+    GT1_RXUSRCLK_OUT => open,
+    GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
+ 
+    GT2_TXUSRCLK_OUT => open,
+    GT2_TXUSRCLK2_OUT => gt2_txusrclk2_i,
+    GT2_RXUSRCLK_OUT => open,
+    GT2_RXUSRCLK2_OUT => gt2_rxusrclk2_i,
+ 
+    GT3_TXUSRCLK_OUT => open,
+    GT3_TXUSRCLK2_OUT => gt3_txusrclk2_i,
+    GT3_RXUSRCLK_OUT => open,
+    GT3_RXUSRCLK2_OUT => gt3_rxusrclk2_i,
+
+	--_____________________________________________________________________
+	--_____________________________________________________________________
+	--GT0  (X1Y12)
+
+	--------------------------------- CPLL Ports -------------------------------
+	gt0_cpllfbclklost_out => open,
+	gt0_cplllock_out => open,
+	gt0_cpllreset_in => '0',
+	---------------------------- Channel - DRP Ports  --------------------------
+	gt0_drpaddr_in => (others => '0'),
+	gt0_drpdi_in => (others => '0'),
+	gt0_drpdo_out => open,
+	gt0_drpen_in => '0',
+	gt0_drprdy_out => open,
+	gt0_drpwe_in => '0',
+	--------------------------- Digital Monitor Ports --------------------------
+	gt0_dmonitorout_out => open,
+	--------------------- RX Initialization and Reset Ports --------------------
+	gt0_eyescanreset_in => '0',
+	gt0_rxuserrdy_in => '0',
+	-------------------------- RX Margin Analysis Ports ------------------------
+	gt0_eyescandataerror_out => open,
+	gt0_eyescantrigger_in => '0',
+	------------------ Receive Ports - FPGA RX interface Ports -----------------
+	gt0_rxdata_out => gt0_rxdata_i,
+	------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+	gt0_rxdisperr_out => open,
+	gt0_rxnotintable_out => gt0_rxnotintable_i,
+	--------------------------- Receive Ports - RX AFE -------------------------
+	gt0_gtxrxp_in => G0_rxP,
+	------------------------ Receive Ports - RX AFE Ports ----------------------
+	gt0_gtxrxn_in => G0_rxN,
+	------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+	gt0_rxphmonitor_out => open,
+	gt0_rxphslipmonitor_out => open,
+	--------------------- Receive Ports - RX Equalizer Ports -------------------
+	gt0_rxdfelpmreset_in => '0',
+	gt0_rxmonitorout_out => open,
+	gt0_rxmonitorsel_in => "00",
+	------------- Receive Ports - RX Initialization and Reset Ports ------------
+	gt0_gtrxreset_in => gt0_gtrxreset_i,
+	gt0_rxpmareset_in => '0',
+	------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+	gt0_rxcharisk_out => gt0_rxcharisk_i,
+	-------------- Receive Ports -RX Initialization and Reset Ports ------------
+	gt0_rxresetdone_out => gt0_rxresetdone_i,
+	--------------------- TX Initialization and Reset Ports --------------------
+	gt0_gttxreset_in => '0',
+	gt0_txuserrdy_in => '0',
+	------------------ Transmit Ports - TX Data Path interface -----------------
+	gt0_txdata_in => gt0_txdata_i,
+	---------------- Transmit Ports - TX Driver and OOB signaling --------------
+	gt0_gtxtxn_out => G0_txN,
+	gt0_gtxtxp_out => G0_txP,
+	----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+	gt0_txoutclkfabric_out => testword0(35),
+	gt0_txoutclkpcs_out => testword0(34),
+	--------------------- Transmit Ports - TX Gearbox Ports --------------------
+	gt0_txcharisk_in => gt0_txcharisk_i,
+	------------- Transmit Ports - TX Initialization and Reset Ports -----------
+	gt0_txresetdone_out => gt0_txresetdone_i,
+
+
+
+
+	--_____________________________________________________________________
+	--_____________________________________________________________________
+	--GT1  (X1Y13)
+
+	--------------------------------- CPLL Ports -------------------------------
+	gt1_cpllfbclklost_out => open,
+	gt1_cplllock_out => open,
+	gt1_cpllreset_in => '0',
+	---------------------------- Channel - DRP Ports  --------------------------
+	gt1_drpaddr_in => (others => '0'),
+	gt1_drpdi_in => (others => '0'),
+	gt1_drpdo_out => open,
+	gt1_drpen_in => '0',
+	gt1_drprdy_out => open,
+	gt1_drpwe_in => '0',
+	--------------------------- Digital Monitor Ports --------------------------
+	gt1_dmonitorout_out => open,
+	--------------------- RX Initialization and Reset Ports --------------------
+	gt1_eyescanreset_in => '0',
+	gt1_rxuserrdy_in => '0',
+	-------------------------- RX Margin Analysis Ports ------------------------
+	gt1_eyescandataerror_out => open,
+	gt1_eyescantrigger_in => '0',
+	------------------ Receive Ports - FPGA RX interface Ports -----------------
+	gt1_rxdata_out => gt1_rxdata_i,
+	------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+	gt1_rxdisperr_out => open,
+	gt1_rxnotintable_out => gt1_rxnotintable_i,
+	--------------------------- Receive Ports - RX AFE -------------------------
+	gt1_gtxrxp_in => G1_rxP,
+	------------------------ Receive Ports - RX AFE Ports ----------------------
+	gt1_gtxrxn_in => G1_rxN,
+	------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+	gt1_rxphmonitor_out => open,
+	gt1_rxphslipmonitor_out => open,
+	--------------------- Receive Ports - RX Equalizer Ports -------------------
+	gt1_rxdfelpmreset_in => '0',
+	gt1_rxmonitorout_out => open,
+	gt1_rxmonitorsel_in => "00",
+	------------- Receive Ports - RX Initialization and Reset Ports ------------
+	gt1_gtrxreset_in => gt1_gtrxreset_i,
+	gt1_rxpmareset_in => '0',
+	------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+	gt1_rxcharisk_out => gt1_rxcharisk_i,
+	-------------- Receive Ports -RX Initialization and Reset Ports ------------
+	gt1_rxresetdone_out => gt1_rxresetdone_i,
+	--------------------- TX Initialization and Reset Ports --------------------
+	gt1_gttxreset_in => '0',
+	gt1_txuserrdy_in => '0',
+	------------------ Transmit Ports - TX Data Path interface -----------------
+	gt1_txdata_in => gt1_txdata_i,
+	---------------- Transmit Ports - TX Driver and OOB signaling --------------
+	gt1_gtxtxn_out => G1_txN,
+	gt1_gtxtxp_out => G1_txP,
+	----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+	gt1_txoutclkfabric_out => open,
+	gt1_txoutclkpcs_out => open,
+	--------------------- Transmit Ports - TX Gearbox Ports --------------------
+	gt1_txcharisk_in => gt1_txcharisk_i,
+	------------- Transmit Ports - TX Initialization and Reset Ports -----------
+	gt1_txresetdone_out => gt1_txresetdone_i,
+
+
+
+
+	--_____________________________________________________________________
+	--_____________________________________________________________________
+	--GT2  (X1Y14)
+
+	--------------------------------- CPLL Ports -------------------------------
+	gt2_cpllfbclklost_out => open,
+	gt2_cplllock_out => open,
+	gt2_cpllreset_in => '0',
+	---------------------------- Channel - DRP Ports  --------------------------
+	gt2_drpaddr_in => (others => '0'),
+	gt2_drpdi_in => (others => '0'),
+	gt2_drpdo_out => open,
+	gt2_drpen_in => '0',
+	gt2_drprdy_out => open,
+	gt2_drpwe_in => '0',
+	--------------------------- Digital Monitor Ports --------------------------
+	gt2_dmonitorout_out => open,
+	--------------------- RX Initialization and Reset Ports --------------------
+	gt2_eyescanreset_in => '0',
+	gt2_rxuserrdy_in => '0',
+	-------------------------- RX Margin Analysis Ports ------------------------
+	gt2_eyescandataerror_out => open,
+	gt2_eyescantrigger_in => '0',
+	------------------ Receive Ports - FPGA RX interface Ports -----------------
+	gt2_rxdata_out => gt2_rxdata_i,
+	------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+	gt2_rxdisperr_out => open,
+	gt2_rxnotintable_out => gt2_rxnotintable_i,
+	--------------------------- Receive Ports - RX AFE -------------------------
+	gt2_gtxrxp_in => G2_rxP,
+	------------------------ Receive Ports - RX AFE Ports ----------------------
+	gt2_gtxrxn_in => G2_rxN,
+	------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+	gt2_rxphmonitor_out => open,
+	gt2_rxphslipmonitor_out => open,
+	--------------------- Receive Ports - RX Equalizer Ports -------------------
+	gt2_rxdfelpmreset_in => '0',
+	gt2_rxmonitorout_out => open,
+	gt2_rxmonitorsel_in => "00",
+	------------- Receive Ports - RX Initialization and Reset Ports ------------
+	gt2_gtrxreset_in => gt2_gtrxreset_i,
+	gt2_rxpmareset_in => '0',
+	------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+	gt2_rxcharisk_out => gt2_rxcharisk_i,
+	-------------- Receive Ports -RX Initialization and Reset Ports ------------
+	gt2_rxresetdone_out => gt2_rxresetdone_i,
+	--------------------- TX Initialization and Reset Ports --------------------
+	gt2_gttxreset_in => '0',
+	gt2_txuserrdy_in => '0',
+	------------------ Transmit Ports - TX Data Path interface -----------------
+	gt2_txdata_in => gt2_txdata_i,
+	---------------- Transmit Ports - TX Driver and OOB signaling --------------
+	gt2_gtxtxn_out => G2_txN,
+	gt2_gtxtxp_out => G2_txP,
+	----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+	gt2_txoutclkfabric_out => open,
+	gt2_txoutclkpcs_out => open,
+	--------------------- Transmit Ports - TX Gearbox Ports --------------------
+	gt2_txcharisk_in => gt2_txcharisk_i,
+	------------- Transmit Ports - TX Initialization and Reset Ports -----------
+	gt2_txresetdone_out => gt2_txresetdone_i,
+
+
+
+
+	--_____________________________________________________________________
+	--_____________________________________________________________________
+	--GT3  (X1Y15)
+
+	--------------------------------- CPLL Ports -------------------------------
+	gt3_cpllfbclklost_out => open,
+	gt3_cplllock_out => open,
+	gt3_cpllreset_in => '0',
+	---------------------------- Channel - DRP Ports  --------------------------
+	gt3_drpaddr_in => (others => '0'),
+	gt3_drpdi_in => (others => '0'),
+	gt3_drpdo_out => open,
+	gt3_drpen_in => '0',
+	gt3_drprdy_out => open,
+	gt3_drpwe_in => '0',
+	--------------------------- Digital Monitor Ports --------------------------
+	gt3_dmonitorout_out => open,
+	--------------------- RX Initialization and Reset Ports --------------------
+	gt3_eyescanreset_in => '0',
+	gt3_rxuserrdy_in => '0',
+	-------------------------- RX Margin Analysis Ports ------------------------
+	gt3_eyescandataerror_out => open,
+	gt3_eyescantrigger_in => '0',
+	------------------ Receive Ports - FPGA RX interface Ports -----------------
+	gt3_rxdata_out => gt3_rxdata_i,
+	------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+	gt3_rxdisperr_out => open,
+	gt3_rxnotintable_out => gt3_rxnotintable_i,
+	--------------------------- Receive Ports - RX AFE -------------------------
+	gt3_gtxrxp_in => G3_rxP,
+	------------------------ Receive Ports - RX AFE Ports ----------------------
+	gt3_gtxrxn_in => G3_rxN,
+	------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+	gt3_rxphmonitor_out => open,
+	gt3_rxphslipmonitor_out => open,
+	--------------------- Receive Ports - RX Equalizer Ports -------------------
+	gt3_rxdfelpmreset_in => '0',
+	gt3_rxmonitorout_out => open,
+	gt3_rxmonitorsel_in => "00",
+	------------- Receive Ports - RX Initialization and Reset Ports ------------
+	gt3_gtrxreset_in => gt3_gtrxreset_i,
+	gt3_rxpmareset_in => '0',
+	------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+	gt3_rxcharisk_out => gt3_rxcharisk_i,
+	-------------- Receive Ports -RX Initialization and Reset Ports ------------
+	gt3_rxresetdone_out => gt3_rxresetdone_i,
+	--------------------- TX Initialization and Reset Ports --------------------
+	gt3_gttxreset_in => '0',
+	gt3_txuserrdy_in => '0',
+	------------------ Transmit Ports - TX Data Path interface -----------------
+	gt3_txdata_in => gt3_txdata_i,
+	---------------- Transmit Ports - TX Driver and OOB signaling --------------
+	gt3_gtxtxn_out => G3_txN,
+	gt3_gtxtxp_out => G3_txP,
+	----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+	gt3_txoutclkfabric_out => open,
+	gt3_txoutclkpcs_out => open,
+	--------------------- Transmit Ports - TX Gearbox Ports --------------------
+	gt3_txcharisk_in => gt3_txcharisk_i,
+	------------- Transmit Ports - TX Initialization and Reset Ports -----------
+	gt3_txresetdone_out => gt3_txresetdone_i,
+
+
+
+    --____________________________COMMON PORTS________________________________
+	GT0_QPLLOUTCLK_OUT  => open,
+	GT0_QPLLOUTREFCLK_OUT => open,
+	sysclk_in => sysClk
+    );
+
+    -------------------------- User Module Resets -----------------------------
+    -- All the User Modules are held in reset till the RESETDONE goes high. 
+    -- The RESETDONE is registered a couple of times on USRCLK2 and connected 
+    -- to the reset of the modules
+    
+process(gt0_rxusrclk2_i,gt0_rxresetdone_i,G0_LOS)
+    begin
+        if(gt0_rxresetdone_i = '0') or (G0_LOS='1') then
+            gt0_rxresetdone_r  <= '0'   after DLY;
+            gt0_rxresetdone_r2 <= '0'   after DLY;
+            gt0_rxresetdone_r3 <= '0'   after DLY;
+elsif (gt0_rxusrclk2_i'event and gt0_rxusrclk2_i = '1') then
+            gt0_rxresetdone_r  <= gt0_rxresetdone_i   after DLY;
+            gt0_rxresetdone_r2 <= gt0_rxresetdone_r   after DLY;
+            gt0_rxresetdone_r3  <= gt0_rxresetdone_r2   after DLY;
+        end if;
+    end process;
+process(gt0_txusrclk2_i,gt0_txfsmresetdone_i,gt0_txresetdone_i)
+    begin
+        if(gt0_txfsmresetdone_i = '0') or (gt0_txresetdone_i='0')  then
+            gt0_txfsmresetdone_r  <= '0'   after DLY;
+            gt0_txfsmresetdone_r2 <= '0'   after DLY;
+elsif (gt0_txusrclk2_i'event and gt0_txusrclk2_i = '1') then
+            gt0_txfsmresetdone_r  <= gt0_txfsmresetdone_i   after DLY;
+            gt0_txfsmresetdone_r2 <= gt0_txfsmresetdone_r   after DLY;
+        end if;
+    end process;
+	
+process(gt1_rxusrclk2_i,gt1_rxresetdone_i,G1_LOS)
+    begin
+        if(gt1_rxresetdone_i = '0') or (G1_LOS='1') then
+            gt1_rxresetdone_r  <= '0'   after DLY;
+            gt1_rxresetdone_r2 <= '0'   after DLY;
+            gt1_rxresetdone_r3 <= '0'   after DLY;
+elsif (gt1_rxusrclk2_i'event and gt1_rxusrclk2_i = '1') then
+            gt1_rxresetdone_r  <= gt1_rxresetdone_i   after DLY;
+            gt1_rxresetdone_r2 <= gt1_rxresetdone_r   after DLY;
+            gt1_rxresetdone_r3  <= gt1_rxresetdone_r2   after DLY;
+        end if;
+    end process;
+process(gt1_txusrclk2_i,gt1_txfsmresetdone_i,gt1_txresetdone_i)
+    begin
+        if(gt1_txfsmresetdone_i = '0') or (gt1_txresetdone_i='0')  then
+            gt1_txfsmresetdone_r  <= '0'   after DLY;
+            gt1_txfsmresetdone_r2 <= '0'   after DLY;
+elsif (gt1_txusrclk2_i'event and gt1_txusrclk2_i = '1') then
+            gt1_txfsmresetdone_r  <= gt1_txfsmresetdone_i   after DLY;
+            gt1_txfsmresetdone_r2 <= gt1_txfsmresetdone_r   after DLY;
+        end if;
+    end process;
+	
+process(gt2_rxusrclk2_i,gt2_rxresetdone_i,G2_LOS)
+    begin
+        if(gt2_rxresetdone_i = '0') or (G2_LOS='1') then
+            gt2_rxresetdone_r  <= '0'   after DLY;
+            gt2_rxresetdone_r2 <= '0'   after DLY;
+            gt2_rxresetdone_r3 <= '0'   after DLY;
+elsif (gt2_rxusrclk2_i'event and gt2_rxusrclk2_i = '1') then
+            gt2_rxresetdone_r  <= gt2_rxresetdone_i   after DLY;
+            gt2_rxresetdone_r2 <= gt2_rxresetdone_r   after DLY;
+            gt2_rxresetdone_r3  <= gt2_rxresetdone_r2   after DLY;
+        end if;
+    end process;
+process(gt2_txusrclk2_i,gt2_txfsmresetdone_i,gt2_txresetdone_i)
+    begin
+        if(gt2_txfsmresetdone_i = '0') or (gt2_txresetdone_i='0')  then
+            gt2_txfsmresetdone_r  <= '0'   after DLY;
+            gt2_txfsmresetdone_r2 <= '0'   after DLY;
+elsif (gt2_txusrclk2_i'event and gt2_txusrclk2_i = '1') then
+            gt2_txfsmresetdone_r  <= gt2_txfsmresetdone_i   after DLY;
+            gt2_txfsmresetdone_r2 <= gt2_txfsmresetdone_r   after DLY;
+        end if;
+    end process;
+	
+process(gt3_rxusrclk2_i,gt3_rxresetdone_i,G3_LOS)
+    begin
+        if(gt3_rxresetdone_i = '0') or (G3_LOS='1') then
+            gt3_rxresetdone_r  <= '0'   after DLY;
+            gt3_rxresetdone_r2 <= '0'   after DLY;
+            gt3_rxresetdone_r3 <= '0'   after DLY;
+elsif (gt3_rxusrclk2_i'event and gt3_rxusrclk2_i = '1') then
+            gt3_rxresetdone_r  <= gt3_rxresetdone_i   after DLY;
+            gt3_rxresetdone_r2 <= gt3_rxresetdone_r   after DLY;
+            gt3_rxresetdone_r3  <= gt3_rxresetdone_r2   after DLY;
+        end if;
+    end process;
+process(gt3_txusrclk2_i,gt3_txfsmresetdone_i,gt0_txresetdone_i)
+    begin
+        if (gt3_txfsmresetdone_i = '0') or (gt3_txresetdone_i='0') then
+            gt3_txfsmresetdone_r  <= '0'   after DLY;
+            gt3_txfsmresetdone_r2 <= '0'   after DLY;
+elsif (gt3_txusrclk2_i'event and gt3_txusrclk2_i = '1') then
+            gt3_txfsmresetdone_r  <= gt3_txfsmresetdone_i   after DLY;
+            gt3_txfsmresetdone_r2 <= gt3_txfsmresetdone_r   after DLY;
+        end if;
+    end process;
+
+
+
+G0_rxLocked <= gt0_rxresetdone_r3;
+G1_rxLocked <= gt1_rxresetdone_r3;
+G2_rxLocked <= gt2_rxresetdone_r3;
+G3_rxLocked <= gt3_rxresetdone_r3;
+G0_rxLocked <= gt0_rxresetdone_r3;
+G0_txLocked <= gt0_txfsmresetdone_r2;
+G1_txLocked <= gt1_txfsmresetdone_r2;
+G2_txLocked <= gt2_txfsmresetdone_r2;
+G3_txLocked <= gt3_txfsmresetdone_r2;
+
+gt0_gtrxreset_i <= G0_LOS;
+gt1_gtrxreset_i <= G1_LOS;
+gt2_gtrxreset_i <= G2_LOS;
+gt3_gtrxreset_i <= G3_LOS;
+
+LEDs_link_ok(0)  <= '1' when (gt0_rxresetdone_r3='1') and (gt0_txfsmresetdone_r2='1') else '0';
+LEDs_link_ok(1)  <= '1' when (gt0_rxresetdone_r3='1') and (gt1_txfsmresetdone_r2='1') else '0';
+LEDs_link_ok(2)  <= '1' when (gt0_rxresetdone_r3='1') and (gt2_txfsmresetdone_r2='1') else '0';
+LEDs_link_ok(3)  <= '1' when (gt0_rxresetdone_r3='1') and (gt3_txfsmresetdone_r2='1') else '0';
+
+LEDs_rx <= (others => '0');
+LEDs_tx <= (others => '0');
+
+			
+end Behavioral;
+
+
+
diff --git a/data_concentrator/sources/xilinx/spi_dpram_32_to_8_dummy.vhd b/data_concentrator/sources/xilinx/spi_dpram_32_to_8_dummy.vhd
new file mode 100644
index 0000000..5fe102f
--- /dev/null
+++ b/data_concentrator/sources/xilinx/spi_dpram_32_to_8_dummy.vhd
@@ -0,0 +1,30 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- dummy unit
+entity spi_dpram_32_to_8 is
+    port (
+        DataInA: in  std_logic_vector(31 downto 0); 
+        DataInB: in  std_logic_vector(7 downto 0); 
+        AddressA: in  std_logic_vector(5 downto 0); 
+        AddressB: in  std_logic_vector(7 downto 0); 
+        ClockA: in  std_logic; 
+        ClockB: in  std_logic; 
+        ClockEnA: in  std_logic; 
+        ClockEnB: in  std_logic; 
+        WrA: in  std_logic; 
+        WrB: in  std_logic; 
+        ResetA: in  std_logic; 
+        ResetB: in  std_logic; 
+        QA: out  std_logic_vector(31 downto 0); 
+        QB: out  std_logic_vector(7 downto 0));
+end spi_dpram_32_to_8;
+
+architecture Structure of spi_dpram_32_to_8 is
+
+begin
+        QA <= (others => '0');
+        QB <= (others => '0');
+
+
+end Structure;
+
diff --git a/data_concentrator/sources/xilinx/sync_bit.vhd b/data_concentrator/sources/xilinx/sync_bit.vhd
new file mode 100644
index 0000000..626fa52
--- /dev/null
+++ b/data_concentrator/sources/xilinx/sync_bit.vhd
@@ -0,0 +1,94 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   21-05-2015
+-- Module Name:   sync_bit
+-- Description:   Synchronization for 1 bit cross clock signal
+-- Modifications:
+----------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+----------------------------------------------------------------------------------
+-- sync_bit
+-- Synchronize a signal to a different clock by passing through several registers.
+-- This is the Xilinx version with Xilinx specific registers and attributes
+--
+-- Library
+-- 
+-- Generics:
+-- 
+-- Inputs:
+--     clock : clock to synchronize to
+--     data_in : signal from different clock
+-- 
+-- Outputs:
+--     data_out : synchronized signal
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+
+entity sync_bit is
+	port (
+		clock       : in  std_logic;
+		data_in     : in  std_logic;
+		data_out    : out std_logic
+	);
+end sync_bit;
+
+
+architecture structural of sync_bit is
+
+  signal dsync1 : std_logic;
+  signal dsync2 : std_logic;
+
+  -- These attributes will stop timing errors being reported in back annotated
+  -- SDF simulation.
+  attribute ASYNC_REG                       : string;
+  attribute ASYNC_REG of dsync_reg1    : label is "true";
+  attribute ASYNC_REG of dsync_reg2    : label is "true";
+  attribute ASYNC_REG of dsync_reg3    : label is "true";
+
+  -- These attributes will stop XST translating the desired flip-flops into an
+  -- SRL based shift register.
+  attribute shreg_extract                   : string;
+  attribute shreg_extract of dsync_reg1 : label is "no";
+  attribute shreg_extract of dsync_reg2 : label is "no";
+  attribute shreg_extract of dsync_reg3 : label is "no";
+
+  
+begin
+
+  dsync_reg1 : FD
+  port map (
+    C    => clock,
+    D    => data_in,
+    Q    => dsync1
+  );
+
+ dsync_reg2 : FD
+  port map (
+    C    => clock,
+    D    => dsync1,
+    Q    => dsync2
+  );
+
+ dsync_reg3 : FD
+  port map (
+    C    => clock,
+    D    => dsync2,
+    Q    => data_out
+  );
+
+
+
+end structural;
+
+
diff --git a/data_concentrator/sources/xilinx/trb_net16_fifo.vhd b/data_concentrator/sources/xilinx/trb_net16_fifo.vhd
new file mode 100644
index 0000000..d2de3c8
--- /dev/null
+++ b/data_concentrator/sources/xilinx/trb_net16_fifo.vhd
@@ -0,0 +1,233 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+USE ieee.std_logic_signed.ALL;
+USE IEEE.numeric_std.ALL;
+use work.trb_net_std.all;
+
+entity trb_net16_fifo is
+    generic (
+      USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+      USE_DATA_COUNT   : integer range 0 to 1 := c_NO;
+      DEPTH      : integer := 6
+      );
+    port (
+      CLK    : in std_logic;
+      RESET  : in std_logic;
+      CLK_EN : in std_logic;
+      DATA_IN         : in  std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+      PACKET_NUM_IN   : in  std_logic_vector(1 downto 0);
+      WRITE_ENABLE_IN : in  std_logic;
+      DATA_OUT        : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+      PACKET_NUM_OUT  : out std_logic_vector(1 downto 0);
+      READ_ENABLE_IN  : in  std_logic;
+      DATA_COUNT_OUT  : out std_logic_vector(10 downto 0);
+      FULL_OUT        : out std_logic;
+      EMPTY_OUT       : out std_logic
+      );
+end entity;
+
+architecture arch_trb_net16_fifo of trb_net16_fifo is
+-- attribute box_type: string;
+
+  component xilinx_fifo_18x1k
+    port (
+    clk: IN std_logic;
+    din: IN std_logic_VECTOR(17 downto 0);
+    rd_en: IN std_logic;
+    rst: IN std_logic;
+    wr_en: IN std_logic;
+    dout: OUT std_logic_VECTOR(17 downto 0);
+    empty: OUT std_logic;
+    full: OUT std_logic);
+  end component;
+-- attribute box_type of xilinx_fifo_18x1k : component is "black_box";
+
+
+  component xilinx_fifo_18x16
+  port (
+  clk: IN std_logic;
+  din: IN std_logic_VECTOR(17 downto 0);
+  rd_en: IN std_logic;
+  rst: IN std_logic;
+  wr_en: IN std_logic;
+  dout: OUT std_logic_VECTOR(17 downto 0);
+  empty: OUT std_logic;
+  full: OUT std_logic);
+  end component;
+-- attribute box_type of xilinx_fifo_18x16 : component is "black_box";
+
+  component xilinx_fifo_18x32
+    port (
+      clk: IN std_logic;
+      sinit: IN std_logic;
+      din: IN std_logic_VECTOR(17 downto 0);
+      wr_en: IN std_logic;
+      rd_en: IN std_logic;
+      dout: OUT std_logic_VECTOR(17 downto 0);
+      full: OUT std_logic;
+      empty: OUT std_logic
+      );
+  end component;
+-- attribute box_type of xilinx_fifo_18x32 : component is "black_box";
+
+  component xilinx_fifo_18x64
+    port (
+      clk: IN std_logic;
+      sinit: IN std_logic;
+      din: IN std_logic_VECTOR(17 downto 0);
+      wr_en: IN std_logic;
+      rd_en: IN std_logic;
+      dout: OUT std_logic_VECTOR(17 downto 0);
+      full: OUT std_logic;
+      empty: OUT std_logic
+      );
+  end component;
+-- attribute box_type of xilinx_fifo_18x64 : component is "black_box";
+
+  component xilinx_fifo_lut
+    generic (
+      WIDTH : integer := 18;
+      DEPTH : integer := 3
+      );
+    port (
+      clk: IN std_logic;
+      sinit: IN std_logic;
+      din: IN std_logic_VECTOR(17 downto 0);
+      wr_en: IN std_logic;
+      rd_en: IN std_logic;
+      dout: OUT std_logic_VECTOR(17 downto 0);
+      full: OUT std_logic;
+      empty: OUT std_logic
+      );
+  end component;
+
+  component xilinx_fifo_18x1k_datacount is
+    port (
+      clk: IN std_logic;
+      din: IN std_logic_VECTOR(17 downto 0);
+      rd_en: IN std_logic;
+      rst: IN std_logic;
+      wr_en: IN std_logic;
+      data_count: OUT std_logic_VECTOR(9 downto 0);
+      dout: OUT std_logic_VECTOR(17 downto 0);
+      empty: OUT std_logic;
+      full: OUT std_logic
+      );
+  end component;
+-- attribute box_type of xilinx_fifo_18x1k_datacount : component is "black_box";
+
+  signal din, dout : std_logic_vector(c_DATA_WIDTH + 2-1 downto 0);
+  signal data_counter : std_logic_vector(9 downto 0);
+
+begin
+  din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN;
+  din(c_DATA_WIDTH + 2 -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN;
+  DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0);
+  PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 2 - 1 downto c_DATA_WIDTH);
+  DATA_COUNT_OUT <= '0' & data_counter;
+
+  gen_FIFO6_Count : if DEPTH = 6 and USE_DATA_COUNT = 1 generate
+    fifo:xilinx_fifo_18x1k_datacount
+      port map (
+        clk     => CLK,
+        rd_en   => READ_ENABLE_IN,
+        wr_en   => WRITE_ENABLE_IN,
+        din     => din,
+        rst     => RESET,
+        data_count => data_counter,
+        dout    => dout,
+        full    => FULL_OUT,
+        empty   => EMPTY_OUT
+        );
+
+  end generate;
+
+  gen_FIFO6 : if DEPTH = 6 and USE_DATA_COUNT = 0 generate
+    fifo:xilinx_fifo_18x1k
+      port map (
+        clk     => CLK,
+        rd_en   => READ_ENABLE_IN,
+        wr_en   => WRITE_ENABLE_IN,
+        din     => din,
+        rst     => RESET,
+        dout    => dout,
+        full    => FULL_OUT,
+        empty   => EMPTY_OUT
+        );
+    data_counter <= (others => '0');
+  end generate;
+
+  gen_OWN_CORES : if USE_VENDOR_CORES = c_NO generate
+    gen_FIFO_LUT : if DEPTH < 6 generate
+      fifo:xilinx_fifo_lut
+        generic map (
+          WIDTH => c_DATA_WIDTH + 2,
+          DEPTH => ((DEPTH+3))
+          )
+        port map (
+          clk     => CLK,
+          rd_en   => READ_ENABLE_IN,
+          wr_en   => WRITE_ENABLE_IN,
+          din     => din,
+          sinit   => RESET,
+          dout    => dout,
+          full    => FULL_OUT,
+          empty   => EMPTY_OUT
+          );
+      data_counter <= (others => '0');
+    end generate;
+  end generate;
+
+  gen_XILINX_CORES : if USE_VENDOR_CORES = c_YES generate
+    gen_FIFO1 : if DEPTH = 1  generate
+      fifo:xilinx_fifo_18x16
+        port map (
+          clk     => CLK,
+          rd_en   => READ_ENABLE_IN,
+          wr_en   => WRITE_ENABLE_IN,
+          din     => din,
+          rst   => RESET,
+          dout    => dout,
+          full    => FULL_OUT,
+          empty   => EMPTY_OUT
+          );
+      data_counter <= (others => '0');
+    end generate;
+
+    gen_FIFO2 : if DEPTH = 2  generate
+      fifo:xilinx_fifo_18x32
+        port map (
+          clk     => CLK,
+          rd_en   => READ_ENABLE_IN,
+          wr_en   => WRITE_ENABLE_IN,
+          din     => din,
+          sinit   => RESET,
+          dout    => dout,
+          full    => FULL_OUT,
+          empty   => EMPTY_OUT
+          );
+      data_counter <= (others => '0');
+    end generate;
+
+
+    gen_FIFO3 : if DEPTH = 3  generate
+      fifo:xilinx_fifo_18x64
+        port map (
+          clk     => CLK,
+          rd_en   => READ_ENABLE_IN,
+          wr_en   => WRITE_ENABLE_IN,
+          din     => din,
+          sinit   => RESET,
+          dout    => dout,
+          full    => FULL_OUT,
+          empty   => EMPTY_OUT
+          );
+      data_counter <= (others => '0');
+    end generate;
+  end generate;
+
+
+end architecture;
+
+
diff --git a/data_concentrator/sources/xilinx/trb_net16_fifo_arch.vhd b/data_concentrator/sources/xilinx/trb_net16_fifo_arch.vhd
new file mode 100644
index 0000000..d2de3c8
--- /dev/null
+++ b/data_concentrator/sources/xilinx/trb_net16_fifo_arch.vhd
@@ -0,0 +1,233 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+USE ieee.std_logic_signed.ALL;
+USE IEEE.numeric_std.ALL;
+use work.trb_net_std.all;
+
+entity trb_net16_fifo is
+    generic (
+      USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
+      USE_DATA_COUNT   : integer range 0 to 1 := c_NO;
+      DEPTH      : integer := 6
+      );
+    port (
+      CLK    : in std_logic;
+      RESET  : in std_logic;
+      CLK_EN : in std_logic;
+      DATA_IN         : in  std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+      PACKET_NUM_IN   : in  std_logic_vector(1 downto 0);
+      WRITE_ENABLE_IN : in  std_logic;
+      DATA_OUT        : out std_logic_vector(c_DATA_WIDTH - 1 downto 0);
+      PACKET_NUM_OUT  : out std_logic_vector(1 downto 0);
+      READ_ENABLE_IN  : in  std_logic;
+      DATA_COUNT_OUT  : out std_logic_vector(10 downto 0);
+      FULL_OUT        : out std_logic;
+      EMPTY_OUT       : out std_logic
+      );
+end entity;
+
+architecture arch_trb_net16_fifo of trb_net16_fifo is
+-- attribute box_type: string;
+
+  component xilinx_fifo_18x1k
+    port (
+    clk: IN std_logic;
+    din: IN std_logic_VECTOR(17 downto 0);
+    rd_en: IN std_logic;
+    rst: IN std_logic;
+    wr_en: IN std_logic;
+    dout: OUT std_logic_VECTOR(17 downto 0);
+    empty: OUT std_logic;
+    full: OUT std_logic);
+  end component;
+-- attribute box_type of xilinx_fifo_18x1k : component is "black_box";
+
+
+  component xilinx_fifo_18x16
+  port (
+  clk: IN std_logic;
+  din: IN std_logic_VECTOR(17 downto 0);
+  rd_en: IN std_logic;
+  rst: IN std_logic;
+  wr_en: IN std_logic;
+  dout: OUT std_logic_VECTOR(17 downto 0);
+  empty: OUT std_logic;
+  full: OUT std_logic);
+  end component;
+-- attribute box_type of xilinx_fifo_18x16 : component is "black_box";
+
+  component xilinx_fifo_18x32
+    port (
+      clk: IN std_logic;
+      sinit: IN std_logic;
+      din: IN std_logic_VECTOR(17 downto 0);
+      wr_en: IN std_logic;
+      rd_en: IN std_logic;
+      dout: OUT std_logic_VECTOR(17 downto 0);
+      full: OUT std_logic;
+      empty: OUT std_logic
+      );
+  end component;
+-- attribute box_type of xilinx_fifo_18x32 : component is "black_box";
+
+  component xilinx_fifo_18x64
+    port (
+      clk: IN std_logic;
+      sinit: IN std_logic;
+      din: IN std_logic_VECTOR(17 downto 0);
+      wr_en: IN std_logic;
+      rd_en: IN std_logic;
+      dout: OUT std_logic_VECTOR(17 downto 0);
+      full: OUT std_logic;
+      empty: OUT std_logic
+      );
+  end component;
+-- attribute box_type of xilinx_fifo_18x64 : component is "black_box";
+
+  component xilinx_fifo_lut
+    generic (
+      WIDTH : integer := 18;
+      DEPTH : integer := 3
+      );
+    port (
+      clk: IN std_logic;
+      sinit: IN std_logic;
+      din: IN std_logic_VECTOR(17 downto 0);
+      wr_en: IN std_logic;
+      rd_en: IN std_logic;
+      dout: OUT std_logic_VECTOR(17 downto 0);
+      full: OUT std_logic;
+      empty: OUT std_logic
+      );
+  end component;
+
+  component xilinx_fifo_18x1k_datacount is
+    port (
+      clk: IN std_logic;
+      din: IN std_logic_VECTOR(17 downto 0);
+      rd_en: IN std_logic;
+      rst: IN std_logic;
+      wr_en: IN std_logic;
+      data_count: OUT std_logic_VECTOR(9 downto 0);
+      dout: OUT std_logic_VECTOR(17 downto 0);
+      empty: OUT std_logic;
+      full: OUT std_logic
+      );
+  end component;
+-- attribute box_type of xilinx_fifo_18x1k_datacount : component is "black_box";
+
+  signal din, dout : std_logic_vector(c_DATA_WIDTH + 2-1 downto 0);
+  signal data_counter : std_logic_vector(9 downto 0);
+
+begin
+  din(c_DATA_WIDTH - 1 downto 0) <= DATA_IN;
+  din(c_DATA_WIDTH + 2 -1 downto c_DATA_WIDTH) <= PACKET_NUM_IN;
+  DATA_OUT <= dout(c_DATA_WIDTH - 1 downto 0);
+  PACKET_NUM_OUT <= dout(c_DATA_WIDTH + 2 - 1 downto c_DATA_WIDTH);
+  DATA_COUNT_OUT <= '0' & data_counter;
+
+  gen_FIFO6_Count : if DEPTH = 6 and USE_DATA_COUNT = 1 generate
+    fifo:xilinx_fifo_18x1k_datacount
+      port map (
+        clk     => CLK,
+        rd_en   => READ_ENABLE_IN,
+        wr_en   => WRITE_ENABLE_IN,
+        din     => din,
+        rst     => RESET,
+        data_count => data_counter,
+        dout    => dout,
+        full    => FULL_OUT,
+        empty   => EMPTY_OUT
+        );
+
+  end generate;
+
+  gen_FIFO6 : if DEPTH = 6 and USE_DATA_COUNT = 0 generate
+    fifo:xilinx_fifo_18x1k
+      port map (
+        clk     => CLK,
+        rd_en   => READ_ENABLE_IN,
+        wr_en   => WRITE_ENABLE_IN,
+        din     => din,
+        rst     => RESET,
+        dout    => dout,
+        full    => FULL_OUT,
+        empty   => EMPTY_OUT
+        );
+    data_counter <= (others => '0');
+  end generate;
+
+  gen_OWN_CORES : if USE_VENDOR_CORES = c_NO generate
+    gen_FIFO_LUT : if DEPTH < 6 generate
+      fifo:xilinx_fifo_lut
+        generic map (
+          WIDTH => c_DATA_WIDTH + 2,
+          DEPTH => ((DEPTH+3))
+          )
+        port map (
+          clk     => CLK,
+          rd_en   => READ_ENABLE_IN,
+          wr_en   => WRITE_ENABLE_IN,
+          din     => din,
+          sinit   => RESET,
+          dout    => dout,
+          full    => FULL_OUT,
+          empty   => EMPTY_OUT
+          );
+      data_counter <= (others => '0');
+    end generate;
+  end generate;
+
+  gen_XILINX_CORES : if USE_VENDOR_CORES = c_YES generate
+    gen_FIFO1 : if DEPTH = 1  generate
+      fifo:xilinx_fifo_18x16
+        port map (
+          clk     => CLK,
+          rd_en   => READ_ENABLE_IN,
+          wr_en   => WRITE_ENABLE_IN,
+          din     => din,
+          rst   => RESET,
+          dout    => dout,
+          full    => FULL_OUT,
+          empty   => EMPTY_OUT
+          );
+      data_counter <= (others => '0');
+    end generate;
+
+    gen_FIFO2 : if DEPTH = 2  generate
+      fifo:xilinx_fifo_18x32
+        port map (
+          clk     => CLK,
+          rd_en   => READ_ENABLE_IN,
+          wr_en   => WRITE_ENABLE_IN,
+          din     => din,
+          sinit   => RESET,
+          dout    => dout,
+          full    => FULL_OUT,
+          empty   => EMPTY_OUT
+          );
+      data_counter <= (others => '0');
+    end generate;
+
+
+    gen_FIFO3 : if DEPTH = 3  generate
+      fifo:xilinx_fifo_18x64
+        port map (
+          clk     => CLK,
+          rd_en   => READ_ENABLE_IN,
+          wr_en   => WRITE_ENABLE_IN,
+          din     => din,
+          sinit   => RESET,
+          dout    => dout,
+          full    => FULL_OUT,
+          empty   => EMPTY_OUT
+          );
+      data_counter <= (others => '0');
+    end generate;
+  end generate;
+
+
+end architecture;
+
+
diff --git a/data_concentrator/sources/xilinx/trb_net16_med_gtx2_kintex7_sfp.vhd b/data_concentrator/sources/xilinx/trb_net16_med_gtx2_kintex7_sfp.vhd
new file mode 100644
index 0000000..4f10c1b
--- /dev/null
+++ b/data_concentrator/sources/xilinx/trb_net16_med_gtx2_kintex7_sfp.vhd
@@ -0,0 +1,713 @@
+--Media interface for Xilinx Kintex7 using SFP at 2GHz
+--One channel is used.
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+--use work.med_sync_define.all;
+
+entity trb_net16_med_gtx2_kintex7_sfp is
+  port(
+    CLK                : in  std_logic; -- SerDes clock
+    SYSCLK             : in  std_logic; -- fabric clock = 100MHz
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    CLK_EN             : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic;
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic;
+    MED_READ_IN        : in  std_logic;
+    REFCLK2CORE_OUT    : out std_logic;
+    CLK_RX_HALF_OUT    : out std_logic;
+    CLK_RX_FULL_OUT    : out std_logic;
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic;
+    SD_RXD_N_IN        : in  std_logic;
+    SD_TXD_P_OUT       : out std_logic;
+    SD_TXD_N_OUT       : out std_logic;
+    SD_REFCLK_P_IN     : in  std_logic;
+    SD_REFCLK_N_IN     : in  std_logic;
+    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out  std_logic; -- SFP disable	
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0);
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end entity;
+
+architecture trb_net16_med_gtx2_kintex7_sfp_arch of trb_net16_med_gtx2_kintex7_sfp is
+
+component GTX_trb3_2gb_wrapper
+generic
+(
+    -- Simulation attributes
+    EXAMPLE_SIM_GTRESET_SPEEDUP    : string    := "FALSE";    -- Set to TRUE to speed up sim reset
+    STABLE_CLOCK_PERIOD            : integer   := 10 
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+        --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+   
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT                     : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT                  : out std_logic;
+     SYSCLK_IN                              : in   std_logic
+);
+end component;
+
+  
+  signal refck2core             : std_logic;
+  --serdes connections
+  signal tx_data                : std_logic_vector(15 downto 0);
+  signal tx_k                   : std_logic_vector(1 downto 0);
+  signal rx_data                : std_logic_vector(15 downto 0); -- delayed signals
+  signal rx_k                   : std_logic_vector(1 downto 0);  -- delayed signals
+  signal comb_rx_data           : std_logic_vector(15 downto 0); -- original signals from SFP
+  signal comb_rx_k              : std_logic_vector(1 downto 0);  -- original signals from SFP
+  signal link_ok                : std_logic; 
+  signal ff_txhalfclk           : std_logic;
+  signal ff_rxhalfclk			      : std_logic;
+  signal ff_rxfullclk           : std_logic;
+  --rx fifo signals
+  signal fifo_rx_rd_en          : std_logic;
+  signal fifo_rx_wr_en          : std_logic;
+  signal fifo_rx_reset          : std_logic;
+  signal fifo_rx_din            : std_logic_vector(17 downto 0);
+  signal fifo_rx_dout           : std_logic_vector(17 downto 0);
+  signal fifo_rx_full           : std_logic;
+  signal fifo_rx_empty          : std_logic;
+  --tx fifo signals
+  signal fifo_tx_rd_en          : std_logic;
+  signal fifo_tx_wr_en          : std_logic;
+  signal fifo_tx_reset          : std_logic;
+  signal fifo_tx_din            : std_logic_vector(17 downto 0);
+  signal fifo_tx_dout           : std_logic_vector(17 downto 0);
+  signal fifo_tx_full           : std_logic;
+  signal fifo_tx_empty          : std_logic;
+  signal fifo_tx_almost_full    : std_logic;
+  --rx path
+  signal rx_counter             : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal buf_med_dataready_out  : std_logic;
+  signal buf_med_data_out       : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+  signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal last_rx                : std_logic_vector(8 downto 0);
+  signal last_fifo_rx_empty     : std_logic;
+  --tx path
+  signal last_fifo_tx_empty     : std_logic;
+  --link status
+  signal rx_k_q                 : std_logic_vector(1 downto 0);
+
+  signal quad_rst               : std_logic;
+  signal lane_rst               : std_logic;
+  signal tx_allow               : std_logic;
+  signal tx_allow0              : std_logic;
+  signal rx_allow               : std_logic;
+  signal tx_allow_qtx           : std_logic;
+
+  signal rx_allow_q             : std_logic; -- clock domain changed signal
+  signal tx_allow_q             : std_logic;
+  signal swap_bytes             : std_logic;
+  signal buf_stat_debug         : std_logic_vector(31 downto 0);
+
+  -- status inputs from SFP
+  signal sfp_prsnt_n            : std_logic; -- synchronized input signals
+  signal sfp_los                : std_logic; -- synchronized input signals
+
+  signal buf_STAT_OP            : std_logic_vector(15 downto 0);
+
+  signal led_counter            : unsigned(16 downto 0);
+  signal rx_led                 : std_logic;
+  signal tx_led                 : std_logic;
+
+
+  signal tx_correct             : std_logic_vector(1 downto 0); -- GbE mode SERDES: automatic IDLE2 -> IDLE1 conversion
+  signal first_idle             : std_logic; -- tag the first IDLE2 after data
+
+  signal reset_word_cnt         : unsigned(4 downto 0);
+  signal make_trbnet_reset      : std_logic;
+  signal make_trbnet_reset_q    : std_logic;
+  signal send_reset_words       : std_logic;
+  signal send_reset_words_q     : std_logic;
+  signal send_reset_in          : std_logic;
+  signal send_reset_in_qtx      : std_logic;
+  signal reset_i                : std_logic;
+  signal reset_i_rx             : std_logic;
+  signal pwr_up                 : std_logic;
+  signal clear_S                : std_logic;
+
+  signal clk_tx                 : std_logic;
+  signal clk_rx                 : std_logic;
+
+  signal gt0_txfsmresetdone_i   : std_logic;
+  signal gt0_rxfsmresetdone_i   : std_logic;
+  signal gt0_txresetdone_i      : std_logic;
+
+  signal gt0_rxnotintable_S     : std_logic_vector(1 downto 0);
+  signal link_rx_error_S        : std_logic;
+  signal link_tx_error_S        : std_logic;
+   
+-- attribute mark_debug : string;
+-- attribute mark_debug of tx_data : signal is "true";
+-- attribute mark_debug of tx_k : signal is "true";
+-- attribute mark_debug of rx_data : signal is "true";
+-- attribute mark_debug of rx_k : signal is "true";
+-- attribute mark_debug of quad_rst : signal is "true";
+
+-- attribute mark_debug of link_ok : signal is "true";
+-- attribute mark_debug of rx_k_q : signal is "true";
+-- attribute mark_debug of sfp_prsnt_n : signal is "true";
+-- attribute mark_debug of tx_allow : signal is "true";
+-- attribute mark_debug of rx_allow : signal is "true";
+-- attribute mark_debug of swap_bytes : signal is "true";
+-- attribute mark_debug of gt0_rxnotintable_S : signal is "true";
+-- attribute mark_debug of link_rx_error_S : signal is "true";
+-- attribute mark_debug of link_tx_error_S : signal is "true";
+-- attribute mark_debug of ctrl_op : signal is "true";
+-- attribute mark_debug of buf_stat_debug : signal is "true";
+
+-- attribute mark_debug of make_trbnet_reset : signal is "true";
+-- attribute mark_debug of send_reset_in : signal is "true";
+-- attribute mark_debug of reset_i_rx : signal is "true";
+-- attribute mark_debug of gt0_txfsmresetdone_i : signal is "true";
+-- attribute mark_debug of gt0_rxfsmresetdone_i : signal is "true";
+-- attribute mark_debug of gt0_txresetdone_i : signal is "true";
+
+  begin
+
+--------------------------------------------------------------------------
+-- Select proper clock configuration
+--------------------------------------------------------------------------
+  clk_rx  <= ff_rxhalfclk;
+
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+  clear_S <= clear;
+
+
+  PROC_RESET : process(SYSCLK)
+    begin
+      if rising_edge(SYSCLK) then
+        reset_i <= RESET;
+        send_reset_in <= ctrl_op(15);
+        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
+      end if;
+    end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+  generic map(
+    DEPTH => 3,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => sd_prsnt_n_in,
+    D_IN(1)  => sd_los_in,
+    CLK0     => SYSCLK,
+    CLK1     => SYSCLK,
+    D_OUT(0) => sfp_prsnt_n,
+    D_OUT(1) => sfp_los
+    );
+
+
+THE_RX_K_SYNC: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 4
+    )
+  port map(
+    RESET             => reset_i,
+    D_IN(1 downto 0)  => comb_rx_k,
+    D_IN(2)           => send_reset_words,
+    D_IN(3)           => make_trbnet_reset,
+    CLK0              => clk_rx, -- CHANGED
+    CLK1              => SYSCLK,
+    D_OUT(1 downto 0) => rx_k_q,
+    D_OUT(2)          => send_reset_words_q,
+    D_OUT(3)          => make_trbnet_reset_q
+    );
+
+THE_RX_DATA_DELAY: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 16
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN     => comb_rx_data,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT    => rx_data
+    );
+
+THE_RX_K_DELAY: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN     => comb_rx_k,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT    => rx_k
+    );
+
+THE_RX_RESET: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 1
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => reset_i,
+    CLK0     => clk_rx,
+    CLK1     => clk_rx,
+    D_OUT(0) => reset_i_rx
+    );
+
+-- Delay for ALLOW signals
+THE_RX_ALLOW_SYNC: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => reset_i,
+    D_IN(0)  => rx_allow,
+    D_IN(1)  => tx_allow,
+    CLK0     => SYSCLK,
+    CLK1     => SYSCLK,
+    D_OUT(0) => rx_allow_q,
+    D_OUT(1) => tx_allow_q
+    );
+
+THE_TX_SYNC: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => send_reset_in,
+    D_IN(1)  => tx_allow,
+    CLK0     => clk_tx,
+    CLK1     => clk_tx,
+    D_OUT(0) => send_reset_in_qtx,
+    D_OUT(1) => tx_allow_qtx
+    );
+
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+    generic map (
+      CHECK_FOR_CV => c_YES,
+      HIGHSPEED_STARTUP => c_YES
+      )
+    port map(
+      SYSCLK            => SYSCLK,
+      RESET             => reset_i,
+      CLEAR             => clear_S,
+      SFP_MISSING_IN    => sfp_prsnt_n,
+      SFP_LOS_IN        => sfp_los,
+      SD_LINK_OK_IN     => link_ok, -- apparently not used
+      SD_LOS_IN         => '0', -- apparently not used
+      SD_TXCLK_BAD_IN   => link_tx_error_S,
+      SD_RXCLK_BAD_IN   => link_rx_error_S,
+      SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+      SD_ALIGNMENT_IN	=> rx_k_q,
+      SD_CV_IN          => gt0_rxnotintable_S,
+      FULL_RESET_OUT    => quad_rst,
+      LANE_RESET_OUT    => open, -- apparently not used
+      TX_ALLOW_OUT      => tx_allow,
+      RX_ALLOW_OUT      => rx_allow,
+      SWAP_BYTES_OUT    => swap_bytes,
+      STAT_OP           => buf_stat_op,
+      CTRL_OP           => ctrl_op,
+      STAT_DEBUG        => buf_stat_debug
+      );
+sd_txdis_out <= quad_rst or reset_i;
+link_rx_error_S <= '1' when (gt0_rxfsmresetdone_i='0')  else '0'; -- loss of lock 
+link_tx_error_S <= '1' when (gt0_txresetdone_i='0') or (gt0_txfsmresetdone_i='0') else '0';
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+-- SerDes clock output to FPGA fabric
+REFCLK2CORE_OUT <= ff_rxhalfclk;
+CLK_RX_HALF_OUT <= ff_rxhalfclk;
+CLK_RX_FULL_OUT <= ff_rxfullclk;
+
+THE_SERDES: GTX_trb3_2gb_wrapper port map
+    (
+        soft_reset_tx_in => quad_rst,
+        soft_reset_rx_in => quad_rst,
+		DONT_RESET_ON_DATA_ERROR_IN => '0',
+		Q2_CLK0_GTREFCLK_PAD_N_IN => SD_REFCLK_N_IN,
+		Q2_CLK0_GTREFCLK_PAD_P_IN => SD_REFCLK_P_IN,
+		GT0_TX_FSM_RESET_DONE_OUT => gt0_txfsmresetdone_i,
+		GT0_RX_FSM_RESET_DONE_OUT => gt0_rxfsmresetdone_i,
+		GT0_DATA_VALID_IN => '1', -- tx_allow,
+ 
+		GT0_TXUSRCLK_OUT => open,
+		GT0_TXUSRCLK2_OUT => clk_tx, -- clock for tx_data (100MHz)
+		GT0_RXUSRCLK_OUT => ff_rxfullclk,
+		GT0_RXUSRCLK2_OUT => ff_rxhalfclk, -- clock for rx_data (100MHz)
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y10)
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out => open,
+        gt0_cplllock_out => open,
+        gt0_cpllreset_in => '0',
+        ---------------------------- Channel - DRP Ports  --------------------------
+        gt0_drpaddr_in => (others => '0'),
+        gt0_drpdi_in => (others => '0'),
+        gt0_drpdo_out => open,
+        gt0_drpen_in => '0',
+        gt0_drprdy_out => open,
+        gt0_drpwe_in => '0',
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out => open,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in => '0',
+        gt0_rxuserrdy_in => '0',
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out => open,
+        gt0_eyescantrigger_in => '0',
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out => comb_rx_data,        
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out => open,
+        gt0_rxnotintable_out => gt0_rxnotintable_S,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in => sd_rxd_p_in,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in => sd_rxd_n_in,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out => open,
+        gt0_rxphslipmonitor_out => open,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in => '0',
+        gt0_rxmonitorout_out => open,
+        gt0_rxmonitorsel_in => "00",
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+        gt0_gtrxreset_in => '0',
+        gt0_rxpmareset_in => '0',
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out => comb_rx_k, 
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out => link_ok, 
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in => '0',
+        gt0_txuserrdy_in => '0',
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in => tx_data,
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out => sd_txd_n_out,
+        gt0_gtxtxp_out => sd_txd_p_out,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclkfabric_out => open,
+        gt0_txoutclkpcs_out => open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in => tx_k,     
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out => gt0_txresetdone_i,
+
+    --____________________________COMMON PORTS________________________________
+		GT0_QPLLOUTCLK_OUT  => open,
+		GT0_QPLLOUTREFCLK_OUT => open,
+		SYSCLK_IN => SYSCLK
+    );
+
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+generic map(
+  USE_STATUS_FLAGS => c_NO
+       )
+port map( read_clock_in  => SYSCLK,
+      write_clock_in     => clk_rx,
+      read_enable_in     => fifo_rx_rd_en,
+      write_enable_in    => fifo_rx_wr_en,
+      fifo_gsr_in        => fifo_rx_reset,
+      write_data_in      => fifo_rx_din,
+      read_data_out      => fifo_rx_dout,
+      full_out           => fifo_rx_full,
+      empty_out          => fifo_rx_empty
+    );
+
+fifo_rx_reset <= reset_i or not rx_allow_q;
+fifo_rx_rd_en <= not fifo_rx_empty;
+
+-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
+THE_BYTE_SWAP_PROC: process(clk_rx)
+  begin
+    if rising_edge(clk_rx) then
+		last_rx <= rx_k(1) & rx_data(15 downto 8);
+		if( swap_bytes = '0' ) then
+		  fifo_rx_din   <= rx_k(1) & rx_k(0) & rx_data(15 downto 8) & rx_data(7 downto 0);
+		  fifo_rx_wr_en <= not rx_k(0) and rx_allow and link_ok;
+		else
+		  fifo_rx_din   <= rx_k(0) & last_rx(8) & rx_data(7 downto 0) & last_rx(7 downto 0);
+		  fifo_rx_wr_en <= not last_rx(8) and rx_allow and link_ok;
+		end if;
+	end if;
+  end process THE_BYTE_SWAP_PROC;
+
+buf_med_data_out          <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out    <= rx_counter;
+med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
+
+
+THE_CNT_RESET_PROC : process(clk_rx)
+  begin
+    if rising_edge(clk_rx) then
+		if reset_i_rx = '1' then
+		  send_reset_words  <= '0';
+		  make_trbnet_reset <= '0';
+		  reset_word_cnt    <= (others => '0');
+		else
+		  send_reset_words   <= '0';
+		  make_trbnet_reset  <= '0';
+		  if fifo_rx_din = "11" & x"FEFE" then
+			if reset_word_cnt(4) = '0' then
+			  reset_word_cnt <= reset_word_cnt + to_unsigned(1,1);
+			else
+			  send_reset_words <= '1';
+			end if;
+		  else
+			reset_word_cnt    <= (others => '0');
+			make_trbnet_reset <= reset_word_cnt(4);
+		  end if;
+		end if;
+	end if;
+  end process;
+
+
+THE_SYNC_PROC: process(SYSCLK)
+  begin
+    if rising_edge(SYSCLK) then
+		med_dataready_out     <= buf_med_dataready_out;
+		med_data_out          <= buf_med_data_out;
+		med_packet_num_out    <= buf_med_packet_num_out;
+		if reset_i = '1' then
+		  med_dataready_out <= '0';
+		end if;
+	end if;
+  end process;
+
+
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process( SYSCLK )
+  begin
+    if( rising_edge(SYSCLK) ) then
+      last_fifo_rx_empty <= fifo_rx_empty;
+      if reset_i = '1' or rx_allow_q = '0' then
+        rx_counter <= c_H0;
+      else
+        if( buf_med_dataready_out = '1' ) then
+          if( rx_counter = c_max_word_number ) then
+            rx_counter <= (others => '0');
+          else
+            rx_counter <= std_logic_vector(unsigned(rx_counter) + to_unsigned(1,1));
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+  generic map(
+    USE_STATUS_FLAGS => c_NO
+        )
+  port map( read_clock_in => clk_tx,
+        write_clock_in    => SYSCLK,
+        read_enable_in    => fifo_tx_rd_en,
+        write_enable_in   => fifo_tx_wr_en,
+        fifo_gsr_in       => fifo_tx_reset,
+        write_data_in     => fifo_tx_din,
+        read_data_out     => fifo_tx_dout,
+        full_out          => fifo_tx_full,
+        empty_out         => fifo_tx_empty,
+        almost_full_out   => fifo_tx_almost_full
+      );
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+fifo_tx_rd_en <= tx_allow_qtx;
+
+
+THE_SERDES_INPUT_PROC: process( clk_tx )
+  begin
+    if( rising_edge(clk_tx) ) then
+      last_fifo_tx_empty <= fifo_tx_empty;
+      first_idle <= not last_fifo_tx_empty and fifo_tx_empty;
+      if send_reset_in = '1' then
+        tx_data <= x"FEFE";
+        tx_k <= "11";
+      elsif( (last_fifo_tx_empty = '1') or (tx_allow_qtx = '0') ) then
+        tx_data <= x"50bc";
+        tx_k <= "01";
+        tx_correct <= first_idle & '0'; -- ???????????
+      else
+        tx_data <= fifo_tx_dout(15 downto 0);
+        tx_k <= "00";
+        tx_correct <= "00"; -- ???????????
+      end if;
+    end if;
+  end process THE_SERDES_INPUT_PROC;
+
+
+
+--Generate LED signals
+----------------------
+process( SYSCLK )
+  begin
+    if rising_edge(SYSCLK) then
+      led_counter <= led_counter + to_unsigned(1,1);
+
+      if buf_med_dataready_out = '1' then
+        rx_led <= '1';
+      elsif led_counter = 0 then
+        rx_led <= '0';
+      end if;
+
+      if tx_k(0) = '0' then
+        tx_led <= '1';
+      elsif led_counter = 0 then
+        tx_led <= '0';
+      end if;
+
+    end if;
+  end process;
+
+stat_op(15)           <= send_reset_words_q;
+stat_op(14)           <= buf_stat_op(14);
+stat_op(13)           <= make_trbnet_reset_q;
+stat_op(12)           <= '0';
+stat_op(11)           <= tx_led; --tx led
+stat_op(10)           <= rx_led; --rx led
+stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(15 downto 0)  <= rx_data;
+stat_debug(17 downto 16) <= rx_k;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(24)           <= fifo_rx_rd_en;
+stat_debug(25)           <= fifo_rx_wr_en;
+stat_debug(26)           <= fifo_rx_reset;
+stat_debug(27)           <= fifo_rx_empty;
+stat_debug(28)           <= fifo_rx_full;
+stat_debug(29)           <= last_rx(8);
+stat_debug(30)           <= rx_allow_q;
+stat_debug(41 downto 31) <= (others => '0');
+stat_debug(42)           <= SYSCLK;
+stat_debug(43)           <= SYSCLK;
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
+
+end architecture;
\ No newline at end of file
diff --git a/data_concentrator/sources/xilinx/trb_net16_med_sync_gtx2_kintex7_sfp.vhd b/data_concentrator/sources/xilinx/trb_net16_med_sync_gtx2_kintex7_sfp.vhd
new file mode 100644
index 0000000..7ffa414
--- /dev/null
+++ b/data_concentrator/sources/xilinx/trb_net16_med_sync_gtx2_kintex7_sfp.vhd
@@ -0,0 +1,1035 @@
+--Media interface for Xilinx Kintex7 using SFP at 2GHz
+--One channel is used.
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+--use work.med_sync_define.all;
+
+entity trb_net16_med_sync_gtx2_kintex7_sfp is
+  port(
+    CLK                : in  std_logic; -- SerDes clock
+    SYSCLK             : in  std_logic; -- fabric clock = 100MHz
+    SODA_clock         : in  std_logic; --//try
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    CLK_EN             : in  std_logic;
+	disable_GTX_reset  : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic;
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic;
+    MED_READ_IN        : in  std_logic;
+    REFCLK2CORE_OUT    : out std_logic;
+    CLK_RX_HALF_OUT    : out std_logic;
+    CLK_RX_FULL_OUT    : out std_logic;
+    --SFP Connection
+	SODA_RXD_P_IN      : in  std_logic;
+    SODA_RXD_N_IN      : in  std_logic;
+    SODA_TXD_P_OUT     : out std_logic;
+    SODA_TXD_N_OUT     : out std_logic;
+    SODA_REFCLK_P_IN   : in  std_logic;
+    SODA_REFCLK_N_IN   : in  std_logic;
+    SODA_PRSNT_N_IN    : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SODA_LOS_IN        : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SODA_TXDIS_OUT     : out  std_logic; -- SFP disable	
+	SODA_DLM_IN        : in  std_logic;
+	SODA_DLM_WORD_IN   : in  std_logic_vector(7 downto 0);
+	SODA_DLM_OUT       : out  std_logic;
+	SODA_DLM_WORD_OUT  : out  std_logic_vector(7 downto 0);
+    SODA_CLOCK_OUT     : out  std_logic; -- 200MHz
+	SODA_LOCKED_OUT    : out  std_logic;
+
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0);
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end entity;
+
+architecture trb_net16_med_sync_gtx2_kintex7_sfp_arch of trb_net16_med_sync_gtx2_kintex7_sfp is
+
+component GTX_trb3_sync_2gb_support
+generic
+(
+    -- Simulation attributes
+    EXAMPLE_SIM_GTRESET_SPEEDUP    : string    := "FALSE";    -- Set to TRUE to speed up sim reset
+    STABLE_CLOCK_PERIOD            : integer   := 10 
+);
+port
+(
+    SOFT_RESET_TX_IN                        : in   std_logic;
+    SOFT_RESET_RX_IN                        : in   std_logic;
+    DONT_RESET_ON_DATA_ERROR_IN             : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_N_IN               : in   std_logic;
+    Q2_CLK0_GTREFCLK_PAD_P_IN               : in   std_logic;
+
+    GT0_TX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_RX_FSM_RESET_DONE_OUT               : out  std_logic;
+    GT0_DATA_VALID_IN                       : in   std_logic;
+    GT0_TX_MMCM_LOCK_OUT                    : out  std_logic;
+ 
+    GT0_TXUSRCLK_OUT                        : out  std_logic;
+    GT0_TXUSRCLK2_OUT                       : out  std_logic;
+    GT0_TXUSRCLKX2_OUT                      : out  std_logic; --// Modified
+    GT0_RXUSRCLK_OUT                        : out  std_logic;
+    GT0_RXUSRCLK2_OUT                       : out  std_logic;
+
+    --_________________________________________________________________________
+        --GT0  (X1Y10)
+    --____________________________CHANNEL PORTS________________________________
+    --------------------------------- CPLL Ports -------------------------------
+    gt0_cpllfbclklost_out                   : out  std_logic;
+    gt0_cplllock_out                        : out  std_logic;
+    gt0_cpllreset_in                        : in   std_logic;
+    ---------------------------- Channel - DRP Ports  --------------------------
+    gt0_drpaddr_in                          : in   std_logic_vector(8 downto 0);
+    gt0_drpdi_in                            : in   std_logic_vector(15 downto 0);
+    gt0_drpdo_out                           : out  std_logic_vector(15 downto 0);
+    gt0_drpen_in                            : in   std_logic;
+    gt0_drprdy_out                          : out  std_logic;
+    gt0_drpwe_in                            : in   std_logic;
+    --------------------------- Digital Monitor Ports --------------------------
+    gt0_dmonitorout_out                     : out  std_logic_vector(7 downto 0);
+    --------------------- RX Initialization and Reset Ports --------------------
+    gt0_eyescanreset_in                     : in   std_logic;
+    gt0_rxuserrdy_in                        : in   std_logic;
+    -------------------------- RX Margin Analysis Ports ------------------------
+    gt0_eyescandataerror_out                : out  std_logic;
+    gt0_eyescantrigger_in                   : in   std_logic;
+    ------------------------- Receive Ports - CDR Ports ------------------------
+	GT0_RXCDRRESET_IN                       : in  std_logic; --// Modified
+    GT0_RXCDRLOCK_OUT                       : out  std_logic; --// Modified
+    ------------------ Receive Ports - FPGA RX interface Ports -----------------
+    gt0_rxdata_out                          : out  std_logic_vector(15 downto 0);
+    ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+    gt0_rxdisperr_out                       : out  std_logic_vector(1 downto 0);
+    gt0_rxnotintable_out                    : out  std_logic_vector(1 downto 0);
+    --------------------------- Receive Ports - RX AFE -------------------------
+    gt0_gtxrxp_in                           : in   std_logic;
+    ------------------------ Receive Ports - RX AFE Ports ----------------------
+    gt0_gtxrxn_in                           : in   std_logic;
+    ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+    gt0_rxphmonitor_out                     : out  std_logic_vector(4 downto 0);
+    gt0_rxphslipmonitor_out                 : out  std_logic_vector(4 downto 0);
+    --------------------- Receive Ports - RX Equalizer Ports -------------------
+    gt0_rxdfelpmreset_in                    : in   std_logic;
+    gt0_rxmonitorout_out                    : out  std_logic_vector(6 downto 0);
+    gt0_rxmonitorsel_in                     : in   std_logic_vector(1 downto 0);
+    ------------- Receive Ports - RX Initialization and Reset Ports ------------
+    gt0_gtrxreset_in                        : in   std_logic;
+    gt0_rxpmareset_in                       : in   std_logic;
+    ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+    gt0_rxcharisk_out                       : out  std_logic_vector(1 downto 0);
+    -------------- Receive Ports -RX Initialization and Reset Ports ------------
+    gt0_rxresetdone_out                     : out  std_logic;
+    --------------------- TX Initialization and Reset Ports --------------------
+    gt0_gttxreset_in                        : in   std_logic;
+    gt0_txuserrdy_in                        : in   std_logic;
+    ------------------ Transmit Ports - TX Data Path interface -----------------
+    gt0_txdata_in                           : in   std_logic_vector(15 downto 0);
+    ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+    gt0_gtxtxn_out                          : out  std_logic;
+    gt0_gtxtxp_out                          : out  std_logic;
+    ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+    gt0_txoutclkfabric_out                  : out  std_logic;
+    gt0_txoutclkpcs_out                     : out  std_logic;
+    --------------------- Transmit Ports - TX Gearbox Ports --------------------
+    gt0_txcharisk_in                        : in   std_logic_vector(1 downto 0);
+    ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+    gt0_txresetdone_out                     : out  std_logic;
+   
+
+    --____________________________COMMON PORTS________________________________
+     GT0_QPLLOUTCLK_OUT  : out std_logic;
+     GT0_QPLLOUTREFCLK_OUT : out std_logic;
+        sysclk_in : in std_logic
+);
+end component;
+
+component DC_data8to16 is
+	port ( 
+		clock_in                : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		kchar_in                : in std_logic;
+		clock_out               : in std_logic;
+		data_out                : out std_logic_vector(15 downto 0);
+		kchar_out               : out std_logic_vector(1 downto 0)
+	);
+end component;
+
+component DC_data16to8 is
+	port ( 
+		clock_in                : in std_logic;
+        data_in                 : in std_logic_vector(15 downto 0);
+        kchar_in                : in std_logic_vector(1 downto 0);
+        notintable_in           : in std_logic_vector(1 downto 0);
+        clock_out               : out std_logic;
+        data_out                : out std_logic_vector(7 downto 0);
+        kchar_out               : out std_logic;
+        notintable_out          : out std_logic
+	);
+end component;
+
+component DC_SODA_clockcrossing is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		DLM_in                  : in std_logic;
+		DLM_WORD_in             : in std_logic_vector(7 downto 0);
+		DLM_out                 : out std_logic;
+		DLM_WORD_out            : out std_logic_vector(7 downto 0);
+		error                   : out std_logic
+	);
+end component;
+
+component DC_rxBitLock is
+	port (
+		clk                     : in  std_logic;
+		reset                   : in  std_logic;
+		resetDone               : in  std_logic;
+		lossOfSync              : in  std_logic;
+		rxPllLocked             : in  std_logic; 
+		rxReset                 : out  std_logic;
+		fsmStatus               : out  std_logic_vector (1 downto 0)
+	);
+end component;
+
+component HUB_8to16_SODA is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		char_is_k               : in std_logic;
+		fifo_data               : out std_logic_vector(17 downto 0);
+		fifo_full               : in std_logic;
+		fifo_write              : out std_logic;
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		error                   : out std_logic
+	);
+end component;
+
+component HUB_16to8_SODA is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		fifo_data               : in std_logic_vector(15 downto 0);
+		fifo_empty              : in std_logic;
+		fifo_read               : out std_logic;
+		TX_DLM                  : in std_logic;
+		TX_DLM_WORD             : in std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(7 downto 0);
+		char_is_k               : out std_logic;
+		error                   : out std_logic
+	);
+end component;
+
+component DC_posedge_to_pulse is
+	port (
+		clock_in                : in  std_logic;
+		clock_out               : in  std_logic;
+		en_clk                  : in  std_logic;
+		signal_in               : in  std_logic;
+		pulse                   : out std_logic
+	);
+end component;
+
+component sync_bit is
+	port (
+		clock       : in  std_logic;
+		data_in     : in  std_logic;
+		data_out    : out std_logic
+	);
+end component;
+
+signal refck2core                   : std_logic;
+--serdes connections
+signal txData16_S                   : std_logic_vector(15 downto 0);
+signal txCharIsK16_S                : std_logic_vector(1 downto 0);
+signal rxData16_S                   : std_logic_vector(15 downto 0);
+signal rxCharIsK16_S                : std_logic_vector(1 downto 0);
+signal rxNotInTable16_S             : std_logic_vector(1 downto 0);
+signal rxNotInTable16_q             : std_logic_vector(1 downto 0);
+signal txData8_S                    : std_logic_vector(7 downto 0);
+signal txCharIsK8_S                 : std_logic;
+signal rxData8_S                    : std_logic_vector(7 downto 0);
+signal rxCharIsK8_S                 : std_logic;
+signal SODA_DLM_WORD_OUT_S          : std_logic_vector(7 downto 0);
+signal SODA_DLM_OUT_S               : std_logic;
+
+signal ff_txhalfclk                 : std_logic;
+signal ff_txfullclk                 : std_logic;
+signal ff_rxhalfclk	                : std_logic;
+signal ff_rxfullclk                 : std_logic;
+--rx fifo signals
+signal fifo_rx_rd_en                : std_logic;
+signal fifo_rx_wr_en                : std_logic;
+signal fifo_rx_reset                : std_logic;
+signal fifo_rx_din                  : std_logic_vector(17 downto 0);
+signal fifo_rx_dout                 : std_logic_vector(17 downto 0);
+signal fifo_rx_full                 : std_logic;
+signal fifo_rx_empty                : std_logic;
+--tx fifo signals
+signal fifo_tx_rd_en                : std_logic;
+signal fifo_tx_wr_en                : std_logic;
+signal fifo_tx_reset                : std_logic;
+signal fifo_tx_din                  : std_logic_vector(17 downto 0);
+signal fifo_tx_dout                 : std_logic_vector(17 downto 0);
+signal fifo_tx_full                 : std_logic;
+signal fifo_tx_empty                : std_logic;
+signal fifo_tx_almost_full          : std_logic;
+--rx path
+signal rx_counter                   : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+signal buf_med_dataready_out        : std_logic;
+signal buf_med_data_out             : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+signal buf_med_packet_num_out       : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+signal last_fifo_rx_empty           : std_logic;
+--link status
+signal quad_rst                     : std_logic;
+signal quad_rst_S                   : std_logic;
+
+signal tx_allow                     : std_logic;
+signal rx_allow                     : std_logic;
+
+signal rx_allow_q                   : std_logic; 
+signal tx_allow_q                   : std_logic;
+signal buf_stat_debug               : std_logic_vector(31 downto 0);
+
+signal sfp_prsnt_n                  : std_logic; -- synchronized input signals
+signal sfp_los                      : std_logic; -- synchronized input signals
+signal buf_STAT_OP                  : std_logic_vector(15 downto 0);
+
+signal pllLkDet_S                   : std_logic;
+signal rxResetBitLock_S             : std_logic :='0';
+signal sync_rxResetBitLock_S        : std_logic :='0';
+signal prev_rxResetBitLock_S        : std_logic :='0';
+signal rxLossOfSync1_S              : std_logic;
+signal fsmStatus_S                  : std_logic_vector(1 downto 0);
+signal rxPLLwrapper_reset_S         : std_logic :='0';
+signal rxResetBitLock_pulse_S       : std_logic :='0';
+
+signal rxReset_S                    : std_logic :='0';
+signal resetDone_S                  : std_logic :='0';
+signal rxCDRlock_S                  : std_logic :='0';
+signal CDR_reset_S                  : std_logic :='0';
+signal rxLocked0_S                  : std_logic;
+signal rxLocked1_S                  : std_logic;
+signal rxLocked2_S                  : std_logic;
+
+signal SODA_DLM_IN_S                : std_logic;
+signal SODA_DLM_WORD_IN_S           : std_logic_vector(7 downto 0);
+
+		
+signal drpaddr_in_S                 : std_logic_vector(8 downto 0);
+signal drpdi_in_S                   : std_logic_vector(15 downto 0);
+signal drpdo_out_S                  : std_logic_vector(15 downto 0);
+signal drpen_in_S                   : std_logic;
+signal drprdy_out_S                 : std_logic;
+signal drpwe_in_S                   : std_logic;
+
+signal comma_align_latency_S        : std_logic_vector(6 downto 0);
+signal comma_align_latency0_valid_S : std_logic;
+signal comma_align_latency_valid_S  : std_logic;
+type drp_state_type is (initting, running, reading);
+signal drp_state_S                  : drp_state_type := initting;	
+
+signal led_counter                  : unsigned(16 downto 0);
+signal rx_led                       : std_logic;
+signal tx_led                       : std_logic;
+
+signal reset_word_cnt               : unsigned(4 downto 0);
+signal make_trbnet_reset            : std_logic;
+signal make_trbnet_reset_q          : std_logic;
+signal send_reset_words             : std_logic;
+signal send_reset_words_q           : std_logic;
+signal send_reset_in                : std_logic;
+signal send_reset_in_qtx            : std_logic;
+signal reset_i                      : std_logic;
+signal reset_i_rx                   : std_logic;
+signal pwr_up                       : std_logic;
+signal clear_S                      : std_logic;
+
+
+signal gt0_txfsmresetdone_i         : std_logic;
+signal gt0_rxfsmresetdone_i         : std_logic;
+signal gt0_txresetdone_i            : std_logic;
+signal gt0_txfsmresetdone_q         : std_logic;
+signal gt0_rxfsmresetdone_q         : std_logic;
+signal gt0_txresetdone_q            : std_logic;
+
+signal link_rx_error_S              : std_logic;
+signal link_tx_error_S              : std_logic;
+   
+   
+   
+attribute mark_debug : string;
+-- attribute mark_debug of txData16_S : signal is "true";
+-- attribute mark_debug of txCharIsK16_S : signal is "true";
+-- attribute mark_debug of rxNotInTable16_S : signal is "true";
+-- attribute mark_debug of rxData16_S : signal is "true";
+-- attribute mark_debug of rxCharIsK16_S : signal is "true";
+
+-- attribute mark_debug of txData8_S : signal is "true";
+-- attribute mark_debug of txCharIsK8_S : signal is "true";
+-- attribute mark_debug of rxData8_S : signal is "true";
+-- attribute mark_debug of rxCharIsK8_S : signal is "true";
+
+-- attribute mark_debug of quad_rst : signal is "true";
+-- attribute mark_debug of quad_rst_S : signal is "true";
+-- attribute mark_debug of rxLocked2_S : signal is "true";
+-- attribute mark_debug of sfp_los : signal is "true";
+-- attribute mark_debug of tx_allow : signal is "true";
+-- attribute mark_debug of rx_allow : signal is "true";
+-- attribute mark_debug of link_rx_error_S : signal is "true";
+-- attribute mark_debug of link_tx_error_S : signal is "true";
+
+-- attribute mark_debug of fifo_rx_rd_en : signal is "true";
+-- attribute mark_debug of fifo_rx_wr_en : signal is "true";
+-- attribute mark_debug of fifo_rx_full : signal is "true";
+-- attribute mark_debug of fifo_rx_empty : signal is "true";
+-- attribute mark_debug of fifo_tx_rd_en : signal is "true";
+-- attribute mark_debug of fifo_tx_wr_en : signal is "true";
+-- attribute mark_debug of fifo_tx_full : signal is "true";
+-- attribute mark_debug of fifo_tx_empty : signal is "true";
+
+-- attribute mark_debug of make_trbnet_reset_q : signal is "true";
+-- attribute mark_debug of send_reset_in : signal is "true";
+-- attribute mark_debug of reset_i_rx : signal is "true";
+-- attribute mark_debug of gt0_rxfsmresetdone_q : signal is "true";
+-- attribute mark_debug of gt0_txfsmresetdone_q : signal is "true";
+-- attribute mark_debug of gt0_txresetdone_q : signal is "true";
+
+-- attribute mark_debug of pllLkDet_S : signal is "true";
+-- attribute mark_debug of CDR_reset_S : signal is "true";
+-- attribute mark_debug of rxCDRlock_S : signal is "true";
+-- attribute mark_debug of rxReset_S : signal is "true";
+-- attribute mark_debug of resetDone_S : signal is "true";
+-- attribute mark_debug of rxLossOfSync1_S : signal is "true";
+-- attribute mark_debug of rxResetBitLock_S : signal is "true";
+-- attribute mark_debug of fsmStatus_S : signal is "true";
+
+-- attribute mark_debug of rxResetBitLock_pulse_S : signal is "true";
+-- attribute mark_debug of gt0_txresetdone_i : signal is "true";
+
+
+	
+  begin
+  
+SODA_CLOCK_OUT <= ff_rxfullclk;
+--SODA_LOCKED_OUT <= rxLocked2_S;
+SODA_LOCKED_OUT <= '1' when (tx_allow='1') and (rx_allow='1') else '0';
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+  clear_S <= clear;
+
+
+  PROC_RESET : process(SYSCLK)
+    begin
+      if rising_edge(SYSCLK) then
+        reset_i <= RESET;
+        send_reset_in <= ctrl_op(15);
+        pwr_up  <= '1'; --not CTRL_OP(i*16+14);
+      end if;
+    end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => SODA_PRSNT_N_IN,
+    D_IN(1)  => SODA_LOS_IN,
+    CLK0     => SYSCLK,
+    CLK1     => SYSCLK,
+    D_OUT(0) => sfp_prsnt_n,
+    D_OUT(1) => sfp_los
+    );
+
+
+THE_SENDRESET_SYNC: signal_sync
+	generic map(
+		DEPTH => 1,
+		WIDTH => 1
+	)
+	port map(
+		RESET => reset_i,
+		D_IN(0) => send_reset_words,
+		CLK0 => SYSCLK,
+		CLK1 => SYSCLK,
+		D_OUT(0) => send_reset_words_q
+	);
+
+THE_RESET_SYNC: DC_posedge_to_pulse 
+	port map(
+		clock_in => ff_rxhalfclk,
+		clock_out => SYSCLK,
+		en_clk => '1',
+		signal_in => make_trbnet_reset,
+		pulse  => make_trbnet_reset_q
+	);
+	
+THE_RX_RESET: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 1
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => reset_i,
+    CLK0     => ff_rxhalfclk,
+    CLK1     => ff_rxhalfclk,
+    D_OUT(0) => reset_i_rx
+    );
+
+-- Delay for ALLOW signals
+THE_RX_ALLOW_SYNC: signal_sync
+  generic map(
+    DEPTH => 2,
+    WIDTH => 2
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => rx_allow,
+    D_IN(1)  => tx_allow,
+    CLK0     => SYSCLK,
+    CLK1     => SYSCLK,
+    D_OUT(0) => rx_allow_q,
+    D_OUT(1) => tx_allow_q
+    );
+
+THE_TX_SYNC: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 1
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => send_reset_in,
+    CLK0     => ff_txfullclk,
+    CLK1     => ff_txfullclk,
+    D_OUT(0) => send_reset_in_qtx
+    );
+
+THE_SFPSIGNALS_SYNC: signal_sync
+  generic map(
+    DEPTH => 1,
+    WIDTH => 3
+    )
+  port map(
+    RESET    => '0',
+    D_IN(0)  => gt0_rxfsmresetdone_i,
+    D_IN(1)  => gt0_txfsmresetdone_i,
+    D_IN(2)  => gt0_txresetdone_i,
+    CLK0     => SYSCLK,
+    CLK1     => SYSCLK,
+    D_OUT(0) => gt0_rxfsmresetdone_q,
+    D_OUT(1) => gt0_txfsmresetdone_q,
+    D_OUT(2) => gt0_txresetdone_q
+    );
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+    generic map (
+      CHECK_FOR_CV => c_YES,
+      HIGHSPEED_STARTUP => c_YES
+      )
+    port map(
+      SYSCLK            => SYSCLK,
+      RESET             => reset_i,
+      CLEAR             => clear_S,
+      SFP_MISSING_IN    => sfp_prsnt_n,
+      SFP_LOS_IN        => sfp_los,
+      SD_LINK_OK_IN     => rxLocked2_S, -- apparently not used
+      SD_LOS_IN         => '0', -- apparently not used
+      SD_TXCLK_BAD_IN   => link_tx_error_S,
+      SD_RXCLK_BAD_IN   => link_rx_error_S,
+      SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+      SD_ALIGNMENT_IN	=> "01",
+      SD_CV_IN          => rxNotInTable16_q,
+      FULL_RESET_OUT    => quad_rst,
+      LANE_RESET_OUT    => open, -- apparently not used
+      TX_ALLOW_OUT      => tx_allow,
+      RX_ALLOW_OUT      => rx_allow,
+      SWAP_BYTES_OUT    => open,
+      STAT_OP           => buf_stat_op,
+      CTRL_OP           => ctrl_op,
+      STAT_DEBUG        => buf_stat_debug
+      );
+SODA_TXDIS_OUT <= quad_rst or reset_i;
+link_rx_error_S <= '1' when (gt0_rxfsmresetdone_q='0') or (rxLocked2_S='0') else '0'; -- loss of lock 
+link_tx_error_S <= '1' when (gt0_txresetdone_q='0') or (gt0_txfsmresetdone_q='0') else '0';
+
+process(SYSClk,quad_rst)
+variable counter_V : std_logic_vector(23 downto 0) := (others => '0');
+begin
+	if quad_rst='1' then
+		quad_rst_S	<= '1';
+		counter_V := (others => '0');
+	elsif rising_edge(sysClk) then
+		quad_rst_S	<= '0';
+		if counter_V(counter_V'left)='1' then
+			if resetDone_S='0' then
+				counter_V := (others => '0');
+				quad_rst_S	<= '1';
+			end if;
+		else
+			counter_V := counter_V+1;
+		end if;
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+-- SerDes clock output to FPGA fabric
+REFCLK2CORE_OUT <= ff_rxhalfclk;
+CLK_RX_HALF_OUT <= ff_rxhalfclk;
+CLK_RX_FULL_OUT <= ff_rxfullclk;
+
+THE_SERDES: GTX_trb3_sync_2gb_support port map
+    (
+        soft_reset_tx_in => quad_rst_S, -- quad_rst,
+        soft_reset_rx_in => quad_rst_S, -- quad_rst,
+		DONT_RESET_ON_DATA_ERROR_IN => '1',
+		Q2_CLK0_GTREFCLK_PAD_N_IN => SODA_REFCLK_N_IN,
+		Q2_CLK0_GTREFCLK_PAD_P_IN => SODA_REFCLK_P_IN,
+		GT0_TX_FSM_RESET_DONE_OUT => gt0_txfsmresetdone_i,
+		GT0_RX_FSM_RESET_DONE_OUT => gt0_rxfsmresetdone_i,
+		GT0_DATA_VALID_IN => '1', -- tx_allow,
+		GT0_TX_MMCM_LOCK_OUT => open,
+ 
+		GT0_TXUSRCLK_OUT => open,
+		GT0_TXUSRCLK2_OUT => ff_txhalfclk, -- clock for tx_data (100MHz)
+		GT0_TXUSRCLKX2_OUT => open, --//tryff_txfullclk, -- clock for 8 bits data (200MHz)
+		GT0_RXUSRCLK_OUT => open,
+		GT0_RXUSRCLK2_OUT => ff_rxhalfclk, -- clock for rx_data (100MHz)
+        --_____________________________________________________________________
+        --_____________________________________________________________________
+        --GT0  (X1Y10)
+        --------------------------------- CPLL Ports -------------------------------
+        gt0_cpllfbclklost_out => open,
+        gt0_cplllock_out => pllLkDet_S,
+        gt0_cpllreset_in => '0',
+        ---------------------------- Channel - DRP Ports  --------------------------
+		gt0_drpaddr_in => drpaddr_in_S,
+		gt0_drpdi_in => drpdi_in_S,
+		gt0_drpdo_out => drpdo_out_S,
+		gt0_drpen_in => drpen_in_S,
+		gt0_drprdy_out => drprdy_out_S,
+		gt0_drpwe_in => drpwe_in_S,
+        --------------------------- Digital Monitor Ports --------------------------
+        gt0_dmonitorout_out => open,
+        --------------------- RX Initialization and Reset Ports --------------------
+        gt0_eyescanreset_in => '0',
+        gt0_rxuserrdy_in => '0',
+        -------------------------- RX Margin Analysis Ports ------------------------
+        gt0_eyescandataerror_out => open,
+        gt0_eyescantrigger_in => '0',
+		------------------------- Receive Ports - CDR Ports ------------------------
+ 		GT0_RXCDRRESET_IN => CDR_reset_S,
+		GT0_RXCDRLOCK_OUT => rxCDRlock_S,
+        ------------------ Receive Ports - FPGA RX interface Ports -----------------
+        gt0_rxdata_out => rxData16_S,        
+        ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
+        gt0_rxdisperr_out => open,
+        gt0_rxnotintable_out => rxNotInTable16_S,
+        --------------------------- Receive Ports - RX AFE -------------------------
+        gt0_gtxrxp_in => SODA_RXD_P_IN,
+        ------------------------ Receive Ports - RX AFE Ports ----------------------
+        gt0_gtxrxn_in => SODA_RXD_N_IN,
+        ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
+        gt0_rxphmonitor_out => open,
+        gt0_rxphslipmonitor_out => open,
+        --------------------- Receive Ports - RX Equalizer Ports -------------------
+        gt0_rxdfelpmreset_in => '0',
+        gt0_rxmonitorout_out => open,
+        gt0_rxmonitorsel_in => "00",
+        ------------- Receive Ports - RX Initialization and Reset Ports ------------
+		gt0_gtrxreset_in => rxReset_S, --// => '0',
+		gt0_rxpmareset_in => rxReset_S, --// => '0',
+        ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
+        gt0_rxcharisk_out => rxCharIsK16_S, 
+        -------------- Receive Ports -RX Initialization and Reset Ports ------------
+        gt0_rxresetdone_out => resetDone_S, 
+        --------------------- TX Initialization and Reset Ports --------------------
+        gt0_gttxreset_in => '0',
+        gt0_txuserrdy_in => '0',
+        ------------------ Transmit Ports - TX Data Path interface -----------------
+        gt0_txdata_in => txData16_S, 
+        ---------------- Transmit Ports - TX Driver and OOB signaling --------------
+        gt0_gtxtxn_out => SODA_TXD_N_OUT,
+        gt0_gtxtxp_out => SODA_TXD_P_OUT,
+        ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
+        gt0_txoutclkfabric_out => open,
+        gt0_txoutclkpcs_out => open,
+        --------------------- Transmit Ports - TX Gearbox Ports --------------------
+        gt0_txcharisk_in => txCharIsK16_S,     
+        ------------- Transmit Ports - TX Initialization and Reset Ports -----------
+        gt0_txresetdone_out => gt0_txresetdone_i,
+
+    --____________________________COMMON PORTS________________________________
+		GT0_QPLLOUTCLK_OUT  => open,
+		GT0_QPLLOUTREFCLK_OUT => open,
+		SYSCLK_IN => SYSCLK
+    );
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+
+sync_notintable1: DC_posedge_to_pulse port map(
+		clock_in => ff_rxhalfclk,
+		clock_out => SYSCLK,
+		en_clk => '1',
+		signal_in => rxNotInTable16_S(0),
+		pulse => rxNotInTable16_q(0));
+sync_notintable2: DC_posedge_to_pulse port map(
+		clock_in => ff_rxhalfclk,
+		clock_out => SYSCLK,
+		en_clk => '1',
+		signal_in => rxNotInTable16_S(1),
+		pulse => rxNotInTable16_q(1));
+
+
+DC_data16to8_1: DC_data16to8 
+	port map(
+		clock_in => ff_rxhalfclk,
+		data_in => rxData16_S,
+		kchar_in => rxCharIsK16_S,
+		notintable_in => rxNotInTable16_S,
+		clock_out => ff_rxfullclk,
+		data_out => rxData8_S,
+		kchar_out => rxCharIsK8_S,
+		notintable_out => open
+	);
+
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+	generic map(
+		USE_STATUS_FLAGS => c_NO
+	)
+	port map( read_clock_in  => SYSCLK,
+		write_clock_in     => ff_rxfullclk,
+		read_enable_in     => fifo_rx_rd_en,
+		write_enable_in    => fifo_rx_wr_en,
+		fifo_gsr_in        => fifo_rx_reset,
+		write_data_in      => fifo_rx_din,
+		read_data_out      => fifo_rx_dout,
+		full_out           => fifo_rx_full,
+		empty_out          => fifo_rx_empty
+	);
+
+fifo_rx_reset <= reset_i or not rx_allow_q;
+fifo_rx_rd_en <= not fifo_rx_empty;
+HUB_8to16_SODA1: HUB_8to16_SODA
+	port map(
+		clock => ff_rxfullclk,
+		reset => fifo_rx_reset,
+		data_in => rxData8_S,
+		char_is_k => rxCharIsK8_S,
+		fifo_data => fifo_rx_din,
+		fifo_full  => fifo_rx_full,
+		fifo_write => fifo_rx_wr_en,
+		RX_DLM => SODA_DLM_OUT_S,
+		RX_DLM_WORD => SODA_DLM_WORD_OUT_S,
+		error => open
+	);
+--//try SODA_DLM_OUT <= SODA_DLM_OUT_S;
+--//try SODA_DLM_WORD_OUT <= SODA_DLM_WORD_OUT_S;
+DC_SODA_clockcrossing2: DC_SODA_clockcrossing --//try
+	port map(
+		write_clock => ff_rxfullclk,
+		read_clock => SODA_clock,
+		DLM_in => SODA_DLM_OUT_S,
+		DLM_WORD_in => SODA_DLM_WORD_OUT_S,
+		DLM_out => SODA_DLM_OUT,
+		DLM_WORD_out => SODA_DLM_WORD_OUT,
+		error => open
+	);
+
+  	
+buf_med_data_out          <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out    <= rx_counter;
+med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
+
+THE_CNT_RESET_PROC : process(ff_rxhalfclk)
+begin
+	if rising_edge(ff_rxhalfclk) then
+		if reset_i_rx = '1' then
+			send_reset_words  <= '0';
+			make_trbnet_reset <= '0';
+			reset_word_cnt <= (others => '0');
+		else
+			send_reset_words   <= '0';
+			make_trbnet_reset  <= '0';
+			if (rxCharIsK16_S="11") and (rxData16_S=x"FEFE") then
+				if reset_word_cnt(4) = '0' then
+					reset_word_cnt <= reset_word_cnt + 1;
+				else
+					send_reset_words <= '1';
+				end if;
+			else
+				reset_word_cnt <= (others => '0');
+				make_trbnet_reset <= reset_word_cnt(4);
+			end if;
+		end if;
+	end if;
+end process;
+
+THE_SYNC_PROC: process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+			med_dataready_out     <= buf_med_dataready_out;
+			med_data_out          <= buf_med_data_out;
+			med_packet_num_out    <= buf_med_packet_num_out;
+		if reset_i = '1' then
+			med_dataready_out <= '0';
+		end if;
+	end if;
+end process;  
+  
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process(SYSCLK)
+begin
+	if( rising_edge(SYSCLK) ) then
+		last_fifo_rx_empty <= fifo_rx_empty;
+		if reset_i = '1' or rx_allow_q = '0' then
+			rx_counter <= c_H0;
+		else
+			if( buf_med_dataready_out = '1' ) then
+				if( rx_counter = c_max_word_number ) then
+					rx_counter <= (others => '0');
+				else
+					rx_counter <= rx_counter + 1;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;  
+
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+	generic map(
+		USE_STATUS_FLAGS => c_NO
+	)
+	port map( 
+		read_clock_in => ff_txfullclk,
+		write_clock_in => SYSCLK,
+		read_enable_in => fifo_tx_rd_en,
+		write_enable_in => fifo_tx_wr_en,
+		fifo_gsr_in => fifo_tx_reset,
+		write_data_in => fifo_tx_din,
+		read_data_out => fifo_tx_dout,
+		full_out => open,
+		empty_out => fifo_tx_empty,
+		almost_full_out   => fifo_tx_almost_full
+	);
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+ 
+clockdouble: DC_data16to8 port map( --//try
+		clock_in => ff_txhalfclk,
+        data_in => (others => '0'),
+        kchar_in => (others => '0'),
+        notintable_in => (others => '0'),
+        clock_out => ff_txfullclk,
+        data_out => open,
+        kchar_out => open,
+        notintable_out => open);
+
+HUB_16to8_SODA1: HUB_16to8_SODA
+	port map(
+		clock => ff_txfullclk,
+		reset => send_reset_in_qtx,
+		fifo_data => fifo_tx_dout(15 downto 0),
+		fifo_empty => fifo_tx_empty,
+		fifo_read => fifo_tx_rd_en,
+		TX_DLM => SODA_DLM_IN_S,
+		TX_DLM_WORD => SODA_DLM_WORD_IN_S,
+		data_out => txData8_S,
+		char_is_k => txCharIsK8_S,
+		error => open
+	);
+
+DC_SODA_clockcrossing1: DC_SODA_clockcrossing
+	port map(
+		write_clock => SODA_clock, -- ff_rxfullclk,  --//try
+		read_clock => ff_txfullclk,
+		DLM_in => SODA_DLM_IN,
+		DLM_WORD_in => SODA_DLM_WORD_IN,
+		DLM_out => SODA_DLM_IN_S,
+		DLM_WORD_out => SODA_DLM_WORD_IN_S,
+		error => open
+	);
+		
+DC_data8to16_1: DC_data8to16
+	port map( 
+		clock_in => ff_txfullclk,
+		data_in => txData8_S,
+		kchar_in => txCharIsK8_S,
+		clock_out => ff_txhalfclk,
+		data_out => txData16_S,
+		kchar_out => txCharIsK16_S
+	);  
+  
+rxLossOfSync1_S <= '0' when (rxNotInTable16_S="00") or (disable_GTX_reset='1') else '1';
+DC_rxBitLock1 : DC_rxBitLock port map (
+		clk => ff_rxhalfclk,
+		reset => quad_rst,
+		resetDone => resetDone_S,
+		lossOfSync => rxLossOfSync1_S,
+		rxPllLocked => PllLkDet_S,
+		rxReset => rxResetBitLock_S,
+		fsmStatus => fsmStatus_S
+	);
+	
+
+rxReset_S <= '1' when ((rxPLLwrapper_reset_S='1') or (quad_rst='1') or (rxResetBitLock_pulse_S='1')) and (disable_GTX_reset='0') else '0';
+
+rxLocked0_S <= '1' when (resetDone_S='1') and (fsmStatus_S = "10") else '0';
+sync_rx_locked: sync_bit port map(
+	clock => SYSCLK,
+	data_in => rxLocked0_S,
+	data_out => rxLocked1_S);
+
+process(SYSCLK) 
+begin
+	if rising_edge(SYSCLK) then
+		if (sync_rxResetBitLock_S='1') and (prev_rxResetBitLock_S='0') then
+			rxResetBitLock_pulse_S <= '1';
+		else	
+			rxResetBitLock_pulse_S <= '0';
+		end if;
+		sync_rxResetBitLock_S <= rxResetBitLock_S;
+		prev_rxResetBitLock_S <= sync_rxResetBitLock_S;
+	end if;
+end process;
+process(SYSCLK) 
+variable counter_V : std_logic_vector(5 downto 0) := (others => '0');
+variable timoutcounter_V : std_logic_vector(11 downto 0) := (others => '0');
+begin
+	if rising_edge(SYSCLK) then
+		rxPLLwrapper_reset_S <= '0';
+		CDR_reset_S <= '0';
+		comma_align_latency0_valid_S <= '0';
+		drpen_in_S <= '0';
+		drpwe_in_S <= '0';
+		drpdi_in_S <= (others => '0');
+		case drp_state_S is
+			when initting =>
+				rxLocked2_S	<= '0';
+				counter_V := (others => '0');
+				if resetDone_S='1' then
+					drp_state_S <= running;
+				end if;
+			when running =>
+				if rxLocked1_S='0' then
+					drp_state_S <= initting;
+				else
+					if counter_V(counter_V'left) = '1' then
+						counter_V := (others => '0');
+						timoutcounter_V := (others => '0');
+						drpen_in_S <= '1';
+						drpaddr_in_S <= "101001110"; -- x"14E";
+						drp_state_S <= reading;
+					else
+						counter_V := counter_V+1;
+					end if;
+				end if;
+			when reading =>
+				if drprdy_out_S='1' then
+					comma_align_latency_S <= drpdo_out_S(6 downto 0); --		COMMA_ALIGN_LATENCY
+					comma_align_latency0_valid_S <= '1';
+					if drpdo_out_S(6 downto 0)/="0000000" then
+						CDR_reset_S <= '1'; --// rxPLLwrapper_reset_S <= '1';
+						rxLocked2_S	<= '0';
+					else 
+						rxLocked2_S	<= '1';
+					end if;
+					drp_state_S <= running;
+				elsif timoutcounter_V(timoutcounter_V'left)='1' then
+					CDR_reset_S <= '1';
+					rxPLLwrapper_reset_S <= '1';
+					drp_state_S <= initting;
+				else
+					timoutcounter_V := timoutcounter_V+1;
+				end if;
+			when others =>
+				drp_state_S <= initting;
+		end case;
+	end if;
+end process;
+
+
+
+--Generate LED signals
+----------------------
+process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+		led_counter <= led_counter + 1;
+		if buf_med_dataready_out = '1' then
+			rx_led <= '1';
+		elsif led_counter = 0 then
+			rx_led <= '0';
+		end if;
+		if fifo_tx_wr_en = '1' then
+			tx_led <= '1';
+		elsif led_counter = 0 then
+			tx_led <= '0';
+		end if;
+	end if;
+end process;
+
+stat_op(15)           <= send_reset_words_q;
+stat_op(14)           <= buf_stat_op(14);
+stat_op(13)           <= make_trbnet_reset_q;
+stat_op(12)           <= '0';
+stat_op(11)           <= tx_led; --tx led
+stat_op(10)           <= rx_led; --rx led
+stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(15 downto 0)  <= rxData16_S;
+stat_debug(17 downto 16) <= rxCharIsK16_S;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(24)           <= fifo_rx_rd_en;
+stat_debug(25)           <= fifo_rx_wr_en;
+stat_debug(26)           <= fifo_rx_reset;
+stat_debug(27)           <= fifo_rx_empty;
+stat_debug(28)           <= fifo_rx_full;
+stat_debug(29)           <= '0';
+stat_debug(30)           <= rx_allow_q;
+stat_debug(41 downto 31) <= (others => '0');
+stat_debug(42)           <= SYSCLK;
+stat_debug(43)           <= SYSCLK;
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
+
+end architecture;
\ No newline at end of file
diff --git a/data_concentrator/sources/xilinx/trb_net_fifo_16bit_bram_dualport.vhd b/data_concentrator/sources/xilinx/trb_net_fifo_16bit_bram_dualport.vhd
new file mode 100644
index 0000000..58341de
--- /dev/null
+++ b/data_concentrator/sources/xilinx/trb_net_fifo_16bit_bram_dualport.vhd
@@ -0,0 +1,71 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+library unisim;
+use UNISIM.VComponents.all;
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_fifo_16bit_bram_dualport is
+   generic(
+     USE_STATUS_FLAGS : integer  := c_YES
+     );
+   port (
+     read_clock_in:   IN  std_logic;
+     write_clock_in:  IN  std_logic;
+     read_enable_in:  IN  std_logic;
+     write_enable_in: IN  std_logic;
+     fifo_gsr_in:     IN  std_logic;
+     write_data_in:   IN  std_logic_vector(17 downto 0);
+     read_data_out:   OUT std_logic_vector(17 downto 0);
+     full_out:        OUT std_logic;
+     empty_out:       OUT std_logic;
+     fifostatus_out:  OUT std_logic_vector(3 downto 0);
+     valid_read_out:  OUT std_logic;
+     almost_empty_out:OUT std_logic;
+     almost_full_out :OUT std_logic
+    );
+end entity trb_net_fifo_16bit_bram_dualport;
+
+architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport is
+
+  signal buf_empty_out, buf_full_out : std_logic;
+
+attribute box_type: string;
+  component xilinx_fifo_dualport_18x1k
+    port (
+      din: IN std_logic_VECTOR(17 downto 0);
+      rd_clk: IN std_logic;
+      rd_en: IN std_logic;
+      rst: IN std_logic;
+      wr_clk: IN std_logic;
+      wr_en: IN std_logic;
+      dout: OUT std_logic_VECTOR(17 downto 0);
+      empty: OUT std_logic;
+      full: OUT std_logic;
+      valid: OUT std_logic);
+  end component;
+attribute box_type of xilinx_fifo_dualport_18x1k : component is "black_box";
+
+BEGIN
+  FIFO_DP_BRAM : xilinx_fifo_dualport_18x1k
+    port map (
+      din => write_data_in,
+      rd_clk => read_clock_in,
+      rd_en => read_enable_in,
+      rst => fifo_gsr_in,
+      wr_clk => write_clock_in,
+      wr_en => write_enable_in,
+      dout => read_data_out,
+      empty => buf_empty_out,
+      full => buf_full_out,
+      valid => valid_read_out
+      );
+
+empty_out <= buf_empty_out;
+full_out  <= buf_full_out;
+almost_full_out <= buf_full_out;
+almost_empty_out <= buf_empty_out;
+fifostatus_out <= (others => '0');
+end architecture;
+
diff --git a/data_concentrator/sources/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd b/data_concentrator/sources/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd
new file mode 100644
index 0000000..58341de
--- /dev/null
+++ b/data_concentrator/sources/xilinx/trb_net_fifo_16bit_bram_dualport_arch.vhd
@@ -0,0 +1,71 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+library unisim;
+use UNISIM.VComponents.all;
+library work;
+use work.trb_net_std.all;
+
+entity trb_net_fifo_16bit_bram_dualport is
+   generic(
+     USE_STATUS_FLAGS : integer  := c_YES
+     );
+   port (
+     read_clock_in:   IN  std_logic;
+     write_clock_in:  IN  std_logic;
+     read_enable_in:  IN  std_logic;
+     write_enable_in: IN  std_logic;
+     fifo_gsr_in:     IN  std_logic;
+     write_data_in:   IN  std_logic_vector(17 downto 0);
+     read_data_out:   OUT std_logic_vector(17 downto 0);
+     full_out:        OUT std_logic;
+     empty_out:       OUT std_logic;
+     fifostatus_out:  OUT std_logic_vector(3 downto 0);
+     valid_read_out:  OUT std_logic;
+     almost_empty_out:OUT std_logic;
+     almost_full_out :OUT std_logic
+    );
+end entity trb_net_fifo_16bit_bram_dualport;
+
+architecture trb_net_fifo_16bit_bram_dualport_arch of trb_net_fifo_16bit_bram_dualport is
+
+  signal buf_empty_out, buf_full_out : std_logic;
+
+attribute box_type: string;
+  component xilinx_fifo_dualport_18x1k
+    port (
+      din: IN std_logic_VECTOR(17 downto 0);
+      rd_clk: IN std_logic;
+      rd_en: IN std_logic;
+      rst: IN std_logic;
+      wr_clk: IN std_logic;
+      wr_en: IN std_logic;
+      dout: OUT std_logic_VECTOR(17 downto 0);
+      empty: OUT std_logic;
+      full: OUT std_logic;
+      valid: OUT std_logic);
+  end component;
+attribute box_type of xilinx_fifo_dualport_18x1k : component is "black_box";
+
+BEGIN
+  FIFO_DP_BRAM : xilinx_fifo_dualport_18x1k
+    port map (
+      din => write_data_in,
+      rd_clk => read_clock_in,
+      rd_en => read_enable_in,
+      rst => fifo_gsr_in,
+      wr_clk => write_clock_in,
+      wr_en => write_enable_in,
+      dout => read_data_out,
+      empty => buf_empty_out,
+      full => buf_full_out,
+      valid => valid_read_out
+      );
+
+empty_out <= buf_empty_out;
+full_out  <= buf_full_out;
+almost_full_out <= buf_full_out;
+almost_empty_out <= buf_empty_out;
+fifostatus_out <= (others => '0');
+end architecture;
+
diff --git a/data_concentrator/test_module.vhd b/data_concentrator/test_module.vhd
deleted file mode 100644
index b52c213..0000000
--- a/data_concentrator/test_module.vhd
+++ /dev/null
@@ -1,174 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-
-  entity test_module is
-    port (
-      CLK_IN            : in  std_logic;
-      RESET_IN          : in  std_logic;
-      -- Slave bus
-      BUS_READ_IN       : in   std_logic;
-      BUS_WRITE_IN      : in   std_logic;
-      BUS_BUSY_OUT      : out  std_logic;
-      BUS_ACK_OUT       : out  std_logic;
-      BUS_ADDR_IN       : in   std_logic_vector(1 downto 0);
-      BUS_DATA_IN       : in   std_logic_vector(31 downto 0);
-      BUS_DATA_OUT      : out  std_logic_vector(31 downto 0);
-      LEDS_ACT_OUT      : out  std_logic;
-      LEDS_OUT          : out  std_logic_vector(3 downto 0);
-      SPARE_LINE        : in  std_logic_vector(5 downto 0);
-      TEST_LINE         : out  std_logic_vector(15 downto 0);
-      -- Status lines
-      STAT              : out  std_logic_vector(31 downto 0) -- DEBUG
-	  );
-end entity;
-
-architecture Behavioral of test_module is
--- Signals
-  type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
-  signal CURRENT_STATE, NEXT_STATE: STATES;
-
-  -- slave bus signals
-  signal bus_ack_x        : std_logic;
-  signal bus_ack          : std_logic;
-  signal store_wr_x       : std_logic;
-  signal store_wr         : std_logic;
-  signal store_rd_x       : std_logic;
-  signal store_rd         : std_logic;
-  signal buf_bus_data_out : std_logic_vector(31 downto 0);
-
-  signal LEDregister_i    : std_logic_vector(31 downto 0);
-  signal TEST_LINE_i      : std_logic_vector(31 downto 0);
-			  
-begin
-
----------------------------------------------------------
--- Debugging                                           --
----------------------------------------------------------
-stat(31 downto 0)  <= (others => '0');
-
----------------------------------------------------------
--- Statemachine                                        --
----------------------------------------------------------
-  STATE_MEM: process( clk_in)
-    begin
-      if( rising_edge(clk_in) ) then
-        if( RESET_IN = '1' ) then
-          CURRENT_STATE <= SLEEP;
-          bus_ack       <= '0';
-          store_wr      <= '0';
-          store_rd      <= '0';
-        else
-          CURRENT_STATE <= NEXT_STATE;
-          bus_ack       <= bus_ack_x;
-          store_wr      <= store_wr_x;
-          store_rd      <= store_rd_x;
-        end if;
-      end if;
-    end process STATE_MEM;
-
--- Transition matrix
-  TRANSFORM: process(CURRENT_STATE, BUS_read_in, BUS_write_in )
-    begin
-      NEXT_STATE <= SLEEP;
-      bus_ack_x  <= '0';
-      store_wr_x <= '0';
-      store_rd_x <= '0';
-      case CURRENT_STATE is
-        when SLEEP    =>
-          if   ( (BUS_read_in = '1') ) then
-            NEXT_STATE <= RD_RDY;
-            store_rd_x <= '1';
-          elsif( (BUS_write_in = '1') ) then
-            NEXT_STATE <= WR_RDY;
-            store_wr_x <= '1';
-          else
-            NEXT_STATE <= SLEEP;
-          end if;
-
-        when RD_RDY    =>
-          NEXT_STATE <= RD_ACK;
-
-        when WR_RDY    =>
-          NEXT_STATE <= WR_ACK;
-
-        when RD_ACK    =>
-          if( BUS_read_in = '0' ) then
-            NEXT_STATE <= DONE;
-            bus_ack_x  <= '1';
-          else
-            NEXT_STATE <= RD_ACK;
-            bus_ack_x  <= '1';
-          end if;
-
-        when WR_ACK    =>
-          if( BUS_write_in = '0' ) then
-            NEXT_STATE <= DONE;
-            bus_ack_x  <= '1';
-          else
-            NEXT_STATE <= WR_ACK;
-            bus_ack_x  <= '1';
-          end if;
-
-        when DONE    =>
-          NEXT_STATE <= SLEEP;
-
-        when others    =>
-          NEXT_STATE <= SLEEP;
-  end case;
-end process TRANSFORM;
-
-
----------------------------------------------------------
--- data handling                                       --
----------------------------------------------------------
-
--- register write
-THE_WRITE_REG_PROC: process( clk_in )
-  begin
-      if( rising_edge(clk_in) ) then
-          if   ( RESET_IN = '1' ) then
-              LEDregister_i <= (others => '0');
-              TEST_LINE_i <= (others => '0');
-           elsif( (store_wr = '1') and (bus_addr_in = "00") ) then
-              LEDregister_i <= bus_data_in;
-           elsif( (store_wr = '1') and (bus_addr_in = "01") ) then
-              TEST_LINE_i <= bus_data_in;
-          else
-          end if;
-      end if;
-  end process THE_WRITE_REG_PROC;
-  
-LEDS_OUT <= LEDregister_i(3 downto 0);
-LEDS_ACT_OUT <= LEDregister_i(4);
-TEST_LINE <= TEST_LINE_i(15 downto 0);  
-
--- register read
-THE_READ_REG_PROC: process( clk_in )
-  begin
-      if( rising_edge(clk_in) ) then
-          if   ( RESET_IN = '1' ) then
-              buf_bus_data_out <= (others => '0');
-          elsif( (store_rd = '1') and (bus_addr_in = "00") ) then
-              buf_bus_data_out <= LEDregister_i;
-          elsif( (store_rd = '1') and (bus_addr_in = "01") ) then
-              buf_bus_data_out <= TEST_LINE_i;
-          elsif( (store_rd = '1') and (bus_addr_in = "10") ) then
-              buf_bus_data_out(5 downto 0) <= SPARE_LINE;
-              buf_bus_data_out(31 downto 6) <= (others => '0');
-          end if;
-      end if;
-  end process THE_READ_REG_PROC;
- 
-
--- output signals
-BUS_DATA_OUT <= buf_bus_data_out;
-BUS_ACK_OUT  <= bus_ack;
-BUS_BUSY_OUT <= '0';
-
-end Behavioral;
diff --git a/data_concentrator/trb3_periph_data_concentrator.sdc b/data_concentrator/trb3_periph_data_concentrator.sdc
new file mode 100644
index 0000000..f3d7aac
--- /dev/null
+++ b/data_concentrator/trb3_periph_data_concentrator.sdc
@@ -0,0 +1,17 @@
+define_clock   {n:THE_MAIN_PLL.CLKOP} -name {clk_65_i}  -freq 65
+define_clock   {n:THE_MAIN_PLL.CLKOS} -name {clk_200_i}  -freq 200
+define_clock   {n:THE_CLKDIV.CDIV2} -name {clk_100_i}  -freq 100
+define_clock   {n:THE_MEDIA_UPLINK.THE_SERDES.rx_full_clk_ch2} -name {rx_full_clk_ch2}  -freq 200
+define_clock   {n:THE_MEDIA_UPLINK.THE_SERDES.tx_full_clk_ch2} -name {tx_full_clk_ch2}  -freq 200
+define_clock   {n:THE_MEDIA_UPLINK.THE_SERDES.rx_full_clk_ch3} -name {tx_full_clk_ch3}  -freq 200
+define_clock   {n:THE_MEDIA_UPLINK.THE_SERDES.tx_full_clk_ch3} -name {rx_full_clk_ch3}  -freq 200
+define_clock   {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.THE_SERDES.rx_full_clk_ch0} -name {rx_fee_clk0}  -freq 200
+define_clock   {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.THE_SERDES.rx_full_clk_ch1} -name {rx_fee_clk1}  -freq 200
+define_clock   {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.THE_SERDES.rx_full_clk_ch2} -name {rx_fee_clk2}  -freq 200
+define_clock   {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.THE_SERDES.rx_full_clk_ch3} -name {rx_fee_clk3}  -freq 200
+define_clock   {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.clk_tx_full[0]} -name {tx_fee_clk0}  -freq 200
+define_clock   {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.clk_tx_full[1]} -name {tx_fee_clk1}  -freq 200
+define_clock   {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.clk_tx_full[2]} -name {tx_fee_clk2}  -freq 200
+define_clock   {n:THE_FEE_SERDES.serdesQuadMUXwrapper1.med_ecp3_quad_sfp_sync1.clk_tx_full[3]} -name {tx_fee_clk3}  -freq 200
+define_clock   {n:clk_SODA200_i} -name {clk_SODA200_i}  -freq 200
+
diff --git a/data_concentrator/trb3_periph_data_concentrator_only1error_200MHz.lpf b/data_concentrator/trb3_periph_data_concentrator_only1error_200MHz.lpf
deleted file mode 100644
index cdb9c4c..0000000
--- a/data_concentrator/trb3_periph_data_concentrator_only1error_200MHz.lpf
+++ /dev/null
@@ -1,268 +0,0 @@
-rvl_alias "clk_80_i" "clk_80_i";
-RVL_ALIAS "clk_62M5_i" "clk_62M5_i"; 
-RVL_ALIAS "clk_62M5_i" "clk_62M5_i"; 
-RVL_ALIAS "clk_100_i" "clk_100_i"; 
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-SYSCONFIG MCCLK_FREQ=2.5 ;
-FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ;
-FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
-FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ;
-FREQUENCY PORT "CLK_GPLL_LEFT" 125.000000 MHz ;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18" ;
-LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-DEFINE PORT GROUP "CLK_group" "CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# Trigger I/O
-#################################################################
-#Trigger from fan-out
-LOCATE COMP "TRIGGER_LEFT" SITE "V3" ;
-LOCATE COMP "TRIGGER_RIGHT" SITE "N24" ;
-IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
-IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0   #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1   #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2   #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3   #7
-LOCATE COMP "SFP_MOD1_1" SITE "R1" ;#DQLL0_4   #9
-LOCATE COMP "SFP_MOD2_1" SITE "R2" ;#DQLL0_5   #11
-LOCATE COMP "SFP_RATESEL_1" SITE "N3" ;#DQSLL0_T  #13
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C  #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6   #17
-LOCATE COMP "SFP_TXFAULT_1" SITE "P6" ;#DQLL0_7   #19
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8   #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9   #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0   #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1   #27
-LOCATE COMP "SFP_MOD1_2" SITE "AB1" ;#DQLL2_2   #29
-LOCATE COMP "SFP_MOD2_2" SITE "AC1" ;#DQLL2_3   #31
-LOCATE COMP "SFP_RATESEL_2" SITE "AA1" ;#DQLL2_4   #33
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5   #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
-LOCATE COMP "SFP_TXFAULT_2" SITE "W6" ;#DQLL2_C   #39  #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0   #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1   #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2   #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3   #8
-LOCATE COMP "SFP_MOD1_3" SITE "AB3" ;#DQLL3_4   #10
-LOCATE COMP "SFP_MOD2_3" SITE "AB4" ;#DQLL3_5   #12
-LOCATE COMP "SFP_RATESEL_3" SITE "Y6" ;#DQLL3_T   #14  #should be DQSLL3
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6   #18
-LOCATE COMP "SFP_TXFAULT_3" SITE "AA4" ;#DQLL3_7   #20
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8   #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9   #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0   #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1   #28
-LOCATE COMP "SFP_MOD1_4" SITE "T1" ;#DQLL1_2   #30
-LOCATE COMP "SFP_MOD2_4" SITE "U1" ;#DQLL1_3   #32
-LOCATE COMP "SFP_RATESEL_4" SITE "P4" ;#DQLL1_4   #34
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5   #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T  #38
-LOCATE COMP "SFP_TXFAULT_4" SITE "R4" ;#DQSLL1_C  #40
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0   #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1   #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2   #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3   #175
-LOCATE COMP "SFP_MOD1_5" SITE "AA26" ;#DQLR1_4   #177
-LOCATE COMP "SFP_MOD2_5" SITE "AB26" ;#DQLR1_5   #179
-LOCATE COMP "SFP_RATESEL_5" SITE "W21" ;#DQSLR1_T  #181
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C  #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6   #185
-LOCATE COMP "SFP_TXFAULT_5" SITE "AA23" ;#DQLR1_7   #187
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0   #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1   #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2   #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3   #176
-LOCATE COMP "SFP_MOD1_6" SITE "T26" ;#DQLR2_4   #178
-LOCATE COMP "SFP_MOD2_6" SITE "U26" ;#DQLR2_5   #180
-LOCATE COMP "SFP_RATESEL_6" SITE "V21" ;#DQSLR2_T  #182
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C  #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6   #186
-LOCATE COMP "SFP_TXFAULT_6" SITE "V24" ;#DQLR2_7   #188
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-LOCATE COMP "SPARE_LINE[0]" SITE "M25" ;#194
-LOCATE COMP "SPARE_LINE[1]" SITE "M26" ;#196
-LOCATE COMP "SPARE_LINE[2]" SITE "W4" ;#198
-LOCATE COMP "SPARE_LINE[3]" SITE "W5" ;#200
-LOCATE COMP "SPARE_LINE[4]" SITE "M3" ;#DQUL3_8_OUTOFLANE_FPGA__3 #69
-LOCATE COMP "SPARE_LINE[5]" SITE "M2" ;#DQUL3_9_OUTOFLANE_FPGA__3 #71  
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-MULTICYCLE TO GROUP "LED_group" 100.000000 ns ;
-#################################################################
-# Basic Settings
-#################################################################
-SYSCONFIG MCCLK_FREQ=20 ;
-FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ;
-FREQUENCY PORT "CLK_PCLK_LEFT" 200.000000 MHz ;
-FREQUENCY PORT "CLK_GPLL_RIGHT" 200.000000 MHz ;
-FREQUENCY PORT "CLK_GPLL_LEFT" 125.000000 MHz ;
-#################################################################
-# Reset Nets
-#################################################################  
-GSR_NET NET "GSR_N";
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-#//?   LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#//?   LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_125_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-#####REGION "MEDIA_UPLINK" "R90C95D" 13 25;
-#####REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;
-REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE;
-#####REGION "REGION_IOBUF" "R10C43D"  88 86 DEVSIZE;
-LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ;
-LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-#####LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-#####LOCATE UGROUP "THE_SODA_SOURCE/media_interface_group" REGION "MEDIA_DOWNLINK" ;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/sci*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/wa_pos*" 20.000000 ns ;
-#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
-MAXSKEW NET "clk_125_i" 1.000000 nS ;
-MAXSKEW NET "clk_160_i" 1.000000 nS ;
-MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_62M5_i" 8.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_125_i" 8.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_62M5_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_100_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_62M5_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_200_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_125_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_100_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_125_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_200_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_160_i" TO CLKNET "clk_80_i" 6.250000 ns ;
-MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_160_i" 6.250000 ns ;
-MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_80_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_100_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_80_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_200_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "clk_160_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_160_i" TO CLKNET "clk_100_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "clk_160_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_160_i" TO CLKNET "clk_200_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_62M5_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_62M5_i" TO CLKNET "clk_80_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_125_i" TO CLKNET "clk_80_i" 200.000000 ns ;
-MULTICYCLE FROM CLKNET "clk_80_i" TO CLKNET "clk_125_i" 200.000000 ns ;
-
-
-BLOCK JTAGPATHS ;
-#MAXSKEW NET "the_dataconcentrator/dc_quad_fiber_module_all/serdesquadbuflayermux1/serdesquadmuxwrapper1/med_ecp3_quad_sfp_sync1/tx_sync_qd_c" 1.000000 nS ;
-#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 0.100000 ns ;
-#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 0.100000 ns ;
-#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 0.100000 ns ;
-#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" TO CLKNET "clk_125_i_c" 0.200000 ns ;
-#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" TO CLKNET "clk_125_i_c" 0.200000 ns ;
-#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" TO CLKNET "clk_125_i_c" 0.200000 ns ;
-#MULTICYCLE FROM CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" TO CLKNET "clk_125_i_c" 0.200000 ns ;
-#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1.000000 nS ;
-#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1.000000 nS ;
-#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1.000000 nS ;
-#MAXSKEW NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1.000000 nS ;
-#MAXDELAY FROM CELL "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/tx_sync_qd_c" TO ASIC "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/THE_SERDES/PCSD_INST" PIN "FFC_SYNC_TOGGLE" 1.200000 ns ;
-#MULTICYCLE FROM CLKNET "clk_125_i_c" TO CLKNET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 0.100000 ns ;
-#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1.000000 nS  ;
-#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1.000000 nS  ;
-#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1.000000 nS  ;
-#PERIOD NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1.000000 nS  ;
-#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full1" 1000.000000 MHz ;
-#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full2" 1000.000000 MHz ;
-#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full3" 1000.000000 MHz ;
-#FREQUENCY NET "THE_DATACONCENTRATOR/DC_Quad_fiber_module_all/serdesQuadBufLayerMUX1/serdesQuadMUXwrapper1/med_ecp3_quad_sfp_sync1/clk_tx_full0" 1000.000000 MHz ;
diff --git a/data_concentrator/trb_net16_endpoint_data_concentrator.vhd b/data_concentrator/trb_net16_endpoint_data_concentrator.vhd
deleted file mode 100644
index 199637d..0000000
--- a/data_concentrator/trb_net16_endpoint_data_concentrator.vhd
+++ /dev/null
@@ -1,1079 +0,0 @@
--- the full endpoint for HADES: trg, data, unused, regio
-
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-
-
-entity trb_net16_endpoint_data_concentrator is
-  generic (
-    USE_CHANNEL                  : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
-    IBUF_DEPTH                   : channel_config_t := (6,6,6,6);
-    FIFO_TO_INT_DEPTH            : channel_config_t := (6,6,6,6);
-    FIFO_TO_APL_DEPTH            : channel_config_t := (1,1,1,1);
-    IBUF_SECURE_MODE             : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-    API_SECURE_MODE_TO_APL       : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-    API_SECURE_MODE_TO_INT       : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-    OBUF_DATA_COUNT_WIDTH        : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
-    INIT_CAN_SEND_DATA           : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
-    REPLY_CAN_SEND_DATA          : channel_config_t := (c_YES,c_YES,c_YES,c_YES);
-    REPLY_CAN_RECEIVE_DATA       : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
-    USE_CHECKSUM                 : channel_config_t := (c_NO,c_YES,c_YES,c_YES);
-    APL_WRITE_ALL_WORDS          : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
-    ADDRESS_MASK                 : std_logic_vector(15 downto 0) := x"FFFF";
-    BROADCAST_BITMASK            : std_logic_vector(7 downto 0) := x"FF";
-    BROADCAST_SPECIAL_ADDR       : std_logic_vector(7 downto 0) := x"FF";
-    TIMING_TRIGGER_RAW           : integer range 0 to 1 := c_YES;
-    REGIO_NUM_STAT_REGS          : integer range 0 to 6 := 3; --log2 of number of status registers
-    REGIO_NUM_CTRL_REGS          : integer range 0 to 6 := 3; --log2 of number of ctrl registers
-    --standard values for output registers
-    REGIO_INIT_CTRL_REGS         : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
-    --set to 0 for unused ctrl registers to save resources
-    REGIO_USED_CTRL_REGS         : std_logic_vector(2**(4)-1 downto 0)    := (others => '1');
-    --set to 0 for each unused bit in a register
-    REGIO_USED_CTRL_BITMASK      : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
-    REGIO_USE_DAT_PORT           : integer range 0 to 1 := c_YES;  --internal data port
-    REGIO_INIT_ADDRESS           : std_logic_vector(15 downto 0) := x"FFFF";
-    REGIO_INIT_UNIQUE_ID         : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
-    REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
-    REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
-    REGIO_COMPILE_TIME           : std_logic_vector(31 downto 0) := x"00000000";
-    REGIO_COMPILE_VERSION        : std_logic_vector(15 downto 0) := x"0001";
-    REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
-    REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
-    REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES := c_NO;
-    CLOCK_FREQUENCY              : integer range 1 to 200 := 100
-    );
-
-  port(
-    --  Misc
-    CLK                          : in std_logic;
-    RESET                        : in std_logic;
-    CLK_EN                       : in std_logic := '1';
-
-    --  Media direction port
-    MED_DATAREADY_OUT            : out std_logic;
-    MED_DATA_OUT                 : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_OUT           : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-    MED_READ_IN                  : in  std_logic;
-    MED_DATAREADY_IN             : in  std_logic;
-    MED_DATA_IN                  : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_IN            : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-    MED_READ_OUT                 : out std_logic;
-    MED_STAT_OP_IN               : in  std_logic_vector(15 downto 0);
-    MED_CTRL_OP_OUT              : out std_logic_vector(15 downto 0);
-
-    -- LVL1 trigger APL
-    TRG_TIMING_TRG_RECEIVED_IN   : in  std_logic;    --strobe when timing trigger received or real timing trigger signal
-
-    LVL1_TRG_DATA_VALID_OUT      : out std_logic;    --trigger type, number, code, information are valid
-    LVL1_TRG_VALID_TIMING_OUT    : out std_logic;    --valid timing trigger has been received
-    LVL1_TRG_VALID_NOTIMING_OUT  : out std_logic;    --valid trigger without timing trigger has been received
-    LVL1_TRG_INVALID_OUT         : out std_logic;    --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
-
-    LVL1_TRG_TYPE_OUT            : out std_logic_vector(3 downto 0);
-    LVL1_TRG_NUMBER_OUT          : out std_logic_vector(15 downto 0);
-    LVL1_TRG_CODE_OUT            : out std_logic_vector(7 downto 0);
-    LVL1_TRG_INFORMATION_OUT     : out std_logic_vector(23 downto 0);
-
-    LVL1_ERROR_PATTERN_IN        : in  std_logic_vector(31 downto 0) := x"00000000";
-    LVL1_TRG_RELEASE_IN          : in  std_logic := '0';
-    LVL1_INT_TRG_NUMBER_OUT      : out std_logic_vector(15 downto 0);  --internally generated trigger number, for informational uses only
-
-    --Information about trigger handler errors
-    TRG_MULTIPLE_TRG_OUT         : out std_logic;
-    TRG_TIMEOUT_DETECTED_OUT     : out std_logic;
-    TRG_SPURIOUS_TRG_OUT         : out std_logic;
-    TRG_MISSING_TMG_TRG_OUT      : out std_logic;
-    TRG_SPIKE_DETECTED_OUT       : out std_logic;
-    TRG_LONG_TRG_OUT             : out std_logic;
-
-    --Data Port
-    IPU_NUMBER_OUT               : out std_logic_vector (15 downto 0);
-    IPU_READOUT_TYPE_OUT         : out std_logic_vector (3 downto 0);
-    IPU_INFORMATION_OUT          : out std_logic_vector (7 downto 0);
-    --start strobe
-    IPU_START_READOUT_OUT        : out std_logic;
-    --detector data, equipped with DHDR
-    IPU_DATA_IN                  : in  std_logic_vector (31 downto 0);
-    IPU_DATAREADY_IN             : in  std_logic;
-    --no more data, end transfer, send TRM
-    IPU_READOUT_FINISHED_IN      : in  std_logic;
-    --will be low every second cycle due to 32bit -> 16bit conversion
-    IPU_READ_OUT                 : out std_logic;
-    IPU_LENGTH_IN                : in  std_logic_vector (15 downto 0);
-    IPU_ERROR_PATTERN_IN         : in  std_logic_vector (31 downto 0);
-
-
-    -- Slow Control Data Port
-    REGIO_COMMON_STAT_REG_IN  : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
-    REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-    REGIO_REGISTERS_IN        : in  std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
-    REGIO_REGISTERS_OUT       : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-    COMMON_STAT_REG_STROBE    : out std_logic_vector(std_COMSTATREG-1 downto 0);
-    COMMON_CTRL_REG_STROBE    : out std_logic_vector(std_COMCTRLREG-1 downto 0);
-    STAT_REG_STROBE           : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
-    CTRL_REG_STROBE           : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-    --following ports only used when using internal data port
-    REGIO_ADDR_OUT            : out std_logic_vector(16-1 downto 0);
-    REGIO_READ_ENABLE_OUT     : out std_logic;
-    REGIO_WRITE_ENABLE_OUT    : out std_logic;
-    REGIO_DATA_OUT            : out std_logic_vector(32-1 downto 0);
-    REGIO_DATA_IN             : in  std_logic_vector(32-1 downto 0) := (others => '0');
-    REGIO_DATAREADY_IN        : in  std_logic := '0';
-    REGIO_NO_MORE_DATA_IN     : in  std_logic := '0';
-    REGIO_WRITE_ACK_IN        : in  std_logic := '0';
-    REGIO_UNKNOWN_ADDR_IN     : in  std_logic := '0';
-    REGIO_TIMEOUT_OUT         : out std_logic;
-    --IDRAM is used if no 1-wire interface, onewire used otherwise
-    REGIO_IDRAM_DATA_IN       : in  std_logic_vector(15 downto 0) := (others => '0');
-    REGIO_IDRAM_DATA_OUT      : out std_logic_vector(15 downto 0);
-    REGIO_IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0) := "000";
-    REGIO_IDRAM_WR_IN         : in  std_logic := '0';
-    REGIO_ONEWIRE_INOUT       : inout std_logic;  --temperature sensor
-    REGIO_ONEWIRE_MONITOR_IN  : in  std_logic := '0';
-    REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
-    REGIO_VAR_ENDPOINT_ID     : in  std_logic_vector(15 downto 0) := (others => '0');
-
-    GLOBAL_TIME_OUT           : out std_logic_vector(31 downto 0); --global time, microseconds
-    LOCAL_TIME_OUT            : out std_logic_vector(7 downto 0);  --local time running with chip frequency
-    TIME_SINCE_LAST_TRG_OUT   : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
-    TIMER_TICKS_OUT           : out std_logic_vector(1 downto 0);  --bit 1 ms-tick, 0 us-tick
-    --Debugging & Status information
-    STAT_DEBUG_IPU            : out std_logic_vector (31 downto 0);
-    STAT_DEBUG_1              : out std_logic_vector (31 downto 0);
-    STAT_DEBUG_2              : out std_logic_vector (31 downto 0);
-    MED_STAT_OP               : out std_logic_vector (15 downto 0);
-    CTRL_MPLEX                : in  std_logic_vector (31 downto 0) := (others => '0');
-    IOBUF_CTRL_GEN            : in  std_logic_vector (4*32-1 downto 0) := (others => '0');
-    STAT_ONEWIRE              : out std_logic_vector (31 downto 0);
-    STAT_ADDR_DEBUG           : out std_logic_vector (15 downto 0);
-    STAT_TRIGGER_OUT          : out std_logic_vector (79 downto 0);
-    DEBUG_LVL1_HANDLER_OUT    : out std_logic_vector (15 downto 0)
-    );
-end trb_net16_endpoint_data_concentrator;
-
-
-
-
-
-architecture trb_net16_endpoint_data_concentrator_arch of trb_net16_endpoint_data_concentrator is
-
-
-  signal apl_to_buf_INIT_DATAREADY: std_logic_vector(3 downto 0);
-  signal apl_to_buf_INIT_DATA     : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-  signal apl_to_buf_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-  signal apl_to_buf_INIT_READ     : std_logic_vector(3 downto 0);
-
-  signal buf_to_apl_INIT_DATAREADY: std_logic_vector(3 downto 0);
-  signal buf_to_apl_INIT_DATA     : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-  signal buf_to_apl_INIT_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-  signal buf_to_apl_INIT_READ     : std_logic_vector(3 downto 0);
-
-  signal apl_to_buf_REPLY_DATAREADY: std_logic_vector(3 downto 0);
-  signal apl_to_buf_REPLY_DATA     : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-  signal apl_to_buf_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-  signal apl_to_buf_REPLY_READ     : std_logic_vector(3 downto 0);
-
-  signal buf_to_apl_REPLY_DATAREADY: std_logic_vector(3 downto 0);
-  signal buf_to_apl_REPLY_DATA     : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-  signal buf_to_apl_REPLY_PACKET_NUM:std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-  signal buf_to_apl_REPLY_READ     : std_logic_vector(3 downto 0);
-
-  -- for the connection to the multiplexer
-  signal MED_IO_DATAREADY_IN  : std_logic_vector(3 downto 0);
-  signal MED_IO_DATA_IN       : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
-  signal MED_IO_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
-  signal MED_IO_READ_OUT      : std_logic_vector(3 downto 0);
-
-  signal MED_IO_DATAREADY_OUT  : std_logic_vector(7 downto 0);
-  signal MED_IO_DATA_OUT       : std_logic_vector (8*c_DATA_WIDTH-1 downto 0);
-  signal MED_IO_PACKET_NUM_OUT : std_logic_vector (8*c_NUM_WIDTH-1 downto 0);
-  signal MED_IO_READ_IN        : std_logic_vector(7 downto 0);
-
-  signal buf_APL_DATA_IN : std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
-  signal buf_APL_PACKET_NUM_IN : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
-  signal buf_APL_DATAREADY_IN : std_logic_vector(3 downto 0);
-  signal buf_APL_READ_OUT : std_logic_vector(3 downto 0);
-  signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0);
-  signal buf_APL_DTYPE_IN : std_logic_vector(4*4-1 downto 0);
-  signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(4*32-1 downto 0);
-  signal buf_APL_SEND_IN : std_logic_vector(3 downto 0);
-  signal buf_APL_DATA_OUT : std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
-  signal buf_APL_PACKET_NUM_OUT : std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
-  signal buf_APL_DATAREADY_OUT : std_logic_vector(3 downto 0);
-  signal buf_APL_READ_IN : std_logic_vector(3 downto 0);
-  signal buf_APL_TYP_OUT : std_logic_vector(4*3-1 downto 0);
-  signal buf_APL_RUN_OUT : std_logic_vector(3 downto 0);
-  signal buf_APL_SEQNR_OUT : std_logic_vector(4*8-1 downto 0);
-  signal buf_APL_LENGTH_IN : std_logic_vector(16*4-1 downto 0);
-
-  signal MY_ADDRESS : std_logic_vector(15 downto 0);
-
-  signal buf_api_stat_fifo_to_apl, buf_api_stat_fifo_to_int : std_logic_vector (4*32-1 downto 0);
-  signal buf_STAT_GEN : std_logic_vector(32*4-1 downto 0);
-  signal buf_STAT_INIT_BUFFER : std_logic_vector(32*4-1 downto 0);
-  signal buf_CTRL_GEN : std_logic_vector(32*4-1 downto 0);
-  signal buf_STAT_INIT_OBUF_DEBUG      : std_logic_vector (32*4-1 downto 0);
-  signal buf_STAT_REPLY_OBUF_DEBUG     : std_logic_vector (32*4-1 downto 0);
-
-  signal REGIO_REGIO_STAT : std_logic_vector(31 downto 0);
-
-  signal buf_COMMON_STAT_REG_IN: std_logic_vector(std_COMSTATREG*32-1 downto 0);
-  signal buf_REGIO_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-
-  signal buf_IDRAM_DATA_IN       :  std_logic_vector(15 downto 0);
-  signal buf_IDRAM_DATA_OUT      :  std_logic_vector(15 downto 0);
-  signal buf_IDRAM_ADDR_IN       :  std_logic_vector(2 downto 0);
-  signal buf_IDRAM_WR_IN         :  std_logic;
-  signal reset_no_link           :  std_logic;
-  signal ONEWIRE_DATA            :  std_logic_vector(15 downto 0);
-  signal ONEWIRE_ADDR            :  std_logic_vector(2 downto 0);
-  signal ONEWIRE_WRITE           :  std_logic;
-
-  signal buf_COMMON_STAT_REG_STROBE :  std_logic_vector((std_COMSTATREG)-1 downto 0);
-  signal buf_COMMON_CTRL_REG_STROBE :  std_logic_vector((std_COMCTRLREG)-1 downto 0);
-  signal buf_STAT_REG_STROBE        :  std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
-  signal buf_CTRL_REG_STROBE        :  std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-  signal int_trigger_num            : std_logic_vector(15 downto 0);
-
-  signal buf_LVL1_TRG_TYPE_OUT        : std_logic_vector(3 downto 0);
-  signal buf_LVL1_TRG_RECEIVED_OUT    : std_logic;
-  signal buf_LVL1_TRG_NUMBER_OUT      : std_logic_vector(15 downto 0);
-  signal buf_LVL1_TRG_CODE_OUT        : std_logic_vector(7 downto 0);
-  signal buf_LVL1_TRG_INFORMATION_OUT : std_logic_vector(23 downto 0);
-  signal last_LVL1_TRG_RECEIVED_OUT   : std_logic;
-  signal LVL1_TRG_RECEIVED_OUT_rising : std_logic;
-  signal LVL1_TRG_RECEIVED_OUT_falling: std_logic;
-  signal buf_LVL1_ERROR_PATTERN_IN    : std_logic_vector(31 downto 0);
-
-  signal temperature                  : std_logic_vector(11 downto 0);
-  signal got_timing_trigger           : std_logic;
-  signal got_timingless_trigger       : std_logic;
-  signal trigger_number_match         : std_logic;
-  signal buf_TIMER_TICKS_OUT          : std_logic_vector(1 downto 0);
---   signal timing_trigger_missing       : std_logic;
-
-  signal buf_LVL1_VALID_TIMING_TRG_OUT    : std_logic;
-  signal buf_LVL1_VALID_NOTIMING_TRG_OUT  : std_logic;
-  signal buf_LVL1_INVALID_TRG_OUT         : std_logic;
-  signal buf_LVL1_TRG_RELEASE_IN          : std_logic;
-  signal buf_LVL1_TRG_DATA_VALID_OUT      : std_logic;
-
-  signal int_lvl1_delay            : std_logic_vector(15 downto 0);
-  signal int_trg_reset             : std_logic;
-  signal reset_trg_logic           : std_logic;
-  signal stat_lvl1_handler         : std_logic_vector(63 downto 0);
-  signal stat_counters_lvl1_handler: std_logic_vector(79 downto 0);
-  signal trg_invert_i              : std_logic;
-  signal int_multiple_trg          : std_logic;
-  signal int_lvl1_timeout_detected : std_logic;
-  signal int_lvl1_spurious_trg     : std_logic;
-  signal int_lvl1_missing_tmg_trg  : std_logic;
-  signal int_spike_detected        : std_logic;
-  signal int_lvl1_long_trg         : std_logic;
-
-
-  signal last_TRG_TIMING_TRG_RECEIVED_IN : std_logic;
-  signal last_timingtrg_counter_write    : std_logic;
-  signal last_timingtrg_counter_read     : std_logic;
-
-  signal reg_timing_trigger : std_logic;
-  signal trigger_timing_rising : std_logic;
-  signal last_reg_timing_trigger : std_logic;
---   signal timing_trigger_missing_stat : std_logic;
-
-  signal link_error_i            : std_logic;
-  signal link_and_reset_status   : std_logic_vector(31 downto 0);
-
-  signal make_trbnet_reset       : std_logic;
-  signal last_make_trbnet_reset  : std_logic;
-  signal lvl1_tmg_trg_missing_flag : std_logic;
-
-  component edge_to_pulse is
-    port (
-      clock     : in  std_logic;
-      en_clk    : in  std_logic;
-      signal_in : in  std_logic;
-      pulse     : out std_logic);
-  end component;
-
-begin
-
-  process(CLK)
-    begin
-      if rising_edge(CLK) then
-        reset_no_link  <= MED_STAT_OP_IN(14) or RESET;
-        reset_trg_logic <= RESET or buf_REGIO_COMMON_CTRL_REG_OUT(1);
-      end if;
-    end process;
-
-  MED_CTRL_OP_OUT(7 downto 0)  <= (others => '0');
-  MED_CTRL_OP_OUT(8)           <= buf_REGIO_COMMON_CTRL_REG_OUT(64+27);
-  MED_CTRL_OP_OUT(15 downto 9) <= (others => '0');
-  MED_STAT_OP <= MED_STAT_OP_IN;
-
-  --Connections for data channel
-    genbuffers : for i in 0 to 3 generate
-      geniobuf: if USE_CHANNEL(i) = c_YES generate
-        IOBUF: trb_net16_iobuf
-          generic map (
-            IBUF_DEPTH          => IBUF_DEPTH(i),
-            IBUF_SECURE_MODE    => IBUF_SECURE_MODE(i),
-            SBUF_VERSION        => 0,
-            SBUF_VERSION_OBUF   => 6,
-            OBUF_DATA_COUNT_WIDTH => std_DATA_COUNT_WIDTH,
-            USE_ACKNOWLEDGE     => cfg_USE_ACKNOWLEDGE(i),
-            USE_CHECKSUM        => USE_CHECKSUM(i),
-            USE_VENDOR_CORES    => c_YES,
-            INIT_CAN_SEND_DATA  => INIT_CAN_SEND_DATA(i),
-            REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA(i),
-            REPLY_CAN_RECEIVE_DATA => REPLY_CAN_RECEIVE_DATA(i)
-            )
-          port map (
-            --  Misc
-            CLK     => CLK ,
-            RESET   => reset_no_link,
-            CLK_EN  => CLK_EN,
-            --  Media direction port
-            MED_INIT_DATAREADY_OUT  => MED_IO_DATAREADY_OUT(i*2),
-            MED_INIT_DATA_OUT       => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
-            MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
-            MED_INIT_READ_IN        => MED_IO_READ_IN(i*2),
-
-            MED_DATAREADY_IN   => MED_IO_DATAREADY_IN(i),
-            MED_DATA_IN        => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-            MED_PACKET_NUM_IN  => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-            MED_READ_OUT       => MED_IO_READ_OUT(i),
-            MED_ERROR_IN       => MED_STAT_OP_IN(2 downto 0),
-
-            MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
-            MED_REPLY_DATA_OUT      => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
-            MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
-            MED_REPLY_READ_IN       => MED_IO_READ_IN(i*2+1),
-
-            -- Internal direction port
-
-            INT_INIT_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i),
-            INT_INIT_DATA_OUT      => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-            INT_INIT_PACKET_NUM_OUT=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-            INT_INIT_READ_IN       => buf_to_apl_INIT_READ(i),
-
-            INT_INIT_DATAREADY_IN  => apl_to_buf_INIT_DATAREADY(i),
-            INT_INIT_DATA_IN       => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-            INT_INIT_PACKET_NUM_IN => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-            INT_INIT_READ_OUT      => apl_to_buf_INIT_READ(i),
-
-            INT_REPLY_DATAREADY_OUT => buf_to_apl_REPLY_DATAREADY(i),
-            INT_REPLY_DATA_OUT      => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-            INT_REPLY_PACKET_NUM_OUT=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-            INT_REPLY_READ_IN       => buf_to_apl_REPLY_READ(i),
-
-            INT_REPLY_DATAREADY_IN  => apl_to_buf_REPLY_DATAREADY(i),
-            INT_REPLY_DATA_IN       => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-            INT_REPLY_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-            INT_REPLY_READ_OUT      => apl_to_buf_REPLY_READ(i),
-
-            -- Status and control port
-            STAT_GEN               => buf_STAT_GEN(32*(i+1)-1 downto i*32),
-            STAT_IBUF_BUFFER       => buf_STAT_INIT_BUFFER(32*(i+1)-1 downto i*32),
-            CTRL_GEN               => buf_CTRL_GEN(32*(i+1)-1 downto i*32),
-            STAT_INIT_OBUF_DEBUG   => buf_STAT_INIT_OBUF_DEBUG(32*(i+1)-1 downto i*32),
-            STAT_REPLY_OBUF_DEBUG  => buf_STAT_REPLY_OBUF_DEBUG(32*(i+1)-1 downto i*32),
-            TIMER_TICKS_IN         => buf_TIMER_TICKS_OUT,
-            CTRL_STAT              => x"0000"
-            );
-
-      gen_api : if i /= c_TRG_LVL1_CHANNEL generate
-        constant j : integer := i;
-      begin
-        DAT_PASSIVE_API: trb_net16_api_base
-          generic map (
-            API_TYPE          => c_API_PASSIVE,
-            FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH(i),
-            FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH(i),
-            FORCE_REPLY       => cfg_FORCE_REPLY(i),
-            SBUF_VERSION      => 0,
-            USE_VENDOR_CORES   => c_YES,
-            SECURE_MODE_TO_APL => API_SECURE_MODE_TO_APL(i),
-            SECURE_MODE_TO_INT => API_SECURE_MODE_TO_INT(i),
-            APL_WRITE_ALL_WORDS=> APL_WRITE_ALL_WORDS(i),
-            ADDRESS_MASK       => ADDRESS_MASK,
-            BROADCAST_BITMASK  => BROADCAST_BITMASK,
-            BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
-            )
-          port map (
-            --  Misc
-            CLK    => CLK,
-            RESET  => RESET,
-            CLK_EN => CLK_EN,
-            -- APL Transmitter port
-            APL_DATA_IN           => buf_APL_DATA_IN((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
-            APL_PACKET_NUM_IN     => buf_APL_PACKET_NUM_IN((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
-            APL_DATAREADY_IN      => buf_APL_DATAREADY_IN(j),
-            APL_READ_OUT          => buf_APL_READ_OUT(j),
-            APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN(j),
-            APL_DTYPE_IN          => buf_APL_DTYPE_IN((j+1)*4-1 downto j*4),
-            APL_ERROR_PATTERN_IN  => buf_APL_ERROR_PATTERN_IN((j+1)*32-1 downto j*32),
-            APL_SEND_IN           => buf_APL_SEND_IN(j),
-            APL_TARGET_ADDRESS_IN => (others => '0'),
-            -- Receiver port
-            APL_DATA_OUT      => buf_APL_DATA_OUT((j+1)*c_DATA_WIDTH-1 downto j*c_DATA_WIDTH),
-            APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT((j+1)*c_NUM_WIDTH-1 downto j*c_NUM_WIDTH),
-            APL_TYP_OUT       => buf_APL_TYP_OUT((j+1)*3-1 downto j*3),
-            APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT(j),
-            APL_READ_IN       => buf_APL_READ_IN(j),
-            -- APL Control port
-            APL_RUN_OUT       => buf_APL_RUN_OUT(j),
-            APL_MY_ADDRESS_IN => MY_ADDRESS,
-            APL_SEQNR_OUT     => buf_APL_SEQNR_OUT((j+1)*8-1 downto j*8),
-            APL_LENGTH_IN     => buf_APL_LENGTH_IN((j+1)*16-1 downto j*16),
-            -- Internal direction port
-            INT_MASTER_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
-            INT_MASTER_DATA_OUT      => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-            INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-            INT_MASTER_READ_IN       => apl_to_buf_REPLY_READ(i),
-            INT_MASTER_DATAREADY_IN  => buf_to_apl_REPLY_DATAREADY(i),
-            INT_MASTER_DATA_IN       => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-            INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-            INT_MASTER_READ_OUT      => buf_to_apl_REPLY_READ(i),
-            INT_SLAVE_DATAREADY_OUT  => apl_to_buf_INIT_DATAREADY(i),
-            INT_SLAVE_DATA_OUT       => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-            INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-            INT_SLAVE_READ_IN        => apl_to_buf_INIT_READ(i),
-            INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
-            INT_SLAVE_DATA_IN      => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-            INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-            INT_SLAVE_READ_OUT     => buf_to_apl_INIT_READ(i),
-            -- Status and control port
-            CTRL_SEQNR_RESET =>  buf_REGIO_COMMON_CTRL_REG_OUT(10),
-            STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
-            STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
-            );
-        end generate;
-
-        gentrgapi : if i = c_TRG_LVL1_CHANNEL generate
-          buf_APL_READ_OUT(i) <= '0';
-          buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
-          buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
-          buf_APL_DATAREADY_OUT(i) <= '0';
-          buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8) <= (others => '0');
-          buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
-          buf_APL_DTYPE_IN((i+1)*4-1 downto i*4) <= (others => '0');
-          buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');
-          buf_APL_RUN_OUT(i) <= '0';
-          buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0');
-          buf_APL_READ_IN(i) <= '0';
-          buf_APL_SHORT_TRANSFER_IN(i) <= '0';
-          buf_APL_TYP_OUT((i+1)*3-1 downto i*3) <= (others => '0');
-          buf_APL_DATAREADY_IN(i) <= '0';
-          buf_APL_SEND_IN(i) <= '0';
-          buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
-
-          apl_to_buf_INIT_DATAREADY(i) <= '0';
-          apl_to_buf_INIT_DATA((i+1)*16-1 downto i*16) <= (others => '0');
-          apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
-          apl_to_buf_INIT_READ(i) <= '0';
-
-          buf_to_apl_REPLY_READ(i) <= '1';
-          buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
-          buf_to_apl_REPLY_DATAREADY(i) <= '0';
-          buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
-
-          buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) <= (others => '0');
-          buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32) <= (others => '0');
-
-
-          the_trigger_apl : trb_net16_trigger
-            generic map(
-              USE_TRG_PORT => c_YES,
-              SECURE_MODE  => std_TERM_SECURE_MODE
-              )
-            port map(
-              --  Misc
-              CLK    => CLK,
-              RESET  => RESET,
-              CLK_EN => CLK_EN,
-              INT_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i),
-              INT_DATA_OUT      => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-              INT_PACKET_NUM_OUT=> apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-              INT_READ_IN       => apl_to_buf_REPLY_READ(i),
-              INT_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i),
-              INT_DATA_IN      => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-              INT_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-              INT_READ_OUT     => buf_to_apl_INIT_READ(i),
-              TRG_RECEIVED_OUT      => buf_LVL1_TRG_RECEIVED_OUT,
-              TRG_TYPE_OUT          => buf_LVL1_TRG_TYPE_OUT,
-              TRG_NUMBER_OUT        => buf_LVL1_TRG_NUMBER_OUT,
-              TRG_CODE_OUT          => buf_LVL1_TRG_CODE_OUT,
-              TRG_INFORMATION_OUT   => buf_LVL1_TRG_INFORMATION_OUT,
-              TRG_RELEASE_IN        => buf_LVL1_TRG_RELEASE_IN,
-              TRG_ERROR_PATTERN_IN  => buf_LVL1_ERROR_PATTERN_IN
-              );
-        end generate;
-
-        gen_ipu_apl : if i = c_DATA_CHANNEL generate
-          the_ipudata_apl : trb_net16_ipudata
-            port map(
-              CLK    => CLK,
-              RESET  => RESET,
-              CLK_EN => CLK_EN,
-              API_DATA_OUT           => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-              API_PACKET_NUM_OUT     => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-              API_DATAREADY_OUT      => buf_APL_DATAREADY_IN(i),
-              API_READ_IN            => buf_APL_READ_OUT(i),
-              API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(i),
-              API_DTYPE_OUT          => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),
-              API_ERROR_PATTERN_OUT  => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),
-              API_SEND_OUT           => buf_APL_SEND_IN(i),
-              API_DATA_IN            => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-              API_PACKET_NUM_IN      => buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-              API_TYP_IN             => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),
-              API_DATAREADY_IN       => buf_APL_DATAREADY_OUT(i),
-              API_READ_OUT           => buf_APL_READ_IN(i),
-              API_RUN_IN             => buf_APL_RUN_OUT(i),
-              API_SEQNR_IN           => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),
-              API_LENGTH_OUT         => buf_APL_LENGTH_IN((i+1)*16-1 downto i*16),
-              MY_ADDRESS_IN          => MY_ADDRESS,
-              --Information received with request
-              IPU_NUMBER_OUT         => IPU_NUMBER_OUT,
-              IPU_READOUT_TYPE_OUT   => IPU_READOUT_TYPE_OUT,
-              IPU_INFORMATION_OUT    => IPU_INFORMATION_OUT,
-              --start strobe
-              IPU_START_READOUT_OUT  => IPU_START_READOUT_OUT,
-              --detector data, equipped with DHDR
-              IPU_DATA_IN            => IPU_DATA_IN,
-              IPU_DATAREADY_IN       => IPU_DATAREADY_IN,
-              --no more data, end transfer, send TRM
-              IPU_READOUT_FINISHED_IN=> IPU_READOUT_FINISHED_IN,
-              --will be low every second cycle due to 32bit -> 16bit conversion
-              IPU_READ_OUT           => IPU_READ_OUT,
-              IPU_LENGTH_IN          => IPU_LENGTH_IN,
-              IPU_ERROR_PATTERN_IN   => IPU_ERROR_PATTERN_IN,
-              STAT_DEBUG             => STAT_DEBUG_IPU
-              );
-        end generate;
-
-        gen_regio : if i = c_SLOW_CTRL_CHANNEL generate
-          buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');
-
-          regIO : trb_net16_regIO
-            generic map(
-              NUM_STAT_REGS      => REGIO_NUM_STAT_REGS,
-              NUM_CTRL_REGS      => REGIO_NUM_CTRL_REGS,
-              --standard values for output registers
-              INIT_CTRL_REGS     => REGIO_INIT_CTRL_REGS,
-              --set to 0 for unused ctrl registers to save resources
-              USED_CTRL_REGS     => REGIO_USED_CTRL_REGS,
-              --set to 0 for each unused bit in a register
-              USED_CTRL_BITMASK  => REGIO_USED_CTRL_BITMASK,
-              --no data / address out?
-              USE_DAT_PORT       => REGIO_USE_DAT_PORT,
-              INIT_ADDRESS       => REGIO_INIT_ADDRESS,
-              INIT_UNIQUE_ID     => REGIO_INIT_UNIQUE_ID,
-              INIT_ENDPOINT_ID   => REGIO_INIT_ENDPOINT_ID,
-              COMPILE_TIME       => REGIO_COMPILE_TIME,
-              COMPILE_VERSION    => REGIO_COMPILE_VERSION,
-              HARDWARE_VERSION   => REGIO_HARDWARE_VERSION,
-              CLOCK_FREQ         => CLOCK_FREQUENCY
-              )
-            port map(
-            --  Misc
-              CLK      => CLK,
-              RESET    => RESET,
-              CLK_EN   => CLK_EN,
-            -- Port to API
-              API_DATA_OUT           => buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-              API_PACKET_NUM_OUT     => buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-              API_DATAREADY_OUT      => buf_APL_DATAREADY_IN(i),
-              API_READ_IN            => buf_APL_READ_OUT(i),
-              API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN(i),
-              API_DTYPE_OUT          => buf_APL_DTYPE_IN((i+1)*4-1 downto i*4),
-              API_ERROR_PATTERN_OUT  => buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32),
-              API_SEND_OUT           => buf_APL_SEND_IN(3),
-              API_DATA_IN            => buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-              API_PACKET_NUM_IN      => buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-              API_TYP_IN             => buf_APL_TYP_OUT((i+1)*3-1 downto i*3),
-              API_DATAREADY_IN       => buf_APL_DATAREADY_OUT(i),
-              API_READ_OUT           => buf_APL_READ_IN(i),
-              API_RUN_IN             => buf_APL_RUN_OUT(i),
-              API_SEQNR_IN           => buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8),
-            --Port to write Unique ID
-              IDRAM_DATA_IN          => buf_IDRAM_DATA_IN,
-              IDRAM_DATA_OUT         => buf_IDRAM_DATA_OUT,
-              IDRAM_ADDR_IN          => buf_IDRAM_ADDR_IN,
-              IDRAM_WR_IN            => buf_IDRAM_WR_IN,
-              MY_ADDRESS_OUT         => MY_ADDRESS,
-              TRIGGER_MONITOR        => buf_LVL1_VALID_TIMING_TRG_OUT,
-              GLOBAL_TIME            => GLOBAL_TIME_OUT,
-              LOCAL_TIME             => LOCAL_TIME_OUT,
-              TIME_SINCE_LAST_TRG    => TIME_SINCE_LAST_TRG_OUT,
-              TIMER_US_TICK          => buf_TIMER_TICKS_OUT(0),
-              TIMER_MS_TICK          => buf_TIMER_TICKS_OUT(1),
-            --Common Register in / out
-              COMMON_STAT_REG_IN     => buf_COMMON_STAT_REG_IN,
-              COMMON_CTRL_REG_OUT    => buf_REGIO_COMMON_CTRL_REG_OUT,
-            --Custom Register in / out
-              REGISTERS_IN           => REGIO_REGISTERS_IN,
-              REGISTERS_OUT          => REGIO_REGISTERS_OUT,
-              COMMON_STAT_REG_STROBE => buf_COMMON_STAT_REG_STROBE,
-              COMMON_CTRL_REG_STROBE => buf_COMMON_CTRL_REG_STROBE,
-              STAT_REG_STROBE        => buf_STAT_REG_STROBE,
-              CTRL_REG_STROBE        => buf_CTRL_REG_STROBE,
-            --following ports only used when no internal register is accessed
-              DAT_ADDR_OUT           => REGIO_ADDR_OUT,
-              DAT_READ_ENABLE_OUT    => REGIO_READ_ENABLE_OUT,
-              DAT_WRITE_ENABLE_OUT   => REGIO_WRITE_ENABLE_OUT,
-              DAT_DATA_OUT           => REGIO_DATA_OUT,
-              DAT_DATA_IN            => REGIO_DATA_IN,
-              DAT_DATAREADY_IN       => REGIO_DATAREADY_IN,
-              DAT_NO_MORE_DATA_IN    => REGIO_NO_MORE_DATA_IN,
-              DAT_UNKNOWN_ADDR_IN    => REGIO_UNKNOWN_ADDR_IN,
-              DAT_TIMEOUT_OUT        => REGIO_TIMEOUT_OUT,
-              DAT_WRITE_ACK_IN       => REGIO_WRITE_ACK_IN,
-              STAT                   => REGIO_REGIO_STAT,
-              STAT_ADDR_DEBUG        => STAT_ADDR_DEBUG
-              );
-          gen_no1wire : if REGIO_USE_1WIRE_INTERFACE = c_NO generate
-            ONEWIRE_DATA  <= REGIO_IDRAM_DATA_IN;
-            ONEWIRE_ADDR  <= REGIO_IDRAM_ADDR_IN;
-            ONEWIRE_WRITE <= REGIO_IDRAM_WR_IN;
-            REGIO_IDRAM_DATA_OUT <= buf_IDRAM_DATA_OUT;
-            REGIO_ONEWIRE_INOUT <= '0';
-            REGIO_ONEWIRE_MONITOR_OUT <= '0';
-
-          end generate;
-          gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate
-
-
-            REGIO_IDRAM_DATA_OUT <= (others => '0');
-
-            onewire_interface : trb_net_onewire
-              generic map(
-                USE_TEMPERATURE_READOUT => c_YES,
-                CLK_PERIOD => 10
-                )
-              port map(
-                CLK      => CLK,
-                RESET    => RESET,
-                --connection to 1-wire interface
-                ONEWIRE  => REGIO_ONEWIRE_INOUT,
-                MONITOR_OUT => REGIO_ONEWIRE_MONITOR_OUT,
-                --connection to id ram, according to memory map in TrbNetRegIO
-                DATA_OUT => ONEWIRE_DATA,
-                ADDR_OUT => ONEWIRE_ADDR,
-                WRITE_OUT=> ONEWIRE_WRITE,
-                TEMP_OUT => temperature,
-                STAT     => STAT_ONEWIRE
-                );
-          end generate;
-          gen_1wire_monitor : if REGIO_USE_1WIRE_INTERFACE = c_MONITOR generate
-            REGIO_IDRAM_DATA_OUT <= (others => '0');
-            REGIO_ONEWIRE_MONITOR_OUT <= '0';
-
-            onewire_interface : trb_net_onewire_listener
-              port map(
-                CLK      => CLK,
-                CLK_EN   => CLK_EN,
-                RESET    => RESET,
-                --connection to 1-wire interface
-                MONITOR_IN => REGIO_ONEWIRE_MONITOR_IN,
-                --connection to id ram, according to memory map in TrbNetRegIO
-                DATA_OUT => ONEWIRE_DATA,
-                ADDR_OUT => ONEWIRE_ADDR,
-                WRITE_OUT=> ONEWIRE_WRITE,
-                TEMP_OUT => temperature,
-                STAT     => STAT_ONEWIRE
-                );
-          end generate;
-        end generate;
-      end generate;
-      gentermbuf: if USE_CHANNEL(i) = c_NO generate
-        buf_APL_DATA_OUT((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
-        buf_APL_PACKET_NUM_OUT((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
-        buf_APL_READ_OUT(i) <= '0';
-        buf_APL_DATAREADY_OUT(i) <= '0';
-        buf_APL_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
-        buf_APL_SEQNR_OUT((i+1)*8-1 downto i*8) <= (others => '0');
-        buf_APL_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
-        buf_APL_DTYPE_IN((i+1)*4-1 downto i*4) <= (others => '0');
-        buf_APL_LENGTH_IN((i+1)*16-1 downto i*16) <= (others => '1');
-        buf_APL_RUN_OUT(i) <= '0';
-        buf_APL_ERROR_PATTERN_IN((i+1)*32-1 downto i*32) <= (others => '0');
-        buf_APL_READ_IN(i) <= '0';
-        buf_APL_SHORT_TRANSFER_IN(i) <= '0';
-        buf_APL_TYP_OUT((i+1)*3-1 downto i*3) <= (others => '0');
-        buf_APL_DATAREADY_IN(i) <= '0';
-        buf_APL_SEND_IN(i) <= '0';
-
-        apl_to_buf_INIT_READ(i) <= '0';
-        apl_to_buf_INIT_DATAREADY(i) <= '0';
-        apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
-        apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
-        apl_to_buf_REPLY_DATAREADY(i) <= '0';
-        apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
-        apl_to_buf_REPLY_READ(i) <= '0';
-        apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
-
-        buf_to_apl_INIT_READ(i) <= '0';
-        buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
-        buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
-        buf_to_apl_INIT_DATAREADY(i) <= '0';
-        buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH) <= (others => '0');
-        buf_to_apl_REPLY_DATAREADY(i) <= '0';
-        buf_to_apl_REPLY_READ(i) <= '0';
-        buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
-
-        buf_STAT_INIT_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');
-        buf_STAT_GEN((i+1)*32-1 downto i*32) <= (others => '0');
-        buf_STAT_REPLY_OBUF_DEBUG((i+1)*32-1 downto i*32) <= (others => '0');
-        buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32) <= (others => '0');
-        buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32) <= (others => '0');
-        buf_STAT_INIT_BUFFER((i+1)*32-1 downto i*32) <= (others => '0');
-
-        termbuf: trb_net16_term_buf
-          port map(
-            CLK    => CLK,
-            RESET  => reset_no_link,
-            CLK_EN => CLK_EN,
-            MED_DATAREADY_IN       => MED_IO_DATAREADY_IN(i),
-            MED_DATA_IN            => MED_IO_DATA_IN((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH),
-            MED_PACKET_NUM_IN      => MED_IO_PACKET_NUM_IN((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH),
-            MED_READ_OUT           => MED_IO_READ_OUT(i),
-
-            MED_INIT_DATAREADY_OUT  => MED_IO_DATAREADY_OUT(i*2),
-            MED_INIT_DATA_OUT       => MED_IO_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH),
-            MED_INIT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_OUT((i*2+1)*c_NUM_WIDTH-1 downto i*2*c_NUM_WIDTH),
-            MED_INIT_READ_IN        => MED_IO_READ_IN(i*2),
-            MED_REPLY_DATAREADY_OUT => MED_IO_DATAREADY_OUT(i*2+1),
-            MED_REPLY_DATA_OUT      => MED_IO_DATA_OUT((i*2+2)*c_DATA_WIDTH-1 downto (i*2+1)*c_DATA_WIDTH),
-            MED_REPLY_PACKET_NUM_OUT=> MED_IO_PACKET_NUM_OUT((i*2+2)*c_NUM_WIDTH-1 downto (i*2+1)*c_NUM_WIDTH),
-            MED_REPLY_READ_IN       => MED_IO_READ_IN(i*2+1)
-            );
-      end generate;
-    end generate;
-
-
-  MPLEX: trb_net16_io_multiplexer
-    generic map(
-      USE_INPUT_SBUF => (1,1,1,1,0,0,1,1)
-      )
-    port map (
-      CLK      => CLK,
-      RESET    => reset_no_link,
-      CLK_EN   => CLK_EN,
-      MED_DATAREADY_IN   => MED_DATAREADY_IN,
-      MED_DATA_IN        => MED_DATA_IN,
-      MED_PACKET_NUM_IN  => MED_PACKET_NUM_IN,
-      MED_READ_OUT       => MED_READ_OUT,
-      MED_DATAREADY_OUT  => MED_DATAREADY_OUT,
-      MED_DATA_OUT       => MED_DATA_OUT,
-      MED_PACKET_NUM_OUT => MED_PACKET_NUM_OUT,
-      MED_READ_IN        => MED_READ_IN,
-      INT_DATAREADY_OUT  => MED_IO_DATAREADY_IN,
-      INT_DATA_OUT       => MED_IO_DATA_IN,
-      INT_PACKET_NUM_OUT => MED_IO_PACKET_NUM_IN,
-      INT_READ_IN        => MED_IO_READ_OUT,
-      INT_DATAREADY_IN   => MED_IO_DATAREADY_OUT,
-      INT_DATA_IN        => MED_IO_DATA_OUT,
-      INT_PACKET_NUM_IN  => MED_IO_PACKET_NUM_OUT,
-      INT_READ_OUT       => MED_IO_READ_IN,
-      STAT               => open,
-      CTRL               => CTRL_MPLEX
-      );
-
--------------------------------------------------
--- Include variable Endpoint ID
--------------------------------------------------
-  gen_var_endpoint_id : if REGIO_USE_VAR_ENDPOINT_ID = c_YES generate
-    buf_IDRAM_DATA_IN  <= REGIO_VAR_ENDPOINT_ID when RESET = '1' else ONEWIRE_DATA;
-    buf_IDRAM_ADDR_IN  <= "100"                 when RESET = '1' else ONEWIRE_ADDR;
-    buf_IDRAM_WR_IN    <= '1'                   when RESET = '1' else ONEWIRE_WRITE;
-  end generate;
-
-  gen_no_var_endpoint_id : if REGIO_USE_VAR_ENDPOINT_ID = c_NO generate
-    buf_IDRAM_DATA_IN  <= ONEWIRE_DATA;
-    buf_IDRAM_ADDR_IN  <= ONEWIRE_ADDR;
-    buf_IDRAM_WR_IN    <= ONEWIRE_WRITE;
-  end generate;
-
-
-
--------------------------------------------------
--- Common Status Register
--------------------------------------------------
-  proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, trigger_number_match, temperature, int_trigger_num,
-                                      link_error_i, link_and_reset_status, stat_lvl1_handler)
-    begin
-      buf_COMMON_STAT_REG_IN               <= REGIO_COMMON_STAT_REG_IN;
-      buf_COMMON_STAT_REG_IN(4)            <= stat_lvl1_handler(12);
-      buf_COMMON_STAT_REG_IN(8)            <= lvl1_tmg_trg_missing_flag;
-      buf_COMMON_STAT_REG_IN(13)           <= stat_lvl1_handler(7);
-      buf_COMMON_STAT_REG_IN(15)           <= link_error_i;
-      if REGIO_USE_1WIRE_INTERFACE = c_YES then
-        buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature;
-      end if;
-      buf_COMMON_STAT_REG_IN(47 downto 32)   <= int_trigger_num;
-      buf_COMMON_STAT_REG_IN(127 downto 64)  <= stat_lvl1_handler;
-      buf_COMMON_STAT_REG_IN(159 downto 128) <= link_and_reset_status(31 downto 0);
-      buf_COMMON_STAT_REG_IN(175 downto 160) <= buf_LVL1_TRG_INFORMATION_OUT(15 downto 0);
-      buf_COMMON_STAT_REG_IN(179 downto 176) <= buf_LVL1_TRG_TYPE_OUT;
-      buf_COMMON_STAT_REG_IN(183 downto 180) <= buf_LVL1_TRG_NUMBER_OUT(3 downto 0);
-      buf_COMMON_STAT_REG_IN(191 downto 184) <= buf_LVL1_TRG_CODE_OUT;
-      buf_COMMON_STAT_REG_IN(271 downto 192) <= stat_counters_lvl1_handler;
-      buf_COMMON_STAT_REG_IN(287 downto 272) <= (others => '0');
-    end process;
-
-
-
-  REG_LINK_ERROR : process(CLK)
-    begin
-      if rising_edge(CLK) then
-        if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then
-          link_error_i <= '0';
-        elsif MED_STAT_OP_IN(15) = '0' and MED_STAT_OP_IN(13) = '0' and MED_STAT_OP_IN(7 downto 4) = "0111" then
-          link_error_i <= '1';
-        end if;
-
-        if buf_REGIO_COMMON_CTRL_REG_OUT(4) = '1' then
-          lvl1_tmg_trg_missing_flag <= '0';
-        elsif int_lvl1_missing_tmg_trg = '1' or int_lvl1_spurious_trg = '1' or int_spike_detected = '1' then
-          lvl1_tmg_trg_missing_flag <= '1';
-        end if;
-
---         if LVL1_TRG_RECEIVED_OUT_falling = '1' then
---           timing_trigger_missing_stat <= timing_trigger_missing;
---         end if;
-
-        if make_trbnet_reset = '1' then
-          link_and_reset_status(3 downto 0) <= link_and_reset_status(3 downto 0) + '1';
-        end if;
-
-        if MED_STAT_OP_IN(12) = '1' then
-          link_and_reset_status(31 downto 24) <= link_and_reset_status(31 downto 24) + '1';
-        end if;
-
-        if MED_STAT_OP_IN(8) = '1' then
-          link_and_reset_status(23 downto 16) <= link_and_reset_status(23 downto 16) + '1';
-        end if;
-
-        if buf_REGIO_COMMON_CTRL_REG_OUT(5) = '1' then
-          link_and_reset_status <= (others => '0');
-        end if;
-
-      end if;
-    end process;
-
-  PROC_FIND_TRBNET_RESET : process(CLK)
-    begin
-      if rising_edge(CLK) then
-        last_make_trbnet_reset <= MED_STAT_OP_IN(13);
-        make_trbnet_reset      <= MED_STAT_OP_IN(13) and not last_make_trbnet_reset;
-      end if;
-    end process;
-
--------------------------------------------------
--- Check LVL1 trigger number
--------------------------------------------------
-
-  THE_LVL1_HANDLER : handler_lvl1
-    generic map (
-      TIMING_TRIGGER_RAW           => TIMING_TRIGGER_RAW
-    )
-    port map(
-      RESET                        => reset_trg_logic,
-      RESET_FLAGS_IN               => buf_REGIO_COMMON_CTRL_REG_OUT(4),
-      RESET_STATS_IN               => buf_REGIO_COMMON_CTRL_REG_OUT(5),
-      CLOCK                        => CLK,
-      --Timing Trigger
-      LVL1_TIMING_TRG_IN           => TRG_TIMING_TRG_RECEIVED_IN,
-      LVL1_PSEUDO_TMG_TRG_IN       => buf_REGIO_COMMON_CTRL_REG_OUT(16),
-      --LVL1_handler connection
-      LVL1_TRG_RECEIVED_IN         => buf_LVL1_TRG_RECEIVED_OUT,
-      LVL1_TRG_TYPE_IN             => buf_LVL1_TRG_TYPE_OUT,
-      LVL1_TRG_NUMBER_IN           => buf_LVL1_TRG_NUMBER_OUT,
-      LVL1_TRG_CODE_IN             => buf_LVL1_TRG_CODE_OUT,
-      LVL1_TRG_INFORMATION_IN      => buf_LVL1_TRG_INFORMATION_OUT,
-      LVL1_ERROR_PATTERN_OUT       => buf_LVL1_ERROR_PATTERN_IN,
-      LVL1_TRG_RELEASE_OUT         => buf_LVL1_TRG_RELEASE_IN,
-
-      LVL1_INT_TRG_NUMBER_OUT      => int_trigger_num,
-      LVL1_INT_TRG_LOAD_IN         => buf_COMMON_CTRL_REG_STROBE(1),
-      LVL1_INT_TRG_COUNTER_IN      => buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32),
-
-      --FEE logic / Data Handler
-      LVL1_TRG_DATA_VALID_OUT      => buf_LVL1_TRG_DATA_VALID_OUT,
-      LVL1_VALID_TIMING_TRG_OUT    => buf_LVL1_VALID_TIMING_TRG_OUT,
-      LVL1_VALID_NOTIMING_TRG_OUT  => buf_LVL1_VALID_NOTIMING_TRG_OUT,
-      LVL1_INVALID_TRG_OUT         => buf_LVL1_INVALID_TRG_OUT,
-      LVL1_MULTIPLE_TRG_OUT        => int_multiple_trg,
-      LVL1_DELAY_OUT               => int_lvl1_delay,
-      LVL1_TIMEOUT_DETECTED_OUT    => int_lvl1_timeout_detected,
-      LVL1_SPURIOUS_TRG_OUT        => int_lvl1_spurious_trg,
-      LVL1_MISSING_TMG_TRG_OUT     => int_lvl1_missing_tmg_trg,
-      LVL1_LONG_TRG_OUT            => int_lvl1_long_trg,
-      SPIKE_DETECTED_OUT           => int_spike_detected,
-
-      LVL1_ERROR_PATTERN_IN        => LVL1_ERROR_PATTERN_IN,
-      LVL1_TRG_RELEASE_IN          => LVL1_TRG_RELEASE_IN,
-
-      --Stat/Control
-      STATUS_OUT                   => stat_lvl1_handler,
-      TRG_ENABLE_IN                => buf_REGIO_COMMON_CTRL_REG_OUT(95),
-      TRG_INVERT_IN                => buf_REGIO_COMMON_CTRL_REG_OUT(93),
-      COUNTERS_STATUS_OUT          => stat_counters_lvl1_handler,
-      --Debug
-      DEBUG_OUT                    => DEBUG_LVL1_HANDLER_OUT
-    );
-
-  TRG_SPIKE_DETECTED_OUT   <= int_spike_detected;
-  TRG_SPURIOUS_TRG_OUT     <= int_lvl1_spurious_trg;
-  TRG_TIMEOUT_DETECTED_OUT <= int_lvl1_timeout_detected;
-  TRG_MULTIPLE_TRG_OUT     <= int_multiple_trg;
-  TRG_MISSING_TMG_TRG_OUT  <= int_lvl1_missing_tmg_trg;
-  TRG_LONG_TRG_OUT         <= int_lvl1_long_trg;
-
-  
-
---   THE_TRG_SYNC : signal_sync
---      generic map(
---        DEPTH => 2,
---        WIDTH => 1
---        )
---      port map(
---        RESET    => RESET,
---        D_IN(0)  => TRG_TIMING_TRG_RECEIVED_IN,
---        CLK0     => CLK,
---        CLK1     => CLK,
---        D_OUT(0) => reg_timing_trigger
---        );
---
---
---
---
---   proc_internal_trigger_number : process(CLK)
---     begin
---       if rising_edge(CLK) then
---         if reset_no_link = '1' then
---           int_trigger_num <= (others => '0');
---         elsif LVL1_TRG_RECEIVED_OUT_falling = '1' then
---           int_trigger_num <= int_trigger_num + 1;
---         elsif buf_COMMON_CTRL_REG_STROBE(1) = '1' then
---           int_trigger_num <= buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32);
---         end if;
---       end if;
---     end process;
---
---   proc_check_trigger_number : process(CLK)
---     begin
---       if rising_edge(CLK) then
---         if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then
---           trigger_number_match <= '1';
---         elsif LVL1_TRG_RECEIVED_OUT_rising = '1' then
---           if int_trigger_num = buf_LVL1_TRG_NUMBER_OUT  then
---             trigger_number_match <= '1';
---           else
---             trigger_number_match <= '0';
---           end if;
---         end if;
---       end if;
---     end process;
---
---
---   proc_detect_trigger_receive : process(CLK)
---     begin
---       if rising_edge(CLK) then
---         last_reg_timing_trigger <= reg_timing_trigger;
---         trigger_timing_rising   <= reg_timing_trigger and not last_reg_timing_trigger; -- and buf_REGIO_COMMON_CTRL_REG_OUT(95);
---
---         last_LVL1_TRG_RECEIVED_OUT <= buf_LVL1_TRG_RECEIVED_OUT;
---         LVL1_TRG_RECEIVED_OUT_rising <= buf_LVL1_TRG_RECEIVED_OUT and not last_LVL1_TRG_RECEIVED_OUT;
---         LVL1_TRG_RECEIVED_OUT_falling <= not buf_LVL1_TRG_RECEIVED_OUT and last_LVL1_TRG_RECEIVED_OUT;
---
---         if reset_no_link = '1' or LVL1_TRG_RECEIVED_OUT_falling = '1' then
---           got_timing_trigger <= '0';
---           got_timingless_trigger <= '0';
---           timing_trigger_missing <= '0';
---         elsif trigger_timing_rising = '1' then --TRG_TIMING_TRG_RECEIVED_IN
---           got_timing_trigger <= '1';
---         elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') then
---           got_timingless_trigger <= '1';
---         elsif (LVL1_TRG_RECEIVED_OUT_rising = '1' and not (buf_LVL1_TRG_TYPE_OUT >= x"8" and buf_LVL1_TRG_INFORMATION_OUT(7) = '1') and got_timing_trigger = '0') then
---           timing_trigger_missing <= '1';
---         end if;
---       end if;
---     end process;
---
---
---   proc_gen_lvl1_error_pattern : process(LVL1_ERROR_PATTERN_IN, trigger_number_match, got_timing_trigger,got_timingless_trigger )
---     begin
---       buf_LVL1_ERROR_PATTERN_IN     <= LVL1_ERROR_PATTERN_IN;
---       buf_LVL1_ERROR_PATTERN_IN(16) <= not trigger_number_match or LVL1_ERROR_PATTERN_IN(16);
---       buf_LVL1_ERROR_PATTERN_IN(17) <= (not got_timing_trigger and not got_timingless_trigger) or LVL1_ERROR_PATTERN_IN(17);
---     end process;
---
---   buf_LVL1_VALID_TIMING_TRG_OUT    <= trigger_timing_rising; --TRG_TIMING_TRG_RECEIVED_IN;
---   buf_LVL1_VALID_NOTIMING_TRG_OUT  <= LVL1_TRG_RECEIVED_OUT_rising and not got_timing_trigger
---                                         and buf_LVL1_TRG_TYPE_OUT(3) and buf_LVL1_TRG_INFORMATION_OUT(7);
---   buf_LVL1_INVALID_TRG_OUT         <= '0';
-
---   proc_count_timing_trg : process(CLK)
---     begin
---       if rising_edge(CLK) then
---         last_TRG_TIMING_TRG_RECEIVED_IN <= TRG_TIMING_TRG_RECEIVED_IN;
---         last_timingtrg_counter_write <= timingtrg_counter_write;
---         last_timingtrg_counter_read <= timingtrg_counter_read;
---         if RESET = '1' or timingtrg_counter_write = '1' then
---           timingtrg_counter <= (others => '0');
---         elsif TRG_TIMING_TRG_RECEIVED_IN = '1' and last_TRG_TIMING_TRG_RECEIVED_IN = '0' then
---           timingtrg_counter <= (others => '0');
---         end if;
---       end if;
---     end process;
-
-
-
--------------------------------------------------
--- Connect Outputs
--------------------------------------------------
---   buf_LVL1_TRG_RELEASE_IN        <= LVL1_TRG_RELEASE_IN;           --changed back
---   LVL1_TRG_DATA_VALID_OUT        <= buf_LVL1_TRG_RECEIVED_OUT;     --changed back
-  LVL1_TRG_DATA_VALID_OUT        <= buf_LVL1_TRG_DATA_VALID_OUT;  --changed back
-
-  LVL1_TRG_VALID_TIMING_OUT      <= buf_LVL1_VALID_TIMING_TRG_OUT;
-  LVL1_TRG_VALID_NOTIMING_OUT    <= buf_LVL1_VALID_NOTIMING_TRG_OUT;
-  LVL1_TRG_INVALID_OUT           <= buf_LVL1_INVALID_TRG_OUT;
-
-  LVL1_TRG_TYPE_OUT              <= buf_LVL1_TRG_TYPE_OUT;
-  LVL1_TRG_NUMBER_OUT            <= buf_LVL1_TRG_NUMBER_OUT;
-  LVL1_TRG_CODE_OUT              <= buf_LVL1_TRG_CODE_OUT;
-  LVL1_TRG_INFORMATION_OUT       <= buf_LVL1_TRG_INFORMATION_OUT;
-  LVL1_INT_TRG_NUMBER_OUT        <= int_trigger_num;
-
-  COMMON_STAT_REG_STROBE         <= buf_COMMON_STAT_REG_STROBE;
-  COMMON_CTRL_REG_STROBE         <= buf_COMMON_CTRL_REG_STROBE;
-  STAT_REG_STROBE                <= buf_STAT_REG_STROBE;
-  CTRL_REG_STROBE                <= buf_CTRL_REG_STROBE;
-
-  TIMER_TICKS_OUT                <= buf_TIMER_TICKS_OUT;
-
-  buf_CTRL_GEN                   <= IOBUF_CTRL_GEN;
-  REGIO_COMMON_CTRL_REG_OUT      <= buf_REGIO_COMMON_CTRL_REG_OUT;
-
-  STAT_DEBUG_1                   <= REGIO_REGIO_STAT;
-  STAT_DEBUG_2(3 downto 0)       <= MED_IO_DATA_OUT(7*16+3 downto 7*16);
-  STAT_DEBUG_2(7 downto 4)       <= apl_to_buf_REPLY_DATA(3*16+3 downto 3*16);
-  STAT_DEBUG_2(8)                <= apl_to_buf_REPLY_DATAREADY(3);
-  STAT_DEBUG_2(11 downto 9)      <= apl_to_buf_REPLY_PACKET_NUM(3*3+2 downto 3*3);
-  STAT_DEBUG_2(15 downto 12)     <= (others => '0');
-  STAT_DEBUG_2(31 downto 16)     <= buf_STAT_INIT_BUFFER(3*32+15 downto 3*32);
-
-  STAT_TRIGGER_OUT               <= stat_counters_lvl1_handler;
-
-end architecture;
-
diff --git a/data_concentrator/trb_net16_endpoint_data_concentrator_handler.vhd b/data_concentrator/trb_net16_endpoint_data_concentrator_handler.vhd
deleted file mode 100644
index f9f7cd4..0000000
--- a/data_concentrator/trb_net16_endpoint_data_concentrator_handler.vhd
+++ /dev/null
@@ -1,801 +0,0 @@
--- the full endpoint for HADES: trg, data, unused, regio including data buffer & handling
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-
-
-entity trb_net16_endpoint_data_concentrator_handler is
-  generic (
-    IBUF_DEPTH                   : channel_config_t              := (6,6,6,6);
-    FIFO_TO_INT_DEPTH            : channel_config_t              := (6,6,6,6);
-    FIFO_TO_APL_DEPTH            : channel_config_t              := (1,1,1,1);
-    APL_WRITE_ALL_WORDS          : channel_config_t              := (c_NO,c_NO,c_NO,c_NO);
-    ADDRESS_MASK                 : std_logic_vector(15 downto 0) := x"FFFF";
-    BROADCAST_BITMASK            : std_logic_vector(7 downto 0)  := x"FF";
-    BROADCAST_SPECIAL_ADDR       : std_logic_vector(7 downto 0)  := x"FF";
-    REGIO_NUM_STAT_REGS          : integer range 0 to 6          := 3; --log2 of number of status registers
-    REGIO_NUM_CTRL_REGS          : integer range 0 to 6          := 3; --log2 of number of ctrl registers
-    REGIO_INIT_CTRL_REGS         : std_logic_vector(16*32-1 downto 0) := (others => '0');
-    REGIO_INIT_ADDRESS           : std_logic_vector(15 downto 0) := x"FFFF";
-    REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
-    REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
-    REGIO_COMPILE_TIME           : std_logic_vector(31 downto 0) := x"00000000";
-    REGIO_COMPILE_VERSION        : std_logic_vector(15 downto 0) := x"0001";
-    REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
-    REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
-    REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES   := c_NO;
-    CLOCK_FREQUENCY              : integer range 1 to 200        := 100;
-    TIMING_TRIGGER_RAW           : integer range 0 to 1 := c_YES;
-    --Configure data handler
-    DATA_INTERFACE_NUMBER        : integer range 1 to 16         := 1;
-    DATA_BUFFER_DEPTH            : integer range 9 to 14         := 9;
-    DATA_BUFFER_WIDTH            : integer range 1 to 32         := 32;
-    DATA_BUFFER_FULL_THRESH      : integer range 0 to 2**14-2    := 2**8;
-    TRG_RELEASE_AFTER_DATA       : integer range 0 to 1          := c_YES;
-    HEADER_BUFFER_DEPTH          : integer range 9 to 14         := 9;
-    HEADER_BUFFER_FULL_THRESH    : integer range 2**8 to 2**14-2 := 2**8
-    );
-
-  port(
-    --  Misc
-    CLK                          : in  std_logic;
-    RESET                        : in  std_logic;
-    CLK_EN                       : in  std_logic := '1';
-
-    --  Media direction port
-    MED_DATAREADY_OUT            : out std_logic;
-    MED_DATA_OUT                 : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_OUT           : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-    MED_READ_IN                  : in  std_logic;
-    MED_DATAREADY_IN             : in  std_logic;
-    MED_DATA_IN                  : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_IN            : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-    MED_READ_OUT                 : out std_logic;
-    MED_STAT_OP_IN               : in  std_logic_vector(15 downto 0);
-    MED_CTRL_OP_OUT              : out std_logic_vector(15 downto 0);
-
-    --Timing trigger in
-    TRG_TIMING_TRG_RECEIVED_IN   : in  std_logic;
-    --LVL1 trigger to FEE
-    LVL1_TRG_DATA_VALID_OUT      : out std_logic;    --trigger type, number, code, information are valid
-    LVL1_VALID_TIMING_TRG_OUT    : out std_logic;    --valid timing trigger has been received
-    LVL1_VALID_NOTIMING_TRG_OUT  : out std_logic;    --valid trigger without timing trigger has been received
-    LVL1_INVALID_TRG_OUT         : out std_logic;    --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
-
-    LVL1_TRG_TYPE_OUT            : out std_logic_vector(3 downto 0);
-    LVL1_TRG_NUMBER_OUT          : out std_logic_vector(15 downto 0);
-    LVL1_TRG_CODE_OUT            : out std_logic_vector(7 downto 0);
-    LVL1_TRG_INFORMATION_OUT     : out std_logic_vector(23 downto 0);
-    LVL1_INT_TRG_NUMBER_OUT      : out std_logic_vector(15 downto 0);  --internally generated trigger number, for informational uses only
-
-    --Information about trigger handler errors
-    TRG_MULTIPLE_TRG_OUT         : out std_logic;
-    TRG_TIMEOUT_DETECTED_OUT     : out std_logic;
-    TRG_SPURIOUS_TRG_OUT         : out std_logic;
-    TRG_MISSING_TMG_TRG_OUT      : out std_logic;
-    TRG_SPIKE_DETECTED_OUT       : out std_logic;
-
-    --Response from FEE
-    FEE_TRG_RELEASE_IN           : in  std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
-    FEE_TRG_STATUSBITS_IN        : in  std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
-    FEE_DATA_IN                  : in  std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
-    FEE_DATA_WRITE_IN            : in  std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
-    FEE_DATA_FINISHED_IN         : in  std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
-    FEE_DATA_ALMOST_FULL_OUT     : out std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
-
-    --Slow Control Port
-    --common registers
-    REGIO_COMMON_STAT_REG_IN     : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
-    REGIO_COMMON_CTRL_REG_OUT    : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-    REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);
-    REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);
-    --user defined registers
-    REGIO_STAT_REG_IN            : in  std_logic_vector(2**(REGIO_NUM_STAT_REGS)*32-1 downto 0) := (others => '0');
-    REGIO_CTRL_REG_OUT           : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
-    REGIO_STAT_STROBE_OUT        : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
-    REGIO_CTRL_STROBE_OUT        : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-    --internal data port
-    BUS_ADDR_OUT                 : out std_logic_vector(16-1 downto 0);
-    BUS_DATA_OUT                 : out std_logic_vector(32-1 downto 0);
-    BUS_READ_ENABLE_OUT          : out std_logic;
-    BUS_WRITE_ENABLE_OUT         : out std_logic;
-    BUS_TIMEOUT_OUT              : out std_logic;
-    BUS_DATA_IN                  : in  std_logic_vector(32-1 downto 0) := (others => '0');
-    BUS_DATAREADY_IN             : in  std_logic                       := '0';
-    BUS_WRITE_ACK_IN             : in  std_logic                       := '0';
-    BUS_NO_MORE_DATA_IN          : in  std_logic                       := '0';
-    BUS_UNKNOWN_ADDR_IN          : in  std_logic                       := '0';
-    --Onewire
-    ONEWIRE_INOUT                : inout std_logic;  --temperature sensor
-    ONEWIRE_MONITOR_IN           : in  std_logic := '0';
-    ONEWIRE_MONITOR_OUT          : out std_logic;
-    --Config endpoint id, if not statically assigned
-    REGIO_VAR_ENDPOINT_ID        : in  std_logic_vector (15 downto 0) := (others => '0');
-
-    --Timing registers
-    TIME_GLOBAL_OUT              : out std_logic_vector (31 downto 0); --global time, microseconds
-    TIME_LOCAL_OUT               : out std_logic_vector ( 7 downto 0); --local time running with chip frequency
-    TIME_SINCE_LAST_TRG_OUT      : out std_logic_vector (31 downto 0); --local time, resetted with each trigger
-    TIME_TICKS_OUT               : out std_logic_vector ( 1 downto 0); --bit 1 ms-tick, 0 us-tick
-
-    --Debugging & Status information
-    STAT_DEBUG_IPU               : out std_logic_vector (31 downto 0);
-    STAT_DEBUG_1                 : out std_logic_vector (31 downto 0);
-    STAT_DEBUG_2                 : out std_logic_vector (31 downto 0);
-    STAT_DEBUG_DATA_HANDLER_OUT  : out std_logic_vector (31 downto 0);
-    STAT_DEBUG_IPU_HANDLER_OUT   : out std_logic_vector (31 downto 0);
-    CTRL_MPLEX                   : in  std_logic_vector (31 downto 0) := (others => '0');
-    IOBUF_CTRL_GEN               : in  std_logic_vector (4*32-1 downto 0) := (others => '0');
-    STAT_ONEWIRE                 : out std_logic_vector (31 downto 0);
-    STAT_ADDR_DEBUG              : out std_logic_vector (15 downto 0);
-    STAT_TRIGGER_OUT             : out std_logic_vector (79 downto 0);
-    DEBUG_LVL1_HANDLER_OUT       : out std_logic_vector (15 downto 0)
-    );
-end entity;
-
-
-
-
-
-architecture trb_net16_endpoint_data_concentrator_handler_arch of trb_net16_endpoint_data_concentrator_handler is
-
-component trb_net16_endpoint_data_concentrator is
-  generic (
-    USE_CHANNEL                  : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
-    IBUF_DEPTH                   : channel_config_t := (6,6,6,6);
-    FIFO_TO_INT_DEPTH            : channel_config_t := (6,6,6,6);
-    FIFO_TO_APL_DEPTH            : channel_config_t := (1,1,1,1);
-    IBUF_SECURE_MODE             : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
-    API_SECURE_MODE_TO_APL       : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
-    API_SECURE_MODE_TO_INT       : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
-    OBUF_DATA_COUNT_WIDTH        : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
-    INIT_CAN_SEND_DATA           : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
-    REPLY_CAN_SEND_DATA          : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
-    REPLY_CAN_RECEIVE_DATA       : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
-    USE_CHECKSUM                 : channel_config_t := (c_NO,c_NO,c_NO,c_YES);
-    APL_WRITE_ALL_WORDS          : channel_config_t := (c_NO,c_NO,c_NO,c_NO);
-    ADDRESS_MASK                 : std_logic_vector(15 downto 0) := x"FFFF";
-    BROADCAST_BITMASK            : std_logic_vector(7 downto 0) := x"FF";
-    BROADCAST_SPECIAL_ADDR       : std_logic_vector(7 downto 0) := x"FF";
-    TIMING_TRIGGER_RAW           : integer range 0 to 1 := c_YES;
-    REGIO_NUM_STAT_REGS          : integer range 0 to 6 := 3; --log2 of number of status registers
-    REGIO_NUM_CTRL_REGS          : integer range 0 to 6 := 3; --log2 of number of ctrl registers
-    --standard values for output registers
-    REGIO_INIT_CTRL_REGS         : std_logic_vector(2**(4)*32-1 downto 0) := (others => '0');
-    --set to 0 for unused ctrl registers to save resources
-    REGIO_USED_CTRL_REGS         : std_logic_vector(2**(4)-1 downto 0)    := (others => '1');
-    --set to 0 for each unused bit in a register
-    REGIO_USED_CTRL_BITMASK      : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1');
-    REGIO_USE_DAT_PORT           : integer range 0 to 1 := c_YES;  --internal data port
-    REGIO_INIT_ADDRESS           : std_logic_vector(15 downto 0) := x"FFFF";
-    REGIO_INIT_UNIQUE_ID         : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876";
-    REGIO_INIT_BOARD_INFO        : std_logic_vector(31 downto 0) := x"1111_2222";
-    REGIO_INIT_ENDPOINT_ID       : std_logic_vector(15 downto 0) := x"0001";
-    REGIO_COMPILE_TIME           : std_logic_vector(31 downto 0) := x"00000000";
-    REGIO_COMPILE_VERSION        : std_logic_vector(15 downto 0) := x"0001";
-    REGIO_HARDWARE_VERSION       : std_logic_vector(31 downto 0) := x"12345678";
-    REGIO_USE_1WIRE_INTERFACE    : integer := c_YES; --c_YES,c_NO,c_MONITOR
-    REGIO_USE_VAR_ENDPOINT_ID    : integer range c_NO to c_YES := c_NO;
-    CLOCK_FREQUENCY              : integer range 1 to 200 := 100
-    );
-
-  port(
-    --  Misc
-    CLK                          : in std_logic;
-    RESET                        : in std_logic;
-    CLK_EN                       : in std_logic := '1';
-
-    --  Media direction port
-    MED_DATAREADY_OUT            : out std_logic;
-    MED_DATA_OUT                 : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_OUT           : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
-    MED_READ_IN                  : in  std_logic;
-    MED_DATAREADY_IN             : in  std_logic;
-    MED_DATA_IN                  : in  std_logic_vector (c_DATA_WIDTH-1 downto 0);
-    MED_PACKET_NUM_IN            : in  std_logic_vector (c_NUM_WIDTH-1 downto 0);
-    MED_READ_OUT                 : out std_logic;
-    MED_STAT_OP_IN               : in  std_logic_vector(15 downto 0);
-    MED_CTRL_OP_OUT              : out std_logic_vector(15 downto 0);
-
-    -- LVL1 trigger APL
-    TRG_TIMING_TRG_RECEIVED_IN   : in  std_logic;    --strobe when timing trigger received or real timing trigger signal
-
-    LVL1_TRG_DATA_VALID_OUT      : out std_logic;    --trigger type, number, code, information are valid
-    LVL1_TRG_VALID_TIMING_OUT    : out std_logic;    --valid timing trigger has been received
-    LVL1_TRG_VALID_NOTIMING_OUT  : out std_logic;    --valid trigger without timing trigger has been received
-    LVL1_TRG_INVALID_OUT         : out std_logic;    --the current trigger is invalid (e.g. no timing trigger, no LVL1...)
-
-    LVL1_TRG_TYPE_OUT            : out std_logic_vector(3 downto 0);
-    LVL1_TRG_NUMBER_OUT          : out std_logic_vector(15 downto 0);
-    LVL1_TRG_CODE_OUT            : out std_logic_vector(7 downto 0);
-    LVL1_TRG_INFORMATION_OUT     : out std_logic_vector(23 downto 0);
-
-    LVL1_ERROR_PATTERN_IN        : in  std_logic_vector(31 downto 0) := x"00000000";
-    LVL1_TRG_RELEASE_IN          : in  std_logic := '0';
-    LVL1_INT_TRG_NUMBER_OUT      : out std_logic_vector(15 downto 0);  --internally generated trigger number, for informational uses only
-
-    --Information about trigger handler errors
-    TRG_MULTIPLE_TRG_OUT         : out std_logic;
-    TRG_TIMEOUT_DETECTED_OUT     : out std_logic;
-    TRG_SPURIOUS_TRG_OUT         : out std_logic;
-    TRG_MISSING_TMG_TRG_OUT      : out std_logic;
-    TRG_SPIKE_DETECTED_OUT       : out std_logic;
-    TRG_LONG_TRG_OUT             : out std_logic;
-
-    --Data Port
-    IPU_NUMBER_OUT               : out std_logic_vector (15 downto 0);
-    IPU_READOUT_TYPE_OUT         : out std_logic_vector (3 downto 0);
-    IPU_INFORMATION_OUT          : out std_logic_vector (7 downto 0);
-    --start strobe
-    IPU_START_READOUT_OUT        : out std_logic;
-    --detector data, equipped with DHDR
-    IPU_DATA_IN                  : in  std_logic_vector (31 downto 0);
-    IPU_DATAREADY_IN             : in  std_logic;
-    --no more data, end transfer, send TRM
-    IPU_READOUT_FINISHED_IN      : in  std_logic;
-    --will be low every second cycle due to 32bit -> 16bit conversion
-    IPU_READ_OUT                 : out std_logic;
-    IPU_LENGTH_IN                : in  std_logic_vector (15 downto 0);
-    IPU_ERROR_PATTERN_IN         : in  std_logic_vector (31 downto 0);
-
-
-    -- Slow Control Data Port
-    REGIO_COMMON_STAT_REG_IN  : in  std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
-    REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-    REGIO_REGISTERS_IN        : in  std_logic_vector(32*2**(REGIO_NUM_STAT_REGS)-1 downto 0) := (others => '0');
-    REGIO_REGISTERS_OUT       : out std_logic_vector(32*2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-    COMMON_STAT_REG_STROBE    : out std_logic_vector(std_COMSTATREG-1 downto 0);
-    COMMON_CTRL_REG_STROBE    : out std_logic_vector(std_COMCTRLREG-1 downto 0);
-    STAT_REG_STROBE           : out std_logic_vector(2**(REGIO_NUM_STAT_REGS)-1 downto 0);
-    CTRL_REG_STROBE           : out std_logic_vector(2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-    --following ports only used when using internal data port
-    REGIO_ADDR_OUT            : out std_logic_vector(16-1 downto 0);
-    REGIO_READ_ENABLE_OUT     : out std_logic;
-    REGIO_WRITE_ENABLE_OUT    : out std_logic;
-    REGIO_DATA_OUT            : out std_logic_vector(32-1 downto 0);
-    REGIO_DATA_IN             : in  std_logic_vector(32-1 downto 0) := (others => '0');
-    REGIO_DATAREADY_IN        : in  std_logic := '0';
-    REGIO_NO_MORE_DATA_IN     : in  std_logic := '0';
-    REGIO_WRITE_ACK_IN        : in  std_logic := '0';
-    REGIO_UNKNOWN_ADDR_IN     : in  std_logic := '0';
-    REGIO_TIMEOUT_OUT         : out std_logic;
-    --IDRAM is used if no 1-wire interface, onewire used otherwise
-    REGIO_IDRAM_DATA_IN       : in  std_logic_vector(15 downto 0) := (others => '0');
-    REGIO_IDRAM_DATA_OUT      : out std_logic_vector(15 downto 0);
-    REGIO_IDRAM_ADDR_IN       : in  std_logic_vector(2 downto 0) := "000";
-    REGIO_IDRAM_WR_IN         : in  std_logic := '0';
-    REGIO_ONEWIRE_INOUT       : inout std_logic;  --temperature sensor
-    REGIO_ONEWIRE_MONITOR_IN  : in  std_logic := '0';
-    REGIO_ONEWIRE_MONITOR_OUT : out std_logic;
-    REGIO_VAR_ENDPOINT_ID     : in  std_logic_vector(15 downto 0) := (others => '0');
-
-    GLOBAL_TIME_OUT           : out std_logic_vector(31 downto 0); --global time, microseconds
-    LOCAL_TIME_OUT            : out std_logic_vector(7 downto 0);  --local time running with chip frequency
-    TIME_SINCE_LAST_TRG_OUT   : out std_logic_vector(31 downto 0); --local time, resetted with each trigger
-    TIMER_TICKS_OUT           : out std_logic_vector(1 downto 0);  --bit 1 ms-tick, 0 us-tick
-    --Debugging & Status information
-    STAT_DEBUG_IPU            : out std_logic_vector (31 downto 0);
-    STAT_DEBUG_1              : out std_logic_vector (31 downto 0);
-    STAT_DEBUG_2              : out std_logic_vector (31 downto 0);
-    MED_STAT_OP               : out std_logic_vector (15 downto 0);
-    CTRL_MPLEX                : in  std_logic_vector (31 downto 0) := (others => '0');
-    IOBUF_CTRL_GEN            : in  std_logic_vector (4*32-1 downto 0) := (others => '0');
-    STAT_ONEWIRE              : out std_logic_vector (31 downto 0);
-    STAT_ADDR_DEBUG           : out std_logic_vector (15 downto 0);
-    STAT_TRIGGER_OUT          : out std_logic_vector (79 downto 0);
-    DEBUG_LVL1_HANDLER_OUT    : out std_logic_vector (15 downto 0)
-    );
-end component;
-
-
-  signal lvl1_data_valid_i       : std_logic;
-  signal lvl1_valid_i            : std_logic;
-  signal lvl1_valid_timing_i     : std_logic;
-  signal lvl1_valid_notiming_i   : std_logic;
-  signal lvl1_invalid_i          : std_logic;
-  signal lvl1_type_i             : std_logic_vector ( 3 downto 0);
-  signal lvl1_number_i           : std_logic_vector (15 downto 0);
-  signal lvl1_code_i             : std_logic_vector ( 7 downto 0);
-  signal lvl1_information_i      : std_logic_vector (23 downto 0);
-  signal lvl1_error_pattern_i    : std_logic_vector (31 downto 0);
-  signal lvl1_release_i          : std_logic;
-  signal lvl1_int_trg_number_i   : std_logic_vector (15 downto 0);
-
-  signal ipu_number_i            : std_logic_vector (15 downto 0);
-  signal ipu_readout_type_i      : std_logic_vector ( 3 downto 0);
-  signal ipu_information_i       : std_logic_vector ( 7 downto 0);
-  signal ipu_start_readout_i     : std_logic;
-  signal ipu_data_i              : std_logic_vector (31 downto 0);
-  signal ipu_dataready_i         : std_logic;
-  signal ipu_readout_finished_i  : std_logic;
-  signal ipu_read_i              : std_logic;
-  signal ipu_length_i            : std_logic_vector (15 downto 0);
-  signal ipu_error_pattern_i     : std_logic_vector (31 downto 0);
-  signal reset_ipu_i             : std_logic;
-
-  signal common_stat_reg_i       : std_logic_vector (std_COMSTATREG*32-1 downto 0);
-  signal common_ctrl_reg_i       : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
-  signal common_stat_strobe_i    : std_logic_vector (std_COMSTATREG-1 downto 0);
-  signal common_ctrl_strobe_i    : std_logic_vector (std_COMCTRLREG-1 downto 0);
-  signal stat_reg_i              : std_logic_vector (2**(REGIO_NUM_STAT_REGS)*32-1 downto 0);
-  signal ctrl_reg_i              : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)*32-1 downto 0);
-  signal stat_strobe_i           : std_logic_vector (2**(REGIO_NUM_STAT_REGS)-1 downto 0);
-  signal ctrl_strobe_i           : std_logic_vector (2**(REGIO_NUM_CTRL_REGS)-1 downto 0);
-
-  signal regio_addr_i            : std_logic_vector (15 downto 0);
-  signal regio_read_enable_i     : std_logic;
-  signal regio_write_enable_i    : std_logic;
-  signal regio_data_out_i        : std_logic_vector (31 downto 0);
-  signal regio_data_in_i         : std_logic_vector (31 downto 0);
-  signal regio_dataready_i       : std_logic;
-  signal regio_nomoredata_i      : std_logic;
-  signal regio_write_ack_i       : std_logic;
-  signal regio_unknown_addr_i    : std_logic;
-  signal regio_timeout_i         : std_logic;
-
-  signal time_global_i           : std_logic_vector (31 downto 0);
-  signal time_local_i            : std_logic_vector ( 7 downto 0);
-  signal time_since_last_trg_i   : std_logic_vector (31 downto 0);
-  signal time_ticks_i            : std_logic_vector ( 1 downto 0);
-
-  signal stat_handler_i          : std_logic_vector (127 downto 0);
-  signal stat_data_buffer_level  : std_logic_vector (DATA_INTERFACE_NUMBER*32-1 downto 0);
-  signal stat_header_buffer_level: std_logic_vector (31 downto 0);
-
-  signal dbuf_read_enable        : std_logic;
-  signal dbuf_addr               : std_logic_vector (3 downto 0);
-  signal dbuf_data_in            : std_logic_vector (31 downto 0);
-  signal dbuf_dataready          : std_logic;
-  signal dbuf_unknown_addr       : std_logic;
-
-  signal tbuf_dataready          : std_logic;
-  signal tbuf_read_enable        : std_logic;
-
-  signal dummy                   : std_logic_vector(300 downto 0);
-  signal write_enable            : std_logic_vector(6 downto 0);
-  signal read_enable             : std_logic_vector(6 downto 0);
-  signal last_write_enable       : std_logic_vector(6 downto 0);
-  signal last_read_enable        : std_logic_vector(6 downto 0);
-
-  signal debug_data_handler_i    : std_logic_vector(31 downto 0);
-  signal debug_ipu_handler_i     : std_logic_vector(31 downto 0);
-
-  signal int_multiple_trg          : std_logic;
-  signal int_lvl1_timeout_detected : std_logic;
-  signal int_lvl1_spurious_trg     : std_logic;
-  signal int_lvl1_missing_tmg_trg  : std_logic;
-  signal int_spike_detected        : std_logic;
-  signal int_lvl1_long_trg         : std_logic;
-  signal tmg_trg_error_i           : std_logic;
-
-  signal stat_buffer_i             : std_logic_vector(31 downto 0);
-  signal stat_buffer_read          : std_logic;
-  signal stat_buffer_ready         : std_logic;
-  signal stat_buffer_unknown       : std_logic;
-  signal stat_buffer_address       : std_logic_vector(4 downto 0);
-
-
-begin
----------------------------------------------------------------------------
--- TrbNet Endpoint
----------------------------------------------------------------------------
-
-  THE_ENDPOINT: trb_net16_endpoint_data_concentrator ---- trb_net16_endpoint_hades_full
-    generic map(
-      IBUF_DEPTH                 => IBUF_DEPTH,
-      FIFO_TO_INT_DEPTH          => FIFO_TO_INT_DEPTH,
-      FIFO_TO_APL_DEPTH          => FIFO_TO_APL_DEPTH,
-      APL_WRITE_ALL_WORDS        => APL_WRITE_ALL_WORDS,
-      ADDRESS_MASK               => ADDRESS_MASK,
-      BROADCAST_BITMASK          => BROADCAST_BITMASK,
-      BROADCAST_SPECIAL_ADDR     => BROADCAST_SPECIAL_ADDR,
-      REGIO_NUM_STAT_REGS        => REGIO_NUM_STAT_REGS,
-      REGIO_NUM_CTRL_REGS        => REGIO_NUM_CTRL_REGS,
-      REGIO_INIT_CTRL_REGS       => REGIO_INIT_CTRL_REGS,
-      REGIO_INIT_ADDRESS         => REGIO_INIT_ADDRESS,
-      REGIO_INIT_BOARD_INFO      => REGIO_INIT_BOARD_INFO,
-      REGIO_INIT_ENDPOINT_ID     => REGIO_INIT_ENDPOINT_ID,
-      REGIO_COMPILE_TIME         => REGIO_COMPILE_TIME,
-      REGIO_COMPILE_VERSION      => REGIO_COMPILE_VERSION,
-      REGIO_HARDWARE_VERSION     => REGIO_HARDWARE_VERSION,
-      REGIO_USE_1WIRE_INTERFACE  => REGIO_USE_1WIRE_INTERFACE,
-      REGIO_USE_VAR_ENDPOINT_ID  => REGIO_USE_VAR_ENDPOINT_ID,
-      TIMING_TRIGGER_RAW         => TIMING_TRIGGER_RAW,
-      CLOCK_FREQUENCY            => CLOCK_FREQUENCY
-      )
-    port map(
-      CLK                        => CLK,
-      RESET                      => RESET,
-      CLK_EN                     => CLK_EN,
-
-      MED_DATAREADY_OUT          => MED_DATAREADY_OUT,
-      MED_DATA_OUT               => MED_DATA_OUT,
-      MED_PACKET_NUM_OUT         => MED_PACKET_NUM_OUT,
-      MED_READ_IN                => MED_READ_IN,
-      MED_DATAREADY_IN           => MED_DATAREADY_IN,
-      MED_DATA_IN                => MED_DATA_IN,
-      MED_PACKET_NUM_IN          => MED_PACKET_NUM_IN,
-      MED_READ_OUT               => MED_READ_OUT,
-      MED_STAT_OP_IN             => MED_STAT_OP_IN,
-      MED_CTRL_OP_OUT            => MED_CTRL_OP_OUT,
-
-      -- LVL1 trigger APL
-      TRG_TIMING_TRG_RECEIVED_IN => TRG_TIMING_TRG_RECEIVED_IN,
-      LVL1_TRG_DATA_VALID_OUT    => lvl1_data_valid_i,
-      LVL1_TRG_VALID_TIMING_OUT  => lvl1_valid_timing_i,
-      LVL1_TRG_VALID_NOTIMING_OUT=> lvl1_valid_notiming_i,
-      LVL1_TRG_INVALID_OUT       => lvl1_invalid_i,
-      LVL1_TRG_TYPE_OUT          => lvl1_type_i,
-      LVL1_TRG_NUMBER_OUT        => lvl1_number_i,
-      LVL1_TRG_CODE_OUT          => lvl1_code_i,
-      LVL1_TRG_INFORMATION_OUT   => lvl1_information_i,
-      LVL1_ERROR_PATTERN_IN      => lvl1_error_pattern_i,
-      LVL1_TRG_RELEASE_IN        => lvl1_release_i,
-      LVL1_INT_TRG_NUMBER_OUT    => lvl1_int_trg_number_i,
-
-      --Information about trigger handler errors
-      TRG_SPIKE_DETECTED_OUT     => int_spike_detected,
-      TRG_SPURIOUS_TRG_OUT       => int_lvl1_spurious_trg,
-      TRG_TIMEOUT_DETECTED_OUT   => int_lvl1_timeout_detected,
-      TRG_MULTIPLE_TRG_OUT       => int_multiple_trg,
-      TRG_MISSING_TMG_TRG_OUT    => int_lvl1_missing_tmg_trg,
-      TRG_LONG_TRG_OUT           => int_lvl1_long_trg,
-      --Data Port
-      IPU_NUMBER_OUT             => ipu_number_i,
-      IPU_READOUT_TYPE_OUT       => ipu_readout_type_i,
-      IPU_INFORMATION_OUT        => ipu_information_i,
-      IPU_START_READOUT_OUT      => ipu_start_readout_i,
-      IPU_DATA_IN                => ipu_data_i,
-      IPU_DATAREADY_IN           => ipu_dataready_i,
-      IPU_READOUT_FINISHED_IN    => ipu_readout_finished_i,
-      IPU_READ_OUT               => ipu_read_i,
-      IPU_LENGTH_IN              => ipu_length_i,
-      IPU_ERROR_PATTERN_IN       => ipu_error_pattern_i,
-
-      -- Slow Control Data Port
-      REGIO_COMMON_STAT_REG_IN   => common_stat_reg_i,
-      REGIO_COMMON_CTRL_REG_OUT  => common_ctrl_reg_i,
-      REGIO_REGISTERS_IN         => stat_reg_i,
-      REGIO_REGISTERS_OUT        => ctrl_reg_i,
-      COMMON_STAT_REG_STROBE     => common_stat_strobe_i,
-      COMMON_CTRL_REG_STROBE     => common_ctrl_strobe_i,
-      STAT_REG_STROBE            => stat_strobe_i,
-      CTRL_REG_STROBE            => ctrl_strobe_i,
-
-      REGIO_ADDR_OUT             => regio_addr_i,
-      REGIO_READ_ENABLE_OUT      => regio_read_enable_i,
-      REGIO_WRITE_ENABLE_OUT     => regio_write_enable_i,
-      REGIO_DATA_OUT             => regio_data_out_i,
-      REGIO_DATA_IN              => regio_data_in_i,
-      REGIO_DATAREADY_IN         => regio_dataready_i,
-      REGIO_NO_MORE_DATA_IN      => regio_nomoredata_i,
-      REGIO_WRITE_ACK_IN         => regio_write_ack_i,
-      REGIO_UNKNOWN_ADDR_IN      => regio_unknown_addr_i,
-      REGIO_TIMEOUT_OUT          => regio_timeout_i,
-
-      REGIO_ONEWIRE_INOUT        => ONEWIRE_INOUT,
-      REGIO_ONEWIRE_MONITOR_IN   => ONEWIRE_MONITOR_IN,
-      REGIO_ONEWIRE_MONITOR_OUT  => ONEWIRE_MONITOR_OUT,
-      REGIO_VAR_ENDPOINT_ID      => REGIO_VAR_ENDPOINT_ID,
-
-      GLOBAL_TIME_OUT            => time_global_i,
-      LOCAL_TIME_OUT             => time_local_i,
-      TIME_SINCE_LAST_TRG_OUT    => time_since_last_trg_i,
-      TIMER_TICKS_OUT            => time_ticks_i,
-
-      STAT_DEBUG_IPU             => open,
-      STAT_DEBUG_1               => open,
-      STAT_DEBUG_2               => open,
-      MED_STAT_OP                => open,
-      CTRL_MPLEX                 => (others => '0'),
-      IOBUF_CTRL_GEN             => (others => '0'),
-      STAT_ONEWIRE               => open,
-      STAT_ADDR_DEBUG            => open,
-      STAT_TRIGGER_OUT           => STAT_TRIGGER_OUT,      
-      DEBUG_LVL1_HANDLER_OUT     => DEBUG_LVL1_HANDLER_OUT
-      );
-
----------------------------------------------------------------------------
--- RegIO Bus Handler
----------------------------------------------------------------------------
-
-  THE_INTERNAL_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER                => 7,
-      PORT_ADDRESSES             => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", 6 => x"7300", others => x"0000"),
-      PORT_ADDR_MASK             => (0 => 15,      1 => 4,       2 => 0,       3 => 0,       4 => 0,       5 => 0,       6 => 5,       others => 0)
-      )
-    port map(
-      CLK                        => CLK,
-      RESET                      => RESET,
-
-      DAT_ADDR_IN                => regio_addr_i,
-      DAT_DATA_IN                => regio_data_out_i,
-      DAT_DATA_OUT               => regio_data_in_i,
-      DAT_READ_ENABLE_IN         => regio_read_enable_i,
-      DAT_WRITE_ENABLE_IN        => regio_write_enable_i,
-      DAT_TIMEOUT_IN             => regio_timeout_i,
-      DAT_DATAREADY_OUT          => regio_dataready_i,
-      DAT_WRITE_ACK_OUT          => regio_write_ack_i,
-      DAT_NO_MORE_DATA_OUT       => regio_nomoredata_i,
-      DAT_UNKNOWN_ADDR_OUT       => regio_unknown_addr_i,
-
---       BUS_READ_ENABLE_OUT(0)     => BUS_READ_ENABLE_OUT,
---       BUS_WRITE_ENABLE_OUT(0)    => BUS_WRITE_ENABLE_OUT,
---       BUS_DATA_OUT(31 downto 0)  => BUS_DATA_OUT,
---       BUS_ADDR_OUT(15 downto 0)  => BUS_ADDR_OUT,
---       BUS_TIMEOUT_OUT(0)         => BUS_TIMEOUT_OUT,
---       BUS_DATA_IN(31 downto 0)   => BUS_DATA_IN,
---       BUS_DATAREADY_IN(0)        => BUS_DATAREADY_IN,
---       BUS_WRITE_ACK_IN(0)        => BUS_WRITE_ACK_IN,
---       BUS_NO_MORE_DATA_IN(0)     => BUS_NO_MORE_DATA_IN,
---       BUS_UNKNOWN_ADDR_IN(0)     => BUS_UNKNOWN_ADDR_IN,
---
---       BUS_READ_ENABLE_OUT(1)     => dbuf_read_enable,
---       BUS_WRITE_ENABLE_OUT(1)    => open,
---       BUS_DATA_OUT(63 downto 32) => open,
---       BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
---       BUS_ADDR_OUT(31 downto 20) => open,
---       BUS_TIMEOUT_OUT(1)         => open,
---       BUS_DATA_IN(63 downto 32)  => dbuf_data_in,
---       BUS_DATAREADY_IN(1)        => dbuf_dataready,
---       BUS_WRITE_ACK_IN(1)        => '0',
---       BUS_NO_MORE_DATA_IN(1)     => '0',
---       BUS_UNKNOWN_ADDR_IN(1)     => dbuf_unknown_addr,
---
---       BUS_READ_ENABLE_OUT(2)     => tbuf_read_enable,
---       BUS_WRITE_ENABLE_OUT(2)    => open,
---       BUS_DATA_OUT(95 downto 64) => open,
---       BUS_ADDR_OUT(47 downto 32) => open,
---       BUS_TIMEOUT_OUT(1)         => open,
---       BUS_DATA_IN(95 downto 64)  => stat_header_buffer_level,
---       BUS_DATAREADY_IN(2)        => tbuf_dataready,
---       BUS_WRITE_ACK_IN(2)        => '0',
---       BUS_NO_MORE_DATA_IN(2)     => '0',
---       BUS_UNKNOWN_ADDR_IN(2)     => '0'
-
---Fucking Modelsim wants it like this...
-      BUS_READ_ENABLE_OUT(0)     => BUS_READ_ENABLE_OUT,
-      BUS_READ_ENABLE_OUT(1)     => dbuf_read_enable,
-      BUS_READ_ENABLE_OUT(2)     => tbuf_read_enable,
-      BUS_READ_ENABLE_OUT(3)     => read_enable(3),
-      BUS_READ_ENABLE_OUT(4)     => read_enable(4),
-      BUS_READ_ENABLE_OUT(5)     => read_enable(5),
-      BUS_READ_ENABLE_OUT(6)     => stat_buffer_read,
-      BUS_WRITE_ENABLE_OUT(0)    => BUS_WRITE_ENABLE_OUT,
-      BUS_WRITE_ENABLE_OUT(1)    => dummy(0),
-      BUS_WRITE_ENABLE_OUT(2)    => write_enable(2),
-      BUS_WRITE_ENABLE_OUT(3)    => write_enable(3),
-      BUS_WRITE_ENABLE_OUT(4)    => write_enable(4),
-      BUS_WRITE_ENABLE_OUT(5)    => write_enable(5),
-      BUS_WRITE_ENABLE_OUT(6)    => write_enable(6),
-      BUS_DATA_OUT(31 downto 0)  => BUS_DATA_OUT,
-      BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2),
-      BUS_DATA_OUT(95 downto 64) => dummy(65 downto 34),
-      BUS_DATA_OUT(191 downto 96) => dummy(191 downto 96),
-      BUS_DATA_OUT(223 downto 192)=> dummy(291 downto 260),
-      BUS_ADDR_OUT(15 downto 0)  => BUS_ADDR_OUT,
-      BUS_ADDR_OUT(19 downto 16) => dbuf_addr,
-      BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66),
-      BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78),
-      BUS_ADDR_OUT(95 downto 48) => dummy(242 downto 195),
-      BUS_ADDR_OUT(100 downto 96)=> stat_buffer_address,
-      BUS_ADDR_OUT(111 downto 101)=> dummy(259 downto 249),
-      BUS_TIMEOUT_OUT(0)         => BUS_TIMEOUT_OUT,
-      BUS_TIMEOUT_OUT(1)         => dummy(94),
-      BUS_TIMEOUT_OUT(2)         => dummy(95),
-      BUS_TIMEOUT_OUT(3)         => dummy(192),
-      BUS_TIMEOUT_OUT(4)         => dummy(193),
-      BUS_TIMEOUT_OUT(5)         => dummy(194),
-      BUS_TIMEOUT_OUT(6)         => dummy(243),
-      BUS_DATA_IN(31 downto 0)   => BUS_DATA_IN,
-      BUS_DATA_IN(63 downto 32)  => dbuf_data_in,
-      BUS_DATA_IN(95 downto 64)  => stat_header_buffer_level,
-      BUS_DATA_IN(191 downto 96) => stat_handler_i(95 downto 0),
-      BUS_DATA_IN(223 downto 192)=> stat_buffer_i,
-      BUS_DATAREADY_IN(0)        => BUS_DATAREADY_IN,
-      BUS_DATAREADY_IN(1)        => dbuf_dataready,
-      BUS_DATAREADY_IN(2)        => tbuf_dataready,
-      BUS_DATAREADY_IN(3)        => last_read_enable(3),
-      BUS_DATAREADY_IN(4)        => last_read_enable(4),
-      BUS_DATAREADY_IN(5)        => last_read_enable(5),
-      BUS_DATAREADY_IN(6)        => stat_buffer_ready,
-      BUS_WRITE_ACK_IN(0)        => BUS_WRITE_ACK_IN,
-      BUS_WRITE_ACK_IN(1)        => '0',
-      BUS_WRITE_ACK_IN(2)        => '0',
-      BUS_WRITE_ACK_IN(3)        => '0',
-      BUS_WRITE_ACK_IN(4)        => '0',
-      BUS_WRITE_ACK_IN(5)        => '0',
-      BUS_WRITE_ACK_IN(6)        => '0',
-      BUS_NO_MORE_DATA_IN(0)     => BUS_NO_MORE_DATA_IN,
-      BUS_NO_MORE_DATA_IN(1)     => '0',
-      BUS_NO_MORE_DATA_IN(2)     => '0',
-      BUS_NO_MORE_DATA_IN(3)     => '0',
-      BUS_NO_MORE_DATA_IN(4)     => '0',
-      BUS_NO_MORE_DATA_IN(5)     => '0',
-      BUS_NO_MORE_DATA_IN(6)     => '0',
-      BUS_UNKNOWN_ADDR_IN(0)     => BUS_UNKNOWN_ADDR_IN,
-      BUS_UNKNOWN_ADDR_IN(1)     => dbuf_unknown_addr,
-      BUS_UNKNOWN_ADDR_IN(2)     => last_write_enable(2),
-      BUS_UNKNOWN_ADDR_IN(3)     => last_write_enable(3),
-      BUS_UNKNOWN_ADDR_IN(4)     => last_write_enable(4),
-      BUS_UNKNOWN_ADDR_IN(5)     => last_write_enable(5),
-      BUS_UNKNOWN_ADDR_IN(6)     => stat_buffer_unknown
-      );
-
-  proc_ack_strobes : process(CLK)
-    begin
-      if rising_edge(CLK) then
-        last_write_enable <= write_enable;
-        last_read_enable  <= read_enable;
-      end if;
-    end process;
-
-
----------------------------------------------------------------------------
--- Data and IPU Handler
----------------------------------------------------------------------------
-
-  THE_HANDLER_TRIGGER_DATA : handler_trigger_and_data
-    generic map(
-      DATA_INTERFACE_NUMBER      => DATA_INTERFACE_NUMBER,
-      DATA_BUFFER_DEPTH          => DATA_BUFFER_DEPTH,
-      DATA_BUFFER_WIDTH          => DATA_BUFFER_WIDTH,
-      DATA_BUFFER_FULL_THRESH    => DATA_BUFFER_FULL_THRESH,
-      TRG_RELEASE_AFTER_DATA     => TRG_RELEASE_AFTER_DATA,
-      HEADER_BUFFER_DEPTH        => HEADER_BUFFER_DEPTH,
-      HEADER_BUFFER_FULL_THRESH  => HEADER_BUFFER_FULL_THRESH
-      )
-    port map(
-      CLOCK                      => CLK,
-      RESET                      => RESET,
-      RESET_IPU                  => reset_ipu_i,
-      --LVL1 channel
-      LVL1_VALID_TRIGGER_IN      => lvl1_valid_i,
-      LVL1_INT_TRG_NUMBER_IN     => lvl1_int_trg_number_i,
-      LVL1_TRG_DATA_VALID_IN     => lvl1_data_valid_i,
-      LVL1_TRG_TYPE_IN           => lvl1_type_i,
-      LVL1_TRG_NUMBER_IN         => lvl1_number_i,
-      LVL1_TRG_CODE_IN           => lvl1_code_i,
-      LVL1_TRG_INFORMATION_IN    => lvl1_information_i,
-      LVL1_ERROR_PATTERN_OUT     => lvl1_error_pattern_i,
-      LVL1_TRG_RELEASE_OUT       => lvl1_release_i,
-
-      --IPU channel
-      IPU_NUMBER_IN              => ipu_number_i,
-      IPU_INFORMATION_IN         => ipu_information_i,
-      IPU_READOUT_TYPE_IN        => ipu_readout_type_i,
-      IPU_START_READOUT_IN       => ipu_start_readout_i,
-      IPU_DATA_OUT               => ipu_data_i,
-      IPU_DATAREADY_OUT          => ipu_dataready_i,
-      IPU_READOUT_FINISHED_OUT   => ipu_readout_finished_i,
-      IPU_READ_IN                => ipu_read_i,
-      IPU_LENGTH_OUT             => ipu_length_i,
-      IPU_ERROR_PATTERN_OUT      => ipu_error_pattern_i,
-
-      --FEE Input
-      FEE_TRG_RELEASE_IN         => FEE_TRG_RELEASE_IN,
-      FEE_TRG_STATUSBITS_IN      => FEE_TRG_STATUSBITS_IN,
-      FEE_DATA_IN                => FEE_DATA_IN,
-      FEE_DATA_WRITE_IN          => FEE_DATA_WRITE_IN,
-      FEE_DATA_FINISHED_IN       => FEE_DATA_FINISHED_IN,
-      FEE_DATA_ALMOST_FULL_OUT   => FEE_DATA_ALMOST_FULL_OUT,
-
-      TMG_TRG_ERROR_IN           => tmg_trg_error_i,
-      --Status Registers
-      STAT_DATA_BUFFER_LEVEL     => stat_data_buffer_level,
-      STAT_HEADER_BUFFER_LEVEL   => stat_header_buffer_level,
-      STATUS_OUT                 => stat_handler_i,
-      TIMER_TICKS_IN             => time_ticks_i,
-      STATISTICS_DATA_OUT        => stat_buffer_i,
-      STATISTICS_UNKNOWN_OUT     => stat_buffer_unknown,
-      STATISTICS_READY_OUT       => stat_buffer_ready,
-      STATISTICS_READ_IN         => stat_buffer_read,
-      STATISTICS_ADDR_IN         => stat_buffer_address,
-
-
-      --Debug
-      DEBUG_DATA_HANDLER_OUT     => debug_data_handler_i,
-      DEBUG_IPU_HANDLER_OUT      => debug_ipu_handler_i
-
-      );
-
-  reset_ipu_i                  <= RESET or common_ctrl_reg_i(2);
-  lvl1_valid_i                 <= lvl1_valid_timing_i or lvl1_valid_notiming_i or lvl1_invalid_i;
-  STAT_DEBUG_IPU_HANDLER_OUT   <= debug_ipu_handler_i;
-  STAT_DEBUG_DATA_HANDLER_OUT  <= debug_data_handler_i;
-  tmg_trg_error_i              <= int_lvl1_missing_tmg_trg or int_lvl1_spurious_trg or int_lvl1_timeout_detected or int_multiple_trg
-                                  or int_spike_detected or int_lvl1_long_trg;
-
----------------------------------------------------------------------------
--- Connect Status Registers
----------------------------------------------------------------------------
-  proc_buf_status : process(CLK)
-    variable tmp : integer range 0 to 15;
-    begin
-      if rising_edge(CLK) then
-        dbuf_unknown_addr        <= '0';
-        dbuf_dataready           <= '0';
-        tbuf_dataready           <= tbuf_read_enable;
-        if dbuf_read_enable = '1' then
-          tmp := to_integer(unsigned(dbuf_addr));
-          if tmp < DATA_INTERFACE_NUMBER then
-            dbuf_data_in         <= stat_data_buffer_level(tmp*32+31 downto tmp*32);
-            dbuf_dataready       <= '1';
-          else
-            dbuf_data_in         <= (others => '0');
-            dbuf_unknown_addr    <= '1';
-          end if;
-        end if;
-      end if;
-    end process;
-
-
-
----------------------------------------------------------------------------
--- Connect I/O Ports
----------------------------------------------------------------------------
-
-  TRG_SPIKE_DETECTED_OUT   <= int_spike_detected;
-  TRG_SPURIOUS_TRG_OUT     <= int_lvl1_spurious_trg;
-  TRG_TIMEOUT_DETECTED_OUT <= int_lvl1_timeout_detected;
-  TRG_MULTIPLE_TRG_OUT     <= int_multiple_trg;
-  TRG_MISSING_TMG_TRG_OUT  <= int_lvl1_missing_tmg_trg;
-
-  LVL1_TRG_DATA_VALID_OUT        <= lvl1_data_valid_i;
-  LVL1_VALID_TIMING_TRG_OUT      <= lvl1_valid_timing_i;
-  LVL1_VALID_NOTIMING_TRG_OUT    <= lvl1_valid_notiming_i;
-  LVL1_INVALID_TRG_OUT           <= lvl1_invalid_i;
-  LVL1_TRG_TYPE_OUT              <= lvl1_type_i;
-  LVL1_TRG_NUMBER_OUT            <= lvl1_number_i;
-  LVL1_TRG_CODE_OUT              <= lvl1_code_i;
-  LVL1_TRG_INFORMATION_OUT       <= lvl1_information_i;
-  LVL1_INT_TRG_NUMBER_OUT        <= lvl1_int_trg_number_i;
-
-  REGIO_COMMON_CTRL_REG_OUT      <= common_ctrl_reg_i;
-  REGIO_COMMON_STAT_STROBE_OUT   <= common_stat_strobe_i;
-  REGIO_COMMON_CTRL_STROBE_OUT   <= common_ctrl_strobe_i;
-  REGIO_CTRL_REG_OUT             <= ctrl_reg_i;
-  REGIO_STAT_STROBE_OUT          <= stat_strobe_i;
-  REGIO_CTRL_STROBE_OUT          <= ctrl_strobe_i;
-
-  stat_reg_i                     <= REGIO_STAT_REG_IN;
-
-  TIME_GLOBAL_OUT                <= time_global_i;
-  TIME_LOCAL_OUT                 <= time_local_i;
-  TIME_SINCE_LAST_TRG_OUT        <= time_since_last_trg_i;
-  TIME_TICKS_OUT                 <= time_ticks_i;
-
-  process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i,common_ctrl_reg_i, common_stat_reg_i)
-    begin
-      common_stat_reg_i(8 downto 0) <= REGIO_COMMON_STAT_REG_IN(8 downto 0);
-      common_stat_reg_i(47 downto 12) <= REGIO_COMMON_STAT_REG_IN(47 downto 12);
-      common_stat_reg_i(6)       <= debug_ipu_handler_i(15) or REGIO_COMMON_STAT_REG_IN(6);
-
-      if rising_edge(CLK) then
-        if common_ctrl_reg_i(4) = '1' then 
-          common_stat_reg_i(11 downto 9) <= "000";
-        else 
-          common_stat_reg_i(9)       <= debug_ipu_handler_i(12) or REGIO_COMMON_STAT_REG_IN(9) or common_stat_reg_i(9);
-          common_stat_reg_i(10)      <= debug_ipu_handler_i(13) or REGIO_COMMON_STAT_REG_IN(10) or common_stat_reg_i(10);
-          common_stat_reg_i(11)      <= debug_ipu_handler_i(14) or REGIO_COMMON_STAT_REG_IN(11) or common_stat_reg_i(11);      
-        end if;
-      end if;
-      common_stat_reg_i(159 downto 64) <= REGIO_COMMON_STAT_REG_IN(159 downto 64);
-    end process;
-
-  process(CLK)
-    begin
-      if rising_edge(CLK) then
-        if ipu_start_readout_i = '1' then
-          common_stat_reg_i(63 downto 48) <= ipu_number_i;
-        end if;
-      end if;
-    end process;
-
-end architecture;
\ No newline at end of file
diff --git a/hub_SODA/sources/HUB_16to8_SODA.vhd b/hub_SODA/sources/HUB_16to8_SODA.vhd
new file mode 100644
index 0000000..f6977e6
--- /dev/null
+++ b/hub_SODA/sources/HUB_16to8_SODA.vhd
@@ -0,0 +1,180 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   09-07-2015
+-- Module Name:   HUB_16to8_SODA
+-- Description:   16 bits to 8 bits conversion and SODA
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- HUB_16to8_SODA
+-- Read from fifo with 16 bits, convert to 8 bits and add idles and SODA K-character
+-- If no data is available Idles (data 50 and k-char BC) are put on the output.
+-- SODA signals (DLM) are passed on directly (highest priority).
+--
+-- Library
+--
+-- Generics:
+-- 
+-- Inputs:
+--     clock : clock synchronous with SODA
+--     reset : reset : k-char FE are sent
+--     fifo_data : 16-bits input data from fifo
+--     fifo_empty : 16-bits input fifo empty signal
+--     TX_DLM : transmit SODA character
+--     TX_DLM_WORD : SODA character to be transmitted
+-- 
+-- Outputs:
+--     fifo_read : read signal for 16-bits input data fifo
+--     data_out : 16-bits output data
+--     char_is_k : corresponding byte in 16-bits output data is K-character
+--     error : error in DLM or read fifo
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+
+entity HUB_16to8_SODA is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		fifo_data               : in std_logic_vector(15 downto 0);
+		fifo_empty              : in std_logic;
+		fifo_read               : out std_logic;
+		TX_DLM                  : in std_logic;
+		TX_DLM_WORD             : in std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(7 downto 0);
+		char_is_k               : out std_logic;
+		error                   : out std_logic
+	);
+end HUB_16to8_SODA;
+
+architecture Behavioral of HUB_16to8_SODA is
+
+signal reset_S                  : std_logic;
+signal fifo_read_S              : std_logic;
+signal fifo_databuf_S           : std_logic_vector(15 downto 0);
+signal data_out_S               : std_logic_vector(7 downto 0);
+signal char_is_k_S              : std_logic;
+
+signal fifo_buffilled_S         : std_logic := '0';
+signal fifo_read_after1clk_S    : std_logic := '0';
+signal TX_DLM_S                 : std_logic;
+
+signal second_reset_S           : std_logic;
+signal second_idle_S            : std_logic;
+signal second_data_S            : std_logic;
+signal error_S                  : std_logic;
+
+
+begin
+
+process (clock)
+begin
+	if rising_edge(clock) then
+		data_out <= data_out_S;
+		char_is_k <= char_is_k_S;
+		error <= error_S;
+	end if;
+end process;
+fifo_read <= fifo_read_S;
+
+fifo_read_S <= '1' when (fifo_empty='0') 
+		and (TX_DLM='0')
+		and (fifo_read_after1clk_S='0')
+		and ((fifo_buffilled_S='0') or (second_data_S='1'))
+		and (not ((fifo_buffilled_S='1') and (TX_DLM_S='1')))
+		and (reset_S='0')
+	else '0';
+	
+process (clock)
+begin
+	if rising_edge(clock) then
+		fifo_read_after1clk_S <= fifo_read_S;
+		if fifo_read_after1clk_S='1' then
+			fifo_databuf_S <= fifo_data;
+		end if;
+		TX_DLM_S <= TX_DLM;
+		reset_S <= reset;
+	end if;
+end process;
+
+process (clock)
+begin
+	if rising_edge(clock) then
+		error_S <= '0';
+		if (TX_DLM_S='1') then
+			data_out_S <= TX_DLM_WORD;
+			char_is_k_S <= '0';
+			if fifo_read_after1clk_S='1' then
+				fifo_buffilled_S <= '1';
+			end if;
+			if TX_DLM='1' then
+				error_S <= '1';
+			end if;
+		elsif (TX_DLM='1') then
+			data_out_S <= x"DC";
+			char_is_k_S <= '1';
+			if fifo_read_after1clk_S='1' then
+				fifo_buffilled_S <= '1';
+			end if;
+		elsif (second_reset_S='1') then
+			data_out_S <= x"FE";
+			char_is_k_S <= '1';
+			second_reset_S <= '0';
+		elsif (second_idle_S='1') then
+			data_out_S <= x"50";
+			char_is_k_S <= '0';
+			second_idle_S <= '0';
+			if fifo_read_after1clk_S='1' then
+				fifo_buffilled_S <= '1';
+			end if;
+		elsif (second_data_S='1') then
+			data_out_S <= fifo_databuf_S(15 downto 8);
+			char_is_k_S <= '0';
+			second_data_S <= '0';
+			if fifo_read_after1clk_S='1' then
+				fifo_buffilled_S <= '1';
+			else
+				fifo_buffilled_S <= '0';
+			end if;
+		elsif reset_S = '1' then
+			data_out_S <= x"FE";
+			char_is_k_S <= '1';
+			second_reset_S <= '1';
+			fifo_buffilled_S <= '0';
+			second_idle_S <= '0';
+			second_data_S <= '0';
+		elsif (fifo_buffilled_S='1') then
+			data_out_S <= fifo_databuf_S(7 downto 0);
+			char_is_k_S <= '0';
+			second_data_S <= '1';
+			if fifo_read_after1clk_S='1' then
+				error_S <= '1';
+			end if;
+		elsif (fifo_read_after1clk_S='1') then
+			data_out_S <= fifo_data(7 downto 0);
+			char_is_k_S <= '0';
+			second_data_S <= '1';
+			fifo_buffilled_S <= '1';
+		else
+			data_out_S <= x"BC";
+			char_is_k_S <= '1';
+			second_idle_S <= '1';
+			if fifo_read_after1clk_S='1' then
+				fifo_buffilled_S <= '1';
+			end if;
+		end if;
+	end if;
+end process;
+
+
+
+end Behavioral;
+
+
diff --git a/hub_SODA/sources/HUB_8to16_SODA.vhd b/hub_SODA/sources/HUB_8to16_SODA.vhd
new file mode 100644
index 0000000..daa1865
--- /dev/null
+++ b/hub_SODA/sources/HUB_8to16_SODA.vhd
@@ -0,0 +1,140 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   09-07-2015
+-- Module Name:   HUB_8to16_SODA
+-- Description:   16 bits to 8 bits conversion and SODA
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.std_logic_unsigned.all ;
+USE ieee.std_logic_arith.all ;
+
+----------------------------------------------------------------------------------
+-- HUB_8to16_SODA
+-- Convert 8-bits data from fiber and convert to 16 bits plus two K-character
+-- SODA signals (DLM) are passed on directly (highest priority).
+--
+-- Library
+--
+-- Generics:
+-- 
+-- Inputs:
+--     clock : clock synchronous with SODA
+--     reset : reset : k-char FE are sent
+--     data_in : 8-bits input data from fiber
+--     char_is_k : data from fiber is k-character
+--     fifo_full : full signal from connected fifo: should not 
+-- 
+-- Outputs:
+--     fifo_data : 16-bits output data plus 2 bits for k-character indication 
+--     fifo_write : write signal for connected fifo
+--     RX_DLM : receive SODA character
+--     RX_DLM_WORD : received SODA character
+--     error : error in DLM or read fifo
+-- 
+-- Components:
+--
+----------------------------------------------------------------------------------
+
+
+entity HUB_8to16_SODA is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		char_is_k               : in std_logic;
+		fifo_data               : out std_logic_vector(17 downto 0);
+		fifo_full               : in std_logic;
+		fifo_write              : out std_logic;
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		error                   : out std_logic
+	);
+end HUB_8to16_SODA;
+
+architecture Behavioral of HUB_8to16_SODA is
+
+signal data_in_S                : std_logic_vector(7 downto 0);
+signal char_is_k_S              : std_logic;
+
+signal fifo_write_S             : std_logic;
+signal fifo_data_S              : std_logic_vector(17 downto 0);
+signal data_buf_S               : std_logic_vector(7 downto 0);
+signal char_is_k_buf_S          : std_logic;
+
+signal RX_DLM_WORD_S            : std_logic_vector(7 downto 0);
+signal RX_DLM_S                 : std_logic;
+
+signal expect_dlm_word_S        : std_logic := '0';
+signal expect_second_idle_S     : std_logic;
+signal expect_second_data_S     : std_logic;
+signal error_S                  : std_logic;
+
+
+begin
+
+RX_DLM_WORD <= RX_DLM_WORD_S;
+RX_DLM  <= RX_DLM_S;
+
+process (clock)
+begin
+	if rising_edge(clock) then
+		data_in_S <= data_in;
+		char_is_k_S <= char_is_k;
+		fifo_data <= fifo_data_S;
+		fifo_write <= fifo_write_S;
+		error <= error_S;
+	end if;
+end process;
+
+process (clock)
+begin
+	if rising_edge(clock) then
+		error_S <= '0';
+		RX_DLM_S <= '0';
+		fifo_write_S <= '0';
+		if expect_dlm_word_S='1' then
+			expect_dlm_word_S <= '0';
+			if (char_is_k_S='0') then
+				RX_DLM_WORD_S <= data_in_S;
+				RX_DLM_S <= '1';
+			else
+				error_S <= '1';
+			end if;
+		elsif (char_is_k_S='1') and (data_in_S=x"DC") then
+			expect_dlm_word_S <= '1';
+		elsif expect_second_idle_S='1' then
+			expect_second_idle_S <= '0';
+			expect_second_data_S <= '0';
+			if (char_is_k_S='1') or (data_in_S/=x"50") then
+				error_S <= '1';
+			else
+--//				fifo_data_S <= "01" & x"50BC";
+--//				fifo_write_S <= '1';
+--//				if fifo_full='1' then
+--//					error_S <= '1';
+--//				end if;
+			end if;
+		elsif (char_is_k_S='1') and (data_in_S=x"BC") then
+			expect_second_idle_S <= '1';
+		elsif expect_second_data_S='1' then
+			expect_second_data_S <= '0';
+			fifo_data_S <= char_is_k_S & char_is_k_buf_S & data_in_S & data_buf_S;
+			fifo_write_S <= '1';
+			if fifo_full='1' then
+				error_S <= '1';
+			end if;
+		else 
+			expect_second_data_S <= '1';
+			data_buf_S <= data_in_S;
+			char_is_k_buf_S <= char_is_k_S;
+		end if;
+	end if;
+end process;
+
+
+
+end Behavioral;
+
+
diff --git a/hub_SODA/sources/HUB_SODA_clockcrossing.vhd b/hub_SODA/sources/HUB_SODA_clockcrossing.vhd
new file mode 100644
index 0000000..4cecf7d
--- /dev/null
+++ b/hub_SODA/sources/HUB_SODA_clockcrossing.vhd
@@ -0,0 +1,125 @@
+----------------------------------------------------------------------------------
+-- Company:       KVI/RUG/Groningen University
+-- Engineer:      Peter Schakel
+-- Create Date:   22-05-2015
+-- Module Name:   HUB_SODA_clockcrossing
+-- Description:   Transfer SODA signals to different clock domain
+-- Modifications:
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library work;
+
+----------------------------------------------------------------------------------
+-- HUB_SODA_clockcrossing
+-- Transfer SODA signals to different clock domain
+--
+-- Library
+--     work.gtpBufLayer : for GTP/GTX/serdes constants
+--
+-- Generics:
+-- 
+-- Inputs:
+--     write_clock : clock for DLM input
+--     read_clock : clock for DLM output
+--     DLM_in : SODA DLM active input
+--     DLM_WORD_in : 8-bits SODA DLM data (valid one clock cycle after DLM_in)
+-- 
+-- Outputs:
+--     DLM_out : SODA DLM active output
+--     RX_DLM_WORD : 8-bits SODA DLM data
+--     error : error : fifo full
+-- 
+-- Components:
+--     async_fifo_16x8 : 8-bits asynchronous fifo
+--
+----------------------------------------------------------------------------------
+
+
+entity HUB_SODA_clockcrossing is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		DLM_in                  : in std_logic;
+		DLM_WORD_in             : in std_logic_vector(7 downto 0);
+		DLM_out                 : out std_logic;
+		DLM_WORD_out            : out std_logic_vector(7 downto 0);
+		error                   : out std_logic
+	);
+end HUB_SODA_clockcrossing;
+
+architecture Behavioral of HUB_SODA_clockcrossing is
+
+component async_fifo_16x8
+	port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(7 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(7 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic);
+end component;
+
+
+
+signal DLM_in_S                 : std_logic;
+signal DLM_WORD_out_S           : std_logic_vector(7 downto 0);
+signal fifo_read_S              : std_logic;
+signal fifo_empty_S             : std_logic;
+signal fifo_read_aftr1clk_S     : std_logic := '0';
+signal DLM_reading_busy0_S      : std_logic := '0';
+signal DLM_reading_busy1_S      : std_logic := '0';
+
+begin
+
+process(write_clock)
+begin
+	if rising_edge(write_clock) then
+		DLM_in_S <= DLM_in;
+	end if;
+end process; 
+
+syncSODAfifo: async_fifo_16x8 port map(
+		rst => '0',
+		wr_clk => write_clock,
+		rd_clk => read_clock,
+		din => DLM_WORD_in,
+		wr_en => DLM_in_S,
+		rd_en => fifo_read_S,
+		dout => DLM_WORD_out_S,
+		full => error,
+		empty => fifo_empty_S);
+
+fifo_read_S <= '1' when (DLM_reading_busy0_S='1') and (DLM_reading_busy1_S='1') and (fifo_empty_S='0') and (fifo_read_aftr1clk_S='0') else '0';
+
+process(read_clock)
+begin
+	if rising_edge(read_clock) then
+		DLM_WORD_out <= DLM_WORD_out_S;
+		DLM_out <= fifo_read_aftr1clk_S;
+	end if;
+end process; 
+
+process(read_clock)
+begin
+	if rising_edge(read_clock) then
+		if DLM_reading_busy0_S='0' then
+			if fifo_empty_S='0' then
+				DLM_reading_busy0_S <= '1';
+			end if;
+		else
+			if fifo_empty_S='1' then
+				DLM_reading_busy0_S <= '0';
+			end if;
+		end if;
+		fifo_read_aftr1clk_S <= fifo_read_S;
+		DLM_reading_busy1_S <= DLM_reading_busy0_S;
+	end if;
+end process;  
+
+end Behavioral;
+
diff --git a/hub_SODA/sources/HUB_posedge_to_pulse.vhd b/hub_SODA/sources/HUB_posedge_to_pulse.vhd
new file mode 100644
index 0000000..0f5a9ee
--- /dev/null
+++ b/hub_SODA/sources/HUB_posedge_to_pulse.vhd
@@ -0,0 +1,72 @@
+-----------------------------------------------------------------------------------
+-- HUB_posedge_to_pulse
+--		Makes pulse with duration 1 clock-cycle from positive edge
+--	
+-- inputs
+--		clock_in : clock input for input signal
+--		clock_out : clock input to synchronize to
+--		en_clk : clock enable
+--		signal_in : rising edge of this signal will result in pulse
+--
+--	output
+--		pulse : pulse output : one clock cycle '1'
+--
+-----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.STD_LOGIC_ARITH.all;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+
+entity HUB_posedge_to_pulse is
+	port (
+		clock_in        : in  std_logic;
+		clock_out       : in  std_logic;
+		en_clk          : in  std_logic;
+		signal_in       : in  std_logic;
+		pulse           : out std_logic
+	);
+end HUB_posedge_to_pulse;
+
+architecture behavioral of HUB_posedge_to_pulse is
+
+  signal resetff	: std_logic := '0';
+  signal last_signal_in	: std_logic := '0';
+  signal qff	: std_logic := '0'; 
+  signal qff1	: std_logic := '0'; 
+  signal qff2	: std_logic := '0'; 
+  signal qff3	: std_logic := '0'; 
+begin  
+
+process (clock_in)
+begin
+	if rising_edge(clock_in) then
+		if resetff='1' then
+			qff <= '0';
+		elsif (en_clk='1') and ((signal_in='1') and (qff='0') and (last_signal_in='0')) then 
+			qff <= '1';
+		else
+			qff <= qff;
+		end if;
+		last_signal_in <= signal_in;
+	end if;
+end process;
+resetff <= qff2;
+
+process (clock_out)
+begin
+	if rising_edge(clock_out) then
+		if qff3='0' and qff2='1' then 
+			pulse <= '1'; 
+		else 
+			pulse <= '0';
+		end if;
+		qff3 <= qff2;
+		qff2 <= qff1;
+		qff1 <= qff;
+	end if;
+end process; 
+
+
+end behavioral;
+
diff --git a/hub_SODA/sources/lattice/async_fifo_16x8.vhd b/hub_SODA/sources/lattice/async_fifo_16x8.vhd
new file mode 100644
index 0000000..163de1a
--- /dev/null
+++ b/hub_SODA/sources/lattice/async_fifo_16x8.vhd
@@ -0,0 +1,51 @@
+library IEEE;
+use IEEE.std_logic_1164.ALL;
+use IEEE.std_logic_ARITH.ALL;
+use IEEE.std_logic_UNSIGNED.ALL;
+
+entity async_fifo_16x8 is
+port (
+		rst                     : in std_logic;
+		wr_clk                  : in std_logic;
+		rd_clk                  : in std_logic;
+		din                     : in std_logic_vector(7 downto 0);
+		wr_en                   : in std_logic;
+		rd_en                   : in std_logic;
+		dout                    : out std_logic_vector(7 downto 0);
+		full                    : out std_logic;
+		empty                   : out std_logic
+	);
+end async_fifo_16x8;
+
+architecture Behavioral of async_fifo_16x8 is
+
+component async_fifo_16x8_ecp3 is
+    port (
+        Data: in  std_logic_vector(7 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(7 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end component;
+
+begin
+
+async_fifo_16x8_ecp3_1: async_fifo_16x8_ecp3 port map(
+        Data => din,
+        WrClock => wr_clk,
+        RdClock => rd_clk,
+        WrEn => wr_en,
+        RdEn => rd_en,
+        Reset => rst,
+        RPReset => rst,
+        Q => dout,
+        Empty => empty,
+        Full => full);
+
+end Behavioral;
+
diff --git a/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.edn b/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.edn
new file mode 100644
index 0000000..00f9881
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.edn
@@ -0,0 +1,1375 @@
+(edif async_fifo_16x8_ecp3
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timestamp 2015 7 14 16 15 57)
+      (program "SCUBA" (version "Diamond (64-bit) 3.2.0.134"))))
+      (comment "C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_16x8_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -pfu_fifo -depth 8 -width 8 -depth 8 -rdata_width 8 -no_enable -pe -1 -pf -1 ")
+  (library ORCLIB
+    (edifLevel 0)
+    (technology
+      (numberDefinition))
+    (cell AGEB2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port CI
+            (direction INPUT))
+          (port GE
+            (direction OUTPUT)))))
+    (cell AND2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell CU2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port CI
+            (direction INPUT))
+          (port PC0
+            (direction INPUT))
+          (port PC1
+            (direction INPUT))
+          (port CO
+            (direction OUTPUT))
+          (port NC0
+            (direction OUTPUT))
+          (port NC1
+            (direction OUTPUT)))))
+    (cell FADD2B
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A0
+            (direction INPUT))
+          (port A1
+            (direction INPUT))
+          (port B0
+            (direction INPUT))
+          (port B1
+            (direction INPUT))
+          (port CI
+            (direction INPUT))
+          (port COUT
+            (direction OUTPUT))
+          (port S0
+            (direction OUTPUT))
+          (port S1
+            (direction OUTPUT)))))
+    (cell FD1P3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1P3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port SP
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3BX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port PD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell FD1S3DX
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port D
+            (direction INPUT))
+          (port CK
+            (direction INPUT))
+          (port CD
+            (direction INPUT))
+          (port Q
+            (direction OUTPUT)))))
+    (cell INV
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell OR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell ROM16X1A
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port AD3
+            (direction INPUT))
+          (port AD2
+            (direction INPUT))
+          (port AD1
+            (direction INPUT))
+          (port AD0
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT)))))
+    (cell DPR16X4C
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port DI0
+            (direction INPUT))
+          (port DI1
+            (direction INPUT))
+          (port DI2
+            (direction INPUT))
+          (port DI3
+            (direction INPUT))
+          (port WCK
+            (direction INPUT))
+          (port WRE
+            (direction INPUT))
+          (port RAD0
+            (direction INPUT))
+          (port RAD1
+            (direction INPUT))
+          (port RAD2
+            (direction INPUT))
+          (port RAD3
+            (direction INPUT))
+          (port WAD0
+            (direction INPUT))
+          (port WAD1
+            (direction INPUT))
+          (port WAD2
+            (direction INPUT))
+          (port WAD3
+            (direction INPUT))
+          (port DO0
+            (direction OUTPUT))
+          (port DO1
+            (direction OUTPUT))
+          (port DO2
+            (direction OUTPUT))
+          (port DO3
+            (direction OUTPUT)))))
+    (cell VHI
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell VLO
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port Z
+            (direction OUTPUT)))))
+    (cell XOR2
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port A
+            (direction INPUT))
+          (port B
+            (direction INPUT))
+          (port Z
+            (direction OUTPUT)))))
+    (cell async_fifo_16x8_ecp3
+      (cellType GENERIC)
+      (view view1
+        (viewType NETLIST)
+        (interface
+          (port (array (rename Data "Data(7:0)") 8)
+            (direction INPUT))
+          (port WrClock
+            (direction INPUT))
+          (port RdClock
+            (direction INPUT))
+          (port WrEn
+            (direction INPUT))
+          (port RdEn
+            (direction INPUT))
+          (port Reset
+            (direction INPUT))
+          (port RPReset
+            (direction INPUT))
+          (port (array (rename Q "Q(7:0)") 8)
+            (direction OUTPUT))
+          (port Empty
+            (direction OUTPUT))
+          (port Full
+            (direction OUTPUT)))
+        (property NGD_DRC_MASK (integer 1))
+        (contents
+          (instance AND2_t8
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_1
+            (viewRef view1 
+              (cellRef INV)))
+          (instance AND2_t7
+            (viewRef view1 
+              (cellRef AND2)))
+          (instance INV_0
+            (viewRef view1 
+              (cellRef INV)))
+          (instance OR2_t6
+            (viewRef view1 
+              (cellRef OR2)))
+          (instance XOR2_t5
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t4
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t3
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t2
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t1
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance XOR2_t0
+            (viewRef view1 
+              (cellRef XOR2)))
+          (instance LUT4_10
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x8000")))
+          (instance LUT4_9
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_8
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_7
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_6
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_5
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_4
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x6996")))
+          (instance LUT4_3
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x0410")))
+          (instance LUT4_2
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x1004")))
+          (instance LUT4_1
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x0140")))
+          (instance LUT4_0
+            (viewRef view1 
+              (cellRef ROM16X1A))
+            (property initval
+              (string "0x4001")))
+          (instance FF_49
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_48
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_47
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_46
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_45
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_44
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_43
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_42
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_41
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_40
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_39
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_38
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_37
+            (viewRef view1 
+              (cellRef FD1P3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_36
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_35
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_34
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_33
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_32
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_31
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_30
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_29
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_28
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_27
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_26
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_25
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_24
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_23
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_22
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_21
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_20
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_19
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_18
+            (viewRef view1 
+              (cellRef FD1P3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_17
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_16
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_15
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_14
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_13
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_12
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_11
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_10
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_9
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_8
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_7
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_6
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_5
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_4
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_3
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_2
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_1
+            (viewRef view1 
+              (cellRef FD1S3BX))
+            (property GSR
+              (string "ENABLED")))
+          (instance FF_0
+            (viewRef view1 
+              (cellRef FD1S3DX))
+            (property GSR
+              (string "ENABLED")))
+          (instance w_gctr_cia
+            (viewRef view1 
+              (cellRef FADD2B)))
+          (instance w_gctr_0
+            (viewRef view1 
+              (cellRef CU2)))
+          (instance w_gctr_1
+            (viewRef view1 
+              (cellRef CU2)))
+          (instance scuba_vhi_inst
+            (viewRef view1 
+              (cellRef VHI)))
+          (instance r_gctr_cia
+            (viewRef view1 
+              (cellRef FADD2B)))
+          (instance r_gctr_0
+            (viewRef view1 
+              (cellRef CU2)))
+          (instance r_gctr_1
+            (viewRef view1 
+              (cellRef CU2)))
+          (instance empty_cmp_ci_a
+            (viewRef view1 
+              (cellRef FADD2B)))
+          (instance empty_cmp_0
+            (viewRef view1 
+              (cellRef AGEB2)))
+          (instance empty_cmp_1
+            (viewRef view1 
+              (cellRef AGEB2)))
+          (instance a0
+            (viewRef view1 
+              (cellRef FADD2B)))
+          (instance full_cmp_ci_a
+            (viewRef view1 
+              (cellRef FADD2B)))
+          (instance full_cmp_0
+            (viewRef view1 
+              (cellRef AGEB2)))
+          (instance full_cmp_1
+            (viewRef view1 
+              (cellRef AGEB2)))
+          (instance a1
+            (viewRef view1 
+              (cellRef FADD2B)))
+          (instance fifo_pfu_0_0
+            (viewRef view1 
+              (cellRef DPR16X4C))
+            (property MEM_INIT_FILE
+              (string "(0-7)(0-3)"))
+            (property MEM_LPC_FILE
+              (string "async_fifo_16x8_ecp3.lpc"))
+            (property COMP
+              (string "fifo_pfu_0_0"))
+            (property initval
+              (string "0x0000000000000000")))
+          (instance scuba_vlo_inst
+            (viewRef view1 
+              (cellRef VLO)))
+          (instance fifo_pfu_0_1
+            (viewRef view1 
+              (cellRef DPR16X4C))
+            (property MEM_INIT_FILE
+              (string "(0-7)(4-7)"))
+            (property MEM_LPC_FILE
+              (string "async_fifo_16x8_ecp3.lpc"))
+            (property COMP
+              (string "fifo_pfu_0_1"))
+            (property initval
+              (string "0x0000000000000000")))
+          (net invout_1
+            (joined
+              (portRef Z (instanceRef INV_1))
+              (portRef B (instanceRef AND2_t8))))
+          (net invout_0
+            (joined
+              (portRef Z (instanceRef INV_0))
+              (portRef B (instanceRef AND2_t7))))
+          (net w_gdata_0
+            (joined
+              (portRef D (instanceRef FF_45))
+              (portRef Z (instanceRef XOR2_t5))))
+          (net w_gdata_1
+            (joined
+              (portRef D (instanceRef FF_44))
+              (portRef Z (instanceRef XOR2_t4))))
+          (net w_gdata_2
+            (joined
+              (portRef D (instanceRef FF_43))
+              (portRef Z (instanceRef XOR2_t3))))
+          (net wptr_3
+            (joined
+              (portRef Q (instanceRef FF_38))
+              (portRef AD3 (instanceRef LUT4_1))
+              (portRef AD3 (instanceRef LUT4_0))))
+          (net r_gdata_0
+            (joined
+              (portRef D (instanceRef FF_33))
+              (portRef Z (instanceRef XOR2_t2))))
+          (net r_gdata_1
+            (joined
+              (portRef D (instanceRef FF_32))
+              (portRef Z (instanceRef XOR2_t1))))
+          (net r_gdata_2
+            (joined
+              (portRef D (instanceRef FF_31))
+              (portRef Z (instanceRef XOR2_t0))))
+          (net rptr_3
+            (joined
+              (portRef Q (instanceRef FF_26))
+              (portRef AD3 (instanceRef LUT4_3))
+              (portRef AD3 (instanceRef LUT4_2))))
+          (net w_gcount_0
+            (joined
+              (portRef D (instanceRef FF_17))
+              (portRef Q (instanceRef FF_45))))
+          (net w_gcount_1
+            (joined
+              (portRef D (instanceRef FF_16))
+              (portRef Q (instanceRef FF_44))))
+          (net w_gcount_2
+            (joined
+              (portRef D (instanceRef FF_15))
+              (portRef Q (instanceRef FF_43))))
+          (net w_gcount_3
+            (joined
+              (portRef D (instanceRef FF_14))
+              (portRef Q (instanceRef FF_42))))
+          (net r_gcount_0
+            (joined
+              (portRef D (instanceRef FF_13))
+              (portRef Q (instanceRef FF_33))))
+          (net r_gcount_1
+            (joined
+              (portRef D (instanceRef FF_12))
+              (portRef Q (instanceRef FF_32))))
+          (net r_gcount_2
+            (joined
+              (portRef D (instanceRef FF_11))
+              (portRef Q (instanceRef FF_31))))
+          (net r_gcount_3
+            (joined
+              (portRef D (instanceRef FF_10))
+              (portRef Q (instanceRef FF_30))))
+          (net w_gcount_r20
+            (joined
+              (portRef Q (instanceRef FF_9))
+              (portRef AD3 (instanceRef LUT4_9))))
+          (net w_gcount_r0
+            (joined
+              (portRef D (instanceRef FF_9))
+              (portRef Q (instanceRef FF_17))))
+          (net w_gcount_r21
+            (joined
+              (portRef Q (instanceRef FF_8))
+              (portRef AD2 (instanceRef LUT4_9))
+              (portRef AD3 (instanceRef LUT4_7))))
+          (net w_gcount_r1
+            (joined
+              (portRef D (instanceRef FF_8))
+              (portRef Q (instanceRef FF_16))))
+          (net w_gcount_r22
+            (joined
+              (portRef Q (instanceRef FF_7))
+              (portRef AD1 (instanceRef LUT4_9))
+              (portRef AD3 (instanceRef LUT4_8))
+              (portRef AD2 (instanceRef LUT4_7))))
+          (net w_gcount_r2
+            (joined
+              (portRef D (instanceRef FF_7))
+              (portRef Q (instanceRef FF_15))))
+          (net w_gcount_r23
+            (joined
+              (portRef Q (instanceRef FF_6))
+              (portRef AD0 (instanceRef LUT4_9))
+              (portRef AD2 (instanceRef LUT4_8))
+              (portRef AD1 (instanceRef LUT4_7))
+              (portRef AD1 (instanceRef LUT4_3))
+              (portRef AD1 (instanceRef LUT4_2))))
+          (net w_gcount_r3
+            (joined
+              (portRef D (instanceRef FF_6))
+              (portRef Q (instanceRef FF_14))))
+          (net r_gcount_w20
+            (joined
+              (portRef Q (instanceRef FF_5))
+              (portRef AD3 (instanceRef LUT4_6))))
+          (net r_gcount_w0
+            (joined
+              (portRef D (instanceRef FF_5))
+              (portRef Q (instanceRef FF_13))))
+          (net r_gcount_w21
+            (joined
+              (portRef Q (instanceRef FF_4))
+              (portRef AD2 (instanceRef LUT4_6))
+              (portRef AD3 (instanceRef LUT4_4))))
+          (net r_gcount_w1
+            (joined
+              (portRef D (instanceRef FF_4))
+              (portRef Q (instanceRef FF_12))))
+          (net r_gcount_w22
+            (joined
+              (portRef Q (instanceRef FF_3))
+              (portRef AD1 (instanceRef LUT4_6))
+              (portRef AD3 (instanceRef LUT4_5))
+              (portRef AD2 (instanceRef LUT4_4))))
+          (net r_gcount_w2
+            (joined
+              (portRef D (instanceRef FF_3))
+              (portRef Q (instanceRef FF_11))))
+          (net r_gcount_w23
+            (joined
+              (portRef Q (instanceRef FF_2))
+              (portRef AD0 (instanceRef LUT4_6))
+              (portRef AD2 (instanceRef LUT4_5))
+              (portRef AD1 (instanceRef LUT4_4))
+              (portRef AD1 (instanceRef LUT4_1))
+              (portRef AD1 (instanceRef LUT4_0))))
+          (net r_gcount_w3
+            (joined
+              (portRef D (instanceRef FF_2))
+              (portRef Q (instanceRef FF_10))))
+          (net rRst
+            (joined
+              (portRef PD (instanceRef FF_1))
+              (portRef Z (instanceRef OR2_t6))
+              (portRef PD (instanceRef FF_37))
+              (portRef CD (instanceRef FF_36))
+              (portRef CD (instanceRef FF_35))
+              (portRef CD (instanceRef FF_34))
+              (portRef CD (instanceRef FF_33))
+              (portRef CD (instanceRef FF_32))
+              (portRef CD (instanceRef FF_31))
+              (portRef CD (instanceRef FF_30))
+              (portRef CD (instanceRef FF_29))
+              (portRef CD (instanceRef FF_28))
+              (portRef CD (instanceRef FF_27))
+              (portRef CD (instanceRef FF_26))
+              (portRef CD (instanceRef FF_25))
+              (portRef CD (instanceRef FF_24))
+              (portRef CD (instanceRef FF_23))
+              (portRef CD (instanceRef FF_22))
+              (portRef CD (instanceRef FF_21))
+              (portRef CD (instanceRef FF_20))
+              (portRef CD (instanceRef FF_19))
+              (portRef CD (instanceRef FF_18))
+              (portRef CD (instanceRef FF_13))
+              (portRef CD (instanceRef FF_12))
+              (portRef CD (instanceRef FF_11))
+              (portRef CD (instanceRef FF_10))
+              (portRef CD (instanceRef FF_5))
+              (portRef CD (instanceRef FF_4))
+              (portRef CD (instanceRef FF_3))
+              (portRef CD (instanceRef FF_2))))
+          (net iwcount_0
+            (joined
+              (portRef NC0 (instanceRef w_gctr_0))
+              (portRef D (instanceRef FF_49))))
+          (net iwcount_1
+            (joined
+              (portRef NC1 (instanceRef w_gctr_0))
+              (portRef D (instanceRef FF_48))))
+          (net w_gctr_ci
+            (joined
+              (portRef CI (instanceRef w_gctr_0))
+              (portRef COUT (instanceRef w_gctr_cia))))
+          (net iwcount_2
+            (joined
+              (portRef NC0 (instanceRef w_gctr_1))
+              (portRef D (instanceRef FF_47))))
+          (net iwcount_3
+            (joined
+              (portRef NC1 (instanceRef w_gctr_1))
+              (portRef D (instanceRef FF_46))))
+          (net co1
+            (joined
+              (portRef CO (instanceRef w_gctr_1))))
+          (net co0
+            (joined
+              (portRef CI (instanceRef w_gctr_1))
+              (portRef CO (instanceRef w_gctr_0))))
+          (net wcount_3
+            (joined
+              (portRef PC1 (instanceRef w_gctr_1))
+              (portRef B (instanceRef XOR2_t3))
+              (portRef AD2 (instanceRef LUT4_1))
+              (portRef AD2 (instanceRef LUT4_0))
+              (portRef Q (instanceRef FF_46))
+              (portRef D (instanceRef FF_42))
+              (portRef D (instanceRef FF_38))))
+          (net scuba_vhi
+            (joined
+              (portRef Z (instanceRef scuba_vhi_inst))
+              (portRef AD0 (instanceRef LUT4_10))
+              (portRef AD1 (instanceRef LUT4_10))
+              (portRef AD3 (instanceRef LUT4_10))
+              (portRef B1 (instanceRef w_gctr_cia))
+              (portRef A1 (instanceRef w_gctr_cia))
+              (portRef B1 (instanceRef r_gctr_cia))
+              (portRef A1 (instanceRef r_gctr_cia))))
+          (net ircount_0
+            (joined
+              (portRef NC0 (instanceRef r_gctr_0))
+              (portRef D (instanceRef FF_37))))
+          (net ircount_1
+            (joined
+              (portRef NC1 (instanceRef r_gctr_0))
+              (portRef D (instanceRef FF_36))))
+          (net r_gctr_ci
+            (joined
+              (portRef CI (instanceRef r_gctr_0))
+              (portRef COUT (instanceRef r_gctr_cia))))
+          (net ircount_2
+            (joined
+              (portRef NC0 (instanceRef r_gctr_1))
+              (portRef D (instanceRef FF_35))))
+          (net ircount_3
+            (joined
+              (portRef NC1 (instanceRef r_gctr_1))
+              (portRef D (instanceRef FF_34))))
+          (net co1_1
+            (joined
+              (portRef CO (instanceRef r_gctr_1))))
+          (net co0_1
+            (joined
+              (portRef CI (instanceRef r_gctr_1))
+              (portRef CO (instanceRef r_gctr_0))))
+          (net rcount_3
+            (joined
+              (portRef PC1 (instanceRef r_gctr_1))
+              (portRef B (instanceRef XOR2_t0))
+              (portRef AD2 (instanceRef LUT4_3))
+              (portRef AD2 (instanceRef LUT4_2))
+              (portRef Q (instanceRef FF_34))
+              (portRef D (instanceRef FF_30))
+              (portRef D (instanceRef FF_26))))
+          (net rden_i
+            (joined
+              (portRef A1 (instanceRef empty_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t7))
+              (portRef SP (instanceRef FF_37))
+              (portRef SP (instanceRef FF_36))
+              (portRef SP (instanceRef FF_35))
+              (portRef SP (instanceRef FF_34))
+              (portRef SP (instanceRef FF_33))
+              (portRef SP (instanceRef FF_32))
+              (portRef SP (instanceRef FF_31))
+              (portRef SP (instanceRef FF_30))
+              (portRef SP (instanceRef FF_29))
+              (portRef SP (instanceRef FF_28))
+              (portRef SP (instanceRef FF_27))
+              (portRef SP (instanceRef FF_26))
+              (portRef SP (instanceRef FF_25))
+              (portRef SP (instanceRef FF_24))
+              (portRef SP (instanceRef FF_23))
+              (portRef SP (instanceRef FF_22))
+              (portRef SP (instanceRef FF_21))
+              (portRef SP (instanceRef FF_20))
+              (portRef SP (instanceRef FF_19))
+              (portRef SP (instanceRef FF_18))
+              (portRef B1 (instanceRef empty_cmp_ci_a))))
+          (net cmp_ci
+            (joined
+              (portRef CI (instanceRef empty_cmp_0))
+              (portRef COUT (instanceRef empty_cmp_ci_a))))
+          (net w_g2b_xor_cluster_0
+            (joined
+              (portRef B0 (instanceRef empty_cmp_0))
+              (portRef DO0 (instanceRef LUT4_9))))
+          (net wcount_r1
+            (joined
+              (portRef B1 (instanceRef empty_cmp_0))
+              (portRef DO0 (instanceRef LUT4_7))))
+          (net rcount_0
+            (joined
+              (portRef A0 (instanceRef empty_cmp_0))
+              (portRef A (instanceRef XOR2_t2))
+              (portRef Q (instanceRef FF_37))
+              (portRef D (instanceRef FF_29))
+              (portRef PC0 (instanceRef r_gctr_0))))
+          (net rcount_1
+            (joined
+              (portRef A1 (instanceRef empty_cmp_0))
+              (portRef B (instanceRef XOR2_t2))
+              (portRef A (instanceRef XOR2_t1))
+              (portRef Q (instanceRef FF_36))
+              (portRef D (instanceRef FF_28))
+              (portRef PC1 (instanceRef r_gctr_0))))
+          (net co0_2
+            (joined
+              (portRef CI (instanceRef empty_cmp_1))
+              (portRef GE (instanceRef empty_cmp_0))))
+          (net wcount_r2
+            (joined
+              (portRef B0 (instanceRef empty_cmp_1))
+              (portRef DO0 (instanceRef LUT4_8))))
+          (net empty_cmp_clr
+            (joined
+              (portRef B1 (instanceRef empty_cmp_1))
+              (portRef DO0 (instanceRef LUT4_2))))
+          (net rcount_2
+            (joined
+              (portRef A0 (instanceRef empty_cmp_1))
+              (portRef B (instanceRef XOR2_t1))
+              (portRef A (instanceRef XOR2_t0))
+              (portRef Q (instanceRef FF_35))
+              (portRef D (instanceRef FF_27))
+              (portRef PC0 (instanceRef r_gctr_1))))
+          (net empty_cmp_set
+            (joined
+              (portRef A1 (instanceRef empty_cmp_1))
+              (portRef DO0 (instanceRef LUT4_3))))
+          (net empty_d
+            (joined
+              (portRef S0 (instanceRef a0))
+              (portRef D (instanceRef FF_1))))
+          (net empty_d_c
+            (joined
+              (portRef CI (instanceRef a0))
+              (portRef GE (instanceRef empty_cmp_1))))
+          (net wren_i
+            (joined
+              (portRef A1 (instanceRef full_cmp_ci_a))
+              (portRef Z (instanceRef AND2_t8))
+              (portRef AD2 (instanceRef LUT4_10))
+              (portRef SP (instanceRef FF_49))
+              (portRef SP (instanceRef FF_48))
+              (portRef SP (instanceRef FF_47))
+              (portRef SP (instanceRef FF_46))
+              (portRef SP (instanceRef FF_45))
+              (portRef SP (instanceRef FF_44))
+              (portRef SP (instanceRef FF_43))
+              (portRef SP (instanceRef FF_42))
+              (portRef SP (instanceRef FF_41))
+              (portRef SP (instanceRef FF_40))
+              (portRef SP (instanceRef FF_39))
+              (portRef SP (instanceRef FF_38))
+              (portRef B1 (instanceRef full_cmp_ci_a))))
+          (net cmp_ci_1
+            (joined
+              (portRef CI (instanceRef full_cmp_0))
+              (portRef COUT (instanceRef full_cmp_ci_a))))
+          (net r_g2b_xor_cluster_0
+            (joined
+              (portRef B0 (instanceRef full_cmp_0))
+              (portRef DO0 (instanceRef LUT4_6))))
+          (net rcount_w1
+            (joined
+              (portRef B1 (instanceRef full_cmp_0))
+              (portRef DO0 (instanceRef LUT4_4))))
+          (net wcount_0
+            (joined
+              (portRef A0 (instanceRef full_cmp_0))
+              (portRef A (instanceRef XOR2_t5))
+              (portRef Q (instanceRef FF_49))
+              (portRef D (instanceRef FF_41))
+              (portRef PC0 (instanceRef w_gctr_0))))
+          (net wcount_1
+            (joined
+              (portRef A1 (instanceRef full_cmp_0))
+              (portRef B (instanceRef XOR2_t5))
+              (portRef A (instanceRef XOR2_t4))
+              (portRef Q (instanceRef FF_48))
+              (portRef D (instanceRef FF_40))
+              (portRef PC1 (instanceRef w_gctr_0))))
+          (net co0_3
+            (joined
+              (portRef CI (instanceRef full_cmp_1))
+              (portRef GE (instanceRef full_cmp_0))))
+          (net rcount_w2
+            (joined
+              (portRef B0 (instanceRef full_cmp_1))
+              (portRef DO0 (instanceRef LUT4_5))))
+          (net full_cmp_clr
+            (joined
+              (portRef B1 (instanceRef full_cmp_1))
+              (portRef DO0 (instanceRef LUT4_0))))
+          (net wcount_2
+            (joined
+              (portRef A0 (instanceRef full_cmp_1))
+              (portRef B (instanceRef XOR2_t4))
+              (portRef A (instanceRef XOR2_t3))
+              (portRef Q (instanceRef FF_47))
+              (portRef D (instanceRef FF_39))
+              (portRef PC0 (instanceRef w_gctr_1))))
+          (net full_cmp_set
+            (joined
+              (portRef A1 (instanceRef full_cmp_1))
+              (portRef DO0 (instanceRef LUT4_1))))
+          (net full_d
+            (joined
+              (portRef S0 (instanceRef a1))
+              (portRef D (instanceRef FF_0))))
+          (net full_d_c
+            (joined
+              (portRef CI (instanceRef a1))
+              (portRef GE (instanceRef full_cmp_1))))
+          (net rdataout7
+            (joined
+              (portRef DO3 (instanceRef fifo_pfu_0_0))
+              (portRef D (instanceRef FF_18))))
+          (net rdataout6
+            (joined
+              (portRef DO2 (instanceRef fifo_pfu_0_0))
+              (portRef D (instanceRef FF_19))))
+          (net rdataout5
+            (joined
+              (portRef DO1 (instanceRef fifo_pfu_0_0))
+              (portRef D (instanceRef FF_20))))
+          (net rdataout4
+            (joined
+              (portRef DO0 (instanceRef fifo_pfu_0_0))
+              (portRef D (instanceRef FF_21))))
+          (net rdataout3
+            (joined
+              (portRef DO3 (instanceRef fifo_pfu_0_1))
+              (portRef D (instanceRef FF_22))))
+          (net rdataout2
+            (joined
+              (portRef DO2 (instanceRef fifo_pfu_0_1))
+              (portRef D (instanceRef FF_23))))
+          (net rdataout1
+            (joined
+              (portRef DO1 (instanceRef fifo_pfu_0_1))
+              (portRef D (instanceRef FF_24))))
+          (net rdataout0
+            (joined
+              (portRef DO0 (instanceRef fifo_pfu_0_1))
+              (portRef D (instanceRef FF_25))))
+          (net rptr_2
+            (joined
+              (portRef RAD2 (instanceRef fifo_pfu_0_1))
+              (portRef Q (instanceRef FF_27))
+              (portRef RAD2 (instanceRef fifo_pfu_0_0))))
+          (net rptr_1
+            (joined
+              (portRef RAD1 (instanceRef fifo_pfu_0_1))
+              (portRef Q (instanceRef FF_28))
+              (portRef RAD1 (instanceRef fifo_pfu_0_0))))
+          (net rptr_0
+            (joined
+              (portRef RAD0 (instanceRef fifo_pfu_0_1))
+              (portRef Q (instanceRef FF_29))
+              (portRef RAD0 (instanceRef fifo_pfu_0_0))))
+          (net dec0_wre3
+            (joined
+              (portRef WRE (instanceRef fifo_pfu_0_1))
+              (portRef DO0 (instanceRef LUT4_10))
+              (portRef WRE (instanceRef fifo_pfu_0_0))))
+          (net scuba_vlo
+            (joined
+              (portRef Z (instanceRef scuba_vlo_inst))
+              (portRef AD0 (instanceRef LUT4_8))
+              (portRef AD1 (instanceRef LUT4_8))
+              (portRef AD0 (instanceRef LUT4_7))
+              (portRef AD0 (instanceRef LUT4_5))
+              (portRef AD1 (instanceRef LUT4_5))
+              (portRef AD0 (instanceRef LUT4_4))
+              (portRef AD0 (instanceRef LUT4_3))
+              (portRef AD0 (instanceRef LUT4_2))
+              (portRef AD0 (instanceRef LUT4_1))
+              (portRef AD0 (instanceRef LUT4_0))
+              (portRef CI (instanceRef w_gctr_cia))
+              (portRef B0 (instanceRef w_gctr_cia))
+              (portRef A0 (instanceRef w_gctr_cia))
+              (portRef CI (instanceRef r_gctr_cia))
+              (portRef B0 (instanceRef r_gctr_cia))
+              (portRef A0 (instanceRef r_gctr_cia))
+              (portRef CI (instanceRef empty_cmp_ci_a))
+              (portRef B0 (instanceRef empty_cmp_ci_a))
+              (portRef A0 (instanceRef empty_cmp_ci_a))
+              (portRef B0 (instanceRef a0))
+              (portRef B1 (instanceRef a0))
+              (portRef A0 (instanceRef a0))
+              (portRef A1 (instanceRef a0))
+              (portRef CI (instanceRef full_cmp_ci_a))
+              (portRef B0 (instanceRef full_cmp_ci_a))
+              (portRef A0 (instanceRef full_cmp_ci_a))
+              (portRef B0 (instanceRef a1))
+              (portRef B1 (instanceRef a1))
+              (portRef A0 (instanceRef a1))
+              (portRef A1 (instanceRef a1))
+              (portRef RAD3 (instanceRef fifo_pfu_0_0))
+              (portRef WAD3 (instanceRef fifo_pfu_0_0))
+              (portRef RAD3 (instanceRef fifo_pfu_0_1))
+              (portRef WAD3 (instanceRef fifo_pfu_0_1))))
+          (net wptr_2
+            (joined
+              (portRef WAD2 (instanceRef fifo_pfu_0_1))
+              (portRef Q (instanceRef FF_39))
+              (portRef WAD2 (instanceRef fifo_pfu_0_0))))
+          (net wptr_1
+            (joined
+              (portRef WAD1 (instanceRef fifo_pfu_0_1))
+              (portRef Q (instanceRef FF_40))
+              (portRef WAD1 (instanceRef fifo_pfu_0_0))))
+          (net wptr_0
+            (joined
+              (portRef WAD0 (instanceRef fifo_pfu_0_1))
+              (portRef Q (instanceRef FF_41))
+              (portRef WAD0 (instanceRef fifo_pfu_0_0))))
+          (net Full
+            (joined
+              (portRef Full)
+              (portRef Q (instanceRef FF_0))
+              (portRef A (instanceRef INV_1))))
+          (net Empty
+            (joined
+              (portRef Empty)
+              (portRef Q (instanceRef FF_1))
+              (portRef A (instanceRef INV_0))))
+          (net dataout7
+            (joined
+              (portRef (member Q 0))
+              (portRef Q (instanceRef FF_18))))
+          (net dataout6
+            (joined
+              (portRef (member Q 1))
+              (portRef Q (instanceRef FF_19))))
+          (net dataout5
+            (joined
+              (portRef (member Q 2))
+              (portRef Q (instanceRef FF_20))))
+          (net dataout4
+            (joined
+              (portRef (member Q 3))
+              (portRef Q (instanceRef FF_21))))
+          (net dataout3
+            (joined
+              (portRef (member Q 4))
+              (portRef Q (instanceRef FF_22))))
+          (net dataout2
+            (joined
+              (portRef (member Q 5))
+              (portRef Q (instanceRef FF_23))))
+          (net dataout1
+            (joined
+              (portRef (member Q 6))
+              (portRef Q (instanceRef FF_24))))
+          (net dataout0
+            (joined
+              (portRef (member Q 7))
+              (portRef Q (instanceRef FF_25))))
+          (net RPRst
+            (joined
+              (portRef RPReset)
+              (portRef B (instanceRef OR2_t6))))
+          (net reset
+            (joined
+              (portRef Reset)
+              (portRef A (instanceRef OR2_t6))
+              (portRef PD (instanceRef FF_49))
+              (portRef CD (instanceRef FF_48))
+              (portRef CD (instanceRef FF_47))
+              (portRef CD (instanceRef FF_46))
+              (portRef CD (instanceRef FF_45))
+              (portRef CD (instanceRef FF_44))
+              (portRef CD (instanceRef FF_43))
+              (portRef CD (instanceRef FF_42))
+              (portRef CD (instanceRef FF_41))
+              (portRef CD (instanceRef FF_40))
+              (portRef CD (instanceRef FF_39))
+              (portRef CD (instanceRef FF_38))
+              (portRef CD (instanceRef FF_17))
+              (portRef CD (instanceRef FF_16))
+              (portRef CD (instanceRef FF_15))
+              (portRef CD (instanceRef FF_14))
+              (portRef CD (instanceRef FF_9))
+              (portRef CD (instanceRef FF_8))
+              (portRef CD (instanceRef FF_7))
+              (portRef CD (instanceRef FF_6))
+              (portRef CD (instanceRef FF_0))))
+          (net rden
+            (joined
+              (portRef RdEn)
+              (portRef A (instanceRef AND2_t7))))
+          (net wren
+            (joined
+              (portRef WrEn)
+              (portRef A (instanceRef AND2_t8))))
+          (net rclk
+            (joined
+              (portRef RdClock)
+              (portRef CK (instanceRef FF_37))
+              (portRef CK (instanceRef FF_36))
+              (portRef CK (instanceRef FF_35))
+              (portRef CK (instanceRef FF_34))
+              (portRef CK (instanceRef FF_33))
+              (portRef CK (instanceRef FF_32))
+              (portRef CK (instanceRef FF_31))
+              (portRef CK (instanceRef FF_30))
+              (portRef CK (instanceRef FF_29))
+              (portRef CK (instanceRef FF_28))
+              (portRef CK (instanceRef FF_27))
+              (portRef CK (instanceRef FF_26))
+              (portRef CK (instanceRef FF_25))
+              (portRef CK (instanceRef FF_24))
+              (portRef CK (instanceRef FF_23))
+              (portRef CK (instanceRef FF_22))
+              (portRef CK (instanceRef FF_21))
+              (portRef CK (instanceRef FF_20))
+              (portRef CK (instanceRef FF_19))
+              (portRef CK (instanceRef FF_18))
+              (portRef CK (instanceRef FF_17))
+              (portRef CK (instanceRef FF_16))
+              (portRef CK (instanceRef FF_15))
+              (portRef CK (instanceRef FF_14))
+              (portRef CK (instanceRef FF_9))
+              (portRef CK (instanceRef FF_8))
+              (portRef CK (instanceRef FF_7))
+              (portRef CK (instanceRef FF_6))
+              (portRef CK (instanceRef FF_1))))
+          (net wclk
+            (joined
+              (portRef WrClock)
+              (portRef CK (instanceRef FF_49))
+              (portRef CK (instanceRef FF_48))
+              (portRef CK (instanceRef FF_47))
+              (portRef CK (instanceRef FF_46))
+              (portRef CK (instanceRef FF_45))
+              (portRef CK (instanceRef FF_44))
+              (portRef CK (instanceRef FF_43))
+              (portRef CK (instanceRef FF_42))
+              (portRef CK (instanceRef FF_41))
+              (portRef CK (instanceRef FF_40))
+              (portRef CK (instanceRef FF_39))
+              (portRef CK (instanceRef FF_38))
+              (portRef CK (instanceRef FF_13))
+              (portRef CK (instanceRef FF_12))
+              (portRef CK (instanceRef FF_11))
+              (portRef CK (instanceRef FF_10))
+              (portRef CK (instanceRef FF_5))
+              (portRef CK (instanceRef FF_4))
+              (portRef CK (instanceRef FF_3))
+              (portRef CK (instanceRef FF_2))
+              (portRef CK (instanceRef FF_0))
+              (portRef WCK (instanceRef fifo_pfu_0_0))
+              (portRef WCK (instanceRef fifo_pfu_0_1))))
+          (net datain7
+            (joined
+              (portRef (member Data 0))
+              (portRef DI3 (instanceRef fifo_pfu_0_0))))
+          (net datain6
+            (joined
+              (portRef (member Data 1))
+              (portRef DI2 (instanceRef fifo_pfu_0_0))))
+          (net datain5
+            (joined
+              (portRef (member Data 2))
+              (portRef DI1 (instanceRef fifo_pfu_0_0))))
+          (net datain4
+            (joined
+              (portRef (member Data 3))
+              (portRef DI0 (instanceRef fifo_pfu_0_0))))
+          (net datain3
+            (joined
+              (portRef (member Data 4))
+              (portRef DI3 (instanceRef fifo_pfu_0_1))))
+          (net datain2
+            (joined
+              (portRef (member Data 5))
+              (portRef DI2 (instanceRef fifo_pfu_0_1))))
+          (net datain1
+            (joined
+              (portRef (member Data 6))
+              (portRef DI1 (instanceRef fifo_pfu_0_1))))
+          (net datain0
+            (joined
+              (portRef (member Data 7))
+              (portRef DI0 (instanceRef fifo_pfu_0_1))))))))
+  (design async_fifo_16x8_ecp3
+    (cellRef async_fifo_16x8_ecp3
+      (libraryRef ORCLIB)))
+)
diff --git a/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.ipx b/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.ipx
new file mode 100644
index 0000000..9f045bb
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.ipx
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="async_fifo_16x8_ecp3" module="async_fifo_16x8_ecp3" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 07 14 16:16:02.803" version="5.7" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="async_fifo_16x8_ecp3.lpc" type="lpc" modified="2015 07 14 16:15:57.082"/>
+		<File name="async_fifo_16x8_ecp3.vhd" type="top_level_vhdl" modified="2015 07 14 16:15:57.161"/>
+		<File name="async_fifo_16x8_ecp3_tmpl.vhd" type="template_vhdl" modified="2015 07 14 16:15:57.161"/>
+		<File name="tb_async_fifo_16x8_ecp3_tmpl.vhd" type="testbench_vhdl" modified="2015 07 14 16:15:57.166"/>
+  </Package>
+</DiamondModule>
diff --git a/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.lpc b/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.lpc
new file mode 100644
index 0000000..1285328
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.lpc
@@ -0,0 +1,50 @@
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8FN672C
+SpeedGrade=8
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.7
+ModuleName=async_fifo_16x8_ecp3
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=07/14/2015
+Time=16:15:57
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=LUT Based
+Depth=8
+Width=8
+RDepth=8
+RWidth=8
+regout=0
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=0
+WDataCount=0
+EnECC=0
+
+[Command]
+cmd_line= -w -n async_fifo_16x8_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -pfu_fifo -addr_width 3 -data_width 8 -num_words 8 -rdata_width 8 -no_enable -pe -1 -pf -1
diff --git a/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.vhd b/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.vhd
new file mode 100644
index 0000000..7596e6b
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/async_fifo_16x8_ecp3.vhd
@@ -0,0 +1,642 @@
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.2.0.134
+-- Module  Version: 5.7
+--C:\Lattice\diamond\3.2_x64\ispfpga\bin\nt64\scuba.exe -w -n async_fifo_16x8_ecp3 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -pfu_fifo -depth 8 -width 8 -depth 8 -rdata_width 8 -no_enable -pe -1 -pf -1 
+
+-- Tue Jul 14 16:15:57 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity async_fifo_16x8_ecp3 is
+    port (
+        Data: in  std_logic_vector(7 downto 0); 
+        WrClock: in  std_logic; 
+        RdClock: in  std_logic; 
+        WrEn: in  std_logic; 
+        RdEn: in  std_logic; 
+        Reset: in  std_logic; 
+        RPReset: in  std_logic; 
+        Q: out  std_logic_vector(7 downto 0); 
+        Empty: out  std_logic; 
+        Full: out  std_logic);
+end async_fifo_16x8_ecp3;
+
+architecture Structure of async_fifo_16x8_ecp3 is
+
+    -- internal signal declarations
+    signal invout_1: std_logic;
+    signal invout_0: std_logic;
+    signal w_gdata_0: std_logic;
+    signal w_gdata_1: std_logic;
+    signal w_gdata_2: std_logic;
+    signal wptr_3: std_logic;
+    signal r_gdata_0: std_logic;
+    signal r_gdata_1: std_logic;
+    signal r_gdata_2: std_logic;
+    signal rptr_3: std_logic;
+    signal w_gcount_0: std_logic;
+    signal w_gcount_1: std_logic;
+    signal w_gcount_2: std_logic;
+    signal w_gcount_3: std_logic;
+    signal r_gcount_0: std_logic;
+    signal r_gcount_1: std_logic;
+    signal r_gcount_2: std_logic;
+    signal r_gcount_3: std_logic;
+    signal w_gcount_r20: std_logic;
+    signal w_gcount_r0: std_logic;
+    signal w_gcount_r21: std_logic;
+    signal w_gcount_r1: std_logic;
+    signal w_gcount_r22: std_logic;
+    signal w_gcount_r2: std_logic;
+    signal w_gcount_r23: std_logic;
+    signal w_gcount_r3: std_logic;
+    signal r_gcount_w20: std_logic;
+    signal r_gcount_w0: std_logic;
+    signal r_gcount_w21: std_logic;
+    signal r_gcount_w1: std_logic;
+    signal r_gcount_w22: std_logic;
+    signal r_gcount_w2: std_logic;
+    signal r_gcount_w23: std_logic;
+    signal r_gcount_w3: std_logic;
+    signal empty_i: std_logic;
+    signal rRst: std_logic;
+    signal full_i: std_logic;
+    signal iwcount_0: std_logic;
+    signal iwcount_1: std_logic;
+    signal w_gctr_ci: std_logic;
+    signal iwcount_2: std_logic;
+    signal iwcount_3: std_logic;
+    signal co1: std_logic;
+    signal co0: std_logic;
+    signal wcount_3: std_logic;
+    signal scuba_vhi: std_logic;
+    signal ircount_0: std_logic;
+    signal ircount_1: std_logic;
+    signal r_gctr_ci: std_logic;
+    signal ircount_2: std_logic;
+    signal ircount_3: std_logic;
+    signal co1_1: std_logic;
+    signal co0_1: std_logic;
+    signal rcount_3: std_logic;
+    signal rden_i: std_logic;
+    signal cmp_ci: std_logic;
+    signal w_g2b_xor_cluster_0: std_logic;
+    signal wcount_r1: std_logic;
+    signal rcount_0: std_logic;
+    signal rcount_1: std_logic;
+    signal co0_2: std_logic;
+    signal wcount_r2: std_logic;
+    signal empty_cmp_clr: std_logic;
+    signal rcount_2: std_logic;
+    signal empty_cmp_set: std_logic;
+    signal empty_d: std_logic;
+    signal empty_d_c: std_logic;
+    signal wren_i: std_logic;
+    signal cmp_ci_1: std_logic;
+    signal r_g2b_xor_cluster_0: std_logic;
+    signal rcount_w1: std_logic;
+    signal wcount_0: std_logic;
+    signal wcount_1: std_logic;
+    signal co0_3: std_logic;
+    signal rcount_w2: std_logic;
+    signal full_cmp_clr: std_logic;
+    signal wcount_2: std_logic;
+    signal full_cmp_set: std_logic;
+    signal full_d: std_logic;
+    signal full_d_c: std_logic;
+    signal rdataout7: std_logic;
+    signal rdataout6: std_logic;
+    signal rdataout5: std_logic;
+    signal rdataout4: std_logic;
+    signal rdataout3: std_logic;
+    signal rdataout2: std_logic;
+    signal rdataout1: std_logic;
+    signal rdataout0: std_logic;
+    signal rptr_2: std_logic;
+    signal rptr_1: std_logic;
+    signal rptr_0: std_logic;
+    signal dec0_wre3: std_logic;
+    signal scuba_vlo: std_logic;
+    signal wptr_2: std_logic;
+    signal wptr_1: std_logic;
+    signal wptr_0: std_logic;
+
+    -- local component declarations
+    component AGEB2
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
+    end component;
+    component AND2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component CU2
+        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
+            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
+    end component;
+    component FADD2B
+        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
+            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
+            S0: out  std_logic; S1: out  std_logic);
+    end component;
+    component FD1P3BX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            PD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1P3DX
+        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
+            CD: in  std_logic; Q: out  std_logic);
+    end component;
+    component FD1S3BX
+        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component FD1S3DX
+        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
+            Q: out  std_logic);
+    end component;
+    component INV
+        port (A: in  std_logic; Z: out  std_logic);
+    end component;
+    component OR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    component ROM16X1A
+        generic (INITVAL : in std_logic_vector(15 downto 0));
+        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
+            AD0: in  std_logic; DO0: out  std_logic);
+    end component;
+    component DPR16X4C
+        generic (INITVAL : in String);
+        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
+            DI3: in  std_logic; WCK: in  std_logic; WRE: in  std_logic; 
+            RAD0: in  std_logic; RAD1: in  std_logic; 
+            RAD2: in  std_logic; RAD3: in  std_logic; 
+            WAD0: in  std_logic; WAD1: in  std_logic; 
+            WAD2: in  std_logic; WAD3: in  std_logic; 
+            DO0: out  std_logic; DO1: out  std_logic; 
+            DO2: out  std_logic; DO3: out  std_logic);
+    end component;
+    component VHI
+        port (Z: out  std_logic);
+    end component;
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component XOR2
+        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
+    end component;
+    attribute GSR : string; 
+    attribute MEM_INIT_FILE : string; 
+    attribute MEM_LPC_FILE : string; 
+    attribute COMP : string; 
+    attribute GSR of FF_49 : label is "ENABLED";
+    attribute GSR of FF_48 : label is "ENABLED";
+    attribute GSR of FF_47 : label is "ENABLED";
+    attribute GSR of FF_46 : label is "ENABLED";
+    attribute GSR of FF_45 : label is "ENABLED";
+    attribute GSR of FF_44 : label is "ENABLED";
+    attribute GSR of FF_43 : label is "ENABLED";
+    attribute GSR of FF_42 : label is "ENABLED";
+    attribute GSR of FF_41 : label is "ENABLED";
+    attribute GSR of FF_40 : label is "ENABLED";
+    attribute GSR of FF_39 : label is "ENABLED";
+    attribute GSR of FF_38 : label is "ENABLED";
+    attribute GSR of FF_37 : label is "ENABLED";
+    attribute GSR of FF_36 : label is "ENABLED";
+    attribute GSR of FF_35 : label is "ENABLED";
+    attribute GSR of FF_34 : label is "ENABLED";
+    attribute GSR of FF_33 : label is "ENABLED";
+    attribute GSR of FF_32 : label is "ENABLED";
+    attribute GSR of FF_31 : label is "ENABLED";
+    attribute GSR of FF_30 : label is "ENABLED";
+    attribute GSR of FF_29 : label is "ENABLED";
+    attribute GSR of FF_28 : label is "ENABLED";
+    attribute GSR of FF_27 : label is "ENABLED";
+    attribute GSR of FF_26 : label is "ENABLED";
+    attribute GSR of FF_25 : label is "ENABLED";
+    attribute GSR of FF_24 : label is "ENABLED";
+    attribute GSR of FF_23 : label is "ENABLED";
+    attribute GSR of FF_22 : label is "ENABLED";
+    attribute GSR of FF_21 : label is "ENABLED";
+    attribute GSR of FF_20 : label is "ENABLED";
+    attribute GSR of FF_19 : label is "ENABLED";
+    attribute GSR of FF_18 : label is "ENABLED";
+    attribute GSR of FF_17 : label is "ENABLED";
+    attribute GSR of FF_16 : label is "ENABLED";
+    attribute GSR of FF_15 : label is "ENABLED";
+    attribute GSR of FF_14 : label is "ENABLED";
+    attribute GSR of FF_13 : label is "ENABLED";
+    attribute GSR of FF_12 : label is "ENABLED";
+    attribute GSR of FF_11 : label is "ENABLED";
+    attribute GSR of FF_10 : label is "ENABLED";
+    attribute GSR of FF_9 : label is "ENABLED";
+    attribute GSR of FF_8 : label is "ENABLED";
+    attribute GSR of FF_7 : label is "ENABLED";
+    attribute GSR of FF_6 : label is "ENABLED";
+    attribute GSR of FF_5 : label is "ENABLED";
+    attribute GSR of FF_4 : label is "ENABLED";
+    attribute GSR of FF_3 : label is "ENABLED";
+    attribute GSR of FF_2 : label is "ENABLED";
+    attribute GSR of FF_1 : label is "ENABLED";
+    attribute GSR of FF_0 : label is "ENABLED";
+    attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-7)(0-3)";
+    attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "async_fifo_16x8_ecp3.lpc";
+    attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0";
+    attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-7)(4-7)";
+    attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "async_fifo_16x8_ecp3.lpc";
+    attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1";
+    attribute syn_keep : boolean;
+    attribute NGD_DRC_MASK : integer;
+    attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+    -- component instantiation statements
+    AND2_t8: AND2
+        port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+    INV_1: INV
+        port map (A=>full_i, Z=>invout_1);
+
+    AND2_t7: AND2
+        port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+    INV_0: INV
+        port map (A=>empty_i, Z=>invout_0);
+
+    OR2_t6: OR2
+        port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+    XOR2_t5: XOR2
+        port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+    XOR2_t4: XOR2
+        port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+    XOR2_t3: XOR2
+        port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+    XOR2_t2: XOR2
+        port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+    XOR2_t1: XOR2
+        port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+    XOR2_t0: XOR2
+        port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+    LUT4_10: ROM16X1A
+        generic map (initval=> X"8000")
+        port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, 
+            AD0=>scuba_vhi, DO0=>dec0_wre3);
+
+    LUT4_9: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, 
+            AD1=>w_gcount_r22, AD0=>w_gcount_r23, 
+            DO0=>w_g2b_xor_cluster_0);
+
+    LUT4_8: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>wcount_r2);
+
+    LUT4_7: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, 
+            AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+    LUT4_6: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, 
+            AD1=>r_gcount_w22, AD0=>r_gcount_w23, 
+            DO0=>r_g2b_xor_cluster_0);
+
+    LUT4_5: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, AD1=>scuba_vlo, 
+            AD0=>scuba_vlo, DO0=>rcount_w2);
+
+    LUT4_4: ROM16X1A
+        generic map (initval=> X"6996")
+        port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, 
+            AD1=>r_gcount_w23, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+    LUT4_3: ROM16X1A
+        generic map (initval=> X"0410")
+        port map (AD3=>rptr_3, AD2=>rcount_3, AD1=>w_gcount_r23, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+    LUT4_2: ROM16X1A
+        generic map (initval=> X"1004")
+        port map (AD3=>rptr_3, AD2=>rcount_3, AD1=>w_gcount_r23, 
+            AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+    LUT4_1: ROM16X1A
+        generic map (initval=> X"0140")
+        port map (AD3=>wptr_3, AD2=>wcount_3, AD1=>r_gcount_w23, 
+            AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+    LUT4_0: ROM16X1A
+        generic map (initval=> X"4001")
+        port map (AD3=>wptr_3, AD2=>wcount_3, AD1=>r_gcount_w23, 
+            AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+    FF_49: FD1P3BX
+        port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, 
+            Q=>wcount_0);
+
+    FF_48: FD1P3DX
+        port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_1);
+
+    FF_47: FD1P3DX
+        port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_2);
+
+    FF_46: FD1P3DX
+        port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wcount_3);
+
+    FF_45: FD1P3DX
+        port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_0);
+
+    FF_44: FD1P3DX
+        port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_1);
+
+    FF_43: FD1P3DX
+        port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_2);
+
+    FF_42: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>w_gcount_3);
+
+    FF_41: FD1P3DX
+        port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_0);
+
+    FF_40: FD1P3DX
+        port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_1);
+
+    FF_39: FD1P3DX
+        port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_2);
+
+    FF_38: FD1P3DX
+        port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, 
+            Q=>wptr_3);
+
+    FF_37: FD1P3BX
+        port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, 
+            Q=>rcount_0);
+
+    FF_36: FD1P3DX
+        port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_1);
+
+    FF_35: FD1P3DX
+        port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_2);
+
+    FF_34: FD1P3DX
+        port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rcount_3);
+
+    FF_33: FD1P3DX
+        port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_0);
+
+    FF_32: FD1P3DX
+        port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_1);
+
+    FF_31: FD1P3DX
+        port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_2);
+
+    FF_30: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>r_gcount_3);
+
+    FF_29: FD1P3DX
+        port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_0);
+
+    FF_28: FD1P3DX
+        port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_1);
+
+    FF_27: FD1P3DX
+        port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_2);
+
+    FF_26: FD1P3DX
+        port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>rptr_3);
+
+    FF_25: FD1P3DX
+        port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>Q(0));
+
+    FF_24: FD1P3DX
+        port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>Q(1));
+
+    FF_23: FD1P3DX
+        port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>Q(2));
+
+    FF_22: FD1P3DX
+        port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>Q(3));
+
+    FF_21: FD1P3DX
+        port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>Q(4));
+
+    FF_20: FD1P3DX
+        port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>Q(5));
+
+    FF_19: FD1P3DX
+        port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>Q(6));
+
+    FF_18: FD1P3DX
+        port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst, 
+            Q=>Q(7));
+
+    FF_17: FD1S3DX
+        port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+    FF_16: FD1S3DX
+        port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+    FF_15: FD1S3DX
+        port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+    FF_14: FD1S3DX
+        port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+    FF_13: FD1S3DX
+        port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+    FF_12: FD1S3DX
+        port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+    FF_11: FD1S3DX
+        port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+    FF_10: FD1S3DX
+        port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+    FF_9: FD1S3DX
+        port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r20);
+
+    FF_8: FD1S3DX
+        port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r21);
+
+    FF_7: FD1S3DX
+        port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r22);
+
+    FF_6: FD1S3DX
+        port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, 
+            Q=>w_gcount_r23);
+
+    FF_5: FD1S3DX
+        port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+    FF_4: FD1S3DX
+        port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+    FF_3: FD1S3DX
+        port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+    FF_2: FD1S3DX
+        port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+    FF_1: FD1S3BX
+        port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+    FF_0: FD1S3DX
+        port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+    w_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, 
+            S1=>open);
+
+    w_gctr_0: CU2
+        port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, 
+            NC0=>iwcount_0, NC1=>iwcount_1);
+
+    w_gctr_1: CU2
+        port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, 
+            NC0=>iwcount_2, NC1=>iwcount_3);
+
+    scuba_vhi_inst: VHI
+        port map (Z=>scuba_vhi);
+
+    r_gctr_cia: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, 
+            B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, 
+            S1=>open);
+
+    r_gctr_0: CU2
+        port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, 
+            NC0=>ircount_0, NC1=>ircount_1);
+
+    r_gctr_1: CU2
+        port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, 
+            NC0=>ircount_2, NC1=>ircount_3);
+
+    empty_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+    empty_cmp_0: AGEB2
+        port map (A0=>rcount_0, A1=>rcount_1, B0=>w_g2b_xor_cluster_0, 
+            B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
+
+    empty_cmp_1: AGEB2
+        port map (A0=>rcount_2, A1=>empty_cmp_set, B0=>wcount_r2, 
+            B1=>empty_cmp_clr, CI=>co0_2, GE=>empty_d_c);
+
+    a0: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, 
+            S1=>open);
+
+    full_cmp_ci_a: FADD2B
+        port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, 
+            CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+    full_cmp_0: AGEB2
+        port map (A0=>wcount_0, A1=>wcount_1, B0=>r_g2b_xor_cluster_0, 
+            B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
+
+    full_cmp_1: AGEB2
+        port map (A0=>wcount_2, A1=>full_cmp_set, B0=>rcount_w2, 
+            B1=>full_cmp_clr, CI=>co0_3, GE=>full_d_c);
+
+    a1: FADD2B
+        port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, 
+            B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, 
+            S1=>open);
+
+    fifo_pfu_0_0: DPR16X4C
+        generic map (initval=> "0x0000000000000000")
+        port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), 
+            WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, 
+            RAD2=>rptr_2, RAD3=>scuba_vlo, WAD0=>wptr_0, WAD1=>wptr_1, 
+            WAD2=>wptr_2, WAD3=>scuba_vlo, DO0=>rdataout4, 
+            DO1=>rdataout5, DO2=>rdataout6, DO3=>rdataout7);
+
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    fifo_pfu_0_1: DPR16X4C
+        generic map (initval=> "0x0000000000000000")
+        port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), 
+            WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, 
+            RAD2=>rptr_2, RAD3=>scuba_vlo, WAD0=>wptr_0, WAD1=>wptr_1, 
+            WAD2=>wptr_2, WAD3=>scuba_vlo, DO0=>rdataout0, 
+            DO1=>rdataout1, DO2=>rdataout2, DO3=>rdataout3);
+
+    Empty <= empty_i;
+    Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of async_fifo_16x8_ecp3 is
+    for Structure
+        for all:AGEB2 use entity ecp3.AGEB2(V); end for;
+        for all:AND2 use entity ecp3.AND2(V); end for;
+        for all:CU2 use entity ecp3.CU2(V); end for;
+        for all:FADD2B use entity ecp3.FADD2B(V); end for;
+        for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
+        for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
+        for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
+        for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
+        for all:INV use entity ecp3.INV(V); end for;
+        for all:OR2 use entity ecp3.OR2(V); end for;
+        for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
+        for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for;
+        for all:VHI use entity ecp3.VHI(V); end for;
+        for all:VLO use entity ecp3.VLO(V); end for;
+        for all:XOR2 use entity ecp3.XOR2(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on
diff --git a/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.ipx b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.ipx
new file mode 100644
index 0000000..f19145b
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.ipx
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="serdes_sync_200_full" module="serdes_sync_200_full" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 11 27 15:50:28.339" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="serdes_sync_200_full.lpc" type="lpc" modified="2014 11 27 15:50:24.795"/>
+		<File name="serdes_sync_200_full.pp" type="pp" modified="2014 11 27 15:50:24.796"/>
+		<File name="serdes_sync_200_full.sym" type="sym" modified="2014 11 27 15:50:25.058"/>
+		<File name="serdes_sync_200_full.tft" type="tft" modified="2014 11 27 15:50:24.828"/>
+		<File name="serdes_sync_200_full.txt" type="pcs_module" modified="2014 11 27 15:50:24.831"/>
+		<File name="serdes_sync_200_full.vhd" type="top_level_vhdl" modified="2014 11 27 15:50:24.827"/>
+  </Package>
+</DiamondModule>
diff --git a/code/ip/serdes_4_sync_downstream.lpc b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.lpc
similarity index 92%
rename from code/ip/serdes_4_sync_downstream.lpc
rename to hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.lpc
index d4653b9..4341888 100644
--- a/code/ip/serdes_4_sync_downstream.lpc
+++ b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.lpc
@@ -13,11 +13,11 @@ CoreType=LPM
 CoreStatus=Demo
 CoreName=PCS
 CoreRevision=8.2
-ModuleName=serdes_4_sync_downstream
+ModuleName=serdes_sync_200_full
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=02/19/2015
-Time=11:41:22
+Date=11/27/2014
+Time=15:50:24
 
 [Parameters]
 Verilog=0
@@ -99,10 +99,10 @@ _rx_ficlk_rate0=200
 _rx_ficlk_rate1=200
 _rx_ficlk_rate2=200
 _rx_ficlk_rate3=200
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
+_tdrv_ch0=1
+_tdrv_ch1=1
+_tdrv_ch2=1
+_tdrv_ch3=1
 _tx_pre0=DISABLED
 _tx_pre1=DISABLED
 _tx_pre2=DISABLED
@@ -136,8 +136,8 @@ _los_threshold_hi1=7
 _los_threshold_hi2=7
 _los_threshold_hi3=7
 _pll_term=50
-_pll_dcc=DC
-_pll_lol_set=0
+_pll_dcc=AC
+_pll_lol_set=1
 _tx_sb0=DISABLED
 _tx_sb1=DISABLED
 _tx_sb2=DISABLED
@@ -244,15 +244,15 @@ _rx_los_port2=Internal
 _rx_los_port3=Internal
 _sci_ports=ENABLED
 _sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
+_refck2core=DISABLED
+Regen=auto
 PAR1=0
 PARTrace1=0
 PAR3=0
 PARTrace3=0
 
 [FilesGenerated]
-serdes_4_sync_downstream.pp=pp
-serdes_4_sync_downstream.tft=tft
-serdes_4_sync_downstream.txt=pcs_module
-serdes_4_sync_downstream.sym=sym
+serdes_sync_200_full.pp=pp
+serdes_sync_200_full.tft=tft
+serdes_sync_200_full.txt=pcs_module
+serdes_sync_200_full.sym=sym
diff --git a/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.pp b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.pp
new file mode 100644
index 0000000..29a5647
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.pp
@@ -0,0 +1,191 @@
+#define _device_name "LFE3-150EA"
+#define _ch0_pll_rxsrc "REFCLK_CORE"
+#define _ch0_mode "RXTX"
+#define _ch0_protocol "G8B10B"
+#define _ch0_ldr "DISABLED"
+#define _ch0_tx_data_rate "FULL"
+#define _ch0_tx_data_width "8"
+#define _ch0_tx_fifo "DISABLED"
+#define _ch0_tx_ficlk_rate 200
+#define _ch0_rx_datarange "MEDHIGH"
+#define _ch0_rx_data_rate "FULL"
+#define _ch0_rxrefclk_rate "200"
+#define _ch0_rx_data_width "8"
+#define _ch0_rx_fifo "ENABLED"
+#define _ch0_rx_ficlk_rate 200
+#define _ch0_tdrv "1"
+#define _ch0_tx_pre "DISABLED"
+#define _ch0_rterm_tx "50"
+#define _ch0_rx_eq "DISABLED"
+#define _ch0_rterm_rx "50"
+#define _ch0_rx_dcc "DC"
+#define _los_threshold_lo0 "2"
+#define _ch0_tx_sb "DISABLED"
+#define _ch0_tx_8b10b "ENABLED"
+#define _ch0_rx_sb "DISABLED"
+#define _ch0_ird "DISABLED"
+#define _ch0_rx_8b10b "ENABLED"
+#define _ch0_rxwa "ENABLED"
+#define _ch0_ilsm "ENABLED"
+#define _ch0_scomma "K28P157"
+#define _ch0_comma_a "1100000101"
+#define _ch0_comma_b "0011111010"
+#define _ch0_comma_m "1111111100"
+#define _ch0_ctc "DISABLED"
+#define _ch0_cc_match_mode "1"
+#define _ch0_byten "0000011100"
+#define _ch0_byten1 "0000000000"
+#define _ch0_byten2 "0100011100"
+#define _ch0_byten3 "0100011100"
+#define _ch0_cc_min_ipg "3"
+#define _ch0_lbtype "DISABLED"
+#define _ch0_teidle "DISABLED"
+#define _ch0_rx_lol_port "INTERNAL"
+
+#define _ch1_pll_rxsrc "REFCLK_CORE"
+#define _ch1_mode "RXTX"
+#define _ch1_protocol "G8B10B"
+#define _ch1_ldr "DISABLED"
+#define _ch1_tx_data_rate "FULL"
+#define _ch1_tx_data_width "8"
+#define _ch1_tx_fifo "DISABLED"
+#define _ch1_tx_ficlk_rate 200
+#define _ch1_rx_datarange "MEDHIGH"
+#define _ch1_rx_data_rate "FULL"
+#define _ch1_rxrefclk_rate "200"
+#define _ch1_rx_data_width "8"
+#define _ch1_rx_fifo "ENABLED"
+#define _ch1_rx_ficlk_rate 200
+#define _ch1_tdrv "1"
+#define _ch1_tx_pre "DISABLED"
+#define _ch1_rterm_tx "50"
+#define _ch1_rx_eq "DISABLED"
+#define _ch1_rterm_rx "50"
+#define _ch1_rx_dcc "DC"
+#define _los_threshold_lo1 "2"
+#define _ch1_tx_sb "DISABLED"
+#define _ch1_tx_8b10b "ENABLED"
+#define _ch1_rx_sb "DISABLED"
+#define _ch1_ird "DISABLED"
+#define _ch1_rx_8b10b "ENABLED"
+#define _ch1_rxwa "ENABLED"
+#define _ch1_ilsm "ENABLED"
+#define _ch1_scomma "K28P157"
+#define _ch1_comma_a "1100000101"
+#define _ch1_comma_b "0011111010"
+#define _ch1_comma_m "1111111100"
+#define _ch1_ctc "DISABLED"
+#define _ch1_cc_match_mode "1"
+#define _ch1_byten "0000011100"
+#define _ch1_byten1 "0000000000"
+#define _ch1_byten2 "0100011100"
+#define _ch1_byten3 "0100011100"
+#define _ch1_cc_min_ipg "3"
+#define _ch1_lbtype "DISABLED"
+#define _ch1_teidle "DISABLED"
+#define _ch1_rx_lol_port "INTERNAL"
+
+#define _ch2_pll_rxsrc "REFCLK_CORE"
+#define _ch2_mode "RXTX"
+#define _ch2_protocol "G8B10B"
+#define _ch2_ldr "DISABLED"
+#define _ch2_tx_data_rate "FULL"
+#define _ch2_tx_data_width "8"
+#define _ch2_tx_fifo "DISABLED"
+#define _ch2_tx_ficlk_rate 200
+#define _ch2_rx_datarange "MEDHIGH"
+#define _ch2_rx_data_rate "FULL"
+#define _ch2_rxrefclk_rate "200"
+#define _ch2_rx_data_width "8"
+#define _ch2_rx_fifo "ENABLED"
+#define _ch2_rx_ficlk_rate 200
+#define _ch2_tdrv "1"
+#define _ch2_tx_pre "DISABLED"
+#define _ch2_rterm_tx "50"
+#define _ch2_rx_eq "DISABLED"
+#define _ch2_rterm_rx "50"
+#define _ch2_rx_dcc "DC"
+#define _los_threshold_lo2 "2"
+#define _ch2_tx_sb "DISABLED"
+#define _ch2_tx_8b10b "ENABLED"
+#define _ch2_rx_sb "DISABLED"
+#define _ch2_ird "DISABLED"
+#define _ch2_rx_8b10b "ENABLED"
+#define _ch2_rxwa "ENABLED"
+#define _ch2_ilsm "ENABLED"
+#define _ch2_scomma "K28P157"
+#define _ch2_comma_a "1100000101"
+#define _ch2_comma_b "0011111010"
+#define _ch2_comma_m "1111111100"
+#define _ch2_ctc "DISABLED"
+#define _ch2_cc_match_mode "1"
+#define _ch2_byten "0000011100"
+#define _ch2_byten1 "0000000000"
+#define _ch2_byten2 "0100011100"
+#define _ch2_byten3 "0100011100"
+#define _ch2_cc_min_ipg "3"
+#define _ch2_lbtype "DISABLED"
+#define _ch2_teidle "DISABLED"
+#define _ch2_rx_lol_port "INTERNAL"
+
+#define _ch3_pll_rxsrc "REFCLK_CORE"
+#define _ch3_mode "RXTX"
+#define _ch3_protocol "G8B10B"
+#define _ch3_ldr "DISABLED"
+#define _ch3_tx_data_rate "FULL"
+#define _ch3_tx_data_width "8"
+#define _ch3_tx_fifo "DISABLED"
+#define _ch3_tx_ficlk_rate 200
+#define _ch3_rx_datarange "MEDHIGH"
+#define _ch3_rx_data_rate "FULL"
+#define _ch3_rxrefclk_rate "200"
+#define _ch3_rx_data_width "8"
+#define _ch3_rx_fifo "ENABLED"
+#define _ch3_rx_ficlk_rate 200
+#define _ch3_tdrv "1"
+#define _ch3_tx_pre "DISABLED"
+#define _ch3_rterm_tx "50"
+#define _ch3_rx_eq "DISABLED"
+#define _ch3_rterm_rx "50"
+#define _ch3_rx_dcc "DC"
+#define _los_threshold_lo3 "2"
+#define _ch3_tx_sb "DISABLED"
+#define _ch3_tx_8b10b "ENABLED"
+#define _ch3_rx_sb "DISABLED"
+#define _ch3_ird "DISABLED"
+#define _ch3_rx_8b10b "ENABLED"
+#define _ch3_rxwa "ENABLED"
+#define _ch3_ilsm "ENABLED"
+#define _ch3_scomma "K28P157"
+#define _ch3_comma_a "1100000101"
+#define _ch3_comma_b "0011111010"
+#define _ch3_comma_m "1111111100"
+#define _ch3_ctc "DISABLED"
+#define _ch3_cc_match_mode "1"
+#define _ch3_byten "0000011100"
+#define _ch3_byten1 "0000000000"
+#define _ch3_byten2 "0100011100"
+#define _ch3_byten3 "0100011100"
+#define _ch3_cc_min_ipg "3"
+#define _ch3_lbtype "DISABLED"
+#define _ch3_teidle "DISABLED"
+#define _ch3_rx_lol_port "INTERNAL"
+
+#define _datarange "MEDHIGH"
+#define _pll_txsrc "REFCLK_CORE"
+#define _refclk_mult "10X"
+#define _refclk_rate 200
+#define _pll_term "50"
+#define _pll_dcc "AC"
+#define _pll_lol_set "1"
+#define _cchmark "9"
+#define _cclmark "7"
+#define _rst_gen "DISABLED"
+#define _sci_ports "ENABLED"
+#define _sci_int_port "DISABLED"
+#define _refck2core "DISABLED"
+#define _circuit_name serdes_sync_200_full
+#define _lang vhdl
+
+#include <pcs/PCSD.vhd>
+#include <pcs/pcsd_cfg.txt>
diff --git a/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.tft b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.tft
new file mode 100644
index 0000000..b9db080
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.tft
@@ -0,0 +1,100 @@
+@set suppresnewline=on@
+
+@comment --------------------------------------------------------------------- @
+@comment Template-drive TFI generator                                          @
+@comment Template for TFI generation.                                          @
+@comment --------------------------------------------------------------------- @
+
+@set suppresnewline=off@
+ TOOL:     orcapp
+ DATE:     19-MAR-2008 13:11:52
+ TITLE:    %title%
+ MODULE:   %module%
+ DESIGN:   %module%
+ FILENAME: %filename%
+ PROJECT:  %project%
+ VERSION:  %ver%
+ This file is auto generated by the ispLEVER
+@set suppresnewline=on@
+
+@cr@
+@cr@
+
+@set sigdelim=@
+
+NOTE: This readme file has been provided to instantiate the interface@cr@
+netlist.  Since this template contains synthesis attributes for precision that@cr@
+are crucial to the design flow, we recommend that you use this@cr@
+template in your FPGA design.@cr@
+entity chip is@cr@
+port (@cr@
+@cr@
+--  Add your FPGA design top level I/Os here@cr@
+@cr@
+@cr@
+-- ASIC side pins for PCSD.  These pins must exist for the@cr@
+-- PCS core.@cr@
+  refclkp         : in std_logic;@cr@
+  refclkn         : in std_logic;@cr@
+  hdinp_ch0          : in std_logic;@cr@
+  hdinn_ch0          : in std_logic;@cr@
+  hdinp_ch1          : in std_logic;@cr@
+  hdinn_ch1          : in std_logic;@cr@
+  hdinp_ch2          : in std_logic;@cr@
+  hdinn_ch2          : in std_logic;@cr@
+  hdinp_ch3          : in std_logic;@cr@
+  hdinn_ch3          : in std_logic;@cr@
+@cr@
+  hdoutp_ch0         : out std_logic;@cr@
+  hdoutn_ch0         : out std_logic;@cr@
+  hdoutp_ch1         : out std_logic;@cr@
+  hdoutn_ch1         : out std_logic;@cr@
+  hdoutp_ch2         : out std_logic;@cr@
+  hdoutn_ch2         : out std_logic;@cr@
+  hdoutp_ch3         : out std_logic;@cr@
+  hdoutn_ch3         : out std_logic;@cr@
+@cr@
+@cr@
+);@cr@
+end chip;@cr@
+@cr@
+architecture chip_arch of chip is@cr@
+@cr@
+-- This defines all the high-speed ports. You may have to remove@cr@
+-- some of them depending on your design.@cr@
+attribute nopad : string;@cr@
+attribute nopad of@cr@
+  refclkp, refclkn,@cr@
+  hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
+  hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
+  hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
+  hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
+
+@cr@
+@tab@COMPONENT %module%
+@set sigdelim=@
+@cr@@tab@PORT(
+@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
+@ifhas oport=*@ @comment if the design has any output ports... @
+   @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
+   @set sigdelim=;@
+   @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
+@endif@
+@ifnhas oport=*@ @comment we need an "else in this language! @
+   @set sigdelim=;@
+   @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
+@endif@
+@cr@@tab@@tab@);@cr@
+@tab@END COMPONENT;@cr@@cr@
+@comment Now do a signal declaration for each port @
+
+@cr@@cr@
+@comment do the component instantiation                                    @
+@set sigdelim=,@
+@tab@uut: %module% PORT MAP(
+@iterate@%port%
+@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
+@cr@@tab@);@cr@@cr@
+@set suppresnewline=off@
+
+
diff --git a/code/ip/serdes_4_sync_downstream.txt b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.txt
similarity index 96%
rename from code/ip/serdes_4_sync_downstream.txt
rename to hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.txt
index 8e076a7..d303ba1 100644
--- a/code/ip/serdes_4_sync_downstream.txt
+++ b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.txt
@@ -48,10 +48,10 @@ CH0_RX_FIFO        "ENABLED"
 CH1_RX_FIFO        "ENABLED"
 CH2_RX_FIFO        "ENABLED"
 CH3_RX_FIFO        "ENABLED"
-CH0_TDRV      "0"
-CH1_TDRV      "0"
-CH2_TDRV      "0"
-CH3_TDRV      "0"
+CH0_TDRV      "1"
+CH1_TDRV      "1"
+CH2_TDRV      "1"
+CH3_TDRV      "1"
 #CH0_TX_FICLK_RATE      200
 #CH1_TX_FICLK_RATE      200
 #CH2_TX_FICLK_RATE      200
@@ -89,8 +89,8 @@ CH1_LOS_THRESHOLD_LO       "2"
 CH2_LOS_THRESHOLD_LO       "2"
 CH3_LOS_THRESHOLD_LO       "2"
 PLL_TERM                "50"
-PLL_DCC                 "DC"
-PLL_LOL_SET             "0"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "1"
 CH0_TX_SB               "DISABLED"
 CH1_TX_SB               "DISABLED"
 CH2_TX_SB               "DISABLED"
@@ -158,6 +158,6 @@ CH1_PCSLBPORTS          "DISABLED"
 CH2_PCSLBPORTS          "DISABLED"
 CH3_PCSLBPORTS          "DISABLED"
 INT_ALL                 "DISABLED"
-QD_REFCK2CORE           "ENABLED"
+QD_REFCK2CORE           "DISABLED"
 
 
diff --git a/code/ip/serdes_4_sync_downstream.vhd b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.vhd
similarity index 99%
rename from code/ip/serdes_4_sync_downstream.vhd
rename to hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.vhd
index f772fcd..a555326 100644
--- a/code/ip/serdes_4_sync_downstream.vhd
+++ b/hub_SODA/sources/lattice/ecp3/serdes_sync_200_full.vhd
@@ -17,7 +17,7 @@ GENERIC(
   CH2_CDR_SRC   : String := "REFCLK_EXT";
   CH3_CDR_SRC   : String := "REFCLK_EXT";
   PLL_SRC   : String
---  CONFIG_FILE : String  := "serdes_4_sync_downstream.txt";
+--  CONFIG_FILE : String  := "serdes_sync_200_full.txt";
 --  QUAD_MODE : String := "SINGLE";
 --  CH0_CDR_SRC   : String := "REFCLK_CORE";
 --  CH1_CDR_SRC   : String := "REFCLK_CORE";
@@ -1530,8 +1530,8 @@ library IEEE, STD;
 use IEEE.std_logic_1164.all;
 use STD.TEXTIO.all;
 
-entity serdes_4_sync_downstream is
-   GENERIC (USER_CONFIG_FILE    :  String := "serdes_4_sync_downstream.txt");
+entity serdes_sync_200_full is
+   GENERIC (USER_CONFIG_FILE    :  String := "serdes_sync_200_full.txt");
  port (
 ------------------
 -- CH0 --
@@ -1670,13 +1670,12 @@ entity serdes_4_sync_downstream is
     tx_pll_lol_qd_s   :   out std_logic;
     tx_sync_qd_c    :   in std_logic;
     rst_qd_c    :   in std_logic;
-    refclk2fpga   :   out std_logic;
     serdes_rst_qd_c    :   in std_logic);
 
-end serdes_4_sync_downstream;
+end serdes_sync_200_full;
 
 
-architecture serdes_4_sync_downstream_arch of serdes_4_sync_downstream is
+architecture serdes_sync_200_full_arch of serdes_sync_200_full is
 
 component VLO
 port (
@@ -2234,8 +2233,6 @@ end component;
    attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
    attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
    attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_REFCK2CORE: string;
-   attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
    attribute black_box_pad_pin: string;
    attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
 
@@ -2269,7 +2266,6 @@ begin
 vlo_inst : VLO port map(Z => fpsc_vlo);
 vhi_inst : VHI port map(Z => fpsc_vhi);
 
-  refclk2fpga <= refclk2fpga_sig;
     rx_los_low_ch0_s <= rx_los_low_ch0_sig;
     rx_los_low_ch1_s <= rx_los_low_ch1_sig;
     rx_los_low_ch2_s <= rx_los_low_ch2_sig;
@@ -2811,4 +2807,4 @@ BEGIN
    wait;
 END PROCESS;
 --synopsys translate_on
-end serdes_4_sync_downstream_arch ;
+end serdes_sync_200_full_arch ;
diff --git a/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.ipx b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.ipx
new file mode 100644
index 0000000..d072c41
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.ipx
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="sfp_3sync_200_int" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 07 13 09:03:34.099" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+  <Package>
+		<File name="sfp_3sync_200_int.lpc" type="lpc" modified="2015 07 13 09:03:29.063"/>
+		<File name="sfp_3sync_200_int.pp" type="pp" modified="2015 07 13 09:03:29.065"/>
+		<File name="sfp_3sync_200_int.sym" type="sym" modified="2015 07 13 09:03:29.325"/>
+		<File name="sfp_3sync_200_int.tft" type="tft" modified="2015 07 13 09:03:29.097"/>
+		<File name="sfp_3sync_200_int.txt" type="pcs_module" modified="2015 07 13 09:03:29.100"/>
+		<File name="sfp_3sync_200_int.vhd" type="top_level_vhdl" modified="2015 07 13 09:03:29.096"/>
+  </Package>
+</DiamondModule>
diff --git a/code/ip/serdes_sync_upstream.lpc b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.lpc
similarity index 87%
rename from code/ip/serdes_sync_upstream.lpc
rename to hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.lpc
index edc2b42..41214b1 100644
--- a/code/ip/serdes_sync_upstream.lpc
+++ b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.lpc
@@ -13,11 +13,11 @@ CoreType=LPM
 CoreStatus=Demo
 CoreName=PCS
 CoreRevision=8.2
-ModuleName=serdes_sync_upstream
+ModuleName=sfp_3sync_200_int
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=03/04/2015
-Time=13:04:49
+Date=07/13/2015
+Time=09:03:29
 
 [Parameters]
 Verilog=0
@@ -29,8 +29,8 @@ Order=Big Endian [MSB:LSB]
 IO=0
 _mode0=DISABLED
 _mode1=DISABLED
-_mode2=DISABLED
-_mode3=RXTX
+_mode2=RXTX
+_mode3=DISABLED
 _protocol0=G8B10B
 _protocol1=G8B10B
 _protocol2=G8B10B
@@ -45,8 +45,8 @@ _refclk_mult=10X
 _refclk_rate=200
 _tx_protocol0=DISABLED
 _tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=G8B10B
+_tx_protocol2=G8B10B
+_tx_protocol3=DISABLED
 _tx_data_rate0=FULL
 _tx_data_rate1=FULL
 _tx_data_rate2=FULL
@@ -57,36 +57,36 @@ _tx_data_width2=8
 _tx_data_width3=8
 _tx_fifo0=ENABLED
 _tx_fifo1=ENABLED
-_tx_fifo2=ENABLED
-_tx_fifo3=DISABLED
+_tx_fifo2=DISABLED
+_tx_fifo3=ENABLED
 _tx_ficlk_rate0=200
 _tx_ficlk_rate1=200
 _tx_ficlk_rate2=200
 _tx_ficlk_rate3=200
 _pll_rxsrc0=EXTERNAL
 _pll_rxsrc1=EXTERNAL
-_pll_rxsrc2=EXTERNAL
-_pll_rxsrc3=INTERNAL
+_pll_rxsrc2=INTERNAL
+_pll_rxsrc3=EXTERNAL
 Multiplier0=
 Multiplier1=
 Multiplier2=
 Multiplier3=
 _rx_datarange0=2.5
 _rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=2
+_rx_datarange2=2
+_rx_datarange3=2.5
 _rx_protocol0=DISABLED
 _rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=G8B10B
+_rx_protocol2=G8B10B
+_rx_protocol3=DISABLED
 _rx_data_rate0=FULL
 _rx_data_rate1=FULL
 _rx_data_rate2=FULL
 _rx_data_rate3=FULL
 _rxrefclk_rate0=250.0
 _rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=200
+_rxrefclk_rate2=200
+_rxrefclk_rate3=250.0
 _rx_data_width0=8
 _rx_data_width1=8
 _rx_data_width2=8
@@ -94,11 +94,11 @@ _rx_data_width3=8
 _rx_fifo0=ENABLED
 _rx_fifo1=ENABLED
 _rx_fifo2=ENABLED
-_rx_fifo3=DISABLED
+_rx_fifo3=ENABLED
 _rx_ficlk_rate0=250.0
 _rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=200
+_rx_ficlk_rate2=200
+_rx_ficlk_rate3=250.0
 _tdrv_ch0=0
 _tdrv_ch1=0
 _tdrv_ch2=0
@@ -121,8 +121,8 @@ _rterm_rx2=50
 _rterm_rx3=50
 _rx_dcc0=AC
 _rx_dcc1=AC
-_rx_dcc2=AC
-_rx_dcc3=DC
+_rx_dcc2=DC
+_rx_dcc3=AC
 _los_threshold_mode0=LOS_E
 _los_threshold_mode1=LOS_E
 _los_threshold_mode2=LOS_E
@@ -244,15 +244,15 @@ _rx_los_port2=Internal
 _rx_los_port3=Internal
 _sci_ports=ENABLED
 _sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
+_refck2core=DISABLED
+Regen=auto
 PAR1=0
 PARTrace1=0
 PAR3=0
 PARTrace3=0
 
 [FilesGenerated]
-serdes_sync_upstream.pp=pp
-serdes_sync_upstream.tft=tft
-serdes_sync_upstream.txt=pcs_module
-serdes_sync_upstream.sym=sym
+sfp_3sync_200_int.pp=pp
+sfp_3sync_200_int.tft=tft
+sfp_3sync_200_int.txt=pcs_module
+sfp_3sync_200_int.sym=sym
diff --git a/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.pp b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.pp
new file mode 100644
index 0000000..bec2cc4
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.pp
@@ -0,0 +1,191 @@
+#define _device_name "LFE3-150EA"
+#define _ch0_pll_rxsrc "REFCLK_EXT"
+#define _ch0_mode "DISABLED"
+#define _ch0_protocol "G8B10B"
+#define _ch0_ldr "DISABLED"
+#define _ch0_tx_data_rate "FULL"
+#define _ch0_tx_data_width "8"
+#define _ch0_tx_fifo "ENABLED"
+#define _ch0_tx_ficlk_rate 200
+#define _ch0_rx_datarange "MEDHIGH"
+#define _ch0_rx_data_rate "FULL"
+#define _ch0_rxrefclk_rate "250.0"
+#define _ch0_rx_data_width "8"
+#define _ch0_rx_fifo "ENABLED"
+#define _ch0_rx_ficlk_rate 250.0
+#define _ch0_tdrv "0"
+#define _ch0_tx_pre "DISABLED"
+#define _ch0_rterm_tx "50"
+#define _ch0_rx_eq "DISABLED"
+#define _ch0_rterm_rx "50"
+#define _ch0_rx_dcc "AC"
+#define _los_threshold_lo0 "2"
+#define _ch0_tx_sb "DISABLED"
+#define _ch0_tx_8b10b "ENABLED"
+#define _ch0_rx_sb "DISABLED"
+#define _ch0_ird "DISABLED"
+#define _ch0_rx_8b10b "ENABLED"
+#define _ch0_rxwa "ENABLED"
+#define _ch0_ilsm "ENABLED"
+#define _ch0_scomma "K28P157"
+#define _ch0_comma_a "1100000101"
+#define _ch0_comma_b "0011111010"
+#define _ch0_comma_m "1111111100"
+#define _ch0_ctc "DISABLED"
+#define _ch0_cc_match_mode "1"
+#define _ch0_byten "0000000000"
+#define _ch0_byten1 "0000000000"
+#define _ch0_byten2 "0100011100"
+#define _ch0_byten3 "0100011100"
+#define _ch0_cc_min_ipg "3"
+#define _ch0_lbtype "DISABLED"
+#define _ch0_teidle "DISABLED"
+#define _ch0_rx_lol_port "INTERNAL"
+
+#define _ch1_pll_rxsrc "REFCLK_EXT"
+#define _ch1_mode "DISABLED"
+#define _ch1_protocol "G8B10B"
+#define _ch1_ldr "DISABLED"
+#define _ch1_tx_data_rate "FULL"
+#define _ch1_tx_data_width "8"
+#define _ch1_tx_fifo "ENABLED"
+#define _ch1_tx_ficlk_rate 200
+#define _ch1_rx_datarange "MEDHIGH"
+#define _ch1_rx_data_rate "FULL"
+#define _ch1_rxrefclk_rate "250.0"
+#define _ch1_rx_data_width "8"
+#define _ch1_rx_fifo "ENABLED"
+#define _ch1_rx_ficlk_rate 250.0
+#define _ch1_tdrv "0"
+#define _ch1_tx_pre "DISABLED"
+#define _ch1_rterm_tx "50"
+#define _ch1_rx_eq "DISABLED"
+#define _ch1_rterm_rx "50"
+#define _ch1_rx_dcc "AC"
+#define _los_threshold_lo1 "2"
+#define _ch1_tx_sb "DISABLED"
+#define _ch1_tx_8b10b "ENABLED"
+#define _ch1_rx_sb "DISABLED"
+#define _ch1_ird "DISABLED"
+#define _ch1_rx_8b10b "ENABLED"
+#define _ch1_rxwa "ENABLED"
+#define _ch1_ilsm "ENABLED"
+#define _ch1_scomma "K28P157"
+#define _ch1_comma_a "1100000101"
+#define _ch1_comma_b "0011111010"
+#define _ch1_comma_m "1111111100"
+#define _ch1_ctc "DISABLED"
+#define _ch1_cc_match_mode "1"
+#define _ch1_byten "0000000000"
+#define _ch1_byten1 "0000000000"
+#define _ch1_byten2 "0100011100"
+#define _ch1_byten3 "0100011100"
+#define _ch1_cc_min_ipg "3"
+#define _ch1_lbtype "DISABLED"
+#define _ch1_teidle "DISABLED"
+#define _ch1_rx_lol_port "INTERNAL"
+
+#define _ch2_pll_rxsrc "REFCLK_CORE"
+#define _ch2_mode "RXTX"
+#define _ch2_protocol "G8B10B"
+#define _ch2_ldr "DISABLED"
+#define _ch2_tx_data_rate "FULL"
+#define _ch2_tx_data_width "8"
+#define _ch2_tx_fifo "DISABLED"
+#define _ch2_tx_ficlk_rate 200
+#define _ch2_rx_datarange "MEDHIGH"
+#define _ch2_rx_data_rate "FULL"
+#define _ch2_rxrefclk_rate "200"
+#define _ch2_rx_data_width "8"
+#define _ch2_rx_fifo "ENABLED"
+#define _ch2_rx_ficlk_rate 200
+#define _ch2_tdrv "0"
+#define _ch2_tx_pre "DISABLED"
+#define _ch2_rterm_tx "50"
+#define _ch2_rx_eq "DISABLED"
+#define _ch2_rterm_rx "50"
+#define _ch2_rx_dcc "DC"
+#define _los_threshold_lo2 "2"
+#define _ch2_tx_sb "DISABLED"
+#define _ch2_tx_8b10b "ENABLED"
+#define _ch2_rx_sb "DISABLED"
+#define _ch2_ird "DISABLED"
+#define _ch2_rx_8b10b "ENABLED"
+#define _ch2_rxwa "ENABLED"
+#define _ch2_ilsm "ENABLED"
+#define _ch2_scomma "K28P157"
+#define _ch2_comma_a "1100000101"
+#define _ch2_comma_b "0011111010"
+#define _ch2_comma_m "1111111100"
+#define _ch2_ctc "DISABLED"
+#define _ch2_cc_match_mode "1"
+#define _ch2_byten "0000000000"
+#define _ch2_byten1 "0000000000"
+#define _ch2_byten2 "0100011100"
+#define _ch2_byten3 "0100011100"
+#define _ch2_cc_min_ipg "3"
+#define _ch2_lbtype "DISABLED"
+#define _ch2_teidle "DISABLED"
+#define _ch2_rx_lol_port "INTERNAL"
+
+#define _ch3_pll_rxsrc "REFCLK_EXT"
+#define _ch3_mode "DISABLED"
+#define _ch3_protocol "G8B10B"
+#define _ch3_ldr "DISABLED"
+#define _ch3_tx_data_rate "FULL"
+#define _ch3_tx_data_width "8"
+#define _ch3_tx_fifo "ENABLED"
+#define _ch3_tx_ficlk_rate 200
+#define _ch3_rx_datarange "MEDHIGH"
+#define _ch3_rx_data_rate "FULL"
+#define _ch3_rxrefclk_rate "250.0"
+#define _ch3_rx_data_width "8"
+#define _ch3_rx_fifo "ENABLED"
+#define _ch3_rx_ficlk_rate 250.0
+#define _ch3_tdrv "0"
+#define _ch3_tx_pre "DISABLED"
+#define _ch3_rterm_tx "50"
+#define _ch3_rx_eq "DISABLED"
+#define _ch3_rterm_rx "50"
+#define _ch3_rx_dcc "AC"
+#define _los_threshold_lo3 "2"
+#define _ch3_tx_sb "DISABLED"
+#define _ch3_tx_8b10b "ENABLED"
+#define _ch3_rx_sb "DISABLED"
+#define _ch3_ird "DISABLED"
+#define _ch3_rx_8b10b "ENABLED"
+#define _ch3_rxwa "ENABLED"
+#define _ch3_ilsm "ENABLED"
+#define _ch3_scomma "K28P157"
+#define _ch3_comma_a "1100000101"
+#define _ch3_comma_b "0011111010"
+#define _ch3_comma_m "1111111100"
+#define _ch3_ctc "DISABLED"
+#define _ch3_cc_match_mode "1"
+#define _ch3_byten "0000000000"
+#define _ch3_byten1 "0000000000"
+#define _ch3_byten2 "0100011100"
+#define _ch3_byten3 "0100011100"
+#define _ch3_cc_min_ipg "3"
+#define _ch3_lbtype "DISABLED"
+#define _ch3_teidle "DISABLED"
+#define _ch3_rx_lol_port "INTERNAL"
+
+#define _datarange "MEDHIGH"
+#define _pll_txsrc "REFCLK_CORE"
+#define _refclk_mult "10X"
+#define _refclk_rate 200
+#define _pll_term "50"
+#define _pll_dcc "AC"
+#define _pll_lol_set "0"
+#define _cchmark "9"
+#define _cclmark "7"
+#define _rst_gen "DISABLED"
+#define _sci_ports "ENABLED"
+#define _sci_int_port "DISABLED"
+#define _refck2core "DISABLED"
+#define _circuit_name sfp_3sync_200_int
+#define _lang vhdl
+
+#include <pcs/PCSD.vhd>
+#include <pcs/pcsd_cfg.txt>
diff --git a/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.tft b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.tft
new file mode 100644
index 0000000..b9db080
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.tft
@@ -0,0 +1,100 @@
+@set suppresnewline=on@
+
+@comment --------------------------------------------------------------------- @
+@comment Template-drive TFI generator                                          @
+@comment Template for TFI generation.                                          @
+@comment --------------------------------------------------------------------- @
+
+@set suppresnewline=off@
+ TOOL:     orcapp
+ DATE:     19-MAR-2008 13:11:52
+ TITLE:    %title%
+ MODULE:   %module%
+ DESIGN:   %module%
+ FILENAME: %filename%
+ PROJECT:  %project%
+ VERSION:  %ver%
+ This file is auto generated by the ispLEVER
+@set suppresnewline=on@
+
+@cr@
+@cr@
+
+@set sigdelim=@
+
+NOTE: This readme file has been provided to instantiate the interface@cr@
+netlist.  Since this template contains synthesis attributes for precision that@cr@
+are crucial to the design flow, we recommend that you use this@cr@
+template in your FPGA design.@cr@
+entity chip is@cr@
+port (@cr@
+@cr@
+--  Add your FPGA design top level I/Os here@cr@
+@cr@
+@cr@
+-- ASIC side pins for PCSD.  These pins must exist for the@cr@
+-- PCS core.@cr@
+  refclkp         : in std_logic;@cr@
+  refclkn         : in std_logic;@cr@
+  hdinp_ch0          : in std_logic;@cr@
+  hdinn_ch0          : in std_logic;@cr@
+  hdinp_ch1          : in std_logic;@cr@
+  hdinn_ch1          : in std_logic;@cr@
+  hdinp_ch2          : in std_logic;@cr@
+  hdinn_ch2          : in std_logic;@cr@
+  hdinp_ch3          : in std_logic;@cr@
+  hdinn_ch3          : in std_logic;@cr@
+@cr@
+  hdoutp_ch0         : out std_logic;@cr@
+  hdoutn_ch0         : out std_logic;@cr@
+  hdoutp_ch1         : out std_logic;@cr@
+  hdoutn_ch1         : out std_logic;@cr@
+  hdoutp_ch2         : out std_logic;@cr@
+  hdoutn_ch2         : out std_logic;@cr@
+  hdoutp_ch3         : out std_logic;@cr@
+  hdoutn_ch3         : out std_logic;@cr@
+@cr@
+@cr@
+);@cr@
+end chip;@cr@
+@cr@
+architecture chip_arch of chip is@cr@
+@cr@
+-- This defines all the high-speed ports. You may have to remove@cr@
+-- some of them depending on your design.@cr@
+attribute nopad : string;@cr@
+attribute nopad of@cr@
+  refclkp, refclkn,@cr@
+  hdinp_ch0, hdinn_ch0, hdinp_ch1, hdinn_ch1,@cr@
+  hdinp_ch2, hdinn_ch2, hdinp_ch3, hdinn_ch3,@cr@
+  hdoutp_ch0, hdoutn_ch0, hdoutp_ch1, hdoutn_ch1,@cr@
+  hdoutp_ch2, hdoutn_ch2, hdoutp_ch3, hdoutn_ch3 : signal is "true";@cr@
+
+@cr@
+@tab@COMPONENT %module%
+@set sigdelim=@
+@cr@@tab@PORT(
+@iterate@%iport%@cr@@tab@@tab@@iterator@ : IN @vhdl_typedec@;@enditerate@
+@ifhas oport=*@ @comment if the design has any output ports... @
+   @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@;@enditerate@
+   @set sigdelim=;@
+   @iterate@%oport%@cr@@tab@@tab@@iterator@ : OUT @vhdl_typedec@@enditerate@
+@endif@
+@ifnhas oport=*@ @comment we need an "else in this language! @
+   @set sigdelim=;@
+   @iterate@%bport%@cr@@tab@@tab@@iterator@ : INOUT @vhdl_typedec@@enditerate@
+@endif@
+@cr@@tab@@tab@);@cr@
+@tab@END COMPONENT;@cr@@cr@
+@comment Now do a signal declaration for each port @
+
+@cr@@cr@
+@comment do the component instantiation                                    @
+@set sigdelim=,@
+@tab@uut: %module% PORT MAP(
+@iterate@%port%
+@cr@@tab@@tab@@iterator@ => @iterator@@enditerate@
+@cr@@tab@);@cr@@cr@
+@set suppresnewline=off@
+
+
diff --git a/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.txt b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.txt
new file mode 100644
index 0000000..c9fed33
--- /dev/null
+++ b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.txt
@@ -0,0 +1,58 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH2_PROTOCOL            "G8B10B"
+CH0_MODE                "DISABLED"
+CH1_MODE                "DISABLED"
+CH2_MODE                "RXTX"
+CH3_MODE                "DISABLED"
+CH2_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH2_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH2_RX_DATA_RATE        "FULL"
+CH2_TX_DATA_RATE        "FULL"
+CH2_TX_DATA_WIDTH       "8"
+CH2_RX_DATA_WIDTH        "8"
+CH2_TX_FIFO       "DISABLED"
+CH2_RX_FIFO        "ENABLED"
+CH2_TDRV      "0"
+#CH2_TX_FICLK_RATE      200
+#CH2_RXREFCLK_RATE        "200"
+#CH2_RX_FICLK_RATE      200
+CH2_TX_PRE              "DISABLED"
+CH2_RTERM_TX            "50"
+CH2_RX_EQ               "DISABLED"
+CH2_RTERM_RX            "50"
+CH2_RX_DCC              "DC"
+CH2_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH2_TX_SB               "DISABLED"
+CH2_RX_SB               "DISABLED"
+CH2_TX_8B10B            "ENABLED"
+CH2_RX_8B10B            "ENABLED"
+CH2_COMMA_A             "1100000101"
+CH2_COMMA_B             "0011111010"
+CH2_COMMA_M             "1111111100"
+CH2_RXWA                "ENABLED"
+CH2_ILSM                "ENABLED"
+CH2_CTC                 "DISABLED"
+CH2_CC_MATCH4           "0000000000"
+CH2_CC_MATCH_MODE       "1"
+CH2_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH2_SSLB                "DISABLED"
+CH2_SPLBPORTS           "DISABLED"
+CH2_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "DISABLED"
+
+
diff --git a/code/ip/serdes_sync_upstream.vhd b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.vhd
similarity index 95%
rename from code/ip/serdes_sync_upstream.vhd
rename to hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.vhd
index 3ceaa4f..1d746b4 100644
--- a/code/ip/serdes_sync_upstream.vhd
+++ b/hub_SODA/sources/lattice/ecp3/sfp_3sync_200_int.vhd
@@ -17,12 +17,12 @@ GENERIC(
   CH2_CDR_SRC   : String := "REFCLK_EXT";
   CH3_CDR_SRC   : String := "REFCLK_EXT";
   PLL_SRC   : String
---  CONFIG_FILE : String  := "serdes_sync_upstream.txt";
+--  CONFIG_FILE : String  := "sfp_3sync_200_int.txt";
 --  QUAD_MODE : String := "SINGLE";
 --  CH0_CDR_SRC   : String := "REFCLK_EXT";
 --  CH1_CDR_SRC   : String := "REFCLK_EXT";
---  CH2_CDR_SRC   : String := "REFCLK_EXT";
---  CH3_CDR_SRC   : String := "REFCLK_CORE";
+--  CH2_CDR_SRC   : String := "REFCLK_CORE";
+--  CH3_CDR_SRC   : String := "REFCLK_EXT";
 --  PLL_SRC   : String := "REFCLK_CORE"
   );
 port (
@@ -1530,43 +1530,44 @@ library IEEE, STD;
 use IEEE.std_logic_1164.all;
 use STD.TEXTIO.all;
 
-entity serdes_sync_upstream is
-   GENERIC (USER_CONFIG_FILE    :  String := "serdes_sync_upstream.txt");
+entity sfp_3sync_200_int is
+   GENERIC (USER_CONFIG_FILE    :  String := "sfp_3sync_200_int.txt");
  port (
 ------------------
 -- CH0 --
 -- CH1 --
 -- CH2 --
+    hdinp_ch2, hdinn_ch2    :   in std_logic;
+    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
+    sci_sel_ch2    :   in std_logic;
+    rxiclk_ch2    :   in std_logic;
+    txiclk_ch2    :   in std_logic;
+    rx_full_clk_ch2   :   out std_logic;
+    rx_half_clk_ch2   :   out std_logic;
+    tx_full_clk_ch2   :   out std_logic;
+    tx_half_clk_ch2   :   out std_logic;
+    fpga_rxrefclk_ch2    :   in std_logic;
+    txdata_ch2    :   in std_logic_vector (7 downto 0);
+    tx_k_ch2    :   in std_logic;
+    tx_force_disp_ch2    :   in std_logic;
+    tx_disp_sel_ch2    :   in std_logic;
+    rxdata_ch2   :   out std_logic_vector (7 downto 0);
+    rx_k_ch2   :   out std_logic;
+    rx_disp_err_ch2   :   out std_logic;
+    rx_cv_err_ch2   :   out std_logic;
+    rx_serdes_rst_ch2_c    :   in std_logic;
+    sb_felb_ch2_c    :   in std_logic;
+    sb_felb_rst_ch2_c    :   in std_logic;
+    tx_pcs_rst_ch2_c    :   in std_logic;
+    tx_pwrup_ch2_c    :   in std_logic;
+    rx_pcs_rst_ch2_c    :   in std_logic;
+    rx_pwrup_ch2_c    :   in std_logic;
+    rx_los_low_ch2_s   :   out std_logic;
+    lsm_status_ch2_s   :   out std_logic;
+    rx_cdr_lol_ch2_s   :   out std_logic;
+    tx_div2_mode_ch2_c   : in std_logic;
+    rx_div2_mode_ch2_c   : in std_logic;
 -- CH3 --
-    hdinp_ch3, hdinn_ch3    :   in std_logic;
-    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
-    sci_sel_ch3    :   in std_logic;
-    txiclk_ch3    :   in std_logic;
-    rx_full_clk_ch3   :   out std_logic;
-    rx_half_clk_ch3   :   out std_logic;
-    tx_full_clk_ch3   :   out std_logic;
-    tx_half_clk_ch3   :   out std_logic;
-    fpga_rxrefclk_ch3    :   in std_logic;
-    txdata_ch3    :   in std_logic_vector (7 downto 0);
-    tx_k_ch3    :   in std_logic;
-    tx_force_disp_ch3    :   in std_logic;
-    tx_disp_sel_ch3    :   in std_logic;
-    rxdata_ch3   :   out std_logic_vector (7 downto 0);
-    rx_k_ch3   :   out std_logic;
-    rx_disp_err_ch3   :   out std_logic;
-    rx_cv_err_ch3   :   out std_logic;
-    rx_serdes_rst_ch3_c    :   in std_logic;
-    sb_felb_ch3_c    :   in std_logic;
-    sb_felb_rst_ch3_c    :   in std_logic;
-    tx_pcs_rst_ch3_c    :   in std_logic;
-    tx_pwrup_ch3_c    :   in std_logic;
-    rx_pcs_rst_ch3_c    :   in std_logic;
-    rx_pwrup_ch3_c    :   in std_logic;
-    rx_los_low_ch3_s   :   out std_logic;
-    lsm_status_ch3_s   :   out std_logic;
-    rx_cdr_lol_ch3_s   :   out std_logic;
-    tx_div2_mode_ch3_c   : in std_logic;
-    rx_div2_mode_ch3_c   : in std_logic;
 ---- Miscillaneous ports
     sci_wrdata    :   in std_logic_vector (7 downto 0);
     sci_addr    :   in std_logic_vector (5 downto 0);
@@ -1578,13 +1579,12 @@ entity serdes_sync_upstream is
     tx_serdes_rst_c    :   in std_logic;
     tx_pll_lol_qd_s   :   out std_logic;
     rst_qd_c    :   in std_logic;
-    refclk2fpga   :   out std_logic;
     serdes_rst_qd_c    :   in std_logic);
 
-end serdes_sync_upstream;
+end sfp_3sync_200_int;
 
 
-architecture serdes_sync_upstream_arch of serdes_sync_upstream is
+architecture sfp_3sync_200_int_arch of sfp_3sync_200_int is
 
 component VLO
 port (
@@ -2102,24 +2102,24 @@ end component;
    attribute QUAD_MODE of PCSD_INST : label is "SINGLE";
    attribute PLL_SRC: string;
    attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE";
-   attribute CH3_CDR_SRC: string;
-   attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
+   attribute CH2_CDR_SRC: string;
+   attribute CH2_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
    attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
    attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000";
    attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
    attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
    attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "200";
    attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
+   attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000";
    attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
    attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000";
    attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
    attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
    attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "100";
    attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
-   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
+   attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000";
    attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
    attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
    attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
@@ -2136,8 +2136,6 @@ end component;
    attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
    attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
    attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
-   attribute FREQUENCY_PIN_REFCK2CORE: string;
-   attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
    attribute black_box_pad_pin: string;
    attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
 
@@ -2146,7 +2144,7 @@ signal fpsc_vlo : std_logic := '0';
 signal fpsc_vhi : std_logic := '1';
 signal cin : std_logic_vector (11 downto 0) := "000000000000";
 signal cout : std_logic_vector (19 downto 0);
-signal    tx_full_clk_ch3_sig   :   std_logic;
+signal    tx_full_clk_ch2_sig   :   std_logic;
 
 signal    refclk2fpga_sig  :   std_logic;
 signal    tx_pll_lol_qd_sig  :   std_logic;
@@ -2168,18 +2166,17 @@ begin
 vlo_inst : VLO port map(Z => fpsc_vlo);
 vhi_inst : VHI port map(Z => fpsc_vhi);
 
-  refclk2fpga <= refclk2fpga_sig;
-    rx_los_low_ch3_s <= rx_los_low_ch3_sig;
-    rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
+    rx_los_low_ch2_s <= rx_los_low_ch2_sig;
+    rx_cdr_lol_ch2_s <= rx_cdr_lol_ch2_sig;
   tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
-  tx_full_clk_ch3 <= tx_full_clk_ch3_sig;
+  tx_full_clk_ch2 <= tx_full_clk_ch2_sig;
 
 -- pcs_quad instance
 PCSD_INST : PCSD
 --synopsys translate_off
   generic map (CONFIG_FILE => USER_CONFIG_FILE,
                QUAD_MODE => "SINGLE",
-               CH3_CDR_SRC => "REFCLK_CORE",
+               CH2_CDR_SRC => "REFCLK_CORE",
                PLL_SRC  => "REFCLK_CORE"
   )
 --synopsys translate_on
@@ -2400,10 +2397,10 @@ port map  (
   FFC_RATE_MODE_RX_1 => fpsc_vlo,
 
 ----- CH2 -----
-  HDOUTP2 => open,
-  HDOUTN2 => open,
-  HDINP2 => fpsc_vlo,
-  HDINN2 => fpsc_vlo,
+  HDOUTP2 => hdoutp_ch2,
+  HDOUTN2 => hdoutn_ch2,
+  HDINP2 => hdinp_ch2,
+  HDINN2 => hdinn_ch2,
   PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo,
   PCIE_TXCOMPLIANCE_2 => fpsc_vlo,
   PCIE_RXPOLARITY_2 => fpsc_vlo,
@@ -2411,27 +2408,27 @@ port map  (
   PCIE_POWERDOWN_2_1 => fpsc_vlo,
   PCIE_RXVALID_2 => open,
   PCIE_PHYSTATUS_2 => open,
-  SCISELCH2 => fpsc_vlo,
-  SCIENCH2 => fpsc_vlo,
-  FF_RXI_CLK_2 => fpsc_vlo,
-  FF_TXI_CLK_2 => fpsc_vlo,
+  SCISELCH2 => sci_sel_ch2,
+  SCIENCH2 => fpsc_vhi,
+  FF_RXI_CLK_2 => rxiclk_ch2,
+  FF_TXI_CLK_2 => txiclk_ch2,
   FF_EBRD_CLK_2 => fpsc_vlo,
-  FF_RX_F_CLK_2 => open,
-  FF_RX_H_CLK_2 => open,
-  FF_TX_F_CLK_2 => open,
-  FF_TX_H_CLK_2 => open,
-  FFC_CK_CORE_RX_2 => fpsc_vlo,
-  FF_TX_D_2_0 => fpsc_vlo,
-  FF_TX_D_2_1 => fpsc_vlo,
-  FF_TX_D_2_2 => fpsc_vlo,
-  FF_TX_D_2_3 => fpsc_vlo,
-  FF_TX_D_2_4 => fpsc_vlo,
-  FF_TX_D_2_5 => fpsc_vlo,
-  FF_TX_D_2_6 => fpsc_vlo,
-  FF_TX_D_2_7 => fpsc_vlo,
-  FF_TX_D_2_8 => fpsc_vlo,
-  FF_TX_D_2_9 => fpsc_vlo,
-  FF_TX_D_2_10 => fpsc_vlo,
+  FF_RX_F_CLK_2 => rx_full_clk_ch2,
+  FF_RX_H_CLK_2 => rx_half_clk_ch2,
+  FF_TX_F_CLK_2 => tx_full_clk_ch2_sig,
+  FF_TX_H_CLK_2 => tx_half_clk_ch2,
+  FFC_CK_CORE_RX_2 => fpga_rxrefclk_ch2,
+  FF_TX_D_2_0 => txdata_ch2(0),
+  FF_TX_D_2_1 => txdata_ch2(1),
+  FF_TX_D_2_2 => txdata_ch2(2),
+  FF_TX_D_2_3 => txdata_ch2(3),
+  FF_TX_D_2_4 => txdata_ch2(4),
+  FF_TX_D_2_5 => txdata_ch2(5),
+  FF_TX_D_2_6 => txdata_ch2(6),
+  FF_TX_D_2_7 => txdata_ch2(7),
+  FF_TX_D_2_8 => tx_k_ch2,
+  FF_TX_D_2_9 => tx_force_disp_ch2,
+  FF_TX_D_2_10 => tx_disp_sel_ch2,
   FF_TX_D_2_11 => fpsc_vlo,
   FF_TX_D_2_12 => fpsc_vlo,
   FF_TX_D_2_13 => fpsc_vlo,
@@ -2445,17 +2442,17 @@ port map  (
   FF_TX_D_2_21 => fpsc_vlo,
   FF_TX_D_2_22 => fpsc_vlo,
   FF_TX_D_2_23 => fpsc_vlo,
-  FF_RX_D_2_0 => open,
-  FF_RX_D_2_1 => open,
-  FF_RX_D_2_2 => open,
-  FF_RX_D_2_3 => open,
-  FF_RX_D_2_4 => open,
-  FF_RX_D_2_5 => open,
-  FF_RX_D_2_6 => open,
-  FF_RX_D_2_7 => open,
-  FF_RX_D_2_8 => open,
-  FF_RX_D_2_9 => open,
-  FF_RX_D_2_10 => open,
+  FF_RX_D_2_0 => rxdata_ch2(0),
+  FF_RX_D_2_1 => rxdata_ch2(1),
+  FF_RX_D_2_2 => rxdata_ch2(2),
+  FF_RX_D_2_3 => rxdata_ch2(3),
+  FF_RX_D_2_4 => rxdata_ch2(4),
+  FF_RX_D_2_5 => rxdata_ch2(5),
+  FF_RX_D_2_6 => rxdata_ch2(6),
+  FF_RX_D_2_7 => rxdata_ch2(7),
+  FF_RX_D_2_8 => rx_k_ch2,
+  FF_RX_D_2_9 => rx_disp_err_ch2,
+  FF_RX_D_2_10 => rx_cv_err_ch2,
   FF_RX_D_2_11 => open,
   FF_RX_D_2_12 => open,
   FF_RX_D_2_13 => open,
@@ -2470,30 +2467,30 @@ port map  (
   FF_RX_D_2_22 => open,
   FF_RX_D_2_23 => open,
 
-  FFC_RRST_2 => fpsc_vlo,
+  FFC_RRST_2 => rx_serdes_rst_ch2_c,
   FFC_SIGNAL_DETECT_2 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_2 => fpsc_vlo,
-  FFC_PFIFO_CLR_2 => fpsc_vlo,
+  FFC_SB_PFIFO_LP_2 => sb_felb_ch2_c,
+  FFC_PFIFO_CLR_2 => sb_felb_rst_ch2_c,
   FFC_SB_INV_RX_2 => fpsc_vlo,
   FFC_PCIE_CT_2 => fpsc_vlo,
   FFC_PCI_DET_EN_2 => fpsc_vlo,
   FFC_FB_LOOPBACK_2 => fpsc_vlo,
   FFC_ENABLE_CGALIGN_2 => fpsc_vlo,
   FFC_EI_EN_2 => fpsc_vlo,
-  FFC_LANE_TX_RST_2 => fpsc_vlo,
-  FFC_TXPWDNB_2 => fpsc_vlo,
-  FFC_LANE_RX_RST_2 => fpsc_vlo,
-  FFC_RXPWDNB_2 => fpsc_vlo,
-  FFS_RLOS_LO_2 => open,
+  FFC_LANE_TX_RST_2 => tx_pcs_rst_ch2_c,
+  FFC_TXPWDNB_2 => tx_pwrup_ch2_c,
+  FFC_LANE_RX_RST_2 => rx_pcs_rst_ch2_c,
+  FFC_RXPWDNB_2 => rx_pwrup_ch2_c,
+  FFS_RLOS_LO_2 => rx_los_low_ch2_sig,
   FFS_RLOS_HI_2 => open,
   FFS_PCIE_CON_2 => open,
   FFS_PCIE_DONE_2 => open,
-  FFS_LS_SYNC_STATUS_2 => open,
+  FFS_LS_SYNC_STATUS_2 => lsm_status_ch2_s,
   FFS_CC_OVERRUN_2 => open,
   FFS_CC_UNDERRUN_2 => open,
   FFS_SKP_ADDED_2 => open,
   FFS_SKP_DELETED_2 => open,
-  FFS_RLOL_2 => open,
+  FFS_RLOL_2 => rx_cdr_lol_ch2_sig,
   FFS_RXFBFIFO_ERROR_2 => open,
   FFS_TXFBFIFO_ERROR_2 => open,
   LDR_CORE2TX_2 => fpsc_vlo,
@@ -2501,15 +2498,15 @@ port map  (
   LDR_RX2CORE_2 => open,
   FFS_CDR_TRAIN_DONE_2 => open,
   FFC_DIV11_MODE_TX_2 => fpsc_vlo,
-  FFC_RATE_MODE_TX_2 => fpsc_vlo,
+  FFC_RATE_MODE_TX_2 => tx_div2_mode_ch2_c,
   FFC_DIV11_MODE_RX_2 => fpsc_vlo,
-  FFC_RATE_MODE_RX_2 => fpsc_vlo,
+  FFC_RATE_MODE_RX_2 => rx_div2_mode_ch2_c,
 
 ----- CH3 -----
-  HDOUTP3 => hdoutp_ch3,
-  HDOUTN3 => hdoutn_ch3,
-  HDINP3 => hdinp_ch3,
-  HDINN3 => hdinn_ch3,
+  HDOUTP3 => open,
+  HDOUTN3 => open,
+  HDINP3 => fpsc_vlo,
+  HDINN3 => fpsc_vlo,
   PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo,
   PCIE_TXCOMPLIANCE_3 => fpsc_vlo,
   PCIE_RXPOLARITY_3 => fpsc_vlo,
@@ -2517,27 +2514,27 @@ port map  (
   PCIE_POWERDOWN_3_1 => fpsc_vlo,
   PCIE_RXVALID_3 => open,
   PCIE_PHYSTATUS_3 => open,
-  SCISELCH3 => sci_sel_ch3,
-  SCIENCH3 => fpsc_vhi,
+  SCISELCH3 => fpsc_vlo,
+  SCIENCH3 => fpsc_vlo,
   FF_RXI_CLK_3 => fpsc_vlo,
-  FF_TXI_CLK_3 => txiclk_ch3,
+  FF_TXI_CLK_3 => fpsc_vlo,
   FF_EBRD_CLK_3 => fpsc_vlo,
-  FF_RX_F_CLK_3 => rx_full_clk_ch3,
-  FF_RX_H_CLK_3 => rx_half_clk_ch3,
-  FF_TX_F_CLK_3 => tx_full_clk_ch3_sig,
-  FF_TX_H_CLK_3 => tx_half_clk_ch3,
-  FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3,
-  FF_TX_D_3_0 => txdata_ch3(0),
-  FF_TX_D_3_1 => txdata_ch3(1),
-  FF_TX_D_3_2 => txdata_ch3(2),
-  FF_TX_D_3_3 => txdata_ch3(3),
-  FF_TX_D_3_4 => txdata_ch3(4),
-  FF_TX_D_3_5 => txdata_ch3(5),
-  FF_TX_D_3_6 => txdata_ch3(6),
-  FF_TX_D_3_7 => txdata_ch3(7),
-  FF_TX_D_3_8 => tx_k_ch3,
-  FF_TX_D_3_9 => tx_force_disp_ch3,
-  FF_TX_D_3_10 => tx_disp_sel_ch3,
+  FF_RX_F_CLK_3 => open,
+  FF_RX_H_CLK_3 => open,
+  FF_TX_F_CLK_3 => open,
+  FF_TX_H_CLK_3 => open,
+  FFC_CK_CORE_RX_3 => fpsc_vlo,
+  FF_TX_D_3_0 => fpsc_vlo,
+  FF_TX_D_3_1 => fpsc_vlo,
+  FF_TX_D_3_2 => fpsc_vlo,
+  FF_TX_D_3_3 => fpsc_vlo,
+  FF_TX_D_3_4 => fpsc_vlo,
+  FF_TX_D_3_5 => fpsc_vlo,
+  FF_TX_D_3_6 => fpsc_vlo,
+  FF_TX_D_3_7 => fpsc_vlo,
+  FF_TX_D_3_8 => fpsc_vlo,
+  FF_TX_D_3_9 => fpsc_vlo,
+  FF_TX_D_3_10 => fpsc_vlo,
   FF_TX_D_3_11 => fpsc_vlo,
   FF_TX_D_3_12 => fpsc_vlo,
   FF_TX_D_3_13 => fpsc_vlo,
@@ -2551,17 +2548,17 @@ port map  (
   FF_TX_D_3_21 => fpsc_vlo,
   FF_TX_D_3_22 => fpsc_vlo,
   FF_TX_D_3_23 => fpsc_vlo,
-  FF_RX_D_3_0 => rxdata_ch3(0),
-  FF_RX_D_3_1 => rxdata_ch3(1),
-  FF_RX_D_3_2 => rxdata_ch3(2),
-  FF_RX_D_3_3 => rxdata_ch3(3),
-  FF_RX_D_3_4 => rxdata_ch3(4),
-  FF_RX_D_3_5 => rxdata_ch3(5),
-  FF_RX_D_3_6 => rxdata_ch3(6),
-  FF_RX_D_3_7 => rxdata_ch3(7),
-  FF_RX_D_3_8 => rx_k_ch3,
-  FF_RX_D_3_9 => rx_disp_err_ch3,
-  FF_RX_D_3_10 => rx_cv_err_ch3,
+  FF_RX_D_3_0 => open,
+  FF_RX_D_3_1 => open,
+  FF_RX_D_3_2 => open,
+  FF_RX_D_3_3 => open,
+  FF_RX_D_3_4 => open,
+  FF_RX_D_3_5 => open,
+  FF_RX_D_3_6 => open,
+  FF_RX_D_3_7 => open,
+  FF_RX_D_3_8 => open,
+  FF_RX_D_3_9 => open,
+  FF_RX_D_3_10 => open,
   FF_RX_D_3_11 => open,
   FF_RX_D_3_12 => open,
   FF_RX_D_3_13 => open,
@@ -2576,30 +2573,30 @@ port map  (
   FF_RX_D_3_22 => open,
   FF_RX_D_3_23 => open,
 
-  FFC_RRST_3 => rx_serdes_rst_ch3_c,
+  FFC_RRST_3 => fpsc_vlo,
   FFC_SIGNAL_DETECT_3 => fpsc_vlo,
-  FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c,
-  FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c,
+  FFC_SB_PFIFO_LP_3 => fpsc_vlo,
+  FFC_PFIFO_CLR_3 => fpsc_vlo,
   FFC_SB_INV_RX_3 => fpsc_vlo,
   FFC_PCIE_CT_3 => fpsc_vlo,
   FFC_PCI_DET_EN_3 => fpsc_vlo,
   FFC_FB_LOOPBACK_3 => fpsc_vlo,
   FFC_ENABLE_CGALIGN_3 => fpsc_vlo,
   FFC_EI_EN_3 => fpsc_vlo,
-  FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c,
-  FFC_TXPWDNB_3 => tx_pwrup_ch3_c,
-  FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c,
-  FFC_RXPWDNB_3 => rx_pwrup_ch3_c,
-  FFS_RLOS_LO_3 => rx_los_low_ch3_sig,
+  FFC_LANE_TX_RST_3 => fpsc_vlo,
+  FFC_TXPWDNB_3 => fpsc_vlo,
+  FFC_LANE_RX_RST_3 => fpsc_vlo,
+  FFC_RXPWDNB_3 => fpsc_vlo,
+  FFS_RLOS_LO_3 => open,
   FFS_RLOS_HI_3 => open,
   FFS_PCIE_CON_3 => open,
   FFS_PCIE_DONE_3 => open,
-  FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s,
+  FFS_LS_SYNC_STATUS_3 => open,
   FFS_CC_OVERRUN_3 => open,
   FFS_CC_UNDERRUN_3 => open,
   FFS_SKP_ADDED_3 => open,
   FFS_SKP_DELETED_3 => open,
-  FFS_RLOL_3 => rx_cdr_lol_ch3_sig,
+  FFS_RLOL_3 => open,
   FFS_RXFBFIFO_ERROR_3 => open,
   FFS_TXFBFIFO_ERROR_3 => open,
   LDR_CORE2TX_3 => fpsc_vlo,
@@ -2607,9 +2604,9 @@ port map  (
   LDR_RX2CORE_3 => open,
   FFS_CDR_TRAIN_DONE_3 => open,
   FFC_DIV11_MODE_TX_3 => fpsc_vlo,
-  FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c,
+  FFC_RATE_MODE_TX_3 => fpsc_vlo,
   FFC_DIV11_MODE_RX_3 => fpsc_vlo,
-  FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c,
+  FFC_RATE_MODE_RX_3 => fpsc_vlo,
 
 ----- Auxilliary ----
   SCIWDATA7 => sci_wrdata(7),
@@ -2698,4 +2695,4 @@ BEGIN
    wait;
 END PROCESS;
 --synopsys translate_on
-end serdes_sync_upstream_arch ;
+end sfp_3sync_200_int_arch ;
diff --git a/hub_SODA/sources/lattice/serdes_rx_reset_sm.vhd b/hub_SODA/sources/lattice/serdes_rx_reset_sm.vhd
new file mode 100644
index 0000000..73b9746
--- /dev/null
+++ b/hub_SODA/sources/lattice/serdes_rx_reset_sm.vhd
@@ -0,0 +1,196 @@
+--Reset Sequence Generator
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity serdes_rx_reset_sm is
+port (
+	rst_n			: in std_logic;
+	refclkdiv2        : in std_logic;
+	tx_pll_lol_qd_s	: in std_logic;
+	rx_serdes_rst_ch_c: out std_logic;
+	rx_cdr_lol_ch_s	: in std_logic;
+	rx_los_low_ch_s	: in std_logic;
+	rx_pcs_rst_ch_c	: out std_logic;
+    STATE_OUT         : out std_logic_vector(3 downto 0)
+);
+end serdes_rx_reset_sm ;
+
+architecture serdes_rx_reset_sm_arch of serdes_rx_reset_sm is
+
+type statetype is (WAIT_FOR_PLOL, RX_SERDES_RESET, WAIT_FOR_TIMER1, CHECK_LOL_LOS, WAIT_FOR_TIMER2, NORMAL);
+
+signal	cs:		statetype; 	-- current state of lsm
+signal	ns:		statetype;	-- next state of lsm
+
+signal	tx_pll_lol_qd_s_int:	std_logic;
+signal	rx_los_low_int:			std_logic;
+signal	plol_los_int:			std_logic;
+signal	rx_lol_los	:	std_logic;
+signal	rx_lol_los_int:		std_logic;
+signal	rx_lol_los_del:		std_logic;
+signal	rx_pcs_rst_ch_c_int:	std_logic;      
+signal	rx_serdes_rst_ch_c_int:	std_logic;
+
+signal	reset_timer1:	std_logic;
+signal	reset_timer2:	std_logic;
+
+signal	counter1:	std_logic_vector(1 downto 0);
+signal	TIMER1:	std_logic;
+
+signal	counter2: std_logic_vector(18 downto 0);
+signal	TIMER2	: std_logic;
+
+begin
+
+rx_lol_los <= rx_cdr_lol_ch_s or rx_los_low_ch_s ;
+
+process(refclkdiv2,rst_n) 
+begin
+	if rising_edge(refclkdiv2) then
+		if rst_n = '0' then 
+			cs <= WAIT_FOR_PLOL;
+			rx_lol_los_int <= '1';
+			rx_lol_los_del <= '1';
+			tx_pll_lol_qd_s_int <= '1';
+			rx_pcs_rst_ch_c <= '1';
+			rx_serdes_rst_ch_c <= '0';
+			rx_los_low_int <= '1';
+		else 
+			cs <= ns;
+			rx_lol_los_del <= rx_lol_los;
+			rx_lol_los_int <= rx_lol_los_del;
+			tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+			rx_pcs_rst_ch_c <= rx_pcs_rst_ch_c_int;
+			rx_serdes_rst_ch_c <= rx_serdes_rst_ch_c_int;
+			rx_los_low_int <= rx_los_low_ch_s;
+		end if;
+	end if;
+end process;
+
+--TIMER1 = 3NS;
+--Fastest REFCLK = 312 MHz, or 3ns. We need 1 REFCLK cycles or 2 REFCLKDIV2 cycles
+--A 1 bit counter  counts 2 cycles, so a 2 bit ([1:0]) counter will do if we set TIMER1 = bit[1]
+
+process(refclkdiv2, reset_timer1) 
+begin 
+	if rising_edge(refclkdiv2) then
+		if reset_timer1 = '1' then 
+			counter1 <= "00";
+			TIMER1 <= '0';
+		else 
+			if counter1(1) = '1' then
+				TIMER1 <='1';
+			else
+				TIMER1 <='0';
+				counter1 <= counter1 + 1 ;
+			end if;
+		end if;
+	end if;
+end process;
+
+--TIMER2 = 400,000 Refclk cycles or 200,000 REFCLKDIV2 cycles
+--An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+process(refclkdiv2, reset_timer2) 
+begin
+	if rising_edge(refclkdiv2) then
+		if reset_timer2 = '1' then 
+			counter2 <= "0000000000000000000";
+			TIMER2 <= '0';
+		else 
+			if counter2(18) = '1' then
+--			if counter2(4) = '1' then -- for simulation
+				TIMER2 <='1';
+			else
+				TIMER2 <='0';
+				counter2 <= counter2 + 1 ;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+process(cs, tx_pll_lol_qd_s_int, rx_los_low_int, TIMER1, rx_lol_los_int, TIMER2)
+begin
+		reset_timer1 <= '0';        
+		reset_timer2 <= '0';        
+
+	case cs is
+		when WAIT_FOR_PLOL => 
+			rx_pcs_rst_ch_c_int <= '1';        
+			rx_serdes_rst_ch_c_int <= '0';
+			if (tx_pll_lol_qd_s_int = '1' or rx_los_low_int = '1') then  --Also make sure A Signal       
+				ns <= WAIT_FOR_PLOL;    			--is Present prior to moving to the next 
+			else	
+				ns <= RX_SERDES_RESET;
+      		end if;
+          		
+	    when RX_SERDES_RESET => 
+			rx_pcs_rst_ch_c_int <= '1';        
+			rx_serdes_rst_ch_c_int <= '1';        
+			reset_timer1 <= '1';        
+      		ns <= WAIT_FOR_TIMER1;
+
+		when WAIT_FOR_TIMER1 => 
+			rx_pcs_rst_ch_c_int <= '1';        
+			rx_serdes_rst_ch_c_int <= '1';
+			if TIMER1 = '1' then 
+				ns <= CHECK_LOL_LOS;
+			else	
+				ns <= WAIT_FOR_TIMER1;
+      		end if;
+      
+		when CHECK_LOL_LOS =>
+			rx_pcs_rst_ch_c_int <= '1';        
+			rx_serdes_rst_ch_c_int <= '0';        
+			reset_timer2 <= '1';        
+      		ns <= WAIT_FOR_TIMER2;
+        		
+		when WAIT_FOR_TIMER2 =>
+			rx_pcs_rst_ch_c_int <= '1';        
+			rx_serdes_rst_ch_c_int <= '0';
+			if rx_lol_los_int = rx_lol_los_del then 	--NO RISING OR FALLING EDGES
+				if TIMER2 = '1' then
+					if rx_lol_los_int = '1' then 
+						ns <= WAIT_FOR_PLOL;
+					else
+						ns <= NORMAL;
+					end if;
+				else
+					ns <= WAIT_FOR_TIMER2;
+				end if;
+			else
+	   			ns <= CHECK_LOL_LOS; 	--RESET TIMER2					
+			end if;
+
+		when NORMAL =>  
+			rx_pcs_rst_ch_c_int <= '0';        
+			rx_serdes_rst_ch_c_int <= '0';
+			if rx_lol_los_int = '1' then
+				ns <= WAIT_FOR_PLOL;
+			else	
+				ns <= NORMAL;
+			end if;
+
+		when others =>
+			ns <= WAIT_FOR_PLOL;
+
+		end case;
+
+end process;
+
+
+
+STATE_OUT <= 
+	x"1" when cs=WAIT_FOR_PLOL else
+	x"2" when cs=RX_SERDES_RESET else
+	x"3" when cs=WAIT_FOR_timer1 else
+	x"4" when cs=CHECK_LOL_LOS else
+	x"5" when cs=WAIT_FOR_timer2 else
+	x"6" when cs=NORMAL else
+	x"f";
+			
+end serdes_rx_reset_sm_arch;
diff --git a/hub_SODA/sources/lattice/serdes_tx_reset_sm.vhd b/hub_SODA/sources/lattice/serdes_tx_reset_sm.vhd
new file mode 100644
index 0000000..5a71d15
--- /dev/null
+++ b/hub_SODA/sources/lattice/serdes_tx_reset_sm.vhd
@@ -0,0 +1,174 @@
+--TX Reset Sequence state machine--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity serdes_tx_reset_sm is
+port (
+	rst_n 			: in std_logic;
+	refclkdiv2      : in std_logic;
+	tx_pll_lol_qd_s : in std_logic;
+	rst_qd_c		: out std_logic;
+	tx_pcs_rst_ch_c : out std_logic_vector(3 downto 0);
+	STATE_OUT       : out std_logic_vector(3 downto 0)
+	);
+end serdes_tx_reset_sm;
+
+architecture serdes_tx_reset_sm_arch of serdes_tx_reset_sm is
+
+type statetype is (QUAD_RESET, WAIT_FOR_TIMER1, CHECK_PLOL, WAIT_FOR_TIMER2, NORMAL);
+
+signal	cs:		statetype;	-- current state of lsm
+signal	ns:		statetype;	-- next state of lsm
+
+signal 	tx_pll_lol_qd_s_int	: std_logic;
+signal 	tx_pcs_rst_ch_c_int	: std_logic_vector(3 downto 0);
+signal 	rst_qd_c_int		: std_logic;
+	
+signal 	reset_timer1:	std_logic;
+signal	reset_timer2:	std_logic;
+
+signal	counter1:		std_logic_vector(2 downto 0);
+signal	TIMER1:			std_logic;
+
+signal	counter2:		std_logic_vector(18 downto 0);
+signal	TIMER2:			std_logic;
+
+begin
+
+process (refclkdiv2, rst_n) 
+begin
+	if rst_n = '0' then 
+		cs <= QUAD_RESET;
+		tx_pll_lol_qd_s_int <= '1';
+		tx_pcs_rst_ch_c <= "1111";
+		rst_qd_c <= '1';
+	else if rising_edge(refclkdiv2) then
+		cs <= ns;
+		tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s;
+		tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int;
+		rst_qd_c <= rst_qd_c_int;
+	end if;
+	end if;
+end process;
+
+
+--TIMER1 = 20ns;
+--Fastest REFLCK =312 MHZ, or 3 ns. We need 8 REFCLK cycles or 4 REFCLKDIV2 cycles
+-- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2]
+
+
+process (refclkdiv2, reset_timer1) 
+begin
+	if rising_edge(refclkdiv2) then
+		if reset_timer1 = '1' then
+			counter1 <= "000";
+			TIMER1 <= '0';
+		else 				
+			if counter1(2) = '1' then
+				TIMER1 <= '1';
+			else
+				TIMER1 <='0';
+				counter1 <= counter1 + 1 ;
+			end if;
+		end if;
+	end if;
+end process;
+
+
+--TIMER2 = 1,400,000 UI;
+--WORST CASE CYCLES is with smallest multipier factor.
+-- This would be with X8 clock multiplier in DIV2 mode
+-- IN this casse, 1 UI = 2/8 REFCLK  CYCLES = 1/8 REFCLKDIV2 CYCLES
+-- SO 1,400,000 UI =1,400,000/8 = 175,000 REFCLKDIV2 CYCLES
+-- An 18 bit counter ([17:0]) counts 262144 cycles, so a 19 bit ([18:0]) counter will do if we set TIMER2 = bit[18]
+
+
+process(refclkdiv2, reset_timer2) 
+begin
+	if rising_edge(refclkdiv2) then
+		if reset_timer2 = '1' then 
+			counter2 <= "0000000000000000000";
+			TIMER2 <= '0';
+		else 
+			if counter2(18) = '1' then
+--			if counter2(4) = '1' then		-- for simulation
+				TIMER2 <='1';
+			else
+				TIMER2 <='0';
+				counter2 <= counter2 + 1 ;
+			end if;
+		end if;
+	end if;
+end process;
+
+process(cs, TIMER1, TIMER2, tx_pll_lol_qd_s_int)
+begin
+
+		reset_timer1 <= '0';        
+		reset_timer2 <= '0';        
+
+	case cs is     
+  	
+      when QUAD_RESET	=> 
+		tx_pcs_rst_ch_c_int <= "1111";        
+		rst_qd_c_int <= '1';        
+		reset_timer1 <= '1';        
+      	ns <= WAIT_FOR_TIMER1;
+                		
+      when WAIT_FOR_TIMER1	=> 
+		tx_pcs_rst_ch_c_int <= "1111";        
+		rst_qd_c_int <= '1';
+		if TIMER1 = '1' then 
+			ns <= CHECK_PLOL;
+		else	
+			ns <= WAIT_FOR_TIMER1;
+      	end if;
+
+      when CHECK_PLOL	=> 
+		tx_pcs_rst_ch_c_int <= "1111";        
+		rst_qd_c_int <= '0';        
+		reset_timer2 <= '1';        
+      	ns <= WAIT_FOR_TIMER2;
+      	    		
+      when WAIT_FOR_TIMER2	=> 
+		tx_pcs_rst_ch_c_int <= "1111";        
+		rst_qd_c_int <= '0';
+		if TIMER2 = '1' then 
+			if tx_pll_lol_qd_s_int = '1' then
+				ns <= QUAD_RESET;
+			else
+				ns <= NORMAL;
+			end if;
+		else
+	   		ns <= WAIT_FOR_TIMER2;					
+     	    	end if;
+     	
+	when NORMAL	=> 
+		tx_pcs_rst_ch_c_int <= "0000";        
+		rst_qd_c_int <= '0';
+		if tx_pll_lol_qd_s_int = '1' then 
+			ns <= QUAD_RESET;
+		else	
+			ns <= NORMAL;
+      	end if;
+
+	when others =>
+		ns <= 	QUAD_RESET;
+	
+	end case;
+
+end process;
+
+STATE_OUT <= 
+	x"1" when cs=QUAD_RESET else
+	x"2" when cs=WAIT_FOR_TIMER1 else
+	x"3" when cs=CHECK_PLOL else
+	x"4" when cs=WAIT_FOR_TIMER2 else
+	x"5" when cs=NORMAL else
+	x"f";
+
+	
+end serdes_tx_reset_sm_arch;	
diff --git a/hub_SODA/sources/lattice/trb_net16_med_sync3_ecp3_sfp.vhd b/hub_SODA/sources/lattice/trb_net16_med_sync3_ecp3_sfp.vhd
new file mode 100644
index 0000000..e2e378f
--- /dev/null
+++ b/hub_SODA/sources/lattice/trb_net16_med_sync3_ecp3_sfp.vhd
@@ -0,0 +1,851 @@
+--Media interface for Lattice ECP3 using PCS at 2GHz
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+--USE IEEE.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.med_sync_define.all;
+
+
+entity trb_net16_med_sync3_ecp3_sfp is
+  port(
+    CLK                : in  std_logic; -- SerDes clock
+    SYSCLK             : in  std_logic; -- fabric clock
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    CLK_EN             : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic;
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic;
+    MED_READ_IN        : in  std_logic;
+    REFCLK2CORE_OUT    : out std_logic;
+    CLK_RX_HALF_OUT    : out std_logic;
+    CLK_RX_FULL_OUT    : out std_logic;
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic;
+    SD_RXD_N_IN        : in  std_logic;
+    SD_TXD_P_OUT       : out std_logic;
+    SD_TXD_N_OUT       : out std_logic;
+	SD_DLM_IN          : in  std_logic;
+	SD_DLM_WORD_IN     : in  std_logic_vector(7 downto 0);
+	SD_DLM_OUT         : out std_logic;
+	SD_DLM_WORD_OUT    : out  std_logic_vector(7 downto 0);
+    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out  std_logic; -- SFP disable
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    SCI_NACK           : out std_logic := '0';
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0);
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end entity;
+
+architecture trb_net16_med_sync3_ecp3_sfp_arch of trb_net16_med_sync3_ecp3_sfp is
+
+
+component sfp_3sync_200_int is
+ port (
+------------------
+-- CH0 --
+-- CH1 --
+-- CH2 --
+    hdinp_ch2, hdinn_ch2    :   in std_logic;
+    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
+    sci_sel_ch2    :   in std_logic;
+    rxiclk_ch2    :   in std_logic;
+    txiclk_ch2    :   in std_logic;
+    rx_full_clk_ch2   :   out std_logic;
+    rx_half_clk_ch2   :   out std_logic;
+    tx_full_clk_ch2   :   out std_logic;
+    tx_half_clk_ch2   :   out std_logic;
+    fpga_rxrefclk_ch2    :   in std_logic;
+    txdata_ch2    :   in std_logic_vector (7 downto 0);
+    tx_k_ch2    :   in std_logic;
+    tx_force_disp_ch2    :   in std_logic;
+    tx_disp_sel_ch2    :   in std_logic;
+    rxdata_ch2   :   out std_logic_vector (7 downto 0);
+    rx_k_ch2   :   out std_logic;
+    rx_disp_err_ch2   :   out std_logic;
+    rx_cv_err_ch2   :   out std_logic;
+    rx_serdes_rst_ch2_c    :   in std_logic;
+    sb_felb_ch2_c    :   in std_logic;
+    sb_felb_rst_ch2_c    :   in std_logic;
+    tx_pcs_rst_ch2_c    :   in std_logic;
+    tx_pwrup_ch2_c    :   in std_logic;
+    rx_pcs_rst_ch2_c    :   in std_logic;
+    rx_pwrup_ch2_c    :   in std_logic;
+    rx_los_low_ch2_s   :   out std_logic;
+    lsm_status_ch2_s   :   out std_logic;
+    rx_cdr_lol_ch2_s   :   out std_logic;
+    tx_div2_mode_ch2_c   : in std_logic;
+    rx_div2_mode_ch2_c   : in std_logic;
+-- CH3 --
+---- Miscillaneous ports
+    sci_wrdata    :   in std_logic_vector (7 downto 0);
+    sci_addr    :   in std_logic_vector (5 downto 0);
+    sci_rddata   :   out std_logic_vector (7 downto 0);
+    sci_sel_quad    :   in std_logic;
+    sci_rd    :   in std_logic;
+    sci_wrn    :   in std_logic;
+    fpga_txrefclk  :   in std_logic;
+    tx_serdes_rst_c    :   in std_logic;
+    tx_pll_lol_qd_s   :   out std_logic;
+    rst_qd_c    :   in std_logic;
+    serdes_rst_qd_c    :   in std_logic);
+
+end component;
+
+
+component serdes_rx_reset_sm is
+port (
+	rst_n			: in std_logic;
+	refclkdiv2        : in std_logic;
+	tx_pll_lol_qd_s	: in std_logic;
+	rx_serdes_rst_ch_c: out std_logic;
+	rx_cdr_lol_ch_s	: in std_logic;
+	rx_los_low_ch_s	: in std_logic;
+	rx_pcs_rst_ch_c	: out std_logic;
+    STATE_OUT         : out std_logic_vector(3 downto 0));
+end component ;
+component serdes_tx_reset_sm is
+port (
+	rst_n 			: in std_logic;
+	refclkdiv2      : in std_logic;
+	tx_pll_lol_qd_s : in std_logic;
+	rst_qd_c		: out std_logic;
+	tx_pcs_rst_ch_c : out std_logic_vector(3 downto 0);
+	STATE_OUT       : out std_logic_vector(3 downto 0)
+	);
+end component;
+
+component HUB_8to16_SODA is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		char_is_k               : in std_logic;
+		fifo_data               : out std_logic_vector(17 downto 0);
+		fifo_full               : in std_logic;
+		fifo_write              : out std_logic;
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		error                   : out std_logic
+	);
+end component;
+
+component HUB_16to8_SODA is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		fifo_data               : in std_logic_vector(15 downto 0);
+		fifo_empty              : in std_logic;
+		fifo_read               : out std_logic;
+		TX_DLM                  : in std_logic;
+		TX_DLM_WORD             : in std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(7 downto 0);
+		char_is_k               : out std_logic;
+		error                   : out std_logic
+	);
+end component;
+
+component HUB_SODA_clockcrossing is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		DLM_in                  : in std_logic;
+		DLM_WORD_in             : in std_logic_vector(7 downto 0);
+		DLM_out                 : out std_logic;
+		DLM_WORD_out            : out std_logic_vector(7 downto 0);
+		error                   : out std_logic
+	);
+end component;
+
+component HUB_posedge_to_pulse is
+	port (
+		clock_in        : in  std_logic;
+		clock_out       : in  std_logic;
+		en_clk          : in  std_logic;
+		signal_in       : in  std_logic;
+		pulse           : out std_logic
+	);
+end component;
+
+  -- Placer Directives
+  attribute HGROUP : string;
+  -- for whole architecture
+  attribute HGROUP of trb_net16_med_sync3_ecp3_sfp_arch : architecture  is "media_interface_group";
+  attribute syn_sharing : string;
+  attribute syn_sharing of trb_net16_med_sync3_ecp3_sfp_arch : architecture is "off";
+
+  signal ffc_quad_rst           : std_logic;
+  --serdes connections
+  signal tx_data                : std_logic_vector(7 downto 0);
+  signal tx_k                   : std_logic;
+  signal rx_data                : std_logic_vector(7 downto 0);
+  signal rx_k                   : std_logic; 
+  signal link_ok                : std_logic;  
+  signal ff_txhalfclk           : std_logic;
+  signal ff_txfullclk           : std_logic;
+  signal ff_rxhalfclk		    : std_logic;
+  signal ff_rxfullclk           : std_logic;
+  --rx fifo signals
+  signal fifo_rx_rd_en          : std_logic;
+  signal fifo_rx_wr_en          : std_logic;
+  signal fifo_rx_reset          : std_logic;
+  signal fifo_rx_din            : std_logic_vector(17 downto 0);
+  signal fifo_rx_dout           : std_logic_vector(17 downto 0);
+  signal fifo_rx_full           : std_logic;
+  signal fifo_rx_empty          : std_logic;
+  --tx fifo signals
+  signal fifo_tx_rd_en          : std_logic;
+  signal fifo_tx_wr_en          : std_logic;
+  signal fifo_tx_reset          : std_logic;
+  signal fifo_tx_din            : std_logic_vector(17 downto 0);
+  signal fifo_tx_dout           : std_logic_vector(17 downto 0);
+  signal fifo_tx_empty          : std_logic;
+  signal fifo_tx_almost_full    : std_logic;
+  --rx path
+  signal rx_counter             : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal buf_med_dataready_out  : std_logic;
+  signal buf_med_data_out       : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+  signal buf_med_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+  signal last_rx                : std_logic_vector(8 downto 0);
+  signal last_fifo_rx_empty     : std_logic;
+  --link status
+
+  signal quad_rst               : std_logic;
+  signal lane_rst               : std_logic;
+  signal tx_allow               : std_logic;
+  signal rx_allow               : std_logic;
+
+  signal rx_allow_q             : std_logic; -- clock domain changed signal
+  signal tx_allow_q             : std_logic;
+  signal buf_stat_debug         : std_logic_vector(31 downto 0);
+
+  -- status inputs from SFP
+  signal sfp_prsnt_n            : std_logic; -- synchronized input signals
+  signal sfp_los                : std_logic; -- synchronized input signals
+
+  signal buf_STAT_OP            : std_logic_vector(15 downto 0);
+
+  signal led_counter            : unsigned(16 downto 0);
+  signal rx_led                 : std_logic;
+  signal tx_led                 : std_logic;
+
+  signal reset_word_cnt         : unsigned(4 downto 0);
+  signal make_trbnet_reset      : std_logic;
+  signal make_trbnet_reset_q    : std_logic;
+  signal send_reset_words       : std_logic;
+  signal send_reset_words_q     : std_logic;
+  signal send_reset_in          : std_logic;
+  signal send_reset_in_qtx      : std_logic;
+  signal reset_i                : std_logic;
+--  signal reset_i_rx             : std_logic;
+  signal pwr_up                 : std_logic;
+  signal clear_n                : std_logic;
+  signal trb_tx_pll_lol_qd_i    : std_logic;
+ 
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+signal sci_state                : sci_ctrl;
+  signal sci_ch_i               : std_logic_vector(3 downto 0);
+  signal sci_qd_i               : std_logic;
+  signal sci_reg_i              : std_logic;
+  signal sci_addr_i             : std_logic_vector(8 downto 0);
+  signal sci_data_in_i          : std_logic_vector(7 downto 0);
+  signal sci_data_out_i         : std_logic_vector(7 downto 0);
+  signal sci_read_i             : std_logic;
+  signal sci_write_i            : std_logic;
+  signal sci_timer              : unsigned(12 downto 0) := (others => '0');
+  signal trb_reset_n            : std_logic;
+  signal trb_rx_serdes_rst      : std_logic;
+  signal trb_rx_cdr_lol         : std_logic;
+  signal trb_rx_los_low         : std_logic;
+  signal trb_rx_pcs_rst         : std_logic;
+  signal trb_tx_pcs_rst         : std_logic;
+  signal trb_tx_pcs_rst_all     : std_logic_vector(3 downto 0);
+  signal rst_qd                 : std_logic;
+  signal trb_rx_fsm_state       : std_logic_vector(3 downto 0);
+  signal trb_tx_fsm_state       : std_logic_vector(3 downto 0);
+  
+  signal trb_rx_los_low_q       : std_logic;
+  signal trb_rx_cdr_lol_q       : std_logic;
+  signal trb_tx_pll_lol_qd_q    : std_logic;
+  signal trb_rx_cv_err_ch2      : std_logic;
+  signal trb_rx_cv_err_ch2_q    : std_logic;
+
+  signal link_tx_ok             : std_logic;
+  signal link_rx_ok             : std_logic;
+  signal link_tx_ok_q           : std_logic;
+  signal link_rx_ok_q           : std_logic;
+    
+  signal wa_position_sync1      : std_logic_vector(3 downto 0);
+  signal wa_position            : std_logic_vector(15 downto 0) := x"FFFF";
+
+  signal SD_DLM_IN_S            : std_logic;
+  signal SD_DLM_WORD_IN_S       : std_logic_vector(7 downto 0);
+  
+  attribute syn_keep : boolean;
+  attribute syn_preserve : boolean;
+  attribute syn_keep of led_counter : signal is true;
+  attribute syn_keep of send_reset_in : signal is true;
+  attribute syn_keep of reset_i : signal is true;
+  attribute syn_preserve of reset_i : signal is true;
+
+begin
+
+--------------------------------------------------------------------------
+-- Internal Lane Resets
+--------------------------------------------------------------------------
+  clear_n <= not clear;
+
+
+PROC_RESET : process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+		reset_i <= RESET;
+		send_reset_in <= ctrl_op(15);
+		pwr_up  <= '1'; --not CTRL_OP(i*16+14);
+	end if;
+end process;
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFP_STATUS_SYNC: signal_sync
+	generic map(
+		DEPTH => 3,
+		WIDTH => 2
+	)
+	port map(
+		RESET    => '0',
+		D_IN(0)  => sd_prsnt_n_in,
+		D_IN(1)  => sd_los_in,
+		CLK0     => SYSCLK,
+		CLK1     => SYSCLK,
+		D_OUT(0) => sfp_prsnt_n,
+		D_OUT(1) => sfp_los
+	);
+
+
+THE_RX_K_SYNC: signal_sync
+	generic map(
+		DEPTH => 1,
+		WIDTH => 1
+	)
+	port map(
+		RESET             => '0',
+		D_IN(0)           => send_reset_words,
+		CLK0              => ff_rxfullclk,
+		CLK1              => SYSCLK,
+		D_OUT(0)          => send_reset_words_q
+	);
+
+THE_RESET_SYNC: HUB_posedge_to_pulse 
+	port map(
+		clock_in => ff_rxfullclk,
+		clock_out => SYSCLK,
+		en_clk => '1',
+		signal_in => make_trbnet_reset,
+		pulse  => make_trbnet_reset_q
+	);
+
+process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+		if (tx_allow='1') and (link_tx_ok_q='1') then
+			tx_allow_q <= '1';
+		else
+			tx_allow_q <= '0';
+		end if;
+		if (rx_allow='1') and (link_rx_ok_q='1') then
+			rx_allow_q <= '1';
+		else
+			rx_allow_q <= '0';
+		end if;
+		link_tx_ok_q <= link_tx_ok;
+		link_rx_ok_q <= link_rx_ok;
+	end if;
+end process;
+-- synchronize link_OK 
+process(CLK)
+begin
+	if rising_edge(CLK) then
+		if trb_tx_fsm_state=x"5" then
+			link_tx_ok <= '1';
+		else
+			link_tx_ok <= '0';
+		end if;
+		if (trb_rx_fsm_state=x"6") then
+			link_rx_ok <= '1'; 
+		else
+			link_rx_ok <= '0';
+		end if;
+	end if;
+end process;
+	
+THE_TX_SYNC: signal_sync
+	generic map(
+		DEPTH => 1,
+		WIDTH => 1
+	)
+	port map(
+		RESET    => '0',
+		D_IN(0)  => send_reset_in,
+		CLK0     => ff_txfullclk,
+		CLK1     => ff_txfullclk,
+		D_OUT(0) => send_reset_in_qtx
+	);
+	
+THE_ERROR_SYNC: signal_sync
+	generic map(
+		DEPTH => 1,
+		WIDTH => 4
+	)
+	port map(
+		RESET    => '0',
+		D_IN(0)  => trb_rx_los_low,
+		D_IN(1)  => trb_rx_cdr_lol,
+		D_IN(2)  => trb_tx_pll_lol_qd_i,
+		D_IN(3)  => trb_rx_cv_err_ch2,
+		CLK0     => SYSCLK,
+		CLK1     => SYSCLK,
+		D_OUT(0) => trb_rx_los_low_q,
+		D_OUT(1) => trb_rx_cdr_lol_q,
+		D_OUT(2) => trb_tx_pll_lol_qd_q,
+		D_OUT(3) => trb_rx_cv_err_ch2_q
+	);
+	
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+
+THE_SFP_LSM: trb_net16_lsm_sfp
+	generic map (
+		CHECK_FOR_CV => c_YES,
+		HIGHSPEED_STARTUP => c_YES
+	)
+	port map(
+		SYSCLK            => SYSCLK,
+		RESET             => reset_i,
+		CLEAR             => clear,
+		SFP_MISSING_IN    => sfp_prsnt_n,
+		SFP_LOS_IN        => sfp_los,
+		SD_LINK_OK_IN     => link_ok, -- apparently not used
+		SD_LOS_IN         => trb_rx_los_low_q, -- apparently not used
+		SD_TXCLK_BAD_IN   => trb_tx_pll_lol_qd_q,
+		SD_RXCLK_BAD_IN   => trb_rx_cdr_lol_q,
+		SD_RETRY_IN       => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+		SD_ALIGNMENT_IN	=> "01", -- should always be correct
+		SD_CV_IN(0)       => trb_rx_cv_err_ch2_q,
+		SD_CV_IN(1)       => trb_rx_cv_err_ch2_q,
+		FULL_RESET_OUT    => quad_rst,
+		LANE_RESET_OUT    => lane_rst, -- apparently not used
+		TX_ALLOW_OUT      => tx_allow,
+		RX_ALLOW_OUT      => rx_allow,
+		SWAP_BYTES_OUT    => open,
+		STAT_OP           => buf_stat_op,
+		CTRL_OP           => ctrl_op,
+		STAT_DEBUG        => buf_stat_debug
+	);
+sd_txdis_out <= quad_rst or reset_i;
+
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+-- SerDes clock output to FPGA fabric
+REFCLK2CORE_OUT <= ff_rxhalfclk;
+CLK_RX_HALF_OUT <= ff_rxhalfclk;
+CLK_RX_FULL_OUT <= ff_rxfullclk;
+
+
+THE_SERDES: sfp_3sync_200_int 
+	port map(
+		hdinp_ch2 => sd_rxd_p_in,                
+		hdinn_ch2 => sd_rxd_n_in,                
+		hdoutp_ch2 => sd_txd_p_out,              
+		hdoutn_ch2 => sd_txd_n_out,              
+		sci_sel_ch2 => sci_ch_i(2),
+		rxiclk_ch2 => ff_rxfullclk,
+		txiclk_ch2 => ff_txfullclk,
+		rx_full_clk_ch2 => ff_rxfullclk,
+		rx_half_clk_ch2 => ff_rxhalfclk,
+		tx_full_clk_ch2 => ff_txfullclk,
+		tx_half_clk_ch2 => ff_txhalfclk,
+		fpga_rxrefclk_ch2 => CLK,
+		txdata_ch2 => tx_data,
+		tx_k_ch2 => tx_k,
+		tx_force_disp_ch2 => '0',
+		tx_disp_sel_ch2 => '0',
+		rxdata_ch2 => rx_data,
+		rx_k_ch2 => rx_k,
+		rx_disp_err_ch2 => open,
+		rx_cv_err_ch2 => trb_rx_cv_err_ch2,
+		rx_serdes_rst_ch2_c => trb_rx_serdes_rst,
+		sb_felb_ch2_c => '0',
+		sb_felb_rst_ch2_c => '0',
+		tx_pcs_rst_ch2_c => trb_tx_pcs_rst,
+		tx_pwrup_ch2_c => '1',
+		rx_pcs_rst_ch2_c => trb_rx_pcs_rst,
+		rx_pwrup_ch2_c => '1',
+		rx_los_low_ch2_s => trb_rx_los_low,
+		lsm_status_ch2_s => link_ok,
+		rx_cdr_lol_ch2_s => trb_rx_cdr_lol,
+		tx_div2_mode_ch2_c => '0',   
+		rx_div2_mode_ch2_c => '0',   
+	---- Miscillaneous ports
+		sci_wrdata => sci_data_in_i,
+		sci_addr => sci_addr_i(5 downto 0),
+		sci_rddata => sci_data_out_i,
+		sci_sel_quad => sci_qd_i,
+		sci_rd => sci_read_i,
+		sci_wrn => sci_write_i,
+		fpga_txrefclk => CLK,
+		tx_serdes_rst_c => CLEAR,
+		tx_pll_lol_qd_s => trb_tx_pll_lol_qd_i,  
+		rst_qd_c => '0',
+		serdes_rst_qd_c => ffc_quad_rst
+	);
+
+-------------------------------------------------------------------------
+-- RX Fifo & Data output
+-------------------------------------------------------------------------
+THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+	generic map(
+		USE_STATUS_FLAGS => c_NO)
+	port map( 
+		read_clock_in => SYSCLK,
+		write_clock_in => ff_rxfullclk,
+		read_enable_in => fifo_rx_rd_en,
+		write_enable_in => fifo_rx_wr_en,
+		fifo_gsr_in => fifo_rx_reset,
+		write_data_in => fifo_rx_din,
+		read_data_out => fifo_rx_dout,
+		full_out => fifo_rx_full,
+		empty_out => fifo_rx_empty
+	);
+fifo_rx_reset <= '1' when (reset_i='1') or (rx_allow_q='0') else '0';
+fifo_rx_rd_en <= not fifo_rx_empty;
+HUB_8to16_SODA1: HUB_8to16_SODA
+	port map(
+		clock => ff_rxfullclk,
+		reset => fifo_rx_reset,
+		data_in => rx_data,
+		char_is_k => rx_k,
+		fifo_data => fifo_rx_din,
+		fifo_full  => fifo_rx_full,
+		fifo_write => fifo_rx_wr_en,
+		RX_DLM => SD_DLM_OUT,
+		RX_DLM_WORD => SD_DLM_WORD_OUT,
+		error => open
+	);
+		
+buf_med_data_out          <= fifo_rx_dout(15 downto 0);
+buf_med_dataready_out     <= not fifo_rx_dout(17) and not fifo_rx_dout(16) and not last_fifo_rx_empty and rx_allow_q;
+buf_med_packet_num_out    <= rx_counter;
+med_read_out              <= tx_allow_q and not fifo_tx_almost_full;
+
+THE_SYNC_PROC: process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+		med_dataready_out     <= buf_med_dataready_out;
+		med_data_out          <= buf_med_data_out;
+		med_packet_num_out    <= buf_med_packet_num_out;
+		if reset_i = '1' then
+			med_dataready_out <= '0';
+		end if;
+	end if;
+end process;
+
+THE_CNT_RESET_PROC : process(ff_rxfullclk,reset_i)
+	begin
+		if reset_i='1' then
+			send_reset_words  <= '0';
+			make_trbnet_reset <= '0';
+			reset_word_cnt    <= (others => '0');
+		elsif rising_edge(ff_rxfullclk) then
+			send_reset_words   <= '0';
+			make_trbnet_reset  <= '0';
+			if (rx_k='1') and (rx_data=x"FE") then
+				if reset_word_cnt(4) = '0' then
+					reset_word_cnt <= reset_word_cnt + 1;
+				else
+					send_reset_words <= '1';
+				end if;
+			else
+				reset_word_cnt    <= (others => '0');
+				make_trbnet_reset <= reset_word_cnt(4);
+			end if;
+		end if;
+	end process;
+  
+--rx packet counter
+---------------------
+THE_RX_PACKETS_PROC: process(SYSCLK)
+begin
+	if( rising_edge(SYSCLK) ) then
+		last_fifo_rx_empty <= fifo_rx_empty;
+		if reset_i = '1' or rx_allow_q = '0' then
+			rx_counter <= c_H0;
+		else
+			if( buf_med_dataready_out = '1' ) then
+				if( rx_counter = c_max_word_number ) then
+					rx_counter <= (others => '0');
+				else
+					rx_counter <= rx_counter + 1;
+				end if;
+			end if;
+		end if;
+	end if;
+end process;
+  
+  
+  
+--TX Fifo & Data output to Serdes
+---------------------
+THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+	generic map(
+		USE_STATUS_FLAGS => c_NO
+	)
+	port map( 
+		read_clock_in => ff_txfullclk,
+		write_clock_in => SYSCLK,
+		read_enable_in => fifo_tx_rd_en,
+		write_enable_in => fifo_tx_wr_en,
+		fifo_gsr_in => fifo_tx_reset,
+		write_data_in => fifo_tx_din,
+		read_data_out => fifo_tx_dout,
+		full_out => open,
+		empty_out => fifo_tx_empty,
+		almost_full_out   => fifo_tx_almost_full
+	);
+
+fifo_tx_reset <= reset_i or not tx_allow_q;
+fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
+fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
+ 
+HUB_16to8_SODA1: HUB_16to8_SODA
+	port map(
+		clock => ff_txfullclk,
+		reset => send_reset_in_qtx,
+		fifo_data => fifo_tx_dout(15 downto 0),
+		fifo_empty => fifo_tx_empty,
+		fifo_read => fifo_tx_rd_en,
+		TX_DLM => SD_DLM_IN_S,
+		TX_DLM_WORD => SD_DLM_WORD_IN_S,
+		data_out => tx_data,
+		char_is_k => tx_k,
+		error => open
+	);
+
+HUB_SODA_clockcrossing1: HUB_SODA_clockcrossing
+	port map(
+		write_clock => ff_rxfullclk,
+		read_clock => ff_txfullclk,
+		DLM_in => SD_DLM_IN,
+		DLM_WORD_in => SD_DLM_WORD_IN,
+		DLM_out => SD_DLM_IN_S,
+		DLM_WORD_out => SD_DLM_WORD_IN_S,
+		error => open
+	);
+
+
+
+trb_reset_n <= '0' when (RESET='1') or (CLEAR='1') else '1';
+ffc_quad_rst <= quad_rst;
+
+-------------------------------------------------      
+-- Reset FSM & Link states
+------------------------------------------------- 
+THE_RX_FSM1: rx_reset_fsm -- reset FSM for receiver channel 2 (SODA), synchronize to fiber bit with wa_position
+	port map(
+		RST_N               => trb_reset_n,
+		RX_REFCLK           => CLK, --//ff_rxfullclk, --??CLK,
+		TX_PLL_LOL_QD_S     => trb_tx_pll_lol_qd_i,
+		RX_SERDES_RST_CH_C  => trb_rx_serdes_rst,
+		RX_CDR_LOL_CH_S     => trb_rx_cdr_lol,
+		RX_LOS_LOW_CH_S     => trb_rx_los_low,
+		RX_PCS_RST_CH_C     => trb_rx_pcs_rst,
+		WA_POSITION         => wa_position_sync1,
+		STATE_OUT           => trb_rx_fsm_state
+	);
+SYNC_WA_POSITION: signal_sync
+	generic map(
+		DEPTH => 1,
+		WIDTH => 4)
+	port map(
+		RESET => '0',
+		D_IN(3 downto 0) => wa_position(11 downto 8),
+		CLK0 => CLK, --// SYSCLK,
+		CLK1 => CLK, --//ff_rxfullclk,
+		D_OUT(3 downto 0) => wa_position_sync1
+	);
+
+
+THE_TX_FSM1: serdes_tx_reset_sm   -- original from Lattice
+	port map(
+		RST_N           => trb_reset_n,
+		refclkdiv2      => CLK, --//??SYSCLK,
+		TX_PLL_LOL_QD_S => trb_tx_pll_lol_qd_i,
+		RST_QD_C        => rst_qd,
+		TX_PCS_RST_CH_C => trb_tx_pcs_rst_all,
+		STATE_OUT       => trb_tx_fsm_state
+	);
+trb_tx_pcs_rst <= trb_tx_pcs_rst_all(1);
+
+
+-------------------------------------------------      
+-- SCI
+-------------------------------------------------      
+--gives access to serdes config port from slow control and reads word alignment every ~ 40 us
+PROC_SCI_CTRL: process(SYSCLK)
+variable cnt : integer range 0 to 4 := 0;
+begin
+	if( rising_edge(SYSCLK) ) then
+		SCI_ACK <= '0';
+		case sci_state is
+			when IDLE =>
+				sci_ch_i        <= x"0";
+				sci_qd_i        <= '0';
+				sci_reg_i       <= '0';
+				sci_read_i      <= '0';
+				sci_write_i     <= '0';
+				sci_timer       <= sci_timer + 1;
+				if SCI_READ = '1' or SCI_WRITE = '1' then
+					sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+					sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+					sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+					sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+					sci_qd_i      <= not SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
+					sci_reg_i     <=     SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8);
+					sci_addr_i    <= SCI_ADDR;
+					sci_data_in_i <= SCI_DATA_IN;
+					sci_read_i    <= SCI_READ  and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
+					sci_write_i   <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and     SCI_ADDR(8));
+					sci_state     <= SCTRL;
+				elsif sci_timer(sci_timer'left) = '1' then
+					sci_timer     <= (others => '0');
+					sci_state     <= GET_WA;
+				end if;      
+			when SCTRL =>
+				if sci_reg_i = '1' then
+					--//			SCI_DATA_OUT  <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
+					SCI_DATA_OUT  <= (others => '0');
+					SCI_ACK       <= '1';
+					sci_write_i   <= '0';
+					sci_read_i    <= '0';
+					sci_state     <= IDLE;
+				else
+					sci_state     <= SCTRL_WAIT;
+				end if;
+			when SCTRL_WAIT   =>
+				sci_state       <= SCTRL_WAIT2;
+			when SCTRL_WAIT2  =>
+				sci_state       <= SCTRL_FINISH;
+			when SCTRL_FINISH =>
+				SCI_DATA_OUT    <= sci_data_out_i;
+				SCI_ACK         <= '1';
+				sci_write_i     <= '0';
+				sci_read_i      <= '0';
+				sci_state       <= IDLE;
+
+			when GET_WA =>
+				if cnt = 4 then
+					cnt           := 0;
+					sci_state     <= IDLE;
+				else
+					sci_state     <= GET_WA_WAIT;
+					sci_addr_i    <= '0' & x"22";
+					sci_ch_i      <= x"0";
+					sci_ch_i(cnt) <= '1';
+					sci_read_i    <= '1';
+				end if;
+			when GET_WA_WAIT  =>
+				sci_state       <= GET_WA_WAIT2;
+			when GET_WA_WAIT2 =>
+				sci_state       <= GET_WA_FINISH;
+			when GET_WA_FINISH =>
+				wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
+				sci_state       <= GET_WA;    
+				cnt             := cnt + 1;
+		end case;
+
+		if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
+			SCI_NACK <= '1';
+		else
+			SCI_NACK <= '0';
+		end if;
+	end if;
+end process;
+    
+  
+
+--Generate LED signals
+----------------------
+process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+		led_counter <= led_counter + 1;
+		if buf_med_dataready_out = '1' then
+			rx_led <= '1';
+		elsif led_counter = 0 then
+			rx_led <= '0';
+		end if;
+		if tx_k = '0' then
+			tx_led <= '1';
+		elsif led_counter = 0 then
+			tx_led <= '0';
+		end if;
+	end if;
+end process;
+
+stat_op(15)           <= send_reset_words_q;
+stat_op(14)           <= buf_stat_op(14);
+stat_op(13)           <= make_trbnet_reset_q;
+stat_op(12)           <= '0';
+stat_op(11)           <= tx_led; --tx led
+stat_op(10)           <= rx_led; --rx led
+stat_op(9 downto 0)   <= buf_stat_op(9 downto 0);
+
+-- Debug output
+stat_debug(7 downto 0)   <= rx_data;
+stat_debug(16)           <= rx_k;
+stat_debug(19 downto 18) <= (others => '0');
+stat_debug(23 downto 20) <= buf_stat_debug(3 downto 0);
+stat_debug(24)           <= fifo_rx_rd_en;
+stat_debug(25)           <= fifo_rx_wr_en;
+stat_debug(26)           <= fifo_rx_reset;
+stat_debug(27)           <= fifo_rx_empty;
+stat_debug(28)           <= fifo_rx_full;
+stat_debug(29)           <= last_rx(8);
+stat_debug(30)           <= rx_allow_q;
+stat_debug(41 downto 31) <= (others => '0');
+stat_debug(42)           <= SYSCLK;
+stat_debug(43)           <= SYSCLK;
+stat_debug(59 downto 44) <= (others => '0');
+stat_debug(63 downto 60) <= buf_stat_debug(3 downto 0);
+
+
+end architecture;
+
diff --git a/hub_SODA/sources/lattice/trb_net16_med_syncfull_ecp3_sfp.vhd b/hub_SODA/sources/lattice/trb_net16_med_syncfull_ecp3_sfp.vhd
new file mode 100644
index 0000000..2b37483
--- /dev/null
+++ b/hub_SODA/sources/lattice/trb_net16_med_syncfull_ecp3_sfp.vhd
@@ -0,0 +1,998 @@
+--Media interface for Lattice ECP3 using PCS at 2GHz, RX clock == TX clock
+--For fully synchronized FPGAs only!
+--Either 200 MHz input for 2GBit or 125 MHz for 2.5GBit.
+--system clock can be 100 MHz or 125 MHz
+
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+--use ieee.numeric_std.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.std_logic_arith.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+use work.med_sync_define.all;
+
+
+entity trb_net16_med_syncfull_ecp3_sfp is
+  port(
+    CLK          : in  std_logic; -- SerDes clock
+    SYSCLK       : in  std_logic; -- fabric clock
+    RESET        : in  std_logic; -- synchronous reset
+    CLEAR        : in  std_logic; -- asynchronous reset
+    CLK_EN       : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic_vector(3 downto 0);
+    MED_READ_OUT       : out std_logic_vector(3 downto 0);
+    MED_DATA_OUT       : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic_vector(3 downto 0);
+    MED_READ_IN        : in  std_logic_vector(3 downto 0);
+    REFCLK2CORE_OUT    : out std_logic;
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic_vector(3 downto 0);
+    SD_RXD_N_IN        : in  std_logic_vector(3 downto 0);
+    SD_TXD_P_OUT       : out std_logic_vector(3 downto 0);
+    SD_TXD_N_OUT       : out std_logic_vector(3 downto 0);
+    SD_REFCLK_P_IN     : in  std_logic;
+    SD_REFCLK_N_IN     : in  std_logic;
+    SD_PRSNT_N_IN      : in  std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out std_logic_vector(3 downto 0); -- SFP disable
+	--Synchronous signals
+	RX_DLM             : out std_logic_vector(3 downto 0);
+	RX_DLM_WORD        : out std_logic_vector(4*8-1 downto 0);
+	TX_DLM             : in std_logic_vector(3 downto 0);
+	TX_DLM_WORD        : in std_logic_vector(4*8-1 downto 0);
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    -- Status and control port
+    STAT_OP            : out  std_logic_vector (4*16-1 downto 0);
+    CTRL_OP            : in  std_logic_vector (4*16-1 downto 0);
+    STAT_DEBUG         : out  std_logic_vector (64*4-1 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end entity;
+
+architecture arch_ecp3_sfp_4 of trb_net16_med_syncfull_ecp3_sfp is
+ 
+component serdes_sync_200_full is
+  port (
+------------------
+-- CH0 --
+    hdinp_ch0, hdinn_ch0    :   in std_logic;
+    hdoutp_ch0, hdoutn_ch0   :   out std_logic;
+    sci_sel_ch0    :   in std_logic;
+    rxiclk_ch0    :   in std_logic;
+    txiclk_ch0    :   in std_logic;
+    rx_full_clk_ch0   :   out std_logic;
+    rx_half_clk_ch0   :   out std_logic;
+    tx_full_clk_ch0   :   out std_logic;
+    tx_half_clk_ch0   :   out std_logic;
+    fpga_rxrefclk_ch0    :   in std_logic;
+    txdata_ch0    :   in std_logic_vector (7 downto 0);
+    tx_k_ch0    :   in std_logic;
+    tx_force_disp_ch0    :   in std_logic;
+    tx_disp_sel_ch0    :   in std_logic;
+    rxdata_ch0   :   out std_logic_vector (7 downto 0);
+    rx_k_ch0   :   out std_logic;
+    rx_disp_err_ch0   :   out std_logic;
+    rx_cv_err_ch0   :   out std_logic;
+    rx_serdes_rst_ch0_c    :   in std_logic;
+    sb_felb_ch0_c    :   in std_logic;
+    sb_felb_rst_ch0_c    :   in std_logic;
+    tx_pcs_rst_ch0_c    :   in std_logic;
+    tx_pwrup_ch0_c    :   in std_logic;
+    rx_pcs_rst_ch0_c    :   in std_logic;
+    rx_pwrup_ch0_c    :   in std_logic;
+    rx_los_low_ch0_s   :   out std_logic;
+    lsm_status_ch0_s   :   out std_logic;
+    rx_cdr_lol_ch0_s   :   out std_logic;
+    tx_div2_mode_ch0_c   : in std_logic;
+    rx_div2_mode_ch0_c   : in std_logic;
+-- CH1 --
+    hdinp_ch1, hdinn_ch1    :   in std_logic;
+    hdoutp_ch1, hdoutn_ch1   :   out std_logic;
+    sci_sel_ch1    :   in std_logic;
+    rxiclk_ch1    :   in std_logic;
+    txiclk_ch1    :   in std_logic;
+    rx_full_clk_ch1   :   out std_logic;
+    rx_half_clk_ch1   :   out std_logic;
+    tx_full_clk_ch1   :   out std_logic;
+    tx_half_clk_ch1   :   out std_logic;
+    fpga_rxrefclk_ch1    :   in std_logic;
+    txdata_ch1    :   in std_logic_vector (7 downto 0);
+    tx_k_ch1    :   in std_logic;
+    tx_force_disp_ch1    :   in std_logic;
+    tx_disp_sel_ch1    :   in std_logic;
+    rxdata_ch1   :   out std_logic_vector (7 downto 0);
+    rx_k_ch1   :   out std_logic;
+    rx_disp_err_ch1   :   out std_logic;
+    rx_cv_err_ch1   :   out std_logic;
+    rx_serdes_rst_ch1_c    :   in std_logic;
+    sb_felb_ch1_c    :   in std_logic;
+    sb_felb_rst_ch1_c    :   in std_logic;
+    tx_pcs_rst_ch1_c    :   in std_logic;
+    tx_pwrup_ch1_c    :   in std_logic;
+    rx_pcs_rst_ch1_c    :   in std_logic;
+    rx_pwrup_ch1_c    :   in std_logic;
+    rx_los_low_ch1_s   :   out std_logic;
+    lsm_status_ch1_s   :   out std_logic;
+    rx_cdr_lol_ch1_s   :   out std_logic;
+    tx_div2_mode_ch1_c   : in std_logic;
+    rx_div2_mode_ch1_c   : in std_logic;
+-- CH2 --
+    hdinp_ch2, hdinn_ch2    :   in std_logic;
+    hdoutp_ch2, hdoutn_ch2   :   out std_logic;
+    sci_sel_ch2    :   in std_logic;
+    rxiclk_ch2    :   in std_logic;
+    txiclk_ch2    :   in std_logic;
+    rx_full_clk_ch2   :   out std_logic;
+    rx_half_clk_ch2   :   out std_logic;
+    tx_full_clk_ch2   :   out std_logic;
+    tx_half_clk_ch2   :   out std_logic;
+    fpga_rxrefclk_ch2    :   in std_logic;
+    txdata_ch2    :   in std_logic_vector (7 downto 0);
+    tx_k_ch2    :   in std_logic;
+    tx_force_disp_ch2    :   in std_logic;
+    tx_disp_sel_ch2    :   in std_logic;
+    rxdata_ch2   :   out std_logic_vector (7 downto 0);
+    rx_k_ch2   :   out std_logic;
+    rx_disp_err_ch2   :   out std_logic;
+    rx_cv_err_ch2   :   out std_logic;
+    rx_serdes_rst_ch2_c    :   in std_logic;
+    sb_felb_ch2_c    :   in std_logic;
+    sb_felb_rst_ch2_c    :   in std_logic;
+    tx_pcs_rst_ch2_c    :   in std_logic;
+    tx_pwrup_ch2_c    :   in std_logic;
+    rx_pcs_rst_ch2_c    :   in std_logic;
+    rx_pwrup_ch2_c    :   in std_logic;
+    rx_los_low_ch2_s   :   out std_logic;
+    lsm_status_ch2_s   :   out std_logic;
+    rx_cdr_lol_ch2_s   :   out std_logic;
+    tx_div2_mode_ch2_c   : in std_logic;
+    rx_div2_mode_ch2_c   : in std_logic;
+-- CH3 --
+    hdinp_ch3, hdinn_ch3    :   in std_logic;
+    hdoutp_ch3, hdoutn_ch3   :   out std_logic;
+    sci_sel_ch3    :   in std_logic;
+    rxiclk_ch3    :   in std_logic;
+    txiclk_ch3    :   in std_logic;
+    rx_full_clk_ch3   :   out std_logic;
+    rx_half_clk_ch3   :   out std_logic;
+    tx_full_clk_ch3   :   out std_logic;
+    tx_half_clk_ch3   :   out std_logic;
+    fpga_rxrefclk_ch3    :   in std_logic;
+    txdata_ch3    :   in std_logic_vector (7 downto 0);
+    tx_k_ch3    :   in std_logic;
+    tx_force_disp_ch3    :   in std_logic;
+    tx_disp_sel_ch3    :   in std_logic;
+    rxdata_ch3   :   out std_logic_vector (7 downto 0);
+    rx_k_ch3   :   out std_logic;
+    rx_disp_err_ch3   :   out std_logic;
+    rx_cv_err_ch3   :   out std_logic;
+    rx_serdes_rst_ch3_c    :   in std_logic;
+    sb_felb_ch3_c    :   in std_logic;
+    sb_felb_rst_ch3_c    :   in std_logic;
+    tx_pcs_rst_ch3_c    :   in std_logic;
+    tx_pwrup_ch3_c    :   in std_logic;
+    rx_pcs_rst_ch3_c    :   in std_logic;
+    rx_pwrup_ch3_c    :   in std_logic;
+    rx_los_low_ch3_s   :   out std_logic;
+    lsm_status_ch3_s   :   out std_logic;
+    rx_cdr_lol_ch3_s   :   out std_logic;
+    tx_div2_mode_ch3_c   : in std_logic;
+    rx_div2_mode_ch3_c   : in std_logic;
+---- Miscillaneous ports
+    sci_wrdata    :   in std_logic_vector (7 downto 0);
+    sci_addr    :   in std_logic_vector (5 downto 0);
+    sci_rddata   :   out std_logic_vector (7 downto 0);
+    sci_sel_quad    :   in std_logic;
+    sci_rd    :   in std_logic;
+    sci_wrn    :   in std_logic;
+    fpga_txrefclk  :   in std_logic;
+    tx_serdes_rst_c    :   in std_logic;
+    tx_pll_lol_qd_s   :   out std_logic;
+    tx_sync_qd_c    :   in std_logic;
+    rst_qd_c    :   in std_logic;
+    serdes_rst_qd_c    :   in std_logic);
+end component;
+
+component HUB_8to16_SODA is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		data_in                 : in std_logic_vector(7 downto 0);
+		char_is_k               : in std_logic;
+		fifo_data               : out std_logic_vector(17 downto 0);
+		fifo_full               : in std_logic;
+		fifo_write              : out std_logic;
+		RX_DLM                  : out std_logic;
+		RX_DLM_WORD             : out std_logic_vector(7 downto 0);
+		error                   : out std_logic
+	);
+end component;
+
+component HUB_16to8_SODA is
+	port ( 
+		clock                   : in std_logic;
+		reset                   : in std_logic;
+		fifo_data               : in std_logic_vector(15 downto 0);
+		fifo_empty              : in std_logic;
+		fifo_read               : out std_logic;
+		TX_DLM                  : in std_logic;
+		TX_DLM_WORD             : in std_logic_vector(7 downto 0);
+		data_out                : out std_logic_vector(7 downto 0);
+		char_is_k               : out std_logic;
+		error                   : out std_logic
+	);
+end component;
+
+component HUB_SODA_clockcrossing is
+	port ( 
+		write_clock             : in std_logic;
+		read_clock              : in std_logic;
+		DLM_in                  : in std_logic;
+		DLM_WORD_in             : in std_logic_vector(7 downto 0);
+		DLM_out                 : out std_logic;
+		DLM_WORD_out            : out std_logic_vector(7 downto 0);
+		error                   : out std_logic
+	);
+end component;
+
+component HUB_posedge_to_pulse is
+	port (
+		clock_in        : in  std_logic;
+		clock_out       : in  std_logic;
+		en_clk          : in  std_logic;
+		signal_in       : in  std_logic;
+		pulse           : out std_logic
+	);
+end component;
+  
+  -- Placer Directives
+  attribute HGROUP : string;
+  -- for whole architecture
+  attribute HGROUP of arch_ecp3_sfp_4 : architecture  is "media_interface_group";
+  attribute syn_sharing : string;
+  attribute syn_sharing of arch_ecp3_sfp_4 : architecture is "off";
+  type array4x8_type is array(3 downto 0) of std_logic_vector(7 downto 0);
+  type array_4x4_type is array(3 downto 0) of std_logic_vector(3 downto 0);
+
+
+  signal refck2core             : std_logic;
+  --reset signals
+  signal ffc_quad_rst           : std_logic;
+  --serdes connections
+  signal tx_data                : array4x8_type;
+  signal tx_k                   : std_logic_vector(4*1-1 downto 0);
+  signal rx_data                : array4x8_type;
+  signal rx_k                   : std_logic_vector(4*1-1 downto 0);  
+  signal link_ok                : std_logic_vector(4*1-1 downto 0);
+  signal link_ok_q              : std_logic_vector(4*1-1 downto 0);
+  --rx fifo signals
+  signal fifo_rx_rd_en          : std_logic_vector(4*1-1 downto 0);
+  signal fifo_rx_wr_en          : std_logic_vector(4*1-1 downto 0);
+  signal fifo_rx_reset          : std_logic_vector(4*1-1 downto 0);
+  signal fifo_rx_din            : std_logic_vector(4*18-1 downto 0);
+  signal fifo_rx_dout           : std_logic_vector(4*18-1 downto 0);
+  signal fifo_rx_full           : std_logic_vector(4*1-1 downto 0);
+  signal fifo_rx_empty          : std_logic_vector(4*1-1 downto 0);
+  --tx fifo signals
+  signal fifo_tx_rd_en          : std_logic_vector(4*1-1 downto 0);
+  signal fifo_tx_wr_en          : std_logic_vector(4*1-1 downto 0);
+  signal fifo_tx_reset          : std_logic_vector(4*1-1 downto 0);
+  signal fifo_tx_din            : std_logic_vector(4*18-1 downto 0);
+  signal fifo_tx_dout           : std_logic_vector(4*18-1 downto 0);
+  signal fifo_tx_full           : std_logic_vector(4*1-1 downto 0);
+  signal fifo_tx_empty          : std_logic_vector(4*1-1 downto 0);
+  signal fifo_tx_almost_full    : std_logic_vector(4*1-1 downto 0);
+  --rx path
+  signal rx_counter             : std_logic_vector(4*3-1 downto 0);
+  signal buf_med_dataready_out  : std_logic_vector(4*1-1 downto 0);
+  signal buf_med_data_out       : std_logic_vector(4*16-1 downto 0);
+  signal buf_med_packet_num_out : std_logic_vector(4*3-1 downto 0);
+  signal last_fifo_rx_empty     : std_logic_vector(4*1-1 downto 0);
+  --tx path
+  signal last_fifo_tx_empty     : std_logic_vector(4*1-1 downto 0);
+  --link status
+  signal fifo_rx_full_q         : std_logic_vector(4*1-1 downto 0);
+
+  signal rx_rst_n               : std_logic;
+  signal tx_rst_n               : std_logic;
+  
+  signal quad_rst               : std_logic_vector(4*1-1 downto 0);
+  signal lane_rst               : std_logic_vector(4*1-1 downto 0);
+  signal tx_allow               : std_logic_vector(4*1-1 downto 0);
+  signal rx_allow               : std_logic_vector(4*1-1 downto 0);
+  signal link_tx_ok             : std_logic_vector(4*1-1 downto 0);
+  signal link_rx_ok             : std_logic_vector(4*1-1 downto 0);
+  signal link_tx_ok_q           : std_logic_vector(4*1-1 downto 0);
+  signal link_rx_ok_q           : std_logic_vector(4*1-1 downto 0);
+  signal rx_fsm_state           : array_4x4_type;
+  signal tx_fsm_state           : array_4x4_type;
+
+  signal rx_allow_q             : std_logic_vector(4*1-1 downto 0); -- clock domain changed signal
+  signal tx_allow_q             : std_logic_vector(4*1-1 downto 0);
+  signal buf_stat_debug         : std_logic_vector(4*32-1 downto 0);
+
+  -- status inputs from SFP
+  signal sfp_prsnt_n            : std_logic_vector(4*1-1 downto 0);
+  signal sfp_los                : std_logic_vector(4*1-1 downto 0);
+
+  signal buf_STAT_OP            : std_logic_vector(4*16-1 downto 0);
+
+  signal led_counter            : unsigned(16 downto 0);
+  signal rx_led                 : std_logic_vector(4*1-1 downto 0);
+  signal tx_led                 : std_logic_vector(4*1-1 downto 0);
+
+  type arr5_t is array (0 to 3) of unsigned(4 downto 0);
+  signal reset_word_cnt         : arr5_t;
+  signal make_trbnet_reset      : std_logic_vector(4*1-1 downto 0);
+  signal make_trbnet_reset_q    : std_logic_vector(4*1-1 downto 0);
+  signal send_reset_words       : std_logic_vector(4*1-1 downto 0);
+  signal send_reset_words_q     : std_logic_vector(4*1-1 downto 0);
+  signal send_reset_in          : std_logic_vector(4*1-1 downto 0);
+  signal reset_i                : std_logic;
+  signal reset_i_rx             : std_logic_vector(4*1-1 downto 0);
+  signal pwr_up                 : std_logic_vector(4*1-1 downto 0);
+  signal rx_serdes_rst          : std_logic_vector(4*1-1 downto 0);
+  signal tx_pcs_rst             : std_logic_vector(4*1-1 downto 0);
+  signal rx_pcs_rst             : std_logic_vector(4*1-1 downto 0);
+  signal rst_qd                 : std_logic;
+  signal rst_qd_S               : std_logic_vector(3 downto 0);
+  signal rx_los_low             : std_logic_vector(3 downto 0);
+  signal rx_los_low_q           : std_logic_vector(3 downto 0);
+  signal rx_cdr_lol             : std_logic_vector(3 downto 0);
+  signal rx_cdr_lol_q           : std_logic_vector(3 downto 0);
+  signal rx_cv_err              : std_logic_vector(3 downto 0);
+  signal rx_cv_err_q            : std_logic_vector(3 downto 0);
+  signal tx_pll_lol             : std_logic;
+  signal tx_pll_lol_q           : std_logic;
+	
+  signal tx_sync_qd_c           : std_logic;
+  signal tx_sync_qd_c_S         : std_logic;
+
+  signal rx_fullclk_i           : std_logic_vector(3 downto 0);
+  signal tx_fullclk_i           : std_logic_vector(3 downto 0);
+  
+  signal sci_ch_i               : std_logic_vector(3 downto 0);
+  signal sci_addr_i             : std_logic_vector(8 downto 0);
+  signal sci_data_in_i          : std_logic_vector(7 downto 0);
+  signal sci_data_out_i         : std_logic_vector(7 downto 0);
+  signal sci_read_i             : std_logic;
+  signal sci_write_i            : std_logic;
+  signal sci_write_shift_i      : std_logic_vector(2 downto 0);
+  signal sci_read_shift_i       : std_logic_vector(2 downto 0);
+
+  signal RX_DLM_S               : std_logic_vector(3 downto 0);
+  signal RX_DLM_WORD_S          : std_logic_vector(8*4-1 downto 0);
+
+  attribute syn_keep : boolean;
+  attribute syn_preserve : boolean;
+  attribute syn_keep of led_counter : signal is true;
+  attribute syn_keep of send_reset_in : signal is true;
+  attribute syn_keep of reset_i : signal is true;
+  attribute syn_preserve of reset_i : signal is true;
+  attribute syn_keep of SCI_DATA_OUT : signal is true;
+  attribute syn_preserve of SCI_DATA_OUT : signal is true;
+
+begin
+
+--------------------------------------------------------------------------
+-- Internal Resets
+--------------------------------------------------------------------------
+PROC_RESET : process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+		reset_i <= RESET;
+		pwr_up  <= x"F"; --not CTRL_OP(i*16+14);
+	end if;
+end process;
+
+THE_SENDRESET_SYNC: signal_sync
+	generic map(
+		DEPTH => 1,
+		WIDTH => 4
+	)
+	port map(
+		RESET => '0',
+		D_IN(0) => ctrl_op(15),
+		D_IN(1) => ctrl_op(15+16),
+		D_IN(2) => ctrl_op(15+32),
+		D_IN(3) => ctrl_op(15+48),
+		CLK0 => SYSCLK,
+		CLK1 => CLK,
+		D_OUT(0) => send_reset_in(0),
+		D_OUT(1) => send_reset_in(1),
+		D_OUT(2) => send_reset_in(2),
+		D_OUT(3) => send_reset_in(3)
+	);
+
+--------------------------------------------------------------------------
+-- Synchronizer stages
+--------------------------------------------------------------------------
+
+-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
+THE_SFPSIGNALS_SYNC: signal_sync
+	generic map(
+		DEPTH => 1,
+		WIDTH => 29
+	)
+	port map(
+		RESET             => '0',
+		D_IN(3 downto 0)  => SD_PRSNT_N_IN,
+		D_IN(7 downto 4)  => SD_LOS_IN,
+		D_IN(11 downto 8) => send_reset_words,
+		D_IN(15 downto 12) => link_ok,
+		D_IN(19 downto 16) => rx_los_low,
+		D_IN(23 downto 20) => rx_cdr_lol,
+		D_IN(27 downto 24) => rx_cv_err,
+		D_IN(28) => tx_pll_lol,
+		CLK0              => SYSCLK,
+		CLK1              => SYSCLK,
+		D_OUT(3 downto 0) => sfp_prsnt_n,
+		D_OUT(7 downto 4) => sfp_los,
+		D_OUT(11 downto 8)=> send_reset_words_q,
+		D_OUT(15 downto 12) => link_ok_q,
+		D_OUT(19 downto 16) => rx_los_low_q,
+		D_OUT(23 downto 20) => rx_cdr_lol_q,
+		D_OUT(27 downto 24) => rx_cv_err_q,
+		D_OUT(28) => tx_pll_lol_q
+	);
+
+	
+process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+		for i in 0 to 3 loop
+			if (tx_allow(i)='1') and (link_tx_ok_q(i)='1') then
+				tx_allow_q(i) <= '1';
+			else
+				tx_allow_q(i) <= '0';
+			end if;
+			if (rx_allow(i)='1') and (link_rx_ok_q(i)='1') then
+				rx_allow_q(i) <= '1';
+			else
+				rx_allow_q(i) <= '0';
+			end if;
+		end loop;
+		link_tx_ok_q <= link_tx_ok;
+		link_rx_ok_q <= link_rx_ok;
+	end if;
+end process;
+
+process(CLK)
+begin
+	if rising_edge(CLK) then
+		for i in 0 to 3 loop
+			if tx_fsm_state(i)=x"5" then
+				link_tx_ok(i) <= '1';
+			else
+				link_tx_ok(i) <= '0';
+			end if;
+			if (rx_fsm_state(i)=x"6") then
+				link_rx_ok(i) <= '1';
+			else
+				link_rx_ok(i) <= '0';
+			end if;
+		end loop;
+		fifo_rx_full_q <= fifo_rx_full;
+	end if;
+end process;
+
+
+--------------------------------------------------------------------------
+-- Main control state machine, startup control for SFP
+--------------------------------------------------------------------------
+gen_LSM : for i in 0 to 3 generate
+	THE_SFP_LSM: trb_net16_lsm_sfp
+		generic map (
+			HIGHSPEED_STARTUP => c_YES
+		)  
+		port map(
+			SYSCLK => SYSCLK,
+			RESET => reset_i,
+			CLEAR => clear,
+			SFP_MISSING_IN => sfp_prsnt_n(i),
+			SFP_LOS_IN => sfp_los(i),
+			SD_LINK_OK_IN => link_ok_q(i),
+			SD_LOS_IN => rx_los_low_q(i),
+			SD_TXCLK_BAD_IN => tx_pll_lol_q,
+			SD_RXCLK_BAD_IN => rx_cdr_lol_q(i),
+			SD_RETRY_IN => '0', -- '0' = handle byte swapping in logic, '1' = simply restart link and hope
+			SD_ALIGNMENT_IN => "01", -- no swapping
+			SD_CV_IN(0) => rx_cv_err_q(i),
+			SD_CV_IN(1) => rx_cv_err_q(i),
+			FULL_RESET_OUT => quad_rst(i),
+			LANE_RESET_OUT => lane_rst(i),
+			TX_ALLOW_OUT => tx_allow(i),
+			RX_ALLOW_OUT => rx_allow(i),
+			SWAP_BYTES_OUT => open,
+			STAT_OP => buf_stat_op(i*16+15 downto i*16),
+			CTRL_OP => ctrl_op(i*16+15 downto i*16),
+			STAT_DEBUG => buf_stat_debug(i*32+31 downto i*32)
+		);
+
+	sd_txdis_out(i) <= quad_rst(i) or reset_i;
+	ffc_quad_rst <= quad_rst(0);
+
+end generate;
+
+
+PROC_SCI : process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+		if SCI_READ = '1' or SCI_WRITE = '1' then
+			sci_ch_i(0)   <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_ch_i(1)   <=     SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_ch_i(2)   <= not SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_ch_i(3)   <=     SCI_ADDR(6) and     SCI_ADDR(7) and not SCI_ADDR(8);
+			sci_addr_i    <= SCI_ADDR;
+			sci_data_in_i <= SCI_DATA_IN;
+		end if;
+		sci_read_shift_i  <= sci_read_shift_i(1 downto 0) & SCI_READ;
+		sci_write_shift_i <= sci_write_shift_i(1 downto 0) & SCI_WRITE;
+		SCI_DATA_OUT      <= sci_data_out_i;
+	end if;
+end process;
+
+sci_write_i <= or_all(sci_write_shift_i);
+sci_read_i <= or_all(sci_read_shift_i);
+SCI_ACK <= sci_write_shift_i(2) or sci_read_shift_i(2);
+  
+THE_SERDES: serdes_sync_200_full 
+	port map(
+-- CH0 --
+		HDINP_CH0           => sd_rxd_p_in(0),
+		HDINN_CH0           => sd_rxd_n_in(0),
+		HDOUTP_CH0          => sd_txd_p_out(0),
+		HDOUTN_CH0          => sd_txd_n_out(0),
+		SCI_SEL_CH0         => sci_ch_i(0),
+		RXICLK_CH0          => rx_fullclk_i(0), -- CLK, -- ?
+		TXICLK_CH0          => CLK,
+		RX_FULL_CLK_CH0     => rx_fullclk_i(0),
+		RX_HALF_CLK_CH0     => open,
+		TX_FULL_CLK_CH0     => tx_fullclk_i(0),
+		TX_HALF_CLK_CH0     => open,
+		FPGA_RXREFCLK_CH0   => CLK,
+		TXDATA_CH0          => tx_data(0),
+		TX_K_CH0            => tx_k(0),
+		TX_FORCE_DISP_CH0   => '0',
+		TX_DISP_SEL_CH0     => '0',
+		RXDATA_CH0          => rx_data(0),
+		RX_K_CH0            => rx_k(0),
+		RX_DISP_ERR_CH0     => open,
+		RX_CV_ERR_CH0       => rx_cv_err(0),
+		rx_serdes_rst_ch0_c => rx_serdes_rst(0),
+		SB_FELB_CH0_C       => '0', --loopback enable
+		SB_FELB_RST_CH0_C   => '0', --loopback reset
+		tx_pcs_rst_ch0_c    => tx_pcs_rst(0),
+		TX_PWRUP_CH0_C      => '1', --tx power up
+		rx_pcs_rst_ch0_c    => rx_pcs_rst(0),
+		RX_PWRUP_CH0_C      => '1', --rx power up
+		RX_LOS_LOW_CH0_S    => rx_los_low(0),
+		LSM_STATUS_CH0_S    => link_ok(0),
+		RX_CDR_LOL_CH0_S    => rx_cdr_lol(0),
+		TX_DIV2_MODE_CH0_C  => '0', --full rate
+		RX_DIV2_MODE_CH0_C  => '0', --full rate
+-- CH1 --
+		HDINP_CH1           => sd_rxd_p_in(1),
+		HDINN_CH1           => sd_rxd_n_in(1),
+		HDOUTP_CH1          => sd_txd_p_out(1),
+		HDOUTN_CH1          => sd_txd_n_out(1),
+		SCI_SEL_CH1         => sci_ch_i(1),
+		RXICLK_CH1          => rx_fullclk_i(1), -- CLK, -- ?
+		TXICLK_CH1          => CLK,
+		RX_FULL_CLK_CH1     => rx_fullclk_i(1),
+		RX_HALF_CLK_CH1     => open,
+		TX_FULL_CLK_CH1     => tx_fullclk_i(1),
+		TX_HALF_CLK_CH1     => open,
+		FPGA_RXREFCLK_CH1   => CLK,
+		TXDATA_CH1          => tx_data(1),
+		TX_K_CH1            => tx_k(1),
+		TX_FORCE_DISP_CH1   => '0',
+		TX_DISP_SEL_CH1     => '0',
+		RXDATA_CH1          => rx_data(1),
+		RX_K_CH1            => rx_k(1),
+		RX_DISP_ERR_CH1     => open,
+		RX_CV_ERR_CH1       => rx_cv_err(1),
+		rx_serdes_rst_ch1_c => rx_serdes_rst(1),
+		SB_FELB_CH1_C       => '0', --loopback enable
+		SB_FELB_RST_CH1_C   => '0', --loopback reset
+		tx_pcs_rst_ch1_c => tx_pcs_rst(1),
+		TX_PWRUP_CH1_C      => '1', --tx power up
+		rx_pcs_rst_ch1_c    => rx_pcs_rst(1),
+		RX_PWRUP_CH1_C      => '1', --rx power up
+		RX_LOS_LOW_CH1_S    => rx_los_low(1),
+		LSM_STATUS_CH1_S    => link_ok(1),
+		RX_CDR_LOL_CH1_S    => rx_cdr_lol(1),
+		TX_DIV2_MODE_CH1_C  => '0', --full rate
+		RX_DIV2_MODE_CH1_C  => '0', --full rate
+-- CH2 --
+		HDINP_CH2           => sd_rxd_p_in(2),
+		HDINN_CH2           => sd_rxd_n_in(2),
+		HDOUTP_CH2          => sd_txd_p_out(2),
+		HDOUTN_CH2          => sd_txd_n_out(2),
+		SCI_SEL_CH2         => sci_ch_i(2),
+		RXICLK_CH2          => rx_fullclk_i(2), -- CLK, -- ?
+		TXICLK_CH2          => CLK,
+		RX_FULL_CLK_CH2     => rx_fullclk_i(2),
+		RX_HALF_CLK_CH2     => open,
+		TX_FULL_CLK_CH2     => tx_fullclk_i(2),
+		TX_HALF_CLK_CH2     => open,
+		FPGA_RXREFCLK_CH2   => CLK,
+		TXDATA_CH2          => tx_data(2),
+		TX_K_CH2            => tx_k(2),
+		TX_FORCE_DISP_CH2   => '0',
+		TX_DISP_SEL_CH2     => '0',
+		RXDATA_CH2          => rx_data(2),
+		RX_K_CH2            => rx_k(2),
+		RX_DISP_ERR_CH2     => open,
+		RX_CV_ERR_CH2       => rx_cv_err(2),
+		rx_serdes_rst_ch2_c => rx_serdes_rst(2),
+		SB_FELB_CH2_C       => '0', --loopback enable
+		SB_FELB_RST_CH2_C   => '0', --loopback reset
+		tx_pcs_rst_ch2_c => tx_pcs_rst(2),
+		TX_PWRUP_CH2_C      => '1', --tx power up
+		rx_pcs_rst_ch2_c    => rx_pcs_rst(2),
+		RX_PWRUP_CH2_C      => '1', --rx power up
+		RX_LOS_LOW_CH2_S    => rx_los_low(2),
+		LSM_STATUS_CH2_S    => link_ok(2),
+		RX_CDR_LOL_CH2_S    => rx_cdr_lol(2),
+		TX_DIV2_MODE_CH2_C  => '0', --full rate
+		RX_DIV2_MODE_CH2_C  => '0', --full rate
+-- CH3 --
+		HDINP_CH3           => sd_rxd_p_in(3),
+		HDINN_CH3           => sd_rxd_n_in(3),
+		HDOUTP_CH3          => sd_txd_p_out(3),
+		HDOUTN_CH3          => sd_txd_n_out(3),
+		SCI_SEL_CH3         => sci_ch_i(3),
+		RXICLK_CH3          => rx_fullclk_i(3),  -- CLK, -- ?
+		TXICLK_CH3          => CLK,
+		RX_FULL_CLK_CH3     => rx_fullclk_i(3),
+		RX_HALF_CLK_CH3     => open,
+		TX_FULL_CLK_CH3     => tx_fullclk_i(3),
+		TX_HALF_CLK_CH3     => open,
+		FPGA_RXREFCLK_CH3   => CLK,
+		TXDATA_CH3          => tx_data(3),
+		TX_K_CH3            => tx_k(3),
+		TX_FORCE_DISP_CH3   => '0',
+		TX_DISP_SEL_CH3     => '0',
+		RXDATA_CH3          => rx_data(3),
+		RX_K_CH3            => rx_k(3),          
+		RX_DISP_ERR_CH3     => open,
+		RX_CV_ERR_CH3       => rx_cv_err(3),
+		rx_serdes_rst_ch3_c => rx_serdes_rst(3),
+		SB_FELB_CH3_C       => '0', --loopback enable
+		SB_FELB_RST_CH3_C   => '0', --loopback reset
+		tx_pcs_rst_ch3_c => tx_pcs_rst(3),
+		TX_PWRUP_CH3_C      => '1', --tx power up
+		rx_pcs_rst_ch3_c    => rx_pcs_rst(3),
+		RX_PWRUP_CH3_C      => '1', --rx power up
+		RX_LOS_LOW_CH3_S    => rx_los_low(3),
+		LSM_STATUS_CH3_S    => link_ok(3),
+		RX_CDR_LOL_CH3_S    => rx_cdr_lol(3),
+		TX_DIV2_MODE_CH3_C  => '0', --full rate
+		RX_DIV2_MODE_CH3_C  => '0', --full rate
+---- Miscillaneous ports
+		SCI_WRDATA          => sci_data_in_i,
+		SCI_RDDATA          => sci_data_out_i,
+		SCI_ADDR            => sci_addr_i(5 downto 0),
+		SCI_SEL_QUAD        => sci_addr_i(8),
+		SCI_RD              => sci_read_i,
+		SCI_WRN             => sci_write_i,      
+		FPGA_TXREFCLK       => CLK,
+		TX_SERDES_RST_C     => CLEAR,
+		TX_PLL_LOL_QD_S     => tx_pll_lol,    
+		TX_SYNC_QD_C        => tx_sync_qd_c,
+		rst_qd_c            => rst_qd,
+		SERDES_RST_QD_C     => ffc_quad_rst
+	);
+	
+
+-------------------------------------------------      
+-- Reset FSM & Link states
+-------------------------------------------------
+process(CLK)
+begin
+	if (rising_edge(CLK)) then 
+		if rst_qd_S/="0000" then
+			rst_qd <= '1';
+		else
+			rst_qd <= '0';
+		end if;
+		tx_sync_qd_c <= tx_sync_qd_c_S;
+	end if;
+end process;
+
+process(CLK)
+variable prev_state_ok : std_logic_vector(0 to 3) := "0000";
+variable cntr : std_logic_vector(3 downto 0) := "0000";
+begin
+	if (rising_edge(CLK)) then 
+		if ((tx_fsm_state(0)=x"5") and (prev_state_ok(0)='0')) or
+		   ((tx_fsm_state(1)=x"5") and (prev_state_ok(1)='0')) or
+		   ((tx_fsm_state(2)=x"5") and (prev_state_ok(2)='0')) or
+		   ((tx_fsm_state(3)=x"5") and (prev_state_ok(3)='0')) then
+			tx_sync_qd_c_S <= not tx_sync_qd_c_S;
+			cntr := (others => '0');
+		else -- double toggle, necessary?
+			if cntr="1110" then
+				tx_sync_qd_c_S <= not tx_sync_qd_c_S;
+			end if;
+			if cntr/="1111" then
+				cntr := cntr+1;
+			end if;			
+		end if;
+		for i in 0 to 3 loop
+			if (tx_fsm_state(i)=x"5") then
+				prev_state_ok(i) := '1';
+			else
+				prev_state_ok(i) := '0';
+			end if;
+		end loop;
+	end if;
+end process;
+
+GENERATE_RESET_FSM: for i in 0 to 3 generate  
+
+THE_RX_FSM : rx_reset_fsm
+	port map(
+		RST_N               => rx_rst_n,
+		RX_REFCLK           => CLK,
+		TX_PLL_LOL_QD_S     => tx_pll_lol,
+		RX_SERDES_RST_CH_C  => rx_serdes_rst(i),
+		RX_CDR_LOL_CH_S     => rx_cdr_lol(i),
+		RX_LOS_LOW_CH_S     => rx_los_low(i),
+		RX_PCS_RST_CH_C     => rx_pcs_rst(i),
+		WA_POSITION         => "0000", -- for master
+		STATE_OUT           => rx_fsm_state(i) -- ready when x"6"
+	);
+
+rx_rst_n <= '0' when (RESET='1') or (CLEAR='1') else '1';
+
+THE_TX_FSM : tx_reset_fsm
+	port map(
+		RST_N           => tx_rst_n,
+		TX_REFCLK       => CLK,
+		TX_PLL_LOL_QD_S => tx_pll_lol,
+		RST_QD_C        => rst_qd_S(i),
+		TX_PCS_RST_CH_C => tx_pcs_rst(i),
+		STATE_OUT       => tx_fsm_state(i) -- ready when x"5"
+	);
+	
+process(CLK)
+begin
+	if (rising_edge(CLK)) then 
+		tx_rst_n <= not CLEAR;
+	end if;
+end process;
+
+end generate;
+    
+
+GENERATE_RXDATA_FSM: for i in 0 to 3 generate  
+
+	HUB_8to16_SODA1: HUB_8to16_SODA 
+		port map(
+			clock => rx_fullclk_i(i),
+			reset => RESET,
+			data_in => rx_data(i),
+			char_is_k => rx_k(i),
+			fifo_data => fifo_rx_din(i*18+17 downto i*18),
+			fifo_full => fifo_rx_full(i),
+			fifo_write => fifo_rx_wr_en(i),
+			RX_DLM => RX_DLM_S(i),
+			RX_DLM_WORD => RX_DLM_WORD_S(8*i+7 downto 8*i),
+			error => open
+		);
+
+	THE_FIFO_SFP_TO_FPGA: trb_net_fifo_16bit_bram_dualport
+		generic map(
+			USE_STATUS_FLAGS => c_NO)
+		port map( 
+			read_clock_in => SYSCLK,
+			write_clock_in => rx_fullclk_i(i),
+			read_enable_in => fifo_rx_rd_en(i),
+			write_enable_in => fifo_rx_wr_en(i),
+			fifo_gsr_in => fifo_rx_reset(i),
+			write_data_in => fifo_rx_din(i*18+17 downto i*18),
+			read_data_out => fifo_rx_dout(i*18+17 downto i*18),
+			full_out => fifo_rx_full(i),
+			empty_out => fifo_rx_empty(i)
+		);
+	fifo_rx_reset(i) <= reset_i or not rx_allow_q(i);
+	fifo_rx_rd_en(i) <= not fifo_rx_empty(i);
+
+	buf_med_data_out(i*16+15 downto i*16) <= fifo_rx_dout(i*18+15 downto i*18);
+	buf_med_dataready_out(i) <= not fifo_rx_dout(i*18+17) and not fifo_rx_dout(i*18+16) 
+								  and not last_fifo_rx_empty(i) and rx_allow_q(i);
+	buf_med_packet_num_out(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3);
+
+	THE_SYNC_PROC: process(SYSCLK)
+	begin
+		if rising_edge(SYSCLK)then
+			med_dataready_out(i) <= buf_med_dataready_out(i);
+			med_data_out(i*16+15 downto i*16) <= buf_med_data_out(i*16+15 downto i*16);
+			med_packet_num_out(i*3+2 downto i*3) <= buf_med_packet_num_out(i*3+2 downto i*3);
+			if reset_i = '1' then
+				med_dataready_out(i) <= '0';
+			end if;
+		end if;
+	end process;
+		
+	--rx packet counter
+	---------------------
+	THE_RX_PACKETS_PROC: process(SYSCLK)
+	begin
+		if (rising_edge(SYSCLK)) then
+			last_fifo_rx_empty(i) <= fifo_rx_empty(i);
+			if reset_i = '1' or rx_allow_q(i) = '0' then
+				rx_counter(i*3+2 downto i*3) <= c_H0;
+			else
+				if( buf_med_dataready_out(i) = '1' ) then
+					if( rx_counter(i*3+2 downto i*3) = c_max_word_number ) then
+						rx_counter(i*3+2 downto i*3) <= (others => '0');
+					else
+						rx_counter(i*3+2 downto i*3) <= rx_counter(i*3+2 downto i*3) + 1;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+	THE_CNT_RESET_PROC : process(rx_fullclk_i(i))
+	begin
+		if rising_edge(rx_fullclk_i(i)) then
+			reset_i_rx(i) <= reset_i;    
+			if reset_i_rx(i) = '1' then
+				send_reset_words(i)  <= '0';
+				make_trbnet_reset(i) <= '0';
+				reset_word_cnt(i)    <= (others => '0');
+			else
+				send_reset_words(i)   <= '0';
+				make_trbnet_reset(i)  <= '0';
+				if (rx_k(i)='1') and (rx_data(i)=x"FE") then
+					if reset_word_cnt(i)(4) = '0' then
+						reset_word_cnt(i) <= reset_word_cnt(i) + 1;
+					else
+						send_reset_words(i) <= '1';
+					end if;
+				else
+					reset_word_cnt(i)    <= (others => '0');
+					make_trbnet_reset(i) <= reset_word_cnt(i)(4);
+				end if;
+			end if;
+		end if;
+	end process;
+
+	THE_RESET_SYNC: HUB_posedge_to_pulse
+		port map(
+			clock_in => rx_fullclk_i(i),
+			clock_out => SYSCLK,
+			en_clk => '1',
+			signal_in => make_trbnet_reset(i),
+			pulse  => make_trbnet_reset_q(i)
+		);
+		
+	HUB_SODA_clockcrossing1: HUB_SODA_clockcrossing
+		port map(
+			write_clock => rx_fullclk_i(i),
+			read_clock => CLK,
+			DLM_in => RX_DLM_S(i),
+			DLM_WORD_in => RX_DLM_WORD_S(8*i+7 downto 8*i),
+			DLM_out => RX_DLM(i),
+			DLM_WORD_out => RX_DLM_WORD(i*8+7 downto i*8),
+			error => open
+		);
+		
+end generate; -- end GENERATE_RXDATA_FSM 
+
+GENERATE_TXDATA_FSM: for i in 0 to 3 generate  
+
+	HUB_16to8_SODA1: HUB_16to8_SODA 
+		port map(
+			clock => CLK,
+			reset => send_reset_in(i),
+			fifo_data => fifo_tx_dout(i*18+15 downto i*18),
+			fifo_empty => fifo_tx_empty(i),
+			fifo_read => fifo_tx_rd_en(i),
+			TX_DLM => TX_DLM(i),
+			TX_DLM_WORD => TX_DLM_WORD(i*8+7 downto i*8),
+			data_out => tx_data(i),
+			char_is_k => tx_k(i),
+			error => open
+		);
+		
+	--TX Fifo & Data output to Serdes
+	THE_FIFO_FPGA_TO_SFP: trb_net_fifo_16bit_bram_dualport
+		generic map(
+			USE_STATUS_FLAGS => c_NO)
+		port map( 
+			read_clock_in => CLK,
+			write_clock_in => SYSCLK,
+			read_enable_in => fifo_tx_rd_en(i),
+			write_enable_in => fifo_tx_wr_en(i),
+			fifo_gsr_in => fifo_tx_reset(i),
+			write_data_in => fifo_tx_din(i*18+17 downto i*18),
+			read_data_out => fifo_tx_dout(i*18+17 downto i*18),
+			full_out => fifo_tx_full(i),
+			empty_out => fifo_tx_empty(i),
+			almost_full_out => fifo_tx_almost_full(i)
+		);
+
+	fifo_tx_reset(i) <= reset_i or not tx_allow_q(i);
+	fifo_tx_din(i*18+17 downto i*18) <= med_packet_num_in(i*3+2) & med_packet_num_in(i*3+0) & med_data_in(i*16+15 downto i*16);
+	fifo_tx_wr_en(i) <= med_dataready_in(i) and tx_allow_q(i);
+	med_read_out(i) <= tx_allow_q(i) and not fifo_tx_almost_full(i);
+
+end generate;  -- end GENERATE_TXDATA_FSM 
+
+   
+--------------------------------------------------------------------------
+--------------------------------------------------------------------------
+
+-- SerDes clock output to FPGA fabric
+refclk2core_out <= '0';
+
+--------------------------------------------------------------------------
+--Generate LED signals
+--------------------------------------------------------------------------
+PROC_LED : process(SYSCLK)
+begin
+	if rising_edge(SYSCLK) then
+		led_counter <= led_counter + 1;
+
+		if led_counter = 0 then
+			rx_led <= x"0";
+		else
+			rx_led <= rx_led or buf_med_dataready_out;
+		end if;
+		if led_counter = 0 then
+			tx_led <= x"0";
+		else
+			tx_led <= tx_led or not (tx_k(3) & tx_k(2) & tx_k(1) & tx_k(0));
+		end if;
+	end if;
+end process;
+
+gen_outputs : for i in 0 to 3 generate
+	stat_op(i*16+15)              <= send_reset_words_q(i);
+	stat_op(i*16+14)              <= buf_stat_op(i*16+14);
+	stat_op(i*16+13)              <= make_trbnet_reset_q(i);
+	stat_op(i*16+12)              <= '0';
+	stat_op(i*16+11)              <= tx_led(i); --tx led
+	stat_op(i*16+10)              <= rx_led(I); --rx led
+	stat_op(i*16+9 downto i*16+0) <= buf_stat_op(i*16+9 downto i*16+0);
+												  
+	-- Debug output                                 
+	stat_debug(i*64+7 downto i*64+0)  <= rx_data(i);            
+	stat_debug(i*64+16) <= rx_k(i);               
+	stat_debug(i*64+19 downto i*64+18) <= (others => '0');
+	stat_debug(i*64+23 downto i*64+20) <= buf_stat_debug(i*16+3 downto i*16+0);
+	stat_debug(i*64+24)                <= fifo_rx_rd_en(i);
+	stat_debug(i*64+25)                <= fifo_rx_wr_en(i);
+	stat_debug(i*64+26)                <= fifo_rx_reset(i);
+	stat_debug(i*64+27)                <= fifo_rx_empty(i);
+	stat_debug(i*64+28)                <= fifo_rx_full_q(i);
+	stat_debug(i*64+29)                <= '0';
+	stat_debug(i*64+30)                <= rx_allow_q(i);
+	stat_debug(i*64+41 downto i*64+31) <= (others => '0');
+	stat_debug(i*64+42)                <= sysclk;
+	stat_debug(i*64+43)                <= sysclk;
+	stat_debug(i*64+59 downto i*64+44) <= (others => '0');
+	stat_debug(i*64+63 downto i*64+60) <= buf_stat_debug(i*16+3 downto i*16+0);
+end generate;
+
+end architecture;
\ No newline at end of file
diff --git a/soda_source/project/SODA_source.ldf b/hub_SODA/trb3_periph_hub_SODA.ldf
similarity index 59%
rename from soda_source/project/SODA_source.ldf
rename to hub_SODA/trb3_periph_hub_SODA.ldf
index f3daabf..08e66d6 100644
--- a/soda_source/project/SODA_source.ldf
+++ b/hub_SODA/trb3_periph_hub_SODA.ldf
@@ -1,42 +1,42 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="2.0" title="SODA_source" device="LFE3-150EA-8FN672C" synthesis="synplify" default_implementation="SODA_source">
+<BaliProject version="3.2" title="trb3_periph_hub_SODA" device="LFE3-150EA-8FN672C" default_implementation="trb3_periph_hub_SODA">
     <Options/>
-    <Implementation title="SODA_source" dir="SODA_source" description="SODA_source" default_strategy="Strategy1">
-        <Options def_top="TDC" top="trb3_periph_sodasource"/>
-        <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
+    <Implementation title="trb3_periph_hub_SODA" dir="trb3_periph_hub_SODA" description="trb3_periph_hub_SODA" synthesis="synplify" default_strategy="Strategy1">
+        <Options def_top="pll_in125_out125" top="trb3_periph_hub_SODA"/>
+        <Source name="trb3_periph_hub_SODA.vhd" type="VHDL" type_short="VHDL">
+            <Options top_module="trb3_periph_hub_SODA"/>
         </Source>
         <Source name="version.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/basics/priority_arbiter.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
         <Source name="../../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
@@ -48,28 +48,43 @@
         <Source name="../../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
+        <Source name="../../trbnet/basics/wide_adder_17x16.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="../../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
+        <Source name="../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
         <Source name="../../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
         <Source name="../../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net_sbuf4.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net_sbuf3.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net_sbuf2.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
         <Source name="../../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
@@ -108,154 +123,183 @@
         <Source name="../../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net16_hub_logic_2.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net16_hub_ipu_logic.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/special/slv_register.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
         <Source name="../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/lattice/ecp3/fifo_dualclock_width_16_reg.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
         <Source name="../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trb3/base/cores/pll_in125_out125.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.lpc" type="LPC_Module" type_short="LPC">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
+        <Source name="sources/lattice/ecp3/sfp_3sync_200_int.ipx" type="IPX_Module" type_short="IPX">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
+        <Source name="sources/HUB_8to16_SODA.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
+        <Source name="sources/HUB_16to8_SODA.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
+        <Source name="sources/HUB_SODA_clockcrossing.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../data_concentrator/sources/Panda_package.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../source/soda_hub.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../source/soda_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
+        <Source name="sources/lattice/trb_net16_med_sync3_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
+        <Source name="sources/lattice/trb_net16_med_syncfull_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/optical_link/f_divider.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../source/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>
-        <Source name="../../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
+        <Source name="../source/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/ecp3/serdes_sync_200_full.ipx" type="IPX_Module" type_short="IPX">
             <Options/>
         </Source>
-
-        <Source name="trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
-            <Options top_module="trb3_periph_sodasource"/>
+        <Source name="sources/lattice/ecp3/async_fifo_16x8_ecp3.ipx" type="IPX_Module" type_short="IPX">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/async_fifo_16x8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/lattice/serdes_tx_reset_sm.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="../source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="sources/HUB_posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
+            <Options/>
+        </Source>
+        <Source name="reveal_SODA1.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
+            <Options/>
         </Source>
-        <Source name="../../trb3/tdc_releases/tdc_v1.1.1/bit_sync.vhd" type="VHDL" type_short="VHDL">
+        <Source name="reveal_SODA2.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
             <Options/>
         </Source>
-        <Source name="../../source/soda_intercept.vhd" type="VHDL" type_short="VHDL">
+        <Source name="reveal_uplink1.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
             <Options/>
         </Source>
-        <Source name="../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" type="VHDL" type_short="VHDL">
+        <Source name="trb3_periph_hub_SODA.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>
-        <Source name="../trb3_periph_sodasource.lpf" type="Logic Preference" type_short="LPF">
+        <Source name="trb3_periph_hub_SODA.xcf" type="Programming Project File" type_short="Programming">
             <Options/>
         </Source>
     </Implementation>
-    <Strategy name="Strategy1" file="SODA_source1.sty"/>
+    <Strategy name="Strategy1" file="trb3_periph_hub_SODA1.sty"/>
 </BaliProject>
diff --git a/hub_SODA/trb3_periph_hub_SODA.lpf b/hub_SODA/trb3_periph_hub_SODA.lpf
new file mode 100644
index 0000000..97d0ee2
--- /dev/null
+++ b/hub_SODA/trb3_periph_hub_SODA.lpf
@@ -0,0 +1,313 @@
+rvl_alias "rx_clock_200" "rx_clock_200";
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#################################################################
+# Basic Settings
+#################################################################
+
+  SYSCONFIG MCCLK_FREQ = 20;
+
+  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
+  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
+  
+#################################################################
+# Reset Nets
+#################################################################  
+GSR_NET NET "GSR_N";  
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
+LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18" ;
+LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10" ;
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
+DEFINE PORT GROUP "CLK_group" "CLK*" ;
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
+#################################################################
+# Trigger I/O
+#################################################################
+#Trigger from fan-out
+LOCATE COMP "TRIGGER_LEFT" SITE "V3" ;
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24" ;
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
+#################################################################
+# To central FPGA
+#################################################################
+LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ;
+LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ;
+LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ;
+LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ;
+LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ;
+LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ;
+LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ;
+LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ;
+LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ;
+LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ;
+LOCATE COMP "FPGA5_COMM_10" SITE "V10" ;
+LOCATE COMP "FPGA5_COMM_11" SITE "W10" ;
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+LOCATE COMP "TEST_LINE_0" SITE "A5" ;
+LOCATE COMP "TEST_LINE_1" SITE "A6" ;
+LOCATE COMP "TEST_LINE_2" SITE "G8" ;
+LOCATE COMP "TEST_LINE_3" SITE "F9" ;
+LOCATE COMP "TEST_LINE_4" SITE "D9" ;
+LOCATE COMP "TEST_LINE_5" SITE "D10" ;
+LOCATE COMP "TEST_LINE_6" SITE "F10" ;
+LOCATE COMP "TEST_LINE_7" SITE "E10" ;
+LOCATE COMP "TEST_LINE_8" SITE "A8" ;
+LOCATE COMP "TEST_LINE_9" SITE "B8" ;
+LOCATE COMP "TEST_LINE_10" SITE "G10" ;
+LOCATE COMP "TEST_LINE_11" SITE "G9" ;
+LOCATE COMP "TEST_LINE_12" SITE "C9" ;
+LOCATE COMP "TEST_LINE_13" SITE "C10" ;
+LOCATE COMP "TEST_LINE_14" SITE "H10" ;
+LOCATE COMP "TEST_LINE_15" SITE "H11" ;
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
+#################################################################
+# Connection to AddOn
+#################################################################
+LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0   #1
+LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1   #3
+LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2   #5
+LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3   #7
+LOCATE COMP "SFP_MOD1_1" SITE "R1" ;#DQLL0_4   #9
+LOCATE COMP "SFP_MOD2_1" SITE "R2" ;#DQLL0_5   #11
+LOCATE COMP "SFP_RATESEL_1" SITE "N3" ;#DQSLL0_T  #13
+LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C  #15
+LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6   #17
+LOCATE COMP "SFP_TXFAULT_1" SITE "P6" ;#DQLL0_7   #19
+LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8   #21
+LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9   #23
+LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0   #25
+LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1   #27
+LOCATE COMP "SFP_MOD1_2" SITE "AB1" ;#DQLL2_2   #29
+LOCATE COMP "SFP_MOD2_2" SITE "AC1" ;#DQLL2_3   #31
+LOCATE COMP "SFP_RATESEL_2" SITE "AA1" ;#DQLL2_4   #33
+LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5   #35
+LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
+LOCATE COMP "SFP_TXFAULT_2" SITE "W6" ;#DQLL2_C   #39  #should be DQSLL2
+LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0   #2
+LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1   #4
+LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2   #6
+LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3   #8
+LOCATE COMP "SFP_MOD1_3" SITE "AB3" ;#DQLL3_4   #10
+LOCATE COMP "SFP_MOD2_3" SITE "AB4" ;#DQLL3_5   #12
+LOCATE COMP "SFP_RATESEL_3" SITE "Y6" ;#DQLL3_T   #14  #should be DQSLL3
+LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
+LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6   #18
+LOCATE COMP "SFP_TXFAULT_3" SITE "AA4" ;#DQLL3_7   #20
+LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8   #22
+LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9   #24
+LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0   #26
+LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1   #28
+LOCATE COMP "SFP_MOD1_4" SITE "T1" ;#DQLL1_2   #30
+LOCATE COMP "SFP_MOD2_4" SITE "U1" ;#DQLL1_3   #32
+LOCATE COMP "SFP_RATESEL_4" SITE "P4" ;#DQLL1_4   #34
+LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5   #36
+LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T  #38
+LOCATE COMP "SFP_TXFAULT_4" SITE "R4" ;#DQSLL1_C  #40
+LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0   #169
+LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1   #171
+LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2   #173
+LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3   #175
+LOCATE COMP "SFP_MOD1_5" SITE "AA26" ;#DQLR1_4   #177
+LOCATE COMP "SFP_MOD2_5" SITE "AB26" ;#DQLR1_5   #179
+LOCATE COMP "SFP_RATESEL_5" SITE "W21" ;#DQSLR1_T  #181
+LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C  #183
+LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6   #185
+LOCATE COMP "SFP_TXFAULT_5" SITE "AA23" ;#DQLR1_7   #187
+LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0   #170
+LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1   #172
+LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2   #174
+LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3   #176
+LOCATE COMP "SFP_MOD1_6" SITE "T26" ;#DQLR2_4   #178
+LOCATE COMP "SFP_MOD2_6" SITE "U26" ;#DQLR2_5   #180
+LOCATE COMP "SFP_RATESEL_6" SITE "V21" ;#DQSLR2_T  #182
+LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C  #184
+LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6   #186
+LOCATE COMP "SFP_TXFAULT_6" SITE "V24" ;#DQLR2_7   #188
+DEFINE PORT GROUP "SFP_group" "SFP*" ;
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#################################################################
+# Additional Lines to AddOn
+#################################################################
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
+#all lines are input only
+#line 4/5 go to PLL input
+LOCATE COMP "SPARE_LINE_0" SITE "M25" ;#194
+LOCATE COMP "SPARE_LINE_1" SITE "M26" ;#196
+LOCATE COMP "SPARE_LINE_2" SITE "W4" ;#198
+LOCATE COMP "SPARE_LINE_3" SITE "W5" ;#200
+LOCATE COMP "SPARE_LINE_4" SITE "M3" ;#DQUL3_8_OUTOFLANE_FPGA__3 #69
+LOCATE COMP "SPARE_LINE_5" SITE "M2" ;#DQUL3_9_OUTOFLANE_FPGA__3 #71  
+#################################################################
+# Flash ROM and Reboot
+#################################################################
+LOCATE COMP "FLASH_CLK" SITE "B12" ;
+LOCATE COMP "FLASH_CS" SITE "E11" ;
+LOCATE COMP "FLASH_DIN" SITE "E12" ;
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
+LOCATE COMP "PROGRAMN" SITE "B11" ;
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#################################################################
+# Misc
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "A13" ;
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
+#coding of FPGA number
+LOCATE COMP "CODE_LINE_1" SITE "AA20" ;
+LOCATE COMP "CODE_LINE_0" SITE "Y21" ;
+IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+#terminated differential pair to pads
+LOCATE COMP "SUPPL" SITE "C14" ;
+IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "F12" ;
+LOCATE COMP "LED_ORANGE" SITE "G13" ;
+LOCATE COMP "LED_RED" SITE "A15" ;
+LOCATE COMP "LED_YELLOW" SITE "A16" ;
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+MULTICYCLE TO GROUP "LED_group" 100.000000 ns ;
+
+
+
+#################################################################
+# Locate Serdes and media interfaces
+#################################################################
+LOCATE COMP   "THE_MEDIA_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
+LOCATE COMP   "THE_MEDIA_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+
+
+#REGION "MEDIA_UPLINK" "R90C95D" 13 25;
+#REGION "MEDIA_DOWNLINK" "R55C120D" 25 35;
+#REGION "REGION_SPI"   "R13C150D" 12 16 DEVSIZE;
+#REGION "REGION_IOBUF" "R10C43D"  88 86 DEVSIZE;
+
+LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; 
+LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
+
+LOCATE UGROUP "gen_sync_media_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE UGROUP "gen_full_media_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
+LOCATE UGROUP "THE_MEDIA_DOWNLINK/media_interface_group" REGION "MEDIA_DOWNLINK" ;
+
+#LOCATE UGROUP "THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_1_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_2_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_3_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_4_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_5_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+#LOCATE UGROUP "THE_HUB/gen_muxes_6_MPLEX/MUX_group" REGION "REGION_IOBUF" ;
+
+#LOCATE UGROUP "THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group"  REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group"     REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group"     REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_5_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_6_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+#LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF";
+
+
+MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
+
+
+#not releated:  
+MULTICYCLE FROM CLKNET "clk_100_i" TO CLKNET "rx_clock_200" 200 ns ;
+MULTICYCLE FROM CLKNET "rx_clock_200" TO CLKNET "clk_100_i" 200 ns ;
+MULTICYCLE FROM CLKNET "clk_200_i" TO CLKNET "rx_clock_200" 200 ns ;
+MULTICYCLE FROM CLKNET "rx_clock_200" TO CLKNET "clk_200_i" 200 ns ;
+
+MULTICYCLE FROM CLKNET "THE_MEDIA_UPLINK/sci_read_i" TO CLKNET "clk_100_i" 200 ns ;
+MULTICYCLE FROM CLKNET "THE_MEDIA_UPLINK/sci_read_i" TO CLKNET "clk_200_i" 200 ns ;
+MULTICYCLE FROM CLKNET "THE_MEDIA_UPLINK/sci_read_i" TO CLKNET "rx_clock_200" 200 ns ;
+
+
+BLOCK JTAGPATHS;
diff --git a/code/trb3_periph_hub.vhd b/hub_SODA/trb3_periph_hub_SODA.vhd
similarity index 68%
rename from code/trb3_periph_hub.vhd
rename to hub_SODA/trb3_periph_hub_SODA.vhd
index 75ac24b..81c2aa3 100644
--- a/code/trb3_periph_hub.vhd
+++ b/hub_SODA/trb3_periph_hub_SODA.vhd
@@ -6,15 +6,14 @@ library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
 use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
+--use work.trb3_components.all;
 use work.version.all;
+use work.soda_components.all;
+use work.panda_package.all; 
 
 
 
-entity trb3_periph_hub is
-  generic(
-    SYNC_MODE : integer range 0 to 1 := c_NO   --use the RX clock for internal logic and transmission. 4 SFP links only.
-    );
+entity trb3_periph_hub_SODA is
   port(
     --Clocks
     CLK_GPLL_LEFT  : in std_logic;      --Clock Manager 1/(2468), 125 MHz
@@ -71,7 +70,6 @@ entity trb3_periph_hub is
     TEST_LINE : out std_logic_vector(15 downto 0)
     );
 
-
   attribute syn_useioff                  : boolean;
   --no IO-FF for LEDs relaxes timing constraints
   attribute syn_useioff of LED_GREEN     : signal is false;
@@ -107,11 +105,105 @@ entity trb3_periph_hub is
 
 end entity;
 
-architecture trb3_periph_hub_arch of trb3_periph_hub is
+architecture trb3_periph_hub_SODA_arch of trb3_periph_hub_SODA is
   --Constants
   constant REGIO_NUM_STAT_REGS : integer := 2;
   constant REGIO_NUM_CTRL_REGS : integer := 2;
 
+component trb_net16_med_sync3_ecp3_sfp is
+  port(
+    CLK                : in  std_logic; -- SerDes clock
+    SYSCLK             : in  std_logic; -- fabric clock
+    RESET              : in  std_logic; -- synchronous reset
+    CLEAR              : in  std_logic; -- asynchronous reset
+    CLK_EN             : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic;
+    MED_READ_OUT       : out std_logic;
+    MED_DATA_OUT       : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic;
+    MED_READ_IN        : in  std_logic;
+    REFCLK2CORE_OUT    : out std_logic;
+    CLK_RX_HALF_OUT    : out std_logic;
+    CLK_RX_FULL_OUT    : out std_logic;
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic;
+    SD_RXD_N_IN        : in  std_logic;
+    SD_TXD_P_OUT       : out std_logic;
+    SD_TXD_N_OUT       : out std_logic;
+	SD_DLM_IN          : in  std_logic;
+	SD_DLM_WORD_IN     : in  std_logic_vector(7 downto 0);
+	SD_DLM_OUT         : out std_logic;
+	SD_DLM_WORD_OUT    : out  std_logic_vector(7 downto 0);
+    SD_PRSNT_N_IN      : in  std_logic;  -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic;  -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out  std_logic; -- SFP disable
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    SCI_NACK           : out std_logic := '0';
+    -- Status and control port
+    STAT_OP            : out std_logic_vector (15 downto 0);
+    CTRL_OP            : in  std_logic_vector (15 downto 0);
+    STAT_DEBUG         : out std_logic_vector (63 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end component;
+
+component trb_net16_med_syncfull_ecp3_sfp is
+  port(
+    CLK          : in  std_logic; -- SerDes clock
+    SYSCLK       : in  std_logic; -- fabric clock
+    RESET        : in  std_logic; -- synchronous reset
+    CLEAR        : in  std_logic; -- asynchronous reset
+    CLK_EN       : in  std_logic;
+    --Internal Connection
+    MED_DATA_IN        : in  std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_IN  : in  std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_IN   : in  std_logic_vector(3 downto 0);
+    MED_READ_OUT       : out std_logic_vector(3 downto 0);
+    MED_DATA_OUT       : out std_logic_vector(4*c_DATA_WIDTH-1 downto 0);
+    MED_PACKET_NUM_OUT : out std_logic_vector(4*c_NUM_WIDTH-1 downto 0);
+    MED_DATAREADY_OUT  : out std_logic_vector(3 downto 0);
+    MED_READ_IN        : in  std_logic_vector(3 downto 0);
+    REFCLK2CORE_OUT    : out std_logic;
+    --SFP Connection
+    SD_RXD_P_IN        : in  std_logic_vector(3 downto 0);
+    SD_RXD_N_IN        : in  std_logic_vector(3 downto 0);
+    SD_TXD_P_OUT       : out std_logic_vector(3 downto 0);
+    SD_TXD_N_OUT       : out std_logic_vector(3 downto 0);
+    SD_REFCLK_P_IN     : in  std_logic;
+    SD_REFCLK_N_IN     : in  std_logic;
+    SD_PRSNT_N_IN      : in  std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
+    SD_LOS_IN          : in  std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
+    SD_TXDIS_OUT       : out std_logic_vector(3 downto 0); -- SFP disable
+	--Synchronous signals
+	RX_DLM             : out std_logic_vector(3 downto 0);
+	RX_DLM_WORD        : out std_logic_vector(4*8-1 downto 0);
+	TX_DLM             : in std_logic_vector(3 downto 0);
+	TX_DLM_WORD        : in std_logic_vector(4*8-1 downto 0);
+    --Control Interface
+    SCI_DATA_IN        : in  std_logic_vector(7 downto 0) := (others => '0');
+    SCI_DATA_OUT       : out std_logic_vector(7 downto 0) := (others => '0');
+    SCI_ADDR           : in  std_logic_vector(8 downto 0) := (others => '0');
+    SCI_READ           : in  std_logic := '0';
+    SCI_WRITE          : in  std_logic := '0';
+    SCI_ACK            : out std_logic := '0';
+    -- Status and control port
+    STAT_OP            : out  std_logic_vector (4*16-1 downto 0);
+    CTRL_OP            : in  std_logic_vector (4*16-1 downto 0);
+    STAT_DEBUG         : out  std_logic_vector (64*4-1 downto 0);
+    CTRL_DEBUG         : in  std_logic_vector (63 downto 0)
+   );
+end component;
+
   attribute syn_keep     : boolean;
   attribute syn_preserve : boolean;
 
@@ -124,10 +216,10 @@ architecture trb3_periph_hub_arch of trb3_periph_hub is
   signal GSR_N                    : std_logic;
   attribute syn_keep of GSR_N     : signal is true;
   attribute syn_preserve of GSR_N : signal is true;
-  signal clk_100_internal         : std_logic;
-  signal clk_200_internal         : std_logic;
   signal rx_clock_100             : std_logic;
   signal rx_clock_200             : std_logic;
+  attribute syn_keep of rx_clock_200     : signal is true;
+  attribute syn_preserve of rx_clock_200 : signal is true;
 
   --Media Interface
   signal med_stat_op        : std_logic_vector (7*16-1 downto 0);
@@ -207,7 +299,27 @@ architecture trb3_periph_hub_arch of trb3_periph_hub is
   signal sci2_data_out : std_logic_vector(7 downto 0);
   signal sci2_addr     : std_logic_vector(8 downto 0);  
   
-  --FPGA Test
+    -- soda hub
+  signal soda_read_en      : std_logic;
+  signal soda_write_en     : std_logic;
+  signal soda_ack          : std_logic;
+  signal soda_addr         : std_logic_vector(3 downto 0);
+  signal soda_data_in      : std_logic_vector(31 downto 0);
+  signal soda_data_out     : std_logic_vector(31 downto 0);
+		
+ 
+  signal DLM_to_uplink_S           : std_logic;
+  signal DLM_WORD_to_uplink_S      : std_logic_vector(7 downto 0);
+  signal DLM_from_uplink_S         : std_logic;
+  signal DLM_WORD_from_uplink_S    : std_logic_vector(7 downto 0);
+
+  signal DLM_from_downlink_S       : std_logic_vector(3 downto 0);
+  signal DLM_WORD_from_downlink_S  : std_logic_vector(8*4-1 downto 0);
+  signal DLM_to_downlink_S         : std_logic_vector(3 downto 0);
+  signal DLM_WORD_to_downlink_S     : std_logic_vector(8*4-1 downto 0);
+
+  
+ --FPGA Test
   signal time_counter : unsigned(31 downto 0);
 
 
@@ -225,7 +337,7 @@ begin
     port map(
       CLEAR_IN      => '0',              -- reset input (high active, async)
       CLEAR_N_IN    => '1',              -- reset input (low active, async)
-      CLK_IN        => clk_200_internal, -- raw master clock, NOT from PLL/DLL!
+      CLK_IN        => clk_200_i,        -- raw master clock, NOT from PLL/DLL!
       SYSCLK_IN     => clk_100_i,        -- PLL/DLL remastered clock
       PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
       RESET_IN      => '0',              -- general reset signal (SYSCLK)
@@ -243,184 +355,68 @@ begin
   THE_MAIN_PLL : pll_in200_out100
     port map(
       CLK   => CLK_GPLL_RIGHT,
-      CLKOP => clk_100_internal,
-      CLKOK => clk_200_internal,
+      RESET => '0',
+      CLKOP => clk_100_i,
+      CLKOK => clk_200_i,
       LOCK  => pll_lock
       );
-      
-gen_sync_clocks : if SYNC_MODE = c_YES generate
-  clk_100_i <= rx_clock_100;
-  clk_200_i <= rx_clock_200;
-end generate;
-
-gen_local_clocks : if SYNC_MODE = c_NO generate
-  clk_100_i <= clk_100_internal;
-  clk_200_i <= clk_200_internal;
-end generate;
 
 
 ---------------------------------------------------------------------------
 -- The TrbNet media interface (to other FPGA)
 ---------------------------------------------------------------------------
-gen_full_media : if SYNC_MODE = c_NO generate
-  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp_4
-    generic map(
-      REVERSE_ORDER => c_NO,              --order of ports
-      FREQUENCY     => 200                --run on 200 MHz clock
-      )
-    port map(
-      CLK                => clk_200_i,
-      SYSCLK             => clk_100_i,
-      RESET              => reset_i,
-      CLEAR              => clear_i,
-      CLK_EN             => '1',
-      --Internal Connection
-      MED_DATA_IN(0*16+15 downto 0*16) => (others => '0'),
-      MED_DATA_IN(1*16+15 downto 1*16) => med_data_out(0*16+15 downto 0*16),
-      MED_DATA_IN(2*16+15 downto 2*16) => med_data_out(5*16+15 downto 5*16),
-      MED_DATA_IN(3*16+15 downto 3*16) => med_data_out(3*16+15 downto 3*16),
-      
-      MED_PACKET_NUM_IN(0*3+2 downto 0*3)  => "000",
-      MED_PACKET_NUM_IN(1*3+2 downto 1*3)  => med_packet_num_out(0*3+2 downto 0*3),
-      MED_PACKET_NUM_IN(2*3+2 downto 2*3)  => med_packet_num_out(5*3+2 downto 5*3),
-      MED_PACKET_NUM_IN(3*3+2 downto 3*3)  => med_packet_num_out(3*3+2 downto 3*3),
-      
-      MED_DATAREADY_IN(0) => '0',
-      MED_DATAREADY_IN(1) => med_dataready_out(0),
-      MED_DATAREADY_IN(2) => med_dataready_out(5),
-      MED_DATAREADY_IN(3) => med_dataready_out(3),
-
-      MED_READ_OUT(0) => open,
-      MED_READ_OUT(1) => med_read_in(0),
-      MED_READ_OUT(2) => med_read_in(5),
-      MED_READ_OUT(3) => med_read_in(3),
-
-      MED_DATA_OUT(0*16+15 downto 0*16) => open,
-      MED_DATA_OUT(1*16+15 downto 1*16) => med_data_in(0*16+15 downto 0*16),
-      MED_DATA_OUT(2*16+15 downto 2*16) => med_data_in(5*16+15 downto 5*16),
-      MED_DATA_OUT(3*16+15 downto 3*16) => med_data_in(3*16+15 downto 3*16),      
-      
-      MED_PACKET_NUM_OUT(0*3+2 downto 0*3)  => open,
-      MED_PACKET_NUM_OUT(1*3+2 downto 1*3)  => med_packet_num_in(0*3+2 downto 0*3),
-      MED_PACKET_NUM_OUT(2*3+2 downto 2*3)  => med_packet_num_in(5*3+2 downto 5*3),
-      MED_PACKET_NUM_OUT(3*3+2 downto 3*3)  => med_packet_num_in(3*3+2 downto 3*3),
 
-      MED_DATAREADY_OUT(0) => open,
-      MED_DATAREADY_OUT(1) => med_dataready_in(0),
-      MED_DATAREADY_OUT(2) => med_dataready_in(5),
-      MED_DATAREADY_OUT(3) => med_dataready_in(3),
 
-      MED_READ_IN(0) => '1',
-      MED_READ_IN(1) => med_read_out(0),
-      MED_READ_IN(2) => med_read_out(5),
-      MED_READ_IN(3) => med_read_out(3),      
-
-      REFCLK2CORE_OUT    => open,
-      --SFP Connection
-      SD_RXD_P_IN        => SERDES_ADDON_RX(11 downto 8),
-      SD_RXD_N_IN        => SERDES_ADDON_RX(15 downto 12),
-      SD_TXD_P_OUT       => SERDES_ADDON_TX(11 downto 8),
-      SD_TXD_N_OUT       => SERDES_ADDON_TX(15 downto 12),
-      SD_REFCLK_P_IN     => open,
-      SD_REFCLK_N_IN     => open,
-      SD_PRSNT_N_IN(0)   => '1',
-      SD_PRSNT_N_IN(1)   => FPGA5_COMM(0),
-      SD_PRSNT_N_IN(2)   => SFP_MOD0(5),
-      SD_PRSNT_N_IN(3)   => SFP_MOD0(3),
-      SD_LOS_IN(0)   => '1',
-      SD_LOS_IN(1)   => FPGA5_COMM(0),
-      SD_LOS_IN(2)   => SFP_LOS(5),
-      SD_LOS_IN(3)   => SFP_LOS(3),
-      SD_TXDIS_OUT(0)   => open,
-      SD_TXDIS_OUT(1)   => FPGA5_COMM(2),
-      SD_TXDIS_OUT(2)   => SFP_TXDIS(5),
-      SD_TXDIS_OUT(3)   => SFP_TXDIS(3),
-      
-      SCI_DATA_IN       => sci1_data_in,
-      SCI_DATA_OUT      => sci1_data_out,
-      SCI_ADDR          => sci1_addr,
-      SCI_READ          => sci1_read,
-      SCI_WRITE         => sci1_write,
-      SCI_ACK           => sci1_ack,
-      -- Status and control port
-      
-      STAT_OP(0*16+15 downto 0*16) => open,
-      STAT_OP(1*16+15 downto 1*16) => med_stat_op(0*16+15 downto 0*16),
-      STAT_OP(2*16+15 downto 2*16) => med_stat_op(5*16+15 downto 5*16),
-      STAT_OP(3*16+15 downto 3*16) => med_stat_op(3*16+15 downto 3*16),
-
-      CTRL_OP(0*16+15 downto 0*16) => x"0000",
-      CTRL_OP(1*16+15 downto 1*16) => med_ctrl_op(0*16+15 downto 0*16),
-      CTRL_OP(2*16+15 downto 2*16) => med_ctrl_op(5*16+15 downto 5*16),
-      CTRL_OP(3*16+15 downto 3*16) => med_ctrl_op(3*16+15 downto 3*16),
-      
-      STAT_DEBUG         => open,
-      CTRL_DEBUG         => (others => '0')
-      );
-end generate; 
- 
-gen_sync_media : if SYNC_MODE = c_YES generate 
   med_stat_op(3*16+15 downto 3*16) <= x"0007";
   med_stat_op(5*16+15 downto 5*16) <= x"0007";  
   
-  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
-  generic map(
-      SERDES_NUM  => 1,     --number of serdes in quad
-      EXT_CLOCK   => c_NO,  --use internal clock
-      USE_200_MHZ => c_YES, --run on 200 MHz clock
-      USE_CTC     => c_NO,
-      USE_SLAVE   =>  c_YES
-      )
+  THE_MEDIA_UPLINK : trb_net16_med_sync3_ecp3_sfp
     port map(
-      CLK                => clk_200_internal,
-      SYSCLK             => clk_100_i,
-      RESET              => reset_i,
-      CLEAR              => clear_i,
-      CLK_EN             => '1',
+      CLK => clk_200_i,
+      SYSCLK => clk_100_i,
+      RESET => reset_i,
+      CLEAR => clear_i,
+      CLK_EN => '1',
       --Internal Connection
-      MED_DATA_IN        => med_data_out(15 downto 0),
-      MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
-      MED_DATAREADY_IN   => med_dataready_out(0),
-      MED_READ_OUT       => med_read_in(0),
-      MED_DATA_OUT       => med_data_in(15 downto 0),
+      MED_DATA_IN => med_data_out(15 downto 0),
+      MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
+      MED_DATAREADY_IN => med_dataready_out(0),
+      MED_READ_OUT => med_read_in(0),
+      MED_DATA_OUT => med_data_in(15 downto 0),
       MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
-      MED_DATAREADY_OUT  => med_dataready_in(0),
-      MED_READ_IN        => med_read_out(0),
-      REFCLK2CORE_OUT    => open,
-      CLK_RX_HALF_OUT    => rx_clock_100,
-      CLK_RX_FULL_OUT    => rx_clock_200,
+      MED_DATAREADY_OUT => med_dataready_in(0),
+      MED_READ_IN => med_read_out(0),
+      REFCLK2CORE_OUT => open,
+      CLK_RX_HALF_OUT => rx_clock_100,
+      CLK_RX_FULL_OUT => rx_clock_200,
       --SFP Connection
-      SD_RXD_P_IN        => SERDES_ADDON_RX(8),
-      SD_RXD_N_IN        => SERDES_ADDON_RX(9),
-      SD_TXD_P_OUT       => SERDES_ADDON_TX(8),
-      SD_TXD_N_OUT       => SERDES_ADDON_TX(9),
-      SD_REFCLK_P_IN     => open,
-      SD_REFCLK_N_IN     => open,
-      SD_PRSNT_N_IN      => FPGA5_COMM(0),
-      SD_LOS_IN          => FPGA5_COMM(0),
-      SD_TXDIS_OUT       => FPGA5_COMM(2),
-      
-      SCI_DATA_IN        => sci1_data_in,
-      SCI_DATA_OUT       => sci1_data_out,
-      SCI_ADDR           => sci1_addr,
-      SCI_READ           => sci1_read,
-      SCI_WRITE          => sci1_write,
-      SCI_ACK            => sci1_ack,      
+      SD_RXD_P_IN => SERDES_ADDON_RX(8),
+      SD_RXD_N_IN => SERDES_ADDON_RX(9),
+      SD_TXD_P_OUT => SERDES_ADDON_TX(8),
+      SD_TXD_N_OUT => SERDES_ADDON_TX(9),
+      SD_DLM_IN => DLM_to_uplink_S,
+      SD_DLM_WORD_IN => DLM_WORD_to_uplink_S,
+      SD_DLM_OUT => DLM_from_uplink_S,
+      SD_DLM_WORD_OUT => DLM_WORD_from_uplink_S,
+      SD_PRSNT_N_IN => SFP_LOS(5), --//3?
+      SD_LOS_IN => SFP_LOS(5), --//3?
+      SD_TXDIS_OUT => SFP_TXDIS(5), --//3?
+
+      SCI_DATA_IN => sci1_data_in,
+      SCI_DATA_OUT => sci1_data_out,
+      SCI_ADDR => sci1_addr,
+      SCI_READ => sci1_read,
+      SCI_WRITE => sci1_write,
+      SCI_ACK => sci1_ack,      
       -- Status and control port
-      STAT_OP            => med_stat_op(15 downto 0),
-      CTRL_OP            => med_ctrl_op(15 downto 0),
-      STAT_DEBUG         => med_stat_debug(63 downto 0),
-      CTRL_DEBUG         => (others => '0')
+      STAT_OP => med_stat_op(15 downto 0),
+      CTRL_OP => med_ctrl_op(15 downto 0),
+      STAT_DEBUG => med_stat_debug(63 downto 0),
+      CTRL_DEBUG => (others => '0')
       );
-end generate;
-      
-THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4
-    generic map(
-      REVERSE_ORDER => c_NO,              --order of ports
-      FREQUENCY     => 200                --run on 200 MHz clock
-      )
-    port map(
-      CLK                => clk_200_i,
+
+THE_MEDIA_DOWNLINK : trb_net16_med_syncfull_ecp3_sfp port map(
+      CLK                => rx_clock_200,
       SYSCLK             => clk_100_i,
       RESET              => reset_i,
       CLEAR              => clear_i,
@@ -435,7 +431,7 @@ THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4
       MED_PACKET_NUM_IN(1*3+2 downto 1*3)  => med_packet_num_out(6*3+2 downto 6*3),
       MED_PACKET_NUM_IN(2*3+2 downto 2*3)  => med_packet_num_out(2*3+2 downto 2*3),
       MED_PACKET_NUM_IN(3*3+2 downto 3*3)  => med_packet_num_out(4*3+2 downto 4*3),
-      
+	  
       MED_DATAREADY_IN(0) => med_dataready_out(1),
       MED_DATAREADY_IN(1) => med_dataready_out(6),
       MED_DATAREADY_IN(2) => med_dataready_out(2),
@@ -445,7 +441,7 @@ THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4
       MED_READ_OUT(1) => med_read_in(6),
       MED_READ_OUT(2) => med_read_in(2),
       MED_READ_OUT(3) => med_read_in(4),
-
+	  
       MED_DATA_OUT(0*16+15 downto 0*16) => med_data_in(1*16+15 downto 1*16),
       MED_DATA_OUT(1*16+15 downto 1*16) => med_data_in(6*16+15 downto 6*16),
       MED_DATA_OUT(2*16+15 downto 2*16) => med_data_in(2*16+15 downto 2*16),
@@ -467,17 +463,20 @@ THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4
       MED_READ_IN(3) => med_read_out(4),      
 
       REFCLK2CORE_OUT    => open,
-      --SFP Connection
+
+	  --SFP Connection
       SD_RXD_P_IN        => SERDES_ADDON_RX(3 downto 0),
       SD_RXD_N_IN        => SERDES_ADDON_RX(7 downto 4),
       SD_TXD_P_OUT       => SERDES_ADDON_TX(3 downto 0),
       SD_TXD_N_OUT       => SERDES_ADDON_TX(7 downto 4),
-      SD_REFCLK_P_IN     => open,
-      SD_REFCLK_N_IN     => open,
+
+      SD_REFCLK_P_IN     => '0',
+      SD_REFCLK_N_IN     => '0',
       SD_PRSNT_N_IN(0)   => SFP_MOD0(1),
       SD_PRSNT_N_IN(1)   => SFP_MOD0(6),
       SD_PRSNT_N_IN(2)   => SFP_MOD0(2),
       SD_PRSNT_N_IN(3)   => SFP_MOD0(4),
+
       SD_LOS_IN(0)   => SFP_LOS(1),
       SD_LOS_IN(1)   => SFP_LOS(6),
       SD_LOS_IN(2)   => SFP_LOS(2),
@@ -486,15 +485,20 @@ THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4
       SD_TXDIS_OUT(1)   => SFP_TXDIS(6),
       SD_TXDIS_OUT(2)   => SFP_TXDIS(2),
       SD_TXDIS_OUT(3)   => SFP_TXDIS(4),
-
+	  
+	--Synchronous signals
+      RX_DLM => DLM_from_downlink_S,
+      RX_DLM_WORD => DLM_WORD_from_downlink_S,
+      TX_DLM => DLM_to_downlink_S,
+      TX_DLM_WORD => DLM_WORD_to_downlink_S,
+    --Control Interface
       SCI_DATA_IN       => sci2_data_in,
       SCI_DATA_OUT      => sci2_data_out,
       SCI_ADDR          => sci2_addr,
       SCI_READ          => sci2_read,
       SCI_WRITE         => sci2_write,
       SCI_ACK           => sci2_ack,      
-      -- Status and control port
-      
+    -- Status and control port
       STAT_OP(0*16+15 downto 0*16) => med_stat_op(1*16+15 downto 1*16),
       STAT_OP(1*16+15 downto 1*16) => med_stat_op(6*16+15 downto 6*16),
       STAT_OP(2*16+15 downto 2*16) => med_stat_op(2*16+15 downto 2*16),
@@ -506,9 +510,7 @@ THE_MEDIA_DOWNLINK : trb_net16_med_ecp3_sfp_4
       CTRL_OP(3*16+15 downto 3*16) => med_ctrl_op(4*16+15 downto 4*16),
       
       STAT_DEBUG         => open,
-      CTRL_DEBUG         => (others => '0')
-      );
-
+      CTRL_DEBUG         => (others => '0'));
 
       
 ---------------------------------------------------------------------------
@@ -590,9 +592,9 @@ THE_HUB : trb_net16_hub_base
 ---------------------------------------------------------------------------
   THE_BUS_HANDLER : trb_net16_regio_bus_handler
     generic map(
-      PORT_NUMBER    => 4,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"b000", 3 => x"b200", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 1,       1 => 6,       2 => 9,       3 => 9,       others => 0)
+      PORT_NUMBER    => 5,
+      PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"b000", 3 => x"b200", 4 => x"e100", others => x"0000"),
+      PORT_ADDR_MASK => (0 => 1,       1 => 6,       2 => 9,       3 => 9,       4 => 4,       others => 0)
       )
     port map(
       CLK   => clk_100_i,
@@ -610,55 +612,69 @@ THE_HUB : trb_net16_hub_base
       DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
 
       --Bus Handler (SPI CTRL)
+      --Bus Handler (SPI Memory)
+      --SCI first Media Interface
+      --SCI second Media Interface
+      --SODA
       BUS_READ_ENABLE_OUT(0)              => spictrl_read_en,
+      BUS_READ_ENABLE_OUT(1)              => spimem_read_en,
+      BUS_READ_ENABLE_OUT(2)              => sci1_read,
+      BUS_READ_ENABLE_OUT(3)              => sci2_read,
+      BUS_READ_ENABLE_OUT(4)              => soda_read_en,
       BUS_WRITE_ENABLE_OUT(0)             => spictrl_write_en,
+      BUS_WRITE_ENABLE_OUT(1)             => spimem_write_en,
+      BUS_WRITE_ENABLE_OUT(2)             => sci1_write,
+      BUS_WRITE_ENABLE_OUT(3)             => sci2_write,
+      BUS_WRITE_ENABLE_OUT(4)             => soda_write_en,
       BUS_DATA_OUT(0*32+31 downto 0*32)   => spictrl_data_in,
+      BUS_DATA_OUT(1*32+31 downto 1*32)   => spimem_data_in,
+      BUS_DATA_OUT(2*32+7 downto 2*32)    => sci1_data_in,
+      BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
+      BUS_DATA_OUT(3*32+7 downto 3*32)    => sci2_data_in,
+      BUS_DATA_OUT(3*32+31 downto 3*32+8) => open,
+      BUS_DATA_OUT(4*32+31 downto 4*32)   => soda_data_in,
       BUS_ADDR_OUT(0*16)                  => spictrl_addr,
       BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
-      BUS_TIMEOUT_OUT(0)                  => open,
-      BUS_DATA_IN(0*32+31 downto 0*32)    => spictrl_data_out,
-      BUS_DATAREADY_IN(0)                 => spictrl_ack,
-      BUS_WRITE_ACK_IN(0)                 => spictrl_ack,
-      BUS_NO_MORE_DATA_IN(0)              => spictrl_busy,
-      BUS_UNKNOWN_ADDR_IN(0)              => '0',
-      --Bus Handler (SPI Memory)
-      BUS_READ_ENABLE_OUT(1)              => spimem_read_en,
-      BUS_WRITE_ENABLE_OUT(1)             => spimem_write_en,
-      BUS_DATA_OUT(1*32+31 downto 1*32)   => spimem_data_in,
       BUS_ADDR_OUT(1*16+5 downto 1*16)    => spimem_addr,
       BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
-      BUS_TIMEOUT_OUT(1)                  => open,
-      BUS_DATA_IN(1*32+31 downto 1*32)    => spimem_data_out,
-      BUS_DATAREADY_IN(1)                 => spimem_ack,
-      BUS_WRITE_ACK_IN(1)                 => spimem_ack,
-      BUS_NO_MORE_DATA_IN(1)              => '0',
-      BUS_UNKNOWN_ADDR_IN(1)              => '0',
-      --SCI first Media Interface
-      BUS_READ_ENABLE_OUT(2)              => sci1_read,
-      BUS_WRITE_ENABLE_OUT(2)             => sci1_write,
-      BUS_DATA_OUT(2*32+7 downto 2*32)    => sci1_data_in,
-      BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
       BUS_ADDR_OUT(2*16+8 downto 2*16)    => sci1_addr,
       BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
-      BUS_TIMEOUT_OUT(2)                  => open,
-      BUS_DATA_IN(2*32+7 downto 2*32)     => sci1_data_out,
-      BUS_DATAREADY_IN(2)                 => sci1_ack,
-      BUS_WRITE_ACK_IN(2)                 => sci1_ack,
-      BUS_NO_MORE_DATA_IN(2)              => '0',
-      BUS_UNKNOWN_ADDR_IN(2)              => '0',
-      --SCI second Media Interface
-      BUS_READ_ENABLE_OUT(3)              => sci2_read,
-      BUS_WRITE_ENABLE_OUT(3)             => sci2_write,
-      BUS_DATA_OUT(3*32+7 downto 3*32)    => sci2_data_in,
-      BUS_DATA_OUT(3*32+31 downto 3*32+8) => open,
       BUS_ADDR_OUT(3*16+8 downto 3*16)    => sci2_addr,
       BUS_ADDR_OUT(3*16+15 downto 3*16+9) => open,
+      BUS_ADDR_OUT(4*16+3 downto 4*16)    => soda_addr,
+      BUS_ADDR_OUT(4*16+15 downto 4*16+4) => open,
+      BUS_TIMEOUT_OUT(0)                  => open,
+      BUS_TIMEOUT_OUT(1)                  => open,
+      BUS_TIMEOUT_OUT(2)                  => open,
       BUS_TIMEOUT_OUT(3)                  => open,
+      BUS_TIMEOUT_OUT(4)                  => open,
+      BUS_DATA_IN(0*32+31 downto 0*32)    => spictrl_data_out,
+      BUS_DATA_IN(1*32+31 downto 1*32)    => spimem_data_out,
+      BUS_DATA_IN(2*32+7 downto 2*32)     => sci1_data_out,
+      BUS_DATA_IN(2*32+31 downto 2*32+8)  => (others => '0'),
       BUS_DATA_IN(3*32+7 downto 3*32)     => sci2_data_out,
+      BUS_DATA_IN(3*32+31 downto 3*32+8)  => (others => '0'),
+      BUS_DATA_IN(4*32+31 downto 4*32)    => soda_data_out,
+      BUS_DATAREADY_IN(0)                 => spictrl_ack,
+      BUS_DATAREADY_IN(1)                 => spimem_ack,
+      BUS_DATAREADY_IN(2)                 => sci1_ack,
       BUS_DATAREADY_IN(3)                 => sci2_ack,
+      BUS_DATAREADY_IN(4)                 => soda_ack,
+      BUS_WRITE_ACK_IN(0)                 => spictrl_ack,
+      BUS_WRITE_ACK_IN(1)                 => spimem_ack,
+      BUS_WRITE_ACK_IN(2)                 => sci1_ack,
       BUS_WRITE_ACK_IN(3)                 => sci2_ack,
+      BUS_WRITE_ACK_IN(4)                 => soda_ack,
+      BUS_NO_MORE_DATA_IN(0)              => spictrl_busy,
+      BUS_NO_MORE_DATA_IN(1)              => '0',
+      BUS_NO_MORE_DATA_IN(2)              => '0',
       BUS_NO_MORE_DATA_IN(3)              => '0',
+      BUS_NO_MORE_DATA_IN(4)              => '0',
+      BUS_UNKNOWN_ADDR_IN(0)              => '0',
+      BUS_UNKNOWN_ADDR_IN(1)              => '0',
+      BUS_UNKNOWN_ADDR_IN(2)              => '0',
       BUS_UNKNOWN_ADDR_IN(3)              => '0',
+      BUS_UNKNOWN_ADDR_IN(4)              => '0',
       
       STAT_DEBUG => open
       );
@@ -714,6 +730,56 @@ THE_HUB : trb_net16_hub_base
       STAT          => open
       );
 
+	  
+---------------------------------------------------------------------------
+-- SODA
+--------------------------------------------------------------------------- 
+THE_SODA_HUB: soda_hub 
+	port map(
+		SYSCLK => clk_100_i,
+		SODACLK => rx_clock_200,
+		RESET => reset_i,
+		CLEAR => '0',
+		CLK_EN => '1',
+		
+	--	SINGLE DUBPLEX UP-LINK TO THE TOP
+		RXUP_DLM_IN => DLM_from_uplink_S,
+		RXUP_DLM_WORD_IN => DLM_WORD_from_uplink_S,
+		TXUP_DLM_OUT => DLM_to_uplink_S, 
+		TXUP_DLM_WORD_OUT => DLM_WORD_to_uplink_S,
+		TXUP_DLM_PREVIEW_OUT => open,
+		UPLINK_PHASE_IN => c_PHASE_H,
+
+	--	MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
+		RXDN_DLM_IN(0) => DLM_from_downlink_S(0),
+		RXDN_DLM_IN(1) => DLM_from_downlink_S(1),
+		RXDN_DLM_IN(2) => DLM_from_downlink_S(2),
+		RXDN_DLM_IN(3) => DLM_from_downlink_S(3),
+		RXDN_DLM_WORD_IN(0) => DLM_WORD_from_downlink_S(0*8+7 downto 0*8),
+		RXDN_DLM_WORD_IN(1) => DLM_WORD_from_downlink_S(1*8+7 downto 1*8),
+		RXDN_DLM_WORD_IN(2) => DLM_WORD_from_downlink_S(2*8+7 downto 2*8),
+		RXDN_DLM_WORD_IN(3) => DLM_WORD_from_downlink_S(3*8+7 downto 3*8),
+		TXDN_DLM_OUT(0) => DLM_to_downlink_S(0),
+		TXDN_DLM_OUT(1) => DLM_to_downlink_S(1),
+		TXDN_DLM_OUT(2) => DLM_to_downlink_S(2),
+		TXDN_DLM_OUT(3) => DLM_to_downlink_S(3),
+		TXDN_DLM_WORD_OUT(0) => DLM_WORD_to_downlink_S(0*8+7 downto 0*8),
+		TXDN_DLM_WORD_OUT(1) => DLM_WORD_to_downlink_S(1*8+7 downto 1*8),
+		TXDN_DLM_WORD_OUT(2) => DLM_WORD_to_downlink_S(2*8+7 downto 2*8),
+		TXDN_DLM_WORD_OUT(3) => DLM_WORD_to_downlink_S(3*8+7 downto 3*8),
+		TXDN_DLM_PREVIEW_OUT	=> open,
+		DNLINK_PHASE_IN => (others => c_PHASE_H),
+
+		SODA_DATA_IN => soda_data_in,
+		SODA_DATA_OUT => soda_data_out,
+		SODA_ADDR_IN => soda_addr,
+		SODA_READ_IN => soda_read_en,
+		SODA_WRITE_IN => soda_write_en,
+		SODA_ACK_OUT => soda_ack,
+		LEDS_OUT => open,
+		LINK_DEBUG_IN => (others => '0')
+	);
+
 ---------------------------------------------------------------------------
 -- Reboot FPGA
 ---------------------------------------------------------------------------
@@ -725,8 +791,6 @@ THE_HUB : trb_net16_hub_base
       PROGRAMN  => PROGRAMN
       );
 
-
-
 ---------------------------------------------------------------------------
 -- LED
 ---------------------------------------------------------------------------
@@ -734,7 +798,20 @@ THE_HUB : trb_net16_hub_base
   LED_ORANGE <= not med_stat_op(10);
   LED_RED    <= not time_counter(26);
   LED_YELLOW <= not med_stat_op(11);
-
+---------------------------------------------------------------------------
+-- Test Circuits
+---------------------------------------------------------------------------
+    blink : process (clk_100_i)
+    begin
+        if rising_edge(clk_100_i) then
+            if (time_counter = x"FFFFFFFF") then
+                time_counter <= x"00000000";
+            else
+                time_counter <= time_counter + 1;
+            end if;
+        end if;
+   end process;
+-- 
 
   gen_LED : for i in 1 to 6 generate
     LED_LINKOK(i) <= not med_stat_op(i*16+9);
diff --git a/trb3_soda_hub.xcf b/hub_SODA/trb3_periph_hub_SODA.xcf
similarity index 81%
rename from trb3_soda_hub.xcf
rename to hub_SODA/trb3_periph_hub_SODA.xcf
index f790783..6726c6c 100644
--- a/trb3_soda_hub.xcf
+++ b/hub_SODA/trb3_periph_hub_SODA.xcf
@@ -1,6 +1,6 @@
 <?xml version='1.0' encoding='utf-8' ?>
 <!DOCTYPE		ispXCF	SYSTEM	"IspXCF.dtd" >
-<ispXCF version="3.4.0">
+<ispXCF version="3.2.0">
 	<Comment></Comment>
 	<Chain>
 		<Comm>JTAG</Comm>
@@ -19,7 +19,8 @@
 				<BScanLen>1</BScanLen>
 				<BScanVal>0</BScanVal>
 			</Bypass>
-			<Operation>Fast Program</Operation>
+			<File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/soda/hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit</File>
+			<Operation>Bypass</Operation>
 			<Option>
 				<SVFVendor>JTAG STANDARD</SVFVendor>
 				<IOState>HighZ</IOState>
@@ -45,13 +46,13 @@
 				<BScanLen>1</BScanLen>
 				<BScanVal>0</BScanVal>
 			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20150317.bit</File>
-			<FileTime>03/17/15 15:09:57</FileTime>
+			<File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/soda/SODA_source/trb3_periph_SODA_source/trb3_periph_SODA_source_trb3_periph_SODA_source.bit</File>
+			<FileTime>07/24/15 09:45:34</FileTime>
+			<JedecChecksum>N/A</JedecChecksum>
 			<Operation>Fast Program</Operation>
 			<Option>
 				<SVFVendor>JTAG STANDARD</SVFVendor>
 				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
 				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
 				<OverideUES value="TRUE"/>
 				<TCKFrequency>1.000000 MHz</TCKFrequency>
@@ -61,7 +62,7 @@
 			</Option>
 		</Device>
 		<Device>
-			<SelectedProg value="FALSE"/>
+			<SelectedProg value="TRUE"/>
 			<Pos>3</Pos>
 			<Vendor>Lattice</Vendor>
 			<Family>LatticeECP3</Family>
@@ -75,19 +76,23 @@
 				<BScanLen>1</BScanLen>
 				<BScanVal>0</BScanVal>
 			</Bypass>
+			<File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/soda/hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit</File>
+			<FileTime>07/30/15 16:40:51</FileTime>
 			<Operation>Fast Program</Operation>
 			<Option>
 				<SVFVendor>JTAG STANDARD</SVFVendor>
 				<IOState>HighZ</IOState>
+				<PreloadLength>1326</PreloadLength>
 				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
 				<OverideUES value="TRUE"/>
 				<TCKFrequency>1.000000 MHz</TCKFrequency>
 				<SVFProcessor>ispVM</SVFProcessor>
+				<Usercode>0x00000000</Usercode>
 				<AccessMode>JTAG</AccessMode>
 			</Option>
 		</Device>
 		<Device>
-			<SelectedProg value="FALSE"/>
+			<SelectedProg value="TRUE"/>
 			<Pos>4</Pos>
 			<Vendor>Lattice</Vendor>
 			<Family>LatticeECP3</Family>
@@ -101,8 +106,8 @@
 				<BScanLen>1</BScanLen>
 				<BScanVal>0</BScanVal>
 			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20150317.bit</File>
-			<FileTime>03/17/15 13:31:23</FileTime>
+			<File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/soda/hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit</File>
+			<FileTime>07/30/15 16:40:51</FileTime>
 			<Operation>Fast Program</Operation>
 			<Option>
 				<SVFVendor>JTAG STANDARD</SVFVendor>
@@ -131,9 +136,8 @@
 				<BScanLen>1</BScanLen>
 				<BScanVal>0</BScanVal>
 			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20150318.bit</File>
-			<FileTime>03/18/15 13:53:16</FileTime>
-			<JedecChecksum>N/A</JedecChecksum>
+			<File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/soda/hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit</File>
+			<FileTime>07/30/15 16:40:51</FileTime>
 			<Operation>Fast Program</Operation>
 			<Option>
 				<SVFVendor>JTAG STANDARD</SVFVendor>
@@ -162,8 +166,8 @@
 				<BScanLen>1</BScanLen>
 				<BScanVal>0</BScanVal>
 			</Bypass>
-			<File>/local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed</File>
-			<FileTime>04/10/13 09:35:41</FileTime>
+			<File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/trb3/base/clockmanager/CM1_125twice.jed</File>
+			<FileTime>03/26/15 13:13:40</FileTime>
 			<JedecChecksum>0x1C57</JedecChecksum>
 			<Operation>Erase,Program,Verify</Operation>
 			<Option>
@@ -193,8 +197,8 @@
 				<BScanLen>1</BScanLen>
 				<BScanVal>0</BScanVal>
 			</Bypass>
-			<File>/local/lemmens/lattice/trb3/base/clockmanager/CM2.jed</File>
-			<FileTime>04/10/13 09:35:41</FileTime>
+			<File>D:/Project/Panda/G2009-010 P3 Data-collector board/TRB3/data_concentrator_SODA2/trb3/base/clockmanager/CM2.jed</File>
+			<FileTime>03/26/15 13:13:40</FileTime>
 			<JedecChecksum>0x18FB</JedecChecksum>
 			<Operation>Erase,Program,Verify</Operation>
 			<Option>
@@ -221,5 +225,10 @@
 	<CableOptions>
 		<CableName>USB</CableName>
 		<PortAdd>EzUSB-0</PortAdd>
+		<USBID>\\?\usb#vid_1134&amp;amp;pid_8001#7&amp;amp;2a838890&amp;amp;0&amp;amp;2#</USBID>
+		<JTAGPinSetting>
+			TRST	ABSENT;
+			ISPEN	ABSENT;
+		</JTAGPinSetting>
 	</CableOptions>
 </ispXCF>
diff --git a/soda_hub/serdes_4_sync_downstream.txt b/hub_SODA/trb3_periph_hub_SODA/serdes_sync_200_full.txt
similarity index 96%
rename from soda_hub/serdes_4_sync_downstream.txt
rename to hub_SODA/trb3_periph_hub_SODA/serdes_sync_200_full.txt
index 8e076a7..d303ba1 100644
--- a/soda_hub/serdes_4_sync_downstream.txt
+++ b/hub_SODA/trb3_periph_hub_SODA/serdes_sync_200_full.txt
@@ -48,10 +48,10 @@ CH0_RX_FIFO        "ENABLED"
 CH1_RX_FIFO        "ENABLED"
 CH2_RX_FIFO        "ENABLED"
 CH3_RX_FIFO        "ENABLED"
-CH0_TDRV      "0"
-CH1_TDRV      "0"
-CH2_TDRV      "0"
-CH3_TDRV      "0"
+CH0_TDRV      "1"
+CH1_TDRV      "1"
+CH2_TDRV      "1"
+CH3_TDRV      "1"
 #CH0_TX_FICLK_RATE      200
 #CH1_TX_FICLK_RATE      200
 #CH2_TX_FICLK_RATE      200
@@ -89,8 +89,8 @@ CH1_LOS_THRESHOLD_LO       "2"
 CH2_LOS_THRESHOLD_LO       "2"
 CH3_LOS_THRESHOLD_LO       "2"
 PLL_TERM                "50"
-PLL_DCC                 "DC"
-PLL_LOL_SET             "0"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "1"
 CH0_TX_SB               "DISABLED"
 CH1_TX_SB               "DISABLED"
 CH2_TX_SB               "DISABLED"
@@ -158,6 +158,6 @@ CH1_PCSLBPORTS          "DISABLED"
 CH2_PCSLBPORTS          "DISABLED"
 CH3_PCSLBPORTS          "DISABLED"
 INT_ALL                 "DISABLED"
-QD_REFCK2CORE           "ENABLED"
+QD_REFCK2CORE           "DISABLED"
 
 
diff --git a/hub_SODA/trb3_periph_hub_SODA/sfp_3sync_200_int.txt b/hub_SODA/trb3_periph_hub_SODA/sfp_3sync_200_int.txt
new file mode 100644
index 0000000..c9fed33
--- /dev/null
+++ b/hub_SODA/trb3_periph_hub_SODA/sfp_3sync_200_int.txt
@@ -0,0 +1,58 @@
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSD quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSD quad to the final design requirements.
+
+DEVICE_NAME "LFE3-150EA"
+CH2_PROTOCOL            "G8B10B"
+CH0_MODE                "DISABLED"
+CH1_MODE                "DISABLED"
+CH2_MODE                "RXTX"
+CH3_MODE                "DISABLED"
+CH2_CDR_SRC       "REFCLK_CORE"
+PLL_SRC                 "REFCLK_CORE"
+TX_DATARATE_RANGE       "MEDHIGH"
+CH2_RX_DATARATE_RANGE   "MEDHIGH"
+REFCK_MULT              "10X"
+#REFCLK_RATE            200
+CH2_RX_DATA_RATE        "FULL"
+CH2_TX_DATA_RATE        "FULL"
+CH2_TX_DATA_WIDTH       "8"
+CH2_RX_DATA_WIDTH        "8"
+CH2_TX_FIFO       "DISABLED"
+CH2_RX_FIFO        "ENABLED"
+CH2_TDRV      "0"
+#CH2_TX_FICLK_RATE      200
+#CH2_RXREFCLK_RATE        "200"
+#CH2_RX_FICLK_RATE      200
+CH2_TX_PRE              "DISABLED"
+CH2_RTERM_TX            "50"
+CH2_RX_EQ               "DISABLED"
+CH2_RTERM_RX            "50"
+CH2_RX_DCC              "DC"
+CH2_LOS_THRESHOLD_LO       "2"
+PLL_TERM                "50"
+PLL_DCC                 "AC"
+PLL_LOL_SET             "0"
+CH2_TX_SB               "DISABLED"
+CH2_RX_SB               "DISABLED"
+CH2_TX_8B10B            "ENABLED"
+CH2_RX_8B10B            "ENABLED"
+CH2_COMMA_A             "1100000101"
+CH2_COMMA_B             "0011111010"
+CH2_COMMA_M             "1111111100"
+CH2_RXWA                "ENABLED"
+CH2_ILSM                "ENABLED"
+CH2_CTC                 "DISABLED"
+CH2_CC_MATCH4           "0000000000"
+CH2_CC_MATCH_MODE       "1"
+CH2_CC_MIN_IPG          "3"
+CCHMARK                 "9"
+CCLMARK                 "7"
+CH2_SSLB                "DISABLED"
+CH2_SPLBPORTS           "DISABLED"
+CH2_PCSLBPORTS          "DISABLED"
+INT_ALL                 "DISABLED"
+QD_REFCK2CORE           "DISABLED"
+
+
diff --git a/ctsc_20141217.bit b/hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit
similarity index 60%
rename from ctsc_20141217.bit
rename to hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit
index 36f43d6..9497383 100644
Binary files a/ctsc_20141217.bit and b/hub_SODA/trb3_periph_hub_SODA/trb3_periph_hub_SODA_trb3_periph_hub_SODA.bit differ
diff --git a/linkdesignfiles.sh b/linkdesignfiles.sh
deleted file mode 120000
index 0edd456..0000000
--- a/linkdesignfiles.sh
+++ /dev/null
@@ -1 +0,0 @@
-../trb3/base/linkdesignfiles.sh
\ No newline at end of file
diff --git a/soda4srcEP.ldf b/soda4srcEP.ldf
deleted file mode 100644
index d98efa6..0000000
--- a/soda4srcEP.ldf
+++ /dev/null
@@ -1,278 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="soda4srcEP" device="LFE3-150EA-8FN672C" default_implementation="soda4srcEP">
-    <Options/>
-    <Implementation title="soda4srcEP" dir="soda4srcEP" description="soda4srcEP" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="trb3_periph_ep_soda4source" top="trb3_periph_EP_soda4source"/>
-        <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_4source.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_start_of_burst_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_1_125_int.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_1_125_int.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_1_200_int.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="code/ip/sfp_1_200_int.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_4_sync_downstream.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_4_sync_downstream.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_4_sync_downstream.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="code/med_ecp3_sfp_4_SODA.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/cores/pll_in200_out100.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/cores/pll_in200_out100.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/trb3_periph_EP_soda4source.vhd" type="VHDL" type_short="VHDL">
-            <Options top_module="trb3_periph_EP_soda4source"/>
-        </Source>
-        <Source name="soda4srcEP.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>
-        </Source>
-        <Source name="soda4srcEP.rvl" type="Reveal" type_short="Reveal">
-            <Options/>
-        </Source>
-    </Implementation>
-    <Strategy name="Strategy1" file="soda4srcEP1.sty"/>
-</BaliProject>
diff --git a/soda4srcEP.lpf b/soda4srcEP.lpf
deleted file mode 100644
index 1246f20..0000000
--- a/soda4srcEP.lpf
+++ /dev/null
@@ -1,167 +0,0 @@
-rvl_alias "clk_200_osc" "clk_200_osc";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-BLOCK JTAGPATHS ;
-
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0   #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1   #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2   #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3   #7
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C  #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6   #17
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8   #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9   #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0   #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1   #27
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5   #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0   #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1   #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2   #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3   #8
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6   #18
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8   #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9   #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0   #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1   #28
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5   #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T  #38
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0   #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1   #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2   #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3   #175
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C  #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6   #185
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0   #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1   #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2   #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3   #176
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C  #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6   #186
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-# TEST LINES
-#################################################################
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "MED_ECP3_SODA_QUAD_SOURCE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-#MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 25.000000 ns ;
-MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 25.000000 ns ;
-MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_0" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_1" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_2" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_full_clk_3" 200.000000 MHz ;
-
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_0" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_1" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_2" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/rx_half_clk_3" 100.000000 MHz ;
-
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_0" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_1" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_2" 200.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_full_clk_3" 200.000000 MHz ;
-
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_0" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_1" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_2" 100.000000 MHz ;
-FREQUENCY NET "MED_ECP3_SODA_QUAD_SOURCE/tx_half_clk_3" 100.000000 MHz ;
-
-MULTICYCLE TO CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
diff --git a/soda_4source_EP.lpf b/soda_4source_EP.lpf
deleted file mode 100644
index 11365cc..0000000
--- a/soda_4source_EP.lpf
+++ /dev/null
@@ -1,197 +0,0 @@
-rvl_alias "clk_200_osc" "clk_200_osc";
-RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; 
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-#   SYSCONFIG MCCLK_FREQ = 2.5;
-#  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-#  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-#  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP  "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP  "PCSA_REFCLKN" SITE "AC18";
-#LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AC10";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0   #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1   #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2   #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3   #7
-#LOCATE COMP  "SFP_MOD1_1"    SITE "R1";     #DQLL0_4   #9
-#LOCATE COMP  "SFP_MOD2_1"    SITE "R2";     #DQLL0_5   #11
-#LOCATE COMP  "SFP_RATESEL_1" SITE "N3";     #DQSLL0_T  #13
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C  #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6   #17
-#LOCATE COMP  "SFP_TXFAULT_1" SITE "P6";     #DQLL0_7   #19
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8   #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9   #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0   #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1   #27
-#LOCATE COMP  "SFP_MOD1_2"    SITE "AB1";    #DQLL2_2   #29
-#LOCATE COMP  "SFP_MOD2_2"    SITE "AC1";    #DQLL2_3   #31
-#LOCATE COMP  "SFP_RATESEL_2" SITE "AA1";    #DQLL2_4   #33
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5   #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
-#LOCATE COMP  "SFP_TXFAULT_2" SITE "W6";     #DQLL2_C   #39  #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0   #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1   #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2   #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3   #8
-#LOCATE COMP  "SFP_MOD1_3"      SITE "AB3";    #DQLL3_4   #10
-#LOCATE COMP  "SFP_MOD2_3"      SITE "AB4";    #DQLL3_5   #12
-#LOCATE COMP  "SFP_RATESEL_3"   SITE "Y6";     #DQLL3_T   #14  #should be DQSLL3
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6   #18
-#LOCATE COMP  "SFP_TXFAULT_3"   SITE "AA4";    #DQLL3_7   #20
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8   #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9   #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0   #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1   #28
-#LOCATE COMP  "SFP_MOD1_4"      SITE "T1";     #DQLL1_2   #30
-#LOCATE COMP  "SFP_MOD2_4"      SITE "U1";     #DQLL1_3   #32
-#LOCATE COMP  "SFP_RATESEL_4"   SITE "P4";     #DQLL1_4   #34
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5   #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T  #38
-#LOCATE COMP  "SFP_TXFAULT_4"   SITE "R4";     #DQSLL1_C  #40
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0   #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1   #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2   #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3   #175
-#LOCATE COMP  "SFP_MOD1_5"     SITE "AA26";   #DQLR1_4   #177
-#LOCATE COMP  "SFP_MOD2_5"     SITE "AB26";   #DQLR1_5   #179
-#LOCATE COMP  "SFP_RATESEL_5"  SITE "W21";    #DQSLR1_T  #181
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C  #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6   #185
-#LOCATE COMP  "SFP_TXFAULT_5"  SITE "AA23";   #DQLR1_7   #187
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0   #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1   #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2   #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3   #176
-#LOCATE COMP  "SFP_MOD1_6"     SITE "T26";    #DQLR2_4   #178
-#LOCATE COMP  "SFP_MOD2_6"     SITE "U26";    #DQLR2_5   #180
-#LOCATE COMP  "SFP_RATESEL_6"  SITE "V21";    #DQSLR2_T  #182
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C  #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6   #186
-#LOCATE COMP  "SFP_TXFAULT_6"  SITE "V24";    #DQLR2_7   #188
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
-#LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
-#LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
-#LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
-#LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-#GSR_NET NET "GSR_N";  
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "MED_ECP3_SODA_QUAD_SOURCE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/sci*" 25.000000 ns ;
-MULTICYCLE TO CELL "MED_ECP3_SODA_QUAD_SOURCE/SCI_DATA_OUT*" 50.000000 ns ;
-MULTICYCLE FROM CELL "MED_ECP3_SODA_QUAD_SOURCE/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-
-BLOCK JTAGPATHS ;
-
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-
diff --git a/soda_addressmap.txt b/soda_addressmap.txt
deleted file mode 100644
index 8b86a1a..0000000
--- a/soda_addressmap.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-SODA_SOURCE (0xF355)
-
-WRITE_REG:
-
-BE00			soda_cmd_word_S
-BE01			LEDregister_i
-
-READ_REG:
-
-BE00			soda_cmd_word_S
-BE01			super_burst_nr_S
-BE02			calib_register_S
-BE03			LEDregister_i
-
-
-SODA_CLIENT	(0xF356)
-
-WRITE_REG:
-
-BE00			LEDregister_i
-
-READ_REG:
-
-BE00			soda_cmd_word_S
-BE01			super_burst_nr_S
-BE02			LEDregister_i
-BE03			Debug_status
-BE04			Debug_RX_count
-BE05			Debug_TX_count
-BE06			Debug_SOS_count
-BE07			Debug_CMD_count
-
-
-
-
-DEBUG_STATUS(31)		<= send_link_reset_i when rising_edge(SYSCLK);
-DEBUG_STATUS(30)		<= '0';
-DEBUG_STATUS(29)		<= internal_make_link_reset_out when rising_edge(SYSCLK);
-DEBUG_STATUS(28)		<= '0';
-DEBUG_STATUS(27)		<= '0';
-DEBUG_STATUS(26)		<= rx_allow;
-DEBUG_STATUS(25)		<= tx_allow;
-DEBUG_STATUS(24:20)	<= (others => '0');
-DEBUG_STATUS(19:16)	<= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
-DEBUG_STATUS(15:3)		<= (others => '0');
-DEBUG_STATUS(2)			<= CLK_EN;
-DEBUG_STATUS(1)			<= CLEAR;
-DEBUG_STATUS(0)			<= RESET;
-
------------------------------------------------------------------------------------
-constant K_IDLE   : std_logic_vector(7 downto 0) := x"BC";
-constant D_IDLE0  : std_logic_vector(7 downto 0) := x"C5";
-constant D_IDLE1  : std_logic_vector(7 downto 0) := x"50";
-constant K_SOP    : std_logic_vector(7 downto 0) := x"FB";
-constant K_EOP    : std_logic_vector(7 downto 0) := x"FD";
-constant K_BGN    : std_logic_vector(7 downto 0) := x"1C";
-constant K_REQ    : std_logic_vector(7 downto 0) := x"7C";
-constant K_RST    : std_logic_vector(7 downto 0) := x"FE";
-constant K_DLM    : std_logic_vector(7 downto 0) := x"DC";
-
-
diff --git a/soda_client.ldf b/soda_client.ldf
deleted file mode 100644
index 554b219..0000000
--- a/soda_client.ldf
+++ /dev/null
@@ -1,325 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="soda_client" device="LFE3-150EA-8FN672C" default_implementation="soda_client">
-    <Options>
-        <Option name="HDL type" value="VHDL"/>
-    </Options>
-    <Implementation title="soda_client" dir="soda_client" description="soda_client" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="trb3_periph_sodaclient" top="trb3_periph_sodaclient"/>
-        <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_client.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/med_ecp3_sfp_sync_up.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_sync_upstream.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_sync_upstream.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_sync_upstream.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
-            <Options top_module="trb3_periph_sodaclient"/>
-        </Source>
-        <Source name="code/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="soda_client.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>
-        </Source>
-        <Source name="soda_client_probe.rvl" type="Reveal" type_short="Reveal">
-            <Options/>
-        </Source>
-    </Implementation>
-    <Strategy name="Strategy1" file="soda_client1.sty"/>
-</BaliProject>
diff --git a/soda_client.ldf~ b/soda_client.ldf~
deleted file mode 100644
index bc86f25..0000000
--- a/soda_client.ldf~
+++ /dev/null
@@ -1,316 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="2.0" title="soda_client" device="LFE3-150EA-8FN672C" synthesis="synplify" default_implementation="soda_client">
-    <Options>
-        <Option name="HDL type" value="VHDL"/>
-    </Options>
-    <Implementation title="soda_client" dir="soda_client" description="soda_client" default_strategy="Strategy1">
-        <Options def_top="trb3_periph_sodasource" top="trb3_periph_sodaclient"/>
-        <Source name="source/version.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_client.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/tx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="source/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
-            <Options top_module="trb3_periph_sodasource"/>
-        </Source>
-        <Source name="soda_client.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>
-        </Source>
-    </Implementation>
-    <Strategy name="Strategy1" file="soda_client1.sty"/>
-</BaliProject>
diff --git a/soda_client.lpf b/soda_client.lpf
deleted file mode 100644
index 05dff1a..0000000
--- a/soda_client.lpf
+++ /dev/null
@@ -1,165 +0,0 @@
-rvl_alias "rx_full_clk" "rx_full_clk";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-BLOCK JTAGPATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-SYSCONFIG MCCLK_FREQ = 20;
-#  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-#  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-#  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP  "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-#LOCATE COMP  "FPGA5_COMM_0"   SITE "AD4";
-#LOCATE COMP  "FPGA5_COMM_1"   SITE "AE3";
-#LOCATE COMP  "FPGA5_COMM_2"   SITE "AA7";
-#LOCATE COMP  "FPGA5_COMM_3"   SITE "AB7";
-#LOCATE COMP  "FPGA5_COMM_4"   SITE "AD3";
-#LOCATE COMP  "FPGA5_COMM_5"   SITE "AC4";
-#LOCATE COMP  "FPGA5_COMM_6"   SITE "AE2";
-#LOCATE COMP  "FPGA5_COMM_7"   SITE "AF3";
-#LOCATE COMP  "FPGA5_COMM_8"   SITE "AE4";
-#LOCATE COMP  "FPGA5_COMM_9"   SITE "AF4";
-#LOCATE COMP  "FPGA5_COMM_10"  SITE "V10";
-#LOCATE COMP  "FPGA5_COMM_11"  SITE "W10";
-#DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-#IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0   #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1   #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2   #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3   #7
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C  #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6   #17
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8   #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9   #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0   #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1   #27
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5   #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0   #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1   #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2   #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3   #8
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6   #18
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8   #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9   #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0   #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1   #28
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5   #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T  #38
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0   #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1   #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2   #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3   #175
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C  #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6   #185
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0   #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1   #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2   #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3   #176
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C  #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6   #186
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
-#LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
-#LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
-#LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
-#LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF  PORT "SUPPL" IO_TYPE=LVDS25;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-#LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-FREQUENCY NET "rx_full_clk" 200.000000 MHz ;
-FREQUENCY NET "rx_half_clk" 100.000000 MHz ;
diff --git a/soda_client/serdes_sync_upstream.txt b/soda_client/serdes_sync_upstream.txt
deleted file mode 100644
index 9f2bf0d..0000000
--- a/soda_client/serdes_sync_upstream.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH3_PROTOCOL            "G8B10B"
-CH0_MODE                "DISABLED"
-CH1_MODE                "DISABLED"
-CH2_MODE                "DISABLED"
-CH3_MODE                "RXTX"
-CH3_CDR_SRC       "REFCLK_CORE"
-PLL_SRC                 "REFCLK_CORE"
-TX_DATARATE_RANGE       "MEDHIGH"
-CH3_RX_DATARATE_RANGE   "MEDHIGH"
-REFCK_MULT              "10X"
-#REFCLK_RATE            200
-CH3_RX_DATA_RATE        "FULL"
-CH3_TX_DATA_RATE        "FULL"
-CH3_TX_DATA_WIDTH       "8"
-CH3_RX_DATA_WIDTH        "8"
-CH3_TX_FIFO       "DISABLED"
-CH3_RX_FIFO        "DISABLED"
-CH3_TDRV      "0"
-#CH3_TX_FICLK_RATE      200
-#CH3_RXREFCLK_RATE        "200"
-#CH3_RX_FICLK_RATE      200
-CH3_TX_PRE              "DISABLED"
-CH3_RTERM_TX            "50"
-CH3_RX_EQ               "DISABLED"
-CH3_RTERM_RX            "50"
-CH3_RX_DCC              "DC"
-CH3_LOS_THRESHOLD_LO       "2"
-PLL_TERM                "50"
-PLL_DCC                 "AC"
-PLL_LOL_SET             "0"
-CH3_TX_SB               "DISABLED"
-CH3_RX_SB               "DISABLED"
-CH3_TX_8B10B            "ENABLED"
-CH3_RX_8B10B            "ENABLED"
-CH3_COMMA_A             "1100000101"
-CH3_COMMA_B             "0011111010"
-CH3_COMMA_M             "1111111100"
-CH3_RXWA                "ENABLED"
-CH3_ILSM                "ENABLED"
-CH3_CTC                 "DISABLED"
-CH3_CC_MATCH4           "0000000000"
-CH3_CC_MATCH_MODE       "1"
-CH3_CC_MIN_IPG          "3"
-CCHMARK                 "9"
-CCLMARK                 "7"
-CH3_SSLB                "DISABLED"
-CH3_SPLBPORTS           "DISABLED"
-CH3_PCSLBPORTS          "DISABLED"
-INT_ALL                 "DISABLED"
-QD_REFCK2CORE           "ENABLED"
-
-
diff --git a/soda_client_probe.rvl b/soda_client_probe.rvl
deleted file mode 100644
index 678f7a0..0000000
--- a/soda_client_probe.rvl
+++ /dev/null
@@ -1,168 +0,0 @@
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2015-01-08">
-    <IP Version="1_5_062609"/>
-    <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_client"/>
-    <Core InsertDataset="0" Insert="1" Reveal_sig="2085654093" Name="trb3_periph_sodaclient_LA0" ID="0">
-        <Setting>
-            <Clock SampleClk="rx_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
-            <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
-            <Capture Mode="0" MinSamplesPerTrig="8"/>
-            <Event CntEnable="0" MaxEventCnt="8"/>
-            <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_client_LA0_net"/>
-        </Setting>
-        <Dataset Name="Base">
-            <Trace>
-                <Sig Type="SIG" Name="the_sync_link/got_link_ready_i"/>
-                <Sig Type="SIG" Name="the_sync_link/link_phase_out"/>
-                <Bus Name="the_sync_link/rx_data">
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_sync_link/rx_k"/>
-                <Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
-                <Bus Name="the_sync_link/rx_dlm_word">
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
-                </Bus>
-                <Bus Name="the_sync_link/tx_data">
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_sync_link/tx_k"/>
-                <Sig Type="SIG" Name="the_sync_link/tx_dlm"/>
-                <Sig Type="SIG" Name="the_sync_link/tx_dlm_preview_in"/>
-                <Bus Name="the_sync_link/tx_dlm_word">
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_sync_link/rx_allow_q"/>
-                <Bus Name="sfp_los">
-                    <Sig Type="SIG" Name="sfp_los:1"/>
-                    <Sig Type="SIG" Name="sfp_los:2"/>
-                    <Sig Type="SIG" Name="sfp_los:3"/>
-                    <Sig Type="SIG" Name="sfp_los:4"/>
-                    <Sig Type="SIG" Name="sfp_los:5"/>
-                    <Sig Type="SIG" Name="sfp_los:6"/>
-                </Bus>
-                <Bus Name="the_sync_link/wa_position_rx">
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:7"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:8"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:9"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:10"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:11"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:12"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:13"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:14"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:15"/>
-                </Bus>
-                <Sig Type="SIG" Name="clk_100_osc"/>
-                <Sig Type="SIG" Name="rx_half_clk"/>
-                <Bus Name="the_sync_link/sci_state">
-                    <Sig Type="SIG" Name="the_sync_link/sci_state:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_state:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_state:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_state:3"/>
-                </Bus>
-                <Bus Name="the_sync_link/wa_position">
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:7"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:8"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:9"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:10"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:11"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:12"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:13"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:14"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:15"/>
-                </Bus>
-                <Bus Name="the_sync_link/sci_addr_i">
-                    <Sig Type="SIG" Name="the_sync_link/sci_addr_i:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_addr_i:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_addr_i:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_addr_i:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_addr_i:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_addr_i:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_addr_i:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_addr_i:7"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_addr_i:8"/>
-                </Bus>
-                <Bus Name="the_sync_link/sci_data_in_i">
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_in_i:7"/>
-                </Bus>
-                <Bus Name="the_sync_link/sci_data_out_i">
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_data_out_i:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_sync_link/sci_read_i"/>
-                <Sig Type="SIG" Name="the_sync_link/sci_write_i"/>
-                <Bus Name="the_sync_link/sci_ch_i">
-                    <Sig Type="SIG" Name="the_sync_link/sci_ch_i:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_ch_i:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_ch_i:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/sci_ch_i:3"/>
-                </Bus>
-            </Trace>
-            <Trigger>
-                <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_client/start_of_superburst_s,"/>
-                <TU Serialbits="0" Type="0" ID="2" Sig="a_soda_client/soda_cmd_valid_s,"/>
-                <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/watchdog_trigger,"/>
-                <TU Serialbits="0" Type="0" ID="4" Sig="general_reset_i,"/>
-                <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)the_sync_link/sci_state[3:0],"/>
-                <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
-                <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
-                <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
-                <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
-                <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
-            </Trigger>
-        </Dataset>
-    </Core>
-</Project>
diff --git a/soda_hub.ldf b/soda_hub.ldf
deleted file mode 100644
index e773792..0000000
--- a/soda_hub.ldf
+++ /dev/null
@@ -1,353 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="soda_hub" device="LFE3-150EA-8FN672C" default_implementation="soda_hub">
-    <Options>
-        <Option name="HDL type" value="VHDL"/>
-    </Options>
-    <Implementation title="soda_hub" dir="soda_hub" description="soda_hub" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="trb3_periph_sodahub" run_flow="NORMAL" top="trb3_periph_sodahub"/>
-        <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_hub.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_pkt_builder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/med_ecp3_sfp_sync_up.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/med_ecp3_sfp_4_sync_down.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_cmd_window_generator.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_sync_upstream.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_sync_upstream.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_sync_upstream.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_4_sync_downstream.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_4_sync_downstream.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_4_sync_downstream.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/wide_adder_17x16.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_ipu_logic.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/trb3_periph_sodahub.vhd" type="VHDL" type_short="VHDL">
-            <Options top_module="trb3_periph_sodahub"/>
-        </Source>
-        <Source name="code/soda_hub_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="soda_hub.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>
-        </Source>
-        <Source name="soda_hub_probe.rvl" type="Reveal" type_short="Reveal">
-            <Options/>
-        </Source>
-        <Source name="trb3_soda_hub.xcf" type="Programming Project File" type_short="Programming">
-            <Options/>
-        </Source>
-    </Implementation>
-    <Strategy name="Strategy1" file="soda_hub1.sty"/>
-    <Strategy name="soda_hub" file="soda_hub.sty"/>
-</BaliProject>
diff --git a/soda_hub.lpf b/soda_hub.lpf
deleted file mode 120000
index 35b4571..0000000
--- a/soda_hub.lpf
+++ /dev/null
@@ -1 +0,0 @@
-soda_hub_groningen.lpf
\ No newline at end of file
diff --git a/soda_hub/serdes_sync_upstream.txt b/soda_hub/serdes_sync_upstream.txt
deleted file mode 100644
index 9f2bf0d..0000000
--- a/soda_hub/serdes_sync_upstream.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH3_PROTOCOL            "G8B10B"
-CH0_MODE                "DISABLED"
-CH1_MODE                "DISABLED"
-CH2_MODE                "DISABLED"
-CH3_MODE                "RXTX"
-CH3_CDR_SRC       "REFCLK_CORE"
-PLL_SRC                 "REFCLK_CORE"
-TX_DATARATE_RANGE       "MEDHIGH"
-CH3_RX_DATARATE_RANGE   "MEDHIGH"
-REFCK_MULT              "10X"
-#REFCLK_RATE            200
-CH3_RX_DATA_RATE        "FULL"
-CH3_TX_DATA_RATE        "FULL"
-CH3_TX_DATA_WIDTH       "8"
-CH3_RX_DATA_WIDTH        "8"
-CH3_TX_FIFO       "DISABLED"
-CH3_RX_FIFO        "DISABLED"
-CH3_TDRV      "0"
-#CH3_TX_FICLK_RATE      200
-#CH3_RXREFCLK_RATE        "200"
-#CH3_RX_FICLK_RATE      200
-CH3_TX_PRE              "DISABLED"
-CH3_RTERM_TX            "50"
-CH3_RX_EQ               "DISABLED"
-CH3_RTERM_RX            "50"
-CH3_RX_DCC              "DC"
-CH3_LOS_THRESHOLD_LO       "2"
-PLL_TERM                "50"
-PLL_DCC                 "AC"
-PLL_LOL_SET             "0"
-CH3_TX_SB               "DISABLED"
-CH3_RX_SB               "DISABLED"
-CH3_TX_8B10B            "ENABLED"
-CH3_RX_8B10B            "ENABLED"
-CH3_COMMA_A             "1100000101"
-CH3_COMMA_B             "0011111010"
-CH3_COMMA_M             "1111111100"
-CH3_RXWA                "ENABLED"
-CH3_ILSM                "ENABLED"
-CH3_CTC                 "DISABLED"
-CH3_CC_MATCH4           "0000000000"
-CH3_CC_MATCH_MODE       "1"
-CH3_CC_MIN_IPG          "3"
-CCHMARK                 "9"
-CCLMARK                 "7"
-CH3_SSLB                "DISABLED"
-CH3_SPLBPORTS           "DISABLED"
-CH3_PCSLBPORTS          "DISABLED"
-INT_ALL                 "DISABLED"
-QD_REFCK2CORE           "ENABLED"
-
-
diff --git a/soda_hub_frankfurt.lpf b/soda_hub_frankfurt.lpf
deleted file mode 100644
index 6f8c310..0000000
--- a/soda_hub_frankfurt.lpf
+++ /dev/null
@@ -1,222 +0,0 @@
-rvl_alias "rxup_full_clk" "rxup_full_clk";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-BLOCK JTAGPATHS ;
-
-#################################################################
-# Basic Settings
-#################################################################
-SYSCONFIG MCCLK_FREQ = 20;
-#  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-#  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-#  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP  "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP  "PCSA_REFCLKN" SITE "AC18";
-#LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AC10";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM_10" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM_11" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-
-LOCATE COMP "TEST_LINE_0" SITE "A5" ;
-LOCATE COMP "TEST_LINE_1" SITE "A6" ;
-LOCATE COMP "TEST_LINE_2" SITE "G8" ;
-LOCATE COMP "TEST_LINE_3" SITE "F9" ;
-LOCATE COMP "TEST_LINE_4" SITE "D9" ;
-LOCATE COMP "TEST_LINE_5" SITE "D10" ;
-LOCATE COMP "TEST_LINE_6" SITE "F10" ;
-LOCATE COMP "TEST_LINE_7" SITE "E10" ;
-LOCATE COMP "TEST_LINE_8" SITE "A8" ;
-LOCATE COMP "TEST_LINE_9" SITE "B8" ;
-LOCATE COMP "TEST_LINE_10" SITE "G10" ;
-LOCATE COMP "TEST_LINE_11" SITE "G9" ;
-LOCATE COMP "TEST_LINE_12" SITE "C9" ;
-LOCATE COMP "TEST_LINE_13" SITE "C10" ;
-LOCATE COMP "TEST_LINE_14" SITE "H10" ;
-LOCATE COMP "TEST_LINE_15" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0   #1
-LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1   #3
-LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2   #5
-LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3   #7
-#LOCATE COMP  "SFP_MOD1_1"    SITE "R1";     #DQLL0_4   #9
-#LOCATE COMP  "SFP_MOD2_1"    SITE "R2";     #DQLL0_5   #11
-#LOCATE COMP  "SFP_RATESEL_1" SITE "N3";     #DQSLL0_T  #13
-LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C  #15
-LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6   #17
-#LOCATE COMP  "SFP_TXFAULT_1" SITE "P6";     #DQLL0_7   #19
-LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8   #21
-LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9   #23
-LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0   #25
-LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1   #27
-#LOCATE COMP  "SFP_MOD1_2"    SITE "AB1";    #DQLL2_2   #29
-#LOCATE COMP  "SFP_MOD2_2"    SITE "AC1";    #DQLL2_3   #31
-#LOCATE COMP  "SFP_RATESEL_2" SITE "AA1";    #DQLL2_4   #33
-LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5   #35
-LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
-#LOCATE COMP  "SFP_TXFAULT_2" SITE "W6";     #DQLL2_C   #39  #should be DQSLL2
-LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0   #2
-LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1   #4
-LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2   #6
-LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3   #8
-#LOCATE COMP  "SFP_MOD1_3"      SITE "AB3";    #DQLL3_4   #10
-#LOCATE COMP  "SFP_MOD2_3"      SITE "AB4";    #DQLL3_5   #12
-#LOCATE COMP  "SFP_RATESEL_3"   SITE "Y6";     #DQLL3_T   #14  #should be DQSLL3
-LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6   #18
-#LOCATE COMP  "SFP_TXFAULT_3"   SITE "AA4";    #DQLL3_7   #20
-LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8   #22
-LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9   #24
-LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0   #26
-LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1   #28
-#LOCATE COMP  "SFP_MOD1_4"      SITE "T1";     #DQLL1_2   #30
-#LOCATE COMP  "SFP_MOD2_4"      SITE "U1";     #DQLL1_3   #32
-#LOCATE COMP  "SFP_RATESEL_4"   SITE "P4";     #DQLL1_4   #34
-LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5   #36
-LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T  #38
-#LOCATE COMP  "SFP_TXFAULT_4"   SITE "R4";     #DQSLL1_C  #40
-LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0   #169
-LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1   #171
-LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2   #173
-LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3   #175
-#LOCATE COMP  "SFP_MOD1_5"     SITE "AA26";   #DQLR1_4   #177
-#LOCATE COMP  "SFP_MOD2_5"     SITE "AB26";   #DQLR1_5   #179
-#LOCATE COMP  "SFP_RATESEL_5"  SITE "W21";    #DQSLR1_T  #181
-LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C  #183
-LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6   #185
-#LOCATE COMP  "SFP_TXFAULT_5"  SITE "AA23";   #DQLR1_7   #187
-LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0   #170
-LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1   #172
-LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2   #174
-LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3   #176
-#LOCATE COMP  "SFP_MOD1_6"     SITE "T26";    #DQLR2_4   #178
-#LOCATE COMP  "SFP_MOD2_6"     SITE "U26";    #DQLR2_5   #180
-#LOCATE COMP  "SFP_RATESEL_6"  SITE "V21";    #DQSLR2_T  #182
-LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C  #184
-LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6   #186
-#LOCATE COMP  "SFP_TXFAULT_6"  SITE "V24";    #DQLR2_7   #188
-
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
-#LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
-#LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
-#LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
-#LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE_1" SITE "AA20" ;
-LOCATE COMP "CODE_LINE_0" SITE "Y21" ;
-IOBUF PORT  "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT  "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF  PORT "SUPPL" IO_TYPE=LVDS25;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-#GSR_NET NET "GSR_N";  
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
-#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ;	# to debug only
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
-#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ;	# to debug only
-#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;
-
-BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ;
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*";
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*";
-
-#UGROUP "SPIlogic" BBOX 20 20
-#       BLKNAME THE_SPI_RELOAD;
-#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ;
-
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_0";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_1";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_2";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_3";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_0";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_1";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_2";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_3";
-
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-USE PRIMARY NET "rxup_full_clk" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-FREQUENCY NET "rxup_full_clk" 200.000000 MHz ;
diff --git a/soda_hub_groningen.lpf b/soda_hub_groningen.lpf
deleted file mode 100644
index 4147b84..0000000
--- a/soda_hub_groningen.lpf
+++ /dev/null
@@ -1,211 +0,0 @@
-rvl_alias "rxup_full_clk" "rxup_full_clk";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-BLOCK JTAGPATHS ;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP  "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP  "PCSA_REFCLKN" SITE "AC18";
-#LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AC10";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM_10" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM_11" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-
-LOCATE COMP "TEST_LINE_0" SITE "A5" ;
-LOCATE COMP "TEST_LINE_1" SITE "A6" ;
-LOCATE COMP "TEST_LINE_2" SITE "G8" ;
-LOCATE COMP "TEST_LINE_3" SITE "F9" ;
-LOCATE COMP "TEST_LINE_4" SITE "D9" ;
-LOCATE COMP "TEST_LINE_5" SITE "D10" ;
-LOCATE COMP "TEST_LINE_6" SITE "F10" ;
-LOCATE COMP "TEST_LINE_7" SITE "E10" ;
-LOCATE COMP "TEST_LINE_8" SITE "A8" ;
-LOCATE COMP "TEST_LINE_9" SITE "B8" ;
-LOCATE COMP "TEST_LINE_10" SITE "G10" ;
-LOCATE COMP "TEST_LINE_11" SITE "G9" ;
-LOCATE COMP "TEST_LINE_12" SITE "C9" ;
-LOCATE COMP "TEST_LINE_13" SITE "C10" ;
-LOCATE COMP "TEST_LINE_14" SITE "H10" ;
-LOCATE COMP "TEST_LINE_15" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0   #1
-LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1   #3
-LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2   #5
-LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3   #7
-#LOCATE COMP  "SFP_MOD1_1"    SITE "R1";     #DQLL0_4   #9
-#LOCATE COMP  "SFP_MOD2_1"    SITE "R2";     #DQLL0_5   #11
-#LOCATE COMP  "SFP_RATESEL_1" SITE "N3";     #DQSLL0_T  #13
-LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C  #15
-LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6   #17
-#LOCATE COMP  "SFP_TXFAULT_1" SITE "P6";     #DQLL0_7   #19
-LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8   #21
-LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9   #23
-LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0   #25
-LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1   #27
-#LOCATE COMP  "SFP_MOD1_2"    SITE "AB1";    #DQLL2_2   #29
-#LOCATE COMP  "SFP_MOD2_2"    SITE "AC1";    #DQLL2_3   #31
-#LOCATE COMP  "SFP_RATESEL_2" SITE "AA1";    #DQLL2_4   #33
-LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5   #35
-LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
-#LOCATE COMP  "SFP_TXFAULT_2" SITE "W6";     #DQLL2_C   #39  #should be DQSLL2
-LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0   #2
-LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1   #4
-LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2   #6
-LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3   #8
-#LOCATE COMP  "SFP_MOD1_3"      SITE "AB3";    #DQLL3_4   #10
-#LOCATE COMP  "SFP_MOD2_3"      SITE "AB4";    #DQLL3_5   #12
-#LOCATE COMP  "SFP_RATESEL_3"   SITE "Y6";     #DQLL3_T   #14  #should be DQSLL3
-LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6   #18
-#LOCATE COMP  "SFP_TXFAULT_3"   SITE "AA4";    #DQLL3_7   #20
-LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8   #22
-LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9   #24
-LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0   #26
-LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1   #28
-#LOCATE COMP  "SFP_MOD1_4"      SITE "T1";     #DQLL1_2   #30
-#LOCATE COMP  "SFP_MOD2_4"      SITE "U1";     #DQLL1_3   #32
-#LOCATE COMP  "SFP_RATESEL_4"   SITE "P4";     #DQLL1_4   #34
-LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5   #36
-LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T  #38
-#LOCATE COMP  "SFP_TXFAULT_4"   SITE "R4";     #DQSLL1_C  #40
-LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0   #169
-LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1   #171
-LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2   #173
-LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3   #175
-#LOCATE COMP  "SFP_MOD1_5"     SITE "AA26";   #DQLR1_4   #177
-#LOCATE COMP  "SFP_MOD2_5"     SITE "AB26";   #DQLR1_5   #179
-#LOCATE COMP  "SFP_RATESEL_5"  SITE "W21";    #DQSLR1_T  #181
-LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C  #183
-LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6   #185
-#LOCATE COMP  "SFP_TXFAULT_5"  SITE "AA23";   #DQLR1_7   #187
-LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0   #170
-LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1   #172
-LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2   #174
-LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3   #176
-#LOCATE COMP  "SFP_MOD1_6"     SITE "T26";    #DQLR2_4   #178
-#LOCATE COMP  "SFP_MOD2_6"     SITE "U26";    #DQLR2_5   #180
-#LOCATE COMP  "SFP_RATESEL_6"  SITE "V21";    #DQSLR2_T  #182
-LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C  #184
-LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6   #186
-#LOCATE COMP  "SFP_TXFAULT_6"  SITE "V24";    #DQLR2_7   #188
-
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
-#LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
-#LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
-#LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
-#LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE_1" SITE "AA20" ;
-LOCATE COMP "CODE_LINE_0" SITE "Y21" ;
-IOBUF PORT  "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT  "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF  PORT "SUPPL" IO_TYPE=LVDS25;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-#################################################################
-#GSR_NET NET "GSR_N";  
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
-#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ;	# to debug only
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
-#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ;	# to debug only
-#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;
-
-BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ;
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*";
-BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*";
-
-#UGROUP "SPIlogic" BBOX 20 20
-#       BLKNAME THE_SPI_RELOAD;
-#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ;
-
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_0";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_1";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_2";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c_3";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_0";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_1";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_2";
-PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_3";
-
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-FREQUENCY NET "rxup_full_clk" 200.000000 MHz ;
diff --git a/soda_hub_probe.rvl b/soda_hub_probe.rvl
deleted file mode 100644
index 644a0ea..0000000
--- a/soda_hub_probe.rvl
+++ /dev/null
@@ -1,303 +0,0 @@
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2015-03-17">
-    <IP Version="1_5_062609"/>
-    <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
-    <Core InsertDataset="0" Insert="1" Reveal_sig="2095246907" Name="trb3_periph_sodahub_LA0" ID="0">
-        <Setting>
-            <Clock SampleClk="rxup_full_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
-            <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="64"/>
-            <Capture Mode="0" MinSamplesPerTrig="8"/>
-            <Event CntEnable="0" MaxEventCnt="8"/>
-            <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_hub_LA0_net"/>
-            <DistRAM Disable="0"/>
-        </Setting>
-        <Dataset Name="Base">
-            <Trace>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/got_link_ready_i"/>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/rx_k"/>
-                <Bus Name="the_hub_sync_uplink/rx_data">
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_data:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm"/>
-                <Bus Name="the_hub_sync_uplink/rx_dlm_word">
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:7"/>
-                </Bus>
-                <Bus Name="the_hub_sync_uplink/rx_fsm_state">
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:3"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/tx_k"/>
-                <Bus Name="the_hub_sync_uplink/tx_data">
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm"/>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_preview_in"/>
-                <Bus Name="the_hub_sync_uplink/tx_dlm_word">
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_dlm_word:7"/>
-                </Bus>
-                <Bus Name="the_hub_sync_uplink/tx_fsm_state">
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/tx_fsm_state:3"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/sd_los_in"/>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/sd_txdis_out"/>
-                <Bus Name="the_hub_sync_uplink/wa_position_rx">
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:8"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:9"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:10"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:11"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:12"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:13"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:14"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position_rx:15"/>
-                </Bus>
-                <Bus Name="the_hub_sync_uplink/wa_position">
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:8"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:9"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:10"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:11"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:12"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:13"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:14"/>
-                    <Sig Type="SIG" Name="the_hub_sync_uplink/wa_position:15"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pll_lol"/>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pcs_rst"/>
-                <Bus Name="sfp_los">
-                    <Sig Type="SIG" Name="sfp_los:1"/>
-                    <Sig Type="SIG" Name="sfp_los:2"/>
-                    <Sig Type="SIG" Name="sfp_los:3"/>
-                    <Sig Type="SIG" Name="sfp_los:4"/>
-                    <Sig Type="SIG" Name="sfp_los:5"/>
-                    <Sig Type="SIG" Name="sfp_los:6"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_hub_sync_uplink/watchdog_trigger"/>
-                <Bus Name="the_hub_sync_downlink/got_link_ready_i">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/got_link_ready_i:3"/>
-                </Bus>
-                <Bus Name="the_hub_sync_downlink/rx_k">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:3"/>
-                </Bus>
-                <Bus Name="the_hub_sync_downlink/rx_data[3:0]">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:7"/>
-                </Bus>
-                <Bus Name="the_hub_sync_downlink/rx_dlm">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm:3"/>
-                </Bus>
-                <Bus Name="the_hub_sync_downlink/rx_dlm_word[3:0]">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:0:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:1:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:2:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/rx_dlm_word:3:7"/>
-                </Bus>
-                <Bus Name="the_hub_sync_downlink/tx_k">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:3"/>
-                </Bus>
-                <Bus Name="the_hub_sync_downlink/tx_data[3:0]">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:7"/>
-                </Bus>
-                <Bus Name="the_hub_sync_downlink/tx_dlm">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm:3"/>
-                </Bus>
-                <Bus Name="the_hub_sync_downlink/tx_dlm_word[3:0]">
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:0:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:1:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:2:7"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:0"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:1"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:2"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:3"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:4"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:5"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:6"/>
-                    <Sig Type="SIG" Name="the_hub_sync_downlink/tx_dlm_word:3:7"/>
-                </Bus>
-            </Trace>
-            <Trigger>
-                <TU Serialbits="0" Type="0" ID="1" Sig="a_soda_hub/start_of_superburst_s,"/>
-                <TU Serialbits="0" Type="0" ID="2" Sig="a_soda_hub/soda_cmd_valid_s,"/>
-                <TU Serialbits="0" Type="0" ID="3" Sig="the_hub_sync_uplink/watchdog_trigger,"/>
-                <TU Serialbits="0" Type="0" ID="4" Sig="the_hub_sync_uplink/the_rx_fsm/reset_timer2,"/>
-                <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)the_hub_sync_uplink/the_rx_fsm/state_out[3:0],"/>
-                <TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
-                <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
-                <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
-                <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
-                <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
-            </Trigger>
-        </Dataset>
-    </Core>
-</Project>
diff --git a/soda_slave/project/README.txt b/soda_slave/project/README.txt
deleted file mode 100644
index 5cb3f50..0000000
--- a/soda_slave/project/README.txt
+++ /dev/null
@@ -1 +0,0 @@
-The place for diamond projects
diff --git a/soda_slave/sim/README.txt b/soda_slave/sim/README.txt
deleted file mode 100644
index 288a440..0000000
--- a/soda_slave/sim/README.txt
+++ /dev/null
@@ -1 +0,0 @@
-The place for the simulator projects.
diff --git a/soda_slave/trb3_periph_sodaslave.p2t b/soda_slave/trb3_periph_sodaslave.p2t
deleted file mode 100644
index 3942b0a..0000000
--- a/soda_slave/trb3_periph_sodaslave.p2t
+++ /dev/null
@@ -1,21 +0,0 @@
--w
--i 15
--l 5
--n 1
--y
--s 12
--t 23
--c 1
--e 2
-#-g guidefile.ncd
--m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
--exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
diff --git a/soda_slave/trb3_periph_sodaslave.prj b/soda_slave/trb3_periph_sodaslave.prj
deleted file mode 100644
index ce9db77..0000000
--- a/soda_slave/trb3_periph_sodaslave.prj
+++ /dev/null
@@ -1,160 +0,0 @@
-
-# implementation: "workdir"
-impl -add workdir -type fpga
-
-# device options
-set_option -technology LATTICE-ECP3
-set_option -part LFE3_150EA
-set_option -package FN672C
-set_option -speed_grade -8
-set_option -part_companion ""
-
-# compilation/mapping options
-set_option -default_enum_encoding sequential
-set_option -symbolic_fsm_compiler 1
-set_option -top_module "trb3_periph_sodaslave"
-set_option -resource_sharing true
-
-# map options
-set_option -frequency 200
-set_option -fanout_limit 100
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-#set_option -force_gsr 
-set_option -force_gsr false
-set_option -fixgatedclocks false #3
-set_option -fixgeneratedclocks false #3
-set_option -compiler_compatible true
-
-
-# simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 1
-
-# automatic place and route (vendor) options
-set_option -write_apr_constraint 0
-
-# set result format/file last
-project -result_format "edif"
-project -result_file "workdir/trb3_periph_sodaslave.edf"
-
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
-impl -active "workdir"
-
-####################
-
-
-
-#add_file options
-
-add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib "work" "../../trb3/base/trb3_components.vhd"
-
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic.vhd"
-
-
-add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
-
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
-
-add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
-add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
-
-
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
-
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
-
-add_file -vhdl -lib "work" "../../trb3/base/cores/pll_in200_out100.vhd"
-
-
-
-
-add_file -vhdl -lib "work" "trb3_periph_sodaslave.vhd"
-
diff --git a/soda_slave/trb3_periph_sodaslave.vhd b/soda_slave/trb3_periph_sodaslave.vhd
deleted file mode 100644
index d6670cd..0000000
--- a/soda_slave/trb3_periph_sodaslave.vhd
+++ /dev/null
@@ -1,615 +0,0 @@
---No serdes connection to central FPGA, only one synchronous input link on one SFP of the SFP-AddOn
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodaslave is
-  generic(
-    SYNC_MODE : integer range 0 to 1 := c_NO;   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
-    USE_125_MHZ : integer := c_NO;
-    CLOCK_FREQUENCY : integer := 100;
-    NUM_INTERFACES : integer := 1
-    );
-  port(
-    --Clocks
-    CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
-    CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
-    CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-    CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
-    --Trigger
-    --TRIGGER_LEFT  : in std_logic;       --left side trigger input from fan-out
-    --TRIGGER_RIGHT : in std_logic;       --right side trigger input from fan-out
-    --Serdes Clocks - do not use
-    --CLK_SERDES_INT_LEFT  : in  std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
-    --CLK_SERDES_INT_RIGHT : in  std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
-
-    --serdes I/O - connect as you like, no real use
-    SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
-    SERDES_ADDON_RX      : in  std_logic_vector(15 downto 0);
-
-    --Inter-FPGA Communication
-    FPGA5_COMM : inout std_logic_vector(11 downto 0);
-                                                      --Bit 0/1 input, serial link RX active
-                                                      --Bit 2/3 output, serial link TX active
-                                                      --others yet undefined
-    --Connection to AddOn
-    LED_LINKOK : out std_logic_vector(6 downto 1);
-    LED_RX     : out std_logic_vector(6 downto 1); 
-    LED_TX     : out std_logic_vector(6 downto 1);
-    SFP_MOD0   : in  std_logic_vector(6 downto 1);
-    SFP_TXDIS  : out std_logic_vector(6 downto 1); 
-    SFP_LOS    : in  std_logic_vector(6 downto 1);
-    --SFP_MOD1   : inout std_logic_vector(6 downto 1); 
-    --SFP_MOD2   : inout std_logic_vector(6 downto 1); 
-    --SFP_RATESEL : out std_logic_vector(6 downto 1);
-    --SFP_TXFAULT : in  std_logic_vector(6 downto 1);
-
-    --Flash ROM & Reboot
-    FLASH_CLK  : out   std_logic;
-    FLASH_CS   : out   std_logic;
-    FLASH_DIN  : out   std_logic;
-    FLASH_DOUT : in    std_logic;
-    PROGRAMN   : out   std_logic;                     --reboot FPGA
-
-    --Misc
-    TEMPSENS   : inout std_logic;       --Temperature Sensor
-    CODE_LINE  : in    std_logic_vector(1 downto 0);
-    LED_GREEN  : out   std_logic;
-    LED_ORANGE : out   std_logic;
-    LED_RED    : out   std_logic;
-    LED_YELLOW : out   std_logic;
-    SUPPL      : in    std_logic;       --terminated diff pair, PCLK, Pads
-
-    --Test Connectors
-    TEST_LINE : out std_logic_vector(15 downto 0)
-    );
-
-
-  attribute syn_useioff                  : boolean;
-  --no IO-FF for LEDs relaxes timing constraints
-  attribute syn_useioff of LED_GREEN     : signal is false;
-  attribute syn_useioff of LED_ORANGE    : signal is false;
-  attribute syn_useioff of LED_RED       : signal is false;
-  attribute syn_useioff of LED_YELLOW    : signal is false;
-  attribute syn_useioff of TEMPSENS      : signal is false;
-  attribute syn_useioff of PROGRAMN      : signal is false;
-  attribute syn_useioff of CODE_LINE     : signal is false;
-  attribute syn_useioff of LED_LINKOK    : signal is false;
-  attribute syn_useioff of LED_TX        : signal is false;
-  attribute syn_useioff of LED_RX        : signal is false;
-  attribute syn_useioff of SFP_MOD0      : signal is false;
-  attribute syn_useioff of SFP_TXDIS     : signal is false;
-  attribute syn_useioff of SFP_LOS       : signal is false;
-  attribute syn_useioff of TEST_LINE  : signal is false;
-
-  --important signals _with_ IO-FF
-  attribute syn_useioff of FLASH_CLK  : signal is true;
-  attribute syn_useioff of FLASH_CS   : signal is true;
-  attribute syn_useioff of FLASH_DIN  : signal is true;
-  attribute syn_useioff of FLASH_DOUT : signal is true;
-  attribute syn_useioff of FPGA5_COMM : signal is true;
-
-
-end entity;
-
-architecture trb3_periph_sodaslave_arch of trb3_periph_sodaslave is
-  --Constants
-  constant REGIO_NUM_STAT_REGS : integer := 0;
-  constant REGIO_NUM_CTRL_REGS : integer := 2;
-
-  attribute syn_keep     : boolean;
-  attribute syn_preserve : boolean;
-
-  constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
-  
-  --Clock / Reset
-  signal clk_sys_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
---   signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
-  signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
-  signal clear_i                  : std_logic;
-  signal reset_i                  : std_logic;
-  signal GSR_N                    : std_logic;
-  attribute syn_keep of GSR_N     : signal is true;
-  attribute syn_preserve of GSR_N : signal is true;
-  signal clk_sys_internal         : std_logic;
-  signal clk_raw_internal         : std_logic;
-  signal rx_clock_half             : std_logic;
-  signal rx_clock_full             : std_logic;
-  signal clk_tdc                  : std_logic;
-  signal time_counter, time_counter2 : unsigned(31 downto 0);
-  --Media Interface
-  signal med_stat_op        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-  signal med_ctrl_op        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-  signal med_stat_debug     : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-  signal med_ctrl_debug     : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-  signal med_data_out       : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-  signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-  signal med_dataready_out  : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-  signal med_read_out       : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-  signal med_data_in        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-  signal med_packet_num_in  : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-  signal med_dataready_in   : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-  signal med_read_in        : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
-  --Slow Control channel
-  signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-  signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-  signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-  signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-  signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
-  signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
-  signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-  signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
-  --RegIO
-  signal my_address             : std_logic_vector (15 downto 0);
-  signal regio_addr_out         : std_logic_vector (15 downto 0);
-  signal regio_read_enable_out  : std_logic;
-  signal regio_write_enable_out : std_logic;
-  signal regio_data_out         : std_logic_vector (31 downto 0);
-  signal regio_data_in          : std_logic_vector (31 downto 0);
-  signal regio_dataready_in     : std_logic;
-  signal regio_no_more_data_in  : std_logic;
-  signal regio_write_ack_in     : std_logic;
-  signal regio_unknown_addr_in  : std_logic;
-  signal regio_timeout_out      : std_logic;
-
-  --Timer
-  signal global_time         : std_logic_vector(31 downto 0);
-  signal local_time          : std_logic_vector(7 downto 0);
-  signal time_since_last_trg : std_logic_vector(31 downto 0);
-  signal timer_ticks         : std_logic_vector(1 downto 0);
-
-  --Flash
-  signal spimem_read_en          : std_logic;
-  signal spimem_write_en         : std_logic;
-  signal spimem_data_in          : std_logic_vector(31 downto 0);
-  signal spimem_addr             : std_logic_vector(8 downto 0);
-  signal spimem_data_out         : std_logic_vector(31 downto 0);
-  signal spimem_dataready_out    : std_logic;
-  signal spimem_no_more_data_out : std_logic;
-  signal spimem_unknown_addr_out : std_logic;
-  signal spimem_write_ack_out    : std_logic;
-
-  --media interface
-  signal sci1_ack      : std_logic;
-  signal sci1_write    : std_logic;
-  signal sci1_read     : std_logic;
-  signal sci1_data_in  : std_logic_vector(7 downto 0);
-  signal sci1_data_out : std_logic_vector(7 downto 0);
-  signal sci1_addr     : std_logic_vector(8 downto 0);  
-  signal sci1_nack     : std_logic;
-
-
-  signal soda_rx_clock_half : std_logic;
-  signal soda_rx_clock_full : std_logic;
-  signal tx_dlm_i          : std_logic;
-  signal rx_dlm_i          : std_logic;
-  signal tx_dlm_word       : std_logic_vector(7 downto 0);
-  signal rx_dlm_word       : std_logic_vector(7 downto 0);
-  signal send_net_reset    : std_logic;
-  signal make_reset        : std_logic;
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-  GSR_N <= pll_lock;
-  send_net_reset <= med_stat_op(15);
-  
-  THE_RESET_HANDLER : trb_net_reset_handler
-    generic map(
-      RESET_DELAY => x"FEEE"
-      )
-    port map(
-      CLEAR_IN      => '0',              -- reset input (high active, async)
-      CLEAR_N_IN    => '1',              -- reset input (low active, async)
-      CLK_IN        => clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
-      SYSCLK_IN     => clk_sys_i,        -- PLL/DLL remastered clock
-      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
-      RESET_IN      => '0',              -- general reset signal (SYSCLK)
-      TRB_RESET_IN  => make_reset,       -- TRBnet reset signal (SYSCLK)
-      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
-      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
-      DEBUG_OUT     => open
-      );  
-
-make_reset <= med_stat_op(13); -- or med_stat_op(1) or med_stat_op(0);
-      
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
-  THE_MAIN_PLL : pll_in200_out100
-    port map(
-      CLK   => CLK_GPLL_RIGHT,
-      CLKOP => clk_sys_internal,
-      CLKOK => clk_raw_internal,
-      LOCK  => pll_lock
-      );
-end generate;      
-
-gen_125 : if USE_125_MHZ = c_YES generate
-  clk_sys_internal <= CLK_GPLL_LEFT;
-  clk_raw_internal <= CLK_GPLL_LEFT;
-end generate; 
-
-gen_sync_clocks : if SYNC_MODE = c_YES generate
-  clk_sys_i <= rx_clock_half;
---   clk_200_i <= rx_clock_full;
-end generate;
-
-gen_local_clocks : if SYNC_MODE = c_NO generate
-  clk_sys_i <= clk_sys_internal;
---   clk_200_i <= clk_raw_internal;
-end generate;
-
-
--- ---------------------------------------------------------------------------
--- -- The TrbNet media interface (to other FPGA)
--- ---------------------------------------------------------------------------
---   THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
---     generic map(
---       SERDES_NUM  => 1,     --number of serdes in quad
---       EXT_CLOCK   => c_NO,  --use internal clock
---       USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
---       USE_125_MHZ => USE_125_MHZ,
---       USE_CTC     => c_NO,
---       USE_SLAVE   => SYNC_MODE
---       )      
---     port map(
---       CLK                => clk_raw_internal,
---       SYSCLK             => clk_sys_i,
---       RESET              => reset_i,
---       CLEAR              => clear_i,
---       CLK_EN             => '1',
---       --Internal Connection
---       MED_DATA_IN        => med_data_out(15 downto 0),
---       MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
---       MED_DATAREADY_IN   => med_dataready_out(0),
---       MED_READ_OUT       => med_read_in(0),
---       MED_DATA_OUT       => med_data_in(15 downto 0),
---       MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
---       MED_DATAREADY_OUT  => med_dataready_in(0),
---       MED_READ_IN        => med_read_out(0),
---       REFCLK2CORE_OUT    => open,
---       CLK_RX_HALF_OUT    => rx_clock_half,
---       CLK_RX_FULL_OUT    => rx_clock_full,
---       
---       --SFP Connection
---       SD_RXD_P_IN        => SERDES_ADDON_RX(2),
---       SD_RXD_N_IN        => SERDES_ADDON_RX(3),
---       SD_TXD_P_OUT       => SERDES_ADDON_TX(2),
---       SD_TXD_N_OUT       => SERDES_ADDON_TX(3),
---       SD_REFCLK_P_IN     => '0',
---       SD_REFCLK_N_IN     => '0',
---       SD_PRSNT_N_IN      => FPGA5_COMM(0),
---       SD_LOS_IN          => FPGA5_COMM(0),
---       SD_TXDIS_OUT       => FPGA5_COMM(2),
---       
---       SCI_DATA_IN        => sci1_data_in,
---       SCI_DATA_OUT       => sci1_data_out,
---       SCI_ADDR           => sci1_addr,
---       SCI_READ           => sci1_read,
---       SCI_WRITE          => sci1_write,
---       SCI_ACK            => sci1_ack,        
---       -- Status and control port
---       STAT_OP            => med_stat_op(15 downto 0),
---       CTRL_OP            => med_ctrl_op(15 downto 0),
---       STAT_DEBUG         => med_stat_debug(63 downto 0),
---       CTRL_DEBUG         => (others => '0')
---       );
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
-  THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
-    generic map(
-      REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
-      REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
-      ADDRESS_MASK              => x"FFFF",
-      BROADCAST_BITMASK         => x"FF",
-      BROADCAST_SPECIAL_ADDR    => x"45",
-      REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
-      REGIO_HARDWARE_VERSION    => x"9100b000",
-      REGIO_INIT_ADDRESS        => x"f351",
-      REGIO_USE_VAR_ENDPOINT_ID => c_YES,
-      CLOCK_FREQUENCY           => CLOCK_FREQUENCY,
-      TIMING_TRIGGER_RAW        => c_YES,
-      --Configure data handler
-      DATA_INTERFACE_NUMBER     => 1,
-      DATA_BUFFER_DEPTH         => 9,  --13
-      DATA_BUFFER_WIDTH         => 32,
-      DATA_BUFFER_FULL_THRESH   => 256,
-      TRG_RELEASE_AFTER_DATA    => c_YES,
-      HEADER_BUFFER_DEPTH       => 9,
-      HEADER_BUFFER_FULL_THRESH => 256
-      )
-    port map(
-      CLK                => clk_sys_i,
-      RESET              => reset_i,
-      CLK_EN             => '1',
-      MED_DATAREADY_OUT  => med_dataready_out(0),
-      MED_DATA_OUT       => med_data_out,
-      MED_PACKET_NUM_OUT => med_packet_num_out,
-      MED_READ_IN        => med_read_in(0),
-      MED_DATAREADY_IN   => med_dataready_in(0),
-      MED_DATA_IN        => med_data_in,
-      MED_PACKET_NUM_IN  => med_packet_num_in,
-      MED_READ_OUT       => med_read_out(0),
-      MED_STAT_OP_IN     => med_stat_op,
-      MED_CTRL_OP_OUT    => med_ctrl_op,
-
-      --Timing trigger in
-      TRG_TIMING_TRG_RECEIVED_IN  => '0',
-      --LVL1 trigger to FEE
-      LVL1_TRG_DATA_VALID_OUT     => open,
-      LVL1_VALID_TIMING_TRG_OUT   => open,
-      LVL1_VALID_NOTIMING_TRG_OUT => open,
-      LVL1_INVALID_TRG_OUT        => open,
-
-      LVL1_TRG_TYPE_OUT        => open,
-      LVL1_TRG_NUMBER_OUT      => open,
-      LVL1_TRG_CODE_OUT        => open,
-      LVL1_TRG_INFORMATION_OUT => open,
-      LVL1_INT_TRG_NUMBER_OUT  => open,
-
-      --Information about trigger handler errors
-      TRG_MULTIPLE_TRG_OUT     => open,
-      TRG_TIMEOUT_DETECTED_OUT => open,
-      TRG_SPURIOUS_TRG_OUT     => open,
-      TRG_MISSING_TMG_TRG_OUT  => open,
-      TRG_SPIKE_DETECTED_OUT   => open,
-
-      --Response from FEE
-      FEE_TRG_RELEASE_IN(0)       => '1',
-      FEE_TRG_STATUSBITS_IN       => (others => '0'),
-      FEE_DATA_IN                 => (others => '0'),
-      FEE_DATA_WRITE_IN(0)        => '0',
-      FEE_DATA_FINISHED_IN(0)     => '1',
-      FEE_DATA_ALMOST_FULL_OUT(0) => open,
-
-      -- Slow Control Data Port
-      REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
-      REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
-      REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
-      REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
-      REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
-      REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
-      REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
-      REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
-      REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
-      REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
-      BUS_ADDR_OUT         => regio_addr_out,
-      BUS_READ_ENABLE_OUT  => regio_read_enable_out,
-      BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
-      BUS_DATA_OUT         => regio_data_out,
-      BUS_DATA_IN          => regio_data_in,
-      BUS_DATAREADY_IN     => regio_dataready_in,
-      BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
-      BUS_WRITE_ACK_IN     => regio_write_ack_in,
-      BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
-      BUS_TIMEOUT_OUT      => regio_timeout_out,
-      ONEWIRE_INOUT        => TEMPSENS,
-      ONEWIRE_MONITOR_OUT  => open,
-
-      TIME_GLOBAL_OUT         => global_time,
-      TIME_LOCAL_OUT          => local_time,
-      TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
-      TIME_TICKS_OUT          => timer_ticks,
-
-      STAT_DEBUG_IPU              => open,
-      STAT_DEBUG_1                => open,
-      STAT_DEBUG_2                => open,
-      STAT_DEBUG_DATA_HANDLER_OUT => open,
-      STAT_DEBUG_IPU_HANDLER_OUT  => open,
-      STAT_TRIGGER_OUT            => open,
-      CTRL_MPLEX                  => (others => '0'),
-      IOBUF_CTRL_GEN              => (others => '0'),
-      STAT_ONEWIRE                => open,
-      STAT_ADDR_DEBUG             => open,
-      DEBUG_LVL1_HANDLER_OUT      => open
-      );
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
-  THE_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER    => 2,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 9,       1 => 9,       others => 0)
-      )
-    port map(
-      CLK   => clk_sys_i,
-      RESET => reset_i,
-
-      DAT_ADDR_IN          => regio_addr_out,
-      DAT_DATA_IN          => regio_data_out,
-      DAT_DATA_OUT         => regio_data_in,
-      DAT_READ_ENABLE_IN   => regio_read_enable_out,
-      DAT_WRITE_ENABLE_IN  => regio_write_enable_out,
-      DAT_TIMEOUT_IN       => regio_timeout_out,
-      DAT_DATAREADY_OUT    => regio_dataready_in,
-      DAT_WRITE_ACK_OUT    => regio_write_ack_in,
-      DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
-      DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
-    --Bus Handler (SPI Memory)
-      BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
-      BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
-      BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
-      BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
-      BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
-      BUS_TIMEOUT_OUT(0)                  => open,
-      BUS_DATA_IN(0*32+31 downto 0*32)    => spimem_data_out,
-      BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
-      BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
-      BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
-      BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
-
-
-      --SCI soda uplink Media Interface
-      BUS_READ_ENABLE_OUT(1)              => sci1_read,
-      BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
-      BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
-      BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
-      BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
-      BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
-      BUS_TIMEOUT_OUT(1)                  => open,
-      BUS_DATA_IN(1*32+7 downto 1*32)     => sci1_data_out,
-      BUS_DATAREADY_IN(1)                 => sci1_ack,
-      BUS_WRITE_ACK_IN(1)                 => sci1_ack,
-      BUS_NO_MORE_DATA_IN(1)              => '0',
-      BUS_UNKNOWN_ADDR_IN(1)              => sci1_nack,
-
-      STAT_DEBUG => open
-      );
-
-
-  
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
-  port map(
-    CLK_IN               => clk_sys_i,
-    RESET_IN             => reset_i,
-    
-    BUS_ADDR_IN          => spimem_addr,
-    BUS_READ_IN          => spimem_read_en,
-    BUS_WRITE_IN         => spimem_write_en,
-    BUS_DATAREADY_OUT    => spimem_dataready_out,
-    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
-    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
-    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
-    BUS_DATA_IN          => spimem_data_in,
-    BUS_DATA_OUT         => spimem_data_out,
-    
-    DO_REBOOT_IN         => common_ctrl_reg(15),     
-    PROGRAMN             => PROGRAMN,
-    
-    SPI_CS_OUT           => FLASH_CS,
-    SPI_SCK_OUT          => FLASH_CLK,
-    SPI_SDO_OUT          => FLASH_DIN,
-    SPI_SDI_IN           => FLASH_DOUT
-    );
-
-      
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------      
-
-THE_SODA_INPUT : med_ecp3_sfp_sync
-  generic map(
-    SERDES_NUM  => 0,    --number of serdes in quad
-    IS_SYNC_SLAVE => c_YES
-    )
-  port map(
-    CLK                => clk_raw_internal,
-    SYSCLK             => clk_sys_i,
-    RESET              => reset_i,
-    CLEAR              => clear_i,
-    --Internal Connection for TrbNet data
-    MED_DATA_IN        => med_data_out(15 downto 0),
-    MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
-    MED_DATAREADY_IN   => med_dataready_out(0),
-    MED_READ_OUT       => med_read_in(0),
-    MED_DATA_OUT       => med_data_in(15 downto 0),
-    MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
-    MED_DATAREADY_OUT  => med_dataready_in(0),
-    MED_READ_IN        => med_read_out(0),
-    CLK_RX_HALF_OUT    => soda_rx_clock_half,
-    CLK_RX_FULL_OUT    => soda_rx_clock_full,
-    
-    RX_DLM             => rx_dlm_i,
-    RX_DLM_WORD        => rx_dlm_word,
-    TX_DLM             => tx_dlm_i,
-    TX_DLM_WORD        => tx_dlm_word,
-    --SFP Connection
-    SD_RXD_P_IN        => SERDES_ADDON_RX(0),
-    SD_RXD_N_IN        => SERDES_ADDON_RX(1),
-    SD_TXD_P_OUT       => SERDES_ADDON_TX(0),
-    SD_TXD_N_OUT       => SERDES_ADDON_TX(1),
-    SD_REFCLK_P_IN     => '0',
-    SD_REFCLK_N_IN     => '0',
-    SD_PRSNT_N_IN      => SFP_MOD0(1),
-    SD_LOS_IN          => SFP_LOS(1),
-    SD_TXDIS_OUT       => SFP_TXDIS(1),
-    
-    SCI_DATA_IN        => sci1_data_in,
-    SCI_DATA_OUT       => sci1_data_out,
-    SCI_ADDR           => sci1_addr,
-    SCI_READ           => sci1_read,
-    SCI_WRITE          => sci1_write,
-    SCI_ACK            => sci1_ack,  
-    SCI_NACK           => sci1_nack,
-    -- Status and control port
-    STAT_OP            => med_stat_op(15 downto 0),
-    CTRL_OP            => med_ctrl_op(15 downto 0),
-    STAT_DEBUG         => med_stat_debug(63 downto 0),
-    CTRL_DEBUG         => (others => '0')
-   );      
-
-
----------------------------------------------------------------------------
--- The Soda Slave
----------------------------------------------------------------------------         
-  tx_dlm_i <= '0';
-  tx_dlm_word <= x"00";
-   
-   
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
-  LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
-  LED_YELLOW <= '1';
-  LED_GREEN  <= not med_stat_op(9);
-  LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
-
-  LED_LINKOK(1) <= not med_stat_op(9);  --link established
-  LED_TX(1)     <= not (med_stat_op(10) or med_stat_op(11)); --data RX or TX
-  LED_RX(1)     <= not med_stat_op(12);   --DLM RX 
-  
-  LED_LINKOK(6 downto 2) <= "11111";
-  LED_TX(6 downto 2)     <= "11111";
-  LED_RX(6 downto 2)     <= "11111";
-  
-  --no link to central FPGA
-  FPGA5_COMM(3) <= '0'; 
-  FPGA5_COMM(2) <= '0';
-
-
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------    
-  TEST_LINE(15 downto 0) <= med_stat_debug(15 downto 0);
-
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-  process
-    begin
-      wait until rising_edge(clk_sys_internal);
-      time_counter <= time_counter + 1;
-    end process;
-
-
-
-
-end architecture;
diff --git a/soda_slave/trb3_periph_sodaslave_constraints.lpf b/soda_slave/trb3_periph_sodaslave_constraints.lpf
deleted file mode 100644
index b6bc42b..0000000
--- a/soda_slave/trb3_periph_sodaslave_constraints.lpf
+++ /dev/null
@@ -1,53 +0,0 @@
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-
-#################################################################
-# Basic Settings
-#################################################################
-
-  SYSCONFIG MCCLK_FREQ = 20;
-
-  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-  
-#################################################################
-# Reset Nets
-#################################################################  
-GSR_NET NET "GSR_N";  
-
-
-
-
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-
-LOCATE COMP   "THE_SODA_INPUT/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-
-REGION "MEDIA_UPLINK" "R90C95D" 13 25;
-REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;
-REGION "REGION_SPI"   "R13C150D" 12 16 DEVSIZE;
-REGION "REGION_IOBUF" "R10C43D"  88 86 DEVSIZE;
-
-LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; 
-LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-LOCATE UGROUP "THE_SODA_INPUT/media_interface_group" REGION "MEDIA_DOWNLINK" ;
-
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_INPUT/SCI_DATA_OUT*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_INPUT/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_SODA_INPUT/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_INPUT/wa_pos*" 20 ns;
-
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-
diff --git a/soda_slave/workdir/.gitignore b/soda_slave/workdir/.gitignore
deleted file mode 100644
index 026f571..0000000
--- a/soda_slave/workdir/.gitignore
+++ /dev/null
@@ -1,10 +0,0 @@
-*
-
-!*txt
-!pmi*ngo
-!tsmac*ngo
-!sgm*ngo
-!.gitignore
-
-run_options.txt
-
diff --git a/soda_slave/workdir/pmi_ram_dpEbnonessdn208256208256.ngo b/soda_slave/workdir/pmi_ram_dpEbnonessdn208256208256.ngo
deleted file mode 120000
index c8f247d..0000000
--- a/soda_slave/workdir/pmi_ram_dpEbnonessdn208256208256.ngo
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn208256208256.ngo
\ No newline at end of file
diff --git a/soda_slave/workdir/pmi_ram_dpEbnonessdn96649664.ngo b/soda_slave/workdir/pmi_ram_dpEbnonessdn96649664.ngo
deleted file mode 120000
index e4f243b..0000000
--- a/soda_slave/workdir/pmi_ram_dpEbnonessdn96649664.ngo
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn96649664.ngo
\ No newline at end of file
diff --git a/soda_slave/workdir/serdes_ch4.txt b/soda_slave/workdir/serdes_ch4.txt
deleted file mode 120000
index 0fdc84c..0000000
--- a/soda_slave/workdir/serdes_ch4.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_ch4.txt
\ No newline at end of file
diff --git a/soda_slave/workdir/serdes_full_ctc.txt b/soda_slave/workdir/serdes_full_ctc.txt
deleted file mode 120000
index c3c2ef1..0000000
--- a/soda_slave/workdir/serdes_full_ctc.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.txt
\ No newline at end of file
diff --git a/soda_slave/workdir/serdes_gbe_0ch.txt b/soda_slave/workdir/serdes_gbe_0ch.txt
deleted file mode 120000
index 5d0d4c0..0000000
--- a/soda_slave/workdir/serdes_gbe_0ch.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.txt
\ No newline at end of file
diff --git a/soda_slave/workdir/serdes_onboard_full.txt b/soda_slave/workdir/serdes_onboard_full.txt
deleted file mode 120000
index 74ee4d8..0000000
--- a/soda_slave/workdir/serdes_onboard_full.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.txt
\ No newline at end of file
diff --git a/soda_slave/workdir/serdes_sync_0.txt b/soda_slave/workdir/serdes_sync_0.txt
deleted file mode 120000
index 616aa00..0000000
--- a/soda_slave/workdir/serdes_sync_0.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.txt
\ No newline at end of file
diff --git a/soda_slave/workdir/serdes_sync_125_0.txt b/soda_slave/workdir/serdes_sync_125_0.txt
deleted file mode 120000
index 11cb7c5..0000000
--- a/soda_slave/workdir/serdes_sync_125_0.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_125_0.txt
\ No newline at end of file
diff --git a/soda_slave/workdir/sfp_0_200_ctc.txt b/soda_slave/workdir/sfp_0_200_ctc.txt
deleted file mode 120000
index 980cc4a..0000000
--- a/soda_slave/workdir/sfp_0_200_ctc.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.txt
\ No newline at end of file
diff --git a/soda_slave/workdir/sfp_0_200_int.txt b/soda_slave/workdir/sfp_0_200_int.txt
deleted file mode 120000
index 9ca2088..0000000
--- a/soda_slave/workdir/sfp_0_200_int.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.txt
\ No newline at end of file
diff --git a/soda_slave/workdir/sfp_1_125_int.txt b/soda_slave/workdir/sfp_1_125_int.txt
deleted file mode 120000
index 9cd19aa..0000000
--- a/soda_slave/workdir/sfp_1_125_int.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.txt
\ No newline at end of file
diff --git a/soda_slave/workdir/sfp_1_200_int.txt b/soda_slave/workdir/sfp_1_200_int.txt
deleted file mode 120000
index 917cb3f..0000000
--- a/soda_slave/workdir/sfp_1_200_int.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.txt
\ No newline at end of file
diff --git a/soda_slave/workdir/sgmii_gbe_pcs35.ngo b/soda_slave/workdir/sgmii_gbe_pcs35.ngo
deleted file mode 120000
index 06f3878..0000000
--- a/soda_slave/workdir/sgmii_gbe_pcs35.ngo
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.ngo
\ No newline at end of file
diff --git a/soda_slave/workdir/tsmac35.ngo b/soda_slave/workdir/tsmac35.ngo
deleted file mode 120000
index 51654ad..0000000
--- a/soda_slave/workdir/tsmac35.ngo
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35.ngo
\ No newline at end of file
diff --git a/soda_source.ldf b/soda_source.ldf
deleted file mode 100644
index afa532b..0000000
--- a/soda_source.ldf
+++ /dev/null
@@ -1,340 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="3.2" title="soda_source" device="LFE3-150EA-8FN672C" default_implementation="soda_source">
-    <Options>
-        <Option name="HDL type" value="VHDL"/>
-    </Options>
-    <Implementation title="soda_source" dir="soda_source" description="soda_source" synthesis="synplify" default_strategy="Strategy1">
-        <Options def_top="trb3_periph_sodasource" top="trb3_periph_sodasource"/>
-        <Source name="code/version.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_source.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_d8crc8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_start_of_burst_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_clockscaler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_packet_handler.vhd" type="VHDL" type_short="VHDL" excluded="TRUE">
-            <Options/>
-        </Source>
-        <Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/med_ecp3_sfp_sync_down.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_cmd_window_generator.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_sync_source_downstream.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_sync_source_downstream.lpc" type="LPC_Module" type_short="LPC">
-            <Options/>
-        </Source>
-        <Source name="code/ip/serdes_sync_source_downstream.ipx" type="IPX_Module" type_short="IPX">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trb3/base/trb3_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_buf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_CRC8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_lvl1.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_ipu.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/handler_trigger_and_data.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/fpga_reboot.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_slim.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_master.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_databus_memory.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_ltc2600.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/rom_16x8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/state_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x8_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_16x16_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/ram_dp_rw.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/basics/pulse_stretch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_addresses.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf5.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf6.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_sbuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regIO.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_regio_bus_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_encoder.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_dummy_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_term_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_priority_arbiter.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net_pattern_gen.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_obuf_nodata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ibuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_api_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_iobuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_io_multiplexer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_trigger.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_endpoint_hades_full_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/med_sync_define.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_base.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/trb_net16_hub_logic.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../trbnet/special/spi_flash_and_fpga_reload.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="code/trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
-            <Options top_module="trb3_periph_sodasource"/>
-        </Source>
-        <Source name="code/soda_source_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
-            <Options/>
-        </Source>
-        <Source name="soda_source.lpf" type="Logic Preference" type_short="LPF">
-            <Options/>
-        </Source>
-        <Source name="soda_source_probe.rvl" type="Reveal" type_short="Reveal">
-            <Options/>
-        </Source>
-        <Source name="trb3_soda_source.xcf" type="Programming Project File" type_short="Programming">
-            <Options/>
-        </Source>
-    </Implementation>
-    <Strategy name="Strategy1" file="soda_source1.sty"/>
-</BaliProject>
diff --git a/soda_source.lpf b/soda_source.lpf
deleted file mode 120000
index 5a1ab78..0000000
--- a/soda_source.lpf
+++ /dev/null
@@ -1 +0,0 @@
-soda_source_groningen.lpf
\ No newline at end of file
diff --git a/soda_source/compile_kvi_periph.sh b/soda_source/compile_kvi_periph.sh
deleted file mode 100755
index 81cb83b..0000000
--- a/soda_source/compile_kvi_periph.sh
+++ /dev/null
@@ -1,9 +0,0 @@
-#!/bin/sh -x
-cd /usr/local/diamond/2.1_x64/bin/lin64
-export bindir=`pwd`
-
-#export bindirs=/usr/local/diamond/2.1_x64/bin/lin64
-. /usr/local/diamond/2.1_x64/bin/lin64/diamond_env
-
-cd /local/lemmens/lattice/soda/soda_source
-exec ./compile_periph_kvi.pl
diff --git a/soda_source/compile_periph_kvi.pl b/soda_source/compile_periph_kvi.pl
deleted file mode 100755
index a6478a1..0000000
--- a/soda_source/compile_periph_kvi.pl
+++ /dev/null
@@ -1,153 +0,0 @@
-#!/usr/bin/perl -W
-use Data::Dumper;
-use warnings;
-use strict;
-
-
-
-
-###################################################################################
-#Settings for this project
-my $TOPNAME                      = "trb3_periph_sodasource";  #Name of top-level entity
-my $PRJNAME                      = "soda_source";  #Name of the project
-my $lattice_path                 = '/usr/local/diamond/2.1_x64';
-my $synplify_path                = '/usr/local/diamond/2.1_x64';
-my $lm_license_file_for_synplify = "27031\@kvivs17.kvi.nl";
-#my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
-my $lm_license_file_for_par      = "27031\@kvivs17.kvi.nl";
-###################################################################################
-
-
-use FileHandle;
-
-$ENV{'SYNPLIFY'}=$synplify_path;
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-
-
-my $FAMILYNAME="LatticeECP3";
-my $DEVICENAME="LFE3-150EA";
-my $PACKAGE="FPBGA672";
-my $SPEEDGRADE="8";
-
-
-#create full lpf file
-system("cp ../../trb3/base/trb3_periph_hub.lpf workdir/$TOPNAME.lpf");
-system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
-
-
-#set -e
-#set -o errexit
-
-#generate timestamp
-my $t=time;
-my $fh = new FileHandle(">version.vhd");
-die "could not open file" if (! defined $fh);
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
-    constant VERSION_NUMBER_TIME  : integer   := $t;
-
-end package version;
-EOF
-$fh->close;
-
-system("env| grep LM_");
-my $r = "";
-
-## timestamp to remember compiletime
-my $c="$synplify_path/bin/lin64/synpwrap -prj $PRJNAME"."_syn.prj"; ##$TOPNAME.prj";
-$r=execute($c, "do_not_exit" );
-
-
-chdir "workdir";
-##$fh = new FileHandle("<$TOPNAME".".srr");
-$fh = new FileHandle("../$PRJNAME".".srr");
-my @a = <$fh>;
-$fh -> close;
-
-
-
-foreach (@a)
-{
-    if(/\@E:/)
-    {
-	print "\n";
-	$c="cat $PRJNAME.srr | grep \"\@E\"";
-	system($c);
-        print "\n\n";
-	exit 129;
-    }
-}
-
-
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-
-
-$c=qq| $lattice_path/ispfpga/bin/lin64/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "../$PRJNAME.edn" "$PRJNAME.ngo" |;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/edfupdate   -t "$PRJNAME.tcy" -w "$PRJNAME.ngo" -m "$PRJNAME.ngo" "$PRJNAME.ngx"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$PRJNAME.ngo" "$PRJNAME.ngd"|;
-execute($c);
-
-my $tpmap = $TOPNAME . "_map" ;
-
-system("mv $TOPNAME.ncd guidefile.ncd");
-# $c=qq|$lattice_path/ispfpga/bin/lin/map -g guidefile.ncd -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-$c=qq|$lattice_path/ispfpga/bin/lin64/map                  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-execute($c);
-
-
-#$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
-$c=qq|$lattice_path/ispfpga/bin/lin64/par -f "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# IOR IO Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin64/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-#execute($c);
-
-# TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin64/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/ltxt2ptxt $TOPNAME.ncd|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No  $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd"  "$TOPNAME.prf"|;
-execute($c);
-
-chdir "..";
-
-exit;
-
-sub execute {
-    my ($c, $op) = @_;
-    #print "option: $op \n";
-    $op = "" if(!$op);
-    print "\n\ncommand to execute: $c \n";
-    $r=system($c);
-    if($r) {
-	print "$!";
-	if($op ne "do_not_exit") {
-	    exit;
-	}
-    }
-
-    return $r;
-
-}
diff --git a/soda_source/serdes_sync_source_downstream.txt b/soda_source/serdes_sync_source_downstream.txt
deleted file mode 100644
index cf095d4..0000000
--- a/soda_source/serdes_sync_source_downstream.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL            "G8B10B"
-CH0_MODE                "RXTX"
-CH1_MODE                "DISABLED"
-CH2_MODE                "DISABLED"
-CH3_MODE                "DISABLED"
-CH0_CDR_SRC       "REFCLK_CORE"
-PLL_SRC                 "REFCLK_CORE"
-TX_DATARATE_RANGE       "MEDHIGH"
-CH0_RX_DATARATE_RANGE   "MEDHIGH"
-REFCK_MULT              "10X"
-#REFCLK_RATE            200
-CH0_RX_DATA_RATE        "FULL"
-CH0_TX_DATA_RATE        "FULL"
-CH0_TX_DATA_WIDTH       "8"
-CH0_RX_DATA_WIDTH        "8"
-CH0_TX_FIFO       "DISABLED"
-CH0_RX_FIFO        "ENABLED"
-CH0_TDRV      "0"
-#CH0_TX_FICLK_RATE      200
-#CH0_RXREFCLK_RATE        "200"
-#CH0_RX_FICLK_RATE      200
-CH0_TX_PRE              "DISABLED"
-CH0_RTERM_TX            "50"
-CH0_RX_EQ               "DISABLED"
-CH0_RTERM_RX            "50"
-CH0_RX_DCC              "DC"
-CH0_LOS_THRESHOLD_LO       "2"
-PLL_TERM                "50"
-PLL_DCC                 "AC"
-PLL_LOL_SET             "0"
-CH0_TX_SB               "DISABLED"
-CH0_RX_SB               "DISABLED"
-CH0_TX_8B10B            "ENABLED"
-CH0_RX_8B10B            "ENABLED"
-CH0_COMMA_A             "1100000101"
-CH0_COMMA_B             "0011111010"
-CH0_COMMA_M             "1111111100"
-CH0_RXWA                "ENABLED"
-CH0_ILSM                "ENABLED"
-CH0_CTC                 "DISABLED"
-CH0_CC_MATCH4           "0100011100"
-CH0_CC_MATCH_MODE       "1"
-CH0_CC_MIN_IPG          "3"
-CCHMARK                 "9"
-CCLMARK                 "7"
-CH0_SSLB                "DISABLED"
-CH0_SPLBPORTS           "DISABLED"
-CH0_PCSLBPORTS          "DISABLED"
-INT_ALL                 "DISABLED"
-QD_REFCK2CORE           "ENABLED"
-
-
diff --git a/soda_source/sim/README.txt b/soda_source/sim/README.txt
deleted file mode 100644
index 288a440..0000000
--- a/soda_source/sim/README.txt
+++ /dev/null
@@ -1 +0,0 @@
-The place for the simulator projects.
diff --git a/soda_source/trb3_periph_sodasource.p2t b/soda_source/trb3_periph_sodasource.p2t
deleted file mode 100644
index 5e8d0d9..0000000
--- a/soda_source/trb3_periph_sodasource.p2t
+++ /dev/null
@@ -1,21 +0,0 @@
--w
--i 15
--l 5
--n 1
--y
--s 12
--t 24
--c 1
--e 2
-#-g guidefile.ncd
--m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
--exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
diff --git a/soda_source/trb3_periph_sodasource.vhd b/soda_source/trb3_periph_sodasource.vhd
deleted file mode 100644
index 0ee33ce..0000000
--- a/soda_source/trb3_periph_sodasource.vhd
+++ /dev/null
@@ -1,719 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all; 
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodasource is
-  generic(
-    SYNC_MODE : integer range 0 to 1 := c_NO;   --use the RX clock for internal logic and transmission. Should be NO for soda tests!
-    USE_125_MHZ : integer := c_NO;
-    CLOCK_FREQUENCY : integer := 100;
-    NUM_INTERFACES : integer := 2
-    );
-  port(
-    --Clocks
-    CLK_GPLL_LEFT  : in std_logic;  --Clock Manager 1/(2468), 125 MHz
-    CLK_GPLL_RIGHT : in std_logic;  --Clock Manager 2/(2468), 200 MHz  <-- MAIN CLOCK for FPGA
-    CLK_PCLK_LEFT  : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-    CLK_PCLK_RIGHT : in std_logic;  --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
-    --Trigger
-    --TRIGGER_LEFT  : in std_logic;       --left side trigger input from fan-out
-    --TRIGGER_RIGHT : in std_logic;       --right side trigger input from fan-out
-    --Serdes Clocks - do not use
-    --CLK_SERDES_INT_LEFT  : in  std_logic;  --Clock Manager 1/(1357), off, 125 MHz possible
-    --CLK_SERDES_INT_RIGHT : in  std_logic;  --Clock Manager 2/(1357), 200 MHz, only in case of problems
-
-    --serdes I/O - connect as you like, no real use
-    SERDES_ADDON_TX      : out std_logic_vector(15 downto 0);
-    SERDES_ADDON_RX      : in  std_logic_vector(15 downto 0);
-
-    --Inter-FPGA Communication
-    FPGA5_COMM : inout std_logic_vector(11 downto 0);
-                                                      --Bit 0/1 input, serial link RX active
-                                                      --Bit 2/3 output, serial link TX active
-                                                      --others yet undefined
-    --Connection to AddOn
-    LED_LINKOK : out std_logic_vector(6 downto 1);
-    LED_RX     : out std_logic_vector(6 downto 1); 
-    LED_TX     : out std_logic_vector(6 downto 1);
-    SFP_MOD0   : in  std_logic_vector(6 downto 1);
-    SFP_TXDIS  : out std_logic_vector(6 downto 1); 
-    SFP_LOS    : in  std_logic_vector(6 downto 1);
-    --SFP_MOD1   : inout std_logic_vector(6 downto 1); 
-    --SFP_MOD2   : inout std_logic_vector(6 downto 1); 
-    --SFP_RATESEL : out std_logic_vector(6 downto 1);
-    --SFP_TXFAULT : in  std_logic_vector(6 downto 1);
-
-    --Flash ROM & Reboot
-    FLASH_CLK  : out   std_logic;
-    FLASH_CS   : out   std_logic;
-    FLASH_DIN  : out   std_logic;
-    FLASH_DOUT : in    std_logic;
-    PROGRAMN   : out   std_logic;                     --reboot FPGA
-
-    --Misc
-    TEMPSENS   : inout std_logic;       --Temperature Sensor
-    CODE_LINE  : in    std_logic_vector(1 downto 0);
-    LED_GREEN  : out   std_logic;
-    LED_ORANGE : out   std_logic;
-    LED_RED    : out   std_logic;
-    LED_YELLOW : out   std_logic;
-    SUPPL      : in    std_logic;       --terminated diff pair, PCLK, Pads
-
-    --Test Connectors
-    TEST_LINE : out std_logic_vector(15 downto 0)
-    );
-
-
-  attribute syn_useioff                  : boolean;
-  --no IO-FF for LEDs relaxes timing constraints
-  attribute syn_useioff of LED_GREEN     : signal is false;
-  attribute syn_useioff of LED_ORANGE    : signal is false;
-  attribute syn_useioff of LED_RED       : signal is false;
-  attribute syn_useioff of LED_YELLOW    : signal is false;
-  attribute syn_useioff of TEMPSENS      : signal is false;
-  attribute syn_useioff of PROGRAMN      : signal is false;
-  attribute syn_useioff of CODE_LINE     : signal is false;
-  attribute syn_useioff of LED_LINKOK    : signal is false;
-  attribute syn_useioff of LED_TX        : signal is false;
-  attribute syn_useioff of LED_RX        : signal is false;
-  attribute syn_useioff of SFP_MOD0      : signal is false;
-  attribute syn_useioff of SFP_TXDIS     : signal is false;
-  attribute syn_useioff of SFP_LOS       : signal is false;
-  attribute syn_useioff of TEST_LINE  : signal is false;
-
-  --important signals _with_ IO-FF
-  attribute syn_useioff of FLASH_CLK  : signal is true;
-  attribute syn_useioff of FLASH_CS   : signal is true;
-  attribute syn_useioff of FLASH_DIN  : signal is true;
-  attribute syn_useioff of FLASH_DOUT : signal is true;
-  attribute syn_useioff of FPGA5_COMM : signal is true;
-
-
-end entity;
-
-architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
-  --Constants
-  constant REGIO_NUM_STAT_REGS : integer := 0;
-  constant REGIO_NUM_CTRL_REGS : integer := 2;
-
-  attribute syn_keep     : boolean;
-  attribute syn_preserve : boolean;
-
-  constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
-  
-  --Clock / Reset
-  signal clk_sys_i                : std_logic;  --clock for main logic, 100 MHz, via Clock Manager and internal PLL
---   signal clk_200_i                : std_logic;  --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
-  signal pll_lock                 : std_logic;  --Internal PLL locked. E.g. used to reset all internal logic.
-  signal clear_i                  : std_logic;
-  signal reset_i                  : std_logic;
-  signal GSR_N                    : std_logic;
-  attribute syn_keep of GSR_N     : signal is true;
-  attribute syn_preserve of GSR_N : signal is true;
-  signal clk_sys_internal         : std_logic;
-  signal clk_raw_internal         : std_logic;
-  signal rx_clock_half             : std_logic;
-  signal rx_clock_full             : std_logic;
-  signal clk_tdc                  : std_logic;
-  signal time_counter, time_counter2 : unsigned(31 downto 0);
-  --Media Interface
-  signal med_stat_op        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-  signal med_ctrl_op        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-  signal med_stat_debug     : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-  signal med_ctrl_debug     : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
-  signal med_data_out       : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-  signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-  signal med_dataready_out  : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-  signal med_read_out       : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-  signal med_data_in        : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
-  signal med_packet_num_in  : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
-  signal med_dataready_in   : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-  signal med_read_in        : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
-  --Slow Control channel
-  signal common_stat_reg        : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-  signal common_ctrl_reg        : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-  signal stat_reg               : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
-  signal ctrl_reg               : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
-  signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
-  signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
-  signal stat_reg_strobe        : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
-  signal ctrl_reg_strobe        : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
-  --RegIO
-  signal my_address             : std_logic_vector (15 downto 0);
-  signal regio_addr_out         : std_logic_vector (15 downto 0);
-  signal regio_read_enable_out  : std_logic;
-  signal regio_write_enable_out : std_logic;
-  signal regio_data_out         : std_logic_vector (31 downto 0);
-  signal regio_data_in          : std_logic_vector (31 downto 0);
-  signal regio_dataready_in     : std_logic;
-  signal regio_no_more_data_in  : std_logic;
-  signal regio_write_ack_in     : std_logic;
-  signal regio_unknown_addr_in  : std_logic;
-  signal regio_timeout_out      : std_logic;
-
-  --Timer
-  signal global_time         : std_logic_vector(31 downto 0);
-  signal local_time          : std_logic_vector(7 downto 0);
-  signal time_since_last_trg : std_logic_vector(31 downto 0);
-  signal timer_ticks         : std_logic_vector(1 downto 0);
-
-  --Flash
-  signal spimem_read_en          : std_logic;
-  signal spimem_write_en         : std_logic;
-  signal spimem_data_in          : std_logic_vector(31 downto 0);
-  signal spimem_addr             : std_logic_vector(8 downto 0);
-  signal spimem_data_out         : std_logic_vector(31 downto 0);
-  signal spimem_dataready_out    : std_logic;
-  signal spimem_no_more_data_out : std_logic;
-  signal spimem_unknown_addr_out : std_logic;
-  signal spimem_write_ack_out    : std_logic;
-
-  signal sci1_ack      : std_logic;
-  signal sci1_write    : std_logic;
-  signal sci1_read     : std_logic;
-  signal sci1_data_in  : std_logic_vector(7 downto 0);
-  signal sci1_data_out : std_logic_vector(7 downto 0);
-  signal sci1_addr     : std_logic_vector(8 downto 0);  
-  signal sci2_ack      : std_logic;
-  signal sci2_nack     : std_logic;
-  signal sci2_write    : std_logic;
-  signal sci2_read     : std_logic;
-  signal sci2_data_in  : std_logic_vector(7 downto 0);
-  signal sci2_data_out : std_logic_vector(7 downto 0);
-  signal sci2_addr     : std_logic_vector(8 downto 0);  
-
-  --TDC
-  signal hit_in_i : std_logic_vector(63 downto 0);
-      
-  signal soda_rx_clock_half : std_logic;
-  signal soda_rx_clock_full : std_logic;
-  signal tx_dlm_i          : std_logic;
-  signal rx_dlm_i          : std_logic;
-  signal tx_dlm_word       : std_logic_vector(7 downto 0);
-  signal rx_dlm_word       : std_logic_vector(7 downto 0);
-
-	--SODA
-	signal rst_S							: std_logic;
-	signal clk_S							: std_logic;
-	signal enable_S						: std_logic := '0';
-	signal soda_cmd_word_S				: std_logic_vector(31 downto 0)	:= (others => '0');
-	signal soda_cmd_strobe_S			: std_logic := '0';
-	signal SOS_S							: std_logic := '0';
-	signal super_burst_nr_S				: std_logic_vector(30 downto 0)	:= (others => '0');		-- from super-burst-nr-generator
-	signal SOB_S							: std_logic := '0';
-	signal dlm_word_S						: std_logic_vector(7 downto 0)	:= (others => '0');
-	signal dlm_valid_S					: std_logic;
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-  GSR_N <= pll_lock;
-
-  THE_RESET_HANDLER : trb_net_reset_handler
-    generic map(
-      RESET_DELAY => x"FEEE"
-      )
-    port map(
-      CLEAR_IN      => '0',              -- reset input (high active, async)
-      CLEAR_N_IN    => '1',              -- reset input (low active, async)
-      CLK_IN        => clk_raw_internal, -- raw master clock, NOT from PLL/DLL!
-      SYSCLK_IN     => clk_sys_i,        -- PLL/DLL remastered clock
-      PLL_LOCKED_IN => pll_lock,         -- master PLL lock signal (async)
-      RESET_IN      => '0',              -- general reset signal (SYSCLK)
-      TRB_RESET_IN  => med_stat_op(13),  -- TRBnet reset signal (SYSCLK)
-      CLEAR_OUT     => clear_i,          -- async reset out, USE WITH CARE!
-      RESET_OUT     => reset_i,          -- synchronous reset out (SYSCLK)
-      DEBUG_OUT     => open
-      );  
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
-  THE_MAIN_PLL : pll_in200_out100
-    port map(
-      CLK   => CLK_GPLL_RIGHT,
-      CLKOP => clk_sys_internal,
-      CLKOK => clk_raw_internal,
-      LOCK  => pll_lock
-      );
-end generate;      
-
-gen_125 : if USE_125_MHZ = c_YES generate
-  clk_sys_internal <= CLK_GPLL_LEFT;
-  clk_raw_internal <= CLK_GPLL_LEFT;
-end generate; 
-
-gen_sync_clocks : if SYNC_MODE = c_YES generate
-  clk_sys_i <= rx_clock_half;
---   clk_200_i <= rx_clock_full;
-end generate;
-
-gen_local_clocks : if SYNC_MODE = c_NO generate
-  clk_sys_i <= clk_sys_internal;
---   clk_200_i <= clk_raw_internal;
-end generate;
-
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
-  THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
-    generic map(
-      SERDES_NUM  => 1,     --number of serdes in quad
-      EXT_CLOCK   => c_NO,  --use internal clock
-      USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
-      USE_125_MHZ => USE_125_MHZ,
-      USE_CTC     => c_NO,
-      USE_SLAVE   => SYNC_MODE
-      )      
-    port map(
-      CLK                => clk_raw_internal,
-      SYSCLK             => clk_sys_i,
-      RESET              => reset_i,
-      CLEAR              => clear_i,
-      CLK_EN             => '1',
-      --Internal Connection
-      MED_DATA_IN        => med_data_out(15 downto 0),
-      MED_PACKET_NUM_IN  => med_packet_num_out(2 downto 0),
-      MED_DATAREADY_IN   => med_dataready_out(0),
-      MED_READ_OUT       => med_read_in(0),
-      MED_DATA_OUT       => med_data_in(15 downto 0),
-      MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
-      MED_DATAREADY_OUT  => med_dataready_in(0),
-      MED_READ_IN        => med_read_out(0),
-      REFCLK2CORE_OUT    => open,
-      CLK_RX_HALF_OUT    => rx_clock_half,
-      CLK_RX_FULL_OUT    => rx_clock_full,
-      
-      --SFP Connection
-      SD_RXD_P_IN        => SERDES_ADDON_RX(2),
-      SD_RXD_N_IN        => SERDES_ADDON_RX(3),
-      SD_TXD_P_OUT       => SERDES_ADDON_TX(2),
-      SD_TXD_N_OUT       => SERDES_ADDON_TX(3),
-      SD_REFCLK_P_IN     => '0',
-      SD_REFCLK_N_IN     => '0',
-      SD_PRSNT_N_IN      => FPGA5_COMM(0),
-      SD_LOS_IN          => FPGA5_COMM(0),
-      SD_TXDIS_OUT       => FPGA5_COMM(2),
-      
-      SCI_DATA_IN        => sci1_data_in,
-      SCI_DATA_OUT       => sci1_data_out,
-      SCI_ADDR           => sci1_addr,
-      SCI_READ           => sci1_read,
-      SCI_WRITE          => sci1_write,
-      SCI_ACK            => sci1_ack,        
-      -- Status and control port
-      STAT_OP            => med_stat_op(15 downto 0),
-      CTRL_OP            => med_ctrl_op(15 downto 0),
-      STAT_DEBUG         => med_stat_debug(63 downto 0),
-      CTRL_DEBUG         => (others => '0')
-      );
-
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
---   THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
---     generic map(
---       REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,  --4,    --16 stat reg
---       REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,  --3,    --8 cotrol reg
---       ADDRESS_MASK              => x"FFFF",
---       BROADCAST_BITMASK         => x"FF",
---       BROADCAST_SPECIAL_ADDR    => x"45",
---       REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
---       REGIO_HARDWARE_VERSION    => x"91000000",
---       REGIO_INIT_ADDRESS        => x"f306",
---       REGIO_USE_VAR_ENDPOINT_ID => c_YES,
---       CLOCK_FREQUENCY           => 100,
---       TIMING_TRIGGER_RAW        => c_YES,
---       --Configure data handler
---       DATA_INTERFACE_NUMBER     => 1,
---       DATA_BUFFER_DEPTH         => 9,  --13
---       DATA_BUFFER_WIDTH         => 32,
---       DATA_BUFFER_FULL_THRESH   => 256,
---       TRG_RELEASE_AFTER_DATA    => c_YES,
---       HEADER_BUFFER_DEPTH       => 9,
---       HEADER_BUFFER_FULL_THRESH => 256
---       )
---     port map(
---       CLK                => clk_sys_i,
---       RESET              => reset_i,
---       CLK_EN             => '1',
---       MED_DATAREADY_OUT  => med_dataready_out,
---       MED_DATA_OUT       => med_data_out,
---       MED_PACKET_NUM_OUT => med_packet_num_out,
---       MED_READ_IN        => med_read_in,
---       MED_DATAREADY_IN   => med_dataready_in,
---       MED_DATA_IN        => med_data_in,
---       MED_PACKET_NUM_IN  => med_packet_num_in,
---       MED_READ_OUT       => med_read_out,
---       MED_STAT_OP_IN     => med_stat_op,
---       MED_CTRL_OP_OUT    => med_ctrl_op,
--- 
---       --Timing trigger in
---       TRG_TIMING_TRG_RECEIVED_IN  => '0',
---       --LVL1 trigger to FEE
---       LVL1_TRG_DATA_VALID_OUT     => open,
---       LVL1_VALID_TIMING_TRG_OUT   => open,
---       LVL1_VALID_NOTIMING_TRG_OUT => open,
---       LVL1_INVALID_TRG_OUT        => open,
--- 
---       LVL1_TRG_TYPE_OUT        => open,
---       LVL1_TRG_NUMBER_OUT      => open,
---       LVL1_TRG_CODE_OUT        => open,
---       LVL1_TRG_INFORMATION_OUT => open,
---       LVL1_INT_TRG_NUMBER_OUT  => open,
--- 
---       --Information about trigger handler errors
---       TRG_MULTIPLE_TRG_OUT     => open,
---       TRG_TIMEOUT_DETECTED_OUT => open,
---       TRG_SPURIOUS_TRG_OUT     => open,
---       TRG_MISSING_TMG_TRG_OUT  => open,
---       TRG_SPIKE_DETECTED_OUT   => open,
--- 
---       --Response from FEE
---       FEE_TRG_RELEASE_IN(0)       => '1',
---       FEE_TRG_STATUSBITS_IN       => (others => '0'),
---       FEE_DATA_IN                 => (others => '0'),
---       FEE_DATA_WRITE_IN(0)        => '0',
---       FEE_DATA_FINISHED_IN(0)     => '1',
---       FEE_DATA_ALMOST_FULL_OUT(0) => open,
--- 
---       -- Slow Control Data Port
---       REGIO_COMMON_STAT_REG_IN           => common_stat_reg,  --0x00
---       REGIO_COMMON_CTRL_REG_OUT          => common_ctrl_reg,  --0x20
---       REGIO_COMMON_STAT_STROBE_OUT       => common_stat_reg_strobe,
---       REGIO_COMMON_CTRL_STROBE_OUT       => common_ctrl_reg_strobe,
---       REGIO_STAT_REG_IN                  => stat_reg,         --start 0x80
---       REGIO_CTRL_REG_OUT                 => ctrl_reg,         --start 0xc0
---       REGIO_STAT_STROBE_OUT              => stat_reg_strobe,
---       REGIO_CTRL_STROBE_OUT              => ctrl_reg_strobe,
---       REGIO_VAR_ENDPOINT_ID(1 downto 0)  => CODE_LINE,
---       REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
--- 
---       BUS_ADDR_OUT         => regio_addr_out,
---       BUS_READ_ENABLE_OUT  => regio_read_enable_out,
---       BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
---       BUS_DATA_OUT         => regio_data_out,
---       BUS_DATA_IN          => regio_data_in,
---       BUS_DATAREADY_IN     => regio_dataready_in,
---       BUS_NO_MORE_DATA_IN  => regio_no_more_data_in,
---       BUS_WRITE_ACK_IN     => regio_write_ack_in,
---       BUS_UNKNOWN_ADDR_IN  => regio_unknown_addr_in,
---       BUS_TIMEOUT_OUT      => regio_timeout_out,
---       ONEWIRE_INOUT        => TEMPSENS,
---       ONEWIRE_MONITOR_OUT  => open,
--- 
---       TIME_GLOBAL_OUT         => global_time,
---       TIME_LOCAL_OUT          => local_time,
---       TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
---       TIME_TICKS_OUT          => timer_ticks,
--- 
---       STAT_DEBUG_IPU              => open, 
---       STAT_DEBUG_1                => open,
---       STAT_DEBUG_2                => open,
---       STAT_DEBUG_DATA_HANDLER_OUT => open,
---       STAT_DEBUG_IPU_HANDLER_OUT  => open,
---       STAT_TRIGGER_OUT            => open,
---       CTRL_MPLEX                  => (others => '0'), 
---       IOBUF_CTRL_GEN              => (others => '0'),
---       STAT_ONEWIRE                => open,
---       STAT_ADDR_DEBUG             => open,
---       DEBUG_LVL1_HANDLER_OUT      => open
---       );
-
-
----------------------------------------------------------------------------
--- Hub 
----------------------------------------------------------------------------
-
-THE_HUB : trb_net16_hub_base
-  generic map (
-    HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),
-    IBUF_SECURE_MODE  => c_YES,
-    MII_NUMBER        => NUM_INTERFACES,
-    MII_IS_UPLINK     => (0 => 1, others => 0),
-    MII_IS_DOWNLINK   => (0 => 0, others => 1),
-    MII_IS_UPLINK_ONLY=> (0 => 1, others => 0),
-    INT_NUMBER        => 0,
-    USE_ONEWIRE       => c_YES,
-    COMPILE_TIME      => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
---    COMPILE_TIME      => VERSION_NUMBER_TIME, 
-    HARDWARE_VERSION  => x"91003200",
-    INIT_ENDPOINT_ID  => x"0000",
-    INIT_ADDRESS      => x"F355",
-    USE_VAR_ENDPOINT_ID => c_YES,
-    BROADCAST_SPECIAL_ADDR => x"45",
-    CLOCK_FREQUENCY   => CLOCK_FREQUENCY
-    )
-  port map (
-    CLK    => clk_sys_i,
-    RESET  => reset_i,
-    CLK_EN => '1',
-
-    --Media interfacces
-    MED_DATAREADY_OUT(NUM_INTERFACES*1-1 downto 0)   => med_dataready_out,
-    MED_DATA_OUT(NUM_INTERFACES*16-1 downto 0)       => med_data_out,
-    MED_PACKET_NUM_OUT(NUM_INTERFACES*3-1 downto 0)  => med_packet_num_out,
-    MED_READ_IN(NUM_INTERFACES*1-1 downto 0)         => med_read_in,
-    MED_DATAREADY_IN(NUM_INTERFACES*1-1 downto 0)    => med_dataready_in,
-    MED_DATA_IN(NUM_INTERFACES*16-1 downto 0)        => med_data_in,
-    MED_PACKET_NUM_IN(NUM_INTERFACES*3-1 downto 0)   => med_packet_num_in,
-    MED_READ_OUT(NUM_INTERFACES*1-1 downto 0)        => med_read_out,
-    MED_STAT_OP(NUM_INTERFACES*16-1 downto 0)        => med_stat_op,
-    MED_CTRL_OP(NUM_INTERFACES*16-1 downto 0)        => med_ctrl_op,
-
-    COMMON_STAT_REGS                => common_stat_reg,
-    COMMON_CTRL_REGS                => common_ctrl_reg,
-    MY_ADDRESS_OUT                  => open,
-    --REGIO INTERFACE
-    REGIO_ADDR_OUT                  => regio_addr_out,
-    REGIO_READ_ENABLE_OUT           => regio_read_enable_out,
-    REGIO_WRITE_ENABLE_OUT          => regio_write_enable_out,
-    REGIO_DATA_OUT                  => regio_data_out,
-    REGIO_DATA_IN                   => regio_data_in,
-    REGIO_DATAREADY_IN              => regio_dataready_in,
-    REGIO_NO_MORE_DATA_IN           => regio_no_more_data_in,
-    REGIO_WRITE_ACK_IN              => regio_write_ack_in,
-    REGIO_UNKNOWN_ADDR_IN           => regio_unknown_addr_in,
-    REGIO_TIMEOUT_OUT               => regio_timeout_out,
-    REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
-    REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-    ONEWIRE                         => TEMPSENS,
-    ONEWIRE_MONITOR_OUT             => open,
-    --Status ports (for debugging)
-    MPLEX_CTRL            => (others => '0'),
-    CTRL_DEBUG            => (others => '0'),
-    STAT_DEBUG            => open
-    );
-
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
-  THE_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER    => 3,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 9,       1 => 9,       2 => 9,       others => 0)
-      )
-    port map(
-      CLK   => clk_sys_i,
-      RESET => reset_i,
-
-      DAT_ADDR_IN          => regio_addr_out,
-      DAT_DATA_IN          => regio_data_out,
-      DAT_DATA_OUT         => regio_data_in,
-      DAT_READ_ENABLE_IN   => regio_read_enable_out,
-      DAT_WRITE_ENABLE_IN  => regio_write_enable_out,
-      DAT_TIMEOUT_IN       => regio_timeout_out,
-      DAT_DATAREADY_OUT    => regio_dataready_in,
-      DAT_WRITE_ACK_OUT    => regio_write_ack_in,
-      DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
-      DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
-    --Bus Handler (SPI Memory)
-      BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
-      BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
-      BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
-      BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
-      BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
-      BUS_TIMEOUT_OUT(0)                  => open,
-      BUS_DATA_IN(0*32+31 downto 0*32)    => spimem_data_out,
-      BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
-      BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
-      BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
-      BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
-
-
-      --SCI first Media Interface
-      BUS_READ_ENABLE_OUT(1)              => sci1_read,
-      BUS_WRITE_ENABLE_OUT(1)             => sci1_write,
-      BUS_DATA_OUT(1*32+7 downto 1*32)    => sci1_data_in,
-      BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
-      BUS_ADDR_OUT(1*16+8 downto 1*16)    => sci1_addr,
-      BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
-      BUS_TIMEOUT_OUT(1)                  => open,
-      BUS_DATA_IN(1*32+7 downto 1*32)     => sci1_data_out,
-      BUS_DATAREADY_IN(1)                 => sci1_ack,
-      BUS_WRITE_ACK_IN(1)                 => sci1_ack,
-      BUS_NO_MORE_DATA_IN(1)              => '0', 
-      BUS_UNKNOWN_ADDR_IN(1)              => '0',
-      --SCI soda test Media Interface
-      BUS_READ_ENABLE_OUT(2)              => sci2_read,
-      BUS_WRITE_ENABLE_OUT(2)             => sci2_write,
-      BUS_DATA_OUT(2*32+7 downto 2*32)    => sci2_data_in,
-      BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
-      BUS_ADDR_OUT(2*16+8 downto 2*16)    => sci2_addr,
-      BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
-      BUS_TIMEOUT_OUT(2)                  => open,
-      BUS_DATA_IN(2*32+7 downto 2*32)     => sci2_data_out,
-      BUS_DATAREADY_IN(2)                 => sci2_ack,
-      BUS_WRITE_ACK_IN(2)                 => sci2_ack,
-      BUS_NO_MORE_DATA_IN(2)              => '0',
-      BUS_UNKNOWN_ADDR_IN(2)              => sci2_nack,
-      STAT_DEBUG => open
-      );
-
----------------------------------------------------------------------------
--- SPI / Flash 
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
-  port map(
-    CLK_IN               => clk_sys_i,
-    RESET_IN             => reset_i,
-    
-    BUS_ADDR_IN          => spimem_addr,
-    BUS_READ_IN          => spimem_read_en,
-    BUS_WRITE_IN         => spimem_write_en,
-    BUS_DATAREADY_OUT    => spimem_dataready_out,
-    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
-    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
-    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
-    BUS_DATA_IN          => spimem_data_in,
-    BUS_DATA_OUT         => spimem_data_out,
-    
-    DO_REBOOT_IN         => common_ctrl_reg(15),     
-    PROGRAMN             => PROGRAMN,
-    
-    SPI_CS_OUT           => FLASH_CS,
-    SPI_SCK_OUT          => FLASH_CLK,
-    SPI_SDO_OUT          => FLASH_DIN,
-    SPI_SDI_IN           => FLASH_DOUT
-    );
-
-      
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------      
-
-THE_SODA_SOURCE : entity work.med_ecp3_sfp_sync
-  generic map(
-    SERDES_NUM  => 0,    --number of serdes in quad
-    IS_SYNC_SLAVE => c_NO
-    )
-  port map(
-    CLK                => clk_raw_internal, --clk_200_i,
-    SYSCLK             => clk_sys_i,
-    RESET              => reset_i,
-    CLEAR              => clear_i,
-    --Internal Connection for TrbNet data -> not used a.t.m.
-    MED_DATA_IN        => med_data_out(31 downto 16),
-    MED_PACKET_NUM_IN  => med_packet_num_out(5 downto 3),
-    MED_DATAREADY_IN   => med_dataready_out(1),
-    MED_READ_OUT       => med_read_in(1),
-    MED_DATA_OUT       => med_data_in(31 downto 16),
-    MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),
-    MED_DATAREADY_OUT  => med_dataready_in(1),
-    MED_READ_IN        => med_read_out(1),
-    CLK_RX_HALF_OUT    => soda_rx_clock_half,
-    CLK_RX_FULL_OUT    => soda_rx_clock_full,
-    
-    RX_DLM             => rx_dlm_i,
-    RX_DLM_WORD        => rx_dlm_word,
-    TX_DLM             => tx_dlm_i,
-    TX_DLM_WORD        => tx_dlm_word,
-    --SFP Connection
-    SD_RXD_P_IN        => SERDES_ADDON_RX(0),
-    SD_RXD_N_IN        => SERDES_ADDON_RX(1),
-    SD_TXD_P_OUT       => SERDES_ADDON_TX(0),
-    SD_TXD_N_OUT       => SERDES_ADDON_TX(1),
-    SD_REFCLK_P_IN     => '0',
-    SD_REFCLK_N_IN     => '0',
-    SD_PRSNT_N_IN      => SFP_MOD0(1),
-    SD_LOS_IN          => SFP_LOS(1),
-    SD_TXDIS_OUT       => SFP_TXDIS(1),
-    
-    SCI_DATA_IN        => sci2_data_in,
-    SCI_DATA_OUT       => sci2_data_out,
-    SCI_ADDR           => sci2_addr,
-    SCI_READ           => sci2_read,
-    SCI_WRITE          => sci2_write,
-    SCI_ACK            => sci2_ack,  
-    SCI_NACK           => sci2_nack,
-    -- Status and control port
-    STAT_OP            => med_stat_op(31 downto 16),
-    CTRL_OP            => med_ctrl_op(31 downto 16),
-    STAT_DEBUG         => open,
-    CTRL_DEBUG         => (others => '0')
-   );      
-
-   
----------------------------------------------------------------------------
--- The Soda Source
----------------------------------------------------------------------------         
-  tx_dlm_i <= '0';
-  tx_dlm_word <= x"00";
-	 
-	
-	superburst_gen :  super_burst_generator
-		generic map(BURST_COUNT		=> 16)
-		port map(
-			SYSCLK					=>	clk_sys_i,	--clk_S,
-			RESET						=>	reset_i,		--rst_S,
-			CLEAR						=>	'0',
-			CLK_EN					=>	'0',
-			--Internal Connection
-			SODA_BURST_PULSE_IN	=>	SOB_S,
-			START_OF_SUPERBURST	=>	SOS_S,
-			SUPER_BURST_NR_OUT	=>	super_burst_nr_S
-		);
-
-	packet_builder : soda_packet_builder
-		port map(
-			SYSCLK					=>	clk_sys_i,	--clk_S,
-			RESET						=>	reset_i,		--rst_S,
-			CLEAR						=>	'0',
-			CLK_EN					=> '0',
-			--Internal Connection
-			SODA_CMD_STROBE_IN	=> soda_cmd_strobe_S,
-			START_OF_SUPERBURST	=> SOS_S,
-			SUPER_BURST_NR_IN		=> super_burst_nr_S,
-			SODA_CMD_WORD_IN		=> soda_cmd_word_S,
-			TX_DLM_OUT				=> dlm_valid_S,
-			TX_DLM_WORD_OUT		=> dlm_word_S
-		
-			);
-   
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
-  LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
-  LED_YELLOW <= '1';
-  LED_GREEN  <= not med_stat_op(9);
-  LED_RED    <= not (med_stat_op(10) or med_stat_op(11));
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------    
---  TEST_LINE(15 downto 0) <= (others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-  process
-    begin
-      wait until rising_edge(clk_sys_internal);
-      time_counter <= time_counter + 1;
-    end process;
-
-
-
-
-end architecture;
diff --git a/soda_source/trb3_periph_sodasource_constraints.lpf b/soda_source/trb3_periph_sodasource_constraints.lpf
deleted file mode 100644
index 2b9f3d2..0000000
--- a/soda_source/trb3_periph_sodasource_constraints.lpf
+++ /dev/null
@@ -1,53 +0,0 @@
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-
-#################################################################
-# Basic Settings
-#################################################################
-
-  SYSCONFIG MCCLK_FREQ = 20;
-
-  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-  
-#################################################################
-# Reset Nets
-#################################################################  
-GSR_NET NET "GSR_N";  
-
-
-
-
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-
-LOCATE COMP   "THE_SODA_SOURCE/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-
-REGION "MEDIA_UPLINK" "R90C95D" 13 25;
-REGION "MEDIA_DOWNLINK" "R90C120D" 25 35;
-REGION "REGION_SPI"   "R13C150D" 12 16 DEVSIZE;
-REGION "REGION_IOBUF" "R10C43D"  88 86 DEVSIZE;
-
-LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; 
-LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ;
-
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-LOCATE UGROUP "THE_SODA_SOURCE/media_interface_group" REGION "MEDIA_DOWNLINK" ;
-
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/SCI_DATA_OUT*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/sci*" 20 ns;
-MULTICYCLE FROM CELL "THE_SODA_SOURCE/sci*" 20 ns;
-MULTICYCLE TO CELL "THE_SODA_SOURCE/wa_pos*" 20 ns;
-
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-
diff --git a/soda_source/workdir/.gitignore b/soda_source/workdir/.gitignore
deleted file mode 100644
index 026f571..0000000
--- a/soda_source/workdir/.gitignore
+++ /dev/null
@@ -1,10 +0,0 @@
-*
-
-!*txt
-!pmi*ngo
-!tsmac*ngo
-!sgm*ngo
-!.gitignore
-
-run_options.txt
-
diff --git a/soda_source/workdir/pmi_ram_dpEbnonessdn208256208256.ngo b/soda_source/workdir/pmi_ram_dpEbnonessdn208256208256.ngo
deleted file mode 120000
index c8f247d..0000000
--- a/soda_source/workdir/pmi_ram_dpEbnonessdn208256208256.ngo
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn208256208256.ngo
\ No newline at end of file
diff --git a/soda_source/workdir/pmi_ram_dpEbnonessdn96649664.ngo b/soda_source/workdir/pmi_ram_dpEbnonessdn96649664.ngo
deleted file mode 120000
index e4f243b..0000000
--- a/soda_source/workdir/pmi_ram_dpEbnonessdn96649664.ngo
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/pmi_ram_dpEbnonessdn96649664.ngo
\ No newline at end of file
diff --git a/soda_source/workdir/serdes_ch4.txt b/soda_source/workdir/serdes_ch4.txt
deleted file mode 120000
index 0fdc84c..0000000
--- a/soda_source/workdir/serdes_ch4.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_ch4.txt
\ No newline at end of file
diff --git a/soda_source/workdir/serdes_full_ctc.txt b/soda_source/workdir/serdes_full_ctc.txt
deleted file mode 120000
index c3c2ef1..0000000
--- a/soda_source/workdir/serdes_full_ctc.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.txt
\ No newline at end of file
diff --git a/soda_source/workdir/serdes_gbe_0ch.txt b/soda_source/workdir/serdes_gbe_0ch.txt
deleted file mode 120000
index 5d0d4c0..0000000
--- a/soda_source/workdir/serdes_gbe_0ch.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.txt
\ No newline at end of file
diff --git a/soda_source/workdir/serdes_onboard_full.txt b/soda_source/workdir/serdes_onboard_full.txt
deleted file mode 120000
index 74ee4d8..0000000
--- a/soda_source/workdir/serdes_onboard_full.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.txt
\ No newline at end of file
diff --git a/soda_source/workdir/serdes_sync_0.txt b/soda_source/workdir/serdes_sync_0.txt
deleted file mode 120000
index 616aa00..0000000
--- a/soda_source/workdir/serdes_sync_0.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.txt
\ No newline at end of file
diff --git a/soda_source/workdir/serdes_sync_125_0.txt b/soda_source/workdir/serdes_sync_125_0.txt
deleted file mode 120000
index 11cb7c5..0000000
--- a/soda_source/workdir/serdes_sync_125_0.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_125_0.txt
\ No newline at end of file
diff --git a/soda_source/workdir/sfp_0_200_ctc.txt b/soda_source/workdir/sfp_0_200_ctc.txt
deleted file mode 120000
index 980cc4a..0000000
--- a/soda_source/workdir/sfp_0_200_ctc.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.txt
\ No newline at end of file
diff --git a/soda_source/workdir/sfp_0_200_int.txt b/soda_source/workdir/sfp_0_200_int.txt
deleted file mode 120000
index 9ca2088..0000000
--- a/soda_source/workdir/sfp_0_200_int.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.txt
\ No newline at end of file
diff --git a/soda_source/workdir/sfp_1_125_int.txt b/soda_source/workdir/sfp_1_125_int.txt
deleted file mode 120000
index 9cd19aa..0000000
--- a/soda_source/workdir/sfp_1_125_int.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.txt
\ No newline at end of file
diff --git a/soda_source/workdir/sfp_1_200_int.txt b/soda_source/workdir/sfp_1_200_int.txt
deleted file mode 120000
index 917cb3f..0000000
--- a/soda_source/workdir/sfp_1_200_int.txt
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.txt
\ No newline at end of file
diff --git a/soda_source/workdir/sgmii_gbe_pcs35.ngo b/soda_source/workdir/sgmii_gbe_pcs35.ngo
deleted file mode 120000
index 06f3878..0000000
--- a/soda_source/workdir/sgmii_gbe_pcs35.ngo
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii_gbe_pcs35/sgmii_gbe_pcs35.ngo
\ No newline at end of file
diff --git a/soda_source/workdir/tsmac35.ngo b/soda_source/workdir/tsmac35.ngo
deleted file mode 120000
index 51654ad..0000000
--- a/soda_source/workdir/tsmac35.ngo
+++ /dev/null
@@ -1 +0,0 @@
-../../../trbnet/gbe2_ecp3/ipcores_ecp3/tsmac35/tsmac35.ngo
\ No newline at end of file
diff --git a/soda_source_frankfurt.lpf b/soda_source_frankfurt.lpf
deleted file mode 100644
index 31d15d7..0000000
--- a/soda_source_frankfurt.lpf
+++ /dev/null
@@ -1,202 +0,0 @@
-rvl_alias "clk_100_osc" "clk_100_osc";
-RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; 
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP  "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP  "PCSA_REFCLKN" SITE "AC18";
-#LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AC10";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM_0" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM_1" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM_2" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM_3" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM_4" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM_5" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM_6" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM_7" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM_8" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM_9" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM_10" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM_11" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE_0" SITE "A5" ;
-LOCATE COMP "TEST_LINE_1" SITE "A6" ;
-LOCATE COMP "TEST_LINE_2" SITE "G8" ;
-LOCATE COMP "TEST_LINE_3" SITE "F9" ;
-LOCATE COMP "TEST_LINE_4" SITE "D9" ;
-LOCATE COMP "TEST_LINE_5" SITE "D10" ;
-LOCATE COMP "TEST_LINE_6" SITE "F10" ;
-LOCATE COMP "TEST_LINE_7" SITE "E10" ;
-LOCATE COMP "TEST_LINE_8" SITE "A8" ;
-LOCATE COMP "TEST_LINE_9" SITE "B8" ;
-LOCATE COMP "TEST_LINE_10" SITE "G10" ;
-LOCATE COMP "TEST_LINE_11" SITE "G9" ;
-LOCATE COMP "TEST_LINE_12" SITE "C9" ;
-LOCATE COMP "TEST_LINE_13" SITE "C10" ;
-LOCATE COMP "TEST_LINE_14" SITE "H10" ;
-LOCATE COMP "TEST_LINE_15" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK_1" SITE "P1" ;#DQLL0_0   #1
-LOCATE COMP "LED_RX_1" SITE "P2" ;#DQLL0_1   #3
-LOCATE COMP "LED_TX_1" SITE "T2" ;#DQLL0_2   #5
-LOCATE COMP "SFP_MOD0_1" SITE "U3" ;#DQLL0_3   #7
-#LOCATE COMP  "SFP_MOD1_1"    SITE "R1";     #DQLL0_4   #9
-#LOCATE COMP  "SFP_MOD2_1"    SITE "R2";     #DQLL0_5   #11
-#LOCATE COMP  "SFP_RATESEL_1" SITE "N3";     #DQSLL0_T  #13
-LOCATE COMP "SFP_TXDIS_1" SITE "P3" ;#DQSLL0_C  #15
-LOCATE COMP "SFP_LOS_1" SITE "P5" ;#DQLL0_6   #17
-#LOCATE COMP  "SFP_TXFAULT_1" SITE "P6";     #DQLL0_7   #19
-LOCATE COMP "LED_LINKOK_2" SITE "N5" ;#DQLL0_8   #21
-LOCATE COMP "LED_RX_2" SITE "N6" ;#DQLL0_9   #23
-LOCATE COMP "LED_TX_2" SITE "AC2" ;#DQLL2_0   #25
-LOCATE COMP "SFP_MOD0_2" SITE "AC3" ;#DQLL2_1   #27
-#LOCATE COMP  "SFP_MOD1_2"    SITE "AB1";    #DQLL2_2   #29
-#LOCATE COMP  "SFP_MOD2_2"    SITE "AC1";    #DQLL2_3   #31
-#LOCATE COMP  "SFP_RATESEL_2" SITE "AA1";    #DQLL2_4   #33
-LOCATE COMP "SFP_TXDIS_2" SITE "AA2" ;#DQLL2_5   #35
-LOCATE COMP "SFP_LOS_2" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
-#LOCATE COMP  "SFP_TXFAULT_2" SITE "W6";     #DQLL2_C   #39  #should be DQSLL2
-LOCATE COMP "LED_LINKOK_3" SITE "AD1" ;#DQLL3_0   #2
-LOCATE COMP "LED_RX_3" SITE "AD2" ;#DQLL3_1   #4
-LOCATE COMP "LED_TX_3" SITE "AB5" ;#DQLL3_2   #6
-LOCATE COMP "SFP_MOD0_3" SITE "AB6" ;#DQLL3_3   #8
-#LOCATE COMP  "SFP_MOD1_3"      SITE "AB3";    #DQLL3_4   #10
-#LOCATE COMP  "SFP_MOD2_3"      SITE "AB4";    #DQLL3_5   #12
-#LOCATE COMP  "SFP_RATESEL_3"   SITE "Y6";     #DQLL3_T   #14  #should be DQSLL3
-LOCATE COMP "SFP_TXDIS_3" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP "SFP_LOS_3" SITE "AA3" ;#DQLL3_6   #18
-#LOCATE COMP  "SFP_TXFAULT_3"   SITE "AA4";    #DQLL3_7   #20
-LOCATE COMP "LED_LINKOK_4" SITE "W8" ;#DQLL3_8   #22
-LOCATE COMP "LED_RX_4" SITE "W9" ;#DQLL3_9   #24
-LOCATE COMP "LED_TX_4" SITE "V1" ;#DQLL1_0   #26
-LOCATE COMP "SFP_MOD0_4" SITE "U2" ;#DQLL1_1   #28
-#LOCATE COMP  "SFP_MOD1_4"      SITE "T1";     #DQLL1_2   #30
-#LOCATE COMP  "SFP_MOD2_4"      SITE "U1";     #DQLL1_3   #32
-#LOCATE COMP  "SFP_RATESEL_4"   SITE "P4";     #DQLL1_4   #34
-LOCATE COMP "SFP_TXDIS_4" SITE "R3" ;#DQLL1_5   #36
-LOCATE COMP "SFP_LOS_4" SITE "T3" ;#DQSLL1_T  #38
-#LOCATE COMP  "SFP_TXFAULT_4"   SITE "R4";     #DQSLL1_C  #40
-LOCATE COMP "LED_LINKOK_5" SITE "W23" ;#DQLR1_0   #169
-LOCATE COMP "LED_RX_5" SITE "W22" ;#DQLR1_1   #171
-LOCATE COMP "LED_TX_5" SITE "AA25" ;#DQLR1_2   #173
-LOCATE COMP "SFP_MOD0_5" SITE "Y24" ;#DQLR1_3   #175
-#LOCATE COMP  "SFP_MOD1_5"     SITE "AA26";   #DQLR1_4   #177
-#LOCATE COMP  "SFP_MOD2_5"     SITE "AB26";   #DQLR1_5   #179
-#LOCATE COMP  "SFP_RATESEL_5"  SITE "W21";    #DQSLR1_T  #181
-LOCATE COMP "SFP_TXDIS_5" SITE "W20" ;#DQSLR1_C  #183
-LOCATE COMP "SFP_LOS_5" SITE "AA24" ;#DQLR1_6   #185
-#LOCATE COMP  "SFP_TXFAULT_5"  SITE "AA23";   #DQLR1_7   #187
-LOCATE COMP "LED_LINKOK_6" SITE "R25" ;#DQLR2_0   #170
-LOCATE COMP "LED_RX_6" SITE "R26" ;#DQLR2_1   #172
-LOCATE COMP "LED_TX_6" SITE "T25" ;#DQLR2_2   #174
-LOCATE COMP "SFP_MOD0_6" SITE "T24" ;#DQLR2_3   #176
-#LOCATE COMP  "SFP_MOD1_6"     SITE "T26";    #DQLR2_4   #178
-#LOCATE COMP  "SFP_MOD2_6"     SITE "U26";    #DQLR2_5   #180
-#LOCATE COMP  "SFP_RATESEL_6"  SITE "V21";    #DQSLR2_T  #182
-LOCATE COMP "SFP_TXDIS_6" SITE "V22" ;#DQSLR2_C  #184
-LOCATE COMP "SFP_LOS_6" SITE "U24" ;#DQLR2_6   #186
-#LOCATE COMP  "SFP_TXFAULT_6"  SITE "V24";    #DQLR2_7   #188
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
-#LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
-#LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
-#LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
-#LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE_1" SITE "AA20" ;
-LOCATE COMP "CODE_LINE_0" SITE "Y21" ;
-IOBUF PORT "CODE_LINE_1" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE_0" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-SYSCONFIG MCCLK_FREQ=20 ;
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-#REGION "MEDIA_UPLINK_REGION" "R90C95D" 20 25 DEVSIZE;
-#REGION "MEDIA_DOWNLINK_REGION" "R90C45D" 25 35 DEVSIZE;
-#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE;
-
-REGION "SPI_REGION" "R10C150D" 15 16 DEVSIZE;
-LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ;
-LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ;
-#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ;
-#LOCATE UGROUP "THE_SYNC_LINK/media_downlink_group" REGION "MEDIA_DOWNLINK_REGION" ;
-#USE SECONDARY NET "THE_MEDIA_UPLINK/rx_clock_half_c" "MEDIA_DOWNLINK_REGION" ;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ;
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-BLOCK PATH FROM CLKNET "clk_100_osc" TO CLKNET "THE_MEDIA_UPLINK/tmp_1";
-BLOCK PATH FROM CLKNET "clk_100_osc" TO CLKNET "THE_SYNC_LINK/sci_write_i_0";
-
-## IOBUF ALLPORTS ;
-#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-#USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
diff --git a/soda_source_groningen.lpf b/soda_source_groningen.lpf
deleted file mode 100644
index b3cabfd..0000000
--- a/soda_source_groningen.lpf
+++ /dev/null
@@ -1,200 +0,0 @@
-rvl_alias "clk_200_osc" "clk_200_osc";
-RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; 
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP  "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP  "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP  "PCSA_REFCLKN" SITE "AC18";
-#LOCATE COMP  "CLK_SERDES_INT_LEFT"  SITE "AC10";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0   #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1   #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2   #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3   #7
-#LOCATE COMP  "SFP_MOD1_1"    SITE "R1";     #DQLL0_4   #9
-#LOCATE COMP  "SFP_MOD2_1"    SITE "R2";     #DQLL0_5   #11
-#LOCATE COMP  "SFP_RATESEL_1" SITE "N3";     #DQSLL0_T  #13
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C  #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6   #17
-#LOCATE COMP  "SFP_TXFAULT_1" SITE "P6";     #DQLL0_7   #19
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8   #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9   #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0   #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1   #27
-#LOCATE COMP  "SFP_MOD1_2"    SITE "AB1";    #DQLL2_2   #29
-#LOCATE COMP  "SFP_MOD2_2"    SITE "AC1";    #DQLL2_3   #31
-#LOCATE COMP  "SFP_RATESEL_2" SITE "AA1";    #DQLL2_4   #33
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5   #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T   #37  #should be DQSLL2
-#LOCATE COMP  "SFP_TXFAULT_2" SITE "W6";     #DQLL2_C   #39  #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0   #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1   #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2   #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3   #8
-#LOCATE COMP  "SFP_MOD1_3"      SITE "AB3";    #DQLL3_4   #10
-#LOCATE COMP  "SFP_MOD2_3"      SITE "AB4";    #DQLL3_5   #12
-#LOCATE COMP  "SFP_RATESEL_3"   SITE "Y6";     #DQLL3_T   #14  #should be DQSLL3
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C   #16  #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6   #18
-#LOCATE COMP  "SFP_TXFAULT_3"   SITE "AA4";    #DQLL3_7   #20
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8   #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9   #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0   #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1   #28
-#LOCATE COMP  "SFP_MOD1_4"      SITE "T1";     #DQLL1_2   #30
-#LOCATE COMP  "SFP_MOD2_4"      SITE "U1";     #DQLL1_3   #32
-#LOCATE COMP  "SFP_RATESEL_4"   SITE "P4";     #DQLL1_4   #34
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5   #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T  #38
-#LOCATE COMP  "SFP_TXFAULT_4"   SITE "R4";     #DQSLL1_C  #40
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0   #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1   #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2   #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3   #175
-#LOCATE COMP  "SFP_MOD1_5"     SITE "AA26";   #DQLR1_4   #177
-#LOCATE COMP  "SFP_MOD2_5"     SITE "AB26";   #DQLR1_5   #179
-#LOCATE COMP  "SFP_RATESEL_5"  SITE "W21";    #DQSLR1_T  #181
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C  #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6   #185
-#LOCATE COMP  "SFP_TXFAULT_5"  SITE "AA23";   #DQLR1_7   #187
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0   #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1   #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2   #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3   #176
-#LOCATE COMP  "SFP_MOD1_6"     SITE "T26";    #DQLR2_4   #178
-#LOCATE COMP  "SFP_MOD2_6"     SITE "U26";    #DQLR2_5   #180
-#LOCATE COMP  "SFP_RATESEL_6"  SITE "V21";    #DQSLR2_T  #182
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C  #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6   #186
-#LOCATE COMP  "SFP_TXFAULT_6"  SITE "V24";    #DQLR2_7   #188
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP  "SPARE_LINE_0"    SITE "M25"; #194
-#LOCATE COMP  "SPARE_LINE_1"    SITE "M26"; #196
-#LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
-#LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
-#LOCATE COMP  "SPARE_LINE_4"    SITE "M3";  #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP  "SPARE_LINE_5"    SITE "M2";  #DQUL3_9_OUTOFLANE_FPGA__3 #71  
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-SYSCONFIG MCCLK_FREQ=20 ;
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-#LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-#REGION "MEDIA_UPLINK_REGION" "R90C95D" 20 25 DEVSIZE;
-#REGION "MEDIA_DOWNLINK_REGION" "R90C45D" 25 35 DEVSIZE;
-#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE;
-
-REGION "SPI_REGION" "R10C150D" 15 16 DEVSIZE;
-LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "SPI_REGION" ;
-LOCATE UGROUP "THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "SPI_REGION" ;
-#LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK_REGION" ;
-#LOCATE UGROUP "THE_SYNC_LINK/media_downlink_group" REGION "MEDIA_DOWNLINK_REGION" ;
-#USE SECONDARY NET "THE_MEDIA_UPLINK/rx_clock_half_c" "MEDIA_DOWNLINK_REGION" ;
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_SYNC_LINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/sci*" 25.000000 ns ;
-MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ;
-MULTICYCLE FROM CELL "THE_SYNC_LINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-BLOCK JTAGPATHS ;
-## IOBUF ALLPORTS ;
-#USE PRIMARY PURE NET "CLK_PCLK_LEFT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-#USE PRIMARY PURE NET "CLK_GPLL_RIGHT_c" QUADRANT_TL QUADRANT_TR QUADRANT_BL QUADRANT_BR ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
diff --git a/soda_source_probe.rvl b/soda_source_probe.rvl
deleted file mode 100644
index a1a1253..0000000
--- a/soda_source_probe.rvl
+++ /dev/null
@@ -1,370 +0,0 @@
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2015-03-18">
-    <IP Version="1_5_062609"/>
-    <Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_source"/>
-    <Core InsertDataset="0" Insert="1" Reveal_sig="2095382979" Name="trb3_periph_sodasource_LA0" ID="0">
-        <Setting>
-            <Clock SampleClk="clk_200_osc" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
-            <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="128"/>
-            <Capture Mode="0" MinSamplesPerTrig="8"/>
-            <Event CntEnable="0" MaxEventCnt="8"/>
-            <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_source_LA0_net"/>
-            <DistRAM Disable="0"/>
-        </Setting>
-        <Dataset Name="Base">
-            <Trace>
-                <Sig Type="SIG" Name="the_soda_source/soda_reset_s"/>
-                <Sig Type="SIG" Name="the_soda_source/soda_enable_s"/>
-                <Sig Type="SIG" Name="the_soda_source/dead_channel_s"/>
-                <Sig Type="SIG" Name="the_soda_source/report_error_s"/>
-                <Sig Type="SIG" Name="the_soda_source/downstream_error_s"/>
-                <Sig Type="SIG" Name="the_soda_source/channel_timeout_status_s"/>
-                <Bus Name="the_soda_source/ctrl_status_register_s">
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:4"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:5"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:6"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:7"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:8"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:9"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:10"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:11"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:12"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:13"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:14"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:15"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:16"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:17"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:18"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:19"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:20"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:21"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:22"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:23"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:24"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:25"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:26"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:27"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:28"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:29"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:30"/>
-                    <Sig Type="SIG" Name="the_soda_source/ctrl_status_register_s:31"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_soda_source/soda_burst_pulse_in"/>
-                <Bus Name="the_soda_source/super_burst_nr_s">
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:4"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:5"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:6"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:7"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:8"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:9"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:10"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:11"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:12"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:13"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:14"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:15"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:16"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:17"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:18"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:19"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:20"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:21"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:22"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:23"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:24"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:25"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:26"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:27"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:28"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:29"/>
-                    <Sig Type="SIG" Name="the_soda_source/super_burst_nr_s:30"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_soda_source/soda_cmd_strobe_s"/>
-                <Bus Name="the_soda_source/soda_cmd_word_s">
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:4"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:5"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:6"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:7"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:8"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:9"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:10"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:11"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:12"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:13"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:14"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:15"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:16"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:17"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:18"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:19"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:20"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:21"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:22"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:23"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:24"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:25"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:26"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:27"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:28"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:29"/>
-                    <Sig Type="SIG" Name="the_soda_source/soda_cmd_word_s:30"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_soda_source/soda_cmd_window_s"/>
-                <Sig Type="SIG" Name="the_sync_link/got_link_ready_i"/>
-                <Sig Type="SIG" Name="the_sync_link/rx_k"/>
-                <Bus Name="the_sync_link/rx_data">
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_data:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
-                <Bus Name="the_sync_link/rx_dlm_word">
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
-                </Bus>
-                <Bus Name="the_sync_link/rx_fsm_state">
-                    <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/rx_fsm_state:3"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_sync_link/tx_k"/>
-                <Bus Name="the_sync_link/tx_data">
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_data:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_sync_link/tx_dlm_preview_in"/>
-                <Sig Type="SIG" Name="the_sync_link/tx_dlm"/>
-                <Bus Name="the_sync_link/tx_dlm_word">
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
-                </Bus>
-                <Bus Name="the_sync_link/tx_fsm_state">
-                    <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/tx_fsm_state:3"/>
-                </Bus>
-                <Bus Name="the_sync_link/wa_position">
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:7"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:8"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:9"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:10"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:11"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:12"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:13"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:14"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position:15"/>
-                </Bus>
-                <Bus Name="the_sync_link/wa_position_rx">
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:0"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:1"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:2"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:3"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:4"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:5"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:6"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:7"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:8"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:9"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:10"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:11"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:12"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:13"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:14"/>
-                    <Sig Type="SIG" Name="the_sync_link/wa_position_rx:15"/>
-                </Bus>
-                <Bus Name="the_soda_source/packet_builder/build_packet_state_s">
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/build_packet_state_s:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/build_packet_state_s:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/build_packet_state_s:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/build_packet_state_s:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/build_packet_state_s:4"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_data_valid_s"/>
-                <Bus Name="the_soda_source/packet_builder/crc_datain_s">
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:4"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:5"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:6"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_datain_s:7"/>
-                </Bus>
-                <Bus Name="the_soda_source/packet_builder/crc_out_s">
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:4"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:5"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:6"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_out_s:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/crc_valid_s"/>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_pending_s"/>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_strobe_in"/>
-                <Bus Name="the_soda_source/packet_builder/soda_cmd_word_in">
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:4"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:5"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:6"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:7"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:8"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:9"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:10"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:11"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:12"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:13"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:14"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:15"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:16"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:17"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:18"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:19"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:20"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:21"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:22"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:23"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:24"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:25"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:26"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:27"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:28"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:29"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_word_in:30"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cycle_in"/>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/start_of_superburst"/>
-                <Bus Name="the_soda_source/packet_builder/super_burst_nr_in">
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:4"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:5"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:6"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:7"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:8"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:9"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:10"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:11"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:12"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:13"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:14"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:15"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:16"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:17"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:18"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:19"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:20"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:21"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:22"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:23"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:24"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:25"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:26"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:27"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:28"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:29"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/super_burst_nr_in:30"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_out"/>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_preview_out"/>
-                <Bus Name="the_soda_source/packet_builder/tx_dlm_word_out">
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:4"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:5"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:6"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/tx_dlm_word_out:7"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/wait4cycle_s"/>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_strobe_s"/>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_cmd_window_in"/>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_dlm_preview_s"/>
-                <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_valid_s"/>
-                <Bus Name="the_soda_source/packet_builder/soda_pkt_word_s">
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:4"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:5"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:6"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/soda_pkt_word_s:7"/>
-                </Bus>
-                <Bus Name="the_soda_source/packet_builder/cmd_window_state_s">
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/cmd_window_state_s:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/packet_builder/cmd_window_state_s:1"/>
-                </Bus>
-                <Sig Type="SIG" Name="the_soda_source/superburst_gen/soda_burst_pulse_in"/>
-                <Sig Type="SIG" Name="the_soda_source/superburst_gen/soda_cmd_window_out"/>
-                <Sig Type="SIG" Name="the_soda_source/superburst_gen/start_of_superburst_out"/>
-                <Bus Name="the_soda_source/superburst_gen/burst_counter_s">
-                    <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:0"/>
-                    <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:1"/>
-                    <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:2"/>
-                    <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:3"/>
-                    <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:4"/>
-                    <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:5"/>
-                    <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:6"/>
-                    <Sig Type="SIG" Name="the_soda_source/superburst_gen/burst_counter_s:7"/>
-                </Bus>
-            </Trace>
-            <Trigger>
-                <TU Serialbits="0" Type="0" ID="1" Sig="the_soda_source/start_of_superburst_s,"/>
-                <TU Serialbits="0" Type="0" ID="2" Sig="the_soda_source/packet_builder/soda_cmd_pending_s,"/>
-                <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
-                <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
-            </Trigger>
-        </Dataset>
-    </Core>
-</Project>
diff --git a/soft/README.txt b/soft/README.txt
deleted file mode 100644
index 1bb8803..0000000
--- a/soft/README.txt
+++ /dev/null
@@ -1 +0,0 @@
-The place for all Soda related scripts.
diff --git a/code/posedge_to_pulse.vhd b/source/posedge_to_pulse.vhd
similarity index 100%
rename from code/posedge_to_pulse.vhd
rename to source/posedge_to_pulse.vhd
diff --git a/code/soda_calibration_timer.vhd b/source/soda_calibration_timer.vhd
similarity index 99%
rename from code/soda_calibration_timer.vhd
rename to source/soda_calibration_timer.vhd
index bbd46f9..309acde 100644
--- a/code/soda_calibration_timer.vhd
+++ b/source/soda_calibration_timer.vhd
@@ -37,7 +37,7 @@ architecture Behavioral of soda_calibration_timer is
 	signal	calibration_timer_S		: std_logic_vector(15 downto 0)	:= (others => '0');		-- from super-burst-nr-generator
 
 begin
-
+
 	CALIBRATION_RUNNING	<=  calibration_running_S;
 
 	calibration_fsm_proc : process(SODACLK)
diff --git a/code/soda_client.vhd b/source/soda_client.vhd
similarity index 99%
rename from code/soda_client.vhd
rename to source/soda_client.vhd
index 498ccc8..5533471 100644
--- a/code/soda_client.vhd
+++ b/source/soda_client.vhd
@@ -30,7 +30,7 @@ entity soda_client is
 		SODA_READ_IN			: in	std_logic := '0';
 		SODA_WRITE_IN			: in	std_logic := '0';
 		SODA_ACK_OUT			: out	std_logic := '0';
-		LEDS_OUT       	   : out  std_logic_vector(3 downto 0);
+		LEDS_OUT       	   : out  std_logic_vector(3 downto 0);
 		LINK_DEBUG_IN			: in	std_logic_vector(31 downto 0)	:= (others => '0')
 	);
 end soda_client;
@@ -59,8 +59,8 @@ architecture Behavioral of soda_client is
 	signal buf_bus_data_out : std_logic_vector(31 downto 0);
 	signal ledregister_i		: std_logic_vector(31 downto 0);
 	signal tx_dlm_out_S		: std_logic;
-
---	debug
+
+--	debug
 	signal debug_status_S		: std_logic_vector(31 downto 0)	:= (others => '0');
 	signal debug_rx_cnt_S		: std_logic_vector(31 downto 0)	:= (others => '0');
 	signal debug_tx_cnt_S		: std_logic_vector(31 downto 0)	:= (others => '0');
@@ -80,20 +80,20 @@ begin
 			SUPER_BURST_NR_OUT			=> super_burst_nr_S,
 			SODA_CMD_VALID_OUT			=> soda_cmd_valid_S,
 			SODA_CMD_WORD_OUT				=> soda_cmd_word_S,
---			CRC_VALID_OUT					=> crc_valid_S,
+--			CRC_VALID_OUT					=> crc_valid_S,
 --			CRC_DATA_OUT					=> crc_data_S,
 			RX_DLM_IN						=> RX_DLM_IN,
 			RX_DLM_WORD_IN					=> RX_DLM_WORD_IN
 		);
 
-	reply_packet_builder : soda_reply_pkt_builder		
+	reply_packet_builder : soda_reply_pkt_builder		
 		port map(
 			SODACLK					=>	SODACLK,
 			RESET						=>	RESET,
 			CLEAR						=>	'0',
 			CLK_EN					=> CLK_EN,
 			--Internal Connection
-			LINK_PHASE_IN			=> LINK_PHASE_IN,
+			LINK_PHASE_IN			=> LINK_PHASE_IN,
 			START_OF_SUPERBURST	=> start_of_superburst_S,
 			SUPER_BURST_NR_IN		=> super_burst_nr_S,
 			SODA_CMD_STROBE_IN	=> soda_cmd_valid_S,
@@ -210,15 +210,15 @@ end process TRANSFORM;
 			end if;
 		end if;
 	end process THE_READ_REG_PROC;
-
---	debug signals
-	DEBUG_CLIENT : process(SODACLK)
-	begin
-		if( rising_edge(SODACLK) ) then
+
+--	debug signals
+	DEBUG_CLIENT : process(SODACLK)
+	begin
+		if( rising_edge(SODACLK) ) then
 			debug_status_S(0)		<= RESET;
 			debug_status_S(1)		<= CLEAR;
 			debug_status_S(2)		<= CLK_EN;
-			if   ( RESET = '1' ) then
+			if   ( RESET = '1' ) then
 				debug_rx_cnt_S		<= (others => '0');
 				debug_tx_cnt_S		<= (others => '0');
 			else
@@ -235,10 +235,10 @@ end process TRANSFORM;
 					debug_cmd_cnt_S	<= debug_cmd_cnt_S + 1;
 				end if;
 			end if;
-		end if; 
-	end process;
-
-	debug_status_S(31 downto 3)		<=	LINK_DEBUG_IN(31 downto 3);
+		end if; 
+	end process;
+
+	debug_status_S(31 downto 3)		<=	LINK_DEBUG_IN(31 downto 3);
 	TX_DLM_OUT								<= tx_dlm_out_S;
 -- output signals
 	LEDS_OUT									<= LEDregister_i(3 downto 0);
diff --git a/code/soda_components.vhd b/source/soda_components.vhd
similarity index 99%
rename from code/soda_components.vhd
rename to source/soda_components.vhd
index df80d96..54c2a74 100644
--- a/code/soda_components.vhd
+++ b/source/soda_components.vhd
@@ -94,6 +94,9 @@ package soda_components is
 	end component;
 
 	component soda_packet_handler
+		generic(
+			CLOCKSper25ns					: integer := 5 -- PS
+		);
 		port(
 			SODACLK							: in	std_logic; -- fabric clock
 			RESET								: in	std_logic; -- synchronous reset
@@ -105,6 +108,7 @@ package soda_components is
 			START_OF_CALIBRATION_OUT	: out std_logic	:= '0';
 			SODA_CMD_VALID_OUT			: out std_logic := '0';
 			SODA_CMD_WORD_OUT				: out std_logic_vector(30 downto 0) := (others => '0');
+			SODA_CYCLE_OUT				: out std_logic := '0'; -- PS
 			RX_DLM_IN						: in std_logic;
 			RX_DLM_WORD_IN					: in	std_logic_vector(7 downto 0) := (others => '0')
 		);
diff --git a/code/soda_d8crc8.vhd b/source/soda_d8crc8.vhd
similarity index 99%
rename from code/soda_d8crc8.vhd
rename to source/soda_d8crc8.vhd
index e47e2ad..5e4e333 100644
--- a/code/soda_d8crc8.vhd
+++ b/source/soda_d8crc8.vhd
@@ -31,12 +31,12 @@
 library ieee ;
 use ieee.std_logic_1164.all ;
 use ieee.std_logic_arith.all ;
-use ieee.std_logic_unsigned.all ;
-
+use ieee.std_logic_unsigned.all ;
+
 library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; 
+use work.trb_net16_hub_func.all; 
 use work.soda_components.all;
 
 entity soda_d8crc8 is
@@ -52,9 +52,9 @@ entity soda_d8crc8 is
 	);
 end soda_d8crc8;
 
-architecture behavioral of soda_d8crc8 is
-	
-	constant		crc_const: std_logic_vector(7 downto 0) := (others => '0');
+architecture behavioral of soda_d8crc8 is
+	
+	constant		crc_const: std_logic_vector(7 downto 0) := (others => '0');
 
 	signal crc_r				: std_logic_vector(7 downto 0);
 	signal crc_c				: std_logic_vector(7 downto 0);
diff --git a/code/soda_hub.vhd b/source/soda_hub.vhd
similarity index 95%
rename from code/soda_hub.vhd
rename to source/soda_hub.vhd
index 6739dba..f3e0276 100644
--- a/code/soda_hub.vhd
+++ b/source/soda_hub.vhd
@@ -49,7 +49,7 @@ architecture Behavioral of soda_hub is
 
 	--SODA
 	signal soda_reset_S						: std_logic;
-	signal soda_enable_S						: std_logic;
+	signal soda_enable_S						: std_logic;
 	
 	signal soda_cmd_word_S					: std_logic_vector(30 downto 0)	:= (others => '0');
 	signal soda_cmd_valid_S					: std_logic := '0';
@@ -89,7 +89,7 @@ architecture Behavioral of soda_hub is
 	signal common_timeout_status_S		: std_logic;
 	signal common_downstream_error_S		: std_logic;
 	signal common_report_error_S			: std_logic;
-
+
 	signal dead_channel_S					: t_HUB_BIT_ARRAY		:= (others => '0');
 
 	signal COMMON_CTRL_STATUS_register_S: std_logic_vector(31 downto 0);
@@ -115,9 +115,13 @@ architecture Behavioral of soda_hub is
 	signal ledregister_i			: std_logic_vector(31 downto 0)	:= (others => '0');
 --	signal txup_dlm_out_S		: std_logic;
 
+	signal SODA_CYCLE_S			: std_logic; -- PS
 begin
 	
 	hub_packet_handler : soda_packet_handler
+		generic map(
+			CLOCKSper25ns					=> 5 -- PS
+		)
 		port map(
 			SODACLK							=>	SODACLK,
 			RESET								=> RESET,
@@ -129,6 +133,7 @@ begin
 			SUPER_BURST_NR_OUT			=> super_burst_nr_S,
 			SODA_CMD_VALID_OUT			=> soda_cmd_valid_S,
 			SODA_CMD_WORD_OUT				=> soda_cmd_word_S,
+			SODA_CYCLE_OUT				=> SODA_CYCLE_S, -- PS
 			RX_DLM_IN						=> RXUP_DLM_IN,
 			RX_DLM_WORD_IN					=> RXUP_DLM_WORD_IN
 		);
@@ -154,7 +159,7 @@ begin
 
 	channel :for i in c_HUB_CHILDREN-1 downto 0 generate
 			
-	start_calibration_S(i)	<= send_start_calibration_S(i);
+start_calibration_S(i)	<= send_start_calibration_S(i);
 
 		packet_builder : soda_packet_builder
 			port map(
@@ -162,12 +167,12 @@ begin
 				RESET							=>	RESET,
 				--Internal Connection
 				LINK_PHASE_IN			=>	UPLINK_PHASE_IN,			--link_phase_S,	PL! 17092014    vergeten ??? of niet nodig ?
-				SODA_CYCLE_IN			=> '1',							-- 40MHz cycle is only required to sync superbursts at the source PL! 24022015
+				SODA_CYCLE_IN			=> SODA_CYCLE_S, -- PS	: 40MHz cycle also required for commands !!!
 				SODA_CMD_WINDOW_IN	=> '1',							-- soda-source determines the sending of a command; hub always copies
-				SODA_CMD_STROBE_IN	=> trb_cmd_strobe_S,			--soda_cmd_valid_S,	--TXsoda_cmd_valid_S(i),
+				SODA_CMD_STROBE_IN	=> soda_cmd_valid_S, -- PS: commands from source must be passed on !, my opinion:no need for hubs to send commands -- trb_cmd_strobe_S, -- PS: should be trb_cmd_strobe_sodaclk_S			--soda_cmd_valid_S,	--TXsoda_cmd_valid_S(i),
 				START_OF_SUPERBURST	=> start_of_superburst_S,	--TXstart_of_superburst_S(i),
 				SUPER_BURST_NR_IN		=> super_burst_nr_S,			--TXsuper_burst_nr_S(i)(30 downto 0),
-				SODA_CMD_WORD_IN		=> trb_cmd_word_S,			--soda_cmd_word_S,	--TXsoda_cmd_word_S(i)(30 downto 0),
+				SODA_CMD_WORD_IN		=> soda_cmd_word_S, -- PS: commands from source must be passed on !, my opinion:no need for hubs to send commands -- trb_cmd_word_S,			--soda_cmd_word_S,	--TXsoda_cmd_word_S(i)(30 downto 0),
 				EXPECTED_REPLY_OUT	=> expected_reply_S(i),
 				SEND_TIME_CAL_OUT		=>	send_start_calibration_S(i),
 				TX_DLM_PREVIEW_OUT	=>	TXDN_DLM_PREVIEW_OUT(i),
@@ -274,7 +279,7 @@ begin
 		--CTRL_STATUS_register_S(i)(0)					<= channel_timeout_status_S(i);
 
 	end generate;
-
+
 	soda_reset_S											<= (RESET or COMMON_CTRL_STATUS_register_S(31));
 	soda_enable_S											<= COMMON_CTRL_STATUS_register_S(30);
 	common_downstream_error_S			 				<= '1' when ((downstream_error_S(0)='1') or (downstream_error_S(1)='1') or (downstream_error_S(2)='1') or (downstream_error_S(3)='1'))
diff --git a/code/soda_packet_builder.vhd b/source/soda_packet_builder.vhd
similarity index 78%
rename from code/soda_packet_builder.vhd
rename to source/soda_packet_builder.vhd
index be45e14..75dfd48 100644
--- a/code/soda_packet_builder.vhd
+++ b/source/soda_packet_builder.vhd
@@ -1,68 +1,70 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 use ieee.std_logic_unsigned.all;
-
+
 library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; 
+use work.trb_net16_hub_func.all; 
 use work.soda_components.all;
-
-entity soda_packet_builder is
-	port(
-		SODACLK						: in	std_logic; -- fabric clock
-		RESET							: in	std_logic; -- synchronous reset
-		--Internal Connection
+
+entity soda_packet_builder is
+	port(
+		SODACLK						: in	std_logic; -- fabric clock
+		RESET							: in	std_logic; -- synchronous reset
+		--Internal Connection
 		LINK_PHASE_IN				: in	std_logic := '0';	-- even/odd fase needed to match 16-bit link stuff in trb
 		SODA_CYCLE_IN				: in	std_logic := '0';	-- 40MHz cycle for soda transmissions
 		SODA_CMD_WINDOW_IN		: in	std_logic := '0';
 		SODA_CMD_STROBE_IN		: in	std_logic := '0'; 
-		START_OF_SUPERBURST		: in	std_logic := '0';
-		SUPER_BURST_NR_IN			: in	std_logic_vector(30 downto 0) := (others => '0');
-		SODA_CMD_WORD_IN			: in	std_logic_vector(30 downto 0) := (others => '0');		--REGIO_CTRL_REG in trbnet handler is 32 bit
+		START_OF_SUPERBURST		: in	std_logic := '0';
+		SUPER_BURST_NR_IN			: in	std_logic_vector(30 downto 0) := (others => '0');
+		SODA_CMD_WORD_IN			: in	std_logic_vector(30 downto 0) := (others => '0');		--REGIO_CTRL_REG in trbnet handler is 32 bit
 		EXPECTED_REPLY_OUT		: out	std_logic_vector(7 downto 0) := (others => '0');
 		SEND_TIME_CAL_OUT			: out	std_logic := '0';
 		TX_DLM_PREVIEW_OUT		: out	std_logic := '0';	-- 
 		TX_DLM_OUT					: out	std_logic := '0';	-- 
-		TX_DLM_WORD_OUT			: out	std_logic_vector(7 downto 0) := (others => '0')
-	);
-end soda_packet_builder;
-
-architecture Behavioral of soda_packet_builder is
+		TX_DLM_WORD_OUT			: out	std_logic_vector(7 downto 0) := (others => '0')
+	);
+end soda_packet_builder;
+
+architecture Behavioral of soda_packet_builder is
 
 	signal	soda_cmd_pending_S		: std_logic	:= '0';
 	signal	soda_cmd_strobe_S			: std_logic	:= '0';
 	signal	soda_cmd_word_S			: std_logic_vector(30 downto 0)	:= (others => '0');		-- from slowcontrol
-	signal	soda_pkt_word_S			: std_logic_vector(7 downto 0)	:= (others => '0');
+	signal	soda_pkt_word_S			: std_logic_vector(7 downto 0)	:= (others => '0');
 	signal	soda_pkt_valid_S			: std_logic;
 	signal	reg1_soda_pkt_valid_S	: std_logic;
 --	signal	reg2_soda_pkt_valid_S	: std_logic;
 	signal	wait4cycle_S				: std_logic;
 	
 
-	signal	soc_S							: std_logic;
-	signal	eoc_S							: std_logic;
-	signal	crc_data_valid_S			: std_logic;
-	signal	crc_datain_S				: std_logic_vector(7 downto 0)	:= (others => '0');
-	signal	crc_out_S					: std_logic_vector(7 downto 0)	:= (others => '0');
-	signal	crc_valid_S					: std_logic;
-	
+	signal	soc_S							: std_logic;
+	signal	eoc_S							: std_logic;
+	signal	crc_data_valid_S			: std_logic;
+	signal	crc_datain_S				: std_logic_vector(7 downto 0)	:= (others => '0');
+	signal	crc_out_S					: std_logic_vector(7 downto 0)	:= (others => '0');
+	signal	crc_valid_S					: std_logic;
+	
 	type		build_packet_state_type is (	c_IDLE, c_ERROR, 
 													c_WAIT4CYCLE_B, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8,
 													c_WAIT4CYCLE_C, c_CMD1, c_CMD2, c_CMD3, c_CMD4, c_CMD5, c_CMD6, c_CMD7, c_CMD8
-													);	--	c_WAIT4BST1, c_WAIT4CMD1, 
-	signal	build_packet_state_S		: build_packet_state_type := c_IDLE;
+													);	--	c_WAIT4BST1, c_WAIT4CMD1, 
+	signal	build_packet_state_S		: build_packet_state_type := c_IDLE;
 	signal	build_packet_bits_S		: std_logic_vector(7 downto 0)	:= (others => '0');
-	
+	
 	type		cmd_window_state_type is (	c_WINDOW_IDLE, c_WAIT4WINDOW, c_START_CMD); 
-	signal	cmd_window_state_S		: cmd_window_state_type := c_WINDOW_IDLE;
+	signal	cmd_window_state_S		: cmd_window_state_type := c_WINDOW_IDLE;
 	
-
+
 	signal	soda_dlm_preview_S		: std_logic;
-
-begin
-
+
+	signal	PS_crc_out_S			: std_logic_vector(7 downto 0); -- PS
+	
+begin
+
 	tx_crc8: soda_d8crc8
 		port map(
 			CLOCK				=> SODACLK,
@@ -75,31 +77,31 @@ begin
 			CRC_VALID_OUT	=> crc_valid_S
 		);
 
-	soda_cmd_word_S			<= SODA_CMD_WORD_IN;
-	
+	soda_cmd_word_S			<= SODA_CMD_WORD_IN;
+	
 --	TX_DLM_PREVIEW_OUT		<= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (soda_cmd_strobe_S='1'))) or
 --													((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1'))) 
 --													else '0';
 	TX_DLM_PREVIEW_OUT		<= '1' when ((soda_dlm_preview_S='1') or ((wait4cycle_S='1') and (SODA_CYCLE_IN='1')))
 											else '0';
-	TX_DLM_OUT					<=	reg1_soda_pkt_valid_S;
+	TX_DLM_OUT					<=	reg1_soda_pkt_valid_S;
 	TX_DLM_WORD_OUT			<=	soda_pkt_word_S;
-
-
---	strobe_delay_proc : process(SODACLK)
---	begin
+
+
+--	strobe_delay_proc : process(SODACLK)
+--	begin
 --		if rising_edge(SODACLK) then
 --			if (RESET='1') then
 --				soda_cmd_pending_S	<= '0';
---			elsif (SODA_CMD_STROBE_IN='1') then
---				soda_cmd_pending_S	<= '1';
---			elsif (soda_cmd_strobe_S='1') then
+--			elsif (SODA_CMD_STROBE_IN='1') then
+--				soda_cmd_pending_S	<= '1';
+--			elsif (soda_cmd_strobe_S='1') then
 --				soda_cmd_pending_S	<= '0';
---			end if;
---		end if;
---	end process;
-
-
+--			end if;
+--		end if;
+--	end process;
+
+
 --	strobe_delivery_proc : process(SODACLK)
 --	begin
 --		if rising_edge(SODACLK) then
@@ -112,56 +114,56 @@ begin
 --			end if;
 --		end if;
 --	end process;
-
+
 	SODA_CMD_FLOWCTRL : process(SODACLK)
 	begin
 		if( rising_edge(SODACLK) ) then
 			if( RESET = '1' ) then
 				cmd_window_state_S	<= c_WINDOW_IDLE;
 				soda_cmd_pending_S	<= '0';
-				soda_cmd_strobe_S		<= '0';
+				soda_cmd_strobe_S		<= '0';
 			else
-				case cmd_window_state_S is
+				case cmd_window_state_S is
 					when c_WINDOW_IDLE =>
 						if (SODA_CMD_STROBE_IN='1') then
 							cmd_window_state_S	<= c_WAIT4WINDOW;
-							soda_cmd_pending_S	<= '1';
+							soda_cmd_pending_S	<= '1';
 						end if;
-					when c_WAIT4WINDOW =>
+					when c_WAIT4WINDOW =>
 						if ((SODA_CMD_WINDOW_IN ='1') and (soda_cmd_pending_S ='1')) then
 							cmd_window_state_S	<= c_START_CMD;
 							soda_cmd_strobe_S		<= '1';
-							soda_cmd_pending_S	<= '0';
+							soda_cmd_pending_S	<= '0';
 						end if;
-					when c_START_CMD =>
+					when c_START_CMD =>
 						cmd_window_state_S	<= c_WINDOW_IDLE;
 						soda_cmd_strobe_S		<= '0';
 						soda_cmd_pending_S	<= '0';
-					when others =>
-						cmd_window_state_S	<= c_WINDOW_IDLE;
+					when others =>
+						cmd_window_state_S	<= c_WINDOW_IDLE;
 						soda_cmd_strobe_S		<= '0';
 						soda_cmd_pending_S	<= '0';
-				end case;
+				end case;
 			end if;
 		end if;
-	end process SODA_CMD_FLOWCTRL;			
-
-	packet_fsm_proc : process(SODACLK)
-	begin
-		if rising_edge(SODACLK) then
-			if (RESET='1') then
-				build_packet_bits_S		<= x"00";
-				build_packet_state_S		<=	c_IDLE;
+	end process SODA_CMD_FLOWCTRL;			
+
+	packet_fsm_proc : process(SODACLK)
+	begin
+		if rising_edge(SODACLK) then
+			if (RESET='1') then
+				build_packet_bits_S		<= x"00";
+				build_packet_state_S		<=	c_IDLE;
 				soda_dlm_preview_S		<= '0';
 				soda_pkt_valid_S			<= '0';
 				reg1_soda_pkt_valid_S	<= '0';
---				reg2_soda_pkt_valid_S	<= '0';
+--				reg2_soda_pkt_valid_S	<= '0';
 				wait4cycle_S				<= '0';
 				soda_pkt_word_S			<= (others => '0');
-			else
+			else
 				soda_pkt_valid_S			<= reg1_soda_pkt_valid_S;
 --				reg2_soda_pkt_valid_S	<= reg1_soda_pkt_valid_S;
-				case build_packet_state_S is
+				case build_packet_state_S is
 --					when c_IDLE	=>
 --						if (START_OF_SUPERBURST='1') then
 --							soda_dlm_preview_S	<= '1';
@@ -221,7 +223,7 @@ begin
 							reg1_soda_pkt_valid_S		<= '0';
 							soda_pkt_word_S				<= (others=>'0');
 						end if;
-					when c_WAIT4CYCLE_B =>
+					when c_WAIT4CYCLE_B =>
 						wait4cycle_S						<= '1';
 						if ((SODA_CYCLE_IN='1') and (LINK_PHASE_IN = c_PHASE_H)) then
 							build_packet_bits_S			<= x"11";
@@ -241,49 +243,49 @@ begin
 --						soda_dlm_preview_S				<= '1';
 --						reg1_soda_pkt_valid_S			<= '1';
 --						soda_pkt_word_S					<= '1' & SUPER_BURST_NR_IN(30 downto 24);
-					when c_BST1	=>
+					when c_BST1	=>
 						build_packet_bits_S				<= x"12";
-						build_packet_state_S				<= c_BST2;
+						build_packet_state_S				<= c_BST2;
 						reg1_soda_pkt_valid_S			<= '0';
-					when c_BST2	=>
+					when c_BST2	=>
 						build_packet_bits_S				<= x"13";
-						build_packet_state_S				<= c_BST3;
+						build_packet_state_S				<= c_BST3;
 						reg1_soda_pkt_valid_S			<= '1';
 						soda_pkt_word_S					<= SUPER_BURST_NR_IN(23 downto 16);
-					when c_BST3	=>
+					when c_BST3	=>
 						build_packet_bits_S				<= x"14";
-						build_packet_state_S				<= c_BST4;
+						build_packet_state_S				<= c_BST4;
 						reg1_soda_pkt_valid_S			<= '0';
-					when c_BST4	=>
+					when c_BST4	=>
 						build_packet_bits_S				<= x"15";
-						build_packet_state_S				<= c_BST5;
+						build_packet_state_S				<= c_BST5;
 						reg1_soda_pkt_valid_S			<= '1';
 						soda_pkt_word_S					<= SUPER_BURST_NR_IN(15 downto 8);
-					when c_BST5	=>
+					when c_BST5	=>
 						build_packet_bits_S				<= x"16";
-						build_packet_state_S				<= c_BST6;
+						build_packet_state_S				<= c_BST6;
 						reg1_soda_pkt_valid_S			<= '0';
-					when c_BST6	=>
+					when c_BST6	=>
 						build_packet_bits_S				<= x"17";
-						build_packet_state_S				<= c_BST7;
+						build_packet_state_S				<= c_BST7;
 						reg1_soda_pkt_valid_S			<= '1';
-						soda_pkt_word_S					<= SUPER_BURST_NR_IN(7 downto 0);
+						soda_pkt_word_S					<= SUPER_BURST_NR_IN(7 downto 0);
 						EXPECTED_REPLY_OUT				<= SUPER_BURST_NR_IN(7 downto 0);
-					when c_BST7	=>
+					when c_BST7	=>
 						build_packet_bits_S				<= x"18";
-						build_packet_state_S				<= c_BST8;
+						build_packet_state_S				<= c_BST8;
 						soda_dlm_preview_S				<= '0';
 						reg1_soda_pkt_valid_S			<= '0';
-					when c_BST8	=>
-						if (soda_cmd_strobe_S='0') then
+					when c_BST8	=>
+						if (soda_cmd_strobe_S='0') then
 							soda_dlm_preview_S			<= '0';
 							build_packet_bits_S			<= x"00";
-							build_packet_state_S			<= c_IDLE;
-						else
+							build_packet_state_S			<= c_IDLE;
+						else
 							soda_dlm_preview_S			<= '1';
 							build_packet_bits_S			<= x"21";
-							build_packet_state_S			<= c_CMD1;
-						end if;
+							build_packet_state_S			<= c_CMD1;
+						end if;
 						reg1_soda_pkt_valid_S			<= '0';
 						soda_pkt_word_S					<= (others=>'0');
 					when c_WAIT4CYCLE_C	=>
@@ -301,146 +303,180 @@ begin
 							soda_dlm_preview_S			<= '0';
 							reg1_soda_pkt_valid_S		<= '0';
 							soda_pkt_word_S				<= '0' & soda_cmd_word_S(30 downto 24);
-						end if;
+						end if;
 --					when c_WAIT4CMD1	=>
 --						build_packet_state_S	<= c_CMD1;
 --						soda_dlm_preview_S	<= '1';
 --						soda_pkt_valid_S		<= '1';
 --						soda_pkt_word_S		<= '0' & soda_cmd_word_S(30 downto 24);
-					when c_CMD1	=>
+					when c_CMD1	=>
 						build_packet_bits_S				<= x"22";
-						build_packet_state_S				<= c_CMD2;
+						build_packet_state_S				<= c_CMD2;
 						soda_dlm_preview_S				<= '1';
 						reg1_soda_pkt_valid_S			<= '0';
 						SEND_TIME_CAL_OUT					<= soda_cmd_word_S(30);
-					when c_CMD2	=>
+					when c_CMD2	=>
 						build_packet_bits_S				<= x"23";
-						build_packet_state_S				<= c_CMD3;
+						build_packet_state_S				<= c_CMD3;
 						reg1_soda_pkt_valid_S			<= '1';
 						soda_pkt_word_S					<= soda_cmd_word_S(23 downto 16);
 						SEND_TIME_CAL_OUT					<= '0';
-					when c_CMD3	=>
+					when c_CMD3	=>
 						build_packet_bits_S				<= x"24";
-						build_packet_state_S				<= c_CMD4;
+						build_packet_state_S				<= c_CMD4;
 						reg1_soda_pkt_valid_S			<= '0';
-					when c_CMD4	=>
+					when c_CMD4	=>
 						build_packet_bits_S				<= x"25";
-						build_packet_state_S				<= c_CMD5;
+						build_packet_state_S				<= c_CMD5;
 						reg1_soda_pkt_valid_S			<= '1';
 						soda_pkt_word_S					<= soda_cmd_word_S(15 downto 8);
-					when c_CMD5	=>
+					when c_CMD5	=>
 						build_packet_bits_S				<= x"26";
-						build_packet_state_S				<= c_CMD6;
+						build_packet_state_S				<= c_CMD6;
 						reg1_soda_pkt_valid_S			<= '0';
-					when c_CMD6	=>
+						if (crc_valid_S = '0') then --PS 
+							build_packet_state_S			<= c_ERROR; --PS
+						else
+							PS_crc_out_S				<= crc_out_S; --PS
+						end if;
+					when c_CMD6	=>
 						build_packet_bits_S				<= x"27";
-						build_packet_state_S				<= c_CMD7;
+						build_packet_state_S				<= c_CMD7;
 						reg1_soda_pkt_valid_S			<= '1';
-						soda_pkt_word_S					<= soda_cmd_word_S(7 downto 0);
-						EXPECTED_REPLY_OUT				<= soda_cmd_word_S(7 downto 0);
-					when c_CMD7	=>
-						if (crc_valid_S = '0') then
+						soda_pkt_word_S					<= PS_crc_out_S; --PS: crc needed soda_cmd_word_S(7 downto 0);
+						EXPECTED_REPLY_OUT				<= PS_crc_out_S; --PS: crc needed soda_cmd_word_S(7 downto 0);
+					when c_CMD7	=>
+						if (crc_valid_S = '1') then  --PS
 						build_packet_bits_S				<= x"0E";
-							build_packet_state_S			<= c_ERROR;
+							build_packet_state_S			<= c_ERROR;
 						else
 							build_packet_bits_S			<= x"28";
-							build_packet_state_S			<= c_CMD8;
-						end if;
+							build_packet_state_S			<= c_CMD8;
+						end if;
 						soda_dlm_preview_S				<= '0';
 						reg1_soda_pkt_valid_S			<= '0';
 					when c_CMD8	=>
 						build_packet_bits_S				<= x"00";
-						build_packet_state_S				<= c_IDLE;
+						build_packet_state_S				<= c_IDLE;
 						soda_dlm_preview_S				<= '0';
 						reg1_soda_pkt_valid_S			<= '0';
 						soda_pkt_word_S					<= (others=>'0');
 					when c_ERROR	=>
 						build_packet_bits_S				<= x"00";
-						build_packet_state_S				<= c_IDLE;
+						build_packet_state_S				<= c_IDLE;
 						soda_dlm_preview_S				<= '0';
 						reg1_soda_pkt_valid_S			<= '0';
-					when others	=>
+					when others	=>
 						build_packet_bits_S				<= x"00";
-						build_packet_state_S				<= c_IDLE;
+						build_packet_state_S				<= c_IDLE;
 						soda_dlm_preview_S				<= '0';
 						reg1_soda_pkt_valid_S			<= '0';
-				end case;
-			end if;
-		end if;
-	end process;
-
---	soda_cmd_reg_proc : process(SODACLK)
---	begin
---		if rising_edge(SODACLK) then
---			if (RESET='1') then
---				soda_cmd_reg_full_S	<= '0';
---				soda_cmd_reg_S			<= (others => '0');
---			elsif (soda_pkt_valid_S = '1') then
+				end case;
+			end if;
+		end if;
+	end process;
+
+--	soda_cmd_reg_proc : process(SODACLK)
+--	begin
+--		if rising_edge(SODACLK) then
+--			if (RESET='1') then
+--				soda_cmd_reg_full_S	<= '0';
+--				soda_cmd_reg_S			<= (others => '0');
+--			elsif (soda_pkt_valid_S = '1') then
 --				soda_cmd_reg_full_S	<= '1';
 --				soda_cmd_reg_S			<= '0' & soda_cmd_word_S;
 --				
---			end if;
+--			end if;
 --		end if;
---	end process;
-
-
-	crc_gen_proc : process(SODACLK, build_packet_state_S)
-	begin
-		if rising_edge(SODACLK) then
-			case build_packet_state_S is
-					when c_IDLE	=>
-						crc_data_valid_S	<= '0';
-						crc_datain_S		<= (others=>'0');
-						soc_S					<= '1';
-						eoc_S					<= '0';
-					when c_CMD1	=>
-						crc_data_valid_S	<= '1';
-						crc_datain_S		<= '0' & soda_cmd_word_S(30 downto 24);
-						soc_S					<= '0';
-						eoc_S					<= '0';
-					when c_CMD2	=>
-						crc_data_valid_S	<= '0';
-						crc_datain_S		<= (others=>'0');
-						soc_S					<= '0';
-						eoc_S					<= '0';
-					when c_CMD3	=>
-						crc_data_valid_S	<= '1';
-						crc_datain_S		<= soda_cmd_word_S(23 downto 16);
-						soc_S					<= '0';
-						eoc_S					<= '0';
-					when c_CMD4	=>
-						crc_data_valid_S	<= '0';
-						crc_datain_S		<= (others=>'0');
-						soc_S					<= '0';
-						eoc_S					<= '0';
-					when c_CMD5	=>
-						crc_data_valid_S	<= '1';
-						crc_datain_S	<= soda_cmd_word_S(15 downto 8);
-						soc_S					<= '0';
-						eoc_S					<= '1';
-					when c_CMD6	=>
-						crc_data_valid_S	<= '0';
-						crc_datain_S		<= (others=>'0');
-						soc_S					<= '0';
-						eoc_S					<= '0';
-					when c_CMD7	=>
-						crc_data_valid_S	<= '0';
-						crc_datain_S		<= (others=>'0');
-						soc_S					<= '0';
-						eoc_S					<= '0';
-					when c_CMD8	=>
-						crc_data_valid_S	<= '0';
-						crc_datain_S		<= (others=>'0');
-						soc_S					<= '0';
-						eoc_S					<= '0';
-					when others	=>
-						crc_data_valid_S	<= '0';
-						crc_datain_S		<= (others=>'0');
-						soc_S					<= '0';
-						eoc_S					<= '0';
-			end case;		
-		end if;
-	end process;
-
+--	end process;
+
+
+-- -- PS : crc one clock earlier
+crc_data_valid_S <=
+	'1' when (((build_packet_state_S=c_WAIT4CYCLE_C) and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)))
+			or ((build_packet_state_S=c_BST8) and (soda_cmd_strobe_S='1'))
+			or ((build_packet_state_S=c_IDLE) and (START_OF_SUPERBURST='0') and (soda_cmd_strobe_S='1') and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H))))
+	else '1' when (build_packet_state_S=c_CMD2)
+	else '1' when (build_packet_state_S=c_CMD4)
+	else '0';
+
+crc_datain_S <= 
+	'0' & soda_cmd_word_S(30 downto 24) 
+		when (((build_packet_state_S=c_WAIT4CYCLE_C) and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)))
+			or ((build_packet_state_S=c_BST8) and (soda_cmd_strobe_S='1'))
+			or ((build_packet_state_S=c_IDLE) and (START_OF_SUPERBURST='0') and (soda_cmd_strobe_S='1') and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H))))
+	else soda_cmd_word_S(23 downto 16) when (build_packet_state_S=c_CMD2)
+	else soda_cmd_word_S(15 downto 8) when (build_packet_state_S=c_CMD4)
+	else (others => '0');
+
+soc_S <= 
+	'1' 
+		when (((build_packet_state_S=c_WAIT4CYCLE_C) and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H)))
+			or ((build_packet_state_S=c_BST8) and (soda_cmd_strobe_S='1'))
+			or ((build_packet_state_S=c_IDLE) and (START_OF_SUPERBURST='0') and (soda_cmd_strobe_S='1') and ((SODA_CYCLE_IN = '1') and (LINK_PHASE_IN = c_PHASE_H))))
+	else '0';
+								
+eoc_S <= '1' when (build_packet_state_S=c_CMD4) else '0';
+
+
+							
+	-- crc_gen_proc : process(SODACLK, build_packet_state_S)
+	-- begin
+		-- if rising_edge(SODACLK) then
+			-- case build_packet_state_S is
+					-- when c_IDLE	=>
+						-- crc_data_valid_S	<= '0';
+						-- crc_datain_S		<= (others=>'0');
+						-- soc_S					<= '1';
+						-- eoc_S					<= '0';
+					-- when c_CMD1	=>
+						-- crc_data_valid_S	<= '1';
+						-- crc_datain_S		<= '0' & soda_cmd_word_S(30 downto 24);
+						-- soc_S					<= '0';
+						-- eoc_S					<= '0';
+					-- when c_CMD2	=>
+						-- crc_data_valid_S	<= '0';
+						-- crc_datain_S		<= (others=>'0');
+						-- soc_S					<= '0';
+						-- eoc_S					<= '0';
+					-- when c_CMD3	=>
+						-- crc_data_valid_S	<= '1';
+						-- crc_datain_S		<= soda_cmd_word_S(23 downto 16);
+						-- soc_S					<= '0';
+						-- eoc_S					<= '0';
+					-- when c_CMD4	=>
+						-- crc_data_valid_S	<= '0';
+						-- crc_datain_S		<= (others=>'0');
+						-- soc_S					<= '0';
+						-- eoc_S					<= '0';
+					-- when c_CMD5	=>
+						-- crc_data_valid_S	<= '1';
+						-- crc_datain_S	<= soda_cmd_word_S(15 downto 8);
+						-- soc_S					<= '0';
+						-- eoc_S					<= '1';
+					-- when c_CMD6	=>
+						-- crc_data_valid_S	<= '0';
+						-- crc_datain_S		<= (others=>'0');
+						-- soc_S					<= '0';
+						-- eoc_S					<= '0';
+					-- when c_CMD7	=>
+						-- crc_data_valid_S	<= '0';
+						-- crc_datain_S		<= (others=>'0');
+						-- soc_S					<= '0';
+						-- eoc_S					<= '0';
+					-- when c_CMD8	=>
+						-- crc_data_valid_S	<= '0';
+						-- crc_datain_S		<= (others=>'0');
+						-- soc_S					<= '0';
+						-- eoc_S					<= '0';
+					-- when others	=>
+						-- crc_data_valid_S	<= '0';
+						-- crc_datain_S		<= (others=>'0');
+						-- soc_S					<= '0';
+						-- eoc_S					<= '0';
+			-- end case;		
+		-- end if;
+	-- end process;
+
 
 end architecture;
\ No newline at end of file
diff --git a/code/soda_packet_handler.vhd b/source/soda_packet_handler.vhd
similarity index 87%
rename from code/soda_packet_handler.vhd
rename to source/soda_packet_handler.vhd
index f294bf0..7bbc83f 100644
--- a/code/soda_packet_handler.vhd
+++ b/source/soda_packet_handler.vhd
@@ -5,10 +5,13 @@ use ieee.numeric_std.all;
 library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; 
+use work.trb_net16_hub_func.all; 
 use work.soda_components.all;
 
 entity soda_packet_handler is
+	generic(
+		CLOCKSper25ns					: integer := 5 -- PS
+	);
 	port(
 		SODACLK							: in	std_logic; -- fabric clock
 		RESET								: in	std_logic; -- synchronous reset
@@ -20,6 +23,7 @@ entity soda_packet_handler is
 		START_OF_CALIBRATION_OUT	: out std_logic	:= '0';
 		SODA_CMD_VALID_OUT			: out std_logic := '0';
 		SODA_CMD_WORD_OUT				: out std_logic_vector(30 downto 0) := (others => '0');
+		SODA_CYCLE_OUT				: out std_logic := '0'; -- PS
 		RX_DLM_IN						: in std_logic;
 		RX_DLM_WORD_IN					: in	std_logic_vector(7 downto 0) := (others => '0')
 	);
@@ -35,6 +39,7 @@ architecture Behavioral of soda_packet_handler is
 												c_SODA_PKT5, c_SODA_PKT6, c_SODA_PKT7, c_SODA_PKT8
 											);
 	signal	packet_state_S				:	packet_state_type := c_IDLE;
+	signal	SODA40MHz_counter_S			: integer range 0 to CLOCKSper25ns-1 := 0; -- PS
 
 begin
 
@@ -135,7 +140,7 @@ begin
 						START_OF_SUPERBURST_OUT				<= '0';
 						START_OF_CALIBRATION_OUT			<=	'0';
 						SODA_CMD_VALID_OUT					<= '0';
-						soda_pkt_word_S(31 downto 24)		<=	RX_DLM_WORD_IN;
+						soda_pkt_word_S(31 downto 24)		<=	RX_DLM_WORD_IN;
 					when c_SODA_PKT2	=>
 						-- do nothing -- disregard K28.7
 					when c_SODA_PKT3	=>
@@ -155,9 +160,9 @@ begin
 							SUPER_BURST_NR_OUT				<= soda_pkt_word_S(30 downto 0);
 						else
 							SODA_CMD_VALID_OUT				<= '1';
-							SODA_CMD_WORD_OUT					<= soda_pkt_word_S(30 downto 0);
-							if soda_pkt_word_S(30)='1' then
-								START_OF_CALIBRATION_OUT	<=	'1';
+							SODA_CMD_WORD_OUT					<= soda_pkt_word_S(30 downto 0);
+							if soda_pkt_word_S(30)='1' then
+								START_OF_CALIBRATION_OUT	<=	'1';
 							end if;
 						end if;
 					when others	=>
@@ -172,5 +177,25 @@ begin
 		end if;
 	end process;
 
+-- PS : 40MHz clock cycle, synchronized to SODA
+make_synchronous_40MHz_proc : process(SODACLK, packet_state_S)
+	begin
+		if rising_edge(SODACLK) then
+			if ((packet_state_S=c_RST) or (packet_state_S=c_IDLE)) and (RX_DLM_IN='1') then
+				SODA40MHz_counter_S <= 0;
+			else
+				if SODA40MHz_counter_S<CLOCKSper25ns-1 then
+					SODA40MHz_counter_S <= SODA40MHz_counter_S+1;
+				else
+					SODA40MHz_counter_S <= 0;
+				end if;
+			end if;
+			if SODA40MHz_counter_S=1 then 
+				SODA_CYCLE_OUT <= '1';
+			else
+				SODA_CYCLE_OUT <= '0';
+			end if;
+		end if;
+	end process;
 
 end architecture;
\ No newline at end of file
diff --git a/source/soda_reply_handler.vhd b/source/soda_reply_handler.vhd
new file mode 100644
index 0000000..e6a9d0e
--- /dev/null
+++ b/source/soda_reply_handler.vhd
@@ -0,0 +1,87 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb_net16_hub_func.all; 
+use work.soda_components.all;
+
+entity soda_reply_handler is
+	port(
+		SODACLK						: in	std_logic; -- fabric clock
+		RESET							: in	std_logic; -- synchronous reset
+		CLEAR							: in	std_logic; -- asynchronous reset
+		CLK_EN						: in	std_logic;
+		--Internal Connection
+		EXPECTED_REPLY_IN			: in	std_logic_vector(7 downto 0) := (others => '0');
+		RX_DLM_IN					: in	std_logic	:= '0';
+		RX_DLM_WORD_IN				: in	std_logic_vector(7 downto 0)	:= (others => '0');
+		REPLY_VALID_OUT			: out std_logic := '0';
+		REPLY_OK_OUT				: out std_logic := '0'
+	);
+end soda_reply_handler;
+
+architecture Behavioral of soda_reply_handler is
+
+	-- type		packet_state_type is (	c_RST, c_IDLE, c_ERROR,	c_REPLY, c_DONE);
+	-- signal	reply_recv_state_S				:	packet_state_type := c_IDLE;
+
+begin
+
+	reply_fsm_proc : process(SODACLK)
+	begin
+		if rising_edge(SODACLK) then
+			REPLY_VALID_OUT <= '0';
+			REPLY_OK_OUT <= '0';
+			if (RX_DLM_IN='1') then
+				REPLY_VALID_OUT <= '1';
+				if (EXPECTED_REPLY_IN = RX_DLM_WORD_IN) then
+					REPLY_OK_OUT <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+	
+	-- reply_fsm_proc : process(SODACLK)
+	-- begin
+		-- if rising_edge(SODACLK) then
+			-- if (RESET='1') then
+				-- REPLY_VALID_OUT					<= '0';
+				-- REPLY_OK_OUT						<= '0';
+				-- reply_recv_state_S				<= c_IDLE;
+			-- else
+				-- REPLY_VALID_OUT					<= '0';
+				-- case reply_recv_state_S is
+					-- when c_IDLE	=>
+						-- if (RX_DLM_IN='1') then
+							-- reply_recv_state_S	<= c_REPLY;
+							-- REPLY_VALID_OUT		<= '1';
+							-- if (EXPECTED_REPLY_IN = RX_DLM_WORD_IN) then
+								-- REPLY_OK_OUT		<= '1';
+							-- else
+								-- REPLY_OK_OUT		<= '0';
+							-- end if;
+						-- end if;
+					-- when c_REPLY =>
+						-- REPLY_VALID_OUT			<= '0';
+						-- REPLY_OK_OUT				<= '0';
+						-- if (RX_DLM_IN='0') then
+							-- reply_recv_state_S	<= c_IDLE;
+						-- else
+							-- reply_recv_state_S	<= c_ERROR;
+						-- end if;
+					-- when c_ERROR	=>
+						-- reply_recv_state_S		<= c_IDLE;
+						-- REPLY_OK_OUT				<= '0';
+						-- REPLY_OK_OUT				<= '0';
+					-- when others =>
+						-- reply_recv_state_S		<= c_IDLE;
+						-- REPLY_OK_OUT				<= '0';
+				-- end case;
+			-- end if;
+		-- end if;
+	-- end process;
+
+end architecture;
\ No newline at end of file
diff --git a/code/soda_reply_pkt_builder.vhd b/source/soda_reply_pkt_builder.vhd
similarity index 98%
rename from code/soda_reply_pkt_builder.vhd
rename to source/soda_reply_pkt_builder.vhd
index cbcacb7..72a4673 100644
--- a/code/soda_reply_pkt_builder.vhd
+++ b/source/soda_reply_pkt_builder.vhd
@@ -1,34 +1,34 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
-
+
 library work;
 use work.trb_net_std.all;
 use work.trb_net_components.all;
-use work.trb_net16_hub_func.all; 
+use work.trb_net16_hub_func.all; 
 use work.soda_components.all;
-
-entity soda_reply_pkt_builder is
-	port(
-		SODACLK						: in	std_logic; -- fabric clock
-		RESET							: in	std_logic; -- synchronous reset
-		CLEAR							: in	std_logic; -- asynchronous reset
-		CLK_EN						: in	std_logic; 
-		--Internal Connection
+
+entity soda_reply_pkt_builder is
+	port(
+		SODACLK						: in	std_logic; -- fabric clock
+		RESET							: in	std_logic; -- synchronous reset
+		CLEAR							: in	std_logic; -- asynchronous reset
+		CLK_EN						: in	std_logic; 
+		--Internal Connection
 		LINK_PHASE_IN				: in	std_logic := '0';	--_vector(1 downto 0) := (others => '0');
-		START_OF_SUPERBURST		: in	std_logic := '0';
-		SUPER_BURST_NR_IN			: in	std_logic_vector(30 downto 0) := (others => '0');
-		SODA_CMD_STROBE_IN		: in	std_logic := '0';	-- 
-		SODA_CMD_WORD_IN			: in	std_logic_vector(30 downto 0) := (others => '0');		--REGIO_CTRL_REG in trbnet handler is 32 bit
+		START_OF_SUPERBURST		: in	std_logic := '0';
+		SUPER_BURST_NR_IN			: in	std_logic_vector(30 downto 0) := (others => '0');
+		SODA_CMD_STROBE_IN		: in	std_logic := '0';	-- 
+		SODA_CMD_WORD_IN			: in	std_logic_vector(30 downto 0) := (others => '0');		--REGIO_CTRL_REG in trbnet handler is 32 bit
 		TX_DLM_PREVIEW_OUT		: out	std_logic := '0';	-- 
 		TX_DLM_OUT					: out	std_logic := '0';	-- 
-		TX_DLM_WORD_OUT			: out	std_logic_vector(7 downto 0) := (others => '0')
-	);
-end soda_reply_pkt_builder;
-
-architecture soda_reply_pkt_builder_arch of soda_reply_pkt_builder is
+		TX_DLM_WORD_OUT			: out	std_logic_vector(7 downto 0) := (others => '0')
+	);
+end soda_reply_pkt_builder;
+
+architecture soda_reply_pkt_builder_arch of soda_reply_pkt_builder is
 
 	type		reply_packet_state_type is	(	c_IDLE, c_ERROR,
 													c_WAIT4BST1, c_BST1, c_BST2, c_BST3, c_BST4, c_BST5, c_BST6, c_BST7, c_BST8,
@@ -36,35 +36,35 @@ architecture soda_reply_pkt_builder_arch of soda_reply_pkt_builder is
 												);
 	signal	reply_packet_state_S		: reply_packet_state_type := c_IDLE;
 	signal	reply_packet_bits_S		: std_logic_vector(7 downto 0)	:= (others => '0');
-
+
 	signal	soda_dlm_preview_S		: std_logic;
 	signal	sequence_error_S			: std_logic;
 	signal	next_superburst_nr_S		: std_logic_vector(30 downto 0);
-
-
-begin
+
+
+begin
 	
 --	TX_DLM_PREVIEW_OUT		<= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1'))) or
 --													((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1'))) 
 --													else '0';
 	TX_DLM_PREVIEW_OUT		<= soda_dlm_preview_S;
-
+
 sequence_check_proc : process(SODACLK)
 	begin
 		if rising_edge(SODACLK) then
-			if (RESET='1') then
-				sequence_error_S		<= '0';
-				next_superburst_nr_S	<= (others => '0');
-			else
+			if (RESET='1') then
+				sequence_error_S		<= '0';
+				next_superburst_nr_S	<= (others => '0');
+			else
 				case reply_packet_state_S is
 					when c_IDLE	=>
 						if (START_OF_SUPERBURST='1') then
-							if (SUPER_BURST_NR_IN=next_superburst_nr_S) then
+							if (SUPER_BURST_NR_IN=next_superburst_nr_S) then
 								sequence_error_S		<= '0';
-							else
+							else
 								sequence_error_S		<= '1';
-							end if;
-						end  if;
+							end if;
+						end  if;
 --					when c_BST1 =>
 --						sequence_error_S		<= '0';
 --						next_superburst_nr_S	<= SUPER_BURST_NR_IN + 1;
@@ -73,14 +73,14 @@ sequence_check_proc : process(SODACLK)
 						next_superburst_nr_S	<= SUPER_BURST_NR_IN + 1;
 					when others =>
 				end case;
-			end if;
-		end if;
-	end process;
-
+			end if;
+		end if;
+	end process;
+
 reply_fsm_proc : process(SODACLK)
 	begin
 		if rising_edge(SODACLK) then
-			if (RESET='1') then
+			if (RESET='1') then
 				reply_packet_bits_S	<= x"00";
 				reply_packet_state_S	<= c_IDLE;
 				soda_dlm_preview_S	<= '0';
@@ -89,7 +89,7 @@ reply_fsm_proc : process(SODACLK)
 			else
 				case reply_packet_state_S is
 					when c_IDLE	=>
-						if (START_OF_SUPERBURST='1') then
+						if (START_OF_SUPERBURST='1') then
 							soda_dlm_preview_S	<= '1';
 							if (LINK_PHASE_IN = c_PHASE_H) then
 								reply_packet_bits_S	<= x"11";
@@ -111,7 +111,7 @@ reply_fsm_proc : process(SODACLK)
 							else
 								reply_packet_bits_S	<= x"20";
 								reply_packet_state_S	<= c_WAIT4CMD1;
-								TX_DLM_OUT				<= '0';
+								TX_DLM_OUT				<= '0';
 							end if;
 						end if;
 					when c_WAIT4BST1	=>
@@ -124,7 +124,7 @@ reply_fsm_proc : process(SODACLK)
 						reply_packet_bits_S			<= x"12";
 						reply_packet_state_S			<= c_BST2;
 						TX_DLM_OUT						<= '0';
-						soda_dlm_preview_S			<= '0';
+						soda_dlm_preview_S			<= '0';
 					when c_BST2 =>
 						reply_packet_bits_S			<= x"00";
 						reply_packet_state_S			<= c_IDLE;
@@ -142,7 +142,7 @@ reply_fsm_proc : process(SODACLK)
 					when c_CMD2 =>
 						reply_packet_bits_S			<= x"00";
 						reply_packet_state_S			<= c_IDLE;
-					when others =>
+					when others =>
 						reply_packet_bits_S			<= x"00";
 						reply_packet_state_S			<= c_IDLE;
 						TX_DLM_OUT						<= '0';
@@ -150,6 +150,6 @@ reply_fsm_proc : process(SODACLK)
 				end case;
 			end if;
 		end if;
-	end process;
-
+	end process;
+
 end soda_reply_pkt_builder_arch;
\ No newline at end of file
diff --git a/code/soda_source.vhd b/source/soda_source.vhd
similarity index 95%
rename from code/soda_source.vhd
rename to source/soda_source.vhd
index ae227fb..cd86999 100644
--- a/code/soda_source.vhd
+++ b/source/soda_source.vhd
@@ -14,14 +14,14 @@ entity soda_source is
 		SYSCLK					: in	std_logic; -- fabric clock
 		SODACLK					: in	std_logic; -- clock for data to serdes
 		RESET						: in	std_logic; -- synchronous reset
-
+
 		SODA_BURST_PULSE_IN	: in	std_logic := '0';	-- 
 		SODA_CYCLE_IN			: in	std_logic := '0';	-- 
 
 		RX_DLM_WORD_IN			: in	std_logic_vector(7 downto 0) := (others => '0');
 		RX_DLM_IN				: in	std_logic;
 		TX_DLM_OUT				: out	std_logic;
-		TX_DLM_WORD_OUT		: out	std_logic_vector(7 downto 0) := (others => '0');
+		TX_DLM_WORD_OUT		: out	std_logic_vector(7 downto 0) := (others => '0');
 		TX_DLM_PREVIEW_OUT	: out	std_logic	:= '0';	--PL!
 		LINK_PHASE_IN			: in	std_logic	:= '0';	--PL!
 
@@ -74,19 +74,21 @@ architecture Behavioral of soda_source is
 	signal calib_data_valid_S			: std_logic;
 	signal calibration_time_s			: std_logic_vector(15 downto 0)	:= (others => '0');
 	signal calib_register_s				: std_logic_vector(31 downto 0)	:= (others => '0');
---	signal calib_register_rst_s		: std_logic	:= '0';	-- read of calibration register resets contents to 0
+--	signal calib_register_rst_s		: std_logic	:= '0';	-- read of calibration register resets contents to 0
 	signal reply_timeout_error_S		: std_logic;
 	signal channel_timeout_status_S	: std_logic;
 	signal downstream_error_S			: std_logic;
 	signal report_error_S				: std_logic;
-
+
 	signal dead_channel_S				: std_logic;
 	signal soda_reset_S					: std_logic;
 	signal soda_enable_S					: std_logic;
 
+-- PS synchronize calib_data_valid_S
+	signal calib_data_valid_SYSCLK_S	: std_logic;
+
+begin
 
-begin
-
 	superburst_gen :  soda_superburst_generator
 		generic map(BURST_COUNT		=> 16)
 		port map(
@@ -95,7 +97,7 @@ begin
 			ENABLE						=>	soda_enable_S,
 			SODA_BURST_PULSE_IN		=>	SODA_BURST_PULSE_IN,
 			START_OF_SUPERBURST_OUT	=>	start_of_superburst_S,
-			SUPER_BURST_NR_OUT		=>	super_burst_nr_S,
+			SUPER_BURST_NR_OUT		=>	super_burst_nr_S,
 			SODA_CMD_WINDOW_OUT		=> soda_cmd_window_S
 		);
 
@@ -106,13 +108,13 @@ begin
 			--Internal Connection
 			LINK_PHASE_IN				=>	LINK_PHASE_IN,		--link_phase_S,	PL!
 			SODA_CYCLE_IN				=> SODA_CYCLE_IN,
-			SODA_CMD_WINDOW_IN		=> soda_cmd_window_S,
+			SODA_CMD_WINDOW_IN		=> soda_cmd_window_S,
 			SODA_CMD_STROBE_IN		=> soda_cmd_strobe_sodaclk_S,		--soda_send_cmd_S, goes with removal of SODA_CMD_FLOWCTRL
 			START_OF_SUPERBURST		=> start_of_superburst_S,
 			SUPER_BURST_NR_IN			=> super_burst_nr_S,
 			SODA_CMD_WORD_IN			=> soda_cmd_word_S,
 			EXPECTED_REPLY_OUT		=> expected_reply_S,
-			SEND_TIME_CAL_OUT			=>	start_calibration_S,
+			SEND_TIME_CAL_OUT			=>	start_calibration_S,
 			TX_DLM_PREVIEW_OUT		=>	TX_DLM_PREVIEW_OUT,
 			TX_DLM_OUT					=> TX_DLM_OUT,
 			TX_DLM_WORD_OUT			=> TX_DLM_WORD_OUT
@@ -142,42 +144,53 @@ begin
 			START_CALIBRATION			=>	start_calibration_S,
 			END_CALIBRATION			=>	reply_data_valid_S,
 			VALID_OUT					=>	calib_data_valid_S,
-			CALIB_TIME_OUT				=>	calibration_time_S,
+			CALIB_TIME_OUT				=>	calibration_time_S,
 			TIMEOUT_ERROR				=>	reply_timeout_error_S	-- timeout because no reply was received
 		);
+
+	--PS: synchronize calib_data_valid_S (not very important: calibration time is internal in FPGA)
+	calib_data_valid_posedge_to_pulse: posedge_to_pulse 
+	port map(
+		IN_CLK		=> SODACLK,
+		OUT_CLK		=> SYSCLK,
+		CLK_EN		=> '1',
+		SIGNAL_IN	=> calib_data_valid_S,
+		PULSE_OUT	=> calib_data_valid_SYSCLK_S
+	);
+
 		
 	sodasource_calib_timeout_proc  : process(SYSCLK)	-- converting to sysclk domain
 	begin
 		if rising_edge(SYSCLK) then
 			if( RESET = '1' ) then
-				calib_register_S								<= (others => '0');
+				calib_register_S								<= (others => '0');
 				channel_timeout_status_S 					<= '0';
 				downstream_error_S							<= '0';
 				channel_timeout_status_S					<= '0';
 				report_error_S									<= '0';
-			elsif (calib_data_valid_S = '1') then					-- calibration finished in time
-				calib_register_S(15 downto 0)				<= calibration_time_S;
+			elsif (calib_data_valid_SYSCLK_S = '1') then					-- calibration finished in time
+				calib_register_S(15 downto 0)				<= calibration_time_S;
 				channel_timeout_status_S 					<= '0';
 			elsif (reply_data_valid_S = '1') then							-- the reply was correct
-				channel_timeout_status_S 					<= '0';
-				if (reply_OK_S = '1') then
-					downstream_error_S						<= '0';
-				elsif (dead_channel_S = '0') then
-					downstream_error_S						<= '1';
+				channel_timeout_status_S 					<= '0';
+				if (reply_OK_S = '1') then
+					downstream_error_S						<= '0';
+				elsif (dead_channel_S = '0') then
+					downstream_error_S						<= '1';
 					report_error_S								<= '1';			-- set REPORT_ERROR status-bit
 				end if;
 			elsif ((reply_timeout_error_S = '1') and  (reply_OK_S = '1')) then
 				channel_timeout_status_S 					<= '1';
 				downstream_error_S							<= '1';			-- set CALIBRATION_TIMEOUT_ERROR status-bit
-				report_error_S									<= '1';			-- set REPORT_ERROR status-bit
-			elsif (report_error_S = '1') then		-- check if slowcontrol wants to reset errors
+				report_error_S									<= '1';			-- set REPORT_ERROR status-bit
+			elsif (report_error_S = '1') then		-- check if slowcontrol wants to reset errors
 				channel_timeout_status_S 					<= '0';
 				downstream_error_S							<= '0';			-- set CALIBRATION_TIMEOUT_ERROR status-bit
 				report_error_S									<= '0';			-- set REPORT_ERROR status-bit
 			end if;
 		end if;
 	end process;
-
+
 ---------------------------------------------------------
 -- RegIO Statemachine
 ---------------------------------------------------------
@@ -251,8 +264,8 @@ soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse
 		SIGNAL_IN	=> soda_cmd_strobe_S,
 		PULSE_OUT	=> soda_cmd_strobe_sodaclk_S
 	);
-
-
+
+
 ---------------------------------------------------------
 -- Control bits                                        --
 ---------------------------------------------------------
@@ -266,7 +279,7 @@ soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse
 	CTRL_STATUS_register_S(14 downto 2)	<= (others => '0');
 	CTRL_STATUS_register_S(1)				<= downstream_error_S;
 	CTRL_STATUS_register_S(0)				<= channel_timeout_status_S;
-
+
 ---------------------------------------------------------
 -- data handling                                       --
 ---------------------------------------------------------
@@ -290,7 +303,7 @@ soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse
 			end if;
 		end if;
 	end process THE_WRITE_REG_PROC;
-
+
 
 -- register read
 	THE_READ_REG_PROC: process( SYSCLK )
@@ -315,4 +328,5 @@ soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse
 	SODA_DATA_OUT	<= buf_bus_data_out;
 	SODA_ACK_OUT 	<= bus_ack;
 
+
 end architecture;
diff --git a/code/soda_start_of_burst_control.vhd b/source/soda_start_of_burst_control.vhd
similarity index 99%
rename from code/soda_start_of_burst_control.vhd
rename to source/soda_start_of_burst_control.vhd
index 8baee2b..0e82525 100644
--- a/code/soda_start_of_burst_control.vhd
+++ b/source/soda_start_of_burst_control.vhd
@@ -43,7 +43,7 @@ begin
 				burst_counter_S			<= cCYCLES_PER_BURST;
 				SODA_40MHZ_CYCLE_OUT		<= '0';
 				SODA_BURST_PULSE_OUT		<= '0';
-			elsif (cycle_counter_S=0) then
+			elsif (cycle_counter_S=0) then
 				cycle_counter_S			<= cCLOCKS_PER_CYCLE;
 				SODA_40MHZ_CYCLE_OUT		<= '1';
 				if (burst_counter_S=0) then
@@ -52,8 +52,8 @@ begin
 				else
 					burst_counter_S		<= burst_counter_S - 1;
 					SODA_BURST_PULSE_OUT	<= '0';
-				end if;
-			else
+				end if;
+			else
 				cycle_counter_S			<= cycle_counter_S - 1;
 				SODA_40MHZ_CYCLE_OUT		<= '0';
 			end if;
diff --git a/code/soda_superburst_gen.vhd b/source/soda_superburst_gen.vhd
similarity index 100%
rename from code/soda_superburst_gen.vhd
rename to source/soda_superburst_gen.vhd
diff --git a/trb3_soda_client.xcf b/trb3_soda_client.xcf
deleted file mode 100644
index 7316181..0000000
--- a/trb3_soda_client.xcf
+++ /dev/null
@@ -1,227 +0,0 @@
-<?xml version='1.0' encoding='utf-8' ?>
-<!DOCTYPE		ispXCF	SYSTEM	"IspXCF.dtd" >
-<ispXCF version="2.1.0">
-	<Comment></Comment>
-	<Chain>
-		<Comm>JTAG</Comm>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>1</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_central_gbe_20130626.bit</File>
-			<FileTime>09/24/13 10:52:51</FileTime>
-			<Operation>Bypass</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>SVF Processor</SVFProcessor>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="TRUE"/>
-			<Pos>2</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140827.bit</File>
-			<FileTime>08/27/14 11:21:53</FileTime>
-			<Operation>Fast Program</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>3</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/home/gsi/bitfiles/trb3_periph_sodasource_20130903.bit</File>
-			<FileTime>09/03/13 16:32:30</FileTime>
-			<JedecChecksum>N/A</JedecChecksum>
-			<Operation>Bypass</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>4</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/home/gsi/bitfiles/trb3_periph_sodasource_20130408.bit</File>
-			<FileTime>04/10/13 14:12:21</FileTime>
-			<JedecChecksum>N/A</JedecChecksum>
-			<Operation>Bypass</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="TRUE"/>
-			<Pos>5</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140827.bit</File>
-			<FileTime>08/27/14 09:49:24</FileTime>
-			<Operation>Fast Program</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>SVF Processor</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="TRUE"/>
-			<Pos>6</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>ispCLOCK</Family>
-			<Name>ispPAC-CLK5410D</Name>
-			<IDCode>0x00190043</IDCode>
-			<Package>64-pin QFNS</Package>
-			<PON>ispPAC-CLK5410D-XXSN64C</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed</File>
-			<FileTime>04/10/13 09:35:41</FileTime>
-			<JedecChecksum>0x1C57</JedecChecksum>
-			<Operation>Erase,Program,Verify</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>32</PreloadLength>
-				<IOVectorData>0x00000000</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0xFFFFFFFF</Usercode>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>7</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>ispCLOCK</Family>
-			<Name>ispPAC-CLK5410D</Name>
-			<IDCode>0x00190043</IDCode>
-			<Package>64-pin QFNS</Package>
-			<PON>ispPAC-CLK5410D-XXSN64C</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<Operation>Bypass</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>32</PreloadLength>
-				<IOVectorData>0x00000000</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-	</Chain>
-	<ProjectOptions>
-		<Program>SEQUENTIAL</Program>
-		<Process>ENTIRED CHAIN</Process>
-		<OperationOverride>No Override</OperationOverride>
-		<StartTAP>TLR</StartTAP>
-		<EndTAP>TLR</EndTAP>
-		<VerifyUsercode value="FALSE"/>
-	</ProjectOptions>
-	<CableOptions>
-		<CableName>USB</CableName>
-		<PortAdd>EzUSB-0</PortAdd>
-	</CableOptions>
-</ispXCF>
diff --git a/trb3_soda_dual_client.xcf b/trb3_soda_dual_client.xcf
deleted file mode 100644
index 2c45894..0000000
--- a/trb3_soda_dual_client.xcf
+++ /dev/null
@@ -1,222 +0,0 @@
-<?xml version='1.0' encoding='utf-8' ?>
-<!DOCTYPE		ispXCF	SYSTEM	"IspXCF.dtd" >
-<ispXCF version="3.3.0">
-	<Comment></Comment>
-	<Chain>
-		<Comm>JTAG</Comm>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>1</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<Operation>Fast Program</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="TRUE"/>
-			<Pos>2</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20141204.bit</File>
-			<FileTime>12/04/14 15:43:18</FileTime>
-			<Operation>Fast Program</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>3</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<Operation>Fast Program</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="TRUE"/>
-			<Pos>4</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20141204.bit</File>
-			<FileTime>12/04/14 15:43:18</FileTime>
-			<JedecChecksum>N/A</JedecChecksum>
-			<Operation>Fast Program</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="TRUE"/>
-			<Pos>5</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_periphEP_soda_quad_source_20141203.bit</File>
-			<FileTime>12/03/14 10:10:40</FileTime>
-			<Operation>Fast Program</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="TRUE"/>
-			<Pos>6</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>ispCLOCK</Family>
-			<Name>ispPAC-CLK5410D</Name>
-			<IDCode>0x00190043</IDCode>
-			<Package>64-pin QFNS</Package>
-			<PON>ispPAC-CLK5410D-XXSN64C</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed</File>
-			<FileTime>04/10/13 09:35:41</FileTime>
-			<JedecChecksum>0x1C57</JedecChecksum>
-			<Operation>Erase,Program,Verify</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>32</PreloadLength>
-				<IOVectorData>0x00000000</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0xFFFFFFFF</Usercode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>7</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>ispCLOCK</Family>
-			<Name>ispPAC-CLK5410D</Name>
-			<IDCode>0x00190043</IDCode>
-			<Package>64-pin QFNS</Package>
-			<PON>ispPAC-CLK5410D-XXSN64C</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/trb3/base/clockmanager/CM2.jed</File>
-			<FileTime>04/10/13 09:35:41</FileTime>
-			<JedecChecksum>0x18FB</JedecChecksum>
-			<Operation>Erase,Program,Verify</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>32</PreloadLength>
-				<IOVectorData>0x00000000</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0xFFFFFFFF</Usercode>
-			</Option>
-		</Device>
-	</Chain>
-	<ProjectOptions>
-		<Program>SEQUENTIAL</Program>
-		<Process>ENTIRED CHAIN</Process>
-		<OperationOverride>No Override</OperationOverride>
-		<StartTAP>TLR</StartTAP>
-		<EndTAP>TLR</EndTAP>
-		<VerifyUsercode value="FALSE"/>
-	</ProjectOptions>
-	<CableOptions>
-		<CableName>USB</CableName>
-		<PortAdd>EzUSB-0</PortAdd>
-		<JTAGPinSetting>
-			TRST	ABSENT;
-			ISPEN	ABSENT;
-		</JTAGPinSetting>
-	</CableOptions>
-</ispXCF>
diff --git a/trb3_soda_source.xcf b/trb3_soda_source.xcf
deleted file mode 100644
index 5e6f4c4..0000000
--- a/trb3_soda_source.xcf
+++ /dev/null
@@ -1,227 +0,0 @@
-<?xml version='1.0' encoding='utf-8' ?>
-<!DOCTYPE		ispXCF	SYSTEM	"IspXCF.dtd" >
-<ispXCF version="3.4.0">
-	<Comment></Comment>
-	<Chain>
-		<Comm>JTAG</Comm>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>1</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_central_gbe_20130626.bit</File>
-			<FileTime>09/24/13 10:52:51</FileTime>
-			<Operation>Bypass</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>SVF Processor</SVFProcessor>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="TRUE"/>
-			<Pos>2</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20150317.bit</File>
-			<FileTime>03/17/15 13:31:23</FileTime>
-			<Operation>Fast Program</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>3</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/home/gsi/bitfiles/trb3_periph_sodasource_20130903.bit</File>
-			<FileTime>09/03/13 16:32:30</FileTime>
-			<JedecChecksum>N/A</JedecChecksum>
-			<Operation>Bypass</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>4</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/home/gsi/bitfiles/trb3_periph_sodasource_20130408.bit</File>
-			<FileTime>04/10/13 14:12:21</FileTime>
-			<JedecChecksum>N/A</JedecChecksum>
-			<Operation>Bypass</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="TRUE"/>
-			<Pos>5</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>LatticeECP3</Family>
-			<Name>LFE3-150EA</Name>
-			<IDCode>0x01015043</IDCode>
-			<Package>All</Package>
-			<PON>LFE3-150EA</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20150319.bit</File>
-			<FileTime>03/19/15 08:09:52</FileTime>
-			<JedecChecksum>N/A</JedecChecksum>
-			<Operation>Fast Program</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>1326</PreloadLength>
-				<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>SVF Processor</SVFProcessor>
-				<Usercode>0x00000000</Usercode>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="TRUE"/>
-			<Pos>6</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>ispCLOCK</Family>
-			<Name>ispPAC-CLK5410D</Name>
-			<IDCode>0x00190043</IDCode>
-			<Package>64-pin QFNS</Package>
-			<PON>ispPAC-CLK5410D-XXSN64C</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<File>/local/lemmens/lattice/trb3/base/clockmanager/CM1_125twice.jed</File>
-			<FileTime>04/10/13 09:35:41</FileTime>
-			<JedecChecksum>0x1C57</JedecChecksum>
-			<Operation>Erase,Program,Verify</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>32</PreloadLength>
-				<IOVectorData>0x00000000</IOVectorData>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>SVF Processor</SVFProcessor>
-				<Usercode>0xFFFFFFFF</Usercode>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-		<Device>
-			<SelectedProg value="FALSE"/>
-			<Pos>7</Pos>
-			<Vendor>Lattice</Vendor>
-			<Family>ispCLOCK</Family>
-			<Name>ispPAC-CLK5410D</Name>
-			<IDCode>0x00190043</IDCode>
-			<Package>64-pin QFNS</Package>
-			<PON>ispPAC-CLK5410D-XXSN64C</PON>
-			<Bypass>
-				<InstrLen>8</InstrLen>
-				<InstrVal>11111111</InstrVal>
-				<BScanLen>1</BScanLen>
-				<BScanVal>0</BScanVal>
-			</Bypass>
-			<Operation>Bypass</Operation>
-			<Option>
-				<SVFVendor>JTAG STANDARD</SVFVendor>
-				<IOState>HighZ</IOState>
-				<PreloadLength>32</PreloadLength>
-				<IOVectorData>0x00000000</IOVectorData>
-				<OverideUES value="TRUE"/>
-				<TCKFrequency>1.000000 MHz</TCKFrequency>
-				<SVFProcessor>ispVM</SVFProcessor>
-				<AccessMode>JTAG</AccessMode>
-			</Option>
-		</Device>
-	</Chain>
-	<ProjectOptions>
-		<Program>SEQUENTIAL</Program>
-		<Process>ENTIRED CHAIN</Process>
-		<OperationOverride>No Override</OperationOverride>
-		<StartTAP>TLR</StartTAP>
-		<EndTAP>TLR</EndTAP>
-		<VerifyUsercode value="FALSE"/>
-	</ProjectOptions>
-	<CableOptions>
-		<CableName>USB</CableName>
-		<PortAdd>EzUSB-0</PortAdd>
-	</CableOptions>
-</ispXCF>